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AFIPS
CONFERENCE
PROCEEDINGS
VOLUME 33
PART TWO
1968
FALL JOINT
COMPUTER
CONFERENCE
December 9-11, 1968
San Francisco, California
The ideas and opinions expressed herein are solely those of the authors and are
not necessarily representative of or endorsed by the· 1968 Fall Joint Computer
Conference Committee or the American Federation of Information Processing
Societies.
Library of Congress Catalog Card Number 55-44701
THOMPSON BOOK COMPANY
National Press Building
Washington, D.C. 20004
© 1968 by the American Federation of Information Processing Societies, N ew York,
New York, 10017. All rights reserved. This book, or parts thereof, may not be
reproduced in any form without permission of the publisher.
Printed in the United States of America
CONTENTS
PART II
PROGRAMMING SYSTEMS II
WRITEACOURSE: An educational programming language. .. . . . . . . . .
923
A table driven compiler for use with automatic test equipment. . . . . . . .
929
On the basis for ELF: An extensible language facility.. . . . . . . . . . . . . . . .
937
MEMORY TECHNIQUES-HERE TODAY
Associative processing for general purpose computers through the use
of modified memories .......................................... .
Addressing patterns and memory handling algorithms ..
949
957
i
•••••••••••••
E. Hunt,
M. Zosel
R. L. Mattison,
R. T. Mitchell
T. E. Cheatham,
A. Fisher,
P. Jorrand
H. Stone
S. Sisson,
M. Flynn
T. lshidate
Design of a 100-nanosecond read cycle NDRO plated wire memory .....
High speed, high cur~ent word matrix using charge storage diodes for
rail selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
981
S. Waaben,
P. Carmody
AUTOMATED MAINTENANCE AND CHECKOUT OF HYBRID
SIMULATION FACILITIES
Automatic Checkout of a large hybrid computing system ............ .
Hybrid diagnostic techniques. . . . . . . . . . . . . . . . . . . . . . . . . . ........... .
987
997
J. C. Richards
T. K. Seehuus,
W. M aasberg,
W. A. Harmon
DYNAMIC RESOURCE ALLOCATION
Demand paging in perspective. . . . . . . . . . . . . . . . . . . . . . . . . ........... .
1011
Program behavior in a paging enviromnent ......................... .
1019
JANUS: A flexible approach to real-time time-sharing ............... .
1033
A parallel process definition and control system. . . . . . . . . . ........... .
1043
969
B. Randell,
C. Kuehner
B. Brawn,
F. Gustavson
J. Kopj,
P. Plauger
D. Cohen
HUMAN AUGMENTATION THROUGH COMPUTERS AND
TELEOPERATORS (A Panel Session-No papers included in
this volume)
LA;BORATORY AUTOMATION
A computer system for automation of the analytical laboratory ....... ,
Real-time time-sharing, the desirability and economics. . . . . . . . . . . . .
1051
1061
P. J. Friedl,
C. H. Sederholm,
T. R. Lusebrink
B. E. F. M acefield
A modular on-line computer system for data acquisition and
experimental control ....... '.' ........................... , , . ' . . ..
1065
A standardised data highway for on-line computer applications ....... ,
1077
~
1089
Use of a computer in a molecular biology laboratory ..... ' ...........
A small computer as an on-line multiparameter analyzer for a neutron
spectrometer ................ , .. , ................ , . . . . . . . . . . . .. '1099
H. P. Lie,
R. W. Kerr,
G. L. Miller,
D. A. H. Robinson
I. N. Hooton,
R. C.,M. Barnes
J. F. W. Mallett,
T. H. G088li,ftg
1'v.l. G. Silk,
S. B. Wright
Applications of digital computers to the long term measurement of
blood pressure and the management of patients in intensive care
situations ...... , , . , ......... , .. , .................. , ...... , . . . .
1105
J. L. Corbett
HAND PRINTED CHARACTER RECOGNITION
Some conclusions on the use of adaptive linear decision functions .. , . , ,
1117
E. R. Ide,
C. E. Kiessling,
C. J. Tunis
Experiments in the recognition of hand-printed text: Part I-Character
recognition................. , . , .. , .', ........... , ............... . 1125
Experiments in the reoognition of hand printed text Part II-Context
analysis ..... , ............ , ............. , .......... , ....... ' .. . 1139
The design of an OCR system for reading handwritten numerals .. , . , ..
1151
OPERATING SYSTEMS I/OPERATING SYSTEMS II
The dynamic behavior of programs ... , ................ , , . , . , ... ' , , , 1163
Resource allocation with interlock dete~tion in a multi-task system. , . , , 1169
Cage dual processing ... , ... , , , ... , ..... ' . '.... , ........... , . , . , , , . 1177
An operating system for a central real-time data processing
computer ....... , .............................. , ............. . 1187
J. H.
1~funson
R. O. Duda,
P. E. Hart
P. J. Hurley,
W. S. Rohland,
P. J. Traglia
I. F. Freibergs
J. E. Murphy
K. C. Smith
P. Day,
H. Krejci
~EW
MEMORY TECHNIQUES
Holographic read -only memories accessed by light-emitting diodes ..... .
Semiconductor memory circuits and technology .... , , , , , , , ... , ' , , , , "
2Yr-D Core search memory ............ ' ................. , . . . . . ..
1197
1205
1213
Design of a small multi-turn magnetic thin film memory. ' , .... , ...... 1219
D.H.R. Vilkomerson,
R. S. 1\1[ezrich,
D. I. Bostwick
W. B. Sander
}\I[. W. Rolund,
P. A. Harding
W. Simpson
HYBRID SIlVIULATION TECHNIQUES
An adaptive sampling system for hybrid computation ........ , ... ' , ..
1225
G. A. Hahe,
lV. Karplus
A new solid state electronic iterative differential analyzer making
maximum use of integrated circuits ............................. '.
1233
B. K. Conant
A general method for programming synchronous logic in analog
computation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
APPLICATIONS OF COMPUTERS TO PROBLEMS OF THE
ATMOSPHERE AND GEOPHYSICS
Computer experiInents in the global circulation of the earth's
atmosphere. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Computational problems encountered in the study of the earth's
normal modes ............................................... ".
1251
R. A. Moran,
E. G. Gilbert
1259
A. Kasa;.hara
1273
F. Gilbert,
G. Backus
PROGRESS IN DISPLAYS (A Panel Session-No papers in this volume)
COMPUTER GENERATED PICTURES-PERILS, PLEASURES,
PROFITS
Computer animation and the fourth dimension ..................... .
Computer displays in the teaching of physics ....................... .
1279
1285
Art, computers and mathematics .................................. .
1292
CAMP-Computer assisted movie production ...................... .
1299
What good is a baby? ........................................... .
1307
A computer animation movie language ............................. .
1317
NEW TRENDS IN PROGRAMMING LANGUAGES
CABAL-Environmental design of a compiler-compiler .............. . 1321
Cage test language-An interpretive language designed for aerospace .. . 1329
An efficient system for user extendible languages .................... . 1339
Program composition and editing with an on· line display ............. . 1349
BULK MEMORY DEVICES
New horizons for magnetic bulk storage devices ..................... .
Laser recording unit for high density permanent digital data storage ... .
1361
1369
A magnetic random access terabit magnetic memory ................ .
1381
A. 1ll. Noll
J. L. Schwartz,
E. E. Taylor
C. Csuri,
J. Shaffer
J. WhitneY,
J. Citron
N. W ink less ,
P. Honore
D. Weiner,
S. E. Anderson
R. K. Dove
G. S. Metsker
M. C. Newey
H. Bratrnan,
H. G. Martin,
E. C. Perstein
F. D. Risko
K. McFarland,
M. H ashiguchi
S. Damron,
J. Miller,
E. Salbu,
M. Wildman,
J. Lucas
Diagnostics and recovery programs for the IBM 1360 photo-digital
storage system ................................................ .
1389
D. P. Gustlin,
D. D. Prentice
SIMULATION IN THE DESIGN AND EVALUATION OF DIGITAL
COMPUTER SYSTEMS
. Simulation design ofa multiprocessing system. . . . . . . . . . . . . . . . . . . . . ..
1399
R. A. Merikallio,
F. a.Holland
A simulation study of resource management in a time-sharing system ...
1411
Performance of a simulated multiprogramming system ............... .
1431
THE COMPUTER FIELD: WHAT WAS PROMISED, WHAT WE
HAVE, WHAT WE NEED (HARDWARE SESSION)
Hardware design reflecting software requirements. . . . . .............. .
What was promised, what we have and what is being promised in
character recognition .......................................... .
High speed logic and memory: Past, present and future .............. .
S. L. Rehmann,
S. G. Gangwere, Jr.
M. M. Lehman,
J. L. Rosenfeld
1443
S. Rosen
1451
1459
A. W. Holt
A. W.Lo
REAL-TIME INFORMATION SYSTEMS AND THE PUBLIC
INTEREST
Real-time systems and public information .......................... .
National and international information networks in science and
technology ................................................... .
Real-time computer communications and the public interest .......... .
1467
C. W. Churchman
1469
1473
Toward education in real-time .................................... .
A public philosophy for real-time information systems. _ ............ .
1479
1491
H. Borko
1\!1 • M. Gold,
L. L. Selwyn
P. E. Rosove
H. Sackman
COMPUTER DESIGN AUTOlVIATION: WHAT NOW AND WHAT
NEXT?
Introduction ................................................... .
Functional design and evaluation ................................. .
Interface between logic and hardware .............................. .
Hardware implementation ........................................ .
Hardware fault detection ........................................ .
1499
1500
1501
1502
1502
J. M. K urtzberg
D. F. Gorman
R. L. Russo
W. E. Donath
M. A. Breuer
WRITEACOURSE:
An educational programming language*
by EARL HUNT and MARY ZOSEL
University of Washington
Seattle, Washington
The problem
equipment suitable for his use. This alternative
is extremely expensive (the equipment alone would
rent for $100,000 a year or better) and is feasible
only for large research projects. He could hire a computer programmer and tell him what the computer was
supposed to do. This introduces another speci9li5t
into the research team, and has the disadvantage
that the computer will then act as the programmer
thought the educator wanted it to act. The educator
may not discover a misunderstanding until after it has
been built into the programming system, at which point
it is hard to fix.
We advocate another alternative, placing in the general purpose computing system a language which is easy
for the educator to use. This is the solution which was
taken over ten years ago by mathematicians, when they
were faced with the prospect of writing mathematics in a
language which was designed for machine execution,
rather than for problem statement. The great success of
languages such as FORTRAN and ALGOL testifies to
the feasibility of the approach. In the next ten years an
educator's language may also be needed.
What should the characteristics of such a language
be? By far the most important requirement is that the
language should be natural for the teacher. Its syntax
and semantics should conform to his writing habits.
Insofar as possible, and there are limits on this , the form
of the language should not be determined by the physical characteristics of the computer on which it will be
used.
Readability is a second requirement, It will often be
necessary for a person to understand a program he did
not write. The structure of the programming language
should be such that the basic plan of a program can be
communicated without forcing the reader to master the
intricacies of each line of code.
A judicious choice of a language can also ensure the
Computer applications in education are becoming
more ~nd more prevalent. Perhaps the most talked
about use of computers in the schools is to control the
educational material presented to students ... the Computer Assisted Instruction (CAl) application. CAl requires that two problems be solved. Someone has to decide what material should be sent to a student, and
when, and someone has to arrange that the computer
actually do what is desired. The first problem, what
should be done, is a topic for educators and psychologists. Our concern is with the second. How can we make
CAl a convenient tool for the educator?
We will assume that the educator has access to an
int~ractive system, but that system was not specifically
desIgned for computer assisted instruction. Once the
educator has determined the form of a lesson he would
~ike to ?e able to go to the typewriter, t;pe in the
InstructIOns, and then leave the typewriter knowing
when he returns with a student, the computer will be
prepared to conduct the lesson. The problem is that the
computer "understands" instructions only in a very restricted set of languages. The form of these languages
has, for the most part, been dictated either by the internal design of the machine or by the requirements of
mathematicians and statisticians who are, after all, the
largest group of users of general purpose computers.
The language problem can be solved in several ways.
The educator could, himself, become proficient in computer pro~ramming. This diverts his timefrom the problem he wIshes to pursue. He could acquire a specially
designed computing system which had languages and
*This research was supported by the- Air .Force Office of Scientific Research, Office of Aerospace Research, United States Air
F~rce., ~der AFOSR Grant No. AF-AFOSR-l:3U-67.
DIstrIbutIOn of this document is unlimited.
923
924
Fall Joint Computer Conference, 1968
----------~-----------------------------------------------------------------------
availability of a computer. Any language which is not
tied to the physical characteristics of a computer requires a translator. Pragmatically speaking, then, the
language is defined by the translator program. Thus
the educational language can be "inherited" by any
machine for which its base language translator exists.
Weare by no means the first to recognize the need for
an educator's language. Several others have already
been developed. The best known are probably IBM's
COURSEWRITER5 and System Development Corporation's PLANIT.2 These languages are admirably
suited for the particular computer configurations for
which they were developed. For a variety of reasons,
however, we believe that they fail to meet the criteria
we have listed. Our principal criticism is that they
either are too much influenced by the way a computer
wishes to receive commands, instead of the way a person
wishes to give them, or that they contain features which,
although quite useful in themselves, would not be available except in specially designed computing systems.
The WRITEACOURSE Language.
We have developed an educational language, called
WRITEACOURSE, which is consciously modeled after
the ALGOL arithmetic programming language, 7 which it
resembles in its syntactic structure. The basic unit of
discourse is the statement, corresponding roughly to an
English sentence. Statements are grouped into larger
units called lessons, and lessons into courses, similar to
the way a group of subroutines make up a program.
Statements are composed of instructions. In WRITEACOURSE there are only ten instructions. Physically,
they are English words, such as ADD and PRINT,
which have been chosen to have a meaning as closeas
possible to their meaning in the natural language.
Limiting the commands of the language restricts us.
There are actions which can be executed by a computer,
but which are difficult to express in a restricted idiom.
The initial users of WRITEACOURSE have not found
this to be a great problem. They appear to be able to
say almost everything they want to say without extensive training.
The WRITEACOURSE translation program has been
written entirely in the PLII programming language,6
which we expect to be widely available in a few years.
We assume that the particular configuration has an
interactive computing capability, in which the user can
exchange messages with a program from a remote station equipped with a typewriter or other keyboard device. By 1970 this sort of capability should be common
in universities, at a price well within the reach of a
modest research budget.
An earlier version of WRITEACOURSE4 was defined for the Burroughs B5500 computer only, using the
extended ALGOL provided for that machine. 1 Thus the
early version was not machine independent in the sense
that our present program is, although it would be a
fairly straightforward task to adopt it to some other
computer which had an ALGOL compiler.
Our approach should produce an easily maintained
system. This is a very important point. Undoubtedly
there will be errors in any system as complicated as a
programming language. Also, different users will want to
extend the language to suit their own purpose. Since the
translation program is written in a commonly available,
user oriented language, the educator wil1 find that there
are many people who can understand and alter it. This
will be particularly true in universities, where Computer Science departments and computer centers will
regularly offer undergraduate courses in PLII programming.
A user's view of the language.
The purpose of developing WRITEACOURSE was
to have a language which could be easily understood by
educators. We can test this now by presenting a fragment of a WRITEACOURSE lesson. Hopefully it will
be readable with only a minimal explanation.
The following statements are taken from a fragment of a WRITEACOURSE lesson. They appear
exactly as they would be typed by an instructor, with
the exception of the numbers in parentheses at the beginning of each line. These have been introduced for
ease of reference in explaining the lesson.
(1) 20 PRINT "THE ANGLE OF INCIDENCE IS
EQUAL TO THE ANGLE OF ... "
(2)
ACCEPT CHECK "REFLECTION" "REFRACTION" IF 1 CHECKS THEN GO TO 51
(3)
IF 2 CHECKS THEN PRINT "NO, THE
ANGLE OF REFRACTION DEPENDS ON
(4)
THE TYPE OF LENS"I
(5)
PRINT "TRY AGAIN" ACCEPT CHECK
REFLECTION" IF 0 CHECKS THEN
(6)
PRINT "THE CORRECT ANSWER IS REFLECTION"I
(7) 5 PRINT "HERE IS THE NEXT QUESTION"I
What would happen when a student executed this
lesson? The first statement (statement 20) to be exe- .
cuted is the statement beginning on line (1) and extending to the end of statement marker("I") on line (2).
Statements always begin on a new line; otherwise, they
may be typed in any way convenient. Line (1) would
print the question THE ANGLE OF INCIDENCE IS
EQUAL TO THE ANGLE OF ... on the computer-'
controlled typewriter. At line (2) the ACCEPT in:"
struction would print an underscore ("_") on the next
line. This would be a signal to the student indicating
WRITEACOURSE
that an answer was expected. At this point the paper
in front of the student would look like this
THE ANGLE OF INCIDENCE IS EQUAL TO
THE ANGLE OF ...
The computer would then wait for the student, who
would type whatever he thought was an appropriate reply, then strike the carriage return key of the typewriter,
indicating that he was through with his answer. The
program would ACCEPT this answer, and CHECK it
against indicated possible answers. Suppose the student
had typed
REFRACTION
The CHECK command on line (2) would match this
answer against the quoted statements "REFLECTION" and" REFRACTION." The quoted statem en1 s
are called check strings. In this case the answer would
be identical to the second check string, so we say that
"2 CHECKS." At line (2), however, the question asked
is, "DOES 1 CHECK?" This would only be true if the
student had replied REFLECTION (the correct answer), in which case control would have been transferred
to the statement named 5, at line (7) of the lesson,
which continues with ~ new question.
However, 1 did not check, so the next commands to be
executed are those on line (3), which begins a new, unnamed statement.S Lines (3) and (4) are straightforward.
The computer asks if 2 CHECKS, which it does, since
the student's reply was identical to the second check
string.6 Upon determining this, the computer types out
the correcting response given on lines (3) and (4).
Next the statement begiIming on line (5) is executed.
This prints another line, urging the student to try
again, and an underscore (the ACCEPT of line (5))
teHing him an answer is expected. The student will now
have in front of him
THE ANGLE OF INCIDENCE IS EQUAL TO
THE ANGLE OF ... REFRACTION
NO, THE ANGLE OF REFRACTION DEPENDS
ON THE TYPE OF LENS
TRY AGAIN
Assume that he replies correctly, printing REFLECTION. This will be read by the ACCEPT statement in
line (5) and the immediately following CHECK statement will determine that 1 CHECKS is true. IF 0
CHECKS tests to see if nothing checked, i.e., 0
CHECKS is true if the student's answer does not match
any of the check stIings. In this case, the condition 0
CHECKS would be true fOl 2.ny answer other than
REFLECTION. Looking at the final three lines of the
conversation, we have
925
TRY AGAIN
REFLECTION
HERE IS THE NEXT QUESTION
But suppose that the student had not been so bright.
The final lines could have read
TRY AGAIN
WHO KNOWS?
THE CORRECT ANSWER IS REFLECTION
HERE IS ,THE NEXT QUESTION
M ore sophisticated programming
The example just given was very simple. Using the
computer's capabilities more fully, WRITEACOURSE
makes possible the specification of a much more complex branching sequence. There is also a limited arithmetical capability. A set of counters (temporary variables) are provided to keep track of intermediate results. Counters can be used either to do arithmetic or to
record the number of times a student takes a particular path through a course. This turns out to be a powerful device. We will give a few examples. 'I
Counters are named by preceding a number with the
symbol "@." Thus @10 means "counter 10." Three
commands are defined for counters, SET (counter ,number) TO (value), ADD (value) TO (counter number,
and SUBTRACT (value) FROM (counter number).
They have the obvious meaning.
SET@10toO
establishes 0 as the value of counter 10, while
ADD5TO@10
sets the value of counter 10 to 5 plus its original value.
It takes little imagination to see that the counters can
be used to keep scores on a student's responses, through
the device exemplified by
IF 1 CHECKS THEN ADD 1 TO @7.
The value of a counter may also be printed. To do this
the name of the counter is included in a PRINT command. When the command is executed, its current value
will be printed. The statement
SET @8 TO 5 PRINT "THE VALUE OF 8 IS@8"
will print
THE VALUE OF 8 IS 5.
The content of a counter is a value, so arithmetic can
be done on counters. ADP @2 TO @3 would set the
value of counter 3 to the original value ()f counter 2
plus the value of counter 3.
There are actually three groups of counters. Counters
926
Fall Joint Computer Conference, 1968
50-99 are lesson counters, their values are carried over
from one use of a WRITEACQURSE lesson to another.
There are several reasons for doing this. For instance, a
counter can be used to keep track of the number of students executing a lesson, or the number of students who
miss a particular question. Counters 1 to 49 are the
temporary counters. They are set to zero when a student
first signs in for a session with the computer. They are
retained for that student, however, for the duration of
the session even if he switches WRITEACOURSE lessons. Finally, Counter 0 is a special counter set by the
computer's internal clock. It can be used to time a student's responses.
A set of Boolean IF statements are provided to check
the value of a counter against another counter, or some
constant value. The command IF @4 = 7 THEN GO
TO 6 will cause a transfer to statement 6 only if counter
4 contains 7. The' normal arithmetical relations of
equality and ordered inequality are permitted.
Counter numbers may also be used for a computed
GO TO. GO TO @2 is an instruction to go to the statement whose number is contained in counter 2. Of
course, the instructor who writes this command must
insure that counter 2 will contain the name of a statement whenever this command is executed.
Let us look at an example which uses some of these
more complex commands.
SET @54, @41 TO 0 PRINT "WHAT DISCOVERY
(2)
LEAD TO LASERS?" I
(3) 3 ACCEPT CHECK "MASER" "QUASER"
(4)
"CANDLES" IF 1 CHECKS THEN GO TO 61
(5)
ADD 1 TO @41 IF 0 CHECKS THEN GO TO
401
(6)
IF 2 CHECKS THEN PRINT "THAT IS IN
ASTRON01VIY."
(7)
GOT040 I
(8)
IF 3 CHECKS THEN PRINT "DO NOT BE
SILLY." I
(9) 40 IF @41 < 3 THEN PRINT "TRY AGAIN"
GOT031
(10)
ADD 1 TO @54 PRINT "THE ANSWER IS
MASER." I
(11) 6 PRINT "HERE IS THE NEXT QUESTION"I
(1)
the following exchange might take place between the
student and computer.
WHAT DISCOVERY LEAD TO LASERS?
SUASER
THAT IS IN ASTRONOMY.
TRY AGAIN
MASER
HERE IS THE NEXT QUESTION.
The first statement sets counters .54 and 41 to zero,
then prints the basic question. Statement number 3
through statement number 40 establish a loop, which
checks the student's answer for the correct answer or
two anticipated wrong answers, prints an appropriate
message for a wrong answer, then gives the student
another chance. If the correct answer is detected (if 1
CHECKS in line (4)), the loop is broken by a transfer to
statement 6. If a wrong answer is detected, the question
is reasked. Counter 41 is used to keep track of the nunlber of wrong answers. If three wrong answers are given,
the correct answer is printed, and the program continues on. If this alternative occurs, howeve~, the value
of counter 54 is incremented by l. Recall that counter
54 is one of the lesson counters, i.e., its value carries
over from one user of the lesson to another. At some
later time, then, an instructor could interrogate the lesson to see how many students had failed to answer this
question in three or fewer tries.
Lessons and courses
Statements are grouped into lessons, and lessons into
courses. Roughly, a lesson can be thought of as the number of WRITEACOURSE statements needed to carry
on the computer's part of a computer-student interaction lasting about half an hour. Another important
functional distinction is that a lesson is the WRITEACOURSE unit to which counters are attached. Thus if
@54 appears in two different statements in the same
lesson, it refers to the same counter. If the two statements arein different lessons, they refer to different counters. Note that this is not true for temporary counters,
since they remain attached to a student for the duration
a student-computer conversation. Thus if it is anticipated that a student will use more than one lesson during a' single session, the results accumulated while the
first lesson is active may be communicated to the second
lesson via the temporary counters.
Lessons themselves are grouped into courses. Functionally, the chief distinction of a course is that it is possible to activate one lesson from within another, providing that the two lessons are in the same course. Suppose a student signs in, with the intention of taking a
course in Romance Literature. He would begin by indicating that he wanted to work on the first lesson of this
course. He would do this by replying, in response to a
computer question, that he wished to work on LE8SONI/LIT 47. LIT47 is assumed to be a course name,
and LESSON 1 a lesson of the course. Let us suppose
that this lesson is going to discuss the novel Don Quijote.
The instructor might want to check to make sure the
student knew enough Spanish to understand some of
phrases. This can be accomplished by the following
statement.
WRITEACOURSE
(1)
(2)
1 PRINT "DO YOU WISH TO REVIEW
SPANISH?"
ACCEPT CHECK "YES" IF 1 CHECKS
THEN CALL SPREVUE/LIT471
If the last command Qn the secQnd line is activated, it
will suspend the current lesson nQW active (LESSONI/
LIT47), and IQad the lessQn SPREVUE/LIT47. BQth
lessQns must be in the same CQurse. U PQn cQmpletiQn Qf
SPREVUE/LIT47, cQntrQI WQuid be returned to' the
statement' in LESSONl/LIT47 immediately after
line (2).
The cQmmand LINK (lessQn name) / (cQurse name)
will alsO' change a student frQm Qne lessQn to' anQther
within the same CQurse. In this case, hQwever, there is
nO' autQmatic return to' the calling lessQn after the called
lessQn is cQmpleted. The nQrmal use Qf LINK is to'
string tQgether several lessQns which the instructQr
wishes to' have executed in sequence.
Using WRITEACOURSE
The steps in using WRITEACOURSEwill nQW be
described. The steps a student must gO' thrQugh to' initiate a lessQn have been kept to' a minimum. He types
XEQ and then supplies the lessQn name and CQurse
name when requested. After a lessQn is Qver, he may
type XEQ and gO' thrQugh anQther lessQn, Qr type
STOP to' terminate the sessiQn.
When an instructQr CQnstructs a lessQn, the prQcess
is necessarily mQre involved. After calling the system
the instructQr sends the message / / / COMPILE indicating a CQurse is to' be established ar mQdified. (In
general, the symbQls "// /" precede cQmpiler CQmmands.) If a new CQurse is to' be written, the Qrder is
sent.
/ / /PROGRAM NEW lessQn/ CQurse
The translatQr will then be ready to' accept the lessQn.
Each statement is checked fQr syntax errQrs as it is
received. If there is nO' errQr, the next statement is requested. Whenever an errQr is detected, a message is
printed indicating where it Qccurred. After determining
the cQrrected fQrm, the instructQr re-enters the statement, frQm the PQint Qf the errQr to' the end. When the
instructQr wishes to' stQP wQrking Qn the lessQn, he types
/ / /END. ThelessQn will be autQmatically stQred in the
cQmputing system's files. If the mstructQr desires, he
may Qrder a check fQr undefined statement numbers referenced by GO TO instructiQns befQre the lessQn is recQrded.
The instructQr may mQdify existing lessQns Qr Qbtain
a listing Qf lessQns, using the cQmmands / / / ADD,
/ / /DELETE and / / /LIST.
927
System implementation.
WRITEACOURSE has been tested Qn an IBM
360/50 with a remQte 2741 terminal. The translatQr
was written in the RUSH4 subset Qf PL/I, pravided by
Allen-BabcQck CQmputing (8). The Qnly nQn-standard
PL/I used is the timer functiQn. WRITEACOURSE
lessQns are incrementally cQmpiled intO' a decimal integer cQde, which is stQred in a data file. The stQrage file
fQr each CQurse cQnsists Qf 64 tracks 0' ~ fixed fQrmat data
with a black size Qf 252 bytes. The internal cO' de is
edited whenever a teacher makes a mQdificatiQn. The
executiQn prQgram interprets this cQde to' praduce the
sequence O'f events planned by the instructQr. The first
blQck Qf cade in a caurse cO'ntains the names and IQcatiQns Qf the lessO'ns in it. Each lessQn O'ccupies 38 blQcks
O'f the file, and is divided intO' five parts.
1. The instructiQn table, which cO'ntains the cQmpiled
decimal cQde with apprQximately Qne cO'de wQrd
fO'r each instructiQn in the lessO'n.
2. The statement number table, which cQntains the
statement numbers with a PQinter to' the cO'rresPQnding instructiQns.
3. The CQunters attached to' the lessO'n.
4. The print tables, which cQntain all O'f the strings
to' be printed.
5. The print table index, which cO'ntains a PQinter t ')
the IO'catiO'n O'f each string.
Since the source cQde is nQt saved, the cQmpiled cQde
must be used whenever the lessQn is changed. TO' Qbtain
a listing Qf the lessQn, the cQde is interpreted, as if it
were to' be executed, and the SQurce cO'de is reCQnstructed. When a sectiQn O'f a lessQn is deleted, the instructiQn table and the statement number table are
clQsed up to' eliminate the desired PQrtiQn. The strings
in the print tables are marked inactive, fO'r later garbage
cQllectiQn. CQde is added to' a lessQn by apening a hO'le
in the instructiQn table and statement number table O'f
the prQper length, and then inserting the cQmpiled cQde.
New print strings are added to' the end Qf the print
tables.
A PQinter is kept in each table to' indicate the last
entry in the table, sO' that new cQde can be added to' the
end Qf a lessQn. SO'urce cO' de is input to' the cQmpiler Qne
statement at a time. The cQmpiler analyzes the statement instructiQn by instructiQn. If it detects any errQrs
it requests that the user re-input the statement frO'm the
instructiO'n cQntaining the errQr to' the end.
WRITEACOURSE is brO'ken intO' several prQgrams
in Qrder to' fit within the limited cQmputer space available in a time-shared system. The prO'grams Qperate as
Qverlay segments, with PL/I external variables used to'
cQmmunicate between them. The mQdular structure Qf
928
Fall Joint Computer Conference, 1968
WRITEACOURSE should facilitate system additions
or modifications. Figure 1 shows the basic overlay structure. The functions of each program are indicated in
the figure.
BIHOR
(CQfpUaUon MONitor
(Uecution M031tor)
Handle file
S.t up 1•••01\11 for
operatiol\ll
_ecutlon
and lesson
aDd haDdle
f11e operat101\11
1IIOdlflcaUona
I
I
CCllPIL
IDCUT
Accept les.on
Interpret the
statements from user
Internal code and
handle .tudent
cheek .yntax. and
produce Internal codl
FIGURE 1
Statu8
The earlier ALGOL version of WRITEACOURSEhas
been successfully used by people with little programming experience. Although the current version, at the
time of this writing, has not yet been put into general
use, the programming is completed. A limited number
of manuals describing the language details and use of
the system are available from the Department of
Psychology (Cognitive Capabilities Project), the
University of Washington. Listings of the translator
and manuals will be provided up()n request and at cost.
REFERENCES
Burroughs B5500 information processing systems extended Algol
language manual
Burroughs Corporation 1966
2 S L FEINGOLD C H FRYE
U8er's guide to PLANIT
System Development Corporation 1966
3 J FELDMAN DGRIES
Translator writing systems
Comm ACM Vol 11 Feb 1968
4 S HENDRICKSON E HUNT
The WRITEACOURSE language programming manual
Department of Psychology University of Washington 1967
5 IBM 1500 operating system computer-assisted instruction
coursewriter II
Form CAl-4036-1 IBM
6 IBM operating system/360 PL/I: language specifications
Form 028-6571-2 IBM 1966
7 P NAUR (Editor)
Revised report on the algorithmic language Algol 60
Comm ACM Vol 6 pp 1-17 Jan 1963
8 RUSH terminal user's manual
Allen-Babcock Computing Inc 1966
FOOTNOTES
1. This research was supported by the Air Force Office of
Scientific Research, Office of Aerospace Research, United
States Air Force, under AFOSR Grant No. AF-AFOSR1311-67. Distribution of this document is unlimited.
2. We 'wish to express our thanks to Sidney Hendrickson for
his comments and work on an earlier version of the language.
3. There is an unfortunate ambiguity in the word "program",
since it is used by educators to mean a sequence of interchanges
between student and teacher, and by computer scientists to
mean the sequence of commands issued to a computer. We shall
use "lesson" when we mean "sequence of educational steps"
and "program" when we mean "sequence of commands to
be executed by a digital computer."
4. At this point the mind of people not familiar with modern
computer technology tends to swim. It is possible to carry
this process even further (3).
5. The statement had to end at line (2) because of the IF ..
THEN command. The general rule is that when a question of
the form IF condition THEN is asked, the commands between
the word THEN and the next I are executed only if the condition
is true. If it is false, as it is in this case, the command immediately following the I, i.e., the first command of the next statement,
is executed.
6. More complicated matches are possible, which do not require exact identity. For instance, it is possible to ask if a
check string is included anywhere in an answer, so that, in
this case 2 would check if the answer had been IT IS REFRACTION.
7. A manual describing the language in detail is available.
A table driven complier for use with automatic test
equipment
hy ROLAND L. MATTISON and ROBERT T. MITCHELL
Radio Corporation of America
Burlington, Massachusetts
INTRODUCTION
When generating compilers for use with automatic test equipment (ATE), a substantial need
arises for flexibility in both the source and object
languages. Flexibility is desirable for two reasons: (1) The field of ATE construction is rapidly
expanding1 and (2) the hardware and support
software design, development, and debug cycles
are often going on simultaneously. In earlier, more
standard compilers, the modifications and/or extensions of either language could easily create
chaos for the systems prQgrammer.
In an attempt tQ facilitate compiler implementation and growth, a table driven system, the Universal Test Equipment Compiler (UTEC), has
been developed. As in other table driven systems ,2 the function of defining a source language
.
has been dissociated from the actual translatIon
mechanism. The source language is specified to
the generator whic~ creates a set of tables for subsequent use by the translator. A dual-purpose
meta-language has been created for use in the
system. This language is used tQ specify the syntax of a particular source language and the meaning to be imparted to the variQus allQwable constructs 'Of that language.
A typical ATE system cQnsists of various prQgrammable devices for applying stimuli to, and
'Obtaining measurements from, the unit under test
(UUT).1,3
A requirement peculiar to ATE compilers is the
creation of a wire list specifying connections between the ATE and the UUT. An equipment
designator has been included in the system tQ
handle the wire list and to insure that the wire
list remains fixed despite source program recom-
pilations. This is necessary due tQ the CQst incurred in the production of this wiring.
The wide range of computers currently used in
ATE dictates that the output 'Of UTEC be a symbolically addressed code which must then proceed
thrQugh the second pass 'Of a normal two pass assembler. Since this reduced assembler CQuid be
different for each type of ATE, it will be excluded
from the following discussiQn.
The flQW of information through the UTEC sys·
tem is depicted in Figure 1. The source language
specifications and translation IQgic are defined to
UTEC using the meta-language and are fed intQ
the generator. From this, the generatQr produces
translation tables for use by the translator. The
generator also accepts the .ATE hardware CQnfiguratiQn and produces equipment tables fQr the
equipment designatQr. When a source program is
input to UTEC for translation, the translator uses
the translation tables and outputs an intermediate
code ready fQr assembly. Whenever ATE equip-
.----------,
I
EQUIPMENT !PECIFICATION
LANGUAGE &EFINITION
GEN
EQUIPMENT TABLES
TRANSLATION TABLES
L _________ -.lI
I
ENGINEER'S TEST PROGRAM
ASSEt.4BLER
4---~
~~~!PER
..
MACHINE CODE
TAPE, CARDS, MAG. TAPE)
FIGURE I-System flow block diagram
929
930
Fall Joint Computer Conference, 1968
ment must be specified by the translator, it inserts
a symbolic into the intermediate code, and requests
the required equipment from an available equipment pool in the equipment tables. The request is
tied to the intermediate code by the symbolic. The
equipment designator now processes the equipment requests and, using the equipment tables,
produces equipment assignments for each symbolic
in the form of a symbol table.
The META-language
We now present a language, SYNSEM, (SYNtax and SEMantics) for explicitly defining a problem oriented language (POL).4 SYNSEM itself
is a twofold problem oriented language which (1)
specifies the syntax of the POL's and (,2) specifies
the semantics of the allowable constructs in a
POL. SYNSEM is therefore divided into two sublanguages: SYN for specifying syntax, and SEM
for specifying semantics.
Problem oriented languages currently in use
with ATE are tabular in format. The reason for
this, and examples of such languages have been
previously presented,5,7 and, therefore, will not
be considered here. Let it suffice to say that fixed
fields are generally adhered to, with one field set
aside for the function or verb and the remaining
fields for modifiers of various types. Each verbmodifier complex is referred to as a source statement.
The goal of SYN is to allow format-syntax type
information to be specified for each verb of the
POL. This information is encoded into a table by
the generator and will be used by the translator
whenever the verb is used in a source program.
SYN is comprised of various disjoint subsets of
any commonly used character set. Three of the
subsets are given below:
NU~\IBERS = {A, B, C, D, E, F, G, H, I, ~1, N, O,}
LETTERS
= {p, Q, R, U, V, W, y}
:VIAIN UNITS = {K}
To specify a numeric modifier, a letter is chosen
from NUMBERS and repeated so that the number
of times the letter appears equals the maximum
number of digits the modifier may contain. Alphabetic modifiers are handled in a similar way by
choosing from LETTERS.
If desired, a MAIN UNITS modifier may be
used with any verb. When the letter K is recog-
nized by the generator, the 4 characters immediately following the K are taken as the MAIN
UNITS and entered into a dictionary with the
verb. MAIN UNITS are used to further distinguish the verb when more than one source
statement uses the same verb.
As an example, consider the following SYN
statement to specify the verb CONNECT with the
modifier VDC:
CONNECT AAA KVDC
BBB
PPPP
The modifiers may be 2 numeric (A and B), 1
alphabetic (P), and the MAIN UNITS for this
form of CONNECT is VDC.
Once SYN has been used to specify a given verb,
a SEM"program" is written, later to be executed
by the translator, which analyzes the verb-modifier relationship and generates the desired intermediate code for the source statement. The SEM
language is composed of a number of semantic instructions, some of which are described below. A
maximum of 750 such instructions can be used
in anyone SEM program. A statement in SEM
consists of a semantic instruction followed by its
possible modifiers. A three digit label is optional
for all statements. A three digit branch is required with some instructions and optional with
others. If a branch is given on optional instructions, it is considered unconditional. The SEM
instructions are divided into three categories: (1)
Code producing, (2) Modifier handling and (3)· .
Control.
COD·E, CV AR, CALPHA, and CSIGN are four
·of the code generating instructions. CODE tells
the translator to output the characters which are
literally specified with the CODE instruction.
CODE
3
PSl
will cause the three characters "PSI" to appear
in the intermediate code. CVAR, CSIGN, and
CALPHA each are used with an identifier which
the translator references to find the data to be
output. The identifiers with CVAR and CSIGN
must be numeric.
CSIGN
NUMl
will generate a
NUMl
CVAR
+
NUMl
or - depending on the sign of
4
2
will cause the value of NUMl to be coded using
Table Driven CQmputer
fQur characters with tWQ implied decimal places.
If NUM1==46.913, the characters 4691 will be
cQded.
CALPHA
WI
3
will cause the three leftmQst characters .of WI
tQ be cQded.
TEST, RANGE, and the four arithmetic QperatQrs ADD, SUB, MUL, and DIV are SQme .of the
mQdifier handling SEM instructiQns. TEST causes
the translatQr tQ compare a referenced quantity
with a grQUp .of characters specified fQllQwing the
instructiQn. RANGE causes a check .of a referenced quantity tQ see if it is numerically between
tWQ limits. ExecutiQn .of either a TEST .or RANGE
instructiQn by the translatQr can cause a branch
in prQgram flow tQ a labeled SEM statement if the
cQmparisQn fails.
TEST
A
3 AMP
40
causes a cQmparisQn .of the three leftmQst characters .of A with the three characters AMP.
RANGE
B
20.0
30.0
40
causes a CQmparisQn .of B to see if 20.0 ~B:s;; 30.0.
If the abQve cQmparisQns are satisfied. the translatQrexecutes the next sequential instructiQn:
.otherwise, statement 40 will be prQcessed next.
JUMP, SCWL, ROUTINE and EQUI are each
SEM cQntrQI instructiQns. JUMP is used with a
SEM statement label and causes an uncQnditiQnal
transfer by the translatQr tQ the labeled statement. SCWL infQrms the translatQr that all .of the
intermediate cQde generated fQr a particular
SQurce statement must be saved with a label fQr
future use. The SEM language is prQvided with
a subrQutine capability thrQugh the ROUTINE instructiQn. ROUTINE may be fQllQwed by a parameter list .of frQm .one tQ seven ·dummy parameters. The CALL instructiQn, fQllowed by the
actual parameters, is used tQ invQke a SEM subrQutine. The EQUI instructiQn is used tQ cause
the translatQr tQ generate a symbQlic equipment
request fQr the equipment designatQr. Its mQdifiers must be a unique symbQlic, which will be
placed in the intermediate cQde by the ECODE
jnstructiQn, a type number referencing a particular pOQI .of equipment, and a set .of "cQnnectiQns"
tQ which a specific piece .of equipment frQm that
PQQI shQuld be wired.
A cQntrQI card called REQUIRED· is. used between the tWQ parts .of the SYNSEM language
931
and lists all required mQdifiers in the SYN portiQn.
The fQllQwing example shQWS the cQmbined use
of the SYN and SEM languages tQ specify the
verb CONNECT mQdified by VDC.
CONNECT
REQUIRED
NEWN
CODE
RANGE
EQUI
ECODE
CVAR
10 RANGE
EQUI
ECODE
CVAR
20 CODE
30 ERROR
40 E~D
AAAA
AC
UN1
1
A
5
UN1
A
A
6
UN1
A
2
A
KVDC
JC
JD
0
UN1
50
C
D
4
51
UN1
2
120
C
5
2
S
10
20
30
D
40
ES
OUT OF RANGE
The abQve prQgram is suitable fQr input tQ the
generatQr which WQuld create the necessary table
entries fQr later use by the translatQr after it sees
the CONNECT VDC verb in a source prQgram.
For example, supPQse the statement
CONNECT
4.2
VDC
JI-4
J3-5
was prQcessed by the translator. The cQde prQduced by the previQus definitiQn WQuid be
S ;00005 ;0420ES
'--"
EQUIPMENT
SYMBOLIC
which would cause the ATE tQ cQnnect 4.2 VQlts
.of direct current between PQints JI-4 and J3-5.
The equipment symbQlic number. 00005 was prQduced by the SEM instructiQn NEWN.
In a compiler fQr use with ATE, there is another function .of the meta-language, other than
defining source statement syntax and semantics.
It is to specify equipment available in any ATE
configuration. This is done in UTEC by the two
instructions, SYMBOL and DATA.
All equipment is divided into types, e.g., power
supplies, signal generators, v.oltmeters, and each
type is given a number to identify it. One SYMBOL instruction and as many DATA instructiQns
as there are pieces of equipment in a type are
used to define that type .. The SYMBOL instructi.on tells h.oW many pieces .of equipment in the
type, how many c.onnection terminals each has,
and the t.otal table area required t.o store requests
932
Fall Joint Computer Conference, 1968
for this type. Each DATA instruction gives an
equipment name and the ATE connection terminals for it.
When a new POL or a modification to an existing POL is defined to UTEC by means of SYNSEM, the syntax of the language and its semantics are stored into tables by the generator. Since
ease of language modification is a requirement,
three tables have been implemented as linked
lists. 6 The format list is used to hold the syntax
specification for each verb in the language. The
logic list is used to hold one entry for each SEM
instruction specified in a verb definition. The logic
modifier list holds SEM instruction modifiers
which are not suitable for entry in the logic list.
A dictionary is also used which contains the name
of each functio.n defined by SYNSEM as well as
various pointers to. the lists. Since UTEC is designed to handle POL's for automatic test equipment, it automatically controls the assignment of
equipment and produces wire lists. A pair of
equipment tables, the hardware name table and
hardware usage table, are built by the generator
to aid in these tasks.
The generator
The generatQr division 'Of UTEC accepts the
definitions of verb syntax and semantics written
in the SYNSEM language, and assembles this information into all the necessary tables and lists.
It also has the ability to delete and equate verbs
in the lists, and to build the equipment tables. The
generator is used whenever a DEFINE, EQUATE,
.DELETE, or EQUIPMENT control card is encountered and is divided into. fQur corresPQnding
sections as f'Ollows:
Define: F'Ollowing the DEFINE control card,
the SYNSEM language is used to define verbs.
First the syntax ofa verb is given using the SYN
language. The verb is placed into the dicti'Onary.
The syntax specification is analyzed character by
character, determining the type 'Of each argument
encountered. It counts the number 'Of characters
or uses a standard count allowed in each argument,
and thus builds the format list. It also enters the
symb'Olic character of each argument along with
its f'Ormat list position into an argument table for
later reference by the REQUIRED control card
and SEM language instructions. At the c'Omple-
tion of analyzing the syntax, the argument table
contains the one letter symbolic of each argument,
in the order in which they will appear in the
source statements. The REQUIRED control card
eontaining the one letter symbolic of each required
argument foll'OWS the SYN syntax specification.
Each argument is found in the argument table
and its format list position obtained. The format
list is thus modified to indicate which arguments
in the syntax are required with each usage 'Of the
verb. After the REQUIRED control card is processed, the generator must load the SEM program, which gives the semantics of the verb, into
the logic and lcgic m'Odifier lists. There are fourteen different f'Ormats for the thirty-six SEM instructions. There are f'Ourteen corresponding r'Outines in the generat'Or t'O handle the building of the
lists. For each instruction, the ccrrect r'Outine is
called to set up the list entries. When· a m'Odifier
'Of a verb is referenced by an instruction, the 'One
character symbolic of the SYN language is given
as a m'Odifier to the SEM instruction. This character is I'Ooked up in the argument table and its
integer positi'On number is used for the I'Ogic list
entry. (When a s'Ource statement is parsed by the
translator, each argument is I'Oaded int'O a table
at the same position as is used for containing its
SYN symbolic character in the generator.) Variables may be established in the SEM language by
a symbolic name. This symbolic name is placed
into. the argument table after the symb'Olic SYN
m'Odifiercharacters, thus establishing a location
for numeric reference in the logic lists entries and
for storage use by the translatcr. The argument
table provides st'Orage 'Only within a single definition, in that each new source statement starts
using this table at its top, destroying symbolic
names from previcus scurce statements. The SEM
instructions SX and TX provide storage locations
f'Or use throughout an entire source pr'Ogram compilation. A table exactly like the argument table
is used, except that the location symb'Olic name is
never destr'Oyed, thus giving each definiti'On access
to the same locati'On and pr'Oviding f'Or exchange
of information between definitions. If a SEM instruction requires alphanumeric information, or
if one entry in the I'Ogic list is not sufficient t'O ccntain all the necesary data for the instruction, a
pointer t'O the logic modifier list is placed in the
logic list entry, and as much space as necessary
is used in the logic modifier list. A two digit cp
Table Driven Computer
code (1-36), for access by the translator; and a
brance and link address, are always in a standard
location in each logic list entry.
E quat-e: Many verbs in a particular POL de-
veloped for use with automatic test equipment
are similar in syntax and semantics. For example,
the source statement for connecting a stimulus to
deliver volts is very similar to the statement for
connecting kilo-volts or milli-volts. The equate
section of the generator was therefore developed
whereby two or more verbs may share the same
definition, and therefore the same list area. The
name of the verb to be equated is placed in the
dictionary and all the pointers associated with the
equated verb are used with the new one, thereby
using the same definition. In order that the small
differences of the two verbs can be taken into account, the CHFLG SEM instruction must be used
in the original definition. This instruction requires
two indicators which are stored in the dictionary.
A definition always sets them to zero, but they may
be set to any desired value by the language designer using the EQUATE option. The CHFLG
op code can test the value of these indicators and
thereby set up branching logic in the SEM language program to control the translation.
Delete: The generator section of UTEC maintains a list of available cells to which the DEFINE
section looks as it makes the various list entries
for a given definition. The purpose of the DELETE section is to remove previously defined
verbs from the dictionary and to restore their
various list entries to the list of available cells.
This is done by changing the link at the bottom of
the list of available cells to point to the top of the
list entry for the deleted verb. This makes the
last list entry for the deleted verb the bottom cell
on the list of available cells.
Equipment: In this section, the generator builds
the hardware name table and allocates area in the
hardware usage table, both of which are used by
the equipment designator. All equipment of each
type which the system has available is defined in
the SYNSEM language by the SYMBOL and
DATA instructions. The generator calculates the
area required in each table section, and sets up
the pointers in the hardware name table and hardware usage table. The DATA cards contain the
name of orle piece of equipment along with its
933
terminal connections in the allocated positions in
the hardware name table.
Translator
The analysis and translation of source programs
and the subsequent output of intermediate code is
handled by the translator.
When analyzing a .source statement, the verb is
first checked against the list of defined verbs in
the dictionary. When a match occurs, an attempt
is made to verify any main units allowed with the
verb. Once a verb and main units match is made,
the associated dictionary entries are used as references to the format and the logic lists where information specified by the SYNSEM program for
this source statement has been stored by the generator.
Using the format list as a guide, the translator
parses each source statement and creates an argument table as it goes. A left to right scan of the
source statement is initiated looking for a modifier
of the type specified in the first format list entry.
If the modifier is found, it· is placed in the first
position of the argument table. The scan continues
looking for the next modifier as called for in the
next format list entry and places it· in the next
available argument table position. An error condition exists if the scan fails to verify a modifier,
unless that modifier is not required in which case
a dash is placed in the argument table in the next
position. The scan finishes when the entire format
list for this verb has been considered and an argument table entry is present for each item in the
list. Once the format scan has been completed, the
translator turns its attention to the logic list
where the algorithm for generating intermediate
code has been stored for this source statement.
Each entry in the logic list is a numeric representation of one of the SEM instructions. A two digit
op code is extracted from each entry which identifies the particular SEM instruction requested.
Once the instruction is known, the translator is
able to completely dissect the logic list and modifier list entries for this instruction and perform
the desired operation. All references by the instruction to the verb modifiers are made by simply
referencing the argument table position for that
modifier, as the parsing algorithm already has
inserted the modifiers in the table. As an example,
consider the following SYNSEM specification:
934
Fall. Joint Computer Conference, 1968
CONN
RANGE
AAA
A
KVDC
10.0
20.0
JC
JD
100
The generator creates the argument table as
shown in Figure 2.
1
2
3
4
A
K
C
D
FIGURE 2-Argument table of generator
Since the character A is in position 1, this position number is used in the logic list when the
RANGE instruction is processed by the generator.
When the source statement:
CONN 14.6 VDC JI01-42 J16-33
is parsed by the translator, the argument table is
filled as shown in Figure 3.
1
2
3
4
14.6
VDC
.1101-42
J16-33
FIGURE 3--'-Argument table of translator
When the translator discovers the RANGE instruction number in the logic list, it decodes a
reference to position one in the argument table for
the number it is to test. In the example, the number 14.6 is checked to determine if it is between
10.0 and 20.0.
Each logic list entry provides the translator
with the position 'Of the next instruction to be consid-ered, or in the case of conditi'Onal instructions;
the translator must pick the next instructi'On from
two or three choices after it performs the current
instructi'On.
The translator continues through the logic list
until the END'opcode is discovered, at which time
it has completed its analysis and code generati'On
for the source statement under consideration. The
next statement is read and the entire process repeats. When the translator reads the END verb
it turns the intermediate code generated for the
program over to the assembler for final 'Object
C'Ode' pr'Oducti'On.
Equipment designator
Each time the translator processes a source
statement which requires the use 'Of ATE equipment, an entry on a tape is generated by means of
the SEM instructions EQUI or PREAS. This tape
is called the request tape. The translator itself
has no ability to select equipment from the available equipment pool in order to satisfy the needs of
the source statement. The SEM language program
used to translate these source statements requiring equipment first generates a unique symbolic
number which will be used by it to symbolically
refer to an equipment name in the intermediate
code it produces. It then determines the type of
equipment required by the source statement and
generates the request tape entry. Each such entry generated tells the type of equipment desired
and the symbolic number used to identify it, and
tells how the terminals of that equipment should
be connected. In the case when a specific piece of
equipment must be used in a particular manner,
the translator also processes an equipment preassignment by producing a request tape entry
which gives the specific name of a device and tells
how it is to 'be c'Onnected.
The function of the equipment designator is to
read and process the entries on the request tape
produced by the t~anslator. It attempts to match
an equipment name of the correct type to each
symbolic number and produce inf'Ormation describing how each piece of equipment is to be connected. In the assembly of the intermediate code,
each symbolic number is replaced by the matching
equipment name as provided by the equipment
designator.
The equipment designator operates using two
tables: the hardware name table and the hardware
usage table. The hardware usage table is divided
into two secti'Ons for each equipment type: the
hardware assignment section and the hardware
request section.
The hardware assignment section for each
equipment type contains one assignment indicator
and one row for each piece of equipment of that
type. The indicator gives the, status 'Of the equipment while the row c'Ontains references to the c'Onnections made to this equipment.
The hardware request section for each equipment type can contain a number of requests for
equipment of that type. Each request section entry is made up of an indicator and row like th'Ose
Table Driven CQmputer
in the assignment sectiQn, plus a half-wQrd which
is used tQ hQld the unique symbQlic number fQr the
request. The number 'Of entries allQwed in the request sectiQn fQr a particular type of equipment is
specified in the SYNSEM equipment definitiQn.
The requests prQcessed by the designatQr fall
intQ tWQ classes: ( 1 ) ThQse which name specific
pieces 'Of equipment, and (2) ThQse which symbQlically seek an assignment 'Of any piece 'Of equipment 'Of a specified type. When fulfilling requests,
tWQ passes are made 'Over the request tape with
the items in classes one and tWQ being handled 'On
passes 'One and tWQ respectively.
On pass 'One, the designatQr simply reads the
requests, and in the hardware assignment sectiQn,
Rets the indicatQr fQr the named piece 'Of equipment and fills the rQWS with the cQnnectiQn references. BefQre the first pass, all indicatQrs reflect
an equipment available status. After pass 'One,
the indicatQrs 'Of the equipment named in pass
'One are set tQ indicate 'One 'Of tWQ states: (1) Hard
preassigned-specified equipment may 'Only be used
as stated.
(2) Update preassigned-specified
equipment shQuld be used as stated if PQssible, but
may be used differently if needed. This preassignment is autQmatically generated at the end 'Of each
cQmpilatiQn fQr each pi.ece 'Of equipment used. It
then is submitted 'On the fQllQwing run tQ insure
that the same wire cQnnectiQns will be generated
whenever PQssible, even when changes are made
in a source prQgram.
On pass tWQ, the designatQr tries tQ assign 'One
piece 'Of equipment tQ each symbQlic request. In
additiQn, it creates the matching list tQ be used
by the assembler when prQcessing the symbQlic
references in the intermediate cQde.
Each request causes a scan 'Of the hardware assignment sectiQn fQr the type 'Of equipment requested. If the connecti'Ons 'Of the request match
thQse 'Of a piece 'Of equipment already used, the
request is matched with that equipment. If the
cQnnectiQns 'Of the request dQ nQt match thQse 'Of
any already used, a new piece is assigned tQ match
this request. If all the equipment 'Of the type requested has b.een used, the request is put intQ the
hardware request sectiQn and saved. When the
entire request tape has been read in pass tWQ, the
designator is finished unless SQme unfulfilled requests. remain in the request section. If unfulfilled
requests dQ exist, the designatQr scans the assignment sectiQn fQr all equipment which was update
935
preassigned but not used in this cQmpilatiQn. It
resets the indicatQrs of these equipments tQ reflect an available status. An attempt is then made
tQ assign the unfulfilled requests tQ the equipment
made available. If the request still cannQt be satisfied, it remains in the hardware request sectiQn.
Finally, a wire cQnnectiQn list is prQduced frQm
the hardware assignment sectiQn giving all the
equipment used in the cQmpilatiQn and hQW it is to
be cQnnected. HQW the equipment was used in reJatiQn tQ a possible previQus cQmpilatiQn is alsQ
stated. ErrQr conditiQns are prQduced based 'On entries remaining in the hardware request sectiQn.
New update preassignments are also generated
fQr use if the prQgram is tQ be changed and recQmpiled, SQ that a similar wire list can be prQduced.
CONCLUSION
At this time, UTEC has been cQmpletely written
and checked 'Out using FORTRAN IV, and a language develQped for use with 'One type 'Of autQmatic test equipment (LeSS) currently being
prQduced by RCA has been implemented using
UTEC.
The implementatiQn 'Of anQther language fQr a
secQnd type equipment is being considered at this
time.
It is interesting to nQte that after having defined
the language tQ UTEC, the users CQuld evaluate
the quality of the language and its usefulness, and
suggest changes and imprQvements.
These changes were easily incQrpQrated intQ the
language almost daily during a shakedQwn periQd,
thus allQwing them to be tested within days after
they were cQnceived. The overall effect was to
stimulate ideas for improvement. Thus, a much
more effective language than that 'Originally specified was developed.
REFERENCES
1 BJEVANZIA
A utomatic test equipment: a million dollar screwdriver
Electronics August 231965
2 P Z INGERMAN
A syntax-oriented translator
Academic Press 1966 ch 1 pp 13-19
3 VMAYPER
Programming for automated checkout-Part I
Datamation April 1965 Vol 11 No 4 pp 28-32
4 VMAYPER
Programming for a'ltomated checko.·t Part-II
Datamation May 1965 Vol II No 5 pp 42-46
93&
Fall Joint Computer Conference, 1968
5 BLRYLE
The atoll checkout language
Datamation April 1965 Vol II No 4 pp 33-35
6 MVWILKES
Lists and why they are useful
Proc ACM 19th Natl Conf August 1964 Phila Pa
7 BHSCHEFF
Simple U8er oriented compiler source language for programming
'automatic te8t equipment
Communication of thE' ACM Apri11966 pp 258-266
On the basis for ELF-An extensible
language facility*
by T. E. CHEATHAM, JR., A. FISCHER and P. JORRAND
Computer Associate8, Inc.
Wakefield, Massachusetts
INTRODUCTION
There are two basic premises which underlie the
development of ELF. The first of these is that there
exists a need for a wide variety of programming languages; indeed, our progress ·in the understanding and
application ot computers will demand an ever widening variety of languages. There are, in fact, "scientific"
problems, "data .processing" problems, "information
retrieval'~ problems, "symbol manipulation" problems,
"text handling" problems, and so on. From the point of
view of a computer user who is working in one or more
of these areas there are certain units of data with which
he would like to transact and there are certain unit
operations which he would like to perform on these data.
The user will be able to make effective use of a computer
only when the language facilities provided allow him to
work toward a desired result in terms of data and operations which he chooses as being a natural representation
of his conception of the problem solution. That is, it is
not enough to have a language facility which is formally
sufficient to allow the user to solve his problem; indeed,
most available programming languages are, to within
certain size limitations, universal languages. Rather,
the facility must be natural for him to use in the solution of his particular problem.
The second premise underlying our work is that the
environment in which programs are prepared, debugged,
operated, documented and maintained is changing and
that the language facilities currently available do not
properly reflect these changes. Weare speaking, of
course, of the advent of computer-based files and of
interactive computer systems which permit the user to
be more intimately involved with his program than was
possible with a batch system. A modern language system must be developed with this kind of environment
*This work was supported, in part, by the National Aeronautics
and Space Administration under contract No. 12-563
937
in mind, but should still be adaptable to the older environment.
Let us now explore briefly the implications of these
two premises and examine some alternative approaches
to providing an appropriate language facility.
The "classical" approach to providing a large variety
of languages has been that of developing languages and
their translators-and often even their operating environments-independently. However, it seems clear
that the cost of creating and maintaining an ever
increasing number of language systems is not tolerable.
Somehow we must both provide the variety of "facilities
but, at t~e same time, also reduce the number of different systems. It would seem that there are two extreme approaches to the problem of developing a
language facility which provides all things to all men.
These are referred to as the shelZ approach and the core
approach. The shell approach calls for the construction
of one universal language which contains all the facilities required for every class of users. PL/I with the
"compile-time" facility is probably the best current
example of a shell language. In contrast, the core approach calls for the development of a small "core" language which, by itself, is probably not appropriate for
any class of user, but which contains facilities for selfextension. A particular class of users then extends the
core language to create a language which is appropriate
for their problems. There are, to our knowledge, three
current languages which are, to some extent, core languages: ALGOL-D, GPL, and ALGOL-68.
The shell approach does have a certain appeal. Like
the modern supermarket it promises us a great variety
of both ordinary and sophisticated products. But the
overhead inherent in utilizing such a system is rather
large. As in the supermarket the user must pay for both
the space to contain the products he is not using and the
extra time to access the desired product. Perhaps a more
important difficulty inherent in the shell approach is
938
Fall Joint Computer Conference, 1968
that whenever a meaning is prescribed for a construction,
that same meaning is force'dupotiallll,sers, even tho'llg-h
the construction might" reasonably mean several things.
In PL/I this has lead to such anomalies as: botli of the
boolean expressions 5 < 6 < 7 and 7 < 6 < 5, are
true; the interpretation A *B where A and B are matrices is the matrix whose (i,j) th element is the product
of the (i,j) th elemen~s of A and B. It is not that these
kinds of interpretatIons are "bad"-the point is that
they are built-in and unchangeable. No matter what
meaning onemight like for 7 < 6 < 5 (we like false) or for
(i,j) th element of A *B, (we like the inner product of
the i th row of A and of the j th column of B), that meaning
provided by the designers is now fixed. One must revert to procedures if he wishes to introduce new operators or to detour around the built-in operators when he
needs to vary the meaning of those originally provided.
And this becomes even more cumbersome when, .as in
PL/I, procedures can produce only scalar results. We
would maintain that our reasons for rejecting the shell
approach are not based on speCUlation; the difficulties
currently being experienced with the implementation
and utilization of full PL/I provide ample evidence.
Thus it is our contention that the most reasonable
approach to providing the desired" variety of language
facilities is that of providing an extensible language
supported by an appropriate compiling system. We do
not, however, suggest that we can now devise a single
. universal core language which will adequately provide
for the needs of the whole programming community;
the diversity in "styles" of languages and translation
mechanisms will probably always be sufficient to encourage sev~rallanguage facilities. ELF, which is the
subject of this paper, provides a facility in the "style"
of such languages as ALGOL-60, PL/I, and COBOL.
N ow let us discuss the second premise, concerning the
environment in which we envision programming being
done. Our basic assumption here is that the programmer
does not approach the computer with a deck of cards or
magnetic tape which constitute a complete and independent run: a "run" deck which would commence with
control cards, followed by his problem and then by his
data, and which would result in the system accepting
these, compiling his problem, running it against his
data, and finally burying him in dumps or some other
visible output. Rather, the programmer's unit transactions shOUld be thought of as acts of updating some file.
He might insert a few corrections to his program text,
might call for some incremental change to some executable form of his program, and then might let his program run.
If he is working in an interactive system, he might
maintain intimate control over the proceedings, responding to messages as they occur instead of having to wait
for the final results before he can exert any control.
We do not suggest that ELF is a solution to the problem .of '. providing' 3, langUage for the effective use of a
modern time~shared* system with permanent users'
files. Indeed, there is really very little experience now
accumulated in using such facilities, as most of the language facilities now in use on the available systems
were developed as "batch" languages. It is to be hoped
that work such as that now underway at CarnegieMellon under PerIis' direction will provide some
guidance in this area. 11
We do suggest, however, that we can now devise an
extensible language facility in such a manner that it is
cognizant of an avilable filing system and provides for
interactive control; we will discuss oUr point of view on
the relation of the language to the system in a later section.
The remainder of this paper is divided into four sections. In the next section we will discuss the overall design criteria which have guided the development of the
language. Following this, we will present an overview of
the language with the object of providing the reader
with a general feeling for the language as well as for the
translating and executing mechanisms which we envision. Following this we will discuss the kinds of features and facilities which will be in the language; the
purpose of this section is to justify and describe certain
constructions proposed for the programming language
component of ELF. The final section is devoted to a
summary and conclusion.
Design criteria
Perhaps the most eloquent defense of the overall design criteria to which we have tried to adhere was given
in the 1966 Turing lecture by A..J. PerIis. 10 There
PerIis framed the problem as that of providing for systematic variability in a language. All acceptable languages provide for constant as well as for variable operand values. However, a great deal more variability
must be provided if a language is to be extensible. There
must be means of providing for variability in the
types of quantities with which we deal, in the operations
on these quantities, in programs or procedures, in the
syntax of programs, in regimes of control, in the binding of programs to other programs and data, in the
means of accessing data, in the employment of the
various. storage and input/output resources afforded
by the system, and so on. However, we must provide
for this variability very carefully so that we retain the
necessary control over the efficiency of use of the com*That is, interactive" how the intimacy between the user and
the system is arranged does not concern us.
ON the Basis for ELF
puter, or else our result will be a purely academic exercise.
In our design of ELF we have looked toa number of
"users" as sources of constraint; unless the language
facility is properly matched to its users, it will not be
an effective tool. These' "users" include the programmers who will read and write in the language, the computer which will execute programs, the compiler or
translator which will prepare executable programs, and
the operating system which will provide the environment for the preparation and execution of programs.
In addition, we feel that there are two other important
sources of constraint: the traditions established by
current languages, and the practicality of the language.
Let us now briefly discuss the nature of the constraints
which each of these various sources imposes.
Programmers
People have to learn and use the language. Indeed
we hope that people will even read programs in the language in addition to writing them. However, we find
that different people have rather different ideas about
the form in which a program should be cast. Most
serious programmers adhere to the basic expression
forms where these forms are appropriate-using the infix, prefix, and postfix operators plus parentheses which
have resulted from the years of development of mathematical notation. The form of program text which is
not inherently "expression-like" is, of course, not so well
established. We note here, however, that the usual
"out" for introducing new operations into a languagethe use of functions or procedures-does not provide an
adequate notation for the majority of operations. If the
number of arguments required exceeds three or four, the
user has difficulty in associating the "meaning" of an
argument with its position in the argument list and he
might be considerably better off with some keywords to
help him focus on what is what. Also, if the nesting of
function calls gets to be more than two or three deep,
the "LISP-unreadability" problem becomes serious. We
would also note that, for the user, an important criterion is that he should not have to introduce and deal
with constructs which are unnecessary to the solution
of his problems. The arithmetic expression form provides
a facility which is both natural to a large class of users,
and which also very effectively hides the setting up of
temporary storage for intermediate results. Similarly the various renderings of McCarthy'S conditional
expressions as well as the iteration or looping facilities
which appear in many programming languages have, as
a secondary effect, that of eliminating the need of
introducing temporaries or labels which are used. only
once (see Refs. 2 and 9 for interesting discussions of this
point).
'989
Computers
The abilities of current and projected computers must
also be viewed as a source of constraint. That is, we
should try to "match" the basic types and operations in
the language with those available in "standard" computers (and here we have reference to OPUs, not the
whole "system' ') . Thus, for example, although our
mathematical natures might encourage us to define only
integer quantities and operations as primitive, and obtain
floating point quantities and operations by extension,
this would surely be foolish when we are faced with
computers which by-and-Iarge have floating point
quantities and operations as primitives. Similarly, we
reject the notion of quantities and operations drawn
from set theory as primitive in the language because of
the wide variety of implementation strategies which
might be employed in providing for these. Such quantities and operations should be introduced via extensions.
We must presume that the facilities available in current computers mirror, to some extent, the basic
facilities which the users require.
Compilers
The past several years have-witnessed-the-emergence
of a considerable body-of experience-and technology-in
compiling plograms. Unfortunately, most recent language developments seem to ignore this technology and
demand new and ever more difficult and expensive
translating mechanisms. We have attempted to reverse
this trend and -to adhere rather strictly to the technology available-to provide a language which can be
effectively and efficiently translated and for which the
known techniques of code generation and optimization
will apply.
Operating systems
The constraints which mi,ght be imposed -by the
peripheral devices and operating systems which are' to
be used must be noted. Thus, the -means for encoding
messages to and from the computer are rather strictly
dependent upon the devices (and software) which are
available; our adherence to a conventional string language with reasonably conventional characters is dictated by this consideration. The control structure inherent in modern computers must also be kept in mind;
for example, the notion of "interrupt" is basic in -most
computer systems and our language facilities should
reflect this. Further, the availability of various kinds of
storage having varying degrees of accessibility plus the
needs of the operating system to allocate the storage
and other resources of the system must not be ignored.
940
Fall Joint Computer Conference, 1968
Tradition
The "tradition" which has been established·by such
languages as ALGOL-60, PL/I, COBOL, and LISP
and which is being established by ALGOL-68, GPL,
and ALGOL-D sho~td be considered as a source of
constraint. That is, it does not seen reasonable to reinvent and re-cast the facilities available in those
languages just to be different. Our departures from the
facilities available there should be well thought out
and well justified. It will be·clear that we have in fact
departed in more-or-Iess significant ways from all these
languages; we hope that our arguments for doing this
are convincing.
Practicability
The final source of constraint which we have tried to
observe is that of practicability. It is our intention that
the language· be as efficient and useable as any of the
conventional programming languages. In adhering to
this constraint we have failed in many ways to reach
all the goals of variability which Perlis prescribed. Thus,
ELF provides a language which has the kinds of
variability which we can imagine being handled with
reasonable efficiency. Another generation of language
development will be desirable when we better understand other kinds of variability and can devise mechanisms for handling them efficiently.
Overview of the extensible language facility
There are a number of facets of ELF that are of
interest. In this section we will look at three of these.
First we will look briefly at the base language (BASEL) .
Following this we will consider a compiler for BASEL,
and the ways in which it might be extended. Finally we
will consider the interface between the language system
and the operating environment.
The base language
BASEL has four kinds of primitive program elements:
a Names identify the objects that a program manipulates.
b. Operators manipulate the objects. These. include
the assignment operator, operators such as plus
and less than, and procedure calls.
c. Control statements are used to specify the order in
which the expressions are executed.
d. Declarations are used to define objects and operators, and give them names.
These program elements are embedded in a block structure which is a generalization of that in ALGOL-60.
In the next section we will discuss the elements of the
language in somewhat more detail; for the moment it
will suffice to think of the language as similar to
ALGOL-60 but with provisions for new data types and
operations (or, if ALGOL-68 is familar to you, similar
to ALGOL-68).
A BASEL compiler
Second we want to explore the compiling mechanism
which we have in mind. Although one does not converitionally talk about compil!ng techniques in describing a language, we believe that it is helpful in this case.
Our choice of language constructs, notations, and
mechanisms has been strongly influenced by what we
feel can be readily handled by the current compiling
technology. Thus understanding our view of the kinds
of compiling mechanisms envisioned is rather important. For present purposes we want to think of the compiler for the language as consisting of several "components," including: a lexical analyzer, a syntactic analyzer, a parse interpreter, and a user controlled optimizer, plus other components for generating machine
code and filing it, or for interpretively executing some
"internal" representation of the program text, and so
on. We shall have no particular interest in these latter
components here; let us now consider the other components.
Lexical analyzer
The lexical analyzer will be responsible for isolating,
identifying, and appropriately converting the source
input (e.g., typed characters) thus producing a stream
of "token descriptors" representing constructs at the
level of "identifier," "literal," "operator," "delimiter,"
and so on. We anticipate that, although the lexical
analyzer will be "table driven" by tables derived from a
grammar which specifies the structure of the tokens,
these tables will not ordinarily be changed or extended
by the average user and we will thus think of them as
fixed.
Syntactic analyzer and parse interpreter
We intend that the syntactic analyzer be essentially
an operator precedence analyzer. An operator precedence analyzer is, of course, one of the simplest and
most eflicient kinds of syntactic analyzers available.
Operator precedence analysis works only on a rather restricted set· of languages. However, as Floyd demonstrated in his original paper on this method ,4 ALGOL60 is close to being an operator precedence language;
further, those changes Floyd proposed to the original
syntax rules for ALGOL-60 and to certain constructions
in the language in order to make it operator precedence
ON the Basis for ELF
did no real violence to the language but actually made
it cleaner and more symmetric. Thus, a language does
not necessarily suffer in richness of style because it was
designed with this method of analysis in mind. Another
important reason for the choice of this method is that
those properties of the operators which, properly encoded, are required to "drive" such an anlyzer are
exactly the properties which the user has in mind when
he·specifies an operator, namely, the precedence, in the
sense of order of evaluation of that operator relative to
other operators.
It will be convenient to think of the operators available in the language as including binary infix (e.g. '+'
or '<'), unary prefix (e.g. C'), unary suffix (e.g. '1'),
unary outfix (e.g. 'I ·.. 1'), n-ary "distributed" (e.g. 'if ...
then ... else' or lincrement ... by ... '), and llfunctional"
(e.g. 'lVIAX ( ... ,... )' or 'SINO'). Each operator (actually
each fixed "part" of each operator) will enjoy one of
four relations with respect to all other operators (or
parts of operators), namely: takes precedence, yields
precedence, has equal precedence, or none. The user
will introduce a new operator (syntactically) by
specifying the precedence of each of its parts relative to the precedence of operators already available. It will generally be the case that a given operator
will be defined for operands of a variety of data types;
the "syntactic analyzer" will isolate a phrase-an
operator plus its operands-by using the precedence relations, and then the parse interpreter will then determine the "meaning" or "interpretation" of the phrase in
accordance with specifications which are either built-jn
(e.g. with '+' operating on two integers) or supplied as
extentions by the user (e.g. with '+' operating on two
quaternions). One of the' 'dispositions" which the parse
interpreter might make of some phrase is to place the
operands of that phrase into some previously given
(macro) "skeleton" and re-submit the resulting text for
syntactic analysis. This will provide what are essentially
the "lexical macro" and "syntactic macro" facilities
proposed in. 1
User controlled optimizer
There are certain operators which require a larger
context than the phrase in which they occur for their
interpretation, particularly if one has a goal of producing optimal coding and either does not have, or perfers
not to overburden, a code optimizer. An example here
would be the coding of the multiplication of two conformable matrices in the three contexts:
A*C
(A
+ B) *C
(A
+ B) * (C + D)
Thus, it may be that one might desire an algorithm for
matrix mUltiplication which required only one tem-
941
porary scalar for the first case, a temporary row for the
second, and a full temporary matrix only for the third.
On the other hand, one might use tenlporary rows for
all three cases, giving up storage efficiency in the first
case and computation efficiency in the third. The point
is that there are cases in which the determination of the
appropriate means for performing some operation depends upon some context. The user controlled optirnization phase provides for this. It would also be in this
stage that the user would have the ability to tinker
with' such things as the allocation of storage, the means
of access (e.g., via some hardware or software "paging"
scheme) to certain quantities, and so on.
Briefly, we think of the parse interpreter as constructing what in effect is a computation tree representation
of the analyzed program text; each node of this tree
would be labelled with the data type of the value it
represents. The user controlled opti11'"izer may then be
thought of as a mechansim. which "walks" over this
computation tree, inspects context as appropriate, and
re-organizes and re-constructs portions of this tree.
The mechanism has certain similarities with those proposed in ALGOL-D, but with a control and sequencing
strategy similar to that of the GSL component of the
CGS system (see Refs. 12, 13 and 15)
Interface view
N ow let us briefly consider the interaction of the
language with the environment in which programs are
constructed, debugged, and executed. First, we want to
emphasize that we would expect the language to include
the means for the kinds of communication with the
operating environment which are typically handled
via "control" or "job" statements as well as the kinds
of communications which have to do with "editing."
We presume that there is a filing systenl which contains
such things as: (1) program text which we might want
to incorporate into the input stream to the compiler
during some run, (2) specifications of modes of programs
or procedures which our current program might want to
reference, (3) lnodifications or extensions to the compiler which we might want incorporated for processing
our current program text, (4) an "executor" which can
execute programs as they are represented following the
interpretation of the parse and user-controlled optimization, (5) data which has been previously input or
generated and then filed, (6) and so on. Clearly there
must also be means for placing any of these items in the
filing system. Thus, a "run" or "session" might be one
in which we input a number of extensions to the language including new data types and operations over
them, with the result that they are filed in such a fashion that we can later call the compiler, mentioning
that it is to include these extensions. Another type of
942
Fall Joint Computer Conference, 1968
session might be the input of program statements
with the expectation that they be executed directly.
Another might be the input and editing of a program
with the expectation of filing it for later execution. That
is, a "unit transaction" within the ELF system will
typically utilize material previously developed and filed,
and result in material to be filed. There will be a number
of forms which this material mjght take, rangjng from
or certain programs within the compiler at the other.
So long as this philosophy of operation is understood we
will not go into further details here; we intend to s~ell
out more details of the linguistic forms and possible
system mechanisms to attend to problems in this area
in a subsequent paper.
The base language
In this section we will present the basic concepts and
mechanisms which are introduced in BASEL the base
Ianguage component of
\ ELF. It is not our purpose
'
to
provide an introduction or primer for the language.
(One must see Ref. 3 for this.) Rather, we hope that our
discussion will, as it were, "soften the blow" and make
the details of BASEL appear reasonable. Thus we will
suggest the kinds and means of variability which
BASEL permits. We" might also note that we are not
attempting to justify all the concepts and notions in
the language. This section is divided into two parts':
First we will discuss the fundamental notion of value
and show how it is handled in BASEL, comparing
BASEL to other languages. Then we will present the
declarations and expressions which manipulate values.
Values
One Of. the baSi? characteristics" of a programming
language IS the vanety of values it can handle and the
-;vay in which these may be manipulated (that is, read
In, stored, named, declared, operated upon, passed as
parameters or returned as results of functions and writ- .
ten ~ut.) The larger the variety of values a language ~an
manIPul~te, the more "powerful" that language is; the
more unIformly these values are treated the easier
that language will be to write, compile ~nd extend.
We will use FORTRAN II to demonstrate what we
mean by "~ value." FORTRAN handles only real
values and ~nteger values in a general way. One may
rea~ and wrIte alphabetic values, but must treat them
as If they were integers. Also, FORTRAN has arrays,
?ut no concept of an array value which may be treated
In all ways as a unit.
We can distinguish two aspects of a value : (We have
been strongly influenced here by ALGOL-68.)
-
its data type or mode (that is, the "class" it belongs to, that aspect which
determines the contexts in
which it is meaningful and
the operations which apply
to it.)
-
its meaning
(that is, its interpretation,
the object which it represents.)
Example:
The number 3.14159 has the mode real and its meaning is an approximation to the number pi.
One must be able to store values, and thus we are led
to think about variables. We see that we can treat
variables like values, having both mode and meaning.
Example:
A real variable has the mode loe real (a location in
which to store a real value) and its meaning is the
address of that location.
We have made a distinction here between the meaning of a variable and its value (that is, the value stored
in it.) We can refer to either (as will be described later)
and speak of the mode of either. This makes possible a
simple and uniform treatment of pointers. We see that a
pointer is simply a variable in which the meaning
(address) of another variable is stored.
Example:
A pointer to a real variable has the mode loe loe real
and its meaning is the address of a box in which we
can store the meaning of a real variable (a loe real).
Continuing this line of thought we see that we can
describe the mode of. any pointer in terms of the mode of
the thing it points to, which permits a compiler to decide
whether it is meaningful to use that pointer in any
given context.
The aggregate-value is another generalization of the
concept of a value to which the notions of mode and
meaning must also apply. We must go further than
PL/I did. The PL/I declaration
DECLARE
1
A
2 Al INTEGER
2 A2 FLOAT
ON the Basis for ELF
declares an instance of an aggregate, but there is no way
of speaking of the mode of that aggregate independently of this instance. One result of this is that such
aggregates may not be returned as the results of functions. This difficulty also arises with arrays in ALGOL60 and FORTRAN.
So in addition to a set of "basic modes" (like real) we
need a set of "mode constructors" which can be used to
combine the basic mode descriptors into descriptions of
more complicated values.
Basic modes
We have adopted the following set of modes as basic:
integer value
real value
boolean value
character value
written
int
real
bool
char
Mode constructors
Variables:
If ffit is a mode, then loc mt is the mode of a variable
which can store a value of mode mt. ("loc" in
BASEL serves the same purposes as "ref" in
ALGOL-68. The differences will be explained later.)
Aggregates:
An aggregate is a sequence of values. BASEL has
three ways of describing these.
tuple: A tuple is an ordered list of values. These are
used primarily as the actual parameter list in a
function call, but they can also be computed,
constructed and stored in variables.
If mt1 , mt2, ...ffit n are modes, then
tuple (ffitl, ffit2, ... mt n ) is the mode of an aggregatevalue whose parts are n values of these modes.
Examples:
tuple (real, int, char)
tuple (loc real, real)
row: A row is a homogeneous aggregate. We treat
this case separately for two reasons: first, rows
are particularly ·simple to implement, and second,
this is the only way to describe a variablelength aggregate.
If n is an integer value and ffit is a mode, then
row n of ffit is the mode of a homogeneous series
of n values, each of mode mt. These are numbered
from 1 to n and may be accessed by number.
Note that this is a more elementary notion than
the array of ALGOL-60.
943
Examples:
row 3 of real
row 6 of loc char
(This might be used to
describe a character
string variable.)
(This describes a variable length row of
integers.
row any of int
struct: The mode constructor struct attaches names to
the elements of an aggregate, permitting these parts
to qe accessed by name. If mtl, mt2, ... , mtn are modes
and el, e2, ... en are identifiers, then struct (ffitlel,
mt2e2, ... mtne n) is the mode of an aggregate-value
with n named parts. (This mode constructor is exactly
the same as in ALGOL-68.)
Examples:
struct (real r, real i)
might be used to describe a complex number.
struct (loc int level, row 50 of loc bool elem)
might be used to describe a push-downstack which can hold up to 50 boolean
values. The integer vari2 ble 'level' would
store the index of the current top of the
stack.
Procedures:
A procedure is a parameterized description of a
value. (This value is usually specified by giving an
algorithm by which to compute it.) In BASEL,
procedures are also considered to be values, which
may be stored, passed as parameters, etc. Because
of this we are interested in the mode of procedures.
Since procedure calls are used in expressions, the
procedure's mode must embody information about
its domain and range, in order for the compiler to
ensure the meaningfulness of expressions involving
procedures. Therefore we define the mode of a
procedure as follows: if mtl, ffit2, ... mtn and ffit are
modes then proc (ffitl, mt2, ... mt n ) mt is the mode of
a procedure which takes n parameters of modesmtl'
mt2, ... , etc. and returns a result of mode ffit. If the
procedure takes no paraID:eters, empty parentheses
are written. If it returns no result, the word "none"
is used in place of the mode of the result.
Examples:
proc (real) real
proc (int) none
describes the mode of of the
sine function.
might be used to describe a procedure which
944
Fall Joint Computer Conference, 1968
opens the file designated by the integer code.
proe
0 strue (int, int)
proe () none
could describe a procedure which returns the
current time of day expressed as two integers
representing hours and
hundredths of hours.
A row or a structure is denoted by writing a row or
struet mode followed by a tuple with the appropriate number of elements, each of which has the
appropriate mode.
A procedure of mode proc (;)11,1, 2, " ' , mt n) mt is
written: proc (mt1f1, 2f2, "', mtnfn) (E)
where the fi are the names given to the dummy
parameters, and E denotes an expression whose
value has mode mt. If the procedure returns no
result, then E must denote an expression with no
value.
could be used to describe a DUlVIP procedure.
Dynamically varying modes
Finally, if
Occasionally it is useful to permit a varIable to store
values of more than one mode, or to permit an expression to produce a value whose mode depends on the
data. The mode-descriptor operator 'union' is used to
build the description of a mode which is not completely
fixed, but can be one of a fixed finite set of modes. The
mode of a value stored in a 'loe union' can vary dynamically among the fixed set of modes specified by the
'union'. The mode of the value of an expression' can
vary if that expression contains a conditional whose
'then' and 'else' clauses have values of different modes.
If mtl,.'" mtn are modes than union (mt1, ••• mt n ) describes
an object whose meaning may have anyone of the given
modes; which one may not be known until run time, and
may change.
~m;
is a mode then
a mt creates a value of mode ;me
Examples:
Mode
A Value of that Mode
tuple (int, int, int)
[1, 5
tuple (real)
[sine X]
row 4 of bool
row 4 of bool [true, true, true,
true]
struct (real r, real i)
complex [0.5, 2.J ("complex"
has been declared as a
synonym for the mode
struct (real r, real i).)
proc (int, int) tnt
proe (int A, int B) (if A
then A else B)
loe int
aloe int (This causes an
Meanings
Certain values of the basic modes 'have pre-defined
representations. These are:
the
the
the
the
+
7, 4J
>
B
integer variable to be created. Its contents are not
initialized. This expression
then denotes the new address.)
non-negative integers written 0, 1, 2, ...
non-negative reals
. 0., 3.96, .5, 3.7 e-2
boolean values
true, false
'A' ... , 'Z', '1', '2',
character values
.. " ',','+', ...
Declarations, expressions and programs
Because these are conventional representations of
their meanings, they are sometimes called 'literals'.
Through declarations, the programmer can give other
names to these values. In fact, it is possible to name any
value that can be computed.
Since an unbounded number of modes can be defined
in BASEL, the language must provide a consistent way
of denoting a value of any mode.
The conventions we have chosen are:
A value of mode tuple (~1, "', mt n) is denoted by
writing [VI, v!, ... v fll. Each VI denotes a value of
mode mt,.
Declarations
A declaration attaches a name to a value, thereby
creating an object. In BASEL, any value which can be
computed or denoted may be named. BASEL has four
kinds of declarations, which we will consider in the following order:
-
mode declarations
data declarations
operator declarations
meaning definitions
ON the Basis for ELF
Mode declarations
A mode declaration defines a name for a mode.
This name then acts as a synonym for that mode.
Example8
let complex be 8truct (real re, real im)
This describes a complex number. Having
given a na'lle to the mode expression, the following expressions become exactly equi valent:
8truct (real re, real 1m) [l.4, .2]
complex [1.4, .2]
let tree be 8truct (char top, row 2 of loc tree son)
This describes a recursive tree structure, in
which each node has two sons.
As with mode declarations, a data declaration
defines a name for a value. Within the scope of this
declaration that name and the value it denotes are
completely synonymous.
Example8
This declares "pi" to be a name for the real
value "3.14". Notice that pi is a name for a
constant, not a variable. One would never be
able to store another value in pi.
Examples:
let i be infixR prec > *
let ! be 8uffix prec > *
let sin be prefix prec > !
If these three declarations were given in this
order, the resulting precedence relations would
be:
t > prec of sin > prec of ! > prec of •
After an operator has been declared one or more meaning definitions are used to associate procedures with that
operator. These are written:
let (operator name) mean (procedure-value)
let + mean proc (bool a, bool b) (if a then ..., b
el8e b)
"+"
This definition states that
is to be meaningful when written between two boolean values,
and is to denote "exclusive or" in that context.
A call on this operator would be written: x
y,
where x and yare boolean values. When the procedure is executed "x" is bound to dummy
parameter "a" and "y" is bound to "b."
+
let X be a Zoe real
As mentioned. above, the expression "a loe
real" causes a new loe real to be created, and
denotes the resulting address. This declaration
makes X a synonym for that address.
>
j then i else j)
This declares that MAX is a name for a procedure which computes the maximum of its
two integer arguments.
Operators
In BASEL an operator is simple a collection of related procedures plus some information on how a
call on that operator is to be written. This syntactic information is declared with an operator declaration, written as follows:
let (operator name) be (shape) prec (precedence
relation) where the (shape) may be
prefix
suffix
and the precedence relation specifies that the
precedence of the new operator is either =,
(equal to), > (just greater than) or < (just less
than) that of some previously defined operator.
Example:
let pi be 3.14
let MAX be proc (int i, int j) (if i
injixL (left associative)
infixR (right associative)
infix
(non associative)
prec of
Data Declarations
945
The term "generic" is commonly used to describe an
operator that can have different meanings, depending
on the modes of its operands. A particular meaning is
chosen in a given context by matching the modes of the
operands to the modes of the formal parameters in one
of the procedures attached to the operator. This "match"
is made according to the conventions described later
for procedure calls.
Expressions
Program Structure
In BASEL a program is a compound expre8sion.
A compound expression has a body, which is written
between "begin" and "end" or between
"("and")" .
The body itself is a series of block8 separated by
commas.
946
Fall Joint Computer Conference, 1968
A block begins with a declaration part and ends
with an expression part.
The declaration part is a series of declarations each
terminated by a ";". This part may be omitted.
The expression part is a series of clauses separated
by "exit" s.
A clause is a series of expressions separated by" ;"s.
Finally, the syntax of an expression corresponds to
conventional usage. Statements such as "go to",
"for", "iJ", compound expression, and the empty
statement are also considered to be expressions.
A compound expression may be used anywhere
a name is legal.
The evaluation of a compound expression
A compound expression (or a program) is evaluated
by serially evaluating its blocks. At most one of
these blocks may have a value, and this value,
if any, is taken as the value of the compound
expression.
A block is evaluated by
(1) Elaborating its declarations, in order. The
scope of a declared name or operator meaning is the smallest block which contains that
declaration.
(2) Evaluating the expression part until the first
"exit" is encountered. The expressions in this
part are evaluated in order except, of course,
any "go to" commands are obeyed. The
value of a block is the value, if any, of the
last expression evaluated in it.
The value of each kind of expression is defined as
follows:
The go to statement and the empty statement
have no value.
A conditional is evaluated in the conventional
wa.y, its value is the value, if any, of the selected
expression.
The value of a "Jor" statement is the series of
values produced by the repeated evaluated of
its scope.
Since the use of an operator is considered to be a call
on one of the procedures associated with it, in all other
cases an expression is nothing but a set of procedure
calls ordered with respect to the precedence of the
operations involved. Its value is the value, if any, returned by the last procedure call.
Procedure calls
A procedure call is written as a procedure-valued ex-
pression followed by a tuple-valued expression. The call
is evaluated in four steps:
1. The tuple expression is evaluated resulting in the
tuple of values, [VI, V2, ••• , v,.J. Note that these
value's may be of any mode including loc modes
and p~oc modes. Thus we may have calls by value,
address or procedure.
2. The procedure expression is evaluated resulting in
the procedure: proc (mtlfl , mt2f2, "', mtnf,,) (E).
3. The parameters are bound. This has the same
effect as replacing the procedure call by the
following compound expression:
(let fl be VI; "'; ; let f" be v,,; E)
4. This compound expression is evaluated.
In order for a procedure call to be legal, the modes of
the values v" must "match" the modes of the dummy
parameters. For the basic modes, the definition of
"match" is the natural one; "match" only becomes
complicated when "union" is involved. The precise
defi~tion follows:
A mode P of an actual parameter "matches" a mode
Q of a dummy parameter (we will write P c Q)if
- P is union (mtl, "', mt n ) and V., mtl C Q
or Q is union (mtl, "', mt,,) and ~" such that
Pc mt.
or P is int, bool, real or char and Q is respectively
int, bool, real or char.
or P is loc mt and Q is loc mt' with mt c mt' and
mt' C mt.
or P is tuple (mtl, "', mt n ) or struct (mtlel, "',
mt"e n ) and Q is respectively tuple (mt/l' "',
mt' n) or struct (mt'lel, "', mt' "e,,) where V", mt"
c mtl.
or P is proc (mtl, ... , mt n ) mt and Q is proc (mt'l, ... ,
mr' ,,) mt' where mr c mt', and V. mtl c mt •.
Some other aspects of BASEL
. Assignment
The infix operator ---+ is used to denote assignment.
The assignment of a value v, of any mode mr, to a
variable V of mode loc mt is written v ---+ V.
The assignment I ---+ J where I and J are both
integer variables (loc int) is meaningless, since both
I and J stand for their meanings, which are addresses. One must write: val I ---+ J, which explicitly
fetches a value from I and stores it in J. In BASEL
there is no automatic built-in mechanism to f,etch
the value of a variable or to do any of the other
transformations performed by the "COERCION"
mechanism of ALGOL-68. Of course, one can
ON the Basis for ELF
freely define extended meanings for "-+" and other
operators, which would make the expression
"1 + 1 -+ I" meaningful.
Allocation
We have already mentioned that the expression a
"mt", where mt is a mode, causes a value of mode mt
to be created. Thus allocation is caused when m is
"loe fir'" . If fir' is in turn a "loc" a second location
is not created. This is a major difference between
loc in BASEL and ref in ALGOL-68 where the
declaration:
ref ref real Y
= ref real 0
causes two locations to be allocated, the first one
pointing to the second one, which in turn can store
areal.
In addition to the block-entry-time allocation
caused by declarations of variables, BASEL also
permits dynamic allocation: if V is a value of mode
fir, then aloe V stores V in a newly created location,
and returns its address as a result. This result, of
course, has mode loc fir.
Using a "union"
With "union", BASEL allows dynamically varying
modes. But in order to use an object of "union"
mode it is often necessary to check the current
status of the mode. This is done with a "when"
conditional expression, defined as follows:
when (name of the object) is fir then El else E2
where fir must "match" the deelared mode mr' of
the object.
In such expression, all uses of the object in El are
treated exactly as if the object's mode were fir rather
than ffit'.
SUMMARY
BASEL derives its simplicity and power from a general
and unifying notion of data objects. Data objects in
BASEL comprise not only the usual integers, reals,
booleans, and character strings, but procedures, pointers, and aggregates as well. Aggregates may be built
out of any objects whatsoever, so that arrays of arrays
and arrays of procedures are but special cases. Similarly,
any object may be pointed at, so that procedure variables and aggregate variables are treated just like
integer variables.
947
This generality in the treatment of objects greatly decreases the number of special constructs which need
appear in the language. Any object may be named using
a declaration, so that separate statement types are not
needed to name procedures, variables, arrays, and
numeric constants (the latter is not allowed in ALGOL60). Similarly, a single parameter passing mechanism
serves to allow call by value, call by address, and call by
name (procedure) for all three are simply BASEL data
objects. Arrays and procedures may be passed to other
procedures as arguments and may be returned by them
as results. Location valued procedures are likewise permitted, allowing the user for example to define new subscripting functions. The left and right sides of an assignment statement may be evaluated using exactly the
same set of rules; the compiler need not distinguish between them.
To enable the wide class of data objects to be used
effectively, BASEL allows the user to extend the
meaning of existing operators as well as to define new
ones. Thus, the user is free to define (or leave undefined)
as he chooses such strange combinations as the concatenation of a teal and an integer or the square root of
a character.
Unlike many other generalized languages, BASEL is
designed to be compiled with as little as possible left to
be interpreted at run time. Efficient compilation
is enabled by the mode information which the programmer specifies (as he is required to in most other higher
level languages). Only when complete mode information
is not known until run time is the type checking done
interpretively (as indeed then it must).
We hope that BASEL has helped to illustrate that
power and generality are not necessarily bought at the
cost of complexity-indeed, careful generalization can
provide power and at the same time make a language
much simpler, both to learn and to implement.
REFERENCES
1 T E CHEATHAM JR
.
The introduction of definitional facilities into higher level
programming languages
Second Edition Proceedings of the AFIPS Fall Joint Computer Conference San Francisco November 1966 Vol 29
Washington DC Spartan 1966 pp 623-637
2 E W DIJKSTRA
Letter to the editor
Communications of the ACM Vol 11 March 1968 pp147-148
3 A E FISCHER P JORRAND
BASEL The base language for an extensible language facility
Mass Computer Associates Inc CA-6806-1311 June 1968
4 R WFLOYD
Syntactic analysis and operator precedence
Journal of the ACM 10 July 1963 pp 316-333
5 J V GARWICK J R BELL L D KRIDER
The GP L language
948
Fall Joint Computer Conference, 1968
Control Data Corporation Palo Alto California Programming
Technical Report TER-05, 1967
6 JVGARWICK
A general purpose language (GPL)
Forsvarets Forskningsinstitut Norwegian Defence Research
Establishment Intern Report 8-32
7 B A GALLER A J PERLIS
A propoealjor definitions in ALGOL
Communications of the ACM Vol 10 April 1967 pp 204-219
8 G F LEONARD J R GOODROE
An environment for an operating system
Proceedings of the ACM 19th National Conference Philadelphia Pennsylvania 1964 New York ACM 1964 pp E2 3-1-E2
3-11
9 PJLANDIN
The next 700 programming languages
Communications of the ACM Vol 9 March 1966 pp 157-166
10 AJPERLIS
The synthesis of algorithmic systems
First ACM Turing Lecture Journal .)f the ACM Vol 14
January 1967 pp 1-9
11 AJPERLIS
Private Communication
12 R M SHAPIRO S WARSHALL
A general purpose table driven compiler
Proceedings of the AFIPS Spring Joint Computer Conference
Washington DC April 1964 Balitmore Spartan 1964 pp 59-65
13 R M SHAPIRO L J ZAND
A description of the compiler generator system
Massachusetts Computer Associates Inc Wakefield Mass
CA-6306-0112 June 1963
14 A VAN WIJNGAARDEN BJ MAILLOUX J E L PECK
A draft proposal for the algorithmic language ALGOL 68
IFIP Working Group 2 1 MR 92 January 1968
15 NWIRTH HWEBER
EULER: A generalization of ALGOL and its formal definition
Part I
Communications of the ACM Vol 9 January 1966 pp 3-9
Part II
Communications of the ACM Vol 9 February 1966 pp 89-99
Associative processing for general purpose
computers through the use of modified memories*
by HAROLD S. STONE
Stanford Research I nstit'l.tte
Menlo Park, California.
INTRODUCTION
permit row-column access. The last section contains an
evaluation of the technique and a summary.
Tbe concept of the content-addressable memory has
been a popular one for studY'in recent years/· 2.3 •4 but
relatively few real systems have used cont~mt-addres
sable memories successfully. This has been partly for
economic reasons-the cost of early designs of contentaddressable memorieR has been very high-and partly
because it is a difficult problem to embed a contentaddressable memory into a processing system to increase system effectiveness for a large class of problems.
In this paper, we describe a relatively inexpensive
modification to the memory access circuitry of a general
purpose computer that will permit it to perform some of
the operations that can be performed in a contentaddressable memory. The major restriction is that the
memory must be a 272D memory.6.6 The modification
resul ts in a new access mode to memory, one which
permits a bit slice from a number of different words in
memory to be accessed. Memory can be viewed as a
collection of N X N arrays of bits such that an access
can be made to either the ith row or the ith column of
an array. Although this capability is somewhat limited
by comparison to the capability of large contentaddressed memories as they are normally conceived, it
is ideally suited to that class of problems that requires
both conventional and associative processing. A good
example of this type of problem is the Gauss-Jordan
algorithm for matrix-inversion which involves a search
through a matrix for the numerically greatest element.
In the next section we further describe the functional
behavior of the modified memory and illustrate its use
through a series of examples. The subject of the third
section is the m()dification of a 272D memory in order to
A880ciative proce88ing with row-column operation8
The functional behavior that is described in this
section is not novel; it was first described nearly a
decade ago. The reason for its resurrection is due to the
ease with which it can be implemented in present technology using techniques described in the next section.
The basic idea is illustrated in Figure 1. Memory is
viewed to be partitioned into multiple arrays of bits,
each of size N X N, where N is a power of two. Memory
accesses can be made in one of two modes, row mode
or column mode. In either mode, a particular array in
memory is selected by the high order bits of an effective
address while the least significant log2 N bits select
either a row or a column. This behavior is essentially
the same as that of the horizontal-vertical computer
described by Shooman.7 •8 Row selection' is equivalent
to word selection in a conventional computer. The
column selection mode has no counterpart in conventional computers and is the mode that supports a
limited form of associative processing.
There is a major difference between Shooman's
vertical-horizontal processor and the idea that is developed in this paper. Shooman conceives of two separate collections of registers and processing logic to be
used in his processor, one for vertical processing and
one for horizontal processing. An implementation of
Shoomar:t's idea is described in Ref. 12. What we describe here uses just one collection of registers and logic.
This characteristic comes about because in the modified memory. all data is transferred between memory
and a common data register for both row and column
operations.
To be more specific, Figure 2 shows an N X N array of
bits and shows the contents of the memory data register
*This research was supported by the Office of Na.val Research
I~ormation Systems Branch, under contract Nonr-4833 (00)
WIth Stanford Research Institute.
949
950
Fall Joint Computer Conference, 1968
BIT-
o
..
I
Let X and Y be the base addresses of two N X N
bit 0, 1 matrices in memory. Then rows of X can be
stored as columns of Y by iterating the instructions
below for different values of the index variables.
2 •.• N-I
RI
EFFECTIVE MEMORY ADDRESS
I I I
-----""---1
SELECTS
AN ARRAY
'-----~
I I
FIGURE I-The logical organization of memory. The mode of
access is determined by the instruction
both after reading the kth column and after reading the
the ith row. Note carefully that rows are placed in the
register such that the first bit, bi,o, is at the left end of
the register and that the first bit of a column, bOok, is
placed at the right end of the register.
To illustrate how row-column accessing is useful for
associative processing, we n~w consider several examples. The notation that is used in the examples needs
a brief explanation. Symbols written in capital letters,
such
X and Y, are symbolic addresses. Subscripted
letters such as Ra denote hardware registers which are
part of a central processor. The symbols "~,, and
"~" denote row and column operations respectively.
Symbolic addresses that are followed by bracketed
symbols such as X[I] denote indexed addresses such
that X[I] is the address obtained by adding the contents
of memory location I to the address of X.
Thus, we have the primitive operations:
as
RI~X;
Y
~RI;
R2~X;
Y[J]
. •1
log2 N bits
- - SELECTS A COLUMN
OR ROW IN ARRAY
Fetch a row and place it in R 1 •
Store RI as a row at address Y.
Fetch a column addressed by X
and store in R 2.
Store the contents of R2 as a
column at address Y.
~
X[I];
~
R1 ;
If I is equal to J and the loop is repeated for I = 1,
2, ... , N, Y will contain a copy of X rotated a quarter
turn. If I = N -J, then Y will contain the transpose of
X where the transpose is taken about the minor diagonal.
To aid in search operations, we introduce the machine
function NORMALIZE. The NORMALIZE instruction left shifts a specified register until a "I" appears.
in the left-most position or until N shifts are performed
if there are no "1"'s in the register. A count of the number of shifts is placed in another designated register.
In our symbolic notation we use the form
to mean that RI is normalized and the shift count is
placed in R2.
As an illustration of the use of the column operation
for searching consider the problem of scanning a status
vector array to find a vector with a "I" in the ith bit
position. The pair of instructions that perform the
search are
RI ~ STATUS [I];
R2
~
NORMALIZE (R 1);
R2 contains N-j where j is the index of a vector with
a "I" bit in the ith position. (For programming convenience it would be wise to implement the NORMALIZE
co~and so that the result left in R2 would be j instead of N-j.)
Now consider the problem of searching an array for a
vector that contains a particular field matching a
specified pattern. The technique that we use is to perform an iterative sequence of column operations on the
pattern field. In the instruction sequence below, register
RI holds the pattern, R2 holds columns fetched from
memory, and Ra holds a 0, 1 vector that contains a 1
bit in a bit position if the corresponding word in the
array has matched the pattern on all preceding operations. The sequence is initialized so that the left-most
bit of the pattern lies in the left-most bit of R 1, and Ra
is initialized to all "1"'s. "NOT" and "AND" are full
register logical operators.
Associative Processing for General Purpose Computers
Fetch the next column of the
pattern;
IF LEFTBIT(R 1) = 0 THEN
R2
Rs
f-
f-
NOT R 2;
Ra AND R 2; l\1ask out bits in Ra that
disagree with pattern for
this iteration.
The sequence of instructions must be repeated for
values of I ranging over the index field. After the final
iteration, Ra contains a "I" in positions that correspond
to words with fields that match the pattern. A NORMALIZE command ci:m be used to obtain the addresses
of words that satisfy the search criterion.
Note that the search procedure effectively looks at
N words but the number of fetches required is equal
to length of the pattern. Hence, for short patterns,
considerably fewer than N memory fetches will serve to
search N words. Patterns that occupy a full word can
be processed about equally well in row mode or in
column mode.
Searches need not be made on "equality" matches.
A slight modification of the instructions above is all
that is required to implement a threshold search. We
use one more register, R 4, that contains "1"s in posititions that correspond to words with fields greater than
the pattern. R 1, R2 and Ra are used as before. R4 is
initialized to all "O"s prior to executing the sequences
below.
R2
~
X[I];
Fetch next column
of the pattern;
951
Sets that satisfy any of the relations" = ", "~", ">",
"~", "<", and "~" can be obtained easily by simple
operations on the vectors in Ra and R 4. "Between
limits" or "outside limits" searches can be done by
using three registers for each limit, i.e., one register to
hold the limit pattern, and two that function as counterparts of Ra and R 4.
A number of other operations are also possible with
row column accessing. Many of these are given in
Shooman7 • The examples given here and in Reference 7
should suffice to illustrate the power of idea. It is appropriate at this point to consider the implementation.
The memory I1wdification
The memory modification can be developed from a
discussion of the functional requirements of row-column
processing and the constraints of conventional memory
technology. We begin by examining the N X N matrix
in Figure 2.
In a conventional memory, the bits in the matrix
are stored so that the columns of the matrix lie on
separate and distinct sense lines of the memory. Because of constraints of conventional memory technology,
during any memory cycle no more than one bit per
sense line can be read or written. For row operations,
selection circuitry activates all bits of a specified row,
each of which lies on a different sense line. The physical
portion of a core memory that is threaded by a sense
line will be called a bit plane in the following material.
For both 2%D and 3D memory organizations, the
entities that we call bit planes correspond to physical
planes of memory stacks, but the correspondence is
usually not true for 2D memories.
For column operations, the technology constraint is
severely restrictive. With physical memory organized
IF LEFTBIT(R 1) = 0 THEN
BEGIN R4
R2
f-
f-
R4 OR (Ra AND R 2 );
NOT R 2;
END;
bO,O
bo,l
b o ,2
bo,N-1
bl,o
b l, I
b l ,2
b l , N-I
b 2 ,o
b 2,1
b 2 ,2
b 2 ,N-1
Ra
f-
Ra AND R 2 ;
.
Rl
f-
LEFTSHIFT(R 1);
.
The statement immediately after the "BEGIN"
updates the vector in R4 such that a word is greater
than the pattern if it had been greater on the previous
iteration or had been equal before and is greater on the
current iteration. At the close of a sequence of iterations of the rrogram steps given above, the vectors in
Ra and R4 uniquely identify all words that are either
equal to the pltttern or greater than the pattern. All of
the remaining words are clearly less than the pattern.
bN-1,o
bN_1,1 b N _ 1,2
K
THE LOGICAL
AYOUT OF
DATA IN MEMORY
bN-1,N-1
DATA APPEARING
IN PROCESSOR
REGISTER
FIGURE 2-The result of fetching a row and a column from an
N X N array
952
Fall Joint Computer Conference, 1968
as shown in Figure 2, columns of arrays will lie wholly
within bit planes, and thus no more than one bit per
column could be accessed during any memory cycle
under the assumed constraint. In order to overcome the
constraints of memory technology, memory can be
organized as shown in Figure 3. Each row in the array
corresponds to a row in the array shown in Figure 2,
but in Figure 3, the matrix is stored such that the ith
row is cyclically shifted to the left by i bit positions.
Careful examination of the figure shows that both rows
and columns of the matrix have the property that
exactly one bit lies in each plane. The bits are scattered
and shifted, however, so that the memory access circuitry must be constructed to take this into account.
Figure 4 shows how row and column selections must
function when data is held in a skewed fashion. In
WORD
~
MEMOR Y P LA NES
I
o
l
~
I
~
+
boo
bOI
b
b ll
b l2
b l3
blO
2
b 22
b 23
b 20
b 21
3
b 33
b 30
b 31
b 32
b
02
03
MEMORY
PLANE INDEX
0
2
3
FIGURE 3-Physicallayout of a 4 X 4 array in memory
o
3
2
o
3
2
Figure 4a, the first row is read into a data register, and
must be cyclically shifted right one bit to place in a
standard format. In general, an operation on the ith
row requires a right cyclical shift of i bits after a read
cycle, and a left cyclical shift of i bits before a write
cycle.
Column operations are somewhat more complex.
Examination of Figure 4b shows that N different words
must be accessed to obtain all of the N bits in one column. Specifically, the memory planes must be able to
support simultaneous selection of bits in different rows.
We shall return to this point later. The planes in Figure
4 are numbered from left to right as 0, N, N-I, ... ,l.
The selection of the ith column is such that the jth
plane must selec,t the bit in word (i+j) mod N. After
access, the word must be cyclically shifted to the right
by N":i-l bits. The skewed storage technique has been
used in the Illiac IV design,9 where Illiac IV memory
modules correspond to bit planes ·here, and full word
operands in Illiac IV correspond to bits.
Thus far, the discu~;sion has been functional in nature.
Now we must take a closer look at memory technology.
Among the conventional memory organizations only
one can easily be adapted to permit aocesses to different
hits in different bit planes. This memory organization
is the so':called "2~D" memory, and its organization is
shown in Figure 5.
In the figure, it is shown that addresses are split into
two components, X and Y, and are separately decoded.
There is a single set of X drivers for all planes, but
there is an individual set of Y drivers for each bit plane.
The several sets of Y drivers act in unison for selection
purposes in the normal mode of operation. It is precisely the mu.ltiplicity of Y drivers that permits the
memory access circuitry to be modified to support the
column mode of operation.
o
2
3
FIGURE 4-Examples of a row and column access to a 4 X 4
array
FIGURE 4a-Access to row 1 followed by a right shift of 1 bit
FIGURE 4b-Access to column 1 followed by 3, right shift of 2
bits
FIGURE 5-The organization of a
2~D
memory system
Associative Processing for General Purpose Computers
::t>-AND
:tr-OR
C:R~~~~~
_______'!'_~RIVERS
,,
BIT PLANE
[---.-_ _--.
A DECODED
WORD ADDRESS
x - DRIVE
LI NES
FIGURE 6-Modifications requirec:. for the ith memory plane.
The modifications are enclosed by the dashed rectangle
For column mode operations, it is necessary to modify
the drive circuitry slightly in order to place independent
control in each plane for the selection of the Y driver to
be energized. The requirements are that each plane
energizes either the driver corresponding to the decoded
Y address (row mode) or the driver corresponding to
the sum of decoded Y address and bit plane index
(column mode).
Since the plane index is fixed for each plane, it is not
necessary to use an adder in each plane to implement
associative access mode. Consider, for example, the
schematic diagram of the memory drive circuitry for a
single bit plane as shown in Figure 6. In this figure, the
X drive lines link all bit planes and effectively select a
particular N X N bit array for interrogration. The Y
drive lines select either a row or a column from the
N X N array. The circuit in Figure 6 is intended to
be identical to that in :figure 5 except for the two level
logic circuit shown in dashed rectangle. *
The two level logic circuit has the following property.
In row mode, signal A is false, and the output of the Y
decoder is fed directly to corresponding drive lines in
the selection matrix. Note that all planes act identically
in ,this condition, so that each plane returns a bit from
the same word address. When signal A is true, the output of the Y decoder is displaced cyclically by an
amount i in the ith plane. Thus, each plane reports a
bit that belongs to a different word of the N X N
array, and in fact reports the bit indicated by Figure 4.
The signal displacement in column mode i~ "endaround." That is, if the decoded address is the jth
address, then line (i + j). mod N will be activated in the
ith plane.
953
In terms of logic circuitry, the two level circuit
shown in Figure 6 is the only modification that is
necessary for the access circuitry.
One possible adverse effect of the two level logic
circuit is a small increase 'in the total memory cycle
time. This increase is expected to be less than one percent in magnetic storage technologies, and is likely to
be more than balanced by an increase in memory
effectiveness. However, in newer technologies, such as
integrated circuit memories, the increase in cycle time
may be somewhat larger.
We turn our attention now to the problem of cyclica1ly shifting data prior to entry to the memory and
after retrieval from memory. The two shifts are called
preshifts and postshifts, respectively. To solve the
shifting problem note that the amount of a preshift or
a postshift can be derived from the mode and the
effective memory address. Let the least significant log2
N bits of an effective address be called the s index.
(s for shift). Then, the shift direction and amount is
given by the table below.
TABLE I
Mode
row
column
Preshift amount
s bits left
N - s - 1 bits left
Postshijt amount
s bits right
N - s - 1 bits right
Note that the value of N-s-l can be computed by taking
the l's complement of s in a register with log2 N bits.
Consequently, it is extremely. simple to compute the
shift amount because it is equal to the lower address
bits in row mode or the 1's complement of these bits in
column mode.
A good candidate for the shift circuit is the barrel
shifter shown in Figure 7. Shifters of this type have been
SHI FT AMOUNT
ith BIT OF
SHIFT AMOUNT
T
2 i+1 E
APAf
1
*Actually, X and Y axis selection circuits of 2%D memories
are more complex than is indicated in Figures 5 and 6. In most
implementations, the Y address lines are partitioned into two sets
~hich are separately deco.ded. The decoder outputs are connected
In a cross-bar arrangement and the Y lines that thread cores are
~ocat~d at the crosspoints. The modifications shown in Figure 6
IS easIly adapted to the cross-bar method of selection.
FIGURE 7-A barrel shift register with a detailed view of a
typical cell
954
Fall Joint Computer
Confer~nce,
1968
implemented in several commercial computers. A
shifter with log2 N stages can cyclically shift N bit
words by any amount from 0 to N-l. Each stage shifts
either 0 or 2 i bits depending on the ith bit in the binary
representation of the shift amount. For our purposes,
it is most likely that two shifters are needed, one for
postshifting -and one for preshifting. The two shifters
should be placed on the data paths between memory
and processor, and not between the memory data register and the memory. The reason for the placement on
the data paths is that there is ,a possibility for overlapping the shift operation ,with other operations,
whereas if the shifters were phiced bet~en data register and drivers or sense amplifiers, the effect would be
to increase the memory cycle:
A good example of masking the effect of shifting
time through overlap of· operations occurs for write
cycles. Normally, write cycles are preceded by clear
cycles to clear memory in thebit positions that are to
receive new data. The clear cycle can proceed as soon
as an address is available. While the clear cycle is
active, data can be shifted into the proper format and
be ready for storage when the write cycle begins. Postshifting after read cycles will tend to increase the time
. required to access data but it will not increase the
memory cycle time.
The barrel shifters thus are used to translate between
a standard data format for the processor and one of N
different storage formats. Because data within the processor are held in a standardized form, manipulation of
data within the processor can be done in conventional
ways. Conventional load and store commands can be
issued from the central processor without regard for
the fact that data might be cyclically rotated during
the transfer. In essence, the physical form of data storage is completely invisible to the processor.
What has been gained, of course, with the barrel
shifter, the modified memory, and the modified storage
format, is the capability for performing associative
operations in a general purpose computer. The net cost
of the memory modification is two-barrel shift registers,
and some logic in the Y address circuitry. The cost is
undoubtedly a small fraction of the cost of the memory
and processor. There may be some impairment of performance because of increased access time, but this is
unlikely to be significant because the delays through a
microelectronic barrel shift register are very small
compared to the cycle time of a core memory.
SUMMARY AND CONCLUSIONS
The performance benefits to be derived from rowcolumn addressing depend greatly on the effectiveness
of column mode operations in reducing the number of
nlemoryaccesses. The greatest benefit of column mode
addressing is for those operations in which a small
. portion of a large number of words in memory must be
accessed. Scaling and magnitude searches fall iIi this
category. Take, for example, IBM System/360 long
floating point words with 7-bit exponents and 56-bit
mantissas. Scaling and magnitude searches over 64word groups can be done with approximately eight
accesses by accessing the exponent field of the groups in
column mode. This is essentially how one would conduct the search for a pivot element in a Gauss-Jordan
reduction.
Since the word-length effectively determines the
number of different words that are accessed in a column
operation, it is desirable to have as large a word length
as possible. In present technology, it is feasible to
implement memories with up to 64 or 128 bits/word.
It appears that reasonably good performance improvement is possible with 64-bit words, so that a useful
implementation of row-column accessing is possible
within present technology.
Some analysis is required to determine the utility
of column accessing for common operations such as
symbol table searching and sorting. Hash-addressing
used in combination with column mode access is one
possible method for performing table searching. Hashaddressing normally involves a search when conflicts
occur10 ,11 and this search might be speeded with column
access. The biggest improvement would come when
tables are nearly full, at which time there is a high
probability that a search will take place after the
eomputation of the hash-code.
Ultimately, the performance improvement to be
derived from the techniques that have been described in
this paper are determined by the applications. While
we cannot predict what benefits might accrue at this
time, the fact that row-column accessing can probably
be achieved for little cost within present technology
indicates that the benefits of an implementation of the
technique will almost certainly outweigh the cost of
implementation.
REFERENCES
1 AKAPLAN
A 8earch memory 8ub8y8tem for a general purp08e computer
AFIPS Proc of the 1963 FJCC Vol 24 Spartan Books Balti-.
more Md pp 193-200
2 RGEWING PM DAVIES
A n associative proce88or
AFIPS Proc of the 1964 FJCC Vol 26 Spartan Books Baltimore Md pp 147-158
3 B T McKEEVER
The associative memory 8tructure
AFIPS Proc of the 1965 FJCC Vol 27 Part 1 Spartan Books
Baltimore Md pp 371-388
4 AGHANLON
Associative Processing for General Purpose Computers
5
6
7
8
Content-addressable and associative memory systems--a survey
IEEE TEC Vol EC-15 No 4 pp 509-521 August 1966
T J GILLIGAN
2-1/2D high speed memory systems-past present and future
IEEE TEC Vol EC-15 No 4 pp 475--485 August 1966
JRBROWN JR
First and second order ferrite memory core characteristics and
their relationship to system performance
IEEE TEC VOL EC-15 No 4 pp 485-501 August 1966
WSHOOMAN
Parallel computing with vertical data
Proceedings of the EJCC V0118 december 1960
WSHOOMAN
Orthogonal computer
955
US Patent 3 277 449 October 4 1966
9 D L SLOTNICK
Unconventional systems
AFIPS Proc of the 1967 SJCCThompsonBookCo Washingt.on
DC pp 477--481
10 WDMAURER
An improved hash code for scatter storage
CACM Volume 11 Number 1 pp 35-38 January 1968
11 RMORRIS
Scatter storage techniques·
CACM Volume 11 Number 1 pp 38-43 January 1968
12 P A HARDING M W ROLUND
A 2-1/2 D core search memory
Fall Joint Computer Conferencp Decemb(3r 1968
Addressing patterns and memory handling algorithms
by SHERRY S. SISSON* and
MICHAEL J. FLYNN**
Northwestern University
Evanston, Illinois
INTRODUCTION
One of the principal problems facing the designer
of a high performance computer system is the
efficient handling of memory. In arranging a
lnemory system the designer, lacking knowledge
of the programs to be run, usually selects "worst
case" assumptions concerning addressing patterns. This paper is an attempt to compare a set
of selected disparate programs and analyze their
actual addressing traces with respect to the various memory algorithms.
In hig.h performance systems an increase in the
bandwidth* of memory must be achieved to insure an ample supply of instructions and operands
to the central processing unit. More efficient program storage organizations are needed to decrease
effective memory access time to a time compatible
with the process'or cycle time.
Three methods by which storage bandwidth can
be improved are: (1) making use of a high speed
immediate storage by transferring blocks of words
between local and main storage as required (variations of this method have been called paging),
(2) interleaving independent memory units in
order to obtain a faster effective access time, and
(3) using a high speed virtual memory (lookahead unit) .in the central processing unit in order
to obtain. an optimum instruction or data flow.
This method anticipates the actual information
requirements of the system.
*Present Address: Bell Telephone Laboratories
Naperville, Illinois 60540
**Author's time' supported in part by U.S. Atomic Energy
Commission, Argoune National Laboratory, Argoune, Illinois
The purpose of this project is to evaluate these
system organizations by studying recorded address traces of executed programs. Blocking, interleaving, and looking ahead configurations were
evaluated and compared with similar results presented in the literature. This work was done in
two parts.
.
1. The first step was to write a simulator which
chronologically recorded on tape storage demands requested by a test program as this
program was being executed. This simulator was then used to generate addressing
pattern tapes of three representative test
programs. The memory requests of each. test
program were written on tape in the order
used by the program and were flagged to
indicate whether they were data or instruction requests.
2. The second step consisted of statistical
analysis of the data. This study was done by
adapting various program organizations to
the data generated by Part 1. Three statistical programs were written. All of them
gathered information for: a) the instruction stream** b) the data stream c) instruction and data stream combined. These
statistical programs determined the frequency of run lengths, number of jumps
within a look-ahead unit for various level
sizes, and the interference occurring for
various interleaving configurations.
The results of the data analysis can be used to
give an indication as to how blocking, interleaving, and look-ahead organizations improve the
speed of execution of actual programs. First, a.
**Stream is defined to be a sequence of data or instructions as
seen by the machine during the execution of a program.1i
*Storage bandwidth is the retrieval rate of words from memory.'
957
Fall Joint Computer Conference, 1968
958
DATA BUS
M,2M
i,i+M
1,HM
REQUEST BUS
I1
MEMORY CYCLE
b
...
I
ACCESS rEGENERATION,
1
NUMBER OF
REQUESTS PER
MEMORY CYCLE
NUMBER OF MEMORY UNITS, M
BANDWIDTH =NUMBER OF REQUESTS PER MEMORY CYCLE
FIGURE 1
general review of program storage organizations
will be presented, followed by descriptions of the
simulator, test programs, and analysis programs.
The final sections present the results of the adaptions of program storage organizations to the test
program address traces, and conclusions.
Organization of storage (memory) systems
Concept of interleaved storage
The concept of interleaved storage is developed
from the idea of using M independent memory
units instead of one main memory. The words of
a program and its data are distributed successively
among the memories modulo M such that memory
1 contains addresses 1, 1 + M, 1 + 2M, etc., as
shown in Figure 1. By increasing M for a given
computer, the memory bandwidth is increased because the number of accessing conflicts is decreased. Recall that bandwidth is the service rate
of the main memory. This bandwidth must process fetching of instructions and operands, storage
of results, and input/output demands.
In his paper, Flores4 studied the limiting effect
of the number of memory banks on computer response time and developed an equation relating
a waiting time factor to relative memory cycle
time based on a queuing model. His work was
based on the assumption that the demands are independent of response; therefore, the demand
distribution is stationary. As a result, the probability of the arrival of a demand request in a
small fixed time interval is the same as any other
period. Only the worst case condition of random
TIlemory addressing was considered. In reality,
programs ,execute demands somewhere between
the extremes of sequential and random. The interleaving results of this project used actual program addressing patterns. From these results,
one can get an idea as to the effect of the assumption of random storage demand. The results are
presented and contrasted with Flores' predicted
results.
Blocking and look-ahead design
Gibson's block-oriented system
LARGE
MAIN MEMORY
1
PAGE
LOCAL STORAGE
CPU
FIGURE 2
Another approach to the bandwidth problem is
a block-oriented design presented by Gibson.6 He
proposed a block storage method where a request
to main memory moves a block of words to a local
store. Statistical results are presented on how
big a block should· be and what the size of local
storage should be. Of course, the optimum configuration at -anyone time depends on· the program being executed; thus, one must find an overall best configuration for the system.
Gibson's simUlations results show that for a
local storage size of 2048 words the number of
accesses to main storage is relatively independent
of the block size. This result indicates that the
block size should be kept as small as possible. If
large blocks are used, then the local store size
Addressing Patterns and Memory Handling Algorithms
should be increased in order to get good performance compared to conventional storage. The
local storage replacement algorithm used does
have some effect on the usefulness of local storage,
while the size of the program being executed has
little effect 'On local storage characteristics. As a
reference the paging results of this project will be
compared to Gibson's block storage results.
959
ADDRESS TAPE FORMAT
THE TAPES CONTAIN BINARY RECORDS, 24 WORDS PER
RECORD.
THE ADDRESSES ARE WRITTEN ON TAPE IN ORDER OF
USE DURING EXECUTION OF THE TEST PROGRAM
RECORD FORMAT:
Look-ahead systems
Look-ahead systems are employed in large-scale
computers in order to increase program execution
speed and to sm'Ooth fluctuations in memory demand. The Stretch3 system included a look-ahead
unit in its design for these reasons. Other systems incorporating a look-ahead feature are the
IBM System 360 Model 9P· and CDC 6600.
Look-ahead, as the name implies, is anticipatory
in nature unlike the block transfer method which
operates 'On demand. Instruction look-ahead is
counter driven by the expectation of instructions
to lie in a strict sequence. Data look-ahead is
driven by the expected instruction stream. Figure
3 shows the types of look-ahead units that were
applied to the address traces. A comparison of
the performance of these look-ahead models will
be presented as part of the results.
Simulator description
SimuIatorprogram description
INSTRUCTION
FORWARD
LOOK- AHEAD
BACKWARD CENTERED
T
ALGO- CONTENTS CONTENTS CONTENTS
RITHM
OF
OF*+I
OF*-I
TO*+N TO *-N *±1- N
* =PRESENT
VALUE
*
CONTENTS
OF
LOOK-AHEAD
1
N INSTRUCTION
'--_....,j
REGISTERS
INSTRUCTION COUNTER
INSTRUCTION Rt.GISTER
*
DATA LOOK-AHEAD
INSTRUCTION
LOOK-AHEAD
REGISTERS
T: I
•
••
••
C(l()
• I
N
1
••
I
~
C(B)
C(oc.)
It
'"
I
DATA
LOOK-AHEAD
REGISTERS
N
1
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FIGURE 3
WORD 1
•
•
•
•
•
•
•••
WORD 24
S 1
D
I
17 18
ADDRESS
•
•
•
•
•
••
•
•
•
•
••
••
•
•
•
01
35
/0 ----------0
•
••
•
••
•
•
•
= 1 I F ADDRESS IS IN DATA STREAM
= 0 IF ADDRESS IS IN INSTRUCTION STREAM
FIGURE 4
This program was written in FAP, the IBM
7094 assembly language, for the purpose of monitoring the execution of other F AP programs. The
simulator keeps an instruction location counter
for the test program being monitored. This location counter is used by the simulator to read the
next instruction of the test program and record
the location on tape. If an instruction requires an
operand, the absolute address of the operand is
recorded 'On tape following the instruction address.
Any index modification of the operand is done
before recording the address. One level of indirect addressing can be handled, with all absolute
addresses requested during the indirect addressing process recorded on tape. These addresses are
written on tape in the order requested by the test·
program and are flagged to indicate whether it
was an instruction stream or data stream address.
'The format of the tapes is shoWll.in Figure 4.
Some difficulties were encountered in writing
the simulator. The execute command (XEC) was
used to run a test program under control of the
simulator. The maj'Or problem with this method
of control is that when XEC executes a transfer,
the simulator loses control to the transferred location. This problem was partly solved in the following manner: Before executi'On of a transfer,
the simulator inserts at the transferred location
a transfer to a location in the simulator program
and sets a flag to indicate that this was a transfer
960
Fall Join.t Computer Conference, 1968
operation. After execution of the transfer instruction (conditional or unconditional), the simulator, replaces the original instruction into the
test program. If the transfer was taken, the instruction location counter is updated to the transferred location. This method works except when
control is transferred to a protected area in core
during an input/output sequence.
The input/output problem was resolved by placing any test program I/O code in the simulator
B,nd placing an unconditional transfer to this code
in the appropriate test program location~ As the
simulator is executing the test program, it looks
for a transfer to I/O code before executing an
instruction. When it finds one, the I/O code is
executed. The simulator then reads the next instruction of the test program and continues execution. Because the simulator performs the I/O,
no addresses used during I/O execution are recorded on tape.
'l'est program descriptions
This simulator was used to simulate and record the accessing patterns of three test programs.
In an attempt to get a representative sample of
patterns, programs with varied characteristics
were run.
Differential equation solution
The first program was an iteration problem
which solved the Van der Pol differential equation
using Hamming's method. The Van der Pol equation,
is used to describe non-oscillatory systems. Input
parameters were given to the program for e,
h, and the first four x and y points. The next 96
points were calculated using the input parameters
and Hamming's predictor-corrector equations (see
Ralston 7 p. 189) :
Predictor: yo n4-1 = Yn-3
+
+
2y' n-2)
+ (3h/8) (y n+l)' + 2y' n -
y' n-l)
(4h/3) (2y' n - y' n-l
'+1
Corrector: Yn+! = (1/8) (9Yn - Yn-2)
i
'Where: YOn+! is the estimated initial value of y n+1,
y' n
i~
yin
i:-: the ith approximation to Yn+l.
the derivative of y 11,
The corrector formula was reapplied at each point
until the change was less than 0.0001. Each x,y
point plus the number of times the corrector was
applied at each step were printed at the end of the
program. This program passed through a few distinctive loops many times as each new point was
predicted and the corrector formula applied. The
simulation of this program caused 83856 accessing
requests to be recorded on tape.
I>ata processUng problemm
A data processing program was run as the second test program. D'ata cards are initially read
and stored sequentially in storage. Each card
contains an employee name (last name first), number, and codes indicating marital status and sex.
After all the cards are read into storage, the following steps are performed.
1. The cards are sorted
SQ that the employee
numbers are ~n ascending order.
2. The input information is used to prefix each
employee name by MR., MRS., or MISS.
Each prefixed name is reversed to last name
last before going to the next employee name.
Several logical and shift commands were
user to prefix and reverse a name and place
it left adj usted in storage.
3. Any leading zeroes on the employee number
are replaced with blanks.
4. The employee names, each with the proper
prefix and followed by the employee's number, are printed in numerical order.
When executed by the simulator, this program
requested 190608 accesses to main storage.
Machine simulation
The last· test program was a program which
simulated the language of a nonexistent machine
on the IBM 7094. It interpreted control cards ·and
simulated the instructions of the nonexistent machine. The main program read and interpreted
the control cards which included such commands
as IDMP, LOADER, PRINT, SNAP, and START.
After the START control card was read, the program transferred to a decoding routine which
read and decoded the instructions of the nonexistent machine. Each instruction was simulated by
Addressing Patterns and Memory Handling Algorithms
a oommand subroutine. A very small program.,
consisting of a few control cards and instructions,
was written in this new language for the test program to simulate. The test program requested
1392 addresses when it was executed, enough to
get an idea of the characteristics of this program.
There was more input/output in this program
than in the other two test programs. Recall that
memory requests in an input/output section of
code are not recorded by the simulator, thus a portion of the test program access pattern is not considered in the program analysis.
Analysis program descriptions
When executed, the following programs made
three passes of an address tape, one for each of
the three addressing streams.
Run length program
The first program written recor,ded run length
information. A run length is defined as the number of addresses increasing in value by one over
the previous address in an addressing pattern.
When an address breaks the sequential pattern,
this address is taken as the start of a new run
length. A table is printed showing the run lengths
that occurred in the program and the number of
times each run length occurred. Also recorded are
the total number of instruction, data, and combined stream references used by the test program. This information can give an idea of the
size and number of loops occurring in a program,
and of the sequential nature 'Of a program.
Blocking and look-ahead program
Blocking and look-ahead characteristics were
obtained by the second analysis program. The
program as written with the assumption that
only one page can reside in local memory (readily
available to the processor) at a time. For a given
page size, the number of new pages requested by
a test program is printed. Along with the page
count, the number 'Of addresses used by a test program assuming single word access is printed. It
should be noted that the blocking analysis program considered accesses to memory, not distinguishing between fetches and stores. The lookahead section looked f'Or three situations for a
given number of levels (N).
961
1. It considered that N levels followed the cur-
rent address (forward look-ahead).
2. N was considered to be the number of se-
quential addresses preceding the current address (backward look-ahead).
3. The levels were considered to be centered
with N/2 addresses preceding the current
address and N/2 following.
The analysis program printed the total number
of jumps occurring within N for each situation
(forward, backward, and centered). The blocking
and lo'Ok-ahead data were collected first on the
combined stream and then on the instruction
stream and data stream separately.
Interlea,ved storage program
The last program tabulated information on interleaved storage. It required three input parameters, relative memory cycle time, relative processor cycle time, and the number of memory banks
used. Several items were tabulated for each· set
'Of input parameters, including the f'Ollowing.
1 A count was made of the number of inter-
2.
3.
4.
5.
ferences that 'Occurred. An interference
occurs when service is requested of a memory bank which is still busy with a previous
request.
The total wait time due to memory bank interference was recorded; the wait time being
the total time in cpu cycles that the cpu had
to wait because the requested memory bank
was busy.
The total processing time was tabulated.
This time included one cpu cycle for each
memory access plus the wait time.
The number of accesses to memory was
printed.
The occupancy ratio (busy ratio divided by
the number of banks) was calculated. The
busy ratio is the ratio of memory cycle time
to process'Or request rate.
Increasing the number of banks for a given.
relative memory cycle time proportionately .. decreased the occupancy:ratio. Results were obtained on: all three .addressing . streams. When the
instruction stream was used alone, the data
stream and any of its effects on processing time
were ignored. Theref'Ore,. the results are worst
case interference' figures for' the given relative
processor and memory cycle times.
962
Fall Joint Computer Conference, 1968
100
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6
8
10
RUN LENGTH. WORDS
FIGURE 6
20
30
40
RUN LENGTH, WORDS
50
60
FIGURE 5
100
U)
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Re8ults
au
90
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c
Run length results
The .run length results in Figures 5 - 7 show the
sequential nature of the three addressing streams
fore each test program. They are a plot of the
percentage of addresses which are of a given run
length size or less. The figures show the worst
and best case range of results. From observation
of these figures, one can see that the instruction
stream run lengths are significantly longer than
either the data. or combined stream run lengths.
Because a run length is a number of sequential
addresses, this longer run length of the instruction
stream indicates that the instruction stream is
more sequential than either the data or combined
streams. The difference is more marked in program 1 where the mean instruction stream run
length is 14.4 words white the data and combined
stream mean run lengths are. just over 1 word.
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6
LE~GTH.WORDS
FIGURE 7
8
10
Addressing Patterns and Memory Handling Algorithms
The wide range of instruction stream run lengths
generated by program 1 and 2 is reflected by their
large standard deviations of 13.7 and 8.8, respectively.
100
MEAN RUN LENGTH, WORDS
80
COMB
INST
DATA
1.08
1.09
1.33
14.44
4.52
3.78
1.05
1.04
1.38
TEST PROGRAM 1
TEST PROGRAM 2
TEST PROGRAM 3
,
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::::)
~
CENTERED
\
~
560
(I)
&.J
RUN LENGTH VARIANCE
(STAN pARD DEVIATION IN PARENTHESES)
COMB
TEST PROGRAM 1
TEST PROGRAM 2
TEST PROGRAM 3
INST
0.08(0.29) 187.5(13.7)
0.13(0.37) 77.1( 8.8)
0.73(0.86) 13.7( 3.7)
DATA
0.07(0.27)
0.09(0.30)
0.39(0.63)
~
\
\
\---.
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a::
w
~
a::
... 40
z
w
(.)
'
....
....... ~FORWARD
-~
CENTERED
20
FULL
CENTERED ONLY
OL-----~----~----r_----r_--~r_--~~
o
4
2
16
8
32
FIGURE 8
Results in Figure 8 depict the probability of an
instruction reference to a point outside a lookahead unit for a given size. The best and worst
case results for each look-ahead model are plotted.
Results were also obtained on instruction stream
...z
::::)
w
0
j!?
a
(I)
w
z
Another way to observe the sequential nature
of program accessing patterns is to investigate its
branching characteristics. A look-ahead unit anticipates the sequential nature of the instruction
stream alone. An instruction operand· is obtained
from memory as a part of the look-ahead process
and is saved along with the instruction at a single
level of the unit. One problem with a look-ahead
unit is that its effectiveness is diminished when
a program branches to a location outside the unit.
64
NUMBER OF LEVELS IN A UNIT
(.)
Look-ahead results
"'~
a::
~
TABLE 1
For all three programs, the data run lengths
are short with means ranging from only 1.04 to
1.40 words. This almost random referencing of
data is primarily due to the initial data layout.
For example, program 1 sequenced through large
tables; but in between referencing a location in
the table, constants and temporary storage locations were referenced~ Perhaps the single data
stream should be considered as two streams, one
referencing the tables, and another referencing
constants and temporary storage locations. The
short combined stream runs strongly reflect the
data characteristics.
In general, one can observe from these figures
that the instruction stream is significantly more
sequential than either the data or combined
stream. This difference gives an indication that
the instruction and data streams should be treated
as separate memory areas in a computer organization.
BACKWARD
RANGES,tr-_.......~_-A
...z
963
w
a::
w
La..
w
a::
...z
w
(.)
a:: 20
w
Q.
0
0
2
4
8
16
NUMBER OF LEVELS IN A UNIT
FIGURE 9
32
964
Fall Joint Computer Conference, 1968
branching to instructions just previously executed
(backward look-ahead) and on branching to instructions in both the forw~rd and backward direction. For all test programs the three different
look-ahead configurations are plotted on the same
figure so that the configurations may be compared.
Similar results are also plotted for the data stream
in Figure 9.
100
Inst~uction stream
Test program 1 demonstrates the best lookahead characteristics because of its highly sequential accessing pattern. For any of the lookahead configurations, program 1 had a" probability
of less than 0.07 of not finding any given instruction within the look-ahead. However, this program was also the least sensitive to look-ahead size
with the probability of not finding a given instruction within the unit decreasing by only 0.01 up
through the 64 level unit size.
The most significant improvement in the probability of finding a reference within a unit came
when expanding from 2 to 4 levels for the forward
and backward cases. For example, for the best
forward unit results the probability of a branch
instruction transferring out of 4 forward levels
is 0.54, down 0.23 from 2 levels. The same probability at 4 levels in the backward unit was somewhat higher at 0.78, down 0.17 from 2 levels.
Each level plotted" on the centered look-ahead
reflects the combination of the forward and backward results of the next lower level. The branching improvement decreases rapidly for the first 8
levels, then decreases more slowly for the rest 'Of
the range.
Branching conclusions
Based on" the results in Figure 8, a centered
unit would be most desirable, but this configuration may also be the most difficult to implement.
A" unit of at least 8. levels is needed before the
centered look-ahead performs any better than the
forward configuration. If a smaller unit were required, then the forward look-ahead would provide the best performance. A timing simulation
study was made for the Stretch computer to get
information as to the effect of a forward lookahead unit on relative program execution speed. 8
The Stretch results indicate that the biggest improvement in speed came when expanding to 4
levels. The same characteristic is displayed by the
ffi
~
20
1&1
CL
10
*512-WORO
&....JCOMBINEO STREAM*
LOCAL S'roRAGE
~
o
- ...... -...t-.-
o
2
4
8
~
~
M
128
2S6
BlOCK SIZE • WORDS
FIGURE 10
test program branching patterns. This comparison indicates that program branching behavior is
a direct indication of look-ahead applicability.
Blocking results
Another method for improving program execution speed is by use of blocking techniques. The
first results were obtained by the paging analysis
program with the assumption of 'Only a one-page
local storage. From previous observations of the
run length curves, one would expect paging to be
most applicable to the more sequential instruction
stream. Figure 10 reveals, as expected, that the
instruction stream always has a smaller probabil;.
ity of not finding a word in local storage than
either of the other streams. It takes only a 4-word
page to bring the instruction stream probability
down, to less than 0.5 while the data stream needs
a 32-word page to achieve the same performance.
A 64-word page brings the probability of not finding an instruction reference down to less than 0.1.
However, at this large size, the number of references made to local storage represents a small
fraction of the number of words transferred to
local storage. A large number" of words are now
being transferred from main memory to local
Addressing Patterns and Memory Handling Algorithms
8.0
8.0
6.0
5.0
6.0
5.0
4.0
4.0
~ 3.0
3.0
~
~ 2.0
2.0
...en
@
z
li-
......
~
~
~ 1.0
2
i=
.8
~
.6
.5
ALL PROGRAMS
0
....
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~ 1.0
~
~
~
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MODEL 91 SIMULATION
c:(
8\
i= .8
(!)
~12
(.)
.6
.5
----------------------------ACTUAL TRACE
.4
4
~3
.2
O~----_r------~----~------------~
48
o
16
32
.1
INTERLEAVING
.6
.8
OCCUPANCY RATIO
NUMBER OF REQUESTS PER MEMORY CYCLE,TM)
(
.NUMBER OF MEMORY UNrTS
FIGURE 13
data stream causes the greater blocking times.
One way to make the data stream wait times more
compatible with those of the instruction stream
would be to separate the data stream into three
operand areas as enumerated in the previous section.
Flores' curve, shown in the figures for comparison purposes, was derived from an open loop
queuing model assuming a uniform random accessing pattern. It should be used only as a limiting factor in considering program execution
speeds and not for determining the optimum waiting time for a system. Comparison of the test program addressing patterns with Flores' random
accessing pattern reveals that fewer banks are
needed to obtain a reasonably low memQry waiting
time for the test program patterns. With an occupancy ratio of 0.5, the average waiting time is
less than one-half of the wait with random accessing. Increasing the occupancy ratio to 1.0
causes an insignificant increase in the waiting
time of the test program addressing patterns as
FACTOR
FIGURE 4
1.0
compared to Flores' curve. It should be noted that
the test program waiting times are slightly optimistic because interferences generated by input/
output sequences were not included in the accessing pattern.
The relative improvement of the accessing rate
that occurs as· interleaving and memory speed are
improved· can be demonstrated in another manner.
Figure 14 depicts the average access time in cpu
cycles as a function of interleaving. Notice that
the amount of interleaving yields an exponentially diminishing improvement. Similar results
were obtained from a simulation of the IBM System 360 Model 91 storage system. 2 The Model 91
simulation also used a random addressing pattern,
which resulted in longer average access times than
those· of the test programs.
CONCLUSION
The objective in the design of a general-purpose
computer is a system which executes' programs as
fast as possible, and is technically and economically feasible. The analysis of dynamic address traces
provides a quantitative measure of system performance which can be used to guide computer
system design. This project examined program
accessing patterns, looking for characteristics
Addressing Patterns and Memory Handling Algorithms
which would lead to more efficient storage utilization by programs. Final evaluation of the optimum method of organization depends on hardware
costs for the various configurations which were
not considered in this study.
The major methods of organization are blocking, interleaved storage, and look-ahead. Results
indicate that separation of the instruction and
data streams improves program performance.
The results of a one-page local storage show that
the test program performance is much improved
wi th a page size of 4 or more words. However,
the results presented using a larger local storage
reveal that performance is improved by more than
an order of magnitude when more than one page
is saved in local storage. Interleaved storage performance is good with the combined stream, but
could be significantly improved by using separate
streams. Reasonably low access waiting times are
produced by using enough memory units to offset
the ratio of memory to processor cycle times.
A look-ahead unit would be more applicable to
an interleaved storage organization than an organization with local storage. A centered lookahead handles program branching more efficiently
than the other configurations at a size of 8 or more
967
levels. If a smaller look-ahead is to be considered
for a system, a forward look-ahead would provide
the best performance.
REFERENCES
1 D W ANDERSON F J SPARACIO
R M TANASULO
The M odel91 : Machine philosophy and instruction handling
IBM J Res and Dev January 1967
2 L J BOLAND G D GRANITO A M MARCOTTE
B U MESSINA J W SMITH
The model 91 storage system
IBM J Res and Dev January 1967
3 W BUCHHOLZ Ed
Planning a computer system
New York McGraw-Hi1l1962
4 I FLORES
Derivation of a waiting time factor for a multiple band merrwry
JACM VollI pp 265-282 July 1964
5 MJFLYNN
Very high-speed computing systems
Proc IEEE Dec 1966 pp 1901-1909
6 DGIBSON
Considerations in block-oriented systems design
AFIPS Conf Proc Vol 30 pp 75-80
7 ARALSTON
A first course in numerical analysis
New York McGraw-Hi1l1965
8 SSISSON
Statistical analysis oj computer accessing SY8tems
Thesis for the MSEE degree Electrical Engr Dept Northwestern Univ Evanston Illinois June 1968
Design of a IOO-nanosecond read-cycle NDRO
plated-wire memory
by TAKASHI ISHIDATE
Nippon Electric Co., Ltd.,
Kawasaki, Japan
INTRODUCTION
Disadvantages:
Plated-wire memories are now attaining a promising
position in main memories. UNIVAC claims that, in the
non-destructive readout (NDRO), the cost of peripheral
circuit can be reduced, since peripheral circuits are useful enough to maintain multiple words. However, the
NDRO is most effective only for slower memories with
a comparatively small number of interface bits. Themain
memories such as 72-bit-per-word 100-nsec read-cycle
memory system cannot be improved by the use of the
NDRO as recommended by UNIVAC.
This paper deals with the best use of the NDRO
techniques in the high speed operation of memory system.
(1) The output signal level obtained by NDRO mode is
generally lower than that obtained by DRO mode,
because, in the NDRO operation, the readout word
field is kept considerably below the amplitude
which brings the magnetic vectors along the hard
axis of thin magnetic films. Low output signals
make the sense circuit more complicated.
(2) When the thin film is operated by NDRO mode, the
domain wall is apt to creep, and the yield of good
plated wires fall, thus increasing the cost of memoryplanes.
(3) The read cycle time of NDRO is short. But the time
required to write information increases due to the
limited word current for writing.
(4) The difference between read cycle time and write
cycle time is not favorable to the control unit of a
processor to access the memory.
Reasonsfor adopting NDRO
The advantage and disadvantage of NDRO opera.
tion of plated -wire memory are as follows.
Advantages:
(1) The NDRO memory is more reliable as compared
with the DRO memory agaihst temporary errors.
In the :ORO memory, stored information will he
definitely destroyed, if the readout signal is detected in the wrong sense or if there is any malfunction in the recirculation loop.
(2) The read cycle time is short. There is neither re·
write time nor recovery time of digit noises in the
NDRO memory.
(3) If the word current for writing is compatible with
that for reading, we can store information exclusively' into desired bits of a word, while reading the
remaining bits. This gives rise to efficient use of the
memory.
(4) From the similarity between NDRO memory and
electronically changeable read-only memory
(ROM), most of the NDRO techinques can be uti
lized in R01VI.
Design objectives
The following items were selected for the design,
anticipating the demand of performance characteristics
in the 1970's.
(1) Unit capacity of the memory is 16,384 words of 72
bits each.
(2) The memory must have a read cycle time of 100
nanoseconds, a read access time of 70 nanoseconds,
and a write cycle time of 200 nanoseconds.
(3) Input .and output signal levels must be compatible
with those of CMLs.
Timing
The time should be determined for each functional
block before the detail system design is given. The
timing waveforms are shown in Figure 1.
Read operation is repeated at a rate of 10 M cycles
969
970
Fall Joint Computer Conference, 1968
Digit current consists of a pair of pulses, one positive
and the other negative. The first timing is called "Digit
Phase I" and the second "Digit Phase II."
The digit current timings shown by broken lines mean
that the digit driver advances the digit current in the
same amount as the propagation delay in the memory
plane.
This technique insures the precise time relation of the
word and digit current for any address.
per second. The time delay for the address decoding and
for the propagation of word current from the current
source to the memory plane is estimated as. 30 nanoseconds.
The peak of readout signal appears 10 nanos~conds
after the mid-point of the rise of the word current.
The maximum propagation time of the signal in the
memory plane is assumed to be 15 nanoseconds. The delayed signal is shown with broken lines.
Each of the circuit delays admitted, in the sense amplifier, in the polarity detecting strobe circuit, and in
the output buffer, is 5 nanoseconds.
For write operation, 200 nanoseconds" are allotted.
The word current has two timjngs. The timings are
called "Word Phase I" and "Word Phase II."
o
20
40
60
80
100
120
System design
The system design should be accomplished taking engineering feasibility and cost into consideration".
Some of the possible combinations of word and bit
nanoseconds
140
160
180
200
220
240
260
I
,---____________~)xC~___________
~
Read Instruction
Address
I
L
30n~
'--_/
~~'n
n5
Word Current
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----c--=i"
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Sense Signal
__~15ns 15 ns
,
Output Buffer
Reset
Write· Instruction
=x______________________
Word Phose I
Word Phase
n
- ' "
Read
Word Current
Word Current
Di git CUrrent
Digit Current
Strobe Pulse
Strobe Pu I se
Figure 6-Timing waveforms in the digit control system
Figure 7-Timing waveforms in the word control system
Let the memory location nearest to the digit circuit:ry
be Mn and the farthest M, in :Figure 5, then an example
of the time relation using the digit control system is as
shown in Figure 6.
In the cases such as write-after-write, read-after-read,
and write-after-read, the time separation of succeeding
timings may be smaller than the typical value. However, it is not so serious as will be shown in the case of
the word control system.
Figure 7 shows another time relation of word and
digit timings when the word control system is employed.
The timings of digit circuitry are fixed irrespective of
the selected memory location.
As shown in Figure 7, the time separation of succeeding word currents becomes very small in the worst case.
The reason why the situation is worse with the word
control system is that the "time rel~tion is adjusted only
by the word current, causing a significant approach of
leading and trailing word currents.
The timing generator for a total system is shown in
Figure 8. The delay circuits connected with address decoding logics are used to control the bit timings in accordance with the memory address selected.
Strobe circuit
A two-stage monolithic differential sense amplifier is
followed by a :modified CML circuit which detects the
polarity of readout signals at the strobe timing, and
also holds it as long as the strobe pulse is present.
As shown in Figure 9, the polarity detecting strobe
circuit consists of a current switch made of transistors
Ql and Q2, feed-back loops made of transistors Qa and
Q4, steering transistors Q6 and Qs, and an emitter Q7
which makes the current switch inactive when the
strobe pulse is absent.
At the moment the base level of transistors Q7 is
shifted from -0.8 volt to -1.6 volt, i.e., the strobe pulse is
976
Fall Joint Computer Conference, 1968
given, the current switch is turned on. Since both the
transistors Qland Q2 cannot conduct simultaneously,
one of them assumes "on" state answering to an imbalance, however small, present between the base levels of
input transistors Qs and Q4'
ll'ord seTeztion matrix
Diode-st.eered transformer matrlx7 and transistor
matrixs can be selected as word selection matrices.
The feature of the two methods are compared in
Table 4.
Word (Even Plane)
Word (Odd Plane)
Execute
Instruction
10
Strobe
Addresses
0----{}:
Digit Phose I
Digit Phose II
(Arabic figures show delays
in nanoseconds)
D = Delay Lines
J:t'ij.Cure 8-TiminJl: pulse Jl:enerator
Design of lOO-Nanosecond Read-Cycle NDRO Plated-Wire Memory
Items
977
Transistor Matrix
Diode-steered Transformer Matrix
(1) The current capacity must be large
(1) The current required is l/fJ times the
enough to supply the word current.
word current.
(2) The characteristic impedance of the
(2) The characteristic impedance of the bus
line must be as low as possible to minimize bus line can be made higher.
the voltage shift of the bus line. A large part
(3) The voltage swing is a function of
of the power wiIa be wasted in the terminating
transistor parameters. It is generally smaller
register.
than the peak amplitude of the back volt(3) The voltage swing must be greater than ages on the word line.
the peak amplitude of the back voltage on the
word line.
Switch
Lines
Problems in the
current Switch
Lines
Problems in the
Ground Line
Problems in the
Half-Selected
Word Current
No particular problems exist.
Since the bus line is apt to ring, a. damping
resistor must be added.
There is hardly any current in the ground Instead of the voltage source bus line the
plane, because the transformer prevents com- ground or power line supplies the current to
the word line. Accordingly the impedance of
mon moqe current.
the ground or power line must be kept as
low as possible.
(1) Transistors with less collector-to-base
(1) The balance in the transformer windings
must be improved to prevent the common capacity are recommended.
(2) The voltage swing of the base driver
mode voltage on the primary winding from
inducing a differential mode current in the (voltage switch) must be designed to be
secondary winding.
small.
(2) Diodes with less junction capacity must
be used.
TABLE 4.-Comparison of word selection matrics
Figure 9-Polarity detecting strobe circuit
Output
Strobe
Pulse
to Planes
-6V
lOOp
Oi fferential
Amplifier
978
Fall Joint Computer Conference, 1968
When production is taken into consideration, a transistor matrix is preferred in the NDRO plated-wire
memory. A blockdiagram of word selection circuits is
shown in Figure 10.
Experimental results
A cross-sectional model of the system was con~
structed, and it worked as expected.
The memory stack consists of four modules each containing eight planes. Each plane has 128 word line s by
288 plated-wire digit lines.
The· memory wire is prepared by electroplating permalloy onto a bronze phosphide wire 0.13 mm in diameter. The plated wires are spaced at 1.0 mm centers
and the word lines are spaced at 1.5 mm centers.
The back EMF of the word line for 300 milliamperword current with a rise time of 20 nanoseconds is approximately 14 volts. A 40 milliampere digit current
gives rise to a typical output signal of 10 millivolts.
The basic logic element exclusively used in the experimental model is a current-mode-Iogic circuit J.I. PB 80
which has two four-input gates. Typical propagation
Address
delay of J.I. PB 80 is 3 nanoseconds.
A monlithic integrated differential amplifier J.l.PC7B
is used for the sense amplifier. It has a bandwidth of 40
MHz and a voltage gain of 40 dB.
Transistor selection matrices and digit drivers are
temporarily constructed by discrete components.
The propagation delay and the attenuation per 1-K
words were measured. The results obtained are 14 nanoseconds and 1.5 dB.
Adjustment of terminating resistors was necessary to
minimize the digit noises.
The use of diodes, connected back-to-back in series
with the digit line, was satisfactory.
The minority carrier strage in the diodes and the
junction capacity gave rise to a slight ringing on the
digit line.
CONCLUSION
It has been pointed out that the delays in address decoders, sense amplifiers and strobe circuits are the princi-
.
Decoders
/
Registers.
Memory Plane
/////////////
.Q
¢
~X16 Transistor M o t ¥ /
Transistor
Matrix
Selection
77///7 7/////
/
c:
.2
U
.!
¢
Q)
Bose line
Selection
)(
..::
0
Emitter Line
Selection
~
~
2
¢
Word Phase I
0
~
n
Word Phase
(WOrd Phose I )
for Reod CycJe
Read IWrite
Word Phose I
Word Phose n
~
f/)
.-
Q
7
f/)
c:
1'1'
··-
.J
/
I
'II
V
···
ZZ22Z7
···
/
70
j
~ZZZZZ? 7
CJ)
/////////////
7
~72 ZZZZZ? 7
iI"~
II
V
II
I~
··•
/0
/LJ
/5
Emitter Line Selection
(Word Phose 1)
Bose Line
Selection
Figure 100BIockdiagram of word selection circuitR
Emitter Une Selecti on
(Word Phase lU
Design of lOO-Nanosecond Read-Cycle NDRO Plated-Wire Memory
pal factors determining the read cycle time of the mem0ry.
Small-scaled transistor selection matrices in combination with Cl\1L decoders were employed, and a decoding
delay of 30 nanoseconds was obtained.
A polarity detecting strobe circuit was developed
with a modified CML circuit. The strobing delay observed was less than 5 nanoseconds.
The method to compensate the propagation delays in
the memory plane was discussed. It was shown that it is
desirable to control the timing of digit circuitry.
ACKNOWLEDGMENT
This paper is a part of work done jointly by many research engineers of the Central Research La boratories
of Nippon Electric Co., Ltd.
The author would like to express his cordial thanks to
Dr. I. Someya and Dr. Y. Sasaki for their support and
guidance, and also to his colleagues, particularly
Messrs T. Furuoya and H. Murakami for their cooperation in the construction of his memory system.
979
REFERENCES
1 C F CHONG R MOSENKIS D K HANSON
Engineering design of a mass mndom accessplaled wire memory
Proc F JCC 363 1967
2 JP McCALLISTER C F CHONG
A 500-nanosecond main computer memory utilizing plated-wire
elements
Proc F JCC 305 1966
3 B A KAUFMAN P BELLINGER H J KUNO
A rotationally switched ROD memory with a tOO-nanosecond cycle
time
Proc F JCC 293 1966
4 S A MEDDAUGH K L PEARSON
A 200-nanosecond thin film main memory system
Proc FJCC 2811966
5 TISHIDATE
Circuit techniquesJor one hundred nanosecond thinfilrn memory
Colloque International sur les Techniques des Memoires
Editions Chiron Paris 1966 p 671
6 TISHIDATE
Delay co'mpensation concept in very high speed memories
NEC Res and Dev 9 129 1967
7 E E BITTMANN
A t6 K-word, 2-Mc magnetic thin film memory
Proc F JCC 93 1964
High speed, high-current word-matrix using charge~
storage diodes for rail selection
byS. WAABENandP.CARMODY
Bell Telephone Laboratories, Incorporated
Murray Hill, New Jersey
INTRODUCTION
Diode matrices used to select the path of an unidirec~
or bidirectional matrix current are well known. l-3
Conventional matrices use a low storage diode crossP?int for unidirectional current, and a charge-storage
dIOde c~osspoint for bidirectional current. For typical
magnetIc memory cells the required currents approach
1 ampere. Also, for magnetic thin film memories the
required word current duty cycle' is small, typically 30
ns out of a store cycle time of several hundred nanoseconds. To conduct such currents, the required silicon
area for a diode is almost one order of magnitude less
tha~ that required for a transistor. Since the cost of a
s~~lConductor device is strongly dependent on the
SIlicon area used, diode matrices are therefore commo~ly used for the economical selective drive of magnetIc ~emory stacks. For many memory system configuratIOns, because of the significant cost of high current t~ansistor m~trix. selection switches, the cost per
word hne of matrIX raIl selection is comparable to that
of the individual word selection diode. Large matrices
are therefore commonly employed to share the switch
cost among. many matrix crosspoints. The penalty is
more stray Impedance and system noise as weH as difficulty of reliable assembly of large arrays. It will be
~hown how this rail selection switch function can be
nnplemented advantageously by a circuit combination
of a. low co~t, high-current charge-storage diode and
an InexpenSIve 100-200 rnA current transistor. No
transformers are needed. Furthermore, the usual number of rail selection transistors can typically be halved
by a tandem diode matrix arrangement.
I~ this paper the basic schemes are presented. The
desIgn tradeoffs are then given and discussed. Experimental results are shown.
tio~l
Basic charge-8torage diode rail8election
Figure 1 is the schematic of a diode matrix of 32 word
rails and 32 diode rails for a plated-wire store which
will be used-as an example. The distributed word rail
loading capacitance is 32 X 32 pF ~ 1000 pF. The distributed diode rail capacitance is 32 :X 3 pF ~ 100 pF.
Resistors for biasing the matrix diodes in such a manner that nonselected diodes will remain backbiased are
also shown. Note that inherent in all diode matrix
selection schemes the matrix rail selection switches
must carry the current of the selected path.
To select the crosspoint of a word rail and a diode
rail, one of the 32 word rails is changed from zero volt
, to El volt by turning the charging current Iclll on. If
Ichl is constant then the word rail voltage rises linearly
to El volt. When the rail voltage reaches El, CSDl goes
into forward conduction and the rail voltage is thus
clamped to E l . From this point on, charge is accumulated in CSD1 by the continued flow of I chl. All matrix
diodes remain backbiased since the diode rail voltage is
more positive than the Qlamped word rail voltage.
Similarly, the closure of a diode rail selection switch
generates a current flow through CSD 2• Charge has
now been accumulated in the two matrix rail chargestorage diodes, OS01 and CSD 2. The charging currents
Ichl and Icll2 are supplied via two selected low current
transistors. In the reverse conduction phase of the
charge-storage diode, the voltage drop across the diode
is the junction voltage across the forward biased junction of a reversely conducting diode minus the IR drop
across the body resistance. Therefore, by closing a
common control switch transistor to ground potential,
current will flow in the selected path as long as there
is charge. available in the electrically floating· chargestorage diodes. Notice that the current handling and
tum-on and tum-off requirements on the matrix rail
selection switches are relaxed and decoupled from the
high-speed, high-current requirements of the selected
matrix path. Rise time, amplitude and duration of the
current pulse are determined ,by the circuit parameters
and the common control circuitry described below.
981
982
Fall Joint. Computer Conference, 1968
t
DIODE RAIL BIAS VOLTAGE
+E2
QNDRO
=
f i dt
=
U ·OA·40·1()-9
4 nC
=
QDRO = ~ ·1·50·10-9 = 25 nC
WORD RAIL
T
C.S.D.,
This amount of charge must be supplied by CSD I , CSD2
and the common control circuit. The following arithmetic indicates the relative sensitivities of the parameters involved. For a desired word current peak Ip
~p the rerIse
V2Qs. Also since
and a constant rising current slope s =
quired charge Q is given by: Ip
s
=
=
t
~,
E is the fixed driving voltage minus the
L where
.
semiconductor junction drops of a selected path, and
L is the driven word loop impedance, it follows that
,CHARGE STORAGE
DIODE C.S.D.
1 =
p
--i>tNORMAL COMPUTER
DIODE
~
LONG T
CHARGE STORAGE
DIODE
BASIC
COMMON
CONTROL
WORD
CURRENT - - t - - - - i
TIMING
R
FIGURE I-A basic 32X32 diode matrix with charge-storagediodes for matrix rail selection
As an extension on the basic scheme the number of
rail selection switch drivers can be reduced by a cirouit
arrangement where groups of the rail selection diodes
are shared by common switch drivers. Figure 2 illustrates this principle as applied to the diode rails. A
16 word rail by 64 diode rail matrix is shown selected
by 16 + 8 + 8 = 32 medium current transistor switches. This should be compared to 80 high-current switches
for a classical 16 X 64 matrix. Alternatively, 64 sWItohes
would be required for a square matrix covering the same
1024 matrix crosspoints. It can be seen that the chargestorage diodes are also arranged in matrix form which
we shall refer to as being in tandem with the original
matrix.
The practicality of the basic scheme presented above
depends on a tradeoff between particular circuit parameters and requirements. A brief analysis of typical
circuit performance will be presented next.
Required charges
Word current charge area
The nominal plated-wire store word current pulses
shown in ,Fig. 3 require the following amounts of charge:
.~.
V
E
Consequently for a fixed available Q,al0 percent variation of E or L will result in 5 percent variation of 1 peak.
This reduced .sensitivity to variations in L is significant
because L may vary from word loop to word loop while
Q and E are more readily controlled in a memory systems efl;vironment. The charges of the matrix capacitance will be discussed next.
Matrix capacitance charges
To change the voltages at the matrix terminals
charge must be supplied to or drained from the matrix
rail capacitances. Here only the charges at the word
rail will be discussed.
The word rail terminal of the word l!ne must for
pulses with equal rise and fall times supply twice the
basic 25 nC for the DRO and 4 nC for NDRO. At the
word rail terminal there are three possible sources of
charge available to supply the word current (see Figures
1 and4):
(a) The rail selection switch.
(b) The charge-storage diode CSD I •
(c) The word rail capacitance ..
To attain a linearly rising word current the voltage on
the word rail must remain constant during the rise time
of the word current pulse. Th~refore the role of CSD 1
is twofold (I) to limit and clamp the charging of the
selected word rail capacitance to a well-defined voltage
and (II) to implement a low impedance charge reservoir at a fixed votage level during the rising portion of
the word current. This buffer can in principle be either
the CSD or the large word rail capacitance of 1000 pF.
However, such a charge drain from the word rail capaci-
High Speed, High Current Word-Matrix
983
1000mA
WRITE
mA
400mA
NORO
WORD RAILS-I6, SWITCHES-16
DIODE RAILS- 64, SWITCHES- 8+8
FIGURE 2-Tandem diode matrix ",'ith charge-storagediodes. There are 16 word rails and 64 diode rails. The word rails
are operated as indicated in Fig. 1. The diode rail charge-storagediodes are arranged in a diode matrix of eight groups of diodes
(A, B, ... , H) each of eight diodes. After charging, a selected
crosspoint is driven by the closure of the common control circuit.
20
Charge-storage diode properties
The continuity equation for charge describes the
charge flow through a diode:
dQ
dt
The term
~ is
T
+9 =
i(t)
T
the amount of charge disappearing by
recombination in the diode and the other terms express
the conservation of charge. Assume a current IF is
conducted in the forward direction for a period of time
t F • Charge is accumulated in the diode. The efficiency
E of this charge reservoir measured at time tF is:'
TIME nS
t,
QNDRO=
tance will produce access noise during read. It follows
implicitly from the discussion above that in the caseof
the 8 nC necessary at the word rail terminal for NDRO
that the charge storage feature of the word rail diode is
in some ways incidental. For NDRO operation in particular the matrix access time is dominated by the
charging time, say 75 ns, of the word rail capacitance
of 1000 pF charged to 15 volts at the corresponding
charging current of 0.2 A. The finite lifetime of the caJriers in the CSD does, however, set a practical limit to
how small a rail selection current one can realize and
still achieve a 1 ampere DRO pulse. The next .section
will summarize the charge-storage-diode phenomena
briefly.
50
f
Lo dt, =+.04 020 010-9 =4nCOUL
o
t
QWRITE=
f
i.. o dt,=+01-50 o I0- 9 =25nCOUL
o
FIGURE 3-Current, time and charge for nominal word currents
It follows that the longer the lifetime T the higher the
efficiency. The necessary charging time is given by:
Figure 5 shows typical calculated tradeoffs using this
expression.
Notice that limiting the peak current with a common
control charge-storage diode eases the charge uniformity requirement on the many rail selection diodes.
The rail diode requirement is therefore only single
ended; namely, more charge is required by the rail
diodes than the amount in the common control diode.
A simple common control circuit for a 400 rnA peak
NDRO pulse is implemented using a short lifetime
diode, thus securing a maximum peak word current
which is insensitive to the duration of the charging
pulse. The 1.0 A peak DRO pulse is conveniently implemented using a longer lifetime diode for common
control.
Rail selection switches
E = Charge Available
Charge Supplied
IFT(l - e -tiT)
IF"tF
The rail selection switches can be implemented in a
variety of ways. The "optimum" choice depends heav-
984
Fall Joint Computer Conference, 1968
02
01
ON
~ 601--609
11 P J nE~NI~G
The working set model for program behalli()r
Comm ACM 115196R pp ~{2;{-3~:)
12 LWCOMEAU
A study 0.1 the effect (~f user program optimization in a paging
system
ACM Symposium on Operating System Principles Gatlinhurg
Tennessee Oct 1-41967
1~ A C McKELLAR E G COFFMAN
The organization of matrices and matr£x operations in a paged
multiprogramming environment
Technical Report No 59 Dept of Elec Eng Comput.er Rcien('es
Laboratory Prin~et.on Universit.~, February 196R
14 .J A COHEN
Use of fast and slow me'mories in li.'!t pr()Ces"H:n(! languages
Comm ACM 10 2 1967 pp 82-86
15 D G BOBROW D L MURPHY
Structure of a LISP system using two-level storage
Comm ACM 1031967 pp 155-159
16 B BRA VYX F GUSTAVSON
An evaluation of program performance on the 11/44/44X system
Pali. 1 Report RC 2083 IBM T J Wa.tson Research Center
Yorktown Heights New York May 1968
17 R L PATRICK
Time-sharing tally sheet
Datamation 13 111967 pp 42--47
18 G OPPENHEIMER ~ WEIZER
Resource management for a medium scale time sharing operating system
Comm ACM 11 5 1968 pp 313-322
19 LA BELADY
1018
Fall Joint Computer Conference, 1968
A study oj replacement algorithms for a virtual storage computer
IBM Systems J 5 2 1966 pp 78-101
20 BRANDELL
A note on storage fragmentation and program segmentation
Report RC 2102 IBM T J Watson Research Center Yorktown
Heights New York May 1968
Program behavior in a paging environment
by BARBARA S. BRAWN and FRANCES G. GUSTAVSON
IBM Watson Resarch Center
Yorktown Heights, New York
Study objectives
This paper is the result of a study conducted
on the M44/44X system, an experimental timeshared paging system designed and implemented
at IBM Research in Yorktown, New York. The
system was in operation serving up to sixteen
users simultaneously from early 1966 until May
19.68. Conceived as a research project to implement the virtual machine concept, the system has
p.rovided a good deal of information relating to the
feasibility 'Of that concept. 1 The aim of this study
is to investigate the concept more thoroughly from
a user's viewpoint and to try to answer some important questions related. to program behavior in
a paging environment. As an experimental system, the M44/44X provided, an. excellent vehicle
for the purposes of this study, and the study itself
forms some basis for an evaluation of the system.
It is recognized by the authors that the results
and conclusions presented here are to a great extent characterized by a particular configurati'On of
a particular paging system, and as such do not constitute an exhaustive evaluation of paging systems or the virtual machine concept. Nonetheless,
we feel that the implications of the conclusions
reached here are of consequence to other system
implementations involving paging.
Conventional vs automatic memory management
There has been much written about the benefits
and/or disadvantages of paging machines and the
virtual machine concept. 2 ,3,4 However, little data
have been obtained which sheds a realistic light 'On
the relative- merits of such a system compared to
a conventi'Onally designed system. From a programmingpoint of view there is little question
that any technique which obviates the necessity
1019
for costly pre-planning of memory management
is inherently desirable. The question that arises
is-given such a technique, how efficiently is the
automatic,management carried out?
From a user's point 'Of view this can simply
mean-how long does it take to run a program
which relies on the automatic memory management, and is this time comparable to the time it
would take to run the program if it were written
in a c'Onventional way where the burden of memory management is the programmer's responsibility. It is this user's viewpoint that forms one focal
point for this study.
The· role of the programmer
Perhaps the most important aspect of the study
concerns the role of the programmer. How does
the role of the virtual machine programmer differ
from that of the conventional programmer? For
a conventional system the role 'Of the programmer
is well defined-the performance (i.e., running
time) of his program is usually a direct result of
his ability to make efficient use of system resources. How much he is willing to compromise efficiency for the sake of ease of programming may
depend on how often the program is to be run.
In any case, the decision rests with him. (There
of course exist many applications where his choice
of programming style or ability have little effect
'On performance; this case is of little interest to
our stUdy.)
When faced with th.e problem of insufficient 'JIlachine resources to accommodate a direct solution
of his problem, the conventional, programmer is
left with no choice but to use some procedure
which is inherently a more complex programming
task. The quality of the procedure he chooses may
1020
Fall Joint Computer Conference, 1968
have a dramatic effect on performance but it is at
least a consistent effect and often quantifiable in
advance. In any event, because conventional systems have been around a long time, there are
many guidelines available to the programmer for
achieving acceptable performance if he should
wish to do so.
The role of the virtual machine programmer is
not nearly so well defined. One of the original attributes claimed for the virtual machine concept
was that it relieved the programmer from consideration of the environment on which his program
was to be run. Thus he need not concern himself
with machine limitations. As was pointed out
previously, the question is-given that the programmer does in fact ignore all environmental
considerations, what kind of efficiency results?
Assuming that the answer to this question is sometimes undesirable, that is, running time is unacceptably long, another question arises. Can the
programmer do anything about it? Clearly it is
difficult to conceive of his being able to reorganize
his program in such a way as to assure improved
performance if he has no knowledge of the environment nor takes it into consideration when
effecting such changes. Thus if the premise 'Of
freedom from environmental considerations is to
be strictly adhered to, there can be no way for the
programmer to consciously improve performance.
Sh'Ould this premise be compromised to allow
the programmer to influence performance through
exercising knowledge of the system environment?
This study assumes that this should indeed be the
case and shows that there is much to be gained
and little to be lost. It ,should be emphasized, however, that the original premise need not be compromised at all in so much as it would, of course,
not be necessary for the programmer to ever assume the responsibility of having knowledge of
the environment (unlike in the case 'Of the conventional programmer faced with insufficient machine resources). It would only enable him to have
better assurance of acceptable performance if he
chose to do so.
Clearly, the many interesting questions concerning the role of the virtual machine programmer
and his effect on performance are worthy of pursuit We feel that the measurements obtained in
this study. of program behavior in a paged environment provide a valuable insight to such questions and serve as motivation for further consideration of them.
Test environment
Before discussing the results of the study we
feel it is advisable to describe the environment in
which they were obtained. Thus included herein
are brief descriptions of the M44/44X system and
the methods employed to obtain and measure the
test load programs. (More complete information
is available in References 1, 5 and 7.) It is assumed throughout this discussion that the reader
is generally familiar with the concepts of virtual
machines, paging, time-sJ.taring and related topics;
however, a short general discussion on paging
characteristics of programs is included in order
to establish an appropriate reference frame for
the presentation of the experimental data.
The experimental M44/44X system
To the user a virtual computer appears to be a
real computer having a precise, fixed description
and an 'Operating system which provides various
user facilities and links him to the virtual machine
in the same way as the operating system of a conventional system links him to the real machine
(Figure 1). Supporting the virtual machine definition. is a transformation (control) program
ConventIonal System
Virtual System
Real Machine
Real Machine
r-- --,
I
I
VIrtual
MachIne
L
___
FIGURE 1~Conventional and virtual systems
I
I
.J
Program Behavior in Paging Environment
which runs on the real machine.. This program, together with special mapping hardware, "creates"
the virtual machine as it appears to the user. Implementation of multi-programming within the
framework of the virtual machine concept permits
the transformation program to define the simultaneous existence of several separate and distinct
virtual machines.
The virtual machine programmer may write
programs without knowledge of the transformation program or the configuration of the real machine-his concern being the virtual machine description, which is unaffected by changes in the
real hardware configuration or the transformation
program. In the M44/44X system the real machine is called the M44, the transformation program is MOS, the virtual machine is the 44X and
the virtual machine operating system is the 44X
Operating System (Figure 2).
The real computer
Figure 3 shows the hardware configuration of
the M44 computer. It is an IBM 7044 with 32K,
36-bit words of 2 JLsec core which has been modified to accommodate an additional 184K words of
8 JLsec core and a mapping device. The resident
control program together with the mapping device and its associated 16K, 2 JLosec mapping memory, implement the 44X virtual machines on a demand paging basis in the 8 JLsec store. The backup store of the M44/44X system, which is used
fo~ both paging and permanent file storage, con-
1021
Non-Overlapped
Channel A Omitted
FIGURE 3-M44/44X hardware configuration
sists of two IBM 1301 II disks. The page size (a
variable parameter on this system) used for our
tests was 1024 words (1 K). The average time
required to seek and transmit one page from the
disk to core is 0.21 second for that page size (computed from our data). The IBM 7750 serves as a
message switching deyice, connecting a number
of IBM 1050 terminals and teletype 33's to the
system. To facilitate measurement our tests were
not run from terminals (foreground) but as background jobs from tape. (The system makes no distinction between the two for the single programmed case-nor for the multi-programmed
case as long as all jobs on the system are of the
same type, i.e., all background or all foreground.)
The control program
FIGURE 2-M44/44X Multi-programming system
MOS, the control program, resides in the nonpaged 2 JL sec store. This M44 program "creates"
and maintains each virtual 44X machine and enables several 44X's to run simultaneously, allocating the M44 resources among them. All 44X I/O
is monitored by MOS, and all error checking and
error recovery is performed by MOS. Some of the
design parameters of MOS are easily changed to
facilitate experimentation. The variable parameters include the page size, the size of execution
store (real core) made available to the system, the
page replacement algorithm, the time slice and the
1022
Fall Joint Computer Conference,
19~8
scheduling discipline (via a load leveling facility).
The last two parameters mentioned are applicable
only in the multi-programmed case. As previously
stated, the page size used throughout the study
was 1024 words. The size 'Of real c'Ore was, of
course, one 'Of the m'Ost important parameters and
was varied to investigate paging properties of the
programs (in. b'Oth the single and multi-programmed environments).
For the single pr<,>grammed part of the study
the page replacement algorithm e.mpl'Oyed was
FIFO (First In-First Out). If a page in real core
must be 'Overwritten, the page selected by FIFO
is the one which has been in core f'Or the longest
period of time. .Data were also obtained for single
pr'Ogrammed paging behavior under a minimum.
page replacement algorithm developed by L. Belady. 6 A non-viable algorithm, MIN computes the
minimum number 'Of page pulls required by examining the entire sequence of program address
references.
For the multi-pr'Ogramming part of the study,
a time slice of 0.1 second was used. Runs were
made using three different page replacement algorithms to determine the effect 'Of this design
parameter on system performance. (Available
real store is competed f'Or freely by all the 44X's.)
The three algorithms were FIFO, BIFO, a biased
version of FIFO which fav'Ors (on a r'Ound r'Obin
basis) one 44X by choosing not to overwrite the
pages associated with it for a preselected' interval
'Of time, and AR, a hardware supported alg'Orithm
which ch'Ooses a candidate for replacement fr'Om
the set of pages which have n'Ot been recently
referenced. (These algorithms are described more
fully in Refs. 1 and 6.)
The virtual machine
Each virtual 44X machine is defined to have 221
words of addressable st'Ore. The virtual memory
speed of a 44X is 10 J.Lsec (44X pr'Ograms are executed in 8. J.L:sec store and a 2 J.Lsec mapping cycle
is added to a mem'Ory cycle) ; the CPU speed is 2
ILsec.The user c'Ommunicates with the 44X virtual machine' thr'Ough the 44X Operating System,
a 44X pr'Ogram which permits continu'Ous pr'Ocessing 'Of a stack of 44X jobs; it contains a c'Ommand
language, debugging facilities, a FORTRAN IV
c'Ompiler, an assembly pr'Ogram, a rel'Ocatable and
absolute loader facility, routines for handling a
user's permanent disk files and a subroutine library.
Test load problems
Test pr'Oblems were chosen from the scientific,
c'Ommercial, list processing and systems areas of
computer applications. The problems chosen inv'Olved large data bases which required the programmer of a conventiona,l machine to c'Oncern
himself with memory management. The pr'Oblems
discussed in this paper include matrix inversion
and data c'Orrelati'On fr'Om the scientific area and
s'Orting fr'Om the c'Ommercial area. (A c'Omplete
rep'Ort 'On the entire study can be f'Ound in Ref. 7.)
Pr'Ograms were initially c'Oded for each problem in tW'O ways:
i) a c'Onventi'Onal manner where the b.urden
'Of mem'Ory management is assumed by the
pr'Ogrammer (c'Onventi'Onal c'Ode), and
ii) a straightf'Orward manner utilizing the
large virtual mem'Ory ("casual" virtual
c'ode) .
Simple modificati'Ons were then made t'O the
"casual" virtual c'Odes to pr'Oduce pr'Ograms better
tail'Ored t'O the paged envir'Onment. Our interest
lay in c'Omparing the performance of the different
versi'Ons· 'Of the virtual C'Odes under variable paging
c'Onstraints in b'Oth single and multi-pr'Ogramming
envir'Onments. We were als'O interested in c'Omparing the c'Onventi'Onally c'Oded pr'Ogram perf'Ormance
with that of the virtual (i.e., aut'Omatic mem'Ory
management) c'Odes given the same real memory
c'Onstraints.
It sh'Ould perhaps be n'Oted here that f'Or our
purp'Oses a pr'Ogram's perf'Ormance is directly related t'O its elapsed run time. Thus in a paging envir'Onment, where this elapsed time includes the
time necessary t'O acc'Omplish the required paging
activity, po'Or paging characteristics are reflected
by increased run time and thus degraded perf'Ormance.
Measurement techniques
A n'On-disruptive hardware m'Onitoring device
capable 'Of measuring time spent in up t'O ten
phases. 'Of pr'Ogram executi'On was used f'Or all
7044 runs and relevant single-pr'Ogrammed 44X
runs. In additi'On, f'Or 44X runs (b'Oth single and
multi-pr'Ogrammed), a s'Oftware measurement
r'Outine in MOS was utilized. This r'Outine c'Ollects
data while the system is running (using the cl'Ock
and a special high-speed hardware counter) and
'On system termination produces a summary of the
Program Behavior in Paging Environment
data including; total time, idle time, time spent in
MOS (including idle time), number of page exceptions, page pulls, page pushes and other pertinent run data.
All programs were run in binary 'Object f'Orm
as background jobs residing 'On a system input
tape; all output was written on tape. For the
multi-programmed runs, a facility of MOS was
used which permits several background jobs to be
started simultane'Ously. For the single pr'Ogrammed study the 44X programs were first
run and measured on the system with sufficient
real core available t'O eliminate the need for paging; these same pr'Ograms were then run (and
measured) in a "squeezed core" envir'Onment, i.e.,
with insufficient real mem'Ory available, thus necessitating paging.
Program behavior under paging
Pr'Ogram performance on any paging system is
directly related to its page demand characteristics. A program which behaves poorly acc'Omplishes little on the CPU before making a reference to a page of its virtual address space that is
not in real core and thus spends a good deal of time
in page wait. A program which behaves well
references storage in a more acceptable fashion,
utilizing the CPU m'Ore effectively bef'Ore referencing a page which must be brought in from
back-up store. This characteristic of st'Orage referencing is often referred t'O. as a pr'Ogram's "locality of reference." 6 A pr'Ogram having "g'O'Od"
locality 'Of reference is one whose storage reference pattern in time is m'Ore local than global in
nature. For example, although a program in the
course 'Of its execution may reference a large number of different pages, if in any reasonable interval
'Of (virtual) time, references are c'Onfined to 'Only
a small set of pages (n'Ot necessarily contiguous in
the virtual address space), then it exhibits a desirable locality of reference. If, on the 'Other hand,
the size of the set is large, then the locality of
reference is poor and paging behavior is correspondingly poor. (The "set" 'Of pages referred to
in the ab'Ove example corresponds roughly to Denning's8 noti'On of a "~orking set."
All pr'Ograms typical of real pr'Oblems exhibit
badly deteri'Orated paging characteristics when
run in s'Ome limited real space environment. What
is 'Of interest is the extent to which the space can
be limited without seriously degrading perf'Ormance. Clearly, the size 'Of this space is related to
1023
the program's locality and provides some indication of the size of what might be called the program's critical or characteristic working set. As
the single pr'Ogrammed results presented below
show, the effects of programming style on the
relative size of this space can be enorm'Ous.·
Single programmed measurement results
We first measured the behavi'Or 'Of the 44X programs in a controlled single programmed envir'Onment. The results obtained are discussed in terms
'Of the relative effects of pr'Ogramming style on
performance for three problems: Tl~Matrix Inversion, T2-Data C'Orrelation, and T4-Sorting.
In each case we are concerned with showing how
even simple differences in programming technique
can make a substantial difference in perf'Ormance.
Unquestionably there are further improvements
which could be made in the alg'Orithms employed;
however, we feel that our point is best illustrated
by the very simplicity 'Of the changes made.
Timing and paging overhead data are given for
actual runs made on the system employing a FIFO
page replacement alg'Orithm. Also, in 'Order to establish that these results were not unduly influenced by that page replacement alg'Orithm, c'Orresponding computed minimum paging overhead
data are given (obtained thr'Ough interpretive program executi'On and application 'Of L. Belady's6
MIN algorithm).
The data collected f'Or the comparison of the
aut'Omatic and manual methods of memory management is also discussed in this section.
Problem T1 . .. Matrix inversion
The virtual machine codes for this program
were written in FORTRAN IV and are intended
to handle matrices of large' 'Order. They all empl'Oy an "in-c'Ore" technique since the large addressable virtual store permits the acc'Ommodati'On
of large arrays (the burden of real memory management being assumed by the system· through
the automatic facility of paging). The curves in
Figure 4 give the respective program run times
as a function of real c'Ore size f'Or the three differ- .
ent versi'Ons which were written for the virtual
machine. These times are for inverting a matrix
of order 100 (which is admittedly not an unusu~l
ly large array, but sufficiently large t'O illustrate
our point without requiring an impractical amount
of CPU time).
1024
Fall Joint Computer Conference, 1968
o
o
3000
~
o
TI.IX
42 PAGES
TLlX* 35 PAGES
I:::. TUX
35 PAGES
IK PAGE SIZE
FIFO REPLACEMENT ALGORITHM
SINGLE. PROGRAMMED
o
**
TI.IA
TI.IX*
42 PAGES (CASUAL CODE)
35 PAGES (MOST IMPROVED CODE)
---- MIN REPLACEMENT ALGORITHM
FIFO REPLACEMENT ALGORITHM
2500
I K PAGE SIZE
SINGLE PROGRAMMED
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1500
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1000
1000
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500
500
0L---~8-K--~16-K---2~4-K---3~2K---4-0~K---4~8-K-----
REAL CORE SIZE (K = 1024 WORDS)
FI G URE 4-Effects of real core size
TI-Matrix inversion (lOOxIOO)
All three programs employ the same algorithm,
a Gaussian procedure utilizing a maximum pivotal
condensation technique to order successive transformations. The differences in the three versions
are extremely simple. The "casual" version,
T1.1X, stores the matrix in a FORTRAN double
subscripted array of fixed dimensions (storage allocated columnwise to accommodate a matrix of
up to order 150), reads the input array by rows
and prints out the inverted array by rows. The
innermost computation loop traverses elements
within a column. Version T1.1X** is the same as
T1.1X except that variable dimension capability
was employed (thus insuring the most compacted
allocation of storage for any given input.· array) .
Version T1.1X* is the same as T1.1X** except
that the input and ouput is columnwise instead of
rowwise. Obviously neither of these changes is
Gomplicated or of any .consequence in a conventional environment; however, as clearly shown in
Figure 4, they make a considerable difference in a
paging environment.
The paging overhead data is shown in Figure 5
for the casual (T1.1X) and the most improved
(T1.1X*) versions for both the FIFO algorithm
(corresponding to the time curves of Figure 4)
i
,
I
8K
16K
24K
32K
40K
REAL CORE SIZE (K= 1024 WORDS)
48K
FIGURE 5-Effects of page replacement algorithm
TI-Matrix inversion (lOOxIOO)
and the MIN algorithm. This paging overhead is
-given in terms of the number of page transmissions required during execution of the respective
program when run with a given amount of real
core available under the discipline of the particular page replacement algorithm. (Each reference
to a page not currently residing in real core requires a page to be transmitted from backup store
into real core [a "pull"] and often also requires
a page to be copied from real core onto backup
store [a "push"]. The total number of pulls and
pushes is the number of page transmissions.
Given a particular real core size, the MIN algorithm employed gives the theoretical minimum
number of pulls required. Belady has shown that
the number of page transmissions obtained by
this algorithm differs insignificantly from the
number obtainable by minimizing both pulls and
pushes.)
As can be seen in Figure 5, there is no great
disparity between the paging overhead sustained
under FIFO and the theoretical minimum possible
(under MIN) for either of the programs. In particular it should be noted that the paging behavior
of the well. coded program is considerably better
Program Behavior in Paging Environment
under FIFO than that exhibited by the casual program under the most optimum of page replacement s~hemes. Certainly these data support the
argument that improvement in programming style
is advantageous to performance, irrespective of
what page replacement scheme is used.
Clearly there are modifications which could be
made to the algorithm itself which would further
improve performance through improved locality
of reference. McKellar and Coffman 9 have indeed
shown that for very large arrays, storing (and
subsequently referencing) the array in sub-matrix
form (one sub-matrix to a page) is superior to the
more conventional storage/reference procedure
employed in our programs. (For the lOOX100 array, however, the difference is not significant.)
Problem T2
0
0
00
Data, correlation
For the other problem in the scientific area an
existing conventional FORTRAN program, which
required intermediate tape I/O facilities because
of memory capacity limitations, was modified to
be an "in-core" procedure for the virtual machine.
The problem, essentially a data correlation procedure, involves reconstructing the most probable
tracks of several ships participating in a joint
exercise, given a large input data set consisting
of reported relative and absolute position measurements. The solution irnplemented is a maximum
likelihood technique; the likelihood functions relating the independent parameters are Taylor expanded to yield a set of simultaneous equations
with approximate coefficients. The equations are
solved (using the inversion procedure of problem
Tl) ,the solutions are used to recompute new approximate coefficients, and the process is reiterated until a convergent solution is reached. (Each
iteration involves a single pass of the large data
set.) The measured position data, together. with
the accepted solution are used to compute the reconstructed ships' tracks. (This final step requires one pass of the data set for each ship.)
For the first (or "casual") version, T2.1X, the
conventional code was modified for the large virtual store in the most apparent way. The large
data set, a mixture of fixed and floating point variables stored on tape for the conventional version,
was stored in core in several single-subscripted
fixed dimension arrays, one for each variable in
the record format. As the curve for this program
in Figure 6 shows, the performance is rather poor.
This is accounted for in part by the fact that the
1025
/:). T2.IX 54PAGES
o T2.IX* 45 PAGES
3500
IK PAGE SIZE
FIFO REPLACEMENT ALGORITHM
SINGLE PROGRAMMED
3000
(/)
o
z
8 2500
IAJ
(/)
I
IAJ
~
2000
z
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a::
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~
1500
~
1000
500
O~
__
~
SK
__- L_ _ _ _
~
__
~
_ _- L _ _ _ _
~~
16K
24K
32K
40K
4SK
REAL CORE SIZE (K =1024 WORDS)
_ __
54K
FIGURE 6-Effects of real core size
T2-Data correlation
manner in which the data are stored causes a glob..
al reference pattern to occur due to the program's
logical use of those data. Version T2.IX* attempts
to improve the locality by storing the data compactly in one single-subscripted floating point array, such that all of the parameters comprising a
single logical tape record in the conventional code
are in sequential locations. (The conversions necessitated by assigning both fixed and floating
point variables to the same array name increased
the CPU time slightly.) The curves in Figure 6
clearly show that this modification resulted in a
significant improvement.
The same ordered relationship exhibited under
FIFO holds for the casual and improved versions
under the MIN algorithm (Figure 7). Although
in the case 'of the poorly behaving code, the MIN
algorithm does appreciably better than FIFO
given a core size of 32K where FIFO performance
has already deteriorated badly. The improvement
is short lived, however, since deterioration under
MIN occurs with any further decrease .in real
core size.
1026
Fall Joint Computer Conference, 1968
It should be noted that the actual data set used
for these runs was not exceptionally large (as the
total number of pages referenced indicates).
Again, practicality demands that we settle for a
data case 'Of reasonable size. The case at hand involved six ships (resulting in 26 equations) and a
rather small data base of only 240 reports. The
data base storage requirements in the case of the
well coded program, T2.1X*, were satisfied by
four pages. In the case of T2.1X, however, the
several large fixed dimension arrq,ys used to store
the data in that pr'Ogram required 13 pages; thus
not only was the data ordering poor but a great
deal of space was wasted as well.
Once again, there are probably other improvements that could be made. For example, because
the program is divided into several subroutines
(17) of reasonable length, a change in the order
of loading the routines could improve (or degrade) performance. We have illustrated here
only the effects of a change in the manner of storing the data base.
!::. T2.IX
54 PAGES
T2.1 x* 45 PAGES
--- MIN REPLACEMENT ALGORITHM
FIFO REPLACEMENT ALGORITHM
IK PAGE SIZE
!::. SINGLE PROGRAMMED
o
8000
7000
o
,,
,,
,,
,,
,,
,,
,,
o
3000
2000
\
\
o
1000
\
\
\
\
16K
24K
32K
40K
48K
REAL CORE SIZE (K =1024 WORDS)
56K
FIGURE 7-.:..Effects of page replacement algorithm.
T2-Data correlation
Problem T4 .•.• Sorting
Sorting, a classical example of the necessity for
introducing complicated programming techniques
to accommodate a problem on a conventional memory bound computer, also aff'Ords an excellent example of how drastically programming style can
effect performance in a paging environment.
Ideally, if memory capacity were sufficient for the
entire file to be in core, the sort programmer
would only need to concern himself with the internal sorting algorithm and never be bothered
with the other plaguing procedures involved with
doing the job piecemeal. This was the approach
taken, programming the virtu'al machine codes
assuming that the file could be accommodated in
virtual store.
Initially, two different algorithms were codedthe' Binary Replacement algorithm (basically a
binary search/insertion technique employed in a
generalized sorting program in the Basic Programming Support for IBM System 360) and the
Quicksort 1o algorithm (a partitioning exchange
procedure). When the c'ompleted programs were
run with a reasonably l'Ong data set, it became immediately apparent that the Binary Replacement
algorithm was exceptionally bad for large lists
because of the amount of CPU time required.
(Note that this characteristic presents little problem for the internal sort phase of a conventional
code which never deals with a very' large list.)
We will, 'Of course, acknowledge that someone
more knowledgeable in the field of sorting than
we would have recognized this characteristic of
the algorithm beforehand. Our experience nonetheless pointed out rather dramatically that an accepted technique for a conventional machine need
n'Ot be acceptable when translated to a virtual machine environment, irrespective of its paging behavior! Because of its unacceptable CPU characteristics, the algorithm was discarded and our
efforts were concentrated on Quicksort since that
algorithm is efficient for either small or large
lists.
Four versions were ultimately c'Oded for the
virtual machine, each of which is described below.
All of the .changes made to get from one version
to another were simple and required little programmer time. N one of these changes altered the
total number 'Of pages referenced; they simply improved the locality of reference. The time curves
in Figure 8· and the paging curves in. Figure 9
Program Behavior in Paging Environment 1027
size of the- file in the case shown is 100,000 words,
occupying 100 pages in virtual memory.)
T 4.1XQ, the "casually" coded version, reads in
the entire file, performs a non-detached keysort
3500
• T4.IXQ
129 PAGES
4730 SECONDS
o T4.IXQ*I30 PAGES
AT 64K
utilizing the Quicksort algorithm and a table of
• T4.IXQR 129 PAGES
key address pointers, then retrieves the records
o
T4.IXQR* 129 PAGES
3000
IK PAGE SIZE
for output by using the rearranged table of pointFIFO REPLACEMENT ALGORITHM
0
ers. The records themselves are not- reordered durz
SINGLE PROGRAMMED
§ 2500
ing the sort thus storage references are random
and
global during both sort and retrieval, making
!oJ
locality of ref.erence poor. Deprived of only a
j:: 2000
z
::::l
small amount of its required store, this program
II::
...J
behaves very badly. Note that although the MIN
~ 1500
f2
curve in Figure 9 does show some improvement in
paging behavior over FIFO, the improvement is
of no consequence since performance is still quite
1000
unacceptable.
T 4.1XQ* treats the file as N sublists; each is
500
~
read
in, then sorted using the non-detached key':
•
4~1I
----,I I
~I
1 1
1><1 C><1 ,----I
1....--'
>32
19
>
T4
- Qu1wort
1,000,000
word f11.
[70:.":::]
15
1'-----1
The data indicate that, if reasonable pr'Ogramming techniques are employed, the automatic paging facility compares reas'Onably well (even favorably in some instances) with programmer controlled meth'Ods. While n'Ot spectacular, these
results nonetheless lo'Ok g'O'Od in view 'Of the substantial savings in pr'Ogrammer time and de-
Program Behavior in Paging Environment
bugging time that can still be realized even when
constrained to employing reason,able virtual machine programming methods.
I:::. T4.IXQ
1200
The effects of programming style
The two versions 'Of the sort program used for
this study were the "casually coded" version,
T4.1XQ, and the "most improved" version, T4.lXQR*. Multiple copies of a given program were
run simultaneously (as background jobs) on the
system with the full real core (184K) available.
(N 0 more than 5 background jobs can be run
simultaneously because of tape drive limitations.)
The curves in Figure 10 compare the multi-programming effic,iency 'Obtained with the two different programming styles. .These curves are plots
of Time/Job vs the number of (idEmtical) jobs
run simUltaneously on the system (Multi-programmin.g Level) .
Clearly the efficiency of the system is nearly
identical whether multi-programmed at tne' two
level or the five-level in the case of the well-coded
program, T4~IXQR *, but is substantially degraded
for each additional job in the case of the casually
coded version, T4.1XQ. In fact, multi-programming at even the two level for that program is
(CASUAL CODE)
IMPROVED CODE)
BIFO REPLACEMENT ALGORITHM
I K PAGE SIZE
0.1 SECOND TIME SLICE
REAL CORE SIZE - I84K
PAGE REQUIREMENTS 129 PAGES/JOB
NO LOAD LEVELER
o T4.IXQR *(MOST
Multi-programming measurements
The importance of programming style to paging
behavior was clearly demonstrated in the single
programmed part of this study. We were interested in learning if it would have similarly dramatic effects on performance in the domain more
common to paging systems, i.e., multi-programming. Because the most notable changes in behavior were observed in the sorting area, we
decided to plan our measurement efforts around
these programs. An extensive measurement program was undertaken which was designed to give
us insight into the relative effects on perf'Ormance
of the following: programming style, page replacement algorithm, size of real core, number of
users and scheduling. It should be noted that the
question of performance in a multi-programmed
environment involves b'Oth the individual user
response and total system thruput capability. Although the study addressed both of these aspects,
the results discussed here pertain only to the
latter. (A complete in-depth report 'On the entire
multi-programmed measurement study is given
in Ref. 7, Part III.)
1029
1000
(J)
o
z
~
800
I
m
o
~
~ 600
~
400
200
~ /.
tlLo--o--o
--
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____ -
-
__ -
.
T4.IXQR
-OPTIMUM
_
T4.IXQ
OPTIMUM
2
3
4
5
MULTI-PROGRAMMING LEVEL
FIGURE to-Effects of programming style
T4-8orting (10,000 10-word items)
worse than running sequentially. (For T4.1XQR*
multi-programming is consistently more advantageous than running sequentially up through the
five-level. )
The effects of load leveling
One of the capabilities available on the M44/
44X system aimed at improving efficiency is that
of dynamically adjusting the load on the system
in order to attempt to av'Oid the overload condition which is characterized by excessive paging
coupled with low CPU utilizati'On. When this I'Oad
leveling function is activated, the system peri'Odically samples paging rate and CPU utilization,
compares them with pre-set criteria to determine
if a condition of overload 'Or underload exists, and
then takes action appropriately to adjust the' system load by either setting aside a user, i.e., removing him temporarily from the CPU queue, or' restoring to the queue a user who was previously
set aside. The function of the load leveler is thus
essentially one which affects· scheduling.
The extremely poor behavi'Or e.~hibited by the
casual code when multi-programmed made this
case a likely candidate for studying the effects of
load leveling. Figure 11 shows the remarkable
improvement which the load leveler achieved
1030
Fall Joint Computer Conference, 1968
b.
A
o
1200
1000
T4.1XQ
(CASUAL CODE) -NO LOAD LEVELER
T4.IXQ
(CASUAL CODE) - LOAD LEVELER ACTIVE
T4.IXQR* (MOST IMPROVED CODE) NO LOAD LEVELER
BIFO REPLACEMENT ALGORITHM
I K PAGE SIZE
0.1 SECOND TIME SLICE
REAL CORE SIZE -184K
PAGE REQUIREMENTS
129 PAGES/JOB
•
•
•
b.
500
BIFO)
AR
LOAD LEVE LER
FIFO
6.
o
BIFO)
.
AR . NO LOAD LEVELER
O· FIFO
REAL CORE· SIZE - 64K
IK PAGE SIZE
~400
z
0.1 SECOND TIME SLICE
~
PA~E REOUIREMENTS-129 PAGES/JOB
o
fa
(J)
~ 300
o
~
ILl
:I:
i=
b.
/~~~
.200
O~_O _ _O _ _ O
100
400
200
~
-
-
-
T4.IXQR*
- . - - ----OPTIMUM
,
~:l
~~~~~
OPTIMUM
-------_T4.IXQ
OPTIMUM
:3
4
5
MULTI- PROGRAMMING LEVEL
FIGURE ll-Effects of load leveling
T4-Sorting (10,000 10-word items)
2
3
4
MULTI- PROGRAMMING LEVEL
FIGURE 12-Effects of page replacement algorithm
T4.1XQR*
when there were three or more jobs involved. UnlXQR* multi-programmed (up to the five-level)
fortunately, the efficiency is still sUbstantially
with only 64K 'Of real memory available to the enworse than in the sequential case. We nonetheless
tire system, i.e., shared by all the users. The level
feel that the p'Otential for improved performance
of multi-programming for which the efficiency is
achieved through the use of an automatic dynamic . optimum is in all cases three; however, in the case
facility such as this is promising and indicative
of the AR algorithm, multi-programming at the
that it would be well worth implementing-in parfive-level with only 64K 'Of real memory is still
ticular if it can be kept simple and efficient as is
more advantageous than running the five jobs sethe case with the M44/44X load leveler.
quentially (with the same 64K of real memory).
Note that this is also true when running under
The effects of page replacement algorithm
the other algorithms with load leveling.
As might have been suspected from the singleprogrammed MIN study, the role of the page· replacement algorithm appears to be 'Of relatively
little significance. In the case of T4.1XQ, runs
were made using the more sophisticated AR algorithm but the data collected differed little from
that obtained for the BIFO algorithm. Similarly,
in the case of T4.1XQR* the difference in the results is inconsequential for those runs made where
all 'Of real core (184K) was available. (Figures
10 and 11 show the BIFO data.) However, when
the same T4.1XQR* runs were made with the real
core size restricted to 64K there was some change
in performance for the different replacement algorithms. The curves in Figure 12 compare the
effects of using the different algorithms for T4.-
The effects of real size
Performance is so pour for the 'T'4.1XQ program
given the full 184K of real memory, that it is obviously unnecesary to show how bad things would
be given an even smaller memory! In the case of
T4.1XQR * however,performance fur the system
is so close to optimum that we were curious to
learn just how small the real core size could be
before performance would be worse than in the
single-programmed case (for the same size of
real memory). The curves in Figure 13 compare
Time/Job for the single-programmed case, with
multi-programming at the three and five levels for
different real core sizes. Runs were also made
mJ,llti-programmed at the five level with the load
Program Behavior in Paging Environment
the question of individual thruput .(or resp'Onse)
time in the data shown here; however; we have
shown that total system thruput is most certainly
affected by the programming style employed by
the users on the system. We have shown in our
other work (Ref. 7) that this is als'O true for individual response time (often even if system thruput is unaffected).
AR REPLACEMENT ALGORITHM
I K PAGE SIZE
0.1 SECOND TIME SLICE
PAGE ~EQUIREMENTS-I29 PAGES/JOB
NO LOAD LEVELER
----0
SUMMARY
~~O-------O
~-----~~·----O
~
100
32K 48K 64K
96K
1031
128K
1841<
REAL CORE SIZE
(K·,024 WORDS)
FIGURE 13-Effects of real core size
T4.1XQR*
leveler activated and real core sizes of 48K and
32K. As can be seen in Figure 13, while improving
performance, the load leveler was not able to improve it sufficiently to compare favorably with the
single-programmed sequential case.
When viewed· in the perspective of page requIrements per job, the performance of the system is
remarkable for the well coded program. Five jobs,
each requiring 129 pages, shared a 32K memory
and still behaved reas'Onably well! (The time per
job is even a few seconds less than that required
for the overlapped 2-way merge conventional
code.) On the other hand, the performance for the
casual code given the full memory capability of
184K is at best (load leveled) quite a lot worse
than sequential and at worst (not load leveled) a
minor disaster.
The data which we have presented here on
multi-programming represent only part of that
collected for the stUdy. The cases chosen are obviously the extreme ends 'Of the spectrum. One
would not (hopefully) encounter all "bad" programs running at the same time on a system under
real time-sharing conditions, nor (regretfully) is
one likely to encounter all "good" programs. The
real situation lies somewhere inbetween-and
most likely, so does the characteristic perform~
ance of the system. We have not directly addressed
The single programmed data presented in this
paper give strong support to the conclusion that
the effects of programming style are of significant
consequence to the question of good performance
in a paging system. Indeed, as the MIN results
indicate, the basically external consideration of
programming style can be considerably more important than the internal systems design consideration of replacement algorithm. We feel that data
obtained for the multi-programmed case, some of
which were presented in the previous section, further support our conclusions. In view of these
results, we feel that this aspect of performance
must not be disregarded in future endeavors t'O
implement paging systems. Programming techniquesshould be developed at both the user and
system levels which are aimed at achieving acceptable performance on such systems. For example,
higher level language processors such as FORTRAN should be designed for paging systems to
produce good code for the environment as well as
to perform well themselves in that environment.
While we support the stand that paging and
virtual machines are inherently desirable concepts
with much potential, we strongly feel that in order
to fully realize that potential in terms of practical
performance characteristics, the notion 'Of programming with complete unconcern for the environment must be discarded. Our data have
~hown, however, that one can often realize acceptable performance by employing even simple
techniques which acknowledge the paging environment. Their simplicity leads us to feel that the
programming advantages inherent to the concept
of virtual systems can, to a great extent, still be
preserved.
ACKNOWLEDGMENT
We would like to acknowledge E. S. Mankin for
his extensive contribution in preparing the test
load programs for the sort area.
1032
Fall Joint Computer Conference, 1968
REFERENCES
1 RWO'NEILL
Experience using a lime-shared multiprogramming system with
dynamic address reZocation hardware
SJCC Proceedings Vol 30 1967 pp 611-621
2 PWEGNER
Machine organization for multiprogramming
Proceedings of 22nd ACM National Conference Washington
DC 1967 ACM Publication P-67 pp 135-150
3 GHFINE CW JACKSON PVMCISAAC
Dynamic program behavior under paging
Proceedings of 21st ACM National Conference Washington
DC 1966 ACM Publication P-66 pp 223-228
4 Adding computers-Virtually
Computing Report for the Scientist and Engineer Vol III No
2 March 1967 pp 12-15
5 The M 44f4.4X user's guide and the 44X reference manual
IBM Corp T J Watson Research Center Yorktown Heights
New York September 1967
6 LABELADY
A study of replacement algorithms for a virtual storage computer
IBM System's Journal Vol 5 21966 pp 78-101
7 BSBRAWN FGGUSTAVSON
An evaluation of program perJormance on the MJ,.J,.f4.J,.X system
Parts I II III
R C 2083 IBM T J Watson Research Center Yorktown
Heights May 1968
8 PJDENNING
Working set model for program behavior
CACM Vol 11 5 May 1968 pp 323-333
9 A C McKELLAR E G COFFMAN
The organization of matrices and matrix operations in a paged
multiprogramming environment
Princeton University Technical Report No 59 February 1968
10 CARHOARE
Quicksort
Computer Journal Vol 5 April 1962 to January 1963 pp 10-15
JANUS: A Hexible approach to realtime timesharing *
by J. O. KOPF and P. J. PLAUGER
Michigan State University
East Lansing, Michigan
to meet the goals outlined above. JANUS has
proved to be far more powerful than we originally
expected.
INTRODUCTION
Motivation
A third generation computer seems to cause as
many problems as it solves; not because it is difficult to program or too problem directed-quite
the contrary. The problems arise because such a
computer lends itself so willingly to all applications-realtime data acquisition, process control,
scientific calculations, bookkeeping and conversational time-sharing. In· a nuclear physics laboratory, there are enough imaginative people interested in each of these subjects that eventually all
are implemented with some success. The central
problem, then, is to develop an operating environment compatible with open-ended development of
any or all types of computer usage. Ideally, one
seeks a standard operating system providing the
framework and resources to aid all such development.
In our case, the desired priority of computer
usage was to be: 1. realtime data acquisition and
control; 2. interactive on-line operations, especially data analysis; 3. background operation. In a
nuclear physics experiment, realtime operation
is normally characterized by immense bufferswhich are updated at each input event, rather
than transmitted as sequential data-indicating
the desirability of a small resident monitor, and
non-permanently dedicated interrupt routines and
buffers. Event rates as high as 50,000 events/
second may be expected, implying the need for a
powerful computer to perform quickly the operations necessary to each event.1 ,2
The Michigan State University Cyclotron Laboratory installed a Scientific Data Systems
Sigma-7 computer in January 1967. We have constructed operating system JANUS for the Sigma-7
*Supporled by the National Science Foundation.
The SDS Sigma-7
The SDS Sigma-7 is a high-speed, integra~ed
circuit machine with sophisticated timesharIng
hardware. 3 It features a 32-bit word, with displacement indexing by 8-bit bytes, half-words,
words and doublewords, and direct addressing to
128k words. Timesharing hardware includes master / slave modes, rapid context switching (~x
change- and Load_Program-Status-Doubleword ~n
structions), a powerful interrupt structure wIth
certain functions inhibitable under program control program traps which are independent of the
int~rrupt structure~ and mapping hardware.
The Sigma makes extensive use of scratch-pad
memories; integrated flip-flop registers whose access time is insignificant compared with core memory. Thus there are 16 distinct registers, effectively accumulators. Instructions normally reference one or more of these registers. In addition,
the computer treats these register~ as the fir~t
16 locations of memory: all instructions are ~al~d
for'register-register operations. The computer IS
thus effectively a two-address machine, where one
address space is a subset of the other. Furthermore four registers may be used in a block as a
deci~al accumulator (31 digits plus sign), seven
others may be used as index registers (post indexing) , and any even-odd register pair may be usedfor double precision work.
The hardware also makes use of hard-wired
table look-up and translation for certain fune ..
, tions. An example is the map. Memory is na~urallY
divided into 512-word pages. The map consIsts of
a scratch-pad memory of 256 bytes, one for each
page of virtual memory (virtual memory is the
full address space of the machine, independent of
1033
1034
Fall Joint Computer Conference, 1968
the actual core memory available). When the map
mally uses the lOP for conventional I/O operais in operation, the first byte of the effective virtions;- the DIO for acquisition and control.
tual address is used as an index to look up a transFigure 1 details the resources available on the
lation byte from the map, which replaces the origMSU
Sigma-7.
inal byte to form the actual address used to make .
the memory reference. As a result, contiguous
Other approaches
virtual pages need not be in contiguous actual
memory; under a properly initialized map they
Before going into the details of JANUS, we
act as though they are. Associated with each page
should perhaps explain why we felt existing apis a two-bit access process code which can inhibit
proaches were inadequate for our needs.
slavemode from writing, executing, or even readConventional realtime systems are usually
ing words in the page. In conjunction with a rapid
geared for one application, or one set of appliaccess dis.c (RAD) , this hardware provides the
cations. One cannot randomly start and stop arbiswapping control needed for efficient timesharing.
trary functions, even though the particular reIn addition, the computer has two major means
sources needed may be standing idle. In particuof communicating with the external world. The
lar, one cannot "batch" process (i.e. compile, load
Input-Output Processor (lOP, of which there may
and run a series of purely computational probe up to 8) is designed for sequential transmission
grams) to take advantage of the usually large
of data asyncronously with the operation of the
CPU time available between interrupts.
computer. The Direct I/O (DIO) provides for the
By dividing memory into foreground and backtransmission of one word at a time to or from the
ground areas, it is possible to operate, a batch
registers, under program control. JANUS norsystem in conjunction with one or more realtime
operations. Aside from the fact that either of
these areas is frequently; a) unused for long
periods of time or, b) inadequate for many jobs
that could be run in full memory, there is a more
sophisticated drawback. Since realtime operations
must often use the same resources as the batch, a
large resident monitor is needed to handle common
operations and to prevent confiictsJ-Furthermore,
since realtime operations occur on an interrupt
basis, the monitor must either be reentrant to
several levels or must inhibit interrupts while it
is active (or a little of both). The former solution makes the resident even larger and slowerthe latter interferes with fast response to realtime events.
Conventional time-sharing systems 4 can be
geared to provide the random stop/start of realtime which we desire, and are better geared to
adapt efficiently to dynamically changing memory
availability. But the usual approach has been to
take an already large foregroundlbackground type
monitor and to add a swapper, job scheduler and
elaborate
I/O queuing routines to the resident. The
~-f--- MONITOR
dedjcable memory left over can be vanishingly
small.
Figures 2 and 3 caricaturize the distinction we
made between what we saw in conventional approaches to realtime timesharing and what we
FIGURE 1-Hardware resources of the MSU Sigma-7 system.
envisioned for JANUS.
Items labelled "J" are handled by JANUS. Those labelled "S"
There still remains the problem, not yet menare shared by all users on a cyclic basis. All others are loaned out
tioned, of the hybrid job. It is often desirable to
on a first come, first served basis for exclusive use.
JANUS
1035
c::I:J
TRAP (HARDWARE)
S S S J J J J J
r-,-I-
c:::cJ
I I "
I I
I Lilli
I I I I
-
TRAPS
+'
Iva slNfERRUPT
r-:
f-
~
f-or
CLOCKS
r-+-
c::I:J
I-
r-+
f0-
INT. INTERRUPTS
r
c::I:J
MAP
DISKPAGES (684)
c:I::J
~
TTY (CONSOLE)
c=J
c::::J
c=J
[ilIJ
c::::J
c:::J
C=:J
RAD
TTY- PT
CR
MT
LP
010 REGISTERS (8)
SCRATCHPAOS (4)
EXT. INTERRUPTS (8)
c:=:J
CP
RESOURCE
JANUS
RESIDEN .....
T - -......
JANUS
REALTIME
TIMESHARING
FIGURE 2-Caricature of a "conventional" realtime timesharing system. It is characterized by a large resident monitor and
rather rigid frame-at-a-time use of remaining memory.
construct programs having a small realtime part
and a large problem-solving part that could happily be timeshared. The question is raised as to
specifying such an animal. How is communication
between the two parts effected?
We found the answers to these questions, and
the inspiration for answering many more, in the
definition of PL/I.5
Design of JANUS
Terms and philosophy
The PL/I language definition provides a vocabulary and a philosophy (we have probably corrupted both). In PL/I a piece of code containing
all routines needed to perform a job, or distinct
part of a job, is a task. A task can start one or
more subtasks to perform asynchronous opera..
PLOT
CHART
MSU L7
FIGURE 3-Caricature of JA~US system, with small resident
and intertwined tasks having both dedicated realtime and
timeshared pari,s.
tions; it can go into a wait state until certain
events, signalled by other tasks, occur, On can
specify on-units to be activated when conditions
are raised (interrupts or traps). These are the
terms needed to describe what JANUS does.
Equally important is the philosophy. PL/I is
a modular language with the built in attitude, "If
you don't know about this option, it isn't there. I
will do what you most likely want done." With
only 16k words of core memory, one must necessarily begrudge the presence of excess code. This
is the philosophy by which JANUS works.
It should be emphasized that JANUS does not
require the PL/I compiler to operate, nor do we
plan to write one. The concepts are quite useful
without the compiler.
Timeshared monitors
A monitor is used. to provide certain functions,
such as control and I/O, which a user either does
not want to implement himself, or cannot be
trusted with. However, these functions may be
made modular in. form, and can thus be loaded
from a library.
1036
Fall Joint Computer Conference, 1968
The amount of code that truly must be resident
in a timesharing system is really quite small. A
scheduler (JOB CHANGER) and RAD handler
(SWAPPER) are, of course, required. A console
teletype handler is rather important to initiate
system actions and to provide a common voice-ear
for all users. Other I/O handlers are not required.
If one extends the concept of a task to include
all the mastermode routines required for its execution, many interesting by-products result. First,
the resident requirements are drastically reduced.
If no one is reading cards, no card reader handler
is in memory. Second, each task can have a "tailornlade monitor." If task A never does realtime
operations, it has no such handlers in its mastermode end. Third, and perhaps most important,'
monitor routines need not be re-entrant. Each
talks only to one user.
All the resident must do is act as referee.
Peripherals, indeed any nonshareable system resources (interrupts, extra register blocks, disc
space) are handed out on a first come, first served
basis, and passed on to the next requestor when
released by the current user.
Naturally, such a scheme requires that all
mastermode routines be "honest," and completely
deb!lgged, but this is a rather ordinary requirement. A malicious or naive mastermode routine .
can cause damage any number of ways, so JANUS
assumes that no such routine exists and performs
virtually no checking. While it may appear that
spreading the responsibility for system integrity
over many routines increases the programming
load, the fact that each routine is a module with
clearly defined rules of construction actually
makes the coding job much easier.
Thus, JANUS is a system that timeshares
monitors, in the ordinary sense, and is itself
'Only a referee. Each monitor essentially patches
together the small computer it needs to perform
a specific operation, leaving all unused system
resources available for other tasks. Since, in general, no one job requires more than a few private
resources, another subsystem can be constructed
from the remainder, and then another, until the
entire system is active.
In the MSU implementation, the JANUS resident occupies 3.5k words (7 pages).
Resident and system tasks
The RAD is arbitrarily divided into approximately 680 diskpages, each holding 512 words of
useable information. Each distinct page of a task
or file has a unique diskname (16-bit) by which
JANUS can locate it. The first page of every
task begins at location X' COO' under the map and
is called the task control page (TCP). All information required by JANUS to bring in a task and.
start it up is stored in fixed locations in the first
34 to 283 words of the TGP, depending on the
size of the task. Thus. JANUS needs only know
the diskname of the TGP, called the taskname, to
bring in the whole task. With 16-bits of status
information, the taskname becomes a one-word
entry on the resident ring of active tasks..
Note' that a task sees only 3.0k of JANUS.
(Under the map, each task is executing in its
own unique address space of up tQ 128k-words,
generally independent of the available core
memory. Task address spaces diverge after 6
pages: the lower 3k are CQmmon to all tasks
and contain the major portion of JANUS.) The
remaining resident page is the TGP of the
HOUSEKEEPER task, the nonresident supervisor. Rather than maintain complete lists of
resources and requests in resident, JANUS maintains only token lists, tQ meet short-term needs,
and invokes the HOUSEKEEPER as needed tQ
tidy up lower core.
JANUS also serves as intermediary between
interrupt routines, which run unmapped in dedicated memory, and their cQntrQlling tasks, which
are mapped and not .necessarily in memory at
any given time. The most important service provided is the MESSAGE CENTER, the only multiply re-entrant resident routine in the system. It
will accept a 'One word signal (consisting a 16-bit
taskname and an 8-bit identifier) from any source
and pass it on to the specified task, pulling it
out of a wait stateif necessary. Great pains have
been taken to ensure that no signals are lost,
duplicated or rejected by JANUS.
CommunicatiQn in the other direction-alerting interrupts-is generally possible through the
. hardware. Interrupts can be triggered under program control. But since the I/O interrupt has a
software fan out to individual device handlers,
JANUS provides a software device-directed
trigger, or "kick," to aid communication. A
pseudo-acknowledgment status word is added to
a queue and the interrupt is triggered. The resident interrupt routine, after acknowledging all
real interrupts, empties the queue, passing the
contents to the individual rQutines. This feature
simplifies coding of I/O handlers, since all con-
JANUS
tro.I o.peratio.ns can be co.nfined to. the interrupt
end o.f the handler.
The last majo.r co.mpo.nent o.f the resident is
the co.nso.le teletype handler, used by all tasks
to. co.mmunicate with the o.perato.r. Output is
sequential in o.rder o.f request and may interrupt
an input. All co.nso.le teletype I/O is prefix directed to. the appro.priate task. A prefix Po.o.I is
available to. pro.vide unique prefices UPo.n request.
Prefices co.nsist o.f a byte co.unt, plus up to. 3
characters.
One prefix, the ampersand (&) is reserved fo.r
directing messages to. JANUS. A special task,
the AMPERSCANNER, deco.des these messages
and takes appro.priate actio.n. The AMPERSCANNER kno.ws where to. find, o.r ho.W to generate, all tasks built into. the system, and thus
is resPo.nsible fo.r initiating mo.st pro.cesses.
A third system task is the MORTICIAN, which
dissects dead tasks and files, and returns their
co.mpo.nent pages to. the system diskpage Po.o.l.
Other system tasks are an o.pen-ended set o.f
symbio.nts, used to. perfo.rm an I/O o.peratio.n with
a disk file. Tasks may either do. their o.wn I/O
o.r generate a file, and let the appro.priate symbio.nt perfo.rm the necessary I/O o.peratio.ns. Symbio.nts do. no.t take up any memo.ry space unless
they are actively wo.rking o.n a file. Only the
system tasks are immortal under JANUS. All
o.ther tasks are bro.ught into. existence fo.r a
specific applicatio.n and are interred when no
Io.nger needed.
Operation
Job changer
Figure 4 is a flo.W chart o.f the JOB CHANGER,
which is resPo.nsible fo.r entering and leaving tasks
between time slices, and fo.r delivering messa~es
(signals) to tasks. The Io.west prio.rity interrupt
is the jo.b-changing interrupt. It fires when its
co.rresponding co.unt pulse interrupt co.unts to. zero
(o.r when triggered by 'a CPU instructio.n), and
transfers co.ntro.I directly to. the task mo.nito.r to
perfo.rm register saving and any o.ther slice-end
functio.ns needed befo.re branching to. the JOB
CHANGER.
Similarly at slice-start, the JOB CHANGER
gives the task mo.nito.r an o.PPo.rtunity to. pro.cess
signals and resto.re registers befo.re co.ntinuing.
A special purpo.se task thus has the o.ptio.n o.f
streamlining both ends o.f the pro.cess. N o.te that
a task a~so has the o.ptio.n o.f putting itself on
1037
high prio.rity, a status such that it must be the
next task executed, altho.ugh this practice is disco.uraged.
No. attempt is made to. co.mpute an "o.ptimal"
slicetime. This interval is fixed by an empirical
tuning pro.cess and is currently 0.1 seco.nd.
Swap per
A flo.W chart o.f the SWAPPER algo.rithm is
sho.wn ill' Figure 5. Once the TCP o.f the next
task is in memory, the SWAPPER wo.rks fro.m a
variable length table in the TCP to. determine
what pages must be bro.ught in (or Io.cated in
memo.ry) to. permit the task to. proceed.
Since it' takes an average o.f 28 milliseco.nds to.
read o.r write one page o.f memo.ry to. the RAD,
whenever possible great effo.rt is made to. avo.id
actually swapping. So.me o.f the techniques used
are:
1) Sto.rage areas are gro.uped to.gether, beginning o.n a page bo.undary, so. that all o.ther pages
can be flagged "read o.nly." Thus, the SWAPPER
kno.ws no.t to. write these pages back to. the RAD.
2) Slavemo.de sto.rage areas are at first writepro.tected, so. that the task mo.nito.r can info.rm
the SWAPPER (via the TCP table) whether o.r
no.t a page has been mo.dified.
3) Only those pages o.f a task which are
kno.wn to be needed (o.r fo.r which usage cannot
be mo.nito.red) during the next timeslice are
flagged "must be in next time" o.r "must be in
everytime. "
4) A fo.ur-level "usage prio.rity" is maintained
fo.r each page of real memo.ry (see Figures 4
and 5). After each timeslice it is' set to. a high
value if used, reduced to.ward zero. if no.t. As a
result, pages are "turned" acco.rding to. a weighted
LRU (Least-Recently Used) algo.rithm. A page
which must be written back has a higher weight
than o.ne which do.es no.t. Other weight criteria
may also. be established. This simple trick helps
the JOB CHANGER and SWAPPER "learn" the
best way to. use memo.ry as the system lo.ad
changes.
Such great pains were taken to. impro.ve swap
efficiency, in fact, that a wholly unexpected bypro.duct was created. Slavemo.de memo.ry usage
could be monitored so clo.sely that the slave portion of a task need never be all in memory at once,
but instead pages would be brought into. core
upon demand. Thus a pro.blem-solving program
could be written Ulsing the full 128k address space
1038
Fall Joint Computer Conference, 1968
FIGURE 4-Flow chart for JOB CHANGER (scheduler). It operates at lowest priority interrupt level.
YES
CLEAR '~SK
READY' FLAG
FIND TCp,SET MAP
SET ALL AC=3
RETURN SIGNALS
AND REMOVE
TASK FROM WAIT
JANUS
1039
FIGURE 5-Flow chart for SWAPPER. It operates at I/O interrupt level whenever RAD operation completes or software
"kick" is administered by JOB CHANGER.
1040
Fall Joint Computer Conference, 1968
of the-machine and, with no alteration, run on a
Sigma-7 with as little as 8k of actual memory, al.
though less efficiently than in the full machine.
Demand paging
Figure 6 is a flow chart of the demand paging
algorithm. It is implemented as an optional task
monitor module (a pure process control task
would have no use for this feature), and occupies
250-words. Whenever an access protect violation
is signalled via the Nonallowed Operation trap,
the routine is entered to detennine a) what page
reference caused the trap and b) whether it was
indeed an error or a valid reference. If the latter,
the page is made available and usage is noted.
The routine is time consuming because the
access protects were not originally designed for
this purpose, and hardware deficiencies must be
made up in software. .But each page traps at
most twice during each 0.1 second timeslice, and
the possible gain in information weighs heavily
against 28 milliseconds per page swaptime.
Except for the Execute instruction, which is
infinite level, no Sigma-7 instruction can access
more than five pages before reaching an exit
point. With special handling for execute, this five
.page limit applies to all cases. Consequently,
timesharing can be maintained as long as there
are sufficient non-dedicated pages of memory to
hold the largest task monitor, plus five slavemode pages. The MSU Sigma-7 thus has over
half its 16k memory dedicable for I/O and other
realtime processes.
FIGURE 6--Flow chart of Demand Paging algorithm, a 250-word routine ,which may be included in a task monitor to permit
task to occupy full 128k virtual memory. It operates whenever Nonallowed Operation trap occurs in the task.
JANUS
· STRUCTURE
AND
INTERNAL CaJlMUNICAT ION
UNDER JANUS
INTERRlJ'T (REAL-TIME)
ROUTINE AND
ASSOCIATED
UNIQUE STORAGE
~
INTERRUPT CONTROL
~
STORAGE COMMaI!· TO BOTH REAL-TIME AND CONTROL
FUNCTIONS (INTERSECTION)
'---
L
CAL TRAPS
COMMON STORAGE
AN~
SLAVEMODE
(COMPUTATION)
ROUTINES AND
ASSOCIATED
UNIQUE STORAGE
---
MASTERMOOE (CONTROL)
ROUTINES AND
ASSOCIATED
UNIQUE STORAGE
ROUTINE
PRIVILEGED
SIGNALS
CJ
INSTRUCTIONS
FIGURE 7-Typical realtime (I/O) driver. This illustrates
optional three-part division of labor and modes of communication
bet ween parts.
Efficiency
It is difficult to measure the overall efficiency
of the JANUS system, because loading changes so
rapidly with even the simplest uses. Several extreme cases can be cited, however, to provide a
feel for overall parameters:
1) In the case where all active tasks fit in
memory at once, the SWAPPER "learns" in about
1 second that all codes should be in memory.
Afterward, the time spent in the JOB CHANGER
and SWAPPER (overhead) drops to less than 5 %
total CPU time.
2) The FORTRAN optical model code GIBELOMP, which requires approximately 35k words
of slave code in a Sigma-7, registers a swap
overhead (the fraction of time not spent in slave
problem-solving mode) of 20% when running
alone in the machine.
3) While it is possible to create pathological
cases where swap overhead would exceed 99%,
system processors and compiled code seUlom
burst over 50 % overhead.
These figures are, of course, degraded as available memory decreases or external interrupt load
increases.
CONCLUSION
JANUS has proved to be a viable solution to the
needs outlined in the introduction. By extending
the concept of realtime operations to include all
I/O operations, a small resident is possible, permitting the use of most of memory for produc-
1041
tion. Whether that production is realtime data
acquisition, computation, or a mix is irrelevant-it can 6roceed if the necessary resources are
available. Any realtime process can interrupt the
system or background processes at all times, permitting high data rates. The ability to run large
computation codes with reasonable efficiency, and
in a timesharing environment, is an unexpected
boon.
While the concept of timesharing monitors does
permit a minimal resident supervisor, it would
appear to suffer from the need of writing specialized monitors for the library. However, certain facts should be kept in mind. Each monitor is
no more complex than a· corresponding standalone system would be-only the rules are different. Each monitor need contain only those
function~ necessary and sufficient for the task in
question. The various functions are modular; once
a specific function has been coded, it may be
placed in a library for future use, rather than
having to be recoded again and again. Given such
a library of monitor functions, it is possible to
define a system loader (actually a task maker)
which can generate a tailor-made monitor. This
sort of operation is not uncommon in single-user
monitors, where, for example, a magnetic tape
handler is included only if the programmer references it implicitly or explicitly. It is not an overly
restrictive requirement that the possible set of
operations to be performed be known before execution is started.
Demand paging requires some form of map
with protection, as well as an external storage
medium. Although there is some controversy as
to the value of demand paging in a timesharing
environment, JANUS demonstrates the value of
the concept in situations of single user, limited
memory machines. While overhead for problems
which fit into core is minimal, larger problems
can also be run, although at lower efficiency, at
less monetary cost than would be incurred by an
increase in core memory. Given demand paging,
additional memory increases efficiency. Comparing
an open-shop, small demand-paged computer with
a closed-shop computation center, turn around
time is significantly reduced, even if the actual
computer running· time is increased by orders of
magnitude.
The Sigma-7 is an admirable machine for timesharing, but was not designed with demand paging in mind. Certain features necessary for demand paging, while capable of being implemented
1042
Fall Joint Computer Conference, 1968
by software, would be much more efficient if implemented in hardware. These include: 1. Scratchpad registers, readable and clearable under computer control, which would automatically keep
track of all pages referenced and modified. 2. A
more powerful hierachy of operation modes and
a different sequence of protection. A better
sequence of protection might be: write permitted,
write permitted from master-mode, no write permitted, and no access permitted. Master-slave
modes of operation should be expanded to the
point where the protection could optionally apply
to master-mode thus permitting demand paging
operation of such code. 3. A privileged instruction which would interpretively execute any instruction, and return the reference which would
cause a trap. Other features, such as a readable
map, would be of great use.
In conclusion, we feel that JANUS may well
serve as a model for future computer systems,
due to its flexibility and lack of constraints. As
much as possible, limitations on computer usage
are set by hardware, rather than by 8ystem conventions.
REFERENCES
1 J A JONES
On-line computers lor research
Nucleonics p 34 Jan 1967 A survey of the field containing many
references which will not be duplicated here
2 JBIRNBAUM M M SACHS
Computer and nuclear physics
Physic~ Today p 43 July 1968
3 SDS Sigma-7 computer reference manual (#90009-506)
Scientific Data Systems Santa Monica California May 1967
4 BWLAMPSON
A scheduling philosophy for multiprocessing systems
Communications of the ACM p 347 May 1968
5 IBM System/360 operating system-PL/I language specifications (#C28--6571-4)
IBM Corporation New York New York Dec.. mber 1966
A parallel process definition and control system
by DAN COHEN
Harvard University
Cambridge, Massachusetts
ternally to indicate failure, or externally to indicate that
this process is not needed.
The combinations of f, g, h may be interpreted as:
INTRODUCTION
(1)
General
The purpose of this work is to supply a simple method
for definition and efficient control of a network for asyp.chronous parallel processing.
The system is able to compile a definition of a network of processes which run partially in parallel and
partially sequentially, into a set of control instructions
for some monitoring process, to be executed at run time.
The defined network is composed of a set of interrelated processes and a monitoring process which initiates
processes according to some dynamic conditions. Typical resources for processes are processors, I/O devices,
memory banks, and bulk storage.
The system discussed below is concerned with two
tasks, the handling of raw input statements (the network definition language and its parsing algorithms),
and the network control process, which initiates and inhibits processes as they become needed or unnecessary.
(S)
f
0
0
0
0
g h
0 0
0 1
1 0
1
1 0
1 1
1 0
1 1
(3)
1
0
0
1
1
reset
the process is not needed
illegal
illegal
initiated
sucessfully completed
failed or not needed
successfully completed
The control language
Each process, p, has two propositions associated with
it:
b(p) which is 'TRUE' if p has already started, and
c(p) which is 'TRUE' if p was successfully completed.
The states of the processes
Anetwork is defined by a set t>f statements {S,} of the
Each process at any time can b~ in one of the following states:
(a)
(b)
(c)
(d)
(e)
form:
reset (not initiated)
initiated
successfully completed
failed
not needed
where the {f i} are propositional functions, which contain
AND and OR.
The meaning of Si above is that when f, is 'TRUE' then
b(pi,) is set to 'TRUE' (which initiates the process p, if it
was not already initiated). For a more convenient notation, we write Pk for C(Pk) on the left hand side, and write
Pk for b(Pk) on the right hand side.
Statements with identical propositional functions are
combined by writing their propositional functions on
the left, and writing the set of all their right hand sides,
on the right. Example:
However there is no need to distinguish between
states (d) and (e). Each process has three binary variables f, g and h to indicate its state.
f = 1 : the process was initiated.
g = 1 : the process was successfully completed.
h = 1 : the process failed or was found not needed.
The f variable is set externally to initate a process.
The g variable is set internally by the process to indicate its completion. The h variable may be set in-
1 =} means logical implication. e.g. x
impliesy = 1
1043
=}
y means that x = 1
Fall Joint Computer Conference, 1968
1044
+ c(B) & c(O) => beD)
c(A) + c(B) & c(O)::::} beE)
c(A)
2
is written as:
A + B &C
= > D, E a
An example for definition of a network
s ::::} A, B
read: start with processes A and B
(s for start)
B & C::::} D, E
read: When Band C
are successfully
completed initiate D and E
A
+ B::::} C, D
When A or B is
successfully
completed initiate C and D
read: When (CandD)
or E is successfully completed,
end (e for end).
read:
Let L be the left hand side of a statement (Le, the propositional function) and let R be the set of the processes
which are initiated when L is 'TRUE.' Hence each
statement has the form:
(read: L, implies R,)
We say that p is used in L ::::} R, if L contains p.'
Any process which is used by the network, but is not
initiated by it, like s, is called a source-process, and its
beginning is a source of the network.
Any process which is initiated by the network, but
not used by it, like e, is called a sink-process, and its end
is a sink of the network.
Each network must have at least one source. A circuit-free network has at least one source and one sink.
(3.1)
(3.2)
initiated only once (3.2.3)
(d) separate AND from OR (3.2.4)
(e) transform the network so that each process is
used only once (3.2.5)
(f) simplification (II), if possible (3.2.6)
Each simplification (I) step is applied as soon as it
applicable.
This ordering of the steps insures that no reduction
steps except simplifications are needed as a result of a
later step.
.
After this procedure the input statements are reduced
to a "graphable" form, where the definition statements
correspond to vertices, and the processes correspond to
edges. Because of the AND/OR separation (3.2A) each
node can be represented by an AND or OR gate.
During the reduc_tion dummy processes are created,
which can be recognized as such, thereafter. The role of
these dummy processes is similar to the role of temporariesin program compilaticn. All dummy processes are
created and named only by the compiler. We will name
all dummy processes hereafter by q ,. Dummy processes
have no duration, and do not need any time or resources
to be executed. They serve to eliminate ambiguities
in the network definition. The nature of these processes
will be made clear in (3.2.3), (3.2.4) and (3.2.5) below.
Note that this reduction is not a complete optimization.
(3.2.1): validity checking.
There must be at least one source to any network.
(3.2.2) : simplification (I)
The simplification is not essential, however it may
save time and space and therefore is desirable.
(a) is s is the only source of the network then replace s & p by p, and s + p by s, in any L.
(Note that we drop subscripts for processes, for
simplicity. )
(b) If e is the only sink of the network, then if
{e,p} E R, delete p from R. If p is initiated only
in this statement, replace c(p) by 'false' whereever p is used.
(c) Apply any available method of propositional
calculus ::simplification, to L. (i.e.,· replace A +
The control language processor
The input statements are compiled into a set of control instructions to be executed at run time. This compilation has two stages. The first stage checks validity
(and outputs diagnostics) and reduces the input statements to some "graphable" form. D The second stage
produces control instructions according to the reduced
statements.
(a) check validity (3.2.1)
(b) simplification (I), if possible (3.2.2)
(c) transform the network so that each process is
The reduction procedure
2 ± and & mean logical OR and AND. The AND takes precedence over the OR.
aD, E means the set{D, E}.
"i.e., c(p) appears in thepropositionalfunction, L.
'The meaning of a "graphable" form is explained later, in
(3.2)
Parallel Process Definition and Control System
~1------"
)=z
« ~~~'4
t3-----
~2----
A
L1
B
q
i, repLaced by
~~
~
£1-----12
i3
FIGURE I-An example for rule (3.2.2.f)
A by A, and A + A & B by A.)
(d) Delete L =} II
(e) Replace L =} Rl and L =} R2 by L =} R11 R2
(f) Delete q =} R (where q is a dummy-process),
and replace q by R, where q was initiated. See
Figure 1.
(g) Delete p =} q (where q is a dummy-process,
and p a process) and replace q by p wherever
q is used. See Figure 2.
(h) Delete statements of the form 'FALSE' =} R. If
some process pER is initiated only in this
statement, replace c(p) by 'false' wherever pis
used.
(3.2.3): Uniqueness of initiation
C
L2.
0
is
Ll =} ql, Rl - (R1
~=}
/\
R 2)
q2, R - (RI /\ R 2)
repLaced by
A
B
L1
C
0
L2
FIGURE 3-An example for rule (3.2.3)
qi
+ q2=} RIA R2
where ql and q2 are new dummy processes.
Example: Ll
placed by:
=}
A, B, C and L2 =} B, C, D are re-
This rule is illustrated in Figure 3.
(3.2.4): OR/AND separation
If any process is initiated more than once then there
are Ll =} Rl and L2 =} R2 such that Rl /\ R2 :;C 0, i.e.
there are common terms in the sets Rl and R 2. In this
case replace Ll =} Rl and L2 =} R2 by:
1045
Any statement which contains both AND and OR is
converted to several statements which use only AND or
OR. Some dummy proc~sses are used to represent subcombinations of processes (the same way compilers use
temporaries). A simple precedence reduction analysis
suffices. For simplicity here, let us assume that L is
converted to, or is given as a sum of products: L =
Sum of products may be simplified by using the
idempotant and absorption rules.7 In this case replace
L=}R by:
L1I"i.
is repLaced by
6
FIGURE 2-An example for rule (3.2.2.g)
0 is the empty set.
7 The absorption rule: x
rule: x + x = xandx&x = x
+
x & y
x The idempotent
1046
Fall Joint Computer Conference, 1968
where the {q,;} are new dummy processes. Repeat this
step as necessary, until all the statements are ANDstatements or OR statements.
The similarity between dummy processes and temporaries in program compilation may be illustrated by
the following example. Consider the statement:
A
A------+f
~----------~~
8----=::::::-
J-------. rZ
C-------.c
+ B * C * (D + E) ~ F
is replaced by
As an arithmetic statement it may be compiled as:
D+E~1\
B
* C * Tl ~ T2
A+T2~F
D+E~Tl
)
Tl and T2 are temporaries
ql~q2
B--...c
c-------..t
,
As a process statement it may be compiled as:
B& C&
A--------., )-------------. r1
ql and q2 are dummy processes
8ee Figure 4.
(3.2.5): uniq~eness of usage
If some process, p, is used m > 1 times, then add
p ~ {ql, q2 .... qm}, and replace p in its nth usage by q.
(these {q n t are new dummy processes). See Figure 5.
1-----------. r 2
FIGURE 5-An exa~ple for rule (3.2.5)
(a) p + El ~ q and q + E2 => R, where q is a
dummy process is replaced by p + El + E2 =>
R. 8ee Figure 6.
(b) p & El => q and q & E2 => R, where q is a
dummy process is replaced by p & El & E2 ~
R. 8ee Figure 7.
(3.3) : Example
(a) The input statements:
(8 1) s=>A,B
(3.2.6): simplification (II)
8implification (II) like simplification (I) is not essential, hut may save time and spa~e. It may be done only
after (3.2.3) OR/AND separation, and (3.2.4) uniqueness of initiation, are completed.
A - - - - - - -...
t---~F
B--------,.
c------..
0--------,.
(82 )
(83)
A+B~C,D
B~D ,E
(84 ) C&D
(b) D is initiated twice, in 8 2 and in 8 3 • Apply
(3.2.3) :
(81)
s~A,B
(82) A+ B=*C,ql
(83) B =* q2, E
(84) C & D
(84) ql
FIGURE 4-An example for rule (3.2.4)
+ E =* e
+ q2~D
lc) 8 4 contains both AND and OR. Apply (3.2.4):
(81) s~A,B
(82) A
B~C, ql
(83) B~q2,E
(84) qa
q4 =* e
(811 ) ql q2 =* D
(86) C & D =* qa
(s,) E =* q4
+
E------I
+ E~.e
+
+
Parallel Process Definition and Control System
p
1047
(e) B is used twice, in 8 2 and in 8 a• Apply (3.2.5)
(81)
(82)
(8 a)
(8,)
(85)
(8s)
(8,)
)..-----I~R
q. =:} q2, E
qs + E =:} e
q1 + q2 =:} D
C & D =:} qa
B =:} q& , PII
(f) step (f) of simplification I, can be applied to 8 a,
and 8,:
is rep/aced by
(81)
(82)
(8 a)
(8,)
(85)
(8s)
(8,)
p
__~-=:---..J~J-_------"~
s =:} A, B
A + q&=:} C, q1
R
s =:} A, B
A + q. =:} C, ql
deleted
qa + E =:} e
q1 + q2 =:} D
C&D=>qa
B =:} q&, q2, E
No more reduction rules can be applied. The network
is now in a "graphable" form, as shown in Figure 8.
FIGURE a-An example for rule (3.2.6.a)
p
R
FIGURE 8-The
lS
replaced by
p
---:~:-~
..... 8t J-----~.R
FIGURE 7-AiJ. exmple for rule (3.2.6.b)
Now we assume that the input statements have been
reduced to their "graphable" form, as described before.
The next goal' is getting instructions for updating the
process variables f,g and h. These instructions are
executed at run time by some monitoring process. Let
{.e i} be the processes used in L, and {rj} the processes in
R.
Lt,
(4.1) A set of rules for compiling
=:}{rj}
can be written:
(4.1.1) If any t i in L succeeds, initiate R (success
forward):
(81) s =:} A, B
+
+
of example (3.3)
(4) Compiling the input statements to control instructions
(d) step (g)of simplification I, can be applied to 8"
and 84 :
(82) A + B=>C, q1
(8s) B =:} q2, E
(84) qa E=>e
(8&) q1 q2 =:} D
(811 ) C & D::::} q3
~etwork
8 -+
x+y.
means replacing (setting) e.g. x -+ y means replace y by
'
. 1048
Fall Joint Computet Conference, 1968
A
D
A
B--------
c
t----~D
E
c
FIGURE 9-An eXample for (4.1)
B
FIGURE lo-An example for (4.2)
Example (Figure 9): if A, or B, or C succeeds, initiate
DandE.·
(4.1.2) If all {.e d in L fail, then R is not needed
(failure forward):
Example (Figure 10) if A and B succeed then initiete
C,D,andE.
(4.2.2) If any t i in L fails, then R is not needed
(failure forward) .
Example (Figure 9): is A, and B, andC fail, so do D
andE.
.
Example (Figure 10): if A or B fails, so do C, D and E.
(4.1.3) If R is not needed, th~n L is not .needed
either (failure backward):
(4.2.3) If R is not needed, then L is not needed
either (failure backward) :
TIh(ri) -+ {h(t.)}
Example (Figure 9) : if D and E are not ne-eded, neither
are A, Band C.
.
Example (FigurelO) : if C and D and E are not needed
neither are A and B
(4.1.4) If any ti in L succeeds, then its brothers
are not needed (inhibit brothers )10
(4.2.4) If any t i inL fails, then its brothers are
not needed (inhibit brothers):
Example (Figure -9): if A succeeds, Band C are not
needed. If B succeeds A and C
are not needed, etc.
Example (Figure 10): if A fails B is not needed. If B
.
fails A is not needed.
II
(4.2) A set of rules for compiling t i ::::} {ri} can
written:
(4.2.1) If all (, i in L succeed, initiate R (success
forward) :
IIg(t ,) -+ {f(ri)}
The overbar means ·logical complementation, e.g.
and i = o.
9
'0
=
I
10 Processes which terminate at a common vertex are called .
"brothers" here.
The statement p ::::} R can be compiled according to
either rules. However we consider one input node as an
AND node. Note that (4.2.4) is not necessary as it is implied by (4.2.2) and (4.2.3).
For each dummy process, q, the setting instruction of
f(q) is replaced by the setting instruction of g(q).
The purpose of the rules set forth in 4.1 and ·4.2 is to
inhibit the execution of processes which are not needed,
and to initiate the execution of processes which are
needed. A networ~ with one sink only, is always inhibited upon arrival at it.
Parallel Process Definition and Control System
1049
(4.3) Example:
FIGURE ll-The network for example (4.3)
I. Consider the time-slice B-D-C, as marked on the
graph in Figure 11. Say that D fails there at that time.
Then (4.2.2) inhibits G and H, (4.2.3) or (4.2.4) inhibits
E, (4.2.2) inhibits J. and (4.2.3) inhibits F and B. This
means that process B, already initiated, is told to quit,
since its success is not necessary to produce "e". This
leaves only A, C and I not inhibited.
II. Consider process I completed. Process J is now
deemed useless, and is turned off, as are its "parents",
F and H.
A computer system for automation of a laboratory
by P. J. FRIEDL, C. H. SEDERHOLM,
T. R. LUSEBRINK and C. J. JENNY
IBM Scientific Center
Palo Alto, California
INTRODUCTION
In the past,. scientists have applied the digital
computer in an off-line fashion to the problems
of analyzing the voluminous data pr.oduced by
their laborat.ory instruments. The use of computer techniques for digital filtering, peak
finding, and spectral dec.omposition has greatly
increased the rate at which experimental data can
be analyzed. More recently, many instrument
manufacturers and users have also begun to apply
computers on-line t.o their instruments in an effort
to increase the rate· at which useful experimental
data can be .obtained. This paper describes a laborat.ory automati.on computer system which simultaneously supports multiple closed-loop experiments and data analysis programs.
Let us first distinguish between instrument
aut.omation and lab.oratory aut.omation. In the
f.ormer case a single computer, usually small, is
devoted to a single instrument, or at least to one
instrument at a time; whereas in lab.oratory automation, a gr.oUP of instruments in a laboratory
is automated using one central cQmputer system.
A discussion of the relative advantages of these
two modes .of autQmation follows.
There are several advantages to a dedicated
c.omputer. The most important of these is that of
iSQlation. Each individual user prefers to cQncern:
himself with his own problems. He dQes not want
malfunctions of other instruments or their interfaces tQ j eQpardize his experiment. Pr.ogramming cQnsiderati.ons associated with his .own instrument are sufficiently complex that he doesn't
want to worry about other users' pr.ogramming
pr.oblems too. He is rightfully afraid .of being
forced to factor parts .of his pr.ogramming requirements int.o general purpose programs which
serve the entire laboratory (programming by
committee) .
Immediate accessibility to the c.omputer system
can be guaranteed in a devoted computer configurati.on. This fact also errc.ourages one to favor
multiple C.omputers, .one per instrument; h.owever,
if a time-shared computer system could almost
always be made available in a period of a few
seconds, or at most one or two minutes, this would
not be intolerable. The prospects, however, .of
having to schedule one's experiments and schedule
the use of the computer facilities long in advance
is very unpalatable to most users. In general,
users prefer fewer facilities which are routinely·
available to larger facilities available by appointment .only. Hence, the desire fQ:r immediate computer access tends t.o favor multiple instrument
automation over laboratory autQmation.
Relative costs should also be considered. A computer system which is capable of expanding to
handle the requirements of an entire lab.oratory
will, .of necessity, be m.ore expensive, even in a
minimal cQnfiguration, than a computer system
capable of automating a single labQratQry instrument. Therefore, when one is taking the first step
toward laborat.ory automation, that is, the automation .of a single instrument, there is· a very
strong tendency to autQmate that instrument
using one small c.omputer since the initial cost
is cQnsiderably I.ower. Quite understandably, an
organization is reluctant to commit large capital
and manpower reSQurces to a project in which it
has little .or n.o experience. H.owever, if the ultimate gQal of completely aut.omating the laboratory is considered, many of the considerati.ons
discussed bel.ow imply that a single, shared labQratQry cQmputer W.ould prQvide m.ore perf.ormance per dQllar.
.
TQ realize all .of the potential .of automati.on,
.one must nQt .only acquire data but alsQ cQntr.oI
the instrument during the data acquisiti.on step,
1051
1052
Fall Joint Computer Conference, 1968
process the data which has been acquired,standardize it,. compare it against known parameters
(e.g., compare an unknown spectrum against a
file of spectra of known compounds for identification), and finally present the results in a form
which is usable to the experimenter. Data
acquisition and control steps can very often be
adequately performed by a small computer. However, the data reduction steps, the comparison
with data files, and the- presentation of results in
usable form often require much larger computer
capabilities. One solution to this is to record the
raw data, which has been acquired with a small
stand-alone computer,. on a recording medium such
as magnetic tape or pUJ?ched paper tape. This data
may then be processed on a large computer when
time is available. However, if the raw data is at
all voluminous, and magnetic tape must btr used.
the cost of the magnetic tape drive relative to the
cost of the small computer. can become very high.
Hence, this approach tends to encourage one to
minimize the quantity of data taken, often resulting in less precise results. Furthermore. the
turnaround time on very large computer facilities
still is much longer than the individual investigator would like to wait between epochs of his
experiment. That is, if he could have the data
from the last epoch back quickly, these results
could be used to determine conditions for his next
experiment.
A larger shared computer has several advantages for the automation of a laboratory. It can
have sufficient core and processing capabilities
to do a large portion of the data reduction required in most laboratories without resorting to
a large central computer. By dynamic allocation
of system facilities one may take advantage of the
fact that most analytical and spectrocopic instruments have low duty cycles (Le., much of the time
is spent in sample preparation or with the instrument oompletely idle). This dynamic allocation of system facilities will allow one to reduce
the total size of the required system below the
sum total of each experiment's requirements. In
addition, under such a system, background data
reduction tasks may be carried out by utilizing
excess capacity that exists at any moment.
Another advantage of a shared computer is
that more sophisticated input/output devices are
available to all users. The advantages of having
access to large disk files, line printer, card reader /
punch, and magnetic tape units are obvious. Only
the largest devoted computer /instrument com-
bination could justify the most modest of such
devices.
As a result of the above considerations, we have
designed and implemented a monitor system. Our
goal was to provide a system which could serve a
laboratory containing a group· of analytical and/
or spectrographic instruments operating in a dynamic mode, i.e., a. research or develop.ment environment. This. system, the Palo Alto Laboratory
System (P ALS), features complete program independence and complete system independence of
each instrument from all others. An application
program for one instrument, either at the time
it is written or executed, need in no way take into
consideration other programs running in the system simultaneously. Furthermore, .application programs need not be modified as a result of a change
in the total instrument configuration attached to
the computer system. Each instrument may have
its own individual data path to the core of the
computer via data channels, .so that there need
be no sharing of the interfaces between various
instruments. Data acquisition associated with the
various instruments is completely asynchronuos.
Closed-loop control capabilities are provided with
a response time of the order of 50 ms. The system dynamically allocates core, disk space, and
I/O devices to provide maximum usage of these
facilities.
This system uses an IBM 1800 computer. It is
possible to operate this system on a computer with
16K words of core; however, it is more useful if
the laboratory to be automated is sufficiently large
to support a 24K or 32K word machine.
A new device, a digital multiplexer, has been
designed and built, specifically to support this
laboratory automation system. This digital multiplexer channel provides up to 32 discrete data
paths between the laboratory and the core of the
computer. Via cycle stealing, it allows data to be
acquired from, or presented to, the individual instruments in a demand/response mode with a
minimum of computer overhead. The reduction in
computer overhead increases the allowable total
data acquisition rate from all instruments by
more than an order of magnitude. Data acquisition is in a demand/response mode which is of
great value in that it allows the instrument to
indicate when data is available rather than letting
the computer determine when data should be presented. An example of the usefulness of demand/
response data acquisition is in acquiring data
from an infrared spectrometer which has automatic scan suppression. Since the scan rate is a
Computer Systems for Automation of a Laboratory
function of the first derivative of the absorption,
data acquired at equal intervals of time would
not be at equal increments in wavelength or wave
number. However, with a demand/response interface, the instrument could be run with scan suppression, and demands to take data could be made,
by the instrument at equal wavelength or wave
number increments.
The monitor system
The PALS monitor system is made up of a
group of relocatable modules which are initially
stored on the disk. Modules serve either input/
output devices or are responsible for initiating
program loading, linking to the Job Control Language (JCL), controlling multi-task communications, and monitoring time slicing operations.
The only portion of the system which is not
. relocatable is a 200-word area in low core contains
information related to hardware wiring, such as
an interrupt transfer vector and the word count
and address registers for the various sub channels
of the multiplexer.
The various modules making up the system
communicate with each other by means of task
control blocks and task-complete control blocks.
When one module has a task to be performed by a
second module, a task oontrol block is generated
by the originating module. The address of that
block is passed to the second module which performs the task as soon as it is able. When the
task has been completed, the second module generates a task-complete control block which is returned to the originating module. The task-complete control block indicates whether the task has
been completed successfully or unsuccessfully, and
the reason for any unsuccessful completion if
appropriate.
Two monitor modules, a real-time module
(foreground) and a non-real-time module (middleground) are responsible for the execution of
all users' programs and for communication between users' programs and the rest of the system.
A second non-real-time module (background) is
not part of the system's modules, but is read from
disk upon request.
Input/output device modules service disk files,
all the subchannels of the digital multiplexer,
printer, card reader, the typewriter terminals, etc.
There may be several modules stored on the disk
servicing the same input/output device at various
levels of complexity. That is, one may be a very
sophisticated package, having many operations in-
1053
eluded in it, while another services the device at
a minimal level having only one or two very
simple operations implemented in it.
The system is configured by reading in a pack
of control cards which indicate which modules
should be loaded and link-edited together. The
reconfiguration of the system, depending on the
various users' needs, is very easy and requires
only a few seconds. At this time the operator may
choose, for example, whether he wishes to have
full printer support requiring over a thousand
words of core, or minimal printer support requiring only a couple of hundred words of oore.
,It is also possible to eliminate devices which are
not to be used. After this deck of cards is read
in, the system is cold-started with a one-card
cold-start routine which loads and link-edits the
appropriate system modules in low core.
Dynamic core allocation
All of core not taken up by the system is divided into pages of 512 words and all of these
Core Allocation
)
Relocatable
Modules
I
System
Making Up
System
t
)
A
B
A
System Subroutines
A
B
A
)
t
Variable Core
(512 Word Pages)
I
)
1---------------.... ---------------
Assembler or
Variable Core
FIGURE I-CorE" allocation map
pages are put into a pool of free pages (Figure
1) . The loader module is responsible for allocation
of the pages of variable core. When a task is
given to the loader to load and set a user's program into execution, the loader places that user's
program into any pages of core which are presently available. These pages need not be contig-
1054
Fall J.oint C.omputer C.onference, 1968
U.oUS, since the I.oader takes care .of altering the
rel.ocatable addresses within the user's pr.ogram
at I.oad time, S.o that it may execute out .of n.onc.ontigu.ous pages .of c.ore. In additi.on, the first and
last w.ords .on each page of a user's program and
all w.ords which are not modified during execution
.of that pr.ogram are st.orage-protected at load
time. This pr.ovides a high degree of pr.otection
of .one user's program from another.
Systems subroutines, such as floating addition,
multiplicati.on, division, sine, etc., are shared
am.ong individual user's programs. These subr.outines are st.ored .on the disk, in gr.oups which
are assembled into a block that will occupy one
page of variable core. At I.oad time, when the
I.oader encounters call to a systems subroutine
from a user's pr.ogram, the loader checks whether
the page on which that system subroutine exists
has previously been loaded into core. If it has, the
loader links the program being loaded to that
systems subr.outine. If the systems subroutine has
n.ot previously been loaded, the loader I.oads the
page which contains the called systems subroutine
from the disk and links it with the program being
loaded.
When a program has completed its execution
and has called EXIT, a task is given to the loader
t.o return all the pages associated with that user's
program t.o the pool of free variable core. The
loader clears all the st.orage protection hits from
these pages and interr.ogates to see if the terminating progr'am was the only program using
any of the systems subroutines. All systems subroutine pages which are not being used by other
programs are als.o returned to variable core. However, th.ose subr.outine pages which c.ontain subroutines being used by .other application programs
still in executi.on are n.ot affected.
a
Disk allocation
Many of the problems encountered in a laboratory require random access to individual data
or groups of data within large files, hence the file
structure on a peripheral disk is of considerable
importance. It is usually impossible to define the
ultimate size of a data file before it is generated
so that a dynamic file allocation is highly desirable. Disk files in the PAL system are organized
as logical tapes which are aut.omatically expanded or contracted according to the present length
of the data table written thereon. These logical
tapes are defined by name and allocated by' the
system one cylinder of the disk file (2560 words)
at a time. Such tiles may be used in much the
same way as a physical magnetic tape, that is,
one can read, write, backspace any number of
words, rewind, etc. In addition, the inherent advantage of the disk file is preserved, i.e., reading,
writing .or altering single words anywhere .on the
logical tape in the direct access m.ode is still possible. The system all.ows this by keeping an internal w.ord c.ounter which points t.o the I.ocati.on
where the last access was made. Alteration of
this pointer to any value is easily done by giving
an instruction t.o the system. If the data table
exceeds the length of the first cylinder, the system
automatically adds cylinders to the logical tape,
restricted only by the maximum value the word
count pointer may attain, 32767 words. The tape
may be closed at any value to retain the file for
future use. If the length of the tape upon closure
is less than a previous length, the excess cylinders
are returned to the system, providing automatic
contraction of the file. For example, if a previous
data file required six cylinders and the present
one .only requires three and a half cylinders, the
fifth and sixth cylinders will be returned to the
pool of empty cylinders for reallocation by the
system.
Multitasking
Allocation of the CPU is implemented using the
multilevel interrupt structure of the 1800. Therefore, if a task is being processed and a task of
higher priority is initiated, the low priority task
is suspended and the higher priority task is processed immediately.
The entire PALS system is oriented toward
performing a variety of tasks, many being associated with input/output. In general, it takes 12
words' of a user's program to specify a task for
the system. These tasks are accepted by the system and performed as soon as possible. Multiple
tasks may be queued for a single input/.output device; e.g., the line printer may have a current
task in execution while five other tasks are
waiting for the line printer to be free. A given
application program may have several tasks
outstanding simultaneously. For instance, a given
application program may instruct the system to
(1) acquire a block of data from a given instru- \
ment, (2) read a card in the card reader, (3)
print a line on the line printer, (4) light a light
at the user interface, and (5) write a block of
data on a logical tape. These tasks would be given
to the system sequentially; but all five tasks would
be set into execution before the first one was
completed.
Computer Systems for Automation of a Laboratory
CYCLE STEALING
Active
Queued
1.055
Passive
A -4,.;..------- B
MACHINE CHECK
ANSWER INTERRUPTS
START INPUT/OUTPUT
FIGURE 3-Flow diagram of monitor algorithm
REAL TIME USERS MONITOR
Below that, hardware interrupts are answered and I/O devices are started. Each of
the system modules which is responsible for
an I/O device may queue, to an indefinite
length, tasks to be performed in conj unction
with its particular I/O device. When a hardware interrupt occurs, indicating the completion of a task or a subtask, the next task
or subtask is initiated as a portion o~ the
interrupt handling routine. In addition,
when a task has been completed as a portion
of the interrupt handling routine, a taskcomplete contr.ol block is returned to the
system module which originally issued the
task.
Next is the real-time user's monitor under
which all real-time programs are executed.
A user's program in execution under the
auspices of the real-time user's monitor may
be in one of three states: passive, queued, or
active (Figure 3). When a p;rogram originally goes into execution it is placed at the
bottom of the queue. As programs are taken
from the top of the queue and placed in
execution, the program at the bottom of the
queue works its way up through the queue.
Finally, the program. is taken from the top
of the queue into active status and the user's
monitor transfers control to the user's program. The. user's program maintains control for doing processing.
After giving out a number of tasks and
having done a certain amount of processing,
one of two things can happen which will take
a user out of the active status. The first
possibility is that he has completed all processing and has given out all the tasks he
desires at that time and can do nothing
more until one of his I/O tasks. has been
completed. At this point the user executes a
relinquish operation which then cause~ the
user's monitor to remove him fro~ the
active status and place him in the passive
status. Control then passes to the next
LOADER
NON-REAL TIME USERS MONITOR
HOUSEKEEPING
JOB CONTROL LANGUAGE
ASSEMBLER
WAIT LOOP
FIGURE 2-Priority list' for CPU cycle allocation
If the user's program wishes to initiate an I/O
operation, it does so by giving specifications of the
task to the user's monitor, which In turn generates a task control block and gives it to the
system module responsible for executing that task.
As soon as the task has been started or queued,
and before the task is completed, control is returned to the user's program. From this point the
user's program may send out additional tasks to
the system, each time control being returned to
the user's program. Two of the arguments in a
specified task are entry points to the user's program. One is associated with a normal return
addres~, and one is associated with an abnormal
return address. If the task is completed successfully, the user will regain control at his normal
return address, whereas if the task is completed
unsuccessfully, control will be returned to the
abnormal return address.
A priority list for allocation of CPU cycles
is given in Figure 2.
The highest priority is cycle stealing for the
transfer of data between' the various I/O
devices, including the instrument interfaces
and memory.
The next highest priority is for servicing
machine check conditions.
· '1056
Fall J.oint Computer C.onference, 1968
pr.ogram in the active queue. The user in the
passive status does not relinquish core, only
his P.osition in the active queue.
The other possibility is that of a "time-out."
Each time a user's program is put into
execution, the user's monitor sets an interval
timer for a n.ominal five millisec.onds, and at
the expiration of this time the user's m.onitor takes control away from the user's pr.ogram, saves all status and registers, and
puts the program from the active status to
the bottom of the queue (time slicing). The
user then must work his way up through
the queue t.o the top again to resume processing. Using five millisec.ond time slices,
it has been our observation that a real-time
user usually relinquishes before he is timed
.out.
When a user is put into the passive status,
the .only way he can return to active queue
is as a result of a task-complete control
block being returned to the user's monitQr,
indicating that .one the user's I/O operatiQns
has been completed, either successfully or
unsuccessfully. At this point the user's monitQr takes the user's prQgram out .of the
passive status and places it at the bQttQm
of the active queue. A guaranteed response
time, i.e., the time from cQmpletion of an
I/O .operation until the time that a user's
prQgram may act upon that cQmpletiQn, may
be implemented by limiting the number .of
users allQwable in the real-time executiQn
and by implementing five millisecond time
slices. If, fQr instance, the real-time user's
monitQr limits the number .of users to five,
, a worst case conditiQn WQuld be four users
in the queue. When an I/O operatiQn has
been cQmpleted or a hardware interrupt
.occurs, the maximum length of time necessary tQ answer WQuld be five milliseconds
fQr each .of the peQple in the active queue,
plus nQt mQre than 20 millisecQnds overhead
assQciated with the higher priority operatiQns (if .overhead were 100 percent). This
would mean a total .of 40millisecQnds maximum frQm the time that the interrupt
cQnditiQn .occurred until the time that the
user's program gained cQntrol .of the CPU
fQr a five millisecond time slice. N Qte that
interrupt servicing and queue manipulating
dQ nQt interfere with .on-line data acquisitiQn which proceeds via CPU cycle-stealing.
Immediately below the real-time us·er's monitor in priority is the module' contrQlling
loading of programs and dynamic allocation
of core. It was given a IQwer priority than
the real-time monitor in order to avoid interference with operational real-time programs. Because the loader module can ac~
cept tasks from other modules, operations
such as having a real-time program load a
non-real-time prQgram and vice versa are
possible. A typical example of load time is
1.7 secQnds for a seven page program,
during which time all of the operatiQns previously discussed under core allocation are
performed. This .overhead occurs just once
at the time each program is initially loaded,
and it is negligible compared to the manual
set-up times needed to ready an instrument
or experiment.
Next is the non-real-time user's monit.or.
Programs executing in a non-real-time
status are executed under the control of this
mQnitQr which has the same algorithm for
scheduling time t.o the various user's programs as does the' real-time monitor, except
the time .out peri.od in the non-real-time
monitor is a nominal one hundred millisec'Onds.
Below the non-real-time monitor in priGrity
are various housekeeping modules. These
modules are in general responsible for code
conversiQn and spooling operatiQns between
variQus I/O devices. For instance, a user's
program may give a task to the system to
print an entire logical tape~ This task WQuld
be executed by a h.ousekeeping module,
which in turn WQuld give out subtasks to
read sectors of the logical tape and tQ print
the individual lines. This module would also
be responsible for the code conversi.on from
EBCDIC to printer cQde .
Below the housekeeping modules in priQrity
is the module which deals with job control
language. This module offers a fairly high
level .of conversational interaction between
the operatQr .of the system and the system.
FrQm the console typewriter the operatQr
may load a program or set a program into
execution, may cancel a program, may get
a dynamic dump of a program while it is in
execution, or a dynamic dump of any area
core, may get a dump of a logical tape, may
define or scratch a l'Ogical tape, or may get
a status of the entire system.
Computer Systems for Automation of a Laboratory
The lowest pri.orities are devoted to the
language assembler, and a wait loop.
The PALS
languag~
Language requirements for a laboratory automation system include the ability to easily program multiple on-line data acquisition and control tasks as well as off-line data reduction or
analysis tasks. Data acquisition and control tasks
demand programming of a number of input/output interactions with sensor-based devices. Logical operations are required for the various control
functions. Past experience indicates that data reduction and analysis tasks are best served by the
FORTRAN or PL/I type of language.
1057
The approach chosen for the PALS system was
a macr.o language with statements natural to the
laboratory environment. There are statements for
easy handling of sensor-based input/output (e.g.,
mUltiplexer channel commands, analog inputs, and
a series of special logical statements used to set
up bit patterns for control of instrument interfaces, etc.). FORTRAN-like statements are available for data analysis, and they. require very
little re-Iearning for users familiar with
FORTRAN.
Some examples of the various types .of PALS
statements may serve to indicate the salient features of the language.
I/O OPERATIONS
SUBCHANNEL OPERATE
SCOP
SCl, 3, DTNAMl, NRET, ARET
READ LOGICAL TAPE
DRTP
WC, NAME, BUF
W rite the c.ontents of table DTN AMl out .over
subchannel 1 in demand/resp.onse mode (operation code 3). After successful completion of the
operation, return contr.ol to n.ormal entry point
NRET, if not successful to abn.ormal entry point
ARET.
Read the number .of words c.ontained in location
WC from logical tape NAME and place them in
core starting at locati.on BUF.
READ CARD INTO CARD BUFFER
CRDR
CONVERSION
CARD BUFFER TO INTEGER VECTOR
CBIV
N,M,VEC,AI
INTEGER TO EXTENDED PRECISION
FLOATING POINT
FLOT
INTEGER TO EBCDIC·
IEBC
I, E
I,CH, EBCDIC
The contents of address N is the number of card
columns to be used f.or each element; location M
contains the number of elements per card; VEC
is the starting address of the vector; and location AI contains the subscript .of the first vect.or
element t.o be filled by the present card buffer.
Convert the integer at location I to extended precision floating point number at location E.
C.onvert the integer at location I to CH number
of characters starting at location EBCDIC.
'1058
Fall Joint Computer Conference, 1968
,MATHEMATICS
STANDARD FLOATING ADD
FADD
A,B,C,ERR
MULTIPLY VECTOR ELEMENTS
IMPX
A, I, B, J, C, K, ERR
SQUARE ROOT FUNCTION
FSQT
A, B, ERR
The macro language permits programmers to
mix assembler language with macro statements.
It is at the user's discretion to define new statements to meet the needs and level of programming
experience of the scientists writing applications.
The PALS macro processor is treated somewhat as if it were an application program, except
that it is executed in background mode. It is not
paged but is loaded into a partition at the high
end of variable core. When the loader is asked
to load the assembler, the request is queued until
the 12 pages at the high end of core are all free. At
that point,' the limits of variable core are lowered
about 6000 words from the top end .of core and
the assembler is loaded into this partition. When
the assembler has completed its operation, its
core block is returned to variable core. This
means that several minutes may be required from
the time it is requested to load the assembler
until the assembler is actually loaded. However,
since this system is built on the basis that assembly should be a background operation" this
allocation scheme appears to be satisfactory.
Application programs
A joint study was carried out with Varian Associates in order to investigate and demonstrate
the usefulness of a time-shared, laboratory automation computer system. A simulated research
Add the standard precision fl'Oating point numbers
I'Ocated at A and B and put the result in location C.
ERR is the entry point 'Of a user error correction
r'Outine.
Perform a floating point mUltiply of the Ith element of vector located at A by the Jth element of
vector located at B and place result in the location of the Kth element of vector located at C.
Branch to ERR if any error.
Take the square root in floating point 'Of the number at A and place the result in location B.
Branch to ERR if any error.
lab'Oratory, containing an M-66 medium resolution
mass spectrometer, an A-60 NMR spectr.ometer,
two Aerograph gas chromatography columns, and
a Statos recorder, was linked to an on-line IBM
1800 computer (Figure 4). Each of the instruments was interfaced with the computer via
prototype Varian interfaces, an example of which
is diagrammed in Figure 5.
Each instrument interface provided facilities
which allowed the spectroscopist to have complete
control over his use of the computer from his
remote spectrometer. These facilities consisted of
backlighted push buttons, lights, and thumb
switches. Prompting lights, operated under program control, served to indicate the present status
of the operating program. Functions executable
from the remote console included loading and
aborting application programs, controlling branch
points within the application pr.ograms, and entering parameters during the execution of programs. In general, the recorder ass9Ciated with
a particular instrument was used as the graphical
output device; the Varian Statos recorder being
used fur the two chromatographs. Tabular reports were printed on the shared-line printer.
A disk resident master program was associated with each instrument. When an experiment
was to be perf'Ormed, the master program was
loaded into the core memory by depressing a
Computer Sy-stems for Automation of a Laboratory
1059
pushbutton on the interface. The function of the
master program was to initialize the spectrometer
and to provide a choice of the available application programs to the user. After the master program was loaded, it armed appropriate pushbuttons for program selection. This was indicated
by. lights behind the several pushbuttons. When
Programs
1
2
3
4
I I I I D
DEntllrlnteger
o
Select
EntllrFrlCtion
o
000 000 000
Error
256 128 64
Program
Stop
D
FIGURE 4-An automated analytical laboratory
o
Manuel Entry
32 16 8
Scan Count
4
2
1
D
FIGURE 5-Typical control panel of instrument interface
DATA MANIPULATION
TRANSFER VECTOR ELEMENT
A, J, B, K
TVEI
INCREMENT VARIABLE
Transfer integer element Ai into integer· element Eko
Increment integer at I by the integer J, where
INC
I, J
- 128 =::;
J=::; 121.
FIND MAXIMUM ELEMENT OF INTEGER
VECTOR
IMAX N, YDATA, I, YMAX, IMAX
Search N elements of the vector starting with the
Ith element of vector YDATA and place the maximum values of YDATA and its index I into locations YMAX and IMAX respectively.
PROGRAM SWITCHING
IF
IF
I, J, A, B, C
Branch to A if integer quantity (I-J) < 0, to B
if == 0, and to C if > 0.
A, B, C, D, POINT
Branch to A, B, C, D if location POINT contains
0, 1, 2, 3 respectively.
LOC, N, I, K
Execute all statements starting at location LOC
through the REPT statement th~ number of times
contained in N. Each time through the loop, increment integer at I by the number K.
COMPUTED GO TO
GOTO
REPEAT LOOP
REPT
; 1060
Fall Joint Computer Conference, 1968
one. of these programs was selected, it. was loaded
and the maSter program would exit (release its
core). After the subprogram completed its function, and before it exited, it requested that the
master program be reloaded. This mode of operation minimized the core requirements of a single
user.
Several application subprograms, which performed some of the more elementary instrument
functions, were jointly specified and written by
Varian and IBM. With the A-60 NMR it was possible to: aCquire data in a demand/response-mode
by sweeping the magnetic field; time average the
data by repeating the scans any desired number
of times; digitally smooth the acquired data; and
control the magnetic field homogeneity. The mass
spectrometer programs acquired data in a demand/response mode; replotted any desired portion of the data on the instrument recorder; found
all peaks' in the spectrum and normalized their
intensities; and found the five highest peaks and
identified the compound by comparison with a
table of spectra of known compounds on the disk
file. The gas chromatography programs acquired
data, detected and resolved peaks, calculated their
areas and wrote a report giving retention times
with peak areas.
Actual experience with· the above system was
quite good. Programs were easily and quickly
written using the macro language. No noticeable
interference between users occurred, even when
alI instruments and data processing I/O devices
were running simultaneously.
In conclusion, we believe that we have been
able to produce a system for use -in laboratory
automation which provides each individual user
the isolation, the availability, the real-time control responsiveness, and the price per instrum~nt
associated with multiple computers, one per instrument. In addition, this system provides powerful input/output devices, disk files, and a large
amount of support :for the I/O devices and the
files, which is not normally found on a small dedicated computer. Each user, then, has the impression that he has a large computer attached to his
instrument and completely at his disposal. The
1800 PALS program, excluding the instrument
application programs, is available from the IBM
Type III library (PIn #5778) ~
INSTRl]MENTATION CONTROL
READ DATA AND WRITE LOGICAL TAPE
RDLT
SCPNT, WCPNT, LTPNT, NPRA, APRA
ALTER SUBCHANNEL BIT
ASCB
BC, BIT, N
CONVERT THUMB SWITCH TO FLOATING
POINT NUMBER
CTTF
F
ASSIGN PROCESS INTERRUPTS
ASPI
PINO, ENT
From subchannel number contained in SCPNT,
read the number of words contained in WCPNT
(1 ~ we ~ 32767), and store on a logical tape
whose name resides in LTPNT. Return control
to normal entry point NPRA for successful completion of the read, and to APRA for abnormal
conditions.
Alter one bit (number of bit contained in location
BIT) of a subchannel register (number of subchannel contained in location SC) to a new value
N == 0 or N = 1.
Read a set of manual switches on instrument
interface and convert the setting to a floating
point number at location F.
Assign a program entry point ENT to the process
interrupt whose number is contained in location
PINO.
Real time time sharing, the desirability and economics
by B. E. F. MACE FIELD
University of Oxford
Oxford, England
INTRODUCTIOK
The thoughts expressed in the following contribution
have arisen largely as a result of work at the University
of Oxford, Nuclear Physics Laboratory. In Oxford, we
have had a demand for two real time users and one
background user. The achievement of this goal is described in the first reference. 1 It has been clear, however,
that many institutions have a similar problem and it
was the fact that the solution was not impossibly difficult that prompted this plea for more efficient use of
large capital investments represented by on-line computers.
I think most of us would agree that the battle of the
stored programme computer versus the fixed wired
kicksorter is over in the field of nuclear data collection.
The victory has certainly gone to the stored programnle
device. But once the euphoria had died down many people, the author included, have found that a certain
amount of fast front end hardware has been necessary
to supplement the activities of the central processor.2
This requirement will probably be Jess prominent in the
future with the current increase in nUllJ.ber of sub-one
micro second cycle time computers. I might point out
that front end hardware is usually used to lnake decisions on the admissibility of the incoming data faster
than the computer.
The proposition
It is the utilization of the computer used in such a
data col1ection system that I wish to exanline. The increasing speed of even the smallest computers has given
rise to some interesting consequences. In very general
terms the speed of processing the incoming data in a
real time environmenl. is inversely proportional to the
memory cycle time. The add one to memory or for very
sophisticated data the programme manipulation time
are both very obviously dependent on cycle time. As a
result we can get to a stage where the C.P.U. is infre1061
quently used because the data is serviced in a time considerably shorter than the time between events. Let us
examine this further. Assume we have a 1 ,usec cycle
time machine.
The add one facility fronl an external source should
not take longer than 2 ,usec giving a mean rate of 500,000
events/sec. Now there are a few detectors and no analogue to digital converters that will perform at this rate.
The best. the latter can do is probably 50,000 events/sec
at the present time. Thus for a physically realisable configuration we can see 10% utilization in the simple case.
For the complex data system we may require programmes which take say a millisecond to sort an event.
Now complicated events usually occur at very slow
rates, typically l00-200/sec, so our multiparameter
data analysis takes at most 20% of the time. Even
allowing for a factor of 2 upwards in these estimates we
see a sizeable fraction of the total processor time is
unused.
But, you will be asking, what about the display and
other user requirements. These user requests, often for
data manipulation, are very infrequent on a computer
time scale and in consequence need not affect the overall
argument even though they may take a substantial
time to complete. The display, however, is another
matter.
Most people working in real time with computers require some form of immediate access to the data. The
most usual form for this to take is a visual display. I
would distinguish, very obviously, two types. The
C.P.U. controlled variety and the directaccesstomemory type. The former obviously ties up the C.P.U. continuously for display and in my opinion is so bad an investment (regardless of its price) as to be completely
disregarded from the current discussion. The latter
comes in forms ranging from simple analogue scopes to
sophisticated vector and character generators. The
major problem about C.P.U. controlled scopes is that
once installed, economic arguments win be advanced
1062
Fall Joint Computer Conference, 1968
forcing them to be used and in consequence be a large
Jnhibiting factor on the application of the computer.
(This conunent may be toned down somewhat by the
advent of large diameter storage tubes and the fact that
it is a comparatively trivial modification to convert such
a device to a direct access system). But, given we have a
scope that will display a frame without C.P.U. interyention, save for start up, then it is unlikely that the
total increase in used time would be another 5% giving
at most "40-45% total time used.
Having dealt in general terms let me give an example
from our work in Oxford. We have several A.D.C.'s in
use, each connected t~ front end hardware. 2 Figure 1
shows the time left over when they are in operation at
the event rates indicated. Two sets of curves are shown,
a software (API) storage system and hardware storage
(DES) . We see for the software case less than 10%
time left over if 6 A.D.C.'s are working at rates of 2000/
sec each. This, however, is not a physically sensible rate
for such a system since Figure 2 shows that at this rate
A.D.C.'s 1 and 6 have vastly different storage efficiencies
as seen by the outside world, making usage very difficult. The solution is thus either to reduce the input
rate to get the efficiences more nearly equal, say to
lOOO/sec, when the time left free is a usuable 30% or
build front end hardware and get similar efficiences and
30% free time at 20,OOO/sec. The derivation of these
curves and explanation of the different shapes of the
DES and API efficiency curves is set out in reference.3
If either of the above approaches were adopted we obtain some free C.P.U. time and we must therefore ask
why is this time not used?
Nevertheless the question needs some justification
even though once put it seems obvious enough.
Figure I-Free C.P.V. time for various input rates on
each A.D.C
Figure 2-Efficiency of each A.D.C. for various input rates
Modus operandi
When buying a computer the expenditure must be
justified to some funding body, as in the purchase of an
accelerator facility. In the latter case, however, one of
the earliest questions is what is the percentage utilization? If we asked for an accelerat<;>r to be used only 50%
of the time, it would be completely unacceptable to the
financial experts and physicists alike. So why do we not
get such questions from the computer users who have
most to gain from efficient machine use?
Anothrr point that arises is that a given institution be
it a small laboratory or a government enterprise, buys
the computer it can afford and this, I propose, results in
the computing expenditure being a constant fraction of
the total expenditure on the project. In other words all
user~ have the same percentage to gain be they large or
small. So on this premise we should be hearing a clamour
for time sharing even the smallest machines, but we do
not. Why not? Because we have to some extent been
brain washed into thinking that only with the largest
installations is this at all possible.
Where do we start in attempting to achieve this
utopia of 100% computer utilization? We start by delimiting exactly our goals. We are not aksing for 10-20
users ~ut in terms of 1-3 or maybe 4. In Oxford, we
have already 3 simultaneous users on a 24k PDP-7; why
would others not do the same? The one single problem
with most on-line nuclear structure computer systems is
the inabiIi~y to get at the computer after taking the experimental data. Obviously, therefore, the extension of
the users from 1 to 2 produces an infinite improvement.
To attain this end we have to split the machine in
some way, either by swapping programmes in core or
memory allocation. In Oxford we have a mixture of
these approaches;1 memory allocation to separate back-
Real Time Sharing
ground from foreground and swapping for the two online users. At this stage we ran into the first problem.
The system software as then supplied for our machine
was not designed for multiple users and moreover was
not organized on a modular concept using bulk storage
peripherals. (I would point out that in the latter case
this has since been changed with the PDP-9).
In a small system it is not essential to get two background users but the background system must function
in the presence of unusual device flag combinations.
This implies a flag mask to allow only specified flags to
cause interrupts and an efficient automatic priority interrupt system (API). This should be an interrupt chain
with successive channels having non-consecutive memory locations. In this way the low priority channels can
be assigned to the background system and the higher
channels to the foreground system in a completely different and possible protected memory area. (To my
knowledge no company has such an API system.)
The concept of memory protection necessarily entails
some mode of trapping the incorrect memory references;
obviously to be a location different from the API channels and programme interrupt. Since ~e are in a small
system we will need to share peripherals, on the grounds
of expense, and thus 10 instructions need to be trapped
also. Along with 10 trapping we will need a supervisor
programme to oversee this concurrent peripheral use.
This programme need not be extensive, we have an
800 10 word programme to share Dectape, punch and
plotter.
We have now got round to the question of 10. In a
real time environment it is evident that all synchronous
devices must have a higher priority than random data
from a nuclear experiment. By synchronous I include
magnetic tapes of all types together with discs but not
most paper tape readers which stop between characters.
To guarantee this priority sequence we must have all
such syllchronous 10 by data channe1.
Necessity hardware canfiguratian
Perhaps it might now be possible to see what we are
asking of the computer manufacturers:
(i) A versatile API system
(ii) An effective 10 trap system
(iii) Synchronous 10 by data channel
(iv) Flag mask.
Hopeful1y some may conclude that many machines
1063
seem to have most of these facilities already. I think this
is true, so why are there not more foreground-background systems in existence, for given the above four
requirements, time·sharing in that context is straightforward.
There seem to be three possible reasons for the present state of the art:
(i) the expense of memory for a memory al1ocation
system
(ii) the cost of fast swapping discs
and (iii) we are persuaded that we need to buy a bigger
machine to achieve these resu1ts.
The costs of the first two items are continuously falling and from this point of view we :may expect an increasing number of multi-user applications. In the third,
we, as computer users, must be more critical of what is
provided by the manufacturers and not succumb to their
advertising.
Ecanomics
Of the three major hardware requirements the ones
most llkely to be missing are the s1it API system, 10
Trap and flag :mask. Given that the machine runs asynchronously the cost of putting these into an existing machine is UP likely to exceed $2400. The duplication of the
smal1est system is unlikely to be less than $15,000. The
latter cost obvious1y depends on the system while the
former is a1most independent of the system context.
CONCLUSION
In conclusion then, it is evident that to achieve more
than 50% real time utilization in nuclear structure work
we require more than one real time user. It is also evident that this can be done with a mipimum of effort
given the right hardware configuration, which i~ not so
very different from that existing on most small to
medium processors. It is thus much more economic to
satisfy a demand by a small extension to an existing
machine than to duplicate the system.
REFERENCES
1 G L MURRAY B E F MACEFIELD
N uel Inst & Meth 51 1967 229
2 G L MURRAY B E F MACEFIELD
Nuel Inst & Meth 57 1967 37
3 G L MURRAY B E F MACEFIELD
Nucl Inst & Meth 62 1968 122
A modular analog digital input output system
(ADIOS) for on-line computers
by R. W. KERR, H. P. LIE, G. L. MILLER,
and D. A. H. ROBINSON
Bell Telephone Laboratories, Incorporated
Murray Hill, New Jersey
INT'RODUCT'ION
The most important single feature that allows a
computer to be employed in a broad range of calculations is the fact that one' can, by programming, in effect restructure the machine to perform the desired computational task.
I t is not possible to retain the same degree of
flexibility in on-line systems because of their
need to be connected to specialized external hardware. Primarily for this reason the majority of
on-line computer systems that have been constructed in the past have been designed to perform a pre-defined class of specialized operations.
This situation is analogous to that which existed
before the invention of the stored program machine when a computing device would be constructed to perform each new special task.
The system described here is the result of
an 'effort to obtain a reasonable degree of flexibility
in on-line computer controlled environments and
is based on careful considerations of the factors
that tend to limit such flexibility. The consequences of such problems in previous systems has
been evidenced by difficulties of adding or reconfiguring hardware and interface equipment. Such
difficulties have reduced the potential versatility
of many existing systems in which the· effort
required to implement useful changes is uneconomic and such changes are therefore only rarely
made.
It is possible, however, by the use of appropriately designed modular units interconnected
by a common two-way analog and digital databus to obtain the desired degree of flexibility and
power. The next section of this paper outlines
the general consideration involved in the desii11
of such data-bus systems, while the remainder of
the paper describes the implementation of these
ideas for a specific small computer, namely a
Digital Equipment Corporation PDP-So
. Design considerati0n8
Of the many schemes whereby equipment may
be connected to a computer perhaps the simplest
division is between "radial" and "bus" systems.
In the former, the inte'rconnecting cables can be
thought of as radiating like the spokes of a wheel
to connect the computer to each external unit,
while in the latte'r each external unit is connected to a common "highway," "party line," or
"bus" cable system. In a certain sense this distinction is artificial since in the last resort even
a radial connection is handled on a bus basis
once the signals enter the computer hardware
proper. However, the distinction is a valid one
for the domain of equipment external to the
computer itself and can serve as a starting point
for comparing different systems.
The greatest single advantage in a radial system, from the use'r's point of view, is the fact
that exte'rnal equipment need only be plugged
into a suitable connector to be on-line with the .
computer. The outstanding disadvantage, however, is that such systems are relatively inflexible
and can become expensive if large numbers of
external units are required. Furthermore, the user
may become overly dependent on the computer
vendor and his instrument division since only
their equipment i~ automatically interfaced with
the machine. In bus systems, on the other hand,
the organization is different in that each external
unit is connected to a common set of cables which
1065
1066
Fall Joint Computer Conference, 1968
o
COMMON ADDRESS
AND DATA LINES
SEPARATE ADDRESS
AND DATA LINES
FIGURE I-Logic tree indicating the major decisions involved
in the design of a data bus system
carry address, data, and status information to
and from the computer.
A feature of such bus systems that is worth
noting is that the interfacing operation between
theoomputer and the external world occurs only
once, namely between the computer and the data
bus. It is theref'Ore possible to design such systems so that the sa~e, or different, collections of
on-line equipment can be connected to many different computers by changing only the bus-tocomputer interface.
The differentiation into radial and bus systems is
indicated by the node labeled 1 in Figure 1. Other
important decisi'Ons follow at other nodes in this
diagram and it is the purpose of this section of
the paper briefly to indicate the major consid.erations involved at each branch. In order to forestall
any misunderstanding it may be well to point out
that th'Ough a particular design path was foll'Owed
in the PDP-8 sysltem described in the remainder
of this paper, it is by no means claimed that the
resulting system is ideal for every application.
As will become clear the design of any system
is dependent 'On numbers 'Of factors,' major ones
being, for example, the total size 'Of the system
envisa.ged (i.e., number of input and output units
together withinf'Ormation on their spatial separation), and whether the system is to be employed
by a single user or time shared by several noninteracting users simultaneously. An'Other important consideration is of course input/output speed
and data-rate. Interestingly enough, h'Owever, in
a number of actual on-line experimental environments that we have c'Onsidered, it turns out that
the bus approach imposes only a small time burden on the system. In the last resort this arises
from two causes, first because operati'Ons proceed sequentially inside the computer, requiring a
certain time to service each external unit, and
second because external units are themselves 'Often
qui~ slow (e.g., ~50 P.s conversion time for a
typical 12 bit nuclear physics ADC). The result
of this is that if reas'Onable care is exercised in
the design 'Of the bus system the access and I/O
time f'Or external units· can become quite small
compared with the sum 'Of the device 'Operation
and computer servicing time. Obviously it is
always possible to envisage situations where this
is not the case, but we believe them to be only a
small subset of most 'On-line situations. In those
cases where I/O speed bec'Omesan unavoidable
limitation, e.g., CRT displays, it is usually worthwhile t'O consider the use 'Of a separate dedicated
piece of equipment (such as a disc with suitable
DAC's, etc., for display) to perform the critical
function at all times.
Returning to the general considerations indicated
in Figure 1, the next question is one of .system
size. It is taken for granted that the user's hardware will consist of some form of modules which
plug into bins (see for instance the European
standard IANUS system or the ADIOS system
. described here) , and the question is whether there
will be one bin or several. This decision involves
questions of how multiple bins are to be addressed,
and what will be their physical separation and
distance from the computer. This latter point is
highly important though easily overlooked. Its importance can be seen in the following way. If the
cable length is l'Ong then the cables must be terminated to avoid reflection. The logic levels employed for modern microcircuits are typically 0
and +4 volts. F'Or 50 ohm terminated c·able this
means 80 rna/hit. Since on-line systems usually
employ common grounds between analog and digital hardware it folIows that the transfer of a 16
bit word can involve a current pulse at over 1.2
ADIOS
amperes in the ground return. The noise and
crosstalk implications of this are obvious. (A
new data bus system presently being designed at
Bell Telephone Laboratories for a multi-user environment using SDS Sigma computers circumvents this problem by using balanced currentdriven twisted pair. No such extreme steps were
necessary for the relatively small PDP-8 system
described in this paper.)
If multiple simultaneous users are envisaged it
is advantageous to employ a buffer unit between
each bin and the data bus. This has a number o.f
advantages fo.r large systems, not least being the
ability to pro,vide logical buffering between bins
to prevent one user from wiping out another by,
for instance, unplugging a module. This decision
is shown at node 3 in Figure 1.
Again in large multi-bin environments it can
be advantageous to provide a bin address with
unit sub-addresses within each bin, (this is the
route followed in both the European IANUS and
BTL Sigma system' designs).
At node 5 a difficult choice must be made regarding the extent to which the bus cables are
shared by time, or other multiplexing arrangements. The advantage of multiplexing lies in its
ability to reduce the numbe:r of cables in the system. The disadvantages are reduced I/O speed
and added complications to unit hardware and
system programming.
. The way in which external units signal the
computer via the interrupt system is also one ef
central importance. In this connection the major
choices lie, as indicated at node 6, between using
a single common interrupt line, or of employing
a hierarchical or priority system. The latter can
be organized two ways, either by using a sepa.rate physical interrupt wire from each external
unit to the computer, or by connecting the external unit interrupts in head-to-tail fashion whereby priority is defined by position in the chain.
Neither of the latter system is well suited to a
flexible data bus system designed to accommodate
a wide variety and number of external units
since each time a chang.e is made in the configuration of modules, numbers of separate physical
wires must also be re-routed.
It will be appreciated that the foregoing di~
cussion of general. questions is of necessity superficial, though we believe it to indicate most of the
major hardware considerations involved. Without
going too deeply into details of software and logical design one other question regarding module
1067
addressing must be raised. This is the issue of
what we term "generic" addressing and its importance can be seen with a simple example.
Suppose the on-line system involves a number of
external devices which must be turned on and
off in exact time synchronism. Since any bus system is by definition sequential, in that only one
set of address lines is used, it is not at first clear
how this can be achieved. A solution to the problem can be provided by allowing units to recognize mOore than one address. E.ach unit or module
recognizes its own unique address and having
been so addressed one of the commands to which
it can then respond is to enable recognition of another address. Such other addresses are termed
generic addresses and they can be common to
many different units. In this way the computer
can issue generic commands which apply simultaneously to any subset of extern.al modules, allowing them to operate in exact time synchronism.
By way of concluding this section on general
design considerations it may be illuminating to
consider a number of questions that can be asked
regarding the logical organization of any o.nline computer syste'm. Do'es it, for example, require special timing, logic and drive circuits to
be added to an external unit before it can talk to
the computer? If the ans·wer is yes then the
chances are that considerably less experimental
innovation will be carried· out with the on-line
hardware than would otherwise be the case.
Another important point to bear in mind is the
ability of the system to check itself. Can the computer tell what' units are connected and whether
they are operating? This feature can be very important in systems employing many modules.
An area that is outside the scope of this account
is that of programming, but it is obvious that
the hardware and software of anyon-line system
must be harmoniously designed. Less frequently
considered from the outset, however, is the question of the ease of debugging the operation of
the entire on-line system. Our experience with
the present system has shown the extreme desirability of being able to "force" external equipment
to well defined conditio.ns, by hand, as a check in
debugging programs and hardware. This also is,
therefore, a point to consider in comparing system configurations, how difficult is it to debug the
hardware-software interaction in preparing programs for the on-line system? .
A corollary to this point is the related one of
investigating the degree to which the computer
1068
Fall Joint Computer Conference, 1968
is able to exercise external equipment. In this
connectiQn it has been found extremely useful
to prepare programs which operate all the computer-accessible features of a mQdule sequentially.
This approach allows convenient debugging of
modules as they are produced since an Qperator
c'an examine repetitive waveforms ,at his leisure,
proceeding sequentially through a series of test
conditions under programmatic contrQl.
A final point invQlves the prQvision of an analog
measurement capability within the data bus system. This has been fouhd to ~; most useful in
. the PDP--8 system described, here, and comprises
a shielded twisted pair in the data bus cable
connected to a central 12 bit ADC at the CQmputer. In conjunction with suitable external
modules this furnishes the ability to. both measure and prQvide analQg levels. TQ'gether with the
digital capabilities of the system this provides a
combined digital and analog capability which encompasses a broad range of appNcatiQns.
The data bus
A diagram of the data bus system chosen for a
PDP-8 and a single-user envirQnment is shQwn in
I
ANALOG BUS
X
X
INSTRUCTION
LINES
IOPI
I
IOP2
J
~
i
<]- r+f-+BLOCK OF
r+3 LINE
DRIVERS
..
- ;+BLOCK OF
12 LINE
BUFFERS
I
I
1/0
SKIP
PROGRAM
INTERRUPT
1/0 SKIP
BUFFER
--'"
....
L-..J
T
FIGURE 2-Simplified block diagram showing the computer
interface and data bus cable
Figure 2. The IQgic Qf the Qperation Qf the data
bus closely parallels that Qf the PDP-8 cQmputer.
Commands are sent to a particular module by
placing the mQdule address on the address lines
and activating the instruction lines. The-three instructiQn pulses in this system Qccur at 1 P.s intervals and are .4 P.s in width. Because one Qf the
system rules is that the modules operate with
instruction pulses Qf any length greater than
~.2 p's, there is no. restrictiQn Qn the maximum
length of the cycle. (Thus the system may also
be us·ed with other computers of lower speed than
the PDP-8 provided a suitable computer to databus interface is cQnstructed.)
The type Qf operation performed with each instruction pulse has been standardized as fonQws.
Instruction Pulse
Operation
IOP1
Augmented InstructiQns
IOP2
and I/O Skip
IOP4
Input to. cQmputer
Output to. mQdules
Since it was useful to have many more than
three instructions, a syste:m for deriving a set of
augmented instructions during IOP1 is used
wherein the six low order hits of the computer
output lines are each interpreted as a separate
instruction. The six high order bits have been reserved to be us,ed in coincidence to obtain 64 additional augmented instructions, should such a
need arise in the future. IOP2 is used to. generate
all inputs so as to relax the requirement on the
fall time of the input pulses which must be clear
before the next instruction is executed.
·A mQdule requests attentiQn from the computer by energizing a co.mmo.n interrupt line
until it is s,erviced by the computer. The computer then interrogates the modules to determine
which one is requesting s·ervice. (Since a priority
interrupt system might be desirable when the
system is interfaced to. a different computer, fQur
additional lines in the data bus have been provided, which may be used in this manner.)
The I/O skip line pro,vides a means for a
module to respond to interrogation by the computer. An a.ffirmative response is signalled by
energizing this line, which. causes the PDP-8 to.
skip an instruction. If the system were connected
to a different computer, the I/O skip line could
set a status bit in the machine.
The distribution of the analog input lines to
the mQdule bins is performed with shielded
twisted pair. The interface contains a parametric
amplifier in a configuratiQn which CQnverts the
ADIOS
single ended 0 to -10V range of the an;alog to
digital converter in the PDP-8 toa +10V to
-10V differential system with good dynamic
.common mode rejection.
Since the Io.gic o.f the bus system is compatible
with the PDP-8, the interface is used simply to
provide the level shiftin-g and buffering that is
necessary to. communicate directly with the integrated circuits in the modules.
The interface unit con.verts the negative logic
levels of the PDP--8 to standard microcircuit
levels as used in the d.ata bus system. In addition
the interface input buffers provide noise filtering
and an input threshold which can be varied in
order to investigate noise margins. Tests have
sho.wn the data bus syste.m capable of operating
with cable lengths of more than 100 feet.
. The data bus co.nsists physically of 48 ilninia_
ture co.axial cables, to.gether with one shielded
twisted pair, which interconnect the required
number o.f module bins. Within the bins, the
data bus loops through twelve 50 pin connectors
into which the modules connect upon insertion
into the bins.
The plug-in modules
Four general purpose modules were designed
to. operate in conj unction with the computer to
assist in the operation and control of experiments and in the acquisition of the resulting
data. Figure 3 sho.WS one of each type of module
installed in a module bin. A mo.dified NIM power
supply located at the rear of the bin provides
local power for the modules.
The construction of all the modules is similar to
1069
FIGURE 4-Photograph of a scaler module, showing the location of the plug-in address cards at the lower center of the printed
circuit
that of the scaler, which is sho.wn in Figure 4.
The use of integrated circuits on a single special
purpose board results in considerable reduction
of Co.st and size over the mo~e usual technique of
using general purpose logic boards.' The cost of
the more complex modules is approximately $300
each.,
In order to simplify programming and debugging, the module address,es are defined by small
plug-in cards, visible in Figure 4, which may be
changed at will. Removal o.f a unit for repair
may thus be performed by switching its address
card to. a new module. A brief discussion o.f the
structure and operation o.f eadi of the modules
is given in the follo.wing sectio.ns.
Register
FIGURE 3-Photograph of one medified NIM bin containing
one of each of the four modules
The register provides a general purpose interface fo.r digital devices. It is capable o.f accepting
a 12 bit word from an external device and input.·
ting the word to the computer. It can also accept a word fro.m the co.mputer and present it,
with buffering, to the outside world. The block
diagram o.f this unit is shown in Figure 5. Table I
lists the commands for the unit, most of which
require no explanation.
The vo.ltage levels for input and output are
standard NIM and integrated circuit levels. The
use of jam transfer makes res,etting unnecessary,
and allows alteration of selected bits of the
register without even a momenta:ry change in the
other bits.
The use of master-slave flip-flo.Ps as buffers
1070
Fall Joint C'Omputer C'Onference, 1968
DATA
a
ADDRESS
INSTRUCTION
DECODING
LINE
DRIVERS
DATA BUS
BUS
INPUT
GATES
a
ADDRESS
INSTRUCTION
DECODING
INTERRUPT
BUFFER
rI
------
I
I
EXTERNAL DEVICE
L ____
12 LINES
FROM
REGISTER
I
~---------------~
,-I
FIGURE 6--8implified block diagram of relay driver module
Scaler
This m'Odule cQmprises a12 bit binary ripple
counter and the necessary logic t'O permit the
module to function on the PDP-8 data bus system. In operation the module sends an interrupt
to the CDmputer for every 4096 input pulses. The
system records the number 'Of these interrupts
and the ref'Ore functi'Ons as a scaler modulo 4096.
At the end 'Of the cQunting period the fractional
CQunt remaining in the scaler is added to the
previously recorded t'Otal. Figure 7 is a I'Ogic
block diagram 'Of this unit. A unique· feature in
this design is the use of a two address command
structure. The first 'Of these is the generic address and the second the unit address. By use of
DATA BUS
Relay module
The I'Ogic 'Of this m'Odule is sh'Own in bl'Ock diagram in Figure 6. It contains twelve single P'Ole
d'Ouble throw high speed relays each capable 'Of
switching 3 amps. It is used in c'Onjuncti'On with
a regi.ster module t'O handle signal and power
levels which are inc'Onvenient to handle electr'Onically.
The relay driver commands are shQwn in Table
II. The Test Unit Ready c'Ommand allQws the
computer to test for the presence 'Of the m'Odule.
I
L------ J
FIGURE 5-Simplified block diagram of register module
permits the register to be used as a hardware
bit-ref'Ormatting device by connecting the outputs
of the register to the inputs in the desired sequence. The word tOo be ref'Ormatted is sent out
tOo the register and then read in as external data.
This feature alsQ permits use 'Of SQme bits of the
register as input and some as 'Output, since by
connecting it bit 'Output line to the cQrresponding
bit input line one makes the value of the bit independent of the Load Register fro'm External
Unit c'Ommand.
The most serious stumbling block in interfacing an external device tOo a computer is not the
compatibility 'Of the input/'Output levels, but the
necessity 'Of establishing logical cQmmunicati'On
between the devices and the c'Omputer in a simple
way.. In the register the "freeze" circuitry allows
the c'Omputer t'O command a device to remain
stable while being read. The interrupt circuitry
allows the device t'O request service from the
computer. A busy line informs the unit 'Of the
status 'Of its request.
--,
EXTERNAL
DEVICE
UNIT
ADDRESS
INSTRUCTION
DECODING
a
r--
GENERIC
ADDRESS
INSTRUCTION
DECODING
a
LINE
DRIVERS
----,
II
EXTERNAL
I
DEVICE
L _____
..JI
FIGURE 7-Simplified hlock diagram of scaler module
ADIOS
the generic address the computer can execute any
one of three c'Ommands and have all scalers sharing that address respond simultaneously. The
c'Ommand structure f'Or the unit is shown in
Table III. Most 'Of the commands are self-explanatory. While Increment 'Operates in front
of· the input gate, Preset,. which also incre'ments,
operates at all times. Enable Generic and Disable
Generic permit the generic command,s to be
'Obeyed or ign'Ored.
The 'Overflow and saturate logic allo'w the computer to, serve as the high order portion of the
'scaler in the following manner. When the high
order bit of the scaler overflows, its overflow flipflop is set and a program interrupt is sent to
the computer. The computer then initiates a
search using the Test Overflow instructi9n and
thereby ascertains which module interrupted.
Should a sec'Ond 'Overflow occur in a scaler before the previous one has been recorded by the
computer then the saturate flip-flop is set. The
cO'mputer can test this flip-flop, ,and thus either
ascertain that the scaling has been :performed
without error or take appropriate action to insure correct scaling.
A rear panel switch connects the output of the
most significant bit to' either the O'verflow detecting circuitry or to a front panel connector,
thus all 'Owing the use of a sec'Ond scaler module
to form a 24 bit scaler if desired.
A discriminator is located at the input to the
mO'dule and its level is adjustable from -5 volts
to +5 volts. A front panel lamp indicates the
status of the input gate.
A three position switch allows manual setting
of the unit in either the start or stop condition,
or returns this control to the computer.
Programmable power supply
The primary purp'Ose 'Of this module is to al16w the co·mputer to supply adjustable voltages to
external devices. As shown in Figure 8, the computer controls the power supply voltage by causing
rotation of a motor driven ten turn potentiometer
which serves as an inexpensive anal'Og memory.
The series regulators, which operate by re-regulating the bin power, are built either as positive
or n~gative supplies, and furnish 0 to 10 volts
with overcurrent protection from 10 to 250 rna.
The control commands f'Or this unit are shown
in Table IV. The computer controls the unit by
operating the potentiometer while simultaneously
1071
DATA BUS
ANALOG
ADDRESS a
INSTRUCTION
DECODING
MOTOR DR IVEN
POTENTIOMETER
POWER
SUPPLY
FIGURE 8-Simplified block diagram of power supply module
m'Onitoring its output voltage, thus becoming part
'Of a servo lo'Op.
The fr'Ont panel dial attached to the potentiometer indicates the supply voltage directly while
also permitting manual setting of the voltage.
In addition, the module may be used as an analog
inp:ut from the 'Operator, since the computer can,
in effect, read the dial setting. Connecti'On of
the potentiometer shaft to other r'Otating equipment could also pe.rmit the computer to cause
controlled motion in the external equipment
should this be desired.
Sample applicationS
The system has been used to control, and process data from space experiments; to run nuclear
analysis displays using DAC's; and as the data
acquisition and control center for an automatic
Hall-effect measuring system.
Figure 9 is a block diagram showing h'Ow experiments are connected into the system. Note
that the computer 'Output can c.ontrol the experiment via the data bus. Computer input can store
digital 'Outputs fro,m the experiment via the data
bus, and make anal'Og measurements via the
analog bus and computer ADC.
Testing of a satellite charged particle
spectrometer
A simplified block diagram of a satellite paT-
1072
Fall Joint Computer Conference, 1968
EXPERIMENT
"X"
12 MODULE
NIM BIN
STATION I
INCIDENT
c:>
PARTlClES
r---""
, .... I DATA I
4;.-:;>j PHONE I
LLINK.J
-rI
'.y
TO LARGE
COMPUTER
FACILITY
DETECTOR THICKNESS
( i ) - 5DMU
12> -IOOMU
1 3 ) - 2MM
@ ) - 2 MM
B}
CONTROL
LEAST SIG. BITS
LOGIC
~ FROM SEQ. CLOCK
'-------"
FIGURE IO-Simplified block diagram of a satellite experiment
DIGITAL OUTPUT LINES
(ADDRESS,COMMANDS,
INSTRUCTIONS)
DIGITAL INPUT LlNES(DATA)
FIGURE 9-Simplified block diagram showing three bins connected to the data bus
ticle detector experiment is shown in Figure 10.
Particles incident on the semiconductor detector
assembly deposit their charge in one or more
detectors. Coincidence logic applied to detector
'Outputs determines the particle· type, while the
linear system sorts the energy of each particle
type into one of five consecutive energy ranges.
Sixteen different particle identifying modes
and the five channel energy ranges are controlled
by the digital outputs from the spacecraft sequence clock in such ·a way that each mode lasts
for approximately 10 seconds. For in-flight calibration the experiment contains a test pulse generator and two internal sources, each activated
by certain states 'Of the sequence clock once every
six hours·.
When tested in thermal vacuum in the laboratory by the computer system, outputs from a
register unit simulated the sequence clock and
thereby controlled the experiment modes. Calibrati'On modes were arranged to alternate between the
test pulser and internal source modes for every
complete sequence of experiment modes, interspersed with complete sequences of no excitation.
In this way a calibration cycle was repeated· about
'Once every 25 minutes, so large amounts of calibration data were processed in a relatively short
time. The sequences of no excitation were useful
for the .observation of noise counts.
Scalers were used to accumulate the five chan-
nel outputs and to transfer the counts into the
computer for printout.
Temperatures were also recorded. The outputs
of temperature sensors were switched onto the
analog bus using a relay driver and register combination, and were measured by the computer
ADC.
Although not used in this particular test, it
would be appropriate to use programmable power
supply units in a test of this kind to investigate
the effect of varying power supply voltages on
circuit performance.
Automated hall-effect measurements
An . ion implantation laboratory is in operation and many implanted diode samples will require extensive electrical testing. Each sample is
expected to go through several stages of annealing, and following each stage measurements
will be made to evaluate Hall coefficients, specific
conductivity, carrier concentration and carrier
mobility, over the temperature range 2°K to
300 o K. Figure 11 shows a simplified block diagram of the electrical system.
A large number of voltage measurements from
contact to contact are required at each temperature of interest, and the temperature stability at
each measurement point must be carefully controlled.
Figure 12 is a flow chart showing the main
steps in the computer controlled system. After
the sample is mounted and ready to' be lowered
into the cryostat, the program starts with a
comprehensive check of the hardware and a
"FAULT" printout is generated indicating the
nature of any malfunction. An "OK" printout in-
ADIOS
1073
.:.
CHARACTERISTIC
8 HALL EFFECT
TEMPERATURE
CONTROL
MAGNETIC FIELD
CONTROL
TO COMPUTER
FROM COMPUTER
FIGURE ll-Electrical block diagram of Hall effe('t
measurement system
dicates the satisfactory completion of each test.
When the hardware test is completed the sample is manually lowered into the cryostat. The
program continues by welding the sample contacts to ensure good connections and then checking that the voltage drop across each is within
acceptable limits. The weld current and the contact test current paths are selected, by using
relay units, so that they flow in the appropriate
direction (depending on the diode j unction type)
and through any desired contact.
The next step is the measurement of a complete set of diode characteristics. These are made
at several values of current, taken from a table
in memory. A first set of Hall measurements is
then made. Coefficients are processed and printed
out. A manual decision is then made whether the
Hall properties exhibited by the sample make
continuation of the measurements worthwhile.
In continuing the test, the operator types in
the upper and lower limits of temperature range
and the increments at which measurements are
FIGURE 12-Simplified ftow-gr'aph of Hall effed measurement
to be made, and· opens the liquid helium valve on
the cryostat. The computer selects the te'mperature values by interpolation from a table in
memory, starting with the lowest specified temperature. The required temperature control is
provided by the setting of a programmable power
supply whose output controls the power applied
to the sample heaters.
The computer proceeds in a similar way to
control and check the remaining experimental
conditions, as indicated in Figure 12.
The measurement of each of the many voltages
is accomplished by using relay units as multiplexers at the input of a digital voltmeter. Two
register modules are used to receive the DVM
digital data and transfer it to the computer via
the data bus. One of these registers is used to
trigger, and also to· recognize the end of each
DVM measurement, signaling to the computer
that data is ready for input.
1074
Fall Joint Computer Conference, 1968
Other applications
Many uses other than those already described
have been considered. An example is that of automated sample liquid' scintillation counting in
which programmable power supplies can pro,vide
levels'defining pulse-height windows. In conjunction with scalers this provides pulse height
analysis, while relay/register combinations can
exercise electromechanical control .
. The system may also serve as a versatile, economical alternative to large multiparameter pulse
height analyzers when u.sed in conj unction with
pulse analog-to-digitaI converters, and fast digital-to-analog converters for CRT displays.
When connected to an engineering breadboard,
the system has been used asa versatile programmed pulser and circuit tester.
DISCUSSION
The point can be made, and with justification,
that computer manufacturers realized years ago
that peripheral hardware was best handled on a
bus basis, which is all that is being achieved with
the system described here. This is quite true.
The differences that arise with on-line systemg
are primarily those of degree (with the' exception
of analog bus facilities) rather than those of
. kind. One example will suffice to make the point.
The present system might be required to handle
60 scalers all counting at '---.1 MHz (e.g., a data
rate of 6 X 10 1 bits/second) with the subsidiary
requirement that various subsets. of them be
gated on and off in exact time synchronism. Such
requirements are not encountered with standard
computer peripherals for which supervisory control and timing c'an always be exercised in a logical sequential manner.
The major point being made here is really a
different one, namely how to design a modular
system with a smaIl number of different .types
of modules to encompass a large number of online tasks~ While examples of such tasks are endless it is 'hoPed. the outline of the rationale of the
design, together with the- sample applications
given, demonstrates the flexibility that such an
on-line modular analog-digital system can provide.
A CKNOWLEDGME-NTS
It is a pleasure to acknowledge the many contributions of others to the work presented here.
Notable among these, have been E. H. CookeYarborough and his associates at AERE Harwell
in discussions of design philosophy and in providing inforrnation on their IANUS system, R.
Stensgaard of the University of Aarhus in all
phases of the work on Hall effect measurements,
and W. L. Brown of Bell Telephone Laboratories
for constant encouragement and. support.
lOP
1
1
2
4
DATA
BIT
6
7
8
9
10
11
COMMAND
Test Interrupt
Generate Interrupt from Computer
Disable Interrupt
Enable Interrupt
Set Freeze Output
Load Register from External Unit
Load Computer from Register
'Load Register from Computer
TABLE I -Register module commands
lOP
COMMAND
1
2
4
Test Unit Ready
Enable Relay Drivers
Disable Relay Drivers
TABLE II-Relay module commands
A. UNIT ADDRESS COMMANDS
lOP
'1
1
1
1
2
4
DATA
BIT
6
7
8
9
10
11
COMMAND
Test Overflow
Test· Saturate
Disable Generic
Enable Generic
Increment
Clear
Load Comput.er from Scaler
Preset
B. GENERIC ADDRESS COMMANDS
lOP
COMMAND
1
2
4
Start Scaling
Clear
Stop Scaling
TABLE III-Scaler module commands
ADIOS
lOP
1
2
4
DATA
BIT
11
10
9
8
COMMAND
Motor Off
Measurement Off
Measure Current
Measure Voltage
Motor Counterclockwise (Lower Voltage)
. Motor Clockwise (Raise Voltage)
TABLE IV-Power supply module commands
1075
A standardized data highway for on-line computer
applications
by I. N. HOOTON and R. C. M. BARNES
.4tomic Energy Research Establishment
Harwell, England
INTRODUCTION
In nuclear experiments the quantity and complexity of
the data have led to the widespread adoption of automatic processing equipment. This equipment may be
divided generally into two categories. The first consists
of data gathering and converting devices intimately
involved 'Nith the experiment, e.g., radiation detectors,
scalers and analogue-to-digital converters. The second
category consists of devices for storing and processing
the data, and for controlling the experiment. Increasing
use is now being made of small general purpose computers to perform these latter functions, in place of the
special purpose devices previously employed.
Each experimental situation requires a unique system
of equipment, although in principle the functions to be·
performed are very similar. This has led, historically, to
the creation of modular instrumentation systems to
satisfy the experimental requirements in. the first category above. For example, the Harwell 2000 Series, l the
ESONE System2 and the U .S.A.E.C. N .I.M. System3
provide standard hardware which allows up to 5, 8 and
12 modular units, respectively, to be held in a 19 inch
rack-mounted crate. Within each system mechanical and
electrical compatibility is achieved by specifying standards and codes of practice. None of these systems however incorporates a means of communicating with 'computers, and individual laboratories have adopted ad hoc
arrangements. As a consequence the representatives of
major European nuclear laboratories (see Appendix)
have collaborated under the auspices of the ESONE
(European Standard of Nucleonic Equipment) Committee to draw up recommendations for a modular system incorporating a standardised data highway. The
basic features of this system, known provisionally as
IANUS, may be summarised as follows:
a) It is a modular system so that any combination of
functional units may be assembled easily by the
experimenter.
1077
b) Each module makes direct connection to a highway
which conveys digital data, control signals and power.
The highway standards are independent of the type
of module or computer used.
c) The mechanical structure is designed to exploit the
high component packing density possible with integrated circuit packages and similar devices.
d) The data transfer highway and modules are kept as
simple as possible. Any system complexity is introduced in the interface between the computer and the
highway.
e) Although the recommendations for the IANUS system were drawn up by representatives of nuclear
laboratories it was designed as a generalised data
handling system for use in any field of instrumentation.
f) IANUS is a non-proprietary specification which is
freely available to all.
g) The IANUS system incorporates the experience
gained with previous modular systems and aims to
augment rather than replace these systems.
The system has provisionally been given the name
IANUS after the Graeco-Roman god Ianus (or Janus)
Gemini who had two faces. The system looks to the
experimental environment and to the computer. It also
looks back to previous modular instrumentation and
forward to the fully automated laboratory.
This paper gives an informal description of the IANUS
system and then outlines the way it is used at the
Atomic Energy Research Establishment, Harwell, as a
standard interface between digital computers and
peripheral devices.
The IAN US system
IANUS is a modular instrumentation system which
links transducers or other devices with digital controllers or computers. Figure 1 illustrates the use of the
system in a generalised experiment such as is commonly
Standardized .Data Highway for On-line Computer
1078
TABLE 1--8tandard dataway_ usage
Title
Designation
Use at a Module
Pins
~
Station Number
Selects the module (Individual line f.rom control station).
N
1
Al, 2, 4, 8.
4
Selects a section of the module.
Fl, 2, 4, 8, 16.
5
Defines the function to be performed in the module.
Strobe 1.
Sl
1
Controls first phase of operation (Dataway signals must not change).
Strobe 2.
S2
1
Controls second phase
Write
Wl - W24
24
Bring information to the module.
Read
Rl - R24
24
Take information fran the module.
Look-at-Me
L
1
Indicates request for service (Individual line to control station).
Response
Q
1
Indicates status of feature selected by command.
Busy
B
1
Inhibits change in Dataway signals (except as pennitted at S2).
Sub-Address
Function
Timing
(Dataway signals my change).
Q!.!:!
~
Non-Addressed
Oeerate on all features connected to them, no canmand re9.!!lred.
1
Sets module to a defined state. (Accompanied by S2)
I
1
Disables features for duration of signal.
C
1
Clears registers.
X
1
Reserved for future allocation.
P1 - P5
5
Free for unspecified interconnections.
Initialise
Z
Inhibit
Clear
(Accompanied by S2)
Reserved
Reserved Bus
Private
May be used as a patch bus.
Wiri~
Patch Points
Mandator~
Power Lines
The IANUS Crate is Wired for
+24V D.C.
+24
1
+6V D.C.
+6
1
-6V D.C.
-6
1
-24V D.C.
-24
1
0
2
CN
Additional Power Lines
Mandato~
+200
1
Main power return.
+12V D.C.
Su~~lies
Low current for indicators etc.
+12
1
-12V D.C.
-12
1
117VA.C. (Live)
ACL
1
117V A.C. (Neutral)
ACN
1
E
1
Referen~efor
Yl, Y2
2
Reserved for future allocation.
"Reserved
and Additional Lines
Lines are Reserved for the Followins Power
+200v D.C.
Clean Earth
No Dataway lines.
circuits requiring clean earth.
~
TOTAL
86
1079
::Fall Joint Computer Conference, 1968
All dimensions in millimiltres.
C ·Ianus Control Module
p
C
---1~n
IANUS
r
111.62
r~:,.
Front Panel
I
200
86 printe~ contacts
(43 per s,de)
"L/
f
Pitch of edge connectors 17·2
J
Datum Face
~~~ ~~~~_
0"""" ,,,,"
~1'---------305 --------~.l
Centre linez:
01 Card
~17'2N-0.2
Centre line
of Guide
Man-to-Machine Communication
Figure 2-Critical dimensions of the lANUS module
Figure 1-A generalised experimental system
nector on the NIM unit to the edge connector socket.
encountered in R. and D. establishments. Experhnenta
data produced by transducers may be taken directly to
peripheral modules (P) where, for example, it is digitised or buffered before being presented in standard
form to the control and data highway or 'Dataway.'
Alternatively, use may be made of equipment in other
standards with an adapter module to produce compatible signals. Other peripheral modules may be used to
provide co:m:munication between the experimenter and
the computer or to provide control signals to the experiment. Previous experiences suggest that the experimental parameters should be set up via the computer so
that they may be checked and recorded. A controller
(0) supervises the operation of the Dataway and provides connection between the IANUS system and the
computer. It will be noted that the peripheral modules
are isolated from the computer and are hence independent of its input/output standards.
Mechanical standards
A standard IANUS crate mounts in a 19 inch rack
and is fitted with 25 edge-connector sockets. Each socket, together with upper and lower guides, constitutes a
'station' into which a module may be inserted. A mod.
ule consists basically of a printed card and a front
panel. Runners on the module engage with the guides in
the crate, and 86 printed plug contacts on the card mate
with the edge-connector socket. Figure 2 shows the critical dimensions of the module which define the position
of the printed contacts in relation to the runners and the
front panel. Any method of construction which conforms
to these dimensions will be compatible with a standard
crate. A module may occupy as many crate positions as
.are required. Units in the U.S.A.E.C. N.I.M. format
will fit into the guidance system, with each NIM single
width occuping two basic IANUS widths and a simple
adapter completing the connection from the AMP con-
The Dataway
The Dataway is a standard highway which conveys
digital data, control signals and power. It consists
mainly of bus-lines joining corresponding pins on the
86-way edge-connector sockets within a standard crate.
One station, known as the 'control station,' has individual lines to each other station. The module occupying the control station acts as a 'controller' for its crate.
During each Dataway operation the controller generates a command on the control lines of the Dataway. It
is implicit in all data transfer operations that one p9.rticipant is the' controller and the other is the module or
modules specified by the command. In practice the
various features which constitute the controller may be
distributed among several physical units. It is convenient to distinguish between the controlling and controlled parts of a system by the generic terms 'controller' and 'modules.' The Dataway includes lines by
which modules can demand attention and a line by
which the controller can test the status of a module.
The Dataway lines (see Table I) may be divided into
seven categories as follows:
A command consists of signals which
select a specified module or modules within a crate
(by station number lines), a particular section of the
module (by sub-address lines) and the function to be
performed (by function lines). Each normal station is
addressed individually by a signal on one of the station
number lines (N) which link the control station separately to each other station (see Tables II and III).
There is no restriction of the number of modules that
may be addressed simultaneously, so that the same
command may be given to any desired selection
of modules in the same oper~tion. The duration of
the signal on the N line defines the Dataway operation period.
1. Commands:
'1080
Fall Joint Computer Conference, 1968
TABLE II-Pin allocation at normal station viewed from front of crate
Individual Patch Point
"
"
"
"
""
"
"
"
"
"
"
Bus Line with Patch Point - Reserved
Inhibit
" .. Clear
"
" " "
" "
"
"
"
Individual Lines
-_ Station Number
[
with Patch Points
Look-at~e
Bus Line
- Strobe 1
.. Bus Line
- Strobe 2
24 Write Bus Lines
W1 = least significant bit
W24 = most signi ficant bit
24 Read Bus Lines
R1 = least significant bit
R24 most significant bit
=
Reserved for -12 volts D.C.
Reserved for +200 volts D.C.
Reserved 117 volts A.c. Live
Reserved
Reserved for + 12 volts D.C.
Reserved
o volts (Power retarn)
P1
P2
P3
P4
PS
X
B
F16
F8
F4
F2
F1
Z
"
"
"
"
Sub-Address
"
"
"
Initialise
Q
Response
I
A8
C
A4
N
L
Sl
S2
W24
W22
W20
W18
W16
W14
W12
Wl0
W8
W6
W4
W2
R'24
R22
R20
R18
R16
R14
R12
R10
A2
A1
W23
W21
W19
W17
W1S
W13
Wll
W9
R6
R4
R2
-12
+200
ACL
Y1
E
+12
Y2
+24
+6
0
0
Signals on the sub-address bus li:i1es (A8, A4, A2 and
AI) specify one of the, 16 sub-addresses in the module.
This sub-address may be used to select a specific
register, to define which of sixteen different flags controls the Response signal, or to direct functions such
as 'enable,' 'disable' or 'clear' to the required section
of the module.
Signals on the five function bus lines (FI6, F8, F4, F2
and Fl) specify one of 32 functions. Sixteen of these
functions are fully defined within the lANDS recommendations. This permits the same command to be
interpreted correctly in modules from different designers and assists in the design of table-driven software.
The remaining si~teen codes are available for special
functions at the discretion of individual designers.
The standardisation of codes is discussed more fully
below in the section on 'Function Codes.'
2. Timing: Each Dataway operation occurs asynchronously, and is timed by two strobes S 1 and S2 which
are generated in sequence on separate bus lines. The
-
Bus Line
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
W7
WS
W3
Wl
R23
R2l
R19
R17
RIS
RU
Rll
R9
R7
RS
R3
Rl
-24
-6
ACN
R8
Busy
Function
-24 volts D. C.
-6 volts D. C.
Reserved for 11 7 volts A. C. Neutral
Reserved for Clean Earth
+24 vol ts D. C. .
+6 volts D.C.
o volts (Power Return)
ti.mes, Tl to T5, shown in Figure 3 may each have
any value greater than a prescribed mini.mum. This
minimum is currently defined as 200 nS. The signals
conveying the command are maintained throughout
each Dataway operation and the other signals are set
Command
.-1-----ljJS(min.)----.l·1
Signals ~!-I-_ _ _ _ _ _ _ _
--!V-
51
52 - - r - - + - - + - - ' "
TI
T2
Figure 3-Dataway timing
Standardized .D'ata Highway for On-line Computer
1081
TABLE III-Pin aiIocation at control station viewed from front of crate
Individual Patch POint
"
"
"
"
"
"
"
tI
tI
"
Bus Line with Patch Point
"
"
"
"
"
"
"
Individual Patch POint
"
Pt
P2
P3
P4
P5
""
"
-
Reserved
Inhibit
Clear
-
Strobe 1
Strobe 2
n
Bus Line
Bus Line
24 Individual Look-at-Me Lines
Reserved fOr -12 volts D.~
Reserved for +200 volts D.C.
Reserved for 117 volts A. C. Live
Reserved
Reserved for +1 2 volts D. ~
Reserved
o vol ts (POoVer Return) .
X
I
C
P6
P7
Sl
S2
L24
L23
L22
L21
L20
L19
L18
L17
L16
L15
L14
L13
L12
Ltt
LlO
L9
L8
L7
L6
L5
L4
L3
L2
Ll
-12
+200
ACL
Y1
+12
Y2
0
up as soon as the command has been interpreted. For
example, a module instruct~d to transmit will establish its data on the 'Read lines' in response to the command. Sufficient time is allowed for the data to settle
before the first strobe (81) admits this data to the
controller. S1 is used for actions which do not change
the state of signals on the Dataway. The second
strobe S2 may be used to initiate actions which
change the state of Dataway signals, for example,
clearing a register which has just been read and whose
output is connected to the Dataway.
3. Data : Up to 24 bits may be transferred in parallel to
or from the selected modul~. Independent lines
('Read' and 'Write') are provided for the two directions of transfer.
All information carried on these data lines is regarded
as 'data' although it may in specific instances be concerned with the status or control features of the modules. The 24 parallel lines in each direction set an
B
Ft6
F8
F4
F2
Fl
Busy
Function
AS
Sub-address
A4
A2
At
"
"
Z
Q
N24
N23
N22
N21
N20
N19
N18
N17
Nt6
N15
N14
N13
Nt2
Nt1
NlO
N9
N8
N7
N6
N5
"
"
"
"
"
Initialise
Response
-
Bus Line
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
24 Indi vidual Station Lines
N~
N3
N2
Nt
-24
-6
ACN
E
+24
+6
0
-24 vol ts D. C.
-6 volts D.C.
Reserved for 117 volts A. ~ Neutral
Reserved for Clean Earth
+24 vol ts D. C.
+6 volts D.~
o volts (POoVer Return)
upper limit to the word length but shorter words may
be transferred.
As shown in Tables II and III, the data lines are not
taken to the control station, where the corresponding
pins are used for Nand L lines. A controller therefore
requires connection to the control station and one
normal station.
4. Status: Individual Dataway lines from each station
to the control station are used for 'Look at Me' signals (L) by which modules can demand attention.
The action taken in response to such a signal is a property of the controller and/or computer.
The L signals may be cleared, enabled and disabled
by appropriate commands.
The status of the Dataway itself is indicated by a Busy
signal (B). While· the N signal specifies the duration
of a Dataway operation to the modules involved, the
B signal indicates to all modules that an operation is
in progress. I t is generally used to staticise the con-
1082 Fall Joint Computer Conference, 1968
ditions on the Dataway so as to reduce crosstalk.
While B is present all signals, including for example L
signals, must remain constant unless their state is
modified at S2.
The status of any specific feature of a module may be
tested by a command to transmit a signal on a common Response (Q) bus line. The appropriate signal is
set up on the Qline by the module as soon as the command is recognised, it is strobed into the controller at
Sl and may be changed at S2 if the feature being
tested is set or cleared then. One bit of status information may thus be sent to the controller with every
Dataway operation and may, for example, be held
in a one-bit register for testing by the computer. The
module designer is free to decide which feature, if any,
is tested.
An obvious application of the Response signal is to
test for the source of a 'Look at lYle' demand in a system which has only a single-level interrupt. In more
complex installations ~t may identify which of several
possible demands has originated from the same module.
5. Common Controls: Common control signals operate
on all modules connected to them without requiring
individual addressing signals.
The Initialise signal (Z) is generally connected to all
modules and forces them to a basic state by resetting
all data and control registers. It also clears all L signals and where possible disables them. It provides a
quick and sure method of dealing with the situation
at switch-on when registers and control bistables
may, in principle, have assumed unpredicted states~
A common time control is provided by an Inhibit signal (I). This may be connected to any modules which
require accurate timing of activities, such as data
taking, independent of computer access times. The
Inhibit signal may be controlled by any appropriate
signal from the computer, the IANUS system or elsewhere.
A common Clear signal (C) may be connected to any
selection of modules in which data registers require to
be cleared.
As a protection against spurious signals both the Initialise (Z) and Clear (C) signals are accompained by
the S2 strobe.
6. Private Wiring: Five ways on the 86-way socket are
not connected to bus lines but may be brought out to
individual local pins on the Dataway wiring. They
are available for unspecified patch connections subject
only to the restriction that the signals must not interfere with standard Dataway signals and must be able
to tolerate some crosstalk from the Dataway lines.
Highly sensitive signals or those that require coaxial
connection are more appropriately located in the
space provided above the edge connector socket.
7. Power: The mandatory power supplies, which may
be used by any module, are +24V, +6V, -6V and
-24V d.c. The maximum current loading for a crate
is 6A for each 24 volt line and 25A for each 6 volt line.
The recommended total power dissipation is 200W
per crate. Two pins are provided in parallel on the
edge-connector as a heavy current 0 volt return for
digital circuits.
Lines are provided for + 12V and -12V d.c. optional
supplies. Low current lines are allocated for a +200V
d.c. supply (primarily for neon indicators) and for
117V a.c. (two lines.) There are also two 'reserved'
power lines which may be allocated in the future. A
return, independent of and isolated from the digital
ovolt line, is provided for low current operations that
require a 'Clean Earth.'
Signal standards
The signal standards are derived from CompatibleCurrent-Sinking-Logic (CCSL), that is, Diode-Transistor-Logic (DTL) and Transistor-Transistor-Logic
(TTL). In all situations where more than one module
may feed onto a line intrinsic, (or wired) OR operation is
specified. This requirement makes it appropriate that
the 'Low' state (short to ground) be interpreted as the
significant or '1' state while the 'High' state (open circuit) is the non- significant or '0' state.
Function codes
While it is desirable for table-driven software, for
autonomous operation, and for multiple addressing to
have standardised functions, it is impossible to legislate
for all possible modules. Half of the 32 functions (see
Table IV) are therefore fully specified and the other half
are available for special applications. For software convenience a single bit (F4) distinguishes between standard (Le., universal) codes and non-standard (Le., local)
codes. Similarly, bit F16 specifies the direction of data
transfer. This is an important feature with some computers when the controller must interpret the function in
order to set up the required data path.
Registers within a module may be divided into two
groups which have independent commands. It is therefore simple to distinguish between control and data registers. This is particularly useful in a system which
makes large scale use of autonomous transfers or in
which it is desired to 'step through' registers on the subaddress codes.
The incrementing functions are provided mainly as a
test facility; code 27 in particular permitting a group of
preselected registers within a module to be incremented
simultaneously.
Standardized .D·ata Highway for On-line Computer
1083
TABLE IV-lANUS function codes
I No.
0
1
2
3
Function
Read
Read
Read
Read
Group 1 Register
Group 2 Register
and Clear Group 1 Register
Canplement of Group 1 Register
4
5
6
7
Non-s tandard
Reserved
Non-standard
Reserved
8
9
10
11
Test Flag
Clear Group 1 Register
Clear Flag
Clear Group 2 Register
12
13
14
15
Non-standard
Reserved
Non-standard
Reserved
16
17
18
19
20
21
22
23
24
25
26
27
28
29
~
31
Overwrite
Overwrite
Selective
Selective
Group 1 Register
Group 2 Register
Overwrite Group' Register
Overwrite Group 2 Register
State After SI
Q = FA;
Q = FA;
Q = FA;
Q = FA;
Ci
= 1Ai
Ci
=
State After S2
LA = 0;
LA = 0;
LA = 0;
LA = 0;
Ci = 2Ai
Ci = 1Ai
'Ai
Q= FA
Q = FA
Q = FA
Q = FI\
Q
Q
Q
Q
= FA;
= FA;
= FA;
= FA;
Q = FA
Q = FA;
Q = FA
Q = FA;
= Il\i
= 2Ai
= 0
= 1Ai
FA = FA
FA
= Ci
2Ai = Ci
If Ki = "
'Ai
If Ki
=
1,
1Ai
2Ai
= Ci;
= Ci;
If Ki = 0,
If Ki '" 0,
'Ai = 1Ai
2Ai = 2Ai
LA
LA
LA
LA
=0
=0
=0
=0
=0
Non-standard
Reserved
Non-standard
Reserved
Disatile
Increment Group 1 Register
Enable
Increment Preselected Register
1Ai
2Ai
1Ai
1Ai
RA=RA+l
Rp=Rp+l
Non-standard
Reserved
Non-standard
Reserved
Q is tne state of the Q line.
FA is the state of the Flag associated with the selected sUbaddress.
LA is the state of the Look at Me assOCiated with the selected subaddress.
Ci is the state of the ith bit of the register in the controller.
1Ai is the state of the ith bit of the register, selected by subaddress,
fran a first group of registers in the module.
2Ai is the state of t}le ith bit of the register, selected by !'IIbaddress,
fran a second group of registers in the module.
The tenn Overwrite (codes 16-19) is synonYlnous
with 'Jam Transfer'-a term which has led to some confusion, particularly in translation.
Application of the system
The IANUS specification sets out in detail the logical
and electrical features of a data and control highway
within a single crate system. It also defines themechanical dimensions necessary to ensure that modules from
different sources are mutually interchange::j,ble. These
recom:mendations have been accepted by major nuclear
laboratories throughout Europe.
In practical applications of computer-based data processing it is also necessary to specify the computer-tocrate and crate-to-crate interconnections. The following sections describe the local standards and techniques
adopted at A.E.R.E., Harwell, for computer-based
IANUS systems.
External representation of the command
A command is represented within a IANUS crate by
'Ai = 0
2Ai = 0
•
•
•
•
F
16
F
8
F
4
F
2
F
1
No.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
8
9
10
11
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
12
13
14
15
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
I'
0
1
0
1
16
17
18
19
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
20
21
22
23
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
24
25
26
27
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
1
~
31
Ki is the state of the ith bit in a mask register.
RA is the content of a register selected by subaddress in the module.
Rp is the content of a register preselected in the module.
Q = FA indicates that the state of the Flag at the selected subaddress
is tested before the Flag is cleared.
• Data transfers 'Ai = Ci and 2Ai = Ci may, alternatively, orcur at
Strobe 52.
a 5-bit function code, a 4-bit sub-address code, and signals on the appropriate station number (N) lines. When
the command is transmitted externally, e.g., between a
crate and a computer, it is generally perferable to use a
5-bit code for N instead of the internal 24-bit form. The
decoded values 1 through to 24 are used to address the
corresponding stations directly. The remaining codes
(25 through to 31) may have special applications. For
example Code 31 may be interpreted as 'address all
modules' and Code 30 as 'address preselected modules.'
This makes it possible to address the same command to
a selection of modules simultaneously.
The command to a single crate requires 14-bits. In
multi-crate systems the command is extended to include
a binary coded crate address, e.g., a 16-bit command
will control a 4-crate system.
Multi-crate operation
In a single-crate system the controller has to perform
logical and level conversions between the specific
computer and the IANUS standards. This 'Master
1084
Fall Joint Computer Conference, 1968
Controller' is given the crate address '0' so that it can
operate with 14-bit commands. The number of crates
may be extended by providing a 'Line Driver' module
in the master crate. This buffers the Dataway bus-lines
onto an external highway which feeds a 'Slave Controller'in each added crate. The line driver and slave
controller modules .are independent of the computer
type. The master crate may contain more than one line
driver module, so that the connections to slave crates
can be arranged as a star rather than as a highway (see
Figure 4). Some conneetions, in addition to the Dataway, are required between the master controller and
line driver modules, e.g., for the coded crate and station
addresses. These are provided by a multiway socket
above the Dataway at the rear of the crate.
Program interrupt demands
The individual Look -at-l\/Ie (L) signals within a single
crate are brought to the controller via the Dataway.
There are three general methods by which the computer
may identify the source of the demand. Firstly, the L
signals may be taken individually from the controller to
a multi-level priority interrupt option on the computer.
Secondly, the demands may be combined into a single
program interrupt request, leaving the compute-r to
identify the highest priority demand by a search algorithm. This may operate on either the individual sources
of L signals by 'Test Flag' commands, or on a 24-bit
status word giving the pattern of demands on the L
lines. Thirdly, the controller complex may include a
CRATE 2
Slave
Controller
D
:
CRATE I
To/from r-----__,c--~r__-..___.f---__r_---__,
Remote
Line Drivers
Crate
CRATE 0
CRATE 3
Slave
Controller
[]
Figure 4-Multi-crate interconnection
'priority sorter' module to select the highest priority demand and identify it to the computer. These three
methods may be combined in various degrees.
In a multi-crate configuration a single status flag is
generated within each crate to indicate that a demand
is present. The intercrate connection provides a commonline for these flags, a response line by which the
mastel controller may staticise the crate demands, and
iines on which the highest priority crate may indicate
its binary coded address. In such an arrangement each
additional crate automatically adds a crate priority level to the system. Altelnatively the indi.vidual crate
flags could be assembled into a status word in the master controller. When the crate has been identified by
the computer any of the previously described rnethods
may be used to locate the individual module making the
request.
Autonomous operations
Autonomous operations typically transfer data to or
from the computer store via direct access I/O channels
in response to a Look-at-1Vle signal, without requiring a
direct command from the computer program. Each de~
mand may result in one Dataway operation (Simple
Autonomous Operation) or a sequence of Dataway oper;..
ations (Complex Autonomous Operation).
Simple autonomou8 operation8: Demands for simple
autonomous operations originate in precisely the same
way as demands for program interrupts, i.e., as Look-atMe signals generated in modules and transmitted along
the individual L lines to the crate controller. Here they
are not combined, as demands for program interrupt
may be, but are routed as individual signals to a priority
sorter module in the same crate. This module generates
a request for autonomous operation on a common line to
the master controller, which then freezes the priority
sorters and reads a channel number code corresponding
to the highest priority demand present. The channel
number. specifies the type and direction of transfer required. The controller, in conjuction with a direct-access I/O channel of the computer, initiates either a
Dataway Read operation followed by an input to the
computer, or an output from the computer followed by
a Dataway Write operation. The simplest priority sorter generates a command consisting of one function bit
associated with the channel code (giving a choice of
function 0 for Read transfers or function 16 for Write
transfers), and a station number derived from the identity of the L line. The sorter can, however, be elaborated to generate a full command with choice of station
address, sub-address and function codes. On completion
of the transfer the priority sorters are released. If a buffer area limit ('End of Record,' 'Word Count Overflow') .
Standardized .Data Highway for On-line Computer
in the computer has been reached, a program interrupt
is generated.
Multi-word records may be transmitted from a module by maintaining the demand flag after the completion
of each transfer until the record is complete. However,
since the system operates in multiplexer rather than selelJtor mode, a higher priority demand will interrupt the
sequenrte.
Complex autonomous operations: These consist of a defined sequence of different Dataway operations initiated
by a single demand. One complex operation may include, for example, reading some registers, writing into
others and generating a program interrupt. One or more
such operations are controlled by a 'programmer' module which holds a list of extended po:m:mands, each consisting of the normal co:m:mand together with a channel
code (as described above). There is also a tag bit indicating the last extended command in the sequence. A
Look-at-Me signal demanding a complex operation
starts the appropriate sequence in the progra:m:mer,
which then competes with any other requests for autonomous operations. When its request is granted the programmer sets qp the first extended co:m:mand, and the
master controller initiates the appropriate I/O and
Dataway transfers. The progra:m:mer repeats its request and generates successive extended co:m:mands until the sequence is completed. If a higher-priority demand intervenes the progra:m:mer remains locked at its
current state until it is able to resume the sequence.
The progra:m:mer may have a patchboard on which the
list of co:m:mands is set up manually, or a scratchpad
memory which is loaded by ,the computer. Alternatively it may have fixed, prewired co:m:mands to suit a
specific application.
Module-to-mod~e
transfers
Information may be transmitted between modules
via the computer in two Dataway operations. A direct
module-to-module transfer in a single operation may be
performed under progra:r:n control or autonomously. In
'the latter case it is identified by a specific autonomous
channel code. Since two modules are involved, one
Reading and the other Writing, it follows that on~ of
them"must interpret the Dataway command in a nonstandard manner. During this operation the master
controller couples the Read and Write lines in order to
complete the data path.
. Error checking
The IANUS system incorporates facilities for checking data transfers within its own boundaries.. In a
Write operation a data word isest~blished on the Write
lines of the Dataway by the controller and strobed into
1085
the module by S1. The data signals are maintained but
the function code is then forced to 'Read Complement'
(Code 3). The content of the module register is unaffected by this command but the complement of its content is put out on the Read lines. A separate module
checks that corresponding bits on the Read and Write
lines are in fact complementary. The original function
code is then allowed to return and the Dataway operation completed.
With a Read operation the same procedure is followed
except that, after the data have been transferred from
the module to the controller, the 'Read Complement'
function causes the module to put the complement of its
register on the Read lines and the controller to put the
coritent of its data register on the Write 1ines. The comparison then continues as before.
This technique is more rigorous than a simple parity
check and requires no additional lines on the Dataway.
The hardware to generate complements need only be
added in those modules which require error checking.
The technique is equally applicable to program controlled and autonomous transfers. Only one comparison module is required in a multi-crate system and may
be installed in any crate.
Sub-standard systems
Simple laboratory experiments often make use of
small computers which may have only a 12-bit word
length, program controlled input/output, and a singlelevel program interrupt. Cost is a major consideration
is these systems.
Many modules transfer 12-bits or less per operation.
When more bits are essential they may be accessed in
12-bit byte mode by separate transfers at different subaddresses. The computer word length makes it desirable
that the command is also limited to 12-bits. This may
be achieved with 4-bits for the coded station number
(N), 4-bits for the sub-address (A) and 4-bits for the
function (F). The restricted address code permits only
16 stations to be addressed. However, the controller
itself occupies a number of stations, and certain modules
such as fixed gain amplifiers do not require addressing.
The reduced function code permits the use of a 16 func
tion subset containing all the standard codes shown in
Table IV, or an eight function subset of standard codes
(such as Codes 0, 2, 8, 10, 16, 18, 24 and 26) with an
additional eight non-standard codes.
The simple interrupt facilities of the computer are
used by combining ail the L signals as a common interrupt request. With a short connection between the
crate and the computer it may also be possible to join
the Response line (Q) directly to the computer 'Skip' or
'Branch' facility.
1086 Fa]l Joint Computer Conference, 1968
IANUS is particularly suitable for simple applications
since the compatibility problem.s are restricted to the
controller. Any pe.ripherals developed specifically for
. simple systems are fully comratible with larger systems.
Such simple systems may be expanded by the addition of a data buffer register to give the controller 24-bit
capacity. Data transfers will now take two I/O opera·
tions for modules utilising more than 12-bits. However,
virtually the entire range of standard modules-becomes
available to the experimenter.
System expansion
The expansion of a system to provide any of the facilities outlined above is achieved by additions to the controller and associated units. This capability therefore
neither requires modifications to standard modules and
the Dataway nor raises their basic cost.
The growth of a minimum program-controlled system
into a complex system with autonomous and pregranuned transfers will be given as an example. Conversion from a sub-standard syste:m to one with the full
range of function codes and station addresses involves
the replacement of the controller. All further developments are achieved by the addition of appropriate units.
CRATE 1\.
Extension from a single-crate to a multi-crate system requires a line driver module -in the master erate and a
slave eontroller in each additional crate. Systems with
autonomous transfers need priority sorting modules for
simple operations and programmer modules for complex
operations, the ntimberof each depending on the system
configuration. The same peripheral modules :may be
used in both programmed and autonomous modes. An
error-checking :module may be added to any standard
system. Since a standard co:mmand structure is used,
syste:m expansion does not destroy program co:mpatibility. At any stage a change to a different type of computer involves only the replacement of that portion of the,
master -controller which adapts the logical and e]ectrical signal standards. A highly simplified out1ine of a
multi-crate system is shown in Figure 5.
CONCLUSIONS
The pooled resources of major European nuclear laboratories have established the specification for a new
range of modular instrumentation as an international
standard. This includes the connection of modules to a
data and control highway within a single crate. At
A.E.R.E., Harwell, this work has been extended to
I
DATAWAY
~
Data &
Control
1--
---
1
I
,
~T~O~E~XP_E_R~IM~E~N~T__________L__-_-_-+l_-_--______-_-_-~l---CRATE
I
I
MODULE
0
,
Transfer Request
I
Program
1
Interrupt Request
,I
I
I1- _ _ _ _ _ _ _ _ _ _ •• ____ -
___ -
__I
-
Data &
Control
Auton omous
R4!qu ests
DATAWAY
EBJ.Q8!.I.X
SORTER
---I
'AUTONOMOUS I
I PROGRAMMER I
,
,
I Coded }
, Address
~
I
I
I
I
',~
1
1
,I
I •
,
_______ .J
MASTER
CONTROLLER
I
'D4!mands
---r--
Autonomous
r--
I seqU4!nCed}
EXPERIMEN~
I
I
Data & Control
r--
1
TO
I
... _______ ..1
1
:P-;RIP~ER:;;:LI
1
I
I
I
1
Data &
Control
--I
SLAVE
CONTROLLER
I PERIPHERAL
I MODULE
I
I
I
I
I
1
Initiating D4!mand
r
I
I •
Autonomous Requ4!sts
Program Interrupt Requests
"
L---r-_J ,-
I
I ndividual
~
:
_____ .JI
Data
&
ontrol
Multiplutll
Autonomo
R4!quests
5
Program
Int4!rrupt
R4!quests
TO COMPUTER
Figure 5-Schematic representation of a complex system
Interrupt
Requests
Standardized Data Highway for On-line Computer
include multi-crate systems with programmed and
autonomous transfers to and from on-line co~puters.
and Applied Physics Division and the authors must express their thanks to their many colleagues on this
project .
. ACKNOWLEDGMENTS
The develop:rnent of the IANUS system would have
been impossible without the active collaboration and
good will of representatives from laboratories throughout Europe. The authors hope that this attempt to present the results of that collaboration will indicate their
gratitude.
The work at the Atomic Ell:ergy Research Establishment, Harwell, has been conducted in 'the Electronics
. REFERENCES
1 Harwell 2000 series specification and guide SG2000
AEREUKAEA
.
2 ESONE standards EUR 1831e
Euratom Ispra
3 U SAEG nuclear instrument module series
TID 20893 (Revision 2) National Bureau of Standards
Washington, DC
APPENDIX
Organisations which ,took part in the specification of the JANUS system
International
Austria
Belgium
Britain
France
Germany
Holland
Italy
Yugoslavia
Switzerland
Secretariat
1087
CERN, European Organisation for Nuclear Research, Geneva
Centro Comune di Ricerca (Euratom), Ispra
Bureau Central de Mesures Nucleaires (Euratom), Geel
Studiengeaellschaft fur Atomenergie
Centre d'Etude de l'Energie Nucleaire (CEN)
Atomic Energy Research Establishment
Rutherford High ~nergy Laboratory (SRC)
Daresbury Nuclear Physics Laboratory (SRC)
Centre d'Etudes Nucleaires
Centre d'Etudes Nucleaires
Physikalisches Institut der U niversitat
Deutsches Elektronen Synchrotron
Hahn Meitner Institut
Kernforschungsanlage
Kernforschungszentrum
Physikalisches Institut der Universitat
Reactor Centrum Nederland
Laboratori Nazionali (CNEN)
Centro Studi Nucleari (CNEN)
Centro Studi Nucleari Enrico Fermi (CESNEF)
Centro Informazioni Studi Esperienze
Instituto di Fisica
Boris Kidric Institute
Institut fur Angewandte Physik der Universitat
Dr. W. Becker, CCR, Euratom, Ispra
Switzerland.
Italy.
Belgium.
Vienna.
Mol.
Harwell.
Chilton.
Daresbury.
Saclay.
Grenoble.
Marburg.
Hamburg.
West Berlin.
Julich.
Karlsruhe.
Frankfurt.
Petten.
Frascati.
Cassaccia.
Milan.
Milan.
Bari.
Belgrade.
Basle.
Italy.
Use of computers in a molecular biology laboratory
byT. H.GOSSLINGandJ. F. W. MALLETT
M.R.C. Laboratory of Molecular Biology
Cambridge, England
.
INTRODUCTION
On-line computers have been making considerable pro-.
gress in recent years, to the point where they represent
a sizeable proportion of the computing field. Only lately
however, have they started to make their mark in the
laboratory as a research tool. In this paper, we shall
illustrate this application from our experience in molecular biology.
In our laboratory at Cambridge, we have been using a
time-s~aring on-line computer (a Ferranti Argus 300)
for a little over three years. We hope that the techniques
that we have developed will be of interest to others, and
also that our experience in running this kind of computer
in a specialized environment may be illuminating. We
shall also say a little about possible future developments:
Molecular biology is a science in which computers
have a central role. This is particularly truein the study
of protein structure, simply because of the enormous
quantity of data to be processed; one of the final proces~es, a three dimensional Fourier transformation, may
typICally contain some 106 terms, and have required as
many measurements. Until a few years ago this was
entirely off-line computing, i.e., data in num:rical form
had to be prepared by hand, and the output, also
numerical, required considerable further hand processing to get it into a useable state. Certain parts of the
process, particularly data collection, have gradually become automated to the extent that punched tape or
cards can be directly generated. From now on, however,
we shall see more computers being used for on-line data
collection and reduction, for control of experiments, and
presentation of comprehensible results.
Since we shall be concentrating mainly on protein
structure, it might be as well to summarize briefly what
is already known on this subject. A protein is simply a
very large organic molecule-of the order of thousands
of atoms. Fortunately, this apparent complexity is reduced by the. fact that the molecule is a folded chain
of about 200 amino-acids, and there are only twenty
amino-acids to choose from. To understand how a pro-
tein works, we need to know both the sequence of aminoacids in the chain and the' physical structure-the way
in which the chain is folded. There are thus two parts to
the study, chemical and physical, and these are complementary.
In Figure 1, we show these two approaches, with an
indication of the places where computers come into the
pic~ure, or might do so in the future. The computers
have been classified as "small," "medium" and "large";
this classification is deliberately vague, but roughly
the dividing lines may be taken in this context as about
20,000 and 100,000 bytes (of 8 bits) of core store, with
appropriate backing store in each case. The many computers shown do not have to be separate, of course. In
our case, we make do with two: the on-line computer already mentioned in the laboratory, and an IBM 360 a
few miles away. The two machines communicate with
each other by magnetic tape, on a daily courier basis.
Use in crystallography
Let us begin with the physical approach-the study of
structure by means of X-ray crystallography. To use
this technique, the protein must be grown as a crystal,
which is a regular lattice of identical molecules in the
same orientation. If this is placed in a monochromatic
X-ray beam,it acts as a diffraction grating, in that, for
certain specific orientations, diffracted beams, called "reflections," are produced. From the intensities and
phases of tlIe reflections, it is possible to reconstruct the
internal form of the molecule, by Fourier synthesis.
Unfortunately, phases are not directly measurable; they
can, however, be inferred by repeating the measurements for the same protein, with a heavy atom chemically attached at a known point-this process is similar
to holography.
Usually two or three such "heavy-atom derivatives"
are needed, and this adds to the amount of data that
must be collected. Typically, a total of 106 reflections
would resolve a protein to about 2 Angstrom Units,
which is not fine enough to see individual atoms, but al-
1089
1090
Fall Joint Computer Conference, 1968
lows identification of the amino-acids, given the chemical sequence.
There are two basic methods of collecting the intensities of reflections from a crystal: diffractometers and
X-ray film. A diffractometer (Figure 2) is an instrument for orienting the crystal and an X-ray quantum
detector accurately-to about one minute of arc-orientations being changed from reflection to reflection.
Computation of the setting angles involves a certain
amount of trigonometry, and the accuracy required im-
plies that it must be done digitally. X-ray quantum counting 1S also inherently a digital process, and most diffractometers are now therefore automated to the extent of
taking in settings from pre-computed ~ards or paper tape,
and punching out ~he measurements in a similar form.
From here it is a small step to connect the diffractometer directly to an on-line computer. This offers two
advantages. First, the data can be compressed as they
are collected, so that not only is the convenience in-"
creased but also the errors introduced by electro-
FIGURE I-General diagram of the stageEl in solving a protein structue
ISOLATE
PROTEIN
CHEMICAL"
PHVSlCAL. STRUCTURE
(X-ray or neutron diffraction)
STRUCTURE
Chemistry: brsk
into Ca'lStituent
amino acids
Chemistry: aystallts. natiw Prot.in and
hay-atom derivatives
down
o •0
AMINO
ACID
ANALYSER
Crystals
DIFFRACTOMETER
CAMERA
METHODS
METHODS
reccrd
"\
manual
analysis
manual
c:::r'densitometry
Medium Off-line
Comput~r:
density
sc:aUng. merging.
phasing & Fourier
transformation
peak analysis
structu~ computation
& refinement
(f:\atomic
WCo-ordinatn
1
M4tdium Off-lin.
Comput4tr& Plott.r: _
rotation & perspectMt
~
"~
~
0-
structural views
rnNIUNmInts
~
W
M4tdium Online Computer:
mNSurement &
control
MICRODENSITOMETER
Use of Computers in Molecular Biology Laboratory
.
I' \
1091
.
.,
." ,.
,t ••
C"~,,,,
<,0\
-
;
.
,1:»)
":'./",
(~
"
, I
/
\1'
FIGURE 2-A typical diffractometer
mechanical' devices are reduced. Secondly, it becomes
possible to monitor the data collection process in a
"closed-loop" mode, and correct for minor error~ as they
arise.
The control of diffractometer setting and output of
basic measurements can be carried out on quite a small
computer. If it is larger-somewhere in our "medium"
range-then it is possible to do some of the preliminary
processing of data, and add the monitoring function.
The final assembly of complete data, involving scaling
of measurements from a number of crystals and determination of phases, must in any case be carried out on
a large off-line machine.
Presentation of results
Before turning to the other method of data collection,
X-ray film, we must digress to the far end of our subject, namely the presentation of results. Mter the
measurements have been assembled in a large computer, a Fourier transformation is applied to them, the result bei;ng a three-dimensional map of electron density
in the molecule. This map is in the form of spot values
of density on a regular grid. Traditionally, this ~as
listed on the output printer, section by section, and contoured by hand; if the crystal axes were not orthogonal,
then the numbers had first to be transferred to suitably
laid out paper, also by hand. In all, the process took
about a day and a half per section-two to three months
for a complete molecule.
When we purchased our on-line computer, for
ftJ
4»
~
0.25
5
Harmonic
, FIGURE 5-Amplitude-frequency spectrum of blood pressure
waveform (From Patel, 1965)
"Problem" waveforms
While the classical shape of the blood pressure
waveform is that illustrated in Figure 4, other
shapes are frequently enc'Ountered. A sample of
such .shapes is shown in Figure 6, the records being taken from 6 different patients. All of the
patterns shown are' accurate recordings made with
the same critically damp system as described above
and the differences are therefore not due to artefacts, although their explanation lies outside the
purpose of this paper. Their importance lies in the
fact that short periods of the overall wave during
which a sign reversal occurs must not be recognized by the programme as new heart beats. Difficulties arise particularly when detailed predictions
based on the exact shape of the waveform are to
be made, especially since the pattern may not be
constant even in one patient. This is demonstrated
in the records shown in Figure 7 where the shape,
.DC level, pulse amplitude and rate of the bl'Ood
pressure wave all change rapidly in response to a
voluntary temporary increase in the pressure inside the subject's chest. 41 ,42 During this manoeu-
1108
Fall Joint Computer Conference, 1968
0'11-7-67
P.S. 19- 11 - 67
1°O1~
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IItREASED IIITRATIORACIC
PRESSURE
\ \\ \
sec s
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-.
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ioU. 28 - 10 - 66
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FIGURE 7-The effect on blood pressure and heart rate of a
voluntary temporary. increase in the pressure within the chest
100· ........
llil
't "
.'!'
sec s
'tll"'I"'"
MOVEMENT OF SUUJFCT
J.S.
sec s
rJm
H:OO
[j\~.~.I\'--
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FIGURE 6-Varying blood pressure waveforms
IIITERFERENCE \¥ I TH
CATHETER
J.S.
vre, even in normal subjects, there may occur
pulse pressure variations between successive heart
beats of up to 20% and heart rate variations of up
to 45 %, while the mean pressure may vary by up
to approximately 80% 'Of its original value depending on how hard the subject "blows." Similar
but less marked changes in the wave shape also
occur with changes of posture and may be compounded by the presence of disease. A further difficulty is the frequent presence of noise
(Figure 8") which has been interpreted here in
a very wide sense. An example of a tremor in the
patient, c'Oughing, movement, interference with
the catheter and ·an abnormal heart rhythm are
shown, all of these events being common in clinical situations. It will be apparent that the frequency and amplitude of these events will usually
distinguish them from a normal recording.
~
Programme for analysis of individual
waveforms
Detection of the start of contraction of the heart
(systole) has been found possible with a method
based on the speed and duration of the rise of
pressure during this period-probably the most
I~~
100 ['
mm Hg
o
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ABIIORIoiAl HEART
RYTHMIl
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'I
100~
,. Hg [
o
's e c s
.INTERFERENCE WITH
CATHETER
sec s
~
n
E 1·'0 R
FIGURE 8-Noise in blood pressure recordings
constant feature of the blood pressure waveform.
The computer is programmed to recognize this
event by searching for a number of monotonically
increasing sample values, the number chosen depending on the sampling rate being used. The
diastolic pressure is then taken as the immediately
preceding minimum and the systolic pressure as
the highest subsequent maximum occurring within
a specified time. If this time is properly chosen
the dicrotic notch, the "notch" seen during the
downstroke of the wave in a number of the illustrations in Figures 6 and 7, will be ignored. Once
systolic and diastolic. pressures have been determined it is a simple matter to calculate the
mean and pulse pressures and heart rate. Constraints are built into the programme to detect
Applications of Digital Computers to Long Term Measurement 'Of BI'Ood Pressure
high frequency noise and 'Off-scale values, and
limits are set f'Or the maximum acceptable percentage variati'On between successive amplitudes
clnd rates. When an unacceptable value is f'Ound
the programme will either stop 'Or register a fault
c'Ount depending on which choice the user has
made in a pr'Ogramme "'Option." Other features
'Of the programme are an aut'Omatic calibrati'On
search, an initial scan to check that the signal
c'Onf'Orms t'O the user parameters inserted, simple
5 point sm'Oothing t'O remove high frequency n'Oise,
and 'Opti'Ons f'Or the type 'Of 'Output and the duration
'Of analysis.
The set of user parameters in the present version 'Of this programme is indicated in Table I.
The programme has been written in F'Ortran and
als'O in machine code t'O increase its speed 'Of 'OPerati'On. It will reliably accept samples at a rate
'Of 600 per second t'O pr'Oduce an analysis 'Of the
derivatives indicated in Figure 4 with an accuracy
within 2 %, enabling the speed of replay 'Of the
tape recorded signals to be increased by a fact'Or
'Of 16. VVhen the tape speed is increased t'O 30
times the 'Original and sampling rate is increased
t'O a thousand per sec'Ond, which is the highest of
which the available hardware is capable, the accuracy of analysis decreases by a further 1 t'O
2.5 %, depending on heart rate. It will be apparent
that the am'Ount of data will exceed available c'Ore
store during analysis 'Of I'Ong rec'Ordings since 'One
track 'Of a 16 inch sP'O'OI can accept a c'Ontinu'Ous
20 hr rec'Ording at a speed 'Of 1% inches per
sec'Ond. The pr'Ogramme is theref'Ore designed t'O
automatically dump data 'On the disc st'Ore after
every 320 heart beats and then return to the analysis. Inc'Oming data is I'Ost during this peri'Od.
TABLE I-User parameters for blood pressure analysiR
prog;ramme
1.
2.
3.
4.
Sampling rate of Analogue - to - Digital Converter.
Values of calibration signals (in mm fig.).
Number of CYcles, or period of time, to be analyseO.
Permissible variation in . a) amplitude·
b) heart rate between successive cycles.
5. Number of monotonically increasing points required to indicate systole.
6. Fal~ in ~mpli~ude after systolic point before beginning search for
diastolic pomt
At the end 'Of the entire analysis further pr'Ogrammes are instituted f'Or averaging set periods
1109
'Of the data and determining auto- and crossc'Ovariances. Depending 'On the latter findings and
'On the nature and durati'On of the initial rec'Ording
'One or m'Ore selected derivatives are 'Output 'On
punched tape and 'Occasi'Onally'On cards f'Or cumulative sum 'Or other subsequent· analysis. F'Or certain tests an example 'Of which is given later, a
"marker" signal is als'O rec'Orded 'On the tape during the initial recording. Two types 'Of marker
have been empl'Oyed, viz., a DC signal on an adjacent (unused) track which is then sampled
alternately with the bl'O'Od pressure signal during
pr'Ocessing, and an AC signal 'Of fixed amplitude
and durati'On, superimp'Osed 'On the data track itself. The latter meth'Od has been f'Ound m'Ore efficient f'Or m'Ost purposes and the marker signal is
detected by a separate I'O'OP in the pr'Ogramme. A
similar meth'Od is used t'O indicate the end 'Of a
rec'Ord.
Cumulative sum analysis
The beat-to-beat values derived fr'Om the f'Oreg'Oing bl'O'Od pressure analysis c'Onstitutes in statistical terms a time series 'Of n'Onstationary data
in which the serial values are highly dependent
and in which b'Oth the mean and r'Oot mean square
.vary with time. 40 If the degree 'Of aut'O-c'Ovariance
is kn'Own the initial derived series can be sampled
at sufficiently infrequent intervals t'O c'Onvert it
int'O a time series 'Of independent samples. Present
experience indicates that the degree 'Of aut'O-correlati'On in the data varies c'Onsiderably at different
times in the 'One patient, and between patients.
F'Or the present illustrati'On (Figure 10), serial
half-h'Our-average values 'Of heart rate, derived
from a fifteen-day c'Ontinu'Ous blo'Od pressure recording have been used. The method of time
series analysis applied has been devel'Oped f'Or· an'Other applicati'On by W'Oodward and G'Oldsmith,4:i
and is illustrated in bl'Ock f'Orm in Figure 9. Its
purpose is t'O detect changes in the average level
between groups of data in a time series and t'O
determine the P'Oint 'Of 'Onset of such ~hanges. The
pr'Ogramme causes the c'Omputer t'O read in a time
series, t'O calculate the cumulative sums 'Of the
series using the grand mean as a reference value,
and t'O P'Oint out the occurrence of significant
changes 'Of sl'Ope in the cumulative sum chart.
These changes can be determined at different
probability levels, and the standard deviations of
significantly different stages in the series are
calculated. The. output includes a graph 'Of the
1110
Fall Joint Computer Conference, 1.968
CHAPTER O.
INPUT
RAW
-DATA
DETECT AND
REPLACE
FREAKS
PRINT TABLE OF
TIME SERIES &
THEIR CUMULATIVE
SUMS
CHAPTER 1.
SELECT SIGNIFICANT
CORNERS IN
CUMULATIVE SUM
CHART IN FORWARD
DIRECTION
PRINT TABLE OF
SIGNIFICANTLY
DIFFERENT STAGES
IN SERIES
CHAPTER 2.
CALCULATE WITHIN
STAGE MEANS &
WITHIN STAGE S.D.
SCALE AND PLOT GRAPH ON SAME AXES
OF ORIGINAL TIME SERIES, CUMULATIVE
SUMS, MANHATTEN DIAGRAM
FIGURE 9-0utline of programme for cumulative sum analysie
original data, its cumulative sum or "cusum," and
a "Manhatten" diagram, a term used to describe
the graph of significantly different stages in the
series.
It is obvious from Figure 10 that the initial
series (a) is highly irregular and that trends of
variation in the mean level are n'Ot very obvious.
The cusum chart (b) however, gives a very clear
indication of the overall trend, and visual inspection confirms the presence of a pattern in the
original data which could easily have been overlooked. The Manhatten diagram (c) has condensed the scattered original data into a relatively
small number 'Of groups whose difference from
their neighbors is significant, in this case at the
1 % level. The within-group standard deviations,
although available from the analysis, have not
been included in this illustration. Differences produced by treatment of the patient with two
anaesthetic agents, nitrous oxide and halothane,
are clearly shown in both the cusum and Manhattan plots, the mean having decreased SIgnificantly. This method has ·also been used to test
'Objectively the effects of various other treatments
(to be published).
A further important application is shown in
Figure 11, where an assessment has been made of
the variability of the heart rate in the same patient
over the same period. The difference between the
highest and lowest values of instantaneous heart
rate (excluding "freaks" produced by an abnormal
rhythm) has been measured for each successive
half hour period, and used as a prImary measure
of variability. These figures have then been proc-
FIGURE lo-Cumulative sum analysis of half-hourly-mean
heart rates during a IO-day period in a patient with tetanus
(see text)
FIGURE ll-Cumulative sum analysis of the variability of
heart rates during a IO-day period in a patient with tetanus
(see text)
Applications of Digital Computers to Long Term Measurement of Blood Pressure
1111
essed in a fashion identical to that described above.
The general comments already made on the type
of output resulting from this analysis again hold .
true, and it is also clear that the changes in variability detected by this method do not closely·
parallel the changes in the average heart rate,
although treatment with an anaesthetic agent has
produced a clear decrease in the variability.
DISCUSSION
Blood pressure and heart rate are usually measured and recorded by a nurse. She is relatively
cheap, easily understood, replaceable, reliable and
compact. An automatic monitoring system must
offer significant advantages over her to justify
the increased capital cost and increased complexity. There is little doubt that most automated systems are indeed superior but there is equally little
doubt that most currently available systems. are
much more effective in producing large volumes
of unprocessed data than in efficiently compressing
results-they tend to act rather as a team of
nurses taking measurements more frequently. The
presence of large volumes of potentially useful but
unprocessed data in intensive care and research
units is a growing problem, and blood pressure
records of this type are in fact largely unprocessable, .due to the time required for manual analy. sis. For instance, this may require up to 5 - 6
weeks for analysis of a continuous record lasting
" 7 - 10 days, and even after this time the analysis is
limited. The need for computing is very real and
will grow with time.
Reference has already been made to previous
applications of digital computers to these problems. The present tendency is to make automatic
comprehensive measurements and thereafter to
compress the data simply by averaging over varying periods of time. Unfortunately, this is not
a.Iways a particularly sensitive method of compressing the data without losing its information·
content. The point is illustrated in Figure 12,
where five sections of a blood pressure record
taken from the same patient at different stages
of a disease process are shown. The duration of
each of the traces is about 25 minutes, and a calibration signal is shown for each record. On the
. right hand side an approximate mean level is
written, and the highest and lowest pressure during the period is indicated by a mark. It is immediately apparent to the eye that in the upper
FIGURE 12-Blood pressure recordings taken on a pen recorder
with a slow time base (see text)
record, there is great lability of blood pressure,
while this decreases in the lower records. Neither
the mean pressure however, nor the blood pressure
range adequately reflect the various stages between a very labile and a very stable pressure, although these differences are very important in describing and interpreting changes brought about
by the disease process. 33 ,44 The method of cumulative sum analysis described appears to be a more
sensitive method for automatically and objectively
describing and assessing such results and also approximates to what one normally attempts to estimate by eye. The in-built application 'Of statistical
methods of testing the significance of changes pro-
1112 Fall Joint Computer Conference, 1968
vides one means of assessing treatments which is
free from observer bias and this may well prove
to be one of the most important applications, as
well as being a critical test of the method. Such
assessments must at present be made with caution
since a comprehensive analysis of the auto-correlation in such biological parameters as heart
rate and blood pressure is not yet available.
It is to some extent a disadvantage of this
method that the analysis is necessarily retrospective, since prior knowledge of the grand mean and
overall standard deviation is required to determine
the cusums. The analysis is however, rapid, and
may prove convenient for many units which lack
on-line computing facilities. It may also prove
possible to develop a method based on the use of
provisional estimates of the mean and variance or,
in time, to define normal limits of these derivatives.
The methods described for blood pressure analysis should have important applications to the study
of other physiological phenomena, the principal
differences for many applications being that a
lower sampling rate is required (Table II). The
variables shown in the table are all very commonly monitored in clinical situations and in research and the important frequencies and derivatives are shown. Comments made above for the
near impossibility of measuring the variability
and quantitating trends of blood pressure with
standard methods may be made again for some
of these functions. Harmonics of the basic frequencies do not at present appear to require analysis for these signals, so that the frequencies to be
. analyzed are much lower than with blood pressure
recordings. In addition, it is only the rate or the
mean level which needs to be derived in most cases.
The similarity lies in the fact that, each function
being a time-series in which the degree of autocorrelation is high, they are statistically similar,
and are all probably suitable for analysis and
presentation by similar techniques, with the addition of cross-correlation analysis. The table is by
no means exhaustive, and measurements cou 1,'
easily be extended to include the study of bladdc'
and alimentary tract pressures and motility, some
aspects of locomotor activity, and probably other
body functions as well.
Research is also required to determine which
primary derivatives of the blood pressure wave
form have physiological significance and therefore
need processing. The mean pressure, mean square
TABLE II-Frequencies and sampling rates for physiological
variables suitable for study by techniques similar to those for
blood pressure analysis
APPROXIMATE SAMPLING RATES REQUIRED FOR DIGITAL COMPUTER
ANALYSIS OF COMMON PHYSIOLOGICAL SIGNALS
Physiological
Signal
Arterial Blood
Pressure
Frequence
rangel min.
in adults.
Derivatives
usually
required
45 - 200
I
I
Central Venous
Pressure
Heart Rate
( from instantaneous ratemeter )
Systolic Pressure
Diastolic Pressu re
(Mean Pressure)
( Pulse Pressure)
(Heart Rate )
Approximate
sampling ratel sec
required for
computer analysis
in real time
120
I
I
45 - 200
Mean Pressure
10
45 - 200
Heart Rate
Respiration
8 - 60
Respiration Rate
10
Temperature
0
(slowly varying
DC level)
Temperature
1
10 for instantaneous rate
1 for average rate
pressure, and heart rate may provide as much information alone as they do in combination with
systolic, diastolic and pulse pressures. The mean
square pressure in particular is likely to be a
powerful derivative, though its derivation has
not previously been proposed. For certain applirations it could also prove more suitable to derive
such primary derivates with analogue techniques.
Both in these research applications and in clinical
practice cumulative sum techniques appear to have
important applications. Above all the necessity
for arithmetic processing of records must be affirmed. It is only in the critical analysis of a record that its worth or otherwise becomes apparent,
and a great deal of information is likely to be lost
if complete reliance is placed on simple visual in
spection.
ACKNOWLEDGMENTS
I am grateful to Dr. D. Clarke and Mrs. H. Somner for substantial help with programming, Dr.
A. Barr for advice on statistics, Dr. J. M. K.
Spalding and Miss R. Williams for other support,
and the Oxford University Systems Engineeri~g
Group for the use of their facilities. The investigations were supported by grants from the National Fund for Research into Crippling Diseases,
the N uffield Trust and the Well come Trust.
The programme for cumulative sum analysis
has been kindly made available by Dr. P. L. Gold~mith, M.A., D.I.C. of Imperial Chemical Industries Limited.
Applications of Digital Computers to Long Term Measurement of Blood Pressure
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Procedures in measurement of blood preS81.tre: a historical note
Practitioner 184 2431960
2 WASPENCER CVALLBONA
Application of computers in clinical practice
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Simple and accurate form of sphygmomanometer or arterial
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Brit med J 2 904 1897
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Automatic device for periodically determining and recording both
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Indirect sphygmomanometry physical and physiologic analysis
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E A PARTEN OPE ED FREIS
. Clinical and investigative application of a new instrument jor
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Blood pressure follower for continuous blood pressure recording
inman
J Physiol London 130 37P 1955
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An automatic blood pressure recording machine
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M odel16 atuomatic blood pressure measuring instrument
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1959
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Ein apparat zur Jortlaufenden unblutigen registrierung von
puls and blutdruck
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13 R WWARE ARKAHN
A utomatic indirect blood pressure determination in flight
J Appl Physiol18 210 1963
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A digital readout technique for aerospace biomedical monitoring
Am J Med Electron 2 152 1963
15 R JONN ARD chairman
Symposium on patient monitoring. 15th annual conference on
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Pennsylvania 1963
16 L A GEDDES H E HOFF C VALLBONA
G HARRISON W A SPENCER J CARRZONERI
Numerical indication oj indirect systolic blood pressure heart rate
and respiratory rate
Anesthesiology 25 8611964
17 L A GEDDES H E HOFF W A SPENCER
C VALLBONA
Acquisition of physiological data at the bedside: a progress report
Ann NY Acad Sci 11510911964
1113
18 B L STEINBERG S B LONDON
A utomated blood pressure monitoring during surgical anaesthesia
Anaesthesiology 27 68611966
19 WWHOLLAND SHUMERFELT
Measurement oj blood pressure: comparison of intra-arterial and
cuff values
Brit med J 21241-1964
20 F H VAN BERGEN D S WEATHERHEAD
A E .TRELOAR A B DOBKIN J J BUCKLEY
Comparison oj indirect and direct methods of measuring artierial
blood pressure
Circulation 104811954
21 L N ROBERTS J R SMILEY G W MANNING
A comparison of direct and indirect blood pressure determination
Circulation 8 2321953
22 JMSTEELE
Measurements of arterial pressure in man
J Mt Sinai Hosp 810491941-2
23 W F HAMILTON R A WOODBURY H J HARPER JR
Physiologic relationships between intra-thoracic, intraspinal and
artierial pressure readings
J Am Med Ass 106 853 1936
24 R E JENSEN H SHUBIN P F MEAGHER M H WElL
On-line computer monitoring of the seriously ill patient
Med BioI Engin 4 265 1966
25 H SHUBIN M H WElL
Efficient monitoring with a digital computer oj cardiovascular
function in seriously ill patients
Ann Intern Med 65 4531966
26 M H WElL H SHUBIN W RAND
Experience with a digital computer jor study and improved
management of the critically ill
JAMA 198 10111966
27 SHTAYLOR HRMACDONALD
RPSAPRU
MCROBINSON
Computers in cardiovascular investigation
Brit Heart J 29 352 1967
28 H SHUBIN M H WElL
M A ROCKWELL JR
A utomated measurement of arterial pressure in patients by use
of a digital computer
Med BioI Engin 5 3611967
29 S I SELDINGER
Catheter replacement of the needle in percutaneous arteriography,
a new technique
Acta Radiol39 3681953
30 FDSTOTT
Medium term direct blood pressure measurement
Bio-medical Engineering 14571966a
31 FDSTOTT
Methods of assessment of variations of blood pressure
Bio-medical Engineering 1 544 1966b
S2 A L MACMILLAN F D STOTT
Continuous intra-arterial blood preS8ure measurement
Bio-medical Engineering 1 20 1968
33 J L CORBETT
Long-term measurements of intra-arterial pressure in man
In preparation
34 A T HANSEN E WARBURG
Acta Physiol Scand 193061949
35· A T HANSEN
Pressure measurement in the human organism
Teknisk Forlag Copenhagen 1949
36 DLFRY FWNOBLE AJMALLOS
An evaluation of modern pressu~e recording systems
1114 Fall Joint Computer Conference, 1968
...
Circulat Res 5 401957
37 HWSHIRER
41 AMVALSALVA
De aure humana tractatus
Blood pressure measuring methods
IRE Trans BME 116 1962
38 D J PATEL J C GREENFIELD W G AUSTEN
MORROW D L FRY
J Appl Physiol20 4591965
39 R B BLACKMAN J W TURKEY
The measurement of power spectra
Dover Publications Inc New York 1959
40 J S BENDAT A G PIERSOL
Measurement and analysis of rancom data
John Wiley & Sons Inc N ew York 1966
A C
G vande Water Utrecht 1707
42 G DE J LEE M B MATTHEWS
E P SHARPEY-SCHAFER
Brit Heart J 16 3111954
43 R H WOODWARD P L GOLDSMITH
Cumulative sum techniques
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44 JLCORBETT CPRYS-ROBERTS JHKERR
Cardiovascular disturbances in seven tetanus due to overactivity of the sympathetic nervous system.
Submitted for publicatiou
Some conclusions on the use of adaptive
lineardecision functions
by E. R. IDE, C. E. KIESSLING and
C. J. TUNIS
International Busine88 Machines Corporation
Endicott, N.Y.
INTRODUCTION
3)
Any pattern recognition system can be considered
to have three sections:
1)
2)
3)
The coding problem
a transducer section,
a measurement secti'On, and
a decision section.
The first two sections transform each pattern to
be recognized into one point in a multidimensional
space. The axes of this space are .the measurements or characteristics of the pattern. The decision section must assign regions of the measurement space to particular classes of pattern. One
common and convenient decision surface is the
linear boundary or hyperplane; much work has
been done ·with ". adaptively derived" hyperplanes. 1 ,2 Algorithmic procedures have been de,..
veloped for positioning the linear decision boundaries in the measurements space on the basis of
statistically meaningful samples of each pattern
class.3
Theoretical studies of the classification capabilityof linear decision b'Oundaries can be performed
by assuming a particular statistical distribution
of the measurements in the measurement space
for each class. For certain assumed distributions
in the two-class case, it has been shown that a
linear decisi'On boundary is the optimum one. 4 Of
course, this boundary would not be the optimum
one for many real recognition problems. However,
the linear boundary has been the subject of many
experimental investigations because it is:
1)
2)
convergent adaptive algorithms 5 exist for
this boundary.
optimum in certain idealized cases,
a convenient boundary to implement in
hardware, and
1117
In order to have a pattern classifier we must
..
'
posItIon a sufficient number of linear boundaries
in the measurement space; this separates the
measurements arising from one pattern class from
the measurements arising from all other pattern
classes.
. There are a variety of ways of positioning linear
boundaries. Figure 1 shows four pattern classes
(in a two-dimensional measurement space) separated by only two planes. (The contour in the
figure can be taken to mean that 990/0 of all patterns of this class will give rise to measurements
that fall within this boundary.) N'Ote that these
two planes, given the dichotomies they are assigned (i.e., plane "A" must separate classes 1 and
2 from 3 and 4), can indeed be positioned iIi such
a way as to perform the separations. If, on the
other hand, we had intended to use a single plane
to separate classes 1 and 3 from 2 and 4, the separation would not have been possible. This situation, i.e., nonlinear separability, is referred to as
the coding assignment problem and is described
in a previous paper by the authors. 6
Figure 2 shows another way oi separating each
class in the measurement space.· This particular
method uses a significantly greater number of
planes. Here, one plane separates each class from
one 'Other class. This will be referred to as the
class-pair plane coding assignment. This should
be the best linear-boundary classifier since each
plane only separates one pair of patterns. Note
1118
Fall Joint C'Omputer Conference, 1968
,---:--~------.
CODING ASSIGNMENT
Notes: • Planes are designated by A and B
• Arrow. designate "on" side of the planes
FIGURE I-Coded boundaries
-
---,------,
CODING ASSIGNMENT
Notes: • Planes are designated by A. B. C. D, E. and F
Cloll Plane
A B
I
11
2
I 0
~-
..
oI
00
that the regions assigned to each class are determined by different numbers of planes. For example class 3 is determined by three planes while
class 4 only needs one plane (planes E and Care
redundant with respect to class 4). The disadvantage of this coding assignment is that a large
number of planes is required. For example, if
there are n classes then n (n- 1) /2 planes are
required.
Another popular method of separating classes
with linear boundaries is shown in Figure 3. Here
we have assigned one plane to separate each class
from all others. This is sometimes referred to as
the l-out-'Of-n code, because there are as many
planes as classes (n) and only one plane will be
"on" for one pattern presentation. (By "on" we
refer to the state of the threshold circuit corresponding to the plane; a cUtssifiable measurement
will be in those regions of the measure"ment space
delineated by the positive side of one plane and
the negative side of all other planes.) The problem here, of course, is that it may not be possible
to separate one class from all others by means 'Of
a single plane.
A variant of the method shown in Figure 3,
• Arrows designate .. on" side of the planes
CIOSl
• Numbers in parentheses designate class
separation (e. g. • A (1.2) means Plane A
separatei class 1 &om class 2)
1
2
..3
Plane
ABCDEF
1 I I x x x
oxx I Ix
xOxOxl
xxOx.OO
FIGURE 2-Class-pair boundaries
called the matched filter app'roach, uses as many
planes ( or linear functionals) as the previous
case (i.e., only n) but the actual decision boundaries are the bisectors of the vari'Ous pairs of
planes 2 (see dotted lines in Figure 3). The
threshold circuit network corresponding to this
classifier is organized to allow only one plane to
be "on" at anyone time.
The purp'Ose of our experiment was to compare
the classification performance of all class-pair
planes (in one particular problem) to the classification performance of the matched filter ·approach. In addition, we tried to develop a classifier that would provide the performance 'Of the
class-pair classifier but would have fewer planes.
The method started with the class-pair classifier
and attempted to eliminate geometrically redundant planes and also to utilize other dichotomies
performed by the class-pair boundaries. We show
that the performance 'Of the matched filter classifier is surprisingly close to the performance obtained by using all class-pair planes. Our method
of eliminating some of the class-pair planes quick-
Conclusions on Use of Adaptive Linear Decision Functions
,,
,
\
,
\
,
\
\
\
,
\
\
.A·-~~K~~fL-~:;;:;;...;J-.
CODING ASSIGNMENT
Notes: • Planes are designated by A. 8. C and 0
I
• Arrows designate" on" side of the planes
Closs
Plone
ABC 0
1
2
100 0
0100
001 0
000 1
3
4
FIGURE 3-Matched filter boundaries
ly brought performance levels that were inferior
to those of the "l-out-'Of-n" code, even though we
were using more decision boundaries.
The classification problem used for this set of
experiments was the recognition of a small number of spoken words. In our experiment 15 words
or classes were handled. The measurements were
obtained by a spectrum analysis of each word; this
provided a binary representation of the energy
peaks in the frequency domain as a function of
time. The speech analyzer and some initial recognition experiments on this data set were reported
in an IBM Journal article. 7 The data from Reference 7 were used in this experiment.
Our data base is divided into two parts:
1)
2)
one set of sample utterances (i.e., the
analysis sample) ; used for adapting or positioning the hyperplanes in the measurement space and
an equal size sample (i.e., the test sample) ;
used to test the performance of the classifying hyperplanes
1119
It is the performance of the hyperplanes on this
hitherto unseen sample that is reported as the
recognition performance of the system.
The initial step of the experiment was to adaptively position all class-pair hyperplanes on the
basis of the training sample. Since the number
of classes was 15,we positioned 105 hyperplaneseach hyperplane having the assignment of separating one class of spoken words from one other
class. After the class-pair hyperplanes were positioned, we did a recognition run on this same
training set. We were not concerned with how
well the class-pair plane separated the two classes
for which it was designed (it generally does very
well, since this is the training set), but rather we
were concerned with what 'Other classes of pattern
each class-pair plane separated.- Recognize that
here the word "separator" means de,gree of separation; for example, a particular class-pair hyperplane may correctly separate 90 % of the members of class 7 from those of class 9 and only 75%
of members of class 3 from those of class 5. Thus,
we compiled a number of tables indicating not only
which classes each class-pair plane separates but
also to what level, i.e., 95 % separation, 90% separation, etc.
The second step in our experiment was to choose
a subset of all class-pair hyperplanes that still
separated all patterns, 'One from the other. From
the table that shows what class each class-pair
planes separates to a 95 % level, we had to select
as many as 43 hyperplanes to partition the space.
Each pattern class was described by its position
with respect to the 43 planes. This set of 43 binary
symbols ("I" denoting that the region is the "on"
side of a plane, "0" denoting the "off" side) constituted a code word. Looking at the table that
shows what classes each class-pair plane separates
to a 90 % confidence level, we had to select only 23
planes that would separate all the classes. We
then trained the chosen subset of the class-pair
planes on the training sample, taking into account
the other classes of pattern that we wanted each
plane to separate. Once these new planes were
chosen and adapted, we determined their performance on the test sample. By using the test sample,
we also determined the performance of the classifiers consisting of all class-pair planes, the l-outof-n, and the matched filter. This performance
data is tabulated in Table 1.
Table 1 shows us that the class-pair classifier
was the best linear classifier. The results are sur-
1120 Fall Joint Computer Conference, 1968
TABLE I -Coding of adaptive linear classifiers
Code
No. of
Hyperplanes
Rejects (R)
(%)
Substitutions (S)
(%)
viS
105
4.8
0.4
1.4
Reduced Class Pair
43
5.1
1.3
2.6
Closs Pair
Reduced Class Pair
25
6.2
1.1
2.6
Reduced Class Pair
22
5.8
1.2
2.6
l-out-of-n (Matched Filter)
15
4.1
1.4
2.4
l-out-of-n (Thresh)
15
11.0
0.3
1.8
Note:
This table wal prepared by sampling 1050 warda.
prising because the l-out-of-n coded classifier, requiring only 15 hyperplanes, is exceedingly close
to the performance of the class-pair classifier.
Also, we observe the failure of our method of
eliminating some of the class-pair planes in arriving at a c'Ode that is only nearly as good as the
simple l-out-of-n code. We cannot claim that
every recognition pr'Oblem can be handled so well
by this obvious coding assignment, but we have
shown an example here of a practical pattern recogniti'On problem where this was indeed the case.
The effect of weight quantization
The implementation of a linear decision function
requires that there be a variable weighting of each
of the binary inputs or measurements. The question we seek to answer in this section is, "How
does the categorization performance of the decision function vary with the number of discrete
weight levels available?" This, of course, has
tremendous implications. to the ease 'Of implementing the linear decision functi'On in hardware.
If a resistor array is used, then the tolerance on
each resistor is eased. If the linear decisi'On function ~is implemented by storing, the weights in a
digital mem'Ory and simulating the summati'On
effect 'Of the network, then the am'Ount of st'Orage
required is affected significantly. We thus describe
an experiment where adaptivelyderived linear
decision boundaries are 'Obtained and then the
effect 'Of different available weight quantization
levels on the rec'Ogniti'On performance of the netw'Ork is determined.
The applicati'On considered here was the rec'Ognition of the ten numeric characters and one
"special" class (period, c'Omma, d'Ollar sign, minus
sign) from approximately forty typewritten fonts.
The transducer and pre-pr'Ocessor were similar
t'O those described in Liu and Kamentsky. 8 Characters were scanned by a flying SP'Ot CRT 'Optical
scanner; a raster image was produced in a shifting
register. Position-invariant measurements were
made on a character as it passed thr'Ough the shift
register to produce a 100-bit (approximate) measurement vector.
This 100-bit measurement was the input to the
netw'Ork of linear functionals expl'Ored here. There
are eleven linear functi'Onals, one assigned to each
class of character (in the "matched filter" assignment of the previous part). The total sample obtained for this experiment consisted of 55,000
characters. Approximately one-half of these were
-used for the adaptation of the weights; the other
half were used as a test sample.
We were interested in obtaining the weights by
first simulating the adaptive pr'Ocess on the training sample on a digital c'Omputer and then storing
the weights in our recognition machine. The recognition portion of the machine was a special purpose digital computer which "emulates" the set
'Of linearfuncti'Onals. Thus, the number 'Of bits
required to st'Ore the set 'Of weights was 'Of interest.
After adaption 'On the training sample, the
weights were all within the range ±256; thus, we
require 9 bits t'O st'Ore each weight. Table 2 shows
the rec'Ogniti'On perf'Ormance 'On a test sample
when these finely quantized weights were used. It
als'O sh'OWS the deteri'Oration in the substitution
and reject rates as the levels 'Of quantizati'On in
the weights were successively reduced. Als'O
sh'Own is the square r'Oot of the pr'Oduct 'Of the
substituti'On and reject rates (sometimes used as
a Figure 'Of Merit* f'Or a rec'Ogniti'On system).
This is used because there is a "trade-'Off" between
these tW'O rates for any rec'Ogniti'On system, but
their pr'Oduct is approximately constant.. N'Ote
that when using even three-bits per weight (which
corresP'Onds t'O 'Only eight distinct weight levels),
the rec'Ognition rate has n'Ot yet degraded by a
fact'Or 'Of tW'O, while the substituti'On rate has remained the same. This behavi'Or is a complex functi'On of the nature 'Of the adaptive pr'Ocedure, the
shape 'Of the decisi'On boundary, and the distribution 'Of characters in the measurement space. Withassumed statistical distributi'Ons, it would be possible to "c'Ompute" this functional relationship,
but it is interesting t'O observe it in this "realvlOrld" application.
*The larger this figure, however, the less the merit of the rec;..
ognition system.
Conclusions on Use of Adaptive Linear Decision Functions
Thus, if this decision procedure were implemented by storing the individual weights in a digital machine, only 3300 bits** of storage would
produce a quite respectable classifier. This storage
requirement is about 1/20 of. that required by a
familiar method 9 (that of storing one, or more,
ternary references for each class and computing
the "distance" of the unkn'Own fr'Om the stored
leferences), but achieves a comparable recognition rate. ,This advantage of linear decision functions has not, to the auth'Ors' knowledge, been
noted in the literature.
Unsupervised learning
The literature 'Of pattern rec'Ognition, signal detecti'On, adaptive systems, and self-organizing systems has treated the subject 'Of unsupervised learning (learning without a teacher) fr'Om both the
theoretical and empirical p'Oints 'Of view. 10
We now summarize an experimental investigation 'Of an unsupervised adaptive pattern recognition algorithm previously reported elsewhere.ll
Our adaptive linear classifier undergoes an early
training period in which it is presented with a
number of labeled samples f'Ollowed by a later
peri'Od (which may be indefinitely l'Ong) during
which it c'Ontinues to adapt its parameters based
'On its own decisions.
An unsupervised system can begin with parameters generated from a small labeled sample, and
then can use a large sample of unlabeled patterns
to design accurate class boundaries. In a typewritten character problem, N agy12 used starting
parameters generated from nine type fonts. His
unsupervised system (quite different fr'Om that
used here) designed decision criteria f'Or each 'Of
twelve other fonts fr'Om a five-hundred-character
sample 'Of each. Using no labeled patterns from
these twelve fonts, he achieved "essentially singlefont, single-machine performance" on each.
It is intended that, during normal use 'Of a rec'Ognition system, unsupervised adapti'On will take
place and will allow the system to f'Oll'Ow gradual
changes in the class distributions due to data
changes or hardware degradation. Such "tracking"
was attempted by Koford and Mays13 with a supervised algorithm which, without data repeating
(without using a given input more than once),
will track changing statistics and remain close to
**Three bits for each weight; 100 weights/functional; 11 linear
functionals, 1 functional assigned to each class.
1121
optimal, if the. changes are not too rapid. Cooper
and Cooper14 suggested an unsupervised algorithm for tracking time-variant statistics in a very
special case that does not generalize.
T he supervised algorithm
We repeat the supervised algorithm: We construct a vector Wi and a constant t i for each
class in the problem, such that each pattern vector
X is assigned to a class as foll'Ows:
If Wi·X
+ ti > WrX + tj +
E
f'Or all j
¢
i, (1)
the pattern X is assigned t'O the class i. This type
of Glassifier is sometimes referred t'O as a trainable matched filter.
If there is no i such that Equation (1) is true,
the pattern is assigned to no class; it is rejected.
For this reason, E h is often called the reject
thresh'Old.
We 'Obtain the set 'Of vect'Ors and c'Onstants by
presenting iteratively to the netw'Ork a sequence
of sample measurements fr'Om each class t'O be
identified, where the class 'Of each sample is
known. Our sample must be statistically representative 'Of the individual classes.
The algorithm has advantages noted elsewhere.
It is general in applicati'On and is relatively easy
to implement in hardware. It adjusts the weights
(W i and t) after each pattern, eliminating the
need to save patterns 'Or sums of patterns in s'Ome
sort of storage. In previ'Ous experimental w'Ork
wi th both sp'Oken word and optically sensed typewritten patterns (d'One by one of the auth'Ors), it
has displayed somewhat better results than those
of several other current methods.1.5
The unsupervised algorithm
To the advantages menti'Oned above, the unsupervised algorithm adds the benefits of unsupervised adaption: labeling elimination and tracking
ability. It differs from the supervised alg'Orithm
in that the class of X is unknown. Theref'Ore,
the adaption must proceed as if the class assigned
by the decisi'On rule, Equation (1), is in fact the
class of X.
Specifically, the alg'Orithm proceeds in the following way: If the pattern is rejected 'Or str'Ongly
assigned t'O a class, the vectors are not changed.
If the pattern is weakly assigned to a class m,
W m and t m are incremented as though X be-
1122
Fall J'Oint Computer C'Onference, 1968
longed to class m, and the vector 'Of the nearest
'Other class (n) is decremented. The details 'Of the
alg'Orithm are presented in (11).
10 ALPHABET STARTING WEIGHTS
30
-
20
Data
Generalization
The classifier was first trained in the supervised
m'Ode (i.e., on a labeled set) 'Of thirty alphabets.
(An alphabet is defined as a set 'Of single utterances 'Of each w'Ord in the v'Ocabulary.) Then the
perf'Ormance of the classifier (weight vect'Ors)
was tested 'On the identificati'On sample after
each additi'Onal ten alphabets 'Of unsupervised
training. The results, shown in Figure 4, sh'OW
a decrease in the reject rate from 10.5 % t'O 1.6 %
12.-------------------------------------~
11
10
~ 9
I:j
~
8
~ 7
o
~
6
~
5
;::
~:.
E
i 2
SUBSTITUTIONS
,A,
... ,.,1$'
\
" \ ''b-......
-
n • 10
20
8·75
REJECfS
-- ".'''ruT'''"'
Results
30
'""o-_-<)O---4."'o---o()o.--Oo.,,'O-__ ..,. __
«I
50
60
70
II)
90
~--o-_-o-_-<>--oo()o--..()..--o----<)
100 110 120 130 1«1 150 160 170 III) 190 200 210
15
10
/+\
UNSU~RVISED PERFORMANCE DURING TRAINING
(·30
0-
+_ STARTING WEIGHT PERFORMANCE
25
The performance 'Of an adaptive linear classifier
designed (trained) using the unsupervised alg'Orithm just described was extensively tested in tW'O
distinct pattern rec'Ognition pr'Oblems-sP'Oken
w'Ord rec'Ogniti'On (the same data base as in Part
I) and handprinting recogniti'On. The tW'O pr'Oblems clearly had different statistical pr'OP~rties,
alth'Ough they had r'Oughly the same number 'Of
vattern classes. The measurement space of the
sP'Oken word pr'Oblem was 320 dimensi'Onal; that
'Of the handprinting rec'Ogniti'On pr'Oblem was 180
dimensi'Onal.
We shall repeat the detailed results c'Oncerning
the w'Ord recogniti'On data; but with the fact noted
that sUbstantially the same kind 'Of perf'Ormance
was 'ObtaiDed in the 'Other, rather different, applicati'On. This fact tends t'O indicate that the alg'Orithm has general applicability.
i
35-r--------~---~___:-------___,
"fj
+
./
"
\
+
,..
+
/
/\
/
1'/"" :~
/
,,",\ ,~I '>' ,,~ _~~~~ /~
\
,0,
I:+:'
/'
n' 10
20
'~
30
+
/
50
60
70
'+',
~o~ _ ' ,
~-¥,:-P'
_-h,
«I
,//
II)
--0'
'
~~S-.¥-o'
"of
\
_,
"0",,+
90 100 110 120 130 1«1 150 160 170 III) 190 200 210
NUMBER Of ALPHABETS Inl
FIGURE 5-Performance of starting weights and of the unsupervised system during each ten alphabets of training
as the classifier is "trained" 'On additional alphabets. There was als'O a decrease in the substituti'On rate.
Performance during training
H'Owever, the n'Ormal m'Ode 'Of an unsupervised
classifier W'Ould be described by its "perf'Ormance
during training"; i.e., its rec'Ogniti'On rate as it is
adapting itself 'On inc'Oming patterns. To 'Obtain
a rate, we sh'OW the rec'Ogniti'On rate f'Or each successiv~ 10 alphabets (150 w'Ords) as the classifier
is exposed t'O these alphabets. Figure 5 sh'OWS the
reject and substituti'On rates (f'Or each 10 alphabets) as the system is underg'Oing unsupervised
TABLE II-Performance of a set of weights quantized into a
varying number of levels
Weight Size
Rejects (R)
(%)
Substitutions (S)
(%)
v'RS
9-bit weights as
originally generated
0.443
0.111
0.219
6-bit weights
derived from 1
0.426
0.110
0.215
5-bit weights
0.462
0.111
0.226
4"'bit weights
0.523
0.136
0.226
3-bit weights
0.634
0.111
0.265
2-bit weights
("large" reject zone)
4.07
0.154
0.791
2-bit weights
("small" reject zone)
1.06
0.555
0.767
NUMBER Of ALPHABETS Inl
Note:
FIGURE 4-Unsupervised generalization on the ID sample
after each ten alphabets
This table was prepared from approximately 55.000 characters obtained
from a Cl~.T flying-spot scanner; the characters were then preprocessed
to about 100 measurements. Also. 27.930 characters were used for test
sample and 27.830 were used for adaptation of the weights (training
sample).
Conclusions on Use of Adaptive Linear Decision Functions
training. In addition, we show the comparable
recognition performance of the fixed classifier
using the starting weights, i.e., the weights obtained after supervised learning 'On thirty labeled
alphabets. The unsupervised weight classifier
fluctuates much less than the fixed classifier and
generally improves as its experience increases.
Tracking pattern shifts
To test "tracking capability" under more severe
conditions, a systematic and severe change in the
measurement statistics was artificially ~reated.
This change was a right shift by one column of all
the bits in the pattern matrix. We felt that performance of the unsupervised algorithm in tracking such a distortion would be generally indicative of its capability of tracking a variety of
changes in the statistics due to other malfunctions.
A sample of 100 alphabets was used in this experiment. An initial supervised learning was done
on these alphabets in their nominal position. These
initial classifier weights were preserved; their
recognition performance on the patterns of the
subsequently shifted 100 alphabet sample is
shown in column One of Table 3. Each pattern of
the 100 alphabet sample was then shifted right
'One column, and a classifier was trained on them
(1 pass) in the unsupervised mode, using the
previously mentioned supervised weights as the
starting weights. For comparison, a supervised
(labeled) training was also done on the shifted
patterns under the same conditions. Four successive column shifts were performed. For each shift
the performance 'Of the unsupervised and supervised classifier was measured (see columns Two
and Three of Table 3).
TABLE III-Shifting of patterns-Percent correct recognition
(forced decision) of fixed weight, unsupervised, and supervised
tracking classifiers
Shift in
Bits
Weight
Classifier
0
16
32
100.0
92.5
-
-
99.2
99.3
55.0
97.4
99.1
48
28.0
96.2
99.3
64
18.0
93.1
98.9
Unsupervised
Classifier
Supervised Tracking
Classifier
1123
It can be seen (from column One, Table 3) that
after the four shifts, the original weights are indeed useless in a fixed classifier, for their recognition rate is less than 2070. However, the unsupervised classifier has traced the changing data and
is still getting 93 % correct recognition.
This experiment clearly indicates that unsupervised training allows the recognition system to
survive (i.e, continue to perform well), even a
relatively rapid change in measurement statistics.
Such changes may occur for a variety of reasons
such as degradation of hardware or changes in the
data input environment.
SUMMARY
Based on the experimental work reported here
(and other work rep'Orted elsewhere), the authors
conclude that the use of adaptively derived linear
decision boundaries in practical pattern recognition systems deserves serious consideration. It has
been shown to be more than competitive with
other classification methods. 15 We have further
shown here that the .simple, trainable matched
filter represents a powerful coding scheme in the
practical cases investigated here. Undoubtedly,
there are applications where piecewise linear decision boundaries will have t'O be used. 3
Once the linear decision boundaries have been
derived, surprisingly few number of discrete
weight levels have been shown to be usable without
significant sacrifice in performance. This allows
either the digital storage requirements to be relaxed if a special purpose digital processor simulating the effect of the linear functionals is used,
or allows the use of analog implementations with
relaxed tolerance on the stored weights. Hithert'O,
the tolerance requirement has been the main barrier to an economical analog hardware implementation of linear decision functions.
The experiments reported here show that unsupervised learning has potential utility., It has
been demonstrated, in two applications, that a
classifier in the unsupervised mode can follow
changing statistics of' the input pattern set. This
may indeed be the most useful aspect of adaptively derived linear decision boundaries.
ACKNOWLEDGMENT
The authors wish to acknowledge the assistance
of Mitchell P. Marcus.
1124
Fall Joint Computer Conference, 1968
REFERENCES
1 N JNILSSON
Learning machines: Foundations of trainable pattern classifying
systems
New York McGraw-Hill 1965
2 J S GRIFFIN JR J H KING JR C J TUNIS
A pattern-identification device using linear decision functions
In Computer and Information Sciences
J T Tou and R H Wilcox Eds Washington D C Spartan pp
169-1931964
3 R 0 DUDA H FOSSUM
Pattern classification by iteratively determined linear and piecewise linear discriminant junctions
IEEE Transactions on Electronic Computers vol EC-15 pp
220-232 April 1966
4 J S KOFORD G F GRONER
The use of an adaptive threshold element to design a linear
optimal pattern classifier
IEEE Transactions on Information Theory vol 12 No 1 pp
42-50 January 1966
5 N JNILSSON
Op cit Chapters 4 and 5
6 C E KIESSLING C J TUNIS
Linearly separable codes for adaptive threshold networks
IEEE Transactions on Electronic Computers
Vol EC-14 No 6 pp 935-936 December 1965
7 JHKINGJR CJTUNIS
Some experiments in spoken word recognition
IBM Journal of Research and Development January 1966
8 LA KAMENTSKY C N LIU
Computer-automated design of multi/ont print recognition logic
IBM Journal of Research and Development
Vol 7 pp 2-13 January 1963
9 CN LIU GLSHELTON JR
A n experimental investigation of a mixed-font print recognition
system
IEEE Transactions on Electronic Computers vol EC-15 pp
916-925 December 1966
10 J SPRAGI~S
Learning without a teacher
IEEE transactions on information theory
Vol IT-12 No 2 pp 223-230 April 1966
11 ERIDE CJTUNIS
A. n experimental investigation of a nonsupervised adaptive
algorithm
IEEE Transactions on Electronic Computers Dec 1967
12 G NAGY G L SHELTON JR
Self-corrective character recognition system
IBM Yorktown Research Report RC 1475 1965
13 JSKOFORD CHMAYS
Adaption of a linear classifier without data repeating
Record of the 1965 International Space Electronics Symposium November 2-4 1965
14 DB COOPER P W COOPER
N onsupervised adaptive signal detection and pattern recognition
IEEE Transactions on information Theory vol IT-12 No 2 pp
215-222 April 1966
15 R G CASEY Editor
An experimental comparison of several design algorithms used
in pattern recognition
IBM Yorktown Research Report RC 1500 1965
Experiments in the recognition of hand-printed text:
Part I-Character r.ecognition
by JOHN H. MUNSON
StanJord Research Institute
Menlo Park, California
INTRODUCTION AND BACKGROUND
Among the many subject areas in the field of pattern
recognition, the recognition of machine-printed and
hand-printed alphan:umeric characters has perhaps been
the classic example to which people have referred in
exemplifying the field. Interest in character recognitio.n
has long run high; an extensive literature in handprinted character recognition alone dates back to at
least 1955.1- 36
In recent years, the .recognition of machine printing
has become a commercial reality. Following the introduction of the highly controlled E13B magnetic font
by the banking industry, several advances in optical
character recognition (OCR) capability have been
brought to the marketplace. The trend of these advances
is toward the acceptance of broader and less controlled classes of input: from single, stylized fonts to
multi-font capability; from high-quality copy to
ordinary inked-ribbon impressions, and even to multipart carbons of surprisingly poor quality. Still, in
contrast to hand printing, the approaches to OCR have
been able to rely on the lack of gross spatial distortions
in the character images, and to make considerable use
of templates.
Progress in the off-line recognition of hand printing
has been slower. The problem is intrinsically harder
than that of OCR, as reflected in the fact that the
human recognition error rate for isloated, hand-printed
characters is many times higher than for machine
printing. The great spatial variability of hand-printed
characters has led many researchers to explore nontemplate methods for recognition.
Thus, the maj or effort of many researchers has been
the exploration of unique methods of preprocessing, or
feature extraction, applied to the hand-printed char~cter ~mages. Dinneen, 1 in one of the earliest papers,
InvestIgated local averaging and smoothing operations
to improve the quality of the character image. Similar .
operations have appeared as a part of many other
approaches. 4,7 Lewis,16 Uyehara,21 Stern and Shen,23
and Rabinow Electronics 31 have used schemes in which
the sequence of intersections of a slit scan with the
character image, or the equivalent, gave rise to features
for classification. Lewis15 .was one of the relatively few
to emphasize the use of multiple-valued rather than
binary-valued features, an ingredient we have found
important in our own work.
Singer12 and Minneman 30 employed a circular raster,
which can facilitate size normalization and rotation
invariance. Unger,7 Doyle,9 and Glucksman27 have
emphasized features derived from shape attributes
such as lakes, bays, and profiles. The building up of a
character representation from component elements
matched to the image, such as short line segments or
portions of the boundary, has been attempted by
Bomba,4 Grimsdale et al.,6 Kuhl,19 and Spinrad. 26 Correlation techniques have been tried by Highleyman13
and Minneman. 30 Contour-following with a captive
flying-spot scan or its simulated equivalent has appeared
in the work of Greanias et al.,20 Bradshaw,22 and
Clemens. 28 The work of Greanias et al.,20 is especially
significant because it led to the method used in the IBM
1287 character reader.
Other 'workers have placed greater relative emphasis
on classification techniques and on the selection of features from a feature set or pool. Chow16 ,29 has long
worked with statistical classification methods. Bledsoe
and Browning3 and Roberts8 applied adaptive procedures to features obtained from more or less random
connections with the image raster. Uhr and Vosslerll
performed an important pioneering study of a program
that "generates, evaluates, and adjusts" its own
parameters. Not surprisingly, however, the automatically generated features were confined to simple,
local templates.
The recognition of characters printed subject to
1125
1126
Fall Joint Computer Conference, 1968
specific constraints (such as guide markers appearing
in the printing area) has been studied by Dimond,2
Kamentsky,14 and Masterson. I8
It may be said of most of these investigations that
they were in the academic, rather than the practical,
r~alm. In general, the methods were never tested
against a body of real-world data large enough to give
some estimate of their performance in a practical
situation. This probably reflects a common emphasis
on checking out a preprocessing scheme rather than
attacking a particular application problem; it certainly also reflects the labor and equpiment requirements involved in collecting and controlling a significant body of data. An exception to this general statement is the work of Highleyman and Kamentsky in
the early 1960's, in which they used data files numbering
in the thousands of characters. 13 •14 Also, several files
each containing many thousands of characters of
graded quality were gathered in conjunction with the
development of the IBM 1287 character reader and are
currently in use at IBM and in our group. Bakis et al. 35
describe these data, on which they and others at IBM
have performed extensive experiments.
The use of context to improve recognition performance, which figures prominently in oUr own work,
was discussed briefly by Bledsoe and Browning,3 but
otherwise has received scant attention in the past.
Some studies have been carried out under simplifying
assumptions such as M:;trkov dependence in digrams
and trigrams.
Chodrow et al. 31 surveyed hand-printed characterrecognition techniques in 1965 and discussed at some
length the procedures of Clemens,28 Greanias et al.,20
and Rabinow Electronics. The book Pattern Recognition
by Uhr 32 reprints a number of the important source
papers 3.6 •8.11 and contains a well written survey. An early
progress report on the work described herein was given
by Munson. 36
Recently, commercial organizations have announced
the capability to read off-line hand printing. At the
date of this writing (early 1968), one system (the IBM
1287 optical reader) has achieved pilot production
operation. The 1287 reader can read the ten numerals
and five letters. Another system is announced to have
full alphanumeric capability.
A common characteristic of the announced systems
is that they are intended to work with hand printing of
very high quality, produced by coders who have undergone training in the skill of printing for machine
recognition. If individual characters must be recognized
with, say, better than 99.9% accuracy in order to
yield usable document acceptance rates, this type of
training is clearly required. Some experiments that will
he described in the next section show that humans
cannot recognize isolated characters printed by an
untutored population with any rate approaching the
required acc~racy.
.
In our work, we have taken the alternative approach:
Given text from an untutored coder, in which the
individual characters cannot be recognized (by man or
machine) with high accuracy, contextual analysis is
used to reduce the error rate. Every form of text has
its o~n contextual structure, which is utilized by
humans in a complex, largely unconscious process. We
have therefore emphasized the following points in our
research: the establishment of large hand-printed data
files of known ,quality; the choice of a well defined
char~cter alphabet and textual situation (FORTRAN
program texts) as a vehicle for study and the reporting
of results; the use of multiple approaches to preprocessing; context analysis to improve recognition; and
the preservation of non-binary confidence information
between the preprocessor and classifier and between
the classifier and the context analyzer.
In a companion paper,37 Duda and Hart describe the
use of programmed contextual analysis in the recognition of FORTRAN program texts. The present paper
will therefore concern itself only with the problem of
recognizing individual characters.
Problem definition
In a recent paper, the author has argued that there is
an infinity of character-recognition problems, and that
recognition results are meaningless as they are often
reported in the literature, without an adequate description of the problem being tr~ated. 38 Accordingly,
we shall try to describe the two recognition problems
dealt with in this paper thoroughly enough that the
reader can form an intuitive opinion of the difficulty of
the problems.
We must first distinguish between off-line character
recognition from a printed page, and on-line recognition,
in which the characters are generated by a light pen,
RAND tablet, or similar device.24.33.34 On-line ·recog~
nition is much simpler because the data provide a nearly
exact trace of the path of the writing instrument and
give accurate stroke-position and time-sequence information. Furthermore, an error rate of as much as 5%
may be considered acceptable, because each character
can be classified, displayed, and corrected immediately
by the writer if it is wrong.
The recognition of hand-printed characters should
also be distinguished from that of cursive (connected)
script.25 The separation of the printed characters and
the fact that each belongs in fl, well~specified category
obviate the "segmentatiqn problem" that makes cursive-script recognition much more difficult.
Experiments in Recognition of Hand-Printed Text
Within the framework of off-line block hand printing,
the difficulty of a particular problem is still affected by
many variables: the size of the alphabet; the "standard" forms of the individual characters and the degree
of constraint placed on their formation; the size, spacing, and arrangement of text on the page; the writing
-instrument(s); the number of writers; their -training
and motivation; and the (fixed and time-varying)
characteristics of each individual writer. To illustrate
the variability of hand printing, we may cite several
instances of human recognition /rates on Isamples of
hand printing. Neisser and WeEme reported a 4.1%
average error rate on character~ printed by visitors at
the front gate at Lincoln Laboratory.1o With all subjects
voting together, the error rate was 3.2%. We have
reported an error rate of 11 % on the well-known
quantized character set collected by Highleyman,
which suffers from crude quantization of the characters.3D
On the multiple-coder data file used in our experiments and described below, the error rate was 4.5%;
on the single-coder file, 0.7%. Fin~lly, present commercial systems are intended to operate with character
error and reject rates on the order of 0.1 % to 0.01 %.
The most significant determinants of hand-printing
quality are the training and the motivation of the
printing population. Our choice in the work described
in this paper was to treat data from an essentially untutored, moderately motivated population, represented
by computer users who hand-code program texts for
keypunching. Such a coder has typically received no
instruction in printing, beyond a few rules about
slashing or crossing characters to avoid such confusions
as 1-1, O-zero, and 2-Z. He does receive feedback of the
results from prior keypunching jobs, which motivates
-him to maintain (perhaps grudgingly) a certain level of
'legibility. Thus, while this printing is far sloppier than
that allowed by presently announced recogn:ition systems, it is more legible than that produced by the
general public while, for example, addressing mail.
Two files of data were used in the experiments reported in this paper, a multiple-coder file and a singlecoder file. The characters in both files were handprinted on standard general-purpose coding sheets
obtained from the Stanford Research Institute computer center. The cells on these sheets measured 1/4
inch high by 3/16 inch wide, with no extra spacing
between cells. A thin-lead mechanical pencil with an
HB (soft) lead was used, after brief experimentation
indicated that no other conventional writing instrument gave crisper images when viewed through our
input system. (A pencil is the preferred instrument
because it facilitates erasure.) The coder was free to
use whatever character size he found natural.
1127
The 10 numerals, the 26 uppercase letters, and the
symbols [ = * / + - .,' $1 comprised the alphabet of 46
characters. This is the basic FORTRAN alphabet, with
brackets substituted for parentheses in accordance with
the convention associated with our computer system at
the time. The blank was not treated as a character'
category, the recognition of blanks being more a function of a document-scanning subsystem than a patternr~cognition problem. We instructed the coders to print
zero with a diagonal slash and Z with a midline slash,
and to put crossbars on the letter 1. Numeral 1 was to
be without serifs; several coders, however, added serifs.
Other choices were left to the individual, such as open
versus closed 4, the crossbar on J, and the number of
verticals in $.
Multiple-coder file
Printed data from 49 individuals were included in
the multiple-coder file. Each person was asked to print
several 46-character alphabets on a coding sheet (at
one sitting), and the first 3 alphabets from each sheet
were taken for the file. The data from the first 32 persons (96 alphabets, 4416 characters) were used as
training or design data during the experiments, and the
data from the remaining 17 persons (51 alphabets,
2346 characters) for test. The coders of the training data
were all personnel of the author's laboratory and the
computer center at SRI. The coders of the test data
were 8 from SRI and 9 from the US Army Electronics
Command, Fort Monmouth, N.J. Any cross-country
bias in printing styles is probably small compared with
individual differences.
Por~ions of several of the test alphabets are shown in
Figure 1. The coders were asked to print naturally,
being neither especially casual nor especially meticulous. However, it is obvious that data gathered this
way are not candid; they are probably better than data
from actual coding sheets prepared for keypunching.
Unfortunately, it was not feasible for us to process
candid data from a number of people using a variety of
coding forms and languages.
Five human subj ects were asked to classify the
character~ in 17 of the test alphabets-one from each
coder-viewing the quantized images (see the section
on scanning) in isolation and in random order on a
cathode-ray tube display. The error rates ranged from
3.0% to 6.4%, with an average of 4.5%. Taking a
plurality vote among the five responses, the error rate
was 3.2%.
Single-coder file
Experiments were also performed with a single-
1128 Fall Joint Computer Conference, 1968
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FIGURE 2-A sample of the single-coder test data
humans but not highly regular. Ten human subjects
were asked to classify the test characters. The average
error rate was 0.7%. Taking a plurality vote among the
10 responses, the error rate was 0.2% (2 errors in 1042
characters) .
Scanning
FIGURE I-Portions of several multiple-coder test alphabets
coder file, in order to investigate the Improvement in
performance resulting from allowing the recognition
system to specialize in the printing of a single individual.
This file contained 1727 training characters and 1042
test characters. The training set included 15 alphabets
(690 characters) of the type collected for the multiplecoder file. The remaining 1037 training characters were
taken from FORTRAN text on coding sheets, as were
the 1042 test characters. The 15 alphabets were included
in the training set to ensure adequate representation of
all the character categories, since their appearance in
actual text was haphazard.
The text characters were taken from FORTRAN
coding sheets prepared by the author in the course of
actual program development, some months befo,re the
recognition experiments were performed. The coder
corrected major malformations of characters as he
noticed them, but avoided printing with unnatural
care. Thus, while these data are not candid, it is felt that
they closely model a realistic situation that would be
obtained if one tried to serve a coder who was making
a minimal effort to assist the system. '
A sample of the test data" is shown in Figure 2. We
may describe these characters as being quite legible to
The hand-printed characters were scanned from the
source documents (the coding sheets) by a vidicon television camera fitted with a close-up lens and operated
under the control of an SDS 910 computer. Each document was mounted in a concave cylindrical holder so
that, as the camera panned across the document,· the
viewing distance and hence the image scale remained
constant. The field of view was approximately one inch
square. The camera generated a standard closed-circuit
television waveform, which was quantized to two
levels (black/white) by a Schmidt trigger and sampled
in a raster of 120 X 120 points.
The document was illuminated by four floodlights
mounted around the TV camera. A colored filter was
placed over the camera lens, to suppress the colored
coding-sheet guidelines anpearing on the document.
The guidelines could have been used for locating the
characters, but we preferred to strive for a free-field
character-locating procedure that could ultimately handle between-the-lines corrections or coding on a blank
sheet of paper. Also, without a color-sensitive input
system, separating the guidelines from the characters
where they crossed or coincided could be a major
problem.
The field of view was chosen so that a single character image was usually a little less than 24 points high
and about 15 points wide. The computer began the
scanning by reading in a 120 X 120 picture containing,
in general, several character images. A scanning routine
Experiments in Recognition of Hand-Printed Text
then proceeded approximately horizontally through the
picture, finding and isolating character images. Provisions were included for tracking a line of text, and for
accepting multi-part character images such as. equals
signs and characters with unconnected crossbars.
When the scanning routine got to the right of the
120 X 120 picture, it requested the camera to move to
the right and input another picture.
As each character was isolated, it was placed in a
standard 24 X 24 raster format (Figure 3). No corrections for magnification or rotation were applied.
The BCD code of the character was entered manually
**************************
*
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o 000000000
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0000000000000
*
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0000000
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00000000
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00000000000
****************************
FIGURE 3-A hand-printed character in the standard
24 X 24 format
1129
at the console typewriter and attached to the character
record, for subsequent use in the training and testing
procedures. The two files (single-coder and multiplecoder) of quantized 24 X 24 black/white character
images served as the starting point for all subsequent
processing. We hope to .make these files available to
other researchers through the efforts of the .subcommittee on Reference Data Sets of the Committee on Pattern Recognition of the IEEE Computer Group.
Our scanning setup was "strictly experimental." It
was an inexpensive substitute for the sophisticated
optical scanner and mechanical transport required for
a high-volume production system. Although the scanning routine enabled us to gather the thousands of
quantized characters in our data files, it was never
capable of running without an attendant to rescue it
from its errors. These were due to badly non-uniform
sensitivity across the field of view (common in vidicon
tubes), which made it impossible to set a single quantization threshold valid throughout the field, and to the
lack of precise knowledge of the position of the TV
camera. (Incidentally, by solving these problems, it
should be possible to create a low-speed, inexpensive
automatic scanning system along the lines of the one
described above.)
Other files of digitized hand-printed data, supplied
through the courtesy of W. Highleyman and researchers
at IBM Corporation and Recognition Equipment,
Iric., have been processed merely by converting them
to our standard 24 X 24 format. In some cases, this
has required changing the size of the character raster
by copying Or deleting rows and columns.
Preprocessing
The term "preprocessing" has acquired a variety of
meanings. We use it here to refer to the specific activity
of feature extraction: The calculation, from the
(quantized) character image, of a set of numerical feature values that form the basis of subsequent pattern
classification.
Two preprocessing methods were used in these
experiments. The first, embodied in a computer program called PREP, was a simulation of a .previously
constructed optical preprocessor capable of extracting,
in parallel, 1024 optical correlations between a character image and a set of photographic templates, or
masks. 4O The second, a program called TOPO, extracted a large number of topological and geometric
.features of the character image.
The PREP preprocessor
The PREP program performed edge detection on
the 24 X 24 quantized images through the use of
1130
Fall Joint Computer Conference, 1968
FIGURE 4-Edge-detecting masks in PREP
(a) Quantized character image
(b) An edge mask
(c) Character and mask together
edge-detecting mask pairs, or templates. Each mask
pair consisted of two 2 X. 8 rectangles of points, adjacent to each other along their long edges. One of the
masks was given positive weight, the other, negative,
and a threshold was set such that if the positive mask
encountered six more figure points than the negative
one, the binary response of the mask pair was ON
(Figure 4).
To provide a limited degree of translation invariance,
the responses of five such mask pairs were OR-ed together to give a single binary component of the output
feature vector. The five mask pairs in a group had the
same orientation and were in the same region of the
24 X 24 field. Nine regions were allotted to each of the
four major compass directions, and six regions were
allotted to each of the eight secondary directions (at
300 intervals). Thus, the complete feature vector consisted of 84 binary components, and the significance of
a typical component was, "An edge oriented north-ofwest has been detected in the left central region of the
field." Figure 5 shows a computer display in which the
lines are normal to edges detected in a sample of the
numeral 2. The lines emanate from 15 loci representing
the allotted regions.
Each quantized image was presented to the PREP
preprocessor nine different times, first in the center of
the 24 X 24 field,then in the eight positions formed
by translating it vertically and/or horizontally by two
units. Thus, for each pattern, a set of nine 84-bit feature
FIGURE 5-Responses of the PREP edge-detecting mask groups
to a numeral "2"
vectors was formed. The use of these multiple-view
feature vectors· to improve classification performance
is described below.
The TOPO preprocessor
The TOPO preprocessor was a sizable collection of
computer routines assembled to extract topological
and geometric features from the character image. In
general, these features described the presence, size,
location, and orientation of such entities as enclosures
and concavities (lakes and bays) and stroke tips in·
the character.
TOPO began with a single connected character image
in the 24 X 24 field. (The equals sign was sought out
in advance, and treated as a special case. Other unconnected figures were forcibly joined by growing a
bridge between the individual connected regions. If
this failed, the lesser region(s) were discarded.) The
perimeter of the figure was first found (Figure 6). The
perimeter was defined asa list of figure points, beginning
with the bottommost of the leftmost points of the
character figure, found by stepping along the edge of
the figure and keeping the figure always at the right
hand and the ground (non figure) at the left. The
perimeter has the property of including all figure points
hand and the ground (non-figure) at the left. The peri-
Experiments in Recognition of Hand-Printed Text
**************************
*
*.
*
*
XOXOOOOOOOOOX
*
*
XXOOOOO
OOX
*
*
XOOXOO00
OOX
*
*.
XX XOO
OOX
*
*
XOO
OX
*
*
XOO
OOX
*
*
XOO
OOX
*
*
XOO
OOX
*
XOO OOXX
*.*
*
XOOOOOX
*
*
XOOOOOX
*
*
XOOOOOOXX
*
*
XOO
OOXX
*
*
XOO
00 OX
*'
*
XOO
ox
*
*
XOO
OX
*
*
XOOO
OOX
*
*
XOO
OOOX
*
*
XOO
OOX
* XXOOO
*
OOX
* XOOO OOXXX
*
* XXXXXXXXXXX
*
*
*
**************************
X
x XXXXXXOXX
FIGURE 6-Hand-printed character with perimeter points
marked X
meter has the property of including aU figure points
that are 8-adjacent (adjacent horizontally, vertically,
or diago~ally) to ground points outside.
Next, the convex hull boundary (OHB) of the figure
was found (Figure 7). The OBB of a two-dimensional
figure may be thought of as the outline of a rubber band
stretched around the figure. In the case of a quantized
figure, some arbitrariness is reqUired in the specification
of the OBB, because a straight line between two points
on the image grid does not generally fall on exact grid
locations. We defined the OHB to include all the extremal points of the character image, represented by letters
1131
**************************
*
E
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
DxXXXXXXOXF
XOOOOOOOOOOOG
CXOOOOO
OOX
OOH
~OOOOOOO
xOO 000
OOX
. X
000
OOX
000
OOOX
X
000
000 X
X
000
000 X
X
000 0000 X
X
0000000
X
X
0000000
X
X
X
000000000 X
X 000
OOOOX
X 000
OOOX
X 000
OX
X
000
OX
X 0000
OOX
X 000
0001
X 000
OOX
XOOOO
OOX
XOOO
OOXXJ
AXXXXXXXXXK
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
**************************
FIGURE 7-Character with convex hull boundary (CHB)
t
ot herthan "X" or "O'J in Figure 7. In between these
extremal points, the OlIB was to follow as straight a
path as possible, bu~ never falling outside of the
theoretical straight line connecting the extremal
points. Keeping the ORB to the inside reduced the number of small, insignificant concavities found subsequently. To find the extremal points in the OHB, it
was only necessary to search among those perimeter
points at which the perimeter turned to the right.
After the OBB was obtained, the concavities and
enclosures of the character image could be found quite
readily using computer routines that simulated Boolean
and connectivity operations performed in parallel over
1132
Fall Joint Computer Conference, 1968
the entire 24 X 24 field. Let the border consist of those
ground point.s in the outerm')st rows and columns of
the 24 X 24 field. Let an image be formed consisting
of the ground, minus the CHB. The portion of this image that is not connected to the border lies within the
CHB and consists of the concavities and enclosures
of the character. Those regions that are connected to
the border by a path of ground points (including ground
points in the CHB) are concavities; those regions that
are not are enclosures within the figure. The character
in Figure 7 contains two concavities and two enclosures.
Multiple concavities and/or enclosures were extracted all at once in a single 24 X 24 array by the parallel
operations. They were then separated (again using the
connectivity operations) and sorted by size for subsequent use.
The spurs of a character are those strokes that end in
an isolated tip. Ideally, the letter X has four spurs, the
letter 0, none, and the letter S, one spur with the special property of having a tip at each end. The list of
perimeter points was used to find the spurs. Consider
two pointers moving down the list of perimeter points,
with one pointer ahead of the other by, say, 15 places.
As the pointers moved, we calculated the Euclidean
distance between the two perimeter points indicated by
the pointers. Some of these distances are represented by
arrows in Figure 8(a). Most of the time this distance
would be approximately 15 units. A sudden decrease of
the distance between the two points to a minimum that
was less than half its usual value indicated that the
perimeter had gone around a sharp bend-i.e., had
gone around the tip of a spur. The position of the spur
tip, indicated by the perimeter point halfway on the
list between the two minimum-separation points, was
the primary attribute of the spur used for forming features.
Once a spur was found, it could be traced by the
"caliper method" [Figure 8(b)]. Imagine that the legs
of a pair of calipers are placed at the two minimumseparation points. The calipers are then "slid" along
the spur by stepping the legs of the calipers along the
perimeter, away from the tiiJ. The calipers are moved as
far as they can go without having to be spread by more
than, say, seven units. In some cases, such as the numeral "6," the calipers will be obstructed by the body of
the figure and must stop. In other cases, such as the
letter "S," the legs of the calipers will travel all the way
along the figure and meet at the far end, indicating a
"single-stroke" figure. The midpoint of the moving
calipers traces out the backbone of the spur, and a list
of the midpoint positions can be stored to represent the
spur (the heavy line in Figure 8b).
Another set of character attributes found in TOPO
**************************
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
**************************
**************************
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
xxxxx
*
*
oooooooooxx
*
*
xoooooooooooooox
*
*
*
* xoooooooo oooooox
ooox
*
* xooooo
oooox *
* XOOOOO
xooooooooooooooox
*
*
xxoooooooooooox
*
*
xxooooooooox
*
*
xxxxxxxxx
*
*
*
*
*
*
*
*
**************************
FIGURE 8-Spur-finding
(a) Finding thp spur tip
(b) Tracing the spur
and used for feature generation were the profiles of the
character image. The profiles were four lists, of 24
entries each, specifying the first row (or column) in
which a figure point was encountered in each successive
column (or row) as seen from the top, bottom, left, and
right. The profiles were the basis of a number of specialized feature calculations, designed to discriminate
among particular categories, that evaluated such properties as the width of the character at various levels,
the number of reversals of direction in a profile, and
discontinuities in the profiles.
Numerical feature calculation in TOPO
After the topological and geometric components of
the character image-concavities, enclosures, spurs,
profiles, etc.-were extracted, it remained to convert
them to numerical components of a feature vector
suitable for subsequent classification by an adaptive
machine. This task was beset with several conceptual
and practical difficulties that may not be obvious at
first.
In TOPO, the task was carried out in two steps.
First, descriptors (individual numerical quantities) were
derived from the information at hand. Second, features
in a standard form were calculated from the descriptors.
Each descriptor had to be chosen so that it always
represented a unique characteristic of the character
image. For example, suppose that one descriptor were to
represent the vertical position of the rightmost spur
tip. Such a descriptor would help to discriminate, for
example, between T and L. But this descriptor would
give unpredictable results for characters such as C,E,
and [, depending on which spur extended farther to the
, Experiments in Recognition of Hand-Printed Text
right, and would probably be detrimental to the classification of characters in these categories. In addition,
there is the problem of vacuous descriptors: What value
do we assign to the above descriptor in the case of a
letter O?
In TOPO, these problems were countered by a careful
choice of the definition of the descriptors. In many
cases, it was possible to devise a descriptor that was
always well defined. For example, if a spur-descriptor
is put in the form, "To what extent is there a spur in the
upper right-hand corner," it is defined for any number
of spurs and can properly be given its minimum value
for a figure with no spurs at all. In addition, this form
of definition (unlike the preceding one) has the important property of continuity: Deformations of the character image that move the spurs by small amounts
always cause small changes in the value of the descriptor. In another paper, the author has argued that
the preservation of continuity is important throughout
the various stages of the pattern-recognition process. 38
As the final step in TOPO, the actual features (the
numerical components of the feature vector for classification) were calculated from the descriptors. A first
requirement on the features was that they be of comparable magnitudes, so that none would dominate the
sums formed in the pattern classifier. Thus, the features were all given a standard range of zero to 100.
(Note that these features were multiple-valued, whereas
those from the PREP preprocessor were binary.)
A second, heuristic requirement on the features was
that they emphasize the significant differences among
character classes. In a two-category classification problem, it is feasible to analyze the discriminating power
of a feature statistically (or even by inspection) and to
adjust the transformation from descriptor to fe~ture so
as to maximize this power. In our 46-category problem,
we could only guess at reasonable transformations. In
any case, one should not expect the feature to be a
simple linear function of a descriptor.
The,derivation of features in TOPO may be indicated
by an example. Consider a descriptor, MCONC(up)
which is a measure of the presence of an upward-facin~
concavity in the character. For a flat-topped or roundtopped character, such as T or 0, MCONC(up) should
have the value zero. For a character such as U or V
MCONC(up) should have a value of eight or greater:
For a Y or an open-topped 4, however, we should only
expect values of five or greater. Owing to the linear
nature of the dot-product units used in the pattern
c~sifier, it is impossible for a single feature proportIonal to MCONC(up) to discriminate between Y and
T, for example, without treating U as a "super-Y."
We actually require two features-one that "switches"
5
MCONC (up)
LNC~::~ .
O~!
o
1133
10
!
5
10
MCONC (up)
FIGURE 9-Two transformations that derive features from a
concavity descriptor
in the range 0 to 5 and one that does so at a higher
range.
The two transformations that derived features from
MCONC(up) in TOPO are shown in Figure 9. There
were two such features corresponding to each spur
descriptor and concavity descriptor in TOPO. In all,
TOPO produced 68 features: 16 for the spurs, 16 for
the concavities, 8 for the enclosures, 6 for overall
character size and shape, and 22 resulting from special
calculations about the width of the character at various
levels, discontinuities in the profiles, etc. Each feature
was calculated from a numerical descriptor by a transformation arrived at by'inspection.
It should be evident from the foregoing description
that the development of TOPO was a cut-and.,;'try
affair. The extraction of topological entities and the
generation of descriptors and features were continued
'only as far as patience permitted. For example, a featUre to look for structure within' an enclosure and help
discriminate between 0 and Q was never implemented.
It is the author;s opinion that the generation and selection of features for pattern classification, especially in
the multi-category case, is the greatest problem area
in pattern recognition at the present. 38
Olassification
An adaptive pattern classifier, or learning ma;chine,
was used to classify the characters on the basis of the
feature vectors generated, by a preprocessor; either
PREP or TOPO. The learning machine was of the
piecewise linear (PWL) type, described by Nilsson. '1
1134
Fall Joint Computer Conference, 1968
The learning machine for these experiments was implemented by a computer program called CALM (Collected Algorithms for Learning Machines),42 running on
the SDS 910 computer, which simulated the action of
the MINOS II hardware learning machine constructed
earlier during this project.40·43.44
Briefly, a learning machine embodies a set of Dot
Product Units (DPU's) that form the dot product (also
called the inner product or vector product) between
the incoming pattern, or feature vector, and a set of
stored weights. The jth DPU of the machine forms
the dot product
Sj
= X . Wj =
L: Xi Wij
between the pattern vector X and the weight vector W j
associated with the jth DPU. In a PWL learning machine, a small number of DPU's are assigned to each of
the 46 character categories. The largest dot product
formed among the DPU's assigned to a category is
taken as the response for that category.
The category responses may be utilized in two ways.
If it is desired to explicitly categorize a character, the
character is assigned to the category with the largest
response. A testing margin or dead zone may be employed, so that any character for which the largest response does not exceed the second largest by the margin
is classed as a reject. In the performance results listed
below, the reject margin is not used. The performance
scores are thus of the simplest possible type: percentage
of successful classifications with no rejects allowed
(response ties are broken arbitrarily).
Alternatively, if the goal is not to achieve a succinct performance measure but rather to use the character-classifi<>ation information for contextual analysis,
the responses may be used to obtain confidence information. The simplest confidence measure is the set of
46 responses from the learning machine, with a higher
response indicating a higher confidence that the character belonged to the category in question.
To adapt a learning machine, a training pattern is
presented, and the responses to that pattern are obtained. If the resPOnse in the true category of the
training pattern does not exceed the largest response
among the other categories by a value called the
training margin, the DPU yielding the response in the
true category is marked to be ~ncremented, and that
yielding the competing response is marked to be
decremented. This is done by setting
.
3.true = 1
; acompeting = - 1
in the adapt vector A,and setting all the other components of A to zero. Adaptation of the weights is then
performed according to the fixed-increment error
correction rule:
Wi
~
Wi
+
ai . D . X,
for all j.
In other words, the pattern vector is added to or
s:ubtracted from the jth weight vector, depending
on ai' D· i~ an overall multiplying factor called the
adapt step size, usually set to a small integer throughout
a block of training. (Other methods of determining the
responses and A and D lead to learning machines other
than the PWL machine.)41.42
The adaptation causes the subsequent dot product
between the pattern vector and the weight vector to
be changed· by an amount
L\Sj =
X . (aj' D . X) = ajD
Ix12.
Since ](2 and D are always positive, the sign of aj
automatically determines. whether the response (i.e.,
the dot product) of the jth DPU with the pattern X is
enhanced or reduced. Through this means, appropriate
DPU's can be made to respond to certain patterns and
ultimately to classes of patterns.
To perform a learning-machine experiment, the
adaptive weights w ii are initialized, usually to zero.
The training patterns are then presented sequentially.
The responses to each training pattern are f~rmed,.and
if the classification is incorrect the machine is trained.
One pass through the training patterns is called an
iteration. Typically, repeated iterations through the
training set are performed until the classification performance on the training patterns' ceases to improve. At
that time, .the test patterns may be presented, and the
classification performance on them recorded. This performance is generally taken as the measure of success of
the learning machine on the task represented by the
training and test patte~.
In dealing with the nine-view sets of feature vectors
produced by the PREP preprocessor, the running procedure was modified slightly (Figure 10). During training, one of the nine feature vectors representing a
training pattern was selected quasi-randomly at each
iteration. Thus, it took nine iterations for the machine
to encounter each view of each pattern. The use of
multiple views had the effect of "broadening" the
training experience of the learning machine. During
"nine-view testing," all nine views of each test pattern
were presented and the nine responses in each category
were added together to form cumulative responses that
were used as the basis for classification. It will be seen
that the redunda~cy achieved by accumulating the nine
responses led tq a'significant improvement in performance. This technique has also been used successfully
Experiments in Recognition of Hand-Printed Text
113.5
ther improvement with the combined system of Condition 4. The mORt important results can be summarized as follows:
c=J
OVERALL
CLASSIFICATION
RESPONSE
N
C LASSIFICAT ION
RESPONSES
FIGURE 10-Multiple-view testing procedure
U sing the combined system, a correct characterclassification rate of 97% (with no rejects) was
obtained on independent test of relatively unconstrained hand printing in the 46-character FORTRAN alphabet, when the learning machine was
allowed to specialize on data from a single coder.
When the learning machine was trained on the
printing of 32 coders and tested on the printing of 17
others, the correct classification rate was only 85%.
These rates are for the isolated characters, without
context.
Final Classification Scores
by Darling and Joseph in the processing of satellite
photographs. 46
Condition
Number of
Iterations
Preprocessor
Training
Patterns
Test
Patterns
Single-Coder File
Experimental result8
A series of experiments were performed on the singlecoder and multiple-coder data files, using the preprocessors and learning machine described above. Experiments were run under four conditions.
In Condition 1, the characters were preprocessed by
PREP, but only the one feature vector representing
the central view of each pattern was use~ for training
and testing the learning machine. Only the single-coder
file was run under Condition l.
In Condition 2, the characters were preprocessed by
PREP in all nine views, and nine-view training and
testing were performed as described above. A PWL
learning machine with two DPU's per category was
used in Conditions 1 and 2.
In Condition 3, the characters were preprocessed by
TOPO, and the single feature vectors produced by
TOPO were used for training and testing. Owing to
computer restrictions, a learning machine with only
one DPU per category was used. This is generally called
a linear rather than a PWL learning machine, after the
form of the discriminant functions in feature space. 41
In Condition 4, the responses of the learning machines in Conditions 2 and 3 for each test pattern were
added together and taken as a new basis for classification. This procedure was a way of harnessing the
preprocessor-classifier systems of Conditions 2 and 3
"in tandem" in order to improve classification performance, in a manner analogous to the nine-view testing
of the PREP feature vectors.
The results of the experiments are presented in
Table I. The results show a significant improvement in
performance for the case of nine-view training and
testing over single-view training and testing, and fur-
88'70
PREP, 1 view
10
99'70
PREP, 9 views
27
89% *
96'70
TOPO
10
94%
91'70
97%
Combined
Mult iple-Coder File
PREP, 9 views
18
TOPO
Combined
*Single-view
65'70
84%
*
78%
77%
85%
classification scores
TABLE I-Experimental results on two files of hand-printed:
alphanumeric characters
A well known set of quantized hand-printed character images (letters and numerals only) cqllected by
Highleyman were also processed under Condition 2,
yielding a test classification score of 68%. Previously
reported classification methods, not employing preprocessing, had achieved scores of 58% or less. These
characters are of very poor quality, being only 86% to
89% classifiable by humans. These results are described in Ref. 39.
A large number of preliminary and auxiliary experiments, not described in this paper, were performed.
In particular, during the development of the TOPO
preprocessor, an attempt was made to use the features
produced by TOPO in a binary decision-tree classifier.
The results of this effort were very poor, because it was
impossible to find features reliable enough to serve for
dichotomization of the character classes. For example,
1136
Fall'Joint Computer Conference, 1968
the presence of an enclosure was a useless feature,
because quantization noise introduce<;l some spurious
enclosures, and other expected ones were lost because
they were filled in or not completely formed. It thus
appears to us that, for patterns with the variability of
hand printing, an approach that considers all the
features in parallel is a necessity.
The development of the TOPO preprocessor, the
exploration of variations of the PREP preprocessor,
and the running of classification experiments with,
different learning-machine configurations and different
data files were all severely restricted by system limitati....
.,. ".....
..tJ. .A&lE•.
.1te.......1:1
,It.
.... , ..... ,,,,,-
X
If the first plus sign were chosen as the delimiter we
would have the two simple legal subexpressions
X as first choices' of each segment of the
X X and
P-list, but the concatenation of the two with another
plus sign is illegal. This pitfall can be avoided by making
a final legality check which, if not satisfied, forces a new
selection of potential delimiters. Thus although the
+
ll.e.
I:L~.L.A.G
.6.•6:"1
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N
COU.31-40
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XX++X
COLS.21-50
COLS. 11-20
COLS.I-IO
.T."".A.&
.11<
.T.a,lt .
,".iI..
..." ".A./ftl<'. II:
;"! 10 ...........
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.,.
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d>4
A.I.p-.r,A.6-.E.,
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........
x."
- ......r ....
0" ... .. ..........
A ... p. ........
.cd>
'T.I
to~
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.d.
.e..(),J
r-...
··.. ·'·-.AlcaE ",E,
N
".-
/
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....' •. I:I:.P.....
.~",
.... 4t..'s,:
.d>,.
.,10.
.T.O.
.0.
,4.
LI>.
'I..
•
..,.
FIGURE I-A hand-printed FORTRAN program
Experiments in Recognition of Hand-Printed Text
I
100
R~AD-IOI.AGE.WEIGHT
5
101
10
to!
20
21
7. 0
so
1~2
60
C0MM0N AG~.WE~GHT.AGEMEAN.WTMCAN.C0V
DIMENSI0N AGECI001.UEIGHTCIOOj
READ 1001IFLAG.M0KCF0RM/TC2ISl
-IF[ MER= 160. S. 5
FQRMATCFIO.21
G~ T0 [IN.=01301.IFLAG
01 I I 1=1.100
Wr:IGH.:.CIl=AGECSl
G~ T0 10
-00 21 1=1.100
AGECI1=WEIGHTCI1
CALL AVECAGE.IOO.AGEMEANl
tALL AVECWEIGHT.IOO.WTMEAN1
[0V=0.
GO SQ 1=1.100
C0V ; C0V+[AGECI1-AG[~CAN1*CWEIGHTCIl-UTMEANl
C0V=C0V/IOO.
--.
TYPE 102.IFLDG.C0V
F0RMATCIS.FIO.S1
G0 TQ I
=T0F'£ND-
TABLE I-First choice of classifier
based on the syntactic requirements of the respective
statement types. Each subpart consists of one of a
small number of constructs, e.g., an expression or a list
of integers. The analysis of each construct often begins
with a match against the table of identifiers. If the
resulting P-list is combinatorially simple it is analyzed
exhaustively by dynamic programming. Otherwise, the
P-list is further partitioned into segments by means of
delimiters and the segments are examined. Before any
exhaustive analysis is made the P-list is compressed to
reduce the number of alternatives. The final answer is
reconstructed from the compressed answer by comparison with the uncompressed P-list.
1145
products between a feature vector and 46 stored weight
vectors, one for each of· the 46 categories. The first
choice response is the category corresponding to the largest dot product. The context-directed analyzer uses
these dot products to determine alternative choices for
each character, together with a measure of confidence for
each alternative. The confidences C i are obtained by
normalizing the dot products according to
C . -- Si - Smax
Smax
~
1
=
1, . ~ ., 46,
where Si is the ith dot product, and Smax is the largest
dot product observed for all of the characters in the
source program.
Since the correct category for the character is usually
included among the choices having high confidence, it is
not necessary to consider every alternative for every
character. An empirical study showed that almost invariably the correct category was among those alternatives whose dot products were at least half of the
maximum dot product for that character. Thus, only
those characters whose confidences met this condition
were included in the list of alternatives. This typically
reduced the number of alternatives from 46 to 4 or 5,
with occasionally only 1, and never more than 10. The
price for this simplification was an occasional failure
to include the correct category, which was the case for
the five doubly-underlined characters in Table 1. Although this introduces extra problems, the reduction in
combinatorial complexity is worth the price.
Statement identification
Example
Source data
This section describes an experiment illustrating the
operation of the context-directed analyzer. The source
data for this example came from the hand-printed
FORTRAN program shown in Figure 1. The characters on
the coding sheet shown were scanned, preprocessed, and
classified by the methods described by Munson. 1 Because we purposely wanted data with a moderate error
rate, we chose to use only .topologically-derived
features. Using these features, Munson had previously
obtained a nine percent error rate on other data by the
same writer. The results on this data were very similar,
with 38 out of the 410 characters misclassified for an
error rate of 9.3 percent. The particular errors made are
shown underlined in Table 1. It is interesting to note
that about one-third of these classification errors would
not have been detected by purely syntactic methods.
These error rates correspond to the first choice responses of the character classifier, a linear machine. The
linear machine classifies a character by computing dot
As mentioned previously, the analyzer is organized as
a two-pass program. During the first pass, the type of
each statement is determined and variable names are
collected for the construction of the identifier table.
Statement identification was done by comparing the beginning of each statement with the "control" words,
IF, DO, READ, etc. For example, the alternatives and
the corresponding confidences for the first part of the
sixth statement were as follows:
R KA D
A [ R 0
V
Z E
U
R
L
Z
-25 -65 -28 -42
-49 -65 -62 -52
-61
-62 -68
-69
-77
-81
-81
The average confidence for the first choice selection
RKAD was -40. The average confidence for READ was
-41, which was sufficiently high to identify the state-
1146
Fall Joint Computer Conference, 1968
ment as a READ-statement. This matching procedure
correctly identified all but one of the 24 statements, including two cases in which the correct category of a control word character was not included in the list of alternatives. However, absence of the correct, category
caused the ninth statement, a DO-statement, to be
erroneously identified as the arithmetic-assignment
statement D711I = 1,100. Subsequent analysis failed
to resolve this as a legal arithmetic-assignment-statement, however, and the result of this failure condition
was that first choice decisions from the classifier were
accepted as the final output.
During the first pass, all COMMON, DIMENSION,
and input/output statements were inspected to collect
potential variable names. This operation was allowed to
be somewhat liberal, since the inclusion of spurious
identifiers is less harmful than the exclusion of actual
identifiers. For example, in the last TYPE-statement
the input/output list had the following alternatives:
F L D G
[
[ A 6
S
6 M+
K
2 N U
1
GAGE M0KE IFLAG WEIGHT AGEMEAN
COY
WTMCAN
IFL
Of these names, two were spurious (G and IFL), but
caused no trouble. Two' were wrong (MaKE and
WTMCAN), but since only one representative of each
was found, they could not be fixed. The remainder
(AGE, COY, IFLAG, WEIGHT, and AGEMEAN)
were correctly clustered.
Statement analysis
The identifier table
I
identifier table to the following first choice possibilities:
C
[
a v
DW
Q U
B +
G a
P
Because the fifth-choice comma had a fairly high confidence, the program found IFL and G as well as
IFLDG and COY as possible variable names. While
there is a danger 'that these fragments might have accidentally matched similar names elsewhere in the pro.gram, no such matches occurred. One reason is that long
names are tried before short names when the identifier
table is used, and this prevents the premature discovery
of erroneous matches with short fragments. Another is
that completely accidental matches involving names of
length greater than three or four are highly unlikely.
The search for possible variable names yielded the
following (first choice) possibilities:
G AGC MOK[ IFLAG WEIGHT AGEMEAN
IFLDG WTMCAN
COY
AGE
UEIGHT
AGE
WEIGHT
IFL
COY
Even in this simple example the need to cluster the
identifier table is clear, since (a) four names were found
more than once, and (b) three' of t1?-ese appeared with
different first choice spellings. Clustering reduced the
During the second pass, each statement was resolved
in turn. Since each different type of statement had to be
treated differently, a complete description of how this
was accomplished.would be tedious. However, the spirit
of our procedures can be conveyed by considering the
resolution of the long arithmetic-assignment statement.
For this statement, the first choices of the classifier were
50 COY = COy + [AGE[I] - AG[HCAN]
[WEIGHT[I] - UTMEAN] .
*
As with all statements, the label field (columns 1
to 5) was inspected first. Its resolution was trivial, since
the first choices were legal. Attention then shifted to
the statement field. Starting in column 7, a search was
begun for a possible equals sign to be used to break the
statement into a tentative variable and a tentative expression. (Had later procedures failed to resolve either
of these parts, the search would have been resumed for
a possible equals sign further to the right.)
The first character found having an equals sign for an
alternative was, in fact, the correct equals sign. At this
pOlnt, the first step was to resolve the left-hand side of
the statement. Since the tentative variable, COV, could
have been either a simple identifier (scalar variable) or
'an identifier followed by a bracketed list of expressions
(array variable), a search was begun for a string of the
form "alphanumeric, left-bracket." No such string was
found, of course, and the tentative variable was declared to be just an identifier of length three. A search
through the corresponding part of the identifier table
produced a match, and COY was accepted for the name.
The next step was to resolve the expression. Here an
exhaustive search of the expression for candidate identifiers was begun at once. Each candidate found was
matched against appropriate length entries in the
identifier table. This procedure produced five matches,
and changed the first choices for the expression from
bOY + [AGE[I] - AG[HCAN]
- UTMEAN]
* [WEIGHT[I]
Experiments in Recognition of Hand-Printed Text
to
1147
are much more difficult to implement. For example, the
of s~atement type is currently made by
matchmg the leadmg portion of the P -list against the
various control words. A short control word results in a
greater risk that the statement "type will be misidentified, yet a human easily identifies· statement types by
their general appearance or gross structure, as well as by
t~e (possibly misclassified) control word. This appreciatIOn of global structure has been one of the more difficult
abilities to give the analyzer.
Another observation is that the basic strategy employed by the analyzer should change with variations in
the error rate of the input data. The support for this observation rests on intuitive, rather than experimental
grounds, but it seems clear that elaborate procedures
that may be required for very poor data are unnecessarily inefficient on very good data. While the present
analyzer can cope with a certain amount of error-rate
variability by automatic ,adjustment of thresholds,
there is no provision to change the basic nature of the
operations as a function of the quality of the input data.
A third observation is that there will always exist
FORTRAN programs that are unlikely to be resolved
successfully. One need only consider the contrary programmer who defines three separate variables as
SS5S5, S5S5S, and S5SS5 to appreciate this. Whenever
there can be errors in the input, there is a chance of
errors in the output. In a practical system, one would
want to provide the user with more· than the final dec~sion of the recognitio.n system. For example, diagnostIC messages could be gIven to aid the user in finding and
correcting errors, whether they were committed by the
classifier, the analyzer, or the user himself.
I t is difficult to assess the usefulness of our techniques on the basis of an exploratory investigation. A
deter~ination
COY
+
[AGE[I] - AGEMEAN]
- WTMCAN1,
* [WEIGHT[I]
which, even though it contains the error in WTMEAN
a syntactically valid expression. Thus, in this case'
the expression was resolved by the first operation, the
use of the identifier table. The remaining operations
which have been very useful in other instances, were not
needed, and hence were not performed. Since both the
variable and the expression were now resolved, these
parts were joined by an equals sign and appended to the
results of the label-field analysis to yield the final resolution of the statement.
When similar procedures were applied to the other 23
statements, 28 of the 38 errors were corrected, reducing
the error rate from 9.3 percent to 2.4 percent. The final
output of the analyzer is shown in Table 2, where the
10 remaining errors are underlined. Thr.ee of these errors
were due to the appearance of WTMCAN rather than
WTMEAN in the identifier table, and three more were
due to other problems with identifiers: lVIOKE, MERE,
and S. A better method of using the identifier table, in
which a final determination of variable names is postponed until all matches are made, would no doubt yield
improved results.
Of the remaining four errors, one was in a FORMATstatement, one in the DO-statement control word, and
two involved labels. The FORMAT error was due to the
fact that we have yet to implement that part of the program that resolves FORMAT statements. The DO
error was caused by the missing alternative, and its correction would require the use of much more sophisticated methods for identifying statement types. Both
label errors, however, could easily be cured by using a
table of labels similar to the table of identifiers. Thus,
roughly half of the 10 uncorrected errors could be resolved by relatively straightforward additions to our
present program; the remainder would be difficult
indeed to fix.
.
IS
1
100
5
101
DISCUSSION
10
11
This paper has been concerned with techniques for using context to detect and correct character recognition
errors. A few concluding remarks and observations
about these techniques and their implementation are in
order.
Our first observation is that the addition of new techniques to the context-analyzer program can continue
virtually without limit. Many of these additions are
straightforward. For example, tables of library subroutine names or statement labels could be incorporated and used in an obvious fashion. Other strategies, which humans employ with remarkably little effort,
20
21
10
50
102
60
C0MM0N AGE,WEIGHT,AGEMEAN,WTMCAN,C0V
DIMENSI0N AGE[100l,WEIGHT[100]
READ 100,IFLAG,M0KE
F0RMAT[2I8l
In MERE 160,5,5
READ-I0l,AGE,WEIGHT
F0RMATCFI0.21
G0 T0 (10,201301,IFLAG
D7 11 1=1,105
WEIGHT[I1=AGE[Sl
G0 T0 30
D0 21 1=1,100
AGE[11=WEIGHT(I1
CALL AVE(AGE,100,AGEMEAN1
CALL AVE[WEIGHT,100,WTMCANl
C0V=O
D0 50 1=1,100
C0V=C0V+[AGE(I1-AGEMEANJ*(WEIGHT(IJ-WTMCANJ
C0V=C0V/I00.
TYPE 102,IFLAG,C0V
F0RMAT(I8,FI0.5J
G0 T0 1
STep
END
TABLE II-Final output of analyzer
1148
Fall Joint Computer Conference, 1968
thorough evaluation of the performance of the analyzer
can be made only by testing it on a large number of
FORTRAN programs produced by a variety of authors.
Unfortunately, we we:r,:e unable to undertake a dataprocessing project of this magnitude.
An equally difficult question concerns the extend.:.
ability of the reported techniques to other problem domains. These techniques can be characterized by three
qualities: risk-spreading in decision making, partitioning of a large decision problem into a hierarchy of subproblems, and continual checking of internal consistency. It seems clear that our basic approach applies
more or less directly to other programming languages,
and perhaps could be used with natural language in
tightly constrained situations. The conjecture that the
general approach, at least, can be. applied in more
general problems has a certain piquancy, but it remains only a conjecture.
We have, however, been able to achieve a substantial
reduction in error rate for a particular application. In
our opinion, it would have been difficult to obtain a
comparable improvement by applying more conventional context analysis methods which do not take
advantage of the special nature of the problem.
AKNO\VLEDGMENTS
The authors wish to thank their colleagues at Stanford
Reasearch Institute, and most particularly to thank
Dr. John H. Munson for many stimulating and fruitful discussions.
This work has been supported by the United States
Army Electronics Command, Fort Monmouth, New
Jersey under Contract DA ~8-o43 AMC-01901(E).
APPENDIX
In this Appendix we derive the decision rule that
classifies strings of alphanumeric characters in an optimal (minimum probability of error) fashion. By appropriately interpreting our result, we arrive at the decision rule described in the text.
Suppose that we are given some string of n characters
to classify. Our problem is to determine a string of n
categories that minimizes the probability of misclassification. If we let the vector Xi denote the set of
measurements made on the ith character and () i denote
the category selected for the ith character, then it is well
known from Bayesian decision theory that the minimum
probability of error is achieved by the following rule:
Select the categories
()I, ••• , ()n
which maximize the
posterior probability P(()l, ... , ()n/XI, ... , Xn).
In other words, the posterior probability is computed
for every possible assignment of ()l through ()n, and the
most probable assignment is taken as the decision.
By Bayes' law of inverse probabilities we can write
the posterior probability as
P(()l, ... , ()nIXI, ... , Xn)
p(XI, ... , Xn /()l, ... , ()n) P(()l, ... , ()n)
. p(XI , . . . , Xn)
(1)
This shows that the computation of the posterior probability depends upon both the prior probability
P(()l, .. ',()n) and the conditional probability P(XI, ... ,'
Xnl()l, .. . ,()n,). To simplify the computation of the conditional density, we make the reasonable assumption that the manner in which a character is formed
depends only upon the category of the. character
and not on the categories or the measurements of any
surrounding character. This assumption is equivalent to
an assumption of conditional independence, namely
that
n
. ' ... ,XnI()l, ... , () n
P (.XI
II p(Xil()i).
(2)
i=l
At this point we must make some assumptions about
the performance of the character classifier that provides the input to the con,text-directed analyzer. If this
classifier were designed for the optimal classification of
characters without regard to context it would compute,
for every () i, the posterior probability
During the design of the classifier it was tacitly assumed that all classes are equally likely a priori, so that
P(()i) = 1/46. We therefore make the bold assumption
that the classifier computes, for all 46 values of () i,
Substituting (3) and (2) into 0), we obtain
P(()l, ... , ()n/XI, ... , Xn)
=
IT
pe()l,···, ()n)
46 P(Xi)P*(()iIX i )
P(XI' ... , Xn) i=l
•
Now for given measurements Xl, ... ,Xn we are interested
in maximizing this quantity over ()l, ... ,()n so we can
ignore constants and factors depending solely on Xi and
obtain the following optimal compound decision rule:
Select the categories ()l, ... , ()n for which
Experiments in Recognition of Hand-Printed Text
11.
p(llt, ... , On)
IT p*(OiIX i) is maximum.
i=1
We can, of course, take any monotonic function of this
quantity and maximize it instead. Taking logarithms
we can select the 01, ••• ,0 11. which maximize
11.
log P (01, ... , On)
+L
log p * (Oi IX i )
.
i=1
If we define log p* (OiIXi) as being the confidence that
the measurements Xi indicate class Oi, then we may
reasonably define the confidence of the string to be
11.
~L log p*(oiIX i ) .
i=1
The optimal decision rule, then, computes the confidence of each string of length n, biases each string confidence by adding the logarithm of the prior probability
of the string, and selects as the answer that string
having the highest biased confidence.
REFERENCES
1 JMUNSON
Experiments in the recognition of hand-printed text: Part 1Character recognition
In this volume
2 BGOLD
Machine recognition of ,hand-sent Morse code
IRE Trans on Information Theory Vol IT-5 pp 17-24 March
1959
3 W W BLEDSOE J BROWNING
Pattern recognition and reading by machine
1149
Proc EJCC pp 225-232 Dec 1959 Also in Pattern Recognition
L Uhr Ed pp 301-316 Wiley New York 1966
4 LDHARMON
A utomatic read~:ng of cursive script
In Optical Character Recognition Fischer et al Eds pp 151-152
Spartan Washington DC 1962
5 A W EDWARDS R L CHAMBERS
Can a priori probabilities help in character recor;nition
JACM Vol 11 pp 465-470 October 1964
6 GCARLSON
Techniques for replacing characters that are gaTbled on input
AFIPS Conf Proc Vol 28 pp 189-192 Spring Joint Computer
Conference 1966
7 CKMcELWAIN MBEVENS
The degarbler-A program for correcting machine-read morse
code
Information and Control Vol 5 pp 368-384 1962
8 C M VOSSLER N M BRANSTON
The use oj context JOT correcting garbled English text
Proc ACM 19th National Conference paper D2 4-1 D24-13
lQ64
9 KABEND
Compound decision procedures JOT pattern recognition
Proc NEC Vol 22 pp 777-7801966
10 KABEND
Compound decision procedures for unknoWn distributions and
for dependent states oj nature
In Pattern Recognition L Kanal Ed Thompson Book Co
Washington DC 1968
11 JRAVIV
Decision making in 1tlarkov chains applied to the problem of
pattern recognition
IEEE Trans on Info Thy Vol IT-13 pp 536-551 October 1967
12 R 0 DUDA P E HART J H MUNSON
Graphical-data-processing research study and experimental
investigation
Fourth Quarterly Report Contract DA 28-043 AMC-01901
(E) SRI Project ESU 5864 Stanford Research Institute Menlo
Park Calif March 1967
The design of an OCR system for reading handwritten
numerals
by WILLIAM S. ROHLAND, PATRICK J. TRAGLIA
and PATRICK J. HURLEY
International Business Machines Corporation
Roahester, Minnesota
INTRODUCTION
The problem of transcribing computer input data
from a human-sensible form to a machine-sensible
form has grown with the computer industry. The
".Inpu t gap" h as aIso grown as the time to process
a given batch of data in the CPU (central processing unit) has become smaller and smaller when
compared to' the time needed to manually transcribe that same batch of data. In short, today's
da~a process~ng systems are capable of accepting,
USIng, and dIsposing of data at much faster rates
than available input devices are capable of providing, without some form of preliminary offline conversion or transcribing process.
Optical character recognition (OCR) has been
given much credit for helping bridge the "input
gap." This is because optical character readers
have been used for several years for the automatic transcription to computers of data printed
in certain specified type fonts on certain specified
types of input devices such as high-speed line
printers, typewriters, credit-card imprinters, and
a variety of printing presses, cash registers and
adding machines. This would include sales checks'
ai:line, bus, and train tickets; utility bills; pre~
mIum notices; charge -account statements, and
countless others too numerous to mention. One
input device for character recognition that had
not been successfully exploited during the early
years of OCR was the common lead pencil.
This paper traces the steps taken in exploring
the practicality of an input system consisting of
a usually unconcerned, intractable human being;
an always too sharp or too dull pencil; and an
optical reader designed to accommodate many of
these variables. The initial objectives, as defined
by Market Planning, will be discussed. The tech-
-nology choices will then be examined, and the
limitations and problems of the system discussed.
Finally, relative performance as a function of
training, motivation of, and feedback to, the
writer will be presented.
This paper deals with only one aspect of the
IBM 1287 Optical Reader (Figure 1). Although
this machine possesses the capability of reading
many type fonts printed by a variety of input
devices, only the Numeric Handwriting Feature
(NHW) will be discussed. The discussion presented here also applies to the numeric handwriting feature of the recently announced IBM
1288 Optical Page Reader.
Initial objectives
Several initial design objectives for developing
a hardware capability for the reading of numeric
handwriting were set forth.
• The minimum character set should be the ten
numerics plus five control symbols, preferably
alphabetic characters. (e, S, T, X and Z were
chosen)
Although some applications require, or
prefer, full alphanumeric capability, a
definite majority of the applications can
be handled with the stated minimum set.
Dollar amounts, stock numbers, merchandise classes, departments, dates, clerks,
customers and creditors can all be identified by numbers. The limited number of
control symbols are necessary for tagging
various categories of numeric information,
i.e., negative balance, sub-total, taxable
amount, etc.
• Acceptable character shapes should be thO,fJe
1151
1152
Fall Joint Computer Conference, 1968
acter reject and substitution rates) and product cost are interrelated to a high degree, with
many trade-offs possible among these three
factors. General limitations, however, mus·t be
set for each factor.
FIGURE I-IBM 1287 optical reader
rw..turally formed by the majority of the population.
There is some disagreement as to whether
one "writes" or "prints" numeric characters. On the other hand, the difference between handwritten and hand-printed alphabetic characters is generally recognized.
For· clarification, the character shapes are
defined as handwritten numerals and handprinted alphabetic symbols (not cursive
script).
Although it is highly desirable through
training techniques to limit the distribution of acceptable character shapes, these
techniques should not force the writing of
unnatural character s·hapes.
• Within the limit8 of good human engineering,
the constraints printed on the document to
guide the writer relative to the location, size,
and aspect ratio of the character, shall be minimum.
This is based on the premise that the simplest constraint will tend to· result in the
simplest training and maximum effectiveness in writing.
• No special printing devices must be required,
other than a common No.2 pencil.
There should be no requirement· for special
inks, pencil leads, 'or for papers other than
OCR bond papers.
• The objectives for recognition rates (characters
per second),' recognition performance ( char-
The recognition rates must be such that,
when effective throughput rates are calcu-lated, with provision for transport time,
format control, and reject rescans, these
effective throughput rates represent a good
payoff to the customer.
Reject and substitution rates should be
the same or lower than equivalent error
rates of equal impact in the manual transcription process. For example, the character substitution rate should be no higher
than keypunching error rates, which are
comprised primarily of transposition' errors. Customer satisfaction with a given
level of· rej ects and substitutions will depend to some extent on the effectiveness
of his system checking and correction routines.
The product cost, after all trade-offs
have been made, must obviously be compatible with a marketable price.
Technical description-IBM 1287 Optical Reader
The numeric handwriting function of the mM
1287 Optical Reader will be described in three
parts:
• Scanner and Format Control,
• Data Extraction Process, and
• Recognition Decision.
Scanner and format control (Figure 2)
A CRT (cathode ray tube) flying spot scanner
was chosen for the 1287 primarily because of its
format and scan pattern versatility. This versatility was required to accommodate a wide range
of· document sizes and formats, and to provide
the scan patterns for mark reading and for a
variety of stylized type fonts, in addition to those
required for NHW.
The scanner is composed of a 5-in. PS6 CRT
(PS6 is the phosphor type), two mirrors, a f/2.8
2:1 magnifier lens, a 11h-in. Sll response .monitor PMT (photomultiplier tube), a 5-in. Sll responsedocument PMT, a PMT power supply, and
a high voltage power supply which provides bQth
the focus potential and post-accelerator anode p0tential for the CRT. Mechanically, the light-tight
Design of OCR System for Reading Handwritten Numerals
.../1-(------{}-~:~~
PMTr~
,
!
I
Document
I PI.III
II
1
.---.1-._ _
To CPU
FIGURE 2-Schematic of scanner and format control
scanner housing is mated at the document transport plane to a vacuum bed plate. A clutched belting arrangement transports the document to the
vacuum bed plate through a pair of light-seal
brushes.
Within- the scanner housing, the CRT spot of
light is reflected 90 deg. by the first mirror, and
magnified and focused at the document plane by
the lens via the second mirror. Light reflect~d
from the document is sensed by the document
PMT which, in turn, provides an intensity-modulated signal to the video amplifier.
The CRT spot is constantly and directly monitored by the monitor PMT. The state of the art
of phosphor deposition on CRT screens precludes
a perfect screen; therefore, variations in spot
intensity at the CRT screen, which are caused by
phosphor graininess, are detected by the monitor
PMT and the output from this PMT is subtracted
(in the video amplifier) from the output of the
document PMT.
The video circuitry amplifies the video signal,
compensates for long and short term drift in
scanner components, and stores peak electrical
excursions for clipping functions and other ana-
1153
log-to-digital conversions. The output of the video
circuitry goes to beam control.
Beam control is that portion of the logic which
maintains control of the CRT beam at all times.
This block of circuitry receives input from the
format control circuitry and from the recognition
logic, as well as from the video circuitry. The
beam control provides input to the CRT deflection
drivers and to the location-direction generators.
The feedback of beam control data to the. CRT
deflection system completes the optical-electrical
flying-spot. scanner loop. The CRT beam action,
therefore, is really dependent upon what the
document PMT had seen as a result of beam action a half-microsecond earlier.
The location-direction generators, which provide basic vital data to the recognition logic, will
be described in detail in connection with data
extraction.
The beam control circuitry can be controlled to
generate sine and cosine functions ·in such a manner as to produce a circle scan (Figure 3). In addition, the circle size can be selectively attenuated
while in black so that scanning progresses along
a black edge. If the circle is allowed to proceed
unattenuated at diameter X until it strikes black,
and is then attenuated to a diameter of X/2 for
Yaxis
X.xis
-----+---..,....--+---+---+---
Direction of belm trlVel
LBllCk hit detected .ttenulte to smlll circle
I
I
I
Non reflective line
!
~.---+t~
Direction of trlVei of locus of centers
FIGURE 3-Circle sca.n method
•
1154
Fall Joint Computer Conference, 1968
180 deg., and the process repeated, the scanning
along a line will progress at the rate of X/2 per
circle.
Two modes of circle scan are utilized by the
1287 in the NHW mode. The search for the first
character in the field is accomplished by forcing
a horizontal right-to-left circle scan. As real black
video is encountered, curve following is initiated
with the full flying-spot scanner feedback loop in
operation. The result is that the beam progresses
generally clockwise around the outer contour of
the character.
Many of the 1287 functions are under program
control. These include the run control, the scanning format, direction of scan, type fonts to be
read, reading modes to be employed, and special
format conditions. Two-way· communication between the 1287 and the CPU (normally System/
360 Models 25 through 50) is handled by the CPU
interface circuitry. This control may best be illustrated by following a sequence of events in the
processing of a document.
When the CPU has determined that the 1287
is in a "ready" status, as indicated by the run
control (via the CPU interface), a command is
issued to the run control to feed a document. The
run control then takes over and feeds, separates,
and aligns the next document and properly registers it in the light-tight scan station. The CPU is
then advised by the run control that a document
is in the read station and the 1287 is prepared to
scan the document.
The CPU then issues a series of format words,
one for each field of data to be scanned, as required
by the 1287. Each format word contains four
hexadecimal bytes. The first 3 bytes contain .the
vertical and horizontal start, and the horizontal
stop respectively. (The CRT beam can be addressed to any set of coordinates within a 256 X
256 grid.) The fourth byte identifies the type font
to be read in that field, determines the scan direction, how blanks should be transmitted, and
whether on-line or off-line correction is to be effected should a reject character appear.
It should be noted that the first format word
transmitted for a new document results in addressing the document reference mark. A special
hardware routine is initiated to locate the edges
of the reference mark with respect to the coordinates defined in bytes 1 and 2, and to generate a
registration error voltage which is "used to modify
the coordinates of all fields subsequently addressed on this document.
As this information is being transmitted from
the CPU, it is stored in the format control circuitry-the first three bytes in a digital-to-analog
converter and the fourth byte in digital storage.
At the conclusion of the transmission, the scanner
is ready to begin a seek operation to a point to
the right of the field to be scanned, as defined by
bytes 1 and 2.
When the CPU replies with a signal indicating
that it is ready to accept the transmission of recognition information, the format control signals
the beam control to seek to the XY coordinate indicated by the first two bytes. When the beam
reaches that point, a right-to-Ieft artificial follow
is initiated by the beam control to search for the
first character in the field. When the last character
in the field has been scanned and the beam has
progressed horizontally to the location indicated
in the byte 3 of the format word, the beam is
forced into a large raster or idle mode.
The beam remains in large raster until the CPU
transmits the format word for the next field to
be scanned. This process is repeated until all fields
on the document have been scanned. At that time,
the CPU transmits a document eject command.
The run control executes the command by moving
the document just scanned into the stacker transport and by moving the next document into the
scanning station.
Data extraction process
Because of the wide variability of handwritten
numerals, it is highly desirable to extract a relatively small number of measurements that are
highly insensitive to minor variations in the shape
of the same character. On the other hand, these
measurements must dichotomize the character set
in order to have discrimination value. There is a
very practical limit, however, on how far a given
measurement can go in meeting these two requirements. As we shall see later, if the variation in shape for a given character is allowed to
degrade beyond a reasonable limit, it can no longer
be distinguished from the degraded form of another character.
A form of measurement that generally meets
these requirements is a sequential arrangement of
combinations of locations and vectors (or directions) generated as a result of contour following.
The process of contour following with a circle
scan and selectively attenuated circles has been
described.
The handwritten numeral is found on the document by means of the artificial follow search rou-
Design of OCR System for Reading Handwritten Numerals
S.rch circle scan
. ..
1155
I.~;'
~ ~, :~.
Point addressed by format
2
3
4
•• "!"
.~::
... :,.
& "':'.':.'..... :.:..
Seek
-"'n
c_.....tar
SEMI
·d./dl > . (dy/dtl (t•• 15°)
FIGURE 4-Contour following a character
tine (Figure 4).· When real video data is encountered, the video-deflection feedback loop causes
the beam to follow the outer contour of the character in a clockwise direction. The beam is permitted to make a "first follow" or complete trip
around the character to exactly locate the character, normalize the measurement circuitry to the
size of the character, and optimize threshold circuitry. The follow circle scan frequencies are filtered out of the deflection signals thereby providing signals representing the locus of circle centers
for subsequent recognition measurements.
During the "first follow," the filtered horizontal
and vertical deflection signal excursions about a
zero reference voltage are tracked, and their extremes are stored. The stored voltages, representing the horizontal and vertical extremities of the
character, are applied across resistor divider networks which divide the horizontal dimension into
four zones (A, B, C and D) and the vertical dimension into five zones (1, 2, 3, 4, and 5) (Figure
5A). During the "second follow," location information is. provided by comparing the current referenced deflection voltages to the levels stored in
the four by five matrix.
The instantaneous direction of travel, with an
angular resolution of 30 deg., of the circle center
is obtained as follows: The filtered XY deflection
signals are differentiated to generate the signals
+dx/ dt, -dx/dt, and -dy/ dt. Each of these
three signals is then effectively multiplied by the
tangent of 15 deg. Voltage comparisons of appropriate pairs of these six signals yield six digital
signals which represent six semi-circles, each
one displaced 30 deg. from the next. For example,
the output of the voltage comparator comparing
+SEM1~
'SEM2-VN.
FIGURE 5-A four by five matrix
B Voltage comparator
C "ANDing" Sem 1 and Sem 2
the amplitudes of -dx/dt and -dy/dt (tan 15°)
is active whenever the direction of circle center
travel is in the semi-circle bounded by 15 deg. west
of due south to 15 deg. east of due north (refer
to the shaded area in Figure 5B). Any particular
30 deg. direction segment, or any combination of
30 deg. segments, can be generated by "ANDing"
two of the 12 signals composed of the six semicircles signals and their inverses. The 30 deg. segment representing "north" is generated by "ANDing" together + (semi-circle 1) and - (semicircle 2) as illustrated in Figure 5C.
In order that information about the duration
of travel in a particular direction might be utilized for characters of varying size, the time to
follow around a second time is normalized by making the follow circle scan diameter linearly dependent on the amplitude of the stored voltage
representing the character height.
Two types of measurements, known as feature
tests and supplementary scans, are made on the
character.
Feature tests make use of the parameters of
1156
Fall Joint Computer Conference, 1968
2~h~~eJ
3J..-~~~aJ
4
--1
1
2
(W + WNW)~) T = X Ilsec (sets first 3BN latchJ
@.y (1+2)
- (resets first 3BN latch)
(E + ESE) .(4+5) T = Y Ilsec (sets second 3BN latchJ
(W+WNW).(5) resets SecoM 3BN latch)
(WSW + W).(5).(C + D) (sets first 2BT latchJ
(A + B)
(NNE + ENE + E + ESE + SSE + S + SSW)
~ T = Z Ilsec resets first 2BT latch)
r
@
<1illD
<:iillV
r
-~(1+2)
i
t::\3 (1)
'&'
r
~ + N)
T = Y Ilsec (sets second 2BT latchJ
(NNE + ENE + E + ESE + SSE + S + SSW)
~
T = F Ilsec resets SecoM 2BT latch)
~lID (WSW + W).(3 + 4 + 5).(A + B) (sets third 2BT
latch, which resets second 3 BN latchJ
{sets final 3BN latchJ
r
FIGURE 6-Typical feature. test
location, direction, time, and sequence while following the outer contour of the character to identify character feature shapes. These feature
shapes are subordinate to an entire character
shape and many are common to several characters.
A typical feature test will be described in detail
to illustrate the manner in which position and
direction information is used (Figure 6). This
feature test is called 3BN-"three bottom, normal"-because it is intended to recognize the most
common variations of the bottom horizontal stroke
of the numeral 3 (or 5). Three sequential conditions are required to satisfy 3BN. They must all
occur during "second follow." First, the circle
center must travel west or west-northwest in
rna trix row 5 for x microseconds. N ext, there
must be y microseconds of travel east or eastsoutheast in matrix rows 4 or 5. If the beam
tJ'avels into matrix rows 1 or 2 before satisfying the second condition, the first condition is reset, and must be satisfied again to reinitiate the
sequence. This "reset" condition prevents such
shapes as "open topped" zeros or ones with a tick
on the right side from- passing the test. The final
requirement is that the beam travel into matrix
row 1.
There are two events that will reset the second
condition if they. occur before the final requirement is met. They are, 1) if the beam travels
west or west-northwest again in row five, which
prevents the test being prematurely passed during "first follow," and, 2) if the third condition
of the feature test "two bottom-like-three" (2BT)
is met. This last reset condition makes use of a
portion of the feature test designed to recogniz~
two bottoms that droop down toward the lower
right, somewhat like the upper right hand portion
of a normal three bottom. This sort of thing is
done fairly often throughout the feature test
logics. Sometimes, instead of using part of another feature test, the reset condition is itself
sequential. The only reason for asking for row 1,
as the last requirement for 3BN, was to make it
possible to implement the last two reset conditions.
Nearly all recognition decisonscan be made on
the basis of only feature test data. Only when the
feature tests do not yield a high-confidence recognition decision are supplementary scans employed
to "look inside the character" for additional information. Some of the conflict pairs that can be
resolved by supplementary scans are the skinny
zero vs the fat one; a nine vs an eight with a narrow bottom loop; a zero vs an eight without dimples on the sides; and, a fat-topped seven vs a
thin-topped nine. The first two examples would
be resolved by a horizontal supplemental
scan looking for two black hits vs one hit. Similarly, the third and fourth examples would be resolved by a vertical supplementary scan.
The recognition decision
Compared to what has been described thus far
concerning beam and format control, t.rigonometric scan patterns, generation of locations and directions, and the development of feature tests, the
recognition decision logic may appear to be somewhat trivial. Basically, it is a combinatorial logic
statement for each character in the set, operating
on the output of the feature test circuitry, that
provides the decision directly (unless a conflict
must be broken by the use of a supplementalscan) . Based on the characters involved in the conflict, the recognition logic will select the type of
supplemental scan required. The logic statement
for any given character usually consists of a number of paths representing the most commonly encountered variations of that character's shape. For
example, the logic tree for the nine logic includes
a path for nines with open tops (4:j), a different
path for nines with an opening on the left side
(Q), another path for nines with a three-like
bottom (9), as well as paths for the more con-
Design of OCR System for Reading Handwritten Numerals / 1157
is directed to a point immediately to the right of
right center (referred to as the initial point).
Right-to-Ieft artificial follow is then initiated with
the video blanked until the beam has passed the
area occupied by the character just recognized.
Artificial follow then continues until the next
character is encountered. If the recognition logic
is unable to make a decision based on available
measurement data, the beam is returned to the
initial point and a second recognition attempt is
made. Up to two rescans are made, with clipping
level adjustments made in instances where specific
degradations of the character are indicated. If
the character cannot be confidently identified after
two rescans, the CPU is so informed and the
recognition process is continued on the next character.
Document format and writing implements
This section presents a typical handwriting doc-
um~nt format showing the field and character lo-
FIGURE 7-Feature tests satisfied by "3"
ventional closed loop-straight stemmed nines.
Figure 7 shows a well-formed character 3 and
some of the feature tests which it satisfies. A
fairly horizontal top start produces 2 TN (2 'rop
Normal) which is commonly found in the characters 2, 3, and 7. A number of other feature tests,
representing a variety of other top start conditions would be just as acceptable. The RNS (Right
Notch Straight) is a strong characteristic in the
character 3, and to a lesser degree in the 8. The
9B3 (9 Bottom Like 3) is very common for the
character 3 and some forms of the 9. The 3BN (3
Bottom Normal) ending is typical for the five and
some forms of the nine. All other normal 3 endings also yield acceptable feature tests in this area.
The 3CN (3 Cusp Normal) adds considerable
weight to the decision for the 3.
This diagram shows only those feature tests
satisfied by this particular shape of the character 3. There must obviously be a number of feature tests that remain unsatisfied in order to
prevent other character shapes from substituting
(or satisfying the 3 logic). In the same manner,
some of the sequence tests that are strongly satisfied by the 3 should show up as inhibit conditions
in the logics for other characters.
When a character has been recognized, the beam
cators determined to be optimum by a series of
extensive human factors experiments and field
studies, and discusses the proper choice of writing
implements.
Document format
Figure 8 is one possible format for a retail sales
check. The document reference mark, which can
be located anywhere on the do.cument within the
scanning area, is used to provide the link between all field locations on the document and
the format co.ntro.l system, and to compensate
for variables such as paper cutting, printing registratio.n, and do.cument stopping tolerance. On
this document, the reference mark is the dark
"L-shaped" mark in the upper right-hand corner.
All the fields o.n this do.cument are horizontally
aligned, but may be both horizontal and vertical
on the same document if this is desired in the application. The o.nly requirement on the placement
o.f data fields is a 0.125-in. clear band between any edge o.f the field and the edge of the
do.cument o.r ano.ther field. Each field is co.mprised
o.f o.ne o.r mo.re character lo.cators, which are rectangular boxes printed in a reflective ink (shaded
area in Figure 8). As determined by human facto.rs studies o.n ho.w peo.ple no.rmally and comfortably write, the aspect ratio of the bo.xes should
be three-to-fo.ur (width to height), with the height
ranging fro.m 0.240 to. 0.320 in.
A space o.f 0.020 in. between boxes is recommended in order to. minimize linking o.f adj acent
1158 Fall Joint Computer Conference, 1968
-4~S....
dJ
!J---=--~
-
o
041735
FIGURE 8-Possible format for retail sale& check
characters. The lower left-hand field of Figure 8
illustrates the confusion that can result both to
the human reader and the OCR reader when handwritten characters are linked. The field was intended to contain the digits 2 1 5 1. Without the
preconditioning that the boxes provide, the field
could easily be interpreted as 4 5 1, or even 4 3 7.
Constraints other than a rectangular box were
considered and tested early in the development of
the current technology, but these were discarded
because of the additional burden placed on the
writer and their interference with normal writing
habits. Generally, it was concluded that the fewer
rules the writer must remember about the formation of each character, the greater will be his
acceptance of recommendations for good writing
disci pline.
Writing implements
The ideal writing implement should provide a
continuous stroke of uniform width and density
throughout the character. The written character
should be largely independent of the pressure applied to the writing implement, should be highly
insensitive to smudge and smear, and should have
a minimum of extraneous non-reflective matter.
A number of writing implements were investigated for their suitability in providing the desired characteristics. No known implement studied
consistently provided all of these characteristics,
and therefore the selection of the implement was
a matter of a best compromise.
Table I presents the conclusions of an evaluation of a variety of fine-line pencils and pens in
terms of the characteristics desired in a writing
implement. A plus (+) in the matrix should be
interpreted as an advantage for that implement,
a minus (-) as a disadvantage, and a zero (0) as
no net advantage or disadvantage. Note that it is
next to impossible to assign a value to each of
the pluses and minuses, and that they have widely
varying values. Inasmuch as a minus in only one
characteristic could nearly rule out a given implement, the scores are not directly additive. It
should also be noted that the applicability of a
given implement varies with the application, the
writing environment, the training emphasis of
the writer, and other factors.
A primary conclusion is that the best overall
writing implement is the fine-line mechanical pencil with a medium lead (No. 2-2112). All mechanical pencils have a minor maintenance disadvantage in that they can run out of lead, but normally the lead can be quickly replaced by a spare
carried inside the pencil.
One runner-up is the wood pencil with a medium
lead. Its disadvantage is that the point breaks or
becomes dull (reliability), and needs to be sharpened (maintenance). A second runner-up is the
fine-line mechanical pencil with. a hard lead
(harder than No. 2 112). Its disadvantage is its
lighter stroke density and the range of density,
particularly under the condition of lightly applied
pressure. This factor can be overcome to some extent, however, with proper emphasis on training.
Soft lead pencils have the disadvantage of susceptibility to smudge and smear and to leaving
extraneous deposits of graphite, compared to medi urn and hard lead pencils.
Ball-point pens are characterized by their uniform stroke width and insensitivity to applied
pressure on the one hand, and by skipping (lack
of stroke continuity), smear susceptibility, extraneous ink deposits, and running out of ink (reliability) on the other hand.
The advantages of the fountain pen are its continuity of stroke and uniform stroke density. However, it tends to smear wet ink, and at times leaves
a double track. It also runs out of ink (reliability)
and needs to be filled (maintenance).
The felt pen has some key advantages, such as
continuous uniform stroke (both width and density) and insensitivity to pressure. It has some
Design of OCR System for Reading Handwritten Numerals
equally key disadvantages. Its (absolute) stroke
width relative to normal character size is too
large causing a general blobbing of the character.
It leaves extraneous deposits of ink, and the pen
tip dries quickly unless it is covered.
In most applications the ordinary medium wood
pencil will satisfy the need for a writing implement. A medium lead mechanical pencil adds reliability and convenience. In applications where a
more permanent recording is required, certain
1159
types of ball-point pens can be successfully used
under proper conditions.
Hurnan factors
Motivation
In most endeavors, motivation can make the
difference between success arid failure, or at least
the difference between highly successful results
and moderately successful results. Case studies
Writing Implement
•
..c:C)
Desired Characteristic
C"I
•
Q)~
~e.
+
+
Uniform Stroke Width
(constant pressure)
o
Absolute stroke Width
o
+
Continuous Stroke
(constant pressure)
o
Uniform Stroke Density
+
+
+
o
+
+
+
o
o
o
o
o
o
o
o
+
o
o
Smudge/Smear Resistant
o
+
o
+
Lack of Extraneous Deposits
o
+
o
+
+
+
+
o
Lack of Maintenance
+
+
+
o
Reliability
+
+
+
o
Good Stroke Starting
+
+
+
o
+
+
+
o
This characteristic is an advantage of this implement.
This characteristic is neither an advantage nor a disadvantage of this implement.
This characteristic i~ a disadvantage of this implement.
TABLE I-Suitability of writing implements for NHW.
-
+
+
+
o
o
o
+
o
o
Pressure Insensitive
+
o
+
o
o
o
1160
Fall Joint Computer Conference, 1968
on the application of numeric handwriting as direct input to data processing systems have verified some interesting data. These case studies
were conducted in a variety of .industries to determine the effectiveness of motivation, training,
and feedback, and the interrelation of these factors. In all cases, the gauge of effectiveness. was
actual performance on a prototype model of the
IBM 1287 Optical Reader in reading documents
generated in the case studies. Only the conclusions
from the studies will be presented.
Motivation must first be instilled at the user's
top management level. If the enthusiasm for and
confidence in a program is generat~d there, and
the need for positive involvement is communicated
downward through all levels to the operational
level, the probability of success is greatly enhanced. In the case studies where management interest and involvement were obvious to the lower
level employees, the response was one of equal
interest and enthusiasm. In post-test interviews
that were conducted among participating highly
unionized employees, comments such as "If it's
good for the company, I want to do well" were
common.
In general, the case studies demonstrated that
highly motivated employees working under poor
environmental conditions yielded results that
were at least as successful as those produced by
moderately motivated employees working under
excellent environmental conditions.
Some employees were motivated by the mere
fact that management was interested enough in
the program to provide a training session on the
writing of proper shapes, particularly when those
shapes looked like the characters they had always
written. Many others were motivated through
properly applied feedback where they knew that
the quality of their output was important to the
success of the system.
Most frequently, the motivation was in some
intangible form, such as the sincere desire to comply with a management plan, when that plan had
been presented to the employees in terms of the
benefit to be derived. Today, monetary rewards in
the form of bonuses and discounts are offered as
motivation in at least one application. However,
most forms of motivation discussed here cost only
a small amount of management time and effort,
but they produce handsome payoffs.
Training
Because of the limitless variety of character
shapes encountered in numeric handwriting, some
OOP#I//I
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2.. ). 1..
h b b bb 6
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3333333333339
11111111
5558~7f~~8gg
:?bb6,56(.66g gg
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55777777q9<19
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FIGURE 9-Exampl€.s of character degradation sequences'
limit must be imposed on the number of variations of a given character shape that will be allowed to define that character. Needless to say,
the greater the number of variations allowed for
any particular character, the more difficult and
costly it becomes to maintain sufficient separation
between the decision logic for that character and
the logics for all other characters in the set.
Figure 9 illustrates some common examples of
character degradation sequences, in which progressively more degraded forms of one character pass through a "twilight zone" and emerge as
progressively less degraded forms of another character. The few shapes on either end of the sequence are both human and machine sensible, but
those falling toward the center of the. sequence
cannot be confidently recognized, particularly
when they do not appear within a sequence that
limits the choice. The only way to limit the variations in handwritten character shapes that must
be handled by an optical reader is to motivate and
train the writer to exercise a reasonable degree
of care.in writing.
In developing the 1287, a practical compromise
was sought between recognition hardware complexity and the degree of care required of the
writer. Happily, a compromise was found which
requires relatively little conscious attention to
writing rules. The "model" character set chosen
as a handwriting "font" does not differ from the
normal character shapes taught in most grammar
schools. Furthermore, considerable effort was devoted to making allowances for the most com-
Design of OCR System for Reading Handwritten Numerals
1161
• Avoid linking characters.
• Avoid leaving gaps in line strokes.
• Write simple shapes without fancy strokes or
curls.
• Make loops closed and rounded.
monly ep.countered reasonable deviations from the
"model" shapes. For example, although the
"model" shape of the numeral (l.) does not show
a loop at the junction of the bottom stroke with
the upright stroke, a common variation of this
shape which does have a loop at the junction (~)
is accepted by the recognition logic.
Human factors' studies indicated that some
training would be beneficial to writers to help
them achieve an optimum writing style. The small
degree of constraint imposed, and the ease of
learning the "model" shapes (which involved little
more than a review of writing habits learned in
grammar school) led to the development of a
short, easy to understand self-instruction manual.
This training is easily given, including supervised
practice if desired, in less than 30 minutes.
The model shapes are shown on the top line of
the Any Store document in Figure 8. It may appear unnecessary to require employees, who will
be writing for direct entry into data processing
systems, to take instructions on how to form
handwritten numerals that are no different than
were learned in elementary school. However, the
primary purpose of the instruction was to impress
the writer with these five basic rules:
.
Feedback
The instruction session provides the. writer with
these basic rules and a feel for allowable deviations. Through immediate feedback during the instruction session he also receives an indication of
his initial performance. As in all servomechanisms
with feedback removed, the writer tends to become lax and sloppy if occasionally he does not
receive some word about his performance. As indicated earlier, the feedback provides a motivating effect in demonstrating to the writer that his
output has a bearing on the success of the total
system. ,From a practical standpoint, feedback in
the form of helpful hints from his supervisor will
tend to correct "open-loop eights," "thin-topped
nines," a tendency to write very light characters,
or any other individual quirk.
Another type of feedback is the computer-generated report card, a listing of error documents by
clerk or employee number. Table II is a relative
performance chart illustrating the importance. of
motivation, training, and feedback for machIne
recognition of handwritten numerals. This chart
shows only relative performance under the various
• Write the character, just filling the box (the
1287 can handle characters that are less than
half the height of the smallest recommended
box height) .
TABLE II-Relative reader performance as a function of motivation, training, and feedback
Level Of
Supervision
I
I
_1_
Very
Close
Level Of
Training
~ Detailed initial
.training and
continuing feedback
~ Detailed in~tial
training; early feedback only, probably
problem oriented
Initial training by
manual; little or no
feedback
A
r
Loose
to
Moderate
B
C
s
r
s
r
s
10
15
I
7.5
1
1
5
2.5
2.5
6
10
12.&
17.5
4
4
9
15
15
20
2.5
2.5
7.5
10
12.5
20
4
4
9
12.5
15 "
30
6
5
11
15
20
40
L9
1L
3. Low
2. Average
1. Very High
A
I
I
l
.J!L
Little,
B
I
4
5
.p
11
any.
C
7.5
15
I
11
i
15
I
25
15
I
20
I
30
II
I
50
75
!
1162 Fall Joint Computer Conference, 1968
combination of these factors. Each number may be
considered a reject and substitution rate multiplier in relation to the rates obtainable under the
most favorable conditions.
CONCLUSION
Any system involving the reading of handwritten characters is subject to a myriad of human
variables. It is impossible for even the most
sophisticated optical reader to compensate for all
of them if no control is exercised. As indicated in
Table II, the user frequently has the degree of
freedom to provide the environment compatible
with the system performance he desires.
Customer satisfaction with reading performance is highly variable with the application and
the degree of control that the customer has over
~¥7' -----11
I i I nT' I L
'!t---=-
ACKNOWLEDGMENTS.
--- - -- -- - l
'f ! t
4
\ /
I
the quality of his input. Character reject rates of
a fraction of a percent are achievable from input
prepared by unskilled workers on a routine job
in a controlled environment.
Figure 10 illustrates the range of character
shapes beyond the "model" shapes that are read
correctly by the IBM 1287 Optical Reader. Its significance is that the success of a handwriting
reader application can be greatly enhanced if the
reader is designed to read a broader range of
character shapes than what the writer is asked
to write.
In conclusion, it must be stated that the practi-.
cality of reading handwritten ;numerals by machine in a variety of industry applications is a
demonstrated fact by.virtue of wide customer acceptance. Its application in the future seems almost without limit.
I ' \ /: ~
The authors would like to acknowledge Mr.
Douglas C. Antonelli for his Human Factors contributions, and the many others from the Optical
Reader Development departments of the IBM
Systems Development Division Laboratory, Rochester, Minnesota, who helped develop the 1287
Optical Reader.
REFERENCES
)'
t>~ I~J
~ ~ It,"~'
"
,), 7
~!f
---....,--•.,~!IP,
,1)
-------_.......
7
l~ [~
It
&P
77
i, i~
l5
t ~
L
1
t ~
1
J
t. ~ ,
"'f~ ~
7 '1!" T
I~ 'ie Z
~ '{{!t;
X
1 DC ANTONELLI
Optical character recognition oj numeric handprinting
Case Studies and Results, IBM Rochester Minnesota (un,
published report
2 TLDIMOND
Devices for reading. handwritten characters
Proceeding of EJCC 232-237 1957
3 M N CROOK D S KELLOG
Experimental study of human factors for a handwritten numeral
reader
IBM J of Research and Development 7 No 1 January 1963
4 E C GREANIAS et al
I
I . .~. . . . . . . .~~. . .
il . .
FIGURE 100Range of character shapes beyond "model"
shapes that are read correctly by the 1287
The recognition of handwritten numerals by contour analysis
IBM J of Research and Development 7 No 1 14-21 January
1963
5 NSEZAKI HKATIGIRI
Character recognition by the follow method
IEEE Pf')ceedings 510 May 1965
The dynamic behavior of programs*
by I. F. FREIBERGS
McGill Univen;ity
Montreal, Canada
INTRODUCTION
A computer system consists of several resources for
which users' programs are competing: CPU time,primary and secondary storage and Input-Output devices.
More and more computer systems, which are being marketed currently, allow for resource sharing among
several jobs, in order to obtain a better utilization of all
available equipment, or to provide better service to the
users by reducing their job "turnaround" time, or both.
Some of the approaches tried so far in order to
achieve these aims are:multiprogramming, as in Univac 1108, IBM 360,
i.e., the sharing of core memory by several users'
programs;
remote-access computing via teletype-like terminals, as in the RAX system on IBM 360, or Dartmouth College's time-sharing system on GE265,
i.e., "slicing" of the CPU's time between the terminal users;
on-demand paging. Only the active parts of programs, or pages, are kept in core memory, a.s in
CDC3300, SDS940, IBM 360/67, GEM5. This is
achieved by dividing up the available core memory
into blocks of a certain size. Blocks of storage
might then. be allocated to program pages on an
"on-demand" basis.
The performance of the above three types of systems
becomes difficult to estimate, as compared to batch processing systems, since each program can no longer be
considered per se, but is heavily dependent on the
priority and scheduling rules of the operating environment, as well as on the type and volume of other programs to be processed. In time-shared systems, the performance will also be influenced by the size of the timeslices and by the resulting systems overhead for pro*This research was supported by the National Research
Council of Canada through Grant A-4081.
1163
gram swapping between core and auxiliary storage. In
paged systems additional performance parameters are
introduced by page size and page turning strategies.
Such systems are generally considered to be too complex and non-deterministic in nature for analytical
study methods. The alternative for studying these systems is simulation, validated by subsequent 'direct
measurement.
As an exception, it must be pointed out that remoteaccess low speed terminal systems have been studied by
queueing theory. A summary of the models and the
measures used is available.1 Simulation models of
remote-access systems have also been developed, at
MIT,2 and at SDC.3
Multiprogramming on Univac 11074 as well as an
IBM 7094/44 directly-coupled, system 5 have been
simulated.
The IBM 360/67 system has been simulated at
Stanford.6 Paging strategies have been investigated at
IBM, both experimentally using the M44/44X system,7
and by simulation.s
In all such models, and particularly in ones dealing
with page-turning, crucial assumptions have to be made
about the dynamic behavior of prograIlJs under execution, in particular about .frequency of references to data
in memory, and about the distance between successive
instruction and data fetches. It has been said that
page-turning can be either very useful or disastrous, depending on the type of program to which it is applied. 9
Up to now, few direct investigations have been carried
out, and performance estimates of systems, such as the
IBM 360/67, were based on certain theroretical assumptions about the behavior of compilers and of the users'
programs of different classes. Recently, at SDC a study
of actual memory requirements and simulated page demand rates has been carried out for a fixed page size of
1024 words on some interpretive type programs (LISP,
META5), with some interesting conclusions.10
In the Spring of 1966 it was decided to obtain em-
1164' Fall Joint Computer Conference, 1968
pirical data about the dynamic behavior of programs,
typical to McGill University Computing environment,
from the point of view of CPU time and memory utilization.
The data thus obtained would also be used as input to
subsequent simulation studies about varioUs paging and
scheduling strategies.
Method
A trace-like program was developed for the IBM 7044
which executes interpretively any program, instruction
by instruction, recording for each the operation code
and the actual address of the instruction. For instructions referencing data in memory, the actual address of
tJ:1e data word was also recorded, together with an indicator as to whether it was a data fetch or a data store.
Supervisor calls (SVC) were not executed interpretively, since it was felt that the design philosophies behind supervisor routines would diff-er too widely, so that
the IBM 7044 supervisor routines would not have a sufficient degree oJ generality for subsequent study of other
systems. Instead, the entry point in the supervisor was
noted, and the time spent in the supervisor was measured in clock pulses of 1/60th of a second each. From
the entry point it was then possible to determine the
type of SVC which caused the suspension of program
execution. Most of the SVC's occurred for input or output (I/O) operations.
Since the programs Investigated were not specifically
organized for execution with paging, dividing the core
memory into 32 equal size pages of 1024 words regardless of program organization would result in an overestimation of page bO,undary crossings. For this reason a
memory map, or layout, was taken for each program
investigated, indicating _its functional parts, namely
the regions occupied by thesupervispr, the input-output control blockS' and buffers, the problem program,
its subroutines, system-suppIled subroutines, common
data areas, etc. Memory was then subvided into a
variable number of pages of 1024 words or less, but
making sure that each functional part begins on a new
page boundary. Table I shows a typical memory layout
with page allocation. Since any program would cons'st
of the above funct:onal parts, regardless of the computer system used, it was felt that the results of this
investigation would be of more general value, beyond
the IBM 7044 memory organization.
The output of the trace-like program was recorded on
magnetic tape, and was subsequently analyzed and
summarized by an analyzer program.
After various attempts, the best way to summarize in
TABLE I-Memory layout of an in-corP Fbrtran'compiler
No.
PAGE
DESCRIPTION
SYMBOL
PAGE ADDRESS
PAGE SIZE
(WoRDS)
(IN OcTAL>
START
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
FILE CoNTROL
CoNTROL PGM
CoNTROL PGM
LOADER
LOADER
loADER
LOADE~
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
BUFFER
F
C
C
L
L
L
L
P
P
P
P
P
P
P
P
P
P
P
P
B
END
14323 14467
16113 20112
20113 21201
21202 23201
23202 25201
25202 2n01
27202 30004
30005 32004
32005 . 34004
34005 36004
36005 40004
40005 42004
42005 44004
44005 46004
46005 50004
50005 52004
52005 54004
54005 56004
56005 60000
76122 77776
101
1024
567
1024
1024
1024
387
1024
1024
10211 .
1024'
1024
1024
1024
1024
1024
1024
1024
1020
941
pictorial form the information obtained was found to be
a series of "Snapshots" of memory between successive
supervisor calls. Typical output of the analyzer program
is shown in Table II, which shows the sequence of steps
for an in-core Fortran compiler.
TABLE II-"Snapshots" showing memory utilization between
successive SVC's for an in-core Fortran compiler
I1&...lL
FCC L L L L P P P P P P P P P P P P B*
P Fl ••• S •••••• I • • • • • •
MSEC •.
0
.SG . . . . PPP .. psP.P . . .
16
PSS . . . .PSS .. PS .. G . . .
1
PSS . . . . PFSP.PS .. G .. G
2
PSS •••• PF •••••• : ••• P
1
PSS . . . . PIS . . . . . . 6 .. P
1
PSS·•••••• F ••••••••• P
1
PSS •••• PIS •••••• G •• 6
1
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSSPPS .. P .. G
7
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSS.S . . . G .. G
4
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSSSSP .. P .. G
9
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSSSSP .. P .. G
10
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSS.SS .. P .. G l l
PSS •••••• F • • • • • • • • • P
1
PSS • • • • PSSSSSS • • P • • G
19
PSS •••••• F • • • • • • • • • P
1
PSS . . . . PSSSIS . . . P .. G
2
PSS . . . . PSSFPPSSSS .. P
62
.P • • • • • • • • • GGP.SS •••.
34
.G • • • • • • • • • GGG.SS •••
18
.G • • • • • • • • • GGG.SS...
5
.P • • • • • • • • • • • G.SS...
2
PSS • • • • • • • • • • • • SF...
1
PSS • • • • • • • • • • • • • • • • G
1
.l.tmR.B.uill.
~
LOAD
110
GET
PUT
PUT
PUT
GET
PUT
GET
PUT
GET
PUT
GET
PUT
GET
PUT
GET
PUT
GET
PUT
GET
PUT
PUT
PUT
PUT
PUT
PUT
GET
TYPE
C, OCK
PULSES
165
o
o
1
o
o
o
o
o
1
1
o
o
1
o
o
o
o
o
o
o
o
1
o
o
o
o
o
23
* SYMBOLS FOR PAGE IDENTIFICATION AS PER TABLE I.
A header line identifies the pages of each functiona.l
part of the program. Each snapshot line begins with a
layout of memory, split up into pages as described
above. The meanings of the symbols used in the snap-
Dynamic Behavior of Programs
shots are (for each page) :
page not used during this interval
I Instructions fetched
F Instructions and data words
Page content
fetched
unchanged
G Data words fetched
P Data words stored and fetched
S Instructions fetched and data
words stored and fetched
Page content
changed
N ext the time (in msec.) spent in uninterrupted com~
putation before the SVC occured is given . .The average
instruction time for the IBM 7044 was found to be 4.4
microseconds. Finally, the reason for the supervisor call
is indicated with the number of clock pulses spent in the
supervisor before program execution was resumed.
Snapshots were chosen between successive SVC's
rather than for a fixed number of instructions, because
at each SVC the scheduling algorithm has the option of
deciding whether to continue with the present program
or to switch to a different one.
Results
A summary of the classes of programs investigated so
far is shown in Table III. This table also shows a percentage breakdown by type of instruction within each
cla~s of programs. Of interest here is the 34% average
proportion of branch instructions, which may result in
references to instructions on a different page in memory.
Also of interest is the 51 % average ratio of data words
to instruction words.
TABLE III~Classes of programs investigated
1165
instance in the IBlY! 360 with 16 general purpose registers, as opposed to 2' Arithmetic registers and 3 Index
registers in the IBlV[ 7044, the proportion of instructions
referencing data in memory was expected to be reduced
in favor of more register-to-register type instructions.
To verify this some IBM 7044 programs were rerun
with 360 Fortran G and Cobol F. The p'(rcent increase
in the proportion of R type instruction was found to be
between 40% (Fortran) and 340% (Cobol). The percentage of B type instructions was decreased between
56% (Fortran) and 64% (Cobol) to compensate for this.
The proportion of branch instructions for which the
branch is taken was found to be around 90% on the 360.
The instruction tjmes obtained in this investigation can
then be adjusted accordingly.
By comparing the "snapshots" of the various programs investigated, several results emerge.
A program does not execute very many instructions
between successive SVC's. This is illustrated in Figure
1, which shows the cumulative percentage of the number of SVC's vs. the number of instructions executed
between successive SVC's. For most classes of programs
50% of the time this number lies somewhere between
100 and 1000 instructions, i.e. less than 5 msec.
Figure 2 shows the cumulative percentage of SVC's
vs. the number of instruction pages required between
successive sve's. It can be seen that this stabilizes
around 2 to 3 pages, except for the in-core Fortran
compiler which requires 5 pages most of the time.
Data page requirements are higher than those for
instruction pages and practically coincide with total
page requirements. This is illustrat'ed in Figure 3. Most
programs need 4 to 6 data pages between successive
SVC's with the execption again of the in-core Fortran
compiler, which requires between 5 and 12 data pages.
100
CLASS OF
PROGRAM
FORTRAN ExECUTION
(11 PROGRAMS)
TOTAL No, OF
I NSTRUCTI ONS
TRACED
(IN MILLIONS)
4,02
PERCeNTAGE OF DIFFERENT
TYPES OF I NSTRUCTI ONS
----------------------------------G (X)
P (X)
R (X)
36
20
11
B
(Xl
33
RATIO OF
DATA \lORDS
To I NSTRUCTI ON
WORDS (X)··
57
,28
1',29
LIST PROCESSING
(SLIP)
1.13
FORTRAN COMPILATION
IN-CORE COMPILER
(7 PROGRAMS)
1.74
28
22
14
36
54
CoBOL EXECUTION
1.89
28
15
14
43
45
29
22
15
34
51
MBA6E
I
-
.
III)
0
38
28
26
STRING PROCESSING
SIMULATION (GPSS)
FORTRAN
80
~STRIicTiONS REQUIRING A DATA WORD FETCH IN MEMORY,
NSTRUCTIONS REQUIRING A DATA WORD STORE,
NSTRUCTIONS REFERRING TO REGISTERS ONLY,
ANCH, OR JUMP, INSTRUCTIONS,
• AVERAGE INSTRUCTION TIME FOR IBM 7044,
•• DATA WORDS G+P+I'!OVE INSTRUCTIONS
23
27
23
15
20
19
24
25
32
61
55
49
!~
MICROSECONDSl·
MICROSECONDS
MICROSECONDS
MICROSECONDS
>
III)
80
I&.
0
.,.
40
20
O~
__
D2
____
~
J
~
____
.3
____
(
INSTRUCTIONS ( IN 1000)
L ____ ~
__ la __
~
~~
4.5
1.1
TIME
The percentages of Table III will vary somewhat, depending on the instruction repertoire and on the number
of registers available in a particular computer. For
~
IN
MSEC
20,
~~
~
80
)
FIGURE I-Cumulative frequency of the number of instructions executed between supervisor calls
1166 Fall Joint Computer Conference, 1968
100~--------~~-=======--=~----------
100r-----:-----------------======t
80
USERS
PROGRAMS
ONLY
80
COMPILATI
LIST
60
PROC.
...
o
60
en
40
'It
u
>
en
!+-~HI--- SIMULATION
II.
0
o
4 ,
~
10
6
PAGE
REQUIREMENTS
(1024
12
14
16
18
WORDS)
FIGURE 4-Cumulative frequency of the total number of
pages required for a 127 job sample at McGill University
o
4
2
NO.
OF
6
INSTRUCTION
8
PAGES
12
(1024 WORDS)
FIGURE 2-Cumulative frequency of the number of instruction pages required between supervisor calls
100r-------------r--r----------~----~_===
80
II)
60
~
...o
40
r
20
o
I
8
NO.
OF
TOTAL
PAGES
(1024
10
12
14
WORDS)
FIGURE 3-Cumulative frequency of the total number of
pages required between supervisor calls
In order to obtain an estimate about the total
memory requirements of the class of jobs processed by
the McGill Computing Centre, all the jobs submitted
during a certain 24 hour period were examined. For 127
of these jobs which reached the execution phase, a
memory layout was obtained. The results of the analysis are shown in Figure 4, i.e., the cumulative percentage
of the number of jobs vs. their total memory requirements (for the entire duration of the job).
It can-be seen that 50% of the jobs require less than
7 pages, made up as follows: Problem program including its subroutines 3 pages
2 pages
System supplied subroutines
1 page
I/O Buffer areas
1 page
Common data area (for larger programs)
DISCUSSION
Contrary to the popular view, long compute sequences
without any interruption seem to be the exception
rather than the rule. The number of instructions executed betweed supervisor calls is of the order of 102 to
103 • Since most of the SVC's are due to I/O requests, assuming a blocking factor of about 10 with a fully overlapped I/O channel operation, return to the interrupted program could be immediate in 9 out of 10 cases.
This would result in a sequence of 103 to 104 instructions
(5 to 10 msc) about 50% of the time.
On the other hand, the corresponding memory requirements appear to be larger than generally expected, in agreement with the SDC study.lo They are of
the order of2 to 3 instruction pages and 4 to 6 total
pages. An exception here is the Fortran Compiler whose
page requirements are about twice as large.
From these considerations it seems clear that the systems overhead for a "one-page-on-demand" strategy
would be prohibitive. To avoid this, at least 3 pages for
instructions and data, plus one page for I/O buffers,
plus 2 pages for systems supplied subroutines (which
could be shared code) should be made available to any
program at the outset, as well as during each successive
period of activity.
From Figure 4 it can be seen that such a memory assignment policy would accommodate the entire program of 50% of all jobs entering the execution phase,
so that there would be no further paging overhead for
the entire duration of these jobs.
Dynamic Behavior of Programs
Another question worth ralsmg at this point is
whether the additional· cost of implementing a fixed
page size hardware system is warranted, as opposed to a
multiprogrammed system where the entire program is
brought into memory.
These costs should also be weighed against those of
acquiring more Large Capacity Storage, especially in
view of the large memory requirements of Compilers.
1167
utilities
Proc 22nd ACM Nat Conf pp 85-96 August 1967
2 ALSCHERR
An analysis of time-shared computer systems
Research Monograph No 36 The MIT Press Cambridge Mass
1967
3 G M FINE P V McISSAC
Simulation oj a time-sharing system
Mgt Sei 126 pp B18Q--B194 February 1966
4 G K HUTCHINSON J N MAGUIRE
Computer systems design and analysis through simulation
SUMMARY
In this paper the results obtained from an interpretive
instruction by instruction execution of different classes
of programs (Fortran compilation and execution, Cobol,
GPSS, SLIP) on an IBM 7044 have been presented.
Memory and CPU time requirements between
successive supervisor calls have been analyzed, with the
outcome that most of the time instruction sequences
are rather short and more than one page (1024 words)
of memory is required.
The data obtained can be used as realistic input to
simulation models of multiprogrammed or fixed page
size computer systems.
REFERENCES
1 G ESTRIN
L KLEIN ROCK
M ecuures models and meaaurement8 for time-shared comfYlJlm
Proe of the 1965 Fall Joint Computer Conf pp 161-167 1965
5 JHKATZ
Simulation of a multiprocessor computer system
Proe 1966 Spring Joint Computer Conf pp 127-139 1966
6 NRNIELSEN
The simulation of time sharing systems
Comm ACM 107 pp 397-412 July 1967
7 RWO'NEILL
Experience using a time sharing mult~programming system
with dynamic address relocation hardware
Proe 1967 Spring Joint Computer Conf pp 611-622
8 LABELADY
A study of replacement algorithms for a virtual-storage computer
IBM Sys J 5 2 pp78-1011966
9 J B DENNIS E L GLASER
The structure oj on-line information processing systems
Proe of the 2nd Congress on the Information System Seiences
p61964
10 G M FINE C W JACKSON P V McISSAC
Dynamic program behavior under paging
Proe of the 21st ACM Nat Conf pp 223-228 August 1966
Resource allocation with interlock detection
in a multi-task system
by JAMES E. MURPHY
International Business Machines Corporation
Poughkeepsie, N ew York
INTRODUCTION
In a multiprogramming environment, special care must
be taken to insure that, for a given physical record on a
data set, only one task at a time is involved in the following sequence:
1)
2)
3)
4)
Read the physical record (with update in mind);
Find the logical record to be changed;
Change the logical record;
Write the "new;' physical record.
. For example, suppose there exists on a (direct access)
data set a physical record, R, consisting of the logical
records A, B, C, and D, and that there are two programs, PI and P 2 , contending for the resources of the
system.
Suppose further that the following sequence of events
is allowed to take place:
1) PI reads R and obtains A, B, C, D in its buffer;
2) P 2 reads R and obtains A, B, C, D in its buffer;
3) PI changes A so that its buffer contains A,l B: C,
D;
4) P 2 changes D so that its buffer contains A, B, C,
Dl;
5) PI writes the "new" physical record so that
Rl=Al,B,C,D;
6) P 2 writes the "new" physical record so that
Rl = A,B, C,Dl.
As a result of P 2'S action, the update to the data.set
made by PI has been erased as though it never existed.
Any recovery via an audit trail at a later time would
duplicate this error. This example demonstrates the
general need for protecting the integrity of system resources and insuring validity of the work done by the
resources' users.
1169
There are three degrees of protection required by resources and their users in a multiprogramming environment. These are:
1) If a resource is to be altered by a task, then the entire sequence of events essential to the alteration
of the resource must be protected from any interference which would affect the completion of the
change.
2) If a task is using a resource but not changing it,
then that task requires protection against any
changes in the resource which would affect· the
validity of the information the task receives from
the resource.
3) If a task uses a resource without changing it, then
no protection is required when changes to the resource do not affect the ultimate use of information received from it, and the task in no way
interferes with other users of the resource.
All tasks wishing to use a resource seek control of it
by name through a resource management facility. Requests for a given resource are queued on a first-in,
first-out (FIFO) basis. The concepts of shared (S) vs.
exclusive (E) control are used. Any number of tasks
may use a resource simultaneously if they have all requested shared control. A task requesting exclusive control will be the only task using the resourse once it
gains control (except for those tasks falling into category (3) above). Tasks coming under category (1)
would request exclusive control; tasks in category (2)
would request shared control; and tasks in category (3)
would use the resource with-out requesting control.
Embedded in the typical approach to resource allocation, however, are certain rigid constraints designed to
avoid all possibility of system interlock:, i.e., the situation in which two or more tasks place each other into a
permanent wait state.
Suppose that a task is allowed to request control of a
resource without releasing control of another resource
1170
Fall J'oint Computer Conference, lU68
it has previously obtained. Here the expression "enqueue" (ENQ) will refer to the requesting of a resource,
and "dequeue" (DEQ) will mean the releasing of a resource (both actions performed through queue manage,:"
ment).
Assume the following sequence of events, where P l
and P 2 are programs running concurrently in a multitask system and Rl,R 2are resources:
a) P l ENQ's Rl for E (exclusive control);
b) P 2ENQ'sR 2forE;
c) P 2ENQ's Rl for 8 (shared control);
(At this point P 2 is placed in a wait state);
d) P l ENQ's R2 for 8 (Now P l is placed in a wait
state).
The queues for Rl and R2 would appear thus:
FIGURE 1
Now P l and P 2 are each waiting for a resource which
the other holds. Under these conditions both programs
would remain inactive until one or both were terminated by control programming, either through a timeout mechanism or other such safeguard.
Interlocks can occur only if a task is allowed to wait
for a resource without releasing all resources it previously controlled. However, this is only a necessary
and not a sufficient condition for interlock. Usually, resource control is handled as though the two conditions
were equivalent, and tasks must request multiple resources in parallel or in some pre-defined sequence.
This paper discusses a more flexible resource management which examines each request in the context of all
currently pending requests and determines the existence
or absence of an interlock.
Queue management
For each resource, maintain a queue cont,aining the
name, mode, and rank for each task which hasrequest~d
control of the resource but which has not yet released It.
Within this queue:
TA8K NAME identifies the task requesting use of
the resource.
MODE refers to the type of control desired-"E" for
exclusive, "8" for shared.
RANK indicates the task's relative position in the
queue. This is assigned as follows:
A) Enqueuing
1) The first task in the queue is assigned control
of the resource in the desired mode, and is
assigned a rank of of that resource.
2) If the new task requests mode 8 and the mode of
the last task in the queue was also 8, then the
rank of the new task is equal to that of the old.
Otherwise, the rank of the new is one greater
than that of the old.
3) If its rank in the queue is 0, then the task may
use the resource without waiting for another
task to finish with it.
4) If its rank is not 0, the task's request for the
resource must be set aside for analysis of inter1ocks.
5) This same procedure is followed for each of the
resources requested simultaneously by the task.
6) Interlock analysis is now performed. The algorithm and the procedures followed when an
interlock is detected are described later in this
paper.
7) If the task is allowed to wait for the requested
resources without releasing those it already controls, its name, rank, and mode are entered in
the resource queues. In this case, the wait count
of the task is increased by one for each resource
for which it has a rank greater than zero.
°
B)
Dequeuing
If a task releases control of a resource, then:
1) The name of the task requesting a DEQ is
removed, along with its mode and rank, from
the queue, for the specified resource.
2) If there are other tasks in the queue having
rank zero, or if the queue is empty, the dequeuing process is finished.
3) The rank of each task in the queue is decremented by one, and the wait count is decremented by one for each task whose rank is now zero.
4) When the wait count for a task is zero, it is removed from the wait state and proceeds sharing
or c~ntrolling resources in the requested mode.
Example: Let us suppose the following
requests occurs for resource R.
1.
2.
3.
4.
5.
seque~ce
of
Task B requests exclusive control
Task C requests shared control
Task A requests shared control
Task D requests exclusive control
Task E requests exclusive control
At the end of this time, the entries on the queue for
Resource Allocation with Interlock Detection
resource R would be:
NAME
MODE
RANK
B
E
0
C
S
1
A
S
1
D
E
2
E
E
3
FIGURE 2
When task B releases R, the entries become:
NAME
MODE
RANK
C
S
0
A
S
0
D
E
1
E
E
2
FIGURE 3
"Waits-for" as an ordet telation
Definition: Let the symbol, Pi;' represent the rank of
task T j on the queue for resource R ,.
Definition: IfPa ,> Pajforsomea, 1 ~a ~m where m
is the number of resources being used in the system,
then taElk T i waits for task T j to finish with resource R a •
The expression T i~ T j is defined to symbolize this relationship.
If T i waits for T j to finish with resource "a" and T j
waits for Tk to finish with resource "b", then we have
Ti~Tj and Tj~Tk' or Ti ~Tj ~ T k. Clearly T,
waits for T k to finish with resource Rb because the
minimum length of time T i must wait for resource Ra is
the length of time during which T j controls resource Ra
plus the length of time during which T k controls resourc,e R b • This might be expressed in the form
Tia~Tk'
However, in this paper we are only indirectly concerned with the resources for which a task waits. Our
main interest here is that a task must wait. To determine for which other tasks a given task is waiting, re-
1171
quires knowledge of the resources involved. In line with
this, make the following definition:
Let T i and T j be any two tasks currently resident in a
multi-task system. Then say that Ti waits for Tj, expressed T i > T;, if and only if there exists a series of
resourses, rk, 1 ~k ~m, and a series of tasks, 1\, 1 ~h
~m -1, such that Ti ~Tl ~ .. ~Ta ...~rmTj.
Lemma: The relation "waits-for", ">", is transitive
and is an order relation.
Note: Transitivity of the "waits-for" relation may be
proven formally by introducing the variable, T, for time.
Of significance here are the times when a task gains control of a given resource, when it releases the resource,
and when the task gains control of the last resource for
which it is waiting.
Definition: A (system) interlock is said to occur if there
is a task, To, related by competition for resources to
other tasks, T i , in a system such that a chain of wait-for
relations To> Ti ...T m > To exists.
Matrix reptesentation of "waits-fot"
The ordering of the set, T, of the n tasks in a system
by the relation ">" may be portrayed in an 'n x n
matrix, W, the Wait Matrix, constructed as follows:
Let the n columns and the n rows be named by the
tasks in the system, To - Tn _ 1. Let the elements
W ij be assigned the value 1 if T i has a rank higher
than that of T j on the queue for any resource R-i.e.
T i ~T j. If there exists no resource, R, for which
T i ~Th then let W ii = O. Note that the elements
along the main diagonal are all zeros.
Consttuction of the ptecedence matrix
For a more complete, and more complex, model of the
task-resource system, construct a matrix, P, (the precedence matrix) as follows. Let the n columns be named by
the tasks in the system, To - Tn _ l' Let the rows be
named by the ill different resources currently being used,
Ro - Rm - 1. Let the m x n elements of the matrix
Pij = (Ri, T j ), each contain the rank (or place) on the
queue for Ri which has been assigned to task T j •
Clearly many of the elements will be empty (blank or
null, as opposed to zero.)
Going across any row i, corresponding to resource R i ,
we find an entrw in column j, corresponding to every
task T j which is in the queue for R i . A zero in
column k of row i indicates that task T k has control of
resource R i. Multiple zero entries in row i indicate that
several tasks share control of that resource. Duplicate
non-zero (and non-null) values indicate tasks whicJ:t will
share control at a later time. Similarly Pik < P ij indi-
1172
Fall Joint Computer Conference, 1968
cates that Tk is ahead of T j in line and that T J will have
to wait for T k.
Going down any column j, corresponding to task T j,
we find an entry in rows h, ... ,i e corresponding to every
resource Ri which T j controls or for which it is queued
and waiting. An entry (rank) of zero in row k of column
j indicates that task T j now has the use of resource R k.
N on-zero (and non-null) entries in column j indicate
those resources for which task T j is waiting.
To
T
T2
T3
To
0
0
0
0
Tl
1
0
0
0
T2
0
0
0
0
T
0
1
1
0
3
Illustrations
FIGURE 6
Assume a system with four tasks, To - T s, and six resources, Ro - RI), with all queues initially empty, and
that the following sequence of requests has been processed by queue management:
1) To request E for Ro and S for RI);
2) Tl requests S for R o, Rs, and RI);
3) T 2 requests E for Rl and R 2 , and S for Ra;
4) Ts requests E for R a, R 4, and R 5 •
5) To releases R 5 •
At this point, the queues for the six resources are
shown in Figure 4.
SOURCE
Ro
MODE
E
S
E
E
RANK
o
1
o
0
S
S
E
ESE
o
1
0
0
1
FIGURE 4
Figure 5 summarizes the state of the system in a precedence matrix. In Figure 5, two tasks, To and T 2 , are
not waiting for any resources and are able to process.
Tl is able to process when Tl releases Ro. T a, however,
must wait to process until both T 1 and T 2 releases Ra
and T 1 releases RI)'
RO
TO
Tl
0
1
T2
Rl
0
R2
0
R3
0
0
T3
The-wait matrix is shown in Figure 6.
Interlock detection
To demonstrate the interlock detection procedure,
continue with the system described in the previous section, using the state of the system shown in Figures 4
and 5.
Starting at this point, we will examine two cases as
To requests a resource. In each case, To must wait for a
resource to become available while another task is able
to continue processing and To and the remaining two
tasks are in a wait state. In one case, as resources are released by the task which is running, subsequent tasks
are able to process. In the second case, if the request
were to be honored, the remaining three tasks would still
be in a wait-state once the task which was still running
released its resources. In this situation, only a new task
could run, and it could only continue so long as it demanded no resources held by any of the th:r;ee totally
interlocked tasks.
Case 1: Suppose To asked to share R 2• Figure 7 shows
the resulting resource queues, and Figure 8 shows the
new precedence matrix. ("A" indicates the affected
entries.) The significant steps in determining if the request may be honored and To allowed to wait for R2 are
as follows:
a)
b)
c)
d)
To ~ T 2;
T 2 ::J> Ti for any value of i;
To~Tiforanyi~ 2;
To ~ Ti for any j ~ 2.
Thus there exists no sequence To >... > To, and
the request may be honored without fear of interlock.
1
RESOURCE
Ro
MODE
E
S
E
E
S
SSE
RANK
o
1
o
0
1
0
0
R4
RS
1
0
FIGURE 5
1
FIGURE 7
E
S
E
010
0
1
Resource Allocation with Interlock Detection
Ro
To
Tl
0
1
T2
T3
~1
R2
0
0
0
R3
1
0
R4
1
0
R5
FIGURE 8
Case 2: Suppose that, instead of R2, To requests
shared control of R 4 • The resulting resource queues and
the precedence matrix are described in Figures 9 and 10.
("t:." indicates those entries which are new).
Significant steps in concluding that the request can
not be honored follow and are keyed to the arrows in
Figure 10.
a)
b)
c)
d)
e)
To~Ts;
Ts is waiting for control of Rs;
Ts ~3 T 1 ;
T 1 is waiting for control of Ro;
Tl ~ To.
RESOURCE
R0
Rl
R2
R3
Thus there exists a sequence To> ... > To and the
request must be denied. In this case the wait-chain is
To > Ts > Tl > To. 1£ To were allowed to wait for
without first releasing Ro, the tasks To, T 1, and Ta
would be in a permanently interlocked wait state.
Since there is only one new resource requested and
one old resource being held, no further paths need be
followed. Note that there is an alternate branch which
parallels the first path, but which does not lead to any
new knowledge.
For a sinlpler view of the interlock, use the wait
matrix shown in Figure 11. Scanning across the row
from To, we find that To > Ts. Scanning across Ts's
row, we find Ts > T 1 • Scanning T1's row, we see that
Tl > To. Thus To > Ts > Tl > To, and an interlock
exists.
It is apparent from even this simple example that an
algorithm using the wait matrix would be far simplef to
implement and use than would one based on the precedence matrix. However, since the information which
can be provided with the wait matrix (i.e., whether or
not an interlock exists) is only a subset of the information available by using the precedence matrix, this discussion will concentrate on the latter.
R:
0
Rl
1173
The detection algorithm
R4
R5
TASK NAME
To
Tl
MODE
E
S
T2
E
T2
E
Tl
S
T2
S
T3 T3 ToA Tl
E E S
S
RANK
0
1
0
0
0
0
1
0
1
0
T3
E
1
The algorithm to trace through the chains of waitrelations in the precedence matrix may be regarded as
making a series of horizontal and vertical movements
through the elements of the matrix. If a valid series of
movements leads back to the column from which the
series began, then an interlock has been detected.
The rules governing movements through the matrix
are as follows:
1) Searching for positions to which to move is done
FIGURE 9
To
Ro
O~
T2
Tl
--Cef'l
",-'1\
Rl
' II
'/(d)
R2
I
R3
/0
I
R4
R5
T3
down columns from the top and from left to
right along rows.
2) Movement alternates in direction. A position
occupied via a horizontal move must be vacated
by a vertical move and vice versa.
I-A··
I
\
\O~ -
Tl
T2
T3
0
0
0
1
Tl
1
0
0
0
T2
0
0
0
0
T
0
1
0
0
T
0
J~_ -0- c)
-1
-----
To
0
~( b)
-(~ >o~
--
FIGURE 10
J
-I'"
0
3
FIGURE 11
1174 Fall Joint Computer Conference, 1968
3) Movement along a row (within the queue for a
resource) can be made only to a position having
a (non-null) place-value (rank) less than that
of the position the algorithm currently occupies.
This locates a task in the queue ahead of the
task whose column is now being occupied
4) Movement down a column through the list of resources contended for by a task can be made to
any position having a non-zero (and non-null)
place-value. This locates resources for which
the task whose column is occupied must wait.
5) If, during a horizontal move, the column corre, sponding to the original task is reentered, an interlock has been found.
6) A sequence of moves stops when an interlock is
found, or when no position is open in the specified
direction.
7) A new sequence is started at those points from
which multiple paths lead.
To insure that all moves are taken before vacating the
spot currently held, all positions which may be oecupied
next are selected and their coordinates saved for later
use. In the list with the coordinates of these "next"
positions is placed the direction in which movement will
be made.
When all the "next" moves from a position have been
listed, the position is vacated and a new one taken from
the list of "next" positions. The jobs is complete when
the' 'next" position list is empty.
Describe the precedence matrix as a two-dimensional
array indexed by the variables Rand T, with each element of the matrix consisting of three entires:
1) P, the rank of task T on the queue for resource R;
2) H, the row flag, turned on to show that this element has been accessed horizontally:
3) V, the column flag, turned on to show that this
element has been accessed vertically.
Define the "NEXT list as a last-in, first-out stack,
indexed by the variable i, having the entries:
1) RNEXT, to save the R-coordinate of selected
elements of the precedence matrix
2) TNEXT, to save the T -coordinate of selected
elements of the precedence matrix
3) NEXTMOVE, containing "H" or "V", depending whether the direction of move~ent from this
entr.y is to be horizontal or vertical when its coordinates are selected from the NEXT list.
With all indexes, assume a value of 0 to reference the
first element.
It is assumed that, prior to entering the analysis
routine, queue management has:
1) Checked that analysis is really needed in that:
a) At least one resource was already controlled by
the task; and,
b) At least one of the newly requested resources
has been assigned a rank higher than zero;
2)
3)
4)
5)
Stored the number of tasks in TMAX;
Stored the number of resources in RMAX;
Constructed the matrix;
Stored the column number corresponding to the
requesting task in TINIT (0 ~ TINIT ~ TMAX
-1);
6) Stored the row number corresponding to anyone
of the resources already controlled by the requesting task in RINIT (0 ~ RINIT ~ RMAX
-1).
RESOURCE
Ro
TASK NAME To
Ta Ta T2
Ta
MODE
E E S
E
101
1
RANK
E
1
FIGURE 12
Example
Suppose the request in Case 1 of Section VII has been
made (and validated) and the state of the system is
as shown in Figures 7 and 8.
Assume that T 2 now requests shared control of R 4 •
The new queues and precedence matrix are described in
Figures 12 and 13.
o
1
o
o
1
o
o
o
1
1,6.
0
1
FIGURE 13
In this case it is obvious that ali interlock exists,
because no task remains in a run condition. However, as
Resource Allocation with Interlock Detection
WHEN
ADDED
TO
LIST
RNEXT
TNEXT
NEXTMOVE
WHEN
REMOVED
(2)
4
2
H
(4)
(S)
4
3
V
(7)
(9)
3
3
H
(21)
(10)
S
3
H
(11)
(12)
S
1
V·
(13)
(14)
0
1
H
(1S)
(16)
0
0
V
(17)
(18)
2
0
H
~19)
V
(24)
(22)
3
1
FIGURE 14
has been shown in previous examples, an interlock can
exist even though another task is running.
Since T 2 must wait for a resource and already controls
other resources, analysis is needed.
Now queue management sets TINIT = 2, TMAX =
4, and RMAX = 6. Figure 14 traces the maintenance of
the "next" list. The numbers in Figure 14 are keyed to
the following text which outlines the algorithm as it
processes the matrix (Figure 13);
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
The column under T 2is scanned.
An open position is found in the row with R 4.
No further entries in column 2.
Latest entry taken from "next" list.
Row 4 scanned, with an entry found in column 3.
End of Row 4.
Latest entry taken from "next" list.
Column 3 scanned.
Entry found in Row 3.
Entry found in Row 5, then end of row.
Latest entry taken fronl "next" list.
Row 5 scanned, with the only entry in column 1.
Latest entry taken from "next" list.
Column 1 scanned, with only eligible position in
RowO.
15) Latest entry taken from "next" list.
16) Row 0 scanned, with an eligible position in
columnO.
17) Latest entry taken froJ)l "next" list.
18) Column 0 scanned, with an eligible position
found in Row 2.
19) Latest entry taken from "next" list.
20) Row 2 scanned, with the only open position
found in Column 2, corresponding to TINIT. The
routine enters "2" in the message list for queue
management.
1175
21) Latest entry ta.ken from "next" list. (In this case,
the only one left in the list is the entry placed
during step 9.)
22) Row 3 is scanned, and the first valid next position found in column 1. This entered in the
"next" list.
23) Continuing the scan of row 3, another valid
next position is found in column 2. Since this
corresponds to the requesting task, the row number (3, for Rs) is placed in the message list for
queue management.
24) The next entry is taken from the "next" list.·
25) This entry indicates that the position in row 3,
column 1 is to be occupied and a vertical scan
made. However, the vertical flag in this position
was set during the process implied in step 14.
Therefore the entry is discarded.
26) The "next" list is empty and the process in complete.
27)R2 and Rs ("2" and "3" in the message list) must
both be released before the request for R4 can be
honored.
Representation as a directed yraph
Alternatively, interlock detection may be viewed as
isolating loops (cycles) in a directed graph. This is so because a system of tasks and resources, inter-related
through queues, may be represented as a directed graph.
Let the tasks in such system be represented by the
vertices (or nodes) of a directed graph. Let an arc be
drawn from node T i to node T;, oriented toward T;, if
and only if T i must wait in the queue behind T i for resource rk. Associate with the arc T, Tithe symbol rk to
complete the representation.
The total set of these arcs, connected "into a minimal
network, illustrates the inter-relationships of all the
tasks in the system with respect to their competition for
available resources.
Using the illustration in an earlier section, first construct the set of individual arcs for each "wait pair."
(S)~_R_o..;;;J~~C9
(T l waits tor To to release Ro>
®
~(S)
(§) R5~ eY
Construct the minimal graph, retaining duplicate
1176
Fall Joint Computer Conference, 1968
arcs between the same pair of-nodes for completeness.
Note that the tasks which are still able to process are
the sinks of the graph. If To releases R a, the graph becomes:
If To were nowto request R 2, the graph is:
~ven though T 2 is now the only task able to process,
no mterlock exists. When T 2 completes, To may run.
When To completes, Tl may run, and then Ta.
Suppose, however, that instead of R!), To requested
R4 (S or E). The graph would then be:
T 2 is still free to process. However, an interlock
exists: for when T 2 completes, no other task may run.
Each is waiting for a resource held by another of them.
There are several techniques from Graph Theory for
the detection of cycles in a directed graph, l -some
oriented toward matrix representation. In view of the
relatively small-number of elements in this application,
adaptations of these might be highly efficient.
Also of potential usefulness from Graph Theory is the
idea of the length of the longest path between any pair
of vertices. This could be used as a rough estimate of the
length of time a task would have to wait for a resource.
The task could decide whether to use an alternate, even temporary, resource, if appropriate.
CONCLUSIONS
This paper has presented a queue management technique which detects interlocking requests for system resources. Two variations of matrix manipulation were
shown, offering a choice between completeness or compactness.
Either approach offers more flexibility and security
than traditional resource control. Conventionally, the
possibility of system interlock constrains a task to:
1) Release all currently-controlled resources prior to
requesting others;
2) Request multiple resources in parallel; and!or
3) Use resources in a strictly-defined order.
The wait-matrix, with elements consisting of a single .
binary digit, requires very little storage. It yields only a
yes/no answer as to whether an interlock exists, but it
provides the information with a minimum of programming. When a task's request for a resource is denied, it
has to release all those it already controls and then rerequest control of them in parallel with the new resource.
The precedence matrix is bulky, especially in complex
systems with many resources defined. H()wever, the algorithm based upon it can isolate the minimal set of resources which must be released by the task.
In addition, the algorithm is easily modified to reverse the direction of search through the wait-chains.
This action permits it to identify the minimal set of resources for which the request for control must be denied.
Topics for further investigation are suggested by
showing that the set of tasks in a system is a partially
ordered set under the relation "wait-for"; and that the
system of tasks and their requests for resources may be
represented as a directed graph.
REFERENCES
1 CCYUNG
The connectedne88 of directed graph8 and applications
PhD Thesis Columbia University New York 1966 p 71
A dual processor checkout system
by KENNETH C. SMITH
Martin Marietta Corporation
Denver, Colorado
"The brain 'Of the higher animals, including
man, is a dQuble 'Organ, cQnsisting 'Of right and
left hemispheres cQnnected by an isthmus 'Of nerve
tissue. It IQQks as thQugh in animals with an intact
calQsum (nerve tissue) a CQPy 'Of the visual wQrld
as seen in 'One hemisphere is sent 'Over tQ the 'Other,
with the result that bQth hemispheres can learn
tQgether a discriminatiQn presented tQ just 'One
hemisphere. When this CQnnectQr between the
tWQ halves 'Of the cerebrum was cut, each hemisphere functiQned independently as if it was a
cQmplete brain. . . ."
"KnQwing that the answer was wrQng, the right
hemisphere precipitated a frQwn and a shake 'Of
the head, which in turn cued in the left hemisphere
tQ the fact that the answer was wrQng and that
it had better CQrrect itself! ... Taken tQgether,
'Our studies seem tQ demQnstrate cQnclusively that
in a split-brain situatiQn we are really dealing,
with tWQ brains, each separately capable 'Of mental
functiQns 'Of a high 'Order...." 1
As human sciences prQbe deeper intQ the physical and psychQIQgical makeup 'Of man; and as
'Other sciences extend man's technical creatiQns,
there frequently seems tQ exist a parallel between
the man himself and his inventiQns. N Qt 'Only do
these parallels 'Occur 'Often but they frequently
occur tQ an extent much mQre grQSS than could
have been PQstulated. Such is the case with a
"Dual PrQcessQr CheckQut System." AlthQugh
seemingly a new technical creatiQn it is clQsely
parallel tQ its creatQrs in its decisiQn and cQntrolling mechanisms.
CQntrQI and decision making is achieved by tWQ
Sigma 7 computers which act independently in
mQnitQring test article data but CQQrdinate effQrts
tQ diagnQse data and transmit cQmmands. Func-
1177
tiQns perfQrmed by 'Only half the brain and results 'Of tests are shared such that each cQmputer
may learn frQm the 'Other. N 'Ow we may discuss
a mQre technical descriptiQn of the checkQut system.
General discussion
TWQ Scientific Data Systems, Sigma 7 prQcesSQrs and five 16k, 32 bit WQrd memQry banks were
chosen fQr the basic cQmputer compQnents. Connected directly intQ the memQry with cQntrol frQm
direct I/O lines are tWQ PCM links, analog channels, and tWQ identical discrete data links. CQmmand links to the test article are provided redundantly. This cQnfiguration prQvides a high
prQbability 'Of cQmpleting a test shQuld a checkout
equipment malfunctiQn 'Occur; and a high prQbability 'Of test article error detectiQn tQ guarantee
human safety.
The sQftware cQnsists 'Of three main elements:
Executive Subsystem, Data MQnitoring Subsystem, CQmmand/CQntrQI Subsystem. The Data
MQnitQring Subsystem prQcesses PCM data links,
discrete data links,- data assQciated interrupts and
nQtifies the remainder 'Of the subsystems 'Of anQmalies which may have 'Occurred frQm the expected
data flow. Specially built hardware helps tQ filter
a raw discrete data rate of lMHZ and a PCM
data rate 'Of 384 KHZ per link. All data is mQnitored at all times tQ prQvide a cQmplete test article profile.
The CQmmand/CQntrQI Subsystem interprets
'Output frQm a user 'Oriented test language translator (subject 'Of anQther paper for this cQnference) which prQvides the test engineer with full
cQntrQI 'Over vehicle testing in a language he may
easily use. Tests may be written ,vhich send com-
1178
Fall Joint Computer Conference, 1968
A
A
R
T
I
I
R N
T T
I
C
L
E
C
E A
L
E
C
E
FIGURE 1-Checkout system online software
mands to the test article and set criteria in the
D'ata Monit'Oring Subsystem as to what results are
expected. The Command/Control Subsystem then
acts on the recovered data as to how to proceed
further.
Executive software fundamentally- consists of a
modified version of the SDS Basic Control Monitor
herein described as BCM. Each CPU is normally
administered by BCM which handles all the checkout system processing functions. Processor work
loads are divided into modular software elements
called tasks and scheduling these tasks, core allocation, I/O processing, trap processing, self tests~
etc., become service functions of BCM. The Executive Subsystem provides these services and overall
control of processing to the other subsystems.
Reliability and integrity are fundamental to the
design philosophy and cannot be compromised.
All data c'Oming into the checkout system must be
processed by both CPU's as are commands transmitted to the test article. This minimizes any possible data error or incongruity between CPU's to
the extent that a disagreement between CPU's will
stem from a discernible hardware malfunction.
The important points being first to detect an error
at the earliest possible 'Opportunity and second, to
take proper recovery action for continuation of the
test with one or two CPU's on line.
A self-test program is the basic element of integrity which guarantees the success of the system
and exists as the lowest pri'Ority task in the scheduler. This means that whenever a CPU is idling
it is in fact testing itself and associated memory
for operability. Several types of tests are conducted on the computer processor and memory
banks: Instruction tests are executed on the CPU.
Read/write tests are performed on the mem'Ory
modules and periodic sum-checks are made on software programs. Self test is also used in processing
Sigma 7 traps and in this way a CPU may determine which particular part of the hardware has
caused a failure.
Responsibility rests with each CPU to cross
examine the validity flags, which, if they are set,
indicates a critical failure in the CPU whose flags
are being tested. The validity flag is set whenever a possible malfunction may have occurred
and is reset when the proper recovery has been
executed. The weight of making a command decis-ion rests upon the good CPU which must learn
the maj or computer component failure of the other
computer system. This may result in new processing functions or a small modification of the test
presently being c'Onducted.
The functions which will be described consist
of that functional hierarchy which manages these
learning and controlling processes between CPU's.
With the internal computer programs and hardware being tested as they are, all that remains to
maintain integrity is to control the data inputs
and outputs. The methods 'Of doing this will later
be described in detail. Such is the spectrum of
programs which guarantee system integrity.
Figure 2 depicts a generalized control and error
flow for the Executive Subsystem and portrays
the hierarchy of the Executive Programs. CPU/
CPU communication is processed through the Dual
Processing Controller with the exception of testing the validity flag. This and CPU/CPU syn-
Control
r--
Task
Delegation
Executive
cro/cro
Interrupt and
Memory ]rtaoe
Dual
Processor
Exeoutive
Dual
Prooessi.J!g
Controller
Non
-agTeement
CPU
Beset
~
Service
Impasse
1
1I~
Control
~
BCM
Control
~
Tasks
I
Inquiry
Selt
T
1 - - - - - - - e....l Tests! ~ _ _
. ---0.
e
r
FIGURE 2-Checkout system executive subsystem
A Dual Processor Checkout System
chronization tests are conducted on a periodic
basis so that an inter-CPU link will not be required to detect a faulty processor. The Check-out
System receives a BCD range time which is required for data synchronization purposes. A
binary doubleword image of this time is maintained in each CPU for basic clocking purposes.
These three sources must be in agreement for the
Checkout System to be fully operati'Onal and any
disagreement is indicative of a computer or data
error. In this case a computer may be taken off
line or a related checkout system function disc'Ontinued.
Errors resulting from any data disagreements
are passed to the Dual Processor Executive which
diagnoses inconsistencies on a detailed level.
Whenever the computer systems disagree upon a
data input, a program failure or some hardware
failure, exhaustive testing must be initiated to uncover the error. Because this is difficult it is imperative that programs compare data wherever
the eventuality may arise that different functi'Ons
may be performed as a result of the data change.
Should a discrete error be detected in one Data
Monitoring Subsystem but not in the other then
that inconsistency will be reported immediately
to the Dual Processor Executive, this indicates a
hardware malfunction if the criteria for the Data
are pre-checked. It may be parenthetically added
that this particular error seldom arises since all
critical discretes (those which are crucial to the
test articles successful performance) are triply
voted in hardware before being evaluated by the
software, indicating that a single discrete failure
will not be detected as an error---..:only a dissenting
vote.
The Dual Processing Executive isolates the malfunctions in the Checkout System and determines
the proper posture to continue testing. Any decisive errors, hardware or software, from all executive subsystem programs are sent to the task
Delegation Executive which reconfigures the software to be compatible with the hardware failures.
If a PCM link failed, then all programs pertaining
to that link would be disarmed, a message would
be printed and processing would continue. CPU
Reset is entered if the Task Delegation Executive
has determined that the functions assigned to this
Executive Subsystem cannot be completed. This
obviously assumes that the computer memory and
processor are 'Operational to a large degree so that
it may turn itself off. Memory or CPU failures
.1179
would be observed in the verification flags which
help to alleviate' this problem.
Executive programs reflect the Checkout System redundancy philosophy. Stated simply, all
critical command/control loops are triply redundant. Whenever a command is to be sent out to the
.test article,· that command is first voted by both
CPU's; the command is transmitted only if both
CPU's agree. The command is sent down three
separate transmission links to the pad equipment
and ultimately to the test article. Critical data are
monitored in an analogous manner. Commands
will generally result in a discrete event change
through the .Data Monitoring Subsystem where
the discrete events are again voted by the CPU's.
Should the CPU's disagree upon an anomaly,·then
this would result in control being passed to the
Dual Pr'Ocessor Executive where such inconsistencies are processed. Each CPU is self-reliant to
the extent that it can fully complete a test independently and run asynchr'Onously with periodic
data and timing checks. This helps to minimize
the data crossover, simplifies analysis in case of
an error and ultimately reduces the complexity
of the software programs.
Thus far, little uniqueness has been suggested
for s'Oftware implementation in the checkout system. Functions such as dynamic allocation of memory, program scheduling (with a hardware priority interrupt algorithm), high speed mass storage
buffer techniques, on-line data analysis and display have seldom been seen in one real-time system but are generally known and understood. It
is not the intent of this discussion to discuss the
total Checkout System Executive uniqueness but
it must be mentioned (even if trite) that the
Sigma 7 dictated some unique implementation by
virtue of its real time characteristics. N ow, we
may proceed to a more specific treatment of the
dual system.
Task delegation executive
Ultimate hierarchal control resides with the'
Task Delegation Executive. All noteworthy information of system status is available here and
all decisions to be based on tailures will be made
here. A failure may result in two general actions:
(1) elimination of that particular function from
the processing chain in that CPU; (2) elimination 'Of a CPU. Each action that is to be taken is
fully dependent on the present system state. For-
1180
Fall Joint Computer Conference, 1968
tunately, however, there are only two hasic states;
Redundant Mode with both CPU's executing the
same test to provide reliability; Test Mode with
each CPU operating independently. This minimizes the number of switch positions.
Switching is accomplished on three program
levels. At the first level is the arming and disarming of tasks (scheduled entries) and interrupts. Both these areas contribute to the change
of data flow (input and output). At the second
level is a gross trap vector change affecting all
Executive Services such as I/O, inter CPU communications, etc. The third level is more refined
and lies within the service trap processors as a
trap may branch to one of several programs for
processing. The Task Delegation Executive must
weigh each of the failures and turn the switches
to the proper position. Notification of the other
CPU and operator/test conductor notification are
other functions completed.
portant than the integrity gained since the number
of command transmissions to the vehicle is not
great over a one second interval. There are also
frequent occasions where the CPU's must be synchronized which implies CPU lost time by forcing one CPU to wait for another. The result of
the technique is a synchronization of events rather
than of a timing window. A communication technique of this type allows each CPU to run asynchronously most of the time which is important
for this system since the loads on the processors
are not identical. Areas of non-redundancy such
as CRT displays, PCM evaluation and recording,
and analog data collection can cause processing
imbalances.
Redundant functions, such as critical anomalies
and commands, are always agreed upon by the
CPU's so that any subsequent action will be the
same in both CPU's. This then must be done in
a synchronous manner.
Dual processing controller: Transmit/receive logic
Dual processing controller: Inter-processor
services
Communication between the CPU's is accomplished using interrupts and common memory. Implementation incorporates both a simplex and duplex interrupt structure. The former technique
is used where ultimate action will result in a processor being taken off-line. This is a high priority
communique for highly significant messages. The
remainder of communication is implemented
through a duplex algorithm where an acknowledgement is always required to complete' the loop.
In both cases messages are placed in mail boxes
which are scrutinized when inter-processor interrupts occur. For the duplex system, timers are
set up upon initiation of a transmission which determine the greatest allowable time that may be
delayed before receiving an acknowledgement.
The inter-processor time delays, as set by the
timers, are only dependent upon interrupt priorities and their processing. These times are not
difficult to determine, and not dependent upon
total processor loads. A second set of timers is
used where necessary to guarantee that queuing
functions are ultimately processed. A failure to
do so implies a serious system non-agreement.
Later examples will demonstrate the technique
where these timers are used. A disadvantage in a
_duplexed system is that it implies a loss of speed
and lost processor time due to. bookkeeping requirements.This lost time is felt to be less im-
Three basic types of services are provided:
memory check, hardware register check and much
of the intra CPU service linkage. These services
may be put together into several combinations to
process any particular circumstance which may
arise. All these services are requested through a
trap processor. that a task may initiate~ This being the only manner in which a slave program
(one that does not have full access to the instruction repertoire) may enter the master mode and
subsequently do I/O, trigger interrupts, etc. The
tool used to provide this linkage :qas been discussed
in the previous paragraphs in general and will
now lend to a more specific treatment of technique.
As has been previously mentioned, the CPU's
run asynchronously and for this reason queuing
type techniques are used so as not to inhibit the
processors operating upon other tasks. To compare data between ~rocessors, then, some memory
allocation scheme must be implemented so that
data may be passed from CPU to CPU. Inherent in
the design is a large segment of memory which has
been designated for dynamic allocation herein
termed "Free Storage." A free storage block
(FSB) may be assigned to a program for an indefinite length of time.
Inter-CPU communication is separated into
three priorities. _ These priorities are assigned to
A Dual Processor Checkout System
a service function and dictate some of the implementation. At the highest priority level, are the
intra-CPU services to be allowed between CPU's.
Expected processing delay and acknowledgement
times are short and no synchronization is required.
Therefore, no queuing is used.
The second transmit/receive pair is assigned to
command functions. Execution delay time due to
interrupting functions is again expected to be nonexistent but because of a synchronous processing
characteristic some queuing is required. Data
cross checking is executed at the lowest level of
priority with normally expected delay times in
the milliseconds region. Therefore extensive queuing is required.
EXAMPLE 1
All inter-CPU services do not require a FSB
and, in fact, this is the rule rather than the exception. Traps which provide scheduler services between CPU's are of such a nature and no addi-
cre
I
!
Program
Requiring an
Alternate
Servic
1 PROGRAMS
1181
tional linkage is needed than that already provided within one CPU.· No queuing is necessary
because the message may be acted on immediately
requiring no synchronization at all between
CPU's. A task such as PCM processing may be
active in CPU 2 and desire to communicate an
anomaly to CPU 1. The task would form all the
normal setup required to activate a task within
CPU 2 but would execute an inter-CPU trap instead. The scheduler in CPU 1 will in turn activate the requested task depending on its level in
the task priority structure. Any address modification will be done in the trap processor if the addressing needs to be changed. This is a serious consideration since the memory banks are numbered oppositely from each CPU with bank 3 being addressed the same from both CPU's. A
buffer area relative to CPU 2 will be displaced by
a constant (for that location) so that CPU 1 may
address the correct buffer.
.
Figure 3 depicts a typical inter-CPU scheduler
service processing. A task being processed by
Cre 2 PROGRAMS
FIGURE 3-Alternate service processor
Dual Processing
Controller
Functions
Dual Processing
Controller Functions
r -_ _ _--L---=In~rru
t
Examine Service
Code
Issue CAL32 Trap
Set Message in
Mailbox
Send Interrupt
Set cre 1
Mailbox
,Set Watchdog Timer
Send Interrupt
/
Retum
Retum
/
/
I
Intermpt
Fetch Code
Turn
orr
Return
Interrupted Program
Clock
r----
.
I
CPU 1
Mailbox
/
~
Return to
Interrupted Program
1182
Fall Joint Computer Conference, 1968
CPU 1 desires to transmit a display message in
CPU 2 and therefore initiates a trap to perform
that function. The message is deciphered by the
Dual Processing Controller. A special code is
placed in CPU 2's mailbox which will direct it to
perform the desired function. Argument addresses are modified for CPU 2 usage. Then, an interrupt is generated for CPU 2 to look in a specific
mailbox location. Before CPU 1 exits it must set
a timer to be certain that CPU 2 has received the
message. Control is returned back to the requesting task to continue processing.
N ow CPU 2 comes into operation through the
interrupt, immediately performs the desired function, sets the acknowledge code in the mailbox,
and triggers an acknowledge interrupt to CPU 1.
FIGURE 4-CPU/CPU memory crosscheck
~
CPU I PROGRAMS
DUAL PROCESS I NG
CONTROLLER FUNC TIONS
Scheduler
Activates
A Task
CPU 2 PROGRAMS
DUAL PROCESSING
FUNCTIONS
~
Get FS'B
Crosscheck
Request
r----sa
Suspend Task
Modi fy Memory
Address For
Other CPU
Set Mar Ibox
Set Tfmers
Send Interrupt
1
~.
Fetch Code
CPU 2
ar Ibox
Queue
·,les5age
Acknowledge Message
Return
I
g
.
rI
Interrupt
Return
Ret rn To
Interrupted
Program
Queue
I
Get FSB
~
..
Fetch Code
Conti nue Task
Executl'on
Acknowledge
Message
. Return
Return To
Interrupted Program
I
Sea rch Queue
~--
CPU I
af Ibox
Scheduler
ActIvates
Canpare Ce I 15
Set Mar Ibox
Send Interrupt
Return
A Dual 'Processor Checkout System
When the interrupt routine is exited, the scheduler will consider the new request and service it
at the proper priority level. A CPU 1 interrupt
routine next comes into activity, turns off the
timer and. exits back to the interrupted program.
EXAMPLE 2
The case above is the more frequent of the
types' of inter-CPU service$' but far ,from the most
interesting. Data compares demonstrate a greater
level of complexity and require a FSB to be accomplished. Following Figure 4 will assist in
comprehending the design implementation of the
inter-CPU data compare service. Since the work
scheduled for the processors in asynchronous, we
may assume that the schedular activates a task in
CPU 1 which requires a check of data in memory
(the synchronous case of both CPU's executing
the same task at the same time cannot be ignored
for implementation but is d'One so here for sim,plicity. The proper trap is set and control is
given to the Dual Processing Controller which
first suspends the task. By suspending execution
of this task it may be observed that the mailbox
entry'to be made is unique as to the task which
requested service. All queued entries are keyed
to a task since it has been temp'Orarily ignored by
the scheduler and no new service can be requested
from that task. The memory address of the FSB
is modified to be read by CPU 2 and the message
is set in the mailbox for CPU 2. CPU 2 is notified
of the pending message by an interrupt from
CPU 1 and then CPU 1 returns to normal execution with the service requesting task suspended.
CPU 2 receives the interrupt, 10'Oks into the
mailbox and decides to queue this message for
later reference. An interrupt is returned to the
initiating CPU to complete one duplex loop. Again,
CPU 1 is initiated and cleans up any bookwork
that may be pending such as turning off one timer.
In this type of service an additi'Onal clock is required to assure that the request to compare data
will not be ignored indefinitely. This is precisely
the type of error the checkout system is designed
to process and timer runout could be indicative of
a maj or malfunction. M'Ore will be said on this
a.rea later in the discussion of the Dual Processing
Executive. It is observed that except for the initial memory compare request all processing proceeds asynchronously under interrupt control.
The second half 'Of the sequence may now take
1183'
place! CPU 2 has the same task activated which
also wishes to compare data. The queue is
searched, an entry f'Ound and the data cells, are
compared. The results of this compare are sent
back to CPU 1 which continues execution of the
suspended task if the results agree. If they do
not, an error mode results which sends control to
the Dual Processing Executive to diagnose the
problem. Acknowledgement is sent back to CPU
2 from CPU 1 to complete the duplex loop. Control is returned to the task if it is still the highest
active task in the schedule and if the data agree.
EXAMPLE 3
Implicit in describing the CPU/CPU service
functions is a method to compare commands that
are to be sent to the vehicle. Although simple in
concept, the actual implementation is somewhat
more formidable than the example previously described for data cross-checking. Three distinct
steps are required to transmit a command and
these c'Ommands are intimately connected to the
redundant philosophy that both processors participate in transmitting commands. This condition may be overridden but only if one processor
is on line, otherwise agreement. is mandatory in
the c'Ommand/control loop. This is not to say that
a program may not be generated to test the test
article up to checkout system processing limits
such. as generating a frequency 'Of 10 KHZ or
better to determine phase shift in a. vehicle subsystem. In this situation no inter-CPU communication is required at the command level.
Implementation has been in such a way that a
minimal amount of inter-CPU communication is
required for synchronization and is somewhat
similar to that as demonstrated inthe previous example. Following Figure 5, a task which is to
send a command causes a trap to the special I/O
handler routine. The Task Delegation Executive
has previously set this trap process'Or to respond
for a Redundant Mode. In this case the task
requesting service does not know how many
CPU's are on line or which CPU is executing the
program. The proper processing path is automatically taken. An interrupt is sent to CPU 2
which queues the message and transmits the acknowledge back. At a later time CPU 2 has the
same task activated as in CPU 1 which determines
to send the same command. CPU 2 observes CPU
1 is already waiting and therefore proceeds with
1184
Fall Joint Computer Conference, 1968
command execution· by loading the proper hardware command registers. A message is placed in
the mailbox for CPU 1 to check and send the command to the test article, which CPU 1 does. The
task which was suspended is continued and a
transmission complete or incomplete is sent to
CPU '2. If the command is sent, then control is
returned back to the task when the interrupt
routine finally releases control. Control is sent to
the Dual Processor Executive should this not be
the case, if the command should be· bad or the
CPU's do n'Ot agree on register content. CPU·2
continues the suspended task when it gets an in-
terrupt which indicates the transmission has been
sent. Control is then returned to the task which
was suspended.
Dual processing executive
The function of this program is to determine
which computer system has malfunctioned, not an
obviously simple assignment with 'Only two voters.
'Ve must recall, at this time, that all data inputs
.and outputs are agreed between CPU's before
they are allowed to occur. Also important is the
awareness a CPU must have to its peripheral
FIGURE 5-Command comparison service
,-
cro
CP(J 1 PROGRAMS
Dual Processing
Controller Functions
I
Task Decides
to Issue a
COJDnand
Dual Processing
Controller Functions
Interrupt
r---t! CPU 2
Sus :pend Task
Set Mailbox
Tri&ger Interrupt
Set Busy Flag
for Command I/O
j
• -I:>; Mailbox
r-------~------~
Fetch Code
-
i
QUeue Me8Sage
Return
n
I
Queue
r--i
In+.
Fetch Code
\
\~.-.
Set Transmission
L::J
Good in Mailbox
I
-:::: Return to
Interrupted Program
I
I
! Task Decides
!
Get Queued Entry
\
Send Command
Continue Task
Return
Return to
Interrupted Program
to Issue
~ _ ~r--s-us-pe-.-n-d-Ta-S-'k-S-----Irt&eomm&Ild .J
~
Check Hard. ware
Registers
Reset Command I/O
Busy Flag
Trigger Interrupt
2 PROGRAMS
~
I
Set Busy Flag for
Command I/O
Load Hardware
Registers
Set Mailbox
Trigger Interrupt
"..
_._----..----..,.,
~ cro
2
.Return to
Scheduler
iL
(MailbOX.
~
--
Interrupt
Fetch Code
Command
I/O Busy Flag
Cont·n e Task
a. •• t
Return to
Interrupted l'rogram
I-----.----~
' - -_ _.........M.W.o"'"-_ _ _ _- - j
A Dual Processor Checkout System
equipment (peripheral to the processor and memory that is). To this end all Martin built hardware has extensive error detecting capability
which compliments the SDS equipment.
U sing this knowledge, that the only malfunction
left must be in one of the computers themselves,
then a self-test is initiated in both computer systems. A period of time is passed to allow completion of. the test and then the validity flags are
tested, each CPU testing the other. Should an
error be detected then the malfunctioning CPU
will be taken off line. The responsibility for this
function resides with the good CPU.
Far, far down the processing path lies the possibility that an error will not be detected. To
realize how far down it is necessary to point out
that all critical data, that which can force a processing decision, are majority voted; and that the
programs for testing a test article have been frequently run before. Therefore, it is not expected
to find software errors in this environment. All
data loads are well analyzed and programmed for.
However, should this eventuality arise then the
test article will be "safed" by both systems to assure that nothing and no one will be harmed.
Reset
This program attempts to clean up a bad CPU
and place itself off line. At the same time the good
CPU also performs a reset function on the bad
CPU which will prohibit that CPU from taking
any further action by isolating the processor from
all memory. This will assure that no further interaction will be allowed by an uncontrollable
computer.
Technique effectiveness
One method of evaluating the effectiveness of
the implementation technique is to examine the
trade-offs available within the implementation and
make this information available for future use.
Core used for the total dual processing control
and error processing scheme for all the processes
described amount to a total of 1200 locations.
Sigma 7 processors must have unique first memory
modules to process traps and interrupts which accounts for the reverse addressing scheme previously mentioned. From this same consideration,
and because of the reliability factor, CPU's are
not allowed to access these modules in a dual processor configuration. Therefore, mailboxes reside
1185
in the second two memory modules and any message· sent out is also recorded so that lost messages
can be recovered to the fullest. extent. Eight interrupts are assigned for inter-CPU linkage and each
interrupt has two mailbox locations with the exception of one which is not used for duplex operation. Six of the interrupts are tied in pairs with
the seventh available for interrupt error recovery.
A timing chart would also be in order. Two basic
considerations are made: (1) elimination of the
duplex system, (2) elimination of queuing.
Nominal Total Time (usee)
CPU Service
Crosscheck
Command Transmission
Alternate Service
W /0 Duplex W /0 Queuing Normal
369.3
320.0
186.0
469.3
370.0'
246.0
639.3
520.0
246.0
Times shown do not take into consideration expected delays due to asynchronous operation nor
is an individal processor share of the time shown.
In general, execution times may be divided in half
to obtain these times. Therefore, to process a
crosscheck service each CPU would require about
320 usec processor time for a queued, fully duplex technique.
Observations
The computerized dual processor solution to
automatic checkout is not a concept that has
evolved over night but after years of experience
in the field. A pilot study was undertaken to aid
in feasibility which resulted in a basic checkout
system design criteria. Data, dynamics and interfaces are all well defined and the problems left became those of fitting a computer into this environment. Uniqueness of the checkout system stems
from its reliability requirements and the method
of implementation. The Dual Computer System
with its asynchronous characteristics allows either
computer to control the article being tested. Moreover, system information must be made available
for automatic switchover to occur. It is also recalled that both computers take an active part in
test execution. .In this light, the similarity with
the human counterpart can be observed.
Software and hardware design and implementation optimization are observed on two levels: (1)
design criteria for the checkout system where
trade-offs were made, (2) frequent testing of very
well defined processes. Imvlementation errors can
1186
F~ll
JQtnt C'Omputer ConfeNnce, 1~66
sh'OW up during preliminary article testing since
many tests are dynamic en'Ough t'O exercise the
check'Out system t'O its fullest capability. This is
in additi'On t'O normal pr'Ogram check'Out.
The Dual Pr'Ocess'Or Check'Out System has been
implemented with the idea that integrity cann'Ot
be c'Ompr'Omised and at the same time system dynamics must n'Ot be restricted. The system must
resP'Ond t'O 95 discrete changes in 10 millisec'Onds
'Of which all changes are n'Ot critical in nature.
H'Owever, this will result in 'Only a few. c'Ommands
being generated. Asynchr'On'Ous pr'Ocessing'is the
answer t'O the 'Overall pr'Oblem all'Owing each c'Omputer the greatest latitude possible.
The Dual Pr'Ocess'Or Check'Out System with its
tW'O brained system, requires close c'O'Ordinati'On
t'O achieve the desired ends. This is done thr'Ough
an isthmus 'Of mem'Ory which is stimulated by. interrupts. A capability exists f'Or each pr'Ocess'Or
to gain inf'Ormation and c'Ommands fr'Om each
other. Should 'One half 'Of the check'Out system
fail the 'Other half is fully capable 'Of carrying 'On
n'Ormally but must have t'O re-Iearn menial, n'Oncritical tasks. Specifically, PCM m'Onit'Oring may
have t'O be re-initialized S'O that c'Orrect test criteria
may be set, which indicates a learning phase. This
is also true 'Of anal'Og testing. Finally, the c'Onnection between the pr'Ocessors may be severed in
which case they may 'Operate independently.
BIBLIOGRAPHY
1 M S GAZZANIGA
The split brain in man
Scientific American August
196~
An operating system for a central real-time
data-processing computer *
by PAUL DAY and HENRY KREJCI
Argonne National Laboratory
Argonne, Illinois
INTRODUCTION
A detailed study of the laboratory data-proces,sing
needs of our' Chemistry Division has shown that
about 25 unrelated experiments (see Table I)
will require or .greatly benefit from real-time
computer service. An assessment of the nature of
these requirements and a careful study of the
capabilities .of the Sigma 7** cQmputer clearly indicate 'that this work IQad could be handled by
such a central computer. This load will use up
to 10 % of the I/O capacity of the system ~nd
require about 40 % of the Central Processor tI~e
to satisfy the real-time needs of all the experI~
ments if they are running simultaneously. An additional 30 % of the Central Processor capability
would be used to perform final processing and
analysis .of the data at the end of each ex~er~
ment. Further examination of the problem IndIcated that while a comparable amount of money
. would have tQ be spent whether we purchased individual .computers for each experiment or a
single Sigma 7 system, the service that could be
provided by the central system would be far superior to the individual small computer service. In
additiQn to the usual features found in third generation computers, the Sigma 7 has true independent Input/Output processors, independent
memory modules and a high speed random access
device (3 X 106 bytes/sec transfer rate), all of
which are essential for the efficient operation of
a large data-collection and processing system.
Analog, information from the various laboratory instruments will be digitized at the remote
*Work performed under the auspices of the U.S. Atomic
.
Energy Commission.
**Manufactured by Scientific Dat~ Systems, Sa.nta Monica,
Calif.
site and transmitted directly to the central computer memory. The data from each of these remote instruments will be processed by a separate
prQgram residing in the central computer. In
the initial stages of our installation, most of the
experimentalists will require this collection and
storage of data for processing at the termination of a .run which may last anywhere from
seconds to days. On the other hand, some of these
experiments, such .as 'nuclear detector multiparameter analyzers, will be partially controlled
by the computer. These experiments will be provided with amplifier gain stabilization and live
displays of computer modified spectra. There is
little doubt that as the experimentalists become
more cognizant of the capabilities of a central
computer, mQre and more experiments will be
mQdified tQ become increasingly interactive with
the computer during an experiment.
The very nature of laboratory research requires that the experimentalist be allowed to'
change his operating parameters during an experiment and make interrogations regarding its
progress. Therefore, in addition to the data lines,
each remote site will contain at least a teletypewriter which will always be interactive with the
computer. Using this device, the experimentalist
will be able to initiate the loading of, his program
and provide the relevant program parameters
by responding to a series of questions posed by
the computer.
Upon termination of an experiment, the ac. cumulated data will be completely processed by
a user-selected processing program. This processing will be done in a low priority background
mode. Additional background processing will be
run on an open-shop basis and small batch jobs
will run one-at-a-time during the many milli-seconds per second that the Central Processor is not
1187
1188
Fall Joint CQmputer CQnference, 1968
handling the real-time prQcessing. In additiO'n,
there are some verylQng-term (hundreds O'f hO'urs)
rO'utine cO'mputatiQns that are O'f important theQretical interest which will be carried out as a "subbackground" jQb. While these calculatiO'ns CQuld
be dQne mQre readily O'n a larger and faster
cQmputer, the time available on larger systems
is better spent Qn dO'ing more advanced research
in this cQmputatiO'nal area.
Design goal
The specific requirements O'f the users in a
typical chemistry research facility cO'ver a brO'ad
spectrum: (a) Data rates vary frO'm O'ne byte/sec
to' lOOK bytes/sec during millisecQnd periO'ds. (b)
Real-time O'peratiQns, except· fO'r data stO'rage requirements, vary from zerO' to sO'phisticated
analysis requiring abQut 10 % O'f the Central
PrO'cessing Unit's (CPU) time thrO'ughout the
O'peratiO'n O'f an experiment. HQwever, there is nO'
instance in which a high request rate and a large
computatiO'nal lO'ad combine to' require mO're than
0.1 sec per secO'nd O'f CPU usage. (c) While
sO'me experiments are cO'mpletely invalidated by
the lO'SS Qf a single data PO'int, O'thers WO'uld nO't
be degraded significantly even if 20 % of the data
were lQst. (d) AlsO', a few experiments must have
a sQphisticated reSPO'nse from the cQmputer in less
than a secQnd and others eQuId wait all day, the
lQSS being the expe.rimentalist's time and patience.
The cO'mputer will be used as a data buffer by
each of the experiments, SQme of which will require mO'derate calculatiO'ns on a real-time basis.
Most O'f the real-time prQgrams require the
evaluatiO'n O'f mathematical functiO'ns and the use
O'f many cO'mmon sub-routines. For example, over
half O'f these prO' grams require a rather large
spectrum-analysis rO'utine. CO'nsiderable memO'ry
can be saved by cQding these routines as "pure
prQcedures" (re-entrant cQde) and having Qne
CO'Py resident in memory shared by many resident prQgrams. As a result, in the majQrity Qf
the cases (20), the data buffer area will require
about four times mQre cO're than the specialized
portiQn O'f each program. Since most of the experiments are transmitting data in an asynchrO'nQus manner, these large data areas must
be dedicated fO'r the d uratiO'n O'f an experiment;
O'nly a 20% saving in CQre WQuld be realized if
"O'verlay techniques"l were emplQyed Qn the cQde
area. TherefO're, at the expense O'f buying sufficient memory to keep these real-time programs
resident during an experiment, the Operating System is relieved Qf the burden O'f re-establishing
apprQpriate memO'ry-residence fQr the majO'rity
O'f the prO'grams. A few (5) O'f the experiments
will transmit their data in bursts at intervals O'f
30 seconds O'r longer and then require a rather
large prQgram fO'r analysis and a nO'n-critical reSPO'nse (time-wise) back to' the laboratO'ry. These
service requests are handled using O'verlay techniques and ar~ processed O'ne at a time on a firstcome first-served basis in a cO'mmO'n memQry area
on a lO'W priO'rity basis.
A simulatiQn prO'gram has been written to'
assess the cO'mpatibility O'f the CPU requirements O'f the variO'us users. This prQgram depicts
Qn a graphical plO't (Figure 1) the dedicatiQn Qf
the CPU as a functiQn Qf time. The input parameters to' the prQgram include the switching Qverhead time, data rates, buffer size, cO'mputatiO'n
time per service request, number O'f I/O requests
per service, and the elapsed time between an I/O
request and its completiO'n. Included in the prO'gram is a routine which simulates the randQmness of the individual events in thO'se experiments where this is applicable. Table II summarizes the results Qf simulating 21 minutes O'f
Sigma 7 O'peratiQn. As can be seen, each service
request was satisfied befQre the succeeding request was signalled (zerO's in cQlumn labeled "NO'.
Inst. Lost"). This gives O'ne assurance that the
demands O'f all of the prQPO'sed users will be
satisfied by the CPU when they are running
simultaneO'usly. The simulatiO'n alsO' shO'WS that it
is practical, when a brO'ad spectrum O'f requirements is to' be satis,fied, to' assign a priO'rity to'
each task and let it run to' cQmpletiQn O'r until it
is interrupted by a service request frO'm a jQb Qf
higher priority. UpO'n cO'mpletiQn Qf the higher
priQrity task, the interrupted task is resumed.
When a real-time prO'gram is to' be IO'aded, its
priQrity will be assigned based O'n the current
cO'mputer wQrk IO'ad, the service frequency, cO'mputatiO'nal time and its required reSPQnse time.
Inasmuch as the sequence O'f tasks carried Qut
by the CPU will be determined by the priority
assignments, sO'me means must be undertaken to'
insure that a high priority prQgram dQes nO't
exceed its allotted running time (preventing prQgrams O'f IO'wer priQrity from running) due to' a
program errO'r O'r an unusual data sequence. AlsO',
all of the real-time prQgrams will be assO'ciated
with research projects whQse data-prQcessing requirements change frO'm time to' time, implying
that these prQgrams will require mO'dificatiO'n on
Operating System for Central Real-Time Data-Processing Computer
USER
INSTRUMENT
INVESTIGATION
Digital potentiometer
Neutron spectrometer
Multi-channel anal.
Atomic beam
Multi-parameter anal.
Multi-channel anal.
Multi-parameter anal.
Multi-parameter anal.
Multi-channel anal.
Mass spectrometers
Mass spectrometer
Cryogenic NMR
Digital potentiometer
Neutron spectrometer
X-ray spectrometer
36-det. count lab
Multi-parameter anal.
Time-of-flight m. s.
Mass spectrometer
Multi-parameter anal.
N ucl. mag. res.
Abraham
Atoji
Camall
Diamond
Engelkemeir
Fields
Friedman
Glendenin
Hines
Holt
Katz
Katz
Osborne
Peterson
Siegel
Steinberg
Steinberg
Studier
Wexler
Unik
Weil
1189
Low temp. heat capacity
Crystallography
Optical absorption spectra
Nuclear spins
Heavy element decay studies
Decay scheme studies
Proton reaction studies
Fission studies
Decay scheme studies
Routine mass analysi~
Deuterated compounds
Deuterated compounds
Low temp. heat capacity
Crystal structure
Crystal structure
Decay and spectra studies
Proton-nuclei reactions
Carbonaceous chondrites
Charge states of mol. frag.
High res. fission studies
Structural studies
TABLE I-Work load summary
i es
8"C~QND.
e
e..
UNI~
ea
HINES
ee
CARtiALL
21
STtl8RD I!
eo
f'ItLDS
l-
19
STUDIE"
f
18
!'BRH"
17
kATZ 2
16
OSBRtI I!
I
II-
15
OSBRN 1
f
1"
SEtOtL
13
flTDJI
I
I-
12
HOLT 2
11
HOLT 1 .
9~
10
kATZ 1
] }
l-
IlI-
--------~
~--~)
---~
--~
~
l---
l------+
1------)
H
1---+
I-~I~
9
"~IL
B
tNOLk"R
7
OLNDIN
6
STNBRO
5
UNI~
I I
11
II
] 1
] 1] 1] ] 11]
] ] I' ] ] ] } I ]
} } }
1
..
FRD"flN
a
STN8RG 1
e
WEXLtR
1
WEXLtR 1
] ]
e
l ]
]1
}
] ]
] }
] ]
] ]
} }
]]
I ]
] ]
] ] J ] ] ]] ] ]
] ] I ] ) I ] ]]
] ] ] ) ] ] ] ] ]
] I ] ] ] ] ] ] ]
]]
] 1
] ]] ]
J ]
] ]
]1]1])]])
} ] 11 ] ] ] ] J
1 ]
] ]
] ] I ] ] 1] ]
1]
I I
] ]
J J
]1
]1
1.00 SEC.
] ]
] 1 ] ] 1 } I 1 ].
1]
11
] ]
I ]
] ) ] J ) ] J 1]
] ] ] ] ]
] ]
I ]
1]
]]
, e.oo I
FIGURE 1--8imulation of CPU usage as a 'function of time. Increasing time along horizontal axis and tasks of decreasing
priority along vertical axis.
SEC.
1190
Fall Joint Computer Conference, 1968
occasion. With 25 such programs resident in
memory at a time, some of which have not been
thoroughly tested, it is absolutely necessary that
these programs be prevented from writing over
each other.
In addition to being required for the Operating
System, auxiliary storage must be .used for several other purposes.. The real-time processing for
a single multi-parameter experiment requires
the maintenance of eight updated spectra. Each
spectrum (2048 words.) must be updated during
a data buffer processing which takes place at
intervals of about one second. Limiting core
residency to one table ata time reqUires the readal.7~2
ing and writing of the eight tables once each
second. The simultaneous running of the four
planned multi-parameter experiments will require an aggregate data transfer rate of 512K
bytes/sec between memory and .mass storage.
Also, the raw data from the multi-parameter experiments must be written on magnetic tape.
The remainder of the remote sites will generate
considerably less data (less than 65K bytes per experimental run), which can be readily handled by
a mass storage device with a capacity of several
million bytes. To facilitate remote loading of
real-time programs, their object forms must reside in mass storage.
MIN •• TOTAL RUN TIME
.32 MSEC./SWAP, OVERHEAD
PRIORITY
AND LINE
DESCRIPTION
1 WEXLER 1
2 WEXLER 2
3 STNBRG 1
FROMAN
!5 UNIt< 1
4
.6 STNBRG
7 GLNDIN
a
E.NGLKMR
9 WElL
10 KATZ 1
.1 1 . HOLT 1
12 HOLT 2
13 ATO..JI
14 SEIGEL
15
OSeRN t
16 OSSRN 2
17 KATZ 2_
18 ABRHM
19 STUDIER
20
21
22
23
24
FIELDS
STNBRG 2
CARNAl.L
HINES
UNIt< 2
T.IME REa. AVE. -TI ME
TO SERVe BETWEEN
AN INT.
INTERRUPT
1.50
1.20
2.00
2.50
2.70
2.50
2.20
2.10
1.80
3.10
16.00
16.00
60.00
50.00
150.00
249.56
249.56
247.66
100.49
55.65
55.78
55.71
250.42
150.18
150.36
29606.75
31016'.60
957S.65
12771.54
150.0~
IS147.64
18609.96
14803.38
28319.50
930.9.79
217116.16
162837.12
162837.12
1 08S!l8.oe
400.00
·150.00
270.00
2000.00
2000.00
2000.00
2500.00
3000.00
14803~38
PERCENT NO. INTS. NO. INTS. TIMES INOF TOTAL SERVICED LOST
TERRUPTEO
TIME
.60
• 48
.Sl
2.49
4.85
4.48
3.95
• 84
1.20
2.06
.05
• 05
• 63
• 39
t.Ol
.99
2.15
1.01
.95
2.15
.-..-.-.----.-.
....
- TOTAL FOREGROUND
37.6f
BACKGROUND
57.00
OVERHEAD
O.
o.
o•
o.
o.
O.
o.
o.
o.
o.
o.
o. :
o.
o.
o.
- 46.
14.
6•
• 92
1.23
1.54
2.76
o.
o.
o.
o.
o.
o.
o.
o.
o.
5220.•
5220 •
5260.
12964.
23408.
23355.
23382.
5202 •
8674.
8664.
44.
42.
136.
102 •
S8.
86.
70.
88.
a.
a.
12.
..
122099.
--........
5.40
TABLE II-Real time simulation-summary
--.-
-.
.......................
o.
o.
12.
82.
349.
939.
-1082.
1175.
544.
834.
1641.
77.
72.
8~3 •
49·8.
1276.
1261.
2736.
1300.
1204.
2840.
1225.
1611.
2026.
3641.
~.-
.......-...
27258.
73765.
Operating System for Central Real-Time Data-Processing Computer
While the most efficient code is written in assembly language, the experimentalists should not
be required to learn a particular machine language, but be permitted to write their own programs in the more familiar FORTRAN language,
if they prefer. Therefore, FORTRAN capability
should be provided for the real-time user as well
as for the batch processing users.
Although immediate final analysis is useful
to the experimentalist, it does not have the urgency of the real-time operations and therefore
should be executed in a "background mode" which
will operate at a low priority level. The actual
final processing requests will be placed in a
background queue by the data-collection phase
program upon completion of an experimental
run. The remaining' CPU time should be used for
"open shop" batch processing and long-term computations.
The Supervisor offered by Scientific Data Systems (Batch Processing Monitor) for the Sigma
7 was designed to handle a number of real-time
tasks in the foreground mode (high priority)
while running a sizable batch-processing operation in the background mode (low priority). The
principal shortcomings of their system are that
the practical number of foreground tasks is considerably less than ten, there is inadequate memory protection, no provision is made for foreground program "overrun time" traps, and that
it contains an inefficient Rapid Access Device
(mass storage) handler. Rather than attempt to
modify a Supervisor that was designed without
large-scale real-time operation as the primary
goal, it was decided that a fresh start, with the
detailed requirements of the experimentalist in
mind, would be a better approach.
Hardware configuration
The Sigma 7 is a third-generation machine:!
with an 85.0 nano-second memory and an instruction set whose .execution times range from
1.2 J.L sec for an "add immediate" to 25 J.L sec for a
"long form floating divide" (16 decimal digit).
The Central Processing Unit (CPU) has sixteen
programmable registers, of which seven may be
used as index registers. The instruction counter,
"memory write key," and other information germane to the currently running program reside in
a 64 bit CPU register called the Program Status
Doubleword (PSD). When a program is to be
interrupter, the 16 registers and the current PS.D
must be saved, and the PSD of the interrupting
1191
program must be set in the CPU. This can be
accomplished with .a series of three instructions
(,24 J.L sec). When the interrupted program is to
be resumed, the 16 registers and the PSD must
be reloaded. This is also accomplished with three
instructions (22 J.L sec). The CPU also has a
priority interrupt structure which responds to
signals from internal clocks, I/O terminations and
up to 240 external sources. A memory "write
protection" feature associated with the CPU compares the "write protect key" (two hits in the
PSD) with the portion of a 512 bit "write-protect
lock" image (private CPU register) associated
with the page of memory (512 word) being referenced. An attempt to modify memory with an
in1proper "lock and key" match results in a fault
trap. This checking operation proceeds in parallel
with instruction interpretation and thus does not
lengthen instruction execution time.
The hardware configuration for our system is
shown in Figure 2. For the remote terminals
and the standard pe·ripherals, data transfer with
the main memory is accomplished through one of
the two "Multiplexor Input/Output Processors,"
each of which can service up to 32 simultaneous
users with a throughput of about 400 K bytes/sec.
For high-speed data exchange with mass storage
at speeds approaching full memory speed, one
"Selector Input/Output Processor" will be used.
Both types of I/O processors operate _independently of the CPU once an I/O operation has been
initiated. They also contain internal hardware
which permits them to execute a succession of
I/O commands from core memory ("command
chaining") without CPU intervention once they
have the address of the first command in a
chain.
The advantages of independent input-output
processors would tie obviated if there were only
a single set of addressing hardware for all of
memory. Our configuration will contain four
separate memory banks of 16K words each. Each
bank of memory is accessed through a port, one
port being dedicated to the CPU and one to each
of the I/O Processors. Each of the banks contains its own reading and writing hardware.
Therefore, the CPU can operate at full computational speed when instructions are being executed from one bank of memory while a mass
storage device is transferring data through the
"Selector I/O Processor" at near full memory
speed into another bank.
The mass sto·rage device will be an SDS "Rapid
1192' Fall Joint
Co~puter
Conference, 1968
Access Device" .(RAD) which consists of a r0tating disk (35 msec. rotation period) with fixed
heads that transfer data at 3 X '10 6 bytes/sec.
The 64 bands of 82 sectors (1024 bytes) each
have a total storage capacity of about 5 X 106
bytes.
Operating system structure
Overview
Our system is not a generalized data acquisition system, but an Operating System in the fullest sense of the term as. recently described by
Wood,s consisting of a Supervisor and a set of
Processors. The Supervisor was written to provide a well defined multi-program environment
in which a large number of programs may operate without mutual interference; the Processors
(assembler, compiler a.nd loader), which run
under the Supervisor, are the current SDS versions. Each program is fully protected from all
other programs both in space as well as time. By
"E"ORY
8"NIt 0
1& It '
SIG"" 7
CENTR"L
PROCESSINg
UNIT
implementing the Sigma 7 "write-protection"
feature, a program is prevented from writing in
a portion of memory which is not assigned to it.
In addition, all I/O is executed via I/O ha.ndlers
(part of the Supervisor) which fully check the
validity of each request. U'sing the CPU internal
clock, the system also keeps control of the time
that it spends on each program and can abort
a job which exceeds its allotted time (or proceed
to the next program if' a time-slice has been consumed in a time-sharing situation). The Supervisor is structured in such a manner that it is
event-driven from three types of signals; request
for service from a remote site, the completion of
an I/O operation, or the run-out of an internal
clock. With this structure it is then quite feasible
to have a mix of tasks running simultaneously
which include: real-time data-collection and/or
processing programs requesting service via an
I/O completion or external signal; a group of
. time-sharing conversational terminals which are
time-sliced via an internal clock; and a modest
batch-processina- operation.
"ErtORY
8"Nat 1
1& It
"E"ORY
8"NIt
e
. 16 It
--------------------,
-----.
I
I
I
I
I
I
I
I
I
I
I
C"RD
PUNCH
FIGURE 2-Hardware configuration
"EMORY
S,.NIt
16 It
a
Operating System for Central Real-Time Data-PrO'cessing CO'mputer
Data buffering
As indicated in an earlier sectiO'n, the, variety
of tasks that must be performed Dn a real-time
basis is Df such a nature that they may be assigned a priO'rity and performed on a run-to-completion basis (interruptable only by a higher'
priority task). The task that each prO'gram must
perfDrm generally consists of transferring the
data that accumulates in memDry tOo auxiliary
stDrage and/or performing sO'me modest cO'mputations and returning the results to' the remO'te
site. Since response times of less than a secO'nd
are nDt required in most Df the cases, and in O'rder
to keep the program switching rate down to a
reasonable level (about a hundred per second),
the data will be accumulated in blO'cks (under contrO'I O'f a Multiplexor lOP) intD dedicated portions of memory assO'ciated with each program.
The size O'f these blocks will depend on the average data rate, the peak rate, the amO'unt of
processing required and the urgency for computer analysis. In mO'st O'f the prO'gra.ms under
consideration, the experiment can proceed before
a block O'f data is analyzed Dr transferred to'
auxiliary stO'rage. Thus, to facilitate an uninterrupted flow O'f data, the data buffer areas are
divided up into a minimum O'f two equal blocks
and the "command chaining" feature of the I/O
PrO'CeSSDrs is incO'rpDrated in the follO'wing manner. The first I/O command fills half of the
buffer and upon filling this area the commandchaining flag directs the input/output processor
to get the next cO'mmand which initiates input
intO' the Dther half O'f the buffer. Simultaneously,
with the cDmpletiO'n O'f the filling of the first half,
the I/O interrupt of the CPU is triggered, signalling the Supervisor that service is needed. With
the expected mix of tasks, the assO'ciated program shDuld obtain sufficient CPU usage to
prO'cess the buffer and extend CO'mmand chaining
in a circular manner before the second half of
the buffer fills. As a result, the experiment can
cO'ntinue to transmit its data to' the cO'mputer independently O'f the detailed needs of the O'ther
users. In the event the task is nO't completed befO're the second half of the buffer is full, the I/O
fO'r . this terminal will halt because command
0haining had nO't yet been set; the, processing
program will have to. start the I/O O'peratiO'n
again when the apprO'priate task has been completed O'n the other half O'f the buffer. For data
inputs that vary a great deal in rate during the
course O'f an experiment, this double-buffering
1193
technique can be extended to' any level. Typically,
these buffers are a few hundred words IO'ng with
a filling time of about onesecO'nd.
Software priority structure
The CPU task sequence can be readily related
to the priority chain in Dne of two ways. The
rapid switching capabilities of the external
priority interrupt structure could be used if the
requirements O'f the tasks can be estima.ted with
sufficient accuracy and remain cO'nstant fO'r extended periods. However, if the real-time needs
change, the priO'rity assignments must be modified. AlthO'ugh changing hardware priority assignments is a relatively simple changing of
cables, it could O'ften mean stO'Pping someexpen.
ments while the cables were changed. This WO'uld
be intO'lerable. TO' avoid this problem, a software
priDrity interrupt system was designed and implemented which allows priDrity alteratiO'n in
microseconds and has the potential for a SupervisO'r cO'ntrolled dynamic priority re-assignment.
Figure 3 depicts the priorities as they are established in the present SupervisO'r. Any task Df
higher priority can gain the services of the CPU
(via an interrupt) after the request has been
processed by the "Interrupt Supervisor" portion
of the Supervisor.
Program description table
The Supervisor runs, services and contrO'ls the
variO'us resident prDgrams by referring to a PrO'gram DescriptiO'n Table (PDT) assO'ciated with
each prO' gram. These tables contain the Program
Status DoublewO'rds, the "write-prO'tection" lock
image, the current and allotted running times,
space fO'r saving the register contents when interrupted and various cO'ntrO'I bytes which assist
the Supervisor in keeping track of the current
status O'f the prDgram. All of the I/O cO'mmands
and the memO'ry bounds are also stored in the
table. The I/O handlers use this informatiO'n in
processing I/O:, requests. The integrity Df these
tables is insured by making them inaccessible to
the user prO'grams ("write-prO'tected").
Input/output handlers
All input-output DperatiO'ns are effected by appropriate handlers which· nDt only facilitate data
buffering but also permit prO' grams O'f IDwer
priO'rity to run while a prO' gram O'f higher
priority is waiting for the completion of an I/O
. 1194 Fall Joint Computer Conference, 1968-'
I/O INTERRUI"T
I/D INTERRUPT LEVEL
REAL T1"E LEVELS
···
··
j
I
··
··
·
F"IRST THREE
~~~~¥ Of" A
ID Of" NEXT LOWER
PRIORITY PDT
DEVICE ADDRESS
.
END OF" JOB
'
<.-----.:.--
(7)
(8)
where· (J max is the maximum angle, as seen from the
hologram, over which the· image is played out, A is the
mean wavelength of the'illumination, and .:l A is the
wavelength spread. As examples, with a mean wavelength of 8500A, a .:l A of 30A, and a (J max of 450 ,
(all values for lasing diodes) the number of bits that can
be stored is 5 x 104 • If now ~ A is 300A (the value for
non-lasing diodes), the capacityis reduced to 500 bits
per hologram.
The third, and perhaps most important limitations
arise from the spatial coherence of conventional light
emitting diodes. The GaAs diodes is an extended source
of light, each segment of the source emitting light independently of every other segment. As a result there is
no unique, time-invariant representation of the emitted
radiation that can be made that relates one part of the
wavefront with another. It is this that is meant by spatially incoherent illumination. Such illumination imposes a severe limitation on the capacity of a holographic
store, for it can be demonstrated that if spatially incoherent light is used to illuminate a hologram, and
if the source as seen from the hologram is of a given
angular extent, then the smallest image from the
hologram will have the same angular extent. As
a result the number of bits per hologram (the number of resolvable spots in the hologram's image),
which is inversely proportional to the smallest resolvable spot in the image, is reduced. There are a
number of ways to overcome this limitation. The first is
by the use of a lens to reduce the angular extent of the
source as seen by the hologram. The second, and more
elegant, is the use of smaH, lasing GaAs diodes. These
diodes, as will be. discussed below, have a high surface brightness, near monochromatic output, and if
made very small have spatially coherent light emission.
There are other factors that could be considered, for
example the effects of emulsion shrinkage. However,
this and other effects are not peculiar to this application
of holography and so will not be discussed here. Com-
1201
plete discussion can be found in the literature. See for
example Ref. 7.
Light emitting diodes
There are actually two types of light emitting diodes
to consider, incoherent and coherent (lasing) diodes.
We will first consider incoherent light emitting diodes
and then turn out attention to coherent (lasing) diodes.
IncohereI).t diodes emit light, when forward biased, at
a -mean wavelength of 91OOA, with a spectral width of .
300A. The diodes typically have a low power efficiency,
about 2%, requiring large currents to achieve high
light output. In our experiments, using a commercially
available diode, four amps are required to obtain 40mw
of emitted radiation. The diode response time, current
in to light out, is relatively long, typically 100--150 ns.
I t is suspected that the slow speed of response is due to a
mechanism involving deep traps which must be filled
before light of appreciable intensity will be emitted.
Surface brightness, a figure of merit commonly used
to compare different sources of illumination, is 40 mw/
mm2 which is large when compared to conventional
sources but low, as will be seen, when compared to a
lasing source. Surface brightness is important in that it
ultimately determines, regardless of the kind of optics
used, the power per point in the image. A low surface
brightness therefore, will result in a low storage capacity
in the hologram memory.
As mentioned previously, such a source is spatially
incoherent. Furthermore, due to its low surface brightness, the source size must be large to achieve reasonable
power levels. We can see therefore, that such a source
will always impose a severe limitation on the capacity of
such a memory (especially if a high speed memory is de.
sired).
Coherent (la.sing) diodes emit light at a mean wavelength of 85OOA, with a spectral width of less than 30A.
Above threshold (approximately 50 ma) they have a
high differential power efficiency about 30 %, allowing
low drive currents. The speed of response very high,
the diodes typically turn on in less than ten nanoseconds.
Surface· brightness is very high, typically 8 X 108
mw/mm2 • Thus even with incoherent illumination,
small source sizes can be used and still yield appreciable
puwer levels, implying high storage capacities. Encouragingly however, light emission has been achiev~
for small (~1/2 mil) lasing diodes which is completely
coherent and implies that capacities of up to 30 X 103
bits per hologram can be achieved. The small size of
these diodes also allows one to fabricate an array of
light sources which is qUite compact. Arrays of 1 mil
diodes on 10 mil centers are contemplated for future
models of the memory.
is
1202 Fall Joint Computer Conference, 1968
The main disadvantage of coherent .(lasing) GaAs
diodes is that presently they must be used in a liquid
nitrogen enviornment. With the availability of reasonably low cost closed cycle liquid nitrogen refrigerators
this is not a real disadvantage, mainly a psychological
one.
The photodetecting array
1000 bit array, a 25 nanosecond risetime is indicated.
One of the features of this array is the isolation of the
selection current, which flows horizontally through the
switching diodes, and the signal currents, which flow
through the vertical line. Since the large currents associated with driving the GaAs diodes are electrically
separate, due to the optical coupling, high speeds without drive noise spikes in the sense output are achievable.
Moreover, this simple diode structure is fairly easy to
integrate, and the photodetecting array can be built up
of smaller subsections. Such photodetecting arrays have
been built at out laboratories and operated successfully ..
Figure 6 shows a word-organized photodetecting array suitable for the Light-Emitting Diode holographic
memory system. The total analysis of this matrix will-be
published elswhere; in this section we will outline how
this matrix works and its characteristics.
A word is selected by turning on the switching diodes _
Discussion of experiments
of a particular (horizontal, in the case of Figure 6) line
by closing its switch (a transistor). Then the photo curExperiments were performed to demonstrate the imrent generated by light falling on the back-biased photoplications of the previous statements. To illustrate the
diodes (which can -have typically 70% quantum effisalient features of the concept, a small working model
ciency) on the vertical lines has a path through the
of a holographic read-only memory accessed by light
sense amplifier, which has low imput impedance,
emitting diodes was built. * The model consisted of four
through ground and the conducting word line. Photoholograms accessed by four GaAs light emitting diodes.
currents generated in the photo diodes associated with
The hologram stored 26 bits, with the output of the
an unselected word line see a high impedance path and
hologram projected onto a 26 bit photodetector array as
so do not contribute to the sense signal. The risetime of
described in the previous section. The outputs of the
such an array has been calculated to be
photo detector array were amplified to a suitable level,
threshold detected, and strobed out. Each component
R. T. = 5 X wn Rswitch diode Cphotodiode
will be examined in turn.
To compensate for the wavelength shift, as discussed
where 5 represents the ratio of a selected word sense sigpreviously, each hologram stored a predistorted array
nal to worst case unselected word signal, wn the number
of spots as shown in Figure 7, with the output
of bit~ in the detecting matrix, Cphotodiode the capacity
of each hologram a square array. The hologram
of a photodiode, and R switch diode the on resistance of
was made with the configuration schematically
the switching diode. Putting in typical values of 5 pf for
photodiode, 1 ohm resistance switching diodes and a
BIT
SWITCHING
--.01--+.::.tI-l)t--............C+-~t-......-ot-., DIODE
FIG URE 7-Input spot array, showing reference
Notice lack of squareness
FIGURE 6-A word-organized photodetecting array
* For ADP/ECOM,
~eam
Fort Monmouth, New Jersey.
position.
Holographic Read-Only Memories
shown in Figure 8, using light from a He-Ne laser
(X = 6328A). The reference beam diverged from a point
1" in front of the hologram surface and at an angle of
2° to the hologram normal.
The sources of illumination for hologram reconstruction were commer9ial GaAs light emitting diodes. The
diodes were driven by a pulse amplifier capable of delivering 4' ampere pulses with a 50% duty cycle at 10
Mhz. The pulses was able to deliver the four ampere
pulse within 25 nanoseconds at the initiate pulse, including delay plus current risetime.
The desired diode was selected by means of a switch.
A simple lens was used to collect the light emitted by
the diode to provide the convergent beam needed for
undistorted hologram reconstruction. As discussed
earlier the playout beam converged to a point at the
'plane of the image I" from the hologram.
The image of each hologram was projected onto a
photodetector array, of the type discussed previously,
with each hologram imaging on the same photodetector
array. The light sensitive elements of the array were
hpa 4207 diodes. The word diodes were hpa 1006
high conductance diodes. Separate word lines could be
selected either mechanically, by means of switches, or
electronically.
The output of each bit line was fed into a low input
impedance, high gain, wide bandwidth, amplifier. The
amplifier had a total delay plus rise time of about 50
nanoseconds, an input impedance of 50 ohms, and a
transfer ratio of 1.5 volts per 1 #-,watt of illumination
incident on a photodetector. The output of the amplifier was strobed and then applied to a threshold detector.
Sense amplifier output of two bits read in parallel is
shown in Figure 9. There are a number of things of interest to be seen in the figure. The first is the high one to
zero ratio obtained from this kind of memory system.
FIG URE 8-Recording arrangement
1203
. The second is the long rise time of the light emitting
diodes. Figure 10 illustrates the access time ofthe system. The top trace is the input to the light emitting
diodes, pulse amplifier (the address pulse), the second
trace is the sense amplifier output, and the bottom trace
is the processed output. The access time shown is 200
no; again it can be seen that amost all of the delay is
caused by the slow turn on time of the light emitting
diodes, as seen in the second trace. As shown the pulse
duration is 500 ns. This length was chosen for pictorial
reasons only, and is not representative of pulse duration
achievable. As we have said above, the main speed
limitation is the time of response of the. light emitting
diodes, which with incoherent diodes is about 150 ns,
while with coherent light emitting diodes it is about 10
ns, or less.
The minimum detectable signal, the value of which
was a prime objective of this study, for it ultimately
determines the speeds and capacities that can be
achieved in future systems, was found to be 2.5 X IO-~4
watt-seconds. (This corresponds to a 1/4 #-,watt signal
of 100 nanoseconds duration, we give the result in terms
of minimum energy for reasons of generality.) This
value would allow a 10:1 signal to noise ratio, or an
error rate of l(t-s, which is minimally acceptable. With
this figure it is possible to determine the energy needed
a
b
FIGURE 9-The sense amplifier output for a one (a) and zero
(b). Vertical scale ~ volt/em Horizontal scale lOOns/em
FIGURE lo-Operating waveforms of hologram read-only
memory using incoherent light-emitting diodes
(a) Initiate pulse
(b) Sense amplifier output, showing rise time
of light-emitting diode
(c) Strobed output
Horizontal se~le lOOns/em
1204
Fall Joint Computer Conference, 1968
to access a hologram memory system, for if N is the
number of bits, Ell is the hologram efficiency, then the
energy needed is
E TOT =
N X 2.5 X 10-14
.
watt-seconds.
E"
The hologram used in this model had an efficiency of
5%, which is typical for the type of holograms used.
This means the minimum energy needed in a hologram
memory is
E TOT
=NX5X
10-18 watt-seconds.
The storage capacity of the holograms used has been
shown to be most severely limited by the low surface
brightness and lack of spatially coherent radiation of
the light emitting diodes. The maximum number, of bits
that can be stored with such a source is below 200 bits
per hologram if access times of .5 #,secs are desired. The
large physical size of the light emitting diodes does not
allow compact spacing of the array of sources (and thus
of holograms) and thus limits the capacity of a complete
system, for the conditions of a maximum hologram output angle of 450 and a hologram array size larger than
the photodetector array are not compatible. As a result,
if the hologrmns can not be spaced compactly, only a
small number of holograms can be used, limiting the
system capacities. All of the above indicate that coherent (lasing) diodes must be used to make the concept
realizable.
the hologram at high speed. It has been the purpose of
this paper to describe a technique to achieve ~uch a
means, the use of an array of light emitting diodes to access the holograms.
The use of light-emitting diodes as a hologramselector severely reduces the capacity of this type of hologram memory when compared with that using a gas
laser. However, the. use of these diodes allows very
rapid access to the memory store, something not yet
achievable with the gas laser systems.
This is the philosophy of this class of read-only
memories: sacrifice capacity for the speed and easy
changeability of contents. Experimentally we have
demonstrated the feasibility of making holograms for
such systems and. devised photodetecting arrays of requisite sensitivity and speed. As both our analyses and
experiments have indicated, the critical element in this
type of memory is the accessing array. Incoherent
diodes possess neither the surface brightness nor short
turn-on time required for this memory system. With
lasing diodes, capacities of 1()5-106 bits at cycle times
below 100 nanoseconds appear achievable with present
hologram and photodetecting array techniques. However all present lasing diodes need to be cooled to 701500 K. With further improvement in the device
characteristics, an order of magnitude larger capacities
become possible. Such memory systems can be evaluated on the basis of the analysis presented in this paper.
REFERENCES
1 RJPOTTER
CONCLUSIONS
From the discussion in this paper, the advantages of a
hologram read-only memory are manifest. Digital information can be stored with high bit dens~ty and with
great redundancy. The need for fine, highly corrected
lenses is obviated; accordingly, the need for precise,
mechanical placement does not exist. Easy replacement
of the storage medium is possible since the only link
between the medium and the rest of the system is light,
requiring no electrical or mechanical connections. The
most important advantage, however, is that through
the use of holography large information stores can be
achieved with relatively few electric components. In a
properly made system, the number of components
needed in a conventional memory is essentially divided
by the number of holograms used: each hologram' projects its images onto the same detector array, reducing the ~eed for extensive electronics.
While these advantages have been apparent to us and
others for some time, a total system has not been implemented due to a lack of an efficient means of accessing
Optical processing of information
Spartan Books Baltimorev1963
2 DGABOR
Microscopy by reconstructed wave-fronts
Proc Roy Soc London A197 454 1949
3 HFLEISHER
Application of interference photography to optical information
storage
Presented at Holography Seminar Colorado State University
January 1967
4 1J K ANDERSON et al
A high-capacity semipermanent optical memory
Presented at Conference on Laser Engineering and Applications
Washington DC June 1967
5 AOPLER
Fourth generation software
Datamation 1322 1967
6 R CHAPMAN M FISHER
A new technique for removable media read-only memories
Proc of 1967 Fall Joint Computer Conference Anaheim Calif
1967
7 D BOSTWICK D H R VILKOMERSON R S MEZRICH
Techniques for removal of distortions in hologram images caused
by a change in playback wavelength
Presented at Spring Meeting of Optical Society of America
March 1968
Semiconductor memory circuits and technology
by WENDELL B. SANDER
Fairchild Semiconductor
Palo Alto, California
INTRODUCTION
In the past few years the use 'Of semic'Onduct'Or
flip-fl'OPs f'Or a significant P'Orti'On 'Of the mem'Ory
of a c'Omputing system has been appr'Oaching a
practical reality. The pressures and c'Ommitments
within semic'Onduct'Or lab'Orat'Ories t'Oward achieving a c'Ompetitive edge in the main frame mem'Ory
market are increa&ing. The mem'Ory field 'Offers
a new market area as 'OPP'Osed t'O the displacement
'Of existing pr'Oducts in a new f'Orm. Furtherm'Ore,
the manufacturing pr'Ocess f'Or semic'Onduct'Or
memories is characterized by the mass pr'Oducti'On
'Of similar items; this pr'Ocess is in exact acc'Ordance with the present pr'Oducti'On methods in the
semic'Onduct'Or industry and is far less painful
than that 'Of ~he LSI l'Ogic field, which threatens
t'O lead t'O an endless pr'Oduct pr'Oliferati'On at small
v'Olumes. Alth'Ough the mem'Ory field is in its infancy and largely speculative, it is P'Ossible t'O
make a brief survey 'Of the techn'Ol'Ogy and the c'Oncepts being pursued in the devel'Opmental lab'Oratories. A further review 'Of semic'Onduct'Or mem'Ory can be f'Ound in Reference (1).
Chip technologies
At the present time three distinct chip techn'Ol'Ogies are being c'Onsidered; bip'Olar, p-channel
MOS and c'Omplimentary MOS. The bip'Olar pr'Ocess used f'Or semic'Onduct'Or mem'Ory is similar t'O
conventi'Onal pr'Ocessing including multi-layer
metal. Mem'Ory circuits are repetitive and can be
relatively non-critical 'Of c'Omp'Onent value permitting expl'Oitati'On 'Of the bip'Olar pr'Ocess in new
ways t'O achieve a marked impr'Ovement in c'OmP'Onent density. An excellent example 'Of this is a
cell described by BTL 2 at the 1967 ISSCC. The
p-channel MOS techn'Ol'Ogy 'Offers a c'Onceptually
simple techn'Ol'Ogy capable 'Of pr'Oducing mem'Ory
cells at g'O'Od density.
Pr'Ogress in MOS techn'OI'Ogy is pr'Oceeding m'Ore
or less independently fr'Om the particular needs
'Of semic'Onduct'Or mem'Ory and the maj'Or eff'Ort in
p-channel MOS mem'Ory circuit techniques is
simply t'O expl'Oit the techn'OI'Ogy t'O its fullest. F'Or
example, it is desirable t'O use bip'Olar circuits t'O
pr'Ovide high level drive and l'OW level sensing t'O
achieve the best mem'Ory system perf'Ormance
fr'Om the MOS cells. 3,4,5
C'Omplimentary MOS is the integrati'On 'Of b'Oth
p-channel and n-channel MOS devices 'On the same
chip. It is the least well devel'Oped 'Of the three
techn'OI'Ogies discussed in terms 'Of pr'Oducti'On
capability. There is a wide variety 'Of fundamental
appr'Oaches t'O c'Omplimentary MOS being· devel'Oped including thin film field effect transist'Ors, 6
silic'On 'On saphire 7, and simple diffused silic'On.
Due t'O the need f'Or pr'Oducti'On c'Ompatibility and
low C'Ost, the all-silic'On system is them'Ost likely
near-term pr'Oducti'On pr'Ocess and in fact, is the
'Only pr'Ocess with standard pr'Oducts 'Of any kind
presently available. C'Omplimentary MOS is
viewed by many (but n'Ot all) in the semic'Onduct'Or
field as being applicable primarily t'O special mem'Ory applicati'Ons where the inherently I'OW P'Ower
is essential. It is n'Ot likely t'O be C'Ost c'Ompetitive
in m,em'Ory applicati'Ons with either bip'Olar 'Or
p-channel MOS f'Or the f'Oreseeable future.
1205
Packaging technologies
There are three basic techn'Ol'Ogical fact'Ors in
interc'Onnecti'On 'Of the m'On'Olithic chips int'O a
mem'Ory m'Odule; interc'Onnecti'Ons fr'Om the chip,
sec'Ond level interc'Onnecti'Ons, and chip sealing
against c'Ontaminati'On. There is a maximum size
1206
Fall Joint Computer Conference, 1968
of chip for any given technology that can be fabricated with 100% yield over the chip. This number is fairly small; on the order of 64 to 256
bits/chip with present technology. This represents a level of testing required before proceeding
to interconnecting the chips (or wafer region)
with a higher level interconnection.
The most straightforward way to handle these
good chips is to test the wafer, ink the bad chips,
dice the wafer, and throwaway the bad die. However, at least one manufacturer, Texas Instruments, has taken an alternative approach, wherein
the good areas are mapped and a special interc'Onnection mask for the wafer is made and applied
to interconnect these regions. 8,9 This approach
will not be discussed in detail here. The following
discussion as'sumes the handling of small chips
acquired by wafer sort and dicing. The attachment of the chip to the next level interconnect can
be handled by individual lead bonding of pads on
the die to a next level interconnect or may be
formed by anyone of several batch attachment
techniques. Since memory chips tend to have a
large number of leads, batch attachment is most
attractive.
Some 'Of the batch connection techniques are:
1) Ultrasonic bonding of aluminum bumps
on the chip to the substrate metalization
2) Thermo compression bonding of aluminum bumps. on the chip to the substrate
metalization
3) S'Older reflow of solder bumps on the chip
to the substrate metalization (Figure 1)
4) Form solder coated beams extending beyond the edge of the chip which are
bonded to the substrate with the die
ei~her face up or face down.
A comparative evaluation of methods 1, 2 and 3
may be found in Reference 10. Thebeam lead approach of 4) was developed by Bell Telephone
Laboratories and is described in reference. 11
The attachment is usually made with the die
mounted face down on the substrate, however,
techniques for face up mounting are being developed for both beam lead structures and by batch
interc'Onnectiqn of face up chips after die attachment. 12 The major factors to consider in the attachment systems are the economics, attachment
yield, repairability and heat dissipation. Ease of
repair will probably be a dominant factor if many
chips are attached to a single substrate. In gen-
FIGURE I-Chip with solder bumps
eral, the face down bonding technologies are easier
io repair, but the face-up technolOgies allow better
inspection 'Of bond quality and better heat dissipation.
The substrate (Figure 2) for next level interconnection can be anything from a single chip
package to dozens of uncased chips on a multilayer substrate. The best economic potential lies
in multiple attachment of uncased chips to the
substrate. Single layer metalization on the substrate is highly desirable from an economic standpoint but may not be adequate in all cases. The
substrate material is usually either alumina with
FIGURE 2-Single and double layer substrate
Semiconductor Memory Circuits and Technology
gold plated molymanganese interconnections·· or
silicon with aluminum or moly-gold interconnections. The alumina is a common ceramic well understood for the purpose whereas silicon is more
fragile but can provide very high interconnection
densities.
Chip sealing is required to prevent surface
contamination which can degrade the circuits.
Chip sealing can be accomplished by a sealing
cap on every chip, by sealing the entire multichip
substrate (Figure 3), or by a sealing coat of silicon nitride on the chip. The nitride sealing method
is by far the most attractive but is not yet a well
developed production technology for integrated
circuits. The most common and practical alternative is sealing the entire module. This requires a
large area seal that is not easy but can be done.
Memory circuit8
Read-write cells
Bipolar
Figure 4 illustrates the most common bipolar
memory cell in linear select and coincident select
form. This cell operates with the word line at a
. low potential for standby. When the word line is
raised the information in the cell is read out by
sensing the current in the bit line, or is written
into by holding down one bit line, thus forcing the
transistor on the held down side to be turned on.
The major disadvantage of this cell is that the
standby power dissipation is higher than the
power dissipation when addressed. This problem
+V
COINCIDENT
LINEAR
FIGURE 4-Bipolar cells
can be alleviated for the linear select cell by treating both the illustrated word line and the +v line
as word lines. Both lines can be raised for addressing and minimum supply voltage for standby
operation can be utilized. 8
Other cell circuits can be used 13,1',15 and four
layer devices have been proposed/ 6 but the cell
of Figure 4 will probably be the most common
bipolar cell for the near future in large memory
arrays due to its simplicity.
MOS cells
Figure 5 illustrates the most commonly used
MOS cell in both 17,12,13,14 linear select and coincident select form. The cell is operated by turning
on the MOS transistors to connect the cell to the
bit lines. The bit lines can then be sensed to determine which state the cell is in. For writing
into the cell a differential voltage is impressed
across the bit lines to force the cell into the desired state. To achieve the best performance from
this cell the word lines (or x and y lines) are
driven from powerful bipolar drive circuits, thus
providing very fast addressing to· the cell. If the
LINEAR
FIGURE 3-Multichip module assembly
1207
COINCIDENT
FIGURE
5~
MOS cells
1208
_Fall J 'Oint C'Omputer C'Onference, 1968
bit lines are held negative during the sense time
then a differential current will appear 'On the bit
lines as s'O'On as the w'Ord line is 'On. This differential current can be sensed by a bip'Olar differential thresh'Olding circuit with very little v'Oltage
change 'On the bit lines. Thus, the p'O'Or capabilities 'Of MOS devices t'O drive large capacitance has
been defeated by using bip'Olar drive and sensing.
The resistance 'Of the MOS resist'Ors is of little
importance in this cell since signal current is
drawn thr'Ough the ON switch and the write v'Oltages (again bip'Olar) will f'Orce b'Oth sides 'Of the
cell t'O the c'Orrect p'Otential. Theref'Ore, these l'Oad
resist'Ors need 'Only pr'Ovide leakage current 'Or be
supplied by asynchr'On'Ously pulsing the -v line.
In this way, standby cell p'Ower can easily be in
the micr'Owatts. Peripheral circuit p'Ower and
transient p'Ower are the maj'Or s'Ources 'Of p'Ower
dissipati'On in the MOS mem'Ory.
on S'O that the flip-fl'Op will be f'Orced t'O the state
impressed 'On the bit line.
C'Omparative evaluati'On
In all three technol'Ogies the mem'Ory 'Organization will be repetitive arrays of dense cells and
specialized peripheral circuitry. Only the c'Omplimentary MOS is likely t'O be treated as having
l'Ogic compatible signal levels; the MOS and bilJ'Olar will be used with very specialized bipolar
interface circuits. Table I is a brief c'Omparis'On
of the three cell technologies assuming present
pilot line technology. The designs are assumed
optimized for cost with speed a secondary factor.
The speed here means the cycle time in a complete
memory system of the order of 105 bits.
TABLE I -Cell technology comparison
C'Omplimentary MOS
Figure 6 illustrates a c'Omplimentary MOS memory cell. This is not suggested as an 'Optimum cell
but is representative 'Of the c'Omplexity 'Of c'Omplimentary MOS cells. 5 ,6 In this cell transmissi'On
gate A is n'Ormally 'On t'O cl'Ose the flip-fl'Op 1'O'Op.
T'O read the cell transmissi'On gate B c'Onnects the
cell to the bit line and the state 'Of the cell can be
sensed. T'O write int'O the cell transmissi'On gate
A is turned 'Off and transmission gate B is turned
WRITE
READ/WRITE -----~--+---l.--_4_-BIT LINE
FIGURE 6-Complimentary MOS cell
Bipolar
p-channel M OS
Compi. MOS
Cell Area
(sq. mil)
Speed
(n sec).
10
15
80
100
250
200
Power (cell
only) (mw)
0.5
0.01
10-0
The cell density of bipolar and pMOS are close
enough that cell c'Ost will not be a determining
factor. The complimentary MOS density, however, is poor enough to shut it out of a raw cost
race. Furthermore, it offers no major advantage
'Over p-channel MOS in speed r therefore, the first
conclusion that can be drawn is that complimentary MOS is. most suited in micropower applications where very low standby power is essential.
This market area is sufficiently large to assure
. development of c'Omplimentary MOS mem'Ories.
The bip'Olar vs pMOS trade-'Off is m'Ore inv'Olved.
The bip'Olar has a speed advantage with n'O direct
cell c'Ost penalty; h'Owever, the 0.5 mw power level
causes definite thermal problems. A 4K mem'Ory
m'Odule c'Ould be assembled 'Oli less than 1 sq. inch
'Of substrate but w'Ould dissipate 2 watts of p'Ower.
Thus, simple air c'Onvecti'On c'Ooling is inadequate
alth'Ough other cooling. meth'Ods can easily handle
this p'Ower density. The pMOS cell does n'Ot have
this pr'Oblem and can be packaged t'O the mechanical limit with simple c'O'Oling.
The big market is in the l'Ow cost/go'Od performance area. There is no clear cut winner between
Semiconductor Memory Circuits and Technology
bipolar and pMOS for memory cells as the tradeoffs are too close. Both will be developed and a
final edge of one over the other will require some
dramatic development in one of the technologies.
Bipolar technology will always have an edge in
speed, however, because speeds much faster than
100 n sec. system cycle time are achievable. Therefore, bipolar cell technology is assured a niche in
the memory market.
On-chip decoding
As cell density increases there is increasing difficulty in getting the interconnections off the chip.
For example, a 4 mil by 4 mil linear select cell will
have leads on 4 mil centers in one direction and 2
mil centers in the other. These leads can be
brought off on alternate sides around the chip
giving 8 mil pad to pad centers on two sides and
4 mil centers on the other two. Coincident select
cells require only 8 mil centers on all sides but the
cells will be larger with a given technology.
These lead centers are manageable in terms of
actually making the connections to the substrate
but the substrate problem can be serious. It is
very difficult to place 4 mil centers on a ceramic
substrate, although such placement is not too bad
on silicon. Unfortunately, the unscrambling
8.round the chip will be a maze and will almost
certainly require complex multilayer substrate interconnection.
If the lead density can be significantly relieved,
then single layer substrates can be considered
since part of the interconnections can be reflected
onto the chips if more pads are available. This all
leads to the consideration of on-chip decoding. Onchip decoding must be very simple since it must
be duplicated on many chips. The simplest decoding is diode networks in bipolar and series gating
in p MOS. In both cases on-chip address inversion
is prohibitive. In bipolar the complexity is too
severe and in pMOS the speed penalty is too severe. Assuming on-chip decoding with non-inverting logic, three choices of input are available:
1) True and complement binary signals.
For 2 n bits 2 n lines are required. The
internal decoding gates are n input gates.
2) Multi-dimensional decoding. For 2n bits
two dimensional decoding requires 2 (2n/2)
lines (n even) and a decoding gate fan-in
of 2: Three dimensional decoding requires
1209
as little as 3 (2nl3 ) lines with a gate fan-in
of three. Multidimensional decoding can
be continued to the point that each dimension is only 4 lines wide (plus possibly
one 2 line dimension) where the number
of lines required is only 2n and the number of gate inputs is ~ (n even) or n~1
(n odd). Thus, the number of inputs is
the same as for true-complement inputs
but the decoding gates are simpler.
3) Combinatorial Decoding. If there are m
input lines and the internal decoding gates
have n inputs then ( mn ) independent signals can be decoded. For example, with
12 inputs and 3 input gates the number of
lines that can be selected on chip is (l~ ) =
220 whereas the multidimensional case
would also use 12 inputs and 3 input gates
but only select 26 =64 lines.
Of the three input structures the multidimensional decoding is superior to true-complement input and the input code is very easy to construct.
The combinatorial decoding is the most efficient
on the chip but the input code is very complex to
construct and the number of select lines is not
inherently a power of 2. Since the multidimensional decoding is sufficient to solve the lead problem (for example 16 lines for 256 bits vs 48 lines
for the undecoded linear select cell) the complication .of combinatorial decoding is not required.
Figure 7 illustrates decoding networks for the
bipolar cell. Both word line decoding and bit line
decoding are possible. On the word line all diode
inputs must be high to permit the selected word
line to rise. On the bit lines all inputs must be high
on the selected bit line pairs toeprmit the cell
current to be coupled through the output diodes to
the bit line bus. Note that by using both word line
and bit line decoding the decoding is broken into
two networks so that for 256 bits, two 4 X 4 decoding networks can be used requiring only 2input gates.
Figure 8 illustrates decoding for the pMOS
structure. Series gating is the most desirable
form of decoding since the series gates can be
made with low on impedance and driven by bipolar drivers. Word line decoding is again possible, however, the drive voltage of the series gate
must be somewhat higher than the highest potential expected on the line and since the word
1210
Fall. Joint Computer
+v
Conference~
1968
+v·
WORO LINE
. DECODING
I
-+- ------- -- --------I
BIT LINE
DECODING
----+-----...1....--+-----...1....--
BIT LINE
_ _ _...L.-_ _ _ _ _....l-_ _ _ _ _ _
BUS
FIGURE 7-Bipolar cell decoding
-v
-v
such that p'Owerful drivers and sensitive ·sense
circuits are used. This provides a minimum peripheral circuit 'Overhead cost.
The pMOS word lines and bit lines are generally capacitive requiring drive voltages in the 5 to
20 volt range with sense currents in' the order of
0.1 rna. The high voltage capacitance drive required leads to active pull-up drivers.. Transient power at these voltages can be the dominant
power requirement 'Of the system.
Bipolar cell drive circuits require a low voltage
swing (in the order of 1 volt) but currents in the
range of 0.1 to 0.2 ma per bit, therefore, bipolar
cells use a low voltage current driver and driver
power is small compared t'O cell power. Bipolar
sense circuits must sense 0.1 rna signals with small
bit line perturbation so the sense circuit requirement are quite similar between bipolar and pMOS
cells.
Other memory forms
WORD LINE
DECODING
-v
BIT LINE
DECODING
BIT LINE
BUS
FI GURE 8-MaS cell decoding
line is already driving a series gate the input voltages must be quite high. On the bit lines, however, the series decoding gate drive required is
the same as the normal word line so that bit line
decoding is more desirable since the voltage
swings are somewhat smaller.
:peripheral circuit consideration
The peripheral circuitry for semic'Onductor
memory has many of the attributes of peripheral
circuitry for magnetic memory. In particular the
largest possible fan-outs and fan-ins are desirable
Other memory structures than simple readwrite are possible. The most commonly considered
are associative memories,19,20 multiport memories
and read-'Only memories. Of these three, read-only
memories are making the biggest splash in the
market place.
Both bipolar and pMOS read-only memories
are available from semiconductor manufactl.lrers
today. Both contain complete logic compatible deeoding 'On the chip and use a fixed connection pattern applied during fabrication. Thus, there is
a tooling charge to get the pattern desired. The
bipolar version is somewhat faster but the pMOS
version is somewhat lower cost. The pMOS memory is stored by selectively creating or c'Onnecting
to a dense array of MOS transistors. The bipolar
memory is stored by selectively connecting to an
array of diodes or emitter followers. The actual
array densities can be quite similar, however, the
logic compatible pMOS decoding is much more
dense than the logic compatible bipolar decoding.
An economic example
Table II provides an illustration 'Of the economic factors in semiconductor memory. This is
an example of potential 1972 costs in high v'Olume
production. A 4096 bit module is assumed using
16, 256 bit bipolar memory chips, 4 decode-drive
chips and 2 sense-digit drive chips. The packaging
Semiconductor Memory Circuits and Technology
is assumed as a single layer interconnect ceramic
substrate with repairable upsidedown chip attachment. The module would have about 70 n/sec
read or write cycle time and would dissipate about
2.5 watts.
TABLE II-Module cost
Cost Each
Total!
Module
Cost/Bit
(cents)
$1.00
0.75
1.00
10.00
.50
2.00
$16.00
3.00
2.00
10.00
11.00
2.00
0.4
0.075
0.05
0.25
0.275
0.05
25 % yield loss
Repair
Retest
44.00
11.00
1.00
1.00
1.1
0.275
0.025
0.025
5% Yield loss
57.00
3.00
1.43
0.075
60.00
1.5
Cost Center
256 bit chip
Decode/drive chip
Sense/digit chip
Substrate
Attach cost
Test
Table II illustrates module cost alone and does
not include system packaging or power. The po
tential for system packaging compatability and at
least partial power supply compatibility are fav'Orable fact'Ors in semic'Onduct'Or memories.
CONCLUSIONS
Semiconductor memory is looming as contender
f'Or a maj'Or portion of the computer main frame
memory market. C'Omplimentary MOS and bip'Olar
techn'OI'Ogies are assured 'Of a niche in the micr'O
P'Ower and very high speed areas respectively. The
major battle will be between bip'Olar and p channel MOS f'Or the I'OW C'Ost (and high v'Olume) seg'
ment 'Of the market.
The semic'Onduct'Or and packaging technol'Ogies
required are in an advanced state 'Of devel'Opment
and a maj'Or impact sh'Ould be seen within the
next few years.
REFERENCES
1 DAHODGES
Large-capacity semiconductor memory
Proceedings of the IEEE Vol 56 No 7 July 1968
2 J ElVERSON J H WOURINEN JR B T MURPHY
DJDSTEFAN
12111
Beam-lead sealed-junction semiconductor merrwry with mini rna
cell complexity
IEEE Journal of Solid-State Circuits Vol SC-2 No 4 ppl96201 December 1967
3 PPLESHKO LMTERMAN
An investigation of the potential of MOS transistor merrwries
IEEE Transactions on Electronic Computers Vol EC-15 No
4 pp 423-427 August 1966
'4 D E'BREWER S NISSIM G V PODRAZA
Low power computer memory system
AFIPS Conference Proceedings vol 31 pp 301-393 FJCC 1967
5 JHFRIEDRICH
A coincident-select MOS storage array
Digest of Papers pp 104-105 ISSCC 1968
6 J R BURNS J J GIBSON A HAREL K C HD
R A POWLUS
Integrated memory using complimentary field-eifect transistors1
Digest of Papers pp 118-119 ISSCC 1966
7 J F ALLISON F P HEIMAN J R BURNS
Silicon on sapphire complimentary MOS memory cells
IEEE Journal of Solid State Circuits Vol SC-2 No 4 pp
208-212 December 1967
8 R S DUNN G E JEANSONNE
Active memory design using discretionary wiring for LSI
Digest of Papers ISSCL 1967 pp 48-49
9 RSDUNN
The case for bipolar semiconductor memories
AFIPS Conference Proceedings Vol 31 pp 596-598 FJCC 1967
10 P SCHARLT T COLEMAN K AVELLAR
Flip component technology
Proceedings 1967 Electronic Components Conference pp
269-275
11 M P LEPSETTER
Beam lead technology
Bell systems Tech J vol 45 pp 233-253 February 1966
12 J MARLEY J H MORGAN
Direct interconnection of uncased silicon integrated circuit chips
Proceedings 1967 Electronic Components Conference pp
283-290
13 G B POTTER J MENDELSON S SIRKIN
Integrated scratch pads sire new generation of computers
Electronics vol 39 No 7 pp 119-126 April 4 1966
14 H A PERKINS J D SCHMIDT
A n integrated semiconductor memory system
Proceedings-Fall Joint Computer Conference 1965 pp
1053-1064
15 I CATT E C GARTH DE MURRAY
A high speed integrated circuit scratch pad memory
Proceedings Fall Joint Computer Conference 1966 pp
315-331
16 R P SHIRELEY
SMID A new memory element
Proceedings Fall Joint Computer Conference 1965 pp
637--647
17 J D SCHMIDT
Integrated MOS transistor random access memory
Solid State Design Janua.ry 1965 pp 21-25
18 A W BIDWELL
A high speed associative memory
Digest of Technical Papers ISSCC 1967 pp 78-79
19 R IGARASH T KAROSARA T YAlTA
A 150-nanosecond associative memory using integrated MOS
Transistors
Digest of Technical Papers ISSCC 1966 pp 104-105
2·1/2D core search memory
by PHILIP A. 'HARDING and MICHAEL. W. ROLUND
Bell Telephone Laboratories, Inc.
Naperville, Illinois
WORD
Usual memories allow addressing of individual word
lines with each word line containing an assemblage of
bits. Bit detectors which can sense all words are utilized
to read the word contents. Associative memories allow
bit lines to be addressed, as well as word lines, to determine which set of words match the input bit states.
Such memories ~re useful because they eliminate time
consuming word hunting in table look up operations,
and because they allow· easy access to specific words
highlighted by activity or flag bits.
Unfortunately, most associative memories proposed
are expensive. Possibly circuits based on large scale
integration may allow low cost associative operations,
but they are not economically feasible today. Core associative memories rarely have been proposed; those
described have complex memory mat structures.1 In
most cases, the cost penalties far outweigh the usefulness of the true associative array.
The semiassociative solution, one in which a segment
of any single bit line in an array can be addressed to
read out the corresponding bit locations for anum ber of
words may be the compromise that finds a wide range of
applications.2 This type of memory, defined as'a single
bit search memory, is symbolically illustrated in Figure
1. Such a memory may be operated in the ordinary sense;
one of the "n" unique addresses can be selected to read,
the "m" bit word contents. Similarly, a unique address
may be chosen and the m bits can be independently written. The figure illustrates the selection of address "Ai"
either for reading or writing the "m" bit contents.
In the search mode, a single block' of K address locations associated with any single word bit, Bj, may be
selectively read or written. The figure highlights the
B jth bit of words 1 through K in block 1 and the B tth
bit words of SK through (S + l)K in block S as possible search words. The entire word field of n can be arranged in n/K blocks of K words each to facilitate the
search mode. It has been found that a modified 2 wire
or 3 wire 2-1/2D Core 'Memory can economically
I-"- BLOCK 1 - .
r-'
WORD',
WORD
BLOCK S --,
BLOCK
%
1
III
BIT
u
4
3
2
1
l1li
1234
1\
SK
,
(S+I)K
n
AODRESS
FIGURE l-Definition of a single bit search memory
achieve the single bit search memory function if only
one m-bit nonnal address word or one K-bit search word
is selected during one memory cycle.
2-1/2D, 2-wire memory
A single bit search memory can be thought of as an
extension of the conventional, 2-1/2D, 2-wire core
memory shown in Figure 2, which was reported on in an
earlier paper.3 In a 2-wire, coincident current memory,
the readout voltage from a particular core must obviously be sensed across one of the two drive wires intersecting the core. In the memory of Figure 2, the core array is composed of a front and rear plane, with the readout voltage being sensed differentially across a pair
of selected bit wires, one in each plane. The centertapped conneetion of the bit readout transformer also
forces the bit drive current to divide equally between
the front and rear planes. The group selection cirouit
provides a virtual ground to the selected pair of memory
wires in each bit while simultaneously isolating the nODselected wires, whioh are multipled to the readout transformers at the top of the array. Hence, any noise voltages induced on the nonselected wires are not coupled
into the readout. The group selection circuit is formed
of diode rails conneoted in a driven bridge configuration
1213
1214
Fall Joint Computer Conference, 1968
BIT READOUT
TRANSFORMER
WORD
GROUP
SelECTION
CIRCUIT
WORD
DRIVERS
FIGURE 3-A single bit search core memory
FIGURE 2-2-1/2D core memory
BIT DRIVER
of the type described in Reference 4.
The word access consists of a diode matrix driving
folded word loops each of which intersects two cores on
a given bit line. Since the word and bit currents will add
in one of the cores and cancel in the other, the direction
of word current is'used to select one core or the other,
thus reducing the number of word access circuits required by a factor or two. 4 The looping of the word wire
has anum ber of additional advantages. The cores can
be oriented in-line, rather than in a diamond pattern,
increaE-ing packing density. The shuttle voltages due
to word current tend to cancel. And finally, no more
than half of the cores on a bit line can be disturbed by
word current into a worst case delta noise state. 4
A word is read out of this memory in the following
fashion. Bit read current is applied first causing a large
noise spike in the readout. When this noise has expired,
the word current is applied, reading out the state of the
m bits of the word. The word is rewritten into memory
by reversing the word current and applying reverse bit
write current to those locations where a "one" is to be
stored. This timing is indicated in FigureA.
Single bit search memory
The word access of Figure 2 supplies current' to only
one selected word loop. At little additional cost, we can
perform the same selection process with an access that
is virtually identical to that used in the bit dimension,
as shown in Figure 3. We can select a pair of word lines
(rather than a single loop) by energizing the appropriate
word driver and word group selection circuit. Note that
the cores on the front and rear planes are oppositely
phased with respect to the word current so that only one
WORD DRIVER
BIT REAQ.OUT
FIGURE 4-Memory address sequence: bit driver current
word driver current, bit readout
core is selected per bit. However, we now have the
added flexibility of being able to readout in the word
dimension. That is, rather than energizing m bit drivers
and then a single word driver and finally sensing the
readout on m pairs of bit wires, we energize all K word
drivers first and then a single bit driver while sensing
the readout on K pairs of word wires. Thus, we can
readout the state of K different word locations of a
given bit in a "search" mode, or all m bits of a word in
the normal or "address" mode. The timing for the
search mode is illustrated in Figure 5. The readout wave
form is the same in either mode, but appears across the
bit transformers in the address mode and across the
word transformers in the search mode.
4- plane single bit search
The word wiring scheme of Figure 3 lacks the shuttle
2-1f2D Core Search Memory
~-BIT
1215
-_ DRIVERS
BIT
--
BIT DRIVER
\
o
WRITE 0
'----~
rJ
m
(1
WORD DRIVER
WRITE 1
WORD READOUT
FIGURE 5-Memory search sequence, bit driver current,
word driver current, word readout
and delta noise reauction advantages of the word line
looping of Figure 2. These advantages can be regained
by using the four-plane configuration of Figure 6. The
word and bit lines are wired so that only one plane receives a simultaneous word and bit current. This is indicated in Table 1.
TABLE 1--4 memory plane wiring
1
2
3
4
Search memory operation
Let "llS consider the operation of a search memory of
n words, having m bits per word, and with the word
access divided into K segments (each segment having an
independent driver, detector, and register cell). The
block diagram of such a memory is shown in Figure 7.
BIT
LINES
CORE
SELECTED
PLANE
PLANE
PLANE
PLANE
FIGURE 6-Improved search memory access
PLANES
PLANES
PLA NES
PLA NES
1,2
1,2
3,4
3,4
WORD
LINES
PLANES
PLANES
PLANES
PLANES
1,4
2,3
2,3
1,4
WORD
DATA
BIT
DATA
FIGURE 7-Single bit search memory block diagram
1216
Fall Joint Computer Conference, 1968
In a normal or address mode, the address to be intern
rogated is supplied in two parts; log2 K address bits
are supplied to the address register which controls the
bit group and word group selector circuits. As an example let us assume equal bit and word group selector
circuits. Then the bit group selector circuit decodes 1/2
log2 ~ inputs and selects one of the
¥~ groups of m
bits each. The word group selector decodes the remaining 1/2 log, ~ inputs and selects one of the
~
groups of K bits each.
The remaining lout of K address selection is performed via the word data input, which energizes the
appropriate lout of K word drive:rs. All m bit drivers
are atcivated and readout is accomplished via the m bit
detectors.
desired flag bits. The matching operation is readily accomplished by using a word register such as the one
shown in Figure 8. The register is initially set to the
"'1's" state by a timing pulse. If the readout from a
given word detector mismatches the match bit B J , the
corresponding flip-flop in the word register is reset. On
the subsequent search read, the match bit becomes
the second· desired flag bit B J + 1, and· those readouts
which mismatch will again reset their corresponding
word register flip-fl()ps. Thus, any word flip-flop which
remains set after all of the flag bits have been searched
corresponds to an address whose flag bits match all of
the desired flag bits.
The following example further illustrates the ripple
search technique. Suppose that the desired flag bits B J
through BJ + 3 are 1001 and that the memory contents
FROM DETECTORS
n
In a search read mode, log2 K address bits are again .
MATCH BIT Bj
supplied to the address register to control the group selector circuits. However, now the roles of the word data
and bit data inputs are interchanged. All K word drivers
are energized, corresponding to the K addresses over
which the search is to be made, while only a single bit
driver is energized, dependent on which bit is to be
searched. Readout is accomplished via the K word detectors.
Flag bi~ memory
As mentioned earlier, one of the attractive applications of a search memory is in the reduction of hunting
for an active or "flagged" word. If a single bit of the
word is reserved to indicate activity in the remainder
of the word, that particular bit can be called a "flag"
bit. If one performs a search read on the flag bit, then
those locations in the word register which are set will
correspond to the words which are "active," and subsequent normal reads can be used, with the active word
locations automatically stored in the word register, to
determine the entire contents of the active words. If
multiple words are flagged in a word block, some form
of priority selection may be necessary. In the case of few
active words, the flag bit search can reduce the hunting
time by a factor of K. In practice, the reduction can be
as great as' one or two orders of magnitude.
Ripple search
In the case where more than a single flag bit is required to locate a desired address in memory, a "ripple
search" technique can be employed. This simply involves sequentially searching through the flag bits, eliminating all addresses which mismatch on any of the
DOUBLE
RAIL
MISMATCH
GATES
TIMING
~R~
----------K
FIGURE 8-Ripple search word register
MEMORY CONTENTS
OF WORD BLOCK "S"
BIT
Bj+3=1
0
Bj+2=O
0
h
1
1
1 0
0 1
1
Bj+1 =0
0
0
0
Bj=1
0
1
1 0
1
~
1
'I"{
I
0 ,..
0
/j
SK+l SK+2SK+3SK+4
(S+l)K
0
1
0
1
0
0
0
1
0
0
0
j::
~ r:100:000
l../ ~
l../ ~
0.95~
for large sized memories.
The memory described is ba~ically a 2-1/2D-2-wire
core store; it therefore has the speed, size and cost limitations inherent to such systemE!. Microsecond operation for a. few million bits is entirdy feasible. However,
it is also possible to extend the scheme to 3-wire systems
for inoreased speed capability.
BITS
REFERENCES
0.86
....
c(
1 W L McDERMID
Y.II
ali:
HE PETERSON
A magnetic associative memory system
0.5
The IBM Journal of Research and Development Vol 5 No 1
January 1961 pp 59-62
2 HSSTONE
Associative processing for general purpose computers through the
use of modified memories
o
2
3
4
5
6
7
8
NUMBER OF SEARCH BITS
24 BITS/WORD
32 WORDS/SEARCH
FIGURE 12-2-1/2D core address and search memory costs:
relative cost/bit vs number of search bits for an
800,000 and 6,400,000 bit memory
1968 Fall Joint Computer Conference
3 PAHARDING MWROLUND
Novel low cost design for 2-1/2D storage systems
1967 Solid State Circuits Conference Digest of Technical
Papers Vol X IEEE Catalog No 4C-49 pp 82-83
4 PAHARDING MWROLUND
Bit access problems in 2-1/2D 2-wire memories
1967 Fall Joint Computer Conference Proceedings Vol 31 pp
353-362
Design of a small multiturn magnetic
thin :film memory
by WILLIAM .0.. SIMPSON
Texas Instruments, Incorporated
Da.lla.s, Texas
INTRODUCTION
Since Pohm* introduced the concept of multiturn
windings ,as a means for improving the efficiency
of planar thin film memory elements and thereby
lowering the cost, very little, work has been published on memories using this technique. Planar
thin film memory elements typically require word
currents on the order of 500 rna and bit currents
on the order of 150 rna while signals are in the
range of 1 to 2 mv. Multiturn windings can be
used for sense lines and/or word lines to improve
the efficiency of planar film elements because the
drive requirements are inversely proportional to
the number of turns while the signal output is
theoretically directly proportional to the number
of turns. This paper describes the design of a
74000 bit planar thin film memory using a multi.turn sense-digit structure but using single lines
for word drive.
strates approximately 3 in. square (Figure 1).
A layer of SiO is deposited over the film for protection. Typical values for Hc and Hk are 5.0 and
4.8 respectively. The aluminum substrate serves
as a ground plane and also. plays an important
role in obtaining virtually creep free films.
System characteristics
The memory is organized into 1024 words of
72 bits each, using 24 film planes in two 3 X 4
back-to-back arrays as shown in Figure 2. Word
Design goal
The prime purpose for design of this system
was to obtain a planar thin film memory concept
which would be compatible with standard integrated circuits and yet retain relatively high performance characteristics. Cost, power, and reliability as always were also important considerations.
Film characteristics
The magnetic films used in this system are continuous sheets of 1100 A Ni-Fe-Co film evaporated
on electro-chemically polished aluminum sub·Pohm, A. v., "Magnetic Film Scratch-Pad Memories," IEEE
Transactions on Electronic computers, Vol. EO-I5, No. 4 August
1966.
FIGURE 1-Film plane
1219
1220
Fall Joint Computer Conference, 1968
FIGURE 4-Bit geometry cross section
FIGURE 2-Film plane array
lines are etched from copper-Mylar** laminate and
are 10 mils wide on 20 mil centers, approximately
10 inches long. Sense-digit lines are made from
insulated 4 mil round wire wound into 4-turn flat
coils approximately 13 inches long held in place
by Mylar cladding. These flat coils shown in Figure 3 are on 80 mil centers. Since there are two
**Trademark of E. I. du Pont de Nemours & Co.
BIT1{
C
BIT2{C
BIT3{
C
2 SPOTS PER BIT
:I:
:1:1
.080
crossings of each coil for each word line, there are
necessarily two memory elements per bit. Furthermore, since the flat coil serves both as the
sense signal pickup coil and the bit drive line, the
two elements receive opposing easy-direction fields
and are always magnetized in opposite directions.
Thus, the signals from the two elements switched
by rotation in the conventional DRO mode are
additive in the coil and appear in differential
mode at the coil output terminals. As Pohm indicated, the sense line does not behave like a
transmission line but like a lossy inductive pickup coil.. If this were not the case the signals
would not be additive at the output terminals
because of time delays in the 13 in. long coil.
The memory cell cross section, shown in Figure
4~ consists of the aluminum plate with film on
the upper surface, an overlay of word lines fol..
lowed by an overlay of sense-digit lines, the word
LOWER HALF
UPPER HALF
WORDLIN~
~~
FIGURE 3-Memory element geometry
FIGURE 5-Sense-digit channel
Design of Small Multiturn Magnetic Thin Film Memory 1221
12
>E
~
....
iodes are included on both ends of the word lines to prevent
"half select" currents in unselected lines during
word current transients.
All of the logic circuitry, is accomplished using
standard series ·74 networks. System timing is
achieved through the use of tapped delay lines
so that no one-shots or other adjustable devices
are required. In fact, there are no controls· or
·other variable elements in the entire memory.
Physical specifications
The memory package shown in Figure 10 is
designed for 19 in. rack mounting with a panel
height of 3 112 in. 'and a total depth of 20 in. The
weight is approximately 35 lbs. The power dissipation of the memory is less than 60 ;w:atts. This
relatively low power level is primarily due to the
saturated stage nature of TTL networks used
throughout.
Memory performance characteristics
The sense amplifier analog output is shown in
Figure 11. Signals for both Is' "and Os' are shown
superimposed for one particular bit channel with
all 1024 words of the memory operating. Note
that the recovery pattern indicates a minimum
cycle time of 350 ns can be achieved using this
technique, although the memory was originally
designed for application as a 500 ns cycle time
system. Similarly, the design goal for access time
of 250 ns was also achieved.
CONCLUSION
FIGURE 10-Memory photograph
A planar magnetic thin film memory has been
designed and bunt by Texas Instruments using
all integrated circuits for electronics achieving a
cycle time faster than 500 ns, and an access time
of 250 ns. The memory is organized as 1024 words
by 72 bits in order to balance the costs of the
word drive circuits against the sense-digit cir-
Design of Small Multiturn Magnetic Thin Film Memory 1223
cuits. The inherent advantage of this particular
organization is that the computer can achieve
speed advantage not only because of a fast repetition rate, but also because four 18 bit words are
accessed simultaneously. (Comparable core memory designs are ordinarily organized 4096 words
of 18 bits each.) The outlook is for higher speed
(faster than 150 ns) memories in similar organizations to be developed in planar magnetic
films. The cost of these memories will be COID-
petitive with 2112 D core memories of the same
capacity but the organization and speed can be
considered to offer at least a 4: 1 improvement in
mUltiple word accessing and a 3:1 improvement
in speed. As a result of this, more computers will
be designed to take advantage of the long word
either by extending the word length of the computer itself or by ordering instructions and data
in such a manner that sequential addressing will
be required a large percentage of the time.
An adaptive sampling system for hybrid computation
by GEORGE A. RAHE
Naval Po~tgraduate School
Monterey, California
and
WALTER KARPLUS
University of California
Los Angeles, California
INTRODUCTION
Redundancy in 8ynchronou8 8ampling
In most data processing and hybrid computing
The concept of sampling is central to the operation of
all systems in which analog information is to be pro- . systems, the sampling rate is dictated by specified error
bounds upon the reconstructed signal. If the continuing
cessed by a digital computer. In conventional hybrid
analog signal is sampled and processed by a digital
computing and data-processing systems the continuous
computer, itmust be possible to reconstruct a continuanalog signal is represented by an amplitude-modulated
ous signal from the samples so that the maximum
pulse train in which the pulses occur at fixed intervals of
difference between the reconstructed and the original
time. Such synchronous sampling facilitates control by
signal nowhere exceeds a specified tolerance. In accordthe digital computer clock and requires a minimum
ance with the well-known sampling theorem, this
amount of equipment. In many applications, however,
sampling rate is based on the largest magnitude and the
it is important to minimize the number of samples emhighest frequency components the signal is expected
ployed to represent the analog signal. For example in
to attain. Actually, the analog signal may never attain
telemeter applicat.ions, it is important to economize
these maximum magnitudes or frequencies, or it may
transmitter power by limiting. the number of samples
attain them for only brief periods of time. Therefore, the
transmitted over long communication links.
utilization of fixed sampling usually leads to a large
In hybrid computation, power conservation is not a
number of unnecessary samples, samples which can be
primary objective, but high sampling rates often tax
eliminated without deteriorating the quality of the reseverely available digital computer memory capacity
constructed signal. Ih essence, the synchronous train of
and the band-width of data channels. Not infrequently,
samples contains redundant information, and the
. high sampling rates limit .the number of analog channels
various data-compression schemes are intended to
which can be accommodated by a given analog-digital
interface. Accordingly, a variety of so-called data-. minimize this redundancy. A number of proposed datacompression methods involve the suppression of recompression techniques have been proposed, techniques
dundant samples. In that case the analog signal is
which are designed to reduce the number of samples
sampled, and the sample is analyzed to determine
which must be transmitted across an analog-digital
whether samples can safely be omitted from the signal
interface without exceeding specified error bounds.
transmitted to the digital computer. An alternate
The system described· in this paper represents a
approach, proposed in this paper, involves the utilinovel approach to this problem. It differs from conzation of an adaptive sampling system so that the
ventional data-compression techniques in that the
analog signal is sampled only as often as neceessary,
analog signal is modified or SUbjected to an approxibut all samples actually taken are transmitted to the
mation prior to sampling. The theory underlying this
digital computer. The sampling interval is therefore
method is first briefly developed below, followed by
continuously and automatically controlled as a function
description of a hybrid computer mechanization of the
data compression syst"em.
of the analog signal activity.
1225
1226
Fall Joint Computer Conference, 1968
Accuracy constraints
The accuracy demanded of a sampled data system
of the type considered in this paper. is dictated first of
.all .by the characteristics of available hardware. Thus '
It IS unreasonable to attempt to reduce the reconstruction error below the combined magnitudes of
the various error sources inherent in the hybrid system.
These error sources include particularly the drift,
zero-offset, phase-shift, and noise in the analog portion,
and the quantization error (related to the word-length)
on the digital computer.
. The purpose to which the data is to be put also
dIctates the form of reconstruction and therefore the
control laws for the sampling operation. Consider for
example the operation of graphic CRT terminals in
hybrid computation where analog signals are to be
displayed on one or more such terminals. Commercially available terminals represent a function by a
series of straight line segments to an accuracy of from
1%to .5%. Line segment generators require only the
origin and terminus of a line segment to produce the
req~red line. ~or the purposes of this type of applicatIOn, a samplmg control law is required which will
provide a reconstruction by linear interpolation to a
predefined maximum error, with the minimum number
of lir:e se~ments, and in real time. In addition the apprOXImatIOn must be continous at the end points of the
line segments in order not to be objectionable to the
user. "
Definition of the approximation - continuous secant
The nature of the reconstruction to be considered
and some of the properties of the approximation
wIll ~ow be described. Consider that the function cf>(x),
contmuous on a closed interval (a,b), is to be approximated by line segments P i(X) over subintervals
h~re
.6 i
= (Xi+l - Xi) i
~i
The set of line segments P i(X) which form the best
approximation to cf>(x) are defined to be those which
mi~imize the nllmber of segments n for a given predefmed tolerance E. The defihition that cf>(x) is continuous in the mathematical sense will of course present no restriction on mechanizable functions.
It can be readily shown 3 that a minimum of nonunique number of line segments on a closed interval
a ~ x ~ b is made up of the set determined by the
maximum line segment with orgin at a point (a) and
maximizing the length of each succeeding line segment
adjoining them at their end points until a segment is
determined which contains the point (b).
. The problem of finding the optimum sampling points
~s reduced t.o dete~mining the largest value of A i in any
mterval whICh satisfies the predefined error.
Determination of approximati~n interval
Before proceeding with the derivation of the control
laws for determining the maximum approximation
interval, it will be advantageous to consider the nature
of the function cf>(x) to be approximated. The continuous function cf>(x) to be approximated on a certain
finite interval has, in most cases, a fixed direction of
cor:c~vity (upward or downward) which changes only
a fmIte number of times. Such functions will be referred
to here as "piecewise convex or concave".
Without loss in generality, the study of conca ve
function cf>(x) is reduced to that for convex function
- cf>(x) and defined as follows: Definition: A function
cf>(x) is convex on the interval (a,b) provided that2
.
cf>(p.fj
1, 2, .... n such that l
=
hi = cf>(Xi+I) - cf>(Xi)
+ (1
- p.) a)
(a, fj) C (a, b) "
a ~ x ~ b
Maxlcf>(x)
(1)
~
p.cf>(fj)
+ (1
- p.) cf>(a)
(2)
P.E(O, 1)
i=l
The plot of a convex function cf>(x) in cartesian coordinates, therefor~, is characterized by the property
that any arc of the plot has all of its points located not
higher than the secant chord that joins its end points.
For the purposes of exposition only, consider cf>(x)
twice differentiable on the interior interval Xi < x < Xii-I"
then
.
where
Pi(x) = ai
+ bix
P~(x) = 0
and
n
L,:-1 ~i =
(a, Xl)
+ (Xl, X2) + ...
(Xn-l, b)
(a, b)
(3)
An Adaptive Sampling System for Hybrid Computation
A vaiue of x = Xi+l is sought such that the maximum
deviation of cf>(x) from the secant P(x) is equal to E in
the interval Xi .::; X ~ Xi+11 where
P(X) = cf>(Xi)
+
cf>(Xi+l) - cf>(Xi) (x - Xi)
Xi+! - Xi
taking the derivative
(4)
then there exists a Xi+! such that:
P(X) - cf>(X) = E
1227
(9)
From which
Xi
<
X
<
Xi+l
(5)
dcf>(x)
dx
= cf>(x) - [cf>(Xi) X -
E]
= M2(X)
(io)
Xi
Substituting equation 4 into equation 5
For
cf>(Xi)
+ cf>(Xi+!)
- cf>(Xi) (x Xi+l - Xi
Xi) -
cf>(x) = E
So that the value of X = Xi+! is that value of Xfor which
or
(11)
(6)
defining
M (x) = cf>(x) -. [cf>(Xi) - E]
3
X - Xi
as is shown in Figure 2a.
In an entirely parallel development for the case where
cf>(x) is concave:
· M ()
cf>(x) - [cf>(Xi) + E]
D efi Ulng. 1 X = ~-=-..-::..:..-.;.---:...----=.
X - Xi
(7)
and
then
Xi+l
(12)
is that value of x for which
Ma(X)
M (x) = cf>(x) - cf>(Xi)
2
X - Xi
< MaxM 1 (x)
(13)
XEAi
as is shown in Figure 2b.
It is seen· from Figure 1 that the slope pf the tangent
line UV is equal to the minimum value of M 3 (x) so that
the value of X = Xi+l is sought such that:
~
E
I
Figure 2d
Figure 2b
c:p (x)
...
:Q-
2
~....
P~x),. .-),..........
. .-
Ma P(;,
... .......
R
...
E
::.----
MIN Ma
u
~------~
Xi+1
Xi
Figure 2a
E
~
MIN Ma
X'I.
Xi+1
Figure 2c
Xi
FIGURE 1-The continuous secant method.
FIGURE 2-Behavior of the secant method for (a) convex
interval; (b) concave interval; (c) concave-convex interval;
(d) convex-concave interval.
1228
Fall Joint Computer Conference, 1968
Consider the case now where cp(x) is not strictly concave or convex in an interval. If the curve is concave
convex as in Figure 2c, the maximum excursion of cp(x)
from MaxM1 (x) must have been less than E in the
concave portion. Since M 2(x) at x = Xi+l must be greater than MimM 2 (x) in the interval, then the error in
approximation over the concave portion must be less
than E. Which is to say that the interval is effectively
convex to within a predefined error E. A similar argue
ment follows directly for the case where c/>(x) is convexconcave, as shown in Figure 2d.
Analog
Memory
_1_
r------ -I
t-t
o
t-t
~
o
(t)
Summary of control laws for the determination
of sam ling points
The general control laws for determination of the.
optimum sample points may now be summarized as
follows:
Defining
M1(x)
=
cp(x) - [cp(x,)
+
E]
x - Xi
M 2(X) = cp(x) - CP(Xi)·
x - Xi
(14)
FIGURE 3-Mechanization of the control laws for the secant
method.
Successful Runs
Ma(x)
=
Unsuccessful Runs
cp(x) - [CP(Xi) - E]
x -
and x
>
•
Significant Samples
Xi
Xi.
¢
(x)
-,--, - - - ---- --
The sample point Xil-l is given by the minimum value
of X for which either of the following logical equations
is satisfied:
I
"
I
,
I
I
.
.
I
1.
(15)
II.
(16)
M eehanization of the hybrid interpolator
A primary concern in the development of any sampling control law is ease of mechanization. A functional
diagr~ of the mechanization of the proposed hybrid
interpolator is given in Figure 3. While an all analog
mechanization encounters certain difficulties, modern
hybrid multipliers are suited to divide by a parameter
as restricted as time. Equipment will allow updating of
time at a 500· kHz rate. The suitability of this method
was verified by simulation on a hybrid computer system.
By contrast, the operation of a pure digital interpolator is illustrated in Figure 4. The interpolator
Sample·
Interval
--t.1. ......
fs .
FIGURE 4-A digital linear interpolation.
forms a straight line with f(O) as the origin and f(2)
as the terminus, and computes a value for the intervening sample f (1). If that value is within tolerance a
new line is formed with f(3) as terminus and both
intervening values must be computed and compared
with the actual values. If either value is not within
tolerance f(2) is transmitted and becomes the origin
of the next line. This procedure has two significant
failings: first, the operation requires· at least one subsequent value of the function in order to make an
approximation, and second each intervening point
An Adaptive Sampling System for Hybrid Computation
. must be reapproximated at every new interval. It
follows then that for a line lenght of n intervals, s = n/2
(1 + n) intermediate points must be calculated and
compared with the actual sample values. Even for rela:tively smaIl values of n the computation time prohibits its use in most applications. .
A determination of efficacy
1229
number of sampling methods was determined on an
IBM 7094 computer. The results of that study are presented in Table I. This summary indicates that even
under worst case conditions the proposed system
demonstrates a marked reduction in the number of
samples required for reconstruction to a fixed predefined error. Certain familiar reconstructions were
included for the same relative RMS error for comparison purposes. I ••
Choice of test signal
In order to compare various sampling systems it is
necessary to define an appropriate test signal. Two
considerations prompt the selection of a signal which
is a worst case for adaptive sampling: a) The resulting
compression provides a lower bound on system performance; and b) it provides a measure of system
susceptibility to the generation of more samples than
a suitably formulated synchronous system.
Since the adaptive system samples on the basis of
both amplitude and frequency, a worst case would be
one which is characterized by a flat power spectral
density over the total predicted bandwidth (a maximum information signal).
Such a signal which is easily generated and easily
described in both statistical and deterministric terms
can be constructed from a sum of sine waves.'
N
t/>(t) =
L
,.-1
&"sin(c.).t
+ 8.)
(17)
For eight or more non-harmonic related sine waves.
the probability density function becomes indistin~
p;uishable from the Gaussian one.
The operation of a sampling system in the presence
of source noise is often neglected since noise over the
entire predicted bandwidth works to reduce sample
reduction and also precludes the successful operation of
many proposed systems which rely on measurement.
of the derivatives of the function to be sampled.
In the absence of noise, adaptive sampling can be
expected to reduce the sampling rate by additional
factor of ten when the signal occupies only one tenth
of the predicted bandwidth. However, noise can be
expected to occupy the entire band and the effect of the
presence of this noise is paramount to the evaluation
of adaptive system.
In order to evaluate this effect, noise with a flat
spectral density, a Gaussian distribution and· RMS
level equal to half the predefined tolerance and cut off
at 18 db per octave at a frequency ten times the highest signal frequency was added to the signal. The
effective sampling rate even at this excessive noise
level was increased by only twenty percent over the
rates determined for the noise free case.
CONCLUSIONS
Comparison of sampling rates
The sampling rate for a fixed maximum error for a
SAMPLES/
SAMPLING
CYCLES OF
RMS
RECONSTRUCTION HIGHEST ':ERROR
METHOD
FREQ.
(%)
Butterworth
4-stage filter
8.0
2.0
Linear phase
4-stage filter
15.0
2.0
Zero-order hold
628
First-order hold
62.8
First-order (Synch).
interpolator
22~2
Continuous Secant
6.7
1.76
Source noise
PREDEFINED
TOLERANCE%
FULL
SCALE
:±:.5
:±:.5
An algorithm has been presented for the determination of a continuous polygonal approximation which
results in the least number of samples for a given predefined maximum error where the end points of the
line s~gments are restricted to lie on the function. The
method is suitable for general application since it requires no apriori knowledge of the properties of the
function to be sampled. The method has been shown
to provide a reduction in the sampling rate even under
worst case conditions and to operate effectivelv with
little degradlttion in performance when the signal is
corrupted by noise.
ACKNOWLEDGMENT
:±:.5
:±:.5
TABLE I-Relative sampling rate (fr) and RMS error vs.
predefined tolerance for test signal input8•6
The studies described in this paper were sponsored in
part by the National Science Foundation under a grant
to the Department of Engineering, University of
California at Los Angeles, and by the U. S. Naval
1230
Fall Joint Computer Conference, 1968
Ships Systems Command under a contract with the
Department of Electrical Engin~er~g, Naval Postgraduate School, Monterey, California. The authors
also gratefully acknowledge the courtesy extended to
them by the Electronic Associates Inc. Computing
Center, El Segundo, California, and by Mr. J. Magnall
formerly the director of that center.
cp (t)
Continuous Function
BIBLIOGRAPHY
1 DE LA VALLEE-POUSSIN
Lecon,s sur l'approximation des jonctions d'une variable reaZle
Paris 1919
2 JWYOUNG
General theory of approximation by functions involving a given
number of arbitrary parameters
Trans-American Math Soc 23:331-334 July 1907
3 GARAHE
Adaptive sampling
PhD Dissertation UCLA 1965
4 L W GARDENHIRE
Redundancy reduction the key to adaptive telemetry
Nat Telemetering Conf Los Angeles California June 1964
5 RKSISKIND
Probability distributions oj sums oj independent sinusoids
Technical Memo No 83 Systems Technology
Laboratories Inc Ingelwood California March 1961
6 DDMcRAE
Interpolation errors
Radiation Inc Reports 1 pt 1 May 1961
cp • (t)
Sampled Function
CPiOH
cPFOH
Output Zero-order Hold
-
Output First-order Hold
APPENDIX I.
FIGURE A. I-Zero and first-order holds.
Synchronous sampling in hybrid computation
The reconstruction of signals in hybrid computation
have been restricted in general to the simple zero and
first-order holds shown in Figure A.I. Since the error
in computer systems is generally required to remain
within a predefined tolerance E, the synchronous
sampling rate is dictated by the smallest interval in
which this tolerance can be reached.
From Figure A.I, the reconstruction by a zero-order
hold is seen to be glven by the value of the functions at
the last sampling instant nT. The output of the zeroorder hold cJ>ZOH (t) is given by:
cJ>ZOH(t.) = cJ>{nT)
nT
<
t
< Cn +
I)T
(A.I)
for which the construction error eZOH(t) is given by
(A.2)
the maximum full scale relative error becomes
emaa:
where n
T
Since
=
=
=
Max eZOH(t)
2A
(A.4)
nwT = 211"
(A.5)
= 1I"/n
(A.6)
then
ema;e
and for a predefined tolerance E, the sampling rate n is
given by
n>_11"_
(A.3)
2A
the number of sa,mples/cycle
sampling period
For an input signal cJ>(t)
cJ>(t) = A sin wt
AwT
E/2A
An Adaptive Sampling System for Hybrid Computation
1231
Choosing a value of relative error which is used to
evaluate the Secant Method, e max < .5 percent, the
sampling rate (n) for the zero order hold is found to be:
n
>
638 samples/cycle.
(A.8)
The number of samples required when reconstruction
is performed by a first-order hold is derived in much the
same fashion. The output of the first-order hold can be
written as follows:
c/>FOH(t) = 2(t - T) - c/>(t - 2T)
.5 percent is
n # 62.8 samples/cycle
(A.12)
Similarly the sampling rate for a linear interpolator can
be shown to be:
(A.9)
Max eLI(t)
2A
and the error for a first order hold eFOH becomes
~OH =
<
and the sampling rate for e max
therefore
c/>(t) - 2c/>(t - T) - c/>(t - 2T) (A.I0)
n
In the case of the sine wave input
>
< ",2T2
= ~
-
>
16
4n2
(A.13)
__1__
2 VE/2A
~
Again for a maximum relative error of .5 percent
c/>(t) = A sin wt
n
the maximum full scale relative error is given
(A.ll)
>
22.2 samples.'cycle.
(A.14)
A new solid state electronic iterative differential
analyzer making maximum use of integrated circuits
by BRIAN K. CONANT
University oj Arizona
Tucson; Arizona
INTRODUCTION
The feasibility of really fast hybrid computation was
demonstrated by the development and application of
The University of Arizona's ASTRAC 11. 4 ,8,10 But,
no machine commercially available to date has the
required mode-control switching speed and lowimpedance computing networks; and most computers
do not have the required amplifier bandwidth. The
development of the LOCUST system represents an
attempt to design a truly producible very fast computer at moderate cost.
The new machine was developed as a project-group
Ph.D. dissertation, a somewhat novel concept in
engineering education: The writer acted as a project
engineer on the overall design, test,and application of
the LOCUST computer and helped to supervise four
M.S. thesis projects14 ,17,19,21, plus several term-paper
projects1 ,2,/i,20, which contrihuted significant components. The computer, including all printed circuit
cards, was built by undergraduate student technicians,
using Motorola and Fairchild integrated circuit modules
and discrete components.
The LOCUST system is an all solid-state iterative
differential analyzer making maximum use of integrated circuits (Figure 1). The machine comprises 34
free amplifiers of which 16 can be used as integrator/
track hold circuits, plus 18 amplifiers permanently committed to 6 high-speed multiplier/dividers, and 4 comparators (56 amplifiers total). The new machine is
capable of solving a sixteenth-order linear or non-linear
differential-equation system up to 2000 times per second
for iterative and random-process computations under
digital control. 4 Linear errors are within 0.2 percent up
to 10 kHz. Special "slow'" summing networds also
permit operation as a slow analog computer. The following design featu:res are of special interest:
1. Maximum use of both linear and digital monolithic integrated· circuits enhances computer performance and still reduces parts and assembly
costs.
Figure I-The LOCUST computer, built in the University
of Arizona's Analogjhybrid Computer Laboratory. Linear and
digital integrated circuits enhance computer performance and
still. reduce parts and assembly costs
2. New mounting and shielding te,chniques, including a technique for shielding low cost unshielded
patchbays, were developed (Figure 2).
3. Low level current-mode digital logic modules
(Motorola, MECL, integrated circuits) el~inated
digital noise in the analog portion of the computer.
The low-level logic swing (0:8 V) along with the
balanced·-current nature of the non-saturating current mode logic serve to reduce radiation and,
more importantly, computer ground-system disturbances.
1233
1234
Fall Joint Computer Conference, 1968
Figure 2-Analog-circuit boxes and digital-circuit cards
plug directly into the rear of inexpensive low-leakage plastic
patchbay receivers. Rows and columns of patchbay springs used
for grounds, power connections, and logic also serve as analogpatchbay shields. Simple metal patchboards with shielded patchcords have patch holes only for the actual analog-computer
terminations for an uncluttered appearance. Summer-integrator
patching is logic controlled and does not require cumbersome
bottle plugs
the gain/bandwidth requirements of fast analog computation with the aid of a new high-performance amplifier developed at The University of Arizona as an M.S.
thesis ploject; 14 the reference describes its design in
great detail. The performance of the new amplifiers is
summarized in Table 1a.
The block diagram of Figure 330 shows the basic amplifier design, which employs a three-channel feed-forward circuit. Beginning from the amplifier input, the
channels are: the high-frequency channel directly to the
wide-band class AB output stage, the intermediate-frequency channel through a Motorola MC1433 integrated-circuit operational amplifier, and the low-frequency channel through a Fairchitd ~726C hot-substrate preamplifier.
The bandwidth and output-current limitations of the
MC1433 integrated-circuit amplifier are overcome by
cascading it with a high-current output stage and by
feeding forward the high frequency signals directly to
the output stage from the summing junction. Because
LOW-FREQ
CHAI'REPEAT
$ EEEEJ $ EEE8
n
SET
DIGITAL
PATCH BAY
n<
N
N
EEE
T
SCAN
SCAN
\. .2
Clock and repetition-rate selection
A frequency-dividing counter chain receive~ 4 MHz
pulses from a crystal-controlled clock and delivers
timing pulses whose frequencies are 4 MHz, 2 MHz,
1 MHz, 500 kHz, 100 kHz, 50 kHz, and 10 kHz for
control and display purposes. From these, the repetition-rate selector switch selects a clock pulse train (CI)
1239
REV
SCAN
(~
T2 OR 10
Figure 9-LOCUST digital module panel
(~)
1240 ~. Fall Joint Computer Conference, 1968
In normal repetitive operation (Figure lOa), the int.egrator control pulse R is equal to logicall at t = 0 and a
logical 0 at t = T thus producing periodic pulses so
that COMPUTE periods of length T alternate with
RESET periods of length TR - T. Note that one can
independently select TR (with the repetition rate selector)
and T (with the thumbwheel decade switches). The
output at t = tl milliruns feeds a timing logic block to
produce periodic sampling pu'ses 81 and also delayed
sampling 'pulse 8 m of length Ts . ';= T R/I0 for
special track-told-pair oper~tions. 8
track-hold circuit controlled by 81 will periodically TRACK for Ts
Ai
o
milliruns and then switch into HOLD at t = tl milliruns. Sm switches Ts milliruns later than Eh for
memory pair or memory triplet (when l,lsed with R)
op,eration.
All timing pulses, RESET pulses and TRACKHOLD cdntrol pulses are available on the digital patch.
bay for flexible control and timing of individual integrators, switches, and digital operations. In normal repetitive hybrid-computer operation integrators are controlled by R; and the track-hold Qircuits are controlled
by SI for digital readout of sample values X(t1) at the
accurately ~et oomputeI time t 1• Different patohing
1000 R
100R
lOR
DIGITAL PATCHBAY
TERMINATlON
R
MASTER
4 MH~
CLOCK - PULSE
GENERATOR
AND
COUNT DOWN
LOGIC
2000
1000
TIMER
r-
·R
T AND t, THUMBWHEEL
SWITCHES
500
250
RESET
100
50
10
KHz
EXT•.
Y
AUXILIARY
TIMER
S
REPETITION
RATE SWITCH
4MHz
t2 0 R
2MHz IMHz
SUBROUTI NE
COUNTER
COUNTS R
OR
PATCHED AS
FREE COUNTER
nAND N THUM8WHEEL
SWITCHS
Figure 9-: block dIagram (b)
'TO THUMBWHEEL
SWITCH
R'
Solid State Electronic Iterative D,ifferential Analyzer
102 PtJLSES
-I
1 - - - - - 1000 PULSES
,I
+'C:":'"IYnT'n"IT!TTTmITTTT""'T""--- iii iii iii iii iii i' iii iii
r-
RI
iJ
10 WS DEL.AY
COWUTE
RESET
~----------
......--------
------ - - --.......-------
R'
I-::===-~N~COM~PUTER RUNI_-=====:::;--"'1'I
I1\
COMPUTER RUNS - - - -
LJ - --
t..i.INITIAL. RESET
Figure lO-(a) Timing and control signals for normal repetitive operation and (b) control signals for SCAN 1 operation
connections can em ploy R, S1, and S1D to produce very
flexible memory and timing control.
A patchable master timer-reset input allows one to
reset C1 and permits finer control of the computer-run
period than is possible by the normal coarse repetitionrate selection. For instance, one can use 81 to reset C1
at t 1; this will reset integrators for 102 milliruns and
start a new COMPUTE period of duration tl milliruns.
Many other possibilities exist. One may also patch to an
external clock. One can also interrupt the C1 pulses with
a digital-computer control signal. It is also possible to
control the length of individual computer runs with
patched comparator logic to conserve time in long computations.
The auxiliary timer
The auxiliary timer (C 2 counter) is another threedecade counter with a thum bwheel decade-switch
preset output. The 8 2 function swtich controls
the operation of the C 2 counter and its associated
logic. For the different 8 2 function switch settings, the
thumbwheel switch, "t2 -or 7'D", functions as follows
(1 efer to Figures 9 and 10).
1241
T2.position-T~e trailing edge of S2 (TRACK to
HOLD) occurs t2 milliruns after the start of each
COMPUTE period.
2. 7'0 position-The trailing edge of ~ occurs at
t1 + 7'0 milliruns after the start of each COMPUTE period. Thus the "~ or 7'D" thumb wheel switch
directly sets a delay interval of length 'TD between the
8 1 and S2 sampling pulses. When S1 and 82 are
used to control track-hold circuits, the sample
pairs X(t1), Y(t1 + 'To) are produced, e.g., for correlation and prediction studies.
3. -T position-The trailing edge of S2 now occurs at
T + 1i2 milliruns after the start of each COMPUTE period. S2 and S20 then serve for readout
during the RESET period, as S1 and Sm serve during the COMPUTE period. This is useful for "alternating" differential analyzer runs using integrator
groups controlled by R and It
4. SCAN 1 position-C2 recycles after 1,000 + M
milliruns where M is 1, 10 or 100 millruns selected
by the scan increment switch. On the first run, the
trailing edge of 8 2 occurs at t2 milliruns; on the
second run ~ occurs at t2 + M milliruns; on the
third at t2 + 2M milliruns, etc. (Figure lOb).
Track;'hold circuits controlled by S2 and S20 wiU
then "scan" periodic computer runs Jor readout into
slow recorders, printers, or digital computers. With the
repetition rate switch set at 100 and M set to 1, for
instance, a complete solution scan requires 10
seconds.
5. SCAN 2 position-The subroutine counter (Ca
counter) permits the scanning 8 2 to step forward
by M milliruns onlyofter a preset number, N,
computer runs or N other events. This feature is
used for automatic computation of random-process
statistics (correlatiOn Junctions, delay errors) over samples oj N computer runs.
6. REVERSE SCAN position~On the first run, the
trailing edge of 8 2 occurs at 1i2. milliruns; on the
second run S2 ends at t2 - M milliruns and COntinues to scan backwards in steps of M milliruns
1.
The SCAN modes are useful for slow recording of
repetitive solutions (X vs. t, or Y vs. X), but also for
automatic parameter changing (new values of a repeti·
tive-analog-computer solution are used in successive
computer runs,) for multiple-solution oscilloscope displays and for solution checks with slow computers. The
REVERSE SCAN mode is useful for computing convolution integrals, for backward integration (e.g., in
boundary-value problems), for modified-adjoint-system
techniques, and for controlling delay-line-memory read/
write cycles. The SCAN 2 mode is, as noted earlier, intended for automatic computation of statistics over N
computer runs.
1242
Fall Joint Computer· Conference, 1968
Subroutine counter
The subroutine counter Cs (Figure 9) is a four-decade counter with dual thumbwheel switch preset· outputs and is patohed to l ount computer runs, comparator
output steps or other events. Cs produces preset .oounter outputs after n aLd N events (OS of heating in the atmosphere
must be sent back to outer space. This ultimate return
of energy to space is in the form of low-temperature
terrestrial radiation. Figure 6 sh~ws the two curves.
One represents the annual mean of solar radiation
absorbed by the earth and the atmosphere, and the
other the outgoing terrestrial radiation from the
atmosphere, both as functions of latitude. 26 •27
At low latitudes the earth-atmosphere system gains
more heat energy per unit area by the absorption of
short wave radiation from the sun than it loses to space
by the emission of long-wave radiation; the reverse
happens at high latitudes. The net radiation gained by
the earth-atmosphere system at the equator is, for
example, about 100 ly/day,* while the net loss at the
North Pole is about 260 lyjday. At a latitude of 38°,
the incoming and outgoing radiation are balanced.
It is clear that the surplus heat energy in the tropics must somehow be carried to the poles. Otherwise,
tropical regions would become steadily hotter and
polar rep-ions steadily colder. About ten percent of the
surplus heat is transported poleward by ocean currents.
The remainder. is transported by the atmosphedc
circulation, including both the large-scale eddy motions
(which are cyclones and anticyclones) and the mean
meridional circulations.
Since atmospheric motions are generated by nonuniform heating of the air, a physical prescription is
needed for the heating rate, Q, in the thermodynamic
equation (5). In general, the following three processes
(expressed as rates) are important in the atmosphere
(Figure 9): heating from radiational sources, denoted by
Qa; the release of lateJlt heat by condensation, denoted
*ly is an abbreviation for langley, a unit equal to one gram
calorie per square centimEter.
by Qc; and heating/cooling due to eddy diffusion,
denoted by Qd.
The rate of heating due to radiational sources, Qa,
may be divided into two parts: one is the rate of heating
due to absorption of solar insolation in the atmosphere,
Qa", and the other is the rate of heating/cooling due
to infrared radiation, Qat. These terms can be evaluated
by integrating the transfer equations, taking into
. account the distributions of water vapor, carbon
dioxide, and ozone, the major absorption gases in the
atmosphere.
However, the amounts of Qat and Qat are considerably altered by the presence of clouds in the atmosphere. The evaluation of Qc, the rate of released latent
heat of condensation, is, of course, directly dependent
on the prediction of cloud formation. Thus, the prediction of clouds is one of the important aspects of a
general circulation model.
The moisture field of the atmosphere is continually
replenished by evaporation from the earth's surface.
Since heat is required to evaporate water, and heat is
released by condensation of water vapor, the evaporation process transports latent heat from the earth's
surface to -the atmosphere. Similarly, sensible heat is
transported from the surface to the a~mosphere, and
vice versa, by the actions of small-scale turbulence and
convection.
The direction of energy flow, in the form of latent
heat and sensible heat, is determined primarily by the
difference between the temperature of the ear;th's surface and the air temperat.ure directly above it. Thus,
it is necessary to calculate the temperature of the
earth's surface.
The temperature of the earth's surface is determined
Computer Experiments in Global Circulation
1265
...
STRUCTURE OF THE LOWER ATMOSPHERE
SURFACE TEMPERATURE CALCULATION
O"T: + E.l
+ Es + M - (0 + 50 ) = 0
where
SOLAR 'RADIATION FLUX
FREE ATMOSPHERE
500
IV
1000m
PLANETARY BOUNDARY LAYER
DOWNWARD INFRARED RADIATION FLUX
BLACKBODY RADIATION OF THE SURFACE
SENSIBLE HEAT FLUX
(EKMAN LAYER)
50 ,..,
100m
-----------SURFACE BOUNDARY LAYER
LATENT HEAT FLUX
(PRANDTL LAYER)
HEAT FLUX IN SOIL AND WATER
EARTH SURFACE
IJJ7JJ/J/J/J/J/J/JI/JJ/J//J//J/I/J////J// I
~
FIGURE
9~Schematic
structure of the lower atmosphere
(after Sutton)
FIGURE 8-Balance requirement of heat flux at the earth's
surface for calculation of surface temperature
by the balance of energy flux at the earth's surface, as
shown in Figure 8. The surface of the earth absorbs solar
radiation, So, and downward infrared radiation, D,
from the atmosphere. A portion of the absorbed energy
is transported down into the ground by heat conduction
in the soils or is carried away by the motion of water
in the oceans. This quantity is denoted by M.
Energy is also carried away in the form of sensible
heat, E s, and of latent heat, E(. The magnitudes of Es
and E( are dependent on both the thermal and dynamical conditions of the atmosphere and the properties of
soil and water.
The remainder of the absorbed energy is re-radiated
to space as infrared radiation from the earth's surface.
This amount is expressed by i; exp(hA;)
;=1
where the Aj are the eigenvalues of G and 4>i; are related
to the matrix of eigenvectors, e
will be a conservative estimate of the step-size.
Define
n
L
(C i ; - Ak~ij) e;k = 0
i-I
( - A(
km+
) /1) jk
A (HI)
m
= A(0)
m exp
m
= 0,1, ... (9)
"
n
i=1
i=1
L: 4>ii = L: eijJl; =
For E<1 (E«m + l)m+l/(m + I)! ) the limit
in (9) exists and is the solution to (8). A set of values of
Am for m = 1, ... ::.\1 can be calculated for a given E.
Then the variable step sizes are
hm(x) .=A m/A(X)
(10)
(14)
From (13) it appears that A = max IAkl is a plausible
upper bound.
When C is not constant (13) suggests that the repre. sentation
f i(X) ~
L 4>ii(X) exp JX
n
;=1
A less conservative, but intuitively plausible, upper
bound A can be found as follows. Suppose C does not
depend on x for x( ~ x ~ X(+l
f i(Xt)
Aj(Z) dz j
X(
<
x
<
Xl+l
(15)
Xl
may be a useful one if the 4>ij(xl) are computed from
Cii(Xl) and fi (Xl) according to (14), and if the Aj(Z) are
Computational Problem Encountered in Study of Earth's Normal Modes
the eigenvalues of C(z). Substituting (15) into (1) yields
i;
1=1
exp fX Aj(Z) dz
X,e
-E.
[cf/ ,u(x) + CPij(X) Aj(X)
C;,(x) q,.;(x) ] = 0
(16)
A sufficient condition for (16) to be satisfied is
11.
cp'i;(X) =
L
[Cik(X) - OikA;(X)]cpkj(X)
(17)
1275
There are numerous eigenvalue problems that can be
put in the form (22). In many of these problems one or
more minors of Fare sought"It is not uncommon that
the elements of F are large and nearly equal, the result
being that some of the minors are calculated with
severe rounding error. This difficulty can be overcome
by calculating the minors of F directly, as follows:
An n x f. matrix (f. ? n) has N X L minors of order
m ~ f.where
N =
.
(f.)
( m11.) -- ml(n n!
- m)!' L -m
k=1
For x = X,e, cp'ij = 0 so, if we assume a power series representation for CPi;, it has the form
Therefore it is plausible to assume that cp' ij is small comto CPijAj in (16), and that cf>i~ changes siowly in (15). If
so, then A = maxIAk(x) I, x,e < X< X,e+l, is a reasonable
upper bound. It has been our experience that such a definition of Aworks quite well.
To illustrate the method we consider a simple but
characteristic example. Let
When the minors of order m are arranged in an N X L
array in some definite manner the array is called the
mth minor matrix of F [Gantmacher's (1959) compound matrix] which we denote by g:(m).
denote an mth order minor of F
;m=1
o
F idu F ilit
1
•••
F imim X
(23)
C(X) =
f2(x) = J' n(x)
(19)
xE
Then
A = .5/x
+
In2/x2
+ 1/4x
2
-
11
t
where E is the mth order alternating symbol. For example let n = 4,f. = 3,m = 2.
(20)
Given n = 10 and
f1 (1)
=
2.63061 512 (-10)
f 2 (1) = 2.61863 505 (-9)
(21)
we seek f i(X), x = 1.5(.5) 20. We take 1\11 = 8 and use
the one-step Runge-Kutta methods of [Shanks (1966)].
With E = 10-5 we find f i(20) = .1&648540. The correct
value is J1o (20) = .18648 256 giving a relative error of
1.524 ( -5) which is not much larger than e.
A generalization of (1) is the matrix equation
i = 1, .. ·,n;j = 1" "', f.
(22)
(24)
Since F is a solution to (22) we can differentiate (23)
and express the result in terms of C.
1276 Fall Joint Computer Conference,. 1968
+ C'2" F (
h" ·im
-018
)
k 1k2'" k m
+0
(25)
44
-C14
0
-C 14
0
C13
C 12
-Cu
Cu
C22 + C44 C23
C 32
C S2
C 12
0
C22 + 0 33
048
-C42
+
C44
(28)
Thus
ff-'(m)
is a solution of
Notice that trace (e
d
dx
-ff-'
..
(m)
(x)
"
I:e
1:-1
lJ
em)
(x) ff-'
kj
ik
(x)
i = 1, .. " N; j = 1, "', L
trace (l:?(m»)
=
In the special case m
=
(26)
e
where
(m) is a square coefficient matrix or order N.
For example let n = 4, t = 3, n = 2. Then N = 6,
L = 3. We arrange the second order minors of F in the
6 X 3 array
12
F
=
(2»
3trace (C) in general
(m)
12
F
12
11
U
13
13
18
=
= det (F(x»
(29)
(30)
trace (C). Thus
d
dx det (F) = tr (C) det (F).
F
12
eCn)
trace (el
t = n s: (n) is a scalar
s:(n) (x)
and
(;::)
(31)
and
F
F
F
II
18
12
det (F(x) = det (F(xo» exp
f
x
tr (C(z»dz (32)
Xo
14
F
14
F
12
14
a relation known as Jacobi's identity.
For the normal modes of the Earth n = 6 for the
equations governing the elastic-gravitational oscillations. The dispersion relation is a third-order minor of
Fwitht = 3. ThusN = 20, L = 1.
Notice that the N eigenvalues of e (m) are the combinations of the n eigenvaltles of C taken m at a time, a
result related to Kronecker's theorem (Gantmacher,
1959,1,p.75)
As a trivial but revealing example take t = m = n =
2 and
F
23
11
(2)
s:
=
28
F
23
F
11
12
24
F
28
F
28
24
24
F
F
12
12
21
F{x)
14
F
F
12
Then
e
(!.
(2)
(2)
84
34
F
11
21
is th~ array
=
C11
C 32
C42
-C 31
-C.u
0
+C
22
C23
C24
C11 + C 88 C u
C48
C11
C21
0
0
C 21
Cn
-C'1
(27)
=
cosh x
sinh x
[ sinh x
cosh x
Now S:(2) (x) = det (F(x»
For (33)
=
J
(33)
cosh2x - sinh2 x = 1.
:J
(34)
If we integrate (22) to get F(x) for increasing x then, no
matter what precisicim we use in the calculation, eventually rOllIld-off error will cause det (F(x) ) to approach
Computational Problem Encountered in Study of Earth's Normal Modes
zero. However, from (34) we have trace C = 0 so we
know from (26) and (31) that det (F(x) ) is a constant.
C L PEKERIS
F GILBERT G E BACKUS
Propagator matrices in elastic wave and vibration problems
ARCOLLAR
EBSHANKS
Solutions oj differential equations by evaluations oj junctions
Geophysics 31 326-332 1966
Proc Roy Soc A 25280-95 1959
RAFRAZER W JDUNCAN
Elementary matrices
Cambridge London 1960
F R GANTMACHER
Theory oj matrices
Translated from Russian by K A Hirsch 2 vols Chelsea New York
1959
REFERENCES
Z ALTERMAN H JAROSCH
Oscillations oj the earth
1277
Math Comp 21-38 1966
Computer animation and the fourth dimension
by A.lVlICHAEL NOLL
Bell Telephone Laboratorie8, Incorporated
Murray Hill, New Jersey
INTRODUCTION
1\Jan is a creature restricted to a world of three spatial dimensions in which he is reasonably free to move
about at will except for the arbitrary territorial boundaries imposed by different nations. Mari also lives in
another dimension over which he prese~tly has no control other than to watch its continual' forward movement in the mechanical and electrical gadgets he has
devised to measure this dimension which he calls time.
Many people call time the fourth dimension, but because of its many unique qualities I would rather consider time as a special dimension. Therefore, in this paper the fourth dimension is a fourth purely spatial dimension not to be confused with time.
Since we live in a world of three spatial dimensions,
we are unable to visualize a fourth spatial dimension
perpendicular to our three' spatial dimensions. However, the computer is not bothered by problems of human visualization and is able to deal with objects in
four-dimensional space as easily as it performs calculations for three-dimensional objects. Only a fourth number is required by the computer to locate a point in fourdimensional space. But if the computer is to present
the results of its calculations with four-dimensional objects to man, then the computer must come down from
its digital tower and perform the necessary operations so
that man can visualize and possibly obtain some
intuitive feel for the results. The technique of perspective projection from four dimensions to three dimensions is particularly helpful here.
In a previous paper ("A Computer Technique for
Displaying n-Dimensional Hyperobj ects," Communications of the ACM, Vol. lO,No. 8, August 1967,
pp. 469-473), I described in general the technique of
perspective projection of n-dimensional hyperobjects
and also the application of this technique to the production of computer-generated three-dimensional movies of
rotating four-dimensional hyperobjects, and in particular, the hypercube. The mathematical details of this
previous paper will not be repeated here but a physical
interpretation of the results will be explored with
particular emphasis on the purely artistic effects
obtainable with the technique.
A computer technique Jor displaying
Jour-dimensional hyperobjects
The computer performs its calculations and other
operations under the control of a program as outlined
in Figure 1. The computer first reads into its memory
the four-dimensional coordinates of each point of the
hyperobject. Just as three numbers exactly position a
point in three-dimensional space, each set of four numbers exactly positions a point in four-dimensional space.
These points usually are the end points of straight lines
in four-dimensional space, and have been previously
punched onto standard punched cards.
Rotation
After the four-dimensional object has been converted
to straight lines and the four-dimensional coordinates of
the end points of these lines have been read into the
COMPUTER PROGRAM
(I ) READ-IN punched
carcis
contaihing 4D coordinates of
hrperobject
(2) READ-IN punchlct cards
1i':'E!!i1iiEl-.....
~:ini~ rotatian pia,. and
, ) CALaJLATE rotatian of 4D
hypIrobjlct
(4) CALCULATE 4D to 3D
perspective projection
(5) CALQJLATE 3D to 20
perspective projectian
(6) PLOT one fra"" of movie
.--------,
I
I
I
I
I
I
I
I
I
I
I
I'
RAY
I
I
I
I
I
L -_ _ _ _ _.JI
I
I
repeat 'these operations for
eaCh franw of movie
AUTOMATIC PLOTTER
FigUre 1-0utline of computer program and technique used to
generate movies of rotating four-dimensional hyperobjects
1279
1280
Fall Joint Computer Conference, 1968
memory of the computer, the object must then be
moved in some fashion in the four-dimensional space
since a movie of a completely stationary object is quite
senseless to most people.
There are many types of motions which can be considered such as shrinking, expanding, translating, or
rotating the object in four-dimensional space. I arbitrarily decided to restrict the movie to rotation of the
hyperobject in four-dimensional space, but this decision
is unfortunately not enough since some thought must,
be given to exactly what is meant by rotation in a fourdimensional space.
In three dimensions, we usually think of rotation in
terms of rotating an object about some specified axis,
i.e., the axis of rotation. An alternative approach is to
consider the two-dimensional plane that is perpendicular to this axis and define a rotation as a rotation within
this two-dimensional plane. If we define a principal
rotation to be one which involves a rotation about one
of the principal coordinate axes, then the successive
application of three rotations about each of these three
axes can rotate the three-dimensional object to any
specified position. In any ,single plane perpendicular to
one of the principal axes, only two coordinates change
as a result of the rotation in that particular plane.
In four dimensions I have decided to extend this
three-dimensional concept of rotation. However, in fourdimensional space there are many axes all perpendicular
to the same two-dimensional plane so that specifying a
rotation about an axis is both intuitively and mathematically meaningless. The solution is to specify the twodimensional plane in which the rotation is to take place
and to completely drop the three-dimensional concept
of rotation about an axis. Once again, all of this is somewhat arbitrary since one could define other four-dimensional rotations, but I desired a mathematical definition
that was a simple extension of a rotation in three-dimensional space as specified by a two-dimensional plane.
Thus, the computer program next instructs the computer to read in the punched cards specifying the desired two-dimensional rotation planes and the corresponding rates of rotation in these planes as degrees
per frame of the movie.
Perspective projection
Since we are restricted to three spatial dimensions,
it is impossible for us to visualize a fourth spatial dimension. Of course, these problems do not affect the inhuman computer .which purely manipulates numbers
in a mathematical fashion according to specified formulas. But, since we should desire to see the results of
the rotations of the hyperobject in four-dim.ensional
space, the computer must perform some transformation
upon the hyperobject so that we can look at it. In other
words, the four-dimensional object has to be projected
to three dimensions so that we can see it in our threedimensional world.
Just as there were many alternatives for various
motions, there are many alternatives for the type of
projection from four dimensions to three dimensions.
One type of projection is parallel projection in which
the projection lines from the object to the projection
space are all parallel to each other. This is also equivalent to simply eliminating one coordinate in the specification of each four-dimensional point so that one is
left with three numbers for each point in the object.
However, parallel projection is not usually encountered
in our three-dimensional world since our eyes are really
a perspective proj ection system. For this reason, I
decided to use perspective proj ection from four dimensions to .three dimensions. The equations for this
projection are derived in the previous paper and are a
very simple extension of the projection equations for
going from three dimensions to two dimensions. The use
of perspective projection allows one to retain a threedimensional feel for what is happening although absolutely no feel for the fourth dimension in terms of rigidity of the four-dimensional object is obtained as will be
described later.
Plotting the movie
The three-dimensional projection of the four-dimensional object is finally perspectively projected to two
dimensions. These two-dimensional coordinates are
used as input to an automatic plotter consisting of a
cathode ray tube and a camera positioned to photograph the face of the tube. After each single frame of
the movie has been plotted, the computer program instructs the computer to rotate thehyperobject to its
next position, to project the hyperobject to three dimensions and then to two dimensions, and finally to plot
another frame of the movie on the face of the cathode
ray tube. These operations are repeated until the desired number of frames of the movie are obtained.
The hypercube
The four-dimensional hypercube is introduced now
because of its importance in unde~standing the motions
that result from rotations in four-dimensional space.
The three-dimensional perspective projection of a fourdimensional hypercube .looks like a three-dimensional
cube within a three-dimensional cube as depicted in
Figure 2. Some intuitive insight can be gained by considering the two-dimensional perspective projection of a
three-dimensional cube, as depicted in Figure 3, which
looks like a square within a square. What is happening
here is that the face of the cube closest to the projection
Computer Animation and the Fourth Dimension
Figure 2-The three-dimensional perspective projection of a
four-dimensional hypercube is a cube-within.:.a-cube with the outer
cube corresponding to the face of the hypercube which is closest
to the projection space
t
1281
plane appears largest while the face farthest away is
smallest. If the closest face is par~lled to the projection
plane,then its p'erspective projection is undistorted except for its overall size. Thus, the perspective projection
of a three-dimensional cube is actually an undistorted
two-dimensional face within an undistorted two-dimensional face. Since the face of a four-dimensional hypercube is a three-dimensional cube, the perspective projection of the hypercube with one face parallel to the
projection space is a cube within a cube.
When the hypercube is rotated, some very intriguing
distortions occur in the three-dimensional perspective
projection depending upon the choice of rotation plane.
If the two-dimensional rotation plane is perpendicular to
the axis along which the hypercube is being viewed,
then the cube-within-a-cube turns as a whole. If the
rotation plane is not perpendicular to the viewing axis,
then the inner cube enlarges until it becomes the outer
cube while the outer cube shrinks until it becomes the
inner cube. This turning-inside-out motion is to be expected since as the hypercube turns one face comes
closest to the projection plane and therefore appears
largest. All of this is similar to the three-dimensional
cube that rotates in a plane which is not parallel to the
. projection plane except that the faces of the threedimensional cube are squares which distort and change
their size as different faces come closer or recede from
the projection plane as shown in Figure 4.
The four-dimensional cube is of course completely
rigid while it is being rotated, and the turning-insideout motion is purely a result of the perspective projection from four dimensions to three dimensions. It
was hoped that one might be able to obtain some feel
or visualization for the rigid four-dimensional hypercube by observing the three-dimensional perspective
projection but no such feel could be obtained. On the
contrary, only a cube-within-a-cube turning inside out
was observed as if its members were made of rubber and
could stretch to perform the observed contortions.
Thus, this experiment in computer graphics was something of a complete failure in terms of its stated purpose
of assisting man to visualize a fourth spatial dimension.
However, the technique might yet have merit as a
pure display method for observing scientific data in
higher than three dimensions such as the results of
multi-dimensional factor analyses of experimental data,
and research in this direction involving real~time computer graphics is actively being pursued.
A "tistic consequences
F~gure 3-The perspective projection of a three-dimensional cube
wIth one face parallel to the projection plane is a square-withina-s~uare. If the rotation plane is perpendicular to the axis along
WhICh the cube is being viewed, then the square-within-a-square
simply turns as a whole
:\lost people, including many artists and animators,
were awed by the thoroughly fascinating artistic beauty
of the cube-within-a-cube that so gracefully turned itself inside out; it was purely incidental to them that the
1282 Fall Joint Computer Conference, 1968
the letters A, M, and N which form my initials. Some
selected frames from the movies corresponding to different configurations of the three letters in four-dimensional space are shown in Figure 5. In the movie, the
individual letters appear to float through space or to be
hinged together although able to mysteriously distort
while rotating as a whole.
t
PROJECTION
POINT
"Incredible Machine'"
If individual letters could be used in the program,
then a series of letters could be strung together to form
words on two-dimensional planes in the four-dimensional space. This approach was also experimented with
and resulted in words rotating about and through each
other in-a beautifully fascinating but thoroughly controlled uniform fashion. I used this effect to create the
main title for a movie about computer graphics produced for American Telephone and Telegraph Company
by Owen~Murphy Productions in New York City.
Figure 4-If the rotation plane is not perpendicular to the viewing
axis, then the faces;appear as distorted squares which change both
their size and shape as the cube rotates
movie was produced by a digital computer or that the
cube-within-a-cube was the perspective projection of a
four-dimensional hypercube. Some further investigation and exploitation of the °technique for its artistic
c.onsequences alone was quite definitely indicatedoy all
the enthusiasm generated by the movie. The remainder
of this paper describes these artistic explorations as far
as it is possible to verbalize matters involving aesthetic
concepts.
Four-dimensional letters
The computer program for producing the movie of
the hypercube was general purpose in the sense that any
set of four-dimensional points could be used as input. In
my mind, I visualized letters rotating and moving
through each other in: an extremely graceful yet obviously thoroughly controlled manner similar to the motion of the hypercube. To investigate this effect, I used
the four-dimensional coordinates of points specifying
the end points of straight lines as input to the program"
These straight lines formed individual letters which I
could easily in effect place on different two-dimenslonal
planes in the four-dimensional space. Conceptually,
this is identical to placing the letters on the two-dimensional planes which make up the hypercube. I .chose
Figure 5-8elected frames from different computer-generated
movies of different configurations or placements of the letters
A, M, and N on different two-dimensional planes in four-dimensional space
Computer Animation and the Fourth Dimension
The individual letters of the title of this movie "Incredible Machine" were converted to straight lines connecting points whose two-dimensional coordinates were
then obtained by plotting the letters of each word on
graph paper. The two words were then in effect placed
upon two different two-dimensional planes in fourdimensional space, and the four-dimensional points of
the end points of the lines fornling the letters were
punched into cards for input to the computer. A numberof different configurations of the two words in fourdimensional space were then appraised for their artistic
merit by my judgment of the effectiveness of the computer-generated movies of the rotating words. A single
configuration was finally chosen, and fairly long movie
,of the rotating two words was produced. From this
movie, a single frame was chosen in which the two words
both were individually legible and also formed an
aesthetically pleasing overall form.
.
The ,final title movie opens with a zoom-in on the rotating words. The zoom has a linearly-decreasing accelation so that transition at the end of the zoom to the rotating portion is smooth. The rotating portion continues until the previously-mentioned frame is reached
whereupon all motion ceases for a very short while.
This freeze is followed by another zoom-in which was
done optically rather than by the computer since this
was easier than programming the computer to detennine
which lines exceeded'the picture area. The final title
:movie was optically superimposed over the opening
scene of a man working at a graphical display console.
Selected frames from the title movie including the freeze
frame are shown in Figure 6.
CONCLUSION
A question arises in some people's minds about the
artistic merit of purely scientific techniques which are
applied to artistic purposes. I would like to think that
/the end result, no matter through what medium it was
produced, should be judged for its own artistic merit.
The fact that these movies were produced by a digital
computer performing all sorts of mathematical operations on four-dimensional'data should be incidental to
1283
INC~
Figure 6-Selected frames from the computer-generated main
title of a movie about computer graphics entitled "Incredible··
Machine"
the artistic effects thereby achieved. However, I do feel
that these techniques involving the new technology, and
in particular computers, will only be exploited fully for
artistic purposes when the artist who has dedicated his
life to artistic explorations learns to use these new tools
as new artistic media. I am an engineer and my artistic
ideas are somewhat conservative. But, I am quite excited by the prospects for the new artistic effects and
beauty which will surely result from creative collaboration between artists and the computer.
Computer displays in the teaching of physics
by JUDAH L. SCHWARTZ and EDWINF. TAYLOR
Massachusetts Instiute oj Technology
CambJ!idge, Massachussets
INTRODUCTION
Relativity
An egg falls on the floor and breaks. Now run the movie
backward: the broken egg reassembles itself and jumps
into the air. Everyone laughs; they know that all the
king's horses and all the king's men cannot put Humpty
Dumpty together again. Even a child recognizes that
an egg will not reassemble itself. Why won't it do so?
The answer is deep, involving concepts of order, entropy, irreversibility. The intuition is simple and natural. The precise formulations should be embedded in a
developed intuition.
Higher education, particularly in the sciences, tends
to start with the formal, the symbolic, the abstract.
Usually it is only after the equations and concepts are
mastered that one is able to develop an intuition for the
subject. And the teacher usually provides no help in the,
intuition-building process. Even in laboratory and demonstration experiments a long chain of inference lies
between the observations and the physical questions at
issue.
Our scientific education is largely backward, i.e.,
formalism first, intuition later (if at all). By teaching in
this order we repel the majority of people who do not feel
comfortable starting with' equations. We also make it
. difficult for the professionals, since we offer them little
assistance in developing the intuitive grasp of a subject
from which new ideas spring. The display computer provides a powerful means for
'modeling phenomena of nature. It can help the student
visualize some effects more directly than through equations. Moverover,.there are realms of physics in which
one cannot hope to have a direct experience with the
senses. For example, the high speeds of special relativity
and the sub-microscopic s~ale of atomic physics closes
both to direct visual observation. This paper deals with
some attempts to present as visually and directly as
possible some of the fundamental results of special
relativity and quantum physics using computer
'.
displays.
Rocket travel
Figure 1 shows a display tube face containing a view
of a country road as might be seen from the front wind. shield of a "rocket car." Lining the road are telephone
poles with crosspieces. making the poles L-shaped. Because of computer memory limitations, only three poles
are displayed on each side of the road. The operator
controls the forward or backward acceleration of the
rocket (the "proper acceleration") down the road by
giving fight pen commands. Rocket· velocity is limited
only by the laws of relativity and can approach the
velocity of light. However, the visual presentation is
scaled, so that relativistic effects are easily visible. This
scaling can be interpreted in either one of two alternative ways: (1) the road is normal width, and the speed
of light is sixty miles per hour, or (2) the speed of light
has its normal value, while the telephone pole height
and the road width are comparable to the dimensions
of the planet Jupiter. Either interpretation applies to
the one display.
By manipulating the display, an operator can become
familiar with the following effects due to time delays for
light propagation (effects 1 and 2 below~ and due to the
kinematics of' spacetime (effects 3 thru 5 below) .
1285
1. Bending Poles.
As poles move toward the observer ("forward motion
down the road") the poles appear to be bent backward
(Figure 2), with the tops farther back down the road than
the middles. This is due to the fact that the top of a
pole is farther from the observer's eye than the middle
of the pole. Therefore it takes light longer to reach the
observer's eye from the pole top than from the pole middle. Therefore the observer sees the more distant top of
the approaching pole wher~ it was at an earlier time
(i.e., farther away from him) than the observed position
of the middle portion of the pole.
1286
Fall Joint Computer Conference, 1968
Figure I-Perspective view of "country road" as seen through
front windshield of rocket ship at rest. T!lree L-sh3ped telephone
poles are shown on either side of the road. Numbers displayed
below picture: center number is rocket speed vic along road as a
fraction of the speed of light; on the right, lower number is
reading of clock carried in cockpit, upper number is time read off
adjacent road clock; number at left is count of telephone poles
passed. Light pen controls: operator sets forward or backward
acceleration on horizontal line at bottom of picture; letters at
left: X means "start again"; F means "freeze"; C means "coast
without acceleration"; A means "go back to accelerating. "
2~
Terrell rotation effect.
The cross piec~s of the poles appear to rotate about
the pole as axis as the poles approach the observer
(Figure 2). This effect is arather-more-complicated
result than (1) of the relative time delay of signals
from different parts of the pole. The' effect was
analyzed by T~rrelP in 1959, more than fifty years after
FIGURE 2-Rocket moves down the road with speed vic =
0.367. Acceleration is positive. Poles appear to bend backward
down the road; crosspieces show Terrell·Rotation Effect.
FIGURE 3-Rocket moves at velocity almost three-quarters
of the speed of light. Acceleration is negative. Note different
readings on rocket clock (lower number on right) and passing
road clocks (upper number on right)-the "time dilation effect."
relativity was propounded i This effect results automatically from the transformation equations and was not
specially programmed.
3. Time dilation.
The lower number of the pair on the right of Figure 3
is the time measured in the cockpit of the rocket car, in
arbitrary units (about three units per second). The
number above is the time, in the same units, read off a
series of road clocks, synchronized in the road frame, as
each in turn passes by the rocket. The rocket clock always shows a lower cumulative reading than the adjacent road clock. By taking a round trip down the road
and back while watching the pole counter at the left of
FIGURE 4-Displayof cubes along one side of road; rocket at
rest.
Computer Displays in Teaching of Physics
the figure, the operator can see the two clock readings
to demonstrate the "twin paradox" according to which
a traveling twin who moves at high velocity is younger
on his return than his stay-at-home-brother.
4. Non-addition of velocities.
No matter how high a rocket acceleration is set by_
the operator, the speed of the vehicle (expressed by the
central numeral as a decimal fraction vic of the speed of
light) cannot exceed that of light. Instead, the speed
with respect. to the road is seen to increase more and
more slowly as the velocity vic approaches unity. This
is true even though the acceleration of the rocket main~
tains its constant value ("constant proper acceleration"). In a real rocket, the passengers would continue
to be pressed against the backs of their seats with a constant pressure-a pressure not reproducible,with a computer display! One way to describe this effect is to say
that velocities do not add: the second-by-second increase of rocket velocity in the local frame is not equal
to the incremental change of velocity of the rocket in
the road frame.
5. Surprising changes in aberration angle.
When the rocket is first accelerated at a high rate
from rest forward along the road, the poles appear to
move initially away from the observer instead of toward
him as one expects fro~ everyday experience. This reresult was unanticipated and was initially perplexing to
those who developed the display. It is explained in
terms of aberration angle: At high velocity, objects are
observed in directions different from those at which they
would be seen if the observer were at rest. If the acceleratioIl: is great enough, the velocity change modifies the
aberration angle to a nearby pole faster thandisplace-
FIGURE 5-View of cubes at high rocket velocity. Leading
face of distant cube is turned around, so we look at its back or
inner side.
/
1287
FIGURE 6-Spacetime diagram display. Horizontal axis represents a single space dimension; vertical axis represents time
dimension.' Point A shows location of event in spacetime (coordinates of A displayed on lower right in identical units, such as
meters). To place a point-:-event, tracking cross on right is moved
by light pen to desired location and button EVENT touched tOe
create labeled point. This diagram is drawn for the "original"
reference frame, so speed v / c = 0 on lower left.
ment down the road can displace the pole in the opposite direction.
Figures 4 and 5 show a similar display with cubes on
one side of the road instead of telephone poles on both
sides. The cube display is destined for film loop use and
not as an interactive program.
FIGURE 7-Spacetime diagram locating event A of preceding
figure for rocket observer moving at speed v /c = 0.751 relative to
"original" frame. Transfonnation is accomplished by holding
light button + on symbol - LT +. Note altered space and time
coordinates as observed in rocket frame. "Invariant hyperbola,"
along which event A slides during transfonnation, has been added
using HYPERB button.
1288
Fall Joint Computer Conference, 1968
We must not leave these relativity pictures without
acknowledging that they are deficient in ~t least two
respects: at high· velocities the colors and intensities of
observed objects would vary rapidly as they approach
and pass the observer. These changes in color and intensity are not reproduced in the display programs pre·sented above.
Spacetime diagram
A more analytic manipulation of the results of special
relativity is presented in the spacetime diagram display
(Figure 6). This display demonstrates how the x (space)
and t (time) coordinates of an event as observed in one
frame of reference are related to the corresponding x'
and t' coordinates of the same event are observed in a
second frame of reference in high uniform- motion with
respect to the first frame. The horizontal axis in Figure 6
is the x-axis. The vertical axis is the t (time) axis expressed in units of length by'plotting ct. The location of
a point in the x-t plane (such as point A) gives the space
and time coordinates of that event (see coordinate
reading for point·A in lower right portion of diagram).
Coordinates of events in all frames are measured with
respect to some common agreed-upon "reference event"
(or "starting gun") taken by definition to occur at the
zero of time and space (event 0 at the origin of Figures5
and 7).
Figure 7 shows the same event A and its coordinates
ae measured with respect to a rocket reference frame
moving at a speed vic = 0.751 along the x spatial direction with respect to the original reference frame (value
vic recorded automatically in lower left corner of dis.;.
play in Figure 7). The transformation of the coordinate
FIGURE 8-A field of point-events, showing some of the constructions available on the display. Light cone through origin
event 0 divides spacetime into three kinds of regions with respect
to this origin event.
FIGURE 9-Diagram of Figure 8 transformed to rocket frame.
These two figures, taken together, illustrate the Doppler shift,
time dilation, relativity of simultaneity, relative synchronization
of clocks, and inv~riance of the spacetime interval.
plot is accomplished by touching with the light pen the
"Lorentz transformation button" (LT +) on the display. The relative velocity between frames increases
continually as long as the "button" is touched with the
light pen. The reverse transformation back to coordinates in the original reference frame is accomplished by
pushing the minus sign in the symbol " - LT+ ".
Event-points are placed on the display by using the
light pen to move the tracking cross to the desired place
on the screen and then touching the "EVENT" button.
Up to 16 points can be displayed on the screen simultaneously (Figure 8). Each new point is automatically
labeled with a letter in alphabetical order. Coordinates
of any single event are displayed when the cooresponding display point is touched by the light pen. When a
transformation is made from one frame to another, the
entire field of points is simultaneously transformed,
each to its new coordinate position (Figure 9) .
Other light buttons .are used to erase selectively
(ERASE), to clean the slate (RESET), to contract and
expand the scale of the display (ZOOM), to join events
with lines (JOIN), to draw through any event: an invariant hyperbola (HYPERB). or crossed straight lines
at 45 degrees from horizontal (LIGHT) or a horizontal
line (HORIZ) or a verticleline (VERT). The respective
space and time coordinates of two events can be a.dded
to create a third event (ADD).
Using these commands, one can. investigate a wide
variety of the properties of spacetime including:
the world 1i~es of particles and light flashes-their
paths through spacetime
invariance of the interval (ct)L-X2 that separates
two events
Computer Displays in Teaching of Physics.
the light cone as a partition in spacetime {(invariance of the speed of light.)
regions of spacetime: timelike~ lightlike and spacelike relations between events
clocks using light pulses
Doppler shift
time dilation
Lorentz contraction
non-additivity of velocities
The components of momentum and the relativistic
energy of a particle .transform from one frame to
another in the same way that the space coordinates and
time of an event transform. This means that a point on
the spacetime diagram can be used to represent the
x-momentum (horizontal dimension) and energy (vertical dimension) of a particle. Using this interpretation of
the diagram, the operator can analyze one-dimensional
collisions between particles. In particular the REFLECT button reflects all points about the verticle
axis. This can be used to represent the exchange of
x-momentum of two particles in an elastic collision as
observed in the center-of-momentum frame.
The spacetime diagram is especially versatile in that
the student can both manipulate it to get a qualitative
feel for relativistic phenomena and also read numbers
o
200
240
o
300
400
600
650
700
800
1050
1289
1450
FIGURE ll-Gaussian wave packet scattering from a square
barrier. The average energy is equal to the barrier height. Numbers denote the time of each configuration in arbitra,ry units.
from the figure accurate to three places. In this way he
can pass easily between tlie analytic and intuitive aspects of learning relativity.
280
320
440
Quantum physics
One-dimensional scattering
480
560
800
FIGURE 1Q--Gaussian wave packet scattering from a square
barrier. The average energy is one half the barrier height. Numbers denote the time of each configuration in arbitrary units.
In a quantum mechanical description of nature it is
impossible in principle to describe the instantaneous
position of a moving particle with complete precision.
The dynamical theory provides a probability distribution as a function of position that evolve~ in time. *
This is to be understood in terms of the real world as
the cumula.tive result of a succession of a large number
of independent identical experiments, each one of which
bv itself is unpredictable. One can detect both classical
*The equation to be solved is the time dependent Schroedinger
equation. In general we solve this partial differential equation in
position space for the complex function t/t(x,t) at ~ach time t for
somewhere between 1000 lind 2000 values of x. Except where
otherwise indicated the absolute square of this function is the
plotted curve in the figures. Interested readers· may find the
computational techniques described in Am. Jour. of Phys. 35, 177
(1967).
1290
Fall Joint Computer Conference, 1968
o
400
560
800
900
1040
1200
1360
1680
F~GURE 12-Gaussian wave packet scattering from a square
barner. The. average energy is twice the barrier height. Numbers
denote the tIme of each configuration in arbitrary units.
and non-classical patterns of behavior in these situations. For example in the first scene of the film entitled
"~~rrier~ ~see. Figure 10), one observes the probabIlI~y d~stributlOn for a particle that is approaching a
barrIer wIth an energy that is not sufficient to allow it to
~e transmitted. During the most violent part of the scattering the probability distribution penetrates the region
of the.barrier. T~is corresponds to a finite probability at
that tIme of findIng the particle in a region that is inaccessible to it in a classical description of nature. On the
other hand, toward the close of the first ~cene one sees
~he wave packet reflected from the region of the barrier
In much the same way that a classical particle would
bounce off a wall. The viewer will note, however, that
t?e probabili~y ?istributionhas widened substantially
smce the begmnlng of the process. This, too, is strictly
quantum effect.
The second scene in this film (see Figure 11) shows the
~uant~ descri~tion of a part icle approaching a barner wIth energy Just equal to the barrier height. In this
case one would expect on the basis of classical physics
that the particle would enter the region of the potential
~d lose kine~ic energy until finally all its kinetic energy
IS expended m mounting the barrier, where it would
then find itself in a region of no force with aU its kinetic
energy gone and, therefore, would remain in the region
of the barrier forever. The film shows the quantum
mechanical analog of this special case. Sure enough, a
probability packet remains in the region of the barrier,
a~ least for a long time. In addition, however, one observes transmitted and reflected packets representing
the chances for transmission and reflection when many
experiments are carried out. This "splitting up of the
incident packet" due to the fundamentally statistical
character of the quantum picture is foreign to classical
mechnics.
In the final scene (see Figure 12) the particle has more
than enough energy to overcome the barrier, but we
find, nonetheless, a small but significant probability
that the particle will be reflected.
.
Thus far we have displayed the time development of
probability in space-the so-called "configuration
space reptesentation" of events. An equivalent method
for describing an encounter of a particle with a barrier is
the "momentum space representation"-that is, in
terms of the momentum distribution of the probability
packet. Quantum mechanics shows that the momentum
space representation is every bit as good -as the configuration space representation; each one carries all the
information obtainable about the probable results of
experiment. **
Most students have their first exposure to quantum
mechanics in configuration space and, as a result, obtain a somewhat lopsided view of quantum mechanics.
The next film, entitled "Momentum Space" portrays a
collision as described by quantum mechanics in configuration space and in momentum space, in order to contrast the two and to see how the same physical event
manifests itself in different representations. The first
scene depicts the evolution in time of the position probability distribution of a particle as it approaches a region in which it will feel an attractive force (a potential
well). After the "event" we observe a substantial probability of reflection. The second scene in this film depicts
the evolution in time of the momentum probability
distribution. Momenta corresponding to motion to the
right in position space are here plotted to the right of
the center line and momenta corresponding to leftward
motion in position space are plotted to the left·t
**The computer displays filmed here present squared magnitudes of momentum and config~ra.tion funotions. Information
about complex phase (neoessary to demonstrate. the oomplete
eqt,.ivalence of momentum and configuration representations) is
thus masked.
tThe fUDction here plotted is the absolute square of the Fourier
transform of the solution to the dependent Schroedinger equation
in position space. Only the recent availability of the CooleyTukey algorithm for Fourier Transforms as a standard library
subroutine makes this computation a feasible one.
Computer Displays in Teaching of Physics
1291
T- 0
T=O
- I \'--__
T=250
,I
T=200
I
I
\,
~- ''\----T=400
T=300
jl,
':1'
I,];'
T=500
/\
f'.
T=400
T=750
_.JL
CONFIG:";RATlON
SPACE
/\
~~'j~;:~-_L
-~/_-
"'--
MC.\i.~.\TUM
SPACE
FIGURE 13-The probability distributions in configuration
space and momentum spa,ce at corresponding instants of time for
the scattering of a Gaussian wave packet from a square well. The
particle energy is equal to one half the magnitude of the well
depth. The vertical ~cales are arbitrary. See A. Goldberg, H. M.
Schey and J. L. Schwartz, American Journal of Physics, 36,454,
(1968).
As long as the particle travels freely toward the region of the force the distribution of momenta remains
unaltered, an aspect of quantum theory that Newton
would have been content with. As the particle begins to
feel the effect of the force, the distribution of momenta
undergoes severe distortions, due in part to the increased kinetic energy (and therefore increased momentum) as the packet passes over the potential well.
After a short while the momentum distribution begins
to develop a peak centered about some average leftward momentum, the momentum of the reflected
packet. When the interaction between packet and well
is completed, the momentum distribution again remains
constant while the probability packets in configuration
space sail majestically offstage. Figure 13 shows these
two descriptions of the collision at five instants of time.
A
B
FIGURE 14-The position probability density at selected
times for scattering from a square well and a Wood-Saxon well.
See A. Goldberg, H. M. Schey, J. L. Schwartz, American Journ.al
of Physics, 35, 777, (1967).
real
The barriers encountered in
quantum collisions
are atoms and nuclei. These potential barriers and wells
are not square in shape but have a potential that
changes smoothly with position. In this respect the
quantum displays shown thus far do Il:ot correspond to
reality. Happily, the computer makes its calculations
using a point-by-point specification of the potential.
Therefore interaction with a potential with "rounded corners" is no more difficult to program and compute
than an interaction with a square potential. The resUlt
of rounding the comers of the barrier is a dramatic reduction in the probability of reflection from the well. In
analogy to electromagnetic wave phenomena, one may
say a more gradual "change in impedance" at the sur-
Fall Joint Computer Conference, 1968
face of the well results in less reflection of the incident
"wave."
The effects of softening the barrier walls is presented
in the next film, entitled "Edge Effects." The results of
progressive rounding of the corners is shown in three
stages. Notice that during interaction the structure of
the probability is much smoother for the rounded barrier than for the square one, also that the probability for
reflection is less for the rounded barrier. Figure 14 contrasts the scattering from a square well with the scattering from a well which has a diffuse surface.
CONCLUSION
It is not very difficult to propose additional aspects of
modern science that are difficult to visualize and for
which this kjnd of presentation would be of some benefit. In fact, under development now at the Computer
Film Project of the MIT Education Research Center are
efforts in physical chemistry, electrodynamics, and
molecular biology. Each of these, we have reason to
believe, will enhance the understanding of students as
well as broaden the range of tools available to the
instructor.
1292
Some of the displays discussed here have been used
informally with students and professors. Others have
recently been made available commercially as film loops
As yet the use has not been widespread enough to allow
us to draw firm conclusions about their effectiveness in
developing intuition about relativity and quantum
physics. What little evidence we have leads us to want
to continue developing these materials. Students appreciate the opportunity to focus on the phenomena without being burdened by the constant onslaught of mathematical symbols. Some of our most gratifying moments
occur when professional physicists of the highest caliber
respond to one of these films with wonder and delight
and indicate that, although they have grown up with
the field, they have never seen the behavior of the system revealed this clearly.
REFERENCES
1 JTERRELL
. Physical Review 11610411959
Art, computers and mathematics
by CHARLES CSURI and JAMES SHAFFER
ThR, Ohio State University
Columbus, Ohio
The computer
The c'Omputer is having an impl'Osive effect
up 'On the way we deal with a variety 'Of pr'Oblems.
As an extensi'On 'Of man's senses, c'Omputer techn'OI'Ogy can pr'Ovide an exciting new P'Otential f-or
the creati'On 'Of art. The fr'Ontiers 'Of kn'Owledge
in c'Omputer research suggest a new appr'Oach t'O
pr'Oblem s'Olving in the arts. With a c'Omputer
the artist can n'Ow deal with different variables
in his decisi'On making pr'Ocess than with c'Onventi'Onal meth'Ods. F'Or example, it is P'Ossible t'O
put int'O the memory 'Of the c'Omputer a c'OI'Or
representation 'Of a'landscape. This landscape can
be simulated 'On a graphic c'Ons'Ole. Then with
c'Omputer pr'Ograms which implement mathematical functi'Ons, the artist can watch the effects 'Of
wind vel'Ocity, temperature and fact'Ors which inv'Olve the am'Ount 'Of daylight UP'On his landscape.
He can also 'Observe data which are generally unavailable such as the effects 'Of m'Olecular structure, weight, mass and time UP'On the landscape.
In his decisi'On making pr'Ocess, the artist can
rely 'On n'On-visual cues as well as visual cues, He
can m'Odify many m'Ore parameters in the t'Otal
landscape envir'Onment t'O create a w'Ork 'Of art
than by c'Onventi'Onal meth'Ods.
The artist and the modern environment
The fr'Ontiers 'Of kn'Owledge in c'Omputer research 'Offer a glimpse int'O the future r'Ole 'Of the
artist. At M.I.T. and Stanf'Ord University c'Onsiderable research is in pr'Ogress which attempts
t'O deal with artificial intelligence pr'Ograms. S'Ome
researchers suggest that 'Once we pr'Ovide c'Omputer pr'Ograms with sufficiently g'O'Od learning
techniques, these will impr'Ove t'O the P'Oint where
they will bec'Ome m'Ore intelligent than humans.
SUPP'Ose we have a machine which has st'Ored in
it a kn'Owledge 'Of art hist'Ory, the'Ories 'Of phil;s'OPhy and aesthetics, in fact, the intellectual hist'Ory 'Of man. Every kn'Own technique ab'Out painting, sculpture and the c'Omputer graphics ,,:ill als'O
be st'Ored in the c'Omputer, n'Ot t'O mentI'On an
ability t'O make judgments m'Ore I'Ogically than
man. What happens to questi'Ons ab'Out art when
there is a dial'Ogue between man and such a c'Omputer pr'Ogram? What bec'Omes the pr'Oblem?
Wh'O is the artist ? What are the implicati'Ons
f'Or man? It is b'Oth terrifying and exciting at
the same time.
The emergence 'Of new f'Orms and media in
c'Ontemp'Orary art indicates the artist's, deep inv'Olvement in twentieth century techn'OI'Ogy. R'Obert
Rauschenberg creates f'Orms which c'Ombine 'Objects such as aut'Om'Obile d'O'Ors and heating ducts
with s'Ophisticated electr'Onic devices that create
s'Ounds and smells. Artists Tom Wesselman and
George Segal utilize plastics and neon lights as
well as radi'Os and TV sets. Kinetic art has pr'Oduced a vast array of 'Objects which move 'Or vibrate. Current artists have used practically every
pr'Oduct in our society t'O make art. In the tradition
of the craftsman, these artists seem to be more
c'Oncerned ab'Out materials and technical processes
than any underlying scientific concepts which produced these products.
The computer which handles fantastic amounts
'Of data f'Or pr'Ocessing brings the artist close to
the scientist. Both can now use the same disciplines and kn'Owledge in different ways. F'Or
the first time, the artist -is in a P'Ositi'On t'O deal
directly with the basic scientific concepts of the
twentieth century. He can now enter the w'Orld
of the scientist and examine th'Ose laws which
describe a physical reality, The artist can enter
1293
1294
Fall J 'Oint CQmputer CQnference, 1968
a micrQuniverse 'Of science and alter parameters
tQ create a different kind 'Of artistic wQrld. In a
highly systematic and disciplined manner he can
deal with fantasy and imaginatiQn. One example 'Of the use 'Of a scientific cQncept fQr artistic
purpQses is the well-knQwn LQrentz transfQrmati'On. It is a theQry 'Of special relativity which is
a scientific explanatiQn 'Of the apparent distQrtiQn
'Of a fQrm as it approaches the speed 'Of light. It
WQuld be interesting tQ see what happens graphically to a drawing 'Of a turtle 'Or a hummingbird,
which can be used as input tQ the cQmputer, as
it apprQaches the speed 'Of light. The artist may
be interested in the absurdity 'Of such an idea
and it may give him a different kind 'Of fQrm.
He may enjQY the cQntradictiQn 'Of a turtle travel- ing near the speed 'Of light.
The artist need nQt necessarily stQP at the parameters defined by a transfQrmatiQn in relativity.
He can arbitrarily declare that 'Objects will mQve
at a speed which is five times that 'Of light (prQvided the mathematical equatiQns dQ n'Ot degen-I
erate). In fact, he can, with the cQmputer, take
a br'Oad variety 'Of well-known equatiQns which
describe 'Our physical universe and change the
parameters. He can create his 'Own persQnal
ficti'On.
It is quite apparent that the c'Omputer artist
will have cQntact with the scientist. The c'Omputer and the mathematical disciplines required
t'O s'Olve pr'Oblems, artistic and, scientific' make f'Or
a c'OmmQn grQund.Those fields will be brQught
clQsely tQgether, and bQth will benefit by the
dia~Qgue made PQssible thrQugh cQmputer science.
The artist, when invQlved in the creative prQCess, feels free tQ deal with experience in any
terms which can express his cQnception. He is
nQt restricted tQ the rules required. 'Of the scientist tQ express a reality. In a sense, 'One rn:ight
say that he takes the many parameters 'Of 'Ordinary experience and changes them tQ express his
imaginatiQn. He creates a new universe. Since
his purpQse is tQ make art, the artist is nQt bQund
by the laws which aCCQunt fQr the physical WQrld.
On the 'Other hand, the scientist is alsQ inte'rested
in realities. He explains the' behaviQr 'Of physical
phen'Omena and usually verifies it in mathematical
terms. The famQus mathematician and writer
J aCQb BrQnQwski summarizes the similarities and
the differences between artist and scientist in the
fQllQwing statement:
"The creative act is alike in art and in sci-
ence; but it cannQt be identical in the two;
there must be a difference as well as a likeness.
FQr example, the artist in his creation surely
has 'Open tQ him a dimensiQn 'Of freedQm· which
is clQsed tQ the scientist. I have insisted' that
the scientist does nQt merely recQrd the facts,
but he must cQnfQrm tQ the facts. The sanctiQn
'Of truth is an exact boundary which enclQses
him, in a way which it dQes nQt cQnstrain the
PQet 'Or the painter. . . ,,*
Mathematics and the arts
SQme artists thrQughQut histQry have been intrigued with the PQssibility 'Of making use 'Of
mathematics in their art. The renaissance idea
'Of virtual space (the imitatiQn 'Of 3-D space) was
generated by mathematical formulae fQr linear
perspective. MQdern artists such as Paul Klee,
MQhQlyNagy, Naum GabQ, and AntQine Pevsner
have used simple mathematical systems tQ analyze
and develQP forms. In the past, mathematics has
been given limited applicatiQn as a tQQI fQr the
discQvery 'Of aesthetic fQrm because the techniques
emplQyed were slow and extremely time-c'Onsuming. TraditiQnal ways 'Of sQlving prQblems 'Of
measurement an'd plQtting were tQQ awkward and
mechanical fQr artistic applicatiQn. As a CQnsequence, the artist's cQncept 'Of structure· was'
limited by what he was able tQ design 'Or draw
by hand. If an artist was able t'O understand 'Or
use the traditiQnal methQds 'Of mathematical
analysis, he was quickly discQuraged because 'Of
the many repetitive steps in the cQmputatiQn' of
a prQblem.What he CQuld visualize was limited
by traditiQnal methQds.
An artist can nQW make use 'Of cQmplex mathematical functiQns. With the advent 'Of cQmputers
the artist has at his disposal the cQmputatiQnal
PQwer tQ apply many mathematical transfQrmatiQns tQ a variety 'Of images. By implementing
mathematical functiQns thrQugh cQmputer prQgrams, and generating the results 'On a mechanical plQtter 'Or CRT display, the. artist can pursue
an 'Orderly in-depth inquiry 'Of visual fQrm. He
can examine clQsely related 'Or widely divergent·
functiQns. The results can be evaluated artistically against the background 'Of the mathematical functiQns invQlved. AbQve all, there are new
fQrm PQssibilities that can be generated by the
cQmputer. Artists are faced with the prQspect
*From J. Bronowski Science and Human Values, 1956.
Art, Computers and Mathematics
of a new medium to enable the exploration of
visual ideas.
The interest here is in the use of mathematical
functions t'O modify form in a variety of ways.
There is no intention to define a particular mathematical theory of art, but simply to say that
mathematics is a useful means to create many
kinds of art. One artist may prefer to work with
realistic images while another one may prefer
abstract images. An artist may select visual information in such a way as to communicate qualities of surrealism or expressionism, and even a
tragic or lyrical view of reality. Questions about
artistic content involve artistic decisions. Mathematics per se does not make the art. One brings
artistic criteria to the 'Object and makes value
judgments about it. This criteria must deal with
the nature of aesthetic experience and those
aspects which make it art. Mathematics and the
computer ,only provide us with another means to
make artistic inquiry.
In a broad sense certain modern educational
theories, and the way in which mathematical
strategies can be applied, are also relevant. Currently there is considerable discussion ab'Out
"psychological sets" in learning. This concept of
sets suggests that the artist is often the victim
of his own "set producing tendencies." At times,
he has great difficulty in breaking down his own
biases in order to solve an artistic problem in a
creative way. ' Because 'Of his' biases, the artist
usually gets only. slight variations on a basic structural theme. A mathematical orientation toward
visual proble.m solving can enable the artist both
to break down his biases and to express another
range of solutions. Essentially this would depend
upon the types of strategies which the artist employed to effect his original data. To say this
another way, the computer's capabilities, if exploited by the artist, would be made to yield a
greater number of alternatives more rapidily and
efficiently. Within a short period of time a computer-cathode ray tube-plotter or graphic console
capability can give hundreds of variations of a
form.
It is conceivable that any given transformation
can be 'of use in computer art. Special consideration seems appropriate for transformations with
properties which enable an artist to visualize the
approximate result of the transformation and to
transformations which are easily adapted to
machine computation.
1295
Mathematical functions are found in almost
every branch 'Of mathematics and they can produce an unlimited number of variations for the
discrete set of coordinate points associated with
a line drawing. Successive applications of the
same or different functions can produce interesting results. In the example of SINE CURVE
MAN there was a successive application of a sine
curve function in which the amplitude was increased each time. Numerous possibilities exist if
one/ uses a multiplicity 'Of functions to achieve a
final transformation. Some of the applications
include a sequence of functions in which many
functions are used. The example PLUS SIGNS,
includes functions which deal with 'Orientation,
size and distribution. The motion picture HUMMNGBRD' which' is in time, utilizes several
functions simUltaneously, each varying independently as in the "three bird scramble" sequence.
Each bird was on a different mathematically defined path, while their size was cha:b.ged sinusoidally-each at its own frequency. Also each image
IQ,oved from an abstract picture to a realistic bird
at an independent' and non-uniform ,rate.
Figure I-SINE CURVE MAN, 1967. A digitized line drawing
of a man was used as the input figure to a computer program
which applied a mathematical function., The X value remained
constant and a sine curve function was placed upon the Y value.
Given the X and Y coordinates for each point, the figure was
plotted by the computer from X' = X, Y' = Y + C* SIN (X)
where C is increased for each successive image.
1296
Fall Joint Computer Conference, 1968
+
+
+
)-
\~++
+
Figure 3-Computer film, HUMMINGB.IRD, 1967, One still
frame from a computer animated movie.
'
+
+
++
Figure 2-In figure 2 the equations x' = y* (x + y - 1)/
+ y~ - x - y) y' = x* (x + y - 1)/(x2 + y2 - X _ y)
cause the lettered primed and unprimed areas to interchange
while the numbered areas map into themselves. To produce' the
accompanying figures rectangular areas were defined in which
random coordinates were generated. Mter applying the transformation equations those coordinates which fell inside a second
rectangle were accepted as the location for 8 fly or plus sign.
.
(x~
cording to properties such as: those which pre..
serve size and shape; those which preserve lines;
those which 'preserve angles of intersection; those
which preserve continuity; and S'O forth. If trans,.
formations are given by equations for coordinates
of image points, the transformations can be clased..
fied by the form of the equations. Perhaps one
might even try to develop a mathematical theory
of art, and include a heirarchy of functions based
upon ideas about periodicity, harmony, permutation, ratio, progression, and so forth. This would
seem to presupp'Ose a theory of artistic structure
and one may find many,'problems in such a mathe..
mati cal theory 6f art: There is no clear cut
criteria on which to make a judgment about classification. What is important, however, is that the
artist have a broad range of functions and computer programs available to him.
It is quite true that an artist can probably
imitate any image the computer can generate.
Some images would be difficult, but not impos. .
sible. However, the question is not one 'Of hand
skills versus machine skills. The problem is one
of c'Onception, wherein the mathematical transformations made possible by the computer present a new dimension to art.
Research
AppUcable types of mathematical
transformations
Transformations can be classified in many ways.
One approach is to group transformations ac-
During the past two years we 'have produced
several hundred pictures by computer. Our work
has involved color as well as black and white.
We have developed many programs which make
use of functions in trigonometry, coordinate sys-
Art, Computers and Mathematics
1297
terns, conformal mapping, n-dimensional g~'ometry
and randomness. In addition' we have developed
several programs which deal with special problems of graphic display by computer.
The technique we use is as follows: (1) An
artistic drawing· is made' with line segments of
points of the subject matter to be used. (2) The
drawing is digitized line by line with the resultant coordinates punched into cards. (3) Decisions
are made a.bout the type of form modification and
the mathematical steps required to accomplish it.
( 4) The mathematical algorithm is programmed
for a computer which then generates the plotter
commands. (5) At this point another decision is
made about the color and line width for the transformation. (6) The transformed image is plotted
on a CalComp 563 plotter.
U sing a variation of the photo-nylon screen
technique we have developed 3) method to transfer
the plotter output to canvas and plastic sheets.
This allows us to use a permanent non-fading
paint to' represent the image.
"
We have also cokpleted a ten minute computer
animated motion; picture entitled HUMMINGBIRD.* The subject was a line drawing of a
*Awarded a prize at the 4th International Experimental Film
Competition, Brussels, Belgium, 1967.
I
Figure 4-RANDOM WAR, 1967. A drawing was made of one
toy soldier and this became the data deck. A computer program
which generates random numbers is called a pseudo-random
number generator. Such a program determined the distribution
and position of 400 soldiers on the battlefield. One side is called the
"Red" and the other one the "Black", and the names of real
people were given to the program. Another computer program
assigned military ranks' and army serial numbers at random. The
random number generator decided the following information and
the computer made this picture with the casualty list. (1) Dead
(2) Wounded (3) Missing (4) Survivors (5) One Hero for each
side (6)Medals for 'Valor (7) Good Conduct (8) Efficiency Medals.
Figure 5-RANDOM COLOR DISTRIBUTION, 1967. A
realistic line drawing of an old man was used as the data deck,
A line drawing was transformed mathematically into a shaded
image. A spiral, rectangle, triangle and star were the character
symbols used to replace each line segment. The position of
the four colors was determined by the random number generator.
The size of each character symbol is a function of distance from a
reference point outside the picture space.
hummingbird for ,which a sequence of movements
appropriate to the bird were outlined. Over 30,000 images comprising some 25 motion sequences
were generated by the computer. For these, se. .
lected sequences were used f'Or the film. A microfilm plotter recorded· the images' directly' on film.
To facilitate c'Ontrol over the motion of some
sequences the programs were written ~o read all
the controlling parameters from cards, one card·
for each frame~ Curve ,fit 'Or other data generating programs were used to punch the parameter
decks. We also built a windowing option into our
plot subroutine.
Our most recent proj ect is. sculpture using a
3-axis, continuous path, numerically controlled
milling machine. Mathematically generated surfaces such as the Bessel function were our first
works. We have developed our own supp'Orting
1298
Fall Joint Computer Conferen,Qe.1 1968
chine Company for guidance and the use of their
equipment for numerically controlled milling. The
Ohio State University for its generous' support
of our research efforts.
Figure 6-FLIES IN A CIRCLE, H,)66. A computer program
generates random numbers which determine the distribution of a
specific number of flies in a series of 1" concentric rings. Within
predetermined limits the random number generator also decides
the orientation and the size of each fly.
routines rather than using one of the special languagessuch as APT. The rigid program-part
correspondence as in APT was not suited for our
purposes. This problem lead us to develop a
method' which provides a more flexible input capability for general artistic Use.
Mter Leonardo's HUMAN PROPORTIONS
F.igure 7-The program finds Ymin and Y max (or Xmin and
Xmax) for the input image. Then from Amin and Amax, read as
input parameters, Al can, be calculated for each Y i. The mapping
function is Y'i = K* tan (Ai) where K is a constant calculated
to yield a final figure at the desired height.
ACKNOWLEDGMENTS
Mr. Sam Cardman for his mathematical analysis and programming for numerically controlled
milling and HUMMINGBIRD. Professor Leslie
Miller for his ideas and concepts dealing with
proj ective transformations. Cali~ornia Computer
Products Company for the use of their 835 microfilm plotter. A' special note of thanks to Mr.
Arthur Francis and the Cincinnati Milling Ma-
Figure 8-CIRCLE INVERSION, 1967. The input image is
scaled to fit inside a circle of unit radius. Working in polar coordinates the transformed image is (J' = 8, r' = 1/r. A point at
the unit circle's center transforms to a point at infinity while a
point on the circle's circumference is invariant.
CAMP-computer assisted movie production*
byJ.CITRON
IBM Corporation
Los Angeles, California
and
JOHN H. WHITNEY
Pacific Palisades, California
INTRODUCTION
In designing a language for computer assisted production of animated film sequences, a serious attempt has
been made to -avoid dependence upon the user's
knowledge of mathematics, geometry, and programming logic. Such a user Can be expected to have the
sense and sensitivity of an artist in manipulating given
geometric figures, so our first objective is to provide a
general way to construct a wide variety of figures and
then to provide manipulative functions for their spatial
and temporal evolution. While the mathematical and
logical program necessary to perform this processing
may be complex, the language seen by the user must
afford control over all the technical flexibility available
in the program, but from the user's non-technical standpoint.
The approach we have takenis to minimize the number of types of statements in the language-basically
there are three-and introduce numerous fundamental
concepts which may be learned by experience with the
aid of an interactive program.
Various approaches to hardware are possible, and so
the language only depends on the ability of the computer to address a display device. If a cathode ray tube
is used, a camera should also be attached under full control of the computer.
Our implementation consists of a program written in
the GRAF language1 to run on the IBM 360 with a
2250 display unit equipped with a program function
keyboard. Mr. D. Bottles of the IBM Los Angeles
Scientific Center has constructed a control box which
connects to the function keyboard and a camera constructed by Mr. Whitney. This device allows the light
circuits on the keyboard to activate the camera controls
under computer direction to photograph images on the
2250 and advance the film frame, and also uses the key
circuits as feedback sensors to advise the computer of
the camera's status with regard to these controls.
Technical background
The list of figures which one would like to be able to
generate is practically endless. Thus, a direct geometrical approach suggests an infinity of subroutines which
can be singled out according to the figure classification
requested. An alternate viewpoint would be to consider
any desired patterns to consist of curve segments of
limited size (they must fit on a film frame) and then attack the problem of creating generalized curve segments. This decreases the required number of figure
generation routines tremendously and, in fact, a single
routine can be devised in different ways which will
prove quite adequate for constructing just about any
desired pattern within the given hardware limitations.
The curve -equati~n and its parameters
Behind the scenes, so to speak, of our program lies a
single mathematical function embedded in an algorithm
with a number of parametric controls. This function
may be expressed as the polar equation:
*Development was carried out at the Health Sciences Comput:ing Facility of the Medical School, University of California at
R = A (sinB8)P .
Two points are specified in a 2-dimensional Cartesian
Los Angeles.
1299
1300
Fall Joint Computer Conference, 1968
frame by four parameters-(X,Y) and (U,V)- to define the lower left-hand and upper right-hand corners of
the computed picture. Theoretically, assignment of
values to A, B, and P then produces the curve R(O)
which mayor may not lie within the frame· defined
above. However, because of the nature of current display hardware, the values taken on by the variable 0
must be enumerated in a discontinuous fashion so that
if the discrete points (R,8) i are to be connected, they
will be joined by straight lines. Fortunately, this provides many advantages and few, if any, handicaps since
the eye cannot detect the discontinuous nature of the
curvature of a segment whose points lie reasonably
clos~ together. This introduces the need for four more
parameters. 8 and T are the first and last values taken
on by o. N is the number of intervals into which the
range T - 8 will be divided. The connectivity of the
points marking the intervals is given by the parameter,
J. If J equals 0, only points are displayed while the
internal ordering of the points is the same as for J
equals 1. For J not equal to 0,0 runs from 8 to T in N
steps but ordered by skipping J points ahead and cycling in the given range. If J and N have a common submultiple, fewer than N points are used.
The use of the parameters A and B is clear from the
equation, but the exponent, P, requires further clarification. If P were restricted to integer values (which it is
not), the odd and even integers would govern two different regimes of (R,O). Even values for P would cause
all R values to have the same sign as A, regardless of the
sign of (sin BO), whereas odd P values would give R the
sign of the product of the signs of A and (sin BO)P.
Further ,negative values for P destroy the main attribute of the sine function-its boundedness! Our algorithm makes available both the odd and even integer
regimes in a continuous way for all real values of P
(not just integers) and avoids the negative P problem
by using the sign of P to specify the regime. Negative P
assigns the sign of A sin BO to A Isin Bol IPI while
positive P mimics the even integers. P set to zero
causes R to equal A for all values of o.
The algorithm uses two additional parameters for remapping the (R,O) i points to (R,0) i. A rotation, Q, is
added to all 0 values and the interval containing the rotated points (8 + Q to T + Q) is stretched (or shrunk)
linearly by a factor, W, so that the points run from
8 + Q to WT + Q in units of J(TW - S)/N. If W is
equal to zero, the program uses the original interval
(8 + QtoT + Q).
Now, given the point (R,<,/», one would expect its
Cartesian coordinates to be expressed by (x,y) where:
x == Rcos<'/>
y
= Rsin<'/>.
However, we have added three' additional pairs of
parameters to allow individual x and/or y translations
and scalings:
x = C
+ ER (COS<,/»H
=
+ FR· (sin <'/»z
y
D
where the signs of Hand Z are handled like the sign of
P. Finally, a rotation with respect to the center of the
film frame is specified by the parameter O.
In 3:11 then, there are 20 parameters which may be
used to define a single curve. We refer to each set of 20
parameters as a curve so that a number of curves may
make up a single figure. Default values are predefined
for the parameters so that only "distorted" parameters
need to be specified for any curve.
Options connecting curves
Beside the ability to control multiple exposures, there
are three options which provide a manifold of techniques for "combining" curves. We refer to these as the
add, link, and concatenate options and use the symbols
+, -, and I to represent them in equations. Further, we
label the polar coordinates of the computed points with
a curve index, c, and a point ordering index, i, which
runs from 1 to n(c). Thus ( R(24) , <,/>(24) ) represents the
fourth point in the second curve. Weare now in a position to describe the curve combining options in a precise
way.
If curves (1) and (2) are added in that order
i. e. (1)
+ (2)
the computed points have coordinates
while
(2)
+
(1) results in plotting the points:
(R(li)
+
R(2 i ), <,/>(li»).
Thus we see that the add option is not commutative but
results in using the angular· coordin'ates of the last
curve specified. Of course, if the two curves have the
same number of points and the same range of 0 and
identical point ordering (that is identical values for N,
J, 8, T, and W) as well as the same frame scaling parameters' this operation is equivalent to a direct algebraic
addition of the two curves and their apparent order is
immaterial.
Linking two curves causes points with the same
CAMP
ordering index to be connected by straight lines. Thus
(1) - (2) results in a pattern of lines connecting points
(R(l,), q, (I,» to points (R(2.), q, (2,» with connections
between points having identical i indices. One of the
many uses of this option is to connect two curves which
are identical in all respects except for position on the
frame and possibly size thus providing 3-D "wire
frame" perspectives.
Concatenation of curves· orders their points in a sequential manner for treatment as a single curve in subsequent add or link operations. That is, (1) 1 (2) effectively produces a single curve whose point indices run
(11), (12),
... , (1.(1), (21), (22)' ... , (2.(2»,
giving a total of n(1) + n(2) ordered points.
Two special counters affect the option algebra
strongly. One marks the point at which the last concatenation started and the other marks the beginning
of the previous link. Add is carried out starting at the
position of the concatenation counter so that
1 + 213 + 4 implies (1 + 2)1(3 + 4).
Concatenate uses the last point of the last curve as a
starting point so that, in the above example, the final
result depends on the relative lengths of the point
strings 1 and 2. If there are fewer points in curve 1 than
in curve 2 (or if the number of points is equal in both),
the figures contain all computed points. But if curve
1 has more points than curve 2, there is a resultant loss
of some points. This is most clearly seen graphically:
(ordered points of curve 1
lpoints of, curve 2.
1
1301
where the three curves in the brackets are treated as a
single string of points for the two link operations.
It should now be clear that the three options provide
much flexibility over and above that afforded by the 20
parameters per curve.
Temporal control
So far, our definition of a curve seems fairly straightforward because of the assumed static nature of the
parameters. However, two different systems for control
of the time rate of change of each parameter are available in the program algorithm. Thus a curve can be an'
extremely complex function of time and may appear on
a film frame to be identical to some other curve at one or
a few separate instants of time. This. ability requires
that at least one and possibly even all twenty parameters be specified by more than just a single numerical
value. Each parameter now consists of a list of up to 16
items, and the interpretation of these list entries depends on which temporal control system is in effect.
For the type 1 rate controls, the list contains three
kinds of entries-values, rates, and relative timesgrouped in that order. The use of relative times allows a
curve to evolve in a given manner during the time spanning any number of frames. Such evolution may occur
in separate sequences or overlapped in the same sequence.
To explain the rate entries, we'll call V1 the initial
value of the parameter at time tl and V 2 the value to be
reached at time t 2• The value V at any intermediate
time T is computed according to the rate entry in the
list. If the rate is zero, the parameter goes from V1 to
V 2 linearly in time-that is:
::
plus
2
Itai I of 1
I points
of
3
4
3+4
:oJ
If the rate is a positive number, r, an acceleration is
made so that the value of the parameter at any time
other than tl or t2 is less than the lineally computed
value. The equation used is:
:
'tail
4I
4 _ _.....
L-_l:.....:+;.....;:2:....-_ _.L...:3:....-+:...-_
1_ta_il---L4I ***RESUlT***
Note that the points of curve 1 which overlapped i:r{ the
add operation with curve 2 are simply lost in the result.
This' could be avoided if desired by specifying
2+ 113+4.
Link is always carried out from the -beginning of the
previous ,link, providing there. was one. Thus
, 1- 2 + 314 - 5 is expressed logically as 1- [(2 + 3) 14]-5
To obt~in a deceleration, a negative rate is used. In this
case, in order to provide temporal symmetry with the
accelerating rate path, the required equation turns out
to be:
The symmetry mentioned is Ill:0st easily seen geometri-
Fall Joint Computer Conference, 1968
1302
cally:
Parameter
value
---,
rate
= -r
add, link, and concatenate options, there are "ERASE,"
"CLEAR," and "KEEP." Touching the erase option
erases the curve and returns the parameter menu with
all the previously set values still intact. Touching
"CLEAR" removes the curve from the display and also
from the computer's memory. The default values again
appear on the menu. "KEEP" functions in the same
way as "ERASE" except that, after setting up a new
curve and touching, "GO", that new curve is displayed
along with the kept ones.
rate: r
R
= A (S 1N, B9) P ,
9
= $. T • J ( T -$) / N
= .ROTATION$
o.~
= MAPPING$
W.C.D.E.F.H.R
---.....:--...;.--_ _ _...:...._......,j_ _ _.. time
X
:
-1
0
;:
.1
Y
::
-1
W
;:
8
J
::
V ::
N
;:
3b0
A :: 23
C
;:
0
0
u
Tl - tl = t2 - T2 in the figure. At T 1, the difference
between the linear value and the decelerating value is d.
At T 2, the accelerating path is the same distance from
the linear one. Thus, temporal segments can be pieced
together so as to match velocities as well as values at
their connecting point.
The type 2 temporal controls are quite different in
appearance. Actually, one can set up the same motions
in either system, but it may well prove very tedious to
acquire certain results by one method and relatively
simple by the other. Under type 2 control, a parameter
obeys the equation:
v
= (Vm
-
Vo)(sin T)P
+ Vo
::
8
:
D
;:
p
::
E
;:
S
::
0
F
;:
T
::
.01
H
;:
-1
Q ::
0
R
;:
-1
2
.>
4
5
b
1
8
CJ
0
GO
Parameter menu-Default values are right justified in Fortran
13 format. Values entered with the light pen build from left to
right, digit by digit. In the paper, the parameter, R, has been
called Z to avoid confusion with R in the basic equation.
where T runs from T ito T, and the sign of the exponent
p is used just as for P, H, and Z to affect the shape of the
oscillation. For this kind of control then, the list of items
characterizing each parameter must contain values,
phases, exponential rates, and relative times.
Learning the fundamentals
Static use of the parameters and options is learned
with the assistance of a separate program. This code
-displays on the 2250 a list of the twenty parameters '
equated to their default values. Along with the parameters there are also displayed a numeric "keyboard"
and the word "GO." Touching a parameter with 'the
light pen causes its value to be erased. Then as "keyboard" entries are touched, those particular digits appear consecutively setting up the new value for the
parameter. When "GO" is touched, the entire menu is
erased, and the curve specified by the parameters
appears along with a list of return options. Besides the
*
K~EP
*
ADD
•
CL~AR*
(RASE* LINK
*
CONC
A typical figure display showing the return options
CAMP
This program can be used to develop an intuitive
feeling for the parameters and options as well as to
study seriously the analytic geometry of the fundamental equation. It is also most useful to the experienced
user for determining experimentally how to construct
any desired figures and then transcribing that construction knowledge directly into the animation program language. The animation program itself may also
be used in a "dry run" mode for testing and debugging
time sequences.
The language
As soon as one feels he has some grasp of the options
and a few of the parameters, he is ready to learn the format of the data cards which comprise the language for
the animation program. The three types of cards are
referred to as identification statements, parameter
statements, and frame statements. For one time sequence, a curve is specified by one identification statement and as many parameter statements as needed. Up
to ten curves can be defined in one time sequence in
the present program. After all curve specification cards,
the frame statements are entered· for the sequence.
Other sequences may follow these directly.
The identification statement
An identification card contains the leters "ID" in
columns 1 and 2. From that point on, the field positions
are not rigidly defined except for two rules:
1) from one to four spaces may separate fields
2) anything following a 5-space gap will be treated as
a comment
The first numeric field is a curve identification num.ber from 1 to 10. The remaining fields are optional. As
many as will fit on a card may be used to establish parameters which are to remain constant for the entire
sequence at a value different than the default value.
Typical identification statements are:
IDI
ID
2 P =0 T = 1.75 W = 179.651
ID
3 N=251
C= -.5 F=.75 H= - 3
Z= -2.566
Par8lneter statements
Each parameter that is to vary with time must be
specified on a single card. Column 1 contans the symbol
representing that parameter-
1303
x, Y, U, V, A, B, P, S, T,J, N, W, Q, 0, C, D, E, F,
H,orZ.
If column 2 is blank, the remainder of the card is interpreted according to the type 1 temporal control system
described earlier. If any non-blank character appears in
column 2, a type 2 list is assumed to follow. The same
two rules regarding spaces between fields hold for the
remainder of the card as was the case for identification
statements.
For the type 1 parameter card, the field beginning in
column 3, 4, or 5 gives the initial value of the parameter.
If the rest of the card is. blank, the parameter is held
constant at the initial value for the entire sequence. If a
slash follows the initial value, a decimal fraction representing a relative time may follow the slash. The effect
here is to hold the parameter constant for that fraction
of the total 'time of the sequence. If no slash appears,
the next field contains another value toward which the
parameter will approach by a type 1 rate.· This rate occupies the following field and is in turn followed by a
decimal fraction representing the relative time in the
sequence over which the parameter must make the
transition between the two values. The last group of
three fields-value, rate, time~forms a typical unit of
type 1 parameter card entries. Following the initial
value of the parameter (the first numeric field), up to
five such groups may be given. The last group (and
there might only be one) leaves the time field blank implying that that group carries the parameter up to the
last frame of the sequence. Any fractional time field
may be followed by a slash which effectively replaces
the value and rate of the next group. This causes the
last value reached at the last time (before the siash) to
be held constant until the new time (the field following
the slash). Typical examples would be:
B
1 7 0
.25 /
.5 3
1.5
o
0 2 -1 .333 /
.5 4
1
C.5 /.5
.667/
-.50
The parameter B starts at the value 1.0 and varies at a
constant rate to the value 7.0 which is reached at the
quarter point of the whole sequence. The value of 7 is
then retained as a constant until the half way point in
time. An accelerating change (rate = 1.5) is then made
to the value 3.0 which occurs on the last frame. The
parameter 0 (and all other angular parameters) has its
value given in units of pi (3.1415927) radians. In the example above, 0 begins with the value 0 and changes
to the value 2 (360 degrees) at a decelerating rate
of -1 in one third the total time. I t retains this
1304
'Fall Joint Computer Conference,
196~
value until one half the sequence is over and then goes
through another 360 degrees (to the value 4) at an acceleration of 1 up to the 2/3 point. The slash followed by
blanks then makes it stay constant to the end. C begins with the value '.5 and stays that size for the first
half of the sequence. It then progresses to a value of
-.5 at a constant rate (rate = 0) reaching that value on
the last frame.
For the type 2 time controls, recall that the equation
for the parameter was written as
v
= (V m
-
Vo)(sin T)P
+ Vo
where T runs from Ti to T,.
On the parameter card, the field following the parameter itself (~d the non-blank entry signifying type 2
control) contains the median value, Yo, for the first
oscillating segment. The next field is the peak value,
Vm' This is followed in order by the initial and final
phases, and T i , T J in units of pi, the exponent, p, and
the fraction of the total time, t, at which this segment
ends if less than the total time for the entire sequence.
Three groups of (Vm, TiT" p,t) may appear on one card
(with t omitted for the final group implying the value
1 for the relative time). For groups after the first, Vo is
is taken as the last value of the parameter actually calculated in the previous segment. Thus it is easy to obtainoscillating behavior of various kinds Jas well as continuous piecing together of up to three different oscillations for a single time sequence. An example would
be the following card on which U is specified to oscillate
as shown in the sketch: '
u
5
4
3
2
.5
Uj 2
1 0 3 2
time,
.5 7 0 1.1
-2
Note that the first exponent, 2 in the fifth numeric field,
confines the oscillation to one side of the median value
and gives a zero slope at the median. The second ex-
ponent, -2 in the last field, causes an inflection point at
the new value median (which happens to be the same
as the old one) .
Frame statements
Following all identification and parameter cards for a
sequence are the frame cards. These must be' blank in
the first two columns. The first two fields on each frame
card contain the initial and final frame numbers for the
time sequence -defined by that card. The remainder of
each card contains curve identification numbers and options in alternating fields with a maximum of five
curves and four options per card, and up to twenty
cards can describe one "conglomerate" sequence. For
example, the cards
11440 1/2
+
3
+ 3,
200 13004 L 1, 2 + 3 GO
100 300 1 / 2
define three overlapping sequences. From frame 1 to
'frame 1440, the curve whose identification number is 1
evolves as specified by its parameter cards. Simultaneously, curves 2 and 3 are combined by the add option. The slash causes curve 1 to be displayed separately
on the 2250. The camera photographs it, the picture is'
erased, but no frame advance occurs. The combined
curve, 2 + 3, is computed and displayed. This picture
is photographed on the same frame of film and the 2250
is ,agained erased. The program then checks ~o see it
any other frame cards require an exposure for the current frame number. If such is not the case, the frame is
advanced. When frame 100 is reached, the same sequence starts over as specified by the second frame card.
Notice that this sequence occurs, much more rapidly
while the same curves flore still evolving in the same relative way but in .the absolute time span fixed by
, the first card. When 200 is reached, a third sequence begins in conjunction with the two already in progress.
The third card states that curve number 4 is to be
linked ("L") to curves 1 and 2 + 3 which are concatenated (comma implies concatenation on the frame
cards). The "GO" informs the computer that this is the
last frame card for the defined curves. This entire set
of cards may be followed immediately by another set of
identification, parameter, and frame cards for successive sequences.
Other control8
Two data cards which the user may wish to alter
contain the defaUlt parameter values and the eX-
CAMP
posure time for the camera. These can be· changed at
the beginning of any sequence.
.
Before a sequence begins, a pair of function key
lights are turned on and the computer waits for a depression of one of the two corresponding keys. The key selected determines whether or not the camera will be
used for the sequence. If it is not to be used, the figures
are displayed as rapidly as they can be computed. If the
camera is to be operative, a curve is computed and displayed, the camera is activated, the curve is erased, the
next curve is computed and displayed, and so on.
The camera in use was specially made for this project.
Some features were included that are not usually as-"
sociated with microfilm recording systems. First, the
film registration meets quality standards of the motion
picture industry. Excellent frame to frame steadiness
has been achieved. Second, also in conformance with
motion picture procedures, the camera film' magazines
accepts standard 1000 ft. core wound rolls of 35 mm
film.
Other features of this camera are typical of microfilm
systems in general. The film movement is independent
of the shutter action. To advance the film one frame at
a time, a Slo-Syn stepping moter is used with an attendant translator power supply for variable speed. The
shutter is activated by a Ledex rotary solenoid. Switching, interface connections, and power supplies are contained in a box mO"Wlted on the camera's own floor pedestal. The interface connections to the computer include feedback circuits to detect shutter open or closed
positions and to confirm film advance so that computer
control is fully automatic and well supported with failsafe and sequence error detection.
Exposure tests established that an ASA 25 slow panchromatic type 5220 film was ample for good exposure
density. With the camera in place before the console,
an f/1.9 Baltar high resolution lens is set and locked for
a fixed field so that final positioning of the camera is
simply a matter of bringing a focus tape into contact
with the surface of the 2250 ORT and sighting through
a precision gun-sight type range finder. The camera is
positioned into fine adjusted alignment with the aid of a
computer generated test pattern.
The program turns on light 1 as a signal to open the
camera shutter; On responding, the camera effectively
1305
depresses key 1. This is followed by an exposure timing
loop in the program and subsequently light 2 is illuminated ordering the shutter to close. A successful responseto this command is signalled by the apparent depression of key 2 by the camera. Programmed logic
decides whether or not more information is to be displayed for this same frame of film. When the film frame
is to be advanced, light 3 goes on and satisfactory response by the camera initiates the corresponding key
depression.
With a working knowledge of this language, an artist can compose choreographic movements of simple or
complex visual patterns and exercise control over such
elements in ways never before possible. With additional
darkroom techniques, he can make still further use of
technological developments to add" color and even
sound as well as indulge in the purely human p~ocess of
editing. For example, the filmed product of our progranl
is subjected to certain optical procedures. The 35 mIll
black and white negative from the camera is processed
normally and printed on high contrast stock yielding an
image that consists of clear lines on a dense black field.
This film is threaded into the projector side of an optical
printer with a Bell and Howell movement and a 16
mm camera. The optical printer has several special features. The optical axis of the system is vertical with the
camera looking down into the R'rojector. The projector
itself is mounted on a compound mill table. Thus additional translations and rotations of a mechanical nature
may be superimposed, and the camera may be moved
along the axis so as to provide for an additional scaling
factor of from .1 to 10. A stepping switch circuit and
preset frame counter allow a wide range of skip frame
ratios to expand editing capabilities in the time domain.
At this point, we would like to present some slides
showing curves drawn with the stati c program, blackand
white moving pictures taken. directly from the 2250,
and color movies with sound added which were produced using some of the optical printing methods
described above.
REFERENCES
1 A HURWITZ J CITRON J YEATON
GRAF Graphic additions to FORTRAN
AFIPS Conference Proceedings 1967 SJCC
What good is a baby?
by NELS WINKLESS and PAUL HONORE
Communications Contact, Inc.
Mountain View, California
Some of us think that Computer Graphics is the wave
of the future and that our electronic gadgets will become standard tools for commerical artists. This is not
likely to h~ppen soon or suddenly. Both buyers and
sellers of computer graphics must change in significant
w'ays before our prophecy can be fullfilled. The changes
will not occur au Gomatically .
Let us approach the utilization of computer graphics
_with the thought that however hard we expect it to be
it win turn out to be harder. This business is not for
those who tire easily because we expect the whole undertaking to be depressingly difficult.
To begin with, people in the computer business always find it difficult to explain to their relatives and
neighbors just what they do.
Every once in a while someone rudely asks us what
we computer guys actually do with all the money we
take from him in the form of taxes and phone bills. He
doesn't necessarilv object to our having the money, but
he would like to have some feel for what is done with
it.
When we explain that computers are great for tasks
like matrix inversion and the solution of polynomial
equations he admits that he is impressed but he'd like
to have something in lay terms-and never mind telling
him about accounting and record-keeping. He. knows
about that because he has been corresponding with a
computer at the book club of which he is a member
and the impact of computers in that area is alreadv
painfully familiar to him.
At this point we not only tell him what we do, we
show him.
We make pictures with computers, see? (Figure 1)
He looks at our so-called pictures and says that since
he is neither an art critic nor a masochist he doesn't have
the proper background to judge our work ... and by
the way, how much would it cost to have a guy who
can draw make a real picture of something?
1307
There is a nagging feeling after one of these encounters that all is not right with the world. If we actually
had to do something useful to justify our place in
society, those of us who deal with computer graphics
would be very hard pressed. If we wish to improve our
standing instead of just defending our present position,
we face uphill work.
After all, how do we measure the usefulness of something in our society? We ask if somebody will pay
money or effort to have whatever it is.
Will people pay for computer generated pictures?
Who? Why?
I t's no fair counting other people in the computer
business although this trade increasingly uses pictorial
output. Computer people, like normal human beings,
are especially designed to make use of graphic information.
According to somebody who counted: "38% of all
FIGURE 1
1308
I
Fall Joint Computer Conference, 1968
fibers entering or leaving the central nervous system
are in the optic nerve." It is estimated that as much as
75% of information entering the brain is from the eyes. 1
As Scientific American readers know, there is a great
deal of evidence to suggest that information processing
is done in the eye before data are passed to the brain. A
recent estimate indicates that there are about a hundred million sensors in the retina and only five million
channels to the brain from the retina. This twenty to
one sort of data reduction is apparently not accomplished simply by using every fifth input on a sampling
scheme.
For example, to recall McCullough's famous work
. at MIT, if a frog's eye is isolated from its brain in an
experiment that measures output from the eye in response to visual stimuli it turns out that the eye is
very selective. If something that looks like a fly is moved
past the eye at about one frog's tongue distance, the
eye puts out a substantIal jolt in response. The eye wIll
not respond similarly to a list of numbers desc:dbing a
fly.
Even our Indo-European languages equate the words
"see" and' 'understand." "I see, Ya vizhu, je vois."
Seeing something is tantamount to understanding it.
We often plot numbers on a graph so we can see
what they mean. Programmers often surrender efficency and their native neatness to make their typewriters print out verv bad graphs because even a bad
graph provides more meaning usually than a tidy list
of numbers.
Some processes are too difficult to visualize mentallv
a.,nd we must turn oUf numbers into motion pictures to
grasp the ide.as. We've been involved with Sandia's
ACCEL circuit card design program 3 and it's interesting to recall that the first motion picture sequences
showing the placement and routing processes were not
made to demonstrate the working program after its completion. Thev were used to let the programmers see
what the programs were actuallv doing all along the
way.
It has been suggested that prime numbers might be
plotted graphically in such fashion that we could grasp
the visual pattern of their occurrence and learn to predict their place in the number sequence.
Of course the computer business can use computer
graphics,. but what percentage of our society is in the
computer business? A kid who sets out to be an insurance salesman can sell a few policies to his uncles and
cousins but soorer or later he has to go out and tackle
hostile strangers to justify the draw his company pays
him. We manage to draw a good many million dollars
from society and it seems we must figure out how to
sell our work to hostile strangers.
A small number of people have been triyng to make
a commercial venture of computer graphics. The survivors of the effort report vivid impressions of hostile
strangers.
When we say "computer graphics" we tend to put the
accent on "computer" and let the "graphics" take care
of 1tself. Actually, hostIle strangers are only moderately
interested in computers. To them a computer is sort of
like a head on a pole-nothing they'd deliberately
seek out, but interesting as a novelty.
On the other hand our prospects do know a lot about
commercial picture making.' They are keenly aware of
the mechanics and economics of their work. They want
to know what sort of thing we can draw, how fast, for
what price.
We can draw anything. (Figure. 2)
The actual drawing is done very rapidly and a thousand variations on a given piece of work can be produced with the speed of summer lightning, but the
programming and especially the input of data are
complex and tedious procedures. Further, the making
of pictures is a creative undertaking subject to irrational and unavoidable disagreements. Weare unable to
predict with confidence the time required to do the
work and live through all the arguments over taste.
Similarly we cannot predict the price. Any number we
choose is Ieally a blind stab.
We have tried to get around these sordid realities by
deciding that we are actually fine artists-as opposed
to commercial artists. Fine art speaks for itself. Commercial art has to be good for something.
Like everyone else in this field we were equipped
with a huge collection of randomly derived geometric
forms. They are quite interesting the first few hundred
FIGURE 2
What Good is a Baby?
times through. It isn't that we were so crazy about geometric forms, but the computer likes to draw them and
it jolly well won't draw anything else without a large
investment in time and money.
With op art at the height of its popularity we looked
around for somebody who appeared to like randomly
derived geometric forms. The big time art people who
run the museums were interested in the material· we
offered and asked what artist had done the work. When
we explained that no one who could quite be described
as an artist had done the work, only a programmer who
set some policies for the computer, there was a sense of
coolness in the air.
It was regretful that an artist had not infused our
work with artistic value. They named some artists who
might-lend grace to our poor efforts.
The recognized artists we talked to were hearty,
pleasant chaps who were not fools. They could tell
that we harbored a cynical attitude toward that sort of
art of which op is a sub class. They didn;t care to be
used by us. We did not wish to use them.
We might whip up more· enthusiasm if we thought
there were money in fine art, but how many non-objective artists is the world willing to support? When we
consult standard statistical references like the World
Almanac we do not find any figures dealing with fine
art, no indication of the annual yearly business of art
galleries, or the number of people who list their profession as "fine artist."
On the other hand, there are figures dealing with
advertising expenditures, with television programming,
with various sorts of things that depend upon the creation of pictures. One learns, for example that the annual billing of an ad agency like Leo Burnett Company
is approximately $250 million. That is $37 million more
than a published estimate of the annual budget of
Sandia Corporation. 4 Burnett is not the largest agency.
It's only about fifth. Sandia is certainly the largest
atomic bomb manufacturer in this country~
Presumably one can find out about the economics of
fine art but the lack of publicity attending the numbers
does not suggest that we can win the hearts and the
cash of our countrymen by automating Piet Mondrian ... even in three dimensions.
Fine artists will have an opportunity to use our
instruments and their creative help will be stimulating
and provocative. On the other hand we have not been
able to break down any barriers by acting as if our
randomly derived geometric forms are anything but
interesting exercises .. If they speak for themselves, they
speak an unknown tongue.
We really have little to show, collectively, in this
field. There is some variety and there are some spectacularly beautiful things. Some of the fine figure work
1309
at Boeing and some of Whitney's handsome work come
to mind. The trouble is that we have a little man who
couldn't draw better, faster, and cheaper.
On that basis it is very difficult to approach people
who normally make good pictures that fit their purposes well. In that case we are inviting them to take a
fling on research and d~velopment with our talent and
their money. We can weave dreams for them, but we
don't know how to perform to their specifications.
Indeed, they can't imagine how to specify anything for
us.
Obviously, we can use our techniques in the long run
for things like package design.
A designer could feed the basic elements of a new
package into the computer and get back five hundred
variations on a basic theme overnight. He could paste
up a few selected treatments right from the hardcopy
and deliver a virtually complete job to his client along
with a bill.
Many such commercial applications will be practical
once we have appropriate software, I/O hardware, and
the right attitude.
Meanwhile, there is one area in which we are· just
barely able to do something of value. We have in fact
sold computer animation to producers of television
commercials.
We started some years ago with jittery sequences of
geometric nonsense and bit by bit-literally-we have
worked up to smoothly flowing, shimmering, full color
sequences of geometric nonsense.
Television network executives look at it and say:
"Whatever would we do with anything like that?"
Hollywood producers say: "You show me an aninlated character emoting and I'll get you millions of
dollars." By then, who needs it?
When we showed black and white material to ad
agencies they said; "It certainly would be better in
color."
When we show them color footage they say: "It
certainly is hard to judge the basic art with all that
distracting color."
One producer was putting together a series of psychedelic backgrounds for use behind musical groups on
television.
He likes our colorful geometric nonsense and offered
to pay a dollar a foot for specially prepared material.
That's sixteen frames per 35mm foot. A three minute
sequence would pay us $270. If that footage· cost ten
cents a frame, total, including postage for sending the
bill, we'd lose $162 on the deal. Still, he was a live
customer offering genuine cash money. It liappens that
he is just as happy with out-of-focus pictures of splattering ink as he is with our expensively wrought material. So are most people:- Besides, ten cents a frame is
1310
i
I
Fall Joint Computer Conference, 1968
not enough by a factor of twenty or fifty or eighty,
depending.
Weare left searching for wealthy customers who
want to buy very carefully controlled, dramatically
. complex animation effects.
There is one such market.
When we worked in the television commercial business a typical one minute spot cost seven or eight thousand dollars to produce--about five dollars a frame.
That seemed like rather expensive production even in
Hollywood a few years ago.
Old friends in the business tell us now that a typical full blown spot for· a national sponsor costs eighteen thousand· or so dollars and it is not unusual to
spend thirty or forty thousand dollars-twenty dollars
a frame. That's enough to pay for some careful computer work . . . not too much, because most of that
money is carefully earmarked. Still, it beats trying to
swindle an artist out of his fellowship money.
People argue the point, but we feel that the television commercial is the great American Art Form-native grown, governed by stringent disciplines of time
and purpose--subject to fast feedback from a responsive audience of a hundred million people. There is
more creative innovation in television commercial
design, in commercial music, in the deft handling of
language than there is in films that are designed for
entertainment. We may quarrel about specific pieces
of work, but notice that your kids will run to watch a
commercial embedded in a program they have been
ignoring.
Our highly stylized computer animation is acceptable
and useful in television commercials.
Since we grasp the economics and the mechanics of
both filin making and computer animation we assumed
that we could head off most of the problems and interpret adequately between the film people and the
computer people in doing commercial work on contract.
We learned a lot that was not'intuitively obvious.
One thing was not a surprise. The man in the middle
gets a lashing from both sjdes. The surprise was the
number of subjects that bring on trouble.
There is a difference of viewpoints that makes it
hard for either side to tolerate the obstinacy and irrationality of the other. Since we in the computer busi~ess are- trying to sell something to the film people,
It seems that we must flex, not they-at least in the
short run.
Let us consider some conventions in the motion
picture business and brood a bit about the ways in
which our computer material varies from those conventions.
A professiona1 motion picture is usually composed
(Figure. 3) of rectangular images 3 X 4 in aspect ratio
-Q
~
~r-
a
a
a
.
Q
0
Q
a
a[
0
- ........
0
]9
EARLY 3X4 FILM.
APERTURE
FIGURE 3
arranged at regular intervals along a strip of sprocketed
35mm film. Sixty years of working with international
standards have established these specifications rather
firmly.
Computers put out pictures by two standard means,
through an oscilloscope tube, thence to either film or
sensitized paper that is processed to produce hard
copy, or through a stylus that draws an image directly
on paper.
Since oscilloscope faces tend to be round, efficient
practice suggests that the image area utilized on the
scope face should be the largest practical square. The
typical field is 1024 by 1024 points. This is not only
practical, b'Ut 210 is a number of great power among
mathematicians. The product of this mystical rationale
is a square picture.
A chap at Eastman Kodak did a study almost forty
years ago in which he measured 250 paintings by fifty
famous artists. These were pictures that people were
willing to pay good money for and to hang on their
walls.
The plot of width to height of these pictures looked
like this: (Figure 4). Square pictures were very scarce.
Another researcher wrote during the time when
sound movies were just coming into use:
, 'We purposefully use the expression 'rebellio~' because for the first time in motion picture history a
number of exhibitors and at least one of the greatest
exhibiting and distributing organizations in America
have taken matters into th~ir own hands and have reduced the height of the projector aperture. They have
considered it essential to maintain the rectangular
form of the screen even at the risk of cutting off parts
of the performe;s heads or some detail of the lower
part of the general scheme of composition. Such procedure is rebellion and what is more important, it is
seemingly j ustifia ble. "8
(Figure 5) The situation was this: the 3 X 4 aspect
ratio had been established early in the movie game
because people liked it that way. When sound came in
What' Good is a Baby?
1311
Q'-_ _ _. - J Q
a"....----.... o
Q
C
o
Q
C'---------
Q
C)
a
MOTION PICTURE -ACADEMYAPERTURE,NOTE: PICTURE
AREA IS OFFSET FROM FILM
CENTER LINE
5
Ratio W toH
1.4
1.6
1
Ratio Curve of 250 Paintings by 50 VVelI Known Artists
FIGURE 4
Q
Q
~D~
Q
Q
at ,-_
0
0
JO
EARLY 3X4 FILM
APERTURE
1.1:1 FILM
APERTURE WITH
OPTICAL SOUND
TRACK
FIGURE 5
it was clear that the track had to be put somewhere so
it was printed inside the sprocket holes in what 'had
been picture area and the picture area was chopped off
to make room, leaving a square image. 'It was efficient
and practical and people hated it.
(Figure 6) The present so-called Academy Aperture
was a compromise arranged by the ::\Iotion Picture Academy to meet this problem. It is inefficient and reduces
by an appreciable fraction the possible resolution of the
picture on the screen, but people like it.
At le~st thirty years after this drama when we first
needed. some computer generated footage, the nlessenger bro~ght back from the data center a roll of
randomly spaced square images filling from side to
side a piece of non-sprocketed 16 mm film. Run that
through your projector! We h~d to shoot more nearly
standard film footage from hard copy of this stuff.
This brings up another quaint custom of the computer business. It seems a shame to make an issue of
the fact that this industry at the very forefront of
FIGURE 6
technology is using antiquated methods, but the fact
is that scrolls have been largely out of use in civilized society for some hundreds of years. Computers tend
to print out scrolls.
Machines may handle scrolls comfortably but people
don't. Further, machine operators aren't accustomed
to really long runs of hard copy. During our two thousand frame runs the machines gradually ran out of
developer and the last few hundred frames were decorated with orange-brown streaks that wove strangely
through the movies.
No matter, we can now put the images on regular
movie film but it would never occur to a producer to
specify sprocketed .film and it does not necessarily
occur to computer people that it matters.
We use the scrolls only in short test runs of some
material and calm handling of the paper solves all problems. Still, there is little calm in the motion picture
business and the customer always winds up with
crushed and torn artwork somehow. It seems a pity.
Don't accept the simple thought that standard cameras taking pictures off the scope solve all the problems.
There's still that square picture to contend with and
the computer readout equipment is in general completely inflexible. The camera is locked into an electronics rack over the tube and it stares fixedly at the
square image. If you're like us you don't own the equipment and you're in no position to modify what they
have at the data center.
(Figure 7) Suppose you want the camera to see only
that portion of the square that makes a 3 X 4 image
and you can program so that all the action takes place
inside that rectangle.
You call the man with the readout machine and say:
, 'Can I position the camera so that each standard rectangular frame of motion picture film is filled from
side to side with the scope picture?"
, 'Yes" he says, ' 'the image is normally 17 X 17mm
1312
Fall Joint Computer Conference~ 1968
X.".
u ....... ']
~Q.Qgg
HSl'ANDARD" 35mm CAMERA FILM
35mm MOVIE FILM
FIGURE 7
FIGURE 8
but it can be expanded to fill the frame from side to
side."
"Good!"
. "We can expand it to 19mm," says he.
Since a normal frame is about 25mm wide you can't
fill it with 19mm of picture and you point this out.
(Figure 8) After an airplane ride he didnit want you to
find out that his idea of side to side is your idea of top
to bottom. He thinks of the film as running horizontally as it does in a 35mm still camera.
Crying relieves your feelings, but it doesn't modify
the hardware for you.
You carve your 3 X 4 area out of the available
square and photgraph it. This gives you a small rectangle of picture the proper shape somewhere in the
normal film field.
The producer who is paying you will have to blow
the image up to fill the frame. He resists the thought
and expense and you tell him about 210 and how mathematicians are fond of it. He tells you to move the
camera and you re-live the whole scene at the center.
Of course, the producer has to go to the optical
house with his film anyway because you are supplying
him with three separate strips of high contrast black
and white microfilm. (Figure. 9)
These three strips must be printed in register, each
with a different color filter, to produce a final color
negative. It's just like color separation work in printing. Dreary technical concerns prevent production of
COMPOSITE COLOR PRINT
FIGURE 9
fully saturated color pictures right from the scope onto
color stock.
The producer is also horrified to hear that the picture we produce for him is centered on the film. The
Academy aperture to which he must convert this stuff
is not centered on the film. It is off to one side, leaving
room for the sound trac~ the way it is supposed to.
Not only that, the producer must rely on the computer people to generate designs that allow each of the
three strips to be approximately uniform in density.
That is to say: very fine lines On the negative can
stand to have a' lot of light pumped through them for
reproduction on prints. Too little light will leave weak,
broken lines with poor color saturation. On the other
What Good is a Baby? lal3
hand, large areas of solid color will bloom on the print
if too much light is used in printing. If a given frame
contains both fine lines and large areas the printer
cannot balance for either and the product is bad.
Further, if the producer does not want the colors to
blend at the points where lines intersect, he must make
traveling mattes~a process too complex to cover here,
but fussy in the extreme and especiaily difficult with
multidudes of fiD.e lines.
If our irregular film product is to be made useful to
the buyer, we must anticipate a great many little problems. Some unexpected things crop up.
Normal motion picture film is numbered along the
edge so that the original film can be matched foot for
foot with prints made from it simply by matching
numbers.
The microfilm stock normally used in computer
systems is not edgenumbered. Nobody thinks about
this until the editor bursts into tears after days of working with footage he cannot make head nor tail of.
We've been talking about purely mechanical matters.
Consider creative problems.
A computer can do things a human animator cannot
do. The computer can move each of ten thousand
lines from frame to frame without fatigue. The human
animator gags at the thought.
He not only can't do it practically. He can't imagine
why he would want to. It is utterly outside his experience. If he designs action he does understand he
wastes the capabilities of the computer. Anything he
really understands can be done better and cheaper by
hand.
He can't figure out what to do with hundreds of
units of animation. He can't imagine what such stuff
would look like, what to ask for. He does get a warm
glow when we tell him that the computer will cheerfully draw action that is tough for human animators.
It will move active figures toward and away from the
camera and maintain the sort of perspective variations that occur when real objects are photographed
We're not talking about regular forms that appear
to move near or far simply by changing size. We're
talking about the kind of distortion you get with a wide
angle lens. (Figure 10) Such a lens enlarges closer parts
of the figure more than distant parts. It is easy for an
animator to show a figure walking left to right across
the field at a given distance. It is much harder to make
that figure look right when it walks toward the camera.
The computer can handle that sort of thing well by
formula.
The animator senses the power of the tool we offer
when he thinks about this sort of thing, but he still
doesn't know how to use it.
He's not about to learn for a given commercial job.
FIGURE 10
The producer suggests that he send his animation
director out to work with us at the computer so he can
see what actually happens to the rough ideas they
eventually pull together.
He is disappointed when we explain that the computer is a smashingly uninteresting box that lives in a
room of its own behind an iron fence somewhere. Even
if we do have access to the computer it does nothing
more dramatic than blow 'hot air on your shoe while it
hums and soaks up money.
The computer output is invisible, just a lot of magnetic signals on tape that must be transported to the
printout system somewhere else.
Fine, he'll have his man watch the printout machine.
No such luck, the thing is sealed tight and the outside
of the box doesn't have the visual appeal of a Brownie
Reflex.
He can see sonie test pictures, stills drawn on scrolls,
that show him what the computer thinks it is supposed
to be drawing, but he can't see test runs of. animation
unless he wants to pay a fortune for the privilege.
Normally his animators draw the material roughly
in pencil and photograph that directly in what is logically known as a pencil test. It gives him a feel for the
action and allows correction at an inexpensive level. .
It's all or nothing with the computer. Onlv faith and
1314
Fall Joint Computer Conference, 1968
hard liquor allow the customer to hold his peace while
he waits to see the finished product.
In spite ~f all, the struggle has been worthwhile in
practice. The effects are so striking, especially the
effects of bugs, that customers do come back for more.
The point that seizes our attention is really that the
computer is completely wasted if it is used to produce
material that is already well understood and is under
full controL We have a brandnew medium and none of
us quite knows what to do with it. This is not without
historical parallel in the computer field or in the motion
picture field.
Each of us has sometime been through a discussion
with people who are convinced that a computer is
simply the equivalent of ten thousand men with adding
machines. They grant the idea is impractical but they
feel we are begging the question when we insist that
computers a,re really more than that. Well, maybe, but
we were not able to predict from our knowledge of
people with adding machines many 9f the things we
now do with computers. Our viewpoint has changed
with experience.
With respect to graphics, we suspect that the computer is more than the equivalent of ten thousand men
at drawing boards. We must assume that the future
holds surprises for us.
When motion pictures were first developed-if
you'll pardon the pun-the mere technical fact of being
able to record and reproduce moving images was stunning. It struck people that they could record great
actors in great plays and carry the film off to places
where people had never seen fine drama. Culture could
, be taken to the people.
Indeed, they put cameras down in the audience and
recorded plays for the enrichment of mankind.
I t turned out that motion pictures were no good for
what they had in mind. If you plop a camera down and
let it watch a play you find that the camera doesn't see
a play the way a human being does. It is non -selective.
When a human being watches what the camera has
'recorded he is bored to tears because he cannot escape
the camera's ~ewpoint.
Every motion picture technique we now take for
granted was at one time a startling innovation. _
Everybody knows full well that one image following
another on film follows in time as well as in position on
the film. Still, if you see a burning house in one scene,
then action at a firehouse, then a picture of a woman
picking up a baby in a smoky room, you assume that
these pieces of action are related and may be simultaneous in time. How do you know?
The first motion picture to include edited action of
this sort was very creative in the eyes of the people who
saw it. Although roughly similar action in stage plays
was common the effect was not quite the same. The
camera could be moved and it was a surprise that story
continuity could be maintained-even enhancedin spite of abrupt changes in viewpoint. Motion picture,
technology was wasted if it was used only to record
material that people already understood and could
comfortably controL
Motion picture techniques developed rapidly because
the technology was rather simple. Anybody coUld
operate a camera and even process his own film with a
bit of experience. Of course there was a big hassle about
standards. Further, stage directors and actors did not
all readily adapt to the limitations and new opportunities inherent in making movies. A whole new class of
creative craftsmen had to grow up in the film business.
N ow here we are with a new medium-computer
generated pictures. Our technology is not simple. Our
equipment is not designed so that anybody can handle
it and innovate in the new medium. Even timesharing
systems with light pens and memory drums and CRT
displays allow laymen to do only such crude work at
great expense that we do not see these systems as the
key to general progress. Outsiders with fresh attitudes
cannot easily join our club.
Weare doing something,about the input bottleneck.
We're starting to beat the problem of teaching the
computer what to draw. Till now the mere input chore
was more costly than the programming and computer
cost. It isn't that the programming is easy. It's just
that after years of learning what to do to make things
move the way we want, the big task in any given production job is to ram the picture data into the miserable
machine. Weare improving that and it will help a lot.
Does it matter to us how the computer graphics
revolution will occur if we are so confident that it will-,
apart from commercial considerations?
Well, there's that nagging question about what we
have been doing with all that money society spends on
our recommendation. Can we produce anything,people
want to buy?
So far, nobody can tell what we have to offer and as
long as we speak gibberish and put out our work in
forms nobody can use, hardly anybody will trouble
himself to find out what we have to offer. Their enthusiasm for paying us may evaporate.
There is the happy possibility that a whole new
class of creative craftsmen will grow up among us. If
we actually follow standard practices in the graphics
field and speak something resembling English or Russian or Chinese and we develop hardware that anybody
can use without fjve yeal'S of intensive training-then
the hostile strangers may actually buy things from us,
whatever those things turn out to be.
There's an old story about a man who presented a
What Good is a Baby?
new idea and was asked what it was good for. He
floundered for a while and said:' 'I don't know, but what
good js a baby?"
If we help our computer graphics baby to grow up
we'll find out what it's good for.
REFERENCES
1 F R SIASJR
The eye as a coding mechanism.
Medical Electronic News
2 GBIERNSON
1315
A Jeedback-control model of human vision
IEEE Proceedings June 1966
3 C J FISK D L CASKEY L E WEST
ACCEL Automated circuit card etching layout
IEEE Proceedings November 1967
4 Article re Sandia Corporation
Business Week March 1968
5 LAJONES
Rectangular proportions in pictorial composition
SMPTE Journal #14 Jan-Jun 1930
6 A SHOWELL J A DUBRAY
Some practical aspects and recommendations on wide film standardsSMPTE
Journal #14 Jan-Jun 1930
A computer animation movie language for
educational motion pictures*
by D. D. WEINER and S. E. ANDERSON
Syracuse University
Syracuse, New York
INTRODUCTION
The value of motion picture films as an effective
teaching aid has been long established. In recent years
preliminary efforts have demonstrated the feasibility of
producing animated fihns by means of a digital computer in conjunction with a microfilm recorder. A block
diagram of the computer animation movie process is
indicated in Figure 1. A programming language is used to
translate the motion picture script into a computer program. The program, usually in the form of a deck of
cards, is processed by the digital computer which generates a magnetic tape output for input to the microfilm
recorder. The recorder, containing a cathode ray tube
and motion picture camera, produces an exposed roll of
fihn that is then developed to yield the finished motion
picture.
Advantages of computer animation
Computer animation has many advantages to people
having educational needs. Some of these are briefly in.
dicated below:
1. Computer animation makes it possible for individuals with many different backgrounds to make motion
pictures. The movie language, if carefully designed, aan
readily be learned and used by personnel who have no
particular technical background in computers and motion picture production. In addition, because of the large
num ber of computer centers distributed throughout the
nation, the computer ~imation capability can be
available to potential fihn producers irrespective of their
geographical location .
~
2. Computer animation is a relatively economical
technique for producing motion pictures. Of course, the
cost depends upon the complexity of the images being
.generated. Past experience with simple line drawing
*The above work was sponsored by the United States Air
Force under the Contract No. AF 30(602)-4283.
l317
animation indicates a typical cost of approximately
. $.10 per frame. In contrast, conventional motion picture
techniques average around $1.40 per frame. Thus, it
should be possible to extend the use of the animation
technique into areas of education and training where
formerly it was precluded because of cost.
3. Computer animation allows the film maker to
generate revisions with minimum expense and effort.
By changing the proper parameter in only a few instructions of the program, it is possible to produce several
versions of a film sequence having different motions,
spacings, scale, object dimensions, and picture complexity. Thus, at relatively small cost, t,he film maker can
experiment with different arrangements to obtain certain desired effects so as to improve the illustration and
explanation of the subject matter of his film.
4. Computer techniques can produce animated film
much more rapidly than conventional methods. When
both digital computer and microfilm recorder have been
available at the sam€. site, it has been possible to begin
and finish a five minute film -clip within one week's time.
In addition, successive animated films require less time
and effort because subroutines developed fOl a particular film can then be used in future films.
Basic movie language developed at Syracuse University
The capability for graphic digital computer output
has been available fOl many years. However, where
movies are ooncerned, thousands of frames of film are
usually required. For example, a 5 minute movie running
at 24 frames per second oonsists of 7200 frames. It is
FIGURE 1
1318
Fall Joint Computer Conference, 1968
impractical to program each frame as R separate entity.
What is needed is a language that is capable of generating tens, or even hundreds, of frames by means of justa
few instructions. Suoh a language has been developed at
Syraouse University.
The language consists of the four programs:
1) CALD (Computer Aided . Line Drawings)
2) CAPER (Computer ~ided Pe~speoti:es)
3) CAMP
(Computer Aided
M~t).on
PICt~l'es)
4) CAMPER (Computer Aided MOVIe PerspectIves).
CALD and CAPER are wri;tten for output on the Cal
Comp' 565 mechanical plotter While CAMP and
CAMPER are to be used with the Stromberg Carlson
4020 miorofilm recorder. A capability for output on both
the mechanical plotter and microfilm recorder is needed
because of the unavailability of a conveniently located
microfilm recorder. When producing computer animated mo1ion pictures, several attempts are usually required before satisfactory results are aohieved. In addition to debugging the program, the animator often experiments with various picture parametere so as to best
obtain a certain effect. Beoause no microfilm reoorder is
located within the Syracuse area, the magnetio tapes
are sent for prooessing to the nearest installation at the
Polyteohnic Institute of Brooklyn located approximately 300 miles away. In order to eliminate long delays during the debugging and experimental phase of the movie,
provision is made for graphio output on the University's
mechanioal plotter. It is intended that movies be debugged by plotting selected frames using CALD and
CAPER. Sinct the names of the oommands in CAMP
and CAMPER are identical to those of CALD and
CAPER, little additional work is required to convert
from the mechanical plotter to the microfi1m rE-cOl'der.
The option exists for drawing pictures in either a two- or
three-dimensional representation. CALD and CAMP
are programs for generating and manipulating basic
line drawings and simple geometric figures in two
dimensions. CAPER and CAMPER are programs for
creating, manipulating, and plotting three-dimensional
figures onto a two~dimensional plane in true perspective.
All four programs have been written in FORTRAN
IY. It is recognized that other programming languages
are more versatile and efficient. However, the use of
such languages is limited to a relatively small number of
computing centers. If computer animation is to develop
rapidly into a useful, effective, and widely available
educational tool, it is desirable to create a common library of subroutines that will be available to as many
computer installations as possible. Clearly, FORTRAN
IV is ideally suited for this purpose. Unavoidably,
either assembly or machine language is needed to provide the input codes for both the plotter and the microfilm recorder. (FORTRAN IV is unable to manipulate
data on a bit level.) Fortunately, this is required for
only a very small number of commands.
The four programs consist of a series of subroutines.
Each subroutine is called by one data card. The program user need not know FORTRAN. He need only
learn the movie language (i.e., the name and function of
each command and the purpose of the parameters associated with each command). The names of the subroutines and associated parameters have been chosen to
be as simple and descriptive as possible. Should the user
be familiar with FORTRAN, it is possible for him to
enlarge the original set of subroutines.
A list processing technique is used for the storage of
pictures. Each new figure is stored consecutively at the
end of a variable length list, called a stack. Each figure
within the stack is called an array. Figures are ref~rred
to by specifying their respective stack and array numbers. Stacks and arrays can be altered either in total or
in part. Hence, it is possible to individually alter entire
frames, figures within frames, or points within figures.
Figure 2 gives an example in which the arrays of two
separate stacks are used to store the basic figures
generating the dog and the letters comprising the text.
Should it be desirable to wag both the dog's tail and
ears, it is only necessary to modify the fourth and
seventh array of the first stack. Thus, constant backgrounds and non-varying portions of a frame need not
be computed more than once during an animated sequence.
Basic figures are provided for in the movie language.
For example, Figure 3 illustrates the command used to
generat~ an arrow. Sand ARR denote the stack and ar-
0
B
t:.
t:.
~
()
0
'II
Bnw wow
'II
0
'II
<0
~
I>
t>
..
FIGURE 2
Computer Animation Movie Language
ARRowls.IARRlpIXlIYl.lx2.IY2IHEAOI
T I ME=ll
?j,,(X2'YZ)
-J
(Xl,Y1)iii
1319
.~~I
HEAD
FIGURE 5
FIGURE 3
ray numbers in which the arrow is to be stored. The
parameter P equals 0, 1, 2, or 3 depending upon
whether the shaft is to be solid or dashed and the head
open or closed. The arrow is directed from the coordinates (Xl, Y1) to (X2, Y2) and the size of the head is
specified by the parameter HEAD. Subroutines for
generating circles, rectangles, triangles, crosses, grids,
clocks, and sine waves are also available. Some electronic circuit symbols are included.
In addition, an alphanumeric set of 49 characters is
provided. They have been created using straight line
segments and may be manipulated in size, position, and
orientation so as to give a large degree of flexibiJity in
creating text. When lines of text are desired, a single
command can be used that automatically spaces up to
20 characters. If more than 20 characters are required,
the command can be used consecutively to concatenate
the strings of text. A sample title used in a movie explaining the movie language' is shown in Figure 4.
Figure 4 also illustrates the masking routine. By
specifying the boundary of a rectangular area, it is possible to draw only those lines and portions of lines that
fall outside of the specified area. As an application of the
masking routine, Figure 4 is taken from a "dissolve" sequence in which the rectangular area is made successively larger until the entire title has been masked
leaving a blank frame of film. In this way, an interesting
scene transition is made. Windowing, the inverse of
masking, is also part of the movie language. With this
routine only those lines and portions of Jines that fall inside a specified rectangular area are drawn. In Figure 5
the windowing routine is used to simulate an odometer.
During the animation sequence, numerals move vertically through the window indicating current time on the
clock.
Commands are provided for the translation, rotation,
and magnification of objects. The rotation command ro-
COMPUTER
A
T
ni=-l]
Ml),1
1
IN
CB@
0
0
0
PICTURES
FIGURE 4
FIGURE 6
1320
Fall Joint Computer Conference, 1968
helpful in animating sequences, is the MOVE command
which moves an object in equal increments from an
initial to final position. This is demonstrated in Figure 7
where the six animated figures are produced by means of
only two MOVE commands.
Finally, three commands (SAVE, ESAVE, and REPET) are included for use when the same scene is to be
repeated many times. A great deal of computer time is
saved since the scene is retained in SC-4020 coded form.
Figures 2-5 and Figure 7 are taken from a ten minute
computer animated movie explaining the CAMP movie
language. This movie will be shown as part of the conference presentation. Additional film clips will be included as time permits.
FIGURE 7
tates an object about any desired center point by a
specified angular incremen t. The magnification command expands or contracts all points of an object as
measured from any specified reference point. Figure 6
illustrates the simultaneous use of magnification and
windowing to properly truncate an object as it is blown
up beyond the limits of the screen. Another command,
REFERENCES
1 K C KNOWLTON
Computer-produced movies
Science Vol 150 Nov 26 pp 1116-1120
2 AM NOLL
Computer-generated three-dimensional movies
Computers and Automation Nov 1965 pp 20-23
3 EEZAJAC
Computer anima,ion a new scientific and educational tool
Journal of the SMPTE Vol 74 Nov 1965 pp 1006-1008
Design highlights of CABAL- A compiler-compiler*
by RICHARD K .. DOVE
Carnegie-Mellon University
Pittsburgh, Pennsylvania
languages which are fed into syntax and seman~ics
loaders. Each loader builds a table, one controllIng
The advantages offered by compilers over machine or
recognition and parsing and the other containing a
assembly coding are well known to all of us. The perdescription of the meaning of statements. These two
sonal satisfaction and minimal execution time of optitabltis, a single pushdown stack, code generation
mally perfect code rarely outweigh compiler language
routines, and common translator facilities form a
implementations which are implemented and debugged
table-driven translator. Each element in the stack conquicker' and cheaper. The returns from readability and
tains a syntactic construct and its associated semantics.
machine independence further unbalance the scales.
When a construct is recognized the semantic informaIn an effort to reduce the amount of required machine
tion in the stack a,nd the semantic table direct the
coding to a minimum, compiler-compilers are begintranslator to take some action, usually code generation
ning to attract attention. Although the systems proor compile time memory for things such as declarations.
grammer must continue, to struggle with operating
Currently, the field is characterized by three efforts:
systems, compiling has been around long enough that
FSL 2 TGS 3,4 and CC.o FSL consists of two parts:
"
.
formalisms and common techniques are being forged
Floyd-Evans6 ,7 production~ provide a picture language
into various compiler writing languages. The current
for syntax recognition and a series of semantic routines
literature reflects the youthfulness of the field. New
linked to certain productions direct the semantic proconcepts and solutions to new problems have affected
cessing when constructs are recognized. Code generacompiler-compiler design in a predictable way: the
tion is accomplished through a code bracket facility
primary concern has been to demonstrate a working
which allows one to specify arithmetic and control
system. Only after we relegate these new problems to
coding using semantic information stored in the pushan innocuous position and comfortably understand the
down stack. The effort here was mainly toward develnew concepts involved do we turn our attention to
oping a machine independent formal semantic lanuseable systems as opposed to workable systems.
guage.
The current state of the art is surveyed byFeldman
Unlike FSL, TGS consists of a single language comand Gries in the February 1968 Communications of the
piled into an int~rpretive code. It contains a pattern
ACM.l Along with compiler-compilers, he includes
matching facility similar to. FSL's productions, but
discussions and evaluations of automatically produced
the matching range is more flexible in that it can be
reca'gnizers, syntax-directed symbol processors, metaused on a number of stacks as well as various properties
assemblers and extendible compilers, as well as an
other than identity of symbols. Code generation first
introduction to the necessary terminology.
goes through an' intermediate phase whose outpu~ is
Before discussing the CABAL design some informathen processed by a code selection phase producing
tion drawn from the Feldman-Gries survey of compileroutput for later assembly. Although TGS has more
compilers will supply some context. Generally speaking" , flexibility than FSL, it requires lnore detailed informawhen a compiler for some language is needed, its syntax
tion from the compiler-writer.
and semantics are ea'ch expressed in appropriate metaCC, the compiler-compiler project at Manchester
University, uses a top down syntax analysis which
produces a complete syntax tree later used by the
*This work was supported by the Advanced Research Projects
semantic phase. As it builds a tree top down analysis
Agency of the Office of the Secretary of Defense (SD-146).
INTRODUCTION
1321
1322
Fall Joint Computer Conference, 1968
does a considerable amount of backup; consequently,
the recognition phase is slow. The syntax phase uses
a BNF-like construct for recognition. Non-terminal
symbols are handled by format statements which in
turn call format routines to do semantic processing and
code generation. An open ended design allows new
format statements to be defined at compile time; thus,
CC can produce extendible compilers.
CABAL
The highlights of CABAL are presented in this
section following a brief discussion of the design goals.
The design criteria were formulated by an evaluation
of CABAL's ultimate environment considered on three
levels: physical system, user, and maintenance. Additionally, the fact that these will change demands an
open ,ended design which can grow as the environment
changes.
The physical system environment contains both
hardware and software appropriate to a, rapidly expanding computer utility. This means a configuration
consisting of various types of remote terminals, a
multiple number of control processors of unlike design,
and operating systems capable of time sharing, batch
processing, and possible parallel processing.
Maintenance must be considered for' compilers produced by CABAL as well as for CABAL itself. With a
useable compiler-compiler we may well expect more
compilers t~ would otherwise be the case. Anything
which could help to reduce the amount of time for
maintenance personnel to learn and maintain systems
would be welcomed.
The CABAL user environment will include the usual
systems staff interested in implementing permanent
systems. However, there will also be researchers working on compiler and compiler-compiler techniques,
languages, and large programming systems; graduate
students whose theses involve special purpose languages
to implement their main concern; and enough nonsystems oriented talent looking for means to express
itself that lowering the amount of pain incurred to
implement a language system will increase the amount
of talent used.
Considering the environmental factors and some
well known rules of thumb has led to the following list
of design criteria:
1. applicability of compiling language translators;
2.
3.
4.
5.
wide range of producible translator types;
flexibility in a dynamic environment;
modularity;
power and terseness for the professional systems
programmer;
6. transparency for the non-professional user;
7.
8.
9.
10.
readability;
machine independence;
reliability;
compatability with environment.
Basic structure, appearance, and control flow
CABAL is an ALGOL-like language and in fact has
ALGOL's block structure comnlete with BEGIN-END
pairs and identifier scope. In addition, the internal
structure of a block is divided into a declaration part
followed by a statement sequence part. Among other
things, the declaration part includes declarations for
two programming structures; co-routines and ALGOL
procedures. A co-routine declaration is syntactically
similar to an ALGOL procedure declaration and will be
discussed shortly.
At a lower level, modular concepts are applied to the
structure of the various language constructs. Concepts
with similar meanings exhibit similar structure. For
example, the syntax for accessing an element within a
multiple element data structure uses square brackets
around the indexing information. An extension of this
concept demand~d square brackets around the indexing
information associated with accessing bit fields within
elements. Thus, A [3] . [4J requests bit number 4 of
element number 3 in data structure A.
Applying modular structural concepts again resulted
in declarations resembling those of PL/I rather than
ALGOL's. Whereas ALGOL has individual declarations for each kind of typed storage structure, PL/I
has a single DECLARE construct which is parameterized. Extensions can easily be accommodated without
adding a new declaration concept.
Modular structure concepts and simplicity considerations were responsible for unitizing five data structures
into a single concept. An examination of data structure
declarations will finish the structural concepts. CABAL
has only one data structure. However, it has the capability to function as a scalar, array, threaded list, stack,
or queue. Trees and plexes can be built from threaded
lists. The syntax is:
::
= DECLARE
::
=
«structure> )
I,
( < structure> )
:: =
::
=
NUMBER,
< number optio> n
ILOGIC,
Design Highlights of CA"SAL
\STRING ,
INAME,
::
=
I?I?
::
=
< element linkage>
1
,FIXED
1
, [< bound pair list> ]
< pop linkage>
< pop linkagf3> :: = , LIFO
1 ,
FIFO
1 ,
RANDO M 1
::= :
1
< bound pair list> , < bound> : < bound>
::=
.. -
1
,
I
I
< name> < digit>
::= (the null string of characters)
< number
expression>
(expression of type
number)
Examples follow for scalars A and B, array C,
stack D, and list E:
DECLARE A,B (NUMBER,6),
C(LOGIC, 4, [0:10,0:10]),
D(STRING, 10, [1:?15],LIFO),
E(STRING, ?,[1 :?],RANDOM);
Thus, if there is no element linkage a scalar is signified, element linkage without pop linkage results in an
array, and the presence of pop linkage signifies how
elements will be pushed and popped for stacks, queues,
and lists. FIFO signifies first in fir~t out; LIFO, last in
first out; and RANDOM, arbitrary inserting and removing.
The expressions following the type indicate how
many significant figures associated with the type in
question are to be retained. Limits on these will be set
.by the implementation. A ? signifies an unknown
number and results in dynamic allocation. An expression following a ? indicates the user's guess and allows
the compiler to take advantage of this information for
efficient structuring.
Co-routines
Conway8 introduced co-routines in 1963 in a paper
1323
discussing their use in implementing a COBOL compiler .
Since then co-routines have been recognized as a
natural implementation for pass concepts in multiplepass compilers. For this reason, as well as their application to parallel processing, they are included in
CABAL.
A co-routine is a programming structure similar to a
procedure. However, unlike a procedure which begins
processing at its first instruction each time it is called,
a co-routine resumes processing following the point
where it last gave up control. A second difference is
that co-routines do not exhibit the master-slave relationship between a procedure call and the called procedure. A co-routine receiving control is not required
to return to the caller but may consider itself at the
highest control level; being free to pass control anywhere without creating a chain of linked returns. Thus
a co-routine is characterized by an incremental mode
of processing and an autonomous mode of access.
Syntactically co-routines are identical to procedures
with two exceptions: their declaration specifies COROUTINE rather than PROCEDURE and they may
contain a COMMON declaration which has no meaning
in a procedure. The COMMON declaration is simply a
statement which is executed every time control enters
the co-routine in concern. Immediately after execution
of the COMMON statement control passes to the
internal point which last gave up control.
Co-routines retain their autonomosity when receiving control from GOTO statements. However, they may
also receive control in the standard procedure call
method. In this latter situation they are required to
return control just as a procedure would.
Recursive operation necessitates a different approach
than procedures due to their incremental processing
nature. Rather than having only the deepest nested
recursion available to the system, as is the case with
procedures, instances of co-routines are duplicated and
each is actively a part of the system.
Allocating an instance of a co-routine may be done
one of two ways. For example, if C is the name of a
declared co-routine and N is a variable of type NAME,
then N~FORM(C) will assign to N the form of C,
allowing N to be used as if it had been declared in place
of C; and N ~COpy{C) will assign to N both the form
of C and its current status, again N can be used in place
of C. The current status provides current local variable
values and the next point of entry associated with the
co-routine when the COpy function is invoked.
Reductions and related concepts
A reduction statement provided for syntax recognition offers a convenient pattern matching facility for
stack elements. An example will clarify:
1324
Fall Joint Computer Conference, 1968
L: I'WHILE', EXPI~STAIWHCODE;RETURNI
The sequence of events is as if an IF-THEN statement were executed. If the top two stack entries match
the left parts, EXP and WHILE respectively, the
statement sequence WHCODE ;RETURN is executed,
otherwise control passes to the statement following
the reduction statement. The right part, STA, is used
only if a match occurs; in which case the left part elements are replaced by STA, a single element. This
replacement occurs either when the statement sequence
completely gives up control or a manipulation statement is encountered in the statement sequence, whichever occurs first. A manipulation statement is simply
a * which requests the stack be manipulated now.
Elements in the left and right parts are of two kinds:
literals and meta-characters. The literals, signified by
quotes, cause straightforward comparisons between
the character string enclosed in quotes and the character string associated with the corresponding stack
position. Meta-characters represent a group of literals
and are matched if the character string associated with
the corresponding stack position is identical to any of
the group.
CABAL associates a meta-character with its member
literals through a define declaration. An example covering unary and binary numerical operators follows:
"+,"
= UNOP 1"/"1"*"1"1' "1"0"1" e";
DEFINE UNOP
BNOP
= "-"
1
Additionally, meta-characters can be defined for nonprinting characters like end-of record, end-of-file,
carriage return, tab, space, backspace, etc. by using
the numerical equivalent of the character in question
as a definiens:
DEFINE EOC = 64.
The matter of the sigma function, a meta-character
which always matches, is taken care of by the absence
of either a meta-character or literal, when one is clearly
called for by the comma placement. Alternatively, for
those who demand a printable sigma function, a metacharacter may be used whose definens is empty.
Actually reductions are not restricted to operating
on stacks, any data structure will do. However, trying
to match a two element reduction to a scalar is undefined as is any match which is larger than the declared
size of the coupled data structure. A multiple element
data structure with ? number of elements is permissible
though.
Should ambiguous cases arise such as:
IA,B,AI~A,BIRETURNI·
where the meta-character A in the right part could be
either of the two in the left, a subscript is allowed in
the right part signifying the left part element number.
IA,B,AI~A(1),BIRETURNI
Counting is from right to left.
Couple statements are used to dynamically associate reductions to ~J specified data structure. Reductions are coupled to the structure specified in the last
executed couple statement at the same or higher block
level. .
There is a system supplied routine which will produce
a unique integer value for every unique character string
supplied to it. The inverse function is also available.
Normally, reductions will expect these unique integers
to be stack entries rather than character strings as a
considerable time and space saving can be realized.
However, should a particular parsing job consist of
short strings only, it might be profitable to bypass the
string translation. Communicating the nature of stack
contents is accomplished by the stack type, either
NUMBER or STRING, associated with the stack
specified by the appropriate couple statement. An example of a couple statement follows:
COUPLE (SYNXSTK) ;
Reductions match only a certain field within NUMBER stack elements extending from digit one to X
where X will be defined by the implementatiop.. Thus,
the user may declare a wider or multiple dimensioned
stack and gain parallel storage if he so desires. Stacks of
type STRING will have the entire first element of
each stack row· matched by the reductions and consequently the only way to gain parallel storage here is
with multiple dimensioning.
The left two sections of a reduction statement act as
a pattern recognition and generation device for syntax
parsing and bear little resemblance to the rest of CABAL even though reduction control is similar to IFTHEN statements. The third section, however, exhibits
the full range of CABAL as its content is syntactically
defined as a statement sequence, with the exception.
that another reduction statement may not appear unless imbedded within a BEGIN-END pair.
This structure, along with the placement freedom
of reductions allows diverse ways to organize a language
translator. Notably, the two ways most usually desired:
a complete set of productions following one right after
another with their associated semantic routines' also
grouped in one sequential mass disjoint from the
reductions; and alternations of syntax and semantics
statements with each syntactic mechanism containing
or followed by its associated semantic routines.
Design Highlights of CABAL
1325
T. E. Cheatham9 has noted .(p. 65) that-"While
there exist reasonable elegant schemes for 'automatically' doing syntactic analysis (and even much of code
synthesis), the handling of declarations is generally
messy with any but the simplest of languages. For
this reason (among others) it will pr~ve. highly useful
in any general purpose compiling system to have the
ability to do arithmetic and relationals-Le., the
'action language' should contain at least the\rudiments
of a good algebraic language."
Rather than just containing "rudiments," CABAL
has all the power of ALGOL as well as some significant
extensions, notably co-routines, stacks, field and bit
level addressing within storage elements, and the
reduction statement which is not limited to syntax
parsing alone.
Name expressions never contain operators as their
function is to convey pointers. For example, a name
variable N might be assigned the name of a label,
N~NAME(LABELX), and then appear in a subsequent GOTO statement. Name variables may be
used in place of any CABAL name provided they have
been assigned either the name, copy, or form of the
item tlley are representing. Assigning N[X]~A allows
N[X] to be used in place of A as N[X] has a pointer to
A. However, if the value of A is changed then the value
of N[X] has also been changed. To circumvent this,
N[X]~COPY(A) will duplicate A and assign a pointer
of the copy to N[X]. Additionally, [NX]~FORM(A)
will allow N[X] to be referenced as if it had been declared
the same way A had~ The name variable concept is
particularly useful in building up threaded lists or trees.
Expressions and types:
Statements:
Expressions have four types as do data structures.
However, typing in CABAL does not follow the usual
rules. An expression type is determined purely by the
operators appearing in it unless it has only a single
oI>erand, in which case it takes on the operands type.
Thus, a string'variable could be numerically added to a
logic variable and would produce a value of type NUMBER. The main reason for typing variables is so that
information within them may be partially accessed.
For example: . [ ]
is a means to address a portion of the variable. If the
construction was A. [2:4] we would be addressing the
second, third, and fourth digits within element A where
digit is defined according to the type of A. Digit definitions are as follows: NUMBER-decimal digit,
STRING-alphanumeric character, LOGIC-one bit,
NAME-one entire name.
There are four statements specifically supplied for
semantics processing: assignment, conditional, iterative,
and push-pop. The assignment statement is straight
forwar'd:
The unary and binary operators are classified according to the expression type they produce.
< unary numerical operator> :: =
-I + 1~
' ..
::=
>1<1~1~1=I=I=IAlv
::= &
Some of the unfamiliar operators are & : concatenation,
o :mod, E: is a substring of, and ~ : truncation. The
substring operator provides a value of 0 if the left
string is not contained in the right string and a value
corresponding to the digit position of the left string's
first character match in the right string if it is contained.
< expression> :: =
1
1 < logic expression> 1 < string expression>
The replacement operator does not affect type as the
value of the expression is stored in the variable with
no regard to type differences. If the length of the expression value cannot fit in the variable then the replacement is undefined.
The IF-THEN conditional is standard ALGOL and
needs no further explanation. The iterative statement
is as follows:
DO
::= -1+1/1*11' 10iE
::= -,
~
.. WHILE < logic expression>
I FOR
~
< terminal condition>
::= TO BY
I TO
WHILE < logic expression>
1WHILE
Although the syntax has been shortened, the semantics
here are similar to ALGOL for statements.
1326
Fall Joint Computer Conference, 1968
The push-PQP statement is used tQ push and PQP
eleme,nts assQciated with LIFO, FIFO, and RANDOM
linked stQrage.
< push-PQP statement> :: = < stack QperatQr>
1
::=
1V
~
1
~
I < stack QperatQr> V
< grQUp reference> :: = < name>
[ ]
< grQUp definitiQn> :: = < index range list>
< number expressiQn list>
::= 1* , I
< index ,range list> *,
TQ exemplify the range 'Of manipulatiQn this buys
consider the fQllQwing structure:
DECLARE MST (LOGIC, 32, [1: X,1 :Y, 1 :Z],
RANDOM);
ThIs gives us a master symbQI table similar tQ the 'One
which must be declared by the user at a blQck level
sufficiently high tQ encompass all cQde bracket statements. Z is the maximum element number in the list
. and cQrresPQnds tQ the maximum number 'Of identifiers
the users cQmpiler will handle; Y specifies the number
'Of 32 bit stQrage elements needed per identifier;, and X
specifies the number 'Of remembered nested declaratiQns
any 'One identifier may have. By asking fQr RANDOM
linkage 'We can push and PQP any grQUp 'Of elements in
the list at any time. The result 'Of pushing element
[*, *,2] is ~Q have its address nQW by [*,*,3] ; [*,2,2]
gQes tQ [*,3,2] ; and [2,2,2] gQes tQ [3,2,2]. pQpping any
'One of these, thQugh, remQves it entirely frQm the list
and changes grQUp [*, *,3] tQ [*, *,2] andsQ 'On.
Consequently, using this as 'Our master symbQI table
allQws us tQ push and PQP infQrmatiQn cQncerning every
declaratiQn 'Of a given identifier name as well as 'Only
that infQrmatiQn assQciated with its declaratiQn at a
specific block level.
,The master symbQI table (MST) serves as a CQmmunicatiQn link between the semantics prQcessing and
cQde generatiQn. As will be discussed lin the cQde
generatiQn sectiQn, stQrage allQcatiQn and 'Other necessarY MST infQrmatiQn is entered intQ the MST by the
cQde generatQrs. During semantics prQcessing this
infQrmatiQn as well as additiQnal data the semantics
rQutines may stQre in the MST is available fQr use.
Code generation
Co de generation is accQmplished thrQugh the use 'Of
cQde statements and item statements. A cQde statement simply enclQses in cQde brackets CQnstructs which
fQr the mQst part CQmpQse the CABAL language as a
whQle. Item statements are used tQ prQvide parameters
in cQnjunction with the indicated cQde frQm a cQde
statement. Thus, the translatQr writer merely translates his input stream intQ valid CABAL and enclQses
it in cQde brackets.
There are a few restrictiQns and extensiQns which
may appear in cQde brackets. With the exceptiQn 'Of
having tQ put 'Out cQmplete statements, structure is
nQn-existent. DeclaratiQns and statements may be interspersed at will. A declaratiQn in cQde brackets causes
the gene~atQr tQ push the MST at the apprQpriate place
and stQre the necessary infQrmatiQn. Subsequent usage
'Of declared items in statements causes retrieval 'Of MST
data in 'Order tQ prQduce cQde.
The 'Output frQm cQde brackets is a stream 'Of items
which are interpreted by the generatQr intQ cQde. CQde
is prQduced whenever a sufficient amQunt 'Of infQrmatiQn
CQmes through the cQde brackets. Thus, 'One statement
may be executed such as CODE( # 1), prQducing nQ
cQde until the CQnstruct is sufficiently cQmpleted by,
perhaps,
CODE(~#1+
#2).
All names within cQde brackets which must be
identified have syntax = # . This relates
them tQ parameters in the mQst recently executed item
statement. FQr example:
ITEM (SMT[4],SMT[1], # A, # B);
CODE(FOR#1~#4 TO #3 BY #2 DO);
Here we have the parameters in the item statement
implicitly numbered starting with 1 at the left. The cQde
statement designates which parameter it wants by
signifying the number. The # in the item statement is
used tQ indicate that a parameter represents a CQnstant
rather than a declared name.
When the generatQr receives a parameter representing a declared' name, it IQQks in the MST tQ get the
apprQpriate stQrage address and related infQrmatiQn.
When a parameter name has mQre than 'One declaratiQn,
the tQP 'One is always used.
ShQuld it be necessary tQ pass a name parameter tQ
the generatQr whi~h has nQt yet been declared, like a
label name fQr' instance, the CHAIN functiQn is useful.
This functiQn need 'Only be used 'Once per name as it
cQntinues tQ chain all instances 'Of the name until the
ASSIGN ~unctiQn is invQked. ASSIGN is used after
the apprQpriate declaratiQn has been made and retraces
the chained list inserting apprQpriate addresses and
cQmpleting any unfinished coding.
Design Highlights of CABAL
There are times when a compiler written in CABAL
wishes to transfer some of the data collected during
compilation to the compiled program. This is facilitated
quite easily as:
ITEM(RUNNAME,#TABLE);
CODE(#1~#2;);
This transfers the data stored in TABLE, a compiletime data structure, to a run-time data structure of
identical dimension called RUNNAME which has been
previously declared in a CODE statement.
Control can be passed to compiled code by generating a GOTO < label name> NOW j where < label
name> is some pre-declared label in the generated
code. Returning cOI\l:trol to the point following the code
statement which gave up control will happen if execution runs into a pre-generated RETURN NOW.
Execution of HALT by either the compiler written in
CABAL or the translated code produced by the compiler will give contr~l to the operating system.
CONCLUSION
Looking now with an eye for comparing the language
description with the design criteria, there are a number
of points worth mentioning. For applicability to compiling-compilers there are incl~ded co-routines for
natural phase and pass separation, reductions for
syntax parsing, full algebraic power for semantics
processing, structures and operators for string manipulation, system supplied. routines for handling strings
comfortably, a master symbol table easily accessible by
both code generation system routines and user written
semantic routines, and a code generation facility that
couples the easy and nonchalant use of a high level
language with optimal system routines capable of
streamlining the resultant code to a degree determined
by how much time is deemed worthwhile.
Producible translators include interpreters, which
make use of the output facility for compile time data
and code as well as reduction statements; conversational compilers, aided by ease of control flow between
environment, compiler, and generated code; and
multiple language systems using co-routine and reduction stack coupling. Compatibility is maintained with a
dynamic environment through machine independence
and an open ended design ready to accept extensions.
In this respect a macro facility is anticipated and seems
reasonably easy to implement.
Modularity is provided not only by the language
structure and its program and data structures, but also
at a lower level its statement and declaration syntax is
modular to a degree that makes extension trivial.
Flexibility, besides benefitting from points already
1327
mentioned, is further assured by an absolute minimum
of communication linkages and interdependencies within and amOIJ,g the language system subdivisions and the
system environment.
There is full algebraic power as well as the ability to
reference all system variables and even drop down to
an assembly language sequence. Readability and transparent learning is assured from the ALGOL nature as
well as keeping the concepts to a minimum and using'
a high level language for code generation. The syntax
was specially geared for terseness to such an extent that
FOR-STEP-UNTIL-DO was superceded by FOR-TOBY-DO.
Finally, reliability is facilitated through an easily
understood and well-partitioned language system with
no major hidden subdivisions. To the author's knowledge, this is the first high level language to provide
recursive co-routines, a structure well suited for compiler writing. A generalized data structure declaration
providing scalars, arrays, lists, ~tacks, and queues as
well as ope~ators for these structures are conveniently
imbedded in any compiler produced by CABAL. This
last point is in answer to the Feldman-Gries9 statement
(p. 28): "One central question in any TWS [translator
writing system] is the choice of data structures built-in
at both translation and execution time. . . essentially
nothing has been done to provide built-in structure
operators for execution time." The code generation
facility provides the answer to this problem by using
CABAL as an output language, providing storage,
operation, and control transfer through a high level
language.
Optional control over compiler storage efficcy isent
provided in the data structure declaration. The intein
is that the compiler writer tell CABAL as much as he
knows about storage requirements; receiving the most
efficient storage layout for the information he provides.
Code generation also has optional features governing
the efficiency of compiled code. A simple declarative
means allows the compiler writer to request varying
degrees of code optimization; depending on how much
compile time he is willing to sacrifice for shorter run
time.
Until CABAL has been used on a few systems, an
attempt to name its shortcomings would be premature.
One possible disadvantage might be the time taken for
code generation. This, however, will be a function of
the completeness of each CODE statement and consequently will be under some control by the compiler
writer.
Although compiler-compiler techniques are by no
means near to being a closed issue, there is enough
foundation material currently available that a little bit
of polish can produce a palatable system. I think
1328
Fall Joint Computer Conference, 1968
CABAL demonstrates that programming languages
aimed at complex problems not fully formalized or
understood need not wait for absolute insight before
user problems are considered. In fact, making the usage
of such a system as painless as possible will do much
for increasing the number of users and thereby q¢cken
the time when language translation is yesterday's
problem.
Computation Center Carnegie-Mellon University Pittsburgh
Penna 1964
3 J PLASKOW S SCHUMAN
ACKNOWLEDGMENTS
Proc IFIP Congress New York 1965 pp 592-593
5 R A BROOKER D MORRIS J S ROHL
The CABAL design project involved a number of people
over its three years duration and is indebted to each of
them. Jan Fierst, the initial project leader, and Mary
Shaw did much of the initial design. Other contributers
include J ames Eve~ Edward McCreight, David Adams,
and Bernard Lansac. Working papers written during
the design process by these project members are available as computer center reports and serve as evolutionary documentation of the· design effort.
REFERENCES
1 J FELDMAN
D GRIES
Translator writing 8Y8tems
CommACM Vol 11 No 2 Feb 1968pp77-113
2 JAFELDMAN
A formal8emantics for computer oriented language8
The TRANGEN 8Y8tem on the MJ,.60 computer
AFCRIr66-516 July 1966
4 TECHEATHAM
The TGS-II translator-generator 8Y8tem
Compiler-compiler facilities in atlas autocode
cumput J9 1967 pp 350-352
6 RWFLOYD
A descriptive language for 8ymbol manipulation
JACM 8 Oct 1961 pp 579-584
7 AEVANS
An ALGOL 60 compiler, nanual review in automatic
programming
Vol41964 pp 87-124
8 ME CONWAY
Design of a 8eparable tran8mition diagram compiler
Comm ACM July 1963 pp 396-408
9 TECHEATHAM
N ote8 on compiling technique8
Computer Associates Inc Wakefield Massachusetts 1965
Checkout test language:
An interpretive language designed for
aerospace checkout tasks
by GENE S. METSKER
Martin Marietta .Corporation
Denver Colorado
The topic of this paper is the CHECKOUT
TEST LANGUAGE (CTL), which is a new interpretive test-oriented language designed in nearEnglish. form. However, before disc.ussing the language itself, a brief description of the system will
be given so the language/software/hardware relationship can be shown.
The center of the system is two general purpose
eomputers (reference Figure 1). The two central
processor units (CPU's) can operate independent-
FIGURE 1
1329 .
1330 Fall Joint Computer Conference, 1968
ly or in a dual redudant mode during critical operating periods. The two CPU's share 80k of core
memory contained in five 16k banks. The computer word is 32 bits, and memory is addressable
and alterable by byte, halfword, word and doubleword. Numerous peripherals interface with each
CPU. Associated with CPU I are three magnetic
tape units, one 1000 LPM line printer, one card
reader, one card punch, one teletype, one X-Y
plotter, one paper tape reader, and one 24 ~I
BYTE rapid access disc. Associated with- CPU 2
are 2 CRT displays, one magnetic tape unit, one
1000 LPM line printer, one card reader, one teletype and one 24 M BYTE rapid access disc.
Output control functions from the CPU's, located in the control center (reference Figure 2)
are routed through the command I/O, verified for
correctness, and transmitted to the remote equipment over one or more of the three 300kc biphase
transmission links. The in~tructions are received,
checked for correct parity, decoded and routed to
the correct device. Located at the remote installation are three analog stimulus generators, three
bias generators, four programmable A/D converters, a 600 point analog switch matrix, 320 singleinput discrete switches, 96 majority voted discretes, and Data Monitor System (DMS) scanners capable of monitoring on a real-time basis,
3000 discrete inputs.
The analog data are returned from the remote
location to the control center over a single 250kc
biphase trans.mission line. The four A/D output
are multiplexed onto this line. The discrete data
are returned to the control center via four 250kc
biphase transmission lines. Each transmission
line carries a maximum of 750 channels of discrete
data, thereby establishing a scan cycle for up to
3000 channels of 3 milliseconds. The analog data
FIGURE 2
.~-~~~,1
"
~~j-l
_
joo----+---i"1
1
- -I r - -,
~t~'~~i;~
I
'CM '.uTS-U_' '1
_
BLOCK DIAGR
Checkout Test Language
are routed through the analog I/O at the control
center to memory bank C. The CPU then compares the data value against stored limits after
appropriate manipUlation of the data. The DMS
data to the DMS I/O is compared against stored
"success criteria" which is continually updated
as a function of the sequence, events or time. When
the criteria is not satisfied, 'One or both of the
CPU's is notified of the anomaly, and suitable
error seque\lces are initiated.
Additionally, the PCM data is routed to the
PCM I/O from the Ground Instrumentation System (GIE) in the form of two serial data links.
The analog and bi-Ievel PCM data are not used by
CAGE as hold criteria, but all error data will be
printed and are available as backup data to the
analog and discrete system.
Having briefly described the checkout system,
it is relevant to now examine the need for a special purpose test language.
The pattern has become well established that
any entrant into the aerospace ground equipment
field is going to have a computer as an integral
part of the system. The computer may play 'Only
8. passive monitoring role, or it may be fully active
in the control loop, but it will be there.
This is a desirable evaluation in checkout technology. Computers can play a very useful role in
the checkout field due to their ability to analyze,
sort, and report on massive quantities of data in
near real time. If they are also used in the control
loop, computers can take alternate or corrective
action to a dynamically changing situation by selection 'Of the proper alternate path among a
myriad of possibilities, while conventional test
equipment is normally limited to a single preselected "abort" procedure, or worse, reliance on
the human to take proper action.
However, to realize the potential of a computerized checkout system, the combined intelligence
of many experienced engineers and scientists must
be entered into the computer before it is turned
loose in an operational environment. It is the purpose of this paper to examine how this transfer
'Of intelligence takes place, and how steps can be
taken to make this process almost painless for the
human and the computer too!
It is unfortunate but indisputable that most experienced engineers who must define the checkout
and control tasks are not experienced programmers, and most c'Omputer programmers are not
1331
experienced test engineers. A language such as
FORTRAN enables a man to easily master the use
of a computer for general purpose business use
or standard mathematical operations, but do not
tven begin to satisfy the aerospace requirements
which require unique hardware and software
manipulations.
When Martin Marietta's checkout system was
in the c'Onceptual phase, one of the prime areas
of emphasis was in the development of a language
that was near-English in form but which contained all the tools by which the test engineer
could express commands and criteria completely,
simply and unambiguously. Additionally, it was
considered imperative that the format be readily
understandable to all interested observers such as
the customer, the user and the reviewer. Thus, the
checkout TEST LANGUAGE (CTL) was developed. This paper will describe the salient features of this language, and will examine some of
the trade-off's that must be made when designing
such a language.
The basic objective of the CTL is to provide a
vocabulary of terms which can be easily translated
into machine instructions. The vocabulary must
provide the flexibility that the test writer needs
to set up and evaluate his test. However, most
checkout and control systems usually have potentially hazardous conditions that they can cause,
or must react to, and because of this it is often
desirable to place certain hardware or software
.safeguards 'Or restrictions on what the man. is allowed to do. When designing the CTL it was decided to provide a great deal of flexibility in the
basic language structure, and make extensive use
of diagnostics during the off-line translation and
on-line execution of a sequence in order t'O protect
against illegal or hazardous operations. Thus, the
man is not restricted in his use of the language,
but the test article is protected against inadvertent human errors.
A second object of the CTL is to reduce the
writing burden of the test engineer by providing
sequence preparation aids. These aids enable the
writer to abbreviate his tests in such a form that
the translator (the software programs that convert test language statements into machine usable
form, can expand the statements into a fully defined list which can be easily understood and reviewed by all interested parties. Most typical
sequences written in test language undergo about
1332
Fall Joint Computer Conference, 1968
a 20:1 expansion ratio as they are passed through
the translator. Also, each CTL statement requires
about four computer words after translation.
Thus, the total reduction in the physical writing
task from an assembly language program to a CTL
program is about 80: 1. This means that in addition to writing in a near-English form using common everyday verbage, the test writer is required
to specify only 1.25 % as much as he would if he
were writing in machine language.
Before describing the CTL itself, it is relevant
to now summarize the importance of an interpretive language.
1)
2)
3)
4)
5)
6)
7)
Assembly language programmers who do
not understand test techniques and requirements are not involved in generating sequences.
Test engineers .who do understand vehicle
test requirements can prepare the sequences in a near-English format.
The customer and contractor quality control personnel can easily understand and
validate the sequences.
Any addition, deletion or update to any
sequence can be accomplished by an engineer by simply stating the cha.nge in test
language.
Field modifications to translated sequences
are easily accomplished.
The writing burden has been reduced almost a hnudredfold.
On-line use of the CTL enables generation
and execution of tests on-site with near
zero delay.
The CTL consists of 20 basic elements or verbs
and their associated modifiers.
The various test elements may be classified according to their function and how they relate to
the on-line programs. Many of the elements correspond to element subroutines, while others are
provided by the translator to simplify preparation
of test sequences in the Test Language.
The elements which correspond to internal programs may be roughly divided into four classes:
1)
2)
Discrete Signal Observation and Control
APPLY
RESET
CHECK/.DISCRETE
Analog Signal Observation and Control
3)
4)
CONNECT
STIMULATE
MEASURE
CHECK/ANALOG
Test Flow Control
BEGIN
END
TIME
SET
DEFER
CONTINUE
Special
DISPLAY
SAVE
RESTORE
Several "Elements" and translator facilities are
provided as tools for the test engineer. All of these
are provided to eliminate non-productive repetition of recurrent test sequences, and detailed descriptions of frequently used groups of data.
Features designed to facilitate test sequence
preparation include:
1)
2)
3)
4)
SEQUENCE
R}~PEAT
REP/Test
SYSTEM/TEST
The first of these, SEQUENCE, is actually an
element used in on-line control. It facilitates the
use of established library test sequences within
any other sequence. The other three are facilities
of the translator; i.e., the translator inserts the
repetitious data or elements into the control file
using the REP/TEST, REPEAT, OR SYSTEM/
TEST elements as a mode.
Before further elaboration of the elements
themselves, it is useful at this time to demonstrate
the organizational structure of the test sequences.
The highest level of organization in the test
language is the test sequence. The test sequence
1S composed of a logical grouping of lower level
blocks, which as a "whole, accomplish the specified
task. The terms describing the levels of organization are unique to this language (reference Figures 3 and 4).
ELEMENT-The test element is the basic building block of the test language. Each element
serves a specific purpose such as commanding
a relay closure, establishing a stimUlus, ete.
Each element has a set of modifiers asso-
Checkout Test Language
SEQUENCE ST RUe T u R E
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An efficient system for user extendible languages.
by MALCOLM C. NEWEY
University oj Colorado
Boulder, Colorado
INTRODUCTION
The recent survey by Feldman and Gries on
Translator Writing Systems 1 devQtes space to
discussion Q.f "extendible" ,cQmpilers but fails to
explain fully the motivatiQn. The reaSQns for an
extendible high level language (and hence fo·r
an extendible compiler) are as fQllQws.
i ) It is nQt feasible to foresee all the prQgramming techniques which have not been developed
at the time of language definitiQn, and which
might deserve a place in a language.
ii) It is nQt p,ractical to incQrporate all the
data structures, operations and statement forms
currently known into Qne coloss,al language since
this language will be barely teachable, and implementation may be uneconQmical or maybe impossible.
Extendible cQmpilers have, of course, not been
available and it has been shrugged off as a fact
Qf life that most programmers constantly come
acrQSS problems to' which the language available
is really not suited. The normal "solutions" of
this difficulty are bOth unattractive. The first way
out is to abandon the general purpose language
for assembly code or change to some special purpose language (which may require a compiler
being written for it). This line of attack has
given rise to a multitude of special purpose languages such as string processors, list prQcessors,
etc. The Qther way Qut Oof the problem is to resign Qneself to tediQus, inefficient, complicated
cQde, and is illustrated by the way many ALGOL
60 programmers incQrpQrated complex variables
into their prOograms.
i) represent each complex quantity by a 2
element array.
ii) Qperations between complex quantities are
performed by procedures and sO' z: = (u
v)*
(u - v) / (u * v) is computed as follows:-
+
add complex (a, U, v) ;
subtract complex (b, u, v) ;
multiply cQmplex (c, a, b) ;
divide complex (a, c, u) ;
divide complex (z, a, v) ;
This awkward dilemma can be aVQided com. pletely if we have a language with very strong
basjc structure (such as ALGOL) and a facility
fQr extension by the user Qf the language. The
problem with this scheme is that an extendible
cQmpiler must be devised. This is a problem of
autQmating something that compiler writers are
Qld hands at; that is, amending the cQmpiler to
.recOognize extensiQns to the base language.
There are twOo semi-automatic schemes for extendible cQmpilers that deserve a mention:
i) Syntax Directed Compiler Approach
The Syntax Directed Compiler 2 is a compiling system accepting first the translation rules
Qf a language and then a SQurce program in that
language, to produce a target program according to' the rules supplied. The system has great
merit where researchers are experimenting with
variQus SQurce languages. The system eQuId be
made to process an extended SQurce language by
altering the translation rules appropri.ately~
ii) The Compiler-Compiler Approach
This genus of translator writing system
(usually associated with Brooker, Morris, et aVS)
accepts a definitiQn of a phrase structure language including the meaning of each of the
phrases (in terms of the target language) and
prQduces a compiler. As with the Syntax Directed
cQmpiler the description of the source langua.ge
can be altered tOo accommodate the extended language.
1339
1340
Fall Joint Computer Conference, 1968
This paper describes an approach to this subject which is claimed superior to each of these
possible attacks and also superior to the approaches described .by Cheatham,S. Galler, Perlis.4
It must also be noted that although ALGOL
60 is used as a basis for discus,sion (as did Galler
and PerIis, 4 the notions can be extended to extendible compilers for other high level, powerful,
general purpose languages such as ALGOL 68
and PL/l. I ts use is justified by the fact that
ALGOL 60 is more familiar.
Nature of useful extensions
It must be realized that if one has an automatic
means of extending a compiler then there is precisely the same problem (as encountered with
languages such as ALGOL) that led to the need
for extendible languages. That is, it is probably
not possible to be simple to learn and operate,
readily implementable and completely general.
This difficulty is offset, as will be indicated in this
section, by the fact that there are a small number
of discrete areas which contain most extensions.
The difficulty is also offset by the fact that there
are often many ways to extend a language but
only certain of these can be said to' be in ''harmony" with the language, and it appears that
these harmonious extensions are the most powerful and most easily describable. To illustrate this
last point, consider a typical example of a feature to be added to ALGOL: string proces,sing as
used in SNOBOL. 6
1) It i.s quite likely that someone wanting
both string processing and arithmetic power
CQuld take the main SNOBOL statement (which
is very powe,rful) and incorporate it in ALGOL.
This would be syntactically recognizable providedeach such statement was flagged by some
symbol such as asterisk.
2) Alternatively one CQuld revise the type
string or ALGOL 60, add a concatenation operator, tie and introduce a statement of a form such
as
search < string > for < string exprn > :=
< str exprn> else < Roman>
Comparing these two alternatives we note the
fQllowing points in favor of the second which is,
of course, in harmony with ALGOL 60.
i) Because string is added in the second case
with the same status as real or Boolean, both
string functions and strings as procedure parameters are po,s,sible.
ii) In the first case there will be confusion and
contradiction of labelling conventions.
iii) Because the second implies string arrays,
indirect addressing of strings is made simpler.
iv) Implementation of the first scheme is
tantamount to including most of a SNOBOL compiler inside an ALGOL 60 compiler which is of
course nasty for implementation.
The above example does emphasize that some
methods of including a concept into ALGOL are
in harmony and ·some are not. Furthermore, it
illustrates that harmonious extensions make use
of and work in with the various concepts of
ALGOL that are well founded (the concepts of
type, statement, label, variable, etc.).
It is with this principle in mind that the following basic methods of extending ALGOL-like
languages are proposed.
Provision for additional data types
This was the technique that was used in the
above example for incorporation of string
manipulation and which made a very attractive
extension. In fact it is probably the most powerful device possible since it opens large numbers
of non-numeric fields to the scope of Algorithmic
languages in a very simple manner. An example
of the type complex was mentioned in the introduction and it may readily be seen that introduction of a type ,complex with the same status as
real, integer, and Boolean is the only satisfactory
way of introducing the concept of complex
arithmetic.
A flood of other extensions to' ALGOL 60 come
to mind by means of this device of providing
additional types. It is the author's opinion that
the bulk Qf the shortcomings of ALGOL 60 that
people feel at various times could be removed
if they could define additional types. The following examples illustrate the wide application for
this technique.
i) The type double real would enable double
precision hardware, presently available on most
curl'ent computers, to be utilized by a programmer,
ii) the type half real would sometimes be· useful when space is at a premium rather than
accuracy.
iii) the type polynomial WQuld make polynomial
manipulation programs (Hamblin, 7 Collins 8 etc.)
quite redund.ant since the inclusion of the routines
Efficient System for User Extendible Languages
into the framework of ALGOL allows the more
comfortable programming speech of the more
sophisticated language.
iv) The types note or chord, etc., could be a
great boon to the researcher in music by making
music text manipulation available in the ALGOL
framework.
The implications of additional types
The extensibility of ALGOL-like languages in
the direction indicated in the previous section is
obviously very powerful but in order that its
full value may be realized the following additional types of extension must accompany any
provision of additional types.
i) Additional significance for existing operators. If the concept of subtraction, for example, is
applicable to. the extra data type then the sigof the operato.r "minus" must be defined fo.r operatio.n on quantities of the new
type.
ii) Additional Transfer Functions
Conside'r the case where the extra type is
complex. Just as it is necessary for an inbuilt rule
to be available for conversio.n of any integer
quantity to the equivalent real quantity, sO' it is
necessary that the transformation fro.m real to
complex be defined. The combination of these two
transfer functions shO'uld automatically, then, be
available for conversion from int~ger to' complex,
There are actually twO' classes of transfer functions which I shall label "generalizing" and "degeneralizing." It is readily seen that real may
be .considered a more. general type than integer
since each integer can be transfGrmed to a real
quantity without loss of information but most
real quantities have nO' inte,ger counterpart. Hence
it is apprO'priate that the transfer intege'r ~ real
is called "generalizing" and the transfer real ~
integer is termed "degeneralizing."
It is o.bvio.US that "generalizing" transfer functio.llS are essential fo.r most new types. Wirth and
Hoare 9 express clearly the major argument for
using operators and functio.ns instead of degeneraIizing transfer functions.
" ... , and he (the programmer) is therebyencouraged to select the alternative which corresponds to his real requirements, rather than
rely on a built-in "default" conversio.n about
which he may have only vague or mistaken ideas."
The opposing po·int o.f view is that such functions and operators can clutter up a pro.gram.
I don't propose to add anything to this debate
nificanc~
1:l41
and so will just proceed anticipating either.
Therefore we should allo.w extendibility in the
directio.n of both generalizing and degeneralizing
transfer functions.
iii) Additional Operators
It is readily seen that if entirely new data
types were introduced then new ways of co.mbining quantities o.f tho.se types could also be
required. For instance if the new type were complex then monadic operators ip and rp suggest
themselves fo.r extracting real and imaginary
parts of a complex quantity. Similarly, if the new
data type were polynomial then a diadic o.perator
deriv would be useful for taking the derivative
of a polynomial with respect to. some variable.
iv) Additional Forms of Constant
For every type in a language there must be
some fo.rmat, for a primary o.f an expressio.n,
which can be used to specify constants of that
type. The types Gf ALGOL 60 include real and
Boolean and the corresponding constant forms are
numeric co.nstants such as 5.2, 123.4 and logical
constants true and false.
Provision for additional statements
This is another very powerful way o.f grafting
Gnto the framework o.f any general purpo.se language additional special purpose features. Because harmo.nious extensions are ones which
make the most of existing parts of the co.mpiler,
it is reasonable to. specify that the co.mponents of
the statement are either basic symbols or the
vario.us important syntactic units already found
in the l_anguage. These are the co.mponents of
existing statements and i~clud~ < statement> ,
< variable> , < Boolean expression> , < array> ,
< label>. The deli meters Wo.uld be chosen from
the standard set of the language o.r manufactured
with so.me mnemonic significance.. The fGllowing
example of a parallel processing statement ill ustrates that extra statement forms can be the o.nly
convenient solutio.n for some tasks. The construction "do .< statement> also < statement>
• . . also < statement>"; is almost essential fo.r
making use of parallel p:ro.c.essing hardware via
ALGOL 60.
A language for extensions to ALGOL
The motivation for a
compiler eJq>ansion
1342
Fall Joint Computer Conference, 1968
scheme a:nd the directions in which extensibility
is required have now been expounded. The extension scheme described in this paper consists
of two programs. The main one is the skeleton
of a compiler without information about types,
operators, etc. The second part of the system is
a program which will accept as input the information necessary to describe the extensions
desired to the language and use this information
to pad out the s:keleton compiler to accept and
compile any programs written in the new extended language. The information that the extender program requires can be considered to be
a program in the language LACE (Language for
ALGOL Compiler Extension). A LACE program
will be a sequence of statements-each one being
a specification of some new addition to ALGOL.
There will, of course, be statements associated
with. each of the directions for extension that
were described in PART II.
The following ten LACE statement form·s are
proposed to allow descriptions of extensions to
be specified.
TYPE
CONSTANT FORM
MONADIC OPERATOR SIGNIFICANCE
DIADIC OPERATOR SIGNIFICANCE
GENERALISING TRANSFER FUNCTION
DEGENERALISING TRANSFER FUNCTION
OPERATOR PRIORITY
STATEMENT FORM
BASIC SYMBOL
CONTROL ROUTINE
T
CF
MOS
DOS
GTF
DTF
OP
SF
BS
CR
Each of these statements or functions require
parameters and so a convenient form for each
statement is its na.me (either full name or abbreviated) followed by the parameters required.
These parameters will be separated by commas.
A description of the parameters required follows.
i) TYPE ,
To add a new type to ALGOL, a name, which
is a new basic symbol, must be specified so it can
be used in declarations, specification parts etc.
The parameter 'length' is required to specify the
"amount of memory space that is required to contain the value of any quantity of that type. This
will normally be a number of bits required but
for certain types of data, such as polynomial, a
variable length field is required for values and
so instead of an integer another symbol such as
'V' (for variable length) would be used.
ii) GTF and DTF , ,
The parameter 'CODE' is the body of code that
is required to transform quantities of the initial
type to quantities of the final type. The body of
code must be surrounded by appropriate symbols.
We will use "and".
iii) MOS , , ,
and
DOS , , , ,
In the statements to define new operato·rs T1
and T2 are the names of the types of the arguments of the operator. TR is the name of the
type of the result of the operation and the parameter 'CODE' is the body of code necessary to
perform the operation.
iv) Operator priority < operator>, < priority value>
The priority value for an entirely new operator
would be obtained by referring to a list of priorities for use with the' system. The compiler requires an ordering of priorities for all operators.
< type>, < syntax>,
Each constant form for a particular type in the
language will have some syntax associated with
it. The form of syntax strings in LACE is discussed later. The semantics required must be target code that will generate a constant of the
appropriate, value for use by the program.
v) Constant Form
vi) Basic Symbol ,
This statement can be used when a particular
value is desired for new basic symbols in the
language. It is also useful where equivalent symbols are desired, as is the case with some versions
of ALGOL-the underlined words can be in several languages.
vii) Statement Form < syntax>, < semantics.>
Refer to the later section on syntax and semantics strings.
viii) Control Routines
This statement is to allow the specification of
a routine that will be available at run-time of an
ALGOL program.
Efficient System for User Extendible Languages
The strings that represent syntax
To represent the syntax of statements ·and constants we use an extension of Backus Normal
Form in which the following nine symbols are reserved as meta-symbols.
<
>
for surrounding syntactic units.
for use as a choice operator.
for denoting a sequence of zero or
more repetitions of the enclosed
string.
for bracketing a series of choices
together.
"
for delimiting the whole string.
These characters will not be available on all
computing equipment but for any given system
suitable replacements can be made. The extensions to BNF are minor and should be readily understood with the aid of an example. The syntax
string for the conditional statement of ALGOL
60 follows
"if < Boolean expression > then < uncondi tional
statement> [else I "
It has previously been mentioned that the
syntax string is composed of the syntactic units
of ALGOL and basic symbols, either new or old.
This is, of course, an oversimplification. Firstly,
there are many syntactic units in the ALGOL 60
Report 14 that are included merely as steps in the
.development of the syntax; terms such as 'Boolean secondary' or 'compound tail' are units we
need not consider useful in· this scheme. Secondly, the grammar should be unambiguous and all
developments ~ of the syntax string should be
recognisable in a left to right scan; this means
that such syntax strings as
abc [ < variable>
I ];
are made illegal because it is both ambiguous for abc alpha; and involves backup for
abc be~ [1+mxn]+2;
Thirdly its;hould never be the ease that two
syntactic units can be run together, either directly ,or indirectly, to remove furthe'r difficulties, or
even ambiguities., for the compiler. Hence it is
not allowed to write a syntax string
1343
pqr xyz or the string
pqr [lmnl ] xyz
The strings that represent semantics
For the LACE statements for defining new
forms of statements in ALGOL and new forms
of constant, there was a parameter for denoting
the· syntax and a parameter for denoting the
semantics. This pair of parameters forms a translation rule just as in the Syntax Directed Compiler or the Compiler-Compiler. Just as the nine
symbols
"" [] I
<
>
were reserved for use as meta-symbols in syntax
strings, so they are reserved here. Of course,
there is no ·syntax units in the semantics string
so the symbols
and
are used in constructing
semantic units. The symbol * is also reserved for
this purpose. It should be clear that the semantics
string will have an identical structuring of the
metasymbols "
"
.[
]
I
{l
to the corresponding' s~tax string. Apart from
the metasymbols the semantics string is made up
of a sequence of semantic units. There are 8
types of semantic units as follows:i) A semantic unit may be any symbol of the
target language. Special conventions will have to
he made for representing symbols which are reserved as metasymbols.
ii) A semantic unit may be a pointer to one
of the syntactic units in the syntax string and
has the form ,forexample, <6> or <1.?>
The syntactic unit to which it refers is that one
with ordinal number equal to the quoted integer.
The target code that this initiates is the code
normally associated with the syntactic unit. This
code is well defined for such units as > statement> , < expres,sion > but for others like
< label> would be empty, and so a pointer to
< label> would be useless.
iii) A semantic unit may also be a call of a
system function designator which will have certain parameter requirements. A call on a function
has the following form.
*function name «parameter-list> )
The' parameters w~ich form the list will normally
be pointers, symbols or integers. There will be
1344
Fall Joint Computer Conference, 1968
functions for all the attributes that the various
syntactic units have and so an example of a
function is
*fetch ·indirect(XR1)
{*load address (XR2, <4»
*fetch indirect (XR2)
*ADDRESS «2» which gives as a result the
address of synta~tic unit number 2 in the syntax
string which may be < variable> or < label> .
*store indirect (XR1)
CPYREG XR1,XR2}
*load address (XR2, < 6> )
The effectiveness of the system will, of course,
depend to a great extent on a suitable set of
functions. However, experience derived from an
actual implementation would affect the choice so
much that no more than a few examples are included in this paper.
A simple illustration of the correspondence between 'the syntax strings and the semantics
strings is now presented in such a ay as to
demonstrate an instance of the us fulness of'
hat the time
LACE. Many programmers reali
spent in duplicate address calculation in the following types of statement is wasted but there is
no way out in' current ALGOL.
xyz [i, j, k, I]
: xyz[i, j, k, 1]
+ 1;
With a compiler extension scheme available the
frustrated programmer could write a more efficient and more suggestively worded
step xyz [i, j, k, I] by 1
The following text would be a suitable LACE
definition.
NSF ("step < variable> by < expression >. ",
"*load address (XR1, <2»
*fetch indirect (XR1) <4> *apply diad(
+,
*type. «2», *type( <4»)
*store indirect (XR1) " )
where XRl may be an index register.
A second and more complex example is nO'w given
which is the definitiO'n of a statement to permute the
contents of any number of variables.
NSF {"rotate
{ } ",
"*load address (XR1, <2»
*fetch indirec(XR2)
*store indirect , (XR1)
*store indirect(XR2)")
In the above example the string CPYREG is an
instance of the object code output required. In
both examples some notional stack is assumed.
Implementation
This part is concerned with the design of an
ALGOL compiler in such a way that it will be
extendible; obviously special considerations are
required in formulating its structure. ALGOL, in
particular, is chosen because of the difficulty of
talking in the abstract· about translation techniques. The schemes are modifications of well
known ones and consequently much familiar material is presented, but only in the interest of a
clear description.
Only two areas' of the system will be discussed;
these are the O'nes that present most of the
challenge. These areas are expression analysis/
compilation and statement analysis/compilation.
Other areas affected are the basic symbol input
routine, simple variable declarations, arra.y
declarations and procedure specification parts.
It shO'uld be noted that the following are
demonstrations that the problems that arise in
implementation are soluble. It may be that the
techniques proposed are not' immediately applicable to certain languages which are not
ALGOL-like or nO't immediately compatible
with certain optimisation requirements for the
compiler. The propo-sals should, in any case, suggest the m-ethod of revision for alternate techniques.
Expression analysis rO'Utine
The technique that· seems most convenient is
the operatO'r priority technique for translation to
Reverse Polish notation. E,arly references to the
Efficient System for User Extendible Languages
method are DIJKSTRA,to HAMBLIN 11 and
HIGMAN 12 (all appeared in 1962).
The technique is normally described in terms
of an input string (in source code) and an output string (in target code). At the start of an
expression a left parenthesis is put on the opera~
tor stack to protect the contents of a previous
recursion and if the first symbol is "if" then appropriate action is taken; otherwise there is a
normal simple expression. All primaries encountered during the left to right scan generate
output code immediately (including sub-expressions) but operators may be stacked according
to the following 'rules.
i) Operators which can be either, monadic or
diadic are treated as diadic if they follow a
primary, else they are treated as monadic.
ii) Operators which are monadic are added to
the operator stack, provided there is not an operator of higher priority on the stack. This condition would correspond to a failure.
iii) Operators which are diadic must occur immediately after a primary or else an error exists.
Also a monadic operator or another primary must
follow. Diadic operators first displace each operator on top of the stack which is of equal or
higher priority. It is then added to the stack
with the current value of the variable, BETA,
which indicates the type of the left argument of
the operator.
iv) An expression terminator displaces all operators until it finds a left parenthesis which it
removes. It then causes exit from this level of
the expression routine indicating that it found
an expression of type given by the· value of
BETA.
v) A monadic operator is displaced as fo1 ..
lows:-The,type of quantity to which the operator
'is to' be applied is given by the variable BETA.
The appropriate operator significance for that
operator and the type of quantity is then added
to the output. The ,type that is given as the type
of the result of the operation is placed in BETA
and the operator removed from the operator
stack.
vi) A diadic operator is displaced as follows : The type of the 1st argument of the operation is
stored with the operator and the value of BETA
gives the type of the second argument. The operator significance appropriate to that operator
and that pair of types is selected and added to
the output. This may be one of the operator significances specified by the programmer or may be
one which was specified, but compounded with
1345
one or more generalising transfer functions.
The expression analysis routine described
above is one pass, left-to-right scan and does
not produce optimum code. The ideas could, however, be extended to other expression analysis
techniques.
l t has been noted earlier that there are transfer functions which are defined for the extended
language both explictly and implictly. If a new
data type abed is defined and a generalising transfer function from type real to type abed is also
defined, then a new generalising function is implicitly defined frO'm type integer to' type abcd.
It is clear that it is more efficient for the extender program, after having absorbed all the
transfer functions which are explicitly defined, to
generate, as well, all the other transfer functions
that are implicitly defined. New generalising
transfer functions are generated as minimum
cO'mbinations of explicit generalising transfer
functiO'ns. Implicit degeneralising transfer functions are generated as minimum combinatiO'ns of
explicit degeneralising functiO'ns or as the combination of a generalising transfer function
(which need not be explictly defined) and a
string of degeneralising transfe'r functions.
It is also profitable for the extender program
to' generate, and form as a list in the compiler, all
operator significances which are implicit. An implicit operator significance is formed when a
generalising transfer function is applied to convert the quantity to an appropriate type for some
operator significance, which is given for the operator, to act on.
Statement analysis
The extender program has the task of constructing, from the syntax and semantics strings
which are supplied, that part of the compiler
which will analyse the statements of the extended-ALGOL programs. We shall talk about
this process assuming that the compiler is constructed along the lines commonly known as
syntax routine method of compiling.18 This means
that wherever a' syntactic unit appears in a
syntax string this transforms into compiler code
as a call on that, syntax routine. The syntactic
routine will scan the code till it exhausts that
syntactic unit.
A basic symbol which appears in a syntax string
will be transformed to a test or a check in the compiler code generated. Because the choice operator, I , separates alternatives, a series of tests
1346
Fall Joint Computer Conference, 1968
must be made with one branch made to a section
of code for each alternative. At the end of each
of the alternatives, there must be jumps to a common point.
The transformation of a pair of braces f
}
which denotes optional repetition, is a loop in the
compiler code. The contents of the braces, when
transformed, form the body of the loop. The decision to jump out of the loop is made at the
start with a test to see whether the next symbol
to be fetched from the input is appropriate to
continuing or discontinuing the loop.
The above is a description of how the syntax
string imparts structure, tests and syntax routine
calls to the code generated for the compiler. The
, semantics string, of course, has the same structure and so where the tests and routine calls are
made for some particular element of the syntax
string, the corresponding element of the semantics string is designated for output.
CONGLU8IONS
This paper has been an introduction to a solution ef the problem of general purpose languages being inflexible; a two ,segment system
which allows the user to introduce new data
types and new data manipulations. The scheme
is intended for high-level- general purpo'se languages to make them more general but was illustrated with ALGOL. A generalisation to other
appropriate languages should not be difficult.
There are several questions that should be
asked of this comp-iler extension scheme. The first
ef these is whether the direction of extra data
types and extra operations en these types is the
right way to previde fer extensions. The second
question is whether it is ambitious enough (i.e.,
powerful enough), and the third is whether it is
feasible (i.e., not tee ambitious). The author's
opinion on these questions is that they should all
be affirmed. However, the areas are subjective
since there has been no implementation of such
a system yet, but the contents of the paper explain and give weight to the point of view.
A fourth and less subjective question asks
hew it compares with rival schemes. We compare
it to four other systems which can be used to
provide compilation of extended languages.
i) Syntax Directed Compiler (SDC).
The use of a SDC for compiling an ALGOLlike language requires a standard primary 'program' which de'fines the whole syntax and semantics of the language, rigorously and cempletely.
To make use ef SDC fer user extensions, the
primary pregram would require suitable altera.tien. This would demand knowledge ef the target
code (as does the scheme here presented) but
alse demands quite intimate knowledge ef the
primary program-h9th its langua,ge and structure., This is probably significantly easier than
amending a hand coded compiler but suffers
from the same disadvantages.
ii) Compiler-Computer (CC)
This is also a semi-automatic method ef extending a compiler and suffers the same dis'advantages as SDC.
iii) Cheatham's approach~
This is an attempt to previde macro facUities
for high level languages, and, in the terms ef
this paper, only in'the area ef new statement
forms. That is, no direct attack is made on the
area of provision of extra data types, which is
crucial. It is readily admitted that macro facilities are very useful and' a powerful macro preprocessor such as LIMP (WAITE 15) can help
to remove some of the problems of tedious programming speech. However, it is also true that
if it is impossible to write code fo,r some given
task (in some language) that will be compiled
both efficiently and compactly, then mac'ro processing is not going to help. It is contended, therefore, that the present paper has a better answer
as regards efficiency.
iv) ALGOL C-Galler, Perlis I.
As with the above scheme (Cheatham), considerable importance is given to provi'sion of
macro facilities in ALGOL-like languages. For
the same reasons it is potentially less efficient
than the approach of extended compiler generation. Recall it was mentioned in the intreductory
section, that the case of complex numbers is a
classic example of tedious and inefficient ALGOL;
yet Galler andPerlis still have complex numbers
implemented as 2 element arrays. On the other
hand their approach means that extensions are
not machine dependent.
A second disadvantage i8 that it stops short
of providing new statement forms. A last and
quite significant disadvantage is that all the
definitional facilities are in the compiler and
therefore the same work is done ever and over
again, wasting time and compiler space.
REFERENGEiS
1 J FELDMAN D GRIES
Efficient System for User Extendible Languages
Tran8lator writing systemIJ
Comm A C M 11 Feb 1968 pp 77-113
2 E T.IRONS
The structure and use of the syntax directed compiler
Annual Review in Automatic Programming Vol 3 1963 pp
207-227
3 T CHEATHAM
The introduction of definitional facilities into higher level programming languages
Proc AFIPS 1966 Vol 29 pp 623-637
4 B GALLER A J PERLIS
A proposal for definitions in ALGOL
Comm A C M 10 April 1967 pp 204-219
5 R A BROOKER et al .
The compiler-compiler
Annual review in Automatic Programming Vol 3 1963 p 229
6 D J FARBER et al
SNOBOL A string manipulation language
J A C M 11 Jan 1964 p 21
7 CLHAMBLIN
A n algorithm for polynomial operations
Computer Journal 10 Aug 1967
8 GECOLLINS
PM A systemJor polynomial manipulation
Comm A C M 9 Aug 1966 p 578
9 NWIRTH CARHOARE
A contribution to the development of ALGOL
Comm A C M 9 June 1966 pp 413-432
10 E W DIJKSTRA
Making a translator for ALGOL 60
Annual Revi~w in Automatic Programming Vol 3 1963
11 C L HAMBLIN
Translation to and from Polish notation
Computer Journal 5 Nov 1962 p 210
12 BHIGMAN
Towards an ALGOL translator
Annual Review in Automatic Programming Vol 3 1963
13 B RANDELL D J RUSSELL
ALGOL 60 implementation
Academic Press Inc LONDON 1964
l4 PNAUR
Revised report on the algorithmic language ALGOL 60
Comm A C M 6 Jan 1963 pp 1-17
15 WMWAI',fE
A language independent macro processor
Comm ACM 10 July 1967 p 443
1347
Program composition and editing with an on-line
display
by HARVEY BRATMAN, HIRA...M: G. MARTIN,
and ELLEN CLARK PERSTEIN
System Development Corporation
Santa Monica, California
INTRODUCTION
An Interactive Programming Support System (IPSS)
has been under development at System Development
Corporation since 1965. * The purpose of the system is
to permit all of the progr~mming processes-composition (in a procedure-oriented language), editing, execution' testing, and documentation-to be carried out as
parts of a single, coordinateq activity centered around
an interactive compiler. IPSS attempts to unify techniques that are usually embodied in separate functional
programs, so that the programmer need not know which
particular program is performing a specific task. The
system is intended for a time-sharing environment,
with user interaction via a small tabular display or
typewriter-like terminal.
In the development of IPSS, emphasis has been
placed on the functions of program composition and
editing, particularly via an interactive display. The current object of this work has been to investigate the use
of a small tabular display by a professional programmer
to compose and edit programs and to retrieve dynamic
information about the state of his program. This paper
reports the results of three aspects of that work.
• It describes how the display is used, how the display compares with a typewriter-like terminal,
and how the user interacts with the display to
accomplish the tasks of program composition and
editing.
• It describes the advantages of doing syntactic
analysis concurrently with program composition
and editing, -how program information is obtained,
and how IPSS does the analysis and editing.
• It describes the software interface between IPSS
*This work has been supported in part by the Advanced Research Projects Agency of the Department of Defense.
134£
and the display hardware, how IPSS can be used
with various displays, and what the characteristics of.an "ideal" display are.
Background
The Interactive Programming _ Support System
operates under SDC's new time-sharing system (known
as ADEPT-50) on an IBM 360 l\t{odel 50 computer.
Since one of the maj or purposes of ADEPT-50 is to support large-scale program development, testing, and debugging, IPSS is considered to be an essential element of
the ADEPT -50 system.
A small, tabular display (rather than a typewriterlike terminal) was chosen as the primary interactive device in this work for the following reasons. First, we are
looking forward to the near future when relatively inexpensive display devices are expected to be available.
These devices could be installed directly in the programmer's office or work area, and could be connected to a
central time-sharing system. Second, a display provides
faster response by presenting many lines of output in the
same time a hardcopy device requires to print one line.
'Thus we hope to eliminate the need for the programmer
to search through numerous pages of program listings,
,hoping to find some single piece of information, but not
knowing if the listing really corresponds to the current
state of his program. Instead, he will be able to display
all the information he wishes to see, and will be assured
that it reflects the true state of his program at that instant. Third, the display scope minimizes the amount of
typing the programmer Inust do to compose and edit
his program. The programmer is able to use the "replace-character" feature of a display scope to modify
parts of his program, rather than having to retype
whole lines. Previous systems (such as the Q.E.D.
Time-Sharing Editor developed at the University of
1350
Fall Joint Computer Conference, 1968
California, Berkeley,l or the editing routines used under
the M.LT. Compatible Time-Sharing System2) show
the ingenuity and complexity required to perform similar functions with a typewriter terminal.
The display device used in this project is an IBM
2250. This device is more powerful and expensive than
necessary for this work, but we can use it to simulate
the characteristics of displays such as the Sanders 720,
Computer Communications Inc. 300 TV display, or'
RCA video data terminal-which are typical of the devices we are considering.
The current system is limited to the use of the
JOVIAL programming language (since this is the most
readily available language at SDC). The operational
principles derived in this work, however, are applicable
to other languages such as FORTRAN or PL/1. The
user can choose either the 2250 display or an IBM
2741, a typewriter-like device, as his interactive
medium. However, some IPSS functions such as automatic program display and minimization of programmer typing can be done only on a display scope; other
functions may be too time consuming- to be used often
on the IBM 2741. The current capabilities of IPSS allow the user to compose and edit his program interactively. All program statements are checked for syntactic correctness as they are input, and correct statements are automatically displayed to show the current
status of program composition. The programmer is informed of errors in syntax, which he can correct immediately. Syntactic checking combined with editing
insures that the edited program is free from the more
common programming errors. Thus, the programmer
need not be afraid of unpleasant surprises when his program is compiled. The programmer can display parts of
his program, he can obtain current "where set" and
"where used" information about variables in his program, and he can obtain all the references to any program
label.
roughly defined as a physical segment of the display surface, set aside for some specific function. Block 1 is the
area where IPSS requests user actions. IPSS signals the
user when it is ready for input by displaying two question marks (1?) in position 1,0 (block 1, field 0) and by
placing a cursor in position 2,0. A descriptive message is
written in position 1,1. Block 2 is the work area where
the user responds to IPSS jnput requests. Since the cursor has been placed in position 2,0, typing on the keyboard causes input to appear there. The user is restricted by IPSS from typing into block 3. Block 3 is
the area where IPSS displays information requested by
the user or automatically generated in response to some
user action. Every line but the first contains one field of
72 characters. The first line is divided into two fields of
2 and 72 characters each. Block 1 consists of 1 line,
block 2 consists of 5 lines, and block 3 consists of 47
lines. The size of the blocks can be varled for experimental purposes.
The IBM 2250 has been available to us only since
February 1968. (Prior to that time, we used the IBM
2741 to test many IPSS functions.) Hence our ideas on
how to use the display are still evolving as the result of
experience. We have decided on some general principles
to guide us in the use of block 2, the user work area, and
block 3, the program's output area. To meet the stated
goals of IPSS, the minimum sizes for blocks 2 and 3 are
2 and 20 lines, respectively. Hence any practical display
scope should hold about 25 lines of at least 50 characters
each.
We wish to minimize the amount of typing the user
must do. As shown below, IPSS will, in the case of error
correction and editing, regenerate program statements
on block 2 so that the user can modify them as necessary, and does not have to retype entire statements. The
user can add new displays to block 3 without destroying
the display already there. He can change a current dis72 Characters
2
UIe of the dilplay
The display is used to convey information both from
IPSS to the user, and to IPS.S from the user. IPSS
either requests input and waits for the user to respond,
or it outputs information in response to user actions and
again waits for the next user response. User responses
may be answers to specific questions from IPSS, program statements, or requests for IPSS action.
The face of the display has been organized into three
logical "blocks" to facilitate these uses (see Figure 1).
The number pair shown in Figure 1 represents block and
field numbers; e.g., 3,0 represents block 2, field 0. Each
line is composed of one field except for block 1,
where the line is divided into two fields. A "block" is
1,0
1,1
2,0
2,1
Block 1 (1 line)
2,2
Block 2 (5 lines)
2,3
2,4
3,0
3,1
3,2
Block 3 (47 lines)
FIGURE I-Display organizaiion
Program Composition and Editina- with On-Line Display
play to make room for a new display, and thus make
effective use of the display as a substitute for leafing
through program listings.
1351
?? COMPOSE MODE
LOOP. IF XX LS 0$ GOYO OVER$
XX=XX+l$
GOTO
LOOP$
Display interaction in program composdion
OVER.
An example of program composition is shown to
describe the use of the display and also to point out
some advantages of a display over a typewriter-like terminaL The example corresponds to the program shown
in Figure 2. Figure 3 shows how the display is used in
program composition. Block 3 on the display surface
contains an automatic display of the program thus far
composed. Statement numbers corresponding to the
last statement on each line have been added. The pro-
INITIAL
STOP$
GOTO INITIAL$
0001.
0003..
START$
INITIAL.
XX=10000$
FIGURE 3-The display scope used for program compositio1l
gram label is formatted on the same line with a statement so that its statement number does not appear. For
editing purposes, INITIAL. is statement 2 and XX =
10000$ is statement 3. Block 1 indicates that IPSS is
ready for more input. The user has typed more of his
program in block 2. There are two incorrect statements
in this example. They will be discussed later. When the
user is satisfied with the contents of block 2, he sends it
to IPSS by pressing a "SEND" key.
Figure 4 shows the results of IPSS action on the in-
SET XX
TO 10000
??
GOYO OVER $
XX=XX+l$
NO
DECREMENT
XX BY 1
GOTO LOOP $
OVER. STOPS GO TO INITIAL$
A SYMBOL PAIR IS ILLEGAL
FIGURE 2-Example progrs.m
0003.
INITIAL.
XX=l0000$
0005.
LOOP. .
IF XX LS 0$
FIGURE 4-The display scope after an error has been detected
1352
Fall Joint Computer Conference, 1968
put. Correct statements 4 and 5 have been deleted from
block 2; they have been reformatted and added to
block 3. The incorrect statement
??EDIT MODE
XX=XX-..!.$
'RE 7 $
GOYOOVER$
STARTS
0001.
is flagged by an asterisk (*) in block 1 and the type of
error is explained at the top of block 3. The cursor has
been placed in block 2, ready for user input. The user
can correct the statement to read
GOTOOVER$
by positioning the cursor under the Y, typing T and
sending the entire block 2 again to IPSS. He does not
have to retype the rest of his previous input because
IPSS has restored it to block 2. If he had been using a
typewriter-like terminal, he would have had to retype
the entire incorrect statement and everything after it.
(The statement XX = XX + 1$ is logically incorrect.
it will be used later to illustrate editing and debugging.)
0003.
INITIAL.
XX =1 0000$
0005.
lOOP.
IF XX lS 0$
0006.
GOTO OVERS
0007.
XX=XX+l$
0008.
GOTO LOOPS
0010.
OVER.
STOPS
0011.
GOTO INITIAL S
0012.
TERMS
FIGURE 5-The display scope showing statement replacement
Display interaction in program editing
The user can change his program in several ways: he
can delete lines, replace lines, insert new lines, copy
lines, and move lines. He can also change "signs" within
statements in a particular area of his program. These
tasks are all done by typing the appropriate edit commands in block 2. The user can save himself extra typing if the change consists of modifying statements. The
command *
#COPY M,N$
brings lines M through N to block 2. The user can then
treat the lines as if he had typed them there. For example, suppose that after compilation, execution, and debugging, the programmer finds that statement 7 is
logically wrong and must be replaced. Figure 5 shows
the response ofIPSS after the following sequence. The
programmer types and sends the command *
#COPY 7$
The response by IPSS is to bring statement 7
XX=XX+l$
to block 2. The user then types the command *
*All IPSScommands have both a long and short form. The
short form consists of the first two letters of the long form, e.g.,
#CO and#RE are the short forms forlCOPYand #REPLACE.
# REPLACE 7$
He positions the cursor under the" +" and changes it
to a "-." When he sends block 2 to IPSS, statement 7
will be replaced. Block 3 will be modified to show the
replacement.
The length of the program is not limited to the length
of block 3. When the program exceeds the length of
block 3, lines at the top are removed and the new lines
appear at the bottom. The line identifiers M,N in the
command
#COPY M,N
can refer to any lines of the program, visible or not. The
seemingly more straightforward technique of moving
the cursor to the appropriate position in block 3 has not
been included in IPSS. The technique of determining
which lines have been changed in block 3 is ilifficult in
the type of display equipment we are considering. We
have avoided the use of expensive, complex hardware
such as light pens and function keys. We are assuming
just the ability to move a cursor and send an interrupt
to the main computer. (The TVEDIT program, which
runs under the THOR Display Based Time-Sharing
System at Stanford University,3 provides an example
of what can be done with more complex equipment).
Other display interaction
Consider the previous example of program editing.
Program Composition and Editing with On-Line Diiplay
Suppose that in the course of debugging, the programmer knows that the variable XX is being set incorrectly, but he does not yet know where. Assume that the
program in question is a large one and that the programmer does not remember every place the identifier XX is
used.
The following sequence of commands shows how the
programmer can make use of saved program information, and can use displays to find and correct errorS in
program logic (see Figure 6).
The user first types
1353
He then types **
#ADD DISPLAY 7
which adds statement 7
0007. XX
=
XX
+
1$
Upon reflection, he determines that statement 7 is
wrong and changes it as previously described.
Other 1PSS commands
#DISPLA Y SET USED XX
IPSS clears the display and outputs at the top of block
3:
xx
S3 U5 B7
This indicates that the identifier XX is set in line 3,
used in line 5, and both set and used in line 7. The user
then types **
#ADD DI3PLL\.¥ :3
which adds statement 3 to the current display, as
follows:
0003. INITIAL. XX = 10000$
??
This paper will not describe in detail all the com..
mands available to the user. In brief, the user can display all or part of his program using either statement
numbers or symbolic names for the areas. He can request that the current program display be rolled up or
down like a scroll. He can display the names and corresponding identifying statement numbers of every procedure and statement label. He can display the statement
number of every reference to any identifier. In addition,
any display can be directed toward a hard..copy printer.
The editing commands are described in the following
'
section.
When the programmer is satisfied with his program,
he can compile, execute and debug it using facilities
available in the ADEPT-50 Time-Sharing System.
Eventually, we plan to include compilation of modified
program segments and execution-time debugging in
IPSS.
Techniques oj program editing used by I PSS
*ADDI 7
XX S3 U5 87
0003.
0007.
INITIAL.
XX =1 0000$
XX=XX+I$
FIGURE 6-Program debugging
The previous sections of this paper have described
the user interaction with IPSS via a display scope. The
display scope was chosen for the convenience of the user
and because it offers facilities that-on other devicesare cumbersome or impossible. The techniques IPSS
uses to carry out the user composition and editing requests are, in general, independent of what interactive
device is employed. Their only requirements are that
they are efficient in their use of time and do not impose
undue restrictions on user actions.
Edilling is permitted in any part of a program and in
any order that the user desires. The program is blocked,
and blocks are output to disc as required. IPSS keeps a
record of what statement numbers are included in a disc
record, and permits insertions or deletions of any length
anywhere in the program. The disc records need not be
in order according to statement numbers. This makes
it easy to insert statements anywhere in the program,
**The short form of the CGmmand (lAUD!) is shown in Fi,ure 6
· 1354
Fall Joint Computer Conference, 1968
since new disc records can be added at the end. An attempt is made to combine two records into one after
statements are deleted, when this is possible without
causing extra input/output. A disc record freed in this
way becomes available for reuse whenever needed.
Output of records is minimized by not outputting until
a user request forces it (unknowingly, of course, since he
has no concern with the blocking and input/output of
his program.) Input of records is minimized by remembering what disc records are currently in core.
Editing is done on program segments where a program segment is a single statment or a consecutive
series of statements identified by its starting statement
number or starting statement label, and by its ending
statement number or ending statement label. (The ending statement need not be given if only one statement is
involved.) Such program segments may be deleted froln
the program, moved to (inserted after) another program
statement, copied after another program statement
(this is similar to moving except that the statements are'
also retained in their original place), or replaced by a
new series of statements that the user inserts.
The statement numbers assigned by IPSS during program composition permit up to 1000 insertion statement
numbers between statements. During editing, IPSS
computes insertion numbers based upon the number of
statements to be inserted at a time, and the numbers of
the bracketing statements. The user may override the
automatic assignment of statement numbers by prefixing the first of a series of statements with the starting
number he desires. Automatic assignmer. .t of following
statement numbers depends upon the number he uses
and the next statement number in the program.
The DELETE, MOVE, and COpy commands are
complete in themselves; IPSS assumes that the user
wishes to continue program composition when they
have been executed. The INSERT and REPLACE
commands assume that any number of statements may
follow in one or more inputs; therefore, IPSS continues
to assign statement numbers depending upon the numbers available where the statements are inserted. The
user may indicate that he wishes to continue program
composition by inputting COMPOSE. Block 1 of the
display scope shows the user whether he is in the edit
mode or the compose mode.
A. COpy command that does not indicate where the
statements are togo causes the statements to appear on
block 2 of the display scope. The user may then modify
them as desired and give a command to insert them anywhere in the program.
A SEQUENCE command causes the entire program
to be resequenced. An option permits specifying the
starting statement number and statement increment to
be used in the resequencing.
'
All editing commands previously discussed apply to
entire program statements. There is also a CHANGE
command that permits any specified string of signs
(except a null set) within a statement to be replaced
with any other specified string of signs (including a null
set). The range of statement numbers to be searched for
the substitutions may be limited if desired. At the end
of a statement in which one or more substitutions of
signs have been made, the old statement is deleted and
the new version of the statement is checked for syntactic correctness; it then replaces the old stateme~t.
This process continues until the end of the specified
statement range is reached or until an error in syntax is
detected.
IPSS tries to be permissive to the user and often provides optional ways of accomplishing the same result.
For example, a REPLACE N command followed by a
series of statements accomplishes the same result as a
DELETE N command and an INSERT AT N command followed by the series of statements. User convenience is considered more important than optimumefficiency.
Program information storage and retrieval
At all stages of program composition and editing, a
list (ordered by statement number) is maintained for
each identifier in the program. Each list shows every
current reference to the identifier and denotes whether
the identifier is declared, set, or used in the statement.
Deletions of statements cause deletions of references in
the appropriate identifier lists; insertions of statements
cause insertions of references in the appropriate identifier lists. Thus, at any time, the user may ask where a
variable is set or used and the information is immediately available for display. A link deleted from the list
for one identifier is available for reuse as needed for any
identifIer. In this way the size of the table needed for
the set/used information is not prohibitive.
A dictionary is maintained with an entry for each
identifier in the program. Information that helps in syntactic analysis and links to other tables (such as the set/
used table and the table of procedures and tables) is
kept in the dictionary entry. If a declaration of an identifier is deleted, it is assumed that this identifier will be
redeclared and it will then be assigned to the same
dictionary entry, so that the proper linkages are maintained. For this reason a dictionary entry is not reusable
for another identifier even if the declaration and all
references to the original identifier are deleted.
Other program information available tQ the user by
command consists of a list of procedure names and their
scope denoted by statement numbers, and a list of
statement labels and corresponding statement numbers
Program Composition and Editing with On-Line Display
within the entire program or within any procedure.
Syntax analysis, error detection and correction
Most of the error detection done by IPSS is on an
individual statement basis. All such errors within statements are detected regardless of whether the user is
composing or editing his program. Some additional
checks involving sequences of statements are made during program composition. During composition, -a memory of preceding statements is maintained so that errors
such as an incorrect table structure or a conditional clause
immediately following another conditional clause are
detected, whereas these same errors may go undetected
when the user is editing his program. In the compose
mode, an error message may tell the user what input is
required; in this event only that particular input will be
accepted next as a part of his program.
It is possible (though, in some cases, difficult) to detect these same errors in the edit mode but it is not considered desirable to do so, since this would force the
user to construct his program in a particular order. It is
not required that a program be correct at all stages of
program editing. The final program is the one that
counts; consequently, some kinds of errors involving
sequences of statements are left for the compiler to
catch. Most of the errors are detected by IPSS and the
user is given a chance to correct these before compilation is attempted. When consecutive statements are input in the edit mode, some memory can be built up; the
error checking of statement sequences approaches that
of the compose mode.
In order that program names occurring in edited statements may be correctly identified as to class and scope,
IPSS keeps track of the beginning and ending statement numbers associated with each table and each procedure in the program. This identification is necessary
for error detection within individual statements. It
certainly would be possible for the user to confuse IPSS,
for example, by deleting the END of one procedure and
the heading of the next in order to combine the two procedures into one. This may accomplish what he wishes,
but some error checking is lost. He can accomplish the
saine result without the confusion by moving the desired statements .from one procedure to another and
then deleting the unneeded statements. More complete
error detection is obtained through this second method.
When the end of the program is signaled by TERM$
or when the user requests that his program be compiled
or saved, each procedure and the main program is
checked to see that the BEGIN/END count is correct;
if not, the user ·is told, for each such program area, that
there aren too many BEGIN's orn too many END's. In
order to determine more exactly just where the problem
1355
occurs, he can request that a BEGIN/END count be
made for any program segment. When the error is narrowed down to a reasonably small program segment, he
can request that segment to be displayed for visual
checking. Unfortunately, because of the editing freedom
permitted, a correct BEGIN/END count guarantees
only that the number of BEGIN's and END's is correct
and not that their order is logical. Here again, the final
judge is the compiler.
The syntax analyzer was implemented using syntaxoriented techniques. These techniques have been used
. to construct compilers and have been well documented.4
The syntax analyzer contains subroutines that parse the
statement symbol string and then analyze it ·using an
encoded version of JOVIAL syntax equations. The same
technique is used to analyze the IPSS commands. It
would be relatively straightforward to change the syntax analyzer to handle another language that could be
described in syntax equations. This technique also simplifies the task of changing the IPSS command structure.
Display hardware interface consideration
As stated before, one of the primary objectives of the
IPSS project was to include the use of a display scope as
an interactive device between a time-shared computer
operating system and a user. As usual, there were many
display devices available, and their characteristics
(particularly their computer interfaces) were quite
varied. Thesecharacteristi~s, which ar~ discussed later,
exerted considerable influence on the proposed use ·of a
display in IPSS. In an attempt to reduce any delays i~
the project, an intermediate language was developed
that isolated device-dependent computer code from the
proposed IPSS design. The language made it possible to
plan and implement information manipulations on an
available display before the operational display device
was chosen.
Development of an intermediate display language
that would be easy to use but not restricted to any
particular display device proceeded naturally. After
looking at descriptions of several displays that were
being considered, one common characteristic (which
was so dominant that it was almost overlooked) was
noted. This characteristic was also an essential part of
the hUlnan-to-computer interface. The characteristic
was simply the ability to read and write in a language
already known to the human. The only adequate and
completely versatile means of communicating between
a human and a computing machine is with words and
numbers. If a display can accept and show a written
language that is intelligible to the user, there is no limit
to the type or a.mount of information that can be ex.
~"all
1356
Joint Computer Conference, 1968
changed. Each of the displays being consider
for use had this capability. With this one character. istic in mind, a language was developed assuming
only that a display device would be chosen that would
have the ability to display alphanumeric information
in a gridded form (a number of lines of characters) ;
that the device would also accept external inputs
from a typewriter keyboard; and that it would send
and receive the displayed data to and from a controlling
.
computer.
An intermediate display ti8er'.Q,·language '(IDUL)
The Intermediate Display User's Lang;uage (IDUL)
, is a tool for defining the format and content of a display
device as specified by the program designer. This is done
by dividing the view screen of the display into fields of
information with one or more characters of displayed
information per field. Fields are located by line and
starting column; their lengths are established by field
sizes; associated fields are grouped together with block
numbers, and information to be displayed is defined by
its location or address. This language is not a communication device between the outside user a~d the machine.
Such communications ar~ a function of each particular
application-like IPSS-and should be left to the computer program designer's discretion. IDUL is concerned
with internal communication. It allows the program designer to establish a display format and to design information exchanges without the burden of considering
display specifics.
A language is a communication tool that is used to
exchange information. In the case of I DUL" the language does not have the complex form of a natural language. Instead, it is composed of tabular data that
have accepted meanings. Figure 7 shows a typical
initial display view that can be used to explain the languageforms. Notice that this display has 20 lines of 40
columns or positions which can be described as 22 fields
shown in Table I.
'
It is convenient to group the 22 fields into three
1
2
3
..
5
6
7
8
9
10 11 12 13
'4 IS
16 17 18 19 20 21
•
EN T E R
F·I L E N A.M E:
INDICATE
OESI RED
•
E N T ERN E W
~IO
DATA
0 A T.A
NOW
·ON
22
~::
2. 25 26 21
- - - - - _ - OPERATION:
HER E :
2! 21. 30
~l
32
:;~
34
~5
COMPOSE
E 0 I T
FILE:
FIGURE 7-Typical initial display
-.
36
~ '~
:;9
40
separate blocks: (1) communications or control block~
(2) input block, and (3) heading and data display block,
Remember, the display specification language is a
programming convenience. The program designer uses
it to effect selected information displays in predetermined formats. Therefore, device-specific routines to
generate a display or to read indicated display fields as
defined by internal tabulations must be avaIlable. The
programmer sets up the tables and calls the proper routine to perform either the generation or reading of a display. This fact places an importance on the order and
structure of the display definition tables.
Table II is a Format Definition Table that shows the
fields that were defined in Table I in the IDUL tabular
form for format definition. The fields are entered in the
table in block, line, column order. The display input
fields have zero entries under the "Location of Data"
tabular column to indicate that the fields should initially contain blanks. The entries for heading fields in the
same cohnnn ("Location of Data") show the actual information to be displayed, preceded by the code, LOC,
which is an abbreviation for "location." In the internal
format definition table, the variable data locations for
the heading data, entries 7 through 11, would be inserted by the controlling computer program. The displayed contents of the last ten lines will change as the
data file is enlarged; the data descriptions for these fields
must be continually updated by the using program. The
data fields most frequently read are put in block 1 of the
table to make it more accessible. The next most frequently read fields are put in block 2, and all data to be
displayed but not altered by the viewer are put in
block 3. The block assignments are completely arbitrary
with the exception of block 3 fields. Any field with a
block number of 3 is protected from external change if
this is possible on the display equipment. Block 3 was
used as the protection indicator to allow the user more
freedom in his block assignments while maintaining an
ordered· sequence to the field definitions. It is 'unlikely
that any program designer will need more than two
blocks to identify input fields, and there is no need to '
have more than one proteetion flag. Besides, if the designer wants more field blocking, he can always put the
protected field definitions first and start his data blocks
with block 4.
The last entry in the format definition table (Table
II) is a cursor location. Column 18 of line 3 in Figure 7
is underlined. The underline mark is commonly used by
display manufacturers to indicate for the display user's
benefit where the next input character will go when he
hits a keyboard character key. This mark (universally
known as a cursor) is not alwavs an underscore mark. On
some displays it is a vertic~l line to the left of the
character position. However, its function is always the
Program Composition and Edithli with On-Line Display
same. It points to the next inpllt positiOl,l. The cursor is
a valuable aid, but it is not essential; inf"Ormation exchange could take place without it. (The operitor might
have a little trouble ge1ting his data in t~e right plac6y
but he could ~o it.) IDUL does provide for cursor insertion, as the last entry indicates. It can be recognized ~s
a cursor definition by its position in the table (last) and
its zero field size.
FIELD
1357
The Intermediate Display User's Language (IDUL)
is simply a table containing a fiel~-by-field definition of
a display view, where each field description contains a
block number, line number, starting column, field size,
and data location. Flexibility is obtained by establishing some rules for the use of block numbers and by allowing modifications of the master or o{iginalformat definition .with an overlay specification table. This table
LINE
COLUMN
SIZE
1
1
1
12
Communications or control data
2
3
1
16
Heading
3
3
18
8
4
4
1
38
5
4
37
1
Code input
6
5.
29
7
' Heading
7
5
34,
1
Code input
8
6
1
20
Heading
9
7
1
36
Data input
10
8
1
36
Data input
11
9
1
36
Data input
12
10
5
17
Heading
13
11
1
40
File data display
·
·
·
·
·
·
·
·
·
·
·
·
·
·
22,
20
1
40
DESCRIPTION OF FIELD
File name input field
Heading
·
File data display
T:t\BLE I-A field by field ,description of typical display in Figure 7
1358 Fall Joint Computer Conference, 1968
(which is identical in content to the format definition
table) is used to temporarily change one or more entries
in a format definition table and to identify fields to be
read from the display. Fields can be deleted by simply
zeroing the size, or-:--if this is confusing-by replacing
the block, line, and column numbers with zero, which is
an undefined use. Also, block expansion can be provided by leaving an appropriate number of undefined
field entries in the tables between blocks.
Device-specific routines to interpret the tabular lan-
guage can be built and inserted at any time. This allows
display device. changing with minimal delays, and it
makes it possible to support more than one display type
through internal selection of conversion routines.
Display characteristics
Required insight into the problems of implementing
routines to transcribe such a display definition language
was gained through an examination of some display
LOCATION OF DATA
ENTRY
BLOCK
LINE
COLUMN
SIZE
0
1
1
1
12
0
1
2
3
18
8
0
2
2
4
37
1
0
3
2
5
34
1
0
4
2
7
1
36
0
5
2
8
1
36
0
6
2
9
1
36
0
7
3
3
1
16
LOC(ENTER FILE NAME:)
8
3
4
1
38
LOC(lNDICATE DESIRED
OPERATION: COMPOSE
,)
.)
9
3
5
29
7
10
3
6
1
20
LOC(ENTER NEW DATA HERE:}
11
3
10
5
17
LOC(DATA NOW ON FILE:)
12
3
11
1
40
0
~
~ ~
.
LOC(EDIT
·
·
·
~
21
3
20
1
40
0
22
2
3
18
0
0
TABLE II-Format definition table for typical display
{Cursor Location}
Program Composition and Editing with On-Line Display
characteristics. The three displays discussed here are
hypothetical, rather than real. This was done to incorporate as many characteristics of real displays into as
few examples as possible.
The hypothetical displays have several common
characteristics. Each one has a buffer storage where the
display image is retained for automatic periodic regeneration of the picture; each one has a cursor that
points to the next input position; each one has an input/
output path to a computer; and (as pointed out before)
each one displays character information in rows. The
actual data transfer technique is not important in this
discussion. Data transfer is a function of the sending
and receiving equipment, and is-therefore-different
in every combination. Yet, the capability must be there.
Likewise, the buffer storage medium is not as important
as the fact that the buiffer is there. Some input/output
restrictions are caused by the buffer hardware; these are
important. (These restrictions are indicated in the individual display discussions.)
The three typical displays do not cover all of the possible display characteristics. They do exhibit a representative set of visual display features.
Table III lists six characteristi cs of three hypothetical
display devices and an ideal display. The first device
has a maximum of 40 lines of up to 50 characters per
1359
line. Its data storage buffer has space for 1000 characters of data that includes the format control characters.
Thus, the amount of information that can be displayed
is limited by size of the storage buffer, not by the row
and column limits. Also, note that the buffer storage
units are not addressable. The entire buffer must be reloaded to change the picture, or all preceding data must
be read to read a field of data. Since the device has no
computer interrupt signal, the computer program must
poll the display to determine when data are ready for
transmission from the display storage to the computer
storage. This means that the supporting program must
periodically send a message to the display ,asking for
control data. As indicated above, format controls are
required to position the information on the screen in the
required positions. These characters (such as carriage
return, horizontal and vertical spaces, insert cursor,
enter format mode, return to start, etc.) occupy space
in the display buffer storage, but at the same time they
eliminate the need for storing blanks to fill fields and
lines, and they protect data from keyboard change. The
cursor controls are limited in the sense that the cu~sor
position cannot be determined by the computer. It can
be positioned, but it cannot be located if it has been
moved.
The second display device is more versatile. It can
TABLE III-Characteristics of hypothetical display devices
MAX.
MAX.
NO.
NO.
LINES COlMS.
BUFFER SIZE
AND
ACCESS METHOD
I/o CONTROLS
FORMA T CONTROLS
CURSOR CONTROLS
1
40
50
1000 characters of
non-addressable
storage
Computer-initiated
full buffer with
polling required
All displayed fields
are relative to a
starting position
controlled by stored
formatting characters;
protection provided
Cursor can be inserted
but cannot be found by
computer
2
50
70
4000 or 8000
characters of
add ressab Ie
storage
Conso lei nterru pt
signal available
Display positions are
controlled by light
beam position and
display orders;
protection provided
Cursor can be inserted
into any buffer position
and its position can be
determined by the
computer program
3
20
40
800 characters of
addressable storage plus space for
format controls
Console interrupt
available
Each storage pOsition
is displayed in a
fixed display position;
.protection provided
Cursor controlled by
Cursor Address Register
that can be set or read
by the computer program
I
D
E
A
l
40
80
3200 characters of
addressable storage
Console interrupt;
partial read/writes
from any location
Fixed storage-todisplay positions
relationship; data'
protection
Computer-accessible
Cursor Address
Register
1360
Fall Joint Computer Conference, 1968
display a full 50 lines of 70 characters per line; it has
4000 or 8000 characters of addressable buffer storage;
it can be signaled to read through a computer interrupt
key; display positions are set by positioning the light
beam; fields can be protected; the cursor can be inserted
at any displayed position; and the computer can determine the cursor location. This more flexible device can
also draw lines or vectors between grid points, but this
capability is not very cOrnlnon, so it is not handled by
the basic IDUL. It can be utilized with simple additional code, but the resultant program becomes restricted to the device.
The last hypothetical display device is more direct
and easier to use than the other two. It has 800 fixed
storage positions that correspond to the 20 lines of 40
characters per line of displayed data. The first buffer
storage character is displayed at line 1, position 1, the
forty-first character is displayed at line 2, position 1,
etc. This display can signal for computer action with an
operator key, and the cursor is controlled by a cursor
address register that can be set or sampled by the computer program. The displayed data can be protected
from external change.
'Of course, these typical display devices do not contain all of the features that are now available. They do
point out some of the major differences that IDUL routines or any display support package must consider. The
language translator that transcribes the display definitions into computer code must be able to recognize
signals from the individual displays; it must convert the
tabular definitions into forms acceptable to the display;
it must convert data from the display (and in some
cases reformat the data) into a form usable by the computer program; it must control the input/output
operations; it must be able to effect data protection, and
the Intermediate Display User's Language Translator
must provide a mechanism for setting cursor locations.
The characteristics for the ideal display were selected
to simplify the translation of the Intermediate Display
User's Language into computer code. The fixed relation-.
ship between the storage position and display positions
makes it possible to change or read all or part of the display. This eliminates the transmission of redundant information between the computer and the display. The
absolute cursor controls and keyboard interrupt provide
for immediate location of· communication areas with
minimal computer testing. And the character-by-character protection of displayed information permits maximum flexibility in the selection of characters for protection. An IDUL--to-machine-code translator could be
quickly and easilt written for these ideal characteristics.
The described Intermediate Display User's Language
has been implemented for the Interactive Programming
Support System using an IBM 2250 display operating
under the ADEPT-50 Time-Sharing System. The 2250
display is not the one that will ultimately be used.
Therefore, new routines will be required to interpret
the basic ID UL, but the many display views set up by
the IPSS routines will (we hope) remain intact, with
each view defined in terms of its field length and display
view position by line and column as stated in the
Intermediate Display User's Language tables.
CONCLUSION
We have found that a display scope for program composition and editing is preferred over a typewriter-like
terminal by most users. This preference has also been
noted in THOR.3 This perhaps reflects the fact that
typing is a skill not necessarily possesed by all programmers.
None of the displays we have examined are completely suitable for the requirements of IPSS. In addition to the hardware characteristics noted in Table III,
an ideal display should be large enough (say 40 lines
with 80 characters each) to contain a reasonable sample
of data, We have found that the programmer needs
a minimum of 20 lines in block 3 alone, in order to correlate displays of several kinds of information. Two
final requirements are that the display device must be
compatible with computer input/output hardware and
the device must be inexpensive.
Syntactic analysis combined with editing gives the
programmer two powerful programming aids. He is assured that his edited program is syntactically correct
by being immediately advised of errors. He has access to
dynamically current program information. IPSS has
just begun to develop techniques to process this information and present it in a form useful to the user and
thus offer him a significantly improved alternative to
personally extracting similar information from program listings.
REFERENCES
1 L P DEUTSCH B W LAMPSON
Reference manual QED time-sharing editor
Document No 30 60 30 University of California Berkeley
November 1965
2 The compatible time-sharing system-A programmer's guide
The MIT Press Massachusetts Institute of Technology
Cambridge Massachusetts
3 J McCARTHY et al
THOR-A display based time-sharing system
Proceedings Spring Joint Computer Conference 1967 pp
623-633
4 R WFLOYD
The syntax of programming languages-A survey
IEEE Transactions on Electronic Computers 1964 Vol EC-133
pp346-353
New horizons for magnetic bulk storage devices
by FRANK D. RISKO
Bryant Computer Products
Walled Lake, Michigan
INTRODUCTION
There are many types O'f auxiliary bulk stO'rage
devices available O'n the market nO'w and certainly
many mO're will be available in the future. The
second, and in sO'me cases, thirdgeneratiO'n bulk
stO'rage devices are making their appearance O'n
the cO'mputer peripheral market nO'w. These devices, much to' the surprise O'f many peO'ple, are
still rO'tating magnetic media devices. This paper
discusses O'nly state O'f the art bulk stO'rage devices
of the magnetic recO'rding variety. HO'wever,
since a IO'O'k at the future is in O'rder, tO'ward the
end O'f the paper, we will attempt to' cO'njecture as
to' what future memO'ries may IO'O'k like.
The questi'On O'f using bulk stO'rage evO'lves
arO'und certain maj O'r factO'rs. One factO'r is CO'st.
This is the primaryreasO'n why such items as
micrO'lO'gic O'r integrated circuiV flip-flO'Ps have
nO't emerged as bulk stO'rage devices. The CO'st
per bit O'f these types O'f devices is extremely high
and even with LSI (Large Scale Integration) O'r
wO'ven screen memO'ries, it is still an expensive
proPO'sitiO'n. Magnetic thin film devices and magnetic cO'res are bO'th used in mO'st cO'mputer systems fO'r the sO'-called scratch pad, O'r high speed
memO'ry. But again, these devices-in terms O'f
bulk stO'rage-are much toO' CO'stly.
TO' put the area O'f bulk stO'rage into perspective,
this paper cO'nsiders small stO'rage as thO'se O'f less
than five milliO'n bits. (The majO'rity O'f these are
head per track devices.) The next memO'ry size
range cO'nsiders a medium range memO'ry to' gO'
frO'm 5 milliO'n to' 50 milliO'n bits. (This is the
beginning O't the PO'sitiO'nable,..head devices.) Large
magnetic memO'ries are then cO'nsidered from 50
milliO'n to' 500 milliO'n bits. Bulk memO'ries 'ObviO'usly fall abO've the 500 milliO'n bits capacity
and have ranges gO'ing up to 10 billion bits. Mem
O'ries above this range which could gO' up to the
1361
trilliO'n* and possibly the quadrilliO'n bit range
shO'uld be cO'nsidered large bulk memO'ries. Since
a cO'mmon term makes cO'mparisO'n easier, the bit
has been generally used in this paper because
character length is manufacture-dependent. When
apprO'priate, character is used and is assumed to'
have eight bits.
Since the abO've ranges of memO'ry-particularly in magnetic stO'rage devices-cO'ver a lot of
applicatiO'ns, discussiO'n is limited first to' state O'f
the art memO'ries in bulk stO'rage category O'f the
cO'ntact and nO'n-c'Ontact type and then extends
these to' the near future and beyO'nd. Many papers
have been presented in the past107 which have documented many aspects of bulk memO'ries. This
paper tO'uches O'nly O'n sO'me O'f the mO're inportant
aspects which are affecting present-day thO'ught
and equipment design.
Performance factors
There are twO' majO'r perfO'rmance factO'rs which
must be cO'nsidered in the discussiO'n of bulk stO'rage devices. These performance factO'rs can be
defined as hardware-derived and system-derived. 4
The hardware derived perfO'rmance factO'rs cO'nsider the major areas of:
-
Capacity
Access Time
Latency
Data Transfer Rates
C'Ost per Bit (or bits per dollar)
The system derived performance factO'rs cO'nsider such items as:
-
Throughput
*Possibly a new unit of measure such as the Mega-Mega Bit
(MMB) for trillion bit capacity should be used since the "mega"
is already an accepted term.
1362
-
Fall Joint Computer Conference, 1968
Indexing Procedure.
Memory Allocation
Chainipg Provisions
File Activity
Provisions for Queuing
Checking Techniques
Format
Each of the various types 'Of memory devices
such as tape, disc or drum excel in one of the
areas listed above more so than in another. Obviously the most important points must be considered in order to 'Optimize the utility of a particular type of system. Because it would be almost
impossible to discuss all of the just mentioned
factors, this paper is limited to throughput, memory allocations, file activity and format.
Hardware factors
Capaeity
Capacity is considered as twofold since this
could be taken as total fixed on-line capacity, or
total unit capacity, where the unit could be a reel
of tape or a replaceable disc, or disc pack. The
disc has maj or advantages when c'Onsidered as a
bulk store. Using any 'Of these three devices it is
possible to have virtually rooms full of records
up to an almost infinite store. However, the access time of a particular record in that store includes the operators' "fetch" time when c'Omparing
it to an on-line fixed store. Most people do not
consider "fetch" time when comparing storage
devices. Further comparison between these devices is not meaningful because the disc pack outperf'Orms the tape in the area of random access
and longevity, and all of these devices have :'
limited on-line unit capacity.
Consider the fixed capacity on-line store. If
enough units (floor space provided) can be put in
tandem with the proper controller, it is possible
to have in excess of five billion characters available. This means "wall-to-wall" data cells, disc
files or drums.
TABLE I
MANUFACTURE
I
2
Bryant
CDC
Data
Products
Burroughs
IBM
UNIT NO.
4
4000
4000
4000
4000
5
6
7
3
CAPAC I TV
MILLIONS OF BITS
Mod
Mod
Mod
Mod
I
2
2.
2b
750
1600
4000
5000
60
60
60
60
140
160
160
160
Phd 340*
Phd 170*
340
170
30
30
70
Co-145*
145
9
10
11
~IB
12
13
dp/f5"045111
~
~14
663~
dp/f50~5
£475
14
15
16
17
2302-4
2311-12
2314
2321**
NCR
I~
353-5**
RCA
19
20
70/56~- I 1**
21
Fastrand FRII
Univac
ACCESS TIME
M I LLI SECONDS
MIN.
AVG. MAX.
24HH-H**
I~O
END USER COST
DOLLARS
BI TS/oOLLARS
260K
305K
440K
4~OK
70
105
105
115K
105K
17
33
210K
690
11,100
2,720
1,~20
3750
1200
1000
40
34
25
146
65
70
726
110
115
310K
205K
325K
~70
50
15
150
~5
250
150
217K
450K
20
40
95K
I,OHO
115
IHO
9~
1~5
5,0]'0
1,650
~~
165
600
355K
16K
252K
140K
5000
102
I~OO
43
1656
3200
50
30
25
50
550
5,~50
3,O~0
3,~40
11,100
6,5~0
22,!:SOO
360
3
110
125
5~K
6,220
44HH
2400
136
130
500
500
550
640
23HK
135K
t!:S,!:SOO
17,HOO
920
5
92
155
16~K
5,4~0
*
DRUM
.** STRIPS OR CARDS
All other units are discs.
the long access time ranges. Some head per track
devices are only limited by rotational latency for
access time, but they generally fall into the large
storage area rather than the bulk storage area
as we mentioned earlier.
If we consider the larger replaceable disc drive
type device, such as the IBM model 2314 with
eight disc packs and single data channel operation, we find that we have multiple-seek features
for the 3.2-billion bit st'Orage. If, for a moment,
Aeeess time
Access times for very large stores are generally
longer than 75 milliseconds. The reason for this
is that they are generaIIy moving head devices,
or moving strips such as CRAM. The simple fact
that an electro-mechanical or electro-hydraulic
p'Ositioning device is used puts these devices into
2,~~0
5,240
9,100.
10,400
205
105
205
FIGURE I-Bulk store-capacity vs, access time
New Horizons for Magnetic Bulk Storage Devices
1363
types 'Of mass mem'Ory devices. Nete that the
greatest economy is gained with strip-type devices at an increase in access time. Also, that all
the units outside the trend area to the left in
Figure 2 are strip devices. However, the need fer
increasing speed to obtain data will reduce this
trend and cause the industry to move toward the
faster access devices into the high bits per dellar
range. One of the major problems with the strip
device' is its poor reliability and limited magnetic
coating life.
Latency time
we w:ant to consider only cost versus access time,
we can get the cheapest bulk storage device by
buying a unit which has very low cost, but with
a long access time. The IBM model 2321 gives
22,800 bits per dollar but at 550 milliseconds access time. A similar price comparison for a Bryant Series 4000 Model 2B Disc File gives us 10,400
bits per dollar and an average access time of only
160 milliseconds. In other words, on one hand
you can reduce the cost of a memory system by
50 %, but the access time is increased by over
300 %. See Table I for a comparison of various
manufacturers capacities, access time and costs.
To fully appreciate some of these hardware
performance characteristics, we may examine
Figure 1 which shows the capacity of the various
electro-mechanical types of devices versus access
time. This area shows that the higher the capacity
'Of a given store the longer its average access time.
Naturally, everyone wants not only a larger store,
but wants access to that store in the minimum
amount of time, so the area trend line can be expected to move to the left in the future. Figure 2
indicates the capacity versus end-user cost on a
bits-per-dollar basis. Again, the trend is end-user
cost reduction with increasing capacity. The trend
area shows the cost by capacity of the various
Latency time and data transfer rates are inseparable. Latency time is defined as the time of
a single cycle of the magnetic memory device.
Data transfer rate is directly related to how many
bits-per-inch have been packed ente the given device surface. Since we are always striving· fer
maximum capacity, we are usually recording at
maximum packing density. In order to reduce
latency, we need as high a surface speed as p'Ossible, which increases the transfer rate. In a
typical serial device, the data transfer rate ceuld
be five Mega-bits per second. This weuld be typically a rotating device with a mean diameter of
10 inches, turning at 3600 RPM with data written
at 2500 bits-per-inch. Lower surface speed units
with parallel data transfer can achieve similar
rates.
System factors
System-derived performance factors previde a
most interesting, as well as practical aproach to
the bulk sterage areas. With time sharing users
becoming more sophisticated, a larger amount of
en-line storage is required. This larger on-line
storage, however, necessitates a higher throughput. One of the ways threughput ('Or transactiens
per second) can be improved upon in a bulk st'Ore
is to increase the tetal number 'Of time sharing accesses to that store.
Throughput
Censider for a moment an imaginary timesharing installatien which has a given number 'Of
users.· Te use this computer 'On a time-share basis
it sheuld be obvieus that there must be s'Ome
amount 'Of sterage allocated fer the users. Sterage
requirements are a function 'Of hew the user is
actually achieving his necessary results with his
1364
Fall Joint Computer Conference, 1968
so-called "own computer." A sophisticated user
would probably need on the order of 200,000 characters of storage as opposed to a less sophisticated
user who would only require on the order of 50,000
characters of storage. Generally this means
that somebody has to wait during the access-time
period depending on queuing of the various computer user requests. It could be feasible to reduce
waiting time for a given number of users by
doubling the computer store access capability.
(Additionally, security must be provided S'O users
cannot access each other's data.) Since these
people are not accessing the same data, it then
seems practical f'Or each user to have his own independent access mechanism. This could be taken
care of very easily by going to a group of disc
drives (let us say 50 drives for 50 users) in 'Our
imaginary time-share system. Obviously, the cost
of such a system would be prohibitive because the
time-share user cannot afford this luxury.
The next best thing would be to have a number
of accesses of positioners on the same device. Some
average number of users will always be on-line
(let us assume this number to be 25). With 25 on
line, how many will be needing access to the bulk
storage continuously during any given period of
time? The number would probably average 10 to
15. Because of the very nature of the binary application, it would be most feasible to have a binary number of accesses. This may be 8 or 16
positioners. Let us now assume that we do have
16 available; this allows the system performance
to increase by a factor or 16 (in regard to
throughput) over what a normal single positioner
machine would give. One of the unfortunate features of a time-shared system is the fact that at
a given point in time we usually have more than
one user wanting to access the same positioner.
No end to the dilemma....
Memory allocation
. Having more than one user accessing a device,
a time-share application, memory allocations
for each user ts limited in order to serve as many
people as p'Ossible and still not over-extend the
available memory. This is particularly important
because the computer itself will want some of the
available memory for internal executive and
swapping programs. Therefore, it is sometimes
l1ecessary for time-share systems to redistribute
data in order to make a more ec'Onomical access
and thereby maintain reliable· throughput time.
Memory organization
Another side of the system-derived factors are:
what is the best rec'Ord length; the best format;
the best organization, in order to optimize the
system? The user may not always organize his
data for the most efficient throughput or most
efficient search operations, so an additional strain
is put 'On the total system. Many studies have been
made of the most efficient storage length (or sector length) and storage use. One such study by
Brenner8 discusses this as a probability function
versus data length, and the frequency of use versus
data length. In weighing performance versus
storage use, Brenner showed that for a performance of 90 %, a record length 'Of 600 to 700 characters is optimum. His decision to use this length
was based on the absolute change in performance
versus storage use. Figure 3 shows that storage
use decreases very quickly as data length increases. In other words, to achieve a performance
approaching 'One hundred percent, it is necessary
to have a very long record length.
Of course, one of the major problems with
record length is the fact that storage use dePerformance
I.p
:8
.6
.5
Storage
Uti Ilzatlqn
...
In
.2
.1
Character length
FIGURE 3
Performance and storage utilizati n
New HorizQns fQr Magnetic Bulk StQrage Devices
creases as length increases because 'Of variQus
'Over-head functiQns. This is reflected in an independent (unpublished) study which shQwed
that the mQst feasible length is apprQximately
nine-thQusand bits. In 'Order tQ make the bit
quantity binary, the amQunt with the nearest factQr is actually 256 twenty-fQur bit wQrds, which
gives us apprQximately 6000 bits as the mQst useful ('Or 'Optimum) length. This study is in apprQximate agreement with the study made by
Brenner.
The system and prQgramming aspects must be
extended fQr a given unit in 'Order tQ allQw fQr the
prQper indexing, chaining and queuing techniques
which are required by the mechanical PQrtiQns 'Of
the stQrage device. ObviQusly a head-per-track,
parallel system WQuld prQvide the ultimate in all
these areas, but WQuld be very expensive because
of the electrQnics required tQ handle such a system.
Present and future trends
The present hardware state 'Of the art of the
hulk memQry field has decreased tQ 5-mil track
widths with 7.5 mil centers between tracks while
packing densities have increased upwards tQ 2500
bits-per-inch. The 5-mil track widths give apprQximately 128 tracks-per-inch. This gives us a
quarter 'Of a milliQn bits per square inch stQrage
capacity as the state 'Of the art magnetic recQrding
'Of t'Oday. H'Owever, magnetic recQrding develQPment is n'Owhere near 'being finished in this particular area.
Magnetic recording in the 'Order 'Of 20,000 bitsper-inch have been demQnstrated9 ,1.0 and will,
nQ dQubt, be the future packing densities by the
mid-1970's. Additi'Onal hybrid electrQnic circuits
and recQrding methQds will definitely be necessary
to achieve these ends. At the present time we're
talking 'Of practical playback levels at the head
'On the 'Order 'Of 'One t'O three millivQlts. By 1970
tQ 1975, the playback ranges will be dQwn tQ the
'Order 'Of 10 t'O 30 micr'OvQlts. This will require
amplifiers which must be absQlutely immune tQ
nQise and spuriQus signals. These values, I might
~,dd, are being achieved experimentally tQday in
the labQr~tQry and this is where we were apprQXimately five years agQ. I believe during 1961 and
1962 that Shew frQm IBM was dQing magnetic
recording 'On the 'Order 'Of 1000 to 1500 bits-perinch under labQratQry cQnditiQns wQrking with
1365
l-mil wide PQle pieces. 11. At that time, state 'Of the
art was generally 300 bits-per-inch.
Positioners
A majQr CQncern abQut use 'Of the 1-mil PQle
piece is that 'Of PQsitiQning tQlerances necessary
so that 'Off-track and peak-shifting prQblems dQ
nQt affect playback. The PQsitiQning mechanism
will have tQ be at least tWQ 'Orders 'Of magnitude
better than present day standards in 'Order tQ accQmmQdate this type head. DevelQpment wQrk at
Bryant shQWS that the next generatiQn bulk stQres
will make use 'Of a 2.5 tQ 3 mil track and will be
spaced 'On 3.75-mil centers. This means that we
shQuld achieve apprQximately 256 tracks-per-inch.
CQnsidering 'Only a mQdest increase in packing tQ
4000 bits-per-inch, we will arrive easily at onemillion bits-per-square inch by 1970. The majQr
breakthrQugh, 'Of CQurse, is the PQsitiQning device
itself, which must be fantastically mQre accurate
in the area 'Of track selection and PQsitiQning repeatability.
TQ cQntinue 'Our view 'Of future magnetic devices, I WQuld venture tQ say that a minimum 'Of
16 multiple access mQving head-bulk stQres, with
tQtal capacities 'Of 50 billiQn bits, shQuld be with
us by 1972. The capacity frQm then 'On willprQbably increase I'Ogarithmically and the next jump,
I WQuld say withQut any hesitatiQn, WQuld be frQm
50-billiQn tQ 100-biliQn bits and then frQm 100billiQn t'O a 100-trilli'On bit magnetic memQry by
1975. This again will be a magnetic memQry in
which certain as yet unimagined manufacturing
techniques will have been achieved.
Head developments
By 1975 the head will nQt be a discrete individually-assembled element but will be batchfabricated heads similar t'O t'Oday's micrQI'Ogics.
The preamplifiers will n'O dQubt be deposited as
part 'Of the head assembly. I alsQ believe that
Inany new techniques will have tQ CQme frQm the
metallurgical and the chemical industries t'O give
us the needed techniques and materials in 'Order
tQ achieve 16 tQ 32 heads per pad withQut interfering cr'Osstalk and frequency limitations. At the
present time there are many devices 'On the market
which have fr'Om 9 t'O 20 heads per pads, the Bur,·
r'Oughs disc file f'Or 'One, the D'ata Disc and Bryan)
units (which have 9) fQr anQther.
The nerSQn wh'O wants a tremend'Ous bulk stQrp
1366
Fall J 'Oint C'Omputer C'Onference, .1968
10.0,--_ _ _ _ _ _ _ _ _ _ _ _ _..,......,...._ _.....,
/
/
/
/
1.0 I-----------~~---------l
/
/
O. I
>D-
o
Z
~
l!! 0.01
ID
~
NOTE:
See Table 2
fo,. data
en
ffi
c
0.001
1951j
19511
1962
1966
1970
yEAR
FIGURE 4 Packing density vs. year
iR n'Ot g'Oing t'O pay any more in 1975 f'Or a trilli'On
(Mega-Mega) bits than he W'Ould f'Or a trilli'On bits
right n'Ow. The maj'Or difference will be that a
user will probably 'Only need 1/16 the fl'O'Or space
t'O h'Old that device and, n'O d'Oubt, at a much lower
P'Ower consumpti'On. The gr'Owth 'Of the industry
as shown in Table 2, is pl'Otted as a functi'On 'Of
packing density (bits/sq. in.) versus the year ass'Ociated with it.4-6 This is sh'Own in Figure 4, and
is interesting, because the gr'Owth has been increasing by an 'Order 'Of magnitude every five years
fr'Om 1956. At this rate a milli'On bits-per-square
inch will be c'Omm'Onplace by 1970.
TABLE 2
YEAR
1956
1962
1963
1967
DENSITY (Bits/Sq. In.)
2,000
25,000
50,000
250,000
The 'Obvi'OUS area of impr'Ovement al'Ong with
the batch fabricati'On techniques envisi'Oned f'Or P'Ositi'Oning head devices will be t'O P'Ositi'On the heads
over a much sh'Orter distance. The sh'Orter this
distance the greater the impr'Ovement in access
time. S'Ome present day devices m'Ove as much as
two inches and some as little as a quarter of an
inch. I believe that 'Our 1975 devices will use electrical P'Ositi'Oners and that the distances traveled
will pr'Obably be 'On the 'Order 'Of less than 50th'Ousandths inch. The reas'On is that the track
width being 'Only I-mil, 'Or P'Ossibly 2-mils, will n'Ot
all'Ow a P'Ositi'Oning accuracy for m'Ovements
greater than that.
If we c'Onsider the present C'Ost 'Of these vari'Ous
devices the future cost rati'O will n'Ot really change.
In 'Other w'Ords, the C'Ost per bit is n'Ot g'Oing t'O g'Oup appreciably, n'Or is it g'Oing to dr'OP. The manufacturing and material C'Osts will increase, causing
the unit C'Ost t'O increase, but, by the same t'Oken,
the techn'OI'Ogy in terms of packing density and
bits-per-square inch, as well as bits-per-cubic inch
(which, 'Of c'Ourse, plays an imp'Ortant r'Ole in fl'O'Or
space) will also change such that the average C'Ost
per bit ('Or bits per d'Ollar) will n'Ot change, but
will remain relatively c'Onstant.
CONCLUSION
Magnetic type devices are definitely here t'O stay
f'Or an'Other ten years bef'Ore they give way t'O the
laser/'Optical type devices. The disc packs pr'Ovide
useful bulk st'Orage and will c'Ontinue t'O d'Ominate
the small-st'Orage market. The disc packs have a
definite place in the bulk mem'Ory market alth'Ough
in a different way. The 'On-line bulk st'Ore will be
m'Ore necessary in the future and will be available
,vith multiple accesses. S'Ome 'Of the pr'Oblems t'O
be 'Overc'Ome are reliability and impr'Oved perf'Ormance andeliminati'On 'Of the redundant st'Ore
which is necessary f'Or large systems. An'Other
area 'Of gr'Owth will be the medium range (head
per track) devices f'Or use in swapping require
ments f'Or time-share instaIlati''Ons.
Optical type devices ~re a definite way t'O g'O, but
they may get c'Omnetiti'On fr'Om LSI devices. The
ph'Ot'Ochr'Omic and laser 'Or 'Optical-type device~.
which wiJI far exceed t'Otal capacity per sauare
inch (25 milli'On-bits-rer-sa. in.) have a I'Ong way
to g'O t'O reach the present state 'Of the art 'Of magnetic rec'Ording.
Alth'Ough they are capable 'Of larger canacitie~
in smaller areas. the techn'OI'Ogy t'O devel'OP them
js still in the future. Magnetic rec'Ording 'Of digit~l
inf'Ormati'On has a g'O'Od S'Olid 15 years, maybe 19
years, 'Of techn'Ol'Ogy behind it, where3s attempting
t'Oemnl'Oy las-ers in reading and writing (not just
read only) is a tremendous techn'OI'Ogical achieve"'!.
ment that must be made bef'Or~ the laser technique
New Horizons for Magnetic Bulk Storage Devices
or beam-memory techniques will become feasible.
At the present time there are many laser readonly memories in 'Operation. I don't want to detract from this achievement, but I feel very strongly that--in order for them to achieve the same
state of the art as the magnetic recording media
has now (and will have by 1970)-some major
technological advances will have to occur. Maj or
research effort is being devoted to this area and
the advancement could occur sooner. The holographic displays, although they haven't been publicized much lately, appear also to be feasible and
will pr'Obably give the laser photochromic devices
a good run for their money. However, they still
must be nondestruct read/write.
I would like to quote Marvin Camras from the
50th anniversary issue of the IRE Pr'Oceedings in
196212 extrapolating progress to the year 2012.
"The first magnetic memory devices resembled tape rec'Orders, just as the first
aut'Omibiles resembled horse carriages.
Eventually tape recorders evolved into the
standard memory pack which is presently
manufactured in large quantities by specialists. The memory pack of today (2012) is a
sealed. b'OX abQut the size 'Of a package 'Of
playing cards. It holds upwards 'Of 1020 bits
'Of information, and has n'O mechanically moving parts; the recording, read 'Out, and scanning are all electronic. The stQrage density
is SQ high that the infQrmatiQn 'Of entire libraries is cQndensed intQ a few cubic feet.
Additional mQdules are added t'O extend the
capacity tQ any required .level."
I WQuld say we still have a I'Ong way to go to
achieve that prediction, but the way thingR can
and do happen, a major breakthr'Ough CQuld at
any mQment 'Occur; I certainly do believe that it
can be done.
REFERENCES
1 R A HENLE L 0 HILL
Integrated computer circuits-past present and future
Proceedings of the IEEE December 1966 pp 1849-60
2 L C HOBBS
Effects of large arrays on machine organization and hardware /
software tradeoffs
Proceeding-Fall Joint Computer Conference 1966 pp 89-96
3 LCHOBBS
Present and future state-of-the-art in computer memories
IEEE Transactions on Electronic Computers vol EO-15
August 1966 pp 535-549
4 A S HOAGLAND
1367
Mass storage revistied
AFIPS Proceeding-Fall Joint Computer Conference 1967
pp 235-60
5 LCHOBBS
Review and survey oj mass memories
AFIPS Proceeding-Fall Joint Computer Conference 1963
pp 295-310
6 THBONN
Mass storage A broad review
Proceedings of the IEEE December 1966 pp 1861-70
7 NNISENOFF
Hardware for information processing system: today and in the
future
Proceeding of the IEEE vol 54 no 12 December 1966 pp 182035
8 FHBRENNER
On designing generalized file records for management
information system
AFIPS Proceeding-Fall Joint Computer Conference 1967
pp 291-303
9 KANORRIS
A technique for high density digital magnetic recording
Presented at the Western Electronic Show and Convention
August 241967
10 C W STEEL J C MALLINSON
A computer simulation oj unbiased digital recording
Abstracts of 1938 Intermag Conference Washington D C p 3 3
11 LFSHEW
High density magnetic head design for non-contact recording
IRE Transactions on Electronic Computers December 1962
pp 764-83
12 MCAMRAS
Magnetic recording and reprodu,ction-2012 AD
Proceeding of the IRE vol 50 no 5 May 1962 p 639
BIBLIOGRAPHY
1 M S FINEBERG 0 SERLIN
Multiprogramming for hybrid computation
AFIPS Conference Proceedings 1967 vol 31 Washington D C
Thompson Book pp 1-13
2 L R GLINKA R M BRUSH A J UNGAR
Design through simulation of a multiple-access information
system
AFIPS Conference Proceedings 1967 vol 31 Washington D C
Thompson Books pp 437-47
3 A S HOAGLAND
Mass storage
Proceedings IRE vol 50 May 1962 pp 1087-92
4 RLPETRITY
Current status of large scale integration technology
AFIPS Conference Proceedings 1967 vol 31 Washington D C
Thompson Books pp 65-85
5 CSPOLAND
Advanced concepts of utilization of mass storage
Proceedings of IFIP Congress 65 vol 1 Washington D C
Spartan Books 1965 pp 249-54
6 J A RAJCHMAN
Computer memories-possible fut1~re developments
RCA Review
vol 23 June 1962 pp 137-51
7 D E SPELIOTIS
Magnetic recording theories; Accomplishments and unresolved
problems
IEEE Transaction and Magnetics vol MAG-3 September
1967 pp 195-200
Laser recording unit for high density permanent
digital data storage
by K. McFARLAND and M. HASHIGUCHI
Precision Instrument Company
Palto Alto, California
INTRODUCTION
The Laser Recording Unit designed and developed
by Precision Instrument Company provides a
means for reliably and permanently recording
and- reproducing digital data.
The Laser Recording Unit uses a new type of
permanent recording process which employs a
laser to vaporize minute holes in the metallic surface of the recording medium. In this manner
digital information is recorded in parallel data
tracks along the length of a recording medium
strip. The tracks are spaced on the order of five
to ten microns (micrometers), center-to-center;
each track is composed of bit cells three to five
microns in size. For recording or reproducing
8equential tracks of digital data, the maximum
transfer rate of the Laser Recording Unit is approximately four million bits per second, with an
average unrecoverable error rate of one in 108
to 109 bits, depending on the data density selected.
The Laser Recording Unit includes a programmable Recorder Control Subsystetrl which can be
designed to provide a hardware and software
interface compatible with a specified computer
system.
The major benefits offered by the Laser Recording Unit as a mass digital-data storage unit are
summarized below:
(1) Permanent Storage: Data do not degrade
over a period of time of the order of years.
(2) Compact Storage: Data are stored at a
density approximately 250 times greater
than that of digital magnetic tape.
(3) Unlimited Readout: Data can be repeatedly readout for long periods of time with-
out reduction in quality or damage to the
record.
( 4) Recording Verification: Essentially errorfree data records result from the simultaneous read-while-write verification capability
that is unique to the laser hole-vaporization
method of permanent recording.
(5) Low Error Rates: .The average unrecoverable error rate is approximately one in 108
to 109 bits.
(6) Economical Data Storage: Recording of
large quantities of data on the Laser Recording Unit and permanent storage of the
data in PI Record Strips significantly decreases the cost-per-bit of recording and
storage imposed by existing methods.
Laser recording unit de8ign
The Laser Recording Unit employs a special
recording medium in strip form which is automatically mounted on a precision drum assembly.
Using digitally modulated incident coherent laser
radiation, diffraction-limited marks or holes, each
representing one bit of information, are permanently evaporated in a track pattern in the recording medium as the medium and mounting
drum rotate under a focusing microscope objective. Thus, parallel data tracks are recorded
transversely along the recording medium . .
The major parameters which must be considered in the design of a Laser Recording Unit
are:
( 1 ) Optical mode of laser beam.
1369
1370
Fall J 'Oint C'Omputer C'Onference, 1968
(2) .Diameter and divergence angle 'Of the
beam.
(3) Diffracti'On limits of the optical system
which images the laser aperture 'On the
rec'Ording medium.1
(4) The therm'Odynamics 'Of the h'Ole-f'Orming
vap'Orizati'On pr'Ocess.1 ,2,S
(5) The kinematics of the 'Optical scanning and
mechanical transP'Ort 'Of the rec'Ording
medium. s
(6) Characteristics of thin metallic films, deP'Osited 'Ont'O flexible substrates. 4
A typical emb'Odiment 'Of these principles is the
pr'Ot'Otype dem'Onstrat'Or unit in 'Operati'On at the
Research Lab'Orat'Ory 'Of the Precisi'On Instrument
C'Ompany since January 29, 1968 (see Figure 1).
The rec'Ording/repr'Oducing laser is a cw arg'On
II i'Onic laser 'Operating in' zer'O-'Order. single-m'Ode
(TEMoo) at a maximum P'Ower 'Of 'One watt 'Over
all wavelengths. The wavelength 'Of 4880 A has
a maximum intensity of 0.40 watt and is separated fr'Om the t'Otal 'Output of the laser by means
'Of multiple-layer dielectric filtering,
The light beam emitted fr'Om the laser passes
thr'Ough a ~ NBS-calibrated therm'Opile t'O determine the t'Otal emitted laser P'Ower and enters
the electr'O-'Optical m'Odulat'Or which is a P'Ockel's
cell, which pr'Ovides changes 'Of the refractive
index 'Of the m'Odulat'Or medium (KD*P) as a
function 'Of the sine 'Of the applied electric field
intensity. The physical c'Onfigurati'On 'Of this P'Orti'On 'Of the equipment is sh'Own in Figure 2.
FIGURE 1
FIGURE 2
,After passing the electr'O-optical m'Odulat'Or and
adjacent P'Olarizati'On analyzer (Glan prism), the
laser beam enters track widening 'Optics which
include a beam f'Older and an aspheric reflect'Or
spreading the wavefr'Ont 'Of the laser beam in
'One dimensi'On. Thereafter, the laser beam passes
an 'Optical beam splitter which separates the beam
incident t'O the rec'Ording medium fr'Om the beam
reflected. A perisc'Ope adj usts the laser. height t'O
that 'Of the rec'Order S'O that the laser beam reaches
the mirr'Or 'Of the tracking galvan'Ometer. The
light reflected back fr'Om the rec'Ording medium
returns again t'O the 'Optical beam splitter, yielding tW'O separate beams f'Or ph'Ot'Oelectric signal
detecti'On and err'Or detecti'On, respectively. The
appearance 'Of this P'Orti'On 'Of the equipment is
sh'Own in Figure 3.
The recording/repr'Oducing pr'Ocess may be interpreted as f'Oll'Ows. Assuming a laser beam is
incident t'O the rec'Ording medium at a relative
intensity level 'Of 100 percent, reflection and diffracti'On 'Of the beam 'Occur at the medium. In
the absence 'Of a rec'Ording, appr'Oximately 50 percent 'Of the incident laser P'Ower is reflected back
t'Owards the incident laser directi'On. Assuming
n'Ow the incident laser intensity t'O be str'Ong
en'Ough t'O vap'Orize a diffracti'On-limited secti'On
of the rec'Ording medium, during the rec'Ording
pr'Ocess the reflectivity 'Of this area is reduced
fr'Om 50 percent d'Own to five percent. Hence,
separati'On 'Of incident and reflected light in the
path 'Of the laser beam, utilizing a beam splitter,
yields an intensity variati'On 'Of the reflected signal
between 50 percent and five percent, thus pr'Oducing the necessary ph'Ot'Oelectric signal 'Output
Laser Recording Unit
1371
INCIDENT LASER INTENSITY
UNIDENSITY MEDIUM
100%
REFLECTED LASER INTENSITY
50%
5%
UNIDENSITY MEDIUM
FIGURE 4
FIGURE 3
for reproducing. Figure 4 is a diagram indicating
this relationship.
. Figure 5 is a block diagram of the equipment
used with the prototype Laser Recording Unit to
produce test recordings and evaluate retrieval
capabilities. In operation, an unrecorded region
suitable for ten or more data tracks is manually
set up on the record strip surface. For each track
to be recorded, a known arbitrary number is set
int'O the manual count selector switches. The
unit is placed in record m'Ode and, when a drumactuated home signal nevt occurs, the data are recorded 'On the selected track. To verify retrieval,
the tracking servo is commanded t'O f'Ollow this
recorded track and repeatedly read out the data
thereon. The output of the data sense system is
then transmitted to the data 'Output counter, during each drum revolution, and, upon completion
of the track readout, this value is transmitted to
a parallel identity comparator, to be matched
against the state 'Of the count selector switches.
Each time an error occurs, as indicated by fail-
ure of identity comparison, a count is transmitted
to an error counter.
A typical count entered on a data track is ab'Out
5,000 repeated data bit patterns. With the drum
operating at a nominal rate of 30 RPS, the unit
in read m'Ode will repeatedly read and check ab'Out
150,000 such bit patterns per second. Repeated
runs over. a period 'Of several weeks established an
average of about 700 seconds of 'Operati'On between
errors, or an error of ab'Out one in 108 bits.
High density data storage system
Such a system is comp'Osed of a Laser Recording Unit and a Recorder Control Subsystem and
is typically operated as a peripheral device to a
large computing or data processing system.
Laser recording unit
The Laser Recording Unit functionally is a rotating memory with a single movable head for
permanent· data recording and nondestructive data
reproduction. The standard recording-medium
strip used with the device is approximately 4.75 by
1372
Fall Joint Computer Conference, 1968
I
Home and Clock.si nals
cording medium strips are provided with a protective package called a PI Strip Pack. The Strip
Pack for a standard record strip is approximately
5.0 by 32.0 by 0.25 inches in size.
Figure 6 is a perspective view of the proposed
physical design for a production model of the
High Density Storage System incorporating a
Laser Recording Unit, configured for use in a
computing room environment.
Figure 7 is the overall Laser Recording Unit
block diagram. It illustrates the major equipment
groups necessary to guarantee subsyst~m performance. The track-position and carriage-position servos ensure proper positioning of the read
and record laser beam. The focus position control
group maintains proper objective lens focus position over the full drum width. Laser recording
power level is maintained by the laser intensity
control group which also provides attenuation of
the laser power for the Read Mode. The control
logic group provides synchronizati'On, sequencing,
Track Select order
FIGURE 5
31.25 by 0.01 inches in size; it is wrapped lengthwise around a drum and held down by combined
Inechanical and vacuum means to provide a precision cylindrical recording surface.
Each standard recording-medium strip can provide a total net data capacity of 1.96 X 109 bits,
or 245 million bytes. This capacity will be provided with a bit-cell size of four microns, allowing
~J bit density of 6,350 bits per inch along each data
track and thus approximately 198,500 bits per
track; a center-to-center track spacing of eight
microns will provide a track density of 3,175
tracks per inch of recording-medium width. Since
about 11 percent of the recorded bits will be used
for clocking and control purposes, about' 175,000
bits per track will represent the net data-recording capacity. With about 11,200 tracks recorded
on each strip, the total net data capacity of the
strip will be 1.96 X 109 bits or 245 million bytes.
For this standard record strip a data transfer
rate of 4 million bits, or 500,000 bytes per second
can be .obtained at a drum rotation speed of 22.9
rps (43.5 milliseconds per revolution). This configuration provides a bit error rate of approximately 'One bit in 108 data bits.
For convenient storage anq handling, the re-
B. Cover and Doors Removed
FIGURE 6
Laser Recording Unit
and selection signals for automatic internal control
of the subsystem, as well as input/output interface
to the Recorder Control Subsystem.
The drum motor servo speed control group provides precise control of record/read drum rotational velocity. The maintenance panel provides
controls, indicators, and meters required for
routine maintenance and calibration. The data
sense group provides media and record verification, as well as data readout. Figures 8A thr'Ough
8D are block diagrams depicting the functions 'Of
the above groups._
1373
P'Orts the preCISI'On m'Ounting plate, which pr'Ovides for the mounting of the laser and 'Optics.
The top of this cabinet is structurally reinforced
t'O accept the shock mounts holding the precisi'On
plate. The base is sufficiently strong to permit the
use of a fork lift for moving the laser recorder
console. The cabinet consists of four 19-inch
standard bays with removable c'Overs or both front
and back access. The bay itself is 96 inches long by
32 inches high by 34 inches deep. The strip-pack
loading surface is located approximately 38 inches
from the floor, and the overall dust c'Over maximum height is 56 inches from the fl'Oor, providing
a convenient strip-pack loading height for a standing operator. (Reference Figure 6A.) The laser
P'Ower supply and heat exchange (used for cooling
Electronics enclosure
The electronics enclosure is located in the laser
recorder console cabinet. The cabinet als'O sup-
FIGURE 7
$.--------=-
Trock
'Olition
AnIIv_
I
1
1
'olori•.,
1;------I I
1 1
I I
1
MonitarFunctioni
From Verioul Groupl
~
L.:=.J
",R_~V"ilica~tion~),~
r----~----'~~~---~
,-_. __
Dota_
Group
,-,l
r - - = " . ' " Verification
ReodDo..
~
I
I."
1374
Fall Joint Computer Conference, 1968
the laser head) will be located in a separate cabinet (not shown.) The space provided in the console cabinet of the Laser Recording Unit is used
for the packaging of the signal and contr'Ol electronics required by the laser recorder, the Recorder Control Subsystem, and the cooling and
air-filtration system required for the console (Le.,
dust removal in the optical area).
Recorder control subsystem
The Recorder Control Subsystem is physically
packaged as part of the Laser Recording Unit. A
block diagram of the subsystem is shown in Figure
9. The major element of the sUbsystem is a special-purpose programmed processor. One output of
this processor is to the data channel interface unit
of the specified main computing system of which
the High Density Storage System is a peripheral
device. Other interfaces are to local peripherals
of the programmed processor. A final and important interface is to the Laser Recording Unit
itself. A block diagram of this interface is shown
in Figure 10.
The Laser Recording Unit recording process is
.conducted 'On a serial bit-by-bit basis which requires that information transmitted from the Recorder Control Subsystem for recording be not
'Only serialized, but also logically interleaved with
two auxiliary signals; the clock and verify signals.
The principal objective of the clock is to place,
with the stored information, a timing reference
for retrieval synchronization. The verify signals
will be of two types: the segment (16-hit) verify
signal which determines the recording validity of
FIGURE 8
-
Commond
Pooitionlne
!tom
FormItControi '.'
_ _ Troc:k
"mon·B....
,_Errod
r=- f
.....
N ...........,•
~I"'_""'''-'-''''
~--==----.,.
-~ .... l_===--I
T......,
=-"-'
Laser Recording Unit
the preceding data segment, and the check sum
verify signal, which is a two-character (16-bit)
character-oriented accumulated sum verification
for each 256-character string.
During retrieval, the Recorder Control Subsystem is required to: (1) determine validity and
destination of retrieved in,formation; (2) perform
remedial actions and rettirn to normal operation
after completion of such .actions; and (3) logically
remove all clocks, verify' and check-sum bits from
the serial data while maintaining smoothness of
data flow.
Since the function of the Recorder Control Subsystem is to provide commu:t;tications between the
controlling computer complex and the Laser Recording Unit, it is this unit which must be adaptable to the interface requirements imposed by
1375
various computers. The Recorder Control Subsystem will accommodate various computer input/
output requirements by changing the input· interface and the control programs in the programmed
processor unit. The remainder of the Recorder
Control Subsystem will remain virtually unchanged regardless of the computer complex
utilized.
Since a major goal in the design of the Laser
Recording Unit-and Gonsequently the Recorder
Control Subsystem-is to provide a structure with
maximum dependability, additional auxiliary logic
is included in the Recorder Control Subsystem to
perform a thorough closed-loop .diagnostic test of
all logical features and characteristics.
During a diagnostic mode, the auxiliary diagnostic logic sets up a logic configuration simulating
FIGURE 9
~-~lDa~~&;".m- -
I
II
I
I
I
I
I
IL___
~~-------Arithmetic Section
--------,I
~tlS
I
--,
0:
PI-!,"7RIW:
....OT
... "";,
I
I
I
I
I
I
I
__.J
r~~~~_~:----~--------I
I
I
I rr======;)
I
1376
Fall Joint Computer Conference, 1968
FIGURE 10
-----,
I
I
I
I
I
I
.b . .
=logical value of d~ta
bit to be recorded
b r = logical value recorded
Data Retrieved
Laser Recording Unit
a recording-reading operation; i.e., as data are received from the data channel, they follow a normal-sequence recording path; however, the data
transmission is diverted from the Laser Recording
Unit and instead follows a closed loop within the
Recorder Control Subsystem. A simulated retrieval is performed in essentially every respect, which
concludes with the data being sent back to the
computer to be examined for evaluati'On of Recorder Control Subsystem operation. After successful completion of this diagnostic procedure, a
further procedure for test of the Laser Recording
Unit may be initiated. With the aid 'Of an operator, PI strip packs may be inserted in the Laser
Recording Unit under order of a diagnostic program, known synthetic data recorded, and then
successfully read back for a diagnostic check of
the complete Laser Recording Unit.
Recorded data format
The data recorded by the Laser Recording Unit
will be placed on the high-density recording medium through incident coherent laser radiation,
causing diffraction-limited holes to be permanently
evaporated in the recording medium in a pattern
which represents the binary input data.
The recorded data will be placed in tracks rUll:ning parallel to the length of the medium. In a
typical organization of the recorded data, these
tracks will be separated by an S.O-micron centerto-center spacing: this will allow over 3000 tracks
per inch of medium width. The data bits to be
written along these tracks will be spaced on 4.0micron centers thus allowing for about 2.0 X 105
bits to be recorded on any given track. A section
FIGURE 11
of typical laser recording, greatly enlarged, is
shown in Figure 11.
A prime consideration associated with such a
recording technique is the format or organization .
of the data so recorded. A format control portion
of the Recorder Control Subsystem controls the
format of the data as they are recorded.
Figure 12 illustrates the track-'Oriented recording organization employed to combine ali auxiliary
recording signals, such as time-synchronizing
pulses, diagnostic patterns, and track identification with the data to be recorded from the computer data channel. The following paragraphs
describe the various areas shown in Figure 12 for
a typical data track.
Timing synchronizing sector
The timing synchronizing sector will be recorded with two alternating patterns; namely, all
ones and character-separated ones. The initial all
ones are employed to accelerate the synchronism
of the read clock with a voltage-controlled clock
(VCC) by performing repeated comparisons to
FIGURE 12
f
D,u Bloc.
"'
~.
J
o.ta Block V.lid Chara..'ttr$
o.u Btock V.lid CNr'Ktm
In 128 Two-Chlraaer Segments
in 128 Two-Character Segments
5, .T V
010101 .. ..010
f:J
1377
4~tK.
S,T
~
J
.• SooT V
}-,
II
Lf
:
Segment 128
S,. .
S, T
50· .
S" T
vi
C1 • . • . C.T C., ... C I • TV
1378
Fall Joint Computer Conference, 1968
accurately measure their time occurrence difference, thus generating a fine control 'Of the VCC
period. The character-oriented clocks will be compared with a counted-down clock derived from the
voltage-controlled oscillator clock to establish a
synchronism within longer intervals and generate
a secondary feedback quantity to obtain furtber
VCC period control adjustments, if necessary.
Other formats
It can be seen that a data track may be divided
into separate sectors with capability of acquisition
of track at each sector-start point, rather than for
an entire track. Many such modifications may be
implemented, depending on record size and format
of input data.
PI strip pack
Diagnostic pattern
After timing synchronizing patterns 'are recorded, a diagnostic pattern will be recorded. This
diagnostic pattern will be employed to determine
if the retrieval logic structure is performing correctly (Le., data retrieval, holding, verification,
data stripping, and transmission are exercised by
the diagnostic pattern to search for any probable
logic or circuit anomalies).
Track identification
A track identification number will be recorded to
aid in determining the location of a selected track
during data retrieval. During recording, if frequent errors occur, remedial action will be initiated which will record an identical track identification pattern in the adjacent track and repeat the
core memory block transfer into the newly identified track. During reading, the search for a track
position is greatly aided by the track-identification
patterns which will avoid ambiguous track determination.
The flexible mylar high-density recording medium strip, which is 4.75 inches wide by 31.25
inches long by 0.010 inch thick, is contained in its
strip pack, which is 32 inches long by 5 inches
wide by 0.25 inch thick (Ref. Figure 13). The
Strip Pack contains edge index slots which prevent
the data surface of the recording medium from
contacting the Strip Pack's protective surface.
Protective caps seal each end of the Strip Pack.
The recording medium may be inserted from
either end.
.... 6, ..
Los. -.J
--ll-
--..j
~1--.Ol0"
1---",.61" ~
End Cap
II
T
Data block
The data block will be a block of information
which contains the actual data to be recorded from
magnetic tape. This block will be of length equal
to 128 16-bit verified segments (Le., if a 16-bit
segment verify position indicates an error within
the segment occurred during recording, this segment is considered invalid or nonexistent).
31.25"
- - 1-1-8.0."
Typ
Track
Spacing
32"
Check sum
The check sum locations contain an algebraic
sum derived by a process of repeated additions of
the values of the recorded valid segments. The
algebraic check sum is a 16-bit segment which will
be transmitted to the computer only during diagnostic modes. During reading, the retrieved check
sum will be compared with a calculated check sum.
End Cap
b~~~
I· ~ Area
l
High Density
Recording Medium
Storage
Strip Pack
FIGURE 13
l_~
Laser Recording Unit
System capabilities
Loading
Since the recQrd strips are demQuntable, any
number 'Of recQrd strips can be used tQ CQmpQse
a mass data file. TQ access a blQck 'Of data in such
a file, the PI Strip Pack cQntaining the recQrd
strip that hQlds the required data must be identified. Typically, this actiQn is perfQrmed by the
data-prQcessing system 'Of which the Laser Rec'Ording Unit is a peripheral device: the actiQn is
initiated by an input request, which is fQllQwed
by cQmputer lQQkup in an index file and then a
printQut 'Or display fQr an QperatQr. The QperatQr
then selects the requested strip pack frQm file and
places it 'On the Laser Rec'Ording Unit in readiness
fQr lQading.
The Laser Rec'Ording Unit autQmatically lQads
the recQrd strip QntQ the drum surface and confirms that the requested recQrd strip is cQrrectly
IQaded. N ext, a mechanical carriage-PQsitioning
unit, 'Operating under serVQ CQntrQl, translates the
recQrd/reprQduce head tQ the apprQximate track
address requested by the c'Omputer. Finally, an
'Optical tracking serVQ selects the exact track desired; when the start PQsitiQn fQr the requested
data recQrd is reached, data transfer 'Occurs and
cQntinues at the 500 kilQbyte rate (except fQr sh'Ort
gap times) 'Over all sequential tracks cQntaining
the requested data.
On the basis 'Of evidence frQm experiments invQlving repeated lQading and unlQading 'Of recQrd
strips 'On a breadbQard mQdel 'Of the drum mechanism, it is expected that a particular recQrd strip
repeatedly accessed and IQaded will return tQ the
same positiQn 'On the drum periphery within. 2
Mils 'Or apprQximately 50 MicrQns, maximum.
This is well, within the tracking range 'Of the galvanQmeter serVQ.
The strip-1Qading prQcess requires abQut 15 secQnds after the QperatQr places the requested strip
pack in the IQad slide 'Of the Laser Rec'Ording Unit.
HQwever, after a selected recQrd strip is lQaded
QntQ the drum, access t'O each additiQnal blQck 'Of
data 'On the same strip can take place in less than
400 millisecQnds.
1379
tiQn the track access mechanism 'On the LRU tQ
the track cQntaining a specified recQrd 'On an already mQunted and rQtating recQrd strip.
In the LRU, the recQrd/read head is PQsitiQned
tQ the selected track by a carriage PQsitiQn servo.
This unit uses a linear mechanical carriage which
is supported by precisiQn ball bushings and driven
frQm a serVQ mQt'Or, thrQugh a precisiQn steel belt.
A linear incremental encQder plate prQvides PQsitiQn inputs. FQr this mechanism, the maximum
carriage-PQsitiQning time tQ mQve frQm track 1 tQ
track 11,200 'On the recQrd strip is less than 400
millisecQnds. The minimum access time t'O mQve
tQ the adjacent sequential track is less than tWQ
millisecQnds, and the QperatiQn can be acc'Omplished during the gap time at the end 'Of each
track 'On the recQrd strip.
Head selectiQn time
The LR U has a single recQrd/read head mounted 'On an 'Optical tracking serVQ. UpQn arrival of
the mechanical PQsitiQner tQ within tWQ mils 'Of
the desired track IQcatiQn, the galvanQmeter-cQntrQlling 'Optical tracking serv'O will access the track
at the center 'Of the field t'O the 'Objective lens.
This field is 'Of the 'Order 'Of 100-'200 micrQns and
will CQver 10 to 25 tracks, depending 'On recQrding
density.
At N PQints arQund each track the track address
number will be recQrded, and an 'Optical tachQmeter 'On the drum will indicate these IQcatiQns
'Or sectQrs. Within l/N revQlution, the track address will be determined.
Due to possible PQsitioningerr'Or in the carriage
mechanism, the track initially accessed by the
'Optical serVQ may be 'One or tWQ tracks distant
frQm the track actually addressed. If the accessed
track address is wrong, the 'Optical servo thEm
slews to the cQrrect track; again a wait equivalent
tQ l/N 'Of a drum revolution may be required to
cQnfirm the address. If the specified data were
passed in the process, a rQtational delay ensues.
The galvanQmeter has a PQsitioning accuracy 'Of
'One micrQn and requires abQut tWQ millisecQnds
slew time tQ reach the new track.
RQtatiQnal delay
Timing
Access mQtiQn time
Access mQtiQn time is the time required t'O PQsi-
RQtatiQnal delay is the time required after the
proper track is reached fQr the correct data tQ
rQtate to the read/write head for the start 'Of data
transfer.
1380
Fall Joint Computer Conference, 1968
Assume the LR U device described above has
just entered one sector of the specified track and
determined that the track address was correct. If
the sector contains the desired data, data may be
read out immediately.
If the device has entered the wrong sector, the
addressed data will be in one of the other sectors
of the track, since the machine is on the correct
track. Thus, a maximum rotational delay can occur equivalent to (N-l)/N percent of a drum revolution. With N =8 and a nominal revolution time
of 43.5 milliseconds, there is a total possible maximum lapse of 51 milliseconds for head selection
and rotational delay.
File updating
Since the Laser Recording Unit is a permanent
recording device, with nondestructive read, data
once written cannot be erased and rewritten as in
a magnetic memory. For a large direct access file
one convenient organization is that the file master
index in key number order be stored on disc pack
units under control of the main processor. When
it is desired to delete or modify a record in the
mass store, the record data are pulled out to the
core memory in the recorder control unit, the data
modification made, and the entire record rewritten
at a new vacant location on the LRU record meclium. The new track address is then placed in the
disc-mounted index in. place of the obsolete address, and this data item will be thereafter accessed at the new location in the mass store.
Where a data record has continuing transactions, which do not obsolete the remainder of the
record, at the time of initially placing this record
into the mass store, blank spaces may be left, and
a local address stored in the disc-mounted index.
Then when a transaction is to be added to a mass
store record, the address is read from disc, incremented by one and returned, and the mass file
track and sector address read, access obtained,
local address used to count down the record, and
the new transaction written. This may be repeated
until the local address regions initially allocated
to this record are all filled. Then, either a transfer
address to a new.mass store track may be utilized
for continuation of the record, or the procedure
of completely transferring the record to a new location in the mass file may be used.
In a system which contains more than one LRU,
the mass file may from time to time have all obsolete material deleted, by passing through the
current disc index in key order, and rewriting
only those portions of the original mass file which
are currently accessible. Also, a special mark or
code can be placed on any data record in the mass
store to cause the readout system to ignore this
data, in a manner similar to that used for readwhile-write data validation in which any write
error causes the data to be marked as invalid, and
the recording repeated.
REFERENCES
1 CHBECKER
(TN ICON-Coherent light data prucessing
Instrument Society of America 21st Annual ISA Conference
October 1966 Section 1613-1-66 pp 1-12
2 JFREADY
Effects due to absorption of laser radiation
Journal of Applied PhYRics Vol 36 No 2 February 1965
:) CHBECKER
US Patents 3,314,07:~; 3,314,074; :3,314,075
4 0 S HEAVENS
JJ[easurement of optical constants of thin .films
p 193
.J T COX G HASS
Antireflection coatings for uptical and infrared optical materials
p23H
Physies of Thin Films Vol 2 1H64 Aca.demic Press
A random access terabit mag~etic memory
by s. DAMRON, J. LUCAS,* J. MILLER,
E. SALBU and M. WILD MANN
Ampex Corporation
Redwood City, California
INTRODUCTION
The storag,e of large amounts of information will,
for the foreseeable future, consist of storage on
a surface. At prese:nt, magnetic surfaces are most
widely used, although silver halide surfaces are
also finding some limited application where the
non-erasability is not a serious limitation. Other
media now in the laboratory will undoubtedly find
practical use. The problem facing the large memory designer is one of choosing a suitable medium
and determining a way of breaking up this surface
to make it accessible.
If it is desired to have a memory that can be
updated, an erasable surface is imperative, and
we are therefore limited, at present to magnetic
surfaces. With a magnetic surface, storage densities in the order of one million bits per square
inch are feasible at present or will be available
in the near future. With this packing density,
storage of 1012 bits will require one million
square inches. (This is approximately one-sixth
of an acre, or the size of an average suburban
building lot.)
The choice of a suitable medium, with the imposed constraint of erasability, was relatively
easy. How to break up this surface for ease of
access. is a somewhat more difficult problem. However, the storage of information for computers is
really not diff,erent from the storage of any other
information-a problem which has confronted
mankind since the invention of writing. Throughout history three principal methods of providing
Rurfaces for writing have been used: solid sur• Department of Defense
1381
faces in the stone age and for monuments; flexible
surfaces' in the form of sheets as in most bO,oks.
In computers, these same three forms can also
be found. .D·isc and drum files use solid surfaces.
Their advantage lies in comparatively rapid access and in comparatively fixed position of the
stored bits. Howev~r, their volumetric efficiency,
i.e., the number of bits per cubic inch, is low. A
reel of magnetic tape is the modern equivalent of
ancient scrolls;' access is slower, the medium
stretches, but the volumetric efficiency is the best
of any digital storage unit. Magnetic strip files
can be compared to books or file folders. Both access and volumetric efficiency are between those of
discs and reels of tapes. Since storage on a flexible
medium has the advantage of high volumetric efficiency, and since erasability and reusability are
possible with iron-oxide coated polyester film, this
medium seems to be the ~bvious choice for a large
memory.
Magnetic tape on reels has the disadvantage that
a'relatively long time is required to move from an
address at one end of a tape to an address at the
other end. However, if sufficiently high tape
speeds and paCKing densities can be achieved, this
djsadvantage is less severe and tapes therefore
become a very attractive storage medium.
Laboratory developments completed prior to the
initiation of the program described here demonstrated that tape speeds well in excess of 1000
inches per second (ips) and packing densities of
Cone million bits per square inch, with high data
reliability,' were feasible.. Using these developments as a basis, a large memory system could
therefore be designed. A prototype "small" system with a total storage capacity of 101.1 bits has
1382
Fall Joint Computer Conference, 1968
been built and tested. The following is a description of such a system and its major components.
T BM* system description
The TBM (terabit memory, i.e., 1012 bit memory) random access memory uses magnetic tape as
a basic storage medium. Random access is provided by using tape search speeds of 1000 ips
(compared to approximately 300 ips used on conventional transports) and by using packing densities of 700,000 bits per square inch (compared
to approximately 14,000 bits/in. 2 for standard
computer tape transports). Data recording is
done in the transverse mode (to the direction of
tape motion) using rotating heads, the technique
used for video recording. A, redundant recording
scheme permits the achievement of error rates of
two errors in 1010 information bits. The salient
features of the tape transport, permitting this
high search speed, and of the recording mode and
associated data channels, permitting this high
packing density, will be considered in detail following the system description.
A block diagram of a typical TBM memory system ·is given in Figure 1. The memory system is
composed of four major building blocks: 1) the
tape transport, 2) the transport controller, 3) the
TBM controller, and 4) the digital signal channels. In addition to these main components, buffers between the memory and the central processor
are usually required. Furthermore, a' switching
matrix has to be provIded between the transport
controller and the transports, to permit operation
ef each transport from anyone of the controllers,
Simila-rly, a switching matrix between the transports and the signal channels has to be provided
to permit the signal -channels to be connected to
each of the transports.
The tape transport contains the components'
necessary to move the tape (reels, capstans, and
vacuum chambers), address read and write heads,
digital data erase head, auxiliary heads for the
control of tape,. and rotary digital read and write
heads. Vacuum chamber tape position sensor and
signal preamplifiers are also provided. Only those
functions which cannot be provided in the transport controller or in the digital signal channels
are incorporated in the transport. The transport
controller contains all the circuitry necessary for
control of a tape transport, i.e., the reel servo, the
capstan servo, the rotary head servo, as well as
... Trademark, Ampex Corporation
BUffER
DIC;fTAI. SIGNAl. CHAN NELS
TRANSPORTS
T l'
TRANSPORT CONTROLLERS
FIGURE I-Block diagram of TBM memory system
read-write circuitry and the main memory controller interface. The transport controller can be
used to operate anyone of the transports in the
system.
The memory controller is a small general-purpose digital computer. Its function is to provide
the command interface between a central processing unit, which is served by' the digital memory
described, and the various memory building blocks.
Because it is a general purpose digital computer,
it can be programmed to fill any number of functions specifically designed for any particular application.
The digital data channel accepts the digital input, which is then FM modulated and written in
that form on the tape. In reading, the FM data is
demodulated and reconstructed into digital format.
The read and write channels are independent.
This permits simultaneous reading and writing
on separate transports. Data erase is an independ~nt function, which does not require the data
A Random Access Terabit Magnetic Memory
channels. The data rate of each channel is 6 megabits per second.
In the transverse recording mode used, the data
is recorded across the width of the tape as shown
in Figure 2. In addition to the data, ir"formation
is also recorded longitudinally, i.e., along the direction of motion of the tape. Three longitudinal
channels are provided: (1) to record addresses
to identify data blocks; (2) a control track containing one pulse for each revolution of the rotating head. (This is primarily needed for operation
of the rotating head.) ; and (3) a tally track t'O
record auxiliary inf'Ormation, such as number 'Of
accesses to each data block, illegal addresses 'Or
addresses in which tape defects occurred, or t'O
identify data blocks which cann'Ot be erased. The
length of each data block is determined only by
the length of the longitudinal address on the address track. Data blocks are used which contain
one million bits, and use up 0.90 in. of the two
inch tape. Different block lengths, down to onequarter million bits and up to a full reel of tape,
may be used without requiring any hardware
change. Each data block can be individually
erased and recorded. Update consists of first
erasing and then re-recording as required. During high speed search, only the control, tally, and
. address tracks are read and the rotating transverse head is not in contact with the tape .. Tape
wear on the data channels is eliminated during
the search operation.
The system just described is completely modular; i.e., it is made up of a number of components
which can be combined in many different ways.
This modularity of the system has the following
Hdvantages:
Versatility
Different combinations of the basic main building blocks can provide different system character-
,,
Address
Data Tracks
,/
I
/
and Tally Tracks
T
I
)
\1
2"
/
\
~BIOCk
-1
~
\
\
Control Track
FIGURE 2-Tape format
1383
istics. Total system capacity can be greatly expanded with relatively little increase in system
cost by adding more transports. The number of
requests that can be answered per unit time by
a large memory is usually one of the most important characteristics of such a system. By using
more than one transport controller, several transports can be searched at the same time. This
simultaneous search operation allows a typical
system with five controllers to answer 1200 requests per hour, giving an average time per request of 3 seconds.
The independence of the read and write functions in the signal channel permits independent
read and write. For large systems, two data channels are usually required for housekeeping, such
as pre-recording of address and control tracks on
tapes, rewriting of used tapes, or aligning of new
heads without removing the entire system from
operation. These channels also provide redundancy.
Reliability
The modular construction of the system results
in complete redundancy of all the major building
blocks. In an electromechanical system it is the
mechanical components which usually exhibit the
lowest mean time between failures. This system
has only one mechanical component--the tape
transport. Because the tape transports are operated in parallel, and because complete switching
arrangement is provided both between the transport controllers and the transports, and between
the signal channels and the transports, failure of
a transport does not result in system failure. If
a spare transport is used, the downtime resulting
from a transport failure need only be the time
required to remove the tape and rotary head from
the failed transport and to mount them on the
spare. This is"an operation requiring, at most, five
minutes.
Redundancy is also provided in the digital signal recorded on the tape. Each bit is recorded
twice with a separation of approximately three-.
fourths inch between each recording. The m~jor
cause of data errors (tape defects) is thus eliminated because defects are small and rarely have
the required spatial relation to cause simultaneous dropouts. It is because of this redundancy
that the demonstrated error rate of less than two
errors in 10~() data bits can be obtained.
1384
Fall Joint Computer Conference, 1968
Each transport can accommodate up to 45,000
inches of tape, or about 5 X 101.0 bits of information. The system described here has the capability
of storing anywhere from 5 X 10]'0 bits for a single
transport system to 3X1012 bits for a 64 transport
system. Larger systems could, of course, be built,
but problems such as very large switching matrices and long cables might make such systems
unwieldy. To date, a "small" prototype 'Of a system containing two transports, one signal channel,
one transport controller, and one TBM controller has been built and tested. A small system
such as this (shown in Figure 3) has a total capacity of 1011 bits. This is the equivalent to the
capacity of approximately 1000 reels of conventional one-half inch computer tape, or of thirty
IBM '2321 Data Cells.
Component description
The two components novel to this system are
the transport and the data channel. Part of the
data channel is contained in the rotary head which
is mounted on each transport. The transport and
the data channels will now be described in detail.
Transport
The functions of the tape transport are, primarily, to move the tape at high speed for searching, to accelerate and decelerate the tape, and to
nlOve the tape accurately during data transfer.
A diagram of the transport is shown in Figure 4.
The configuration chosen for the transport has
FIGURE 3-Photograph of 1011 hit memory system
'Address, Control Track,
and Tally Track Heads
.'
FIGURE 4-Tape transport layout
the following advantages: With the vacuum
chambers arranged as shown, a small transport
package resu,lts, and two transports may be
mounted in one rack. The tape path is such that
all guide and capstan contact is on the Mylar side
of the tape only. Only the longitudinal control
track, address head, and rotary head contact the
oxide side 'Of the tape. Thus, no damage of the
data surfaces can occur from contact with the
guides or vacuum chambers. Furthermore, all
heads except the rotary head are air lubricated so
that, the only contact with the oxide occurs at the
rotary head during data transfer. All guides are
air lubricated to provide the low friction necessary
for successful high speed operation.
At the low speed required for data transfer, the
tape speed is controlled by the capstan (friction
between tape and capstan is enhanced by supplying vacuum to the capstan). Control at high speed
with the capstan is not possible because of entrapment of air between the capstan and the tape. To
permit operation at spe,eds at which such air entrapment would make capstan control impossible~
the tape is moved by allowing a difference in pressure between the two vacuum chambers to occur,
With this difference in pressure, the tape essentially "flows" from the high pressure to the Im~T
pressure chamber. Speed control in this mode is
provided by using the control track as a speed
reference and by servoing the difference in pressure between the two vacuum chambers to obtain
a constant speed.
A Random Access Terabit Magnetic Memory
Two transports are mounted in one rack with
room for switches or auxiliary air pressure and
vacuum suplies mounted at the bottom. A photograph of the two transport rack is shown in
Figure 5.
Data channels
The transvers'e recording technique was developed for video application in 1956. This method
of recording has several advantages over conven·
ti0l!al fixed-head recording techniques. It allows
high relative head-to-tape velocity while tape
speed is low. Thus, accurate speed control to prov'ide the necessary timebase accuracy is easily
,thieved. Because of the high head-to-tape velocii es, good signal levels, and therefore high signalo-noise ratios can be obtained with narrow tracks
which are compared in width to those used for
1385
disc recording. This results in high packing densities. Furthermore, high frequencies (up to 20
MHz with the present state of the art) can be
recorded and reproduced with good signal-to-noise
ratios.
A picture of a rotating head in contact with the
tape is shown in Figure 6. In addition to the ro·
tating head with the eight transducers, a tape with
the transverse data, longitudinal address, control
and tally tracks is shown. The detail of the data
tracks, as recorded on tape is shown in Figure 7.
The tape itself extends slightly moie than 90 degrees of the circumference of the rotating head
drum. With eight heads, separated by 45 degrees
each, a minimum of two heads are in contact with
the tape at all times. By providing the same signal
to the two heads which are in contact with the
tape simultaneously, all the information is recorded twice. This is also shown in Figure 7.
The data channel takes the digital data and
derives a frequency modulated signal from this
with a "zero" corresponding to 5.25 MHz and a
Air Lubricated
Ta~e
GUide
Transducers
Head Drum
FIGURE 6-Transverse scan rota.ting head and tape
Redunda01 Bus
FIGURE 5-Photograph of two-transport rack
FIGURE 7-Ta.pe format detail
COfItrolTrack.
1386
Fall J 'Oint CQmputer Conference, 1968
"'One" cQrresPQnding to 6.75 MHz. In addition tQ
these tWQ frequencies, a 500 KHz pilQt signal is
multiplexed QntQ the data and recQrded tQgether
with the data. Repr'OductiQn 'Of the data is dQne
by taking the signal individually frQm each 'Of the
tWQ redundant heads and using the pil'Ot reprQduced frQm tape t'O generate an errQr signal, when
cQmpared tQ the system clQck. This errQr signal
is used as input t'O the variable delay line, which
a.ccurately cQrrects the timebase 'Of the signal.
After timebase cQrrectiQn, the tW() signals are
c'Ombined; dr'OP'Out in 'One channel causes a 6 db
drQP in signal level, rather than a cQmplete lQSS
'Of signal.
In 'Order tQ provide a c'OntinuQus stream 'Of data,
rather than an intermittent 'One, each time 'One
rQtating head leaves the edge 'Of the tape and the
next 'One engages the 'Other ,edge 'Of the tape, there
is a small amQunt 'Of 'Overlap between the signal
recQrded by each head. In reprQducing the signal,
the signal level 'Of the head leaving the tape is
slowly decreased while the signal level 'Of the head
entering the tape is sl'Owly increased. The tW'O
signals, after timebase c'OrrectiQn, can then again
be cQmbined, prQviding a c'Ontinu'Ous signal without switching transients. A detailed descripti'On 'Of
the signal system is bey'Ond the SCQpe 'Of this paper.
.A descripti'On will be fDund, h'Owever, in reference
1*.
The signal system just described is 'Obvi'Ously
the heart 'Of the memory system. It permits rec'Ording 'Of data with a packing density 'Of 1.4X106
bits/in. 2 The data rate is 6 megabits/sec. Intreasing this data rate t'O 10 'Or, even 20 megabits/
sec is feasible. Higher packing densities of up tQ
2 million bits/in. 2 als'O appear tQ be PQssible.
Data accuracy measurements have been made
by recording a pseud'O-rand'Om pattern 'On the tape,
reprQducing the data, and cQmparing this data t'O
the recQrded data 'On a bit-by-bit basis. After
eliminating all permanent err'Ors which were repeatable at 'One lQcation of the tape, the resulting
data rate was 1.8 err'Ors in 1010 bits 'Of data. A
total 'Of slightly less than 1012 bits was recQrded
and repr'Oduced tQ test the data accuracy 'Of the
signal system.
WithQut the dual channel feature, the err'Or rate
is in the 'Order 'Of 'One err'Or per 106 bits of data.
*E. Kietz, "Transient-Free and Time-Stable Signal Reproduction from Rotating Head Recorders." Record, IEEE Tech. Grp.
on Space Elect. and Telemetry, 1963.
The amount of tape that has to be cQnsidered as
useless because 'Of drQPQuts amQunts tQ abQut
0.1 % 'Of the tQtal tape tested. This is acc'Omplished
by identifying certain addresses illegal. The system perfQrmance is nQt degraded by removal 'Of
such a small percentage 'Of storage area.
System specifications
Because the system is mQdularit is PQssible tQ
generate a large number 'Of systems specifications
t'O meet a variety 'Of applicati'Ons. The f'OllQwing
specifications were prepared tQ meet a typical 1012
bit applicatiQn:
Storage capacity
N umber 'Of transPQrts
Tape per transPQrt
N umber 'Of transport
cQntrQllers
Requests per hQur
Average time per
request
Data transfer rate
Bl9Ck length
1012 bits
36
30,000 inches
5
1,200
3 sec
6 X 106 bits/sec
106 bits
TWQ other cQnsideratiQns which enter intQ the
. useful measure 'Of a system are tape life and rotary head life. Address and erase heads, being
air lubricated, d'O nQt wear 'Out. Because 'Of the
high data rate, the transfer 'Of each typical data
block 'Of 'One milli'On bits requires 1/6 secQnd CQntact between the head and the tape. Of the average
time per request 'Of 3 secQnds, the head is in c'Ontact with the tape . 'Only abQut 1/18 'Of the t'Otal
time. With a large number Q~ transPQrts, the actual c'Ontact time per head is even further reduced,
S'O that in a 36 transPQrt system, ea'ch head WQuld,
1
. 'OT
3X6X36
1/648 'Of the 'Operating time 'Of the system if 'One
data channel is used. Head life 'Of 100 h'Ours in
contact can reliably be 'Obtained, S'O that system
head life 'Of 'Over 64,800 hQurs can be expected.
Data deteriQrati'On due tQ wear 'Of the tape 'Occurs s'Omewhat faster. Experience has shQwn that
at least 1000 data transfer passes can reliably be
'Obtained. Remember that n'O contact 'Occurs during search. In a large system there shQuld be nQ
data blocks which are frequently used. Such blQcks
shQuld be stQred elsewhere in the system. The
purpQse of the tally track is t'O keep CQunt 'Of the
'On the average, be in c'Ontact 'Only
A Random Access Terabit Magnetic Memory
number of accesses on each block so that excessive
use can be identified.
inter/acing
Interfacing the TBM 'system to a typical general-purpose computer requires two interfaces:
command and control, and data. The command
and control interface with the memory controller
is fairly straightforward and consists of several
simple commands, such as "write address," "control track," "write digital data," "read digital
data," "search for address," "erase digital data,"
"abort last command," and "return control to local
command." The data interface. can be handled by
providing for the output of the memory system to
go directly into the central processor core memory.
However, because of the large data blocks involved, sufficient core memory capacity is usually
1387
not available and provision of a buffer between the
memory and the central processor is therefore required. A small disc or drum is a suitable buffer.
In order to avoid the difficulties involved in matching two mechanical devices, such as a tape transport and a drum or disc, a small core-type buffer
between the two is necessary. Many other suitable
schemes can be visualized.
CONCLUSION
The TBM memory system described, provides a
greater capacity than any memory presently available in the marketplace and is based on existing,
well developed technology, some of which has been
used for ten years. Applications for this system
will be found in. many computer installations
which have large tape libraries because of cost
savings, and for large memory stores which should
operate on-line.
Dynamic recovery techniqes guarantee
system reliability
by D. P. GUSTLIN and D. D. PRENTICE
International Business Machines Corporation
San Jose, California
INTRODUCTION
The IBM 1360 Photo-Digital Storage System,
shown in Figure 1, is capable in its present form
of storing up to 2.38 X 1012 data bits on-line to the
main processor. Currently, there are two systems
installed, both being less than the maximum configuration. One system is located at the AEC
Lawrence Radiation Laboratory, Livermore, California (1.02 X 1012 bit capacity), and the other
at the AEC Lawrence Radiation Laboratory,
Berkeley, California (3.4 X 1011 bit capacity). In
this paper, any specific consideration will refer to
the Livermore system, because its larger size tends
to better illustrate system complexity and related
recovery procedures.
Immense storage capacity in the IBM 1360 is
achieved by high-density recording in two· dimensions 011 silver-halide photographic-film chips
(4.7 X 106 bits per chip) and by the storage of 32
chips in 1.1 by 1.6 by 3.0 inch containers, or ceUs
(1.51 X 108 bits per cell), which reside remote
from the reading device. Figure 2 shows a cell
containing chips. The cells are brought to the
reader under automatic control in response to
main processor commands. Writing is accomplished with an electron beam and reading with a
FIGURE I-IBM 1360 photo-digital storage system
1389
~
\~
~
~
.
\
\
STORAGE TRAY
SHIFTED TO
PERMIT CELL
RETRIEVAL
FIGURE 3-The file used for storing cells
FIGURE 2-Cell and chips. Note the arrangement of data
frames on the chip
cathode ray flying-spot scanner. Because of the
differing methods for writing and reading, the
write and read devices are separate and basically
dissimilar physical entities. The residence for cells
is called a file. A file is a five-tray array containing 2250 cells. See Figure 3. The write device and
the read devices (LRL-Livermore has two), or
terminals as they are referred to in the 1360, are
connected to the files (LRL-Livermore has three)
by a pneumatic transport system.
Overlapped processing operations
The time to move cells between a file and a terminal varies from 2.5 to 4 seconds. Of course, this
is ~ong compared to data processing time. To improve effective performance, the 1360 is designed
to provide simultaneous operation. For example,
one file can be restoring a cell to its resident compartment, a second file can be preparing to send
a cell to a terminal, and a cell can be moving in
the main pneumatics between a third file and some
terminal, all at the same time. Concurrently, one
reader can be actually reading and simultaneously
readying a second cell and, overlapped with these
operations, the other reader can be exchanging
chips between the completion 'Of 'One job and the
start of another. Further, the recorder may itself
be performing several 'Overlapped functions, such
as recording of a chip, on-line automatic chip developing, and extraction \ or return) 'Of chips from
(or to) cells.
This considerable complexity of overlapped
functions and the logical problems deriving from
the combinatorial p'Ossibilities 'Of operations at
any given instant made it imperative to find a
sophisticated methoq of device control. The result
was a decision to control the hardware with a
stored program process'Or, a slightly modified IBM
1801 which is the main memory and CPU 'Of the
IBM 1800 Data Acquisiti'On and Contr'Ol System.
Having decided t'O use a contr'Ol pr'Ocess'Or, it
seemed a reasonable extensi'On t'O have this process'Or assume many functi'Ons n'Ormally perf'Ormed
by circuitry. The pr'Ograms then c'Ontrol the hardware at a very detailed level, 'Or at what has been
termed the solenoid/sens'Or level. This simply
means that the program initiates an· acti'On by activating or deactivating a particular single s'Olen'Oid and determines hardware conditi'Ons by individually sensing the state 6f micr'Oswitches 'Or
photosens'Ors .. The processor used f'Or these actions is referred to as the contr'Ol process 'Or, and
the process'Or that uses the IBM 1360 as a storage
subsystem is called the h'Ost computer.
Advanta.ges and objectives
With respect to diagn'Ostics/automatic recovery,
Dynamic Recovery Techniques Guarantee System Reliability
the use of a control processor provides a fundamental advantage of making detailed information available in the event of a failure. The pro...
. grammed embodiment of the complex logic 'Of the
many operations makes it possible to know the
system environment in which the specific failure
occurred. The information available, together with
the intelligence of the processor, makes it possible
to perform specific yet flexible analysis and recovery beyond what has previously been feasible.
With these benefits accuring from a control
processor which has both intelligence and memory
(a 16K word core and a 512K word disc), certain
objectives become realizable in the area of diagnostics/automatic recovery, referred to subsequently as D/AR. The primary objectives are the
precise identification of a failure (intermittent or
solid), the automatic recovery from intermittent
failures to significantly increase system availability, and the provision 'Of a complete failure history
and sophisticated set of programs to aid the field
engineer to analyze and solve problem situations
and establish the valid operation of equipment
after repair without requiring program execution
time 'Or space in the host computer.
In order to elaborate on the accomplishment of
these objectives, it seems appropriate first to describe the general structure of the control programs and the related diagnostic procedures.
Organization of operations
Control design is founded on a conceptual organization of the equipment. In describing a complex mechanical/electronic device like the 1360, it
becomes apparent that there is a limited set of procedures which are termed operations. Each operation has the characteristic of being invariant as
to actions and their sequence, though in s'Ome cases
the action parameters such as time may be variable. For example, the length of time that air is
applied to move a cell out of a file is dependent on
the vertical distance the cell must travel in the
file. The subsystem functions which are available
to the host computer consist 'Of a set of sequences,
each sequence being a particular progression of
operations. To be initiated, an operation must encounter suitable hardware and system conditions.
As examples, a hardware conditi'On would be the
proper position of the load mechanism to accomplish a mechanical cell transfer, while a system
condition would be the ability to seize a pneumat-
1391
ics path before initiating hardware action that
would block that path.
The 'Operations represent the detail control and
detail knowledge level of the control programs.
The linkage points, in stringing operations to
make sequences, represent the environmental control and environmental knowledge level of the control programs.
Sets of operations and logic combining them into
sequences have been termed control strings. These
strings are totally re-entrant codes composed of
symbolic commands. There is an interpretive program called the string processor which examines
and actually executes the symbolic control commands. A number of transactions is possible in
the system at a given time, each transaction representing a cell-oriented request for action by the
host. The string processor defines and maintains
a program pointer for each transaction to indicate
its current location in a control string.
The baekground is now established to examine
the steps involved in D/AR and the means of accomplishing them.
D/AR structure
There are six clearly defined elements in the
.D/AR procedure:
1.
2.
3.
4.
5.
6.
Manifestation-detecting an abnormal condition.
System suspension-arresting the remainder
of the system under exact control to examine
the particular abnormality.
Analysis-investigating the abnormality to
determine its nature, location, and degree of
seriousness.
Automatic recovery-re-establishing proper
functioning, if possible.
Failure history-recording the detailed data
on all failures, whether or not recovery was
possible, for use by a field engineer.
System restoration-establishing the new
status of the system as a result of a failure
and the D/AR.
These steps are elaborated on below. A special
dass of recovery, read recovery, which does not
involve the steps above is also described.
Manifestation
Basically, control of an operation consists of
activate-time-sense, this being more or less com-
1392
Fall Joint Computer Conference, 1968
plex, depending on the particular operation. Once
the control string has determined that proper
hardware and system conditions exist, the operation is initiated. An action is started, such as engaging a clutch, lifting a detent, or opening a
valve. Most conditions are determined by program polling, rather than by an interrupt at action
completion. There are usually two times associated
with an action. The first is normal time, 'Or the interval after which the result of the action can be
expected. This time is used to avoid taking processor time to look immediately for the end of an
action that normally takes a finite time for completion. The second time, called tolerance, specifies
the limit for normal completion. The sense is, of
course, the determination that the appropriate
sensors reflect a successful completion of the action. B'Oth times are measured via system clocks.
Failure manifestation is defined, then, as failure
to successfully sense correct action completion
within the tolerance time. If such a failure occurs,
the string processor notes this fact by setting a
diagnostics request bit in the proper transaction
pointer, and the next step in the procedure is entered.
System suspension
An abnormality must be handled in such a manner that the valid control of the rest of the system
is not compromised. This is particularly important
in the 1360 which has many independent, overlapped functions. The method of bringing the system to a controlled suspension to devote resources
to D/ AR is based on the concept of operation and
interpretive control by the string processor. Since
an operation is discrete and invariant, it represents a necessary unit; that is, once initiated, it
must be carried to unhampered completion in order to be valid. The control string, then, upon initiating an operation, sets a pointer-oriented bit
called "stop-suppress," which is an indication to
the string processor that it is processing a noninterruptable 'Operation. On completion of the
operation, the stop-suppress bit is reset.
When a diagnostic request is made by a. pointer
with an abnormal condition, the string processor
thereafter allows processing only on pointers with
8,' stop-suppress bit set, c'Ontinuing in this mode
until all such bits are cleared. The arrival at this
state means that the entire system is in a legitim,.ate, suspended state, and. the· next step is begun.
Analysis
Analysis is, of course, the true diagnostic element. The diagnostic master program is called
and ,executed. Basic functions of the diagnostic
master are to save the failure data and system information, perform gross checks such as testing
the relevant component p'Ower supply, and determine which specific diagnostic program is required
and call it from the disk.
Each specific diagnostic program is related to
a particular time/sense failure and is therefore
able to further analyze the possible conditions associated with the failure. The usual result is entering the next step, automatic recovery, within
the diagnostic program. (The term real-time diagnostics is proper here because the 1360 system
analyzes itself without the knowledge or intervention of the host computer; and, in recoverable circumstances, the host experiences only a minor
time delay with no effect on the functions in process.)
Automati,c recovery
The definition of automatic recovery is the restoration of the subsystem, that is, the IBM 1360,
to proper operation by the subsystem itself without intervention by either the host computer or a
human. It is too early to provide reliable statistics
on the ratio of intermittent to solid failures, but
to date a large percentage of failures has been intermittent. The detailed knowledge of the failure
conditi'Ons and the resultant capability of having
very specialized recovery programs greatly enhances the ability to deal with intermittent failures. In its simpler form, automatic recovery involves retry. For example, the failure may have
been due to an intermittent malf}l~ction of a sensor, which then performs properly on a retry. An
extended f'Orm of automatic recovery may include
several retries at normal or subnormal speeds,
which may clear temporary conditions causing
nonserious, substandard mechanical performance.
Automatic recovery has the ability, in some circumstances, to deal successfully with solid failures.
For example, recovery from a failure to obtain. a
proper current for the electron beam in the recorder may be achieved by program-controlled
rotation of the filament turret to bring a new filament into operati'On.
The area of automatic recovery will be covered
in more detail subsequently. It is certainly a sig-
Dynamic Recovery Techniques Guarantee System Reliability
nificant feature 'Of the IBM 1360. Th'Ose familiar
with the problems and total system disruptions
attendant with malfunctions find it gratifying to
observe the subsystem discern a failure, go
through an automatic recovery procedure, and
then resume complete and normal operation.
The variety of failure eauses and recovery procedures do not permit a simple statement on recovery times. However, the considerable majority
of recoverable malfunctions represent a delay of
less than 20 seconds from suspension of processing
to its full restoration. The host computer has been
passive in the process and 'Only experiences a time
delay in completion of its commands.
Of course, the success or lack thereof by automatic recovery determines the subsequent procedure, discussed under system restorati'On. However, at this point we briefly examine the failure
hist'Ory element of the D/AR procedural steps.
Failure history
Regardless of the results of the recovery attempt, a failure history is always recorded. The
detailed data and the results are formed into a
record and stored on the 1360's disk. These recods, elaborated on later, are useful to the field
engineer in solving a solid problem by isolating
the malfunction to a very narrow area. The records are also useful in a preventive sense. The
field engineer can, when servicing a solid failure
or when performing preventive maintenance, determine from the failure-history output a pattern
indicating substandard performance. He can thus
give special attention to a marginal piece 'Of equipment and perhaps obviate a solid failure.
System restoration
Once the preceding steps in the D/AR procedure
have been accomplished, the remaining concern is
to reinstate the 1360 system to a status compatible.
with the D/ AR result. Consider the action first in
the two extreme forms, namely, total recovery or
total system down.
In the case of total recovery, the failing mechanism is put in the desired state and processtng is
allowed t'O continue. Referring to previous discussion on the control programs, it can be seen
that this is not a very involved process.
. In the event of a nonrecoverable failure which
requires that the 1360 system be taken down, there
is a somewhat more involved pr'Ocess. First, the
1393
host is notified that the system is down. Then, a
special program in the c'Ontrol processor "clears
out" the system. This consists'of taking chips and
cells not in their resident file positi'On and moving
them to a reserved section 'Of the file, so that the
host may identify them and restore them when
the system is again operational. A message is
als'O typed on the 1360 typewriter, indicating that
it is necessary to call a field engineer.
An intermediate case of a nonrecoverable failure is when a c'Omponent is down but the entire
1360 system is not down. The availability of a
single file, the pneumatics, and a single terminal
(either a reader or the recorder) is sufficient t'O
permit operation. For example, if a s'Olid failure
occurs in one reader, .the rest of the system can
operate; or, if the recorder is d'Own, the 1360 is
still fully capable of satisfying the read functi'On.
In these cases, the host is notified as to which
component went down. For a reader or the recorder, a distinction is made between a data failure and a mechanical failure. A mechanical failure means that the comp'Onent is immediately
down and any chips and cells at that terminal are
temporarily unavailable. A data error means that
the read or write function is lost, but the h'Ost has
the ability to handle and return chips and cells.
After doing so, the host sh'Ould release the component, and the 1360 will then declare it down. A
message identifying the d'Own component is typed
on the 1360 typewriter to request field engineer
service, but the 1360 is able to function with the
remaining comp'Onents.
This flexibility avoids the "for want 'Of a nail,
the shoe was .lost" problem. The advantage of this
is made even more significant by the fact that the
field engineer in many cases is able to service the
d
r
o
I
.
.'
..
....,.
------ ---_..
......
~---'---
9
9
17
15
100
200
I COMPUTED
".'
"""
-~--
1-----
~
~
rOFFERED
",'
-==~"-- ~ ....
~.-.-.-.-
I-
/
/
_____
~Specifiea~l~
Typical uses of models
1. Resource Quantities
I-
10
Simulation results
The simplest use of the simulatien models is
the optimizatiO'n of design parameters, which are
those features of the hardware and software design that can be modified witheut changing the
overall logical design, e.g.,
1405
----- -----
25
31
35
20
29
32
40
37
J
J
-L
-0
FIGURE
~Handoff
300
LOAD IN TRACKS
500
actions response time 2 CEs
Figures 4-8 show typical results from simulation runs in the early stages of N AS system design when numerous alternatives were being considered. Although the latest system design has
different performance characte,ristics, the relative effects and the analysis techniques remain
the same. Unless otherwise specified, a two compute element system is being simulated, generally
for 60 seconds of real time.
Figure 4 shows how the response time for the
important handoff action varies- with the total
number of tracked aircraft. A hand off of centrol
occurs when a plane moves from one sector, controlled by one R-, D-, and A- controller trio, to
another sector in the same or another ARTGC.
The "Offered" line in Figure 4 shows the total
number of handoff actions entered into the system during the simulated 60 seconds. The "Completed" line s,hows the number of handoff actions
completed by the end of the 60 seconds. If the
number completed is less than the number offered,
it indicates that the balance is still being pr6c12
11 l-
10
lS
~ 9 Iu
::: 8
•
;;; 7 I-
• AVERAGE
H·l00%
z
~
i
I
75%
I
6
!<
o 5 l-
~
~
4
~ 3
~
/~
~
:
t11!!.'lLSJ!!I:!fl£a!i~
J (("HFnlll FO
i
i
...........
---- ------,====--=--=--.:. .:;.::-_-=-.:::; ~
~
J lID
H COMPLETED I
/'
i
i
60
I:IJ
I:IJ
I:IJ
60
59
60
I
I
I
100
200
300
60
52
60
40
I
]-
I
LOAD IN TRACKS
FIGURE 5-Maximum radar data age 2 CEs
500
Fall Joint Computer Conference, 1968
1406
2.0
~
~ •a
TOTAL IDLE
SUSPENDED IDlE
• TRUE IDLE
I
2.0
3RDCE
~ ~ ~ t::::::- -
o
~
~
e
Z
1.5
A~ .....
1.0
..... .....
1.0
' ....
.~
------- "
.s
o
o
I
I
I
I
I
........
",.......
,'-",
200
~~
I
500
r-
.......----;
I
aAKRR
• FPIN
• TKDT
I
-.
.6
.5
~
A
.3
,.'
, """....
," ~
, ,'" ~--~
~.~.
.2
-'
....... V"
~
~
.1 ~
o
I
o
I
I
I
100
I
I
I
200
I
I
I
I
I'
I
I
I
I
1 CE
-
I
I
I
I
20
40
6b
'--1lO
100
FIGURE 8----Total CE effectiveness-RDPRA
~
~
I
I
I
EXPECTED
RATIO IN
RDPRA
I
I
300
1.0
.7
~
PERCENT DATA IN SAME Sf AS PROGRAM
essed. These remaining handoff actions may be
encountering normal queuing delays or, more
seriously, a backup may be developing because
the system capacity has been exceeded.
Figure 5 shows how the maximum radar data
age varies with the number of tracks being processed. Radar data is read continuously into wraparound buffers. One pro-gram element (RDPR) is
activated every second to process the radar data
received since the beginning of the previous
RDPR operation. The processed radar data is
written out at the end of each RDPR operation to
various 'R' controller CRTs. The maximum radar
data age is defined as the time from the beginning of the previous RDPR P.E. to the end of
the next operation. The specified maximum radar
age is 2.0 seconds.
Each RDPR operation results in one measure
of maximum radar datage; The "Scheduled" line
shows that ideally there would be 60 RDPR
operations per minute. However, a· particular
RDPR operation may be delayed in getting necessary resources and hence, may take longer than
H
J
2 tEs
~:n
20
FIGURE 6-Average CE idle time 2 CEs
.8
1
1
1"'"
" ---"-:'''::.::u
~,~
l
100
.5
LOAD IN TRACKS
.9
I
I
~tl
0
Z
:....
1-3CE.
1.5
I
300
LOAD IN TRACKS
FIGURE 7-Lock area utilization 2 CEs
I
I
I
500
two seconds to complete its work. Meanwhile another RDPR operation would no.rmally have been
activated for the next second. The system executive, however, lets the delayed RDPR operation
continue on into the following second, so that less
than 60 RDPR operations per minute can occur, as shown in the "Completed" line. Figure 5
shows that the maximum radar age increases considerably for loads in excess of 300 tracks.
Figure 6 gives a clue to the maximum system
capacity through the relationship between com. puting element average idle time and track load. Idle time has been subdivided into two components. "True Idle" is the fraction of a G.E.'s time
that it is idle and there are no program elements
(tas·ks) in any type o.fresource or wait IjOsuspension. "Suspended Idle" is the fraction of a
G.E.'s time that a compute element is idle when
one or more P .E.s are suspended. C.E.s are ready
to perform work but the P.E.s are suspended because of the unavailahility of other system resources, e.g., common data locks. The leveling out
of the Total Idle curve at 400 tracks in Figure 6
is an indication that the system capacity has been
reached. Further work load is being added to
the system yet no. further computing is being
done. Resources other than compute elements are
causing infinite queuing to develop. Various response time specifications may, however, have
been exceeded at lower track loads.
Figure 7 shows the utilization of three important common data tables (AKRR, FPIN, TKDT)
as a function of the track load. The system has
been found to approach saturation when the utilization of the most critical common data areas
approaches 0.8. The key system design problem
has been to reduce the usage of the various common data areas. Whenever such reductions are
simulated, system performance improves markedly.
Simulation Design of Multiprocessing System 1407
Techniques for enhancing parallel processing
of a common data base
A variety of techniques have evolved to enhance the ability of multiple processors to operate
off a common data base and to reduce the loads
on critical areas. Each technique must generally
be tailored to the particular application and data
base. The simplest way to avoid interference is
to schedule the various functions so that two
program elements will never require access si.
multaneously to a common portion of the data
base. This is difficult, however, in a random realtime system.
Access to a specific portion of the data base
can be controlled by a common data lock associated with that portion. The restrictive or queuing
delay character of these locks can be diminishing
by allowing each lock to operate either as a read
lock or write lock. Only one program element can
gain a write lock, but multiple program elements
can simultaneously gain a particular read lock by
which they read but do not modify the particular
portion of the data base.
The queuing delays caused by simultaneous attempts to lock data areas can be reduced by minimizing the duration of the lock; first, by delaying
as long as possible before attempting to lock, and
secondly, by unlocking as soon thereafter as possible. The monitor can also facilitate the earlier
unlocking by giving higher priorities to program
elements which have critical locks. One way to
hold off locking is to only add completely processed data to the data base.
If a number of common data locks are required
by a program element, they do not have to be
acquired at the same time, but can be requested
only when ne'eded. This, however, requires that
all program elements request common data locks
in the same sequence, so as to avoid the following system lockup problem: PE 1 obtains a Lock
A while PE 2 is concurrently obtaining Lock B.
After additional processing time, PE 1 attempts
to get Lock B while PE 2 attempts to get Lock A.
However, neither program element will unlock
its first lock until after it has obtained the second
lock. The lockup could be avoided by requiring
all PE's to request locks in the same order, e.g.,
A first, then B.
Another way to reduce the impact of common
data locks is to increase their number by breaking up the data base into smaller portions, each
of which has a data lock. For example, consider
a data table with n entries, each of which has p
fields or items. Several common data locks could
be defined, each identified with a subset of the
p fields in all entries. Alternatively, multiple common data locks could be defined for subsets of
the n entries, where in the ultimate each entry
in the table has its own individual lock.
If program 1 transmits data to program element 2 by a communication table, a common data
lock on the table can be avoided by treating the
table as a wraparound buffer. Each PE maintains a pointer to where it is currently processing.
Both PE'scan operate simultaneously by not
moving ahead of where the other PE is currently
pointing. Some monitor services would have to
be provided to suspend a PE temporarily when
it catches up with the other PE, and to resume
the suspended PE when it can do further processing.
Results of memory interference model
With a multiprocessing system, it is possible to
have re-entrant programs (which permit sev-,
eraI processors to execute them in parallel),
thereby minimizing core storage. However, the
computing power of the processors would be de ..
graded by their mutual interference in fetching
instructions and data from the storage element
in which the program is located. Figure 8 shows
the results of a typical series of runs with a
special memory interference model which determine tradeoffs between using single copy reentrant programs and using more core for duplicate copies in different storage elements. The
system simulated in Figure 8 has 1, 2 and 3 computing elements executing the same program in
the same storage element (SE). There are no
IIO data transfers occurring. Run.s were made by
varying the p'ercentage of the total data acces·ses
which are located in the same 8E as the program
(the horizontal axis). For 0 percent all the data
accessed by the program is in a different SEe
The stretchout factor is defined as the ratio of
the execution time of a program with interference
to the execution time without interference. Thus,
if the stretchout factor is 1.25, then a program's
execution time will be extended by 25 percent.
The effectiveness of a CE (the vertical axis of
Figure 8) is the reciprocal of the stretchout factor.
If two CE's are each executing the same program,
with a stretchout factor of 1.33, the effectiveness
of each CE is 1/1.33 = 0.75. Thus, the total effectiveness of the two CE's is 2 X .750 = 1.500.
If three GE's were executing the same program,
1408 Fall Joint Computer Conference, 1968
each with a time stretchout of 2.00, then the
total effectiveness of the three CE's would be
3 X 1/2.0 = 1.5. Thus, the total effectiveness
of the three CE's is the same as two CE's and
therefore, the third CE, from a system point of
view, does not perform any useful data processing.
Figure 8 illustrates the relationship between
total CE effectiveness for a particular NAS program called RDPRA and the interference level.
When· there is only one CE executing a program
in an SE, then there is no interference and the
effectiveness is 1.0 regardless of the location of
the data. When two CE's are executing programs
like RDPRA in parallel in the same SE, the total
effectiveness varies between 1.78 and 1.28 depending upon the fraction of the data· fetches and
stores that are requested from the same SE as
the programs. Thus, the contribution of the second CE to the total system effectiveness is between.78 and .28 GE's.
When three GE's are executing programs like
RDPRA in parallel in the same SE, the total effectiveness varies between 2.0 and 1.28. Thus, the
contribution of the third CE to the total syste~m
effectiveness would be between .2,2 and O.
It should be noted that data can be located in
different SE's than the program by modifying the
assembler or complier and the loader so that internally defined tables, literals, etc., can be purposely loaded into a storage element (s) other
than the program. The other alternative is to
duplicate small high use programs so that memory
interference is minimized.
Structure of the simulation models
The basic approach has been to develop a family of simulation models to evaluate various design problems. A simulation language was used:
the IBM/360 General Purpose Simulation System
(GPSS). Consequently the data processing entities of the N AS system (processors, channels,
programs, I/O operations, etc.) were modeled in
terms of GPSS entities (transactions, blocks, facilities, storage, queues, etc.) and their attributes.
Consideration was given initially to the 7090
version of the more specialized IBM Computer
System Simulator (CSS). The 7090 CSS could
not simulate multiple processors so that GPSS
was chosen. The/360 GSS can model multiple
processors (up to 256) and so various GPSS
models have recently been replaced by ess models.
The IBM Computer System Simulator employs
data proce'ssing oriented entities and commands.
The new ess models are expected to be faster
running, easier tOo learn and more readily modified in evaluating alternative system designs.
A separate memory interference model was
developed which determined the average stretchout Oor slowing down of a program· being executed
in a particular storage element as a function of
the I/O and processor interference levels in the
storage element. The memory interference model
simulated the execution of individual instructions
and I/O data transfers in order to obtain accurate interference relationships. The overall system model would run far too slow if it simulated
individual instructions. Consequently computing
operations are represented by large aggregate
times which are estimated for interference free
conditions. The memory interference which would
occur during these computing times is approximated by:
1. Determining the average time stretchout
factor as a function of:
A. The total I/O data rate in the storage
element in which the computing operationwill occur.
B. The total number of processors executing instructions in this storage element
and
2. Multiplying the interference-free computing
time by this stretchout factor to determine the
actual computing time.
Another model creates a GBSS jobta.pe which
contains a random, time ordered s,et of. external
input mess~age!S and internal events. The same
message-event mix can, therefore, be inputted
tOo a set of alternative system designs. There are
several advantages to this approach. First, the
overall system model runs faster since it does
not have to take computer time in each new run
to generate mess-ages and events and their attri.
butes. More importantly, a constantly regenerated
message-event mix could vary from run to run,
thereby by confounding statistical variations
caused by these changes with those caused by true
variability between alternative designs. The messages and events which are simulated are only a
small portion of the total number of possible message and event types. They, however, constitute
more than 90 percent of the total volume of messages and events.
The overall system model was developed in two
distinct parts: a monitor/hardware submodel and
Simulation Design of Multiprocessing System
an operational program submodel. The monitor/
hardware suhmodel is far more complex, requiring 3500 GPSS blocks while the operational program submodel requires 2000 GPSS blocks, many
of which are only used for calling sequence arguments. In the actual system, the portion of the
monitor modeled represents about 8000 out of
172,00.0 words of program. This apparent distortion, however, reflects the fact that the monitor
controls the system resources which are the major
elements of the system model. The monitor/hardware submodel also uses the great majority of the
other GPSS entities (facilities, storages, savevalues, etc.)
The monitor/hardware submodel simulates the
following standard monitor progra:r:ns :
1. Dispatcher program (ZMDP) which allocates tasks to the processors on the basis of task
priorities.
2. I/O interrupt processing program (ZMCX)
which performs housekeeping functions associated with the completion of I/O operations and
allocates delayed I/O requests to ava.ilable devices
and channels..
3. External interrupt processing program
(ZMEX) which performs functions associated
with periodic timer interrupts and write direct
operations between processors.
4. Monitor service request program (ZMSX)
which handles various monitor services provided
to the operational programs, such as initiating
I/O reads and writes, leasing dynamic storage
blocks, locking common data areas, scheduling
other tasks, and waiting for the completion of
outstanding I/O operations.
The monitor/hardware submodel also simulates
the I/O hardware (channels, control units, lines
and terminals), the execution of various I/O operations on this hardware, and the generation of
I/O interrupts of processors. The monitor/hardware submodel has built-in performance statistics
which are intended to answer' most of the important questions on system performance. Additional special statistics can usually be obtained
with ease because of the inherent flexibility of
the GPSS language.
The operational program submodel was designed to operate in relative ignorance of the
complexities of the monitor/hardware submodel.
The major interface between the two submodels
is a set of standardized monitor service requests.
Each request is a transfer to the monitor submodel with a set of arguments that define the
1409
type of service or resource required by the operational program. Cons,equently, personnel who are '
less skilled and experienced: in the complexities of
the GPSS simulation language can model the
various N AS operational programs using the
simple monitor service requests. They can concentrate their effort on accurately representing
the problem state processing times and programming logic. One experienced person has maintained the relatively unchanging model of the
monitor programs and hardware.
The overall system model has itself generated
some offspring. Because of its complex structure
and its relatively slow running time, a scaled
down version was produced which eliminated the
simulation of various syste1m resources and the
gathering of many performance statistics. pynamic leased blocks and I/O. hardware resources
were dropped. Memory interference was not accounted for. Instead, the smaller, faster running,
system model concentrates on two key resources:
the processors which perform computing and the
31 common data locks which govern access to
various parts of the system's common data base.
This model has proved useful in evaluating different resource scheduling schemes.
Table IV summarizes the size and running time
characteristics of the family of models.
Model
Block
Size
Memory Inter50
ference
Input MessageInternal Event
200
Generator
5500
Overall System
Scaled Down
1000
System
Unit
Time
Run
Time
360/50
Time
.1 #,sec
10 msec
30 sec
1 msec
1 #,sec
3 min
60 sec
4 min
20-40 min
1 msec
60 sec
2 min
TABLE IV-Characteristics of GPSS models
CONCLUSION
Simulation modeling should be an integral part
of designing complex data processing systems. A
family of models will generally be requiredrepresenting different aspects or portions of the overall
system. Simulation models permit an accurate
evaluation of numerous design alternatives. They
can spotlight critical resource bottlenecks before
actual system implementation. Through Murphy's
Law of Simulation every simulation run provides
1410
Fall Joint Computer Conference, 1968
a vital quality assurance function by pos'sibly revealing some unanticipated design problem. Multiprocessing systems present significant ·new design
problems because of simultaneous competition
among processors, first, for access to a common
data base and, secondly, for storage element memory cycles. Simulation modeling may alone deter.
mine the best design to minimize the performance degradation resulting from this competition.
REFERENCES
1 An application-oriented multiprocessing system
IBM Systems Journal Vol 6 No 2 1967
2 FKSEWARD
'
National airspace system enroute
Proceedings 1967 IEEE International Convention
3 System description national airspace system en route, stage A.
FAA April 1965
4 GP SS / 360 introduction-user' s manual
IBM Form Number H2o-:G304
5 GPSS/360 user's manual
IBM'Form Number H2o-:G326
6 GPSS/360 OS operator's manual
IBM Form Number H20-0311
7 GPSS/360 system manual
IBM Form Number Y20-o075
8 Computer system simulator /360 program description and
operations manual (IBJJf Confidential)
IBM Form Number Y2o-:G130
9 Computer 8yslem simulator/360 application desc7'iptiotl
IBM Form Number Y20-0028
10 T A HUMPHREY
Large core storage utilizal'ion ,in theory and in practice
Proceedings of 1967 Spring Joint Computer Conference
11 WISTANLEY HFHERTEL
Statistics gathering and simulation for the .4POLLO real time
operating system
IBM Systems Journal Vol 7 No 21968
12 E C SMITH JR
Simulation in systems engineering
IBM SystemsJournalVol11963
13 N R NIELSEN
The simulation of time sharing systems
Comm ACM Vol 10 July 1967
14 JHKATZ
Simulation of a multiprocessor computer system
Proceedings of 1966 Spring Joint Computer Conference
A simulation study of resource management
in a time-sharing system
by SANDRA L. REHMANN
IBM Corporation
San Jose, California
and
SHERBIE G. GANGWERE, JR.·
Computer Application Incorporated
Palo Alto, California
INTRODUCTION
In general, simulation has two main uses. One is
to provide basis for predicting how the system
simulated will perform under varied conditions
and for determining which conditions are necessary for optimum performance. The other is
more basic. Complex systems can be beyond the
scope of human comprehension, and the statistical data generated in a simulation can be used to
further the understanding of the interworkings
of the system under study. The knowledge gained
can, in turn, become the basis for further analysis
and evaluation. Results can improve the performance of the system being simulated, as well as
broaden performance goals and· attainments of
future systems;
This paper describes the design and use of a
simple time-sHaring, multi-programming model.
Both goals of the simulation study were met:
a
1. To estimate the requirements for optimum
performance.
2. To 'obtain a basic understanding, through
use of a simple model, of what happens in a
multi-programming environment.
Several ideas had been incorporated into the design of the system. The simulation provided us a
means of evaluating these ideas.
Response time was selected as· the performance
*Now with Advanced Programming, Incorporated, Santa.
Clara, California..
1411
guideline in the simulation, since, to the user,
response time is one of the most meaningful
measurements of a time-sharing system.
Background
The simulation was directed at the problem of
"slave-resource" management.
Slave-resource
management is defined as the management of .
core memory, disk channel(s) and drives, and the
central processor, to accomplish compilations
and/or executions on behalf of a user. A compute interaction is the total amount of computing required as a result of an EXECUTE
command or user response to a READ statement.
A time slice is the· maximum amount of CPU
time allotted to a· program for compilation and/or
execution. If the program does not complete in
one time slice, it must wait in a queue until additional CPU time can be allotted to it.
The EXECUTE command results in compila.
tion and execution of the compiled code. The
READ statement results in a compute interaction.
Sequentially the program is compiled, and object
code execution begins and continues up to the
point of the READ statement. The object code
notifies the operating system that input data
from the terminal are required. The object program is swapped to disk. All computing up to this
point is due to the EXECUTE command. When
the user responds with input data, the program
can resume execution. Computing from· this point
1412
Fall Joint Computer Conference, 1968
on is a result 'Of response to the READ statement.
System description
The system studied is nonpaging, multi-programming. Users are swapped in and out of high
speed core memory via a disk storage unit.
The system does not execute line. by line. Instead, all lines for a program are entered; the
user then issues an EXECUTE command. The
EXECUTE command results in a compilation and
execution of the user's program.
All compute requirements up to the EXECUTE
command are handled in system's overhead. In
the simulation, the only concern was the problem of system management during the compile
and execute phaae.
A user can cause the system to do a compile
and/or execute in two ways:
1. The EXECUTE command causes a compile
and execute.
2. When object code is being executed and a
READ statement is encountered, execution
of that program is suspended, and an appropriate message is sent to the user's terminal. After the user supplies, the input
data, execution of his program will resume.
,The ideas
To the best of our knowledge, H.CantreUl was
the first to propose using a time slice to separate
short jobs and long jobs. His basic idea was to
treat all new jobs as though they, would complete
ill one time slice or less. If a time slice, was
chosen so that 90% of all jobs would complete in
one time slice or less, a slave-resource management system could take advantake of the probability that:
1. 90% of' all new jobs would complete in one
.
time slice or less.
2. Jobs that did not complete in a time slice
tend to be long-running jobs.
Cantrell observed that, having identified long-running jobs, if the slave-resource management system ,can keep at least one long job in core, the
long-running jobs can use compute time available
during I/O time of the new jobs.
Both Dr. Amdahl 2 and H. Cantrell1 suggested
USIng two queues, one for new. jobs, and another
for' partly-finished jobs that have already used
more than a time slice.
In evaluating the proposed system, we found
that the probability of being able to hold two
jobs in memory simultaneously was greater than
.9996.
As a result, our simulaHon study was based on
a further assump.tion that:
1. Two jobs would always fit in core.
2. A maximum of two ,jobs would be allowed
in core at any time.
With only two job areas in memory, calculations indicated that CPU utilization could possibly
exceed 90% when jobs were in the queue waiting
for service.
The model
The simulator was written in GPSS.3 Simulator
output was hand-checked to verify the model.
Each run required about three minutes of System
360/50 time. A total of ninety-one runs were made
and the results tabulated and graphed.
Figure 1 is a block diagram of the model. All
new jobs, (i.e., compute interactions due to an
EXECUTE command, or response, toa READ
statement) are entered in the bottom of ,Queue
2 (a FIF? queue). New jobs are generated at the
rate of one per user per 110 seconds. When a
user generates a job, he is removed' from the set
of users generating jobs. VVhen a user has issued
an,EXECUTE command or responded to a READ
statement, the same user cannot generate another
compute interaction request until his first request is completed. When Facility 2 (core memory
area number 2) is not in use,the job at the head
of Queue 2 is loaded into core. A simulation system study (unpublished) measuring'disk chan-
FACILITY 1
, (CORE AREA 1)
~--10"'" END
JOB
OLD
JOBS
FACILITY 2
(CORE AREA 2)
NEW
JOBS
.......-._.... END
JOB,
FIGURE I-Block diagram of model
Simulation Study of Resource Management
nel(s) usage had been done by S. Rehmann. Results of this simulation were used to determine
requirements for disk I/O time. The model used
an I/O time of 150+25 ms (random in the. range
of 125 to 175 ms). When the load is completed,
the CPU is applied to the job until either the
compute time-slice is up or the job signals EOJ
(end of job).
When the job signals EOJ, the job is :r.emoved
from the system. If it used· a time slice and did
not signal EOJ, it is move" to Queue 1 (a FIFO
queue). Regardless of the reason f~r termination,
one I/O time is used to remove the'Job from core.
Assume for a moment.:that a job is removed
because the time slice isap. After completing the
I/O (by rolling the job out to disk), the job is
placed at the end of Queue 1. When Facility 1
(core memory area number 1) is available, the
job at the head of Queue 1 is loaded. When the
load is completed, the CPU is applied to the job
ita new jobjs not in Facility 2. CPU priority is
a simple three-level priority:
1. A new job in Facility 2 gets the CPU.
2. If the CPU is not required for a job in F~
cility 2, the CPU is applied to a job in Facility 1. VVhen the CPU is applied to a job
in Facility 1 and a load completes for a job
in Facility 2, the Facility 1 job is inter·rupted and the CPU is applied to the job in
Facility 2.
3. The CPU is idle when a job is not present
in either facility.
A job from Queue 1 resides in Facility 1 until it
runs to completion.
We can now discuss the model in terms of a
job's life span. By definition, there are two kinds
of jobs in the system--.;..short jobs and long jobs.
Short jobs
Short jobs are jobs which will complete in one
time-slice or less. Refer to Figure 2 for a timing
chart of the life span of a short job.
A new job entering the system is placed in the
New Job Queue (Queue 2, Figure 1). Since jobs
are processed on a first-in-first-out basis, jobs advance until they are at the head of the queue.
VVhen core memory (Facility 2, Figure 1) is
available, the I/O required to load the job is
initiated.
After loading, the CPU is applied to the job
for the length of time required to complete the
job. A short job will complete when:
1413
SHORT JOB
Walt In
new job
queue
I/O time to
load job to
core
Compute time
~ one time slice
~I------------~I------------~--------
I/O time to
swap job out
of core
____~-+I------------~IEOJ
LONG JOB
Wait in
new job
queue
I/O time to
load job to
core
Compute time
= one time slice
I/O time to.
swap job out
of core
--------------fl· ....
I~-----~--------------+-----~-----+I
Wait in
old job
queue
• • ••
I/O time to
load job to
core
Wait time +
compUte time
to job completion*
I/O time to
swap job out
of core.
------------+-1---------------+-------------11 EOJ
I~----_~I
* An old job using the CPU may be interrupted by a new
job needing the CPU. Therefore, there may be some
waiting time for the CPU.
TIME
FlQURE 2-Lifespan of jobs
1. computing is completed, or
2. the job requires input from the terminal.
A job that does not complete for one of the
above two reasons is terminated when the timeslice is up. Such a job is then defined as a "long
job". Regardless of the reason for termination,
I/O is initiated to roIl the job to disk.
Long jobs
Long jobs are those which require more than
one time-slice. When the time-slice is up and a job
has been rolled out to disk, it is placed at the end
of the long-job queue (Queue 1, Figure 1). It
waits in the long job queue until it has worked its
way to the . top of the queue. When the core
memory (Facility 1, Figure 1) is available, the
I/O to load the job is initiated.
A short job in Facility 2 \always has CPU
priority over .the long job in Facility 1. Due to
this CPU priority algorithm, the long job will
more than likely be interrupted several times
when short jobs in memory require the CPU.
VVhen the long job terminates, the I/O to roll
the job to disk is initiated.
At this point· let's examine the results that
m:ightbe expected from this simple kind of slaveresource management. New jobs are treated as
though they can be completed in one time slice.
1414
Fall Joint Computer Conference, 1968
This is a reasonable conclusion since 85 % to 99 %
will complete, .depending on the time slice.
All old jobs (i.e., the ones which are placed in
Queue 1) are treated as though they w-ill require a large amount of CPU time. This also is
a reasonable conclusion, since the mean compute
time of all old jobs is much greater than the mean
compute time of jobs completed in one time slice
or less. By giving CPU priority to new jobs, jobs
requiring one time slice or less will have a short'
response time. This approach, in effect, favors
short-running jobs. Longer jobs (the remaining
10 %) will require considerable compute time,
and little can be done to improve their response
times.
Compute load
H. Cantrelll observed that the computer load
curves are almost identical when the compute load
data from the GE 265 time-sharing system and
the MAC CTSS4 time-sharing system are scaled
(to take into account the different central processor speeds) and plotted on the same graph.
For this simulation (see Figure 3) the first
90% of the MAC CTSS curve was scaled to a
two microsecond CPU and used as the first 90 %
of all three compute loads. The last 10% of the
three compute load curves were arbitr.arily picked
to give various mean compute times. One purpose
of this simulation was to determine the effect on
the model as the compute load varied. The- model
is not sensitive to reasonable changes in the first
90 % of the compute load, but is sensitive to small
changes in the last 10%.
Characteristics of the three compute loads are.:
:
.100%
.61 seemeatl
.99 sec mean
1.56 sec mean
@65
(2.0,95)
(.067, .54)
3.. 0
2.0
1.0
.5
•
COMPUTE TIME (SEC.)
FIGURE 3-System compute load
lems are illustrated using data tables and graphs.
Refer to these tables and graphs in relationship
to the conclusions of these problems, which are
summarized in the following paragraphs.
Case 1
This run was made with an active user load of
from 10 to 200 active users in steps of 10, using
the Standard Curve. Refer to Tables la, Ib and
Figures 4a-4e.
100
90
80
70
l
z
Standard Curve
Medium Curve
Heavy Curve
:~~~~.T~O1~00%~@=59=SEC='::'=====1r.i(3.0;;=;,99;:)
::s;TO 100%
(3.0,98)
SEC.
60
0
j::
.:(
N
:::;
SO
j::
:)
:)
40
~
u
When the simulator picks a value from the compute curve, that value is divided by .75 to compensate for the 25 % system overhead.
20
10
Case problems
Seven case problems were addressed during the
course of this study~ For each case the result
was generated by running 2000 jobs through
the model. Data attained from these case prob-
o~
o
__
--------~
so
__________
~
________
100
~~
150
NO. OF USERS
FIGURE 4a-Case l-CPU utilization
__________
200
Simulation Study of Resource Management.
1415
TABLE ta-Case l-Data.table
Number of Users
Facility 1
Percent
Utilization
Facility 2
CPU
Facility 1
Aver(r.
Time Sec.)
.625
Facility 2
CPU
Max. Contents
New
Job
Queue
Avg. Contents
Avg. Time (Sec.)
Max. Cantents
Old
.73
1
.00
.00
2
.002
Avg. Contents
Job
Queue
Avg. Time (Sec.J
System
Mean
Response
Time (Sec.)
Short Jobs
Lone Jobs
System
Mean
Compute
Time (Sec.)
Case 1.
10
3.7
".5
5.8·
5.0
Short Jobs
Long Jobs
20
8.4
10.1
12.8
5.0
.675
.72
1
.00
.00
2
.02
.32
1.15
.52
6.67
.61
.16
4.5
1.3
100
58.1
110
65.9
58.7
73.2
6.8
.63
.71
1.27
.52
7.79
.61
.16
4.5
40
30
13.3
15.8
19.8
5.2
.625
.71
1
.00
.00
5
.08
3.0
1.46
.52
9.62
.61
.16
4.5
1a.5
21.4
26.8
5.2
.625
.71
1
.00
.00
·7
.19
5.3
1.71
.52
12~ 1
.61
.16
4.5
60
70
80
90
24.1
26.9
33.6
5.4
.625
30.0
32.5
40.6
5.6
37.0
43.9
SO.S
37.9~
.n
.35
7.8
.71
1
.00
.00
7
.55
10.2
.87
. 13.8
1.99
2.26
2.66
.52
14.8
.61
.16
4.5
.52
17.4
.61
.16
4.5
.52
21.3
.61
.16
4.5
48.5
43~3
.60.5
54.0
6.3
6.1
.625
.625
.71
.71
1
1
.03
.01
.04
.015
12·
11
1.82
1.26
22.7
17.6
3.66
3.09
;.56
.53
30.7
25.4
.61
.61
.16
.16
4.5
4.5
50
.625
,
.00
.00
7
47.3
5.9
.625
.71
1
.00
.00
10
Compute Load = Standard
Time Snce = 933 ms
Number of Users =Variable
Tobie la.
Case 1 - Data Tobie
Number of Users
Percent
Uti Iization
Facility 1
Facility 2
CPU
Facility 1
Average
Time (Sec.)
Facility 2
CPU
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Meon
Compute
Time (Sec.)
Cose 1.
Mox. Contents
Avg. Contents'
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Shott Jobs
Long Jobs
System
Short Jobs
Lon9. Jobs
53.8
67.0
6.5
.63
.71
2
.06
.08
14
2.6
29.5
4.4
.59
37.8
.61
.16
4.5
3
.11
.11
19
3.8
38.8
5.5
.63
47.5
.61
.16
4.5
120
72.9
63.3
78.9
7.0
.63
.71
3
.16
.16
20
5.3
50.7
6.8
.68
59.7
.61
.16
4.5
130
SO.6
67.9
84.3
7.4
.62
.70
4
.25
.23
25
7.3
65.3
8.3
.74
75.7
.61
.16
4.5
140
86.6
71.7
88.6
7.8
.62
.70
5
.34
.29
29
10.3
86.7
10.4
.81
99.4
.61
.16
4.5
150
90.0
75.2
90.7
7.7
.62
.69
5
.43
.36
34
14.2
114.3
13.3
.88
129.2
.61
.16
4.5
160
92.6
78.3
92.5
8~ 1
.62
.68
6
.56
.45
41
18.4
142.2
15.6
.97
160.3
.61
.16
4.5
170
92',9
81.2
93.3
9.1
.63
.67
7
.71
.55
54
23.7
173.9
15.7
1.1
183.2
.63
.16
4.6
Compute Load == Standard
Time Slice
=933 ms
=Variable
Number of Users
Tabl. lb.
Cose 1 - Data Tobl. (continued)
TABLE Ib-Ca.se I-Data. table (continued)
180
93.1
84.1
93.5
8.8
.63
.65
9
.98
.73
190
93.2
86.9
93.7
9.0
.63
.63
14
1.6
1.1
54
64-
28.3
200.4
18.9
1.3
220.7
.63
.16
4.6
33.2
226.8
20.6
1.7
248.7
.63
.16
4.5
200
93.2
89.5
93 ..8
9.0
.63
.61
21
2.8
1.9
74
37.2
247.5
22.7
2.5
274.1
.62
.16
4.5
Fall Joint Computer Conference, 1968
1416
•
~
25
3.0
~
20
~
15
i=
w
Z
g
~
10
o~
Z
______~______+_------+_------+
o
<
~
50
100
150
200
NO. OF USERS
5
FIGURE 4e-Case 1-Short job mean response time
o
~
o
____-+______
50
~
______+-____
100
~
150
Analysis
200
NO. OF USERS
FIGURE 4b.,-Case I-System mean response time
5.0
~
4.0
i=
3.0
~
w
I
I
LJ
I-
~
~
2.0
z
1.0
8
<
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYSTEM
0 ~====~=======r==~==~~==~SJ
0
50
150
100
200
NO. OF USERS
FIGURE 4c-Case I-Mean compute timf'
is
300
~
~
~
i=
w
."
Z
2
~
ac::
·Z
<
:E
00
200
180
160
140
120
100
0...,
80
C>
60
40
20
0
Z
0......
0
50
100
150
NO. OF USERS
FIGURE 4d-Case I-Long job mean response time
If we pick a point wher(. the CPU utilization is
67% (say, 100 users) and look at the data, we
can get a good idea of what is happening in the
system. The New Job Queue has an average of
.06 users. This means that the system is working
off new jobs about as fast as they enter the system. No gains in performance would be realized
by trying to put two new jobs in core at the same
time.
The Old Job Queue has an average of 2.6
users, but Facility 1 is used only 58.1 %. of the
time. The low usage of Facility 1 means that
sometimes the Old Job Queue does not have any
entries; hence, Facility 1 is idle or not used. Combining the facts that the Old Job Queue has an
average of 2.6 users, but Facility 1 is used only
58.1 % of the time, we can deduce that the system, at times,
in a temporary "overload" condition in the Old Job Queue-Facility 1 area, but
the system is able to "catch up." During overload
conditions, some gain could be realized if two old
job core areas were used. The gairi may not be as
great as one might expect, because if two old
jobs core areas were used, there is still only one
CPU to apply to the jobs. The only gain would
be to use the CPU on the second old job during
the I/O times for the first old job and the new
job.
During the Old Job Queue-Facility 1 overload
periods, the CPU utilization undoubtedly goes
much higher. From the data we can estimate
what the CPU utilization is during overloads.
The old job mean compute time is 4.5 seconds,
4.5 -+ ~75 to compensate for the 25% overhead =
6.0 seconds. The total I/O time is 0.8 second. Compute plus I/O is equal to 6.0
0.8 = 6.8. If the
200
+
Simu1atiop St\ldy of Resource Mana~ement
Old Job Queue always had a job ready to load
into core and the CPU was used only for long
jobs, the CPU utilization would be 6.0 -T- 6.3 or
about 95 %. The CPU utilization will be higher
than 95% due to the multi-programming gain of
having applied the CPU to short jobs as well as to
long jobs.
From the foregoing analysis we conclude that
the gain to be made by having a second old job
in core would be negligible.
1417
temporary overloads.
(with 150 users)
1. New jobs are worked off about as fast as
they arrive. .
2. CPU utilization is good.
3. Having a second old job in core would not
.help much, as the CPU is 90 % used up at
this point.
4. Response time is acceptable.
Case 2
Conclusions
(with 100 users)
1. New jobs are worked off about as fast as
they enter the system.
2. The CPU is not used up except during
The second case study addressed the problem of
the effects of varying the time slice. This case
covered variance of the time slice at 120 users
using the Standard Curve. Refer to rpable II and
Figures 5a-5f.
TABLE II-Case 2-Data t.able
Percent
Uti lization
Average
Time (Sec.)
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Case 2.
Table II.
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec~)
System
Short Jobs
Long Jobs
System
Short Jobs
Long Jobs
Compute Load = Standard
Time Slice = Variable
Number of Users = 120
Case 2 - Data Table
4.0
69.9
74.2
82.0
66.6
.71
3.0
70.6
73.0
82.2
67.1
.69
.77
9
.87
.82
.50
45.4
2.67
1.48
.120.1
.612
.265
33.4
.68
.77
.77
8
3
2.5
70.9
71.9
81.9
46.6
6
.66
.63
3
.49
44.6
2.41
1. 28
120.1
.612
.265
33.4
.56
.53
4
.85
54.1
2.66
1. 18
107.1
.612
.253
24.2
2.0
71.6
70.6
81.8
35.0
.67
.76
6
.45
.43
5
1.08
51. 6
2.n
1.06
91.4
.612
.243
18.7
Time
1.5
72.5
68.8
81.6
27.7
.66
.76
5
.33
.32
7
1.50
56.0 .
3.08
.93
88.6
.613
.235
15.1
Slice (Sec.)
1.0
.933
72.5
72.9
64.7
·63.3
79.5
78.9
9.0
7.0
.63
.63
.72
.71
4
3
.16
.20
.19
.16
20
15
5.3
4.48
50.7
55.2
6.76
5.92
.74
.68
59.7
66.4
.613
.613
.164
.185
5.57
4.50
.8
73.9
60.5
n.9
5.4
.60
.68
3
.10
.10
25
6.7
48.3
8.1
.58
55.5
.613
.136
3.60
.7
74.8
58.2
77.5
4.7
.58
.67
2
.07
.07
30
7.3
45.7
8.8
.52
51.9
.613
.119
3.18
.6
76.0
55.5
n.o
4.1
.56
.65
1
.03
.03
30
8.0
50.0
9.~
.46
48.4
.613
.101
2.81
.4
78.0
49.4
76.2
3.4
.50
.63
1
.00
.00
33
9.1
39.8
10.6
.40
44.2
.613
.on
2.37
Fall Joint Computer Conference, 1968
1418
,...;..---~LJ
100
30
90
~
~
~.
80
20
j:
W
I-
70
2
~
l
z
Q
....
8
60
10
Z
«
;5
~
50
:::;
t=
:l
o L_i===i=====F=====F====~nSTEM
o
1.0
2.0
3.0
4.0
TIME SLICE (SEC.)
.w
~
u
30
FIGURE
5c-Case
2-Mean
compute
time
20
10
200
0
2.0
1.0
0
TIME
3.0
4.0
slice (sec.)
~
~
150
~
;::
FIGURE 5a-Case 2-CPU utilization
w
V)
Z
0
0-
V)
100
w
e..:
Z
«
~
Z
9
o
o
2.0
1.0
20
3.0
4.0
TIME SLICE (SEC.)
FIGURE 5d-Case 2-Long job mean response time
15
~
~
~
;::
w
Z
2
~
10
3.0
~
~
V)
~ll;!
;::
wZ
Z
2.0
'"Z
1.4
w
ti;:;5
~~
~
5
«
~
::::>
40
0
1.0
;!
.....
2.0
3.0
4.0
TIME SLICE (SEC)
FIGURE 6c-Case 3-Mean compute time
~
u
30
200
20
8~
10
LLJ
~
.....
0
150
LLJ
Z
III
0
1.0
2.0
3.0
4.0
0~
III
LLJ
TIME SLICE (SEC.)
0<:
100
Z
«
LLJ
FIGURE 6a-Case 3-CPU utilization
~
on
Q
50
(!)
Z
0...J
20
oL-------~----~------~------~
3.0
4.0
o
1.0
2.0
TIME SLICE (SEC.)
15
FIGURE 6d-Case 3-Long job mean response time
~
~
~
3.0
U
LLJ
i=
LLJ
III
Z
~
10
LLJ
~
2
;;:
III
LLJ
Z
~~
III
LLJZ
I;;~
2.0
00..
~~
~
0<:
5
Z
«
LLJ
~
1.0
on
Q
.....
0<:
0
o
J:
o
1.0
2.0
3.0
TIME SLICE (SEC.)
FIGURE 6b--Case 3-System mean response time
4.0
III
0
L--------~1-.0--------2~.0--------~3.~0--------:4.0
0
TIME SLICE (SEC.)
FIGURE 6e-Case 3-8hort job mean response time
Simulation Study of Resource Management
1421
effect on system response.
2. At the point of best response, the CPU
utilization is as good as it can be with this
user load.
Conclusions
1. With this particular compute curve, vary-
ing the time slice can have a measurable
99%@ 11 SEC.
:g
Q
-'
-'
<
u..
o
"*
o
1.0
2.0 3.0 4.0 5.0 6.0 7.0
8.0 9.0 10.0 11.0 12.0
SYSTEM RESPONSE TIME (SEC.)
FROM CASE 3:
STD. CURVE, 140 I,JSERS, 3 SEC. TIME SLICE
FIGURE 6f-Case 3-Distribution of job response times
Percent
Uti lization
Average
Time (Sec.)
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean·
Compute
Time (Sec.)
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
long Jobs
System
Short Jobs
long Jobs
Compute load = Medium
Time Slice =933 ms
Number of Users = Variable
Table IVa. Case 4 - Data Table
4.5
9.4
9.96
.625
1. 19
1.0
.000
.000
2
.009
1.21
1.75
.519
12.5
20
16.8
10.1
20.9
10.1
.625
1.17
1.0
.000
.000
3
.051
3.09
1.97
.519
14.6
30
26.8
15.7
32.3
10.3
.625
1.17
1.0
.000
.000
5
.183
7.07
2.42
.519
.99
.99
.164
8.16
.164
8.16
.99
.164
8.16
10
7.4
19~0
40
37.5
21.1
43.5
10.7
.625
1.17
1.0
.000
.000
7
.414
11.8
2.95
.519
24.2
Number of Users
50
70
60
48.6
71.9
60.3
26.6
31.8
36.8
75.5
54.7
65.4
11.0
11.4
11.8
.625
.625
.625
1.16
1.16
1. 16
1.0
1.0
1.0
.000
.000
.000
.000
.000
.000
10
11
7
.788
1.49
2.61
28.2
42.9
17.9
3.62
4.72
6.29
.519
.519
.519
30.6
56.5
41.3
.80
82.5
. 41.1
84.2
12.2
.625
1.16
1.0
.004
.007
15
4.• 58
67.2
8.81
.526
81.7
.99
.99
.99
.99
.99
.164
8.16·
.164
8.16
.164
8.16
.164
8.16
.164
8.16
Case 4.
TABLE IVa-Case 4-Data table
90
90.8
44.9
90.8
13.0
6.24
1.15
1.0
.017
.025
17
7.81
105.0
12.3
.542
122.0
.99
.163
8.13
100
94.6
48.0
93.9
13.1
6.24
1.16
1.0
.031
.041
28
12.4
:56.1
17.2
.559
176.4
.
.99
.164
8.10
110
95;7
50.3
'94.8
13.3
.625
1.08
2
.045
.056
41
18.5
222.0
22.8
.574
246.6
.98
.164
8.05
1422
Fall· Joint Computer Conference, 1968
3. There is very little difference in varying the
time slice at 120 users and 140 users.
Case 4
simulation. The active user load was varied from
10 to 150 in steps of 10. Refer to Tables IV-a-IVb
and Figures 7a-7e.
The Medium Curve (Figure 3) was used in this
TABLE IVb-Case 4-Data table (continued)
Number of Users
Percent
Utilization
Average
Time (Sec:)
New
\ Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
Long Jobs
System
Short Jobs
Long Jobs
120
96.4
52.9
95.5
14.4
.626
1.05
3
130
97.0
55.6
95.9
14.0
.63
10.0
3
.063
.075
52
24.3
275.1
23.7
.593
285.2
1.00
.164
8.18
140
97.1
58.1
96.1
14.1
.63
.97
4
.11
.08
.095
56
29.6
316.1
28.1
.61
342.5
1.00
.16
8.12
Compute Load =Medium
Time Slice =933 ms
Number of USers = Variable
Table IVb. Case 4 - Data Table (continued)
Case 4.
.12
64
35.2
3f:IJ.2
30.1
.64
385.9
1.00
.16
8.1
150
97.2
fIJ.7
96.3
14.6
.63
.93
4
.15
.15
77
40.8
398.8
30.0
.67
414.3
1.00
.16
8.0
100
90
80
70
~
z
f:IJ
«
N
50
::>
::>
40
0
;::
::;
;::
CI..
u
30
20
10
0
0
50
100
150
NO. OF USERS
FIGURE 7a-Case 4-CPU utilization
200
Simulation Study of Resource
30
Man~~lIlellt
1423
400
u
UJ
~
~
300
IUJ
Z
§
0.::
200
Z
oe(
~
al
0
.....
100
~
z
9
OL-------~-------+--------~----~200
o
50
100
150
~-------r------~~------~-----~
o
o
NO. OF USERS
50
100
150
200
NO. OF USERS
FIGURE 7b-Case 4-System mean response time
FIGURE 7d-Gase 4--Long job mean response tIme
~
10
~
~
~
~
--------------------~----. LJ
8
i=
w
z
6
~
2
Z2
0.::
~
Z
.6
~
4
Z
0
u
oe(
.8
UJ
VI
~
i=
1.0
.4
oe(
~
2
al
~
0.....
------~---------------.
SYSTEM
• SJ
0
It:>O:
50
0
100
150
.2
200
0
:I:
VI
0
0
50
NO. OF USERS
FIGURE 7c-Case 4-Mean compute time
Conclusions
1. 100 active users is a reasonable upper limit.
2. Short job response times are very good.
100
150
200
NO. OF USERS
FIGURE 7e-Case 4-Short job mean response time
Case
I)
Using the Medium Curve with a load of 80 ac. tive users, the time slice was varied from 4.0
seconds down to 0.4 seconds. Refer to Table V and
Figures Sa-Sf.
Fall Joint Computer
1424
Conference~
1968
..
FIGURE 8b-Case 5--System mean response time
FIGURE 8a-Case ~-CPU utilization
100
..
90
15
80
70
~
60
~
~
~
VI
Z
W
i=
0
W
i=
<
N
::::i
i=
:::>
:::>
VI
Z
0
A-
50
VI
~~
:;;~
)oW
40
A-
u
10
5
VI~
30
20
o
o
10
3.0
2.0
1.0
4.0
TIME SLICE (SEC.)
0
0
3.0
2.0
1.0
4.0
TIME SLICE (SEC.)
Percent
Utilization
Average
Time (Sec.)
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Case 5.
Table V.
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
Long Jobs
System
Short Jobs
Long Jobs
Compute Load = Medium
Time Slice = Variable
Number of Users = 80
Case 5 - Data Table
4.0
82.8
56.4
87.7
63.5
.82
1.25
6
.41
.~
4
1.1
81.8
4.15
1.33
154.0
.99
.32
34.8
3.0
83.2
54.8
87.8
63.7
.80
1.25
5
.31
.45
4
1.1
80.8
4.0
1.2
151.8
.99
.32
34.8
2.5
81.9
52.5
86.5
30.0
.78
1.23
5
.23
.34
8
2.5
84.1
5.8
.99
120.3
.99
.26
17.1
2.0
81.9
49.7
85.7
20.7
.74
1.21
4
.15
.22
11
3.3
80.4
7.0
.82
106.2
.99
.22
12.8
Time Slice (Sec.)
1.0
.933
82.4
82.5
46.fk
41.7
41.1
84.7
84.2
84.2
12.5
15.3
12.2
.69
.63
.63
1.18
1.16
1.16
2
1
1
.067
.01
.004
.10
.016
.007
15
13
15
4.0
4.5
4.6
73.2
68.1
67.2
8.0
8.7
8.8
.54
.65
.53
92.0
83.0
81.7
.99
.99
.99
.19
.17
.16
9.9
8.34
8.16
1.5
81.8
TABLE V-Case 5-Data table
.8
82.1
39.1
83.1
9.2
.~
1.13
1
.000
.000
17
5.7
64.0
10.7
.48
75.1
.7
82.2
37.6
82.5
7.9
.58
1.10
1
.000
.000
20
6.3
~.8
11.7
.46
70.4
.99
.99
.14
6.34
.12
5.53
.6
82.1
35.8
81.8
6.8
.56
1.08
1
.000
.000
23
7.0
57.8
12.8
.44
66.1
.99
.10
4.82
.4
82.4
31.7
80.7
5.6
.50
1.04
1
.000
.000
26
7.9
53.6
14.3
.40
~.2
.99
.08
3.99
Simulation Study of Resource Management
36
1.4
U
w
30
1.2
~
~
UJ
1.0
t=
0
~
~
;:::
w
VI
Z
.8
2
20
~
I-
0<:
::J
~
.6
Z
oc(
0
u
~
Z
.4
OD
<{
:E
1425
Q
10
I0<:
.2
0
J:
VI
0
SYSTEM
SJ
o
1.0
1.0
2.0
3.0
4.0
TIME SLICE (SEC.)
4.0
3.0
2.0
0
FIGURE 8e-Case 5-Short job mean response time
TIME SLICE (SEC.)
FIGURE 8c-Case 5-:Mean compute time
98.1% @9SEC.
100
80
150
70
~
VI
OD
0
.....
~
~
t=
w
60
-I
;t
100
50
u..
0
VI
Z
0Q"
'*
~
0<:
40
30
Z
oc(
~
50
OD
20
<'
10
Q
Z
0-I
o L-------~---------r--------~------~
o
1.0
2.0
3.0
4.0
TIME SLICE (SEC.)
o
1.0
2.0 3.0
4.0
5.0
6.0 7.0
8.0
9.0
12.0
SYSTEM RESPONSE TIME (SEC.)
FROM CASE 5:
MED. CURVE, 80 USERS, 3 SEC. TIME SLICE
FIGURE 8d-Case 5-Long job mean response t.ime
Conclusion
A three-second time slice is best.
Case 6
The Heavy Curve (Figure 3) was used in this
FiGURE Sf-Case 5-Distribution of job response times
simulation. The active user load was varied from
10 to 120 in steps of 10. Refer to Tables Vla-Vlb
and Figures 9a-ge.
Fall Joint ComputerConference 1968
1426
f
TABLE Vla-Cf!oSe 6-Data table
I
Percent
Utilization
Aver-Oge
Time (Sec.)
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
Long Jobs
System
Short Jobs
Long Jobs
10
13.0
4.4
14.9
17.6
.63
1.88
1
.00
.00
2
.01
1.7
2.6
.52
20.7
1.56
.16
13.7
20
29.S
10.0
33.1
17.9
.63
1.87
1
.00
30
47.3
15.4
51.0
18.5
.63
1.87
1
.00
65.4
20.7
68.0
19.3
.63
1.86
1
.00
.00
.00
.00
6
3
.re
5.3
3.0
.52
24.8
1.56
.16
13.7
.
.33
12.8
3.9
.52
31.4
1.56
.16
13.7
40
7
.99
27.8
5.S
.52
49.6
1.56
.16
13.7
Number of Users
70
50
60
96.0
82.0
93.3
28.8
25.5
30.6
92.8
95.2
83.3
20.5
19.7
20.1
.63
.62
.63
1.77
1.85
1.83
1
1
1
.00'
.00
.00
.00
.00
.00
8
2.4
56.8
8.4
.52
78.2
1.56
.16
13.7
15
6.3
132.3
16.2
.52
156.2
1.56
.16
13.7
22
13.3
263.4
30.0
.52
297.0
1.55
. '6
13.6
80
96.8
32.1
96.0
20.6
.62
1.71
1
90
97.3
33.7
96.5
22.1
.63
1.66
1
.00
.003
.006
.002
34
20.6
387.5
40.4
.52
433.6
1.56
.16
13.7
47
~8.1
498.0
45.7
.52
SU.3
1.59
.16
13.8
Compute Load = f:ieavy
Time Slice =933 ms
Number of Users =Variable
Table Via. Case 6 - Data Table
Case 6.
Number of Users
Percent
Utilization
Average
Time (Sec.)
New
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
Long JQbs
System
Short Jobs
Long Jobs
120
97.7
39.4
97.0
22.4
.63
1.4
2
.02
.03
75
48.2
725.2
56.5
.55
783.3
1.57
.16
13.5
Case 6.
Compute Load = Heavy
Time Slice = 933 ms
Number of Users = Variable
Table Vlb. Case 6 - Data Table (continued)
TABLE Vlb--Cs.se 6-Data table (continued)
100
HO
97.5
35.6
96.7
21.7
.63
1.58
1
.006
.01
97.6
37.5
96.8
21.9
.63
1.51
2
.012
.02
64
41.5
656.8
56.1
.54
726.8
1.58
.16
13.6
54
34.7
580.8
52.5
.53
645.7
1.59
.16
13~7
Simulation Study of Resource Management 1427
100
15
.---------------------~.
90
LJ
80
10
70
~
(JJ
Z
Q
....
~
50
5
~
i=
::>
'::>
0..
40
U
••-.----.-.-.-~~.-. SYSTEM
30
o ~~=====T========~==~S~J
o
20
50
100
__~______~
ISO
200
NO. OF USERS
10
FIGURE 9c-Case 6-Mean compute time
0
50
0
100
200
150
. NO. Of USERS
FIGURE 9a-Case 6-CPU utilization
800
700
(JJ
~
e
i=
w
Z
V
w
e
~
w
Z
40
~
400
~
300
'"Z
30
~
2
III
0..,
In
W
:E'"
wZ
SOO
In
i=
In
(JJO
~
50
20
200
C>
Z
0....J
t;;~
~:E
100
10
0
0
50
0
0
50
100
200
150
.100
150
NO. OF USERS
NO. Of USERS
FIGURE 9d-Case 6-Long job mean response time
FIGURE 9b-Case &-System mean response tim~
.5
•
•
•
•
•
I
•
•
•
r
.~
o L---------~---------_+------------r_-----~
o
50
100
150
200
NO. OF USERS
FIGURE 9&-Case 6-Short job mean response time
200
1428
Fall Joint Computer Conference,. 1968
Case 7
Conclusion
1. 60 active users is a reasonable upper limit.
2. Short job response time is very good.
Using the Heavy Curve with a load of 50 active
users, the time slice was varied from 4.0 seconds
down to 0.4 seconds. Refer to Table VII and Figures 10a-tOf.
TABLE VII-Case 7-Data table
Percent
Uti Iization
Average
Time (Sec.)
New'
Job
Queue
Old
Job
Queue
Mean
Response
Time (Sec.)
Mean
Compute
Time (Sec.)
Facility 1
Facility 2
CPU
Facility 1
Facility 2
CPU
Max. Contents
Avg. Contents
Avg. Time (Sec.)
Max. Contents
Avg. Contents
Avg. Time (Sec.)
System
Short Jobs
Long Jobs
System
Short Jobs
Long Jobs
..
4.0
81.0
36.4
84.7 _
38.7
.88
1.94
3
.13
.30
5
1.4
67.3
6.5
.92
113.1
1.56
.24
26.0
3.0
81.8
33.5
84.8
37.9
.81
1.9
2
.05
.13
5
1.5
66.1
6.3
.74
109.4
1.56
.23
25.4
2.5
82.2
~2.1
84.9
38.0
.77
1.9
2
.03
.08
5
1.4
65.5
6.2
.69
108.2
1.56
.23
25.4
Time
1.5
82.2
28.5
84.1
26.8
.69
1. 90
1
2.0
82.5
30.6
85.0
38.1
.74
1.9
1
.02
.00
.04
.00
5
1.4
64.8
6.1
.65
106.9
1.56
.23
24.9
7
2.0
62.5
7.3
.56
92.2
1.56
.19
18.2
Slice (Sec.)
·1.0
.933
82.0
82.0
25.9
25.5
83.3
83.4
20.6
19.7
.63
.63
1.9
1.9
1
1
.0.0
0.0
0.0
0.0
8
8
2.4
2.3
56.7
57.5
8.2
8.4
.52
.52
78.2
SO.l
1.56
1.56
.16
.17
13.7
14.3
.8
81.2
24.3
82.2
14.9
.60
1.8
1
0.0
0.0
11
3.1
55.4
10.2
.48
72.0
1.5&
.14
10.5
.7
81.0
23.3
81.5
12.8
.58
1.8
1
0.0
0.0
11
3.4
52.8
11. 1
.46
67.1
1.56
.12
9.1
.6
80.6
22.1
80.6
11.0
.56
1.7
1
0.0
0.0
15
3.8
51.3
12.2
.44
63.6
1.56
.10
7.8
.4
80.3
19.5
79.5
9.0
.50
1.7
1
0.0
0.0
15
4.4
49.1
13.9
.40
59.1
1.56
.08
6.4
Compute Load = Heavy
Time Slice = Variable
Number of Users = 50
Table VII. Case 7 - Data Table
Case 7.
FIGURE lOb-Case 7-System mean response time
FIGURE lOa-Case 7-CPU. utilization
100
90
15
80
u
w
70
l
Z
Q
...
~
::::i
;:
;:)
e
60
10
50
40
Z2
u
30
20
o L...._ _ _ _ +1_ _ _ _-+1_ _ _ _-+1_ _ _ _-+-1
o
1.0
2.0
3.0
4.0
10
TIME SLICE (SEC.)
0
0
1.0
2.0
TIME SLICE (SEC.)
3.0
4.0
Simulation Study of Resource Management
I
FIGURE lOe-Case 7-Mean compute time
____~--~----------LJ
25
~
20
i=
15
U
w
1429
FIGURE lOe-Case 7-8hort job mean response time
1.0
~
~
w
~
:::>
~
.5
10
u
Z
5
<
~
0
0
1.0
2.0
3.0
o
4.0
o
TIME SLICE (SEC.)
1.0
2.0
3.0
4.0
TIME SLICE (SEC.)
FIGURE lOd-Case 7-Long job mean response time
150
FIGURE lOf-Case 7-Distribution of job response times
~
100
~
w
:E
j::
w
VI
100
Z
0
Q..
~
a:::
70
Z
«
:a
~
0-.
50
:::>
Q..
40
U
30
20
10
0
0
50
100
,...
60
150
USER LOAD BAN D
150
200
10
II
12
13
1430
Fall Joint Computer Conference, 1968
Conclusion
A two-second time slice is best.
CONCLUSIONS OF THE SIMULATION STU.D,Y
CPU load curve
The parameter having the most profound effect
on the system is the actual compute load generated by the users. This simulation used three
different compute load curves. Using any of the
curves, the system seems to be able to deliver
acceptable response tiine to the users when CPU
utilization does not exceed 90 %. If user loads are
increased, where '95-98 % CPU utilization is seen,
response times become unacceptable. As long as
CPU utilization is 90 % or less, the system has
"reserve compute power" to work off temporary
overloads.
Figure 11 illustrates CPU utilization versus
number of active users for the three compute
loads (Standard, Medium, Heavy). Notice that at
90% CPU utilization the system can handle ~
maximum of about 150 users with the Standard
Curve. The Heavy Curve provides a lower lim-it
of about 50-60 users with 90 % CPU utilization.
We now have a "band" of how many users the
system can handle as a function of the CPU load
curves.
Time slice
The effect of varying the time slice on system
response time is a phenomenon that has not been
covered in any known literature. Up to now there
have been only opinions as to what the time slice
should be. It is interesting to note that the best
time sl,ice seems to be that value which maximizes
the CPU utilization.
BIBLIOGRAPHY
1 HCANTRELL
Presentation given at Workshop on Models jor time-shared
processing at the symposium on computers and communication,
their system interaction
Sponsored by the IEEE Communications Technology Group
and the Computer Group January 1967 in Santa Monica
California unpublished
2 GMAMDAHL
IBM Fellow
Menlo Park California
3 General purpose simulation system 1360 user's manual
IBM H20-D326-D
4 A LSCHERR
An analysis of time-shared computer systems
June 1965
Performance of a simulated multiprogralnming system
by MEIR M. LEHMAN and
JACK L. ROSENFELD
Thomas J. Watson Research Center
Yorktown Heights, New York
INTRODUCTION
In a recent paper,t A. Sch~rr discussed main storage fragmentation and other aspects of the behavior of the MVT option of OS/360 (Multiprogramming with a Vari~ble Number of Tasks).
The behav~or of MVT running on a System/360,
Model 65 CPU was deduced from observations and
measurements on a model.
The model simulates a number, fixed for each
run, of initiator-terminators (I/T's) each of
which accepts a job request from an input stream
and retains control of its execution until completion. On completion of any job, the I/T that
had controlled it accepts a new job from the input
stream and remains with that job until it, in turn,
terminates. The storage and CPU power required
by the I/T's themselves were ignored in the model.
Each job consists of several job-steps to be
executed in sequence. Each job-step is described
in terms of three attributes, storage space required, execution time and wait factor. The· execution time is the t'Otal CPU time required by the
step, that is the CPU time that would be observed
if the job-step were running alone in the system.
The wait factor is the percentage of its running
time (total core residence time) that a job-step
would be in the wait state (for I/O, for example)
if it were running alone in an actual system.
A job-step that has been initiated will either be
waiting f'Or main storage space or may have had
main storage space allocated. In the latter case, it
will share the CPU power with other job-steps
then resident in core. The maximum level of
multiprogramming will thus be limited by either
the number of I/T's 'Or by the size of the store.
All I/T's controlling job-steps awaiting the
availability of an appropriately sized block of
. storage are queued. When storage becomes available on termination of a job-step, an attempt is
made to fit each waiting job-step into storage on
the basis of a first come, first served discipline.
The simulated system satisfies each request for
storage from the first empty region found that is
large enough. The search for an empty region
proceeds from the top of main storage. Upon allocation an· empty region is generally split into two
regions: 'One, at the top end, being allocated to
the job-step, and a new, unused region being
created at the bottom end. As soon as a job-step
terminates, its storage is released and is coalesced
with any neighboring free storage. The next step
for that job, or the first j'Ob-step of a new job, is
'Obtained, and its initiator is placed at the bottom
of the queue waiting for main storage. It is, of
course, possible that this new request may be imlnediately granted.
The job-step that has been in storage l'Ongest is
given the highest priority for execution, and runs
a.s if it were alone. Thus, its run time equals the
specified execution time divided by one minus its
wait factor. Run times for other jobs are multiplied by expansion factors (see Table 1) 'Obtained from a simple Markov model, to allow for
the fact that each j'Ob can run only when all jobs
'Of longer residency in storage are in the wait
state. Thus, the e..xpanded execution time in the
model represents the sum or the execution time
and forced idle time due to CPU unavailability in
an actual· system.
Scherr's experiments were performed while
executing a "standard" job-stream containing
FORTRAN, COBOL and Sort jobs. The mix from
which the stream was· generated c'Ontained 21 jobs
comprising a total of 97 job-steps (compile, link1431
1432
Fall Joint. Computer Conference, 1968
TABLE I-Expansion factor
EXPANSION FACTOR
Level of
Multiprogramming
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
65% Wait Time
90% Wait Time
1.00
1.19
1.63
3.13
12.56
230.61
over 1,000
1.00
1.01
1.02
1.04
1.06
1.09
1.14
1.20
1.30
1.48
1.84
2.83
6.96
47.82
over 1,000
"
II
"
"
"
"
"
'"
b. No large jobs were delayed indefinitely dur-.
ing any of the simulation runs, despite ·the
fact that the allocation procedure favors jobsteps requiring little storage.
c. Dynamic relocation, modelled in these experiments by single register relocation, does not
appreciably increase throughput.
d. Other job-streams with larger, longer-running steps were simulated without yielding
appreciably different results. As the number
of liT's was increased, the. average number
of job-steps held in 'core invariably approached the ratio of the size of allocatable
storage to the time-average job-step size.
Maximum main storage utilization rarely
left the 80-90 % range.
Extensions to the experiments
edit, or gO). Average job-step core requirement
was lOOK with the actual distribution shown in
Table 2.
TABLE 2-Core requirements of job-steps in the standard mix
Core Size
Required (bytes)
Number of
Job-Steps
230K
220K
88K
17K-83K
3
15
36
43
Average job-step execution time was 62.8 seconds, and Scherr used a constant wait factor of
65 % in all his experiments. Scherr mentions that
this level is typical for many Model 65 installations. The job-stream was obtained by random
selection of a job by an liT from an infinite pool
of jobs distributed as in the mix whenever the
lIT terminated its previous job assignment.
Scherr's main conclusions
Scherr presents a number of conclusions:
a. System throug hput is basically unaffected
by storage fragmentation, since given
enough liT's and storage space, the algorithms used ensure· that fragmentation merely affects the order in which jobs are completed.
The present authors raised the following questions not addressed in Scherr's study:
a. Can more discrimination be obtained in the
model, so as to enable observation of system
behavior when it is storage-rather than
1/1'- or CPU-limited?
b. What are the maximum delays and the distribution of delays suffered by jobs? How
are these related to job storage requirements, job e.~ecution times, the number of
lIT's, and system storage capacity?
c. What is the time behavior of the model?
d. How does system behavior change when the
core requirements of individual job-steps
are chosen from continuous rather than
from discrete distributions? In the mix
used by Scherr, for example, 15 job-steps
required exactly 220K· bytes (Table 2).
e. While dynamic relocation has no significant
effect on system throughput and storage
utilization, how does it affect relative performance on the various jobs of the job mix?
New experimental assumptions
Run time
In the 'course of extending Scherr's investigation, some changes were made in the values of the
parameters used. In particular, most of our runs
were undertaken with a fixed execution time for
all job-steps, equal to the mean run time of the
standard mix. This was done to permit analysis
Performance of Simulated Multiprogramming System
as a function of only one variable, the storage requirement.
The measured effect of using a constant runtime for all job-steps was to increase throughput
by 19 % at most. There are two basic reasons for
this increase. The first is that when all job-steps
require the same amount of processing time, the
job-steps terminate in precisely the same order in
which they are allocated. Thus, a regular pattern
of storage aJlocation is established. This pattern
favors the fitting of job-steps into core. Secondly,
in the standard job stream, some of the job-steps
requiring the smallest amount of storage are those
requiring large amounts of processing time. When
aJIocations are made to these job-steps, storage
tends to remain fragmented for long periods of
time, decreasing throughput when the system is
storage-limited. Despite the assumption of constant execution time, however, the results reported
are qualitatively correct, as evidenced by runs in
which the assumption was discarded.
Wait factor
The 65 % wait factor used by Scherr, although
determined to be realistic for the job load and
the S/360, Model 65 hardware configuration considered by Scherr, does not yield much discrimination. That is, the CPU app·roaches 100% utilization with only 4 or 5 job-steps in storage, and performance measurements increase very rapidly as
the number of job-steps in storage changes. 'To
increase discrimination and to reveal more of the
fundamental properties of the system, most of the
present experiments were first performed with 2.
wait factor of 90
Confirming experiments were
then undertaken at the 65 % wait level, and also
for the actual run times specified in the job mix.
ro.
1433
suIts of some further runs support this as illustrated for example in Figure 5.
Predicted results
Among the quantities measured were turnaround time, delay to job-steps, number of jobsteps allocated to core storage, core storage utilization and processor utilization. These quantities
are all closely interrelated, and derivations of their
relationships are given in the Appendix. A summary of the relationships follows:
(1) Throughput is given by
TP = 3600 IT, job-steps per hour
=
779 IT jobs per hour,
where T represents the mean execution time
for a job-step in seconds. This is valid only when
the amount of core storage and the number of
liT's are large enough to make CPU power the
limiting resource.
(2) Turn-around time (TAT) for a job-step is
measured from the time when the liT for the jobstep initially requests core storage allocation to
the time when processing for the job-step is complete. The mean job-step turn around time is
given by
TAT =
limited)
Nit
X 3600/TP (=
Nit
X T when CPU-
where TAT is in seconds and N it is the number of
liT's
(3) The delay to a job-step is the difference between the turn-around time for that job-step and
the time in which the job-step would have been
completed had it been the only one in the system
This is given by
Initial transients
Early experiments indicated strong initial
transients. Thus, the first 5000 job-steps were
generally processed without statistics-gathering.
Measurements were then taken over the next 10,000 job-steps. These figures suggest that an actual
installation would not necessarily ever reach
steady-state. They were used, nevertheless, to enable. the determination of some system mean-performance values. However, the cyclic behavior
subsequently discovered and described below indicates that the so-called, start-up transient were~ in
fact, part of the general cyclic pattern. The re-
DELAY = TAT -RTj"
where RT j8 is the mean job step run time. Th~
average delay to all JOE-steps, as the amount of core
increases, approaches T(N it - 1/ (1 - w))
(4) Let L be the effective level of multiprocessing (L ~ Nit)' that is the number" of job-steps
that receive, say, at least 1 % of CPU time when
the average CPU utilization is, say, 99% (See
Table 1 and Appendix). Also let the mean storage
requirement per Job be S. Then for a total (jobavailable) storage capacity in excess of LS, the
1434
Fall Joint Computer Conference, 1968
system will increasingly tend to delay job-steps
requiring small amounts of core storage as a result of being able to more effectively process jobsteps requiring large amounts of core storage. In
fact, delays to all job-steps will approach the general mean delay as in (3) asymptotically. Thus
storage capacity (job-available) of order LS
represents a point of discontinuity of the system
job-delay characteristic as a function of available storage.
Result8
Throughput as a function of core size
Typical of the type of results obtained is the
plot of throughput vs. core size shown in Figure
1. This is shown for values of the wait factor,
0.65 and 0.90 to illustrate the effect that increasing the wait factor has in expanding the horizontal
scale, thus increasing discrimination. Note that
8·S core size increases, throughput increases, rapidly at first but then more slowly as the additional
job-steps for which core storage is allocated contribute less and less to throughput. This decreasing contribution to throughput is implied by Table
1, which shows that the first few job-steps allocated use virtually all the CPU resources. The
asymptotic behavior of the curves occurs because
the system is CPU-limited as core size increases.
The asymptotic value of the measured throughput
is 57.4 job-steps per hour, which agrees with the
predicted value discussed in an earlier section.
Turn-around time as a function of core size
Figure 2 shows measured turn-around time and
delay as functions of core size. Figures 1 and 2
verify the predicted inverse relationship between
mean turn-around time and throughput. Job-step
turn-around time distributions as a function of
total available storage are given in Tables 3, 4 and
5. For Table 3, wait time is 90 %; in Table 4 and
5 it is 65%. For Tables 3 and 4 all job-steps require 62.8 seconds of CPU time, that is turnaround time when running alone in the system
would be 628 seconds and 180 seconds respectively. For the experiments of Table 6, actual jobstep times were used. Thus the first two tables
4500
4000
-
(NIT= 15)
W=0.9
CI)
0
Z
60
3500
0
0
1.&.1
~ 3000
1.&.1
::e
t=
50
cr
.... =>
=>0
0
Z
:::>
40
2500
0
0::
0..::I:
::I: 0::
1'>
=>0..
i~ 2000
::I: 0..
... 0
zZ
z ....
1.&.11.&.1
LIJ
:::>1.&.1
~ en 30
.... LIJ
. c(
c(c(
::e::e
en
LlJCD
1500
::eo
TURN -AROUND TIME
3
1000
10
(NIT =15)
CORE SIZE (THOUSANDS OF BYTES)
FIGURE 'I-Throughput vs. core size
500
00
FIGURE 2-Turn-around time and delay vs. core size
Perf"ormance of Simulated Multiprogramming System
TABLE 3-Percentage of job steps with turn-around time in each region (constant job-step time = 62.8 seconds,
w = 0.9)
Turn-around Time (in seconds)
core
size
(in bytes)
600800
8001000
10001200
12001400
14001600
16001800
18002000
250K
350K
400K
450K
500K
750K
1000K
1500K
2000K
35.4
37.3
31.0
35.1
38.5
45.8
42.1
1.9
0.0
0.2
1.4
4.4
4.6
6.6
10.9
23.6
85.1
98.2
1.7
2.5
3.6
3.8
5.9
7.3
11.4
9.5
1.6
8.7
7.7
10.6
10.0
11.4
7.7
5.1
2.7
0.2
0.3
0.9
3.7
3 9
5.3
4.3
2.7
0.7
0.0
0.2
0.9
2.4
2.7
3.3
3.8
3.3
0.0
0.0
4.5
6.2
8.8
7.3
4.4
2.8
3.6
0.0
0.0
worst
case
>2000 (in seconds)
49.0
43.2
36.5
32.8
24.7
17.4
8.3
0.0
0.0
TABLE 4-Percentage of job steps with turn-around times in each region (constant job-step times
w = 0.65)
=
26028
23755
28466
29748
31120
10283
9321
1481
1383
62.8 seconds,
Turn-around Time (in seconds)
core
size
0(in bytes) 200
250K
350K
400K
450K
500K
750K
1000K
2000K
2.3
0.3
0.0
0.0
0.0
0.0
0.0
0.0
200- 400- 600-·
400 600 800
8001000
10001200
12001400
14001600
16001800
18002000
33.2
35.1
26.5
28.1
29.7
3.4
0.0
0.0
3.4
7.5
11.5
9.8
8.8
12.3
23.6
98.7
2.6
9.1
8.1
7.6
6.0
10.2
10.0
1.2
2.5
7.1
3.6
4.6
2.7
1.7
2.3
0.1
3.3
2.0
1.3
2.0
1.1
1.8
3.4
0.0
3.3
0.4
0.9
1.5
l.3
2.9
3.5
0.0
4.5
0.5
1.0
1.6
1.3
2.8
3.2
0.0
8.4
13.6
18.4
19.4
22.4
32.0
8.4
0.0
5.4
7.8
14.5
13.3
14.1
24.0
41.3
0.0
worst
case
> 2000 (in seconds)
31.3
16.7
14.2
12.2
12.6
8.8
4.3
0.0
8900
10457
10150
13362
15499
8608
6471
1319
TABLE 5-Percehtage of job steps with turn-around times in each region (job-step times given in standard mix,
w = 0.65)
Turn-around Time (in seconds)
core
size
0(in bytes) 200
200- 400- 600400 600 800
8001000
10001200
12001400
14001600
16001800
18002000
250K
350K
400K
500K
750K
lOooK
1500K
2000K
15.0
19.6
23.3
23.0
19.0
11.4
1.6
0.6
10.5
16.2
15.6
17.1
23.3
24.9
16.1
14.4
3.5
7.2
5.0
7.4
10.0
12.7
21.0
22.7
2.1
3.6
3.0
4.3
6.7
8.1
13.0
15.3
2.5
3.5
2.0
3.7
3.8
5.1
8.4
8.8
2.2
2.0
1.2
2.6
3.2
3.7
5.0
5.2
J.8
1.1
0.9
2.0
2.5
2.9
2.9
2.3
1.7
1.0
0.9
1.5
2.1
2.2
1.8
1.4
21.1
18.0
22.6
12.2
2.9
0.4
0.0
0.0
8.9
12.4
9.9
11.7
15.6
20.2
27.7
27.6
worst
case delay
> 2000 (in seconds)
30.6
15.4
15.6
14.6
11.0
8.5
2.5
1.8
8094
12956
14834
10383
7314
4930
·3069
203~
1435
1436
Fall Joint Computer Conference, 1968
clearly bring out the delay behavior of the system
as a function of available storage, a pattern less
clear in the third table.
The final columns of each table give the worst
case turn-around time for each core size. We discuss this quantity further in a later section.
In Table 3, one observes that under core-limited
conditions there are three concentrations of delay,
in the ranges 600-800, 1200-1400 and in excess of
2000 seconds. We indicate in the next section that
these correspond to three classes of. job-steps as
grouped by their core requirements.
The data in Tables 3 and 4 illustrate clearly the
very large delays suffered under space-limited
conditions . by the job-steps requiring large
amounts of core storage. Moreover, the abrupt
change in behavior for a core size around 1400K
for Table 3 and 500K for Table 4 corresponds to
the behavior as discussed in a previous section.
More, particularly, for the present job-mix the
average core requirement per job-step (8) is lOOK
bytes. Moreover for w=0.9 the effective level of
Inultiprocessing (L) is about 14 and for w=0.65
L is between 5 and 6 (Table 1). Thus LS for these
two cases is 1400K and between 500K and 600K
respectively. The predicted discontinuity in the
system delay pattern is clearly confirmed in Table
3 and 4. Also, the turn-around time concentration
in the 800-1000 sec'Ond region corresponds to the
limiting TAT given in an earlier section. Thus,
job-steps requiring small amounts of storage are
actually delayed more when storage is freely available and a high degree of multiprocessing 'Occurs
then when the system is storage limited. Table 5
gives dat~ which could be compared to actual data
obtained in an MVT system appropriately loaded
to test the accuracy of the model.
An important practical conclusion from these
results is that merely increasing core size when
the system is CPU-limited has its dangers since it
increases delays to some jQb..,steps and changes the
general pattern of delay behavior.
Time dependencies
An interesting aspect of this study, and one that
explains the delay phenomena discussed above,
has been the observation of detailed queueing behavior with time. The particular nature of the
standard job mix leads to a certain pattern of
queueing behavior. Table 2 breaks down the mix
by core requirements. The critical aspect of this
rnix is the number of job-steps reqUIrIng large
core storage of only two distinct sizes, 220K
(these will be called large job-steps), with the
remaining job-steps considerably smaller. The
consequence of this fact is that the allocation pat
tern is strongly controlled by the presence or absence of job-steps requiring large storage. When
processing for a job-step of a certain size is CQmplete, another job-step waiting for storage alloca.~
tjon and requiring the same amount 'Of storage can
fit into the same place.
Consider the situation in which the system has
a relatively small amount of core storage-say
350K. Only 'One large job-step at a time can fit
into CQre stQrage. Any 'Other large job-step inj ected into the system must wait in the queue for
the availability of an adequately-sized storage
blQck. Suppose now that at some mQment a large
job-step has been in CQre and is terminated at a
m.oment when no other large job-step is waiting
at the head of the queue. Storage will then be allocated to the small job-steps heading the waiting
queue. Even one such job-step will be likely to
fragment storage so that no other large jQb-step
lower d'Own in the queue can then be allocated
storage. As a: result, core storage will cQntinue
tv be allocated only to small job-steps. Gradually
the number of large jQb-steps waiting to be allQcated will increase, because every so 'Often a large
job-step appears in the job-stream. These queue.'
large job-steps will move to the top of the quep
as the smaller jobs are worked 'Off.
Eventually, one of the large jQb-steps-the top
cne in the queue in general-will be allocated core
space, because either all the jobs waiting fQr storage are large job-steps or because of some fortuitous release of large am'Ounts of storage. When
this large job-step's pr'Ocessing is complete, it wi1~
release its large block 'Of storage, and the next
large job-step in the queue will be allocated the
same block 'Of storage, and so on, since the quantized nature of the 'large requests almost guarantees fit. Thus most of the large j'Ob-steps that
have been waiting a long time for storage allocation will have been worked 'Off entirely. However,
there may be some exceptions left on the queue,
because in the presence of predominantly 220K
job-steps one cann'Ot be certain that a 230K step
may not be further delayed.
One or more small job-steps will be allocated
storage when at least all 220K steps have been
processed, and this will reduce the available stor-
1437
Perf'Ormance 'Of Simulated Multipr'Ogramnling System
15
5000
5000
10000
15000
20000
25000 30000
10000
15000
20000
TIME (SECONDS)
35000 40000
TIME (SECONDS)
FIGURE 4-Queue of large job steps vs. time for lOOOK bytes
FIGURE 3-Queue of large job steps vs. time for 350K bytes
age bel 'OW the critical level. The number 'Of large
j'Ob-steps in the queue will then begin t'O build up
'Once m'Ore. The cycle 'Of building up the queue of
large j'Ob-steps and w'Orking it 'Off c'Ontinues indefinitely.
Clear evidence 'Of the cyclic behavior is presented in Figures 3, 4, and 5 f'Or vari'Ous c'Ombinati'Ons 'Of I'Oad parameters. Each sh'OWS several
cycles 'Of the variati'On in numbers. 'Of large j'Obsteps waiting f'Or c'Ore all'Ocati'On vs. time. N 'Ote
that in Figure 3 the peri'Od is appr'Oximately
four hours f'Or j'Ob-steps requiring s'Ome ten minutes 'Of c'Ore residence time. F'Or larger c'Ore sizes,
the peri'Od and amplitude 'Of the cyclic pattern
gradually decreases, because in systems with
larger am'Ounts 'Of c'Ore st'Orage, the large j'Obsteps are m'Ore easily all'Ocated. This is illustrated
in Figure 4, where the system c'Ore size is lOOOK,
compared t'O the 350K 'Of Figure 3. N'Ote that the
scales are different 'On the tW'O figures. Figure 5
sh'OWS the queue 'Of large j 'Ob-steps fr'Om time zer'O,
illustrating that the cyclic behavi'Or 'Occurs fr'Om
the beginning 'Of a run. F'Or this figure, W= .65,
and actual j'Ob-step times fr'Om the standard mix
were used.
S'Ome general calculati'Ons based 'On· mean levels
'Of multipr'Ogramming achieved with I'Oads having
attributes which c'OrresP'Ond t'O the average levels
of the present I'Oad have sh'Own that the 'Orders 'Of
magnitude 'Of the amplitude and peri'Od 'Of the 'OScillati'On are predictable. We d'O n'Ot repr'Oduce
these calculati'Ons here.
It is this cyclic behavi'Or which causes differential treatment 'Of j'Obs and, as will be sh'Own in the
next secti'On, leads t'O very I'Ong delays f'Or j'Obsteps having a large st'Orage requirement. These
results suggest changing the presentall'Ocati'On
15
INITIAL TRANSIENT
- 15000
«
~
~
10000
..J
LIJ
o
Variable sized storage requests
::E
::::>
::E
x«
::E
00
500
1000
1500'
CORE SIZE (THOUSANDS OF BYTES)
FIGURE 6-Maximum delay vs. core size
(i)
lLI
I~
~
~q~~
(f)
lLI
~
~
0
z
:::>
0
0::
1-
(CS =350K)
W=O.9
oz
UlLI
o..::!E
a=O
lLIlLI
1-0::
(f)-
:::>
m@
~o::
~
230K
z
0::
:::>
~
I0::
lLI
~
~
~
(f)
220K
88K J--~
L - ,-
~~ 50-88K
J
-
-
-
-
-
-
-
-
~l...-_ _ _ _ _ _ _ __
1~-~Kft
o
<30K 0
2--4-~6~8~~IO~I~2~14~~16~1~8~2~0>~2~O
RELATIVE TURN AROUND TIMES
FIGURE 7-Distributions of turn-around times
The quantized nature of the core requirements
has already been noted. To determine whether this
has any effect on performance, we ran experiments .with the standard core sizes modified by a
factor uniformly distributed between l+a, and
l-a, where a was observed. This is evidenced in
Figure 8. This .result was at first surprising, since
it was expected that for a=O (the standard mix)
throughput would be greater. This is because
when space for a specified core size is made available, it should be easier for a job-step with identical requirement to fit into the vacated space.
However, it is now clear that only large' job-steps
are affected and the cyclic behavior modified.
Since these job-steps constitute only 18% of the
load, one would expect a throughput deterioration
of less than 9 %, which corresponds to the effect
observed. More appropriately, it implies that the
effect is not so much noticeable in throughput
rneasurements, but could be expected to effect the
delay pattern and was so observed.
Maximum and mean delay to large job-steps
increased considerably for a=O.5 and small system
core sizes. In particular, a small number of jobsteps with very large core requirements (> 300K
bytes) occurs. These job-steps remain in the
queue of job-steps awaiting storage allocation
much longer than they do with the standard mix.
Even for small variations on the standard mix
( a==O.l) , significantly larger delays are experifilnced, on the average, by the large job-steps. This
is shown in Figure 9. This figure, when compared
with Figure 7, confirms that non-quantized storage requests increase storage fragmentation, and
suggests that the delay pattern of an actual. sys-
Performance of Simulated Multiprogramming System
tiO
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2
4
6
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10 12
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RELATIVE TURN-AROUND TIMES
FIGURE 9-Distribution of tum-around times for ex
,
500
30- 50K
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i <3OK~~------------------ ~
.W
0:::
:I:
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1000
1500
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CORE SIZE (THOUSANDS OF BYTES)
FIGURE 8-Effect of spreading core requirements of job steps
upon throughput
-
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tem load might well be worse than that shown in
Tables 3, 4 and 5.
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Dynamic relocation
Another question raised about the allocation
system relates to storage relocation. Scherr indicated that for the experiments he performed there
was no appreciable improvement in throughput
when single register relocation was used. (Single
register relocation implies the capability of moving blocks allocated to job-steps within core storage in order to eliminate storage fragmentation.)
Experiments that confirm this conclusion were
conducted by the present authors. Results are
shown in Figure 10. Throughput is slightly improved, since job-steps that otherwise would not
fit into storage because of the fragmentation can
fit due to relocation.
0-
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• WITH RELOCATION
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CORE SIZE (THOUSANDS OF BYTES)
FIGURE Io-Effect of relocation upon throughput:
1440
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Fall Joint Computer Conference, 1968
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CORE SIZE (THOUSANDS OF BYTES)
FIGURE II-Effect of relocation upon maximum delay
~
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50-88K
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RELATIVE TURN- AROUND' TIMES
Nevertheless, the significance of dynamic -relocation will be seen in the behavior of those jobsteps with very large core requirements-the 230K job-steps. These, in particular, are generally
the ones subjected to the maximum delays. Figure
11 illustrates the decrease in maximum job-step
delay when relocation is used over the delay (from
Figure 6) without relocation. _Another aspect of
the same phenomenon is demonstrated in Figure
12, in which the distributions of relative turnaround time are shown. Comparing this with
Figure 7, one observes that the distributions for
all ranges of job-step core requirements are nearly
unchanged, except for the 230K job-steps. This
distribution changes from one that peaks for
relative turn-around time exceeding 20 to a distribution very close to that for 220K job-steps
The reason for this effect is obvious. When a
220K job-step terminates and relinquish~s its core
storage, another 220K job-step waiting will always'-'
fit in, while a 230K step can only fit if an adequate
amount of neighboring free space happens to be
available. A 230K job-step will therefore tend to
be delayed longer than a 220K job-step waiting in
Queue. With dynamic relocation, this difference
i~ likely to be minimized, since available space
anywhere in core will be made available.
Further work
The authors feel that the present results should
FIGURE 12-Effect of relocation upon distributions
of tum-around times
be validated by actual measurements on an MVT
System. If general agreement is seen, then the
model can be used for system performance prediction and improvement. We are hoping to perform some such experiments.
CONCLUSIONS
The results of the experiments reported here point
up critical aspects of the MVT system and add
considerably to our insight into its oper~tion.
While knowledge 'of throughput (CPU utilization) is helpful in evaluating system performance
when sufficient storage and a sufficient number
of liT's are provided, it has been shown that large
delays may be exp'erienced by certain classes of
jobs. Certain jobs may be kept in the system for
as much as 8 hours as a result of fragmentation.
In an actual operating environment this could be
unJesirable, and some modification to the simple
alallocation algorithm appears advantageous.
It has also been shown that addition of core to
reduce delays is' not an unmixed blessing, since
it radically changes the general delay pattern,
increasing delays to some classes of job-steps. The
insight gained by experilt:lentation of the type desc~ibed suggests algorithm changes and system
Performance 'Of Simulated Multipr'Ogramming System
parameter c'Ombinati'Ons that resuit in desired
patterns 'Of behavi'Or.
APPENDIX
Analysis of interrelations among measured
quantitie8
Throughput
Thr'Oughput (TP) is expressed in terms 'Of j'Obsteps c'Ompleted per hour. If we c'Onsider first that
an indefinitely large am'Ount 'Of c'Ore storage is
available, the number 'Of j'Ob-steps all'Ocated c'Ore
st'Orage will equal the number of initiat'Or-terminat'Ors. The liT resident in c'Ore st'Orage the I'Ongest will receive CPU time whenever its j'Ob-step is
n'Ot in the wait state. Other liT's have the 'Opportunity t'O use the remaining CPU time in 'Order 'Of
c'Ore residence pri'Ority. The relati'Onship between
the pri'Ority of the j'Ob-step and the expansi'On 'Of
the running time has been given in Table 1. Numbers 'Of j'Ob-steps required t'O utilize the CPU m'Ore
than 99 % f'Or vari'OUS wait fact'Ors are given in
Table A.
BATLE A-Number of allocated job-steps required to utilize
CPU better than 90%
Wait Factor
Number of
Job Steps
.2
2
.3
3
3
.4
.5
.6
.7
.8
.9
4
4
6
7
13
Theref'Ore, when the am'Ount 'Of available c'Ore
st'Orage is large en'Ough and the number 'Of_initiat'Or-terminat'Ors is large en'Ough, the CPU c'Onstitutes the limiting res'Ource. The thr'Oughput then
can be determined in terms 'Of average j'Ob-step
time. Thus,
TP = 3600/T
rr
where represents the mean executi'On time f'Or a
j'Ob-step in sec'Onds and TP the thr'Oughput in j'Obsteps per h'Our. The thr'Oughput in j'Obs per h'Our
1441
differs fr'Om this by the fact'Or 'Of 21/97 j'Obs per
j'Ob-step f'Or the particular w'Ork I'Oad used. The
same fact'Or also c'Onverts all subsequent results
fr'Om per j'Ob-step t'O per j'Ob.
N'Ote that if the wait fact'Or is S'O large that the
CPU is n'Ot saturated f'Or the number 'Of j'Ob-steps
allocated c'Ore st'Orage, then the ab'Ove equati'On
d'Oes n'Ot h'Old. This is the case, when the am'Ount
'Of c'Ore st'Orage is n'Ot sufficient to acc'Omm'Odate
en'Ough j'Ob-steps t'O saturate the CPU. It als'O
'Occurs when the number 'Of initiat'Or-terminat'Ors,
in the system is insufficient t'O saturate the CPU.
, The f'Ormer case is the 'One under which many experiments were run. It was not deemed necessary
t'O als'O measure perf'Ormance in the latter situati'On.
Thr'Oughput is clearly related t'O the mean number 'Of j'Ob-steps all'Ocated c'Ore storage and t'O the
mean percentage 'Of available st'Orage allocated.
These quantities can be measured fr'Om simulati'On. The dependency 'Of CPU utilizati'On UP'On the
number 'Of job-steps all'Ocated c'Ore st'Orage is,
h'Owever, n'On-linear, and n'O the'Oretical derivati'Ons are made f'Or the relationship.
Tum-around time
Turn-ar'Ound time (TAT)f'Or a j'Ob-step is the
difference between the time when the liT f'Or the
j'Ob-step initially requests c'Ore st'Orage allocation
and the time when pr'Ocessing f'Or the j'Ob-step is
c'Omplete. The mean turn-ar'Ound time is the sum
of the turn-ar'Ound times f'Or all steps during a
run divided by the number 'Of j'Ob-steps. An expressi'On f'Or turn-ar'Ound time can be derived by
first c'Onsidering 'One liT. At time zer'O, it requests
st'Orage all'Ocation f'Or the first j'Ob-step. When the
pr'Ocessing f'Or that j'Ob-step is c'Omplete, it immediately requests all'Ocati'On f'Or the next job-step,
and S'O 'On until the run is terminated. Theref'Ore,
the c'Ontribution 'Of a single liT t'O the accumulated turn-ar'Ound time is appr'Oximately equal t'O
the time 'Of the run. If Nit initiat'Or-terminat'Ors
are in the system, then the t'Otal c'Ontributi'On to
turn-ar'Ound time is Nit x simulati'On run time.
Theref'Ore, the mean turn-ar'Ound time equals N
x run time divided by the t'Otal number 'Of jobsteps c'Ompleted. Since run time divided by j'Obsteps c'Ompleted is IITP,
TAT = Nit X 3600/TP (== Nit
CPU-limited)
X
T
when
1442
Fall Joint C'Omputer Conference, 1968
where TAT is measured in seconds and 1.'P is in
1ob-steps per hour. Therefore, mean turn-around
time is directly proportional to the number of lIT's
and inversely proportional tQ'the throughput. This
holds true whether or not the CPU is fully utilized and all job-steps are allocated space in core
storage.
_
In this relati~nship, turn-around time is proportional to the number 'Of lIT's in the system
because each added lIT provides the capacity for
accepting another job..step in the system, allowing
it, to wait for storage to be allocated and processing to be perf'Ormed.
Delay
The delay to a job-step is defined as the difference between the turn-around time for that jobstep and the time in which the job-step would
have been .completed had it been the only one in
the system. It follows directly from this definition that the mean j'Ob-step delay equals the mean
job-step trup-around time minus the mean jobstep run time. The latter is mean execution time
divided by 1 minus the wait factor. This diVision
serves to em>and the time into. the time a solitary
job-step remains in the system. Thus, in the case
of a CPU-limited system
DELAY == T (Nit -l/(l-w»
ACKNOWLEDGMENT
The authors grat~fully acknowledge the contribution of J. M. Lee, who coded the present version
of the simulation model, ran most of the eXperiments aJ}d contributed to our understanding of the
phenomena studied.
REFERENCE
1 ALSCHERR
Analysis of main 8torage fragmentation
Proceedings of IBM Symposium on Storage Hierarchy
,Systems
TR 00 1556 December 301966 pp 159-174
Hardware design reflecting software requirements
by SAUL ROSEN
Purdue University
Lafayette, Indiana
INTRODUCTION
What
WU8
promised
All of the features that have been designed into
digital computers may be considered to be, at least
to some extent, reflections of software needs.
Starting with some of the earliest machines, the
EDSACl provided for address modification on input to make it c'Onvenient to use relocatable subroutines. The 4-address code of the EDVAC2 was
designed to make it possible to do minimum access time coding. The Datatron3 provided off-line
tape search, the RCA Bizmac4 and the Univac
File Computer provided special hardware-programmed tape s'Orting machines. FI'Oating point
hard~are5 was introduced on many computers to
eliminate the need for software scaling systems
and for interpretive floating point systems.
New computing systems, and whole new generations of computers have been intr'Oduced at an
astonishing rate. 6 Even the small computers of
a new generation are powerful machines, comparing favorably with some of the very large
machines 'Of earlier generati'Ons.
The c'Omp'Onent design engineers have made
great advances 'Over the years in the devel'Opment
'Of high speed mem'Ories, and in the devel'Opment
'Of circuit c'Omp'Onents that are cheap and fast and
small. There seems t'O be an 'Order 'Of magnitude
impr'Ovement in these areas every few years, and
the c'Oncept 'Of large scale integrati'On 7 pr'Omises
additi'Onal advances 'On the same scale.
It is the j'Ob 'Of the hardware system designers
and the s'Oftware system pr'Ogrammers t'O translate these advances in c'Omp'Onents int'O impr'Ovements in system effectiveness.
Perhaps the m'Ost imp'Ortant part 'Of the j'Ob 'Of
c'Omputer system design is t'O determine which
functi'Ons are best handled by hardware, and
which sh'Ould be pr'Ovided by s'Oftware. All of the
1443
traditi'Onal engineering c'Onsiderati'Ons c'Ome int'O
play here. One must c'Onsider the added C'Ost 'Of
additi'Onal hardware measured against P'Ossible
gains in 'Operating efficiency. One must c'Onsider
the availability 'Of manpower with the appr'Opriate
skills f'Or design and f'Or implementati'On. One
must als'O c'Onsider intangible fact'Ors such as the
inherent advantages 'Of simplicity and the hidden
C'Osts 'Of c'Omplexity.
Fr'Om the P'Oint 'Of view 'Of the c'Omputer user
it makes n'O difference which features are inc'Orp'Orated int'O the hardware and which are programmed in software.
It is the c'Ombined hardware-s'Oftware system,
the "extended machine"* that the user must rely
on t'O pr'Ovide the P'Ower. and flexibility and c'Onvenience that have been pr'Omised with each new
generati'On 'Of c'Omputing equipment. Multipr'Ogramming and interactive systems, pr'Oblem-oriented languages, 'On-line debugging, aut'Omatic
st'Orage and retrieyal 'Of inf'Ormati'On-these and
many 'Other devel'Opments 'Of m'Odern computer
technol'Ogy promise the user c'Onvenience in pr'Oblem statement~ in pr'Ogram preparati'On, and debugging. They pr'Omise t'O make it P'Ossible t'O
'Obtain timely, useful, meaningful results without
the waste of pers'Onnel time and equipment time
that has been S'O characteristic of c'Omputer problem solving.
S'O far at least the promises have not been kept.
Most problems that are s'Olved 'On the new generati'On 'Of c'Omputers are s'Olved very much in the
same way as they were s'Olved 'On earlier c'Omputers. M'Ost debugging is 'Off-line. Pr'Ogrammers,
even in s'O-called higher level languages still wait
thr'Ough h'Ours and days 'Of turn-ar'Ound time f'Or
·The term "extended machine" has been used in this context
by a number of people. To the best of my knowledge it was first
used in this way by Anatol Holt and William Turanski.
Fall Joint Computer Conference, 1968
their octal and hexadecimal dumps. The hardware
machine has changed and developed and improved
at a great rate, but the capabilities of the extended
machine have grown disappointingly slowly.
What we have
It would take a large volume devoted to the subject of- computer organization to discuss all of the
hardware features of existing computing systems
that reflect software needs. There have been many
hardware developments that have contributed to
the development and the perforinance of multiprogramming and multiprocessor operati:ng sys;,.
terns and compiling and translating systems. A
few of these are discussed in this section.
Microprogramming
The word microprogr~mming has been used in
a number of different though related ways from
the earliest days of computer design. 8
In the most usual current usage of the word a
computer is said to be microprogrammed if it
interprets the user or programmer instructions
(add, multiply, branch, etc.) as calls on routines
(the microprogram routines) stored in a microprogram memory. These routines are themselves
sequences of the more elementary operations that
are built into the machine hardware. For reasons
of speed and economy in the technology now available, the microprogram memory is usually a readonly storage device. 9
For this reason, the microprogram routines are
usually designed and written by hardware engineers rather than by software programmers.
There are microprogrammed computers in
which the microprograms are stored in fast readwrite storage which is logically or even physically
the same as the ordinary program and data storage of the computer. The elementary operations
of the computer thus become available to the problem programmers. This kind of system may in a
sense permit each programmer to design his own
instruction code. If that were true on a sufficiently
basic level, it would be very difficult to supnly software in the s~me s~nse as it is now supplied. Typically, in such systems. only software programmers (i.e., systems programmers) are permitted
to design instructions.
Microprogramming in a read-only memory is a
relatively simple, easy to understand technique
1444
whereby it is possible to "build-in" quite complex
operations.
It makes it clearer perhaps than it was before
that much of the sequencing that is done by hardware is the same kind of thing that is done in
programming.
With the popularization of microprogramming
it is easier to talk about performing some traditional software functions in the hardware, i.e.,
in programs on the elementary operation level
1'ather than pn the instruction level.
Such programs could be done in the hardware
without the formalism of microprogram control.
We shall use the term hardware programming
to indicate programming built into hardware,
either through a microprogramming system or by
other hardware sequencing methods.
Emulation and simulation
One of the most successful applications of the
recent microprogramming technology is in the
simulation of computers on computers.
The microprogram control and the set of microprogram routines are in effect a simulation program that simulates the programmer's instruction
set on a computer whose instruction set is the set
of elementary operations. It may be equally possible to simulate computers with other programmer instruction sets in terms of the same set of
elementary operations. This, slightly oversimplified perhaps, is the idea of hardware assisted
simulation that is now usually called emulation.'1°
Simulation of one computer on another had been
done for many years using the programmer instructions. The resulting systems were inevitably
so slow as to be almost useless for general computation, and were limited in use to special applications such as checkout, etc. The speed that makes
emulation practical for much wider areas of ap-plication can only be achieved by operating at the
hardware level.
Interrupt systems
One of the critical areas in most operating systems is the handling of interrupts, especially routine input-output interrupts. The time it takes
to recognize an interrupt. handle the functions required by the interrupt. initiate new onerations
,vhere needed. and finally return to the interrupted
program, is usually 'one of the most important performance parameters of the system. If a great
Hardware Design Reflecting Software Requirements
many instructions must be executed in response
to each interrupt, an otherwise fast computer may
become intolerably slow.
1'his is an area of programming in which the
programmer deals directly with the idiosyncracies
of the computer hardware. It is, almost by definition, an area that cannot be handled by software
alone. Much of the programming here is best done
at the elementary operation level. There are many
hardware features of many computing systems
that have been designed in response to the need
for efficient handling of interrupts. Some of these
perform the following functions.
1. Identify the device that interrupted, either
by transferring control to a location that
is specific to that device or class of devices, or by storing a device identificati'On
code in a special register or storage location.
2. Provide special locations into which information about the state of the device is
automatically rec'Orded.
3. Provide for automatic storage of the most
important registers that will then be automatically restored when the interrupted
program is resumed.
4. Switch automatically into a speecial supervisory mode. In some systems the special
m'Ode has its own instruction control register and its own special registers for
temporary storage and for control functions.
Also important in this area are hardware devices that cut down on the number of interrupts
that have to be handled by the central computer.
An example is the so-called multiplexer channel
that automatically transfers streams of inform"
tion between core memory and a large number of
slow devices, interrupting the central computer
only at the beginning and end of each stream.
Dynamic storage allocation
There have been a nun;tber of interesting and
useful hardware developments to assist in the
allocation and addressing of storage. In the Bur"
roughs 5000-6000-700011 series an array ('Or a subprogram) may be addressed as if it is present in
main memory even though it may actually be in
peripheral storage. Addressing is indirect, by way
of a descriptor. A "presence" bit in the descriptor
causes an interrupt if the addressed array (or sub-
1445
program) is not in core storage. The supervisor
may then fetch it from peripheral storage and
place it, without change, in any area of core memory that is large enough to hold it. The origin
of the assigned storage area is placed in the descriptor, and all subsequent references to any
elements are interpreted as relative to this origin.
The descriptor also contains the length of the
array and the hardware automatically checks f'Or
and interrupts on any reference beyond the limit8
of the array.
Another, perhaps more influential design was
the Atlas one-level storage system. 12 In that system core storage is organized into 512-word pagesJand programs are organized into 512-word blocks.
A block in peripheral storage may be loaded into
any page in core storage. The block number is
placed in a page address register. The page address registers form an associative memory" that
is searched by hardware. A program address that
consists of a bl'Ock number and a displacement
within the block is automatically translated into
a hardware address that is a page number and
the same displacement within the page. A reference to an address in a block that is not physically
present in memory causes an interrupt to the
supervisor which will fetch the block from peripheral storage and place it in any available
page and place its block number in the page address register for that page.
A three level addressing scheme1.3 was introduced on the General Electric 64514 and on the
IBM 360 model 67. 15 There a program address is
interpreted as a segment number, a page number,
and a displacement. An active segment has a page
table which correlates physical page numbers with
logical block numbers. A segment table gives the
location of the beginning of the page table for"each
segment. A program address is converted into a
hardware address by an automatic two level table
look-up. In both the IBM and GE systems a small
associative memory stores a few of the most recent translations, and the address translation is
very much speeded "up if the segment-page combination has been used recently enough so that its
translation is still available in the ass'Ociative
memory.
The GE645 and IBM 360/67 address translation
system, and other hardware address mapping
schemes that were introduced since the Atlas development were designed as hardware ::lids tn
time.sharing systems. Computer manufacturers.
I
, 1446
Fall Joint Computer Conference, 1968
and many users tend to refer to any computer
that has any kind of hardware address translation
as a time-sharing computer.
It takes much more than adding an automatic
scheme for address translation to an existing
general-purpose computer design to produce an
effective time-sharing system.
Supervisory functions
In m'Ost systems supervisory functions are initiated in response to interrupts, but they are too
varied and complex to be considered as part of the
interrupt system.
With the recent and continuing developments in
integrated circuits and large scale integration it
is becoming both technically and economically
feasible to handle supervisory functions by hardware rather than software programming.
In the input-output area such functions may
include the maintenance of input-output 'queues,
the handling of priorities and issuance of inputoutput commands, the response to error conditions
and other special c'Onditions.
In the job management area they include once
again the management of priority queues. They
also include the handling of address translation
tables in systems that provide automatic translation, and more generally the management of a
multi-level hierarchical storage system.
There are dangers and pitfalls in attempts to
handle these functions in the hardware. Program8
'On the microprogram level may become excessively
long. They may be difficult or even imp'Ossible to
debug. Hardware programmers are not necessari1y better than software programmers. They make
errors that must be corrected. Their first versions
of programs are often incomplete and inefficient
and must be replaced by later better versions
Hardware programming for really c'Omplicated
tasks will only be feasible when it is relatively
easy to make changes to the programs.
This is still a research area. It seems reasonably certain that some of the functions mentioned
above will be handled by hardware programming.
Eventually they all may be handled that way.
Compilation
C'Ompilation of programs written in Fortran,
Algol, Cobol and other higher level languages is
another critical area in the performance of software systems. lt is an area in which hardware
programming can and in some cases already does
handle at least part of the job.
With the microprogramming systems that now
exist it is reasonable to handle all of the process
that is usually called lexical analysis on the micropr'Ogramming level. Micr'Oprograms can also be
used in the construction and manipulation of
tables, and to provide arithemetic capabilities not
otherwise provided in the hardware. Much of this
has already been d'One in the Allen-Babcock PL-1
System by adding microprograms to those already
present in the IBM 360/50.
As in the case of supervisory systems, here too
by making use of the integrated circuit and LSI
technologies it may hecome economically feasible
to do the whole compiling process by hardware
rather than by software programming. This too
is a research area, and so far none of the proP'Osed
designs for building higher-level language capabilities into hardware seem both practical and
a ttracti vee '16
The Burr'Oughs 5500-6500-7500 computers represent a very interesting approach in this area.
The machines, especially the later ones, contain
very elaborate hardware programs to help in the
processing and running of Algol programs. One
might, say that the block structure of Algol is built
into the hardware, along with the automatic interpretation 'Of Polish strings and the automatic
handling of push-down lists or stacks. The logic
of the 6500-7500 computers is described in some
detail in.17
TVhat we need
The most important need is for a design philosophy that aims at the design of total, information processing systems, and that will eliminate
the mostly artificial 'distinction between hardware
systems and software systems. We need a continuing development of the trend toward combined
hardware-software programming discussed in
part 2. Practically no 'One would deny that these
are desirable goals, and it would serve little purpose to elaborate on them here. The remainder of
this section will therefore discuss a few more
specific and perhaps less obvious needs.
Peripheral storage
Writers in the computer field have' overemphasized the importance of central processor speeds
and capabilities in discussing the performance of
Hardware Design Reflecting Software Requirements
computing systems. This is understandable, since
there have been such dramatic advances in speed
and compactness of circuits and central memories.
The advances in peripheral storage have been
fewer and less spectacular. Software programs,
along with almost all other information-p:;"ocessing
programs, can profit far more from hardware advances in the area of peripheral storage, than from
improvements in central computer logic and speed
At a SHARE meeting in 1966, representatives
of IBM presented figures concerning the performance of an initial version of the OS 360, the opel"
ating system for the 360 computer. For the areas
.covered in that presentation, the operating system
ran almost as fast with the slow model 40 central
processor as it did with the very much faster
model 65. Both used the same disc storage system, and it was the very frequent reference to
disc storage, not the speed of internal processing,
that was the limiting factor in the performance
of the system.
I have been told that the design philosophy of
OS 360 that permits frequent reference to system
routines resident in peripheral storage, was influenced by a hardware development program that
was to provide very much faster-access peripheral
storage for system residence than is provided in
current disc or drum storage systems.
A peripheral storage system large enough, cheap
enough, and fast enough to permit its use as a
rapid access device for system residence would he
the most important contribution that hardware
designers could make to software systems.
Peripheral core storage devices such as IBM's
LCS and Control Data's ECS are too expensive.
The cost per bit of bulk core is roughly 100 times
the cost per bit of large disc storage (2¢ - 4¢ per
hits vs .. 002¢ - .004¢ per bit). The random access
time differs by a factor of about 10000. The most
obvi'OUS design point between these tW'O W'Ould aim
Ht a device with random access 100 times as fast
as disc at about 10 times the cost per bit-i.e .. access time less than 1 millisecond at a cost of .02¢
to .04¢ per bit.
Software systems deal with file management.
with the cataloging, the storage and the retrieval
'Of information. Catalogues and glossaries must
be kept in peripheral storage. If the files are at
all extensive, the c~talogues must be several levels
deep. One glossary leads to another which in turn
leads to another. all reouiring additional accesses
to peripheral storage. The faster access peripheral
1447
storage mentioned above W'Ould be of great help,
but even there, and more so in connection with
disc and drum systems, hardware that provides
f'Or automatic search, for branching from one
catal'Ogue to another, for parallel readout from a
number of index tracks-these would all provide
major assistance to a large segment of software
programming.
Time sharing
In recent years there has been a great deal 'Of
interest in, and a great deal of effort expended on
the design and implementation of large interactive
time-sharing systems. The results achieved in
1968 are very disapP'Ointing when c'Ompared with
the promises of 1965.
Hardware performance is only one aspect of
time-sharing system perf'Ormance. Improvements
in coinputer hardware alone, will have little effect
without corresP'Onding developments in areas of
s'Oftware and c'Ommunications. However, new computer hardware developments are essential before
the promise 'Of interactive time-sharing systems
can be realized.
There are many general hardware design improvements that are relevant to time-sharing sys·
terns. These include improvements in peripheral
storage, faster channels with greater bandwi~th.
and hardware programming of many operatInp;
svstem functions.
Specific to the time-sharing field there is a need
f'Or the development of adequate c'Onsoles, especially graphical input-output consoles. There are conflicting requirements for low cost and for many
huilt-in features that minimize the load 'On the
central computer. An adequate graphical console
may require built-in hardware equivalent to th~t
required in a fairly sophisticated computer. ThIS
is an area in which anal'Ogue as well as digital
techniques may be imp'Ortant. It is an area in
which the new component techn'OI'Ogies may make
significant contributions.
L
Analysis and debugging
S'Oftware systems, especiallv on large computers
are systems 'Of great complexity. Hardware design
can ano sh'Ould c'Ontribute t'O the analysis, to the
debugging and to the d'Ocumentati'On 'Of such systems.
In order t'O imnrove the performance of a soft",Tare system, we need to be able to evaluate itR
1448
Fall Joint OomPllter Conference, 1968
performance. In the case of a number of c'omputing systems, separate and very complicated
hardware was built to gather information needed
in such analyses. The problem is to get the necessary information without loading the system
and thereby distorting the information gathered.
This can be very difficult to do in software alone.
Hardware aids built-in to the initial design may
represent a trivial cost compared to the cost of
external monitoring equipment that may otherwise be needed.
There has been far too little concern on the part
of the hardware system designers with the problems of debugging of complex programs. Hardware aids to program debugging would be among
the most important hardware aids to software
production. On-line debugging is essential. It
should be possible to monitor the performance of
software on a cathode ray tube console, without interfering with the performance of the software.
It should be possible to examine areas of peripheral storage as well as areas of core storage.
One of the most interesting features of the recently announced IBM 360 model 85 is the microfiche reader built into the system console. This
reader will permit reference to the software documEmtation and at the' same time permit reference
to the state of various hardware registers.
We should perhaps aim for a software system
design and implementation technique that will
make it unnecessary to have a microfiche reader
at the console for debugging and maintenance, but
in systems where documentation has to be voluminous, a simple hardware retrieval system can be
of great value.
Compatibility and standards
Advances in the area of standardization and
compatibility in computer hardware can be of importance to software developments in a great
many ways. There is always a danger that standardization will inhibit progress, but at some point
in time this danger must be faced. Over the years
the computer industry has become accustomed to
change at a frenetic pace, and such change is often
but not always accompanied by progress.
The time may be near, or already at hand when
there should be standardization of computer instructions, of input-output interfaces, of character
sets. Duplication and multiplication of identical
and nearly identical programming efforts is typical of the computer field today. It is hard to over-
estimate' the saving in manpower and computer
power if such duplication could be eliminated.
Standardization of computer hardware would be
the major step in the elimination of such duplication. We tnight even then find that there exists a
surplus and not a shortage of system programmers.
REFERENCES
1 M V WILKES
D J WHEELER S GILL
The preparation of programs for an electronic digita.l computer
Addison-Wesley 19511957
2 Functional description of the EDVAC
University of Penna Moore School of EE Research Division
Report 50-9 under contract W-36-03400RD-7593 with the
Ordnance Dept Dept of the Army Nov 1 1949
3 JCALRICH
Engineering description of the electro data digital computer
IRE Trans on electronic computers EC-4 March 1955 p 1-10
4 W K HALSTEAD et al
Purpose and application of the RCA BIZMAC system
Proc of the WJCC Feb 1956 p 119-124'
.5 S G CAMPBELL
Floating-point operation
In W Buchholz Editor Planning a computer system McGrawHi1l1962
6 SROSEN
Electronic Computers-a historical survey
Document CSD TR 25 Computer Sciences Dept Purdue
University July 1968
7 DFFarina
Large-scale integration: A status report
Datamation 14 Feb 1968 p 22-29
8 M V WILKES J B STRINGER
Microprogramming and the design of the control circuits in an
electronic digital computer
Proc Cambridge Philosophical Society 49 Part 2 April 1949 p
230-238
9 SGTUCKER
Microprogram control for system/360
IBM Systems Journal 6 4 1967 p 222-241
10 JGREEN
Microprogramming, emulators and programming languages
Comm ACM 9 March 1966 p 230-232
11 RSBARTON
A new approach to the junctional design of a digital computer
Proc of the WJCC 1961 p 393-396
12 T KILBURN et al
One-level storage .'3ystem
IRE Trans on Electronic Computers EC-ll April 1962 p
223-235
13 JBDENNIS
Segmentation and the design of multiprogrammed compu,t.er
systems
Journal of the ACM 12 Oct 1965 p 589--602 Reprinted in S
Rosen Editor Programming systems and languages McGrawHi111967
14 R C DALEY J B DENNIS
Virtual memory, process, and sharing in MULTICS
Comm of the ACM 11 May 1968p 306-312
15 B WARDEN B A GALLER T C O'BRIEN
F H WESTERVELT
Hardware Design Beftecting Software Requirements
Program and addressing structure ina time-sharing environment
Journal of the ACM 13 January 1966 p 1-16
16 TRBASHKOW ASASSON AKRONFELD
System design of a FORTRAN machine
IEEE Trans on Electronic Computers EG:-16 Aug 1967 p
485-499
17 AAHAUCK BADENT
Burroughs' B6500/ B7500 stack mechanism
Proc of the SJCC AFIPS Vol321968 p 245-251
1449
What was promised-what we have-and what is
being promised in character recognition
by A. W. HOLT
Control Data Corporation
Rockville, Maryland
INTRODUCTION
head light while reading in bed".
Like the dishwasher, where you have to wash the
dishes first before" you use it, character recognition "machines have certainly not solved the whole
problem of man-machine communications. You
still have to clean up your inputs. On the whole,
however, it seems fair to say that the engineers
have succeeded quite well in delivering what they
promised, particularly if you make" allowance for
the purple prose occasionally delivered by the
Fourth Estate. What we have today is systems
that work well if the sour.ce of character imprinting is controlled. In the future, systems will accept data generated by non-captive sources in the
course of normal business transactions.
'How can we measure what was promised? One
analog method is to look back "ina file of old newspaper and magazine articles. The following excerpts are taken from an article which appeared
on the front page of a big city daily newspaper.
The date was February 26, 1963.
The author was not given a by-line.
To measure what we have is relatively easier
than to measure promises-a list of all constructed
machines will suffice. Since nearly 100 different
types have been built, however, we will confine
the list to the top few, publicity wise.
"Slip that new novel into the scanner. Lie back,
close your eyes and read.
"That restful arrangement-reading with your
eyes shut-came a step nearer to reality today
with the demonstration of a new 'seeing' machine.
"It can already read numbers in ordinary print.
And
said work is going on to refine the
device so it can master the alphabet.
"The development," he said, "points toward the
building of a universal machine that can read anything intelligible, including handwritten material.
"The prospect raises all kinds of novel possibilities. For instance: driving along the highway,
and keeping your eyes on the road, while at the
same time, with your scanner-speaker plugged in
your ears, reading a book of ancient history.
"Yon won't even need an extra pillow or over-
Font
F~rrington
Oil Credit
Card Reader
Control Data 915 Page
Reader
REI Document Reader
IBM 1287
Philco Reader for Post
Office
IBM 1975 Reader for
Social Security
Control Data Reader for
Fort Monmouth
NCR 420
Magnetic Ink Character
Reader (MICR)
Self Check 7B
USASI (ISOA ASA)
407E
Carefully Hand
Printed Numbers
Omni-Font
Omni-Font
Multi-Font, consisting of:
USA-SI
12 Pitch Elite,
Upper and
Lower Case
10 Pitch Pica,
Upper and
Lower Case
NOF
E13b
These machines, and many others, were promised and delivered, but the mere fact of their delivery and acceptance does not really measure
whether they lived up to their promises, because
1451
1452
Fall Joint Computer Conference, 1968
the designers and users were certainly hoping for
applications far beyond the use of only the first
prototype.
A way of measuring the ratio of success of
these machines to the promises made for them
is to count the number of repeat orders. On this
basis the MICR machine certainly ranks five stars
with at least 500, machines in the field, the NCR
420 ranks four stars. The Rabinow Division has
delivered about 100 of the Control Data 915 Page
Readers. The Oil Credit Card Readers certainly
number over 100 and the IBM 1287 has at least
25 machines in the field. REI has at least 10 Document Readers out, and Philco has probably installed at least 4 machines for the Post Office.
Only single models of the rest of the machines
have been built.
The significant point about this list is that by
far the most successful machines have been those
which read a stylized font-that is to say, a set
of character shapes which are very limited in
number and carefully controlled as to quality.
The only exception to this is the good showing
of the Philco Post Office Reader, which is, of
course, required to do its job on an enormous
variety of shapes and sizes of characters. Even
so, the Philco reader has not been successful in
the business data processing market. At another
end of the spectrum, we find the IBM 1287, which
is a machine specializing in the reading of carefully hand printed numerals. Before attempting
to explain why successful machines have primarily
fallen in the category of stylized font readers, we
will present a brief discussion of the construction
and uses for character readers.
Why reading machines are useful as inputs to
computers
First, let us recall that we are not discussing the
entire field of pattern recognition, but only a very
narrow corner.
The major attractiveness of character recognition as a method of input to computers is because
it is entirely compatible with the way humans
communicate among themselves. Why is compatibility good? Because humans produce better accuracy, better verification, better correction and better flexibility using a single language than using
a double language. Also, humans seem to get a
greater feeling of personal security out of using
a familiar set of marks.
There are a number of ways that character recognition can save money over keypunching.
1. The source documents are prepared in such
a way that they are used by humans for
their non-machine purposes and are then
returned to the information collecting station to be machine read. The best example
of this is the preprinted account number on
the bank che~ks.
2. Even when the machine readable document
does not go out into the flow of general
business commerce there are very important
savings that can be realized over the traditional method of key-punching. These are:
a. Higher accuracy. Part of this is due to
the fact that a typewriter keyboard is
more familiar to people than a keypunch
keyboard. Another part of this is due to
the ability of instantaneous verification
r-'
of what key has been stuck (sic) *
b. Wages and training time for typists are
less than for keypunch operators.
c. The format flexibility of an OCR document is almost infinite.
d. The document or page is completely correctible in any part without disjointing
the whole.
What about mark sensing? It has the potential
ability to acquire information from non-captive
humans. Certainly there are some good uses for
it, like exam answering, but it is still a double
language and suffers from all the attendant problems. (It is useful to visualize tab cards as a special case of mark sensing.) The advantages of
OCR recognition machines over various forms of
mark sensing are:
There is more redundancy in a character than
can be built into a mark system. There is considerable space saving. There is also human
compatibility, instantaneous verification, and
correctability. In fact, almost all of the advantages which can be enumerated for OCR over
punched cards can be enumerated over mark
sensing.
On the negative side of the ledger, one would
expect to find that the cost of a character recognition machine is greater than for a mark sensing
machine. True, in comparison with readers for
punched cards, present day character readers are
more expensive. In comparison with readers for
*In the course of rough-typing this paper, a secretary actually
made this mistake and corrected it on the spot as shown.
What was Promised-What We Have-What is Promised in Character Recognition
less .rigidly controlled mark sensing documents,
however, the character reader is very nearly the
same price. The reason for this is that the majority of the machinery to do the two jobs is identical-namely, there must be an input hopper, a
paper pickoff, a paper transport and at least two
output sorting bins. There must be a complex
array of photocells and there must be a data recording device, or at least an interface to a computer. It turns out that only in the area of the
recognition circuitry itself does the character
reader have a more expensive component.
I
1453
U~A51 -A.
THIS IS AN EXAMPLE
coos
Optical versus magnetic scanning
The major reason why the banking system
chose a magnetic method was that this allowed
overprinting to be done on top of the magnetic
numbers and still have them read. This relative
advantage of magnetic over optical is rapidly disappearing as systems people have finally been
discovering that there is no need to overprint on
data areas. The optical has a real advantage over
the magnetic system in the area of quality control, because OCR makes its basic measurements
the same way that humans do. The thickness of
magnetic material in an MICR character, in particular, is very critical, and the human being cannot measure this value without a special instrument. Because of this the magnetic ink characters are expensive to print and an ordinary typewriter cannot be used.
Techniques of reading
Let us now discuss a few of the methods which
are used to decipher which character is which.
There are basically four outstanding classes. The
first of these techniques is called "Feature Recognition" and this involves simply taking the character apart into its pieces (big pieces, like bars
and columns), recognizing the pieces, and then
reassembling them into a truth table. This truth
table may very well be in the form of a completely
digital decision matrix, although it may have considerable redundancy.
A second method, called "Area Correlation," is
to take the character apart into tiny unit areas,
each black or white, and then compare it point
by point with all templates. No decisions are made
on parts of the character-decisions are made
by choosing the best match correlation between
the complete image and the complete templates.
This image may be in a purely optical form or it
may be in a digital form; the correlation may be
FIGURE I-Several varieties of stylized font
done optically or by using weighted resistor networks.
The third class may be called "Topological Recognition." This is found most commonly in machines designed to read hand printed numbers.
The basic method is to track the lines and to discover the relationship of each line to other lines
in the form of sharp 'curvatures,beginnings of
lines, ends of lines, joints, and splits.
The fourth class we will brand with the name
"Inhuman Recognition." This is a group of special recognition techniques which are useful only
with severely stylized fonts. Two of these are illustrated in Figure 1. In this class of reading machines the complexity of the character reading
portion of the machine is nominally reduced by
designing the character set to have some trick
shane which can produce an electrical signal more
easily deciphered. One example of this is the
MICR Reader which has the font designed to give
various coded amplitude outputs as a function of
time, the character being scanned horizontally
with a narrow vertical slit. Another example of
this is the COC5 font. Its trick is that it is made
up of combinations of wide and narrow spaces
between vertical black bars. The particular set
of wide-narrow spaces form a digital code.
All of the first three techniques· have been suc-
1454
Fall Joint Computer Conference, 1968
cessfully used with non-stylized fonts, but improvement invariably results from the use of a
somewhat stylized character. The USASI (ISOA)
font was developed for this purpose. It is now a
national standard and is being required as a font
which must be read on all OCR reading machines
which are purchased by the U. S. Government.
(Note: machines purchased may also .read additional other fonts.) The use of a slightly stylized
font together with a powerful technique such as
area correlation allows an inexpensive central
reader and insures a very high accuracy rate.
There are a great many other techniques which
have been promised and seem promising to some.
The idea of the Perceptron triggered off a burst
of studies aimed at self-Qrganizing systems, and
the theoretical work is undoubtedly laying the
foundations for exotic new fields in Automata.
Practically, some interesting extrapolations of the
Perceptron have been made at SCOPE and at
Andromeda, but it does not appear that the selforganizing method is likely to be useful for character reading in business. One system,called the
"N Tuple" method, was very nearly a commercial
success for the conversion of plate impressions.
Groups of statistical measurements are made by
a computer on a training set, and these measurements are later correlated with the unknown characters. Economic justification for a self-learning
reader is difficult, the argument being that the
self-learning feature need really only be used once
(or at most occasionally) and that therefore the
requisite machinery for accomplishing this would
sit idle most of the time while the reader proper
was paying the rent.
A very severe problem common to all machines
reading non-stylized alphabets is the separation
of characters when they touch. This is particularly bad in a 12 Pitch font with serifs.
A more detailed discussion of the philosophy
and construction of reading machines may be
found in the references.1 •2
Scanning
Scanning is the term used for the job of getting
the character shape off the paper and into the
electronics. For magnetic character readers the
job is done by using one or a few magnetic heads
arrayed in a vertical slot. These are, perforce, in
contact with the paper and so the variety of the
possible structures is severely limited.
OCR readers, on the other hand, have a bewiI-
dering array of possibilities for scanning, since
lenses and mirrors can be used ad infinitum.
Some of these are:
1. A single photocell which peeks through a
moving slit or hole. Typically, this hole will
be traveling vertically at high speed and the
paper wiII be moving horizontally at low
speed, thus producing an area scan.
2. A column or a row of photocells. If a column
of photoceIIs is used, the paper will be traveling horizontally, thus giving an area scan.
3. "Retina" of photocells. This is simply an
X-Y array of photocells which is typically
somewhat larger than the size of a character.
4. Cathode ray tube scanning. This is particularly attractive where there is a very large
area to be covered while searching for the
small portion of information to be read.
In all of these schemes, moving mirrors may be
employed to help scan, but the mirrors are notorious thieves of light. Light level and uniformity
is always a major problem. Where only a single
line is to be read and the paper can move in one
of the directions, the light J,roblem is much easier.
Another major requirement for the scanning
system is to be able to resolve down to very fine
line width. Omni-Font machines characteristically
require the ability to see line widths down to 6
mils. In order to make sure of catching this line,
the scanner must resolve about 3 mils. It is important to remember, however, that one should
not resolve too finely because then dirt will quantize very nicely instead of integrating. There isn't
much danger of anybody getting finer than 3 mils,
though, because it is a struggle to get even this
much resolution.
Paper handling
The complexities of handling paper are typically
very much underestimated, and broken promises
exist in almost every design. A tabulating card is
a nearly ideal object for being moved around by a
machine since it is stiff, has close tolerances. Not
so for paper.
The two most critical areas in paper transport
are the pickoff and the stacker. In general, these
problems get more difficult the wider the variety
of paper which is required to be handled. For example, while a vacuum pickoff works very well for
16 lb. paper, it works quite poorly for tab cards;
while a "ledge" type pickoff works very well for
What was Promised-What We Have-What is Promised in Character Recognition
tabulating cards it is utterly useless on paper
under 20 lbs. Undoubtedly, the most difficult pickoff and stacking problems occur with the use of a
very light paper, particularly the type used in airline tickets. For such paper the pickoffs are better
than the stackers.
In between the pickoff and the stacker, we have
some other problems, the majority of which are
concerned with starting and stopping the paper
smoothly while preventing skew. The aspect ratio
of documents is extremely important. Those documents which can be moved with a long edge in the
direction of travel tend, because of some very
basic physical laws, to be much more stable than
those documents which must be moved the other
direction.
Choice of font
As we have hinted before, the detailed shape of
characters for OCR is all important. If the shape
is laid out on a grid such as a 5 X 9 matrix, the
reading machine gets cheaper and more accurate
than one which has to read non-stylized. How
about reading Chinese characters, or worse yet
Arabic alphabet? Symbols of the Arabic alphabet
often extend under each other for several characters. (Let us try analyzing the font problem from
the point of view of information content. Firstly,
it is clear that the binary code is the most efficient
-good for the machine but hard for the human.
A compromise must be established which has good
redundancy, has good recognition ability by humans, and also can result in an inexpensive reading machine. There are several examples of such
"stylized" fonts that· have been constructed with
the reading machine in mind. Figure 1 illustrates
the USASI-A, the COC5 and the E13b.
It is educational to calculate the redundancy of
a character. Let us say that we have 26 characters
in the set and a 45 point black-white grid. The
redundancy of any character ought therefore to
be 245 _ 26 = 289.
Don't be fooled, however, by this superficial
redundancy figure. It is a poorly recognized fact
even today that in every OCR business application the critical parts of the font must be carefully controlled. No matter how good the reading
machine is, there is some limitation to the degradation which can be allowed. Because this requirement is only now beginning to be firmly
understood, many past users have had a hard li(~
living with old typewriters. Suppose the potential
user already owns several thousand typewriters
1455
which carry the 12 pitch Elite font. He figures
that if he can get a reading machine which can
read these existing typewriters, he can save the
price of new typewriters and can, therefore, afford
to pay a fancy rent. If the system is going to equal
the accuracy of a USASI font machine, however,
he must make sure that the elemental areas (or
features, if the machine is a feature reading machine) stay very well defined. Since there are
more critical dimensions in the Elite font than
there are in the USASI font, he has to spend extra
maintenance and care in printing characters.· This
means better paper, better ribbons, more frequent
changing of ribbons (or use of one-shot ribbons),
more frequent cleaning of the type, and most desirable, the use of an electric typewriter instead
of a manual typewriter. This costs!
Applications
The following paragraphs -present a partial list
of applications classified according to their most
likely requirements in terms of font.
A. Stylized font: (Characters can be generated
by printing, typing, plates, high speed printers, cash registers). Point-of-sale readers
(credit sales, charge plates), bank checks,
tally roll records, inventory control, production control, insurance payments, way bills
(transportation), stock certificates, message
entry, prize coupons, insurance payments.
B. Multi-Font: More than one font, but probably less than 5 fonts.
1. Typewriters: mail correspondence, Social
Security returns, tax returns, banking,
rental companies.
2. Plate Imprinters: Mass mail, conversion
to computer language, credit cards.
C. Omni-Font: Post Office, Social Security, tax
returns, books, magazines, newspapers, information retrieval, language translations,
readers for blind people.
D. Hand-Written:
1. Numeric: Post Office, tax returns, mail
orders, credit sales, bank checks, sales
slips, meter reading.
2. Alphabetic: _ Computer programming,
exam. papers.
Systems including character recognition
The amount of effort needed for systems analysis is only now beginning to be recognized.
The greatest application of character readers
is undoubtedly in the business community where
1456
Fall Joint Computer Conference, 1968
man must communicate with the machine. One
historical difficulty is that forms design evolved
from information typed on a piece of paper in
locations which seemed suitable to forms designers
of twenty years ago. These forms were deciphered
and interpreted by humans. The ability of a human reader to perform a whole host of operations-not part of the character reading itselfhave been very poorly appreciated. For example,
it may be that a girl is handling 30 different forms
from which she is only copying the serial number
and the total amount of the invoice. In old systems these items might appear in as many different places as there are forms. The most obvious
thing to do to correct this, of course, is to design
all forms to have similar information in similar
locations, but this is often impractical, if not
completely impossible. There are not only the
problems of space, but inventory, training, and ~
host of others. Worse yet, your requirements may
change again before you get the new forms on
line!
One of the important breakthroughs in character recognition systems came with the concept of
attaching a very small computer to the optical
reading machine. Initially, the first experiment in
this direction was not too satisfactory because
the cost of the computer used outweighed the
cost of the reading machine by a factor of 2 to 1.
More recent systems, however, such as the Control Data 915 Page Reader, use an on-line com,;.
puter representing only a small fraction of the
total system cost. Such a computer can accommodate not only the formatting of read information,
the buffering of this, and the writing of it all to
a mag tape-it can also (and this is the breakthrough) control the reading machine according
to a stored program. Thus, the program may read
the number of a form at the top of the page, select the appropriate stored program, instruct the
reading machine to move 2 inches down, 3 inches
across, read 8 numeric digits, advance paper by
one inch, read an alphanumeric number of unknown length, inspect the last 2 characters on
that line to make a decision as to whether to continue to read more information on that form, or
to immediately use a fast paper advance to shoot
the document into anyone of two or more hoppers.
Each form can have a senarate program. We thus
say that the concept of stored program contro,l of
the reading machine can result in enormous flexibility in system design and forms design.
In order to reduce the amount of programming
'\.
necessary to accomplish this flexibility, compiler
programs are available. To use the compiler, the
parameters of a new program are typed on a sheet
of paper and read by the reading machine. The
compiler then generates a program for reading
the desired specialized form.
Perhaps the difference between a "Page Reader"
and a "Document Reader" should be emphasized
at this point. A "Page Reader" is designed as a
reading machine which can read many lines on a.
page; the size of the page is normally very flexible,
ranging from a 3 112 X4 inch document up to a
10 X 14 inch document and including Fanfold. A
"Document Reader" is normally designed as a machine which can read three lines or less on a document; the paper motion is parallel to the lines of
typing..
Outside of Business Data processing there are
only a few solid opportunities for OCR. The Post
Office problem is a major one, but the systems
problem is so difficult that it may never be satisfactorily solved without much cooperation from
the public.
Sum'f!Wtry of performance promise8
As mentioned earlier in this paper, the engineers have, by-and-Iarge, delivered machinery
which worked quite well when compared with the
specifications which were agreed upon at the time
of contract. In fact, the accuracy rate has gone
sky high for machines using fixed fonts such as
the USASI. Most users never check the accuracy
of the machine at all. A typical machine guarantees an accuracy rate of less than one substitution
per 50,000 characters read; this is a point at
which the errors produced by humans in. the systems are far more significant than' any errors
produced by the reading machine. In the area of
making a system work more flexibly and easily,
the presently available generation of program controlled Page Readers has given the systems designer a new dimension of freedom.
With respect to manually formed characters,
promises were made only for carefully hand
printed numbers. The reports from users of the
IBM 1287 machine are so encouraging that many
new applications for this form of data reporting
are being considered.
There is a very interesting hole in thesnectrum
of successful nromises as measured by the number
of repeat orders. This hole appears in the ma;;'chines which were designed for Multi-Font and
Omni-Font work. The specifications for accuracy
What was Promised-What We Have-What is Promised in Character Recognition
of a machine reading 5 different fonts is something in the neighborhood of one reject per 1,000
characters and one substitution per 5,000 characters. In practice, these machines probably get one
rej ect per 500 characters and one substitution per
2,500 characters. (It is quite correct in most cases,
to allow an engineer to point out that the difference is almost invariably due to the fact that the
quality of typing or printing didn't meet the specifications.) In Omni-Font reading, the only really
powerful machines have been built for the Post
Office and Social Security; the reject and substitution rates are probably of the order of one in
a hundred and one in 500. Although these readers
probably meet the negotiated specifications, it is
clear that for Omni-Font machines a much better
technique of recognition would result in greatly
increased usage. Here, indeed, exists an enormous
challenge for the engineer. The production of new
ideas about how to read noisy junk continues at a
splendid rate, and this all to the good. It is not unreasonable, if you want to call names, to say that
the engineers have not yet kept their promises
with respect to the Omni-Font reading machine.
With respect to the Multi-Font readers, however (those that read just a few fonts, well controlled) the promises that have not been kept are
primarily those promises of the users, the m~.inte
nance people, and the systems designers. The
point is that the reject and substitution rate of
such machines is satisfactory for most business
apnlications. The sum total of print quality problems is not unsurmountable for these Multi-Font
annlications. The most likely reason for having so
few Multi-Font reading machines in service is that
the systems design of such applications is so enormous that the whole job of re-design couldn't get
finished. The basis for this complaint may vanish
shortly, since there are some very impressive
people working right now on Multi-Font systems.
What is being promised
Stylized font readers
We have, of course, both Page Readers and Document Readers using stylized fonts. We will certainly see more flexibility in both these applications, and this means a wider range of paper sizes,
paper thicknesses, computer orders to the reading machine, etc. It is even possible that a pickoff
may be offered which can handle documents of
varying sizes and thicknesses within one stack,
but this may require a fractional bending of the
laws of physics. We will certainly see lower prices
1457
and higher throughput rates, perhaps both in the
same machine. The systems support will be much
wider and better. Along this line many general
purpose programs will be available, and the user
can also expect to find several varieties of compilers and assemblers available for use. Reliability
and maintenance will both be improved. For certain types of remote terminal devices and pointof-sale devices, an exceedingly low cost is possible.
Recently there has been considerable publicity
about optical techniques using the Fourier transform and the hologram. These ideas are fascinating, but some severe technical problems need to
be overcome before such machines go commercial.
Their most likely first application is in the reading
of numeric sets.
Laser scan would undoubtedly be a big help to
OCR if it can be developed to have non-mechanical
wide angle deflection at a low cost. It would then
replace the cathode ray tube for scanning.
Multi-font readers
A likely collection of fonts to be found in one
reader might be as follows: 1) An upper and
lower case stylized font such as USASI (although
a lower case companion for the present USASI
font has not been yet formally approved, it is expected that this will occur certainly within the
next year). 2) A high speed printer font. This
may either be nominally the same font as the
USASI or it may be one of the sans-serif fonts in
use on familiar printers. It is worthy of note that
there is now in the field at least one high speed
printer (such as the Control Data 1742) which
makes a strong effort to produce high quality
printing. 3) A 12 pitch font containing serifs,
such as Elite. 4) Other fonts recognized by this
type of machine will be primarily numeric sets,
such as those generated by charge plates, cash
registers, billing machines, etc. The chances are
that the user will be able to order a collection of
these which is specialized to his needs.
It is also promised that these machines will
be able to read through a whole line of characters
each one of which touches its neighboring characters. Most of the comments made above for the
new generation of stylized readers will apply here
also, with the exception that it is not likely that
the price will go down. In the application of these
Multi-Font machines, a very large effort will go
into prior systems study. The Document Reader
type of organization, rather than the Page Reader,
seems to be the most profitable way to organize a
Multi-Font machine at present, and it is predicted
1458
Fall Joint Computer Conference, 1968
that most of the sales of Multi-Font readers will
be in Document Readers.
The Multi-Font Page Readers will be asked to
perform Herculean tasks of separating readable
information from information which is not supposed to be read by the machine, in addition to
following large· skew angles, large instantaneous
jumps of characters with respect to the characters next door-all within the framework of a 6
lines to the inch situation! Instantaneous character reading rates of better than 10,000 characters
per second will be offered. All of these requirements, while they can be fulfilled in a single machine, lead to nightmares for the engineer and,
one suspects, for system managers.
Topological readers
The attractiveness of having human beings act
as free keypunchers is so great that we will work
very hard to give you the right machinery. The
most likely possibility right now is the recognition
of hand printed numbers. It seems not unreasonable that bank checks, for example, will have
boxes for the numeric amount of the check. The
customer will then fill in the amount in arabic
numerals, and the reader will read these optically.
Many banks have already adopted deposit slips
with boxes for the account number. The advantage
of boxes is twofold: First of all it separates the
numerals well and secondly, it tends to normalize
the size of the characters. It is predicted that machines can shortly be built which will read these
numbers with the same accuracy that a human
being can read them. The recognition of hand
printed alphabet has now been announced by Recognition Equipment, Inc., and sales expertence will
indicate how valuable this capability is.
Readers for "Inhuman Fonts" (COC5, CMC7,
E13b) will undoubtedly proliferate in special purpose situations in spite of their miserable appearance.
Magnetic ink machines will command an ever
decreasing share of. the market, however, because
the scanning modes possible in OCR are so much
more flexible than in MICR. This is primarily due
to a world-wide shortage of magnetic lenses.
Omni-font readers
These will improve and be used with some success in situations where the input is historically
uncontrolled. In order to bring real savings to
these applications, however, strenuous efforts will
have to be made to improve the quality of the inputs.
Cursive script readers
The target application is the U. S. Post Office,
and the existence of this problem gladdens the
heart of every OCR researcher. By 1975 a machine
should be available to read 80 % of the script
addresses. More important than the reader, however, will be the vast increase in knowledge about
automata and the human brain which will accompany the success.
CONCLUSION
There are two categories of "What Was Promised."
1. Promises made by authors.
2. Promises made by engineers in their specifications for machines.
The performance on category one has been
pretty spotty, and may get worse, but performance
on specifications has been good for most projects.
"What We Have" is an excellent capability for
most intra-company business data, a modest capability for inter-company transactions, a poor capability for data collection, and practically no capability for uncontrolled communications.
"What Is Being Promised" . . . source data col;.
lection will expand one hundred times in five years
... forms for inter-company transactions will be
standardized by public and private agencies . . .
discovery of methods for reading cursive script
will illuminate the problems of human 'language.
Perhaps, before we lay down our soldering irons,
these machines will send letters to each other in
clear text:
"Dear Complex 479:
Please be advised that your 47th print hammer
is badly out of synchronization ..."
REFERENCES
1 L N KANAL (editor)
Pattern recognition
Thompson Book Company Inc Washington DC 1968
2 AWHOI,T
Comparative religion in character recognition machine8
Computer Group News IEEE November 1968
High-speed logic and memory-Past, present
and future
by ARTHUR W. LO
Princeton University
Princeton, New Jersey
INTRODUCTION
By 1950 the logic and memory functions required
in data processing were successfully implemented
by vacuum-tube technology to demonstrate the
feasibility of electronic computers. In the decade
of 1950-1960 a large variety of solid-state switching and storage elements and associated circuit
schemes were proposed, and pursued to various
extent through the research, development and production phases. The present decade, 1960-1970,
has witnessed the consolidation of hardware technology to semiconductor logic circuits and magnetic random-access memories to achieve cost and
performance advantages in practical systems. The
overwhelming success of the semiconductors and
the magnetics appears to deter the development
of other technologies .. Whether or not this trend
will continue in the next decade, 1970-1980, depends on the magnitude of the demand and the
advancement of science and technology.
This article provides a brief account of what
was promised, what we have, and what is being
promised in high-speed logic and memory hardware. It aims to show the reasoning behind the
past promises, why we have what we have, and
what is reasonable to expect for the near future. A
chronological sketch of the major developments in
hardware technologies for high-speed logic and
memory is shown in Tables I and II to aid the
discussion.
No hardware technology can be successful unless it lends itself to the fulfillment of certain universal device and circuit requirements pertinent
to digital operation. The "function-composition"
nature of digital information processing systems
makes possible the synthesis of complex system
VACUUM TUBE
1-950
SEMICONDUCTOR
DIODE
TRANSISTOR
1955
MAGNETICS
CRYOOPTOELECTRIC ELECTRIC
FERRITE
CORE
WIREUND
MULTlAPERTURE
EL-PC
wl
I
DISCRETECOMPONENT
GATE
COR~
PARAMETRON
I
THINFILM
1960
I
PHOTOTRANSISTOR
I
INJECTION
LASER
1965
NEGATIVE
RESISTANCE
DEVICES
VARACTOR
DIODE
TUNNEL
DIODE
INTEGRATED
GATE
'T
BIPOLAR
OPERATION
I
INTEGRATED
NETWORK
I
1970
INTEGRATED
FUNCTIONAL
BLOCK
1
TABLE I-Chronology of high-speed logic development
functions from primitive operations. The physical
realization of such systems relies on the interconnection of a large number of elementary circuits
to form complex electronic networks. The requirement of extensive and flexible interconnection dictates the fundamental properties of the elementary circuits. In order that arbitrary combinational and sequential logic functions may be implemented with least constraint, it is essential that
the elementary circuits (the logic gates which performs the primitive logic functions) can be "free1459
1460
Fall Joint Computer Conference, 1968
DELAY-LINE AND STORAGE-TUBE
1950
MAGNETICS
FERRITE
CORE
SEMICONDUCTOR
TRANSISTOR
I
APERTURED
PLATE
I
TUNNEL
DIODE
WAFFLE
IRON
LAMINATED
FERRITE
1965
INTEGRATED
___ ":..R_R!o:! __ _
BIPOLAR
IGFET
1970
TABLE II-ChronololZv of high-speed memory development
ly" interconnected with one another without obstructing their basic operations. The interconnected gates must respond to one another according to the design and with little delay. These basic
requirements demand that the elementary logic
circuits must have the following characteristics:
(a) Signal Quantization. The provision of
signal quantization ensures that the output signal of the elementary circuit is
more true to the sp.ecified "0" or "1"
representation than the input signal, so
that there is no signal deterioration in a
logic network of any size.
(b) .D·irectivity and Isolation. The provision
of directivity and isolation of signal flow
ensures clear designation of "cause and
effect" to prevent spurious interactions
between connected circuits.
(c) Fast Switching. The minimization of the
switching delay time between switching
circuits ensures the operation speed of
the digital system.
Most of these desired characteristics of the elementary circuit are provided by the switching element (s) employed in the circuit. The Quantization
requirement demands switching elem~nts having
a' sharp and uniform switching threshold, as well
as an operating region of high gain. Th,ese properties ensure reliable switching of the eiement by
small input voltage and current excursions, under
the realistic constraints of noise, component tolerance, and fan-in and fan-out loading. The requirement of directivity and isolation of signal flow
calls for switching elements of unilateral isolation
property or the use of unidirectional coupling elernlents. The switching delay time of a digital circuit is essentially determined by the tinle required
to charge or discharge reactances in the circuit to
produce the specified signal voltage or current excursion. Reduction of component size and high
density circuit construction are essential to reduce
the intrinsic and parasitic reactances associated
with the devices and their interconnections. In
summary, the physical implementation of highspeed logic demands high-grain, highly nonlinear
unilateral switching elements which can be readily
fabricated to very small size and high uniformity,
and interconnected to one another in high density.
In the case of memory, very-high-speed, smallcapacity information storage is usually intimately
connected to the logic circuits, and the same hardware technology serves for both logic and memory.
For memories of storage capacity of thousands of
bits to millions of bits, some efficient, random-access address-selection arrangement is indispensable. Such memory is usuaily arranged in the
form of an array, or planes of array, of storage
elements with provision of selective addressing.
The major considerations for high-speed, medium
and large capacity memories are as foHows:
(a) The storage elements must provide discrete, static or dynamic remanent states
to retain the stored information, with
little or no standby power.
(b) The storage elements should provide
simple means of selective addressing,
and they must be immune to repeated
disturbs (produced by digit-drive, partial word-drive, and spurious coupling).
A foremost requirement is that the storage cell has a sharp, stable and uniform
switching threshold.
'( c) High-speed operation requires that the
storage elements can be made to minimal
physical size (and with high uniformity)
and "wired" into high density arrays.
( d) The large number of storage elements
needed in each memory unit puts the
High Speed L'Ogic and Memory
emphasis on high-yield, mass fabrication
techniques for the production of storage
elements and memory arrays at reasonable cost.
This outline of the fundamental device and circuit requirements for high-speed logic and memory
implementation provides the basis of a systematic
appraisal of the merits and limitations (leading
to the success and failure) of the vari'Ous hardware technologies, present, past and future.
High-speed logic
What was promised?
The large variety of promised hardware approaches for the implementation of high-speed
logic are summarized under the following categories.
Semiconductor diode, transistor and integrated
circuits
From the earliest stage of development, the
semiconductor transistors and diodes, with their
obvious advantages in size and power consumption,
offered good promise of their replacement of the
vacuum-tubes in logic circuits. The advancement
of semiconductor technology soon revealed the
significant advantages in reliability and life,
switching speed, and manufacturing cost of the
semiconductor devices, several orders 'Of magnitude over what could be achieved with vacuumtubes. A unique property of the semiconductor
junction devices is that the pn junction voltagecurrent characteristic provides a switching threshold which is not only very sharp but also "naturally" uniform in the sense that the threshold
value is insensitive to the physical dimensions and
the fabrication processes of the device. Thus
diodes and transistors can be readily fabricated
to extremely small size (where dimensi'Onal vari,
ance is unavoidably large) and in large quantitv,
while having uniform switching thresholds. The
sharp and uniform threshold permits reliable
switching by voltage excursion of less than a volt.
The minimal device capacitance (from the small
physical size) and the high transconductance 'Of
the device provide fast switching. Early promise
of logic SUbsystems' composed of thousands of
transistor logic gates with logic delav of a fraction
of a microsecond 'and cost below $1.00 per gate
were readily surpassed in the late 1950's. The
1461
phenomenal success of planar silicon transistor
technology, consisting of the processing steps of
epitaxial growth, oxide passivation, photolithographically controlled selective impurity-diffusion
and metal-deposition, made practical the batchfabrication of large number of components (diodes, transistors and resistors) of extremely small
size and great uniformity at low cost. The same
technology readily makes the interconn.ections between c'Omponents to form logjc gates, and the
interconnections between gates to form logic networks, all at the surface of a silicon chip. Following the undisputed demonstration of the producibility of integrated-circuits and their advantage
over discrete-element assembly, came speculations
of larger- and-larger scales of integration, all the
way to "computer on a chip," as well as delaytime "limited only by the speed of light" and cost
of "practically n'Othing."
In the decade 1950-1960, when the need of practical high-speed logic hardware was urgent and
luuch of the potentials of transistor logic circuits
were not fully appreciated 'Or realized, a large
number of solid-state devices and circuits were
seriously considered for logic implementation. The
maj or developments and expectations of these
approaches are outlined in the following secti'Ons:
Cryotron logic circuits
The early wire-wound cryotron offered an electronic analog of the electromechanical relay, with
the potential advantages of higher speed, longer
life and lower power consumption, despite the obvious cryogenic requirement. The advent of thinfilm cryotron structure prompted great expectation of batch-fabrication of large and complex
logic networks by the simple· process of vacuumdeposition of homogeneous materials. An inherent drawback of cryotron logic circuit is the low
operation speed dictated by the lar~e L/R time
constant (even after the introduction 'Of superconductive ground-plane which drastically reduced
the circuit inductance). Efforts to imnrove operation speed by size miniaturization and the use of
higher-resistance metal-allov encountered difficulties in the uniformity of the switching threshold, which is directly related to line-width and
critically dependent on temperature (thus ohmic
heating in switching), as well as material and
fabrication imperfections. The success of cryoelectric logic system hinges on the ability to batch-
1462
Fall Joint Computer Conference, 1968
fabricate large, complex logic networks economically, but the present status of cryogenic science
and technology has not warranted such undertaking. The promise of entire logic and memory
system batch-fabricated at low cost by the cryoelectric technology is not likely to be fulfilled in
the near future.
Opto-~lectric
logic circuits
The early EL-PC pair, employing polycrystalline electro-luminescent phosphor and cadiumsulfide photoconducting material, promised lowcost production of logic circuits by the "printingpress" process. However, the cost of assembling,
interconnecting, and protective packaging of these
circuits for sizable logic systems was not low, and
the operation speed was intolerable. l\!ore recent
opto-electric logic, using semiconductor lightemitting injector-laser and light-sensitive phot'Odiode (or transistor) still could not achieve operation speed comparable to transistors. The major
difficulty is that, for any realistic network interconnecti'On, only a small fraction of the emitted
llght from a driving element can be effectively
coupled to the active region of a receiving element
to realize the high gain required to achieve effective quantization and fast switching. There has
been few promises of practical opto-electric logic
except for special purpose applicati'Ons.
Magnetic logic circuits
Square-loop magnetics pr'Ovide static storage
and stable switching-threshold, but they are handicapped by the lack of gain and unilateral property.
The development of "all-magnetic" logic was more
a challenge than a practical solution. The use 'Of
sequenced clock-pulse energization and multiaperture cores has produced logic circuits operating at low speed and high power level. The more
recently developed "bipolar" operation overcame
n1uch 'Of the earlier drawbacks, but the cost and
performance advantages of the magnetic circuit
were, by then, lagging far behind transistor circuits. The promises of magnetic logic were limited
to its high reliability against noise, its immunitv
to radiation damage and its apparently unlimited
life.
Parametric phase-lock oscillator logic circuits
The phase-script, carrier-powered, logic circuits
(beginning with the Parametron) promised im-
munity to noise (but not spurious interaction between circuits) and the potential of extremely
high frequency operation (using varactor diode
and microwave structure). The majority-logic
operation, however, demands uniform oscillation
amplitude and coupling attenuators, as well as
precision phase-control of the transmission of signal and carrier power at microwave frequency.
The practical aspects of interconnecting complex
microwave .structures make the implementation
difficult and costly even for small logic systems.
Tunnel-diode logic circuit
The two-terminal, negative-resistartce, semiconductor device (with its majority-carrier conduction mechanism) attracted early attention on account of its subnanosecond switching time. The
problem of uniformity of switching thresholds
among units (their peak-current being directly
proportional to the tiny junction area) resulted
in low gain, and consequently longer switching
time than promised. The balanced-pair circuit (requiring only matched-pair instead of uniformity of
all units) overcame some of the operation difficulties, but the need of sequenced clock-pulse supply
and precision coupling attenuators makes the realizable operation speed no better than. modern
transistor logic circuits. The voltage-limiting
property of the high-speed device might still be
useful if it could be conveniently integrated to the
more conventional semiconductor elements.
What we have
Presently the field of high-speed l'Ogic is
m'Onopolized by the semiconductor integratedcircuit technology. Technical developments are
c'Oncentrated on smaller component-size and higher
component density. A typical transistor at present
rnay have emitter strip-width 'Of 0.1 mil and base
width of OA,u. Such a transistor can be switched
reliably in one nanosecond by a voltage excursion
cf less than one volt. The basic logic gates, composed of transistors, diodes and low-precision resistors have logic delay time of 2-20 ns and power
consumption of 10-15 mW. (The integrated-circuit technology has all but obsoleted the TRL and
.DCTL gates, in favor 'Of the DTL and the TTL
gates for cost-oriented applications, and the ECL
gates for speed-oriented applications.) The present scale of integration is 10 to 50 interconnected
gates on a chip (corresponding to density 'Of
104 - 10 5 components per square inch), for the
High Speed L'Ogic and Mem'Ory
cost of about 25 cents per gate.
The Insulated-gate Field-effect Transistor has
been successfuly developed to rival the bipolar
transistor as practical basic switching element.
In comparis'On with the bipolar transistor, the
IGFET is handicapped by the lack of a "naturally"
uniform switching threshold and its low transconductance at lower operating voltage. Thus the
basic .IGFET inverter requires a larger voltageexcursion and a larger "load" resistance for reliable switching, and consequently has a longer
switching delay time (ten times that of the bip'Olar
transistor inverter). The shortcomings of the
basic IGFET circuit are partially overcome by the
pulse-mode circuit (at the expense of sequencedpulse power-supply) and the complementary-symmetry circuit (at the expense of more complex
device fabrication). The IGFET circuits are not
likely to match the performance 'Of the bipolartransistor circuits for general-purpose, high-speed
logic, without some significant advancement in
IGFET technology. The inherent' advantage of
the IGFET is its simpler device structure which
lends itself to higher degree of miniaturization
and higher fabrication yield (than the bipola"'"
transistor), thus more suitable f'Or practical largescale integration.
The limiting factor of larger-and-Iarger scale of
integration on a chip is essentially determined by
the yield of the completed network. Presently
there are two distinct approaches to large-scale
integration. The fixed-pattern wiring (metalizati'On) approach requires all the components
covered by the interconnection pattern to be free
of defects. Integrated logic networks of 10 - 30
bipolar transistor gates and over 100 IGFET gates
have been produced in this manner. Larger integration by this approach suffers severe yield
shrinkage. The discretionary-wiring approach allows reasonable imperfections among the fabricated components to make larger integration feasible, only at the expense of tedious testing at the
component level, considerable data processing to
formulate interconnection patterns, and the CO<:l~
of preparing individual metalization masks. At
the present time the fixed-pattern technique is
used for the majority of integrated-circuit production. and the discretionary-wiring technique is
userl for some products.
What is being promised
The present trend of logic hardware is larger-
1463
and-larger scale of integration on a chip, since
the interconnection between chips is largely responsible for the degradation of speed, reliability
and cost of present logic systems. This fact
prompts the promise that by early 1970's we will
have 1,000 -10,000 interconnected gates on a chip,
with component density of 105 -10 6 components
per square inch and switching delay time of 2 - 5
ns, at the cost of 5 cents per gate. With this many
interconnected gates a single chip would constitute
the entire electronic network of a complete logic
subsystem, thus greatly reducing the number of
terminal leads to the chip. The manufacturing of
"functional-units" of such complexity can be
achieved only by automation to handle the tasks
'cf logical design, device and circuit layout, and
diffusion (and metalization) mask design, as well
as automatic fabrication and testing. The fulfillment of such promise is largely governed by the
law of demand and supply. The functional-units
which have large-volume demand will be developed
and produced, and the others will be neglected. The
progress in this direction will depend heavily on
the standardization of computer structure and
the consolidation of computer types. Never before
is there such urgent need for interaction between
software and hardware planning. "What to
make" and "How to test them, when made" deserves as much a~tention as the technology of producing the hardware.
It is of interest to note that the sobering experience of past developments and a better understanding of the basic requirements of digital circuits have refrained speculations of revolutionary
logic-implementation in recent years. Nevertheless, there are expectations that new andsignificant progress will be made if and when certain
difficulties ass'Ociated with a number of hardware
technologies are overcome 'Or bypassed. Gerrnanium transistor operating at low temperature
can provide very high speed logic if the fabrication techniques of germanium can reach the same
level of silicon technology. The feasibility of alloptic logic for extremely high speed operation depends on the development of practicaJ means of
efficient light-c'Oupling between laser-like elements
Large-scale cryoelectric logic a.nd memory system<:l
(at extremely low fabric~tion cost) could becom p
practical through the discovery of sunerconducto'f'
material of higher normal resistance and higher
onerating- temperature (A~V. liouid nitrogen temperature). Practical use of two-termin31 bulk-
1464
Fall Joint Computer Conference, 1968
effect semiconductor devices for high-speed logi~
hwaits the development of uncomplicated means
of providing directivity and isolation. All-magnetic logic based on flux steering 'Of magnetic donlains within homogeneous material (thus eliminating signal-path interconnections) could be
feasible with the development of practical means
of providing flux quantization and signal directivity.
core for reliable nondestructive read-out, and twocore-per-bit partial-switching operation for higher
speed were also demonstrated, but not widely
adopted on account of the added complexity and
cost. The promised batch-fabricated ferrite memory, such as apertured-plate, laminated ferrite
and waffle-iron, did not achieve the expected cost
advantage, mainly because of yield and the burden
(of switching excess magnetic material) imposed
'On the drive;..and sense-circuitry.
High-speed memory
What was promised
A maj or consideration in the development of
high-speed, large-capacity memory systems is the
cost of producing and assembling the large quantities of storage cells. The magnetics has been, and
still is, the dominating memory technology.
Ferrite core-mem'Ory
The ferrite core memory technology has the
distinction of having promised little (in storage
capacity, cycle time and system cost), and delivered much. By 1955 the main memories of all
rnaj or computers were being implemented with
this technology. The ferrite core, with its inherent static-storage property (without standbypower) and material stability (polycrystalline ceramic material), 'easily obsoleted the electroacoustic delay-lines and the storage tubes. The
switching threshold of the magnetic core is directly related to its physical dimensions and material imperfections, which are difficult to control
in the high-temperature, high-pressure processing
of the polycrystalline material. The cores, therefore, are tested individually to meet the actual
operating conditions (including the large number
of disturbs) before wired into the array. This enforced device uniformity, and the tremendous demand of random-access mem'Ory of adequate speed
and capacity to match the existing logic circuitry,
resulted in the, production of million-bit memory
with read-write cycle time around 5 f.LS by 1960.
The cost of the core-memory systems was found to
depend more and more on the driving and sensing
circuitry, which followed closely the advancement
of the semiconductor technology. Three types of
memory organizations, 3D, 2D and the middleground 2 1hD, were adopted to fit the compromi.se
between storage capacity, cycle time, ~nd system
cost for any particular, random-access memory
application. The feasibility of multi-aperture
Magnetic thin-film memory
The anisotropic magnetic thin-film shows the
promise of exceedingly fast coherent-rotation
switching, convenient orthogonal drive operati'On,
D.,nd planar structure for easy batch-fabrication.
The development of practical flat-film memory,
however, has been slower than expected. The qpenflux path structure imposes a compromise between
dot size and film thickness, and the output signal
voltage, thus prohibiting very high density array
structure. The desired uniformity of switching
and disturb thresholds are difficult to achieve with
present material and batch fabricati'On techniques.
The more recently developed cylindrical-film
(plated-wire) memory elements provide a closed
flux-path in the easy axis (thus permitting the
use 'Of small-radius wire and thicker film) to overcome some of the difficulties (particularly disturb
sensitivity) of the planar thin-film. The promise
for these thin-film memories is that, once the ma··
terial and fabrication problems are solved, improvement of memory storage capacity, cycle
time, and system cost by one order of magnitude
'Over the core memory should be readily achievable.
A comfortable thought is that there is no lack of
large demand for multi-million-bit, sub-microsecond memory at present and in the foreseeable future, provided the price is not outrageous.
Cryoelectric persistent current memory
The development of cryoelectric memory, (from
cryotron-cell, to Crowe cell, to continuous-sheet
and cavity-sensing) promised very-large capacity
random-access memory operating at modest speed.
The task of producing high-uniform, highdensity array with good yield remains a chailenge
to our material and fabrication ·technology.
What we have
Core memories of 3D or 21/2D organization,
High Speed Logic and Memory
with capacity of multi-million-bits and cycle-time
of 1 - 2 p,s, dominate the field of internal main
nlemory in the present generation of computers.
Some flat-film and cylindrical-film memories of
lOti bit and 0.5 p,s cycle-time have been installed in
working systems. Memory systems cost is difficult to assess, but it appears to be in the range
of 1 - 5¢ per bit~ In the area of high-speed, smallcapacity random-access memory, the magnetic
thin-film technology (both flat-film and cylindrical
film) has produced memories of 5 X 104 bits with
access-time (for read or write) of 100 - 200 ns.
Semiconductor, integrated-circuit technology is
making an inroad to the field of very high-speed
memory. .Development effo'rts on the fabrication
of large arrays of semiconductor memory cells
hnd interconnections has shown.that IGFET memory of 104 bits with access-time of 100 ns, and bipolar-transistor memory of 103 bits with accesstime less than 50 ns are technically feasible.
What is being promised
The normal progress of core-memory technology
will see some further reduction of cost so that it
will be economically feasible to have tens of millions bits of random-access storage (with cycletime around 1 p, s) in the present generation of computers. There is strong expectation that the evolution of thin-film technology (flat-film and platedwire) will finally reach the goal of low-cost batchfabrication, thus providing memories of 106 -10 7
bits capacity, 200 - 500 ns cycle-time, at the cost of
a fraction of a cent per bit. Integrated IGFET
TI1emory is expected to dominate the area of smallcapacity storage (less than 106 bits) with access
time of 100 - 200 ns, at the cost of 1c per bit. The
semiconductor technology also shows good promise
for merging the logic and the memory functions to
1465
nlake medium-capacity associative-memory economically feasible and to allow much more sophisticated computer organizations.
Much attention is currently focused on the development of block-oriented random-access memories. One prospect is the magnetosonic delay-line
raemory which employs magnetic storage and
block-access by semiconductor electronics (to
cause the propagation of a sonic wave in the selected line). Nondestructive read-out is derived
on the digit lines in sequence by the propagation
sonic wave, and write-in is carried out by the
coincidence of digit currents and the propagating
wave. Another prospect is the opto-electric readonly memory, where the stored information on
high resolution photographic plate is block-selected
by optical means, employing light-beam deflection
or an array of light-emitting elements. The optical.
readout (of all the bits in the block in parallel) is
converted to electric signal by an array of photosensitive elements. Holographic techniques are
proposed for the implementation of the highdensity photographic processing. The practicality
of these block-oriented systems are too early to be
realistically appraised.
CONCLUDING REMARKS
The present hardware technologies for high-spee<).
logic and memory have reached a high level of proficiency, making the central processing unit far
ahead in cost and performance in computer sys·
terns. Evolutionary progress of these technologies,
particularly in batch-fabrication techniques, will
provide more logic and memory at less cost, but
only slight improvement in operation speed. There
is, however, no sign of any revolutionary hardware
implementation of high-speed logic and memory
in the near future.
Real time systems and public information
by C. WEST CHURCHMAN
University of California
Berkeley, California
It is perhaps obvious that computer technology will
open up a new era in public information in the coming
decade. What is not so obvious at all is the proper design of the future information systems. Nor do I sense
any simple answers.
The questions that come to mind with regard to public information systems are these:
1. Is it feasible to build systems which will more accurately and quickly inform the public o~ major issues of
social policy?
2. If so, is it desirable to build such systems?
3. Is it feasible to build systems which will more accurately report to the legisl,ative and executive branches of
government the opinions of the public on social policy?
4. If so, is it desirable to build such systems?
As I say, none of these questions seem to me to have
an obvious answer. In the case of the first, it is easy to
point out that there exist "manual" systems, like the
New York Time8 or the radio-TV, which do a reasonably
good job of informing the public, but which are not
widely used. Are we to expect that merely increasing the
facility of access will lead to wider use? But is a more informed public socially desirable? And if legislators could
react more quickly to changes in public opinion, would
this be desirable?
In order to make the point that these questions have
no simple answer, I'd like to contrast two "world views"
of the public and its value system, both world views being plausible, but each leading to a different answer to
the questions I've posed.
In the first world of the public, the citizen is viewed as
a living entity who seeks to attain certain "life goals."
In a democratic society, these goals may vary considerably and often will come in conflict. The aim of government is to resolve such conflicts fairly, and to use the
national resources to come as near as possible to aiding as
many citizens as possible to attain their respective
goals. In such a world, information plays a very important role. The citizen needs to know the policies of the
government with respect to matters that are relevant to
him. If it is the case that the government plans to implement a policy, the citizen should be able to inform his
representatives about the consequences of such a policy
vi8-a-vi8 his goals. The measure of performance of the
information system is the extent to which it removes
ignorance, ignorance on the part of both citizen and
representative. Consequently, the answer to all four of
my questions, according to this world view, is "yes,"
but the critical point is that the information system
needs to be supplemented by a vast educational program. The citizen needs to learn the value of information. He must come to realize that acquiring and transmitting information is an essential part of his value system, so that he will freely seek to be well informed.
Hence the government must see to it that the information systems are of the highest quality, and that the
public is made aware of their value.
Admittedly, this first world view is a bit simplistic
but when painted in more complicated detail it becomes
quite attractive to the social planner. It justifies a social
commitment of large resources to the building of better
information systems.
The second world view is also plausible, but by no
means as attractive to the system designer. It says that
there is no such thing as accurate or objective information, especially in the context of social policy. Instead,
so-called "information" is simply one kind of incentive,
which can be used by one person or group to influence
the behavior of another person or group. It is, in fact, a
commodity with its own price, a commodity that serves
the purpose of shaping social action. When a person
"informs" another, he uses up some of his commodity
for the sake of getting the other person to act in ways
desirable to him. Thus one man "informs" the citizens of
the USA that the North Vietnamese massacred 60,000
Catholics, while another "informs" us that the United
States Air Force in its bombings massacred an equivalent number of North Vietnamese civilians. Both are us1467
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Fall Joint Computer Conference, 1968
ing their information commodity to attain a reaction,
either for or against the war. Note that both must be
concerned with timing; the commodity is in fact "used
up" when information is transmitted. The repeated use
of the same information has a quite different effect from
the first application.
According to this second world view of public information, the answers to my four questions are generally
in the negative. By creating more powerful information
systems, we shall be giving certain power groups a tool
to manipulate pub1ic action. Which group benefits depends on who designs the system, but the net effect will
be one in which political power is enhanced. Inevitably,
therefore, a reaction will set in, either civil war or fascism, if only one public information system is designed.
What needs to be examined at the outset is the legal and
moral aspects of such systems, and this examination will
inevitably lead us to conclude that there should at least
be competing information systems. In other words,
there should be a free market of the commodity.
This world view is also rather simplistia. In order to
enrich it, we might listen some more to the protagonist of the first world view. In his rebuttal, he will point
out that of aourse the designers of the system need to inform the public about the reliability of the information.
It is true, he says, that so-call~d information is often
mere subjective opinion. But well documented and objective facts are not the inventions of scheming minds;
they are "there" and cannot be changed. A fact is a fact,
after all.
To this rebuttal, the other side points out that there
are two ways to deceive a person even though what you
ten him is the "truth". One way is to tel1 him only a part
of the story, i.e., to select the data. It is not the case
that the New York Times prints all the news that's fit
to print, because such a task is impossible. Instead it
filters out "uninteresting" news, using its own value system to do so. The second way is to interpret the data.
No fact is "pure". Whenever I tell you something, I
must include shades of meaning and inference, either
explicitly or implicitly. This is especially true when the
data are supposed to b~ relevant to policy making. If I
tell you that the USSR will produce more engineers in
1970 than the USA, this is not a pure fact, especially if
the telling occurs in the environment of alarm about
the arms race. The "datum" is attached to a world view,
and cannot be detached from it. Hence it is simply impossible to warn the citizen about reliability in any
real sense. Furthermore, it is doubtful whether there is
any true scale of reliability of information.
The debate is not apt to have any end, because both
sides argue in the context of ignorance. Neither one has
knowledge of the real social system, though each can tell
a plausible story about his view of it. My sympathies
are with the second side, because I suspect that the first
is somewhat dishonest: by trying to insist on obj ective
inform9tion, it also tries to escape from moral commit"ment. Its proponents want us to believe that a fact
stands there independent of one's purposes. Hence they
believe that the designer of information systems does
not have to declare what his opponent takes to be the
implicitly assumed moral assumptions. Furthermore, I
believe that all too many legislators and executives aid
and abet this moral deception.
I wouldn't vote for the second viewpoint if it ended in
relativism, i.e., in the position that information can
mean whatever one wants it to mean. Rather, I take it
to be saying that (1) there is such a thing as morality in
social policy making, (2) the morality dictates in part
which goals are legitimate and which are not, and (3)
that information is valid which directs us towards the
moral goals. That is, the design of an information system ought not to be accomplished without an explicit
moral commitment. Finally, no one should claim expertise on morality, which is the voice of an people, past,
present and future. Morality is above all a matter of
experience, or even of experiment, in which all of
us are both subj ects and observers.
The unpopular antithesis I've been developing in this
paper says in effect that as a culture we are morally immature, and that this immaturity comes to be a serious
threat every time anyone proposes a technological innovation. We don't understand the moral basis for building freeways, supersonic transports or public information systems. Weare not mature enough to deserve the
fruits of technological change. Because we are childish
in our morality, we believe we can keep shifting moral
responsibility. We say that it's not up to the system
scientist to find the moral basis for an information
system; this is a matter for managers or the public to decide. No study of morality ever seems to get into the
proposals or RFP's. We even childishly assert that it's
meaningless to try to study moral issues because people
have been trying for centuries "without success." Only
a child believes that "success" means satisfaction and
removal of the problem. Every adult knows that serious
problems are never resolved, and must be studied continuously and deeply.
The antithesis is bound to be unpopular and probably
will go unheeded. No child likes to be told that he's
behaving like a child, especially when physically he is
quite strong and mature.
National and international information networks
in science and technology
by H. BORKO
University of California
Los Angeles, California
The 20th Century has been variously called the
atomic age; the age of the second industrial
revolution ~nd the century of the computer. However the historians choose to label this period, it
is clear that science and technology has had a
central role and a significant impact on our society. Research and engineering are no longer
considered esoteric disciplines, for their products
are clearly visible. Although the importance of
science has been recognized and accepted for many
years, only now are we becoming concerned with
the results of these scientific activities. It is not
enough to produce new knowledge; the information must be made available so that it can be
tested, evaluated, and applied for the benefit of
the community.
New knowledge is being produced at an ever
increasing rate by an ever increasing number of
scientists so that the sheer volume of output is
clogging and constricting the information transfer
processes. Scientific literature has increased to
such an extent that the unaided scientist is unable
to keep abreast of, and make use of, the information relevant' to his own research. The growth
and proliferation of the literature could rapidly
produce chaos and unnecessary duplication of
effort. This could happen and would happen were
it not for the development of information science
centers that control the collection and dissemination of science information.
A few such centers are already in existence
and many more are needed, as are more efficient
procedures for t1.te storage, retrieval and dissemination of scientific information. Conceptually,
the idea of an information center is an old one
since such centers evolved from the research library. However, the mode~ computerized information center is a relatively new development requiring, in addition. to the high speed computer,
a large capacity storage device and specialized
programs for the processing of requests and the
manipulation of files. These capabilities now exist
and are being used in a number of specialized information centers. Although these centers are
reasonably efficient, they are expensive to operate and there are frequent delays in responding
to the user's request.
The information transfer problem is world wide
and must be approached at both national and internationallevels. A number of significant stepsboth technical and administrative-have already
been taken toward the creation of information
centers. It is important for us to review these
activities in order to understand their present
status and the implications that an efficient information exch&nge can have on the social, economic and political milieu in which we live. In
the United states, our leaders have taken cognizance of the new technology and have recognized
the .importance of expediting the exchange of
scientific information. As an illustration of this
fact let me quote from a congressional report of
the U.S. Senate Committee on Government Operations, June 1965. This paper is usually referred
to as the Humphrey Report. It states:
"Information is an agency resource, a federal,
national, and international resource.
Modern information technology is making it
possible to place much of the accumulated
knowledge of the human race within the reach
of a man's fingertips, so to speak. The potentialities of this access to power are awesome,
in terms of improving the well-being of our
own and other people, as well as in terms of
improved education for young and old alike.
If man's collected. knowledge is to become truly
1469
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Fall Joint Computer Conference, 1968
accessible, plans and programs must be made,
priorities assigned and resources allocated." 1
Note Senator Humphrey's statement that,
"Modern information technology is making it possible to place much of the accumulated knowledge
of the human race within the reach of a man's
fingertips ...." Clearly, he is talking about computer technology, and the reference to "a man's
fingertips" alludes to remote access via timeshared systems. The phrase that priorities need
to be assigned and resources allocated is indicative of a growing sense of urgency. Of course,
after this report had been written, other national
problems have received even higher priorities, but
the need for information transfer has not diminished. The problem remains and has been reemphasized by Garter's report on National Document-Handling Systems for Science and Technology. 2 Garter writes:
"The es,s·ence of scientific and technical information transfer is contained in the process
of communication. The development of scientific knowledge depends on the communication of new theories and new experimental observations to others. No new idea is afforded
acceptance in the scientific community until
it has been discussed and evaluated by people
knowledgeable in that area, whose knowledge of
the idea and background for evaluating it is
derived from formal and informal communications."
As a result of the work of these and other study
groups, federal agencies have given increased attention and support for activities in the field of
scientific and technical communication. Important
improvements have been made and more are under
way as both governmental and non-governmental
agencies move toward the ·development of an effective national program. The goals are threefold:
To increase the effectiveness of R&D management in the Federal government; to make readily
available to all U.S. scientists and engineers the
world's current and past output of significant scientific information; and to encourage the transfer
of defense generated technology to the civilian·
sector in order to induce comparable advances in
the total economy.
Within the federal establishment, the significant actions in the scientific and technical information program may be summarized as follows: 8
• The Department of Defense has redesignated
the Armed Services Technical Information
Agency as the Defense Documentation Center in
order to reflect its broadened mission and the enlarged scope of its document collection. Under the
supervision of the Director of Defense Research
and Engineering, the Center has two specific new
assignments: the maintenance of an index of current "Research Development Tests and Evaluation" programs within the department and the
establishment of a centralized directory and referral service on available DOD Scientific and
Technical information activities.
,
• Within the Department of Health, Education,
and Welfare, committees on scientific information
have been established to survey information needs
and to examine scientific and technical information activities in the Public Health Service, including the National Institutes of Health, and the
Food and Drug Administration. The National Library of Medicine, which is a component ·of the
Public Health Service, is currently operating a
computer-based Medical Literature Analysis and
Retrieval System called MEDLARS, and a National Drug Information Clearinghouse.
• The National Bureau of Standards, under the
Department of Commerce, has established a National Standard Reference Data System which
provides scientists and engineers with critically
evaluated numerical tables in the physical and
engineering sciences.
• The Office of Information Service in the National Science Foundation has sponsored numerous research projects in information science so as
to improve the collection and dissemination of information. In addition this Office has helped support the establishment of many specialized information centers including the Science Information
Exchange which monitors research in progress,
and the National Referral Center. This latter
agency is housed at the Library of Congress and
directs any scientist or research organization to
the most appropriate source of information on
any scientific or technical question. In so doing,
the Referral Center interconnects the immense resources of information services currently available in the United States.
• One of the largest sources of report literature
is the Office of Technical Services in the Department of Commerce. This agency administers the
Clearinghouse for Federal Scientific and Technical
Information, and provides a central and ready
source of information from which the user can
get copies of government reports, scientific papers
and translations of Russian and other foreign
works in specific fields.
National and International Information Networks
In the private sector, there are in existence a
large number of specialized information centers
in the fields of agriculture, engineering, physics,
chemistry, etc., and more are being planned.
All of this activity is convincing evidence that
a number of very .significant steps have been
taken to disseminate information in a manner
that will make government-sponsored research
available for public use, minimize duplication, and
aid in the development of new products and processes. But while these efforts are coordinated,
they are not truly integrated. There is a need
for a national document-handling system for science and technology, and by this I mean an integrated system in which all of the individual
centers are interconnected and cooperate with
each other in sharing their resources, and this
includes the responsibility for gathering and
translating foreign language periodicals. No one
organization has sufficient resources-material
and personnel-to collect everything. Only
through an organized cooperative effort can complete coverage be obtained.
An integrated system also requires the standardization of procedures,format rules, and terminology. This will be very difficult to achieve
as anyone working with the United States Standards Institute will testify. And no organization
that has an existing operational system would be
interested in changing their procedures. A national scientific and technical information center
will also be expensive, and it is only reasonable to
ask whether the effort and the cost will be worthwhile. Unfortunately, there does not seem to be
any way of placing an acceptable value on information, and it is even more difficult to determine
the value of that information that has been lost
or not retrieved.
While the problems are numerous, the social
and economic implications of such a network are
also great, and this is particularly true when we
broaden our perspective to include the international scene. Whereas within the United States
the main impetus for the establishment of an information network was to transfer information
from one part of the economy to another-from
military support programs to civilian utilizationthe international problem is a different one. Information is seen as a means by which a developing nation can increase its gross national product,
raise the standard of living for its citizens and
narrow the gap between the have and the havenot nations of the world. In short, information
is seen as a very valuable commodity which should
1471
flow freely across national boundaries to the
mutual benefit of all. There ar,e a number of international science information activities either
in existence or in the planning stage, but they are
for the most part narrow in scope and reflect the
dominant interest of the sponsoring organization.
One such information exchange agency is
sponsored by the Committee for International. Cooperation in Information Retrieval among Examining Patent Offices. The committee's objective
is to facilitate 'all types of patent searches, and
to cooperatively develop and share procedures for
improving patent retrieval. By working together,
the 21 national offices have developed special indexing systems and have agreed on the standardization of microforms, of punched-card formats, of specification headings, and of other relevant matters.
EURATOM, the European Atomic Energy
Agency, has successfully operated an international center on nuclear information. The center collects documents and provides fast and reliable access to its files. Additionally, a proposal has been
made by the International Atomic Energy Agency
to create a computerized International Nuclear Information System which would provide for more
efficient storage and transfer of nuclear information.
Other agencies, such as the Food and Agriculture Organization, the World Health Organization, the International Federal of Library Associations are also engaged in science information activities, but as I indicated, these are all specific,
uncoordinated, and separate.
Recently, in December 1967, the International
Council of Scientific Unions and the United Nations Educational, Scientific and Cultural Organization convened a joint project to study the feasibility of a World Science Information System.
Such a world system is now possible; although
there are a host of problems that need to be
solved before the system could be implemented.
I do not wish to minimize these problems for they
do exist and they are concerned with such technical things as communication lines, memory size,
file organization, data elements, compatible terminology, etc.
Because the members at this audience are experts in computer systems and data base management, I will not dwell on these technical matters.
If we thought about it for a few minutes, each of
us could list a dozen or more problems. And then
if we thought about it a little longer, we might
even come up with some solutions. There are no
1472
Fall Joint Computer Conference, 1968
insurmountable problems in technology. However,
the management problems are less obvious and
because of the political implications, more difficult
to solve. Namely:
• Who should manage such a world science information system? Should it be a committee of
interested and involved countries? Should the
Center be organized under the auspices of the
United Nations? Or should the leadership come
from the professional societies such as IFIPS or
the International Federation for Documentation?
• Should the service be free to all qualified personnel East and West? Or should there be a
metered charge for each delivered item of information?
• Granted that scientific information is a
valuable commodity, should the United States,
share this information without any strings, or
should the government insist upon a quid pro quo
arrangement?
• Who shall be responsible for gathering and
reviewing the documents that are to be part of
information system? Shall this responsibility be
delegated to the c()untry, the professional societies
vr some international body?
These and similar questions are being debated
by a number of international organizations. The
debates will be long and arduous, but eventually
solutions will be found, for a World Science Information Center is a necessity.
The very concept staggers the imagination.
Such an Information Center will provide a means
for helping to equalize the differences between
the poor and the wealthy nations of the world.
A data bank of scientific and technical information will enable a farmer in one country to learn
how to combat a plague of destructive insects by
using a technique developed in another country.
A food processor could learn how to preserve
crops and thus alleviate a famine in a distant
land. Technicians, engineers, and scientists will
be able to pool their knowledge internationally
and all will benefit. Educational opportunities will
be more readily available and resources will be
spread more equitably. Students, wherever they
are will be able to learn from the best of instr~ctors arid have the most up-to-date material.
Doctors ali over the world would be better trained
and more knowledgeable, and health care will improve. Perhaps people will even learn to trust and
respect one another and there will be no need for
war.
As you see, my imagination has been stimulated
and I am blinded by the grandeur of the vision.
In truth, I recognize that information itself will
not change the world; although the utilization of
information may. A World Science Information
Center is a means of making knowledge available
so that it can be utilized. As such it has a small
but necessary role to play in improving our social
and economic status. Furthermore it is a practical
first step, and one that we can and should take.
Here is an application of computing power that
is worthy of data processing technology. Here is
a proj ect that gets us out of the area of techniques and into the arena of real social problems.
Let us allow ourselves to be stimulated by this
concept and let us be challenged to solve the technical· problems so that a World Science Information Center can become a reality.
REFERENCES
1 Summary of activities toward interagency coordination
.
US Congress Senate Committee on Government OperatIOns
Report No 369 89th Congress 1st Session Washington DC GPO
June 1965 The Humphrey Report
2 L F CARTER et al
National document-handling systems jor science and technology
John Wiley & Sons New York 1967
3 Status report on scientific and technical information
Federal Council for Science and Technology June 181963
Real time computer communications and the public
interest*
by MICHAEL M. GOLD
Carnegie-Mellon University
Pittsburgh, Pennsylvania
and
LEE L. SELWYN
Boston University
Boston, Massachusetts
INTRo.DUCTION
The devel'Opment 'Of rem'Ote c'Omputer access has
resulted in am'Ong 'Other things, the empl'Oyment,
by the data pr'Ocessing industry, 'Of an imp'Ortant
new raw material-telec'Ommunicati'On services. In
the United States the principal s'Ource 'Of this raw
material is the c'Ommunicati'Ons c'Omm'On carrier
industry. Each member is a "regulated c'Omm'On
carrier"; a firm granted certain m'On'OP'Oly privileges and which, in return, must subject itself t'O
review and regulati'On by the Federal C'Ommunications C'Ommissi'On ('Or appr'Opriate state regulat'Ory b'Odies) acting t'O safeguard the public interest. All 'Of this might be very interesting but,
until n'Ow, has been 'Of relatively little c'Oncern t'O
members 'Of the data pr'Ocessing industry. H'Owever, as the c'Omputer bec'Omes m'Ore dependent
UP'On c'Ommunicati'Ons services, S'O t'O'O d'Oes the data
pr'Ocessing industry bec'Ome m'Ore subject t'O the
structure and practices 'Of an industry that has
n'Ow bec'Ome a principal supplier 'Of 'One 'Of its key
inputs 'Of raw material.
In 'Our present discussi'On, we are c'Oncerned
with the nature and, hence, the adequacy 'Of the
services that are made available and furnished by
*This work was supported in part by the Advanced Research
Projects Agency of the Office of the Secretary of Defense (SD146) and is maintained by the Air Force Office of Scientific Research. Partial support was also provided by Project MAC, an
M.LT. research program sponsored by the Advanced Research
Projects Agency, Department of Defense, under Office of Naval
Research Contract Number Nonr-4102 (01). Reproduction in
whole or in part is permitted for any purpose of the United
Stat.es Government.
these c'Omm'On carriers t'O the c'Omputer industry.
Our view is that their services are inadequate f'Or
the requirements 'Of c'Omputer systems. They are
designed t'O the same requirements as that empl'Oyed f'Or v'Oice teleph'Ony; because they d'O n'Ot
reflect the unique characteristics and requirements
'Of data c'Ommunicati'Ons, they are highly inefficient
services f'Or such purp'Oses. As a result, they C'Ost
t'O'O much. This high C'Ost may well result in the
restricti'On in the m'Ost widespread use 'Of rem'Ote
access c'Omputhig . systems, since the communicati'Ons C'Osts 'Of the services n'Ow available and their
ass'Ociated tariffs are 'Often pr'Ohibitive.
The techn'Ol'Ogy required f'Or significant impr'Ovement in the pr'Oducti'On 'Of data transmissi'On services has been devel'Oped. Its implementati'On W'Ould
significantly reduce the C'Ost 'Of such services. T'O
the extent that implementati'On 'Of this techn'Ol'Ogy
is delayed, the m'Ost widespread use 'Of rem'Oteaccess c'Omputer systems will als'O be retarded.
G'Overnment regulat'Ory agencies 'have the resP'Onsibility t'O enc'Ourage the use 'Of the m'Ost appr'Opriate techn'Ol'Ogy f'Or the pr'Oducti'On 'Of c'Ommunicati'Ons services by the regulated firms. At
the present time, the Federal C'Ommunicati'Ons
C'Ommissi'On is investigating the extent and directi'On 'Of their resP'Onsibility in this area. It is 'Our
h'Ope that, as a result 'Of thi~ inquiry, regulat'Ory
policies c'Ognizant 'Of the unique requirements 'Of
the data pr'Ocessing industry will be pr'Omulgated.
As the cust'Odian 'Of the public interest, it is the resP'Onsibility 'Of g'Overnment regulati'On and public
P'Olicy t'O f'Oster the devel'Opment 'Of such services
that will n'Ot impede the gr'Owth and devel'Opment
1473
1474
Fall Joint Computer Conference, 1968
of data processing but will permit the latter to develop along its own economic course.
The need for a more data-'Oriented communications service exists. The technology for providing
such a service, with its resulting reduction in unit
cost, is available. Our purpose is to suggest that
this technology must be implemented so as to satisfy the present and future demands already evident. Several techniques fur providing the indicated services have been suggested. (See, for example, Davies, 1967 or Mills, 1965.) We propose,
as an example, one such technique and present the
potential benefits of its implementation.
The development of remote real-time computer
access
The concept of time-sharing a real-time computer is not new-as such it was proposed as
early as 1959 and had been implemented at various
places on a limited basis as early as 1963. Although there are many advantages to the user of
such systems, the maj or ones seem to stem from
the ability of a computer user to work at his most
advantageous speed, c'Ommunicating with the remote computer at a time and place convenient to
the user. From the standpoint of efficient usage
of the computer system, such usage also has its
advantages: the larger computer is not required
to spend valuable time waiting for a human t'O
make decisions, communicate a line of input, or
even wait for a mechanical device to transmit signals. While the user, for example, is typing a line
of input to the system, thinking about what he is
going to do next, 'Or seeing a line of output being
typed, the computer can be servicing many other
users.
Of potentially greater advantage, the availability of remote access computer systems reduces
the user's dependence on having close physical access to the actual computer system and instead,
allows the user to gain access t'O the computer system through communications channels-independent of his location. This ability to use a computer
from afar has led to the concept and development
of the "remote service bureau," 'Or "computer utility," to provide the user with computing power.
Although many different systems have been developed under various names 1 they all have one
thing in common-many remote users are connected simultaneously via communicati'On channels to a central computer.
The problems with remote real-time computer
access
At the present time, relatively little "remote
use" of these systems from distances of more than
a few miles has occurred. This is a result of the
high cost 'Of using a communications network-designed for voice-for the transmission of data.
The characteristics of data transmission are sufficiently unique and the potential demand sufficiently great, that a system designed for voice
communication cannot be expected to provide the
required services, efficiently and ec'Onomically,
over the long run.
In order to make effective use of most real-time
computer systems, the user's remote console must
be C'onnected to the computer facility for the entire time he is working. This is expensive. For
other than "local" service, where the cost is nominal, the cost of remote usage creates an effective
barrier against geographically extended use of
computers.
To provide a more c'Oncrete example of these
costs, we have presented the approximate charges
per hour for non-permanent telephcne and teletype grade lines between Boston and several cities
in Table I.
TABLE I -Typical hourly costs of dial-up
communication channels
Between Boston and:
~ew
York
Washington, D.C.
Chicago
Dallas
Los Angeles
Telephone
Mess9.ge Toll
Teletype
TWX
$12
$18
$24
$27
$30
$21
$24
$30
$33
$36
These fixed hourly charges are incurred as a
result of being connected to the interactive c'Omputer system by "long-distance" telephone or teJetype lines, irrespective of the actual amount of
,vork done or the number of messages transmitted
between the user and the computer. During an
average hour 'Of console hookup, a user might be
billed for $10 to $20 of actual computer (main
frame) usage. A local user (within the local telephone service area) of a Boston-based system
would be billed $0.60 per hour for communicati'On
channel usage; a user in Washington, D. C., $18,
Real Time Computer Communications and Public Interest
and one in Los Angeles, $30. The tariff structure
under which this communication service falls is
based upon the assumption that most of the time
the communication channel is actively connected,
it will be used to transmit information and, thus,
one full-time circuit would be required for each
connection. Although this assumption of relatively full utilization of the communication channel is
satisfactory when voice communication is being
transmitted, it is not when these channels are employed for remote, interactive use of a multi-access
computer system. With such systems, only a small
percentage of the facilities of the communication
channels are utilized-the primary characteristic
of this type of usage is the transmission of a number of small data-content messages with relatively
large delays between successive messages. The
communication channels used for data transmission have the capacity to transmit 'Over 12,000
characters per minute. Currently used remote
console devices have a maximum data rate of 900
characters per minute or less than 7.5% of the
channel capacity. Measurement of users interacting with existing time-sharing systems indicate
maximum use of less than 10% of the capacity of
the console-and, thus, less than 1 % of the capacityof the communications channel (Gold, 1968).
The high "overhead" charge to communicate
with the system will have a detrimental effect upon
the remote computer user. In addition to the
rather obvious one of having to pay the "phone
bill," the user may be pressured into working fast,
thinking fast, editing fast, and making mistakes
fast. This, of course, tends to negate a basic feature of interactive real-time systems-the ability
of the user to work at his own pace, unhurried by
external pressures. Research comparing on-line
computing and the more traditional batch-processing computing indicates this real-time or timesharing access can result in higher performance
(a higher quality product) if the computer is
available to the user upon demand and the output
is generated within a reasonably short amount of
time (Gold, 1967). It would appear, t~en, that
the existing communications service offerings and
the resulting tariff rates-which discourage remote users from having a computer available upon
demand-will be a real and serious barrier to the
effective development of remote u~e of such systems. In view of the unique communication requirements of such systems, a reassessment of the
means of effecting this service appears warranted.
1475
ReqU'/'rements jor remote real-time computer
access
What appears to be needed is a communication
system which will allow the user to communicate
with the remote computer as the need ariseswith a minimum of effort and delay to the user
and at a price not significantly greater than that
incurred by a user located at the r~mote computer
site. Under the existing service and rate structure, the user of a remote computer utility is faced
with several alternative methods of using the communication channels. First, he may maintain the
connection between his console and the computer
for the duration of his computing session, even if,
for the majority of the time, the communications
facility is lying idle. This, of course, is most expensive but provides minimum bother to the user.
Or second, if he wants to economize, he (or the
computer) may break and subsequently re-establish the-connection, by dialing, for only as long as
it will actually be needed. This second alternative
has immediate economic advantages to the user,
but would certainly prove extremely cumbersome
in practice or, for real-time operations where immediate access is normally a requirement, would
prove impossible. In either case, such a scheme
would negate many important aspects of real-time
systems-especially the ability of a user to communicate with a remote real-time computer at a
time and place convenient to him.
It is clear that any attempt to minimize the relatively high cost of the communication channels for
remote computer access through somewhat devious
means would result in a substantial downgrading
of the services provided by a time-sharing system
-as compared with those received by a user at
the facility. Simply -a cheaper system for communicating with the computer utility is not suf:ficient~an adequate system must provide service
similar to that available to a user located at the
computer facility, and must do so at a cost which:
(1) does not act as a barrier to remote use of the
eomputer system; and (2) is somehow proportional to the actual usage of the communication channel and not simply to the time the user is. actively
connected to these channels. This objective of
eliminating the effective barrier to remote computer usage may be achieved by adapting existing
communication plant to the specific requirements
of such systems. The result will necessarily be:
1476
Fall Joint Computer Conference, 1968
(1) a change in the basis of communication
charges-from elapsed time to the amount of information transmitted; and (2) a substantial reduction in the cost of the communication service.
This would attempt tQ change the cost structure
by eliminating the full time devotion of one circuit
to each user-a maj 'Or factQr in present remote
computer usage costs.
Proposed data-transmission service
Computer time-sharing is founded, in part, on
the idea that of the many users actively connected
to the cQmputerat any time, the computer pays
attention only to those requesting service and does
not waste its time by trying to provide service to
the others. Thus, the system as a whole can operate efficiently-charging the users only for the
time the computer wQrks for them. It should be
possible to extend this concept to the communications facilities that are associated with such remote access computer system-that is, provide
a PQol of communication resources for a number
of active users of the system such that, at any instant of time, when' 'One user is not using the facility it is available tQ another user for transmission of his data. As an example, a computer utility
in, say, Boston might have fifty active users in the
New York area. Rather than establish fifty independent connections between N ew York and Boston as must be done presently, it should be possible
to connect each New York user to some c'Ollection
point in the N ew York area; either through a permanent connection or by dialing, and then have
some smaller number of pooled circuits between
this. collection point and the computer in Boston.
Equipment at the collection point would take care
of assembling complete messages from the user
(and the computer) and assigning an open line to
transmit the entire ~essage at full line transmission speed. Once the message was sent, the line
could be made available for the next message to
be sent-in much the same way as the main control unit at the central computer assigns the various components of the cQmputer system among
the various users. Although this would reduce the
"rent" on the 'communication circuit to a small
percentage of its previous cost and, thus, provide
more efficient usage, there 'would be a cost for the
switching hardware which could be substantial' if
shared only by a small number of users.
In the more general case, however, it would per:-
haps be unwise for each computer utility to establish such c'Ollection points. The economies of a
larger scale operation would be significant, while
the cost of anyone collection point operated independently might well exceed the savings derived
from it-such a system would only functi'On efficiently when a sufficiently large group of users
made it econQmically practical.
However, this problem can easily be eliminated
by pooling the entire system of remote computer
users and providing one communication system
which they could all share-p'Ossibly within the
structure of present or proposed communication
systems. Such a system could operate more efficiently because the' requirements of one large
group of users could mQre accurately be predicted
than thQse 'Of several smaller individual groups.
In addition, the entire system could afford· to
maintain (in the short-run) a portion of the network which does not have a sufficiently large number of users-sQmething nQt possible with a number of independent cQllection points.
There appears to be ample technical and economic justification fQr such a system. First, it is
technologically possible for a common carrier to
'Operate public "collection points" of the type mentioned above-in fact, this has been done for overseas telephone calls. In the case of overseas telephone conversations, the pool of two-way circuits
is shared among a larger number of individual
calls. The callers have access to the pool only when
they are actually talking, and in only the direction
that the talk is traveling. Second, as the demand
for this type of service increases, the number of
users of different computer utilities. Thus, Bossible to share communication facilities among
users 'Of different cm;nputer utilities. Thus, BostQn users 'Of aNew YQrk cQmputer utility might
share a PQQI 'Of circuits with New York users of,
say, three different BostQn computer systems.
To provide a concrete example of the savings
which CQuld result frQm implementation 'Of the
prQPQsed system, we have presented hourly communication channel costs under both the present
system and the 'prQPosed system based on permanent service between Boston and several cities
in Table II. The calculations include the costs involved in sharing the lines and transmitting data.
Local termination charges (as much as $0.60 per
hour for a local dialed connection) are not included.
Real Time C'Omputer Communications and Public Interest
TABLE II -Comparison of hourly charges under present and
proposed communication systems
Between Boston and: Dial-up Cost
New York
Washington, D.C.
Chicago
Dallas
Los Angeles
$12
18
24
27
30
Proposed System's Cost
50 User*
100 User*
$0.44
0.47
0.52
0.59
0.70
$0.42
0.43
0.46
0.49
0.54
*These figures are based on the use of the system 40 hours a
week. Substantial reductions in these costs could be effected
through the use of this equipment more than 40 hours per week.
See the Appendix for the derivation of these costs.
CONCLUSION
It is essential to the public interest that both the
common carriers, who provide communications
services, and the public agencies who regulate
them recognize the potential importance to the
public of modern computer technology and offer
communicati'Ons services that will serve and encourage its development. Rates for such service
should not be out of line with the value it may add
to the total system; they should be based not upon
the elapsed time 'Or duration of the connection but
instead upon the amount of data transmitted by
the carrier. Changes from the present technique of
full-time use of a circuit to a method enabling a
large number of active computer users to share
a small number of these circuits can meet this
goal. Although such techniques might be implemented on a limited scale by small groups of computer users and computer service suppliers, the
full development of a widespread network of such
data-oriented communications facilities is rightfully the responsibility of the communicati'Ons
common carrier. It is essential that the communications companies and the regulatory agencies
take appropriate action now to bring about· the
econ'Omically viable shared-facility data communications services.
BIBLIOGRAPHY
1 American Telephone and Telegraph Company Tariffs
Federal Communication Commission Nos 132 130
2 DWDAVIESetal
A digital communications network for computing giving· rapid
response at remote terminals
Symposium on Operating System Principles ACM October
1-41967 unpublished
1477
3 Digital Equipment Corporation
Price listfor PDP-8
Maynard Mass 1967
4 MMGOLD
A metlwdology for evaluating time-shared computer usage
Carnegie Institute of Technology 1967
5 MMGOLD
Communication circuit utilization during experimental timesharing operation
Unpublished report 1968
6 RSGRISETTI
The synthesis oj communications and computers
In F Gruenberger (ed) Computers and Communications
Toward a Computer Utility
Prentice-Hall Englewood Cliffs 1968 pp 209-219
7 RGMILLS
Communications implications of the Project MAC multipleaccess computer system
IEEE Convention Record 1965
8 PEMUENCH
Common carrier approach to digital data transmission: terminals transmission equipment and future plans for the compuler utility
in F. Gruenberger (ed) Computers and CommunicationsToward a Computer Utility
Prentice-Hall Englewood Cliffs 1968 pp 209-219
9 LLSELWYN
The Information Utility
Industrial Management Review
Vol 7 No 21966 pp 17-26
10 D DIAMOND LLSELWYN
Considerations for computer utility pricing policies
Proceeding of 23rd National ACM Conference 1968 pp. 189200 Brandon Systems Press Princeton, New Jersey
Typical Hardware Costs
PDP-8
(one end)
Extra 4K memory
CAB-8B
681 Interface
685 Multiplexor
W750 Modules (64)
DF32 Disc file and controller
CAB-B-S
637B Dataphone interface $ 49,350
PDP-8 (second end)
49,350
PDP-8 (2 - one each for redundancy)98,700
Total hardware cost for 64 lines
$197,400
Equivalent m'Onthly rental
$ 4,400
Equivalent hourly rental (40) hrs./wk)
25
0.39
Equivalent hourly rental per full-time line
Full duplex leased line monthly cost with channel
terminators
1478FaU Joint Computer Conference, 1968
Monthly
Cost
Boston to New York
Boston to
Washington, D.C.
Boston to Chicago
" Dallas
"
II Los Angeles
"
Hourly Line
Hourly Cost Cost per User
(40 hrs.jwk.) (50 Users)
$ 445
$ 2.53
$0.05
721
1144
1750
2656
4.10
6.55
10.00
15.20
0.08
0.13
0.20
0.31
If we further assume only 50 % system utilization, we should double the ab'Ove costs, e.g., for
Boston to Los Angeles, the. hourly hardware cost
would be $0.39 and the line charges (with 50
users), $0.31-for a total of $0.70. With only 50%
utilization the c'Ost would be $1.40.
With more than one shift operation, the costs
would be reduced, e.g., B'Oston to Los Angeles for
80 hours a week .(with 50 % utilization) would
c'Ost $0.70 per hour.
It should be emphasized that these figures are
used for demonstration purposes only.
The two extra computers are for redundancy
only; more economical methods of providing this
redundancy would probably be available.
These costs are based on the research investigating the amount of data transmited by users of
time-sharing systems ,(Gold, 1968). In all cases
studied, the circuit utilization was significantly
less than 1 % 'Of the advertised half-duplex capacity. It would thus appear that up to 100 simultaneous users could be handled by such a circuit;
the cost data, however, is for full-duplex circuits.
Use of inexpensive scope displays indicates data
transmission requirements of these devices may
be double those of existing cons'Oles-or a maximum of 50 users per circuit.
Toward education in real time
by PERRY E. ROSOVE
SY8tem Development Corporation
Santa Monica, California
INTRODUCTION
The Bureau of Research of the U.S. Office of
Education, in January 1967, expressed ~ts concern with the potential impact of sOCIal and
technological changes on the formulation of educational policy. This concern was manifested in
the creation of five, nine-months pilot centers
for educational policy research with funds made
available by the Bureau of Research under Title
IV of the Elementary and Secondary Education
Act (PL 89-10). The primary task of the centers,
according to the Bureau, was "to analyze future
educational needs and resources and, in light of
these analyses, provide educational policy makers
at all levels with relevant informati'On and techniques for decision making."1
The Request for Proposal (RFP) distributed
by the Bureau of Research reflected a concern
with what may be referred t'O here as a temporal
lag between the future needs of education and
current educational policies, objectives, and programs. The RFP called attention to alleged "revolutions" in population growth, civil rights, urbanization, automation, etc., and asked the centers
to address themselves to the implications of these
revolutions for current and future educational
policies. In the wording of the E,FP, the U.S.
Office of Education explicitly rec'Ognized that the
response of the educational community to largescale social and technological changes was excessively slow and that it was necessary, therefore,
for educators and other responsible authorities to
attempt to "invent alternative futures."2
The problem of anticipating the future is especially difficult for educators. Policy makers in
noneducational areas may be required to plan
for a future that 'extends five years, or perhaps
ten years, ahead. But in educati'On, decisions must
1479
be made today for a future that is a generation
away. A child starting school this year (1968)
will be in the prime of his adult life' in twenty
years. Will the, education he will receive during
this period of time prepare him adequately for a
lifetime of work and self-fulfillment? How relevant is today's education for life in the 1980's
and beyond? Do today's educators carry out their
tasks with that future in mind or is it the past
and the present which provide them with guidelines?
These, then, were the general issues which the
five pilot centers were requested to probe. T'O
carry out the Bureau of Research's objectives,
approximately $110,000 was awarded to each of
the centers. They included the Stanford Research
Institute, a consortium 'Of Syracuse University
and the General Learning Corporation, Western
Behavioral Sciences Institute, the National Planning Association, and the System Development
Corporation.
Ea:ch 'Of the pilot centers was required by the
Bureau of Research to design "a model operational center." It was the intention of the Bureau,
based upon the performances of the pilot centers,
to select two or more 'Of them to become 'Operational centers with long-term contracts and with
expanded staffs. Selection of the pilot centers
would depend heavily upon their designs f'Or operational centers. In additi'On to' this requirement
which was levied on each pilot center, the System
Development Corporation's pilot center, named
the Educational Policy Research and Support
Center (EPRSC), elected to focus its attention
on tw'O areas: * (1) the applicability of available
forecasting methods to the study 'Of the future
*The EPRSC subsequently developed studies in other areas
but they are not discussed in this paper.
1480
Fall Joint Computer Conference, 1968
of education and its social and technological environment; and (2) the possible roles of educators in the late 1980's. This paper describes some
of the results of the work done in these areas,
specifically with respect to the concept "real time."
The first objective was selected for fairly obvious reasons. The field of forecasting, if it may be
referred to as a "field," is relatively new. It
seemed necessary, as a preliminary step, to investigate what forecasting methods were available and to determine which, if any, might be
appropriate to employ in a study of the future of
education.
The second objective, the possible roles of educators in' the late 1980's, was selected since such
roles are central both to the educational process
and to education as an institution. Educational
policy making at all levels is concerned with them.
If the roles of educators were to change drastically during the next twenty years, as many
experts predict, this change would require important policy decisions affecting broad areas of
education.
Contextual 'fYU];pping
Early in the life of the SDC pilot center, the
writer conducted a survey of forecasting methods
to determine which method or methods might be
relevant to the substantive issues - referred to
above. As a result of this survey, it was decided
to concentrate upon and experiment with an
extrapolative method known as "contextual mapping," which may be briefly defined as a graphic
display of the logical and causal depedencies of
functionally related phenomena. 3 The selection of
this method by the EPRSC staff was based on
the philosophy that the formulation of educational
policy would be facilitated by the development of
a forecasting, method which would lend itself to
public scrutiny and debate.
Over a period 'Of approximately three months,
a contextual map was constructed. The map was
composed of a two-dimensional matrix containing
36 cells (see Figure 1). The vertical axis of the
Major Sub-Trellds
Social and Techn1cal Implications
Implications tor
Education
Educational
Functions
P088ible Future
Role8
MaJor I8sue8
lA
2A
3A
l!A
5A
6A
IDcreaa1ngq sensate,
empirical, humanistic,
prapatic, utllitarian
culture.
1B
2B
3D
4B
5B
6B
(EcOnomic Sector-National)
Transitional, mas8-COnsumption society characterized
by h1g!Ier GNP and per80nal
1nccmes, affluence (among
better educated).
lC
2C
3C
4C
50
6c
lD
2D
3D
4D
5D
6D
1E
2E
3E
4E
5E
6E
IF
2F
3F
411'
511'
611'
Basic, Long-term Trends
(Cultural Sector)
Increaaingq se1Ulate,
empirical, bumani8tic,
pl'II6JII&tic, utilitarian
culture.
~-------------(Socio-cultural Sector)
(Economic SectorInternational)
World-vide II1d~al1zation
and lIIOdern1zatlon.
(Science & Technology Sector)
(I Organization)
Institut1onalization ot
chazlge, especi~ through
research, development, innovat10n & organized dlffu8ion.
(Science & Technology Sector)
(II Information)
Accumulation ot scientific
and technological
IaIovledge.
FIGURE I-An EPRSC contextual map (roles)
Toward Education in Real Time
matrix was divided into rows, each of which
represented "basic, long-term trends" of Western
civilization. These trends were adapted from the
work of the Hudson Institute. 4 To facilitate the
mapping process, the basic, long-term trends were
grouped, as indicated by the double lines in Figure
1, into three major "sectors" and a total of six
subsectors were identified as rows of the matrix:
cultural, socio-cultural, economic-national, economic-international, science and technology-organization, and science and technology-informati'On. Since the basic, long-term trends were too
broadly conceived to lend themselves readily to
the derivation of logical and causal dependencies,
each of the six sectors was further divided into
three functionally distinctive areas providing a
total of 1'8 rows in the matrix, each row identified
as shown in Ta.ble 1.
TABLE I-Eighteen rows of the contextual map matrix
Ba8ic, Long-Term Trends
Cultural Sector
~ocio-Cultural
Sector
Economic Sector-National
Rows of Contextual Map
1. Pragmatism
2. Values in Art, Religion,
Philosophy
3. Permissiven(>~s re: Mores
4. Rising Aspirations of
Disadvantaged
5. Urbanization
6. Changing Aspirations of
Middle Class
7. Occupational Changes
8. Controlled Economy
9. Social Growth
Economic Sector-International
10. Industrialization-World
wide
11. Internationalism
12. Transportation and Communication
Science and Technology
Sector-Organization
13. Technological Replacement
14. Tempo of Change
15. Technological Complexity
Science and Technology
Sector-Information
16. Information as Waalth
17. Growth of Knowledge
18. Information Technology
The horizontal axis of the map matrix was
divided into six columns which were designed to
1481
show the logical and causal sequences of events,
trends, conditi'Ons, and pr'Ocesses associated with
each 'Of the 18 functionally distinctive areas 'Or
r'Ows. As sh'Own in Figure 1, the six c'Olumns
included:
•
•
•
•
•
•
Major Subtrends
S'Ocialand Technical Implications
Implicati'Ons f'Or Education
Educati'Onal Functions
P'Ossible Future R'Oles (for educat'Ors)
Maj'Or Issues (in education)
The selecti'On 'Of these column headings reflected
b'Oth a logical sequence and the substantive concerns of the SDC pil'Ot center, e.g., the implicati'Ons 'Of s'Ocial and techn'Ological trends for educati'On and the r'Oles 'Of educat'Ors.
Trends, events, c'Onditi'Ons, and pr'Ocesses were
represented in each cell 'Of the matrix by "entries"
(see Figure 2). Each entry was encl'Osed in a
rectangular b'OX and numbered t'O facilitate identification. Entries which were regarded as especially important were set 'Off from other entries
by heavier lines. Lines joining the entries indicated hypothesized logical and causal sequences.
D'ependency relati'Onships fl'OW fr'Om left to right.
The c'Ontent of initial entries f'Or the first C'Olu:mn
'Of the map in Figure 1 was obtained from an
extensive review 'Of the published literature dealing with social and technological trends in additi'On to the w'Ork of the Huds'On Institute referred
t'O ab'Ove.
It sh'Ould be emphasized that each entry was
regarded as an hYP'Othesis which was and is subj ect t'O debate and revisi'On as relevant data bec'Ome available. While the c'Onstructi'On 'Of the map
in the EPRSC was the w'Ork 'Of one individual, it
was anticipated that it W'Ould be the responsibility of an interdisciplinary team to review and
develop it further in the operational center.
It is n'Ot necessary f'Or 'Our purposes here to
repr'Oduce the c'Ontents 'Of the entire map. A document describing the c'Ontextual mapping meth'Od
and' c'Ontaining all the map entries may be obtained fr'Om SDC 'Or the writer UP'On request. 5
However, t'O illustrate the content of entries and
h'OW entry relationships are graphically portrayed,
Figure 2 reproduces a segment 'Of the map, cell lB.
The extrapolati'On 'Of current s'Ocial and technol'Ogical trends into the future resulted in the conclusi'On that existing educati'Onal organization and
1482
Fall Joint Computer Conference, 1968
MAJOR SUB-TRENDS
BASIC, LONG-TERM
TRENDS
4.1
4.0
RISING ASPIRATIONS
OF DISADVANTAGED
~ TREND TOWARD HIGHER ASPIRATIONS
AMONG THE DISADVANTAGED PORTIONS
OF THE POPULATION.
4.2
I1
-I THERE WILL BE A MAJOR SHIFT IN CLASS-I
RELATED VAlUES Iii WHICH THE LOWERIClASS
WILL BECOME "STRIVERS".
5.5
5.9
IRAPID INCREASE IN NEGRO PARTICIPATION I
I NEGROES GAIN POLITICAL CONTROL OF SEVERAL
.1
I OF THE LARGEST CITIES IN THE NATION.
liN POLITICAL ACTIVITIES; BLACK POWER
MOVEMENTS; BLACK NATIONALIST GROUPS.
I
5.1
5.0 URBANIZATION
~1
TREND TOWARD URBANIZATION
CONTINUES WITH THE GROWTH
OF MEGALOPOLISES.
J
5.4
I
5.7
~
NEGROES WILL COMPRISE AN INCREASING
PROPORTION OF THE POPULATION IN
I URBAN CORE AREAS (GHETTOS)
II
~ TREND
TOWARD INCREASING VIOLENCE I
IN URBAN GHETTOS.
--1
5.8
5.2
J
URBAN LIFE BECOMES INCREASINGLY UGLY, NOISY,
DISORGANIZED, UNSAFE FROM TRAFFIC, CRIME, AND
POLLUTANTS.
(SOCIO-CUL TURAl
SECTOR)
INCREAS INGL Y
SENSATE.
EMPIRICAL,
HUMANISTIC,
PRAGMATIC,
UTILITARIAN
CULTURE.
6.0
CHANGING ASPIRATIONS OF MIDDLE
CLASS
Y
5.3
THE MIDDLE-ClASS CONTINUES THE FLIGHT
TO THE SUBURBS AND JOINED BY UPPERLOWER CLASS WITH INCREASING AFFLUENCE.
6.1
~
INCREASING AFFLUENCE IN THE MIDDLE-ClASS
UNDERMINES TRADITIONAL CONCERNS FOR
ACHIEVEMENT/ADVANCEMENT/CAREERS.
I
I
I
WHITE BACKlASH AGAINST NEGRO POLITICAL ACTIONS, I
BLACK POWER ADVOCATES, ETC •• RESULTS IN MUCH
POLITICAL CONTROVERSY IN BIG CITIES.
5.6
MAJOR EFFORTS ARE UNDERTAKEN TO SALVAGE
AND REBUILD URBAN CENTERS.
6.2
I
6.4
, C",""NAN' "EROSION
.. , .,.,,'<""
W,"
~ THE
"'N'
" " "••
"'''''''NG
''''-'N' 'N
I..EXPERIENCE
OF WORK-QRIENTED,
NUMBER
OF AN
YOUNG
PEOPLE INTERESTED
IACHIEVEMENT-oRIENTED VAlUES.
IN CAREERS IN BUSINESS AND INDUSTRY.
I
6.3
I AlIENATION(?) I
FIGURE 2-Segment of the contextual map: CelllB
the generic concept of the role of the "teacher"
would be incompatible with future conditions and
requirements.
Our review of the published literature dealing
with educational reforms, which was conducted
over a period of three to four months following
the construction of the contextual map, revealed
that while current reform efforts are highly significant and major undertakings, they can only
be characterized as piecemeal and inadequate
efforts. They represent a form of tinkering with
existing educational roles, curricula, and organization which leaves the contemporary educational
system essentially unchanged.
The remedy proposed most frequently by educators to accelerate adaptive changes in education
is the improvement of the educators' education.
But this does not appear to be an adequate response to the problem. The extrapolation of current trends, particularly in the six rows of the
map comprising the science and technology sector
(see Table 1), highlighted the exponential growth
of knowledge, the obsolescence of existing knowledge, and the proliferation of new specialties.
How can the pre-service training of educators be
altered to conform with such changes on a continuing basis?
The fact is that schools at all levels of the
educational system below the university level,
including the schools that prepare educators, are
autonomous institutions and relatively isolated
from developments, new knowledge, and changes
Toward Education in Real Time
occurring in other areas of society.6 Although research is a major function of universities, it is
not conducted at lower levels of the system. The
new Research and Development Centers established by the U.S. Office of Education do not alter
this basic pattern in which the generation of new
knowledge, even new knowledge .concerned with
learning processes, is the responsibility, not 'Of
teachers, but of other professionals such as experimental psychologists. Thus there remains the
fundamental question of how new knowledge,
either in subject fields or in the learning process,
is injected into the elementary and. secondary
schools. As academic critics of contemporary education have too often noted, what is taught in
the schools may be as much as thirty years behind
new developments ;7 and the isolation 'Of the
teachers from sources of new knowledge too frequently results in the dissemination of either
"trivia" or "untruth."s
Three basic organizational concepts for the
Functional Areas From The
Contextual Map
1.
Industrialization - Wor1dwide
2.
Internationalism
1483
education of the future evolved out of our construction of the contextual map and the review
of the literature on educati'Onal reform. The sequence of logical steps and tasks which were followed to derive the organizational concepts and a
new generic role concept of the teacher ("learning facilitator") is shown in Figure 3. In the
balap.ce 'Of this paper, we shall limit our remarks
to the conception of the learning environment as
a real time facility.
Education in real time
In the language of the information sciences, *.
education currently occurs in a non-real time
mode but it may increasingly have both a need
and a capability for 'Operating in real time. The
*The term "information sciences" is used here to apply, in the
broadest sense, to those fields concerned with information-cybernetics, computer science, data processing, system analysis, information storage and retrieval, etc.
Basic Organizational. Concepts
Generic Role Concept
3. Transportation and Communication
4.
Rising Aspirations of Disadvantaged
5.
Urbanization
1.
6. Changing Aspirations of the
Middle-Cl.ass
The Learning Env1roDD~nt as a
Real Time FacUity
3. TASK OF
ROLE DESIGN
7. Occupational Changes
8. Controlled Economy
9.
2.
Social Growth Indicators
10.
Prat?Jll&tism
ll.
Values in Art, Religion, PhUosophy
12.
Permissiveness re:
The Continuous, Vertical, Learning
Organization Serving All Educational
Level.s
1.
The Generic Role of
the Learning FacUitator
as a Counselor, Engineer,
Instructor, and Researcher
Mores
13. Technological Repl.acernent
14.
Tempo of Change
15.
TechnolOgical Compl.exity
3. The Learning Environnent as a
MUlti-Purpose Facility
16. Information as Wealth
17. Growth of
18.
Knowl.edge
....~---f
1. TASK OF TREND ANALYS
AND CONTEXTUAL M6.PPING
Information Technology
FIGURE 3-Sequence of logical steps and tasks to derive the generic role concent
1484
Fall Joint Computer Conference, 1968
changes displayed on the contextual mapchanges in society, in the economy, and in science and technology-imply a reduction in the
amount of time available for institutional adaptation. Education, from the point of view of its
timeliness, can operate effectively in isolation
from other institutions when change is relatively
slow; it cannot be equally effective in isolation
when change is relatively rapid, as is now the
case. Hence we are led inexorably to the idea
that within the next twenty years learning environments ought to be designed more like realtime information processing systems.
In the United States since the turn of the century, with the advent of the free public. school
system, formal schooling has become increasingly
isolated from the "real" world both in time and
space. In primitive and peasant societies, as well
as in apprenticeship programs within our own
society, learning is closely geared to the world of
reality. The child in a nonliterate society may
be taught his cultural traditions by his kinsmen
as he participates with them in hunting or foodgathering expeditions. In peasant societies skilled
craftsmen, artists, and priests transmit their
stores of knowledge to their designated successors most typically as an on-the-job experience.
In agricultural communities, children acquire the
cultural heritage and necessary technical skills
as they labor beside their elders in the fields or
rice paddies. In all of these situations, one learns
by doing in the real life environment. Formal
schooling, if it exists at all, represents only a
fraction of the learner's time. But, increasingly,
as our institutions have evolved, as specialization
has increased, and as the amount of knowledge
required to perform occupational tasks has accumulated, the amount of time required 'Of the
individual to devote to formal schooling in institutions physically separated from the nonscho'Ol
world has increased. Since the end of W'Orld
War I, welfare legislation has required the child
to spend more time in formal school environments
while apprenticeship opportunities have declined
in number. Indeed, if contemporary trends continue, it may soon be mandatory for all citizens
to remain in school through the associate of arts
or the baccalaureate degree level. Thus, unless
there is a reversal 'Of this trend, the "school" as
an instituti'On, very much like the penitentiary,
will prolong and exacerbate the isolation of the
young from the real world.
In the traditional notion of the "school" as the
basic learning environment, its isolation from the
world of reality or "real life" has taken three
forms: (a) education is separated from the
world of work; (b) learning is separated from
research on the learning process; and (c) education as a discipline is separated from the other
academic disciplines. We propose here a concept
of the learning environment in which these separations are drastically reduced.
A real time approach to education and work
Formal schooling as a prelude to entering specialized occupati'Ons and professions is based
upon an assumption that the fund of knowledge
needed by the student in preparation for life is
relatively static. It is also based on the assumption that the number and variety of occupations
and professions are unchanging and that each
individual will be prepared during his formal
school years to enter and remain in one occupation or profession throughout his lifetime. Indeed, in the past if an individual changed his
specialty too often it was not uncommon t'O interpret this as a sign of personal instability or, worse
still, as opportunism. The "jack-of-all-trades" has
never been regarded as a social success. "Finding
one's self" for a male was synonym'Ous with identification with one's specialized field.
These assumptions contributed to the conception of formal education as something separate
in time and space from the w'Orld of work. One
went to school for a fixed period of time. One then
graduated and went to work, presumably, until
retirement or death, in the field of one's choice.
The readers of this paper, perhaps more than
other audiences, can appreciate how archaic such
notions are. Who among us is in the occupation
or profession for which he prepared himself so
assiduously in college or graduate scho'Ol? Today
it has become almost a cliche to comment, since
Margaret Mead first made the remark, that young
people will have four or five different and successive jobs or careers in their lifetimes. Thus the
references to education becoming a "continllous,
lifelong" process have become comm'Onplace in the
ed ucational literature.
If one accepts the idea of continuous, lifelong
education seriously, then we should n'O longer retain the notion that the lives of future students
Toward Education in Real Time
should be divided into two distinct phases-an
educational phase and a working phase-dich'Otomized by an ancient ritual called "graduation."
If we take seriously the idea that each individual
will have several different jobs, occupations, or
careers in a lifetime, then education has no termination; there is, rather, interspersed periods of
education, work, reeducation, work, ad infinitum.
From this perspective the concept of the "school"
as the place where education occurs is obsolete.
Professional educators are attempting to cope
with the impact of an accelerating rate of change
in science and technology on educational institutions or, rather, the lack of impact. However, it
does not appear to this writer that their recommendations are adequate for the future conditions
which they themselves anticipate. Grant Venn,!}
for example, maintains, in his study of postsecondary vocational and technical education,
that the problems of an excessive student dropout
rate and the unemployment and underemployment
of dropouts can be attributed to the liberal, academic orientation of the educational community
which is of no 'interest to 80 percent of the student population. The time has come, he asserts,
for schools and colleges to recognize that the new
occupations spawned by science and technology
"must be taught where they are best able to be
learned." Venn believes existing educational institutions are the best places to achieve this,
although, as he points out, they have failed to
perform this task successfully in the past. He
hopes that they can be reformed. But are they
failing, as Venn maintains, merely because 'Of a
liberal, academic orientation, or is it not also
bec~~use today's educational system operates in a
temporal mode which is out of gear with the rate
of change in science and techn'Ology? It is our
contention here that the institutional isolation of
the typical school, at elementary, secondary, and
college levels, makes it impossible for it, with contemporary methods of pedagogy, to cope with the
rapidity of change characteristic of what Venn
calls the "new technology."
Whether the objective of education is "liberal,"
"academic," "humanistic," etc., designed to prepare the student for citizenship and self-fulfillment, or whether its obj ective is to provide the
trained technical and professional manpower for a
highly industrialized society, the isolation of the
formal school system from the real world remains
a fundamental problem.
In addition, the individual while on the j'Ob
1485
should, in the future, remain closely tied to educational processes. He may have as much need
for information and new knowledge, if he is a
technician, scientist, or professional, as the formal
student in today's scho'Ol environment. The acceleration of production of new knowledge, the
obsolescence of existing knowledge, and the proliferation of new specialties which we can expect
to follow in the wake of scientific developments,
suggest that the learning process must become
a real time process in which it will become increasingly difficult t'O differentiate between work and
education. This is the essence of a "learning society." To the extent that knowledge generation
becomes a basic process of our society and knowl- .
edge the major product, developments which have
already been predicted by Machlup,10 then the
knowledge bearers in society must become lifelong learners and education must become a real
time, continuous process.
A real time approach to research on learning
processes
Traditi'Onally the function of teaching and the
task of conducting research on learning processes
and educational techn'Ology have been separated.
The isolation 'Of the elementary and secondary
teacher from the sources of new knowledge in
these areas, while 'On the job, has been accepted
as inevitable. But, less excusably, the educati'On
of the educators in teachers' colleges has also
been isolated from the research on learning conducted by university scholars and other types 'Of
professional researchers.
A real time approach to research on learning
processes becomes technically feasible as soon as
one introduces the computer into that process
and begins to c'Onceive the learning environment
as a man-machine system. In man-machine system theory, the system need not be regarded as a
static entity but as evolutionary in character. The
system may be perceived in the spirit of experimental inquiry. Every employment of c'Omputerassisted instruction may be regarded as an experiment, the object of which is to evolve a more effective man-machine learning process. The c'Omponents of the expei-imental situation include such
items as: the computer programs, the displays,
the data formats, the mechanisms provided for
stUdent-computer interaction (input and output
devices), the sequencing and branching of subject
matter, the measurement, recording, and evalua-
1486
Fall Joint Computer Conference, 1968
tion of the learner's performance, and his associated behavior. The results of the learner's performance can be recorded and stored in the
computer's memory for later review and analysis,
or the results may be presented immediately for
review and study by the learning facilitator
("teacher"). Computer languages written in natural English may make it possible within twenty
years to modify subject matter or its sequencing
or branching on the spot or to make revisions
immediately following a man-computer run. Sackman, for example, foresees a time in the near
future when the computer facilities of man-machine educational systems would make possible a
continuous series of experiments "directed to their
own operations and aimed at the improvement of
their own design and performance."ll Such educational systems would undergo an evolutionary
development as each experiment is carried out.
Computer-assisted instruction makes it possible
for the learning facilitator to obtain almost immediately upon the completion of a lesson an analysis
of that lesson to determine which parts of it
caused difficulties and for which students. The
learning facilitator's function is to modify the instructional programs where the difficulties are
found and then evaluate the changes after another
computer-run with the same students or another,
comparable, group. With this sort of an experimental attitude toward the learning process, the
approach to the design of educational systems is
altered so that if the student fails to learn, it is
considered to be the fault of the system rather
than of the student, and the system is modified
as many times as necessary until a pre-established
criterion of learning success is achieved.12
This point of view has profound implications
for educational policy. It places the "teacher" in
the nerve center of the man-machine learning
system. It makes possible a transformation in the
traditional role of the teacher. While the machine
takes over the function of dispensing facts or
data, or the expl~nation of a concept or theory,
the teacher (1) serves to facilitate the learning
process by providing assistance, guidance, and
counseling as needed by the student; (2) designs
and conducts experiments on the learning process
using the actual learning situation as his laboratory; and (3) contributes to the development of
improved man-machine learning systems and
procedures.
'The transformation of the role of the teacher
into that of a learning facilitator as a component
of a man-machine learning system and as a system designer is fraught with obstacles. The education of today's teachers at the elementary and
secondary levels does not contribute to respect for
either machines or experimental inquiry,13 particularly if the subject of the experiment is the
learning process involving the teacher as one element. Insecure teachers do not appreciate or
welcome having administrators or supervisors
monitor their performances in the classroom. A
revolutionary change in attitude by both teachers
and administrators toward the learning process
as a phenomenon to be investigated while it takes
place-in real time-will be required. It is questionable if such an attitude can be taught in the
colleges which produce our teachers. Who will
provide the necessary instruction? More likely,
an attitude which regards research into the learning process as a proper function of the teacher
while' on the job will occur as computers are
gradually installed in school systems and as individual teachers learn, by trial and error, how to
maximize the machine's capabilities.
A real time approach to subject matter transmission
The institutional isolation of professional educators from their colleagues in the academic disciplines and res,earch organizations should be considerably reduced within the next twenty years.
A number of trends suggest this. To reduce the
widely recognized lag between the creation of new
knowledge in the sciences and the introduction of
this material into the curricula of the elementary
and secondary schools, a large number of multidisciplinary committees, composed of professional
educators and academic specialists, have been conducting extensive curriculum revisions in the
major disciplines during the past. decade.14 Such
committees have been active in biology, ,physics,
chemistry, mathematics, English, social studies,
anthropology, and other fields. The inherent weakness of these efforts is that, -for the most part,
they represent relatively infrequent modifications
to the existing curricula. The participating academicians come and go, while the summer institute is the most common institutional device for
preparing' the professional educators to teach the
new curricula. New .knowledge, however, is continuously being generated in all fields. There are,
Toward Education in Real Time
as yet, no procedures for up-dating the curricula
in a given field as new concepts and data are
generated.
In recognition of the need to reduce the time
lag between the generation of knowledge and its
dissemination to school children, some communities have instituted arrangements with corporations engaged in research tc? have their top engi··
neers and scientists pres~nt lectures. In New
York City, for example, riinecorporations have
agreed to pool their scientific manpower resources
to provide lecturers each.' week on such subjects
as nuclear ~hysics, jet propulsion, and space technology as part of the City's high school program
on contemporary science. 15 Unfortunately, few
communities throughout the United States have
this sort of skilled' manpower available locally.
From a national point of view, this is hardly a
very satisfactory solution.
An associated dilemma is that elementary and
secondary teachers are ill-prepared to present
the basic language and concepts of a particular
discipline. As an anthropologist who served on a
curriculum revision committee for his field at the
elementary school level states, "relatively few
teachers have taken formal courses in anthropology."16 They are prepared as generalists not
as subject specialists. This accounts, unfortunately, for the frequency with which elementary
teachers, and secondary school teachers as well,
tend to teach facts without the conceptual framework which makes the facts meaningful. Yet it is
increasingly recognized by professional educators,
not only the academic scholars, that it is more
important to convey concepts to the student rather
than mere factual data out of context. Does the
long-range solution to this problem lie in better
education for educators or in bringing what the
academic scholars and professional researchers
have to say directly to the student in a form he
can understand?
Educational technology already exists which
can bring real events into the classroom as they
occur. The significance of such a capability can··
not be exaggerated. It is not too far fetched to
hypothesize that today's student rebellions at the
secondary and postsecondary levels might not
have occurred if educators had attempted to bring
the real world into the classroom as a proper
subject for discussion, as a source of raw data,
and for scientific analyses. As Carpenter ha~
pointed out in Congressional hearings on educa-
1487
tional technology before the Subcommittee on
Economic Progress, "what is taught (in the classroom) is so often perceived by students to be
remote from reality, abstract and sterile."17
Computer-assisted instruction and other types
of innovative educational technolOgy, such as
closed-circuit television, video tape recordings,
film cartridges, microfiche, etc., should make unnecessary during the next two decades the existing intellectual isolation of teachers in the lower
educational levels from the universities and the
research community. With appropriately designed
information storage, dissemination, and display
systems, the prototype or experimental forms of
which already exist,18 it should be possible for
new knowledge tn specialized fields, generated at
the university level or in research laboratories? to
be made available to learning facilitators at all
educational institutions or in private homes as
soon as it is in transmittable form. In terms of
technical feasibility, there would be no need for
elementary and secondary teachers to transmit
trivia and untruth to their students if they and
their students were linked via appropriate communication networks to the sources of new knowledge. The teaching of a subject such as biology
need not suffer from a lag of thirty years in the
elementary schools if both the learning facilitator
and his students could view together the lectures
of the most prominent researchers in biology via
teleVIsion, or could operate a computer-driven program dealing with the most recently developed
biological findings and theory. Such programs, of
course, would have to be written and maintained
by the specialists in biology and other sciences.
The qualifying expression here is "with appropriately designed information . . . systems." Our
assumption is that within twenty years the "book"
will be replaced, at least in part, by more efficient
types of data transmitters.19 For example, we
assume that the research papers of investigators
in biology will be available for worldwide transmission via electronic reproducing and transmitting equipment as soon as they are written. We
also assume that important. experiments in' biology and other fields will be observed via TV
networks as they occur.
One of the most important functions of the learning facilitator in the types of learning situations
suggested above would be acting as an intermediary between the scholar or researcher and
the students. His task would be to translate the
1488
Fall J'oint Computer Conference, 1968
concepts and findings of the knowledge generators
into a language appropriate to the educational
level of his students, and to serve, where the learn-:ing situation permits, as a discussion leader, guiding and directing the real time interactions between the scholars or researchers and the students
. S'O that a genuine intellectual exchange can occur.
It should be noted that the installation of
carrels,. in the rooms and dormitories of students
at the college and university levels, whereby they
can switch themselves at any time into instructi'Onal systems, by-passes the teacher (as a data
dispenser) and makes his basic, contempor~ry
function obsolete. If, in addition, two-way communication between academic scholars and students is provided while the learning process is
taking place, the intelligent or gifted student may
become a participant in the generation 'Of new
knowledge. With such capabilities, which are already within the technical state of the art, the
temporal lag between knowledge generation and
its dissemination would be greatly reduced. We
can reasonably anticipate that the transmission
of new subj ect matter will thus gradually evolve
in the direction of real time.
CONCLUSION
Even a relatively uns'Ophisticated form of conjecturing about the future of our society, particularly in the area of its knowledge generating
power, leads to the conclusion, that education in
real time should replace, eventually, the contemporary mode 'Of education. The prototype and
experimental systems for real time education
already exist, but their impact on our educational
institutions has, as yet, been insignificant.
Before this impact can become significant, the
designers and builders of real-time information
processing systems will have to join with professional educators in a concerted effort to define
educational objectives more precisely than heretofore, and then proceed to specify the system requirements to meet those objectives. This may
prove to be a difficult task, but ultimately a more
rewarding one, in terms of its social consequences,
than the introduction of real time systems in the
industrial, commercial, and military spheres.
ACKNOWLEDGMENT
The author would like to express his appreciation
to his colleagues at the System Development Cor-
poration who comprised the staff of the Educational Policy Research and Support Center: Dr.
Marvin Adelson, Director; Dr. John F. O'To'Ole,
Jr., Associate .Director, Jack Jaffe, and Thorington B. Robertson. Their direct and indirect contributions to the research on which this paper is
based is hereby acknowledged. I am als'O indebted
to Dr. Harold Sackman whose independent work
on real time systems contributed to the development of the ideas expressed in this paper.
REFERENCES
1 Policy research center program
Request for Proposal Bureau of Research US Office of Education Department of Health Education and Welfare Washington DC January 1967 pI
2 Ibid
3 EJANTSCH
Technological forecasting in perspective
Organization for Economic Cooperation and Development
Paris France 1966
pp 178-181
4 H KAHN A J WIENER
The Year 2000 A framework for speculation on the next thirtythree years
Vol II of the working papers of the Commission on the Year
2000 Hudson Institute Inc Croton-on-Hudson 1967 Chapter I
5 PEROSOVE
An analysis of possible future roles of educators as derived froma
contextual map
System Development Corporation Santa Monica California
SP-3088 8 March 1968
6 Technology in education
Hearings before the Subcommittee on Economic Progress of
the Joint Economic Committee Congress of the United States
89th Congress Washington DC US Government Printing
Office June 610 and 13 1966
7 BGLASS
Information crisis in biology
Bulletin of the Atomic Scientists October 19,62 pp 6-12
8 R J SCHAEFER
The school as a center of inquiry
Harper & Row New York 1967 p 46
9 GVENN
Man education and work: Postsecondary vocational and technical education
American Council on Education Washington DC 1964
10 FMACHLUP
The production and distribution of knowledge in the United
States Princeton Univeraity Press Princeton New Jersey 1962
11 HSACKMAN
Computers system science and evolving society
John Wil~y & Sons Inc New York 1967 p 531
12 DLBITZER
"PLA TO: Research in automatic teaching at the coordinated
science laboratory University of Illinois The automation of school
information systems
National Education Association of the United States Mono-,
graph No 1 (ed.) D D Bushnell 1964 pp 103-105
13 R J SCHAEFER
op cit pp 33-40
Toward Education in Real Time
14 J I GOODLAD et al
The changing school curriculum
The Fund for the Advancement of Education 1966
15 Technology in education
op cit p 8
16 WCBAILEYFJCLUNEJr
Preparation oj elementrary school units on the concept of culture
Human Organization Vol 27 No 1 Spring 1968 p 8
17 Technology in education
op cit p 78
18 J W LOUGHARY
Man-machine systems in education
Harper & Row New York 1966
19 J C R LICKLIDER
Libraries of the future
The MIT Press Cambridge Massachusetts 1965
1489
A public philosophy for real time
information systems
by H. SACKMAN
System Development Corporation
Santa Monica, California
INTRODUCTION
The electronic digital computer has been with us for
only a single human generation. When spawned in
World War II, the human motivation behind its birth
and development was in the tradition stemming from
the ancient abacus up to the digital machines used by
Pascal, Leibnitz, and Babbage-to relieve the tedium of
laborious computation through machine assistance.
Babbage was attracted to computers because of the endless, repetitive work necessary to produce logarithmic
tables; von Neumann's early interest in computers grew
from its potential as a shortcut computational aid in
such problems as the analysis of atomic reactions.
The social implications of computers caught the public eye in the 1950's when the first real time information
systems were applied to military command and control,
to manned spaceflight, and at the end of that decade, to
initial applications of online systems in business and industry. The time-sharing developments of the 1960's
have extended the twin concepts of online man-computer communication and real time control in the form of
the impending information utility. The speed of technological change in the computer world, coupled with
the lack of an experimental and huxnanistic tradition in
the application of computers, has contributed to a philosophical void in the social ramifications of real time
inforniation systems.
The computer scientist was initially able to take
refuge in the once-respectable but now largely discredited notion that philosophy and human values lie
in a transcendental subjective domain far removed from
the objective operations of science. On the social side,
the experience of the atomic scientists in World War II
has underscored the social accountability of all
scientists in radioactive human debris. On the psychological side, the analysis of scientific problem-solvingin the real world, not the paper world-has shown the
all-too-human behavior of scientists. Human values and
scientific method are passengers in the same boat,
traversing the same stormy sea, sharing a common
destiny.
The public has been insulated from philosophical confrontation with computers because they rarely had
direct interactions with computers. However, the inquiry of the Federal Communications Commission into
the computer/communications industry and the imminence of public computer utilities irrevocably
changes the role of the public from spectator to participant.
.
The refusal to think problems through and to take a
stand is itself a philosophical position-a position of
passivity, drift, solipsism, nihilism, or agnosticismdepending upon one's temperament. The admission of
the need to start thinking problems through and basing
action on rational, tested belief is the admission of a
need fora philosophical quest, for a public philosophy of
real time information systems.
The need for a public philo8ophy
The diverse needs for a public philosophy on the use
of computers for the regulation and control of social
affairs stem from many cultural roots. Perhaps the
most fundamental source is the accelerating tempo of
contemporary change spurred by the advance of science
and technology. Situations and events seem to be moving faster than we can recognize and cope with them.
Social solutions which once had a useful half-life spanning decades now have useful total lives over much
shorter periods and have to be constantly revised and updated along the way to keep pace with changing conditions.
The concept of the real time information system-a
system that monitors events in a specified environment
and controls the outcome of such events in a desired
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Fall Joint Computer Conference, 1968
direction-is a leading technical concept that is being
increasingly applied to cope with fast-moving changes
in many wa1ks of life. The power of computerized real
time information systems to meet rapidly changing
problems and situations has been garnered from over a
decade of experience in computer-assisted command
and control. The technique is well-known: continual
surveillance over the object environment to permit
early warning of critical situations; identification of
problems; corrective regulation- and control in accordance with established standards of system performance;
and evolutionary adaptation of system design and
operations to meet changing conditions.
The real time information system is a new class of
social institution, a more radically powerful and rapidly
responsive social form to recognize, meet and deal with
specified problems at the time they occur and in time to
modify their outcome. If we neglect to formulate desirable social consequences for these new systems, we neglect them at our own peril, and at public peril.
Information power is a new dilemma in modern
society. Social control of information power is a focal
problem for a public philosophy of real time information
systems. Prior to the advent of real time computing
systems, information was c01lected and stored in a manner that tended to separate knowledge from action, as
in books and films. Radio and television allowed more
timely collection and dissemination of information, but
these mass media of communication were still not
linked to direct social action. In real time computing
systems, however, the collection, organization and storage of information leads directly to action, to integrated surveillance and control over the object environment. This dynamic marriage of information and control in real time systems is a fusion of knowledge and
action, and, through directed action in real time, informationis expressed as power.
As more and more. social knowledge becomes computer-accessible, so will more extensive, interlocking,
and more powerful real time systems come into being.
As surely as the night follows the day-or the day follows the night, depending on your outlook-so will computer-~ccessible information be followed by real time
control. In a democracy, the public is the ultimate
source of social power, and information power, accordingly, is ultimately a public trust. A public philosophy
on information power needs to account for new democratic forms and procedures bearing on the organization
and equitable distribution of social information.
Philosophical challenges are encountered not only in
general areas such as meeting the tempo of contemporary change and coping with the· institutionalization of
information power, but also and perhaps most critically
in the problems of social implementation. A workable
philosophical position should provide guide-lines for
social method, for putting principles into practice.
While many agree on broad principles, consensus often
vanishes when details of implementation are hammered
out.
There are many knotty questions facing the implementation of real time information systems in the public
interest. Where does the domain of public information
end and where does the domain of private information
begin? Is the information utility a genuine public
utility and, if it is, what kind of commodity is public
information? Should information be distributed to the
public on a metered basis, as we do with gas, water and
electricity, or should it be freely available as in radio
and television? Should the cultural store of computeraccessible public information be available to all as a
basic human right, supported by the government and
the taxpayer, or should such public infonnation services be supported by private enterprise, or do we need
a judicious mix of public and private support? Who
tests and evaluates real time information systems for
social effectiveness and who evaluates the evaluators?
What legal changes and what new social agencies are
required to safeguard the public interest and to protect
the private interest in the field of information services?
It should be apparent from the foregoing that the
challenge of a public philosophy for real time information systems is, in many respects, unprecedented and
extremely complex, at general levels, in details, and in
implementation. At the same time, the need for such a
philosophy is vital and long overdue. The next section
is devoted to an inquiry into key elements of a public
philosophy of real time information systems; this inquiry then leads to a synthesis of these elements into an
initial philosophical framework.
Elements of a public philosophy
The desiderata of a public philosophy are developed in
three stages, starting from definitions of the area of inquiry, prooeeding to scientific and technical aspects,
and cuhninating with social considerations. Each stage
builds upon and incorporates the preoeding stage.
While the social stage represents the broadest set of elements and requirements, it does not attempt to describe
a substantive public philosophy of real time information
systems, per se, which is the main business of the last
part of this paper.
A philosophy on real time information systems presupposes some definition of the concept of "real time".
Historical interpretations of time, and by extension,
"real time," have assumed the varied forms of the conceptual containers into which notions of time, like a
liquid, have been poured. These interpretations range
Public Philosophy for Real Time Information Systems
from the ceaseless flux of Heraclitus, to the flickering
unreality of Platonic change, to Newton's geometrization of time, to Einstein's space-time, to probabilistic
and indeterminate temporal constructions in quantum physics, to ecological statistical trends in evolutionary time. While probabilistic and contingent interpretations of real time seem to be gaining increasing
ground in the physical, biological and social sciences,
controversy has been and still is the rule.
For present purposes, three aspects of real time are
distinguished: real time events, real time information
systems, and real time science. Each is defined and discussed in turn.
Real time essentially refers to events-their appea.rance and duration, their passage and succession, and the
hypothesized interrelations of events as empirically
tested and demonstrated in any referent system and its
environment. Real time is thus the way events happen,
our description of how they happen, and our best interpretations of why they happen as they do. The definition also implies that warranted interpretations are
those empirically certified by experimental method in a
system context.
Real time information systems refer to systems that
1) continually sense and respond to selected changes in an
object environment 2) in a manner and in tinle to enable
regulation and control over some ongoing events in the
system and its environment while they occur, 3) within
the bounds of minimal or acceptable levels of system
performance as determined by continual test and evaluation of feedback from system events.
As mentioned earlier, the central feature of real time
information systems is direction and control over selected system events while they take place; and in
order to exert such cognizance it is necessary to maintain constant surveillance, identification (decision making), and control to modify the environment as required.
Note that the definition does not mention computers.
It essentially states that any system that is organized
to sense and respond to an object environment accord;..
ing to some criterion of effectiveness is, in principle, a
real time information system. The crux of this definition is that real time systems are not merely passive
spectators of their own events, but are creators of desirable outcomes, that they are active agencies that mold a
partially plastic environment in accordance with a preconceived image.
The next definition-real time science-moves into the
second stage toward a public philosophy: the technical
and scientific stage.
Real time science deals with temporally and situationally contingent events amenable to experimental
method, and it results in an extension of human mastery
over such events; it is broadly eclectic, borrowing freely
1493
from the methods and findings of the pure and applied
sciences, and from any mix of interscience and new
science as required and needed to understand and control real world events.
As we enter into the era of computer-catalyzed real
time information systems, we need a scientific discipline
to develop the theory and practice of real time systems, and the suggested discipline is real time science as
defined above. This definition is different from conventional concepts of science in several leading respects.
First, it explicitly fuses knowledge and action together
as a single entity; no pretense is made for the pursuit of
antecedent, abstract knowledge for its own sake. ·Second, the pursuit of knowledge is for human purposes,
for improving human effectiveness. Third, the proper
object of real time science is real world events-real time
science belongs where the action is. Laboratory events
and abstract constructions are not excluded, but they
are preparatory rather than consummatory in the sense
that they contribute toward the ultimate objective of
understanding, shaping and controlling real world
events for human ends.
The eclecticism of real time science is a restless, fastmoving, aggressive eclecticism, itself changing in real
time with new methods and findings. Real time scienceborrows freely from any established or new experimental discipline that contributes to improved real time system performance. Anyone who has worked in the design
and development of real time information systems is
acutely aware of the eclectic and pluralistic nature of
such systems, of the requirement to optimize interdisciplinary teamwork, of the necessity to adopt new
science and technology into system design and operations, of the open-ended, jazz-like need to improvise
against residual uncertainty, of the need to continually
test and modify system configuration throughout the
entire life cycle of the system.
The relation of real time science to traditional forms
of science is that real time science borrows experimental
method and findings wherever and whenever they are
useful for understanding and directing real world
events. The common denominator is experimental
method. With the advent of computer-serviced societies we may expect a flowering of new species of computer-catalyzed experimental method, particularly in
real time information systems embedded in real world
happenings.
A criticism that may be levelled against the fore.going definitions of real time events, real time information systems and real time science is that they seem to
be so broad and all-encompassing as to become meaningless; little is left out. The antidote to indiscriminate
extension of real time concepts lies in the distinction
from non-real time concepts. There are two basic senses
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Fall Joint Computer Conference, 1968
in which non-real time may be construed-as an entity
in its own right, and as failure in .real time systems.
In the first sense, a non-real time information system
is one that does· not continually sense and respond to
seiected changes in the object envir~nment in a manner
permitting control over events at the time they occur.
Analyses of past events and planning for future events
fall into the non-real time category. In computer systems, hatch processing is generally conducted in nonreal time, and abstract simulations are typically nonreal time operations.
The results of analyses of the past, of planning for
possible futures, of batch information processing and of
non-real time simulations may eventually be applied to
a real time systems context, and as such, non-real time
behavior may be interpreted as preparatory to real time
behavior. Non-real time behavior may even have its
own characteristic real time pace (as in accelerated real
time simulation), but, insofar as inunediate control is
not exerted over ongoing events, such behavior is interpreted as non-real time for concurrent events. From a
practical point of view, the heart of the distinction between non-real time and real time is the distinction between knowledge disembodied from immediate and concurrent action versus knowledge expressed in action.
The second sense of non-real time is failure of a real
time system to meet some specified standard of performance in controlling the system environment. Thus, in
computerized real time systems, if SAGE does not
destroy a hostile bomber before it reaches its target, if
the Apollo spacecraft is not being picked up by the
ground tracking system, if SABRE airline reservations
are swamped with erroneous manual inputs, if the executive program of a time-sharing system has to handle
too many users at one time, to that extent the real time
information system deteriorates in performance and regresses to a non-responsive or non-real time mode of
operations.
Turning now to the last stage, the social elements of a
public philosophy of real time information systems, we are
primarily concerned with social effectiveness. If the object of real time systems is to regulate selected ongoing
events in the system environment, and if the object of
real time science is to extend human mastery over real
world events, then the aggregated effectiveness of such
efforts is real time social effectiveness.
.
But just what does social effectiveness mean when
applied to real time information systems? It was mentioned earlier that real time systems probably represent
the most advanced technical means available for regulation and control of social change, and that information power, in a democracy, ultimately resides in the
public. Social change via real time information systems
is thus self-change. The·public, ideally, authorizes and
warrants social change. Each individual is thus both
experimenter and subject in the development of real
time public systems; a new level of participant democracy is needed· well beyond anything that has been
attempted so far. A socially effective public philosophy
correspondingly requires educational changes in the
general population that can lead to enhanced participant
democracy. The alternative is the eclipse of the public
by a new technological meritocracy.
The way out of the dilemma of overconcentration of
information power in some new elite is modification of
existing democratic procedures with the aid of new
technological capability. Pluralistic checks and balances between competing groups and interests, conducted in the open forum, is a time-honored method for
preserving a dynamic democratic equilibrium. The design of pluralistic checks and balances for diverse real
time information systems and public information services would be pouring new real time wine into old democratic bottles. The new real time information services can be applied to enable the public to exert closer
scrutiny over elected officials by more frequent voting,
and more frequent expression of public opinion by
electronic polling on key issues as they arise. ~he electronic potential for public control is so great that we
should also be concerned with overcontrol of public
officials by a fickle and changeable public, overcontrol
that could lead to a more virulent form of the tyranny of
the majority (as Alexis de Tocqueville1 described it
more than a century ago). The knife cuts both waysmore power means more work and greater responsibility
for the public and its representatives to maintain equitable equilibrium between shifting majorities and diverse
minorities.
The foregoing should make it obvious that the determination of suitable checks and balances between
competing groups, competing real time information systems, between the public and various elites, between
majorities and minorities, will require a long and continuing course of social experimentation. Doctrinaire
solutions are no match for systematic social experiment
and verified empirical demonstration. An essential
requirement of a public philosophy, then, is the institutionalization of social experiment in public affairs
with a corresponding internalization of experimental
values in thought and outlook.
Summing up, what are the key elements of a public
philosophy for real time information systems? The
philosophy requires an outlook that links knowledge
with action; it needs the support of eclectic real time
sciences concerned with the extension of human mastery over real world events; it is characterized by diverse democratic means to achieve pluralistic social
ends; and it requires an extension of .experimental
Public Philosophy for Real Time Information Systems
method and experimental ethos to social affairs. Do we
have a philosophy that brings these elements together,
or do we have to invent fl. new philosophy for the era of
real time systems in computer-serviced societies?
The promise of American pragmatism
The thesis put forth in this final section is that we do
have the fundamental elements for a public philosophy
of real time information systems in the legacy of American pragmatism. The following discussion develops the
grounds for this position in four steps: a brief description of the historical development of American pragmatism; pragmatism as a philosophical system founded
upon and profoundly influenced by real time concepts
and a real time outlook; pragmatism as a coherent experimental approach to the democratization of real time
social control; and the'extension of pragmatism into systems science and the era of computer-serviced societies.
The recurrent theme throughout the rest of this paper
is that we already have the basic elements of a philosophy of real time in American pragmatism, constructed over almost a century of hotly contested philosophical labor, as represented by its principal originators, Charles Peirce,2 William James3 ,4 and John
DeweY,1i and their successors. These three founders
portray the three faces of pragmatism-Peirce the
mathematical and scientific side, James the psychological side, and Dewey the social side.
"Pragmatism" is derived from a Greek root signifying
action. According to James (1907),3 pragmatism was
first introduced into philosophy by Peirce in 1878. For
Peirce, the meaning and value of a statement consisted
of its conceivable consequences in practice, of its bearing on deliberate human control over future events.
Peirce clearly envisaged the union of knowledge with
action.
.
At the heart of Peirce's belief was his conviction of
the superiority of experimental method over other
methods for gaining and implementing useful human
knowledge. The "truth" of statements is operationally
determined by empirical verification of testable Consequences achieved by iterative experimental inquiry, as
it occurs in scientific progress. Peirce was the first to
use the concept of inquiry in this context, a term later
adopted and elaborated by Dewey. With Peirce, meaning, truth, and experimental inquiry were cast in a temporal frame, contingent upon and responsive to the
cumulative consequences of ongoing human action. The
long-range, evolutionary advance of science served as
the idealized model for Peirce's vision of pragmatism
which contained the seeds for a philosophy of real time
science.
James was the popularizer of pragmatism and its
most eloquent, almost poetic, spokesman. While
1495
agreeing with Peirce that the validity of statements is
to be continually tested by their consequences, James
broaden~d the domain of pragmatic meaning over the
whole of human experience. His earlier preoccupation
with the shifting stream of consciousness was expanded
into an all-encompassing concept of experience(which
he described as radical empiricism) that incorporated
subject and object as an undifferentiated unity, a unity
consonant with that described by Bertrand Russell
(1945)6 as "neutral monism." For James, the temporally conditioned stream of experience, flowing in a "pluriverse," displayed the same strung-along, partially
connected, mosaic character as his stream of consciousness. This strung-along pluriverse was contrasted
by James against the "block universe" espoused by
idealists of all callings who believed in the Platonic tradition of a fixed, 'antecedent structure of the universe
laid out in some grand, sweeping design. J ames' philosophical pluralism, more than that of other pragmatists, lays the groundwork for a virtually unlimited
multiplicity of real time sciences and intersciences
modeled after the kaleidoscopic configurations of real
time systems.
Dewey was deeply concerned with the accelerating
tempo of scientific and technological advance and the
need for continual social reconstruction to keep pacewith
such changes. He seized upon the element of human
control in experimental method, developed previously
by Peirce, as the method of choice to implement and
guide social reconstruction.
In a remarkable anticipation of systems science,
Dewey attacked the efficacy of conventianal notions of
true and false and urged, in their place, the adoption
of operational measures of effectiveness for human, organizational, and social performance. Social behavior
isnot true or false-it exists, for better or worse-and our
concern, according to Dewey, is to find out how effective it is, and to do it ina manner that wil1 permit us to
improve upon it to meet new conditions.
For Dewey, every existence is an event, and all
events are potential experiments. Contrary to the prevailing laboratory view of science, Dewey saw the universal prospects of real world experimentation with real
time events in his doctrine of experimentalism-'-the
extension of experimental method to human affairs.
Dewey effectively anticipated a philosophy of real time
science by urging increased human control over social
events through scientific method.
Dewey's concept of increasing experimental control
over social affairs was consistently qualified as democratic control by' an enlightened public. In The Public
and Its Problems (1927)7 Dewey put forth his prophetic vision of free social communication and democratized public control in a new machine age:
1496
Fall Joint Computer Conference, 1968
"We have but touched lightly and in passing upon
the conditions that must be fulfilled if the Great
Society is to become a Great Community; a society in
which the ever-expanding and intricately ramifying
consequences of associated activities shall be known in
the full sense of that word, so that an organized, articulate Public comes into being. The highest and most
difficult kind of inquiry and a subtle, delicate, vivid and
responsive art of communication must take possession
of the physical machinery of transmission and circulation and breathe life into it. When the machine age has
thus perfected its machinery it will be a means of life
and not its despotic master. Democracy will come into
its own, for democracy is a name of free and enriching
communion. It had its seer in Walt Whitman. It will
have its consummation when free social inquiry is indissolubly wedded to the art of full and moving communication. "
The above sketch is only crudely indicative of the
philosophies of Peirce, James, and Dewey. It is beyond
the scope of this paper to set out the distinguishing
characteristics and the current diversity of American
pragmatism in any detail. But these brief remarks
should suffice to point up the pronounced temporal
thrust of American pragmatism, the continual reconstruction of present belief toward future behavior, with
vigilant appraisal of fresh consequences leading to .new
guidelines for further action. Peirce stressed the selfcorrective aspect of the inquiring process; James focused on the human implications of the pluralistic
stream of experience; Dewey emphasized instrumental
means and experimental control over growingsocialproblems in a precarious world. The flux and pressure of
real time events is written large in these philosophies,
and social mastery over this flux is most apparent and
most comprehensively expounded in Dewey's work.
Social control has become a terrifying notion when
coupled with computers. It conjures up visions of
Orwell's8 Big Brother and Wiener's9 Golem. Dewey was
always. a great believer in democracy even though he
was acutely aware of its many limitations as he saw them
in his time. He also had an abiding faith in the public.
He felt that if, in some manner, available social knowledge could be made freely accessible to the public, that
the effective intelligence of the public would be released, and the excellence of democracy would be
enhanced. Is the imminent emergence of the public information utility the instrumentality through which
Dewey's dream can be realized? If we design the computer utility to gather and distribute public information
on an equitable basis to all, and if we integrate this
utility with new, experimentally evolved democratic
procedures that will enable the public to use this information wisely, then, to that extent, democracy stands
to be the beneficiary of the new concentration of information power, not its victim.
The development of such new democratic procedures
would involve experimentation with prototype computer utilities to test alternative methods of man-computer communication in the management of social information. Results of such tests could be made widely
available, openly discussed and debated, and incorporated into improved versions by public approval or
through authorized agencies appointed and monitored
by the public.
The concept of deliberate, institutionalized, continuing public experiment for public affairs is a new evolutionary force in democratic advance, a challenge that
requires new attitudes and revised values. Each individual will have to learn to think of himself as both subject and experimenter, with lifelong responsibility for
selecting and implementing new experiments, evaluating social effectiveness, and applying the results. The
realization of this new experimental ethos will require
far greater participation and public evaluation of social
feedback than has ever occurred "before in any democracy, including the personalized democracy of the citystates of ancient Greece. The information utility,
linked to the public real time information base, could
conceivably provide the leading instrumentality for the
public to scan the social scene, identify problems, contribute to social control, and provide continuing corrective feedback on the interplay of plur~listic social
experimentation.
The new experimental ethos will also require an infrastructure" of continuing, lifelong education in real
time, the acquisition of new knowledge when it is
needed, in time to meet problems as they arise. When
education occurs in real time, it is responsively adaptive
and education becomes indistinguishable from on-thespot human problem-solving. Real time education will
then articulate with the tumultuous flow of social experience, and education will become an integral part of
such experience. The dusty dogma of the academic
creed may become a relic of the past.
There are those who argue that experimental method
is good, true and beautiful, but only as long as it remains
in the domain of natural science where it originated,
and where, they claim, it belongs. As soon as experimental method is taken out of conventional scientific
pursuits and is indiscriminateiy placed into such fields
as democracy and education, into social affairs, then,
these critics cl3.im, you enter the never-never land of
human values and transcendental metaphysics where
statements become meaningless from a scientific point
of view. Such is the position, for example, of the logical
positivist and most behaviorists.
The pragmatist rejects this view since it would keep
Public Philosophy for Real Time Information Systems
scientific method confined within the scientific priesthood and deny it to the public. Experimental method is
the most precious legacy of scientific endeavor, and it
is too important and too valuable to entrust it to any
aristocracy, scientific or otherwise. The crux of the pragmatic position is that values may be formulated as
hypotheses, operationally defined, quantitatively measured, and empirically tested with results subject to
further test and evaluation as in any other scientific
activity. If values are treated as hypotheses, then
democracy and education, social attitudes and social
change, when they are operationally defined under empirically verifiable conditions, are correspondingly
amenable to social experiment.
The early pragmatists were in a difficult position in
defending their stand on the possibility and validity of
social experimentation because the means for the universalization of experimental method were not at hand
and they could not point to concrete, real-world social
experiments. They could defend their position in principle but not in practice-a vulnerable position for one
who calls himself a pragmatist. But now conditions have
changed dramatically, particularly with the advent of
systems science and the proliferation of the high-speed
electronic computer. Social experiment is now possible
on a scale undreamed of by the early pragmatists.
It is commonplace to point out that computers make
it possible to collect, organize, and process vast amounts
of data quickly and reliably in real time experiments
that were beyond the ken of the precomputer era. The
computeris, in fact, revolutionizing experimental method
in the physical, biological and social sciences, and the end
is nowhere in sight. Systematic experimental method
is comparatively recent' in human history, dating back
only to the Western Renaissance (Sarton, 1948).10 It
has changed rapidly since its inception and has received an electronic jolt with the emergence of the
general-purpose digital computer since World War II.
Social experiments are now possible in a bewildering
variety of forms, for a growing number of variables,
with real time collection, reduction and analysis of
social data. For many, perhaps most, the question is no
longer whether to experiment on a sodal scale, but how
to experiment in the best interests of the public.
The power of systems science in catalyzing and accelerating the extension of experimental method is probably not as well understood as the more obvious impact of computers. The concrete, tangible system, with
its specified stages of definition, design, production, installation and operation, with test and evaluation occurring at all stages, is the organizational vehicle for the
breakthrough into real-world experimentation. If a
coherent social activity is organized into a formal systems framework, then the system serves both as sub-
1497
ject and object of its own evolutionary series of system
experiments, for continuing system test and evaluation.
The integrated system is the crucible in which the realworld experiment is forged.
The combination of computers and system science, in
a concrete system context, makes possible the universalization of experimental method in an unprecedented
manner. The computer complex can and has served as a
built-in laboratory for test and evaluation of system
performance. This has occurred most notably and dramatically in the earliest large-scale real time systems, in
SAGE air defense and in Merc~ry-Gemini-Apollo
manned spaceflight. In each mise there was an attempt
to make a great leap forward into new knowledge and
new control over uncharted domains. The only way to
achieve system goals within planned timetables was to
experiment rapidly and boldly with new techniques and
new findings.
The system configuration served as its own test bed in
measuring and assessing system performance. Simulation, training, testing and evaluation were indistinguishably intennixed in system development in a new
experimental style-in computer-aided, interdisciplinary, mission-oriented, self-experimentation in real
time, under common schedules and common system
goals. With the advent of other and newer real time information systems in industry, science, education, medicine, and now ,on th~ threshold of computer utilities,
the experimental dance is improvised on new real time
tempos.
To the extent that a systems approach is deliberately
integrated into social organization, and to the extent
that such syste:ms are computerized, to that extent will
potential experimental power grow for real-world social
experiment. Saying that experimentation is good and
noble is not enough, there must be the means and the
explicit social configuration-the real time systems configuration-to make such experimentation feasible. The
first step, then, in the evolution of real-world social
experiment is the evolution from non-real time to real
time systems. And the more advanced the computerization of such real time systems, the more potent are the
possibilities for ongoing systems experimentation.
Social experiment will spread as real time information
systems spread and proliferate into interlocking networks, ultimately into ecological complexes of openly
cooperative and competitive real time information
systems.
The form that real time social control will take will depend on how real time information systems are implemented. If competitive social experiments are freely conducted in open forum, if many alternatives are explored,
if real, not rigged choices are open to the public, if grassroots participation and feedbaek is built into the genes
1498
Fall Joint Computer Conference, 1968
and chromosomes of object systems at the system design stage, if adequate checks and balances are devised
between the publi~, the managers, the operators, and
users of such systems, if these and related conditions
are met, then real time social· control may effectively
turn out to be of the people, by the people, and for the
people, rather than for the old plutocracy or a new tech'
nological elite.
When pragmatism was thrust with a "barbaric
yawp" into the world of philosophy, mainly through the
efforts of William James, a hue and cry arose from many
quarters on the crassness and narrowness of this new
outgrowth of American materialism. Pragmatism was
maligned as opportunistic, self-indulgent, unscientific,
anarchistic, and as an ideal comedian's philosophy. The
semantic storm over the pragmatic as the narrowly practical was overwhelming; repeated onslaughts from the
ideal, the good, true, and beautiful, from the pure and
theoretical were launched against this newborn philosophy from all sides.
Peirce, disagreeing with James' exposition of pragmatism, insisted that his theory be called pragmaticism.
James turned to the more technical concept of radical
empiricism to ward off the semantic pitfalls of pragmatism. Dewey lingered longest over pragmatism, and
somewhat reluctantly turned to instrumentalism and
experimentalism to defuse the relentless onslaught from
critics.
But the temper of the times has changed and the
horrendous connotations of pragm'atism have become
more respectable in a world that desperately needs intelligent, practical solutions to mounting problems.
While pragmaticism, radical empiricism, and instrumentalism remain as distinctive historical halhnarks of
their creators, American pragmatism persists as the designation of their common origin, continued growth,
and diversification in contemporary affairs. After being
drummed out of court for challenging the established,
absolutistic order, American pragmatism is, experiencing a renaissance.
With the emergence of real time information systems,
the pragmatic temper of American science and technology has received a fresh impetus and powerful new
thrust. Peirce's "knowledge of consequences" has become transmuted into the principle of real time feedback; James' "cash-value" has become mission payload
and system payoff; Dcw~y's social inquiry and behavioral effectiveness has evolved into system and costbenefit analyses; the early pragmatic focus on the regulation of future consequences has been transformed into
human real time control. The philosophy of pragma-
tism has evolved into the philosophy of real time.
The intent of this. essay has been suggestive and
exploratory. It has suggested the power of the real time
concept in contemporary social change and it has explored its-links with the tradition of American pragmatism. The meaning and import of real time information
systems has not yet been pursued and systematized by
philosophers. The scope and diversity of pragmatism
and competing philosophies has only been hinted at in
these pages. Controversies and logical problems in the
construction of a public philosophy of real time information systems have been bypassed or have been mentioned
only in passing, and those that have been aadressed
have not been dealt with in detail. Some of these problems are treated elsewhere at greater length by the
author (1967).11 If this discussion has served to point up
the vital need for a public philosophy of real time information systems, and if it has shed some light on the formulation of the problem and on key issues, then its purpose has been met.
REFERENCES
1 A TOCQUEVILLE
Democracy in America 1835
2 CSPEIRCE
Collected papers of Charles Sanders Pierce
Charles Hartshorne and Paul Weiss (eds) The Belknap Press
of Harvard University Press Cambridge Massachusetts 1935
3 W JAMES
Pragmatism A new name for some old ways of thinking
Longmans Green & Company New York 1907
4 WJAMES
A pluralistic universe
Longmans Green & Company New York 1909
5 JDEWEY
Intelligence in the modern world
J Ratner (ed) Random House New York 1939
6 BRUSSELL
A history of western philosophY
Simon & Schuster New York 1945
7 JDEWEY
The public and its problems
Henry Holt New York 1927
8 GORWELL
1981,.
Harcourt Brace New York 1949
9 NWIENER
God and Golem Inc
MIT Press Cambridge Massachusetts 1964
10 CSARTON
The life 0/ science
Indiana University Press Bloomington 1948
11 HSACKMAN
Computers system science and evolving society
Wiley & Sons New York 1967
A special interest session on computer design
automation
Computer design automation: What now and what next?
by JEROME M. KURTZBERG, Chairman
IBM Watson Research Center
Yorktown Heights, New York
This special interest session of computer design automation explores the current problems that face us, what
we can do and are accomplishing, and what appears to
be our objectives and possibilities in the future.
Historically, the design tasks that were first automated were those with the largest savings, in terms of
cost and time, and ease of mechanization. Thus, manufacturers initially automated the clerical checking and
documentation functions involved in computer design.
When done manually these tasks consume a major portion of design time and are particularly onerous for humans. Concurrently, the task of establishing pin-to-pin
interconnection chains for backplane wire routing was
mechanized, at first for manual wiring, and later for input to automatic wire-wrap machines.
Success in these areas encouraged manufacturers to
try to automate more of the tasks involved in the physical design area using as input the logic equations or diagrams. This called for development of algorithms to
handle the interrelated problems of partitioning and
assignment of logic equations to circuits on modules
(card-packaging), placement of the modules in a backplane, and determination of pin illterconnection and
wire routing patterns. Although these tasks are interrelated, it was considered necessary, because of their
complexity, to treat them separately. Furthermore, the
exact definitions of these physical design tasks are
strongly dependent upon the particular circuitry employed, so as to encompass an entire class of problems.
Today, a number of the major manufacturers have
developed a set of techniques to handle these problems.
Attention also turned to the automatic generation of
logic equations from the register information flow for
the various computer operations. Gorman and Andersonl in a paper given at the 1962 F JCC demonstrated
that the production of logic equations can be treated as
1499
a formal translation process in the manner of compiler
construction.
The problem of logic equation simplification has been
addressed and extensively treated from the theoretical
viewpoint.2 The same has been true for techniques for
detection of single faults in combinationallogic.2 Also,
there are many production problems in the manufacturing interface area that have received considerable attention such as automatic testing of hardware.
Today, the problems in design automation are more
difficult than in the past because of the increasingly
complex demands imposed on the computer design process. These demands arise from the trend toward more
sophisticated computer organizations and the numerous
and interrelated constraints occurring in the new technologies. These problems are discussed by the panelists
with audience participation after the speakers explore
specific areas of interest.
Gorman deals wi,th the areas of functional computer
design and evaluation of the design. He treats the problems of securing an adequate language for expressing
the system specification, the problems of "design translation" and subsequent evaluation of the resulting detailed design. Next, Russo discusses the interface
between logic and hardware. The problems posed by
tlie LSIt echnology are examined. Donath then elaborates on some of the problems in the physical design
area. He stresses the need for certain analytic studies in
order to gain a better understanding of the algorithms
necessary to handle the network design tasks. Breuer
speaks last on the problems in the automatic generation
of component failure detection and diagnostic test sequences. The various approaches that have been used
and their limitations are discussed along with the effect
of hardware fault detection in the actual design of
equipment.
1500
Fall Joint Computer Conference, 1968
The interested reader is referred to a survey paper by
Breuer2 for a comprehensive bibliography of previous
work in computer design automation.
REFERENCES
1 D F GORMAN J P ANDERSON
A logic design translator
1962 Proc FJCC pp 86-96
2 MABREUER
General survey of design automation of digital computer
Proc IEEE Vol 54 No 12 December 1966 pp 1708-1821
PANELISTS
Donald F. Gorman
RCA
Cherry Hill, New Jersey
RoyL. Russo
IBM Watson Research Center
Yorktown Heights, N ew York
Wilm E. Donath
IBM Watson Research Center
Yorktown Heights, N ew York
Melvin A. Breuer
University of Southern California
Los Angeles, California
used to convert from one level of design to another. It
treats design as the translation of a description of a
product from one language to another.
The conversion from a marketing specification to a
functional design is, at the present time, not a well-defined process and, therefore, not amenable to automation. Although translation from a functional design to a
logic design has been shown to be feasible (1962) the
development of these techniques has not progressed
very rapidly, due to an apparent lack of interest. N evertheless, several such systems are currently being implemented; emphasis is on achieving a practical automation system that will produce practical designs.
The evaluation of information processing systems,
including both hardware and software, has proven to be
quite intractable. The method of evaluation most widely used today is simulation; however, its use is limited
and hardly qualifies as automation. Current work
on simulation centers on the development of the concepts required to model such a complex product as
an information processing system and the development
of simulation languages to embody these concepts and
make them easy to use.
Whatnext'l
Functional design and evaluation
by DONALD F. GO R~VIAN
Radio Corporation of A. merica
Cherry Hill, New Jersey
The design of information processing systems consists of the development of (1) the initial marketing
specifications, (2) a functional design to meet these
specifications including a detailed logic design to
achieve these functions, and (3) an implementation of
this logic design, in either hardware or stored microprogram, using the latest technology.
Functional design encompasses all activities involved
in producing the functional design from the behavioral
specifications and the conversion of this design into a
logic design.
Evaluation of a design is the process of determining if
the functional design, the logic design, and the implementation satisfy the initial behavioral specifications.
Whatnow'l
What techniques are currently available for aiding in
the design and evaluation tasks? To assist in the design
of systems, a technique called "design translation" is
Some areas in which progress must be made in order
to bring the present efforts to fruition will now be
considered.
Provided that a fixed control philosophy is assumed,·
design translation techniques can be applied to a functional design to produce a logic design. However, in
order to optimize a design, it must be possible to merge
several control methods, such as synchronous, asynchronous' a centralized clock, distributed control, etc.,
into a single design. Techniques must be developed to
determine the control method best suited for each portion of the design, and translation techniques are needed
to produce a single coordinated design utilizing several
different control philosophies.
Design translation techniques will provide, for the
first time, sufficient detailed information about alternate designs that tradeoff studies may be effectively
undertaken with respect to hardware vs. software, synchronous vs. asynchronous, etc. When criteria to be
used in these tradeoffs havebeen established, the tradeoffs themselves may be incorporated into the translation procedure and designs may then be optimized over
a wider range of criteria.
Translation from a behavioral specification to a
functional design is the truly creative part of the design
activity and is currently considered to be an art rather
than a science. Design experience using translation techniques and the ability, via automation, to analyze
Special Interest Session on Computer Design Automation
numerous designs will eventually lead to a methodology
for automating aspects of this phase of design.
Evaluation of information processing systems encounters even more problems than design. One of the
fundamental problems today is that there is general
disagreement over what constitutes a "good" design.
Assuming that satisfactory criteria can be found, techniques for rapidly evaluating systems with respect to
these criteria are needed.
Analytic procedures are currently being developed,
but are, as yet, far from being general enough for adaptation to automation.
Simulation, which is the only evaluation technique
available today, suffers from a severe handicap-inefficiency-in both the writing and running of simulation
programs. Efficiency will be achieved and simulation
will become a practical design aid through the following
steps: (1) the use of simulation program generators that
will facilitate the creation of customized simulation programs, (2) the generation of simulation models that
allow a detailed view of the area of immediate interest
to be combined with a very general view of other portions of the system, and (3) the generation of integrated
simulation programs based on such models.
Summary
Design automation, which was first used in the manufacturing and physical engineering areas, has made
considerable progress in logical design and is now making inroads into functional design, previously considered
to be an entirely creative process. The use of simulation
and design translation is the first step in transforming
the functional design of both the hardware and the
software of information processing systems from an art
to a science.
The logic-to-hardware interface area of design
automation
by ROY L. RUSSO
I BM Watson Research Center
Yorktown Heights, New York
The logic-to-hardware interface area is concerned
with the problems of translating a logic description into a
high level physical description. The logic description is
an interconnection of the primitive circuits, such as
And's, Or's, Nor's, Flip-Flops, etc., that are to be used
in the physical packages. A high level physical descrip-
1501
tion takes into account 7 for example, partitioning of
the logic into physical packages, but does not include
relative placement of the primitive circuits within a
package, or pin assignment, wire routing, etc.
This interface area is extremely important at the present time for two basic reasons. First, the present integrated circuit technology imposes critical and interrelated constraints which must be satisfied during this
phase of the design process if the technology is to beused
effectively. These constraints include minimizing the
number of integrated circuit chips or chip types to reduce cost and specifying chips that can be tested adequately and economically. Second, decisions made in
specifying the high level physical description determine
to a great extent, whether or not severe machine design
goals, such as fast cycle times, will be met.
The problems that design automation programs must
help solve for the logic-to hardware interface area are
best categorized by the class of machine being designed:
either a small low-performance one or a large, high-performance machine.
In the small machine category, chip type minimization and machine cycle time constraints can be set
aside to make the problem more amenable to attack and
the cost of the computer programs more reasonable.
Since manufacturing costs will depend almost directly
upon the number of unique chips in the machine, the
major problem in this case will be to partition so as to
reduce that number. The relatively small number of
terminals on a chip compared to the large number of
circuits on the chip makes this partitioning extremely
difficult. It also increases the number of tests which
must be applied to the chip and this raises the cost of
testing. Hence, the effect of the implementation on
testing must also be considered at this level. If the
packaging hierarchy consists of logic on chips, chips on
carriers, etc., then the problems become more difficult
and the techniques must be extended.
The problems increase enormously for large, high-performance machines because the number of constraints
and their complexity increase sharply. In particular,
chip type minimization and proposed machine cycle
time constraints must be considered. (The low volume
of machines implies that the same chip type will have to
be used repeatedly in the machine to reduce costs.)
Whereas in. the small machine case, "the specific placement of chips in the packaging hierarchy was not important, it must now be considered because of its effect
on the cycle time. Hence, for this class of machines,
there are problems of partitioning logic to chips in such
away as to minimize chip types, and of placing the individual chips in the packaging hierachy in such a way
as to satisfy a proposed short cycle time with its implied
constraints.
1502
Fall Joint Computer Conference, 1968
At the present time, it is only by examining hardware
packaging alternatives that designers will be able to obtain a high level physical description that best satisfies
or compromises among the many constraints. Trying
alternatives depends upon three elements. First, the designer must decide on the alternative he wants to try.
Second, a means must be available to implement the
alternative rapidly and economically. Third, the designer
must examine the effect of the implementation and decide what he wants to do next. Design automation programs provide a rapid and economical means for trying
a sufficient number of alternatives with appropriate
output information to the designer.
We in design automation have been for a long time
using the computer as a sort of "passive" partner in the
design process.· We've been using it to keep files, to do
checking and to interface with manufacturing. In so
doing we have lost sight of the 'real problem of design,
that of evaluating alternatives, and of the real potential
of the computer, to be an "active" partner in the design
process by helping the designer to make his design
decisions. The logic-to-hardware interface area offers
the potential of allowing the art of design automation to
advance to this new level.
Hardware implementation
by W. E. DONATH
IBM Watson 'Research Center
Yorktown Heights, New. York.
The area of hardware implementation shall be (some:what arbitrarily) defined to include placement, wire
routing, terminal assignment, and the interface to
hardware fabrication devices. At this stage, many companies have automated at least some of these steps. In
the first three areas, we encounter problems which must
be solved by analysis into sub-problems and by developmentofalgorithms;inthe last area, we are faced with the
problem of developing a convenient means of manmachine communication. LSI Mask Design, 1 for which
various systems were developed over the last few years,
falls into the latter area.
In the first three areas, one may have to solve problems related to placement and wiring rules. However,
at this stage it is most important to note that few, if
any, DA programs can generate as good a design as a
good engineer could. They need either human intervention or much more interconnection space than is really
necessary. This is proportionately more serious now
since the ratio of interconnection cost to circuit cost is
increasing with the new technologies.
Two lines of investigation suggest themselves. For
one, we need to develop a better understanding of the
capabilities of heuristic alogrithms. This implies mathematical analysis and systematic studies. However,DA
problems are much too complex to yield to such analysis
or studies. It seems best to abstract out of the general
range of DA problems mathematical problems that contain the essential difficulties of the DA problems. At
that point mathematical analysis and systematic
studies become feasible. 2
A second area of investigation arises from the structure inherent in computer logic complexes. E. F. Rent,
in an unpublished work in 1960, stated that for a manual
partition of large logic complexes into subcomplexes of
c circuits, the terminal count is given by Acp , where
p=2/3 and A is a constant. Understanding' of the
phenomenon might well lead to methods for taking
advantage of such structure in DA programs. Furthermore, we can feel surer of our mathematical analysis if
our model of logic structure is as close to reality as possible.
In conclusion, I feel that a necessary step toward better DA methods is the systematic investigation of the
mathematical problems basic to Design Automation
procedures where both analytic and experimental procedures are employed.
REFERENCES
1 PWCOOK
NNE MAN
WEDONATH
GALAMKE AEBRE-
A utomatic network generation for large scale inteqration
IEEE of Solid State Circuits SC 2 No 4 pp 190-196 Dec 1967
2 WE DONATH
JSIAM 16 pp 439-4571968
Hardware fault detection
by M. A. BREUER
University of Southern California
Los Angeles, California
One of the most pressing problems currently confronting the design automation specialist is that of the
automatic generation of component failure detection.
and diagnostic test sequences. This problem is made
more difficult due to the new LSI circuits where we may
Special Interest Session on Computer Design Automation
have hundreds of components on a chip with only a few
accessible input/output terminals.
These chips contain both combinational and sequential logic which must be tested. It is now feasible to
generate tests for combinational logic. 1 ,2 However, a
computationally feasible solution for the general class of
sequential circuits is still not known. The trend may be
to only carry out a partial test and specify that a chip
is component failure free with probability p. Most computer companies are currently investigating this problem, and some encouraging results have been reported. 3
There are a number of interesting approaches dealing
with generating test sequences. One technique, called
the behavioral approach,4,5 is based purely on the abstract next state and output functions defining the sequential machine M to be tested. Given a black box containing a machine M', this approach tries to answer the
question of whether or not M' is equivalent to M. This
approach leads to very long testing sequences, and is
only practical for extremely small sequential circuits.
One reason these sequences are so very long is that this
procedure is actually doing machine identification
rather than simply fault detection.
A second approach to this problem of generating test.
sequences is to take into consideration the actual physical implementation of M, where one obtains the machine Mjfrom M by considering how M operates under
the jth component failure. a,6 This procedure leads to
shorter test sequences, and appears to be the most
promising approach presently available.
Most approaches make many assumptions on the
type and number of faults which can occur. For example, usually only one fault is considered at a time,
and the number of states in the machine remains the
same. Fortunately, the resulting checking sequences are
usually still effective even if these assumptions do not
hold. Unfortunately, the stuck-at-zero and stuck-at-one
static fault model most commonly used is not always
sufficient to test a machine, since it neglects time
delay and interconnection shorts. The specification of
an adequate fault model for an LSI circuit chip is still an
open question.
One assumption which is usually not valid is that one
has available the state transition table for the machine.
For any reasonable size circuit, this table is much too
large to either generate or store. In practice all one actually has available is the set of equations or diagrams
specifying the logk of the machine.
A special case of the fault detecting problem isthatassociated with cascaded machine structures. 7 A simple
example of such a structure is an n bit accumulator,
1503
which should be considered as n identical 4 state machines rather than as one 2an state machine. Efficient
procedures for testing such structures are not known except for some specific cases.
Finally, one can take a probabilistic approach to the
problem of generating a good checking sequence. That
is, for a fixed value C, how would one construct a
checking sequence of length C which will maximize the
probability of detecting a fault, should a fault be present.
Fault diagnosability deals with specifying, down to
the component or circuit level, what fault has occurred.
Usually, a fault detection test gives some information
on what fault is present. lVlore detailed information can
be obtained by increasing the length of the test sequence
and by a judicious sequencing of the test cases. Usually,
the computer user is only interested in locating a fault
down to the level of a replaceable unit.
In summary, there are many problems still unsolved
in the area of completely automating the generation of
fault detecting experiments. It is important that these
problems be solved so that our new technological advances can be utilized to their fullest potential. The solution to this problem could be made somewhat easier if
the concept of fault detection was added as a new
criteria in the design of circuits.
REFERENCES
1 JPROTH
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research aud Development 278-2911966
2 D B ARMSTRONG
On finding a nearly minimal set of fault detection tests for combinational logic nets
IEEE Trans on Electronic Computers vol EC-15 no 1 66-73
1966
3 E RJONES C H MAYS
A utomatic test generation methods for large scale integrated logic
IEEE J Solid-State Circuits vol SC-2 221-2261967
4 FCHENNIE
Fault detecting experiments for sequential circuits
IEEE-Switching Circuit Theory and Logical Design 5th Annual Symposium-Special Pub15-164 95-110 1964
5 ZKOHAVI PLAVALLE
Design of sequential machines with fault-detecting capabilities
IEEE Trans. on Electronic Computers vol EC-16 no 4 473-485
1967
6 S SESHU D N FREEMAN
The diagnosis of asynchronous sequential switching systems
IEEE Trans on Electronic Computer vol EC-11 457-465 1962
7 MABREUER
Fault detection in a linear cascade of identical sequential machines
Proceedings 9th Annual Switching and Automata Theory
Symposium 1968
1968 FALL JOINT COMPUTER CONFERENCE COMMITIEE
Chairman
Miss Bernice Doebler
Hewlett-Packard Company
Dr. William H. Davidow
Palo Alto Division
Hewlett-Packard Company
Vice Chairmen
Thomas R. Dines-Administrative
NASA
Ames Research Center
Mrs. Janet Shane
Bechtel Corporation
MissJan Swanson
IBM Corporation
Mrs. Jackie Wheeler
Local Arrangements
Donn B. Parker-Technical
Control Data Corporation
Conference
Ralph R. Wheeler-Chairman
Lockheed Missiles & Space Co.
Adm~nistrator
Albert C. Porter
California 'Public Utilities Commission.
Education Pr()gram
R. J. Andrews-Chairman
IBM Corporation
N. O. Salberg-Vice Chairman
IBM Corporation
R. C. Haseltine
R.C.A.
Instructional Systems
Exhibits
Thomas C. Bieg-Chairman
IBM Corporation
J effery Stein-Vice Chairman
Greyhound Computer Center
Ray Telford McLaury, Jr.
Crocker Citizens Bank
Ladies Program
Norm E. Pobanz-Vice Chairman
Electronic Associates, Inc.
Joe Brashear
Control Data Corporation
Sandy Caipo
Control Data Corporation
Robert L. Colvin
Lockheed Missiles & Space Co.
Everett Eiselen
IBM Corporation
Cuthburt C. Hurd
Computer Usage Company, Inc.
Printing and Mailing
Gordon Pelton-Chairman
Mobility Systems, Inc.
James M. W eldon-Vice Chairman
Hewlett-Packard Co.
Microwave Division
Public Relations
Mrs. Nancy Thoman-Chairman
Hewlett-Packard Company
Russell H. Berg-Chairman
Hewlett-Packard Company
Mrs. Mary Ann Maloney-Vice Chairman
Computer Usage Development Corp.
George F . Caulfield-Vice Chairman
URS Systems Corporation
WilliamC. Estler-Consultant
Publications
Joseph Horner III -Chairman
Control Data Corporation
James B. Dolkas-Vice Chairman
Control Data Corporation
Donald M. Lytle
URS Systems Corporation
Atlantic Systems Center
Registration
David Katch-Chairman
Boole & Babbage, Inc.
Miss Marjorie Hill
Control Data Corporation
Paul Hodge
Memorex Corporation
Warner King
Computer Usage Development Corp.
Mrs. Maria Robertson
Compata, Inc.
Marty Silberberg
IBM Corporation
Roger Simons
IBM Corporation
Treasurer
Kent Gould-Vice Chairman
Boole & Babbage, Inc.
James L. Mueller
U.S. Geological Survey
Edward Dodge-Chairman
R.C.A.
Instructional Systems
Liaison
Science Theater
Nels Winkless-Chairman
Communications Contact, Inc.
Technical Program
Robert H. Glaser-Chairman
Compata, Inc.
Rex Rice-Vice Chairman
Fairchild Semiconductor
Professor James B. Angell
Stanford University
Robert Bond
Hewlett-Packard Company
Dr. Sidney Fernbach
University of Oalifornia
Dr. Morton M. Astrahan-AFIPS Conference Committee
IBM Corporation
Howard Bromberg-ACM
Information Management Incorporated
David R. Brown-IEEE
Stanford Research Institute
D. R. Cruzen-AFIPS Headquarters
American Federation of Information
Processing Societies
James L. Dolby-AMTCL
R&D Consultants
John E. Sherman-Simulation Councils
Lockheed Missiles & Space Co.
REVIEWERS, PANELISTS, AND SESSION CHAIRMAN
REVIEWERS
C. T. Abraham
R. L. Alonso
E. B. Altman
A. Arakawa
P. Armer
G. N. Arnovik
M. M. Astrahan
D. C. Augustin
A. Avizienis
P. R. Bagley
J. A. Baker
A. E.·BarIow
R. Barnett
A. L. Bastian
A. Batenburg
J. A. Bayless
G. S. Beckwith
G. A. Bekey
S. S. Biglione
C. D. Birkhead
H. D. Block
J. A. Bloomfield
H. E. M. Blowey
G. Boer
G. R. Bolton
H. Borko
A. M. Bradley
J. R. Brown, Jr.
R. E. Brown
L. L. Burns
P. Calingaert
E. D. Callender
A. V. Campi
·R. Carlson
R. L. Carmichael
R .. Chapman
T. E. Cheat'ham, Jr.
B. F. Cheydleur
C.Chow
W. F. Chow
A. Clark
L. J. Clingman
A. B. Clymer
R. W. Coleman
T. W. Connolly
M. Connors
R. N. Constant
A. E. Corduan
R. K. Cralle
J. F. Cunningham
D.R.Dawdy
K. Detzer
S. M. Drezner
T. J. Dylewski
1. Earnest
R. Eggelston
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P. England
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M.Fox
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C. V. Freiman
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M. Gilliland
E. Glaser
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M. Heilweil
P. J. Hermann
T. C. Hogan
G. P. Hyatt
E. L. Jacks
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T. G. Jones
T. Kallner
W. J. Karplus
N. M. Kendall
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D. C. Lincicome
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M. E. McCoy, Jr.
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. J. Murphy
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D.Nee
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~ T. Pendergast
J. S. Perry
S. R. Petrick
W. J. Plath
N. Pobanz
A. V. Pohm
D. A. Pope
A. W. Potts
R. Prather
R. J. Preiss
J. P. Pritchard, Jr.
T. P. Plyer
I. C. Pyle
K. H. Rash
L. C. Ray
S. G. Reed
F. C. Reiman
J. W. Rigney
L. Roberts
J. J. Robinson
A. E.Rogers
J. Roseman
C. Rosen
M. Rosenberg.
S. Rosenthal
J. D. Sable
E. Salbu
G. Salton
J. L. Sandborn
W.B. Saner
F. J. Sansom
L. Sashkin
H. N. Sassenfeld
E. S~vas
J. D. Schmidt
A. J. Schnieder
E. Schubert
S. T. Sedelow
T. K. Seehuus
D. Shansky
W. Sharpe
G. T. Shuster
A. Shaw
R. Silve-r
L. C. Silvern
Q. W. Simkins
R. F. Simmons
T. A. Smay
B. L. Smith
L. Smith
P.C. Smith
R. V. Smith
S. Smith
W. R. Smith
E. W. Snyder
C. Spitzer
W. C. Spring
H. H. Steenbergen
K. Stevens
A. J. Stone
J. C. Strauss
W. A. Sturn
R. K. Summit
I.· Sutherland
R. I. Tanaka
A. S. Tauber
W. P. Timlake
F. M. Tonge
D. Toombs
L. Travis
D. Truitt
G. Tyson
R. L. VanHorn
H. R. Van Zueren
E. G. Vesely
R. Vichnevetsky
D. E.Walker
D. Walker
R. K. Wakerlin~
C. Walton
B. Wang
W. M. Washington
G. A. Watson
M. N. Weindling
R. White
R. L. Wigington
:\II. Wildman
J. E. Wolle
H. Wolpe
R. E. Wyllys
J. W. Young, Jr.
P. De Young
N. S. Zimbel
PANELISTS
J. Arachtingi
:\1. H. Ballot
G. R. Bolton
D. Comer
A. J. Critchlow
J. Dengell
M. Duggan
F. R. Field, Jr.
J. K. Hawkins
J. H. Hiestand
G. Hollander
lVI. Irwin
A. S. Jackson
. E. G. Johnson
J. Karber
R. V. Kelly
K. E. Knight
A. J. lVlauceri
H. W. 1Iergler
-E. Shapiro
T. Sheridan
B. Strassburg
P. D. Walker
E. A. Weiss
T. J. Williams
8ESSION CHAIRMEN
· J. B. Angell
K. Beisty
· J. Bouvard
R. Conn
R. J. Creasy
A. J. Critchlow
A. van Dam
S. Elkin
· J. M. Engel
D. C. Englebart
L. Fein
L. Feldner
H. R. Gillettee
A. Greeman
W. A. Gross
O. Gutwin
I. N. Hooton
M·. E. Hopkins
T. Kehl
J. D. Kennedy
J. M. Kurtzberg
G. Lewis
W. Lichtenberger
R. N. Linebarger
R.·Little
P. R. Low
G. Martins
M. S. Mason
G. Michael
D. E. Mulvihill
J. H. Munson
G. L. Murray·
G. W. McClary
N. R. Nielsen
A.Opler
A. V. Pohm
B. Raphael
D. R. Reddy
M. Rotenberg
H. Sackman
I. R. Schwartz
A. Seelenfreund
J. E. Sherman
J. C. Strass
E. A. Weiss
AMERICAN FEDERATION OF INFORMATION
PROCESSING SOCIETIES (AFIPS)
OFFICERS and BOARD of DIRECTORS of AFIPS
Secretary
lVIR. ARTHUR 1. RUBIN, lVIP 170
l\iJartin Marietta Corporation
P. O. Box 5837
Orlando, Florida 32805
President:
l\lR. PAUL ARlVIER
The RAND Corporation
1700 lVlain Street
Santa l\fonica, California 90406
Treasurer
DR. WALTER HOFFMAN
Computing Center
Wayne State University
Detroit, Michigan 48202
V ice President:
DR. RICHARD 1. TANAKA
California Computer Products, Inc.
305 North l\fuller Street
Anaheim, California 92803
ACM Directors
DR. B.A. GALLER
University of Michigan
1056 Ferdon Road
Ann Arbor, lVIichigan 48104
MR. R. G. CANNING
Canning Publications Inc.
134 Escondido Avenue
Vista, California 92083
DR. WALTER HOFFl\IAN
Computing Center
Wayne State University
Detroit, l\1ichigan 48202
)VIR. J. D. l\:IADDEN
ACl\I Headquarters
211 East 43rd Street
New York, New York 10017
IEEE Directors
:.\IR. L. C. HOBBS
Hobbs Associates, Inc.
P. O. Box 686
Corona del ~Jar, California 92625
DR. RICHARD 1. TANAKA
California Computer Products, Inc.
il05 North l\1uller Street
Anaheim, California 92803
MR. KEITH W. UNCAPHER
The RAND Corporation
1700 .:vIain Street
Santa ':\iJonica, California 90406
MR. SAl\1UEL LEVINE
Bunker-Ramo Corporation
44.1 Fairfield Avenue
St~mford, Connecticut 06902
Simulation Councils Director
A merican Society For 1nformation
Science Director
MR. JOHN E. SHERl\1AN
Lockheed l\!Jissiles & Space Corp.
D59-10; B-151
P. O. Box 504
Sunnyvale, California 94088
l\fR. HAROLD BORKO
School of Library Service
UCLA
Los Angeles, California 90064
Association for Computational
Linguistics Observer
Special Libraries Association Observer
l\,fR. BURTON E. LAMKIN, CHIEF
Library & Information Retrieval Staff
Federal Aviation Agency
800 Independence Avenue, S. E.
Washington, D. C. 20003
DR. DONALD E. WALKER
Head, Language & Text Processing
The l\,fitre Corporation
Bedford, lVIassachusetts 01730
A merican I nstitut~ of Certified Puolic
Account'ants Observer
Society for I nformation
Display Observer
YIR. NOEL ZAKIN
l\lanager, Computer Technical Services
AICPA
666 Fifth A venue
New York, New York 10019
l\1R. WILLIAlVI BETHKE
RADC (El\,fE, W. Bethke)
Griffiss AFB NY 13440
Executive Director
DR. BRUCE GILCHRIST
AFIPS 'Headquarters
345 East 47th Street
New York, New York 10017
Executive Secretary
Assistant Executive Secretary
l\lR. H. G. ASl\1US
AFIPS Headquarters
345 East 47th Street
New York, New York 10017
:\,fR. D. R. CRUZEN
AFIPS Headquarters
345 East 47th Street
New York, New York 10017
AFIPS Committee Chairmen
Abstracting
DR. VINCENT E. GUILIANO
School of Information & Library Studies
Hayes C, Room .5
State University of New York
:{435 ::Uain Street
Buffalo, New York 14214
Admissions
DR. ROBERT W. RECTOR
Informatics, Inc.
.~430 Van N uys Boulevard
Sherman Oaks, California 91401
Awards
DR. ARXOLD A. COHEN
UNIVAC
2276 Highcrest Drive
Roseville, ~linnesota .5.5113
Conference
DR . .:\IORTON .:\1. ASTRAHAN
IB~/I
Corporation-ASD D
P. O. Box 66
Los Gatos, California 950aO
Constitution & Bylaws
.\fIR. ARTHUR I. RUBIN, ~IP 170
::\1artin ~Vlarietta Corporation
P. O. Box 5837
Orlando, Florida 32805
Education
DR. ~VrELVIN A. SHADER
.:\Ianager of N ew ~/larkets
IB:~\'l Corporation-SDD
1000 Westchester Avenue
White Plains, New York 10604
Finance
:\JR. WALTER L. ANDERSON
General Kinetics Inc.
11425 Isaac Newton Square South
Reston, Virginia 22070
Harry Goode Memorial A ward
DR. GEORGE E. FORSYTHE
Computer Science Department
Stanford UiIiversity
Stanford, C~lifornia 94305
IFIP Congress 71
Technical Program
DR. HERBERT FREElVIAN
Professor of Electrical Engineering
New York University
School of Engineering and Science
University Heights
New York, New York 10453
DR. DAVID R. BROWN
Stanford Research Institute
333 Ravenswood Avenue
Menlo Park, California 94025
Information Dissemination
lVIR. GERHARD L. HOLLANDER
Hollander Associates
P. O. Box 2276
Fullerton, California 92633
I nt~rnational Relations
DR. EDWIN L. HARDER
1204 lVlilton Avenue
Pittsburgh, Pennsylvania 15218
Public Relations
Consultant
MR. CARL E. DIESEN
Chief, Computer Center Division
U.S. Geological Survey
Washington, D. C. 20242
lVIR. HARLAN E. ANDERSON
Time, Inc.
Time & Life Building
New York, New York 10020
Publications
u.s. Committee for IFIP ADP Group
MR. STANLEY ROGERS
P. O. BoxR
Del Mar, C~lifornia 92014
MR. ROBERT C. CHEEK
Director of l\1anagement Systems
Westinghouse Electric Corp.
3 Gateway Center
Pittsburgh, Pennsylvania 15230
Social Implication of Information
Processing Technology
MR. STANLEY ROTHMAN
TRW Systems, R3/2086
1 Spa.ce Park
Redondo Beach, California 90278
JCC General Chairmen
1989 FJCC
1968 FJCC
MR. JERRY KOORY
Programmatics
12011 San Vicente
Los Angeles, California 90049
DR. WILLIAM H. DAVIDOW
Dymec Division
Hewlett-Packard Company
395 Page Mill Road
Palo Alto, California 94306
1969 SJCC
DR. HARRISON W. FULLER
Sanders Associates, Inc.
95 Canal Street
Nashua, New Hampshire 03060
1968FJCC LIST OF EXHIBITORS
Adage, Inc.
Addison-Wesley Publishing Company, Inc.
Addressograph Multigraph Corp.
American Telephone & Telegraph
Amp, Inc.
Ampex Corporation
Anderson Jacobson Inc.
Applied Data Research, Inc.
Applied Dynamics, Inc.
Applied lVlagnetics Corporation
Association for Computing ~f achinery
Astrodata/Comcor
Athana Corp.
Audio Devices, Inc.
Auerbach Corporation
Auto-trol Corporation
Beta Instrument Corporation
Boole & Babbage, Inc.
Bryant Computer Products
Burroughs Corporation
Caelus Nlemories Inc.
California Computer Products, Inc.
Calma Company
Certex Inc.
Collins Radio Company
Communitype Corp.
Computek, Inc.
Computer Applications Inc.
Computer Communications, Inc.
Computer Design Publishing Corp.
Computer Displays Inc.
Computer Industries
Computer Peripherals Corporation
Computer Sciences Corporation
Computer Transceiver Systems, Inc.
Computer Update
Computerworld
Computron Inc.
Com-Share
Conrac
Control Data Corporation
Cybetronics, Inc.
Data Communications, Systems Inc.
Data Disc, Inc., Display Division
Data General Corporation
Datamation
Data Processing lVlagazine
Data Products Corporation
Datascan
DatelCorp.
Decade Computer Corporation
Di/An Controls, Inc.
Digi-Data Corporation
Digital Development Corporation
Digital Devices, Inc.
Digi tal Equipment Corporation
Digitronics Corporation
Dura, Division Intercontinental Systems, Inc.
Dynamic System Electronics'
EaStman Kodak Company
Edwin Industries
E-H Research Laboratories, Inc.
Electro-Mechanical Research Inc.
Electronic Associates Inc.
Electronic Design
Fabri Tek
Factsystem Inc.
Ferroxcube Corporation
Frieden, Inc.
Gamco Industries, Inc., A Subsidiary of Siboney Corp.
General Automation Inc.
General Computers, Inc.
General Design, Inc.
General Electric Company
General Kinetics Incorporated
Gerber Scientific Instrument Company
Hendrix Electronics
Hewlett Packard Company
HF Image Systems, Inc.
Honeywell
Houston Instrument Div. Bausch & Lomh
Hybrid Systems Inc.
Indiana General Corporation
Information Control Corporation
Information Displays, Inc.
Information Technology, Inc.
Infotechnics, Inc.
IEEE
Interdata, Inc.
IBM Corporation
ITT /Industrial Products
Kennedy Company
Lenkurt Electric Company
Litton Automated Business Systems
Litton/Datalog Division
Lockheed Electronics Company
lVlacmillan Company
lVIAC Panel Company
Magne Head, A Div. of General Instrument Corp.
McGraw Hill Book Company
Memorex Corporation
Memory Technology Inc.
Micro Switch, A Div. of Honeywell
Milgo Electronic Corporation
3M Company
Modern Data Systems
l\tlohawk Data Science Corp.
Motorola Instrumentation & Control Inc.
The National Cash Register Co.
Nissei Sangyo Co., Ltd.
Olivetti Underwood Corp.
Omnitec Corp., A Subsidiary of Nytronics, Inc.
Peripheral Equipment Corp.
Potter Instrument Company, Inc.
Prentice Hall, Inc.
RCA Electronic Components
RCA Information Systems
Raytheon Computer
Rixon Electronics, Inc.
Sanders Associates, Inc.
Sangamo Information Systems
Scientific Control Corp.
Scientific Data Systems
Semicon Computer Systems
Soroban Engineering, Inc.
Spartan Books
Stromberg Datagraphics, Inc.
Systems Engineering Laboratories, Inc.
Systron-Donner Corporation
Systronics, Inc.
Tektronix, Inc.
Teletype Corporation
Telex Computer Products Division
Texas Instruments Incorporated/Components Group
Transistor Electronics Corporation
Tri-Data Corporation
Tymshare, Inc.
UNIVAC, Division, Sperry Rand Corp.
URS Systems Corporation
U.S. Magnetic Tape
Varian Data Machines
Vermont Research Corporation
Viatron Computer Systems Corporation
Wang Laboratories, Inc.
John Wiley & Sons, Inc.
Wyle Laboratories, Inc.
Xerox Corporation
AUTHOR INDEX
Abu-Ghedia, 0.,
731
Allen, R. P.,
157
Anderson, E. P.,
431
Anderson, S. E.,
1317
Ashley, J. R., Jr.,
585
Backus, G.,
1273
Badger, G. F., Jr.,
1
Balzer, R. M.,
233
Barnes, R. C. lV1.,
1077
Bedient, C. K.,
663
Bernstein, W. A.,
7
Bequaert, F. C.,
611
Bobrow, D. G.,
305
Booher, R. K.,
877
Borko, H,
1469
Bostwick, D. I.,
1197
Brandin, D. H.,
345
Bratman, H.,
1349
Brawn, B.,
1019
Breuer, M. A
1502
Bullock, T.,
585
Burger, J. F.,
441
Caceres, C. A.,
381
Calhoun, D. F.,
847
Calvert, T. W.,
227
Campbell, D. J.,
903
Cardwell, D.W.,
243
Carmody, P.,
981
Cheatham, T. E., Jr., 937
Cheek, R. C.,
51
Childs, D. L.,
557
Churchman, G. W., 1467
Chingari, G.,
57
Citron, J.,
1299
Clancy, K.,
29
Cohen,.D.,
1043
Conant, B. K.,
1233
Connors,M. M.,
417
Conway, M. E.,
835
Corbett, J. L.,
1105
Cotton, I. W.,
533
Coulman, G. A.,
593
Crosby, H. A.,
787
Crunkleton, J.,
683
Cserhalmi, N.,
857
Csuri, C.,
1292
Damron, S.,
1381
Day, P.,
1187
Day, W~,
809
Denes, P. B.,
319
Denning, P. 1.,
915
Dike, L. L.,
633
Donath, W. E.,
1502
Dove, R. K.,
1321
Duda, R. 0.,
1139
Earnest, L. D.,
329
Edwin, A.,
127
Edwin., L. B.,
127
Engelbart, D. C.,
395
English, W. K.,
395
Epstein, G.,
141
Erbech, D.,
797
Farmer, 0.,
359
Feldman, C. G.,
67
Ferentzy, E. N.,
637
Fischer, A.,
937
Flynn, M.,
957
Frank, A. J.,
179
Freed, R. N.,
387
Freibergs, I. F.,
1163
Friedl, P. J
1051
Gabura, J. R.,
637
Gangwere, S. G., Jr., 1411
Gardner, R. M ...
809
Geyer, J. B.,
891
Gilbert, E. G.,
1251
Gilbert, F.,
1273
Gold, M.,
1473
Gordon, D.,
545
Gorman, D. F.,
1500
Gosden, J. A.,
81
Gossling, T. H.,
1089
Greatorex, F. S., Jr., 533
Gustavson, F.,
1091
Gustlin, D. P.,
1389
Guzman, A.,
291
Hashiguchi, M.
1369
Hagan, T.G.,/
747
Hara, H. H.,
565
Hardaway, R. H.,
105
Harding, P. A.,
1213
Haring, D. R.,
255
Harmon, W.,
997
Hart, P. E.,
1139
Hatch, T. F ..,
891
Heffner, W. J.,
903
Higgins, A. N.,
39
Hissey, B. L.,
219
Hitt, D. C.,
655
Holland, F. C.,
1399
Holt. A. W.,
1451
Honore, P.,
1307
Hooper, R. L.,
649
Hooton, I.,
1077
Horning, J.,
617
Howe, R. M.,
601
Hau, S.,
601
Hunt, E.,
923
Hurley, P.,
1151
Ide, E.,
1117
Ishidate, T.,
969
719
Jacoby, E.,
Johnson A. E.,
1
Jorrand, P.,
937
Kanter, H.,
493
Karplus, W.,
565, 1225
1259
Kasahara, A.,
Kellogg, C. H.
473
Kerr, R.,
1065
1117
Kiessling, C.,
305
Klatt, D. H.,
787
Klukis, M. K.,
15
Konigsford, W. L.,
1033
Kopf, J. 0.,
1187
Kerjci, H.,
1011
Keuhner, C. J.,
1499
Kurtzberg, J. 1\:1.,
381
Kushner, G.,
1431
Lehman, M.,
15
Lett, A. S.,
1065
Lie, H. P.,
425
Little, J. D. C.,
145
Liu, H.,
1459
Lo,A.W.,
425
Lodish, L. M.,
683
Lord, R. E.,
857
Lowenschuss, 0.,
1381
Lucas, J.,
1051
Lusebrink, T. R.,
431
McAfee, R. K.,
329
McCarthy, J.,
1369
McFarland, K.,
617
McKeeman, W.,
411
McKenney, J. L.,
997
Maasberg, W.,
777
Macaulay, M.,
1061
Macefield, B.,
193
Main, W.,
1089
Mallett, J. F.,
511
Marchand, M.,
1349
Martin, H.,
319
Mathews, M. V.,
929
Mattison, R. L.,
371
Mayne, J.,
1399
Merikallio, R.,
1329 .
Metsker, G. S.,
1197
Mezrich, R. S.,
929
Mitchell, ;R. T.,
L065
Miller, G.,
1381
Miller, J.,
279
Miller, R. B.,
j
Miller, W. F.,
Moore, A.,
Moore, R. K.,
Moran, R. A.,
Morris, S. 1\1.,
Munson, J. H.,
Murphy, J. E.,
Nelson, G. W.,
Nelson, E.,
Newey, M. C.,
Newman, D. J.,
Nielson, N. R.,
Nixon, R. J.,
Noll, A. ::\1.,
O'Donnell, C. F.,
O'Keil, J. T.,Jr.,
Oppenheimer, G.,
Ottaway, G. H.,
Owens, J.,
Perstein, E.,
Philips, R. W.,
Plauger, P. J.,
Prentice, D. D.,
Pryor, T.,
Raby, J. S.,
Rahe, G. A.,
Randell, B.,
Rangel, R. G.,
Rapkin, ::.vI. D.,
Reddy, D. R.,
Rehmann, S. L.,
Richards, J. C.,
Risko, F. D.,
Robinson, D.,
Robinson, D. A. H.,
Rohland, W. S.,
279
493
193
1251
353
1125
1169
45
617
1339
575
521
747
1279
867
201
29
655
7
1349
1
1033
1389
809
719
1225
1011
171
731
329
1411
987
1361
719
1065
1151
Rolund, M. W.,
Rosen, S.,
Rosenfeld, J.,
Rosove, P. E.,
Russo, R. L.,
Sackman, H.,
Salbu, E.,
Sander, W. B.,
Schaefer, L.,
Scheff, B.,
Schiesser, W. E.,
Schwarcz, R. l\l.,
Schwartz, J. 1.,
Schwartz, J. L.,
Sederholm, C. H.,
Seehuus, T. K.,
Seelenfreund, A.,
Selwyn, L. L.,
Selzer, R. H.,
Shaffer, J.,
Shaw, A. C.,
Shirey, R. W.,
Sholtz, P. N.,
Shirk, R.,
Shubin, H.,
Sibley, E. H.,
Siekert, R. G.,
Silk, 1\1. G.,
Simmons, R. F.,
Simpson, W. D.,
Singer, K. l\1.,
Sisson, S. S.,
Smidt, S.,
Smith, K. C.,
Soma, G.,
1213
1443
1431
1479
1501
1491
1381
1205
747
857
353
441
89
1285
1051
997
431
1473
817
1292
279
233
371
655
797
445
219
1099
441
1219
493
957
499
1177
683
Spandorfer, L. M.,
835
Springer, T. E.,
359
Sproull, R. F.,
765
Steel, T. B., Jr.,
99
Stewart, D.,
797
Stone, H. S.,
949
Strauss, J. C.,
339,575
Sutherland, I. E., 757, 765
Svetlik, J.,
593
Thompson, 1\1. D.,
701
Taylor, E. E.,
1285
Taylor, R. W.,
545
Traglia, P.,
1151
Tunis, C. J.,
1117
Uber, G. T.,
219
Vicens, P. J.,
329
Vilkomerson, D. H. R., 1197
Waaben, S.,
981
Weihrer, A. L.,
381
Weiner, D. D.,
1371
Weksel, W.,
371
White, :\1. E.,
75
Whitney, J.,
75, 1299
Wiekert, R. G.,
219
~Vildmann, :\1.,1381
Willard, D. A.,
709
219
Williams, P. E.,
Winer, D. E.,
381, 1317
Winkless, N.,
1307
Woods, W. A.,
457
Wortman, D. B.,
617
Wright, S. B.,
1099
Yavne, R ..
115
Zosel, :\1.,
923
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