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AFIPS
CONFERENCE
PROCEEDINGS
VOLUME 34

1969
COMPUTER
CONFERENCE
May 14 -16, 1969
Boston, Massachusetts

The ideas and Opl1l10nS express herein are solely those of the authors and are
not necessarily representative of or endorsed by the 1969 Spring Joint Computer
Conference CommiHee or the American Federation of Information ProCeSSii1.g
Societies.

Library of Congress Catalog Card Number 55-44701
AFIPS Press
210 Summit Avenue
Montvale, New Jersey 07645

© 1969 by the American Federation of Information Processing Societies,

may not be reproduced in any form without permission of the publisher.
Printed in the United States of America

AMERICAN FEDERATION OF INFORMATION
PROCESSING SOCIETIES (AFIPS)
OFFICERS and BOARD of DIRECTORS of AFIPS
President

Secretary

PAUL ARMER
Computation Center
Stanford University
Stanford, California, 94305

ARTHUR I. RUBIN
Martin Marietta Corporation
P.O. Box 5837
Orlando, Florida, 32805

Vice President

Treasurer

RICHARD I. TANAKA
California Computer Products, Inc.
305 North Muller Street
Anaheim, California, 92803

WALTER HOFFMAN
Computing Center
Wayne State University
Detroit, Michigan, 48202

ACM Directors

R. G. CANNING
Canning Publications, Inc.
134 Escondido Avenue
Vista, California, 92083

B. A. GALLER
University of Michigan
Ann Arbor, Michigan, 48104

211 East 43rd Street
New York, New York, 10017

IEEE Directors

SAMUEL LEVINE
Bunker-Ramo Corporation
445 Fairfield Avenue
Stamford, Connecticut, 06902

L. C. HOBBS
Hobbs Associates, Inc.
P.O. Box 686
Corona del Mar, California, 92625
KEITH W. UNCAPHER
The RAND Corporation
1700 Main Street
Santa Monica, California, 90406

Society for Information
Display Director

American Society For Information
Science Director

WILLIAM BETHKE
RAOC (EME, W. Bethke)
Griffiss AFB NY 13440

HERBERT KOLLER
Leasco Systems & Research Corp.
4833 Rugby Avenue
Bethesda, Maryland, 200 14

Special Libraries Association Director

Association for Computational
Linguistics Director

DONALD E. WALKER
Language & Text Processing
The Mitre Corporation
Bedford, Massachusetts, 01730

BURTIN E. LAMKIN
Library & Information Retrieval Staff
Federal Aviation Agency
800 Independence Avenue, S.E.
Washington, D. C. 20003

Executive Secretary

Executive Director

H. G. ASMUS
210 Summit Avenue
Montvale, New Jersey, 07645

BRUCE GILCHRIST
210 Summit Avenue
Montvale, New Jersey, 07645

American Institute of Certified Public
Accountants Director

Simulation Councils Director

NOEL ZAKIN
Computer Technical Services
AICPA
666 Fifth Avenue
New York, New York, 10019

JOHN E. SHERMAN
Lockheed Missiles & Space Corp.
D59-10; B-151
P.O. Box 504
Sunnyvale, California, 94088

AFIPS Committee Chairmen

Abstracting

Constitution & Bylaws

VINCENT E. GUILIANO
School of Information & Library Studies
Hayes C, Room 5
State University of New York
3435 !-v1ain Street
Buffalo, New York, 14214

ARTHUR I. RUBIN, MP 170
Martin Marietta Corporation
P.O. Box 5837
Orlando, Florida, 32805

Education

ROBERT W. RECTOR
Informatics, Inc.
5430 Van Nuys Boulevard
Sherman Oaks, California, 91401

CSC-Infonet
150 N. Sepulveda Blvd.
El Segundo, California, 90245

Awards

Finance

ARNOLD A. COHEN
UNIVAC
2276 Highcrest Drive
Roseville, Minnesota, 55113

WALTER L. ANDERSON
General Kinetics, Inc.
11425 Isaac Newton Square South
Reston, Virginia, 22070

1969 SPRING JOINT COMPUTER CONFERENCE COMMITTEE
Chairman

Harrison W. Fuller
Sanders Associates, Inc.
Vice Chairman

Treasurer

Brandt R. Allen
W. Burgess (Assistant)
Lybrand, Ross Bros., & Montgomery

John E. Ward
Massachusetts Institute of Technology
Secretary
Technical Program

Theodore H. Bonn, Chairman
Honeywell, Inc.
Richard F. Clippinger, Vice Chairman
Honeywell, Inc.

Albin A. Hastbacka
RCA
Local Arrangements

James H. Burrows
Mitre Corporation

Charles Gardiner, Chairman
Itek

Mark E. Connelly
Massachusetts Institute of Technology

Morton· Elmer, Vice Chairman
Sanders Associates, Inc.

John J. Donovan
Massachusetts Institute of Technology

Charles R. Burgess
QEI Computer and Information Systems

Kent R. Groote
Raytheon Company

Ralph B. Levy
Itek

Robert Hengen
Telefile Computer Corporation

Richard
DASA

Henry S. McDonald
Bell Telephone Laboratories

Edward Minnich
Sanders Associates, Inc.

Fred H. Scife
Control Data Corporation

John A. O'Brien
Itek

Norman H. Taylor
Arthur D. Little, Inc.

Harvey Rubenstein
Sylvania

Special Events

Allen Kluchman, Chairman
Data General Corporation

L.

Libby

David Thorndike
CH Sprague Leasing Company
Oliver Wolcott
Honeywell, Inc.

Jack Porter, Vice Chairman
Mitre Corporation

Public Relations

Jack Nolan
M. I. T. Lincoln Laboratory

Norman M. Bryden, Chairman
Honeywell, .Inc.

Cornelius Peterson
Computer Usage

D. Sweeney, Vice Chairman
Honeywell, Inc.

Joseph Knight
M. I. T. Lincoln Laboratory

Aaron Levine, Consultant
Gilbert-Levine & Co., Inc.

Printing and Mailing

Education Program

A. Dean Barrett, Chairman
Sanders Associates, Inc.

W. Feurzeig, Chairman
Bolt, Beranek & Newman, Inc.

William Pizzo, Vice Chairman
Sanders Associates, Inc.

Jordan Baruch
Educom

Kenneth Rabasca
Sanders Associates, Inc.
Donald Marchand
Sanders Associates, Inc.

David Tiedeman
Harvard
Robert Haven
Project Local
Walter Koetke
Lexington School System

Registration

Bruce M. Campbell, Chairman
IBM Corporation
Richard K. Goran, Vice Chairman
IBM Corporation

Exhibit Coordination

David Sudkin, Chairman
Viatron Computer Systems Corporation
R. G. Gould, Vice Chairman
Digital Equipment Corporation

Marjorie Bloom
Bolt; Bera.nek & Newman, Inc.
Cynthia Soloman
Bolt, Beranek & Newman, Inc.
Liason

Jack L. Mitchell, IEEE
M. I. T. Lincoln Laboratory
M. I. T. Lincoln Laboratory
Maurice I. Stein, SCI
Morton M. Astrahan,
AFIPS Conference Committee
IBM Corporation

Frank E. Heart
Bolt, Beranek & Newman, Inc.

Albert S. Hoagland,
AFIPS Conference Committee
IBM Corporation

Hawley K. Rising
Bolt, Beranek & Newman, Inc.

ICC Conference

IFIP Congress 71

MORTON M. ASTRAHAN
IBM Corporation-ASDD
P.O. Box 66
Los Gatos, California, 95030

HERBERT FREEMAN
New York University
School of Engineering and Science
University Heights
New York, New York, 10453

International Relations
Public Relations

EDWIN L. HARDER
Westinghouse Electric Corp.
1204 Milton Avenue
Pittsburgh, Pennsylvania, 15218

CARL E. DIESEN
Computer Center Division
U. S.Geological Survey
Washington, D. C., 20242

Publications

HARLAN E. ANDERSON
Time, Inc.
Time & Life Building
New York, New York, 10020

Social Implication of Information
Processing Technology

STANLEY ROTHMAN
TRW Systems, R3/2086
1 Space Park
Redondo Beach, California, 90278

ICC Technical Program

DAVID R. BROWN
Stanford Research Institute
333 Ravenswood Avenue
Menlo Park, California, 94025

Information Dissemination

GERALD L. HOLLANDER
Hollander Associates
P.O. Box 2276
Fullerton, California, 92633·

Conference

R. GEORGE GLASER
McKinsey and Co.
100 California St.
San Francisco, California, 94111
JCC General Chairman

U.S. Committee for IFIP ADP Group

ROBERT C. CHEEK
Westinghouse Electric Corp.
3 Gateway Center
Pittsburgh, Pennsylvania, 15230

1969 FICC
1970 SICC

JERRY KooRY
Programmatics
12011 San Vicente
Los Angeles, California, 90049

HARRY L. COOKE
RCA Laboratories
Princeton, New Jersey, 08540

CONTENTS
OPERATING SYSTEMS
A modular approach to file system design ........ ,........... ,........... ,.. .
RTOS ' - Extending OCj360 for real time spaceflight control
A PANEL SESSION - ON-LINE BUSINESS APPLICATIONS

J. Alsop, II
15 J. L. Johnstone

29 J. T. Gilmore, Jr.
30 C. T. Casale
32 M. Greenberger
32 W. M. Zani

A PANEL SESSION - COMPUTERS AND THE
UNDERPRIVILEGED
Computers and the underprivileged ........................ ,........... , ..... ,.... .
A program for the underprivileged and overprivileged in the
Boston community ............................................ :.......................... .
What the JOBS program is all about ............................................. .
Computers and the underprivileged ............................................... .
Experimental and demonstration manpower projects .............. ,.... .

36
37
37
38

A PANEL SESSION - COMPUTERS IN SERVICE TO
LIBRARIES OF THE FUTURE
Computers in service to libraries of the future:
Library Requirements ....................... " ........................................ .
Using computer technology - Frustrations abound ..................... .
Computers in service to libraries of the future ........................... .

41 W. N. Locke
42 H. D. Avram
44 H. W. Dillon

SOFTWARE
Batch, conversational, and incremental compilers ........ ,................ .
TRANQUIL: A language for an array processing computer ........ ..

35 M. Bauman

J. J. Donovan
W. B. Lewis
A. L. Morton, Jr.
J. Seiler

47 H. Katzan, Jr.
57 N. E. Abel
P. P. Budnick
D. j. Kuck

SNAP -

An experiment in natural language programminng ......... .

The compiled macro assembler

Y.
R.
R.
75 M.
W.
89 W.

Muraoka
S.:Northcote
B. Wilhelmson
P. Barnett
M. Ruhsam
D. Maurer

MODELS OF INTELLIGENCE
Some logical and numerical aspects of pattern recognition
and artificial intelligence ............................................................... .
A model of visual organization for the game of GO ................. .
Assembly of computers to command and control a robot ........... .
Diagnosis and utilization of faulty universal tree circuits .......... ,." ..

95
103
113
139

TECHNIQUES FOR DISPLAYS AND PICTURE PROCESSING
Solid state keyboard ........................ ,,........ , ., .................................. ,.

149 E. A. Vorthmann

W. C. Naylor
A. L. Zobrist
L. L. Sutro
G. Cioffi
E. Fiorillo

j.

T. Maupin

Computer generated graphic segments in a raster display ................. .
Errors in frequency-domain processing of images ............. " .......... .
Scan-display system of the Illiac III computer ............................. .

161 R. A. Metzger
173 G. B. Anderson
T. S. Huang
187 L. A. Dunn
L. N. Goyal
B. H. McCormick
V. G. Tareski

COMPUTER AIDED DESIGN
Interactive toierance analysIs with graphic QISplay ....................... .
A method of automatic fault-detection test generation for
four-phase MOS LSI circuits .................................................... .
A method of diagnostic test generation ....................................... .

Programmed test patterns for multi-terminal devices ..................... .

20'7 L. A. O'Neill
215 Y. T. Yen
221 A. B. Carroll
M. Kato
Y. Koga
K. Naemura
229 F. J. McIntosh

W. W. Happ
TIME-SHARING SYSTEMS
OS-3:

The Oregon State open shop operating system

Virtual memory management in a paging environment ................. .
An operational analysis of a remote console system ..................... .
A model for core space allocation in a time-sharing system

241 J. W. Meeker

N. R. Crandell
F. A. Dayton
G. Rose
249 N. Weizer
G. Oppenheimer
257 H. D. Schwetman
J. R. DeLine
265 M. V. Wilkes

GRAPHIC APPLICATIONS
Picture-driven animation .................... ,.............................................. .
Computer graphics displays of simulated automobile dynamics
Fast drawing of curves for computer display .... , .......................... .
A class of surfaces for computer display ................................... .
POGO: Programmer-Oriented Graphics Operation ....................... .

273 R. Baecker
289 C. M. Theiss
297 D. Cohen
T. M.· P. Lee
309 T. M. P~ Lee
32] B. W. Boehm
V. R. Lamb
R. L. Mobley
J. E. Rieber

TOPICS OF CURRENT INTEREST
Computer-aided processing of the news .................................. , .... .
An on-line information system for management ........................... .
Computers and Congress ............ ,.................................................... .
Automatic checkout of small computers ....................... " .............. .
Cryptographic techniques for computers ....................................... .
Montessori techniques applied to programmer training in a
workshop environment ......................................... :....................... .

3a 1 J. F. Reintjes

R. S. Marcus
339 G. F. Duffy
F. P. Gartner
35] E. S. Mesko
;{59 M. S. Horovitz
367 D. Van Tassel
373 E. R. Alexander

PAPERS RELATING TO MEMORY
. Variable topology random access memory organizations

381. M. Fischler

A. Reiter
Fault location in memory systems by program ............................. .
Characteristics of faults in MOS arrays ............................. '" ....
"'J

MANAGING LARGE-SCALE SOFfWARE PROJECTS
A systematic approach to the development of system programs
Management of computer programmers ......................................... .
The management and organization of large scale software
development projects ................................................................... .
INFORMATION RETRIEVAL AND LIBRARIES
Interactive search and retrieval methods using automatic
information displays .. , ..................... ,.......... " ................................ .
The LEADER retrieval system ..................................................... .

A PROGRESS REPORT ON PROJECT INTREX
System characteristics of intrex ..................................................... .
An experimental computer-stored, augmented catalog of
professional literature ................................................................... .

393 C. V. Ravi

403 H. R. Lambert

411 F. M. Trapnell
419 M. M. Gotterer

425 R. H. Kay

435 M.
G.
447 D.
A.

E. Lesk
Salton
J. Hillman
J. Kasarda

457 J. F. Reintjes
461 R. S. Marcus

P. Kugel
R. L. Kusik
Remote text-access in a computerized 1ibrary informationretrieval system ............................................................................. .

475 D. R. Knudson

S. N. Teicher
A combined display for computer-generated data and scanned
photographic images ................................... " ................................ .

483 D. R. Haring

J. K. Roberge
COMPUTERS AND COMMUNICATIONS
A study of multiaccess computer communications
A communications environment emulator ........... " .......................... .

APPLICATIONS OF COMUTERS IN THE URBAN ENVIRONMENT
Development of New York City's real property data base ............... .
Requirements for the development of computer-based urban
information systems ..................................................................... .
Automatic traffic signal control systems - the Metropolitan
Toronto experience ......................................... " ............................ .

491 P. E. Jackson

C.
505 J.
R.
R.

D. Stubbs
M. Pearlman
Snyder
Caplan

513 R. Amsterdam

523 S. B. Lipner
529 J. D. Hodges, Jr.

A PANEL SESSION - EDUCATION OF COMPUTER
PROFESSIONAL
Inter-relating hardware alld software in computer science education
Let's not discriminate against good work in design
or experimentation ....................... '" ................. ,........................... .

537 J. B. Dennis
538 G. E. Forsythe

Applied computer science ............................................ " ................ , .
Identifying and developing curricula in software engineering
TOOLS FOR SYSTEM PROGRAMMING
SAL: Systems Assembly Language .......... ,...................... ,............ ..
BCPL: A tool for compiler writing and system programming
EXDAMS: Extendable Debugging and Monitoring Systems
CENTRAL PROCESSOR SYSTEM DESIGN
Maximum-rate pipeline systems ............................... ,.................. ,.... .
Systematic design for modular realization of control functions
Optimizing floating point arithmetic via post addition
shift probabilities .............. ,...................... " ............... ,.................. .
A PANEL SESSION - SOFTWARE TRANSFERABILITY
Program transferability ........................ ," .......................... ,........... ,.. .
Program transferability .................. ,........... ,....................... ,.............. .
Software compatibility ...... ,.................................................... " ... ,.... ,
Standardization of high-level languages ................. '" .................... ,.
The transferability of computer programs and the data on
which they operate ..... ................................................................. .
Transferability of data and programs 'between computer systems

540 A. J. Perlis

543 C. A. Lang
557 M. Richards

567 R. M. Balzer

581 L. W. Cotten
587 S. M. Altman
A. W. Lo
597 J. A. Field

605 J. A. Ward

606 R. W. Berner
607 J. A. Gosden
608 G. M. Hopper
609 E. Morenoff
611 J. D. Sable

A PANEL SESSION - COMPUTER-ASSISTED INSTRUCTION:
CURRENT STATUS - FUTURE PROBLEMS
CAl problems and prospects ................. " .... " ......................... ,' ..... .
CAl: Research requirements for instructional strategies ............... .
Instructional uses of computers to grow gracefully and effectively
DYNAMIC GRAPHIC -

613 W. Feurzeig
614 D. N. Hansen
614 E. C. Koenig

TODAY AND TOMMORROW

A picture is worth a thousand words - and costs ...................... ..
Computer animation for the academic community ............. ,' ... ,.... .
Graphics in time-sharing: A summary of the TX-2 experience ..... .

Teaching heart function - One application of medical
computer animation ................................... " .......................... ,..... .

617 J. C. R. Licklid~r
623 W. H. Huggins
D. R. Entwisle
629 W. R. Sutherland
J. W. Forgie
M. V. Morello
637 A.
A.
B.
G.

H. Gott
F. Bowyer
R. Kubert
W. Nevatt

THE DARTMOUTH SYSTEM AND ITS APPLICATIONS
The many roles of computing on the campus ............................ ..
Design considerations for an educational time-sharing system
A flexible user validation language for time-sharing systems ....... .
Project IMPRESS: Time-sharing in the social sciences ...... " ....... .
Secondary school use of the time-shared computer at
Dartmouth College ............................. " ................................. ,...... .

649 T. E. Kurtz
657 R. F. Hargraves, Jr.
A. Stephenson
665 J. S. McGeachie
673 E. D. Meyers, Jr.
681 J. H. Danver
J. M. Nevison

COMPUTER SYSTEMS VS. HEALTH SYSTEMS:
WINNING?

WHO IS

Health information and planning systems: The need
for consolidation ........................ ,...................... " .......................... .
Computer assisted instruction in the diagnosis of cardiac arrhythmias
Hospital automation: Something more than a computer ............... .

A Position paper - Computers in medicine: Automation vs.
improvement of status quo ................. ' ............................. '" ....... .

691 P. F. Gross
703 E. J. Battersby
709 W. L. Bennett
C. F. StrQOOeI
B. C. Glueck, Jr.
715 A. R. Feinstein

MEAStJREMENT AND MODELING OF DIGITAL H.'<\RDW~lill/
SOFTWARE SYSTEMS
An analytic model of multiprogrammed computing ..................... .

717 R. R. Fenichel

Measurement based automatic analysis of FORTRAN programs

723 E. C. Russell

A. J. Grossman
G. Estrin
Software measurements and their influence upon machine
language design ................................... " ... ' ....................... , ............ .

733 L. Presser

M. A. Melkanoff
More on simulation languages and design methodology for
computer systems ......................................................................... .

739 D. L. Parnas

SCIENTIFIC APPLICATIONS
Calculating and plotting equipotential lines for objects with
cylindrical geometry .. ;.................................................................. .
A modular system for reactor calculations .................................. ..

Performance testing of function subroutines ................................ ..
Towards. ~ abstract mathematical theory of :iloating-"point arithmetic

751 L. Just
A. Kennedy
P. Walker
A. Rago
G. Leaf
759 W. J. Cody, Jr.
765 D. W. Matula

A PANEL SESSION - SMALL COMPUTERS FOR DATA
TERMINAL NETWORK CONTROL
Small computers in data networks .................................................. ..
The use of a small computer as a terminal controller for a
large computing system ........... " ... " .................................. ,.......... .

773 C. B. Newport
775 H. B. Burner

R. Million
O. W. Richard
J. S. Sobolewski
COMPUTATION AND PROGRAM SPECIFICATION
A system for designing fast programming language translators ....... .
Generating parsers for BNF grammars ......................................... .
An extended BNF for specifying the syntax of declarations
A hierarchical graph model of the semantics of programs ............. .

777
79:3
801
813

V.
F.
G.
T.

Schneider
L. DeRemer
E. Whitney
W. Pratt

HYBRID COMPUTER SYSTEMS AND LANGUAGES
A flexible standard programming system for hybrid computation

A real-time programming language and its processor for digital
control of industrial processes ..................................................... .
A new graphic display/plotter for small digital computers ............. .

Stability controls for the analysis of analogi digital hybrid loops

827 W. Giloi
D. Beckert
H. C. Liebig
843 L.Liang
849 G. A. Kom
S. Simons
R. Steinbach
C. Wiatrowski
859 R. Vichnevetsky

A modular approach to file
system design *
M a8sachusetts Institute of Technology
Cambridge. Massachusetts

and
JOSEPH W. ALSOP, II
International Computation Incorporated
Cambridge, Massachusetts

IXTRODUCTIOK
A generalized model or "blue-print" for the design of
sophisticated file systems is presented in this paper.
The model exploits the concepts of "hierarchical
modularity" and "virtual memory."
Any general file system design model must, of course,
be modified and refined to satisfy the requirements of a
specific environment. The details of the file system
model are presented in three steps: (1) the basic
concepts and overview are discussed, (2) an example
environment consisting of a multi-computer network
with the added complexities of coordination, structured
file directories, and removable volumes is described ,
and (3) each of the hierarchical levels of the file system
is elaborated in terms of the assumed environment.

Basic concepts used in file system design
Two concepts are basic to the general file system
model to be introduced. These concepts have been
described by the terms "hierarchical modularity" and
"virtual memory." They will be discussed briefly
below.

Hierarchical modularity
The term "modularity" means many different things
to different people. In the context of this paper we

* Work reported herein was suppOlted (in part) by Project
Research Projects Agency, Department of "DefeI.se. under
Office of Xaval Research Contract Xonr-4102(Ol).

will be concerned with an organization similar to that
proposed by Dijkstra6 ,7, and Randell. 14 The important
aspect of this organization is that all activities are
divided into sequential processes. A hierarchical
structure of these sequential processes results in a level
or ring organization wherein each level only communicates with its immediately superior and inferior levels.
The notions of "levels of abstraction" or "hierarchical modularity" can best be presented briefly by
an examp Ie. Consider an aeronautical engineer using a
matrix inversion package to solve space flight prob lems .
At his level of abstraction, the computer is viewed as a
matrix inverter that accepts the matrix and control
information as input and provides the inverted matrix
as output. The application programmer who wrote the
matrix inversion package need not have had any
knowledge of its intended usage (superior levels of
abstraction). He might view the computer as a "FORTRAN" machine", for example, at his level of abstraction. He need not have any specific knowledge of
the internal operation of the FORTRAN system
(inferior level of abstraction), but only of the way in
which he can interact with it. Finally, the FORTRAK
compiler implementer operates at a different (lower)
level of abstraction. In the above example the interaction between the 3 levels of abstraction is static
since after the matrix inversion program is completed,
the engineer need not interact, even indirectly, with the
applications programmer or compiler implementer. In
the form of hierarchical modularity used in the file
system design model, the multi-level interaction IS
continual and basic to the file system operation.

2

Spring Joint Computer Conference, 1969

Figure I-Hierarchical levels

There are several advantages to such a modular
organization. Possibly the most important is the
logical completeness of each level. It is easier for the
system designers and implementers to understand the
functions and interactions of each level and thus the
entire system. This is often a very difficult problem in
very complex file systems with tens or hundreds of
thousands of instructions and hundreds of interdependent routines.
Another by-product of this structure is "debugging"
assistance. For example, when an error occurs it can
usually be localized at a level and identified easily.
The complete verification (reliability checkout) of a
file system is usually an impossible task since it would
require tests using all possible data input and system
requests. In order to construct a finite set of relevant
tests, it is necessary to consider the internal structure
of the mechanism to be tested. Therefore, an important
goal is to design the internal structure so that at each
level, the number of test cases is sufficiently small that
they can all be tried without overlooking a situation.
In practice, level would be checked out and verified,
then levell, level 2, etc., each level being more powerful, but because of the abstractions introduced, the
number of "special cases" remains within bounds.

°

Virtual memory
There are four very important and difficult file system
objectives: (1) a flexible and versatile format, (2) as
much of the mechanism as possible should be invisible,
(3) a degree of machine and device independence, and
(4) dynamic and automatic allocation of secondary
storage. There have been several techniques developed

to satisfy these objectives in an organized manner;
the concept exploited in this generalized file system has
been called "segmentation"5 or "named virtual memorv" . 3 Under this system each file is treated as an
~rdered sequence of addressable elements, where each
element is normally the same size unit as the main
storage, a byte or word. Therefore, each individual
file has the form of a "virtual" core memory, from
whence the name of the technique came. The size of
each file is allowed to be arbitrary and can dynamically
grow and shrink. There is no explicit data format
associated with the file; the basic operations of the file
system move a specified number of elements between
designated addresses in "real" memory and the "virtual" memory of the file system.
There are several reasons for choosing such a file
concept. In some systems the similarity between files
and main storage is used to establish a single mechanism
that serves as both a file system for static data and
program storage and a paging system 3 ,5,8 for dynamic
storage management. "Virtual memory" provides a
very flexible and versatile format. When specific
formatting is desired, it can be accomplished by the
outermost file system level or by the user program.
For example, if a file is to be treated as a collection of
card-image records, it is merely necessary to establish a
routine to access 80 characters at a time starting at
byte locations 0,80, 160, .... Almost all other possible
formats can be realized by similar procedures.
Except for the formatting modules, the entire file
system mechanism, including allocations, buffering,
and physical location, is completely hidden and invisible to the user. This relates closely to the objective
of device independence. In many file systems the user
must specify which device should be used, its record
size' (if it is a hardware formatable device), blocking
and buffering factors, and sometimes even the physical
addresses. Although the parameters and algorithms
chosen might, in some sense, be optimal, many changes
might be necessary if the program is required to run
with a different configuration or environment.
There are very serious questions of efficiency raised
by this file system strategy. lHost of these fears can be
eased by the following considerations. First, if a file is
to be used very seldom as in program development,
efficiency is not of paramount importance; if, on the
other hand, it is for long-ternl use as in a commercial
production program, the device-independence and
flexibility for change and upkeep will be very important.
Second, by relieving the programmer of the complexities of the formats, devices, and allocations, he is
able to utilize his energy more constructively and
creatively to develop clever algorithms relating to the

:Modular Approach to File System Design

r------l
I
I

I
I

I

I

I

I

I

I

I
I

I
I

I

I

/~

/
FROM

FILE "9"

~
I
I

I
I

I

I

I

I

I
I
I

I
I

I
L ____ : _ ;

FILE 9

MAIN STORAGE

Figure 2-"Real" memory and "virtual" file memory

logical structuring of his problem rather than clever
"tricks" to overcome the shortcomings or peculiarities
of the file system. Third, in view of· the complexity of
current direct-access devices, it is quite possible that
the file system will be better able to coordinate the
files than the average user attempting to specify
critical parameters.
Overview of file system design model

The file system design model to be presented in this
paper can be viewed as a hierarchy of six levels. _In a
specific implementation certain levels may be further
sub-divided or combined as required. A ,recent study of
several modern file systems, which will be published in
a separate report, attempts to analyze the systems in
the framework of this basic model. In general all of
the systems studied fit into the model, although certain
leveh; in the model are occasionally reduced to trivial
fonn or are incorporated into other parts of the operating systenl.
The six hierarchical levels are:
1.
2.
:3.
4.
5.
6.

Input/Output Control System (IOCS)
Device Strategy )Iodules (DS)I)
File Organization Strategy }Iodules (FOS)!)
Basic File System (BPS)
Logical File System (LFS)
Access :\Iethods and User Interface

The hierarchical organization can be described from
the "top" dO\vn or from the "bottom" up. The file
system would ordinarily be implemented by starting
at the lowest level, the Input/Output Control System,
and working up. It appears more meaningful, however,

3

to present the file system organization starting at the
most abstract level, the access routines, and removing
the abstractions as the levels are "peeled away';.
In the following presentation the terms "file name",
"file identifier", and "file descriptor" will be introduced.
Detailed explanations cannot be provided until later
sections, the following analogy may be used for the
reader's assistance. A person's name (file name),
due to the somewhat haphazard process of assignment,
is not necessarily unique or manageable for computer
processing. A unique identifier (file identifier) is
usually aSf-'ligned to each person, such as a Social Security number. This identifier can then be used to
locate efficiently the information (file descriptor)

Access Methods (AM)
This level consists of the set of routines that superimpose a format on the file. In general there will
probably be routines to simulate sequential fixed-

Level 6:
Access Methods (AM)
User Interfaces

Level 5:
Logical File System
(LFS)
Level 4:
Basic File System
(BFS)

Level 3:
File Organization
Strategy Modules (FOSM)

Level 2:
Device Strategy
Modules (DSM)

Level I:
Input/Output
Control System (IOCS)

Devices
Figure :3-Hiel'al'chical file systems

Spring Joint Computer Conference, 1969

4

length record files, sequential variable-length record
files, and direct-access fixed-length record files, for
example. lVlany more elaborate and specialized fonnat
routLTleS, also called access methods or d9Jta management, can be supplied as part of the file system. Obviously, a user may write his own access methods to
augment this level.

~-------11-}.

Table I-Example procedure to perform logical file system search

-;. VOLUrlE

)0

•
J~

-

1 TC

CdAidIC'l'E.!

(&1,

l?A'fi;_LE~';TrI;

J = ,}

rlY

;i

".:,li"'

{FIL,":_-,->:,":;L>:r.F;A"H .,: P,\"':I(Il);

Basic File System (BFS)
The Basic File System must convert the file identifier
into a file descriptor. In an abstract sense, the file
descriptor provides all infonnation needed to physically locate the file, such as the "length" and "location"
of the file. The file descriptor is also used to verify
write interlocks, and set up system -wide data bases.
The Basic File System perfonns ~any of the functions
ordinarily associated with "opening" or "closing" a file.
Finally, based upon the file descriptor, the appropriate FOSlVI for the file is selected.

File Organization Strategy Modules (FOSM)
Direct-access devices physically do not resemble a
virtual memory. A file must be split into many separate

'

} -- D

Logical File System (LFS)
Routines above this level of abstraction associate
a symbolic name with a file. It is the function of the
Logical File System to use the symbolic file name to
find the corresponding unique "file identifier". Below
this level the symbolic file name abstraction is eliminated.

n

c __

1} ·

n n _

File Virtual
Memory

Record 4
' . DRecord7
Record 14

·D

Record 2

PhysiCO! Records

Figure 4---l\1:apping v"irtual memory' into ph:ysical records

physical records. Each record has a unique address
associated with it. The File Organization Strategy
Module maps a logical virtual memory address into
the corresponding physical record address and offset
within the record.
To read or write a portion of a file, it is necessary for
the FOSM to translate the logically contiguous virtual
memory area into the correct collection of physical
records or portion thereof. The list of records to be
processed is passed on to the appropriate DSM.
To minimize redundant or unnecessary I/O, the
FOSM allocates "hidden" file buffers as needed. If
the requested portion of virtual memory is contained
in a currently buffered record, the data can be transferred to the designated user main storage area without
intervening I/O. Conversely output to the file may be
buffered. If a sufficiently large number of buffer areas
are allocated to a file, it is possible that all read and
write re.quests can be perfonned by merely moving
data in and out of the buffers. When a file is "closed",
the buffers are emptied by updating the physical
records on the secondary storage device and releasing
them for use by other files. Buffers are only allocated to
files that are actively in use (Le., "open").

Device Strategy Modules (DSM)
When a large portion of a file is to be read or written,
many records must be processed. The Device Strategy
Module considers the device characteristics such as
latency and access time to produce an optimal I/O
sequence from the FOSM requests.
The DSM also keeps track of the available records
on the device. It is responsible for allocating records
for a file that is being created or expanded, and deallocating records for a file that is being erased or

Modular Approach to File System Design

truncated. The FOS}! requests that a record be
allocated when needed, the DS::\! selects the record.

Input/Output Control System (IOCS)
The Input/Output Control System coordinates all
physical I/O on the computer. Status of all outstanding
I/O in process is maintained, new I/O requests are
issued directly if the device and channel are available;
otherwise the request is que"!led and automatically
issued as soon as possible. Automatic error recovery is
attempted when possible. Interrupts from devices and
unrecoverable error conditions are directed to the
appropriate routine. Almost all modern operating
systems have an laCS.

File systems versus data management systems
In the literature there is often confusion between
systems as described above, "\vhich this paper calls
"file systems" and systems which will be called "data
management systems", such as Dl\I-1,8 GIM-1,13
and TD::\IS.17 The confusion is to be expected since
both types of systems contain all of the functional
levels described above. The systems differ primarily on
the emphasis placed on certain levels.
In general file systems, the file is considered the
most important item and emphasis is placed on the
directory organization (Logical File System) and the
lower hierarchical levels. It is expected that specialized
access methods will be written by users or supplied
with the system as needed.
In most data management systems, the individual
data items are considered the most important aspect,
therefore emphasis is placed on elaborate access
methods with minimal emphasis on the lower levels of
abstraction. Because of the heavy emphasis on a
single level, data management systems tend to appear
less hierarchical than file systems since the lower
levels are often absorbed into the access methods.
~~.1ulti-computer -netwurk e;nvitO'tI/rneni

5

is not possible to acquire a larger processor,
(b) reliability is important, or (c) there are
real-time or time-sharing constraints.
2. To serve the coordination requirements of a
network of regional computer centers.
3. To support the accessibility to a nation-wide
data base.
An example of the envl...rornnent to be considered. for
this paper can be illustrated in Figure 5. This type of
multi-computer network has been in limited use for
several years in many configurations. The IBM
7094/7044 Direct-Coupled System was probably one
of the earliest practical examples of such an interconnected arrangement.
There are several implicit constraints imposed upon
the multi-computer system illustated in Figure 5:

1. Independence of Central Processors.
Each of the central processors operates independently such that there are no direct processorto-processor data transfer nor signaling, and
furthermore there is no "master" processor.
2. Non-shared YIemory.
Each central processor has its own main storage
unit. These units are not shared with nor
accessed by another central processor.
3. Inter-locked Device Controllers.
The device controllers act as "traffic cops" to
the actual I/O direct access devices. They
control the traffic between a computer's I/O
channel and a selected I/O device. A single
device controller will only accept requests from
one channel at a time and will only select one
I/O device (among those under its control) at
a time. Once a device controller connects a.

CPU

---------MEMORY
----------

CHANNELS

CPU

CPU
--------MEMORY

CHANNELS

CHANNELS

--------MEMORY
----------

--- -------

A general file system design model must, of course,
be modified and elaborated to satisfy the needs of any
specific desired file system environment. To illustrate
the refinement process, a unique file system design will
be presented for a multi-computer network.
Multi-computer networks are becoming an increasingly important area of computer technologyY There
are several significant reasons behind the growth of
multi-computer networks:
1. To increase the power of a computer installation in a modular manner, especially if (a) it

Figure 5-Example of multi-computer file system network

6

Spring Joint Computer Conference, 1969

channel with a device, the connection lemains
intact until the channel releases the device or
an I/O error occurs,
The environment described above, although well
within the boundaries of current technology, has not
been the subject of much investigation. Such configurations are presently very expensive and, therefore,
chosen only for very specialized situations. Even then
there are only two or three processors and very
specialized software and operational factors. A discussion of the CP-67/CMS Time Sharing System 9,21
will serve to establish the relevance of the multicomputer network environment.
The CP-67/CMS Time Sharing System uses the
special hardware features of a single IBNI System/360
model 67 processor augmented by software to produce
an apparent environment corresponding to the multicomputer network illustrated in Figure 5, with many
independent central processors, device controllers, and
direct access I/O devices. In practice a typical single
processor 360/67 configuration w{)uld produce the
affect of about 30 active processors ("vii'tual" System/
360 model 65 processors each with a 256,000 byte
memory) and 50 active device controllers. ~10re
detailed descriptions of the CP-67/CMS System can
be found in the References. 1:n the traditional sense of
time-sharing, each user of the CP-67/CMS System is
provided with a "virtual" computer operated from a
simulated operator console (actually an augmented
remote terminal). Most importantly, each "virtual"
computer (i.e., user) operates logically independently
of all other" virtual" computers except for the specified
inter-connected I/O devices and device controllers.
Problems arising in multi-computer networks

There are many problems associated with the multicomputer file system network. Some of these problems
are unique to this environment. Other problems have
been solved in traditional file systems,2,17,20 but the
solutions require major revisions due to the peculiarities of the environment. The most significant problems
are listed briefly below.
1. No shared memory.

Usually file systems coordinate the status of
the files and devices by using main storage
accessible tables and data areas that describe
file status, access rights, interlocks, and allocation. There is no such common communication
area in main storage that can be accessed by all
the independent processors.
2, NQ inter-computer communication.
~1ulti-computer configurations usually provide

a mechanjsm for sending signals or data transfers
between the separate processors. With this
capability the non-shared memory problem
could be solved by either (a) electing one
processor to be the "master" processor that
coordinates the other processors, or (b) supply
all the processors with enough information
such that each processor knows what all the
other processors are doing. The concept of a
"master" processor opposes the intended homogeneous, independent processor assumption.
The possibility of supplying status information
to all other processors, although reasonable for
a three or four processor configuration, was not
considered a feasible solution for a system
with hundreds of processors and devices and
thouS'tands of files. For these reasons , intercomputer communication, although an available
capability, was not included as a required
capability of the multi-computer environment
described above.
3. No pre-arranged allocations.
For small specialized multi-computer file networks, each processor can be "assigned" a specific area of a device or set of devices that can be
used to write new files, all other processors can
only read from this area by convention. This
prevents the danger of two independent processors writing files at the same place. Such an
"arrangement" is not practical for a large, flexible multi-computer file network since the static
assignment of secondary storage space does not
take account of the dynamic and unpredictable
requirements of the independent processors.
4. Extendable device and file allocation.
The number of devices and sizes of devices as
well as the number and sizes of files are, within
reason, unlimited. For example, a specific
amount of secondary storage equivalent to
100,000 card images could be used to hold 10
files of 10,000 cards each or 1,000 files of 100
cards each. This consideration discourages
techniques that result in a strong efficiency or
main storage capacity dependency on the" size
and shape" of the file system. Of course, the
magnitude of the file system size will affect
the operation, but arbitrary restrictions such
as "no more than 64 files on a device" would be
discouraged unless essential.
5. R.emovable volumes.
It has become common to differentiate between
the I/O mechanism used to record or read information, called a "device", and the physical

Modular Approach to File System Design

medium on which the information is stored,
called a "volume". For most drums and many
disk units, the device and volume are inseparable. But, for magnetic tape units and
many of the smaller disk units the volume,
magnetic tape reel and disk pack respectively,
are removable. It is intended that the file system
include files that are on unmounted volumes
(discoY'.Jlected from an I/O device) as well as
mounted volumes. Therefore, a configuration
that consists of ten disk units may have a file
system that encompasses hundreds of volumes,
only ten of which may be actively in use at a
time. Since removing and mounting a volume
takes several minutes of manual effort, it will
be assumed that the "working set" of volumes
(volumes that contain files that are ~ctively in
use) remains static for reasonable periods of
time and is less than or equal to the number of
devices available. The fact that volumes are
removable and interchangeable (i.e., may be
mounted on different devices at different times)
does affect the organization of the file ~stem.
For example, a scheme that involved. )i,nking
files together by means of pointers .(Cihained
addressing) could require mounting volumes just
to continue the path of the chain even though
little or no "logical" information was requested
from files on that volume. In the worst case, it
might· be necessary to mount and unmount all
the volumes of the file system to locate a desired file. Such a situation should definitely be
avoided if not totally eliminated by the file
system.
6. Structured file directories and file sharing.
In a traditional file system, the mapping between·
the symbolic file name and the corresponding
file was accomplished by means of a single
)laster File Directory. For modern file systems
with thousands of files scattered over hundreds
of volfu"'1l6s, it became desirable, ii not necessary,
to form groupings of files by means of Secondary
File Directories. 4 These groupings are often
used by the system to associate users with files
they own (User File Directories). This capability
is also available to the user to arrange his files
into further sub-groups (libraries) or into separate project-related groupings. Occasionally it
becomes necessary for a file to be included in
two or more groupings (e.g., accessible by more
than one User File Directory) with potentially
different access privileges (protection) associated with each grouping. l\Iany of these features

7

that are relatively easy to implement in a
traditional file system are complicated by the
introduction of independent processors and
removable volume~.
7. Fail-safe operation.
Reliable operation is a very important requirement of a general purpose file system. There are
many known techniques for I/O error and
systematic backup and salvage procedures
that are applicable to this environment. The
important problem associated with the multicomputer network is that potential error conditions exist that are not normally found ill
traditional single computer file systems. For a
single computer system, a processor error
(including unexpected processor disconnection,
i.e., "turning off") is a rare occurrence. Such a
situation is remedied by repairing whatever
physical hardware is necessary and then running
a special "salvager" program to bring the file
system into a well-defined operational state.
In the environment of a multi-computer network, processors may be connected or disconnected at any time without any awareness
by the other processors. To prevent any inconsistent file system operation by the other
processors and eliminate the need for usually
time-consuming salvage techniques, it is necessary to keep the file system in a well-defined
consistent state at all times.
A file system design

The purpose of the remainder of this paper is to apply
the organization presented in th, File System Design
IHodel section to solve the problems associated with a
multi-computer file system network. Discussion of
the Access ::\Iethods and Input/Output Control
System will be omitted. This is necessitated for brevity
and consideration of the facts that the Access )Iethods
are highly application oriented, as discussed in a
previous section, and that the Input/Output Control
System is usually a basic and common component of
all Operating Systems. The principal contribution of
this model lies in the structure of the four other levels.

Logical file system
To present the goals and requirements of the Logical File System in a brief and demonstrative manner,
an example will be used. The reader should refer to
Figure 6 for the following discussion. It is important
that the peculiarities of the example, such as the
choice of file names (e.g., "FILE6" and "DIR4"), not

8

Spring Joint Computer Conference, 1969

VOLUME "Val I"
(User

VOLUME "VOl2"

VOLUME "VOL 3 "

1)

Vall (3)
F1LE.3

D1R 2

(User 2)

VOl2(3)

DIR 3

t

(User 3)

VOL 3 (2)

FILE 5

D1R 4

FILE 6

DIR 3

Vall (2)

VOL 2 (4)

I111111111I

I111111111I

VOll(6)

11/11111111

VOL 1(4)

111111/1111

VOL 1(5)

111/1/11111

VOL3(3)

11/1/111111

Figu!'e 6-Example of file directol'Y structure (to LFS)

be confused with the general characteristics of the
Logical File System.
. In Figure 6, there are 12 files illustrated. Associated
with each file is an identifier of the fomi "VOL1(3)".
The usage of this identifier will not be discussed until
later, in the meanwhile not.ice that each file's identifier
is unique. The 12 lftes are divided into 2 types, directory files (i.e., VOL1(3), VOL2(3), VOL3(2) , and
VOL3(b»), and data files (i.e., VOL1(2), VOL1(6),
VOLl (4), VOLt U5), VOL2(4), VOL2(2), VOL3(4),
and VOI~1(3». The distinction between directory
files and data files i~ only a matter of usage, the Access
lVrethods may operate upon a directory file in the same
manner as a data file, furthermore, all lower levels
(e.g., Basic File System) treat all files as data files.
This factor vdll be elaborated shortly.
I t is the stated function of the Logical File System to
map a file name reference into a unique file identifier.
This mapping is a function of the requested file name
(symbolic file name path) and a starting point (base
directory) in the file directory structure. In Figure 6,
three example base directories are illustrated by
associating VOL1 (3) with user 1, VOL2U~) with user
2, and VOL3(2) with user 3. Therefore, user 1 references to the file name FILE2 yieldR the file VOLl (4).

A more complex example can be illustrated by
considering the file VOL3(4). User 3 can refer to this
file under the name FILE8. Alternatively, it can be
referenced by the name DIR3.FILE7. The file DIRa,
which is associated with VOL3(5) from user 3's base
directory, is interpreted as a lower level directory.
Then from file VOL3(5) , the file name FILE7 is mapped
into VOL3(4) as intended. The file VOL3(4) can be
referenced from user 2's base directory as DIR3.FILE8
or DIR3.DIR3.FILE7, for example. From user 1's
base directory, it can be referenced as FILE3, DIR2.
DIR3.FILE8, DIR2.DIR3.DIR3.FILE7, or even
DIR2.DIR3.DIR4.DIR3.DIR3.FILE7.
Two important side effects of the base file directory
and file name path facilities are that (1) a specific
file may be referenced by many different names, and
(2) the same name may be used to reference many
different files.
The headings VOLUl\IE "VOL1", VOLUME "VOL2", and VOLUl\1E "VOL3" are intended to indicate
that the 12 files are scattered over 3 separately detachable volumes: VOL1 (containing VOL1(2), VOL1(3), VOL1(4), VOL1(5), and VOL1(6», VOL2 (containing VOL2(2), VOL2(3), and VOL2(4)), and VOL3
(containing VOL3(2), VOL3(3), VOL3(4), and VOL3(5»). If volume VOL2 were detached from the system,
user 1 could still reference VOL1(4) as FILE4 and
VOL3(4) as FILE3, but could not reference VOL3(4)
as DIR2.DIR3.FILE8 nor VOL1(5) as DIR2.DIR3.
DIR3.FILE6 since the path would logically require
passing through volume VOL2. Furthermore, user 3
is allowed to erase (Le., remove from file system structure)
the file VOL3(4) under the name FILE8, assuming
appropriate protection privileges, whether or not volume
VOL1 is mounted in spite of user 1's reference to file
VOL3(4) under the name FILE3.
The Logical File System could be extremely com ~lex
of volumes, the device characteristics, and the location
of file directories on volumes, in addition to its obvious
requirement of searching file directories. These problems
are eliminated by introducing the file identifier and
the interface with the Basic File System.
The Basic File System processes requests that
specify a file in terms of a file identifier consisting of a
volume name and index, such as (VOL3, 4), rather than
a file name. A sample call from the Logical File System
to the Basic File System, in PL/I-like notation, is:
the name of the volume containing the file, INDEX
is the corresponding unique index of the file, CORE_

:Modular Approach to File System Design

is the number of bytes to be transmitted. Using these
features, the heart of the Logical File System (ignoring
opening and closing files, file access protection, illegal
file names, etc.) reduces to the PL/I-like code presented in Table 1. It is assumed that the file name
has been broken down into an array of path element
names (e.g., if name is DIR2.DIR3.FILE8, then
PATH (1) = 'DIR2', PATH (2) = iDIR3', PATH(3)= ;
FILE8', and PATH_LENGTH = 3), that BASE_
VOLUl\IE and BASE_IKDEX initially specify the
(VOLU::'VIE,INDEX) identifier of the base directory,
and that each entry in a file directory is N bytes long
and formatted as indicated in the FILE_ENTRY
declaration.
Of course, the handling of access (protection) rights,
errors, and other responsibilities will make the Logical
File System much more complex, but it is important
to note that the design and implementation of the
Logical File System escapes all physical file organization
and device characteristic considerations and complexities.

Basic file system

System was simplified by using the facilities
of the lower hierarchical level, the file descriptors
should be maintained in a manner that allows
the File Organization Strategy Module to
process them as normal files.
These problems are solved by the use of the Volume
File Descriptor Directory (VFDD). There is a single
VFDD for each volume, it contains the file descriptors
for all files residing on the volwlle. The file descriptors
are of fixed length and are located within the VFDD
positionally according to the corresponding file
identifier's index.· In order to exploit the facilities
provided by the File Organization Strategy Module,
the VFD D can be processed by the lower levels as a
normal file. It is assigned a unique file identifier
consisting of the volume name and an index of 1,
in fact the file descriptor for a VFDD is stored (when
not in use) as its own first entry. Figure 7 presents
diagranunatically the logical file structure of Figure 6

VOll(l)
Vall (1)

»»»>

Vall (2)

I111111111

I

»»»>
--------VOl1 (3) »»»>

1. There must be a unique file descriptor for each
file regardleSS' of how often the file appears in

file directories or what symbolic names are
used. This is required to maintain consistent
interpretation of a file's status.
2. The file descriptor information for a file must
reside on the same volume as the file. This is
reasonable since if either the file or its descriptor
is not accessible at some time by the system
(i.e., unmounted) the file cannot be used, this
possibility is minimized by placing them on
the same volume.
3. In the same manner that the Logical File

VOL1 (4)
VOl1 (5)
VOll(6)

Vall (3)
FilE 3

I V0L3(4)

---------+--------DIR 2
I VOL2(3)
---------+--------FilE 2
I Vall (4)

---------

Vall (2)

The Basic File System must convert the file identifier
supplied from the Logical File System into a file
descriptor than can be processed by the File Organization Strategy l\10dule. A file descriptor is essential1y
an entry in the Active FiJe Directory (AFD) that
contains information such as the volume name, physical
location of the file on the volume, and the length of
the file. Every file must have an associated file descriptor, but since the number of passive files (i.e., not
actively in use) might be very large, the file descriptors
are maintained on secondary storage until needed
(i.e., file is "opened"). In organizing the secondary
storage maintenance of the file descriptors there are
several important considerations:

9

---------

--------- t--------

---------

---------t--------FilE 1
I Vall (2)

»»»>

FilE 4

»»»>

---------

Vall (5)

»»»>

11/1/111111

I Vall (6)

VFDD for "Vall"
Vall (6)

Vall (4)

\1111111111

\1/11111111

VOl2 (1)
VOl2( 1)

>>>>>>>

VOL2(2)

»»»>

VOl2 (3)

»»»>

VOl2 (4)

»>>>>>

VFDD for "VOL 2"

I

-.

VOl3(1l

VOL 2(2)
DIR 3

--- ------ t--------FILE 6

VOL3(3)

VOl2(4)

.. _ _._

VOL 3(2)

VUL.:Hl)

»»»>

DIR 4

»»»>

--------VOL3(4)

»»»>

I VOl2(3)

---------t--------DIR 3
I VOl3(5)

»»»>

---------

I VOl2(4)

I11111I111I

-------- ...
VOl3(2)

I VOL3(2)

---------t--------FilE S I VOl2(2)

V0L3(3)

---------t--------FilE 8
I VOL 3(4)

111//////11

--------VOL3(5)

»»»>
VOl3(S)
VOl3(4)

1//111/1111

FilE 6

I VOL 1 (5)

---------t-------FilE 2 I VOl3(3)
---------t--------FILE 7 I VOL 3(4)

FigUl'e 7-Example of file directory structure (to BFS)

10

Spring Joint Computer Conference, 1969

with the added detail of the Volume File Descriptor
Directories and File Directory formats.
The File Organization Strategy Module processes
requests that specify a file in terms of a file descriptor
(the entry extracted from the VFDD) rather than a
file name or file identifier. A sample call from the
Basic File System to the File Organization Strategy
Module, in PL/I-like notation, is:
interpretation as discussed above.
The primary function of the Basic File System
reduces to the single request:
DESCRIPTOR,M*(IlXDEX-l),:Vl); where VFDD_
DESCRIPTOR is the descriptor of the VFDD associated with the volume name supplied by the Logical
File System as part of the file identifier, INDEX is
from the specified file identifier, M is the standard
length of a VFDD entry, and DESCRIPTOR is the
desired file descriptor.
The Basic File System performs several other tasks,
such as protection validation and maintenance of the
core-resident Active File Directory that enables
efficient association between a file's identifier and descriptor for files that are in use (Le., "open"). But, as
in the Logical File System, the domain of the Basic
File System is sufficiently small and narrow that it
remains a conceptually simple level in the hierarchy.

File organization strategy modules

table is a function of the file's length and is potentially
quite large. Therefore, it is not feasible to include the
entire mapping table as part of the file descriptor.
One of the most powerful file organization strategies
utilizes index tables, Figure 8 illustrates such an
arrangement.
In this example it is assumed that each file is divided
into 1000 byte physical records. A file can be in one of
several index arrangements depending upon its current
length. If the file's length is in the range 1 to 999 bytes,
the file descriptor contains the address of the corresponding physical record. If the file is between 1000
and 499,999 bytes long, the file descriptor specifies
the address of an index table located on secondary
storage. Each entry of the index table (assumed to
require 2 bytes) designates the physical address of a
block of the file (blocks are ordered by virtual file
addresses: 0-999, 1000-1999, 2000-2999, etc.). Furthermore, for files greater than 500,000 bytes, but less
than 250,000,000 bytes, there are 2 levels of index
tables as illustrated.

.

I ~~~~n-m:uul
I : I
Descriptor

INDEX STATE 1

999

L=J
»»»>

I------~

Descriptor

»»»>

The Logical File System and Basic File System are,
to a great extent, application and device independent.
The File Organization Strategy l\'Iodules are usually
the most critical area of the file system in terms of
overall performance, for this reason it is expected that
more than one strategy may be used in a larg~ system.
Only one strategy will be discussed in this section, the
reader may refer to the papers listed in the References2 ,12 ,17 ,20 for other possible alternatives.
The FOSM must map the logical file address onto a
physical record address or hidden buffer based upon the
supplied file descriptor information. In the simplest
cast', the mapping could be performed by including a
two-part table ill the file descriptor. The first part of
each entry would indicate a contiguous range of
virtual file addresses, the second part of each entry
would designate the corresponding physical record
address. It has been assumed, however, that all file
descriptors have a specific length, wherells the ma.pping

999

INDEX STATE 2
499,999

t----~----1

»»»> I - - - - - - - . . . ! »»»>
»»»>
Descriptor

»»»>

»»»>

INDEX STATE 3

Figure 8-Example of file organization strategy

Modular Approach to File System Design

This strategy has several advantages. Under the
worst conditions of random access file processing only
from one to three I/O operations need to be performed.
By utilizing several hidden buffers for blocks of the
file as well as index tables, the number of I/O operations
required for file accesses can be drastically reduced.

Device strategy modules
The Device Strategy Modules convert "logical I/O
requests" from the File Organization Strategy Modules
into actual computer I/O command sequences that are
forwarded to the Input/Output Control System for
execution. The Device Strategy Modules handle two
rather different types of requests: (1) read or write
blocks, and (2) allocate or deallocat~ blocks.
When a request to transfer a large portion of a file
(10,000 bytes for example) is issued, it is unlikely that
a significant amount of the needed blocks are in hidden
buffers. It will, therefore, be necessary to request
I/O transfer for several blocks (e.g., about 10 blocks if
each block 1000 bytes long). The FOSl\1 will generate
logical I/O requests of the form: "read block 227 into
location 12930, read block 211 into location 13930,
etc." The DSM must consider the physical characteristics of the device such as rotational delay and "seek"
position for movable heads. It then decides upon an
optimal sequence to read the blocks and generate the
necessary physical I/O command sequence including
positioning commands. The Input/Output Control
System actually issues the physical I/O request, error
retry, and other housekeeping as discussed earlier.
The detailed strategy for choosing the optimal I/O
sequence is, of course, very device dependent and will
not be elaborated here.
The function of automatic block allocation is somewhat more complex since it involves several separate
factors. Before describing the implementation of the
mechanisms, it is wise to review the desired characteristics:
1. A file is allowed to grow in size, the FOS.:\I will
request additional hlocks for the data portions
of a file or its index tables, as needed.
2. Common direct access devices contain from
8000 to 32000 separately allocatable blocks,
thus it is not feasible to store all allocation
information in main storage.
3. Since two independent processors may be
writing new files on the same volume at the
same time, it is necessary to provide interlocks
such that they do not accidentally allocate the
same block to more than one file, yet not require

11

one processor to wait until the other processor
finishes.
These problems can be solved by use of a special
Volume Allocation Table (VAT) on each volume. In
this scheme, a volume must be subdivided into arbitrary
contiguous areas. For direct access devices with movable
"cylinder") covers an area of about 40 to 160 blocks.
A cylinder is a reasonable unit of subdivision. For each
cylinder on the volume, there is a corresponding entry
in the VAT. Each entry contains a "bit map" that
indicates which blocks on that cylinder have not been
allocated. For example, if a cylinder consists of 40
blocks, the bit map in the corresponding VAT entry
would be 40 bits long. If the first bit is a "0", the first
block has not been allocated; if the bit is a "1", the
block has already been allocated. Likewise for the
second, third, and remaining bits.
When the FOS':'\{ first requests allocation of a block
on a volume, the DS':'\! selects a cylinder and reads
the corresponding VAT entry into main storage.
An available block, indicated by a "0" bit, is located
and then marked as allocated. As long as the volume
remains in use, the VAT entry will be kept in main
storage and blocks will be allocated on that cylinder.
When all the blocks on that cylinder have been allocated, the updated VAT entry is written out and a
new cylinder selected. With this technique the amount
of main storage required for allocation information
is kept to a minimUlll (about 40 to 160 bits per volume),
at the same time the numher of extra I/O operations
is minimized (about one per 40 to 160 blocks of allocation).
The problem of interlocking the independent processors still remains. As long as the processors are
allocating blocks 011 different cylinders using separate
VAT entries, they m:1y both proceed uninterrupted.
This condition can be accomplished by utilizing a
hardware feature known as "keyed records" available
on several computers including the IB~\I System/360.
Each of the VAT entries is a separate record consisting of a physical key area and a data area. The
data area contains the allocation information described
above. The key area is divided into two parts: the
identification number of the processor currently
allocating blocks on that cylinder and an indication if
all blocks on that cylinder have been allocated. A
VAT entry with a key of all zeroes would identify a
cylinder that was not currently in use and had blocks
available for allocation.
There are I/O instructions that will automatically
search for a record with a specified key, such as zero.
Since the device controller will not switch processors

"12

Spring Joint Computer Conference, 1969

in the midst of a continuous stream of I/O operations
from a processor (i.e., "chained I/O commands"), it
is possible to generate an uninterruptable sequence of
I/O commands that will (1) find an available cylinder
by searching the VAT for an entry with a key of zero
and (2) change the key to indicate the cylinder is in
use. This thus solves the multi-processor allocation
interlock problem.
CONCLUDING COl\1lVIENTS
To a large extent file systems are currently developed
and implemented in much the same manner as early
"horseless carriages", that is, each totally unique and
"hand-made" rather than "mass produced". Compilers,
such as FORTRAN, were once developed in this
primitive manner; but due to careful analysis of
operation (e.g., lexical, syntax, and semantic analysis,
etc.), compilers are sufficiently well understood that
certain software companies actually offer "do-it-yourself
FORTRAN kits". Since modern file systems often
outweigh all other operating system components such
as compilers, loaders, and supervisors, in terms of
programmer effort and number of instructions, it is
important that a generally applicable methodology
be found for file system development.
ThiEl paper presents a modular approach to the
design of general purpose file systems. I ts scope is
broad enough to encompass most present file systems of
advanced design and file systems presently planned, yet
basic enough to be applicable to more modest file
systems.
The file system strategy presented is intended to
serve two purposes: (1) to assist in the design of new
me systems and (2) to provide a structure by which
existing file systems may be analyzed and compared.
ACKNOWLEDGMENTS
The author acknowledges the many long and often
heated discussions with his colleague, lVIr. Allen
NIoulton, from which many of the basic ideas for this
file system design were molded.
Many colleagues generously contributed their time,
energy, and criticism to help produce this final document. Special thanks are due to Prof. John J. Donovan,
Prof. David Ness, and Prof. Robert 1\1. Graham, as
wen as, Stephen Zilles, Ben Ashton, Hoo-min Toong,
lVIichael l\tfark, Derek Henderson, Norm Kohn, and
Claude Hans.
REFERENCES
1 R E BLEIER
Treating hierarchical data structures in the SDC

time-shared data management system (TDMS)

PAC M 1967
2 F J CORBATO et al
The. compo-tiMe tirne-.'jhanng system

MIT Press Cambridge 1962
3 R C DALEY J B DENNIS
Virtual rnemory, processes and sharing in multics

C A C M May 1968
4 R C DALEY P G NEUMANN
A general purpose file system ofr secondary storage
Proc F J C C 1965
5 J B DENNIS
Segmentation and the design of multi-programmed
computer systems
j A C M October 1965
6 E W DIJKSTRA

The structure of the 'THE' multiprogramming system

A C M symposium on operating systems principles
Gatlinburg Tennsesee October 1967
7 E W DIJKSTRA
Complexity controlled by hierarchical ordering of function
and variability

Working paper for the NATO conference on computer
software engineering Garmisch Germany October 7-11 1968
8 P J DIXON DR J SABLE
DM-J-a generalized data management system

Proc S J C C 1967
9 IBM CAMBRIDGE SCIENTIFIC CENTER
CP-67 JCMS program logic manual
Cambridge Massachusetts April 1968
10 IBM CORPORATION
IBM System/360 ti'TY'.e sharing system access methods
Form Y28-2016-1 1968
Multi-processor software lockout
PAC M August 1968
Design strategies for file systems: a work:ingmodel

File/68 international seminar on file organization
Helsingor Denmark November 1968
13 D B NELSON R A PICK K B ANDREWS
Glllf-1-a gerU3lalized in/orlnation inanagernent Zangu,a,gc ar.,a
computer system

Proc S J C C 1967
14 B RANDELL
Towards a methodology of computer system design

Working paper for the NATO Conference on computer
software engineering Garmisch Germany October 7-11 1968
15 R L RAPPORT
Implementing multi-process primitives in a multiplexed
computer system

S M thesis MIT department of Electrical Engineering
August 1968
16 S ROSEN
Progratnm:i"ng systetns and languages

McGraw-Hill New York 1967
17 J H SALTZER
CTSS technical notes

MIT project MAC MAC-TR-16 August 1965
18 J H SALTZER
Traffic control in a multiplexed computer system

Sc.D thesis MIT department of electrical engineering
August 1968

l\iodular Approach to File 'System Desigu

19 A L SCHERR
An analysis of time-shared computer systems
MIT project MAC MAC-TR-18 June 1965
20 SCIENTIFIC DATA SYSTEMS
SDS 940 time-sharing system technical manual

Santa Monica California August 1968
21 L H SEAWRIGHT J A KELCH
A.n introduction to CP-67 JCMS
IBM Cambridge Scientific Center report 320-2032
Cambridge Massachusetts September 1968

13

RTOS-Extending OS /360 for
real time spaceflight control
by J. L. JOHNSTO~E
Houston, Texas

INTRODUCTION
The Real Time Operating System/360 (RTOS/360),
a modified version of the standard IB::\1 System/360
Operating System (OS/360) *, was developed by the
Federal Systems Division (FSD) of IB::'VI for support of
the Real Time Computer Complex (RTCC) during
XASA's Apollo spaceflights. RTOS/360 is a real time,
• Process real time data
• Provide simplicity of use for the applications programmer
• Ensure fast response system activity (requirements
range from one-tenth of a second to one second)
•Improve efficiency
• Provide support for special devices not supported
byOS/360
• Provide a fail-safe system
• Increase job shop throughput
The presence of these features in OS/360 does not deter
from its basic capabilities; Le., all the facilities of the
current IB::\1 released OS/360 that operate in a
standard or non-real time mode of execution are
available in RTOS/360.
Some of the major functional areas which were developed at IB~1's FSD Houston Operations and added to
OS/360 in the formation of RTOS/360 were:

* IBM System/360 Operating System (OS/360) consists of a
comprehensive set of language translators and service programs
operating under the supervisory control and coordination of an
integrated set of control routines. The operating system is
designed for use with Models 30, 40, 50, 65, and 75 of Computing
System/360.

• Queue ~1anagement
• Data and Time Routing
• Time l\1anagement
• Real Time Input/Output Control System
• Data Tables
• Display Formatting Language (DFL)
• Large Core Storage Support
• Logging
• Simulated Input Control
• Fastime
• Fail-Safe Programs
• Background Utilities
• Houston Automatic Spooling Priority (HASP)
• Statistics Gathering System
• Job Accounting System
• Multi-jobbing
The RTOS environment

Although RTOS/360 can be used in a variety of
applications and computer system configurations, it is
pertinent prior to discussing its functional areas that
we establish the environment in which it was designed
to operate, i.e., the Rea.l Tit1le Computer Complex
(RTCC), the RTCC hardware, and the RTCC applications programs.
TheRTCC
The RTCC is a ground-based computing and data
processing complex for NASA's manned spaceflight
program. It includes the computer equipment, associated peripheral equipment and program packages to
monitor and support-in real time-Apollo missions,
simulations, and training exercises. l
RTCC is the core of NASA's Mission Control Center

------------------------------------------ 15 -----------------------------------------

16

Spring Joint Computer Conference, 1969

(MCC) at Houston, Texas. Flight controllers at lVICC
monitor every phase of a manned spaceflight, from
launch through orbit, reentry, and splashdown. During
a lunar mission, flight controllers also monitor and support the astronauts during their flight to the moon,
the descent to the moon's surface, the liftoff and
earth.
RTCC provides flight controllers with the information they need to monitor the flight and make decisions
regarding the mission. This simply means flight controllers sitting at consoles in Houston have precise
information in real time such as the status of every onboard system, the condition of the astronauts, their
position in space at any desired time up to 40 hours in
advance, or t.he effect that any planned maneuver
would have on the spacecraft or the astronauts.
The RTCC is called on to do many things during a
mission. Some of the more important or more common
requirements include:
• Process radar data during launch and provide
ilight controllers with present position and velocity
• Provide flight controllers with information on
whether or not the spacecraft will achieve orbit
• Process telemetry data and provide flight controllers with vital information such as amount of
oxygen remaining in astronaut environmental
control system
• Compute the orbital path of the spacecraft from
• Predict the position of the spacecraft at some time
in the future
• Compute how and when the spacecraft must
accomplish a particular maneuver to change its
orbital characteristics
• Compute navigation information to update the
Apollo Guidance Computer on board the spacecraft
• Process radar range data and let flight controllers
know the spacecraft is on correct lunar transfer
flight path, and if not, what maneuvers are necessary to get it back on the correct path
• Monitor the Apollo Guidance Computer during
reentry and predict the spacecraft landing point.
In addition to these tasks, and thousands more performed during a typical Apollo mission, the RTCC also
has a key role in flight controller and crew training.
To perform the different requirements of the RTCC,
each of five IBM System/360 Model 75 computers are
assigned a different role and the RTCC is engineered so
that these roles can be exchanged at any moment. This
unified set of computers allows NASA to run either two
actual missions at the same ti..1'fle, two simulated mis-

sions at the same time, or a simulated mission and an
actual mission at the same time. Figure 1, The RTCC,
demonstrates the five systems at work in the latter configuration. In the mission configuration, network data
flows into the RTCC from one of the Communications
Command and Telemetry Systems (CCATS)at MCC.
The data are then sent to the :NIission Operational Computer (MOC) in the RTCC, which processes all the
real time processing tasks of the Mission, and the
Dynamic Standby Computer (DSC), which performs
redundancy processing and is ready to function as the
~![OC, if necessary. In the simulation and training
exercise 1 an Apollo trainer, either at the MCC or Cape
Kennedy, is in a closed loop with one of the identical
Mission Operational Control Rooms (MOCR). (The
other lVIOCR is being used for the mission in progress.)
One simulation computer contains an application program which is generating simulated network data; the
other computer is being used as a simulated operational
computer. The fifth computer is a standby computer
for both exercises; however, it is not idle, but performing job shop checkout for future application program development.

The hardware configurations
There are several System/360 hardware configurations used in the development and execution of the computing systems developed for the real time applications
at NASA. Each configuration is supported by a single
RTOS/360 system. The configuration used on each
of the five computer systems in the RTCC itself consists of a System/360 Model 75 computer with a onemillion byte main memory (IB¥ 2705). (See Figure 2,
System/360 Model 75 for :Mission Support.) An IBM
2361 Large Core Storage (LCS) acts as a four-million
byte exte,nsion of main memory as well as a buffering
MCC

Imls ~ I

GROUNORAMR

Is~

SHIP
COMMUNICA liON

75

~,

I

MISSION

COMNre~

~ -r:,:,r~.::75

COMPUreR

~~~·~~-=---~u·
-r::1---~
,~
TI~
/

r8~

I".., I ,~
S!MU ....

MCC

slMU ....reo
IEMOre
SITE

Figure I-The RTCC

75

RTOS

17

areas and features designed to extend OS/360 to form
RTOS/360. First, let's look at the functional areas.
Functional areas of RTOS/360

IlEAL

TIME
INTUFACE

In OS/360, all processing is done in conjunction with
in core storage nor are data for a program a task. A task

SELECTOR

2705 CPU

CHANNEL
6

IMILUONBYT£S

(STORAGE
CHANNEll

Figure 2-8ystem/360 model 75 for mission support

device for retrieving data and programs from the IB2VI
2314 disk drives. The IBl\1 2701 provides a rapid demand response interface to the digital display (D/TV)
system in the MOCR and RTCC. Real time acceptance
and transmission of large amounts of data and control
information are accomplished through the use of the
IBM 2902 Multiplex Line Adapter (::.\lILA). A card
reader/punch, an IB:'VI 1443 printer, three IB.:Vr 1403
printers, two IBM 1052 consoles, and eight tape drives
complete the configuration.
Another System/360 l\:Iodel 75 configuration is used
primarily for Simulation exercises. In addition to those
devices given in the previous configuration, this Model
75 configuration supports a special Apollo Simulation
Processor Channel (ASPC), which receives data from a
Multichannel Demultiplexor and Distributor (MDD),
an IBl\1 2260 Display Device, and an IBlVI 2844 which
acts as a control unit for the IBl\1 2314 disk drives.
Several different System/360 :Model 50 configurations
are also supported by RTOS/360 at the RTCC.

The applications
The applications programming packages used to
perform in these various configurations include:
• The Apollo lVlission Systems
• The Ground Support Simulation Computer Systems
• The Dynamic Network Data Generation Systems
• The Simulation Checkout and Training Systems
• The Operational Readiness and Confidence Testing Systems.
We've now placed RTOS/360 in its environment; i.e.,
the RTCC, the RTCC hardware configurations, and the
RTCC applications used for real time processing under
RTOS/360 control. 'Vith this environment in mind, we
can now turn to a description of the various functional

is a unit of work (programs and data) requiring resources (CPU etc.) to complete its functions. A task
exists only when a Task Control Block (TCB) is established and its location is known to the supervisor
portion of the operating system. The TCB contains
information on such things as pointers to data (I/O),
the list of programs needed to operate under the task,
the priority of the task, etc. In OS/360, the word "multiprogramming" is replaced by "multi-tasking"; however, the meaning is still the same, i.e., many tasks
processing asynch.ronously-through various paths of
logic with the usage of the CPU being switched according to the requirements of the system. (Figure 3,
Some of the characteristics of an OS/360 task are not
functionally oriented toward the types of work required
to be performed by a real time system. An OS/360 task
requires the existence of its creator in order to exist;
i.e., it is dependent on its creator. This OS/360 concept
has been extended within RTOS/360 to include tasks
which are independent of their creators. This causes a
distinction between dependent and independent tasks.
Therefore, an independent task does not require the
existence of its creator in order to exist.
How do the characteristics of an independent task
render it more especially suited to real time systems?
First, a real time system must be able to receive and
process varying data loads rapidly and efficiently. In
RTOS/360, an independent task may be defined for
each type of data to be processed in real time and be

r---

r-::I ---l

I~I

B

PROGRAMS

18

Spring Joint Computer Conference, 1969

available to receive work at all times even if the data
rate is low or random. The major distinction here
between dependent and independent tasks is that the
independent task will continue to exist in the system
when it has no data to process. During this time it is
module executing in order to exist. Each independent task
is assigned an area in main core called a resource table.
This is a private area that can be used by the programs
running under the task. Usually, information is stored in
this area which is derived from the processing of earlier
data. In this way, the task can "remember" information
through periods of dormancy. When data are received by
the system for an independent task, they are sent to the
task in the form of a request. Each request has its own
priority which in turn becomes the task's dispatching
priority while processing that request. The 08/360
task has only the priority of its creator. If an independent task is processing a request when another request is
generated for it, the new request is enqueued according
to its priority. Requests in this queue will be given to
the task as it completes the processing of higher priority
or older requests.
When an independent task becomes active, it is
assigned a unique protect key. This protect key is
given to all dependent tasks created by the independent
task while processing a request. Therefore, a program
running under an independent task or its descendents
will be protected from all programs controlled by
other active independent tasks or their descendents.
Since dependent tasks are assigned the same protect
key as their creator's, all tasks of a job step in OS/360
have the same protect key. This is not practical in
large real time, multiprogramming systems where
many tasks handle various types of data. Independent.
tasks ensure that unique protect keys will be assigned
to unique functions.
Figure 4, OS/360 Task Structure, represents the
logical structure of tasks operating as a job step in
OS/360. This structure is obviously pyramidal in form.
All tasks depend either directly or indirectly on the
dependent upon them, etc. All tasks compete for system
resources (CPU, I/O, etc.), and OS/360 awards those
resources according to the priority assigned to each
Figure 5, RTOS/360 Task Structure, represents the
logical structure of tasks operating as a job step in
RTOS/360. One can see that a new dimension has been
OS/360 while each independent task forms the basis of
another set of tasks which operate independently of and

JOB STEP

ETC.

ETC.

ETC.

parallel to the Job Step Task and each other. This
structure is comparable to multi-jobbing in OS/360
with each independent task analogous to the Job Step
Task of each active job. However, in RTOS/360, all
a ";single job step, and all tasks in that job step are
awarded the system resources according to their dispatching priority.

In the processing of real time data, it was found that
many units of work (tasks) were unrelated to an existing
task or could be performed asynchronously to existing
Therefore, a capability was developed in RTOS/360
for the RTOS Supervisor or user-created tasks such as
message writing and logging of real time input data.
System tasks can be created and returned from within
1/25th the system overhead time required for either an
OS /360 defined dependent task or R TOS defined independent task. This reduction in overhead to perform
required system services in a real time environment
can prove tremendously important during those CPU
critical periods of high, real time, data processing.

RTOS

19

The large difference in overhead is due to the following:
• All control blocks required for a System Task have
been pre-allocated and pre-initialized for efficient
utilization.
_• The entry point for a System Task is an absolute
case for dependent and independent tasks.

ETC.

Queue management
If an independent task is processing a work request
all other requests for that task must be held by the
request. Therefore, RTOSj360 must build and maintain a queue of work requests which are waiting to be
processed by an active independent task. Information
concerning each request is held in a Real Time Queue
Element (RTQEL). (Figure 6, Independent Task and
RTQEL's, shows the logical structure of an independent task and its RTQEL's which are waiting to be pro..
cessed.) Each active independent task will be processing
one work request and that request is represented by the
active RTQEL. All other work requests for the inde~
pendent task are placed in a queue of waiting RTQEL's.
This queue is ordered by dispatching priority and, i~ the
case of equal priorities, it is first-in first-out (FIFO).
When the task completes processing ()f
~ctive
RTQEL, the top RTQEL in the que~ of waiting
there are no work requests (RTQEL's) waiting for the
system for the arrival of new work. All work requests
for independent tasks can be optionally placed under
queue management controls by directing each RTQEL
into a Real Time Queue (RTQ). Each RTQ is created
by a user macro instruction which defines the five
attributes of the queue:

RTQC8
TOPRTQEL

ACTIVE
RTQEL

the

•Its unique name, which identifies the RTQ.
•Its length, which is the maximum number of
RTQEL's to be held in the RTQ before an overflow condition occurs.
• The sequence in which RTQEL's are to be removed
from the RTQ and given to independent tasks for
processing (dispatching priority, FIFO, LIFO).
• The overflow disposition which identifies the
RTQEL to be removed from the RTQ and discarded if the queue overflows (newest, oldest,
lowest priority RTQEL).
• Whether the RTQ is currently able to give
RTQEL's to independent tasks (enabled or disabled).
Figure 7, Real Time Queue Element Control, gives

Figure 7-Real time queue element control

an example of the logical structure of HTQEVs cont.l"()ll~cl
h" on
"' ... ....., ...................... - J ......,........

"RTf)
Tho ~.L
huo
cd·h.ih.,,+.no " .... ;!
~"' ..... ~ •
V
c:..tiUU.&..LuuU\J..::! GtI.1..L\.A..
..L ....... "'"

l'

A+h,,~

vuJ..1.\".I.J.

,,,.'"
vVU-

trol information pertaining to the R TQ are held in the
Real Time Queue Control Block. In the example, the
RTQEL's would be given to the independent task in
order one, two, three, four, if they were not controlled
by the RTQ. That is the sequence of their relative dispatching priorities. However, the RTQ has a FIFO
order attribute; therefore, the RTQEL's will be given
to the task in the order three, one, two, four.
If queue management is not used, the RTQEL's for
independent tasks in the waiting queues can accumulate indefinitely unless the tasks can process their work
requests faster than they are generated. Queue man-

20

Spring Joint Computer Conference, 1969

agement provides additional controls over the requests
in the waiting queues by limiting the maximum number
of RTQEVs held for independent tasks. It can also be
used to indirectly control the system load by not giving
work to an independent task until another independent
The number and structure of RTQ's is determined
entirely by the user. An RTQ can contain work requests
for any number of tasks, and any number of RTQ's can
contain work requests for the same independent task.
The point to be made here is that queue management is
very versatile in that it can be used in many ways to
regulate the system's \-vork flow.

Data and time routing concept
One of the characteristics of many real time, on-line
systems is that they are driven by the arrival of data to
be processed and by the passage of time; i.e., some processing is accomplished by the programming system
because certain data have arrived while other processing
is accomplished because certain reports and displays are
required at specific times. Another characteristic found
in the R TCC system is that much of the processing is
very repetitive; i.e., the same kinds of data come again
and again, representing different positions of the spacecraft or different data points for the various telemetered
activities that are being monitored. In developing
RTOS/360, and the independent task concept, it was
recognized that a mechanism was required which would
examine all types of input data and cause them to be
sent to the appropriate independent tasks for processing. This mechanism is called data routing, and it acts as
an interface between the hardware interrupt servicing
function and the resident nucleus of RTOS/360. Data
routing is a simple mechanism which requires only that
the applications programs execute a macro instruction
to identify the directives to RTOS which link a type of
input data to an independent task. When input data is
received in the system via the 2902 ::\fLA, RTOS compares the data with the current data definitions established by the applications programs. If a match is found,
the data are routed to the independent task that will
process them. If no match is found, the message is discarded. Data routing can also be instructed to accumulate a number of data messages (for example, input
messages) for the same independent task and generate
a request for the task only after the number of messages
specified by the user have been received. In this case, all
the accumulated messages will be sent to the independent task as one request.
As stated above, work requests may be gener,ated
according to the passage of time also. For example, an

independent task may be created to control a program
which updates the position of a space vehicle every
second. The only data necessary to perform this operation is the position of the vehicle a.t the last second and
some orbit and velocity parameters. Since this operation is controlled by an independent task, the necessary
data and parameters can be saved in the task's resource
table while it is dormant (possibly out of main memory).
Since data arrive in a random manner and not nece~­
sarily sequentially or on a time cycle, there is no metllOd
m:ing input data which will cause requests to be generated for the task which must process a request each
second. Therefore, time routing must be used to generate the required results. To use time routing, a problem
program requests that a certain independent task is to be
activated Bot a certain time or cyclical when a given
delta time has elapsed. RTOS/360 routing and time
management functions will then activate the independent task at the time requested. If the activation is to be
continuous, it is left to the problem programmer to
request the activation's end.
The data and time routing functions (which operate
under a system task) have been constructed so that
their functions can be combined. For example, it is
possible to request the accumulation of data under
data routing with requests generated by time routing
on some specified interval. Each request generated will
contain all the data accumulated during the last interval. Another way of using the combined functions is
that messages can be accumulated over a timed interval and request generated either when the interval expires or when specified numbers of data messages have
been received in the system, whichever event occurs
first.

Time management
The System/360 ::\10del 75 computers used to support X ASA's real time applications are equipped with a
special high-resolution (lOJ,Ls accuracy) G::\1T (Greenwich ::\lean Time) clock and interval timer. In order to
provide support for this special hardware, a time management supervisor was developed for RTOS/360 which
functions in parallel with the standard OS/360 time
management routines. The time management supervisor
maintains the system thne in a job step pseudo clock,
and it controls the setting and interrupt processing from
the G::\IT hardware to keep time and service interval
timeout requests from the routing function and other
areas of RTOS/360. Additional functions have been
added to the time supervisor which provide optional
controls over the job step pseudo clock.

RTOS

It was necessary to develop a Real Time Input/Output Control System in RTOS/360 which would service
real time input/output requests rapidly and efficiently,
perform special device-dependent data manipulation,
and support the special real time input/output devices.
at the RTCC. RTIOCS is comprised of five logical
parts discussed in the following paragraphs.
A real time access method performs device-dependent
data manipu.lation and sends output messages to the
special real time output devices at the RTCC. In addition, standard sequential System/360 output devices
(2400 tapes, 1403/1443 printers) may be substituted for
the special RTCC devices simply by altering the UXIT
designation on cards in the user's input job stream. The
real time access method is also used to control the reading of information from the IB~.vI 2250 and 2260 graphic display units. This section of the real time access
method functions closely with the graphic display
attention control routine, and together, these two areas
of the real time I/O control system provide RTOS/360
users the ability to read information from the IB::'v12250
or 2260 devices. Writing on the display devices is controlled by the real time access method alone. In this
case, the displays are processed as normal real time
output requests.
The real time interrupt servicer and start-stop input
routine provides software control over the real time
input devices at the RTCC. The interrupt servicer
passes input data to the data routing and logging functions in RTOS/360. The start-stop input routine accepts data whenever an active routing request is present for each particular device. An OS/360 OPEN" /
CLOSE is not required.
The digital display control routine provides centralized and simplified control of the special R TCC devices
called digital television displays (D /TV). This control
program is entered by user tasks signaling the change
of status in one or more of the displays, The current
status of the display is updated by the control routine,
and it then gives control to the real time access method
which updates the actual hardware display.
The digital/TV display control routine provides a
software support for the Philco digital/TV display
system at the RTCC. This program services all digital/
TV display requests, maintains information indicating
which displays are currently being viewed and the con8ol,.~ which is viewing them, controls the dynamic alloca·
tion of the digital/TV channels, and generates work
requests for the user tasks which create and update the
actual numbers or figures wit: ':'1 each display.

Data management-data tables
The large amounts of data required to be accessed by
the Mission Systems at the RTCC during spaceflights
prompted a careful evaluation of the OS /360 Data
i\1anagement methods. First, it was found that
although the methods were adequate for the environments for which they were designed, the RTCC real
time environment nroduced a llnim]p, ~it.1Hdi{)n in urhinh
writing data. Second, there was no efficient means to
enable RTOS independent tasks to share data. Third,
due to the critical importance of data in the system, a
means to ensure data integrity and consistency had to
be developed. Finally, an easy method had to be developed to allow users a simple method of reading and
writing data, thereby eliminating the need for complicated coding techniques. The resolution to these
RTOS data management problems was the development of control programs to support data tables.
Data tables are blocks or arrays of data maintained
on direct access devices (2314 disk) in the partitioned
format. (Data tables are treated as members of partitioned data sets.) Each datg table is identified by its
unique EBCDIC name and is defined by its block size
and number of blocks. A data table generation program
employs these parameters in allocating direct access
space for each table, providing the controls required to
access it, and storing its initial data in the direct access
space provided.
The main utility of data tables is the additional
facilities provided by the data table control programs.
Here, the standard OS/360 Data i\1anagement OPEN/
CLOSE logic has been eliminated, thereby increasing
the speed at which data can be read or updated. Data
can be used commonly by any number of different
tasks. The data table programs provide methods of
"locking" data tables which ensure data integrity and
consistency by delaying any tasks which try to write
into a data table until the table is "unlocked." In this
way, various portions of a table can be read through
different requests and the user is ensured that no update has taken place between requests.
...

.

_____

~

Real time input/output control system
(RTIOCS)

21

___

_ _ _ _ _ ....... _

..................

,

...... .&..&.""',1,1

Functional arear-Summary
Briefly, we placed RTOS/360 in its environment and
outlined the major modifications made to OS/360 in its
functional areas of Task l\Ianagement, I/O l\Ianagement, Time }lanagement, and Data Ylanagement to
extend it for real time spaceflight control. In addition,
we have shown the addition of two new functional
areas, Routing and Queue l\lanagement, which add
additional controls necessary for RTOS/36G to effi-

22

Spring Joint Computer Conference, 1969

ciently perform the strenuous requirements of real time
processing. However, RTOS/360 development does not
end here. Experience had taught us that many additional features and facilities would be necessary in an operating system to process and develop real time programming packages. These features are outlined in the following section.

2314 DISK

Special features and facilities of RTOS/360

Large core storage support
The IB1\1 2361 four-megabyte Large Core Storage
(LCS) is supported in three modes of operation by
RTOS/360. The first mode is to use the LCS as a means
for imprO'lJing job shop operations~ This is accomplished
by: (1) using the Le8 as assembler work space instead
of tapes or disks, thereby improving assembler execution time; (2) using the LCS as work storage for compilers to allow larger compilations to be performed in
main memory, thereby decreasing compile time and
increasing job throughput; (3) placing job control information on the LCS, thereby job throughput is increased; (4) using the LCS as a system residence device
for nonresident operating systems programs, thereby
The second mode is to use the LCS as an addressable
extension of main 'Yne'Yfwry. This is especially applicable
to large applications packages being developed on the
one-half megabyte main memory System/360 Model
50's.
The third mode of operation was initiated by the fact
that it was known from the initial development of the
Apollo mission application package that the package
would exceed the capacity of main memory and the
LeS. (The Lunar Landing ~ii88ion p.xceeds six megabytes.) Therefore, an LCS algorithm was developed
that dynamically allows the funneling of data and programs into main memory (see Figure 8, Allocation of
1:Iain l\:Iemory). Basically, this dynamic LCS allocation means that the LCS is used as a high-speed dynamically changing residence device for load modules and
data tables which are heavily used but which cannot be
contained in main storage for the duration of the need
for them. A load module or data table will be put on the
LCS when it is requested and is not presently on the
LCS. As long as the load module or data table is frequently used, it will be retained on the LCS; when it
appears that the load module or data table is no longer
required on the LCS, it may be replaced with another
It is possible to identify load modules and data tables
with such low response requirements that they need
never he placed on the LCS, i.e., residence on a direct
access device is sufficient. Conversely, some load

4 MEGABYTE
LCS

1 MEGABYTE

MAIN
MEMORY

Figure 8-Allocation of main memory

modules and data tables are very critical; therefore,
these may be permanently "locked" on the LCS.
To support the third mode of LCS operation, a Large
Core Storage Access Method (LeSAM) was developed
to provide the R TOS control program with a facility of
moving blocks of storage from the LCS to main storage
or from main storage to LCS. LCSAM will perform the
data move either with the normal System/360 instruction set or by performing a.n I/O operation through
the storage channel, depending on the size of the block
of data.

Two problems encountered in large real time systems
required the development of a feature in RTOS/360
called Real Time Linkages. The first problem pertains
to the fact that the system library subroutines referenced by standard OS/360 load modules (programs)
must be included within each module when built by
the 08/360 linkage editor. This requirement often
results in a large duplication of system subroutines
present in main core at one time. This duplication can
be very wasteful since the amount of main core available
is reduced, and the amount of time required to load a
module is increased, and the amount of space required
to hold the module on a direct access device is increased.

RTOS

modules to reference common resident reentrant library
subroutines.
A second problem pertains to the fact that certain
constants (such as the diameter of the earth) used in the
real time missions must be identical to all programs and
be under close control by the coordinators of the total
application mission system. The real time linkage
mechanism solves this problem.
By holding task priorities in a common parameter
table, the system can be "tuned" by simply changing
those priorities found in that single tab]e rather than
performing a reassembly of a large number of programs.
Real time linkages resolve all the external references
that a load module cop.tains for system subroutines or
common parameters when the module is loaded into
core for execution. The system subroutines and common
parameters are loaded into main core during real time
initialization and held there for the duration of the run
(job step). Therefore, the addresses of these routines
and parameters can be inserted into the appropriate
external address constant fields contained in a module
as it is loaded so that the cost at execution is no greater
than if they appeared in the load modules in the norma]
fashion.
Logging

In most real time applications, especially those which
require post-run analysis, it becomes important to perform some type of recording activity which saves the data
received, transmitted, and processed by the system.
This feature is referred to as logging in RTOS/360.
Logging automatically records all real time input and
oatput messages on magnetic tape. Also, a macro instruction has been provided which will write problem
program generated information on the log tape if an
application programmer wants a record of selected
data or processing results.

Simulated input control
One important factor, which is almost essential in the
of real time systems, is the ability to send
simulated input data to the applications programs. In
real time environments, it is impossible to employ or
always obtain the necessary equipment to produce
"live" data for all applications program checkout. To
solve this situation, RTOS/360 contains a feature
termed Simulated Input Control (SIC), which allows
the uer to run his development programs with simulated input data in an attempt to find most interface
proble'llS between modules and programming errors
prior t ) final checkout with actual data.
The SIC programs which operate as part of RTOS/
develop~ent

23

360 obtain the simulated input data from cards or tape,
or both. All data have a time of receipt associated with
each data message which allows SIC to send each one to
the data routing function when the time of receipt on
the message equals the current internal computer time
(job step pseudo clock time). This in turn generates
requests for independent tasks which will process the
data as if they were a real time message. For convenience,
the SIC package has been designed so that magnetic
tapes produced by the logging function can be used as
SIC input sources without special editing. The SIC
programs will pass over all output messages on the log
tape and send only the input messages to the data
routing function.

Fastime
Another special RTOS/360 function that has become
very valuable at RTCC is Fastime. Fastime is often
used in conjunction with SIC when testing new areas of
the user's system. Its only function is to step the job
step pseudo clock when there is no system activity.
Fastime operates as the lowest priority task in the
system so that it is entered when there is no other
activity. If the Fastime program running under this
task determines that there is no further work to be performed before the next routing request, the time management function is signaled to step the pseudo clock to the
time of the next routing request. One can see that many
hours of computer time can be saved because the system
will not wait for the actual passage of time to generate a
time queue if the system becomes inactive, as time
queues will be generated immediately when idle C;PU
time occurs. This function is further enhanced in SIC
runs because the SIC programs use time queues in
determining the exact moment a message is to be sent to
data routing. Therefore, in a SIC run, time may be
stepped to the time of the next data message. This message will be immediately sent to data routing and then
to a task for processing. In this way, simulated data
messages can be given to tasks as fast as the tasks can
process them, thereby reducing the actual computer
time to Mst new programs. By using Fastime with SIC,
the checkout of an 80-minute orbit can be performed in
about 10 minutes. Fastime and simulated input control
have no place and are not used when the system is
performing its real time production work. These functions are used only in testing new versions of the application systems.

Display- formatting language
There is a large variety of display devices at the
RTCC that have different internal format requirements.

24

Spring Joint Computer Conference, 1969

There is a high probability of change in these devices,
their internal formats, and the displays shown on them.
This changeable character of the display devices increased the need for a series of display formatting
programs. To meet this need, RTOS/360 programmers
designed and developed a versatile display formatting
language (DFL) which isolates the applications programmers from the unique characteristics of each display device and the internal format changes resulting
from modifications to those devices.
The display formatting process consists of two steps.
First, the user must define his display by assembling the
DFL format macro instruction with his program. The
format macro instruction expands into a "format statement" or character stream when assembled.
This character stream provides the display format
controls used by the DFL conversion routines in the
building of an actual output block for the desired display. During execution, the applications programmer
can prepare output data for a display by executing the
DFL conversion macro instruction. When the conversion routines complete processing and return control to
the calling program, the data are in converted form and
ready to be sent to the device specified by a particular
control card (DD card) in the job control language for
the job step. The user can subsequently output the
data to the display device via the real time access method portion of the real time I/O control system. The conversion routines build output blocks for a particular
device. The device is specified by identifying to the conversion routines the DD name of the DD card for the
data set. From this information, the conversion routines can identify the particular device whICh is to receive the converted data and activate the appropriate
conversion modules. This means that the DFL package
provides complete device independence among those
devices supported (see Figure 9, Device Independent
I:ispla.y Language).
Through the simple alteration of control cards in the
mer's job stream, the user can alter his display devices.
This feature can be very valuable when the actual display devices are not readily available. The applications
programmers can code and debug their display programs using common or standard devices, such as IB:;VI
1403 printers. When t.he display devices become available, the programs will be ready for actual production
work after changing the appropriate control cards.
The d3vices currently supported by the DFL package
are printers: IB.M 1403, IBNI 1443; display devices:
IB1\'J 2250, IBl\l 2260, Raytheon l\lCVG, Philco
RTCC Digital/TV; plotters: RTCC X-Y Plotboards,
RTCC Scribers; and Teletypes. The device independence feature and some of the devices supported by D FL
are also shown in Figure 9.

FORMAT STATEMENT

RTPUT

~

®

II

I

ITPUT

RTPUT

)

aBJ

ItAYTHEON COMMNY

MCVG

RTPUT

I

!

!

\

\

HELP

--

-\
IBM 2250

DISPLAY UNIT

PHILCO COlPOIATION
TV

Figure 9 ---Device independent display lang uage

Fail-safe programs
Because of the critical nat.ure of real time manned
spaceflights, it is extremely important that RTOS/360
be able to process abnormal conditions so that it is
virtually impossible for a portion of a flight to go unmonitored because of a software, data, or hardware
failure. Four areas of software support have been developed and included in R TOS /360 to meet this need:
selectover, high-speed restart, error recovery, and time-out.
Selectover is performed by exchanging the operational roles of the :\'Iission Operational Computer (MOC)
and the Dynamic Standby Computer (DSC) without
interruption to the input/output data on the real time
interfaces. During Selectover, the integrity of the mission outputs is maintained.
The Apollo mission support system operating under
RTOS/360 in a System/360 lVIodel 75 with one megabyte main storage and four megabytes LCS, may be restarted in less than 10 seconds on an alternate Model
7!> computer system which may be idle, processing job
shop, or performing real time test operations. This is
accomplished through IBIVI Channel-to-Channel Adapters (CCA) which link each comhination of two out of
five machines. An Initial Program Load (IPL) sequence
is generated from a remote console to the proper CCA
on the operational computer system, simultaneously

RTOS

enabling the CCA path between the two systems. A
special IPL hardware modification enables a restart
even if the machine to be restarted is in manual state.
All of allocated storage is then transferred over the
CCA from the operational system to the selected standby system before resuming in the restarted system. A
similar restart can be performed from magnetic tape by
creating the tape on an operational computer and
carrying it to the standby computer for IPL. (This
The error recovery package of R TOS allows the
system to recover from errors due to the program errors,
hardware-malfunctions, or abnormal conditions arising
within the system itself. As recovery occurs, appropriate messages and recommendations are printed
which indicate the current status of the system. A part
of the error recovery activity includes device switching,
i.e., if one I/O device fails, RTOS will automatically
(or by external signal) select another device of that
type. When the control program detects an error condition, an end-of-tape, or when a user requests a device
switch, Alternate Device Support (ADS) is invoked to
locate an alternate unit of the same device type and
perform the necessary adjustments to allow the alternate to replace the primary device. RTOS/360 programs contain built-in logic which allows recovery
from a situation where an alternate is unavailable. The
computer operator is informed on the console typewriter of all device switching operations. Currently,
device switching is provided for the 1052 typewriter,
tapes, printers, and 2314 disks.
Certain I/O device failures are such .that an interrupt to the CPU is never generated to signal the completion of the I/O operation or an error condition. A
software timeout facility exists in RTOS/360 which
will check once per second to determine if an I/O operation has not completed in a period of time which is
normal for the particular device. When such an occurrence is detected, the I/O operation will be purged and
appropriate messages will be printed. Normal use of the
device will be attempted on subsequent requests.

Since the former was far too expensive, a programming
system was developed specifically for RTOS/360 that
allowed all the peripheral functions normally associated
with off-line support computers to be performed in the
single l\10del 75 CPU. The system was called the Houston Automatic Spooling Priority (HASP) system.
HASP acts as a dependent task under RTOS/360 (cohabitates in a single CPU with other RTOS/360 operations) and uses small amounts of prLlllsry CPU thne to
operate the peripheral functions. These functions include transferring the job stream to direct access to
await execution, collecting job output on direct access,
and printing and punching job output from direct
access following job execution. Jobs awaiting any stage
of processing (print, punch, or execution) are queued on
a priority basis so that the effect of a true priority
scheduler is gained not only for normal job execution
but for associated peripheral functions as well.
A complete "warm start" capability also exists in
HASP so that untimely interruptions of the system will
cause no loss of job input or output queued for processing under HASP. Sophisticated operator communications exist that provide control over the number of
input job streams, the number of output devices, and
the order of job executions.

Background utilities
There are many utility functions in any data processing operation, especially a system which employs
disks, that must be performed. These include: dumping
direct access volumes to tape, restoring direct access
volumes from tape, copying and comparing tapes,
labeling tapes, changing volume serial numbers on
direct access devices, etc. This is especially true when a
large variety of applications systems are under development as in the RTCC. Utility operations usually require the complete dedication of the computer while
they are being performed. This dedication was found to
be unrealistic from both the cost and time required;
therefore, all utility operations were designed so that
loon
tney COUla operate III --oacKgrounu-- unuer 1\,.1VO/OUU
control as dependent tasks. These background utilities
execute asynchronously with the normal job processing
and can be initiated and terminated by the computer
operator at the console typewriter.
.'1

Houston automatic spooling priority system
The tremendous development effort required to meet
critical mission schedules requires that the computer
systems be used to the maximum at all times during job
shop operations. It was known from the onset of Apollo
development that either a large number of "peripheral"
off-line support computers would be required to perform such operations as loading jobs for execution and
printing the vast amounts of output (usually large core
and LCS dumps) or the Model 75 computers would
have to be used to their maximum CPU availability.

25

,

,

I ·

tll

1

",

1

T"'\rnACt

Job accounting system
With the large number of computers being used by a
vast array of development groups, it was found tbt
the R TCC required a means to report accounting and
system measurement data. This was accomplished by
the inclusion of a set of programs called the Job Ac-

26

Spring Joint Computer Conference, 1969

counting System (JAS). Since all computer operations
at the RTCC are under control of RTOS/360, JAS
automatically generates, through punched cards, a
data base for three types of reports which are valuable
for both the accounting and system measurement purposes. The three report types are:
• A Job Shop Analysis Report which provides job
mix and computer system performance statistics.
.A Computer Utilization Report which is used to
charge compute! time to user.
• A Management Report which provides information
on program development costs through statistics
on the use of the computer by individual programmers.

r-----------------------~-l
MASTER
SCHEDUliR

~~TIATOR
TERMINATOR

JOt INITIATOR
TERMINATOR

JOt INITIATOR
TERMINATOR

~~~:SOUND
JOt

HASP
SYSTEM

L ________________________ J

Statistics gathering and modeling activities
Each Apollo mission presents the RTCC with a
unique set of processing requirements. For example,
real time data sources may change in number, arrival
rate, or message size. These and other such factors
cause changes in the performance of real time computing
systems. So that changes do not cause the systems to
perform below acceptable limits, performance of current
systems is measured and that of future systems is
modeled. 2
To measure the performance of a real time system
and monitor its execution, a comprehensive Statistic
Gathering System (SGS) was developed. SGS is a program and not a hardware device attached to the computer. It provides an accurate means of measuring
performance on RTOS/360 by collecting:
• Timing information on control program services
and application programs
• Percentage figures showing how definable system
functions use the CPU resource
• Elapsed time figures showing task response time in
a multiprogramming environment.
The SGS design for RTOS/3oo is patterned after an
earlier version used with the Gemini 7094 Executive
Control Program.
The Real Time Computer Complex is not a project
that is blessed with a firm definition of mission requirements. Results of each mission impose requirements for
future missions and, thus, levy new demands for real
time support. It is essential to the orderly development
of RTCC real time systems to anticipate problems in
computer system configuration or system program
design that could impair the success of future missions.
To analyze future system performance, RTCC uses
models written in the language of the General Purpose
Simulation System (GPSS/3OO).

Information obtained from SGS is used in these
modeling activities.

Multi-jobbing in RTOS
Within this paper, it has been shown that RTOS/360
in the real time environment is a multi-jobbing system
in the broad sense; i.e., a real time job step can be processing several independent paths of logic (independent tasl{s vthich could be termed jobs since the)T sb...are
the system resources) at the same time the multi-tasks
are performing, and the background utilities and HASP
are also vying for the CPU. However, after careful investigation of statistics obtained from SGS and JAS, it
was found that large amounts of time were still spent in
the I/O wait state, and that the full computing power
of the System/3oo Model 75 was not being used. Therefore, the final feature to RTOS/360 was developedreal time mUlti-jobbing under RTOS/3oo control.
The RTOS/360 multi-jobbing differs from the OS/360
multi-jobbing in that RTOS/360 does not require partitioned memory nor, of course, a fixed number of tasks.
An illustration of RTOS/360 multi-jobbing is shown in
CONCLUDING REMARKS
The development of real time control systems for
spaceflight programs has been an evolutionary

~~ ASA's

RTOS

process. For the Mercury Program, IBM devel?ped the
Mercury Monitor, which performed only real tIme control and occupied only a small portion of an IBM 7090
computer. Next came the development of the real time
Executive Control System for the Gemini program.
Executive occupied about 13,000 words of an IBM
7094-11 computer. The third system in this evolutionary
process was the RTOS/360, which is presented in this
paper. RTOSj360, a 150,000 byte system, was the first
system not only containing real time control facilities,
as in the Mercury Monitor and Executive, but also
containing the complete gambit of operating system
functions (assemblers, compilers, job shop processing
techniques, etc.).
Today, RTOS/360 has not only successfully su~ported
several NASA Apollo Missions, but because of l~ real
time facilities and special features, coupled with the
current OS/360 System, is being used by other installations outside the RTCC to meet their special require-

27

ments for a real time operating system.
ACKNOWLEDGMENTS
I wish to acknowledge the contributions of all those
members of the RTOS departments whose documents
and comments aided in the preparation of this paper.
Special thanks go to Ray Strecker and Ken Adams,
whose technical documents on RTOS were a major
source oi iniormaiion. For ihe encouragement to write
the paper, I wish to thank W. D. Pollan.
REFERENCES
1 J JOHNSTONE
A real time executive SY8tem for manned 8paceflight
Proc F J C C 1967
2 W STA...~LEY H H E R T E L . ';
Statistics gathering and simulation for the apollo re4l ti1iU
operating system

IBM Systems Journal Vol 7 No 21968

by JOHN T. GILMORE, JR., Chairman of Session
Keydata Corporation
Watertown, Massachusetts

For purposes of background and personal introduction, I would like to begin by stating a few facts about
Keydata and its services.
Keydata Corporation was founded in 1959 by
Charles Adams and myself and was originally called
Adams Associates. Until 1965, when we became the
first to offer time-shared business data processing
services, our main activity was the design and implementation of real-time, graphic display, and online process control systems. That activity is now
being carried on by our Keydata Associates Division.
The Keydata system, centered in Watertown,
Massachusetts, consists of a private dedicated teletype network that extends as far west as Missouri and
south to Delaware. The primary concentration, however, is in New England and Metropolitan New
York. Three kinds of computers are used. The
UNIVAC 494, utilizing Fastrand and high-speed
fixed-head drun1S, is the time-shared processor and
wil1 be duplexed with another 494 before the end of
this year. Honeywell DDP-516 computers, used as
teletype line monitors and message concentrators,
are strategically located geographical1y within the
network to minimize communication costs. An IBM
360 Model 40 is the batch-oriented off-line processor.
Based on the kinds of service we are now providing,
the system has a capacity of 800 to 1,000 lines with a
response time of less than two seconds. Our present
630,000 records or 92 miHion characters. Our basic
services are distribution accounting and accounts
payable. Certain services are used by a small number
of subscribers and other services are under development.
We call our system a "business computer utility"

because it provides the businessman with computer
power and programs that serve as an efficient tool in
operating his company. Like the telephone and
electrical utilities, we provide our services through
on-line tenninals located at his place of business and
operated by his employees who are trained in his
company's activities and who are not-and need not
be-specialists in the service provided by the utility.
Right now, the average businessman would be
satisfied to have his conventional data processing needs
fulfilled without costing him an ann and a leg and
confusing the hell out of his employees. However, once
this is accomplished and he realizes what else is possible,
he'll roar like a lion. Will we in the computer field be
The businessman has as tough a problem to solve as
the scientist-perhaps even tougher if one counts his
variables and unstable conditions. His basic problem
is his data base. He cannot watch it or experiment with
it as easily as his brother scientist or engineer can. More
his data base is measured in several days to weeks-by
which time it is far from being current. However,
modern co~puter technology and on-line communication techniques will enable him to keep his data base
current and available in milliseconds. With this kind of
luxury he could rapidly become as sophisticated a
computer user as his scientific friend. When he does,
and when there are many like him, the impact on the
business community will probably cause the operations
research textbooks to be rewritten and the economists
to take a second look at their crystal ball!
What it boils down to is this. On-line business applications, whether on-line to one's own computer or to a
computer utility, will provide a dynamically updated

________________________________________ 29 ______________________________________

30

Spring Joint Computer Conference, 1969

data base. Once that occurs, the businessman will be in
a position to request the initiation of various operations
either at will or automatically. This will provide him
and his employees with the timely information essential
to the efficient operation of his company. Changes in a
data base will automatically cause reactions to other
parts of the same data base and, through the use of
communications, changes to other data bases, etc.
For example, in performing its invoicing and inventory control function, our system signals the terminal operator when a re-order point is reached based
on the quantity just processed in the invoice being
prepared. The re-ordering of the item is now being done
in the conventional manual way. But the time will soon
come when the computer will communicate directly
with vendors of the item, compare prices and delivery
dates, and order a specific forecast-calculated quantity
of the item from the vendor selected. The same reorder example might instead trigger a production
order message to another terminal in the plant or
perhaps directly to a process control computer. The
examples could go on and on, but the main theme
assumes a data base that is being dynamically processed.
Among the questions I feel the panel should discuss
are:
• What are some of the problems in dynamic data
base systems? What protection must be provided
to safeguard information? What kind of reliability
and availability criteria should there be? What
kind of back-up procedures should be employed?
• To the businessman, each successive stage of developing what for him will be the optimum system
has to be economically justified. V\rhat are some oi
the major impasses? What are the intermediate
payoffs? What kind of time period are we talking
• What industries or job groups may suffer from a
drastic increase in on -line processing? What government intervention, if any, can be anticipated or
perhaps urged?
.l\-fost of us in the computer field see the computer
and its p()wer as a valuable tool to the business
community. Are we missing anything? For example, will it cause a major cleavage between the
unskilled or semiskilled and the bright workers and
managers who will use the computer tool to run the
plants and offices? Will the leisure class ironically
consist of the rich and the unemployed even more
so than it does today?

by CHARLES T. CASALE
Paxon Corporation
Sunnyvale, California

If we look at business applications which are truly
on-line today, we see far fewer than were predicted four
or five years ago when time-sharing and on-line systems
were promised as ultimate solutions. Why is this so? I
believe there are several reason, intertwined, which
have in tum caused secondary effects. I would like to
review some of these briefly.

On-line as a philosophy
To some, on-line reaches the proportions of a religious
belief: it is good for everyone, there are ceremonies,
there are the articles of faith, and there are the missionaries and prophets. In fact, there are large numbers of
people who simply reject onlinism or say that they
simply don't need it. At least not now.
Much of the reason for apparent slippage in implementing on-line systems comes from the earlier
prophetic statements of dire need. If dire need is "assumed, then it can be reasoned that an economic
solution is not far behind.
The degree of need

There is real need for on-line, "instant verification"
of credit cards at gasoline filling stations to capture
voided or stolen cards. So far, we have no systems
filling this need since we don't need the systems badly
enough to pay the current price. The technology is
there. On the other hand, the benefits of having quick
retrieval of airline seat availability are worth the cost
to the airline. So we have large airline seat reservation
systems .
How loud are the demands for on-line inquiry of the
weekly payroll file? Or accounts payable? Or for change
in status of major sales prospects? The promise of
"instant data" in management information systems is
proving illusory in many cases; the information just
doesn't change that frequently, or to that degree, to
warrant the expense and complexity of an on-line
system.

The transition period
The transition from an "old style" manual system to
a fully on-line automated system is an undertaking as

enjoyable as crossing the Italian Alps by elephant in the
winter. It can be done, but the participants and bystanders are loath to ever repeat the experience, at
least in the foreseeable future. Hardly an issue of the
popularized computer magazine 'goes by without at
least one glamour or horror story of the transition pe-riod. These periods take time, rub nerves raw, chew up
valuable resources that others think could be used elsewhere, and are full of surprises. When finished, the
accomplishment is indeed impressive ... so much so that
we are reluctant to make any changes to the new system. This brings us to some other matters:

Who is going to do the system?
First, there is the jurisdictional problem. Secondly,
there is the resources problem. Where do we find skilled
people to plan and implement the system, who will
maintain it, how will they explain it to its users? The
shortage of skilled practitioners need not be restated.
The shortage is responsible for delays in putting
business systems on-line. Once installed, how do
we keep it current? With what tools? Can the system
grow gracefully, or must it be abandoned when it gets
modestly larger?

31

Central storage costs and central computer hardware costs
These continue to decrease relatively, and each year
sees a lower threshold of economic entry. However,
logic and electronic costs are decreasing at a faster rate
than storage costs. Consequently, main frame manufacturers are adding more logic to a given storage size
to do a more sophisticated job. Weare beginning to
see parts of software systems being hardwired into
Conlputer-s as a cheaper way to get the job done. This
same phenomenon of rapidly declining logic costs has
given rebirthto the mini-computer.

The mini-computer
What it lacks in capacity it makes up in muscle. With
storage being the majority hardware expense and more
logic being condensed onto one semi-conductor chip,
the present types of mini-computers will tend to become off-the-sheJf components marketed by distributors
and produced by the memory houses. What this means
to on-line business systems is smaller subsystems
operated relatively independent of the parent data base.
Weare already seeing specialized subsystems based on
"standard" mini-computers.

Specialized subsystems

Profits and returns
After the fact, what are the real bottom-line profits
that the system gives me? Can I show a return on this
sizeable investment comparable to my other business
investments? Are the marginal benefits being used to
justify more than their proportionate costs?

Where do we go from here? What are the
trends?
I t would be useful to look at the major influencing
factors that will accelerate or impede progress towards
more and better on-line business systems. Some of
these are in conflict, others are synergetic.

Data transportation costs
For a given quantity of data, rates decrease slowly.
For the same costs, the quantity of data that can be
pumped over common carriers increases much faster.
Consequently) the threshold of economics for cost
justification remains reJatively constant; but once
justified, the marginal costs of transmitting additional
data are small. This will be changed when the full
impact of the Carterfone decision is implemented. The
result will be a lower threshold caused by reduced
termination costs.

Data acquisition, data distribution and highly structured repetitive tasks can be performed more cheaply
with specialized subsystems than by a general-purpose
system. This is true only because of the continued decreasing cost of logic and storage. We have seen the
success of this in the keypunch replacement area, where
no loss of system capability is experienced in using keyto-tape devices instead of the more generalized and
flexible keypunches.

The programmer gap
::vruch has been said, and much is being done about it.
there just aren't enough of them around to
get done all of the jobs that are on the drawing boards.
And it seems that the gap doesn't close as fast as many
expect.
~1eanwhile,

Programming costs
These are increasing because of personnel shortages
and because there is a Parkinson effect about any productivity increase made in programming. While today's
programmer can produce (via higher-level languages)
ten times what he could ten years ago, the job is enlarged to an even greater multiple. Documentation demands are considerably greater and productivity increases have been significant.

Spring Joint Computer Conference, 1969

32

Consequences of these trends for on-line business systems.

Large data bases will continue to prosper and flourish,
as will their extensions, the time-shared terminals. In
addition to this, an entire sub-industry will mushroom
based on successful exploitation of the disparity in
trends among decreasing hardware costs, rising software costs, and relatively level transportation costs.
The results will be specialized subsystems, ranging
from a few thousand dollars to several hundred thousand dollars. They will be application-oriented, limitedpurpose and highly cost-justifiable.

and examine the actions taken to date as a basis for
distinguishing trends and anticipating future policy
and legislation. The intelligent businessman today cannot afford to become fully preoccupied with hi~ own
plans and problems in a framework shaped solely by
competitive forces. The role and influence of the federal
government should be studied and understood.

by WILLIAM M.

ZA~I

Allston, Yrassachusetts

by MARTIN GREE~BERGER

The Johns Hopkins University
Baltimore, Maryland

The federal government is destined to play a kev
role in the future development of on-line business
tems and the stn1.cture of the new industry grov.-mg up
around them. Six points of contact already are evident:

sy;-

1. Anti-trust action (real and implied) as in the

current cases against IB~1 and AT&T.
2. Inquiries on the practices and policies of the

3.

4.
5.

6.

conununications conunon carriers as in the recent FCC inquiry on the relationship between
computers and conununications, and the now
appointed by Lyndon Baines Johnson.
Hearings on privacy and associated rights of the
individual as conducted last year by Congressman Ga1lagher and Senator Long.
Legislation on copyrights and other possible
mechanisms for protecting computer software.
Encouragement of standardization and economy
measures as in the Brooks Bill alid intended
activities by the National Bureau of Standards
the General Services Administration, and th~
Bureau of the Budget.
Direct and indirect subsidies of development
through research grants, purchase of services
and equipment, and support of education.

A great deal of government participation and in.has go~e on in the past year, and every
IndlCatlOn IS that Its pace and scope will intensify in
:ol:e~ent

On-line computing systems are a relatively recent
development in conunercial computer technology.
Most of the experience to date with the use of such
systems has been gained at universities, large governmental organizations and a few pioneering businesses
like American Airlines, Westinghouse and Keydata
Corporation. Today, from the literature and recent
announcements of computer plans, it appears that online systems are ready to be implemented in many
organizations to perfonn a large variety of tasks.
There are experts predicting that by 1970 the majority
of computer systems sold win be perfonning some online functions. Huge growth is expected to occur in
computers capable of operating on an on-line or timeshared basis.
Much of the growth in usage of on-line systems will
be economically justified. The on-line systems have the
pot~ntial to dramatically change business data processmg and the manner in which business will be conducted. On-line business systems can be used to improve decision making, the operations of a business and
customer service. Certain aspects of decision making
can be improved with on-line systems because a problem
solver is 2 ble to test on-line to the computer several
alternatives and get immediate feedback of results.
The interaction of a problem solver with a computer may
provide an understanding of a problem and its solution
that is not possible to achieve with the long delays in the
computer-generated answer cycle of systems without
on-line capabilities.
Operations of a business improve with on-line computer systems because the reduction in data processing
delays can be used to reduce inventories, provide more

efficient distribution systems and more effective production schedules. Westinghouse has implemented an
on-line inventory control system for its distribution
network, and was able to close seven warehouses and
dramatically reduce the level of inventory required.
On-line systems have the potential of improving customer service by insuring a complete stock of goods and
enabling faster response to customer requests. American Airlines was the first to use an on-line passenger
seat reservation system. The company expected increased passenger sales to result from its ability to process customer requests more speedily and accurately.
While much of the growth of on-line computer use
will be justified, a significant portion of on-line use will
not and cannot possibly be economically justified.
Many companies will repeat the same mistakes in
switching to on-line computers that were made when
computers were first introduced into their organizations. Many companies could not economically justify
their original computers, but they purchased them
because:
• their competition had a computer and they felt
they could not compete successfully without one;
• the companies wanted to keep up-to-date with the
latest management techniques, and
· the computer offered many subjective advantages,
Companies, because of the potential advantages of
on-line systems, are in danger of being caught up in a
whirlwind of unnecessary and uneconomical change.
While on-line business systems can be extremely
valuable, this value is not automatically achieved nor
is it applicable to every business situation. Before any
company decides to implement an on-line system, it
must examine the economics of the specific applications;
otherwise, expensive mistakes can be made. The reasons
for this follow.

33

On-line computing systems do not automatically
improve operating performance. They generally increase the speed of information flow in an organization,
but if this speed is not used or needed it has no economic
value. On-line systems will generate operating savings
only if the reduction in information delays are meaningfully integrated into a management process, and if
the reduced information delays can improve a company's
operations.
On-line systems do not necessarily provide a marketing advantage vis-a-vis competition which does no
use such systems. The nature of the industry, tht
competition and business may not provide an oppore
tunity to gain a competitive advantage. It would be
erroneous to impute the competitive advantage gained
in the airline industry by American Airlines to companies that use on-line systems in all industries. The
generalizations of competitive advantage from on-line
systems must be made carefully and only after considering whether: (1) on-line systems can improve cus-tomer service, and (2) the improved service will result in
increased sales. It is therefore not necessary to use online systems simply because competition is doing so.
Depending on the nature of the industry, a company
using traditional data processing equipment can satisfactorily compete with a company using on-line systems.
In an evaluation of whether or not to implement an
on-line system, it is not sufficient to state that on-line
systems are better simply because they provide more
rapid information flow. It must be shown how and why
the quicker information can be used, and the potential
savings that can be related to the faster availability of
information. If a company does not have a clear idea of
the specific benefits an on-line system will provide and
how these benefits are to be achieved, on-line systems
should be evaluated on a cost displacement basis; that
is, the method of data processing that performs the
required functions at the lowest cost should be selected.

A panel session-Computers and the underprivileged
JAMES H. BURROWS, Chairman of Session
Th£ Mitre Corporation
Bedford, Massachusetts

Computers and the underprivileged
by MILTON BAUMAN

Price Waterhouse and Company

A group from the Delaware Valley Chapter of AClVl
have joined together to form the Urban Education
Committee. :Members of the committee believe that,
in these days of urban crisis, the data processing industry offers a unique opportunity to the disadvantaged
to become involved in the mainstream of the American
way of life.
Mter several abortive attempts to determine where
to employ its professionalism, the Committee has decided upon several projects recommended to it by
different groups within the city of Philadelphia. These
projects include providing counseling on data processing
to the Pennsylvania Employment Service and Philadelphia high school counselors; providing advice and
counsel to the Board of Education on the data processing curriculum taught in high schools; providing
data processing consulting to the Philadelphia Urban
Coalition; and; most. important, running a computer
operator training course in a Philadelphia high school.
The computer operator training course is being given
to 20 high school seniors from Thomas Edison High
to provide the students. We requested that the students
not be college bound, but be of such caliber that would
probably insure the success of the training program.
The Board of Education, in turn, asked the Principal
of Thomas Edison to select the students whom he believed showed leadership qualities and the intelligence
necessary to successfully complete the progr~m. The
20 students finally decided upon were selected from a

--------------------------------------35

group of 48 recommended by the Thomas Edison
faculty.
The training program meets Wednesdays and Saturdays. The curriculum is aimed at IB.:.v1 360/30 operator training and extensive hands-on training will be
provided. The curriculum is divided into two parts. The
first sessions deals primarily with training on punched
card equipment to provide the students with a background in data processing and operations done on computers. The 360/30 training will concern itself primarily
with IBM's Disc Operating System.
The curriculum for the course was developed by a
sub-committee composed of three members. We attempted to obtain curricula from other AClVl chapters
had not, when w.e were beginning the program, formalized their curriculum to the point where we could use it.
It became necessary, therefore, for the suo-coIIlmittee to
collect operator training manuals from various computer manufacturing organizations and from private
sources.
Developing the curriculum was only one of several
problems that were encountered when the program was
started. Other problems were finding instructors (paid
instructors, not volunteers), obtaining funds for paying
for instructors and field trips, etc., finding machine
time (both punched card and computer), and, finally,
placing the students in jobs after graduation (we were
advised that if students were trained and were not
placed in jobs, the training would be at best worthless,

36

Spring Joint Computer Conference, 1969

or even worse than no training at all). I can report, at
this juncture, money has been donated, that instructors
have been hired, machine time has been donated, and
12 of the 20 students have been placed in various companies throughout Philadelphia and the Delaware
Valley.
In summary, the technique used by the Delaware
Valley Chapter in becoming involved in urban affairs
was by becoming involved-headfirst. We collectively
made up our minds to do "our thing" and, with a little
urging from the Board of Education, we did it. We had
a few anxious moments in getting started without having
all of our problems resolved, but the fact that we had to
resolve them in a short period of time made us devote
that extra amount of effort necessary. If we had held
off our program until all problems had soiutions, our
course probably would not have started in 1968, but
rather in 1969 or perhaps never.
Our plans for the future include a similar program in
a Camden High School (we do have a number of interested members from RCA at Cherry Hill, New
Jersey) and expansion of our Philadelphia program to
another high school.

aspect of recent technology, e.g., lasers, computer systems.
A basic program for the first sector in computer programming was established. The tuition to the school was
set at five dollars, a figure low enough to exclude an
absolute minimum and yet still be a commitment on the
part of the student. The response to our notice in local
newspapers, radio and through public relations channels
at 1V1.LT. was overwhelming. For lack of staff to screen
applicants, the first five hundred were accepted. Although our largest interest was in providing access to
education for ghetto dwellers of limited resources, our
inability to screen applications resulted in a net of
about 140 hardcore "deprived" out of the total of five
hundred. Of these 140, about 70 percent were black.
Five graduate students at N1.l. T. provided the instruction and were assisted by ten l\1.I.T. undergraduate teaching assistants. The plan is to initiate a chain
of lectures by asking successful teaching assistants each
year to lecture the following year. We focused on the
140 hardcore "deprived" assigning seven of the M.LT.
teaching assistants, most of whom were black, to those
students. These students were divided into smaller
tutorial sections of ten to fifteen students headed by one
of the teaching assistants. Teaching assistants were also
available for consultation in the keypunch rooms.
An -:.\tLl.T. student-run computer company has
offered to assist in a placement service for these students. vVe feel that follow up to the program is very
important and is presently very weak.
An advanced systems programming course was
offered to the second sector of the community, the
highly educated sector. We accepted 80 into that program. We feel that these programs will tend to complement each other in t.ha,t t.he advanced program will
be taught to people who may later assist or influence the
hiring of those in the other program.
The basic program will be expanded to include
courses in computer maintenance, Boolean algebra,
basic business algebra and other practical courses. As
technology changes business trends change; the program will be modified to fit the needs for training in the
changed environment. It is our overall purpose to offer
courses broad enough to establish a basis for training in
a particular area. We do not pretend to offer a substitute
for the broad knowledge acquired from a college education. We do try to offer a program in a specialized area
which has two undeniable attractions: job opportunities
and subject excitement. Computer programming is such
an area.

A program for the underprivileged and
overprivileged in the Boston Community
by JOH:\' .J.

DO~()V AN

M assachusetis Institute of Technology
Cambridge, MaHsarhu:.;etts

In response to the needs of the Boston Community,
a new direction has been taken in the Lowell School, a
school under the auspices of the Massachusetts Institute
of Technology, which will offer education to the community for no more than the cost of two bushels of
wheat. The program focuses mainly on the needs of two
sectors of our community.
One sector is those individuals who are undereducated
and underemployed, many of whom are the "llnderclass" of the ghetto, suffering from the crippling syndrome of education-motivation-employment deprivation. The other sector is those senior men of industry
who are very well educated but need retraining in some

o..-_ _ _ _ _ _ _"--......;;:.=_ _ _ _ _ _ _

-"

~""~"

_-~"~.~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Computers and the Underprivileged

What the JOBS program is all about
by WILLIAM B. LE\VIS
U.S. Department of Labor
Boston, Mass~,d1Usetts

One of the thorniest problems in America today
is that of the habitually unemployed people living
within the inner core of our 50 largest cities. For a long
time employers and organized labor have written them
off as unemployables. The U.S. Department of Labor
has, over· the years, tried various approaches to these
hard-core jobless, with uncertain success.
In January 1968, President Johnson announced a
program of Job Opportunities in the Business Sector
(JOBS). The new program looked to industry to apply
its full resources and "know-how" in cooperation with
the Government, to help break the cycle of unemployment of the hard-core by making them permanent
productive mem bel'S of the labor force.
In announcing the JOBS program, the President
said he was calling on American industry to establish a
National Alliance of Businessmen (NAB) to launch it,
help achieve its goals, and advise the Government.
Under the leadership of Henry Ford II, NAB was
volunteering to spearhead the effort in the 50 largest
cities of the country.
The K AB goal for JOBS is to put 500,000 disadvantaged persons in jobs by June 1971, with an
interim goal of 100,000 to be placed by June 1969.
The JOBS program involves a commitment by employers to hire workers first and train them afterwardbuilding on the accumulated evidence that initial placement in jobs at regular wages does much more to motivate a disadvantaged individual than a training period
before employment with only a promise of a future job.
The program puts at the disposal of industry the services and financial support of Government, which experience has shown are essential if the disadvantaged
unemployed are to receive the range and depth of services required to help them become productive workers.
The cooperating companjes provide jobs and training
for hard-core unemployed workers and bear as much of
the cost as would be involved in their normal recrui tment and training operations. The extra cost of added
training, counseling, remedial education, prevocational
training, health services, and other specialized support
needed to bring disadvantaged individuals to a satisfactory level of productivity and keep them on the job
may be offset by funds provided through a Department

37

fo Labor contract. In order to encourage smaller companies to participate, an optional standardized program
approach has been developed. Intensive efforts have
also been made to give cooperating employers all possible technical assistance in developing plans and formal
proposals.
The first-year NAB goal of 100,000 hard-core persons
on the job has been reached by the JOBS program ahead
of schedule.
A full assessment of the JOBS program results is not
possible at this early stage, but it is apparent that the
start made is highly promising. The attitude of participating compames is generally either optimistic or
enthusiatic, and they concur regarding the validity of
the JOBS idea and intent.
The immediate effect of the JOBS program has been
to employ those formerly thought to be unemployable.
However, the benefits of JOBS are more far reaching.
The skills gained through the JOBS program open the
doors to advancement to those formerly without hope.
110reover, what the private employer's experience in
the JOBS program has taught him about the problems
of the hard-core and the possible solutions to their
special problems will, in a large number of cases, have
a spillover effect on the company's regular training and
employment practices.

Computers and the underprivileged.
by ALLE~ L. MORTON, JR.
Computer Personnel Development AssociaMon, Inc.
Xew York. Xew York

Statem.ent of objectives

The Computer Personnel Development Association;
Inc. (CPDA) is an organization that has been set up to
secure openings in the computer field for individuals
from ghetto areas. To prepare these people for work in
a business environment, CPDA will provide orientation
and training courses in data processing. The program
is organized by professionals within the computer
industry in collaboration with local community development groups who will help select participants for the
program, and with industrial leaders who will locate and
provide job opportunities for the participants.
The long term objective of CPDA is to establish
career paths in the computer industry for our students.

38

Spring Joint Computer Conference, 1969

This will be accomplished by providing continuous job
training and career guidance in all areas of data processing.
The following points define the broad areas of
CPDA's capabilities.

1. Computer Operations Training Program-Training ghetto personnel judged capable of completing a training program in computer operations and functioning in this capacity within the
data processing area.
2. Computer Programmer Training ProgramTraining similar personnel who are in a position
to complete a training course in computer programming and to function as programmers.
3. Job Placem.ent and Development-Yloving graduates of the above programs from the training
phase into jobs which will be identified prior to
and concurrent with training.
4. Career Guidance-Providing follovy up procedures to smooth the students' transition from
the training to the business environment.
5. Related Personnel Services-~laking available
to management on a consultant basis more
precise selection and training procedures for
minority group personnel.
Implementation of the above program will provide
an opportunity for untried minority group persons who
show a potential for achievement. This program will
serve as a source for desperately needed technicians in
the data processing field as well as provide a program
which realistically meets the job-related directive of
the President's Bipartisan National Commission on
Civil Disorders.
OUf first project is a pilot program to train ann place
computer operators. This program is limited in scope
but can succeed only with the active support of industry.

Experimental and demonstration
manpower projects
by JOSEPH SEILER

U .S.Department of Labo'f
Washington, D.C.

The U. S. Department of Labor's experimental and
demonstration (E and D) program seeks to develop and

test through actual project operation, new ideas and
techniques to meet manpower problems more effectively. Projects focus on the particular problems which
impede employment of Lhe unemployed and underemployed and which are not being met effectively by established manpower program methods. They seek,
through innovative techniques and new types of organizational arrangements, to determine how the programs
might better "reach" and help prepare such workers for
jobs, place them, and retain and upgrade them in gainful employment.
Because each project is specially designed, experimental and demonstration projects are not readily
categorized. They differ widely, not alone by group or
problem focused upon, but by technique or combination
of techniques tried and, of great importance, by type of
institution or combination of institutions enlisted to
conduct the effort.
The groups concentrated on have been primarily unemployed ghetto area youth, minorities with cultural,
emotional and other handicaps to employment, lowincome rual residents, and older workers with limited
education.
Although the E and D program's key objective is to
stimulate and guide innovation rather than to provide
services directly, it does provide significant assistance to
the thousands of participants in its projects.
~l any of the techniques for delivery of manpower
services have been developed or refined in E and Dsponsored projects. Briefly, important concepts which
E and D efforts have helped pioneer and introduce
widely into manpower programming include:
(a) outreach to identify, attract and retain participation of the disadvantaged who do not come forward on
their mvn for needed. manpnwer services; (h) multi-service programs and centers to provide comprehensive
service on a coordinated readily -accessible basis; (c)
work sampling to evaluate the potential of those with
limited education and to build the confidence of those
with limited communication skills; (d) prevocational
training, work orientation and related preparation as
an aid to effective skill training and employment; (e)
use of nonprofessional and indigenous staff as a vital aid
in manpower development for the disadvantaged; (f)
new occupations, particularly as subprofessional aides
in human service activities, to broaden opportunity for
the undereducated; (g) use of community and minority
organization capabilities to complement government
agency manpower development efforts; (h) inducements for employer initiative and action to hire, orient,
train, and retain workers customarily regarded as "unacceptable"; (i) post-placement coaching and "high
support" to enable employers and disadvantaged

Computers and the Underprivileged

workers to overcome difficulties jeopardizing job retention in the initial months after hiring.
1\Tore specifically, the following are major examples
of types of E and D accomplishments:
The major new Concentrated Employment Program
(CEP) and Job Opportunities in the Business Sector
(JOBS) manpower programs, initiated in part on the
basis of E and D findings, were given significant start-up
assistance by the E and D program:

1. lUany features of the CEP have been designed
from examples developed by E and D projects.
The orientation, coaching, and employer involvement components particularly are based on
E and D-developed models. Several E and D
projects, most notably the JOBS NOW program
in Chicago, provided the initial staff training
and technical guidance for CEP personnel. And
key staff needs in several of the initial CEPs were
filled by personnel drawn from E and D projects.
The E and D program also developed specific
guide materials on job development methods,
orientation and coaching to assist the new CEPs
in such activities.
2. The new JOBS program initiated with the
National Alliance for Businessmen was similarly
influenced by E and D pilot experience The
findings of several E and D projects shaped the
guidelines for JOBS efforts, and materials developed in the E and D program have served as
basic resources for JOBS employer-contractors.
0

New ways have been developed by E and D projects to
open and improve employment opportunities for the

1. E and D projects in Cincinnati and Washington
have with union cooperation been exploring how
to provide work preparation and experience for
enable them to enter building trades apprenticeships and employment in housing renovation and
construction. These projects have been looked to
as practical examples to aid development of
Model City program guidelines for employment
of neighborhood residents in ghetto rebuilding.
2. A demonstration project with the Post Office
Department has developed a technique which
other Federal agencies are considering to help
overcome test barriers to employment of the
disadvantaged. Workers unable to pass civil
service tests were recruited and hired on a temporary basis and, after special instruction while

39

employed, a high proportion were enabled to
meet the test requirement for permanent employment-and have performed effectively on
the job.
Techniques are being developed to help employers upgrade their unskilled workers. A pilot E and D effort

provided brief but intensive in-plant training to workers
employer might not otherwise fill from his own employees. The employer response to this project has led
to its extension for further development in new projects in three major cities, preparatory to likely largerscale application iOn the near future.
Techniques are being developed to help identify the
"real" job potentials of disadvantaged persons. The

disadvantaged person's lack of skills and insufficient
knowledge of his own capabilities combined with his
usual very poor performance on paper-and-pencil tests
all conspire to qualify him in the eyes of the counselor
or personnel man for only the most menial dead-end
jobs.
Work sample tests, originally developed by sheltered
workshops for physically and mentally disabled, have
been shown by E and D to be useful with the disadvantaged as a substitute for the unworkable written tests.
The work-sample technique has been refined by the
Service in an E and D project that has led to a ten-city.
pilot operation that will further extend our knowledge of
its utility as an approach to appraising the job potentials
of the unemployed.
Other interesting E and D efforts in their early stages
are:

1. Crime problems. E and D efforts on several proj-

ects are designing systems with courts and police
to develop training and employment as an alternative to criminal prosecution and imprison
ment.
2. Job Zart{iuage facility. Projects are focusing, not on
basic literacy as such, but on "job English" for
Spanish speaking workers and on "occupational
language" for workers with limited literacy
backgrounds.
3. Employer Based Day Care. One project is exploring the feasibility and value of an employer
sponsored day care center as an aid in recruitjng
the inner-city unemployed for existing job vacancies, and as a means of enhancing employee job
stability and performance.

40

Spring Joint Computer Conference, 1969

The E and D program's emphases will steadily shift
as earlier findings are absorbed by established programs
and attention is required by emerging new manpower

problems and by a growing need for measurement and
analysis of relative effectiveness of alternative approaches.

A panel session-Computers in service to libraries
of ihe fuiure
CALVIN N. MOOERS, Chairman of Session
Rockford Research Institute Incorporated
Cambridge, Massachusetts

Computers in service to libraries of the
future: Library requirements
by

w. N. LOCKE

Massachusetts Institute of 'Pechnology
Cambridge, Massachusetts

An outstanding computer engineer recently compared
libraries to the whaling industry, a relic of the romantic
past. As whales disappeared, so will books, he said. We
should stop building libraries, store all information on
tape and retrieve it through consoles.
This may be acceptable as a piece of blue skying but
hardly comes to grips with the problems of information
handling today and tomorrow. At a time when the
world outpouring of written words is going up ten percent a year (an estimated 300,000 books and 100,000
serial titles in 1968), it doesn't make much sense for
librarians or anybody else to plan in terms of a replacement of print by any other form in the near future.
So let's come down out of orbit and talk about
mundane facts. Libraries cost dollars and serve people.
For dollars they compete with other goods and services.
The people they serve are as diverse as the population.
Some just want. a quiet, comfortable place to read or
think; others want a particular book or journal; still
others want all the information you have on some
special topic; some need items that have tQ he located
and brought from some other lihrary. Then there are
those who want to check a fact, a name, and so on. The
library has to he all things to all people. And this
requires complex organization, specialized staff, and
constantly expanding space: it requires a lot better
inventory control techniques than we now have. This is
the challenge to computerniks. If they want to take over
and operate the information handling husiness, they

must do so in a real world of program budgets and cost
benefit analysis. They must also work closely with
librarians to provide a transition from the present to the
future.
It might be well to look at today's information
retrieval in the library context, see how much of it goes
on, and calculate the cost. This amount is in the budget
and presumably available for a computerized service.
The total is not encouraging. Additional services that
can he provided hy the computer will have to be costed
out and budgeted for next year or some future year.
At present, it is the customer who does most of the
information retrieval; only he, and frequently not even
he, knows what he wants. The library staff spends most
of its time on document handling, acquiring, cataloging,
and retrieving, not information, but books and book-like
materials in dozens of forms, fuB size and mini, plus
maps, music scores, manuscripts, sound and video
recordings. The library is the memory of the race. It is
different from the memory of the individual in that the
individual's memory is associative while the library
deals with discrete packages. Cataloging is a poor but
expensive suhstitute for what goes on automatically
and suhconsciously in our minds as we record our
experience.
About 33 percent of the average library personnel
budget goes into the preparation and filing of information about the many kinds of items that come into the
lihrary. This input can as well go into a computerized as
41 -------------------------------------------

42

Spring Joint Computer Conference, 1969

into a manual system; but it is hard to see how savings
can be effectuated by a computer at this point unless we
source like .:\IARC II tapes. If it is cheaper to process
these tapes to find the descriptive and subject catalog
information for individual items as they come to a
library, rather than get it from printed copy or originate
it, then we will Use them. Unfortunately, present
indications are that it may cost more.
Storage is one of the cheapest things we have today.
Even amortizing land and building cost, we can keep
reference books a year on the shelf for 20¢ apiece.
At;j =\f bits each, this is 4¢ per million bits per year. The
card catalog is somewhat more expensive at 48¢ per
year per million bits. Add an annual increment of eight
percent or so atld costs of conventional storage are still
bearable. Not so the costs of on-line storage, \vhieh is
the only conceivable forin of computer storage for this
ty·pe of material.
The numbers are not much better for present day
library reference staff work in information retrieval.
Reference work and catalog service may account for
about ten percent of the personnel budget of a large
library. Half of the time of these professionals may go
into information retrieval. Assuming that they will have
to spend a good deal of time training customers in using
the computer, we may be able to save half the present
budget to put toward the machine. This will not go far.
In fact, my conclusion is that computerized information
retrieval will require practically all new money. ~Iajor
new financial support will be needed for large scale
information retrieval, SDI and other individualized
computer based services which we in the libraries want
to provide.
Librarians have always been quick to adopt new
technology, for instance for catalog card production,
for micro storage, for quick, expendable copies. Computers are no exception. They are urgently needed now
for inventory control. If we can afford anything that
computers have to offer, it is this.

Using computer technology-Frustrations
abound
by HENRIETTE D. AVRAM
Library of Congress
Wa~hington,

D. C.

The automation of libraries is a fairly recent entry to

the growing number of areas of applications for computers. Is this an indication that librarians have been
resisting advancing technology or could it be that the
process of controlling large stores of information is so
complex and the hardware, software, and brainware
still too limited to cope with this complexity? lVlight it
also be that computer specialists, underestimating the
challenges, have evinced little interest in the library
problem?
My experience in the library world suggests that these
states and conditions have all combined with negative
effect. The function of a library is to provide reference
service to users and to make readily available the
contents of its collections. The efficient performance of
this function is directly related to the successful and
timely completion of processing, Le., the selection
acquisition, cataloging, classification, and shelving of a
book. The rapidly increasing number of books and
periodicals places the greatest strain in this area and
thus pinpoints the prime candidate for mechanization.
Before discussing one of the major automation
activities at the Library of Congress and its associated
problems, some facts about LC are in order to set the
environmental background. The Library of Congress
has in its collections about 55.5 million items: books,
serials, maps, music, prints and photographs, manuscripts, etc. Approximately 75 million records contain
the control information and bibliographic description of
this collection. I ts largest file, the Official Catalog,
contains some 14.5 million records. An inventory of files
showed that there are about 1,260 different files which
are used in the Library's operations. Under Title II-C
of the Higher Education Act of 1965, the Library has
been charged with the additional responsibility of
acquiring and cataloging all works, published anywhere
in the world, important to scholarship. The materials
flowing into the Library include items written in 70
different languages, represented by 20 distinct alphabets.
One of the basic functions of librarians is the recording
and organizing of bibliographic data to facilitate access
to and use of the books and other materials contained in
the collections of libraries. Although bibliographic data
may be recorded and stored in a variety of ways, the
card catalog record has been the preponderant medium
used by libraries in the United States. The bibliographic
information on the catalog record is basically of two
kinds: (1) a description of a book in terms of author,
title, etc., and (2) some kind of notation to be used in
locating the book on the shelves. The locating notation
also usually comprises a means for arranging together
materials on the same and related subjects. A catalog
record distinguishes in a unique place one book from all
the other books represented in the catalog. The catalog

Computers in Service to Libraries of the Future

card, with its basic information, can be used again and
again to provide multiple access capability-usually
Ituthor, title, subject-and forms the basis of what is
known as the unit card system. Essentially librarians
Bl"e attempting to organize and make readily available
the intellectual output (books) of other humans in all
disciplines. This involves the application of a rather
complicltted set of rules to the output of very unpredjctable human ~ings; the result being that it is safe
to say that a1m~t every rule will find its exception
manifested.
Since the Library of COJlgress is the major source of
bibliographic infon:rmtion for the American library
community, it was naturQ.l to conduct an experiment at
LC to test the feasibility a.nd utility of centrally
producing cataloging data and di$tributing these data to users. Project MARC (foJ' MAcbin~-Readable Cataloging) was in operation for 19 JIlQntM in. ~st and pilot phases involving sixteen coopel'tt-ting libraries. The project was successful and a full operational system providing selected machine-readable cataloging data for all interested libraries will begin early in 1969, During the pilot period, recommendations for improvement were received from the participants, a cost mod~l was maintained, and the procedures for preparing bibliographic data for conversion to machine-readQ.ble form and the processing of these data were improved. The format for the interchange of the record was evaluated by staff members of many organizations: the Library of Congress, the National Library of :M:edicine, the National Agricultural Library, the United States of America Standards Institute Z39 Subcommittee 2 on Machine Input Records, the Committee on Scientific and Technical Information (COSATI), and other interested organizations both here and abroad. The result was the adoption of a format designed for the interchange of data and hospitable to the bibliographic description of all forms of material. The format for monographs as adopted by the Library of Congress has four important characteristics: 1. It establishes the means by which bibliographic information may be transmitted between libraries. 2. It describes the rigorous rules by which bibliographic information, available in human-readable form, may be converted to machine-readable form. 3. It suggests that if the same format is used for the exchange of information by all libraries, programs and procedures may be exchanged and automation costs reduced. 4. It follows the United States of America Standards Institute Code for Information Interchange 43 (ASCII), the standard for Recorded Magnetic Tape for Information Interchange, and the proposed standard for Magnetic Tape Labels and File Structure. The library community, although operating in a very imperfect world in terms of having both second and third generation computers, configurations progressing from minimal to maximum (when is a 1401 a 1401 ?), and I/O devices not capable of handling the necessary character sets, has forged ahead to adopt standards. This is a significant step forward. The introduction of computers to libraries poses special problems in file organization and hardware while providing new opportunities for multiple access to information. We are faced with deciding how information can best be structured and stored for effective retrieval. Imposed on top of all classic functions performed by librarians, i.e., acquisitions, cataloging, classification, reference, is the function of searching. The search argument varies with the inquiry. It ranges from data on an order slip to the information on the title page of a book, to the Library of Congress catalog card number, to a name in an authority file. The questions of file structure-where in the file to search and when to stop searching-are related to discovering the criteria for the determination of identity. The human mind has certain categories of analytic capability which cannot yet, if ever, be captured by machine. Therefore, we must create ploys which cause the machine to approach, in effect, the desired objectives. Studies at the Library of Congress show that the storage requirements for 1972 is 4 X 1()9 characters. Int.eresting developments in hardware technology in the next five years should partially resolve the problems of large random access stores at acceptable costs. If we can approach an efficient solution for organizing information and consequently retrieving from the files, one nagging question that remains is how best to convert the files and in what order of priority. Because libraries cannot limit coverage in time and discipline, files reflecting the past must in time be converted to machine-readable form. Many conversion strategies have been proposed and the final decision must be based upon reasonable grounds as to use and cost. The conversion of bibliographic information requires specifications for the representation of this information in machine-readable form, i.e., decisions regarding data elements that need explicit identification and the definition of a character set for input, storage, and display. The character set needed to encode bibliographic data is essentially infinite because it is openended. Not only are we concerned with many hnguages in a multiplicity of alphabets, but in addition, any 44 Spring Joint Computer Conference, 1969 ij,l,lthor can use any character at will. The obstacles then become challenges seeking creative solutions. Librarians and computer scientists have rarely communicated well with one another, and this lack of communication results from the fact that each group is too parochially oriented to its own field. Both groups are ~ctually ~triving toward precision but each sees pr~cisiQn hi a different way. The librarian is concerned with pre.cision in the definition of the record, for he must be p~cise in this definition in order to uniquely represent ~ book for retrieval. The computer person is interested in precision in method,· i.e., an exact descriptioll of a process, so that his program will perform efficiently and produce the output required. Machine people have a tendency to minimize the librarian's problems of precision and exhibit a general reluctance to become interested in the data except as it affects the computer application. Without a complete understanding of the co:rnple~ty of the data, the capabilities of the computer are. oversold, thus later causing what might be. tenned a credibility gap. Librarians, on the other hand, must recognize the potential and the limitations of the new technology and provide the necessary guidance for the efficient use of communication and information manipulation devices. Success will not come overnight but will depend upon the combined efforts of the most talented people that can be found in many disciplines. Computers in service to libraries of the future by HOWARD W. DILLON Harvard University Cambridge, Massachusetts Automation activities in libraries have been undertaken with accelerating frequency over the past ten years. I t is no longer uncommon to find successful projects in almost every type and size of library throughout the country. Libraries have demonstrated that they can develop and operate ordering and processing systems to control financial and bibliographic information at the time a new item is added to the collection. Book catalogs and other holdings lists are produced and distributed in many formats. Automated circulation control systems, particularly the data collection type, are widely accepted and functioning successfully. This portion of the panel discussion will describe a few projects with which the speaker is familiar. The projects selected have been chosen because they represent major attacks on problems which must be solved in order for all libraries to move forward with automation. A recurring problem for systenis of library processing developed over the past years has been the reliability of the data first entered into the system at the time a purchase order is placed. In off -line systems, the need to edit or replace the information used at the time of the order with better data obtained when the item purchased is in hand has been a critical update problem. FeVwr systems; therefore; attempted to carry computer processing from ordering through to the completion of cataloging as one integrated system. On-line processing capabilities and the development of a nationally distributed, timely bibliographic record by the Library of Congress in the NIARC II communications format, make it more likely that integrated technical processing systems for libraries can be made operational. Second, given a communications format for the sharing of bibliographic data, libraries with common processing requirements are undertaking to share in the cooperative development and design of processing systems. Standardization and compatibility have been hallmarks of library systems for many years. While not always perfectly achieved, librarians have traditionally demonstrated their concern with the sharing of bibliographic data and collections. The advent of computer processing has not altered that basic philosophy. Rather, it provided an opportunity to realize the goal of compatibility with greater perfection. Systems to be considered in this presentation will include: SYlVIBIOSIS-SYstem for Medical and BIOlogical Sciences Informat.ion Searching NELINET -The New England Library Information Network The Integrated, Computer-Based, Bibliographical Data System for a Large University Library, being developed by the University of Chicago Library, including the subsequently coordinated activities of Columbia and Stanford university libraries in this acquisitions and cataloging system. Computers in Service to Libraries of the Future The Washington State University Library Technical Services System, which is a project to develop an on-line processing capability for that library. 45 The presentation will review the objectives of these projects, summarize their accomplishments to date, and discuss hardware or operating system software problems encountered. Batch, conversational, and incremental compilers by HARRY KATZAN, JR. Pratt Institute Brooklyn, New York INTRODUCTION Compiler-writing techniques have received a great deal of pragmatic and academic attention and are now fairly well-defined. * It was and still is generally felt that the compiler is independent of the operating system jn which it resides, if it resides in one at all. The invention of time-sharing systems with conversational capability, however, has required that compiler experts re-evaluate existing concepts to make better use of external facilities. This was done and conversational and incremental compilers have evolved. A generalized and consolidated discussion of these relatively new concepts is the subject of this paper. First, a model of a batch compiler is introduced. The concepts are then modified and extended for a conversational programming environment. Finally, a recent development termed "incremental" compilation, which satisfies the needs of both batch and conversational compiling as well as interactive computing, is presented. First, some introductory material is required. Basic concepts In the cla~:::;ical data processing environment, ** t.he "compile phase" or "souree language pl'ocet):sing phase" is of prime importance as are definitions of source program and object program. The latter are redefined in light of the time-sharing or iuteractive environment. Extran~ous items, such as where the object program is stored or whether or not the compiler should produce assembler language coding, are practically ignored. The source program is the program as written by the • Two books devoted entirely to the subject are worth mentioning: Lee, J.A .N., 'Phe Anatomy of a Compiler,l and Randell, B. and L. J. Russell, Algol 60 Implernentation. 2 *. See Lee,l p. 9. programmer. It is coded in symbolic form and punched ?n cards or typed in at the terminal. The object program IS the program after being transformed by the compiler into a machine-oriented form which can be read into the computer and executed with very few (if any) modifications. Also of interest is the information vector which gives initial conditions for compilation and denotes the types of output desired. A sample of specifications which might be found in an information vector follow: (1) location of the source program; (2) name of the program; (3) the extent of compiler processing, i.e., syntax check only, optimize, etc.; (4) computer system parameters; (5) compiler output desired; and (6) disposition of the object module. The form of the source program is sometimes required, although in most cases this information is known implicitly. This pertains to different BCD codes and file types which may range from sequential or indexed files on conventional systems to list-structured files in virtual machines. Similarly for output, the user can request a specialized form of object module or none at all, source or object program listing, and cross-reference listings. The object module is known as a Program Module which contains the machine language text and relocation information. Additionally, it may contain an Internal Symbol Dictionary for use during execution-time debugging. The Internal Symhol Dictionary is especially useful in conversational time-sharing systems where execution can be stopped on a conditional basis and the values of internal variables can be displayed or modified. Batch compilation Batch compilation methods are required, quite naturally, in a batch processing environment. The term "batch processing" stems from the days when the programmer submitted his job to the computer center 47 ---------------------------------- 48 Spring Joint Computer Conference, 1969 and subsequently received his results later in time. A collection of different jobs was accumulated by operations personnel and the batch was then presented to the computer system on an input tape. The important point is that the programmer has no contact with his job between the time it is submitted to operations and when he receives his output. The concept has been extended to caver .:\1ultiprogramming Systems, Remote Job Entry (HJE), and the trivial case where no operating system exists and the programmer runs the compiler to completion. The generalized bat.ch environment The most significant aspect of the batch processing envirOlllllent is that the entire source program is available to the compiler initially and that all compiler output can be postponed until a later phase. The compiler writer, therefore, is provided with a liberal amount of flexibility in designing his language processor. For example, specification (i.e., declarative) statements can be recognized and processed in an initial phase and storage allocated immediately. In the same pass, statement labels are recognized and entabled; then in a later phase, validity decisions for statements that use statement labels can be made immediately rather than making a later analysis on the basis of table entries. If desired, source program error diagnostics can be postponed. ::.Yforeover, the designer may specify his compiler so that the source program is passed by the compiler or so that the compiler is passed over the source program, which resides semi-permanently in memory. This inherent flexibility is not exploited in the compiler model which follows. Instead, an attempt has been made to present the material in a conceptually straightforward manner. A generalized batch compiler By itself, a model of a generalized batch compiler is of limited interest. The concept is useful, hmvever, for comparison with those designed to operate in timeshared computer systems. Therefore, the presentation is pedagogical in nature as compared to one which might present a step by step procedure for building one. Processing by the compiler is rather naturally divided into several phases which tend to be more logical than physical. Each phase has one or more specific tasks to perform. In so doing, it operates on tables and lists possibly modifying them and producing nmv ones. One phase, of course, works on the source program froin the system input device or external storage and another produces the required output. The entire compiler is described therefore by listing the tasks each phase is to perform; ordinarily, the description would also denote which tables and lists each phase uses and what tables and lists it creates or modifies. The specific tables and lists which are required, however, tend to be language dependent and are beyond the scope of this treatment. The compiler is composed of five phases and an executive routine, as follows: The Compiler Executive (EXEC). The various phases run under the control of a compiler executive routine (EXEC) which is the only communication with the outside world. It establishe.s initial conditions and calls the different phases as required. It can be assumed that EXEC performs all system input/ output services, upon demand from the phase modules. :\Iore specifically, the EXEC has five maj or and distinct functions: 1. to interface "\vith the compiler's environment; 2. to prepare the source statements for processing by phase one; 3. to control and order the operation of the phases; 4. to prepare edited lines for output; and 5. to provide compiler diagnostic information. Phase 1. Phase 1 performs the source program syntactic analysis, error analysis, and translation of the program into a tabular representation. Each variable or constant is given an entry in the symbol table, with formal arguments being flagged as such. Initial values and array dimensions are stored in a table of preset data. Lastly, information from specification statements is stored in the specification table. The most significant Pl'ocp.ssing; howfwer, occurs wi.th respect to t.hp. Program Reference File and the Expression Reference File. Each executable statement and statement label is placed in the Program Reference File in skeletal form. In addition to standard Program Reference File entries, the Program Referellee File contains pointers to the Expression Heferenc(' File for statements involving; arithmetic or logical expressions. The Expression Reference File stores expressions in an internal notation using pointers to the symbol table . when necessary. As wjth the Expression Heference File, the Program Reference File also contains pointers to the symbol table. Phase 2. In general, phase 2 performs analyses that cannot be performed in phase 1. It makes storage assignments in the Program l\Iodule for all variables that are not formal parameters. It detects illegal flow in loops and recognizes early exits therefrom. It also detel'lnine::; blocks uf a program with IlU path of control Batch, Conversational, and Incremental Compilers to them; and lastly, it detects statement labels which are referenced but not defined. Phase 3. The object of phase 3 is to perform the global optimizations used during object code generation, which is accomplished in phase 4. The first major function of phase 3 is the recognition and processing of common sub-expressions. Phase 3 determines which arithmetic expressions need be computed only once and then saved for later use. In addition, it determines the range of statements over which expressions are not redefined by the definition of one or more of their constituents. If the occurrence of an expression in that range is contained in one or more DO* loops which are also entirely contained in that range, Phase 3 determines the outermost such loop outside which such an expression may be computed, and physically moves the expression to the front of that DO loop. Only the evaluation process is removed from the loop; any statement label or replacement operation is retained in its original position. The moved expression is linked to a place reserved for that purpose in t,he program reference file entries corresponding to the beginning of the respective DO loops. The second major function of phase 3 is the recognition and processing of removable statements. A "removable statement" is one whose individual operands do not have "definition points" inside the loop; obviously, the execution of this statement for each iteration would be unnecessary. A definition point is a statement in which the variable has, or may have, a new variable stored in it (e.g., appears on the left-hand side of an equal sign). In removing statements, they are usually placed before the DO statement. Phase 3 also processes formal parameters and develops the prologue to the program; it optimizes the use of registers; and it merges the Program Reference File and the Expression Reference File to form a Complete Program File in preparation for phase 4. Phase 4-. Phase 4 performs the code generation function. I ts input consists of the symbol table and the Complete Program File and its output is the Code File, which represents completed machine instructions and control information. Phase 5. Phase 5 is the output phase and generates the Program Module, the source and object listings, and the cross reference listing. Upon request, an Internal Symbol Dictionary is also included in the Program Module. * Although the DO keyword is a constituent part of several programming languages, it should be interpreted as representing the class of statements from different languages which effectively enable the programmer to write program loops in a straightforward manner. 49 Any compiler model of this type is clearly an abstraction; moreover, there is almost as much variation between different compilers for the same programming language as there is between compilers for different languages. The model does serve a useful purpose which . ' IS to present a conceptual foundation from which conversational and incremental compilers can be introduced. Conversational compilation Compared with the "batch" environment in which user has no contact with his job once it is submitted, the conversational environment provides the exact opposite. A general-purpose time-sharing system of one kind or another is assumed, * with users having access to the computer system via terminal devices. In the batch environment, the user was required to make successive runs on the system to eliminate syntax and setup errors with the intervening time ranging from minutes to days. Excluding execution-time 'bugs", it often took weeks to get a program running. In the conversational mode, syntactical and setup errors can be eliminated in one terminal session. Similarly, execution-time debugging is also possible in a time-sharing system, on a dynamic basis. . Conversational programming places a heavy load on a compiler and an operating system; the magnitude of the load is reflected in the basic additions necessary to support the conversational environment. The time-sharing environment The time-sharing environment is characterized by versatility. Tasks can exist in the "batch" or "conversational" mode. Furthermore, source program input can reside on the system input device or be prestored. The time-sharing operating system is able to distinguish between batch and conversational tasks; therefore, batch tasks are recognized as such and processed as in any operating system. The ensuing discussion will concern conversational tasks. It is assumed, also, that the user resides at a terminal and is able to respond to requests by the system. During the compile phase, the source program may be entered on a statement-by-statement basis or be prestored. In either case, the compiler responds immediately to the terminal with local syntactic errors. The user, therefore, is able to make changes to the source program immediately. Changes to the source program other than in response to immediate diagnos- * Two typical general-purpm;e time-sharing systemR are T&.,/36(}3·4 and MULTICS.o 50 Spring Joint Computer Conference, 1969 t.ics cause a restart. of t.he compilation process. Obviously, the system must keep a fresh copy of the source program for the restart case. To satisfy this need, a copy of the current up-to-date source program is maintained on external storage; if the source was prestored, the original version is updated with change requests; if the source program is not prestored, the compiler saves :J.ll source (and changes) as they are entered line-by-line. With the user at a tenninal, the compiler is also able to stop midway during compilation (usually after the global statement analysis and before optimization) to inquire whether or not the user wants to continue. Under error conditions, the user may abort the compilation or make changes and restart the compilation process. Moreover, the user can utilize this pause to have his program syntax checked only. During the execution phase, dynamic debugging is often desirable. This facility is uSU811y a part of the command structure of the operating system. In preparation for execution-time debugging, the user would probably request an Internal Symbol Dictionary during compilation so that internal variables can be addressed symbolically. Since execution-time debugging IS a relatively new concept, it is discussed briefly. Debugging commands usually fall into three categories: (1) program control; (2) program modification; and (3) debugging output. Debugging commands may be imbedded in the program itself or the program can be stopped (either asynchronously or with an AT command) and the actions perfonned immediat.ely. Examples of typical program control commands are: AT symbolic-location ... STOP RUN RUN symbolic-location Examples of program modification commands are: SET A = 1.0 IF A (0, SET A = 0 Examples of debugging output commands are: DISPLAY MAIN.I ::\IAIN.A DUMP ARRAY Furthennore, they can be used m combination as follows: AT PTWO.100 IF A = 0, STOP AT T34.360 DUMP T34.A SET CNT = CNT + 1 As was mentioned. earlier, a considerable amount. of the compiler's effort is devoted. to producing an efficient object program. As a result, the instructions to perform certain computations are sometimes not located where one would expect to find them. In fact, this is a direct consequence of common sub-expressions and removable statements, which were discussed previously. Although these processes contribute to efficiency, they have a side effect which hinders the debugging effort. Therefore, when expecting to use dynamic debugging, the user should request an Internal Symbol Dictionary and select the option which does not produce optimized. code. The conversational compiler and the time-sharing operating system must support several aspects of the conversational environment. These are sUlnmarized as follows: (1) the ability to change or forget the effects of the preceding statement; (2) restart logic; (3) maintenance of the entire source program, in up-to-date form, on external storage; (4) the ability to scan statements and produce diagnostics on an individual statement. basis; and (5) the option to produce optimized or unoptimized code. The conversational compiler Basically, the conversational compiler is a conventional batch-processor containing special features making it suitable for conversational, terminal-oriented. operation. Structurally, the major addition over a batch compiler is Compiler Control Program (CCP) , which in effect controls compilation. CCP is cognizant of whether the mode of operation is batch or conversational and is able to fetch source records and dispose of output print lines, accordingly. CCP is the facility which maintains the source program on external storage and is able to tell if a new source record is indeed. new, a change to last one entered, or a change to a previous one. When processing a request to fetch a source record for the compiler, CCP can use this information to simply return the record, return it with the "forget" flag on, or call the compiler at its initial entry for the restart case. The function to fetch a source record is termed GETLINE and is summarized in Table 1. Accordingly, an overview of the CCP is given in Figure 1. The overall logic of the conversational compiler is shown in Figure 2. Clearly, it differs very little from the batch version. The differences in the compiler itself are found in phase one and at the end of phase two. In phase one, as shown in Figure 3, the compiler uses CCP as its external interface. IVloreover, the compiler always compiles a statement conditionally; later it uses the Batch, Conversational, and Increnlental Compilers Initial Ent:rv 51 Continue Ent:rv 1r Phase 3 'n _ _ &: _ _ Initialize Compiler , Figure 1-0vervie\Y of the compiler control program (CCP) Table I-GETLINE Function of the Compiler Control Program (CCP) Conversational Presto red Not Prest. GBTLINE A B Batch Prestored Not Prest. A , Phase 2 Assign Storage; ~ind Global Errors Global Optimization , Phase 4 Generate Object Code t Phase 5 Build PM and ISD; Prepare Listings. C A. Fetches the next source record from external storage and returns it to compiler EXEC. B. Fetches another source record from the terminal input device and updates the source file on external storage. If it is the next source record, the line is returned to the compiler with the "forget" flag off. If the give~ source record is to replace the previous one, the "forget" flag is turned on and the line is again returned. Otherwise, a previous line has been modified and the compiler is entered at the "initial" entry point for the restart case. C. Phase 1 Translate Source; ~ind Syntax Errors. CC.I..l.V.I..lll Fetches the next source record from the system input device and updates the source file on external storage; the line is returned to EXEC with the "forget" flag off. "forget flag" to freeze or delete the compiled information. After phase two, as shown in Figures 1 and 2, the conversational compiler again exits to CCP. In the batch mode, of course, CCP simply returns to the compiler. In the conversational mode, as shown in Figure 1, the user is asked for changes and whether he wants to , Exit to CCP ~, Exit to CCP Figure 2-Logic of the conversational compiler continue. At the user's request, CCP can change the source program, still residing on external storage, and restart the compiler at the "initial" entry. If the user desires to continue, the compiler is entered at the "con-tinue" entry. Otherwise, CCP exits to the command system and the remainder of the compilation is aborted. Conversational compilation offers significant advantages over standard batch processing, most of which deal with the interactive mode of operation. The major disadvantage is that the entire source program must be available before execution can be attempted. In other words, one would like the versatility and flexibility of a language interpreter with the performance of a conversational or batch processor. ~1oreover, the performance must be reflected in the execution time as well as the compile time. 52 Spring Joint Computer Conference, 1969 Lock7 entitled "Structuring Programs for Multiprogram Time-Sharjng On-Line Applicat~ons" and the second by RyanS and others entitled" A Conversational System for Incremental Compilation and Execution in a Time-Sharing Environment." In order that the above goals can be realized, t~e following capabilities are required: Initialize 1. The ability to execute a statement immediately; 2. The ability to modify a prior statement without forcing a recompilation; :3. The ability to execute a source program as it is being input; 4. The ability to execute selected portions of programs; 05, A language processor that can also operate in the batch mode. Clearly, all of the above requirements, except speed, are met with an appropriate interpretive program. In a large time-sharing environment, however, this resource is of prime importance, especially when 50 or more terminals are being serviced. statement Processors r------I Last statement + ( The environment for incremental compilation Return) N y Delete Previous statement Figure 3-Compilel' Phase 1 interface with the eompiler eont.rol program I ncremenlal compilation One of the rnost promising ideas in this era of online computing is a concept termed Incremental Compilation. In an interactive programming environment, one would like to achieve both the speed factors inherent in compiled programs and the flexibility available with interpretive systems. Incremental compilers are an attempt to achieve these goals. ~1uch of the pioneering work in this area is reported in two papers: the first by Basically, the environment for incremental compilation is the same as for its conversational counterpart. By assuming a sophisticated operating system such as TSS/3603.4 or MULTICS,5 many of the problems described in the cited papers by Lock and by Ryan, such as memory protection among users, an effective command system, and memory organization and management, are obviated. Dynamic loading facilities, for utilizing hand coded subroutines, and a memory relocation feature,9 for mapping virtual addresses to real addresses, simplify problems involving the execution of code compiled incrementally and are also assumed. The programming language is naturally of importancp and of great interest to most, systems programmers. A language more powerful than standard Fortran or assembler language is expected, although the techniques would work satisfactorily therewith. A rich language which would enable a significant amount of computation per interaction is most desirable. Languages such as PL/po and Iverson's Languagell are well suited to incremental compiling and executing. The incremental compiler This method of compilation permits two modes of operation: batch and incremental. In the batch mode, the user may compile prestored source program but may not modify or execute the program during compilatioIl. In t.he incrernenial mode, normally uRed only Batch, Conversational, and Incremental' Compilers conversational1y, special facilities are available to permit the modification, execution; and checkout of the program during compilation. These operations are performed through a combination of control and source language statements. Incremental compilation consists of accepting a source program on a statement by statement basis. Each statement is compiled as it is received and the code generated for it is immediately made available for executioll. Associative links between the source program and object code are maintained, thus permitting the user, during compilation, to modify his source program and have the modification immediately reflected in the object code. The ability to compile, execute, and modify a program on a statement by statement basis gives the user a degree of flexibility over his program usually available only with an interpreter, yet reduces the principal objection to interpreters: that of requiring an excessive amount of execution time. While, in an interpreter, each statement must be processed each time it is executed, in an incremental compiler it needs to be processed only when it is entered initially or when the user makes a source program modification. The Incremental Compiler has the added advantage of ensuring that the object code the user tests incrementally is virtually the same as the code produced for an object module, since the same code generators are used in both modes. \\,~hen an Incremental Compiler is used in the batch mode, all of the usual facilities are available to the user. When used in the incremental mode, all of the batch facilities are available in addition to those provided to control the execution and debugging of the generated code. During both modes of compilation, the following options are permitted: 53 statement is a statement in the source language being compiled which is executed and discarded immediately. I t allows the user to intervene during the execution of his program and print results or change values. Commands are control statements which allow the user to make modifications outside the scope of the source language. A good example would be to change the control point of the program. Source program compilation and execution in the incremental mode is under direct control of a Language Controller (LC). Each interaction, by LC, with the user is divided into a processing cycle and/or an execution cycle, depending upon the input parameters. The compiler is called by LC to process source language and transient statements and if exeoution is requested, it is initiated and monitored accordingly. After execution, transient statements are discarded whereas source language statements are retained. The command system of the operating system is called by the Language-Controller to process commands. Clearly, there is a need to tie the various elements of a program together, for operational reasons, and this requirement is satisfied by the Program Structure Table, described below. Since the Language Controller controls a major portion of the processing when in the incremental modes, it is structured accordingly. As pictured in Figure 4, it contains program elements for maintaining the source program and the Program Structure Table, for controlling the compiler, for monitoring the execution of incremental code, and for interpreting and then dispatching or processing control statements. These functions are summarized in the following descriptions of the modules which comprise the Language Controller: Program Structure Routines. The program structure routines maintain the source program on external 1. Analyze the program only for syntactic errors; do not perform a global analysis or generate code. 2. Analyze the program for syntactic and global errors; do not generate code. t • ;~. Analyze the program for syntactIC and global The object program may be executed, in either the batch or incremental mode, only if the third option is selected. In most compilers of this type, the user may select one of several modes of executing the incremental code concurrently with compilation; as errors are UIlcovered, he may make modifications to the source language, without, in most cases, requiring a recompilation of the existing code or affecting previous execution. In order to provide the user with the degree of control desired, two categories of control statements are necessary: transient statements and commands. A transient Figure 4-Structure of the language controller for incremental compilation and execution 54 Spring Joint Computer Conference, 1969 storage and manage the Program Structure Table, which contains an entry for each source language statement in the program being compiled. The relationship of statements is also established for subsequent use by the Execution Monitor. Compiler Controller. The compiler controller provides the interface between the user and the compiler. It passes the identity and location of source statements to the compiler EXEC and receives the location of. the compiled code in return. In so doing, it handles diagnostics and updates the Program Structure Table. Execution Monitor. The Execution Monitor controls program execution as determined by the established mode of operation. It passes control between statements or halts execution after specific statements, as required. It utilizes the dynamic loader of the operating system and envokes other program modules when requested to do so. Command Interpreter and Dispatche1'. The Command Interpreter analyzes control statements and calls either the Compiler Controller or the conunand system of the operating system depending upon whether a transient statement or a command is being processed. The Program Structure Table is obviously of great importance since it indicates the relationship of statements and the static properties of the program. Elements in the table are generated dynamically as source language statements are entered and are composed from the following quantities: * 1. A type indicator specifying the type of statement; 2. A list of structure pointers linking this statement to preceding and succeeding statements and to any function module** in which it might be contained; 3. A pointer to the compiled machl:ne code for the Rtatement; 4. A locator, such as data set name or physical location, of the source program on external storage; and 5. A statement identification, such as a line number, used for referencing the statement and for making insertions, deletioIl::;, and changes to the program. * The article by Lock contains a comprehensive description of internal program structure in a programming environment such as this. **The term function module i!:l used to represent either a block or internai proced1lre as found in Algol or PL/I. Due to the nature of the incremental compilation process and the Program Structure Table, it iR not necessary that t.he incremental code for a given program reside in contiguous memory locations. In fact, only rarely will this be the case. Although this is conceptually different from the established practice of generating object code, it poses no serious problem in the incremental mode of operation. In general, the incremental compiler is composed of the same basic components as the batch and conversational versions. Some differences, which tend to be related to the interrelationshw of statements, do exist but are relatively minor. The" global" analysts of statements, for example, is severly crippled by the fact that all statements in a source module may not be available for analysis. The "global" optimization of statements is in the same category but must be eliminated entirely. It is very feasible, however, to include it as a special phase in the batch mode or provide a mechanism to convert from incremental to object code, including global optimization, in the conversational mode. The basic compiler processing cycle begins when it is called at its source input entry. (Another entry could conceivably exist which might be to convert incremental code to object code.) The compHer EXEC obtains the source text to be processed from the Language Controller and builds a Program Table consisting of t.he text to be processed during the cycle; information Oil additions, insertions, and delet.ions; location of the existing symbol table; and parameter data relating to mode of compilation, listing options, BCD codes, etc. The EXEC then invokes Phase 1 of the compiler which performs a statement classification and syntax analysis and builds the Program Reference File and Expression Reference File from all of the statements specified ill the Program Table. Pointers to t.he encoded statements are then returned to the EXEC, where the encoded statements are linked back to the Program Table. Phase 2 is then invoked to perform a global analysis, when possible, and to assign storage for the statements indicated in the Program Table. This phase updates the symbol table and merges the Program Reference File and Expression Reference File to form the Complete Program File maintaining the links to the Program Table, as required. Phase 4 t is now called to translate the encoded statements into object code forming the Code File. Phase 5 which must generate either object code or incremental code is considered below. Operation of the compiler for each of the two basic modes, batch and incremental, can now be described. In a batch compilation, the source text available at entry t Recognizing that no Phase 3 exists. Batch, Conversational, and Incremental Compilers consists of the complete program. The Program Table passed to each component points to every statement in the source program, so that in a single cycle, the complete compilation is produced. Other than the Executive (EXEC), the only phase which must be aware of the batch parameter is Phase 5, which must build an obj ect module instead of generating incremental code. Again, the obj'ect module consists of a program module (i.e., text and relocation data) and optionally, an Internal Symbol Dictionary. The text portion consists of the object code produced and is entirely self-contaihed, with the code generated for a statement linking directly to the code for the next statement. The source text available at entry to an incremental compilation may represent anything from a single statement to a complete program. Normally, however, the source text available represents only a portion of a program. The Program Table; therefore, contains a group of statements to be added or deleted in the current program. The Program Table is in the same form as for a batch compilation and does not require different handling by Phases 1, 2, and 4. In this mode, Phase 5 generates incremental code. Incremental code differs from an object module in that the Program Module (i.e., the relocation information) must be dynamically generated requiring some special processing by the Language Controller and the system's' dynamic loader. The text is organized on a statement-by-statement basis with inter-statement linkage provided to allow the intervention by the Language Controller* at statement boundaries: . As a result of the incremental process, four modes c~· execution are possible: automatic, controlled, block step, and step. In the automatic mode, statements are executed by the Language Controller immediately after they are processed by the compiler. In the coni;rolled mode, statements are executed only when explicitly requested by a RUN command, which may designate a range of statements. In the block step and step modes, an entire program (i.e., an external procedure) is available for execution, For the block step case; the Language Controller pauses for user intervention after each block (or possible subroutine) in the program. When the step mode is specified, Language Controller suspends obfect program execution after each statement. Early efforts and special problem areas The two specific references to incremental compilation, i.e .. by Lock7 and by Ryan,S are in a sense complementary. Lock tends to emphasize the structural * That is, the Execution Monitor. 55 aspects whereas Ryan emphasizes the systems aspects, even though different computers are involved. The effort by Lock, and probably others, at the California Institute of Technology is part of an experimental time-shating proj ect for the IBM 7040 computer. The programmmg languages supported are ALGOL, FORTRAN, and LISP with much of the paper beIng devoted to the internal organization of programs in an on-line programming environment. The Conversational ComplIer System, reported by Ryan and others, is an outgrowth of Lock's work and runs under an SDS 940 time-sharing system.' ALGOL and FORTRAN are also supported here with the paper emphasizrn.g the command language, memory organization, and compiling techniques. These projects have uncovered some interesting problems of which the most sigriifi cant , perhaps, is considered here. It involves changing a data declaration when executable code exists which uses the variables declared therein. In fact, the code may have been executed previously. Lock solved the problem by designing his pseudotmachine code so that all references to identifiers are indirectly addressed through non-relocatable entries in the user's symbol table. This certainly solves the problem but it partially nullifies one of the basic 'Objectives ot incremental compilation; that is, to gain the speed fact(Jr inherent in compiled code. A hardware mapping of identifiers to physical locations is feasible if relocation hardware and possibly a small associative memory are available, although it remains tD be seen whether dynamic address translatiDn can be used in this particular manner. Finally, one might ask the follDwing philDsDphical questiDn: "Is it unreaSDnable tD require a recDmpilatiDn fDllDWing a change tD a data declaratiDn?" Clearly, the answer must be evaluated in light 'Of the 'Other benefits tD be gained through incremental cDmpilatiDn. CONCLeSIONS The world of time-sharing and its potential for interactive computing at a general level has raised SDme interesting tDpics. First, it shDuld be recognized that althDugh batch techniques are currently very efficient and well defined, they were developed 'Of necessity. 'Vhen these techniques gained their acceptance, the hatch mDde was the 'Only 'Operational prDcedure available fDr using the cDmputer. The prDgramming cDmmunity shDuld alsD recDgnize that prDgram develDpment in a batch envirDnment may nDt be the most natural or the 'Optimum methDd. SecDnd, it shDuld be recDgnized further that CDnver- 56 Spring Joint Computer Conference, 1969 sational techniques do not offer a complete solution in that execution of parts of a program is usually not permitted. Clearly, language syntax errors can be detected as they are being input and this is certainly a step in the right direction. But ita programmer has to develop his algorithm completely before any of it can be executed, he might as well compile in the batch mode and rely on execution-time debugging. Some form of incremental compiling, therefore, seems to be the only answer in sight to questions regarding the development of algorithms in an interactive computing environment. The ability to execute a program as it is being compiled is certainly a natural way and very well may be optimum from a development point of view. It remains to be seen if the gains can justify the complexity of an incremental compiler. REFERENCES 1JANLEE The anatomy of a compiler Reinhold Book Co New York 1967 2 B RANDELL L J RUSSEL Algol 60 implementation Academic Press N ew York 1964 3 W T COMFORT A computing system design for USe?· service Proc F J C C 1965 4 C T GIBSON Time-sharing in the IBM /360: Model 67 Proc S J C C 1966 5 F J CORBATO V A VYSSOTSKY Introduction and overview of the MULTICS system Proc F J C C 1965 6 IBM System/360 Time Sharing System FORTR./1N IV Program logic manual IBM Corporation Y28-2019 Yorktown Heights N Y 1967 7 KLOCK Structuring programs for multiprogram time-sharing on-line applications Proc F J C C 1965 8 J L RYAN R L CRANDALL M C MEDWEDEFF A conversational system for incremental compilation and execution in a time-sharing environmeni Proc F J C C 1966 9 B RANDALL C J KUCHNER Dynamic storage allocation systems C A C M Vol 11 No 5 May 1968 10 G RADIN H P ROGOWAY Highlights of a new programming language C A C M Vol 8 No 1 January 1965 11 K ElVERSON A programming language John Wiley and Sons Inc New York 1964 TRANQUIL: A language for an array processing computer by NORl\1A E. ABEL, PAUL P. BUDNIK, DAVID J. KUCK, YOICHI l\iURAOKA, ROBERT S. NORTHCOTE, and ROBERT B. WILHELl\,IS0N University of Illinois at Urbana-Champaign Urbana, Illinois INTRODUCTION Figure 1 also shows the essential registers and paths in the CU and their relations to the PE's. Instructions are decoded and control signals are sent to the PE array from the control unit. Some instructions are executed directly in the CU; e.g., the loading of CU accumulator registers (CAR's) with program literals. Operand addresses may be indexed once in the CU and again separately in each PE. It is possible to load the local data buffer (64 words of 64 bits each) and CAR's from PE memory. Local data buffer registers and CAR's may be loaded from each other. A broadcast instruction allows the contents of a CAR to be transmitted simultaneously to all PE's. It is often convenient to manipulate all PE mode bits or a number from one PE in a CAR. For this purpose, the broadcast path is bidirectional. TRANQUIL is the algoritlunic language which will be used to write programs for ILLIAC IV, a parallel computer which has been described by Barnes et aZ. 1 ILLIAC IV is designed to be an array of 256 coupled processing elements (PE's) arranged in four quadrants in each of which the 64 PE's are driven by instructions emanating from a single control unit (CU). Each of the 256 PE's is to have 2048 words of 64 bit semiconductor memory with a 250 nanosecond cycle time and an instruction set which includes floating point arithmetic on both 64 bit and 32 bit operands with options for rounding and nonnalization, 8 bit byte operations, and a wide range of tests due to the use of addressable registers and a full set of comparisons. The PE's differ from conventional digital computers in two main ways. Firstly, each is capable of communicating dat.a to its four neighboring PE's in the array by means of routing instructions. Secondly, each PE is able to set its own mode registers, thus effectively enabling 01' disabling itself for the transmission of data or the execution of instructions from its CU. Figure 1 shows 64 PE's, each having three arithmetic registers (A, B, and C) and one protected addressable register (S). The registers, words, and paths in Figure 1 are all 64 bits wide, except the PE index registers (XR), mode registers, and as noted. The mode register may be regarded as one bit which may be used to block the participation of its PE in any action. The routing registers are shown connected to neighbors at distances ± 1 and ±R; similar end around connections are provided at 1, 64, etc. Programs and data are stored in PE memory. Instructions are fetched by the CU in blocks of 8 words as required and are stored in a 64 word CU instruction buffer. The four control units may be operated independently, as pairs, or all together. In the united configuration, all 256 PE's are effectively driven by one CU and routing proceeds across PE boundal ies. This allows some flexibility in fitting problems to the array. If ILLIAC IV, or any other parallel array computer, is to be used effectively, it iH es.."ential that a.lI possible parallelism be detected in those algorithms which are to be executed by that computer. This is difficult, if not impossible, if the algorithms are specified in languages such as FORTRAN and ALGOL which es..<:;entially express all computational processes in terms of serial logic, as required for conventional computers. Since it is also more convenient for the user to express array type computation processes in terms of arrays and parallel operations, rather than having to reduce the the inherent parallelism to serial computational form, the specification of a new language for array processor computation is clearly necessary. 57 Spring Joint Computer Conference, 1969 58 r------ --- ------ -- ---- --- - - ---- --- --- -----------..., I I INSTRUCTION AND DATA FETCHING I I I I I I I I i I I INSTRUCTION BUFFER I I I I I 1111 :e I INSTR. FETCH REQUEST I:' I'" It:: 1 [I 1 64 WORDS OAT< I 10 1 ASSOCIATIVE array operators, and revised loop specifications, including the addition of the set concept. Some of the ideas embodied in TRANQUIL follow similar constructs in other languages, e.g., the index sets in ~lAD­ CAP3 and the data structures and operators in APL.4 The syntax of the current version of the TRANQUIL language is specified in Appendix B. MEMORY 1 lID IN I;;; I Data structures ,CAR 0 I I INSTRUCTION DECODER I I : 1_- C U IWEXING CAR 3 ----- -- -- -------------t----------------it ---1 CONTROL UNIT , P E CONTROL SiGNALS DATA FETCHING I A -r 64 57 2048 C S R --!:...- ~ S i+l R ~ 2!!..J i+ i-1 2 9 ~ -8 • •• I MODE I I : 8 C I • MIR MIl PE MEMORY PE PE MEMORY MEMORY PEi PE64 MIR L I- :is-l PE 1 Figure l-Il..LIAC IV quadrant configuration into blocks for array storage The TRANQUIL language has been designed to achieve both simpler specifications of, and explicit representation of the parallelism in, many algorithms, thus simplifying the programmer's task and maximizing the efficiency of computation on a computer such as ILLIAC IV. An overview of the software and application programming effort for the ILLIAC IV system has been given by Kuck. 2 The data structures which are recognized in TRANQuIL are simple variables, arrays and sets. All data structUres, and quantities such as labels, switches and procedures, must be declared in some block head as in ALGOL. The data type attributes are INTEGER, REAL, COMPLEX and BOOLEAN. Certain precision attributes also may be specified. A mapping function specification must be associated with every declaration of an array. The judicious choice of mapping functions is crucial to the efficient use of ILLIAC IV. Arrays must be mapped so as to optimize I/O transactions, minimize unfilled wasted areas of memory, and keep most of the PE's busy most of the time. In many array operations it is necessary to operate either on a whole row or a whole column of an array. All the PE's would be kept busy in the former case (one operand in each PE) but in the latter case all operands would normally be in only 1 PE. However, by specifying the skewed mapping function which rotates the i 1st row across i PE's, columns as well as rows of the array can be accessed simul~ane­ ously. The more commonly used mapping functions such as STRAIOHT, SKEWED, SKEWED PACKED, and CHECKER are included in TRANQUIL. Array bounds may be specified dynamically, as in ALGOL, but all other attributes are nondynamic, for example: + REAL SKEWED ARRA Y A[I:M, I:N] The 'J'RANQUIL language An important consideration in designing a language such as TRANQUIL is that the expression of parallelism in the language should be problem oriented rather than machine oriented. This does not, and should not, preclude programmer specification of data structure mapping at run time, but once the storage allocation has been made the programmer should have to think only in terms of the data structures themselves. Secondly, the means of specifying the parallelism should be such that all potential parallelism can be specified. The structure of TRANQUIL is based on that of ALGOL; in fact, many ALGOL constructs are used with the addition of furt.her data declarations: standard The user who wishes to specify his own mapping function may make use of a PE memory assignment statement. For example: PEME1lfORY PB [1 :10, 1 :64]; PEM FOR (I, J) 81M ([1, 2, ... , 10] X [1, 2, .. .',64]) DO PB [I, J] +- B [I, MOD (64, I + J - 1)]; REAL ARRA Y (PB) B[l :10, 1 :64]; where 81M is discussed in a later section, establishes virtual space of size 10 X 64 in PE memory, and then TRANQllL: stores a 10 X 64 array B there in skewed form. Thus, instead of making up the aforementioned subarrays out of an array declaration, space reserved in PE memory may be used. In the program, the programmer refers to an element of memory space via the assigned array name B and its subscripts, as usual. It should be noted that storage mapping functions can not be specified dynamically. Should remapping of data be required, an explicit assignment statement may be used; e.g., to change the data in an array B from skewed to straight storage an assignment statement Af-B INCSET JJ ftfONOSET II [27, 6], KK [75, 75] GENSET A [150,100] PATSET P(3) [0:20,0:20, -5:15, 10] The monotonic set II is to have at most 6 one-dimensional elements the integer values of which are 1~,.. .1..L\.i ;'" .L.l..l. +1,.", UJ..L'l.I "0"-"""'" U.LL5"'" ..L r1 '>"71J. l..L,~. or arrays. All meaningful combinations of operands and attributes are valid; e.g., if A and B are matrices then AlB will mean A X B-1 if B has an inverse and the dimensions are correct. The result of a relational operator operating on two matrix operands is reduced to a single logical value through use of the qualifiers ANY and ALL, e.g., ANY A < B or ALL A 1). The declarations also may specify bounds for the integer values of the components of the n-tuple set elements, in ways analagous to the specification of array SUbscript bounds in ALGOL and FORTRAN, and an upper bound for the number of elements in the set. Some examples of set declarations are +'" UV 59 '"Ph,.. ..L J....1.V +U.1..LJ. 1,. ..\..I\..I-\A..1..l..L.l.v.LLQ.l.V.LLUJ,. ",,,, .rl~ ....... nn"';"'T>n 1 pattern set P is to have at most 10 3-tuple elements the first two components of which will lie in the range [0,20] and the third components will be in [-5, 15]. Expressions Expressions which can be formed in ALGOL can in general, also be formed in TRAKQUIL. In addition arithmetic, logical and relational operators, and function designators may be used on arrays. The meaning of an operator is determined by its corresponding operands, which may be simple variables SET2 f- [1, 2, 3, 4, 5, 6, 7, 8] SET3 f- [1, 2, ... , 8] SET4 f- [-2, P, Q, 25] SET5 f- [[10, 10], [9, 8],[ 8, 6]] where SET2 and SET3 are equivalent definitions and SET5 is a 2-dimensional pattern set. Replication factors may be used in general sets. For example: SET6 f- [1(3),4, 5(2)] is equivalent to SET6 f- [1, 1, 1, 4, .'5, .5] A useful device for the generation of a set is the run -time comparison of data values in parallel. For example, if A and B are vectors stored across PE memory, A = {-I, 3, 2, 10} and B = {2, -3, 1, 12} , then the operation SET7 f- SET [I : A[1] < B[1]] where I takes on the values 1, 2, 3, and 4 simultaneously, generates the set [1, 4], the order being defined as monotonically increasing. These definitions are readily extendible to multidimensional pattern sets which are generally used for picking scattered values in an array for simultaneous operation. The set operators INTERSECT, UNION, and COMPLEMENT (a binary operation equivalent to the relative complement) may be used in TRANQUIL and always result in the generation of a monotonic set by reordering elements if necessary. The two additional set operators CONCAT and DELETE do Spring Joint Computer Conference, 1969 60 not result in reordering of the elements. Some examples of set operations are: if R = [1, 2, 3,4, 5] S = [2, 4, 6, 8, 10] I, where {} means one of the alternatives separated by the scope is the statement S, n is an integer, L(i = 1, ... , n) are control variables, and IIi (i = 1, ... , n) are i-dimensional set identifiers or literal set definitions. The use of this statement is illustrated by the following examples. a. FOR (I, J) SEQ ([1, 2, ... , 10], [5, 10, ... , 50]) DO T = [6, 4, 6, 5, 6, 7] U = [100,40,0, 13] A[I] then ~ B[I + 1] + C[J] is evaluated as RUNION U is [0, 1,2, 3, 4,5, 13,40, 100] A[I] R CONCAT Sis [1, 2, 3, 4,5,2,4,6,8, 101 T COMPLEMENT R is [6, 7] T bELETE R is [6, 6, 6, 7] [1, 2] X [3,4] , [5, 6] is [[1,3,5], [1,4,6], [2,3,5], [2,4, 6]] where , has higher precedence t.han X. C[5]; + C[10]; B[II] + C[50] b. FOR (I) SEQ ([2, 4, 6]) WHILE I A[I] ~ < A[I] DO B[I] - A[I] will continue looping until the Boolean expression is FALSE or the index set has been exhausted. As in ALGOL, no pass through the loop is made if the value of the Boolean expression is FALSE after the index variable is assigned the initial value of 2. c. FOR (I, J) SEQ ([1, 2, 3,4], [5, 6]) DO Control statements Control statements in TRANQUIL are used to designate sequential loops, simultaneous statement execution, and the usual conditional and unconditional transfers of control. Index sets play an integral part in these control statements. They are used as a source of values fO! iterative or loop control, and as a means of simultaneously specifying a number of array elements. Their association with the enablement and disablement of PE" b should be obvious. Sequential contr()l: The SEQ statement Sequential control refers to the existence of a loop through which designated index variables take on the values of a set or sets, one element at a time. It is written in the following general form : FOR (11, ... , 111 ) SEQ (Ill {X ~ + Note that the comma between the two set definitions denotes pairwise ordering for the control variables values. [1, 2, 3, 4] , [2, 4, 6, 8] is [[1, 2,] [2, 4], [3, 6], [4, 8]] is [[1, 3], [1, 4], [2, 3], [2, 4]] B[2] A[2] ~ B[3] A[10] .. Fih~uy, it is possible to create sets with multidIIDertsional elements out of sets with scalar elements through use of the pair (,) and cartesian product (X) set operators, e.g., [1, 2] X [3,4] ~ I ,} ... {X I ,} lIn) { (empty) I W H I LE (Boolean expression)} DO S B[I, J] (- A[I, J] In this case the difference in size of the two defined sets is resolved by considering only the pairs (1, 5) and (2, 6), that is, the exhaustion of the smallest index set signals the end of the loop. To indicate otherwise an asterisk is placed after the set the exhaustion of whose elements is to be used as the stoppin h condition. This means that any other sets which run out of elements before completion will be repeatedly used as many times as necessary. If the previous statement is rewritten as FOR (I, J) SEQ ([1, 2, 3, 4]*, [5,6]) DO B[I, J] ~ A[I, J] the result is B[I, 5] (- A[I, 5]; TRANQUiL B[2, 6] ~ A[2, 6]; B[3, 5] ~ A[3, 5]; B[4, 6] ~ A[4, 6]; d. FOR (I, J) 8EQ ([1, 2] X [6, 7, 8]) DO A[I, J] ~ 61 Some examples of the use of SLM are: a. FOR (I, J) Slllf ([1, 2, 3]*, [4, 5]) DO A[I, J] ~ B[J, I] is evaluated as B[J, I]; A[l, 6] ~ B[6, 1]; A[l, 7] ~ B[7, 1]; A[l, 8] ~ B[8, 1]; A[2, 6] ~ B[6, 2]; A[2, 7] ~ B[7, 2]; A[2, 8] ~ B[8, 2]; where the lengths of the two sets do not create the problem that occurred with the pairwise operator. This example also illustrates that the frequency of element change is greatest for the rightmost set used. Simultaneous control: The SIM Function and the SIM Statement The parallel structure of ILLIAC IV is' utilized in TRANQUIL by the specification of simultaneous control functions and statements. The general form of the 81M function is: 81M BEGIN (assignment statement); ... ; (assignment statement) END where the enclosed assignment statements are executed simultaneously, i.e., the data used by anyone of them are the data available before the 81.Af function was encountered. The general form of the 81jt/ statement for simultaneous control is: FOR (II, ... , La) 81M (Ill f X I ,l ... t X I ,} lIn) DO S ., . . 81M BEGIN A[l, 4] ~ B[4, 1]; A[2, 5] ~ B[5, 2]; A[3, 4] ~ B[4, 3] END b. FOR (I, J) 81M (II, X JJ) DO BEGIN C[I, J] ~ 0; FOR (K) 8EQ (KK) DO C[I, J] ~. C[I, J] + A[I, K] X B[K, Jl END is a general routine for the multiplication of two com patible matrices A and B if the index sets II and JJ specify the rows of A and the columns of B, respectively It should be noted that when a set is used in a sequential or simultaneous control statement, it cannot be altered within the scope of that statement. Nested 8EQ and SIM statements The 8EQ and 81M control statements described above may be nested. The effect of nesting is clear except when a 81M statement occurs within the scope of another 81ll! statement, in which case statements inside the scope of both are executed under the control of sets which are related by the cross product operator, for example: FOR (I, J) 81M (II, JJ) DO where m, n are integers, Ii (i = 1, ... , n) are control variables, IL (i = 1, ... , m) are k-dimensional sets (0 < k :::; 7), n equals the total number of dimensions of all IIi, and S is a statement. For this statement each substatement Si of S is executed with the data available before it is reached, i.e., just as if a 81M function was placed around each S,. In this regard it is important to note that simultaneous control is not loop control, but designates that each Si is to be executed in parallel and thus the order of the associated sets is not important. BEGIN FOR (K) 81M (KK) DO BEGIN Area A END; END 62 Spring Joint Computer Conference, 1969 where the control statement in effect in area A is, in effect, The TRANQUIL compiler and its implementation Introduction FOR (I; J; K) 81M (II; JJ X KK) DO If clauses General forms: a. IFSET (indexed Boolean expression) THEN b. IF {FOR (II, ... , In) SIM (III {XL} ... {x I,} IIm)\ (empty)} {ANY\ALL\ (empty)} (Boolean expression) THEN If clauses may be used in arithmetic, Boolean, set and designational expressions. The Boolean expression in form (a) must involve a control variable under SIM control and thus not have a single logical value. This is meaningful in arithmetic and Boolean expressions of assignment statements having left parts which use the same control variable, and also in conditional statements where the control variable is used in the left part of some associated assignment statement, An example of this use is: FOR (I) SIM ([1, 2, ... , 100]) DO T[I] ~ IFSET A[I] ELSE B[I] < B[I] THEN A[I] Array blocking and storage allocation is equivalent to FOR (I) SLY ([1, 2, ... , 100]) DO IFSET A[I] < ~ B[I] THEN T[I] ELSE T[I] ~ A[I] B[I] In either form T[I] ~ A[I] for all values of I for which the value of the Boolean expression is T RUE and T[I] ~ B[I] otherwise. The form (b) results in only a single Boolean value based on the ANY or ALL modifier, and the scope of the SIM control (if explicitly present) extends over the Boolean expression only. If the vector A of length 2 has elements 5 and 10, the if clause test IF FOR (I) SIM ([1, 2]) ANY A[I] < 7 has the value true since A[l] < 7. The same result is achieved by use of the if clause IF ANY A <7 The syntax of TRANQUIL has been specified in a form which is accepted by the syntax preprocessor of the Translator Writing System (TWS)5,6,7,8 being built at the University of Illinois. The preprocessor automatically generates the parsing algorithm for the compiler. In pass 1 of the compiler the recognition of source code constructs invokes calls, via the action numbers embedded in the syntax definition, to semantic actions. These actions build descriptor tables containing' in part, information about declaration types, attributes, and block structure, and transform the source code into an intermediate language form which is composed of operators and operands, the latter being references to the descriptor tables. Pass 2 is the main body of the compiler. The intermediate language stream is read and operators call pass 2 semantic actions (on the basis of their context) for generation of assembly language instructions using associated operands. A number of other important considerations arise, among which are the storage of arrays and sets, and the efficient allocation and use of CU registers. These problems and some solutions are discussed in the following sections. The compiler partitions all arrays into 2-dimensional blocks the maximum size of which is 64q X 64q words (q = 1, ,2, or 4 according as 1, 2 or 4 quadrants of 64 PE's are being used) since ILLIAC IV may be regarded as an array with 2048 rows (number of words in a PE) X 64q columns (number of PE's). For the purposes of this section it will be assumed that q = 1. The sizes of the blocks obtained by the array partitioning then fall into 4 categories: a. 64 X 64 b. m X 64 c. 64 X n d. mXn m, Il < 64 which are called SQUARE, HBLOCK, VBLOCK and SBLOCK, respectively. Small blocks belonging to the same array are packed together to form a larger block, details of which are given' by Muraoka.9 Figure 2 illustrates the partitioning of a 3-dimensional array into 12 blocks and Figure 3 illustrates how the smaller subblocks are packed together to form larger blocks. The partitioning of an array into blocks is independent of the mapping function; i.e., for a SKEWED array skewing is done after partitioning. TRAL~QUIL ~~------15------~~ 64 63 "~t----48 .... - -~."I 11 PACKING VBLOCKs 75 0 64 1 T1------- 64 2 11 3 33 A[1. *. *] 30 11 6 1 I I 2 I 50 :4 5 I HBLOCKs PACKING SBLOCKs 10 I I I PACKING Figure 3-Block packing for array A[l :3, 1 :75, 1 :75] _______ ..JI A[2. 50.30] 6 7 v 9 10 11 Q A[3. *. *] Figure 2-The partitioning of array A[l :3, 1 :75, 1 :75] into blocks for array storage All array operations and data transfers between ILLIAC IV disk and PE memory are done in terms of these blocks. A block of size m X n may be placed in any m adjacent words (rows) stored in n adjacent PE's in PE memory. Blocking facilitates the use of arrays which are larger than the PE memory. All data are normally stored on the 109 bit ILLIAC IV disk and blocks are only brought into PE memory (at a transfer rate of .5 X 109 bits/second) as required. The TRANQUIL compiler automatically generates block transfer I/O requests, which are handled by the operating system. Thus, it is possible to write a TRANQUIL program which includes no explicit data transfers. ThA AffAt>t.l'tra: Q.rlrll"AQQ nf Q.n'tr Q.1"rQ.V A1ATnAnt. u ............. _ ............J ........... _ ..............",..... "' let ..- nht.Q.lnM . - .......- _ .....a. _ _ ---~ ~"'-J --~~~ by computing the block number, which determines an absolute base address (the address of the upper leftmost element of the block if the block is in memory) and a relative address within that block. The block number for an element A[h, i2, . , " in-l, in] of an array declared (( ... ((it - (l)M2 + (i2 - t,»Ma · + . . . (i,,_2 - (,.-2» M,._~ + i,,_~) M: + i~ , Spring Joint Computer Conference, 1969 64 where lUi = Ui - ~J i = (l\L fi + 1, + 63)div 64, i~ = (h - fk)div 64 . If the array is SKEVVED the relative PE number and relative PE address of the element in the specified block are given hy and respectively. After skewing of the blocks in Figure 2, the element A[2, 50,30] is specified by the block number, and PE number and PE address relative to the base address of the block, which have values 4, 14 and 49, respectively. In most cases some or all of the elements in a row or colunm are used simwtaneously. In the case of column operation, for example, each PE can simultaneously compute the relative address (index value) which it will require. In allocating memory space for a block a linked space list, which keeps track only of the nunlber of rows of memory which have been used, is utilized. If a block of size m X 64 is to be stored, the list is searched to locate a space of m adjacent rows and the block is stored there. In the case of a block of size m X n (m, n < 64) 64 rows of PE memory may be allocated and a sublist corresponding to this 64 X 64 block of storage is established. The sublist consists of a Boolean array in which each bit represents the use or otherwise of each 8 X 8 subblock of the associated 64 X 64 block of storage, thus allowing several small blocks to be stored together in a larger unit. The storage and use of sets Associated with the introduction of sets in TRANQuIL is the task of finding storage schemes which can be used efficiently. Sets can be used for loop control, for enabling or disabling PE's, or for PE indexing. The increment set can be used in all three ways and is stored using two words per. set. One word contains the a.~t element, the increment, and the lilY'it packed for use by CAR instructions. The other word is used as a bias value in the case where negative elements are, or may be, in the set. When an increment set is used for sequential control, CU test and increment instructions operate on the appropriate CAR register. When an increment set is used for simultaneous control, it can be expanded at run time into mode words or explicit numbers. Mode words are 64-bit words used to store the elements of a set by position number, where a 1 in the n-th bit indicates tbat n is an element of the set. These words are most frequently used in PE mode registers to enable and disable PE's. Mode words can be generated from an increment set by using a memory row that contains the PE numbers in ascending and descending order and regular mode patterns similar to the 4 PE system shown in Figure 4. In the figure the mode pattern was formed by considering the bo bits to be all ones, the b1 bits to be alternating zeros and ones, the ~ bits to be two zeros alternating with a one, and finally the b s bits to be three zeros alternating with a one. In the general 64 PE case, the word in the i-th PEis I :\Iode pattern 63-il where the 32-bit mode pattern results by considering the bo bits to be all ones: i.e., all PE's on when in use, the b1 bits having the pattern 0101. .. , the ~ bits 001001. .. , and the b i bits O,JO,:1 where 0" stands for i zeros. N ow consider the example of expanding the increment set JJ of Appendix A into mode words and explicit numbers. The set JJ is used simultaneously in forming the comparison set KK by a Boolean test on the skewed arrays A and B. For a given I every other element of A, as signified by JJ, is moved to the A register in the PE's, using the base address of A that has been brought to the CU data buffer as indicated in Figure 5. Every other element corresponds to the hI bit mode pattern, this pattern appearing in the PE mode positions of Figure 5 which is based on Figure 1. The case for I = 2 is shown. Every other element of the I -th column of B is moved to the B register. In this case every other ascending PE number is used in the PE index registers, XR, with appropriate routing to account for the skewed storage. For I = 2 Figure 1-:\'!ode patterns and explicit v3.1ues for increment sets TRANQUIL CU storage allocation and use LOCAL DATA aUFFER 100000001001010000010011 II MOOE WORD BASE ADDRESS OF A BASE ADDRESS OF a ACAR REGISTER I J J IN MODE FORM R E G I / I / 1 0 / 1 7 1 I 0 'x I 1 'x I0 A A[ 2. 63] A[2. 1] A[2. 61] ~ a a[63. 2] a[ 1. 2] a[61. 2] 61 A[0, 63] 5 T S XR M E M o R y I A[ O. 0] A[ 1. 63] A[ 2.62] .. . PEO 1 I I 1] A[ I, 0] A[ O. 2] 1 1 A[O. 3] A[ 1. 1] A[l. 2] A[ 1,62] A[2.63] A[2. 0] A[2. 1] A[ 2. 61] 63 A[ 0, .. . 65 ... ... PE3 PEz Figure 5-PE and CU status for I .. . = 2 in the example problem in Figure 5, an end around route of two is necessary. Every other element of a column is fetched to the B register again by the use of JJ in mode form. The sets II and KK in Appendix A are examples of monotonic sets and are stored in mode form. For looping on II the CD does leading ones detection on the II mode pattern, illustrated in Figure 5, to determine the explicit set elements used in the .CAR as CD indexes for array A, and KK is used in mode form in the PE mode registers under simultaneous control. Monotonic sets can also be stored as explicit numbers for index use. The general set is always stored in explicit form, for obvious reasons, and pattern sets are stored as mode words. The actual management of mode and explicit storage schemes involves the use of a permanent storage area and a stack. All set defInitions are stored in the perrr...anent storage area except comparison sets. The stack is used for storing current set values that are obtained from the permanent area or generated by the user or compiler. The stack is also used because program flow is not known at compile time, in general, due to data based branches, and thus changes in these sets are unpredictable. In PE memory the storage of either the mode or explicit set representation begins on an 8 word boundary to make best use of the 8 word CD fetch capabilities. Further details of the handling of sets are given by Wilhelmson. 10 The allocation and use of CU registers is a very important ILLIAC IV problem since CU instructions which caIUlot be overlapped with PE instructions leave all PE's idle. The allocation of CU registers for needs known at compile time is accomplished by calling one of a group of procedures that have an underlying allocation priority system and that use compile-time pointers to and from important tables and storage locations. The local data buffer is divided into two parts: the lower part for use as determined at compile time and the upper part for dynamic use at run time. The lower part is further divided into three parts. The first is one word used for bit storage and later testing. A list of free bits is kept, bits being assigned on a space available basis. The second part is 16 words in length, where the use of this space is kept to low priority requests unless space is needed for high priority requests. Priorities range from 0 to 3 and are assigned by the compiler writer, these assignments being based on intuition and experience. The third part has n words (0 ~ n ~ -17), where the optimal value of n is yet to be determined. The space is used as much as possible for high priority requests. The reason for this device is to try and keep low priority requests in the lower area, since the lower area will be used to store 8-word blocks transmitted to the CU. When the local data buffer becomes full a word is freed, with appropriate storage and pointer modification if necessary. Thus a user can let the procedures free words when necessary unless he wishes to do so earlier. Three of the CAR registers are allocated using the same priorities as in the local data buffer. The fourth is a free register which may be used in a variety of ways. Another CD problem is connected with its particular data composition, and results from transfers. For example, at the begininng of a loop data in the CD has a certain composition. This composition should be reinstated each .time through the loop. This is made possible by remembering the composition of the CD data at the beginning of the loop. For backward transfers code to set up the CU properly is placed at the jump point while for forward transfer code is placed at the location transferred to. The priority scheme may appear to add to the problem of moving words in and out of CU memory at transfer points. This scheme has been developed since 8-word block stores to PE memory are not allowed; only one word at a time can be stored in PE memory by the CU. 66 Spring Joint Computer Conference, 1969 Assignment statements The use of sets, the notion of S1j}/, the number of different types of arithmetic and storage schemes, combined with the need to compile efficient code for a parallel machine necessitate a substantial analysis of each assignment statement. We now consider this analysis as it is carried out in pass 2 of the compiler. The analysis is effected in several passes over the postfix intermediate language. Consider the last assignment statement in the example in Appendix A: A[I, K] +- A[I + 1, K] + B[I, K + 1] ; Before we even begin to generate code a decision must he made as to which index is to be proces..'3ed simultaneously (i.e., across the PE's) and which is to be done sequentially. The first pass over the intermediate language determines this and also copies the intermediate language into a table to be used for future passes. When a set linked * identifier is entered in the table, additional information provided by the set definition or declaration is also entered. In the case of I, which is linked via 81M control to II, the set is known exactly and precise information from the set definition is entered in the table. For K the compiler makes an estimate of the size and density of the set based on the upper bounds given in the declaration ofKK. In general, when operations are performed on pairs of subscripts or pairs of subscripted arrays, infor-: mation about the interaction between these subscripts must be generated. For example, in the case of the subscript expression I + 1 in the example above, the addition of 1 in no way alters the size, density, or type of the set. Thus, the information provided for I will be recopied with the + operand. After the subscript expression has been processed, a check is made to see how well the type of set resulting from the index expression will work with the particular dimension of the array involved. In the example there are oniy two-dimensional skewed arrays in which either columns or rows can be easily accessed in parallel. If one of the arrays were straight, then at. this point. it would be discovered that no set will work weI] for the column index, because each column is stored in a single PE. This information plus information about the set density, set size, and the array size are all combined to compute a probable efficiency; i.e., the number of PE's that will probably be enabled if this index were varied simultaneously. Of course, it is * We say that I SIlr! (II) DO. is set linked to II in a stat.ement like FOR (I) easy to think up cases in which the estimate will be totally wrong, but in most practical cases encountered, the estimate is reasonable. A table of these probable efficiencies is generated for each set. If the set appears in different subscripts, then on the second occurrence the new estimate is set to the minimum of the previous and present estimates. When the end of the assignment statement is reached, the table of probable efficiencies is sorted and the result of this determines the order in which the indexes will vary. In the example K will be the index chosen to vary across the PE's because the set II is known to be small (6 elements) and the declaration of KK holds the probability of it being fairly large. Now an outer loop must be compiled to generate sequentially the elements of II. Finally, the remainder of the statement is compiled. The effect of the code that is compiled for the example assignment statement foHows. One local data buffer location is set aside as an index to the mode words of KK. Four more locations are set aside for the base addresses of the subblocks of the arrays A and B. The first mode word for KK iR loaded and the leading ones detector is used to set the first value of K. This value, plus the base address of A, plus 1, plus the index set 0, 1, 2, ... , 63 in the PE index registers is used to access the first colwnn of A. In a similar manner the address for the first row of B is fetched, loaded into RGR and a route left one PE is performed The addition is executed and the first mode word for KK is used to store the result in A. N ow the same process is repeated for the next sub block of A, except that the mode pattern for KK must be ended with a word having Ill's followed by O's, because the second sub block of A is only 11 words wide. Additional complications, such as pairwise 81M control specification, small sub arrays , and 81M blocks add to the complexity, but not to the substance, of the algorIthm outlined above. It is clearly impossible to efficiently compile a single short assignment statement for ILLIAC IV, but it is conceivable that a large number of simple assignment statements could be integrated into a fairly efficient ILLIAC IV program. Incorporating such a feature into a compiler presents two basic problems. The first is an algoritlun for efficiently integrating a large number of interrelated assignment statements. Ordinarily the simple assignment statements will be scattered throughout the program. Also, many of the sequential calculations that are prime targets for an integration scheme are likely to be embedded as sUbexpressions in assignment statements containing 81M controlled variables. Filtering out and gathering together these candidates TRANQUIL Figure 6-The tree structure for a set of interrelated arithmetic statements for the integration scheme constitutes the second problem. Figure 6 is a tree structure for the set of assignment statements: A+-B+CXD E+-L+B-C F+-G+HXI K+-A+E+F No node on this tree can be calculated until all nodes on subbranches have been calculated. The method of computing such a tree on ILLIAC IV involves first mapping assignment statements into PE's, in a more or less arbitrary manner. The assignment statements are restricted to a small num ber of operations like addition, subtraction, multiplication and division. ILLIAC IV can only perform one of these operations at a time. A count of the number of PE's that can take advantage of each of these operations is made and that operation which will be executed by the most PE's is the one that code is compiled for. Then the PE counts for all operations are revised and the process continues until all calculations have been perfonned. A similar algorithm is used to do routing to bring the results computed in one PE to the PE's where they are needed. This algorithm is invoked 67 whenever the number of PE's eligible for any operation falls below a certain limit. The problem of gathering together assignment statements for processing by this method is many faceted. What is desired is a rearrangement of the program where simple assignment statements, simple subexpressions, and simple expressions generated by the compiler, like address calculation, have been brought together at several collection points. To rearrange code in this manner requires an extensive analysis of the· overall program to determine what subexpressions and statements can be moved, and how far. This analysis is carried out at the intermediate language level. The collection points are determined to be at the beginning of blocks, subexpressions are moved as physically high up in the code as possible, except that they are not moved past a block head unless they can be moved to the head of an outer block. The method produces a number of bonuses. Calculations inside loops tend to be moved outside when logically permissible. Thus, it is profitable to move nonsimple subexpressions also. Further, duplicate subexpressions can easily be eliminated because they tend to gather at the same point. Finally, for each block a record is made of what variables are nondynamic within that block. Thus, in pass 2, any expressions generated using these variables can be added to the collection of subexpressions at the beginning of the appropriate block. At the head of this block, a transfer tQ the end of the block is compiled, and when all code in the body of the block has been generated, the complete collection of assignment statements is compiled followed by a transfer back to the beginning of the block. More details of this type of analysis are given by Budnik.l1 SUMMARY Designing and implementing a language and its compiler for ILLIAC IV presents a number of problems not encountered with procedure oriented languages for sequential machines. In the design of the language these problems have been met, primarily through the use of sets as indexes and the introduction of language elements for explicit denotation of simultaneous operations. Experience has shown that the resulting notation is as easy to learn as that of conventional languages and in most instances it is more concise. The task of efficiently compiling a language such as TRANQUIL for the ILLIAC IV is more difficult than compiling for conventional machines, simply because the standard compiling techniques are inadequate, thus requiring new compilation algorithms to be 68 Spring Joint Computer Conference, 1969 invented. These techniques will undoubtedly be refined as further experience is gained with the use of ILLIAC IV and parallel languages. However, the completion of the major paris of the TRANQUIL compiler has already demonstrated that reasonably efficient object code can be generated for a large class of array-type problems which have been programmed in TRANQUIL. Several features of TRANQUIL have been omitted from this paper, notably input/output statements and procedures. Execution time input/output will be from/to the ILLIAC IV disk (secondary storage) in blocks of data. Most of these data transfers will be implicitly specified in TRANQUIL programs. However, some explicit specification of unformatted data transfers win be provided. The provision of additional software to iacilitate format specified transfer of data between external peripherals (tertiary storage) and the ILLIAC IV disk is planned. The specification of procedure declarations, and their use in a parallel environment, is under investig(8.tion. Additional features being considered for later incorporation into the TRANQUIL compiler include overlayable code segments, quadrant configuration independent code, and more specialized data structures and mapping functions. Although aspects of the language and its compiler are still being developed, it has been demon8trated that TRANQUIL is a highly satisfactory and useful complement to the ILLIAC IV hardware system design. ACKNOWLEDGMEKTS The research reported in this paper was supported in part by th.e Depa...~ment of Computer Science; University of Illinois at Urbana-Champaign, and in part by the Advanced Research Projects Agency as administered by the Rome Air Development Center, under Contract No. USAF 30(602)4144. APPENDIX A: A SANIPLE TRANQUIL PROGRAM BEGIN REAL SKEWED ARRAY A, B[I:75, 1:75]; INCSET JJ; MONOSET lI(l) [27, 6], KK(l) [75, 75]; INTEGER 1,.1, K; II +- [2, 10, 13, 15, 21, 24]; .JJ +- [2, 4, ... , 74]; FOR (I) SEQ (II) DO BEGIN FOR (.1) SIM (.JJ) DO KK +- SET (J: A[I, J] < BfJ, I)); REFERENCES 1 G BARNES R BROWN M KATO D KUCK D SLOTNICK R STOKES 'Phe ILLIAC IV computer IEEE Transactions on computers Vol C-17 746-757 August 1968 2 D J KUCK ILLIAC IV software and applications programming IEEE Transactions on computers Vol C-17 August 1968 758-770 . 3 M B WELLS Aspects of language design for combinatorial computing IEEE Transactions on computers Vol EC-13 431-438 August 1964 4 K E IVERSON A. programming language John Wiley New York 1962 5 R S NORTHCOTE The structure and use of a compiler-compiler system Proc 3rd Australian computer conference 1966 6 F L DEREMER On the generation of parsers for BNF grarn·mars: an algorithm Proc S J C C 1969 7 A J BEALS The generation of a deterministic parsing algorithm Report No 304 Dept of Computer Science University of Illinois at Urbana 1969 8 H R G TROUT .1 BNF like language for the description of syntax directed compilers Report No 300 Dept of Computer Science University of Illinois at. Urbana 1969 9 Y MURAO}(A Storage allocation algorithms in the TRANQUIL compiler Report No 297 Dept of Computer Science University of Illinois at Urbana 1969 10 R B WILHELMSON Control statement syntax and semantics of a language jor parallel processors Report No 298 Department of Computer Science University of Illinois at Urbana 1969 11 P P BUDNIK TRANQUIL arithmetic Report No 296 Dept of Computer Science University of Illinois at Urbana 1969 TRANQUIL FOR (K) SL7tl (KK) DO A[I, K] ~ A[I + 1, K] + B[I, K + 1] END; FOR (I, K) SIM (II X KK) DO A[I, K] ~ A[I + 1, K] ElfD + B[I, K + 1] APPENDIX B: A SPECIFICATION OF THE SYNTAX OF TRANQUIL A brief description of the syntax metalanguage is given in APPENDIX C. B.1 Program (PROGRA?\I) :: = (BLOCK) (BLOCK) :: = BEGIN list [ (DECLARATION) ffo;] list (STATE:\lENT) separator ffo ; [ffo;) END; (STATEl\IENT) :: = (NONE?\IPTY STATElVIENT) ! < ); (NONE1UPTY STATEl\IE~T) :: = [( * I) : ]* [(CONTROL STATEl\1ENT) I GO TO (DESIGNATIONAL EXPRESSION) I BEGIN (NONE:\JPTY STATEl\lENT) [ffo; (STATE~VrENT )]* END I (BLOCK) I, (IF CLAUSE) (STATEMENT) [ELSE (STATE2'1ENT )]& I (ASSIGN1'1ENT STATEl\1ENT )]; B.2 Declarations (DECLARATION) ::= (VARIABLE DECLARATION) I (ARRAY DECLARATION) I (PEl\I RESERVE DECLARATION) I (PE::\I ASSIGN:\fENT DECLARATION) (SET DECLARATION) I (SWITCH DECLARATION) I (LABEL DECLARATION); I B.2.1 Variable Declarations (VARIABLE DECLARATION) ::= (ATTRIBUTE) [COJIPLEX]& list (*1) separator, ; (ATTRIBUTE) :: = BOOLEAN I REAL I REALS I REALD I INTEGER Il'{TEGERS I IA"'TEGERL I BYTE8 I BYTE16 ; I B.2.2 Array Declarations (ARRAY DECLARATION) :: = [(ATTRIBUTE )]& [(l\lAPPI~G FUNCTION )]& ARRAY (ARRAY LIST) I [(ATTRIBUTE )]& ARRAY ( (PEl\ r AREA) ) (ARRAY LIST); (:\fAPPING FUNCTION) :: = STRAIGHT I SKEW/ED I SKElVED PACKED I CHECKEH: (ARRAY LIST) :: = list [list (*1) separator, (BOUND LIST)] separator, ; (BOUND LIST) :: = ffo[[list [[ * I ** I ffo I ffo ffo ]& (ARITHl\IETIC EXPRESSION) : separator, I list [( * I ** I$ I 

(ARITH~VrETIC

]&

(ARITHl\IETIC EXPRESSION)] separator,] ffo 1;
(PEl''! AREA) :: = (*1);

EXPRERRION)1

69

70

Spring Joint Computer Conference, 1969

B .2.3 P EM Reserve Declarations
(PEM RESERVE DECLARATION) :: = PEAMEMORY (PElVI AREA NAIVIE)
~ [(UNSIGNED INTEGER), (UNSIGNED INTEGER) ~ ];
(PE~1 AREA NA~,1E) :: = (*1);
(UNSIGN""ED INTEGER) :: = (* N);
B.2.4 P BM Assignment Declarations
(PEM ASSIGNMENT DECLARATION) :: =
PEJ.l1 [(PEM ASSIGNMENT CONSTRUCT)
BEGIlv list (PElVI ASSIGNl\lENT CONSTRUCT)
separator; END];
(PEl\1 ASSIGNl\;IENT CONSTRUCT) :: =
(PEM ASSIGNlVIENT STATElVIENT)
(SET ASSIGNMENT STATEl'lENT) I (PEl\l FOR STATEMENT);
(PEIVI ASSIGNlVIENT STATEl\tlENT) :: = (* I)
~ [[ (UNSIGNED INTEGER) (* I)],
[(UNSIGNED INTEGER) (* I)] ~] f - (* I)
~ [list (ARITH1\lETIC EXPRESSION) separator, ;i)$]; (PElV! FOR STATEMENT) :: = FOR ( (SET VARIABLE LIST» 8I;.1{ (SET NAME LIST» DO [(PEM ASSIGNlVIENT CONSTRUCT) BEGIN list (PEIVI ASSIGNl\IENT CONSTRUCT) separator; END]; I I I I I B.2.5 Set Declarations (SET DECLARATION) :: = [INCSET \ AMONOSET I GENSET \ PATSET1list (SET SEG::\IENT) separator,; (SET SEGl\tlENT) :: = list (* I) separator, [( (* N »]& [~[list [(ARITH~'lETIC EXPRESSION) [: (ARITHMETIC EXPRESSION) ]&] separator, ~]]&; B.2.6 Label and Switch Declarations (LABEL DECLARATION) :: = LA.BEL list (*I) separator,; (SWITCH DECLARATION) :: = SWITCH (*1) f - list (DESIGNATIONAL EXPRESSION> separator,; B.3.1 Control Statements (CONTROL STATEl\tIENT) :: = FOR (SET VARIABLE LIST» [SEQ I SI M] (SET N Ai\IE LIST» DO (STATEMENT) I FOR (SET VARIABLE LIST» SEQ (SET NAl\iE LIST» WHILE (BOOLEAN EXPRESSION) DO (STATEMENT) \ (SIM BLOCK); (SET VARIABLE LIST) :: = list (*1) separator,; (SET NAlVIE LIST) :: = list [(*1) [~ *]& I (SET DEFINITION TAIL)] separator [, I X]; (SIM BLOCK) :: = SIM BEGIN list (ASSIGN]\1ENT STATEMENT) separator ~; [~ ;]& END; B.3.2 Set Definitions (SET DEFINITION TAIL) :: = ~ [(LIST SET) ~] (CO~lPARISON SET); (LIST SET) :: = (ELEMENT) [, (ELEl\lENT ), ... , (ELElVIENT) , (ELE:\lENT)]* I (); (ELElVIENT> :: = ~ [list (.A.R1TH~fETIC EXPRESSION) separatorj .~] I I I TRANQUIL 71 (ARITHMETIC EXPRESSION) [( (ARITHMETIC EXPRESSION»]&; (CO.l\1PARISON SET) :: = SET$ [lisi (*1) separator,:
(BOOLEAN EXPRESSION) $]; BA DesignationaZ Expressions (DESIGNATIONAL EXPRESSION) :: = (SII\1PLE DESIGNATIONAL EXPRESSION) (IF CLAUSE) (SIMPLE DESIGNATIONAL EXPRESSION) ELSE (DESIGNATIONAL EXPRESSION); /QTl\tfPTTi' \ .._a........ ~ .L.u.:..o nTi'QT~l\.TArpTl\l\.T AT lJIXDDlJIQQTr\1\T \ •• _ .L.J~u~'-.X ... ,.n..J...J..\J..l'll.n...u.L:.j .J.. .J..".L:.jIJIJ.J..\J.l..'11 / " - IITYJ~'OTn1\.T" 'T'ITr\1I.T" T ~ \.LI.L:.jO~U.l.."t1""1.~~V.l.."t1""1..l.J I ..." lJ II r.1"V"-nTYr.'tSST"""T" \, ~Ar.n.~ ~v (SWITCH IDENTIFIER)$ [(ARITHMETIC EXPRESSION) $] I (LABEL IDENTIFIER); (SWITCH IDENTIFIER) :: = (*1); (LABEL IDENTIFIER) :: = (*I); IF Clauses (IF CLAUSE) :: = IF [(CONTROL HEAD )]& [ANY I ALL]& (BOOLEAN" EXPRESSION) THEN I IFSET (BOOLEAN EXPRESSION) THEN; (CONTROL HEAD) :: = FOR (SET VARIABLE LIST» SLl1 (SET NAlVIE LIST»; B.6 A ssignment Statements (ASSIGNl\1ENT STATEl\1ENT) :: = (BOOLEAN ASSIGNl\IENT STATEMENT) I (ARITHMETIC ASSIGNMENT STATEMENT) (SET ASSIGN~IENT STATEMENT); I B.6.1 Boolean Assignment Statements (BOOLEAN ASSIGNMENT STATEMENT) :: = list [(*I)~] (BOOLEAN EXPRESSION); (BOOLEAN EXPRESSION) :: = (SIMPLE BOOLEA.1~) I (IF CLAUSE) (SIMPLE BOOLEAN) ELSE (SIl\1PLE BOOLEAN"); I SINIPLE BOOLEAN) :: = (BOOLEAN FACTOR) [[OR I I.ltlP I EQV] (BOOLEAN FACTOR )]*; (BOOLEAN FACTOR) :: = (BOOLEAN SECONDARY) [AND (BOOLEAN SECONDARY)]*; (BOOLEAN SECONDARY) :: = (BOOLEAN PRIMARY) I NOT (BOOLEAN PRIMARY); (BOOLEAN PRIl\fARY) :: = TRUE I FALSE I (*1) I (RELATION) I (BOOLEAN EXPRESSION»; (RELATION) :: = (ARITHMETIC EXPRESSION) ELT (SET EXPRESSION) I (ARITHl\1ETIC EXPRESSION) (RELATIONAL OPERATOR) (ARITH.l\fETIC EXPRESSION) I (SET EXPRESSION) [= \ EQL \ ~ I NEQ] (SET EXPRESSION); (RELATIONAL OPERATOR) :: = L88 I LED I = I GED I nTR I VF]D I ~ ( I$ ) I _( I ) I ~ I EQL;
,

r ·

I

-

-.r

I

I

-- - -.....

I

-- -

--

I

- - -

~

i

,,-

,

I

B.6.2 Arithmetic Assignment Statements

(ARITHMETIC ASSIGN.l\IENT STATEMENT) :: = list [(*1)
[ $[(SUBSCRIPT LIST)$]]& ~]
(ARITHl\1ETIC EXPRESSION);
(ARITHl\1ETIC EXPRESSION) :: = (GLOBAL PRI:\1ARY) I (IF CLAUSE)
(ARITH BOOL EXPRESSION) ELSE (ARITH BOOL EXPRESSION)
(ARITH BOOL EXPRESSION);
(GLOBAL PRIMARY) :: = [FOR (SET VARIABLE LIST» SIM
(SET NAlWE LIST »]& [SUM \ PROD IGOR \ GAND I
.ilfAX \.ilfIN] (ARITHMETIC EXPRESSION)];

I

72

Spring Joint Computer Conference, 1969

(ARITH BOOL EXPRESSION) :: = (ARITH BOOL L\1PLICATION)
[EQU (ARITH BOOL Il\1PLICATION )]*;
(ARITH BOOL LVIPLICATION) :: = (ARITH BOOL FACTOR)
[[lVOR I H'EOR I WIAfP I WEQVl (ARITH BOOL FACTOR )}*;
(ARITH BOOL FACTOR) ::= (ARITH BOOL SECONDARY)
[WAND (ARITH BOOL SECONDARY)]*;
(ARITH BOOL SECONDARY) :: = (SIMPLE ARITHMETIC EXPRESSION)
[WNOT (SIMPLE ARITHMETIC EXPRESSION)]*;
(SIMPLE ARITHMETIC EXPRESSION) :: = [ + I - ]& (TERM)
[[ + I - ] (TERM)] *;
(TERM) :: = (FACTOR) [[ X I / I DIy] (FACTOR )]*j
(FACTOR) :: = (PRIMARY) [ # * (PRlMARY)]*;
(PRINIARY) :: = (*I) (1; [(SUBSCRIPT LIST) ~]]& I
({ARITHMETIC EXPRESSION»
(MODFUN)
(FUNCTION DESIGNATOR) «ARITHMETIC EXPRESSION» j
(SUBSCRIPT LIST) :: = list [(ARITHMETIC EXPRESSION) I
(SET EXPRESSION) I ()] separatur,;
(MODFUN) :: = MOD «ARITHMETIC EXPRESSION),
(ARITHMETIC EXPRESSION»;
(FUNCTION DESIGNATOR) :: = ABS \ SIGN I SQRT I TRANS I SIN I COS I

I

I

I

ARCTAN LN EXP

I

I ENTlER;

B.6.3 Set Assignment Statements

(SET ASSIGNMENT STATEMENT) :: = list [(*1) ~]
(SET EXPRESSION);
(SET EXPRESSION) :: = (SIMPLE SET) I (IF CLAUSE) (SIMPLE SET)
ELSE (SIMPLE SET);
(SIMPLE SET) :: = (SET PAIR) [(SET PAIR)}* I
REVERSE (SET PAIR);
(SET PAIR) :: = (SET UNION) [PAIR (SET UNION)]*;
(SET UNION) :: = (SET INTERSECTION) [[UNION I DELETE I SMD I
CONCAT] (SET INTERSECTION )]*;
(SET INTERSECTION) :: = (SET FACTOR) [INTERSECT (SET FACTOR )]*;
(SET FACTOR) :: = (SET OFFSET) [COMPLEMENT {SET OFFSET)]*;
(SET OFFSET) :: = (SET PRIMARY) I ({SET PRIMARY) [+ I -]
(ARITH1vlETIC EXPRESSION»);
(SET PRIMARY) :: = (SET IDENTIFIER) I «SET EXPRESSION» I
CSHIFT ({SET EXPRESSION), (ARITHMETIC EXPRESSION»
(SET DEFINITION TAIL);
(SET IDENTIFillR) :: = (*1);

APPENDIX C: A METALANGUAGE FOR SPECIFYING SYNTAX
The TRANQUIL syntax in Appendix B is specified in a form of BNF which is extended as follows: 8
1. Kleene star:
(A)* = ()

I (A) I (A)(A) I .. ,
where () represents the empty symbol
2. Brooker and Morris' question mark (here &):
(A) & = () I (A)
3, List Facilities
list (A) = (A) (A)*
list (A) separat07' (B) = (A) [ (B) (A)] *

I

TRANQUIL

73

4. Brackets
(T) :: = [(A) I (B) I (C)] (D)
is equivalent to
(T) :: = (R) (D)
(R) :: = (A) (B) (C)
5. Metacharacters:
A sharp (#) must precede each of the following characters when they belong to syntactic definitions:

I

# , [, ],

I

*, ;, (, ).

In the syntax (*1) is used to designate an identifier and (*N) is used to designate a number. Further, the special
words in the language are italicized.

SN AP - An experiment in natural
laHt;uage programmi~
by MICHAEL P. BARNETT
H. W. Wilson Company
New York, New York

and
WILLIAM M. RUHSAM
Cherry Hill. New Jersey

INTRODUCTION
Computers are being used to a rapidly increasing extent,
to manipulate and to generate materially, mechanically.
(1) Many applications simply require items of information to be selected from a file of fixed format, heavily
abbreviated records, and expanded into statements
that are self-explanatory, and used perhaps in individual communications or incorporated in computer
typeset compendia. At the other end of the spectrum
are the interrelated challenges of mechanical indexing. abstracting, and translation. The burgeoning
applications of computers to publishing, education,
library work and information services in most major
branches of science and scholarhsip are leading to a
host of text processing and generating problems that
span these limits of complexity.
Many of the programming problems of mechanical
text processing also arise in other kinds of symbol
man 1pulation, such as the compilation of computer
programs, and the simplification of mathematical
expressions. Several programming languages, such as
COMIT and SNOBOL have b,een developed over the
years for mechanical symbol manipUlation, and used
to process text. FORTRAN, supplemented by some
simple assembly language subroutines, has been applied
to non-numeric problems quite extensively. ALGOL
and COBOL also have been used this way. Several
features of PL/1 will facilitate its use in processing
text. A number of languages and processors have been
developed for special kinds of text processing problems,
such as mechanical editing.

SNAP is a procedural language for nonscientists to
use. A SNAP procedure consists of a sequence of statements that have the appearance of simple English
sentences. The primary rationale of SNAP is that
mechanical text processing requires a language that
many nonscientists will be willing to learn, and which
they will find easy to use. Since such people deal primarily with English sentences in their daily work, a programming language that is a stylized subset of English
should seem to them more "natural" than one that is
symbolic. This rationale is not negated by the fact
that nonscientists are using symbolic languages effectively. Many scientists once learned to write in assembly language, but the number of people programming scientific problems was greatly increased by
FORTRAN.
Several SNAP constructions are quite like COBOL.
SNAP is designed like BASIC, to enable a beginner
to get useful results after learning very little; and to
proceed by incremental learning efforts to deal with
problems of increasing complexity. In its primary
emphasis on string handling, however, SNAP is different; and in the details of the instruction set, and how
the basic instructions are expressed, and in the proposed
use of statements that invoke subroutines, to allow
multitudinous language extensions. SNAP has some
novel features.
A prototype processor for the basic SNAP language,
that is SNAP without the subroutine capability, was
implemented in a compatible subset of FORTRAN
IV and now runs on several models of computers.
75 ---------------------------------

76

Spring Joint Computer Conference, 1969

The language and the prototype processor are used
in a graduate course on Computing and Librarianship
at.Columbia University. An early account of the SNAP
proj ect presented the language in a tabular form.
(2) SNAP is used as a vehicle to develop basic programming concepts in·a recent college text. (3) The implementation of the prototype processor is being reported too. (4) A more advanced processor, that will
allow invoking statements and a range of definitional
capabilities, is under development.

PRINT "TESTING, TESTING". EXECUTE.
or a little more adventurously, by typing
CALL "STILL TESTING" THE MESSAGE.
PRINT THE MESSAGE. EXECUTE.
The computer can be instructed to print output that
is longer than the input, ready to be cut into two line
display labels for the Mesopotamian Merchants Mart
at the Roman Coliseum, by typing as follows:

Programming in MICROSNAP
SNAP statements deal primarily with strings and
quantities. A string can be given a name by a SNAP
statement such as
CALL "YOU CANNOT ERR OR l\fAKE A
BLOOMER \VITH THE \V ARES OF ANCIENT
SUMER" THE TAG.
This statement in a SNAP procedure makes THE
TAG connote YOU CANNOT ERR .. until another
statement that redefines THE TAG is executed. In
general, a CALL statement in SNAP (that is used to
give names, not to invoke subroutines) consists of (1)
the verb CALL, (2) an expression (for example a quotation) that specifies the string which is being given a
name, (3) the name, and (4) a period. The forms that
are allowed for the expression (2) are described in a
later section.
SNAP places almost no restrictions on the choice of
words that can be used as names. Extensive restrictions
on the choice of names would seriously restrict the ease
with which a "natural" programming language could
be learned and used) and one objective of the SNAP
syntax is to permit meta-words within names. How this
may be done is discussed later. For the moment, we
just prescribe that a name is a nonblank sequence of
letters, digits, spaces, hyphens and apostrophes. Leading and trailing spaces are ignored, so are redundant.
internal spaces (i.e., any space that follows a space).
An article (A, AN, THE) at the beginning of a name is
optional (and in fact, ignored, to good advantage-see
later).
A string can be printed by a SNAP statement that
consists of (1) the verb PRINT, (2) a quotation, or a
name that an earlier CALL statement gave to a string,
or any of the other forms of string expressions that. are
to be described in a later section and (3) a period. The
one word statement EXECUTE is used to end a procedure, and to make the processor start executing it, so
that the SNAP conventions which have been described
so far can be demonstrated by typing.

CALL "YOU CANNOT ERR OU 1-1AKE A
BLOOMEH WITH THE WARES OF ANCIENT
SUMER" THE TAG. PRINT "CHARIOTS OF

DISTINCTION". PRINT THE T}:LG. PRINT
"INLAID GAMING BOARDS FOR PORCH
AND PATIO." PRINT THE TAG. PRINT
"DRINKING MUGS FOR THE LONGEST
THIRST" PRINT THE TAG. EXECUTE.
The production of display labels that combine a
common slogan, or class identification with indivlidual
identifications is a very simple and versatile "plot
mechanism" for developing examples and exercises that
relate to the interests of students in different disciplines.
Others include
1. The production of sets of letters that consist of
different selections of form paragraphs.
2. The production of programs for several performances of the same play or opera or other
artistic work on different occasions, with perhaps
some variation of case.
a. The production of a handbill that lists the events
for an entire season in which a few different
works are repeated many times.
4. The production of messages in large letters made
of X's (GO DOG GO, keeps the burden of font
design to a minimum), panoramic vistas of
seagulls and palm trees on desert islands, processions of stylized animals, etc., printed along
the length of the output stationery.

More are given in reference 3. The diversjty of applications that can be handled with a minimal knowledge
of SNAP has just been stressed because is does seem
important to enable students of a nontechnical bent to
overcome their initial apprehension of the computer
by getting results before being overwhelmed by grammati-cal rules. Once this potential barrier is crossed,
most seem able to assimilate programming grammar
with ease. The kinds of examples cited here can, of

SNAP

course, be handled with very little grammatical knowledge in many other languages.

Some more verbs that deal with strings
Input statements: The contents of a card, (or its image
on magnetic tape, for off-line card input) is immitted
by a SNAP statement such as
that consists of (i) the verb READ, (ii) the name that
the user wishes to give to the string that is read, and
(iii) a period. The corresponding instructions that begin
with the verbs REQUEST and FETCH immit an
input record from the console on which the user signed
on (in jnstailations where SNAP is used on line), and
from all other input media respectively. In the latter
case, the device (and the block format for magnetjc
tape input) is specified by a statement that begins
with the word SELECT, and which remains in force
until another SELECT statement that pertains to
input is executed. The input commands are being
extended to interface with operating system commands,
to access files on backing storage conveniently. The
REQUEST command alerts the console worker to type
a record that is ended by pressing the line feed key;
the SNAP processor stores the string under the name
that is given in the command, and goes on to the next
statement jn sequence. There are further SNAP statements to instruct the processor to give certain characters a typographic control interpretation or to use them
literally, and to retain trailing spaces in an input record,
in processes that embed an input item of variable
length within a fixed text framework (e.g., a name in
a form letter). An input record that consists of several
items is deconcatenated by methods that are described
later. The name that the input string is given by an
input statement may have been used before, but does
not need to have been.
Output statements: These consist of a verb, slieh as
PRINT, followed by an expression that specifies the
string to be recorded. This expression is, most simply,
a quotation, or a name that was defined by an earlier
statement in the prdcedure. Other forms are described
later. The verb is PRINT, PUNCH, PERFORATE,
TYPE and WRITE for the line printer, card punch,
paper tape punch, console and all other media respectively. Instructions that begin with the word SELECT
are used to control output on other media in a way that
parallels their use for ihput. The SNAP conventions
include provisions for representing case shifts, special
characters and font changes in a more limited character

77

set; an appropriate code conversion table can be put
into the processor to record output on a device that
has an extended typographic capability. A line printer
with upper and lower case characters has been driven
this way; so has a Flexowriter; and output has been
recorded on a magnetic tape that then served as input
to the composition programs of the RCA Videocomp
electronic typesetting machine.

String synthesis and alteration statements: The CALL
statement in general has the form
CALL b a.
where b denotes a string expression (i.e., an expression
that displays or represents a string) and a denotes the
name that this string is given by the statement. CALL
statements are not recursive, that is the expression b
must not make direct or indirect use of the name a
(the APPEND statement mitigates this-see below).
The definition that a CALL statement provides moreover is dynamic, that is, if the interpretation of the
expression b changes after the CALL statement is
executed, then the interpretation of the name a automatically changes to correspond. The COpy statement,
of the form COpy b AND CALL IT a. however constructs a copy, in core, of the string that b represents,
and gives the name a to this copy. Subsequent changes
in the interpretation of b do not affect the interpretation
of a.
The APPEND statement has the form
APPEND b TO a.

It gives the name a to the result of concatenating the
string represented by b to the string known previously
as a.
The OVERWRITE statement has the forms
OVERWRITE b ON THE m-th AND (SUBSE-

-L, . . . . . . . . . . . . . .

{)TTV1\T'T"
p"RV0VnV1\T'T".\ 0ll A "R A 0'T"V"RQ {)H'
.... ,...a..,
~'-"..,L...I

.£...&. .............................. ~ ........ _

..

...L ....... 4'--'..&. ........ ..&. ............

......, .....

a.

Here m-th denotes an ordinal adjective of the kinds
such as 3-RD, and UMPTEEN-TH which are discussed
later. A single character can be overwritten by a
shorter form of the statement.
OVERWRITE b ON THE m-th CHARACTER
OFa.
The DELETE statement, which elides characters,
takes the forms

78

Spring Joint Computer Conference, 1969

DELETE THE (m-th, m-th THROUGH n-th,
m-th AND PRECEDENT, m-th AND
SUBSEQUENT CHARACTER(S) OF a.
The string name a in an APPEND, DELETE or
OVERWRITE statement must have been given to a
string by a COpy or an input statement previously
(and more recently than by any CALL instruction).
Expressions that purport to represent strings but which
are inconsistent or invalid are considered to represent
null strings.
Storage allocation: A SNAP procedure can be written
without consideration of the lengths of the strings that
are involved, subject to the total core storage capacity
of the computer. The prototype processor allows 16K
bytes in a 128 K byte RCA Spectra or IBM 360 computer, for strings and internal representations of proeedures that are co-resident.
Procedures are condensed appreciably in their internal representation (in "SNAPIC" code), so that for
many problems there is ample room for all the strings
involved, without recourse to paging tactics; and these
can be adopted, using backing storage, when need
occurs.
Strings that are defined by CALL statements are
represented internally by codes within the actual representations of the statements; but strings which are
immitted by input statements, or constructed by COPY,
APPEND) DELETE and OVERWRITE statements
are stored separately in a" string bank." When a COpy
or an input statement is executed, that assigns a string
to a particular name for the first time in the current
operation of a procedure, this string is stored sequentially in the unused portion of the string bank. When
the string that is known by a part.icu lar name is changed.,
the space that it occupies is used for the new string,
and chained to a disjoint portion of the string bank
if it is inadequate. Since sequentially stored material
can be processed more rapidly than disjoint material
in many circumstances, SNAP includes an instruction
of the form
RESERVE SPACE FOR n CHARACTERS IN a.
where n stands for a positive integer, and a for a string
name, that may have been used before, but need not
have been. This reserves a continuous portion of the
string bank, that is n characters long, for strings called
a. It does not preclude longer strings receiving this
name-they are simply chained. The statement may
be advantageous when the strings that are given the
name a vary in length during a procedure, and it is
possible to anticipate a value which this length is. un-

likely to exceed, or to impose a limit on this length.
Storage allocation thus is permitted to the user, but is
not imposed on him.
Instructions that deal with integers

A statement such as
SET I TO 7.
that consists of (1) the verb SET, (2) a mnemonic,
word or phrase that the user chooses for a particular
quantity, (3) the preposition TO, (4) an integer, and
(5) a period, has the dual effect of giving the status of
a quantity name to the word(s) or mnemonic that
appears between SET and TO; and assigning the value
of the integer (item (4)) to this name, until further
statements change it. More generally, the item (4)
may be either
(i) an integer
(ii) a quantity name that was introduced' by an
earlier SET statement,
(iii) a length expression such as THE LENGTH
OF b, where b stands for an expression that
represents a string (expressions for lengths of
lists are discussed later)
(iv) an arithmetic expression of the form
THE f OF

(v)

~

AND

~

where f denotes one of the words SUM, DIFFER~NCE, PRODUCT, QUOTIENT, REMAINDER, CEILING, GREATER, LESSER; el denotes an integer or a name that was
introduced by an earlier SET statement, and
so does ~. A name can be used. more than once
in a SET statement. An article (A, AN, THE)
is optional at the beginning of a quantity name
and it is ignored when it is included. Invalidity is infectious, that is a quantity defined in
terms of an tnvalid quantity is invalid.
a string expression that represents a string
which is a decimal integer, with perhaps re-.·
and trailing spaces.

Defining lists of strings and quantities

A list of strings can be defined by a statement such
as CALL "SUNDAY, MONDAY, TUESDAY,
WEDNESDAY, THURSDAY, FRIDAY, SATURDAY" THE DAY LIST. This permits subscripted
names, such as THE 1-ST DAY and THE 5-TH DAY
to be used for strings, in any of the ways that unsubscripted string names (e.g., THE TAG used e.arlier)

SNAP

can be used. A list element thus can be redefined individually, by CALL, COPY, APPEND, DELETE
and OVERWRITE statements. It can be recorded
by an output statement, and used in expressions that
define further strings. A quantity name that has been
defined in any of the ways that were described earlier
can be used as a symbolic ordinal, by adding -TH,
so that if N and UMPTEEN are quantity names, THE
N-TH DAY and THE UMPTEEM-TH DAY are
acceptable as subscripted string names.
In general, a CALL statement. of t.he form
CALL "Sl, S2, ...

Sk."

THE g LIST.

gives the status of a generic string name to the word
or phrase that is denoted by g, and permits expressions
of the form THE j-th g to be used as subscripted string
names where j-th denotes a numerical ordinal (e.g.,
I-ST, 2-ND, 73-RD) or a symbolic ordihal (e.g.,
N-TH.) A subscripted string name is interpreted as a
null string if the ordinal is invalid, or if its value is
inappropriate. A comma is forced in a list element by
a preceding asterisk, and individual elements are defined
to be null by adjacent delimit.ers (commas and/or
quote marks.)
A generic string name also can be introduced by
input statements of the form
(READ, REQUEST, FETCH) (A, AN, THE)
g LIST.

79

are adjacent for elements that are null. Trailing null
elements and their commas however are suppressed.
Trailing null elements also are ignored in statements
of the form
SET k TO THE LENGTH OF THE g LIST.
A further statement, however, of the form
SET k TO THE REGISTERED LENGTH
OF THE g LIST.
that includes trailing null elements in the Jist, as it
was defined most recently, will be provided for programmed storage control.
A list of numbers nl, n2, ... , nk can be defined by a
statement of the form
SET THE h LIST TO.nl, 112, ... , nk.
This allows expressions of the form THE j-th h
(where j-th denotes a numerical ordinal, or a symbolic
ordinal derived from an unsubscripted quantity name)
to be used as subscripted quantity names, in any of
the contexts allowed for unsubscripted quantity names,
except symbolic ordinals. RESERVE statements and
LENGTH expressions for lists of numbers parallel
those for list of strings.
Expressions that represent strings

This immits a record, and treats commas as separators between list elements (except when forced by a
preceding asterisk). A generic string name also can be
introduced by a stat.ement. of the form
RESERVE SPACE FOR k STRINGS IN THE
g LIST.
where k denotes a positive integer. The same name
can be given to lists of different length, on different
occasions in the execution of a procedure, and the
processor accommodates these changes automatically
by chaining. The RESERVE statement may be used
to take advantage of knowledge of a limit that is likely,
or which can be imposed.
An entire list can be recorded in the output by a
statement of the form
(PRINT, PUNCH, WRITE,
TYPE) THE g LIST.

PERFORATE,

Successive elements are separated by commas, which

A string expression, that is an expression which
displays or represents a string, may take any of the
following forms in a SNAP statement.
1. A quotation, that is bounded by quote marks.
Within a quotation, /, $, 1, >, and < signify forced line break, forced page break, case reversal, upper case and lower case respectively. An asterisk is typed before one of these characters; or a quote mark, to force its literal use within a quotation. Two asterisks are typed to represent a single literal asterisk. An = symbol together with the character that follows represents a special character. When a quotation continues from one input card (line) to the next, one space is included between the last non-blank character on the first card, and the first character on the next, except when the former character is a hyphen, in which case it is elided and the space is not included. 2. An unsubscripted string name, that was introduced by a CALL, COPY, input or RESERVE 80 Spring Joint Computer Conference, 1969 statement, at an earlier point in the procedure, both as written and as executed. :t A subscripted string name that contains (i) a numerical ordinal, or a symbolic ordinal derived from an unsubscripted quantity name that was defined previously; and (ii) a generic string name that was introduced by a CALL, input or RESERVE statement which ends with the word LIST, at an earlier point in the procedure. -t An integer that is positive, or negative, or zero. Leading zeroes, a plus sign, and spaces before and after the integer in the expression are elided. This is because the integer is first stored as a quantity, and then converted back to a Rtring representation. The statement PRINT 007, thus makes the computer print 7 in the first t.ype position. The statement PRIXT "007," however makes the computer print 007 in type positiolls 1 to 3, since 007 is stored as a string because of the encompassing quote marks. 5. An unsubscripted quantity name that was introduced by an earlier SET statement. This is interpreted, in a context that requires a string expression, as the string of characters that represents the value of the quantity, without any leading spaces, or redundant zeroes, or a sign when it is positive. n. A subscripted quantity name that contains a generic quantity name which was introduced by an earlier SET ... LIST ... or RESERVE statement. This is treated in the same way as (5). 7. An extract expression of the form THE k-th CHARACTER OF a. or label. This label may be cited m control statements of the form CREPE.AT, CONTINUE) C\VITH, FROIVl) g. where g denotes the label. The verbs REPEAT and CONTINUE are used respectively when g is earlier and later in the written procedure, for external appearances; but they are synonymous as far as the SNAP processor is concerned. The statements REPEAT FROM THE (BEGINNING, BEGI~NIXG OF THE PROCEDURE). send control back to the first statement of a procedure, '\vhich does not Ileed to be labelled. The one ,"\Tord statement TERMINATE. returns control to the operating system. Two forms of conditional statement are used: IF u v, OTHERWISE w. IF u v. The letters u, v and \" here denote the condition, the succet)s action, and the fail action respectively. The success action consists of one or more clauses, that could stand by themselves as unconditional SNAP sentences. The clauses are separated by commas, when there are several, and the word AND allowed between a comma and the first word of a clause. The success clause, when there is only one, and the last success clause, when there are several~ may be of the (REPEAT, CONTINUE) (FROM, WITH) kind described above. Alternatively, it may be THE k-th THROFGH j-th CHARACTERS OFa. where k-th stands for a numerical ordinal, or a symbolic ordinal t hat contains a previously defined unsubscripted quantity name; and j-th does too, and a denotes a string name. R. A concatenated string expression, that consists of two or more items of the kinds described above, joined by the word THEN, to connote COIl= catenation of the strings that they represent, within the Nlt-ire string that the expression represents. (' ontrol and conditional statements A SNAP statement may be preceded by a bracketed CONTIXCE WITH THE XEXT SEXTE~CE This is implied when the success action does not specify a transfer of control. The fail action may be constructed in just the same ways as the success action, except that CONTINUE AS FOLLOWS is used as the final (or only) clause to take the next sentence in sequence. It is implied when the fail action does not specify a transfer of control, and as the entire fail action in the short form IF u v. SNAP allows the following forms of condition clause at present: SNAP 1. THE I~PUT IS EXHAUSTED 2. £1 IS (GREATER THAN, GREATER THAN OR EQUAL TO, EQUAL TO, LESS THAN OR EQUAL TO, LESS THAN, UNEQUAL TO)~ 3. 4. (IS, ARE)· {THE SAME AS} S2 IS THE SAME AS THE m-th AND (PRECEDENT, SUBSEQUENT) CHARACTERS OF S2 5. THE m-th AND (PRECEDENT, SUBSEQUENT) CHARACTERS OF S1 ARE THE SAME AS S2. S1 S1 and ~ denote quantity expressions. S1 and S2 denote simple string expressions of the kinds (1) to (7) listed previously. m denotes a numerical or a symbolic ordinal that contains· a previously defined unsubscripted quantity name. PRINT THE M-TH MO~TH. 81 PRINT "1969/" . IF K IS EQUAL TO 365 TERMINATE, OTHERWISE CONTINUE AS FOLLOWS. INCREASE K BY 1. IF J IS EQUAL TO THE M-TH LIMIT INCREASE M BY 1, AND SET J TOl, OTHER WISE INCREASE J BY 1. IF N IS EQUAL TO 7 SET N TO 1, OTHERWISE INCREASE N BY 1. REPEAT FROM THE PRINT A PAGE ACTION. EXECUTE. £1 Some more examples The account of S~AP in the last few sections covers almost all the features of the basic language. Several of these may be illustrated by the production of a simple calendar of the form WEDNESDAY 1 JANUARY 1969 THURSDAY 2 JANUARY This example is quite useful as an illustration of the computers ability to print much more than the user types, by repeating items in different combination. It can be extended and modified in numerous ways, with minimal knowledge of SNAP, which is useful for teaching pruposes. Another useful example, whose logic is a trifle more elaborate, reads a classification scheme from a deck of cards, such as VERTEBRATA, (MAMMALIA, (PRIMATES, (ANTHROPOIDEA, (SIMIIDEA, CERCOPITHECIDAE, CEBIDAE, H APALIDAE), LEMUROIDEA, (LEMURIDAE, LORISIDAE, TARSIIDAE, CHYROMIDAE», CHIROPTERA, (MICROCHIROPTERA, (VESPERTILIONIDAE, RHINOLOPHIDAE, PHYLLOSTOMATIDAE), MEGACHIROPTERA, (P TEROPODIDAE», INSECTIVORA, ((ERINCEIDAE, TALPIDAE, SORICIDAE, MAC- 1969 IIDAE, DAE») DIDODONTIDAE, URANOSCOPI- A SNAP procedure to print this is as follows. CALL "JANUARY, FEBRUARY, wiARCH, APRIL, MAY, JUNE, JULY, ArGUST, SEPTEMBER, OCTOBER, NOVEMBER. DECEMBER" THE MONTH LIST. SET THE LIMIT LIST TO 31, 28, 31, 30, 30, 31, 31, 30, 31, 30, 31. CALL "SUNDAY, MONDAY, TUESDAY, WEDNESDAY, THL'"RSDAY, FRIDAY, SATGRDAY" THE DAY LIST. SET M TO 1. SET N TO 4. SET K TO 1. SET J TO 1. (PRINT A PAGE ACTION) PRINT THE N-TH DAY. PRINT" "THEN J. that is strung out to save card space, with brackets indicating subordination, and prints it in a hierarchically indented format, that is VERTEBRATA MAMMALIA PRIMATES ANTHROPOIDEA SIMIIDAE CERCOPITHECIDAE LEMUROIDEA CHIROPTERA tor the zoological scheme just cited. The procedure is 82 Spring Joint Computer Conference, 1969 ACTER OF THE BACKGROUND THEN THE CARRYOVER THEN THE I-TH THROUGH K-TH CHARACTER OF THE INPUT RECORD. TERMINATE. EXECUTE. as follows CALL" " THE BACKGROUND SET P TO 1. SET Q TO 1. CALL THE NULL STRING THE CARRYOVER. (INPUT TEST) SET J TO O. SET I TO O. SET K TO O. IF THE INPUT IS EXHAUSTED CONTINUE WITH THE LAST ITEM ACTION, OTHERWISE CONTINUE AS FOLLOWS. READ AN INPUT RECORD, (CHARACTER TEST) INCREASE J BY 1. CALL THE J-TH CHARACTER OF THE INPUT RECORD THE KEY. IF THE KEY IS "("CONTINUE WITH THE DESCENT, OTHERWISE CONTINUE AS FOLLOWS. IF THE KEY IS "," CONTINUE WITH THE OUTPUT ACTION, OTHERWISE CONTINUE AS FOLLOWS. IF THE KEY IS 'C)"~ CONTINUE WITH THE ASCENT, OTHERWISE CONTINUE AS FOLLOWS. IF THE KEY IS" " CONTINUE WITH THE LAST ITEM: ACTION~ OTHERWISE CONTINUE AS FOLLOWS. SET K TO J. CONTINUE WITH THE END CARD TEST. (DESCENT) INCREASE P BY 1. INCREASE I BY 1. SET Q TO P. CONTINUE WITH THE END CARD TEST. (OUTPUT ACTION) PRINT THE I-ST THROUGH Q-TH CHARACTERS OF THE BACKGROUND THEN THE CARRYOVER THEN THE I-TH THROUGH K-TH CHARACTERS OF THE INPUT RECORD. SET X TO J. INCREASE X BY 1. SET I TO X. SET K TO J. SET Q TO P. CALL THE NULL STRING THE CARRYOVER. CONTINUE WITH THE END CARD TEST. (ASCENT) DECREASE P BY 1. (END CARD TEST) IF J IS LESS THAN 80 REPEAT FROM THE CHARACTER TEST, OTHERWISE CONTINUE AS FOLLOvVS. . COpy THE I-TH THROUGH K-TH CHARACTER OF THE INPUT RECORD AND CALL IT THE CARRYOVER. REPEAT FROM THE INPUT TEST. (LAST ITEM ACTION) PRINT THE I-ST THROUGH Q-TH CHAR- The procedure can be shortened slightly by omitting OTHERWISE CONTINUE AS FOLLOWS from several IF statements. Hundreds of other examples of SNAP procedures are given in reference 3. The prototype SN AP processor The SNAP language was defined almost completely in late 1966. The processor was implemented in stages, in part because there seemed good :re.asons t.o demonstrate a working subset, and incremental progress, as quickly as possible, and in part because of uncertainty in the potential of the language, and in some of the details that might be needed. A processor that dealt with CALL and PRINT statements was developed first; input, COPY and unconditional transfer of control statements were added next; then arithmetic operations and conditional statements; and then the further string instructions, and the statements that deal with lists. The prototype processor is written almost entirely in FORTRAN IV. Implementation was started using a time shared PDP 6 computer. After a few months the processor was transferred to an RCA Spectra 70-45, and to the IBM 7094 at the Columbia University Computing Center, where class exercises were run for a semester using the interim version, while implementation was extended on the Spectra. Work on the prototype was ended recently. It is operating at present on several Spectra computers, and on the IBM 36075/50 system at Columbia University; and a somewhat earlier version compiled and run on a UNIVAC 1108. The prototype processor consists of (1) a small control section, (2) the translator, and (3) the interpr'eter. The translator immits a SNAP procedure, and forms a numerical repersentation (in "SNAPIC" code) in the "procedure table". The interpreter then executes the processes that the SNAPIC representation specify. The control section simply calls the translator and the interpreter, and returns control to the operating system when appropriate. The SNAPIC representation maps a vebral SNAP procedure fairly closely. Integers in different numerical ranges are used for command words, delimiters and precedence codes tor different kinds of expression, and pointers to tables that contain, or point to, objects of interest. An unsubscripted string name in the direct. SNAP object of a SNAP statement in SNAPIC is represented by a pointer to the "string directory". The corresponding entry in this directory points to a definition of the name in the procedure table, or to the origin of the string in the string bank, depending on whether a CALL or a COpy or input statement that ends with the name was executed more recently. A quantity name is represented by a pointer to the "quantity hank" in which actual numerical values are stored. A subscripted string name is represented by the ordinaj (subscript), and a pointer to the string list directory which points in turn to the entry for the first element of the list, in the subscripted string djrectory. This contains pointers that identify the actual strings which are elements of a list, in the same way that string directory elements identify the strings that are known by unsubscripted names. Pointers to successive elements of a list are stored consecutively in the subscripted string directory whenever possible; chaining is used when necessary. A numerical ordinal is represented by its numerical part, and a symbolic ordinal is represented by the negative of the appropriate pointer to the quantity bank. A subscripted quantity name is represented by the ordinal, and a pointer to the quantity list directory, which points in turn to the origin of the list in the subscripted quantity bank, that contains the actual values of the elements. The translator was written in an ad hoc fashion. The initial, and incremental capabiHties were needed, and obtained, in less time than could be spared to implement a reasonably powerful syntactic analyzer. An analyzer will be used in the translator of the advanced system that is being designed, and additional instructions will be provided to permit users to apply it to data strings at object time. The control section, translator and processor occupy 56K, 45K and 48K bytes respectively, of which the last two can be overlayed, in the link edited version that runs on the Spectra 70-45. As an indication of the length of SNAPIC representation, the two procedures in the preceding section require just under 600 and 700 bytes respectively. SNAP as a teaching vehicle Progranuning in SNAP can be taught to non-scientists by introducing the basic constructions, and showing some of their uses, in the following sequence. (1) MICROSNAP: This subset of SNAP consists of (i) PRINT and (ii) CALL statements in which strings are displayed as quotations, or referenced by unsubscripted names, and (iii) EXECUTE statements, to start execution. Some exercises for which MICROSNAP suffices were described earlier in this paper. (2) MINISNAP: This subset of SNAP consists of the elements of MICROSNAP and the word THEN. It extends the variety of display labels, form letters, programs for the performing arts and for athletic and sporting events, catalog and greeting cards, and other materials whose mechanized production can be introduced by MICROSNAP, to allow different items to be joined on a line. This has an obvious benefit, for example in the production of form letters. The addition of the word THEN, moreover, allows the introduction of several relatively general ideas. The production of most hierarchically structured materials (such as a set of catalog cards in which a journal name is repeated throughout while the details of the issue are repeated with infrequent change, and the details of the individual papers are repeated for just a few cards each; or the verbalizations of a long sequence of year numbers) can use hierarchical naring in a variety of ways, particularly when full use is made of the "implied redefinition" characteristic of the CALL statement. Constructing the shortest procedure that is possible for an application, to reduce keyboard work to a minimum, introduces the idea of optimization, in a way that the students can readily appreciate, and which has practical importance when a large volume of material is processed. The problem of deciding which pieces of the output should be given names during its synthesis, and defining these names most concisely, usiRg just CALL, THEN, quotations and other names, provides a challenge to the ingenuity of ~he student, after negligible grammatical instruction, that many non-scientists find novel and intriguing. Such examples, moreover, give the student an opportunity to develop an intellectual process, which he can then analyze, and reduce to an algoritlun , with the prospect of mechanizing this . after . learning more progranuning granunar. An Incentlve is provided to consider fonnal descriptions of the structure of strings, which are amenable to simple algebraic manipulations, of, potential relevance to the design of large files of data, and to some topics in stylistics, and to learn a little about the elementary uses of graphs. Some simple combinatorial examples, such as the production of fifteen menus for table d'hote luncheons, that combine one of four appetizers, fish, meat and dessert dishes in all possible ways, can be handled by procedures that are shorter than the output they produce, and which can be generated by procedures that are even shorter still. Such examples help make the student conscious almost from the outset of the course, that procedures can be written to generate procedures, to advantage. 84 Spring Joint Computer Conference, 1969 programming rhetoric and applications. Containing Some mechanized aspects of teaching also can be these requires a subprocedure capability, such as the broached, using NIINISNAP. Thus, given an output one considered next. device with a reasonable typographic capability, the tactics that can be used to print. personalized form letters can be applied to the production of a set of texts, Scanning and invocation that present MINISNAP (or anything e]se) to reader groups of different professional interests (e.g., middle SNAP is not the first programming language to be put XVth century armorial bearings, later XVth century into use without a subroutine capability, but with the armorial bearings, 4.2 mev nuclear physics, 4.25 mev hope that one would be added later. Plans for an nuclear physics), by substituting examples and exercises extended SNAP processor are well advanced at the time of specialized interest in a common explanatory frameof writing, that will permit subprocedures to be written work. Another educational topic that may merit exin SNAP, and invoked by statements that increase the ploration is the mechanical production of a large number "naturalness n of the language considerably. Quite of exercises (from a relatively short prescription) extensive experimentation probably is needed with a that require the use of different combinations of eleworking system, in working environments, to d~termine ~ent90ry programming constructions, or mathematical t1- - --e1-.L!v- L _~.c.L ..J L ..J £ L ..J'-Cj.' "lie r lC:LlJl t:: ut::l1eUlJS anu uazarus 01 tue uluerent paths manipulations, or equivalent operational units in other along which the syntax of invoking statements can be subjects. It is possible that some students might develop developed. The extended processor is being designed to their "intuitions" for an activity which involves selectfacilitate such experiments, by using a syntax driven ing and manipUlating words or symbols, by working translator to produce a canonical representation in large numbers of exercises that could be generated this extended SNAPIC, for the interpreter to execute. way, with a saving of human effort, and perhaps anaOne line of exploratiop-, that seems to be particularly lyzed and criticized mechanically. The problem of interesting, would co,ntinue to restrict the contexts in generating exercises for SNAP starts to approach an whi~h new names for strings, and quantities, and lists, interesting level of complexity by the time all the posare mtroduced in procedures and subprocedures. Basic sibilities of ~1INISNAP are considered. It becomes SNAP requires these to be introduced by CALL, COPY, interesting when the READ instruction is added, which input, RESERVE and SET statements at points which comes next in the progression that is being discussed. precede their earliest use, in the order in which the (3) MID/SNAP: The addition of the READ procedure is written, to define or alter other strings and statement and REPEAT FROM THE BEGINNING quantities. It is possible therefore to scan a CALL to the elements of MIKISKAP permits the separation statement from left to right alternately for (i) simple of procedures and data, and some very elementary data string expressions of the forms (1) to (7) given earlier driven procedure generating procedures. Adding extract and (ii) the word THEN, and to treat the balance of th~ expressions permits the deconcatenation of input sentence that remains when THEN is not found as the records, and the expansion of fixed field records that name that the statement confers on a string (or on 90 list omit characters (e.g., decimal points, units of measureof strings). This name is added to the name table if it ment, century digits) which are implicit in the record has been used before. The tactic can be elaborated for design, to include these in the output. It is convenient to example to allow names that are substrings of o~her introduce IF statements that compare strings and names. Examples can be constructed to confuse the statement labels next, then the COpy statement and tactic, probably no matter how much it is elaborated then arithmetic. By this stage, additiollal con;trucbut the objective of natural language programming is t~ tions, and applications are accepted as more or less deal with statements that look" natural" rather than expected matters of detail. MIDISNAP, that contains bizarre. The preposition TO can be allowed in the names the elements which have just been mentioned, is of quantities (and strings) by using similar tactics in a adequate for a considerable range of text generating right to left scan of SET statements. problems, that use fixed field files on punched cards The tactic can be extended fairly simply to procedures I\. or ·.j.h t1h e a dd"ItlOn of SELECT and FETCH Wil!l that contain invoking statements of the following kinds: magnetic media); and may well be a convenient subse~ of SNAP for an elementary course in mechanized text 1. The statement begins with a word that is neither processing and programming concepts, for implementaone of the basic verbs of SNAP nor IF; its only tion on relatively small computers. a.rguments are previously defined names, quota(4) Basic 8N AP: The further SNAP constructions tIOns and numbers; the framework in which these that deal with strings and lists open the floodgates of are embedded identifies the subprocedure; no SNAP continuous piece of this framework is used as a name in the procedure. 2. The statement begins _with a basic verb of SNAP, and contains one or more function expressions, in contexts in which the representation of a string or quantity is appropriate. Each function expression consists of an opening word or phrase that is characteristic of the function, followed by one or more arguments, of the kinds mentioned in the preceding paragraph, in alternation with further words, phrases and/or punctuation that completes the framework which identifies the function. It is convenient \to allow either an argument or part of the framework to come last, and to require a comma as the last character in the latter instance. No continuous part of the framework may be a name that is used in the procedure, or a number, and nesting is prohibited. 3. The statement consists of a clause of the form (1) above, a comma, and a further clause such as FORMI~G X, Y,/AND Z CONCURRENTLY, that in general consists of a participle ending in IKG, one or more names that need not have been used previously, separated by commas and possibly AND; and a final word (e.g., THEREBY, ACCORDINGL Y) to round off the sentence. Although these conventions are very simple, they cover quite a range of" natural" expressions. The form (1) goes beyond allowing the user a free choice of one word verbs, which often would be insufficient. A verb can be qualified immediately, or at the end of a sentence adverbially or in other ways. Examples of such invoking statements are: SE~D A ~IE~IBERSHIP CARD TO "GRENDEL .JONES" AT "THE BEACH HUT". SEN"D AN OVERDCE RE~1INDER TO "DR. FArST" AT "SA~S" SO"CCI/BRILLIG DRIYE". ANXOCXCE "THE CHASED AND THE PCHS(,ER" TO "THE TRASH CAX/75 DREARY LANE" IX S(,GGESTIVE TERMS. AKNOCNCE "THE ILLIBERAL LIBERATION" TO "THE PAPER BACK EGGHEAD/93 FARM YARD" IN INTELLECTUAL UKDERTONES. which would invoke four separate subprocedures, characterized by the frameworks left by omittIng the quotations. 85 The proposed conventions also allow free use of prepositions (except THEN, which is best left out) in the invoking framework which is a great aid to naturalness. By allowing the generic name of the elements of a list as an argument, the definition of superlative adjectives (as in THE SHORTEST ITEM) is introduced . The form (1) invoking statement suggested above can be used when a subprocedure does not create any entities for which names do not yet exist in the invoking procedure. Form (2) is useful when one new name must be introduced, and form (3) when several are needed. A simple convent jon for heading sub procedures is to begin with a statement of the form PROCEDURE TO followed by the invoking skeleton in which dummy arguments are embedded. These arguments then can be listed in a statement that begins THE ARGUMENTS ARE .. (or THE ARGUMENT IS .. ). Function subprocedures can be headed PROCEDURE FOR .. ING .. where .. ING denotes an arbitrary participle (e.g., FORMING, FI~DING) and the further dots stand for the function expression with embedded dummy arguments. Some further provisions also will be made for input output, and for user defined conditions. Introducing the indicative SNAP, as it has been described so far, consists almost entirely of imperatjve mood statements. The extended language that is now planned will also include several kinds of indicative mood statements, that will allow statements such as: (i) THE NAMES OF STRINGS INCLUDE THE S"CRNAME, THE PRENAME, AND THE ADDRESS. (ii) THE PRESIDENTIAL RECORD CONTAINS THE STJRNA~IE~ THE GIVEN NA:NIE, AND THE DATE OF BIRTH; I~ CHARACTER POSrrIO~S 3 TO 12, 13 TO 25, A~D 26 TO 33, RESPECTIVELY (iii) THE TOWN DATUM LIST CONSISTS OF THE TOWN NAME, THE INCORPORATION DATE, THE POPULATION, THE ALTITUDE, THE MAYOR, THE MAJOR INDUSTRY, THE LARGEST PARK, AND THE :YIAIN MUSEUM. (iv) THE OB.JECTS INCLUDE THE PRESIDENT, AND THE VICE-PRESIDENT. (v) THE PRESIDENT IS DESCRIBED BY THE PRESIDENTIAL RECORD. (vi) THE VICE-PRESIDENT IS DESCRIBED BY THE VICE-PRESIDENTIAL RECORD. 86 Spring Joint Computer Conference, 1969 (vii) THE PRESIDENT IS DESCRIBED BY A BIOGRAPHICAL RECORD. (viii) THE VICE-PR~SIDENT IS DESCRIBED BY A BIOGRAPHICAL RECORD. (ix) A BIOGRAPHICAL RECORD CONTAINS THE SURNAME, THE GIVEN NAME, AND THE DATE OF BIRTH; IN CHARACTER POSITIONS 3 TO 12, 13 TO 25, AND 26 TO 33, RESPECTIVELY. The sentences (i)-(iii) are, in effect, verbalized fonus of type declaration, format statement and equivalence statemen.t. Sentence (iv) is a type declaration that makes THE PRESIDENT and THE VICE-PRESIDENT the names of objects, which sentences (v) and (vi) relate (by a convention that governs the use of IS DESCRIBED BY) to two strings called THE PRESIDENTIAL RECORD and THE VICE-PRESIDENTIAL RECORD. Statements analogous to (ii) could then be used to describe the internal structure of these strings. Statements (vii) and (viii) take a slightly different tack, using a generic string name. By convention these statements would permit the expressions 'rHE BIOGRAPHICAL RECORD OF THE PRESIDENT and THE BIOGRAPHICAL RECORD OF THE VICE-PRESIDENT to be used as string names, for example in input statements; and in conjunction with sentence (ix) would propagate this association, to allow the use of expressions such as THE SURNAME OF THE PRESIDENT to be interpreted correctly. Further simple sentences, tha~ contain the verb HAS, can be used within the framework of some more simple conventions to introduce the names of obj ects that are attributes of other obj ects, and described by strings that thereby become. indirect attributes of the latter objects. Syntactic definitions are of considerable importance, and in this regard the kind of meta-syntactic language, and method of representing the result of a syntactic analysis that were developed in the author's laboratory at M.I.T.Ii.6 some years ago seem a useful basis for further work. M~ny further kinds of definitional device can be postulated that seem potent~lly useful. For example, class inclusional schemes are given an added dimension by the simple tactic which js illustrated by the following sequence of statements, that relat.e t.o a file concerning animals in a zoo. IN THIS PROCEDURE: THE KINDS OF CATEGORY INCLUDE SUBKINGDOl\fS, ORDERS, CLASSES (SINGU- LAR-CLASS), FAMILIES (SINGULAR-FAMILY), AND SPECIES (SINGULAR-SPECIES). THE KINDS OF OBJECT INCLUDE ANIMALS. THE SUB-KINGDOMS OF ANIMALS ARE VERTEBRATES, AND INVERTEBRATES. THE ORDERS OF VERTEBRATES ARE MAMMALS, BIRDS, REPTILES, AMPHIBIA (SINGULAR-AMPHIBIAN), AND FISH THE SPECIES OF APES ARE GORILLAS, CHIl\1PANZEES, AND ORANG-UTANS. AN ANIMAL IS DESCRIBED BY A RESIDENT RECORD. A RESIDENT RECORD CONTAINS THE SPECIES, THE DATE OF ACQUISITION,. .. (LOOP START) READ A RESIDENT RECORD. IF THE ANIMAL IS A VERTEBRATE PRINT THE ORDER .... The example has, amongst other things, an element of metonymy. The word SPECIES appears as a kind of category, that includes GORILLAS, CHIMPANZEES etc., and also as t.he name of a substring of a RESIDENT RECORD. These two uses will be associated: so that when necessary, the contents of the SPECIES field of a RESIDENT RECORD may be compared with the instances of SPECIES in the class inclusional statements. This will make it possible to use the latter words in the data, and to interpret st.atements such as the IF statement that ends the excerpt. ACKNOvVLEDGlViENTS The work reported in this paper was done in the Graphic Systems Applied Research Lahoratory, RCA Laboratories, Princeton, N.J., with which the authors were associated. REFERENCES 1 Annual reviews of information science John Wiley and Son 1968 2 M P BARNETT W M RUHSAM A natural language programming system for mechanical text processing IEEE Transactions on Engineering Writing and Speech Vol EW8-11 No 2 August 196845 3 M P BARNETT Computer programming in English Harcourt Brace and World New York Spring 1969 SNAP 4 W M RUHSAM M P BARNETT To be published 5 M P BARNETT R P FUTRELLE Syntactic analysis by digital computer CAe M Vol 5 1962515 6 M P BARNETT M J BAILEY The 8hadow V 8y8tem Unpublished work 87 The compiled macro assembler by WARD DOUGLAS MAURER U'YLiversity of California Berkeley, California INTRODUCTION same way. The text of a macro definition is copied into memory, after various minor transformations such as the removal of blanks. In some assemblers, the information contained in a macro may be further compressed, but in an interpreted macro assembler the compression is done in an essentially recoverable way if it is done at all. When the macro is used, this text is read from memory in what may be called an interpretive fashion-although there is no separate interpreter, the entire assembler itself serving as the macro interpreter. In a compiled macro assembler, all pseudo-operations-macros as well as others-have their corresponding subroutines of the assembler. At the start of each assembly there exists a fixed collection of such subroutines. However, when a macro is defined, a new subroutine is formed. This subroutine is compiled (hence the name, compiled macro assembler) from "source text" consisting of the original macro definition. The writing of a compiled macro assembler consists in the mechanization of the process of deducing, from the form of a given macro definition, how a use of this macro would be treated within the assembler if it were a pseudo-operation rather than a macro. As an illustration of the concept of macro compilation, an actual co~piled macro assembler was constructed by the author and his students. * This assembler is written to run on the CDC 6400. The input language is a modified form of IBM 360 assembly language; the output from the assembler is a listing of the IBM 360 code generated, and a deck of binary cards which will execute on the 360 when appropriate control carda are added. This paper describes an advance in the art of writing assemblers. It embodies an idea which has been suggested at least twice, but never actually implemented. In a compiled macro assembler, ordinary source language statements .are processed in the usual way, but macros are processed in a novel way. The advantage of the compiled macro assembler is the speed with which it processes macros. An actual compiled macro assembler has been written by the author and his students, and the speed with which it processes macros, as distinguished from ordinary statements, has been rigorously tested. The bagic concept of the compiled macro assembler We review, first of all, the operation of an ordinary assembler, which we will refer to, in what follows, as an interpreted macro assembler. (The words "compiled" and "interpreted" are presumed to modify the noun "macro," not the noun "assembler.") Each pseudooperation code in the assembly language recognized by a given assembler corresponds to a subroutine of that assembler. This subroutine is called whenever the given pseudo-operation is encountered within the source text. The collection of all of these subroutines, for a given assembler, is a fixed collection, and on a large computer this collection of subroutines is normally contained in core at all times. On a small computer, the subroutine which corresponds to a given pseudooperation may have to be brought in from disk when the pseudo-operation is encountered; however, the total collection of subroutines corresponding to pseudooperations remains fixed. A macro is, in one sense, very much like a pseudooperation. However, in an interpreted macro assembler, the occurrence of a macro does not set aside a special subroutine of the assembler for the use of that macro alone. Instead, all macro definitions are treated in the ------------------------------------------------~----------------- * The students included Donald Alpert, Steven Anderson, 1 Robert Ankerlin, Thomas Baumbach, David Brown, Dennis Griswold,2 Bing Joe, Richard Kayfes,a David Ladd, Kenneth Lew,4 William Nielsen,' Ralph Olstad, Paul Samson, and'Edmond Van Doren.' 89 90 Spring Joint Computer Conference, 1969 Feasibility of macro compilation The following paragraphs are devoted to certain feasibility considerations which the author and his students discovered in the course of writing this assembler. These points should be thoroughly understood by anyone intending to write such an assembler in the future. Substitution of parameters There are two common methods of handling macro parameters in an assembler. These are known as string stwstitution and value Sltbstitution. Either may be used in a compiled macro assembler. In addition, if value substitution is used, compilation may be carried out completely; whereas if string substitution is used, it is necessarv to include both compiled and interpreted macro facilities, and it may be necessary for a compiled subroutine to call the interpretive facility. For the sake of completeness, we now describe these two methods in general terms. In value substitution, each actual parameter in a macro usage is evaluated. This value is substituted within the macro text whenever the corresponding formal parameter is encountered. In string substitution, the character string which comprises a given actual parameter in a macro usage is copied into memory when the macro usage is encountered. If the assembler is an interpreted macro assembler, the source of input characters to it is now diverted to the location of the macro text in memory. When a parameter is encountered, the source of input characters is re-diverted to the location of the character string giving the corresponding actual parameter. String substitution is more general than value substitution because the sequence of input characters passes freely between the characters of the macro and the characters of actual parameters. Thus syntactic units may exist partially within the macro text and partially within the parameter. One important use of this facility is the appending of prefixes or suffixes to an actual parameter to form symbols. If a macro is called with actual parameter DM, for example, the macro may then create symbols DMA, DMB, DMl, TEMPDM, and the like, and use them in an arbitrary fashion. Such symbols, of course, become global, and may be referenced throughout the text. In a value substitution assembler, this facility is not possible; but in many value substitution assemblers a symbol defined in a macro cannot be used outside the macro unless it is specially declared to be global. Thus the. same symbol may be used over and over again, so long as it is always used inside a macro and only once inside each distinct usage of that macro. String substitution has been used in most assemblers which have appeared in published work, such as Halpern's XPOP,7 Strachey's general purpose macro gen ~rator,8 and Mooers' TRAC.9,lo Value SUbstitution, however, because it is simpler, has been used in many actual, working assemblers. Among these are the F AP assembler for the IBM 7094, the SLEUTH II assembler for the UNIVAC 1107, and an assembler for the UNIVAC III, all of which were written by Ferguson, who, so far as we know, hlS published only one account of his work.ll Let us now consider the substitution of parameters in a compiled macro assembler. If value substitution is used, there is no problem. Suppose that a parameter usage is found within a macro definition. Corresponding to this usage in the compiled subroutine, there is a call to a subroutine which retrieves the value of the corresponding actual parameter. (That is, the compiled subroutine, which is produced by the macro compilation process, calls a fixed, special assembler subroutine, whose function it is to retrieve parameter values.) If string substitution is used, we make a distinction between a parameter which occurs in an expression in the variable field, and one which occurs by itself in the variable field. (Most actual parameters are of the latter kind, because most people write relatively simple macros.) If a parameter occurs by itself, th~re is no difference, for this parameter, between stnng and value substitution, and it may be handled as described above. If a parameter occurs in an expression, however, it is generally impossible to han~le it in a compiled manner. The text of the expressIOn must be included with the compiled subroutine, and, at the appropriate point, this subroutine ~alls ~ ~ed, s~ecial asgornhlol" I;,mhw\11t.1TlO whose functlon It IS to Interpreti;;i;& e;~l~~tev·;~ch strings. As in the case of an interpreted macro assembler, this "subroutine" consists, from the logical point of view, of the entire assembler itself. First and second pass compilation The compilation process, as applied to a macro, must take place twice-once in the first pass and once in the second pass. There are many reasons for this; the following is perhaps the simplest. Suppose that the definition of a macro involves a symbol which is not defined until after the macro is defined. Then, when the macro is first encountered, complete compilation cannot take place, since the value of the sym hoI is not kn~wn at that time. Therefore the macro must be compIled in the second pass. But it must also be compiled in The Compiled Macro Assembler the first pass, since the length of the generated code is not known, and different uses of the same macro may result in different lengths of generated code. * The main function of the subroutine which is compiled in the first pass, in fact, is to determine this length; at the same time, any global symbols defined within the macro are placed in the symbol table along with their addresses. It might appear at first sight that this problem could be avoided by defining all sylllbois used in a macro before the macro is defined. However, this is not feasible in general. A macro may contain a call to an error routine which is at the end of the program, or, in general, which follows another usage of the macro. It is, in 'general, true that all symbols occurring within a macro definition which affect the length of the generated code must be defined before the macro is defined. By somewhat devious methods this may be improved slightly to read "before the macro is first used." Saving a compiled subroutine One of the theoretical advantages in compiling macros is that the resulting compiled code can, in theory, be output to cards, in the same way that output from a FORTRAN compiler can be output to cards. These binary cards may then take the place of the original macro definition. We have found that compiled subroutines can, in fact, be saved in most cases. There is one case, however, that creates several difficulties. Suppose that a macro definition contains a symbol which is used but not defined. Presumably such a symbol would be defined in the body of the assembly language text. (In our experience, most macros do not have this characteristic; but some do, and in any event it would be unwise to exclude it.) The definition of the given symbol in the program in which it is defined is not, however, necessarily the same as its definition in the program in which the binary cards are used. It is this latter definition, in fact, which should apply. Therefore, a distinction must be made when, compiling a macro between symbols defined in the macro and symbols defined outside it. There are further difficulties concerned with optimization of the compiled code. If the value of a symbol is known at compilation time, it may be combined with others in an expression, * The SLEUTH II assembler embodies an interesting exception to this. If a given macro always generates the same amount of code, this amount may be specified when the macro is defined. Presumably this feature could be implemented in a compiled ~cro assembler, removing the necessity for compiling such macros on the first pass. However, as we shall see later. such a macro probably should not be compiled anyway. 91 and the value of the result used within the compiled code. If code is being compiled for later use, however, such combination cannot be made. This means that either the resulting compiled code must calculate values of expressions which would not be necessary , if the macro were being compiled in that assembly, or the process of loading the binary cards must effectively incorporate some of the compilation process. Only the second pass compilation need be saved on cards. '\X/hen this is loaded during the first pass of another assembly, it is loaded in a special way which causes it to act like a first pass compilation. Compiled macros and conditional and iterative assembly Conditional statements in assembly language may be compiled; so may iteration statements. In fact, compilation of these statements is the primary justification for compiled macro assembly. A conditional statement in the definition of a macro may be replaced by a conditional transfer in the compiled subroutine; it is no longer necessary to read a number of characters without processing them if the condition is not fulfilled. An iterative (duplication) statement may be replaced by a loop in the compiled code; it is no longer necessary to interpret the iterated statements repeatedly. A macro which is to be used only once, and which contains no conditional or iterative statements, should not, in fact, be compiled. This is a special case of a general statement which may be made about interpretation/compilation situations: compilation is faster than interpretation only if no recycling takes place. If every statement in a program is to be executed at most once, it is cheaper to interpret each statement once than to compile it (which itself involves interpreting each statement once) and then to execute it. The time saving that results from compiling is due to the fact that if a statement is to be execut~d several times, it will be interpreted several times if the program containing it is interpreted, but only once if that program is com piled. A macro without conditional or iterative statements may be speeded up on compilation if it is to be used several times, but an intelligent judgment should be made in each such case. Timing tests of the compiled macro assembler In order to verify the premise that compiling macros improves the efficiency of macro usage processing, a controlled experiment was performed on the compiled macro assembler written by the author and his students, with the standard IBM 360 F level assembler serving as the control. 92 Spring Joint Computer Conference, 1969 Timing comparisons of systems designed in different ways to do the same job has proved to be one of the most frustrating tasks in the computing world today. For ahnost every comparison which has been performed, a perfectly valid argument may be advanced which nullifies its conclusion. Usually this argument takes the form that the observed differences in timing were caused by something other than the differences in the initial conditions. The use of a controlled experiment, a technique borrowed from classical scientific method, is precisely the way in which the effects of such irrelevant factors may be eliminated. In the present situation, the following were the factors which introduced differences in timing comparable to, and sometimes exceeding, the claimed improvements in efficiency: 1. Th.e time taken to process a macro was smaller than the time taken to read a carde 2. The time taken to process a macro was smaller than the time taken to print a line. 3. The total time taken to process a job differed depending on when the job was submitted; in fact, it sometimes happened that when the computer was asked to perform the same job twice in a row (by submitting an input deck consisting of two identical copies of a job deck) the job times differed by a factor exceeding 1.5. 4. The IBM 360 F level assembler as used at the computer center at which the test was made is slower than the Compiled Macro Assembler, by a factor which may exceed 10. 5. The IBM 360 F level assembler is not used at its own greatest efficiency by the computer center at which the test was made. The controlled experiment was set up in the following way....A... macro, RPD3, which generates code to calculate the value of a real polynomial of degree less than or equal to 3, was written for both the Compiled Macro Assembler and the IBM 360 F level assembler. The macro was called, in either assembler, by the line RPD3 X,A,B,C,D where X, A, B, C, and D represent addresses in memory and A + BX + CX2 + DX 3 is the polynomial to be evaluated. The algorithm always uses the fastest computational method; if all of the coefficients are nonzero, then A + X*(B + X*(C + X*D)) is calculated, but if any of the coefficients are zero, a smaller amount of calculation is performed. If all the coefficients are zero, the result register is loaded with zero. Otherwise, the total number of instructions generated is equal to the total number of non-zero coefficients plus the degree of the largest such coefficient. A deck was now made up, containing 200 calls to this macro with various parameters. This deck was assembled to obtain a printout of the code it generated. A second deck was now made up which consisted precisely of this generated code. Assembly of these two decks, then, should produce identical results· in different ways-with and without macro usage processing. To counteract the effect of factor (1) above, a second macro, called NIL, was written, which does nothing. The text of NIL was added to the first deck, and exactly enough usages of NIL were added to the first deck to equalize the number of cards in the two decks. To be absolutely precise, there. were now four decks, because all of the above was done twice, once for each assembler. To counteract the effect of factor (2) above, all assemblies, on both assemblers, were run with a "no list" option during the timing test, after it had been ascertained that they generated correct code. The use of this option insures that no printing will occur during the second pass of assembly. To counteract the effect of factor (3) above, each of these four decks was reproduced several times, and the resulting copies of each deck were run as a connected series of jobs. The results of the timing test were as follows. For the IBM 360 assembler, the runs without macro calling took 3 min. 21.94 sec" 3 min. 39.92 sec., 4 min. 25.87 sec., and 3 min. 29.00 sec. The runs with macro calling took 9 min. 33.90 sec., 7 min. 52.06 sec., and 7 min. 56.28 sec. Even with the large experimental error, it is clear that this assembler is taking over twice as long to process an assembly with macros as without macros. For the Compiled Macro Assembler, the runs without macro calling took 16.433 seconds and 16.428 seconds; the runs with macro calling took 16.458 seconds, and 16.538 seconds. Thus there is no appreciable difference, in the compiled macro assembler, between assembly of macros and assembly of the identical code without macros. The presentation of the results in this form counter~ acts factors (4) and (5) above. In particular, anyavoidable inefficiencies which affected the timing of one of the IBM 360 runs would also have affected the timing of the other. We also note that factors (1) and (2) do not, as has been claimed, remove entirely the timing advantage of compijing macros, since on a time-shared computer the time taken to process a macro will usually not be smaller than the time taken to read a card image from a file. It is also true that time-sharing systems increase the viability of assembly language coding as opposed to coding in a higher-level language, since debugging languages (such as DDT and FAPDBG) are much more amenable to machine language than they are to higher level language coding. The Compiled :Macro Assembler ACKNOWLEDGMENTS The author is grateful for the progrrunming help of the students mentioned in the first footnote to this paper. This research was parti311y supported by National Science FOlUldatjQn Grant G-J43 and Joint Services Electro~cs Program Grant AFOSR-68-1488. REFERENCES l ~ AND.~J:>"S9N Master's report University of Ca1ifornil\ Berkeley J3D.uary 1968 2 D GRISWOLD Object deck output from a compiled macro assembler Master's report Univ of Californ.i8 Berkeley September 1967 3 R KAYFES Decimal arithmetic in a compiled macro assembler Master's report Univof California. Berkeley June 1967 4KMLEW N on-decimal arithmetic in a compiled macro assembler Master's report University of Califoria Berkeley June 1967 5 W C NIELSEN 93 Subsystem implementation of a compiled macro assembler Master's report University of California Berkeley June 1967 6 E D VAN DOREN The literal facility and end card implementation of a compiled macro assembler Master's report Univ of California Berkeley September 1967 7 M HALPERN XPOP: a meta-Janguage without meta-physics Proc F J C C 1964 8 C STRACHEY .4 general purpose macro generator Computer Journal October 1965 9 C MOOERS TRAC, a procedure-descrWing language for the reactive typewriter Communications of the Assoc for Computing Machinery March 1966 10 C MOOERS T RA C, a text-handling language Proc 20th ~ational ACM Conference 1965 11 D FERGUSO~ Evolution of the meta-assembly program Communications of the Assoc for Computing Machinery March 1966 Some logical and numerical aspects of pattern recognition and artificial intelligence by W. CLARK NAYLOR IBM Corporation Rochester, Minnesota INTRODUCTION Artificial Intelligence has received the attentions and contributions of workers in many varied disciplines .. and of many varied interests. As a result there has arisen a large and diverse body of research literature in the field. The task of sorting out and comparing some threads of continuity through this rich and variegated tapestry presents a. tempting prospect. In this article we define and compare two contrasting pattern recognition approaches. We trace their divergent paths of development from their common origin and em.phasize their complementary nature. Finally, we propose their eventual reconciliation and suggest some potentially fruitful lines of development. Threads oj continuity In 1961 Hawkinsl examined the state-of-the-art of self-organizing machines and traced some historical developments from early brain models to later computer implementations. This report builds on Hawkins' historical review, emphasizing two separate lines of development and extending them into more recent pattern recognition efforts. Figure 1 displays two lines of relevant publications by author. At the origin of the lines we indicate the neuron. Section A (below) discusses some of what is known and postulated about the behavior of natural neurons. Section B follows the line of development indicated along the horizontal axis of Figure 1, and emphasizes the logical aspects of pattern recognition. In Section C we follow a line of development displayed along the vertical axis and emphasize the numerical aspects of pattern recognition. In Section D we discuss some of the problems of dealing with both aspects of the pattern classification problem at once. 1 I I :I I ;I •e it z LOIiCII Aspects ., Figure I-Diverging complementary lines of pattern recognition development A. Natural neurons In nature, an organism interacts with its environment to enhance its chances for survival and propagation. The more an organism. is capable of rapid, complex, adaptive behavior, the more effective its interaction can be. In the animal world special sensors, effectors, and associated nervous systems have developed to achieve this rapid, complex behavior. And although the complexity of the nervous systems varies greatly from the lowest to the highest animals, the properties and behavior of the basic nerve cell, the neuron, remain amazingly constant. -------------------------------------- 95----------------------------------------- 96 Spring Joint Computer Conference, 1969 The neuron is a cell specialized for conducting electrical signals. It is the cell of which ail nervous systems are constructed. In vertebrates, bushy dendrites extend from the cell body to receive afferent excitation and conduct it to the axon. The axoIi, on receiving sufficient excitation) "fire's" and conducts a spike pulse along its length to the axonal branches. There the excitation is communicated across various synaptic junctions to succeeding dendrItes, and so on. After firing, the cell enters a refractory state during which it rests and recharges its membranes in preparation for the next firing. Some neurons can repeat this cycle hundreds of times a second, Many neuron configurations exist. Neurons may have long axons, very short axons, several axons, or no apparent 3.Xons at all. They may have many dendrites or no descernible dendrites. Dendrites and axons may be virtually indistinguishable. Likewise, many varieties of synapses exist. Some transmit electrically, some transmit chemically. Some transmit axon-toaxon and Some transmit dendrite-to-dendrite. Probably the most interesting are the synapses between axonal branches and soma or dendrites, typical in vertebrate brain cells. B. Logical development A network ofaxons, each capable of a binary all-ornone response, is strongly suggestive of switching theory and logic, and much of the work in pattern recognition and artificial intelligence is based on this observation. Rashevsky3 in 1938 was perhaps the first to postulate that nets of such binary axons could perform certain decision and memory functions. lVIcCulloch and Pitts4 in 1943 formalized these concepts and showed that the behavior of such nets could be described in terms of Boolean algebra. Later, Lettvin, Maturana, McCulloch, and Pitts5 in 1959, and Verzeano and Negishi6 in 1960, were able to experimentally substantiate some of these ideas. In 1959, Unger7 described a pattern recognition program in which he used the logical structure of a binary tree to separate an alphabet of 36 alphanumeric characters. In 1961, Kochen8 described a concept formation program which could adaptively derive its own Boolean sum of products from its experience with the data. And, in 1967, l\1insky9 considered general machines composed of McCulloch-Pitts neurons. He established several universal bases for building finite automata, and showed that a very simple "refractory cell" formed such a base. c. Numerical development While the logical development exploits the logical ability of the axon behavior, it greatly oversimplifies or largely ignores the role of the synapse. In 1949, Hebb lO suggested that perhaps the synapse provided the site for permanent memory. He postulated that the ability of the axonal branches and the dendrites to form graded potentials, and the ability of the synapse to differentially attenuate and integrate the influence of many impinging signals, might somehow -change as a function of learning. In 1958, Rosenblatt ll incorporated these and other ideas into a model he called the Perceptron. At about the same time, Widrow12 began experiments with similar analog models he called Adalines. Many workers 13- 21 showed the ability of these models to implem~nt linear decision surfaces, and the ability of certain training procedures to converge to feasible surfaces. In 1963, Rosen22 employed quadratic programming to obtain optimal decision surfaces for both linear and quadratic models. In 1964, Mangasarian23 obtained optimal decision surfaces using linear programming. Based on a Bayesian statistical approach, Specht,24 in 1967, derived optimal decision surfaces for general nth order polynomials. D. Combined logical and numerical aspects In his critical review of Artificial Intelligence work, Dreyfus29 addressed himself primarily to workers specializing in logical methods. In criticizing the assumptions of Newell, Shaw, and Simons30 he said "they do not even consider the possibility that the brain might process information in an entirely different way than a computer-that information might, for example, be processed globally the way a resistor analogue solves the problem of the minimal path through a network." In the present context, this and other similar comments in his paper seem to be suggestions for more careful consideration of numerical, as well as logical, methods. While it appears that some workers have been applying logical tools to geometrical tasks, it also appears that other workers have been applying geometrical tools to logical tasks. For example, in the layered machines mentioned in Nilsson,25 it is necessary for the first layer of linear decision surfaces to completely partition the input space. Succeeding layers of linear decision surfaceR then operate on the output of previous layers and so on. However, when the input space has been completely partitioned, it has been mapped without confliet onto the vertices of a hypercube. When this haR been accomplished, only a problem in Boolean logic remains, and it seems a little wasteful L.ogical and Numerical Aspects of Pattern Recognition and Artificial Intelligence to use additional layers of linear decision surfaces for this task. Moreover, no general training procedures for such machines have yet been found. While those workers mentioned in Section B have had success in dealing with the logical aspects of the pattern recognition problem, and- those workers in Section C have had success in dealing with the numerical aspects, few workers have been successful in dealing with both aspects at once. However, some recent approaches appear very promising in this direction. In 1965, C asey26 described a program for reducing the dimensionality of sets of patterns. This would appear to be a good first step toward discovering the structure of a problem. Ball and Hall's program27 to automatically cluster sets of patterns can be viewed as a process for finding logical structures of imbedded numerical decision surfa-ces. The most clear-cut example in this direction is the 1968 program of Mangasarian. 28 This program iteratively builds a ternary tree of linear decision surfaces. Each surface is designed to be the optimum for its level on the tree, and the tree is indefinitely expandable. The complementary nature of logic and geometry in pattern recognition We would like to argue in the following sections that the two divergent lines of development pursued in the previous sections are not alternate approaches to the same problem but rather complementary approaches to that problem. That is, that a general approach must involve both aspects and that an approach emphasizing only one aspect must be somehow incomplete. This argument must be based on efficiency rather than ultimate effectiveness since either approach may be employed to eventually obtain a very good approximation to the desired result. A. Set theory and pattern recognition If we view pattern recognition in a set theoretic framework, the roles played by the two ordering relations, set membership, E, and set inclusion, ( , are very significant. If we are dealing with sets (or .patterns) of real vectors, we see that we have two distinct algebras involved. Among the sets themselves, we have the algebra of set combination or logic. Among the members of the sets, we have the algebra of real numbers, arithmetic or geometry. * The difference in emphasis evident in * In some examples of pattern recognition we may have other relations holding among set members (for example, grammatical relations in language translation). If the algebra among set members happens to be Boolean logic, then this whole distinction may disappear.· 97 the logical and numerical developments amounts to a difference in emphasis on the roles of the two algebras involved. Thus, in the logical development, the ultimate classes are composed of complex combinations of sets with very simple membership criteria. The algebra of set combination (viz logic) is strongly emphasized, while that holding among set members (viz geometry or arithmetic) is largely ignored. On the other hand, in the numerical development the ultimate classes have no apparent constituent sets and the criteria of set membership must bear the whole burden of the classification task. Thus the algebra holding among the set members (viz arithmetic or geometry) is strongly emphasized while the algebra among the sets is largely ignored. B. Example The complementary nature of the logical and numerical approaches may be likened to the complementary nature of Fourier and polynomial series. The Fourier series may be used to approximate a straight line, and the polynomial may be used to approximate a sine curve, but it is an unnatural and wasteful way to use the series. Similarly, logic may do the job of geometry or geometry may do the job of logic, but it is wasteful not to put each technique to its natural uSe. A ~imple example will illustrate that sets which are sllnpiy, and naturally described in terms of logical combiiiliiibhs of numerically defined constituent sets ~y 00 very difficult to describe by logic or geometry alone. Con':' sider the sets of rectangles defined as follows: Circumference less than 20 units Area less than 9 units Area more than 4 units Vertical side no shorter than 1/2 the horizontal side E: Horizontal side no shorter than 1/2 the vertical side F: «B"C)v(IY'E»)vA A: B: C: D: The set F mErimple enough. Try to describe it by geometry or logic alone! Figure 2 is a sketch of set F. c. A proposed response surface The idea of the complementary nature of logic and and geometry is simple enough. Is it possible to quantify it and illustrate it graphically? Consider the following proposed axes: X. Average number of members per component set 98 Spring Joint Computer Conference, 1969 t I \ \ I i .a .. it a. j E E 't; .iE ..... i .! .. z· • 10 Length of horizontal side AVll'lge !IIm"r of .. t.ts per class Figure 3-8uggestive sketch of proposed response surface Figure 2-The set F Y. Average number of component tern class Z. sets per pat- Percentage of correct recognitions achieved If we classify various pattern recognition programs as (X, Y) points and plot Z(X, Y) for each program, what sort of graph would result? Obviously one contour must be Z(O, Y) = Z(X, 0) = O. If we further assume Z to be continuous and monotonic then contours such as those of Figure 3 will result. Figure 4, showing the relative paths of logical and numerical developments on such a surface; illustrates graphically the relative performances of logical and numerical methods. j i i j i D Some optimality criteria Having divided the pattern recognition methods into logical and numerical classes, we will find it useful and interesting to fw"iher subdivide the numerical class according to the optimality criteria used. In numerical analysis, if we are trying to obtain the best fit of a line to a set of points, we generate an error vector and attempt to minimize some norm of the vector. The P=norm of a vector y = (Yl, Y2 ... ,Yn) given by: is the norm most commonly used for this purpose. Av..... !limber of .. bIets ..... ella • Figure 4-8uggestive sketch of various development paths The values of P commonly used are P = 1, P = 2 and P = 00. For P = 1, we minimize the average error. For P = 2, we minimize the SlIm. of squares error. For P = 00- we minimize the maximum error (Chebyschev criterion). In pattern recognition we have a very similar situation. For any separating surface we generate a vector of separation distances and attempt to maximize the overall separation. In analogy with the one norm, we may attempt to maximize the average separation; in Logical and Numerical Aspects of Pattern Recognition and Artificial Intelligence analogy with the Chebyschev 00 norm, we may attempt to maximize the minimum separation; or in analogy with intermediate norms we may similarly choose a whole spectrum of optimality criteria. It is instructive to consider the sensitivity and stability of methods employing the two criteria on the extremes of this spectrum. On the one hand, a method to maximize the minmum separation will seek out the few "worst-case" points and work on them first. Such a worst-case method will be a local, differentiative method; it will be very sensitive to local details, but very prone to over-react to noise. On the other hand, an average-case method will be a global, integrative method. It will tend to be relatively insensitive to noise, but also insensitive to local detail. An example will illustrate this noise and detail sensitivity. Consider the sets and separating plane of Figure Separating Plane 99 5. The plane satisfies worst-case, average-case and intuitive criteria for a good separating plane. Consider the sets and planes of Figure 6. Here set A has been augmented by A2. As long as the minimum difference between points in Band A2 is larger than the minimum difference betweenB and AI, A2 will have no effect on the placement of plane 1, the worst-case plane. The A2 information is essentially redundant. However, plane 2, the average-case plane, will move around and and react to set A2 as set A2 moves. It may even violate one of the sets. Intuitively we would probably choose plane 1. Consider the sets of planes of Figure 7. Here Sets A and B have been augmented by noise patterns. Since these noise patterns affect the minimum distance between the sets, the worst-case plane, plane 1, will react, while the average-case plane, plane· 2, does not. Here we would probably intuitively choose plane 2. Again we can tie these items to physiological considerations. Several averaging and differentiating neuronnets have been observed in nature6 •7-particularly in optic nerves. Apparently their actions are carefully balanced to insure sharp resolution together with noise Figure 5-Sets and separating plane Plane 1 - Worst Case ~~ o Plane 1 - Worst Case Figure 6-Multimodal sets and separating planes Ji'igure 7-8ets and separating planes with noise 100 Spring Joint Computer Conference, 1969 worst-case geometrical methods. Finally, for future development, we have suggested a pattern recognition model encompassing the capabilities of all these methods. ACKNOWLEDGMENTS Figure 8-Proposed pattern recognition structure (shown for binary tree as an example) insensitivity. In pattern recognition we will similarly be forced to achieve a balance in the use of average and worst-case methods. Proposed model for future development From the considerations of this report, it seems clear that a general pattern recognition device will have to perform numeric calculations carefully balanced between global integrative techniques and local differencing techniques. The results of these calculations will then be combined logically to determine the result of the entire device. It also seems clear that natural nervous systems will provide an existence proof and guide in the construction of feasible pattern recognition models. Figure 8 represents a possible logical-nu..rnerical net. At each node a numeric calculation is performed and an exiting branch is chosen. The overall branching network of nodes provides the logical structure (although a logical tree is shown for simplicity, any complex logical structure is intended). SUMMARY Pascal once said that there are two kinds of mathematical minds-logicians and mathematicians. We have indicated that there are two kinds of pattern recognition programs, logical ones and geometrical ones. In this report we have traced the historical development of these two distinct approaches. We have related them to two functIOns of natural nerve nets and to the two algebras of set theory. By these associations we have argued for the complementary nature of the roles played by these two aspects. In addition we have dis.. tinguished and compared the roles of average-case and Work leading to this report was carried out in the Computer Science Department of the University of Wisconsin and the Recognition Systems Development Department of IBM Rochester, Minnesota. The author is indebted to many people for their help and encouragement during this work: Drs. L. Uhr, J. B. Rosen, and O. L. Mangasarian at the University of Wisconsin for many stimulating and enlightening discussionS; A. Hamburgen, D. R. Andrews, P. H. Howard, and M. J. Kimmel of the Recognition Systems Development Department at IBM for their continued encouragement and support; and C. D. Cullum of IBM Yorktown for his helpful ideas. REFERENCES 1 J K HAWKINS Self-organizing systems-A review and commentary Proc of Institute of Radio Engineers January 1961 2 T H BULLOCK A G HORRIDGE Structure and function in the nervous systems of invertebrates W H Freeman and Company N ew York N Y 1965 3 N RASHEVSKY M athernatical biophysics University of Chicago Press Chicago III 1938 4 W S McCULLOCH W H PITTS A logical calculus of the ideas immanent in nervous activity Bulletin of Mathematics Biophysics Vol 115 1953 5 J Y LETTVIN H R MATURANA W S McCULLOCH W H PITI'S What the frog's eye tells the frog's brain rroc of Institute of Radio Engineers Vol 47 November 1959 1940-1951 6 M VERZEANO K NEGISHI Neuronal activity in cortical and thalamic networks J Gen Physiol Vol 43 supply July 1960 177-195 7 S HUNGER Pattern detection and recogll.ition Proc of Instittite of Radio Engineers October 1959 8 M KOCHEN An experimental program for the selection of disjunctive hypothesis Proc Western J C C Vol 19 571-578 May 1961 9 M MINSKY Computation: Finite and infinite machines Prentice Hall Englewood Cliffs New Jersey 1967 10 D 0 HEBB Organization of behavior John Wiley and Sons Inc New York N Y 1949 11 F ROSENBLATT The perceptron-A theory of statistical separability in cognitive systems Cornell Aeronatuical Lab Buffalo New York Report ~o VG-1l96-Gl January 1958 Logical and Numerical Aspects of Pattern Recognition and Artificial Intelligence I ~ B WIDRO"" M E HOFF A.daptive switching circui's Stanford Electronics Lab Stanford California Technical Report No 1553-1 June 1960 13 F ROSENBLATT On the convergence of reinforcenwnt procedures in simple perceptrons Cornell Aeronautical Lab Report No VG-1196-G4 February 1960 14 R D JOSEPH Contributions to perceptrnn theory Cornell Aeronautical Lab Report No VG-1l96-G7 Buffalo NY June 1960 15 H D BLOCK The perceptron: A model for brain functioning-I Reviews of Modern Physics Vol 34 123-135 January 1962 16 A CHARNES On some fundamental theorems of perceptron theory and their geometry Computer and Information Sciences Spartan Books Washington D C 1964 17 A B J NOVIKOFF On convergence proofs for perceptrons Stanford Research Institute Report Nom 3438(00) January 1963 18 R C SINGLETON A test for linear separability as applied to self-organizing systems-1962 Spartan Books 503-524 Washington D C 1962 19 W C RIDGEWAY A n adaptive logic system with generalizing properties Stanford Electronics Lab Technical Report No 1556-1 Stanford University Stanford California April 1962 20 T S MOTZKIN I J SCHOENBERG The relaxation method for linear inequalities Canadian Journal of Mathematics Vol 6 No 3 393-404 1954 21 S AGMON The relaxation. method for linear inequalities Canadian Journal of Mathematics Vol 6 No 3 383-3921954 22 J B ROSEN Pattern separation by convex programming Journal of Mathematical Analysis and Applications Vol 10 No 1 February 1965 23 0 L MANGASARIAN Linear and nonlinear separation of patterns by linear programming Operations Research Vol 13 Xo 3 May 1965 24 D F SPECHT Generation of polynomial di.'~cri'l1dno.nt fu.'f!~hons for pattern recognition Stanford Electronics Lab Technical Report No 6764-5 Stanford University Stanford California May 1966 101 25 N NILSSON Learning machines McGraw-Hill Inc Ne:w York X Y 1965 26 R G CASEY Linear reduction of di1Jwnsionality in pattern recognition IBM Research Report R C-1431 Yorktown Heights N Y March 19 1965 27 G H BALL D J HALL ISODATA, an iterative method of multivariate analysis and pattern classification Proc of International Communications Conference Philadelphia June 1966 28 0 L MANGASARIAN M uUi-surface method of pattern separation (to be published) 29 H L DREYFUS Alchemy and artificial intelligence The RAND Corporation Santa Monica California December 1965 30 A NEWELL H H SIMON Computer simulation oj human thinking Science Vol 134 2011-2017 December 22 1961 31 I P PAVLOV Conditioned reflexes Oxford University Press New York N Y 1927 32 D A SCHOLL A M UTTLEY Pattern discrimination and the visual cortex Nature 387-388 February 28 1953 33 W A CLARK B G FARLEY Generalizations oj pattern recognition in a selJ-organizing system Proc W J C C 86-91 1955 34 S BAKERS Techniques of adaptive decision tnaking General Electric Company Electronics Laboratory Technical Information Series R65ELS-12 Syracuse New York October 1965 35 G L ~AGY Prospects in hyperspace: Stale of the art in pattern recognition IBM Research Paper RC-I869 IBM Watson Research Center Yorktown Heights New York June 1967 36 M D CANON C D CULLUM The determination oj optimum separating hyperplanes I. A finite step procedure IBM Research Report RC-2023 IBM Watson Research Center Yorktown Heights New York June 1967 37 L UHR Pattern recognition John \Viley 8,ild SoilS IIle ~ew York l~ Y 1966 38 G S SEBESTYEN Decision-making processes in pattern recognition Macmillan Company New York N Y 1962 A model of visual organization for the game of GO by ALBERT L. ZOBRIST University of Wisconsin Madison. Wisconsin INTRODUCTION" No successful GO-playing program has appeared in the literature, although Remus! used GO as the subject of a machine learning study, and Thorp and Walden2 have considered some of its mathematical aspects. Another auihor 3 considered GO to be. somewhat mysterious, making it a challenge to those interested in automating it. Apparently the game was described as being mysterious to indicate that people were able to play it without knowing how they were able to play so well. More study of this complex game may reward us with new insight into human perceptual and problem solving abilities as well as foster the development of new techniques for artificial intelligence. This report describes a program which plays GO. The program uses an information processing model to produce perceptual features which are seen by human GO players, and is capable of several responses to the recognition of significant configurations of these perceptual features. A brief description of GO The rules of GO are deceptively simple. The two players alternate in placing black and white stones on +.1-.£11 " ..... v ;n+A...."o ... i-;",n", "'.; .&..L.... uv.LI.;:n.... '-'u.Lv.l.~ V~ n U 10 vA ~1J 10 """~~ Q+"",,,~ ",f +\..." ~,,~~ ~lJ 6J.~U.. UUV.l.J.CO V.1 \lJ.J'Ci OQ.111t:; which are connected by row or column adjacency fonn a chain. Diagonal adjacency is llot ~yffici~llt to connect a chain. The empty intersections which are adjacent to a chain are its breathing spaces. When a chain has no breathing spaces, it is captured by the opponent, and the captured men are removed from the board. A player may place his stones anywhere on the board with two exceptions: (1) he may not form a chain with no breathing spaces unless he is capturing, and (2) he may not capture one stone which has just captured one of his stones on the previous turn. A player may choose to pass at any turn. The game is over when both 00101' of the players pass in sequence. A player's score is the sum of territories surrounded by his color plus the number of opponent's stones captured. Some of the basic consequences of these rules are illustrated by the right side of Figure 1. White can always capture the top black chain, but cannot capture the bottom black chain, if black moves Figure 1 properly. If black moves at either of T2 or T3 then white cannot occupy all of the breathing spaces of the black arIllY without committing self-capture. This is because the black army would have two separate eyes. The ability to form two eyes is what determines whether an army is safe or not. White will score 16 points in the upper right, and black will score four points in the lower right corner. If white moves RIO, then black may not respond Rll, but must move elsewhere on the next turn. This prevents cyclic capture. The rules scarcely describe how GO is actually played. Interested readers are advised to seek a demonstration from someone who plays GO, or to read one of the OOginner's books. 4 ,1i The situations in the left hand corners of Figure 1 are representative of real play. Although the stones are not connected into long chains, they threaten to form chains which will surrQund +~-!+,,_. ~l,,_~ +\...~ ~,, __ ~~ ~_~ ..... ~ ..."'" ",.fl ~\...'"' h"'n ..~ lJCllIIJVI'y <:IoIVlle lJllC \JVIllCI.:> <:IollU V.l Efficient play· requires that as much territory be s~~tQhed out with ~ few §to:p.e~ ~ possible. Throu~h." out the rest of this p~pef' !ilyen aggregat~ 0,1 stq:qes which threaten to inv9.d.e or surround territory will be called armie8. CU5~ UUlV ....~~ ....... The problem of complexity GO is considered more difficult than chess by many people who know both games.1i Numerical measures of the complexity of checkers, chess, and GO tend to SUp'" port this belief. The number of paths down the move 103 Spring Joint Computer Conference, 1969 104 ABCDEFGHJKLMNOPQRST 19 19 18 17 16 15 14 13 12 II 10 9 8 7 6 5 I I I I I I I ! ! ! I I I8 I 7 16 15 14 13 I 12 II 10 9 a 7 '- ~ I i I ods which correspond to the development of strategies. Time will tell whether a successful GO playing program can be written using such methods. - 4 4 3 2 3 2 I I ABCDEFGHJKLMNOPQRST Figure }-An illustration of GO tree has been estimated at 1()40 for checkers6 and 10120 for chess. 7 A rough estimate for the number of paths down the move tree for GO is 361! or 10761 • By this reasoning, GO played on a 6 X 6 board would be comparable to checkers in complexity, and GO on a 9 X 9 board would be comparable to chess. A slightly better extimate of the true complexity of these games may be obtained. For checkers, suppose that a choice of three reasonable moves occurs approximately 20 times per game. Then 320 is a crude estimate of the number of checker games which might occur in ordinary play. Good chess players usually. consider less than five move choices, hence 560 estimates the number of reasonables chess games. A typical GO game lasts about 300 moves and a choice of 10 reasonable moves occurs at least 100 times, thus there are at least 10100 GO games which could occur in hlL.'lln play. Such calculations, however crude they may be, are important to anyone interested in the automation of these games. The complexity of GO may hinder attempts to program it with the methods developed for chess and checkers. 6 ,7,8,9 The move t.ree for GO is ex':' ceedingly deep and bushy, hence any form of heuristic search can explore only a relatively small portion of the complete tree. An alternative approach might be to concentrate upon extremely powerful methods of evaluation of the board situation, thus enabling better play with a more restricted search. Another possibility might be to have the lookahead be directed. by pruning meth- The visual natu1'e of GO The recognition and discrimination of meaningful perceptual stimuli presupposes the active formation of stable perceptual elements to be recognized and discriminated. A person lacking this process would combine all sorts of stimuli into meaningless groupS.10 The choice of a move in GO usually involves the recognition of configurations which are meaningful to the player. This raises the question as to whether certain basic perceptual processes are necessary for the comprehension of a GO board. The following examples might suggest that the answer is yes. First, consider the spontaneous grouping of stones of the same color which occurs during visualization of a GO board. The stones are organized into distinct groups, clusters, or armies even though they may be sparsely scattered about or somewhat intermingled. Grouping is usually the result of proximity of stones of the same color or the predominance of stones of one color in an area, but can be affected by other characteristics of the total board situation. For example, stones which fall into a line are likely to be grouped. Kohlerll and others have found grouping to be a basic perceptuai .phenomenon. Yet the recognition and discrimination of groups or armies is necessary for competent GO play. Closely related in grouping is segmentation, which is also discussed in Kohler. The area subtended by the board is divided into black and white territories, each of which maintains its own integrity in the visual field. These segments are a measure of the territory which is controlled by either side, hence are an important factor in the assessment of a GO board. Another example is the formation of "spheres of influence" about a stone or group of stones. Influence is not an inherent property of stones, but appears to be induced in them by our processess of perception. Yet they are a crude measure of the potential of a stone or army of stones for controlling territory on the board. The spontaneous image' formed by the visualization of a GO board appears to be a complicated assemblage of perceptual units and subunits. For example, the st.ones themselves have their own perceptual identity while at the same time they are parts of chains or groups of stones. The phenomena discussed above show that some of these perceptual processes may be very important to the ability of GO players to comprehend this complex game. It is not within the scope of this report to discuss flLt1:her the psychological nature of these perceptual Model of Visual Organization for Game of GO mechanisms, or to speculate upon the physiological basis for them. Let us adopt the term visual organization to mean the formation of such stable perceptual elements as have just been discussed, and let the resulting "mental picture" be called the internal representation. Given that a player "sees" a fairly stable and uniform internal representation, it follows that familiar and meaningful configurations may be recognized in terms of it. The result of visual organization is to classify a tremendous number of possible board situations into a much smaller number of recognizable or· familiar board situations. Thus a player can respond to a board position he has never encountered, because it has been mapped into a familiar internal representation. This report will describe a simulation model for visual organization. It will use transformations which create information corresponding to the perceptual features discussed above, storIng them in a computer internal representation. A heuristic for visual organization We now examine the problem of modeling the basic visual organization of the GO board. A reasonable goal would be to determine the segmentation of the board, the domains of influence of the stones, and the armies of stones, storing that information in a computer internal representation. Before building the computer model, it is of interest to consider physical processes which give some measure of the influence of physical bodies. There are many candidates in the physical sciences for the process we desire. For example, white stones could be electrons, and black stones could be protons. Contiguous areas of positive or negative potential could determine the segmentation of the board, and the value of the potential would measure the influence of the stones. Of course, the solution would be discretized to the points of the GO board, and the potential at an unoccupied point could determine how well protected that point is by black or by white. For another candidate, let the GO board be made of blotter paper and simultaneously place a drop of oil under each black stone and a drop of water under each white stone. Contiguous areas of oil or water would determine the armies and the segmentation of the board. Since the oil and water would spread evenly, the concentration would not indicate the influence of the stones or even their location. Other possibilities might involve electrical networks or heat conduction, etc. These physical models are considered because they are well defined and easily calculated, whereas the visual process we are attempting 105 to model is ill defined. Let us consider in more detail the first two examples given above. In the center of Figure 1, the electric charge analogy woul~ give the black stone at J10 some weight to the right of the wall of white stones, whereas oil from the black stone ~ould never get past the wall of water spreading from the \V hite stones. Perceptually speaking, the black stone has no influence to the right of the white stones. The oil and water analogy could not differentiate between the two situations in the right hand corners of Figure 1, whereas the electric charge analogy would show four strongly surrounded squares in the lower corner. Thus the oil and water analogy does not reflect our perception of this situation. The finite difference method used by the program was chosen with both of these models in mind, and has the good features of both. It is assumed that a game is in progress and the board position is stored. The position is transferred to a 19X 19 integer matrix by placing 50 for each black stone, -50 for each white stone, and 0 elsewhere. Then each point which is positive sends out a + 1 to each of its four neighors, and each negative point sends out a -1 to each of its neighbors. These numbers are accumulated as this procedure is repeated four times. Figure 2, which is taken from the game listed at the end of this report, illustrates the results of the visual organization heuristic. The negative integers are indicated by an underline. Segmentation can be assessed by determining the contiguous areas of positive or negative integers. The dashed lines in Figure 2 indicate the resulting segments. The stones which lie in a segment may be considered to be a group or army. The integer values at a point give a measure of the degree of influence exerted by the stones nearby. The influence of stones of the same color may reinforce one another, whereas the fields from opposing stones seem to repel and cancel one another. Inspection of Figure 2 should convince us that at least a crude resemblance to perceptual processes has been obtained. The array of Integers from the visual organization heuristic contains, at least implicitly, information corresponding to an internal representation. This heuristic, together with a routine which is capable of creating an explicit computer internal representation of the resulting information, will be part of a model of visual organization. The specific details of the entire GO-playing program will now be given. The program The program is written in ALGOL for the Burroughs B5500 computer. Interaction is provided by remote teletypes. Each move requires 5 to 8 seconds of central Spring Joint Computer Conference, 1969 106 I ABC 0 E F G HIJ K L M N 0 P I 19 18 17 16 15 14 13 I9 I8 i7 I6 I5 I4 I3 I ,f-- 1'-= "\ _ r ~- ~- ~- : ! ~ ~. J J ~- ('J ("r.J -- I (' ',J I II 10 i '\ 1 ! ! (' \. J 9 8 '\: I 1. ~- -h 6 I I ! 5 4 ..~ ,r: ~-J;;I I ~-. J ~r 1-- h "t\ r i 10 9 ! r. J 8 ! i 7 I ,,~- ~-~ 6 I 5 -.~- , "'~- F-- rho' I ,! 3 2 '-= Part I 2 -~, ; Part I realizes a model of visual organization for GO, producing an analogue of a human player's perception of the board. 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This part of the program consists of a set of computations which transform the board position into a computer internal representation. The internal representation contains an analog of important perceptual features of the board position. This information is stored in seven 19X 19 integer arrays in an explicit fashion. That is, the integer values are a direct measure of the features they represent. For example, consider the features of perceptual grouping and segmentation which have been determined by the visual organization heuristic. It would not be easy to reference this information in the array shown in Figure 2. Another process must create an array which gives a direct measure of the size of the segments and the groups of stones. Figure 3 illustrates the results of the processes which sz. r" i --- -- ~- I I --_. -- -~ -~-- •~: I a ~~2~.l62112lQ6210§.§.~106211111 ZU ! 2 u. .s& §J 1& ~ 2 2 1 ~ §. ~ lQ ~ !t: 1 !t: .l !t: !t: 1.J± ~ 10 2 Z ~ Q ~ ~ .l .l 603 603 603 603 603 603 I i !t: 1 ~ Figure 2-Results of the visual organization heuristic prooessor time or about 5 to 20 seconds of real time, depending upon the number of users being serviced by the system. The machine code occupies 6300 words of core memory and 5400 more words are required for storage arrays. The program has two distinct parts. Part I has a coordinated set of procedures, including the visual organization heuristic, which operate on the board position to produce a computer internal representation. Part II has a set of procedures which use the internal representation to calculate a move. 603 603 603 704 704 704 r------------704 704 704 I I 603 603 603 JI ____________ 704 704 704 704 704 704 704 704 704 704 704 704- 501 501 704 704 704 704 I 704 704 704 704 ---------, 501 501 I I I I Figure a-Internal representation of grouping and segmentation Model of Visual Organization for Game of GO calculate perceptual grouping and segmentation. These processes act upon the array of integers produced by the visual organization heuristic to produce an array of integers which are a part of the internal representation. One of these numbers (e.g., 603) may De interpreted as follows: the hundreds indicate the size of the segment which covers that point (600 is a mediumsized segment) and the ones indicate the number of stones which lie in that segment (there are 03 black stones hence 600 + 03 = 603). 500 indicates a small segment with less than 10 empty intersections, and 700 indicates a large segment with more than 25 empty intersections. If no segment covers an intersection, then 0 is stored in the corresponding cell of the array. The empty intersections in a segment are counted as they are a better measure of the safety of the army of stones in a segment. The information is compressed by having the size and the number of stones in the same array for purposes of efficiency only. The array shown in Figure 3 is typical of the seven arrays which constitute the computer internal representation. Numerical values correspond in an explicit fashion to feature which we have considered to be formed by visual organization. The second array gives a numerical measure of the influence of the black and white stones. It is an exact copy of the array of integers shown in Figure 2. The third array measures the number of breathing spaces in a chain. This array is illustrated in Figure 4. The fourth array measures the number of stones in a chain. This array is calculated in the same fashion as the third array. The other three arrays of the internal representation contain integers which indicate the color of stones, the color of segments, and the number of stones of each color which are adjacent or diagonal to the points of the board. Part II The second part of the program uses the recognition of "familiar" configurations in the computer internal representation as the basis of its calculations. The mechanics of this recognition process will be described first. Figure 5 illustrates a configuration which the program is able to recognize. At point A, there is a black stone which has only one breathing space left. Point B is an empty intersection. Point C has a black stone which may be part of a safe army of men. Note that the geometric arrangement of this 3-tuple is as important as the three features. The program contains a prototype of this configuration which we shall call a template. 107 '" ,,, " o " " o o o o o o o o o o o 2 5 5 o 6 I o o o 6 6 o o o o o o o Figure 4-Intemal r'epre..<;entation of hreathing spaces 108 Spring Joint Computer Conference, 1969 I I 1'1"\ ... ~ '101' I"!I. "- I I ..... ""A I """c ..oil 'II B f I Figure 5-Illustration of a :,;ignificant configuration A template consists of an n-tuple of references to the internal representation together with a specification of the geometric arrangment of the elements of the n-tuple. Thus the template for our situation ABC is: (0,0) (1,0) (1,1) black stone, 1 breathing space empty intersection safe black stone. The pairs of numbers are the relative coordinates of the references. The references themselves must be translated into a numerical form which can be used to process the internal representation, for example: safe black stone = 601 thru 900 in array 1 and 1 thru 1 in array 7. That is, a point satisfies the reference "safe black stone" if the value of that point in array 1 of the internal representation lies between 601 and 900 inclusive and the value in array seven equals 1. A 1 in array seven tells us that we have a black stone on that point, and a 601 to 900 tells us that we have at least a mediumsized segment. The program has the ability to scan such templates to all positions, all rotations, and all reflections of the board, thus recognizing the configuration- ABC wherever it occurs. If the template is carefully specified, then configuration ABC can be quite a general occurrence. For example, Point A could be connected to a chain of stones with 1 breathing space left. Allowing this would give the template more generality. The present program has 8;) templates capable of recognizing a wide variety of configurations. A template that matches implies either a move or a heuristic lookahead procedure. In fact, there are two types of templates for these two purposes. The first type of template specifies a weight of implication and a pair of relative coordinates for the move which is implied. For example, the template for configuration ABC described above would specify (1,0) 500 which means that a weight of 500 is assigned to the point B in Figure 5. These weights are stored in a special 19 X 19 array reserved for this purpose. Several templates may imply the same move in which case the weights are summed in this array. The highest sum of weights indicated the best move. Bad moves and illegal moves usually have a negative weight. One more example of this type of template will be given: (0,0) (1,0) (0,0) white segment black segment weight 40. This template implies a move with weight 40 at the interface between opposing segments. A weight of 40 is relatively small, hence it will merely give a tendency towards moving in these areas. This template is very general; it can match as many as 100 times in a single scan of the board. It gives a slight tendency to move between opposing armies which. helps the program's play. There are 65 templates which imply moves in the manner just described, the other 20 templates imply a heuristic lookahead. The difference between these two types of templates is that instead of a weight being placed in the weight array, an x is-placed in a 19 X 19 array as an indication of the template match. The x's are a mark to indicate that a move tree search should be performed in the local area about the x. All of the templates are applied before the search is begun. Figure 6 illustrates a configuration which would be matched by some of the 20 templates, and the location of the x's placed by those templates. The array which contains the x's is used as a mask to determine the extent of the search and the depth is fixed at two moves for each side. The search is actually performed twice, once for ·white moving first, and once for black moving first. At the end of these searches, it is noted whether either side can force a capture by moving first. This information tells the program whether a move is necessary to cause or avoid a capture. Model of Visual Organization for Game of GO ,~ , '4 I't\ .... I't\ " ," "I' '" ,II .... , ji' ....... 1" .... ,~ .. II. ... I't\ .... 109 ,~ ~, "'~ '1' '\11 jl' " " " " J"'''' ~~ " ~., J"" J"'''- " ,~ i'" " 1" .... Figure 6-Creation of a mask for lookahead For example, if black can capture whether he moves first or not, then it is unnecessary for him to move. The decision to move is recorded by placing a weight of 4000 in the array already discussed in connection with the first type of template. In many cases a depth of two moves is not sufficient to determine whether capture takes place or not. The most common instance of this is known as the "ladder attack" which is illustrated in Figure 7. These situations are characterized by the repeated occurrence of moves which force the opponent to reply or to be captured. In such cases, the search procedure continues to a depth of up to 100 moves to see whether capture finally takes place. No branching takes place during this extension of the look ahead. When all of the templates have been applied and the heuristic search procedure is through, the program simply chooses the move which corresponds to the highest sum of weights in the array of weights. If the maximum weight is below 100 then the program passes. This completes the description of the program except for a few minor details of operation. Three seconds are used for the creation of the internal representation and two seconds are used by the template matching procedure. The heuristic search takes from .1 to 4 seconds. A challenger has the option of moving first or second, and can also give the program a handicap of any number of stones on the board. The program is not able to haggle over the final score as GO players Figure 7-Illustration of the "ladder attack" often do, hence a referee may be required to supervise the scoring. RESULTS The program now has a record of two wins and two losses against human opponents. The opponents can best be described as intelligent adults who know how to play GO, have played from two to twenty games but have not studied the game. The program appears to have reached the bottom rung of the ladder of human GO players. Interested readers are urged to get a GO 110 Spring Joint Computer Conference, 1969 board and play through the game listed at the end of this report. The first type of template, those which imply moves, are responsible for about 80 percent of the moves made by the program. These templates give the program fairly good positional play, especially in the first part of the game. The remaining templates, together with the lookahead search, are valuable for avoidance of traps which cause the loss of a stone or two. The opponent's play is also restricted since he must play more carefully. The loss of one stone can have a great effect upon the outcome of the game. The program is able to play without these templates, hence without the search, but opponents soon learn to take advantage of this weakness. The program plays as if it can "see" such things as the influence of stones, the segmentation of the board, and the armies of black and white' stones. This alone makes it a reasonable candidate as a model of visual organization for the game of GO. It would be of interest to test the model by performing standard psychological experiments. For example, a drawing of a GO board could be shown to a human subject with the instructions to segment the board with dashed lines. The results could be compared with the segmentation given by the program. Further work may show how i...llportant perceptual mechanisms are to the ability of humans to play GO. APPENDIX: A GAME BETWEEN THE PROGRAM AND MR G. COWAN The following game, played between the program and lVIr. George Cowan, demonstrates that the program has reached at least the bottom rung of the ladder of human GO players. Mr. Cowan is an undergraduate at the University of Wisconsin, and had five games experience at the time of the contest. The even-numbered moves are by the program (white). Moves which resulted in a capture are indicated by asterisks. The comments are by Professor Paul Purdom, a good GO player, who has shown patient interest in the various GO-playing efforts at Wisconsin. 1. D 3 Q3 3. E 9 D17 5. Q16 H12 too early for such a move 7. F15 R15 too close to opponent 016 M 8 9. 11. R14 H 8 shouldn't give up the corner 13. lVI12 C 5 D5 F12 15. D 7 17. J17 still important moves rernail1il1g in the corner 19. M17 R 8 21. R 5 S 4 23. Dll K 3 25. Q11 G 5 27. Q15 F 6 29. K16 F17 31. G16 G17 33. H16 F 3 35. E13 E 2 still ignoring upper left side 37. Q 7 F 8 wasted move S 7 J18 39. Q 8 o 5 41. R9 P 6 43. R 7 8 8 45. R6 8 9 47. T8 T 9 49. T 7* 810 51. T10 RIO 53. 811 Q9 55. TIl * Rll 57. 812 08 59. 8 6 P 7 61. P 9 T6 63. Q6 Q10 65. P10 810 67. a free gift from black 011 Q12 69. R13 010 71. PH NH 73. N10 a better move R12 H17 75. D2 J16 77. P12 B 3 79. B14 Q13* 81. at last! C14 better 817 K17 83. 815 R16 85. seems to ignore sacrifices 816 814 87. R18 R17 89. F 9 Q18 91. 819 818 93. T17 R19* 95. T14 T19* 97. both players wasting moves FI3 T13 99. T15* T16 101. Model of Visual Organization for Game of GO T18 103. GI4 T16* 105. JI4 JIO 107. JII J12 109. K12 Kl1 better N10 J13* 111. wasted o 9* P 8 113. K9 L14 115. M14 L13 117. M13 better KI5 K9 119. L15 MIO 121. Mll Lll 123. N12* N13 125. Q 5 MI3 127. M15 129. 013 N7 131. N6 should connect N8 and cut stone o7 133. P 5 P14 Q4 135. 137. LIO M9 L9 KIO 139. 141. L 8 L 7 143. K8 J 8 145. L12 K 7* KI4 147. E 5 149. K13 H10 wasted 151. N14 P13 153. F16 E16 155. E15 D15 157. C16 C15 159. E18 E 7 161. E17 D18 163. D16* C17 165. B17 CI8 167. B18 FI8 169. EI9 H18 171. K18 GI9 173. J19 FI9 the program would be much better if it could recognize eye possibilities 175. EI6 B19 177. B16 H15 179. E12 Fll 181. EI4 B 7 183. B 8 C 8 185. B 9 R4 187. C 9 S 5 189. A 7 T 5* 191. B 6 D6 193. D 4 D8 C 7* B 7 D9 EI0 Ell FlO G15 J15 F14 L 4 L 3 K2 M2 M4 L 2 K5 M 1 J 1 J 2 195. 197. 199. 201. 203. 205. 207. 209. 211. 213. 215. 217. 219. 221. 223. 225. 227. 229. 231. 111 C 6 E8 C 4 B 5 E 4 GI0 G9 H14 012 L 5 K4 M3 N3 N4 N2 J 5 K 6* H2 J 3 It was agreed to stop the game at this point. The resulting score was: Mr. Cowan ... 59, program ... 66, a seven point victory for the program. Approximately 15 minutes of computer time was used, and the entire contest took less than two hours of real time. ) ACKNOWLEDGMENTS This research was conducted with the support of NIH grant MH 12266 and NSF grant GP 7069. BIBLIOGRAPHY 1 H REMUS Simulation of a learning machine for playing GO Proc IFIP Congress 1962 2 E THORPE W WALDEN A partial analysis of GO The Computer Journal Yol 7 No 3 1964 3 I GOOD The mystery of GO New Scientist January 21 1965427 4 0 KORSCHELT , The t~ry and practice of GO Tuttle Rutland Yt 1966 5 E LASKER GO and GO-MOKO, the oriental board games Dover New York 1960 6 A SAMUEL Some studies of machine learning using the game of checkers IBM Journal of Research and Development Vol 3 No 3 1959 7 A NEWELL The chess machine Proc Western J C C 1955 8 C SHANNON Programming a digital computer for playing chess 112 Spring Joint Computer Conference, 1969 Philosophy Magazine March 1950 9 R GREENBLATT D EASTLAKE III S CROCKER The Greenblatt chess program Proc F J C C 1967 10 P GREENE Networks which realize a model for information representation Transactions of the University of Illinois Symposium on Self-Organization 1961 11 W KOHLER Gestalt psychology Liveright New York 1947 Assembly of computers to command and control a robot * by LOUIS L. SUTRO Massachusetts Institute of Technology Cambridge, Massachusetts and WILLIAIH L. KIL:JJIER Michigan State University East Lansing, Michigan INTRODUCTION There is a growing consensus among predictors of science that the world is about to witness the evolution of 'what might be called a new species-the robot. Whereas, animal evolution was a trial-and-error process, robot evolution appears likely to be carefully contrived. Starting where animal evolution left off, that is, with man, robot evolution promises to excel man is some respects, and be excelled by him in others. To the computer profession, one challenge in this progression is to develop computers for robots that match those that have been found indispensable in men. We are aided in this task by the description of the human nervous system in computer terms by physiologists such as Warren JicCulloch. With his description before us, we have devised working models of t\VO of the five principal computational domains which he identifies in the nervous system of vertebrates, including man. Others are devising working models of other domains. Implemented in light, portable hardware and connected together, these computers promise to provide intelligence for a system that will sense its environment, move about and perfonn useful tasks. * The work reported here was supported in part by NASA Office of Space Sciences and Applications, Bioscience Programs, under Contract XSR 22-009-138, in part by XASA Electronic R~arch Center under Grant NGR 22-009-140, in part by AIr Force Office of Scientific Research under Grant AF-AFOSR1023-66, and in part by the U. S. Air Force, Wright-Patterson B~se, through contract AF 33(615)-3885. Who needs a robot? Everyone who would like help with tiring chores. However, early models with large arms and wide wheelbases cannot move around the home or office. One need that has led to the development about to be described is exploration of the planet lVlars. For this task, robot development is being pursued not as an end in itself but as a framework within which to develop an automatic visual subsystem. A second need is for a computer to command a system receiving several forms of input, such as sight, sound, touch, and reports on its own movements. Here again robot development provides the framework for the computer development. As well as can be detennined, l the surface of ~fars is open country where a wide-wheelbase vehicle should be at home. ::Hore to the point, the only exploration there for a decade or more will have to be either by a remote-controlled or an automatic vehicle. The distance is such that a single bit of infonnatioll requires V5 minutes, on the average, for transmission from Jlars to earth. '¥ith such a transmission delay, remote control seems hardly practical. An automatic vehicle or robot thus seems imperative. While the surface of Jlars is colder than the surface of the earth, there may be hot spots due to volcanic or other sub-surface activity. All the moisture on lVIars, according to our instruments, is in the form of either gas or ice. The atmospheric pressure is too low to hold it as water, but it might pass through the water phase in these hot spots, lasting as water long enough to make possible life as we know it. 2 To go to these hot spots, if indeed they exist, poke 113--------------------------------- 114 Spring Joint Computer Conference, 1969 around them, pick up and examine samples seems the best way of finding out what is there. Even if there is no life on lVI ars , there are cliffs formed at the edges of craters, that need to be examined for their geology. The craters need to be climbed into and out of. To go from one crater to another, crossing must be made of the ravines called "canals". Research and development The robot design described here began as an effort to design eyes for the artificial intelligence that Marvin l\1insky and John McCarthy called our attention to, in the fall of 1958. Persuaded that eyes for artificial intelligence could be achieved only by employing ideas from anin.lal vision, one of us (Sutro) approached Dr. lVlcCulloch for advice. The collaboration that ensued led first to an analytical model of an animal retina that recognizes objects, namely, the retina of a frog. 3 •4 It led next to a proposal to NASA to develop means of reducing, for transmission to earth, pictorial data acquired in the search for evidence of both life and geological changes on lVIars. Supported then by the NASA Bioscience Programs, we undertook this in the maIUler Dr. IHcCulloch and we thought best, namely, to model animal vision in lightweight, low-power hardware. Study of frog vision showed how recognition of a simple shape (a bug) can be achieved in two levels of computation, but it did not carry far enough the data reduction we felt was required. ~ eeded, we felt, was reduction of a stereo pair of im~ges on :Vlars to a pair of line drawings with shading, as we primates do. Geologists and biologists make line drawings with shading to represent what they see. The lines portray edges, angles and silhouettes. The shading conveys the brightness of surfaces. IVIan forms in his head a model of what he observes. Formation of a line drawing with shadings is a stage in the computation of this model. However, as Dr. McCulloch points out, the vision of a primate cannot be modeled by itself. Data flows not only inward from the images, but outward from the brain to adjust the filters, focus, convergence and direction of gaze that select what will flow inward. For a visual system employed in a single position on l\iars, these adjustments can be either preset or changed by commands from earth, but when the system is required to move about, the commands to adjust it can scarcely be sent from earth. They have to be generated on site. To develop a command computer one of us (Kilmer) undertook to model the part of the vertebrate brain that decides from information received through all the senses what class of thing the animal will do from moment to moment. This is the core of the animal's reticular formation, extending through its brain stem and the length of its spinal cord. Support for its development came first and continues from the Air Force Office of Scientific Research, came then from NASA's Electronic Research Center, and comes now from the U.S. Air Force bionics programs. Cameras and computers under development are pictured in Figure 1. At the left is a binocular pair of TV cameras of which sufficient study has been made to indicate that each camera can be built to view the world through both wide-and narrow-angle lenses. Receiving the output of the camera is the visual first stage computer which enhances contrast in an image, as an animal retina does. Next to it are switching filtering and comparison structures, we call the visual second stage computers. A model of the environment consists of relations formed in this second-stage visual computer and stored in the visual part of the relational computer. A line, which indicates sharp change in luminance, is a relation of high spatial frequencies. Shading, which indicates the difference in luminance of areas, is a relation of low spatial frequencies. Each filter passes one band of frequencies more than others. Commands to adjp.st filters, focus and direction of gaze are shown a.8 arrows rising from the command computer in Figure 1. Since these commands '\-vill pass through structures not shown, the arrows are not drawn directly to the cameras and visual computers. Note the dashed boxes. The present locator of edges and shades, represented by a solid box, forms a stereo pair of monocular line drawings. The dashed box marked "binocular" represents computation now op~rating separately to determine that pairs of points in the left and right views are stereoscopic (stereo), that is, representative of the same point in threedimensional space. Binocular, or range-finding, computation will be merged with the locator of edges and shades. At first, we called a vehicle designed to carry this system "rover". As we came to conceive of it with other senses, beside vision, and other effectors, beside wheels, we renamed it "robot." Biological computers From his life-long study of the human nervous system,S Dr. Warren McCulloch has concluded that the essential features of its computations provide a good basis for the design of a robot. Although as a neurologist, psychologist and physiologist, he is aware of the difficulties involved in embodying mental functions in physical devices, he has nevert.heless developed a simplified model of a vertebrate braL.'1. Assembly of Computers to Command and Control a Robot 115 N contrast between adjoining luminances, the filter will make the dark side of an edge darker and the light side lighter, thus forming Mach bands along the edges of the stone, the stick, the hills and the crater. The vertical lines in the displays of FigUle .5 are due to the method by which the computer of Figure 7 acquired pictorial data. As the electron beam of the camera scans each horizontal line of the raster, the computer commands the reading of one luminance ** A stereoscope for viewing this illustration may be obtained from Air Photo Supply, Yonkers, X.Y. Assembly of Computers to Command and Control a Robot 121 Figure 5--Left-eye-view scope displays at level 1 (left) and level 4 (right) in the computation of the line drawings of Figure 6 Figure 6-Line drawings formed at leveI7:Fine-lineleft-eye-view (left), coarse-line stereo pair (right). To see in stereo, look through a stereoscope at the crater, glancing nearer occasionally at the edges of the rocks and hills measurement. 10 Since the computer employs the same conunand as long as it can, successive measurements are on vertical lines. The unevermess in the spacing of the lines is due .~ 0 nonlinearity in decoders of the display. Figure 6 (left) is the result of applying, at levels 5 and 6, an edge-detecting filter and· threshold, that represent Hteep changes (gradient) in luminance by a fine line. Figure 6 (right) is the result of applying a filter and threshold that represent such changes by a wider and, in this case, more continuous, line. 1t it; thus possible to pick different features from a scene by employing at level 5, different edge-detecting filters and, at level 6, different thresholds. The filters employed at level 5, in producing these illustrations, detected the horizontality and verticality of edges separately, but this information 'was not kept separate in making the line drawings. For details see Appendix A. When contrast is high in the scene, as in Figure 8 (left), first stage visual computation can be skipped. Figure 8 (left) is a photograph of the TV monitor (not the oscilloscope display as in Figure 5,· left) when the scene was lighted from the back left, creating higher contrast than was the case for Figure 5 (left). Levels of computation 2 and 3 were omitted and a. narrow-edge detecting filter was employed at level 5. Thus, both contrast enhancement and. feature deteetiOIl can be va.ried, not only for the entire image, but for each matrix within the image, under control of either a remote human operator or a local conunand computer. This position-by-positioll control of the processing of the image, represented by the leftward 122 Spring Joint Computer Conference, 1969 LONG-PERS ISTENCE"-' DISPLAY t;~~ : GRAY-SCALE i'e ')! Figure 7-Equipment for simulating light-weight, low-power hardware; (above) Camera-computer chain for simulating visual computers, (below) binocular, or stereo, TV camera arrows in Figure 1, separates our work from that at JPL. It makes perception possible. Line drawings, such as those in Figures 5, 6 and 8, do not convey enough information for a scientist on earth to judge what is being pictured. However, by the addition of low-resolution luminance data to left and right views, and presentation of the two views stereoscopically, there may be enough information. Figure 10 is an example of levels 5 and 6 COhlputation alone on data received from the scene pictured in Assembly of Computers to Command and Control a Robot - 123 I ---f----~--~--~--~r-~--~ I ~----~---+--~~--~- Figure 8-Formation of line drawing by levels 6 and 7 computation alone. Left-eye views of (left) image on TV monitor before being digitized, and (right) negative of scope display at level 8 Figure ll-Grid of scene luminance values superimposed on Figure 10 Figure 9-Photograph of scene to be formed into line drawing with shading • Figure 12-Painting "rith shades of gray prescribed by lines and values of Figure 11 Figure 1(1--Computer-generated line representation of scene Figure 9. Figure 11 shows coarse-resolution measurements of luminance on a scale from 0 to 7, which an artist employed to paint in the swatches of gray in Figure 12. When this reconstruction is perfonned by computer, it will illustrate how the appearance of a Martian scene can be reduced for transmission from Mars to earth and then reconstructed on earth for viewing there. The data reduction here is by a factor of 30. The stereo pair of views, shown being reduced in Figures 5 and 6, was not taken with the mirrors illustrated in Figure 7 but by taking one at a time, moving the camera between takes. This is simpler for a report. Hardware version of t'isual first-stage computer We designed the computation first so that it could be implemented in light portable hardware; then we 124 Spring Joint Computer Conference, 1969 simulated this hardware in the computer of Figure 7 and achieved the results described above. The hardware design, diagrammed in Figure 13, is inspired by the layered structure of the animal retina and laterial geniculate body of the thalamus. Since it is not practical to represent in hardware the large number of cells of these animal structures, only a cluster of cells of each layer is represented and data are moved past the cluster by shift registers. A camera containing a single vidicon, that receives left and right views from mirrors, is shown in preference to two cameras because the fonner arrangement ieads to much less uncertainty between the two optical paths. 10 Ia Figure 13, left and right images of an object such as a rock are projected by the optics onto the face of the vidicon. Converted to digital fonn, the signals enter shift registers (1) which move the images past computing elements (2) and (3), which represent clusters of living cells. The filter planned for level 2 is shown schematically at the upper left of Figure 13 and is given in detail in Appendix A. It consists of a central weight strongly positive, immediately peripheral negative weights and more peripheral weakly positive weights. The images are advanced from left to right in the shift registers at the same rate that the tip of the electron beam in the vidicon advances. As data reach the right end of the top row, they are transferred to the left end of the next lower row. In this illustration, Figure 13-Diagram of hardware to perform contrast enhancement when the electron beam of the camera tube has swept 13 lines of the raster, the shift registers in the bank are full. From then on, for each new position of the electron beam, computations take pl91ce in the box behind the shift registers, and one digital word is discarded from the right end of the 13th row of shift registers. Figure 14 shows test hardware under construction to perform levels 1, 2 and 3 computation, on five lines of the raster. Each of the lower five panels contains a shift register 6-bits deep. The registers shift the data past the computing element in the top panel. The medium-scale integrated circuits to be employed here, together with their wiring, can be packed into about 50 cu. in. With large-scale integrated circuits the volulne could be lOcu. in. lO Computation of range To perform second-stage computation, either a man or a robot needs a view from a second position. We refer to the two views as "left" and "right" since they are usually taken from the same horizontal baseline. If the levels of robot computation pictured in Figure 4 are for the left view, then either a second series of levels is needed for the right view or the levels need to be widened to accommodate both views. We have taken the latter approach in the design of the hardware. Animals compute range from comparisons of left and right images, at several levels of computation, and from the angle between the axes of the two eyes, Figure 14-Visual first-stage computer under construction. The top panel is the computing element. The other five are shift registers. Integrated circuits piug into the far side Assembly of Computers to Command and Control a Robot 125 SUMS OF DIFFERENCES ARE STOIED FOR WIDTH OF LIKfLY AREA; SUM OF THE DIFFERENCES BETWEEN CORRESPONDING RESOLUTION ELEMENTS. MTH EACH SUM OF DIFFERENCES ARE STORED THE ADDRESSES ~ WINDOWS, WttCH ARE EMPlOYED N cnwUTlNG RANGE. MEASUREMENTS OF LUMINANCES IN A SCENE. Figure I5-Comparison of left and right views to determine range called the "convergence angle.' '11 The equipment shown in Figure 7 has been programmed to automatically compute range by comparing areas, in the left and right level 2 images, called "windows" (see Figure 15), To find a pair of windows that are vi~\ving the same object, a window is first fixed on say, the left view, according to some criterion such as the presence of an edge; then a likely area is located in the other view. Since this area contains as many potential windows as resolution elements along the horizontal axis, the problem is to determine which of these windows corresponds to the one fixed in the left view. The simplest way is to compare luminances in the fixed window with corresponding luminances in the likely area, determine the difference and use this as a criterion to decide when a best match is obtained. From the data of the best match, range is computed by triangulation. Employing this method, equipment shown in Figure 7 automatically explores a likely area to determine the range of an object at 20 feet with an uncertainty of 1.5 percent. To perform the comparison over the entire likely area requires 16 seconds. The comparison will be performed over less area if the robot visually follows around the edge of an object or visually explores increasingly deep into the scene. In these latter cases, the visual subsystem of the robot starts with a known range and reaches out from it. Perception In the robot we plan, the command computer, assisted by t~e relational computer, will determine what is seen ,by setting filters and thresholds in all stages of visual computation so as to match an iternallygenerated image with an incoming one. This "Keeping up to date the internal organizing system, that represents the external world, by an internal matching response to the current impact of the world upon the receptive system" is. called "perception. m2 "In a sense, the internal organizing system is continually making fast-time predictions on what is going on out there and what is likely to happen out there, and it takes anticipatory action to counter the small errors that might threaten its overall stability." A line drawing with shading, transmitted to earth for a scientist to view, aids his perceptual process, giving him clues about the presence of objects about which he can then demand more information. Within a robot, however, a line drawing with shading will be the result of interaction between the relational computer, setting filters and thresholds, and the second stage visual computer where these filters and thresholds are tried on incoming data. When equpiped to perceive, a robot will make fast-time predictions, possibly as detailed as the computer-generated image of Figure 16. Our general purpose computer formed Figure 16 from the equation of a cylinder, its diameter, height and illumination. It appears that perception of the cylinder could take place in the first and second stages of visual computation if the filters there are continually changed, as data are shifted past them, to search for predicted luminances in each part of an internally-generated image. 13 126 Spring Joint Computer Conference, 1969 Figure 16--Picture generated by computer preparatory to experiments in perception The concept of a command computer The purpose of a command computer, in an animal or robot, is to commit the entire system to one of a dozen or so mutally exclusive modes of behavior. An anim3J requires such a computer because it cannot " fight," go to sleep, run a way, and make love all at once. "14 Our study of a possible Mars robot indicates that it, too, can only enjoy one mode of behavior at a time. Possible modes of such a robot are: 1. Look and feel 2. Advance 3. Retr-eat 4. Right itself if overturned 5. Maintain itself 6. Chart its environment 7. Rest Perform incompatible experiments as follows: 8 Experiment A 9. Experiment B 10. Experiment C "Look and feel" is a separate mode from "advance" because the robot must be stationary while either its camera or its arm is employed. By "chart its environment" we mean that the robot, after advancing (or retreating) an appropriate distance, will establish what a surveyor calls a "station," and mark it with a transponder. Having determined the distance from the previous station and measured the angle between this and the second previous station, the robot can form a triangle in its memory to add to other triangles previously formed. By building triangle upon triangle, the robot establishes a grid with which it can determip.e how far it has gone and in what direction. Through this grid it can later pass, to return to points it has already visited. Within each mode are the detaHed sequences we call acts. Advance, for example, can be either slow, fast, or by turning. These details can be developed after the command computer has been designed to choose among the above modes. The command computer should be capable not only of selecting the mode of behavior, in response to inputs from the environment, and the other computers, but of changing the way it responds to those inputs. Ability to change the record of conditions under which it selects a mode is called "plasticity" and is exemplified by conditioning and habituation. The first simulation of a command computer represented only its mode-selecting ability. It was called S-RETIC where S stood for its ability to respond to both its present internal state and its spatially structured input. IS The second simulation is called STCRETIC where T stands for its ability to be influenced by temporal aspects of the environment and C for conditioning and habituation. The properties of STCRETIC together ,vith several new features are now being designed into special hardware to be called H-RETIC. The inputs to each of these RETICs represent connections from such subsystems as the visual, described in part above, and the contact, described in part in a later section. The number of input channels to the present RETICs is very much smaller than win be required eventually from, say, the visual subsystem of the robot. In fact, the number of input channels, (1'1 to 1'42 in Figure 17) is only as many as needed to demonstrate the principles of operation. How an animal is commanded In the core of the reticular formation of animals (retic), the selection of a mode of behavior is made by a matrix of fan-shaped cells embedded in regions that are stacked like poker chips. The input processes of each cell, its dendrites, give it both its fan-shaped and its poker-chip-like thickness .. Its output is an axon which traverses the long axis of the chip-like stack. Each cell in general receives signals from several parts of the brain, from many other reticular cells, especially those in its own neighborhood, and from several interoceptive and exteroceptive sensory -pathways. Collectively, these cells decide which mode of behavior the animal will enter. In its sharpest form, Assembly of Computers to Command and Control a Robot 127 SIMULATED INPUT Figure 17-Simulation model of the command eomputer, S-RETIC, and threshold units (Ti) that determine convergence. The Mi are logic modules; the Si are sensory systems; all Pi (only P7 shown) are modular mode-indicating output lines: ~ simulates a RETIC environment that engenders input signals (sight, sounds, etc.); T and Bare t.he top and bottom boundaries of S-RETIC; asc and dsc are the ascending and descending "nerve" bundles. For clarity, the connections that recur on all M modules are shown only on :vI7 this assertion is only a hypothesis; but broadly speaking it is an evident biological fact. The informational organization of retic is analogous to a board of medical doctors who must decide upon the treatment each of a series of patients must receive. Suppose there are twelve doctors on the board each a generalist, as well as a specialist in a different field of medicine, and that they must select one of four possible treatments. Their deliberations resemble the process by which S-RETIC selects a mode of behavior. Like the board of medical doctors, the command computer (retic) must cOlnlnit its charge to a mode of behavior which in most cases is a function of the information that has played upon it only over the last second or so (signals indicating mission are part of this). It receives information that is vast in amount, but highly correlated between input channels and arrives at one of a small number of mutually exclusive modes of behavior in a dozen or so tinle steps, with minimal equipment and maximal reliability. After 128 Spring Joint Computer Conference, 1969 a mode is decided upon, it must send oat control directives to the other agencies in its charge to tum them to their respective tasks. Finally, that part of the command computer which at any given time has the most crucial information has authority over the mode of operation. First simulation of a command computer, S-RETIC Like retic, S-RETIC resembles a stack of poker chips, but each chip is now a computer module, M i , and represents many retic cells (see Figure 17). Together the modules of S-RETIC decide on a mode of behavior in response to data from an overall environment that is static while each decision is beLl1g made. Note the word "overall". A major part of the environment of retic is the cerebral cortex where are stored the plans and goals of the animal. Although S-RETIC has only 42 binary input lines and chooses among only four modes of behavior, it demonstrates principles that can be applied on a much larger scale for a robot. The 42 input lines, Ai, are connected from sensory subsystems, Si, to modules, M i , in several-to-several, but not all-to-all fashion. The outer box in Figure 17 represents a generator to simulate an environment formed in response to the input, 1;. At tpjs stage of design, all (j i and 'Y i lines carry binary signals. All of the other lines into and out of modules carry numerical estimates of probabilities. Each of the 12 logic modules computes from its input information the probability that each mode of behavior is best for the robot. After this initial guess, the modules communicate their decisions to each other over the low capacity ascending and descending lines, Then each module combines this information in a nonlinear fashion with new information coming into it to arrive at adjusted probabilities that each of the four modes is best for the robot. The module, in tum, conununicates this adjusted guess to the modules to which it is connected above and below. The process repeats until six or more modules find one mode of behavior best for the robot with a probability greater than 0.5. This threshold is sensed by threshold units T in remote motor controls. Each try at consensus, or convergence, is called a cycle of operation. Fot" details see Appendix B. S-RETIC is a computer program operated now as part of the larger program described below. It always converges to the desired mode of behavior in less then 25 cycles, but 30 are allowed for it in a larger time period called an "epoch" with the new model described below. Second simulation of a command computer, STC-RETIC In the second simulation of' a command computer, the already-operating S-RETIC was exp~:mded to provide interconnections between the a-parts of the modules (w lines), short- and long-term memories (STM and LTM) in each a-part and channels through which the experimenter can reinforce each module. In addition, the number of 'Y lines to each module was increased to seven; the (j lines were increased to 13, and the lnode of behavior of the robot (RM) was fed back to each a-part. The new model is called STC=RETIC 'where S and T stand for a spatially and temporally changing environment, C for conditioning and habituation. "Vhere each module of S-RET! C has a transformation network to form its initial guess, each module of STC-RETIC draws its initial guess from its LTM. During this and the ensuing epoch, it computes the effects of reinforcements, given it by the operator, and then adj usts its L TM accordingly. The result is conditioning, habituation and other fon1lS of "plastic behavior". For details see Appendix C. Given there are examples of the Pavlovian conditioning of a robot in a remote environment and the dropping out of this conditioning, called habituation. Development is also presented there as a form of plastic behavior. The next step is to design a computer to be both a refinement of STC-RETIC and a more faithful reflection of the neurology of the core of the reticular formation. H-RETIC as it will be called, where H stands for hardware, will be organized much like the STC;'RETIC with physically separate modules containing adaptive elements for memory. Contact subsystem Design of a sense of touch has progressed to the point of planning a hand and arm to reach out and press lightly against surf aces to the front and side of the robot. Figure 18 shows the tactile hand with a single finger. A grasping hand is also being designed to be carried by a second arm. As shown by Figure 18, the shoulder provides three degrees of freedom: linear extension and rotations in elevation and azimuth. All motions are polar-centric, that is, centered on a common point, so that trl:msformation of coordinates can be as simple as possible. It is planned to map the probings of the fingee in a somatic first-stage computer, similar to the visual first-stage computer described previously. The zaxis of that mapping will be depth rather than luminance. Sudden changes in depth will be detected by lateral inhibition, as they are in animals. 8 Assembly of Computers to Command and Control a Robot 129 6. hunt for prey or fodder 7. explore" (or search) 8. urinate 9. defecate 10. groom 11. mate (or sex) 12. give birth or lay egg 13. mother the young (e.g., suckle, hatch, retrieve) 14. build or locate nest 15. innate forms of behavior unique to the species, such as migrate hibernate gnaw hoard WRI-ST AnnUDE Figure IS-Degrees of freedom of the arm and hand Command of the commander? Since both visual and tactile computation can be commanded to respond to some sizes and shapes more strongly than others, we are led to ask: What commands the command computer of an animal? Dr. McCulloch's answer is revealing: "Nothing. You can persuade or cajole the command computer, but you cannot command it." His statement is supported by his diagram in Figure 2 where the influences upon retic are represented by the many connections to it. "There need to be connections from more than one sense, preferably at least three," he continues. Other influences upon retic are internal, such as the cerebral cortex, where are stored models of the environment, past and present, and future models in the form of goals. These influences may be stronger than external ones. Influences to a model of retic are represented by theSiofFigure 17. Modes, which the retic of a vertebrate animal chooses among, are as follows. 16 1. sleep 2. eat 3. drink 4. fight 5. flee A comparable list for a Mars robot is given in a previous section. We can imagine how a man'.:) retic selects among his possible modes of behavior. Vision consists of both the feed-inward of raw sensory data and the feed-outward of signals to adjust filters to match internally-generated images. Touch, hearing and kinesthesia appear to operate in similar fashion. Sensory inputs, therefore, of the kind represented by the Si of Figure 13, represent information from external and internal sensors and internal computers. Consider the actions of a soldier on sentry duty at an advanced post in enemy country .He is expected to hold his filters to match the stimuli he has been taught to expect from the enemy: the shape of his face , the color of his unifOlm, his manner of fighting, . etc,17 If the soldier hears the snap of a breakmg twig, turns toward the sound, and receives from i~s direction images that match the projections of hIS stored models, he may classify the sound and the sight as "enemy." What the soldier does next depends upon other models stored in his relational compute}·. If circumstances appear to favor combat, the sentry may fight (mode 4). If pircumstances appear overwhelmingly adverse, the'sentry may turn and run (mode 5). Circumstances that cause his command computer to select a mode are the number of the enemy, its armament, etc., as these are recognized by the process of generating projections and comparing these at the filters with incoming images. Thus the enemy can persuade or cajole the soldier's command conputer. Similarly, the Martian environment should be able to persuade or cajole the command computer of a Mars robot, in cooperation with very many fewer relations than are required for a human being, such as a sentry. As far as we know the Mars robot will not have to contend with enemies and, therefore, 130 Spring Joint Computer Conference, 1969 , _.c~_~_ .. ./J"'';;';:':;':' ~ .. , _ ··:-,--------",,;.c~· -- Figure 19-Proposed mobile data-acquiring element for a Mars landing willllot have to fight 01' flee. Nor will it have to enter any of the other modes which an animal has .to enter in order to eat and reproduce. The ten modes suggested in a previous dection are very much reduced versions of the requirements of an animal. Instead of the elaborate mode of behavior to hunt, are the much simpler ones to advance, retreat, and look-and-f'eel. Stages in the development of a robot The system we have just described can be achieved, we believe, by such a process of designing, simUlating, and testing as we have described for the development of the separate computers. A camera-computer chain of the kind described previously can be packaged so as to be mobile. A possible mobile camera-computer chain is shown in Figure 19. To eliminate the need for its own power supply and transmitter to earth, it is connected to a Mars lander by a cable which it pays out from a spool at its center. To permit it to look from side to side without moving, its camera employs a rotating prismatic mirror which reflects the light of the scene through both left and right optical paths, to photocells which transduce luminances to voltages. The voltage amplitudes, when converted to digital words, then enter shift registers, to move past computing elements in the manner described earlier. Vertical scan is attained by turning the drum that holds the camera. In initial experiments, the visual first-stage computer can be at the far end of the cable in the lander. When a light-weight visual first-stage computer has been completed, it can be placed within the mobile datagathering element. The command computer will not be tied in initially, the command being exercised by the earth operator. W hen the command computer has reached the stage of development where it can be tied in, it can be built into a robot that is physically separate from the lander, in a configuration such as that shown in Figure 20. This design shows, for test purposes, a stereo television camera mounted in gimbals on a commercially-available tractor. The gimbal mounting of the camera permits it to look forward, sideward, up, down and backward. Besides the camera is the arm described in an earlier section. The rubber tires would be replaced for lVlars travel by wire-mesh tires. Comparison tt'ith other robot projects Perhaps because it is directed toward development of the properties of the computers described in an earlier section, ours is the o~ly robot proj ect with a binocular TV camera as input, a visual second-stage computer to employ thi'1:l binocular input for precision computation of range) and a command computer to receive Assembly of Computers to Command and Control a Robot 131 attention to psychology, while other projects assign reverse priority. We make an exhaustive search of the literature on each animal "computer" we investigate and attempt to create, within the constraints of technology, a working model of the "computer". Examples of such literature searches are given in References 28, 4 and 16. Once we have achieved a working model we proceed to improve it and in doing so may excel nature. 'll e are now reducing the appearance of a scene to stereograms that are much better than Figure 6, which had resulted from out attempt to model animal vision. CONCLUSION Figure 20--Proposed experimental robot simultaneous inputs from several senses and decide what class of thing the robot should do. However, the visual computers and the command computer are still operating separately While in other robot projects assemblies of computers and external equipment are already operating together. Eyecomputer-arm-hand systems are in operation at Project MAC," M.LT.ls and the Department of Computer Science at Stanford University.I9 A computerarm-hand system is in operation at the Department of Mechanical Engineering, M.I.T.20 An eye-computervehicle system is in operation at Stanford Research Institute (SRI).21 Out of the efforts of the projects have come list processing langugaes 22 23 which we may use in simulating a relational computer. Other contributions are speech recognition,19 the kinematics of manipulators under computer control,24 the mapping of the space in which a manipulator operat es 25 and recognition of visual contiguity.26 Since we are all engaged in processing increasingly large volumes of data, reward goes to the one who discovers a method of extracting useful data. At Project MAC and Stanford the reward can take the form of a doctor's degree; at SRI and our project, which are more eq'.lipment oriented, the reward is to have either the equipment or a simulation of it work. This reward is also present at the two universities; and SRI and we also d<;> theoretical work. Aside from the amount of equipment in operation, the greatest difference between our project and the other three is in the way we use the life sciences. All of us use this information since we are all trying to make computers and other hardware do what until now, only animals have done. However, we give primary attentidn to anatomy and physiology, secondary To some, the work reported here will appear to be slavish imitation of the vertebrate" nervous system. It appears to us, on the other hand, to be good engineering practice. When something does what you want it to do and is already miniaturized; why not copy it? The copy is made only in principle. Visual computers are time-shared elements, past which data is moved by shift registers. The modules form larger portions of the command computer than do cells in retic. In fact, the modules and the cells are similar only in their mathematics. To quote Dr. McCulloch, "We use the word 'robot' in two ways. The first, and less important, is as a machine that performs isolated functions of a human being. The second, and more' important, is as a description of life applicable to either living things or machines. Such a description is indifferent to whether the system is man-made or grown, whether it is built of hardware or living cells. This is a central theme of cybernetics: to use the same logic and mathematics to describe men and machines. Norbert Wiener looked at control this way. We are looking at both command and control. Thus, in the more important sense, a robot is a prescription for a system that until recently could be achieved only by the growth of living cells but is becoming something we can manufacture." ACKNOWLEDGMENT Because the physiological concepts presented here came from Warren McCulloch it would have been correct to list him as an author, but in doing so we could not have identified his contributions. One who helped us describe these contributions was Dr. Jerome Y. Lettvin. The simulation of the visual fum-stage computer is the work of James Bever who began it, John Hatfield who devised the fonn of 132 Spring Joint Computer Conference, 1969 filter employed in level 5, and Jerome Lerman who devised all of the filters presently employed. The two aimulations of retic were carried out by Jay Blum. REFERENCES 2 :~ 4 5 t) 7 8 9 10 II 12 13 14 C M MICHAUX Handbook of the physical properties of the planet Mat's NASA 1967 for sale by the Superintendent of Documents U S Government Printing Office Washington D C 20402 SPACE SCIENCE BOARD OF THE ;\IATIONAL ACADEMY OF SCIENCES Planetary exploration 1968-1975 2101 Constitution Avenue X \V Washington D C 20418 L L SUTRO Information proces.~ing and data compression for exohiology missions R-545 Instnlmentation Laboratory MIT Cambridge Massachusett~ ] 966 R MORENO-DIAZ A.n analytical model of the group 2 ganglioi/, cell ill the frog'.,: retina Report. E-I858 Instnlmentation Lahorat.()r~· MIT Cambridge MasRacuhsett~ 196fl W S Mc CULLOCH Embodiments of mind MIT Press Cambridge Massachusetts 1965 D DENNY -BROWN The cerebral control of movement Chapter VI Charlel'l Thoma..;; Pllhlisher~ 1965 R H SELZER The u~e of computers to improve biomedical image quality Proc F J C C 1968 G VON BEKESY Sensory inhibition Princeton University Press Princeton )Iew Jerl'ey 1967 F RATLIFF Mach bands: quantitative .<;tudie8 of neural 'netwurks 1:1/ the retina Holden-l)a~r Inc S3n }"f:!TIcisco ! 965 L L SUTRO C D SIGWART J D LEAVITT D G TWEED Instrumentation of camera-cornputer chains Report. R-636 Inst.rumentation Laborat.ory MIT Cambridge Massachusetts 1969 R GREGORY Eye and hrain World University Lihrary MeGraw-Hill New York 1966 50-60 W M BRODI~Y N LINDGREN Human enhancement be yond the machine age IEEE Spectrum Describing the work of Donald Me Kay February 196889 L L SUTRO Computer synthesis of images with shades and shadows Report E-2250 Instrumentation Lahorat.ory M J T Cambridge Massachusetts 1969 W L KILMER W S Me CULLOCH The reticular formation command and contro,' system Proc Symposium on Information Processing in the Nervous System, State University of New York at Ruffalo OC't.oher Hl68 (in pubieat,ion) 15 W L KILMER W S Mc CULLOCH J BLUM L SUTRO A model of life to select a mode of behavior Report R--635 Instrumentation Laboratory MIT Ca~bridge Massachusetts 1969 (in preparation) 16 W L KILMER W S Mc CULLOCH The biology of the reticu.lar formation Michigan State University Division of Engineering Research Report. East Lansing Michigan (in preparation) 17 J D FRANK The face of the enemy Psychology Today November 1968 25 18 M L MINSKY S A PAPERT Research on intelligent aut01nata status report I I Project MAC MIT Cambridge IV!assachusetts 1967 19 .J Mc CARTHY L D EARNEST D R REDDY P J VICENS .1 computer with hands eyes and ears Proc F J C C 196R 20 W R FERRELJj T B SHERIDAN Snpervi.<;ory control of remote manipulation IEEE Speet.rum Vol 4 No 10 October 1967 ~1-88 21 N J )IILSSON C A ROSEJN R RAPHAEL G FORSEX L CHAITIN S WAHLSTROM .4.pplication of intelligent automata to reconnai.'lsance Stanford Research Inst.itute Menlo Park California 196R 22 E C BERKELEY D G BOBROW editor,;; The programming language LISP Information International 200 Sixt,h St,reet Cambridge Massachusettts 1967 23 L G ROBERTS }Ifachine perception of th1'ee-dirnen~i()nal solids Optical and electro-optical information processing MIT Press 1965 24 D L PIEPER The kin,emalics of manipulators u.nder computer control Computer Science Department Stanford University Palo Alto California 1968 25 D E WHITNEY State space models of remote manipulation tasks Engineering Projects Laboratory Department of l\IechanicaI Engineering ~! I T Cambridge !\1ass~chusett~ 1968 26 A GUZMAN So'me Mpects of pattern recognition by computer MAC-TR.-37 Project MAC MIT Cambridge MassachuseUs 1967 27 ILLUMINATING E~GINEERING SOCIETY lE8 lighting ha,ndbook fourth edition 345 E 47th Street New York 1966 2--6 28 L SUTRO editor Advanced Sensor and Control System Studies 1964 to September 1,96.5 Report R-519 Instrumentation Laborat.ory MIT Cambridge Massachusetts 1966 APPE~DIX A Scaling As indiC'R.ted earlier; 9.pplication of a filter such aH Assembly of Computers to Command and Control a Robot G 2 ,vill produce matrices of luminances that are "on scale", except when applied to spots and edges of maximum contrast. By "on scale" we mean on the scale of 0 to 63 that our digital-to-analog converter can convert and our scope can display. vVhen filter G 1 X 1/8 is convolved with all of the submatrices of luminance -in a typical scene and a histogram plotted of the convolution sums, the result is Figure 21. The extremes are formed when the center of the submatrix of luminances is 63 and the surround is zero, or vice versa. By lopping off extremely high and low values of the convolution sum, as shown by cross hatching, the scale is contracted. Added to the central luminance of the submatrix in question, the convolution sum enhances contrast. In the rare case where this addition forms a negative sum, this sum is repJaced by zero. Filter G 1 X 1/8 is used in this example, rather than filter G 2, to demonstrate a symmetrical histogram. The 2 in the center of filter G 2 leads to the unsymmetry. 133 Inputs (stimulus) Layer of interacting model cell units Outputs (impulses), Figure 22-Schema of the receptive layer and interacting layer, with arrowheads indicating the direction of conduction of impulses in an animal, amplitude of signals in a robot Filters to enhance contrast Luminance contrast is defined27 as (AI) Where Ll and L2 are the luminances of the background and object, respectively. Such contrast is detennined in animals and machines, not by a simple subtraction and division as here, but by the convolution of a filter with the luminances in the image. In previous sections we considered the application of a minimum-area filter to an image. Here we consider filters of any size that may be useful. If each filter, in a matrix of filters, has a sensitive central excitatory re~ioll surrounded by a less sensitive inhibitory region, possibly surrounded in turn by a still less- -63 -31 o 31 sensitive excitatory region, the matrix may be represented by the schema of Figure 22.9 The pattern of response is here detennined by the net effects produced by overlapping, and possibly opposed, excitatory and inhibitory influences. This interaction of influences may be expressed by a set of simultaneom; equations, one for each filter. Implied in the diagram of Figure 22 is 'n-iutual inhibition which can be represented by Figure 23 if the recurrent lines are headed by circles, instead of arrows, to represent inhibition. The effect of recurrent inhibition can be achieved either by such connections, by the non-recurrent filter shown in section in Figure 24, or by two applications of the 7 X 7 filter shown in Figure 24. Jerome Lerman devised this 7 X 7 filter which, when convolved with itself, 63 AJ NON-RECURRENT Figure 21-Histogram of convolution sums formed by filter G1 ,,-ith all of the sub-matrices of luminance in a typi('al seene Figure 2;~-Interaction 8) RECURRENT of cells A and 11 Spring Joint Computer Conference, 1969 134 n excitatory and inhibitory effects in Figure 24 is to continue the spatial filtering outward from the center of influence. While this filter passes higher spatial frequencies and rejects low, the frequencies to wr.ich the vidicon responds are not very high, so it might be called a "middle-pass filter." Trf~DESIRED . \ ACTUAL I I I a Filters to form a line drawing I \ I \ -2 -1 To select points of high contrast that outline objects and details, the second-stage visual computer needs to take differences~ not only to detemline contrast as in formula AI, but to determine if this contrast exceeds a threshold. Consider how these differences can be taken in scanning across the five bands of luminance, in Figure 25. The contrast across the area is represented by -2 -1 IA - I \ -I .~ 13 RESOLUTION ELEMENTS -1 -1 -I -1 -1 -2 -2 -2 -1 -2 -1 -2 -1 -2 -1 -z , , , , .. , -z , , , -z -1 -2 -2 -2 -z -2 -1 -1 -1 -1 -1 -1 -1 -1 l b fZ , -1' -1 * -1 -1 Z 3 • 5 6 7 6 5 • 3 'IIW1I22M22JaW1O ; 10 • W 2 .. -W -6 -, -6 -W Z 6 z11 DI where Av is the average of t.he five lumiAv nances. The threshold, for reasons explained below, is best expressed as the reciprocal of the inner difference B-C multiplied by a constant. Employing these differences, Jerome Lerman devised the following criterion which the computer applies first in the horizontal direction, then in the vertical. T-I! -6 , 10 3 .. -151 -1M -M -lt2 -M -194 -151 -6 ]A • 5 11 -W -1M -310 -212 -l5C -212 -310 -194 -W Ja 5 !A-D! 6 22 .. -M -212 116 ... 116 -212 -198 -6 22 6 Av 7 M -2 -lt2 -l5C ... C472 ... -154 -w.! -Z M 7 , 22 -6 -191 -212 116... 116 -212 -191 -6 22 6 5 11 -W -1M -310 -212 -154 -212 -310 -194 -U 11 5 • U .. -151 -1M -M -w.! -191 -194 -151 -6 U • l: 10 2 , 10 2 3 -6 -W U • . , -2 ]I 22 M 5 7 .. -iA ~ , U 22 11 5 • .I. ... , Z If IA-Dj Av iJ Figure 24-(a) Dashed line, graph of cross-section of desired filt.er; solid line, graph of cross-section of approximation shown in (b) _ (b) Weights of the filter employed in enhancing the contrast of Figure 5 produces the 13 X 13 filter below it. If each 7 X 7 filter sununed to zero, the center would be 8. By summ.ing to 56 the filter enhances existing contrast. The 13 X 13 filter also sums to 56. The computer of Figure 7 applies the smaller filter twice since its core memory will hold only seven lines at a time of a digitized image, 2.56 positions wide with 6 bits per position. The purpose of the diminishing waves of alternately (A2) a dot is placed in the line drawing. W 10 3 K -IB -ci > 0, K -IB -cl ~O, (A3) no dot. Figure 26 develops the reason for using the reciprocal of the inner difference, times a constant, as thp threshold. Curve a is a ramp of luminance. Curve b is its derivative when Llx is the narrow span represented by the distance between 1 and -1 at the upper right of curve b. Curve e is the derivat.ive of eurve b when .6.x is larger. To reduce curve a to a dot, it is evident that the threshold needs to be lowest when the derivative is both as great as possible and as peaked as possible. By plotting the reciprocal as in curve d, the peak does not go to infinity, as it could, and remains manageable. The threshold is a fixed fraction k of this reciprocal. Assembly of Computers to Command and Control a Robot 135 APPENDIXB Operation of S-RETIe B A c D Figure 25-Four bands, each of approximately uniform luminance, about a band of luminance not lettered (a) L ~~~----+---------------------. (b) 6L 7lX x 10-1 FOR SMALL 6x x (C) 6L 6x 1000-1 Each set of lines Pi in Figure 17 (only P7 is marked) indicates the ith module's degree of preference for each of the four possible modes. Thus Pi is a probability vector. The ascending and descending lines out of M i are branches of Pi which connect to other modules. As shown in Figure 27, each module has two parts. Each a-part computes from the module's input information the initial guess as to what mode of behavior is best for the robot. The b-part computes an adjusted guess from information received from above, below and from the a-part. The a-part which has five binary input variables and four probabilistic variables, is a nonlinear transfomlation network. The b-part receives 4-component probability vectors po from above, pa from below and p' from the a-part. The components of each vector are the relative probabilities of each of the four possible modes of behavior. The jth component of each pa, po or p probability vector is the probability, computed by the module of origin, that the command computer's present 'Y input signal configuration calls for mode j. The b-part abo receives a measure of the cycle-tocycle difference between 'Y inputs, called "'Y difference" in Figure 27, and a measure, Q, of the strength of convergence on the last mode commanded (shown being formed in the lower right corner of Figure 17). Consensus among the modules is achieved, aR illustrated in Figure 17, by first detemlining in the step function (s), if the jth component of the probabi1ity vector P from each module exceeds 0.5. If it does, a 1 is passed on to the threshold element T j. There, if 50 percent or more of the jth component input connections are 1'8, mode j is commanded. FOR LARGE 6x x (d) 6x 6L r it ---f---+H+IINPUTS ';2 --+---'+++1FROII 'il~_~+1- If_r" ~ r,. ___ FOR SMALL 6x L....-_ _ _J..-_ _ _ _ ---4~ _ _,,",- ,<--_~ X ~ ~.I Figure 26-Explanation of use of reciprocal of inner difference, times a constant, as the threshold in determining whether a dot shall be placed in line drawing. See text. fo r description of steps co.tfCTf0N5 TO lOWf. *llU.ES Figure 27-Input and output connections to parts a and b of a module in S-RETIC 136 Spring Joint Computer Conference, 1969 Note that each element T j in Figure 17 receives 10 inputs, a1though for -1larity in the drawing, connections are shown only to T 3. The threshold elements T are part of the executive computer pictured in Figure 2. Each T receives many inputs, decodes them and executes a mode of behavior. S-RETIC is described in more detail in Reference 15. APPENDIXC Operation of STC-RETIC General Figure 28 diag~ams the a-part of a module in STC-RETIC. Signals from the senses (w's); from modules above and below ('Y's), from the threshold units that determine the mode (R~I) and from the experimenter (RPC and RAC's) enter the short term memory where they are held for two input epochs. STC-RETIC converges on a mode in the same sequence described above for S-RETIC, except that each initial guess is read from a long tenn memory instead of being generated by a transformation network. Each initial gtiess is read out as a probability vector to be used in the same way as p'i in S-RETIC (Figure 27). In the conditioning .process, the information as to module inpuLs, module p', the converged-upon mode and whether it was good or bad, is used to modify the probabilities stored in long term memory. In either conditioning STC-RETIC, allowing it to habituate or in other ways encouraging it to acquire temporally influenced patterns of behavior, the operator of STC-RETIC not only provides the external conditions (~, Fig. 17) to which it will respond, but he takes the place of the parts of a robot that would indicate that the input and response conditions are punishing, neutral, or rewarding. He introduces a negative reinforcement prior to convergence (RPC) to indicate that the external conditions are themselves punishing, and a zero HPC to indicate that they are neutral. Finally he introduces four other numbers (HAC's) to indicate the reinforcement effect on STC-RETIC of its selection of each of its modes of behavior. An RA(\ is a "reinforcement to' be applied after convergence if STC-RETIC converges to mode i." It is used in conjunction with shortterm-memory informatjon in the module to specify the corresponding modification to the module's long term mem~ry. A negative value of RA(\:, called "punishing," IS interpreted by STC-RETIC as evidence for not converging on mode i the next time the same 'Y's and w's are received. A positive value. called" rewarding," is interpreted oppositely. Examples of Pavlovian conditioning and habituation in the robot pi Figure 28-The a-part of a .module in STC-RETIC i Pavlo\~ian COIlditioning is made possible both bjr responses "wired into" the long-term memory of each module of STe-H.ETle, and by 'Y's and w's acquired during two epochs by the module's shortterm memory. For example, let us suppose that a "wired-in" (unconditioned) response is (1) to command l·etre.at. when t.he robot feels a horizontal edge with nothing beyond it (a precipice ?), then (2) to be rewarded (positive RAC) for saving the robot. Let us suppose further that each time the robot feels an edge, beyond which it feels nothing, it also sees an edge, beyond which it sees nothing. The more often the robot both feels and sees an edge, beyond which it feels nothing, and then is rewarded for retreating, the more firmly it becomes' conditioned to back up at the sight, instead of just the feel, of such an edge. In STC-RETIC such conditioning is stored in t.he long-term memory of each module, which contains Assembly of Computers to Command and Control a Robot a reduced record of the conditions under which it has made decisions. An example of habituation in a robot is the following. Suppose a robot travels over the surface of iViars and comes upon territory that is sharply striped in light and dark. vVhen it ceases to behave as though each stripe were a precipice, it will have become habituated to the striped terrain. After a time, the duration of which was pre-specified, it. will spontaneously recover the original response so that, if it then moves into territory where such stripes are shadows marking true hazards, it will not be harmed. What have changed in both of these examples are the long-term memories of modules. Forms of robot behavior due to development As explained above, the initial guess of the a-part 137 of each module is made by consulting its long term memory. If there is no entry for the given values of 'Y and w, then a flat probability vector (all four components equal) is read out. Changes in a long term memory, which starts from flat probability vectors, are what we mean by development. STC-HETIC has room in the long term memory of each module for 100 vectors, some of which are fiat, others are preprogrammed to non-fiat values. Some of the kind of development that is complete in the retic of a mammal at birth may be best achieved by STC-RETIC through experience in its environment. Other forms of plastic behavior modeled by STCRETIC are: generalizatjon of and discrimination among the conditions under which a mode response is given, avoidance conditioning and extinction of Pavlovian conditioning. =::no~i~ _!lnrl .... t;l;~g ...;n~ n.r .ron .... l ...... nl--:,---- - - ..... "' .......... .. T LJ~"' '-'.I..I. u ........ «U.l.L] universal tree circuits by GIACOMO CIOFFI Fondazione U. Bordoni Rome, Italy and EUGENIO FIORILLO I.B.M. Itaiia Milano, Italy INTRODUCTION Cellular tree circuits In the last few years the progress of integration techniques of more and more (;omplex digital circuits has led to the development of a new branch of the switching theory known as cellular logic. 1 Nevertheless the integration of cellular circuits of a certain degree of complexity is hampered at present by poor yield, that is by the likelihood that one or more cells of the circuit may turn out to be faulty. It is useful, therefore, to try to use these circuits even when there are some faulty cells. Generally speaking there are two possibilities: A cellular tree circuit with n levels, An, is a circuit having the structure shown in Figure 1, and can implement any function of the n variables Xl, ... , x n • The circuit is made up of 2n -1 cells, all equal (Figure 2), which implement the function (a) to provide a certain degree of redundancy in the circuit, so as to be able to replace the faulty cells with spare cells;2 (b) to use, if possible, only the part of the circuit functioning correctly. with X = The second way seems easier to carry out, since it does not require interventions on the circuit already realized. Apart from the choice of either way, it is necessary above all to carry out the diagnosis of the circuit in order to determine what failures have taken place. In the present paper these problems are studied in the case of universal cellular tree circuits. 3 ,4 In the first part . a minimal set of diagnostic tests is derived; in the second part a criterion is set forth which, on the basis of the results of the tests carried out, makes it possible to find some functions that can be realized by the faulty circuit. i-I Cji = C2j - Xi + Ci-I 2j+l Xi • The 211 inputs (Xl, ... , Xn) * will be indicated briefly n L x2 i i - 1• The binary inputs co, ... , C2"-1 i=l are for the specialization of the circuit; to be exact each of the 2(2 n ) vectors C == (co, ... , C2"-1) corresponds to one and only one function F(X1, ... , Xn). It is easy to show 3 that, if vector X is applied to An, the output c~ coincides with the specialization bit Cx; therefore there exists a one-to-one correspondence between the minterm mj and the bit Cj (0 ~ j ~ 2n-1). A function F(xt, ... , xn) is implemented on An giving the specialization bits corresponding to the minterms implicating the function values equal to 1 and leaving the rest at O. Tests to detect fauUs in an An In view of the regularity and the simplicity of the (*) 139 Xi = 0 or 1 140 Spring Joint Computer Conference, 1969 Table 1 x Co C C 1 2 C c 3 ... ~----~-;--------~--T-- 0 ,c • •------------------- Zn-~I_L---.--q-t-----t-.,~----t-. --t-~---+-+t• z,, _ _ _ .e; "n ") 0 1 1 2 1 0 1 1 1 1 ") .) 1 1 1 0 1 2n_1 -" 1 1 1 1 1 1 0 c 1 1 ., I 1 .................................. )n_2 1 1 1 1 0 1 12n-1 1 1 1 1 0 .. - F(z, •..• z,,) Figure l-..'3tructure of the universai ceBulaI' circuit (t.e.) Figure 2-j-th cell on level i of the t.e. interconnections, only faults within the cells are considered possible; this implies that, even when there are faults, the output of each cell always remains a function (possibly degenerate) of its three inputs exclusively. To remain on a more general plane, it will be supposed that a faulty cell can implement any of the remaining 255 functions of three variables. This section describes a complete and minimal method of detecting faults in a tree circuit; that is, it detects all faults satisfying the above mentioned hypotheses and consists in the minimal number of tests. complementing all the specialization bits. They give two sequences each of 2n ones at the output of a correct t.c. Let us consider the set of tests 0 j, 1 j, 0 t, 1 t applied to a correctly functioning t.c. The signals at every point of the circuit are shown in Table 2. I t can be seen- that the four tests for the whole tree correspond to the same tests carried out on the subtrees and on the individual cells according to Table 3. Let us take as an example a tree made up of only two levels (Figure 3). The tests are those shown in Table 4, in which it is supposed that the circuit functions correctly. I t is then possible to constru.ct Karnaugh's map of the function implemented by each cell (Figure 4); for the sake of clarity the maps have been arranged in the same way as the respective cells. This result can be easily extended to the case of an n-level tree. On each level the squares of the maps are Table 2 1 1 2 2 2 cOc,c2c)""c2D_2C2D_, c o c""c 2D -'_1 COC''',C 2D-2_ o 0 0 0 0 ... 0 0000 ... 0 1 0 0 0 0 ... 0 00 ... 0 0 0 ... 0 0" ... 0 ~. D-' D-' 1 ... Co c, Co p ... 0 ... 0 0 0 0 0 0·0·0·0·:::·0.. ·0 .... 0·0·:::·0.. ·.. ·0·0·:::·0...... ::: 0'"0''' '0" ~:'i I I .;o..II~. ~. ~. ~.:::. ~ ... ~ ....l"'" ~. ~.:::. ~ ...... ~. ~.:::. ~ ...... ::: ~ ... ~ ... ~. ~ .. I' Description of the tests The test in which all terminals Co, •.• , C2n-l are fixed at 0 and the inputs take on all possible values X o, ••• , X 271 - 1 is called here "fixed 0 test" (0 / ), If the tree circuit (t.c.) functions correctly, during the fixed otest there is a sequence of 2n zeroes in the output. The test described in Table 1 is called here "travelling o test" (Ot). If the t.c. functions correctly, during this test there is a sequence of 2n zeroes in the output. The tests here called "fixed 1" and "travelling I" (1 I and 1 t) are obtained from the OJ and 0 t tests by 1 X 2 -'j 1 , 1 ... 1 1 1 1 1 ... 1 '" 1 1 1 1 1 , 1 ... 1 1 1 ... , 1 1 ••• 1 ... 1 1 ,1 ! I'! ~ 1~ ::: ~ ~ ~ L:: ~ 'I I' 3 , 1 1 1 0 ... 1 ·d··j........ · ........ 1 1 1 ••• 1 1 0 i 0 !1 0 -"l 1 o 10 ... 1 oo . . . 1 0 '001100 ... 0 0 0 0 2 0 ... I' g~ ::: ~ 01 ... 1 \' ::: Ig ~ ... 0 1 II ~ I' 0 i······ .... " .. 'j" " 1 ' " ' ' ' ' +.... ; ill ... 0 ...• •• j'1 00 1 0 1 1 '" 0 ! 1 0 ... 0 ... 1' 0 !1 ! 1 ~ .............. 11 0 0 0 ... 0 2D-~i 1 1 1 1 ... 0 2 1 I' 1 1 ... 0 1 1 ••• 0 ... 0 1 0 ... 01 ... 00 I' I) '1 0 ... 10 ... 00 "'1" 0 0 .. '10 ... \I 1 1 ... 1 ' 11 I' ~ ... ~.~.~.~.:::.~... ~ ..... ~.~.:::.~ ...... ~.~.:::.~ ...... ::: ~ ... ~ ..... ~ .. I 2 -2 0 0 0 ., : •• 1 2D_1 0 0 0 0 ... 0 0 1 i 0 0 ••• 1 I () 0 ... 1 I· 0 0 '" 1 0 \I . . . 1 1 1 I Diagrams and UtiHzation of Faulty Universal Tree Circuits Table 3 , , 1 1 COC1"'C2n-1_2C2n-1 x ° iri':1 OfOf" •• Of i:':, I , ° Of 'r 'r" "r 1r °t'r"'r 'r -, 2 2 Co ···C 2n- 2_, Of"'Or I'r" "r Table 4 ... ... ... °t""r 2 1r Ot ••• 'r 'r 2n -4 2 _3 'r'r···Ot 'r 2n_1 1r 1f" •• 1r °t 3 ~ri" , ° 2 Or n Co 'r 'r °t 'r 'r ' r ' .Ot °t 'r °t Or \"'Or 't Or ....................... ............. .... ~ri':4 ~-3 0r0f""'t Or 2n_1 °r°f"' 'Of \ ~n_2 't Of °f""t \ X2X' c c c c O 1 2 3 0 o0 000 0 1 0 1 o0 0 0 o0 0 0 o0 0 0 o0 2 1 0 3 1 1 0 1 2 o0 3 , o0 o 1 2 1 0 1 1 0 0 1 2 3 .Figure 3-A two level t . c. -,;1 g, (II) 0 0 (IJ f ~) , , f4) (I) £ f OJ) c'o 0 , tI) tuJ 0 0 (8J I , r_J 0 (lIN I (ilJ hJ (f$)

~'
I

o 1
1 0
1 1

3

Xf----~----~----~----~~

1 1
O 1

X
Or

Or

Of

'tOr" 'Or
°r\"'Or

3

n-1 n-'
Co C,

....................... ............. ....

~n_2

141

o0
0 1
1 0
1 1

C C

=

2-F
CO

o0

0

0 0

n
v

o0

0
0

1 1 1 1
1 1 1 1
1 1 1 1
1
1

1
1
1
1

1

1
1
1

1

1

0 1 1
101
1 1 0
1 1 1

0 1
o 1
1 0
1 0

0
0
0

,,

1

1
1
0

1 000
o10 0

001 0
000 1

1
1

1 0

1 0

o
o

0

1
1

1

1

1

1

then for Xl = 1, starting from the map of c~ as far as the
map of ~"-i-l (0, test);
(2) the squares of the third columns, as at point (1)
(I, test);
(3) the upper squares of the fourth columns and then
the lower squares of the second columns, as at point (1)
(0, test);
(4) the upper squares of the second columns and then
the lower squares of the fourth columns, as at point (1)
(It test).
Every cell on level i is tested 2 i-I times. It is useful for
what follows to note the law for the construction of the
map of a cell of level i from the maps of the two cells
above of level i - I (Figure 5).

Properties of the tests
Figure 4-Correspondence between the tests and the entries
of the cell maps

controlled in the following order (the columns are
numbered from left to right):
(1) the squares of the first columns, first for

Xi

= 0,

A tree An can be decomposed into two subtrees having
n - 1 levels, A1I- I and ~-h and in its output cell. For
the sake of simplicity the outputs C~l and C't"l of the
two subtrees An-I and ~-l will be indicated in this
section with a and fJ.

Lemma: If the 0" 1" 0 t, 1 t testf:, carried out on an
A., give correct outputs, outputs a and fJ of subtrees

142

Spring Joint Computer Conference, 1969

Table

i-I

.j

-e2j

.

I
X

A:'~
..I

0, 1

Of:

0, 1

1 :
f

°

at:

A

n

n-1

n-1

~O

bits.

?

Table 6

x

n

AI

A

n-1

Po

0, 1

Of: (Xo

Of:

0, 1

1 : cx,
f

1 : (3,
f

0

at: <:to

f-

- - - - -1

1 : cx
1
f

0

1 : a.
t
1
- - - Of: ~O

f-o--

1

A

n

n-1

'£: (31
f-

-

-

°t:
~

- -

Po

Of: ~O
-- - 1 : ~,
t

II

Of: 0
1f:

at:

1

°1

't: 1

Proof Necessity: it is obvious. Sufficiency:. according
to the Lemma, if the outputs are correct a and (3 axe
. constant in each of the eight half-tests. A Karnaugh map
can therefore be constructed for the function of the
output cell, as shown in Figure 6. The function implemented by this cell is therefore of the following type:
F = a * xn

+ f3* Xn •

(1)

Since the outputs are correct, two possibilities may
occur:

Diagrams and Utilization of Faulty Universal Tree Circuits

a,

a'o

0

0

I

I

I

0

0

I

4
Figure (j-The final cell map

(1) a* = a and!3* = !3: An-I,
are functioning correctly;
(2) a*

= a a/o !3* =

P:

~-I and

the output cell

An - I a/o A~_1 give the

complemented output, but the output cell makes up for
this defect.
In both cases for Xn = 0 {XII = I} the output of An
reproduces that of A n - 1 {A~_I}' apart from complementations. Therefore the maps of C~-l and of C~-l can be
constructed for Xn = 0 and for Xn = 1 respectively. It is
seen at once that also the functions implemented by
these two cells are of type (1), and therefore the
considerations made for c~ are still valid. Proceeding in
the same way, we can construct the maps for all the
cells of the circuit, which always implement functions
of type (1). It can be concluded that circuit An functions
correctly, since it has been proved that all the cells
function correctly, apart from pairs of faults that cancel
each oth~r out and therefore cannot influence the overall
behaviour of the circuit.
Theorem 2: The set of tests 0" 1" Oe, 1 t contains the
minimal number of tests necessary to control the
functioning of a circuit An under the conditions envisaged
for the faults.
Proof: In view of the structure of All and the type
of faults considered, the cells on the first level are all
independent of one another; it is evident, therefore, that
the number of tests necessary to control them is
8.2 11- 1 = 21142. This is obviously a lower limit for the
number of tests referring to the whole circuit. Then, too,
considering the independence of the cells of each level,
the attempt can be made to organize the 2 n+2 tests
necessary to control the cells of the first level so as to
carry out at the same time the tests on all the cells of the
following levels. Theorem 1 shows that this is actually
possible. This is what we set out to prove.

The utilization of fauUy cellular tree circuits

Fault localization
The method set forth in the preceding section also
makes it possible to localize the faulty cells in a way that

143

will be described. As has been seen, tests 0" 1" 0 t, 1 t
make it possible to construct the Karnaugh map for the
ceH at level n, and every square of the map is explored
by 211- 1 tests. At level i a cell c1 is tested 2 i-I times. If
this cell is faulty, exhibiting a mistake in a square
corresponding to Xi = 0 {x i = I}, 2 i-I consecutive
wrong outputs occur starting from element 2k· 2 i-I
{(2k + 1) ·2 i-I} of one of the four sequences.
The same output sequence is obtained if the two cells
c~ and c~tl ar~ faulty in the same way as ct Similarly
it can be seen that 2h cells at level i - h with faults in
the same squares of the maps (and all the combinations
of these faults) lead to the same output sequence.
It can be concluded, therefore, that, if in one or more
tests there exist as many output sequences composed of
2 i-I wrong terms starting from element 2k· 2 i-I or
(2k + 1)·2 i-I, the subtree having ci as its output cell
contains one or more faulty cells. If there exist several
wrong sequences not correlated in the preceding way,
there exist as many faulty subtrees in the circuit.
The data supplied by the four tests do not permit a
more exact localization of the faults. Then, too, it is
easily seen that the number of additional tests necessary
for this purpose can become prohibitive in proportion as
the dimensions of the faulty subtree Ai grow. Furthermore, a minimal set of these tests cannot generally be
fixed in advance independently of the results of the
preceding tests.
A method will be described which makes it possible,
on the contrary, to use a faulty An to implement a subset
of functions of n variables without further diagnostic
tests.

Finding a set of functions that can be
implemented by a faulty t.c.
Let us suppose that the tests 0" 1" Ot, 1 t have
detected a subtree Ai. containing one or more faulty
cells. Cases i = 1 and i > 1 are considered separately.
1st case (i = 1): Tree Ai is reduced to only one cell
of the first level. Since the inputs of this cell are all
accessible from the outside and therefore known, it is
easy to obtain the function implemented by the faulty
cell. Let this function be c} = g(Xl' C2;, C2i+l)' If it is
expanded according to Shannon with respect to Xl, we
get

Terms go and gl can be considered as equivalent
specialization bits and they depend generally on both
the signals applied to the two control terminals of the
cell.
If and only if the correspondence between pairs gog)

144

Spring Joint Computer Conference, 1969

and C2j~j+1 is a permutation, cell c} is still able to
implement all the functions of Xl, and therefore An is
able to implement all the functions of n variables. In all
other cases the functions of Xl that can be implemented
by c} and tberefore the functions of n variables that can
be implemented by An can be found immediately.
Example 1: Let us consider an A3 (Figure 7). The
result of the diagnostic tests is supposed to be the one
shown in Table 7.
In each test one wrong isolated term is noted;
therefore the faults of the circuit are limited to the first
level. Since the wrong terms correspond to X = 2 and
X = 3, it can be deduced (k = 1) thattheyaiicorrespond
to cell c~; the map of the function implemented by this
cell is therefore that shown in Figure 8. The function
impiemented by ci in iorm (2) is therefore

The equivalent specialization bits are:
C!eq

=

C~a

c3eq

=

~C3.

.xyl

f

1

o

0

0

I

I1
i

I0

Figure 8-The map of the faulty cell of example 1

Owing to the correspondence between the specialization bits and the minterms of the functions implemented
by A 3, it can be deduced that all the functions having
one and only one of minterms nl2 and ms can be implemented. To Lrnplement a function with m~ alone the
terminals can be specialized in the usual way; to
implement a function with m3 alone it is necessary, on
the contrary, to fix C2 and C3 both at 1.
2nd case (i > 1): Two types of faults can be distinguished as can be seen from the map of cell c;
which has
(a) one correct row.
(b) errors in both rows.

If------~---+--~--~~~~--+---~--~_+

Z2----------~---+----------~~--~+

F

Figure 7-The t.e, considered in example 1

Table 7

x

Of

1f

°t

't

1

,

0

1

0
0

2

1

0

0
1

,

3

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

0

4
5
6
7

(a) If cell c~ has the map with the row Xi = 0 {Xi = 1}
correct1 it can be said that subtree Ai functions correctly when Xi = 0 {Xi = I} according to the considerations set forth in Theorem 1. The faulty tree can
therefore be decomposed as in Figure 9.
When Xi = 0 {Xi = I} the output c; coincides with
the output of A i - l {~-l}' Then, too, when Xi = 1
{Xi = 0 1 the output of c~ can be known independently
of Xl, ••. , Xi-l if all the specialization bits of ~-l {Ai-I}
are fixed at 0 or at 1. This output coincides with the
value of the lower {upper} square corresponding to test
0, or I, on c).
An An with such faults can implement functions of
the following type

(3)

1

1

0
1
1
1
1

where: X; = Xi {Xi} if the upper {lower} half-map is
'\
correct;
~-i is the vector (X'+l' .," xn) direct or
complemented so that c~ = cj for X!-i = 1.
-yisdefinedinFigure.l0forxi = X;,; for xi = Xi,
'Y is defined in a similar way, taking into
account the lower half-map; 0';'-1 is the
value common to the 2 i-I specialization
bits of ~-l fAi-I} ;

Diagrams and Utilization of Faulty Universal Tree Circuits

145

Table 8

X,

--------~----_+--------~~~_+----~

x.L- -(--------~~------------~~----_+

They are therefore programmed on their
subtrees specializing the bits in the usual
way.

Xjq-l)

0
0
0

1

3

0

4
5
6

0
0
0
0
0
0
0

0
0
0
0
1
1
1

14

1

15

0

1

0

13

0

1
1
1

1
1
1
1
1

1
0
0
1
1

1

1
1
0
0
1
1
1
1

(4)
r

+ II L
q=l

hq~iq

X!~ ghq(Xl, ... , Xiq) .

In fact, owing to the structure of the tree, the first
terms of Equation 3 written for' the individual faults
can be implemented independently. The second terms
of Equation 3 must be intersected with one another so
as to obtain the residual part of An which does not
belong to any of the faulty subtrees.
Example 2: Given an At, it is supposed that the result
of the tests is as shown in Table 8.
There is a sequence 0000 in column 1 t for X = 0,
1, 2, 3; this implies the presence of a fault in a subtree
As (2 i - 1 = 22), which has cg as its output cell (k = 0).
Similarly, the two sequences 00 in tests 1 f and 1 t
corresponding to X = 10, 11 imply the presence of a

~
ITIIJ

0
1
2

12

+ x~ 'rq] +

q-l

1t

10
11

If there are r subtrees ~1' • • • , ~r which show faults
of this type, the proceeding is similar. The circuit can
implement functions of the type:
~q-iq [x;q fq(x!, ... ,

°t

7
8
9

f and g are any functions of their arguments.

r

1f

0
0
0

Figure 9-Deeomposition of a fault.y tree Ai

L

Of

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

x·----------------~~--_+------------~
t,

F(X) =

x

fault in an A2 with c~ as its output cell. The maps
corresponding to cg and c~ are shown in FigUre 11. Both
have one correct row. Applying Equation 4 we obtain:
F(X) = ~ xSf1(Xl, X2)

+ xSO"s + J4Xs x2f2(xl) + X2'0 +

+ J4gl (Xl, X2, Xs) XS~~,1 (Xl, X2) +
+ XaX~'2(Xl, X2) + XsJ4g2.S(XI, X2) =
= X~fl(XI' X2) + XaX40"S + X2 XsJ4f2(xl) +
+ XsJ4f(XI, Xli) .
In the last term f(Xl, X2) has been used instead of
gl(XI, X2, 1) g2,S(XI, X2) since this product is any function
of Xl and X2 .

.c R

.c'
4

()

y=O

r1INIJ )' = "i-I
ITIIJ

~
--;2

.l31 0 0

I

I

-sf

~,
0 0 0 0
.cs

I

[Q[]TI]

ITIIJ

Y ="i-I

[I[JZ[J

ITIIJ

y=

f

,c3
0

Figure 10-Definition of the function

'Y

2

.c2

Figure II-The maps of the faulty... cells of\, example 2

146

Spring Joint Computer Conference, 1969

Table 9

(b) If the map of c) does not have a correct row,
let us consider the functioning of Ai in tests 0 f and 1 f·
Since every square of the map of c; is explored 2 i-I
times co~esp~nding to all the values assumed by
Xl, ... , Xi-I, the output of Ai in these tests is a function
of Xi alone or is constant, according as to whether the
columns of the map of c; corresponding to tests 0 f and
If are 01, 10 or 00, 11. Therefore A1'I can implement
functions of the type:
F(X) = ~-i [CTiC;(Xi)1

I

hq ,c3 q

+

usXa)

1

1

0
0
0
0
0
0
0

1I

0

1
1

m
I

I

,. 0

.c f2

+

XsX4(U2X2

+

CT2'0)

If

0

0
0

0
0

It

0
0
0

1
1
1
1

,

1

1

0
0
0
0

1

0

1

1

1

+

+ [~gl(XI, X:;, xs)]· [XsX4g2,I(XI, X2) +
+ XaX~,2(XI' X2) + X~g2,3(Xl, X2)]
= xsX4 + CT2X2X~ + x~f(xI' X2) .
The number of the functions that can be implemented by a faulty circuit according to Equations 4
and 6 can be considerably increased if we admit the
possibility of permutating the variables XI, ... , X1'I on
the n inputs. To be exact, the number of functions
that can be implemented should be multiplied by n!.
In the case of Example 2, for instance, the fUIlctions

.c03

I
!

1

1
1

.c'
4

"

.%"61
Xiq) •

Example 3: Let the results of the tests carried out
on an A4 be those shown in Table 9. The presence of two
faulty subtrees with output cells c~ and c; can be noted.
Their respective maps are shown in Figure 12.
If we apply Equation 6, we get:
F(X) = ~(CTsXa

1

f

,cZ

r

q=l

0
0
0
0

13
14
15

+ uiq c;:(Xiq)o] +

X!~iq ghq(Xl, .. "

1
1
1

12

(6)

II L

1
1
1

11

q=l

+

1

10

In the case of r subtrees Ail' ... , Ai,. with faults of
this type, we obtain:
[CTiq C;:(Xiq)1

1
1
1
1
0

0
1

7
8
9

where: CT i is the value common to the specialization
bits of Ai;
C)(Xi)1 and C;(Xi)O are the functions implemented
by cell c; during the tests I, and 0 f
respectively;
the gh are any fun~tions of Xl, ... , Xi and are
programmed on their subtrees by specializing the bits in the usual way.

q

0

6

h,ci

r

0
0
0
0

4
5

(5)

L' xt:-'i

0

3

+ L X!-i gh(XI, ... , Xi)

F(X) =

u

1
2

+ UiC;(Xi)O] +

ot

x

I21

~
·0 0 0 I

.c'S
,£'2

Figure 12-The maps of the faulty cells of example

2
:~

implemented are 211 = 2048; by permutating the
variables in any way, they become 2 11 ·4! = 49152.
CONCLUSIONS
A diagnostic method for t.c. has been described which
makes it possible to utilize faulty circuits in a simple
way. The diagnostic tests for the circuit are in minimal
number and can easily be carried out automatically, in
view of their independence of the faults and their
uniformity. In the use of faulty t.c. one or more subtrees
containing the faulty cells are isolated and their
specialization bits are all fixed at 0 or at 1. In this way
it is not possible to TInd all the functions that the faulty

Diagrams and Utilization of Faulty Universal Tree Circuits

t.c. is still able to implement. However a large number
of additional tests, which furthermore cannot be
established in advance, would be necessary to determine
the complete set of functions that can be implemented
on a faulty An. Then, too, the law for giving the
specialization terminals their proper values would be
generally somewhat complicated.

REFERENCES
1 R C MINNICK

147

A. survey of microcellular research
Journal of the A C M vol 14 no 2 April 1967 pp 203-241
2 R C MINXICK
Cutpoint cellular logic
IEEE Trans vol EC-13 no 6 Dec 1964 pp 685-698
3 G CIOFFI V F ALZO~E
Ci7'cuiti cellulari con struttura ad albero
Automazione e Strumentazione vol 16 no 8 Aug 1968
pp 338-350
4 S S YAU C K TANG
Universal loy'ic circuiis and iheir modular reaiizatiorl
Proc S J C C 1968

Solid state keyboard
by EVERETT A. VORTHlVIANN
Honeywell, Inc.
Freeport, Illinois

and
JOSEPH T. MAUPIN
Honeywell, Inc.
Plymouth, Minnesota

INTRODUCTION
The computer industry is no doubt one of the most rapidly growing industries today. With the increase in
computer usage, there is an increased demand to improve man's ability to communicate with the computer.
The prime instrument of input communication today
is a keyboard, and it appears that this will be true for
some time in the future.
The requirements of today's keyboards are becoming
more complex. Increased reliability and more flexibility
to meet specialized demands are essential. Remote
terminals are quite often operated by relatively untrained personnel and the keyboard must be capable
of error-free operation for these people. At the same
time it should be capable of high thru-put for the trained
operator as will be used on a key tape machine.
Some of the limitations of existing keyboards are:

bit parallel code is usually used. Two codes currently
used are ASCII and EBCDIC and the keyboard design and construction must be such that any code can
conveniently and economically be supplied. The output
signal must be compatible with the solid state integrated
circuits used in today's computers.

Specific design objectives
At this point, each key may be thought of as a simple
switch, actuated by the position of a key plunger.
Human factors studiesl -4 helped establish the following for mechanical and tactile features of key operation.
Operate force: 2 to 5 ounces
Pretravel (before operate): .075 inches min. from
free position

.l\1echanical interlocks which reduce operator speed.
• Excessive service (increasingly linportant for remote terminals).
• Contact bounce and wear of mechanical switches.
• Non-flexible format.
Our general objective in developing the solid state
keyboard was to overcome these limitations and still
have a competitively priced design.

Keyboard organization
Before setting forth specific design objectives, some
reader's familiarity with this type of equipment. The
purpose of a keyboard is to feed information into a
digital computer by means of a binary code. An eight

Release point: .040 inches min. from free position
Release point (R.P.)

~

Operate point (O.P.) where a = differential

a

Switching transitions should be "snap acting" or regenerative so that it will not be possible to hold a key
in a position that will cause ambiguity at the output.
Rise and fall times must be in the low microsecond
range without any ringing or oscillation. The encoding
electronics must be capable of blocking error codes when
two or more keys are depressed.
Keyboard formats are quite varied, depending on the
user's needs and preferences. This indicated that each
key should be a separate module. Finally, the service
life should be in excess of 10 million operations per key,

149

150

Spring Joint Computer Conference, 1969

and low cost was given a priority second only to reliability.

TRIGGER CIRCUIT

OUTPUT AMP

I I

The approach
From the outset, our thinking was slanted toward the
development of an integrated circuit chip transducer
for the key module. The powerful and still growing
economic advantages of batch processing used in integrated circuit manufacture were considered essential to
our stringent cost objectives. To fully exploit these
advantages, it was desirable that the chip be complete
in itseif i.e., that ii require no external components to
accomplish its function. The latter cannot be added in
batch fashion.
Several approaches to mechanical position detection
without contacts were studied, based mostly on unique
sensor effects available in a semiconductor such as silicon. Position control of an electric, magnetic, acoustic,
or electromagnetic (including optical) field pattern is
fundamentally involved. Hall effect sensing in a silicon
device, inCluding appropriate integrated electronics,
and coupled with permanent magnet actuation, was
singled out for detailed analysis, design and development.
This approach was eventually adopted for the solid
state keyboard. The competing approaches mentioned
above, though quite feasible, seemed to require more
expensive packaging, or more expensive and less reliable field sources, or were known to require external
components in the electronics. :Vlagnetic actuation
looked particularly attractive because it appeared that
the sensor device could be integrated on the silicon chip
along with associated electronics as well as allowing
more freedom in package selection. Among the several
galvanomagnetic effects present in semiconductors, we
found that only the Hall effect in silicon is large enough
to be useful in the low field « 1000 Gauss) region of
interest.
The' silicon chip that has been developed is described
by the functional breakdown in Figure 1.
A circuit schematic is given in Figure 2, and a picture
of the chip comprises Figure 3.
Some of the analytical and experimental investigations associated with this development are presented
in what follows.

TRIGGER

HALL
GENERATOR

+

~

CIRC.UIl

AMPLIFIER

Figure I--Functional description of silicon chip transducer

o

Figure 2-Circuit schematic of chip transducer

Figure 3-Photograph of chip

H all effect characterization
is old in scientific terms, having been discovered by
Edward W. Hall in 1878. It is currently enjoying a.
renaissance of practical applications interest due mainly
to advances in semiconductor technology. Two publications6 •6 by A. C. Beer provide excellent general references. The Hall effect results directly from the Lorentz
force on moving charge carriers; where the average
motion is constrained in direction, as in a solid. This is
illustrated in Figure 4. The Lorentz force creates a
charge unbalance in the y-direction. The resulting

Solid State Keyboard

151

(2)

VH= EyV
:RHIB

V = supply voltage
8

8

10 t

Where RH=HIII

Coefficient ::
~-IB

I

T Fy

Vx _

.

zJ--x' ···~ ···

Ey ~ I
- -JJ( Bz nqc

+

A factor less than unity has to be applied to equation

F=q(E+(t)vxB)
Figure 4-Hall effect illustration

electric field, called the Hall field, provides a force that
cancels the Lorentz force. Integration of the Hall field
between a pair of probe contacts on the sides of the
conductor produces the Hall voltage.
Equation 1 shows an approximate Hall voltage expression for a homogeneous layer with predominately
one type of carrier concentration.

H

-

RH IB
108 t

(1)

RH

= Hall* coefficient ~_ J:..

n

= concentration (cm- 3)

nq

I, B, V H = mutually perpendicular
t

= Thickness (cm)

B

= Gauss

VH

volts

I

amperes

q

W = width

2 if the aspect ratio W /L is not smaller than unity.

THE HALL EFFECT IN A SOLID IS A DIRECT MANIFESTATION OF THE
LORENTZ FORCE ON MOVING CHARGE CARRIERS:

v _

= mobility (cm2jv-sec)

L = length

1

=-1. (v +B )

Ud

= charge on an electron

Since most electronic circuits operate from a constant
voltage supply, equation 2 below is more appropriate,
It is straight-forward derivation * from equation 1 for a
rectangular geometry.

* \Ve assume "Hall mobility" and "conductivity mobility" to be
substantially equal for the conditions of interest. The validity of
this assumption, has been confirmed through private communication with Dr. G. D. Long. Honeywell Corporate Research
Center.

This is due to the shorting effects of the end contacts on
the Han field. One cannot increase the Hall voltage
indefinitely by increasing W /L.
Equation 2 illustrates the important role of carrier
mobility. In this respect, silicon is not a good material5
compared to, say, IuSb or GaAs. However, one must
go beyond equations 1 and 2 to include practical constraints of power dissipation, electrical resistance,
range of impurity concentrations, and temperature
variation of Hall coefficient. When this is done, silicon
looks much better. Relating constant current and constant voltage modes of operation to semiconductor
processing, observe that thickness and concentration
(equation 1) are also the major processing variables that
control resistor values in integrated circuits, and the
expected tolerance is quite large. On the other hand,with
constant voltage, only the mobility is process dependent, and it tends to be a weak function7 of concentration
in the region of interest. Thus we expect and obtain
much better reproducibility of Hall voltage with constant voltage excitation. This is gained at the expense
of a higher temperature coefficient, however, due to the
variation of mobility with temperature.
Assuming a field of 1000 Gauss t~ be available,
straight-forward calculations using typical mobility
and reasonable geometries showed that we could obtain
a signal of about 30 millivolts with a five volt supply,
and without exceeding typical power dissipation capabilities in IC chips.
Figure 5 shows an expression for total d.c. output
voltage of a Hall element, including the effects of small
entirely in terms of parameters measurable at the
terminals. The offset voltage term, Vq, which is the open
circuit output voltage with zero magnetization, is a very
important parameter in this device. Economic restrictions ruled out the use of external resistors for adjustment of Vq. Its nominal value using IC technology depends mostly on contact geometry and sheet resistance
uniformity in the conducting layer comprising the Hall
element. Fortunately, very accurate geometries are
possible using photolithographic techniques developed

152

Spring Joint Computer Conference, 1969

experimentation was conducted, confirming its feasibility and the accuracy of the preceding characterizations.
As to process considerations for the associated circuitry, the objective was to take advantage of conventional IC processing strengths, which lead to high yield
results on the following:
1. High gain, accurately matched NPN transistors.
2. Low gain PNP transistors.
3. Accurate control of resistance ratios, but not
absolute values.
Throughout the design-development cycle, extensive
effort was devoted to achieving a simple design that is
amenable to high yield processing, yet adequate for the
intended function without external components.

If (13

V34
Vq

+ 1 4 )«

= Vq + VH -

= Offset

The trigger cirmtit
IH ;

I3 R3

~

I4R4

H = Hall Voltage

Voltage; V

Figure 5-Hall element output voltage characterization

for IC fabrication. Variations in Vq can be caused by
several factors, such as internal stress (through the
piezoresistance effect) and temperature gradients. Regardless of the nature of the electronic circuitry that
follows the Hall element, the variations in Vq must be
much lower than the Hall voltage for adequate "signalto-noise" ratio.

Design-Process interrelation8hips
As with any integrated circuit development, the
circuitry, device physics, and process techniques are
interdependent, and must be so treated. At the time the
development was initiated it was considered essential
for low cost objectives to use the epitaxial-diffusion,9
bipolar, NPN based, type of processing which was
rapidly becoming an industry standard. MOS type
processing was not sufficiently controllable to be
seriously considered.
In an NPN type of bipolar structure, the collector
layer has the lowest carrier concentration and highest
mobility; it is the best choice for a Hall element. Hence
the design approach was pursued on the basis of forming
the Hall element simultaneously with collector regions
for NPN transistors. The same isolation diffusion is used
for defining the Hall element geometry. (The Hall element outline is faintly visible in Figure 3). Since this is
a novel type of Hall element structure, some preliminary

The function of the trigger circuit is to accept the
linear output (with or without linear amplification) of
the Hall element and convert it to a binary or ON-OFF
mode, with regenerative switching transitions and controllable hysteresis (or differential between the "turn
on" and "turn off" operate points).
The trigger circuit we devised is shown in Figure 6.
It is a variation on the Schmitt type of circuit. It may
be implemented with just two resistors and two bipolar transistors. An approximate analysis aimed at
providing insight into its general characteristics will
be given here.
Assumptions used in approximate analysis:
a. The transistor model shown in Figure 6 applies.
The most important feature of this model is that
Shockley'S law applies to the I'E - VBE characteristic. This is well established for silicon
planar bipolar transistors. Extrinsic resistances,
collector conductance and all time dependent
effects are omitted. The model requires active
region operation, which is easily met.
b, 111 + I B ' = I, a constant
c. IB« I c (high gain)
The static voltage control characteristics at the input
base is of primary interest.
(3)

Using the above assumptions this becomes,
VB = - KT (1
q

~

n I's

+1

1 - IE/I)
nIBil
(aIR4) IE!I

(4)

Solid State Keyboard

NOT SATURATE

switching transition, but not the fact of its occurrence.
The trigger points are thus found by taking the derivative of equation 4, shown below as equation 5, equating
it to 0, and simultaneously solving equations 4 and 5.

T' DOES

I
I

KT

dV B
V

d (I )

8

III

80-----4

= -

1

q (1 - Ill/I)

fI

- aIR4 = 0

(5)

A result from thls approximate analysls is given
below for one condition of regenerative feedback. The
"ON" condition is defined as T' conducting and T off.

T
E

Trigger Circuit Schematic

1 ~'l

.LVV

Transistor Model Used

Turn ON point

Turn OFF point

- .069 volts 0.723

- .061 volts 0.276

Figure 6-Trigger circuit. schematic

.130 volts

The first term of equation 4 represents the control
characteristic 10 of a conventional difference amplifier
stage using the same assumptions noted above. The
second term is the result of linear regenerative feedback.
If this term has the appropriate magnitude, the transfer
characteristic will have a negative resistance region that
covers a few millivolts. The transfer characteristic may
be easily observed on a curve tracer using a discrete
component version of the circuit. One such observation
is reproduced in Figure 7. The constant total emitter
current condition is approximated in this version of the
circuit by using an emitter resistor with voltage drop
that is several times larger than the VBB voltage.
The nature of regenerative switching transitions may
be reviewed in a number. of references, particularly
those dealing with turmel diode circuits. Chapter 15
in Linvill and Gibbons' bookS is especially good. We
will only note here that the trigger points depend exclusively on static parameters, and are given by the
transition points from positive to negative resistance
around any closed mesh of the circuit. Reactive effects,
active device response time, etc., affect the speed of the

KT = .026 volts, and I, = I',
q

Our investigations showed that this circuit configuration could provide regenerative switching transitions
with rather precisely defined trigger points and voltage
transitions between trigger points of a few millivolts.
The component requirements are well suited for integration, with critical performance depending on transistor matching and resistance ratios. Note that the transistor matching requirements are the same as for a good
difference amplifier stage, with VBB matching to about
±2 millivolts. This is routinely done in Ie's, due to
close physical proximity, extremely accurate matching
of geometries, and simultaneous processing.
Output amplifier

The output amplifier, consisting of a PNP stage
driving an NP~ Darlington, operates in standard saturated switching logic fashion. Its characteristics are
relatively non-critical. The PNP is fabricated with a
"lateral" geometry and its current gain is low. Static
conditions for the OFF and ON states are as follows:

lOpA/div.

.,

INPUT
..

:···~·r~

OFF State T' Off
zero drive to
PNP base
ON State

Figure 7--Experimentallook at trigger circuit contl'Ol
characteristic

OUTPUT
Output voltage = 0
(with reference tosupply)

T'On
Output voltage =
PNP saturated supply voltage minus
(VeIl SATa + V BR4
V BBi)

+

154

Spring Joint Computer Conference, 1969

As previously noted, a functional requirement is that
there be no linear region in the output of the device,
i.e., output voltages between the OFF and ON levels can
only exist on a transient basis, This requires t.h9"t the
thresholds associated with the output amplifier operation be well within the negative resistance region of the
trigger circuit Dontrol characteristic. The resistor R2 is
designed such that the value of I'C at the trigger circuit turn on point will not develop enough voltage
across R2 to forward bias the PNP bas&-emitter junction. The combined PNP-NPN gain requirement is
such that the PNP stage saturates at a value of Fe
that is below the trigger circuit turn off point. Resistor
Ra provides adequate margin against self turn-on in the
Darlington stage under worst case temperature and
gain conditions.
The output transistor has dual emitters and provides
two isolated outputs. This aids in the encoding logic;
in effect, part of that logic is included in the chip. This
is an example of the economics possible when using IC
cost to the chip.
An additional benefit of the solid state keyboard is
that the output sjgnal from the key does not require
additional buffering to eliminate the effects of contact
bounce. Switching times are in the low microsecond
range and are free from ringing or oscillation.

has been the stress sensitivity of the Hall element
through the piezoresistance effect, previously mentioned, and this has been overcome by some special
mechanical features in the chip-package design.

Chip specification
The specification is given in Table I. It is written as
broad as possible to maximize the overall process yield.

Computer aided analysis
In the design of a product intended for the computer
field, the utilization of computer-aided analysis seems
especially fitting. When we avoid some of the simplifying assumptions used in the preceding approximate
analysis; equations analogous to (4) and (5) become
extremely cumbersome. Their simultaneous solution to
obtain operate and release points becomes humanly
intractable; a computer program was written to obtain
such solutions.
Performance of the device was studied as a function
of several independent parameters.
l. Supply voltage
2. Transistor gain, matched and prescribed mISmatch
3. Emitter junction saturation current, matched
and prescribed mismatch
4. Resistor and resistor ratios R 1 , R 4/R 1 .
5. Offset voltage, Vq

Integration of sensor and electronics
Aside from the usual considerations of parasitic
interactions within an integrated circuit, the special
effects resulting from including the sensor in
the Ie chip constituted an interesting and novel
aspect of this development. In general, we find
and predict a growing trend toward "integrated transducer" semi-conductor devices. Inductance parasitics
are virtually eliminated due to the extremely small
dimensions. A potential source of ringing or oscillation
in regenerative switching circuitry is thus avoided. For
the same reason, noise pickup in the leads from sensor
to electronics is minimized. High impedance leads to the
outside world are avoided.
In the functional operation of this device, magnetization is applied over the entire chip. This has no effect on
the electronics, as expected, for the resistors and transistors do not have any magnetic sensitivity in the
magrietic field range of int~rest. The Hall element output, like a balanced bridge with matched temperature
sensitive resistors, is sensitive to temperature gradients.
This has to be taken into account in the output stage
design and operation, and the thermal design of the
package. The most troublesome parasitic encountered

Space does not allow presentation of this analysis
and results. The reader may contact the authors If
interested. The computer-obtained results have been
of great value in guiding the design and the design-process relationship. Figure 8 shows the effect of gain and
~=1.05
5

\=
I

INDUCTION Y. S.

I

800

S
S

I-~~

t1.P.

L

I

I

I

,
600

~

iL
f(

I

I

I

i

i I
I

1

20

I

I

I

~

400
10

30

tB~

I

j,.- V """ I

700

500

~5= 0.9

a

1 I I 1 I I I I II I I I I I I

9001

G
A
U

1.0

40

"!I,

I

I

I

I

i

i

I

I

i

50

60

70

80

Figure S-J£ffect of gain and gain mismatch

I

I,
i

I

tB
"s'

90

100

!

R.P.

t----

Solid State Keyboard

gain mismatch. We note that performance becomes
essentially independent of transistor beta in the range
above 50. With these results, a realistic process gain
specification minimum of 30 was established.

Temperature characteristics
The dependence of operate and release points on
temperature for a typical device is shown in Figure 9,
based on experimental data. The slope of the cunTes is
roughly accounted for by the expected temperature
dependence of mobility. However, second order effects
in the circuitry have a certain influence, not completely
analyzed at this time. First order temperature effects
in the circuitry are eliminated by use of matching and
ratioing techniques.

Packaging the chip
Upon examining the economics of integrated circuits,
it becomes apparent that much of the cost of commercial integrated circuits is in chip packaging rather than
the chip itself. It was necessary, therefore, to develop a
low cost, reliable packaging technique suitable for
magnetic operation.
In developing such a package there are many parameter trade-offs that must be made in order to arrive at
an optimum configuration. In most standard chip packaging approaches the chip is eutecticly bonded to a
which closely approximates the thermal expansion of
the silicon chip. Since this device was to be magnetically
operated, kovar is not desirable because it is ferromagnetic. On examining the non-magnetic metals and al-

loys, it was evident that there were none with the proper
thermal coefficient of expansion. Therefore, it was necessary to find another method of holding the chip. The
approach selected was to allow the ohip, in essence,to
float in a non-rigid. potting material. This is accomplished in the following manner: A leadframe is stamped
from phosphor bronze, inserted into a mold, and transfer molded with a rigid plastic leaving a cavity for the
in Figure 10. It should be noted that the cavity for the
chip is entirely plastic.
The chip is inserted into the cavity and the four
wires are ultrasonically bonded between the pads on the
chip and the leadframe. At this point, the chip is held
in place by the four wires. The final packaging operation
is to fill the cavity with a silicone potting material,
which has a very low viscosity in the uncured condition,
and it completely encapsulates the chip including the
reverse side. Figure 11 shows the chip in its cavity prior
to being potted.
In order to minimize the cost of this packaging approach, it was necessary to design so that wire bonding
could be automated. This was accomplished in the
following manner. The wafer is sawed into chips with an
abrasive slurry, rather than use the normal scribe and
break process. The sawing produces chips with square
edges and with dimensions controlled to within ± .001
inches. The chip cavity is made only slightly larger
than the maximum chip size; hence the location of the
precisely controlled. This allows the wire bonding machine to be mechanically aligned, rather than require
the operator to make a visual alignment for each bond.
It should also be noted from Figure 3 that the pads on
the chip are large-(by integrated circuit standards)approximately .010" square.

800

Gauss
600
OP

400

RP

200

Tempera ture in degrees Cen tigrade

30

Figure 9-Effect of temperature on magnetic operation

155

60

Figure l{}---Lead frame showing chip cavity

Spring Joint Computer Conference, 1969

156

asymptotic to the zero flux axis, a slight change in the
release point of the chip would require a large change in
the movement of the magnet to reach the release point.
This is not desirable. If two magnets a.re used and are
magnetized as shown in Figure 13, the flux versus gap
position curve will tend to be sinusoidal. This is desirable if the total travel of the magnet assembly can be
limited to the nearly linear portion of the curve. Since
the flux required for both operate and release points is
positive, the negative portion of the curve would not be
used. By inserting the two magnets in a "U" shaped
shunt and magnetizing them in place with a specially
shaped magetizing fixture, it is possible to produce the
curve shown in Figure 14. The result of this is to move
the majority of the sinusoid above the zero flux axis.
Figure 14 also shows the ma~l.Let assembly and the shape
of the poles on each of the magnets.
Figure II-Chip bonded in place

sl
IC~IP I

Package thermal considerations

I

Is :

Without a eutectic bond to provide heat transfer
between chip and package, it is necessary for heat
transfer to occur through the aluminum wires and the
silicone potting material. By using .002" diameter wire
the thermal resistance is 355 degrees Centigrade per
watt, unpotted. The potting material further reduces
this to 266 degrees Centigrade per watt, which is quite
comparable to the standard plastic dual in-line package.

(

Magnet actuation

DISTANCE =(d)

If a bar magnet is moved along its axis perpendicular
to the plane of the Hall element, the normal component
of flux will vary with the magnet movement according
to the curve shown in Figure 12. Since the curve runs

MAGNETIC

FLUX

t

Figure 1:3--Flux

HAll GENERATOR

\

1000

(GAUSS)

1

b
~

iBAR

j

VH

position, double pole magnet

100

®

t

MAGKEll

N

NI

~d~

S

MAGNETIC
FLUX
(GAUSS)

d '-'-

100

50

50]

i i i

.050

.100

..

.150

DISTANCE =(d)
Figure 12-Flux vs position. single pole har magnet

.100

DISTANCE

.150

=(d)

Figw'e 14---Fiux V~ position, douhle pole, modified

Solid State Keyboard

The magnets are made of polyvinyl chloride filled
with barium ferrite. This combination produces an extremely stable, yet low cost, permanent magnet material. The shunt is soft iron which increases the magnet
efficiency and helps to reduce the effect of stray· magnetic fields. The chip package is made as thin as possible to reduce the air gap. The magnet assembly with
the chip package is shown in Figure 15. Referring to
the specification on the chip, and relating these to the
flux versus position curve, it is possible to establish the
operate and release points of the key, as shown in
Figure 16.

157

Table I -Chip specifications
Parameter

Operate Point (OP)
Release Point (RP)
Differen tial
(OP - RP)
Supply Voltage
Supply Current
(OFF Condition)
Output Voltage
(ON) @ 5V supply
Output Voltage
(OFF) 5000 ohm
Output Current
(ON) (each
terminal)

Minimum

300
100
150
4.75

Maximum

750

Gauss
Gauss
;).25

15

3.4

Units

Gauss
Volts
rnA

3.6

Volts

0.25

Volts

10

rnA

Reliahility test results

Figure 15-Chip package and magnet assembly

A variety of enviromnental tests have been made on
the key chip integrated circuit, packaged as noted herein. In addition to tests on functional performance on
conventional chips, chips with special metallization
patterns were prepared and packaged, such that junction characteristics and Hall element output could be
measured directly. This allows a more sensitive indication of incipient de~adation than does functi '"lnal
performance. Table II describes tests on four lots of
devices. The results are in keeping with the reliability

1000 -

500 -

o
Key Travel in Inches

Figure 16-Operate and release ranges of key

Figure 17-Plunger magnet assembly

158

Spring Joint Computer Conference, 1969

Table II - Reliahility test results

No. of Dem:ces

Type of Test

30

Functional,
magnetic actuation
Functional,
magnetic actuation
Hall element (Vq)

15
30

Collector junction

6

V CBO @ 10 jJA

Environment

Time

Results

Normal Office

15 months

Xo failures

75 to 100 deg. F.

4~30

No failures

70 deg. C.
90% R.H.
70 deg. C.
90% R.H.

1000 hrs.

hrs.

1000 hrs.'

Maximum variation
of 2%
No change

expected of semiconductor devices, when designed,
processed and packaged properly. These tests are continuing and others are being initiated.

Mechanical assembly
The magnet assembly is inserted into the key plunger
which is shown in Figure 17 .:rrhe plunger magnet assembly is guided in the key housing by large area. guides.
We have shaped the top of. the plunger and the inside of
the two-shot molded button so that the button is press
fitted directly into the plunger, avoiding the conventional adaptor pin. In addition to lower cost this provides the advantage of a low keyboard profile.
The chip package is inserted into slots in the housing
which hold it in the gap of the magnet assembly. Two
small tangs on the bottom of one side of the magnet
shunt hold the return spring in place. This spring is
designed to provide the two to five ounces of operating

Figure t9--Mounting rail-PC board assembly

force under minimum stress conditions, assuring long
life without getting weak.
The key module, shown in Figure 18, is inserted into
a mounting rail. The module snaps into the rail, which
has clearance holes for the leads of the chip package to
extend through it and be soldered into a printed circuit
board. The mounting rails are welded to the end mounting bracket and the entire assembly is riveted to a PC
board as shown in Figure 19. The printed circuit board
provides the electrical connection between the key
modules and a second PC board. The latter contains
the electronics for encoding, t4e strebe signal, and the
electrical interlock which prohibits an error code generation when more than one key is depressed.
CONCLUSION
Figure IS-Key assembly

The solid state keyboard uses a new switching concept
which capitalizes on the inherent reliability and low

Solid State Keyboard

cost of integrated circuits. The output of this device is
compatible with the integrated circuits used in computers.
The keyboard is deliberately made modular so that it
can be adapted to special key formats and codes. It
provides an electronic interlock instead of the usual
mechanical one, and as a result allows higher speed
operation.
¥l}>ile the keyboard is different in TIli:my :respects, it
has maintained those industry standards which have
been substantiated by human factor studies such as key
stroke and force, key loea tion, and the key layout in the
touch typing area.
ACKNOWLEDG MENTS
The development of the solid state keyboard has been
possible through the enthusiastic support and dedicated
efforts of many people in our respective organizations.
We could not hope to fairly cite individual contributions
within acceptable space limits here. We also appreciate
the consultation provided by other research and engineering groups in our Company.
REFERENCES
R L DEININGER
Human factors engineering studies of the design and use

159

of pushbutton telephone sets
BSTJ Vol XXXIX No 4 995-1012 July 1968

2 R L DEININGER
Desirable push-button characteristics

IRE Transactions on Human Factors in Blectronics
March 1960
:3 H M BOWEN
Rational design jor control: Man communicating to machine,

Industrial design Vol XI No 5 51-59 May 1964
4 R D KI~CAID
Human factors design recommendations for
touch operated keyboards

Report 12091-FR Honeywell Systems and Research Center
January 1969
5 A C BEER
The Hall effect and related phenomena

Solid State Electronics Pergamon Press Vol 9 339-351
6 A C BEER
The Hall effect

International Science and Technology December 1966
7 0 N TUFTE E L STELZER
Magnetoresistance in heavily doped N-Type silicon
Phys Rev Vol 139 No 1A A-265-A-271 July 5 1965

8 J G LINVILL J. F GIBBONS
Transistors and active circuits

McGraw-Hill Book Co New York 1961
9 R M WARNER JR J N FORDEMWALT (Editors)
Integrated circuits

McGraw-Hill Book Co New York 132-149 1965
10 J T MAUPIN
The control characteristic oj current switching logic stages

Honeywell Corporate Research Center Memorandum
HR 63-37 July 1963

Computer generated graphic segments
in a raster display
by RICHARD A. METZGER
Rome A ir Development Center

Rome, New York

In addition, graphic figures require a set of defining
equations, each valid for a given domain. Thus one of
the simplest means of generating complex figures is by
combination of graphic segments (lines, circles, arcs,
etc.), into the higher order figures.
The particular problem to be addressed here is the
generation of graphic segments (straight and curved
lines) within the constraints of a raster format display.
Algorithms are developed to allow computer generation
of selected graphip segments of arbitrary length (constrained by screen si,ze) at any desired screen location.
The raster will be considered as an N x M Cartesian
grid, where N is the number of scan lines and M is the
number of addressable points on a line. All operations
will be performed within the constraints of this address
grid. By treating the grid dimensions as variable, the
algorithms are immediately usable for any line standard raster. The software approach to development of
the algorithms was adopted since this allows usage with
any of the standard D-V converters, whereas a hardware implementation is particular as to type. However,
there is nothing within the adopted approach which
prohibits hardware implementation.
Prior to considering the algorithms for generation of
graphic segment, a bri~f discussion of Digital-to-Video
conversion as a display technique will be presented.

INTRODUCTION
The increased use of computer graphics to enhance the
man-machine interface has resulted in many and
varied systems and devices to meet a multitude of
needs. One type of eli,splay that is receiving new emphasis as a computer output device is the "raster
for!p.at" display (of which standard television is a particular type). Among the reasons for using this type of
display are: (1) the relative simplicity of the display
dev~ce, (2) the ease of remote operation for multiple
statIOn users, (3) the low cost per station, (4) capability for mixing output with standard television
sources, and (5) good position repeatability for computer generated data.
However, to utilize a raster display (either standard
525 line TV or other line standard) as a computer output device, a conversion from digital to video data
must be performed. The device utilized to perform this
function Is commonly referred to as a Digital-to-Video
(D/V) Converter. It accepts digital data from the data
processing system and converts it to a video signal
compatible with the raster scan display. The converter
being a digital device, often becomes complicated sinc~
it is forced to operate within the timing constraints of
the Raster Scan Display System (RSDS). A problem
a!so arises in the subjective appearance of the display,
smce all data must be generated within the line-by-line
structure of the raster. In the case of alphanumerics a
fixed-size matrix of dots can be used to generate v:ry
acceptable symbology. However, the generation of
graphic segments is not as easily accomplished.
Graphic segments and figures vary greatly in terms
of size, shape, orientation, and complexity. If the scan
lines forming the raster together with the discrete
points on each scan line are considered as a Cartesian
grid, it can be seen that in general, graphic segments
will not fit exactly within the constraints of this grid.

Digital-to-video conversion

The generation of data within a raster formatted
display is governed by the timing of the raster sweeps.
To generate a "dot" at a given point it is necessary to
unblank the beam at the instant it traverses the specified address. As stated previously~ the Raster Format of
the display can be considered as an address coordinate
grid where the individual scan lines represent the ordinate values (Y -Address) and the points along the line
represent the abscissa values (X ·Address).

161

Spring Joint Computer Conference, 1969

162

By considering the relation between the scan rate of
the electron beam and the Cartesian address grid, it
can be seen that associated with any given picture element there is a corresponding X:- Y coordinate address
and vice versa. Thus by taking into account the number of lines preceding the addressed line and the number of elements on this line preceding the addressed
element, a given tiple interval after the beginning of
each frame can be associated with each picture element.
In this way D- V conversion can be considered as a
position to time conversion.

I

~

,....,,..1-,.

\JQI\..J.1.L

v.L.

Since the raster timing must provide overall control
of the conversion as well as display process, all digital
and display functions must be timed to the raster
synchroniza tion pulses or harmonics thereof. The sync
and comparator section provides this control interface
as well as provide the neceRRary timing signals internal to the converter. There are two primary ways of
providing the control interface. In the first, the raster
synchronization pulses are fed from the display device
to the sync and comparator section and the internal
timing for the converter derived from it. In the second
mode, the sync and comparator section of the converter
contains a crystal controlled clock \vhich operates at a
harmonic of raster timing, with the latter being derived from the crystal.
Under control of the sync and comparator section,
the data is transferred from the buffer memory to the
character generator where a dot pattern of the alpha-

J

Interface
Contro I

l

Sy nc and xComparator

y

Bit per elemept techniques of D-V conversion

One means of implementing a digital-to-video converter to provide the above type of position to time
conversion is the "Bit Per Element" converter. The
general functions of such a converter are outlined in
Figure 1. Input data is accepted from the data source
by the interface control in a word serial, bit parallel
form. This data consists of an X and Y address (es),
character code and control bits. Data format and parity
are checked and if proper, the data is transferred to the
buffer memory and process control. The buffer memory
is a small high speed digjtal memory (usually core)
which temporarily stores the character, vector, and
control data ill the same form as received by the interface unit. By means of the process control, the address
bits are separa ted and transferred to the sync and comparator section while the character/vector dat~ is held
in the buffer memor~-. If the data supplied from the
data source is not sorted (in X-Y address), then the
process control has the additional function of sorting
the address data in ascending orders of Y and X within

Ho ri z and Vert
Synch ron izatlon

DiQitol Data

y

Buffer Memory
and
I nterf ace
Control

Vector
Genera to r

Character
Gene rotor

I
Input

Memory

Control

J
DiQital

l
Output

Video

Memory

,

Memory

Outp u t

Co ntro I

Video

Figure I-Bit per element digital-to-video converter

numeric symbol, etc .... to be displayed is formed.
This dot pattern is then transferred to a section of the
video memory determined by the display coordinate
address. In the case of a graphic segment, a single dot
is generated at each of a series of coordinate addresses
with the group or sequence of dots forming the graphic
figure.
The video memory contains one bit of digital storage
(1 = unblanked electron beam, 0 = blanked electron
beam) for each picture element on the display surface.

Computer Generated Graphic Segments

the contents of the video memory bear a one-to-one
correspondence to the generated display. To maintain
display continuity and eliminate presentation of partial
performed during retrace of the electron beam when it
is blanked from the display surface. The memOIY is
read out in synchronization with the beam, i.e., ever.f
bit is read out as the electron bea.m traverses the corresponding point on the display surface. To attain the
output speed required, it is necessary to perform multiple word read out, multiplex several tracks or lines, or
use very long word lengths. In each case the data is
read into a register for parallel to serial shifts. When
the serial bit stream is inserted into the synchronization and blanking interval, the video signal results.
Real time techniques of D/V conversion

An alternative method for implementation of D /V
converters are the "Real-Time" type represented by
Figure 2. The primary difference is the absence of the
large (digital) video memory to recirculate the "bit per
element" display at the 30 frame/sec refresh rate.
The data is transferred from the data source through
the interface unit to the buffer memory in a manner
analogous to the previous example. In this case, however, the buffer memory is of sufficient capacity to
store a complete frame in computer word form, e.g., to
present 1000 characters, each defined by three computerwords requires a 3000 word memory. The addressed portion of the stored words are continuously
compared to the position of the scanning beam. This is
accomplished by use of two counters controlled by the
raster synchronization pulses. One counter is advanced
by the horizontal synchronization pulse and indicates
which scan line (Y-Address) is being written. A second,
higher speed, counter advances by M for each horizontal sync pulse, until a number corresponding to the
number of picture elements per line is attained. In this
way the second counter indicates the picture element
(X-Address) being scanned. By continuously sampling
both counters, the screen address for any specified X-Y
A given interval prior to coincidence (sufficient to
account for propagation delay) the synchronization and
comparator circuits transfer the character data from
the buffer memory to the character/vector generator.
A dot pattern of the character/vector is generated at a
bit rate sufficient for insertion directly into the raster.
Thus the data is transferred directly from the character/vector generator to the display device by means
of high speed register without the requirement for a

163

Horz ond Vert
Synchroni zotion

Dioital Data

Interfoc e
Control

Sync and X-V
Comparator

Buffer

Memory

Process

Contro I

Vecto r
Generator

C harocter
Generator

Output

Contro I

L

I

J
Output

vi d eo

Figure 2--Real time digital-to-video eonverter

digital video memory. This sequence is performed at a
30 frame per second rate since no digital video memory
is available for display refresh. Erasure of the data is
accomplished by inhibiting the data output from the
character/vector generator and entering new data into
the digital memory. In the use of the bit per element
converters, a specific erase function (which amounts to
entering the complemented character dot pattern) must
be provided to remove the displayed dot pattern from
the digital video memory.
Straight line generation

The complexity involved in generation of graphic
segments in a raster format can be seen by considering
the straight line vector as shmvn in Figure 3. It is desired to generate a line connecting points (Xl, YI ) and
(X2, Y2) where the Y values represent raster lines and

Spring Joint Computer Conference, 1969

164

X,V,

T~---- - - _

.illY'

V

z
Y,

--

--____

•

:::;:.::;".' :: -

.

/ " Troce

--___

Usi",;! Increment

Rounded To Neorest

--

=

:~

based upon a "best fit" technique minimizing the error
with respect to the desired line, introduced with an
incrementation in either the X or Y direction or both.
The main functions to be performed by any straight
line algorithms are:

InteQ,r

1. determination of direction, right or left, which
controls whether incrementation or decrementation, respectively of the X address coordinate
is required.
2. determination of whether the angle of inclination
is greater than, less than, or equal to 45°.
3. determination of the DELTA segment length.
4. generation of a "dot" at the sequence of points
between (Xl, Y1) and (X2, Y2) within the const.raints previously listed and in accordance with
the above data.

X z Yz

Error

I·

IError I

·1

Figure 3-8traight line segment in a raster grid

the X values represent picture elements within a raster
line. If the lines were horizontal, vertical, or 45 degrees,
the generation would be trivial. Without loss of generality, the analysis which follows is for a line directed
down to the right at an angle, a < 45° as shown in
Figure 3. (A similar type of analysis could be performed
for any other octant.)
To form a trace at an angle a < 45°, the address of the
generated dot must be increased by a given number
of units (called the DELTA value), in the X direction,
prior to a one-unit increase in the Y address. For a line
at an angle a > 45°, the address is incremented DELTA
units in the Y direction prior to a one-unit increase in
the X address. The key to generation of the proper line
thus lies in the choice of the "DELTA" value. If
DELTA is set equal to the slope,

then the error is equal to the remainder (R) of the
integer division. If the DELTA is set equal to Q
rounded to the nearest integer, then the error equals R
if R < aY/2 and equals (aY - R) if R ~ aY/2. In
general, if the slope Q is used to determine the DELTA
value, then to obtain a zero end point error requires R
increments of DELTA equal to (Q + 1) and (aY - R)
increments DELTA equals to Q.
This yields
LlX= (Q+l)R+(aY-R)Q=QaY+R (2)

which is the condition for zero error. However, it is a
formidable task to obtain a line with acceptable linearity and no end point error when computations are
based only end point data, since the technique for
intermixing the two different length DELTA segments
resulting in a zero error is dependent on the particular
end points in question. Thus the approach adopted is

The DELTA value is based upon a determination of
whether incrementing the current address (X" VB)' in
the X direction, Y direction or both will result in the
smallest deviation from the desired line. By summing
the number of unit incrementations in a given direction, X or Y (which corresponds to the number of
iterations prior to sign change), the DELTA length can
be determined.
Let the coordinate grid of Figure 4a represent the
raster coordinate grid in the vicinity of the start point
X. Y The actual trace represents the sequence of
points which most closely approximates the desired
line connecting Xs Y and XI YI (not shown). The inclination with respect to the 45° line (determined from
and aY) imposes a limitation upon the degrees of
freedom of movement. Referring to the case depicted
in Figure 4b, it can be seen that the possible new
addresses are point. ] (Xl! + 1; Y.) or point 2
B.

B

ax

xv.
S

y

s/"
,

341

~, ~
'"

y 341

y

345

~.

'"",,,

y 343
y 344

"""-

~

I

~,

\1'

I

~

I

~h

V

~

d
'~ ~.Desire
yac e
~

'",",
Figure 4A-Coordinate grid as utilized in delta suhroutine

Computer Generated Graphic Segments

165

2AY
AX

flY

AX

2 AY-AX

~i---~-dx2 AX- lAY
AX

/

Desired
Trace

Figure 4C--8econd move determination in grid structure

Figure 4B-First move determination in grid structure

x s+ I

XS+2

24Y

(X, + 1, Y 8 + 1). If the error associated with each
move is represented by A or B respectively, the geometric relationships allow the ratio of the error values
to be determined as

I-lll.
4)(

24)(-24Y

X=

4)(

,

YS+2

B

(3)

If the condition of equal error is chosen as the discriminant point, a value Rl can be defined such that

Rl = 2LiY - LiX

(4)

where the sign of Rl indicates the minimum error move
to point 1 or point 2. (In Figure 4b the minimum error
is to point 2.)
Referring to Figure 4c to consider the second move
determination involving error distances C and D, the
same analysis yields an Rl discriminant value
RI = Rl

4)(

+

2LiY - 2LlX

the previous point with the value dependent on
both the previous point and the slope.
upon the sign of the error term.
The form 9f the general equations is based upon
inclination:
a. If the angle of inclination is

(5)

been to point 1 rather than point 2, the RI for the
subsequent move, Figure 4d discriminant, would assume
the form
II

RI = Rl

Figure 4D---Alternate second move determination

+ 2LiY

a. After the first move from point X Y B, all subsequent moves reduce to one of the two above
cases.
b. The form of the error equation is dependent upon

(7)

2LiY - LiX

and

RI+1 =

(6)

In both cases the sign of RI would determine the
minimum error move.
If this analysis is pursued to the general case including inclinations both greater and less than 45°, the
following results are obtained:

=

Rl

< 45°, then

{

RI

t

RI

+ 2LiY

2LiY - 2LlX

if RI 2: 0

(8)

<0

(9)

if RI

b. If the angle of inclination is >45° the roles of X
and Yare interposed and we obtain
Rl

(10)

= 2LlX - LiY

and

8,

RI
RI+1 =

{

RI

+

2LlX - 2LiY

+ 2LiX

if RI 2: 0

(11)

<0

(12)

if R I

166

Spring Joint Computer Conference, 1969

The resultihg equations (Equations 7, 8, 9, 10, 11,
and 12) can be employed to determine the length of the
DELTA segments by noting the number of iterations
performed on RI + 1 between sign changes. Proper
initialization based upon inclination with respect to the
45 0 line allow use of the following equations which are
independent of line inclination:

Rl = 2T [2] - T [1]

RJ+l

fRI + 2T [2] = i
lRI

+ 2T [2]

2T [1]

(13)
if RI

~

if RI

<0

0 (14)
(15)

Each iteration of RI ~ 0 increases the current address
by one in both the X and Y directions. Each iteration
of RJ < 0 increases the X Address by one, while holding
the Y Address constant. Summation of the iterations
RI < 0 prior to each RI 2:: 0 yield the DELTA value.
This algorithm was verified by means of a computer
program to generate straight lines connecting any two
points within a 525-line raster grid.
The constraints placed on the straight line generator
routine were the following:
1. All vectors will be generated in the direction of
increasing Y address with the origin of the
coordinate system at the upper left-hand corner
of the display. (Addresses need not be sorted for
input.)
2. All vectors will be processed (although not
specified) as one of the following:
a.
b.
c.
d.
e.
f.
g.

Down to the left at an angle <45 0
Down to the left at an angle >45 0
Down to the right at an angle <45 0
Down to the right at an angle >45 0
Horizontal line
Vertical line
Down to the right/left at an angle = 45 0

Typical results are depicted in Figure 5. The routine required approximately 370 instructions in a
machine with a 64 instruction repertoire. The maximum error from any computed point to the desired
line is less than 0.5 units.
Circular line generation

In a manner similar to generation of a straight line,
the generation of a circular trace consists of determining the X- Y Address points which minimize the
error distance from the desired trace to the selected
point. By examining a circular trace overlaid on a
Cartesian grid, many of the properties of the circular

Figure 5- -Line segments generated hy eomput.er program

symmetry are observable. A circle of radius 7 is depicted- in Figure 6, together with the appropriate x- Y
Address sequence to generate the trace within the
constraints of the grid structure, where the Y-Address
corresponds to scan lines and X-Address to picture
elements along that line. The display trace ,vould bE'
generated by a" dot" (the area of which is equal to a
It can be seen from Figure 7a (and is equally true
is exactly equivalent to those from 1 to D, 2 to A,
2 to B, 3 to B, 3 to C, 4 to C, and 4 to D. Thus by
determining the proper address sequence for the first
octant, the address sequence for all other octants (referenced to the center of the circle) have been obtained.
It should also be noted that no point is more than one
unit removed in each direction from the previous or
subsequent point. Two possible address modifications
can be determined for each octant, the first of which
modifies only one address (X or Y) by one, while the
second modifies both X and Y addresses by one. The
octant in question determines whether the address
modification is an incrementation or a decrementation.
The possible address sequence for each octant are de-

Computer Generated Graphic Segments

167

picted in Figure 7b. Using these address sequences, it is
apparent that each move encompasses a point exterior
to the circle and a point interior to the circle. Table I

\

OCTAN,.

OCTANT I

4

FigUJ'e 7B-Computational model for first octant

OC TAN T

OCTANT

5

represents the various possible moves for each octant,
where (X Y n ) represents the point from which the
move is being made and the columns are the resultant

8

lI

OCTA NT

6

OCTANT

,

7

I.
Exterior
Interior
Figure 6---X- Y addreHs sequence for generation of a eircular traee

1
2
3
4
5
6

7
8

f

r

,L

OCTANT 4

OCTANT I

I t

OCTANT

OCTANT 8

..J I

5

X
X" +
X,,X
X
X
X" +
X"
1I

1
1

1I

1I

1I

1I

1I

1I

-

Y" - 1
Y
Y
Y
1
Y" + 1
Y

1
1

-

1I

Y"
Y 1I

X" - 1
X" + 1
X
1
X + 1
X" + 1
X" - 1
X + 1
X
1
lI

-

1I

1I

+1

1I

-

Y" - 1
Y1l + 1
Y" + 1
Y" - 1
Y +1
Y" - 1
Y
1
Y" + 1
1I

1I

-

The problem then is to determine in each case,
whether a move to an exterior or an interior point
represents the minimum error. This can be accomplished by comparing the differences bet\veen the actual radius (Ro) and the external and internal radii
(Re and R i ) respectively, as shown in Figure 7b. If it
is determined that

(16)
then the minimum error move is to the next exterior
point. Likewise if
Figure 7A-- -X- Y addl'eH;; sequenee for eac-h oetant

(17)

168

Spring Joint Computer Jonference, 1969

then the interior point represents the minimum error.
From Figure 7b it can be seen that
~

Rn

= v'An2

R. =

V'An2 +

RI =

V' (An

(Bn

- 1)2

+ Bn

2

(18)

+ 1)2

(19)

+

(Bn

+ 1)2

(20)

Substituting Equations (19) and (20) into Equation
(16) yields
2Ro> V'An2 + (Bn

+ 1)2 + V (An

- 1)2

+ (Bn + 1)2
(21)

By means of the Triangular Inequality this yields

In a similar manner, Equations (17), (19), and (20)
yield
4Ro2< (2An - 1)2

+ (2Bn + 2)2

(23)

Thus if we define a quantity Q such that

Q = (2A" - 1)2

+ (2Bn + 2)2

- 4Ro2

(24)

then the sign of Q determines whether the minimum
error move is exterior or interior, with Q < 0 denoting
an exterior point and Q ~ 0 denoting an interior point.
Due to the symmetry of the trace, it is only necessary
to determine the move pattern for the first octant and
use this result to perform the address modification for
all octants.
This algorithm was implemented and found to yield
circular traces (Figure 8) in which no computed element is in error by a distance of more than 0.5 address
units in either direction, i.e., interior or exterior. The
generation of circular arcs is accomplished by the same
algorithm by merely specifying data to define the end
points.
It should be noted that for circles with sufficiently
small radii « 4 units) the appearance of uniform curvature diminishes. This is due not to a failure of the
routine but to the fact that for those radii, insufficient
points within the grid structure exist to properly define the curvature. It can be shown that the algorithm
itself is valid for all radii greater than 1.25, with this
lower limit being dictated by the lowest value of R for
which the use of the triangular with Equation 21 remain vHlid,

Figure S-Circular t.races generated by computer program

Parabolic line generation
The generation of parabolic trace within a raster
format under computer control is accomplished in
much the same way as one would generate the trace on
linear graph paper. A set of X-Y axes are assumed and
for selected values along the Y axis, corresponding
values of X are computed according to the defining
Equation.
X 2 = 4PY

(25)

Similariy for selected values of X, one can compute
values of Y according to the Equation

y2 = 4PX

(26)

The difference in method of generation arises in that
the trace on the graph paper is obtained by connecting

Computer Generated Graphic Segments

the points defined by the computation, whereas within
the raster the increments for the independent variable
are chosen to be one line width apart and thus by
merely generating a "dot" at the computed X-address
points, a continuous curve results.
A typical X-Y address sequence for generation of a
parabola is depicted in Figure 9. The actual trace would
be created by generating a "dot" at each arrowhead.
A. It.nrll1O'n
}l.c1c1rp.~~
~p.Ollp.ncp.
will varv
denendin!!.'
..........
"" ...... - - 0 ...... t.np
_.-.... --- --- .,."
upon the focii value (P) several important factors can
be deduced from the figure. The move pattern is up with
increments to the right and left. The number of increments in a given direction is dependent upon the square
root for value of independent variable in relation to
the square root for the previous value of the same
variable. For each increment in the Y direction if
-~------

-,L-

~

.

a

1.

0

< [y4PY

1I

2. 1/2

3.

1

y4PY1I - 1] :::; 72
then Xn = X n- 1

-

< (y4PYn

< [v!4PYn

y4PY1I-l] :::; 1
then· Xn = X n- 1

-

-

y4PYn - 1] < 1'1
then Xn = X n - 1

+1
+

lVI

The third case depicted will occur near the base of the

parabola with case (1) prevailing as the parabola approaches its asymptote. Since the parabola approaches
an asymptote which tends toward infinity, the trace is
continued until a screen address is exceeded in one
direction at which point the computation stops. The
proper incrementation address sequence is dependent
upon the form of the equation, the sign of P, and the
relative values of the square root for succeeding values
of independent variable. The incrementation conditions
for all cases are depicted in Table II where (Xn, Y is the
point being computed, while the value along axis of
symmetry is incremented by one unit.
TI )

The implementation of an algorithm for performing
the above arithmetic and manipulative function is not
complex. However, the computation time becomes very
large for all cases except where the length of the axis of
symmetry is kept small. This is necessitated by the
iterative methods required for computation of the
square root. When implemented on a computer with a
six (6) microsecond cycle time, running times in excess
of 30 seconds were not uncommon. However, the accuracy obtained placed each computed point within one
half display element, since the X (Y) address points are
computed for each Y (X) address. The question immediately arises that if the accuracy specification is
relaxed and an approximation to the parabola (as it
approaches the asymptote) is acceptable, can an appreciable decrease in running time be obtained?
If, for example it is assumed that beyond a given
point(Xp, Yp) (Figure 10) the parabola can be approximated by the straight line (X p, Y p), (X2, Y2) a maximum error E would result at the point the trace
reaches the maximum address or edge of the screen. In
addition, to maintain the trace uniformity, the slope of
the approximating line is chosen to be the same as
the slope of the parabola at the point (X p, Yp). The
slope of the parabola at X p , Y p is

y- A .. i,

\ /

169

.,,'0';.";0'

Xp
dy \
dx yp = 2P

(27)

Since this also represents the slope of the approximating
line,

\

then

X
Ay
2= 2P

~X

(28)

which yields
x

c

y

c

x - AlIi,

(29)
'Figure 9-X-Y address sequence for generation of a parabola

Spring Joint Computer Conference, 1969

170

Top

The value for Y2 is the STOP address of the axis variable
from which X 2 can ~e computed The approximation
can be completed by drawing straight lines between the
points (X p, Y p) and (X2 ,Y2) where X 2 = X 2 + E.
A similar analysis can be carried out for a parabola
satisfying the Equation

Of Display Grid

~

x:. v:. I

flY

y2 = 4PX
yielding a defining Equation for Y p,

Where )(p
Xp

and

fx,

=

+

def~ned

as

EI=JIXZ+ El' - 4Pv,l

t

v,+ EI±JIY, + El'- 4PXZJ

Yp:
With

Yp are

The inclusion of the approximation as a subroutine,
to be entered if the allowable error is E > 0, results in
greatly reduced running times proportional to the error
allowed. In addition, the subjective appearance is
maintained (Figure 11) by retaining the desired curva-

the

Sion

,±)

dependent

upon

the focii

value

Figure l(}-Parabolic approximation model

but

and

Combining the above yields

The above equation (30) relates the acceptable error E
to the X address of each computed point (X p, Y p) and the
coordinate of the point at which the parabola reaches
the edge of the screen (X2, Y2)' By allowing the error to
be specified by the operator, it allows the choice of the
error specification in terms of percent of axis length,
percent of opening, absolute units, etc ... If we use the
defining equation for the parabola (X2 = 4PY) together with Equation (30), the value for Xp can be
determined as
(31)

Figure 11- -Parabolie tl'a('eH generated by eomplltel' program

Computer Generated Graphic Segments

171

Table II-Address modification pattern for parabolic trace
Defining
Equation

P
Axis of
Symmetry

X2 = 4PY

X2 = 4PY

POSe Y

> 0,

~

y2 = 4PX

Left Side

Right Side

X,,~X"_l

XlI~X_l

X,,~X_l+l

X,,~X_I+1

"

> 1/2, ~ 1
> 1, ~ M
> 0, ~ 1/2

"

> 1/2, ~ 1
> 1, ~ M

>0

1/2

Top

Bottom

Axis

"
"

X2 = 4PY

1/

Neg. Y
Axis

1/

1/

1/

"

y2 = 4PX

"

"

>0

"

POSe X

>0

--.,.~

Xn~X_l

Xn~X_I

Xn~X_I+l

Xn~X_I+l

y

X,.~Xn_I+M

> 0,

~

.+M

X ii+-X,,_l+M

~y

"""-.3Irrr..1j-l

n~X_I+M

Yn~YlI-l

1/2

Y"~Y"-l

Axis

"
"

y2 = 4PX

"
"

"
Neg. X
Axis

"
"

"

> 1/2, ~ 1
> 1, ~ M

Yn~Yn_l+l

Y"~Yn_l+1

Yn~Yn-I+M

Yn~Y"_l+M

<0

> 0, ::; 1/2
> 1/2, ::; 1
> 1, ::; M

Yn~Yn-1

Y"~Yn-l

Yn~Y_I+l

YII~Y_I+I

Y,.~Yn_I+M

Yn~Y"_I+M

II

1/

1/

"

ture at the vertex and use of the straight line approximation as the parabola approaches the asymptotic
value.

c. Circular Arc -Center Point (Xc, Yc), Radius,

Many other graphic figures could be generated by
using the "error minimization" technique above; however, their utility would depend upon the system in
question. The figures developed thus far (straight line,
circle, circular arc, parabola, and parabolic arc) form
the basis for a rudimentary system. The more important
aspect from a user point of view would be the combination of the various segment generators for complex
figures.

d. Parabola

Raster graphic system considerations
To effectively utilize the algorithms thus far defined,
they must be incorporated as part of an overall graphic
system or subsystem which includes the Graphic Segment Generators as well as a Graphic Operating System.
In configuring the combined Segment Generator, it is
assumed that the Operating System would provioo the
following data in addition to the segment type designator:
a. Straight Line-Start Point (Xl, Y1), Stop Point
(X2, Y 2)
b. Circle

(R)

-Vertex (X"' Y v ), Focus (P),
Orientation (H or V), Axis Stop
Point

e. Parabolic Arc-Vertex (Xv, Y v), Focus, Orientation, Side, Axis Start, Axis Stop
The Generator would be entered from a Graphic
Operating System and upon completion of its processing
function would return control to the operating system.
I~ addition, all data points would be entered through
the Graphic Operating System which would control
storage and output of the calculated points as well.
The routine is entered at the same point for any of the
segments and branches to the desired section (Straight
line, Circle, etc ... ), based upon the mode bits of the
data words.
The" move discriminant" functions are the same as
previously derived and must remain separate entities in
the combined program. Fn each case, a determination is
made to increment or decrement the variables X and Y.
In general, N incrementation or decrementation will be
performed upon one variable for each increment or decrement of the other variable, where N is calculated by
the respective discriminant function.
Typical program length on a six-microsecond, 64Instruction Set computer, by function:

172

Spring Joint Computer Conference, 1969

Functional Sections
Discriminant-Straight Line
-Circle
- Parabola
Incrementation/Decrementation
Iteration Control

Locations
60
50
70
250
75
350

The size of the output block set aside for storage of
the calculated points depends upon the system in question. For example, if the converter being driven requires
three computer output words to describe a symbol, then
1200 storage locations would describe 400 symbols to
the converter. The size of this storage block is one reason
for considering hardware methods of graphics generation as an alternative to software.
The running time for generation of any given segment is directly proportional to the dimensions of that
segment since the relative size determines the number
of iterations required and all computer instructions
execute in equal time.
In the construction of complex figures from simple
graphic segments many geometric constructions (Tangents, Normals, etc .... ) appear often enough to warrant inclusion in the Operating system. In general, this
amounts to calculating a new set of defining parameters
based upon the segment (or segments) already generated and new segment to be generated.
The following have been investigated and found to
produce desired results with minimum software (Figure
12).
2. Parallel lines.
3. Perpendicular line from a Point Xp Y p on a line
(L).
4. Perpendicular line from a Point Xp Y p to a line.
5. Tangent and Normal to a circle.
6. Tangent and Normal to a parabola.
It has been found that if the desired segments are
defined in terms of critical parameters much of the
manipUlative software developed for direct writing
systems is applicable, with the segments defined by the
manipUlated points being generated by the special
algorithms.
The entire question of number of segments, hardware
vs software generation, amount of manipulative capa-

Figure 12-Cam lever generated by graphic segment generator

bility, etc ... , in the final analysis must be determined
by the system in question.
REFERENCES
1 F G STOCKTON

x-v move plotting
C A C M Vol 6 No 4 April 196:3
2 BECKENBACK & BELLMA~
An introd'uction to inequalities

Random House ~ew York 1961
3 J H WILKE~SON
Rounding errors in algebraic processes

Prentice Hall Series in Automatic Computation
Englewood New Jersey 1963
4 K E IVERSON
A. programming language

K Wiley and Co New York 1962
5 F GRUEN BERGER
Computer graphics

6

7

8

9

Thompson Book Co Washington D C 1967
L L BRINER
A graphic information processing system
IBM TR-21197 March 1966
I E SUTHERLAND
Sketchpad: A ';nan rnachi'ne graphical communication system
Technical Report fJ 296 Lincoln Labs MIT Jan 1963
A D FALKOFF & IVERSON
The APL/360 terminal system
IBM Research Report RC-1922 Oct 16 1967
A D FALKOFF & IVERSON
The

~1P L

terminal system: instructi01".8 for operation

IBM Research Yorktown Heights New York 1966

Errors in frequencv-domain processine:
of images *
.&.,

.&

'-'

by GRANT B. ANDERSON and THOMAS S. HUANG
Mas8achusett8 Institute of Technology
Cambridge, Massachusetts

INTRODUCTION
Practical techniques for the determination of image
spectra have been developed and become popular in the
past few years. Both optical processing systems and
digital computers can be used to perform linear filtering
via the frequency domain. Optical processing systems
use Fourier-transforming lenses and coherent light.
Digital computer software uses the Cooley-Tukey
algorithm to advantage, while computer hardware must
be augmented by optical scanning devices that interface
with images. Processing errors arise in both types of
systems, but for different reasons. In this paper we
present some results concerning errors in the spatial
frequency domain.

Two-dimensional Fourie:r analysis
To facilitate later discussions, we shall review briefly
the key relations in two-dimensional Fourier analysis.
The Fourier transfonn of f(x, y) is defined as
F(u, v)

= J~

L:

f(x, y)

e- i2r (ux+1IJ1)

dxdy .

(1)

Fourier series may be used to represent f(x, y) in that
area. In particular,

i:: i:

f(x, y) =

m=-QO

am,n

= -1T:.:TlI

fTrt:
0

am,1I ei2r(m:.:!Trt:+1IJ1!T,,) .

(3)

n=r-CO

1'1'11 f(x, y) e-i2r(mx!Trt:+1IJ1!TlI) dxdy.
(4)

0

When f(x, y) is impulsive and of the form
M-l N-l

f(x, y) =

L: L:

m-o

n-o

(jm,lI

a(x - mT:!:, y - nTlI ) , (5)

where a is the Dirac delta function and T:!: = MT:.: and
Ty = NTy, then a discrete Fourier transform is appro- .
priate. The discrete Fourier transfonn of the discrete
function (jm,1I is given as

where k = 0, 1, ... , M - 1, and i = 0, 1, ... , N - 1.
The inversion relation is

The inversion relation is then given by
f(x, y) =

L: f~

(7)
F(u, v) ei2r (w:+111/) dudv .

(2)

If f(x, y) is nonzero only inside a finite rectangular
area 0 ::; x ::; T:.:, 0 ::; y ::; T J" then a two-dimensional

* This work was supported principally by the National Institutes
of Health (Grants 5 POI GM-14940-02 and 5 POI GM-I500602), and in part by the Joint Services Electronics Program
(Contract DA28-{)43-AM~2536(E».

Fourie:r trans!cmnation
Optical processing systems l
When a film transparency of complex amplitude
f(x, y) is illuminated with collimated monochromatic
light at the front focal plane of a double-convex lens,
the light amplitude at the back focal plane will be

17'<

174

Spring Joint Computer Conference, 1969

f(x, y). In this relation, x and yare spatial coordinates,
A is the wavelength of light, d is the focal length of the
lens, and u and v are spatial frequencies.

imately as independent noise that is being added to the
real and imaginary parts of the filter function.
Vander Lugt used a reference beam of coherent light
hi recording his complex filter on filnl. The function
recorded on film, which is non-negative, is

Digital processing systems
The Cooley-Tukey algorithm reduces the number of
basic operations in the calculation of discrete Fourier
transfonus from N2 to 2N 10~N, where N is the number
of sample points involved, and a basic operation is
defined to be a complex multiplication followed by a
the calculation of image spectra practical for digital
machines.
A device, which can act as an interface between
images on film and the digital computer, is needed as
auxiliary equipment. Precision flying-spot scanners,
such as the one built by Professor W. F. Schreiber at
M.LT., are ideal for this purpose. 3

Linear fiUering

Optical processing systems
The simplest optical processing system capable of
doing linear filtering uses two double-convex lenses and
two film transparencies aligned along a path of collimated coherent light. An input film is placed at the
front focal plane of the first lens, while the filter-function
transparency is placed at the back focal plane of the
first lens. The front focal plane of the second lens is
coincident with the back focal plane of the first lens.
When no errors are present, the light amplitude at the
back focal plane of the second lens, except for a possible
change of scale, is
g(x, y) =

11
00

00

-00

-00

F(u, v) H(u, v) e i2r (ux+ell) dudv ,
(8)

where H(u, v) is the filter function, and F(u, v) is the
Fourier transform of the input image.
Complex frequency -domain filters for optical filtering
may be made by varying the density of film according
to a desired magnitude function and varying the film
thickness to regulate phase. Practical difficUlties in
varying film thickness in this direct method have led to
the development of the methods of Vander LUgt, 4
Llhmann,6 and Lee.s These methods penuit complex
filtering using positive real filters. In the Lohmann and
direct methods, noise in the filter transparency can be
modeled approxinlately as independent white noise that
is being added to the magnitude and phase of the filter
function. For the methods of Vander Lugt. and Lee,
noise in the filter transparency can be modeled approx-

+ H(u, v)12
A2 + IH(u, v) 12 + AH*(u, v) ei2rGu

S(u, v) = IA ei2rau

=

+ AH(u, v) e- i21/"Gu,

(9)

where the asterisk denotes complex conjugation. The
impulse response of S(u, v) is
s(x, y) = A2o(x, y)

+ Rh(X, y) +

Ah( -x -a, -y)

+ Ah(x -

a, y),

(10)

where hex, y) is the impulse response of H(u, v), and
Rh(x, y) is the autocorrelation function of hex, y).
lVlultiplication of F(u, v) by S(u, v) corresponds to the
convolution of f(x, y) with sex, y). If f(x, y) and hex, y)
are of finite spread, then the constant a can be chosen to
produce the desired output g(x, y) without interference,
but displaced along the x-axis in the output plane.
The filter of Lohmann has only binary transmittance
values. Clear slits for light transmission are placed on
film to synthesize complex transmission functions. The
slit area determines the magnitude of light transmission.
Varying the slit position changes the phase of the light
transmitted through the slit.
Lee's method for producing complex filters on film is
similar to Lohmann's method, except that it provides
for a continuous variation in transmittance. Lee's filter
uses four non-negative sample points placed along a line
to construct a complex sample point. The positions of
the four sample points result in transmission phases
of 0, 7r/2, 7r, and 37r/2, respectively. By adjusting the
transmission amplitudes for the four points, any desired
complex transmittance can be obtained.

Digital processing systems
Linear filtering is accomplished on the digital computer by Fourier transformation, followed by multiplication, followed by Fourier inversion. Round-off error
occurs in this process. A crude model for the error is
independent white noise added during the computation.

Quantitative effects of frequency-domain errors

If independent noise is added to the real and imaginary
parts of F(u, v) [Equation (2)], then independent noise

Errors in Frequency-Domain Processing of Images

of the same power will be present in the reconstructed
image f(x, y) upon Fourier inversion. This is true
because of Parseval's theorem. In particular, independent white noise transforms to independent white
noise of the same power. Independent white noise added
to the magnitude of F(u, v) also results in contamination of f(x, y) by independent white noise. The model
of independent white noise can be used as a first
approximation for grain noise in film, and for round-off
error in digital computations.

f/>(u, v) for filters made by the direct method. Inaccuracy
in the slit positions has the same effect in the Lohmann
method.

When phase noise occurs, the filter function will be
given by
H(u, v) = \H(u, v)1

g(x, y) =

When Vander Lugt or Lee filters are used for linear
filtering, g(x, y) [Equation (8)] is contaminated by a
noise equal to

-00

L: L:

n(x, y) =

L: f~

where N(u, v) is the film grain noise added to H(u, v),
and is assumed to be independent. Under the condition
(12)

;

(13)

where R, is the autocorrelation function of the input
image f(x, y). Film grain noise causes errors in \H(u, v)\,
the magnitude of H(u, v), for the direct method filter,
while inaccuracy in the slit area has the same effect with
the Lohmann filter. In these cases the filter becomes
H(u, v) = {iH(u, v)1

+ X(u, v)}

ei(u, v) is unifonnly

4

3

e i (u, v) is the phase of H(u, v). If N(u, v) is
independent and obeys Equation (12), then the noise in
the filtered image g(x, y) = g(x, y) + n(x, y) is given by
n(x, y) =

F(u, v) H(u, v)

[e iN(u,lI)

where (}"2 is a positive constant, and the bar denotes
ensemble average, it may be shown that
n(x, y) n * (r, s) = (}"2R,(x - r, y - s),

(18)

The noise output of the system is

F(u, v) N(u, v) e i2r (ux+1I11) dudv ,
(11)

N(u, v) N*(a, (3) = a-2o(u - a, v - (3),

F(u, v) H(u, v) e iN (u.lI)

e i21r (ux+1JY) dudv.

00

Loooo 1

(17)

e i [2 THEN 'output G';
END FNO;
END CYES;
CNO: END SX;
END se;
END SY;

DECODING (WRITE)
INIT: 'input YIN';
IF SLIT THEN 'input eIN';
'input XIN';
IF NGL > 2 THEN 'input G';
SY: DO Y = YB BY LlY TO YE;
SETe:e = eIN;
IF Y = YIN THEN
SX: DO X = XB BY LlX TO XE;
IF X = XIN THEN
MOD: DO; 'modulate beam';
'input next coordinate';
IF 'coordinate is a new Y' THEN
NEWY:DO; IF SLIT THEN 'input eIN';
'input XIN';
IF NGL >2 THEN 'input G';
GO TO SETe;
END NEWY;
NOTNEWY:IFNGL >2 THEN 'inputG';
END MOD;
END SX;
END SY;
where (XB, YB) and (XE, YE) define a rectangular
area to be scanned at increments of (LlX, LlY). In
encoding each scan line is swept once for each of the
orientations between eB and eE, where Ae is the
orientation increment. Actual encoding takes place
only when the criteria is satisfied. In decoding, only
those scan lines which are specifically read in are swept
at the input orientation, and writing takes place (or
more generally, is initiated) only at those positions
which match the input coordinates.
NGL is the number of gray levels. If this number is
greater than two, additional encoding/ decoding is
necessary to obtain the gray levels. For NGL = 2,
the fact that the criteria is satisfied implies the gray
scale infonnation.
The most general coordinate string of an X-axis
scan has the form:
Y coordinate, 8, X coordinate; gray scale;

X coordinate, gray scale, X coordinate, gray
scale...
Y coordinate, e, X coordinate, gray scale, ...

Increlnent forlnat
The incremental string is composed of a sequence of
elements that can be interpreted either as a segment
vector or as an incremental command. The segment
vector is composed of two incremental displacements,
DX and DY, the corresponding signs for each displacement, SX and SY, and the 'beam condition.' DX specifies the number of unit cells the beam is to be displaced
in the X direction and DY specifies the number of unit
cells the beam is to be displaced in the Y direction.
The beam condition is given as being either on or off
during the move.
If (DX, DY) = (0, 0), the two signs, (SX, SY),
and the 'beam condition' are interpreted as an incremental command, where incremental commands have
the following semantics:

H
IT

Halt, close out the operation.
ITerate (magnify) the next segment vector.
The next two elements in the string should
be a count followed by a segment vector.
MB Modulate the Beam intensity (at a fixed
position).
NOP No OPeration
RGR Reset Grid Resolution
RSO Reset Stencil Orientation
RSS Reset Stencil Size and/or shape
RVB Reset Vector Begin point

The IT command with its count is equivalent to having
the same segment vector appear sequentially in the
string by the number of times given in the count byte.
If the displacement is (0, 0) the IT command is ignored.
The four commands that reset parameter values are
followed by string elements containing the new parameter values. The element format is the same as that
defined for the initializing parameter string.
For the incremental format (XD, YD) and (XE,
YE) are interpreted as defining a file area, outside of
which no recording (film) or displaying will be allowed
to take place. (XB, YB) becomes the initial point from
which the beam will start the first segment vector.
Figure 2 shows the use of incr~mental vectors with
the command RSS inserted at point P (between vectors
(2,2) and (3,1» and with command RGR inserted at
point Q,

Parametic Description of Scan-Display System

(XB)"B)

(6,1)

R

---IDEALIZED

SEGMENT

- - - - - . INCREMENT PATH
(IF DIFFERENT THAN IDEAL)

Figure 2-Segment vector plotting. Note change in stencil size
at P and change in resolution (unit cell) at Q

191

gross coordinate position (which can be interpreted
as a local 'benchmark'). One then has a localized grid
of mesh 2bl1+br where b r is the number of bits in the
vernier counter used to extend the gross resolution.
The smallest resolvable square has sides of 2- Cbfl+b r )
units and is termed a vernier basic cell. The remaining
bo bits in the vernier counter define the gross-vernier
overlap, or the maximum vernier window as having sides
of 2bo gross basic cells (see Figure 3) or 2Cbo-bg ) upjts.
The above discussion defines the design parameters
that determine maximum position resolution. Not all
applications warrant this maximum resolution. More
importantly one cannot contrive efficient scanningrecognition algorithms without a range of resolution
options. One clearly wants. independent choices of
resolution for the two axes, either because the application warrants it, or becuase the format warrants it, as in
the case when scanning in the coordinate format using
a slit-like sampling area.
The parameters p and q specify the sampling resolution as every 2p basic cells in the X -direction and
every 211 basic cells in the Y -direction:

ax

Resolution, sampling and scanning parameters

= 2p

basic cells

units

= 2pCb l1+k)

. Resolution
In order to encode a digital representation of an image
it is necessary to impose a grid and coordinate system
upon it. It is convenient to conceive the total image or
raster area as a unit square and to interpret the addressable positions of the image as fractional coordinates
ranging between 0 and 1. The mesh of the grid
superimposed on this range is then 2bfl where b g is the
number of bits used to specify coordinate position.
The smallest resolvable square has sides of frbfl units
and is termed a gross basic cell.
The aspect ratio of the raster area need not be 1 :
1. The physical interpretation of the basic cell will
more generally be a rectangle, hence the effective resolution along one axis may differ from that along the
other.
The adopted coordinate system-left-handed rectangular-is a natural one for most textual material
and also corresponds to standard video practice of
left-to-right top-to-bottom scanning.
In concept one achieves the physical limit of resolution by choosing b g sufficiently large. In practice this
is difficult to implement and one distinguishes between
a gross position counter specified by b g , and a vernier
position COlllter specified by b v • The vernier counter
has a sign bit, Stl, and is interpreted as a signed position
relative to the gross position. This is equivalent to
overlaying a vernier grid in the immediate vicinity of a

(1)
(2)

o

x .....

1

V

I
B

y

+

,

H±t- +

Ey

I

-J

L/

X8:

.101 •.. 1011101
;

GROSS COUNTER
bg >bo

I

I
I
I
I

I
I
I
I

I

I

1+111111111
-"'-"--y-J
bo

br

VERNIER COUNTER

bo =2
b,=2

Figure 3-Maximum vernier 'window area with respect to B
coordinate. Shown is an overlap of two bits (bo) and maximum
local resolution for a resolution extension of two bits (b,.)

Spring Joint Computer Conference, 1969

192

The gross/vernier selection determines k as O/b r • The
smallest resolvable rectangle is flX by flY units and is
termed the unit cell.
rr'l,.",
.L .l.lCi

~",,,~.j.~,,,~
n""''''-/-e''' ;'"
;nn
...a'YYlentarl
Ilt thp
nth
pV~~lJ~V.l~
\JVUJ..L\J .J.
.1.01
.J..1..LV.l.V.l...L.I.
UV'-A.
","",v
v ................ ..t'
.L....

r-----,-,---------~----------4~~

'-

-

~e

X

{'IT'
......
.&.

qth significant position of the gross/vernier counter,
hence the number of significant position bits is:

x
raster gross:
bg - p
raster vernier: b g + b r

y
-

p

For the coordinate representation it is desirable to
increase gross sampling resolution along the scan axis
while incrementing the position counter at the pth significant position as described above. This can be done
by interpolating between counter increments and
concatenating the be interpolation bits to the b g - P
significant counter bits. One then has for the coordinate
resolution:
coordinate

gross: b g

+ be -

,
y

SLIT:

SPOT:
Ls= MINIMUM
Ws =DIAMETER

p

significant

bits.

e

RELEVANT

A natural choice is to make be = b r since b r reflects the
physical limit of resolution.

Sample encoding
The maximum number of image density states for a
read command or recording beam intensity states for a
write command are indicated by the gray scale parameter, n. The number of encoded bits is interpreted
as 2", hence the number of possible states as 22.. , The
maximum value of n is specified as n max .
Triggering or filtering of output information may
be done by either a standa.rd level diRcriminator or by
a specially designed plug-in unit. The value "assigned
to the parameter T chooses between these two.
The parameter B8 will distinguish between the choice
of a standard size spot (~q gross basic cell in diameter),
and a slit or non-standard spot size. If the non-standard
option is taken, then the parameters u and v define
the sample width and length as 41.£ and 2t1 gross basic
cells respectively. The range of circular spot sizes can
be specified by u with v = O.
If the sample area is slit-like then the orientation
becomes significant. The unit of angle is the circle,
or radians/21r. The angular resolution is 2-b a units
where b a is the number of bits used to specify an angle.
The angular sweep Begin-End coordinates, (8B, 8E),
specify the range over which incrementing is to be
accomplished. The increment is defined by the parameter z as 8 = 2z-b a units. The slit is swept the length
of a scan line for each value of 8 in the specified range.

e IRRELEVANT

Figure 4-81itjSpot. geomet.ry

Figure 4 illustrates the /l:eometrical definition and angular reference.

Scanning rate
Sweep velocity will in general be limited by the
following:
1. positional digital-to-analog response time
2. maximum channel data transfer rate
3. number or bits of gray scale eucoding/ decodin~

Sweep velocity can generally be expressed as a function of the following parameters (see Appendix B),
where a constant clock rate for incrementing the positional counter is assumed:

vs =

C1 .

f(p,q,A) , g(DF, K, n, n max ).

Here f is determined by the scan axis and unit cell
selection:
f(p,q,A)

=

(I-A) . 2P .

ox +

A . 2q

•

oy.

The maximum continuous data rate is required for
the Raster format with n = n max , where g can be normalized as
g = Z-"max'

Parametic Description of Scan-Display System

The data per sample are higher for the coordinate
format, but the average data rate is normally less than
for Raster. (Otherwise the nnage would be more optimally encoded in a raster format.) Buffering is needed
to handle local bursts of perhaps three or four consecutive samples. The amount of data for coordinate representation are essentially (though not absolutely)
independent of the number of bits of gray scale encoding/ decoding.
For an X-axis scau at constant sample rate one then
has
Vs

=

C1 •

Z-nmax · 2P . 5x.

C1 can then be determined from the clock frequency.
This equation yields a constant sample rate with the
Raster format for any value of n.
Since the data per sample is 2n bits, one obtains a
constant data rate by introducing the quantity nmax - n
in the exponent yielding:

Here instead of incrementing the position counter
at the pth significant position, the burden on the positional D / A conversion is appreciably lessened if one
increments only at the [p + (nmax - n) ]th significant
position and interpolates to obtanl samples at the
(2 nmax-n -1) positions between counter increments.
The constant data/sample rate option for a given
resolution is then determined by the parameter K.

quence. The scan axis is specified by A as X or Y, and
S selects the scan line sequence as interlaced or sequential. These two parameters a10ng with the B-E combination completely determine the sampling sequence.
One obviously starts with the Begin coordinate and
terminates with the End coordinate, determining the
direction of sampling along a scan line. The hexagonal!
rectangular lattice option is defined by L as described
below.
The matrices in Figures 5 and 6 illustrate the sampling sequences for a scan direction parallel to the Xaxis on a Rectangular Lattice. The position of point
No.1 in the lattices is specified by the Begin Coordinates.
The End Coordinates specify point No. 42 in the Sequential case (Fi~e 5) and point No. 15 in the Interlaced (Figure 6) case. Since the Begin and End coordinates are constrained to be multiples of AX and
AY they will always be member points of the Lattice.
Figure 7 illustrates the relative positioning of points
and their sampling sequence for the two scan directions
on Hexagonal Lattices when line sampling is sequential.
The Hexagonal Lattice is obtained by shifting the
lattice points of odd numbered scan lines in the corresponding Rectangular Format by an amount AX/2
(or AY /2) along the positive scan axis. Otherwise hexagonal formats are analogous to their rectangular counterparts.
The Interlace option and the adopted coordinate
system are particularly suited for communication with
a standard video network through an analog-to-digital
interface. Figure 6 shows the relation between the

\Vindowarea
The term window was introduced above in defining
the maximum area that can be covered in a single operation with vernier resolution. Two pairs of coordinates
serve to specify the portion of an image to be scanned,
encoded and displayed. They are termed the Begin
coordinates (XB, YB), and End coordinates (XE,
YE), and are interpreted as defining diagonally opposed
corners of a rectangle. Since the position counters may
be decremented as well as incremented anyone of four
B-E combinations may be chosen to specify the same
window area. This feature and the coupled-uncoupled
option of the monitor position counters allow the Rotation Group transformations described below. The
coordinates must be multiples of (~X, ~ Y).

Scan format (lattice and sequence)

. . .

2

·

3

4

5

•

8

Y!

15

·

22

.

6

7

•

·
·

0

14

j

6X

1

O'E]
L
CELL

21

2

28
3

.

·

35

36

42

29

•

•

4

5

1

SCAN LINE NUMBER
SEQUENTIAL: LINE SEQUENCE IS

The scan fonnat, determined by the parameters L,
S and A, imposes a Lattice upon the grid in terms of
the un'tt cell and specifies the scan line sampling se-

193

0,1,2,3,4,5

Figure 5-Sequential scan along X-axis using a rectangular lattir·e.
(t1 Y = t1X)

194

Spring Joint Computer Conference, 1969

. .
I

FIELD 2

2

I
I

o

o

o

•

2

•

·)V
•

,
o

vr

L___

21

.35

SCAN
LINE
NUMBER

:
G)

2~---3--__4-----5-----6~.4--~1
,u--~---r21

.1

LINE NUMBER_x'_"_ _ _ _ __

INTERLACED: LINE SEQUENCE IS 0.2,4.1.3.5

31.

16!

I

I

~
.17

.3

--~--

.4

.1-

.5

.25

Figure 6---Interlaced scan along X-axis using a rectangular lattice.
(b)

35.

•30

10

(~y = ~X)

PARALLEL TO

V- AXIS

Figure 7-Sequential scan along (a) X-axis, and (b) Y-axis using
a hexagonal lattice. The hexagons around point 11 in (a) and
point 17 in (b) illustrate neighbor points. The dotted
rectangle.."l Rhow neighbor points in the eorresponding
rectangular lattice. (~y = ~X)

.
2

o

3

't----

4

5

. .

6

7

1

I
I

I

e

1
1
I

14

.~
i

I
I

I
I

V ideo compatibility

I

.

.. --I
I

15

2

When interfaced by a video scan converter the video
can be handled as a scanner. However, the
scan converter is not essential since the S-J\I-V Controller can be designed to satisfy the constraints of the
video systems. The following discussion uses the parameter i to identify the v-ideo system within the network;

4

i

(a) PARALLEL TO X-AXIS

.2

fields and the sample points for the interlace option.
Lines have been drawn between points surrounding
point No. 11 in Figures 7(a) and 8 and point No. 17
in Figure 7 (b) to illustrate the concept of neighbor
points. An interior point of the Hexagonal Lattice has
6 neighbor points whereas that of the Rectangular has
8. Since the Hexagonal Lattice is not regular (it is
rhombic), although it is nearly so for dX = d Y (see
Figure 7), neighbor points are not all equidistant from
their interior point; but they always partition by
distance into two sets of 4 and 2 points each. Those
for the Rectangular Lattice partition generally into
three sets of 4, 2 and 2 points each, and for dX = d Y
the two sets of 2 and 2 become a single set of 4. Compare
Figure 8 with Figure 7.

2

3

·6

n~-twork

I

0
r -_________

30

4

~SCAN

o?

.29

3

10

x

Q9.11

'U.42Xj
· .

•
.22

2S

I

~

7

6

I

I

15

19

18

· .

5

r---1:~

8

17
o

4

3

.

21

I
3

I

2.2

•

•

LSCAN LINE NUMBER

Figure 8--8ame as Figure 7 (a) with ~ Y =

2~X

Parametic Description of Scan-Display System

it assumes the controlJer-video link to be direct and
develops the corresponding constraints.
Since the viedo 1ine sweep timf, Llt(i), is a fixed
parameter the number of data bits that can be transferred to or from core per full scan line is coilstrained
by the I/O channel capacity, where the maximum bit
transfer rate is f b• A buffer will allow a 'burst-mode'
sampling for some fractional part of the scan linehence higher resolution in sampling a vertical band can
be achieved.
The Incremental string cannot be passed directly to
video; it must first be passed to a scan converter.
The Coordinate otring with video has a resolution
along the scan line equivalent to Raster resolution
with n = nmax , hence the scan axis counter increment,
LlC, is given by:
Raster with constant data rate option:

Raster with constant sample rate and Coordinate:

Maximizing position resolution minimizes gray scale
resolution and vice versa. S(j,n) achieves its maximum
value for n = 0:

= S(j,O) =

Smax (j)

2'

A 1-1 correspondence between a full scan line at
video and the S-~f-V control grid requires:
S(j ,n) . LlX = 2bg basic cells.

One would nonnally choose the constant data rate
option. The Coordinate string resolution can only be
locally maintained because the buffer storage limits
the number of succe.3sive saIPples in contiguou~ unit
cells. This is not a severe restriction since the coordinate
representation is not very meaningful unless the image
is rather sparse. Note that orientation sampling is
meaningless with video.
The entire video discussion is from the point of view
of the Rastel' string representation. The stling win have
existence only when core memory participates; otherwise there is only the analog signal transfer between
the other three media. The resolution results are valid
independently of the point of view.

Substituting for S(j,n) from equation (4) yields:

(6)

This defines the achievable video resolution along
Table I-Inherent characteristics of three video systems and
maximum sampling resolution, Smax(j) , as constrained by
other media

i

N(~)

Horizontal (X-axis) resolution

To achieve a maximal uniform resolution across a
full scan line it is necessary to maintain a constant
data rate. We choose the largest j such that
(3)

and hence maximize and fix the number of bits in a
full line of sampling. Position resolution and gray scale
resolution are not independent: the number of bits per
sample is 2 hence equation (1) constrains the number
of samples in a full line to be

t1tCL)

}L-sec
~

56

1

525

2

1536S

~520

3

1536F

~

43

Smox( i )

1

512

9

4096

12

256

8

,

S(j,n)

= 2i- n •

(5)

Table I shows values of Smax(j) for three different
video systems. Parameter values used in the calculation
are given in Appendix C. If a window contains only a
fractional part of a scan line, then only a corresponding
fractional part of S(j,n) samples can he obtained along
each scan line.
Sampling at the position counter stepping frequency,
fe, maintains the aforementioned data rate for an
2 n max bit gray scale datum. An interpolation counter
is used to achieve the rate for other choices of image
density resolution with the constant data rate option:

LlC = 2P.

71

195

(4)

F= FAST SCAN
S= SLOW SCAN

196

Spring Joint Computer Conference, 1969

Table II-Maximum sampling resolution and interdependence of
position and gray scale resolutions as constrained by media
characteristics. The main entry is the maximum number
of samples per video scan line, S(j, n),and the value
in parentheses is the corresponding maximum
value of aX, (ax)mlU:(j,n)

which may be restated as:
CLlY) 17

g(j)

n

8

64
(64)
512
(8 )

( !6 )

(8 )

12

128
(32)
2048. 1024
(4 )
(2 )
64
128
(32) I ( 64)
256

512

9

3

2

I

0

4096
( 1)
256
(16)

32

(128)

4

2

1

I

f(j) . 2Il+ n -p,

where
f(j)

j

=

= r,,/r

B

•

N(i) . 2-i.

As in the discussion of horizontal resolution we wish
to approximate by powers of 2, and determine a g(j)
such that

0
-I

The video line sampling freqw:mcy is then determined
at the 8-l\1-V controller from

3

(LlY)" = 2Il+ n +oW-p

-

8

since the four terms in the exponent are defined by the
parameter assignments.

2 n , bits of gray scale

Media selection
scan lines as well as the largest useable sampling increment that may be associated with the 8-~1-V control
grid scan axis, Table II illustrates the interdependence
of position and gray scale resolution for the three video
systems of Table L It contains the values of 8(j,n) as
constrained by equation (4), and in parentheses the
corresponding maximum values of SX as given by
equation (6). All parameter values used are listed in
Appendix C. The function g(j) is explained in the
following section.

Vertical (Y-axis) resolution

::.vIedia selection is determined by the parameters
F, V and C. The choice of a Read or Write command
is then determined from the source-destination matrix
shown in Figure 9. Of the sixteen possible states for
F , V, C and ReadjW rite ten are allowed as meaningful
or useful, and this may be succinctly stated as:
States
4

4

Having determined the video resolution along a scan
line we now determine the vertical sampling so as to
achieve a unit cell match to the 8-::.YI-V control grid.
Assuming an X-axis scan at the controller, this constraint requires the video line sampling frequency to be

Source

(FEBV)
F
V
C

Destination

Command

(CEBC)
V.C
F.C
(FEBF) . (VEBV) .

WRITE
WRITE

Figure

15
16
16
17

whereEBmeans exclusive OR. As indicated these states
are illustrated in Figures 15-17. A destination medium
always exists since the monitor participates in all
DESTINATION

(LlY)t,

=

r"
-rs

N(i) LlY
. -8('
)' AV'
J,n LlA.

(7)

where r8 and rv are the aspect ratios at the control
grid ltnd video, respectively. N(i) is the number of
lines per video frame. The unit cell resolution ratio at
the 8-NI-V control grid is LlX/LlY, and the corresponding video resolution ratio is 1/8(j,n) N(i)/(.1Y)v. Using
equations (1), (2) and (4) equation (7) can be written as

SCANNER

SOURCE

VIDEO

r-N~R~

l~:RY'

MONITOR

MEMORY

:« W~ ~
R

R

W

W-WRITE

Figure 9-Command matrix. Read/Write selection as a function
of Relected media and desired transfer direction

Parametic Description of Scan-Display System

operations. Whenever core memory (C) is not the
image source, display at the monitor or video can be
indefinitely repeated by setting the Regeneration parameter, J.
When transferring an image between two media, it
is necessary to consider:
a. the XjY aspect ratios, and
b. the XjY resolution ratios.
If either of these ratios differ, then a contraction quite
independent of any magnification can take place along
one of the axes. Both sources of image distortion may
be averted by matching aspect ratios of the unit cell at
source and destination media.. Since several media may
be involved it is useful to adopt the concept of an S-1\1V control grid and coordinate system through which
any inter-media transfer must pass, as illustrated in
Figures 14 through 17. One then forces a match between
each medium and the S-l\I-V control grid. All position
and resolution specifications in the parameters can be
interpreted as referring to the S-M-V control grid and
coordinate system. They must be specified with a
particular medium (or media) in mind, however, and
must be compatible with its associated characteristics.
Scanner and monitor are completely dominated by
the S-l\I-V Controller, hence the unit cell match is
easily accomplished. The same is true of core memory
as a destination mediwn. As a source medium the core
memory unit cell match is under program control, and
it is therefore necessary to associate inviolate unit cell
as well as other parameter information with any string
representation. Except for initiating a video scan, the
link between S-~l-V Control and video is basically an
information transfer link. The video match is effectively
accomplished by selectively transferring information
from video (say every other scan line) and by holding
back information to video (say blanking every other
scan line) by employing (.1Y)v as discussed in the
section on Vertical Resolution.
.
Extending this "match-to-control" concept allows
all the transformations (rotation, magnification and
translation) discussed in the following sections as well
as the dual interpretations of video as a source medium.
The entire transformation discussion is from the
point of view of gross resolution. Vernier resolution
differs basically in having an inherent magnification
of 211,. to both xfonitor and Video, and in having a
limited window area.
Monitor transformations

Information is communicated to the monitor during
each of the S-l\I-V operations. The area of interest
in an image is specified by a 'window' at the S-~l-V

197

control grid delineated by the Begin and End Coordinates. Three types of transformations may be applied
to the window as viewed at the monitor: rotation,
magnification and translation.

Rotation
The Rotation parameter, G, allows the option of:
(Rl) slaving the monitor to the S-1\1:-V Controller
grid in scan axis and direction or,
(R2) choosing the scan axis and direction at the
Monitor to be parallel to the X-axis and
incrementing irrespective of the Controller
choices.
When option (R2) is taken then scanning the X-axis
at the Controller grid obtains the transformations
shown in Figure 10, whereas scanning the Y-axis
yields the transformations shown in Figure 11. The
choice of a B-E orientation fixes the scan direction and
the initial scan line, hence selects one of the four
transformations. The four transformations in Figure
10 are called the "four group" of rotational synunetries
on the rectangle. The eight transformations in Figures
10 and 11 define the "Klein Rotation Group" of
symmetries on the square.

Magnification
The window displayed at the monitor can be magnified by factors of 2 with the parameter h subject to
the combined restrictions:

The underlying assumption is that the range of resolution options on p and q is identical at monitor and
scanner, and that the unit cell at monitor is magnified
by m = 2h.
One naturally constrains the choice of h to keep
the magnified window from exceeding the raster area:

m'

YB-YE ~ 1.
{I XB-XEI}

This restriction is refined in the discussion below on
translation.

Translation
Translation of the window at the monitor may be
achieved with the M on~tor Displacement Coordinates.

Spring Joint Computer Conference, 1969

198

TRANSFORMATION

SCAN

o

DISPLAY

X--+

--_:.!.--,-=------,

8

It
I

p'

IDENTITY

I

I

I

.~

II
.
[II

180ROTATION

8'

REFLECTION

11

8
8

11

I
E

VERTICAL

E

II

~.

8

REFlECTICW

I

HOiI~

i
I

5-M-V
CONTROL

E

E

,.

~

I

f4

I

O-r----__

r-I

E'

J

'

,,'"

I
y

~

I
I
I
I

I
I
L--"""'~~E

I~I------------------~

DARK LINE AND ARROW SHOW SCAN
AXIS AND DIRECTION

Figure l(}-Group transfonnations effected by the four different
Begin-End coordinate orientations with X-axis scan. (G = 1)
MONITOR

DISPLAY

TRANSFORMATION
8

II

,K

.~.

I
II
...• II ·r

REFLECTION
K-K

E

8'

REFLECTION

L~L

B
B

E

1

p

vf4
D

90- CCW

ROTATION

B
E
m

E'

E

If
I I

]
I

9O-CW

ROTATION

-

DISPLACEMENT}
BEGIN
COORDINATES
END
MONITOR MAGNIFICATION

-

-

Figure 12-Image translation and magnification at the monitor

B
IY4RK LINE AND ARROW SHOW SCAN
AXIS AND DIRECTION

Figure II-Same as Figure 10 with Y-axis scan. (G

=

1)

As shown in Figure 12, D transforms into (0, 0) at the
monitor, hence B is repositioned accordingly.
If a magnification m is superimposed on the translation it affects the area delineated by the D-E coordinates, hence the combined transformation is completely
defined as operating on the two vectors u and v:
1. translate the tail of u to (0,0) and
2. magnify the length of u and of v by m.

The four allowed orientations of D, Band E are
shown in Figure 13. The implied const.raint is that in
case (a) D ::; B ::;E with a corresponding interpretation
for the other three cases. D always transforms into the

corresponding corner position at the monitor with
Rotation option (R1). For Rotation option (R2), D goes
to (0, 0) at the monitor in all cases.
For proper centering, one must choose (XD, YD)
such that
m

(IXB -xEI +21xD -xBI ) =

1

m

(IYB - YEI +21YD -

YBI ) =

1.

and

Complete positioning freedom is not always possible
when combined with one of the· rotation transformations, e.g., when the window is very close to the edge
of the grid and the chosen tran.8formation requires D
to be on the edge side of the window.

Parametic Description of Scan-Display System

x

0
~

CONTROL
y
GRID

~

0

r-----~
I

0t"-----,
I B
:

U~E

I

~B!

_oJ

E

CORE MEMORY

S-M-V CONTROL

(b)

(0)

199

SCANNER

S-M-V
CONTROL
GRID

Figure 14-Monitor totally slaved to the source media

MONITOR

EWgj~~

As shown in Figure 14, the Controller can then avoid
the time-consuming redundancy of the transformation
steps inherent in a sequence of small windows.

I

I
I

I

0'
(e)

(d)

Figure 13-Four allowed orientations of D, Band E coordinates
with the corresponding monitor interpretation. (G = 0)

Totally slaved to scanner
When tracking a line or a boundary, by scanning a
sequence of windows, a 1-1 correspondence between
Monitor and source is desirable; otherwise the relative
positioning of windows at the source is not reflected
at the Monitor, and the tracking procedure cannot be
viewed. This can of course be achieved with the proper
parameter assignments as a standard transfonnation
but one would like to avoid the time involved in doing
so. Since the wi~dow will be small the scanning time
can be significantly reduced by recognizing a special
case. The following natural setting for the parameters
listed can be interpreted as defining the special case:
1.
2.
3.
4.

(XD, YD) = (0, 0), no translation
gross resolution
no rotation, option (Rl)
no magnification

Totally slaved to video

As indicated in, Figure 14, video is inc1uded in the
total slaving concept. For video this is accomp1ished
by replacing constraint (4) in the previous section with
the following:
(4')

h·

ax = axmax (j,n).

At most one window can be scanned per video frame,
thereby limiting the repetition rate.

Video transformations
The video network, unlike the monitors, can act
both as a source and as a destination. A window,
specified by the Begin and End coordinates at the
S-M-V control grid, determines the area of interest.
Transfonnations similar to those at the monitor can
be effected within the limits of the video constraints.

Source medium options
It is useful to distinguish two interpretations of
video as a source medium:

Spring Joint Computer Conference., 1969

200

r----------,
I
I

(81) l-lcorrespondence between video and the 8-MV control grid (excluding rotation), thereby
allowing translation and magnification of a
window to the monitor;

I

I

,
I

I
,

,

'

I
I
,
,

I
I
I
I

L~~_E_ ~~~~~: J

(82) 1-1 correspondence between video and some
portion of the 8-M-V control grid, effectively
allowing translation and demagnification of a
window to film.

......
~E

X2

hy

D

..

8

Options (81) and (82) are illustratfd in Figures 15
and 16 respectively.

S-M-V CONTROL

~-:e-'"

l~E

.....

...

..

0'
8'

...

~

xi hy

SCANNER

VIDEO

IX2h

Rotation
0'

When video acts as a destination medium, the
transformations are effected in the same manner as
they are to the monitor under option (R2). Because
the video scan axis and direction are fixed, option (Rl)
never applies.
When video participates as a source medium the role
is reversed and one always gets the inverse transformation to the 8-M-V control grid. If option (R2) is
chosen for the monitor the two transformations cancel
(into and then out from the control grid)-effectively
yielding the identity transformation to the monitor.

e'

f7777:l

I
I

Figure 16-Transmitting between scanner and video. Display
at the monitor 'with h = h"

Magnification and demagnification
Equation (6) defines (aJe)max (j,n), the largest useable
Choosing ax < (ax)max (j,n) allows So video

ax.

I

0'
D

~E

I

---~~,

o~-- ...

8~

l~
Figure 17-Transmitting from core memory to one or more
media. If to video, h = 11.

SCANNER

D"

---~,
~
:

8

I

magnification of
mv(j,n)

= (ax)~ (j,n) =

2hv(j,n)

J

~

80

Figure la-Magnifying a winduw at the munitor and/or
transmitting to core memory

hv(j,n)

=b

g -

j

+

n - p = Pmax (j,n) - p .

Paranletic Description of Scan-Display System

When video is a source medium m is a demagnification, and when video is a destination medium mv is
a magnification.
In the (SI) interpretation of video as a source medium
..:lX = (..:lX)max is assumed, and the monitor magnification is achieved in the same manner as when the
source is core memory or film scanner.
p

Translation
When video is a destination medium translation is
effected in the same way as it is at the monitor with
the rotation option (R2); (XD, YD) at the S-.:.\f-V
control grid transforms into (0,. 0) at the video. For
proper centering (XD, YD) is chosen so that:
mi>(IXB-XEI
mv(IYB-YEI

+ 2IXD-XBI) = S(j,n)

. ..:lX ~ 1,

+ 2IYD-YBj) = ll~~y~u(i) ~

1,

where Nu(i) is the number of useable lines per video
frame (or maximum (llY)l1 steps).
With video as a source medium translation to the
monitor is accomplished by associating (0, 0) at the
video with (0, 0) at the S-M-V control grid. Translation to the monitor then takes place in the usual way.
This is option (SI) and is illUstrated in Figure 15.
Option (S2) is accomplished by associating (0, 0) at the
video with (XD, YD) at the S-M-V control grid and is
illustrated in Figure 16. Translation to film then takes
place as the inverse of the translation effected when
the transfer is from film to video. Note that translation
to monitor and film cannot be effected simultaneously;
the options (SI) and (S2). are mutually exclusive as far
as translation is concerned-hence the distinction.

Totally slaved as a destination
Video is not likely to be useful for display under the
totally slaved concept, since this would constrain the
sampling increment to be
ilX = AXmax(j,n).

SUMMARY
This paper has developed the parametric description
of a general purpose Scan/Display System for image
digitization and display. Central to the system is the
S-~1-V Controller which can service either simultaneously or individually three distinct media: film,
closed-drcuit television and incrementally-driven CRT
displays. An adjunct of the system is a Video Com-

201

munications Net to provide both high and commercial
resolution service to remote users.

Media compatibility
The S-M-V Controller acts as a media-media interface that identifies the necessary information transfer
constraints or rejects the operat~on request as one
demanding inconsistent parameter assignments. Transfer constraints considered include XjY resolution
ratios, aspect ratios and line sweep times of the media,
and D-A/A-D conversion times. A constant data rate
option allows operation at I/O channel capacity for
all choices of gray scale resolution.
The digital encoding of an image generated in a
scanning operation can be retransmitted to the S-M-V
Controller for output (display)-and on any of the
three available media.

Rasters
By associating (X,Y) positions with binary counter
value pairs the controller can generate a family of the
two-dimensional regular lattices-rectangular and hexagonal. X and Y resolutions are independen,tly variable,
the allowed resolution values are in geometric progression and correspond to changes in counter incrementing position. A selected "window" of the full
image can be specified.

Sampling/display strategies
Three sampling formats (Raster, Coordinate and
Incremental) allow a variety of sampling/display
strategies. Raster format provides uniform sampling
of alllat~ice positions. For coordinate format however,
sampling takes place only at those lattice positions
where the image satisfies some criteria prescribed by
selection of a triggering/filtering circuit.
Incremental format is provided for segment vector
plotting. Conunands are provided for setting the
starting point, line width and plotting resolution.
Segment iteration can be specified.
The sampling beam stencil is variable in size, shape
and orientation. The shape options are spot/slit. The
slit option includes orientation resolution and range.

Metrological facilities
An optional local extension of position resolution
can be specified through a gross/vernier counter selection. With the vernier option selected, the gross counters define a benclunark while the vernier counters
represent a local displacement. Using this technique,

202

Spring Joint Computer Conference, 1969

positional resolution of 1: 30,000 is currently attainable
in flying spot scanning.

Implementation
The 11liac III computet' .10 employs a scan/display
system with parameters as specified in Appendix C
of this paper.
Except for the video scan converter, the microimage
storage and the video storage, the scan/display system
is anticipated to be operationa1 by Sununer 1969.
ACKNOWLEDGMENT
Many'stimulating discussions with members of the
Illiac III staff aided in the formulation of concepts
developed in this paper. :NIr. Robert C ...<\....~endola has
contributed significantly to the Video Network specifications and to scanner optical design. Dr. Kenneth
J. Breeding participated in the first design of a scanner
controller which was subsequently expanded into the
S-M-V controller described in this paper.
A description of the analog and digital logic design
of the scan/display system is now being prepared for
publication by Dr. James L. Divilbiss and Mr. Ronald
G. lVlartin, respectively.
The authors wish to thank ~1r. John H. Otten for
preparing the illustrations and :\1rs. Donna J. Stutz
for typing the paper.
REFERENCES

:l

3

4

f)

6

L A DUNN L N GOYAL B H McCORMICK
V G TARESKI
S-M-V programming manual
Department of Computer Science University of Illinois
Urbana Illinois March 1968
D M COSTIGA:.l
Resolution co;~siderations affecting the electrical transrnission
of technical documents by scanning process
National Microfilm Association Jour Vol 1 No 3 Spring 1968
PEPR--a hardware description
Emerging Concepts in Computer Graphics Don Secrest and
Jurg Nievergelt (Eds) W A BenjamL.TJ. Inc New York 1968
R CLARK W F MILLER
Computer-based data analysis systems
Methods in Computational Physics Vol 5 Berni Adler
Sidney Fernbach Manuel Rotenberg (Eds)
Academic Press N ew York 1966
R B M ARR G RABINOWITZ
A software approach to the automatic scanning of digitized
bubble chamber photographs
Methods in Computational Physics Vol 5 Berni Adler
Sidney Fernbach Manuel Rotenberg (Eds)
Academic Press N ew York 1966
J VANDER LANS .J L PELLEGRIX
H J SLETTENHAAR
The hummingbird film digitizer system

SLAC Report No 82 Stanford Linear Accelerator Center
Stanford University Stanford California March 1968
7 R S LEDLEY L S ROTOLO T J GOLAB
J D JACOBSEN M D GINSBERG J B WILSON
FIDAC: Film input to digital automatic compuier and
associated syntax-directed pattern recognition programming
system
Optical and Electro-optical Information Processing Teppep
J Berkowitz D Clapp L Koester C and Vanderburgh Jr
(Eds) 1\1 I T Press Cambridge Massachusetts 1965 Chap 33
8 H KAZMIERCZACK F HOLDERMANN
The karlsruhe system for automatic photointerpretation
Pictorial Pattern Recognition G C Cheng R S Ledley
Donald K Pollock and A Rosenfeld (Eds)
Thompson Book Co Washington DC 1968
9 B H McCORMICK
Advances in the development of image processing hardware
Image Processing in Biological Science Ramsey D M
(Ed) University of California Press 1968 in press
10 B H McCORMICK
The illinois pattern recognition computer--illiac J I I
IEEE Transactions on Electronic Computers Vol EC-12
No 5 December 1963

APPENDIX A-DEVICE SPECIFICATIONS
Scanners

The scanners are flying spot scanning systems with
of the spot into a line element to achieve a slit mode.
All scanners are capable of either scanning from developed film or photographing onto unexposed film. The
optical path of the beam is split, with one path transversing the film and the other path through a reference
grid to establish stability against engraved fiducial
marks.
Several types of media transports are provided to
handle the projected range of problems. A 70 mm.
scanner is provided primarily for 70 mm. negative
bubble chamber fihn. Here the format of the raster is
2.362 inches X 3.522 inches, and the minimum spot
size is approximately 0.001 inch at the film. Due to
the 1ength of the frame to be scanned, scanning is done
in two steps. The two horizontal halves of the frame
are scanned successively with a 4 mm. overlap to
establish half-frame continuity. Large motors are used
for slew and gross positioning of the film and a small
digital stepper motor is used for fine positioning of the
frame. Frame position sensing is accomplished by using
the digital stepper motor as a tachometer and by
counting sprocket holes. Total film capacity is 1000
feet.
A scanner for handling 47 mm. film is similar to the
70 nun. transport design except for the following:
The fi1m format is different. A friction drive is used
on the digital stepper motor, since the film is un-

Parametic Description of Scan-Display System

sprocketed. The frame position is determined by sensing
small index blocks at the lower edge of the fihn using a
fibre-optics light guide and a photodiode.
The microform scanner contains three units. The
first is a 35 mm. full frame digitally controlled camera
which can read light through the fihn both negative
and positive. The second unit contains a 16 mm.
Bolex camera for making computer-generated black
and white movies and a modified 16 rom. film editor
for scanning 16 rom. film of all types. The third unit
is a microfiche transport mechanism for scanning and
producing a single microfic.he in the 72 image COSATI
format. For the three different units the C.R.T. raster
is adjusted optically to fit the particular frame size.
A fourth type of scanner is built around a microscope
with a digitally controlled automatic stage. Positional
accuracies are on the order of ± 2 microns, and the
maximum slide area coverage is 1.2 inches X 1.2 inches.
Variable reduction is available from a four objective
rotating turret. Full visual observation is available to
an operator.

Monitors
The monitors consist of 21-inch cathode ray tubes
controlled in a manner similar to the scanner C.R.T.'s;
viz., digital position counters control the spot location
through accurate, high-speed digital-to-analog converters. The monitor counters are digitally controlled
directly from the S-M-V Controller via an incremental
communications scheme; essential1y the only commands
issued by the S-M-V Controller for the monitors are
increment the counters, decrement the counters, reset
the counters, and reset the parameters. Therefore,
any spot movement possible on a scanner C.R.T. can
be accomp1ished on the monitor C.R.T. The video
input for the C.R.T. grid is also synchronized by the
S-]~/I-V controller.
Included with the monitors for communications to
a central processing system are a selectric typewriter,
microtape input/output tape drives, and a light pen
for cursor control.

Video scan converter
The video scan converter consists of a high resolution storage tube capable of storing a useable picture
from a stored image before degradation is significant.
The storage tube can be written into and read from
at any of the video rates in the system (525, 1536F,
1536S) on the video switching matrix side. On the
SMV control side the scan converter looks like a film

203

as seen by a scanner; therefore, reading and writing is
handled in exactly the same manner as it is in a scanner.

V ideo switching matrix
The video switching matrix is a mechanical cross
bar matrix. Therefore, the switching speed will be in
the order of 100 milliseconds or less. In this routing
switch any source can be switched to from one to tliree
switching provisions are also included to mix any two
video sources to provide a composite signal to the
selected destinations.

Character generator
The Character Generator is designed to accept up to
512 ASCII characters i~to its 4096 bit memory. A 99
dot matrix, 9 dots wide by 11 dots high, is used to
develop each character into the appropriate video
levels. The maximum TV screen display is 16 horizontal
rows of 32 characters or spaces each. Alternatively
132 characters/line print-out can be generated on the
Videograph printer. A special cursor is also available
along with eight commands for controlling it.
The output composite video signal can be either
525 or 1536 lines per frame, depending upon the
externally supp1ied sync signal.

V ideograph printer
The Videograph Printer can print on demand at a
rate of 0.8 seconds per 8~ X 11 inch sheet. Horizontal resolution is 128 lines per inch and vertical
resolution matches the high resolution of the 1536
line slow CCTV cameras. Gray scale resolution is
limited to four shades. The paper used is inexpensive
zinc-oxide coated stock.

525 line T. V. cameras and monitors
The 525 T.V. Cameras and 11onitors are conventional
television units; namely, 525 lines per frame, 30
frames per second interlaced (60 fields per second).
These units provide for relatively low cost reduced
resolution, which is sufficient for many message routing
and simple acquisition and display purposes.

1536 F/ S cameras
The 1536 F /S cameras are vidicon camera units which
can be remotely selected to operate either in fast scan
mode (15 frames per second) or slow scan mode (1.25
frames per second). The format of either mode is 1536
lines per frame done in a sequential (non-interlace)

~4

Spring Joint Computer Conference, 1969

s~. The aspect ratio is variable, but it is set for a
nominal 8Y2 X 11 aspect ratio. The camera bandwidth is limited to 9.5 Mhz for fast scan and 1.4 l\1hz
for slow scan.

track video disk, where a single track can contain a
complete image. Input and output can be at either the
1.25 or the 15 frames per second rate with resolution
matched to the corresponding v-ideo devices.

Remote video consoles
Each remote console is a self-contained unit with
two video monitors and the necessary equipment for
conununicating with a digital computer. The video
monitors consist of a 17 inch 1536 lines per frame slow
(1.25 frames per second) monitor with a P-26 phosphor
and a 17 inch 1536 lines per frame fast (15 fra..rnes per
second) monitor with a VC-4 phosphor. Each monitor
matches characteristics of the associated camera.
Included with the console for direct digital communications to the central iomputer are a teletype
ASR-33 unit and a small special keyboard to be used
for frequently used machine orders. Other items to be
included with the consoles are a microfiche reader, a
digital patch panel for digital control signals, and an
analog patch panel for analog control signals.
Special plug-in options for a universal cursor control
could provide for such devices as a light pen, joy stick,
matrix pad, bug, etc. Other options could include provisions for direct handwriting of orders at the console
by T.V. camera pick-up and/or Rand tablet type device
and a monitor microfiche camera for filming images
from the C.R.T. screen.

Microimage storage
The Microimage storage consists of a microfiche
reader/access mechanism that is able to store, retrieve,
and display COSATI standard microfiche on demand.
Storage of the IPicroflche is by a rotary drum that is
a changeable unit. Images can be digitally selected,
and the display of any requested image requires less
than five seconds. Access time to an adjacent image
(Le., one within the same fiche) is less than two seconds.
The output is displayed in an 8Y2 X 11 inch format
if desired, and it is projected upon the two-inch vidicon
of a 1536 F /S line television camera for distribution
into the video network.
The drum holds 750 modified microfiche cards of
60 frames each. Each frame again contains an array of
7~ microimages or basically a standard microfiche.
Therefore, a single drum will provide storage for
3,240,000 page images. Readout from the selected
microfiche frame is accomplished with a fly's eye

V ideo storage
The video storage consists of an interchangeable 72

APPENXIX B-SYMBOL AND
LIST

PARA~1ETER

Parameter values assigned at design time
Parameter values explicitly assigned at
execution time

$* Upper case Latin *A * ACW B Bs BCW *C * D DCW DF DPB DX DY E Ell ECW *F FPB *G *J *K *L Ls LPB$ N(i)
Nu(i)

NGL
PW

*R

*S

Scan Axis selection
Angle Coordinate Word
Equivalent to (XB, YB)
Standard spot/nonstandard spot, or slit
selection
Begin Coordinate Word
}Iedia selection, Core memory
Equivalent to (XD, YD)
Display Coordinate Word
Data Format selection
Display Parameters Byte
X-component of the incremental format
Displacement vector
Y -component of the incremental format
Displacement vector
Equivalent to (XE, YE)
Same as E, to distinguish Vernier
End Coordinate Word
Media selection, Film (scanner)
Format Parameters Byte
Group rotation selection for the monitor
Display regeneration request
Constant data/sample rate option (for
a given p) with the raster format
Lattice selection
Length of Slit = 2" gross basic cells
Lattic'e Parameters Byte
Number of lines per video frame
N umber of useable lines per video frame
(or maximum (.6Y) v steps).
Number of Bits in a raster string representation
Number of Samples in a raster string
representation
Number of Gray Scale Levels = 22ft
Parameter Word
Gross/vernier Resolution selection
Sequence selection, sequential/interlaced

Parametic Description of Scan-Display System

S(j,n)
Smax(j)

*

SPB
SX
SY
T

* XB
* XD
* XE
XEv

* YB
* YD
* YE
YEv

::\1aximum achievable number of Samples
per full video scan line
Maximum value of S(j,n) (achieved for
n = 0)
Slit/spot Parameters Byte
Sign of DX
Sign of DY
Trigger (filter) selection for encoding in
the coordinate string representation
11edia selection, Video
Sweep Velocity
Width of Slit or spot diameter = 4u
gross basic cells
X-coordinate, Begin cell
X-coordinate, Displacement
X-coordinate, End cell
Same as XE, to distinguish Vernier
Y -coordinate, Begin cell
Y -coordinate, Displacement
Y -coordinate, End cell
Same as YE, to distinguish Vernier

Video magnification/demagnification =
2hv(i ,n)

*n
$nmax *p Pmax(j,n) *$ be

g(j)

k
m

q

$r!.'$ rv

* Sv
*U
$umax *V$vmax

*

Z

$Zmax 2 n is the number of bits of gray scale Maximum value of n AX = 2P (see ~) Maximum value of p for Video Network = bl1 - j n AY = 2q (see AY) Aspect ratio] control grid (Standard) Aspect ratio, video Sign bit of vernier counter Slit width is 4u gross basic cells Maximum value of u Slit length is 2" gross basic cells Maximum value of v e = 2z-b a (see Ae) Maximum value of z + Greek ~t(i) Lower case Latin N umber of bits in the angle orientation counter Number of interpolation bits concatenated with the bg-p gross resolution bits Number of bits in the gross position counter Number of gross-verrrier overlap bits Number of vernier bits that extend gross resolution Number of bits in the vernier position counter Rweep velocity constant (with Cl = fe, V s is given in basic cells per microsecond) Maximum data bit transfer rate Position counter incrementing frequency Video unit cell match function = rv/rs . XCi) . 2- i Video line selection modifier. Closest interger such that f(j) ~ 2g (1) Monitor magnification = 2h Maximum value of h Video magnification/ demagrrification exponent (see mv(j,n)) Video system identification Video system resolution parameter, Smaxmax qmax y=Cl.I, """,7 ANGULAR INCREMENT - - - - - - ' t:.I'J =2'.2- 8 3 z:o:o,l, """ ,7 (d l 7 7 1:1 (but variable) 3:4 Figure 19-Display (a), Lattice (b), Format (c), and Slit/Spot (d) Parameter Bytes as defined for Illiac III Umax Vmax Zma.x slit width is 4u basic cells slit length is 211 basic cells angle increment is 2z-l'a units 3 7 7 Interactive tolerance analysis with graphic display __ _ ... If by LAWRENCE A. O'NEILL Bell Telephone Laboratories, Incorporated Holmdel, X ew Jersey INTRODUCTION spread in each range that is dependent upon the manufacturing process and the component's age. Operat~g conditions are usually introduced during optimization as either typical or worst case discrete values, but more realistic estimates of anticipated performance can be obtained if the actual statistical distributions are taken into account, Tolerance analysis provides two primary sources of inforI.l.latidn to the designer: One of the principal advantages of a dedicated computer with on-line graphic display is that the user is able to quickly and easily interact with the program. The value of this interaction has been clearly demonstrated in the optimization of circuit and system designs.1.2 A related task on which interaction can have a significant impact is the investigation of the influence of parameter tolerances on the performance of an optimized design. There are three basic approaches to computer-aided tolerance analysis currently in use-moment method, monte carlo approach, and worst case analysis. 3 •4 The experimental approach presented here is a version of the monte carlo approach in which performance distributions are acquired by randomly perturbing the parameters. It is economically feasible to accumulate distributions rather than just compute a few statistics because of interaction and graphic display. The experimental approach is not subject to the linear assumptions of the moment method and the performance estimates are more realistic than those obtained by worst case. The advantages of the experimental approach, in computational simplicity and in the nature of the design information provided, are discussed and illustrated III this paper. 1. Tolerance Specifications-The designer can speccify maximum tolerance limits guided by a prediction of the expected yield. 2. Design Information-The designer can select among alternative realizations based either on which is less sensitive to expected parameter variations, or which will be less expensive to manufacture. Experimental approach The experimental approach to tolerance analysis consists of simulating the system under investigation, randomly perturbing the parameter values and displaying the distribution of performance criterion. The two basic advantages of this approach are: 1. Nonlinear systems can be investigated as easily as linear ones, without making assumptions and approximations. 2. The distribution of the performance criterion that is necessary for further statistical investigations can be measured. Tolerance analysis Tolerance analysis 3 of systems and circuits is required because the optimized parameter values cannot be exactly realized in manufacture, and the range of conditions under which the system must operate is usually much broader than the limited number of cases that can be considered during optimization. The parameter values are not exact because components are usually available only in discrete ranges with a statistical This nonlinear capability is important not only because many systems contain nonlinear elements but also because nonlinear performance criterion are normally applied even to linear problems-for example, a mean Rquared error criterion. A nonlinear criterion compli207 208 Spring Joint Computer Conference, 1969 cates a statistical investigation because the relative influence of parameter tolerances cannot readily be predicted, but the influence can be measured by the experimental approach. A measured frequency distribution, when properly normalized, provides the probability used in statistical estimates of yield and cost. vVithout interaction, the computer run times required using this approach become prohibitive because a large number of trials is needed to acquire confidence that an histogram· is representative of the population. In addition, the time required to evaluate the performance is frequently long. With interaction and graphic display, the number of trials can be significantly reduced by quickly terminating unsatisfactory distributions and also recognizing when sufficient samples have been accumulated by the insensitivity of the display to new data. ~\1oreover, if the dedicated computer can be operated in a hybrid mode, the solution time for problems requiring time domain analysis can be drastically reduced by employing analog simulations. The ability to use whichever mode of simulation (digital or hybrid) best satisfies the requirements. greatly broadens the range of problems to which the experimental technique can be economically applied. Tolerance analysis program The experimental approach has been implemented with a digital program. The basic features of this program are shown in Figure 1. * The parameters of the given system are randomly perturbed according to known statistical distributions and the performance is measured. The perturbation subroutine provides for the shaping of the distribution obtained from the random number source and for the correlation of the independent nllillbers to satisfy spo cific problem requirements. The distribution of the performance criterion is obtained from these m~asure­ ments by dividing the criterion range into class intervals and accumulating the number of occurrences in each interval. The accumulated data may be displayed either as a frequency distribution histogram or a cumulative distribution histogram. The real-time display on a digital scope enhances the evaluation of the histogram and facilitates interaction with the program. Documentation is provided on the printer-both parameter specifications and the diRtributions are printed when required. The real-time interaction allows the user to modify the histogram scaling, parameter nominal values * A detailed description of this program has been submitted, elsewhere, for publication by D. M. Bohling and the author. In that paper, the procedures for random number generation, histogram accumulation, and interaction with the computer are discussed. TOLERANCES PARAMETERS I NTERACT I ON Figure I-Tolerance analysis program and tolerances whenever required so that computer time is not wasted in accumulating useless data. It is the simplicity with which this technique can be applied to any problem, linear or nonlinear, without extensive, preliminary investigations that led to the design and wide utilization of this tolerance analysis program. Application The discussion of the experimental approach to tolerance analysis can be clarified by considering applications that illustrate its features. The two examples were selected to demonstrate the value of being able to use both digital and hybrid simulations, and the value of the ability to measure performance in nonlinear problems and then accumulate statistical distributions. Digital simulation of an inductor The first example illustrates the application of the tolerance analysis program to an all-digital simulation of a gyrator circuit. The obj ective of this experiment was to detennine what component tolerances would oe necessary in the gyrator circuit of Figure 2 to allow it to be used as a replacement for an inductor. The reason for using this circuit is to save on the cost, weight, and size of the inductors that are used in this frequency range. Such a replacement is feasible because the price of' the integrated circuit components and amplifier to be used are expected to become quite inexpensive in the future. The gyrator circuit must exhibit the same characteristics as an inductor and be stable, throughout the frequency range from .5 to 10 KHZ. The perfornumee criterion selected was the Q of the cirCUIt-the ratio of standard measure of inductor quality. The Q was evaluated by calculating the input impedance of the gyrator and taking the ratio df imaginary to real part of this impedance. The circuit will become unstable if the real part of the impedance become~ negative. At the instability threshold, the Q becomes quite large and thus Interactive Tolerance Analysis l/Q was used as the criterion to simplify scaling. Since the evaluation of this impedance at a particular frequency is an algebraic problem, one can take advantage of the high speed of digital simulation. A subroutine was written that calculated this performance criterion directly from the perturbed component values. The display of the frequency and cumulative distributions of l/Q used in evaluating the performance is shown in Figure 2. Gaussian variations were applied to all parameters on the circuit-passive components and amplifier characteristics. Several sets of component tolerances were evaluated before the acceptable performance illustrated in Figure 2 was obtained. The frequency distribution was used to determine the stability of the realization (no designs should exist with negative values CO.PONENT TOLERANCE AT 4", 209 of l/Q) and to acquire confidence in the sample size. The cumulative distribution reveals what percentage of the designs can be expected to have a Q less than any selected value. The tolerances used for this design were: 0.1 percent on the passive components, and for the amplifier characteristics, 50 percent on the gain, 10 percent on the cutoff frequency, 67 percent on the input resistance and 100 percent on the output resistance. The design was then statistically evaluated. at several frequencies within the intended operating range. The accumulation of data with this digital simulation was extremely fast; 200 designs could be tested and the histogram updated every second. The total amount of computer time required for this investigation was quite short not only because of this fast operation, but also because the interactive capability allowed the user to terminate unsatisfactory designs before many samples were accumulated. Hybrid simulation of a pulse equalizer PASSIVE 0.11 UPLIFtER Ao 50s T 101 R'I" &71 RD 1001 1.0 FREQUENCY DISTRIBUTION O~-L o ____ ~~~ 0.02 1/0 __ ~ 0.04 1.0 CUIULA Tl YE DISTRIIUTION O~---",-_......L. o _ _ _ _..L- 0.02 1/0 0.04 Figure 2-Performance of a gyrator simulation of an inductor may be evaluated from histograms obtained by applying Gaussian distribut.ions to components The influence of parameter tolerance on the error rate to be expected from a pulse equalizer was investigated to establish manufacturing specifications. The equalizer was one of a set to be used in a digital transmission system operating at 6.3 megabits per second over standard telephone lines. The nominal equalizer designs were optimized by Fleischer2 on the same interactive, hybrid facility that was used for tolerance analysis; therefore, the basic analog simulation and digital error rate calculations were available. The calculation of error rate includes terms reflecting intersymbol interference, thermal noise, crosstalk and sampling jitter. The transient response of each equalizer design had to be evaluated to determine interference and noise. The intersymbol interference, which indicates the effect of adjacent pulses on the one being equalized, was calculated from the analog measurements of the signal at sample points preceding and following the pulse peak. The thermal noise power to be expected from each desjgn was estimated from the impulse response of the system. The determination of the transient response by digital computer simulation took far too long for either optimization or tolerance analysis and thus an analog computer simulation was used. The block diagram of the hybrid simulation of the equalizer that was used in the tolerance analysis is shown in Figure 3. The computer program repeats the following sequence of operations and accumulates the distributions under the user's control. A set of component values for each design is chosen randomly and inserted into the simulation. A subroutine is provided to convert the component nominal values and tolerances specified by the user into simulation parameters. Both 210 Spring Joint Computer Conference, 1969 Figure 3-Hybrid equalizer simulation an input corresponding to the pulse to be equalized and an impulse are sequentially applied to the perturbed design to evaluate intersymbol interference and noise power respectively. The analog outputs of the equalizer are sampled and processed on the digital computer to determine error rate. Even for this complex application, it is possible to evaluate the error rate for one design every five seconds. In the subsequent discussion, only component tolerances in the three bridged -T sections are considered; it is assumed that these sections are buffered and all other parameters are set to their nominal values. All the components in the basic bridged-T equalizer shown in Figure 4 may have tolerances applied to them except the characteristic impedance labeled R. Care must be exercised in a tolerance analysis simulation to avoid programming simplifications that may not be valid when components are perturbed. For example, the bridged -T section can be analyzed as a second order system if it is assumed that the series and shunt arms are properly matched; but since this match would be destroyed by perturbations, a fourth order simulation is required. Before the analytical difficulties introduced by a nonlinear criterion (error rate) are discussed, a linear criterion directly related to the equalizer response is discussed so that the differences can be illustrated. First, the standard deviation (0') of the peak amplitude of the equalizer output pulse is estimated by the moment method for various sets of tolerances applied to the components in one bridged-T section. The same data are obtained by measurement with the tolerance analysis program and the results are compared. Then the error rate is measured under the same conditions and the influence of parameter tolerances are qualitatively compared. The variance of the pulse peak can be estimated from the distributions applied to the component values by the moment method. 4 The performance criterion is expanded in a Taylor series and only the lowest order terms are used. Then the variance of the response (O'~) is found for normally distributed, uncorrelated component perturbations with the formuia. (1) where the a" are the component values. The partial derivatives of the response with respect to the parameters can be obtained by a fiuite difference approximation or by measurement using the parameter iufluence method.1i The second method, which requires that an auxiliary circuit be programmed to measure the partials without an approximation, was used to obtain the data for the equalizer. The auxiliary circuit was realized by analog simulation and the measurements were sampled and nonnalized with a hybrid program to provide the sensitivity coefficients, Si. oln P ai Po S·= - - = - . , alnai P (2) oat HZ c R R where P is the pulse peak with no components perturbations. Let us express the standard deviation of the component distributions about the nominal values in terms of tolerance specifications. We define the tolerance percentage (X) to correspond to the Ka point of the normal distribution. Thus (3) l c Equation (1) can be rewritten as: O'P)2 (P Figure 4-Bridged-T realization of fixed equalizer section 2 i~ Si N = (X lOOK )2 (4) This< same additive procedure can be applied if per- L'"lteractive Tolerance Analysis 211 turbations are introduced in the component values of all three sections. Equation (4) was used with measured sensitivity coefficients, Si, to calculate the data given in Table I for various sets of component tolerances applied to one equalizer section. A comparison of the Si revealed that peak amplitude is most sensitive to variations in C and L'. These two components have equal influence and no other component is even 1/20 as effective. .9999 .999 .99 .98 / .95 . !I!! Table I -Standard deviation of pulse peak .80 :z .70 Tolerance at 2(J (percent) (Jp/P .60 (1Q-2) .50 . 40 H C L Calculated with Equation (4) lVleasured with Tolerance Program CoIPoN ENT Tol ERANCE IS = 100 0 0 0 1 1 1 1 1 3 3 3 3 5 5 5 0 0.56 1.23 1.68 2.80 0.03 0.50 1.20 1.80 2.71 To determine the (J of the pulse peak with the tolerance analysis program, the error rate calculation was replaced with a measurement of peak amplitude. The program was used to accumulate histograms, with at least 150 designs measured for each case, for the tolerance sets listed in Table I. The (J estimated from these histograms is also listed in Table I; the similarity of the reRults is obvious. The finite (J with no perturbations is due to small errors in the analog simulation; the program thus provides a check on analog reproducibility. The relative sensitivity of the components is determined with this program by experimentally varying tolerances and observing the histogram changes. Let us now consider the influence of the parameters on the error rate under the same conditions listed in Table I. The histograms were clearly not normally distributed. These cumulative distributions were replotted on probability paper as shown in Figure fl. On this paper, a normal distribution appears as a straight line with (J inversely proportional to the slope. Since the distributions are not normal, the tolerance sets cannot be compared on the basis of their (J as in the moment method. The relative influence of the tolerance sets can be compared on the basis of yield at a selected rate as determined from the curves. The threshold of acceptability for this equalizer was an error rate less than 10-1°; therefore, using 1 percent tolerances with K = 2 for all components, approximately 98 percent of the designs are acceptable. With the low number of samples used to obtain this data, the absolute yields may not be co 0- :::> ID .30 ~ .20 c ..... 0- C:~i) .10 :::> ~ x CURVE NO. R C l .05 I 0 0 0 .02 2 I I I 3 I I 3 4 3 3 3 5 5 5 5 .01 .005 .002 . DOl .0005 -15 -I 2 -II -10 -9 -8 -7 .0001 LOG OF ERROR RATE Figure 5-Influence of component tolerance on equalizer performance as determined by scaling the Gaussian distributions applied to the components in a single fixed section with various tolerance sets extremely accurate but a comparison of relative values is valid. A comparison of curves two, three, and four in Figure 5 reveals that selectively tightening the tolerances on the R's and C's does reduce the variance, but that the yields are not appreciably improved until the L's are also tightened. With the linear criterion, it was observed that C and L' were equally effective; but when comparing the yields for a given error rate, this is clearly not the case. The difficulty of combining error rates is also evident from the curves of Figures 6 and 7 in which are compared the error rates of each of the three bridged-T sections perturbed separately and all three simultaneously perturbed. The simultaneous perturbation of all three did not produce performance appreciably different from the worst of the individual sections (each section had different nominal component values). If one attempts to combine the individual section data to obtain a worst case estimate of the overall three section performance, a much more pessimistic estimate would result than the performance actually measured.. Spring Joint Computer Conference., 1969 212 1.0r-------------------~__._----~ 1.0------------------~~~------~ SECTION 2 FIRST SECTION 0.8 0.8 z: z: CI CI COMPONENT TOLERANCE AT 2(7' ~ :::I CD a::: 0.6 ~ ~ W > ~ a:: 0.4 ...I C t L 0.6 ~ ~ R 1S CI C ~ :::I CD CI lAo! 1S 3S > ~ c ...I 0.4 r COMPONENT TOLERANCE AT 2(1" :::I -= :::I -= :::I ~ :::I R 1% C 1% L 3% (.) 0.2 0.2 o ~~ ____ -16 ~~ -14 ____ __________ ~ -12 -10 ~~ -8 o -16 -14 LOG OF ERROR RATE Figure 6-Relative influence of each of t.he t.hree fixed sections In the equalizer as determined by applying Gaussian distribution to all components in the section Pessimistic estimates of performance may also occur if fixed values on system parameters, other than components, are used in the calculation of error rate. For example, in obtaining the component tolerance data, a fixed value of crosstalk was used that was indicative of the worst cables measured. A statistical distribution that reflected the measured crosstalk in many cables was introduced into the error rate calculation by the program. Figure 8 shows a comparison of error rates for component variations in one section with fixed and with normally distributed crosstalk. It can be seen that the fixed value yielded an extremely pessimistic estimate since most designs will produce significantly better performance. If acceptable yields can be obtained with worst case estimates, there is no need for measuring the distributions. But typically with 'state of the art" designs this is not the case and the distributions may allow the designer to relax some specifications and still obtain adequate perfonnance. Realistic estimates of yield are invaluable in a cost comparison of different realizations. Rather than tighten all tolerance to provide a 100 percent yield and then compare relative costs, an alternative probabilist.ic approach can be taken. Since yields can be determined from -12 -10 -8 LOG OF ERROR RATE Figure 7-The dominant influence of the first of the three fixed sections of the equalizer is illustrated by applying Gaussian distribution to the components in only the first section and then to all three sections simultaneously the cumulative distributions, the cost can be compared on the basis of testing and rejecting a few of the unitH that are constructed with wider tolerance components. This cost calculation includes the yield to be expected, the cost (C i ) of the individual components with a specified tolerance (T i) and the cost (C T ) of testing to determine defective units. Therefore, the cost of an acceptable unit, that is one with an error rate less than the threshold (k) is: C = CT + M(T1, 1. . . .J.. rp \ .L N) f i =1 C i (T i ) (5) N = number of components in a unit ~I(T 1 , ••• TN) is the yield at threshold k, for the specified set of component tolerances, as obtained from the cumulative distribution. This cost calculation is indicative of the many statistical applications in which the probability density or the cumulative distribution is needed to determine system performance. Interactive Tolerance Analysis _-....,....-------------"'T'"r----,.nll CO.PONENT TOLERANCE AT 2, .999 .95 .90 .ID .70 . 60 . 50 .40 .30 .20 z: 0 ... ...= ...... ...,.. ... IE provides the designer with realistic estimates of anticipated performance on which to base his decisions. The performance distributions are acquired economically because the user can quickly evaluate and terminate the computer runs. This technique is to be made more readily available to designers by modifying a standard digital analysis program such as ECAp6 to fit into the structure. Then a large class of circuit problems can be handled without special purpose programs and simulations being provided. Therefore, only the more difficult problems will require additional programming to perform the tolerance analysis. 0 c ..... ,= !if .10 . 05 .02 ACKNOWLEDGMENT The discussions of this material with J. Chernak, P. Fleischer, R. Snicer, and J. Davis are gratefully acknowledged. The author is particularly indebted to D . Bohling who organized and wrote the tolerance analysis program used in this work. .01 .005 .002 .001 .0005 -45 -40 -35 -30 -25 -20 -15 LOG OF ERROR RATE -10 -5 213 .0001 0 Figure 8-Comparison of equalizer performance as measured with the same Gaussian distributions applied to the components in the first fixed section using both fixed and Gaussianly distributed values for external crosstalk power CONCLUSIONS The values of the interactive computer with graphical display for tolerance analysis has been demonstrated in a variety of applications. The experimental approach REFERENCES 1 Special issue on computer-aided desig'n Proc IEEE Vol 55 November 1967 2 P E FLEISCHER Hybrid optimization for electrical circuit dei:>ign Eastern Simulation Council Princeton X J June 1968 3 D A CALAHAN Computer-aided network design McGraw-Hill ~ew York 1968 4 D G MARKS L H STEMBER JR. Variability analysis Electro-Technology Vol 76 No 1 July 196537-48 5 H F MEISSINGER The use of parameter influence coefficients in computer analysis of dynamic systerns Proc Western J C C 1960 San Francisco May 1960 6 1620 electronic circuit analysis program (ECAP) User's manual H20-0170 IBM Report 1620-EE 02X A method of automatic fault-detection +..00+ "~o,, ~.o""'Q"''''+':I''II.''''' .fl"ll. ... .LVU.L .f1"ll. .......-1'.LI.«0"::; _...,.]" ... O'O ... « "...V.LI. .LV... 6.::1.L1.~ MOS LSI circuits byY. T. YEN National Cash Register Company Dayton, Ohio INTRODUCTION ro determine whether an integrated digital circuit is working properly, one may apply to the circuit a set of· well-devised test sequences and compare the resultant outputs with the corresponding correct outputs. Any discrepancies indicate the presence of a fault. The main task here is to find a set of test sequences which can detect the presence of any prescribed fault in the circuit. This test generation problem will become formidable for large scale integrated arrays, since large number of logic circuits may be contained in an array with a limited number of exterior terminals. Presently, the approach most commonly used in test generation is computer fault simulation. In other words, data are repetitively processed through a cycle of two steps, i.e., test generation followed by test verification. In each cycle, the generation of primary output test sequences can be accomplished by a computer logic simulation technique. The primary-input test sequences are manually generated by engineers because much creative work is involved. In this paper, a method will be proposed to generate primary-input test sequences for 4-phase MOS sequential switching circuits. This method can find the shortest primary-input test sequences to detect a given fault on an array. An MOS transistor stuck at either short or open permanently is the failure mode to be considered. A single fault assumption4 will be made in this paper. Peculiar circuit jeaJ,ures Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits.2 ,3 It is found that the test sequence generation problem can be greatly simplified by exploiting the peculiar features of these circuits. . There are four clock signals and four types of logic gates in a four-phase MOS circuit.2 The time interval of one clock-phase is defined as one unit of time t, as shown in Figure 1. For example, t = 7 is the time at the end of phase 3 of the second bit. Let S t denote the set of logic levels of all internal logic gates of a 4-phase circuit at time t: Where Sit is the logic level of the i-th logic gate at time t, and m is the total number of internal logic gates. It should be noted that the output signal of a 4-phase gate cannot be sampled during the certain clock-phase times, because of the precharging behavior of the gates. The clock-phase time during which the output signal of a gate can be sampled is shown in Table 1. Table I-Bampling time of gates Type of gates type-1 -2 -3 -4 Clock-phase time during which the output signal of a logic gate can be sampled. Phases 3 and 4 Phase 4 Phases 1 and 2 Phase 2 Now the peculiar circuit features useful for test sequence generation can be summarized as follows: 21.5 Spring Joint Computer Conference, 1969 216 lNITIAL CfIX.K PIIASE TI ME t - I 3 I4 I JST 8IT I I 2 I3 I4 0 I 2 I 2ND BJT I I2 I 3I4 I 3RD BIT I 2 I OJ I I .3 4 S , 7 8 'I - - - 10 1/ - - - Figure I-Definition of time t (1) Each four-phase logic gate provides a storage of at its output for one or two clock-phase tunes, (2) feedback and feed-forward in a flipflop circuit do not occur simultaneously, and (3) the logic levels of· all logic gates in a circuit, including flipflops can be initialized to predictable logic levels by inhibit~ the occurrence of one 4>2 or cf>4 clock pulse. ~ormation Tracing technique Jor Jour-phase .il.1 OS circuits In order to force the logic gates of a 4-phase circuit to desirable logic levels, we will trace a signal backward to find the necessary primary-input sequences and circuit initialization. The peculiar features ·of 4-phase circuits enable us to trace a 4-phase signal backward by considering each unit of time t as follows. Let F 11 be the 4-phase signal at a logic gate output at time t = t 1 • ViF 11 will denote the function obtained from tracing F tl backward by j units of time· t where j is a positive integer. To trace V'F tl backward by one unit of time, we will substitute every internal gate variable s. of V'F tl with the combinatorial Boolean function implemented by the logic gate SA:. Let us demonstrate this technique by tracing backward the 4-phase signal s, in Figure 2. In Figure 2, iI, i" and ia are primary inputs. Sa and B4 are type-1 logic gates. BJ, SI, and Bi are type-2 3 and . gates, respectively. ' , 4 ',OglC Since SI gate is a type-3 gate, the logic signal SI can be sampled only during phases 1 and 2. Let tl be the time at the end of phase 4 of bit N. Then (tl - 1), (tl - 2), (~1 - 3) and (tl - 4) are the times at the end of phases 3, 2, 1 of bit N and phase 4 of bit N - 1, respectively. Let SUm and iUm denote the logic level of SI and it at time t = tm, respectively. In tracing SI backward, the following relations are derived for each unit of time t: SIll = St(Il-1) 'S&(tl-l) = ~(tl-l) + ~(tl-l) (1) (2) = S,(I1-I) + ~(tl-I) (3) = 4(tl-a) + i (tl-a) + S1(tl-B) . Bi(tl-8) (4) = 4(11-8) + i2 (tl-8) 2 + (8101-4) • St(fl-4» ·i;(lI-4) (5) J Figure 2-A four-phase MOS Circuit = 4(tl-8) + + i2 (S8(11-1) (tl-8) + ~(I1-1» ·1;(11-4) (6) Where (2) is derived by substituting SI of (1) with the combinatorial Boolean function B!B4, which is implemented by the logic gate SI. Note that the time at which signal SI can ~ sampled is one unit later than that at which signals BJ and B4 can be sampled. The relation (1) = (2) indicates that: (a) SI will be 1 at time t = tl if and only if either or both St = 0 and B4 = 0 hold at time t = tl -1; and (b) SI will be 0 at time t = tl if and only if St = B4 = 1 holds at time t=tt-l. Let us denote SIU as F u. Then VIF 11 will be BJ(Il-l)"B4(U-lh as shown in (2). Equation (3) is derived from (2) by tracing backward another unit of time t. There is a type-2 gate B2 between gates S3 and SI. However, there is no type-2 gate between gates B4 and SI. Therefore, we will substitute 8J of (2) with the combinatorial Boolean function S; implemented by the logic gate 82. And, we will not substitute B4 of (2) at this time. S8(1l-2) + ~(tl-!) of (3) will be denoted as V2F Il • Equation (4) is derived from (3) by tracing backward additional unit of ti'lle t. We substitute S3 and s. of (3) with the combinatorial functions h and it + SII%, respectively. We will denote h(Il-B) + i2 (u-3) + Sl{U-8) !36{U-I) of (4) &.9 VIF u. Method of Auto:matic Fault-Detection Test Generation Equations (5) and (6) are similarly derived from (4) and (5), respectively. It should be noted that gates S1 and S4 of Figure 2 form a RS flipflop. Recall that a 4-phase MOS circuit possesses a peculiar feature that the feedback and feedforward in a 4 phase flipflop cannot occur simultaneously. This feature enables us to trace backward a signal in a 4-phase sequential circuit for each unit of time, as shown above. No additional specification, such as a truth table, is needed to specify a flipflop. output of the logic gate if and only if the inputs of the logic gate, except X m , satisfy the following condition: Where £ i is the combinatorial Boolean function implemented by the logic gate. Let us consider the 4-phase gate shown in Figure 4. Assume that Xs has a fault. Then, = XIX2 + ~ £(X s ~ 0) = X 1X 2 £(X s ~ 1) Conditions of fault signal propagation Let £(X1, X 2, - , Xn) be the combinatorial Boolean function implemented by a 4-phase logic gate. A fault of an input, say Xi, will be defined as the 1\10S transistor fed by Xi is permanently stuck at short or open. In this section, an algebraic method will be discussed to derive the input conditions of a legic gate under which the output of the logic gate will respond to the presence of a fault at an input Xi. Boolean difference See Figure 3. £(XI, X 2, - , Xn) is a combinatorial Boolean function. Assume input Xm has a fault. Sellers et aU show that the fault of Xm can be propagated to the output if and only if the input variables of £, except X m , satisfy the following condition: £(Xm ~ 1) EB £(Xm ~ 0) Boolean difference EB £l(X ~ EB X lX 2 D l • S = £l(XS ~ 1) = X lX 2 + S ~ 0) =Xl~+X2~ Thus, D l ,8 = 1 if and only if either Xl = 0 and X 4 = 1 hold or X 2 = 0 and ~ = 1 hold. Under either of these two input conditions this logic gate behaves as a logic inverter, i.e., £1 = Xa. Consequently, the gate output efl will then respond to any fault of Xt. It should be = 1 Where EB is exclusive OR, and m is one of the integers 1, 2, 3, - , n. Xm ~ 1 (or 0) means that variable Xm ot £ is substituted by the constant 1 (or 0). A Boolean difference of a function £i(X1, X 2, - , X,,) with respect to input Xm will be denoted as Di,m, which is Examining the features of a 4-phase logic gate, we see that the fault of input Xm can be propagated to the X.-t X, COM/JINATORIAL X.. • Figure CIRCUIT ~~-Signal notations of eomhinato,"ial eircuit Figure 4-A four-phase MOS logic gate 218 Spring Joint Computer Conference, 1969 noted that each term of Dj,i represents such an input condition. Assume the l\fOS transistor Ts associated with input Xs is permanently stuck at short. Then we must. apply the signal Xs = 0 to T 3, so that the fault of "short" can be detected at the output J\. Therefore, the input conditions to detect T s permanently stuck at short are the input conditions satisfying Xa.D1,s = 1. Where Xs.D1,s = Xs (Xl~ + In other words, either 0 and ~ = 1 X 2 = 0, Xs = 0 and ~ = 1 = gi,i+1, for 1 :::; :::; k, gl,2 = D 1 ,2 g2,3 = (Vb gl.2) . D 2,s gS,4 = (Vb g2,S) . D s ,4 ~,5 = (Vb gs,4) . D 4,5 X2~) = XIX~+MX~. Xl = 0, Xs We will denote functions as follows: or will detect the fault of "short" of l\'{OS transistor T 3. If Ts is permanently stuck a~ open, then XS.Dl,S = 1 are the input conditions to detect such a fault. The shortest fault detection test procedures See the block diagram of a 4-phase circuit in Figure .5. Each block represents a 4-phase logic gate. Consider logic gate £ k. Assume the transistor associated with its input £ k+l has a fault. We will find the shortest tests to detect this fault. The propagation path of the fault is £k, £k-l, -, £s, £<;., and £1. Starting from £1, we will find the Boolean difference and trace backward for each stage of logic gates until we reach £ k+l as follows. Where D i ,i+l is the Boolean difference of £i with respect to £ i+l. Vb is to trace gJ,i+1 backward b units of time t. b = 1 if one of £ j and £ i+1 gates is either type-2 or type-4 logic gate. b = 2 if both £ i and £ i+l gates are neither type-2 nor type-4 logic gates. Let us consider the gate J'k. If the transistor associated with input £ HI is permanently stuck at short, 1 HI' gk ,k+l = 1 will be the input conditions to detect the prescribed fault. If the transistor associated with input J' HI is permanently stuck at open, £ k+1 • gk,k+l = 1 will be the input conditions to detect the prescribed fault. We will denote G = £HI gk,Hl if the transistor associated with £ HI is stuck at short, = £Hl gk,k+1 if the transistor associated with £ k+1 is stuck at open. Every term of G is an input condition to detect the prescribed fault. Each term of G may consist of primary inputs and internal logic gate signals. We will check each term of G to find whether it satisfies the following condition: Condition A : OUTPUT either 1. All variables of a term of G are primary inputs or 2. All internal-gate variables of a term of G will become logic-l by inhibiting a proper clock signal. - - - fiATE II I ---IT I Figure 5-Block diagram of a four-phase circuit (Sequential or combinatorial) We will follow the following steps to fault detection tests. fin~ the shortest Step 1. Check every term of G to determine if it satisfies condition A. Step 2. If no term of G satisfies condition A, trace G backward by one unit of time t and then repeat step 1. If there is a term Method of Automatic Fault-Detection Test Generation of G which satisfies condition A, this term is the shortest test to detect the prescribed fault. Furthermore, if there exists a test at time t = tr which can detect the prescribed fault, then at least one term of G at time t = tr satisfies condition A .. If the function G becomes 0 at some step of tracing backward, then there exists no test which can detect the prescribed fault. Let us derive the shortest tests to detect some fault in the .circuit shown in Figure 2. Assume T1 is stuck at open permanently. Then £1 and £2 are the gates Sl and S4, respectively. Since the faulty transistor T 1 belongs to gate B4, £k and £k·H are B4 and Sl, respectively Let t1 denote the reference time at Sl. Since £1 = Sl(t1) = B2(tl-1) S4(tJ-l) = B2(tl-l) thus Since £2 = S4(tl-2) = il1 (tl-s) + Sl(tl-S) S5(tl-S) = S5 (tl-S) . i2 (t1-S) thus, ~ ,3 = S5 (t1-S) . h (tl-S) . i~ (tl-S) Since T1 is stuck at open, = Sl(t1-S) S5(tl-S) h(tl-s) i~Ht1-S) We will check G to determine if it satisfies Condition A. Since internal-gate variables Sl and 85 cannot become logic-l simultaneously at time (t1 - 3) by inhibiting either cf>2 or cl>4 clock signal, we will trace G backward one unit of time t. Here, it should be noted that gate S5 is a type-4 gate and gate Sl is a type-3 gate. 219 time t] - 5, then all type-3 gates such as the gate S1, will become logic-l at time (t1 - 4) and (t1 - 3); therefore, V1G satisfies condition A. In other words, if we set up the following condition, the fault of T 1 being stuck at open can be detected at the primary output Sl at time t = t1: Inhibiting cl>4 at time (t1 - 5) is = 0 at time (t1 - 4) h = 1 at time (t1 - 3) i2 = 0 at time (t1 - 3) Since V1G has only one term, this condition is the only test to detect the fault of TI being stuck at open. Compute?' programming 1Ianual implementation of this method was not attempted for the complexity of logic in an LSI array because of the complex detail involved. Using this method, a computer program written in FORTRAN IV was developed and has been used to generate test procedures for each prescribed fault in a 4-phase MOS LSI array. This computer program consists of 15 subroutines to perform the following manipulation: Simplify a function OR functions AND functions Complement a function Find Boolean difference Trace a function backward Check a function to determine if it satisfies Condition A Simulate faulty signals Keep tracking timing. Every signal name is denoted by a number. A Boolean function F x is specified by an integer number NXTER~1, and two integer arrays NXNOVAR(I) and NXVAR(I). For example, F x = SlSsB4 + ~4 and Fy = ~S5 + Ss will be specified as follows in the computer program: Fx: l\""XTERM = 2 NXNOVAR(l) = 3, NXNOVAR(2) = 2 NXVAR(I) = 1, NXVAR(2) = 3, NXVAR(3) = 4 NXVAR(4) = 2, NXVAR(5) = -4. F lI : NYTERM = 2 Let us check VIG to determine if it satisfies Condition A. If we initialize the circuit by inhibiting cl>4 at NYNOVAR(I) = 2, NYNOVAR(2) = 1 NYVAR(I) = -2, NYVAR(2) = 5 NYVAR(3) = 6 220 Spring Joint Computer Conference, 1969 Where NXTERJ\lI specifies the number of terms in function F:t. NXNOVAR(l) and NXNOVAR(2) show the number of variables in the first and second terms. NXVARCi) shows the variable at the ith order counting from the left of the function F:t, i.e., NXVAR(l) = 1 denotes SI, and NXVAR(5) = -4 denotes 84' F y is similarly specified in the program. Now, let us OR the functions F z and F y • The resultant function F z = F:t + F ycan be easily performed by the computer program as follows. Fz: NZTERM = NXTERM + NYTER]\rl = 4 NZNOVARCl) = 3, NZNOVAR(2) 2 NZNOVAR(3) = 2, NZNOVAR(4) = 1 NZVAR(l) = 1, NZVAR(2) = 3, NZVA.R(3) = 4 NZVAR(4) = 2, NZVAR(5) = -4, NZVAR(6) = -2 NZVAR(7) = 5, NZVAR(8) = 6. This computer program is written in FORTRAN IV for a NCR 315 RMC computer. Through the use of 40K-word core memory, 12 bits per word, it can generate the primary input sequences of the shortest fault detection tests for each prescribed fault in a 4-phase }\10S array of 70 four-phase logic gates. The program needs 8 minutes of FORTRAN IV NCR 315 RlVIC computer time for the prescribed faults of one 3-input Jour-phase gate on a typical 70-gate array. The computer time for this test generation can be greatly reduced if this FORTRAN program is converted into a NEAT (machine) language version for the NCR 315 Rl\1C computer. REFERENCES 1 F F SELLERS JR M Y HSIAO L W BEARNSON Analyzing errors wiJ,h the Boolean difference Digest of the First Annual IEEE Computer Conference September 1967 6-9 2 Y T YEN A. mathematical model characterizing four-phase MOS circuits for logic simulation Input data The input data to this computer program only consist of: a. Logic implemented at every individual logic gate. This logic is a combinatorial Boolean function. For example, the program needs the combinatorial Boolean function B2 + ~ to specify the logic implemented by SI gate in Figure 2. b. Type of each logic gate. SI gate in Figure 2, for example, is a type-3 gate. c. Designation of faulty lHOS transistors. d. Designat.ion of one fault-signal propagation path for each faulty gate. An internal signal of an LSI circuit may be propagated to several primary outputs. To simplify the computer program, a desirable propagation path for an internal fault signal need be given. The propagation path of a fault signal S4 in Figure 2, for example, will be specified as S4 ~ SI in the input data, for the faults associated with S4 gate. IEEE Transactions on Computers Vol C-17 September 1968 822-826 3 Y T YEN Intermitient failure problems of four-phase MOS circuits To be published on IEEE Journal of Solid-State Circuits 4 E R JONES C H MAYS A. utomatic lest ge·ne·ration I1wtlwds for large scale integrated logic IEEE Journal of Solid-State Circuits Vol SC-2 No 4 December 1967 5 J P ROTH Diagnosis of automata failures: A. calculus and a method IBM Journal July 1966278-291 6 E G MANNING H Y CHANG A comparison oj fault simulation methods for digital systems Digest oi the First Annual IEEE Computer Conference September 6-8 1967 10-13 7 F P PREPARATA G METZE R T CHIEN On the connection assignment problem of diagnosable system IEEE Trans on Electronic Computers Vol EC-16 December 1967 848-854 8 S SESHU D N FREEMAN The diagnosis of asynchronous sequential switching systems IRE Trans Electronic Computers Vol EC-ll August 1962 459-465 A method of diagnostic test generation by A. B. CARROLL, lVI. KATO, * Y. KOGA, and K. NAEMURA University of Illinois Urbana, Illinois INTRODUCTION A variety of diagnostic techniques1- S have been proposed and applied to error detection and location in computers. The efficiency of the tests generated by them varies from machine to machine depending on the scale of the system, its logic organization, and the employed hardware technology. The impact of highly integrated circuitry is changing the trend in logical design of computers. The significant reduction of propagation delay per individual switching gate and of the physical size of the circuits has made it possible and frequently even desirable to use a less sophisticated technique in the logic design. The use of adder packages with' standard carry lookahead and semiconductor scratch pad memories often results in a better cost/performance ratio than development of the fastest carry propagation technique and the most advanced instruction lookahead control. The design of the ILLIAC IV computer9 is one of the recent examples in which modularity is preferred to an excessive sophistication of logic. On the other hand, the introduction of higher integration technique has posed a problem to diagnostic engineers. The failure modes of the circuits have become more complicated and less obvious. Seventy to eighty percent of catastrophic errors may still be caused by mechanical failures at bonding and connections but the other errors include such subtle faults as marginal errors rising from relatively low noise margins of current mode gates and unexpected shorts (low resistance) between logically distant connections on a semiconductor chip. This paper describes a new approach to the method of diagnostic test generation for a computer built with highly integrated circuitry. The first half of the next section describes the generation of test paths used to test registers and transfer paths between them. The second half is concerned with generation of input patterns for testing combinational logic networks. Techniques employed in logic simulation and location of errors are briefly discussed in the following sections. GeneraJ,ion of test cases Path tests A graph representation of a system is useful to visualize the operation and data flows in it. Several papers have been published on the use of graphs in diagnosis of logical machines.6 In this section, we discuss the generation of efficient tests for detection and location of errors using a graph of the machine. Let us assume that the system has been represented as a directed graph, in, which nodes and arcs correspond to some circuit blocks and signal lines. In addition, let us assume the arcs in the graph can be enabled or disabled independently. A graph is equivalently represented as a square matrix called "adjacency matrix." Figure 1 shows an example of a graph and its adjacency matrix is as follows: No Nl Nt N3 N4 N6 • Currently with Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan. 221 No Nl Nt N3 N4 No 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 222 Spring Joint Computer Conference, 1969 o indicates the absence of the corresponding node or arc There exist thirteen possible paths from the input node No to the output node N I) as shown in Figure 2. Let us define a row vector of Boolean elements for each path, where each column denotes a node or an arc; No IJ! P4 I 1 ~:P7 I !. o '"v o o o o o 1 1 1 1 1 1 1 o o o Ps 1 1 PII P IO 1 1 o Pn Pu 1 1 o o o 1 1 1 1 1 1 1 1 o o 1 o 1 1 1 1 in this path. Now we have the following matrix with respect to the graph in Figure 1. We call it path matrix of the graph. Al At Aa ~ As As A7 As Aa AlO 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 !1 1 .1 1 .1 i\ v 1 1 o 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 .L 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 jJ INPUT ,~". "'~: ~:~: ~ . • ~~ \~~: ,~k: \t~\~ 't'" \f 'r ,~ P1 ;. p. P10 P ll ~ut Figure 2-Possible paths OUTPUT Figure I-Example of a directed graph To diagnose a machine for disconnection errors, we should test paths to see if they successfully connect the input and output. In the above example, if arc Ag fails, Po, PI, P a, P 6, P7, P g, and P u still connect successfully, but P 2, P 4, Pe, P s, P IO , and P I2 contain an error. Thus, by comparing columns of the path matrix with the test result, we can determine which node(s) and/or arc(s) have errors. If an error location can be determined by testing all possible paths, it is said to be distinguishable. All possible path tests may not be required to determine where a single fault has occurred; i.e., we may be able to reduce the number of paths from the complete set of all possible paths in the original graph. The following method may be used to reduce the number of path tests; the resulting set of paths still retain the ability to detect single failures. Let us consider a graph with a single input and a single output; if there are multiple inputs or outputs, we can add a dummy input or output node and connect it to the actual inputs or outputs so that the graph may have only one input and one output. Now we produce a tree from the original graph; starting at the input node, we put down an the nodes which are directly fed by the A Method of Diagnostic Test Generation input node and draw lines corresponding to the arcs between them. Level zero is assigned to the input node and level one to the nodes adjacent to the input node. The level one nodes of the example in Figure 1 are Nt, N 2, and N 3• This step is repeated until all nodes are covered. If a node has already occurred on a higher level or previously on this level, we define it as a pseudo-terminal node and cease to trace arcs down from it. Three pseudo-terminal nodes on level two are shown in Figure 3. Whenever a path from the input has met a pseudo-terminal node, we choose one of the routes which go down to the output to complete the path. We obtain six paths from the graph in Figure 1, as shown in Figure 4. In the example the shortest path was selected after the pseudo-terminal nodes. Errors in node No and N s are indistinguishable. So are the errors in N 2 and arc As, and those in X I and AI, those in N4 and As, respectively. This was true also in the original graph. We call this method as the path generating method hereafter in this paper, and we show that a set of paths generated by the PG:\1 is a minimal and sufficient set Ns -LEVEL 0 Nz -LEVEL 1 N3' -LEVEL 2 223 of paths to detect and locate a failure in a network without feedback. Theorem 1. The set of paths generated by the PGM is a minimal set that is sufficient for detecting and locating any distinguishable single failure within the graph without feedback. Proof. If we insert a dummy node on each arc of the original graph, we can discuss only the distinguishability of node failures. The indistinguishable nodes are defined as follows: if there exist two nodes ni and nj such that no path in the graph passes through exactly one of the two nodes n i and n j, then these two nodes are said to be indistinguishable. It is noted that all nodes of the original graph are exhaustively included in the paths generated by the PGM. 1 INPUT No OUTPUT -LEVEL 3 CO DENOTES A PSEUDO- NODE Figure 4-Generation of a tree from the graph (2) Figure 3-Generation of a tree from the graph (1) No Nl N2 N3 N4 N6 Al A2 A~ ~ A6 A6 A7 A8 A9 Alo 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 Figure 4.2-Path :Matrix 224 Spring Joint Computer Conference, 1969 If anyone of the paths generated by the PG1VI were deleted, then there would exist at least one node (corresponding to an arc in the original graph) which was not included in the set of paths. This is obvious because no arcs are repeated in a tree generated by the method except in the route below the pseudo-terminal nodes. The indistinguishable nodes resulting from the testing of all paths in the original graph do not become distinguishable nodes by testing the paths generated by PG1'I. Next, let us assume that the nodes ni and nj are distinguishable by testing all paths with the original graph. There should be at least one path which passes through either one of the two nodes ni and nj. Let us define a set {Pii} of all possible paths that pass through both nodes ni and nl, and define a set {nii} of all nodes on these paths lying between ni and nj, where the set fnii} includes nodes ni and nj. Because ni is distinguishable from nj, there is at least one branch connected between node nk &Jnij} and a node nt e{nii}' The path through the node nt exists in a set of paths generated by the PG~1 and this path does not pass through both nodes ni and nj. Thus the nodes ni and llj are still distinguishable by testing the paths generated by the PGM. The time-consuming procedure of reducing the set of tests using a minimal cover technique can be avoided by the simple algorithm and the theorem stated above. The theorem is valid for a general class of networks with feedback. Wo WI W2 W3 W4 W~ Ws W7 s We-!l Wg c W,o W" I I W'2 I WI3 l I s Z~ S I Y3 W'4 WI~ : c I Y4 I I C I _____ .JI L WI6 WI7 s W1e S W" c C W20 ~------------ ZIO Figure 5-Example of a combinational network Combinational tests Suppose each solid box in the network of Figure 5 is a full adder and every pair of circuits is put on. a chip as indicated by the dashed line. Let us consider how we can test the logic function of a chip. The following equations are relevant to the chip inputs and outputs: 1. Equations for chip input signals = W W3 4 W7 = Ws Xl X2 = X3 EB Wg EB WIO X4 = WSWg X6 X6 = = + W4W6 + W3W 6 W12 W13 I (1) J 2. Equations for chip function YI y, ya = = = Y4 = Xl EB X2 EB Xa XIX, X4 + X2Xa + XIXa EB Xfi EB Xs X4X6 + X5X6 + X4X6 + (WO + W2)(W3 EB W4 EB W6» EB W6 EB Yl Z4 = (WOw! + (Wo + W2)(Wa EB W4 EB W6»(W6 + YI) + YIW6 Z6 = Wll EB Y2 EB Y3 Za = (WOW2 Zs = = WUy! Z7 + W9WIO + WSWIO EB W14 EB WlO 3. Equations for external outputs (2) + Y2Ya + WllYa (WlaW14 + W14WlO '+ WlaWlO) (3) EB W17 EB WIS EB W19 EB W!O EB W l6 EB Y4 In general, an output of a chip may feed an input to another chip whose output feeds an input (possibly through a few other chips) to the first chip. The equations for chip inputs in such a case will contain a term including the chip output variable. Thus we define a "combinational logic network with pseudo-feedback loops" as follows: 1. It has a (multi-output) combinaiionallogic func- A :rvfethod of Diagnostic Test Generation tion which describes the relation between the external inputs (WI, W2, ... , WN) and outputs (Zl, Z2, ..• , ZM)' 2. It is composed of a finite number of unit circuits each of which has a (multi-output) combinational logic function to describe the relation between its inputs (Xl, X2, ... , xn ) and outputs (Yl, Y2, ... , Ym)· 3. It may contain pseudo-feedback loops; i.e., its connection graph may contain any number ot loops provided that none of these constitute storage of internal states. Thus, the output values of any unit circuit are uniquely determined by the external input values of the network despite the existence of loop8. The unit circuits in the network may be of any size and any structure, provided they satisfy premise (2) above. Specifically, however, we are concerned with unit circuits as a model of integrated circuit chips or portions of chips, the total number of input and output Hnes being limited within the order of 101 • The structure of the circuit may be a net of at most 101"'2 of elementary logic gates. Various types of failures may exist within the logic network. Some of them are of electrical nature, others of mechanical. A considerable fraction of them are only intermittent and cannot be detected except by chance, while the rest persist long enough to be detected as permanent failures. It has been a convention in previous studies to classify those failures by logical modes: stuck-at-O mode, stuck-at-1 mode, other degenerate modes, and nondegenerate modes. Very few papers have treated all of these modes. Techniques for detection and location of more than one failure in a chip have not been extensively developed. So that we may not confine possible failures to any particular mode, we set the foIlmving assumptions, which have been adopted (if not explicitly) by all previous studies: 1. The failure is non-sequential; i.e., it may be any transformation of the combinational logic function of a unit circuit but it doesn't change the unit to a sequential circuit. 2. Only critical failures are of concern; namely, only if they change the external logical function of the network. 3. We will treat failures in any single chip; i.e., we assume that failures don't exist simultaneously in more than one chip, although the existence of more than one failure in a chip is not excluded. The assumption (1) above requires that every possible 225 combination of input values be applied to a unit circuit. (In case a subset of all possible combinations is obtained V\rith a narrower assumption on failure modes, the following discussion can be applied to the subset.) Then, the problem is how to determine external input values so that a unit circuit can be given an arbitrary input combination and that any change in its output value can be detected at an external output. This is formulated as follows. First, obtain the equation f i for a chip input Xi (cf. Figure 6), as follows: 1. Break up all the chip output lines, v!, ... , v m • 2. Insert dummy inputs Yl, Y2, ... , Ym to the network to replace signals v!, ... , vm • 3. Write an equation f; for Xi in terms of external inputs WI, ... , WN and dummy signals Yl, ... , Ym. Now the requirement is stated in the following, where the Boolean difference7 dJL/dti of a function JL = JL (h, ... , t n ) with respect to ti is defined by JL (t l , ... , t n ) EB JL (t l, ... , ti-l, ti, ti+l, ... , t n ). 1. Any combination aI, a2, ... , an of values may be assigned to chip inputs Xl, X2, ... , Xm; i.e., for i = 1, ... , n'. where Vj is an output from an error-free copy of the chip under test and is a function of WI, ... , WN as obtained from the: original network (Figure 6 (a». 2. Some of the external output values should be changed by a deviation in signals Yl, ... , Ym. Thus, for j = 1, 2, ... , m: (5) :3. Any pseudo-feedback loops should be logically broken up to fix the chip input values in the existence of an error. For: i = 1, 2, ... , nand j = 1, 2, ... , m (6) Thus, solving equations (4)-(6) in terms of WI, W2, ... , W N we obtain a set of input values for error detection. A solution for the example in Figure .5 and equations (1)-(3) is shown in Figure 7. Sixty-four input patterns are required to test for all possible combinations of inputs to the chip. Spring Joint Computer Conference, 1969 226 t-:l w1-----f I Wz • • • • • W VI Xl L2 X2 • • •X. N Xi = fI • • • • 0 •z. O2 (WI » VIZ. • .•• WN ) 01 01 0 Y1 04 vJ=a (Xl. XZ ••• -IX.) ;y (Wi. Zit :: glt (WI. 0 WI • • • • ,WII) WI. (0) ORIG I NAL all • .W N ) 06 NETWORK s Y2 C Y3 S Y4 0 0 W1 I I I IL _____ Wz 0 • • 0 WN 0 0 C 0 Yl Xl Yl ~z ff~: • X. Yz • •Y,. • • I =f,*(Wi. WZ • • • •• WN.Yl. Yz , •••• Y.) Zit = (Wi. WZ , • • • ,W... Yl Y. , ... ,Y.) XI g: (b) NETWORK I WITH DUMMY SIGNALS Figure 6-Generalrepresentation of a combinational network Location of errcYT'S The determination of nodes and arcs relevant to each path test is straightforward from the path matrix. Translation from nodes and arcs to packages and wiring then enables us to determine which physical components of the machine affect a test result. Location of single errors detected in path tests is possible by comparing the columns of the path matrix Figure 7-801ution to Figure 5 with each test result expressed in a vector form in which a 1 indicates failure and a 0 success of the test. In effect, simultaneous comparison of many columns with a test result can be done by taking a logical product of the matrix rows complemented if the result of the test corresponding to the row is a success. Multiple errors can be located, though in a less straightforward way and with a lower resolution, by selecting a maximal set of columns each of which implies the test result vector. Another method for locating errors consists of organizing a branching tree of tests so that each terminal of the tree corresponds to a distinguishable error or a set of indistinguishable errors. The execution of tests follows a chain of tests in the tree selecting either a "success" branch or a "failure" branch after each test case until the termination. 8 The following theorem is evident from Theorem 1 on the minimality of path set generated by the PGl\1. A Method of Diagnostic Test Generation Theorem 2: When a set of test paths generated by the PGl\I is developed into a branching tree, the number of tests in the tree (which is the number of tree nodes excluding terminals) is the same regardless of which paths are assigned to the tests, provided that there are no redundant tests. By a redundant test is meant a test of a path which passes through all nodes and arcs remaining to be distinguished at the test point or 'which passes through none of them. Therefore, location of single errors by a branching tree of path tests is an even more straightforward procedure than the comparison of matrix columns. Also, multiple errors (although perhaps not all of them) can be located by an organization of test tree based on the evaluation of a proper weight for each test. Errors detected in the combinational tests may not be located in an equally straightforward manner; however, their locations are identified at least up to a logic block and a further isolation can be done by manipulation of a matrix similar to the path matrix. While the equation (5) guarantees that any error can be observed at some of the external outputs, a Boolean difference dz k / dy j specifies the condition on the external inputs under which any error at signal y j is detected at the specified external output Zk. Therefore the matrix can be obtained by evaluating the difference for each pair of y j and Zk. When a matrix manipulation is not possible or realistic enough in practice, a test dictionary is produced using the methods above and the maintenance engineers can look up the most suspicious error positions listed in it during the actual testing. Logic simulation of the machine It is a common practice to use a logic simulation program to determine the correct respom;e of the machine to each test input. A logic simulator may also be used extensively in debugging the logic design. Because diagnostic generation may proceed in parallel with logic debugging (without waiting for its completion), the construction of the simulator should he as exact as possihle to the mechanic&.l organization of the logic. For discrete circuitry computer systems, the fastest simulators used to be compiled from a gate-level description of the design, a gate in the machine corresponding to a few machine instructions (Boolean or where not available, arithmetic operations) in the simulation program. The ordering of the instructions was a well-defined ordering among the gates. The introduction of integrated circuitry and higher integration into the computer, 227 however, brought in some new features in logic design and simulation. Logic design cannot always precede the package design. Physical and mechanical limitations on semiconductor and packaging technology place significant restrictions on logic design and it is not possible for a machine to be designed completely in detail and then partitioned. The logic of the machine must be described in at least two levels-~the logic of evers package type and the interpackage connections. Thus it is less straightforward than it used to be to compile a gate-level simulator. For the same' reason any change in design may be reflected in different ways in the simulator. Either a logic package is modified, or a connection is replaced by another, or both. A simulator can be much more easily updated if the logic packages and connections can be distinguished one from the other. On the other hand, the turn-around time in designing and manufacturing high density packages cannot be neglected. The logic internal to a package may not be changed as easily as the connections among packages. The construction of the logic simulator may have the same nature. Because of these factors subroutines can be utilized to describe the logic package. When a simulator is created using a general-purpose programming language (ALGOL, FORTRAN, or PL/I), a procedure can define the relations between the inputs and outputs of a package. Then the body of the simulator becomes a sequence of procedure call statements, the actual parameters associated with each call corresponding to the signals incident to the package. The procedure calls must be ordered properly so that the propagation of control and data signals can be followed. There are two problems arising in the ordering of packages. They are: 1. To which level to assign packages containing storage elements. 2. How to order the packages involved in loops. The first problem can be solved by duplicating a register package into two nodes-corresponding to the loading and output selection functions of the pack agein the graph representation. Thus, the receiver and register-output nodes are assigned the first levels, while the drivers and register-input nodes are assigned the last. The packages involved in a loop (or a maximal "circuit," or a "maximal connected subgraph") are assigned the same level. The associated procedure calls are put in a program loop and executed until the values of inter-package signals in the loop are all stabilized. 228 Spring Joint Computer Conference, 1969 Such an assignment can be efficiently programmed in the following steps: 1. Assign levels from the first level in an ascending order and then from the last in a descending order until the remaining nodes cannot be assigned any unique level. 2. Using matrix operations on the adjacency matrix, find all the maximal loops and reduce each of them to a dummy node. :3. Assign the remaining levels using the newly developed dummy nodes in place of loops. CONCLUSIONS A method of generating test cases for diagnosing a machine using high density circuitry has been described. This method is motivated by the assumption that computer organizations are becoming more modular and the failure modes of high density integrated circuits are becoming more complicated and less obvious. A minimal and sufficient set of path tests can be generated by a simple algorithm working on a graph representation of the machine. Combinational logic networks can be diagnosed by a set of test input patterns generated by a procedure described. There are three sets of equations which must be simultaneously solved to obtait""1 input patterns; one of them is a new requirement caused by the high density of circuits in a semiconductor chip. A logic simulator may also reflect the progress of hardware technology. A Imv-cost simulator generator has been developed which uses a general purpose programming language as the simulator media, in which the package logic is described as functional procedures. Several methods of fault location have also been described for path tests and combinational tests. The Path Generating l\Iethod has been programmed in Extended ALGOL on Burroughs B5500. Generation of combinational tests were perfonned semiautomatically. A logic simulator generator has also been programmed on Bi).~OO. A logic simulator of the Processing Element (PE) of the ILLIAC IV Computer was generated by the program and has been used successfully in logic debugging and diagnostic generation. Path and combinational tests generated by the described methods have been employed in off-line testing of the PE. On-line testing will use another set of tests produced by the same methods. AClu~OWLEDG=VIENT The authors wish to express their gratitude to Professor D. L. Slotnick and certain members of the staff in the ILLIAC IV project for their advice and discussions. The algorithm of the Path Generating :\Iethod was developed through discussions with ~\1essrs. W. L. Heimerdinger and Y. l\latsushita of the University of Illinois; programming efforts were done by Ylessrs. C. Chen, J. E. ::.vEller, W. Sterling, ,and C. Tanaka. This work was supported in part by the Department of Computer Science, University of Illinois, Urbana, Illinois: and in part by the Advanced Research Projects Agency as administered by the Rome Air Development Center, under Contract No. USAF 30(602)4144. REFERENCES 1 J SESHU D N" FREEMAN The diagnosis of asynchronous sequential switching systen/'s IRE Trans on Electronic Computers August 1962 T KASAMI H OZAKI 2 S HASHIMOTO Fault diagnosis of comhinationallogical networks Journal of Inst of Electrical Communication Engineers Japan April 1964 ' 3 D B AR:YlSTRO::--rG On finding a nearly minimal set of fault detection tests fot' combinational logic nets IEEE Trans on Electronic Computers February 1966 4 W H KAUTZ Fault testing and diagnosis in combinational digital cirCltitl:: .~ IEEE Trans on Computers April 1968 J P ROTH W G BOURICIUS P R ~CH~EIDER Programmed algorithms to compute tests to detect alld distinguish between failures in logic circuits IEEt~ Trans on J..:lectronlc COn1pl.lters (}rtober 1967 6 C V ItAMAMOORTHY ~l structural theory of machine diagnosis Proc S J C C 1967 7 F F SELLERS JR M Y HSIAO L W A. nalyzing errors with the Boolean difference IEEE Trans on Computers July 1968 X H Y CHA~G BEARSO~ A.n algorithm for selecting an optimum set of diagnostic tests IEEE Trans on Electronic Computers October 1965 9 G H BAR~ES R M BROWN M KATO J D KUCK D L SLOT~ICK It A STOKES The ILLIAC IV computer _ IEEE Trans on Computers August 1968 Programmed test patterns for muititerminai devices by FRANCIS J.l\lcIXTOSH and W. W. HAPP National Aeronautics and Space Ad,m:nistrati01I Cambridge, Massachusetts INTRODUCTION The rapid development of micro-electronics towards multiterminal structures demands corresponding growth in understanding the potential and limitations of multiterminal devices and networks. The increasing sophistication of integrated circuits will impose a new set of criteria upon network synthesis. In particular, through the suitable arrangements of terminals or accessible test points of a multiterminal device, many distinct configurations may be realized. A . multitenninal network like the transistor contains several realizable configurations, typically a voltage amplifier, a current amplifier, an attenuator, or a filter. Hand enumeration will suffice in attaining all of the configurations derivable from such a small network. However, several thousand distinct functions can be realized from a six-terminal network, and the scope of network synthesis could well be directed to selecting one of several million functions available from a multiterminal network. A computer program has boon developed to enumerate all of the allowable configurations so that each may be identified uniquely and non-redundantly. tions is possible so that N(z, x, y) = H(z, x) .'1'(y, x - y), where H(z, x) is related to the partitioning of z, and T(y, x - y) is related to the number of trees of a structure with x components. 2 c. a computer program implements the algorithms contained in the previous papers to calculate the nu..rnbers H, T, and N, but does not list these functions. 3 An extensive bibliography is provided in the references cited. Objectives The objective of this investigation is the generation and listing of the H(z, x) subnetwork configurations, which result when a z-tenninal parent network is constrained to fonn x-terminal subnetworks. The computer program developed will generate and list explicitly all unique and non-redundant x-terminal subnetwork configurations of a z-tenninal parent network. The assumptions under which the program is formulated a:r:e: Scope of investigation a. the z-tenninal network or device asymmetrical; b. the z parent terminals may be utilized to fonu tenninals of the subnetwork, or may be left free or uninvolved in the subnetwork configurations; c. subnetwork configurations are arrived at through the systematic shorting and opening of accessible terminals. Review of related work Previous investigations of multitenninal devices utilized combinatorial techniques to obtain algoritluns for generation of network functions and failure diagnostics: a. the number N(z, x, y) of x-terminal y-port subnetworks derivable from a z-terminal parent network was tabulated. l b. the separation of variables as a product of func- Based on this work future investigations are planned: a. to develop teclmiques for dealing with the symmetry of multitenninal devices and obtain a 229 230 Spring Joint Computer Conference, 1969 non-redundant listing of the H(z, x) configurations with specified symmetry constraints; b. to provide a computer program for listing the T(y, x=y) configurations, and subsequently obtain an explicit list of the N(z, x, y) configurations with and without symmetry constraints; c. to· apply these listings to failure diagnostics of multiterminal structures; d. to select network performance characteristics on the basis of subnetwork listings. DEVICE 2 13"'112A 14"'121A 1S"'211A 16"'11A2 17"'12A1 1d"'21A1 19"'1A12 2U"'1A21 21"'2A11 22$Al12
23"'A121
24"'A211

3

2

I

12A

3

I
3

To illustrate the concepts to be used and the terminology to be defined subsequently more rigorously, the configuration H(4, 2) is examined in Figure 1. Six subnetwork configurations, illustrated on the left, are realiz-

IA2

2

I

2

3

I

I

2

,...------.1

L-

B
-----1'--__
A..L..-....L-_ - - - J

-

1

I.

NETWORK

i23

Illustrative example

1"'12AA
2"'12AC
3"'1A2A
4*1A23
S*1AA2
6*1AS2
7"'A12A
o"'A123
9"'A1A2
lO"'A132
11"'AA12
12"'A612

CODE

1l~

112

IJc

121

I}

3

I

I

-L

A
8

AI2

2

2

--r--lj

3
211

IJc

Figure 2-Code for H(3,2) configurations

1....-_---1

ll~-_~

~

__2

able from a device with z = 3 and x = 2 by utilizing
either:
two of the three terminals of the parent network
and leaving the third terminal disconnected, or
b. all three externally conne<;ting t\VO together t()
form one terminal.

tl..

25"'1112
26"'1121
27*1211
20"'2111

:1;...----1

29*2211
3u*2121
31"'2112

l.__----l
1L..1----I

Larger networks form thousands of subnetwork configurations and hence require a systematic coding procedure. One method iR illustrated in Figure 2 and
Figure 3.
~

__2

~----,b

Figure I-Print-oui of H(4,2) configurations

a. the z parent terminals are arbitrarily numbered;
b. each line (or word) represents a subnetwork in
code;
c. numerals refer to external terminals of the subnet.work;

Programmed Test Patterns for l\fultiterminal Devices

231

11fJi2
4~3

SYMMETRY
(2143 )

o

EXTERNAL
TERMINAL

• INTERNAL
TERMINAL

I

,~,
SYMMETRY
( 1432)

o

f~~::C

• INTERNAL
TERMINAL

UNIQUE

ONE- PORT CONFIGURATIONS
WITH COOE

Figure 3-Unique one-port configurations ~ith code

d. letters refer to the internal terminals, which are
not part of the subnetwork;
e. position of number or letter in a word indicates
the tenninal of the parent network represented
by the number or letter.
The coded computer print-out may then be applied to
a particular network device. The HC3, 2) configurations
are illustrated on the right in Figure 1. Given the COhlputer output for HC3, 2) and the parent network structure, each of the six subnetwork circuit configurations
Algorithms for generating subnetworks

Terminology
• A terminal is an accessible test point in the parent
network, each terminal will become either an external or internal terminal in the subnetwork.
• A multiterminal structure is a network or deyice of
more than two terminals. The computer program

is developed for structures of up to eight tel'mlnals.
• An external terminal of the subnetwork is an accessible testpoint consisting of either a single terminal
of the parent network or a group of terminals from
the parent network constrained to form the single
external terminal.
• An internal terminal in the subnetwork configuration is a parent terminalCs) which is (are) left free
or uninvolved in the subnetwork and thereby COllstitute unaccessible testpoints in the subnetwork
configurations.
• An external configuration is a unique and nOIlredundant arrangement of one or more terminals
of the parent network at each terminal of the subnetwork.
• An internal configuration is unique and non-redundant arrangements of terminals not forming
part of the subnetwork in groups of one or more.
In diagrams the internal configurations are drawn
inside the system to differentiate them from external configurations.

232

Spring Joint Computer Conference, 1969

Separation into external and internal
configurations
The program is based on the following procedure:
a. the external configurations are defined by the
restriction of I terminals, x ::s; I ::s; z, to form x
external terminals;
b. the z-I terminals remaining are constrained into
groups of 1, 2, ... , z-I to form the internal configurations, each group representing a unique
and non-redundant configuration;
c. varying I in unit steps from x to z, enumerate and
store the external and internal terminal configurations for each I and z-I respectively;
d. integrate by appropriate combinatorial techniques the stored external and internal COllfigurations at each step 10 yield the desired
H(z, x) configurations.
To accomplish this, eight subprogram subroutines
are utilized in the program, three of which-EXTERN,
INTERN, INTEG-are called in succession by a small
master program, and which in turn utilize the other
five in appropriate sequences according to the flowchart. 3 Two techniques are of fundamental importance
to these subroutines:
a. Enumeration of Combinations in Binary Cod€
b. Disj'oint Loop Enumeration and Storage
These techniques will he discussed now.

Enumeration of combinations in binary code
The enumeration technique is based upon the subroutines BIN and lVIAIN which generate combinations
of P things taken Q at a time. Each combination is
generated as a series of ones and zeros, yielding C~" ones"
and P-Q "zeros". The terminal numbers under which
the ones fall defined terminals included in each particular combination with P digit-positions in all. By systematically moving the Q ones into all com hi nations of
the P positions, the resultant (P, Q) combinations are
explicitly listed and yield the number which is the
binomial coefficient of P and Q.
Each combination is then Htored in a so called" compendiom; form", a technique previously used in processing of combinatorial information.4.5 Treating each
combination of ones and zeros as a number of base 2,
the word is changed to decimal notation as, for example,
for P = 4 and Q = 2 in Figure 4. This is accomplished
by treating each combination as a Heries Xi i = 1, ... ,P,
p

and

performing the operation F(x) =

LXi. 2
i=1

i - 1•

1100
1010
1001
0110
0101
0011

- 1+2 - 3
- 1+4 - 5
- 1+8
9
2+4 - 6
- 2+8 - 10
- 4+8 12

li'igure 4-Transformation of P = 4, Q
decimal notation

=

2 int.o

Each decimal number thus created is saved as a single
subscripted integer variable in BIN and as a double
subscripted integer variable in MAIN.
This method of storage is advantageous for two reasons. The computer memory utilizes binary coding in
its storage of a decimal number : each combination thus
coded may be recalled from its decimal number.
Efficiency and economy also results by utilizing only Olle
storage position in memory per combination.

Disjoint loop enumeration and storage
The routine which enumerates and stores disjoint
loops exploits an isomorphism between the allocation of
external and internal terminals for a subnetwork and the
identification of disjoint loops in a flowgraph. If eaeh
loop of a flowgraph is coded in binary form in terms of
the nodes it contains, then disjoint loops can be ifientified by binary addjtion. 6.7.8 The resultant subroutines
calculate and store those combinations of loops which
have no nodes in common.
The logical operation .AND. compares two binarycoded decimal numbers. If two loops are disjoint the
resultant combination is defined as a second-ordf>r loop.
The number of disjoint combinations involved in the
union is defined as the loop order. Thus,a loop of order
m consists of m first order loops which have no nodes ill
common.
The loops are stored as a subscripted integer variable
which is made up ,A the subscripts of the integer variables under which the disjoint binary-coded numbers
are stored. Combinations of terminals correspond to
loops or combinations of nodes, each node corresponding to a terminal of the parent network. In the previoli~
example of (4, 2) the loops 12 and 3 are disjoint. Labeling first order loops sequentially, consider row six and
row one, a second order loop results which are stored

Programmed Test Patterns for Multiterminal Devices

233

as 601. Similarly, 11 and 5, 6 and 9 are disjoint binarycoded numbers, and are stored under their subscripts as
502 and 403 respectively. In this way the binary-coded
numbers and the combinations which they represent
are stored in a compendious manner and may be
efficiently recalled.

of which it is representative. By repeating the process
for each row of partition numbers, the matrix of external
configurations IETER (I, J) is formed.

Sequence of subroutines

The final subprogram subroutine INTEG is called
as soon as the matrices IITER (I, J) and IETER (I, J)
are complete for a particular IQ and 1. These matrices
are then integrated systematically as determined by the
ways of combining z terminals I at a time, and as
enumerated by BE\" in ones and zeros. The number of
ones equals I and the number of zeros equals IQ. For
a particular I external terminals and z - I = I Q internal terminals, the H(z, x) .configurations are listed
through the substitution. of entries of the IETER.
(I, J) matrix and IITER (I, J) matrix for the ones and
zeros, respectively, of each combination enumerated by
BIN.

The generation H(z, X) tor a particular I external
terminals and z-I internal terminals is described by
comment cards defining the function performed by
each subroutine and is given in a listing or the program. 3

Internal configurations
After the problem statement provides the program
with z and x, IXTERX is called for IQ = z - I terminals. This subroutine in turn calls BIN" to enumerate
and save the combinations of IQ terminals taken
2, 3, ... , IQ at a time in the stored binary code. The
combinations of IQ items taken one at a time are taken
into effect and enumerated later in INTERX. The
disjoint loops of the above are next calcualted by
INTEHX and stored. SPRINT is utilized to break
do:w-n the stored disjoint loops into their unique configurations and enumerate in numeric code the proper
internal configurations implicitly represented by each
stored loop. These configurations form the matrix
IITER (I, J).

External configurations
The suroutine EXTERN is next referenced for I and
x terminals. The partition numbers subroutine PART
is then called by EXTERN to return how I terminals
are restrained to yield x tenllinals.
For example:

P (4, 2)

=

[!: iJ

For each number in a row of partition numbers, the
combinations of I tenninals taken that number at a
time are enumerated and stored.
Once the combinatorial enumeration of a particular
row is accomplished, subroutine LPORD is utilized to
calculate the disjoint loops for those combinations of the
row.
Since redundant loops may be generated for a particular row if t\""O or more numbers in that row are equal,
this case is accounted for and only non-redundant loops
are enumerated. As each loop is calculated the proper
numeric code is generated for the external configuration

Integration of internal and external
configura tions

Output format for configurations
The configurations thus generated must be represented in a unique and convenient code. Previous workl,2
utilized upper case letters for external terminals and
lower case letters for internal terminals, identical letters
and type indicating those terminals of the parent network that are joined to form the subnetwork c<;mfigura. tion. Since a computer will only print upper case letters,
the lower case letters were replaced by numeric character. A variation of this alphanumeric code is used up
to a point just prior to print-out.
The pre-print-out fomlat for each configuration is a
series of positive and negative numeric characters.
Positive integers correspond to external subnetwork
terminals; negative integers correspond to internal subnetwork terminals. Identical integers and signs indicate
terminals of the parent network which are joined to
form the subnetwork configuration. This coding scheme
is perhaps the most applicable to a computer setup for
testing multitemlinal devices and for network analysis.
An adaptation of this fomlat is the substitution of
upper case alphabetic characters for the negative
integers, since this scheme provides for greater visual
clarity in identifying the unique configurations. A listing
of a number of subnetwork configurations is found in
Figures 5 and 6.

Applications

Identification of unique network functions
The computer print-out for H (4, 2) is given in Figure
1. These eoded subnet,vorks are relevant to testing and

·Spring Joint Computer Conference, 1969

234

HI

3 2)

h(

5 2)

1*12A

,.1AC:

~*~~~ciJ.t

3*~1~

j.12tiAA
4*liAAt.
tl*i2A6C
6*lAZAL;
7*lA2t.lA
8. 1 LI2 .. ..1
9*lAZAA
10*lA2oC
1h1;\A20
1.2*lf,02A
13*10A2A
1'+*1AA2A

.. *11Z
~*1d

0*<.11

1~*1Hb2C

!::>b*dlAi:l
!::>7.11A2A
!::>e*12AlA
!::>9.dAIA
uU.llA2u
bl*12AlrJ
o2*"lAIlJ
'o3*liAA2
64*12AA1
0;'*.:1 AA 1
Ot>.11 ALl2
67.12AiH
ob*dAtH
o9*lA12A
70*1AZIA
71*2AllA
72*IA12b
73*i .. 2111
74*ir,llu
77*, .. 1111
7<:i*iA102
79*IAc.tH
oU*ZAlbl
BHIAAIZ

114*2111A
11tl*Z211A
llo • .::1~1A
11 hdlZA
llb*-111A2
119*112A1
120*1<:1A1
121*dlAI
122.221A1
123*212A1
12'+.211A2
1Z!::>*llAl':
12t>*llA21
j.27*12All
128*dA11
129*22A11
13U*21A,,1
131*21A12
132*IAllZ
133*lA121
134*lAZ11
135*",,111
!jb*2A211
137"Z,,1d
138*2A112
1.39*A1112

h1211A
3*1,:.2A

10*1AAt.i2
1H1AbA2
Ib*lUAA2
19"'111AA2
2U*1A6C2
21*>ll,Ao
*;l.12dC
20*A1A,0
27*AllJ2A
2d*01A2A
29*,,1A.lA
3u*"lb2C
31*A1Ao2
.32*A1E'A2
.33*61AA2

d3*211All
0'''1 .. 612

141*A1211
142*A2111
lI+3..,A22lJ.
144*A2121

1~*211A

.3~*A1bC2

10*11112
17*12A1
18*<::1A1
19*1A12
20*1A21
21*2;..11
22*A112
23*A121
24* .. 211
25*1112
26*1121
27*1211
26*,111
29*i211
30*2121
31*2112

.30*AA12i.3
37*i.i312A
3tl*oA12A
39*AA12A
40*ALl12C
'+1*AAlti2

H(

* 2)

34*A1,,~2

42*Au1A~

43*tlA1A2
4,+*AA1A2
45*Ao1~2

46*AA812
47*A5A12
48*t:lAA1i
49*AAA12
50*AI;,C12
51*112AA
52*121AA
~3*,11AA

55*ldAti

7~*IA1"2

7o-1A2Al

8~*1AB21

Bb*<::AI:il1
d7*A1l2A
8d*A121A
89*,,211A
90*A1120
91*A121d
92*A21l1j
93*A11A2
94*AI2,,1
95*1I21A1
9b*Alld2
97*A121H
9b*A<:lBI
99*A1A12
100*A1A21
101*A2A11
102*A1B12
103*A11321
10**A2811
105*AA112
106*AA121
107*AA211
10&*Ao112
.L09*Abld
1l0.Ato211
111*1112A
112*1121"
113*1211A

14~*A2112

1 .. 6*11112
147*11121
148*11211
149*12111
1~0*2111l

151*22211
152*22121
153*22112
154*21221
15~*21212

156*21122
157*12221
~5e*12212
1~9*12122

100*11222

H( 4 3)
1*123A
2*12A3
3*1A23
4*A123
5*1123
6*1213
1*1231
8*2113
9*2131
10*2311

H( 5 3)
1*123AA
2*123AB
3*1ZA3A
4.12A38
!::>*12AA3
6*12Ab3
7*IA23A
8*1A23Eo
9*IA2A3
10*1A263
11*lAA23
12*1Ab23
1:3*A123A
1,+*AI236
15*A12A3
16*A1263
17*A1A23
18*A1823
19 .. AA123
20*Ai:H23
21*1123A
22*1213A
23*1231A
24*;::113A
25*2131A
26*23111>.
27*1l2A3
28*121A3
29*123A1
30*211A3
31*213A1
32*231A1
33*11A23
34*12A13
35*12A31
36*21A13
37*21A31
38*23A11
39*1A123
40*1A213
41*1A231
42*2A113
43*2A131
44*2A311
45*A1123
46*A1213
47*A1231
48.A2113
49*A2131
50*A2311
51*11123
52*11213

tl6*d3A14

~7*d113
~8*Z1l31

H(

!::>9*21311
00*23111
01.22113
02*22131
03*22311
04*d213
65*21231
06*23,11
67*.:1123
b8*21321
09*23121
70*21132
71*21312
72*23112
73*32211
74*32121
75*32112

t> 4)

1*123,+AA
2*1234AB
3.123A'+A
4*123A4b
5*123AA4
6*l23AEi4
7*12A34A
8*12A34b
9*12A3A4
10*12A3E,I+
11*12AA34
12*12Ab3,+
13*IA234A
l'U1A234li
15*1A2.3A*
16*11123b4
l7.1AZA34
li"IA~B34

19"'IAA23 4
20.1Ab234
<:1*A1234A
22*A1234B
23*A123A4
24*1.1236'+
':~*A12A34

H(

~

h 1234A
2*123A4
.3*12A34
"*1A234
5*Al,34
6*11<:34
7.12134
B*1231~

9*123 ... 1
10*2113'+
11*21314
12*213~1

13*23114
14*231 .. 1
15*23'+11

4)

20*A1263'+
27*AIA234
2tl.Alb234
29.AA1234
30*IIB123'+
j1*1l234A
32*12134A
33*12314A
34*12341A
35*21134A
30*2131 4 A
37*21341A
38*23114A
39*231,+IA
40*.::31111A
41*1123A4
42*1213A4
43*1231A4
4'+*1234A1
45*.::113A4
46*;:131A4
47*2134A1
48*Z311A4
49*Z314A1
~0*2341A1

!::>1*112A34
!::>2*121A~4

~3*1l231

!::>3.123A14
!::>4*123A'+1

54*12113
55*12131
56*12.311

~5*~11A~~

~7*Z13A41

!::>tl*,,31A11+
!::>9*Z31A41
oO*<:34A11
61.11A23'+
02*12A134
03*12A31'+
0,+*12A341
05*21AI3'+
06*,1A31'+
07*21A341
08*23A114
09*23A141
70*23A411
71*IA1234
72·1A2134
73*lA2314
71+*1112.341
75*2A1134
76*2A1314
77*2A1341
78*2A3ii'+
79*2A3141
&O*2A3411
b1*A11234
d2*A1a34
/)3*A1231'+
&,+*A1Z341
jj~*"21134

b6*A21314
b7*A213'+1
68*A2311'+
1:19*A23141
'.I0*A23411
91*111234
92*112134
9:3*112314
9'+*11<:341
95*12113'+
96*121314
97.1213'+1
98*123114

114*223114
115.223141
116*d3411
117*212134
118*Z12314
119.212341
120*232114
12h2321'+1
122*,3Z'+11
123*;::11234
12'+*d3214
125*.::13241
126*231214
127*231241
128*,,34211
129*211324
130~21312'+

131*213 .. 21
132*231124
133*231421
134*234121
135.211342
136*213142
137*213412
138*2311:'2
139*<:31~12

140*234112
141*322114
1'+2*322141
143*322411
144*321214
145*:;21241
146*324211
147*321124
148*321421
149*324121
150*321142
151*321412
152*324112
153*342211
1~4*~44::1a

155*;j4,112

99*1231~1

100*123411
1u1*Z11134
1LJ2*211::i14
103*211341
l(j4*213114
105*<:13141
106.213411
107*231114
1U8*<:31141
109*231411
110*234111
111*221134
112*221314
113*2213'+ 1

Figure 5-Short reference table for test patterns

network analysis since, as two-tenninal configurations,
they identify unique driving-point functions. The technique of generating the nunlber of external tenninals is illustrated in Figure 3. Configurations can be identified
which have' the same external configurations, but
differ in that their internal tenninals are joined or
left disconnected.
From H(4, 2) in Figure 1 it is feasible to generate
network functions from four-ports of known symmetry.
Two examples, Figure 7, define the problem to be
solved next; namely, to eliminate redundance due to
symmetry of the network.

Thin-film

Re

networks

Thirteen unique network functions are attained from

both device A and B in Figure 7. Each circuit configuration is represented by one of the thirty-one H(4, 2)
configurations, and may be identified by the letter A or
B next to the appropriate coded H(4, 2) word and under
the circuit it identifies. The eighteen coded words not
representative of unique network functions, do identify
redundant configuration::; due to rotation of the device
about its axis of symmetry. Redundant configurations
are designated by A and B under the appropriate circuit configurations.

Reference tables for test patterns
To test devices and systems with a small number
of terminals, say z < 10, reference tables to identify
unique test patterns are desirable. From the test pat-

Programmed Test Patterns for MultiterrrJnal Devices

U=--123011 ••

u"auaSi

n •• IAlUA

11"23.&,.
U"UU<311

In.....,U

U"·dSl.U

J"'"
...
na

U ••.,;I:lU_

:'.d~l.

u . .",z3.u

• I.",2U'

.a.,,)oo"u

.._",un

_lolIo"'.

)0012-"

"1.,t.l2~

".12""3

U"·dlll"

TieloU.,,",

1l0.cl'12"
Ul.lll,:.

"O.olblcl

.!.~,I"/.I

2h1Mol;"

.,.•• UlE!.

01""l'"

~

.. , ...o!

2.2e ....JIGI
2,.' .... "..
2s.-1112l8(

U1'e2U"ll

"'·.:""'U
...... "oi,..
a.z.... , .. ,)10

....... 2)-

J~ .... ,.,c.i!

,,,.o/,,,",l.
1l~.211"'"

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"-J

IOBOUND

(2)

where
TIMELEFT-is the time left in the current quantum
and

~,

IOBOUND -is a status word in the PSA that
indicates whether the user is
awaiting the completion of an I/O
operation.

To Page Access Word
Figure 6-PAGETABLE and PAGETIME

When a page of memory is needed for swapping purposes, a search is performed on PAGETABLE to find
the page with the smallest value. Value is infinite if the
system bit is set or zero if the occupied bit is not set.
In all other cases, a function is evaluated which is the
sum of
PAGETIl\1E - clock

+ Value (I)

(1)

where

If no PSA satisfies condition 2, the RPSAPTR advances until a PSA that is not IOBOUND is found and
sets that program to run another quantum.
It is clear that a user who requires extensive swapping
will contribute significantly to the flow of page traffic

Virtual Memory Map
page access

non-reentrant

o
I
clock

is a set of status bits from P AGETABLE
is the current reading of the real time
clock
page

1

and
Value

is given by a function that maps bit configurations into time values.

PAGETIME is set to clock + 1 hour whenever a page
is referenced and is shifted right one position every
hour to prevent overflow. The values in PAGETIME
do not age linearly because of this shift; however, the
function is continuous and is not inaccurate in the
region where the clock is set back one hour and PAGETIME entries shifted.
A user's reference to his virtual memory occurs upon
detection of an illegal write interrupt, and the system is
then table driven based upon the above tables and the
virtual memory map (Vl\1M) in the user's PSA. Each
word in the VMM is either a page access word or a

reentrant

page access word

I
page

B'iu:ure 7-Page access word

08-3

to and from the disk. IVloreover, such a user will receive poor service if the page traffic flow is heavy .
In order to cope with this situation, a more sophisticated scheduling arrangement is required. This kind of
extension to the scheduling algorithm should be adaptive in nature, that is the system should recognize the
existence of a problem situation and proceed to 'tune
itself up.' Further, detection of the problem condition
as well as modification of the scheduling tactics must be
easily computable if an undesirable increase in system
At present, 08-3 includes an initial version of a demand scheduling strategy called the debogging algorithm. This algorithm governs the allocation of processor memory so as to minimize page traffic flow in the
presence of varying user requests.
Conceptually, the algorithm can be viewed as a high
priority pointer that is cycled around the user queue
independent of the RPSAPTR. If a user is designated
the high priority user, then his in-core pages increase in
value, and he is automatically placed second in line in
the swapping queue for requested pages.
In effect, the debogging strategy tends to delay users
whose page requests are heavy with respect to current
page traffic flow, and then run such users with greater
priority for a period of time during which they can
occupy a substantial amount of core.
In particular, the algorithm governs the behavior of
the following independent categories of events:
1. Advancing the high priority pointer
2. Delaying troublemakers, and
3. Rehabilitating former troublemakers.
These categories are now described in greater detail.
The high priority pointer, HPP, is advanced to the
next user whenever one of the following conditions is
satisfled:

K 1 influences the rate at which the HPP will shift to
the next user if the current user is busy swapping. K2
is simply a constant that governs the cycle rate of the
HPP.
If any of the conditions 3, 4, or 5 is satisfied, then
WCT: = SQ: = QCT: = 0
PRj: = 0

(i = 1, ... ,n)

(6)
(7)

wher~

SQ

-is the avera,ge length of the swapping
queue

QCT

-is the number of useful quantums of computing (i.e., time not spent in the idle
loop).

and

The second category concerns the troublemaker. A
user is a troublemaker if only the mass storage wait bit
of'his IOBOUND word is set, and if
.. (8)

where
K3

-is a constant that determines the nunlber of swap requests a user must generate
in order to qualify as a troublemaker.

The last troublemaker is defined as the troublemaker
that is located the greatest distance from the HPP in
the direction of pointer rotation. A troublemaker is
delayed by setting the delay bit in the IOBOUND
word of his PSA. The last troublemaker will, in fact,
be delayed if:
(SQ ~ K4) & (SQ ~ K5)

The user logs off

247

(9)

(3)

where
The user becomes I/O bound

(4)

SQ

-is a counter that contains the current
length of the swapping queue

SQ

-the average length of the swapping queue

K4

-is a stabilizing factor

K5

-determines heavy page traffic flow.

(5)

where
WCT -is the amount of wall clock time that has
elapsed since the HPP was advanced
PRj

-is the page request word in the ith user's
PSA. PRj is incremented by one each
time the ith user requests a page

and

If condition (9) is satisfied then

a.nd
K1, K2-are constants.

SQ: = SQ: = QCT: = 0

(10)

Spring Joint Computer Conference, 1969

248

The final category _provides' for the rehabilitation of
former troublemakers. A former troublemaker is a user
whose delay bit is set. The closest former troublemaker
is defined to be the former troublemaker locat~d the
least distance from the HPP in the direction of pointer
rotation. The closest former troublemaker may be rehabilitated by clearing his delay bit. This will occur when
(QCT ~ K6) & (SQ

< K7)

(11)

where
K6

-is a stabilizing factor

and
-determines relatively light page traffic
flow.
The effect of the preceding debogging strategy is to
match available processor memory· to user demands.
If this cannot be done, then an obvious troublemaker
is delayed, and, after a period of stabilization, the situation is sampled again to determine whether an acceptable match has occurred. If not, then another troublemaker is delayed, and so forth, until a match is
achieved. Conversely, jf user demands are not overloading the swapping queue, then former troublemakers are rehabilitated, one at a time. Of course, if
several users require large quantities of physical memory, the recidivism rate will be high.

System performance
System performance measured in terms of system

overhead tends to be quite good. If the total number of
user hours for a month is compared to the total amount
of billable CPU time for that period, it turns out that
the system spends slightly more than 65 percent ti..me in
an idle loop. Of course, this might indicate that the system is heavily I/O bound; however, test measurements
indicate that this is not the case.
In another test, switching time was measured by
chosen from three categories:
1. Compute bound
2. 65K swap bound
3. I/Obound

The 100 millisecond quantum was then reduced until no
useful computing took phwe. This break-even point
occurred at four milliseconds.
ACKNOWLEDGMENTS

The authors are indebted to Steven K. Sullivan for his
incisive comments, useful criticisms, and system programming support.
REFERENCES
1 J DAVIS
A brief description of OSCAR (Second Revision)
asu Computer Center cc-68-45
2 J MEEKER
OSU Computer Center cc~8-30
3 F DAYTON W MASSIE
OS-3 teletypewriter editor manual (Revised)
OSU Computer Center cc~8-17

Virtual memory management in a
pagil1.-g environment
by NORMAN WEIZER and G. OPPENHEIMER
Camden, ~ew Jersey

INTRODUCTION
The Spectra 70/46 Time Sharing Operating System
(TSOS) is designed to be a combined time-sharing
and multiprogramming system that will support up
to 48 conversational users or a combined total of 64
batch and interactive tasks processing simultaneously.
. The memory management subsystems of TSOS
maintain complete control of main core memory, the
drum backing store and the virtual memory facilities
of the entire system. The virtual memory management
subsystem controls the allocation and release of the
backing store space, the organization of the 2 million
byte virtual memory and the characteristics (the control-bit settings) of the allocated virtual memory space.

Hardware description
A short description of the relevant spectra 70/46
Processor! features is presented here to provide a background for the discussion of the virtual memory management subsystem. The 70/46 is basically identical
to the spectra 70/ 45 ~1od II Processor2 with the addition of a flip-flop implemented hardware translation
memory. The dynamic translation facilities of the
70/46 are provided by this translation memory and
the special functions implemented in the read only
memory.
The translation memory (TM) contains 512 half
word elements each of which represents a single virtual
page. The page size used within TSOS is 4096 bytes,
and thus the virtual memory is a linear space3 of two
million bytes.
Each half word element in the translation memory
is composed of a set of control bits and a physical
page number, shown in detail in the Appendix. The
control bits indicate whether the page has been modified, whether it has been accessed, whether it may

be modified, whether access is restricted to privileged
users and whether the page is in memory. If a referenced page is in memory the physical page number
is used in conjunction with the 12-bit displacement
field of the virtual address to determine the physical
address. If the page is not in memory the hardware
generates a paging queue interrupt, and the software,
utilizing a hardware special analysis function, determines the page (s) required and causes the page (s)
to be brought into main memory.
The 24 bit virtual address format is shown in Figure 1. It represents the address formulated after all
The Page and Displacement portions of the virtual
generated by the 18-bit address arithmetic. If the sum
of the least significant 18 bits of the base register,
an index register, and a displacement field of an instruction would normally cause a carry into the 19th
bit of the address field, this carry is lost and an address
wrap around to the lower boundary of a segment takes
place, thus providing a modified form of segmentation.
The segment, unused, and D bit fields of an address
can be changed in the base registers by using the normal
binary addition capabilities of the processor. TheD bit is used to obtain direct (untranslated) addressing
capability while in the 70/46 or translation addressing
mode. * Only privileged Control system functions
can use this facility.
.
The nine bit field formed by the segment and page
bits of the virtual address forms the index which is
used to determine which of the 512 translation memory
elements corresponds to the addressed virtual page.
* The Spectra 70/46 is also capable of being run in a 70/45 mode.
In the 70/45 mode no address translation takes place and the
address space is limited to 262K bytes.

249

250

1 bit
D

Spring Joint Computer Conference, 1969

2 bits

3 bits

6 bits

IUnused ISegment I PAGE

12 bits
Displacement

The six page bits contained within the indexed Tl\1
entry (see Appendix) are concatenated with the 12
low order bits of the virtual address to form the 18
bit physical address actually used by the processor
Two memory protection capabilities are provided
in the 70/46. The first capability is provided by a set
of protection key locations associated with main core
memory. These keys are only used in the 70/45 mode
of processing, although they are also operational in
the 70/46 mode. The second capability is provided
by the translation memory implementation and is
only available when in the 70/46 mode. A nonprivileged
routine in the 70/46 addressing mode, or a privileged
function not using the direct (untranslated) addressing
capability, cannot address information unless a translation memory element for that task allows translation
to that memory location. In this way, unless the entries
for two users are simultaneously loaded into translation
memory, no user can access the private information
of another user. Also, the control bits of the translation
memory entries prevent nonprivileged access to unauthorized information and also prevent modification
of code which is executable only.
The backing store for the 70/46 is a fixed head drum
of either 800 or 1600 tracks. The track capacity of
the drum is approximately 5000 bytes. By assigning
a single 4096 byte page per track, the 3600 RPM drum
can accommodate 60 page transfers per second. The
time to transfer a page between core and drum is approximately 13.65 msecs, thus leaving about 3 msecsfree time between the end of one page transfer and
the beginning of the next. This free time (gap time)
is an upper bound on the amount of processing that
may be performed between page transfers if the full
drum transfer rate capability is to be realized.
All of the I/O operations, including the paging transfers, use untranslated or direct addresses. This requires
that the virtual to physical address conversioilmust
be made before an I/O is initiated. Also, any pages
involved in an I/O operation, including those which
contain the I/O control information, must remain in
core during the duration of the I/O operation.

Paging algorithm
..A...

demand type paging algorith..1U3 is implemented

in TSOS.4 This algorithm limits the number of tasks
simultaneously competing for the processor and main
memory by using a "working set"5 like concept in
compete for processor time and main memory) the
counter of available main memory pages is decremented
to set aside the number of pages it is anticipated the
task will require. This number is equal to the number
of pages used by the task during its previous activation
period.
Rather than fully swapping a program's working
set into memory or allocating specific memory pages
for the task at activation time, however, only those
pages required by the task's first instruction are actually pre-paged into core. During a task's active
period, its pages in core are normally considered nonpageable. * When a task is deactivated, the counter
of available main memory pages is incremented, and all
of the task's pages in core are placed on the page-out
queues.
When a task is blocked by a paging queue interrupt,
pages are chosen from the page-out queues and the
appropriate drum transfers are initiated. During the
period in which the required pages are being brought
into core, other active tasks are placed in control of
the processor.

Memory management design considerations
In general a memory management subsystem for
a multi-access system should have the following char.acteristics :
1. Protection-no user should be able to destroy

2.

3.

4.

5.

6.

the data beionging to another user or to the
system as a whole;
Privacy-without authorization, no user should
be able to access the data belonging to another
user or the private system data;
Shared Code Use-several users should be
able to simultaneously use the same physical
copy of commonly used routines or programs;
Flexibility-the full memory management capabilities provided by the hardware, consistent
with the protection and privacy considerations,
should be made available to the user programs;
Ease of Usage-the memory management facilities should be provided to the user in a manner which allows them to be easily used;
Low Overhead-the use of the memory man-

* An exception to this rule occurs if a single task requires more
pageable main memory space than is available in the system.

Virtual Memory Management in Paging Environment

to the system as possible, consistent with the
other characteristics;
7. Integrity of Design-the memory management
subsystem should not be designed as a unit
separated from the remainder of the operating
system. It must be designed as an integral
part of the overall system but with clearly
defined boundaries and interfaces. The clearly
defined boundaries and interfaces prevent a
great many problems in the implementation
and debugging phases of operating system
development. (The method used to develop
the scheduling and paging algorithms for TSOS
is described in Reference 4.)
8. Modularity-the memory management· subsystem should be designed as a set of modular
routines. There should be simple and sharply
defined interfaces between the various routines
to simplify implementations and debugging
problems.
In the following sections a description of the TSOS
Virtual Memory Management Subsystem is provided
and an attempt is made to show how all of the above
criteria were met within the hardware environment
described above.
Virtual memory organizatian

The two million bytes of virtual memory are divided
into two equal units. Each user of the system is permitted to use the first one million bytes for code and
data areas related strictly to his own task. The second
one million bytes are reserved for Control System
functions and shared code.
In terms of the use of the translation memory this
means that the first 2.56 entries are used for private
control of the processor the previous task's translation
memory entries are stored in main memory, and the
new task's entries are loaded into the translation memory. During this entire process the upper 256 entries
in the translation memory are unchanged.
This organization of the virtual memory, aside
the Control System to be written using virtual addressing and at the same time to have full access to
all user areas. Since the task in control of the processor
has its entries loaded into the translation memory
while it is running, the task's memory is directly
available to the Control System through the translation
mechanism. (The converse is not true, in that the

251

Control Program pages are privileged and the pages
containing shared code are executable only, preventing
user code from accessing Control Program information
and from modifying shared code.)
If the virtual memory were not divided as it has
available to each user, the Control System would have
and would ht:we required much more code to be resident,
would have been appreciably greater.
Backing store allocatian

Although each user task has a private one million
byte virtual memory, the memory is not actually
usable until it is dynamically allocated by means
of the memory management macros; that is, until
a realtionship is set up between a page of virtual memory and a page of backing store. In a conventional
processor this is analogous to saying that the address
space (which is normally equal to the physical memory
size), is not usable until the program is loaded into
memory. And then only the assigned portion of the
total address space (memory) may be referenced.
Within TSOS user pages are allocated when a program is loaded and when additional space is dynamically requested. When a page is allocated, a translation
memory entry is initialized for it and a drum track
is assigned. This track is associated with the page
on a permanent basis, i.e., until the page is released
and the translation memory entry is no longer valid.
The relationship between the backing store track
and the page of virtual memory is maintained even
while the page is in main memory for the following
reasons. The number of pages of main memory is small
compared to the number of pages on the backing store.
Therefore, the marginal gain in drum tracks available
to the system through the use of a dynamic assignment
system would be small. General utilization of the drum
tracks in this manner would also increase the probability of binding the system intolerably should the
drum become saturated.
From another viewpoint, the fact that there is only
a single page per track means that schemes which
reassign drum tracks to core pages that must be written out, so as to optimize drum utilization in a multiple
page per track environment, are not applicable in
the environment of TSOS.
In summary, until a virtual page is requested and
backing store assigned to it, the virtual memory space
it represents is not usable. Any attempt to access an
unallocated page is detected by a combination of hard-

252

Spring Joint Computer Conference, 1969

ware and software and is treated as a program addressing error.
Virtual memory classification

To regulate the use of virtual memory, and to simplify its request, particularly within the Control System,
virtual memory is divided into six somewhat arbitrary classes. The address assignments for the six
classes are shown in Figure 2. The characteristics
of each class are described below.
Class 1 Virtual M emory is occupied by the resident portion (kernel) of the Control System.
All Class 1 pages are privileged and nonpageable.
There are no drum images of these pages. At
present there are 10 Class 1 pages in TSOS.
Class 2 Virtual Memory is occupied by the non-

resident portion of the Control System. All Class
2 pages are privileged and pageable and may
be marked as executable only, depending upon
the nature of the routines occupying them. There
is a drum image for each of these pages.
Classes 1 and 2 virtual memory are preallocated
at system generation. The boundary between these
two classes (CILIM) may be varied from system to
system. dependent upon installation requirements.
Class 3 Virtual M emory is occupied by the dynamically acquired resident portion of the Control
System. All Class 3 pages are privileged and nonpageable. There are no drum images of these
pages. This memory class is used for task control
blocks, terminal I/O buffers and certain system
work space. It is also dynamically released when
the requirement for resident space iessens.
Page
Number

0
Each
User's

Class 6 Virtual Memory
C6 LiM

~

Class 5 Virtual Memory
256

C1 LIM

Virtual
Memory

Class 1 Virtual Memory
Class 2 Virtual Memory
~

C2 LIM

Class 3 & 4 Virtual Memory
511
Figure 2-Virtual address space assignments of
virtual memory classes

System
Virtual
Memory

Class 4- Virtual Memory is occupied by the non-

resident work space dynamically acquired by the
Control Program and by the shared code called
by the users of the system. All Class 4 pages are
pageable and have drum images. The Class 4
pages used by the Control System are marked
privileged, but those used for shared oode are
marked nonprivileged.
Virtual memory Classes 1 through 4 constitute the
system virtual memory. As a group these four classes
must be contained within the one-million bytes of
address space available to the system. They reside
in the upper one-half of the translation memory and
are not changed (swapped) in the translation memory
as control is passed from user to Uh'er.
Virtual memory Classes 5 and 6 constitute the user's
virtual memory. Together these two classes are limited
to the one million bytes available to the user. They
occupy the lower one-half or the translation memory
and as control is passed from user to user the Class
5 and Class 6 translation memory entries for each
user are swapped out of and into the translation memory. This means that any data stored in a user's Classes
5 and 6 Virtual Memory cannot be accessed using
virtual addresses when that user's entries are not
loaded into TlVI. (This, in turn, means that the system
must use direct, non-translated, addressing to access
user memory for a user that is not in control of the
processor.)
Cla"ss 5 Virtual Memory is occupied by dynamically allocated pageable areas acquired for the
specific user by the Control System. These pages
may he marked privileged or nonprivileged. They
are used for task dependent information such as
task dependent virtual memory tables, protected
file control blocks, program loader data, data
maintained by the interactive debugging language
and I/O buffers acquired for the task by the system.
Class 6 Virtual Memory is occupied by dynamically allocated pages acquired by the user for
his code and work areas. The pages of Class 6
memory are under control of the user task.

The boundary between Class 5 and 6 memory
(C6LINI) is completely variable and depends upon
the requirements of each individual task. Normally
Class 5 memory occupies the 16 pages fronl page 240
through 255, and Class 6 memory occupies the 240
pages from page 0 through 239. Each memory clas~
is allocated contiguously such that a page of Class 5

Virtual Memory Management in Paging Environment

memory is never bounded on both sides by pages of
Class 6 memory or vice-versa.

Shared code
N onprivileged 'shared code offers the potential advantages of savings of main memory and backing
store space plus a reduction in the paging rate. However, additional memory management control logic
is required to realize these advantages. In systems
with true segmentation, the segment is nomlally the
unit which is shared and shared code may be used by
attaching the called segment to the virtual memory
of the calling task. This degree of generality in a system with a linear address space requires more control
logic than the potential advantages warrant.
With a linear address space it seems preferable
to allocate some of the address space for shared code
and to take this space out of the system's area of virtual
memory. This procedure eliminates the need for any
shared code gains or loses control of the processor.
I t also permits the same algorithm to be used for paging the Control System and the shared code, simplifying the design and implementation of the paging
subsystem and thus reducing system overhead.
The major disadvantage of this approach is that
the (virtual memory) space for the shared code must
be allocated for every user, whether or not he uses the
shared code. However, it is felt that the low overhead,
ease and flexibility of use, and ease of implementation
more than make up for the loss of some address space.
In TSOS the system administrator determines for
his specific installation what major routines will be
considered eligible for sharing and makes this determination known to the system by means of a special command. He may choose only RCA supplied software
such as the File Editor, and the Interactive Fortran
compiler; or some user designed programs; or any
combination of the two. Upon the first call for one of
these shared routines the loader allocates the amount
of memory needed to load this routine. This memory
is allocated as nonprivileged, execute only, Class 4
virtual memory. Upon succeeding calls for the same
During execution each user of the shared routine
uses the same physical (and virtual) copy of the routine
as all other users.

Macro caUs
The acquisition and release of virtual memory and

253

the control of the characteristics of allocated virtual
memory are the major services perfomled for users and
other Control System functions by the virtual memory
management subsystem. These services are requested
by means of macros which generate standardized
either Supervisor Call instructions (SVCs) or standardized branching conventions, both of which provide
clean interfaces, an invaluable aid in the debugging
phases of complex system development.
The macros are named REQM (request memory),
RELM (release memory), and CSTAT (change memory status). There are two forms of each macro, one
which may be used by nonprivileged and privileged
(Control System) routines, and the second which is
restricted to privileged routines only.
The nonprivileged forms of the REQM and RELM
macros permit the user to request and release Class
6 memory in multiples of one page, with a maximum
of 64 pages per call. If the address spaces and backing
store space is available, the requested memory will
be allocated in the first unallocated area (lowest
available area in the address space) large enough to satisfy the request; or if the user so ~pecifies, the memory
will be allocated starting at a specific address.
The nonprivileged form of the CSTAT macro allows
the user to change the status of any page in Class 6
also provides the mechanism for users to request that
specific Class 6 pages be made pageable or nonpageable. *
The privileged fonus of the virtual memory macros
allow Control System routines to operate on any page
in Classes 2, 3, 4, 5 and 6 virtual memory. The option
of the CSTAT macro which changes a page's status
classes. The option to make pages pageable or nonpageable is available only for memory Classes 2, 4, 5
and 6. This option of the CSTAT macro is the most
heavily used as it permits the Control System to lock
into (unlock from) main memory pages which are
(were) required to be resident for I/O operations. **
The privileged forms of the REQ:NI and RELM
macros permit Control System functions to request
and release Classes 3, 4 and 5 virtual memory. Classes

* Provision exists within the system, in certain well defined
situations to permit users to use this option of the CSTAT
macro. The limit of the number of pages that a user may make
nonpageable is established based upon system-wide parameters
and conditions set at task initiation.
** All

I/O is done with nontranslated addressing and thus commands must contain physical addresses and buffers must not be
moved until the I/O operations complete.

254

Spring Joint Computer Conference, 1969

1 and :2 virtual memory are structured at system generation. In addition to the full page allocation capability
of the nonprivileged version of the macros, partial
page allocation is provided in the privileged versions.

Partial page allocation

Many Control System functions require different
sized areas of memory during their execution. This
memory may be required specifically for a single task
or it may contain system wide information. Memory
space which need not always be resident and which
is required for a single task is acquired as Class 5 memory; system wide information which is pageable is
stored in Class 4 memory and user dependent or
system dependent infonnation which is nonpageable
is stored in Class 3 memory.
To conserve address space, better utilize main memory and reduce the paging rate for Control System
pages, Classes 3, 4 and 5 memory are allocatable in
partial page units. The units of allocation are 8n bytes
where 2 ::; n ::; 509.
Any request for larger size areas are al10cated in
full page increments. Any size area may be requested,
but during the allocation process the size allocated is
rounded up to the next larger standard size. This standardization, making all allocations multiples of a single
quantum size, eases both the allocation and garbage
collection processes employed.
Each page allocated is treated as a separate unit
so that no partial page allocation crosses a page boundary. This serves two purposes. First it eases the record keeping involved by limiting the number of areas
considered in a single operation. Second it prevents
dynamically acquired I/O buffers from being allocated
across page boundaries.
The latter is significant in that otherwise it would
be necessary to page contiguous virtual pages into
contiguous main memory pages, and this wou1d vastly
complicate the paging and physical memory management subsystems.
To manage the partial page allocation two linked
lists are maintained in each subdivided page. One list,
termed the main list, links all of the areas on the page
in address order. The second list, termed the free list,
links all of the unallocated areas in area size order,
with the smallest area at the head of the Jist. The links
of both lists are eight bytes long. The entries in the
links include a free bit, which is used to indicate unallocated areas, a size field, forward and backward link
fields and a two byte integrity field used by software
to, check that the link was not destroyed by some other
software routine.

are also maintained by the system to manage partial
page allocation. Two of the tables are maintained in
Class 3 memory to control the Class 3 and Class 4
faemory partial page allocations. There is also a corresponding partial page table in each user's Class 5
memory which is used to control the Class 5 partial
page allocations for that user. The entries in each table
are identical. They consist of the virtual page number
of the page to which they correspond and the size
of the largest free area on the page. There is one entry
for each page which is subdivided for partial page allocation.
The placement of the memory links on the same
page as the partial page areas presents the possibility
of malfunctioning system components destroying
the links. However, rather than proving to be a. hindrance, this link placement proved to be a great aid
in system debugging. This is due to the fact that the
memory management routines will often be the first
system function to find the destroyed link. This, in
turn, helps to avoid the problem that some other system function will malfunction, because it uses an adjacent area which was also destroyed, allowing many
bugs of the type which would only occur at widely
scattered intervals to be more easily tracked down.
.l'Jerr.my management tables

A relatively complex table structure is required to
support the memory management functions of T30S.
These tables support the physical memory management
and paging subsystems along with the virtual memory
management subsystem. They are used primarily to
maintain allocation status infonnation for the major
memory resources-the core pages, the drum pages,
The allocation status information for drum pages
and for system virtual memory pages is maintained
in bit-per-page maps cal1ed the Paging Drum Memory
Map and the System Virtual Memory Map. These
tables are used when the request memory (REQM)
macro code must find an unallocated drwn page during
the allocation of a page of pageable virtual memory
and when it is necessary to detennine the address- of
free pages during the allocation of system virtual memory. These tables are also used during the corresponding
RELM (release memory) processing.
The core status data are maintained in two tables
cal1ed the Physical Memory Map and the Physical
Page Allocation Table. Each entry of the Physical
Memory Map indicates whether the page is free or
aJIocated, the memory class data for nonpageable
pages and certain reservation inforrnation. The Ph)~-

Virtual Memory Management in Paging Environment

ical Page Allocation Table contains the drum address
(for pageable pages), the I/O count (the number of
I/O operations in process or scheduled into this virtual
page), link space for the page out queues, and the
address of the Virtual Page Toole entry for pageable
pages.
The System Virtual Page Table is a two part table.
The main portion contains the core image of the entries
loaded into the translation memory for the system
virtual m~mory. However, when the pages represented
by these entries are not in core, the cylinder portion
of the backing store address is maintained in these
entries. The secondary part of the table is used to store
the drum track portion of the backing store address.
The above described tables are maintained in Class
1 virtual memory. They are system wide tables. In
addition, there are four private tables maintained for
each user. They are the Block Address Table and the
associated User Virtual Page Table which are maintained in Class 3 Virtual Memory, and the User Virtual Memory Map and the Class 5 Partial Page Table.
The Block Address Table entries for each user are
maintained within the Task Control Block (TCB).
The TCB contains the master infonnation about each
of a task are used within a special function to cause
the User Virtual P .1ge Table entries to be loaded into
the translation mealory when the task is to be given
control of the processor, and conversely when these
entires are to ce stored in core when control of the
processor is removed from the task. The space used to
store these entries is maintained in System Virtual
Memory to guarantee their accessibility by the Control
System at any time. Otherwise, they would be accessible only when the user was in control of the processor.
The User Virtual }Iemory J\lap parallels the System
Virtual Memory Map and is allocated in the user's
Class;) memory. The Class 5 partial page table is also
allocated in the user's Class 5 memory. It is used to
('ontrol the partial page allocation of the user's Class 5
memory.
SU1IMARY
The salient h'l.rdware features of the system described
are: a linear a::ldress space of 512 pages of 4096 bytes
each; a main memory of 64 pages; a single level page
per track backing store of 800 or 1600 pages; and the
use of a 512 entry translation memory to effect the
virtual memory of the system.
The facilities controlled by the virtual memory
management subsystem described include the organization of the virtual memory, the subdivision of the
virtual memory into classes, the management of the

255

shared code within the system, and the allocation of
backing store and of partial pages.
Within the context of the hardware structure, the
major aspects and advantages of the described software
system are summarized below.
The partitioning of the virtual memory to concurrently accommodate the system and a single user reduces
translation memory swapping overhead and provides
the system code with full accessibility to all user code,
while still pennitting the system code to be written
The division of the virtual memory into classes
structures the use of the virtual memory, regulates
its use and simplifies the request and release procedures,
especially within the Control System.
The incorporation of sharable code wit~ in-,he system
virtual memory affords its direct accesblbllity to all
users, pennits a single page table to be maintained
for the code, and allows the same paging algorithm to
be applied to shared code as is used for system code;
but it requires all users to give up the same amount
of virtual memory for the shared code, whether or not
they use the shared code.
The allocation of backing store only when a page
of pageable virtual memory is allocated enables more
users to be run concurrently with a given level of backing store than if the backing store was allocated for
the entire user virtual memory, regardless of the user's
ntent to utilize his entire virtual memory.
The maintenance of a relationship between a virtual
memory page and a track on the backing store, even
when the page is in memory, is justified based upon
the real probability that the page may not be modified
and therefore will not have to be written out-if the
backing store association is maintained while it is in
memory; and the added consideration that the ratio
of drum tracks to memory tracks is such that the marginal gain in drum tracks available to the system from
reassigning pages in memory is extremely small. The
drum characteristic of a single page per track is also
a factor in this regard.
The provision for partial page allocation for other
Control System functions, while it increases the calls
on the virtual memory subsystem, provides for better
utilization of memory and easier development of reentrant code.
REFERENCES
RCA Spectra 70/46 Processor Reference Manual
2--RCA Spectra 70/35 45 55 Processor Reference Manual

3 B RANDELL C J KUEHNER
Dynamic storage allocation systems

256

Spring Joint Computer Conference, 1969

CAe M Vol 11 No 5 May 1968297-306
4 G OPPENHEIMER N WEIZER
Resource management for a medium scale time sharing
operating system
CAe M Vol 11 No 5 May 1968313-322
5 P J DENNING
The working set model for program behavior
CAe M Vol 11 No 5 May 1968323-333

APPENDIX
The translation memory

The Translation ~1emory is 512 half-words in size.
Each entry in Translation Memory has the format
shown in Figure 3.
The meaning of each of the control bits and the
physical page number in the translation memory entry
is given below:
P = Parity bit (invisible to the software).
vV = vVritten Into Bit: indicates when set, that the
page addressed in memory by this translation
halfword has been written into. This bit is
automatically set by hardware and reset by
software.
G = Accessed Bit: indicates, when set, that the
page addressed in memory by this translation
halfword has been accessed (read, or written
into). This bit is automatically set and reset
by hardware. Attempted but unsuccessful

1 bit

~I

1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 3 bits

WiG

6 bits

1 bit

I I I ElM I::.1~~I~bsERI H I
u

s

Figure 3-Format of a translation memory entry

U = Utilization Bit: indicates, when set, that the
addressed translation word can be utilized.
This bit indicates, when reset, that the addressed translation word cannot be utilized
(i.e., this virtual page is not in core) and a
Paging Queue Program Interrupt occurs. This
bit is set and reset by sottware.
S = State Bit: Indicates when set, that the addressed translation word is nonprivileged.
When this bit is reset, it indicates that the address page is privileged and can only be accessed by a program operating in the pri'vileged
mode (i.e., a portion of the system software).
When this bit is reset and a nonprivileged
Paging Elror Program Interrupt occurs. This
bit is set and reset by software.
E = Executable Bit: indicates when set, that the
page addrest3ed in memory by this translation
word can be read as an operand or instruction
but cannot be written into. When this bit is
reset, all forms of access are allowed for this
page. If a program attempts to write into a
page with this bit set in the translation word,
a Paging Error Interrupt occurs. This bit is
set and reset by software.
M and H bits are used when the 2048 byte virtual
page mode is used. Under TSOS only the 4096 byte
virtual page mode is used.
Physical Page Number: when the U bit is set, these
six bits contain the six most significant bits of the actual
physical address of the page represented by this T.M.
entry. The full physical address is obtained by concatenating these six bits with the low order 12 bits of the
virtual address. \Vhen the U bit is reset no meaningful
information is contained in this field.

An operational analysis of a
remote console system
by HERBERT D. SCHWETMAN

and JAMES R. DELINE
The University of Texas

Austin, Texas

INTRODUCTION
The Computation Center of The University of Texas
6600 computer through a system called RESPOND.!
RESPOND was written by Control Data Corporation
and has been in operation at The University for more
than two years.
The paper gives a brief description of RESPOND and
the capabilities provided the user. This is followed by
a critical evaluation of the performance and reliability
of the RESPOND system based upon experience
gained in its use. A survey of user reactions is presented
next. Finally, the cost of providing this remote batch
entry service is estimated in terms of percent of system
resources used and system maintenance required.
A description oj RESPOND

The RESPOND system was installed on the CDC
6600 at the Computation Center on ~larch 10, 1967 ,
by the Special Systems Division, Control Data Corporation. This was the second implementation of RESPOND on a 6000 series computer, * and the first under
the SCOPE 2.0 operating system. This version later
became the framework for Control Data's standard
6000 series system-TTY RESPOND.2
A RESPOND terminal is typically a Model 33 or
35 Teletype, with or without punched paper tape
system by providing his password and the account
number to which his computing activities will be
charged. He may then enter data into the system via
the keyboard or paper tape and may create a file by
• The first implementation was at Rechenzentrum der TechHochschule Aachen, Aachen, Germany, on a CDC 6400
m January 1967.
~chen

giving this text a name. Such files then become a
member of the user's private file catalog. Files may
also be introduced into RESPOND from other sources.
Card decks and magnetic tape records can be copied
into files in the user's file catalog.
RESPOND appends a sequence number to each
incoming line of text and, by referring to these numbers,
the user is provided with a limited text-editing capability. A line or group of contiguous lines of text may be
displayed at the terminal by referring to the name of
the file and specifying the desired lines. New lines may
be-inserted in~o the body of the file at any point, and
undesired lines may be deleted by reference to their
sequence number. Two or more files may be merged,
with the new file given a name different from the others.
At the user's option, these files may be copied to
punched cards or printed output at the 6600 site, may
be submitted as programs and data to be run by the
6600, or may be saved by the RESPOND system for
use at a later time. Files which are no longer wanted
may be deleted by the user from his file catalog; those
files which remain are periodically dumped to rmgnetic
tape. In addition to holding all user files, this tape
holds public files, which are accessible as read -only
files by all users, and a list of passwords for all authorized users. This tape is copied to disk storage each
morning when RESPOND is placed "on the air" and
is used to restore the system when RESPOND experiences an unrecoverable failure.
RESPOND files of program source text may be
submitted for compilation and execution. In this
environment, a RESPOND job consists of one or more
RESPOND files, the first of which is a SCOPE control
card file. The contents of this file are identical to the
control card record which would be used if the program
were to be run in the normal (over-the-counter) batch

257--------------------------------------

258

Spring Joint Computer Conference, 1969

environment of the 6600. Thus, the same compilers,
assemblers, utility and object-time subroutines, deck
structures, and error messages provided in the normal
batch mode are available to the RESPOND user. As
will be pointed out in a later section, there are some
Once a set of files have been sub;mitted for execution,
they are locked from further user access until the job
has been run. The user is not able to interact with his
program once it is placed into execution, but he is
permitted to create, peruse, and submit for execution
other files in his file catalog.
After the program has been run, RESPOND wiii
collect those files specified by the user which were
created as a result of a program execution. Typical of
these files is the standard output file which or'dinarily
will contain listable output from a compiler and, in the
case of a subsequent load-and-go, the results produced
by the compiled program. These files are converted into
RESPOND format and are placed in the user's file
catalog. Other special-purpose files may be left with the
operating system for on-site disposal, such as plot and
microfilm files, or magnetic tapes created during
program execution. A user/computer-operator message
facility is available to permit close cooperation on
magnetic tape requirements, log-out times, etc.
The commands of RESPOXD can be divided into
five groups. The frequency distribution of the usage of
these commands is given in Table I. It is interesting to
note that use of commands in the EDIT group far
outweighs command usage in the other groups.
Table I-Command frequency distribution
EDIT group
_______ 61% STATUS group
9%
Clear _________ 10%
FIst (Fast List)
5%
Status ________ 3
Delete ________ 10
List ___________ 1
File ___ ______ 9
BATCH Group ________ 9%
Show _ ________ 9
Submit ________ 6%
Copy _________ 2
Enter ________ 8
Compile ______ _
Display ______ 6
Format ______ 0
Assemble ______ 0
UTILITY Group
12% MISCELLANEOUS ____ 9%
Break _________ 7%
Logout _______ 3
Errors _________ 2
Set ___________ 0
Save _________ 2
Message ____ _
3,775 Commands in Sample

The RESPOND system environment

The CDC 6600 computer at The University of Texas
at Austin consists of a high-speed central processor
with 131,072 60-bit words of central memory and 10
peripheral processors, each with 4,096 12-bit words.

All memories have a 1.0 ~sec cycle time; the central
memory has 32 independent banks permitting an upper
limit of 10 memory accesses per micro-second. The
peripheral processors can read and write the central
memory as well as their own private memories and may
address anyone of the twelve high-speed input-output
channels. The central processor has no input-output
instructions.
Jobs can be entered into the 6600 from card readers
within the Computation Center, from any of five
remote computers which communicate via broad-band
telephone lines, and from RESPOND. On a typical
weekday, about 2,500 jobs are processed by the central
computer, of which some 300 originate at RESPOND
consoles.
The SCOPE operating system at The University of
Texas at Austin requires a resident of 13,000 words of
central memory and occupies two of the ten peripheral
processors. In addition, SCOPE will call upon
the remaining eight peripheral processors from time to
time to service users' I/O buffers in central memory,
load jobs or library routines from the disk, service the
card readers by placing incoming jobs into the input
and attempt to keep the print, punch, plot, and microfilm queues empty.
Central memory is dynamically broken into seven
logical areas called control points. User programs are
assigned to these control points for processing, with the
central processor servicing the program in central
memory of the highest priority which does not have any
incomplete I/O buffers. In practice, one of these seven
control points is required to service all of the unit
record equipment; a second control point is occupied by
the central processor portion of the RESPOND systAm.
The central memory requirement for the former control
point varies between 512 and 8,192 words, while the
latter requires 14,600 words as a minimum and in':'
creases as a function of the activity at the remote
terminals. The maximum available central memory for
user programs is approximately 103:000 words.
the input queue on the disk and are assigned a central
memory access priority of two octal digits. The first
digit varies inversely as the time limit requested and
the second varies inversely a,~ the central memory
space requested. Both requests are" extracted from the
job card which is the first card of the control card
record for the program. Jobs submitted from RESPOND terminals are constrained by policy to a time
limit of 127 seconds and central memory limit of
32,768 words. Since 97 percent of all jobs run at the
Computation Center run in less than 127 seconds; the

Operational Analysis of Remote Console System

RESPOXD time limit is not unduly restrictive. While
these job card parameters could result in a modest input
queue priority had the job been entered through a card
reader, RESPOND assigns to all of its jobs a very high
priority.
The central memory scheduling algorithm is based
upon the following criterion: if a control point is
available, the highest priority job in the input queue
whose central memory request is less than or equal to
the current unused central memory is brought to a
control point. Once there, the job runs to completion,
and its disposable files are collected and routed to the
proper output devices. Since RESPOND jobs are given
a very high input queue priority, they are normally
assured of rapid assignment to a control point.
One peripheral processor is dedicated to servicing
the RESPOND communication line multiplexer, which
can accommodate up to 64 data sets. This peripheral
processor polls all active lines eleven times per second,
packing input characters into the appropriate central
memory buffer and placing output characters on the
line for transmission to the remote terminal. At the
present time 15 AT&T 103A2 data sets are available
through a rotary switching scheme. This dial-up
feature permits optimum usage of the available modems
and also permits a recorded audio message to be returned to the user if he should happen to dial up when
RESPOND is inoperative.
In addition to the peripheral processor required to
service the multiplexer, RESPOND occasionally requests other peripheral processors to assist in file
merging, job submission, etc. Also, small percentages
of certain transient system peripheral processors are
required for job scheduling, job processing, and a
dozen or so other system functions.

259

Every time a RESPOND job is submitted to the input
queue, a DAYFILE message is generated. At some
later time, the job is assigned to a control point and
another DAYFILE message is issued. Since the time of
issue is entered along with the message into the DAYFILE, elapsed time between these two events can
easily be measured. The selection of the statistics was
greatly influenced by similar studies of other remote
console systems. 4 ,5,6
The central processor portion of RESPOND is
activated by SCOPE once every 500 milliseconds.
During the few milliseconds it is active, RESPOND
services all terminals which have completed an input
message in the past one-half second. Generally, this
servicing can be completed and a response placed in
the terminal's output buffer in one "duty cycle";
however, several cycles may be required for the more
complex commands.
Figure 1 is a graph displaying the probability density
curve of the "system response time." This response time
is defined to be the elapsed time between a user supplied
carriage return (end of message) and the beginning of
the first output character from RESPOND.
Figure 2 shows the probability density curve of
"user response time" or "think time." Think time is
defined to be the time between the system response or
"go ahead indication" and the next user input character.
Think time is not really a measure of system performance but is provided in order to allow system designers to see an example of user performance. The

~

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Evaluation of performance
The performance discussed in this section refers to
physical characteristics of RESPOND/user interaction.
The measurements made of this aspect of performance
are of (1) system response, (2) user "think time,"
(3) delay in processing of jobs in the SCOPE input
queue, and (4) a history of RESPOND reliability.
The architecture of the 6600 makes possible easy access
to these measurements, since the peripheral processors
are independent of the central processor and may be
called upon to monitor RESPOND's progress from
time to time. 3
The response time statistics were gathered by a
subroutine in the multiplexer servicing program, which
is resident in a peripheral processor. The processing
delay statistics were gathered by post-processing of
the SCOPE chronological log (called the DAYFILE).

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SYSTEM RESPONSE

TIME

Figure 1--8ystem response time

(SECONDS)

Spri~g

260

.18

.15

Joint Computer Conference, 1969

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MEDIUM

CORE

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THINK TIME (SECONDS)
Figure 2-Think time

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"typical" RESPOND user
in Table II.

IS

further characterized

__

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INPUT QUEUE DELAY

____

~

50

_____

60

(SECONDS)

Figure 3-Input. queue delay

Table II-The typical RESPOND Userl
Time at Console __________________________ _
Number of jobs submittted _________________ _
Computer time ___________________________ _
Number of commands input ________________ _
Number of lines of data input ______________ _
Number of lines of data output _____________ _
Number of disk accesses ___________________ _
Average think time ________________________ _

15.25 minutes
1.12 jobs
8.1 seconds
19
29
71
43
5.5 seconds

Figure 3 indicates the input queue delays for submitted jobs. The small core curve represents the delay
for jobs requiring between 0 and 8,192 words of central
memory, the medium core curve for jobs between
8,193 and 24,576 words, and the large core curve for
jobs between 24,577 and 32,768 words. These curves
were derived from more than 28,000 RESPOND jobs
observed over a 9-month period of time. Although these
curves represent delays primarily due to a temporary
unavailability of sufficient central memory in which to
run the job, it can be seen that the operating system
is rather insensitive to varying central memory requirements.
As was demonstrated in a survey of user reactions,
the most important single attribute of a remote console

system is system reliability. One of the most exasperating events in man-machine interaction is for the man
to spend time keying in a text and then for the machine
~o "lose" it. Thus, in spite of almost instantaneous
response time and a multitude of user-oriented conveniences, an unreliable system is of little value.
RESPOND reliability has been uneven at best.
The types of system failures include RESPOND
bugs, SCOPE failures which cause RESPOND to
malfunction, and hardware failures. Currently, there
is a restart capability which permits recovery from
many of these failures. This restart permits a user's
files created prior to his most recent SAVE command
to be recovered. Thus all failures result in some loss of
files, but in most cases, the losses are minimized.
Other failures cause the loss of all files created since
the time of the last dump of RESPOND files to magnetic tape which, in the worst case, is four hours.
Figure 4 is a history of all RESPOND failures from
September 1967 to January 1969. The ordinate of the
graph is the ratio of the number of failures per thousand
RESPOND jobs submitted. It should be noted that
this ordinate is a logarithmic scale. Currently, the
ratio of unrecoverable failures (dump tape reload) to
recoverable failures (restart) is about 1 :10.

Operational Analysis of Remote Console System

261

to do the things it should do, and improvements that
could be made to the system. In the first category,
the single biggest complaint was the unreliable nature
of the system in saving user files from one session to
the next. A new user quickly learns (usually the hard
way) that newly created files should be copied to punch
cards, magnetic tape, paper tape, or the printer as a
precautionary measure. These files can then be reintroduced as RESPOND files with minor inconvenience to the user. Table III presents a tabulation
of users' ratings of RESPOND's reliability.

100

Table III-Users' ratings of RESPOND's reliability
1~~~~~~~~~~--~~~~~~~

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67

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A

M

J

J

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SON

68

D

J
69

DATES
Figure 4-History of RESPOND failure rat.e

Certain sYstem failures include those which involve a
failure in the communication equipment. As initially
installed, RESPOND made no check of the modem
status. In some cases, a telephone line was inadvertently disconnected, but the user's password
remained logically "in use." With the installation of
the dial-up network, this created a serious problem,
since a user could no longer select his point of connection to the multiplexer. A local modification added
a test for "modem connected" status to the multiplexer
servicing routine and automatically initiated a LOGOUT if a disconnected modem was found. This modification has virtually eliminated all RESPOND
failures due to communication equipment malfunctions.

User reactions
Initially, RESPOND passwords were issued only to
faculty and staff personnel and selected graduate
students. This was due in part to the novelty of the
system and a feeling of a lack of need on the part of
many potential users. More recently, the user population has grown to indude graduate students in many
disciplines and certain undergraduate classes as well.
Presently, there are 142 active passwords outstanding
with 1,194 files in their file catalogs.
A questionnaire was recently distributed to .all
RESPOND users. They were asked to comment on
their usage of RESPOND, to give their opinions of
the reliability of the system and to suggest improvements which they felt could be made to the system.
Complaints from the user population can be easily
broken down into two groups: failures of RESPOND

Rating

Percent of Responses

Excellent ___ _______ _____ ____ ______ ____ __ __ __ _ 2.3%
Good________________________________________ 18.2%
Fau_________________________________________ 41.0
Poor ________________________________________ 29.4
Unusable ____________________________________
9.1

Two highly desirable features of RESPOND are the
control card compatibility with the batch system and
the availability of the entire system library to the
RESPOND user. These features eliminate duplication
of programming and system maintenance in the applications software area and permit a user to easily
switch between normal batch processing and RESPOND without fear of system incompatibility. A
summary of programming languages utilized by users
who answered the questionnaire is given in Table IV.
Table IV-Programming languages utilized by RESPOND users
Programming Language

Percent of
Users Responding

FORTRAN _________________________________ 98%
ALGOL ___________________________________ - _ 22
LISP________________________________________ 22
COMPASS ________ _____ ______ ______ ____ _____ 20
Other _________________________________________ 5
L6 ___________________________ :_____________
2
SNOBOL ___________________________________
2

The improvements which were suggested included
the implementation of a context-oriented text editor,
provision for a conversational or interactive capability,
and modification of some of the system-wide services
to limit the amount of printed output for RESPOND
users. The first and third suggestions are particularlr

262

Spring Joint Computer Conference, 1969

important when the remote console in use has a slowspeed printer. The most consistently suggested improvement was that reliability and dependability be
improved. The group making this suggestion stressed
the idea that RESPOND is a useful tool in their work
but that this usefulness would increase as system
integrity and dependability improved.
Those who had the most praise for the system were
the 6600. They tended to have longer sessions at their
terminals and were quite creative in their handling of
multiple files. One graduate student claimed he completed his research for his doctoral dissertation a year

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• Often, the remote console system is just taking up
"slack" in the system resources.
• The remote console system can ease the load on the
nonnal batch processing portion of the computation center.
It cannot be denied that system interference, the
occupation of valuable memory space and a control
point, and the use of one dedicated peripheral processor
by the remote console system represent tangible costs.
Table V shows the utilization of various system resources over a period of one month.
Table V-RESPOND utilization of system resources
Maximum Average Minimum
Characters of disk storage
required for RESPOND files __
Central memory words required
by RESPOND ______________ 29,800
Percent of available central
processor time used by
RESPOND* ________________ 6.9
Percent of available peripheral
processor time used by
RESPOND* ________________ 18.1

14.5xlQ&

22,100

14,600

4.7

0.39

14.1

12.5

The next two figures illustrate the demand made of
certain system resources as a function of the number of
* These figures do not include time required to run the programs
submitted from RESPOND terminals. The peripheral processor
percentages include the dedicated peripheral processor which
services the multiplexer.

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The cost of providing a remote console capability
within a multiprogramming system is difficult to
detennine due to the following considerations:

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NUMBER OF ACTIVE USERS
Figure 5-Central processor usage

active users. Figure 5 indicates central processor time
used by RESPOND. This measurement does not
which averaged 0.62 seconds per file. With no users
logged in, the central processor portion of RESPOXD
requi,res 1.94 milliseconds to complete a duty cycle.
Since duty cycles are initiated once every ,100 milliseconds, an overhead of 0.39 percent of available central
processor t.Lrne is obt.ained. Figure 6 reflects RESPOND's requirements for additional central memory
workspace as the number of active users increases.
Since the amount of workspace required by a user
depends upon the nature of his activity, no simple
fonnula can be given which will anticipate central
memory reqJ.lirements.
The file structure for RESPOND files stored on the
individual lines of text. The SCOPE file system has
as the basic allocatable item a half-track, which is
48 64-word sectors. ** RESPOND breaks down each
half-track assigned to it into 6 disk blocks of 8 sectors
each and keeps a record of both the half-track number
and block starting sector.
Each disk block, then, is 5,120 characters in length,

** Originally 50 sectors, the SCOPE half-track was reduced to
48 sectors in order to achieve a multiple of 8 sectors per halftrack as required by RESPOND.

Operational Analysis of Remote Console System

48

263

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NUMBER OF ACTIVE USERS

DISK BLOCKS PER FILE

Figure 6-Petl.k central memory usage
Fi~ure

and the file structure is such that any coded file requires a minimum of three disk blocks while binary
files require a minimum of two disk blocks. Coded
files are made up of one file header block and an arbitrary number of sequence number and text blocks.
Since binary files have no sequence numbers associated
with them, they do not require sequence number
blocks. It has been observed that many RESPOND
failures occur in the mapping operation between the
SCOPE and RESPOND file structures described
above.
Figures 7 and 8 show how user files are allocated
on the disk by RESPOND. The portion of the file
which contains useful data is plotted against the number
of blocks required to contain that file. As the size of
the file increases, the allocation efficiency of this file
structure appears to stabilize near 85 percent. As Figure
8 indicates, however, the number of files which enjoy
this allocation is a negligible percentage of the total
number of user files. Since two-block files can only be
binary files, the distributions shown in Figures 7 and 8
are slightly distorted. The data used in these figures
represent 1,194 files distributed over 142 users. Ninetyone percent of the files were coded and nine percent
were binary.
Aside from costs in terms of system resources, a
remote console system can add other costs to the operation of a computation center. When such a system is
. first installed, it is very likely that several local modifications will be needed in order to tailor the operation

7-Disk file storage efficiency

100

80

,,,
,,,
,,,
,,,
,

60

40

20

a

a

4

8

12

DISK BLOCKS PER FILE
Figure 8-File size distribution

16

264

Spring Joint Computer Conference, 1969

of the system to the particular user's environment.
As usage of the system increases, demands for additional features, extended capability, and higher
reliability will be voiced by users. Finally, like any
other large, complex system, it is certain to have at
least one remaining "bug" in it at all times. 7 For these
reasons, the talent of a systenI programmer thoroughly
familiar with the operation of the system will be
required throughout the life of the installation.
A remote console system also demands the attention
of the computer operators, a fact that is often overlooked in cost forecasts. It is estimated that at The
University of Texas Computation Center, the computer
directly related to RESPOND. These tasks include
replying to user messages on the master console,
handiing magnetic tape for some RESPOND jobs,
in the event of system failures. Since the remote
console users are on-line, the computer operators must
be prepared to service these demands in a punctual
manner. They sometimes view this responsibility as
a hindrance to thejr normal batch processing duties.
se:\I~IARY

A remote console system whieh has been in operation
for more than 20 months has been analyzed. rrhis
analysis covered system performance, system reliability,
user reaction, and cost. The study pointed out the
following:
• System reliability is of paramount importance.
• A remote batch entry system such as RESPO:XD
is very useful for many types of applications.
Expanding its capabilities to include interactive

processing and context-oriented text editing would
make the system appeal to a larger class of users.,
• It is extremely important that the remote cons~ole
system and the operating system be compatible
in as many areas (e.g., file structure) as possible.
RESPO~D's utilization of standard system software is considered a strong point in its favor.
• The cost of providing such a service is more than
the expenditure of system resources such as
processors, core memory, and mass storage. It
also includes the talents of system programmers,
computer operators, and a person to provide
iiaison between the remote users and the computation center.
REFERENCES
E A PEARSO~
RESPOND, a user's manual
Computation Center The University of Texas Austin 1967
2 TTY RESPOND reference manual
Control Data Corporation Publication nr 60189300 1967
3 D F STEVEXS
System evaluation on the Control Data 6600
Proc International Federation of Information Processing
Societies CO~GRESS 68 C34
4 A L SCHERR
Time-sharing measurement
Datamation Vol 12 No 4 22-26 April H)66
5 G E BRYA~
JOSS: 20,000 hours at the console-a statistical summary
Proc F J C C 1967
6 R V BUTLER
The Langley Research Center remote computing terminal
system: implementation and first year's operation
Proc 21st ~ational ACM Conference 1966
7 E \V PULLE~ D F SHUTTEE
.lfUSE: A tool jor testing and debugging a multi-terminal
programming system
Proc S J C C 1968

A model for core space allocation in a
time-sharing system
by MAURICE V. WILKES
The University Mathematical Lahoratory
Cambridge, England

INTRODUCTION
In a time-sharing system that is intended to serve a
number of console users simultaneously, there are two
related, but distinct, functions to be performed. One
is time slicing, which is the allocation of bursts of processor time to the various active programs according
to a suitable algorithm. The other is core space allocation which arises because, in a modem multi-programmed system, there will be space in core for more
than one active program at the same time. If, as will
normally be the case, there are more active programs
than can be accommodated in core, some of them must
be held on a drum and brought into core periodically;
this is swapping. Confusion has sometimes arisen between time slicing and swapping, since, in the early
time-sharing systems, there was only one active object
program resident in core at any time, all the others being
on the drum. In these circumstances, swapping and time
slicing go together; when a program is in core, it is receiving processor time, and as soon as it ceases to receive
processor time it is removed from core. In a multi-programmed system, however, space allocation and time
slicing can proceed independently. It is the responsibility of the space allocation algorithm to ensure that,
as far as possible, there is always at least one program
in core that is ready to run. The time-slicing algorithm
is responsible for dividing up the available processor
time between the various programs that are in core.
Models can play a similar part in the discussion of
computer systems as they can play in scientific theory.
Practical situations tend to be highly complex, and a
model serves the purpose of isolating and focusing
attention on those features that are relevant to the purpose in hand. Since a model is simple, it can be defined
precisely, and hence made to serve as a suitable basis
for analysis, mathematical or otherwise. A model has

essential features and non-essential features, and one
object of analysis is to determine which are which. A
model of a software system is not a blueprint for an
implementation; a given model may, possibly, be implemented in a number of quite different ways. The
implementer may depart from the model, for example,
by adding features which spoil its simplicity but increase
the running efficiency. In such cases, the analysed performance of the model gives a lower limit to the performance of the system. On the other hand, the implementer may be faced with practical limitations that the
model maker could ignore, and these may lead him to a
variety of compromises and sacrifices to expediency.

The model
This paper is concerned with core-space allocation
for object programs only, and it is assumed that the
supervisor is provided with a separate allocation system
of its own. Practical reasons why this is desirable derive
from the fact that a good deal of information is available about the likely behavior of supervisor processes.
Some routines in the supervisor are needed so frequently
that they must be kept permanently resident in core; in
the case of others; it may be known that, when they
have finished running, they will not be needed again for
an appreciable time, and these processes, therefore, are
best called down on each occasion when they are required. A system of requesting and keeping priorities
space available for supervisor processes has been described by Hartley, Landy, and Needham;l this system
lends itself to use in the case where, as in the model to be
described, the amount of core space actually available
to the supervisor varies dynamically from minute to
minute. One of the responsibilities of the supervisor is
handling input and output, and provision of the necessary space for buffers is dealt with by the space alloca265

266

Spring Joint Computer Conference, 1969

tion procedure associated with the supervisor. There
will be several further references to supervisor space
scheduling, but the subject will not be discussed in
detail.
In describing the model, it will be assumed that there
is only one processor in the system. There is, however,
no reason why there should not be more than one. The
issue hardly affects the problem of space allocation,
although it does, of course, affect the design of the timeslicing algorithm.
There is some difficulty in arriving at a nomenclature
that is not ambiguous or misleading to describe the flow
of work through a time-sharing system that is handling
both a foreground and a background load. In the case
of a batch-processing system, one can think of the work
being presented a.s consist.ing of a series of self-cont.ained
jobs, each of which may pass through a number of stages
variously known as job steps, phases, or tasks. If the
same point of view is adopted in relation to a timesharing system, then an on-line session at a console consists of a single job; a user, however, is more likely to
think of himself as creating a number of separate jobs,
some of which may run independently, and some run
interactjvely. A distinction must also be made between
programs that are run on behalf of a user, and programs
that are run on behalf of the supervisor; the former are
sometimes called object programs. This paper is concerned with the work in the system at a given time and
not with the life history of individual jobs according to
any particular definition of that term. The termsjob and
object program will, therefore,' be used more or less interchangeably to refer to tasks or sub-tasks requiring to be
done on behalf of a user and existing in the system at a
given moment.
Swapping and resident regimes

Object programs that live on the drum and come in
and out of core for periods of activation may be said to
operate in the swapping regime; as pointed out above,
such programs do not necessarily have the use of the
processor for the whole time that they are in core.
Programs that remain in core, and receive bursts of
processor time at intervals, may be said to operate in
the resident regime. In the present model, all programs,
when first loaded, are operated in the resident regime,
and those that survive for more than a short length of
time pass into the swapping regime.
The explanation can be followed by reference to Figure 1. The lowest area of core is known as the swapping
area, and is the area into which programs currently
operating in the swapping regime are transferred in
order to be eligible to receive processor time. In the
simplest mode of operation, there is only one program

n

CORE MEMORY

RESIDENT
SUPERVISOR

NON-RESIDENT
SUPERVISOR.
BUFFERS.
SUBSYSTEMS

VARIABLE BOUNDARY

-------- }-----{

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PIPE LINE

SWAPPING AREA

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ACCORDING TO PRIORITY
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Figure 1

at any time actually loaded into the swapping area, but
more elaborate modes are possible. Above the swapping
area comes the pipeline. This is large enough to contain
several of the maximum-sized programs that are acceptable to the system. Programs enter the pipeline at
the top and work their way down in the manner that
will be described. * If they survive long enough, they
eventually enter the swapping area. The top boundary
of the pipeline is dynamically variable, and is indicated
by a dotted line. Above this comes an area for holding
sections of the supervisor that are kept on a drum or
disc and brought into core only when they are needed.
The same area is used to provide buffer space for the
supervisor, space for lists maintained by the supervisor,
and space for sub-systems that are subjected to supervisor-type scheduling, rather than to object-program
type scheduling. Finally, at the top of the core, there is
a region reserved for sections of the supervisor that are
permanently held in core.
An object program starts its life by being queued on
the disc, along with other object programs that have

* References to programs being moved down the pipeline do not
necessarily imply that in an implementation programs should be
physically moved in core. A system in which a similar effect
were obt2.ined by software devices or by paging hardware would
be a valid implementation of the model.

A :Model for Core Space Allocation

been created either by a user or by the system. When
space becomes available at the top of the pipeline, one
while ensuring that long ones are not indefinitely delayed, and, at the same time, to give effect to the differing priorities that may be attached to object programs, either as a result of administrative decision or
by system requirements. When an object program
enters the pipeline, it is given an upper limit for space
(including space for data) that it may occupy, but no
actual allocation of space is made at this moment
beyond that immediately needed. Thus, a program of
length 4K words that it is known will ultimately require
another 8K for data is given an upper limit of 12K, but
receives no more than 4K of physical space when first
When in the pipeline, object programs receive slices
of processor time as determined by the time-slicing
algorithm. Object programs that do not survive long
enough to enter the swapping regime can leave the
pipeline in various ways. They can become dead or
dormant, the difference between these two states being
that a dead program is needed no more and can be
abandoned, whereas a dormant program must be transferred to the disc for possible reactivation, or post
mortem examination, if required. An object program
can also leave the pipeline as a result of going into a
console wait; a discussion of what should happen in
these circumstances will be reserved until later.
When space in the pipeline becomes free as a result of
an object program leaving it, programs higher up in the
pipeline are shifted down to fill the vacant space. This
can result in space appearing at the top of the pipeline,
load a new object program at once, or wait until additional space has become available. On the other hand,
one of the other object programs in the pipeline, above
the one that has disappeared, may be waiting for additional space, in which case the space now available (or
as much as is needed) is given to this object program,
any surplus being passed upwards for allocation to
another waiting object program or to be made available
bubble of space passing upwards and either being absorbed or partly absorbed on the way, or reaching the
top. If an object program survives long enough to reach
the bottom of the pipeline, it is eligible to pass into the
swapping area. The rate at which object programs are
withdrawn from the pipeline controls ultimately how
routine and hence the rate at which new object programs are loaded.

267

The efficient operation of the system requires that
the pipeline shall contain a sufficient number of object
programs, or jobs as they will now usually be called;
there is no point, however, in increasing the number of
jobs beyond the point at which there is a high probability that, at any instant, there will be at least one job in
core that is ready to run. The criterion here is the number of jobs in the pipeline, not the total core space that
they occupy. The amount of space needed in the pipeline will, therefore, vary from second to second, according to the average size of the jobs. When there is
space to spare, it is better to give it (temporarily) to
the supervisor rather than to load redundant jobs. The
supervisor will be able to make good use of the space
for purposes already mentioned, such as holding nonresident routines. and temporary buffers. In the model,
is designed to keep the number of jobs in the pipeline
constant.
The pipeline has the effect-and this indeed is its
purpose-of filtering out jobs that run for short periods
only, since these will leave the pipeline before they
reach the bottom. Since they never reach the swapping
area, the overheads of swapping are avoided altogether
in the case of such jobs.
Jobs that are interacting closely with a console will
typically run for short periods, and go into frequent
console waits. Such jobs are, therefore, most suitably
dealt with by the pipeline technique, rather than by the
swapping technique, and, of the various strategies
available, the following would appear to be the best
calculated to give a high standard service to such jobs
without interfering with the smooth running of the
system as a whole.
A highly interactive job enters the pipeline in the
manner that has been described with no special privileges; it will not, in fact, be known to the system at this
time that the job is highly interactive. The job may be
expected to reach a console wait while it is still in the
pipeline, although there is no reason why it should not
run long enough to enter the swapping area. The
essence of the strategy proposed is that, when reactivated by a response from the console, the job should
re-enter the pipeline at the top. A job reaching a console
wait is, therefore, immediately removed from the
pipeline and, on reactivation, is returned to the queue
of jobs waiting to enter. In order, however, that it
should not be subject to the delays that normally occur
at this point, it is handled according to special rules;
what these are depend on the importance attached to
giving the best possible response to jobs while they are
interacting with a console. An advantage of the model
is that it enables one to see what is the cost of the
various steps that can be taken to this end, both in

268

Spring Joint Computer Conference, 1969

terms of the employment of system resources and the
effect on the throughput of other types of job. One step
that will naturally be taken is to provide that a console
wait job shall be placed on a separate queue and given
priority over jobs waiting on the regular queue to enter
the pipeline. Further improvement can be obtained by
implementing this special queue on a drum instead of
on the disc; in the model, the drum used for this purpose
would be shown as separate from the drum used for
swapping, although, of course, in an implementation,
the same physical drum might be used for the two
purposes. A further step that could be taken to improve
the response after a console wait would be to design the
pipeline loading algorithm so as to keep in hand a certain amount of space at the top of the pipeline for the
accommodation of console-wait jobs when they are reactivated. The more space kept in hand, the better will
be the service given to highly interactive jobs, but the
greater wHl be the cost to the system. The balance to be
struck is a matter for management decision in any particular case.
Since an interactive job returns to the queue of jobs
waiting to enter the pipeline when it comes to a console
wait, it is treated by the system as though it were a new
job, although one having special priority. In what
follows, therefore, the term 'job' will for brevity be used
to denote either an entirely new job or an interactive
job that has been resuscitated after a console wait.
Jobs may be held up waiting for other forms of peripheral action, such as disc or magnetic-tape transfers. The
former are of brief duration, and the jobs concerned
continue their progress through the system . .:\Iagnetic
tape waits, however, are of relatively long and uncertain duration; they have a good deal in common with
console waits, and it can be argued that they should be
dealt with in a similar way.
Time-slicing algorithm

The core space allocation system ensures that, at any
given time, there are sufficient object programs in core
to make effective multiprogramming possible, and that
any programs resident on the drum come into core often
enough to be able to receive processor time at appropriate intervals. The time-slicing algorithm determines
how the processor time is allocated to the various
programs that happen to be in core and are free to run,
whether they are in the pipeline or in the swapping area.
I t may be assumed, although this is not strictly necessary, that time is shared between the pipeline and the
swapping area in a fixed proportion. Time is given to
programs in the pipeline in small slices; the smaller the
slice the better, provided that program changing over-

heads do not account for a significant fraction of the
total time. X ote that a program temporarily resident in
the swapping area will not be active during the whole
time that it is in core. Like programs in the pipeline, it
will receive time in small slices; it will be returned to the
drum when the total amount of time that it has received
since being loaded reaches a certain figure, chosen to be
high enough to make the overheads of swapping worthwhile. This figure would be greater for long programs
than for short ones since the swapping time depends on
a program's length.
Swapping re1Jime

If the allocation of processor time to jobs in the
swapping regime is a fixed proportion of the total time
available, then the rate at which jobs terminate depends
only on their average expectation of life at the moment
they enter the swapping region; in fact, the rate at
which jobs terminate is I/il, where il is their expectation of life, calculated on the assumption that there
would only be one job in the swapping regime. The
rate of termination of jobs is, in particular, independent
of the number of jobs in the swapping regime. Thus,
the swapping regime may be likened to a hopper from
which objects are extracted at a given mean rate.
Since the rate of entry and the rate of abstraction are
subject to stochastic variations, the number of jobs in
the swapping regime will fluctuate about a mean, even
if the mean rate of abstraction is equal to the mean
rate of ent~y. The problem of investigating these variations may be tackled by the methods of queuing theory.
The simplest method of core space allocation for the
swapping regime is to bring one program into core at a
time; the time-slicing algorithm has then only one program in the swapping area to be concerned with.
Almost as simple, if the hardware permits, is the wrap
around method in which the section of core constituting
the swapping area is addressed modulo n, where n
(in practice a power of ) is the number of words
it contains. Each new program brought down starts
where the previous one left off and if the programs are
short several can be in core at once. A maximum-sized
program will, of course, occupy the whole swapping
area. The time-slicing algorithm can be designed to
take- advantage of the fact that there may be more than
one program in the swapping area at a given time. The
result is an improvement in the average efficiency of the
multiprogramming.
Once a program has entered the swapping regime, its
troubles as regards acquiring core space are over, and
it can occupy as much core (up to the maximum permitted to any program) as it requires.

A Model for Core Space Allocation

The pipeline
If the number of jobs in the pipeline is held constant,
then the methods of standard queuing theory are not
applicable. An approximate treatment is, however,
offered in the Appendix. For a given rate of abstraction
of jobs from the pipeline this enables the distribution of
age of those jobs to be computed, and also the rate at
which jobs must be loaded to keep the pipeline full.
In order to carry through the calculations, it is necessary to assume a form for the statistical distribution of
job life. In one particular case (the Poisson case) the
treatment becomes exact. This is the case in which the
(lxpectation of life of a job is independe.nt of its age.
The practical effect of the pipeline is to filter out short
jobs before they can enter the swapping regime. It is of
interest to know the expectation of life of jobs emerging
from the 'pipeline since this determines their behavior
in the swapping regime, namely, how long they are
likely to remain in it, and how many times they are
likely to be swapped. In the Poisson case, the probability of a job reaching the end of its life in an interval
5t is independent of its age, and its expectation of further life is also independent of its age. In this case, the
expectation of life of jobs entering the swapping area
will be equal to their expectation of life when they enter
the pipeline. If, however, the probability of a job
rea.ching the end of its life in 5t increases with a.ge, so
that a job that has survived an initial period is unlikely
to continue for a long time, then the expectation of life of
jobs entering the swapping area will be less than
their initial expectation of life. If this is ~o to any
marked degree, the effectiveness of swapping is open to
question, since very few jobs will survive more than onf'
swap, and an increase in the length of the pipeline
sufficient to allow all johs to finish while stil1 within it
would he' more' suitable'.

I mpleJlu>,ntatioli

It has alrE'ady been mentiollcd tha,t systrm~ in which
programs are not physieally shifted in tore, but in whi('h
similar effects are achieved by other means, are to be
regarded as valid implementa.tions of the model herp
described; the model is, ill fact, much more general than
the description given above may at first sight suggest.
Essential features, however, art' (1) tha,t WhPll a job is
first loaded it is givpn a period of continuom; residpncp
in (~ore before a regime in whieh regular s,vapping to and
from a drum is initiated, and (2) that spa.ce is given to fl,
program piecemeal as it needs it and not all at oncE'.
These objectives can be achieved by a dircet imple'mentation of the shifting described in thp model or by
making nsf' of a hard·warp paging sy-stpm. In relation to

269

the latter case, the discussion given here is really a
discussion of the way in which the paging algorithm
should be designed. The objectives can also be achieved
in core that enough contiguous space to meet their ultimate needs can be earmarked for their use. Until such
time as they need the space, it can be made available to
the supervisor for accommodating non-resident rou.j.;...,.,..",

nn;J f",~ h".1!{',..~;...,.~ 1
tJU.Lvo a.uu lV.L UU1!\:;.L.L.L.L~.

Overall control of the system
One of the objects of establishing a model for core
space allocation is to enable the control problem for the
system as a whole to be formulated. The problem of controlling a time-sharing system has much in common
with control problems met in the process industries, and
this fact will be brought out by describing a closely
analogous problem connected with the control of an oregrading plant.
In an industrial plant, there are commonly a number
of purely local control loops presided over by controllers
that operate independently of the main control system.
One sueh control loop-eonnected with the balance
between foreground and background jobs-can be
identified in the time-sharing system under discussion.
.Tobs that are ready to enter the pipeline wait on one of
a number of queues on the disc. In the simplest case
there will be separate queues for foreground jobs and for
background jobs, the latter including background jobs
initiated from consoles. There is, in addition, a queue
for jobs waiting to be reloaded after a console wait.
.J obs are loaded into the pipeline according to rules
designed to give priority to jobs waiting to be reloaded, and otherwise to favor the foreground to the
extent determined by operational requirements. These
rules can be designed in such a way that minor shortt.erm variations in the foreground load can be accommodated by varying the ra.te at which background jobs
are fed, thus avoiding the need for significant variation
in the rate of flow of jobs into the pipeline. This is a
piece of local control of a straightforward kind. Longer
term changes-up or down-in the foreground load reINCOMING ORE

•

.

••••• •

SCREENING PlANT

·•

•

Figure 2

270

Spring Joint Computer Conference, 1969

main to be dealt with by the overall control mechanism,
which will forcibly log out a proportion of the users
(after giving them a warning) when the load is heavy
The closely analogous problem that will be considered
is that of controlling the ore-grading plant illustrated in
Figure 2. Lumps of ore of varying sizes enter a screening
plant and the smaller ones fall out. The larger lumps
continue and pass into a hopper from which they are
extracted at a constant rate by a conveyor. The screening plant corresponds to the pipeline and the hopper to
t.he swa.pping area. Ore is fed to the plant from an external source, and the rate of flow can be controlled,
although response to control signals is not rapid. This
corresponds to adjusting the number of console users of
a time-sharing system in the manner just described.
The input parameter:;; on which control of the oregrading plant must be based are ,(1) a measurement of
the amount of the material in the hopper, and (2) a
measurement of the amount of material that has piled
up at the entry to the screening plant. There must be
two output signals from the control system; of these,
one is used to control the rate of flow from the screening
plants to the hopper, and the other is sent to the ext.ernal source of supply and used to control the rate of
feed of ore into the plant. The design objectives of the
control system are, in the short-term, to make use of the
storage capacity available in the hopper to prevent any
appreciable piling up of material at the entry to the
screening plant and, in the long-term, to adjust the rate
of arrival of material so that the system operates
smoothly and efficiently with as little material as
possible in the hopper.
Time delays are a common cause of instability in the
operation of a plant if the control system is not carefully designed. In the time-sharing system, instability
could occur on account of the fact that changes in loadthat is, ehanges in the number of userR logged in-cannot he made instantaneously. If, for example, the control mechanism, faced with an increaRe of activity on
the part of the users currently logged in, were to overestimate the number that must be warned off, the
sYRtem would, at some later time, be found to be underloaded. Over-correction of this situation would, in turn,
proceed to oscillate between one extreme and the other.
On the other hand, the use of a eontrol mechanism that
unduly cautious in allowing the number of on-line
users to grow when the system was underloaded would
obviously result in the system running below capacity
most of the time as far as service to on-line users was

concerned. These are typical problems encountered in
control engineering, and it is suggested that the designers of time-sharing systems could learn something from
their colleagues working in that discipline.

REFERE~CE

D F HARTLEY B LANDY R M )l"EEDHAM
The structure of a multiprogramming supervisor
The Computer Journal 11 No 3 p 247 )l"ovember H)68

APPENDIX
A nalysis of pipeline

The following approximate analysis applies to the
case in which the number of jobs emerging from the
pipeline is small compared "'.vith the number of jobs
entering.
Let P(f) be the probability that a job entering the
pipeline has a life* greater than or equal to f and let
p(f) = - ap(f)/af

p(f) of

IS

the probability that the job finishes in the interval Of, i.e.,
between f and f + Of. The expectation of life of a job
entering the pipeline is then

1=

lr¥J t p(t) dt
o

By integrating by parts it may be shown that
given by

t

=

lr¥J P(t) dt

t

is also

(1)

o

Consider a pipeline containing n jobs from which no
withdrawals are made, but in which each job is replaced
by a new one as soon as it finishes. The probability of a
job selected at random at a randomly chosen instant
having an age greater than or equal to f is then
A(f) = (Ill)

f~ 'P(t) dt
t

The probability that the oldest of the n jobs existing in

* For

this purpose, a job reaches the end of its life ",-hen it becomes dead or dormant, or reaches a console wait. In this Appendix, time is true elapsed time and the distributions take account
of the fa('t t.hat p]'()('essor time is heing shared among a number
of jobs.

A Model for Core Space Allocation

the pipeline at a randomly chosen instant has an age in
is Qn(C) 0( where

0(

Q,,(C) = (lIt)

~

ac

271

pipeline during a period To and the number, W, withdrawn during the same period:

)[t - WL = nTo

[1 - A (C)]r'

or
In practice, a job selected as being the oldest of the n
jobs in the pipeline at a random instant is withdrawn
and replaced by a new one. If the rate of withdrawal is
small compared with the natural death rate of jobs in
the pipeline, it may be assumed as an approximation
that Qn(C) still gives the age distribution.
Let the extra life that a job withdrawn at age f. would
have had if it had remained in the pipeline be J.I.. Then
the expectation of total life C + J.I. is given by
E(C

+ J.I.)

=

foo t

[pet) IP(C)] dt

(

= - [l/P(C)]

foo

t [ap(t) / at] dt

t

+

= f

f A(t) /P(C)

on integrating by part and using (l)' Thus E(J.I.) =
A(t)/P(t)
If this value for E(JL) is averaged over the distribution
Qn(t) , we have the expectation, L, of the amount by
which the life of a job in the pipeline is shortened by
being withdrawn:

!

1

+ WL)/t

If pet) = exp( -at) (the Poisson case) then it is well
known that the expectation of life is independent of age.
In the above notation, as may easily be verified,

The theory then becomes exact, and we have
N = nTol!

+W

The number of jobs that finish in the pipeline is
independent of the withdrawal rate, and if more jobs
are taken out then a similar number of extra jobs must
be prtt in. The expected life of a job on emergence is the
same as its expected life on entry.
I t may be observed that no job can remain in the
pipeline for more than n sampling intervals. The
approximation given by Qn(t) to the age distribution of
jobs in the pipeline, subject to withdrawal, may be
improved by redefining A(t) as follows:
A(t) = (lit)

f

nT

pet) dt

t

00

L = f

1\ = (nTo

[Qn(t) A(C)/P(t)] dC

o

It is now possible to arrive at the following relationship between the number, N, of jobs entering the

where T is the average interval between withdrawals.
The results of a series of simulations suggest that, with
this refinement, the theory is sufficiently precise for
most practical purposes.

Picture-driven animation *
by RONALD M. BAECKER**
National Institutes of Health ***
Bethesda, Maryland

INTRODUCTION
"Animation is the graphic art which occurs in time. Whereas a static image (such
as a Picasso or a complex graph) may convey complex information through a single
picture, animation conveys equivalently complex information through a sequence of
images seen in time. It is characteristic of this medium, as opposed to static imagery,
that the actual graphical information at any given instant is relatively slight. The
source of information for the viewer of animation is implicit in picture change: change in
relative position, shape, and dynamics. Therefore, a computer is ideally suited to
making animation' 'possible" through the fluid refinement of these changes.' ''l1

The animation industry is ripe for a revolution.
Historical accidents of available technology and knowledge of visual physiology have led to the evolution of
the animated fihn as "one that is created frame-byframe.' '1 The prodigious quantities of labor required
for the construction of twenty-four individual frames
per second of fihn have led to a concentration of animation activity in the assembly-line environments of a
few large companies, an artificial yet rarely sunuountable separation of the artist from the medium, and
extravagant costs. 2 In conjunction ·with other tr~nds
in American society, the result is usually what the
English critic Stephenson describes as "the respectable
sadism and stereotype of commerce."l Yet he offers
this hopeful prediction in concluding his 1967 study,
A nimation in the Cinema: There seems every reason
to look forward to changes which would make it possible

for the creative artist to put on the screen a stream of
images with the same facility as he can now produce
a single. still picture."l This paper explains how a
creative, artist, aided by a computer, can define a
stream 6f images with the same facility as he can now
produce a very few still pictures.
Although the computer's entrance into animation
has been a recent one (1964),3-4 the growth of interest
and activity has been phenomenal.6-8 Experience to date
strongly suggests that the following Rtatements are true:
1. The animated display is a natural medium for

the recording and analysis of computer output
from sirhul~tions and data reduction, and for
the modeling, presentation, and elucidation of
phenomena of physics,· biology, and engineering. 9- 15 Depiction through animation is particularly appropriate where simultaneous actions
in some system must be represented. If the
animation is the pictorial simulation of a com..
plex, mathematically-expressed physical theory,
then the film can only be made with the aid of a
computer.
2. The computer is an artistic and animation med'ium, a powerful aid in the creation of beautiful
visual phe~o'mena, and not merely a tool for the
drafting of regular or repetitive pictures. 16-19
3. The formal modeling of pictures by complexes

* Work reported herein was supported in part by Project MAC,
Projects Agency, Department of Defense, under Office of Xaval
Research Contract N"ONR-4102(Ol), and by M.LT. Lincoln
Laboratory with support from the u.S. Advanced Research
Projects Agency.
** This paper is based on a thesis submitted in partial fulfillment
for the degree of Doctor of Philosophy at the Massachusetts
Institute of Technology, Department. of Electrical EJ:lgineering.
*** Division of Computer Research and Technology.
27:3

274

Spring Joint Computer Conference, 1969

of algorithms and data facilitates the continued
modification of a singlearumation sequence and
the production of a series of related sequences.
This paper discusses ways in which man, aided by a
computer in an interactive graphical environment, can
synthesize animated visual displays. It is widely recognized that such an environment facilitates manmachine communication about still pictures. 2o- 22 The
paper seeks to:
1. describe the role of direct graphical interaction

and sketching in computer animation, resulting
in the process we sh8JI call interactive computermediated an?,mation; and,
2. develop a new approach to the specification of
picture dynamics,. one which exploits the capacity for direct graphical interaction. The result
we shall call picture-driven animation.
A nimation in an interactive comp1..l.·ter graphics
environment

The role of direct graphi'cal interaction in the
synthesis of animated visual displays
Three aspects of the role of direct graphical interaction in computer graphics are particularly relevant
to computer anilllation:
1. The availability of immediate visual feedback

of results, final or intermediate;

core: control of the changing spatial and temporal
relationships of graphic information.
Factoring the construction of an animation sequence
facilitates the effective use of feedback from early
stages to guide work in later stages. Working on individual small subsequences helps overcome the serious
practical problems of computer time and space that
could disallow rapid enough calculation and playback.
We know from the computer graphics of still pictures
that the computer sjmulates not only a passive recording agent in its ability to retain images, but an active
medium which transfOl~ms the very nature of the sketching process. This remark applies trivially to computer
animation; one may construct a sequence of drawings
to comprise the individual frames of the film, the static
images existing at single instants of time. Picture
change that extends over entire intervals of time is then
synthesized as a succession of individual (temporally)
local changes that alter one frame into another.
This paper goes further, for it explains how the
computer can be a medium which transforms the very
nature of the process of defining picture change, of
defining movement and rhytlun. Dynamic behavior
is abstracted by descriptions of extended picture change.
These descriptions may themselves be represented,
synthesized, and marupulated through pictures, both
static and dynamic. Thus dynamic control can be exercised globally over the entire sequence. What results
is one new conception of what it means to draw an
animated film.

2. The ability to factor picture construction into

stages, and to view the results after each stage;
and,
3. The ability to sketch pictures directly into the
computer.
The power of immediate visual feedback in animation
is striking. The computer calculates, from its representation of a dynamic sequence, the individual frames
of the corresponding "movie." Like a video tape recorder, it plays it back for direct evaluation. A small
change may be made,. the sequence recalculated, and
the result viewed again. The cycle of designation of
conunands and sketching by the animator, followed by
calculation and playback by the computer, is repeated
until a suitable result is achieved. The time to go once
around the feedback loop is reduced to a few seconds
or minutes. In most traditional and computer animation environments, the time is a few hours or days.
The difference is significant, for now the animator can
see and not merely imagine the res'ult of varying the movement and the rhythm of a dynamic display. Thus he will

be led to perfect that aspect of animation that is its

The components required to realize an interactive computer-mediated animation system
Interactive computer-mediated animation is the process
of constructing animated visual displays using a system containing, in one form or another, at least the
following eight components:
Hardware:

1. A general-purpose digital computer.
2. A hierarchy of auxiliary storage. This is listed

separately to emphasize the magnitude of storage
required for the data structures from which an
animation sequence is derived and for the visual
images of which it is composed.
:). An input device such as a light pen, tablet plus
stylus,23-24 or wand,25 which allows direct drawing to the computer in at least two spatial
dimensions. The operating environment must,
upon user demand, provide at least brief intervals during which the sketch may be made in
real time. The animator must then be able to

Picture-Driven Animation

275

draw a picture without any interruption.
Furthermore, the computer must record the
"essential temporal information" from the act of
sketching. Sampling the state of the stylus 24
times per second often suffices for our purposes.
4. An output device, such as a standard computer
display scope or a suitably modified TV monitor,
which allows the direct viewing of animated
displays at a rate such as 24 fra...tnes per second.
This is essential to enable the interactive editing
of animation subsequences. The final transmission of a "movie" to the medium of photographic
film or video tape can but need not use the same
mechanisms.
Software:

5. A "language" for the construction and manipulation of static pictures.
6. A "language" for the representation and specification of picture change and the dynamics of
picture change. We shall introduce in this paper
methods of specifying: dynamics not possible
with traditional animation media and not yet
attempted in the brief history of computer
animation.
7. A set of programs that transforms the specifica;tions of picture structure and picture dynamiCs
into a sequence of visual images.
8. A set of programs that stores into and retrieves
from auxiliary memory this sequence of visual
images, and facilitates both its real time playback for immediate viewing and its transmission
to and from permanent recording media.

Figure I-An interactive computer-mediated animation console.
The author is sketching with the stylus on the tablet. There
is a CRT for viewing dynamic displays, a storage scope
above it, a typewriter, knobs, toggle switches, and
a telephone so that an animator may summon help

Figure 1 portrays a suitable environment for interactive computer-mediated animation. Figure 2 is a
block diagram of such a system.

A scenario illustrating the use of an interactive
computer-mediated animation system
To illustrate the process of animation in an interactive computer graphics environment, we present a
scenario. The example, chosen for its simplicity, is an
extended version of one actually executed with the
GENEralized-cel animation SYStem. GENESYS is a
picture-driven animation system implemented on the
M.I.T. Lincoln Laboratory TX-2 computer. All capabilities purported to it are operational or could be made
so by minor additions. The written form of the interactive dialogue has been adjusted to increase its clarity.
We want to see a dynamic sequence of a dog dashing to
his dinner and then dining: The dog runs towards a

Figure 2-Block diagram of a minimal system for interactive
computer-mediated animation. The parenthesized numbers
refer to the system components defined in the paper.

bowl. Wagging his tail, he lowers his head and laps up
the milk. Several slurps of the milk are to be shown
before we cut to the next scene.
How we do it:

ANIlVIATOR(A): CALL GENESYS;
GENESYS(G): HELLO. GENESYS A WAITS YOUR
CREATION;
GENESYS either types or displays this response.

276

Spring Joint Computer Conference, 1969

A: FORMMOVIE DINNERTIME;
The animator either types the command name
'FORMMOVIE', hits a corresponding light-button
with the stylus, or writes an abbreviation of the
conunand name to a character-recognizer. 26 He
then types a movie name, 'DINNERTIME'.
G:FRESH;
No such movie exists in the animator's directory.
Hence, work begins on a totally new one.

A: FORMBACKGROUND;
A. wants to define a subpicture that will be visible
in all frames of the sequence.

G: SKETCH IT, MAN;
A: .....
A. sketches the bowl, drawing with the stylus on
the tablet. What he draws appears inunediately on
the display scope.
G:OK;
A: FORMCEL #1 in CLASS BODY;
An initial version of the dog's body·is to be made a
unique subpicture, or eel.

He sketches it, and soon adds one version of the
legs, tail, and head, each as a unique eel in a unique
eel class. Now, a coherent dog, unmoving, appears
on the scope.
A: BIND BODY, LEGS, TAIL, HEAD, TONGUE;
This guarantees that any translational motion
applied to the dog will drive the body, legs, tail,
head, and tongue together. Thus the dog won't
disintegrate while moving.

Figure 3-A static dog glides towards a bowl. The sketches are by
Mrs. Nancy Johnson of \Valtham, Massachusetts

A: FORMCEL #2 in CLASS LEGS:

A. sketches the legs in another position, that is, he
defines the second cel in the class 'LEGS.' This
may be followed by several more positions. The
images are ones that are useful in synthesizing
running and hopping movements.
A: TYPESELECTIONS from LEGS;

He types in a sequence of choices of one of the
positions of the legs. Each succeeding choice selects
which cel is to be displayed as the dog's legs in the
next frame. Of course only one set of legs is visible
in a frame.
A: PLAYBACK;

Now, as is portrayed in Figure 4, the legs move

G:OK;

A: SKETCHPCURVE BODY;
A. now sketches the path of the desired motion,
mimicking the movement with the action of his
stylUS. Hop . . . hop . . . hophophop . . . goes his
hand. The act of mimicking a continuous movement is called a p-curve.
A: PLAYBACK;
Playback the current version of the movie. Hop . . .
hop . . . hophophop . . . glides the rigid dog across
the scope towards the bowl. Four frames from such
a motion are shown superimposed in Figure 3.
Figure 4-Now the dog hops to the bowl

Picture=Driven Animation

while the dog hops to the bowl.
Further refinements to the leg motion are made.
This includes the resketching of one eel. The tail
and head movements are similarly introduced. The
sequence then appears as is shown in Figure 5.
Three tongue cels are sketched.

A: TYPESELECTIONS from TONGUE;
For most of the sequence, the zeroth tongue is
selected, that is, no tongue is visible. A single lap,
or slurp of the tongue is synthesized from the three
tongue positions, and is introduced at the appropriate time in the movie. The leftmost image of
Figure 6 shows the extended tongue.

A: TAPRHYTHM SLURPINTERVALS;
A. can feel or intuit the rhythm of the desired slurps

better than he can rationalize it. Henee he goes
tap ... tap ... taptap ... on a push-button.
A: REPEATPATTERN FROM frame 59 THROUGH
frame 64 of SELECTIONS from TONGUE atINTERVALS of SLURPINTERVALS;
Assume that the visual slurp occurs in frames 59
through 64. The pattern of tongue selections which
yields the slurp is repeated at intervaLg deterrojned
by the tapped rhythm.

A: PLAYBACK;
Now the dog goes hop ... hop ... hophophop ...
slurp . . . slurp . . . . slurp slurp.
The movie is essentially complete; minor refinements may now be made.

A: EDIT X WAVEFORM of BODY;

M~~ .acceleration in the hopping movement would
better portray the dog's eagerness for his dinner.
Henee, A. call~ forth a display of the dog's X coordinate versus time, and resketches part of the
waveform so that there is more horizontal acceleration.

A: EDIT FRAME 44;
Assume that the dog reaches the bowl in frame 44.
Viewing the sequence in slow motion, A. notices
that the dog's position at the bowl could be improved. He alters its location in frame 44 using the
knobs under the scope.
Figure 5-Eager for dinner, he wags his tail

A: FIX X and Y of BODY AFTER/rame 44;
The path descriptions are further modified so that
the dog again holds a fixed position, once it has
reached the bowl.
A: PLAYBACK;

A: SA VE DINNERTIME;
The movie is saved, available for further refinements
at any time.
G: DINNERTIl\'IE IS SA VED. GOOD BYE.

Implications of the scenario
Figure 6--S1ul'p goes his tongue. lapping up the milk

1. Approximately 100 frames have been generated

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Spring Joint Computer Conference, 1969

from fewer than 20 eels. Only very limited
tools have been used in eel construction, specifically, programs that accept direct sketches and
that enable selective erasure of picture parts.
Nonetheless, great power results from the animator's ability to control and evaluate dynamic
combinations of a few static images.
2. Immediate playback enables interactive experimentation to achieve desired visual effects. The
actions described above, including considerable
trial-and-error, may be completed in well under
one hour, even if all cels must be constructed
anew.

3. A variety of static images, analytical graphs of
picture action, depict the time dependence of
dynamic picture parameters. An example is the
waveform representing the dog's -changing
horizontal position. Viewing such static representations aids the understanding of existing
animation sequences; resketching or editing
them changes the actual dynamic behavior
accordingly.
4. The animator may in real time mimic aspects of
dynamic behavior. His movement and rhythm
are recorded by the system for application in
the movie. This occurs when the hopping of his
stylus motion is used to drive the dog, and when
the tapping of a push-button is used to detennine
the rhythm of the slurps of the tongue.
5. Three aspects of dynamic behavior appear in
the example: path descriptions, or conceptually
continuous coordinate changes; selection descriptions, or recurring choices of cels from a cel
class; and rhythm. descriptions, or temporal
patterns marking events. The pictures (3) and
actions (4), through which direct control over
dynamics is exercised, are representations of
thE'Re thl'E'P kiud~ of gloha.l de.'{cript1·ons of dynam.ic.c.;.
6. Global operations (3)-(4), which alter dynamic
behavior over entire intervals of time, may be
supplemented where necessary by local operations, which adjust individual frames. An example is the positioning of the dog near the bowl.

The specification of picture dynamics

Three old approaches to the definition of picture
dynamics
We may distinguish three old approaches to the
synthesis of a sequence of frames:
1. The individual construction of each frame in
the sequence;

2. The interpolation of sequences of frames intermediate to pairs of critical frames' and
.....
'
,
.). The generation of frames from an algorithmic
description of the sequence.
A~imation sequences have traditionally been syntheSIzed through the individual construction of frames.
Th~ i1lusion of a continuum of time is attained through
rapId p~ayback of discrete instants of time. This approach IS the only one applicable to the construction
of pictures that defy regular or formal description, and
that require unique operations on each frame. Yet
the cost is excessive and continues to rise dramatically,
f~ster th~n the GNP.27 Salaries in large studio 'operatIOns typIcally consume half of the cost, for commercial
~~~tion ,is .a complex interaction among producers,
rureC'{;ors, aeslgners, layout artists, background artists,
key animators, assistant animators, inkers and colourists, checkers, cameramen, editors, and studio managers. 2 It is this division of labor, this dispersal of the
creative process, which separates the artist from the
medium.27 Another major weakness of conventional
frame-by-frame animation is that -there are no efficient
methods of making changes to a movie stored on photographic film or video tape. We discuss elsewhere what
role the computer might assume in frame-by-frame
animation. 28
The technique of interpolation has long been used
to cut costs and reduce the burden of picture construction which is placed on the key animator. Interpolation
occurs when the key animator asks his assistants to
fill in the pictures intermediate to a pair of critical
frames. It has been suggested that part of this process
could be mechanized.29 We do not consider further that
problem in this paper.
The generat.ion of a sequenl'.e of frames from a formal
algorithmic description is a process characterized by:

1. the need to use a computer, for it is the only

animation medimn which can follow and execute
with ease a complex algorithm;
2. generality, that is, applicability to a large class
of regularly-structured pictures;
3. representational power, or the compactness
with which interesting animated displays may
be formulated; and,
4. flexibility and adaptabiJity, or the ease with
which a variety of alterations may be made to
a movie expressed as an algorithm.
The fonn of the expression has to this date been a
written program in a picture-processing language such
as .BEFLIX,3-4 or a sequence of directives in a typewrIter-controlled command language such as CAFE.30
Herein lies another strength of the approach and also

Picture-Driven Animation

a fundamental weakness. On the one hand, many
programmers, scientists, and ~ngineers, previously not
animators but fluent in this new "language," can now
produce dynamic displays.31 On the other hand, an
is forced to learn a completely new "language," a
completely new way of thinking.

One new approach to the definition of dynamics
-picture-driven anmlation
Picture-driven animation is a new process that augments harmoniously the animator's traditional techniques, that reflects and extends the ways of thinking

to which he is accustomed. Within his intuitive "language" of pictures and sketching and mimicking, he may
synthesize both components of frames, called eels, and
generative descriptions of extended picture change,
called global descriptions of dynamics.
Global dynamic descriptions are data sequences,
whose successive elements determine critical parameters in successive frames of the movie. Algorithms
embedded in a picture-driven animation system combine cels and dynamic descriptions to produce visible
picture change. The animator defines and refines pictorial representations of dynamic descriptions. These
data sequences then "drive" the algorithms to generate
an animated display. Hence the process is called picture-driven animation.
The process is powerful because it is easy to achieve
rich variations in dynamic behavior by altering the data
sequences while holding constant a few simple controlling
algorithms. The data sequences precisely determine

the evolution of recurring picture change, within the
constraints set by a choice of controlling algorithms.
We next introduce the three kinds of global dynamic
descriptions, some useful algorithms for whi~h they
may be driving functions, and some useful methods for
their static and dynamic pictorial representation and
construction. The following classification will be helpful:
A global dynamic description is either
a movement description, which is either
a continuous movement description = a path
description, or
a discrete movement description = a selection
description; or,
a rhythm description.

Path descriptions
Consider those alterations of static pictures that
consist of modificatjons of continuously variable parameters, such as location, size, and intensity. Their

279

instantaneous values determine the picture's appearance at a given moment. Thus the static picture may be
animated by specifying the temporal behavior of such
parameters. A representation of the temporal behavior
of a continuously variable parameter is called a path
description.

The movement of a fixed-geometry picture (eel) in
GENESYS is described as the change of two coordinates with time, and is represented by a pair of path
descriptions. Their specification may be used to synthesize the drifting of a cloud, the zooming of a flying
saucer, the bouncing of a ball, or the positioning of a
pointer.
Since the behavioral descriptions of the parameters
apply to entire intervals of time, the animation is
liberated from a strictly frame-by-frame synthesis.
The computer is a medium through which one can bypass
the static or temporally local and work directly on the
dynamic or temporally global. Movement is represented

as it is perceived, as (potentially) continuous flow,
rather than as a series of intermediate states.
Path descriptions, in fact, all dynamic descriptions,
may be defined by one of six general approaches:
1. The sketching of a new pictorial representation

of the description;
2. The editing or rdfinement of an existing pictorial
representation of the description;
3. The direct algorithmic specification of the data
sequence;
4. The indirect algorithmic specification in terms
of existing data sequences;
5. An indirect algorithmic specification as a
property of a constituent picture in an existing
.
. sequence; and ,
...
ammatlOn
6. A coupling to a real physical process in the
external world, such that it transmits a data
sequence as (analog) input to the computer.
Interesting couplings may be to particle collisions, the atmospheric pressure, or, in the case
of (1) and (2), a real live animator.
We shall in this paper be concerned with techniques
implementing the first two approaches only. Sketching
is useful when one knows the general shape and quality
of a motion rather than an analytical expression for a
function that determines it. ::\iodifications of the HketcheH
are frequently invoked after one views the eurrent
animation sequence and determines how it is inadequate.
There are two related kinds of pictorial representations of all movement descriptions, static and dynamic.
Both kinds may be introduced with a single example.
Consider the motion of a figure that goes from one

280

Spring Joint Computer Conference, 1969

corner of a square room to the diagonally opposite
corner by walking along two adjacent walls. We shall
ignore the vertical movement and consider only motion
of the center of the body in the two dimensions of the
plane of the ground. He first walks in the direction of
increasing X coordinate, then in the direction of increasing Y coordinate. We further assume that he begins
from a standstill, accelerates and then decelerates to
the first corner, pauses there for a brief interval while
he turns in place, and finalIy accelerates and decelerates
to his destination.
One complete description of this planar movament
consists of the functions of the X and y. coordinates
versus time. These are depicted in Figures 7 and 8.
Such representations of changing picture parameters
are called waveforms. Time is depicted, in the waveionn, along one spati.al dimension. The wavefonn's
construction requires movement of the stylus along that
dimension; the display records and makes tangible
this movement.
Alternatively, both spatial coordinates could denote
the two spatial coordinates of the movement. A natural
correspondence is established between the X(Y) coordinate of the floor and X(Y) coordinate of the me-

dium of the representation (paper, scope face, etc.).
Figure 9 depicts such a parametric curve representation
of the movement. It illustrates with clarity the figure's
path on the floor.
Yet the dynamics of the motion are hidden because
the temporal dimension is only an implicit coordinate.
This rectified in Figure 10. A stream of symbols is used
instead of a continuous trail to depict the path. Characters are spaced along the path at short, uniform
intervals of time, such as every 24th of a second. Dynamics are apparent in the local density of symbols.
Observe in particular how they cluster where the figure
pauses.
The dynamic construction of a path description is a
user-driven animated displayz:n which the timing of the
stylus's movement is preserved by recording its position
in every frame. A tangible representation of the stylus

path is the display of a sequence of characters spaced
equally in time. We shall call a parametric curve dynamically sketched in real time a p-curve. The p-curve
corresponding to Figures 7-10 is depicted in Figure 11.
We have attempted to convey in a single static image
that the p-curve is a dynamic display. Each 2-dimensional p-curve determines two path descriptions. Thus
the hopping of the dog in 'DINNERTIME' may be
synthesized by "hopping" with the stylus along some
path on the tablet surface, that is by mimicking the
desired dynamic.

Figure 7-The X coordinate waveform of a movement

Figure 8--The Y coordinate waveform of a movement

Figure 9-A parametric curve representation of the same
movement. The rhythm of the movement is not visible

Picture-Driven Animation

281

In some cases one may need only one of the path
descriptions. To depict the fluttering of a. heart, we
may assign the X coordinate of the p-curveto a parameter determlnihg the siize of the heart, and then flutter
the pen back and forth horizontally. Any vertical
motion that results is uninterclsting and can be ignored.
A path description, in sununary, defines dynamic
activity that consists of potentially continuous and
arbitrarily fine alterations of value. The reader should
not be misled by the choice of the word "path". What
is meant is a path, or sequenee of values, through an
arbitrary "continuous space", through a mathematical
continuum. One application or interpretation of this
path is the representation of a movement through the
location-spaee of an object, such as a figure's path
through a room. This interpretation, however, is not
the only possible one. Depending upon the picture
description capability of the system in which it is used,
and the algorithm which it drives, a path description
may determine changing locations, intensities, thicknesses,
densities, or texture gradients. For example, a pulsating
heart could be animated by varying either the size or

Figure IQ-A better display of the parametric curve. Symbols are
deposited at short, uniform intervals of tiIl,ltl

the intensity of a single heart shape.
Reference 28 presents a detailed discussion of the
relative strengths and weaknesses of wavefonns, pcurves, and other static and dynamic representations
of continuous movement. The discussion focuses on
their uses as inputs of dynamics and as visual feedback
to .the animator, their dimensionality, their role in
guiding temporal and spatial adjustments to existing
motions, their capacity for conceptual extensions, and
some practical problems (and solutions) that arise in
the sketching process. Furthermore, we describe four
kinds of editing and refining capabilities, operations
for:
1.
2.
3.
4.

scaling curves;
shaping and reshaping them;
algebraically and logically combining them; and,
performing pattern scanning, matching, and
transforming functions upon them.

Selection descriptions

Figure ll-The p.,curve corresponding to Figuresi-IO. The
dynamic display is compressed into a single static picture
containing nine selected frames

Consider the algorithm that selects an element of the
current frame from among members of a cel class. A
good example arises in the synthesis of different facial
expressions through the abstraction of discrete shapes
and positions of mouth, nose, eyeballs, and eyebrows.
One eel class could consist of the two members "eyebrows raised" and "eyebrows lowered." An animation
sequence may be achieved by a temporal concatenation
of selections from a cel class. A changing facial expression may be achieved by the parallel application of

282

Spring Joint Computer Conference, 1969

several such sequences of selections, one corresponding
to each facial component. In 'DINNERTEVIE,' this
technique was used to synthesize the movement of the
dog's legs, tail; head; and tongue.
A representation of the dynamic selection fronl a
finite set of alternative pictures is an example of the
second type of global dynamic description and is called
a selection description. The synthesis of selection descriptions is also aided by the use of pictorial representations, such as one consisting of a sequence of steps,
where the length of each step is an integer multiple of
frames, and the height is limited to transitions to and
from posit.ions on a discrete scale. Such pictures
appear at the top of Figures 15 and 20. Superposition
on a common time axis of pictures of several descriptions facilitates coordinating the counterpoint of the
parallel selection strands.
The use of the term "selection" implies that a mechanism chooses from among a designated set of alternatives. In the previous examples the alternatives are
eels, images to be introduced as components of frames
in a dynamic sequence. A more general view of a selection description regards it as a sequence of selectors,
functions which choose from a designated and finite
yet potentially denumerable set of alternatives. Depending upon the picture description capability of the
system in which it is used, and the algorithm which it
drives, a selection description may choose among alternatives that are subpictures, data, picture-generating algorithms, other global dynamic descriptions, pictorial events
or activities, or strands of dynamic activity. For example,
the dynamic selection from among alternative picturegenerating algorithms would be useful in a system
with discrete texture choices, where there is one algorithm capable of filling an arbitrary region with that
texture.
Further details may be found in reference 28, which
also discusses techniques for the definition and editing
of selection descriptions. These are conceptually similar to those used in the synthesis of path descriptions.

Rhythm descriptions
Rhythm descriptions consist of sequences of instants
of display time (frames), or intervals between frames.
They define patterns of triggering or pacing recurring
events or extended picture change. In this context it
is suggestive to think of a rhythm description as a
pulse train. Each pu]se may trigger the same action, Of,
as is discussed in reference 28, it may trigger one of
several act.ivities under the control of a selection description.
Rhythm descriptions fac~litate the achievement of coordination and synchrony among parallel strands of

dynamic activity. In this context it is suggestive to
think of a rhythm description as a sequence of event
:markers. The marking sequence may be defined with
respect to one pictorial subsequence, and then used to
guide the construction of another subsequence.
A rhythm description cannot by itself define picture
change; it can define a beat, a sequence of cues with
respect to which picture change is temporally organized and reorganized. Animators have sometimes used
metronomes as generators of rhythm descriptions. 2
Proper synchronization of a sound track to the visua1
part of a fihn is most critical to its success. 2
Hence, rhythm descriptions marking critical instants
of time play a key role in the synthesis and editing of
movement descriptions. For these operations a rhythm
description requires pictorial representation. In Figure
20 it is depicted both as a static pulse train and as a
sequence of event markers along the axis of movie
time. A direct and simple dynamic input, as we have
seen in 'DINNERTI:;\;IE', consists of tapping out the
rhythm on a push-button.

Dynamic hierarchies
It is easy to conceive of more complex and useful
couplings of global dynamic descriptions. Suppose, for
example, that a hop, a skip, and a jump have each
synthesized with the aid of several path and selection
descriptions. If the animator wishes to experiment with
varying dynamic patterns of hop, skip, and jump, he
should be able to define a selection description which
chooses among these three alternatives. This is equivalent to defining selections among sets of path and se1ection descriptions. Reference 28 discusses the use of
select·ion descriptions to establish arbitrary hierarchies
of structured dynamic behavior, and illustrates the
significance of this capability to the animator.

been

Exploratory studies in interactive computermediated animation
Three special-purpose picture-driven animation systems have been implemented on the ~J.I.T. Lincoln
Laboratory TX-2 computer. A conunon feature is that
each has a construction or editing mode, a playback or
viewing mode, and a fihning mode. In the first mode
the animator may begin work on new pictures and global dynamic descriptions, or may recall and continue
the construction of pictures and descriptions saved from
other sessions. Algorithms embedded in the systelnS
then compute TX-2 display files, in which sequences
of frames composed of points, lines, and conic sections
are encoded for use by the scopes.
These imag~ files are passed to the playback program,

Picture-Driven Animation

which simulates a variable-speed, bi-directional, video
tape recorder. The program nonnally sequences through
the display file representation of successive frames,
making each in turn visible for 1/24th of a second. One
useful option is that of automatic cycling or the simulation of a tape loop.
When the animator has prepared a satisfactory
sequence, he need no longer view it directly on the
scope; but may instead want to record it on fi1orn. A
pin-registered movie camera can be mounted in a lighttight box to a TX-2 scope. Its shutter is always open.
The filming program (a variant of the playback program) "paints" an image on the scope. After a sufficient
time interval to allow the decay of the phosphor,
approximately 1/5 of a second, a signal from the computer advances the camera. A return signal upon the
completion of the advance triggers the display of the
next frame. The camera can be operated on one scope
while we work at a tablet with another scope. Excellent
film quaJity, with high contrast and low jitter, can be
produced with the system.
The first two systems are very special-purpose.
ADAM allows one to animate a crude line-drawing
repre~mtation of a single human figurcl. EVE is an

Figure 12-This picture, "drawn" by the author, illustrates the
varietv of line and texture that may be included in a GE~ESYS
eel as·of December, 1968 Free-hand sketches are portrayed by
points spaced at an arbitrary, user-controlled density.
Straight lines can be solid or can be dotted, over the
same range of densities. Sections of circles, ellipses,
parabolas, and regular polygons may be
included. Arbitrary sub-pictures may be
copied, translated, rotated, and scaled
along two independent dimensions

283

exercise in abstract dynamic art, in which one can animate a set of points linked by "rubber-band" straight
lines. The animation technique in both cases is the
specific9.tion, via wavefonns and p-curves, of the seventeen path descriptions that define the temporal behavior
of the picture's seventeenc ontrolling continuous parameters. A lengthy discussion may be found in reference
28; we shall here content ourselves with three observa.j.:--~.

lJIUllt:5.

1. Clocked hand-drawn dynamics, or the dynamic
mimicking of animated behavior, produces lifelike, energetic movements, even if used in ADAM

to yield stick figure motions that are obviously
not physically realizable, and even if used in
EVE to yield abstract motions.
2. Slight modifications to a waveform result in
significant alterations to the character of an extended interval of a movement. For example,
saunter by the addition of more bounce to the
vertical coordinate path description, or can be
made effeminate by increasing the scale of the
oscillations of the hip's rotational coordinate
path description.

Figure 13-A parametric curve, the final frame of a p-curve,
defining a movement that is life-like and energetic, smooth
and graceful. Observe how points cluster at pauses in
the motion

284

Spring Joint Computer Conference, 1969

3. Even in a system whose only intended application is cartooning, a dynamic mimick~ng capability must be augmented by an edit~ng capability,
for many motions cannot be mimicked or only so
with dijficulty, being purposeful exaggerations of
real movements.
Although GENESYS is also a special-purpose animation system, it is versatile enough to be used in the
generation of a broad class of dynamic images. The
term "generalized-cel," defined in reference 28, is a
generalization of the concept of cel class illustrated in
that its appearance in a given frame of the final dynamic
display is determined by the values of a set of associated
movement descriptions, both continuous and discrete.
The GENESYS animator may sketch, erase, copy,
transiate, rotate, and scale individual cels consisting
of points, straight lines, and conic sections. He may
sketch p-curves and dynamically tap rhythm descriptions. There are numerous tools for the manipulation

Figure 15--The four selection descriptiom; generate the
movements of the jaws, tail, legs, and body of the
crocodiless. Her translational motion is defined by the
two path descriptions below. The oscillator~T
waveform is the vertical coordinate; the
waveform sloping downward,
the horizontal coordinate

of static representations of dynamic descriptions.
Several individuals with varying degrees of artistic
skill and training in animation have constructed short
cartoon sequences with the aid of G ENESYS. Figures
12-20 illustrate some of these experiences.
Conclusion-the representation of dynamic informationThe concept of a picture

Thus the essence of picture-driven animation is:

Figure 14--The crocodiless cavorts across the screen, delighted
at her recent creation on the TX-2 console. The artist,
Miss Barbara Koppel of Chicago, had little animation
experience, no computer experience, a brief
introduction to GENESYS, and assistance in
using it from the author

1. that there exists a set of abstractions of dynamic
information, data sequences which drive algorithms to produce animated displays; and,
2. that these abstractions may in turn be modeled,
generated, and modified by static as well as
animated pictures, modeled in the sense that
the picture structure represents the data s~
quence, generated and modified in the sense

Picture-Driven Animation

Figure 16-The 1st, 7th, 13th, and 19th frames of the 'take-off'
of a bird are shown. The figure is superimposed on the parametric
curve which defines its path through space. Mrs. Johnson
has mimicked the motion by sketching the p-curve; the
bird then reproduces this movement. Observe the
switching among discrete shapes and positions
of its eye, wing. and feet.

Figure 17-All eels used by Mrs. Johnson in the animation of
Oopy-he tiaps his ear, winks, and Rticks out his tongue-are
shown superimposed on t.he left. To the right GENESYS is in
frame mode, in which the current state of a particular
frame is displayed. Also visible are "light-buttons"
representing eel classes (mouth, tongue, eye, ear,
brow). The animator may alter the current
frame, s"itehing the select.ion of a eel
from a class by pointing at it, or changing
it.s position by turning knobs located
under the scope. The underlying
movement descriptions are
automat.icaUy updated
by GENESYS

that the picture represents the process of synthesis as well.
The three kinds of descriptions constitute a rich,
expressive, intuitively meaningful vocabulary for dynamics.
Each type abstracts an important category of dynamic
behavior-flow and continuous change (path descrip-

285

Figure 18-A short cartoon-what the viewer sees: A man,
t.ripping blithely along, kicks a dog lying in his path. The dog
rises and trots off to the right (shown above). It then
returns, teeth bared (shown in Figure 19), and bites
the man. The man jumps and runs away. The dog
first follows, then returns once again to rest.
The duration of the sequence is
approximately 20 seconds

tions), switching and repetitive choice (selection descriptions), and rhythm and synchrony (rhythm
descriptions). The vocabulary is economical, flexible,
and general in the sense that it can characterize the
dynamic similarities that exist in seemingly diverse
animation sequences.
The use of dynamic descriptions couples picture
definition by sketching and by algorithm; it furthermore
allows both local (of the individual frame) and global
(for an interval_ of time) control over dynamics. We
have chosen to stress the latter and adopted the term
"global dynamic description", for it is the capacity
for global control that results uniquely from the use
of the computer as an animat.ion medIum. Yet a dynamic description is not only a representation over an
interval, but a sequence of single elements whose modification also provides local control over individual
frames. Both local and global control are vital to the
successful synthesis of movement. He who accidentally
crashes into a wall while running from the police is
going from the continuous to the discrete, from a global
motion to a local event. He who aims to scale the wall is
interpolating the continuous between the discrete,
adjusting the global to fit the constraints of the local.
The naturalness and power of the vocabulary is
increased by the ability to manipulate it in an interactive graphics environment. There exist, for each
kind of data sequence, static pictorial representations

286

Spring Joint Computer Conference, 1969

Figure 19-A short cartoon-how it was made: Mr Ephraim
Cohen of Orange, New Jersey, a mathematician and programmer
who is also a skilled caricaturist, completed the eels for his
cartoon one week-end afternoon at the TX-2. The system then
crashed, and he was forced to ret-qrn home. He sent through
t.hemail four selection descriptions, to choose eels from
the classeR "man's head", "man's legs", "dog's
head", and "dog's body", and two path
descriptions, to drive horizontally the
man and the dog. The author input the
dynamic descriptions, viewed the result,
and then refined the movie by
several iterations of editing
the descriptions and viewing
the sequence

such as the waveform which provide a global view of
and facilitate precision control of the temporal behavior
implied by the sequences. There exist, for each kind of
data sequence, methods of dynamic specification such
as the clocked sketching of parametric curves which
allow the animator's sense of time t.o be transmitted
directly through the medium of the computer into the
animated display.
We use the term "global dynamic description" and
the names of the three types somewhat loosely in
referring both to the underlying dynamic data sequences
and to their corresponding pictorial representations.
The imprecision is purposefli:l, for it is v~ry significant
that, in an interactive graphics envirdrJIDent, one can
easily traverse in either direction any leg of the triangle
{Dynamic Data Sequence, Static Pictorial Hepresentation, Dynamic Pictorial Representation}. What results
is an important plasticity in the representation of
dynamics. Characterizations of change can be manipulated (shifted, stretched, superimposed, ... ) within and
between the domains of the· static ana the dynamic.

Figure 20-A short cartoon-why it works: The dynamic
descriptions defining Mr. Cohen's cartoon as of January, 1969,
are shown above. The selection descriptions, from top to
bottom, belong to the man's head, the man's legs, the
dog's head, and the dog's body. There are 4, 8,
8, and 4 eels in each class, respectively.
The t.wo waveforms represent the
changes with time of the horizontal
coordinates of the man
and the dog

Several animation sequences can readily be related,
coordinated, or unified, regardless of whether or not
they ever occur concurrently. Dynamic behavior (data)
can readily be tran~ferred from one animation subsequenc'e (including the animator) to another, from one
representation or embodiment in a picture to
mode
another.
Our concept of a picture is a broad one, and purposely
so. For as we stress in reference 28, a computer-mediated
picture is not only what is visible but what is contained in its model in the computer system, And the
system, i.e., an interactive animation system, includes
not only disks and core but an animator and perhaps
an ongoing physics experiment as well as a tape-recorded speech. This system evolves continually through
real time. Occasioro..ally there occurs a particular reor-

of

Picture-Driven Animation

ganization of the system which results in the transfer
of information from the animator to the pictorial data
base, or in a computation on the data base which results
in a sequence of visual images (i.e., data directly convertihle by hardware into visual images). Thus, as we
have stressed before, the act of mimicking dynamics
is a (user-driven) dynamic picture. This unification of
the concepts of picture 'and action is important.
The greater is the number and generality of available models of pictures and of processes of picture
constructipn, the more flexible and powerful is the
animation system in its abHity to deal with dynamic
information. The design of a multi-purpose, open-ended
animation language that allows the aniinator hi:mself
to synthesize new models is outlined in reference 28.
Wi~h such a language one can describe arbitrary
action-picture interpreters that extract movement
descriptions from the animator's use of system devices
and transform them and existing static and dynamic
displays into new static and dynamic displays.
Finally, the use of dynamic descriptions helps establish a conceptual framework which facilitates efficient
use of the resources of the animation system: animator,
software, and hardware. For details, we again refer the

Extensions, applications, implications
This paper is a pointer to a ::.vIarch, 1969, Ph.D.
dissertation,28 which includes the ma'terial contained
herein considerably expanded, some suggestions for
future research, and ....
1. There is a discussion of major difficulties in

implementing systems embodying these ideas,
with thoughts on the criteria supporting subsystems (both hardware and software) should
satisfy to facilitate interactive computer-mediated animation. The environment in which
current implementations exist is described in
another paper being delivered at this conference. 32
2. There is a lengthy outline of a proposed design
of an Animation and Picture Processing Language. APPL is a multi-purpose, open-ended
interactive animation programming language,
through which the animator may also exercise
algoritlunic control over a dynamic display.
The language will contain quasi-parallel flow
of program control, a data structure that is a
generalization of all hierarchic ordered data
representations, an extensible class of picture
descriptors, and a formalism which models the
aniniator's dynamics as it models the dynamics
of any picture, that is, as an integral component

287

of animated system behavior. A major design
goal is plasticity in the representation a (which includes cI>2 as a proper subset)
contains curve segments which may have inft.ection
points and which may cut themselves, as shown in
Figures 3 and 4 .
For display purposes, on a two-dimensional scope
face, it is enough always to work in P3, although for
many practical uses one wants to impose conditions on
the curve to be satisfied in Rn. In particular, one often
wishes to characterize a curve to be displayed in
two-dimensional projection by conditions expressed in
the projective space P", that is, in three-dimensional
homogeneous coordinates.

Iterative generation of curve
There are several methods for generating a curve,
depending upon its parametric representation. The
simplest is to generate a sequence of short line segments
between points on the curve corresponding to successive
values {to, t l , ~, ••• , t N } of the parameter t, with a fixed
difference 5 = l/N between tm and tm+l' Let x(t) =
X(t)/W(t) and yet) = Y(t)/W(t). Let pet) represent
any of the polynomials X(t), yet), or Wet) and let
Pn = P(tn ) = P(n5) forn = 0,1,2, ... ,~. In the usual
fashion we define two difference operators with respect
to the difference 5 as follows:
the forward difference: af(x) = f(x

+ 5)

- f(x)

the backward difference: \7f(x) = f(x) - f(x - 5)

am and \7n are defined recursively and aOf = \7°f = f.
Figure 2-.'\ closed curve

Note that P n + l - Pn = ap" = \7Pn+l and that if
,\Ve consider the family of curve segments

m

pet)
cI> = {V = Vet), 0 ~ t ~ I}

where each component of V is a polynomial in t. We
restrict the discussion to polynomials only because of
the simplicIty of polynomial evaluation. We consider
these curves in Rn; however our interest lies in pn, the
perspective space of dimension n - 1, generated from
Rn by dividing each component of V by the last
component.
Let cI>m be the family of curve segments defined by
polynomials of degree not exceeding m. The higher mis,
the more general is the family cI>m, but generating each
point on any curve is more complex. The greater
generality of cI>m for larger m enables the curve to satisfy
more conditions, but correspondingly requires more
conditions to wliquely define the curve. cI>2 includes
straight lines and conic sections only, Therefore if

=

L

akt k

then amp = \7mp = m!am for any

k=O

value of t. For the convenience of the presentation
we will let m = 3 in the following.
It is easy to see that

[ P~l] [1
aPn+1
a 2P n + 1
a3Pn+1

=

1 0
0 1 1
0 0 1
,0 0 0

or, in short, F n+l = S F
and

n

[ aP
p.n ]
a 2p,.,
,a3p" '

11

I P~l 1 [1

1
\7P n+1
= 0 1
\7 2P l.+1
0 0
... \73Pn +1 ...
,0 0

nrv~: 1

1
1
1
0 1

J

V2P n
_ \73P .. _

Fast Drawing of Curves for Computer Display

299

x

x

X·
Figure 4-Curve which crosses itself

or memory cells. The successive values {Pn } computed
by either method will be used in some fashion to display
the curve.
Let us factorize the matrices S and T to indicate the
two computational schemes:

S=['~0 0~ 1~ 1~].. [(~0 0~ 1~ 0~]I,.:
,0001,

.0001)

1 1 0 0]

0 1 0 0 = At Al Ao
; 0 0 1 0:
~O 0 0 1j

[
I.

x
Figure 3-Curve with inflection point

or, in short, Bn+1 = T Bn.
We have in mind placing the current values {Pn ,
aPn , ••• , amp,,} (or the {VkP,,}) in a set of fast registers

1 1

T

=~
~
[

I.'

!r [

0 0]1. :~ 01

01 01
.0 0 1
:.0 0 0

0 ]":"I
0
1)

1

1
:0
[I1 0
,,0

0
1
0
0

:

0
0
1
0

0]'
0
1:
.
1"
t.

= Ao Al At

where Ai is the operation of adding L\ i+l p to L\ ip
(or VHlp to Vip).

300

Spring Joint Computer Conference, 1969

We periorm these operations in the order Ao, AJ, A2
for forward differences as indicated by the composition
of operators F n+l = A2AIAoF n and in the opposite order
for backward differences.
There are only three additions involved in eitl}er of
these methods. However, there is a basic difference
between them. In the forward difference scheme, each
"new" value ~ ipn+l depends only on "old" values
~iP n, but in the backward difference scheme each "new"
value depends on the current value of the registers. It is
therefore possible to execute all the additions for the
forward difference scheme in parallel, taking only one
addition time for evaluating successive values of the
polynomials. This however requires much hard~are
(adders). The backward difference scheme is more
economical for sequential computation in software, or
in hardware with only one adder. By using extra logic
one can however overlap the three additions in the same
adder and execute them in not much more than one

Basic curve form
For our purposes a curve in RN is a vector-valued
function from the real line R to the real vector space RN
of dimension N.* That is, a curve is an ordered N-tuple
of real functions (fl , f2' ... , fN)' Furthermore, let us
restrict the functions f i to be linear combinations of
some linearly independent set of functions, q, = [q,o, q,l,
, •• , CPM] and let the functions be defined over the
domain [0, 1].
M

Let fj(u) . =

L

AijCPi(U) where the {Aij} are con-

i-O

stants. Then a curve segment can be represented by a
unique (M + 1) X N real matrix A. A point V(n) on
the curve associated with a parameter u is given by
V(u)

of all matrices AH such that H(cp(u)AH) = H(cp(u)A);
it is clear that all the curves in RN specified by the
AHE H[A] will be mapped into the same-curve in RL and
there will thus be many representations of that curve,
Notice that although the original function space[f1, f2, . , " fN]-is a vector space of rank not exceeding
(NI + 1) its image under the mapping H is not necessarily of finite rank and we cannot in general represent
the resulting curve in RL by an expression of the form
W(u) = w(u) B where W(u) € RL, w(u) € RP and set
B a constant matrix of dimension P X L, w(u) a fixed
of basis functions, dependent only on Hand cP, The
mapping H will of course map the curve [fl, f2, ' , " Lv]
into a curve [gI, g2, ' , ., gL] where gi = Hi[fl, ' , ., f N],
where the {Hd are the components of the vector
function H.
We will usually choose the set of basis functions
[CPo, • , " q,M] to be the polynomials [u M, uM-I, , , " u2 ,
U, 1] or some other set of linearly independent polynomials of degree ::.\1. The functions fi will thus be the
real polynomials of degree :M or less. We will also
choose N to be dimension 3 or 4 and L to be dimension
2 or 3 depending on whether we are talking about two
or three dimensional curves, The mapping H will be
that used in making the transformation from homogeneous coordinates to ordinary coordinates, namely,
the projection obtained by dividing the first L components of the vector V (of dimension L + 1 = N)
by the L + 1st component to arrive at the L components
of the vector H(V), We thus identify the curve specified
by the form cpA and the resulting vector V(u) as
homogeneous coordinates of a curve v(u) in dimension one
less. The ma,ny-to-one property of the mapping H is
illustrated by the fact that two points in homogeneous
coordinates, P and Q, are equivalent if and only if
P = aQ for some non-zero a,
Thus we talk about curves of the form

[CPo(u), CPl(U), ... , CPM(U)] A = ep(u) A =

In this context we will say either that the matrix A
represents the curve, or, more pointedly, that the matrix
A is the curve.
If we have some mapping H:RN ~ RL from N
dimensional into L dimensional space then the image
v(u) = H(V(u» of the curve V lUlder the mapping will
be a curve v(u) in RL. The matrix A does not uniquely
represent the curve v(u), We can define the equiva1ence
class H[A] of a matrix A under the mapping as the set

* In other words, we only consider curves in
(explicit), rather than implicit, form,

&.

paramet.ri~

y=

bMu M
dMu M

+ bM~lUM-l + ' , , + blu + b o
+ dM_Iu M- + . , , + dIU + do
1

and optionally,
CMU M
dMu

+ CM_IU M- + . , , + CIU + Co
+ dM_IU - + . , , + dIU + do
1

z = ---------------------------M
MI

The value for each component of a point on the curve
is the ratio of two polynomials in the parameter u, In
theory and in practice we will first do some operations
on the curve in RN (or upon its representation as a
matrix) and only at the last moment before display

Fast Drawing of Curves for Computer Display

perform the mapping H : R,N ~ RL by doing the
division to remove the homogeneous coordinate. In
most cases the many-to-one property of H will not come
into play explicitly but only when we remember that
the points V(u) are expressed in homogeneous
coordinates.
If we have two sets of basis functions for the original
function space [f1, ... , Lv], say [1, ... ( s} x A
\
\

\
\

a(u) [SM

SM-l ••.

1] A = [UM

U M- 1 •••

\

1] S A

\

s=O

\
\

\

which holds if:

\
\

a(u) [SM

SM-l •••

1] = [UM u M -

1 •••

\

1] S .

\

\
\
\

If the rank of the null space of A is zero then it will be
a necessary condition as well. We will not at this time
pursue a further characterization of curves in tenus of
the null space of their associated matrix.
Under these conditions equating appropriate components of the vectors in the above equation gives:
1. for the last (1\'1

,,(u) 1

+

L_u

~

AU

(cua~u)d)M [[(au

~1

and

rLoJ~ 1

= R(u)

It is a polynomial of degree not exceeding

a~) =

;

=

[(:~! ~)" (:~! nw1_- \

= ~\UI

3. for the first component:

",(u) 8 M = ruM ... 1] S

Substituting in the original equation gives:

•••

1]

= rUM ... 1] S =

Q is a polynomial of degree not exceeding
s = Q/a(u) = Q(u)/P(u)

=

invariant transformation

Q au + b
s=P=cu+d·

a(u)

11srn
lJ

a\uI • = lU- ... 'J

8

6~hape

1

2. for the ~Ith component:

M

Figure

and at most NI zeros (including multiplicities) since the
polynomials Rand P are of degree not greater than ~1.
Thus Q/P has at most one zero and one pole and we
have

= ruM ... 1J S [ ; ] = P(u)

_

~

-!'-

Q(u)= cp(u) x B = cp(u) x 5 x A

1Bt) component,

P is a polynomial of degree not greater than :M. If
P = a(u) is a constant then s = u and S = kI for some
constant k, a trivial and uninteresting equality of
curves. Hence we assume P is not a constant.

f_\

~

+

b)M], [(au

+

b)M-l(CU

+ d)],

... , [(cu

+

d)M]]

Each component of ruM ... 1] S is a polynomial of
degree not exceeding M in u. The components on the
right hand side above must thus be the same polynomials. Hence a(u) = e(cu + d)M, where e is a
constant, and by inspection the component Sij of the
matrix S is the coefficient of U M- i in the expansion of
e(au + b)M-i(cu + d)i.
Bypassing the algebra,

:~\,I

and

[~]"

The expression R/P = [Q/P]M has at most

Sij

=e

t

k=O

:vr poles

aM -

i - i +k

bi-

k

c i-

k

dk

(

~-~

_V"-t-1+k

where we use the convention that
k are outside of the range 0 ~ k :;; j.

a)

)

(j)
11:

o when

j,

Fast Drawing of Curves for Computer Display

The matrix S for:U = 2 is

In fact, in general we have
dp
ds dp
du = du ds

and the matrix for M = 3 is
a 2c
2abc + a2 d
b2c + 2abd
b2d

ac2
bc2 + 2acd
bd2

Typically we will want to use the reparameterization
matrix S to change the amount (extent) of a given
curve that is drawn and to alter the rate at which the
moving vector [u M • • • 1] S A traverses the curve. These
variables can be specified by setting
1. s(O) = a
2. s(l) = /3

curve A at which the new curve B begins. /3 is the value
of the parameter s on A at which the curve Bends. r2 is
a ratio of derivatives; the significance of r will be shown
shortly. It is easily .verified that the ratio
CU2
CUI

+ d )~ ~

+d

The product of the magnitudes of the velocity vectors
at the ends of the new curve B is thus (f3 - a)2 times the
product of the magnitudes of the velocity vectors at the
corresponding points s = a, S = {3 of the origi..'rJ.al
curve A. This product thus remains constant for all
similar curves covering the same interval (a, f3) of A.
It is in any case independent of the rate parameter r.
Notice that if r < 0 the new curve will not completely
overlap the old curve in the range 0 ~ u ~ 1, 0 ~ s ~ 1
although over the full line - 00 < u < + 00, - 00 <
. s < + 00 the two curves will be identical. In particular,
at the value u = r/(r - 1), s(u) = ± 00, definitely
outside the domain of the original curve v(s). Thus, for
example, if the matrix A draws half a circle, the matrix
S A will draw the other half in the same direction
if a = 1, /3 = 0, r = -1. (See Figure 7 for an example
of the use of a continuation matrix.)

[-~ -;]
2

a is the value of the parameter s on the original

=(

(f3 -a )r
dp
[(1 - r)u + r]2 ds

For M d 2 this matrix s(l, 0, -1) is

3. s'(O) = r2
s'(1)

s' (Ul)
S'(112)

-3

1

0

-

Substituting the above conditions into s = (au
(cu + d) we solve for a, b, c, d:

the curve A

+

~

b) /

a=/3-ar
b = ar

c = 1- r

303

(f3 - ar)u + ar
ors = ....:...,...-----,,;--(1 - r)u + r

d = r

using the arbitrary condition c + d = 1 to remove the
extra degree of freedom introduced by the homogeneous
form of the function s. The parameter e will allow an
absolute adjustment of the homogeneous coordinate
system, if that is desired.
The velocity vector dv/ds at the beginning (u = 0,
s = a) will be multiplied by the factor (/3 - a)/r and at
the end (u = 1, s = /3) by (f3 - a)r.

the curve S x A

Figure 7-Continuation of a curve

304

Spring Joint Computer Conference, 1969

and for 1'1 = 3 it is

r

1

'

~

_~ 1

2

4

-3

-8

3

4

5

-l~

-1

-1

-1

-1

[-3

J

is non-singular since the basis functions cI>(u) are by
definition four linearly independent polynomials of
degree 3. Define

M =

If we have a curve v(u) = H[iF AT] represented by a
matrix AT for some other basis function iF = rUM U M-l
... 1] T then the reparameterization matrix ST for this
basis will be given by the similarity transformation
ST = T-l STand the curve matrix after reparameterization will be T-l STAT'

:,' cp(O) ]i
cp(l) \
[ cp'(O) ,
, cp'(1) ,
i

A=M

Endpoint-Derivative form
In the previous sections we have been talking about
curves of arbitrary degree; in this section we will be
concerned only with curves of degree m = 3. Let hv = V
denote the homogeneous coordinates of a point in RN,
that is, let h = V N, V = V/VN = V/h where v is a
vector of the form [VI V2 ... VN-l 1]. Then the equation
of a curve is given parametrically by

Vo = ho Vo

d(hv)
Vo = -du

V(u) = h(u) v(u) = cp(u)A
where cp(u) are appropriate 1\1

Let

Lv~J

We now write

I

dimensional basis functions. The curve in RN-l = RL is
obtained by taking the first L components of the vector
v(u); that is, by dividing out the homogeneous coordinate h(u) from the vector h(u)v(u) and dropping the
last component.

[ ~Vol

I

I

v_o

= ho Vo

+ ho Vo
I

where v~, v~ are the derivatives with respect to the
parameter u and where ho, hI, ~, h~ are meaningful only
in homogeneous coordinates. Notice that the last
component of v~ and v~ is O.
Thus

V(0)

=

Vo

["

......u

V(l) = VI
V'(O) = dV(u)
du

I

=

A=l\1:~

V~

,0

u-o

0
hI
0
h~

OJ [vo]

0
0 o
ho o
0 hI'

VI :
V~ i
, V~

V'(l) = VI
The curve is given by
then we have

Vol
v~
=

r

Vo

L

v,I.J

[CP(O)
cp(l)
cp'(O)
A..'/l \
'Y \-'-)

1

I/>(u) A = I/>(u) M :
[
,

A

.J

One can show that the square matrix
cp(O) ]. .;
cp(l)
cp' (0) ,
[
.. ¢'(l)

ho

].
,

~ h: ho
hI

hI

[~]

We can perform the multiplication cI>(u) lVf separately
to define a new set of basis polynomials [F 0 F I Go G l ] = cp
~1 with transformation of basis matrix :\,1 itself. * We
observe that

* This

notation is borrowed freely from S. A. Coons.7.8

Fast Drawing of Curves for Conlputer Display

305

is especially simple, although for a very special basis
function constructed specifically for the particular set
of homogeneous coordinates ho, hI, ~,. h~. This form
shows that a point on the curve V(u) is always a linear
combination of the vectors Yo, VI, V~, v~.

=

l\tT-Il\/f
~~

~~

=

1 0 0
0 1 0
0 0 1
[
000

0]
0
0
1

With these basis functions, a curve can always be
represented by a matrix AM of the form

since it is given by the equation

We will sometimes write this endpoint-derivative form
as

It will also prove useful to rewrite it in the form

Curve specification
In the previous section we have characterized a
rational parametric cubic polynomial curve in terms of
endpoints-v~, v~-and tangent vectors at the endpoints-yo, vI-with four remaining degrees of freedom,
ho, hI, h~, h~. In this section we investigate several ways
of computing the numbers ho, hI, ~, h~ in order to
completely specify the curve from geometric consideration. (See Figure 8). Although some or all of these
results may be inappropriate for a particular application
the techniques used indicate the generality of the curve
formulation and what we believe to be the proper way
to attack the problem.
Let us require the curve to pass through the point vc
at the value U c of the parameter. We have

Vc

=

or in standard form as

We can solve Vc = hg: v for hg: (and hence for h,
since cf is non -singular for any 0 < lie < 1) if and only
if Vc belongs to the range of v. In R3 the geometrical
meaning of this condition is that if the curve is planar,
Ve must be in the same plane, or, if the curve is linear,
Ve must be on the same line. If the curve is' really
three-dimensional then v will have full rank and we
can solve directly for

where now the matrix

In R2 the equation Ve = hg: v is indeterminate since
we have three equations and four unknowns. If Ve is in
the range of v we can impose an additional condition. *
One convenient such condition is to specify that the
slope at Ve be given by the ratio x' elY' c = dx/dy.

V(u)

* Vc will not be in the range of 11 if and only it V~, v~ and Vo - Vl
are collinear and Vc - Vl is not on the same line. This means
that the tangents at each endpoint point to the other end and
Vc is not on the line between the two endpoints.

306

Spring Joint Computer Conference, 1969

or, rearranging,
vo-ve]
VI-V e
,
=
Vo,
[
VI

Denote the left side of the above by Q. Since we are
only concerned with the slope at Ve, we can extract the
first and second components by a post-multiplication
and obtain the ratio

whence

Figure R-8pecifying the curve

Taking derivatives with respect to u we have

u

=

Ue

because we have let he = 1. (ve = [Xc Yc 1]). Since the
third component of v~, v~, v~ is 0 we can solve for

and thus

If we adjoin this single equation to the original equation
for the curve passing t.hrough the point Vc we have

If the matrix is invertible, we can solve for ho, hI, h~,
h~ and determine a curve passing through a specified
point V c with a given slope x~/y~ with given endpoints
vo, VI and tangent vectors V~, V~ at those endpoints. As
with the three dimensional case above we could
characterize this problem in somewhat more generality
in terms of the range of the appropriate matrices, but we
will not do so since the conditions are not simple
enough to be interesting.
We could in the previous examples have just as easily
required the curve to pass through four non-planar
points Va, V(3, VI" Va at different values a, {3, 'Y, 0 of the
parameter.

Fast Drawing of Curves for Computer Display

\tVe would have

or
f,.'

A

=

¢(a)

Tl

Ii ¢~(j~
C/>Vy) J
L'" ¢(8)

Then let' us ask that the curve pass through v c at
u

=

307

which 'Can be solved directly for [ha h,3 hI' hal if the
matrix is non-singular, that is, if the four points are
non -planar. In this way we have asked the threedimensional curve to pass through five specific points at
. five specific values of the parameter. Similar results
could be derived in two dimensions.

REFERENCES
1 R F SPROULL I E SUTHERLAND
A clipping divider

Proc F J C C 1968
2 I E SUTHERLAND

Ut::
::3

Proc F J C C 1968
L G ROBERTS
Homogeneous matrix representation and manipulation of
n-dimensional constructs

The Computer Display Review Adams Associates May 1965
4 H F BAKER
Principles of ge01netry .

where now we have let

1\1 =

6 Vol., Cambridge University Press Cambridge 1922
5 R M WINGER

¢(a)]
¢({j) ' ,

[ ¢('Y)
, ¢(lJ) _

If we define ¢(u c) 1\1 = [Fo Fl F2 F 3] we have after

rearranging

+

An introduction to projective gemnetry

D C Heath and Co Boston 1923
6 G BIRKHOFF S MACLANE
A survey of modern algebra

Macmillan New York 1965
7 S A COONS B HERZOG
Surfaces for computer-aided aircrajt design

Presented at AIAA 4th Annual Meeting and Technica
Display Anaheim California October 1967 American Inst
Aeronautics and Astronautics, New York
8 S A COONS
Surfaces for computer-aided design of space forrns

Project MAC Report MAC-TR-41 MIT June 1967

A class of surfaces for computer display*
by THEODORE lVL P. LEE**
Harvard University

Cambridge, Massachusetts

INTRODUCTION

conditions. The rest of the paper contains primarily
mathematical techniques for manipulating the surfaces.

This paper describes the mathematical formulation of a
class of three-dimensional surfaces parametrically
represented for efficient computer display. The degrees
of freedom in the representation are such as to provide a
rich variety of surfaces with convenient parameters for
manipulation and constraint satisfaction. Historically
this work began as an investigation of the properties of
rational parametric cubics, a class of curves well-suited
to the Harvard three-dimensional display.l.2 The desire
to represent curvilinear surfaces in terms of these curves
and an introduction to the Coons' surface formulation 3
were sufficient to suggest the approach discussed here.
The particular advantages of this approach with
respect to projective transformations and rapid iterative
display did not become apparent until later, although
they may be its most attractive features. The ability to
truly and simply represent such classic surfaces as the
sphere and torus, although a desired goal, was not
demonstrated until even later.
The paper begins with an introduction to homogeneous coordinate geometry, a topic now out of favor
in the general college curriculum. I apologize to those
who may have seen this material before, but it is
necessary for a proper understanding of the results
presented, especially those dealing with continuity

Notation

We will be talking about surfaces, represented as
tensors, curves, represented as matrices, or points,
represented as either three dimensional (ordinary coordinates) or four dimensional (homogeneous coordinates) vectors. A vector, usually a point in homogeneous
coordinates, will always be denoted by boldface type,
for example, V. Where relevant, a four dimensional
vector will be represented by an upper-case letter and a
three dimensional vector by a lower-case letter. Points
or curves may be obtained as part of a higher order
entity or as separate entities.
Subscripts will be used to denote either components
of the array (tensor, matrix, or vector) or to indicate
partial derivatives with respect to the parameters.
Components of vectors will not be in boldface
alt