1971_Motorola_TTL_Integrated_Circuits_Data_Book 1971 Motorola TTL Integrated Circuits Data Book

User Manual: 1971_Motorola_TTL_Integrated_Circuits_Data_Book

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I GENERAL INFORMATION I

ITECHNICAL DATAl

MC3100/MC3000 Series •

Interchangeability Guide
Packaging Information

~

~

ISELECTOR GUIDES I
MC4300/MC4000 Series

•

MTTL Complex Functions

MC5400/MC7400 Series

•

MC5400/MC7400 Series

MC8200/MC7200 Series

•

MTTL III MC3100/MC3000 Series

MC9300/MC8300 Series

•

MTTL II MC2100/MC2000 Series

MCBC5400/MCB5400F Series

•

MTTL I MC500/MC400 Series

TTL Memories

•

Beam Lead MCBC5400/MCB5400F Series

I APPLICATION NOTESI •

Dielectrically Isolated
MCE54HOO/MCE74HOO Series

MTTL Memories

~

•

~
~

TTL

INTEGRATED CIRCUITS

DATA BOOK
This book presents technical data for a broad line of TTL integrated circuits. Complete
specifications for the individual monolithic circuits in the most popular TTL families are
provided in the form of data sheets. In addition, selector guides are included to simplify
the task of chOOSing the best combination of circuits for optimum system architecture.
The information in this book has been carefully checked and is believed to be reliable;
however, no responsibility is assumed for inaccuracies. Furthermore, this information
does not convey to the purchaser of microelectronic devices any license under the patent
rights of any manufacturer.

First Edition
May, 1971
@ MOTOROLA INC., 1971

CONTENTS
GENERAL INFORMATION
Interchangeability Guide
Packaging Information
SELECTOR GUIDES
MTTL Complex Functions
MC5400/MC7400 Series
MTTL III MC31 OO/MC3000 Series
MTTL II MC2100/MC2000 Series
MTTL I MC500/MC400 Series
Beam Lead MCBC5400/MCB5400F Series
Dielectrically Isolated MCE54HOO/MCE74HOO Series
MTTL Memories
TECHNICAL DATA (Data sheets in each section are in alpha-numerical
order unless otherwise noted.)
MC3100/MC3000 Series
Index
General Information
Data Sheets
MC4300/MC4000 Series
Index
General Information
Data Sheets
MC5400/MC7400 Series
Index
General Information
Data Sheets (in numerical order except MC15482/MC17482-MC25482/MC27482.
which follows MC5480/MC7480.)
MC8200/MC7200 Series
Index
Data Sheets
MC9300/MC8300 Series
Index
Data Sheets (includes MC9601/MC8601)
MCBC5400/MCB5400F Series
Index
General Information
Data Sheets
MTTL Memories
Index
Data Sheets
APPLICATION NOTES

The following are trademarks of Motorola Inc.:
MTTL, MTTL I, MTTL II, MTTL III, MDTL,
MECL, MECL II, MECL III, MRTL,

CROSS REFERENCE

The following listings of TTL devices indicate the
Motorola replacement for most TTL devices available.
Devices are referenced to the prime source only - not to
any manfuacturer who may be a second source.
In some cases a Motorola suggested alternate is given.
These parts have pinout and/or specification differences
and therefore are not exact replacements. The alternate will
generally vary by pinouts, function, or specifications. In
many cases the alternate offers improved performance.

FAMILIES REFERENCED
Manufacturer
Texas Instruments

Series Number
SN54/74
SN54H/74H

Fairchild

9000/9300

Signetics

8200/7200
8800
8HOO

National

8200
8500
8600
8800

Sylvania

SUHL I & II

SERIES 54/74 TTL
TEXAS INSTRUMENTS TO MOTOROLA
TEMPERATURE RANGE CROSS REFERENCE
Temperature Range

T.I.

Motorola

ooC to +70 o C
-55°C to +125 0 C

SN74xx
SN54xx

MC74xx
MC54xx

PACKAGE CROSS REFERENCE
Package

T.I.

Motorola

Comments

Flat Ceramic (1/4" x l/S", 1/2" leads)
Dual I n-Line Ceramic
Dual I n-Line Plastic
Flat Ceramic (1/4" x l/S", 1" leads)

F

Special
L
P
F

Motorola Package is 1/4" x 1/4"

J
N
S

DEVICE CROSS REFERENCE
Function

Type
SN7400
SN7401

Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
(Open Collector)
Quad 2-lnput NOR Gate
SN7402
Quad 2-lnput NOR Gate
SN7403
(Open Collector)
Hex I,nverter
SN7404
Hex Inverter (Open Collector)
SN7405
Hex Inverter Buffer/Driver
SN7406
(Open Collector)
Hex Buffer/Driver (Open Collector!
SN7407
SN740S
Quad 2-lnput AND Gate
Triple 3-lnput NAND Gate
SN7410
SN7412
Triple 3-lnput NAND Gate
(Open Collector)
Dual 4-lnput NAND Schmitt Trigger
SN7413
Hex Inverter Buffer/Driver
SN7416
(Open Collector)
Hex Buffer/Driver (Open Collector)
SN7417
Dual 4-lnput NAND Gate
SN7420
Expandable Dual 4-lnput NOR Gate
SN7423
with Enable
Dual 4-lnput NOR Gate with Enable
SN7425
SN7426
Quad 2-lnput High-Voltage Interface
NAND Gate
SN7427
Triple 3-lnput NOR Gate
S-Input NAND Gate
SN7430
Quad 2-lnput OR Gate
SN7432
Quad 2-1 nput NAN D Buffer
SN7437
Quad 2-lnput NAND Buffer
SN743S
(Open Collector)
SN7440
Dual 4-lnput NAND Buffer
SN7441A BCD-to-Decimal Decoder/Driver

SN7442
SN7443
SN7444
SN7445
SN7446

BCD-to-Decimal Decoder
Excess 3-to-Decimal Decoder
Excess 3 Gray-to-Decimal Decoder
BCD-to-Decimal Decoder/Driver
BCD-to-Seven Segment
Decoder/Driver

"To be introduced

Direct
Replacement
MC7400
MC7401
MC7402
MC7403
MC7404
MC7405
MC7406"
MC7407*
MC740S*
MC7410

Suggested
Alternate

-

-

MC3007

MC7416*

-

MC7417*
MC7420

-

MC7426

-

-

-

-

-

MC3003

MC7440
MC7441A

-

MC7442
MC7443
MC7444
MC7445
MC7446

-

MC7430

Comments

-

Both devices have output
breakdown voltage = 30V

-

MCS317B'

,
MC7441 A has zener clamped
outputs, Nixie® display
driver. V out = 55 V

V out = 30 V } MC7446
lout = 20 mA
V out = 40 V }MCS317B
lout = 20 mA

SERIES 54/74 TTL DEVICE CROSS REFERENCE (conti

Type

Function

SN7447

BCD-to-Seven Segment
Decoder/Driver

Direct
Replacement
MC7447

Suggested
Alternate
MC8317D*
MC4039

Comments
V out ; 15 V }MC7447
'out; 20 mA
V out ;20V}MC8317D
'out; 20 mA

MC7448
MC7449
MC7450

MC8307 •

MC7451
MC7453

-

SN7454
SN7460
SN7470
SN7472
SN7473

BCD-to-Seven Segment Decoder
BCD-to-Seven Segment Decoder
Expandable Dual 2-Wide 2-lnput
AOI Gate
Dual 2-Wide 2-lnput AOI Gate
Expandable 4-Wide 2-lnput
AOI Gate
4-Wide 2-lnput AOI Gate
Dual 4-1 nput Expander
J-K Flip-Flop
J-K Flip-Flop
Dual J-K Flip-Flop

MC7454
MC7460
MC7470
MC7472
MC7473

-

SN7474

Dual Type D Flip-Flop

MC7479

SN7475

Quad Latch

MC7475

SN7476
SN7477
SN7480
SN7481
SN7482

Dual J-k Flip-Flop
Quad Latch
Gated Full Adder
16-B it Memory
2-Bit Adder

MC7476
MC7477
MC7480
MC4004
MC17482

MC4005
MC27482

SN7483

4-Bit Adder

MC7483

MC8260

SN7484
SN7485
SN7486

Gated·lnput 16-Bit Memory
4-Bit Comparator
Quad Exclusive OR Gate

MC7484

MC4022
MC3021

SN7488
SN7489
SN7490

256-Bit Read Only Memory
64-Bit Random Access Memory
Decade Counter

MC7490

MCM4064
MC4023

MC7491A
MC7492

MC4023

SN7448
SN7449
SN7450
SN7451
SN7453

SN7491A 8-Bit Shift Register
Divide-by-12 Counter
SN7492

-

-

MC3052
MC3050
MC3061

MC4015

-

4-Bit Binary Counter
4-Bit Sh ift Register

MC7493
MC7494*

MC4015

SN7495

4-Bit Universal Shift
Register
5-Bit Shift Register
8-Bit Bistable Latch
J-K Flip-Flop
J-K Flip-Flop
Dual J-K Flip-Flop

MC7495

MC4012

MC7496
MC74100*
-

MC7474

SN74110
SN74111
SN74121
SN74122
SN74123
SN74141

J-K Flip-Flop
J-K Flip-Flop
Monostable Multivibrator
Retriggerable Monostable
M ultivibrator
Dual Retriggerable
Monostable Multivibrator
BCD-to-Decimal Decoder

"To be introduced

MC74107

MC74121
-

14-pin flat pack only
MC4005 lout; 20 mA
MC17482 faster, slightly
different loading.
MC27482 has exclusive OR
outputs for look-ahead
carry schemes.
MC8260 has greater
functional capability.

MC3021 is pin compatible,
IF; 3.0 mA;
7486 IF; 1.6 mA

MC4023 fTog; 30 MHz,
multicount capability
MC4023 fTog; 30 MHz,
multicount capability

-

SN7493
SN7494

SN7496
SN74100
SN74104
SN74105
SN74107

MC3050 is edge triggered
MC3061 f Tog ; 40 MHz,
edge triggered
MC7479 has buffered outputs,
Set-Reset override clock.
MC4015 is quad edgetriggered flip-flop

MC8601
MC8602*
-

MC4015 higher speed,
lower power
MC4012 fTog = 30 MHz,
PD;180mW

MC7474 has VCC on Pin 14,
Gnd on Pin 7

SERIES

54n4

TTL DEVICE CROSS REFERENCE (contI

Type

Function

Direct
Replacement

Suggested
Alternate

-

SN74145
SN74150
SN74151
SN74152
SN74153

BCD-to-Decimal Decoder/Driver
16-Bit Data Selector
a-Bit Data Selector
8-Bit Data Selector
Dual 4-Bit Data Selector

MC74145
MC74150'
MC74151'
MC74152"
MC74153*

MC8312
MC8312
MC4000

SN74154
SN74155

One-of-16 Decoder
Dual One-of-Four Line Decoder

MC8311
MC74155*

MC4007

SN74156

Dual Two-to-Four Line Decoder
(Open Collector)
BCD Counter
Synchronous 4-Bit Binary COllnter
Synchronous 4-Bit Decade Counter
Synchronous 4-Bit Binary Counter
8-Bit Serial-I n/Parallel-Out
Shift Register
8-Bit Parallel-In/Serial-Out
Shift Register
Synchronous 8-Bit Shift Register
4-by-4 Register File
8-Bit Parity Generator
Arithmetic Logic Unit
Carry Generator
Binary-to-BCD Converter

MC74156"

-

MC9310
MC9316

-

SN14160
SN74161
SN74162
SN74163
SN74164
SN74165
SN74166
SN74170
SN74180
SN74181
SN74182
SN74185

SN74190
SN74191
SN74192
SN74193
SN74196
SN74197
SN74198
SN74199

Synchronous Decade Up/Down
Counter
Synchronous 4-Bit Binary
Up/Down Counter
Synchronous Decade Counter
Synchronous Binary Counter
50-MHz BCD Counter
50-MHz Presettable Binary Counter
8-Bit Parallel In-Out Left-Right
Shift Register
8-Bit Parallel In-Out J-K Input
Shift Register

'To be introduced

-

-

MC74165*

-

-

MC7260'
MC7261'
MC4001

-

-

-

-

MC74192*
MC74193*

-

-

MC4007 tpd = 14 ns,
PD=125mW

-

MC74164*

-

MC4000 tpd = 18 ns,
Po = 150 mW

-

-

MC74180*
MC74181'
MC74182*

Comments

-

MC8280'
MC8316
MC8291·

-

-

-

-

MC4001 expandable to any
number of bits. Converts
BC D to Binary or Binary
to BCD

SERIES 54H/74H (MC3000) TTL
TEXAS INSTRUMENTS TO MOTOROLA
TEMPERATURE RANGE CROSS REFERENCE
Temperature Range

T.I.

Motorola

OoC to +70 oC
-55°C to +125 0 C

74Hxx
54Hxx

MC30xx
MC31xx

PACKAGE CROSS REFERENCE
Package
Flat
Dual
Dual
Flat

Ceramic
I n-Line
I n-Line
Ceramic

(1/4" x 1/S", 1/2" leads)
Ceramic
Plastic
(1/4" x 1/S", 1" leads)

T.I.

Motorola

Comments

F
J
N
S

Special
L
P
F

Motorola Package is 1/4" x 1/4"

DEVICE CROSS REFERENCE
Direct
Replacement

Type

Function

SN74HOO
SN74H01
SN74H04
SN74H05
SN74H08
SN74H10
SN74H11
SN74H20
SN74H2l
SN74H22
SN74H30
SN74H40
SN74H50
SN74H51
SN74H52
SN74H53
SN74H54
SN74H55
SN74H60
SN74H61
SN74H62
SN74H71
SN74H72
SN74H73
SN74H74
SN74H76

Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate (Open Collector)
Hex Inverter
Hex Inverter (Open Collector)
Quad 2-lnput AND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
Dual 4 Input NAND Gate (Open Collector)
8-lnput NAND Gate
Dual4-lnput NAND Buffer
Expandable Dual2-Wide 2-lnput AOI Gate
Dual 2-Wide 2-lnpu~ AOI Gate
Expandable 4-Wide 2-2-2-3 Input AND-OR Gate
Expandable 4-Wide 2-2-2-3 Input AOI Gate
4-Wide 2-2-2-3 Input AOI Gate
Expandable 2 -Wide 4-1 nput AOI Gate
Dual 4-lnput Expander
Triple 3-lnput E>:,pander
4-Wide 3-2-2-3 Input Expander
J-K Flip-Flop
J-K Flip-Flop
Dual J-K Flip-Flop
Dual Type 0 Flip-Flop
Dual J-K Flip-Flop

SN74H78
SN74H101
SN74H102
SN74H103
SN74H106

Dual J-K Flip-Flop
J-K Flip-Flop
J-K Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop

-

SN74H108

Dual J-K Flip-Flop

-

MC3000
MC3004
MC3008
MC3009
MC3001
MC3005
MC3006
MC3010
MC3011
MC3012
MC3016
MC3024
MC3020
MC3023
MC3031
MC3032
MC3033
MC3034
MC3030
MC3019
MC301S
MC3054
MC3055
MC3063

-

Suggested
Alternate
-

-

-

-

-

-

-

-

-

MC3060
MC3062,
MC3063
MC3061
MC3054
MC3055
·MC3063
MC306:!,
MC3063
MC3061

9000/9300 SERIES TTL
FAIRCHILD TO MOTOROLA
PACKAGE AND TEMPERATURE RANGE CROSS REFERENCE
Package
14-Pin
14-Pin
16-Pin
16-Pin
14-Pin
14-Pin
16-Pin
16-Pin

Flat Ceramic (1/4" x 1/4")
Flat Ceramic (1/4" x 1/4")
Flat Ceramic (1/4" x 3/a")
Flat Ceramic (1/4" x 3/a")
Dual In-Line Ceramic
Dual In-Line Ceramic
Dual In-Line Ceramic
Dual In-Line Ceramic

Temperature Range

Fairchild

Motorola

OoC to +75 0 C
_55°C to +125 O C
OoC to +75 0 C
-55°C to +125 O C
OoC to +75 0 C
_55°C to +125 O C
OoC to +75 O C
-55°C to +125 0 C

U319xxx59x
U319xxx51x
U4L9xxx59x
U4L9xxx51x
U6A9xxx59x
U6A9xxx51X
U6B9xxx59x
U6B9xxx51x

MC8xxxF
MC9xxxF
MC8xxxF
MC9xxxF
MCaxxxL
MC9xxxL
MCaxxxL
MC9xxxL

DEVICE CROSS REFERENCE
Type

Function

Direct
Replacement
-

Suggested
Alternate

9000
9001
9002

J-K Flip Flop
J-K Flip Flop
Quad 2-1 nput NAN D Gate

MC3052t
MC7400#t

MC3000

9003
9004

Triple 3-lnput NAN D Gate
Dual 4-lnput NAND Gate

MC7410#t
MC7420#t

MC3005
MC3010

9005

Dual Expandable AOI Gate

MC7450#t

MC3020

9006
9007

Dual Expander
a-Input NAND Gate

MC7460#t

-

MC3030
MC3015

900a

4-Wide Expandable AOI Gate

-

MC7453#(

9009
9014
9015
9016
9017

Dual 4-lnput Buffer
Quad Exclusive OR Gate
Quad NOR Gate
Hex Inverter
Hex Inverter (Open Collector)

9020
9022
9024
9033

Dual J-K Flip Flop
Dual J-K Flip Flop
Dual J-K Flip Flop
lS-Bit Memory

9034

25S-Bit Read Only Memory

MCM4002

9035
9300

64-Bit Memory
4-Bit Shift Register

MC9300

9301
9304
930S
9307

BCD-to-Decimal Decoder
Dual Full Adder
Up/Down BCD Counter
Seven-Segment Decoder

MC9301
MC9304
MC930S*
MC9307*

MC74192
MC7448

9308
9309
9310

Dual 4-Bit Latch
Dual 4-lnput Multiplexer
Programmable BCD Up Counter

MC930a
MC9309
MC9310

MC4000
MC4016

9311
9312
9314

One-of-16 Decoder
a-Input Multiplexer
4-Bit Latch

MC9311
MC9312
MC9314*

MC7440#t

MC7404t

-

-

-

MC3051

Comments
MC3051 is edge triggered

-

MC3024
MC3021
MC3002
MC3024
MC7405,
MC3009
MC3061
MC30S2
MC3060
MC4004

MCM40S4
MC4012

MC3000 has superior
characteristics
Active bypass
Improved power vs.
frequency characteristic
Direct pin replacement for
DI L and flat pack
MC3015 pin compatible
with 9007
MC7453 is 2-2-2-2 Input
9008 is 2-2-2-3 Input

Edge triggered
High speed (50 MHz)
MC4004: VCC = Pin 4
Gnd = Pin 10
Optional pullup resistors to
facilitate wire OR outputs
(custom metalization)
MC4012 PD = 1aO mW,
fTog = 30 MHz

Active high outputs,
MC7448 is pin replacement

MC4016 programs in binary
code, counts down

MC4015

t These devices are pinout replacements but may vary in electrical specifications
* To be introduced
#Dual in-line package only

MC4015 Quad Type D
Flip-Flop

9000/9300 SERIES TTL DEVICE CROSS REFERENCE (conti

Type

Function

Direct
Replacement

9315
9316

BCD-to-Decimal Decoder/Driver
Programmable Binary Up Counter

MC7441A
MC9316*

9317
9318
9321

Seven-5egment Decoder
8-1 nput Priority Encoder
Dual One-of-Four Decoder

MC9317*
MC9318*

9322
9324
9325
9327
9328
9334
9337
9338
9340
9341
9342
9348

Quad 2-lnput Multiplexer
5-Bit Comparator
BCD-to-Decimal Decoder/Driver
Seven-5egment Decoder
Dual 8-Bit Shift Register
8-Bit Addressable Latch
Seven-Segment Decoder
8-Bit Multiple Register
Arithmetic Logi" Unit
4-Bit Arithmetic Ligic Unit
Carry Extender
12-Bit Parity Tree

9350
9352
9353
9354
9356
9357A
9357B
9358
9359
9360
9366
9375
9377
9380
9382
9383
9390
9391
9392
9393
9394
9395
9396

Decade Up Counter
BCD-to-Decimal Decoder
Excess 3-to-Decimal Decoder
Excess 3 Gray-to-Decimal Decoder
4-Bit Binary Counter
BCD-to-5even Segment Decoder/Driver
BCD-to-5even Segment Decoder/Driver
BCD-to-Seven Segment Decoder
BCD-to-5even Segment Decoder
Decade Up/Down Counter
Binary Up/Down Counter
4-Bit Latch
4-Bit Latch
Full Adder
2-Bit Full Adder
4-Bit Full Adder
Decade Counter
'8-Bit Shift Register
Divide-by-12 Counter
Binary Counter
4-Bit Shift Register
4-Bit Universal Shift Register
5-Bit Shift Register

Suggested
Alternate

MC4018
MC744617

-

-

MC4007

-

MC8266*
MC4022

MC74141

MC9328
-

MC74181*
MC74182*

MC7442
MC7443
MC7444

MC7446
MC7447
MC7448
MC7449
MC74192*
MC74193*
MC7475
MC7477
MC7480
MC7482
MC7483
MC7490
MC7491
MC7492
MC7493
MC7494*
MC7495
MC7496

Comments
Nixie® driver capability
MC4018 programs in binary
code, counts down
MC744617 pin replacements
MC4007 Po = 125 mW,
tpd = 14 ns.

MC7446

MC7260·

MC7261*
MC4008,
MC4010
MC4023

MC7493

-

-

-

t These devices are pinout replacements but may vary in electrical specifications
• To be introduced
#Dual in-line package only

MC4008, 4010 expandable
to any size words

Del ... TTL
SIGNETICS TO MOTOROLA
TEMPERATURE RANGE CROSS REFERENCE
(8200 SERIES ONLY)
Temperature Range

Signetics

Motorola

OoC to +75"C
-55°C to +125 O C

N82xx
S82xx

MC72xx
MC82xx

PACKAGE CROSS REFERENCE
Package
14-Pin
16-Pin
16-Pin
14-Pin
14-Pin
24-Pin
14-Pin
16-Pin
24-Pin

Dual In-Line Plastic
Dual I n-Line Plastic
Dual I n-Line Ceramic
Dual In-Line Ceramic
Flat Glass
Flat Ceramic
Flat Ceramic
Flat Ceramic
Dual In-Line Ceramic

Signetics

Motorola

Comments

A
B
E
F
J
P
Q
R
y

P
P
L
L
F
F
F
F
L

Motorola package is ceramic

Direct
Replacement

Suggested
Alternate

DEVICE CROSS REFERENCE
Type

Function

N8200

Dual 5-Bit Register

-

MC4015

N8202

10-Bit Register

-

MC4015

N8230

8-lnput Data Selector

-

N8241
N8242
N8250
N8251
N8260
N8261
N8266

Quad Exclusive OR Gate
4-Bit Comparator
Binary-to-Octal Decoder
BCD-to-Decimal Decoder
Arithmetic Logic Element
Fast Carry Extender
4-Bit 2-lnput Data
Selector
4-Bit 2-lnput Data
Selector (Open Collector)
Gated Full Adder
4-Bit Universal Shift
Register
4-Bit Universal Shift
Register
Quad Latch
8-Bit Shift Register
Presettable Decade Counter
Presettable Binary Counter
Synchronous Binary
Up/Down Counter
Synchronous Decade
Up/Down Counter
Presettable Divide-by-12
Counter

MC8312,
MC74151'
MC3021
MC3022
MC4006
MC8301

N8267
N8268
N8270
N8271
N8275
N8276
N8280
N8281
N8284
N8285
N8288

MC7241
MC7242
MC7250'
MC7251'
MC7260'
MC7261'
MC7266*

-

-

MC7267*

-

-

MC7480
MC4012

MC7270*
MC7271*

MC7280'
MC7281*
MC7284*

Comments
MC4015 Quad Flip Flop, has
direct Set, Reset, 30-MHz
data rate
MC4015 Quad Flip Flop, has
direct Set, Reset, 30-MHz
data rate

MC8300
MC7475
MC7491A
MC4016
MC4018

-

MC7285*

-

MC7288*

MC7492

MC4016 fully programmable
MC4018 fully programmable

• To be introduced
•• Direct replacement can be supplied as a special.
# Motorola flat-pack device direct replacement for Signetics flat-pack device.
## Motoroia device direct repiacement in duai-in-iine packages ii>, L). Can supply F package as speCial.

DCl •••TTl DEVICE CROSS REFERENCE (cont)

Type
N8806
N8808
N88l6
N8822
N8825
N8826
N8827
N8828
N8829
N8840
N8848
N8855
N8870
N8880
N8881
N8885
N8H16
N8H20
NSH21
N8H22
N8H70
N8H80
N8H90

Function
Dual Expander
8·lnput NAND Gate
Dual4-lnput NAND Gate
Dual J-K Flip Flop
J-K Flip Flop
Dual J-K Flip Flop
Dual J-K Flip Flop
Dual Type D Flip Flop
J-K Flip Flop
Dual AOI Gate
4-Wide AOI Gate
Dual 4-lnput Power Gate
Triple 3-lnput NAND Gate
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
(Open Collector)
Quad 2-lnput NOR Gate
Dual 4-lnput NAND Gate
Dual J-K Flip Flop
Dual J-K Flip Flop
Dual J-K Flip Flop
Triple 3-lnput NAND Gate
Quad 2-lnput NAND Gate
Hex Inverter

Direct
Replacement
MC7460
MC7430

-

MC7479
MC7472
MC7450
MC7453

-

-

MC7401

Suggested
Alternate

MC7420··#
MC7473#
MC3051
MC3061
MC3062

MC7440"
MC7410#
MC7400"#

MC7402
MC3010##
MC3061
MC3062

-

MC3005##
MC3000##
MC3008##

-

MC7479 has buffered outputs

MC3051

-

-

Comments

-

-

re,oao w;~

,,, .~;~

bypass, improved power vs.
frequency characteristic,
improved tpd vs.
temperature.

• To be introduced
•• Direct replacement can be supplied as a special.
# Motorola flat-pack device direct replacement for' Signetics flat-pack device.
##Motorola device direct replacement in dual-in-line packages (P, L). Can supply F package as special.

DM7000/8000 SERIES TTL
NATIONAL TO MOTOROLA
TEMPERATURE RANGE CROSS REFERENCE
Temperature Range

oOc to

+70 oC
-55°C to +125 0 C

National

Motorola

DM8xxx
DM7xxx

MC74xx
MC54xx

PACKAGE CROSS REFERENCE
Package

National

Motorola

Dual In-Line Ceramic
Flat Ceramic (1/4" x 1/4")
Dual I n-Line Plastic

0
F

L
F
P

N

DEVICE CROSS REFERENCE
Type
DM8200
DM8210
DM8211
DM8213
DM8220
DM8283
DM8520

Function
4-Bit Digital Comparator
8-Channel Digital Switch
8-Channel Multiplexer
with Strobe
4-to-16 Line Decoder
Parity Checker/Generator
4-Bit Full Adder
Modulo N Divider

Direct
Replacement

MC8311

Suggested
Alternate

-

MC7483
-

MC4008
MC7260·
MC4016/18

DM8530
DM8532
DM8533
DM8550
DM8551
DM8560
DM8563
DM8570

Decade Counter
Divide-by-12 Counter
Divide-by-16 Counter
Quad Latch
Buss aRable Quad 0
Decade Up/Down Counter
Binary Up/Down Counter
Serial I n-Parallel Out
8-Bit Shift Register

MC7490
MC7492
MC7493
MC7475

MC7280*
MC7288·
MC7281·
MC4015

MC74192·
MC74193·
MC74164·

MC7495

DM8580

4-Bit Universal
Shift Register
Parallel In Serial Out
8-Bit Shift Register

MC7495

MC4012

MC74165*

MC7495

4-Bit Universal Shift
Register
Presettable Decade Counter
Presettable Binary Counter
Presettable Divide-by-12
Counter
Quad 2-lnput TTL-to-MOS Gate
Quad 2-lnput TTL-to-MOS Gate
14-volt Hex Inverter
(Open Collector)
Line Receiver
EIA RS-232C Line Receiver
Line Driver
BCD-to-Decimal Decoder/Driver
BCD-to-Decimal Decoder
BCD-to-Seven Segment
Decoder/Driver
BCD-to-Seven Segment
Decoder/Driver
BCD-to-Seven Segment
Decoder/Driver
Retriggerable Monostable
Multivibrator

MC8300

DM8590

DM8600
DM8680
DM8681
DM8688
DM881 0
DM8811
DM8812
DM8820
DM8822
DM8830
DM8840
DMB842
DM8846
DM8847
DM8848
DM8850

·To be introduced

-

-

Comments

-

-

MC4016/18 program directly
in binary/BCD code
MC7280 is presettable
MC7288 is presettable
MC7281 is presettable
MC4015 is Quad 0 Flip Flop

Two MC7495's can perform
parallel or serial in, parallel
or serial out function
MC4012 Po = 180 mW,
fTOt,= 30 MHz
Two C7495's can perform
8 bit parallel or
serial in, parallel
or serial out function

-

-

-

-

-

-

MC1584
MC1488
MC1582

MC7441 A
MC7442
MC7446

-

MC7447

-

MC7448

-

MC9601

-

-

MC1488 is quad

Active low, V out = 30 Volts,
lout = 20 mA
Active low, V out = 35 Volts,
lout = 20mA
Active High

SUHL TTL
SYLVANIA TO MOTOROLA
TEMPERATURE RANGE CROSS REFERENCE
Temperature Range

Sylvania

Motorola

SF and SG Series (Example: SG40)
-55°C to +125°C, High Fan-Out

SG40
(Base Number)
SG41
SG42
SG43

-55°C to +125 0 C, Low Fan-Out
OoC to +75 0 C, High Fan-Out
OoC to +75 0 C, Low Fan-Out

MC500
MC550
MC400
MC450

SM Series (Example: SM10 - applies only to Direct Replacementl
-55°C to +125 0 C. High Fan-Out

SM10
(Base Number)
SM11
SM12
SM13

+125 0

-55°C to
C, Low Fan-Out
OOC to +75 0 C, High Fan-Out
0
OOC to +75 C, Low Fan-Out

MC4326
MC4327
MC4026
MC4027

PACKAGE CROSS REFERENCE
Package

Sylvania

Motorola

Dual In-Line Ceramic (Black)
Flat Ceramic
Dual In-Line Ceramic
Dual In-Line Plastic

01
02
03

L
F
L
P

Comments
Motorola package is 1/4" x 1/4"
Motorola only

DEVICE CROSS REFERENCE
Type
SF10
SF11
SF12
SF13
SF20
SF21
SF22
SF23
SF30
SF31
SF32
SF33
SF50
SF51
SF52
SF53
SF60
SF61
SF62
SF63
SF80
SF81
SF82
SF83
SF91
SF93
SF100

Function

Direct
Replacement
MC513
MC563
MC413
MC463
MC514
MC564
MC414
MC464
MC521
MC571
MC421
MC471
MC515
MC565
MC415
MC465
MC516
MC566
MC416
MC466
MC522
MC572
MC422
MC472
MC572
MC472
MC573

SF101

R-5 Flip-Flop
R-5 Flip-Flop
R-5 Flip-Flop
R-5,Flip-Flop
Gated R-5 Flip-Flop
Gated R-5 Flip-Flop
Gated R-S Flip-Flop
Gated R-5 Flip-Flop
AC Coupled R-S Flip-Flop
AC Coupled R-5 Flip-Flop
AC Coupled R-S Flip-Flop
AC Coupled R-5 Flip-Flop
AND J-K Flip-Flop
AND J-K Flip-Flop
AND J-K Flip-Flop
AND J-K Flip-Flop
OR J-K Flip-Flop
OR J-K Flip-Flop
OR J-K Flip-Flop
OR J-K Flip-Flop
Dual Type 0 Flip-Flop
Dual Type 0 Flip-Flop
Dual Type 0 Flip-Flop
Dual Type 0 Flip-Flop
Dual Type 0 Flip-Flop
Dual Type 0 Flip-Flop
Dual J-K Flip-Flop
(Separate Clock, 35 MHz)
Dual J-K Flip-Flop

SF102

Dual J-K Flip-Flop

MC423

MC573

Suggested
Alternate

-

MC2126
MC2176
MC2026
MC2076
MC3160
MC3160
MC3060
MC3060
MC3160
MC3060
MC3162
MC2123
MC3162
MC2173
MC3062
MC2023

SUHL TTL DEVICE CROSS REFERENCE (conti
Direct
Replacement

Function

Type

Suggested
Alternate

SF103

Dual J-K Flip-Flop

MC473

SF1.10

MC524

SF111

Dual J-K Flip-Flop
(Common Clock, 35 MHz)
Dual J-K Flip-Flop

SF112

Du;!1 J-K Flip-Flop

MC424

SF113

Dual J-K Flip-Flop

MC474

SF120

MC2123
MC2173
MC2023
MC2073
MC2124

MC3162
MC3062
MC3062
MC3161

SF131
SF132
SF133
SF200
SF201
SF202
SF203
SF210
SF211
SF212
SF213
SF250

Dual J-K Flip-Flop
(Separate Clock, 50 MHz)
Dual J-K Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop
(Common Clock, 50 MHz)
Dual J-K Flip-Flop
Dual J-K Flip-F lop
Dual J-K Flip-Flop
AND J-K Flip-Flop (50 MHz)
AND J-K Flip-Flop
AND J-K Flip-Flop
AND J-K Flip-Flop
OR J-K Flip-Flop (50 MHz)
OR J-K Flip-Flop
OR J-K Flip-Flop
OR J-K Flip-Flop
AND J:K Flip-Flop (30 MHz)

MC3062
MC2073
MC3161
MC2124
MC3161
MC2174
MC3061
MC2024
MC3061
MC2074
MC3162

MC2174
MC2024
MC2074
·MC2125
MC2175
MC2025
MC2075
MC2126
MC2176
MC2026
MC2076

SF251

AND J-K Flip-Flop

-

SF252

AND J-K Flip-Flop

-

SF253

AND J-K Flip-Flop

-

SF260

OR J-K Flip-Flop (30 MHz)

-

SF261

OR J-K Flip-Flop

-

SF262

OR J-K Flip-Flop

-

SF263

OR J-K Flip-Flop

-

MC3161
MC3061
MC3061
MC3151
MC3151
MC3051
MC3051
MC3154
MC3154
MC3054
MC3054
MC3151
MC2125
MC3151
MC2175
MC3051
MC2025
MC3051
MC2075
MC3154
MC2126
MC3154
MC2176
MC3054
MC2026
MC3054
MC2076

SG40
SG41
SG42
SG43
SG50
SG51
SG52
SG53
SG60
SG61
SG62
SG63
SG70
SG71
SG72
SG73
SG80
SG81
SG82
SG83

Dual 4-lnput NAN D Gate
Dual 4-lnput NAN D Gate
Dual 4-lnput NAN D Gate
Dual 4-lnput NAN D Gate
Expandable 4-Wide 2-2-2-3 Input AOI
Expandable 4-Wide 2-2-2-3 Input AOI
Expandable 4-Wide 2-2-2-3 Input AOI
Expandable 4-Wide 2-2-2-3 Input AOI
8-lnput NAND Gate
8-lnput NAND Gate
8-lnputNAND Gate
8-lnput NAND Gate
Expandable Dual2-Wide 2-lnput AOI
Expandable Dual2-Wide 2-lnput AOI
Expandable Dual2-Wide 2-lnput AOI
Expandable Dual2-Wide 2-lnput AOI
Dual Pulse Shaper/Delay AN D Gate
Dual Pulse Shaper/Delay AND Gate
Dual Pulse Shaper/Delay AND Gate
Dual Pulse Shaper/Delay AND Gate

SF121
SF122
SF123
SF130

MC574

-

Gate
Gate
Gate
Gate

Gate
Gate
Gate
Gate

MC500
MC550
MC400
MC450
MC501
MC551
MC401
MC451
MC502
MC552
MC402
MC452
MC520
MC570
MC420
MC470
MC526
MC576
MC426
MC476

-

-

-

SUHL TTL DEVICE CROSS REFERENCE (cont)
Type

Function

Direct
Replacement

SG90
SG91
SG92
SG93
SG100
SG10l
SG102
SG103
SG110
SG111
SGl12
SG113
SG120
SG121
SG122
SG123
SG130
SG131
SGl32
SG133
SGl40

2-Wide 3-lnput AOI Gate with Gated Complement
2-Wide 3-lnput AOI Gate with Gated Complement
2-Wide 3-lnput AOI Gate with Gated Complement
2-Wide 3-lnput AOI Gate with Gated Complement
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable 2-Wide 4-lnput AOI Gate
Expandab!e 2-Wide 4-lnput AOI Gate
Expandable 2-Wide 4-lnput AOI Gate
Expandable 2-Wide 4-lnput AOI Gate
Expandable 8-lnput NAND Gate
Expandable8-lnput NAND Gate
Expandable 8-lnput NAN D Gate
Expandable 8-lnput NAND Gate
Dual 4-lnput Line Driver
Dual 4-lnput Line Driver
Dual 4-lnput Line Driver
Dual 4-lnput Line Driver
Quad 2-lnput NAND Gate

MC503
MC553
MC403
MC453
MC504
MC554
MC404
MC454
MC505
MC555
MC405
MC455
MC506
MC556
MC406
MC456
MC507
MC557
MC407
MC457
MC508

SG141

Quad 2-lnput NAND Gate

MC558

SG142

Quad 2-lnput NAND Gate

MC408

SG143

Quad 2-lnput NAND Gate

MC458

SG150
SG151
SG152
SG153
SG160
SG161
SG162
SG163
SG170
SG171
SG172
SG173
SG180
SG181
SG182
SG183
SG190
SG191
SG192
SG193
SG2DO
SG201
SG202
SG203
SG210
SG211
SG212
SG213
SG.220
SG221
SG222
SG223
SG230
SG231
SG232
SG233

4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates
Triple 2-lnput Buss Driver
Triple 2 -Input Buss Driver
Triple 2 -Input Buss Driver
Triple 2-lnput Buss Driver
Dual 4-lnput Expander for AOI Gates
Dual 4-lnput Expander for AOI Gates
Dual 4-lnput Expander for AOI Gates
Dual4-lnput Expander for AOI Gates
Dual4-lnput Expander for NAND Gates
Dual 4-lnput Expander for NAND Gates
Dual4-lnput Expander for NAND Gates
Dual 4-lnput Expander for NAND Gates
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Expandable 8-lnput NAN D Gate
Expandable 8-1 nput NAN D Gate
Expandable 8-lnput NAND Gate
Expandable 8-lnput NAND Gate
Expandable 2-Wide 4-lnput AOI.Gate
Expandable 2-Wide 4-lnput AOI Gate
Expandable 2-Wide 4-lnput AOI Gate
Expandable 2-Wide 4-lnput AOI Gate
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates
4-Wide 3-2-2-3 Input Expander for AOI Gates

MC509
IV!C559
MC409
MC459
MC519
MC569
MC419
MC469
MC510
MC560
MC410
MC460
MC511
MC561
MC411
MC461
MC512
MC562
MC412
MC462
MC2111
MC2161
MC2011
MC2061
MC2100
MC2150
MC2000
MC2050
MC2101
MC2151
MC2001
MC2051
MC2102
MC2152
MC2002
MC2052

Suggested
Alternate

-

MC2112
MC2162
MC2012
MC2062

MC2111
MC2161
MC2011
MC2061

MC2101
MC3l00
MC2151
MC3l00
MC2001
MC3DOO
MC2051
MC3DOO

-

-

MC3l07

-

MC3007

-

-

MC3l05
MC3l05
MC3005
MC3D05

-

-

MC3l 0.0
MC3100
MC3000
MC3000

-

-

H(;o

SUHL TTL DEVICE CROSS REFERENCE (cont)
Type
SG240
SG241
SG242
SG243
SG250
SG251
SG252
SG253
SG260
SG261
SG262
SG263
SG270
SG271
SG272
SG273
SG280
SG281
SG282
SG283
SG290
SG291
SG292
SG293
SG300
SG301
SG302
SG303
SG310
SG311
SG312
SG313
SG320
SG321
SG322
SG323
SG330
SG331
SG332
SG333
SG340
SG341
SG342
SG343
SG351
SG353
SG370
SG371
SG372
SG373
SG380
SG381
SG382
SG383
SM10
SM11
SM12
SM13
SM20
SM21
SM22
SM23
SM30
SM31

Function
Dual 4-lnput NAND Gate
Dual 4-lnput NAND Gate
Dual 4-lnput NAND Gate
Dual 4-lnput NAND Gate
Expandable 4-Wide 2-2-2-3 Input AOI Gate
Expandable 4-Wide 2-2-2-3 Input AOI Gate
Expandable 4-Wide 2-2-2-3 Input AOI Gate
Expandable4-Wide2-2-2-3InputAOI Gate
8-lnput NAND Gate
8-lnput NAND Gate
8-lnput NAND Gate
8-lnput NAND Gate
Dual 4-lnput Expander for AOI Gates
Dual 4-lnput Expander for AOI Gates
Dual4-lnput Expander for AOI Gates
Dual 4-lnput Expander for AOI Gates
Dual4-lnput AND Gate
Dual4-lnput AND Gate
Dual4-lnput AND Gate
Dual4-lnput AND Gate
Dual 2-Wide 2-3 Input OR Expander
Dual 2-Wide 2-3 Input OR Expander
Dual 2-Wide 2-3 Input OR Expander
Dual 2-Wide 2-3 Input OR Expander
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable 3-Wide 3-lnput AOI Gate
Expandable Dual2-Wide 2-lnput AOI Gate
Expandable Dual 2-Wide 2-lnput AOI Gate
Expandable Dual 2-Wide 2-lnput AOI Gate
Expandable Dual 2-Wide 2-lnput AOI Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAN D Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NOR Gate
Quad 2-lnput Lamp Driver
Quad 2-lnput Lamp Driver
Hex Inverter
Hex Inverter
Hex Inverter
H ex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Full Adder
Full Adder
Full Adder
Full Adder
Dependent Carry Fast Adder
Dependent Carry Fast Adder
Dependent Carry Fast Adder
Dependent Carry Fast Adder
Independent Carry Fast Adder
Independent Carry Fast Adder

Direct
Replacement
MC2103
MC2153
MC2003
MC2053
MC2104
MC2154
MC2004
MC2054
MC2105
MC2155
MC2005
MC2055
MC2106
MC2156
MC2006
MC2056
MC527
MC577
MC427
MC477
MC528
MC578
MC428
MC478
MC2112
MC2162
MC2012
MC2062
MC2113
MC2163
MC2013
MC2063
MC2107
MC2157
MC2007
MC2057

-

-

MC2165
MC2065
MC529
MC579
MC429
MC479
MC2116
MC2166
MC2016
MC2066
MC4326
MC4327
MC4026
MC4027
MC4328
MC4329
MC4028
MC4029
MC4330
MC4331

Suggested
Alternate
MC3110
MC3110
MC3010
MC3010
MC5453
MC5453
MC7453
MC7453
MC3115
MC3115
MC3015
MC3015
MC3130
MC3130
MC3030
MC3030

-

-

-

MC3120
MC3120
MC3020
MC3020
MC3105
MC3105
MC3005
MC3005
MC3102
MC3102
MC3002
MC3002
MC3102
MC3102
MC3002
MC3002

MC5404
MC5404
MC7404
MC7404
MC3108
MC3108
MC3008
MC3008
MC5480
MC5480
MC7480
MC7480

-

-

SUHL TTL DEVICE CROSS REFERENCE (cont)
Type

Function

Direct
Replacement

Suggested
Alternate

-

SM32
SM33
SM41
SM43
SM61
SM63
SM71
SM73
SM81
SM82
SM83
SM90
SM91
SM92
SM93
SM111

Independent Carry Fast Adder
Independent Carry Fast Adder
Carry Decoder
Carry Decoder
Quad Latch (Open Collector)
Quad Latch (Open Collector)
Quad Latch
Quad Latch
16-Bit Scratch Pad Memory
16-Bit Scratch Pad Memory
16-Bit Scratch Pad Memory
Decade Counter
Decade Counter
Decade Counter
Decade Counter
4-Bit Shift Register

MC4030
MC4031
MC4332
MC4032
MC4335
MC4035
MC4337
MC4037
MC4304
MC4304
MC4004
MC5090"
MC5091"
MC5092"
MC5093"
MC5111"

SM113

4-Bit Shift Register

MC5113"

SM121
SM123
SM131
SM133
SM141
SM143
SM151
SM153
SM163
SM173
SM181
SM183
SM191
SM193

8-Bit Parity Tree
8-Bit Parity Tree
4-Bit Comparator
4-Bit Comparator
Programmable Binary Divider
Programmable Binary Divider
Programmable Decade Divider
Pr09rammable Decade Divider
Binary Counter
Decade Counter
Binary Up/Down Counter
Binary Up/Down Counter
Decade Up/Down Counter
Decade Up/Down Counter

MC5121' •
MC5123"
MC5131"
MC5133"
MC5141' •
MC5143"
MC5151"
MC5153"
MC5163"
MC5173"
MC5181 ••
MC5183' •
MC5191' •
MC5193' •

SM203

BCD-to-Seven Se9ment Decoder

SM211
SM213
SM221
SM223

Dual 4-Bit Multiplexer
Dual 4-Bit Multiplexer
Demultiplexer
Demultiplexer

• To be introduced
• * Available on special order only

MC4300
MC4000
MC4302
MC4002

-

-

-

-

MC5490
MC5490
MC7490
MC7490
MC4312,
MC5495
MC4012,
MC7495
MC4308
MC4008
MC4322
MC4022
MC4318
MC4018
MC4316
MC4016
MC7493
MC7490
MC54193'
MC74193'
MC54192'
MC74192' ,
MC8306
MC8307* ,
MC7448,
MC4039

-

PACKAGING INFORMATION

The packaging used for each device type is indicated
on the individual data sheet unless packaging is the
same for all devices in a given Me-number series. In
this case, the packaging description is in the General
Information section for that series.

F SUFFIX
CERAMIC PACKAGE
CASE 607
TO-86

Package type is denoted by a suffix to the part
number as follows:

lead 1 identified by color dot or by elbow on lead.

To convert inches to millim8tars multiply by 25.4
AIiJEDECdimensionsand notes apply

Description
Ceramic Flat
Ceramic Dual In-Line
Plastic Dual In-Line

Suffix
F
L

P

FSUFFIX
CERAMIC PACKAGE
CASE 609
TO-8S
0.013
[iIT7

~

PSUFFIX
PLASTIC PACKAGE
CASE 605
TO-116

'I

1

0.350

T

a.050T.P.

If

SEA.TING

a~~~
OO~I~ l--L:!~
j

MAX

L

0090

r

.11
=c
!j

~

1__

=

1°.150_1

0.150,°.100 __

[400

0]00

0.003
O]ijl

E3

I

o:m

~

rn

0.008

Ii]'Iii

I

I'

0500

[OOQ

lead 1 identified by color dot or by elbow on ltad.
To convert inches to millimeters multiply by 25.4

Four insulating ~nd-otfs ara provided
To. convert jnchas to millimeters multiply by 25.4

AtlJE~EC.dimBnsionsandnol1tsap~ly

All JEDEC dimensions and notes apply

Devices formerly using Case 609 are now being manufactured In Case 607. Either package may be shipped during

the transition.

L
0160

rno

:M·

,--

o~L~ ~SEAT1NGPlANE
~

L o.ld L
T.P.

LSUFFIX
CERAMIC PACKAGE
CASE 620

1----0.740 - - - I

ii

"I..

~~

PSUFFIX
PLASTIC PACKAGE
CASE 612

-01lO8(j)1
DG12

0.021

-Dimension is to lead cenlMline when formed parallel.
CD 4 insuJating stand·offs are providad.
To convert inches 10 millimeteR multiply by 25.4

--l

7'
TVP

~.
=ro:'""\

o;rs

rns

rI

0.090

o:m

0.008

L r ILo.n5
o:m

=

Y

0010150

0015

if.n2O

SEATING PLANE

(i)ThiJdimansion is meIIllrad from dta lead canters
.Ithisaatingpj... withlaadsvartical.

(1) Laad 1 idantifiad by color dot. notch in 1II8d,
ornQtchin,.ramic.
To convert inches to mitlimetarsmultiply by 25.4

'4

¥

if!

PACKAGING INFORMATION (continued)
LSUFFIX
CERAMIC PACKAGE
CASE 623

TO-116

I
"U
I

11

~\-.I~

0.500
0.540

"'\t(..~"'(pr..
13

I-UDDD

LSUFFIX
CERAMIC PACKAGE
CASE 632

t~~~

0160

SEATING

~~FP~"A_N_E

________

~

~Ti I
J i t;&m~
~
oooa--\\-

-l

I-~:n~

-ll--0.016

0.020

0.0301!.!!5
0.135

0.010

"i

15'

Dim

To convert inches to miltiml1lK1 multiply bv 25.4.
AlIJCDEC10-116 dimensions and notesapplv.

To convert inches 10 miillmetersmulliply by25.4
"Dimension is 10 lead centerline when formed parallel.

PSUFFIX
PLASTIC PACKAGE
CASE 648

LSUFFIX
CERAMIC PACKAGE
CASE 638

a::I::I~~

~O.815=1

~:::~:::d

~0.'05·""""'''''1

:f

m;----I
0.400

0.190

0.015

[""I
J
°f'~?-)IJ~l\I-\I-\I-~-\I-:'T
o·;;f
O.O~
U U lUI U U U U U

-

0.100 I I
T,P. -l----l

0.0'5

[lJ05

J!-0.015

(i]2(j

0.085

&Wo

0.012·~
I-O.300~
REF

m'~ "==t-

~:~ll ~

~7~

I-L

-l~55 o.a;-fI--ITJo
nL~~1--

0.100~

To convert inches to millimelers multiply by 25.4
"Dimension is to lead cllnterljml when formaci parallel.

1L015
0.010

T.P.

o:rn

To conven inches to millimeters multiply by 25.4
*Dimension is to IlIBd centerlina whan formed parallel.

PSUFFIX
PLASTIC PACKAGE
CASE 649

I O(\COO

0.240

1.240
1.260---------1

L~--.l

0.003

-,-

---r
0.030

li."OO5

[(!7D

2'

1
-(i)-

~ L~

0040

11

FSUFFIX
CERAMIC PACKAGE
CASE 651
0155

~-i

=,J-1H~~~:.a

0.015_11-- 0.1851
0.020
0.205~: g~

---I/-- O.ooa

"Dimension to lead centerline when formed parallel.
To convart inches to millimeU!rsmulliply by 25.4

iiJiT2

lead 1 identified bV color dot or by elbow on lead.
Top Covar mada of silastic matarial.
To convert inches to millimelers multiply by 25.4

INTEGRATED CIRCUITS
The MTTL complex functions are designed for digital applications
in the medium to high-speed range.
These MTTL devices provide significant reduction in package count
and increased logic per function over devices in the basic MTTL and
MDTL families.

--PSUFFIX

PSUFFIX

PLASTIC PACKAGE
CASE 605
TO-tt6

LSUFFIX

PLASTIC PACKAGE
CASE 6t2

CERAMIC PACKAGE
CASE 620

F SUFFIX

F SUFFIX

CERAMIC PACKAGE
CASE 607.
T0-86

CERAMIC PACKAGE
CASE 609.
TO·a5

~

LSUFFIX

_

CERAMIC PACKAGE
CASE 632
TO·116

FUNCTIONS AND CHARACTERISTICS

(Vee

L SUFFIX

PSUFFIX

CERAMIC PACKAGE
CASE 623

PLASTIC PACKAGE
CASE 649

= 5.0 V, TA = 2S 0 e)

All devices shown can be used with all MTTL and MOTL device.; however, the loading factors Shown reflect use with

other devices in the same

Me number series unless otherwise noted

Tvpe

Function
Dual 4-Channel Data Selector



5

165
10

30

160

10/55#

105

15/12#
15/12#

165
165

35

390

S,S = 10

632

Gated Full Adder

MC5480L

2-8it Full Adder

MC15482F,L

607,632

2-Bit Full Adder

MC25482F,L

607,632

4-BIt Binary Full Adder

MC5483L

620

MC5484L

620

MC7480L,P

632,605

Caut = 5
A*,B*"'3

MC 17482F ,L,P

607,632,605

MC27482F ,L,P

607,632,605

10
10

MC7483L,P

620,612

S'" 10
Cout = 5

IOL=40mA
f - - - - - - f - - - + - - - - - - I - - - - - - l } Open Collector
MC7484L,P
620,612
10L -20mA

16-Bit Scratch Pad Memory Cell
With Gated Inputs

Decade Counter

MC5490F,L

607,632

MC7490F ,L,P

B-Sit Shift Register

MC5491AL

632

MC7491AL,P

632,605

Divide-by- Twelve Counter

MC5492F,L

607,632

MC7492F ,L,P

607,632,605--

4-8it Binary Counter
4-BitShift Register

MC5493L

632

• MC5494l

620

4-Bit Shift Register

MC5495F,L

607,632

5-8it Shift Register

MC5496L

Monostable Multivibrator

MC54121F,L

BCD to One-of-Ten Decoder/Driver

MC54145L

620

16-Channel Data Selector

-MC54150L

a-Channel Data Selector

·MC54151L

623
620

620
607,632

MC7493L,P
~MC7494P

MC7495F ,L,P
MC7496L,P
MC7412IF,L,P
MC74145L,P
-MC74150P
-MC74151P

607,632,605

}

Write Mode: 25
Sense Mode: 15

20/bit

10
10
10
10

632,605

607,632,605

25

175

10

25
25

250
240

10

t o d+,BtoQ=35
50 max

90
215

8.5 to 35
8.5 to 35

200
145
225

620,612
607,632,605

20/bit

160
175
160
160

25
60

612

250

620,612

649
612

Quad Exclusive OR Gate

MC8241F,L

607,632

MC7241F,L,P

607,632,605

10

10

Quad E)(clusive NOR Gate
(Open Collector)

MC8242F,L

607,632

MC7242F,L,P

607,632,605

10

18

170

Universal 4"Bit Shift Register

MC9300L

10

25
22

300
125

8,0 to 28

110

620

MC8300L,P

620,612

BCD-to-Decimal Decoder

MC9301 L

620

MC8301 L,P

620,612

Dual Full Adder

MC9304L

620

MC8304L,P

620,612

Sl,52=10
51, S2."" 9

Dual 4·Bit Latch

MC8308P

649

Dual 4-Channel Data Selector

MC9309L

620

MCB309L,P

620,612

Presettable Oecade Counter

MC9310L

620

MC8310L,P

620,612

MC8311P

One-of-16 Decoder
8-Channel Data Selector

MC9312L

620

MCB312L,P

620,612

MC9316l

620

MC8316L,P

620,612

DuaI8-~it

MC9328L

620

MC8328L,P

620,612

325

9_0 to 24

150

Z,W= 9

14 to 35

649

Presettable4-Bit Binarv Counter

EtoQ"'25

Z,W = 10

E to Q- 26 max

10

z ..

20/10t

Z""

18/91

9.0 to 24

300
175
135

14 to 35

300

a = 22 (tpd_)
~ to~~t3g+)

250

Cto
Shift Register

Retriggerable Monostable Multivibrator

G) F

MC960lF ,L

607,632

MC8601F ,L,P

607,632,605

6

MC9601 "" 6
MCS601 =

a

sUffix denotes ceramic flat package, L suffix denotes.ceramic dual in-line package, P suffix denotes plastic dual in-line package_

-*MC4300 Series/MC4000 Seri.s; loading specified fot use with- MTTL I devices.
#Add delay/Carry delay

tHigh/Low

-To be announced

25

LOGIC DIAGRAMS

Numbers at ends of pin terminals represent pin numbers. Numbers in parenthesis indicate loading. Loading

factors reflect use with other devices in the same

MC~number

series unless otherwise noted.

SHIFT R E G I S T E R S - - - - - - - - - - - - - - - - - - - .
MC4012
4-Bit Shift Register

TRUTH TABLE
Synchranous Inputs

9 (10)

(1) 10
(5)

MC5491A/MC7491A
8·Bit Shift Register

A

5

3

e

I

a

0,

ooo

, ,
,

::»-I-.qe

9

t n+8

B
0

I ',,

,

0

4 (10)

8

(1)

o
(1)

(1) 11
(1)

'n

13 (10)

6 (10)

(1) 13

(1)

o

s

1

(1) 12

(l)All
2(10)

a

R

(1) B 12

'Vcc=Pin

14 (10)

5

Gnd = Pin 10

Vee

~ Pin 14
Gnd = Pin 7

tpd = 25 ns typ

tpd "" 22 os typ/bit

Po ~ 175 mW typ/pkg
f ~ 18 MHz typ

Po ~ 180 mW typ/pkg

MC5494/MC7494
4·Bit Shift Register

MC5495/MC7495
4·8it Shift Register

13 (10)

(1) 1

6

MC5496/MC7496
5-Bit Shift Register

15

9

(2) 6
(1) 9

2

8

12 (10)

3

(1) 2

4

o

11

9

11 (10)

(1)3

VCC=Pin 5
Gnd = Pin 12

16

6

11

16

10

10(10)

(1)5

14

13

4

(1) 4

13

14

2

(1) 8

3

15

Vee
Gnd

Clock

10

= Pin
=

Pin

14
7

Vee = Pin 5
Gnd "" Pin 12

80-----'
tpd. Clock to

Q =

tpd
Po
f

25 ns typ

Po ~ 175 mW typ/pkg
t,-og ~ 10 MHz

=

25 ns typ

~

250 mW typ/pkg

~

31 MHz typ

MC8328/MC9328
Dual 8·Bit Shift Register

MC8300IMC9300
Universal 4·Bit Shift Register

(1)

1

(1)

2

15 (6)

(1)

3

(2.3)

9

(1)

4

(1)

5

(1)

6

(1)

7

14 (6)

13 (6)

o

(1)
(3)

(4) 10

--< E

~"I

01 --014

4-Blt

02 --012

Binary

(1) 50--A

10--A

03 --011

03

6 11

e[---<>5

7-segment Character Generator
Vee = Pin 16
Gnd = Pin 8

a

fl-;-Ib

d[---<>4
e '--013

SEGMENT
IDENTI FICATION

.\-\e

f L-014

150-- C
100-- 0

0

g--02

h

h--03
Po - 240 mW typ/pkg

1
2

lI,b,e,d,e,f
b,'
.,b,d,a,g

3

.,b,c,d,g

o
o
o
o

b,c,f.g
I,e,d,f,g

o
o

0

d

4
5

•,

c.d,a,f.g

·· ,

•• b,c
8,b,c,d,.,f.8

a.b.c,f.g

NONE

h (Ext.)

NONE
NONE
NONE

o
o
1
1
1
1
1
1

o•

b

,

d

•

0

0

0

0

0

0

0 0

0

0
1
1

1
0
1

1

o
o

0
1

1
0

1
0

0

0

0

,

1 0
1
1 1
0
0
0
1 1
1 1
1 1
1
1 1
1 1

o
o
o

1
0

1
1

0 0

0
0
1
1
1
1

o
o
o
o

o

0

1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1

1

1
1

o

o

0

o , a

o
, , o,

1

,

OUTPUT

INPUT

SEGMENTS

DIGIT ILLUMINATED 3 2 1

1

o
o
o

,

0
0
0
1
1
1
1
1
1

1
0
1

,

1
1
1
1
1

1
0
1
1
1
1
1
1
1

1
1
1

o ,

o
a o
0 o
o
0

1
0

1
1
1
1
1 1
0 1
1

~

0
1
1 1
1 0
1 1
1 1
1 1

,
,

0

1
1
1

(continued)

LOGIC DIAGRAMS (continued)

DECODERS ( c o n t i n u e d ) - - - - - - - - - - - - - - - - - - - - - - - . . . ,
MC1441A
BCD-to-Decimal Decoder and
High-Level Driver

MC5442/MC7442
BCD-to-Decimal Decoder

(1) 15

(10)

MC5443/MC7443
Excess Three-to-Decimal Decoder

(1) 3

16

8
(1) 6

(1) 14

MC5444/MC7444
Excess Three Grav-to-Decimal Decoder

15

9

Vee -

Pin 16
Gnd = Pin 8

13

(1) 13

14
(1) 7

10

2

(1) 4

MC5442/MC7442

aco

Vee = Pin 5
Gnd = Pin 12
INPUT

0

C

a

0
0
0
0
0

0
0
0
0

0
0

1
1
1
1
0
0

0

0

0
0
1
1

1
1
0

1
1
0
0

A 9
0 1
1

0
1

,
0

0

1

0
1

1
1
1
1
1
1
1
1
0

a
1
1
1
1
1
1
1
1
0
1

OUTPUT
7 6 5 4 3 2
1
1
1
1
1

,

1
1
1
1
1
1

1

0

0

1
1
1

1
1

1
1
1
1
1
0

1
1
1
1

1
1
1
1

1
1
1

1
1

0
1
1
1
1
1
1
1

0
1
1
1
1
1
1

0

1
1
1
1
1

0

INPUT
C

0

0

0

0
0

0
0
0

0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

-Po - 105 mW typ/pkg

MC5445/MC7445
MC54145/MC74145
BCD to 1-01-10 Decoder/Driver

,

,,
••• , ~,
,, •• ~•
,
, ,, ••
,
0

1 0
1 0
0 1

a

1
0

0

1

1

0

1

1
1

1

0
1

1

1

A
0

0

0

0

,
,

,,
,

0

,,

,

a

0

1

0

1

0

1
0

1
1
0

0
1

0

0

1

0
0

1

,,
,

0

1

•• ,, •
,, , , ,,
•
•• • • •
,
,

,

0

1

,

0

0

1
0

,

1
1

1

1

0

0

0

1

1
1

0

0

1

0
0

1

15

1

16

Po - 265 mW typ/pkg

4

(10)

5

(10)

6

(10)

7

(10)

9

(10)

1

1
1

1

1
1

1

1

1

0

1

1

1
1
1

1
1

1
1
1

1

1

1

1
1
1
1
1

0
1
1
1
1
1
1
1

1

1

1
0

1
0

1
1
0

1

1

1

1
1

1 '1
1 1

1
1
1
1

1
1

1

1

1

1
1
1
1
1
1

0

,,

0

1
1
1

,

,,
,
1

,
,
1

,

1

(1) 7

13

(1) 1

12

(1) 2

11

(1)£

10

(1) 3

9

(1) 5

15

(2.6/5) 4

14

Gnd "" Pin 8

14

1

0

0

2
3

1

"

0
0

0
0

BCD-to-8even Segment Decoder/Drivers

= Pin

1

0

MC5446/MC7446
MC5447/MC7447
MC5448/MC7448

Vee

1
1

0

1

1

1

,,
•,,

0
0
0
0

1

.

0

0

(10)

ALL TYPES
DECIMAL
OUTPUT
7 6 5 4 3 2

a

9

0
0

1

1

1

3
4

,, , ,,, , , , ,, , ,
, , , , , , , ,, ,
,
,,,,
,, ,
,,, , ,, •, •, , , ,
,, ••
•,
, ,, ,
•• • •, ,,, , , ,,, , , ,
, , , ,, ,, ,, ,, ,
• ,
,

,,, ,

0

0
0

,
1

a

0

0

0

MC5444/MC7444
EXCESS3GRAY
INPUT
A
C

0
0

,

0
0

0
0

(10)

11 (10)

(1) 12

MCfi443/MC7443
eXCESS 3
INPUT
C
A

0
0

2

10 (10)

tpd, 2 Logic Levels = 22 ns tvp
3 Logic Levels = 23 ns typ
Po - 140 mW typ/pkg

11

~

5
MC5446/MC7446

6

ALL TYPES
DIGIT
DR
FUNCTION LT RBI 0 C B A BI/RBO
1
1
o0 0 0
1
X o 0 0 1
1
2
X • 0 1
X •• 1 1
3
4
X o 1 0 0
1
x o 1 0 1
1

7

13

•

9
10
11

12

••
•
7

I.
I."

Vee == Pin 16
Gnd == Pin 8

8

11

INPUT

OUTPUT

0

C

a

A 9

a

7

6 6 4 3 2

0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1

0
1
0
1

0
0

0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1

1
1
1
1
1
1

0
0
0

1
1
1
1
1
1
1
1

0

0
0
0
1
1
1
1

1
1

0

0
0

0

1
1
1
1
1
1
1
1
1

1

0

1
1
0

0

1
1

0

1
1

1
1

0

1
1

0

1
1
1
1

1
1
1
1
1
0

1
1
1
1
1
1

1
1
1
1
1
1
1

1
1

1
1

0

1
1
1
1
0
1
1
1
1
1
1
1
1
1

,
, ,,, ,,, , , , ,
, ,
1

0

1
1

0

1

1

1

1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0

1
1
1
1
1
1
1

,
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

13
14,

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

,,
• ,

,,
,
,,
,
1
1
1

,
,
1
1
1
1

X
X
X
X
X
X
X
X
X
X

,, ,

o ,
o , ,

1 0 0

,
•, ,
,,

,•

81

X

X

1
0

0

o

X

X X X

1
1

1

1 0 1
1 • 1
1 1 0 ()
1 1 0 ,
11
1 11 1
X X X X

RBI

LT

0

1 0 0 0

0 0 0
X

1

1
1
0

•
1

MC5447/MC7447
OUTPUT
b
d
f 9

MC5448/MC7448
OUTPUT
b
d
f

·• •• •• • ·• • · , ·
,

1
0

1

1

1
1
1

0

0
0

1

1
1

, ,,, 9
•, ,, •, •, , •• ••
, , •, • •,
,
,
, , ,
1

1

0

• • • ••, •, • ••
•, ,, ,, , •,
o •
• •• • • • • •• • • • • • •
• • • •, • •• •
, ,,
,,
,
•
•
•
•
•
,
o
,,
, , • o, ••
1

0

0

0

1

0

0
0
0
0

1
1
0

0
1
0
1

1
1
1
1
0

1
1
1
0

0

1
1
1
0
1
1
1
0

1

1

0

0

0
1
0
1

1
0
0
1
1

0

0
0

1

1
1
1
0
1
1

0

1
1
0
0
0
1
1
1
0

1

0
0
0
1
1
1
0

1

0

1
0

0
0

1

1
1
1

0
1
0
0
0

·
0
0
0

0
1

1
1
1

0
0

1
0
1

0

1

1

1
1

1

0

0
0

0
0

0
1
0

0
1

1
1
0
1
1

1
1
1

0
0
1

1
1
1
1
1
0
1
1
1
1
1

1

1

X.: Don t care

SEGMENTS ILLUMINATED

SEGMENT
IDENTIFICATION

tpd == 50 ns max
Po - 215 mW typ/pkg

. . . . . .-----.. . . . .-P------"'"-

"~,,---,-----------...,..,

LOGIC DIAGRAMS (continued)

DECODERS ( c o n t i n u e d ) - - - - - - - - - - - - - - - - - - - - - - - - ,
MC5449/MC7449
BCD-to-5even Segment Decoder/Driver
(1) 5

DIGIT
INPUT
OR
FUNCTION DeB A BI

11

•

10

3

o

0 0
0
1
1
0
0
o , ,
o 1 1
1 0 0

o0
o0
o0
o ,
o 1

1

2

(1) 1

•,
•
•
I.
"

9

VCC - Pin 16
Gnd = Pin 8

8

(1) 2

6
(1)4

7

·

13

"15

.,

Po - 165 mW typ/pkg

1 0 0

1

1 0 1
1 1 0
1 1 0
11 1
111

0
1
•
1
0
1

to,

12
13

12

(2.6) 3

0
,
0
1
0
1
0
1
0

x x x )(

· ·

MC8301/MC9301
BCD-to-Decimal Decoder

OUTPUT
f
d

,

,, , , , , , , ••
o •
,, • •, •, •• •
•• •
•,,
•
,
,
1
1
1
1
1
1
1
1
1
1
1
1
1
1

b

0
1
1

1

1

1

1
1
1
1

1

0

1
1
1

1
1

1

1
0
1
1
0
1
0
1
1

0
1
0
1
0
1

1
1
1
0
1

1
1
1
1
1

1
1
1
1
1
1
1
0

• •• • • ••
• • •• • ••
•••
• •• •• •• •• •• •• •
0

1

1

1
1

1

1

1
1
1

(1) 15

12 (10)
11 (10)
(1) 14

(1)

E

(1) 19

Vee = Pin 24

B

(1) 21

C

(1) 20

02

3

(10)

03

4

(10)

04

5

(10)
(10)

7

(10)

07

8

(10)

08

9

(10)

06

A

(1) 22

(10)

05

Gnd - Pin 12

(1) 23

01

2

0

a9

10 (10)

0.10

11 (10)

a"

13 (10)

a'2

14 (10)

a'3

15 (10)

0.14

16 (10)

a'5

17 (10)

,,

1

0 0 0
0 0 t
0
1 0
1 1
0 1
1
1
1 1 0
1 1 1

1

1

·

•

•1
1
1
1

1
1
1
1

10 1
1
1 •
•
1
1
1 1

X,. Doo'tcare

·

tpd

(10)

4

(10)

5

(10)

6

(10)
(10)

Pin 16
Gnd::: Pin 8

,, ,
, ,, ,
,
,
,
o
,
o
,, , , ,, ,, ,, ,
o
o •
,
••
, ,,
o
, ,
••
,
,, ,,
• ••
,, ,"
o •
, ,, ,
o
"

X
X X X X
X X X X

(10)

3

Vcc -

INPUT
OUTPUT
EO ~ 0 C B A 1514131211 1098 7 6 5 4 3 2 1 0

x x x

9

2

MC8311
1-01-16 Decode,

(10)

00

10 (10)

1

~--------------------------------------x-.-O-O"-'-'·-~--------------------~(1)
(1) 18

13 (10)

1 1
1 1 1
1 1
1 1
1
11 1
11 1
111
11
11 ,
1 1 0
1 • 1
01 1
11 1
11 1
1
1
1
1

"
"
"

1 1
1
1 1 1 1 1 1 1
1
1
1 1
1 1 1 1
1 0
1 0 1
1 0 1 1
1
1 1 • , 1 1
1 • 1 1 1
o 1 1 1 1
• 1 1 1
1 1
1 1 1 1 1 1 1
1 1
1 1 1 1
1
1 1
1
1
1 1 1 1
1 1
1 1
1
1
1 1 1 1
1 11 1 1 1 1
1 1 1 1 1 1 1

INPUT

•

OUTPUT
6 5 4 3

•, ,

,0
,•
, ,
,
,
, ,, ,,,, ,,
,,
,
,,
,, ,
,,
,, ,,
,, ,,

C

0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

,

0
0
0
0

1
1
1
1

,,
,

0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0

9

1
1
1
1

1
1

1

, ,,
1
1
1

1
1
1
1
1
1

1
1
0

1
1
1
1
1
0
1

2

1
1
1
1
0
1
1

1
1
1
0

1
1
1
1

1
1
1
1
1
1
1

1

0

0
0

0

1

1

0

1
1
0

0

0

7

1
1
1

1
0
1
0
1

1
1
1
1

0

1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1

1
1
1

1

1
1
0
1
1
1
1
1
1
1

1
1
1
1

1

0

1
1

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1
1
1

tpd "" 22 ns typ
Po - 125 mW typ/pkg

MC54145/MC74145
BCD to 1-01-10 Decoder/Driver

(E to

0) - 26 ns typ
Po - 175 mW typ/pkg

See MC5445/MC7445

PARITY T R E E S - - - - - - - - - - - - - - - - - - MC4010
Dual 4-Bit Parity Tree

MC4008/MC4308
8-Bit Parity Trea
(2) 13
(2) 1
(2) 2
(2) 3
(2) 9
(2) 10

g::.

(2)1~

8 (10)

Vcc -

Pin 14
Gnd = Pin 7

(2) 11

(2) 12
(2)

4-----4

(2)

5-----/

) 0 - - - - - 6 (10)

8-1020309010011012013
6-405
whereX@Y=X·Y+X·Y

tpd - 16-30 ns typ
Po - 150 mW typ/pkg

(2)

5

(2)

9~

6 (10)
VCC - Pin 14

~~: ~~

Gnd-Pin
8 (10)

(2) 13

6-1@2@405
where X 0 Y

tpd

=

xe Y + X. y

= 9.5·22 ns typ

Po - 125 mW typ/pkg

7

LOGIC DIAGRAMS

(continued)

COUNTER-LATCH- D E C O D E R - - - - - - - - - - - - - - - - .
MC4050/MC4350

2

Monolithic Counter-Latch-Decoder

Erliibi8 0------,

High-Current
Drivers

10.

SEGMENT IDENTIFICATION

11 b

9

c

5

d

FUNCTION
Lamp Test
Lamp Blanking
Aaset

Decoder

4 e

C E

R

X
X
X

X
X

X
X

X

rnibii

P
PI

6

.....

7

Serial

3

Output

= Pin
= Pin

Vee
Gnd

16
8

S.qu.~.

Lamp
BI.nle. ing
P

~

~

Latch

.

P2
P3
P'
P.

P7
P8

PO
PtO
Pl1
P

0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0

,
,, ,

S
X

LT

X

0
0
0
0
0
0
0
0
0

I
I

,,
I
I
I
I

,
I
I

0

•
0
0
0
0
0

LB
X

SOUl

0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0

0
0
0

-

I

0
0

any number of pul_ may be applied
P n .. ,,'pul_on the Clock input

fTog ~ 35 MHz typ

Po

f

."
2
3
4

,

I

450 mW typ/pkg

., , ,, , .
OUTPUT

INPUT

7-Segment

Decade
Counter

b

0

0

0

•

I

I

I

I
I

0
0
0

d

0

0

0

I

I
I

I
I

f

0

,, ,, ,,
,, ,
, , ,,,
,,
,o,
o
,
,
,,

0
0
I

0
0
0
0
0
0
I

0
0
0
0
I
I

0
0
0
0
0
0

0

0
0
0
0
0
0
0
0
0
0

I

0
0

0

0
0

I

I

0
0
0

I

0
0
0

0

I
I

1

I
I

0
0
I

0
0

0
0

Q
I

I

,.....,-3.0 V
....J '-OV

X - Don't care

MC4051

Monolithic Counter-Latch-Decoder

2

ertabi8 0------,

High-Current
Drivers

Clock
1

16 Vee

lOa

SEGMENT IDENTIFICATION

11 b
9

c

INPUT
C

E

R

S

.

X
X
X.

X

X
X
I

FUNCTION

Latch

Counter

5

d

Lamp Telt
Lamp Blanking

Reset

rriibi'e

4

State

9

Serial
Output
~

Gnd

= Pin

Pin 16
8

fTd9;;: 35 MHz typ

Po

~

450 mW typ/pkg

. p.

f
2
3

S.qu••"

Vee

X
X

pt

e

6
7

X

P

P.,

.

:

.~

Latch

P2
'3
P'
P,

P1
P8
P.
P10
PIl
P

1
0

X

I
0
0

,
1

0
0
0

0
0

1
1

0

0

0
0
0
0
0

I
I
I
I

0
0
0
0
0
0
0

0

0
0

,
,
I
I

0

LB

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

-

0
0
0

0
0
0

X

0

SOUl

0

0

0

0
0

0

0
0
0
1
0
0
0
0

0
0
0
0
0
0
0

any number of pu'se. may be applied

~ n

. ., , •,
OUTPUT

,

LT

1

0
0
0
0

b

,

1
0
0
0

I

I

0
0
0

0
0
0
0
1
1

f

d

0
0
0

0
0
0
0
0
0
1

0
0
0

I

I

I
I

1
1

0

0
1

I

,
,, , , ,
,, , ,, ,
,

,,
,
,,

0
0

0

,,
,,
,,

0

I
I

0
I
I

0

0
I

I

I
I

0
I
1
1
I
I

0

0

0

0
1
0 0
0 0

0
0
0

0
0
0
I

1

I

I

0
0

,.....,-3.0 V
'-OV

pulses on tha Clock Input

....J

X'" Don"'cars

F

..

LOGIC DIAGRAMS

(continued)

COUNTERS---------------------------------------,
MC4016/MC4316

COUNT

MC40181MC4318

•
8
7
6
5
4

Programmable Modulo-N Hexadecimal Counter

(1)

4

(2)

6

(1)

5

OUTPUT
03 Q2 Q1 00
I
0
0
I
I
0
0
0
I
I
I
0
0
I
I
0
I
0
0
I
0
I
0
0
0
0
I
I
I
0
0
0
0
0
0
I
0
0
0
0

(2)

(2)

1

(8)

Gnd == Pin

I.

COUNT

8

2

3

13

(4)10

12

(3)

I
I

1

13

1
1
1

1
1
0
0

12
11
10

I

•

1
1
0
0
0
0
0
0
0
0

8

7
6
5

·

tpd, Clock to 03 = 50 ns typ
Clock to Buss::; 35 ns typ
Po = 250 mW typ/pkg

3
2
1
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

I

0

0
1
1
1
1
0
0
0
0

1

8 (10)

3

6 (10)

(3)10

OUTPUT
03 02 01 00

15

5 (10)

(1)12

MC4018/MC4318

Vee == Pin 16

2

(2) 13

(8)

15 (8)

(1)14
(2)

I

0

(1)11

(1)

3
2

(8)

9

MC4023
4-Bit Universal Countsr

MC40161MC431.

Programmable Modulo-N Decade Counter

(3)

1
0
1
0
1
0

4

(3) 11

9 (10)

=

I

Vce
Pin 14
Gnd == Pin 7

0
1
0
1
0
1
0
1
0

tpd == 16 ns typ/bit
Po = 200 mW typ/pkg
f = 30 MHz tvP

MC5490/MC7490
Decade Counter
(2)14

CO

QO

12 (10)

(4)

Cl

Ql

9

1

Q2

8

COUNT SEQUENCE TRUTH TABLE

RESET/COUNT TRUTH TABLE

(10)

RO

(10)

(1)

3

(1)

6

Vee ==

Pin 5
Gnd == Pin 10

02

01

00

1~J

0
0
1

0

x

x

X

X

1

X

0

X

0
1
0

X
X

0

X

0

X

0

COUNT

X

0

0

X

COUNT

0

2

Q3

1
1

1
1

)(

-

.oUTPUT

COUNT

OUTPUT

Pin 2 Pin 3 Pin 6 Pin 7

11 (10)
(1)

RS

~J

g

COUNT
COUNT

0
1
2
3
4
5
6
7
8

•

Don I care.

03

02

01

00

0
0
0
0
0
0
0
0
1
1

0
0
0
0

0
0

0

1
1

0

1

0
0
1

0
1
0

-

(2) 14
(4)

MC5492/MC7492

MC5493/MC7493

Divide-by-Twelve Counter

4-8it Binary Counter

1
0
1

OUTPUT
02
01

00

0----<\ CO

QO

12 (10)

(2) 14 0----<\ eo

00

12 (10)

el

Ql

11 (10)

(2)

01

9

(10)

Q2

9

(10)

02

8

(10)

8

(10)

1

Vee

== Pin 5
Gnd = Pin 10

10---...qCl

Vec = Pin 5
Gnd == Pin 10

(1)

6

(1)

2

(1)

7

(1)

3

11 (10)

COUNT Q3
0
1
2
3
4

OUTPUT
COUNT

Po

1
0
0

0
0

tpd == 20 ns typ/bit
Po = 160 mW typ/pkg

(1)

tpd

1
1
1

1
1

=

60 ns typ

= 160 mW typ/pkg

0
1
2
3
4

5
6
1
8

I.•
11

03
0
0

••
0
0
1
1
1
1
1
1

00 connect8d to C1

02
0
0

·
·
1
1

0
0
0
1
1

01
0
0
1
1
0
0
0
0
1

1

0
0

O.
0
1
0
1
0
1
0
1
0
1
0
1

,

6

tpd == 20 ns typ/bit
Po = 160 mW typ/pkg

7

8
8

I.
11
12
13

I.
16

0

0

0

• • •
•
0
0
0
0
0
0
1
1
1

0

0

1

0

1

0
1
0
1

1
1
1
1
1

1
1

1
0
0
0
0
1
1
1
1

1

I

1

0
0
1
1

0

•
0

1

•
•• •
•
1
1

1
1

1
1

1

00 conne<:ted to (;1

(continued I

LOGIC DIAGRAMS (continued)

COUNTERS ( c o n t i n u e d ) - - - - - - - - - - - - - - - - - - - - - - - - . . . ,
MCB310/MC9310
Presettable Decade Counter

MC8310/MC9310

COUNT

a3

,

0

2

(2/3)

3

(2/3)

4

(2/3)

5

(2/3)

6

0
0
0
0
0
0
0
0

2
3

·•

14 (6)

(1)
(2)

MCB316/MC9316

OUTPUT

OUTPUT

MCB316IMC9316
4-Bit Binary Counter

5

13 (6)

,,

7

••

Vee == Pin 16
Gnd = Pin 8

12 (6)

a,

a2

COUNT OJ

ao

,,
0

,, ,,

0
0
0
0

0
0

0

·•

0

,,
,,

0
0

0
0

0
0

3

,
,
,

0

,,

6

0

7

••

0

10
11
12
13

I.

(1)

11 (6)

(2)

15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

a2

a,

ao

, ,,
,
,,
,

0
0
'0
0

1
1
0
0
0
0

1
1
1
1

0
0

0

0
0
1
1
0
0
1
1

0

0

,
0

0
1

•
1

0
0

0

1
1

0

1

,

tpd ::: 14 to 35 ns typ

9

(2) 10

fTog == 28 MHz typ

15 (6)

= 300 mW typ/pkg

Po

MEMORIES AND MAGNETIC MEMORY DRIVERS--------...,
MC4042
Quad Predriver

MC4004, MC4005, MC4304, MC4305
16-Bit Scratch Pad Memory Cell
5

6

7

5

8
(1) Al
(4) B

3

Xl

2

S"I"

12

5"0"

11

X2
X3

14

X4

2
11

(1) A2

6

(1) A3

9

___t_<_-t--o 7 C2

,/++-----0 14 C4

(1) A413
13

90-------'

Vee

== Pin

4

Gnd

= Pin

10

Vee

= Pin 4
Gnd == Pin 10

Substrate

= Pin

tpd: Write Mode == 25 ns typ
Read Mode = 15 ns typ
Po

= 250

Gnd
10

3
tpd = 15 ns typ
Po = 120 mW typ/pkg

mW typ/pkg

MC4043

MC54B4/MC74B4
16-Bit Scratch Pad Memory Cell With Gated Inputs

Dual Line Selector

(I)AI2~14Cl
(2)

VCC2
Cl

B 5

8

6

7

8

9

C2

(1) A2 6

Gnd
10

Vee

=

Pin

4

4

Xl

3

X2

2

X3
X4

Gnd = Pin 10

Substrate = Pin

3

= Pin 1

Vee = Pin 5
Gnd

5"0"

= Pin

12

11

15"--'---""
tpd: Write Mo~e =;: 25,n5 typ
Read Mode = 15 ns typ

16

Gate 2 = Pin 7

10

tpd
Po

12

W"O"

Collectors of Output Transistors:
Gate 1

S"I"

=

20 ns typ

Po = 250 mW typ/pkg

11

= 70 mW typ/pkg

;a 4

LOGIC DIAGRAMS (continued)

ADDERS------------------------------------------,
MC4026/MC4326
MC4027/MC4327

MC4028/MC4328
MC4029/MC4329
Dependent-Carry Fast Adder

Full Adder

(2)

8

(2)

9

(1)

2

MC4030/MC4330
MC4031/MC4331
Independent·Carry F_st Adder

5

tpd

7

Po

6

(1) 13

Vee:::: Pin 4
Gnd::::o Pin 10

= 125

Cin

S

0

0

0
1

0
0
1
1

tpd

0
1
0
1

= (Add

••

0
1
0
0
1

= 13

(2) 13

Cn -l

Note 1

Note 2

S

Ebut

0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0

0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0

0
0
0
0

0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

ns typ

Po - 90 mW typ/pkg

0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
1
1
0
0
.1
1

,

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

Carry Decoder

(4)14
(4) 8
(4) 1
(1) 13

1
1

0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

Co",

Note 3

--

0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

••••
•
•••

0

0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1

--

;;

11

0
1
1
1

••
•-•
:•

1
1
1
1
1
1
1
1
1

1
1
1
1
1

MC5480/MC7480

G_ted Full Adder

(3) 7
(1) 9

(1)

8

(1)

9

5 (10)

(1) 11

(2) 3
(1) 2

(1) 12

(1) 6
(1) 5

(1)

2

(5)

3

6 (10)

(1) 13

Vec::::

Pin
God:::: Pin 14

(Input ~ 1.625)
(Output = 3)

= 4~O ns

typ/decoder
1.0 ns typ/pF at expander nodes

= 20 mW typ/pkg

Cin

•

A

Cout

S

S

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1

1

0
1
1
0
1
0
0
1

0
1
0

0
0

0
0
1
0
1
1
0

4 (5)

Vee::::; Pin 4
Gnd "" Pin 10

Po

0
1
1
1
1
1

MC432914029 Comment

MC4331 (4031
Cout

Notel. This column represantlil the AND function whose Inputs are pins 13 .nd 12, .nd is d.flned' by the
ellpression (An_1@Sn_11(Cn_21_
Note 2. This column rapresents the AND function whO$lllnp ... ts are pinl13, 14, and 1, and is defin.d by the
. .pression (An_1 G;) Bn-1 l\An_2@Sn_2ltCn_31.
Note3. 41- Don'tC.r•. Th. "Don't C.r." occurs for th. MC433O-31/4Q30-31 onlv, b.c....se tha Cn .nd tha@n
from .ny one previous stega entering a gi\len s ... bsequent .tage cannot be sim ... ltaneously at logle "1".

MC4032/MC4332

Atpd

4

CONDENSED TRUTH TABLE FOR THE Nth STAGE
Pin Numblrs
12,13 13,14,1
5
1
6
MC4330/4030 MC4328/4028

B

0

•

3
20-----'

A

0

7

Loads
Loads
Loads
Loads

0

0
0

0

I
I
I
I

11

0

C....
0
0
0
1

MTTL
MTTL
MTTL
MTTL

9

~

Delay) = 25 ns typ

tpd (Carry Delay)

6

(1) 14

8

0
0
0
0
0

OUTPUT

.. .
B
0
0

0
0
0
0
1
1
1
1

5

(1)

Output Loading Factor:
MC4328, MC4330 = 15
MC4329, MC4331 = 7
MC4028, MC4030 = 12
MC4029, MC4031 = 6

MC4326"" 15 MTTL I Loads
MC4327 = 7 MTTL I Loads
MC4026 == 12 MTTL I Loads
MC4027 "" 6 MTTL I Loads

A

9

(1) 11

mW typ/pkg

Output Loading Factor:

INPUT

8

(2)

(1) 12

Delay) = 25 ns typ

tpd (Carry Delay) = 13 ns typ

(1) 11
(1) 12

= (Add

(2)

(Input ~ 1.6251
(Output = 3)

tpd (Add Delay) :::: 55 ns typ
tpd (Carry Delay:::: 10 ns typ

A .. A*.AC, 8 - s* 8S C

whareA*"~
a*=~
2. Whan A* (or S*J is used" an
input, A1 and A2 {or 81 lind s21
must be conneeted to g'OI"Iod,
3. When A 1 and A2 (or S 1 and S21
are uaed u Inputs, A* lor sir)
must be open, or u,.d to perform
wired-OR logic.

Po ~ 105 mW typ/pkg

(continued)

LOGIC DIAGRAMS (continued)

ADDERS (continued)

--------------------------'""""1
MC8304/MC9304
Dual Full Adder

MC5483/MC7483
4-Bit Binary Adder

(4) 130-- Cin
(4) 100-- Al
(4) 110-- 61
(1)

8 0 - - A2

(1)

70-- 62

(4)

3 0 - - A3

(4)

4 0 - - 63

(1)

10-- A4

f------o 9

51

(4)

(10)

2

Al

52f---o6

(10)

53 r---0 2

(10)

(4)

3

61

(4)

4

Cin 1

Caut r---0'4 (5)

(1)1~:D
(4) 15

5
Gnd = Pin 12

INPUT

%

~
ein=1

When

C2=O

Who"
C2=1

X, X t% %~ ~ Vc: %%A

, ,
,
, ,

0
1
0

1
0
0
1

0

8.

0
0
0
0
1
1
1
1
0
0
0
0

Caut
1 ~5

(7)

52 f----lIecfor Outpud

MC5401F,L

607,632

MC7401 F,L,P

607,632,605

10

35

40

Quad 2-lnput NOR Gate

MC5402F,L

607,632

MC7402F,L,P

607,632,605

10

10

40

Quad 2-lnput NAND Gate
(With Open ColI"ctor)

MC5403L

605,632

10

35

40

Hex Inverter

MC5404F,L

607,632,605

10

13

60

-55 to + 125°C

Function

Case

632
607,632

MC7403L,P
MC7404F,L,P

Case

®

Loading
Factor
Each

Output

Hex loverter

MC5405L

632,605

10

35

60

Triple 3-lnput NAND Gate

MC5410F,L

607,632

MC7410F,L,P

607,632,605

10

10

30

Dual 4-lnput NAND Gate

MC5420F,L

607,632

MC7420F,L,P

607,632,605

10

10

20

Quad 2-lnput Interface
NAND Gate

MC54;!6L

632,605

10

17

40

a-Input NAND Gate

MC5430F,L

607,632

MC7430F,L,P

607,632,605

10

Dual 4-1 nput NAN 0 Buffer

MC5440F,L

607,63,

MC7440F,L,P

607,632,605

30

10
13

50

-

BCD-to-Decimal Decoder
and High-Level Driver

632

632

MC7405L,P

MC7426L,P

10

MC7441AL,P

620,612

-

-

105

BCD·to-Decimal Decoder

MC5442L

620

MC7442L,P

620,612

10

22/23#

140

Excess Three-to-Decimal Decoder

MC5443L

620

MC7443L,P

620,612

10

22/23#

140

Excess Three Gray-toDecimal Decoder

MC5444L

620

MC7444L,P

620,612

10.

22/23#

140

-

-'

(ll[l)l
(11 [121
(1) [13J

(5) 10

(1) (13) 13
(1) (14)

BUFFER----------

8 (12) (10)

(11 (14) 5
(11[619
(11
(1)

1

(1)

(1)

(6)

(1)

(7)

(1)

(8)

(1)

(9)

:~

5~

[7J 10
[81 12
[9J 13

(3) 13

(1)

(6)

2

(7)

3

(1)

(8)

4

(11

(9)

5

111 (13)

9

tpd'" 13 ns typ

Po = 50 mW typ!pkg

8 (10) (30)

MC5405/MC7405

Hex Inverter

Hex Inverter
(Open Collector),

1 - 1 > - 2 (14)(101

(11

l--{)o-2

1101

(11[ 3 J 3-{:>o-4 [ 2 ](10)

(1)

3--{)o-4

(101

I 5 - 1 > - 6 [6 ](101

(11

5--{)o-6

(10)

(11[ 7 J 9 - 1 > - S [ S Hl0)

(1)

9--{)o-S

(10)

(1l{ 9 J 11-{::>o-10[10](10)

(1)

11--{)o-10 (10)

(1)[13J 13-V-12[12J (10)

(1)

13--{)o-12 (10)

(11[ 5

1

(1)

(30)

MC5404/MC7404

(11[ 1)

MC5453/MC7453
Expandable 4-Wide 2·lnput
AND·OR·INVERT Gate

[5J

6 [2J

INVERTERS

tpd:: 13 ns typ
Po :: 28 mW typ!pkg

(1)

D
D

6(10)(10)

8 = (9·10) + (13.1)

(1)

2
4

8 (12) 1101

111 (14) 10
Emitter [11
Collector (2]

2=1

S = 113. 1) + 12.3) + 14·51 + 19·101 + IExpander.1

2=1

= 35 ns typ

tpd'" 13 ns typ

tpd

Po = 60 mW typ/pkg

Po = 60 mW tvp!pkg

tpd'" 13 ns typ
Po = 22 mW typ/pkg

MC5454JMC7454
4-Wide 2·lnput
AND·OR-INVERT Gate
111

EXPANDER---------~
MC54601MC7460
Dual 4-lnput Expander for
AND·OR·INVERT Gates

(3) 13

(11

(5)

1

(11

(6)

2

111

[7J

3

111

[S)

4

111

[9J

5

(11 [13J

9

[31 13
Collector
[51 1~---~12[2J
S [121 (101

[6J

2~---~ 11 [1]

171

3

[8J
[9J
[10J
[12J

(11 [14J 10

Emitter

Emitter

:~---~

10 [141

6~--~9

8

[13J

Collector

8 = (13 • 11 + (2 • 31 + (4 • 51 + (9 • 101
tpd'" 13 ns typ

5 (10)

(1)110-- AC
(1) 120-- Bl

S

•

0
0
I
I
I
I

---<>6 (10)

(1) 130-- B2
(1) 2 0 - - BC
(5)

0

Vee = Pin 7
Gnd = Pin 14

•

A

Caul

S

s

0
0
I
I
0
0
I
I

0
I
0
I
0
I
0
I

I
I
I
0
I
0
0
0

I
0
0
I
0
I
I
0

0
I
I
0
I
0
0
I

A*.AC.B=~

I. A-

3 0 - - Cin Cout f---<>4 (5)
A- S*

wh.r.A*"~

s* .. i"1Te2
10!

I"pvt, A1 and,A2 (or 81 and 82)

(Input = 1.625)
(Output = 3)

(Input = 1.625)
(Output

2. Whan A* (or Bot) 1$ used lU lin

!1

= 3)

muff' be connected to ground.
3. When

."d A2

~1

(or B, and 82)

ar. usad as (npun, A* (or 8*1
must be open, or u.ad to perform
wired-OR logic.

tpd (Add Oelay) ~ 55 ns typ
tpd (Carry Delay:: 10 ns typ
Po ~ 105 mW typ/pkg

MC15482/MC17482
MC25482/MC27482

.,

A'

.,

51

.,

0

0

0

0

0

0

I

0

0

0

I

0

0

0

I

0

I

0

0

I

I

0

0

0

I

0

0

t

0

0
I

2-Bit Full Adder

INPUT

AI

30--- Bl

f----<> 1 (10)
S2 f----<> 12 (10)
Ell 1 f----<> 7t (10)

(2) 130--- 82

(92 f---<>8t (10)

(2)

2 0 - - Al

(2) 140-- A2
(2)
(3)

•
•

Sl

50--- Cin :out f---<> 10 (10)

I

OUTPUT

Cin -1

Cin-O

•

C

C

52

SI

e" e,1

•

0

0

I

0

I

0

I

0

I

0

0

I

I

0

0

0

I

0

I

I

0

0

I

I

0

0

0

I

I

I
I

0
0

= ',5 ns

I

0

I

0

0

I

I

0

I

I

0

0

0

I

I

tpd (Carry Delay) = 12 os

I

I

I

0

0

0

I

I

0

I

0

0

0

0

I

0

I

0

I

I

0

0

I

I

0

0

1

1

1

0

0

1

1

1

0

1

0

I

1

I

0

0

1

I

1

tpd

Po

(Add Delay)
~

165 mW typ/pkg

Vee = Pin 4
Gnd = Pin 11

•
0

I

I

I

0

I

0

0

1

I

0

I

0

1

0

0

1

I

0

0

1

1

0

1

0

0

I

0

I

I

I

0

I

0

I

1

1

0

0

1

1

I

I

0

1

0

I

1

I

0

I

1

1

1

0

1

1

I

I

1

0

0

t Available only on MC25482/27482
MC5483/MC7483
4-Bit Binary Adder

OUTPUT

INPUT

% %
/{, %
Cin-,'

Cin"'O

(4) 13 c:>-- Cin
(4) 100-- Al
(4) 110-- Bl
(1)

80-- A2

(1)

70-- B2

(4)

30-- A3

(4)

40-- B3

(1)

10-- A4

(1) 160-- 84

51 f---<>9

(10)

82 f---o6

(10)
(10)

When

C2= 1

%%v.: %l% ~ Vc:
A3

53 f---o2

Wh.n

C2=O

Vee = Pin 5
Gnd = Pin 12

54 f---o15 (10)

0
I
I

I
I
I
I

0

0
0

0

I
I

0
0

0
0

I
I
I
I

I
I

tpd = 35 ns typ
Po ~ 390 mW tvp/pkg

8'

0
0

0

C out ---<>14 (6)

83

0
I
0
I
0
I
0
I

0
I
0
I

I

1
0

I
I

0
0
0
0

0

a

0
0
0
0
0
0
0
I
I
I
I
I
I
I
I

Co

S3

0
I
I

0
0
I
I

0
0
I
I

0
0
0

0
0

I
I
I
0
I
I

0

,
,

0
0
0
0
I
0

0
0

S3

, 0
, ,,

0
0

I

o·

0
0
0

,

0
I
I

I

I

0
0

0
0

0
0

0

I
I

0
0

I
I

0
0

0
.0

I

1

0

I

I

I

0

I
I
I

,,

~

Co

0
0
0
0

0
I
I
I
0
I
I
I
I
I
I
I

ir'put conditions at A 1, A2. B1, 82, and C,n ~rB.used to ~eter
mine oU'tputs S1 and S2, and th" value ofi'the i,nen.al carry, C2.
Ttle values.t C2. A3, 83, A4, .nd 84 are then ut,ed to dB,termin.
outputs 53, 54, and Cout-

LOGIC DIAGRAMS (continued)

COUNTERS---------------------------------------,
MC5490/MC7490

Decade Counter
(2) 1 4 0 - - - . q
(4)

co

10---<11 Cl

aD

12 (10)

al

(10)

9

a2

8

COUNT SEQUENCE TRUTH TABLE
RESET/COUNT TRUTH TABLE

RO

(10)

(1)
(1)

• •
.
X

2

X

Vee::: Pin 5

3

)(

Gnd ." Pin 10

6

X

0

OUTPUT
COUNT

OUTPUT

02

01

~t ~ I ~

11 (10)
(1)

A9

Pin 2 Pin 3 Pin 6 Pin 7 03
1
1
0
x
1
1
X
0
x
X
1
1
X
0
X
0
X
0
0
X

COUNT
COUNT
COUNT
COUNT

•

X

00

I

0

0
0

1
2
3

·••

1

1

••

Don'tc..re.

03

02

01

00

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1

0
0

0

1
1

0

1

1
1

0
0

0
0

0

-

1
1
1
1
1

00 <;onnillcted 10 C1

tpd

(1)

= 20 os tvp/bit

Po = 160 mW typ/pkg

MC5492/MC7492
Divide-by-Twelve Counter

(2) 14 o---~ CO
(4)

1

Cl

VCC = Pin

5

aD

12 (10)

(2)

al

11 (10)

(2)

a2

9

(10)

8

(10)

Gnd = Pin 10

(1)

MC5493/MC7493

4-Bit Binary Counter

14o---~CO

1

VCC
Gnd

6

(1)

(1)

2

(1)

3

Cl

= Pin

= Pin

5
10

aD

12 (10)

al

9

(10)

a2

8

(10)

11 (10)

OUTPUT

01

00

•, •• •• ••,
• • ,
• •• ,,, ••,
• • , ,
•• •,,, • ••,
, • ,
" ,, •,,
,. ,, ,, ,,

•,
•,
•,
•,
•,
•
•,

COUNT
OUTPUT
COUNT

03

1

= 60 ns typ

Po

= 160

0
0
0
0

2
3

·•••

mW typ/pkg

01
0

0

0
0

1
1

0

1
1

0

0

1

tpd :::: 20 ns typ/bit
Po = 160 mW typ/pkg

0

1

1

···
,. ·
2

0

0

,."•

02

3

00

• • •
,
•,,
•• ,
,, •• •,, •,
,, ,, • •,
•
-

0

tpd

02

03·

1

'2
13

0

14

ao connected to C1

0
0

·•,

aD connected to E1

MEMORIES----------------------------------------.
6

7

MC54841MC7484

8 9

16-Bit Scratch Pad Memory Cell With Gatad Inputs

4

XI

3

X2

2

X3
X4

S"I"

12

S"O"

11

tpd: Write Mode:::: 25 ns typ
Read Mode = 16 ns typ

W"O"

Po = 250 mW typ/pkg

15
16
10
11

Vee = Pin

5
Gnd = Pin 12

LOGIC DIAGRAMS (continued)

DECODERS--------------------------------------~
MC7441A
BCD-to-Decimal Decoder and
High-Lavel Driver

MC54421MC7442
BCD-to-Decimal Decoder

(1) 150-- A

c:io - - 0 1 (10)
--02

(10)

(1) 140-- B

02 - - 0 3
03 - - 0 4

(10)

--05

(10)

(1) 130--C

05 - - 0 6
Os - - 0 7

(10)
(10)

07 - - 0 9

(10)

ci1

MC5443/MC7443
Excess Th .....ta-Decim.1 Decoder

(1) 3 0 - - A

0.0 f--016

MC5444IMC7444
Excess Three Gr.v-to-Decimal Decoder

01 f--o 15

54

0.2 f--os
(1) S o - - B

03 f--09
04 f--o 13

Vee = Pin 16
Gnd = Pin S

05 f--o 14
(1) 70-- C

07 f--o 10

MC5442/MC7442

MC5443/MC7443
EXCESS J
INPUT

aco
INPUT

Vee = Pin 5
Gnd = Pin 12
INPUT

0

c a

OUTPUT
A 9 8 765432

0

0

0

0

0
0
0
0
0
0
0
1

0
0
0

0
1
1
0
0
1
1
0
0

,,
,

,

1
0
0

, ,,,
,,,
,

0
1
0

0
1
0
1

1
1
1
1

1
1
1

0

1

1
1
1
0
1

1
1
1
1

,

,
,,
1

0

, ,, ,, ,, ,1 0,
, , ,, ,,
, , , ,, ,, ,
, ,,
,
,, ,

1
1
1
1

0
1
1
1

1
1
1
1

0

0

1

0

0
1
1

0
1

1
1

1

1
1

0
1
1
1
1
1
1
1

1

1

1
1

1
1

Po = 105 mW typ/pkg

MC5445/MC7445
MC54145/MC74145
BCD to 1-of-10 Decoder/Driver
150-- A

(lo - - 0 1

140-- B

01 - - 0 2
02 - - 0 3
03 - - 0 4

130--C

04 - - 0 5
05 --OS
OS - - 0 7

0
0
0
0

0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1

,
1
1
1
0

,
1
1
1
1
1
1

7
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

,

1
1
1
1

o
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1

,
,

1

1
1
1
1
1
1
1

1
1

,

0

1
1
1
1
1
1
1
1
1
1
1
1

tpd = 50 ns max
Po = 215 mW typ/pkg

0
0
0
0

0
0

1

0
0
1

1
1

0

1
1
1

1

1

1
0

1
1

0
0

1

0
0
0

0

0

0

0

0

1

0

0

0
0

0
0

0
1

1
1

1
0
1
0

1
1
1
1
1
1
1
1
0

1
1
1

1
1

0

0

1
1

1

0

0

0
0
0

0

1
0

0
0

0

,, ,~
,,
,
, , ,
, ,
,

1
0

"',
,,
,,
,, ,
,
0
0
0
1

A

0

1

1
0
0
1
1
0
0

a

0
0
0
0
0

1

, ,

C

0

1

0

1
1
1

0
1
0
1
0

1

0
0

1
1

1
0
0
0

0

1
1
0
0
1

0

0
0

, ,

1

,

,

1
1
0
0
0
0
0

0

,
3

4
5
6
7
8
9
10
11

1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

"
I.
13

15
81
R81
LT

1
1
1
1
X

1
0

X

o
o
o
o
o

X
X

o
o

X
X
X

X o
X
X
X
X
X
X
X
X
X
0
X

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

1 0

1

1 1

0

1 1 1
1 0 0 0
1 0 0 1
1 0

1 0

1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1111
X X X X

o

0 0

0

X X X X

1
1
1
1
1
1
1
1
0
1

1
1
0
0
1
1

1
1

2
1

0

0

0

1
1

0

0

0

1
1
0

0

0
1

1
1

1

1
1

1

1
1
1

1
1
1

1

1
1

1

1
1

1

1
1

1
1
1

1

1
1
1

1

1

1

1

(1) 7 0 - - A

a f--o 13

(1) 1 0 - - B

bf--012

(1) 2 0 - - C

cf--oll

(l)So--o

df--ol0

(1)30-- LT
(1)50-- RSI

ef--09

f

f--o 15
(2.S/5) 4 0 - - BI/RBO 9 f--o 14

ALL TYPES

1

1 0
, ,, ,, ,, ,, , ,, ,,
1
,
,, , ,, , , ,, ,, ,,
, ,, , , ,, ,, ,, ,, ,,
,,,,,,
, : ,, ,, ,, ,,, , , ,,
,,, ,
,, , ,,
, , ,,, ,, ,, ,,
,
,
,,, ,
, ,

9 a 7 6 • 4 3
1 1 1 1 1 1 1

0
0

1
1
0
0
0
0
1

0
0

MC5446/MC7446
MC5447/MC7447
MC5448/MC7448
BCD-to-Seven Segment Decoder/Drivers

1
1
1
1
1
1
1
1
1
1
1
1

DECIMAL
OUTPUT

0

C

0

ALL TYPES

A

0

,

0
1

OUTPUT
6 5 4 3 2 1 0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0

a

A

DIGIT
OR

09 --011

8

a

,

FUNCTION L T RBI 0 C B A aI/ABO

Vee = Pin 16
Gnd = Pin S
INPUT
C a A 9
0 1
0
0
1 1
0
0
1
0 1
0
1
1 1
0
1 0
0 1
1 0
1 1
1
1
0 1
1
1 1
1
0 1
0
0
1 0
0
0
0
1
0 1
1 1
0
1
1
0
1 0
1 1
1 0
1
1
0 1
1 1
1
1

c

Po = 2S5 mW typ/pkg

OS - - 0 10

0

0

MC5444/MC7444
EXCESS 3 GRAY
INPUT

Vee = Pin 16
Gnd = Pin S

07 - - 0 9
120-- 0

09 f--oll (10)

(1) 120-- 0

Po = 140 mW typ/pkg

OS f--o 1
09 f--02

(1) 4 0 - - 0

Cia f--o 10(10)

tpd. 2 Logic Levels"" 22 ns typ
3 Logic Levels = 23 ns typ

06 f--oll

(10)

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1

MC5446/MC7446
MC5447/MC7447
OUTPUT
b , d , f
0 0 0 0 0
0 0 1 1 1
0 1 0 0 1
0 0 0 1
1 0
0 0
1 0 0
0
1 0 0 0 0
0 0 1 1 1
0 0 0 0 0
0 0 1 1 0
0 0 1
1 0 0 1 1
0 1 1 1 0
1 1 0 1 0
1 1 0 0 0
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
0 0 0 0 0

.
0
1
0
0

,

0
1
0
0
0
1
1

,

0
1
1
1
1
0

,,

,

,,

.

MC5448/MC7448

•
1
1

1

0

1
1
0

0
0

,

0
0
0
1

0
1
1
1
0
0
0
1
0
0
0

0

0
0
0
0
0
0

1
1
1
0

OUTPUT
b , d
f

,

1
1
1
1
1
0
0

1
1
1
0
0
1
0
0
0

0
0
1

0

1

1 1
1 0
0 1
1 1
1 0
1 1
1 1
1 0
1 1
1 0
0 1
1 1
0 0
0 1
0 1
0 0
0 0
0 0
1 1

1
0
1
0
0
0
1
0
1

1
0

•

1
1
1

0
0
1
1
1
1
1

0

0

1
1
1 0
0 0
0 1
0 1
1 1
0 0
0 0
0 0
1 1

1
1
1
1
1
1
1
0
0
0
1

0

0
0

X .. Oon'l care

SEGMENT
IDENTIFICATION

.
fl Ib
9

·1d Ie

SEGMENTS ILLUMINATED

-II-:hl'- 1
f:H!C!=I!U!'=!:=! !

1 I
11__
I: : 1 :110

1

2

8

9

10

3

I

I_IU

4

11 12

5

S

7

13 14 15

(continued)

LOGIC DIAGRAMS (continued)

1"""1DECODERS

(continued)
MC5449/MC7449
BCD-to-Seven Segment Decoder/Driver

DIGIT
INPUT
OR
FUNCTION DeB A 81

,•

.~11

(1) 5 0 - - A

b~ID

(1) 1 0 - - 8

c~9

Vee"" Pin 16
Gnd = Pin 8

d~8

(1) 2 0 - - C

e~6

(1) 4 0 - - 0

f~13'

(2,6) 3 0 - - 81

9

---<)

12

Q 0 Q 0

1 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

)( X X X

0

1

o

3
4
5

o 0
o 1
o 1
o 1
o ,

8

1 0 0 0
1 0 0 1

•,
I.•

o

0 0 1
0 ,
1
0
0
1
1

0
1
0
1
0
1

to,

0

11

1 0 ,

1

"

, 1 0 1
1 1 1 0

, 1 0 0

13
14

I.

8'

t,

x = Don'teare

·•

OUTPUT

,

•
••• •

· .·
·
•• ·• • ••
• • •• ·
·•• ·• ·• • • • ·•
1

b
1
1
1
1
1
0

1
1
1

1
1
1

1
1
1

•
••

1
1

1
1
1
1
1
1
1

f

d
1

•
1

1
1
0
1
1

•o 1
1 1

1

1

o

0

o •

0

1

1

1

1
1

•1

1

1
1
0

•
•1

1
1
0

0

1

1

1

0

0

o

1
1
1
1
1

1
1
1
1
1
1
1

PO"" 165 mW typ/pkg

SHIFT R E G I S T E R S - - - - - - - - - - - - - - - - - - - - - ,
MC5494/MC7494
4-Bit Shift Register

MC5491A/MC7491A
8-Bit Shift Register

13 (10)

(1) C

9

6

3
4

(I)A II

14 (ID)

(1) 812

9

11
13
14
16
15

Vcc=Pin 5
Gnd"" Pin 10

Clock

lD
8

TRUTH TABLE
Synchronous Inpu1S

A

"

tn+8

B

•I •

•
1
1

1
0
,

a

0

•
•,

1
01

·l'

Vee = Pin 5

tpd "" 25 ns typ
Po :::: 175 mW typ/pkg
f:::: 18 MHz.typ

Gnd "" Pin 12

tpd. Clock to Q = 25 tiS typ
= 175 mW typ/pkg
fTog = 10 MHz ~

Po

(continued)

LOGIC DIAGRAMS (continued)

SHIFT REGISTERS (continued) - - - - - - - - - - - - - - - - - - - - - ,
MC5496/MC7496
5·Bit Shift Register

MC5495/MC7495
4-Bit Shift Register

15
13 (10)

(1) 1

14

(2) 6
(1) 9

12 (10)
13

(1) 8
(1) 2
(1) 3

11 (10)

11

10 (10)

10

(1) 4
(1) 5

Vee = Pin 14
Gnd = Pin 7

tpd
Po

= 25 ns typ
= 250 mW typ/pkg

Vee

= Pin

5

Gnd

= Pin

12

tpd. Clock to' 04· "" 25 ns typ

Po -

240 mW typ/pkg
f Tog = 10 MHz

f-31MHztyp

MULTIVIBRATORS--------.
MC54121/MC74121

Monostable Multivibrator

Vee = Pin 14

Gnd:::: Pin

7

6

2k

(1) AI 3

1
(10)

to INPUT
A1

A2

1

1

0

X

X

0

0

X

X
1
1
X

0
1
1
0

0

X

X

0

0
1
1

X
1
1

•

0
1
1
0
0
1
1
0
0
1
1
0
0

tn+lINPUT
A2

A1
1
0
X
0
X
X
0
X
1
1
1
X
0

1
X
0
X
0
0
X
1
X
1
1
0
X

•

1
0
0
1
1
1
1
0
0
1
1
0
0

OUTPUT
Innibit
Inhibit
Inhibit
Trigpring

Ttigg.rin;
TrlltQtlring

T ri ltSl8 ri ng
",hlblt

Inh.blt
Inhibit
Inhibit
Inhibit
Inhibit

x - Oon tear.
~

t" .. Time period prior to input tr.",ition

tn. 1 '"

Q

(10)

(1) A2 4
(1) B 5 0 - - - - '

Time period following Input tunsition

tpd, B to Q :::: 35 ns typ
Po =90 mW tvp/pkg (50% duty cycle)

Q

INTEGRATED CIRCUITS
MC3000 Series (0 to +750 C)
MC3100 Series (-55 to +125 0 C)

MTTL III integrated circuits comprise a family of transistortransistor logic designed for general purpose digital applications.
The family has a high operating speed (30-50 MHz clock rate),
good external noise immunity, high fan-out, and the capability of
driving lines up to 600 pF capacitance.

_'AX

PLASTIC PACKAGE
CASE 605
TO·116

~

-

LSUFFIX

CERAMIC PACKAGE
CASE 632
TO-116

~SUFFIX
CERAMIC PACKAGE
CASE 607
T0-86

FUNCTIONS AND CHARACTERISTICS (Vee = 5.0 V. TA = 250 e)

-

Type(j)

Function
Quad 2-lnput NAND Gate
Quad 2-lnput AN 0 Gate

Quad 2-lnput NOR Gate
Quad 2-1 "put 0 R Gate
Quad 2-lnput NAND Gate
(Open Collector)
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Triple 3-lnput NAND Gats
(Open Collector)

Propagation
Delay

Power
Dissipation

mW

Case 605. 607. 632
to +750 C

Caso 607. 632

Factor

-55o C to +1250 C

Each Output

tpd
nstyp

typ/pkg

MC3000
MC3001
MC3002
MC3003

MC3100
MC3101
MC3102
MC3103

10
10
10
10

6.0
9.0
6.0
9.0

88
112
122
150

MC3004

MC3104

10

B.O

8B

MC3005
MC3006

MC3105
MC3106

10
10

6.0
9.0

66
84

o

MC3007

MC3107

10

8.0

66

MC300B
MC3009
MC3010
MC3011

MC3108
MC3109
MC3110
MC3111

10
10
10
10

6.0
B.O
6.0
9.0

140
90
44
56

MC3012

MC3112

10

8.0

44

MC3015
MC3016

MC3115
MC3116

10
10

8.0

22
22

MC3018

MC3118

MC3019

MC3119

..

MC3020

MC3120

10

6.0

62.5

MC3021
MC3022
MC3023
MC3024
MC3025
MC3026

MC3121
MC3122
MC3123
MC3124
MC3125
MC3126

8
8
10
30
20
20

14
14
6.0

9.0

100
85
62.5
90
70
90

Dual 3-1 nput 3-0utput AN 0 Series
Terminated Line Driver
Dual 3-lnput 3-0utput NAND Series
Terminated Line Driver
Dual 4-lnput Expander for
AND·OR·INVERT Gates
Expandable 4-Wide 2-2-2-3 Input
ANO-OR Gate
Expandable 4-Wide 2-2-2-3 Input
ANO-OR-INVERT Gate
4-Wide 2-2-2-3 Input ANO-OR·INVERT Gate

MC3028

MC3128

9.0

56

MC3029

MC3129

44

MC3030

MC3130

..

6.0
.:l.tpd = 1.0

15

MC3031

MC3131

10

10

87.5

MC3032

MC3132

10

7.0

40

MC3033

MC3133

10

7.0

40

Expandable 2-Wide 4-lnput
AND-OR-INVERT Gate
AND J-K Flip-Flop
AND Input J-K Flip-Flop
AND Input JJ-Ki< Flip-Flop
Double-Edge-Triggered Master-Stave
TVpe 0 Flip.Flop

MC3034

MC3134

10

7.0

:30

MC3050
MC3051
MC3052

MC3150
MC3151
MC3152

10
10
10

f-40MHz
f
50 MHz
f-40MHz

80
50
75

MC3053

MC3153

10

-

100

OR Input J-K Flip-Flop

MC3054
MC3055
MC3060
MC3061
MC3062
MC3063

MC3154
MC3155
MC3160
MC3161
MC3162
MC3163

10
10
10
10
10
10

f - 30 MHz
f - 30 MHz
f-30MHz
f - 50 MHz
f - 50 MHz
f - 30 MHz

95
80
120
100
100
176

Hex I "vertar
Hex I nvertar
Dual 4-1 nput NAND Gate
Dual 4-fnput AND Gate
Dual 4-lnput NAND Gate

(Open Collector)
a-Input NAND Gate
a-Input NAND Gate
4-Wide 3-2-2-3 Input Expander For
AND-OR·INVERT Gates
Triple 3~lnput Expander For
AND-OR Gates
Expandable Dual 2-Wide
2-lnput AND-OR-INVERT Gate
Quad 2-lnput Exclusive OR Gate
Quad 2-lnput ExcLusive NOR Gate
Dual 2-Wide 2-lnput AND-DR-INVERT Gate
Dual 4-lnput NAND Buffer Gate
Dual 4-lnput NAND Power Gate

Dual 4-lnput AND Power Gate

•

Output
Loading

AND Input J-K Flip-Flop
Dual Type 0 Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop

..

8.0
.:l.tpd1
.:l.tpdO
"tpd1
.:l.tpdO

6.0
6.0

.
.

CD F suffix denotes Flat Package, L suffix denotes Dual In-Line Ceramic Package, P suffix denotes Plastic Package,

(i.e., MC3000F = Flat Package, MC3000L = Ceramic Package, MC3000P = Plastic Package) .
... Direct Output = 10 minus the number of resistor-terminated outputs being used.
"Full output loading factor of the expandable gate is maintained .
• New Devices

=0.4
= 0.05
= U.4
= 0.05

40
25

[li]LfLf~ DOD

lOGIC DIAGRAMS

Numbers at ends of terminals represent pin numbers.
Numbers in parenthesis indicate loading.

Vee = Pin

14, Gnd = Pin 7.

GATES--------------------------------------------~
MC3000/MC3100
Quad 2-lnput NAND Gate

:=0-3

1101

111 : = 0 - 6
(119=0(1110
8

(101

(101

(1112=0(1113
11 (101

(101

.

(101

8

(1112~ 11 (101
(1113

tpd = 9.0 ns typ
Po = 112 mW typ/pkg

MC3003/MC3103
Quad 2-lnput OR Gate

MC3004/MC3104
Quad 2-lnput NAND Gate
(Open Collector)

:=C>-6

1119=C>11110
8

(101

:=r:=r:=r:=r-

(11

( 1112 = C > - 11 (101
11113

8

(1112~
.

11 (101

3=~

tpd = 6.0 ns typ
Po = 122 mW typ/pkg

MC3005/MC3105
Triple 3-lnput NAND Gate

6

1101

111
111
111

~~6

(10)

( 119 = r : = r (1110.
8

1101

1119~ 8
(1110
(1) 11

1101

3

11112=r:=r.
. 11 (101
11113

12'=~

3 ~;-;2
tpd

tpd = 9.0 ns typ
Po = 150 mW tvp/pkg

Po

(11
(1)
(1)

~~6

!1)9~
1) 10

(1)11

12 == 1 •. ? .1-3

tpd -= 9.0 ns typ
Po = 84 mW typ/pkg

8

= 8.0 ns typ
=

tpd == 6.0 ns typ
Po "" 66 m,W typ!pkg

88 mW typ/pkg

MC3007/MC3107
Triple 3-lnput NAND Gate
(Open Collector!

(11'~
111
2
12 (101
(1113

(101

(1110

3 = 1 + 2

MC3006/MC3106
Triple 3-lnput AND Gate

(101

('1'~
(11
2
.
12 (101
(1) 13

111
111

1101

(119~

(101

(101

(11
(101

:~3
:~6

(1113

tpd = 6.0 ns t~p
Po = 88 mW typ/pkg

:=C>-3

(11
(11

(119~
(1110

111
(11

3 = 1• 2

(11
(11

(11

(101

3"'~

(11
(11

111
(1)

(1)

MC3002/MC3102
Quad 2-lnput NOR Gate

:~3
:~6

111

111
(11

MC3001/MC3101
Quad 2-lnput AND Gate

111'~.
111
2
12 (101
11) 13
(11

~~6

(101

(1)

(101

(1~9~
(1 1 0 .
8

(11

(1) 11

12=~
tpd == 8.0 os tYP
Po =' 66 mW typ/pkg-

(10)

(101

MC3010/MC3110
Dual 4-lnput NAND Gate

(11
(11
(11
(1)

~~6!101

(
1)93=>
(1110
. 11112.
.
8110)
(1113

6=1·2·4·5

tpd = 6.0 os typ
Po = 44 mW typ/pkg

(continued)

LOGIC DIAGRAMS (continued)

GATES

(continuedj------------------------,;.-----,
MC3012/MC3112
Quad 4-lnput NAND Gate
(Open Collector)

MC3011/MC3111
Dual 4-lnput AND Gate

i==C}-s
1111!==C}-'

L f-

III ~===3
11)1

110)

III

(1)

110)

= 9.0 ns typ

tpd = 8.0

11)
11)
(1)
(1)
11)
11)

}--Bll0)

8::: 1 . 2 . 3 . 4 -10·11·12·13

ns

typ

''':~

11) 10
(1) 13
(1)
B (10)

MC3021{MC3121
Quad 2-lnput
Exclusive OR Gate
.
8110)

11.S)
(1.S)

III
(1)
S

~

~33»-"'"'

:=[>-3

IS)

(l.S)

""BD(1) 10

:==:)[>-S

IS)

(1)

(l.S) 9 = = : ) [ > (S)
11.S) 10
S

(1)

(l.S) 1 2 = = : ) [ > -

(1)

(l.S) 13

3=1.2+1_2
tpd = 14 ns typ
Po ~ S5 mW typ/pkg

3=1.2+1.2
Po : 100 mW typ/pkg

11 IS)

(1)
(1)

MC3024/MC3124
Dual 4-lnput NAND
Buffer Gate

.

(1) 13

11.6)

IB)

tpd :::: 14 ns typ

MC3023{MC3123
Dual 2-Wide 2-lnput
AND-OR-INVERT GATE

11.6)

:=L>-s

(B)

(l.S) 1 2 = L > l11B)
I1.S) 13

tpd = 6.0 ns typ
PD = 62.5 mW typ/pkg

B.O ns ,yp
22 mW typ/pkg

:=L>-3

11.S) 9 = L > IS)
11.6) 10
B

(9.10) + (13- 1) + (Expanders)

MC3022/MC3122
Quad 2-lnput
Exclusive NOR Gate

11.6)

(l.S)

1

11)

8:::: 3 . 4 . 5 . 6 . 1 1 • 12.1 .2

(1.6)

Emitter 11

(1)

I

tpd =: 8.0 ns typ
PD = 22 mW typ/pkg

Collector 12

~

B (10)

MC3020{MC3120
Expandable Dual 2-Wide 2-lnput
AND-OR-INVERT Gate

ml~

tpd
Po

3
4
10
11
12
13

Po "" 44 mW typ/pkg

MC3016{MC3116
8-lnput NAND Gate

1~

I::l~

~

6=~

Po : 56 mW ,yp/pkg

IiIl~
m

6110)

9--

11!10~
11
12
(1) 13

6= ,.2_4_5

tpd

MC3015/MC3115
8-lnput NAND Gate

SilO)

1

~BD-"'"

!ll

! = = c r -s (30)

!~Il!==cr-S(30)
6-1-2-4-5

S=19-10) +113-1)
tpd
Po

= 6.0 ns typ
~

62.5 mW typ/pkg

typ = 6.0 ns typ
Po ~ 90 mWtyp!pkg

(continued)

LOGIC DIAGRAMS (continued)

GATES ( c o n t i n u e d ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
MC3031/MC3131
Expandable 4-Wide 2-2-2-3-lnput
AND-OR Gate

MC3032/MC3132
Expandable 4-Wide 2-2-2-3-lnput
AND-OR-INVERT Gate
(1) 13

(1)

1--.------..

(1)

2

(1)

3

(1)

4

(1)

(1)

5

8 (10)

(1) 10
(1)

11--,-_

1--'1.-_

(1)

2

(1)

3

(1)

4

(1)

5

(1)

6

(1)

9

8 (10)

(1) 1 0 . - - , - _

(1) 12--r--.....
(1)13
~_
Collector 9 _ _ _ _ _ _ _ _ _--'

Emitter

Collector

11---------~

12~-----------....

8 = (13 -1) + (2 .3)

tpd = 10 ns typ

2

(1)

3-

(1)

5

(1)

6

(1)

9

MC3034/MC3134
Expandable 2-Wide 4-lnput
AND-OR-INVERT Gate
(1)

1

(1)

2

11) 3
(1) 4

~_

8 (10)

8 (10)

11) 10
11)11
(1) 12
(1) 13
5

(1)10,--'1....._
8

.10) + (Expanders)

MC3033/MC3133
4-Wide 2-2-2-3-lnput
AND-OR-INVERT Gate

4

(1)

+ (9

Po = 87.5 mW typ/pkg

1--'1.-_

11)

.6)

=7

ns typ
Po = 40 mW typ/pkg

(1) 13

11)

+ (4.5

tpd

= 113 '1)

9

+ 12 '3) + (4.5 .6) + 19.10)

tpd
Po

8:: (1 . 2 . 3 . 4 ) + (10.11 .12 .13) + (Expanders)

= 7 ns typ
= 40 mW typ/pkg

tpd == 7.0 ns typ
Po = 30 mW typ/pkg

POWER G A T E S - - - - - - - - - - - - - - - - - - - - - ,
MC3025/MC3125
Dual 4-lnput NAND Power Gate
(1.3)

13J--

(1.3)
(1.3)

o-c-- 2

(1)

3--{>o-c-- 5

(1)

6--{>o-c-- 7

(1)

8--{>o-c-- 9

(1)6~7
(1)8~"

(1)9~11
Po = 28 mW typ/pkg

MC2006/MC2056
MC2106/MC2156
Dual4-lnput Expander for
AND-OR-INVERT Gates

(1) 12
(1) 13

==L>-

14

(1) 11--{>o-c--12

3=r;2"

(1),13--{>o-c--14

Collector

(1)14~\
(1) 1
12
(1) 2 ,
-~13
(1)

530 \
3

Emitter

Emitter

(1)
(1)

(1)
( 1)

6

-

7

-\11

~

Collector

Po = 14 mW typ/pkg

9

2 =,1

tpd = 20 ns typ
Po = 105 mW typ/pkg

tpd

= 6.0 ns typ

Po = 132 mW typ/pkg

LOGIC DIAGRAMS

(continued)

FliP-FLOPS---------------------,
MC2023/MC2073
MC2123/MC2173
Dual J-K Flip-Flop
(Separate Clock)

MC2025/MC2075, MC2125/MC2175
AND J-K Flip-Flop
(1.2)

(.)

K3 14
K2 1
Kl 2

(1.00) CLOCK

3

(0.67)
(0.67)
(0.67)

J3

j~

5
6
7

!U!~

8
9

J

a
0

a
a

m"D=

RESET 13

(0.67)
(0.67)
(0.67)

12

11

an

°n+1

0

a

0
1
0

1
0
1

1
1

1

,

a
a

1
1

1
1

J

2

CCl5CK

3

K

1

1

(0.67)

15

12

(o.im

5

_

K

7

a

SET

8

tn

tn+1

K

a

1

13

CLOCK

(.)

K=K,-K2- K a

1
1
1

a

a

·'y"

(1.0)
(0.67)

J "" J, • J2 • J3

a

a

SET

(.)

0

11

a"

a"

t

0

an
f = 50 MHz typ
Po = 50 mW typ/pkg

f
Po

~

11

K

1
3

(0.67)

J

6

(0.67)

K

7

SET

8

tn

·'.2

13
12

5

a "

tn+1
K

a

11

Qn

an

0

t

t

0

a"

a"

MC2100 Series

a"

a

Cl:OCK
(•• ) RESET

(.)

MC2DOO Series
*1.15

14
2

(2.0)

(0.67)

K

a

(0.67)
(1.0)
(0.67)

MC2024/MC2074
MC2124/MC2174
Dual J-K Flip-Flop
(Common Clock)

MC2000 Series
'1.15

··2.3
MC2100 Series
'1.2
"2.4

f = 70 MHz typ
Po = 110 mW typ/pkg

70MHztyp

= 110 mW typ/pkg

MC2028/MC2078
MC2128/MC2178
OR J-K FLIP-FLOP

MC2026/MC2076, MC2126IMC2176
OR J-K Flip-Flop
(1.2)

m:~~!

M2 13
M114

100.67)
.67 )

K2
Kl

1
2

(2.00) CLOCK

3

l~:g~!
12

12

!g:~~!

19:~~!

Jl
J2

5
6

t~

8

(0.67)
(2.0)

J
0
1
X
X
X
X

x

CLOCi<

3

I&:~~I

JtS~

~

(0.67)

Jl

7

(1.2)
(1.2)

SET

11

11
7

SET 9

(1.2)

K2 2

L

K

M

a

x

x

X
1
X
X
X

X
X

X
X
0
X
1

a
1
X

= Don't Care

an

°n+1

0
0
0
1
1
1

0
1
1
1
0

J =

a

J, . J2

L = Ll' L2

K=K,.K2
M=M,.M2

f = 50 MHz typ
Po = 60 mW typ/pkg

Jl

J2

Kl

K2

JKl

JK2

X
X
X
X
1

X
1
0
1
X

X
X
X
X
0

X

0
0
0

0
1
1
1

a
1
0
X
1

X
X
0
1
X

1
1
0

0
0
1
X

0
X
1

a

x = Don't Care

a
1
1
X

a

a

X
X
0
0
0

1
1
1
1
1

X
1
1
X

1
X
X
1

1
1
1
1

a

1

a
a
a

Q

n +l
an
1

a

an
1

a

1
1
1

an
an
1
1

1
1
1
1

an
an

f = 35 MHz typ
Po = 60 mW typ/pkg

a
a

INTEGRATED CIRCUITS
MC400 Series (0 to +75 0 C)
MC500 Series (-55 to +1250 C)

...

MTTL integrated circuits comprise a family of transistor-transistor
logic designed for general purpose digital applications. The family has
a medium operating speed (20 MHz clock rate). good external noise
immunity, high fan out, and the capability of driving lines up to 600
pF capacitance.

"YI'frn!

P SUFFIX
PLASTIC PACKAGE
CASE 605
TO-116

MAXIMUM RATINGS
Rating

Value

Unit

'W'''~

Vdc

Supply Voltage - Continuous
MCSOO/SSO Series
MC400/450 Series
Supply Operating Voltage Range
Input Voltage

+8.0
+7.0
Vdc
Vdc
Vdc

4.5 to 6.0

+5.5
+5.5

Output Voltage

CERAMIC PACKAGE
CASE 632
TO-116

°c

Operating Temperature Range
MCSOO/SSO Series
M C400/450 Series

-55 to +125
o to +75

Storage Temperature Range
Ceramic Package
Plastic Package

-65to+150
-55 to +125

°c
°c

Maximum Junction Temperature

MC500/550 Series
MC400/450 Series

+175

~SUFFIX

+150

Thermal Resistance - Junction To Case (0 JC)

°C/mW

0.09
0.15

Ceramic Package

Plastic Package
Thermal Resistance - Junction 1"0 Ambient (8 JA)

CERAMIC FLAT PACKAGE
CASE 607

°C/mw

0.26
0.30

Ceramic Package

Plastic Package

FUNCTIONS AND CHARACTERISTICS (VCC = 5.0 V, TA

= 25 0 CI
Output

Tvpe(1) 12
(1) 13
2 (30)

Collector

(1)63J-

~~ ___~2

(1) 14

(I)
(1)

7
8

(1)

9

6~ ___\.1

7

10 (30)

Emitter

Emitter

:~---~14
10~ ___ ~13

12
tpd = 13 ns typ
Po = 50 mW typ!pkg

Collector

A maximum of 4 expanders may be connected to

the MC5450F or MC5453F/MC85453F.

FLiP-FLOP--------------------......,
MCBC5472/MCB5472F

J-K Flip-Flop

3 3ID

Numbers in brackets denotes beam number.

1J
1! [7J

!

(2)

(2)

SET

Jl

7

[2] CLOCK

2

1
[91
1 [10J

J2 8
J3 9

!Wnl

~~ 1~

(11[14]

K313

(2)

[5J RESET

a

12[13](10)

Q

10[11](10)

5

tn

tn+1

J

K

a

0
0
I
1

0
1
0
I

an
0
1

On

J::: J1 • J2. J3
K= K1-K2_K3
f~

Po

15 MHz
~ 40 mW Wp/pkg

MCE54HOO I MCE74HOO SERIES
INTEGRATED CIRCUITS
MCE54HOO Series (-65 to +1250 C)
MCE74HOO Series (0 to +700C)

The Dielectrically Isolated Integrated Circuit (DIIC) MTTL family
is designed specifically for use in military and space applications that
require a high degree of reliability under severe radiation environ·
ments and post irradiation operation. The MTTL DIIC family utilizes
nichrome resistors, post metalization passivation, monometallic inter·
connections, and very small high frequency transistor structures to
enhance the radiation resistant qualities of this line. Dielectrically
Isolated MTTL has the same electrical characteristics and pin con·
figurations as the conventional MTTL 54H/74H family which make
them interchangeable. This feature eliminates the need for redesigning
existing equipment to gain radiation·resistance, and allows the design
engineer to utilize a familiar logic type for new systems;

FUNCTIONS AND CHARACTERISTICS (Vcc =

5.0

V, T A

F SUFFIX
CERAMIC PACKAGE
CASE 607
T0-86

= 25°C)
Output
Loading
Factor

Type
Case 607

Function
Quad 2·1 nput NAN 0 Gate
Quad 2-lnput NAND Gate (Open Collector Output

Hex I nvertar
Triple 3-lnput NAND Gate
Dual4-lnput NAND Gate
11-lnput NAND Gate
Dual 4-lnput NAND ~ower Gate
Dual 2·Wlde 2·lriput AND·OR·INVERT Gats
4·Wlde 2·lnput AND·OR·INVERTGate
Dual 2·Wlde 2·3·lnput AND·OR·INVERT Gate
4·Wide 3·3·2·3·lnput AND·OR·INVERT Gate
J·K Fllp·Flop
Dual J·K Fllp·Flop
Dual Type 0 Flip-Flop
Binary To One-Of-Eight Line Decoder

-55 to +125o C
MCE54HOO
MCE64HOI
MCE54H04
MCE54Hl0
MCE54H20
MCE54H31
MCE54H40
MCE54H51
MCE54H54A
MCE54H56
MCE54H57
MCE54H72
MCE54H73
MCE54H79
MCE54Hl46

o

to +700 C
MCE74HOO
MCE74HOI
MCE74H04
MCE74Hl0
MCE74H20
MCE74H31
MCE74H40
MCE74H51
MCE74H54A
MCE74H56
MCE74H57
MCE74H72
MCE74H73
MCE74H79
MCE74H146

Propa·

gation

Power

Delay

Dissipation

Each

tpd

mW

Output
10
10
10
10
10
10
30
10
10
10
10
10
10
10
10

nstyp
6.0
8.0
6.0
6.0
6.0
9.0
6.0
6.0
6.0
6.0
6.0
16
16
16

typ/pkg
80
80
120
60
40
20
80
58
40
68
40
70
140
140
130

-

Individual data sheets for this series of TTL devices are available. To obtain copies, send your
request to: Technical Information Center, Motorola Semiconduci:or Products, Inc., P.O. Box'20924,
Phoenix, Arizona 85036.

MCE54HOO / MCE74HOO
SERIES lOGIC DIAGRAMS
Flat Package: VCC = Pin 4, Gnd = Pin 11.

GATES~----~----------------------------------~
MCE54HOO/MCE74HOO
Quad 2·lnput NAND Gata

(1)
(1)

(1)

2 ' = 0 -3

(')2'~3

(10)

(1)~(10)

(10)

(1)
(1)

7

(1),9~_

(1)130(1) 2
3

6= 0 -6
7

(1) 87~5

(1)10~8(10)

(1)12=014 (10)
(1) 13

(1)930(1) 10
13 (10)

(1)12=014 (10)
(1) 13

(1)

Po

=

tpd

(1)14~

(1)

8
9

(1)7~

= 6.0 ns typ
Po = 60 mW typ/pkg

= 8.0 ns typ
Po = 80 mW typ/pkg

6.0 ns typ

=80 mW typ/pkg

: : ~:~2
6

12

12=~

MCE54H20/MCE74H20
Dual 4.lnput NAND Gate

(1)

(10)

(1)

3=~

tpd

(10)

14

(i)6~

(10)

(1)9~

10~8 (10)

(1)

MCE54H10/MCE74H10
Triple 3·lnput NAND Gate

(1)

6 = 0 -5

(1)

MCE54H01/MCE74H01
Quad 2·lnput NAND Gata
(Open Collector Output)

tpd

MCE54H31/MCE74H31
11·lnput NAND Gate

MCE54H51/MCE74H51
Dual 2·Wide 2·lnput
AND·OR·INVERT Gata

(1) 1 - - - - ,
(1) 2

;::,:~'2('0)

(1) 3

(10)

(1)

5

(1)

6

(1)

7~M~~[=~

12(10)

(1) 8=

10 (10)

(1)

(1)

9

6

7
::: 8
9

(1)10

(1)

10110)

11)

(1) 13

(1)14----'

6=10204 0 5

V>-

(1)14~

8= (9 010) + (13 0 1)

8= 1 0 2 0 3'4 0 5'6,".12
:= 6.0 ns typ
Po = 40 mW typ/pkg

tpd

= 6.0 ns typ
Po = 58 mW typ/pkg

tpd = 9.0 ns typ
P'O = 20 mW typ/pkg

MCE54H54A/MCE74H54A
4·Wide 2·1 nput
AND·OR·INVERT Gate

tpd

MCE54H56/MCE74H56
Dual 2·Wide 2·3·1 nput
AND·OR·INVERT Gat.

MCE54H57/MCE74H57
4·Wid. 3·3·2·3·lnput
AND·DR·INVERT Gate
11)

(1)

(1)
(1)

6-""'---_;

(1)

6

(1)

7-""'---_;

(1)

8

(1)

9-""'---_;

(1)

(1) 3
(1) 13
12 (10)

1

1

(1)2~

3

11) 14
12 (10)

(1)

2

(1)

3

(1) 14
12 (10)
11)
(1)

13

(1)14-""'---_;

11)
(1)
(1)

~~'"''

(1) 6
(1)

7

(1) 8
(1)

9

(1) 10

12 = (3.5) + (6.7) + (8.9) + (13.,4)
12

= 6.0 ns typ
Po = 40 mW typ/pkg

tpd

= (1'2 .3)
tpd

Po

+ (13 "4)

= 6.0 ns typ

= 58 mW typ/pkg

12= (,.,3.,4)+(2.3.5)
+ (6 .7) + (8.9 .'0)
tpd - 6.0 ns typ

Po

= 40 mW typ/pkg

LOGIC DIAGRAMS

(continued)

Numbers at ends of terminals represent pin numbers for devices in the flat package.
Numbers in parenthesis indicate loading.

POWER GATE----,

FLiP-FLOPS------------,
MCE54H72/MCE74H72
J-K Flip-Flop

MCE54H40/MCE74H40
Dual4-lnput NAND Buffer

(2)

(2)

1

(2)12~

ID

Jl

7

J2
J3

8
9

(2) 14

(2) CLOCK

2

(2)6~
7

(1)

(2) 13

2 (30)

(2)

8

(2)

9

Q

K114
K2 1
K313

(1)

(1)

(2)

12(10)

Q

tn+1

tn

SET3

J

K

a

0
0
1
1

0
1

an

0

0
1

1

On

10(10)

10 (30)
(2) RESET

5

J=~
K = K 1. K2. K3

f = 30 MHz
Po = 70 mW typ/pkg

MCE54H73/MCE74H73
Dual J-K Flip-Flop
tpd "" 6.0 ns typ
Po = 80 mW tvpJpkg
J 1 4 1 0 _ 12 (10)
(2) CLOCK

(1)

(1)

INVERTER-----,
MCE54H04/MCE74H04
Hex Inverter

K

2

J

(2) CLOCK
(1)

K

lOa

(2)~

(1)

3-[:>0--2

(10)

(1)

5-[:>0--6

(10)

7-[:>0--8

(10)

(1)

(1)

9 - [ : > 0 - - 1 0 (10)

o

0
1
0
1

(10)

8

(10)

1
1

Q

f=30MHz
Po = 140 mW typ/pkg

MCE54H79/MCE74H79
Dual Type D Flip-Flop

(2)

SET

(1)

0

(2) CLOCK

(2)
(1)

SET

0

(2) CLOCK
14 ~,(2)

tpd = 6.0 ns typ
PD = 120 mW typ/pkg

K

o
9

'~
6

a

9

:

6

10 (10)

(10)

(3) RESET
(1) 1 3 - [ : > 0 - - 1 2 (10)

J

6

1 - [ : > 0 - - 1 4 (10)

(1 )

tn+1

13 (10)

57y_

(2) RESET
(1)

a

3

RESET

"~
2

~

13 (10)

1

a

12 (10)

0

an

on+1

0

0

0

0
1

1
0

0
1

1

1

1

On+1 "" on

3

f:35MHz
Po ~ 140 mW typ/pkg

~

~:

LOGIC DIAGRAMS (continued)

DECODER----------------------------------------~
MCE54H146~CE74H146

.Binary to 1-of-8 Line Decoder

Ei18'bi'8
(1)

1007 (10)

7

9

06 (10)

8

05 (10)

1204 (10)
1303(10)
1402(10)
1

01 (10)

2

00 (10)

(1) A 5

(1)

B 3

(1)

C 6

tpd = 14 ns typ
Po = 130 mW tvp/pkg

INTEGRATED CIRCUITS

MTTL integrated circuit memories comprise a growing family of
memories designed for direct general purpose memory applications
in transistor-transistor logic systems_ The family consists of both
read-only memories (ROMs) for look-up tables, microprograms, or
code conversion, and read-write random access memories (RAMs) for
scratch pad or cache applications_ The family has medium operating
speed, good external noise immunity and high fanout_

PSUFFIX
PLASTIC PACKAGE
CASE 605
TO-116

FSUFFIX
CERAMIC PACKAGE
CASE 607
T0-86

PSUFFIX

LSUFFIX

LSUFFIX

PLASTIC PACKAGE
CASE 612

CERAMIC PACKAGE
CASE 620

CERAMIC PACKAGE
CASE 632
TO-116

L SUFFIX

PSUFFIX

CERAMIC PACKAGE
CASE 638

PLASTIC PACKAGE
CASE 648

FUNCTIONS AND CHARACTERISTICS IVee = 5_0 V, T A = 25 0 e)

.. MC~153,1IIIC~053 .
MC3154,
IIIIC3155,
··MC3160,
MC3161,
.MC3162,
MC3163,

MC3054
MC3055
M~3060

MC3061
MC3062
MC3063

Quad 2-lnput NAND Gate
Quad 2-lnput AND Gate
Quad 2-lnput NOR Gate
Quad 2-lnput OR Gate
Quad 2-lnput NAND Gate (Open Collector)
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Triple 3-lnput NAND Gate (Open Collector)
Hex Inverter
Hex Inverter
Dual 4-II1Put NAND Gate
Dual 4-lnput AND Gate
Dual 4-lnput NAND Gate (Open Collector)
8-lnput NAND Gate
a-Input NAND Gate
4-Wide3-2-2-3 Input Expander For AND-OR-INVERT Gates
Triple 3-lnput Expandar For AND-OR Gates
Expandable Dual 2-Wide 2-lnput AND-OR-INVERT Gate
Quad 2.lnput Exclusive OR Gate
Quad 2-lnput Exclusiva NOR Gate
Dual 2-Wide 2-lnput AND-OR-INVERT Gata
Oual4..,lnput NAND Buffer Gate
Dual4-lnput NAND Power Gate
Dus"4-lnput AND Power Gate
Dual 3-lnput 3-0utput AND Serias Terminated Line Driver
Dual3-lnput 3-0utput NAND Series Terminated Line Driver
Dual4-lnput Expander for AND-OR-INVERT Gates
eXpandable 4-Wide 2-2-2-3 Input AND-OR Gate
Expandable 4-Wida 2-2-2-3 Input AND-OR-INVERT Gate
4-Wide 2-2-,2-3 Input AND-OR-INVERT Gate
Expandable 2-Wide 4-lnput AND-OR-INVERT Gate
AND J-K Flip-Fiop
.ANO J-K Flip-Flop
AND. Input JJ-KK Flip-Flop
Double-Edge-Triggered Master-Slave Type D Flip-Flop
OR Input J-K Flip-Flop
AN.D Input J-.K Flip-Flop
pual Type D Flip-Flop
pual J-K Flip-Flop
Dual J-K Flip-Flop
Dual J-K Flip-Flop

GENERAL INFORMATION
MC3100/3000 Series

INTRODUCTION
MTTL III integrated circuits are designed with speed approaching the limit for saturated logic and for good I.oad
driving capability. This line includes all the characteristics
that have made transistor-transistor logic so popular. The
major advantage of MTTL III over other TTL lines is the
square transfer characteristic (Figure 1) that exists only
for the MTTL III family. Because of this "ideal" transfer
characteristic. the MTTL III farnily is the only TTL line
that is truly compatible with MDTL. Another advantage
of this family over competitive TTL lines is that it is designed to minimize problems associated With ringing.
The circuits in theMTTL III family are distinguished
by a multiple-emitter input transistor, a darlington active
"pUll-Up" in the upper output netWork, and an active bypass network in the base of the output pull-down transistor
as shown in. Figure 2.
The multiple-emitter input configuration offers the
maximum logic capability in the minimum physical area
and provides improved switching characteristics duril'lg
turnoff. Clamp diodes are provided at each of the inputs
to limit undershoot that occurs in typical system applications such as driving long interconnect Wiring. The

FIGURE 1 - COMPARISON OF CONVENTIONAL
TRANSISTOR-TRANSISTOR LOGIC AND MTTL III

4

•

Darlington output configuration provides very low output impedances in each of the two output states. These
low impedances result in excellent ac noise immunity and
allow high-speed operation while driving large capacitive
loads.
The active bypass shown in the unshaded area of Figure 2
holds the phase inverter transistor "off" until gate threshold is reached. This circuit operation provides the
squared transfer characteristic shown in Figure 1.
In addition to improving the transfer characteristic,
the bypass network offers a number of advantages compared
to a simple resistor that can be traced to a much smaller
impedance variation with temperature.
1. Lower bypass impedance for the reverse current
of the output transistor at elevated temperatures, provides faster turn-off.
2. A lower current spike during the turn-off transient causes a lower ac power factor resulting in
a lower total power consumption. This advantage is even more pronounced at higher temperatures.
3. Faster turn-on at low temperature.

FIGURE 2 - TYPICAL MTTL III CIRCUIT

MTTL III

;§
<5

3

?
w
CI

«

I-

2

..J

o

>
I;)

1=
;)
o

1

o~~--~--~==~====~
2
3
o
INPUT VOLTAGE (VOLTS)

~_.......,.

.. ,. . ___=-___~_,"'_'_'_'_I!III"._'~'"W'~lllI'___""_"""___""_"""'"-......;.........-..........
"' ,,.,...-....- - - - -.............- - -.....--~---...,.......".

•

MTTL III

GENERAL INFORMATION
MC3100/3000 Series

TYPICAL CHARACTERISTICS
Typical operating characteristics of the MITL III family
include: (Unless otherwise indicated. the parameters ara defined
for Vce =+5.0 volts and T A =+250 C.l
Supply Voltage Operating Range = 4.5 to 5.5 volts
Operating Temperature Range:
MC3100Series = -550 C to +1250 C
MC3DOO Series = 0 to +750 C
Output Drive Capability
Gates (Output Loading Factor):
MC3100 Series = 10 Gates
MC3DOO Series = 10 Gates
Capacitance = 600 pF
Output Impedance
High State = 100hms nominal (unsaturated)
Low State· 10 ohms nomi nal
Output Voltage Swing = 0.2 to 3.5 volts typical
Input Voltage Limits
+5.5 volts maximum
-1.5 volts minimum (1)

"NAND" GATES
The basic gete of the MTTL III logic family is the positive
logic NAND gate. This gate is characterized by high speed. good
load driving capability. superior transfer characteristic. and freedom
from ringing problems. Representative of the verious NAND gates
presently available in the MITL III family is the 4-input NAN D
gate (% of the MC3110/3010) shown in Figure 3.

"AND" GATES
While it is possible to design a complate logic system with
NAND logiC, it is often desirable to use other logic forms to save
circuits, power dissipation, and propagation delay. Therefore,
Motorola has added the positive logic AND function to the MTTL III
family.
Examples of the AND function are the standard quad 2-input
gate, dual 4-input gate, dual 4-input power gate and a dual 3-input,
3-output line driver.
The technique used to form the AND function is the addition
of an invamr to the basic NAND circuit. As'shown in Figure 4,
the inverter transistor with a collector resistor and an offset diode
conn'ected to its emitter is inserted between themultiple-emitter
input transistor and the basic circuit phase-splitter transistor. The
extra inversion adds only 3.0 ns propagation delay and about 6.0
mW additional power dissipation.

Switching Threshold· 1.5 volts nominal
Input Impedance
High State = 400 k ohms nominal
Low State = 2.4 k ohms nominal

FIGURE 3 - MTTL III POSITIVE LOGIC "NAND" GATE
CIRCUIT

Worst-Case de Noise Margin
High State· 0.700 volt minimum
Low State = 0.700 volt minimum

Vee
'4

Power Dissipation
22 mW per gate typical
50-80 mW per flip·flop typical

Switching Speeds (2)
Average Propagation Delay = 6.0 ns per gate typical
13 ns per flip-flop typical
Rise Time = 1.0 ns typical
Fall Time = 1.3 ns typical
Flip-Flop Clock Frequency (MC3061) = 50 MHz maximum.

7
OND

% Md311013010

FIGURE 4 - MTTL III POSITIVE LOGIC "AND" GATE
CIRCUIT
Vee

'4

(I) Assuming unused inputs are returned to voltage not

greater than 4.0 Vdc.
(2) The switching characteristics.of the MTTL III family are
defined with respect to the associated transitions of the
voltage waVeforms. The average propagation delay is defined as the average of the turn-on delay and the turnoff delay measured from the 1.5 V point of the input to
the 1.5 V point of the associated output transition or:
ton + toff
tpd ='--2-- ns

Rise time is defined as the positive going transition of the output from the 1.0 V to the 2.0 V level. Fall time is defined as
the negative output transition from the 2.0 V to the 1.0 V
level.

7
OND

% MC3101/3001

GENERAL INFORMATION

MTTL III

MC3100/3000 Series

I

"OPEN COLLECTOR" GATES

RL(min) Calculations (See Figure 6)

This open-collector MTTL gate, when supplied with the proper
load resistor RL, may be paralleled with other open-collector
MTTL gates to perforM, the "Implied AND" function, and simultaneously will drive from one to nine MTTL III loads_ When used
by itself the gate can drive ten MTTL III loads_ Only one resistor
is needed for any set of paralleled outputs; the upper and lower
limit for RL will be determined by the desired circuit configuration. The maximum resistor value is required to ensure that
sufficient load current and off current through the outputs will be
available during a logic "1" level at the output_ The minimum
resistor value is required to ensure that I RL plus the load current
will not exceed the current sinking capabilities of one output transistor with the output in the logic "0" state.
For both limits the value of R L is determined by:

Unless it can be absolutely guaranteed that more than one output transistor will be on during all logic "0" output periods, the
sink current (lOLl must be limited to 20 rnA, the maximum current
which will ensure a maximum logic "0" level (VOLI of 0.4 volt.
The sink current comes partly through the loed resistor and partly
from the inputs being driven (IFf. The equation for calculating
the minimum value of R Lis:
VCC-VOL
RL(minl = IOL - N IF -

FIGURE 6

Vee

Where VRL is involts and IRL in amperes.

·Current through OFF
output I. negliglbleet

logic "0'1 level.

RL(max) Calculations (See Figure 5)
The allowable voltage drop across RL (VRLI is the difference
between VCC and the VOH laval required at the load:
VRL = VCC - VOH·
The total current through RL (I RLI is the sum of the load currents
(lRI and the off-level reverse currents (lCEXI through each of the
paralleled outputs:

where n = number of outputs paralleled, and N
MTTL III loads.

number of

I
I

~

I
I

N

L-o-

Therefore, the equation for RL(maxl is:
VCC-VOH
RL(maxl = n ICEX + N IR

"AND-OR-INVERT" GATES
Unlike the MDTL family of logic Circuits, the outputs of
MTTL logic circuits cannot be tied together to perform the "Implied AND", often called the "Wired OR" functio~_ If the outputs
of the MTTL family devices are tied together, the lower output
transistor of one circuit and the upper output transistor of another
circuit can be "on" simultaneously. This condition provides a
lOW-impedance path from VCC to ground, and due to excessive
current flow, the saturated output state cannot be maintained and
the desired logic function is nOt satisfied.
To retain the logical advantages offered by the "Implied
AND" with the speed and loed driving capability of an active pullup, the MTTL III family offers an AND-OR-INVERT Gate. The
gate in Figure 7 incorporates two 2-input AND functions with outputs that are ORed and iilVerted_ The AND function is provided
by two multiple-emitter input transistors (01a and Q1b). The OR
and INVERT operation is accomplished by two paralleled tran·
sistors (02a and Q2bl sharing a single collector resistor and a
single bypass network. These paralleled transistors in turn drive
the standard output.
The common collector and emitter nodes of one gate in each
package are available externally to permit expansion.

FIGURE 5

EXPANDER AND EXPANDER NODES
I
I

I
I

N

~l--cr

The ORing nodes of 1/2 the MC3120/3020 dual AND-ORINVERT Gate (Figure 71 are available for expanding the number of
AND gates to four_ Since these are comparatively high-impedance
nod~s, care should be taken to minimize capacitive loeding on the
expander terminals if switching speed is to be maintained_ When an
expander is to be used with an expandable AND-OR-I NVERT gate,
it should be placed as close as possible to. the gate being expanded.
The increese in the average propagation delay per AND gate added
to an expandable AND-OR-INVERT gate is typically 1_0 nslAND

•

GENERAL INFORMATION

MTTL III

MC3100/3000 Seri..

gate. The increase in average propagation delay as a function of
capacitance added to the expander nodes is typically 1.0 ns/pF.

FIGURE 7 - MTTL 111 "AND"()R-INVERT" GATE
CIRCUIT
Vee
12

14

10

tions that exceed the capability of a standard gate. The MITL II I
power gates, shown in Figure 10, are designed to maet these require·
mants with a minimum of additional circuitry. Available in both

FIGURE 9 - MITL 111 POSITIVE LOGIC "OR" GATE
CIRCUIT

9

Vee
14

13

,
GND

1> MC.3120/3020

,

1/4 MC31 0313003

GND

"NOR"GATES
To save inverters, the system designer often. needs the positive
logic NOR function as well as the negative logic NOR available with
the standard NAND gate. This capability is incorporated in the
MITL III line in the form of the MC31 02/3002, quad 2-input NOR
Gate. The NOR gate is a modified AND"()R-INVERT gate with

NAND and AND functions, the power gates feature output circuitry designed to provide twice the fan-out of conventional gates:
20 stendard gate loads instead of 10.

only a single emitter on each input transistor, as shown in Figure 8.

LINE DRIVERS

"OR" GATES

Standard MTTL III gates offer good load driving capability and
high fan-out. In most systems. however, there are a few applic,,"

To minimize switching transients on long lines, the MITL III
family includes dual 3-input/3·output serieHerminated line drivers.
Two outputs have 75·ohm resistors in series with the standard output node, and one is connected directly to the node. A good
match can be made at the output of each resistor when driving
9:J..ohm coax or 12().ohm twisted peir. For loeds of 50 to 93
ohms, the two resistive outputs are paralleled for impadance match.
ing. The non-resistive output can be used to drive adjacent loads
in a normal fashion. The total number of output loads connected
to the direct output (non-resistive output) is the standard fan-out
of 10, minus the number of resistor terminated outputs being used.

FIGURE 8 - MTTL III POSITIVE LOGIC "NOR" GATE
CIRCUIT

FIGURE 10 - MTTL III POWER GATE
CIRCUIT (AND}

To provide the system designer with still another tool for optimum design, the MTTL III Series also offers the positive logic OR
function. As shown in Figure 9, the OR is essentially a NOR gate
with an additional inverter.

POWER GATES

Vee
Vee
14
2.4 k

2.4

k

800

60

1/2 MC3126/3026

7
GND

GENERAL INFORMATION

MTTl III

MC3100/3000 Series

Figure 11 shows 1/20f the circuit of the MC3129/3029, dual 3input, 3-output series terminated NAND line driver. Figure 12
shows a typical application of this circuit and Figure 13 demonstrattts the effects of series terminl!!ltion without a significant loss in
high state noise immunity.

OPERATING CHARACTERISTICS OF FLIP·FLOPS
The cornerstone of any modern logic family is the capability of
its storage elements. The MTTL III flip·flops are designed to give
maximum logic I performance with fewer sYstem restrictions than

their predecessors. Three basic designs are typified by the MC3150/
3050, MC3160/3060, MC3161/3OO1 and MC3162/3OO2. Common
to aU designs are:
1. Edge clocking.
The flip-flop is clocked at the normal MTTL III threshold voltage (approximet'lily 1.5 V @ 250 C).

FIGURE 11 - MTTL IJJ TERMINATED LINE DRIVER (NANDI

2. Overriding asynchronous inputs.

,.

Vee

The direct SET and RESET inputs control· the operation
of the flip· flop regardless of the state of the clock or the
information on synchronous inputs.

FIGURE 14 - LOGIC DIAGRAMS OF EDGE-CLOCKED MTTL
IJJ FLlp·FLOPS
ReSETo-~--------r---------'

a

7
ONO

1/2 MC3129/3029

CLOCK

o---------t-H
a

SETo-~----------------~

FIGURE 1.2 - TYPICAL APPLICATION OF THE LiNE DRIVER

MC3160/3060

~o--F~========~=r--:

~o--t~========~=t

__)

MC3161/3061

RESET

FIGURE 13 - EFFECTS OF SERIES TERMiNATION WITH A
MTTL III GATE DRIVING A 93-0HM LINE

\ .

UNTEAMINATEO

J3
SERIES TERMINATED

S'OURCE END. A

J
~~___~~_g~;~
~

n

3

SOURCE ENO.A

L

++-+'-t-+-

.

CI}~3 .LO~DENDO

LOAOENDII!IC

uP

~.1
g

J

. e

L

CLOCK
JK

o--t-r-H-----+-1

--+H,,':"'::::::><;

K1

_1-='--·---""~

-.

SET
MC315013060

•

•

GENERAL INFORMATION

MTTL III

MC3100/3000 Series

3. Short set·up times.
Prior to the clocking edge, the input information must
become stable. The MTTL III flip·flops require only a
minimum of time to read a "I" or a "0". Therefore
data may be applied anytime in the clock period except
during the time interval between the Set-up and Hold
times. This characteristic permits higher clock frequen·
cies or eliminates the necessity for critical control of
clock pulse width.
4. All inputs to the storage elements including the clock
input have inputs that are compatible with all three
MTTL families.

Power and Ground Distribution
Special care should be taken to insure adequate distribution of
power and ground syStems. The typical rates of change of current
and voltage for a single MTTL III gate are in the range of 107 A/s
and 108 V Is respectively. These figures reflect the necessity for a
low·impedance power supply and ground distribution system, if
transients are to be minimized and noise margins maintained. The

use of AWG No. 20 wire or larger is often required. For printed
circuitry, line widths of 100 mils or more are often necessary. A

ground plane is desirable when using a large number of units.

Bypassing
·The MC3150/3050 and MC3160/3060 flip-flops are positive
edge triggered storage elements. That is, the inputs are enabled on
the negative edge of the clock and the information is stored in the
flip-flop on the positive edge of the clock. The MC316113061 and
MC3162/3062 dual flip-flops are negative edge triggered devices
and therefore operate in precisely the opposite manner. That is,
itata is stored on the negative edge of the clock.
In addition to the previously mentioned storage elements. The
MC3152/3052 Master-Slave flip-flop is also available. Data is stored
in Master flip-flop when the clock is low and transferred to the Slave
flip-flop when the clock goes high. Detailed discussion of each of
the MTTL III flip-flops is provided on the individual data sheets.

To reduce supply transients, the breadboard should be bypassed
at the point where power is supplied to the board and at intervals
throughout the board. The use of a single bypass capacitor at the
output terminal of the power supply is not adequate in a bread·
board utilizing the fast rise and fall time MTTL III circuits. A com·
paratively large, low-inductance type capacitor (in the 1.0 /IF range)
is suggested at the point where power and ground enter the board.
In many cases it has been found that distributing 0.01 /IF capaci·
tors for every five packages throughout a breadboard is adequate
to suppress normal switching transients. It is also suggested that a
bypass capacitor be placed in close proximity to any circuit driving

a large capacitive load.

Power Dissipation
FIGURE 15 - LOGIC DIAGRAM OF MTTL III MASTER-SLAVE
J-K FLIP-FLOP

The typical average de power dissipation is given for each MTTL
III device (3). It should be noted that the totem·pole output com·
mon to all high-level MTTL circuits has an associated ac power dis·
sipati,on factor. This factor results from the timing overlap of the
upper and lower output transistors during the normal switching op-

eration and is typically 0.4 mW/MHz/output for a 15·pF load.
This ac power dissipation should be added when calculating the
total power requirements of the MTTL III circuits.

Unused Inputs and Unused Gates

MC315213052

To minimize potential problems resulting from external nOise,
the unused inputs of any MTTL III logic circuit should not be left
open, but should either be tied to the used inputs or returned to a
voltage between 2.0 and 5.5 Vdc. (For flip·flops, see appropriate
data sheet for additional detail,) If the unused inputs are returned
to a voltage, care should be exercised to insure that the absolute
voltage between the most negative input level and that voltage
does not exceed +5.5 volts. The total number of inputs that can
be tied to the output of any driving gate is 25. (This is defined as
high-state output loading factor.) It should be noted that the lowstate output loading rules must still be maintained. The minimum

logical "I" [evel for. th.e high,state output loading is summarized
for VCC = 5.0 V, VIL = 1.1 V, and IOH = -2.0 mA: VOH = 2.5
volts minimum @ OOC.
To minimize power drain, the inputs of any unused gate in a

package should be maintained at the level that would place the
outputs in the high state (the low power dissipation state).

BREADBOARDING SUGGESTIONS
When breadboarding with any form of high·speed, high-performance TTL circuit, the designer must always be aware of the problems
caused by very high switChing speeds. These switching speeds, e..
pecially the frequencies associated with the very fast rise and fall
tiines of the circuits, are in the upper RF range and good high·
frequency layout techniques should be used. The follOWing breadboarding suggestions will help the designer in his initial circuit lay·
out. In many cases the breadboarding suggestions will have to be
modified to meet the requirements of the designer's specific application.

(3) Po =

IPOL + IPOH
2
(Vec)

where IpOL and IPOH are the typical current drains at VCC =
+5.0V.

MTTL III

•

GENERAL INFORMATION
MC3100/3000 Series

DEFINITIONS

Input breakdown voltage
Total parasitic 9apacitance, which includes probe,

IC
ICO
ID
IE
lEO
IEXE

PRF
PW

wiring, and load capacitances

L

Collector current
\
Expander collector leakage current

4

Rise time

tHold "0"

I nput diode current with negative voltage applied
Emitter current
Expander emitter leakage current

tHold "1"

Minimum time that low state data must be maintained
after the clocking edge
Minimumtime that high state data must be maintained
after the clocking edge

Expander drive current at emitter node of AN D-ORINVERT gate
Input forward current with VCC applied
Input forward current with VCCL applied
Input forward current with VCCH applied
Clock input forward current

o input forward current
J input forward current
K input forward current
JK input forward current

Atpd

IOL2
IOL2A
IOLlB,'C
IOL2A,2C
IPD
IPDH
IPDL
IR
IRC
IRD
IRJ
IRK
IRJK
IRR
IRS
ISC
P1

applied
Output high state current

capacitance at expansion points

tpd "0"

Output low state current with VCCL applied
Unterrninated output low state current with VCCL
applied
Output low state current with VCCH applied
Unterminated output low state current with VCCH
applied
Terminated output low state current with VCCL
applied
Terminated output low state current with VCCH
applied
F lip-flop power supply drain current
Power supply drain with inputs high
Power supply drain with inputs low
Input leakage current
Clock input leakage current
D'input leakage current
J input leakage current
K input leakage current
JK input leakage current
RESET input leakage current
SET input leakage current
Short-circuit current

Pulse used to set flip-flop state

Turn-on delay
Turn-off delay

tpd "'"
tsd "0"

Turn--on delay from asynchronous input

tsd
"'""0"
tSetup

Turn-off delay from asynchronous input
Minimum time that low state data must be applied
prior to the clocking edge

tSetup "1"
TPin
TP out
VBE max

Unterminated output high state current
Terminated output high state current
Output low state current

Average increase in propagation delay per expander

AND gate when connected to an AND-OR-INVERT
gate
Increased propagation delay caused by additional

RESET input forward current
SET input forward current
I nput current
Maximum rated power supply current with V max

IOH
IOHA
IOHB,C
IOL
lOll
IOLlA

Pulse repetition frequency
Pulse width
Fall time

VBE min
VCC
VCCH
VCCL
VD
VEE1
VEE2

VIL
Vrnax

VOH
VOL
VOLl
VOL2
VOL3

M;nimum time that high state data must be applied

prior to the clocking edge
Test point at input of device under test
Test point at output of device under test
Emitter node threshold voltage for logic "0" output
level
Emitter node threshold voltage for logic "1" output
level
Power supply voltage
High power supply voltage
Low power supply voltage
Diode clamp voltage
Voltage applied to expander emitter for VOL test
Voltage applied to expander emitter node for ICO
test
Maximum logic "0" level output voltage
Logic "1" threshold voltage
Reduced supply voltage to hold input above threshold and to prevent noise from entering_ the device
Logic "0" threshold voltage
Maximum rated power supply voltage
Output high voltage with IOH source current
Output low voltage with IOL source current
Maximum output low voltage with VCCL applied
Maximum output low voltage with VCC H applied
Maximum output low voltage on terminated output

with VCC L applied
VOL4
VR
VRH

.Maximum output low voltage on terminated output

with V CCH applied
Logic uf" minimum reverse voltage
Logic "," maximum reverse voltage

•

GENERAL INFORMATION

MTTL III

MC3100/3000 Series

Rating
Supply Voltage - Continuous

RATINGS

Unit

+7.0
+7.0

Vdc
Vdc

4.5 to 5.5

Vdc

MC3tOOseries
MC3000 series

Supply Operating Voltage Range

MAXIMUM

Value

Input Voltage

+5.5

Vile

Output Voltage

+5.5

Vile

-55 to +125
Oto +75

°c
°c
°c
°c

Operating Temperature Range

MC3t 00 series
MC3000 saries

Storage Temperature Range - Ceramic Package
Plastic Package

-65 to +175
-55 to +125

PACKAGING
All MTTL III integrated circuits are available in the
TO-S6, 14-lead ceramic flat package (add suffix F to
type number when ordering), and in the TO-116, 14lead dual in-line ceramic package (suffix L). MC3000
Series devices are also available in the TO-116, 14·lead
dual in-line plastic package (suffix P).

LSUFFIX
CERAMIC PACKAGE
CASE 632
To-11&

PSUFFIX

0.005

PLASTIC PACKAGE
CASE 605
TO-116

--.1-

+=~1"0~1~~~
~

o.rioo.

o.m

ij]O{o.oo,
[1jj5

~11

0.030
0.07'
0.045

,~

'.240

;m;
Lead 1 identified by color dot or by Ilbow on I..d.

FSUFFIX
CERAMLC PACKAGE
CASE &07
TO-86

SEATING

~~~\
~L
~:::~

['30
MAX

Mj LHH

Four inlUlating IIInd-offs Ire provided

iIm

MC3100/MC3000 series

I

QUAD 2-INPUT "NAND" GATE

MC3100F • MC3000F
MC3100L • MC3000L,P
(54HOOJ)

(74HOOJ,N)

This device consists of four 2-input NAND gates.
Each gate may be used as an inverter, or two gates
may be cross-coupled to form bistable circuits.

CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN

Vcc
14

2.4 k

800

60

3
2

Positive Logic: 3

=~

Negative Logic: 3 =

"i""+"'2

Input Loaqing Factor '= 1
Output Loading Factor = 10
Gnd

Total Power Dissipation = 88 mW typ/pkg

Propagation Delay Time

Pin numbers for the 54HOOF/74HOOF device- are

DEVICE

shown in the chart_ These devices are available on
sp'ecial request.

MC3100F.Ll3000F,L,P
54HOOF/74HOOF

=6.0 ns typ

PIN NUMBERS
3

4

5

6

3

6

7

5

11

8

9

10

11

12

13

14

8

9

10 14

12

13

4

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX

Vcc

950
£.1.0%

280
t+
7.00$

t-

7.0

nS"

TP out
MM06150
or Equiv

PULSE
GENERATOR

t-

10%

- I

=

PRF
1.0MHz tvp
PW - 50% Duty Cycle
t+ = 7.0 ns

50

'MMo7000
or Equiv

= 7.0n5

0 V

tP~_""
'pd+

:;'2.4 V

T~out

1.5 V

-_-SO.4 V
Gnd

CT = 25 pF :"" '!otal parasitic cap_Beitance, which includes probe, wiring, and load
capacitances.
The coax ctelavs from input to Scope and output to scope must be matched.
The sc,?pe must be terminated if'! 50-ohm impe~ance.. The '950-ohm re~istor
and the scope termination impedance 'constitute a 20: 1 attenuator .probe. Coax
shall be.CT-O?O-50 or equivalent.

See General Information section for packaging.

•

ELECTRICAL CHARACTERISTICS

CtJ
....
o

gate. The other gates are tested in the same
manner. Further, test procedures are shown

,o

for only one input of the gate under test.

To complete testing, sequence through remaining inputs.

:=0-:=0-,:=0--

S

n

3

CtJ

o
o
o

6

nO

8

~

12-~

13~11

Test
Temperature

t -sn

MC3000

Characteristic

Symbol

Input
Forward CUrrent

Clamp Voltage

-2.0

~2.

50

IR

I

t

0

50

-2.0

-2.0

-2.0

50

50

50

5.5

BVin

VD

Short-Circuit
Current

2.4

Ise

-40

0.4
2.4

2.4

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

I,.
1.0

1.0

I.

0.4
2.5

50

0.4
2.5

1.1

2.0

0.4

-10

1.1

1.8

0.8

1.8

-10

1.1
1.1
0.9

2.4

4.0

0.4

2.4

4.0

0.4

2.4

4.0

2.0

0.4

2.5

4.0

1.8

0.4

2.5

4.0

1.8

0.4

2.5

4.0

'.0

'.0

~

c
Vee

VCCl

VCCH

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.2.')

10l

I 10H

I I,. I I.

I V"

I VIH I V, I

V,

V'H

I Vmox I Vee IVeCl I VeeH

0.4

2.5

CD

V1HX

0-

2.5

2.5

I

VIHX

Gnd

14

,'

I pAdc

14

2,7

Vdc

14

2,7*

-2.0 I mAde

-1.5

0.4

0.4

VOL

10H

20

!:!.

TEST CURRENT / VOLT AGE APPLIED TO PINS LISTED BELOW,

5.5
-1. 5

Y OH

10l

MC3DOO Test Limits

Output
Output Voltage

O°C
+2SoC
+7SoC

Unit

IF

Leakage Current
Breakdown Voltage

MC3100 Test Limits

+2SoC
+12SOC

V"

TEST CURRENT / VOLTAGE VALUES
Volts
Vmax
VIH V,
V,
V'H

mA

@

MC3100

Pin
Under
Test

Vdc

14

I Vdc

14

Vd,

14

I -100 I -40 I -100 I -40 I -100 I -40 I -100 I -40 I -100 I -40 I -100 I mAde

*

,'
"

I
14

11.2"': "

powerRequirements
(Total Device)
Maximum Power
SUpply Current
Power SupPly Drain

1,2,4,5,7,
9,10,12,13

14

Im=

14

IpDH

14

40

IpDL

14

16.8

tpd+

I,'

10

tpd~

I,'

10

1,2,4,5,
9, 10, 12, 13

14
14

1,2,4,5,7,
9,10,12,13

Switching

Parameters
Turn-On Delay
Turn-Off Delay

S

n

Test procedures are shown for only one

'" Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

"
"

MC3100/MC3000 series
QUAD 2-INPUT "AND" GATE

MC3101F • MC3001F
MC3101L • MC3001L,P
(54H08J)

(74H08J,N)

This device consists of four 2-input AND gates.
This non· inverting function is useful for optimizing
logic design, or for direct implementation of standard
logic equations.

CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN

Vee
14

2.4 k

2.4 k

800

60

3

Positive Logic: 3 = 1 • 2
Negative Logic: 3 = 1 + 2

2

Input Loading Factor:;;; 1
Output Loading Factor = 10
Total Power Dissipation == 112 mW typ/pkg
Propagation Delay Time"" 9.0 ns typ

7

Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

280

,+

7.0 ns

,-

7.0 ns

MMD6150
or Equiv

"-=:"""-0 v
PW = 50% DutV Cycle
t+=7.0ns
t- =7.0n$

50

MMD7000

or Equiv

~0.4V

------------------------Gnd
CT

= 25

pF "" total parasitic capacitance, which includes probe. wiring. and load

capacitances.
The coax deleys from input to -scope and output to scope must be matched.
The $Cope mult be terminated in 50-ohm impedance. The 950-ohm resistor
and the I(:Ope termination impedance constitute a 20: 1 attenuator probe. Coax

shall be CT,-070-50 or equivalent.
See Gene,al I nformation section for packaging.

I

•

ELECTRICAL CHARACTERISTICS

s:
CAl
.....
(")

Test procedures are shown for only one

gate. The other gates are tested in the same
manner. Further, test procedures are shown

o
.....

for only one input of the gate under test.

To complete testing, sequence through fe·
maining inputs.

s:

(")

CAl

o

o
.....
n-O

:=0-3
:=0-6
9=0-8
12=0-"

Tesl
Temperature

10

MC3101

13

10L

10H

{ -SH
+2S"C
+12n

20

-2.0

20

-2.0

20

-2.0

{

20

-2.0

MC3001

Pin
Under
Test

Symbol

Characteristic

MC3101 Test Limils
55'C I +2n .
+125'C
Min I Max I Min I Max I Min I Max

I

MC300 I Tesl limils
O'C
I +25"C I +75"C
Min I Max I Min Max Min Max

1-

Input
Forward Current

'F

-2.0

-2.0

-2.0

- 20

Leakage Current

'R

50

50

50

50

Breakdown Voltage
Clamp Voltage

I

BVin

3

VOL

3

VOH

Short-Circuit
Current

Power Requirements
(Tolal Device)
Maximum Power
Supply Current

Power Supply Drain

14

-

24

14

-

I max

14

IpDH

Switching
Parameters
Turn-On Delay
Turn-Off Delay

t pd _

tpd+

I
I

-40

2.4
-100

34

48

1,3

I- I - I- I

1,3

I - I - I - I

O. ,

0.4

2.4
-100

3

IpDL

2.4

-40

'sc

I

0.4

Unit

-2.0

-2.0

mAde

50

50

/lAde

24
48

-40

0.4
2.5

-100

-

24

4B

2.5

-40

-40

10H

0.4

2.4

4.0

1.8

0.4

2.4

4.0

1.8

0.4

2.4

4.0

5.0

4.5

5.5

2.0

0.4

2.5

4.0

5.0

4.75

5.25

1.8

0.4

2.5

4.0

5.0

4.75

5.25

1.8

0.4

2.5

4.0

5.0

4.75

5.25

VeeL

I VeeH I

-10

0.8

-

1.1

-10

1.1

-

0.9

1.0

I,.

::J

7.0

7.0

Vee

VCCL

VCCH

5.0

4.5

5.5

5.0

4.5

5.5

-

mAde

24

mAde

48

48

4B

mAd,

15

I-I- I

12

I - I - I"' I

n,

V,H

V,

VOH

Vo

Vmllx

Vee

J

V1HX

I

2.5

I

2.5

C

~

3

-

,

-

-

-

-

-

1
1

-

14

2'

14

1,2*

-

Pulse
Out

1

3

1

3

-I-I -I -I-I
T -1 - I - I - I - I

2.7

14

2,7

14

3,7

14

1,2,4,5,9,
10,12,13

I

I

,
,

Gnd

14

14
14

Pulse
In

I

14

2•

,,2,4,5,91
10,12,13

-

V1HX

14

2'
1

-

1

-

34

V"

1

mAde

-100

10

1

-

24

-100

2.0

1.1

1.0

-

3

24

I - I - I - I - I - I

10 ,

Vde

-

12

-2.0

Vd,

-100

I -I- I -I - I- I

-2.0

0.4

-40

15

"Since this is a non-inverting gate, power drain is minimized by tying the inputs to gates
not under test to VRH'

0.4

1.1

10

Vde

2.5

-

20
20

Vde

-1. 5

-1.5

VD

V"

I,.

!:!"

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

I

5.5

5.5

Outpul
Output Voltage

T-

O"C
+25"C
+75'C

::J

TEST CURRENT /VOLTAGE VALUES
Volts
VOH
Vmax
Vo
V'H V,

rnA

@

I
I

-

114

-

I

14

1,2,4,5,7,
9,10,12,13

MC3100/MC3000 series

QUAD 2-INPUT "NOR" GATE

MC3102F • MC3002F
MC3102L • MC3002L,P

This device consists of four 2-input NOR gates.
Each gate may be used as an inverter, or two gates
may be cross-coupled to form bistable circuits.

CIRCUIT SCHEMATIC'
1/4 OF CIRCUIT SHOWN

Vee

2.4

k

2.4

k

800

60

3

Positive Logic: 3

204----4

= "f+"2
= i"'e"2

Negative Logic: 3

Input Loading Factor::: 1
Output Loading Factor == 10
Total Power Dissipation == 122 mW typ/pkg
Gnd

Propagation Delay Time::: 6.0 ns typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vce

280

t+
7.0 ns

j . - -.........t:::::t;;=-3.0

MM06150
or Equiv
PW

50

MM07000

or E,quiv

'~ I
TPout

-1

1;~~:~2.4

.~-

= 25

pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.
The coax delays from input to scope and output to scope .must "be matched.
The scope must be terminated in 50-ohm' impedance. ihe 950-ohm resistor
and the scope termination impedance constitute a 20:1 attenuator pr'Qbe._ Coax'
shall be CT -070-50 or equivalent.
See General Information section for packaging.

V

.

_-_-_-_-~~d4 V

_~_-====--

CT

V

OV

= 50% DutV Cycle

t+ = 7.0 ns
t- = 7.0 ns

,-

7.0 ns

•

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.

~N

To complete testing, sequence through re-

s:

maining inputs.

:=D:=D9~.

10~

12~

13~

n
w
o
o

3

N

Symbol

@Test
Temperature

11

{ -55°C
MC3102
+25°C
+125°C

I

IR

Breakdown Voltage

I

BVin

Clamp Voltage

Unit
-2.0
50

Maximum Power
SUpply Current

Power Supply Drainl

I

I

I

-2.0

-2.0

I

I

50

50

I

V OH

2 4

I

2.4

ISC

-40

I -100

-40

0.4
2.4

-100

14

50

-40

0.4
2.5

-100

-40

2.5

-100

-40

1

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

lin

1.0

1.0

ID

1.1

2.0

0.4

2.4

4.0

-10

1.1

1.8

0.4

2.4

4.0

0.8

1.8

0.4

2.'

4.0

5.0

4.5

5.5

1.1

2.0

0.4

2.5

4.0

5.0

4.75

5.25

-to

1.1

1.8

0.4

2.5

4.0

5.0

4.75

5.25

0.9

1.8

0.4

2.5

'.0

5.0

4.75

5.25

7.0

7.0

Vee

VCCL

VCCH

5.0

4.5

5.5

C.

5.0

4.5

5.5

ro

2.5

-100

-40

-100

I Vee I Vee, I VeeH

Gnd

14

7'

14

2,7*

14

2,7*

14

1,2,3,7*

1,2,4,5,7,
9,10,12,13

mAde

1,2,4,5,
9,10,12,13
1,2,4,5,7,
9,10, 12, 13

Pulse
In

*Since this Is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

Vm~

mAde

mAde

I I I

I

2,7*

mAde

I

VOH

2.7*

45

I I

Vo

14

28

10

I V,H I V, I

14

28

1,3

V"

Vd,

45

lU

I

Vd,

28

1,3

10

7'

45

t pd _

lin

14

45

28

10H

Vd,

28

451

10 ,

MAde

28

14
14

tpd+

10H

20

ImAde

45

IpDH
IpDL

I

0.4

38

Parameters
Turn-Off Delay

10,

:::l
....

S"
c

Vd,

Switching
Turn-On Delay

-2.0
50

0.4

38

I

!

I

-1.5

0.4

0.4

max

-2.0

5.5

-1. 5

VOL

I

I

50

VD

Short-Circuit
Current

Power Requirements
(Total Device)

-2.0

5.5

OUlput
OUtput Voltage

O°C
+2n
+75°C

V"

TEST CURRENT !VOLTAGE VALUES
Volts
VIH V,
VOH
Vmax
Vo

mA

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

IF

Leakage Current

t

Pin
Under
Te.,

Input
Forward Current

nO

6

8

MC3002

Characteristic

s:

n
w
......
o

Pulse
Out

lU

14

2,7*

10

14

2,7*

•

MC3100/MC3000 series

QUAD 2-INPUT "OR" GATE

MC3103F • MC3003F
MC3103L • MC3003L,P

This device consists of four 2-input OR gates. This
non-inverting function is useful for optim izing logic
design, or for direct implementation of standard logic
equations.

CIRCUIT SCHEMATIC
114 OF CI RCUIT SHOWN

Vee
14

2.4 k

2.4 k

2.4 k

BOO

: = D -3

60

4
= D -6
5

1~=D-B
12=D13
11
3
Positive Logic: 3::: 1 + 2

Negative Logic: 3

= 1. 2

20-t---+
Input Loading Factor

=1

Output Loading Factor

= 10

=

Total Power DIssipation
150 rnW typ/pkg
Propagation Delay Time = 9.0 ns typ

7
Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

950
±.'1.0%

280

PULSE
GENERATOR

t- == 7.0nl

7.0 ns

i r -.......t--t-=:;--3.0 V

MMD6150
or Equiv

PRF. 1.0 MHz typ
PW = 50% Duty Cycle
t+-7.0n.

,-

t+

7.0 ns

"-=;""'-0 V
MMD7000
or Equiv

Pd+

~
tpd_

:«2.4 V

TP out

·

1.5 V

,
SO.4V

CT'''' 26 pF = total parasitic capacitance, which includes probe, wiring. and ioad

======------------~==='Gnd

capacitances.
The coax delays from input to scope and output to scope must be matched.

The scope must be terminated in 50~ohm impedance. T~e 950-oftm 'esistor
and the ICOpe termination imp!ldance constitute a 20: 1 attenua'tor probe. Coax
shall be CT -070-50 or equivalent.
.
See General I nformation section for packaging.

flf!li)

"""Wi

pz:;;;q;:;u¢

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

:=D-3
:=D-6
1~=D-8
12=D-11

,W

S

(")

w

o
~

13

MC3103

MC3003

Characteristic

I

IInput

Forward Current

Leakage Current

Breakdown Voltage
Clamp Voltage

Symbol

I

IF

1

I

MC3103 Test limits
sn
+2n
I +12n
Min Max Min Max I Min Max
-2.0

IR

1

-

BVin

1

-

Vo

1

-

VOL

3

50

Short-Circuit
Current

-

0.4

-

-

-2.0

50

-

50

-

-

-

Ise

-40

-100

-40

50
5.5

0.4

-100

-40

-

-

0.4

-100

-40

'0

V"

20

-2.0

20

-2.0

1.1

2.0

0.4

2.4

4.0

1.0

-10

1.1

1.8

0.4

2.4

4.0

0.4

2.4

4.0

5.0

4.5

5.5

2.5

4.0

5.0

4.75

5,25

20

-2.0

1.1

1.8

0.4

2.5

4.0

5.0

4.75

5.25

20

-2.0

0.9

1.8

0.4

2.5

4.0

5.0

4.75

5.25

1.0

-10

'Ol

'OH

"n

10

V"

V,H

-

-

Vdc

3

-

V,

VR

VRH

I

-

1

-

-

-

1

-

mAde

1,2*

mAdc

58

58

mAde

!V

CCH

-

~

Gnd

\

14
14

I

2,7

14

I

2,7

14

14

2'
2'

34

Vee! VCCL

,
,
,

1

-

Vmax

2'

Vdc

34

7.0

:J
C

TEST CURRENT / VOLTAGE APPLIED TO P'NS LISTED BELOW,

Vdc

-

5.5

0.4

-

-100

5.5

4.5

1.8

1

-40

4.5

5.0

2.0

Vdc

-100

5.0

0.8

/lAde

-40

VCCH

1.1

-

-100

VCCL

-2.0

50

0.4

7.0

Vee

-2.0

-

2.5

:J

!:!'.

20

I
Unit

nO

20

-

0.4
2.5

O°C
+2n
+7S"C

'OH

mAde

-1. 5

2.5

2.4

-sn
+2n
+12n

'Ol

-2.0

-2.0

-

0.4

2.4

2.4

MC3003 Test limits
+2SoC
O°C
+7SoC
Min I Max Min I Max Min Max

-2.0

-1. 5

V OH

Requirements
(Total Device)

50
5.5

Output
Output Voltage

-2.0

t
t

"n

TEST CURRENT !VOLTAGE VALUES
Volts
V,H V,
VR
VRH
Vm..

rnA

Test
Temperature
@

Pin
Under
Test

14

I

14

3,7

i Power

Maximum Power
Supply Curr¢nt

Power Supply Drain

1m ",

14

-

45

-

-

IpDH

14

-

34

34

34

34

IpDL

14

-

58

58

58

Switching
Parameters
Turn-On Delay
Turn-Off Delay

t pd _
t d+

*Since this is a non-inverting gate,
not under test to VRH

1,3
1,3

-

-

-

15

-

-

12

power drain is minimized by tying the inputs to gates

s
W
....
o

(")

-

58

45

-

mAde

-

Pulse
In
-

-

-

15

'"

12

"0

1

,

Pulse
Out
3

14

1,2,4,5,9,
10,12,13

-

-

-

-

-

-

-I - I - I - I - I

, I - I - I - I - I - I

-

T --I

1,2,4,5,9,
10,12,13

- I-I

-

I
I

.

I -- II
I

14
14

-

I

14

I

14

T

1,2,4,5,7,
9,10,12,13

MC3100/MC3000 series

QUAD 2·INPUT "NAND" GATE
(Open Collector)

MC3104F • MC3004F
MC3104L • MC3004L,P
(54HOJJ)

(74HOlJ,N)

This device consists of four 2·input NAND gates
with no output pull-up circuits, It can be used where
the Wired-OR-function is required or for driving discrete components_

CIRCUIT SCHEMATIC
1/4 OF CI RCUIT SHOWN

Vcc
14

2.4 k

800

3

2
Positive Logic: 3 = ~
Negative Logic: 3

= "'f"'+"'2

Input 'Loading Factor = 1
Output Loading Factor = 10
Total Power Dissipation"" 88 mW typ/pkg
Propagation Delay Time = 8.0 ns typ

Gnd

Pin numbers for the 54H01F174H01F device are
shown in the chart_ These devices are availab1e on

special request.

DEVICE

PIN NUMBERS

MC3104F,I./3004F,I.,P
54H01 F174H01 F

234
236

5
7

6

7
11

8
8

9
9

10 11 12 13 14
10 14 12 13
4

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

VIHX
+2.5 Vdc

TP out

Vce
t+

t-

7.0 ns

7.0 ns

280

j,.---J----f-,=,....-- 3.0 V
OV

tp~ I
PRF;;; 1.0 MHz typ
PW = 50% Dutv Cvcle
t+ = 7.0 ns

TP out

50

= 25 pF => total

parasitic capacitance •..which includes prObe, wiring, and load

capacitances.

See

~eneral

I~+:<.

2.4 V

~-

----========~~d4

t-=7.0ns

CT

--1

I nformation section for packaging_

444

V

I

•

ELECTRICAL CHARACTERISTICS

....
CtJ

gate. The other gates are tested in the same
manner. Further, test procedures are shown

,~

for only one input of the gate under test.

To

comph~te

testing, sequence through re-

s:

maining inputs.

n
CtJ
o
~

:=D-3
:=D-6

c:;O

,~=D-8
12

::J

Z.
::J
c::

-----r-\..

Cl)

'3~"
@ T.st
Temperature 1
-55"C
MC3104 \ +25"C I
+12SOC
DOC I

MC3D04 \

mA
I~.

_. 1

...

I
.... I
•• I
"I +25°C I .• I "..
2U

TESTCURRENT I VOlTAGE VALUES
Volts
I
VCEX Vm ..
V.
.. 1 V.u
V'H
1 I.• 1 v..
... , 1 v.'I

I I

I I I

I

I - I u I •. u I U., I
I'· I ... I .... I .... I
11:':1"'1'''1
.. .. .
1 - 1 u 1 •. u 1 u., 1
I .. I .. ' I ". I ... I

I

u,' 1 ,., 1 u., 1

1

+75°C

I
I

Characteristic

Symbol

Pin
Unde
Test

MC3104 Test limits
55'C I +25'C
+12SOC
I Min Max I Min I Max I Min I Max

'F

Fqrward Current
Leakage Current
Breakdown Voltage

'2.0

'R

50

I - 1- 2,0 I
I

BV in

Clamp Voltage

MC3004 Test limits
O°C
I +25'C I + 75°C
Min I Max I Min I Max I Min I Max

I

Input

50
5.5

-2.0

-2.0 1

1- 2. 0
50

50

50

I

50

5.5
-1. 5

-1.5

VD

1"-2.0

1

4.0

5.5

4.0

5.5

4.0

5.5

4.0

5.5

4.0

5.5

4.0

5.5

7.0

7.0

0..

Vee

VCCL

VCCH

!

5.0

4.5

5.5

1

5.0

4.5

5.51

5.0

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5,0

4.75

5.25

I

VIHX
2.5

2.5

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,
Unit

10L

I;"

10

V1L I V1H

V,

V,

V'H

I VCEx I V I Vee I VCCL I VCeH I
m ..

14

mAde

I

V1HX

I

Gnd
7'

t.tAdc

14

2,7 *

Vd,

14

2,7 *

Vd,

141

7'

OUtput Voltage

VOL

0.4

0.4

0.4

0.4

0.4

0.4

Yd,

14

I

7'

Output Leakage

I CEX

250

250

250

250

250

250

jJ.Adc

14

I

7'

36

36

36

36

mAde

10

10

10

10

mAde

Output

Current

Power Requirements
(Total Device)

Maximum Power
Supply Current
Power Supply Drain

_ . _ . __ L

'm=

I

14

25

IpDH

I

14

IPDL

I

14

I"
I

.. __

36
10

1

I

25

10

1,2,4,5,7,
9,10,12,13

14

mAde

!

7

1,2,4,5,
9,10,12,13 __

1,2,4,5,-7,
g, 10, 12, 13

Switching
Parameters

-

1,3

14

14

7'

1 20

14

7'

141
1,3

s:

(")

Test procedures are shown for only one

20

1

1

1

1

'" Sinee this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

MC3100/MC3000 series

TRIPLE
3-INPUT "NAND" GATE

MC3105F • MC3005F
MC3105L • MC3005L,P
(54H10J)

(74H10J,N)

This package consists of three 3-input NAND gates.
Each gate may be used as an inverter, or two gates
may be cross-coupled to form bistable circuits.

CIRCUIT SCHEMATIC
1/3 OF CI RCUIT SHOWN

Vee
14

2.4 k

800

60

1
2
13

12

Positive Logic:

12 = ~

Negative Logic~

12=~

Input Loading Factor = 1
Output Loading Factor = 10

7

Total Power Dissipation = f36 mW typ/pkg
Propagation Delay Time'" 6.0 ns typ

Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

280

\+

t-

7.0 ns

MMD6150
or Equiv

PULSE
GENERATOR
PRF = 1.0 MHz typ
PW = 50% Duty Cycle

50

t+=7.0ns
t-=7.0n$

MMD7000
or Equiv

CJ" = 25 pF =tot,1 parasitic capCJ;citance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The S50-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT ·070-50 or equivalent.

See Generel Information section for packaging.

7.0 ns

\"---J-+=~3.0

r

V

OV

tp~ --1 1~+«2.4 V
TP out
~-

_____

~====~-~-~~-c::-~~:V

I

•

ELECTRICAL CHARACTERISTICS

...o
CAl

gate. The other gates are tested in the same
manner. Further, test procedures are shown

~en

for only one input of the gate under test.
To complete testing, sequence through re-

:s:

maining inputs.

(")

~
o

~~12

en

13~

nO

~:=:[J--6

::J

::!.
::J

16~8

C

11~

'Ot

IOH

-SS0(

20

-2.0

1

+25°C

20

-2.0

+125°C

20

-2.0

aoc

20

-2.0

MC300S) +25°C
~ + 75°(

20

-2.0

20

-2.0

'oc

'OH

'ill

1.0

Symbol

Forward Current
Leakage Current

I

Clamp Voltage

Short-Circuit
Current

Power Requirements
(Tot.1 Device)
;~u~u;~;~r

Power Supply Drainl

Unit

IF

-2.0

-2.0

-2.0

-2.0

-2.0

IR

50

50

50

50

50

Turn-Off Delay

0.4

VOL

12

V OH

12

2.4

Ise

C2

-40'

Iruax

14

0.4

.,.40

I

VRH
4.0

1.1

1.8

0.4

2.4

4.0

0.8

1.8

0.4

2.4

4.0

-10

2.0

0.4

2.5

4.0

1.1

1.8

0.4

2.5

4.0

0.9

1. 8

0.4

2.5

4.0

Vma "$.
7.0

7.0

Vee

VCCL

VCCH

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.75

5,25

5.0

4.75

5.25

5.0

4.75

5,25

2.5

2.4

I

-100

I

-40

I

-100

I

-40

0.4

0.4
2.5

I -100 I

-40

20

'i.

'. I VIl I V,H I V,

v,

V'H

Vm..

VCCL

VCCH

I Vee

V1HX
2.5

2.5

2.5

I

-100

I

-40

!

Vdc

12

Vde

12

mAde

14

30

30

30

30

30

30

I mAde

14

12.6

12.6

12.6

12.6

12.6

12.6

I mAde

7'

14

2,7,13 ,.

14

2,7,13 ,.
7'

2,13

14

7'

14

7'
1,2,7,*
12,13

14

1,2,3,4,5,7,
9,10,11,13

14
1,2,3,4,5,
9,10,11,13

14
1,2,3,4,5,7,
9,10,11,13

14

Pulse
'n

Gnd

2,13

I -100 I mAde

20

V1HX

14

14

Vdc

IPDL

tpd+

VR
2.4

/lAde

IpDH

*Since this is an inverting gate,

VF
0.4

Vdo

0.4

0.4

2.4

I -100 I

50

-1.5

-1. 5

Vo

tpd_

V1H
2.0

2,13

-2.0 I mAde

5.5

5.5

BVin

Switching
Paramefers
TUrn-On Delay

-10

V1L
1.1

TEST CURRENT / VOLTAGE APPLIED TO P'NS LISTED BELOW,

U;e~r ~::-'T-:'=----+-C::-'Tc'c-+-c::-,-r:-~

Output
OJtput Voltage

ID

1.1
1.0

Pin
Characteristic

a.

Volts

mA

@Test
Temperature

~

'nput

CD

TEST CURRENT/VOLTAGE VALUES

MC310S

Breakdown Voltage

:s:

(")

Test procedures are shown for only one

Pulse
Out

1,12

10

10

12

14

2,13

7'

1,12

10

10

12

14

2,13

7'

power drain is minimized by grounding the inputs to gates not under test.

MC3100/MC3000 series

TRIPLE 3-1 NPUT "AND" GATE

I

MC3106F • MC3006F
MC3106L • MC3006L,P
(74Hl1J,N)

(54H11 J)

This device consiSts of three 3-input AND gates.
This non-inverting function is useful for optimizing
logic design, or for direct implementation of standard
logic equations.

CIRCUIT SCHEMATIC
1/3 OF CIRCUIT SHOWN

Vcc
14

2.4 k

2.4 k

800

60

1
2
13

12
Positive Logic: 12"" 1 • 2 .13
Negative Logic: 12 = 1 +2+13

Input Loading Factor = 1
Output Loading Factor ... 10
Total Power Orssipation ""' 84 mW tvp/pkg

7

Gnd

Propagation Delay Time

=9.0 05 typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc

280
t+

t-

7.0 ns

1.0 ns

r--t=t:an.z-3.O V

MMD6150

or Equiv

OV
PRF'" 1.0 MHz typ
PW ~ 50% Duty Cvcle
t+ = 7.0ns
t- 7'

MMD7000
or Equiv

50

7.0 nl

tpd~.
tpd+~2.4V
TPout .

1.5 V

'

---SO.4V

-------------------Gnd
CT

= 25 pF =total parasitic capacitance, which i"ctudes probe, wiring, and loa~

capacitancss.

to

The ·coax delays from input to ~op. and output
scope mut.t b. matChed.
The scope must be terminated in 50·ohm impedance. The 950.-ohm resistor

and the lCopa:termination impedance constitute a 20: 1 attenuator probe. Coax
.nall· be CT-0'70-50 or equivalent.
See.Gene,al lnformation section for paC:kaging.

.,ft.

" " ' " U;P:;;;M

•

ELECTRICAL CHARACTERISTICS

s

(')

...o

Test procedures are shown for only one

W

gate. The other gates are tested in the same
manner. Further. test procedures are shown

,~

for only one input of the gate under test.

To complete testing, sequence through remaining inputs

13~==C)--12

@ Test
Temperature

~==C)--6

{ -SS'C
MC3l06 +2S'C
+l2S'C

111~==C)--8

{

MC3006

Characteristic
Input
Forward Current
Leakage Current
Breakdown Voltage
Clamp Voltage

Symbol
IF

MC3l06 Test-limits
MC3006 Test limits
Pin
+2S'C
SS'C
+l2S'C
+2S'C
+7S'C
O'C
Under
Test Min Max Min Max Min Max Min Max Min Max Min Max Unit
1

-

-2.0

-

Short-Circuit
Current

Power Supply Drain

-

-2.0

-

-2.0

-

50

-

50

-

-

-

-

5.5

Turn-Off Delay

20

-2.0

-

20

-2.0

1.0

-10

1.1

1.8

0.4

2.4

4.0

7.0

5.0

4.5

5.5

20

-2.0

-

-

0.8

1.8

0.4

2.4

4.0

-

5.0

4.5

5.5

20

-2.0

-

1.1

2.0

0.4

2.5

4.0

-

5.0

4.75

5.25

20

-2.0

1.0

-10

1.1

1.8

0.4

2.5

4.0

7.0

5.0

4.75

5.25 2.5

20

-2.0

-

0.9

1.8

0.4

2.5

4.0

-

5.0

4.75

5.25

lin

lin

ID

Vil

V'H

V,

V.

V. H

-

-

-

-

-

1

-

2,13*

-

f.lAde

-

-

-

-

-

-

-

1

*

-

Vdc

-

-

1

-

-

-

-

-

*

50

-

50

-

-2.0 mAde

::J

~.

::J

-

c:

(1)

a.

-

Vmax VCC VCCl VCCH V'HX

10H

-

-

Gnd

14

7

-

14

2,7,13

-

14

-

2,7.13

-

1

-

50

-

50

1

-

-

5.5

-

VD

1

-

-

-1. 5

-

-

-

-

-

-1. 5

-

-

Vdc

-

-

-

1

-

-

-

-

*

-

-

14

-

-

7

VOL

12

0.4

-

0.4

-

0.4

-

0.4

-

0.4

-

0.4

Vdc

12

-

-

-

1

-

-

-

2,13*

-

-

14

-

-

7

-

2.4

-

2.4

-

2.5

-

2.5

-

2.5

-

Vdc

12

-

-

-

1

-

-

2,13*

-

-

14

-

-

7

-

-

-

-

-

-

-

-

1,2,13*

-

-

-

14

-

7,12

VOH

12

2.4

ISC

12

-40

Imax

14

-

-

-

28

-

-

-

-

-

28

-

-

mAde

-

-

-

-

-

-

-

-

1,2,3,4,5,
9,10,11,13

14

-

-

-

-

7

IpDH

14

-

20

-

20

-

20

-

20

-

20

-

20

mAde

-

-

-

-

-

-

-

-

-

-

-

14

-

7

IpDL

14

-

1,2,3,4,5,
9,10,11,13

40

-

40

-

40

-

40

-

40

-

40

mAde

-

-

-

-

-

-

-

-

-

-

-

14

-

1,2,3,4,5,7,
9,10,11,13

Pulse
In

Pulse
Out

-

*

-

14

-

-

2,13

7

*

-

14

-

2,13

7

-100 -40

-100 -40

-100 -40

-100 -40

-100 -40

-100 mAde

t pd _

1,12

-

-

-

15

-

-

-

-

-

15

tpd+

1,12

-

-

-

12

-

-

-

-

-

12

- - '----- - - -

- - - --

-

ns

1

12

-

-

-

-

-

ns

1

12

-

-

-

-

--

---

-

*Since this is a non-inverting gate, power drain is minimized by tying the inputs to gates not under test to VRHo

-

-

S
w
o
o0)
(')

n-O

2.5

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BElOW:
10l

-2.0

Switching
Parameters
Turn-On Delay

10H

IR

Power Requirements
(Total Device)
Maximum Power
Supply Current

-2.0

10l

BV in

OUtput
Output Voltage

O'C
+2S'C
+7S'C

rnA

!

TEST CURRENT! VOLTAGE VALUES
Volts
V.H Vmax Vcc VCCl VCCH V'HX
ID Vil V'H V, V.
5.0 4.5
5.5
4.0
- 1.1 2.0 0.4 2.4

MC3100/MC3000 series

TRIPLE 3-INPUT "NAND"GATE
(Open Collector)

I

MC3107F • MC3007F
MC3107L • MC3007L,P

This device consists of three 3-input NAND gates
with no output pull-up circuits_ It can be used where
the Wired-OR function is required or for driving discrete components.

CIRCUIT SCHEMATIC
1/3 OF CIRCUIT SHOWN

Vee
14

800

12

2

13o---f-H

Positive Logic:

12"'~

Negative Logic:

12=~

Input Loading Factor

=1

Output Loading Factor == 10

= 66 mW typ/pkg
Propagation Delay Time = 8.0 ns typ

Total Power Dissipation

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

V,HX
+2.5 Vdc

TP out

Vee
t+
7.0 ns

t7.0 ns

280

Jr---.J-+c=c--3.0 V
OV

PULSE
GENERATOR
PRF

= 1.0 MHz

CT = 25 pF

tp~ I -t I~~.

typ

PW == 50% Duty Cycle
t+ :: 7.0 ns
t- == 7.0 ns

= total

TP out

50

2.4 V

~-'

----====-=-=-=-=-~~d4

V

parasitic capacitance. which includes probe, wiring, and load

capacitances.

See General I nformation section for packaging.

,*""

ZW*" #A#44

;::.,...

ELECTRICAL CHARACTERISTICS

3:

Test procedures are shown for only one
gate. The other gates are tested in the same

....
o

(')

Co)

manner. Further, test procedures are shown

.......

for' only one input of the gate under 'test.
To complete testing, sequence through re·

s:

maining inputs.

(')

~

~~

13~

o
.....

12

0o

~==C:?-6

....

:J

:i"
c

1&~.-.- 8
'l~

CD

@Test
Temperature

t
MC3107

-SS'(
+2S'(
+125'(

M(3007

Characteristic

I

Symbol

Pin
Under
Test

MC3107 Test limits
55'( I +25'C
+ 125'(
Min I Max I Min I Ma.JMin I Max

.1

t

MC3007 Test Limits
O'C
I +2S'C I +7S'C
Min I Max I Min I Max I Min-.lMax

Input
Forward Current
Leakage Current
Breakdown Voltage

Clamp Voltage

IF

-2.0

-2.0

-2.0

-2.0

-2.0

-2.0

'R

50

50

50

50

50

50

BVin
Vn

Oltput Voltage
Output Leakage
CUrrent

VOL

12

0.'

0.'

0.,

0.'

0.'

0.'

I CEX

12

250

250

250

250

250

250

1max

14

IpDH

14

28

28

28

28

2B

IpDL

14

13.5

13.5

13.5

13.5

13.5

'pd'pd.

1,12

Power Requirements
(TOIalllevice)
Maximum Power

Supply Current
Power Supply Drain

,0

20

Swilching

Parameters
Turn-On Delay
Turn-Off Delay

20

1,12

20

"Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

1.0

-10

20
20
20

1.0

-10

20

V"

V,H

1.1

2.0

1.1
0.8

0.'

2.'

'.0

5.5

1.8

0.'

2.'

'.0

5.5

1.8

0.'

2.0

0.'

'.0
'.0

5.5

1.1

2.'
2.5

1.1

1.8

0.'

2.5

'.0

5.5

'.0

5.5

0.'

1.8

0.'

2.5

7.0

5.5
7.0

Vee

VCCL

VCCH

5.0

'.5

5.5

5.0

'.5

5.5

5.0
5.0

'.5
4.75

5.5
5.25

5.0

4.75

5.25

5.0

4.7!)

5.25

VCCL

VCCH

14
20

Vii.
2.5

2.5

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,
Unit

I

10L

I..

I.

V"

V,H

I V,

V.

V.H

VCEX

I V~X I Vcc

2,13

mAde

2,13
2,13

V1HX

12

14

2,7,13*

14

2,7.13*

14

7"

14

7"

14

7"

1,2,3,4,5,7,
91'10,11,13

14

mAde

Gnd
7"

14

j!Adc

14

1,2,3,4,5,
9,10,11, 13

1,2,3,4,5,7,
9,10,11,13

14

Pulse
In
14

I.

Vde

-1.5

-1.5

lin

20

Q;

Vde

5.5

5.5

Output

0'(
+25'(
+75'(

mA
10L

TEST ruRRENT I VOLTAGE VALUES
Volts
VRH
V,
VeEX Vm1x
V.

I Pulse
Out
12

14

2,13

7"

12

14

2,13

7"

1L~

HEX INVERTER

______________

~_r_ie_s~

M_C_3_1_00_I_M_C_3_0_00__

MC3108F • MC3008F
MC3108L • MC3008L,P
(54H04J)

(74H04J,N)

This device offers six independent inverting gates
in a single package. Each gate consists of a single input
driving an output inverter.

CIRCUIT SCHEMATIC
116 OF CIRCUIT SHOWN

Vcc
14

2.S k

1-{>o-2

7S0

3-{>o-4

5S

5-{>o-S
9-{>o-S
2
11-{>o-10
13-{>o-12
Positive Logic: 2:;::

'1

Input Loading Factor == 1
Output Loading Factor = 10

Gnd

Total Power Dissipation == 140 typ/pkg
Propagation Delay Time"" 6 ns typ

Pin numbers for the 54HQ4F/74H04F device are
shown in the chart. These devices are available on
special request.

DEVICE
MC310SF,Ll300SF,L,P
54H04F174H04F

1
10

11
9

12 13
12 13

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc

,+

7.0 ns

,-

7.0 ns

i.---......H--;::;=-3.0 V

MMDS150
or Equiv

OV
t+ = 7.0 ns
t- ..,

50

7.0 os

MMD7000

,p~'pd+

,"2.4 V

or Equiv
TP out

1.5 V

______________

~-_-_-_-~~:V

CT

= 25 pF;. total par4~itic capacitance, which includes probe, wiring, and

load

capacitances.
The coax delays from input to scope and qutput to scope must be matched.
The- scope must be termi_nated in 50-ohm impedance. ihe 950·oh m resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General Information section for packaging.

14
14

I

•

ELECTRICAL CHARACTERISTICS

S

0

Co\)

Test procedures are shown for only one

-a

inverter. The other inverters are tested in

0

the same manner.

~oo

S
0

1--{»-2
3

Co\)

0
0

-------{>-- 4

00

5 -----{>o-- 6

00

9 -----{>o-- 8

V"

TEST CURRENT /VOLTAGE VALUES
Volts
VR
VR•
VJn1i.":
V,. V,

L.1

2.0

0.4

2.4

4.0

L.1

L.8

0.4

2.4

4.0

0.8

1.8

0.4

2.4

4.0

L.1

2.0

0.4

2.5

4.,0

L.1

1.8

0.4

2.5

4.0

0.0

L.8

0.4

2.5

4.0

11 -----{>o--10

Test
Temperature

t
t

-55°C
MC3108 +2SOC
+125°C
MC3008

Characteristic

IInput

Forward Current

Leakage Current
Breakdown Voltal«!
Clamp Voltage

l°utput
OUtput Voltage

Short-Circuit
Current

I

Symbol

I

Pin
Under
Test

I

MC3108 Test Limits
55°C
+25°C
I +12SOC
Min Max Min Max I Min Max

'F
'R

'se

Maximum Power
Supply Current

'm",

Power Supply Drain

IpDH

Delay

Turn-a;£! Delay

-2.0

20

-2.0

20

-2.0

20

-2.0

L.O

L.O

-10

-10

Unit

10L

10•

lin

10

V"

V,.

V,

5.5

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

~

VR

VRH

Vmu

Vee

t I

I.

VCCL _ VCCH

Gnd
7'

50

50

50

50

50

50

.uAdc

14

7'

Vde

14,

7'

5.5

0.4

0.'
2.4

-100

-1.5

-40

-100

0.4

Vde

0.4

2.4

2.5

-40

-40

37.5

0.4

-100

-40

-100

37.5

'pd+

10

10

'I - I -I - I - I - I

1,2

10

10

2

58

58

58

mAde

26

26

26

26

26

26

mAde

11,13

Pulse
In

power drain Is minimized by grounding the inputs to gates not under test.

7'
7'

Pulse
Out

I-I - I - I - I- I

I
I

1,2,7*

1,3,5,7,9
11,13

1,3,5,9,

',2

58

I.
14

m.Ade

58

7'

14

mAde

58

14

14

Vde
Vdc

2.5

I.

* Since this is an inverting gate,

Vcc•

4.5

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

IpDL

'pd-

'.0

VCCL

5.0

mAde

14
14

7.0

Vee

-2.0

Switching
Parameters
Turn~On

-2.0

20

10

-2.0

0.'

-40

20

lin

0

-2.0

-1.5

2.4

~2.

-2.0

5.5

VOL

10•

20

-2.0

VD

Wower Requirements
(Total Device)

MC3008 Test limits
O°C
+25°C
+WC
Min Max Min Max Min Max

O°C
+2SOC
+75°C

10L

~.

::J

C

-2.0

BVin

VOH

mA

@

13 -----{>o--12

::J

I'

7

!4

1,3,5,7,9
11,13

I II II I J
I
I
I
14
14

7'

7'

HEX INVERTER

MC3100/MC3000 series

"

\.----------'

MC3109F • MC3009F
MC3109L • MC3009L,P
(74H05J,N)

(S4HOSJ)

. This device consists of six independent inverting
gates with no output pullup circuits. It can be used
where the Wired·OR function is required, or for driving
discrete components.

CIRCUIT SCHEMATIC
1/6 OF CIRCUIT SHOWN

Vcc
14
1---{)--2
2.S k

760

3---{)--4

5---{)--6
9---{)--S

2

11 - - - { ) - - 1 0
13 - - - { ) - - 12
470
Positive Logic; 2 =

Input Loading Factor

Gnd

'1

=1

Output Loading Factor = 10
Total Power Dissipation = 90 mW typ/pkg
Propagation Delay Time = B ns typ

Pin numbers for the 54H05F174H05F device are
shown in the chart. These devices are available on
special request.

DEVICE
MC3109F)../3009F,L,P
54H05F174H05F

PIN NUMBERS
2
14

3
3

4
2

5
5

6
6

7
11

8
8

9
7

10 11
10 9

12
12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc

TP out

,+

7.0 ns

,-

7.0 ns

280

1r--_.H-;;;=-3.0 V
OV

'pd~'Pd+"'2'4 V

PRF = 1.0 MHz typ
PW = 50% Duty Cycle

t+=7.0ns
= 7.0 ns

TPout

50

1.5 V

---SO.4V

-------------------Gnd

t-

CT "" 25 pF = total parasitic capacitance, w,hich includes probe. wiring, and load

capacitances.

See General I nformation section for packaging.

.

.........

A ,1if4!4

I

•

ELECTRICAL CHARACTERISTICS

3:
o
w

....

Test procedures are shown for only one
inverter. The other inverters are tested in
the same manner.

JS

3:

o

1---[>0--2
3---[>0--4

~
ocg

5 -----{:>- 6

8::J
....
;5'

9 -----{:>- 8
11 -----{:>-10
13 -----{:>-12

MC3109

Characteristic

J

Symbol

I

IInput

Forward Current

Leakage Current
Breakdown Voltage
Clamp Voltage

IF

1

1R

1

-

50

-

50

-

BVin

1

-

-

5.5

-

1

-

-

-

Vo

Output
Output Voltage

Output Leakage
Current

VOL

I

2

ICEX

I

2

Power Requirements
(Tolal Device)
Maximum Power

Supply Current

Power Supply Drain

MC3109 Tesl Limils
SS'C I +2S'C
+12S'C
Min Max I Min Max Min I Max

Pin
Under
Test

'max

I.

IpDH

l4

'PDL

l4

-2.0

Turn-Off Delay

'pd-

1,2

tpd+

',2

-1.5

5.

-

-2.0

- -.

-

-

5.5

-

-

-

-

-

-

-1.5

-

-2.0

50

-

-2.0

50

0.'

I

* Since this is an inverting gate, power drain

-

1 250 I

-

-

58

-

58

28

-

26

-

-

0.4

1 250 I

-

1 250 I

-

1 25. I

37.5

-

-

-

-

37.5

58

58

58

28

-

2.

15

'8

-

-

-

-

is minimized by grounding the inputs to gates not under test.

-

-

-

1 250 I

2.
15

18

-

-

1.1

2.0

0.'

2.'

'.0

5.5

1.0

-10

1.1

1.8

0.'

2.'

'.0

5.5

20
20

c:

7.0

Vee

VCCL

VCCH

5.0

'.5

5.5

5.0

'.5

5.5

1.8

0.'

2.'

'.0

5.5

5.0

'.5

5.5

O'C
+2S'C
+7S'C

2.

1.1

2.0

0.'

2.5

'.0

5.5

5.0

4.75

5.25

1.1

1.8

0.'

2.5

5.0

4.75

5.25

0.•

1.8

0.'

2.5

5.0

4.75

5.25

I Vee,

I VeeH

-10

1.0

20
20

I

I

I Unit
mAde

50

/.LAde

-

lin

-

Vde

-

mAde

58

mAde

2.

mAde

,

V"

-

-

-

-

-

I

I

-

I - I

1

-

-

-

-

-

-

Pulse
In

Pulse
Out

-

ns

1

2

".0

1

2

V,

V.

1

-

-

1

I

-

V,H

-

I

I.

1

Vde

Vde

...

7.0

5.5
5.5

'.0

~

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,

10..

1 200 I "Ade I

-

V"

V,H

0.8

-2.0

0.'

I.

20

t

MC3009 Test Limits
O'C
+2S'C I +7S'C
Min Max Min Max I Min Max

lin

+12S'C

I - I •.• I - I •.• I - I··' I - I I - I I - I I

Switching
Paramete('S
Turn-On Delay

-2,0

10'

t -SS'C
+2S'C

MC3009

TEST CURRENT / VOlTAGE VALUES
Volts
V,
V.
V.H
VeE>( Vml•

RIA

@Test
Temperature

I - I

-

-

-

1

I- I

-

-

-

I

I

I

-

J

-

J

-

J

-

J

-

-

-

-

I
I

-

- 1 - 1 -I - 1
J

Vm1x

-

-

-

-

VeE)(

Vee

-

-

1

-

V.H

I

-

I

-

-

1,3,5,7,
9,11,13

-

1
J

2

-

-

14

I

-

I

I

I.

I

I

-

I

I

I.

I

14

-

1 -

1

J

J

-

-

-

1

14

J

14 J

1

I

Gnd

14'

7'

14

7'

I.

7'

-

7'

I

7'

-

I

7'

-

I

ITS,5,7,
9,11,13

14

1411,g.5,7,
9,11,13

7'

1

1

I

I

7'

MC3100/MC3000 series

DUAL 4-INPUT "NAND" GATE

I

MC3110F • MC3010F
MC3110L • MC3010L,P
(54H20J)

(74H20J,N)

This device consists of two 4-input NAND gates.
These gates may be cross-coupled to form a set-reset
flip-flop.

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

2.4 k

60

800

~==r=}-6

li==r=)-8

1
2

6

4

5o-t+-H

Positive Logic: 6::::;~
Negative Logic: 6 = 1 + 2 + 4 + 5

Input Loading Factor = ,
Output Loading Factor = 10
Total Power Dissipation = 44 mW typ!pkg
Propagation Delay Time'" 6.0 ns typ

Gnd

Pin numbers for the 54H20F174H20F device are

DEVICE

shown in the chart. These devices are available on
special request.

MC3110F,L/3010F,L,P
54H20F174H20F

PIN NUMBERS
2
12

3

3

4

5

13 14

6

2

8
9
11 10 '6

10 11
7 14

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.5 Vdc

Vcc

280
t+

7.0 ns

,-

7.0 ns

TP out
~--...f-!-::=-3.0 V

MMD6150
or Equiv

OV

PRF =1.0 MHz typ
PW = 50% Duty Cycle
t+=7.0n.
t-=7.0nl

t~ I

MMD7000

50

or e"quiv

-i

1~+"2.4

~---..:.
_______-_-_-_-

TPout

:--~~d4

V

V

CT == 25 pF = total parasitic capacitance, which iricludes probe, wrring, and load

capacitances.
The COBX delays from input to scope and o~tput to scope must be matched.
The sc·ope must be terminated in 50-ohm impedance.· The 9SO-ohm resistor
and the scope termination impedance consti,tute a 20; 1 attenuator probe. Coax
shall. be CT -070-50 or equivalent.
See General I nformation section for packaging.

,.ii'

Ii

/RiU;.

'"

..... $Z;:p:;;;

,.

\ i

G4,J •. ;;

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

s:
(")
W
.....

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

.....

~O

s:
n

maining inputs.

~
.....

i==3 }-a
li==r:=}-a

o

n-O
:::l

!:!,
:::l

C

~

Pin
u'nder
Test

Symbol

Characteristic
Input

...., ...............

Forward Current

'F

-2.0

Leakage Current

'R

50

Breakdown Voltage
Clamp Voltage

I

BVin

-2.0
50

Max

I Min I Max

-2.0

-2.0

I

50

50

I

5.5

Unit

-2.0

-2.0

mAde

50

50

!-lAde

',.

10

VIL

I

V'H

..................... ,

V,

V.

Vm ..

V'H

VCCH

VCCl

Vee

2,4,5

Vde

5.5

-1.5

Vn

10L

Max

Min

10H

-1.5

V1HX

Gnd

14

"

14

2,4,5,7*

14

2,4,5,7*

14

Vdc

,'

Output
Output Voltage

Short-Circuit
Current

0.4

VOL
VOH

2.4

'se

-40

0.4

0.4

2.4
-100

-40

2.4

-100

-40

-100

0.4

0.4
2.5

-40

2.5
-100

-40

0.4
2.5

-100

-40

Vde
Vdc

-100

2,4,5

14

2,4,5

14

"
1,2,4,5,6,7

14

mAde

Power Requirements

(Total Dev;ce)

Maximum Power
Supply Current

Imax

14

Power Supply Drain

IpDH

14

20

20

20

20

20

20

mAde

IpDL

14

8.4

B.4

B.4

8.4

8.4

8.4

mAde

12;,5

Switching

Parameters
Turn-On Delay

t pct_

I

1,6

I-I

TUrn-Off Delay

tpd+

I

1,6

1 _ 1

* Since this

I

I
1 - 1

10
10

1

I- I -I - I- I

10

1

1 -

10

1 - I _ I _ I

is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

I - I - I '"
0"

1,2,4,5,7,
9,10,12,13

14

mAde

12,5

1,2,4,5,
9,10,12,13

Pulse
In

r
-I ,

Pulse
Out
-I

I

, I

_I

- 1 - 1 - 1 -

_-r

_-I

1

- 1 -I

1

1

1

I

I

14

I

I

14

I

I
I

14

7

14

1,2,4,5,7,
9,10,12,13

I

2,4.5

I

1

2,4,5

1

"
"

MC3100/MC3000 series

I

OUAl4-INPUT "ANO" GATE

MC3111F • MC3011F
MC31n L • MC30n L P
(54H21J)

(74H21J,N)'

This device consists of two 4-input AND gates.
This non-inverting function is useful for" optimizing
logic design, or for direct implementation of standard
logic equations.

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

2.4 k

2.4 k

800

60

1

2
4

6

Positive Logic: 6 = 1 .2.4.5
Negative Logic: 6 == 1 +2 +4 +5

So-+t-+-+

J nput

Loading Factor"" 1

Output Loading Factor == 10
Total Power Dissipation = 56 mW typ/pkg
Propagation Delay Time == 9.0 ns typ

7

Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX

Vcc

+2.5 Vdc

Coax

9S0
±'1.0%

280

TP out

t- :::

t-

7.0 ns

1..---","-1--:-::--- 3.0

V

MM061S0
or Equiv

PULSE
GENERATOR
PRF = 1.0 MHz typ
PW = 50%' Duty Cycle
t+ = 7.0 ns

t+

7.0 ns,

"--;";;;";';;"'-0 V

so

MM07000
or Equiv

, . . . - -...-,---~2.4 V

7.0 ns
~0.4 V

--------------Gnd
CT

= 25 pF =total

parasitic capacitance, which includes probe, wiring. and load

capacitancM.

The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General Information section for packaging.

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

.....
.....

gate. The other gate is tested in the same
manner. Further. test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

.....
:s:
o
~
.....
.....
nO

mainjng inputs.

~=3 ~}-6

1~~ 8
12

:::l

13

~

MC3111

MC3011

Symbol

Characteristic
Input
Forward Current
Leakage

Curre~

Breakdown Voltage
Clamp Voltage'

I

Short-Circuit
Current

-2.0

IR

50

Power SUpply Drain

-2.0

-2.0

50

50

50

-

I -

-2.0

20

-2.0

O°C
+2SoC
+7SoC

20

-2.0

'0

-Z.O

20.

-Z.O

Unit

ICOL

10•

VOL

6

-

0.'

0.'

0.'

-

2.'

-

-

6

2.'

-

2.'

-

2.5

-

2.5

I.e

6

-.0

-100

-40

-100

-40

-100

-40

-100

-40

Imax

14

18

-

IpDH

14

13.2

-

13.2

13.2

IPOL

14

26

-

26

26

0.'

-

-2.0

-2.0

mAde

50

50

J.l.Adc

Turn-On Delay

t pd_

I

TUrn-Off Delay

'pd+

I

0.'

0.'

-100

-40

-

-100

18

13.2

13.2

26

26

26

1.0

-10

0

VCCH

1.1

2.0

0.'

2.'

'.0

5.0

'.5

5.5

1.1

1.8

0.'

2.'

'.0

5.0

'.5

5.5

0.8

1.8

0.'

2.'

'.0

5.0

'.5

5.5

1.0

-10

1.1

2.0

0.'

2.5

'.0

5.0

4.75

5.2!>

1.1

1.8

0.'

2.5

'.0

5.0

4.75

5.25

0.'

1.8

0.'

2.5

'.0

5.0

4.75

5.25

CD

Co

7.0

7.0

6

-

mAde

-

-

mAde

-

-

~Adc

-

I - I - I - I

IS

I - I - I

6

-

I - I - I- I I-I- I -I - I- I I-I- I
12

V1HX
2.5

I

2.5

lin

10

VOL

V'H

V,

V,

V,.

V",...

Vee

I V IV
CCL

n.
no

V1HX

CCH

14

I

1 1

Goo

2 • 4 • 5,7

14

1

~ 2,4,5,7

I'

I

I

1

1:,2,4,5,7,
9,10,12,13

I.

mAde

1,6

*S:I.nce this is a non-inverting gate, power drain is minimized by tying the inputs to gates not under test to VRH

VCCL

14

Vd,

-

I - I - I - I - I - I

Vee

2,4,5*

Vd,

2.5

13.2

15

VOL

Vd,

1,6

12

10

Vd,

Switching

Parameters

I..

c

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

-1.5

VOH

-

~2.

20

5.5

-1.5

VD

20

I

-2.01

10H

-SSoC
+2SoC
+12SoC

MC3011 Test Limits
+7SoC
O°C
+2SoC
Min I Max I Min Max Min I Max

5.5

BVin

Power Requirements
(Total Device)
Maximum Power
SUpply Current

I

IF

Output
OUtput Voltage

MC3111 Test Limits
SSoC
+2SoC
I + 12SoC
Min I Max I Min I Max I Min I Max

t
t

10L

:;-

TEST CURRENT/VOLTAGE VALUES
Volts
V,
Vm ••
V'H V,
V'H

rnA

@Test
Temperature

Pill
Under
Test

:s:

o
Co.)

f

Pul..
Out

1

6

1

-

,

-

1

- J -\

2,4,5*

-

-

-

-

.
.

6,7

14

1,2,4,5,
9,10,12,13
1,2,4,5,
9,10,12,13

-I -I -I - 1- 1
1
-I - T - T - T

I - I - I

14

- I - I 14
- I - I - I

2,4,5'"

1

1,2,4,5*

.

Pul..
In

r

-

-

1

-

1

-I

I'

-

1

.

1

-

I4

1

1 - 1 14 1 - 1
I

-

114

I

-

I

-1
I

2,4,5
2,4,5

MC3100/MC3000 series

DUAL 4-1 NPUT "NAND" GATE
(Open Collector)

MC3112F • MC3012F
MC3112L • MC3012L,P
(54H22J)

(74H22J,N)

This device consists of two 4·input NAND gates
with no output pull·up circuits. It can be used where
the Wired·OR function is required or for driving discrete components.

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

2

4O--i-i-4
5o--i-i-i-4

Positive Logic: 6 = ~
Negative Logic: 6 = 1 + 2 + 4 + 5

470
Input Loading Factor = 1
Output Loading Factor = 10
Total Power Dissipation = 44 mW typ/pkg
Propagation Delay Time = 8.0 ns typ

Gnd

7

Pin numbers for the 54H22F174H22F device are
shown in the chart. These devices are available on
special request.

DEVICE
MC3112F,L/3012F,L,P
54H22F174H22F

PIN NUMBERS
2
12

3

3

4
5
13 14

6

2

8
11 to

9
6

10 11 12 13
7
14 8
9

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

VIHX
+2.5 Vdc

TP out

Vcc
t+
7.0 ns

,-

7.0 ns

280
if---,j-+c=c;-3.0 V

OV
PULSE

'~pdtpd+

GENERATOR

:i!:2.4 V

PRF

~

1.0 MHz ,yp

PW = 50% Dutv Cycle
t+=7.0n5
t- = 1.0 ns

Cj = 25 pF

= total

TPout

50

1.5 V

,

___-====---_-:"'-:'-=---':'~~d4 V

parasitic capacitance, which includes,probe. wiring~ and load

capacitan~es.

See General Information" Section for packaging.

• ,0

..

.,"'i( 'IQP.W·',

I

•

ELECTRICAL CHARACTERISTICS

s:
....
....

("')

Test procedures are shown for only one

(,J

gate. The other gate is tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

•N

s:
("')

maining inputs.

(,J

~==i

o
.....

»-6

N

0o
::J
.....
S'

16~ 8

12
13

Test
Temperature

mA

@

MC3112

t

MC3012

Characteristic

_1

Symbol

I

Pin
Under
Test

I

MC3112 Test limits
+125'C
55°C I +25'C
Min I Max Min Max Min Max

-S5°C
+25°C
+1 25°C

t

MC3012 Test limits
+75°C
I +25°C
Max I Min Max Min Max

O°C
+25'C
+75"C

10L

lio

ID

20
20

1.0

-10

20
20
20

1.0

-10

20

Vecl

VCCH

5.0

4.5

5.5

V"

V,H

V,

1.1

2.0

0.4

2.4

4.0

5.5

1.1

1.8

0.4

2.4

4.0

5.5

0.8

1.8

0.4

2.4

4.0

5.5

1.1

2.0

0.4

2.5

4.0

5.5

1.1

1.8

0.4

2.5

4.0

5.5

0.8

1.8

0.4

2.5

4.0

5.5

Leakage Current
Breakdown Voltage

Clamp Voltage

IF

1

-2.0
50

IR

1

BV in

I

VD

1

Output
Output Voltage

VOL

Output Leakage
Current

leEX

Power Requirements
(Total Devite)
Maximum Power
Supply Current

I

Power Supply Drainl

I
I

6

-

-2.0
50

Min

-

-2.0

-2.0

50

50

-

5.5

5.5

-

-1. 5

Turn-Off Delay

Unit

-

-2.0

mAde

50

50

/lAde

-

-

Vdc

-1.5

10L

lio

ID

V"

V,H

V,

V,

-

5.5

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

-

0.4

0.4

D.4

0.4

0.4

0.4

Vdo

250

250

250

250

250

250

pAdo

IpDH

20

20

20

20

20

20

mAde

IpDL

14

5.0

5.0

5.0

5.0

5.0

5.0

mAde

12.5

14

14

1,6

20

20

,. Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

Vee

Vecl

\

2.5

VCCH

I

V1HX

Gnd

14

2,4,5,7*

14

2,4,5,7"

14

I

I

1

12,4,51

-

1

-

2,4,5

I
I

1

6

I

I

I

14

I

I

I

I

I

I

14

I

I

I

-I -I -I-I

I

T

"
1,2,4,5,7,
9,10,12,13

14

1

1,2,4,5,7,
9,10,12, 13

141

• I - I - I - I - I

7'

!

14

1,2,4,5,
9,10,12,13

Pulse
Out

I

7'

-

1

1

6

Pulse
In
1,6

2.5

14

mAde

14

12.5

Vm ..

-

I -I I -I I - I I - I I - I I - I I I I - I-I -I I- I
I -I I - I I - I I - I I - I I - I I I - I - I -I

14

tpd+

4.5

2,4,5

-

-

VCEX

V'H

I

Vdo

'max

tpd_

7.0

5.0
5.0

V1HX

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,

-2.0

Switching
Parameters
Turn-On Delay

7.0

CD
0.

DoC

Input
Forward Current

c

TEST CURRENT !VOLTAGE VALUES
Volts
V,
Vee
VCE'X Vm..
V'H

I -I

I I

I - I

14

14

I

I

II

I

2,4,5

I

I

2,4.5

I

"
7•

MC3100/MC3000 series

B-INPUT "NAND" GATE

MC3115F • MC3015F
MC3115L • MC3015L,P

This device is an a-input NAND gate. It is useful
when processing a large number of variables, such as
in encoders and decoders.

Vee
14

2.4 k

800

60

1
2
3

j~8

11
12
13

8

4o-l-+-H
10o-+-IH-+-..

Positive Logic:

Ilo-t-I-++-H

o-:j::;t:I:U4:tJ

8

12
130-

, . 2 . 3 . 4 .'0 .,1 • 12 • 13

Negative Logic:
8

=1 + 2 + 3 + 4

+ 10 + 11 + 12 + 13

Input Loading Factor"" 1

7

Output Loading Factor = 10
Total Power Dissipation = 22 mW typ/pkg

Gnd

Propagation Delay Time

= 8.0 ns typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.5 Vdc

Vee

280
t+
1.0 ns

t-

7.0 ns

ir---.lr-f-==--3.0 V
MMD6150
or Equiv

PULSE
GENERATOR
PRF = 1.0 MHz typ
PW - 50% Duty Cycle

flV
50

MMD7000

or Equiv

t+ = 7.0 ns

t-=7.0n5
CT = 25 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the: ,scope termination impedance constitute a 20; 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
General I nformation section for paCkaging.

I
______________

t~ ~ 1~+~2.4 V
~-

TPout

~~~~~~~:V

•

ELECTRICAL CHARACTERISTICS

:s:

Test procedures are shown for only one
input of this device. To complete testing.
sequence through remaining inputs in the

(")

same manner.

~at

W

.....
.....

:s:

(")

j~8

~
.....

at
0o

11
12
13

::J

~­
::J

c:

@Test
Temperature
MC3115

t

MC3015

Characteristic

Symbol

Iinput

Pin
Under
Test

I
I
I

F

I

IR

Breakdown Voltage

I

BVin

Clamp Voltage

O"C
+25°C
+75"C

10 •
20

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

'0

I

-2.0

-2.0

-2.0

-2.0

-2.0

mAde

50

50

50

50

50

J.lAdc

5.5

5.5
-1.5

Vn

1.0

1.0

I.
-10

-10

V"

TEST CURRENT IVOLTAGE VALUES
Volts
V,H V,
VR
VRH
Vrnax

1.1

2.0

0.4

2.'

4.0

Ll

1.8

0.'

2.'

4.0

0.8

1.8

0.4

2.'

4.0

Ll

2.0

0.4

2.'

'.0

1.1

1.8

0.4

2.'

'.0

0.9

1.8

2.'

4.0

0.'

VCCH

'.0

.... ,,
.. ,

'.0

4.75

5.25

'.0

4.75

5.25

'.0

4.75

5.25

Vee
'.0

7.0

7.0

'.0

10 •

I 1011 I 1'0 I I. I V" I V,H I V, I

I

I I I I I I

VR

I

V1HX

,.,
,.,
,.,

I V_ I Vee I Vcc• I VeeH
I~i~i:: ~~, I - I - ! - I
VRH

2.'

I

2.'

I

V,HX

Goo

14

Vde

-1.5

VCCl

TEST CURRENT {VOLTAGE APPLIED TO PINS LISTED BELOW,

T

-2.0

Leakage Current

t

MC3015 Tost Limits
MC3115 Test Limits
I
+75"C
-55"C
+25"C
I + 125"C I O"C I +25"C
Min I Max Min Max J Min I Max ~ Min Max Min Max Min Max~ Unit

I

Forward Current

-55"C
+25"C
+125"C

mA
1011
I..

~

14

'2,3,4,7,10,
11,12,13

14

2,3,4,7,10,

~

11,12,13

14

Vde

Output
Output, Voltage

Short-CirCUit
Current

0.4

VOL

0.'

0.'

0.4

0.'

0.4

Vde

2,3,4,10

Vde

2,3,4,10,

14

11,12,13

VOH

24T

Ise

-40 1-100

-

2.'

2.'

2. ,

2.'

2.5

14

11,12,13

-40

-100

-,0

-100

-40

-100

-40

-100

-'0

-100

mAde

1,2,3,4,7,8.
10,11,12,13

14

1

Power Requirements
(Total Device)

=~~~u~~~r

Imax

Power Supply Drainl

IPDH

14

10

10

mAde

IpDL

14

'.2

'.2

mAde

14

Switchi!lg
Parameters
Turn-On Delay
Turn-Ofi Delay

'pd'pd+

1,8
1,8

14

mAde

12
12 1

1

I

1

1

1,2,3,4,7,
10,11,12,13'

1,2,3,4,
10,11,12,131

14

14

2,3,4,10,
11,12,13,

14

2,3,4,10,
11,12,13

112
12

1,2,3.4,7,
10,11,12, lsi

14

MC3100/MC3000 series

8-INPUT "NAND" GATE

I

MC3116F • MC3016F
MC31161 • MC30161,P
(54H30J)

(74H30J, N)

This device is an a·input NAND gate. It is useful
when processing a large number of variables, such as
in encoders and decoders.

Vcc
14"

760

2.8 k

58

J~8

3
4
5

12
1
2

8

1~:++tU

Positive Logic:

8 3.4.5.6.".,2.,.2

120-H-++-H
1
2

0-+-1-++-+-1.....

Negative Logic:

O-H:+::II:-t-=-H

8 - 3 + 4 + 6 + 6 + 11 + 12 + 1 + 2

1nput Loading Factor

7
Gnd

Pin numbers for the 54H30F174H30F device are
shown in the chart. These devices are available on
special request.

=1

Output Loading Factor"" 10
Total, Power Dissipation = 22'mW typ!pkg
Propagation Delay Ti me = 8.0 ns typ

DEVICE
MC3116F.Ll3016F,L.P
54H30F174H30F

PIN NUMBERS
9

2
10

3
2

4
3

5
5

6
6

7
11

8
12

9
1

10 11
14 7

12 13 14
8 13 4

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX

Vcc

+2.5 Vdc

280

t7.0 ns

t+

7.0ns

!r--......f-i-;=,-3.0

V

MMD6150

or Equiv

50

MMD7000

or Equiv

PW - 50% Duty CY,cle
t+ = 7.0 nl
t-

=7.0"1

-::-

CT = 25 pF = total parasitic capacitance. whJch includes probe, wiring. and load
capacitances.
The coax delavs from input to scope and output to scope. must be matched.
The 'scope :mult be terminated in

50~ohm

impedance.

The 95Q-ohm resistor

-.nd the -'Cope termination impedance constitute 820: 1 attenuatar probe. Coax
shall be CT -070-50

or equivaJent.

General I nformation section for packaging.

".\

'·%i",,qAA4!Upt

;;:: 4

.i.s;:;aa;1J",,4AA7P:;:::;;::;;

r-

OV

t~ -i 1;~.'~2.4
TPout
___~....:::.==:..-_--'--=--~~d4

V

V

•

ELECTRICAL CHARACTERISTICS

3:
C')

Test procedures are shown for only one

Co)

input of this device. To complete testing,

~

sequence through remaining inputs in the

~

~m

same manner.

s:

C')

~~
"'!

Co)

o

5
6

~

m

0o

8

::J

@Test
Temperature

t
t

-55°C
MC3116 +2Soc
+12Soc
MC3016

Characteristic
Input

Symbol

Forward Current

'F

Leakage Currellt

'R

Breakdown

Vo~tage

Clamp Voltage

Pin
Under
Test

MC3116 Test Limits
+2S oC
55°C
+12SoC
Min Max Min Max I Min I Max

I

I

I
I

MC3016 Test limits
O°C
+7SoC
I +2SoC
Min Max Min I Max Min Max

O°C
+2Soc
+7Soc

Un~

-2,0

-2.0

-2.0

-2.0

-2.0

mAde

50

50

50

50

50

50

/.lAde

5.5

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

20

-2.0

10L

10H

Short-Circuit
CUrrent

VOH

2.4

'se

-'0

Power Requirements
(Total Device)
Maximum Power
SUpply Current

Power Supply Drain

0.'

VOL

-1.5

Imax

2.'

-100

-'0

0.'

-100

-,0

0.'
2.5

2.'
-100

-,0

IpDH

14

10

IpDL

14

'.2

10

.. ,

-'0

-'00

Turn-Off Delay

5.0

4.5

5.5

5.0

'.5

5.5

5.0

5.5

5.0

'.5
4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

1.1

1.8

0.'

2.'

'.0

0.8

1.8

0.'

2.'

'.0

1.1

2.0

0.'

2.5

'.0

1.,

'.8

0.'

2.5

'.0

0.'

1.8

0.'

2.5

7.0

7.0

'.0

V1HX
2.5

I

2.5

I,.

ID

V"

V,H

V,

V,

V'H

Vmn

Vee

I

VCCLJ VCCH

I V,HX I

-'0

-100

1,2,4,5
6.11,12

1

10

mAde

'.2

'.2

'.2

'.2

mAde

14

I

14

I

11,2.3.4,5.8,1

6,7,11, i2

14

-I

8,11,12

1 1,2,3.4.5,

14

mAde

'0

1,2,4,5.
6,7,11,12

\1,2,4,5.

14

1,2,4,5,
6,11,12

mAde

10

Gnd

14

14

7,11,12

1,2,3,4,
5,6,11,12

14
1,2,3,4,5,
7,11,12

14

Pulse
In

'pd'pd.

4.0

141

Vd,

10

Parameter'S
Delay

VCC.H

2.'

1,2,4,5,

Vd,

2.5

Switching
Turn~Qn

0.'

...

8.5

14

VCCL

0.4

Vd,

0.'
2.5

-100

-10

Vee

2.0

Vd,

5.5

0.'

1.0

-10

V"
1.1

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

Output
OJtput Voltage

1.0

ID

TEST CURRENT /VOLTAGE VALUES
Volts
V,H V,
V,
V_
V'H

6,11,12

-1.5

VD

20

I

I

-2.0

BVin

10L

mA
10H
I,.

""
:r
c:
II

Puis.
Out

3,8

12

12

14

1,2,4,5,
6,11,12

3,8

'0

10

14

1,2,4,5,
6,11,12

MC3100/MC3000 series

4-WIDE
3-2-2-3 INPUT EXPANDER FOR
"AND-OR-INVERT" GATES

MC3118F • MC3018F
MC3118L • MC3018L,P
(54H62J)

(74H62J,N)

This expander is designed to expand the AND-ORINVERT capabilities of the MC3032 and MC3034.
One expander can be connected to each expander
input of the expandable gate.
VCC
14

3

8

4

I.

~'7;:~ ~r<~r<
J
2.8 k

!~

50-

~ 2.8 k

5
Collector
__\6
.l.

2--,--_/

___\8

1 2 - - . . - -.....
13
9

lo-H-+-H
2°-hH-+-H

10
11
"-Input Loading Factor"" 1

Full output loading factor of the expandable
gate is maintained.
Total Power Dissipation = 40 mW typ/pkg
Propagation Delay Time:
.6.tp d1 = +0.4 ns tvp
~tpdO = 0.05 ns typ
7
Gnd

6

When added to the expandable
"AND-OR-INVERT" gate.

atpd l/pF ~ +0.3 ns/pF typ
atpdO/pF - +0.04 ns/pF typ
Caused by additional capacitance
at expansion points.

Pin number. for the 54H62F/74H62F device are

DEVICE

shown in the chart. These devices are available on

MC3118F,L/3018F,L,P
54H62F 174H62F

special request.

8
12

9
7

10 11
8
9

12 13 14
5
6
4

APPLICATION: EXPANDABLE 4-WIDE 2-2-3-2-INPUT AND-OR-INVERT GATE
WITH A 4 WIDE 3-2-2-3 INPUT EXPANDER CONNECTED

3
4
5

r-----------,

I

I
I
I

2
12
13
9
10
11

EXPANDER

I

MC3018

I

I
Col1ector 1
Positive Logic:

___ oJI

8"-(1-13)+(2.3) +(4'5'6)+(9 '10) +(3·4·5) +(1-2)+(12 '131+(9 ,10-11)
~-------~r~----------JI

13
2
3
4
5
6
9
10

Expandable Gate

8

I
L

I
____________ JI

See General I nformation section for packaging.

EXPANDABLE
GATE

MC3032

'~

_______~~-------J
Expander

I

•

ELECTRICAL CHARACTERISTICS

3:

(')

W

Test procedures are shown for only one

.....
.....

input of the expander being tested. To
complete testing, sequence through remain-

,r:1l

ing inputs.

S

(')

W

0
.....

3
4

r:1l

5

00

2
12
13
9

@Test
Temperature

10

"

{ -55'C
MC3118
+25'C
+125'C
O'C
MC3018 { +25'C
+75'C

mA
V.

V.H

V.

2.4

4.0

2.4

4.0

7.85

2.4

6.3

10L

I..

10

5.B5

7.0

6.7

1.0

1.0

-10

-10

7.4

10L

Characteristic
Input
Forward Current

Breakdown Voltage

Clamp Voltage

VEE' VEE. V'H

V'L

0.4

1.0

0.85

2.0

0.8

0.85
0.6

0.85

1.8

4.0

0.4
0.4

0.85

1.8

0.8
0.8

2.5

4.0

0.4

1.0

0.85

2.0

0.8

2.5

4.0

0.4

0.8

0.85

1.8

0.8

2.5

4.0

0.4

0.6

0.85

1.8

0.8

'F

-2.0

-2.0

-2.0

-2.0

-2.0

'R

50

50

50

50

50

Output Voltage

Collector Current

-1.5

Vo

50

7.0

1.0

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

10

V.

V.H

V.

VEE' VEE. V,H

0.4

320

'eoti

0.4
-600

-470

-470

-470

V'L Vmax Vee IVee, IVeeH I

JLAdc
Vdc
Vdc

-1.5

0.4

0.. 4

VOL"''''
'Eo

C'
CD
Q.

Vm • x Vee VeeL VCCH

-2.0 mAde

5.5

5.5

BVin

lin

0.4

0.4
-600

-600

570

Vdc

1,2

JlAde

1,2

-I

7'

14

2,7*

14

2,7*
7'

~i~9·1

p-Adc

I

7'

I - I

7'

l14t 1'4t 1'4t
14

I

-

Gnd

14

14

Output
Emitter Current

:J

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

Pin

Leakage Current

...
:;-

TEST CURRENT /VOLTAGE VALUES
Volts

16,14

Power Requirements
(Total Device)
Maximum Power
Supply Current

Power Supply Drain

1 1m. .

14

mAde

8.0

8.0

IpDH

14

7.0

7.0

7.0

7.0

7.0

7.0

mAde

lpOL

14

9.0

9.0

9.0

9.0

9.0

9,0

mAde

"'Ground inputs to gates not under test.
t Apply to pin 14: @Lowtemp. VCCL' @25 C Vec' @ Hi temp VCCR
t t Connect 575 n resistor from Pin 8 to ground.
**This test is a measure of potential difference between pins 6 & 8.
D

1,2,3,4,5,7
9,10.12,13

14

1,2,8,4,5,
9,10,12,13

14
14

I ~'~i;:i2~i~

MC3100/MC3000 series

TRIPLE 3·INPUT EXPANDER
FOR "AND·OR" GATES

MC3119F • MC3019F
MC3119L • MC3019L,P
(74H61J, N)

(54H61J)

This device consists of three independent 3·input AN D
gates. The outputs of each gate are available as ORing
nodes. Using the MC3019 expander, with the MC3031
expandable gate, up to six AND gates can be ORed
together.

1/3 OF CIRCUIT SHOWN

VCC
14

2.8 k

"3=0-

- - - -......- - 0 9

12

2o--+--+

10

13

3O--+-+--i
Input Loading Factor = 1
Full output loading factor of the expandable

gate is maintained.
1k

Total Power Dissipation::: 25 mW typ/pkg
Propagation Delay Time:

dt p dl ::: +0.4 ns typ
AtpdO::: +0.Q5 ns typ
When added to the expandable
"AND-OR" gate.

7
Gnd

Atpdl/pF = +0.3 ns/pF typ
AtpdO/pF = +0.04 nslpF typ
Caused by additional capacitance
at expansion points.

Pin numbers for the 54H61F/74H61F device are

DEVICE

shown in the chart. These devices are available on
special request.

MC3119F,Ll3019F,L.P
54H61F174H61F

APPLICATION: EXPANDABLE 4·WIDE 2·2·2-3·INPUT AND-OR GATE
WITH A TRIPLE 3-INPUT EXPANDER CONNECTED

1
2
3

r--------..,I
9

~$=o-8

";~'0
:r:::;::::L..r
L _____ _

13

I

I
Collector

EXP'ANDER

1

MC3019

I

__ ..JI

Positive Logic:
8

,.........- ..... . . .
2...,..-.........../
10-'--............
11...,...-.........../
12-'--............
3

: IL

.2) + (3.4.5) + (10 ',1) + (12.'3) + (1 .2.3)

v

'---y--J

Expandable Gate

Expander

EXPANDABLE

}----f-S

GATE
MC3031

I

13

= (1

I
_ _ _ _ _ _ _ _ .....II

See General Information section for packaging.

.. 4

(

AlAe A;

"

i1¥JSJt4ll

I

•

ELECTRICAL CHARACTERISTICS

s::

ow

-

Test procedures are shown for only one
expander. The other expander is tested in

a similar manner. Further, test procedures
are shown for only one input of the

eXM

~CD

pander being tested. To complete testing,
sequence through remaining inputs.

s::

o

~

CD

~3=C>-9
3

8
J

....

:j'

:3=C>-s

c:

J

Characteristics
Input
Forward Current
Leakage Current
Breakdown Voltage
Clamp Voltage

@Test
Temperature

{ -5$"C
MC31l9
+25°C
+125°C
DOC
MC3D19 { +25°C
+75°C
MC31l9 Test Limits
MC3D19 Test Limits
Pin
DOC
+25°C
+125°C
+25°C
+75°C
Under -5SoC
Symbol Test Min Max Min Max Min Max Min Max Min Max Min Max Unit
IF

1

-

-2.0

-

-2.0

-

-2.0

5.5
5.5

5.35

-

2.5

4.0

0.4

2.2

2.0

0.8

-

5.0

4.75 5.25

5.5

1.0

-10

2.5

4.0

0.4

1.8

5.0

4.75 5.25

-

-

2.5

4.0

0.4

0.8
0.8

7.0

6._~

2,.2
2.2

-

5.0

4.75 5.25

IOL

lin

ID

V.

V.H

VF VCEX VIH

-

-

2,3

1

-

-

-

-

-

-

-

- -

Vde

-

-

1

-

-

-

Vo

-1. 5

-

- -

-

-

-1. 5

-

1.0

-

-

1.0

-

50

7'

-

-

2,3,7

-

-

-

14

-

14

2,3,7

-

-

-

-

-

14

-

7'

-

-

-

-

-

-

1,2,3

-

7'

2,3

-

9

-

1

-

-

-

-

14

-

14

-

7

-

-

9.0

-

-

-

-

-

9.0

-

-

mAde

-

-

IpOH

-

18

-

18

-

18

-

18

-

18

mAde

-

-

- - -

IPOL

14

-

6.75

-

6.75

-

6.75

6.75

-

6.75

6.75 mAde

-

-

-

--

--

*Ground inputs to gates not under test.

14

9

18

..

-

-

-

-

-

-

-

Vde

-

-

Gnd

~Adc

14

-

-

VI. V..... Vcc VCCl VCCH

50

14

-

,

1.0

lmax

----

VI. V..... VCC Vcc• VCCH

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

1

-

-

1.8

-

-

Power Rrblrements
(Total &Vice)

4.5

-

1

50

5.0

-

-

1.0

1.8

·1

50

5.5

-

4.5

2.4

0.8
0.8

5.0

-

2.2
2.2

7.0

-

0.4
0.4

1.8

7.3

4.0
4.0

-

-

-

-

5.5

2.4

Vde

50

-

50

4.5

-10

t-tAdc

-

-

1.0

5.0

1.0

-

-

50

-

50

-

5.5

50

50

50

0.8

-

-

1.0

2.0

-

5.5

-

2.2

-

-

-

0.4

-

50

9-

4.0

mAde

-

9

V.H

2.4

-2.0

-

VOL

ID
-

V.

-

-

1

ICEX

VF VCEX VIH

'in

4.5

-2.0

1

Output Voltage

mA
10 •

-

~

Emitter Current

Power Supply Drain

-2.0

BVin

Output

Maximum Power
Supply Current

-

~

TEST CURRENT/VOLTAGE VALUES
Volts

-

-

-

-

-

-

14

-

-

-

1,2,3,4,5,
6,7,11,12,13

1,2,3,4,5,6,
11,12,13

-

-

-

-

-

-

-

14

7

-

-

-

-

-

-

-

-

14

1,2,3,4,5,
6,7,11,12,13

MC3100/MC3000 series

EXPANDABLE DUAL
2-WIDE 2-INPUT
"AND-OR-INVERT" GATE

MC3120F • MC3020F
MC3120L • MC3020L,P
(54H50J)

(74H50J,N)

One side of this dual device consists of two 2-input AND
gates ORed together and driving an output inverter. The other
side consists of two 2-input gates ORed together, driving an
output inverter, and the OAing nodes are available for expansion. Up to four AND gates can be ORad together using
the MC3030/3130 expander. Care should be taken to minimize the amount of capacitance on the expander terminals in
order to maintain switching speeds.

CIRCUIT SCHEMATIC
OF CI RCUIT SHOWNt

~1/2

Vee
14

12

2.4 k

BOO

10

9

60

2.4 k

9--....r-~

-~ L_.../

10

B

13
Emitter 11 - _ _ _ _ _ _ _--'

13

Collector 1 2 - - - - - - - - - - - - '

B

Positive Logic:
8

(9.10) + (13 .1) + (Expanders)

Negative Logic:
8 - (9

7

11

Gnd

+ 10) -(13 + 1) -(Expanders)

Input Loading Factor = 1
Output Loading Factor = 10
Total Power Dissipation = 62.5 mW typ!pkg
Propagation Delay Time = 6.0 ns typ

tOther half of circuit omits e:!

1,9,10,
12,13""

14

11

1,2,3,4,5,7,

14

mAde

9,10,13
14

Pulse

Switching
Parameters
Turn~On

Delay

Turn-Off Delay

In

tpd~

tpd+

Pulse
Oul

14

1.8
1.8

:s:
n

w
.....

gate, The other gate is tested in the same

1l

*Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

1l

13

7,9,10*

13

7,9,10*

MC3100/MC3000 series

QUAD 2-INPUT
EXCLUSIVE "OR" GATE

I

MC3121F • MC3021F
MC3121L • MC3021L,P

This device consists of four 2-input Exclusive
OR gates_ They can be used to build parity checking/generating functions. Up/down counters can
be built using these gates and J-K flip-flops.

CIRCUIT SCHEMATIC
1/4 OF CI RCUIT SHOWN

Vee
14

12=D13

Positive Logic: 3 = 1 •

11

'2 + 1. 2

2~~~------+----1~----~

Input l.oading Factor = 1.6
Olftput Loading Factor = 8
Total Power Dissipation""" 1 00 mW typ/pkg
Propagation Delay Time = 14 ns tvp

7
Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

280

t+

t-

7.0 ns

7.0 ns

It--.......H~=-3.0

MMDS150
or Equiv

V

OV

t~pdtpd+

MM07000
or Equiv

50
t+·""'7.0ns

~2.4V

t-=7.0nl

TPout'

1.5 V

-_--===::=-=-=-~~d4

O·ne input to gates not under test must be tied to VI HX the other grounded.

V

CT = 25 p~ = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
Th. C08>t: delays, from inptrt to scope and output to scope must be matched.
The scope must be terml.nated In 50~ohm impedance. The 950·ohm resistor

and the scope t.rminat~Qn i~pedance constltute a 20: 1 attenuator probe. Coax
shall be CT ·070-50 or equivalent.

See General I nformation section for packagj ng.

16,,,,

'~D

" i .. L+9$.N!k

Jtt\' C.

;

4

;: 4 4 1

4 FHj(,....

=

q¢

H

,;jU&4M$

•

ELECTRICAL CHARACTERISTICS

....
s:

To complete testing, sequence through remaining inputs.

(')

~

~~3
:~6
,~~B

N
....

nO
:J

~

S·

'2~"
13---fL...--/-

-SS<>(
MC3121 { +25°C

+125°C
O°C
MC3021 { +25°(
+7So C
MC3121 Test limits
Pin
Under ~-,--f--,--f--,---I
Symbol

~

o I mAde

'F

-3.0

-3.0

-3.

'R

100

100

100 I/.I.Ade

5.5

BVin

Output
Output Voltage

Short-Circuit
Current

VOH

~:: I

'sc

-20 I -65 1-20

PDwer ROqilramants
{Total Devicel
Maximum Power
Supply Current

Imax

L4

I~::

~::
-65

35

16

-1.6

16

-1.6

16

-1.6

0.8

16

-1.6

1. 1

16

-1.6

1.1

16

-1.6

0.9

Itn
1.0

1.0

I

mAde

1.0

V1H

Vf

VI

VaH

1.1

2.0

0.4

2.4

4.0

5.0

1.8

0.4

2.4

4.0

5.0

1.8

0.4

2.4

4.0

5.0

4.5

5.5

2.0

0.4

2.5

4.0

5.0

4.75

5.25

1.8

0.4

2.5

4.0

5.0

4.75

5.25

1.8

0.4

2.5

4.0

5.0

4.75

5.25

1.1

4.5

V1HX

V_ ••

2.5

7.0

2.5

'1.0

V1HX

V""1l

5.5

4.5

5.5

TEST CURRENTIVOlTAGE APPLIED TO PINS LISTED BELOW,

+75'C
10L

10H

I..

ID

I Ya I V,H

V,

V.

VRH

I

I

Vee VCCL VeeH

Gnd

-3.01 mAde

2,5,10,13

14

4,7,9,12

IOO

100 I /.I.Ade

5,10,13

14

2,4,7,9,12

14

2,4,7,9,12

5.5
-1.5

Vdc

5,10,13

Vdc

5,10,13

14

5,10,13
5,10,13
5,10,13
5,10,13

14
14

~:: I = I~:: I =
-20

1.0

~
Vee VCCL VeeH

V1L

-3.0

I g:11 ~~~
~:; I I~: ~ I I ~~~

I I ~~~ I::;

I -20 I -65 I mAdei

ID

IOO

Vdc

g:! I I g:: I ~~~

0.4
0.4

VOL

~
IOH

-3.0

Vdc

-1.5

VD

+25°C

~1~I~xl~IM~I~I~xl~

Forward Current

Breakdown Voltage

101

MC3021 Test limits
O°C

Leakage Current

Clamp Voltage

r:::
~

TEST CURRENT !VOLTAGE VALUES

@~
Temperature

Characteristic
Input

-65

I -20 I

-65

40

I -20 I

1,2
1,2

2,5,10,13

-65 I mAde

mAde

1,4,9,12

4,7,9,12

4.7,9,12

4,7,9,12
4,7,9,12
4,7,9,12

14
14

3,4,7,9,12

14

2,5,10,13

14

Power Supply Drain

14
14

Switching Parameters
Turn-On Delay

'pd-

1,3

25

25

14

2,5,10,13

4,7,9,12

Turn-Off Delay

tpd+

1,3

25

25

14

2,5,10,13

4,7,9,12

Pins not listed are left open.

s:
(')

....NW

Test procedures are shown for only one
gate. The other gate is tested in the same
manner. Further. test procedures are shown
for only one input of the gate under test.

•

MC3100/MC3000 series

QUAD 2-INPUT
EXCLUSIVE "NOR" GATE

MC3122F • MC3022F
MC3122L • MC3022L,P

This device consists of four 2-input Exclusive
NOR gates. They can be used to build parity
checking/generating functions. Up/down counters can be bu ilt using these gates and J-K
flip-flops.

CIRCUIT SCHEMATIC
1/4 OF CI RCUIT SHOWN

Vee
14

4k

4k

4k

100

4k

1.2 k

3

12=nJ-

2o-~-+------~---+----~-------+------~

11

13

2 k

Positive Logic: 3 ==

I nput Loading Factor

1. 2 + 1 .2

= 1.6

Output Loading Factor"" 8
Gnd

Total Power Dissipation = 85 mW typ/pkg
Propagation Delay Time"" 14 os typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

390
t7.0 ns

t+

7.0 ns
TP out

i,.---V---+=;;-3.0 V

MMD6150
or Equiv
PRF "" 1.0 MHz typ
PW"" 50% Duty Cycle~
t+=7.0ns
t- =7.0ns

50

MMD7000
or Equiv

t~

r-

OV

1~~2.4

-1

V

~-

______________

TP out

Ground inputs of gates not under test.

=====~~:V

CT ::; 25 pF "" total parasitic capacitance, which includes probe, wiring, and load

capacitances.
The coax

delav~

from input to scope and output to scope must be matched.

The scope must be terminated· in 50·ohm impedance.

The 950·ohm resistor

and the 'scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See GenEliral I nformation section for packaging.

4U

hi

IX oMn:iuu;::::::a

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

W

gate. The other gate is tested in the same
manner. Further. test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

...&

N
_N

3:
w

(')

~=£>o----3

:=£>0---9~

10~

0
N
N

6

nO

8

@Tesl
Temperature
{ -55·C
MC3122 +25·C
+125·C
{
O·C
MC3022 +25·C
+75·C
MC3022 TeSI Limils

MC3122 Tesl Limits
Pin
O·C
+2S·C
-55·C
+25·C
+125·C
+WC
Under
Symbol Tesl Min Max Min Max Min Max Unil Min Max Min Max Min Max I Unil

I

Forward Current

IF

1

[R

1

Breakdown Voltage
Clamp Voltage

I

-

VD

1

-

VOL

I

Short-Circuit

CUrrent

I 'sC

33
3
3

VOH

I

3

~3.

0

-

100

BVin

Output
Output Voltage

-

-

-3.0
100

5.5

-

-

-1.5

-

-3.0 mAde
j.LAdc

-

Vde

-

-

Vde

-

1-- 10.4
o. ~ 1-- 10.4
O. 'I O. 'I
- 10.4
2.'
2.'
I -20

-I
I
-65

2.'
2.'
-20

-

2.'
2.'
I -65 I -20

-

-

100

--

Vde
Vdc
Vde
Vde

-

-3.0
[00

5.5

- -

-3.0
100

-

-

-

-1.5

I -65 ImAde I -20 I

-I

2.5
2.5

-65

-20

2.5
2.5

I""

16

-1.6

16

I.

-1. 6
-1.6

16

-1.6

16

-1. 6

16

-1. 6

I,.
2.0

2.0

I.
-10

-10

V.

VR

VRH

Vee

VCCL VccHl V_

0.'

2.'

'.0

5.0

'.5

5.5

1.8

0.'

2.'

5.0

1.8

0.'

5.0

1.1

2.0

0.'

2.'
2.5

'.5
4.5

5.5

0.8

'.0
4.0

4.75

5.25

1.1

1.8

0.9

1.8

0.'
O.•

Va

V,H

1.1

2.0

1.1

I

7.0

I

7.0

CD
Q.

5.5

'.0

5.0

2.5

'.0

5.0

4.75

5.25

2.5

'.0

5••

4.75

5.25

TEST CURRENT!VOLTAGE APPLIED TO PINS LISTED BELOW,
VCCH

10l

V..."

GIld

-3.0 mAde

14

4,5,7,9,10,12,13

100

/.LAde

14

2,4,5,7,9,10,12,13

-

Vde

14

2,4,5,7,9,10,12,13

1-- 1O'i
1-- 10.4
O. 'I
1 -- 10.'
0.4
0.4
2.5
2.5

10l

I

Volts

mA

:j'
c

J

TEST CURRENT IVOLTAGE VALUES

13~

Leakage Current

...
::J

12~11

Characterisfie
Input

--

1.

Vde

Vde
Vdc
Vde
Vde

I -65 I -20 I -65 I mAde

1,2

I I,'-

I

4,5,7,9,10,12,13

14
14

4,5,7,9,10,12,13
4,5,7,9,10,12,13

14

4,5,7,9,10,12.13
4,5,7,9,10,12,13

14
1,2

3,4,5,7,9,10,12,13

14

Power Requirements
(ToIal Deyice)
Maximum Power
Supply Current

mAde

Power Supply Drain

14

1,2,4,5,9,
10,12,13

mAde

2,5,10,13

mAde

1,2,4,5,9,
10,12,13

1,4,9,12,

14
14

Switching Parameters
Turn-On Delay

tpd_

22

14

Turn-Off Delay

tpd+

22

14

Pins not listed are left open.

3:

(')

2,4,5,7,9,10,12,13

I

I 2,4,5,7,9,10,12,13

MC3100/MC3000 series

DUAL 2-WIDE 2-INPUT
"ANO-OR-INVERT" GATE

I

MC3123F • MC3023F
MC3123L • MC3023L,P
(54H51J)

(74H51J. N)

This dual device consists of two 2-input AND gates
ORed together and driving an output inverter.

CIRCUIT SCHEMATIC
1/2 OF CI RCUIT SHOWN

Vcc
14

800

10

9

1~~'

8

13

60

2.4 k

1

~~

4
13

6

5

8

Positive Logic:
8=(9·10)+(13.,)

Negative Logic:
8-(9+ 10) .(13+ 1)
Input Loading Fa'ctor = 1

Output Loading Factor

= 10

Total Power Dissipation = 62.5 mW typ/pkg

Gnd

Propagation Delay Time

= 6.0 ns typ

DEVICE

Pin numbers for the 54H51 F174H51F device are
shown in the chart. These devices are available on

MC3123F,Ll3023F,L,P

special request.

54H51F174H51F

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.5 Vdc

Vee
Coax

950
±1.0%

280

TP out

t-

7.0 ns

\.-----.iH"""'=-3,0 V

MMD6150

PRF = 1.0 MHz typ
PW ... 50% Duty Cycle

t+

7.0 ns

or Equiv

I
L ______ JI

OV

50

MMD7000

t+ = 7.0nl
t- =7.005

tP~_
tpd+
,

or Equiv
TP out

~2.4

V

1.5 V

-,--';;0.4 V
Gnd

CT = 25 pF =total
capacitances.

parasitj~

capacit8':lce, which includes probe. wiring, and load

The coax delays from input to scope aoc::l output to scope multt be matched.
The scope must be terminated in 50·ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equ;'valent.

See General I nformation section for packaging.

,U"A,.ifM .. ;

·!AM "'" 4

,

,

;a;a;;;;#

.....

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

gate. The other gate is tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

s(")
W
....
N
.W

S
(")
w
o

maining inputs.

1~~8

N

W
n

13

o

1

::l

~.

::l

~~,

c:

TEST CURRENT/VOLTAGE VALUES

@Test

MC3123

V1L

VIH

VF

VA

V,",o"lts:;-_~_~_ _~_~_ _~
VRH
V m • x Vee
VCCl
VeeH
V1HX

1.1

2.0

0.4

2.4

4.0

1.1

1.8

0.4

2.4

4.0

-2.0

0.8

1.8

0.4

2.4

-2.0

1.1

2.0

0.4

2.5

mA

Temperature

lal

10M

-55G(

20

-2.0

+2S C
+125°C

20

-2.0

20

oDe

20

Unit

10L

t

G

(

lin

10

1.0

-10

5.0

4.5

5.5

5.0

4.5

5.5

4.0

5.0

4.5

5.5

4.0

5.0

4.75

5.25

VCCL

VeeH

7.0

~

2.5

l
Characteristic

Symbol

Pin
Under ~
Test~x

MC3023 Test limits

MC3123 Test limit,

TEST CURRENT I VOLTAGE APPLIED TO PINS LISTED BelOW,
10H

Input
Forward Current
Leakage Current
Breakdown Voltage
Clamp Voltage

Output
Output Voltage
Short-Circuit
Current

Power Requirements
(Total Deyice)
~p~u~u;~:n~r

I

IF

-2.0

IR

50

BVin

2.0

-2.0

-2.0

50

50

50

50

5.5

-1. 5
0.4'

VOL
V OH

2.4

I

-

I

2.4

50

!

I

-

I

2.4

I 0.4 I

I -

I

2.5

I 0.4 I

I

-

I

2.5

I 0.4 I

I

-

I

2.5

I V,H I V,

VR

VRH

Vm ..

I Vee

/lAdc

14

7,9,10,13*

Vdo

14

7,9,10,13*

I 0.4 I Vdc

14

I

13
13

Vdo

14

20

20

7,9,10*
7,9,10 *

14

1,7,10*
1,7,8,9,
to, 13"

14

-40 I -100 I -40 I -100 I -40 I -100 I -40 I -100 I -40 I -100 I -40 I -100 I Vdc

Ise

Gnd
7,9,10*

Wo

I -

V1HX

14

14

-1. 5

'0.4 I

VIL

13

-2.0 I mAde

5.5

VD

Imax

-2.0

I'n

10

1,2,3,4,5,7,

14

mAdc

9,10,13

14

Switching
Parameters

Pulse
In

I Pulse
Oul

Turn-On Delay

t pd _

1.8

11

11

14

13

7,9,10*

Turn-Off Delay

t

1,8

11

11

14

13

7,9,10

pd.

*Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

*

MC3100/MC3000 series

DUAL 4-INPUT "NAND"
BUFFER GATE

MC3124F • MC3024F
MC3124L • MC3024L,P
(54H40J)

(74H40J,N)

This device consists of two 4-input NAND power
gate circuits, Each gate is designed for driving high
fan-out loads (30).

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

390

1.4 k

45

1

2
4

6

So-t+-H

Positive Logic: 6
Negative Logic: 6

=1 • 2 • 4 • 5
=1+2 +4 +5

I nput Loading Factor

:=

2

Output Loading Factor = 30
Total Power Dissipation = 90 mW typ/pkg
Propagation Delay Time = 6.0 ns typ
7
Gnd

Pin numbers for the 54H40F174H40F device are
shown in the chart. These devices are available on
special reques~.

DEVICE
MC3124F,L/3024F,L,P
54H40F174H40F

1

4

PIN NUMBERS
6
8
9 10 11
11 10 6
7
5
14

12 13 14
8
9
4

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

vcc

950
±.1.0%

93
t+
7.0 ns

,-

7.0 os

TP out

!r---.J-+=,.,..-3.0 V

MMD6150
or Equiv

OV
PRF = 1.0 MHz tvp
PW "" 50% DutV Cvcle
t+ "" 7.0 ns
t-""7.0ns

50

MMD7000

'P~dtpd+'
:2:2.4 V

or Equiv
TPout

1.5 V

---';0.4 V
Gnd

Cr

= 25

pF = total parasitic capacitance, which includes probe. wiring, and load

capacitances.
The coax delavs from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The ~50-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General Information section 'for packaging.

I

•

ELECTRICAL CHARACTERISTICS

W
....

gate. The other gates are tested in the ;iame
manner. Further, test procedures are shown

,~

for only one input of t!:le gate under test.

To complete testing, sequence through re·

s:
(")

maining inputs.

~
~

!==L)-s

8::J

:to

9--

19===l
13==l

)-8
MC3124

MC3024

Characteristic
Input

Symbol

Forward CUrrent

-4.0

Leakage Current

IR

100

Breakdown Voltage

-4.0

-4.0

-4.0

-4.0

I mAde

roo

100

100

100

100

I

0.'

VOL

2.'

2.4

0.'
2.4

0.4
2.5

Ise

-1.5

60

-1.5

6.

-L5

60

-1.5

60

-1.5

60

-1.5

10

V"

Vee

VCCL

VCCH

1.0

-10

1.1

2 .•

5.•

'.5

5.5

1.1

1.8

5••

'.5

5.5

0.8

1.8

5.0

5.5

1.1

5.0

'.5
4.75

1.0

-10

5.25

1.1

5.0

4.75

5.25

0.9

5.0

4.75

5.25

...

2.'

'.0

0.'

2.'

4 .•

0.'

2.'

'.0

2.0

0.'

2.5

'.0

1.8

0.'

2.5

4.0

1.8

0.'

2.5

'.0

..

,

'.0

IOL

10H II,. I 10 I V" I V'H I VF I

VR I

VRH

2.'

I

I V I Vee I VCCL I VCCH I
mox

2,4,5

/lAde

2.5

V,HX I

"

14

2,4,5,7"

14

2,4,5,7*

"
"

14

11.2,4,5

Gnd

14

I.

Vd,

2.5

-40 ! -125

~

V1HX

TEST CURRENT /VOlTAGE APPLIED TO PINS LISTED BelOW,

0.4 ! Vdc

0.4
2.5

-40 I -135

o.

lin

Vd,

-1.5

0.4

10H

C

Vd,

5.5
-1.5

Vo

VOH

Short-Circuit
Current

DOC
+25°C
+75°C

0

~4.

5.5

BVin

Output
OUtput Voltage

-55°C
+25°C
+12n

MC3124 Test limits
MC3D24 Test limits
55°C L_+~5°C
1 +12SOC I - It'
1- +25°C
+75°C
~I~I~I~I~I~I~I~I~I~ M~unitl

IF

Clamp Voltage

t
t

10<

::J

TEST CURRENT /VOLTAGE VALUES
Volts
VR
VRH
Vm..
V'H VF

mA

@Test
Temperature

Pin
Under
Test

14

2,4,5

mAde

14

11.2.4.5,6,7*

I.

1,2 .. 4,5,7
9,10,12,13

Power Requirements
(Total Device)

Maximum Power
Supply Current
Power Supply Drain

Imax

14

IpDH

14

IPDL

14

Turn-On Delay
Turn~Off

Delay

'pdt pd +

I
I

14

mAde

22

22

40

40

40

40

.0

40

mAde

16

16

16

16

16

16

mAde

1,2,4,5,9,
10,12,13

9.10~,13

1,6

I

12

12

14

1,6

I

12

12

14

... Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

11,2,:,5, ,

14

lPulseIn 1PuisOut•

..

Switching
Parameters

3:

(")

Test procedures are shown for only one

,

2,.,5'

2,4,5

"
"

MC3100/MC3000 series

DUAL 4-INPUT "NAND"
POWER GATE

MC3125F • MC3025F
MC3125L· MC3025L,P

This device consists of two 4·input NAND power
gate circuits. Each gate is designed for driving high
fan-out loads (20).

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vee
14

450

2.2 k

j:=[~)-6

54

1~==3 =)-8
1
2

6

4

5o-++-H

Positive Logic: 6 l ' 2 • 4 • 5
Negative Logic: 6 - 1 + 2 + 4 + 5

Input Loading Factor = 1.3
Output Loading Factor = 20

Total Power Dissipation = 70 mW typ/pkg
Propagation Delay Time = 6.0 ns typ

Gnd

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX

Vee

+2.5 Vdc
Coax

140

950

± 1.0%

t+

t-

7.0 mi

7.0 ns

TP out

PRF = 1.0 MHz typ
PW =- 50% Du~y Cycle
t+=7.0n5
t-=7.0n5

j,---.lH-=""","-3.0 V

MMD6150

PULSE
GENERATOR

or Equiv

50

MMD7000
or Equiv

tP~_
,
tpd+~2.4 V
TPout

1.5 V
---~0.4V

------------Gnd
CT

= 25 pF =total

parasitic capacitance, which includes probe, wiring, and load

capacitances.
The COax delays from input to ,scope and output to sC'?Pe must'be matched.
The scope must be termtnated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 a"ttenuator probe. Coax
shall be CT -070-50 or $quivalent.
See General I nformation section for packagtng.

.fill;WiiU

c·.

In

IF

,.4P 4

]!4iU¥(¢;;;;:;::;U:;;;:;Z;;;;;;;t;;#4i

I

•

ELECTRICAL CHARACTERISTICS

S

n

Test procedures are shown for only one

CtJ

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

~

J~~

s

n

CtJ

o/'I.)

!===3 }-s
16§}>12

U1

n-O

...5'
::J

8

13

c:

~

Characteristic

Inpul

Symbol

Pin
Under
Test

MC3125 T.sl limils
MC3025 Tesl Limils
55°C I +2S'C
I + 12S°C 10°C
+2S'C
MinTMax Min Max Min Max Min Max Min I Max I Min

I

I

I

I

I

Forward CUrrent

IF

-2.6

-2.6

-2.6

Leakage Current

IR

50

50

50

Breakdown Voltage
Clamp Voltage

BV

Short-Circuit
Current

Power Requirements
(Tolal Device)

-2.6

-2.6

50

50

5.5

w

0.4

VOL
V OH

241

Ise

-50

.

24

I.

I -125 I -50 I -125

Maximum Power
Supply Current

14

Power Supply Drain

14

34

14

10.6

50

0.4

0.4
2.4
-50

-125

-50

-50

16

T. 1

34

I . I 10.6

0.4
2.5

-125

-50

-125

34

34

10.6

10.6

.

Turn-On Delay
Turn-Off Delay

F

I

V,

VRH

I V I Vee I V I V I
rna ..

14

2,4,5

1

.

34

mAde
mAde

I. I. I. I . I. I

12

1,6

I . I . I .I .

121

no

I

no

.

-1

CCH

V1HX

!

Gnd

14

7'

14

2,4,5,7'"

14

2,4,5,7*
7'

I

I

I

7'

14

2,4,5

1

1,2,4,5,6,7*

14

1,2,4,5,7
9,10,12,13

14

.

1,2,4,5,9,
10,12,13

.

Pulse Pulse
In
Oul

I. I. I

CCL

2,4,5

14

6

mAde

10.6

12

*Since this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

,H

1

6

34

12

-1

IL

1

Vd,

10.6

1,6

r

I V IV I V I

1

Vd,

Switc~--

Parametelrs

10

mAde

16

.

I lin

1

Vdo

2.5
-125

IOH

Vdo

0.4

2.5

'OL

I ,uAde

-1. 5

I . I 0.4

I

l Unit I
-2.61 mAde

Max

5.5

-1.5

Vn

Oulput
Output Voltage

r
I

I

r
I

. I. I . I . I. I

I

6

1

6T-l-T-l-I·T

I
T

I .. II II
14

I

14

14

7

14

1,2,4,5,7
9,10,12,13

I II

. I

2,4,5

I

7'

2,4,5

I

7'

•

MC3100/MC3000 series

DUAL 4-INPUT "AND"
POWER GATE

MC3126F • MC3026F
MC3126L • MC3026L,P

This device consists of two 4-input AND power
gates. Each gate is designed for driving high fan-out
loads (20).

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

2.2 k

450

3k

1
2
4

54

6

5o-,..t+-H

Positive Logic: 6 == 1 • 2 • 4 • 5
Negative Logic: 6"" 1 + 2 + 4 + 5

I "put Loading Factor"" 1.3
Output Loading Factor '= 20
Total Power Dissipation = 90 mW typ/pkg
Propagation Delay Time = 9.0 ns typ

7

GND

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee

140

t+
7.0 ns

t-

7.0 ns

j,......:--J--+----3.0 V
MMD6150
or Equiv

PULSE

GENERATOR

"-':"::';;:"'-0 V

PRF = 1.0 MHz tvp
PW

= 50% Duty Cycle

50

t+ = 7.0ns
t-=7.005

MMD7000

or Equiv

"...----+--~~2.4

V

';0.4 V

======~-----~====Gnd
CT = 25 pF =total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be- terminated tn 50-ohm impedance. The 950-ohm resistor
and the scope terminati,on impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General Information section for packaging.

e.@""lI!C1:;;;au::;:::

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

sC')
....
N
Co\)

gate. The other gate is tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

~(j)

S

C')

~

N

(j)

8

:J

lE=~

r+

)-8

13

Temperature
MC3126

MC3026

Characteristic
Input

Symbol

Forward Current

Leakage Current
Breakdown Voltage

1

Clamp,Voltage

I
I

'F

-2.6

'R

50

BVin

V()lt~e

vD

-2.6

-2.6

-2.6

"

'0

50

I

VOL

0.'

2.4

-

0.'

-125

-50

I

I

0.'

-125

-50

-125

-125

-50

.0

-4.0

40

-4.0
-4.0

.0

-4.0

Unit

1",-

10 •

-4.0

lin

1.0

1.0

I.

V,

Vee

VCCl

VCCH

1.1

2.0

0.'

5.0

4.5

5.5

-10

1.1

1.8

0.4

2.4

4.0

0.8

1.8

0.4

2.'

'.0

-10

1.1

2.0

0.'

2.5

4.0

1.1

1.8

0.'

2.5

'.0

0.'

1.8

0.'

2.5

4.0

2.'

'.0
'.0

'.0

I::

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

50

.Ad,

lin

I.

V"

V,.

V,

VR

V_

VR•

Vee

I V IV
CCL

-125

-50

-125

I

2.5

CCH

I

V1HX

14

I

Gnd

T

2,4,5,7

141

I

I

2,4,5,7

14

Vd,

0.4

2.5

14

2,4,5 '"

Vd,

2.5

~

V1HX

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW,

50

2.5

-50

-4.0

'0
40

mAde

0.4

0.'

2.5

2.'

IOH

'0

O°C
+25°C
+75°C

-2.6

-1.5

2.'

-50

' Be

I-

-55°C
+2SOC
+ 125°C

-2.6

5.5

-1.5

V OH

Short-Circuit
Curl.'ent

I

5.5

Output
Output

MC3026 Test Umits
O°C
+25°C
+75°C
Min I Max Min Max Min I Max

MC3126 Test Limits
55°(
+2S oC I + 125°C
Min I Max Min Max I Min I Max

Pin
Under
Test

t
t

10L

5·

TEST CURRENTIVOLTAGE VALUES
Volts
VR
V_
VR•
V,. V,

mA

@Test

Vd,

2,4,5

>II

14

Vd,

2,4,5 '"

14

1,2,4,5

mAd'

*

., ,

14

Power Requirements
(Tolal OeYice)

Maximum POwer

Supply Current
Power Supply Drain

14

IpDH

14

15

15

15

15

15

15

mAd,

IPDL

14

40

.0

40

'0

.0

'0

mAde

22

--

Switching

Parameters
Tum-on petay
Turn-au Delay

t pd _
tpd+

* Since this is a non-inverting gate,
not under test to VRH •

mAd,

Imax

1,6

I

I

,,2,4,5,.1

-

I I

-

15
l5

1

I

I

power drain is minimized by tying the inputs to gates

-

I

l5

I I

l5

14
1,2,4,5,7,
9,10,12,13

!4

In

-

14

9,10,12,13
1,2,4,5,
9,10,12,13

Pulse

-

-

1,8

22

Pulse
Oul

14

2,4,5

14

2,4,5

.,

MC3100/MC3000 series

DUAL 3-INPUT 3-0UTPUT
"AND" SERIES TERMINATED
LINE DRIVER

I

MC3128F • MC3028F
MC3128L • MC3028L,P

This device is a dual 3-input/3-output series-terminated
AND line driver that minimizes switching transients on long
lines by approximating line ·impedance. Two outputs are provided through 75-ohm resistors for use when driving 93 to
120-ohm lines. These outputs should be paralleled when driving 50 tb 93-0hm lines. In addition, an output is provided
directlY at the gate output node for driving adjacen~ gates.

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vee
14

2.4 k

2.4 k

800

60

=0£

I'
12
13

5
I
2

9

8

10

:3
Positive Logic: 4,

5, 6, == 1 .2-3

Negative Logic: 4, 5, 6,

Input Loading Factor

=1 +2 +3

=1

Output Loading Factor, Direct Output (Pins 6 & 8) ==
8 minus the number of reslstor·terminated outputs

7

being used.

Gnd

Output Loading Factor. Resistors (Pins 4,5,9, & 10)

=1

Total Power Dissipation = 56 mW tYP/pkg
Propagation Delay Time"" 9.0 ns typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.5 Vdc

Vee

,+

280

7.0 ns

,-

7.0 os

i,.---V-+-::::::;--3.0 V
MM06150
9r Equiv

TPin

:F'C

"-=::"'-0 V

PW == 50% O'utV Cycle
t+ = 7.0 ns
t- = 7:0n$

Pd+

50

MMD7000
or Equiv

..

'pd-

.?2.4 V

TP out

1.5 V

","0.4 V

--------------------~--Gnd

CT == 25 pF = total parasitic ·capacitance, which includes probe. wrring, and load

capacitances.
The coax delays trom input to scope and output to scope must be matched.
The scope must be terr:ninated in 50-ohm impedance. The 9S0-ohm reSistor
and the scope termination-impedance constitute a 20: 1 attenuatar probe. Coax
shall be CT -070-50 or equivalent.

See General I nformation section for packaging.

II';:\¢':$¢P

, ,,...•it.ru;z:z:u;:;::

•

ELECTRICAL CHARACTERISTICS

s:

o

Test procedures are shown for only one

W

...a

line driver. The other line driver is tested
in the same manner. Further, test proce·

N

dures are shown for only one input of the

,t»

line driver being tested. To complete tast·
ing, sequence through remaining inputs.

s:
o

~~:

~
N

3~4

t»

g

11=0-[:
12
13

:J

~,

:J

C

10

CD

~

TEST CURRENT !VOlTAGE VALUES
@Test
-SSOC

MC3128

MC3028

MC3128 Test limits
55'C I +25'C I + 125'C

Pin
Under
Symbol

Characteristit

Tes'

Min

I

I Max I Min I Max I Min I Max I

Leakage

Cur~nt

BTeakdown Voltage

I

Clamp Voltage

'Fa

-2.0

IR

50

Short-Circuit

Current

-2.0

50

50

-2.0

50

-1.5

VOL 1

0:4

VOL 2

0.5

-1.5

0.4

I -

V OH

2.4 I -

Ise

-40 I -100 I -40

~2.0

-2.0

,.,

Vn

I

0.5

I 2.4 I 1

-100

0.4

0.4

I - I

0.5

I 2.4 I -100

1011

'OlC

IOHA

10NB IOHC

16

2.0

2.0

_1.8

-0.1

-0.1

-0.1

+2S C

16

2.0

16

2.0

oae

16

I - I

-

I

0.5

J

I

I -100 1 -40 1 -100 1

-

I 2.5 I -

VIL

VIN

VF

VI

VIN

1.1

2.0

0.4

2.4

4.0

Vnou

Vee

Veei

VeeH

5.0

4.5

5.5

2.0

-1.8

-0.1

2.4

4.0

4.5

5.5

2.0

-1.8

-o.r

-0.1

0.8

1.8

0.4

2.4

4.0

5.0

-1,8

-0.1

-0.1

1.1

2.0

0.4

2.5

4.0

5.0

4.75

5.25

1.1

1.8

0.4

2.5

4.0

5.0

4.75

5.25

'0.9

1.8

0.4

2.5

4.0

5.0

4.75

5.25

I Vee

VCCL

Vee"

+2SoC

16

2.0

2,0

-1.8

-0.1

-0.1

16

2.0

2.0

-1.8

-0.1

-0.1

1.0

1.0

-10

-10

1.1

1.8

0.4

7.0

7.0

5.0

I",.

lOLA

lo.e Ii0MA

loo.llo.,e

II. I I. I V" I V," I V, I

V,

VRH

V_.

2.3*

I mAde

2.5

V1HX

14

2,3,7

Vdo

14

2:,3,7

14

6,7

14

4·

I Vdc

2,3*

14

2,3'"

14

2,3'"

14

1,2,3'"

-40 [ -100 [ mAde

Power Requirements:

~?J~~o;=~
·1
SUpply Current

SwitChing
Parameters

1_

1

14

1 - 1 - 1- I

18

I - I - 1- I - I - I

18

I - I - I mA'" I - I - I - I - I - I - I . I - I - I - I - I - 11U;~i3 I

Pulse
In

Turn-On Delay

t pd _

1,6

Turn-Off Delay

'pd.

"

1,6

12

"'Since this is a non-inverting gate, power drain is min1mLzed by tying tbe inputs to gates
not under test to VRH •

"
12

Gnd

14

/LAde

0.5 J Vde

I 2.5 I -

V1HX

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,

0.4 I Vdc
I - I

I 2.5
-40

fD

Vdo

0.4

0.5!

lin

2.0

+7S oC

T

,.,

BV in

Output
Oltput Voltage

-2,0

\

lOlA

+12So C

o

MC3028 Test Limits
O'C
+25'C I +75'C
Min I Max Min I Max I MinJ.r.la><.l Unit

Input
Forward Current

[

Volts

mA

Temperature

I

14

Pulse
Out

14

2,3

14

2,3

MC3100/MC3000 series

DUAL 3-INPUT 3-0UTPUT
"NAND" SERIES TERMINATED
LINE DRIVER

I

MC3129F • MC3029F
MC3129L • MC3029L,P

This device is a dual 3-input/3-output series-terminated
NAND line driver that minimizes switching transients on long

CIRCUIT SCHEMATIC
1/2 OF CI RCUIT SHOWN

lines by approximating line impedance. Two outputs are pro·
vided through 75-0hm resistors for use when driving 93 to
120-0hm lines. These outputs should be paralleled when driv·
ing 50 to 93-0hm lines. In addition, an output is provided
directlv at the gate output node for driving adjacent gates.

Vee
14

800

2.4 k

60

11
12
13
2
3

=L>-E

Positive Logic: 4, 6, 6

Negative Logic: 4, 5,6

98

10

=~
=1 + 2 + 3

Inp.ut Loading Factor:: 1
Output Loading Factor, Direct Output (Pins 6 and 8) =
8 Minus The Number of Resistor~Terminated Outputs
Being Used.

7
Gnd

Output Loading Factor. Resistors (Pins 4, 5, 9 and 10)
Total Power Dissipation

= 44 mW typ/pkg

Propagation Delay Time = 6.0 ns typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.5 Vdc

Vee

280
t-

7.0 ns
1.----~+=~-3.0

MMD6150

PULSE
GENERATOR

V

or Equiv

OV
PRF: 1.0 MHz typ
PW : 50% DUtv
t+ = 7.0 ns
t-

Cycle

50

MMD7000
or Equiv

= 7.0ns

tP~_
tPd+.

2:2.4 V

TPout

1.5 V

---SO.4 V
Gnd

CT = 25 pF = total parasitic capacitance, which includes probe, wiring. and load
c;:apacitances.
The coax delays from input to scope and output to scope. must be matched.
The scope must be terminated in 50·ohm impedance. The 9SO·ohm resistor
and the $Cope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be C-r -070-50 or equiva.ent.
See Genera' I nformation section for packaging.

;:, !i#

;

iA

;4

,qs;::;q;wa

4F

=1

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one
line driver The other line driver is tested
in the same manner. Further, test prace·

CAl
.....

N
.CD

cures are shown for only one input of the

s:
(")

line driver under test. To complete testing
sequence through remaining inputs.

~
~

1~:

0o

3~4

:::J

~­

:::J
C

"=0£:

CD

a.

12
13

10

TEST CURRENT/VOLTAGE VALUES
@Test
Temperature

j

-5S
MC3129 +2S oC
+12S oC
0

t

MC3029.

Input
Forward Currellt

Leakage Current
Breakdown Voltage

-2.0

IF
I.

I

Clamp Voltage

-2.0

-2.0

50

50

50

50

2.0

16

2.0

2.0

-0.1

-0.1
5.5

I +2S C
t +75°C

5.25
5.25

2.5

VeeH

V"",

o

I

TEST CURRENT I VOLTAGE APPLIED TO PINS LISTED BELOW,

Unit

10..

I..LI l'Olc I'.....

'CHI

i.... c I 1m I

I.

I V,r I V,. I V,

V..

V,

Vmu

I Vee

Vcc,

a,3,7*

Vd'
~l.

Vd,

5

14

l'

1*

0.4

0.'

0.'

0.4

0.'

0'.4 , Vdc

2,3

14

0.5

0.5

0.5

0.5

0.5

O.S

I Vdc

2,3

14

Vd,

2,3

Ise

2.4

2.4
·100 I ·40 I ·100

2.5
~100

1*

2,3,7*

~Adc

VOL 1

2.4

Gnd

14

2,3

VOL2
VOK

Z.5

5.5

2.0

-2.0

5.5
·1.5

Output

Short·Circult
Current

-2.0

5.5

BV in

VD

O-itput Voltage

-2.0

VtHX

16

5.25

I

Pin
Test'---1-="--'-='-'-'=.L

(

Volts
lOlA

ifC

MC3029 Test Limits
+2SoC
+ 75°C
Min ! Max Min I Max

Un~r C-~~~~~~~~~~~~

Symbol

Characteristic

2.5

2.5

.,
1*

1,2,3,6,7*

14

-40 I ·100 I -40

POW*" Requirements

~J,~~:;lf'

I

Imu

I

14

I - I - I - I

12

I - 1 -

I - 1 - 1 - 1 "

SWitdoing
Parameters
Turn-On Delay
Turn-Off Delay

s:

(")

1 - 1 -

1mAd, I

-

1 -

1 - 1

-

1 -

1 -

1 -I - 1 - 1 - 1 - 1

-

1

-

1 "

1 - 1 -

1 -

1

-

Pulse-, Pulse
In

'pd-

1,6

10

'pd.

1,'

10

*Slnce this is an inverting gate, power drain is minimized by grounding the inputs to gates not under test.

10

Out

14

2,3

14

2,3

1

:,~,~::;

.*
l'

MC3100/MC3000 series

DUAL 4·INPUT EXPANDER
FOR "AND·OR·INVERT" GATES

MC3130F • MC3030F
MC3130L • MC3030L,P
(54H60J)

(74H60J,N)

This device consists of two independent 4·input
AND gates. The outputs of each gate are available as
ORing nodes. Using the MC3030/3130 expander, with
the MC30;20/3120 expandable gate, up to four AND
gates can be ORed together.

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

Vcc
14

2.4 k

Collector

12

lJ~ __~12
1
2
3

20--+.
J

___ ~ 11
Emitter

Emitter

:~ __~,o

o--4-H

6

13C>--H-+...

__~9

ollector '

B

Input Loading Factor = 1
Full output loading factor of the expandable

gate is maintained.
Total Power Oissipatipn = 15 mW typ/pkg
Propagation Delay Time:
.a.tpd = +1.0 ns typ
When added to the expandable
,. AN D·D R·I N VERT" gate.
.6.tpd/pF = +1.0 ns pF typ
Caused by additional capacitance
at expansion points.

7
Gnd

APPLICATION: EXPANDABLE 2·WIDE 2·INPUT AND·OR·INVERT GATE
WITH A DUAL 4·INPUT EXPANDER CONNECTED

,

13

~ ...l_I"'---'---'

Collector

~-7-'r-,-___ J

g=C~--»-~M

I

I

}

___ JI

EXPANDER
MC3030

Positive Logic:
8 - (9.10) + ( 13.1) + l13. 1.2.3) + (4.5.6.8)

r----- ---, }

: '- ________J.
See General I nformation section for packaging.

~---~vr---~

Expandable Gate
EXPANDABLE
GATE
MC3020

Expander

I

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

.....
Co\)

expander, The other expander is tested in
a similar manner. Further, test procedures
are shown for only one input of the

sC"')
Co\)

o
S

ex~

pander being tested. To complete testing,
sequence through remaining inputs.

(")
Co\)

oCo\)
o

Collector

13~ __~12

~

___ \. 11

3

Emitter

c;O

:::J

!:!'.
:::J

Emitter

C

~~__
__"'0
6
\.9

~

Col! ector

Test
Temperature

V,

TEST CURRENT/VOLTAGE VALUES
Volts
Vm• x
V"
V'H V, VEE1 VEE2 V,H

2.4

4.0

0.4

1.10 0.80

2.0

1.1

-10

2.4

4.0

0.4

0.95 0.65

1.8

1.1

-

2.4

4.0

0.4

0.75 0.45

1.8

8.0

-

2.5

4.0

0.4

1. 00 0.70

8.0

1.0

-10

2.5

4.0

0.4

6.0

-

-

2.5

4.0

0.4

mA

@

Ie

lin

-55'C
MC3130 +25'(
+125'(

6.0

-

6.0

1.0

0'(
+25'(
+75'(

M(3030

j

(haracteristic

'nput
Forward Current
Leakage Current
Breakdown Voltage

Clamp Voltage

Symbol

Pin
Under
Test

IF

1

IR

1

BVin

1

VD

1

M(3130 Test Limits
55'(
+25'(
+125'(
Min Max Min Max J .Min I Max

L
I

Output
Output Voltage

VOL

12

Emitter Current

lEO

11

Collector Current

leo

12

Power Requirements
(Total Deyice)
MaJdmum Power
Supply Current

Power Supply Drain
'-----

I""",

14

IpDL

14

* Ground inputs to gates not under test unless
** The inputs to both gates are ungrounded.

-

50

-

-

-2.0

M(3030 Test Limits
0'(
+25'(
+75'(
Min Max Min I Max I Min Max

-

-

-2.0

50

-

50

5.5

-

-

-

-

-1. 5

-2.0

-2.0

Vdc

-

1

1.25

Vdc

-300

.uAdc

300

.uAdc

-

-

mAde

-

4.5

mAde

-

300

-

300

-

-

-

7.0

4.5

-

4.5

--

-

-

1.4
-300

otherWise noted.

1

-

-

-

Vdc

-1. 5

-

4.5

-

-

1.15

-

JlAdc

-

-300

4.5

50

-

-

7.0

-

-

-

-

1.35
-300
300

-

'.

mAde

5.5

1.35

lin

-2.0

-

-300

-

Ie

-

-

4.5

Unit

50

-

10

VCCl

VCCH

4.5

5.5

7.0

4.5

5.5

0.8

-

4.5

5.5

2.0

1.1

-

4.75

5.25

0.95 0.65

1.8

1.1

7.0

4.75

5.25

0.85 0.55

1.8

0 .•

-

4.75

5.25

VCCL

VCCH

-

14

7'

14

2,3, 7,

14

2,3,7,13*

TEST (URRENT I VOLTAGE APPLIED TO PINS LISTED BELOW,

-

1.5

300

-

6.0

50

-300
300

-

-2.0

t
t

12

-

-

V, V'H
1

-

-

-

-

-

-

V,

2,3,
13

1

-

-

-

-

-

VEE1 VEE2

V"

Vm• x

-

-

-

-

-

-

-

-

-

14

-

I

11

-

V,H
-

-

14

-

12,14

1

-

12,14

11

-

11

-

1

-

-

-

-

-

14

-

-

-

-

-

-

Gnd

13~

7'

7'

-

7"
7'

1,2,3,4,5,
6,7,8,13

-

14
-

1,2,3,4,5,
6,7,8,13

MC3100/MC3000 series

EXPANDABLE 4·WIDE
2·2·2·3 INPUT
"AND-OR" GATE

MC3131F • MC3031F
MC3131L • MC3031L,P
(54H52J)

(74H52J, N)

This device consists of three 2·inputAND gat~s and one 3input AND gate ORED together to provide the AND·OR function. A single expander pin is available which provides the
capability to expand this gate to • 1o-wide AND·OR gate using
the MC3119/3019 triple expander.

CIRCUIT SCHEMATIC

2
3
4
5

8

10
11
12
13

Collector

9

Input L.oading Factor

=1

Output Loading Factor"" 10
Total Power Dissipation"" 87.5 mW tvp/pkg

Propagation Delay Time = 10 ns typ

Pin numbers for the 54H52F/74H52F device are

shown in the chart.

These devices are available on

special request.

DEVICE
MC3131F,L/3031 F,L,P
54H52F/74H52F

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIH

Vee

+2.5 Vdc

t+
7.0 ns

280

,-

7.0 ns

1r--~~-==-3.0 V

PULSE
GENERATOR
PRF = 1.0 MHz ,yp
PW = 50% Duty Cycle
t+ = 7.0 ns

t-

OV

TP out

t~pdtpd+

MMD6150

2:2.4 V

or Equiv

TP out

= 7.0 ns
MMD7000

1.5 V

----===_-c:-~c::_=~~d4

or Equiv

Expander pins should be left open when measuring switching times.

CT "" 25 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 9SG-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT-070-50 or equivalent.

V

I

•

ELECTRICAL CHARACTERISTICS

3:
C')

w

Only one input of the expander is being tested.

To complete testing, sequence through remaining
inputs.

~

w

~

1

4
5
10
11
12
13

8

mA
101

10H

Ii.

ID

Ix

V,

VIL

V'H

VOH

Vx

Vo

20

-2.0

1.0

-

-0.3

0.4

1.1

2.0

4.5

1.0

2.4

MC3031 {

IF

IR

Breakdown Voltage
Clamp Voltage

VD

Expander Input
Current

~x

4.5

5.5

+25:C

20

-2.0

1.0

-10

-0.3

0.4

1.1

2.0

4.5

1.0

2.4

4.5

5.5

20

-2.0

1.0

-

-0.3

0.4

0.8

1.8

4.5

1.0

2.4

4.5

5.5

W

J
7.0 I
- I
-

O°C

20

-2.0

1.0

-

-0.3

0.4

1.1

2.0

4.5

1.0

2.5

4.75 5.25

-

+25°C

20

-2.0

1.0

-10

-0.3

0.4

1.1

2.0

4.5

1.0

2.5

4.75 5.25

7.0

+75°C

20

-2.0

1.0

-

-0.3

0.4

0.9

1.8

4.5

1.0

2.5

4.75 5.25

10H

lin

~

0o
:::I

~.

:::I

c::
~

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

-2.0

-2.0

50 I 5. 5

BVin

~

Veel VeeH Vm . .

+12SC

Pin

Forward Current

C')

-55"C

Under ~~:....:..-+--'=r'---~:--r':""':'-I-"'--"-'-'--+CC:"--'~-+=---r:::--i
Symbol I Test

Reverse Current

Volts

@Test
Temperature
MC3131 {

Collector 9 - - - - - - - - - '

characteristic
Input

s:

TEST CURRENT /VOLT AGE VALUES

2
3

I -

15.5

-2.0

I 50

I

I -

I 5.5 I -

~1.

-

I 50

~2.

I

-

0

I 50

I 5.5 I -

-2.0
I -

I 50

I 5. 5 I -

Ix

I V, I VIL I V'H

VOH

Vx

I Vo I VCCL I VeeH IVm••

-2.0 ImAde
I -

I 50

I 5. 5 I

-

-1.5

5

ID

Gnd

14

I "Ade

14

2,7

I Vde

14

2,7

Vde

14

-2.7 I -4.51-2.71-4.51-2.71-4.51-2.91-5.351-2.91-5.351 -2.9 I -5. 351mAde

1,2,3,4,5,
7,10,11,12,13

14

Output
Output Voltage

VOL

VOH

Short-Circuit Current I

8

0.4

0.4

0.4

0.4

0.4

0.4

I Vdc

0.4

0.4

0.4

0.4

0.4

0.4

I Vdc

2.4

2.4

2.4

2.5

2.5

2.5

Vde

2.4

2.4

2.4

2.5

2.5

2.5

Vde

2,4,5,

1,3,
10,12

14

11,13

1,2,3,4,5
10,11,12,13
1,2

14
14

3,4,5,7,10,11

14

1,2,3,4,5.
7,10,11,12.13

12,13

Isc

-40 I -1001-40

I -100 I -40 I -100 I -40 I -100 I -40 1-100 I -40 I -100 ImAde

1,2,3,4,5
10,11,12,13

14

7,8

Power Requirements
Max Power Supply

Current
Power Supply

Dr~n

14

lmax

34

34

IpDH

I 14

31

IpDL

I 14

24

14 I 1,2,3,4,5,7,

mAde

10,11,12.13

31

31

31

31

31

~mAdc

14

24

24

24

24

24

I mAde

14

1,2,3,4,5
7,10,11,12,13

Pulse Pulse
In
Out

Switching Parameters
Turn-On Delay

t1>d_

I

1,8

15

15

Turn-Off Delay

tpd+

I

1,8

15

15

ns

14

3,4,5.7.
10,11.12.13

14

3,4,5,
7,10

MC3100/MC3000 series

EXPANDABLE
4-WIDE 2·2·2·3·INPUT
"AND·OR·INVERT" GATE

MC3132F • MC3032F
MC3132L • MC3032L,P
(54H53J)

(74H53J, N)

This device consists of four 2·2·2·3·input AND gates
ORed together and inverted. Up to four MC3120/3020
or one MC3118/3018 expander gates may be ORed
with the device at the expander points.

CIRCUIT SCHEMATIC

12

14

Vcc
2.8 k

2.8 k

2.8 k

•

2.8 k

13

760

58

2

13 0..1 0-2
3

T.'

.~

3

~~~~~

T.l~

I

8

4
5

8

6

h.

9
10--""1.._"/
Emitter 1 1 - - - - - - - - - - - - l

4
500

5
6
9
10

250

Collector 1 2 ' - - - - - - - - - - - - - - '

l

Positive Logle :'
8"'(13 -I) + (2-3) + (4-5-6)+ (9-10)+ (Expanders)
4k

Negative Logic:
8 - 13 + 1) - (2 + 3) _ (4

+ 5 + 6) -

(9 + 10) - (Expanders)

Gnd

11

I nput Loading Factor;;; 1
Output Loading Factor = 10

Total Power Dissipation = 40 mW typ/pkg
Propagation Delay Time = 7 ns tYP

Pin numbers for the 54H53F/74H53F device are

DEVICE

shown in the chart. These devices are available on

MC3132F.L/3032F.L.P

special request.

54H53F174H53F

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc

VIH
+2.5 Vdc
Coax
950

280

±.1.0%

t+

t-

7.0 ns

7.0 ns

!r---.J-+=;;;-- 3.0

V

PULSE
GENERATOR

OV

TP out ·
PRF - 1.0 MHz typ
PW - 50% Dutv Cycle

tP~_.
.
.. tPd+
:l!:2.4V

)O-4'---+oIf---c..... MMD6150
or Equiv.

t+=7.0nl
t- = 7.0 ns

TPout

1.5 V

___--===:....-_-----~~d4 V

MMD7000
or Equiv.

Expander pins should. be left open ,when measuring switching times.
CT '"" 25 p'F :o:::ltot81 parasitic ,capacitance, which includes probe. wiring, and load

capacitances.
The ,CO~X delays from input to

scope

and ~utpUt to scope must be matched.

The scope must be tenninated in 50-ohm,impedance., The 9SO-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuatar probe, Coax

shall be CT -070-50 or equivalent.
See General I nformation section for packaging.

-~-,.,..------,....~~,.-••----.....",..,.---..,..-,.......~...
".,..
-.~......
Q_....- - -........,.............---------~---------

•

ELECTRICAL CHARACTERISTICS
Tast procedures are shown for one input
of the device. To complete testing, se-

:s:
0

...
Co.)

quence through remaining inputs in the

same manner.

Co.)

,N

s:
0
Emitter 11
Collector 12

Characteristic
Input

MC3132 Test Limits
55 to +125'C
Min
Max
Unit
-2.0

-

IF

1

curre~~

IR

1

50

pAdc

BVin

1

5.5**

-

mVdc

5.5**

Clamp Voltage

Vo

1

-

-1. 5**

mVdc

-

Expander Input Current

lEX

12 Q)

-5.85

Base-Emitter Voltage

V BE

11@

-

VOL

8

-

Breakdown Voltage

Co.)

MC3132
MC3032
MC3032 Test Limits
Oto +75'C
Min Max
Unit

Forward Current

Leakage

0

\\

lD

Pin
Under
Symbol Test

Co.)

8

4
5
6
9

mAde

-2.0

50

10L

10H

lin

rnA
ID
IXI

20

1 -2.0

20

1 -2.0

1.0
1.0

-101 0.7
-101 1.1

0-

v,iYf

0.32
0.57

V"

Vee VCCl VCCH

-0.32

-0.47

63

1.4 1 0.4 1 2.4 1

4.0

1 2.01

0.8

-0.57

-0.6

68

1. 4 1 0.4 1 2.4 1

4.0

J 2.01

0.8

5.0
5.0

Vee VeCL VCCH

4.5
4.75

0

::J

5.5

~.

5.25

c:

::J
CD

TEST CURRENTIVOLTAGE APPLlEO TO PINS LISTED BELOW,
10L

10H

mAde

-

MAde

-

-

mVdc

N

TEST CURRENTIVOLTAGE VALUES (All Temperatures)
Ohms
Volts
VRH
1)(4 R.xli
V, V.
IX.
IX.
V'H

I'n

ID

IXI

1)(2

-

-

-

-

-

-

-

1

-1. 5**

mVdc

mAde

-6.3

mAde

8

-

1.0

Vdc

1.0

Vdc

8

-

0.4

Vdc

-

0.4

Vdc

8

-

0.4

Vdc

-

0.4

Vdc

-

-

Vdc

2.4

8

-

8

-

1

-

-

-

-

-

11

12

-

-

-

-

-

-

-

-

11,12

-

-

-

-

-

-

R,x(3; V,xC!

1)(4

Ix>

-

-

12

-

-

-

11

12

-

-

-

-

V,

V.

1

VRH

V'H

V"

13

-

-

-

1

-

-

-

-

-

-

-

-

-

-

-

-

-

.e:
Gnd

14

141

-

-

2,3,4,5,6,
7,9,10,13

-

14

1,2,3,4,5,6,
7,9,10,13

-

-

-

14

1,2,3,4,5,6,
7,9,10,13

1,13

-

-

14

2,3,4,5,6,
7,9,10,13

14

14

Output
OUtput Voltage

8@
V OH

Short",Cireuit Current

I

8

2.'

Vdc

Vdc

2.4

8

-20

-55

mAde

-18

-55

mAde

IIPDH

I.

-

14

mAde

-

I.

mAde

IpDL

14

-

11

' mAde

-

11

mAde

1lsc

2 .•

Vdc

8

-

-

-

-

-

-

1,13

-

-

-

3,5
10,13

-

1,2,4,9

-

14
14

-

-

-

-

-

-

-

-

1,2,3,4,~

-

I -I
-

1 -

1 13

Power Requirements
Power Supply Drain

Switching Parameters

I

Turn-On Delay

1 tpd_t

Turn-Off Delay
"'*Tested only at 25 QC

CD

See Figure 1.

®

See Figure 2.

@ See Figure 3.

Pulse
In

tpd+i

1,8

-

1,8

l' Expander pms open

11**
11**

ns
ns

-

11**
11**

ns
ns

1
1

-

-

-

-

-

5,9,10,13

-

-

8

l -

1 -

1

-

1 -

-

-

1

1

-

-

1

-

-

1

-

-

13

1

1

-I
-

2,3,4,5,6,
7,9,10

14

1

1,2,3,4,5,6,
'1,9,10,13

I-I

- I.

-I

- 114

-

-

Pulse
Out
8

-

-

114 1

-

I.

14

1,2,3,4,5,6,
7,9,10,13
1,2,3,4,5,6,
'1,8,9.10,13

1 1,2,3,4,5,6.
7,9,10,13

-I - I
-

-

2,3,4,5,6,
7,9,10
2,3,4,5,6,
7,9,10

MC3132, MC3032 (continued)

I
FIGURE 2 - VBE TEST CIRCUIT

FIGURE 1 -lEX TEST CIRCUIT

------..,I
I
I
I

lEX

+

-=-

~-

VEX

FIGURE 3 - VOL TEST CIRCUIT

lr------..,
I
I
I
I

8

•

MC3100/MC3000 series
4-WIOE 2-2-2-3-INPUT
"ANO-OR-INVERT" GATE

MC3133F • MC3033F
MC3133L • MC3033L,P
(54H54J)

(74H54J,N)
This device consists of four 2-2-2-3-input AND
gates ORed together and inverted.

14

Vcc
2.8 k

n
1:3
1
2
:3

~
~

2.8 k

2.8 k

7JlT. 1

2.8 k

1:3

760

~

I

58

~~
I

2
:3

5
8

6
9

f...

10---.._../

4

Positive Logic:

500 250

5
6

l

9

10

8

4

8

= (13

'1) + (2' 3) + (4.5 .6) + (9 '10)

Negative Logic:
8 = 13

4k

+ 1)' (2 + 3)' (4 + 5 + 6). (9 + 10)

Input Loading Factor = 1
Output Loading Factor = 10

Gnd

Total Power Dissipation = 40 mW typ/pkg

Propagation Delay Time = 7 ns typ

Pin numbers for the 54H54F174H54F device are

DEVICE

shown in the chart. These devices are available on
special request.

MC313:3F.L/3033F,L,P
54H54F174H54F

9

1

10 11
14

12 13
2:3

14
4

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX
+2.4 V

Vcc

,+

280

7.0 ns

,-

7.0 ns

ir---J-t-:=;--3.0 V

MMD6150

PW = 50% Duty Cycle
t+=7.0ns

t-=7.0n5

or Equiv

OV

tP~_
'pd+
«2.4V

50
MMD7000
or Equiv

CT := 25 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delavs from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General Information section for packaging.

TPout

1.6 V

----==='--=-::::-=-~~d4

V

:s:
n

ELECTRICAL CHARACTERISTICS

w
.w

Test procedures are shown for only one
input of this device. To complete testing,
sequence through remaining inputs in the
same manner.
13
1
2
3
4
5

:s:
n

w
~

8

w

~

Characteristic

Pin
Under
Symbol Test

Input
Forward Current
Leakage Current
Breakdown

,W

Volt~ge

Clamp Voltage

IF

1

IR

1

-

BVln

1

VD

Short-Circuit Current

-1. 6

1.0

-10

0.4

2.4

4.0

2.0

0.8

5.0

4.5

5.5

[

20

-1. 6

1.0

-10

0.4

2.4

4.0

2.0

0.8

5.0

4.75

5.25

VR

VRH

1

-

-

1

IOL

IOH

I;.

ID

VF

-

-

-

13

-

-

-

14

7

-

-

-

-

-

14

2,3,4,5,6
7,9,10,13

-

-

-

-

-

14

2,3,4,5,6
7,9,10,13

-

-

-

14

-

7

-

1,13

-

-

14

-

3,5,

-

1,2,4,9

-

14

-

7

-

-

-

-

14

1,2,3,4,5,6,
7,8,9,10,13

-

-

-

-

14

7
1,2,3,4,5,6
7,9,10,13

Vcc VCCL VCCH

MAde

-

50

MAde

-

5.5*·

-

mVdc

5.5"

-

mVde

-

-

1

-

-

-

1

-

-1. 5**

mVde

-

-1. 5

mVde

-

-

-

1

-

-

VOL

8

-

0.4

Vde

-

0.4

Vde

8

-

-

-

VOH

8

2.4

-

Vde

2.4

-

Vde

-

8

-

-

-

Ise

8

-40

-100

mAde

-40

-100

mAde

-

-

-

-

-

-

-

IpHH

14

-

14

mAde

-

14

Ill:Adc

-

-

-

1,2,3,4,6,
5,9,10,13

14

-

11

mAde

-

11

mAde

"

-

-

-

-

IpDL

-

-

-

-

-

-

-

14

Pulse
In

Pulse
Out

-

Gnd

2,3,4,5,6
7,9,10

10,13

Tur_n-On Delay

t pd _

1,8

-

u**

ns

-

11**

ns

1

6

-

-

-

13

-

-

-

14

-

-

Turn-Off Delay

tpd+

1,8

-

11**

ns

-

11

**

ns

1

6

-

-

-

13

-

-

-

14

-

-

"Tested only at 25°C

!::

V1L

-2.0

Switching Parameters

::J

V1H

-

mAde

::J

!:!'.

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:

mAde

-2.0

Power Requirements
Power Supply Drain

20

50

Output
Output Voltage

MC3133 Test Limits
SS to +12SoC
Min
Max
Unit

MC3133
MC3033
MC3033 Test Limits
oto +7SoC
Min Max
Unit

g

IOL

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
rnA
Volts
VF
VR
VRH
V1H V1L Vcc VCCL VCCH
I;.
ID
IOH

2,3,4,5,6
7,9,10
2,3,4,5,
7,9,10

•

•

MC3100/MC3000 series

EXPANDABLE 2-WIDE 4-INPUT
"AND-DR-INVERT" GATE

MC3134F e MC3034F
MC3134L e MC3034L,P
(54H55J)

(74H55J, N)

14
VCC

9

2.8 k

2.8 k

This device consists·of two 4-input AND gates ORed
together and inverted. The emitter and collector nodes
of the OR stage are brought out to provide expansion
capability to a 6-wide AOI gate using the MC3130/3030
or MC3118/3018 expanders.

760

58

2
3
4

8

10
11

8

12

2
3
4

13

5--------------~
9----------------~

10o-+-t+l---""'"
11 o-n-+-+------H
12o-~rt_r-----+--H

Positive Logic:

13o-~rt_r-----+-n~

8= (1 e2e3e4)+ (10ell e12e13) + (Expanders)

Negative Logic:
8 = (1 + 2 + 3+ 4)e (10+ 11 + 12+ 13) e (Expanders)

GNO
5

Pin numbers for the 54H55F174H55F device are
shown in the chart. These devices are available on
special request.

7

I nput Loading Factor == 1
Output Loading Factor = 10
Total Power Dissipation = 30 mW typ/pkg
Propagation Delay Time = 7.0 ns typ

DEVICE
MC3134F,Ll3034F ,L,P

8

9

10 11

5

54H55F174H55F

6

12 13 14
784

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VIHX

Vcc

+2.5 Vdc

280
t+
7.0 ns

t-

7.0 ns

....--.J--+=~3.0 V

MM06150
or Equiv

OV
PAF: 1.0 MHz typ
PW

= 50% Duty Cycle

MMD7000
or Equiv

t+ ;: 7.0 ns
t-=7.0n5

1--1

t~
1~+~2.4V
~-

TP out

-----====-=-=-=-=-=-~~d4

CT

= 25

pF

=total parasitic capacitance, which includes probe, wiring, and

capacitances.

load

'

The coax delavs f;om input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 9SO-ohm resistor
anu the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.
See General I nformation section for packaging.

V

ELECTRICAL CHARACTERISTICS

s:

(")

Test procedures are shown for only one

W
....

input of the gate under test. To complete
testing, sequence through remaining inputs.

.~
s:
(")

2
3
4

~

W

10
11
12
13

.jlo.

nO

TEST CURRENT /VOLTAGE VALUES (All Tamparaturas)
Ohms

5-----9------

::J

~.

VCCH

MC3134
MC3034
MC3034 Tast limits
o to +75°C
Min I Max I Unit

Characteristic
Input
Forward Current

-2.0

mAde

Leakage Current

50

)..lAde

::J

5.5

C

5.25

a..

CD

TEST CURRENTIVOlTAGE APPLIED TO PINS LISTED BElOW,
10l

10H

I;"

10

I

IXl

1X2

1X3

IX4

I REX'@I

VEX(j)

I

V,

I v.

V'H

VCCH

2,3,4

14
14

Gnd

2,3,4.7,

10,11,12,13
Breakdown Voltage

14

Clamp Voltage

Vdc

Expander Input Current

-6.3

mAde

Base-Emitter Voltage

1.0

Vd,

0.4

Vd,

0.4

Vdc

5,9

2,3,4,7,
10,11,12,13

7

14
14

1,2,3,4,7,
10,11,12.13

14

1,2,3,4,7,
10,11,12,13

14

7,10,11,12,13

14

1,2,3,4,7,
10.11,12.13

Output
Output Voltage

VOL

I

VOH

I

1SC

I

8@

0.4

Vd,

0.4

Vd,

2.4
2.4

Short-Circuit Current

·40

-100

Vd,

2.5

Vdc

2.5

mAde

·40

1,2,
3,4
1,2,
3.4
2,3,4,
11,12,13

Vdc

.

I .

14

I 1,10

14

Vdc
-100

mAde

1,2,3,4,.7.
10,11,12.13

14

1,2,3,4,7,
10,11.12.13

Power Requirements
Power Supply Drain

IPDH

14

12

IpDL I

14

6.4

1,8

11**

14

1,2,3,4,10,
11,12,13

14

1,2,3,4,7,
10,11,12,13

Switching Parameters

In
Turn-On Delay

tpd_**

I

14

7,10.11,12,13

14

7,10,11,12,13

111"1

Turn-Off Delay

t pd +**11,8

11**

I

I

11 **

**Tested only at 25~C

CD

See Figure 1.

CID See Figure 2.
@ See Figure 3.

II

•

MC3100/MC3000 series

"AND" J-K FLIP-FLOP

MC3150F • MC3050F
MC3150L • MC3050L,P
Information may be applied to, or changed at the J and K inputs
any time in a clock cycle, except during the interval of time between
the Set up and Hold times. The inputs are inhibited when the clock
is high; data is entered into the input steering section of the flip-flop
when the clock goes low. The input steering section of the flip-flop
continually reflects the input state when the clock is low. Data present during the time interval between the Set up and Hold times is
transferred to the bistable section on the positive edge of the clock
and the outputs Q and
respond accordingly. The flip-flop can be
set or reset directly by applying the high state to the SET or RESET
inputs.

This J-K flip-flop triggers on the positive edge of the clock. An
AND input geting configuration formed by three J inputs AN Oed together and three K inputs ANDed together, minimizes the requirements for external gating. The enable input (JKI consists of a J and
8 K input internally connected together. This input provides gating
for the J and K inputs or an additional logic input for use in counters
or other applications. A direct SET and RESET are provided to permit presetting data, such as initial conditions into the flip-flop. The
direct SET and RESET fully override the clock; i.e., the direct SET
and RESET control the operation of the flip-flop regardless of the
state of the clock.
SET

a

9'-----------,

J3 4

LOGIC DIAGRAM
RESIOT

J2 3
Jl 2

8

CLOCK 13+----1
JK 1

Input Loading Factors:
J, K, SET, RESET = 0.75

CLOCK, JK

= 1.5

Output Loading Factor == 10

Kll0

6

K211
K312
RESET

5------..J
J=J1.J2.J3_JK
K = K 1 • K2. K3. JK

TRUTH TABLE

, ,

SET

Q"

a nol

, , ,
,, , ,, ,,
,,
,

0
0
0
0

0
0

0
0

Typical Characteristics (Vee = 5.0 V, TA

Logical "1" Setup Time

= 10 ns

Logical "0" Setup Time"" 5.0 ns
Logical "1" and "0" Hold Time = 5.0 ns

0

tpd_ = 12

0

0
0

tpd+

ns

= 14 ns

0

0

0

14

VCC

5

6C>---~-------4

5c>-~--I+-J

r

Gnd

7

Q

~---~---O8

'---~-

SET
__--o 9

CLOCK
13~~-~+---------~--------+--

Jl

2o-~---+~JII'(1

J2 3 ~+-Jl
J2

K1o--~-,

J3

K3

4k

4k

5

7
Gnd

B

6

Q

a

13

9

a::OcK

Se.08".rIl1 Information .ctlon for packaging.

,.hap;;?;;:>#.....

"ax.

A 11M:

•

ELECTRICAL CHARACTERISTICS

mID
J3 12
J2 11
J1 10

CLOCK

JK

J

Q

w
~

U'I
~

8

@

K3
RESET

K

Cl

mAde
10H lin

10L

-S5"(

20.0

-2.0

20.0

-2.0

20.0
20,0
20.0

-2.0

20.0

-2.0

MC3lS1
6

4
5

Test

Temperature

13
1

~~ ~

MC30S1

t

+2S"C
+12S'C

t

O"C
+25"C
+75"C

Forward Current
K
J
JK
JK

Set

ReSel

Ci'Oci{

CIOCI{

Reverse Current
K
J
JK

'R

sa

Reset
CloCK

Breakdown Voltage
K
J
JK

BVill

Set
Reset
Clock
Clamp Voltage
K
J
JK

Vo

-1.5
-1. 5
-3.0

-1. 5
-1. 5
-3.0

-3.0
-4.0

-4.0

-4.0
-4.6
-4.6

-4.0

-4.6
-4.6

-1. 5
-1.5
-3.0
-3.0
-4.0
-4.0
-4.6
-4.6

50
50
100
140
140
145

50
50
100
140
140
145

50
50
100
140
140
145

-1.5

2
10
1
1
9
5
13
13

-1.5

-3.0
-3.0
-4.0
-4.0

2
10
1
9
5
13
2
10
1
9
5
13

-1.5
-1.5

-1.5 mAde
-1.5

-3.0

-4.6
-4.6

-3.0
-3.0
-4.0
-4.0
-4.6
-4.6

50
50
100
140
140
145

50
50
100
140
140
145

50
50
100
140
140
145

-3.0

0.4

1.1

2.0

2.4

4.0

4.5

5.5

5.0

1.1

1.8

2.4

4.0

4.5

5.5

5.0

-2.0

0.4

0.8

1.8

2.4

4.0

4.5

5.5

5.0

-2.0

0.4

1.1

2.0

2.5

4.0

4.75

5.25

5.0

0.4

1.1

1.8

2.5

4.0

4.75

5.25

5.0

0.4

0.9

1.8

2.5

4.0

4.75

5.25

5.0

1.0

ReSet

-10

I..

ID

-3.0

-4.0
-4.0
-4.6
-4.6

V,

V" V,H

VR

VRH

2
10
1
1
9
5

1,3,4,5,9,13
1,5,9,11,12,13
2,3,4,5,9,10,11,12,13
2,3,4,5,9, IO,H, 12,13
1,2,3,4,5,10,11,12,13

13

1,2J3J4,~,9, 10,11,12
1,2,3,4,5,9,10,11,12

VCCL VCCH

2
10
l'
9
5
13

"r

Voltage

Short Circuit
Current

rSC

0

~

7.0

~.
~

Vm . .

.

1

1

1
14

-1. 5

2

Vde

1

1

1

2
10
1
9
5
13

0.4
0.4

D••

0.4
2.4
2.4
-20
-20

2.4
2.4
-65
-65

-20
-20

0.4
0.4

-65
-65

-20
-20

0.4
0.4
2.5
2.5

2.4
2.4
-65
-65

-20
-20

-65
-65

0.4
0.4

0.4
0.4
2.5
2.5
-20
-20

2.5
2.5
-65
-65

-20
-20

-65
-65

Vde

1

l

14
14
14
14

Power Requirements
(TDtal Device)
Maximum Power
CUrrent

Gnd

14

Vde
Vde

mAdc
mAdc

(1)

1,3.4.5.7.9.13
1.5.7.11.12.13
2,3,4,5,7,9,10,11,12,13
1,2,3,4,7,10,11,12,13
1,2,3,4,7,10,11,12,13
1,2,3,4,5,7,9,10,11,12

1
-1. 5

c:

1.3.4.5.7.13
1.7.9.11.12.13
2,3,4,5,7,9,10,11,12,13
1.2.3.4.7.13
1.7.10.11.12.13
1,2,3,4,5,7,9,10,11,12

10

VOL
VOH

~

0-

14

Output
~tput

W
0
U'I

7.0

j

1,2,3,4,10,11,12,13

13

Vee

S
n

Vmax

14

Vde

5.5

5.5

1
9
5
13

Clock

VCCL VCCH VCC

0.4

10H

10

set

V,

TEST CURRENT!VOLTAGE VALUES
V.lts
V,L V,H VR
VRH

TEST CURRENT !VOLTAGE APPLIED TO PINS LISTED BELOW,

SV1"b.l~

'F

10

1.0 -10

Pin
Characteristic
Input

S
n

I;

7,13
7,13
7,]3
7,13

14
14

5,6,7
7,8,9

1,7,9,13
1,7,9,13

"'Momentary ground before making measurement. If pin number appears in other column, it should be returned to voltage.

.e:

MC3151, MC3051 (continued)

I
OPERATING CHARACTERISTICS
High state data must be present 12 ns prior to the fall of the clock and remain 5.0 ns afterthe clock signal rises.
Negative edge triggering: When the clock goes from the high state to the low state, the information in the input
steering section is transferred to the bistable section.
The direct SET and RESET inputs may be used any time, regardless of the state of the clock. If these inputs
are not used THEY MUST BE TIED to a voltage between 2.0 and 5.5 Vdc.

Unused Inputs:
JK input MUST be in the high state to enable the clocked inputs. When the JK input is not used, it should be
tied to a voltage between 2.0 and 5.5 Vdc.
Unused J inputs should be tied to used J inputs, the used JK input, a, or a voltage between 2.0 and 5.5 Vdc.
Unused K inputs should be tied to used K inputs, the used JK input, a, or a voltage between 2.0 and 5.5 Vdc.
Unused SET and RESET inputs MUST be tied to a voltage between 2.0 and 5.5 Vdc.

FIGURE 1 -MAXIMUM CLOCK FREQUENCY TEST CIRCUIT

VIHX = +2.5 Vdc

Vee
Coax

280
950
±1.0%
TP out

PULSE
GENERATOR

o----i"'/-.-..

t+=7.0ns
50

t- "'" 7.0 ns

Maximum Clock
Frequency = 40 MHz min
PW :: 50% Duty Cycle

CT

= 25 pF =total

r

MMD6150
or, EqUiv.

MMD7000
or Equiv.

• A load is connected to each
output during the test.

parasitic capacitance, which includes probe, wiring, and load

capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.

WAVEFORMS AND DEFINITIONS

TP out

•

MC3151, MC3051 (continued)

OPERATING CHARACTERISTICS (continued)

FIGURE 2 -SWITCHING TIME TEST CIRCUIT
(For J inputs and RESET input; to test other inputs. refer to Test Procedures Chart)

Letter designations
refer to waveforms

Coax

Vee

VIHX = + 2.5 Vdc

Coax

shown below:

280

9S0

950 ±1.0%

± 1.0%

B. e.D. E

TP out

MMD61S0

O---1,:::/-~--t or Equlv.
TPin
PA F = 1.0 MHz typ
t+ = 7.0ns
t- =

A

SO

MMD7000

7.0 ns

or Equiv.

=
F

Three pulse generators are required and
must be slaved together to provide the
waveforms shown.

• A load is connected to each
output during the test.

CT = 25 pF =total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance.

The 950-ohm resistor

and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.

VOLTAGE WAVEFORMS AND DEFINITIONS
A 3.0 V

1.S V

TEST PROCEDURES CHART
B 3.0

v--tr-,....-..I
I
I

OV

I

1.5 V

I
---:

tHold "1"

D3.0v~~ns
I
1.S V
OV

~tSet"O"

.

-.!

I
I

E 3.0 V

tHold "0"

r----

I

OV

"O
I

I

G 3.0V tPd •• 1

I

o V---+---'
I
I

H 3.0

V----i~r-.,

o

V "tpd ..

o.~q

J

tHold "1"

J

"ts.t"O"

J

SET"I RmT"1 K"I
2.4V

D

Gnd

G

God

~o.4V

:i!2.4 V

Gnd

!>:0.4V

~2.4V

J
Gnd

2.4 V

G

tHold "'" K

Gnd

2.4V

G

ts.t "0"

K

Gnd

2.4V

tHold "0"

K

Gnd

2.4 V

..,..

2.4V

I
I

"d··O··
1.5 V
----

l-J1.S V
W t S d "1"

'2

~2.4V

So.4V

~2.4V

~O.4

Oelev from CCOCK to Q during

DeI.V from CLOCK to Q during

'2

V

tset "1" J teSt.

CC6CK to a during Wt "1"

'2

'8

K tIIst.

Wt"'" J

tIIlt.

'8

D ....,from~to Q during tut"1" K test.

f.t",,,

I

I

D

M..
'2

2.4 V
2.4V

K

I

I

G

tHold "0"

500 ns==-t30 nsl._ _ __

R.

Min

ts.t"1"

",. ••0".

_\....3"1.5 V

a"

God

DeleV from

30 ns
I

ts.t-"1"

",.

o V -1"---;:....,
F 3.0 V

J"

TEST

e 3.0V~0.ns.,
OV

LlMITS(ns

INPUT

I--tSet "1"

I

~"O"

DeI.V from lET to

Q

durin"

Wt .""

K test.

"Dllev from

REiE'f to Qdurlngtut "'" J test.

DeIIV from

SeT to Q during ~ "1" K tut.
RElET to Q during Wt "'" J . .t.

DeJey from

··L.-tten thown In th.- column. mer to WlVWformi at tile left.

'8

'8

MC3100/MC3000 series

"ANO"INPUT JJ.KK
FLIP-FLOP

MC3152F • MC3052F
MC3152L • MC3052L,P
This is a master-slave J-K flip-flop that triggers on the positive edge
of the clock. The flip-flop has an AND input configuration consisting

Information is normally apl'l ied to, or changed at, the clocked
inputs while the clock is in the high state, since the inputs are inhi-

of two J-inputs and a J..input ANDed together and two K-inputs and

bited under this condition.

a K-input ANDed together. An enable input (JK) is also provided

master flip-flop section when the clock goes low. Once input data
has been stored in the master flip-flop section it cannot be removed
(or changad) by means of the clocked inputs. The direct SET or
RESET provide the only means of removing previously stored information. The state of the master flip-flop is transferred to the
slave flip-floP section on the positive transition of the clock and
the outputs respond accordingly. The flip-flop can be set or reset
directly by applying the low state to the direct SET or RESET

consisting of an additional J and K input internally connected tow

gether. This input provides gating in addition to the clock for the
clocked inputs (J, J, K and K) or an additional logic input (JK) for
use in counters or certain other applications. A direct SET and
RESET are provided to enable presetting data into the flip-flop such
as initial conditions. The direct SET and RESET control the operation of the flip-flop regardless of the state of the clock.

Information may be stored in the

inputs.

~
LOGIC DIAGRAM

J2
J1
CLOCK
JK
Kl

~----------~
12
4

6

9'i>~t---~

Input Loading Factors:
JK = 1.5
J, K, CLOCK = 0.75

SET. RESlrr = 2.25
Output Loading Factor = 10

3

18 11>".......--""-_. . L.~...J

RESET 13--------__~
J = Jl . J2 .
K = Kl • K2·
J

TRUTH
TABLE

K 0"

"" ,,
,, ,, ,
,, ,, ,
, ,

Typical Characteristics:
\VCC= 5.0 V; T A = 2SoC)

J3 . J K

in·

Total Power Dissipation = 75 mW/pkg
Toggle Frequency = 40 MHz
Logical "1" Setup Time = 10 ns
Logical "0" Hold Time = 8.0 ns

JK

0,,+1

tpd_ = 20 no

0'

tpd+= 12ns

Q

6k

1.2 k

1.2 k

6k

7

See Genaral Information section for packaging.

.

,a;;u

I

~
J2

ELECTRICAL CHARACTERISTICS

J1

gK

12

@Tes!
Temperature 10L

; ' of-<;
CL.OCK

JK

J
Characteristic

1~

-2.0

+25"C

20

-2.0

+125"(

20

-2.0

ooe

20

-2.0

20

-2.0

20

-2.0

MC3052 { +25"C
+7SQ(

4

-1.5

-1.5

-1.5

12
3

-1.5

-1.5

-1.5

-1.5
-1.5

-1.5
-1.5

-1.5
-1.5

-1.5
-1.5

-1.5
-1.5

-1.5
-1.5

-1.5
-1.5

:~: ~ I::~~~
:~: ~ I:!~~

-1.5

-1.5

-1.5

-1.5

-1.5

-l.SlmAde

-1.5

-1.5

-1.5

-1.5

-1.5

-1.5 I mAde

'.e

-1.5

-1.5

-1.5

-1.5

-1.5

-1.5 I mAde

I FJK

-3.0

-3.0

-3.0

-S.,o

-S.O

-S.O I mAde

I FS

-4.5

-4.5

-4.5

-4.5

-4.5

-4.5 I mAde

IFJ

11

I FJ
IFK

10

'.i\

13

-4.5

-4.5

-4.5

-4.5

-4.5

-4.5 I mAde

r.u

4
12

50
50

50
50

50
50

50
50

50
50

;~ I~1~~

'aK

3

11

50
50

50
50

50
50

50
50

50
50

;~ I~!:~

lRJ

1.0 -10

1.0

-10

2.0

0.4

2.4

4.0

1.8

0.4

2.4

4.0

0.8

1.8

0.4 2.4

4.0

1.1

2.0

0.4

2.5

4.0

1.1

1.8

0.4

2.5

4.0

0.9

1.8

0.4

2.5

4.0

1.1

Vmax Vee VCCL VCCH
7.0

5.0

4.5

5.5

5.0

4.5

5.5

4.5

5.5

5.0
7.0

5.0 4.75

5.75

5.0

4.75

5.75

5.0

4.75 5.75

IOH II;. liD I V" I,V,H IV,I V.

VRH

U1

Vmox IVee IVee, IveCHIP,'

1,12

1,4

14
14

5,7,9,13
5,7,9,13

3

1,11
1,3

14
14

2,7,9,10
2,7,9,10

10

S,4,11,12

13

14

2,5,7,9,10,13

14

7,9,13

14

2,7,9

12

5,9
5,9

14
14

1,2,7,12
1,2,4,7

11

9,10
9,10

14
14

1,7,11,lS
1,3,7,13

14

50

50

50

50

50 I/lAde

50

50

50

50

50 I/lAde

'Re

50

50

50

50

50

50 I/lAde

'RJK

100

100

100

100

100

100 I/lAde

5,9,10

14

IRS

150

150

150

150

150

1501/lAde

1,4,10,12,13

14

3,5,7,11

150

150

150

HiO

150

150 I ).lAde

1,2,S,5,11

14

4,7,10,12

5,9
5,9
9,10
9,10
2,5,9,10,13
1,4,10,12,13
1,2,3,5,11

14

1,2,7,12
1,2,4,7
1,7.11,13
I,S,7,13
S,4,6,7,8,11,12
3,5,7,11
4,7,10,12
7
7
7

IRR

13

I BVin

4
12
3

5.5

5.5

10

Vo

14
14

13

Vd,

4

12

3
11
1

2

2

13
5
9
10

13

5

•

10

,•

-1.5

-1.5

12
3

11

11
5
10
9

5

1
2

13

Output
0.'
0.'

VOL

l:!1 :

VOH

=!g I:fgg

Short-CircuitCurrentt ISC

~~:: Power

IImax

14

3,4,6,7,8,11,12

14

Vd,

12

~SI

~:ll ~~~
Il:!1 : lUI lUI: lUI: Inl I ~~~
I:1~ I:fgg I::g I:~gg I:~g I:~gg I :!g I:~gg I:!g I:i~~ I~~~~
0.4
0.4

42

0.4

0.'

0.4

0.'

0.4
0.4

42

mAdc·

is I

14
14
14
14

is
~s

14
14

-

14

N

nO
::l

:!'.
c:

::l

~

14
14

10
9
1
2
13

Power Requirements
(Total Device)

Gnd

14

1

Output Voltage

3l:

50

10

....U1

n
w
o

4
12

11

3l:
w

n

~N

TEST CURRENTIVOlTAGE APPLIED TO PINS LISTED BElOW,

I 10l

11

Clamp- Voltage

lin

•

50

IRK

BreakdownVoltage

!

IOH

-55°(.20

Pin
Under
Symboll Tes! f:-::-T=-:-'---I-cc:-=r-::"-I-:-:::c,=:-=--Io-::-r:'--I=::r:'---t=+"--1 Unit

IFK

Leakage Current

a~

K

10
13

Input
Forward Current

MC31 52

mA

TEST CURRENTIVOlTAGE VALUES
Volts
ID V1L V1H VF VR
VIH

7,9
7,9
7,9
7.9
2.6,7
7,8,13

1,2,3,4,5,7,9,10,11,12.13

MC3152, MC3052 (continued)

I
OPERATING CHARACTERISTICS

Data should be present prior to the negative clock transition. If data is changed from a "1" to • "0"
while the clock is in the low stata, the flip-flop will not recognize this new data state.
The application of a low level to the SE'f input sets a high and low level on the RESET input resets
a low. These functions may be performed at any time without regard to the clock area.
Positive edge triggering - When the clock goes from the low to the high state, the information
stored in the master flip-flop section is transferred to the sIeve flip-flop section thus appearing at the
outputs. When the clock is in the high steta, the inputs are inhibited.
Unused J, K, and JK inputs should be tied together with used inputs, to the internally connected
output, or to a voltage between 2.0 and 5.5 Vdc. The unused J and R inputs must be tied to ground.
The unused SET and ~ inputs should be tied to a voltage between 2.0 and 5.5 Vdc.

FIGURE 1 -MAXIMUM CLOCK FREQUENCY TEST CIRCUIT

VIHX

= +2.5

Vdc

Vee
Coax
280

950
±1.0%
,JPout

MMD6150

o---+"--iIIII-~ or Equiv.
50
t+

MMD7000

= 7.0 ns

or Equiv.

t-=7.0ns
Maximum Clock
Frequency = 25 MHz min

.. A load is connected to each

output during the test.

CT "" 25 pF = total paraSitic capacitance, Which includes probe. wiring, and load

capacitances.
The coax delavs from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 95Q-ohm resistor

and the scope termination Impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.

WAVEFORMS AND DEFINITIONS

TP out

-

J ,S¥4

~,

i

,

"i!RDhlU4U4tiJ4

MC3152, MC3052 (continued!

•

OPERATING CHARACTERISTICS (continued)
FIGURE 2 -SWITCHING TIME TEST CIRCUIT
(For J inputs and ~ input; to test other inputs, refer to Test Procedures Chart)
VIHX = +2.5 Vdc
Letter designations
refer to waveforms
shown below:

VCC

Coax

Coax

280

950
±1.0%

950 ±1.0%

MMD6150
o-~.....-lo"'~' or Eq~iv.

r

PRF = 1.0 MHz typ

50

t+=7.0ns

= 7.0 ns

t-

F

Three pulse generators are required and

MMD7000
or Equlv.

* A load is connected to each

must be slaved together to provide the

output during the test.

waveforms shown.

The coax delays from input to scope and output to scope must be
matched. The scope must be terminated in 50-ohm impedance.
The 960-ohm resistor and the scope termination impedance constitute a 20:1 attenuatar probe. Coax shall be CT-070-50 or
equivalent.

CT = 25 pF = total parasitic capacitance, which includes probe.
wiring, and load capacitances.

VOLTAGE WAVEFORMS AND DEFINITIONS

A3.0 V
OV

B

1.5 V
CLOCK'

OV

o

U~1:~:~ msts)

3.0 V 1 " 0

TEST PROCEDURES CHART

I

""=rFF"'
oV

INPUT
TEST

I

----1

D3'0V~~n'
OV
I
1.5 V
r--tSetup "ON
-:
tHold "0"
E

3.0 V

:

o V-I'-"";,;..J'I
I

:----500 n'==730 n01.,....._ __

3.0 V

I

OV

G

3.0 V

:

tpd+~

oV

jJ
r
r

H 3.0

V--BI
-.
~

OV tpd_

J

tHold"O"

J

'tsetup"1"

II;

te.",p"1"

J

tHoId"O"

J

ts.tup"1"

1.5 V

30 ns
F

'SetuP"'"

tHold U1"

....

_~1.5V

I
t::::r-.
. tod-

i

~_.5_V_ _

I
I

LJ1.5

~

V

tsd+

::: :::: ::: ::5::~:: :::: ::~:: ~~~.
Ctolayl.omcloc:ktoi5duringtsetup","J_t.
C"I.y I.om clock 10 Q dud", 1!ietup "'" II; _ , .

....

O.lay "011'1 mto

Q

dll.ln'ts..1up "1"

II;

11111:•

C••..,f.omJfElf'ftoli durl "ltslltUp"1"J_·
0eI"YfnlmSeT10QdurlntltsMuP "'" I( ",n.
o.llIYfrom i!II"!Il'I'"toQdu.I"I'SIItUp "'" J_t..

·1..IItbIr.lhown In th_ colllm ... ~.. to *-'orm •.

MC3100/MC3000 series

DOUBLE-EDGE-TRIGGERED
MASTER-SLAVE TYPE D
FLIP-FLOP

MC3153F • MC3053F
MC3153L • MC3053L,P

This double-edge-triggered master-slave type D flip-flop accepts
data on the rising clock edge and transfers it to the output when
the clock input changes back to the logic "0" state_ A 4-wide,
2-2-2-3 input AND-OR gate is internally connec.ted to the D input
of the flip-flop. This makes the device useful in forming shift registers using one package per""bit.

3
4

5
2
10

a

6

Q

8

11

13
12

DAI 3
DA2 4
DA3 5

9-------<1·

OBI 1
DB2 2
DCl 13
DC212

VCC- 14
Gnd? 7

001 10
002 11

Input Loading Factor:
o Inputs == 1
Clock Input == 2
Output Loading Factor

=

10

9C

Total Power Dissipation""' 100 mW typ

LOW LEVEL "AND-OR-INVERT" GATE

LOW-LEVEL "NAND" GATE

Vcc

Vcc
1k

:t: Diodes only on
inputs connected
to external points.

HIGH LEVEL "AND-QR-INVERT" GATE

Vcc

:t:Oiodes connected from each input to GND.

See General Information section for packaging information.

tiWO ;;;;;;;

.,

pq:4

I

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

....W

of the input AND gates. Furthermore only
one input on the AND gate is tflSted. To
complete testing. test other gates and
inputs in the same manner.

c.n

_W

s:
(')

,lIDo
11
13

w
o

c.n
w

@Test
Temperature

6

12
9

C

Ci

8

MC3153

MC3053

Characteristic

mAde
'Oll

10H

{ -55°C
+25°C
+125°C

20.0

-1. 6

-

-

0.4

1.1

2.0

2.4

4.0

5.0

4.5

5.5

20.0

-1. 6

1.0

-10

0.4

1.1

1.8

2.4

4.0

5.0

4.5

5.5 I 7.0

20.0

-1. 6

0.8

1.8

2.4

4.0

5.0

4.5

5.5

{

-

0.4

-1. 6

-

-

20.0

0.4

1.1

2.0

2.5

4.0

5.0

4.75 5.25

20.0

-1. 6

1.0

-10

0.4

1.1

1.8

2.5

4.0

5.0

4.75 5.2517.0

20.0

-1. 6

-

-

0.4

0.9

1.8

2.5

4.0

5.0

4.75 5.25

O°C
+25°C
+75°C

MC3053 Test Limits
Pin
O°C I +25°C I +75°C I
Under
Symbol 1 Test f-::::-'T:";:-tC-T:-:"'-+:-::-=;:::=- Min IMax I Min IMax I Min I Max I Unit

lin

'D

nO

TEST VOLTAGE/CURRENT VALUES
vdc
VIL
V.
V'H VR VRH VCC VCCL VCCH IVmax

:l

""
:;'

c:

~

TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW:
lOll

I 10H I I," I I. I V. I

VIL

I V'H I VR I VRH IVccl VCCL IVCCHIVmaxl ,. IGnd'

Input
Forward Current
Data

IF

Clock

Reverse Current
Data
Clock

Breakdown Voltage
Data

IR

-1. 6
-3.2

-I. 6
-3.2

-1. 6
-3.2

-I. 6

-I. 6

-3.2

-3.2

-I. 6
-3.2

mAde
mAde

14
14

40
80

40
80

40
80

40
80

40
80

40
80

p.Adc
MAde

14
14

2,7*
9

5.5
5.5

Vdc
Vdc

14
14

2,7*

-1.5
-1. 5

Vdc
Vdc

BVin

5.5
5.5

Clock

Clamp Voltage
Data

VD

-1.5
-I. 5

CloCk

7

14
14

Output
Output Voltage

VOL

VOH

Power Requirements
(Total Device)
Maximum Power
Supply Current

2.4
2.4

Imax

14

IpDH

14

s:
(')

0.4

0.4

0.4

0.4

0.4

0.4

Vdc

1,2,3,4,5,
10,12,13

11

14

0.4

0.4

0.4

0.4

0.4

0.4

Vdc

1,2,3,4,5,10,11

12,13

14

3,4,5,10,11,12,13
13,4,5,10,11,12,13

1,2
2

14
14

I-

~:: I -

2.4
2.4

2.5
2.5

2.5
2.5

39
30

I - I

30

1 ;0

*Other input pins groWlded.
**Apply positive pulse prior to taking measurement to set flip-flop in the desired state.

30

1-

Vdc
Vdc

2.5
2.5

I

39
30

30

mAde
mAde

Data Present

--\25

nsfi=lVRH

t----J

L-GND

-

1 -I

1 14

14

7*

MC3153, MC3053 (continued)

I
Oata present at the D inputs 20 ns prior to and 5.0 ns following
the rising edge of the clock pulse is stored in the flip-flop until the
clock falling edge, when it is transferred to the outputs. The data
may change any time except between the setup time (20 ns) and
the hold time (5.0 ns) without affecting the outputs.

OPERATING CHARACTERISTICS

SWITCHING TIME TEST CIRCUIT

2.5 Vdc

r----------,

Vee

I

I

Coax

Coal(

I

280

r-----,I

950
1.1.0%

I

950±. 1.0%

MMD6150
or Equiv

W. Xo--..-+-'-I
MMD7000
or Equiv

U.Vo-~;-~------~e

Two pulse generators are required and must be slaved

together to provide the waveforms shown.
• A load is connected to oach

The pulse generator driving the clock must be operated

output during the test.

in the double pulse mode.
~etter

designations refer to waveforms shown below:

WAVEFORM

SYMBOL
U

V

W,X

1.0MHz

0.5 MHz

PW

20MHz
50% Duty Cycle

t+. t-

7.0 ns

30 ns
7.0 ns

1.0 ns

f

-

CT ;:: 25 pF ::: total paraSitic capacitance, which includes probe,
wiring, and load capacitances.

The coax -delays from input to scope and output to scope must be matched. The
scope must be terminated in _50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20:1 attenuator probe. Coax shall be
CT-070-50 or equivalent.

VOLTAGE WAVEFORMS AND DEFINITIONS
30ns

U,V

3.0

v---v---.i

OV

W

3.0

v-f,...-!.......
TEST PROCEDURES CHART

OV
5.0
X

n.~

-t~Old "1"

INPUT

I

3.0 V

OV \

TEST
Turn·On Delay

_~20ns --tJtup "0"

5.0 nsy

l

0.4 V
~

C

tpd-

V
V

Q

Turn·Qff Delay

-tHold "0"

2.4 V

Q

SYMBOL

Q

tpd+

Q

f

Toggle Frequency
Gnd

!-tpd_

a

fTog

Q

V
V
U
U

D
W

Q

Q

LIMIT

Z

y

X

Y

Z

35 ns
max.

X

Y

Z

W

Z

Y

. ..- ..
-

35 ns
max.
20MHz

min.

·0 I nput connected to Q output.

z

2.4 V

1

0.4 V
~

!-tpd+

* ·Output must change state wi1'h each input pulse.

\
Gnd

• JitQ£:::t....

Of·""

MC3153, MC3053 (continued)

•
APPLICATIONS INFORMATION

LOGIC DESCRIPTION
This flip-flop performs the 0 function, with input logic defined
by the following equation:

6= 1.2+ 3.4.5+ 10.11 + 12.13
The operation of the flip-flop is as follows (refer to Figure 1).
AssumeQis "0". To set a "1" on theQ output, "1" must be applied
to all the inputs on either gate A, B, C, or D. When the clock goes
high, a "0" appears on the output of gate G and a "1" appears on
th.e output of gate H. However, because the other input to gate J
comes from gate F, the output of J remains "0", and because of the
input from gate G to gate I, the .output of gate I remains "0". When
the clock goes low, the outputs of gates E and F go to "1". Thus
gate J now has a "1" applied to both inputs and its output goes to
"1". Since gate L now has a "1" applied to it. its output goes to
"0", and this is coupled to gate K, which now has zero applied to
both inputs causing it to go to a "1". The flip-flop has now switched and Q is a "1". Setting a "0" on the output may be followed
through in a similar fashion.

SYSTEM SKEW
Clock skew in a system is one of the most difficult problems that
the system designer must solve. Consider the clock driver circuitry

shown in Figure 2. Clock skew between C1 and C2 could be caused
by a number of factors, including unequalloeding, unequal wiring
distances, and different turn-on and turn-off times between clock
line driver getesthat may be in the circuit between C1 and C2. Most
flip-flops that are presentlv available in integrated form do not allow
the system deSigner to control the amount of skew in the system.

With the MC3153/3053, system clock skew can be adjusted.
Three basic types of flip-flops are now in use: (1) the chargecontrolled flip-flop, (2) the edge-triggered flip-flop, and (3) the
master-slave flip-flop. Figure 2 is an example of a system in which
the clock skew problem is encountered. The direct..,oupled shift

register can be made with the two most common types of flip.
flops - the negative-edge-triggered flip-flop or the master-slave flipflop.
When negative-edge-triggered flip-flops are used to implement
the shift register of Figure 2, the maximum allowable clock skew,
Figure 3A, is the propagation delay from the falling edge of the
clock to the output of flip-flop A minus the hold time of flip-flop
B. It should be noted that the maximum propagation delay time
and the minimum hold time from data sheets may not be used to
calculate maximum allowable clock skew. Instead, the minimum
propagation delay and maximum hold times must be used to calcu-

late maximum clock skew to insure proper system operation over

the entire temperature and power supplV variations expected.
If the shift register of Figure 2 is constructed with master-slave
flip-flops, the maximum allowable clock skew, Figure 3B, is the propsgation delay from the falling edge of the clock to the output of
flip-flop A plus the time required to transfer and latch the inform ..
tion into the master portion of flip-flop B. The minimum propaga.
tion delay and latch times must be used in calculating the maximum
clock skew to guarantee proper system operation.
BV using MC3153/3053 double-edge-triggered master-slave type
o flip-flops in the circuit of Figure 2, the maximum clock skew,
Figure 3C, is the propagation delay from the falling edge of the
clock to the outout of flip-flop A minus the hold time of flip-flop
B plus the clock pulse width. In this case, minimum propagation
delay and maximum hold time must be used in the skewcalcuJations.
However, since the clock pulse width is part of the clock skew calculation, system clock skew can b-

2.8 k

2,8

2.8 k

k

" y I - T W r o 1 JIA
•
- 0 2 JIB
~
7 GND
~

K2A

'----------- 3
L----------f'::I:t±-<> 4

110--+1-.--------~

120--±~~~--------J

K2B

'lI'c~.~l
~~~
'-

nCLOCK
r
13

t

See General I nformation section for packaging.

,.:m;;;;.,

, ,4 . t

u,.

J2A
J28

MC3154, MC3054 (continued)

•
OPERATING CHARACTERISTICS

Data must be applied to the J-K inputs while the clock
is low. When the clock input goes to the positive logic
"'" state, the data at the J and K inputs is transferred to
the master section, where it is stored until the clock changes to the positive logic "0" state. Data at the J and K
inputs must not be changed while the clock is high. When
the clock returns to the positive logic "0" state, information in the master section is transferred to the slave
section.

Application of a logic "0" to the SET J!lQ.ut will force
the Q output to the logic "'" state. The SET input overrides the clock.
Since no charge storage is involved in this flip-flop,
rise and fall times are not important to its operation.
Clock fall times as long as '.0 Ils will not adversely affect
the operation of the flip-flop. The clock pulse need only
be wide enough to allow the data to settle in the master
section. This time, which is the setup time for a logic "''',
is '2 ns minimum.

SWITCHING TIME TEST CIRCUIT

VCC
+5.0Vdc

280

TP out
MMD6150
or Equiv.

PULSE
GENERATOR
50

CLOCK = t- = t+ = 3.0 ns (10% to 90%)
SET = t-= t+ = 7.0 ns (10% to 90%)
f = 10 MHz for waveform A
1.0 MHz for waveforms B, E, and F

""I

Two pulse generators are required and must be slaved together for testing SET.
Only one pulse generator is required for J, K, and CLOCK tests .
• A load is connected to each output during the test.
CT = 25 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
The coax delays from input to scope and output to scope- must be matched.
The scope must be terminated in 50-ohm impedance. The 9SO-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuatOr probe. Coax
shall be CT -070-50 or equivalent.

MMD7000
or Equiv.

=

3:

ELECTRICAL CHARACTERISTICS

(1

....en
to)

Test procedures are shown for only one

J and one K input on each AND gate, plus

,~

the SET and CLOCK inputs. To complete
testing, sequence through remaining J and
K inputs in the same manner.

SET
J1A
J1B
J2A
J2B

s:
(1
~

i~··.·

en

~

CLOCK 13

Q

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
Volts

8

rnA

Cnaraderistic

no
:J
....

06

Pin MC31S4 Test Limits
SS to +12S'C
Under
Symbol Test Min Max Unit

MC3JS4
MC30S4
MC30S4 Test Limits
o to +7S'C
Min Max Unit

::i'

101

10H

lin

VF

Vo

VOH

VIH

V"

20

-1.5

1.0

0.4

2.4

4.5

2.0

0.8

4.5

5.5

20

-1. 5

1.0

0.4

2.4

4.5

2.0

0.8

4.75

5.25

c
~

Vee1 VeeH

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:
101

10H

lin

VF

Vo

VOH

VIH

V"

Vee, VCCH

P ••
A

Gnd

Input
Forward Current "JIA'
KIA

1
11
5
13
13

-2.0
-2.0
-6.0
-4.0
-4.0

mAde

IRI

1
11
5
13
13

50
50
150
100
100

/JAde

BV.
m

1
11

5.5*

5

t

IF

set
CiOCk
Clock

JIA
KIA

Leakage Current

Set
Ci'Ock
Clock

JIA
KIA

Set

ClOCK

Ia
13

CiOc'K

-2.0
-2.0

~

~6.0

-4.0
-4.0
50
50
150
100
100

t
Vde

5.5*

J

1

mAde

1
11
5
13
13

t
t

1

14

7,6
7
7
7
7,6

t

1,2,3,4,5,9,10,11,12

14

1
11
5
13
13

MAde

Vde

2,13

5**,12,13
1,2,3,4,9,10,11,12,13
1,2,3,4,5**,9,10,11,12

2,5,7,13
5,6,7,12,13
6,7,9,10,11,12,13
1,2,3,4,5,7,9,10,11,12
1,2,3,4,5,6,7,9,10,11,12

t

1
11
5
13
13

14

2,5,7,13
5,6,7,12,13
6,7.9.10.11.12.13
1,2,3,4,5,7,9,10,11,12
1,2,3,4,5,6,7,9,10,11,12

1

Output
Output Voltage

0.4
0.4

VOL

Short-Circuit Current

Y OH

6
8

2.4
2.4

ISC

&

-40
-40

0.4
0.4

Vde
Vde

Vde
Vde

9,10,11,12

5
1,2,3,4

14
14

5

14

1,2,3,4

14

13

7,13
7
7,13
7

Yde
Yde

2.4
2.4

-100

mAde

-40

-100

mAde

1,2,3,4,9,10,11,12,13

14

5,6,7

-100

mAde

-40

-100

mAde

1,2,3,4,5,9,10,11,12,13

14

6.7.81

30
30

mAde
mAde

30
30

mAde
mAde

1,2,3 ,4,5,9 ,10,11,12

14
14

1,2,3,4,5,7,9,10.11,12.13
7.1311

Yde
Vdc

9,10,11,12

13

Power Requirements
Power Supply Drain
-

_.-

-.

_._--

IPD

14
14

*Tested at 25°C only.
**MomentarUy ground pin prior to taking measurement, then apply 4. 5 volts.
t Limit duration of test to 100 ns.
t t Momentary 4. 5 V then apply gnd.

PA=JL405/

•

MC3154, MC3054 (continued)

•

TEST PROCEDURES

(Letters shown in test columns refer to waveforms.)
INPUT
SYMBOL

TEST

LIMITS

Q

Q

I:!

J, K

S

fTog

A

2.4 V

2.4 V

t

t

Turn-On Delay

tpd_

B

B

2.4 V

C

C

Turn~Off Delay

tpd+

B

B

2.4 V

0

0

Turn-On Delay

tsd-

E

2.4 V

F

G

H

Turn-Off Delay

tsd+

E

2.4 V

F

G

H

-

1'oggle Frequency

Min

Max

Unit

25

-

MHz

-

27

ns

-

21

ns

24

ns

13

ns

t Output shall toggle with each Input pulse.

VOLTAGE WAVEFORMS AND DEFINITIONS

,----""---------3.0 V

GNO-..L--'------+->...---...;....---O.O V

- - - - - - - - - + - - - , - - - - - - 2 . 4 V min
C

TP out

1.5 V
GNO _ _ _ _ _ _ _ _ _t=--="~-=.!....:===:::O.4 V max

_ _ _ _ 2.4 V min

o

TP out

==================0.4

=

GNO

V max

3.0V
E

TPin

C05CK

GNO

0.0 V

3.0 V
F

TPin

SET

O.OV

GNO

2.4'V min
G

TP out
0.4 V max
GNO

H

TP out

J

GNO

2.4 V min
1.5 V
0.4 V

max

•

MC3100/MC3000 series

"AND" INPUT
J·K FLlP·FLOP

MC3155F • MC3055F
MC3155L • MC3055L,P
(S4H72J)

SEi'

(74H72J,N)

13 - - - - - - ,

Jl
J2
J3

3
4
5

8

CLOCK 12
Kl 9
K2 10
K311
RESET 2 - - - - - . . I

tn

This negative-edge-clocked J-K flip-flop operates on the master-slave
principle. Three K inputs are ANDed together, and three J inputs are
ANDed together. SE'F and RESET inputs are also available. The device
helps minimize package count in J-K flip-flop applications requiring
AND gating into the J or K inputs.

tn+1

J

K

a

0
0
1
1

0
1
0
1

an
0
1

an

J

= Jl

K

=

6

• J2 • J3

Kl • K2 - K3

Input Loading Factor:
J. K, CLOCK = 1
SET, RESET = 2

9

3 Jl

K210

4 J2

K3'11

5 J3

Kl

Output Loading Factor"" 1 0

Total Power Dissipation = 80 mW typ/pkg
Propagation Delay Time = 10 ns typ
Operating Frequency = 30 MHz typ

Pin numbers for the 54H72F/74H72F device are

DEVICE

shown in the chart. These devices are available on
special request.

MC3155F,Ll3055F,L,P
54H72F174H72F

6

2
5

3

5
9

4

8

6

CIRCUIT SCHEMATIC
.------~--~~------1~--~-~---_.----_o14

VCC

58

760

2.8 k

2.8 k

58

760

a

H--06

80--"",,,

470

13O---~--_'----------~

SET

~----~~----,-~----o2

r---1~--~r-~~------~t-~---~~-+-.,
2.8 k

2.8 k

~
2_8
k

2.8 k

KI90----...

; - - - - 0 3 Jl

K210o---...J
K3 11 0-------1

'-----04 J2
'------05 J3

..

L---t--------------1~-~

te~-t_----07 Gnd

CLOCK
12

See General I nformation section for packaging.

$i.li!Q4AU

¥#4A

"¥if

'WM.

MC3155, MC3055 (continued

•
OPERATING· CHARACTERISTICS

Data must be applied to the J·K inputs while the clock
is low. When the clock input goes to the positive logic "1"
state, the data at the J and K inputs is transferred to the
master section, where it is stored until the clock ·changes
to the positive logic "0" state. Data at the J and K inputs
must not be changed while the clock is high. When the
clock returns to the positive logic "0" state, infor·
mation in the master section is transferred to the slave
section.
Application of a logic "O"to the SET input will force the

Q output to the logic "1" state, and application of a logic
"0" to the RESET input will force the a output to the logic
"1" state. The SET and RESET inputs override the clock.
Since no charge storage is involved in this flip·flop,
rise and fall times are not important to its operation.
Clock fall times as long as 1.0 Ils will not adversely affect
the operation of the fl ip· flop. The clock pu lse need only
be wide enough to allow the data to settle in the master
section. This time, which is the setup time for a logic" 1",
is 12 ns minimum.

SWITCHING TIME TEST CIRCUIT

Vee
+5.0Vdc
Coax

280

TPin

MMD6150
or E,quiv

P\JLSE
GENERATOR

-=
t- = t+ ';;7.0 ns (lO% to 90%)
f

= 25 MHz for waveform A
1.0 MHz for waveforms

e, E,-and

MMD7000
or Equfv

~I

F

-=
Two

Pelse generators are required and

and R SET.

must be slaved together for testing

ru

Only one pulse generator is required for J, K, and CLOCK tests.

-A load is connected to each output during the t85:1:.

CT

= 25 pF = total parasitic capaci'lance. which includes ~rObe, wiring, and load

capacitances.
The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm reSistor
and the scope termination impedance (:onstitute a 20: 1 attenuatar probe. Coax
shall be CT -070-50 or equivalent.

s(')
....W

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one J
and one K input, plus the SET, RESET,
and CLOCK inputs: To complete testing,
sequence through remaining J and K inputs
in the same manner.

Jl

.ID
.
Q

8

0:

6

Input
J
K

IF

set
Reset
Clock

J
K

~1

Set
Reset
Clock
J
K

BVin

Set
Reset
Clock

3
9
13
2
12
·12

3
9
13
2
12
3
9
13
2
12

Output
Output Voltage

Short-Circuit Current

--

-

5.5"

-2.0
-2.0
-4.0
-4.0
-2.0
-2.0

mAde

50
50
100
100
50

/LAde

-

Vde

I
1

-

-

5.5**

-2.0 mAde
-2.0
-4.0
-4.0
-2.0
-2.0

I

50
50
100
100
50

/LAde

-

Vde

1

! !!- !
-

-

-

VOL

6
8

-

0.4
0.4

Vde
Vde

-

VOH

6
8

2.4
2.4

-

Vde
Vde

2.4
2,4

ISC

6
8

-40
-40

-100
-100

mAde
mAde

-40
-40

IPD

14
14

25
25

mAde
mAde

-

Power Requirements
Power Supply Drain

IOL

MC3155 20
MC3055 20
Pin MC3155 Test Limits MC3055 Test Limits
oto +75°C
S5 t~ +125?C
Under
Symbol Test Min Max Unit Min Max Unit IOL

Characteristic

Leakage Current

S
n
w
o

3

SEi"13

Forward Current

(J1
~(J1

-

--

Vde
Vde

-

mAde
mAde

1.0

0.4

2.4

4.0

2.0

0.8

4.5

5.5

-2.0

1.0

0.4

2.4

4.0

2.0

0.8

4.75

5.25

IOH

lin

-

-

-

-

-

--

-

-

-

VF
3
9
13
2
12
12

-

-

3
9
13
2
12

-

6

-

--

-

8

-

-

nO
::J
~.
::J

c:

~

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

-

-

-2.0

-

6
8

25
25

lin

--

Vde
Vde

-100 mAde
-100 mAde

rnA
IOH

---

0.4
0.4

U1
U1

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
Volts
VR
VRH
VF
¥IH VIL VCCL VCCH

-

-

-

-

-

3
9
13

:I
12

-

-

-

--

-

-

...

VR

--

-

----

VRH

VIH

V1L

2~ 4,5, 12
10,11,12,13'
3,4,5,9,10,11
3,4,5,9,10,11
2~ 3, 4, 5~ 9,10,11
3,4,5,9,10,11, 13*

-

-

-

-

-

-

-

-

-

-

-

-

VCCL VCCH
-

14

7

I

j

-

14

-

1

-

-

-

14

2
13

13
2

14
14

13
2

2
13

14
14

-

-

-

-

-

-

-

-

-

-

-

- __

Gnd

!

2,4,5,7,12
7,10,11,12,13
7,9,10,11,12
3,4,5,7,12
2,3,4,5,7,9,10,11,13
2,4,5,7,12
7,10,11,12,13
7,9,10,11,12
3,4,5,7,12
2,3,4,5,7,9,10,11,13

7
7

-

7
7

14
14

2,6,7,12
7,8,12,13

14

2,3,4,5,7,9,10,11,12
3,4,5,'1,9,10,11,12,13
- - - - - - - -- -_. - - - -

14._

*Momentarily ground pin prior to taking measurement.
"Tested @ 25°C only.

•

MC3155, MC3055 (continued)

•

TEST PROCEDURES
(Letters shown in test columns refer to waveforms.)

TEST

SYMBOL

INPUT

c

J, K
A

2.4

V

2.4

Toggle Frequency

fTog

A

fj

a

a

V

t

S

LIMITS
Min

Max

Unit

t

26

-

MHz

Turn-On Delav

tpd-

B

B

2.4

V

2.4

V

C

0

-

27

ns

Turn-Off De.lay

tpd:t-

B

B

2.4

V

2.4

V

C

0

21

ns

Turn-On Delay

tsd-

2.4

24

ns

Turn-Off Delay

tsd+

Enable Voltage

'*

I nhjbit Voltage-(:(

V

E

F

G

H

-

2.4 V

2.4 V

E

F

G

H

10

13

ns

VEN

B

2.0 V

2.4 V

2.4 V

t

t

t

VINH

B

0.8 V

2.4

*

*

*

-

-

V

2.4

V

2.4

V

t Output shall toggle with each input pulse.
:t:Output shall NOT,toggle.

* Tested at all temperatures.

VOLTAGE WAVEFORMS AND DEFINITIONS

J.:----"'li::=b.:c=-----3.0 V
A

TPin

CLOCK
Gnd -~~---------+~~~----,OV
~+-"""",----3.0 V
B

Data

1.5 V

Input

Gnd ----~--+---~~--OV

- - - - - - - - - t - - , - - - - - - 2 . 4 V inin

C TP out
tpd_

Gnd
tpd+~,2.4 V min

0

r'·5V

TP out
Gnd

::::::::::::::::::::============'0.4 Vmax
~-----------3.0

E

V

TPin

i'iESEf
Gnd ---~----~Lf------------OV

F

3.0V
TPin

SET
Gnd

---+~====~~======~~----L+---OV
, - - - - - - - - 2 . 4 V min

G

TP out
Gnd --+----'':::::::::::::::::::::::::::::::=I=~---------O.4 V max

tSd+r

I
-'/.5
V

HTP

~----------"\.-+--------2.4

out
Gnd

V min

0.4 V max

MC3100/MC3000 series
DUAL TYPE D FLIP-FLOP

MC3160F • MC3060F
MC3160L • MC3060L,P

This dual flip-flop triggers on the positive edge of
the clock and performs the Type D flip-flop logic
function. This device consists of two completely independent Type D flip-flops, both heving direct SET and
RESET inputs for asynchronous operations such as
porallel data entry in shift register applications.
Information may be applied to, or changed at, the
D inputs any time during the clock cycle except during
the time interval between the Setup and Hold times.
The clocked inputs are inhibited when the clock is
high and data may be applied to the input steering
section of the flip-flop when the clock goes low. The

1/2 OF DEVICE SHOWN
14

input steering section continually reflects the input

state being applied when the clock is low. The information present at the inputs during the time interval

between the Setup and Hold times is transferred to
the bistable section on the positive edge of the clock,
and the outputs Q and Q respond accordingly.
The flip-flop can also be set or reset directly at any
time, regardless of the state of the clock, by applying
a low state to the direct SET or RESET inputs.

SET4~
o
2

O.

5

CLOCK

3

Q

6

i'fE"SE'f

1

SET10~
o 12
a
9
Q

CLOCK 11 .

8

RESET 13

TRUTH TABLE
0

on

On+1

0
0
1
1

0

0
0
1
1

1

0
1

on+1;;; On

Input Loading Factors:

LOGIC DIAGRAM
RESETo-~--------~r----------'

1/2 OF DEVICE SHOWN

SET-l.15
RESET - 1.7
CLOCK- 1.5

0-0.75
Output Loading Factor;;; 10
O~--,--,

Typical Characteristics: (VCC=5.0 V, TA:=l:2S0C)

CLOCKo-----------~~

Total Power Dissipation = 120 mW/pkg
Toggle Frequency = 30 MHz
Logical "1" Setup Time = 10 ns

Logical "0" Setup Time;;; 5.0 ns

a

Logical "1" and "0" Hold Times
tpd_ = 17 ns
tpd+ = 15 ns

SETo-~------------------~
sea General Information section for packaging

=

5.0 ns

•

•

ELECTRICAL CHARACTERISTICS
flip-flop_

The other flip-flop is tested in

4~
a
5

SET
D

2

CLOCK

3

RESET

1

the same manner.

0:

~~

6

Test
Temperature

0:

8

RESET 13

MC3060

10H

20

-2.0

20

-2.0

20

O°C
+25°C
+75°C

Pin
Under f--,-,"":;'::"':"+""':;r:-,.:,-+~'T=-~J-,-,."="':=-O--+""':;::"":-+-""':'-r,..:~
Symbol Test
Unit

Characteristic
Input

Forward Current

Leakage Current

Breakdown Voltage

i FC

-3.0

-3,0

-3.0

-3.0

-3.0

-3.0 I mAde

IFD

-1. 5

-1. 5

-1. 5

-1. 5

-1. 5

-1. 5 I mAde

~s

-2.3

-2.3

-2.3

-2.3

-2.3

-2.3 I mAde

~R

-3.4

-3.4

-3.4

-3.4

-3.4

-3,4 I mAde

1 + t -......---o4~

J

30----+--4

See General Information section for packaging.

t----I----o2 K

3:

ELECTRICAL CHARACTERISTICS

(')

Test procedures are shown for only one
flip·flop. The other flip-flop is tested in
the same manner.

SET

.~

W

~

Q')
5

Test
Temperature

9

MC3162

t

IOL
20

-2.0

1.0

-10

0.4

2.4

4.0

7.0

4.5

5.5

t

20

-2.0

-

0.4

2.4

4.0

-

4.5

5.5

8

MC3062

Characteristic
Input
Forward Current

Leakage Current

Breakdown Voltage

Clamp Voltage

MC3162 Test Limits
MC3062 Test Limits
Pin
+25°C
+12SoC
O°C
+25°C
+75°C
Under -55°C
Symbol Test Min Max Min Max Min Max Min Max Min Max Min Max
-

-4.7

-

-4.7

-4.5
-4.5

-

-

-4.5
-4.5

50
50

-

50
50

150

-

-

150

-

150

150

-

150

-

150

-

5.5

-

~

-

-

-

~S

4

-

-4.7

~C

1
1

-

-4.5
-4.5

IR

2
3

IRS

4

-

IRe

1

-

BVin

2
3
4
1

-

-

2
3
4
1

-

-

-

-

-

VD

50
50

-

-

-

Output
Output Voltage

-1. 5
-1. 5

2
3

-

-

2.4
2.5

-

ISC

5

-20

-65

Maximum Power
~l'ply Current

Imax

14

-

-

Power Supply Drain

lPD

Short-Circuit Current

Power Requirements
(Total Device)

--

-

14
-

-

-

31
_.

-

-1. 5

-

-

0.4

2.5

4.0

-

4.75

5.25

1.0

-10

0.4

2.5

4.0

7.0

4.75

5.25

~.

20

-2.0

-

-

0.4

2.5

4.0

-

4.75

5.25

c:

Unit

IOL

IOH

mAde

mAde

-

-

mAde

-

-

mAde
mAde

-

50
50

--

50
50

/lAde
~Adc

-

-

150

-

150

~Adc

-

150

-

150

~Adc

-

-

-

-

-

Vdc

~

-

-

-1. 5

-

-

~

-

Vdc

-

-

-

-

-4.7

-

-4.5
-4.5

50
50

-

-

150

-

150

-

5.5

-

-- --- -

-

-

-

-

-

-

-

-

-

~

-

VR VRH

lin

ID

VF

-

-

2,6
3,5

-

-

4,6

-

1,2

1,6
1,5

-

2,3
2,3,4

-

1.4
1,4

Vmax
-

-

-

3,7,13

14
14

4

7,13
7,13

-

-

-

-

-

2
3

3
2

-

-

14
14

-

-

-

-

-

4

3

-

-

14

-

-

-

-

-

1

-

-

-

14

-

-

-

-

-

--

-

-

14

-

2
3
4
1

-

-

-

-

14

-

-

~

-

-

2
3
4
1

-

-

-

-

-

-

14
14

-

-

i

--

-

-

-

-

-

-

-

-

---

-

-

-

-

-

0.4
0.4

-

0.4
0.4

-

0.4
0.4

-

0.4
0.4

Vdc
Vdc

5
6

-

4

2.4
2.5

-

2.4
2.5

-

2.5
2.5

-

2.5
2.5

-

2.5
2.5

-

Vdc
Vdc

-

- -

5
6

-

-

4

-

-

4

-

14

-20 -65

-20

-65

-20

-65

-20

-65

mAde

-

-

-

-

-

-

-

-

-

-20 -65

14

-

-- --

-

-

3,7,13
2,7,13

---

-

-

-

-

-

-

--

-

-

-

14

Gnd

--

14
14

0.4
0.4

-

c..

-

-

-

:J

VCCL VCCH PI •

-

-

:J

CD

-

-

0o

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED' BELOW:

-4.7

-4.7
-4.5
-4.5

-

-2.0

-4.5
-4.5

-

-

N

-2.0

-

-1. 5
-1. 5

W

20

-1. 5
-1. 5

-

(')

oQ')

20

-

-

-1. 5
-1. 5

-

O°C
+2n
+75°C

3:

-

-

0.4
0.4

5
6

-

-1. 5
-1. 5

-55°C
+2n
+125°C

~

-

-

V OH

-

-

5
6

VOL

--

-

-1. 5
-1. 5

IF

20

TEST CURRENT /VOLTAGE VALUES
mA
Volts
IOH I.In ID VF VR VRH Vmax VCCL VCCH
-2.0
4.5
- 0.4 2.4 4.0
5.5

@

6

,N

i
-

-

-

1,4,7,13
1,4,7,13

-

2,3,4,7,13

--

7,13

-

5
4

1,2,7,13

1,4,7,13
1,4,7,13
1,2,7,13
2,3,4,7,13

~
1,7,13
1,7,13

4
5

7
1,7,13

14

-

4,5,7,13

-

41

-

-

-

-

-

41

-

-

mAde

-

-

-

-

-

-

-

14

-

-

-

4,7,10

-

31

-

31

-

31

-

31

-

31

mAde

-

-

-

-

-

-

-

-

-

14

-

4,7,10

-

* Momentarily ground pin prior to taking measurement.

(If pin is also in another column the pin must be returned to that voltage or current for measurement. )

•

MC3162, MC3062 (continued)

•
OPERATING,CHARACTERISTICS

The data must be present 12 ns prior to the fall of the clock and remain Until 0 n. after the clock fall •.
The flip-flop is set to the a = 1 state'by applying a low level to the
SET input. The direct SEi' inputs may be used at any time without
regard to the clock state. If these inputs are not used they should be
returned to a voltage between 2.0 and 5.5 Vdc.

Negative edge triggering - The input state during the time interval
between the Setup and Hold times is stored in the flip-flop when
the clock goes low:
Unused clocked inputs should be tied to the clock, to the internally
connected output, or to a voltaga between 2.0 and 5.5 Vdc.

MAXIMUM CLOCK FREQUENCY TEST CIRCUIT

VIHX
+2.5 V

PULSE
GENERATOR

MMD6150
or Equiv
K

t+ = 7.0 os

50
MMD7000
or Equiv

t- == 7.005
Maximum Clock
Frequency == 40 MHz min

.. A load is connected to each
output during the test.

CT = 25 pF == total parasitic capacitance. which includes probe, wiring, and load
capacitances.

The coax delays from input to st:ope and output to scope must be matched.
The scope must be terminated in 50·ohm impedance.

The 950-ohm resistor

and the scope termination impedance constitute a 20: 1 attenuator probe. Coax
shall be CT -070-50 or equivalent.

VOLTAGE WAVEFORMS ANO OEFINITIONS

3 0 V -.--------,
t.5 V
I
1-12

OV~

TP out

r----'"'I

ns-l

L......--.J

. I

.--------,

ro-

I

I

L-.-.-.J

I

L--....J

MC3162, MC3062 (continued)

•

OPERATING CHARACTERISTICS (continued)

SWITCHING TIME TEST CIRCUIT
(For J Inputs; to test other inputs, refer to Test Procedures Chan)

Vee
Letter designations
refer to waveforms
shown below:

Coax

Coax

280

+2.4'V

950
± 1.0%

950±.1.0%
B,C,D,E

"JP

out

o-....'--loIII--+
TPin

MM06150
or Equlv

2.4 V

PRF::: 1.0 MHz typ
PW = 50% Duty Cycle

50

MM07000

H 0'
;;'2.4 V

t+=7.0ns
t- = 7.0 ns

or Equiv

• A load is connected to each
output during the teSt.

Three pulse generators are required and
must be slaved together to provide the
waveforms sh own.

CT '"" 25 pF - total parasitic capacitance, which include. probe. wiring, and load
capacitances.
The coax delavs from input to scQpe and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor

and the scope termination impedance constitute a 20: 1 attenuatar probe. Coax
shall be CT -070-50 or aquiv8.lant.

VOLTAGE WAVEFORMS AND DEFINITIONS

A

TEST PROCEDURES CHART

3,OV

INPUT

B 3,0 V--\,....-"';'"\I

TEST

J'

sp·

K'

LIMITS (ns)
Q'

o·

SO.4V

:l!:2.4V

$"0.4 V

~2.4V

I

OV

Mo.

,
t$atlJp "1" J

""317'"
oV

:

i

1.5 V

E 3.0 V

o

I

~tuP"l"l<

1.5 V

t--tsetup "0"
tHold "0"

tHold "1" K

I

tsetup -'0" K

Gnd

~:2.4 V

$"0.4 V

tHoLd "0" K

j3nd

~2.4V

$0.4 V

30 ns

:---500 ns~o

F 3.0V

,

OV

o

GoO

0"

---:

V-l'-.....,:. . .I

G 3.0 V

0"

:tHold"1"

D3.ov~~n
oV

2.4\1

tHold"1"J

I

tPd+B'

V-----"I"-....

v---+

f\
:j:=r
I """""'

H 3.0
OV

tpd-

n'I _____

_"-.J1.5 V

1Ft

D.ley from

Ci:OCK to Q

oeley from

CLOCK to Qdurlnlltsetup "'" K
:t
U

I

w u
u 5.0 fo----

C!l

«>

----

I.J "0
0. .-

>~

..

I- _4.75

::>

IF21

~

1:

:;

>..J

5.0

r-

1---

DD-

:J

lal UNUSED INPUTS
GROUNDED

Rl

C/l

a:

4.75

~

U

•

i

0

D-

U

>

4.5
10

I~

I

w

0.8 V

/

12

14

16 16.8

18

20

IOL' OUTPUT SINKING CURRENT (rnA)

all unused inputs (common to the unit segment under test) are returned toa referencevoltege, VRH = 4.0 V. Since all the characteristics except the maximum loading current, lOLl are held constant

VCCH

Ib) UNUSED INPUTS
OPEN

Rl

for both test points, these tests not only guarantee the dc noise
immunity but they also define the maximum drive capability of
the output as a function of power supply voltage, as shown in
Figure 5. Using this information, it is possible to relata tha output
drive capability of an MC4000 series function to any of the various
MTTL or MOTL specification formats. The input threshold voltages and the output low-state voltage specified on the MC4000
series data sheet must still be used. For example, the MTTL I
MC500/400 series specifies the output low-stete voltege for VCC =
+5_0 V. Relating a typical MC4000 series function, the MC4008,
to this format, tha following guaranteed limits resultat T A = +7So C:
VOL = 0.4 V at IOL

~

16.8 mA

with Vth "0" = 0.9 V, and all other inputs returned to
Vth "1"= 1.8V.
With this information, it is possible to define the VOL at IOL
characteristics of the MC4000 series to any of the various MOTL
or MTTL specification formats. The input thresholds and the VOL
for the MC4000 series must be used as specified on the MC4000
series data sheat.

Output High-State Voltage
The output high-stete voltage, VOH(volts), specification defines the guaranteed minimum output high~state voltage at maximum high-state loeding current. This voltege is defined to guar-

Input Clamp Diode Voltage
Each of the signal inputs to the MC4000 series functions has a
clamp diode to limit negative ringing that can occur on signal lines.

The input clamp diode voltage tast, VD, at the input diode current,
ID, guarantees the maximum impedance of the clamp diode.

Output Low-8tate Voltage
The output low-state voltage, VOL(volts), in conjunction with
the minimum input threshold voltege, Vth "0", definas the minimum low-state de noise !nargin and the maximum drive capability
of the output for that guaranteed noise margin. The output lowstete voltage is specified ·at both power supply extremes under
maximum output loading conditions with the worst-case input
threshold voltage appiied to a single input of the unit under test;

antee a worst-case, high-state noise immunity. The maximum highstate drive current, lOLl defines the high-state driving characteristics of the device.
The output high-state voltege for the MC4000 .eries is specified
with the worst-case threshold voltage on the input, the minimum
power supply voltege, VCCL, and the maximum high-state output
current as a loed on the output. The unused inputs are returned to
an input reference voltege, VRH. This limit, as specified, is compatible with the other families of MTTL and MOTL and can be
used independant of power supply variations for the threshold
voltages specified on the various MC4000 series data sheets.
The output short circuit current, Isc(mA), the maximum power
supply current, ImaxlmA), and the power supply drain, IpolmA)
can be used directly with the various MTTL and MOTL specification formats.

MTTL

GENERAL INFORMATION
MTlL MC4300/4000 Series
Complex Fundions

I

DEFINITIONS

BVin
CT
IB
ICEX
10

IF
lin
IL
Imax
IOH
IOL
IpO
IpOH

Input breakdown voltage
Total parasitic capacitance, which includes
probe, wiring, and load capacitances
Base current
Logic "1" output leakage current
Input diode current
Input forward current
Input current
Inverse beta current
Maximum rated power supply current with
Vmax applied
Output logic "I" state source current
Output logic "0" state sink current
Power supply current drain
Power supply current drain with inputs in logic
"I" state

IPOL

Power supply current drain with inputs in logic
"0" state

IpO max

Maximum power supply current
Minimum power supply current
Input reverse current
Logic "I" state source current with output
shorted to ground
Pulse repetition frequency
Pulse width

IPOmin
IR
ISC
PRF
PW

t+
ttpd+
tpdtwp
twr
TPin
TPout
VBE
VCC
VCCH
VCCL
Vo
VF
VIH
VIL
Vin
Vmax
VOH
VOL
VR

Voltage rise time
Voltage fall time
Turn-off delay time
Turn-on delay time
Write pulse time
Write recovery time
Test point at input of device under test
Test point at output of device under test
Base-emitter voltage
Power supply voltage
Maximum operating power supply voltage
Minimum operating power supply voltage
Input clamp diode voltage
Input forward voltage
Logic "I" state input voltage
Logic "0" state input voltage
Input voltage

VRH

Maximum rated power supply voltage
Logic "I" state output voltage
Logic "0" state output voltage
Input reverse voltage
High-state reference voltage

Vth "0"
Vth "I"

logic "0" state input threshold voltage
Logic "I" state input threshold voltage

GENERAL INFORMATION

MTTL

MTTL MC4300/4000 Series
Complex Fundions

0.005

.....l 0.035

•

4=~lOC:l;'rd.l

0.603

PACKAGING

-

O.006 D•I19,

Package type is denoted by a suffix to the part
number as follows:
SUFFIX

F SUFFIX
14-PIN
CERAMIC PACKAGE
CASE 607
TO-86

0.030

[ffi

~

O.1i7li

O.04!)
0.055

(ffii5

0.010

001'11

I...J

DESCRIPTION

F

Ceramic Flat

L
p

Ceramic Dual In-Line
Plastic Dual In-Line

Lead'identifiadbycolardot orbVelbowonlead.

To conven inches to millimeters multiply by 25.4
All JEOEC dimenSlOllS and notes apply

0.190...1
if2l"D I

LSUFFIX
14-PIN
CERAMIC PACKAGE
CASE 632
TO-116

l-..J l-!!.!m
I
I I 0.110

INDEX~

... ~

!Il!~ .680----d
~~~ ~l
r--rmo

j

~lmU

MIN

t----::
I '290 I"""'*'i DJTII

SEATING
PLANE

0.0118

j\--

AllJEOECdlmenslollsandnotesopply

0.325
MAX
0.290

o.m
(j)

~OllO

&lirnnrrrn=L
m
r
r IL~~\
o:ns
0090

rna

~

00 to 150

0015

irn2D

SEATING PLANE

CDThis dimension is I1l8IIlIH'ed from thalud cen~'
atth••atinll plane with tndsverucal.
Q)lead 1 ldentifltd by color dot, notth In Ilad,
ornotchincaramlc.
To convert inches to miUimetersmuiliplybyZ5.4

To convartinch8$to millimetarsmuitiply by 25.4.
AIIJEDEC TO·116 dimensions and notes apllly.

Four inwlatingstand-offsars IJrovlded
To COllvert IlIclles to millimeters multiplybV 25.4

-

1

\l.

im'5\\

f~::::::U~

;~~:::::::1~
JLO.D57
Lr---&; - -1--.1

1::2~
I,fflll'lf!0'200a
~
- - - - - - T_Mf--ffl-'29D
~
I

LSUFFIX
16-PIN
CERAMIC PACKAGE
CASE 620

PSUFFIX
14-PIN
PLASTIC PACKAGE
CASE 605
TO-116

PSUFFIX
16-PIN
PLASTIC PACKAGE
CASE 612

iSlo lead canterlinewhen fO/med paraJJel.
G) 4 iosulating stand·ofhare provided.
To CtHlwrt inches to miUimet&rs multipl-y by 25.4

~Oimension

MC4300/MC4000 series

DUAL 4-CHANNEL
DATA SELECTOR

MC4300F,L*
MC4000F,L,P*

B 5

A

-- :::}- To Othe, Data
Selector

3

I

This device consists of two four-channel data selectors with common control lines, constructed from highlevel AND-OR gates and low-level inverters. By selecting one of four logic combinations, information on
one of the four data inputs will be routed to the output.
Data selectors are useful in applications where digital data is to be routed from one of several registers
or locations to another register or location for processing.

1/2 OF DEVICE SHOWN
(Numbers and symbols in parenthesis are for other half of device.)

TYPICAL PROPAGATION DELAY TIMES (ns)
TA = 2SoC
XO 6
(YO)
(2)

INPUT

Z

CONDITIONS

f--';:A:--t_....,.,18~-I XO =X2=X3=logic 110", Xl

t--!;B';--+__1,,5=----I'ogic "1".

~------------~t::::t~l~

X1

X1 7
(Y1) (1)

11

=

A and B are de-

fined by the logic equations.

LOW-LEVEL INVERTER

~------------=+===+~L-"

X2 8
(Y2) (14)

Vee
Vcc~

o---------~====~~

GND

~

PIN 4
PIN 10

4k

X3 9
(Y3) (13)

Z ~ ABXO + ABX1 + ABX2 + ABX3
W =- ABYO + ABV1 + ABY2 + ABY3

:J: Diode used

Input Loading Factor;::: 1

only

~oh:;e~~~~~~s

Output Loading Factor::: 10

--{»>-

external point.
Total Power Oilsipation == 150 mW typ/pkg

HIGH-LEVEL "AND-OR" GATE

Vee

:t: Diodes used only when inputs are connected to external points.
"'F suffix
L suffix
P suffix

= TO-86 ceramic flat package (Case 607).
= TO-116 ceramic dual in-line package (Case 632).

= TO-116 plastic dual in-line package (Case 605).

wee:

;((1\1

•

ELECTRICAL CHARACTERISTICS

s

(1
~

W

o

o

3 o------l A

5

B

z

"TI

11

~

r-

6 o------l XO

~

s

Xl
8

X2

9

X3

2

(1
~

o
o
o

YO

Yl
14

Y2

13

Y3

W~12

' - - - -....

T.!p::ure lOLl
-5SoC
16
{
+25°C 16
+12SOC
16
oDe 16
{
+2SoC 16
+16°C 16

MC4300

MC4000

Characteristic

Pin r-~~=r~~~~~~:i--"'~~~~~~~~=r--~
~::r f-;;;::,!]7.:C:+-=-T;::-::-t-;~r.;::-I-;;;:T=:h;;2T;;::::-t-;;:Ti:::l

Unit

Symbol

lOU
18.4
18.4
18.4
17.6
17.6
17.6

"TI

TEST CURRENT!VOlTAGE VALUES
Volts

mA

IOH
-1.6
-1,6
-1.6
-1.6
-1.6
-1.6

liD

V,L

lin
1.0 -10
-10
-

IT
1.1
0.8

1.1

t.ot

__-.__-.__-.__

..!.:..!.
0.9

V'H
2.0

VIHX

1.8
1.8
2.0

2.5

~
1.8

r-

VF

VR

VCCH

D.4

2.4

5,5

0.4

2.4
2.4 t 4.0
2.5
4.0
2.5

5.5
5.5
5.25
5.25

0.4

0:4
0.4
0.4

5.0 t
5.0

4.5

2.5

I

'""0

8
:J

....

S"

t:
CD

5.25

'--rT~E~S~T~CU~R~R~E~N~TI~V~O~LT~A:G~E~A:P=PL;'E~O:T:O~P:'N:S~L~'S~T~E:D~B;E:LO=W;''-__~-''-__~~-1
V,L
VF
VIH I VIHX
Vn I VRH I Vmax I Vee I VCCL I VCCH

Input
Forward Current

L"k,,, Cu,,,",
B",kdow" Volt",
CI.mp Volt.,.

5
G...
3,5,10

I
I
I

Output
Output Voltage

Short-Circuit Current

IR
BVi"
Vo

I
I
I

6
6
6

I - I 40 I - I 40 I - I 40 I - I 40 I - I 40 I - I 40 I
I - I - I 5.5 I - I - I - I - I - I 5.5 I - I - I - I
I - I - I - I -1.5 I - I - I - I - I - I -1.5 I - I - I
0.4
0.4
0.4
0.4
- 1 2.41 - 12.4

VOL

11
11
11

0.4
0.4
2.41-12.4

0.4
0.4

VOH
ISC

11

-30 1 -1'001 -30

100 1 -30 I -1001 -30 I -1001 -30

0.4
0.4
2.41

-

12.41

I -100 I

-30

0.4
0.4

I

-100

pAd,
Vd,
Vd,
Vd,
Vdc
Vdc

I - I - I - I- I- I
I - I - I - I6 I- I
I - I - I - I- I6 I
11
11

11

mAde

1,2,3,5,6,7,8,9,13,14
, 1,2,3,5,6,7,8,9,13,14
1,3,5,7,8,9,13,14

I - I - I
I - I - I
I - I - I

I 3,5,61 - I - I - I I - I 3,5 I - I - I I - I - I - I - I 4

I
I
I -

3,5,10
10

I

10
10
10
10

2,6
2,5,6,8,9,13,14

-

, 1,3,7

10
10,11

Power Requirements
IT~tal

Device)

Maximum Power
SupplV Current

I

'max

65

65

_d,

Power Supply Orain

I

fpO

45

45

otAd,

SWttching Paramaters
Turn-On Oelay

1,2,3,5,6,7,
8,9,10,13,14

Pulse In

I

1,2,3,5,6,7,
8,9,10,13,14
pUl7,out

1,2,3,5,7,8,
9,10,13,14

tpd_l I

11

16

16

tpd_2 I

11

22

22

11

tpd_3 I

11

27

27

11

1,2,5,B,8,

tpd+1 I

11

16

16

11

1,2,3,5,7,8,
9,10,13,14

tpd+2 I

11

22

22

11

1,2,3,7,8,
9,10,13,14

tpd+3 I

11

27

27

11

1,2,5,B,8,
9,10,13,14

1,2,3,7,8,
9,10,13,14
9,10,13,14

Turn-Off Delay

MC4300F ,L, MC4000F ,L,P (continued)

INPUT AND OUTPUT LOADING FACTORS
with raspact to MTTL and MDTL families

FAMILY

MC4300
INPUT
LOADING
FACTOR

MC4300
OUTPUT
LOADING
FACTOR

MC4300
MC500
MC2100'
MC3100
MC5400
MC930

1.0
1.23
0.8
0.8
1.0
1.0'

10
12.3
8
8
10
10

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

1.0
1.0
0.67
0.7
1.0
1.15 •

10
10
6
8
10
12

.. Applies only when input is being driven by MDTL gate with 2.0 kilohm pullup resistor.

Logic "1" state drive limitations

0(gate5 with 6.0 kilohm pullup resistors reduce drive capability to fan-out of 3.

SWITCHING TIME TEST CIRCUIT
2.4 V

I

Coax·

950 ± 1.0%

TPin

"

PULSE
GENERATOR

3

B

6
8
9
2

950.± 1.0%

XO
X2
X3

/

TP out

YO
Yl

14

PW = 200 ns
t+ = t- = 5.5 ±O.S os
Amplitude = 2.5 V

13

= 25 pF

z

11

XI

50

PRF = 1.0 MHz typ

CT

Coax·
A

Y2

w

12

Y3

= tOtal parasitic capacitance, which includes probe, wiring, and load

capacitances.
·The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedanc::e. The 950-ohm resistor and the

scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT·070·50 or equivalent.

VOLTAGE WAVEFORMS

ir-----------------,l-+-::-;;:-;-;---2.5 V

TPout

1.5 V
t p d+1
t p d+3

TP O'ut

1.5 V

tpd-2

1/4 MC3000

I

MC4300F ,L, MC4000F ,L,P (continued)

TYPICAL PROPAGATION DELAY TIMES

I

FIGURE 2 - THREE-GATE DELAY versus TEMPERATURE

FIGURE 1 - FOUR-GATE DELAY versus TEMPERATURE

.
s

26

w

~5~PF

r-- _ _ _ 25 pF

:<

V

;:::
>-

«
..J

24
,

w

~

Cl

z

o

22

«
Cl

..«o
..

.....-

\

I-

~'::>.

20

---'-

18

-75

--50

o

-25

,/'

!-' tpd_

z

",'"

16

Q

.......

I-

«
Cl

..o«
..

tpd+

5iOPF
25 pF

"- ..........
...... ...

w
Cl

"'~

........... '--

~
r- ___

18

«
..J

I?'

0

",""

.,.--

0:

j

,/

20

:<
;:::
>-

./V

V

tpd_

tpd+

!w

V

~

tpd+ ~

~

k:;:::::::: ~pd-

---1"-- --

~

~

....
....

..........
",""

tpd+

tpd _

14

l

0:

25

75

50

100

12
-75

'tl
~Q.

125

--50

-25

o

25

50

75

100

125

TA. AMBIENT TEMPERATURE (oC)

TA. AM81ENT TEMPERATURE (oC)

FIGURE 3 - TWO-GATE DELAY versus TEMPERATURE
c

15

~50P~

w

~

>-

13

«
..J

w

Cl
Z

--

«
Cl
«
o

9.0 r - - r--tpd_

-0

7.0
-75

...:- f.-::::

.:+---

..
0:

~Q.

--50

I

tp~ ~
t pd _,......-

........

';:::

.

25 pF

....... r-

"- tpd+

11

o

---

"

I-

........

--

o

-25

-- --

25

.... ~ ....

~I-'".

75

50

100

125

TA. AMBIENT TEMPERATURE (oC)

.
s

FIGURE 4 - DELAY versus LOAD CAPACITANCE
28

w

:<

;:::
>-

:3w
Cl

24
20

;:::

16

0:

4.0

o

----

(4G.tes~ ~

::J---"(4 Gates1
tpd+
I-

(3 G a , e s 1 , _

i=-I.
es1

,.......

I,

Ga,es1

tpd+ ~

(3 Gat

_

12
8.0

j

-

'pd-

«
Cl
«

..o
..

-

~ r-

tpd+

Z

o

---=

tpd-

-

~sl

tpd-

30

t:;;;:
~
r---

VCC = 5.0 VdcTA = 25°C
-

Fan-out

o

FIGURE 5 - DELAY versus SUPPLY VOLTAGE

60

90

= 1

120

CL. LOAD CAPACITANCE (pF)

28

CL = 25 pF

w

:<

;:::
>-

tpd_ (4 Gates)

«
..J

20

Cl
Z

16

o

;:::

12

«
Cl
«

..o

8.0

-0

o

w

-

..

150

~Q.

0:

I

TA = 25°C

24

~

!

tpd+ (4 Gates)

J

tpd+ (3 Gates) -

==

tpd_ (3 Gates) _

-

tpd+ (2 Gates) -

-

~pd_ (~ Gat~s)_ -

4.0

4.5

I

1

j

5.0
VCC.SUPPLY VOLTAGE (VOLTS)

5.5

MC4300F ,L, MC4000F ,L,P (continued)

FIGURE 6 - 1-BIT 16-LINE DATA SELECTOR

TYPICAL APPLICATIONS
B

o

A

C

Data selection from one of sixteen inputs can be accomplished by using multiple MC4300/4000 data selector
units, as shown in Figure 6.
An N-bit data selector network may be realized by
paralleling N/2 data selectors as shown in Figure 7. Each
bit is selected from its own group of four different inputs;
therefore from each dual data selector we can obtain two
bits. Thus, for N bits we need N/2 dual 4-line selectors.

XO
Xl
X2

1/2
MC4300/f-f-I---,
MC4000

X3

FIGURE 7 - N-BIT 4-LINE DATA SELECTOR
X4
X5
X6

1/2
MC4300/f-f-I---,
MC4000

B

A

X7
1/2
MC4300/
MC4000

00
XOl
XlI

X8

X21

X9

1/2
MC4300/
MC4000

00

1st Bit

1/2
MC4300/
MC4000

01

2nd Bit

X31

Xl0
XlI

X02
X12
X12
X13
X14

X22
1/2
MC4300/
MC4000

X32

X15

0

C

8

A

00

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

XO
Xl
X2
X3
X4
X5
X6
X7
X8
X9
Xl0
XlI
X12
X13
X14
X15

.4<

1/2
MC4300/f----o ON
MC4000

Nth Bit

B

A

XOn

Xln

X2n

X3 n

an

0
0
1
1

0
1
0
1

1

'"

''""
'"

''""

XO
Xl
X2
X3

''""
'"

q, = Don't care

1

''""

n = any number up to N

1

'"
1

I

BCD-TO-BINARY!
BINARY-TO-BCD
NUMBER CONVERTER

MC4300/MC4000 series

MC4001L,P*

•

4-Blt Number

10

15

Enable

6

7

9

The MC4001 is derived from the XC170!171 128-Bit Read Only
Memory. It serves as a basic building block in Binary-to-BCD and BCDto-Binary converters. Conversion of any length binary or BCD word can
be accomplished by interconnecting MC4001 packages. The MC4001
also contains a full adder and subtractor.
3

2

4

5

11

12

14

13

Features:
Address times < 45 ns
Outputs sink 16 mA
Output capacitance < 7.0 pF

~~

4-Sit BCD

4-Bit'Binary

VCC ~ Pin 16
GND = Pin 8·

@

1.5 V

TRUTH TABLE (POSITIVE LOGICI
OUTPUT

INPUT
D
0
0
0
0
0
0
0
0

,,
,,
,,

C B A
0 0 0
0 0 1
0
0
0
0 0
1 0 1
0

0
0
0
0
0

,
,,, ,
,, ,
,
, ,
, , , ,,
, ,, , ,

0

0
1 0
0

1

Binary to BCD
7 6 5 4

1

1
0
0
1

1
0

0
0

0

1
1
1

0
1

1

0

1

0

,,
,,
,
,,,
,, ,, ,,
,

0
0
0
0
0

0
0
0

0
0

0
0
0
1
0

0

0

0
0
1

0

0
1
0
0
0

BCD to
3 2
0 0
0 0
0 0
0 0
0
0
0
0 1

0
0
1
0

0

0

0

0

0
0
1
1
0
0
0

,,
,
,
,
1

0
0
0

0
0

ENABLE INPUT TRUTH TABLE (POSITIVE LOGIC)

Binary
1 0
0

E

E

07

06

05

04

03

02

01

00

0

0

0
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

,, ,,
,, ,,
,, ,
,, ,

0
0

0
0

0
1
1

0
1
0

0
1

FUNCTION ENABLED

0

0

0

0

0

0

0
0
0

"NAND" GATE EQUIVALENT
OF BCD-TO-BINARY CONVERTER

"NAND" GATE EQUIVALENT OF BINARY-TO·BCD CONVERTER

00

04

~-----------O05

01

~===C::)----<>06
02

A 0-+++----"-+1-."
B

0-4-+_----'

C~~+_---~~_1~

03

Do--+-----~-~-I

B <>--t-i.......-_1~

c

~-H---l--1

00--+----1

• L suffiK = 16-pin dual in-line ceramic package (Case 620),
P suffix = 16-pin dua(in-Hne plastic package (Case 612).

»--+-----------0 07

MC4001 L,P (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL famili..

FAMILY

MC4001
INPUT
LOAOING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

MC4001
OUTPUT
LOADING
FACTOR

Note: Differences in MC4000 series loading factors r..ult from
differences in specifications for each family.

5
5
5

1.0
1.0
0.67
0.7
1.0

•• Applies only when input is being driven by MDTLgate with 2 k ohm
pullup resistor. Logic "'" state drive limitations of gates with 6 k
ohm pullup resisfors reduce drive capability to fan-out of 3.

6
10
11

1.15··

•

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7.0

Vdc

Supply Operating Voltage Range

Vee

Input Voltage

Yin

4.75 to 5.25
-0.5 to +5.5

Vdc

Power Dissipation (Package Limitation)
Derate above TA=25 0 e

PD

625
5.0

mW
mW/oC

°c
°c

Rating

Operating Temperature Range

TA

oto +75

Storage Temperature Range

Tstg

-55 to +125

Vdc

ELECTRICAL CHARACTERISTICS (TA = 0 to +750 C)
Symbol

Characteristic
Address Input Forward Current
(VA = 0, Vee = 5.0 Vde)

IF

Enable Input Forward Current
(VE = 0, Vee = 5.0 Vde)

IF

Address Input Leakage Current
(VA = 5.5 Vde, Vee = 5.0 Vde)

IR

Enable Input Leakage Current
(VE = 5.5 Vdc, Vee'" 5.0 Vdc)

IR

Min

-

Max

Unit
mAde

1.6
mAde
1.6
IlAde
100
IlAde
100

,

Logical "0" Output Voltage
(IOL = 16 mAde, VIL = 0.9 Vde, VIH = 2.0 Vdc, Vee = 4.75 Vde)
Logical "1" Output Voltage
(VIL = 0.9 Vdc, VIH = 2.0 Vde, IOH = -0.5 mAde, Vee = 4.75 Vdc)
Power Supply Drllin Current
(Memory Enabled, Vee = 5.25 Vde)
(Memory Disabled, Vee = 5.25 Vde)

VOL
VOH

Vde

-

0.45

-

2.S

Vde
mAde

IpD
9~

55

SWITCHING TIMES (VCC = 5.0 Vdc, T A - +250 C)
Positive Input Address to PoSitive Output
Negative Input Address to Negative Output
Positive Inl/ut Address Or Enable to Negative Output
Negative Input Address or Enable to Positive Output

4".. 4

IOL= lOrnA
driving
30 pF

(ism

-

45

ns,

45

ns

tA+Q-or
tE+Q-

.45

ns

tA-Q+ or
tE-Q+

45

ns

tA+Q+
tA-Q-

...

MC4001 L,P (continued)

TYPICAL APPLICATIONS
FIGURE 1 - BINARY-TO-BCD CONVERSION

FIGURE 2 - BCD-TO-BINARY CONVERSION

•
BCD
DIGIT 3

BCD
DIGIT 2

BCD DIGIT 1

EQUIVALENT CONVERSION ALGORITHM

1. Examine three most significant bits.
If

sum.,

5, add 3.

BINARY

2. Shift laft 1 bit.
3.

Examine each BCD decade.
add 3.

If sum

~

5,

EQUIVALENT CONVERSION ALGORITHM
1. Shift BCD number right 1 bit. Examine

4. Shift left 1 bit.
5. Is least significant bit in least significant
BCD position: If "no", loop to item 3.
If "yes". conversion Is fInished.

each 4-bit decade. If

~8,

subtract 3.

2. Shift right and examine untif n-4 levels
of examination are completed.

Delay time = 225 ns max

(n equals total number of bits In BCD
input code.)

FIGURE 3 - 4-BIT BINARY ADDER OUTPUT CONVERTED TO BCD
S4
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

53
C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0

52
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

.

51
A

N4

N3

N2

Nl

NO

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0

0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1

0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0

4-BIT BINARY
ADDER

I

IS4 153
TRUTH TABLE

1:7

I

I

SO

S2 lSI

C
B
MC4001
Q6 Q5 Q:I

11,
1 ---Nt

BCD
TENS

NO

BCD UNITS

MC4001 L,P (continued)

FIGURE 4 - BLOCK DIAGRAM

I
Many functions can be designed from the
XC170/171 Read Only Memory. TheMC4001
BCD·to·Binary/Binary·to·BCD converter is
made from the XC171, which has 2.0 k ohm
pullup resistors on the outputs. Through use
of a computer·designed metal mask, the truth
table shown on the first page of this data
sheet is programmed into the Memory by
etching out metal links from the device metal·
ization where a 10gic"1" level must be stored.
Logic "O"s are stored where links are not
removed.

ROM Array
Enable
Inputs

16 Words
Of 8 Bits

ROM {

A~:~:

4 AmplifierInverter Pairs
Decode Array

C
o

:

8 Output

Buffers

Drivers

07

00

~
Data Output

FIGURE 5 - REPRESENTATIVE CIRCUIT
Word 15

Bit 7

,---- ---,

Inputs {
Enable

r-1===r=~~~~~g[::~~'T----:=--t'-

------------>-~

1111

j

Bit 0

______~
I

I

:

l_______

Word 15

r -- -----,

I
I

I

I

I

r-- -- - -,

A

I Bit 7

I

0000

1

I

Word 0

r-----

I Bit 0

1
I

B

--I

I
1
1
1

I

ROM
Address

I

I
_J

Inputs

e
<0

•

Z 4

I

~ _ _ _ _ _ _1

I
I

Word 0

:

Vee

. Q$lii4\"M +4

47

Links removed if logic "1" state desired•

Vee

MC4300/MC4000 series

DUAL DATA
DISTRIBUTOR

MC4002F, L, p~

•

ADVANCE INFORMATION/NEW PRODUCT
B 13

A

X

11 20

3

5

20 ~ ABX
21 ~ ABX
22 ~ ABX
23 ~ ABX
wo~

Wl

y

7

:

TYPICAL PROPAGATION OELAY TIMES (ns)
TA = 25°C

Cy

~ey

t G>o

[hg:'
H

~

INPUT

20

21

22

23

A

14.5
14.5
10.5

10.5
14.5
10.5

14.5
10.5
10.5

10.5
10.5
10.5

23
B

9

Input Loading Factor:
A, B ~ 3

e, y

21

12 22

2

e

This device consists of two data distributors con·
structed from high·level AND gates and low·level in·
verters, One distributes information present at the
input line to one of four output lines; the other dis·
tributes information present at the input to one of
two output lines, The routing path is selected by the
logic signals at the control lines A, B or C.
Data distributors are useful in applications where
digital data is to be routed from a single register or
location to one of several registers or locations for
processing.

X

wo

Wl

INPUT

wo

Wl

e

14.5

Y

10.5

10.5
10.5

Vee ~ PIN 4
GND ~ PIN 10

2

X~4

Output Loading Factor"" 1 0
Total Power Dissipation = 175 mW tvp/pkg

HIGH·LEVEL "ANO" GATE

LOW·LEVEL INVERTER

Vee
Vee

4k
4k

4k

:j:Diodes used only
when inputs are
connected to
external points .
• F suffix = T0-86 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).

P suffix

= TO-116

plastic dual in-line package (Case 605).

2k

1k

100

MC4002F, L, P (continued)

INPUT and OUTPUT LOAOING FACTORS
with respect to MTTL and MOTL families

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

1.0
1.0
0.67
0.7
1.0
1.15**

10
10
6
S
10
12

Note: Differences in MC4000 series loading factors result from

differences in specifications for each family.

** Applies only when input is being driven by MDTL gate with
2.0 k ohm pull~p resistor. Logic "'" state drive limitations of
gates with 6.0 k ohm pullup resistors reduce drive capability to
fan-out of 3.

DC ELECTRICAL CHARACTERISTICS
(TA = 0 to 7soCI

Characteristic

Symbol

Value

Conditions

Input
Forward Current - A, B
C,Y

-4.S mAde max
IFl

X
A,B
C,Y

Threshold Voltage

Yin = 004 Vde, V CC = 4.75 Vde

120 "Ade max
IR

X
Clamp Voltage

-2.8 mAde max
-5.6 mAde max

Leakage Current - A, B

Breakdown Voltage

Yin = 004 Vdc, VCC = 5.25 Vde

-4.2 mAde max
IF2

X
C,Y

-3.2 mAde max

-604 mAde max

SO "Ade max

Vin = 2.5 Vde, VCC = 5.25 Vde

160 "Ade max
aVin

5.5 Vde max

I in = 1.0 mAde, VCC = 5.25 Vde, T A = 25°C

VD

-1.5 Vde max

10 = -10 mAde, VCC = 4.75 Vde, TA = 250 C

Vth "1"

2.0 Vde

TA -OoC

1.8 Vde

TA = +25 0 C, or TA = +750 C

Vth "0"

1.1 Vde

TA = OoC, or TA = +25 0 C

0.9 Vde

TA=+750C

Output
Output Voltage

Short-Circuit Current

VOL

004 Vde max

IOL= 16 mAde, VCC = 4.75 Vde t

0.4 Vde max

IOL = 17.6 mAde, VCC=5.25 Vde t

VOH

2.5 Vde min

ISC

-20 to -65 mAde

IOH = -1.6 mAde, VCC = 4.75 Vde t
V CC = 5.0 Vde. output grounded t

tThese tests are performed according to the logic equations with a true input equal to Vth "'" and a false
input equal to V th "0".

I

MC4300/MC4000 series

16-BIT SCRATCH PAD
MEMORY CELL

MC4304F, L • MC4305F, L*
MC4004F,L,P • MC4005F,L,P*
This 16-Bit memory cell serves as the basic building
block for scratc!'! pad memory systems having cycle times
of less than 100 ns. The basic cell provides 16 words of
one-bit memory operating in the non-destructive readout
~NDRO) mode.
The memory contains 16 flip-flops arranged in a fourby-four matrix. A single bit of the matrix is selected by

5

driving one of four X select lines and one of four V select
lines above the select threshold. Two sense amplifiers are
shared by all 16 bits and provide a double rai I output from
the selected bit. The sense output of many devices can be
"wired ORed" together since the output stage does not
have a pullup resistor or network. Two write amplifiers
allow a "1" or a "0" to be written into a selected bit.

6
V,

8
V2

V4

V3

'3W",,, (Write"''')
X, 3

HI'.'

~

H

~

H

~

~

~

~

~

~

2,1

I

~

3,'

I

~

1.2

~

2,2

',3

1
2,3

9 W"O" (Write "0")

0
~0
~

V cc= Pin 4
G ND=Pin10

tpd: Wri te Mode = 25 ns typ
Sen58 Mode = 15 ns typ
Po= 250 mW typ/pkg

8 1;)=

3,2

~

4,2

H~-~

12 S",,, (Sen.e ",")

~ ~

4,1

I

1
4,4

~

'1 S"O" (Sen.e "0")

- OPERATING SEQUENCE FIGURE 1 - REAO MODE TIMING DIAGRAM

x, Y Select Lines

Sense Output
S",,,

A
I
I
I
I
I
I
I

1.0 Megohm) must be

DEVICE UNDER TEST

Rl
OHMS

R2
OHMS

MC4304, MC4004
MC4305, MC4005

120
240

330
560

See Switching Time Test Procedures

used when taking measurements.

tabJe for val!Je of CT'

VOLTAGE WAVEFORMS AND DEFII\IITIONS

10 ns max

10 ns max

J.-----'-----~-,l=:::l=....:r_---3.0

A

P·RF - 1.0 MHz

PROPAGATION DELAY
TIME
B

V

TPin

'"FG""

=~r:_::_=_=_=_=_=~2~0~0~n~s~=_=_=_=_=_=_=_=__::~==':::===0.4 V

TP out

--------~=====================~-----GND
.1<----,l=b.... . - - - - - - - - - - - 3 . 0
C

TPin
PRF - 5.0 MHz

D

TP out

V

GNDV
=~.!:::.~~~========================0.4
Output not

GND

_ ___~d~.~fi~n!ed~____~==============t=======,
RECOVERY TIME
E

TPin
PRF - 5.0 MHz

==================:.r:~~=+==0.4 V

~rl

F

TPout

GND

~~v
defined

.

GN D

MC4304F,L, MC4305F,L, MC4004F,L,P, MC4005F,L,P (continued)

•

SWITCHING TIME TEST PROCEDURES
(Letters shown in test columns refer to waveforms)

Test
TurnMOff oelay Time
(Address Lines to
sense "0" Output)

Turn·Off Delay Time
(Address Line. to
Sense" 1" Output)

Pin
Symbol Under

....

Test

tpd+
tpd+

11

....

tpd+

....

tpd.+
Turn-On Oelay Time

{Address Lines to
Sense "0" Output)

tpd_

....
....

tpd_

Turn-On Delay Time
(Address Lines to

Sense "1" Output)

tpd_

tpd_
Turn-Off Delay Time
(4 Bits) (Address Lines

to Sense "0" Output)
Turn-Off Delav Time
(4 Bits) (Address Lines
to Sense "1" Output}

Write Recovery Time

Write Pulse Width

Output

Input I;'in
3
X,

2
X2

1

14

5

6

X3

X4

Y,

Y2

7
Y3

8
Y4

Limits
CT" MC4304-5 MC4004-5
nsmax
nsmax
W"O" W",,, S"O" S"," pF
9

12

-

-

-

-

-

B

-

30
200

23
35

23

3.0 V 3.0V 3.0 V 3.0V 3.0 V
3.0 V Gnd Gnd Gnd 3.0 V
A
Gnd Gnd Gnd
A
A
Gnd Gnd Gnd
A

3.0 V 3.0 V 3.0 V 3.0 V

-

-

-

-

-

Gnd

Gnd

Gnd
Gnd

3.0 V 3.0 V 3.0 V 3.0V 3.0 V
3.0 V Gnd Gnd Gnd 3.0 V
Gnd Gnd
Grid
A
A
Gnd Gnd Gnd
A
A

3.0V 3.0 V 3.0V

Gnd

3.0V

3.0 V 3.0 V 3.0 V 3.0 V 3.0 V
3.0 V Gnd Gnd Gnd 3.0V
Gnd Gnd
Gnd
A
A
Gnd Gnd Gnd
A
A

3.0V 3.0 V 3.0 V 3.0 V

12
12

-

3.0V

12
12

11
11

-

Gnd

Gnd

Gnd
Gnd

Gnd
Gnd

Gnd
Gnd

Gnd
Gnd

Gnd

Gnd

Gnd
Gnd

Gnd
Gnc(

Gnd 3.0 V
Gnd Gnd
Gnd
Gnd

B

3.0V

-

Gnd

-

Gnd
Gnd

B

Gnd

-

B

Gnd

Gnd

Gnd

Gnd

E

C

Gnd

Gnd

Gnd 3.0 V

Gnd

Gnd

Gnd

E

C

-

• Capacitance value for load of the Swi~ching Time Test Circuit
• ·Precondltioning procedures for subsequent test.

Tested during 'twr tests.

35

23

-

-

-

-

-

30

35

35

-

-

-

B

30

35

35

0

30

40

-

30

40
40

"smin

nsmin

25

25

B

Gnd 3.0 V

23
35

-

Gnd

30
200

-

Gnd

Gnd

-

,,3
35

Gnd

3.QV
3.0 V

-

-

3.0 V

12
11

-

-

3.0V 3.0V 3.0 V 3.0V 3.0 V 3.0V 3.0 V 3.0 V Gnd
Gnd Gnd Gnd 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V
A
Gnd Gnd
Gnd
A
A
A
A
Gnd

12

-

35

-

-

23
35

Gnd
Gnd

twr

23

-

3.0 V

Gnd
Gnd

tpd+

-

23
35

30
200

Gnd

Gnd
Gnd

3.0 V

30
200

-

B
B

Gnd

Gnd
Gnd

Gnd

B
B

35

-

Gnd

Gnd
Gnd

3.0 V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0 V 3.0 V 3.0 V
3.0V Gnd Gnd Gnd 3.0 V 3.0 V 3.0 V 3.0 V Gnd
Gnd Gnd Gnd
A
A
A
A
A
Gnd

-

Gnd

Gnd

11

twp

11

3.0·V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V Gnd 3.0 V
3.0 V Gnd Gnd Gnd 3.0 V Gnd Gnd Gnd 3.0 V Gnd
Gnd Gnd Gnd
A
A
Gnd Gnd Gnd Gnd
Gnd
A
Gnd und und
A
Gnd Gnd Gnd
Gnd
Gnd

-

....

tpd+

13

-

F

-

-

-

40

MC4300/MC4000 series

BINARY TO ONE-OF-EIGHT
LINE DECODER

MC4306F,L*
MC4006F,L,P*

1000
8
Enable

1101

1202

1303

4

Ci4

3

05

2

Q6

1

Q7

This device converts three lines of input data to a
one·of·eight output. The enable line provides an in·
hibit capability and also allows the decoder to be expanded for larger decoder systems.
The 3·input/B-output decoder consists of high·level
and low· level gates ·internally connected for minimum
power consumption and maximum driving capabilities.
The enable gate must be in the low state to perform
the decode operation shown in the truth table.
The propagation delays shown in the charts are
typical and vary according to loading, interconnection
wiring length, and the number of logic levels involved.

A 5
TRUTH TABLE

8 6
Vee = Pin 14
GND

e 9

= Pin

7

Input Loading Factor = 1

Output Loading Factor = 10
Total Power Dissipation;;: 100 mW typ/pkg

LOW·LEVEL INVERTER

1 = High State
0= Low State

TYPICAL TURN-ON DELAY TIMES Ins)

T A = 2SoC, Cr
INPUT

:f: Applies

only to
input gate.

~

E

HIGH·LEVEL GATE

00

01

11.5

16.0

02

=

25 pF

Q3

04

Q5

Q6

Q7

16.0

11.5

16.0

11.5

16.0

11.5

11.5

160

16.0

11.5

11.5

16.0

16.0

11.5

11.5

11.5

11.5

16.0

16.0

l~.O

16.G

13.5

13.5

13,5

13.5

13.5

13.5

13:5

13.5

Vee
4k

1.2 k

100

·F suffix == T,O-86 ceramic flat package (Case 607).
L suffix'" TO:116 dual in-line ceramic package (Case 632).
P suffix"" TO-116 dual in-Hne plastic pac~age (Case 605).

TYPICAL TURN-OFF DELAY TIMES Insl
TA = 250 C,CT=25 pF
rNPUT

00

Ql

02

53

A.

Q5

56

A

14.0

19.5

14.0

19.5

14.0

19.5

14.0

19.5

14.0

14.0

14.0

14.0

14.0

19.5

19.5

19.5

19.5

14.5

14.5

14.5

14.5

14.5

14.5

14.5

14.5

Q7
19.5·

19.5

•

•

ELECTRICAL CHARACTERISTICS

s

(')

Test procedures are shown for only one

f)
o0)

input and one output. Test other inputs
and outputs in the same manner. Additionally. test,all input-output combinations
according. to the truth table.

..r-

"T1

s

~

10

8

01

o
o0)

11

0212

5---lA

03

6---lB

9---lC

"T1

13

Q4

4

05

3

06
07

2

@Te..
I •..

Temperalure I u.,
-55'( ...

I

MC4306

r

+25'(
\ +12S'(

I

OO(

Characteristic
Input

S.l!!!boI

Forward Current

IF

Leakage Current

I '7.

...

M(4006 Tost limits
MC4306 TOSI limil.
0'(
+2S'( I +7S0(
+25'( I -I'12S'(
Min I Max Min Max Min Max Min Max Min Max Min Max I Unit I

Clamp Voltage

. -

V.

Volts
VRH

2.'

'.0

'0

'.0

"

'.0

'7. : "...n ,-,.. ".0,-'0,:.:,:. ,:.:
U

I

r

-.l.U

I

~

V__

7.0

'.0

2.5

'.0

2.5

'.0

7.0

5.0

4.5

5.5

5.0

'.5

5.5

~,

5.0

'.5

5.5

C

5.0

4.75

5.25

5.0

4.75

5.25

5.0

4.75

5.25

rEST (URRENT /VOlTAGE APPLIED TO PINS LISTED BELOW,

~1.

6

-1.6

-1.6

-1.6

-1.6

-1.6

mAde

.0

.0

.0

.0

.0

"Ade

lOll

I '0 ,2 I 10H I I" I 10 I Vil I .v IH

,

V, , V.

VRH

, Vm " , Vee , VCCl , VeeH I Gnd
14

'0

14

5.5

5.·5

Vde

-1.5

-loS

Vo

14

f

Vde

Short-Clrcuit
Current

VOLI

0.'

0.'

0.'

0.'

0.'

0.'

Vde

5,6,9

VOL2

0.'

0.'

0.'

0.'

0.'

0.'

Vd.

5,6,9

Vde

5.6.8.91

V OH

2.'

I-

2.'

I Be

-20

I -.5

-2.

Power Requirements
(Totar Devitt>

=~~u;::.~r

Ilmax

..

Power Supply Drain

I

14

IPD

2.5

2.'
-.5

-20

-65

-20

2.5
-65

-20

2.5
•• 5

-20

-65

-

14

14

-

14

mAde

51

51

mAde

3.

3.

mAde

....1..1"111"
-

5.6..

I -

I

n-O

VCCL

Oulput
Output Voltage

VeeH
~ .-~

Vee

-S5'(

BVin

BreakdoWn Voltage

.-

I

U

•. .1I 2 .•
I -,. I" 0 I -'0 I;': I:' I:':
-,. I - I - r ~.~ I:' I. :.~ T
I 2.'
I " : -,. I - , - , .. ' ,.. ,:.: 2.5

,..

~',

l

mA
I
I L._
u~ II Lun.. II I.- II L II V..
. ". II V_.~... II _v_~ I

I '0. I

MC4006l +2S'(:
+7s'(.n
Pin
Under
T••I

'i-

TEST (URRENT IVOLTAGE YAlUES

14

:::l

:::l
CD

0.

MC4306F ,L, MC4006F ,L,P (continued)

INPUT AND OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

FAMILY

MC4306
INPUT
LOADING
FACTOR

MC4306
OUTPUT
LOADING
FACTOR

MC4300
MC500
MC2100
MC3100
MC5400
MC930

1.0
1.2
0.8
0.8
1.0
1.0·

10
12
8
6
10
10

FAMILY

MC4006
INPUT
LOADING
FACTOR

MC4006
OUTPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MCB30

1.0
1.0
0.67
0.6
1.0
1.15'

10
10
6
8
10
12

•

* Applies only when input is being driven by MDTL gate with 2.0 kilohm pullup resistor. Logic "1" state drive limitations
of

gat~s'

with 6.0 kilohm pullup resistors reduce drive capability to fan-out of 3.

SWITCHING TIME TEST CIRCUIT
2.5 Vdc

Coax

E

.

950 ±. 1.0%

50
51

PULSE
GENERATOR

A

52

/

TPout

53
54

PRF = 1.0 MHz typ
PW = 200 ns
t+ = t- ;; 5.5 ± 0.5 ns
(10% to 90% points)

B

1/4 MC3000

55
56
lCT

C

57

Load required only
on output being

tenad

CT ;; 25 pF = total parasitic ca'pacitance. which includes probe, wiring, and load
capacitances.
*.The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor antfthe
!:!cope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT-070-50.or BCluivalent.

SWITCHING TIME TEST PROCEDURES (T A • 25 0 C)

VOL TAGE WAVEFORMS·

(Letters shown in test columns refer to waveforms.)

i..------"\.t-t------ 3.0 V

LIMITS
E

C

53

57

Max

Unit

tpd+

(C to 53)

Gnet'

X

Z

-

20

ns

tpc(-

(C to 53)

Gnd

X

Z

-

17

ns

tp'd't

(C to 57)

Gnd

X

-

Y

29

ns

tpd- '(C to 571
tpd+ lEta Q71

Gnd

X

-

y

23

ns

X

2.5 V

-

Z

21

ns

X

2.5 V

-

z,

20

ns

TEST'

tpd_

(EtoQ7)

X

-\f-~---1.5

V

"--'-=--~OV

;"2.4 V
y

---:,--_-b-,~====~~=:====,;;O.4 V

z

,------'--,+-'=--;;,2.4 V

MC4306F ,L, MC4006F ,L,P (continued)

TYPICAL SWITCHING TIMES

•

FIGURE 1 - TURN-"ON DELAY TIME'
versus TEMPERATURE
o

.s

28

w
:;
j::

_

I'

FIGURE 2 - TURN·OFF DELAY TIME
versus TEMPERATURE
o

.s

.1.

Vg~::: p~dC

j::

24

>-

«
-'
w

o

z

20

<;>

z

a:
~

16

I-

j

........

---

............ """- 3 G.tes

12
-55

f...--

-

2 Gates

o

-25

30

25

50

-

~

100

CT

26

«
-'

w

o

22

IJ.
IJ.

o
Z
a:
~

f..-- I-"
75

>-

'-.....

.;
125

--

o

26

j::

o

.s

= 5.0 Vdc
CT = 25 pF

:;

j::

22

>-

a:
~

14

I-

o

---

10
-55

I--

3 Gates

20

IJ.
IJ.

<;>
Z

a:

I--

2 Gates

~

,5l

24

-'
w

-'

18

:J

.;
..0.

o

25

50

75

100

16

I"0

-25

125

--

o

:;

1=

32

-'

w

o
z

<;>

20

.,........

a:
l-

.......- V

16

i

J.

- - - --i-'""'"

V

V f-'

12
25

V

....- .......50

75

.......- .......- 2 G.tos
100

CT. CAPACITANCE (pF)

125

150

32

w

-

j::

28 _

:;

3 G.tes..........

Z

~

0

.s

~

100

125

~

V

~

2 Gates

I
o

-25

V

25

50

~

75

~

100

125

FIGURE 6 - TURN·OFF DELAY TIME
versus CAPACITIVE LOADING

V~C ~.o V~c

24

75

TA. AMBIENT TEMPERATURE (oC)

f=
28 I-- TA = 25°C

>-

«

50

.,/'

3 Gates

-

12
-55

FIGURE 5 - TURN·ON DELAY TIME
versus CAPACITIVE LOADING

w

25

CT= 25pF

TA. AMBIENT TEMPERATURE 1°C)

.s

--

o

,/
f-'

vc6 = 5.0 ~dC
-

«

«
w

2 Gates
-25

28

w
:;

>-

o
z
o
Z

-:---

FIGURE 4 - TURN-OFF DELAY TIME
versus TEMPE RA TUR E

!.

I

I-- VCC

3 Gates

/'"

T A. AMBIENT TEMPERATURE (oC)

FIGURE 3 - TURN-ON DELAY TIME
versus ,TEMPERATURE

w

/

I

14
-55

TA. AMBIENT TEMPERATURE (oC)

.s

= 50 ~F

18

I-

J.

Vc~ = 5.0 ~dC

_

w
:;

>«.
-'
w

24

<;>
Z

20

a:
~

I-

.;

J.

16

--- -

--

12
25

--

TA = 25°C

f.-

0

IJ.
IJ.

v~c = ~.o v~c

-

3 Gates

I---!----

f.--

50

I--

75

1 i'
Ga

100

CT. CAPACITANCE (pF)

.......-

-

125

-...-

150

MC4306F ,L, MC4006F ,L,P (continued)

TYPICAL SWITCHING TIMES (continued)

.

FIGURE 7- TURN-ON DELAY TIME
verus POWER SUPPLY VOLTAGE
20

w

;;;

i=
>
~

.J

.

T~~2~Oe-

.=.

w
;;;

i=
>
.J
W

11.
11.

14

o

Z
:::>

a:
:::>

2 Gates

12

I-

18

16

14

2 Gates

.;

I

J.

Gat~s

Z

a:
l-

3

o

o

o

T~ 25~e-

20

~

3 Gates

W

z

22

oS

18

16

FIGURE 8 - TURN-OFF DELAY TIME
versus POWER SUPPLY VOLTAGE

10
4.5

5.0

J.

5.5

12
4.5

Vee. POVIER SUPPLY VOLTAGE (VOLTS)

5.0

5.5

Vee. POWER SUPPLY VOLTAGE (VOLTS)

TYPICAL APPLICATIONS
state 0 thru 7. enabling decoder unit 1 ~nd inhibiting decoder unit 2. For states 8 thr'u 15 the reverse is true. thus
providing the eight additional sta~es.needed for the fourth
input variable. Outputs 0 thru 15 anlselected by the natural binary code on inputs A. B. C, and D; however, the
MC4306/4006 can be used to decode any four-bit code by
appropriately choosing outputs to correspond to the inputs.

Combinations of MC4306/4006 decoders can be used to
produce various decoding operations. Figure 1 illustrates
the use of two of these binary to one-of-eight decoders
and one inverter to convert four digital inputs into one of
16 mutally exclusive outputs. In this operation the Enable
input of both decoders. in conjunction with the inverter.
is used for the fourth digital bit. The D input is low from

FIGURE 1 - BINARY TO 1-0F-16 DECODER

0

A

B

e
0

E

C

B

A

Device

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0

0
1
0
1
0
1
0
1

1

7
8
9

or Equiv

2
E

OutPl,.It

D

0
1
2
3
4
5

•

116 Me3008

Input

Output I
Terminal

10
11
12
13

,.
15

0

1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

1
0
1
0
1
0
1

2

•

MC4306F ,L, MC4006F ,L,P (continued)

FIGURE 2 - GATED BINARY TO 1-OF-64 DECODER
A' o-------...-l

•

B' o------..-+-l

C' O-----~+I--l

TYPICAL APPLICATIONS
(continued)

Output
Terminal C

,

0

0
0
0
0
0
0
0
0
0
0

2
3
4
5
6
7

.
"

0

'0

Figure 2 illustrates the use of nine
MC4306/4006 decoders in a 1-of-64 decoder.
If the Enable input is used as a·data input terminal, the data bit will appear at
the output terminal selected by the address on lines A, B, and C. Thus the
MC4306/4006 can be used as an eightline data distributor (demultiplexer). All
unselected outputs will be at a logic "1"
level. Figure 3 shows two MC4312/4012
four-.bit shift registers used in conjunction
with an MC4306/4Q06 to yield an eightbit serial data transmission system. The
MC4312/4012's convert eight bits of parallel data to serial for transmission to
another part of the system. The MC4306/
4006 receives the serial data and distributes
it to any of eight locations. By holding
the address lines of the MC4306/4006
constant, all data bits are routed to the
same location where they may be converted to parallel form again. By changing the
MC4306/4006 address inputs at the same
rate that data is being transmitted, each
data bit can be distributed to a different
location.

0
0
0
0
0

12
'3
'4
15
'6

,.,."

A

0

20
21
22
23
24
25
26
27
2.

00
01
02
03
04
05

2.

30
3'
32
33
34
35
36

0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0

,,
,,
,,
"' ,,
,,
,,
,,,
,
,,,
,
,,,
,,
,
" ,,
,,
,,

06
07

3.
3.
40
4'
42
43
44
45
46
47

48

4.
50
51
52

53
54
55
56

5.
5.
60
6'
62
63

Input

Output

B

A

C·

B'

0
0

0
0
0
0
0
0
0

0
0
0
0

0
0

0

,,
,
,, ,
,,
,, ,,
, ,
,, , ,
,,
,,
,,,
,, , ,,
,,, ,,,
,, ,, ,,
,, ,, ,,

0
0
0
0

0
0
0

0

0
0
0

0
0

0

0

0
0
0

0
0
0
0

0

0
0

0

0

0
0
0

0

0
0

0

0
0
0
0
0
0

0
0
0
0
0
0

0

0
0

,
,,,
,,,
,,,
,
,,,
,,

0

0
0

0
0
0

0
0

,
,,,
,
,,,

0

0
0
0
0

0
0
'0
0

,,,
,,
,,
1

A'

0

0
0

0
0

0
0

0
0

2

0
0

0
0

0
0

0

0
0

0

3

0

0
0

0

0
0

0

0

4

0

, ,
,, , ,,
,, ,, ,
, ,
,, , ,,
,, ,, ,
, ,
,, , ,,
,, ,, ,
, ,
,, , ,,
, ,
0
0
0
0

Device

,
,, , ,
,
,, ,
,, ,,
,, ,,
,, ,~
,, ,,
,, ,,
,, ,,
0

0
0

0

0
0

0

0

5

0

0
0
0
0

0
0

0
0

0

6

0

0

0

0
0
0
0

0
0

0
0

0
0

7

0
0

0
0
0

0
0

0

0
0

0

0

0

8

, , ,
0

FIGURE 3 - B·LlNE MULTIPLEXED TRANSMISSION SYSTEM

Serial
Input

MC3015

1/6 MC300e

aD
01
02
03
04

AS

Address {

06
07

ReSet 0--1---,
Serial
Output I

I
I

Logic

"'"

Clocko-+-----+_~---~-+__+---~--+_~-~-+_--~_+----------~

I

MC4306F ,l, MC4006F ,l,P (continued)

FIGURE 4 - DECODED DIVIDE-BY-FIVE COUNTER

TYPICAL APPLICATIONS
(continued)

(n addition to simply decoding the output state of a counter, the MC4306/4006
can be' used to make an ordinary binary
counter into an odd-modulus counter. For
example, three flip-flops and one MC4306/
4006 provide a completely decoded divide·
by-five counter as shown in Figure 4. The
4, output is used to set all the flip·flops
,to the 111 state so that the counter will
return to 000 on the next clocking edge.
The Enable input is used to prevent false
outputs due to rippling of the outputs
through intermed'iate states. Output 7 of
the MC4306/4006 is used for the fifth
counter output state.

•

MC4300/MC4000 series

DUAL BINARY TO
ONE-OF-FOUR LINE DECODER

MC4007L,P"

•

1/2 OF DEVICE SHOWN

4 (12) 00

3 (13) 01

2 (14) 02

x

(10) 6

1 (15) Q3

Y (9) 7

Vee
GND

~
~

This device converts two lines of input data to a
one-of-four output. The enable line provides an in·
hibit capability and also allows the decoder to be ex·
panded for larger decoder systems.
The dual 2-input!4-output decoder consists of
high-level and low-level gates internally connected for
minimum power consumption and maximum driving
capabilities. The enable gate must be in the low state
to perform the decode operation shown in the truth
table.
The propagation delays shown in the charts are
typical and vary according to loading, interconnection
wiring length, and the number of logic levels involved.

PIN 16
PIN 8

TRUTH TABLE

E=O
Number in parenthesis indicates pin number for other side.

Input Loading Factor: 1
Output Loading Factor = 10
Total Power Drssipation "" 125 mW typ/pkg

x

y

00

01

Q2

03

0

0

0

1

1

1

1

0

1

0

1

1

0

1

1

1

0

1

1

1

1

1

1

0

1 = High State
a = Low State

LOW-LEVEL GATE
Vee

TYPICAL TURN-ON DELAY TIMES (ns}
TA=25oC
Input

i

Applies only to
input gate.

HIGH-LEVEL GATE

X

00
11.5

01

02

03

15.5

11.5

15.5

Y

11.5

11·5

15.5

15.5

E

13.5

13.5

13.5

13.5

Vee

TYPICAL TURN-OFF DELAY TIMES (nsl
TA

"L suffix

P suffix

= 16-pin dual in-line ceramic package (Case 620L
= 16-Din in-line plastic Dackage ~----6
Vee
GND

=

Pin 14
1

Input Loading Factor'" 2

= Pin

Output Loading Factor"" 1 0

Positive Logic:

Total Power Dissipation

8 - 1020309010011012013
6 -405
wh.r. X @V = 0': • VI + (X • VI

= 150 mW typ!pkg

Propagation Delay Time = 15-30 ns typ

TYPICAL PROPAGATION DELAY TIMES
-;; FIGURE 1 - THREE-GATE DELAY versus TEMPERATURE
E
55

--I-'~OPF
I- ___
25pF

w

:.
;::

>

o
z

o

.....- .-;

,~+

Cl

25

-':t

-- --

a:

15
-75

-50

~

........

--

~

..«o
..

~

~/~

35

26

-_1-

:::--~

'pd+

....

~
........

:.

>

«
..J

25

50

1

22

II

w

o
z

o

;::
«.
(!l
«

.
o
.

100125

~o.

.......... J

14

-

'pd+

-50

-25

10
-75

TA. AMBIENT TEMPERATURE (oCI

o

40

:.

36

w

;::

>

'pd+ (3 Ga,.s)

«
..J

32

o
z

28

~
Cl

24

w

o

..«o
..a:

j.

20

~
VCC
TA

-

--

Fan-Out

--

=1

-r-

16

-

o

,.....

S
w

I

(1 G.,.),...-

,...-

30

60

. 'pd_ (1 Gate)
90

-o

'pd:,....-

-- -===-= _-1"-

'T-

25

50

75

100

125

120

CL. LOAD CAPACITANCE (pF)
*F suffix = TO-S6 ceramic flat pack.age'(Case 607).
L suffix = TO-11~ ceramic dUB.1 in-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 605).

150

40
36

>

«
..J

32

o

28

;::
«
(!l

24

z
o

~
a:

12

o

1

FIGURE 4 - DELAY varsusSUPPLY VOLTAGE

:.
0;::

w

'pd- (3 G~tes)

= 5.0 Vdc
= 25°C ~ _'pd+

",

--_..---'

-

I

.... ...
...- ..,./

T A. AM81ENT TEMPERATURE (OCI

FIGURE 3 - DELAY versus LOAD CAPACITANCE

S

--

tpd+

18

a:

75

~OPF

- - - - 25pF

;::

"0

o

-25

FIGURE 2 -ONE-GATE DELAY versus TEMPERATURE

w

I

45

:Iw

!

.

tpd+ (3 Gates)
1
'pd- (3 Ga,.s)

f--- CL = 25 pF

~TA

20

o

16

j.

12
4.5

= 25°C

'pd+ (1 Gate)
'pd_ (1 G.te)
5.0
VCC.SUPPLV VOLTAGE (VOLTS)

5.5

•

•

ELECTRICAL CHARACTERISTICS

S

n

Test procedures are shown for only one

~

input and one output. Test other inp!-Its

w

and output in the same manner. To com-.

o

pletetli'Sting. t~ all input-output combinations according to'the logic equation.

CO

-r

"T1

sn

~

o
o

1

2

CO

3
9

"T1

8

r-

10
11

"-g

12

)D

4

5

{
MC4308

-S5·e
+2S Q C

+125Oc

MC4000

Leakage Current
Breakdown Voltage

Clamp Voltage

Symbol

I

MC4308 Test Limits

Pin
Under
TeJt

'F

-

{

aGe
+25 oC

+76OC

IOL1

IOL2

16
16
16
16
16
16

18.4

18.4
18.4
17.6

17.6
17.6

oDc
I +25OC I +l25OC
I Max I Min I Max I Min I Max I Min I Max I Min I Max I Min I Max I Unit I lOLl IIOL21
I

-3.2

-3.2

80~

'R

-3.2

-3.2
80

80

-

80

5.5

BVin
Vo

lin

'OH
-1.6
-1.6
-1.6
1.6
-1.6
-1.6

-3.2
80

-

-3.2
80

mAd,
,.Ad,
Vd,
Vd,

0.4
0.'

Vd,
Vd,
Vd,

5.5
-1.5

-1.5

'D

1.0 -10

1.0 -10

-

MC4OO8 Tast Limits
I +25o C, I +7SoC

-55°C

Min

Volts

mA

"Tnt
Temp8f'ature

Charocteristic:
Input
Forward Current

8:J

TEST CURRENTNOLTAGE VALUES

6

V'L
1.1
1.1
0.8
1.1
1.1
0.9

V'H
2.0
1.8
1.8
2.0
1.8
1.8

VF

VR

VRH

0.4
0.4

2.4
2.4

0.4

2.4

0.4
0.4
0.4

2.5
2.5
2.5

4.0
4.0
4.0
4.0
4.0
4.0

Vmax

7.0

7.0

Vee

VCCL

VCCH

5.0
5.0
5.0
5.0
5.0
5.0

4.5
4.5
4.5
4.75

5.5

4.75

4.75

5.5
5.5
5.25
5.25
5.25

I

~.

:J

V,HX

s::
CD

-1

a.

2.4

2.4

TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:
1oH

I lin 110

V'L

V'H

I

VF

I VR I VRH I Vma• I Vee I VCCL I VCCH

V,HX

Gnd

,.,.
14

13

7,13
7,13

14

Output
Output VOltage

Short·Circuit Curnmt

Maximum Power
Supply Current

2.41

'se

ITotal Device)
'max,
'PO

0.4
0.'

0.4

~

Power ReqUirements

Power SuppJy Drain

0.'

VOL

-201 -65

,.
,.

2.4
-20

-s5

0.4
0.4
2.'
-20

-65

0.4
0.4
2.5
-20

-66

0.'
0.'
2.5
-20

2.5

-65

Turn.()ffOelav

-S5

mAd,

-

14
14
14
14

58

58

mAde

5,13

1.

45

45

mAde

5,13

-

46
23
.6
23

46
23
46
23

Switching Paramat.., ,

Tum-On De:Jay

-20

-

2,3,9,10,11,12,13
2,3,9,10,11,12,13
1.2,3,9,10,11,12,13
1,2.3,9,10,11,12,13

Pulseln

Pulse Out

1

8

7.8

1,2,3,4,7
9,10,11,12
1.2.3,4,7
9.10,11,12

I 14

- I - I ,.,.

,.

I 14

2,3,9,10,11,12

I

7,13
5.7

2,3,9,10,11,12
5.7

MC4308F,L, MC4008F,L,P (continued)

INPUT AND OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

FAMILY

MC4308
INPUT
LOADING
FACTOR

MC4308
OUTPUT
LOADING
FACTOR

MC4300
MC500
MC2100
MC3100
MC5400
MC930

1.0
1.2
0.8
0.8
1.0
1.0'

10
12
8
8
10
10

FAMILY

MC4008
INPUT
LOADING
FACTOR

MC4008
OUTPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

1.0
1.0
0.67
0.7
1.0
1.15·

10
10
6
8
10
12

*Applles only when mput Is bemg driven by MDTL gate With 2.0 kilohm pullup reSistor. LogiC "1" state drive limitations
of gates with 6.0 kilohm pulfup resistors reduce drive capability to fan-out of 3.

SWITCHING TIME TEST CIRCUIT
2.4 V

I

PULSE
GENERATOR

PRF

t+

1

= 1.0 MHz typ

PW= lOOns
0.5 ns

= t- = 5.5 ±

-=-

Coax·
13
8

950 ±. 1.0%

2
3
9

/TPout

10
11
12
4

1/4 MC3000
6
Load required only
on output being

5

tested.

CT = 25 pF = total parasitic capacitance, which includes probe, wiring, and toad

capacitances.

·The coax delays f(om input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 9S0-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT -070-50 or equ iva lent.

VOL TAGE WAVEFORMS

.-

t+

!r---,--- 2.6
1.0. V

V

.;c______~~::::::::::::::::::::::::::::::::::::::::~~::====~G»N~Do-n4V

•

MC4308F ,L, MC4008F ,L,P (continued)

m

FIGURE 5 - 20·BIT PARITY GENERATOR

•

r----------------,
MC4308/4008

APPLICATIONS INFORMATION

.--------+0 Logic "1"

81-<>...j...;..--...

9 r-<>,.,N-../
~

10'--"'-'-,,-........

~

11r-u...,-7t..._

Output A
Parity bit to be added
to original word to form

odd parity

Output B
Parity bit to be added
to original word to form
even parity

L

'-----1--0 Logic "0"
________________
~

A parity generation tree (simple
parity) for a 20·bit word is shown in
Figure 5. It uses two MC4308/4008
8-bit parity trees and one MC4310/
4010 dual 4-bit parity tree. If a parity
word containing odd parity is required
(i.e., the 20·bit word plus the parity bit
are to contain an odd number of"" s").
the direct output from the parity tree
(output A) is used as the parity bit. If
even parity is required, the extra Ex·
clusive·NOR gate in one MC4308/4008
provides the inversion when connected
as indicated for output B.

FIGURE 6 - 20·BIT PARITY DETECTOR

m

P':;ii:V I----_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-,---..,

r

a

MC4308/4008

2 '-"-'-,,-........

3r-u...,-7t..._
4 '-"-'-"............

5r-u...,-7t..._
6 '-"-'-u--....

7,.........,-7t..._

'E0

.

3:

~
N

8
9
10
11

Output A
"," output when odd
parity with no error

12
13
14
15
16

17
18
19

'-----1--0 Logic "0"
L ________________
~

A parity detection circu it for a 20·
bit word is shown in Figure 6. The
20·bit word is connected to a two·stage
parity tree identical to that used for
the 20·bit parity generator; however,
for the detection circuit the output of
the tree must be compared with the
input parity bit. The parity bit serves
as an input to the second stage of the
tree. For odd parity detection, output
A will be a logic "1" if no error has
occurred. For even parity detection, a
logic "1" will appear at output B if no
error has been introduced. Longer word
lengths can be examined in a similar
manner.

MC4300/MC4000 series

DUAL 4-BIT PARITY TREE

MC4010L, P *

ADVANCE INFORMATION/NEW PRODUCT

1~

2

H

:

Three Exclusive NOR gates are connected together to
form each of the two 4·bit parity trees in the package. An
even number of logic ",.' states on the inputs will result in
a logic "," output state. An odd parity checker can be made
by connecting an inverter to the output of the device.
This function is constructed using low and high·level
Exclusive NOR gates connected as shown in the logic
diagram to maximize output drive capability and minimize
power dissipation.

6

L

9~

10
12

L

13

L

H

8

Vee· PIN 14
GNO = PIN 7

Positive Logic:
6=1020405
where X

<:> y =X .'7+ X' Y

Input Loading Factor'" 2
Output Loading Factor = 10

Total Power Dissipation = 125 mW typ/pkg
Propagation Delay Time = 9.5 to 22 ns typ

LOW·LEVEL GATE

HIGH·LEVEL GATE

Vee

Vee
4k

4k

4k

4k

4k

2k

:t:APPlies only to Input gate .

• L suffix = TO~116 ceramic dualln~line package (Case 632).
P suffix =- TO-116 plastic dual In-line package (Case 605),

I

{"om:;;;:::;

4k

I

MC4010L, P (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

I

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MCS30

1.0
1.0
0.67
0.7
1.0
1.15""

10
10
6
S
10
12

Note: Differences in MC4000 series loading factors result from
differences in specifications for each family.
"" Applies onlv when input is being driven by MDTL gate with
2.0 k ohm pullup resistor. Logic "1" state drive limitations of
gates with 6.0 k ohm pullup resistors reduca drive capability
to fan·out of 3.

DC ELECTRICAL CHARACTERISTICS
(TA

Characteristic

=0 to 750 CI

Symbol

Value

IFI

-3.2 mAde max

IF2

-2.S mAdc max

Yin = 0.4 Vdc, VCC = 4.75 Vdc

IR

SOllAde max

Yin = 2.5 Vde, VCC = 5.25 Vde

Conditions

Input
Forward Current
Leakage Current
Breakd.own Voltaga
Clamp Voltage
Threshold Voltage

Yin = 0.4 Vdc, V CC = 5.25 Vdc

BVin

5.5 Vde max

lin = 1.0 mAde, Vce= 5.25 Vde, TA = 250 e

VD

-1.5 Vde max

10 - -10 mAde, Vee - 4.75 Vde, TA = 25°C

Vth "1"

2.0Vde

Vth "0"

I.SVde

TA -ooe
TA = +250 C, orTA = +750 C

1.1 Vde

TA = oOe, or TA = +250 e

0.9 Vde

TA=+750e

Output
OutPUt Voltags

Short-Circuit Current

VOL

0.4 Vde max

IOL = 16 mAde, Vee = 4.75 Vdet

0.4 Vdemax

IOL = 17.6 mAde, Vee = 5.25 Vdet

VOH

2.5 Vdc min

Ise

-20 to -65 mAde

IOH = -1.6 mAde, Vee = 4.75 Vdet
Vee - 5.0 Vde, output groundedt

tThese tests are performed according to the logic equations with a true input equal to Vth "1" and a false input
equal to V th "0".

MC4300/MC4000 series

4-BIT SHIFT REGISTER

MC4012L,P*

This 4-bit register provides parallei or serial data entry and retrieval, determined by the logic state of the mode control
input_ For parallel operation, set the mode control to the logic "1" state and strobe the information at the Dp inputs into the
register. Serial left-shift operation is achieved in this mode by connecting the Q outputs to the Dp inputs of the previous stage_
For serial right-shift operation, set the mode control to logic "0" and clock data into the register from DS.

Strobe 13

o----f----.,

Clock 12

o-j---f----.,

Os

QO

Ql

Q2

Q3

10

9

6

4

2

Mode COntrol 1

11

Vee"" Pin 14
GNO == Pin 7

3
°p3

°PO
Input Loading Factor:

Mode Control = 5

Propagation Oelay Time == 25 ns typ/bit
'tsetup "0" (Mode Control) == 25 ns typ
t setvp "1" (Mode Control) = 12 ns typ
tsetup "0" (OPO; DS) = 4.0 ns typ

Other Jnputs == 1

o.utput Loading Factor = 10
Total Power DISSipation

= 180 mW

typ/pkg

tsetup "'" (OPO. OS) - 3.0 ns typ

INPUT GATING

thold "0"
thold "1"
thold "0"
thold'''1''
fT09 = 35

(Mode Control)
5.0"1 tvp
(Mode Control) , 9.0"s tvp
(OPO. OS) = 7.0 ns typ
(OPO, DS) = 11 ns typ
MHz typ @ 25°C

TYPICAL FLIP-FLOP

r----~---~~----~~------~;_--~------~----~------_r---<> Z2

~

B2

7

~~ ZI

BO

Bl

}-

0
0
0
0
0
0
0
0

Y
}-

J)J

}-

~
Vee
GND

Input Loading Factor = 2
Output Loading Factor = 10
Total Power Dissipation = 250 mW typ/pk~
Propagation Oelay Time = 20 ns typ

= Pin 16
=:;

Pin

8

~
~

This is advance information on a new introduction and specifieations are subject to c!'lange ~ithou:t notice.
*p suffix

= l6-pin dual in-line plastic package (Case 612).

*4

;:c

;,.4S#

,

•

MC4300/MC4000 series
4-BIT UNIVERSAL COUNTER

MC4023F,L,P*

•

ADVANCE INFORMATION/NEW PRODUCT

513_
01

e2

02

81_
e3

Q3

612_
J4

04

9

This device is a 4-bit counter with internally
connected feedback. Inputs and outputs can be
connected to count to any number between two
and twelve except seven and eleven. Reset inputs
are provided on each flip-flop to allow direct
setting of the Q outputs to zero any time during
the counting cycle_
Each flip-flop in the counter is built from
high and low-level gates as shown by the logic
diagram_ The flip-flops and the feedback inverter
are connected as shown by the block diagram
to provide minimum power dissipation and
maximum drive capability_
LOW-LEVEL GATE

Vee

Vee = Pin 14
GND=Pin

7
4k

Input Loading Factor:

J= 1
<:1, <:3 = 2
<:2, R - 3
Output Loading Factor"" 1 0

Total Power Dissipation

= 200

2k

mW typ/pkg

Propagation Delay Time = 16 ns typ/bit
Operating Frequency = 30 MHz typ
·Oiode used only when input Is connected

to external point.

LOGIC DIAGRAM

HIGH-LEVEL GATE

One flip-flop shown. Only inputs shown on block
diagram are present.

Vee
4k

*F suffix"'" TO-S6 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 605).

1_2 k

100

MC4023F, L, P (continued)

INPUT LOADING and OUTPUT DRIVING FACTORS
with respect to MTTL and MDTL families

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
DRIVE
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

1.0
1.0
0.67
0.7
1.0
1.15"

10
10
6
8
10
12

I

Note: Differences in MC4000 series loading factors result from
differences in specifications for each family

•• Applies only when input is being driven by MDTL gate with
2.0 k ohm pullup resistor. Logic "I" state drive limitations of
gates with 6.0 k ohm pullup resistors reduce drive capability
"to fan~out of 3.

DC ELECTRICAL CHARACTERISTICS
ITA = 0 to 75°C)

Characteristic

Symbol

Value

IFI

-1.6 mAde max

Conditions

Input
Forward Current - J
Cl,C3

-3.2 mAde max

C2,R

-4.8 mAde max

J

IF2

-1.4 mAde max

Cl,C3

-2.S mAde max

C2,R

-4.2 mAde max

Leakage Current - J

IR

SO "Ade max

C2,R

120"Ade max

Breakdown Voltage

Threshold Voltage

Vin = 0.4 Vde; VCC = 4.75 Vdc

40 "Ade max

Cl,C3

Clamp Voltage

Vin = 0.4 Vde, VCC = 5.25 Vde

Vin = 2.5 Vde, VCC = 5.25 Vde

BVin

5.5 Vde max

lin = 1.0 mAde, VCC = 5.25 Vdc, TA = 25°C

VD

-1.5 Vde max

10 = -10 mAde, VCC = 4.75 Vde, TA = 25°C

Vth ","
Vth "0"

2.0 Vde

TA = DoC

1.8 Vde

TA = +250 C, orTA = 75°C

1.1 Vde

TA = DoC, orTA = +250 C

0.9 Vde

TA = +750 C

Output
Output Voltage

VOL

VOH
Short·Circuit Current

ISC

0.4 Vde max

IOL = 16 mAde, VCC = 4.75 Vde

0.4 Vde max

IOL = 17.6 mAde, VCC = 5.25 Vde

2.5 Vde max
-20 to -65 mAde

IOH = -1.6 mAde, VCC = 4.i5 Vde
V out = 0 Vde, VCC =5.0 Vde

MC4023F, L, P (continued)

SE~UENCES

COUNTING

•

Ql

513_
C2

Q2

8

6

12

J4

Q3

Q4

DIVIDE BY 3

9

DIVIDE BY4

(;2

Q2

Q4

Cl

Ql

Q3

0

0

0

0

1
2

1

0
0
1

1
2
3

0
0

0

0

DIVIDE BY6

DIVIDE BY 12

Ql

Q2

Q4

C3

Q3

Ql

Q2

0
1

0
1
0
1
0
1

0
0
1
1
0
0

0
0
0
0
1
1

0

0
1
0
1

0

0
0

0

1
1

0

0
0

1
1
1
1
0

0
0
0

5

1
2
3
4

applied to C2; the output is taken from Q4.

5
6
7
8
9

DIVIDE BY 4:

Use flip-flops 1 and 3; connect 01 to C3.

10

Apply the input signal to
In addition to the connection for divide by 3, connect 01 to C2.
ApplV the input signal to Ct.

11

DIVIOE BY 6:

DIVIDE BY 2:

Use flip-flop lor 3.

DIVIDE BY 3:

Use flip-flops 2 and 4, connected as shown. The input signal is

ct.

DIVIDE BY 12: In addition to the connections for divide by 6, connect 03 to

513_
C2

Q2

8 1_
C3

Q3

612_

J4

Q4

ct.

DIVIDE BY5

9

DIVI DE BY 8:

0

1

1
1

0

1
0

0
0

1
0
1

1
1

0

0
0

0

Cl

8

Ql

C2

Q2

6

DIVIDE BY 10
Q4

Cl

Ql

Q2

Q3

Q4

0
1

0
1

0
0

0

0

0

0

1

2
3
4

0

0
0
0
1

1
0

0
0

1
1
0
0

0
0
1
1

1
1
0
0

0
0

0
0
0
0
0
0
0
0
1
1

1

1
1

0

0

<:1

Ql

Q2

Q3

0
1

0

0

0

1
0
1

0

0

1

0
0

0

1

0
0
0
1
1
1

1

1

1

5
6
7

C3

Q3

9

12

J4

Q4

1
1

2
3
4

5
6
7
8
9

1
0
1
0

1
0
1

DIVIDE BY 10:

0

1
1

In addition to

the connections for divide by 5,
connect Q 1 to C2. Apply the input signal to

C1.

C2

Q2

Q3

Ql

0

0

0

0

0

1

1
0
1

0

0
0
0

0

0
0

0
0
0
0
0
0
0

2
3
4

5
6
7

a
DIVIDE BY 9:

11

R4

1
1
1
1

Q3

Connect flip-flops 2 and 3 as shown for divide by 5, but do not connect 03 to j4.
Connect a 1 to C2. The input signal is applied to C1; the output is taken from 03.

5 13

0
0
0

Q2

DIVIDE BY 9
2

0

C2

2
3
4
Connect flip-flops 2,3, and 4 as shown. The input
signal Is applied to <:2; the output is taken from Q4.

0

Q4

Apply the input signal to C3.

DIVIDE BY8

DIVIDE BY 5:

1
1

1

Cl

2
3
4

Ql

1

1
0

1
0

1
1

1
1,
0

1
1
1
1
0

Q4

1

The input signal is applied to C2;
the output is taken from 04.

DUAL
VOL TAGE-CONTROLLED
MULTIVIBRATOR

MC4300/MC4000 series

MC4324F,L*
MC4024F, L, P*

4

-iE

The MC4324/4024 voltage-controlled multivibrator
provides appropriate level shifting to produce an output compatible with MTTL logic levels. Frequency
control is accomplished through the use of voltagevariable current sources which control the slew rate
of a single capacitor. Variation of the output frequency
over a 3.5 to 1 range is possible with an' input dc con·
trol voltage of +1.0 to +5.0 volts.
Voltage·controlled multivibrators are used in phase·
locked loops for digital frequency control. they may
also be used for some types of A to D converters.

3

2

6

12

8

Vcc: VCM = 1. 13
Output Buffer

= 14

GND: VCM = 5. 9
Output Buffer = 7
External Capacitor for
Frequency Range Determination
Output Loading

~actor

Power Dissipation

= 7

= 150. mW typ/pkg

Maximum Operating Frequency

= 30

MHz typ

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN
(Numbers in bracketS are pin numbers for other half.)
4110)
3111)
----------1~---------- X2

Xl

[13] lO-____

~~_+~----------~---c-cfP-n-tr~o-I----~~--~--4r------------,

VCC
(VCM)

,-------"""'"1[014
VCC

2570

(Output

Buffed
4k

1.4k

100

560
Control
Input

750

6 [8)

560

304

560

[9)

5~----~-------------4--+-----~----------~--~--~~~~

GND
(VCM)

"F suffix

= TO-S6 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P'suffix = TO-116 plastic dual in-line package (Case 605).

GND
(Output Buffer)

•

ELECTRICAL CHARACTERISTICS

2

~
VCM

•

e
N

6

~

rnA

Pin
Symbol

Test

Min

Max

Min

Max

lin

2
12

-

40
40

-

40
40

6

-

0.4

-

0.4

IOL2

IOH

VIH

VCC

VCCL

VCCH

11.2

-1.6

5.0

5.0

4.5

5.5

+250 C

9.8

11.2

-1.6

5.0

5.0

4.5

5.5

+1Z::~

9.8

11.2

-1.6

5.0

5.0

4.5

5.5

9.8

11.2

-1.6

5.0

5.0

4.75

5.25

+2SoC

9.8

11.2

-1.6

5.0

5.0

4.75

5.25

+7SoC

9.8

11.2

-1.6

5.0

5.0

4.75

5.25

{
MC4024
MC4024 Test Limits

OoC

+2SoC

Volts

@Tast
Temperature IOL1
{ ~50C 9.8
MC4324

11

MC4324 Test Limits
_55°C
+2SoC
+12SoC

Under

Characteristic

-It

on
!""
S

TEST CURRENTNOL TAGE VALUES

"fr'
10

(")

~

C

~
r.."

"

~

TEST CURRENTNOL TAGE APPLlEO TO PINS LISTEO BELOW,
.~

+7SoC

Max

Min

Max

Min

Max

Min

Max

Unit

IOL1

IOL2

IOH

VIH

VCC

VCCL

VCCH

Gild

-

40
40

-

40

-

-

40
40

,t.tAdc

40

40
40

,t.tAdc

-

-

-

2
12

-

-

14
14

5,7,9
5.7,9

-

0.4

-

0.4

-

0.4

-

0.4

Vdc

6
8

-

-

5.7,9

2.5
2.5
-40
-40

-

Vdc
Vdc

6
8

2
12

-

1.4,14
10,13,14

6
8

2
12
2
12

-

-100
-100

mAde
mAde

-

-

-

2
12

1,3,14
11,13,14

Min

Input

Forward Current

VOL

VOH

I

6
8

2.4
2.4

ISC

I

IpO

11,3,14'-

6
8

+
-

2.4
2.4

1-40 1-100 -40
-40 -100 -40

+
-

-

2.4
2.4

-100 -40
-100 -40

+
-

2.5
2.5
-100 -40
-100 -40

-

.+
-100
-100

2.5
2.5
-40
-40

+

-

-100
-100

~ ~

-

-

-

-

1,4,14
10,13,14

1,3,14
11,13,14

-

-

-

+

5,7,9
5,7,9
5,6,7,9
5,7,8,9

Power Requirements
(Total Device)
Power Supply Drain

8:::J

!:!".
:::J

c:

CD

Output
Output Voltage

Short-Circuit Current

s

(")

37

mAde

37

2.4,10,121

1,13,14

5,7,9

AC TEST CIRCUIT AND WAVEFORMS

TP out

GND

Coax shall be CT-070-50 or equivalent.
CT

= 25 pF

"" total parasitic capacitance, wh ich

includes probe, wiring, and load capacitances.

Co

MC4324F,L, MC4024F,L,P (continued)

AC TEST LIMITS

TEST

SYMBOL

Maximum Operating Frequency

f max

Ratio of Frequency of
Oscillation over Specified
Input Voltage Range

25 MHz

Ccontrol = 100pF, Vin high = 5.0 Vdc,
Vin low = 1.0 Vdc

3.5:1.0

FIGURE 1 -INPUT VOLTAGE versus OUTPUT FREQUENCY
(15 pF FEEDBACK CAPACITOR)
5.5

The operating frequency range of this multivibrator is controlled
by the value of an external capacitor that is connected between X 1

and X2. Either of the two equations shown below may be used to
define the value of Ccontrol:

).IF,

or

Ccontrol

= --

5.0

I..J

0

<1:

I-

is typically 30 MHz.

Three power supply and three ground connections are provided
in this circuit. Each multivibrator has a separate power supply and

ground connection. The output buffers have a common power
supply and ground pin. This provides isolation between VCM's
and minimizes the effect of output buffer transients on the multivibrators in critical applications. This separation of power supply
and ground lines also provides the capability of disabling one VCM
by disconnecting its Vee pin. All grounds must always be connected to insure substrate grounding and proper isolation.
The output buffer transforms the logic levels of the VCM to
MTTL logic levels.

FIGURE 2 - INPUT VOLTAGE versus OUTPUT FREQUENCY
(100 pF FEEDBACK CAPACITOR)
VCC

~

+1~50J V Al
T~~
Y

5.0 Vdc

5.0

-

u;
..J

o

4.0

>
<1:

I-

55 O C

::>

2.0

Q.

~

-

i:

>-

1.0

o

o

1-

I-

-55°C,

IJ
l

0

I-

::>
Q.

z

2.0

~

o
4.0

5.0

f out , OUTPUT FREQUENCY (MHz)

6.0

30

+125 0 C

--

~

K.,~

"">~V'"t---550 C

r---+250C

1.0

o
3.0

25

r- f--+1250C

i:

;;

1.0

~~

VI V

3.0

>

2.0

20

+25 0 C

1

4.0

w

<1:

Q.

15

I I I

Cl

o

2.0

10

5.0 I--- VCC = 5.0 Vdc

~

J

1.0

5.0

FIGURE 3 -INPUT VOLTAGE versus OUTPUT FREQUENCY
(430 pF FEEDBACK CAPACITOR)

..J

o

+250 C

f out , OUTPUT FREQUENCY (MHz)

0

>
::>

~
~ -+1250 C
~

>
I-

..J

f/\+25 C

~+250CI

0

u;

..J

I-

3.0

/V.
.....

:::;--

I-

""':V"+1250 C
3.0

-55°C

/ L K-5~OC

..J

f--

-55°C

w
Cl

4.0

5.5

+25 0 C

I-

~~

U;

Cl

with f given in Hz. The maximum operating frequency of th is device

+125 0 C .....

1-

w

).IF,

1min

5.5

I I I

-vcc = 5.0 Vdc

~

100

500

= f max

Min

Ccontrol = 10 pF, Vin = 5.0 Vdc
Frequency Ratio = 3.5:1

OPERATING CHARACTERISTICS

Ccontrol

•

LIMITS

CONDITIONS

o

0,2

0.4

0.6

0.8

1.0

f out , OUTPUT FREQUENCY (MHz)

1.2

MC4324F,L, MC4024F,L,P (continued)

The basic frequency synthesizer loop shown in Figure 4
consists of five basic components: the reference oscillator,
the phase detector, the low-pass filter, the voltage controlled
multivibrator/oscillator, and the divide by N counter.
This loop achieves a stable state when fVCM = N fref.
When this condition does not exist the VCM searches
through its frequency spectrum until it finds the frequency
at which the stable state occurs. At this point the loop
locks. This system allows the generation of many discrete
frequencies from a single, highly stable source (fref). A
system such as this has many useful applications in com·
munications (frequency control systems) ,computer systems
(for synchronizing data tracks and clocking systems), in
instruments (frequency synthesizers and counters) and
filter networks.
In addition to its function in. the phase'locked loop, the
VCM may be used as a fixed oscillator (plug crystal into
capacitor pins and ground control input), in simple A to D
converter systems, and as an FM modulator.

•
APPLICATIONS INFORMATION

FIGURE 4 - PHASE·LOCKED, FREQUENCY SYNTHESIZER LOOP

Reference
Oscillator

Voltage~

Phase

Controlled
Multivibrator
MC4324/4024

Detector
MC4344/4044

fVCM

7N

N

Progl."ammable
Counter

MC4316/4016
MC4318/4018

fVCM

~~____________M
__C_43_0_0_I_M_C_4_00_0_~
__ri_es__~

FULL ADDERS

MC4326F, L • MC4327F, L*
MC4026F, L, P • MC4027F, L, P*
These full adders are designed for serial and ripple-carry
parallel adder systems. True Sum and Carry are produced at
the output from the input information. A separate 3-input
NAND gate is provided on the monolithic chip to provide the
inverted Su m or Carry output.

5
A 8
B 9

TRUTH TABLE
Input Pins
Output Pins
2
5
7
8
9
A
B
SUM
Cout
Cin
11-------------,
12--------

0
0
0
0

~--------6

13------------~

VCC = Pin 4
GND = Pin 10

Input Loading Factor:
A, B = 2
e, n • Pins 11, 12, 13

=1

Output Loading Factor:
MC4326 = 15 MTTL
MC4327 = 7 MTTL
MC4026 = 12 MTTL
MC4027 = 6 MTTL

1
1
1
1
I
I
I
I

Loads
Loads
Loads
Loads

,

0

0

{}

1

1
1

0

1

1

0

1

0
0

0

1

0

1

1
1

0

0
0

1

1

1
1
1

0

Total Power Dissipation
Add Delay = 25 ns typ
Carry Delay = 13 ns typ

0
0
0

= 90 mW typ!pkg

CIRCUIT SCHEMATIC
VCC
4

4.5 k

4.5 k

4.5 k

4.5 k
C out
~~----------+-~7

5.6 k

6

11

120---+4
130---+-+--+

= TO-B6 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-1 16 Plastic dUal· in-line packaGe (Case 605).

*F suffix

•

II
S
n
t)

ELECTRICAL CHARACTERISTICS
Test procedures are shown for inputs A and

Cin. Other inputs are tested in the same
manner. Output tests should be completed
according to the truth table.

N

0)

"T1

~

r

s

~
W

N
......

TEST CURRENT!VOlTAGE VAlUES
rnA
@ T.s'

Temperature
Cin
2
11
12
13

MC4326*, MC4327

D~--

6
M(4026*, MC4027

I
I

-ssoc

lOt

Symbol

~

,r-

100

Pr*

Std

Pr·

Std

lin

21..

1.0

2.0

VII.

V1H

V.

Vth1

VthO

VOUI

0.45

0.9

5.5

VrM•

Vee

8.0

5.0

20

10

-2.2

-1.2

2.8

4.5

a.o

+25°C

20

10

-2.2

-1.2

0.45

2.8

4.5

1.7

1.0

5.5

+12SoC

20

-2.2

-1.2

0.45

2.8

4.5

1.4

0.8

5.5

5.0

ooe

to

20

10

-2.2

-1.2

0.45

3.0

4.5

1.9

1.0

5.5

5.0

+2S oC

20

10

-2.2

-1.2

0.45

3.0

4.5

1.8

1.0

5.5

+75°C

20

10

-2.2

-1.2

0.45

3.0

4.5

1.7

1.0

5.5

Pin
Under
Characteristic

"T1

Volts

1.0

2.0

5,0

7.0

S
n
~
~

5.0

5.0

:n

TEST CURRENT!VOLTAGE APPLIED TO PINS lISTEO BELOW,

I Test I Min I Max I Min I Max I Min I ,Max I Min I Max I Min I Max I Min I Max I

Un~

lOt

10H

1m

I 21,. I V" I V,H

V.

V"'l

I

VthO

V...

V_.

Vee

Gnd

I""",
Forward Current

'F

-1.33 [

[-1.33

-1.33

-1.~[

[-l.~

-1.661 mAde

8,9,11,12,13

2,10

-2.66

-2.66

-3_~

-3.~

-3.321 mAdc

2,9,11,12,13

8,10

-2.66
Leakage Current

1ft

Inverse Beta Current

'L

Breakdown Voltage

0.1

I

-

10.1

0.1

0.1

0.1

0.1 I mAdc

8,9,10,11,12,13

0.2

I

-

2.9,10,11,12,13

10.2

0.2

0.1

0.1

0.1

0.2
0.1

0.2
0.1

0.2 I mAdc
0.1 I mAdc

0.2

0.2

0.2

0.2

0.2

0.2 I mAdc

BV in

10
10

5.5

5.5

Vd,

~

~

8,9,10,11,12,13

~

2,9,10,1"1,12,13

10

Vout "1"
Leakage Current

0.45

Voot "0"
2.5

Isc

Output Voltage

VOL
VOH

-

I -

-25

I 0.45 1 -

I 2.4 I

0.25 I

IOLK

Short-Circuit Current

I

I 0,45 I

I 2.5 I

I 0.45 1 -

1 0.45 I Vdc

2.8

3.1

3.15

I 0.4

3.0

I -

I 0.25 I

-

-

I

Vdc

2,8,9

10

8,9

10

5,10

I 0.45 I -

-

-

I 2.5 I

2,8,9

-

I 0.25 I

-

I -100 I -25 I -100 I -25 I -100 I -25 I -100 I -25 1 '-100 I -25 I -100 I mAde
I

I 0.25 J -

I 0.45 I

I 2.4 I

10

I 0.4

-

-

I 2.5 1 -

2,8,9

I -

I 0.25 I

-

I 0.25 I mAdc

0.4

-

..

I 0.4 I - I 0.45 I

Vdc

3.15

Vd,

3.1

10

2,8,9
2,8,9

10

Power Requirements
(T..al Oevice)
Mludmum' Power
Supply Current
Power SUpply Drain

'm~
',.DR
IpDL

"'Prime Fan-Out

38

mAd,

47

27

27

27

35

35

35

I mAde

32

32

32

41

41

41

I mAde

s

~

o
......

N

~"T1

r-

~

10

O"'put
Output Voltage

r,""0

2,8,9,10,11,12,13
10

2,8,9,10,11,12,13

8::s

...5'

s::

~

MC4326F,L, MC4327F,L, MC4026F,L,P, MC4027F,L,P (continued)

•

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
Coax·

Coax·

2.5 k
950
±1.0%

50

PRF = 2.0 MHz
Zin = 500hms

CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.
-ni. coax delays from input to scope and output to scope must be matched.
The scope 'must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuatar probe.

Coax shall be CT -070-50 or equivalent.

Jc------------,~i::?__ni:;_---3.0

X

TPin

=

V

GND

= = +_ _ _ _ _ _ _ _--'-f2=====0.4V
~----

200

ns------.,

---~~+==============+==~~~--GND

=====~+_--------~=====GND

SWITCHING TIME TEST PROCEDURES

(Lettars shown in test columns refer to waveforms.)
INPUT PIN

PINS
TEST

tpd+

LIMITS

8

9

lin/Out)

A

B

9/5
9/5

Open

X

Open

Open

Open

Z

Open

X

Open

Open

Open

Z

3.0 V
3.0 V

3.0 V
3.0 V

Open

Open

Z

Open

Open

Z

11

12

13

5

6

SUM

tpdtpd+

11/6

Open

Open

X

tpd-

11/6

Open

Open

tpd+

8.9/7

X

X

X
Open

tpd_
t+

8.917

X

X

Open

t-

OUTPUT PIN

UNDER
TEST

Tested during each of the above tests.

7
Cout

-

-

y
y

ns
max
35
35
20
20
20
20
8.0
5.0

~_______________M_C_4_3_0~O~/_M_C_4_0_00__~_r_ie_s~1

ADDERS

MC4328F, L thru MC4331F, L*
MC4028F,L,P thru MC4031F,L,P*

•

This family of fast adders is designed for use in
parallel look-ahead carry adder applications where
high-speed addition is requirad. The dependentcarry fast adders have a Carry output that is dependent upon the two input bits for that stage
plus the Carry input from all previous stages. The
Carry output from the MC4330/31 is independent
of the carry from the previous stages.

CONDENSED TRUTH TABLE FOR THE Nth STAGE
11

12,13

Cin1(n-1)

Note 1

Pin Numbers
13,14.1
5
MC4330{4030
MC4331/4031

Note 2

Sum

(El,ut

Cout

MC4328/4028
MC4329J4029 Comment
Cout
Note 3

"

""
Input Loading Factor:
<±lln1. A. B~2

<±>in2. Cin1, Cin2. Cin3 = 1

Output Loading Factor:
MC4330 ~ 15 MTTL I Loads
MC4331 ~ 7 MTTL I Loads
MC4030 ~ 12 MTTL I Loads
MC4031 ~ 6 MTTL I Loads

MC4328,
MC4329,
MC4028,
MC4029,

Total Power Dissipation = 125 mW typ/pkg
Add Delay == 25 ns typ
Carry Delay
Note 1. This column represents the AND function whose inputs ere pins 13 and 12, and Is defined by the
expression (A n_,@Sn_1)(Cl n [n-2})'
Note 2. This column represents the AND 'functIon whose inputs are pins 13, 14, and 1, and i5 defined by the
expression (A n _1 G:) B n -l){A n-2 @Bn_2)(Cn_31.
Note 3, q, '" Don't Care. The "Don't Care" occurs for the MC4330-31/4030-31 only, because the C n and the@n
from anyone previous stage entering a given subsequent stage cannot be simultaneously at logic "1"

DEPENDENT-CARRY FAST ADDER
MC4328/4028, MC4329/4029
<±lln2

1

<±lln1 13

INDEPENDENT-CARRY FAST ADDER
MC433014030, MC4331/4031

-----------,
I

Cin3 14

--r-r---<-_/

= 13 ns typ

j---------- --,

<±lin2

I

I I
I
I

Cin3 14
<±lin 1 13

1
I

C in2 12 - - - ' - L . . _ /

Cln2 12

C in1

11

Xl

3

X2

2--~-----~

Cln1
X1
X2

A
B

8 ---'---'-'
9
>r"--~~

--+--------'

I
I

11

I

3

I

2

- - - - - - - - - __ I

A

8---'--..-----):>-_ _ _ _ _--\

B

9

7 C out

~;-,--"1-~

I
I

IL __
r---

;>O-+-r- 6

I.

I
<±l out

I

.:>0---+-+-6

<±lout

I

1
1

I
1 _____________
III JI
L
VCC~PIN4

GND

~

PIN 10

• F suffix = TO-86 ceramic flat package (Case 607).
L. suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 606).

I
1
I

IL

:>O-i-+-5 SUM
_ _ _ _ _ _ _ _ _ _ 1\1
_ .J.I
VCC ~ PIN 4
GND

~

PIN 10

MC4328F,L thru MC4331F,L, MC4028F,L,P thru MC4031F,L,P (continued)

CIRCUIT SCHEMATIC

•

Xl

(f);n2
C in3

14

(f);nl

13

C in2

12

C in1

11

X2

A

8

t-rl-+-07

Cout

t-.....---+---<> 5

SUM

o-+--.--+-+--I'

I
1.2k
I .
L
____________

~

__ =----1I

10
GND

o

Connection shown by dashed line u~ed
only on dependent-carry devices.
.

•

ELECTRICAL CHARACTERISTICS

s:
C')
oI:lo

I nput test procedures are shown for only

w

inputS(t)in2 and A. Other inputsare tested

~

in the same manner. Output tests should be
completed according to the truth table.

·"rr+

...

::T
C

TEST CURRENT!VOlTAGE VALUES

mA
@ Test
Temperature
-SSoC
MC432S', MC4329
0
MC4330. MC4331
+25 C

!

+125°C

I

MC4028*, MC4029I

DOC

MC4030., MC4031

+2S:C

+75 C

10<

s:

Volts

C')

I""

Pr*

Std

Pr*

S1d

20

10

-2.2

-1.2

20
20

10
10

-2.2
-2.2

-1.2
-1.2

20
20
20

10
10
10

-2.2
-2.2
-2.2

-1.2
-1.2
-1.2

lin
1.0

1.0

V1L

VIH

VI

Vth1

0.45
0.45
0.45
0.45
0.45
0.45

Vtho

VOUI

2.8

4.5

2.8
2.8

4.5
4.5

2.0

0.9

5.5

1.7
1.4

1.0
0.8

5.5
5.5

3.0
3.0
3.0

4.5
4.5
4.5

1.9
1.8
1.7

1.0
1.0
1.0

5.5
5.5
5.5

Vm.x

Yee

8.0

5.0
5.0

f)

5.0

W

~

·r-"

5.0
7.0

5.0
5.0

s:

U~~r-~~~~~~~~~-1--crc~~~~~~~~~--i------.------~~~~~~~::~~~~::~-----r----'-~
Characteristic

Symbol

I Test

Leakage Current

Inverse Beta Current

IF

IR

-1.33

-1.33

-2.66

-2.66

-2.66

0.1

0.1

0.1

0.1

0.2

0.2

0.2

0.2

0.1

0.1

0.1

I 0.2

0.2

0.2

0.1

IL

-1."1 1-1.·61

-1.33

0;2
BreakdoWn Voltage

[

BV in

-

-3.32

-3.32

I

I

-

-

[

0.1 I

-

I-I."

mAd'

8,9,11,12,13,14

1,10

-3.32

mAdc

1,9,11,12,13,14

8,10

I

0.1

mAde

8,9,10,11,12,13,14

0.2

0.2 I mAde

1.9,10.11,12.13,14

0.1

0.1 1 mAde

I 0.2

0.2 I mAde

5.5

5.5

Vd,

~

~

~

10
10
8,9,10,11,12,13,14
10,12,14
1,9,10,11,12,13;14
10,12,14

Output
OutpJ.t Voltage

0.45 I

Vout "0"
Vout "1"

Leakage Current

2.5

I

ISC

Output Voltage

VOL
V aH

I

-

10.45

-100

I

-

-25

0.4

0.4
2.7

2.5

2.5
0.25

5** I -25 I -100 1-25

I 3.1 I

0.45

0.45

2.4

0.25

IOLK

Short-Circuit Current

13.15 I

I -

I 0.45

0.45 I Vde
2.5

2.4

I

-

1

Vdc

I .. I 0.25 I mAde

0.25

0.25

0.25

-100 1-25

-100 I -25

-100 I -25 I -100 I mAde

0.45

0.4

0.4

-

I 2.8

3.1 I

-

I

-

I 0.45 I

13.15 I

Vde

-

I Vde

_

I mAde

',9

11,13

',9

11,13

65 I

lmax

Power Supply Drain

IpDH

321-1321-1321-141

JpDL

38

55

I

-

I

38

I

-

I

38

I -

I 48

-

I

41

I

-

I

41

I mAde

48

J

-

I

48

I mAde

r+

...::T
C
s:

~

10

~

5,10
8,9

10

11,1318,9

10

w

·"-c"r8;:,

(Total Device)
Maximum Power
Supply Current

"

r"-c

c

8,10

11,131

00

10

Power Requirements

.Prime Fan-Out
UShort one output at a time.

~

C

N

Il11ut
Forward Current

C')
Gnd

a, 9, 10, 11,13
10
8,9,10,11,13

....

:5'

c
~

MC4328F,L thru MC4331F,L, MC4028F,L,P thru MC4031F,L,P (continued)
SWI TCHI NG TIME TEST CI RCUIT AND WAVEFORMS

VCC

MC511
OR
EQUIV

1 N3605
OR
EQUIV

_~~~~--+,=======0.4
V
~~-GND
t--~~-

Z

200 ns - - - - - I

TP out
GND

t+

CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
"The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe.
Coax shall be CT-070-50 or equivalent.
"" Load only pin 5 when testing output 5. Load both outputs 6 and 7 when
testing pin 6 or 7.

SWITCHING TIME TEST PROCEDURES
(Letters shown in test columns refer to waveforms. I
INPUT PIN

TEST

PINS
UNDER
TEST
Un/Outl

8
A

9
B

tpd+

11/5

Open

Gnd

X

tpd_

11/5

Open

Gnd

X

OUTPUT PIN
LIMITS

11
Cin1

5

7

12
13
Cin2 ®in1

14
1
Cin3 ®in2

Open

Gnd

Open Open

y

-

Open

Gnd

Open Open

y

-

35

6

SUM ®out Cout

-

I)S

max
35

tpd+

8/6

X

3.0 V

Gnd

Gnd

Open

Gnd

Open

Y
-

-

30

tpd_

8/6

X

3.0 V

Gnd

Gnd

Open

Gnd

Open

-

y

-

30

tpd+

8/7

X

3.0 V

Gnd

Gnd

Open

Gnd

Open

-

-

2

20

tpd_

8/7

X

3.0 V

Gnd

Gnd

Open

Gnd

Open

-

-

2

t+
t-

Te,sted during each of the above tests.

20
8.0
5.0

MC4328F,l thru MC4331 F,l, MC4028F ,l,P thru MC4031 F ,l,P (continued)
TYPICAL APPLICATION
The MC4328/29 and MC4330/31 adders can be used with the MC4332 Carry Decoder to build 8stage look-ahead carry subsystems. Each stage examines the carry outputs from all previous stages while
adding bits A and B for that stage. The carry outputs of the first and eighth stages are dependent upon
the carry inputs from previous stages; thus the MC4328/29 adder is used for stages one and eight while
the MC4330/31 adder is used for stages two through seven. The MC4332 Carry Decoder is used to expand the look-ahead carry input capability required for stages four through eight.
The add delay of an eight stage adder is equal to the sum of the add delay and the delay from the A
and B inputs to the@output of one stage. Thus the typical add delay for an 8-stage adder is 25 ns + 13

•

ns or 38 ns typical.

When expander inputs are not used they should not be connected to .any external point. This minimizes possible problems resulting from noise pick-up.
Cin

A1

B1

Jj"

9

11
13

=~
od

~

A2

82

A3

83

A4

B4

AS

85

8

9

8

9

8

9

8

9

~

MC4328

OR

~
=~
~

MC4329

~

~
~
~

r

MC4330

OR
MC4331

~

~

~
~
,....,1{

~

MC4330

OR
MC4331

MC4330

14r--"

~
~
~

5 6 7

56 7

1~

Il~

OR
MC4331

~

~

5 6 7

11
13
12

5rf

~
~

=

MC4330

OR

3 MC4331

~

MC4332

567

~

a
b

c
d

-

ra.STAGE LOOK·AHEAD
CARRY SUBSYSTEM

S1

83

82

84

86

A7

87

AS

8

9

8

9

8

11

I

14r--~

-<>"~

~

~MC4332

MC4330

OR
MC4331

~

5 6 7

~

-4

1 MC4330
14
OR

1 MC4328
14
OR

13
12

MC4331

~

MC4332

56

u-

b'

c'
d'

14r--~

~

MC4329

llo.o..2

13
7

~

~

rl

f3

MC4332

ri

11[,-

5r:f
Cout
Anticip ated Carry

to ne xt a-stage
bsvstem

.u

A1 (i) B1
C2
A2(i) B2
C3
A3(i) B3
C4
M(i)B4
C5
AS (i)·B5

e'
f'

g'
h'

c6
A6(i) B6
C7
56

9

"

14r--~

'V"~

B8

"

13
12

~

a'

55

AS

13
12

1~

9
h

57

58

MC4300/MC4000 series

"\

CARRY DECODER

\.-------------'

MC4332F,L*
MC4032F,L,P*
This 4-wide4, 5, 6,7 input AND-OR expander provides the necessary logic for carry decod ing between
look-ahead carry adder stages using the MC4328/29
and MC4330/31 fast adders.

14

8
13-~++t-J

EMITTER

':::'1---.....---12

9--+++t-J

...__-0----11
COLLECTOR

.3 -tTlFR=:3

2-++++-+-'

Input Loading Factor:

Pinsl,8,14

=4

Pin 7
Pin 3

= 3
= 2

6---..!=====:~

Pins 2, 5, 6, 9, 13 = 1
Total Power Dissipation = 20 mW typ/pkg

5----'

~tpd

= 4.0 ns typ/decoder
1.0 ns tvp/pF at expander nodes

Vee

= Pin

4

GND = Pin 10

TYPICAL APPLICATION
4

Vcc

4k

I

I(rr

..v-

\

13

4k

(r
I

'f

.vk

\

9

4k

I

Y

IrrJ ( ~
2

I

14 8 1

7

(r r

4k

II

5

~

~H:.::

6 3

~

10

·F suffix "'" TO~86 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-116 plastic dual in-line packa.ge (Case 605).

1211

The MC4328/29 and MC4330/31 adders can be
used with the MC4332 Carry Decoder to build 8-stage
look -ahead carry subsystems. (See the MC4328-31 )
data sheet for a diagram.) Each stage examines the
carry outputs from all previous stages while adding bits
A and B for that stage. The carry outputs of the first
and eighth stages are dependent upon the carry inputs
from previous stages; thus the MC4328/29 adder is
used for stages one and eight while the MC4330/31
adder is used for stages two through seven. The
MC4332 Carry Decoder is used to expand the look·
ahead carry input capability required for stages four
through eight.
The add delay of an eight stage adder is equal to
the sum of the add delay and the delay from the A and
B inputs to the (j;) output of one stage. Thus the type
ical add delay for an 8-stage adder is 25 ns + 13 ns or
38 ns typical.
When expand.er inputs are not used they should not
be connected to any external point. This minimizes
possible problems resulting from noise pick-up.

•

•

ELECTRICAL CHARACTERISTICS

s:

e

Test procedures are shown for only one set
of inputs. Test remaining inputs in the

same manner.

N

."

~

14
8

r
s:
o

1TT:1

1
13

~

7--....:I~::::j

9
3
2

8N

12

~"T1

...,r-

-,.m:t==1 _

6--"===~L

nO

5

::J
~.
::J

C

Pin

Uooer~~~-+~~~~~~~~~~-+~~~~~~~

Symbol I Test

Characteristic
Input
Forward Current

Leakage CUrrent

I

IF

I Ia

Inverse Beta Current I

Breakdown Voltage

.~-.

I

IL

BVin

5.5

-5.32
-1.33
-2.66
-3.99

-5.32
-1.33
-2.66
-3.99

-5.32

-6.64

-1.33
'-2.66

-1.66

-6.64
-1.66

-3.32

-3.32

-3.99

-4.98

-4.98

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.'
0.3

mAde

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.2
0.3

0.'
0.1
0.'
0.3

mAde

5.5

5.5

5.5

5.5

lOt

Unit

V,

V.

c..

~

~

~

r [- - [-[i
[

Vdc

Leakage Current

mAde

mAde

2,3,5,6,7,8,9,10,13,14
1,3,5,6,7,8,9,10,13,14
1,2,5,6,7,8,9,10,13,14
1,2,3,5,6,8,9,10,13,14

10

[

~
2,3,5,6,7,8,9,10,13,14
1,3,5,6,7,8,9,10,13,14
1,2,5,6,7,8,9,10,13,14

Vde

OUtput Voltage

Goo
10

I I I I I I I

Output

V" VE3 Vm . . Vee

Vth1 VthO VOUf1 V... 2 VEl

2,3,5,6,7,8,9,13,14
1,3,5,6,7,8,9,13,14
1,2,5,6,7,8,9,13,14
1,2,3,5,6,8,9,13,14

-6.64 mAde
-1.66
-3.32
-4.98

5.5

1,.121,.131,.141,.1

III

-_ ...._.•. , • __ .~ __ ~..

! I- I- I I !
I

12 I - 1-

11

111
11 1 - 1

-

112 1 -

112 1 -

•
•
•

1 " 2'3'5'6'Y'lO''''''

2,3,5;6,7,9,10
1,10

10

Power Requirements
Maximum Power

Supply Current
Power Supply Drain

I

max

mAde

IpDH

mAde

IpDL

mAde

·Voltage measured between pins 11 and 12.

I
12

112

1 - 1-

•

1,2,3,5,6,7,8,9,10,13,14

•

10
1,2,3,5,6,7,8,9,10,13,14

MC4300/MC4000 series

QUAD LATCH
(Open Collector)

MC4335F,L*
MC4035F, L, P *

This monolithic device consists of four latch circuits with
open collector outputs, common Strobe input, and output
DO 1~-J--\-________- ,

Strobe 2
14 00

01 3-...L....s-----.}--r-_ _ _ _ _...,

enable input. The output of each latch will follow the data
input when the Strobe input is in a logical "1" state. When
the Strobe is in a logical "0" state, the latch will store the
logic state of the data input just prior to the change of the
Strobe from a "I" level to a "0" level.
The open collector outputs make this device useful for
bussing or wire DRing outputs together. Two 5.0 k ohm
resistors are available in the package to provide the passive

pullup function in wired·OR or bussed operation. The output
enable is useful where it is desirable to gate information out
of the latches according to a predetermined timing scheme.
1201

02 5

Input Loading Factor (MTTL I Loads):

11 02

03 7-...L....r----.}--t_------,

8

Enable 6 - - - - " - - - - - - - - - - - - - . . . . , _ . . /

03

Two 5.0 k ohm pullup resisTors are internally
connected to VCC and brought out on pins 9 and 13.

Data I nput (Strobe H jgh) - MC4335 =
MC4035 =
Data I nput (Strobe Low) - MC4335 =
MC4035 =
Output Enable - MC4335 = 4.0
MC4035= 3.6
Strobe - MC4335 = 5.2
MC4035= 5.2
Output Loading Factor (MTTL I Loads):

4.2
4.0
1.1
0.9

MC4335 = 7 (I OL = 9.3 mAde)
MC4035= 7 (lOL = 11.6 mAde)
Total Power Dissipation = 140 mW tYP/pkg
Propagation Delay Time = 25 ns typ

CIRCUIT SCHEMATIC
1/4 OF DEVICE SHOWN

VCC

5k

9

'----013

Oatao-~~~-*----+_--------t_----+_--~
~---vQ

Strobe

GNO

.. F suffix = TO-S6 ceramic flat package (Case 607).
L suffix = TO-116 ceramic'dual in-line package 1.0 Megohm) must be used.

SWITCHING TIME TEST PROCEDURES (T A = 25°C)
(Letters shown in test columns refer to waveforms.)

TEST
Strobe Propagation Delay

PIN
UNDER
TEST
(In/Out)

Pin 1
DO

t p d+l

2/14

T

t pd_1

2/14

T

SYMBOL

INPUT

Pin 2

OUTPUT

LIMITS (ns)
Max

RL
Ohms

Strobe

Pin 6
Enable

Pin 14
DO

MC4335

MC4035

MC4335

S

2.4V

U

510

390

25

25

S

2.4V

U

510

390

40

35
50

MC4035

t p d+2

2/14

T

S

2.4V

U

5.0k

5.0k

50

tpd-2

2/14

T

S

2.4 V

U

5.0k

5.0k

34

34

Rise Time

t+

14

T

S

2.4 V

U

5100r

390 or

0.3 RC

0.3 RC

5.0 k

5.0k

Fall Time

t-

14

T

S

2.4V

U

510

390

9.0

5.0

t pd+3

1/14

V

2.4 V

2.4 V

W

510

390

20

20

tpd-3

1/14

V

2.4 V

2.4V

W

510

390

30

25

t pd+4

1/14

V

2.4 V

2.4 V

W

5.0 k

5.0k

50

50

Data Propagation Delav

Enable Propagation Delay

tpd_4

1/14

V

2.4V

2.4V

W

5.0 k

5.0k

25

25

t pd+3

1/14

X

2.4 V

Y

Z

510

390

20

20

t pd-3

1/14

X

2.4 V

Y

Z

510'

390

30

25

t pd+4

1/14

X

2.4V

Y

Z

5.0 k

5.0k

50

50

t pd-4

1/14

X

2.4V

Y

Z

5.0 k

5.0k

25

25

Minimum Strobe Enable

-

1/14

T\l!

1.BV

2.4 V

(6)

5.0 k

5.0k

~

Ma)( imum Strobe Inhibit

-

1/14

T(1)

1.0V

2.4 V

@

5.0 k

5.0k

@

@
@

(!) Pulse T conditions changed: VL"" 1.0 V, VH "" 1.8 V
~ Output shall follow data input.
@ Output shall not toggle.

MC4335F ,L, MC4035F ,L,P (continued)

VOLTAGE WAVEFORMS

STROBE INPUT

===p-t!
~m
~~-:-e

S
PRF

=

4.0 MHz

4

t+_

p-------;:;

,

1---+-----------.---3.0 v

T
PRF == 2.0 MHz

-~~===t======~-----+--------'=g~6
-----i

20 ns min

------+-L~2.0

u

V

1.5 V
1.0 V

------GND

DATA INPUTS

PRF

=

V
4.0 MHz

=~-----+~===='t----I-----+-~==g~6
w

ENABLE INPUT

X
PRF = 2.0 MHz

V
PRF = 4.0 MHz

,------3.0 V

=-q------~~=====~=====g·~6

w

0.4 V

---~~--~~---~---~----------GND
t Pd

tpd+

z

-------------;;-tt-_t-~·-·~rt+rr·--------GND

•

II
Strobe

+:>0

W

0.4 V

This quad latch consists of four gated latches that store data on
the negative edge of the strobe input. Information must be present
at the data inputs prior to the setup time and remain at the data inputs through the hold time to insure that it will be stored by the
latch when the negative edge of the strobe occurs. The setup time
is 7.0 ns for a logical "1" and 5.0 ns for a logical "0", Hold time
is 7.0 ns after the strobe edge for a logical "1" and 5.0 ns prior to
the strobe edge for a logical "0".

OPERATING
CHARACTERISTICS

s:
(")

3.0 V

W

thold"1"
7.0 ns
Data

U'I

r"

"1"

"0"

s:

5.0 ns

(")

Data

.j::o.

o
w

"0"

t setup"1"

U'I

7.0 ns

"

r"'-c
8::l

-------

ELECTRICAL CHARACTERISTICS

-

Test procedures are shown for the Strobe,
Enable, and only one data input, and for
one output, Other data inputs and outputs
are tested. in the same manner.
Pin
Under
ISymbol Test

Characteristic
Input

I

Forw.Hd Current

IF

Leakage Curro"llt

I

Breakdown Voltagr>

IBV in

I

mA
1m

M(433S
M(403S

MC4335 Test Limits
SSO(
+25"(
+125'(
Min Max Min Max Min Max

,:;:

-5.6

I
1
2

-1.5

6

-7.0
-5.3

13

-1.3
0.2
0.5
0.4

IR

5.5

MC4035 Test Limits
0'(
+25'(
+75'(
Min Max Min Max Min Max

-5.6

-1.8

'n
-1.3

.:::i

6

-6.0
-1. 6

0.2
0.5
0.4

0.2
0.5
0.4

0.2
0.5
0.4

0.2
0.5
0.4

5.5

5.5

5.5

-n:

-6.7

6: 8

-1.5
-7.0
-5.3
-1.3

-8.6

0.2
0.5
0.4
5.5

5.5

11. 6

9.3

TEST CURRENT iVOlYAGEVillUEs-(All Temperatures)
Volts

lOH

I,.

V,"

V'H

V,

V,

Vout

I 0.1

l.0

0.8

2.0

0.4

4.5

5.5

7.0

5.0

4.5

l.0

0.8

2.0

0.4

4.5

5.5

7.0

5.0

4.7~5.25

0.'

lOl

lOH

I,.

V,"

V'H

:IlAdl

V,

V,

I
1
2
6

2
3,5,7
1,3,5,6,7
1,2,3,5,7
I

13

Vout Vmax Vcc VCCl VCCH

I

I I-I

I

I

Output Volta!!:e

VOL

0.4

14

0.4

0.4

14
14

VOH1

I

Leakage Current

ICEX

14

14
14

14

2.4
2.4

2.4
2.4

2.4
2.4
0.25
1.0

0.25
1.0

0.4

0.4

0.4

I

I

I

2.4
2.4
0.25
1.0

2.4
2.4
0.25
1.0

2.4
2.4
0.25
1.0

Cl.

I

Pulse Pulse
1
2 -I

Gnd

I- I -I

10

2,10
1,3,5,7,10
1,2,3,5,7,10

Vde

2,10
1,3,5,6,7,10
1,2,3,5,7,10

Vde

14

2,3,5,7

1,10
10
10

2,6

14

14
Vde
Vde

0.25
1.0

4

CD

mAde

I
Output

::l

C

I 5.5

TEST CURRENTiVOLTAGE APPLIED TO PINS LISTED BElOW,
Unit

!:!'.

Ivmaxi Vce IVccllVecH

mAde
mAde

14

14

1,3,5,7,10
10

1,2,6
1,2

14
14

10
6,10

Power Requirements
(Total Device)
Maximum Power
Supply Current

1,3,5,6,7,10

Power Supply Drain

10
1,3,5,6,7,10

~:~ ~

Pulse' 1---,

'ti
-

OV
24V

l~i~S

QUAD LATCH

MC4300/MC4000 series

"'\

l _ _ _ _--------'

MC4331F,L *
MC4037F, L, P *

DO 1~~-r----}_------,

Strobe 2
14 00
01 3

This monolithic device consists of four latch circuits
with active pullup networks for high capacitive load
drive capability. Separate data inputs and a common
Strobe input are provided. Information present on the
data inputs prior to the negative edge of the strobe in·
put will be stored in the latch. When the strobe input
is high, the Q output will follow the data input.

12 01
Input Loading Factor (MTTL I Loads):

025-,t-r-J-t---------,

Data Input (Strobe High) - MC4331 ::: 4.2

MC4037 = 4.0
Data I nput (Strobe Low) - MC4337
Strobe -

03 7·~--'--J"""------}_I_-----__,

= 1.1

MC4037 = 0.9

11 02
MC4337

MC4037

= 5.2
= 5.2

Output Loading -Factor (MTTL J Loads):
MC4337 10 (lOL 13.3 mAde)
MC4037 10 (lOL 16.6 mAde)

=
=

8

03

=
=

Total Power Dissipation
Propagation DelaY Time

= 150 mW tYP/pkg
= 25 ns typ

Vee= Pin 4
GND= Pin 10

CIRCUIT SCHEMATIC
1/4 OF DEVICE SHOWN

VCC

4k

D.t.o-~~~-4--~------~--~r-~

o

Strobe

1 k

2k

GNO

*F suffh( = TO-86 ceramic flat package (Case 507).
L suffix = TO-116 ceramic dual in-line package (Case 632).

P suffix = TO-116 plastic dual in-line package (Case 605),

1 k

•

MC4337F ,L, MC4037F ,L,P (continued)

II1II

~I__________________________

O_P_E_R_A_T_IN_G__C_H_A_R_A_C_T_E_R_IS_T_ICS
__________________________

Strobe

3.0V
1.5 V

0.4 V

This quad latch consists of four gated latches that store data on
the negative edge of the strobe input. Information must be present
at the data inputs prior to the setup time and remain at the data
inputs through the hold time to insure that it will be stored by the
latch when the negative edge of the strobe occurs. The setup time is
7.0 ns for a logical "1" and 5.0 ns for a logical "0". Hold time is
7.0 ns after the strobe edge for a logical "1" and 5.0 ns prior to the
strobe edge for a logical "0".

~

Data

"'"

Data

",".

"0"

"0"

thold"1"

tsetup"O"
5.0 ns

~

I

,.5 V\.

"1

f--

7.0 ns

thold"O"
5.0 ns

i J

1. 5V

I-----.t-

t setup"l"

7.0 ns

SWITCHING TIME TEST CIRCUIT

Vcc
Coax·

00
2
3

PULSE
GENERATOR

5
t+

= t-'55.0 ns

50
7

Zout == 50 ohms

00 '4

Strobe

0'
01
02

'2
11
TP out

02
03

RL 330 ohms - MC4337
280 ohms - MC4037

03

8

Two pulse generators are required
and must be slaved to provide the
waveforms shown.

CT"" 15 pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.
*The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950-ohm resistor
and the scope termination impedance constitute a 20: 1 attenuator probe.
Coax shall be CT-070-50 or equivalent.

MM07000
or Equiv

MC4337F ,L, MC4037F ,L,P (continued)

•

VOLTAGE WAVEFORMS

STROBE INPUT

~--,"-------3.0

V

V
PRF - 4.0 MHz

====~-l---___J.~====-::!....-l-----=====g.~~
Jr--+-------~--3.0 V

W
PRF = 2.0 MHz

----+~==:::j::======~--___J.--------~g.~~
------+--.L~-2.0 V

x

1.5 V

__ _ _ _ _ _

~-~~==l.=O=V==============i===~--------- GND

DATA INPUTS

_Lr--"".lI::-----3.O V

y

PRF

= 4.0 MHz

z

==~~~--+--~======1_+_--~~·GND

SWITCHING TIME TEST PROCEDURES (T A

=

25°C)

(Letters shown In test columns refer to waveforms.)

TEST
Strobe Propagation Delay

OUTPUT

INPUT

PIN
UNDER
TEST
(In/Out)

Pin 1
DO

Pin 2
Strobe

Pin 14

t pd+1

2/14

W

V

X

25

tpd-1

2/14

W

V

X

40

SYMBOL

00

LIMITS (ns)
Max

Rise Time

t+

14

W

V

X

B.O

Fall Time

t-

14

W

V

X

5.0

t p d+2

1/14

y

2.4 V

Z

20

t p d-2

1/14

y

2.4V

Z

30

Minimum Strobe Enable

-

1/14

wUl

1.BV

~

~

MSKimum Strobe Inhibit

-

1/14

wGl

1.0V

@

@

Data Propagation Delay

cr> Pulse W conditions changed: V L = 1.0 V,
® Output shall follow data input.

@ Output sha~' not toggle.

VH = 1.8 V.

•

ELECTRICAL CHARACTERISTICS

S
n

Test procedures are shown for only the

t;

Strobe input, on9 data input, and one out-

put. Other data inputs and outputs are
tested in the same manner.

~

,"T1

r

sn

-I=:to

o

W

......

,."

MC4337
MC4037

1m

10H

lin

V"

V'H

V.

V.

Vou'

Vm~ I VCC IVCCL I· VCCH

8

-1.4

1.0

0.8

2.0

0.4

4.5

5.5

7.0 15.0 14.5

~.

IS.3

-1.4

1.0

O. B

2.0

0.4

4.5

5.5

7.0 15.0 14.7U5.25

IF

Leakage Current

IR

Breakdown Voltage

-5.6
-1. 5
-7.0

-5.6
-1. 5
-7.0

-5.6
-1. 5
-7.0

-6.7
-1. 8
-8.6

-6.7
-1.8
-8.6

-8.6

0.2
0.5

0.2
0.5

0.2
0.5

0,2
0.5

0.2
0.5

0.2
0.5

BVin

5.5
5.5

VOL

14
14

0.4
0.4

-1. 8

mrl

YOH

14

2.4

Short-Circuit Current

ISC

14

-15

Leakage Curren t

I CEX

14

Power Requirements
(Tolal Device)

Il

Maxhrium Power
Supply Current
~er

Supply Drain

ti

Pulse: I ,
Pulse: 2

-

2.4
-60

-15

2.4
-60

-

-

40

, IpDH

-

26

-

26

IPDL

4

-

45

-

45

~:: ~

2.4 Y
OY
100 nS
min

4

-15

0.25

0.25

4

max

0.4
0.4

0.4
0.4
2.4

-60

-15

0.25

-

0.4
0.4
2.4

-60

-15

0.25

-15

0.25

I

Yde

,

-60

mAde

0.25

mAde

Yde

-

-

-

32

-

321-1321mAde

55

-

55

,

-

,

55

I I- I - I - I~

Gnd
10

~
2,10
1,3,5,7,10

Vdc

I-I -I

I

I You, 1,1
I VCCH,I Pulse
V_x Vcc I
VCCL
1 Pulse
2

Yde
Yde

45

3,5,7
2
1,3,5,7

CI>

C-

2,10
1,3,5,7,10

26

50

I

~

c:

mAde

0.4
0.4
2.4

-60

1
11
2

mAde

5.5
5.5

0.4
0.4

I - I - I~ I

-6.7

Output
Output Voltage

10L IloH I 1;0 I V'L I V'H I V. I V.

~

I 5.5

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:

,

Forward Current

~

13.3

MC4337 Test Limits
MC4037 Test Limits
I
Pin
+2S·C , +7S·C ,
SS·C
, +25·C , +12S·C I O·C
Under'
Symbol! Test I Min I Max I Min I Max I Min I Max I Min I Max I Min I Max I Min I Max I Unit

Characteristic
Input

r

TEST CURRENT / VOLTAGE VALUES (All Temperatures)
Volts

mA

mAde

'mAde

10
10

14

14

-

'14

,

,

-

10

'1,2

10,14

I -I- I - I- I- I- I

1,2

'14

10

10
10

1,3,5,7,10

MC4300/MC4000 series

INVERTING/NON-INVERTING
ONE-Of-EIGHT DECODER

MC4038P*

3-Bit Binary
15 6 1
OUtput

7
9

10

Inversion

Enable
Inputs

The MC4038P is derived from the XC170 128-8it Read Only
Memory. A 3-bit binary address selects the desired word for the
8-bit output. The inversion control, D, selects half of the memory
chip with the bit pattern that defines a 1-of-8 decoder function.
When D is a logic "0", the selected output is designated as a logic
"0". A logic "1" on D produces a logic "1" on the selected output.

Control

07

00

Features:
Address times < 45 ns
Outputs sink 20 mA
Output capacitance < 7.0 pf @ 1.5 V
Wired OR capability to 64 memories

324511121413
1-of-8 Output
Vee"" Pin 16
Gnd = Pin 8

TRUTH TABLE (POSITIVE LOGIC)
D

a
a
a
a
a
a
a
0
1
1
1
1
1
1
1
1

INPUT
C B A

OUTPUT

7

6

5 4

3

a a b
a a 1
a 1 a
a 1 1

a

1

1
1
1

a

1
1

1
1

a
1

a

1
1
1
1

0
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

a

1

0
1

o·
a

0
0
0
1
0
0
0
0

a
a
a
a

1
1
1
1

0"

a
1
1

a

1

a a 0
a a 1
a 1 0
a 1 1
1
a a
1
a 1
1
1

1
1

0
1

0

a a
0 a
0
0
0
0

0
0
0

a

Total Power DissipatiOn

1

0

a
0

a
0

=

1
1
1

1
1
1

1

a
0

a

2

1

0

1

1
1
1
1

1
1
1
1

1
1

1
1
1

1
1
1
1

a
1
1

0
0
0
0
0
1
0
0

a

ENABLE INPUT TRUTH TABLE (POSITIVE LOGIC)

a
a
a a
0 a

1
0

0
0
0
1
0

0

E

E

Q7

06

05

04

03

02

01

00

0
0

0
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1

0
1

1
1
1

1
1
1
1
FUNCTION ENABLED

1

1

1

a
a
a

1

1

240 mW typ/pkg

Word Line 16

BltO

Word 16

Bit7

......................................

-----".~
I
I

I

Word 0

ROM
Address
Inputs

•

'P suffix

= lS-pin dual in-line plastic package (C... S12).

Links removed if logic"'" state desired.

BitO I

MC4038P (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

•

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
LOADING
FACTOR

1.0
1.0
0.67
0.7
1.0

Open
Collector
IOL=20mA

MC4000
MC400
MC2000
MC3000
MC7400
MC830

Note: Differences in MC4000 series loading factors r.sult from
differences in specifications for each family.
•• Applies only when input is being driven by MDTLgate with 2 k ohm

pullup resistor. Logic "I" state drive limitations of gates with 6 k
ohm pullup resistors reduce drive capability to fan-out of 3.

1.16··

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Yoltage

YCC

-0.5 to+7.0

Yde

Supply Operating Yoltage Range

YCC

4.5 to 5.5

Yde

Input Yoltage

Yin

-1.5 to +5.5

Yde

Operating Temperature Range

TA

oto +75

Storage Temperature Range

Tstg

-55 to +125

°c
°c

Rating

ELECTRICAL CHARACTERISTICS ITA = 0 to +7SOC)
Symbol

Characteristic

Address Input Forward Current
01A = O. YCC = 5.0 Yde)

IF

Enable Input Forward Current
(YE = 0, YCC = 5.0 Yde)

IF

Address Input Leakage Current
(Y A = 5.5 Yde, YCC =5.0 Yde)

IR

Enable Input Leakage Current
(YE =5.5 Yde, YCC =5.0 Yde)
Logical "0" Output Voltage
(IOL = 20 mAde, YIL =0.9 Ydc, YIH

IR

Min

Max

Unit
mAde

1.6
mAde
1.6
!lAde
100
!lAde
100

=2.0 Yde, YCC =4.75 Yde)

Logical "1" Output Leakage Current
(YIL =0.9 Yde, YIH = 2.0 Ydc, YCEX

=7.0 Yde, YCC = 5.25 Ydc)

Power Supply Drain Current
(Memory Enabled, YCC = 5.25 Ydc)
(Memory Disabled, YCC = 5.25 Ydc)

Ydc

YOL
0.45
ICEX

!lAde
100
mAde

IpD max
IPDmin

73
55

t++
t--

45

ns

45

ns

t+-

45

n.

t-+

45

ns

SWITCHING TIMES (VCC = 5.0 Vdc)
Positive Input Address to Positive Output
Negative Input Address to Negative Output
Positive Input Address or Enable to Negative Output
Negative Input Address or Enable to Positive Output

IOL = lOrnA
driving
30 pF

MC4300/MC4000 series

SEVEN-SEGMENT
CHARACTER GENERATOR

MC4039P*

Enable Il"!puts

Lb

I

B

Output

a

b

12

11

c
5

.,...v

MC4039P

C
0

Pin No.

t>t>-

a

A

1
Digit
6
Number 15
10

I

h

d

e

f

4

13

14

hi
3

9
2

The MC4039P is derived from the XC170
128-8it Read Only Memory. It can directly

Digit
Indicator

operate low-voltage lamp indicators. A four'
digit binary input is translated into combinations of the eight outputs. These combinations correspond to different illuminated

Vee

= Pin

Gnd

~

segments of the seven-bar digit indicator.
The input and output codes with their related

16
Pin B

Total Power Dissipation

= 240

numerical digits are shown in the diagram.

The enable inputs can be used for automatic

mW typ/pkg

blanking.

Features:
TRUTH TABLE (POSITIVE LOGIC)
Digit
Indicator

a

c::==::J

f~ ~b
9

c::==::J

e~ ~c
0

c::==::J

h

d

DIGIT

SEGMENTS
ILLUMINATED

0
1

a,b,c,d,e,f
b,c

2

a,b,d,B,g
a,b,c,d,g
b,c,f,g
a,c,d,f,Q
c,d,e,f,g
a,b,c
8,b,c,d,e,f ,9
a,b,c,f,g

3
4
5
6
7
8
9

NONE

•

-

·NONE
NONE
NONE

h IExt.)
9

INPUT
D

C

B

A

a

b

c

d

e

f

9

h

0
0
0
0
0
0
0
0
1
1
1
1

0
0
0
0

0
1
0

0

0
0
0
0
0
1
1
0
0
0
1

0
0

0

0

0

1

1

1

1

1

0
0
1
0
0

0

1
1
0

1
0
0
0
0
0
1

1
1
1
1
1

1
1
1
1

1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1

1
1
1

0
0
0
0
1
1

1

0
0

1

0
0
0
0
0
0
0
1
1

1

1
1

1
1

1
1

0
1

1
1

1
1

1
1

1

0
1
0
1

0
1
0
1

0

1

0
1
0
0
0
1
1

Io---l-)-r===r~~~~~~~[=~
Word Line 15

Enable
Inputs

1
0

1
1
1
1
1
1
1

1
1

1
0
1
0
1
1
1
1
1

1
1

a

0
1
0

0

0
1

0
1

1

1

1
1
1
1

0
1
1
1

<

Address times
45 ns
Outputs sink 20 mA
Output capacitance < 7.0 pF @ 1.5 V

OUTPUT

Wired OR capability to 64 memories
ENABLE INPUT TRUTH TABLE
(POSITIVE LOGIC)

1
1
1
1
1
1
0
1
1
1
1

b

1

1
1
1
1
1
1
1
1
1
FUNCTION

1
1

Bit7

.;.:.;.;.:.;.;.;.;.;.;.:.:.;.:.;.;.:.:.

....................

f

g

h

1
1
1
1
1
1
1
1
1
ENABLED

1
1
1

e

a

1 1

Word 15

c

E E
0 0
0 1
1 0

d

BitO

Word 15

.......................................
:::::::::;:::::::;:::;:;:;:;:;:;:;:;:;:

~;l].· -----i.il• ~.

• • • • • ••• • • • • • • •
I

.. T····

I

I

I

Word 0

Bit 7 I

ROM
Address
Inputs

•

'P suffix

= 1S-pin dual in-line plastic package (Case 612).

Links removed if logic

06

1" state desired.

I

Word 0

Bit 0 I

MC4039P (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

•

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

MC4000
OUTPUT
LOADING
FACTOR

Note: Differences in MC4000 series loeding factors result from
differences in specifications for each family.

1.0
1.0
0.67
0.7
1.0

Open
Collector
IOL = 20 mA

•• Applies only when input is being driven by MDTLgate with 2 k ohm

pullup resistor. Logie "I" state drive limitations of gates with 6 k
ohm pullup resistors reduce drive capability to fan·out of 3.

1.15··

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7.0

Vde

Supply Operating Voltage Range

Vee

4.5 to 5.5

Vde

Input Voltage

Yin

-1.5 to +5.5

Vde

Rating

Operating Temperature Range

TA

oto +75

°e

Storage Temperature Range

Tstg

-55 to +125

°e

ELECTRICAL CHARACTERISTICS (T A • 0 to +75OCI
Symbol

Characteristic

Address Input Forward eurrent
01 A = 0, Vce = 5.0 Vde)

IF

Enable Input Forward eurrent
(VE = 0, Vce = 5.0 Vde)

IF

Address Input Leakage Current
(V A = 5.5 Vde, Vec = 5.0 Vde)

IR

Enable Input Leakage Current
(VE = 5.5 Vde, Vce = 5.0 Vde)

IR

Min

Max

Unit
mAde

1.6
mAde
1.6
"Ade
100
"Ade
100

Logical "0" Output Voltage
(I0L = 20 mAde, VIL = 0.9 Vdc, VIH = 2.0 Vdc, Vec = 4.75 Vde)

VOL

Logical "1" Output Leakage Current
(VIL = 0.9 Vdc, VIH = 2.0 Vde, VCEX = 7.0 Vde, VCC = 5.25 Vde)

IeEX

Power Supply Drain Current
(Memory Enabled, Vec = 5.25 Vde)

Vde

0.45
"Ade
100
mAde

IpO max

(Memory Disabled, Vce = 5.25 Vde)

IPOmin

73
55

t++

45

ns

t--

45

ns

t+-

45

ns

t-+

45

ns

SWITCHING TIMES (VCC - 5.0 Vdcl
Positive Input Address to Positive Output
Negative Input Address to Negative Output
Positive Input Address or Enable to Negative Output
Negative Input Address or Enable to Positive Output

IOL= lOrnA
driving
30 pF

MC4300/MC4000 series

BINARY TO
TWO-Of-EIGHT DECODER

MC4040P*

4-Bit Binary
1015 6 1
7 Enable
9 Inputs

The MC4040P is derived from the XC170 128-Bit Read Only
Memory. This device, with two enable inputs, transforms any 4-bit
binary number to a 2-of-8-bit coded number. The device can also
be thought of as a dual binary to 1-of-4 decoder.
324511121413
Gnd

= Pin

Features:
Address times < 45 ns
Outputs sink 20 mA
Output capacitance < 7.0 pF @ 1.5 V
Wired 0 R capability to 64 memories

2-of-8 Output

Vec = Pin 16
8

TRUTH TABLE IPOSITIVE LOGIC)
INPUT

OUTPUT

D C

B A

7

6 5 4 3 2 1 0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1

0
1
0
1

1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1

Total Power DISSipation

0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
0
1
1
1
0
1
1
'1
0

1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1

1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1

0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1

ENABLE INPUT TRUTH TABLE (POSITIVE LOGIC)

E

E

07

06

05

0
0
1
1

0
1
0
1

1
1
1

1
1
1

1
1
1

04

03

02

1
1
1
1
1
1
1
1
1
FUNCTION ENABLEO

01

00

1
1
1

1
1

_-L

= 200 ,:"W typ/pkg

Word Line 15

Bit?

BitO

Word 15

- .....

-- .......... .

Word 0

I
I
BltO I

~nn::~ {~LJr-r=G~~g=}-1-~~~~-----.!,~I~~
I

ROM
Address
Inputs

•

'P suffix = H"pin dual in-line plastic package (Case 612).

Links removed if logic "1" state desired.

MC4040P (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

I

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
MC400
MC2000
MC3000
MC7400
MC830

MC4000
OUTPUT
LOADING
FACTOR

Note: Differences in MC4000 series loading factors result from
differences in specifications for each family.

1.0
1.0
0.67
0.7
1.0

Open

Collector
IOL

= 20 mA

"Applies only when input is being driven by MDTLgate with 2 k ohm
pullup resistor. Logic "1" state drive limitations of gates with 6 k
ohm pullup resistors reduce drive capability to fan-out of 3.

1.15··

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.5 to +7.0

Vde

4.5 to 5.5
-1.5 to +5.5
o to +75
-55 to +125

Vde

Rating
Supply Operating Voltage Range

VCC

Input Voltage

Yin

Operating Temperature Range

TA

Storage Temperature Range

Tstg

Vde

°c
°c

ELECTRICAL CHARACTERISTICS (TA = 0 to+750c)
Symbol

Characteristic

Address Input Forward Current
(VA = 0, VCC = 5.0 Vde)

IF

Enable Input Forward Current
(VE = 0, VCC = 5.0 Vde)

IF

Address Input Leakage Current
(VA = 5.5 Vde, VCC = 5.0 Vde)

IR

Enable Input Leakage Current
(VE = 5.5 Vde, VCC = 5.0 Vde)

IR

Min

Max

Unit
mAde

1.6
mAde
1.6
"Ade
100
"Ade
100

Logical "0" Output Voltage
(lOL = 20 mAde, VIL = 0.9 Vdc, VIH = 2.0 Vdc, VCC = 4.75 Vde)

VOL

Logical "1" Output Leakage Current
(VIL = 0.9 Vde, VIH = 2.0 Vde, VCEX = 7.0 Vde, VCC = 5.25 Vde)

ICEX

Power Supply Drain Current
(Memory Enabled, VCC = 5.25 Vde)

Vde
0.45
"Ade
100
mAde

IPDmax

(Memory Disabled, VCC = 5.25 Vde)

IPDmin

60
55

t++
t--

45

n,

45

ns

t+-

45

n.

t-+

45

n.

SWITCHING TIMES (Vce - 5.0 Vdc)
Positive Input Address to Positive Output
Negative Input Address to Negative Output
Positive Input Address or Enable to Negative Output
Negative Input Address or Enable to Positive Output

IOL = lOrnA
driving
30 pF

MC4300/MC4000 series

SINGLE-ERROR
HAMMING CODE DETECTOR
AND GENERATOR

MC4041P*

The MC4041P is a programmed 128-bit Read Only

Message

Memory suitable for a variety of error detection and
correction applications.
Simple parity trees for error detection can be con~

Bits

M:f JM:1M:t MoI
o

I

T,a~smi~ted
Panty Bits

lr L

C

B

A

I. I. I. I. /,

c!mpare Circuit
(Excluslve "OR"

D C

B A

7

6

5

4

3

2

1 0

0
0

0
0
1
1

1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1

1
1

1
0
1
0

1
0
0
1
1
0
0
1
0
1
1
0

a
a a
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1

a

0
1
1
0
0
1
1

a

1
0
1

a

0
0

a

1
1
0
0
1
1
1
1
0
0

0
1
0
1
0
1
0
1
1
0
1
0

P4

Address times < 45 ns
Outputs sink 20 rnA
Output capacitance < 7.0 pF @ 1.5 V
Wired OR capability to 64 memories

Vee

= Pin

ENABLE INPUT TRUTH TABLE
(POSITIVE LOGIC)
E E 07 06 05 Q4 03 02 01 00
0 0 1
1
1
1
1
1
1
1
0 1 1
1
1
1
1
1
1
1
1 0 1
1
1
1
1
1
1
1 1
FUNCTION ENABLED

16

Gnd "" Pjn 8

Simple Parity: The outputs of
bits 0, 6, and 7 provide parity
check over the 4 message bftS.

OUTPUT
0
1
0
1
0
1
0
1
0
1
0
1

Generated
Parity
Bits

PI
P2

Error Detection;

TRUTH TABLE (POSITIVE LOGIC)
INPUT

block. Also, more complex error control schemes,
suchasHamming single error detection and correction,
can be implemented with this device.
Features:

Binary Code of
Bit In Error.

00 01 02030405 0607
13 14 12 11 5
4
2
3

Output

0
0
0

01
02
03

Of Corresponding
Inputs)

Pin No.

structed using the MC4041 P as the basic building

I

MC4041P

t t?

1 Enable

9 Inputs

a
1
1
0

a

1
1
0
1
0
0
1
1
0
0
1
0
1
1
0

PARITY TREE fOR '6-8ITWORD

Hamming Detection and Correetion: Bits 1, 2. and 3 perform
the parity calculations necessary
for Hamming Code generation or

detection on 4 message bits. Fa ...
greater than 4 bits per message,
ROM's may be cascaded. In these
cases, I?its 4, 5, 6, and 7 perform

the necessary parity calculations.
Total Power Dissipation

=

240 mW
typ/pkg

For more information on this tunction and its uses, see Application Note
AN-446, "The XC170 128-Bit Read
Only Memory".

Word 15

BitO

:.:.:.:.:~: .:.:.~.:.:.:.:.:

Inputs

I

I
I

I
I

I

I

Ward 0

Blt7 I

ROM

Address
Inputs

•
• p suffix = 1S-pin dual in-line plastic package (Case 612).

.:.:.:.:-;:

------.~

Enable {

Links removed if logic "1" state desired.

I

Word 0

BitO I

MC4041P (continued)

INPUT and OUTPUT LOADING FAcTbRS
with respect to MTTL. and MDTL famili ..

•

FAMILY

MC4000
INPUT
LOADING
FACTOR

MC4000
OUTPUT
LOADING
FACTOR

Note: Differences in MC4000 series loading factors result from
differences in specifications for each family.

1.0
1.0
0.67
0.7
1.0

MC4000
MC400
MC2000
MC3000
MC7400
MC830

Open
Collector
IOL=20mA

.. Applies only when input is being driven by MDTLgate with 2 k ohm
pullup resistor. Logic "1" state drive limitations of gates with 6 k
ohm pullup resistors reduce drive capability to fan-out of 3.

1.15··

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.5 to +7.0

Vde

Supply Operating Voltage Range

VCC

4.5 to 5.5

Vde

Input Voltage

Yin

-1.5 to +5.5

Vde

Rating

Operating Temperature Range

TA

o to +75

°c

Storage Temperature Range

Tstg

-55 to+125

°c

ELECTRICAL CHARACTERISTICS (TA = 0 to +75 0 cl
Symbol

Ch~ractaristic

Address Input Forward Current
(VA = O. Vce = 5.0 Vde)

IF

Enable Input Forward Current
(VE = 0, VCC = 5.0 Vde)

IF

Address Input Leakage Current
(V A = 5.5 Vde, VCC = 5.0 Vde)

IR

Enable Input Leakage Current
(VE = 5.5 Vde, VCC = 5.0 Vde)

IR

Min

Max

Unit
mAde

1.6
mAde
1.6
/lAde
100
/lAde
100

Logical "0" Output Voltage
(lOL = 20 mAde, VIL = 0.9 Vde, VIH= 2.0 Vde, VCC = 4.75 Vde)

VOL

Logical "I" Output Leakage Current
(VIL = 0.9 Vde, VIH = 2.0 Vde, VCEX = 7.0 Vde, VCC = 5.25 Vde)

ICEX

Power Supply Drain Current
(Memory Enabled, VCC = 5.25 Vde)

Vde
0.45
/lAde
100
mAde

IPDmax

(Memory Disabled, VCC = 5.25 Vde)

IPDmin

73
55

SWITCHING TIMES (VCC = 5 0 Vdcl
Positive Input Address to Positive Output
Negative Input Address to Negative Output
Positive Input Address or Enable to Negative Output
Negative Input Address or Enable to Positive Output

IQL=10mA
driving
30 pF

t++

45

ns

t--

45

ns

t+-

45

ns

t-+

45

ns

MC4300/MC4000 series

QUAD PREDRIVER

MC4042F, L, P*
DUAL LINE SELECTOR

MC4043F, L, P*
The MC4042 and MC4043 are designed for magnetic memory

driver/selector applications.
The MC4042 monolithic quad predriver consists of four high-

speed switching transistors, each driven by an MTTL compatible
NOR gate. Each NOR gate has an individual address input and a
common timing input. The inputs of the MC4042 can be driven

directly with standard MTTL decoders such as the MC4006 binary
to one-at-eight decoder or the MC4007 dual binary to one-af-four
decoder. The open-collector output transistor of the MC4042 will
sink 50 rnA.
The MC4043 monolithic dual line selector con'sists of two high-

speed 400 rnA switches driven by MTTL compatible NOR gates.
Each NOR gate has an individual address input and a common
timing input. The address and timing inputs of the MC4043 can
also be driven directly with standard MTTL decoders such as the
MC4006 and MC4007.

The MC4042 and MC4043 input circuits are the same, but the
output circuitry is different as shown in the device schematics. The
output transistors of both devices have a minimum BVCEX of 15
volts, and are gold doped to increase switching speeds.
Many memory predriver applications employ transformer cou~
piing between the predriver and driver stages. In such designs, large
MC4042

voltage overshoots occur due to the transformer inductance and
high~speed switching currents. The collector of the MC4042 is internally clamped to prevent the collector from exceeding the maximum rated voltage during the switching transitions. The voltage
applied to the diode clamp, pin 5, should be the same or greater
than the collector voltages at pins 1, 7,8, and 14, to prevent the
diode clamp from being forward biased during nonswitching
periods. The output transistor is driven with a conventional totem
pole arrangement to provide active pultup and puUdown.
The collectors of the pullup transistors of the MC4043 are available at pins 1 and 7. An external load resistor to VCC must be
provided. This reduces power dissipation of the package and provides a means by which the speed of the device can be varied by
changing the value of the pullup resistance.
The internal decoding circuitry of the MC4043 is such that both
switches can be turned on at on'e time. However, due to power
limitations, care must be taken to ensure that only one switch is
turned on at anyone time.
The MC4042 and MC4043 can provide a memory Systlllll with
an inexpensive, reliable, fast drive system. They nrl.! also tlsllful 11:->
relay or lamp drivers, high fan-out gates, and MOS drivE~rs.
MC4042 AND MC4043

TRUTH TABLE
(One gate only)

Vee 2
5
VCC=PIN4
GND = PIN 10
SUBSTRATE = PIN 3

Al

B

CI

0
0
1
1

0
1
0
1

0
1
1
1

MC4043
A1

~++------o

14

GNO
10

Collectors of Output Transistors:
Gate 1 = Pin 1
Gate 2 = Pin 7

Input Loading Factors:
A=1,B=4
Total Power Dissipation = 120 mW typ/pkg
Propagation Delay Time"" 15 ns typ

Input Loading Factors:

GND
10

A = 1, 8 = 2

Total Power Dissipation = 70 mW typ/pkg
Propagation Delay Time = 20 ns typ

SCHEMATIC (Yo OF DEVICE SHOWN)

SCHEMATIC (y, OF DEVICE SHOWN)

Vee

Vee
4 k

4 k

e

1.14 k

____-~---IoConnect pins to Vee through a 75-ohm resistor.

•

...:i'o
:::l

t:

m

a.

MC4042F ,L,P. MC4043F ,L,P (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

•

12 Vdc

"The coax delays from input to scope
and output to scope must be matched.
R2

A.~--~---------,

The scope must be terminated in 50ohm impedance. The 950-ohm resistor
and the scope termination impedance

R3

constitute a 20: 1 attenuatar probe.
The 4.95 k ohm resistor and the scope
termination impedance constitute a
100: 1 attenuatar probe. Coax shall
be CT-070-50 or equivalent.

BO-4r~----------4-~~/

Two pulse generators

I

are required to provide

I

the waveforms shown.

t+
6.0 ns

t-

6.0 ns

2.5 V
Pulse A
50

----~~~~~~~~~~~g~~
300 ns

t- "" t+ '= 6.0 ns max
PRF = 1.0 MHz

50 ns

,-,=--2.5 V

PW: Pu Ise A = 300 ns
Pulse B = 200 ns

R

MC4042

R1
R2
R3

All resistances

In

Pulse B

------~~~==~~~~==g~~
6.0 ns

MC4043

950
4.95 k
400

CT = 25 pF = total parasitic
capacitance, which includes

950
4.95 k

probe and wiring capacitances.

30

ohms,

200 ns

TP out

-----====='-===

± 1.0%

MC4042 TYPICAL SWITCHING TIMES
FIGURE 2 - TURN-OFF DELAY TIME versus TEl

FIGURE 1 - TURN-ON DELAY TIME versus TEMPERATURE

16

20

..s"
UJ

19 -

Vee

=

UJ

5.0 Vdc

:;

:;

i=
>-

«
..J

18

Cl
Z

II:

::J
l-

16

~

UJ

..-/
I-""

,/

./

- l o u t = 50 rnA, /

15

/ I out

,.-

=

30 rnA-

~

12

Z

11

II:

~

-

::J
f-

~

10

25

:;

.

TA 25 0 C -

16

""-..

I

25

75

50

FIGURE 4 - TURN·OFF DELAY TIME versus
POWER SUPPLY VOLTAGE
14

..........
.........

0

Z

I"--.

II:

I---

~o.

4.5

r--

TA ~ 25 0 e -

:;

I""--.

lout = 30

..J
UJ

lout = 50 rnA

..........
15 I"--.

UJ

«

.........

UJ

i>

--lout = 50 rnA

I

i=
>-

......

«
..J

14

--~

I--

C

"-

UJ

::J
l-

f..--""

~

..-/

T A, AMBIENT TEMPERATURE (oe)

17

..s

z

f..--

o

75

50

FIGURE 3 - TURN-ON DELAY TIME versus
POWER SUPPLY VOLTAGE

Cl

lout = 30 rnA

9.0

o

-

13

T A, AMBIENT TEMPERATURE (oC)

i=
>-

5 .0

ee

14

Cl
u.
u.

o

./

"..-

14
13

..J

,/

i>

~o.

«

./

UJ

o
Z

>-

./

17

-0 1 ldC

15

I-

./

rn~

--

-

5.0

Cl
u.
u.
0

!--.

-

Z
a:

........

.......... lou~ =

13

......

r----

--

12 I - - · I out

::J

~

50 ,;;;-

36

-

rnA

.-

----

+--

r--

f-

+

"

t--

Vce, POWER SUPPLY VOLTAGE (VOLTS)

t---..

~o.

5.5

4.5

5.0
Vee, POWER SUPPLY VOLTAGE (VOLTS)

MC4042F ,L,P, MC4043F ,L,P (continued)

MC4043 TYPICAL SWITCHING TIMES
FIGURE 5 - PROPAGATION OELAY TIME versus
PULLUP RESISTANCE (Pins 1 and 71
35

r-

w
::;
j:

23

_l

I
IOL - 400 mA

w

V
tpd·

Z

o

~

.«o
..

20

V

V

20

..........

Cl

..........

15

,;

10

_I""""

18

I---

17
16

o

100

50

o

200

150

TA - 25 0 C

j:

>-

:3w

17

Q

z

o

j:

«
Cl
«

16

a:

15

..
..o

7

E

L

~

75

50

21

.--.,-------r-,.--,---,--, ....

w

....... TA· 25°C

j:

>-

/

«

oJ

w

o
z
2
f«
Cl
«
o

r-

Tr·T··

IOL - 400 mA

::;

/'"

~t;-

-tpd+

.......
19r---r--i---t~~---r--i---t---r--i--~

..

..
a:

=

,;

..0.

~

/'

...... 1""""

,.-

FIGURE 8 - PROPAGATION OELA Y TIME versus
POWER SUPPL Y VOLTAGE
o

Vcc = 5.0 Vdc

/'

TA. AMBIENT TEMPERATURE (DC)

FIGURE 7 - PROPAGATION OELAY TIME versus
COLLECTOR CURRENT

18

L

25

PUj,LUP RESISTOR (OHMS)

w
::;

•

L

~

.....-

-

tpd+

II:

..0.

t p d/

19

/" ~

.......

.,.., L

21

V

25

Q

r-- I~L - ~OO ~A
r-- VCC = 5.0 Vdc
r--

22

30 f-- VCC = 5.0 Vdc
f-- TA = 25 0 C

>«
oJ

FIGURE 6 - PROPAGATION OELAY TIME
versus TEMPERATURE

,;

lool~
~
~
~
~
IC. COLLECTOR CURRENT (mA)

~

..0.

__ __

16~~__~~__~__L-~-_ _~r--~~
~=5.0

4.5

5.5

VCC. POWER SUPPLY VOLTAGE (VOLTS)

OUTPUT VOLTAGE VARIATIONS
FIGURE 9 - MC4042

FIGURE 10- MC4043

2
2
OSCILLOSCOPE

PW = 200 ns
V H -3.5V

CJ: = 25 pF = total para-

V L - Q.4 V

sitrc capacitance, which
includes probe and

Pin3=GND
Pin 5 = 12 Vdc

wiring capacitances.

c,.

n.

= 25 pF = total parasitic
capacitance, which inctUdes

PW = 400
VH-3.5V

probe and wiring capacitances.

VL-O.4V
Ground Pin 3 (substrate)
Diode PIV

f-

~

f:::l

=::

,15 V

5:

E
w
Cl

o «
~
00

.)

> >
25
TA. AMBIENT TEMPERATURE (DC)

T A. AMBIENT TEMPERATURE (DC)

75

MC4042F ,l,P, MC4043F ,l,P

(continued)

Figure 11 illustrates a typical core memory driver/selector
using MC4042 and MC4043 devices. The source circuit for the X
or Y drive line consists of an MC4042 predriver transformer

TYPICAL APPLICATION

coupled to a fast high-current transistor. The sink circuit is the
MC4043 line selector. The source and sink circuits are. used in
pairs and are arranged to permit bipolar currents to pass through a
selected drive line. Supply voltage and resistor values are determined
by system requirements.

FIGURE 11 - X or V DRIVE SELECTION MATRIX

NOTE: Stack Bias Resistors are omitted
2N3444

}\ MC4007

'·of·4
• DECODER
ENABLE
2·BIT ADDRESS {

y

03

.- -----,

1}S; MC4043I
I

,-------.
L ___ ~~
1- - - - - - ,

Ir-

2 .JI
____

I
I
I
I

I

L

IX or Y DRIVE LINE
I

I
I

I

X or Y DRIVE LINE

...l

I

.,

I
I
I

I
I
I

L J

[~-_-_-~-jr---"""-o+V

CONTROL
INPUT
AND
TIMING
WRITE

r---~---+-----------~---~-o+V

READ

r--' r---'

:I ::
I I

lI

L_2j L.:..3J
}\ MC4007

'·of·4
DECODER

x

r-.,

I

I

I

I

I

I

I

ENABLE
2·BIT ADDRESS {

I-'
I

I
21
L. __ I

I

I

I
I

1
31

L.. _...J

MC4300/MC4000 series

PHASE-FREQUENCY
DETECTOR

MC4344F,L*
MC4044F, L, P*
This device contains two digital phase detectors and a charge pump
circuit which converts MTTL inputs to a de voltage level for use in
frequency discrimination and phase·locked-Ioop applications.

The two phase detectors have common inputs. Phase-frequency detector 1 is locked in (indicated by both outputs high! when the negative
transitions of the variable input (VI) and reference input (RI) are equal
in frequency and phase. If the variable input is lower in frequency or

lags in phase, the U 1 (up! output goes low; conversely the D 1 (down!

Amplifier

9

~

8

Output

output goes low when the variable input is higher in frequency or leads
the reference input in phase. It is important to note that the duty cycles
of the variable input and the reference input are not important since
negative transitions control system operation.
Phase detector 2, on the other hand, is locked in when the variable

input phase lags the reference phase by 900 I indicated by the U2 and D2
outputs alternately gOing low with equal pulse widths). If the variable
input phase lags by more than goo, U2 will remain low longer than 02,
and, conversely, if the variable input phase lags the reference phase by
less than gOO, 02 remains low longer. In this phase detector the variable
input and the reference must have 50% duty cycles.

Vee = Pin 14
GND= Pin 7

Input Loading Factor:

The charge pump accepts the phase detector outputs (U1 or U2
applied to PU, and 01 or D2 applied to PD! and converts them to fixed

RI, VI = 3

Output L~ading Factor (Pin 8)

= 10

amplitude positive and negative pulses at the UF and OF outputs respectively. These pulses are applied to a lag-lead active filter, which incorporates external components, as well as the amplifier provided in the

Total Power Dissipation = 85 mW typ/pkg
Propagation Delay Time = 9.0 ns typ
(thru phase detector)

MC4344/4044 circuit. The filter provides a de voltage proportional to
the phase error.

PHASE DETECTOR
The phase detector portion of this device is constructed using low
and high-level gates interconnected 8S shown by the logic diagram.

LOW-LEVEL "NAND" GATE

HIGH-LEVEL "NAND" GATE

Vee

:j: Diode used only
when input is
connected to external point.

AMPLIFIER

CHARGE PUMP
Veeo-------~--------~----------~--------~
1 k
3.9 k

Output

..__-_--08
PO
110--_....-'

1 k

:~~----------------~Ud'5
*F suffix = TO-SS ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-, 16 plastic dual in-line package (Case 605).

MC4344F,L , MC4044F,L,P (continued)

•

INPUT
STATE

ELECTRICAL CHARACTERISTICS

UF

PU
Charge

9

Pump
PO
11....---

PhaseFreq
Detector

U

Amp",;e,

5

4

OF
r-'10

0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0

0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0

OUTPUT
U1 01 U2 02

x
X
X
X

x
X

X
X
X
X

0
0
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
1

X

x

1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1

X
X
X
X

TRUTH TABLE

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

This is not strictly a functional
truth table; i.e., it does not show all
possible modes of operation. It is use~
ful for de testing.

1. X indicates output state unknown.
2.

U1 and 01 outputs are sequential;
i,e" they must be sequenced in
order shown.

3. U2 and 02 outputs are combinational; i.e., they need onlv inputs

shown to obtain outputs.

8

Output

~

TEST CURRENTIVOL TAGE VALUES

., Tnt

:-~: _2~:;~_D:~'~; {;~1'~ ~ ~ ; ~'1~! ~ ;.T!7:'M!~l~ ~1'!~ !1!~Hl':! ~!~i!I;!"!I!D! 'A! V!lLl1VI!H!V!F!V!R!ViRiH!Vi-!'!V!C(C!V!~!L1V!C!CHl
~

___
r

INPUT
RI VI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15,
16
17

~C4344

)

+25°C

{+::~ ~~ =:::

MC4044

+1EiiOc

MC4344 Test Limits

Pin
Unci.

Characteristic
"PUI
Forw.-dCurrent

-55Oc

+25Oc

+l25 o C

MC4044 Test Limits
+25o C
+75Oc
MM Min Mu

oOc

Symbol

'F

Leakage Current

,

-

-4.8
-4.8

-

-4.8
-4.8

-

-4.8
-4.8

"1

-

-1.6

-

-1.6

-

-1.6

3
4

-

120
120
5.0
40

-

120
120
5.0
40

-

120
120
5.0
40

3

"
"

Breakdown Voltage

-

-

-4.8
-4.8
-1.6
120
120
5.0
40

Clamp Voltage

-

-1.5
-1.5

VOL
VOH

1.0 -10 0.002 1.1

1.8 0.4

0.002 0.9

1.8 0.4

20 -1.6

IOL 10Hl

IOH2

lin

lOlA

VIL VIH VF
-

-

1

-

-

3
11

6

2.4

4.5

5.0

1.5

Vd,

-

2.5
2.5

0.4
-

2.5

-1.5
-1.5

-

-

2.5
2.5

4.15

+

-

-

2.5

Vdc
Vde

-

-

2.5

2.4

0.4

5.25

VR VRH Voul Vce VCCL VCCH

14
14
4
14

-

2
13
2
13

~H

Short·CircuitCurrenl

Leail;lJ!IBCurrent

2

-

"

1

-

3

2.4
U

-

2.4
14

-

2.4
2.4

U

-

U

-

U

U

-

U

-

U

"

VOL
VOH

2
13
2
13
2
13
2
13

2

0.4

VCE

U

_

2.5
-

~

-

U

U

'0

Leakage Currant

IOLK

"0

2.5

-

2.5
U

-

U

U

8

1,3

13

- =

We

Vdc
Vde

0.4

Vdc
Vdc
Vdc

-

~

-

_

U

U

-

U

-

U

2.4

2.4
2.4
2.4
2.4
-20

2.4

2.4

-

-65

2.4

-

2,'
2.4

-

-20

-

2.4
2.4

-65

2.4
-20

-

-65

-

2.5

-

2,S
2.6

2.5
2.5
2.6
2.5
-20

2.5
2.S

-

2.5
2.S

-

2.5

-65

2.5
-20

-

2.S

-65

-

2.5
2.5
2.5

-

2.5

-

2SO

250

"

250

8

2

1
1
1,3

-

13

',3

-

"

2

-

-20

-65

fA~c

250

250

+

+

+

+

"

120
5.0

40

-

120
5.0

-

120
5.0

-

3

~

-

+
-

120
5.0

-

"
13
2
13

1,3
1,3

3
3

3

-

-

-

1
,

-

1,3

-

-

3
',3

1

14
14
14
14

1,3

',3
3

14
1

3

Vdc

-

+
14

-

1
1

+

-

11

Used 10 ehange pawer supplV yoltage
frompreviQu,tet!.

14
-

2,7
6,7
7,12
7,13

-

4,7

-

"

120 Adc
5.0 ~tk

40

Tha outputs of the dev,cemvstbetestedbysequencongihrough the,nd,cated
input states according to the truth tabl, and runctionaldiagram. All input,
power supplV lind ground voltages must be maintained betWeen tests unless
otherwise noted. ProcedurBli identified by ,double asterisk ( •• ) in the Symbol
column are n9Cl!$l.-V to changEI the nate of the sequenlial logic.

-

3
13

-

14
14
14
14
14
14
14
14
14
14
14
14

-

3

3

0.8
120
6.0

14

3
3

',3

1.5
0.5

1

1,3
1,3

'1,3

0.8
10

-

Vdc
Vdc

Vdc
Vdc
Vdc
Vdc

7

14
14
14
14
14
14
14
14
14

1

',3
',3
13

-

:':+++++++++++++
2

3

_

0.4

2.5
2.5

2.4

5,7

14
14
1,3
1,3

1
1

0.4

10

Output Current

Po_Requirements
(Total Oavlcll
PowerSupplvDrain

2.5
15

0.4

6
12
COllector·Emitter
Voltage
Qutp\ltVoltagEI

-

-

2.5

7
7

-

14
14

-

12

Vd,
Vdc

2.5

2,S

2

~H

2,S

0.4

2.4

"
2

IOLK

2.4
0.4

13

VOL

'SC

2.4

Pulse
1

-

1,3

VOH
VOL
VOH

5.25

1

3

Vdc

12

VOH
VOL

:::

2.5

3

3
1,3
VOH
VOL

~::

1.5

1

-

-

0.4

6
12

-1.0

~:: ::~ ~:~~: ~::

TESTCURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:

S*

Output (Not, "
OutllutVoltage

1.0 -10

-

1

3

20 -1.6

10

::::

8
14

7."7

MC4344F,L , MC4044F ,L,P (continued)

APPLICATIONS INFORMATION
Figure 1 shows the MC4344/4044 in a phase-locked loop with
the following features:

1. Zero ~ error between the reference frequency and the
output of the divide-by-N feedback, achieved because phasefrequency detector 1 locks negative edges in the system;
2. Adjustable channel spacing. achieved by changing the pre-

FIGURE 1 - PHASE-LOCKED,
FREQUENCY SYNTHESIZER LOOP

scaling factor (7 P) when generating the reference frequency;
3. Digitally programmed tuning of the output, in multiples of

the reference frequency, accomplished by changing N in the
divide-by-N chain in the feedback loop.

iMC4344i4044:- - - - - - - - - - - - - - - - - -1
I

VCC

I

I
5

1 k

R1

C1

Charge
Pump

·The resistors, capacitor, and FET
are external to the M C4344/4044.
Values of R 1, R2, R3, and Cl are
determined by operating frequency of interest.
1.4 V
R4=---lOSS

I
1

R3

I
I
1

I
I
8 1

I

I

I
_
I
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..1

-TN

L-__________________ Programmable
Counmr

r-------------------------------~

MC4316/4016
MC4318/4018

Figure 2 shows phase detector 2 of the MC4344/4044, which
operates as a correlation detector, used in a phase-locked loop.
There are two differences between this system and that shown in
Figure 1. First, the VCM output,when locked in,lags the reference
by 900 . Second, since the correlation detector integrates the product of its two inputs over each cycle, it can handle signals in a
high-noise environment. This loop is sensitive to harmonics, therefore care must be taken to limit the frequency range of the VCM.

FIGURE 2 - PHASE-LOCKED,
CORRELATION DETECTOR LOOP

rMC4344/4044"; - - - -- - - -- -- - - --

Refere~

6

I

Note: Noise in this system is
the jitter of each pulse
around its center.

*The resistors, capacitor, and FET
are external to the M C4344/4044.
Values of Al, R2, A3, and C1 are
determined by operating frequency of interest.

V~

1
1

5

11

--~

~------,
1 k

R1

:

I

I
R3

C1

Charge
Pump

I

I
I
I

L ___________________- ______

1.4 V

R4=---lOSS

..1I

-TN

'-________________--1

Programmable
Counter
I-__________
MC4316/4016
MC4318/4018

~

__________________.....J

•

MC4344F,L , MC4044F ,L,P (continued)

APPLICATIONS INFORMATION (continued)

II

Figure 3 depicts the MC4344/4044 in a system used to generate
a slave clock pulse with its negative edge locked to the negative

edge of the master clock, but with adjustable pulse width. The
pulse width of the slave clock pulse is controlled only by the monostable multivibrator, which is triggered from the negative edge of

FIGURE 3 - SLAVE CLOCK
PULSE GENERATOR

an input pulse.
The slave clock application is useful when the clock from a
master computer must be slaved to that of a satellite.

Maste

'-

Clock

r

Phase-F requency

Detector
MC4344/4044

Voltage-Controlled
Multivibrator

Retriggerable
lVIonostable Multivibrator
MC9601/B601

MC4324/4024

Maste,~

L

Clock

~:~~~ -----!
(Set by Monostable
Multivibrator)

r--r-.

Slave
Clock

MC4300/MC4000 series

NON-INVERTING
ONE-Of-EIGHT DECODER

MC4048P*

Vee'" Pin 16
GND = Pin 8

3-Bit Binary

15 6

1

Chip

Function 10
Enable

9

Input

Enable
Inputs

324511121413

The MC4048P is derived from the XC171128-bit Read Only Memory_
A 3-bit binary address selects the desired word for the 8-bit output, and
the selected output goes to a logic "1"_ The function enable input, D,
is useful for expansion of the decoding function_ When D is a logic "0"
all outputs are logic "0"_ A logic "1" on D produces a logic "1" on the
selected output_
Features:
Address times < 50 ns
Outputs sink 16 mA
Output capacitance < 7 _0 pF @ 1_5 V

1-of-8 Output

1-0F-64 DECODER
ISelected output is a positive logic "1 "I

TRUTH TABLE (POSITIVE LOGIC)

INPUT

OUTPUT

DCBA76543210
000000000000
000100000000
001000000000
001100000000

010000000000
010100000000

Total Power Dissipation
= 240 mW tvp/pkg

011000000000

011100000000
100000000001

100100000010
101000000100
101100001000
110000010000

110100100000
111001000000
111110000000

ENABLE INPUT TRUTH TABLE IPOSITIVE LOGIC)
E E Q7 06 05 04 03 02 01 00
0
0
1
1

0
1
0
1

1
1
1

1

1
1

1
1
1

1

1

1
1

1
1

1
1
1

1

1
1

1
1
1

FUNCTION ENABLED

REPRESENTATIVE CIRCUIT SCHEMATIC
Word Line 15

Word 15

Bit 7

Word 15

Bit 0

r-------- -,

r-------,

I

I

I

I

r--Y======r=~~~~~I~II[I=!==~+:lr------~~-t: ---~ i

! ~ ______ J L_____ J
I__

I

I
A

0000 I

I

I

I
I

I-

:
Word 0

r-----

:

I Bit 7

--,

I

I

I

I

Word 0

'Bit 0

r---------,
I

I

I

I

I

I
I

B
ROM

Address
Inputs

C

t

: VCC

I

I

I

_.J

_..l

D

•
• p suffix = 16-pin dual in-line plastic package (Case 612).

Links removed if logic "'1" state desired •

VCC

•

MC4048P (continued)

•

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

FAMILY

MC4048
INPUT
LOADING
FACTOR

MC4048
OUTPUT
LOADING
FACTOR

1.0
1.0
0.67
0.7
1.0

10
10
7
7
10
11

MC4000
MC400
MC2000
MC3000
MC7400
MC830

1.16··

Note: Differences in MC4000 series loading factors result from
differences in specifications for each family.
•• Applies only when input is being driven by MDTL gate with 2 k ohm
pullup resistor. Logic "I" state drive. limitations of gates with 6 k
ohm pullup resistors reduce drive capability to fan-out of 3.

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7.0

Vdc

Rating
Supply Operating Voltage Range

Vee

4.5 to 5.5

Vde

Input Voltage

Yin

-1.5 to +5.5

Vde

Operating Temperature Range

TA

o to +75

°e

Storage Temperature Range

Tstg

-55 to +125

°e

ELECTRICAL CHARACTERISTICS (TA = 0 to +75OC)
Symbol

Characteristic
Address Input Forward Current
0V A = 0, Vee = 5.0 Vde)

IF

Enable Input Forward Current
(VE = 0, Vee = 5.0 Vde)

IF

Address Input Leakage Current
(VA = 5.5 Vde, Vee = 5.0 Vde)
Enable Input Leakage Current
(VE = 5.5 Vde, Vee = 5.0 Vde)

IR

Min

Max

Unit
mAde

1.6
mAde
1.6
/tAde
100
IR

Logical "0" Output Voltage
(IOL = 16 mAde, VIL = 0.9 Vde, VIH = 2.0 Vde, Vee =4.75 Vde)

VOL

Logical "1" Output Voltage
(lOH = 0.5 mAde, VIL =0,9Vde, VIH= 2.0Vdc, Vee = 4.75 Vde)

VOH

Power Supply· Drain Current
(Memory Enabled, Vee = 5.25 Vde)
(Memory Disabled, Vee = 5.25 Yde)

-

/tAde
100
Vde
0.45
Vde

2.5
mAde

IpD max
IPDmin

85
55

tA+B+

50

ns

tA~B-

50

ns

tA+B- or
1£+B-

50

ns

tA-B+ or
tE-B+

50

ns

SWITCHING TIMES (VCC = 5.0 Vdc)
Positive Input Address to Positive Output
Negative Input Addresst" Negative Output
Positive Input Address or Enable to Negative Output
Negative Input Address or Enable to Positive Output

IOL = 10 rnA
driving
30 pF

MC4300/MC4000 series
COUNTER-lATCH-DECODER

MC43S0L*
MC40S0L,P*

ADVANCE INFORMATION/NEW PRODUCT

This device is a monolithic MSI integrated circuit combining the functions of an NBCD counter, four-bit latch,
and a seven-segment decoder/driver. The counter advances
on the negative edge of the Clock, subject to control by the
Enable input. The Serial Output is high driving the ninth
count, allowing synchronous or asynchronous counter op·
eration when used in conjunction with the Enable input
and some external gating. The counter Reset places the
counter in a non-N BCD state, turning off the output driver

transistors when transferred through the latch and decoded. This feature gives automatic suppression of leading
zeros in'the display. The latch section admits information
while the Strobe is high and latches the data on the negative edge of the strobe. The seven-segment decoder/
driver provides up to 40 mA drive capability for displays
which require current sinking in the active mode. A lamp
blanking input is provided for intensity modulation. A
lamp test feature is also available.

2

En8'iJie 0 - - - - ,

Lamp

13

High-Current
Drivers

Test

SEGMENT IDENTIFICATION
.10

a

11 b

Decade
Counter

4-81t

7-5egment

Latch

Decoder

9

c

5

d

4 e

Serial

Output

6

f

7

9

L~mp

3

Vee = Pin 16
GND = Pin 8

Blanking
Total Power Dissipation = 450 mW typ/package
Maximum Toggle Frequency
35 MHz typ

=

FUNCTIONAL TRUTH TABLE
INPUT
R
5

FUNCTION

C

E

Lamp Test
Lamp Blanking

X
X
X

X
X
X

X

1

a
a

Reset
Enable

P
l' PI
P2
2
3 P3
4 .P4

5

St.ate
SequencE!

P5

6 P6
P7
8 P8
9
P9
a PIa
1 Pll
Latch
P
7

a
a
0
·0
0

a

0

a

0
0
0

a

X
1

0

a
a
a
a
a
a
0

a
a
a

P = any number of pulses may be applied
P n "=: n pulses on the Clock input
X = Don.'t care
,

*L suffix
P suffix

= 16-pin dual
= 16-pin dual

X
X

1

I
1
1
1
1
1
1
1

1
1
1
1

a

LT

LB

1

X

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

1

a

-

0

0

a

a
a
a
a
a
a

a
a
a
a

0

0

a
0

a
a
a
3.0 V

It-0 V

in~line ceramic package (Case 620).
in-line plastic package (Case 612),

5 0ut
-

0

6

a
1

a
a
a

a

b

a

a

1
1
1
1

a
0
1

a
a
a
a
a
a
1
1

1
1
1

a
a
a
a
1

I
a

b

a
a
a
a

OUTPUT
c
d

e

f

9

a

a

a
1
1
1
1

0
1
1
1
1
1
1

a

1
1
1

1
1
1
1

a
1

a
a
a
a
a
a
a
a
a
a

a
a
I
a
a
1

a
a
a
1
1

a

.,

a

1

0

1

a
1

a
1
0
1
1

~
0

o·

a
1
1

1
1
1
1

a
a
a
0
.'

a
1

a
a
1
1
1

MC4300/MC4000 series
COUNTER-lATCH-DECODER

MC4051P*

•

Advance InforIDation
ative edge of the strobe. The seven-segment decoder/
driver is active high and will source up to 40 mA at a 10%
duty cycle or 15 mA at a 100% duty cycle. A lamp blanking input is provided for intensity modulation. A lamp
test feature is also available.
The output structure of this device is an open emitterfollower configuration whose equivalent circuit is a voltage
source with a relatively small series resistance. Although
this resistance increases when the output is grounded, the
situation is potentially destructive to the device. When the
outputs are in the high ("1") state, they should not be
connected to ground through an impedance of less than
100 ohms.

This device is a monolithic MSI integrated circuit combining the functions of an N BCD counter, four-bit latch,
and a seven-segment decoder/driver. The counter advances
on the negative edge of the Clock, subject to control by the
Enable input. The Serial Output is high driving the ninth
count, allowing synchronous or asynchronous counter operation when used in conjunction with the Enable input
and some external gating. The counter Reset places the
counter in a non-N BCD state, turning off the output driver
transistors when transferred through the latch and decoded. This feature gives automatic suppression of leading
zeros in the display. The latch section admits information
while the Strobe is high and' latches the data on the neg-

2

ErlBbie 0-----,

Lamp

13

Test

High-Current
Drivers

SEGMENT IDENTIFICATION
16 Vee

10.
11 b

9 c
Decade
Counter

4-Bit

7-58Oment

Latch

Decoder

5

d

4 •
6
7
Serial
Output

3

Vee"" Pin 16
GND = Pin 8

Lamp
Blank ing
Total Power Dissipation = 450 mW typ!package
Maximum Toggle Frequency = 35 MHz typ

FUNCTIONAL TRUTH TASLE
FUNCTION
Lamp Test
Lamp Siank ing
Reset

Enibi8

State
Sequence

1
2
3
4
5
6
7
8
9
0

L~C~

C

E

X
X

X
X
X

X
P

Pl
P2
P3
P4
P5
P6
P7
P8
P9
P'O
P"
p

1
0
0
0
0
0
0
0
0
0
0
0
0

INPUT
R
S
X
X

1
0
0
0
0
0
0
0
0

0
0
0
0
0

P = any number of pulses ~ay be applied
Pn = n pulses on the Clock mput
X == Don't care

LT

LB

X

1

X

X
1
1
1
1
1
1
1
1
1

0
0

,
,,
,
0

0
0
0
0
0
0
0
0
0
0
0

0
0

"ou,

1

-

0

0

O.

0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
O·
0
0
0

,

0

0
0
0
0

OUTPUT
c
d

a

b

1

1

1

1

0

0

0

0

0
0
0
1
1
0
1
1

0
0
1
1
1
1
0
0

0
0
1
0
1
1
1
1

0
0
0
1
1
0
1
1
0

,,
,,
0
O'

,

e

f
1

9
1

0
0
0
0
1
0
0
0
1
0
1
0

0

0

0
0
0
0
0
1
1
1
0

0
0

0
0

0
0

0

1
1
1
1
1
0

,, ,, ,
,
,, , ,,, ,
,,
,, ,
1
1
1

3.0 V

SL0 V

.p suffix = 16-pin dual in-line plastic package (Case 612).
This is advance information on a new Introduction and specifications are subject to change,wlthout notice.

0
0

0
0
0

MC4300/MC4000 series

DUAL
MAJORITY LOGIC GATE

MC4062P*
Advance InforIllation
This integrated circuit offers the designer additional
versatility in logic design. When any two or all three
of the inputs are raised to the "1" level, the output
goes to the "1" level. The output, Z, and its comple·
ment, Z, are both available.
AI

Bl

20-~~-;__- l

Cl

ao--4---i__'/

5

ZI

L-______<> 4

Z1
INPUT
A

B

C

0
0
0
0
1

0
1
0

1

0
0
1
1
0
0

1
1

1
1

0

A2130-~~-i__ .~

8

B2120--+~-{__~

Z2

' - - - - - - 0 1 0 Z2

C211o-~~~__~

1
0

1
1

OUTPUT
Z
Z
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
0

Total Power Dissipation = 75 mW typ/pkg
Propagation Delay Time = 20 ns typ (Z Output)

11 ns typ

Vee = Pin 14
GND=Pin 7

(Z Output)

CIRCUIT SCHEMATIC
(112 OF DEVICE SHOWN)

4>

A

1.2 k

4

>

1.2 k

100

0-----.....- - '

Z
B

1

500

>
500

1 k

4k

C

Z
This is advance information on a new introduction and specifications are subject to change without notice .

• p suffix = TO-116 dual in-line plastic package (Case 605).

•

•

INTEGRATED CIRCUITS

MC5400/MC7400 SERIES

.TTl
MC5400/7400 SERIES
INTEGRATED CIRCUITS

INDEX

•

General Information
General Description
Maximum Ratings
Typical Characteristics
Package Description
Definitions
Usage Suggestions

DEVICE SPECI FICATIONS
MC5400/MC7400
MC5401/MC7401
MC5402/MC7402
MC5403/MC7403
MC5404IMC7404
MC5405/MC7405
MC5410/MC7410
MC5420/MC7420
MC5426/MC7426
MC5430/MC7430
MC5440/MC7440
MC7441A
MC5442/MC7442
MC5443/MC7443
MC5444/MC7444
MC5445, MC54145/MC7445, MC74145
MC5446, MC5447/MC7446, MC7447
MC5448/MC7448
MC5449/MC7449
MC5450/MC7450
MC5451/MC7451
MC5453/MC7453
MC5454/MC7454
MC5460/MC7460
MC5470/MC7470
MC5472/MC7472
MC;;5473/lVIC7473
MC7475
.
MC7476
MC5479/lVIC7479
MC9480/MC7480
...
MC25482, MC15482/MC17482, MC27482
MC5483/MC7483
MC5484/iVtC7484
MC5490iMC7490
MC5491 A/MC7491 A
MC5492/MC7492
MC5.493/MC7493
MC5494/MC7494
MC5495/MC7495
MC5496/Mc7496
MC54107/MC74107
MC54121/MC74121
MC54145/MC74145
MC54150/MC74150
MC54151/MC74151

Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate (Open Collector)
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate
Hex Inverter
Hex Inverter (Open Collector)
Triple 3-lnput NAND Gate
Dual4-lnput NAND Gate
Quad 2-lnput Interface NAND Gate
8-lnput NAND Gate
Dual 4-lnput NAND Buffer
BCD-to-Decimal Decoder
BCD-to-Decimal Decoder
Excess Three-to-Decimal Decoder
Excess Three Gray-to-Decimal Decoder
BCD-to-One-Of-Ten Decoder/Driver
BCD-to-Seven Segment Decoder/Driver
BCD-to-Seven Segment Decoder/Driver
BCD-to-Seven Segment Decoder/Driver
Expandable Dual 2-Wide 2-lnput AND-OR-INVERT Gate
Dual 2-Wide 2-lnput AND-OR-INVERT Gate
Expandable 4-Wide 2-lnput AND-OR-INVERT Gate
4-Wide 2-lnput AND-OR-INVERT Gate
Dual4-lnput El

~
I

1.0 - General Description
The purpose of this section fs to provide guidelines for the use

of MC5400/7400 series digital integrated circuits. It is arranged in
three parts: the first containing maximum ratings, typical character-

istics, package descriptions. and definitions; the second a briefly
worded description of recommended design procedures; and the
third a more detailed explanation of the reasoning behind these
recommendations.

GENERAL INFORMATION

MTTL

MC5400/7400 Serie.

to guarantee that anyone limit is not exceeded. For example, a

1.1 - Maximum Ratings
The maximum rating table is perhaps the most important portion of the General Information Section. Failure to observe these
ratings can result in catastrophic device failure. It is important to
note that this rating table does not guarantee that a device will
operate if the values noted are not exceeded-it only states that
exceeding these values may induce failures. Also. it is not enough

maximum supply voltage of 6.5 volts is with in the rating, but may
induce failure if the design is such that input voltage ratings or
maximum junction temperatures are exceeded as a result of the
high supply voltage. The only exceptions to this rule involve currents and voltages applied to input terminals. The table is constructed to allow the designer to limit either current or voltage

to a safe value.

MAXIMUM RATINGS
Value

Unit

4.5 to 5.5
4.75 to 5.25
7.0
-10
-30

Vdc

Rating

Supply Voltage, Operating
Supply Voltage, Continuous

MC5400 Series
MC7400 Series
All Types

Input Forward Current - Continuous

- Pulsed<30 ms

Vdc
mAde

OR
-0.5
-1.5

Vdc

1.5

mAde

5.5
-55 to +125
Oto + 70
-65 to +150
-55 to +125
+175
+150

Vdc

Negative Voltage at Input - Continuous

- Pulsed <30 ms
Maximum Input Reverse Cl;Irrent

OR
Maximum Positive Voltage at Input
Operating Temperature Range
Storage Temperature Range

Maximum Junction Temperature

MC5400 Series
MC7400 Series
MC5400 Series
MC7400 Series
MC5400 Series
MC7400 Series

°c
°c
°c

1_2 - Typical Characteristics
The following summary presents the typical operating char-

acteristics of the MTTL MC540017400 series. Unless otherwise indicated, the parameters are defined for VCC = +5.0 volts
and T A = +250 C.

Switching Threshold

= 1.5 volts nominal

I "put Impedance

High State = 400 kilohms nominal
Low State = 4.0 kilohms nominal
Worst-Case DC Noise Margin

Supply Voltage Operating Range
MC5400 Series = 4.5 to 5.5 volts
MC7400 Series = 4.75 to 5.25 volts
Operating Temperature Range
MC5400 Series = -55 to +125 0 C
MC7400 Series = 0 to +700C

Output Drive Capability
Other Gates IOutput Loading Factor! = 10
Capacitance = 600 pF
Output Impedance
High State = 70 ohms lunsaturated) nominal
Low State = 10 ohms nominal
Output Voltage Swing = 0.2 to 3.5 volts typical
Input Voltage Limits
+5.5 volts maximum
-0.5 volt minimum

High State - 0.400 volt minimum
Low State - 0.400 volt minimum
Power Dissipation

Basic Gate = 10 mW typ/gate
Basic Flip-Flop = 40 mW typ/pkg
Thermal Resistance - Junction To Case (8 JC)
Ceramic Package = 0.090 C/mW
Plastic Package = 0.150 C/mW
Thermal Resistance - Junction To Ambient 10 JA)
Ceramic Package = 0.260 C/mW
Plastic Package = O.ZOoC/mW
Switching Speeds
Average Propagation Delay = IOns per gate typical
.
30 ns per flip-flop typical
Rise Time = 2.5 ns typical
Fall Time = 1.5 ns typical
Flip-Flop Clock Frequency = 30 MHz maximum

GENERAL INFORMATION

MTTL

MC5400/7400 Series

1.3 - Package Description
PSUFFIX

Package type is denoted by a suffix to the part

PLASTIC PACKAGE
CASE 605
TO-116

number as follows:

Suffix
F

Description
Ceramic Flat
Ceramic Dual In~Line
Plastic Dual In·Line

L
P

SEATING

~A\"\~fuf

.L~..Jo::

~ ~ -L~CI~~~ L=~
I

0.090

Imil

imlI

0.015
J!]J!3

Four insulitingstand-offsare provided
To convert inchlSlo millimeters multiply.by 25.4

AItJEDEC dimensions and notes apply

PACKAGE DIMENSIONS

j

0.006
00"

'~:'1~:::]~
L

~~~OOi~I~t=H
~.C3iJ

O.~3

0.006

iil55

0.070

0.095

POINT

if.W5

01145

0.010

PSUFFIX

1

PLASTIC PACKAGE
CASE 612

0.030

U]"/I!

0.055

I~

=11

FSUFFIX
CERAMIC PACKAGE
CASE 607
TO-S6

~:~~

CDTh.dlmenlion is rneuurtd at the Slating planl.
(l)4inllllatingstend-offsarlprovided.

Lead 1 idantified by color dot or by elbow on lead.

To convert inches to millimeters multiply by 25.4

To convert inchas to millimeters multiply by 25.4
AIIJEDECdimansionsandllotasapply

LSUFFIX

LSUFFIX

CERAMIC PACKAGE
CASe 620

CERAMIC PACKAGE
CASe 632
TO-116

t

o
32'
MAX
.290

1..J----C-~____J--.:!70

I!Jjjj

(j)

t~\-[200\O",o:m
-.-----L

0.135

IrnS

~

L ~Lo:m

0115

0.090

0015

ilJlD

if.U2ii

It tiMI lItIing pi_with laadsftrtical.

a:>Lud1 idlntifiedbycolor dot, nou:hInlHd,
ornotchlncenmil:.
To convert inchel to miilimaterJ muhipiy by 25.4

I

r/
O'to15'

SEATING PI.ANE

--6
(9) 9==C::>-[2)

V

=

Vee

= Pin 14 [4)

Gnd "" Pin

7 [11)

1
2
=
B ±cr
Z -3

(7)

B

[3)

Pin MCS400 Test limits
SS to +12SoC
Under
Symbol Test Min Max Unit

~

,8
:s
C')

To complete testing, sequence through remaining inputs.

(5)

.....
.a:=-

8

[8)

(0'

(OH

VIL

TEST CURREtlT /VOLTAGE VALUES (All Temperatures)
Volts
V.2
V.,
V,hO Vee
VIH V,HH
V'hl

Vee,

VeeH

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5,50

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5.25

mA

11 (14)

Characteristic
Input

:s
C')

ELECTRICAL CHARACTER ISTICS

rLA1 OIL

MCS400
MC7400
MC7400 Test limits
o to +70°C
Min Max Unit

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

nO
:::I

.....

Pin 7[11 Jis grounded
for all tests in addiUon to the pins
listed below:

10 ,

10H

VIL

V'H

V,HH

V.,

VR2

Vthl

V'hO

Vee

VeCL

VeeH

Gnd

-

-

-

V

*

-

-

V

B*

Forward Current

IF

A

-

-1. 6

mAde

-

-1. 6

mAde

-

-

A

-

-

B

-

-

Leakage Current

IRI

A

-

40

/lAde

-

40

/lAde

-

-

-

A

-

-

-

-

IR2

A

-

1.0

mAde

-

1.0

mAde

-

-

-

A

-

-

-

-

-

-

V

B*

VOL

Z

-

0.4

Vdc

-

0.4

Vdc

Z

-

-

-

-

-

-

A,B

-

-

V

-

*

VOH

Z

2.4

-

Vdc

2.4

-

Vdc

-

Z

-

-

-

B

-

-

A

-

V

-

*

ISC t

Z

-20

-55

mAde

-18

-55

mAde

-

-

-

-

-

-

-

-

-

-

-

V

A,B,Z*

IpDH

V

-

22

mAde

-

22

mAde

-

-

-

-

-

All
Inputs

-

-

-

-

V

*

IpDL

V

-

8.0

mAde

-

8.0

mAde

.

.

-

-

-

-

-

.

.

-

-

V

All Input.

Pulse
In

Pulse
OUI
*

Output
Output Voltage

Short-Circuit Current

Power Requirements
(Total Device)
Power Supply Drain

Switching Parameters
Turn-On Delay

tpd_

A,Z

-

15**

ns

.

15**

ns

A

Z

-

B

-

-

.

-

-

V

-

-

Turn-Off Delay

tpd+

A,Z

-

22**

ns

-

22**

ns

A

Z

-

B

-

.

.

.

.

V

-

-

.

Ground inputs, to gates not under test.
**Tested only at 25° C.
tlonly one output should be shorted at a time.

I

.

s·
t:
CD

Cl.

MC540017400 series

QUAD 2-INPUT "NAND" GATE
WITH OPEN COLLECTOR

MC5401 • MC740 1

Add Suffix F for TO-S6 ceramic package (Case 607).
Suffix L for TO-1 16 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7401 only.

This device consists of four 2-input NAND gates
with no output pullup circuits. It can be used where
the Wired-OR function is required, or for driving discrete components.

CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN

•

Vee

r1

1.4 k

4k

z

1 k

Positive Logic: Z
Negative Logic: Z

Gnd

Vee ~ Pin
Gnd

~

Pin

Pin

[lJ
Z - 1 [3J
2=
±[y
B
[2J 3
[6J
[5J
[7J : = = L } - 4
[9J
[10J : = = L } - 1 0 [8J
[12J 1 1 = = L } 13 [14J
[13J 12

A
B

DIL
Pkg

Pkg
LA
Pin

= ',A"";'"B
= A+"B

Input Loading Factor = 1
Output Loading Factor = 1 0
Total Power Dissipation = 40 mW typ/pkg

14 [4J

Propagation Delay Time

7 [11 J

= 35

os typ

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
TP out

Vee
+5.0 Vdc

; - - -.....- - - - - - 3 . 0 V min

'1<-----1.5 V
' -_ _ _ 0 V max

PULSE
GENERATOR

2.4 V min

1.5 V

t+=12nS}
.
= 6.0 ns 10% to 90% POints

t-

PRF ~ 1.0 MHz
Duty Cycle = 50%

PW

~

0.51"

Z·out~50

.n
R L = 400 ohms for tp.d- test.
4.0 k ohms for tpd+ test.

CT

= 15 pF = total

p@rasiticcapacitance,which includes probe. wiring, and load capacitances.

High impedance probes ( >1.0 megohm) must be used for tests.

s:

FLAT] OIL
[ Pkg
Pkg
Pin
Pin

2=tcY-

[IJ

3

[2J
V=

vee

=Pin 14 [4J
Gnd = Pin 7 [111

[6J
[7J
[9J
[10J

C"')
~

z

B

1

:==:[J-4
:==:[J-,0
"==:[J-

[12J
[13J 12

ELECTRICAL CHARACTERISTICS

0'1

o
....
s:
C"')

[3J

[5J

'"

~

[8J

o....

13 [14J

Test procedures are shown for only one
gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

Pin MC5401 Test limits
Under -55 to +125°C
Test Min Max Unit

MC5401
MC7401
MC7401 Test limits
o to +70°C
Min Max Unit

0.4

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
Volts
V,H V,HH
V.,
V.2
V'hO VCEX Vcc
V'hl
5.5
5.0
2.4
4.5
5.0
2. a
0.8
5.5

16

0.4

2.4

IOL

VIL

V,H

-

A

Characteristic
Input

Symbol

Forward Current

IF

A

-1. 6

mAde

-1. 6

mAde

Leakage Current

IRI

A

40

,uAdc

40

!-lAde

IH2

A

1.0

mAde

1.0

mAdc

VOL

Z

0.4

Vdc

0.4

Vdc

I CEX

Z

0.25

mAde

0.25

mAde

IpDII

V

-

22

mAdc

22

mAde

IpDL

V

-

8.0

mAde

8.0

mAde

mA
10L

VIL

16

5.5

4.5

5.0

2.0

0.8

5.5

5.0

!

-

V,HH

V. l

V.2

V'hl

V'hO

VCEX

Vec

Il

VCCH

4.50

5.50

4.75

5.25

Pin 7[11] is grounded
for all tests in addi~
tion to the pins
listed below:

VCCL

VCCH

Gnd

-

V

*

V

B*

V

B*

-

*

A
A

::;'

C
-6
1:=C>-S
11
12~

A

13~

z

B

Positive Logic: Z =
Negative Logic: Z =

1 k·

Gnd

Input Loading Factor

=1

Output Loading Factor

Vee
Gnd

= Pin
= Pin

:A"...-s
A+B

= 10

Total Power Dissipation = 40 mW typ/pkg
Propagation Delay Time = 35 ns typ

14
7

Device available only in dual in-line package.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
TP out

Vee
+5.0 Vdc

'1.-----1.5 V
1.5 V

, . - -....- - - - - - 3 . 0 V min
' -_ _ _ 0 V max

2.4 V min

Duty Cycle = 50%

PW = 0.51l"
Zout~50

.n
R L = 400 ohms for tpd_ test.

4.0 k ohms for tpd+ test.
CT

= 15 pF = total

parasitic capacitance, which includes probe, wiring, and load capacitances.

High impedance probes ( >1.0 megohm) must be used for tests.

:=±cY-

v

= Vee""

:=0-

Pin 14

Gnd = Pin

S

n
~
o

3

6

.W

9~8

7

s

10~

(")

12~~11

~

~

13~

8
8:::I

ELECTRICAL CHARACTERISTICS
- Test procedures are shown for only one

gate. The" other gates are tested in the same

mA

manner. Further, test procedures are shown
for only one input of the gate under test.

To complete testing, sequence through remaining inputs.

Characteristic
Input

Pin MC5403 Test limits
Under -55 to +125'C
Symbol Test Min Max Unit

MC5403
MC7403
MC7403 Test limits
o to +70'C
Min Max Unit

TEST CURRENT /VOLTAGE VALUES
Volts
VR,
VR2
V'H V'HH
V'h'

(All Temperatures)

:::!".
:::I

I::

'Ol

VIl

V'hO

VCEX

16

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.5

5.0

4.50

5.50

16

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.5

5.0

4.75

5.25

Vcc

VCCl

a

VCCH
Pin 7 is grounded for
all tests in addition

to the pins listed

TEST CURRENT !VOlTAGE APPLIED TO PINS LISTED BELOW:

below:

'Ol

VIl

V'H

V'HH

VR,

VR2

V,h'

V'hO

VCEX

Vcc

VCCl

VCCH

Gnd

Forward Current

IF

A

-

-1. 6

mAde

-

-1. 6

mAde

-

A

-

-

B

-

-

-

-

-

-

V

*

Leakage Current

IRI

A

-

40

/lAde

-

40

}.LAde

-

-

A

-

-

-

-

-

-

-

-

V

B*

IR2

A

-

1.0

mAde

-

1.0

mAde

-

-

-

A

-

-

-

-

-

-

V

B*

VOL

Z

-

0.4

Vdc

-

0.4

Vdc

Z

-

-

-

-

-

A,B

-

-

V

-

*

ICEX

Z

-

0.25

mAde

-

0.25

mAde

-

-

-

-

A

-

-

B

Z

-

V

-

*

IpDH

V

-

22

mAde

-

22

mAde

-

-

-

-

-

All
Inputs

-

-

-

-

-

V

-

IpDL

V

-

8.0

mAde

-

8.0

mAde

-

-

-

-

-

-

-

-

-

V

A,B*

B

-

-

-

-

-

V

-

-

-

Output
Outp:ut Voltage

I

Output Leakage Current

Power Requirements
(Total Device)
Power Supply Drain

Switching Parameters
Turn-On Delay

tpd_

A,Z

-

15**

nB

-

15**

nB

-

-

Pulse
In

Pulse
Out

A

Z

!

I

Turn-Off Delay

tpd+

A,Z

Ground inputs to gates not under test.
**Tested only at 25° C.

-

45**

nB

-

45**

nB

A

Z

B

-

-

-

-

-

-

V

-

-

-

MC5400/7400 series

'\

HEX INVERTER

'-_ _ _ _ _- - - - - - 1

MC5404 • MC7404

Add Suffix F for TO·86 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7404 only.

CIRCUIT SCHEMATIC

1/6 OF CIRCUIT SHOWN

•

rLAT]
Pkg
Pin

Vee

100

OIL
Pkg
Pin

[11

1~2

[141

[31

3--\)0---4

[21

[51

5--\)0---6

[61

[71

9--\)0---8

[81

A

[91 1 1 - - \ ) 0 - - - 1 0 [101
Z

[131 1 3 - - \ ) 0 - - - 1 2 [121

1 k

Positive Logic: Z~A

Gnd

I nput Loading Factor == 1
Output Loading Factor == 10
Total Power Dissipation"" 60 mW typ/pkg

Propagation Delay Time == 13 ns typ

Vee ~ Pin 14 [41
Gnd ~ Pin 7 [111

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
Vee
+5.0 Vdc

, . - -...- - - - - - 3.0 V min
400

'\-----1.5 V

oV

max

2.4 V min

PULSE
GENERATOR
t+ = 12 ns }
.
t- = 6.0 ns
10% to 90% pOlOts

PRF

~

1.0 MHz

Duty Cycle = 50%
PW = 0.5J,ls
Zout~50

MMOS150
or Equiv

1_

50

MM07000
or Equiv

n
CT "" 15 pF = total parasitic capacitance. which includes probe. wiring, and load capacitances.
The coax delays from input to scope and output to scope must be matched. The scope must
be terminated in 50-ohm impedance. The 950-ohm resistor and the scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.

1.5 V

rFLAT]
Pkg
Pin

[lJ

v

s:
("')

ELECTRICAL CHARACTERISTICS

DIL
Pkg
Pin

Test procedures are shown for only one

1~2[14]

the same manner.

[3J

3-{:»--4

[2]

[5]

5-{:»--6

[6J

8

[8J

U1

inverter. The other inverters are tested in

~

o

.~

s:("')

......

~

~VCC ~

Pin 14 [4]
Gnd '" Pin 7 [111

o
-{:»--

~

[m

[OH

VIL

TEST CURRENT jVOlTAGE VALUES (All Temperatures)
Volts
VIH VIHH
V. 2
V. I
V,hO VCC
V'h I

VCCL

VCCH

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5.50

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5. 25

mA

10 [10J

MC5404
MC7404
MCl 404 Test limits
o to +70'C
Min Max Unit

12 [12J

Characteristic
Input

Symbol

Pin MC5404 Test limits
Under -55 to +125'C
Test Min Max Unit

Forward Current

IF

A

Leakage Current

IRI

A

IR2

A

VOL

Z

-

V OH

Z

2.4

ISC t

Z

-20

IpDH

V

IpDL

V

-

-I. 6

mAde

40

-

-I. 6

mAde

pAde

40

vAde

1.0

mAde

1.0

mAde

0.4

Vdc

-

0.4

Vdc

Vdc

2.4

-55

mAde

-18

33

mAde

nO
:::l
,...
S·

c

C1l

Pin 7[11] is grounded
for all tests in addi-

tian to the pins
listed below:

TEST CURRENT jVOlTAGE APPLIED TO PINS LISTED BElOW:
10L

10H

-

V"

V,HH

V,H

A

V. I

V. 2

-

-

V'h

I

V'hO

Vce

VCCL

A

-

A

VCCH

Gnd

V

*

V

*

V

*

Output
Output Voltage

Short-Circuit Current

mAde

33

mAde

-

Z

Vdc

-55

A

Z

-

-

V

*

A

V

*
V

A,Z*

-

V

-

-

-

V

All Inputs

-

V

Power Requirements
(Total Device)
Power Supply Drain

All

Inputs
12

mAde

-

12

Switching Parameters
Turn-On Delay

t pd _

A,Z

Turn-Off Delay

tpd+

A,Z

-

15**

ns

22**

ns

-

-

mAde

Pulse
In

Pulse
Out

15**

ns

A

Z

-

22**

ns

A

Z

-

L

*Ground inputs to inverters not under test.
**Tested only at 25°C.
t'Only one output should be shorted at a time.

____

-----'--

*

V
- -

'------

*
..

0.

MC5400/7400 series

HEX INVERTER
(Open Collectorl

MC5405 • MC7405

Add Suffix F for TO·S6 ceramic package (Case 607).
Suffix L for TO·116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7405 only.

This device consists of six independent inverting
gates with no output pullup circuits. It can be used
where the Wired-OR function is required, or for driving
discrete components .

CIRCUIT SCHEMATIC
1/6 OF CIRCUIT SHOWN

•

Vee
rLAT]
Pkg
Pin

4k

DIL
Pkg
Pin

[11

1~2

[141

[31

3--{)o-4

[21

[51

5--{)o-6

[61

[71

9--{)o-S

[SI

1.4 k

A

Z

[91 1 1 - - { ) o - 1 0 [ 1 0 1
1 k

[131 1 3 - - { ) o - 1 2 [121

Positive Logic:

Z=A

Gnd
Input Loading Factor = 1
Output Loading Factor :=:: 10
Total Power Dissipation:=:: 60 mW typ/pkg
Propagation Delay Time = 35 ns typ
0

Vee

= Pin

14 [41
Gnd = Pin 7 [111

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
TP out

Vee
+5.0 Vdc

, - - -.....- - - - - - 3.0 V min
,...----1.5V

' - - - - - - 0 V max
. PULSE
GENERATDR

2.4 V min

1.5 V
t+=12nS}
t- = 6.0 ns
10% to· 90% points
PRF = 1.0 MHz
Duty Cycle = 50%

-l-~~=::::!~:I:::== ~':dV

50

PW = 0.5 III
Zout~50

n
RL

= 400 ohms for

tpd_ test.

4.0 k ohms for tpd+ test.

CT

= 15 pF

= total parasitic capacitance,

whic~ inclu~es

probe, wiring, and load capacitances.

High impedance probes ( >1.0 megohm) must be used for tests.

max

f

FLAT]

s:

DIL

Pkg
Pin

Pkg
Pin

(")

c.TI

[l)l~2[14J

~

o

.c.TI
[3J

3--{:>o---4

[2J

s:

[5J

5--{:>o---S

[6J

"

(")

v = Vee = Pin 14 [4J
Gnd=Pin

~

o

7 [11]

[7J

9--{:>o---S

--{:>o---

c.TI

[SJ

12 [12J

Pin MC5405 Test Limits
55 to +125'C
Under
Test Min Max Unit

nO

10 l101

10L

VeEX

VIL

16

5.5

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5.50

16

5.5

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5.25

Pin 7[11 J is grounded
for all tests in adctitian to the pins
listed below:

Vcc

VCCL

VCCH

Gnd

-

-

V

*

V

*

V

*

mA

MC5405
MC7405
MC7405 Test Limits
o to +70'C
Max Unit
Min

IOL

VCEX

VIL

-1. 6

mAde

-

-

A

40

!lAde

1.0

mAde

0.4

Vdc

Characteristic
Input

Symbol

Forward Current

IF

A

-1. 6

mAde

Leakage Current

lRI

A

40

J.lAde

IR2

A

1.0

mAde

VOL

Z

-

0.4

Vdc

-

ICEX

Z

0.25

mAde

0.25

IpDlI

V

IpDL

V

-

~

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
VR2
VIH VIHH
V.,
V'hl
V'hO Vec

!:t.
~

c

VCCL

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

-

V,H

V,HH

V. ,

V.2

-

-

V,hl

V'hO

A

-

A

-

-

CD
Q.

VCCH

Output
Output

Volta~e

Output Leakage Current

Z

mAde

-

-

-

Z

-

-

A

A

V

*

V

*

Power Requirements
(Total Device)
POWl'r Supply Drain

33**

33**

mAde

t pd _

Turn-Off Delay

tpdT

-

-

-

V

-

-

-

V

All Inputs

Inputs
12**

mAde

-

12**

mAde

Switching Parameters
Turn-On DeLly

All

mAde

Pulse
In

Pulse
Out

A,Z

15**

ns

15**

ns

A

Z

-

A,Z

55**

ns

55**

ns

A

Z

-

*

V

-

-

-

-

*Ground inputs to inverters not under test.
**Tested only at 2S"C.

•

V

-

*

MC5400/7400 series

TRIPLE 3-INPUT "NAND" GATE

MC5410 • MC7410

Add Suffix F for TO-86 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7410 only_

CIRCUIT SCHEMATIC
1/3 OF CIRCUIT SHOWN
FLAT]
[ Pkg
Pin

Vee

[11

OIL
Pkg
Pin
1

A

[212~12(31

[14113~
[61
[71
[SI

3

:3J--

(51

6

(91
[101 1 : 3 J - - S [131
[121 11

z

A
B

e
Positive Logic: Z=~
Negative Logic: Z -A+ii"+C

Input Lo"ading Factor = 1

Output Loading Factor = 10
Total Power Dissipation = 30 mW typ/pkg
Propagation Delay Time = 10 ns typ

Gnd

Vee -

Pin 14 (41
Gnd - Pin 7 (111

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
+5.0 Vdc

~--....- - - - - - 3 . 0

400

'----

MM06150
or Equiv

t+=12n5}
.
t- '" 6.0 ns
10% to 90% POints
Duty Cycle
Zout~50

MM07000

50

or Equiv

= 50%

PW - 0.5"s

-=

n
CT

--OV max
2.4 V min

PULSE
GENERATOR

PRF - 1.0 MHz

V min

lk----1.5V

= 15 pF = total

parasitic capacitance, which includes probe, wiring, and load capacitances.

The coax delays from input to SCope and output to scope must be matched. The scope must

be terminated in 50-ohm impedance. The 950-ohm resistor and the scope termination impedance constitute a 20: 1 atten.uator probe. Coax shall be CT -070-50 or equivalent.

1.5 V

r

FLAT]
Pkg
Pin
[1]

DIL
Pkg
Pin
1

s:
(")

A

[2]2~

[14]

13~

[6]

3

[81

5~

[7]4~

v = Vee = Pin 14 [4J
Gnd=Pin 7 [11]

[9J

ELECTRICAL CHARACTERISTICS

0'1
~

- 1 2 [3]

->

,0
6

93J-

s:

[51

(")

-..J
8

~

[131

10l

10H

V"

TEST CURRENT jVOLTAGE VALUES (All Temperatures)
Volts
VR2
VIH VIHH
VRl
V,hO Vcc
V,hl

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

mA

Pin MC541 0 Test Limits
Under -55 to + 125"C
Test Min Max Unit

Characteristic
Input

Symbol

Forward Current

IF

A

Leakage Current

IR1

A

IR2

A

VOL

-

MC541 0
MC741 0
MC7410 Test Limits
o to +70"C
Min Max Unit

10l

-1. 6

mAde

-

->

o

VCCH

5.0

4.50

5.50

5.0

4.75

5.25

VeCl

VCCH

Gnd

V

*

-

V

B,C*

A

-

V

B,C*

-

A,B,C

-

V

-

*

-

A

V

TEST CURRENT jVOLTAGE APPLIED TO PINS LISTED BELOW,

-1. 6

mAde

40

MAde

-

40

flAde

-

1.0

mAde

-

1.0

mAde

-

Z

-

0.4

Vdc

0.4

Vdc

Z

V OH

Z

2.4

ISC t

Z

-20

IpDH

V

IpDL

V

10H

V"

VIH

VIHH

VRI

A

-

-

B,C

VR2

A

-

n-O

VCCl

V,hl

V'hO

-

-

Vcc

:::J
~.
:::J

Pin 7[14J is grounded
for all tests in addiHan to the pins listed
below:

Output
Output Voltage

Short-Circuit Current

-

Vdc

2.4

-

Vdc

Z

-

-

B,C

-55

mAde

-18

-55

mAde

-

-

-

-

16.5

mAde

-

16.5

mAde,

-

6.0

mAde

-

6.0

mAde

-

-

Pulse
In

Pulse
Out

*

-

V

-

V

-

-

-

V

A,B,C*

-

V

-

*

A,B,C*

Power Requirements
(Total Device)
Power Supply Drain

-

Switching Parameters
Turn-On Delay

Turn-Off Delay

tpd_

A,Z

tpd+

A,Z

-

*Ground inputs to gates not under test.
**Tested only at 25 0 C.
t Only one output should be shorted at a time.

15**

ns

22**

ns

-

-

All
Inputs

-

-

-

-

-

15**

ns

A

Z

-

B,C

-

22**

ns

A

Z

-

B,C

-

-

-

-

-

V

*

c:

~

MC5400/7400 series

DUAL 4-INPUT "NAND" GATE

MC5420 • MC7420

Add Suffix F for TO·86 ceramic package (Case 607).
Suffix L for TO·116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7420 only.

CIRCUIT SCHEMATIC

1/2 OF CIRCUIT SHOWN

Vee

[LAT]
Pkg

DIL
Pkg

Pin

Pin

;~

[1]
[12]

4

[13]
1.4 k

4k

5

[14]

.

e

Z

6 (2]

D

[9] 93r>[6]

(7] 10

8 [10]

[8] 12
13

z

A
B

eo--+--I-.

Do--+++"

Positive Logic: Z = A • B • C. 0
Negative Logic: Z = A + B + C + 0

1k

I nput Loading Factor

Vee =

Pin
Gnd = Pin

=1

Output Loading Factor = 10
Total Power Dissipation = 20 mW typ/pkg
Propagation Delay Time = 10 ns typ

Gnd

14 [4]
7 [111

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
+5.0 Vdc

, , . . . - - - . - - - - - - 3.0 V min
400

'Ir-----l.5V
'I.

0 V

max

2.4 V min
MMD6150
or Equiv

1.5 V

-+---l-~==!~i=== 0.4 V
Gnd

50

Duty Cycle = 50%
PW = 0.51l'
Zout~50

MMD7000

or Equiv

n
CT

= 15

pF = total parasitic capacitance, which includes probe, wiring, and load capacitances.

The coax delays from input to scope and output to sc()pe must be matched. The scope must
be terminated in 50-ohm impedance. The 950~ohm resistor and the scope termination im~
pedance constitut;e a 2.,0: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.

max

r

FLAT]
Pkg

OIL
Pkg

Pin

Pin

[I]

2~

4
5

[13J

= Vee

== Pin 14 [4]
Gnd""Pin 7 [11]

C
0

Z

N

,0

6 [2]

:s:

[14J

(")

[6J9~

[7Jl0~

ELECTRICAL CHARACTERISTICS

(J'I
.j::Io

A

[12]

v

:s:

(")

"'-I

.j::Io

8[10J

VIL

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5.50

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5.25

VCCL

VeeH

Gnd

-

V

*

-

V

B,C,D*

-

V

B,C,D*

mA

Pin MC5420 Test Limits
-55 to +125°C
Under
Test Min Max Unit

Characteristic
Input

Symbol

Forward Current

IF

A

Leakage Current

IRI

A

IR2

A

VOL

10L

10H

)

16

.. _.. _0

16

MC7420 Test Limits
o to +70°C
Min
Max Unit

(")

VeeL

10L

10H

VIL

-

A

mAde

-

-I. 6

mAde

40

MAde

-

40

MAde

-

-

-

1.0

mAde

1.0

mAde

-

-

Z

-

0.4

Vdc

0.4

Vdc

Z

V OH

Z

2.4

-

Vdc

2.4

Vdc

-

ISC t

Z

-20

-55

mAde

-18

-55

mAde

IpDH

V

-

11

mAde

-

11

mAde

IpDL

V

-

4.0

mAde

-

4.0

mAde

VIH

A

-

VIHH

VR1

VR2

B,C,D

-

V'hO

V'hl

-

A

-

Vee

o

VeeH

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

-I. 6

-

N

o

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
VRI
VR2
VIH VIHH
V,hl
V'hO Vee

::t

::!.
::t

Pin 7[11] is grounded
for all tests in addition to the pins
listed below:

Output
Output Voltage

Short -Circuit Current

-

-

-

Z

-

-

-

B,C,D

-

-

-

-

-

-

-

-

*

V

A,B,C,D

-

A

-

-

V

-

*

V

All Inputs

Power Requirements
(Total Device)
Power Supply Drain

Switching Parameters
Turn-On Delay
Turn-Off Delay

Pulse
In

Pulse
Out
Z

tpct_

A,Z

-

15**

ns

-

15**

ns

A

tpd+

A,Z

-

22**

ns

-

22**

us

A

Z
. .-

*Ground inputs to gate not under test.
**Tested only at 25" C.
t Only one output should be shorted at a time.

-

All
Inputs

-

-

-

-

-

B,C,D

-

-

B,C,D

-

'--

----

---

-

-

V

-

-

-

V

A,B,C,D*

-

L-

--

-

V

-

-

V
-

*

-

- - '--

*
---

--

---

C

8..

MC5400/7400 series
QUAD 2-INPUT INTERFACE
"NAND" GATE

MC5426L*
MC7426P,L*

This device features high-output voltage ratings for use as
an interface circuit with 12 volt systems, such as low threshold voltage MOS logic circuits.

The output is rated at 15

volts, however, Vee is connected to the standard 5 volt source.
The output transistor has a 16 milliamp sink capability at an
output voltage of 0.4 volt maximum, thus allowing high fan-

1/4 OF CIRCUIT SHOWN

out drive capability while maintaining the nominal power

dissipation of the standard gate.

14'

I

Vee

4k

1.4 k

3

2

Positive Logic:
Negative Logic:

1 k

3"'" "f"';'2
3

= i""+2'

Input Loading Factor:: 1

Output Loading Factor = 1 0

GND
7

Total Power Dissipation

= 40

mW typ/pkg

Propagation Delay Time = 17 ns typ

• L suffix = TO-116 ceramic package (Csse 632)
P suffix = TO-116 plastic package (Case 605)
See General Information section for package outline dimensions.

VOLTAGE WAVEFORMS AND DEFINITIONS

SWITCHING TIME TEST CIRCUIT

Vee
TP out +5.0 Vdc

1...----,.t--+----3.o v

1 k

'-+----1.5 V
------~~----~~~-----OV

tPd_~Pd+ 2.4V min

t+:S;12 ns
t-:S'6 ns

TP out

PRF ~ 1.0 MHz
Generator Zout~50 ohms
PW = 500 ns

1.5 V

______....::==='---=-=-=-=-=-=-=~~ ~ max
VIH

+2.4 Vdc

CT = 15 pF = total parasitic capacitance, which includes probe, wiring, ,nd load
capacitances.
High impedance probes (>1.0 megohm) must be used for tests.

s:

ELECTRICAL CHARACTERISTICS

n
(11

Test procedures are shown .for only one

~

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

N

0)

r

maining inputs.

s:

n

"""
~

N

0)

:==C}-3
:==C}-6

."'C

r
0o

::J

,~==C}-8

::J
C

12~

II

~.

'3~"
TEST CURRENT!VOl TAGE VALUES (All Temperatures)

mA
IOl

MC5426 Test Limits

Pin

Characteristic

Symbol

Test

MC7426

16

I
I

V,H

VR1

VR2

0.4

2.4

4.5

5.5

0.4

2.4

4.5

5.5

Unit

-1.6
40

'R2

1.0

VOL
VOH

0.4

I
I

Vth 1

VthO

VOH

2.0

0.8

12

2.0

0.8

I

12

I
I

Vee

VCCL

5.0

4.5

VCCH

5.5

5.0

4.75

5.25

Vee

VCCL

VCCH

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

Oto 700 e

Max

Min

16

V,l

MC7426 Test Limits

-55 to + 125°C

Under

MC5426

Volts

IOH

10l

V,l

IOH

V,H

VR2

VR1

Vth

a

VOH

Gnd

Max

Unit

mAde

-1.6

mAde

14

7'

/.lAde

40

,uAdc

14

2,7*

mAde

1.0

mAde

14

2,7"

Vdc
Vdc

0.4

Vdc
Vdc

Min

Vth 1

Input
Forward Current

'F

Leakage Current

'R1

Output
Output Voltage

Output Current

15

IOH

50

/.lAde

22

mAde

8.0

mAde

15
50

pAde

Power Requirements
(Total Device)
Power Supply Drain

IpDH

14

IpOL

14

-

-

22

mAde

-

-

8.0

mAde

-

-

Pulse
In

Switching Parameters
Turn-On Delay

tpd_

1.3

Turn-Off Delay

'pd+

1.3

*Graund Inputs to gates not under test
* *Tested only at 25°C.

-

17* ~

n,

24"

"'

-

17**

n,

1

Pulse
Ou'
3

24''''

"'

1

3

I
1

l

I

-

-

I
1

-

I

2

1

-

2

I

-l

I

1

I

-

-

-l

I

1

-

-

I
1
I

1

_.
-

-

1,14

7'
7'

1,14

7"

14

1.2

I

-

1

-

I

-

I

I
1

-

I

-

1

•

-

I
1

12

I

14

1

-

14

I

-l

-

I

14

-l

14

1' .4.7.9.12

MC5400/7400 series

'\
8-INPUT "NAND" GATE

'-------------'

MC5430 • MC7430

Add Suffix F for TO-S6 ceramic package (Case 607).

Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7430 only.

CIRCUIT SCHEMATIC
Vee

•

rLAT]
Pkg
Pin

OIL
Pkg
Pin

[2i
4k

1.4 k

100

t-o...

IIII III

A
B

e
o

g::::: f-<

(3)

2

[51

3

[61

4

[71

5

[81

6

8 [12)

[91 11

>--0

z

[10) 12

E
F

Positive Logic:

G
H

r-....

Z=AeSeCeDeEeFeGeH
Negative Logic:

A

Z~A+B+C+D+E+F+G+H

1 k

~.~

A
Input Loading Factor = 1
Output Loading Factor = 10

Gnd
Vee
Gnd

Total Power Dissipation

= 10 mW typ!pkg

Propagation Delay Time

= 10 ns typ

= P;n
=

14 [4)
Pin 7 [111

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
Vee
+5.0 Vdc

....- - - - - - 3 . 0 V min

~--

400

'\-----1.5 V
OV max

PULSE
GENERATOR

t+
t-

=
12 ns
=. 6.0 ns

}

2.4 V min
MMD6150
or Equiv

.

10% to 90% pOInts

PRF = 1.0 MHz

50

Duty Cvcle = 50%

MM07000
or Equiv

PW = 0.5,,,
Zout:::::::::50 n
CT

= 15 pF

=

total parasitic capacitance, which includes probe, wiring, and load capacitances.

The coax delays from input to scope and output to scope must be matched. The scope must
be terminated in 50·ohm impedance. The 950~ohm resistor and the scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be CT -070-50 or equivalent.

1.5 V

s:
(")

ELECTRICAL CHARACTERISTICS
FLAT]
[ Pkg
Pin

OIL
Pkg
Pin

[3J

2

[5J

3

[6J

4

,,,n '"
[8J

Forward Current

IF

eN

,0

s:

(")

z

IOL

IOH

VIL

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5.50

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5.25

rnA

G
H

Pin MC5430 Test Limits
-,55 to + 125°C
Under
Test Min Max Unit
A

-

-1. 6

mAde

MC5430
MC7430
MC7430 Test Limits
o to +70°C
Max
Min
Unit
-

-1. 6

-

40

!lAde

A

1.0

mAde

VOL

Z

0.4

Vdc

V OH

Z

2.4

ISC t

Z

-20

IpDH

V

IpDL

V

IRI

A

IOL

IR2

!lAde

-

1.0

mAde

-

0.4

Vdc

C')

VeeL

Short-Circuit Current

Pin 7[11] is grounded
for all tests in addi- I
tion to the pins
listed below:
I

V'L

VIH

V'HH

VRI

VR2

Vthl

VthO

Vec

VeeL

VecH

Gnd

-

A

-

-

B,e,D,E,

-

-

-

-

-

V

-

-

-

-

V

B,C,D,E,F ,G,H

-

-

-

V

B,C,D,E,F ,G,H

-

V

-

V

-

-

V

-

-

V

-

-

V

All Inputs

-

-

-

-

-

A

-

-

-

-

A

-

-

-

Output
Output Voltage

o

VeeH

IOH

mAde

40

o

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

F,G,H
Leakage Current

~
"""
W

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
VR2
VthO Vee
VIH VIHH
VR1
Vthl

6

[101 12

Symbol

~

remaining inputs in the same manner.

"~O""

[9J 11

Characteristic
Input

U1

A

[2J

V ~ Vee ~ Pin 14 [4J
Gnd '= Pin

Test procedures are shown for only one input. To complete testing, sequence through

-

Z

All

-

I~puts

Vdc

2.4

-55

mAde

-18

6.0

mAde

-

Vdc

-

Z

-

-55

mAde

-

-

-

6.0

mAde

-

-

-

2.0

mAde

-

B,C,D,E,
F,G,H

-

-

-

-

A

All Inputs,Z

Power Requirements
Power Supply Drain

-

2.0

mAde

-

t pd _

A,Z

Turn-Off Delay

tpd+

A,Z

-

15'

ns

-

15*

ns

22*

ns

-

22'

ns

----

*,Tested only at 25" C.

t Only one output should be

shorted at a time.

--

All

-

Inputs

Switching Parameters
Turn-On Delay

-

-

-

Pulse
In

Pulse
Out

A

Z

-

Z

-

A
---

-

-

-

-

-

-

-

-

-

-

V

-

-

V

B,C,D,E,
F,G,H

-

-

B,C,D,E,

-

-

~?~-~

---

-

::J
~.
::J

C

~

MC5400/7400 series

DUAL 4-INPUT "NAND"
BUFFER

MC5440 • MC7440

Add Suffix F for TO-S6 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Csse 632).
Suffix P for TO-116 plastic package (Case 605) MC744Q only.

This device consists of two 4-input NAND power
gate circuits. Each gate is designed for driving high
fan-out loads (30).

CIRCUIT SCHEMATIC
1/2 OF CIRCUIT SHOWN

I

Vee

r1
Pkg
LA

500

4k

Pin

100

[1J
[12J
[13J
[14J
[6J
A

OIL
Pkg
Pin

;~

4

e

5

0

Z

9~

[7J 10

B

z

eo-++.

[8J 12

o o--+++-"

6 [2J

8 [10J

[9J 13

Positive Logic: Z = A • B • C • 0
Negative Logic: Z

Gnd

Vee
Gnd

=A +B + C +0

Input Loading Factor"" 1
Output Loading Factor = 30

Totsl Power Dissipation = 50 mW typ/pkg
Propagation Delay Time = 13 ns typ

= Pin

14 [4J
= Pin 7 [11J

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
Vee
+5.0 Vdc

, . . - -.....- - - - - - 3.0 V min

133

'k------1.5V
' -_ _ _ 0 V max
2.4 V min

PULSE
GENERATOR

MM06150
or Equiv

t+ = 12 ns
t- = 6.0 ns

}

.

10% to 90% POints

PRF = 1.0 MHz
Duty Cycle = 50%

50

MM07000
or Equiv

PW = 0.5 /l'
Zout~50

.n
CT

= 15 pF

=

total parasitic capacitance. which includes probe, wiring, and load capacitances.

The coax delays from input to scope and output to scope must be matched. The scope must
be terminated in 50-ohm impedance. The 950-ohm resistor and the scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be CT -070-50 or equivalent.

1.5 V

s:
n

ELECTRICAL CHARACTERISTICS
FLAT]
[ Pkg
Pin

11]
112]
113]
v

===

Vee
Gnd

=
=

Pin 14 [4]
Pin 7 [11]

OIL

Test procedures are shown for only one

Pkg
Pin

1

A

4
5

C
0

2~
Z

C'1

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

.~
s:

maining inputs.

612]

n
.....

114]
16]

9~

~
~

Symbol

Forward Current

IF

A

Leakage Current

IRI

A

IR2

A

VOL

Z

V OH

Z

2.4

IsCt

Z

-20

IpDH

IpDL

10H

Vil

48

-1. 2

0.4

2.4

5.5

4.5

5.0

2.0

0.8

48

-1. 2

0.4

2.4

5.5

4.5

5.0

2.0

0.8

8110]

mA

Pin MC5440 Test Limits
-55 to + 125°C
Under
Test Min Max Unit

Characteristic
Input

10l

TEST CURRENT /VOLTAGE VALUES (Ali Temperatures)
Volts
VR2
V,H V,HH
V. ,
V,hl
V,hO Vce

MC5440
MCl440
MCl440 Test Limits
o to +70 c C
Min Max Unit

-1. 6

mAde

-1. 6

mAde

-

40

11Adc

40

fJ.Adc

-

1.0

mAde

1.0

mAde

0.4

Vdc

0.4

Vdl:

o

VCCH

5.0

4.50

5.50

5.0

4.75

5.25

Pin 7[11 Jis grounded
for all tests in addition to the pins
listed below:

VCCl

VCCH

Gnd

V

*

V

B,C,D*

V

B,C,D*

TEST CURRENT IVOn AGE APPLIED TO PINS LISTED BElOW:
lot

10H

Vil

V,H

V,HH

A

V. ,

VR2

B,C,D

-

V,hl

V,hO

Vee

-

A

-

-

A

nO

VCCl

::l
~.
::l
t:
Ol

a.

Output
Output Voltage

Short-Circuit Current

Vdc

2.4

-70

mAde

-18

V

27

V

8.0

Z

Vdc

-70

mAde

mAde

27

mAde

mAde

8.0

mAde

A,B,C,D

B,C,D

Z

-

-

A

-

V

*

V

*

-

V

A,B,D,D,Z*

Power Requirements
(Total Device)
Power Supply Drain

Switching Parameters
Turn-On Delay

Turn-Off Delay

*:

-

t pd _

A,Z

tpd+

A,Z

-

All
Inputs

-

-

Pulse
In

Pulse
Out

15**

ns

15**

ns

A

Z

B,C,D

22**

ns

22**

ns

A

Z

B,C,D

-

V

-

-

V

A,B,C,D*

V

-

-

V

-

*
-

*

--

Ground inputs to ~ate not under test.
Tested only at 25 C.

tbnly one output should be shorted at a time.

-----------------

,-

~

MC5400/7400 series

BCD-TO-DECIMAL DECODER
AND HIGH-LEVEL DRIVER

MC7441AL,P*

This monolithic device is a BCD to one-of-ten decoder
with high-level outputs capable of driving gas-filled coldcathode indicator tubes or other devices requiring highvoltage drivers. In a typical application, this device would
be driven by the MC7490 decade counter through the

•

MC7475 quad bistable latch. The outputs are guaranteed
to operate at 55 volts with a maximum of 200 IJ.A leakage
current. The outputs of this device are protected by zener
diodes to eliminate the possibility of oscillation due to
the breakdown of the output devices.

TRUTH TABLE
1600
1501

A3

8 02
9

86

03

1304
1405

e7

1106
1007

D4

1

08

2

09

D

INPUT
C B A 9

8 7 6 5 4

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

1
1
1
1
1
1
1
1
0
1

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
0

OUTPUT
3

1
1
1
1
1
1
1
0
1
1

1
1
1
1
1
1
0
1
1
1

1
1
1
1
1
0
1
1
1
1

1
1
1
1
0
1
1
1
1
1

1
1
1
0
1
1
1
1
1
1

Input Loading Factor = 1
Total Power Dissipation = 105 mW typ/pkg

A

3O-----l

16
00

01
15
8

02

03
9
13
54

05
14
11
06

07
10
0.8

09
2

Vee = PIN 5
GND = PIN 12

-=
*L suffix:::: l6-pin ceramic package (Case 620).
P suffix = l6-pin plastic package (Case 612).

2

1 0

1
1
0
1

1
0
1
1
1
1
1
1
1
1

1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1

s:

(")

"""

t
....
»

ELECTRICAL CHARACTERISTICS

n

Test procedures are shown for only the A
input and one output. To complete test~
;ng, sequence through the remaining inputs
and outputs as shown in the truth table.

o

::J
~.

::J
C
CIl

Q..

Ion

TEST CURRENT I VOLTAGE VALUES (All Temperatures)
Volts
Vout VCC VCCL VCCH
VthO
V'L V'H V'HH Vth1

7.0

0.4

rnA

Characteristic

Pin
Under
Symbol Test

Input

MC7441A Test Limits
oto +70°C

2.4

5.5

2.0

0.8

55

5.0

4.75

5.25

TEST CURRENT I VOLTAGE APPLIED TO PINS LISTED BELOW:

Min

Max

Unit

Ion

V'L

V'H

V'HH

Vth 1

Vth 0

YOU!

VCC

VCCL VCCH

Gnd

Forward Current

IF

3

-

-1. 6

mAde

-

3

-

-

-

-

-

-

-

5

12

Leakage Current

IRI

3

-

40

!lAde

-

-

mAde

-

3

-

-

-

12

1.0

-

5

-

-

-

3

-

3

IR2

-

5

12

Output Voltage

VOL

1

-

2.5

Vde

1

-

-

-

4

3,6,7

-

-

5

-

12

Output Leakage Current

IOLK

1

-

200

!lAde

-

-

-

-

-

3,4,6,7

1

-

5

-

12

IpD

5

-

32

mAde

-

-

-

-

-

-

-

5

-

-

4,12

Output

Power Requirements
(Total Device)
Power Supply Drain
L-

~----------.

'@,,-

po

MC5400/7400 series

'BCD-TO-DECIMAL DECODER

-

MCS442L"" • MC7442L,Pol'
EXCESS THREE-TO-DECIMALDECODER

MCS443L"" • MC7443L,Pol'
EXCESS THREE GRAY-TO-DECllI/IAL DECODER

MCS444L"" • MC7444L,Pol'
These devices decode four-bit BCD, Excess 3, or Excess 3 Gray
Input Loading Factor == 1
Output Loading Factor

inputs to select one-ot-ten outputs. The selected output is in the
logic "0" state, while all other outputs are in the logic "1" state,

= 10

Full decoding of all valid input logic ensures that outputs remain
off for any invalid input condition.
These devices are useful in memory selection, industrial control,

Total Power Dissipation = 140 mW typ/pkg
Propagation Delay Time:

and data routing applications.

2 Logic Levels = 22 ns typ
3 Logic Levels = 23 ns typ

.

DC Noise Margin == 1.0 V typ

MC5442/MC7442

MC5443/MC7443

Vee == Pin 16
Gnd = Pin 8

Vee
Gnd

=

MC5444/MC7444

Pin 16
8

Vee = Pin 16
Gnd == Pin 8

= Pin

These decoders are constructed using low~level inverters and high·level NAND gates interconnected as shown by the
logic diagrams. The inverter and gate schematics appear on the next page of this data sheet.

MC5442/MC7442
BCD
INPUT
A
D
C
B

MC5443/MC7443
EXCESS 3
INPUT
A
D
C
B

0
0
0
0
0
0
0

0
0
0
0
0
1
1
1
1
1
1
1
1
0
0

0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

0

0
t

0
1
1

0
1

a

0
1
1
1
1

0
0
0

0
1
1
1
1

1
0
0
1
1
0
0
1
1
0
0
1
1

0

0

0

0
1

a

*L suffix = 16-pin dual in-line ceramic package (Case 620).
P suffix = 16-pin dual in-line plastic package (Case 612).

1
0
1
0
1
0
1
0

1
0
1
0
1
0
1

0

MC5444/MC7444
EXCESS 3 GRAY
INPUT
D
C
B
A
0
0
0

0
0
1
1
1
1
1
1
1
1
0
0
0

0
1
1
1
1
1
1
1
1
0
0

0
0
0
0
0

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

9

8

ALL TYPES
DECIMAL
OUTPUT
7 6 5 4 3 2

1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

1 1
1 1
1 1
1 1
1 ,1
1 0
0 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1

1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1 0
1
0
l'

1
1
1
1
1
1
1
1
1
t
1
1
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

MC5442L, MC5443L, MC5444L/MC7442L,P, MC7443L,P, MC7444L,P (continued)

CIRCUIT SCHEMATICS
LOW-LEVEL INVERTER

HIGH-LEVEL "NAND" GATE

Vee
Vee

•

MC5442/MC7442
ELECTRICAL CHARACTERISTICS

"A

Test procedures are shown for only one input and one output. Test other inputs and

outputs in the same manner according to

o.=c

the truth table. Additionally. test all inputoutput combinations according to the truth
table.

~~~
QSr::-o

o---!..!-o

Cho_,1stic

-

Jl.Adc

-

5.5

-

Vde

5.5

-1.6 mAde
40 .Adc
Vdc

-

-

-

0.4

-

0.4

1

2.4

-

Vdc
Vdc

2.4

-

-20

-55

mAde

.'8

-

aVin

12
12
12

VOL
VOH
Ise

1
1
1

IpD

'6

-

IF
IR

-'.6 mAde
40

Output
Output Voltage

Short-Circuit Current

Vdc
Vde
-55 mAde

Power R..uiremenb
IT_I~.I

Power Supply Drain

41" mAde

-

56"

mAde

Turn-Off Delay

Three Logic Levels
Turn-On Oalay
Tum-Off Delay

V'hO
0.8
0.8

Vee VCCL VCCH
5.0
4.5
5.5
5.0 1 4.75 1 5.25

-

-

-

12

-

- - 12
- 12 - - - - 1
- - - - - -

-

-

13,15

-

-

-

-

-

-

12.13,14,15
12,13,14

15
'2,14

-

-

Gnd

'6
16
16

8
8
8

-

-

'6

8
8
1.8

16

'6

- - -

-

-

16

-

-

8,12,13,14,15

-

-

-

-

16
16

-

-

8,12,'3,14
8,12,13,14.

-

-

-

-

-

8,12,'3,'4
8,12,13,14

Pul.. I"USO

SWitchi.... Par.1Mt8rS
Two LosPc Levels
Turn-On Delay

Voh>

10L 10H lin VF VR V'h 1
MC5442 16 -0.4 1.0 0.4 2.4
2.0
MC7442 161 -0.4 1.0 0.41 2.41 2.0 1

MC5442TestLimits MC1442TestLimits TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Oto+700C
Un_ ~to+125oC
Vee VCCL VCCH
V,hO
10L 10H lin VF VR Vth ,
Symbol T_ Min . MIIx Unit Min MIIx Unit

Input
Leakage Current
Breakdown Voltage

mA

Q9p.L..o

-

Forward Current

TEST CURRENTNOLTAGE VALUES (All Temperatures)

'pd-2
tpd+2

15,1

1pd-3
1pd+3

15,2
15,2

IS,'

10"
10'

30"

n.
n.

10"
10

30'

-

35"

n.

-

35"

36

n.

25

25

36

In

Out

n.
n.

15
15

1
1

-

n.
n.

15
15

2

- -

2

-

'6
16

MC5442L, MC5443L,MC5444L/MC7442L,P, MC7443L,P, MC7444L,P (continued)

MC5443/MC7443
ELECTRICAL CHARACTERISTICS
~re shown for only one input and one output. Test other inputs and
outputs in the same manner according to
the truth table. Additilmally, test all inputoutput combinations according to the truth
table.

Test procedures

I

TEST CURRENTNOL TAGE VALUES CAli Temperatures)
mA

MC5443Test Limits MC7443TestLimits

Characteristic

Symbol

VGlts

TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:

~n ~~~~to~+~I~~~O~C~~~0~t~O~+7~0~OC~~~~~~~~~:T~~r-~~~~:l~~r:==lI.~j
Max Unit Min Max Unit
IOL IOH lin VF VR Vth 1
Vth 0
Vee VCCL VCCH VIHX

u;!' Min

Input

'2

Forward Current
Leakage Current
Breakdown Voltage

-1.6 mAde

12

12

40

5.5

-

/.lAde

Vdc

- '2 '2
'2

-1.6 mAde
40

5.5

",Adc

Vdc

Gnd

'6
'6

'6

Output

Output Voltage

Short-Circuit Current
Power Requirements
(Total Device)
Power Supply Drain
Switching Parameters

!-;V.,.,O~L,-+--;---j~.-+.:0:::"=+-7V;:;dc:-+=c+-.::O':.:'c+-VCi.d;:C-+~+""7+-t-=--r.::--+-,,'4;;"i'5+..';--,2;;,'~3:,-r=-t-7.'6;-,:r-_+_+---;---i
VOH
ISC

'pD

2.4
-20

'6

-55

Vdc 2.4
mAde -18

Vdc
-55 mAde

4'"

mAde

56* mAde

-

13
2.13,14

Pulse

12,14.15
15

16

'.8

'6

'6

-

8,12,13,14,15

'6
'6

'3

8,'2."

'3

8,12.14

'6
'6

'3

'3

8,12,14
8,12,14

ulse

~~

Two Logic Levels
Turn-On Delay

tpd_2

15,2

10'"

30*

10"

30"

Turn-Off Delay

tpd+2

15,2

10

25

10

25

'5

Turn-On Delay

tpd 3

15,3

tpd+3

15.3

35"
35"

'5

Turn-Off Delay

'5

Three Logic Levels

35"
35

'5

"'Tested only at 2SoC.

MC5444/MC7444
ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one in-

put and one output. 'Test other inputs and
outputs in the same manner according to

the truth table. Additionally, test all inputoutput combinations according to the truth
table.

".

".
as

13
v-

C

o-E

0

~:r;-o

a8~

~p2-0
MC5444

TEST CURRENTNOLTAGE VALUES (All Temperatures)
mA

IOl

16

Volts

IOH lin VF VR Vth 1

-0.4 1.0 0.4 2.'

2.0

Vth 0

0.8

Vcc VCCL

5.0

'.5

VCCH V,HX

5.5

2.5

MC7444~'~6i--~0~.4~'.~OtO~.74r.2~.4~!J~.2~.0~-~0~.8~'1~5~.0~~14~.7~5+~5.~25~-2~.~5~

Pin

Characteristic

Input
F,orward Current
Leakage Current
Breakdown Voltage
Output
Output Voltage
Short-Circuit Current
Power Requirements
(Total Davice)
Power Supply Drain
Switching Parameters
Two Logic Levels
Turn-On Delay

Turn-Off Delay
Three Logic Levels
Turn-On Delay
Turn-Off Delay
"Tested only at 26°C.

Symbol

MC5444TeItLimits MC7444TestLimits

TEST CU,RRENTNOLTAGE APPLU:D TO PINS LISTED BELOW:

uT~r~~~t~O~+~I~~~O~c~~~o~ro~+~7~~~C~~~~~~~~J::1~~Y-~~-'~~~~~~-r:--l
....~ Min Max Unit Min Max Unit
IOL IOH lin VF VR Vth 1
Vth 0
Vee VCCL VCCH VIHX
12
12

'2

-1,6 mAde
40 pAde

5.5

VOL

Vdc
0.4

2.4
-20

ISC

'pD

'6

"d-2
'pd+2

'3.1
'3.1

'pd-3
'pd+3

13,2
'3,2

10"
10

-

-1.6 mAde
40 pAde

5.5

Vdc

-

'6

'2

Vdci

16

'6
'6

14
'2,13,'5
'3.'4
'2,'5

-55

Vde 2.4
mAde -18

Vde
-55 mAde

41*

mAde

-

56"

30"

10"

30"

~

'0

25

'3

'6

35"

13
13

'6
16

35"
35

35

12,13,14,15

mAde

Gnd

'6

-

'2

Vdc
0.4

12

-

8

16

',8

'6

-

'6

'4

8,12.13,14,15

8.'2,'5

'4

8,12,15

'4

8.12.'5
8,'2.'5

14

MC5442L, MC5443L, MC5444L/MC7442L,P, MC7443L,P, MC7444L,P (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

Vce

VIHX
+2.5 Vdc

'+5.0 Vdc

00
15

A

400

01
02

14

B

03

TP out

04
13
PRF = 1.0 MHz
=: t- ~10 ns

50

t+

12

C

MMD6150

05

or Equiv

06
07

0
08

09

9
10
11

r

MMD7000
or Equiv

CT

CT = 15 pF == total parasitic capacitance, which includes probe, wiring, and load

capacitances.
·The coax delays from input to scope and output to scope must be matched, The
scope must be terminated in 50-ohm impedance. The 9SO-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT-070-50 or equivalent.

3.0 V

TPin
OV

t p d_2

2.4 V min

TP out
0.4 V max

GND
tpd+3

2.4 V min

TP Qut
0.4 V max

GND

-:::-

MC5442L, MC5443L, MC5444L/MC7442L,P, MC7443L,P, MC7444L,P (continued)

TYPICAL APPLICATIONS

Two MC5442/7442 decoders may be used to perform 4-line to
16-line decoding. Data inputs A, B, and C are paralleled to the two
decoders, while input D is applied to one decoder and is to the other.
(See Figure 1.)

FIGURE 1 - BINARY·TO-DECIMAL DECODING USING
MC544217442

The excess 3 code is similar to the BCD code except that 3 is

•

added to each digit before coding. This code has the advantage of
beingself~complementing. Ifall zeros in a BCD number are changed

to ones and all ones are changed to zeros, the nines complement of
the decimal number is obtained. TJle ability to obtain the nines camplementcan reduce the hardware necessary to perform subtraction.

MC544217442

A

A

B

B

C

C

D

D

00
01
02
03
04
05
06
07
08
09

(See Figure 2.)

All Gray codes have one basic characteristic in common. As
the code is advanced from any number to the next. only one bit
of the code will change at a time. When a non-Gray code such as
straight binary is advanced from 3 to 4 (0011 to 0100) three bits

of the code must change. Since in many applications the voltages
on the three lines do not change simultaneously. a number of false
outputs may be generated which last for a short time. These false
outputs are easily accepted by the high-speed devices now in use.
In contrast, the excess 3 Gray code of the MC5444/7444 would
change from 0101 to 0100 to advance from 3 to 4.

Decimal
Output

0
2

3
4
5
6
8'
9'

M C544217 442

Analog measuring devices require a converter for information
fed to a digital system. These converters usually use a Gray code
output. Gray codes are also useful in sequential circuitry because
of the change of only one bit at a time.

00
01
02
03
04
05
06
07
08
09

D

Figure 3 shows the MC5444/7444 used for decoding 3-line
binary·te-octal. The input to A, B, and 0 is the binary code ABC.

C

The C input of the device is used as a strobe. Octal data is taken

B

from outputs 01 through 08 when the strobe is taken to a logic
"1". Outputs 00 and 09 are not used.

A

8'
9'
10
11
12
13
14
15
Dff
Dff

-These decimal outputs are available from both decoders.

FIGURE 2 -II-LINE EXCESS THREE CODE-TO-NINES COMPLEMENT DECIMAL DECODING USING MC5443/7443

FIGURE 3 - 3-LINE BINARY-TO-OCTAL DECODING
USING MC544417444

MC544317443
Excess 3
Code
Input

Nines
r - - - - , Complement
I

I Input

A
B

C
D
IL

___

..JI

MC3108
or Equiv

00
01
02
03
04
05
06
07
08
09

MC544417 444

Nines
Complement
Decimal

Output

A Input

A

B Input

B

Strob~
C Input

C
D

00
01
02
03
04
05
06
07
08
09

No Connection

tl'~"

No Connection

MC5400/7 400 series

BCD TO ONE-OF-TEN
DECODER/DRIVERS

MC5445L • MC7445L,P iC
MC54145L . MC74145L,P iC

These devices are intended for use as drivers for indicators or relays, rather than drivers
for MTTL logic gates, as is the case with the
MC5442/7 442, which isfunctionally identical.
The output transistors of these devices are
capable of sinking 80 mA, and have break·
down voltages of 30 V (MC5445/7445) and
15 V (MC54145/74145). The outputs are
suitable for open-collector logic applications,
and are compatible for interfacing with most
MOS integrated circuits. Since full decoding
is included, all outputs remain off for nonBCD inputs

00

C

13

2

01

3

02

4

03

5

04

6

05

9

07

10

08

06
D 12

11 09

Vee = Pin 16
GND = Pin 8

Total Power Dissipation = 215 mW typ/pkg
Propagation Delay Time = 50 ns max

INPUTS
D
0

0
0

0
0
0

0
0
1
1
1
1
1
1
1
1

C
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1

B

0
0
1
1

0
0
1
1
0
0
1
1
0

0
1
1

OUTPUTS
A
0
1

a
1
0
1
0
1
0
1
0
1
0
1
0
1

09
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1

·L suffix = 16-pin dual in-line ceramic package (Case 620).
P suffix = 16-pin dual in-line plastic package (Case 612).

08
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

07
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

06
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

05

04

03

02

01

60

1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1

1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

•

I
s:

ELECTRICAL CHARACTERISTICS

(")

Test procedures are shown for only one
input and one output.

0'1

Test other inputs

~
~

and outputs in the same manner according

0'1

to the truth table. Test all input*output
comhinations according to the truth table.

r-

s:(")

"t

00
151A

01

0'1

r-

02
141B

03

Ie

05

"-c

s("):

04
13

0'1

06

~
.....

07
12 I

iii
r-

08

D

11

-

~'I

I

TEST CURRENT/VOLTAGE VALUES (All Temperatures)

s:

Volts

rnA

(")

Symbol

Pin
Under
Test

Forward Current

IF

12

Leakage Current

IRI

12

IR2

12

VOL

1
1

VCEX

Characteristic

MC5445/MC54145
Test Limits
55 to +12SoC

lOll

IOL2

ICEX

VIL

VIH

VIHH

Vth 1

MC5445, MC54145

20

80

0.25

0.4

2.4

5.5

2.0

0.8

5.0

4.5

5.5

MC7445, MC74145

20

80

0.25

0.4

2.4

5.5

2.0

0.8

5.0

4.75

5.25

MC7445/MC74145

MC544517445
MC54145/74145

VCCL

".....

VCCH

~

iii
r-

TEST CURRENTIVOLTAGE APPLIED TO PINS LISTED BELOW:

Test Limits

o to +70o C

Min

Max

Unit

Min

Max

Unit

lOll

-

-1.6

mAde

-1.6

mAde

40

,uAdc

40

,uAdc

1.0

mAde

-

1.0

mAde

-

-

-

0.9
0.4

Vdc
Vdc

-

-

0.9
0.4

1
1

30
15

-

Vdc
Vdc

30
15

-

Vdc
Vdc
Vdc
Vdc

16

-

62

mAde

-

70

mAde

IOL2

ICEX

VIL

VIH

VIHH

V'h 1

Vth 0

VCC

VCCL

VCCH

Gnd

-

12

-

-

-

16

8

12

-

-

-

-

-

-

-

16

8

-

12

-

-

-

-

-

-

-

--

-

-

-

-

-

1

12,13,14

1

12,13,14

-

-

-

Input

Output
Output Voltage

V'hO

VCC

-

-

-

1

1
-

-

-

-

-

1
1

-

16

8

16
16

-

-

-

16
16

8
8
8
8

(Total Device)
Power Supply Drain

IPD

Pulse In

Turn-On Delay

'pd-

15,1

Turn-Off Delay

'Pd+

15,1

#Tested only at 25 u C.

-

50#

ns

-

50#

ns

15

50#

ns

-

50#

ns

15

I
I
1

-

-

-

-

16

8,12,13,14,15

-

16
16

-

-

8

-

nO
::J
~,
::J

C
CD

-

12,13,14,15
12,13,14,15

12,13,14,15
12,13,14,15

-

-

0..

Power Requirements

Switching Parameters

"-c

Pulse Out

8

MC5445L, MC7445L,P/MC54145L, MC74145L,P (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

0.4 V

5.0 V

00
15

A

14

B

100

01
02
03

3
4

04
13

C

0.5
06

TP out

0.7
PRF

=

1.0 MHz

12

50

PW= 100ns

D

lCT

08
09

t+=t-~10ns

CT "" 15 pF

=

total parasitic capacitance, which includes probe and wiring

capacitances.
*The coax delays from input to scope and output to scope must be
matched.

The scope must be terminated in 50-ohm impedance.

The

9S0-ohm resistor and the scope termination impedance constitute a 20: 1
attenuator probe. Coax shall be CT-070-50 or equivalent.

90%

3.0 V

TPin
10%

OV

2.4 V
TP out

0.4 V

GND

MC5445L, MC7445L,P/MC54145L, MC74145L,P (continued)

FIGURE 1 - BINARY-TO-DECIMAL DECODING USING
MC5445/7445 OR MC54145174145

TYPICAL APPLICATIONS

Two MC5445/7445 or MC54145/74145 decoder/drivers
(depending on drive requirementsl may be used to perform 4-line to 16-line decoding. Data inputs A, B, and C
are applied to both decoder/drivers, while input D is applied
to one decoder and B to the other. (See Figure 1.1
In addition to the obvious decoder applications, these
circuits can also be used for data distribution (Figure 21.
Inputs A, B, and C of the decoder/driver are used as con·
trol inputs, while the D input serves as the data input. In a
typical compound data routing application, origin data
is selected by the control inputs of the MC54151/74151
8-channel data selector. The data is then routed to the
proper destination by means of the MC5445/7445 decoder/
driver control lines.

MC5445/7445
MC54145/74145
8CO
Inputs

A---.------1 A
8--+.......- - - - - 1 8
C--+-4-1~----1

C

0--++-1-.......---1 D

00
01
02
03
04
05
06
07
08
09

Decimal
Outputs

0
2
3
4
5
6
7
8'
9'
To Indicators
Relays, etc.

MC5445/7 445
MC54145/74145

D

C
8
A

00
01
Q2
03
04
05
06
07
08
09

8'
9'
10
11
12
13
14
15
Dff
Off

'These decimal outputs are available from both decoders.

FIGURE 2 - COMPOUND DATA ROUTING USING MC544517445

~",,'""

0"" ""' {

A
8

E

00
Z

Data
Origin

C
XO

{

,,",," """"
Control

Xl
X2

A

02
8

03
04
05

X3

C

X4
X5
X6

01

Z

X7

Destination

06
07

Data
0

08
09

MC54151/74151

MC5445/7445

8-Channel Data Selector

Decoder/Driver

MC5400/7400 series

BCD·TO-SEVEN SEGMENT
DECODER/DRIVERS

MC5446L • MC7446L,P*
MC5447L • MC7447L,P*
Compatible with MC5400/7400 Series devices.

These devices decode 4-bit binary coded decimal data,
dependent on the state of auxiliary inputs, and provide
direct driving of incandescent, seven-segment, display indicators.
Ripple blanking inputs provide capability for suppression
of non-significant zeros in a system. The blanking input
can be used to control lamp intensity.

A 7

13 •

B 1

12 b

e 2

SEGMENT IDENTIFICATION
11 c

016

Blanking
Input

Ri~~le

NUMERICAL DESIGNATION - SEGMENTS ILLUMINATED

10 d

(>4+_ _1

Blanking
Output
9

Lamp-Testi3
Input

•

15 f

Ripple 5
Blanking

8

14 9

9

10

11

12

13

14

15

Input

Input Loading Factor:

Vee

=

GND

= Pin

BIIRBO = 2.6
Other Inputs = 1

Pin 16
8

Output Loading Factor:
81/R80 = 5
Total Power Dissipation =

265 mW typ/pkg

TRUTH TABLE
DIGIT
OR
FUNCTION
0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
81

RBI

LT

I

INPUT
LT
Pin 3

RBI
Pin 5

D
Pin 6

C
Pin 2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
0

1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
X

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X

Q

X

B
Pin 1

A
Pin 7

0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
X

0
1
1
0
0

1
1

0

0
1
1
0
0
1
1
X

0

0

X

X

x = Don't care
-L suffix = l6-pin dual in-line ceramic package (Case 620),
P suffix = l6-pln dual in-line plastic package (Case 612).

BI/RBO
Pin 4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1

OUTPUT

a
Pin 13
0
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1
1
1
0

b
Pin 12
0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
1
1

1
0

c
Pin 11
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0

d
Pin 10
0
1
0
0
1
0

0
1
0
1
0
0
1
0
0
1
1
1
0

e
Pin 9
0
1
0
1
1
1
0
1

0
1
0
1
1
1
0
1
1
1
0

f
Pin 15
0
1
1
1
0
0

0
1
0
0
1
1

0
0
0
1
1
1
0

9

Pin 14
1
1

0
0
0
0

0
1

0
0
0
0
0
0
0
1
1
1

0

MC5446L, MC5447L/MC7446L,P, MC7447L,P (continued)

CIRCUIT SCHEMATIC
r-----------~~------~--~16

Vee

13 a

A

70-r--~

12 b

11 c

e 2 o-r--tt-~

10 d

o

6

o-r--ti---"
9

e

15 f
Blanking
Input
.Or

-r----l--1f=t==::::::::~T'--'

4
..
0.

Ripple
Blanking
Output

Ripple

Blanking
Input

5

o-r--+------'

14 g

3
Lamp Test

s:

ELECTRICAL CHARACTERISTICS

(")

~

Test procedures are shown for only one
data input and the blanking input, and for
one driver output and the ripple blanking
output. Test other inputs and outputs in

B

the same manner according to the truth
table. Test all input-output combinations

b

~'

according to the truth table.

r

12

s:

11

6 0

10

3 LT

9

(")
U1

t-...I

.-

15

RBI

41

8;

13

A

s:

14

BIIRBO

n

-...I

.-£

TEST CURRENTNOLTAGE VALUES (All Temperatures)

•

mA
lOLl
20

IOL2
8.0

IOH
-0.2

ICE X
0.25

VIL
0.4

VIH
2.4

VIHH
5.5

Mp446, MC7447

20

8.0

-0.2

0.25

0.4

2.4

5.5

MC7446IMC7447

Test Limits

Test Limits

Vth 1
2.0
2.0

Vth 0
0.8

VCC
5.0

VCCL
4.5

0.8

5.0

4.75

VCCH
5.5
5.25

:a

VIHX
2.4

s:

n

2.4

-...I

TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:

o to +700 C

-55 to +1250 C

Under

Characteristic

MC5446, MC5447
MC5446/MC!;447
Pin

Volts

Svmbol

Tost

Min

Ma.

Unit

Min

Ma.

Unit

lOLl

IOL2

IF

1
4
1
1

-

-1.6
-4.2

mAde
mAde

-

~Adc

"Ade

-

-

1.0

mAde

-

-1.6
-4.2
40
1.0

mAde

40

-

mAde

-

2.4
30
15
-

0.4
0.4

-

-

0.4
0.4

-4.0

Vde
Vde
Vde
Vde
Vde

2.4

-

mAde

30
15
-

-

ISC

9'
4"
4"
9'
9'
4

-4.0

mAde

-

IpD

16

-

76

mAde

-

90

mAde

-

7,9
7,9

-

ns
ns
ns

-

IOH

It;EX

'-

VIL

VIH

VIHH

Vth 1

VthO

VCC

VCCL

VCCH

VIHX

Gnd

-

1
4

3

-

1

-

-

16
16
16
16

-

-

-

-

-

-

8
8
3,8
3,8

-

3,4,5
3
3,5

-

-

-

-

3.4,7
3,4,7
3,5

-

16
16
16

-

1,2,6,7
1,2,5,6,7
1,2,6,7
1,2,6
1,2,6
1,2,6,7

-

-

16
16
16

-

8
8
8
8
8
4,8

Input
Forward Current

Leakage Current

IRl
IR2

mAde

-

-

1
-

-

--

4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Output
Output Voltage

MC!;446/7446
MC544717447
Short-Circuit Current

VOL
VOH
VCEX

Vde
Vde
Vde
Vde
Vde

9

-

-

-

-

-

4

-

-

9
9

-

-

-

-

-

-

-

-

-

-

-

1,2,3,4,5,6,7

-

-

-

16

-

8

-

-

-

-

-

16

-

-

1,2,3,4,5
3,4,5
3

6,8
1,2,6,8
1,2,6,7,8

-

-

3

1,2,6,7,8

-

Power Requirements

(Total Device)
Power Supply Drain

Switching Parameters
Turn-On "Delay
Turn-Dn,Delay

tpd-l
tpd+l
tpd-2

Turn-Off Delay

tpd+2

Turn-Off Delay

4,5,13
4,5,13

*Test procedure for outputs a thru g.
**Test procedure for' BI/RBO only.
#Tested only at 2SoC.

100#
100#
100#
100#

ns

-

Pulse In

Pulse Out

7

9

7

100#
100#
100#

ns
ns
ns

4,5

9
13

100#

ns

4,5

13

-

-

16
16
16

t
.--...I

'"-c

nO
::J
....

5'
c
~

MC5446L, MC5447L/MC7446L,P, MC7447L,P (continued)

SWITCHING TIME TEST CI RCUIT AND VOLTAGE WAVEFORMS

2.4 V

•

5.0V

13

A
B
2

6
3
PRF

~

1.0 MHz

50

PW-l00ns
t+

5
4

= t- :S:24 ns

b

11

C
D

LT
RBI
BI/RBO

280

12

d

10

9

TP out

15
14

r

CT

CT = 15 pF = total parasitic capacitance, which Includes probe and wiring

capacitances.
·Tha coax delays from Input to scope and output to scope must be
matched.

The scope must be terminated in 50-ohm impedance. The

950-ohm resistor and the scope termination impedance conStitute a 20: 1
attenuator probe. Coax shall be CT-070-50 or equivalent.

3.0V

TPin
OV

tpd_1
2.4V

TP out
0.4 V

GND
t p d+2
2.4 V

TP out
0.4 V

GND

MC5446L, MC5447L/MC7446L,P, MC7447L,P (continued)

OPERATING CHARACTERISTICS

These monolithic integrated circuits provide the logic
necessary to decode a BCD input and drive a seven-segment
numerical indicator. Input buffers give an input loading
factor of 1 on all but the BI/R BO input. High-sink-current
outputs, designed to withstand the relatively high voltages
of incandescent seven·segment indicators, permit direct
driving of the indicators. Both devices will draw a maximum reverse current of 250 microamperes at the maximum
output voltage (30volts for the MC5446/7446 and 15 volts
for the MC5447/7447).
Pin 4 serves as both a blanking input and a ripple blank·

ing output (BI/RBO). For displaying digits 0 thru 15 the
blanking input must be held at a logic" 1" or open (see the
truth table). For a decimal 0 output the ripple blanking
input (RBI) must also be at a logic "1" or open.
When a logic "0" is applied to BI, outputs a thru g go to
a logic "1" regardless of the state of any other input. With
RBI at a logic "0" and A = B = C = D also at a logic "0",
outputs a thru g go to a logic "1" and RBO goes to a logic
"0". When a logic "0" is applied to lamp-test and BI/RBO
is open or held at a logic "1", outputs a thru g go to a
logic "0".

INPUT/OUTPUT VOLTAGE WAVEFORMS

LT

BI

~

~

x-------x

'A

0

B

x-------x

c

x-------x

01

Ix-------x

I

LT
RBI

rRSQ Response

BI/RBO

.-

'--___________ x- - -

---------------.l.!r

b

d

x----x ""

Input may be high or low.

.

----X
Forced 81

~

II
This 6-digit display provides blanking of non-significant
zeros in the two most-significant and two least-significant
decades. This causes the number 6.3 to be displayed instead
006.300. Blanking is achieved by grounding input RBI of
the most-significant and least-significant decades and connecting the BI/R BO terminal of these two decades to input

TYPICAL
APPLICATION

RBI of the adjacent decades. The RBI inputs of the decades on either side of the fixed decimal point are inhibited
by connecting them to a 5.0-volt source, causing zeros to

be retained in these positions.
Lamp intensity control is achieved by modulating input
BI with a multivibrator.

:s:

(")
(J1

.j::o.
.j::o.
0)

r

:s:

(")

CJ1

.j::o.
.j::o.

-...J

r

:s:
(")
-...J

To Display Indicators

't

Most-Significant

Decade '(d;cator

~

5'

r

V

~·-t~
DeCimal POint

IndIcator

5'

r

V

~-

T
=c
Least-Significant

.j::o.
.j::o.
0')

r

.""C

:s:
(")
-...J

.j::o.
.j::o.

-...J

r

""C

nO
::I

:~~-1--J---::~~-L~--~------~~,t'==~-----L--II----~~~=J===------BCD Input

BCD Input
Lamp 0

Test

,- -.- -

-

BCD Input

- -----

I

BCD Input

--,

I
I MC540517405

__ J
Voltage-Controlled

::~~~~i~;:~o;4

rl___...._._______-J~-_____~l__ _ __J~_ _ _ _ _ _~L------__.J

!:!'.

::I
I::
CD
0..

MC5400/7400 series

BCD-TO-SEVEN SEGMENT
DECODER/DRIVER

MCS448L • MC7448L,P*

This device decodes 4-bit binary coded decimal input data in a
format suitable for use with incandescent, seven-segment, display
indicators. It is intended for use with other logic elements or
discrete components rather than for the direct driving of display

indicators as is the case with the MC5446/7446 and MC5447/7447
which are similar.

A 7

Ripple blanking inputs provide capability for suppression of
non-significant zeros in a system. The blanking input may be used

to control lamp intensity.

13 a

•

B 1

12 b

C 2

SEGMENT IDENTIFICATION
D6

Blanking
Input
or
4
Ripple
Blank ing

NUMERICAL DESIGNATION - SEGMENTS ILLUMINATED

10 d

0-1'-----1

Output

Lamp-Test 3
Input

Ripple 5
Blanking
Input

8

14 9

9

10

11

12

13

14

15

Input Loading Factor:
BI/RBO ~ 2.6
Other Inputs = 1

Vee = Pin 16
GND =' Pin 8

Output Loading Factor:
BI/RBO ~ 5
a thru g = 4
Total Power Dissipation '"
265 mW typ/pkg

TRUTH TABLE
DIGIT
OR
FUNCTION
0
1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
BI
RBI
LT

x-

I

INPUT
LT
Pin 3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

OUTPUT

RBI
Pin 5

D
Pin 6

C
Pin 2

B
Pin 1

A
Pin 7

BI/RBO
Pin 4

a
Pin 13

1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
X

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
1

X

X

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1

X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

1
0

0

0

X

X

X

0

0

X

X

Don t care

*L suffix:= 16-pin dual in-line ceramic package (Case 620).
P suffix = 16-pin dual in-line plastic package (Case 612).

b

c

d

e

Pin 12

Pin 11

Pin 10

Pin 9

f
Pin 15

Pin 14

1
1

1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
0
1

1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0

1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0

0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0

0
0
1

0
0
1

0
0
1

0
1
0
1
1
1
0
0
0
1
0
0

1
1
0
0
1
1
1
0
0
1
0
0
0

1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0

0
0
1

0
0
1

0
0
1

1

9

•

ELECTRICAL CHARACTERISTICS

s:

n
(11

Test procedures are shown for only one
data input and the blanking input, and for
one driver output and the ripple blanking

t

CO

r

output. Test other inputs and outputs in
the same manner according to the truth
table. Test all input-output combinations
according to the truth table.

s:

t

13

A
b

B

CO

12

r'"C

11

C

~D

d

10

n

o

9

LT

....
::J

15

RBI
41

n
......

::J

C

~

14

BI/RBO

TEST CURR ENT /VOLT AG E VA LU ES (All T emperaturesl
rnA

I

MC5448

MC7448
Pin
Under

Characteristic

Symbol 1 Test

MC5448 Test limits

I M. .

'F

-1.6

Leakage Current

'R1

40

'R2

1.0

Output
Output Voltage

VOL

-4_2

g'

Max

Un;'

-

-1.6

-

-4.2

mAdc
mAdc

Min

4"
VOH

Load Current

I Load

Short-Circuit

ISC

g'
4""

2.4
2.4

g"

-1.3

I
I

mAde
mAd,
J1.Ade
mAd,

-

-

0.0

Vd,
Vd,

-

-

Vd,
Vd,

2.4
2.4

-

mAd,

-1.3

0.4

6.4

I

IOL2
8.0

8.0

I

I

Volts
IOH1
-<)4

-0.4

IOH2

Iv< I v~ I .. ~ I
n ....

40

n ..

.., "

M

VIHX

I

2.4
2.4

'" '"

TEST CURRENT!VOLTAGE APPLIED TO PINS LISTED BELOW:

o to +70 oC
Unit

Input

Forward Current

6.4

I

MC7448 Test Limits

55 to +125OC
Min

10L 1

l

lOll

I

1 IOL2

I

1

1

IOH1

I

IOH2

I

V,L

I

V,H

I

V,HH

I

VLoad

Vth 1

MAde
mAd,

0.4
0.4

Vd,
Vd,

3,4,5,7

-

Vd,
Vd,

3
3.5

-4_0

mAd,

-

-4_0

76

mAde

-

gO

mAde

VthO

I VCC I VCCL I VCCH

VIHX

Gnd

16
16

1.0

mAde
mAd,

I

1

3

1,2,6
1,2,5,6,7

3.5

3,8

16

3.8

16
16

1,2,5,6,7
1,2,6,7
1,2,5,6,7 I

16

16
16
-

1,2,6,7

I

16
4,8

16

Current
Power Requirements
(Total Device)
Power Supply Drain

IpO

16

Turn-On Delay

tpd_1

7,9

100#

n,

Turn-Off Delay

7,9

100#

Turn-On Delay

tpd+1
tpd.,...2

Turn-Off Delay

tpd+2

n'
n,
n,

4,5,13
4,5,13

---Test procedure for outputs a thru g_
......Test procedure for BI/RBO only_
#Tested only at 250 C_

100#

1ilO# t---

-

Pulse In

I

100#

t

100#

I

n,
n,

t

I

4.5
4,5

I

16

Pulse Out

100#
100#

-

1,2,3,4,5,6,7

I

Switching Parameters

16

1,2,3,4,5

16

3.0,5

I
I

6,8
1,2,6,8

---- f3

16

1,2,6,7,8

13

16

1,2,6,7,8

MC5448L, MC7448L,P (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVE'FORMS
5.0 V

2.4 V

7

13

A
B

2
6
3

PRF

1.0 MHz
PW-1QOns
~

5

50

4

t+=t-~24ns

b

12
11

C

o

d

LT

e

10
MM06150
or Equiv ,

9
15

RBI

MM07000

BI/RBO

14

or Equiv

R L ~ 1.0 kn for MC5448. 667 n for MC7448.

CT = 16 pF = total parasitic capacitance. which includes probe and wiring
capacitances.

·Tha coax delavs from Input to scope and output to scope must be
matched.

The scope must be terminated in 50-ohm impedance. The

. 950-onm resistor and the scope termination impedance constitute a 20: 1
attanuat~r probe. Coax .hall be CT:070-50 or equivalent.

A INPUT TO OUTPUTS
3.0V

TPin
A

OV

'pd-l
2.4V

TP out
0.4 V
GNO
t p d:+2

2.4V
"[Pout
'O.4V
GNO

RBI INPUT TO OUTPUTS
TPln
A.B,C,O

\1.5

3.0V
V

Oli
3.0V

TPin
RBI

1.5 V
O'V

2.4V

TP out

1.5 V
0.4 V
GNO

•

MC5448L, MC7448L,P (continued)

OPERATING CHARACTERISTICS

•

ing output (BI/RBO). For displaying digits 0 thru 15 the
blanking input must be held at a logic "1" or open (see
the truth table). For a decimal 0 output the ripple blanking input (RBI) must also be at a logic "1" or open.
When a logic "0" is applied to BI, outputs a thru g go
to a logic "0" regardless of the state of any other input.
With RBI at a logic "0" and A ; B ; C; D also at a logic
"0", outputs a thru g and RBO go to a logic "0". When a
logic "0" is applied to lamp-test and BI/RBO is open or
held at a logic "1", outputs a thru g go to a logic "1".

This monolithic inte!rated circuit provides the logic
necessary to decode a BCD input and drive a seven-segment
numerical indicator. It is intended for use primarily as a
driver for discrete, active components or logic elements.
If direct driving of display indicators is desired, the
MC5446n446 (30 volts maximum output voltage) or the
MC5447n447 (15 volts) should be used, since they are
designed to handle the relatively high voltages and sink
currents (20 mAl of incandescent indicators.
Pin 4 serves as both a blanking input and a ripple blank-

INPUT/OUTPUT VOLTAGE WAVEFORMS

LT
,...A-,

BI
,....-.....,

x-------x

A

0

2

4

6

B

X-------X

c

X-------X

01

IX-------X

I

LT

rRBO Response

BIIRBO

I

'--___-'-_________ x- - - - -

RBI

--------------'--,l.!.r

b

d

x----x = Input m~y be high or low.

--X

Forced 81

c:::::=-

MC5448L, MC7448L,P (continued)

APPLICATIONS INFORMATION

The MC5448/7448 is useful in applications requiring
higher output currents and/or voltages than is available
with the MC5446/7446. The decoder/driver may be used
to drive buffer transistors selected for the required output
characteristics. A suitable interface circuit is shown in
Figure 1, where each decoder/driver output drives two
lamp segments.
If the buffer load current is known, then base current
is obtained from IB "" I L/hFE. From this and the approxi·
mate MC5448/7448 output characteristics, suitable values
of RB can be determined. For a given load current,

ILoad, (21B in this example) the output voltage, Vo , is
given by Vo = 2.5 - 0.139 I Load = 2.22 volts. (See the
load line of Figure 2, with I Load = 2.0 mA.) RB is then
found from:
RB = Vo - VBE
IB

2.22 - 0.75 "" 1.5 kr2
10.3

Operation of the blanking controls is identical to that
of the MC5446/7446 and is illustrated in a typical appli·
cation on the MC5446/7446 data sheet.

FIGURE 1 - TYPICAL INTERFACE CIRCUIT

7-Segment Indicator

7 -Segment I nd ieater

F rom Other Buffers

~

From Other Buffers

IL

IL = 25 rnA

=

25 rnA

2N4264
hFE(min) "" 25

I Load

I

FIGURE 2 - APPROXIMATE OUTPUT CHARACTERISTICS

u;

To Other Buffer Pairs

4.0r---r--'--~---r--'---'-~'---r--'---.

l.J

0

>

3.0

w
~

«

l-

.J

RBI

MC5448/7448

BI/RBO

0

2.0

>
l:J

"-

l:J

1.0

0

BCD Input

"

>

0
0

4.0

8.0

12

lL.oad, LOAD CURRENT (rnA)

16

20

•

MC5400/7400 series

BCD-TO-SEVEN SEGMENT
DECODER/DRIVER

MC5449F· MC7449F*

This device decodes 4-bit binary coded decimal input data in
a format suitable for use with incandescent, seven-segment, di$.
plav indicators. It is intended for use with other logic elements
or discrete components rather than for the direct driving of display indicators as is the case with the MC5446/7446, which is

A 5

similar.
Lamp intensity can be controlled by applying a variable duty
cycle signal to the blanking input.

11 a
'8 1

•

10 b
C 2

SEGMENT IDENTIFICATION
04

3
Blanking

9

c

B

d

6

•

NUMERICAL DESIGNATION - SEGMENTS ILLUMINATED

Input

13 f

8

9

10

12

11

13

14

15

12 9

I nput Loading Factor:
81 - 2.6
Other Inputs = 1
Vee == Pin 14
GND= Pin 7

Output Loading

Fac:~or:

a thru 9 = 6
Total Power Dissipation =
165 mW typ/pkg

TRUTH TABLE
DIGIT
OR
FUNCTION
0
1
2
3
4
5
6
7
B

9
10
11
12
13
14
15
1;11

xIII

Don

INPUT
D
Pin 4

C
Pin2

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0

x
t

0
1
1
1
1
0
0
0
0

1
1
1
1
X

B
Pin 1
0
0
1
1
0
0
1
1
0

0
1
1
0
0
1
1
X

care

F suffix = T0-86 ceramic flat package (Case 607).

BI

A
Pin 5

"Pin 3

a
Pin11

b
Pin 10

c
Ping

0
1
0'
1
0
1
0
1
0
1
0
1
0
1
0
1
X'

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0

1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
0
0

1
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0

1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0

OUTPUT
d
Pin 8
1
0
1
1
0
1
1
0
1

0
1
1
0
1
1
0
D,

e
Pin 6

f
Pin 13

g
Pin 12

1
0
1
0
0
0

1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0

0
0
1
1
1
1
1

l

0
1
0
1
0
0
0
1
0
0

P
1
1
1
1
1
1
1
0
0

s:

ELECTRICAL CHARACTERISTICS

n

0'1

Test procedures are shown for only one

~

data input and the. blanking input, and for
one drrver output and the ripple blanking
output. Test'a-theT ,inputs and outputs in

11

the same manner according to the truth

10

b

A

table. Test all input-output combinations

according to the truth table.

~

s(')"

9

B

2· C

d

4' D

6

3

13

BI

.....

t

8

cg
'TI
(")

o

12

:J

~.

:J
C

~

TEST CURRENT/vOL TAGE VALUES (All Temperatures)

Volts

mA

MC5449 Test Limits

Pin

10

0.4

2.4

5.5

2.0

0.8

5.0

4.75

5.25

2.4

TEST CURRENT/vOLTAGE APPLIED TO PINS LISTED BELOW:
VIL

VIH

-

1

-

-

-

mAde

-

0.4

Vde

9

56

mAde

1.0

Vde

-

mAde

-

mAde

9

-

0.4

14

-

47

IpD

2.4

MC7449

itAdc

1.0

VOL

Output
Output Voltage

VIHX

5.5

mAde

-

1

VCCH

4.5

40

pAde

IR2

VCCL

5.0

-1.6

mAde

40

1

VCC

0.8

-

-1.6

1

IHI

Vth 0

2.0

-

-

IF

Leakage Current

Vth 1

5.5

IOL

-

Input
Forward Current

Min

VIHH

2.4

Unit

Unit

Test

VIH

0.4

Max

Max

Symbol

VIL

10

MC7449 Test Limits
o to +70 oC

55 to+1250C

Under

Characteristic

IOl
MC5449

Min

VIHH

Vth 1

Vth 0

VCC

VCCL

VCCH

VIHX

Gnd
7

-

-

-

-

-

14

1

-

-

-

-

-

14

-

-

1

-

-

-

-

14

-

-

-

-

1,2,3,4,5

-

-

14

-

-

7

-

-

-

1,2,3,4,5

-

-

-

14

-

7

7
7

Power Requirements

(Total'Device)
Power Supply-Drain

Switching Parameters

-

Pulse In

Pulse Out

Turn-On Delay

tpd-1

5,9

-

100#

ns

-

100#

ns

5

9

-

-

-

-

14

-

-

1,2,3

4,7

Turn-Off Delay

tpd,l-1

5,9

-

100#

ns

100#

ns

5

9

-

-

-

-

14

-

-

3

1,2,4,7

Turn-On Delay

tpd_2

3,13

100#

ns

100#

ns

3

13

-

-

-

-

14

-

-

-

1,2,4,5,7

tpd+2

3,13

-

-

100#

ns

-

100#

ns

3

13

-

-

-

-

14

-

-

-

1,2,4,5,7

T urn-Off De lay

#Tested only at 25°C.

II

MC5449F, MC7449F (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
2.4 V

•

5.0 V

11
A

b

9

B

2
4
PRF = 1.0 MHz
PW = 100 ns
t+ = t- ~ 24 ns

50

3

C
D

BI

RL

10

d

8
6

TP out

13

lCT

12

r------t±==-3.0 V

RL = 1.0 kf2 for MC5449, 667 11 for MC7449.

CT

=

15 pF

=

total parasitic capacitance, which includes probe and wiring

''----0 V

capacitances.

·The coax delays from input to scope and output to scope must be
matched.

The scope must be terminated in 50-ohm impedance.

The

950-ohm resistor and the scope termination impedance constitute a 20: 1
attenuator probe. Coax shall be CT-070-50 or equivalent.

2.4 V
TP out

0.4 V

---+--t--------------r~-------GND

TP out

INPUT/OUTPUT VOLTAGE WAVEFORMS

OPERATING CHARACTERISTICS
o 2 4 6 8 10 12 14 0
A~

This monolithic integrated circuit provides the logic
necessary to decode a BCD input and drive a sevensegment numerical indicator. It is intended for use primarily as a driver for discrete, active components or logic
elements. Open collector outputs provide the capability
for wire DRing the outputs with other devices.
If direct driving of display indicators is desired, the
MC5446/7446 (30 volts maximum output voltage) or the
MC5447/7447 (15 volts) should be used, since they are
designed to handle the relatively high voltages and sink
currents (20 mAl of incandescent indicators_
Ripple blanking and lamp test inputs are not available,
due to the pin limitations of the 14-pin flat package. The
blanking input can be used in conjunction with external
gates to obtain suppression of non-significant zeros in a
multiple digit display. Design of zero-suppression systems
is discussed in Application Note AN-516.

B~

c~

Dl
L
BI----------------------,L
a~
b~

c~
d~
e~
f-'~

9----1

U

L

MC5449F, MC7449F (continued)

LOGIC "0" CONDITIONS

TYPICAL APPLICATION

This open-collector output device may be used to drive
other logic circuits by adding an external pull-up resistor
as shown. Maximum and minimum values for the external
resistor, RL, must be determined for the particular circuit
configuration. The maximum value will be determined by
the requirements for sufficient current to external' loads
when the decoder/driver output is high (logic "1"). The
minimum value must be selected to ensure that the current
through the resistor plus the current from external· loads
will not cause the low output voltage (logic "0") of the
decoder/driver to rise above the specified value.
The allowable drop across the load resistor, R L, for
the high state is the difference between Vee (5.0 volts),
and the required output voltage, VOH (2.4 volts) for the
MTTL gates. The current through the resistor is the sum
of the load currents, N I R 1, where N is the nu mber of gates
being driven and I Rl is the leakage current, 40 /lA for a
typical MTTL gate. From this, the maximum value of
; RL is
R (max) = Vee - VOH - 5.0 - 2.4 ""33 kQ
L
NIR12(40) 10-6
for two loads. Since the MC5449/7449 sink current,
IOL, is 10 rnA, the minimum value of R L in this case is
given by:
Vee - VOL
RL(min) = I
NI .
OL- F

5.0 - 0.4
[10 - 2(1.6)]10. 3

=680 Q

I
M C544917 449

---

81

BCD Inputs

LOGIC "1" CONDITIONS

MTTL

v CC o---'IIlIIr.....

MC544917449

~

BCD Inputs

81

MC5400/7400 series

EXPANDABLE DUAL
2-WIDE 2-INPUT
"AND-OR-INVERT" GATE

MC5450 • MC7450

Add Suffix F for TO·86 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7450 only.

This device consists of twoAND-OR-INVERT gates,
one of which OR expandable_ Up to four MC5460/
7460 expander gates may be ORed with the device at
the expander points_

CIRCUIT SCHEMATIC

1/2 OF CIRCUIT SHOWNt

•

Vee

rLAT] OIL
1.4 k

4k

4k

100

Pkg

Pkg

Pin

Pin

13]

9

15] 10
B [12]

[13] 13
[14]

1

Emitter [1] 11

e

Z

Collector [2] 12

o
A
B

0--+-+---+
0--+-+---+-+

[6]2~
3
.

[7]

1 k

[8]

4

[9]

5

6 [10]

Positive Logic:
Z = (A • 5)

E

+ (C

• 0)

+ (Expanders)

Negative Logic:

Gnd

Z = (A

= Pin 14 [4]
Gnd=Pin 7 [11]

+ 5)

• (C

+ 0) • (Expanders)

Input Loading Factor = 1
Output Loading Fa~tor = 10

Vee

Total Power Dissipation = 28 mW typ/pkg
Propagation Delay Time = 13 ns typ
tOther half of ~ircu'ft omits expander inputs.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
+5.0 Vdc
~--------3.0

V min

1.5 V
o V max

950
±.1.0%

2.4 V min

r---------,
I

·1.5 V

_+--l-~=::::!-:!::.i==O.4 V max
or Equiv

MM07000

PRF = 1.0 MHz

or Equiv

Duty Cycle = 50%
PW -0.5/L'

Zout""50

no
CT

= 15 pF "" total

parasitic capacitance, which includes probe, wiring, and load capacitances.

The coax delays from input ~o scope and output to scope must be matched. The scope must
be terminated in 50·ohm impedance. The 950·ohm resistor and the scope termination im·
pedance constitute a 20: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.

rL.AT] DIL

ELECTRICAL CHARACTERISTICS

Pkg
PH'

Test procedures are shown for only one

Pkg
Pm

''''~

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through remaining inputs.

(5] 10

B

(13J 13

C

(14]

D

1

EmItter [1) 11

E

COllector (2) '2

F

Characteristic

1612~
3

(7]

8 [12]

[8]

4

[9]

5

6

~

! 10]

U1

~O
TEST CURRENT JVOLTAGE VALUES (All Temperatures)
Ohms
Volts
VR2
VIH V1HH VRI
1X4 R,x® V,xCD V"

rnA
10L
MC5450
MC7450
MC7450 Test Limits
o to +70°C
Min Max Unit

MC5450 Test Limits
55 to +12n
Min Max Unit

n

U'1

S

V= Vee = Pin 14 [4J
Gnd = Pin 7 [IIJ

Pin
Under
Symbol Test

S

z

10"

IXI

Ix.

IX2

n

-.oJ

~

VthO

Vth1

Vee VCCl VCCH

16

I

-0.4

0.41

0.151 -0.151 0.3

138

0.'

10.4

2.4

5.5

4.5

5.0

I 2.0

0.8

5.0

4.50

16

1 -0.4

0.62

0.271-0.2710.43

130

0;4

10.4

2.4

5.5 1 4.5

5.0

1 2.0

0.8

5.0

4.75

I

Pin 7[ 11] is
5.50 grounded for
all
tests in
5.25
addition to
the pins listed
below:

TEST CURRENT /VOLTAGE APPLlED TO PINS LISTED BELOW,
10L

10H

IXI

1X4

Ix.

IX2

V,x(j)

R,x®

V1HH

V,"

V"

VR2

VRI

VthO

Vth1

Vee VCCl VCCH

Gnd

IF

Leakage Current

IR1

-

D

-

IR2

Expander Input Current

Base-Emitter Voltage

I

I
,

-

40

D

I - I

1.0

I

-

-1. 6

mAde

40

/lAde

1.0

I mAde I

mAde

I

I

I -3.1# I mAde I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

[

[

I

I - I

1. 0#

I

Vde

I

Z

I

I

I

I

0.4

I

Vde

I - I

0.4

I

Vde

I

Z

I

I

0.4

I Vde I

0.4

I

Vdc

2.4#

Vde

-55

mAde

-18

-20

ISC t

E

mAde

IpDH

V

I'

mAde

14

mAde

IpDL

V

8.0

mAde

8.0

mAde

'pd+

*Oround inputs to gate not under test.
** Tested only at 25°C.

D,Z

15**

15**

E

[

F

A,B,C*

V

I

A,B,C*

I

I

I

I

I

I

I

I

I

I

I

V

I

I

A,B,C*,D

I

I

I

I

I

I

I

I

V

I

I

A,B,C*,D

I

I- I

I

I C,D I

I

I

V

I

I

A,B*

I

I

I

V

A,B

V

A,B*

V

A,B,C*,D

I C,D

I
D

F

I

All
Inputs

D

A,B,C*,D,Z

V
V

I

A,B,C*,D

Pulse
Out

I

-

I

-

I

I

I

C

I- I

D,Z

t Only one output should be shorted at a time.

I

I

-

I

V

V

Pulse
In
'pd-

E,F

E,F

-

I

D

C

-55

Switching Parameters

Turn-Off Delay

I

Vde

Vde

I

Z

I

2.4#

I

I

1. 0#

Vde

I

I

I

2.4

I

I

®I

Vde

I

I

E

2.4

I

I

V BE

I

I

I

I

Z

I- I

I

mAde

,

-

D

I -2.9#1

VOL

V

C

-

CDI

Power Requirements
(Total Device)

Turn-On Delay

D

F

V OH

Power SupplyDrain

/lAde

D

Z®I

Short-Circuit Current

mAde

lEX

Output
Output Voltage

-1. 6

#Tested only at low temperature limit.

CD See Figure 1.
® See Figure 2.
@ See Figure 3 .

n0
:::J

!:t.
:::J

c::
CD

a..

Input
Forward Current

U'1
0

•

V

I

A,B*

V

I

A,B*

MC5450, MC7450 (continued)

FIGURE 2 - VBE TEST CIRCUIT

FIGURE 1 - lEX TEST CIRCUIT

l

FLAT] OIL
Pkg
[ Pkg
Pin

FLAT] OIL

Pin

r------,

Pkg
Pin

Pkg
Pin

(14J

1 I

I

(13J

131

I

(14J

r - - - - --..,
1
I

1~12J

(13J

I
1[12J
'8

(3J,,-=--C..r-'

•

[3J

[5J

0I0....=.---I"-'

[5J

-=- Vex

FIGURE 3 - VOL TEST CIRCUIT

r---[141...:....:..r-,
[13J

[ 3J
[5J

'O"::'--'-1-......

MC5400/7400 series

DUAL 2-WIDE 2-INPUT
"AND-OR-INVERT" GATE

MC5451 • MC7451

Add Suffix F for TO"86 ceramic package (Case 607).

Suffix L for TO-1l6 ceramic package (Case 632).
Suffix P for TO-t16 plastic package (Case 605) MC7451 only.

CIRCUIT SCHEMATIC

1/2 OF CIRCUIT SHOWN

OiL
rLAT]
Pkg
Pkg
Prn

Pin
Vee

'~

[3]
[5]

10'
f13] 13
4k

4k

L4 k

[14]

100

[6]

[8]

,
,

Z

8[12]

0

1

17]

e

:

'~

:

','

,,_,6 [10]

(9]

Z

o
A
B

<>--+-+--.....
<>--+-+----'-+-+
+ (C • DJ
+ ,8) • (C + D)

Posi,tive Log-ie: Z = (A ~ B)
:Negative Logic: Z =JA

,Input Loa<;ting Factor = 1

Gnd

Output Loading f!:actor = 10
Total Power Dissipation = 28 mW typ/pkg

Prop?gation Delay Time

Vee ~ Pin 14(4]
Gnd ~ Pin J (11]

= 13 ns'typ

SWITCHING TIME TEST CiR,CUIT ANDWAVEFORMS

r - - ,,--,,--.,.

950
±Lo%

I

,PRF = LO MHz
Duty Cycle = 50%
'PW ~ 0,5",
Zoul~50

Ground inputs to gate not u~~~r·te$t.>

-n
CT = ., 5:pF, = 'total parasitic capacitance, which

,nclud_s probe. wiring, ~nd load capacitances.

The coax delays from input to scope and output to scoRe must be matched. The scope must
be terminated" in 50·ohm impedance. The' 950"Ohm resistor and the scope termfnation impedance constitute a 20; 1 attenuator probe. Coax shall be CT -070-50 -or'eQuivalent.

ELECTRICAL CHARACTERISTICS

•

rLAT] OIL

Test procedures are shown for only one

Pkg

Pkg

Pin

Pin

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re-

"'"~

[5[ 10
[13] 13

maining inputs.

[14]

1

3:

n
(11
:

Z

[6[

[7[

8 [12]

[8]

0
[9]

~

~~""

-'

s:

n
~
(J1

-'

lot

IOH

VIL

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.50

5.50

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

5.0

4.75

5.25

Characteristic
Input

Symbol

Forward Current

IF

Leakage Current

rnA

Pin MC5451 Test limits
Under -55 to + 125°C
Test Min Max Unit

MC5451
MC7451
MCl 451 Test limits
o to +70°C
Min Max Unit

0-

TEST CURRENT !VOLTAGE VALUES (All Temperatures)
Volts
VIH VIHH
V.2
V,hO Vce
V.,
V'hl

v = Vee = Pin 14 [4]
Gnd = Pin 7 [11]

o

:J

~,

Vert

IOH

V'L

VIH

VIHH

V.,

-

D

-

-

C

-

-

D

-

-

D

-

-1. 6

mAde

-

-1. 6

mAde

lRI

D

-

40

/lAde

-

40

fJ.Ade

IR2

D

-

1.0

mAde

-

1.0

mAde

-

VOL

Z

-

0.4

Vdc

-

0.4

Vdc

Z

-

V OH

Z

2.4

-

Vdc

2.4

Vdc

-

Z

ISC t

Z

-20

-55

mAde

-18

-55

mAde

-

IpDH

V

14

mAde

-

14

mAde

IpDL

V

-

D

V.2

~

Pin 7[11] is grounded

for all tests in addition to the pins
listed below:

TEST CURRENT jVOlTAGE APPLIED TO PINS LISTED BELOW:
IOL

:J
C

VCeH

Vth1

V'hO

Vce

Vert

VCCH

Gnd

-

-

-

-

V

*

-

-

-

-

-

-

C,D

-

V

A,B,C*

-

-

V

A,B,C*

-

-

V

-

A,B*

D

-

V

-

A,B*

Output
Output Voltage

Shor" -Circuit Current

-

-

-

C

-

-

-

-

V

A,B,C*,D,Z

Power Requirements
(Total Device)
Power Supply Drain

-

8,0

mAde

-

8,0

mAde

Switching Parameters
Turn-On Delay

Turn -Off D el'ay

-

-

Pulse
In

Pulse
Out

-

-

All

Inputs

-

-

-

-

-

-

V

-

-

V

A,B,C*,D

t pd _

D,Z

-

15**

ns

-

15**

ns

D

Z

-

C

-

-

-

-

-

V

-

-

A,B*

tpd+

D,Z

-

22**

ns

-

22**

ns

D

Z

-

C

-

-

-

-

-

V

-

-

A,B*

.Ground inputs to gates not under test.
**Tested only at 25" C.
t Only one output should be shorted at a time.

MC540017400 series

EXPANDABLE 4-WIDE 2-INPUT
"AND-OR-INVERT" GATE

MC5453 • MC7453

Add Suffix F for TO·86 ceramic package (Case 607).
Suffix L for TO-116 ceramic pacland t""!J scope termination impedance con'stitute a 20: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.
>

r

FL.AT] DIL
Pkg
Pkg
Pin

Gnd = Pin

7

f 11 J

A

Collector

1~~0_~12[2]

[6]

2

e

32_\ 11

3

0

Emitter

[8]

CJ1

.j::o

43=imittec

-..s

~
TEST VOLTAGE VALUES (All Temperatures)

MC5460
MC7460

IF

B

-

-1. 6

Leakage Current

1m

B

-

IR2

B

Volts

Ohms
REX 1

Forward Current

(")

o

[13]

:ollector

Symbol

n

.j::o

--\9

Characteristic
Input

s:

pander being tested. To complete testing,
sequence through remaining inputs.

[I]

. - - " 10 [14]

Pin MCS460 Test Limits
-SS to +12ST
Under
Test Min Max Unit

(j)

~O

are shown for only one input of the ex-

[5]

[7]

V" Vee" Pin 14 [4]

s:(")

expander. The other expander is tested in
the same manner. Further, test procedures

Pin

[31 13

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

REX 2

Vil

V,H V1HH

V.2

Vfh

1

=.
:::l

VlhO VOl V02 V03 Vee Ven

VeeH

:::l

pin 7[ 11] is
grounded for
all tests in
addition to
the pins listed
below:

1.2 k*

1. 1 kl

0.4

2.4

5.5

4.5

5.0

2.0

0.8

4.5

1.0 0.85

5.0

4.50

5.50

1.2 k*

1. 1 kl

0.4

2.4

5.5

4.5

5.0

2.0

0.8

4.5

1.0

5.0

4.75

5.25

VlhO VOl V02 V03 Vee VCCL

VeeH

Gnd

MC7460 Test Limits
o to +70°C
Min

V. ,

0.85

TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
REX

REX 2

Vil

V'H V,HH

V. ,

Max

Unit

mAde

-1. 6

mAde

40

IlAde

40

vAde

-

1.0

mAde

1.0

mAde

-

-

B

-

-

0.4

Vdc

0.4

Vdc

ZO

-

-

-

150§

IlAde

270§

IJ.Ade

ZI

-

-

A,C,D

mAde

-

-

-

I

-

B

-

-

B

-

V.2

V,h I
-

A,C,D

-

-

V

-

-

-

-

V

A,C,D

-

-

-

-

V

A,C,D

-

ZI

-

-

V

-

-

ZO

-

-

ZI

-

-

-

-

-

-

-

-

-

A,B,C,D

-

c:

CD

a.

Output
Output Voltage

VOLt

ZO,ZI

Leakaf:',€ Current

I CEX

ZO

Drive Current

IDR

ZI

-0.3§

IpDL

V

-

4.0

mAdc

-

4.0

mAdc

IpDH

V

-

2.5

mAde

-

2.5

mAde

-

mAde -0.43§

-

-

-

A,B,C,D

B

-

V

-

V

-

-

V

All Inputs

-

V

-

Power Requirements
(T otal Device)
Power Supply Drain

Switching Parameters

Turn-On Delay

Turn-Off Delay

t pd _

tpd+

*Resistor to ground.

tResistor to VCCL·
#Sce test circuit.

-

All
Inputs

-

-

-

-

ZO

A,C,D

-

-

-

-

-

-

-

-

V

A,C,D

-

-

-

-

-

V

-

-

-

-

ZI

Pulse
In

#

20**

ns

-

20**

ns

B

#

34**

ns

-

34**

ns

B

---

-

-

-

'

~ --~

tVOL measured between pins 11 and 12.
§Tested only at low temperature limit; i. e., at _55°C for MC5460, at O°C for MC7460.
**Tested only at 25" C; times include delay of expandable gate.

-

-

-

-

-

•

~------~.--~~-~~~

MC5400/7400 series

"\

\.._-------'

J-K FLIP-FLOP

MC5470L'I'
MC7470L,P'I'

This J-K flip-flop triggers on the positive edge of the clock pulse_ The
multiple-input gating configuration helps minimize package count in J-K flip-flop
applications requiring AND gating at the inputs. This device requires relatively
fast clock rise and fall times ( :s: 150 ns) but is more suitable for use in high-speed

SET 13
Jl

3

J2

4

°

J*

5
CLOCK 12
K* 9
Kl 10

•

8

hold times_ The inputs are inhibited when the clock is high; data is entered into

the input steering section when the clock goes low. The input steering section

5.

6

2

tn

oil

continually reflects the input states when the clock is low. The flip-flop can be
set or reset directly by applying a logic "0" to SET or RESEi'. respectively. while
clock is at logical zero level

K2 11

RESET

systems since information may be applied to, or changed at the steering inputs
any time in a clock cycle except during the interval of time between the setup and

J

K

0
0
1
1

0
1
0
1

tn+1
Q

On
0
1

Output Loading Factor"" 10
J

=

Total Power Dissipation = 65 mW typ/pkg
J1 • J2 •

ji

= 30 ns typ
= 35 MHz typ

Pl'"opagation Delay Time

K=K1. Kl.~

Operating Frequency

an

L suffix = TO-116 ceramic package (Case 632)
P suffix = TO-116 plastic package (Case 605)
See General Information section for package outline dimensions."

7

4k

SET

13

9

K*
10
Kl
K2
11
CLOCK
12

4k

4k

4k

4k

4k

~~'---K~~
~~;r
~
~
.~~ ~
0.8 k

~

REsET
2

5
J*
3
Jl
J2

4

MC5470L, MC7470L,P (continued)

OPERATING CHARACTERISTICS

logic "1"; a low input to RESET sets Q to

Data present during the time interval between the Setup and Hold times is transferred to the bistable section on
the positive edge of the clock pulse. Steering data should
be present 20 ns prior to rise of the clock and remain 5.0 ns
after the clock signal rises.
The direct SET and RESET inputs should be applied
only when clock is low. A low input to SET sets Q to a

a logic "1".

Unused inputs: If J* and K* are not used they should be
grounded. Unused SET and RESET inputs should be tied
to a voltage between 2.4 and 5.5 Vdc.
Unused J or K inputs should be tied to the used J or K inputs, respectively, or to a voltage between 2.4 and 5.5 Vdc.

SWITCHING TIME TEST CIRCUIT

2.4 V

Vee

O.B V

+5.0 V
.. 'to

A load is connected to each
output during the test.

r - - - - - -

- - --,

400

II
I

TP out
MMD6150
or Equiv.

MMD7000
or Equiv.

Two pulse generators are required and must be slaved together for testing
Only one pulse generator is required for~. K, and CLOCK tests.

ffi and

RE"SEf.

The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 9S0-ohm resistor and the
scope termination impedance constitute a 20:1 attenuatar probe. Coax shall be
CT-070-50 or equivalent.

CT := 15 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.

TEST PROCEDURES
(Letters shown in test columns refer to waveforms,)

SYMBOL

TEST
Toggle Frequency

INPUT

C

J

tTog

E

2.4 V

tpd_

.

Q

Q

2.4 V

t

J*

K*

R

S

2.4 V

Gnd

Gnd

2.4 V

K

LIMITS
Min

Max

Unit

t

20

-

MHz

O.BV

5.0 V

5.0 V

Gnd

Gnd

A

B

-

50

ns

O.B V

5.0V

5.0 V

Gnd

Gnd

A

B

e
e

D

tpd+*

D

-

50

ns

Turn-On Delay from Clock

tpd_

E

2.4 V

2.4V

Gnd

Gnd

5.0V

5.0 V

H,I

H.I

10

50

ns

Turn~Off

tpd+

E

2.4V

2.4 V

Gnd

Gnd

5.0V

5.0 V

H.I

H.I

10

50

ns

Minimum Input Setup Time at J*

tsetup

E

2.4V

2.4 V

F

Gnd

5.0V

5.0 V

H,I

H.I

-

20

ns

Minimum Input Hold Time at J1, J2

tHold

E

G

2.4 V

Gnd

Gnd

5.0 V

5.0 V

H,I

H,I

-

5

ns

Turn~On

Delay from SET or RESET

Turn-Off Delay from SET or RESET

Delay from Clock

....

tOutput shall toggle with each Input pulse
·SET or R'E'SE'T function can occur only when .clock input is low. Other gates are inhibited.
* *, dentical teSt to be performed on K 'nput.

*

•

MC5470L, MC7470L,P (continued)

VOLTAGE WAVEFORMS AND DEFINITIONS

3.0 V
TPin

A

•

FfESE'f
PRF

=

1.0 MHz

OV
25 nsmin

3.0 V
TPin
B

SE'f
PRF "" 1.0 MHz

OV
tpd_

2.4 V
C

TP out

1.5 V

Q

GND
D

TP out
Q

GND
E

0.4 V

J

1.5 V

"{

2.4 V

0.4 V

TPin
CLOCK
PRF = 1.0 MHztt

ov
-------"""':4-----+----------3.o v

TPin

J*
~~---+_-----------ov

--------------4---"""',+-~----3.0V
G

T?in

J,K

1'"-'-=---0 v
6.0 ns
---------------+--"""'.--------~2.4 V

H

TP out
Qor Q

GND---------------+---~~'====== ';;0.4 V

t
TP out
Oor

a.

Pd

+)

·~----~2.4

V

1.5 V

GND==================:::'''======== ';;0.4 v

ttPRF varies when,testing fTog"

s:

ELECTRICAL CHARACTERISTICS

n

Test procedures are shown for only one J
and one K input. plus the SET. RESET.
and CLOCK inputs. To complete testing.
sequence through remaining J and K in-

U1

~

......

o
r-

puts in the same manner.

~

s:

n
......

SET

:!:j
o
r-

13----------------~

~~=~

J*

5

"'-

<',
..
...
no=,,~
K1 10
K2 11

RESEi'

.

a

:

IOL

2

.
Pin

.
MC5470 Te~t Limits

Test

IF

1~

Min

IOH

VIL

VIH

~

VIHH

VR

Vt hl

VthO

!:!"
~

VCCL

c:

VCCH

MC5470

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

4.5

5.5

MC7470

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

4.75

5.25

MC7470 Test Limits

-55 to + 125°(:

Under
Symbol

0o

TEST CURRENTIVOLTAGE VALUES (All Temp... ture,)
Volts

mA

6

.

Characteristic

"

8

'

~

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTeD BELOW:

0° to +70°C

Max

Unit

Min

=~:~

mAjdC

::
-

Max

Unit

tOl

IOH

Vil

VIH

VIHH

=~:~

mAtdC

::
-

::
-

130
13
2
12
12

::
-

::
-

VR

V t hl

VthO

VCCL

VCCH

Gnd

::
-

::
-

::
-

lt4

5'j7'9

Input

ForwardCurrent"

~

sot

13
·2
12
12

·Reset
Clock
Leakage Current**

J

I A1

-

~Adc

-

3.4,10,11
3.4.10,11
2',3,4,10,11
3.4.10,11,13'

...,...

40

-

40

-

-

-

3

-

5

-

-

-

14

2,4,7

40
80
80
40

~

-

40
80
80
·40

~

-

-

-

10
13
2
12

-

9
9
5
-

-

-

-

~

7.11,13
7,10,11
7,10,11
3.4,7

,30
'3
2
12

::

't·O

mAtdC

::

I ·O

mAtdc

::

::

::

::

::

::

l4

t

-

-

-

::
,30
13
2
-'2

~

-

9
5
-

-

-

-

t

7:'0:11
7,10,11
7

VOL

6
8

-

-

0.4
0.4

6
8

-

-

-

-

-

2
13

13
2

14
14

-

7,12
7.12

VdH

6
8

2.4
2.4

-

Vdc
Vde

2.4
2.4

-

Vdc
Vde

-

6
8

-

-

-

-

13
2

2
13

14
14

-

7,12
7,12

ISC

6

-20

-57

mAde

-18

-57

mAde

~

~

13

-

-

-

-

-

-

14

5,7,9,12

8

-20

-57

mAde

-18

-57

mAde

-

-

2

-

-

-

-

-

-

'4

5,:1,9,12

14

-

26

mAde

-

26

mAde

-

-

-

-

-

-

-

-

-

14

2,7,12

14

-

26

mAdc

-

26

mAde

-

-

-

-

-

-

-

-

-

14

7,12,13

IR2

sot
Reset
Clock

Power Requirements
Power Supply Drain

I
t

;~~i~~i~~

-

Reset
Clock

Short-Circuit Current

~Adc

-3.2

3

~

Output
Output Voltage

-3.2
-3.2
-1.6
-1.6

10
13
2
12

!S.-

~

::
-

IpO

0.4
0.4

Vdc
Vdc

Vdc
Vdc

*Momentarily ground pin prior to taking measurement.
"'*When testing J* or K* other inputs are left open.

•

I

/ii'~3.
i

'\

MC5400/7400 series

'-------------'

J-K FLIP-FLOP

MC5472 • MC7472

Add Suffix F for TO-S6 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7472 only.

rLAT] OIL

•

Pkg

Pkg

Pin

Pin

This negative-edge-clocked J-K flip-flop operates on the master-slave
principle. Three K inputs are ANDed together, and three J inputs are
ANDed together. SET and RESET inputs are also availab[e. The device
helps minimize package count in J-K flip-flop applications requiring AND
gating into the J or K inputs.

Vee - Pin 14 [4]
Gnd-Pin 7 [II]

[3] 13
[7]

3

[8]

4

[9]

5

8 [12J

[2] 12
[14]

9

6 [10]

[I] 10

LOGIC DIAGRAM

[13] 11
[5]

2

Q

Q

J - Jl • J2 • J3
K = K1 • K2 • K3

Input Loading Factor:

J, K-l

In

In+l

J

K

Q

0
0
1
1

0
1
0
1

a"

Clock, Set, 'R'8s8t= 2

0
1

an

so-t-.==-....

,--=::'--+-0 R
Jl

Kl
K2
K3

J2
J3

Output Loading Factor = 10
Total Power Dissipation = 40 mW typ/pkg
Propagation Delay Time"" 30 ns typ
Operating Frequency = 20 MHz typ

CIRCUIT SCHEMATIC
r-----~----~~--------_.------~r---~~----------~Vee

Q

Set

5.

'R"8s8t

Kl

Jl

K2
1<3

J2
J3

s:

ELECTRICAL CHARACTERISTICS

("')
0'1

Test procedures are shown for only one J

f';-k~T]

LPin

-'....
="

and one K input. plus the Set, Reset, and
Clock inputs. To complete testing, seOIL

v

Pkg

~

Pin

,N

quence through remaining J and K inputs
in the same manner.

Vee ~ Pin 14 [4]
Gnd "" Pin 7 (11 J

s:
("')
....

[3] 13 ____________- ,
[7]

3

[8]

4

[9]

5

[2] 12
[14]

....N-'="

8 [12]

t

n-O

Cj

....

:J

9

[1]10~6[10]

[13] 11
[5]

mA

2

Characteristic

TEST CURRENT (VOLTAGE VALUES (All Temperatures)
Volts
VR
V,hl V'hO VCC VCCL VCCH
VIL VIH VIHH

10L

10H

MC5472 16
MC7472 16
Pin MC5472 Test limits MC7472 Test limits
o to +70'C
55 to +125'C
Under
Symbol Test Min Max Unit
Min Max Unit 10L

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

4.50

5.50

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

4.75

5.25

10H

VIL

VIH

VIHH

-

-

-

Jl
Kl
S
R
C
C

-

-

-

-

Jl
Kl
S
R
C

TEST CURRENT (VOlTAGE APPLIED TO PINS LISTED BElOW:
VR

V,hl

V'hO

J

K

IF

set
Reset
Clock

Leakage Current

J

K

IRI

Set
Reset

CloCk

.J
K

IR2

set

Reset

Clock

Output
Output Voltage

Short-Circuit Current

VOL

Jl
Kl
S
R
C
C
Jl
Kl
S
R
C**
Jl
Kl
S
R
C

-1. 6
-1. 6
-3.2

~
40
40
80

-

mAde

I

-1. 6
-1. 6
-3.2

-

/-lAde

-

+

1

1.0

mAde

-

1 1

-

~
40
40
80

+
1.0

-

mAde

I

/lAde

1

-

-

1 1

-

-

-

-

-

Q
Q

-

-

0.4
0.4

Vdc
Vdc

Q

-

2.4
2.4

-

Vdc
Vdc

2.4
2.4

-

Vdc
Vdc

-

Q
Q

-20
-20

-57
-57

mAde
mAde

-18
-18

-57
-57

mAde

mAde

-

V
V

-

12
12

mAde
mAde

-

-

12
12

mAde
mAde

-

V OH

Q
Q

ISC t

IpD

-

-

-

-

-

-

Vdc
Vdc

Q

-

mAde

0.4
0.4

Q

Power Requirements
Power Supply Drain

-

C.J2.J3.R*
C,K2,K3,S*
C,J1,J2.J3,Kl ,K2.K3
C ,Jl,J2,J3,Kl,K2.K3
J1 ,J2 ,J3 ,Kl ,K2 ,K3,R*
J1 ,J2 ,J3 ,Kl ,K2 ,K3 ,S*

-

-

Q

-

-

-

-

-

-

-

-

-

-

-

-

-

-

~

Pin 7[11 J is grounded
for all tests in addilion to the pins
listed below:

Gnd

-

-

-

-

-

-

-

-

-

-

c:

Vcc VCCL VCCH

Input
Forward Current

:J

-

-

V

I
V

C,J2,J3,R
C.K2,K3.S
C.Jl,J2,J3
C.Kl,K2,K3
C,Jl,J2.J3,Kl,K2,K3,R

-

1

-

V

-

-

1

-

V
V

-

-

V
V

-

-

-

-

-

-

-

-

J1
Kl
S
R
C

-

-

-

R
S

S
R

-

-

-

-

S
R

R
S

-

-

-

Jl,J2,J3,Kl,K2,K3
JI,J2,J3,Kl,K2,K3

-

-

-

-

-

V
V

C,Q,R
C,Q,S

-

-

-

-

-

-

-

-

~I

-

-

R
S

-

-

*Momentarily ground pin prior to taking measurement.
tOnly one output should be shorted at a time.
**Under normal operating conditions this current is negative. This test guarantees that positive leakage current will not exceed the limit shown .

•

-

-

C.J2,J3,R
C.K2,K3,S
C,Jl,J2,J3
C,Kl,K2,K3
C ,Jl,J2,J3,Kl,K2.K3,S

MC5472, MC7472 (continued)

TEST PROCEDURES
(Numbers shown in test columns refer to waveforms.)

TEST

SYMBOL

Toggle Frequency

INPUT

Q

1!

J, K

R

5

fTog

1

1

2.4 V

2.4 V

Turn-On Delay

tpd-

2

2

2.4 V

2.4 V

Turn-Off Delay

tpd+

ttssd+d-

2

2

2.4 V

2.4 V

2.4 V

2.4 V

5 -

6

2.4 V

2.4 V

5

6

Enable Voltage

VEN

2

2.0 V

2.4 V

Inhibit Voltage

VINH

2

0.8 V

2.4 V

Turn-On Delay
Turn-Off Delay

a

LIMITS
Min

Max

Unit

t

15

-

MHz

3

3

10

40

4

4

10

25

7

8

-

40

7

8

2.4 V

t

t

t

-

2.4 V

:/:

:/:

:/:

-

t

25

tOutput shall toggle with each mput pulse.
iOutput shall NOT toggle.

VOLTAGE WAVEFORMS AND DEFINITIONS

" . . - - -....- - - - - - - - - 3.0 V

'-------0 V

---------t---,------2.4
3

TP out

Gnd---------t---------

V min

0.4 V max

~---2.4Vmin

4

TP out

Gnd ===================0.4

V max

,------------3.0 V
1.5 V

'------"'--(----------------0 V

3.0 V

'-------'--(----0 V

, - - - - - - - - 2 . 4 V min

7

TP out

__+___
Gnd Jsd
+ -------.

-=========:j::~=========:O.4

_

8

TP out

.--t--------2.4

V max
V min

1.5 V

Gnd===~:.....---------------~=======O.4 V max

nsns
nsns
-

MC5472, MC7472 (continued)

OPERATING CHARACTERISTICS

Data must be applied to the J-K inputs while the clock is low.
When the clock input goes to the positive logic "1" state, the data
at the J and K inputs is transferred to the master section, where it
is stored until the clock changes to the positive logic "0" state,
Data at the J and K inputs must not b. changed while the clock is
high. When the clock returns to the positive logic "0" state. information in the master· section is transferred to the slave section.
Application of a logic "0" to the R.set input will force the Q
output to the logic "1" state. The Reset input overrides the clock.

Since no charge storage is involvedin this flip-flop. rise and fall
times are not important·to its operation. Clock fall times as long
as 1.0 I-IS will not adversely affect the operation of tha flip-flop.
The clock pulse need only be wide enough to allow the data to
settle in the master section. This time, which is the setup time for
a logic u1", is 20 ns minimum.
Transistors QA have been added to the standard flip-flop circuit
to protect the device against negative clock transients. This addition prevents both outputs from changing to the logic "'" state
when transients in excess of -2.0 V appear at the clock.

SWITCHING TIME TEST CIRCUIT

Vee
+5.0 Vdc

400

MMD6150
or Equiv.

50

t+=10ns
t- ... 5 ns
PA F = 15 M Hz for waveform 1
1.0 MHz for waveforms 2, 5, and 6

r

Two -pulse generators are required and must b!=t sla\led together for testing Set and
ReSet. Only one f),ulse generator is required for J, K, and Clock tests.
-The coax delays from input to scop.., and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20:1 attenuator probe. Coax shall be
CT -070-50 or equivalent.
* • A load is connE!'cted to each output during the test.

CT "" 1 5 pF :: total parasitic capacitance. which includes probe, wiring, and load
capacitances.

MMD7000
or Equiv.

•

,---1

"
DUALJ-K FLIP-FLOP

MC5400/7400 series

'--"------~

MC5473 • MC7473

Add Suffix F for TO~86 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 605) MC7473 only.

12
14=0=0.
a
1

C

3

K

13

R

7yO9
5

This negative-edge-clocked dual J-K flip-flop operates on the masterslave principle. The device is quite useful for simple registers and counters where multiple J and K inputs are not required.

C

1:

KRa

8

LOGIC DIAGRAM
(1/2 OF DEVICE SHOWN)

2

tn

tn+1

J

K

Q

0
0

0
1
0

an

o

Q

...-==......+-0 R'eS8t

1
11 1

Input Loading Factor:
J, K ~ 1

0

an

Reset, Clock"" 2

K

Output Loading Factor = 1 0
Total Power Dissipation::::; 80 mW typ/pkg
Propagation Delay Time:::: 30 ns typ
Operating Frequency = 15 MHz typ

Pin numbers are the same in all packages.

LOGIC DIAGRAM
(112 OF DEVICE SHOWN)

00---+--....

.....---~a

~-

L---------~----------~------~~--------~--------~t-----+_OGnd

L--.------------------------~~-.----~Reset

K

s::
(")

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one
flip-flop. The other flip-flop is tested in

CTI

.j::Io

the same manner.

14=0=012
1

C

3

K

(5

13

-..J
,CN

7=JJ09
5

C

10

K

R

5

s::

(")

-..J

.j::Io

8

R

mA

Pin
Under
Symbol Test

Characteristic
Input
Forward Current

J
K

IF

Reset
Clock
Leakage Current

J
K
Reset

K

K

R
C
IR1

J
K

R

ct

Clock

J

J

IR2

J
K

Reset

R
C

Clock

MC5473 Test limits
55 to +125'C
Min Max
Unit

MC5473
MC7473
MC7473 Test limits
o to +70°C
Min Max
Unit

-

-1. 6
-1. 6
-3.2
-3.2

mAde

-

40
40
80
80

!lAde

~

-

1.0

mAde

-

-

~

~

~

-

-1. 6
-1. 6
-3.2
-3. 2

mAde

-

40
40
80
80

~LAdc

-

1.0

mAde

~

~
~

IOL

10H

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

10L

10H

VIL

-

-

-

J

-

-

Short-Circuit Current

VIHH

V.

-

-

R
C

-

-

C,R
C,R
C,J
J,K,R

-

-

J

-

-

K

-

-

-

K

-

-

-

~

-

-

-

-

-

R

-

J

-

K

R

-

-

Pin 11 is grounded

for all tests in addi-

VCCL

VeCH

-

-

-

-

-

-

-

-

-

-

V

Q

~

Q

-

V

-

Q

-

R

R

-

-

-

VOH

Q
Q

2.4
2.4

-

Vdc
Vdc

2.4
2.4

-

Vdc
Vdc

-

-

-

Q
Q

-

Q

-20
-20

-57
-57

mAde
mAde

-18

-57
-57

mAde

-

-

-

-

-

-

C,J,K

mAde

C,J,K

-

-

40
40

mAde
mAde

40
40

mAde
mAde

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

R
R

-

Gnd
-

-

C,R*
C*
C,J*
J*,K,R
C,R*
C*
C,J*
J*,K,R

~

Q

V
V

-

Q

V
V

-

Q

C,J*,K
C,J*,K

-

V
V

-

Q,Q*

V
V

-

Both R Inputs

BothQ

-

-

-

R

-

-

-

-

-

-

-

-

-

-

**

-

-

-

-

Vee

-

-

-

-

listed below:

V'hO

-

-

-

V'hl

-

R
C

Q
Q

-

.....

tion to the pins

~

Vdc
Vdc

-

5.25

V

0.4
0.4

-

4.75

-

-

V
V

::::l
C

-

Vdc
Vdc

IpD

5.50

-

0.4
0.4

-18

4.50

-

-

Q

::::l

-

-

Q

ISC'

VeCH

-

R
C

Q

Power Requirements
(Total Device)
Power Supply Drain

VIH

VOL

-

to)

n-O

TEST CURRENT jVOlTAGE APPLIED TO PINS LISTED BElOW:

Output
Output Voltage

TEST CURRENT jVOlTAGE VALUES (All Temperatures)
Volts
Vil
V,h 1 V,hO Vee VeCL
VIH VIHH V.

-..J

-

R

-

C,J*,K
C,J*,K

R,Q*

*Ground inputs to flip-flop not under test.

**Momentarily ground pin prior to taking measurement to set flip-flop in the desired state. (If pin is also in another column, the pin must be returned to that voltage or current for measurement.)
tOnly one output should be shorted at a time.
tUnder normal operating conditions this current is negative. This test guarantees that positive leakage current will not exceed the limit shown .

•

ro

a.

MC5473, MC7473 (continued)

OPERATING CHARACTERISTICS

•

Data must be applied to the J-K inputs while the clock is low.

Since- no charge storage is involved in this flip-flop', rise and fall

When the clock input goes to the positive logic "1" state, the data
at the J and K inputs is transferred to the master section. where it
is stored until the clock changes to the positive logic "0" state.
Data at the J and K inputs must not be changed wh He the clock is
high .. When the clock returns to the positive logic "0" state. information in the master section is transferred to the slave section.

times are not important to its operation. Clock fall times as long
as 1.0 I'S will not adversely affect the operation of the flip-flop.
The clock pulse need only be wide enough to allow the data to
settle in the master section. This time, which is the setup time for
a logic ",", is 20 ns minimum.
Transistors QA have been added to the standard flip-flop circuit
to protect the device against negative clock transients. This addition prevents both outputs from changing to the logic "'" state
when transients in excess of -2.0 V appear at the clock.

Application of a logic "0" to the Reset input will force the Q
output to the logic "1" state. The Reset input overrides the clock.

SWITCHING TIME TEST CIRCUIT

Vee
+5.0 Vdc

Coax

400

Q

o--+--qe

MMD6150

or Equv.

Q

K
R
50

MMD7000

or Equiv .

t+=12nS}
t- = 6.0 ns
10% to 90% Points

• A load is connected to each output during the test.

f = 15 MHz for waveform 1
1.0 MHz for waveforms 2 and 3

Two pulse generators are required and must be slaved together for tsd tests.
CT = 15 pF = total parasitic capacitance, which

inclu~es p~obe,

wirinQ, and load capacitances.

The coax delays from input to scope and output to scope must be matched. The scope must
be terminated in 50-ohm impedance. The 950-ohm resistor and the scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.

MC5473, MC7473 (continued)

TEST PROCEDURES
(Numbers shown in test columns refer to waveforms.)

INPUT
TEST

SYMBOL

Q

c

J, K

R

1

2.4 V

t

Toggle Frequency

fTog

1

LIMITS

Q
t

Min

Max

Unit

15

-

MHz

Turn-On, Delay

tpd-

2

2

2.4 V

4

4

10

40

ns

Turn-Off Delay

tpd+

2

2

2.4 V

5

5

10

25

ns

Turn·On Delay

tsd-

2

2

3

6

7

-

40

ns

Turn-Off Delay

'sd+

2

2

3

6

7

-

25

ns

Enab'le Voltage

VEN

2

2.0 V

2.4 V

t

t

t

-

-

2.4 V

t

t

:j:

-

-

Inhibit Voltage

VINH

2

0.8 V

tOutput shall toggle with each input pulse.
:j:Output shal1 NOT toggle.

VOLTAGE WAVEFORMS AND DEFINITIONS

3.0 V
1,2

TPin
OV

3

3.0V

TPin

ReSet

2.4 V min

4

TP out

0.4 V max

Gnd

2.4 V min

5

TP out
0.4 V rna"

Gnd
2,4 V min

6

TP out
0.4 V max

Gnd

TP out

Gnd

\

2.4 V min

0.4 V max

I

~~__________________M_C_5_4_00_1_7_4_00__se_r_ie_s~

QUAD LATCH

MC7475p·

This device consists of four bistable latch circuits in one 16-pin package_ Both a and outputs are available on all four devices_ When the
strobe is in the logic "1" state, the a output will follow the state of the
data input. When the strobe goes to the logic "0" state, the a output
will retain the state of the data input at the time of the transition from
the logic "1" state.

a

DO 2

16

QO

60
Dl

•

Strobe
D2

D3

Strobe

3

15

Ql

13

14

61

9

Q2

8

62

6

10

Q3

4

11

63

7

tn
0

Qt Q

1
0

o

LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN; STROBE COMMON TO TWO LATCH SECTIONS)

tn+l

1

I

0
1

13
Strobe

Input Loading Factor:
D=2

Strobe = 4
Output Loading Factor

Vee = Pin 5
Gnd :: Pin 12

= 10

Total Power Dissipation = 160 mW typ/pkg
Propagation Delay Time

2
D

16- Pin Package

= 30 ns typ

• P suffix = 16-pin plastic package (Case 612)
See General Information section for package outline dimensions.

1/4 OF CIRCUIT SHOWN
(STROBE COMMON TO TWO LATCH SECTIONS)

Vee

r-----._-----1------~~------._----~----_.------_.------~----_.---05

16

a

Q

1

~--+_------~------~~--~----------+_r_------~------~--~~--o12

Gnd

13
Strobe

2
D

MC7475P (continued)

OPERATING CHARACTERISTICS

Data present on the 0 input between the setup and hold times
will be transferred to the Q output when the strobe input changes
from the logic "0" state to the logic "1" state. As long as the strobe
remains in the logic "1" state, the Q output will follow the state of

the D input. When the strobe input changes from the logic "1"
state to the logic "0" state, data present on the 0 input between
the setup and hold times will be retained on the Q output until the
strobe returns to the logic "1" state.

•

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
+5.0 Vdc

Coax·

950± 1.0%
D

Q

MMD6150
or Equiv
~ 15 ns (10% to 90% Points)
Duty Cycle = 50%
Zout = 50 n

t- = t+

50

ST

MMD7000
or Equiv

•• A load is connected to each
output during the test.

Two pulse generators are required and must be slaved together to provide the waveforms shown.

*The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT -070-50 or equ ivalent.
CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.

TPln

Strobe
PRF = 0.5 MHz
Gnd

TPin
PRF

OV
3.0 V

DATA
= 1.0 MHz

Gnd

OV

2.4 V max
TP out

Q

TP out

a

Gnd

0.4 V min
2.4 V max

Gnd

•

ELECTRICAL CHARACTERISTICS

s:

n

Test procedures are shown for only one

"~U'1

latch. The other latches are tested in the

same manner.

D2i16
D

3

""C

a

1

8'

Q

15

!:!".

a

14

:l
:l

D7£i9

STROBE

D

13

6

c:

CD

Co

a

8

~

10

11

IOL

IOH

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
V
V
V
Vth1 VthO VCC
IH
IHH
R1
V'L

16

-0.4

0.4

rnA

Characteristic
Input

Pin MC747S Test Limits
oto +70"(
Under
Symbol Test Min Max Unit
-

VIH

VIHH

VR1

-

-

2
13

-

-

-

13

-

2
13

-

-

-

-

-

-

--

1.0
1.0

mAde
mAde

-

-

1
16

--

0.4
0.4

Vde
Vde

1
16

-

VOH

1
16

2.4
2.4

-

Vde
Vde

1
16

ISC

1
16

-18
-18

-57
-57

mAde
mAde

-

IpD

5

-

49

mAde

-

~1

2
13

~2

2
13

VOL

Output

Short-Circuit Current

VIL

/LAde
/LAde

Leakage Current

-

Output Voltage

IOH

80
80

2
13

4.5

IOL

mAde
mAde

IF

5.5

2.0

0.8

5.0

VCCH

4.75

5.25

VCCL

VCCH

Gnd

-

5
5

12
12

5
5

12,13
2,3,12

5
5

12,13
2,3,12
12
12

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

-3.2
-3.2

Forward Current

2.4

VCCL

-

-

-

Vth1

VthO

-

2
13

-

-

-

-

-

2,13
13

2

Vcc
-

-

-

-

--

5
5

13
2,13

2

5
5

-

-

5
5

1,2,12
12,16

-

-

2,3,4,6,7,12,13

-

-

-

-

-

-

13
2,13

-

-

-

-

-

-

-

-

-

-

-

5

-

-

-

12
12

Power Requirements
(Total Device)
Power Supply Drain

~~_________________M_C_5_4_0_0_17_4_0_0_s_e_ri_es~

DUAL J-K FLIP-FLOP

MC7476P*

2D

SET
J

4

a

CI:OCK

1

_

K 16

a

Rem

15

to

14

3

'0

SET

9

CI:i5CK
K

This negative-edge-clocked dual J-K flip-flop operates on the masterslave principle. The device is quite useful for simple registers and counters where multiple J and K inputs are not required. Available only in the
l6-pin package, this device provides both SET and RESET inputs on
both fl ip-flops in the package.

;:

Rem

Q

11

a

10

tn+l

J

K

Q

0
0
1

0
1
0

an

1

1

lln

0
1

•

LOGIC DIAGRAM
(112 OF DEVICE SHOWN)

Input Loading Factor:
J, K = 1

CLOCK. SET,

RE"S"ET = 2

Output Loading Factor

= 10

Total Power Dissipation:::: 80 mW typJpkg
Propagation Delay Time = 30 ns typ
Operating Frequency = 15 MHz typ

• P suffix = 16-pin plastic package (Case 612)
See Gene,allnfo,mation section fo, package outline dimensions.

1/2 OF CIRCUIT SHOWN
r-----~~------~~------------~--------_.------_.--------------_o5

vcc

15

a

Q

14

GND
3

SET

160-------..
K

RESET

......- - - 0 4

ELECTRICAL CHARACTERISTICS

SET
J

CLOCK

Test procedures are shown for only one

ID=
.
4
1

a

15

6

a

14

s:
IOL

10H

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
VIL
VIH VIHH
VI
V'hl V'hO Vcc

16

-0.4

0.4

mA

11
10

MC7476 Test Limits

Pin
Oto +70°C
Under
Symbol Test Min Max Unit

Characteristic
Input
Forward Current

J
K

~

4
16

Ial

3
1
1
4
16
2
3
1**

Set
Reset
Clock
Leakage Current

J
K

2

Set

ReSet
Clock
J
K

Ia2

Set
Reset
Clock

4
16
2
3
1

Output
Output Voltage

Short-Circuit Current

--

---

....

C')

_

-1.6
-1. 6
c3.2

~

40
40
80

mAdc

J
/lAdc

• !
1 1

1.0

mAdc

2.4

5.5

4.5

2.0

0.8

5.0

VCCL

VCCH

4.75

5.25

.,en:e

nO
....

:J

5·

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:
10L

--

----

10H

VIL

--

4
16
2
3
1
1

-

-

-

-

-

-

-

-

VIH

--

VIHH

VI

-

1,3*
1,2*
4,16
4,16
2*,4,16
3*,4,16

-

-

V'hl

Vcc

VCCL

VCCH

Gnd

-

-

--

5

6,9,12,13

-

--

J

J

-

5

1,3,6,9,12,13
1,2,6,9,12,13
1,6,9,12,13,16
1,4,6,9,12,13
2,3,4,6,9,12,13,16

-

-

-

--

-

-

4
16
2
3
1

--

-

-

-

3
2

2
3

2
3

3
2

--

-

-

VOL

14
15

-

0.40
0.40

Vdc
Vdc

14
15

--

--

--

-

VOH

14
15

2.4
2.4

-

Vdc
Vdc

-

14
15

--

--

ISC

14
15

-18
-18

-57
-57

mAdc
mAdc

--

--

-

-

-

-

-

IPD

5
5

-

32
32

mAdc
mAdc

-

-

-

-

-

-

-

-

(1)

V'hO

--

4
16
2
3
1

c:

-

!

-

5

-

1

5
5

-

-

6,9,12,13
6,9,12,13

-

5
5

-

6,9,12,13
6,9,12,13

-

-

-

-

5
5

3·,6,9,12,13,14
2,6,9,12,13,15

--

5
5

-

-

-

-

-

1,3,6,9,12,13
1,2,6,9,12,13
1,6,9,12,13,16
1,4,6,9,12,13
2,3,4,6,9,12,13,16

Power Requirements
(Total Device)
Power Supply Drain

-

-

*Momentarily ground pin prior to taking measurement.
**Under normal operating conditions this current is negative. This test guarantees that positive leakage will not exceed the limit shown.

2,7,13
3,8,13
.. -

---

.e:

MC7476P (continued)

OPERATING CHARACTERISTICS

Data must be applied to the J-K inputs while the clock is low.
When the clock input goes to the positive logic "'" state, the date
at the J and K inputs is transferred to the master section, where it
is storad until the clock changes to the positive logic "0" state.
Data at the J and K inputs must not be changed while the clock is
high. When the clock returns to the positive logic "0" state, informetion in the master section is transferred to the slave section.
_ Application of a logic "0" to the RESET input will force the
o output to the logic "'" state. The ~ input overrides the
clock.

Since no charge storage is involved in this flip-flop, rise and fall
times are not important to its operation. Clock fall times as long
as '.0 ps will not adverselV affect the operation of the flip-flOp.
The clock pulse need onlv be wide enough to allow the data to
settle in the master section. This time, which is the setup time for
a logiC "''', is 20 ns minimum.
Transistors OA have been added to the standard flip-flop circuit

to protect the device against negative clock transients. This addition prevents both outputs from changing to the logic "'" state
when transients in excess of -2.0 V appear at the clock.

SWITCHING TIME TEST CIRCUIT

5.0 Vdc

t- "" t+ ~ 5.0 ns
f

= 10 MHz for waveform A
1.0 M Hz for waveforms

a, E. and F

5.0 Vdc

Two pulse generators are required and must be slaved together for testing. SET and

R'E"S'ET'.

Onty one pulse generator is required for J, K, and

CL5'C'i< tests.

'" Resistor used only when th:st input is under test.

'" "'The coax delays from input to. scope and output to scope. must be matched. The
scope must be terminated in 50-ohm impedance. The 9S0-ohm resistor and the
scope termination impedance constitute a 20:1 attenuator probe. Coax shall be
CT-07.0-50 or equivalent.
CT = 15 pF ::; total parasitic capacitance, which includes probe, wiring, and load
capadtances.
'

I

MC7476P (continued)

OPERATING CHARACTERISTICS (continued)

TEST PROCEDURES

(Letters shown in test columns refer to waveforms.)
INPUT

I

TEST

SYMBOL

Toggle Frequency

Q

a

2.4 V

t

"C

J, K

Ii

S

fToa

A

A

2.4 V

LIMITS

Min

Max

Unit

t

10

-

MHz

Turn-On Delay

tpd_

B

B

2.4 V

2.4 V

C

C

-

50

ns

Turn-Off Delay

tpd+

B

B

2.4 V

2.4 V

0

0

-

50

ns

Turn-On Delay

t.d_

2.4 V

2.4 V

E

F

G

H

10

50

ns

Turn-Off Delay

tsd+

2.4 V

2.4 V

E

F

G

H

10

50

ns

t

t

t

-

-

*

$

-

-

Enable Voltage

VEN

B

2.0 V

2.4 V

2.4 V

Inhibit Voltage

VINH

B

O.B V

2.4 V

2.4 V

tOutput shall toggle with each input pulse.

*

;Output shall NOT toggle.

VOLTAGE WAVEFORMS AND DEFINITIONS

,----...,.0--------- 2.4 V
Gnd ==~~_ _ _ _ __+-.-:~==========0.4 V

---------+---,,------2.4 Vmin
C

TP out

Gnd _ _ _ _ _ _ _ _-1-1-'-__'-____ 0.4 V max
_ - - - 2 . 4 V min

o

TP out

Gnd -===============::::==-0.4 V max

2.4 V

E

TPin

RESE'f

0.4 V

Gnd

2.4 V
F

TPin

SET

0.4 V

Gnd
2.4 V min

G TP out
0.4 V max

Gnd

H

TP out

Gnd

J

1~5

2.4 V min

V
0.4 V max

MC5400/7400 series
DUAL TYPE D FLIP-FLOP

MC5479 • MC7479

Add Suffix F for TO·86 ceramic package (Case 607).
Suffix L for TO-116 ceramic package (Case 632).
Suffix P for TO-116 plastic package (Case 60S) MC7479 only.)

This dua[ typeD f1ip-f[op triggers on· the positive edge of the clock input. During the clock
transition the state of the D input is transferred
to the Q output. The device is useful in shift
registers and simple counters.

CIRCUIT SCHEMATIC
1/2 OF DEVICE SHOWN

Vee

r~~l
Pm

[8]

Set

OIL
Pkg
Pin
4

[6]

2

5 [9]

[7]

3

6 [10]

[5]
[14] 10

51
[2] 12

el

01

9 [13]

[HII

01 01

8 [12]

RI
[3] 13

tn
D

Q

tn+l

0
1

o1

I a

I

1
0

Input Loading Factor:

0=1
Set, Clock

o

Gnd

Output Loading Factor == 10

Vee = Pin' 14 [4]

Gnd

= Pin

=2

Aeset = 3

7 [II]

Total Power Dissipation .... 84 mW typ/pkg
Propagation Delay Time = 16 ns typ
Operating Frequency = 30 MHz typ

Re~t~~--------~~----------I

D-,
elock

,~~

C)-------------t-'H

s.rto--+------------------------"

LOGIC DIAGRAM
1/2 OF OEVICE SHOWN

•

-.

FLA~ OIL

ELECTRICAL CHARACTERISTICS

L Pkg
Pin

Test procedures are shown for only one
flip·flop. The other flip·flop is tested in

the same manner.

Pkg
Pin

[8J

4

[6J

2

[7J

3

s:

n
~
....

5 [9J

~CD

co

s:

6 [10J

00

RO

v

~ Vec ~ Pin 14 [4J

Gnd

~

Pin

[5J

7 [11J

n
~
....

I

[14J 10

CD

,.--s,[ 2 J 1 2 - Cl

Pin
Under
Symbol Test

Characteristic
D
Clock

D
S
R
C

D
Set
Reset
Clock

D
S
R
C

Set

IF

Reset

Leakage Current

D
Set

IRI

~2

Reset

Clock

IOH

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

4.50

5.50

[3J 13

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

4.75

5.25

R
C

Q

-

D

mAde

t ~

40
80
120
80

ILAde

1.0

mAde

~

TEST CURRENT jVOLTAGE APPLIED TO PINS LISTED BELOW:

o

--

-1. 6
-3.2

t

mAde

~

--

40
80
120
80

ILAde

-

1.0

mAde

~

~

-

-

0.4
0.4

Vde
Vde

-

2.4
2.4

-

Vde
Vde

2.4
2.4

Q

-20
-20

-57
-57

mAde
mAde

-18
-18

V
V

-

-

30
30

mAde
mAde

-

S

ISC t

Q
Q

Q
Q

Power Requirements
{Total Device}
Power Supply Drain

-1. 6
-3.2

MC5479
MC7479
MC7479
Test Limits
to +70°C
Min Max
Unit

~

~

l

0.4
0.4

Vde
Vde

c

~

Pin 7(11] is grOUndedl
for all tests in addition to the pins
I
listed below:
I

IOL

IOH

V1L

V1H

V1HH

VRI

Vthl

VthO

Vcc

VCCL

VCCH

Gnd

--

--

D
S
R
C

--

--

R,S
R
D,S
R

-

-

---

-

V

-

~

CO,CI
CO,Cl,DO
CO,Cl
CI,DO,SO

-

-

-

-

-

-

-

--

C,S
C*,D,R
Co,S
S

--

V

-

D
S
R
C

-

-

D
S
R
C

C,S
C*,D,R
C*,S
S

-

-

-

-

V

-

-

S
R

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

~

!

Cl,RO
Cl
CI, DO
Cl,DO,RO
Cl,RO
Cl
CI,DO
Cl,DO,RO

-

-

~

R
S

-

V
V

-

CO,Cl,DO
CO,Cl,DO

-

R
S

S
R

-

V
V

-

-

CO,Cl,DO
CO,Cl,DO

-

-

-

-

-

-

V
V

CO,SO,QO
Cl,RO,QO

-

-

-

-

-

V
V

CO,Cl,DO,Dl,SO,Sl
CO,DO,RO,Cl,Dl,Rl,

-

I
,
,

VOL
VOH

Short-Circuit Current

-

-

Output
Output Voltage

-

::J
.....

:;"

VCCH

IOL

MC5479
Test Limits
55 to +125°C
Min Max Unit

-

mA

nO

[ 1 J l l - 01 01 -8[121
Rl

Input
Forward Current

01 - 9 [13J

TEST CURRENT jVOLTAGE VALUES {All Temperatures}
Volts
V1L
V1H V1HH VRI Vthl VthO Vee VeCL

IpD

-

-

-

Q

-

Vde
Vd.

-

Q

-57
-57

mAde
mAde

-

-

-

-

30
30

mAde
mAde

-

-

--

_

... -

"Momentarily ground pin prfor to taking measurement, then set to state indicated.

t Only one output should be shortsd at a time.

Q

-

Q

-- -

-

-

-

-

-

-

-

-

MC5479, MC7479 (continued)

SWITCHING TIME TEST CIRCUIT

vee

OPERATING CHARACTERISTICS

+5.0 Vdc

Data may be applied to the D input any
time following 5.0 ns after the leading edge
of a clock pulse and 20 ns before the leading
edge of the following clock pulse. The state
of the D input when the clock changes from
the positive logic "0" state to the positive
logic ",.' state is transferred to the Q output
of the flip· flop. Th~ data input cannot be
changed between the setup time (20 ns) and
the hold time (5.0 ns) without adversely af·
fecting the operation of the flip·flop.
The direct Set and Reset inputs override
the clock, and may be applied any time duro
ing the operating cycle.

400

MMD61S0
or Equiv

MMD7000

t+ = 12 ns }

t- = 6.0 ns

PRF

or Equiv

10% to
90% points

Two pulse generator. are required and

= 20 MHz for waveform

1
"" 1.0 MHz for waveforms

must be slaved together to provide the
waveforms shown. Only ane pulse generator (duty cycle = 50%) is required to

2 thru 5
Zout~50

n

test toggle frequency.

The coax delays from input to scope and output to scope must be matched.
The scope must be ter.minated in 50-ohm impedance. The 950-ohm resistor

and the scope termination Impedance constttute a 20:1 attenuatar probe.
Coax shall be CT -070-50 or equivalent.
CT 15 pF ... total parasitic capacitance. which includes probe. wiring. and load
capacitances.
;<

VOLTAGE WAVEFORMS AND DEFINITIONS

1,2

1.5 V
I

Clock (Must be used on all tests)

~

30ns

3

I
I

1.S V

TEST PROCEDURES CHART

3.0 V

--0 V

(Numbers shown in test columns refer to waveforms.)

1--20 ns

I

TEST

I

C

I

Toggle Frequency
Turn-On Delay
Clock to Q
Turn-Off Delay
Clock to Q
Turn-On Delay

I

I
I

[-20n5
4

:

INPUT

SYMBOL

I

1.S V

R8S8ito

OV

Q

Turn-Off [)elay
Sat to Q

0

R

2.4V 2.4 V

fTog

I
I
I
I

'pd+

6

T~

D

3.0 V
1.5 V

p=:=t

OV

I
I

tsd-

: - 2..5 V

Gnd

, I

Gnd

IJ

r

7
tpd-

I

2.4 V min
0.4 V max

I
I

2.4 V min

L!SV

0.4 V max

tsd+

Q

t

t

LIMITS

2.

Min

Ma.

tSd_

2

3

•

2_4 V

7

6

t,o+

2

4

2.4V

•

6

7

~5

2

4

2.4 V 2.4 V

7

6

2

3

2.4V 2_4 V

6

7

Unit
MH,

3.
3.
2.

""'tpd+

·Connect to Q.
tOuqjut shall toggle with each Input pulse.

S

Q

S

•

GATED FULL ADDER

MC5480L*
MC7480L,P*

"\

MC5400/7400 series

'--------------'

The MC548017480 is a one-bit binary full adder with gated complementary

inputs, complementary Sum and Sum outputs, and an inverted Carry output.
The circuit uses DTL inputs and a high-speed, high-fan-out, TTL "totem pole"
configuration for the Sum, Sum, and Carry outputs. The design of the high-speed
carry circuitry reduces the need for external "look ahead carry" cascading in
system designs. The use of low-level, low-power gates in a monolithic design pro-

TRUTH TABLE

vides significantly lower power dissipation than equivalent adders built from stan-

dard integrated circuits.
This full adder provides a basic building block for medium and high-speed,
multiple-bit, parallel-add/serial-carry subsystems.

I

VCC=Pin7
GND == Pin 14

Cin

B

A

Cout

5

S

0
0
0,
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
0
1
0
0
0

1
0
0
1
0
1
1
0

0
1
1
0
1
0
0
1

S
r------<> 6
:><:-----<>5
S

1. A ~ A*'Ae, B ~ B*'Be
where A*:: A1 • A2
8*~ 81'82

2. When A* (or

a*>

is used as an

input, A 1 and A2 (or 81 and 82)

must

be connected to ground.

3, When A1 and A2 (or B1 and 82)
are used as inputs, A* (or
must be open, or used to perform
wired-OR logic.

a*>

Output Loading Factor:

Input Loading Factor:

A1, A2, Ae, B1, B2. Be

~

1

C out = 5

S~

A*, B* ~ 1.625

S,

Cin= 5

A*, 8*~ 3

eino-------------.,

10

Total Power Dissipation == 105 mW typ/pkg
Propagation Delay Time:
Carry Delay == 10 ns typ
Add Delay == 55 ns typ

3k

veeO---~----------1_----~

100

Alo--14-+--I
A2

+---....------0 Cout
100

Ae

s

Blo-14-+--I
B2

t--+.....--f----t---+--o s
Bk

GNDO------------+-~~~~------------------------------~

-L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 605).

ELECTRICAL CHARACTERISTICS
Output voltage (logic level) tests are
shown ,only for each output. Th~ complete Circuit can be tested by follOWing the

truth table.

-

MCS480
MC7480
Pin
MC54BO Test Limits
Under
55 to + 12S"(

Characteristic

Forward Current

Symbol
B¥

Test

Min

IF

TEST CURRENTiVOLTAGE VALUES (All Temperatures)

~

Volts

CJ'1

rnA

Max

Unit

-2.6

mAde

lOll

IOL2

lOLl

IOH 110M2

IOH3

V1l

VIH V1HH

VRI

V,hl

V,hO

VCCL VCCH

CO~

4.8

8.0

16

-0.12

-0.2

-0.4

0.4

2.4

5,5

4.5

2.0

0.8

4.5

5.5

0

4.8

8.0

16

-0.12

-0.2

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

4.75

5.25

MC74BO Test Limits
0 to +70°C
Min

Max

Unit

-2.6

mAde

r
~

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW,

C')
lOLl

IOL2

lou

IOH

1

IOH2

'OHa

Vlt

V1H V1HH

VR1

Vth1

Vtho

VCCl VCCH
14

Gnd

.......

~

7,12,13

0

7,12,13

r

Be

-1.6

-1.6

CIll

-8.0

-8.0

"

Al

-1.6

-1.6

_

A2

-1.6

-1.6

A¥

10

-2.6

-2.6

AC

11

-1.6

-1.6

Bl

12

82
Leakage Current

j

(")

IRI

2

15

Al

!LAde

15

200

200

15

15

11

12

13

13

12

7,8,9
7,8,9

j

13

BC
C in

10

~

jJ.Ade

14

1,7
7,8,9,12,13
7,9
7,8

11

81
B2
BC

IR2

11

7,10

12

12

7,13

13

13

2

1.0

mAde

1.0

7,12

mAde

14

1,7

C in

7,8,9,12,13

Al

7,9

~

7,8

AC

11

11

7,10

8l

12

12

7,13

B2

13

13

7,12

Output

c
A

Output Voltage

0'1'

VOL

o:

vd'

0.],

:~. ::' ::::::::::: ']'

Vjd'

1
B"

I

I

10

2,3,8,11,12

I - I

10

:,: I VOH I : 12t I

Vd]' 2].,

_

c---=- _ r---:-..

B" I I I
I'se I I
10

9,13

...c'-+-=:---+--cc-:

f--------28•

2. 11

V]d'
10

,,:.:,::,13 ']'

2, 9, 13

3,8,11,12

3, 10, 11

1,2,8,9,12,13

8, ,

Short-Circuit Current

Cout

4

Power Requirements
Power Supply Drain

11'D

-20

I I
14

I
-

-70

-57

mAde

-57

31**

-18

j j

-70

mAde

-57

35**

2,3,8,11,12

141

j

2,9,13

-57

mAde

....

:s"

~

AC

g

3,10,13

4,7,9,13
3,5,7,8,11,12
1,2,6,7,8,9,12,13

mAde

14

**Tested only at 25°C

•

Q.

MC5480L, MC7480L, P (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
2.4 V

Vcc

Coax'"

Coax*

2450

MMD7000
2

•

BC
Cin
A1

Cout

A2

S

AC

A*

B1

B*

o~v

4
C

VGen = 3,0 V

t+

~

15 ns

':"

0-+-+-....._,' -L2= s::,;: L3 - ,

L = _
400 _
ohms
_ _R_
_ .JI
L... except

,..-------,

·The coax delays from input to scope and output

L 1_
- Same
as L2
L... _
__
_ _ JI

to scope must be matched. The scope must be

(10% to 90% points)
PRF = 1.0 MHz
Duty Cycle = 50%

terminated in 50-ohm impedance.

The 2450-

ohm resistor and the scope termination Impedance constitute a 50: 1 attenuatar probe. Coax
shall !:'e CT -070-50 or equ ivalent.
CT = 15 pF::::I total parasitic capacitance, which
includes probe, wiring, and load capacitances.

Zout ~50 ohms

2.4 V min

0.4 V max
GND

TEST PROCEDURES ITA = 25 0 CI
PIN
UNDER
TEST

TEST

tpd+
tpd_
tpd+
tpd_

c;;;rt

4

~
~

co;t

4
4
4

tpd+
tpd_

S
S

5

tpd+
tpd_

S
S

6
6

tpd+
tpd_

A*
A*

10
10

tpd+ B*
tpd_ B*

INPUT
Be

Cin

Pin 2 Pin 3

OUTPUT

A1

A2

Ae

B1

B2

C out

Pin 8

Pin 9

Pin 11

Pin 12

Pin 13

Pin 4

y

Y
Y

Y
2.4 V
2.4 V

Gnd
Gnd

2.4 V Gnd
2.4V Gnd

6

Y

Y

Y

Y

2.4 V
2.4 V

Gnd
Gnd
Gnd
Gnd

L3
L3
L3
L3

Gnd
Gnd

L3
L3

Gnd
Gnd
Y
Y

2.4 V
2.4 V

S

S

Pin 5 Pin 6

A*

B*

MAX

Pin 10

Pin 1

LIMIT
17 ns

12 ns
25 ns
55 ns
L1
L1

L2
L2

70 ns
80 ns

L2
L2

55 ns
75 ns

CT
CT
Y
Y

I
I
I

""' T MMD61.50
I....-d:or Equlv.
_
-__
_ _ _ -=...J

S

B2

t- =

I

2.4 V
2.4 V

65 ns
25 ns
CT
CT

65 ns
25 ns

_________f

2-BIT FULL ADDER

"\

MC5400/7400 series

\..----------'

MC15482L • MC17482L *
MC25482L • MC27482L*

ADVANCE INFORMATION/NEW PRODUCT
A2

14<>----1-"

Each bit of this device performs the logical addition of two
binary numbers. The sum outputs, the carry output for the
second bit, and Exclusive OR outputs for each bit are available. A look-ahead carry is pro1/ided internally. Tho Exclusive
OR outputs of the MC25482/MC27482 can be used for lookahead carry when adding more than two bits.
This device is constructed from low and high-Iavel NAND
.and AND-DR-INVERT gates as shown in the logic diagram

13~"""T""-"_/

B2

to maximize output drive capability and minimize power
dissipation.
12
A1
2n...l _ _...I--'"

__

3~~~~~-t~=-~
B1

______________,

TRUTH TABLE
INPUT

OUTPUT

Cin -1

Cin -0
A'
0

Input Loading Factor: A. B = 2; Cj = 3

Output Loading Factor = 10
Total Power Dissipation = 165 mW tvp/pkg

4k

0

0

0

0

0

0

0

,
,

, ,
, ,

0

0

0
0

0

0

0

1

0

0

(}

,

0

0

0

0

0

0

0

0

,

0

, ,
, ,

,
, , ,
, , ,
,
,
, ,
, ,
,
,
0

0

0

0

0

0

0

0

0

1

0

0

0

1

'* Diodes only on

0

0

,

0

0

r-------------------,-~ Vee

,

0

0

LOW-LEVEL "NAND" GATE

0

0

,
,
, ,
, , ,
,
,
, ,
,
,
, ,
,
,
0

Vee"PIN4
GND"PIN11

0

82

0

t Available only on MC25482/27482.

52

A2

,
,
, ,

Cin
5~------------------~----------L-~

5'
0

8'
0

C

5'

0

0
0

52

C

,
,

0

0

inputs connected

INPUT
B2

C;

input connected

• L. suffix = TO-116 ceramic duslln-line package (Case 632).

0

0

0

0

0

0

0
0

,

, , ,
, , ,
, ,
,
,
, , ,
, , ,
,
,
,
, , ,
, , ,
, , ,

0
0

,
0

0

0

0

0

1

0

1

0

0

0

0

0

,

0

0

,
,
,
,

1

0

0

1

0

0

0

0

0

0

0

0

0

5, 1 52 .1 co .10 5' .1 52 1 Co .1 0
1'8.5.1 .1 9 .5
.1 271 .1'4
5.61

'3.1 9.5 .1 -

9.0.1'8.51'41-

HIGH-LEVEL INVERTER

to external point .

0

0

TYPICAL PROPAGATION DELAY TIMES
TA = 250C
'pd_ (nsl
'pd+ (nsl
OUTPUT
OUTPUT

LOW-LEVEL "AND-DR-INVERT" GATE

:j: Diode only on

0

0

,
,

0

t Available only on MC25482/27482.

to external points.

HIGH-LEVEL "AND-DR-INVERT" GATE

(,!),' ('!)2'

MC15482, MC17482, MC25482, MC27482 (continued)

DC ELECTRICAL CHARACTERISTICS

•

TA = 0 to +700 C for MC17482 and MC27482
TA = -55 to +1250 C for MCI5482 and MC25482

Characteristic

Symbol

Value

IF

-3.2 mAdc max
-4.8 mAdc max

IR

BO"Adc max
120 "Adc max
1.0mAdc max

Conditions

Input
Forward Current - A, B

C;
Leakage Current

~

A, B

Ci
A,B,Ci
Threshold Voltage

Vth "I"

2.0 Vdc

Vth "0"

0.8 Vdc

VOL

0.4 Vdc max

Yin = 0.4 Vdc, VCC = 5.5 Vdc  V SELECT

X SELECT 0--_ _ _ _--'-1___

L ____________ J

1,2,3, or 4

6,7,8,or9
VCC

VCC

850

750

750

850

3,5 k
3.5 k
SENSE AMPLIFIEA
VCC

4-1<

4k
W .. O"

W"I"

11

15

10

16

GND

12

WRITE INVERTER

S

ELECTRICAL CHARACTERISTICS

n

Test procedures are shown for only one
bit. Other bits are tested in the same
manner. In addition, test procedures are

U'1

level.

The other Write inputs are tested
IS"O"

in the same manner.

I

'vv

Volts

I

Symbol

IxV

I

V;n 1

I

V;n 2

I

V;n 3

I

VF

I

VR

I

V'h

I

V'h VV

I

Vo"'

I VCCL I

VCCH

MC5484

5.5

MC7484

5.25

S

n

-..J

TEST CURRENTIVOl TAGE APPLIED TO PINS LISTED BELOW:

__

~

Characteristic

.ir-

TEST CURRENT/VOlTAGE VALUES (All Temperatures)
rnA

shown for only one Write input of each

~:~'~~~~~~~-+~~~~~~~-r~~~~~~~~ ~~~~~~~~r-~--r-~--~~--~~--~~~~~l

Gnd

'F

Write Inputs

Leakage Current
Address Lines

10
15

10
15
BV m

Write Inputs
Output

-11
-11

mAde
mAde

-11
-11

mAde
mAde

-1.60
-1.60

mAde
mAde

-1.60
-1.60

mAde
mAde

0.4
0.4

mAde
mAde

0.4
0.4

mAde
mAde

0.1
0.1

mAde
mAde

0.1
0.1

mAde
mAde

2,3,4,10,11,12,15,16
7,B,9, 10,11, 12, 15, 16

6.7.8,9
1,2,3,4

1,2,3,4,6,7 ,8,9, 12, 15, 16
1,2,3,4,6,7.8,9,10,11,12

10
15

.."

nO
::l

!:!.

'R

Write Inputs
Breakdown Voltage
Address Lmes

~

r-

Input
Forward Current
Address Lines

it

10
15

5.5
5.5

Vdc
Vdc

5.5
5.5

Vdc
Vdc

5.5
5.5

Vdc
Vdc

5.5
5.5

Vdc
Vdc

2,3,4,6,7,8,9,10,11,12; 15, 16
1,2,3,4,7 ,8,9, 10, 11,12,15, 16
10
15

1,2,3,4,6,7,8,9,12,15,16
1,2,3,4,6,7 ,8,9, 1 0, 11,12

::l
t:

~

2,3,4,6,7,8,9,10,11,12,15,16
1,2,3,4,7 ,8,9, 10, 11, 12, 15, 16
10
15

1,2,3,4,6,7,8,9,12,15,16
1,2,3,4,6,7,8,9,10,11,12

(Note 1)

Output Voltage
Wrtte "1"
Logic "0" Level

14

0.45

Vdc

0.45

Vdc

14

V out "0'

14

0.45

Vdc

0.45

Vdc

14

Write "0" !nhlbit
Logic "0" Level

15,16

1,6

Logic "0" Level

V out "0"

13

0.45

Vdc

0.45

Vdc

13

Vout "0"

13

0.45

Vdc

0.45

Vdc

13

V out "0"

14

0.45

Vdc

0.45

Vdc

14

2,3,4,7,8,9,12

'OLK

14

0.25

J

mAde

0.25 ) mAde

1,6

IOLK

13

0.25

j mAde

0.25 ) mAde

1,6

I

Leakage Current

'OLK

13

0.25

) mAde

0.25

J

mAde

1,6

78#

I mAde

I

2,3,4,7,8,9,12

15,16

2,3,4,7,8,9,10,11,12,15,16
15,16

2,3,4,7,8,9,12
14

2,3.4,7.8,9,10,11,12,15,16

13

2,3,4,7,8,9,10,11,12,15,16

10,11

2,3,4,7,8,9,12

1,6,7,8,9
1,6,7,8,9

0.25 ) mAde
0.25 ) mAde

2,3,4,7,8,9,10,11,12,15,16

1,6

10,11

14

1,6
1,6

15,16
IOLK

2,3,4,7,8,9,10,11,12,15,16

1,6

15,16

Leakage Current
Write "0"

2,3,4.7,8,9,12

1.6

2,3,4,7,8,9,12

10,1'

Write "1"

2,3,4,7,8,9,10,11.12.15,16
10,11

15,16

10,11

Write "0"
Leakage Current

10,11

1,6

10,11

1,6

Leakage Current
Write "1"
Leakage Current

2,3,4,7,8,9,12
2,3,4,7,8,9,10.11,12,15,16

1.6

Wnte "1"
Logic "0" Level

I

15,16

Write "1" Inhibit

15,16

1,6

Write "0"
LogiC "0" Level

1,6

10,11
V out "0"

2.3,4,10,11,12
13

2,3,4,10,11,12,15,16

14

2,3,4,10,11,12.15,16

1,6.7,8,9

1,6,7,8,9

2,3,4,12,15,16

P:O-wer Requirements
(Total Device)
Power Supply Drain
Note 1.

'PO

91 II

) mAde

1,2,3,4,6,7,8,9,10,
11,12,13,14,15,16

Output logiC "0" voltage and leakage current measurements are made as part of a functional test of a memory
~
Indicates preconditionmg procedures for the subsequent test All power supply and input voltages must be
maIntaIned between tests
4

# Tested only at 25°C.

- - - - - - - -____I ____~

MC5484L, MC7484L,P (continued)

SWITCHING TIME TEST CIRCUIT

TPout

16

Two pulse generators are
required and must be
slaved to provide the
waveforms shown.

X3
X2
X1
6
Y1
Y2
Y3

50

120

13

S"1"

14

330

11
TP out

High-impedance probes (>1.0 Megohm) must be
used when t8k Ing measurements.

See Switching Time Test Procedures
table for value of CT'

VOLTAGE WAVEFORMS AND DEFINITIONS

MC5484L, MC7484L,P (continued)

SWITCHING TIME TEST PROCEDURES

(Letters shown in test columns refer to waveforms)

Symbol Under
Test

Turn·Qff Delay Time
(Address Lines to
Sense "1" Output)

tpd+
tpd+

tpd+
tpd+

13
13

14
14

"a.. Output)

Turn-Off Delay Time
(4 Bits) (Address Lines
to Sense "0" Output)
Turn-Off Delay Time
(4 Bits) (Address Lines
to Sense" 1" Output)

Write Recovery Time

Write Pulse Width

Xl

X2

X3

1

6

7

8

9

X4

Yl

Y2

Y3

Y4

13
14
10
15
W"O" W"l" 5"0" 5"1"

A
A

Gnd
Gnd

Gnd
Gnd

Gnd
Gnd

A
A

Gnd
Gnd

Gnd
Gnd

Gnd
Gnd

3.0 V 3.0 V 3.0V 3.0 V 3.0V 3.0 V 3.0 V 3.0 V
3.0 V Gnd Gnd Gnd 3.0V Gnd Gnd Gnd
A
Gnd Gnd GOd
Gnd Gnd Gnd
A
A
Gnd Gnd Gnd
A
Gnd Gnd G'nd

Gnd

Gnd

B

Gnd

Gnd

B

3.0 V Gnd
Gnd 3.0 V
Gnd Gnd
Gnd Gnd
3.0 V
Gnd

13

Gnd

tpd_

14

3.0 V 3.0 V 3.0V 3.0 V 3.0V 3.0 V 3.0 V 3.0 V 3.0 V
3.0 V Gnd Gnd Gnd 3.0V Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd
A
Gnd Gnd Gnd
A

tpd_

14

tpd_
tpd_

13

Turn-On Delay Time

(Address Lines to
Sense" 1" Output)

3

3.0 V 3.0 V 3.0 V 3.0V 3.0 V 3.0V 3.0 V 3.0 V Gnd
Gnd 3.0 V Gnd Gnd Gnd 3.0 V
3.0 V Gnd Gnd
A
Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd
A
Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd

Turn-On Delay Time
(Address Lines to
Sense

4

.

CT
pF

Limits
MC5484

MC7484

ns max

ns max

15
200

25
35

35

15
200

25
35

25

15
200

45

45

55

55

B

15

45

45

B

200

55

55

15

30

30

30

3.0 V 3.0 V 3,OV 3.0 V 3.0V 3.0 V 3.0 V 3.0 V Gnd 3.0 V
3.0 V Gnd Gnd Gnd 3.0V GOd Gnd Gnd 3.0 V Gnd

.Turn-Off Delay Time
(Addr~ss Lines to
Sen$e "0" Output)

Output

Input Pin

Pin

Test

Gnd
3.0 V

13

3.0 V 3.0 V 3.0 V 3.0V 3.0 V 3.0 V 3.0 V 3.0 V Gnd
3.0 V Gnd Gnd Gnd 3.0 V 3.0V 3.0 V 3.0 V 3.0 V
A
A
Gnd Gnd Gnd
A
A
A
Gnd

Gnd

tpd+

14

3.0 V 3.0 V 3.0V 3.0 V 3.0V 3.0 V 3.Q V 3.0 V 3.0 V
3.0 V Gnd Gnd
Gnd 3.0V 3.0V 3.0 V 3.0 V Gnd
A
Gnd Gnd Gnd
A
A
A
A
Gnd

twr

14

3.0 V

Gnd

Gnd

Gnd 3.0 V

Gnd

Gnd

Gnd

13

3.0 V

Gnd

Gnd

Gnd 3.0 V

Gnd

Gnd

Gnd

tpd+

Gnd

Gnd

A

Gnd

Gnd

Gnd

3.0 V
Gnd

Gnd

A

Gnd

Gnd
Gnd

Tested during 'twr tests.

twp

B
B

B
B

25

35

-

Gnd
Gnd
3.0 V

B

-

Gnd

B

15

30

E

C

0

15

60

60

E

C

15

60

60

ns min

ns min

25

25

• Capacitance value for load of the Switching Time Test Circuit
• ·Preconditioning procedures for subsequent tll!st.

OPERATING CHARACTERISTICS

Sixteen flip-flops are arranged in a 4-by-4 matrix with each
flip-flop representing one bit of 16 w~rds. Each flip-flop, consisting of two cross-coupled triple-emitter transistors, is used to
store one bit. Memory status of a particular bit is det~rmifled by
sensing which of the two flip-flop transistors is conducting. One
emitter of each of these transistors serves as the sensing outpu"t.
All 16 of the logical "1" sensing output~ are connec~d t~ ~e
sense 109;c "1" amplifier inpot, and all 16 ofthe logical "0" sersing outputs are connected to the sense Jogie "0" amplifier input..
The remaining emitters on each i'ransistor provides the .matrix
'connections required for the X- and V-address lines. Address line
inputs are 'normally held at logiC ~'O" and currents from all conducting flip-flop transistors flow out of these address lines.
To address a flip-flop both the X- and V-address lines associated
with that flip-flop are taken to a logic 'il" voltage. Due to the
matrix nature of the circuit, at least one address line of all flip-flops
except the one being addressed will continue to remain at a logic 00"
level and no change will occur on those flip-flops. But, in the adA

dressed flip-flop, the current in the cOl1ducting transistor diverts
from the Qddress lines to the appropriate sense line and then to one
of the sense amplifiers. Thus, either the sense amplifier associated
with a logic "1" or the sense amplifier associated with a logic "0"
is activated._ When this occurs, the output of the activated sense
amplifier drops from a logic "1" to a !ogic "0" level. The memory
is non-destructive as the states of the flip-flops 'are not disturbed
during sensing.
To store new information in a flip-flop, it is necessary to address
it and apply logic "1" voltage to the appropriate 'write amplifier
input. Th,e output of the write amplifier responds by dropping to a
logic "0" level. Since all logic "0" sense fines are connected to the
output-of the logic "0" write ampl-ifier and all logic "1" sense lines
are connected to the output of the logic "1" write amplifier, a
logic "0" voltage on the output of a write amplifier wi II apply the
same voltage to emitters of all flip:.ftop transistors connected to that
amplifier." In all flip-flops "xcept the one being addressed, this lOW
voltage has no effect since at least one other emitter on each of the
flip-flop transistors is held . low by the address lines. But two
possibilities exist with the flip-flop that is addressed. The flip-flop
may already be in the desired state, in which case no change occurs.
But if the flip-flop must be changed from one state to the other, the
low voltage applied to the emitter of the ~ranslstor which is not
conducting turns that transistor on, causing the other transistor
to turn off.

MC5484L, MC7484L,P (continued)

are enabled before a Y driver. However, if the memory accessing
sequence specifies that only a single bit may be selected at a time

TYPICAL APPLICATIONS

•

and, consequently, that only one of the X (or Y) selection lines

may be high at a time, then the driver requirements can be relaxed
somewhat. This is possible because of current sharing in the multiemitters of the storage flip-flop transistors. If the voltages at the
emitters of the "on" transistor differ by no more than approximately
100 mV, then each emitter will carry an appreciable portion of the
transistor current. The saturation characteristics of the drivers determine the emitter potentials and, therefore, the division of cell
current among the various drivers. Since the Va L of the driver
will increase if the collector current increases, the selection currents
will be almost evenly distributed among the drivers if the driver
saturation characteristics are reasonably uniform. If operation is
restricted to a single X selection line and a single Y selection line
and current sharing is assumed, then each select line must be capable
of carrying the full current from a single cell plus approximately
one half of the current from three cells. Each line must, therefore, carry:

A fast scratch pad memory offers the system designer several design alternatives. Temporary memory with a greater storage capacity
than simple registers can be distributed throughout a system. The
basic technique for expanding bit capacity is shown in Figure 3;
Figure 4 illustrates a method for expanding word capacity.
Optimum design of the selection line drivers depends on the
specific system application. The maximum load presented to the
drivers by the selection lines is a function of the sequence used to
address the memory. The desired logic swing and noi~e immunity

should also be considered when designing the drivers. Each of the
16 flip-flops draws a maximum dc supply current of 2.75 mA
(for Vee = 5.0 Vdc). The total current flowing in all 16 flip·flops,

and consequently the summed current in the eight selection lines,
is 44 rnA. (Each selection line is tested for a maximum of 11 mAl.
Consider the sequence involved in selecting the four bits X 1 y 1,

11/4 + (3) (1/2) (11/4)

X1 Y2, X1Y3, and X1Y 4 simultaneously. If the four Y select lines

= 6.88 mAo

Since the dc output levels of the driver transistors determine
the noise immunity of the selection line, the system noise environment and the desired noise immunity should enter into the
driver selection.

are enabled before the X1 line-then each of the four X lines must
carry the full current from four cells, i.e., 11 rnA. The Y drivers
must also have the capability of sinking 11 rnA if the four X drivers

FIGURE 3 - 16 WORD, N BIT MEMORY

MEMORY ADDRESS REGISTER

J

2

3

1
Decoder 2 Bit Binary to 1 of 4
}\ MC4007

1

Oecoder 2 Bit Binary to 1 of 4

J

% MC40Q7

Timing

Selection Line Drivers

J

0

X3

X2

Selection Line Drivers

I
Xl

Timing

I
Y4

Y3

Y2

I
Yl

X4

/"

\

Bit 1

Bit I Write

Bit I Sense

{~:=:J
{~

Bit 2

!o ! ! !

,0 1
1 '-v-'
__
Write

Sense

Bit 3

~~ ! ~

---Write

Sense

Bit N

---~ ~ !~

Write Sense

C548417484

MC5484L, MC7484L,P (continued)

FIGURE 4 - 64 WORD, 4 BIT MEMORY

MEMORY ADDRESS REGISTER

Decoder 3 8'it Binary to 1 of 8
MC4006

Decoder 3 Bit Binary to 1 of 8
MC4006

Timing

Timing

0---,

Selection Line Drivers

Yl

Y2 Y3

Y4 Y5

Y6 Y7

Selection Line Drivers

X2 X3 X4

Xl

YB

X5 X6 X7

-

.---

-

-

IXC5484174B4

~

'i

."'-

"", ~

o

'" '"

'"

'\ '\J ~

ll'

1 0

1

""

1 0

1

"-

"'."" r\

}
o

XB

o

ll'

1 0

1

~
"\ "" .r\:

}
o

1 0

1

'-..-'-v-

--"'--'-v-'

--....--'-v-'

'-v-''-v-'

Sense Write
Bit 1

Sense Write

Sense Write

Sense Write

Bit 2

Bit 3

Bit 4

~__________________M
__C_5_40_0_1_7_40_0__
se_ri_e_s~

DECADE COUNTER

MC5490F,L*
MC7490F,L,P*
This 4-bit counter is comprised of a divide-by-two section and a
divide-by-five section. These sections can be used independently, or can
be connected to perform the counting function or the simple divide-bYten function with an output duty cycle of 50%. Two sets of direct
RESET inputs are provided to allow setting all outputs to a logic "0"
or to the BCD cou nt of 9.

RESET/COUNT TRUTH TABLE
RO

A9

OUTPUT

I
,, ,,
, , ~I ~ I~ I,
COUNT

Pin 2 Pin 3 Pin 6 Pin 7 Q3~ Q2J Ql

X
X
0
0
X

I

X

X
0
X
X
0

0
X

X
0

X
0
X
0

0
X
0
X

QO

0
0

COUNT
COUNT
COUNT

Don teare.

02
8

01

00 Cl
12
1

CO
14

9

03
11

COUNT SEOUENCE TRUTH TABLE
OUTPUT
COUNT
0
1
2

3

Q3

Q2

Ql

QO

0

0

0

0

0
0
0
0
0
0
0

0
0
0

0

1

1
1

0

0
0

0

,

0

1

,,, ,, ,,
,,
,

4
5

6
7

8

0
0

R

0

C

C

0

C

51
52

0

0
0

9

0

C

5

Q

Rol~

0

00 connected to C1.

R91~

Input Lo'ading Factor:
RO, R9 = 1
CO = 2

(;1 =4
Output Loading Factor = 10

Vee

Total Power Dissipation = 160 mW typ/pkg
Propagation Delay Time = 20 ns typ!bit

GND

TYPICAL FLlp·FLOP

TYPICAL RESET GATE

vcco---~---------,

1k

== Pin 5
= Pin 10

vcco---------~--------~~------------_.------~~--_,

4k

5.6 k

5.6 k

4k

1.4 k

100

3k

RO

RO

r--------+---r--~~~O

+----40--~Gnd

3.2 k

Gndo-----------~~

*F suffix = TO-SS ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Ca~ 632).
P suffix'" TO-116 plastic dual in-line package (Case 605).

ELECTRICAL

CHARACTERISTI~

mA

input of each reset gate. The other input
of each reset gate is tested in "the :Same
manner.

MC5490 Test Limils
-55 to + 125'C

Pin
Under
Symbol Test Min

Characlerislic
Input
Forward Current

RO
R9
CO
Cl

Leakage Current

IF

RO
R9
CO
Cl

IRI

RO
R9
CO
Cl

IR2

2
6
14
1
2
6
14
1
2
6
14
1

s

TESTCURRENT I VOLTAGE VALUES (All Temperatures)

Test procedures are shown for only one

-

-

-

-

MC5490
MC7490
MC7490 Test Limits
o to +70'C

Max

Unit

Min

-1. 6

mAde

-

-1.6
-3.2
-6.4

~

40
·40
80
160

/.lAde

1.0

mAde

~

-

~

~

12

-

0.4

-20

-

-

-

-

--

V"

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

0.7

5.0

4.5

5.5

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

0.8

5.0

4.75

5.25

IOH

V'L

-1. 6
-1. 6
-3.2
-6.4

mAde

pAde

1.0

mAde

-

2
6
14
1

40
40
80
160

-

~

V'H

-

-

-

V'HH VR, V'h 1
-

3
7

-

-

V'hO

V'hL

-

--

-

2
6
14
1

-

-

-

2.3,14

6.7

-

-

-

2,3,6,7

14

-

-

-

-

-

5

-

-

10

1

5

-

-

10

1

-

-

5

1

9,10

2,3,6,7

1

-

5

-

-

10

2,3,6,7

1

-

5

-

-

10

1

-

-

-

5

1

8,10

1

-

5

-

-

10

-

2.3,6,7

1

-

5

-

-

10

6,7

2,3

-

-

5

10,11

6,7

2,3

1

-

5

-

-

-

-

-

-

-

5

-

6,7,10

-

-

-

-

2.3,6.7.14

-

-

6,7

-

-

-

-

9

-

-

-

-

2,3,6,7

Vdc

-

2,3

-

-

8

-

-

-

-

-

-

-

-

-

Vdc

2.4

Vdc

0.4

Vdc

-

0.4

Vdc

-20

-57

mAde

-18

-57

mAde

2.4

-

Vdc

2.4

-

3,10

-

-

-

-

-

10,12

-

2.4

-

3,10
7,10
10
10

14

12

mAde

~
5

-

-

5

-

-57

5

-

9

-18

-

-

-

-

-

-

-

Q

cto

10
10
2,10
2,10

-

-

mAde

-

~

-

-

10

-

-57

-

5

-

-

Vdc

-

-

-

-

-

0.4

-

-

-

s

Gnd

5

-

-

r

Pulse
VCC VCCL VCCH
1

~

-

Vdc

.

-

12

~

-

-

-

~

-

2
6
14
1

-

-

-

~

o

"T1

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:
IOL

~

V,hl

V,hO

Vth L Vcc VCCL VCCH

IOH

Unit

Max

~

Volts
V'H V'HH VR,

IOL

.
r.,
"T1

!

!

7 1 10
10

0o

....
::J

:i"
c:

10

(\)

Output
Output Voltage

QO

CD

VOL

Short-Circuit
Current

Igc

Output Voltage

V OH

j

VOL

9

Ql

CD

IsC

Q2

CD

V OH

1

VOL

8

Igc

Q3

CD

V OH

1

VOL

11

ISC
V OH

1

IpD

5

-

0.4

Vdc

-

0.4

Vdc

-20

-57

mAde

-18

-57

mAde

2.4

-

Vdc

2.4

-

Vdc

-

8

-

-

-

0.4

Vdc

-

0.4

Vdc

11

-20

-57

mAde

-18

-57

mAde

-

-

-

2.4

-

Vdc

2.4

-

Vdc

11

-

-

-

-

-

46

mAde

-

53

mAde

-

-

-

-

-

Power Requirements
(Total Device)
Power Supply Drain

-

-

a.

10

-

Pulse 1: Apply positive pulse prior to taking measurement to set the device in the desired state. r-l-Vth H (2.2 V)
Maintain Vth L voltage for measurement.
.J L Vth L

ill All input,

power supply and ground voltages must be maintained between each test unless otherwise noted.

--------------~-----

MC5490F, L, MC7490F, L, P (continued)

SWITCHING TIME TEST CIRCUIT

Vee
+5.0 Vdc

950

400

±.1.0%

•

Cl
14

PULSE
GENERATOR

MMD6150

01 9

CO

o-~r-_~~",,*",or

Equiv

02 8
MMD7000
or Equiv

Duty Cycle = "50%

fTog = 10 MHz min
CT = 16 pF = total parasitic capacitance. which Includes probe, wiring. and load

capacitances.

*The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm impedance. The 950~ohm resistor and
and the scope termination Impedance constitute a 20: 1 attenuatar probe.
Coax shall be CT -070-60 or equ ivai ant•
•• A load Is connected to each output during the test.

VOLTAGE WAVEFORMS AND DEFINITIONS
t+
15 ns

t-

16 ns

Clock

Pul.e Y (fTog test)
PRF = 10 MHz
Pulse Z (tpd test)
PRF = 1.0 MHz
00

GND,====-----===----f-====------.:==::..---I--=-==----== Vmax
.0.4

r----..,I.---------2.4
01

GND--=======~_______+~======~------~~=========O.4vm8x
___________

02

03

V min

__ 2.4

V min

GND :=============-__________________~~======:O.4

V max

"""\+-....c:'-'-''-'-'-=~

/

, - 2 . 4 V min

GND ==========================~_______~::::0.4 max
V

MC540017400 series

8-BIT SHIFT REGISTER

MC5491AL*
MC7491AL,P ~

The 8·bit serial·in, serial·out shift register is composed
of eight R·S master·slave flip·flops, an input AND gate,
and a dock driver.
Single rail data inputs are ANDed together and applied
to the input of the first flip·flop. The clock inverter·driver

Vee
Gnd

is cor:nmon to all eight flip·flops and causes information
to be shifted to the output on the positive edge of the input
clock pulse. Both Q and Q are available from the last bit.
The 8·bit sh ift register may be used as an 8·bit delay line
in data handling systems and control systems.

5
= Pin 10

= Pin

TRUTH TABLE
Synchronous Inputs
t n +8

tn

A
0
0

B
0

Q
0
0
0

1
11 01 1

Q

1
1
1

Input Loading Factor = 1
Output Loading Factor = 10
Total Power Dissipation = 175 mW 'typ/pkg
Propagation Delay Time = 25 ns typ
Operating Frequency = 18 MHz typ

0

12

11

10~~~~~~~=4~~;=~~=+~~~~=+~~~==~=+~+=+=~=-~

9

·L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix"" TO-116 plastic dual In-line package (Case 606).

•

•

s:

(")

01

~

ELECTRICAL CHARACTERISTICS

TEST CURRENT / VOLTAGE VALUES (All Temperatures)
rnA

MC549 1A
MC749 1A

Characteristic

Pin MC549 1A Test Limits MC7491A Test Limits
-55 to +125°C
oto +70°C
Under
Symbol Test Min Max Unit Min Max
Unit

Input
Forward Current

-

-1. 6

mAde

t

t

40

ilAde

t

t

1.0

mAde

11
12

-

t

t

-

VOL

13
13
14

-

0.4

Vde

t

VOH

13
14

2.4
2.4

-

ISC

13
14

IpD

10

IF

9

11
12
Leakage Current

lRI

IR2

9

11
12
9

Output
Output Voltage

Short-Circuit Current

Power Requirements
Power Supply Drain

CO
....
»

-

t

,

40

ilAde

-1. 6

mAde

-

t

t

-

1.0

mAde

t

t

0.4

Vde

t

-

-

Vde
Vdc

2.4
2.4

-

Vde
Vdc

-20
-20

-57
-57

mAde
mAde

-18
-18

-57
-57

mAde
mAde

-

50'

mAde

-

58'

mAde

t

•
I

s:

IOL

IOH

V1L

V1H

V1HH VR1 VR2 V.h 1 V.hO VCCL VCCH

(")

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

4.5

5.5

16

-0.4

0.4

2.4

5.5

4.5

5.0

2.0

0.8

4.75

5.25

....

-...I
~

CO

»

TEST CURRENT /VOlTAGE APPLIED TO PINS LISTED BELOW:
IOL

IOH

V1L

-

-

-

9

-

11
12

-

-

-

-

-

13
13
14

-

-

-

-

-

13
14

-

-

9

-

-

11
12

-

-

-

-

-

-

-

-

-

-

-

-

9
11

12

-

-

12
11

-

-

-

-

-

-

-

-

-

-

-

-

-

-

10

-

t

-

t

5

-

t

-

10
10,12
10,11

-

5

-

t

-

10
10,12
10,11

5

-

9

10

-

11,12
11

-

,

-

11,12
11

12

5
5

-

-

-

5
5

-

-

-

-

5

9

-

-

-

-

-

-

-

-

-

-

Vth 1
Vth 0
Measure

-

5

Gnd

12
11,12

-

**Input pulse:

-

-

."

**

-

-

-

-

-

-

-

-

-

-

-

-

f'"

V1H V1HH VR1 VR2 V,hl V,hO VCCL VCCH

*Tested only at 25°C.

Setup

f'"

Volts

t
9

9

•

10
10

C'l

o

=.

:l
:l
C
C1l

a.
,

I

9,10,11,12,13,14 i
9,10,11,12,13,14 '
10,11,12

MC5491AL, MC7491AL, P (continued)

SWITCHING TIME TEST CIRCUIT
5.0 Vdc

400

TP out
MMD7000
or Equiv

s
MMD6150
or Equiv

Co--t------i )<>-t-..qC
A

MMD6150
or Equiv

O--r--~-----1--'

.....L.J

t+ = t-= 10 ns

B~+-+--

400

5.0 Vdc

Two pulse generators are required and must be slaved together
to provide the waveforms shown. Pulse generator for Pulses A
and B must be operated in the double pulse mode.

TEST PROCEDURES
(Letters shown in test columns refer to waveforms)

'" Resistor used only wher;t that input is under test.

TEST

B

A

C

W

W

T

.

tpd+

V

2.4V

U

y

tpd+

2.4V

V

U

tpd_

2.4V

X

U

tpd-

X

2.4V

U

must be matched. The scope must be terminated in 50-ohm
impedance. The 9SO-ohm resistor and the scope terminetioM impedance'constitute a 20:1 attenuatar probe. Coax
shall be CT -070-50 or ~uivalent.

CT

= 15

LIMITS

INPUT

'" "'The coax delays from input to scope and output to scope
<

pF = total parasitic capacitance, which includes probe,

wiring, and load capaci,tanc8L

fTog

Q

Q
y

Z
Z

Min

Max

Unit

10

-

MHz

40'

ns

40

ns

40

ns

40

ns

·Output shall toggle with each input pulse.

VOLTAGE WAVEFORMS AND DEFINITIONS

PulseT:

f= 10MHz
Duty CyCle = 50%

Pulse U:

f .. 1.0 MHz
Duty Cycle = 50%

3.0V

OV

tSetup (1)

~ 25

ns min

tHold (1) _= 0 ns min

t-

= 0.5

Pulse V :
Pulsew:

f

PulseX:

f = 0.5 MHz

3.0 V

90%
1.5V
10%

MHz

f = 5.0 MHz

OV

3.0 V

OV

tpd+<
2.4 V min
Pulsey:

TPout

1.5V
0.4 V

GND

max

tpd_
2,.4 V min

0.4 V max

GND

MC5400/7400 series

DIVIDE-BY-TWELVE
COUNTER

MC5492F,L*
MC7492F,L,P*
This 4-bit counter is comprised of a divide-by-two section and a divide-by-six section. These sections can be used
independently. or can be connected to perform the divideby-twelve function. When used independently. the divideby-six section provides the divide-by-three function at the
C output and the divide-by-six function at the D output.
The outputs may be set to the logic "0" state any time during the counting sequence by setting both RO inputs to the
logic "'" state.

COUNT SEQUENCE TRUTH TABLE
OUTPUT
COUNT
0

•

1
2
3
4
5
6
7

03

02

01

00

0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1

0

1

0
0
0
0
1

8

1

9

1

0
0
0
0

10
11

1

1

1

1

1

1
1
1
0

1
0
1
0
1

1
0
0

Vee=PIN5
Gnd = PIN 10

A connected to C1

co

01
12

14

02

01

Cl

03

8

9

11

1

Input Loading Factor:

RO" 1
el = 2

o

e2= 4
Output Loading Factor = 10

o f---+----I

e

Total Power Dissipation = 160 mW typ/pkg
Propagation Delay Time = 60 ns typ

o

o

e
R

R

R

RO 6
RO

7~__..

_ __'

TYPICAL FLIP-FLOP

RESET GATE

Vee

Vee

1 k

5.6 k

4k

5.6 k

4k

1.4k

100

3k

RO
RO

r-------~--~--~--OO

Clock
3.2 k

Gnd

*F suffix = TO-S6 ceramic flat package (Case 607).
L suffix = TO-116 ceramic dual in-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Csse 605)'

....- -....-oGnd

S

ELECTRICAL CHARACTERISTICS
C2

Bf---<> 11

TEST CURRENT / VOLTAGE VALUES (All Temperatures)

140-----:- C1
C 1---0 9
D

RO RO
7

Pin MC5492 Test Limits
Under -55 to + 125°C
Symbol Test Min Max Unit

Characteristic

.

Input
Forward Current

RO

IF

6
7
14
1

IRI

6
7
14
1

Cl
C2

Leakage Current

RO
Cl
C2

-

-

-

-

----

1.0

mAde

~ .•..

~

---

Vtlc

ACD

VOL

-

0.4

ISC

j

-20

-57

2.4

-

Short-Circuit

Current
Output Voltage

V OH

BCD

VOL

ISC
V OH

cCD

VOL

ISC
V OH

DCD

VOL

1;C

1

IpD

5

-1. 6
-1. 6
-3.2
-6.4

mAde

40
40
80
160

J.lAde

1.0

mAde

~
~

10H

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

0.7

5.0

16

-0.4

0.4

2.4

5.5

4.5

2.0

0.8

0.8

5.014.75

V,H V,HH VOl

V'h I

V'hO

I

4.5

5.5

---

.--

10H

V,L

---

6
7
14
1

-

-

-

V,H

--

6
7
14
1

--

V,HH VOl

-

-

-

-

6
7
14
I

-

-

-

-

-

12

-

~

~.

--

-

0.4

Vdc

12

mAde

-18

-57

mAde

-

V~c

2.4

-

Vde

-

0.4

Vde

-

O.•

Vde

-57

mAde

-18

-57

mAde

2.4

-

Vde

2.4

-

Vde

-

-

0.4

Vdc

-

0.4

Vde

9

-20

-57

mAde

'18

-57

mAde

2.4

-

Vde

2.4

-

Vde

-

-'.

7
6

-

V,h I

--

-

-- --- --

VthO

-

-

-

VthL

-

......

Vce VCCL VCCH
5

-

-

-

-

--

5

-

5

-

-

-

-- ---

S
n

.5.25

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:
10L

-

-

--

-

-

-

-

-

-

5

~
~

Pulse Pulse
I
2

---

--

Gnd

-

10

~
7,10
6,10
10
10

-

--

-

-

-

7,10
6,10
10
10

-

-

-

1,10
1,10,12

~

-

-

-

-

6,7,14

-

-

-

-

6,7

-

-

-

5

14

-

-

-

-

-

-

6,7,14

-

5

-

-

-

1,10

-

-

-

-

6,7

-

1

-

10,14

-

6,7

-

1

10,11,14

-

-

-

6,7

1

-

-

10,14

-

\1

-

-

-

-

-

-

-

-

-

-

9

-

-

-

-

-

6,7

1

-

0.'

Vde

-

0.4

Vde

8

-

-

-

-

-

-57

mAde

-18

-57

mAde

-

-

-

-

-

-

2.4

-

Vde

2.4

-

Vde

-

8

-

-

-

-

-

!

-

40

mAde

-

46

mAde

-

-

-

-

-

-

-

-

6,7

5

-

-

5

5

-

-

-

-

10,14

1

9,10,14

-

10,14

-

10,14

5

-

-

-

-

5

1.

-

5

-

-

1

-

5

-

-

-

-

-

5

-

1

1

-

5

-

-

-

10,14

5
--

-

-

-

6,7,10

1

\

8,10,14

Power Requirements
(Total Device)
Power Supply Drain
Pulse 1:

MOJ?1entarily apply Vth 1 then ground prior to taking measu:rement to set the device in the desired state.-,- Vth 1

Pulse 2:

Applil positive pulse prior to taking measurement to set the device in the desir~d state. rI- VIH
...J L GND
Maintain ground for measurement.

Maintain ground for measurement.,

CD All input}

power supply and ground voltages must be maintained between each test unless otherwise noted.

L GND

-

~

.rN

"T1

-

-20

8

V OH

-

Unit

V'hL Vcc VCCL VCCH

10L

-20

9

1

~

---

Max

N
"T1

.r

Volts
V,L

11

11

1

-

JlAdc

12

-

Output

Min

40
40
80
160

C1
C2

IR2

MC5492
MC7492
MC7492 Test Limits
o to +70°C

mAde

~

rnA

!-------o8

-1. 6
-1. 6
-3.2
-6·1

6
7
14
1

RO

Output Voltage

6

n
~
(g

12

A

"-c
8:J
!:!".

:J

c:

<1l

a.

MC5492F ,L, MC7492F ,L,P (continued)

SWITCHING TIME TEST CIRCUIT

Vcc
+5.0 Vdc

Coax·

•

950
±1.0%

950
±1.0%

390
±5.0%

C2

14

Pulse

Generator

B

C1
C

11
MMD6150

9

or Equiv

50
Duty Cycle = 50%

-=

RO

RO

D

8

MMD7000
or Equiv

6

fTog = 10 MHz min

CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.
"The coax delays from input to scope and output to scope must be matched.
The scope must be terminated in 50-ohm Impedance. The 9S0-ohm resistor and

and the scope termination impedance constitute a 20: 1 attenuatar probe.
Coax shall be CT -070-50 or equ ivalent .
... A load is connected to each output during the test.

VOLTAGE WAVEFORMS AND DEFINITIONS

TPin

t+ t-

Pulse V (f Tog test)
PRF = 10 MHz
Pulse Z (t'pd test)
PRF = 1.0 MHz
TP out A

TP out B

TP out C

Ir~~~~~~~~~~~~~~"""d--

TP out 0

~::;;:================--

____ __________
~

2.4 V min

-'~ 0.4 V max

MC5400/7400 series
4-BIT BINARY COUNTER

MC5493L*
MC7493L,P*

This 4-bit counter is comprised of two sections: a divide-by-two section and a divide-by-eight section. These sections can be used independently. or can be connected to provide the divide·by-16 function. All
outputs of the counter can be set to the logic "0" state by applying a
logic "1" level to the Reset input.

TRUTH TABLE

Connect ao to

C1

•

OUTPUT
COUNT

Q3

Q2

Q1

QO

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Input Loading Factor
RO.= 1

CO,Cl =2
V CC =Pin5
Gnd = Pin 10

Output Loading Factor = 10
Total Power Dissipation = 160 mW typ/pkg
Propagation Delay Time = 20 ns typ/bit

TYPICAL FLIP·FLOP

RESET GATE

VCCo----.---------,
1k

VCCo----------.--------~--------------_.------~r_--,

5.6 k

4k

5.6 k

3k

RO
RO

. Clock

O--+--+-.....- ....----1I--.....-~

3.2 k

Gndo---------~~~

·L suffix = TO-116 ceramic dual in~line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 60S).

4k

1.4k

100

--.-_

..

:s:

ELECTRICAL CHARACTERISTICS

n

Test procedures are shown for only one

~w

input of the reset gate. The other input is
tested in the same manner.

r-

l

:s:

01 9

n
.....

02 8

03

RD

~

w
r"'-c

11

2T3

nO

TEST CURRENT/VOLTAGE VALUES (All Temperatures)

mA
IOL

Pin

MC5493 Test Limits

Input
Forward Current

Leakage Current

Output
Output Voltage
Short-Circuit Current
Output Voltage

00

01

02

03

Symbol

Test

RO
CO
(;1

,
,

Max

Unit

'F

2
14
1

-1.6
-3.2
-3.2

RO
CO
C1

'R1

2
14
1

AO
CO
(;1

'R2

2
14
1

CD
CD
CD I
CD I

VOL
'SC
VOH

12

VOL
ISC
VOH

9

VOL
ISC
VOH
VOL
'SC
,VOH

+

,,
+

Min,

o to +70oC

mAde

40
80
80

JlAdc

40
80
80

,uAdc

1.0

mAde

1.0

mAde

+

+

0.4
-57

Vde
mAde
Vde

0.4
-57

-20
2.4

0.4
-57

-18
2.4

0.4
-57

-18
2.4

0.4
-57

-18
2.4

Vde

V,L
0.4

-0.4

0.4

IOL

IOH

2.4
2.4

VIHH

J

5.5
5.5

.1

VRI

Vth 1

VthO

4.5
4.5

2.0

0.8

2.0

0.8

0.4
-57

-18
2.4

J

Vth L

VCCl

0.7

4.5

0.8

4.75

5.25

V,L

V,H

VIHH

VRI

Vth 1

Vth 0

VCCl

VCCH

Vth L

2
14
1

:::J

r:::
CD
c..

VCCH

1

5.5

1

10

10
10

+

3.10
10
10

+
2.3

mAde

12

Vde

2.3

1.
14

14

1

2.3

mAde

Vde
mAde
Vde

10

2.3

8

2.3
11

,
+
1

2.3
11

10
2.3.10.12
10

10
2.3.9.10

2.3

mAde
Vde

,

Gnd

3,10

l'
1
12

,

I Pulse

5

2
14

+
Vdc

V,H

1

Vde

Vde
mAde

IOH
-0.4

Vdc

Vde
mAde

1

::to

TEST CURRENTiVOLTAGE APPLIED TO PINS LISTED 8ELOW,

Vde

Vdc
mAde
Vdc

Vde

11

,
,

-1.6
-3.2
-3.2

0.4
-57

-20
2.4

Min

mAde

A.'

8

16

Unit

-57

-20
2.4

MC7493

Max

+
-20
2.4

16

MC7493 Test Limits

-55 to +12SoC

Under

Characteristic

MC5493

:::J

Volts

2.3

,.

10
2.3.8.10
10
10

2.3.10.11
10

Power ReqUirements

(Total Device)
Pow!'!r Supply Drain
Pulse 1:

CD

IpO

-

I

46

I mAde I

-

I

53

Apply positive pulse prior to taking measurement to set the device in the desired state.
Maintain Vth L voltage for measurement.

I mAde

JTVIH
Vth L
All input, power supply and ground voltages must be maintained between each test unless otherwise noted.

10

MC5493L, MC7493L,P (continued)

SWITCHING TIME TEST CIRCUIT

Vee
+5.0 Vdc

950
±.1.0%

400

MMD6150
or Equiv

Pulse
Generator

Duty Cycle

Q2 8

= 50%

Q3 11

50 pF

1_ -=-

MMD7000
or Equiv

fTog::: 10 MHz min

CT "" 15 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.

"'The coax delays from input to scope and output to SCOpe must be matched.
The scope must be terminated in 60~ohm impedance. The 950-ohm resistor and

and the scope termination impedance constitute a 20: 1 attenuatar probe.
Coax shall be CT-070-.50 or equivalent .

.... A load is connected to each output during the test.

VOLTAGE WAVEFORMS AND DEFINITIONS
Clock
Pulse A
~ 10 MHz

PRF

Pulse B

PRF

= 1.0 MHz
QO

Q1

Q2

OV
-2.4 V min

====--__==__-===--__==_--+-===-__==__-===-__=='----+-==0.4 V max
-2.4Vmin

G~~N~O~====~---~~======~---~========~---~~======~---~~O.4vmax
, - - - - - - - - - k - 2 . 4 V min

=G7N~D~===========~-~------+~==~==========.---:;-,-------+~O.4

Q3

GND

Vmax

MC5400/7400 series
4-BIT SHIFT REGISTER

MC5494
MC7494
Compatible with MC5400/7400 Series dovices.

ADVANCE INFORMATION/PRODUCT PREVIEW*

Soon to be announced, the MC5494/7494 4-bit shift register is constructed of four R-S master-slave flip-flops plus internal
gating to accomplish right-shift or parallel-to-serial conversion.
Right-shift operation is accomplished by entering serial data at the serial input prior to the positive transition of the clock
pulse.
Parallel operation is accomplished by first clearing all flip-flops and then setting the appropriate flip-flop(s) to the logic "1"
state. The common clear input is independent of the clock input, and the separate preset inputs are independent of either clock
or clear inputs.

(~

Presets
____________________
____________________
~A~

1A

2A
16

1B

2B
14

1C
3

2C
13

1D
4

~,

2D
11

Preset 2 15

Preset 1

6

Q

s

Serial Input
Clear

Clock

Q

s

s
C

o

Clock

Clock

Clock

R

Clear

5.

R

Clear

5.

8

Clear 10

Vee = Pin 5
GND = Pin 12

Total Power Dissipation = 175 mW typ/pkg
Propagation Delay Time (Clock to Output) = 25 ns typ
Maximum Toggle Frequency = 10 MHz

"'Products to be introduced

9 Output

B

A

R

Clear

MC5400/7400 series
4-BIT SHIFT REGISTER

MC5495· MC7495
Add Suffix F for T0-86 ceramic package (Case 607).
Suffix L for TO·116 ceramic package (Case 632).

Suffix P for To-116 plastic package (Case 605) MC7495 only.

The MC5495/7495 performs as a right-shift or left-shift register,
Input Loading Factor:
Mode Control = 2
Other Inputs"'" 1

or a parallel-in/parallel-aut storage register. depending on the logic
level present at the Mode Control input.
The device consists of R-S master-slave flip-flops, high and

Output Loading Factor = 10
Total Power Dissipation = 250 mW typ/pkg
Propagation Delay Time"" 25 ns typ

low-level gates and inverters interconnected as shown by the
logic diagram.

•

Maximum Shift Frequency"" 31 MHz typ

Vee = Pin 14
Gnd= Pin
Serial I "put

Os

7

1
2

CpO

6
Mode Control
Clock 2 Left Shift

Clock 1 Right Shift

8
9

13
00

10
03

3
Cpl

LOW-LEVEL "AND-OR-INVERT" GATE WITH INVERTER DRIVER
r---------------~----~--------ovcc

LOW-LEVEL INVERTER
r---------~-----r----~-ovcc

s

'----Hot---<: R

R·S MASTER-SLAVE fliP-flOP
tOiode used only when
input is connected to
external point.

HIGH-LEVEL "AND-OR" GATE
r-------~------~------~~--~ovcc

4k

4k

4k

a

1.5k

so-t---~:.l

:t: Diode used only when input is
connected to external point.

Clock 0--+----+------------+----'

MC5495, MC7495 (continued)

ELECTRICAL CHARACTERISTICS

Vee"" Pin 14
Gnd

= Pin

7

TEST CURRENT/VOLTAGE VALUES (All Temperatures)

rnA

10L
MCS495 16
MC7496 16

Volts

10H

V,L

V,H

-0.4
-0.4

0.4
0.4

2.4
2.4

VIHH VR

V t h1

VthO

0.8
0.8

5.5

4.5

2.0

5.5

I 4.5 I

2.0

I

Vee VCCL VCCH

5.0
5.0

4.5

5.5

4.75

5.25

MC5495TestLimits MC7495TestLimits

Pin

Characteristic
Input
Forward Current

leakage Current

Symbol

-56 to +126oC
Un...
Toot Min Max Unit

'F

-1.6 mAde

'Rl

-3.2
-1.6
-1.6
40 "Adc

~

1
2
3
4
5
6
8

~

9

'R2

Mo.

Unit

-

-1.6 mAde

-

-3.2
-1.6
-1.6
40 #-lAde

~

j
j

80
40
40
1.0 mAde

TEST CURRENT/VOL TAGE APPLIED TO PINS LISTED BELOW:

Oto +700c

Min

--

jj

~

10L

10H

V,L

V,H

V,HH VR

Vthl

VthO

Vee VCCL VeeH
14

VOL

VOH

Short-Circuit Current

lse t

10
11
12
13
13
10
11
12
13
13
10
11
12
13

Power Requirements
Power Supply Orain

'PO

"

0.'

j

j

+
B

6

j

80
40
.0
1.0 mAde

0.'

~ ~

Vdc

2.'

~

-18

Vdc

~ ~

Vde

2.'

~ ~

-57 mAde -18

~

j

6
6

tOnly one output should be shorted at a time.

mAde

-

I.

10
11
12
'3
13

mAde

I.

2.3,4,5

1,6
1,6
1,6
10
11
12
13
13

-

3.4,5.6

-

2,3.4,5

•

2,3,4.5.6

I.

~

~

+

7
6,7
7
8

~

2,3.4,5

-57 mAde

82

+

7
6,7
7
7
6,7

j

+ + + + + +
72

1

6,7
7
6,7

I.

j j

Vdc

6.7
7

6

Output
Output Voltage

Pulse
Gnd
1

+
8

~
I.

+ +
I.

B,9

7

~

7

~

7,10
7,11
7,12
7.13

MC5495, MC7495

(continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vcc
Coax·

400

MMD6150
or Equiv

t+

= t- ~

24 os

(10% to 90%)

50

MM07000
or Equiv

Two pulse generators are
required and must be slaved
together to provide the waveforms shown.

The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the

scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT -070-50 or equivalent.
CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.

SWITCHING TIMES

PRF

=

A
500 kHz

B
PRF = 1.0 MHz

c

-<+-------------+~~~~----_Y~----------~~----------L---------------~OV

------LT-----t~~L------t~--~----_i~--~------~--~------~--OV

~----------'\:-.-------------- 2.4 V min

=======~/______________~======-______________~.=======g.~dV

max

RECOMMENDED SETUP AND RELEASE TIMES FOR MODE CONTROL INPUT
D
Serial Input

E
Clock 1

,----y------------------------------- 3.0

V

1.5 V

------~------~----------------~------~----------------------------OV

,---,---------------3.0 V
Clock 2

1.5 V

______________+-______Lt______
ts etup

~~~------------L-------J---~--------OV

"0"

, - - - - - - - - - - - 3.0 V

G

M ode Control ________--'______________...L~----~--~------''----------------L.-------------- 0 V
ts etup " ' "

H
Output QO

/

\

tRelease "1"

/r---_____\----2.4

V m;n

===========:______________~======__________________'~====~.~dV

max

•

MC5495, MC7495 (continued)

SWITCHING TIME TEST PROCEDURES (T A ~ 25°C)
(Letters shown in test columns refer to waveforms.)

TEST
Propagation Delay Time

•

tpd+

Clock to Output

tpd_
Maximum Shift Frequency

Setup Time, Serial or
Parallel Inputs

MC
Pin 6

C2
Pin 8

C1
Pin 9

QO, Q1, Q2 or Q3
Pin 13,12,11,or 10

0.4 V

Gnd

B

C

-

26

35

ns

-

A

2.4 V

B

Gnd

C

-

26

35

ns

A

-

0.4 V

Gnd

B

C

-

26

35

ns

-

A

2.4 V

B

Gnd

C

-

26

35

ns

f max

Tasted during tpd tests.

Clock 2
ReleaseTime, ModeControl tRelease
Clock 1

Clock 2

20

31

-

MHz

-

10

20

ns

-

-10

0

ns

QO

OPO
tsetup

Unit

-

tHold

Setup Time, Mode Control
Clock 1

Min Typ Max

A

tsetup

Hold Time, Serial or
Parallel Inputs

VALUE

OUTPUT

INPUT
Os
0PO, OP1, 0p2 or OP3
SYMBOL Pin 1
Pin 2, 3, 4, or 5

D

0.4 V

G

0.4 V

E

H

-

-

20

ns

D

0.4 V

G

F

0.4 V

H

-

-

20

ns

D

0.4 V

G

0.4 V

E

H

-

-

10

ns

D

0.4 V

G

F

0.4 V

H

-

-

10

ns

OPERATING CHARACTERISTICS

Data Input

FIGURE 1 - SERIAL RIGHT·SHIFT OPERATION

Logic "0"

For serial right-shift operation, the Mode Control input is held at a logic "0".
This enables the "A u AND gates and inhibits the "B" gates, coupling the output of
each flip-flop to the input of the succeeding flip-flop, and inhibiting all four parallel
data inputs and Clock 2. Serial data is entered at Os and the clock pulse applied at
Clock 1. The input information shifts one output to the right on each negative edge
of the clock pulse.

~ DS

00 ~Data
Output

~ C1

01

L09iC"1"~
Clock

PUlse~
2

3
4

I

Clock Pulse

Data
Output

MC·
FIGURE 2 - SERIAL LEFT-SHIFT OPERATION

12

C2

DpO
Dp1
Dp2

I~~~t~ Dp3

02

~

03~

For seria~ left-shift operation, the Mode Control input is held at a logic "1".
This enables the "B" ANO gates and inhibits the "A" ANO gates, decoupling the
output of each flip-flop from the input o~ the succeedin9 flip-flop. The output of
each flip-flop must be externally connected to the parallel data input of the preceding flip-flOp. Serial data is entered at input Op3 and the clock pulse applied at
Clock 2.

A parallel-in/parallel-out storage register is obtained by applying
a logic "1" level to the Mode Control input, applying parallel data
at inputs 0PO, 0P1, OP2, and OP3, and a clock pulse at Clock 2.
In either mode, information is transferred to the outputs of the
device on the negative transition of the clock pulse.
The Mode Control must be in a logic "0" state 20 ns (tsetup "0")
prior to the negative transition of the Clock 1 pulse, and in a logic

"1" state 20 ns ItSetup "1") prior to the negative transition of the
Clock 2 pulse. The Mode control must also be in a logic "0" state
10 ns (tAelease "0") prior to the positive transition of the Clock 2
pulse, and in a logic "1" state 10 ns (tRelease "1") prior to the
positive transition of the Clock 1 pulse.
Clock 1 must be high when the Mode Control goes from high to
low. Clock 2 must be high when the Mode Control goes from low
to high.

MC5495, MC7495 (continued)

TYPICAL APPLICATION
These diagrams show the external gating and
connections required for a divide-by-N counter.
When the MC549517495 is operated in the serial
mode, a 2-input NAND gate is the only gating required for all odd functions; a single inverter is

sufficient for all even functions.

13

DS
MC
C1
C2
DpO
Dp1
Dp2
Dp3
DIVIDE-BY-8

03

10

MC5400/7400 series
5-BIT SHIFT REGISTER

MC5496
MC7496

ADVANCE INFORMATION

Soon to be announced, the MC5496/7496 5-bit shift register is constructed of five R-S master-slave flip-flops plus internal
gating to accomplish.serial-to-parallel or parallel-to-serial conversion, and parallel-in/parallel-out or serial-in/serial-out operation.
Right-shift operation is accomplished by entering serial data at the serial input prior to the positive transition of clock pulse.
The common clear input is independent of the clock, and the separate preset inputs are independent of the clock or clear
inputs.
The clear input must be at a logic "1" level and the preset input must be at a logic "0" level when clocking occurs.

Preset A
2

Preset Enable

Preset B
3

Preset C
4

~

~

~

~

16

14

13

11

10

SQ---------+-----f-----i-+---+--+.....---i---+--1--+----1h

Q

s

s
B

R

9
Clear

Clear

s

c

Q

E

Clock

Q

R

s

o

Clock

Clock

Clock

Preset E
7

~

A

Serial Input

Preset D
6

Clear

1

Clear 16

Vee:; Pin 5
GND"" Pin 12

Total Power Dissipation = 240 mW typ/pkg
Propagation Delay Time (Clock to Output) "" 25 ns typ
Maximum Toggle Frequency"" 10 MHz

Clock

Q

R
Clear

R
Clear

'\
DUAL J-K FLIP-FLOP

MC5400/7400 series

'------------'

MC54107L*
MC74107P,L*

This negative-edge-clocked dual J-K flip-flop operates on the masterslave principle, The device is quite useful for simple registers and counters where multiple J and K inputs are not required_

J8'y5

CTIiCK

9

0.

K 11

RESET

tn

6

10

J1D3

CLOCK 12
K

RESET

4

K

Q

0

0
1
0
1

an

0
1
1

_

a

tn+1

J

LOGIC DIAGRAM
(1/2 OF DEVICE SHOWN)

0
1

o.n

2

a

13

6

5

t--=:::"'-I~10

Input Loading Factor:

0.
RESET

J, K = 1
RESET, CLOCK = 2
Output Loading Factor = 10

K 11

8 J

Total Power Dissipation"" 80 mW typ/pkg
Propagation Delay Time
Operating Frequency

= 30 ns typ

= 15

MHz typ

·L suffix = TO-116 ceramic package (Case 632)

P suffix

= TO-116 plastic package (Ca.. 605)

See General Information section for package outline dimensions.

1/2 OF CIRCUIT SHOWN
.-----~~--------~----------~--------~------._-------------o14

VCC

a

50---+--"

+--......- - - _ 0 6

~-------4----------~-----+-r--------~--------4_----+_0GNO
L-~--------------------~~.----o10

RESET

1

....-----08
K

MC54107L, MC74107P,L (continued)

OPERATING CHARACTERISTICS

•

Since no charge storage is involved in this flip,-flop, rise and fall

Data must be applied to the J-K inputs while the clock is low.
When the clock input goes to the positive logic "'" state, the data
at the J and K inputs is transferred to the master section, where it
is stored until the clock changes to the positive logic "0" state.
Data at the J and K inputs must not be changed while the clock is

as '.0 jJS will not adversely affect the operation of the flip· flop.
The clock pulse need only be wide enough to allow the data to
senle in the master section. This time, which is the setup time for

high. When the clock returns to the positive logic "0" state, infor-

a logic "1", is 20 ns minimum.

mation in the master section is transferred to the slave section.
Application of a logic "0" to the RESET input will force the
output to the logic "'" state. The RESET input overrides the
clock.

Transistors QA have been added to the standard flip-flop circuit
to protect the device against negative clock transients. This addition prevents both outputs from changing to the logic "I" state
when transients in excess of -2.0 V appear at the clock.

o

times are not important to its operation. Clock fall times as long

SWITCHING TIME TEST CIRCUIT

Vee
+5.0 V

400

PULSE
GENERATOR

MM06150
or Equiv.

50

t-:::: t+~

f

5.0 ns

= 10 MHz for waveform

A
1.0 MHz for waveforms Band C

r

Two pulse gene.rators are required and must be slaved together for tsd tests;.

• The coax delays from input to scope and Ol,.ltput to scope must be matched. The
scope must be terminated in 50-ohm impe-d~nce. 'The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT -070-50 or equfvalent .
•• A load is connected to each output during the test.
CT == 15 PF ::: total paraSitic capacitance, whi'ch inciudes probe, wiring, and load
capacitances.
-,

MMq7000

or Equiv.

MC54107L, MC74107P,L (continued)

TEST PROCEDURES
(Letters shown in test columns refer to waveforms.)

INPUT
TEST

SYMBOL

Q

Q

C

J, K

R
2.4 V

t

t

Toggle Frequency

fTog

A

A

Turn-On Delay

LIMITS
Min

Max

Unit

10

-

MHz

n,
n,
n,
n,

tpd_

B

B

2.4 V

0

0

10

50

Turn-Off Delay

tpd+

B

B

2.4 V

E

E

10

50

Turn-On Delay

tsd-

B

B

C

F

-

-

50

Turn-Off Delay

tsd+

B

B

C

-

G

-

50

Enable Voltage

VEN

B

2.0 V

2.4 V

t

t

t

-

-

Inhibit Voltage

VINH

B

0.8 V

2.4 V

:j:

:j:

:j:

-

-

tOutput shall toggle with each input pulse.

t Output shaU

NOT toggle.

VOLTAGE WAVEFORMS AND DEFINITIONS

A.B

J./

TPin

1---20

2.4 V

"\
n' min-I\.

1.5V
0.4 V

GND

25 ns min

5000'

C

2.4 V

TPin

1.5 V

1.5)1\

FiEsEi'

0.4 V

GND

0

TP out
GND

2.4 V min

!---tpd_.~.5V

0.4 V max
2.4 Vmin

E

f-tPdjt,

1.1; V

TP out

0.4 V max
GND
2.4 V min

F

.~.5V

TPout

-t,d_
GND

--1/

-t,d+

G

TP out
GND _ _ _ _ _ _ _ _

0 .4 V max
2 .4Vmin

~-----_,,-..:~========~7==11.=5=V======0.4

V max

•

--

ELECTRICAL CHARACTERISTICS

s

(")

Test procedures are shown for only one
flip·flop. The other flip·flop is tested in

C1'I

-1=00
....
o

the same manner.
J

......

8~5

r

C'LOcK9~ 6

3

rnA

2

MC54107
MC74107
Pin MC54107 Test Limits MC741 07 Test Limits
55 to +125°C
to +70°C
Under
Symbol Test
Min Max
Unit Min Max
Unit

Characteristic

-

8
11
10
9

-

-1. 6
-1. 6
-3.2
-3.2

mAde

Reset
Clock
J

8

-

40
40
80
80

IlAde

-

~

--

mAdc

Forward Current

J

K

Leakage Current

K
Reset

IF

IRI

10
9

Clock

J

K
Reset

11

-~

~

-1. 6
-1. 6
-3.2
-3.2

mAde

40
40
80
80

IlAdc

-

1.0

mAde

-

-

~
~

IOH
-0.4

0.4

2.4

5.5

4.5

2.0

0.8

5.0

4.5

5.5

-1=00
....
o

16

-0.4

0.4

2.4

5·5

4.5

2.0

0.8

5.0

4.75

5.25

~."

IOL

Short-Circuit Current

---

V1H

V1HH

VR

-

8
11
10
9

-

-

-

-

-

-

10

-

-

-

8
11
10
9

-

-

-

-

-

V.h1
-

-

-

-

-

-

-

-

-

-

-

10

10

9,10
9,10
8,9
2,3,14

-

-

-

-

-

-

-

-

8
11
10
9

-

-

-

10

-

10

-

-

-

~

VOL

5
6

-

0.4
0.4

Vdc
Vdc

-

0.4
0.4

Vdc
Vdc

5
6

-

-

V OH

5
6

2.4
2.4

-

Vde
Vdc

2.4
2.4

-

Vdc
Vdc

-

5
6

-

-

-

ISC

5
6

-20
-20

-57
-57

mAde
mAdc

-18
-18

-57
-57

mAde
mAde

-

-

-

8,9,11
8,9,11

-

-

-

-

-

IpD

14
14

-

-

32
32

mAde
mAde

-

32
32

mAde
mAde

-

--

-

-

-

-

-

------

Vcc

-

~

! !

V. hO

--

Power Requirements
(Total Device)
Power Supply Drain

V1L

-

Output
Output Voltage

IOH

1.0

Clock

VCCH

......

r-

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BElOW:

-

8

11

......

16

10
9

IR2

s

(")

IOL

o

Input

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
Volts
V1L
V1H V1HH
VR
V.h 1 V.hO VCC VCCL

-

-

-

10

-

-

VCCL

VCCH

**

Gnd

-

14

5

~

6

7'
7'

-

7'

-

14

-

--

-

-

-

~
14

c

[

7'

-

7,9,10*
7,9**
7,8,9 ,
7,8,10,11

-

7,9,10*
79*
'
7,8,9 '"
7,8,10,11

,

!

10

14
14

-

-

-

14
14

-

6

-

-

-

14
14

6

5,7*

-

6,7,10*

-

14
14

-

-

7,10,13
7

-

-

-

-

-

-

-

6

-

2,6

~

s·

10
10

8
....

7,8,9,11*
7,8,9,11*
7,8,9,11*
7,8,9,11 *

"'Ground inputs to flip-flop not under test.
"''''Momentarily ground pin prior to taking measurement to set flip-flop in the desired state. (If pin is also in another column, the pin must be returned to that voltage or current for measurement.)
tTest duration ~ 100 ms.
TUnder normal operating conditions this current is negative. This test guarantees that positive leakage current will not exceed the limit shown.

MC5400/7400 series
MONOSTABLE
MULTIVIBRATOR

MCS4121F,L*
MC74121F,L,P*
This monostable multivibrator produces accurate output
pulses from either edge of an input pulse. The output pulse
widths may be varied from 40 nanoseconds to 40 seconds
by using appropriate external timing components. Internal
compensation provides pulse width stability of better than

ex

+,/-

Sf lot
Al
A2

~~

1.0% with variation of Vee and ambient temperature. In
most applications, overall stability will be determined by
the accuracy of the external components. Inputs A 1 and
A2 trigger on the negative·going edge of the input pulse,
and input B triggers on the positive·going edge .

•

RX

~~

2k

Input Loading Factor"" 1
Output Loading Factor"" 1 a
Total Power Dissipation = 90 mW typ/pkg
(50% duty cyc'e)

~6Q

B 5

~1

Q

Vee = Pin 14
GND"" Pin 7

TRUTH TABLE
tn INPUT

tn+1 INPUT
OUTPUT
AI A2
B

AI

A2

B

1

0

1

1
1

0

1
X

X

0

0

1
X

X

0

0

X

X
1
1
X

0

0
0

1
1

1
1

0

0

0

X
0
X,
1
1

0
1
1
0
0

X
0

1
1

0

X

X
X

0
0

0

X
1
X
1
1
0
X

X
1
1
1
X
0

1
0
0

1
1
1
1
0
0

1
1
0
0

Inhibit
Inhibit
Inhibit
Triggering
Triggering
Triggering

Triggering
Inhibit
Inhibit
Inhib1t
Inhibit
Inhibit
Inhibit

X =' Don't care
tn = Time period prior to input transition
tn+1 = Time period following input transition

·F suffix

= T0-86 ceramic flat package (Case 607).
L suftix = TO-116 ceramic dual in-line package (Case 632),
P suffix = TO-116 plastic dual in-line package (Case 605).

•

ELECTRICAL CHARACTERISTICS

s:

(")

Test procedures are shown for only one A
input.

...
(.TI

The other A input is tested in the

+:0-

same manner.

...
N

s:

(")

"N
....
~

...

2 k

A13~

--06

n-O

Q

A24~

::J
~.
::J

TEST CURRENT/VOLTAGE VALUES (All Temperatures)

B 5

f---o1

rnA

Q

C

Volts

CD

0..

VCCH

Pin
Under
Characteristic

T."

Symbol

MC54121 Test Limits
-55 to +12SoC
Min

input

Forward Current

'F

Leakage Current

'R1
3

5

2.4

VOH

-20

'SC

Power Requirements
Power Supply Drain

Unit

I

-1.6

mAde
mAde

40
80
1.0
1.0
0.4

VOL

Short-Circuit Current

Max

-3.2

IR2

Output
Output Voltage

I

-20
14
14

IpO

I Max
-1.6

-3.2

.u Ade

5.25

Unit

=

V,L

I

V,H

mAde
mAde

I

V,HH

I

VR

Vth 1

Vth 0

Vee

VCCl

VCCH

Gnd

4
3,4

14
14

6",7
4,5,7
7

pAde

5,7

.uAdc

IlA de

3,4

14
14

mAde
mAde

1.0
1.0

mAde
mAde

3,4

14
14

4,5,7
7

Vdc
2.4

-55

-18
-18

25
40

mAde

mAde

0.4

Vdc

-55
-55

mAde
mAde

9,14
14

1,3,4,5,7
3,4,5,6,7,10,11" ..

25
40

mAde
mAde

9,14
9,14

3,4,7
3,4,7

Vdc

Switching Parameters

(ex

IOH

10L

40
80

Vdc

r -55

5.5

MC74121

MC74121 Test limits
o to +70 o C
Min

mAde
mAde

-

MC54121

6

Pulse
In

80 pF unless otherwise

I

3,4,5

14

3,4,5

14

7,11

Pulse
Out

-

noted.)

Turn-Off Delay - A to

Q

6
6

tpd+

B to Q

Turn-On Delay - A to Q
8 to Q
Output Pulse Witdth

tpd-

70#
55#
80#
65#

PW

With Internal Timing Resistor
With eX"" 0
With RX = 10 kH, Cx "" 100 pF
RX'" 10kn, Cx = 1.01lF
Minimum Duration of
Trigger Pulse

70'lf
55#
80#
65#

5,1

tHold

I

+

5,1

"Momentarily ground this pin before taking measurement .
..... Pin 10 should be grounded after pin 11.
#Tested only at 250 C.

70#
20.::t"
600#
6.0#

150#
50#
800#
8.0#
50#

n,

t

70#
20#
600#
6.0#

150#
50#
800#
8.0#
50#

4,5

9,14
9,14

4,5

9,14
9,14

3,4
3,4
1

"'

t

+

+

9,14
9,14
14
14

3,4,7

9,14

3,4,7

+

MC54121, MC74121 (continued)

TEST CIRCUIT AND VOLTAGE WAVEfORMS

r-----------,
I vee
I

I Pulse

eX

IW~~

I Test
LC~c~~__

r------I

RX
10k

Vee

I
I

I
I
I

__J
10

9

400

11

r+--~_;,

I

2k

MMD6150
or Equiv

PRF

=::

PW

-=

t+

=.

t-

=.

1.0 MHz

50 ns
(1.5 V·points)

50

MMD7000
or Equiv

6.0 ns
12 ns

L _ _ _ _ _ _ _ _ _ _ _ _ --'

The coax delays from input to scope and output to scope must be marched. The
scope must be terminated In 50-ohm Impedance, The 9SO-ohm resistor and the

scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT -070-50 or equivalent.
CT = 15 pF = total parasitic capacitance. which includes probe, wiring, and load
capacitances.

OUTPUT PULSE WIDTH

SWITCHING TIMES

TPin

B

--f.J=

r----t±con;;;z--3.0 V

.5 V

(I nvert for

A1,A2)

==!....--OV

3.0 V
OV

tHold

~-------:'2.4

V

TP out

TP out

Q

Q

,----,----:.2.4 V
,,0.4 V

===I==========~~.6 V

------t-----------r-----GND

----+"--,---------:.2.4 V
TP out
Q

_____+---.:+=========="0.4

:'2.4

V

TP out

Q

GND V

APPLICATIONS INFORMATION

1.2 vOlts: Internal latching circuitry provides for a typical noise
immunity of 1.5 volts on the Vee line.
During the active state, the outputs are independent of further
transitions on the inputs and depend only on the external timing
components. With no external timing components and pin 9 connected to VCC (pins 10 and 11 left open), an output pulse of

Inputs A 1 and;.A2 are' negativ'e-edge-triggered ar:-d will trigger
the monos table mu Itivibrator into the' active state when either or
both go low while B is high. The B ~nput will trigge~ the one-shot
when B goes hjgh whi!.e .either· A or B i-s low. Triggering occurs at a
particular vortage leve~.and is independent of the input pulse transition time. The Schmitt-trigger capability of th.e B input can be used

to obtain level detection and t~ process relati,vely s~ow leading edges.
Jitter-free triggering is obtai ned with transition times as slow as 1.0
volt/second, providing the circuit with ~ typical noise ;mmunity of

approximately 30 nanoseconds is obtained. An external timing
capacitor connect~ between pins 10 and 11 wjll extend the pulse
width. Accurate repeatable'pulse wfdth'may be obtained by leaving
pin 9 open and connecting an external resistor between pin 11 and
VCC. This resistor should be at least 1.4 kilohms and may be as
large as 40 kilohms for the MC74121 and 30 kilohms for the
MC54121. The timing capacitor may be as large as 1000/'F.

Within these limits, the output pulse width is given by:
PW

= CXRX

loge 2.

•

MC54121, MC74121 (continued)

FIGURE 4 - OUTPUT PULSE WIDTH versus
EXTERNAL TIMING RESISTOR VALUE

FIGURE 1 - SCHMITT TRIGGER THRESHOLD VOLTAGE
versus TEMPERATUR E

~o

1.B
1.7

~

w

Cl

«

1.6

f-

..J

..

o
>
o
..J
o

10 m 5

1.5
1.4

"" '"
~

~

'"
W

0:
J:
f-

1.0m 5

.............. ~e-GOin

-55

b
;:

~e-Goinlg Thresrold

1001'5

..
..

o

25

75

50

100

125

I::l

0:

+10

>
0:

f-

+5.0

'"w

iii
0:
...J

«
Z
0:
W
fZ

..-""1

...-Y

1.01'5

100 pF

Cx

..,....

....,.... .....-

..,.... V

,.,..- ......

,.,..- V
Cx - 10 pF

+15

«

o

V

5

100 n s

FIGURE 2 -INTERNAL TIMING RESISTOR VARIATION
versus TEMPERATUR E

f-

~

.......r---

I::l

t

..-""1

V

..,.... V

o

~
Z
o

/'

Cx = 1000 pF

w
~

::l

-25

V

......r

Cx - 0.01 jJF

TA. AMBIENT TEMPERATURE (oC)

I

..,.... V

V

1.3

1.2

Cx = 0.1 jJF

V

Thres1.o'd

J:

'-

J:

1.0jJF

=Cx

o
-5.0
-55

f-.--

--

o

-25

V

/

/

/

10 n 5
1.0

3.0

5.07.0 10

30

,./

25

75

50

100

125

TA. AMBIENT TEMPERATURE (oC)

FIGURE 5 - OUTPUT PULSE WIDTH versus
EXTERNAL CAPACITANCE

J:

l-

FIGURE 3 - OUTPUT PULSE WIDTH VARIATION
versus TEMPERATUR E

~
z
0

;::

«.
0:
«
>

~

cJ = 60 pl
+0.25 _RX=10k!l
TA = +25 0 C

..
..

w

J:

l-

e

;:
w

e

+0.50

0

-0.25

'"
::l
...J

/

/

/

~

::l

I::l

V

I::l

:/

I"'-pw

o

=

420 ns

5.25

5.5

~.

11.

-0.50
4.25

4.5

4.75

5.0

5.75

VCC.SUPPLY VOLTAGE (VOLTS)

50 70 100

RX. TIMING RESISTOR VALUE (k!l)

6.0
Cx. TIMING CAPACITOR VALUE

MC5400/7400 series

BCD TO ONE-Of-TEN
DECODER/DRIVERS

MCS414SL • MC7414SL,P-lC
MCS44SL • MC744SL,P-lC

1

C 13

D 12

These devices are intended for use as drivers for indicators or relays, rather than drivers
for MTTl logic gates, as is the case with the
MC5442/7 442, which isfunctionally identical.
The output transistors of these devices are
capable of sinking 80 mA, and have breakdown voltages of 30 V (MC5445/7445) and
15 V (MC54145/74145). The outputs are
suitable for open-collector logic applications,
and are compatible for fnterfacing with most
MOS integrated circuits. Since full decoding
is included, all outputs remain off for nonBCD inputs

0.0

2

(11

3

0.2

4

0.3

5

0.4

6

0.5

7

0.6

9

0.7

10 (1S
11 (19

Total Power Dissipation = 215 mW typ/pkg
Propagation Delay Time::;::: 50 ns max

Vee"" Pfn 16
GND= Pin 8

INPUTS

D C
0 0
0 0
0 0
0 0
0
1
0 "I
0
1
1
0
0
1
1 0
1 0
1
0
1
1
1
1

OUTPUTS

B A
0
0

0

1
1

0

09

0
0

0

1
1

0
0
1

0

O.

1
1
1

0
0
1
1
0
0
1

1
1
1
1
1
1
1
1
1

1

1

1
1
1
1
1
1

1
1
1
1

1
0
1

0
1

• L suffix '7' l6-pin dual in-Jin~ ceramic package (Case E?2c;Jl.
P suffix"" l6-pln duel in-line plastic package (Case 612).

QS
1
1
1
1
1
1
1
1
0
.1
1
1
1
1
1
1

07

Q6

1
1
1
1
1
1
1

1
1
1
1
1
1

0

0
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

05 04 03 Q2
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1
1

1
1
1
1

0
1
1
1
1
1
1
1
1
1

1
1

1
1
1

0
1
1
1
1
1
1
1
1
1
1
1
1

1
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1

01

00

1

0

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1

1
1
1
1
1
1
1
1
1

•

T
3:

ELECTRICAL CHARACTERISTICS

C')

Test procedures are shown for only one

...
CJ1

input and one output. Test other inputs

~

and outputs in the same manner according

to the truth table.

Test all input-output

./:110

tTl

.r

combinations according to the truth table.

s:

n
~

-..,

120

IslA

01

~

122
141 8

03

13 Ie

125

tTl

r

-

124

S

06

(")

07

CJ1

osf-2E
11

121 0

I

09

t

1

mA

MC54451MC54145
Test Limits
-55 to +125o C

Pin
Under

Characteristic
Input
Forward Current

Leakage Current
Output
Output Voltage
MC5445/7445
MC54145/74145

Power

Symbol

'F
'Rl
IR2
VOL
VCEX

Tost

Min

12
12

-

12

Max

MC5445, MC54145

20

SO

MC7445, MC74145

20

SO

'eEX
0.25

V,L

V,H

V,HH

0.4

2.4

5.5

0.25

0.4

2.4

5.5

MC7445/MC74145
Test Limits
o to +70o C

12

-

-

12

-

-

-

16
16

-

-

-

12

-

-

-

S
S
S

-

-

-

-

12,13,14,15
12,13,14,15

16
16

-

-

-

-

12,13,14,15
12,13,14,15

-

-

-

16
16

8
S
S
8

-

-

-

-

-

-

-

16

8,12,13,14,15

12,13,14
12,13,14

-

-

-

-

16
16

-

-

-

S
S

mAde

-1.6
40
1.0

mAde

.uAdc

-

-

-

0.9
0.4

-

0.9
0.4

-

1

1

-

-

-

30
15

Vdc
Vdc
Vdc
Vdc

-

70

mAde

-

1
1

-

-

-

16

Requirements

(Total Devicol
Povver Supply Drain

IpO

Switching Parameters
Turn-On Delay
Turn-Off Delay

- C.
#Tested only at 25 u

-

-

Pulse In

'p-3
:=J[>-4
:=J[>-10 [14)
[7)

[8)

[2)

1 2 = J [ > -11 [1)
[3) 13

Input Loading Factor::::; 2

Output Loading Factor = 10
Total Power Dissipation = 225 mW typ/pkg
Vee
GND

= Pin

= Pin

14 [4)
7 [11)

Numbers at ends of terminals represent pin numbers
for devices in the dual in-line package.
Numbers in brackets represent pin numbers for devices

in the flat package.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

TP out

TPin
84.2
)-I--'---+--,---1~~VVIr---<>2.6

V

5k

PRF = 1.0 MHz
PW= lOOns
t+ = t- = 5.0 ns

5 kG and 30 pF include jig and scope.

·F suffix = TO-S6 ceramic flat package (Cass 607).
L suffix =.TO-116 ceramic dual In-line package (Case 632).
P suffix = TO-116 plastic dual in-line package (Case 605).

~

3'OV

1.5 V

tpd+~ ~
TPout~1.5V

'

r-tP.dd--

~

OV

•

ELECTRICAL CHARACTERISTICS

s:

n

Test procedures are shown for only one

00

gate. The other gates are tested in the
same manner. Pin numbers indicated are
for devices in dual in-line packages only.
To test devices in the flat package, substitute pin numbers shown in brackets on
the logic diagram on the first page of this
data sheet.

~
.....
"T1

~

r
s:
C')

"

N
.j:Io
...a
"T1
I

:=L>-3
:=L>-4

~

:=:)[)-10
12=:)[)-11

@Test
Temperature

13

MC8241 {

MC7241

{

Symbol

I

Under

Test

MC8241 Test Limits
-5S0C
Min

I

Max

+25 0 C

I

Min

I

Max

lin

VIL

VIH

VF

VR

Vee

VCCL

VCCH

-550C

16

4.5

5.0

4.75

5.25

10

0.8
0.8
0.8

0.4

16
16

-0.5
-0.5
-0.5

2.0

+25 o C

5.0
5.0
5.0

4.75

4.75

5.25
5.25

-0.5
-0.5
-0.5

0.4
0.4
0.4

4.5
4.5

16
16
16

2.0
2.0
2.0

4.75

5.25

10

2.0
2.0

0.4
0.4

5.0
5.0

4.75
4.75

5.25

oOe
+250 C

MC7241 Test Limits

oOe

+12S Q C

I

Min

I

I

Unit

Min

-3.2
-3.2

mAde
mAde

-0.1

50
50

/lAde
/lAde

Max

+25 0 C

!:t.

10H

+750 C

Characteristic

0o
;j

Volts

10L

+125 0 C

Pin

"

TEST eURRENTIVOLTAGE VALUE
mA

0.8
0.8
0.8

4.5
4.5
4.5

;j

c

m

a.

5.25

TEST CURRENTNOl TAGE APPLIED TO PINS LISTED BELOW:

+7S o C

I Max I Min I Max I Min I Max 1 Unit

10L I

10H II;n I VIL I VIH I VF I VR I Vee I VeeL I VeeH I

Gnd

Input

Forward Current

IF

leakage Current

IR

Breakdown Voltage

Output
Output Voltage

Short Circuit Current

-0.1
-0.1

-3.2
-3.2
50
50

-0.1
-0.1

-3.2
-3.2

-

50
50

1

-0.1
-0.1

6.0
6.0

BVin

~
VOH

0.4
2.6
2.6

I-

0.4

2.8
2.8

0.4
2.6
2.6

-70

mAde

57

mAde

-0.1

-3.2
-3.2

-0.1
-0.1

50
50

-3.2
-3.2

50
50

6.0
6.0
0.4

Vde
Vde
Vde

-0.1

50
50

Vde
Vde

-20

Ise

-0.1

-3.2
-3.2

2.6
2.6

0.4
2.8
2.8

0.4
2.6
2.6

14

mAde
mAde

,.Ade

14
14

2.7
1.7

Vde
Vde

14
14

1.7

/lAde

Vde

14

1.2

14
14

Vde
Vde

-20

-70

mAde

57

I Max

mAde

Typ

2,7

14

2.3.7

Power Requirements
(Total Davk:el
Power Supply Drain

IpO

Switching Parameters

I

14
Typ

I

Max

14
Pulse In

11.6.7.8,13

Pulse Out

Turn-On Delay

tpd_

10

10

14

2.7

Turn·Off Delay

tpd+

10

10

14

2.7

MC8200/MC7200 series

QUAD EXCLUSIVE
"NOR"GATE
(Open Collector)

MC8242F, L*
MC7242F, L, P*

ADVANCE INFORMATION/NEWPRODUCT

This device contains four independent Exclusive NOR
gates with open collector outputs which may be used to
implement digital comparison functions. A four-bit comparison may be made by connecting the outputs together.

3

=". '2 + 1 • 2
Input Loading Factor

=

2

Output Loading Factor = 1 a
Total Power Dissipation = 170 mW typ/pkg
Vee = Pin 14 [4]
GND = Pin 7 [11]
Numbers at ends of terminals represent pin numbers

for devices in the dual in~line package.
Numbers,i" brackets represent pin numbers for devices
in the flat package.

SV)lITCHING TIME TEST CIRCUIT AND WAVEFORMS

TPin

TP out
Vee

~-3.0V

530
PULSE
GENERATOR

PRF = 1.0 MHz
PW""100ns
t+ = t- = 5.0 ns

84.2

)C>-'-'--+--'-+-......I--'lM,......-o 2.6

30 P

l

V

5k

5 kn and~ 30 pF include jig and scope .

• F suffix
L suffix
P suffix

= TO-S6 ceramic flat p.8ckag,e (Case 607).
= TO·116 ceramic duar in-line package (Case 632).
= TO-116 plastic dual in-I ina package (Case 605).

"'"~~ ;~F.Pd~OV
TPout~1.5V

.~

s:
(')

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

CO

gate. The other gates are"tested in the same
manner. Pin numbers indicated are for
devices in dual in-line packages only. To
test devices in the flat package, substitute

N

~

"TI

~

pin numbers shown in brackets on the logic

diagram on the first page of th is data sheet.

r

:=L>-3
:=L>-4

s:
.....
(')

~

:=J[>-10
12=J[>. 11

N
"TI

rnA

!

IOl

Temperature

-55°C

MC8242

MC7242

+25 0 C

25
25

+12SoC

25

OoC

25

+2SoC

25
25

+7SoC

lin

I VIL

- I
10

I

VIH

VF

VR

lIcc

0.8

2.0

0.4

5.0

0.8
0.8

2.0

0.4

4.5
45

2.0
2.0

0.4
0.4

45

5.0
5.0

2.0

0.4

2.0

0.4

4.5
45

0.8
10 I 0.8
0.8

Under ~~~~-4--~~~4---~~~

IOl

Unit

To"

I;n

I

Vil

I

VIH

Input
Forward Current

IF

Leakage Current
Breakdown Voltage

Output
Output Voltage

Leakage Current

IR

I

1
2

45

5.0

VCCL
4.75
4.75
4.75

VCCH

8:J

5.25
525

:j'
c

4.75

525
525

5.0

4.75

5.25

5.0

4.75

5.25

.-.
CD

0..

TEST CURRENTiVOlTAGE APPLIED TO PINS LISTED BELOW,

Pin

Symbol

~

Volts

@Test

Characteristic

r-

TEST CURRENTiVOlTAGE VALUE

13

-0.1 1 -3.21- 0 . 1
-3.2 -0.1
-0.1

-3.2
-3.2

-0.1
-0.1

-3.2
-3.2

50
50

50
50

-

50
50

-

-

-

-

-

-

0.4

OA
25

48

-1 1-

-

BVin

0.4

VOL

6.0
6.0

I -

I -

IOlK

I

VF

VR

I~I~I~I~
14

-3.2
-32

-0.1
-0.1

-3.2
-3.2

-0.1
-0.1

-3.2
-3.2

mAde

50
50

_.

50
50

-

50

/.lAde
J.lAdc

14

N

13

Vdc
Vdc

-

Vdc
Vdc

14
14

1)

Vdc
Vdc

-

0.4

-

-

25

J.lAdc

-

-

-

-

mAde -0.1
mAde -0.1
,u.Adc
f.LAdc

6.0
6.0

-

-

-

-

-

-

0.4

-

-

-

25

mAde

-

-

-

ns

-

-

-W18

48
Max

-

0.4

N

mAde

I

25 I

Vdc
Vdc

1.2

~Adc

V
V
14
14

~
~4

Power Requirements
(Total Device)
Power Supply Drain

IpO

141-1-1 -

Switching Parameters

Turn-On Delay

tpd-

Turn-Off Delay

tpd+

!#
18
3

I -

I -

I 18

I

M:x
-

ns

18

mAde

I 7

ns

I

7

INTEGRATED CIRCUITS

MC9300jMC8300 SERIES

MTTl

MC9300/MC8300 SERIES

COMPLEX FUNCTIONS
INTEGRATED CIRCUITS

INDEX
MC9300, MC8300
MC9301, MC8301
MC9304, MC8304
MC8308
MC9309, MC8309
MC9310, MC8310
MC8311
MC9312, MC8312
MC9316, MC8316
MC9328, MC8328
MC9601, MC8601

•

Universal 4-Bit Shift Register
BCD-to-Decimal Decoder
Dual Full Adder
Dual 4-Bit Latch
Dual 4-Channel Data Selector
Presettable Decade Counter
One-of-Sixteen Decoder
8-Channel Data Selector
Presettable 4-Bit Binary Counter
Dual 8-Bit Shift Register
Retriggerable Monostable Multivibrator

MC9300/MC8300 series

UNIVERSAL
4-BIT SHIFT REGISTER

MC9300L *
MC8300L,P*
This serial/parallel sh ift register consists of four fl ip-flops
operated in the synchronous mode. Functions available are
shift left, sh ift right, serial-to-serial, parallel-to-parallel, serial
to-parallel, and parallel-to-serial conversion.
This device operates on the positive-going edge of the
clock pulse in both the serial and parallel mode. The device
includes an internal clock buffer, input clamp diodes to reduce ringing, Q outputs for all four stages, Q output for the
last stage, synchronous parallel entry, and an asychronous
master reset. The J and R inputs are available, and may be
tied together to produce a D input.

Input Loading Factor
J, K, MR, OpO, Dpl. Dp2,Dp3 = 1
PE ~ 2.3
Clock = 4
Output Loading Factor = 6
Total Power Dissipation

=

300 mW typ/pkg

Propagation Delay Time

=

25 ns typ

4

6

5
Dpl

DpO

Dp3

Vee = PIN 16
GND= PIN 8

Clock 10

1203
1103

J 2

K

3

01

00

02
13

14

15

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTl families

MC9300
INPUT
LOADING

MC9300
OUTPUT
LOADING

FAMILY

FACTOR

FACTOR

FAMILY

MC9300
Me50D
IVlC2100
MC3100
MC4300
MC5400
MC930 ..

1.0
1.06
0.7
0.7
1.0
1.0
2 (6.0 k ohm pullup)
8 (2.0 k ohm pullup)

6
6.4
4.25
3.6
4.65
4.65
5.6

MC8300
MC400
MG2000
MC3000
MC4000
MC7400
MC830· •

Fan-Out
Fan-Out

=:
=

·"'Due to logic "1" state drive limitations of the MDTL family.

*L suffix
P suffix

=
=

16-pin dual in-line ceramic package (Case 620).
16-pin dual in-line plastic package (Case 612).

MC8300
INPUT
LOADING
FACTOR

Fan-Out

=

Fan-Out

=

1.0
1.0
0.6
0.7
1.0
1.0
2 (6.0 k ohm pullup)
B (2.D k ohm pullup)

MC8300
OUTPUT
LOADING

FACTOR
6
5.45
4.5
4.25
5.3
5.3
6.1

•

•

ELECTRICAL CHARACTERISTICS

s:

n
e.g

Test procedures are shown for only one

parallel data input. Other parallel data
inputs are tested in the same manner.

"PI: Dpl up3
J Opo °P2 QO
Ql

2

Further, test procedures are shown for only

~

one output. Complete testing according to
the Functional Test Diagram.

~

Clock

~
~
Q2 !2.0

_

Q3 ~

K

0.3

MR

Temperature IOL1

.!.!..o

r~

+250 C

MC9300

+1250 C

ODC
+25o C

MC8300

+7SoC
Pin

-55 0 C

Characteristic

Input
Forward Current -

Test

Min

Ma.

Min

Ma.

Min

Ma.

Unit

Min

Ma.

Min

Ma.

Min

IFl

1
2
3
4
9
10

-

-1.6

-

-1.6

-

-1.6

mAde

-

-1.6

-

-1.6

-

OPO

PE
Clock

MR
J

IF2

K
°PO

PE
Clock

MR
J

IR

-

-

-

-

~

-

~

-

-3.68
-6.4

-

-3.68
-6.4

-

-1.24

-

-1.24

1
2
3
4

-

9
10

-

-2.85
-4.95

1
2

-

60

~

-

140

-

240

-

-

-

-

-

~

~

-

-2.85
-4.95

-

60

-

-

~

I
~
I
~
I

-3.68
-6.4

-1.24 mAde

-

-2.85

-

-4.95

-

60

140
240

-

-

Vdc

~Adc

-3.68
-6.4

-

-1.41

-

-1.41

~

-

~

-

60

3

4

PE

9
10
1
2

-

3
4
9
10

-

12
12

0.4
0.4

-

0.4
0.4

-

0.4
0.4

Vdc
Vdc

-

-

11

2.4

-

2.4

-

2.4

-

-

-

-

75

-

-

MR

VD

J

K
OPO

PE
Clock

-

Output

Output Voltage

VOL
VOH

-

-

-

140
240
-1.5

j

~

-

K

~

-

OpO

-

~

-3.68
-6.4

-

Clock
Clamp Voltage

MC8300 Test Limits
+7SoC
+25o C

OOc

Symbol

J

-

MC9300 Test Limits
+12SoC
+2SoC

9.6
9.6
9.6
9.6
9.6
9.6

Max

10

IOL2 IOH
7.44
7.44
7.44
8.5
8.5
8.5

-0.36 -0.36 -10
-0.36 -0.36 -0.36 -10
-0.36 -

VIL

VIH

VF

VR

0.80
0.90
0.80

2.0
1.7

0.4
0.4
0.4
0.45

4.5
4.5
4.5
4.5
4.5
4.5

0.85
0.85
0.85

1.4
1.9
1.8
1.6

0.45
0.45

s:

Vcc VCCL VCCH
4.5
4.5

5.5
5.5

5.0

4.5
4.75
4.75

-

4.75

5.5
5.25
5.25
5.25

5.0

-

n

CO

w

o
o

nO
::J

~,

TEST CURRENT NOLTAGE APPLIED TO PINS LISTED BELOW:
Unit

lOLl

IOL2

IOH

-

-

-

10

Pulse
Vcc VCCL VCCH
I

VIL

VIH

VF

VR

-

-

-

-

1
9
9

-

1
2

-

::J

-

-3.24
-5.65

~

140
240

-

-

-

-3.24
-5.65

-

140
240

-

-1.5

60

~

-

-

-1.6 mAde

~

I
~
I
~
I

-3.68
-6.4

-

-1.41 mAde

-

-3.24
-5.65
60

-

-

-

0.45
0.45

-

0.45
0.45

-

Vdc

2.4

-

2.4

-

2.4

-

mAde

-

-

-

80

-

-

j

j

}.LAde

140
240

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

12

12

-

Vdc

-

-

11

-

mAde

-

-

-

-

Vdc

j

0.45 Vdc
0.45 Vdc

-

-

1
2
3

4
9
10

1
9
9

-

9
9

-

-

-

9
10

-

-

1
2
3
4

-

-

-

-

-

9
10

-

-

-

-

1
2
3

-

-

-

4

4

-

-

3
4

4,5,6,7,9
4,5,6,7,9

-

4,5,6,7,9

-

-

-

-

-

4
9

10

-

-

-

16

-

Gnd

CD

8

-

I I
I I
I I
1

-

-

-

-

16

-

-

-

-

8

1

-

-

16

16

-

-

-

8

-

-

-

-

-

-

-

16

1

16

-

1

8

16

-

1

8

-

-

-

16

-

-

-

j

-

8

j
8

Power Requirements
(Total Devic;e)

Power Supply Drain
Pulse 1:-,

c:

0.
MR

K

Leakage Current

~O

Volts

@Tost

J1

Under

~

TEST CURRENTNOLTAGE VALUE
mA

r.VIH

L-....J_ VIL
U100nsmin

IpD

.'6

-

1,8

I

MC9300, MC8300 (continued)

SWITCHING TIME TEST CIRCUIT

2.4V

DpO

2
10

TPin

PULSE
GENERATOR

3

Clock

R

Dp2 00 15
14
01
13
02
12
03
11
0.3

MR

t+ = t-S5.0 ns
(1.0 V to 2.0 V points)

PRF "" 2.0 MHz for all tests
except PW and f sr'

Three pulse generators are
required and must be slaved

together to provide the waveforms shown.

* *The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT-070-50 or equivalent.
CT = 15 P~ = total parasitic capacitance, which includes probe and wiring
capacitances.

SWITCHING TIME TEST PROCEDURES (T A = 25°C)
(Letters shown in test columns refer to waveforms.)

TEST

PIN
UNDER Pin 1 Pin 2
SYMBOL TEST MR
J

INPUT
Pin 3
Pins 4, 5, 6
K
DpO, Dpl, Dp2

Pin 7 Pin 9 Pin 10

PE

OUTPUT
Pin 12

VALUE
Min Typ Max Unit

Clock

03

Turn-Off Delay. Clock to 03

tpd+

10,12 2.4 V 2.4V

Gnd

2.4 V

2.4 V 2.4 V

A

B

-

18

35

Turn-On Delay, Clock to 03

tpd_

10,12 2.4 V 2.4 V

Gnd

2.4 V

2.4 V 2.4 V

A

B

-

25

45

ns

Gnd

2.4 V

2.4 V 2.4V

A

B

15

25

-

MHz

-

13

35

ns

Maximum Shift Rate

fsr

Minimum Clock Pulse Width

PW

12

2.4 V 2.4 V

Dp3

Tested during each of the above tests.

ns

Minimum Data InputSetupTime tsetup "1"
(Serial or Para'lIel Inputs)
tsetup "0"

7,12

F

2.4V

Gnd

2.4 V

C

Gnd

D

E

0..

TEST CURRENTIVOLTAGE APPLIED TO PINS LISTED BELOW,

Min

Min

C

TEST CURRENT /VOLTAGE VALUES
Volts
VIH
V, V. Vee VCCL VeeH V1HX
ID Vil

-

-

16

-

-

-

16

-

16

16

-

8

8

-

8
8

-

8

16

1

2,8,14

16

1

2,8,14

-

MC9301, MC8301 (continued)

INPUT and OUTPUT LOADING FACTORS
with
to MTTL and MDTL families

,_act

FAMILY
MC9300
MC500
MC2100
MC3100
MC4300
MC5400
MC930'

MC9301
INPUT
LOADING
FACTOR

MC9301
OUTPUT
LOADING
FACTOR

FAMILY

1.0
1.06
0.7
0.7
1.0
1.0

10
10.6
7.0
7.0
10
7.75
9.4

MCB300
MC400
MC2000
MC3000
MC4000
MC7400
MC830'

Fan-Out = 2 (6.0 k ohm pullup)
Fan-Out = 8 (2.0 k ohm pull up)

MC8301
INPUT
LOADING
FACTOR

MC8301
OUTPUT
LOADING
FACTOR

1.0
1.0
0.6
0.7
1.0
1.0
Fan-Out = 2 (6.0 k ohm pullup)
Fan-Out = 8 (2.0 k ohm pull up)

10
9.0
6.0
7.4
10
8.75
10.8

"'Due to logic "1" state drive limitations of the MDTL family.

SWITCHING TIME TEST CIRCUIT
2.4 V

Coax

Coax

950 ±.1.0%
~50

±.1.0%

A
50
B

PRF = 1.0 MHz Wp
PW = 100 ns
t+ "" t- ~ 15 ns
Amplitude

=

I

04

TP out

65
C

3.0 V
D

The coax delays from input to scope and output

to scope must be matched. The scope must be
terminated in 50-ohm impedance. The 950-ohm

resistor and the scope termination impedance
constitute a 20: r attenuatar probe. C08)C. shall
be CT -070-50 Or equivalent.

06
07
08
09

-=
CT"" 16 pF "" total parasitic capacitance, whlc"h
includes probe, wiring, and load capacitances,

VOLTAGE WAVEFORMS

t-

t+

1,...----3.0 V

''---------------------------------------~'4_--~-------OV

:========~==~t-----------------~--------------------+_----~~===SVOL
Gnd
tpd--+__----t

•

~f

MC9300/MC8300 series

'\

DUAL FULL ADDER

'-----------

MC9304L*
MC8304L,P*

This device consists of two independent, high·speed,
binary full adders, with complementary Sum outputs. Adder two has provisions for both active high and active low
inputs. Carry In and Carry Out of adder two are com pie·
mentary to those of adder one. These choices provide
greater design flexibility and minimum package count.

ADDER 1
INPUT

OUTPUT

Cin1

B1

Al

c;;;;t1

51

51

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
0
1
0
0
0

1
0
0
1
0
l'
1
0

0
1
1
0
1
0
0
1

~
Gnd "'" Pin

A12
B13
Cin1 4

~

H

H

8

751

FULL ADDER 1

651

5.C out 1

8215

•

Vee
L

A214
A2

FULL ADDER 2

~

1
L

B213
Cin2 12

Gnd

~

= Pin 16
= Pin 8

H

H

9

82

1052

11 Cout 2

ADDER 2
INPUT
I nput Loading Factors:
Adder 1: ~1, ~1, ~1 = 4
Adder 2: A2, B2, Cin2 = 4
A2, B2 = 1

Output Loading Factors:
Adder 1: ~1

=7

51 = 10
51 = 9
Adder 2: C out2 = 7
52 = 9
52 = 10

Total Power Dissipation

= 110 mW typ!pkg

TYPICAL PROPAGATION DELAY TIMES (ns)
TA = 25°C
tpdINPUT

tpd+

Cout

S

Cout

S

C in

8.0

-

8.0

-

Al

-

25

-

28

• L suffix = l6-pin dual In-line ceramic package (Case 620).
P suffix = l6-pln dual in-line plastic package (Case 612),

OUTPUT

Cin 2

B2

A2

B2

11.2

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
.1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Cout 2
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1

52

82

1
0
0
1
1
1
0
0
1
0
1
0
1
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0

0
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
1
1
1
1

3:

ELECTRICAL CHARACTERISTICS

(')

Test procedures are shown for only one
adder. The other adder is tested in the
same manner. Output tests are shown for

(0

W

o

.~

only one set of input conditions. To comADDER 1

plete testing. sequence through all input
combinations according to the appropriate
truth table.

2

Al

eo

5

3

Bl

S

7

3:

(')
CO

~

4~6
14
1

Co

13
15

mA
@Test
Temperature lOll IOL2 lou IDL4 101.5 IOL6 10til IOH2 IOH3

11

S

9

12

MC9304

10

I

-S5
+25°C
+125°C
0(

1+2S c
o

Pin IL-~..t~~~~~~5'ti--Cf.:~~~~~~~~---t

U~~~~+-~~+-~~+-~~4-~~4-~~

Forward Current

IF1

-6.4
-6.4
-1.6
-1.6

I

12

13
14
15

In

-6.4

1

-4.96

12
13

-4.96

I.

-1.24
-1.24
-4.96

I
12
13

240
240

15
Leakage Current

IR

'0

I'
15
Clamp Voltage

VD

60
240

I

I'13
I.
15

Output
Output Voltage

VOL

0.'

9

10
II
9

10
11
V OH

9

10
II

Power Requirements

(Total DeYK')
Power Supply Drain

I

~D

16

r

-6.4
-6.4
-1.6
-1.6
-6.4

-6.4
-6.4
-1.6
-1.6
-6.4

-4.96
-4.96
-1.24
-1.24
-4.96

-4.96
-4.96
-1.24
-1.24
-4.96

240
240
60
60
240

240
240
60

60
240

-6.4
-6.4
-1.6

-5.64
-1.41
-1.41
-5.64

-5.64
-5.64
-1.41
-1.41
-5.64

-5.64 mAd,
-5.64
-1.41
-1.41
-5.64

240
240
60
60
240

240
240
60
60
240

:ff I"A!d'

-5.64

-1.6
-6.4

-1.5

-1.5

I

I

0.'

Turn-Off Delay

-6.4

-1.6
-1.6
-6.4

50

12.4. 11.2

8.70

-1.2 -1.08 -0.84

-

0.85

2.0

0.40

4.5

5.0

4.5

5.5

-

11.2

8.70

-1.2

-1.08- -0.84

-10

0.85

1.7

0.40

4.5

5.0

4.5

5.5

3.4

12.4

11.2

8.70

-1.2

-1.08 -0.84

-

0.85

1.4

0.40

4.5

5.0

4.5

5.5

11.2

14.1

12.7

9.85

-1.2

-1.08 -0.84

-

0.8

1.9

0.45

4.5

5.0

4.75

5.25

11.2

14.1

12.7

9.85

-1.2

-1.08 -0.84

-10

0.9

1.8

0.45

4.5

5.0

4.75

5.251 2.4

I '/5

13

15

14/9

35

.0

13

15

tpd+ 1

I '/5

tpd1-2

14/9

.0

"

-

I

0.8

11.610.451

4.5

:i"

I

Yea. VeeH VIHX

12.4

101 , 11012110"110,,IIOL,lloL6110H' IloH2110>1.1 I.

V"

V'H

mAd,

!
!

c::
~

15.0 14.7515.25

1

V,

V,

I
12
13
14
15

12'3'4'12'13'14'15

12
13
14
15

1 1,2,3,4,13,14,15

Vee

I VCCL

l,2,3,4,12,H,IS
1,2,3,4,12,13,15
1,2,3,4,12,13,14

10

I

16

I

15

13
14
15

II

10
11
10

II

mAd,

I Pulse Out

14

I'

1,12,13,14,15
12,13,14,15
12,13,14
1,12,13,14,15
12,13,14,15
12,13,14
12,13,14,15
1,12,13,14,15
1,12,13,14,15

16
I

1,1:)

1

I
1,15

I

r
16

16

1,2,12

16

1,2,12

3,8,13,15

16

1,2,12
1,2,12

3,8,13,15
3,8,13,15

16

•

2,3,4,8,12,13,14,15
1,2,3,4,8,13,14,15
1,2,3,4,8,12,14,15
1,2,3,4,8,12,13,15
1,2,3,4,8,12,13,14

r

12

10

!

12
13

1

T

God

1,2,3,4,12,14,15
1,2,3,4,12,13,15
1,2,3,4,12,13,14

I'

240

I

VCCH Vmx
16

1,2,3,4,13,14,15

2,3,4,12,13,14,15

Pulse In
tpd_l
tpd_ 2

Vee

11.2

I 'j' I 'j' I 'j' II 'i' IT 'i' IOfTI'
: I vr
45

:J

VR

11.2

0.'

Switching Para~
Turn-On Delay

-6.4

VF

__.-__r--.~.-__r--.~n~~~cU~U~~~T/~V~~~T~AG~E~~~PL~lm~T~O~PI~~~LlS~T~ED~B~n~o:w~,____-;__-,__-;__~__~

Unit

-6.4
-6.4
-1.6
-1.6
-6.4

VIH

16.0 14.4

+7S0CI16.oI14.4111.2114.1112.719.851~1.21-1.081-o.841

Symbol 1 Tost

VIl

16.0 14.4

16.0 14.4

...

Volts
ID

16.0 14.4 11.2

00C 16.0 14.4

MC8304

Characteristic
Input

0o

mT CURRENT /VOLTAGE VALUES

ADDER 2

3,8,13,15

MC9304, MC8304 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Coax

950 ±'1.0%

~____~.~TPoutl

h,.,,-,,-------,L-+------- 3.0

V

TP out 1

ADDER 2

Coax

PRF"'2.0 MHz
t-

Gnd =="'=F=--'-'-~'--------+''====0.4 V

950 ± 1.0%

PW;:::::::250 ns (1.5 V points)

t+ =

~----~~TPout2

< 5.0 ns

TP out 2

2.4 V
VIHX

•

The coax delays from input to scope and output to scope must be matched. The scope
must be terminated in 50-ohm impedance.

The 950-ohm resistor and the scope ter-

mination impedance constitute a 20: 1 attenuatar probe.

Coax shaH be CT·070-50

or equ ivalent.

CT

=:

15 pF == total parasitic capacitance, which includes probe and wiring capacitances.

MC9304, MC8304 (continued)

TYPICAL HIGH-LEVEL "AND-OR-INVERT" GATE
r-------~--------~------------------._--_.----~--oVCC

4k

4k

1.5 k

4k

120

70

This full adder is constructed
using high and low level gates
interconnected as shown by
the logic diagram.

-

:t:Oiodes used only when inputs are connected to external points.

LOW-LEVEL INVERTER

HIGH-LEVEL INVERTER

r---------_.-QVCC

:j: Diode used only
when input is

connected to
external point.

fiGURE 1 - fUNCTION BLOCK DIAGRAM
ACTIVE HIGH INPUTS

ACTIVE LOW INPUTS
OR

ADOER 1

This diagram illustrates the adder function of
the MC9304/8304 using either active low or' high

ADDER 1

2

Al

Co

5

2

3

61

S

7

3

4

Cin1

S

6

4

5

6

inputs.
ADDER 2
11

12

11

13

13
15

14

9
10

15
12

9
10

MC9300/MC8300 series

"

\.----------'

DUAL 4-BIT LATCH

MC8308P*

2
3
4
6
8
10

.,

00

5

DO
01
01
02
02
03 MR 03

9

E

7

11

17

00

15
16
18
20
22

DO
01
02
03

01

19

02

21

03

23

MR

This device is constructed of AND, NAND, and NOR gates. Each
half of the device contains four latches with common enable (EO) and
E1) and common Master Reset (MR). Data entered at the D input of
each latch will appear at the' corresponding Q output if the enable inputs
are in the logic "0" state. When the enable inputs are in the logic "1"
state, each latch will maintain the information present when the enable
inputs were last in the logic "0" state. The master reset input overrides
aJI other input states. When a logic "0" is applied to the MR input, all
outputs of the quad latch will be forced to a logic "0".

INPUTS

MR EO E1

13

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

VCC = Pin 24
GND

I

= Pin 12

Input Loading Factors:
~O. 01, 02, 03 = 1.5
MR, EO, El = 1.0
Output Loading Factor = 9

Total Power Dissipation = 325 mW typ!pkg
Propagation Delay Time (Enable to Output)

a
= 25

ns typ

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

"'x

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

a
1
0
1

x

03
0
0
0
0
1
0
0
1
0
1
1
0
1
1
1
1
X
X
X

OUTPUTS

02 01
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1 .1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
X
X
X
X
X
X

x

x

x

DO Q3 Q2 Q1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
X
LATCHED
X
LATCHED
X
x o ~AoT~Hci'~

QO
0
1
0
0
0
1
1
1
0
0
0
1
1
1

a
1

0

X"" Don t Care

LOGIC DIAGRAM

1/2 OF DEVICE SHOWN

BIT #2

BIT #1

BIT #3

BIT #4

r - - -- - - - - - - - - - - - - - --..., r- - - -..., r - - - -..., r- - - --,
I

I

II

II
II
II
II

EO

L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
E:1

II

II

..J L ____
00

DO

• P suffix = 24-pin dual in-line plastic package (Case 649).

5

I I
II

"

3
4

II

II

II
II

2

II
:I

II
\.1

II

II
II
II

II
II

II

II
II
II

J L ____ J L ___ _

s:

ELECTRICAL· CHARACTERISTICS
Test procedures are shown for only one

(")

2
3
4
6
8
10

bit of one half of the device. The other

bits are tested in the same manner.

00
DO
Dl
D2
D3

00

5

CN
0

01

MR

02

9

03

11

00

("l

0

:l
.....
:l
C
C1l

14 ---c.fEO'J E
IO~

1 6 - DO
1 8 - Dl
2 0 - D2
2 2 - D3

0..

00~17
TEST CURRENTNOL TAGE VALUES

01 1-- 19
02 1--21
MR

03 1--23

Pin

lOLl

IOL2

IOH

VIL

VIH

OOC

12.7

14.4

12.7

14.4

1.9
1.8

0.45 4.5

+25 0 C
+75 0 C

12.7

14.4

-0.6 0.85
-0.6 -10 0.85
-0.6 0.85

1.6

0.45 4.5

Characteristic

MC8308 Test Limits
+2SoC
+75 0 C

DoC

Forward Current

Leakage Current

Clamp Voltage

Output
Output Voltage

,
,
, ,

Symbol

Test

Min

Max

Min

Max

Min

Max

Unit

IF

1
2
4

-

-1.6
-1.6
-2.7

-

-1.6
-1.6
-2.7

-

-1.6
-1.6
-2.7

mAde

-

1
2
4

-

-

60
60
90

-

-

-

/lAde

1
2
4

-

VOLl

5

-

0.45

VOL2
VOH

5
2.4

0.45
-

IR

VD

5

-

-

-

-

-

-

-

-1.5

2.4

-

-

Vde

-

-

0.45

-

0.45

Vde

0.45
-

-

0.45
-

Vde

2.4

ID

VF
0.45

VR
4.5

VCC

VCCL

VCCH

-

4.75

5.25

5.0
-

4.75

5.25

4.75

5.25

TEST CURRENTNOL TAGE APPLlEO TO PINS LISTED BELOW:
lOll

Input

Volts

@ Test
Temperature

13

Under

mA

-

Vde

,, ,
,,

IOL2

IOH

ID

VIL

VIH

VF

VR

VCC

VCCL

VCCH

Gnd

-

-

-

-

-

1
2
-

-

-

-

24

-

12
12
4,12

-

-

-

-

-

-

-

12

-

1
2
4

-

-

-

-

-

24

12

-

1
2
4
-

24

-

-

-

-

24

-

12
12

-

24

24
-

24

-

-

12

-

-

-

-

-

-

-

5

-

-

-

2,3,4

-

-

-

-

2,3,4

-

-

-

5
-

5

-

2,3

4

-

-

Power Requirements

-

-

-

12

VIL

(Total Device)
IpHD

24

-

-

-

117

-

-

mAde

Data Setup "1" Time

tSetup "1"

5

-

-

2.0

-

-

-

Data Hold "1" Time

tHold "1"

5

-

-

-

-

-

Turn·Off Delay
Data Setup "0" Time

tpd+

5

-

-

15
-

-

-

tSetup "0"

5

-

-

6.0

44
-

-

-

Data Hold "0" Time

tHold "0"

5

-

tpd-

5

8.0
-

n5
n5
n5
n5
n5
n5

Power Supply Drain

Switching Parameters

Turn-On Delay

-

-

-

30

-

-

-

-

-

-

2,3,4,6,8,10.14,
15,16,18,20,22

Pulse In

Pulse Out

2,4

5

-

24

-

-

3,12

2,4

5

-

24

-

-

3,12

2,4

5

-

24

-

-

3,12

2,4

5

-

24

-

2,4

5

2,4

5

- - - -_______11

3,12

24

-

24

3,12

-

-

3,12

,-_

MCB30B (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

Two pulse generators
are required and must

be slaved to provide
the waveforms shown.

EO

00

5

El
PULSE

GENERATOR
4
PRF = 1.0 MHz typ
t+ = t- = 10±.a.S ns
(10% to 90% points)
Amplitude = 3.0 V
PW = ns Pulse

30

X

47
44

Y
Z

50

DO

CT = 15 pF = total parasitic capacitance, which includes probe, wiring, and load

capacitances.
·The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT -070-50 or equ ivalent.

•

STORING A "1""

3.0 V

Pulse X - - - - - - - - . .

TPin

EO

OV
tHold "'"

3.0 V

Pulse Y

TPin

DO

TP out

'Pdf.
1.5

OV
~VOH

V
SVOL
GND

STORING A ""0""
PW

3.0V

Pulse X - - - - - - - " '
TPin

EO

OV
tHold "0"

3.0V

Pulse Z - - - - - - ,

TPin

DO

TP out

'Pdt;
1.5

OV
~VOH

V
SVOL
GND

MC9300/MC8300 series

DUAL 4-CHANNEL
DATA SELECTOR

MC9309L*
MC8309L,P*
This device consists of two four·channel data selectors

1/2 OF DEVICE SHOWN

with common control lines, constructed from higtrlevel AND·
OR-I NVERT gates with active pullup outputs. and low-level
inverters on the control inputs. By selecting one of four logic
combinations, information on One of the four data inputs will
be routed to the complementary outputs.

(Numbers and symbols in parenthesis are for other half of device)

Data selectors are useful in applications where digital data
is to be routed from one of several registers or locations to
another register or location for processing.
The MC9309/8309 may be cascaded to multiple levels so
that any number of lines can be multiplexed onto a single
output buss.
XO 12O------------rt++-~~

[YQI

Xl

[Yll

X2
[Y2]

X3

[Y3]

TYPICAL PROPAGATION DELAY TIMES (ns)
TA = 25°C

[4]

11o------------+++-i__--'

[2]

[5]

)0-..------<> 14

[WI

Z

INPUT

Z

Z

CONDITIONS

A

24

16

Xl

17

9

XO = X2 = X3 = logic "0", Xl =
logic "1". A and 8 are defined
by the logic equations.

10o------------+-+-i__--'
[6]

Vee

9O----------------l__../

~

GND~

[7]

PIN 16
PIN 8

LOW-LEVEL INVERTER
r---------~--oVee

2k

z ~ ABXO + ABXl + ABX2 + ABX3
Z ~ ABXO + ABXi + ABX2 + ABX3
W - ABYO + ABYl + ABY2 + ABY3
W~ ABYO + ABY1 + ABY2 + ABY3

I

Input Loading Factor"" 1

= 10
Z.W- 9

Output Loading Factor: Z. W

Total POWBr Dissipation = 150 mW typ/pkg

+Diode used only when input is
connected to external point.

HIGH·LEVEL "AND·OR·INVERT" GATE (Complementarv Outputs)

z

L---------------~z

:j: Diode used only when input is
connected to external, point .

.. L suffj-x = 16-pin dual in-line ceramic package (Case 6201P suffix = 16-pin dua' in-line plastic package (Case 612).

.-s:

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one input and one output. Test other inputs and
outputs in a similar manner according to

A

B

XO

Xl

X2

X3

Z

Z

VO

VI

V2

V3

W

W

0
0
1
1
0
0
1

0
0
0
0
1
1
1
1

0
1




0
1

0
1



0
1

0
1
0
1
0
1
0
1

~

0
1


















1
0
1
0
1
0
1






0
1

0
1
0
1
0
1
0
1




0
1








0
1













L-2q, ::::

13
3
12
11
10
9
4
5
6
7

-






o-

1...---






S
I

0
1
0
1
0

XO
XI
X2
X3
VO
VI
V2
V3

tC

nO

I nput level does not affect output.

....

::J

~

2!--14
W

Wi

TEST CURRENTNOLTAGE VALUES
2

Temperature

{

+2SoC

oOC
{ +250 C
+7SoC

Volts

mA

@Test

MC8309

lOll IOL2
12.4 11,2
12.4 11.2
12.4 11.2
14.1 12.7
14.1 12.7
14.1 12.7

IOL3
16,0
16.0
16.0
16.0
16.0
16.0

IOL4
14.4
14.4
14.4
14.4
14.4
14.4

10Hl
-1,2
-1.2
-1.2
-1.2
-1.2
-1.2

IOH2 10
-1,08 -1.08 -10
-1,08 -1,08
-1.08 -10
-1.08 -

VIL
0,80
0.90
0.80
0.85
0.85
0.85

VIH
2,0
1,7

1.4
1,9
1.8
1.6

VF VR Vcc VCCL VCCHIVIHX
4,5
5,5
0.4 4,5
4.5
0.4 4.5 5,0
5,5 I 2.4
4.5
5.5
0.4 4.5
4.75 5.25
0.45 4.5
0,45 4.5 5,0 4.75 5.25
2.4
4.75 5.25
0.45 4.5

-

1

MC8309 Test Limits
MC9309 Test Limits
TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
oOC
-5S0C
+2S0C
+2S0C
+125 0 C
+750 C
Under
VIH
VF/VR/ VCC/VCCL!VCCH/VIHXI
Test Min I Maxi Min I Maxi Min I Max I Min I Max I Min I Maxi Min I Maxi Unit I'OL1/ IOL2/ IOL3/ IOL4/ IOH1/10H2/ 10/ VIL

Gnd

Input

Clamp Voltage

Output
Output Voltage

IF
IR
'YO

-1.6
60

SO/-/60
-1.5
0.4
0.4
0.4
0.4

0.4
0.4
0.4
0.4

VOLI
VOL2
VOH

-1.6

-1.6

3
3
3

2.4
2.4

I-

2.4
2.4

-1.6
60

0.4
0.4
0.4
0.4
2.4
2.4

0.45
0.45
0.45
0.45
2.4
2.4

2.4
2.4

-1.6
60
-1.5

-1.6
60

0.45
0.45
0.45
0.45

0,45
0.45
0.45
0.45

3

$lAde

Vde

2.4
2.4

16

8

/ 16

8

mAde

31

I

Vde
Vde
Vde
Vde
Vde
Vdc

6,13
13
6,13
13
13
6,13

-

8

16

8
8

16
16

3
3,6
3
3,6
3,6
3

-1

16
16

16
16

8
8
8
8

Power Requirements
(Total Device)
Power Supply Drain

IPOH

Switching Parameters

I 16 I -

I -

I -

I 40 I -

I -

I-

I -

I -

I 43 I -

I -

I mAde

'pd'pd+

16

3,4,5,6,
7,9,10,
11,12,13
Pulse Out

Turn..()n Delay

Turn-Off Delay

CO
W

o

Zt-- 15

+l25oC

Leakage Current

(')

c

-550C

Forward Current

W

o

,tC

5'

A
B

MC9309

Symbol

OUTPUTS:

INPUTS

OUTPUTS

INPUTS

the truth table, Additionally, test all inputoutput combinations according to the truth
table,

Characteristic

(')
tC

TRUTH TABLE

15
15

I

16

16

8

11 13,8,9,10,12
11 13,8,9,10,12

MC9309, MC8309 (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

MC9309
INPUT
LOADING

MC9309
OUTPUT
LOADING FACTOR

MC8309
INPUT
LOADING

MC8309
OUTPUT
LOADING FACTOR

FAMILY

FACTOR

Z

Z

FAMILY

FACTOR

Z

Z

MC9300
MC500
MC2100
MC3100
MC4300
MC5400
MC930'

1.0
1.06
0.7
0.7
1.0
1.0
Fan-Out"" 2
(6.0 k ohm pull up)
Fan-Out == 8
(2.0 k ohm pullup)

10
10.6
7.0
7.0
10
7.75
9.4

9.0
9.5
6.3
6.3
9.0
7.0
8.4

MC8300
MC400
MC2000
MC3000
MC4000
MC7400
MC830'

1.0
1.0
0.6
0.7
1.0
1.0
Fan-Out = 2
(6.0 k ohm pullup)

10
9.0
6.0
7.4
10
8.75
10.8

9.0
8.1
5.4
6.6
9.0.
7.8
9.7

.

Fan-Out"" 8
(2.0 k ohm pullup)

Due to logic "1" state drive limitations of the MDTL family_

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

2.4 V

Coax·
13

A
B

Z

15

XO
Xl

2

14

X2

PULSE
GENERATOR

X3
YO

W

Yl

PRF - 1.0 MHz
PW - 200 ns

Y2

(1.5 V points)

iiii

2

Y3

~5.0 ns
(1.0 V to 2.0 V points)

t+ = t-

Zout ~50 ohms

• ·The coax delays from input to scope and output to scope must be matched. The scope
must be terminated in 50-ohm impedance. The 950-ohm resistor and the scope ter-

mination impedance constitute a 20: 1 attenuatar probe. Coax shall be CT -070-50
or equivalent.
CT"" 15 pF == total parasitic capacitance, which includes probe and wiring capacitances.

h=,---*+---3.0 V
GND=~+~~___---.jp::===0.4 V

TP out

GND======~----------~==

950±1.0%

•

MC9300/MC8300 series

PRESETTABLE
DECADE COUNTER

MC9310L *
MC8310L,P*

COUNT SEOUENCE TRUTH TABLE
OUTPUT
COUNT
0
1
2
3
4
5
6
1
8
9

03

02

01

00

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

The MG9310/8310 decade counter consists of four J-K master-slave
flip-flops plus additional gating to accomplish the counter function_
Parallel inputs are provided for presetting data and parallel outputs
for full counting flexibility_
An asynchronous master reset (M RI clears all flip-flops regard less of
other input states. Parallel information may be preset only while the
parallel enable (PEl is in the logic "0" state.
Inputs GEP and GET and output TG are useful in cascading counters. TG provides an output pulse each time the counter reaches its
maximum count.

Input Loading Factors:
MR. CIOf..= 1
Clock, PE, CET = 2

PO. Pl. P2. P3

Total Power Dissipation = 300 mW typ/pkg
Propagation Delay Time = 14 to 35 ns typ
Toggle Frequency = 28 MHz typ

= 2/3

Output Loading Factor"" 6

14
00

11

12

13
01

02

03

15 TC

4
Vee
GND

• L suffix = 16-pin dual in-line ceramic package (Case 620l.
P suffix = 16-pin dual in-line plastic package (Case 612),

P2

PI

PO

3

5

= Pin 16
= Pin 8

P3

6

ELECTRICAL CHARACTERISTICS

s:

Test procedu'res are shown' for, only one
input and one output. Test other inputs

(g

(")

CAl

......

and outputs in a similar manner according
to the truth table.

o

s:

(")
00,14

MR

2

00

CAl
......
o

e

3
PO
4
-Pl

01

..l

02 ~

P2

~ P3
7

-

9

03

eEP
PE

~ eET

-

Te

13

r!1---

{

~

MC9310

MC8310
MC9310 Test Limits

Characteristic

+25 0 C

Min

Test

Min

Max

Min

Max

IF

1
2
3

-

-1.6
-3.2
-1.07

-

-1.6
-3.2
-1.07

-

60
120
40

-

Max

Unit

Min

IOl2

10H

10

Vil

VIH

VR

VF

Vee

VeCl

-55 0 C

9.6

7.44

-0.36

0.80

2.0

0.4

4.5

-

4.5

5.5

9.6
9.6

7.44
7.44

-0.36 -10 0.90
-0.36 0.80

1.7

0.4

4.5
4,5

5.0

4.5
4.5

9.6
DoC
+25 O C 9.6

8.50

-0.36

-

0.85

1.9

0.45 4.5

-

5.5
5.5

4.75

5.25

8.50

-0.36 -10 0.85

0.45 4.5

5.0

+75 0 C

9.6

8.50

-0.36

1.8
1,6

0.45 4.5

-

4.75
4.75

5.25

Unit

1011

-

-

0.85

1.4

0.4

C

VCCH

+25 0 C

MC831 0 Test Limits

DoC

+125 0 C

Symbol

:::J

Temperature IOl1

+125 0 C

_55°C

:::J
....

Volts

@Test

{

Pin
Under

n-O

TEST eURRENT/vOl TAGE VALUES
rnA

(1)

D..

5.25

TEST CURRENT/VOl TAGE APPLIED TO PINS liSTED BELOW:

+7SoC

+25 0 C

Max

Min

Max

Min

-1.6
-3.2
-1.07

-

-1.6
-3.2
-1.07

-

Max

IOl2

10H

ID

Vil

VIH

VF

VR

-

-

-

-

1
2
3

-

-

-

VCC

VCCl

VCCH

Gnd

16
16
16

8
8
8

16
16
16

8
8
8

Input
Forward Current

Leakage Current

IR

Clamp Voltage

Output
Output Voltage

Switching Parameters
Turn-On Delay -- Q
Turn-Of! Delay - Q

-

60
120
40

-

-

VD

1

-

-

VOU

11

-

0040

11
11
11

-

0040

VOl2

0.40

-

0.40
0.40
0.40

11
11

2,4

2.4

-

2.4
2,4

75

-

VOH
Power Requirements
(Total Dev'ice)
Power Supply-Drain Current

1
2
3

-

204

0040

DAD
-

204

-1.5

-

-1.6 mAde
-3.2 mAde
-1.07 mAde

-

60
120
40

.uAde
,uAdc
,uAdc

-

-

Vdc

-

60
120
40

-

60
120
40

-

-

-1.5

-

-

-1.6 mAde
-3.2 mAde
-1.07 mAde

-

-

-

-

60
120
40

}.LAde
/.LAde
,uAde

-

-

-

Vdc

-

-

-

0.40

Vdc

-

0045

-

0045

Vdc

11

-

Vdc
Vdc
Vdc

-

0.45
0.45
0.45

-

0.45
0.45
0,45

-

0.45

0.40

0040
0040

0.45
0.45
0,45

Vdc
Vdc
Vdc

-

11
11
11

-

Vdc
Vdc

2.4
2.4

-

2.4
2.4

-

2.4
2.4

-

-

Vdc
Vdc

-

-

mAde

75

-

-

mAde

-

-

-

-

1

-

-

11
11

-

-

-

-

-

-

16

-

-

-

tpd_

2,14

-

-

-

30

2,14

-

-

35

2,15

-

-

-

40

ns

2,15

60

ns

Turn-On Delay

TC

tpd+
tpd_

Turn-Off Delay

TC

tpd+

-

-

ns
ns

-

-

-

-

-

1
2
3
-

16

-

8

-

16

8

See Timing Diagram@ t6

16
16
16

8
8
8

See Timing Diagram@t2
See Timing Diagram@t16

16
16

-

16

-

-

8

16

-

-

8

See Timing Diagram@ t4

-

-

See Timing Diagram@ t1

-

2,7
9,10

,.

-

8
8

-

40

-

-

ns

2

14

VIHX =3.0 Vdc
1,3,4,5,6,7,9,10

-

30

-

-

ns

2

14

1,3,4,5,6,7,9,10

16

70

ns

2

15

1,3.4,5,6,7,9,10

16

8

40

ns

2

15

1,3,4,5,6,7,9,10

16

8

Pulse In

Pulse Out

-

.. Apply after potentials have been applied to other pms.

-

-

See Timing Diagram@ t1

I

IpD

-

VR~Gnd ~50ns
(Holdl

•

8

MC9310, MC8310 (continued)

TIMING DIAGRAM

Pin
NQ.

Clock

2

fie

9

rYir1lrrL

y

VIH

CET 10

VIL

r- ~

.1
VIL
I

~

VIH

I

MR

PI

W-- ~ w-' --.r J

J J'J

VIH
JII,. ' - -

CEP

PO

r-,

VIL

3

VIHl

4

VI~

VIL

VI~

VIL

VIJ

;VILI

P2

5

P3

6

QO

14

Ql

13

Q2

12

Q3

11

TC

15

I

I
I
VIL

o r-1

JOH
hh
VOL

-

----,

J \
J 'F\

2

4

3

5

I

I

6

I

t- ~

8

7

I

I

I
I

I
to tl

t2

t3 t4 t5 t6 t7

t8 t9

tl0

tIl

t12

t13

t14

t15

t16

I-t17 t18

NOTES
1. The Clock pulse must be in the" high state during the high to

low transition of CET and CEP, and the low to high transition
of PE for correct logic operation.
2. Pin conditions reflected on timing diagram for tests at time
specified:

to: Parallel (P) inputs high, Parallel Enable
chronous Master Reset (MA) pulsed;
transition from high to low.

a

(PE) low, asynoutputs make

tl: Measure both VOLI and VOL20n OO,Ol,02,03and
TC before Clock goes high.
t2: Clock has been pulsed, 0 outputs are high; measure VOH.
t3: Clock is in high state while 'transitions of PE and CET
occur (necessary condition)'

Parallel entry is now in-

hibited, P inputs are at the low level.

t4: Count enable (CET) is at the low level (disabled), count
cannot occur; ,check Q outputs to see that they remain
at the low level.
t5: CET is set to a high level and CEP is set at the low level
while the Clock is high,
t6: Check 0 outputs to see that count is disabled, outputs
remain low.

t7: CEP is set high while Clock is high; count is now enabled.
t8: 'Clock is pulsed, count begins from 0000 to 0001.

t9
thru Check 0 and TC output states.
t17:
t18: Outputs go to low state, count begins (0000).

MC9310, MC8310 (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

VIHX
3.0 V

00

01

PULSE
GENERATOR

02

03
PRF
PW

= 10 MHz
=:

14

13

12

TP out

11

1/4 MC3000
or Equiv

50

typ

100 ns

TC

15

CTI

t+=t-~10ns

Amplitude

=:

3.0 V

CT

=

15 pF

=

total parasitic capacitance, which includes probe, wiring, and load

capacitances.
·The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20:1 attenuatar probe. Coax shall be
CT-070-50 or equivalent.

•

MC9300/MC8300 series
ONE-OF-5IXTEEN DECODER

MC8311P*

This device converts four BCD inputs to select one
of sixteen outputs. The selected output is in the logic
"0" state while all other outputs are in the logic" 1"
state. Two Enable inputs are provided for increased
logic capability. This device is useful in memory selection control and data routing applications.

ao
2

01

3

02

4

03

5

04

6

05

7

06

8

07

9

08
Input Loading Factor"" 1
Output Loading Factor = 10

1009
11010

..

Total Power Dissipation"" 175 mW typ/pkg

13011

Propagation Delay Time

Ei1'8i:'i1e to

Output"" 26 ns max

14012
15013
16014

!

17 015

Vee = Pin 24
GND=Pin 12

INPUT
EO
1
1
0
0
0
0
0
0
0
0
0
0
0
0

a
a
0

0
0

x ""

E1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

OUTPUT

D

C

B

A

X
X
X

X
X
X

X
X
X

X
X
X

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1

0

0
1
0
1
0
1
0
1
0
1

1

1
0
0
0
0
1
1
1
1

0
1
1
0
0
1
1
0

0
1
1
0
0
1
1

0
1
0
1

0
1

15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0

14
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1

Don't care

.,p suffix::: 24-pin duaJ in-line plastic package (Case 649).

13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1

12
1
1
1
1
1
1
1

1
1
"I
1
1
1
1
1

0
1
1
1

11
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
1

10
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1

9

a

7

6

1
1
1
1
1
1
1
1
1
1
1
1
0
1

1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

1
1

1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

1

1
1
1
1

1

1
1
1
1
1
1
1

a
1
1
1
1
1
1
1
1

5
1
1
1
1
1
1
1
1
0
1
1
1
1

1
1
1
1
1
1

4

3

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1

1
0
1
1
1
1
1
1
1
1
1
1
1
1

2
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

s:

ELECTRICAL CHARACTERISTICS

n

Test procedures are shown for only ~ne input and
one output.

00

....w....

Test other inputs and outputs in a

similar manner according to the truth table. Addi·
tionally. test all input·output combinations accord·
ing to the truth table.
18

00

8::I

01

:;'

...
c:

02

19

~

03 L4

23 'A
11
010 p-'-'-

..E.e

011
012

Leakage Current

Test

Min

Max

Min

Max

Min

'IFl

18
20

-

-1.6
-1.6

-1,6
-1.6

18
20

-

-

-

18

-

20

-

18
20

-

VOU

1

-

VOL2
VOH

1
1

2.4

-

IpO

24

-

-

IR

Vo

IOL1

IOL2

DOC

14.1

16

-0.6

+25 0 C
+750 C

14.1

16

-0.6

14.1

16

-0.6

Unit

lOLl

IOL2

IOH

10

VIL

VIH

VF

VR

VCC

VCCL

VCCH

Gnd

-

-

-

-

-

-

18
20

-

24
24

12
12

-

18
20

-

-

-

-

-

-1.41
-1.41

-

-1.41
-1.41

24
24

-

12
12

60
60

-

60

-

-

c1.5
-1.5

0.45
0.45

-

60

-

-

18
20

-

-

18
20

-

-

-

18,19,20,21,22,23

Max

VF

VR

VIL

VIH

0.85

1.9

0.45 4.5

-10

0.85

1.8

0.45 4.5

5.0

4.75

5.25

-

0.85

1.6

0.45 4.5

-

4.75

5.25

VCC

VCCL

VCCH

4.75

5.25

TEST CUR RENT /VOLTAGE APPLIED TO PINS LISTED BELOW:

+75 o C

Symbol

IF2

Temperature

p.'2-

+25 o C

OOC

10

IOH

MC831t Test Limits

Pin

Under

Clamp Voltage

015

Volts

@Test

013

2!!.o

Input
Forward Current

TEST CURRENTIVOLTAGE VALUES
mA

~

~
014 ~

2!..c

Characteristic

~

-1,6 mAde
-1,6 mAde
-1.41 mAde
-1.41 mAde

-

-

-

-

-

60
60

,uAdc

-

-

Vdc
Vdc

-

0.45

Vdc

1

-

0.45

0.45

Vdc

-

1

2.4

-

2,4

-

Vdc

-

-

1

-

-

60

-

-

mAde

-

Pulsa

-

-

Pulse
In

Out

ns

19

4

ns
ns
ns

19

4

23

4

23

4

,uAdc

-

-

-

-

-

24
24

12
12

24
24

-

12
12

-

-

24

-

-

-

-

-

-

-

-

18,19,20,21,22,23

-

18,20,21,22,23

19

-

-

-

-

Output

Output Voltage

0.45

-

12

24

12

24

-

12

24

-

-

12

24

-

-

12,18,20,21

24

-

-

12,18,19,20,21

-

Power Requirements
(Total Device)
Power Supply Drain

SWitching Parameters

E

tpel-

19,4

-

-

Turn-Off Oelay - E

'pd+

19,4

-

A

'pd-

23,4

-

-

T urn-Off Delay - A

tpd+

23,4

- --

Turn-On Delay Turn-On Delay

-

-

31

-

35

-

40

26

-

-

-

VIHX = 2.4 Vdc

-

-

•

22,23

-

22

-

22

-

22,23

-

-

24
24

12,18,20,21
12,18~

MC8311 (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

Coax·

Coax·

950±. 1.0%

950 ±. 1.0%

TP out
PULSE

23 A

GENERATOR

<>+__..:2;::2-1B

..

PRF ~ 1.0MHztyp
PW= lOOns

r

r-oO-',-_...;2::.1'-1C

50

t+=t-~10ns

(10% to 90% points)
Ampl itude = 3.0 V

+--<>",,--_..:2:.;:°-10
L.. _ _ _ _ _ _ _ _ _ _ _ _ .J

I

CT - 15 pF :: total parasitic capacitance, which includes probe, wiring, and load

capacitances.
·The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be
CT -070-50 or equ iva lent.

-

~

90%
10%

y~P:+

TP out

:==============~,

TPin
E

TPout

'\

~+

------3.0· V
1.5 V
+--------0 V

ftPd-

_________~-::::::::::::

V CC

X4
X5

6

X6

7o--------~r-tt±±=f~

X7

9~--------_r-r_t~r-,

Z

LOW·LEVEL INVERTER
,-------------"t---O V CC

Z = Eo(ABCXO + ABCX1 + ABCX2 + ABCX3 +
ABCX4 + Al!CX5 + ABCX6 + ABCX7)

Z=

4k

E o(ABCi«l + ABCiO + ABCX2 + ABCi<:} +
ABCX4 + ABCX5 + ABCX6 + ABCX7)

Input Loading Factor

=1

Output Loading Factor:
High: Z = 20. Z = 1B
Low: Z=10.Z= 9

Propagation Delay Time = 24 ns typ
Power Dissipation == 135 mW typ/pkg

~ Diode used only when input is
connected to external point.

HIGH·LEVEL "AND·OR·INVERT" GATE (Complementary Outputs)
--~--------------------~~----~~~--4r----~--4r-oVCC

4k

Z

L---------------~z

+Oiod~s used only when· inputs are

connected to external points .

• L sufftx::: 16~pin·dual in-line ceramic package (Case 620)_
P suffix = 16-pin dual in-line plastic package (Case 612).

•

.ELECTRICAL CHARACTERISTICS

s:
(')
CC
W
....
~N
s:
(')

TRUTH TABLE

Test procedures are shown for only one
input and one output. Test other inputs
and outputs in a similar manner according

to the truth table. Additionally, test all
input-output combinations according to
the truth table.

10

.0.......
E

A
B
C

Z

XO
Xl
X2
3

115

E

C

B

A

XO

Xl

X2

X3

X4

X5

X6

X7

Z

Z

1
0
0
a
a
a
a
0
a
a
a
a
0
a
0
0
a









0
0
a
a
a
a
a
0

0
0
a
a
1
1
1
1

0
a
1
1

0
1








a
1





































a
0
1
1











0
1










0
1
















1

a
a
0
a
1
1
1
1

0
0
1
1
a
a
1
1






















a
1






































0
1

CO

....NW

nO
::J

!:!".
::J
t:

a
1
a
1

[

tP = Input level does not atfect output.

J4

4

TEST CURRENT!VOL TAGE VALUES

mA

Volts

"Test
Temperature IOL1 IOL2 'OL3 IOL4 IOHl IOH2 10

{
MC9312

MC8312

Characteristic
Input
Forward Current

leakage Current
Clamp Voltage

I

+25OC
Min Max

1 -1.61 _

'Fl
'F2

-1.24

I

I

+125 o C
Min Max

-1.6

-1.6

-1.24

-1.24

60
-1.5

60

A.•

A.'
0.4
0.4
0.4

'R

Vo

+25o C
+12SoC

14.4

12.4

12.4
12.4
OOc 12.7 14.1
+25o C 12.7 14.1
+15 0 C 12.7 14.1

ODC
1 +25OC
Min
Max Min Max
-1.6

-

I

-

-1.41

-1.2 -1.08 -10
-1.2 -'1.08 -1.2 -1.08 -1.2 -1.08 -10
-1.2 -1.08 -

11.2

14.4

16.0

14.4

16.0

14.4

16.0

14.4

16.0

14.4

16.0

-1.6

VOL1
VOL2

VaH

14
15
14
15
14
15

Power Requirements
(Total Device)
Power Supply Drain

IpDH

16

0.4
0.4
0.4

A.'
0.4

A.'
2.41
2.'

-

A.'
2.4
2.4

2.4
2.4

60

0.45

0.45

0.45

0.45
0.45

0.45
0.45

0.45

0.45

0.45

0.45

~-=-_1

40 1 -

2.4

2.4
2.'

1 '0 1 -

Turn-Off Delay

'pd'pd+

11/15

36
341

I

I

I

36
34

0.85
0.85

V,L

0.45

I

I

5.25

5.25
5.25

VIH VF VR VCC VCCL VCCHI

16

2.4

Vde
Vde
Vde
Vde
Vde
Vde

I n,

VIHX

Gnd

8,10,11.12,13
8.10,11,12,13

16
16

Vde

2.'
2.4

I

0.85

/lAde

-

15

"

15
15
15
14

1-

I

11
11

1 -

-

-

10,11.12.13

14
14

-

1.10.11.12.13

-

1.10,11.12.13

-

10,11,12,13

15

1-

1.10.11.12.13

8
8

16
16

10.11.12.13

14
15

14

1 43 1 - 1 43 1 - 1 43 1mAde 1 -

I

2.4

0.80

16

Pulse In

11/15

5.5
5.5
5.5

VCC VCCL
4.5
5.0
4.5
5.0
4.5
5.0
1.9 0.45 5.0 4.75
4.75
1.8 0.45 4.5 5.0
1.60.45 4.5 5.0 4.15

mAde

Switching Parameters
Tum-On Delay

VIHX

2.0 0.4 1.7 0.4 4.5
1.4 0.4 4.5

-1.41 mAde

-1.41

60
-1.5

2.'

VCCH

0.80
0.90

'D

IOL1 IOL2 IOL3 IOL4 IOH1 IOH2

Unit

Output

Output Voltage

V,H VF VR

TEST CURRENTNOLTAGE APPLIED TO PINS LISTED BELOW:

+75OC
Max

Min

-1.6

-1.2 -1.08

16.0

11.2

MC8312 Test limits

MC9312 Test limits

Pin

-550 C
Under
Symbol I Te.. Min Mex

{

-550 C 11.2

V,L

-

-1

-

16
16

1 -

1 -

1- 1

16

I

I

I

16
16

8

'6
16

Pulse Out

I
I

15
15

I

2,3,4,5,6,7.91 1,8,10,12,13
2.3,4,5.6.7,91 1,8,10,12.13

MC9312, MC8312 (continued)

INPUT and OUTPUT LOADING FACTORS
with respect to MTTL and MDTL families

MC9312
INPUT
LOADING
FAMILY
MC9300
MC500
MC2100
MC3100
MC4300
MC5400
Me930·

FACTOR
1.0
1.06
0.7
0.7
1.0
1.0
Fan-Out = 2

MC8312
OUTPUT
LOADING FACTOR

MC8312
INPUT
LOADING

MC9312
OUTPUT
LOADING FACTOR

Z

Z

FAMILY

10
10.6
7.0
7.0
10
7.75
9.4

9.0
9.5

MC8300
MC400
MC2000
MC3000
MC4000
MC7400
MC830'

6.3

6.3
9.0
7.0
8.4

FACTOR
1.0
1.0
0.6
0.7
1.0
1.0
Fan-Out = 2

(6.0 k ohm pullup)

(6.0 k ohm pulfup)

Fan-Out = 8
(2.0 k ohm pullup)

Fan-Out:;:: 8
(2.0 k ohm pullup)

Z

Z

10
9.0
6.0
7.4
10
8.75
10.8

9.0
8.1
5.4
6.6
9.0
7.B
9.7

.. Due to logic "'" state drive limitations of the MOTL family.

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

10
11

A

8

Coax"

E

z

15

Z

14

C
XO
X1
PULSE

X2

GENERATOR

X3
X4

PAF:::: 1.0 MHz

PW

X5

= 200 ns

X6

(1.5 V points)

t+ ==

X7

t- S:5.0 ns
(1.0 V to 2.0 V points)

2.4 V

.. ·The coax delays from input to scope and output to scope must be matched. The scope
must be terminated in 50-ohm impedance. The 950-ohm resistor and the scope ter-

mination impedance constitute a 20: 1 attenuatar probe. Coax shall be CT-070-50

or equivalent.
CT

= 15

.

.

.

pF'''''-total parasitic capacitance,. which includes probe and wiring cap!-Icitances.

h""":-;---->.-+---3.0 V
GND=::::"+=~~-----l~===0.4 V

TP out

GND=====~------~~

I

MC9300/MC8300 series

PRESETTABLE
4-BIT BINARY COUNTER

MC9316L*
MC8316L,P*

COUNT SEQUENCE TRUTH TABLE
OUTPUT
COUNT 03 02 01 00
0

0
0
0
0

0
0
0
0

0

1
2
3
4

0
0
0
0

1
1
1
1

0
0
1
1

0

10
11

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

12
13
14
15

1
1
1
1

1
1
1
1

.0

0

0
1
1

0

5
6
7

8
9

0
1
0
1

0
1
1

The MC9316/8316 hexadecimal counter consists of four J-K masterslave flip-flops plus additional gating to accomplish the counter function.
Parallel inputs are provided for presetting data and parallel outputs for
full counting flexibility.
An asynchronous master reset (MRl clears all flip-flops regardless of
other input states. Parallel information may be preset only while the
parallel enable (PEl is in the logic "0" state.
Inputs CEP and CET and output TC are useful in cascading counters.
TC provides an output pu lse each time the counter reaches its maximum count.

1
0
1

1
1
Total Power Dissipation = 300 mW typ/pkg
Propagation Delay Time = 14 to 35 ns typ
Toggle Frequency == 28 MHz typ

Input Loading Factors:
MR. CI;E.= 1
Clock, PE, CET = 2
PO, P1, P2, P3 = 2/3

•

Output Load ing Factor

=6

14
QO

13
Q1

12

11
Q2

Q3

MR

Clock

2

CEP

7

i'E

9
15 TC

CET 10
P1

PO
3

5

VCC= Pin 16

GND

*L suffix = 16~pin dual in-line ceramic package (Case 620).
P suffix = l6-pin dual in-line plastic package (Case 612).

P3

P2

4

= Pin

8

6

s:
CO
W
....
s:
00
....

ELECTRICAL CHARACTERISTICS

(")

Test procedures are shown for only one

input and one output. Test other inputs
and outputs in a similar manner according
to the truth table.

•0)
14

QO

MR

(")

-

Co.)

Clock

-

Ql,13

3,PO
4
Pl

------2

0)
Q2 ~

P2

~ P3

----..2
~

Temperature lOLl

PE

~ CET

TC

{

~

MC8316
MC9316 Test Limits

Pin

Characteristic
tnput
Forward Current

Leakage Current

Test

Min

Max

Min

Max

Min

IF

1
2
3

-

-1.6
-3.2
-1.07

-

-1.6
-3.2
-1.07

-

1
2
3

-

-

60
120
40

VD

1

-

VOLl

11

VOL2

Power Requirements
(Total Device)
Power Supply Drain Current
Switching Parameters
Turn-On Delay ~ Q

-

-Max

Unit

-1.6 mAde
-3.2 mAde
-1,07 mAde

Max

Min

Max

-

-1.6
-3.2
-1.07

-

-1.6
-3.2
-1.07

-

-

-

2,14

Turn-On Delay

TC

tpd_

2,15

40

ns

Turn-Off Delay

TC

tpd+

2,15

60

ns

ns

-

-

1
2
3

-

See Timing Diagram@ 11

See Timing Diagram@ 14

-

35

-

tpd+

Q

-

-

ns

Turn-Off Delay

-

-

-

-

-

11
11

-

-

2,14

VR

-

30

-

tpd_

VF

Vdc
Vdc

-

-

VIH

-

mAde

75

16

Vil

2.4
2.4

-

-

IPD

10

-

-

-

-

0.85

IOH

11
11
11

2.4
2.4

2.4
2.4

-

1.4

IOl2

-

-

11
11

-

lOll

Vdc
Vdc
Vdc

2.4
2.4

2.4
2.4

VOH

Unit

0.45
0.45
0.45

Vdc
Vdc

-

-

5.25

0.45 4.5

-0.36

-

-

-

2.4
2.4

0.40
0.40
0.40

4.75
4.75

1.6

8.50

-

0.45
0.45
0.45

0.40
0.40
0.40

-

5.25

5.0
5.0

0.45 4.5

-

-

-

11
11
11

4.75

1.8

-

-

0.40
0.40
0.40

0.40

4.5

5.0

8.50 -0.36 -10 0.85

11

0.45
0.45
0.45

Vdc

-

5.0

0.4

1.9

8.50 -0.36

Vdc

Vdc
Vdc
Vdc

0.40

0.40

4.5

0.45 4.5

0.85

7.44

0.45

0.45

-

-

:::l
~,
:::l

1

-

-

-

Gnd

-

-

16
16
16

8
8
8

-

16
16
16

8
8
8

-

-

1
2
3

-

-

16

8

-

16

8

16
16
16

-

See Timing Diagram @ 19
See Timing Diagram@ 110

8
8
8

See Timing Diagram @ t2
See Timing Diagram @ t16

16
16

-

16

-

-

-

-

8

-

8

-

-

-

2,7
l'
9,10
VIHX = 3.0 Vdc

-

mAde

Pulse In

opulseOut

-

-

-

30

-

-

ns

2

14

1,3,4,5,6,7 ,9, 10

16

ns

2

14

1,3,4,5,6,7 ,9, 10

16

ns

2

15

1,3,4,5,6,7,9,10

16

-

-

ns

2

15

1,3,4,5,6,7,9,10

16

VR~Gnd ~50ns
IHoldl

•

-

-

-

-

40

5.25

VCCH

75

60

CD

c.

VCCl

-

35

c:

VCC

-

-

VCCH

TEST CURRENTNOl TAGE APPLIED TO PINS LISTED BELOW:

-1.6 mAde
-3.2 mAde
-1.07 mAde

60

5.5
5.5
5.5

1.7

-

-

Vdc

-1.5

60
120
40

-

4.5
4.5

2.0

0.90
0.80

Vdc

0.45

,uAdc

-

-

60
120
40

5.0
5,0

0.80

-0.36

-0.36 -10
-0,36 -

-

-

-

-

J,lAdc

4.5
4.5

-

7.44
7.44

,uAdc
/-lAde
,uAde

-1.5

/.lAde

-

0.4
0.4

VIH

120
40

-

60
120
40

-

-

Max

VCCL

VIL

-

-

60
120
40

-

Min

-

-

.. Apply after potentials have been applied to other pi'ns.

Min

Vcc

10

9,6

9.6
OoC
+25 o C 9.6
+7SoC 9.6

VR

VF

IOH

IOL2

9.6
9.6

MC8316 Test Limits
+1SoC
+2SoC

OoC

+12SoC

Symbol

IR

Clamp Voltage
Output
Output Voltage

+2SoC

-55°C

~50C

+25 o C
+12SoC

MC9316

{

Under

Volts

mA
@Test

Q3 ~

CEP

nO

TEST CURRENTNOLTAGE VALUES

8
8

8

8
8

MC9316, MC8316 (continued)

TIMING DIAGRAM

Pin

No.

1!WiLJ1...r-LrJLrJ ' JW-Lr Jf-rlJ~ J~~ r-h-

2J

Clock

PE

9

VIH

CET 10
CEP

VIL

.1.
VIL
I

PFJ

VIH
1L f---'

7

VIH

1 ---,

MR

VIL

PO

I

VIH

3

VIL
P1

VIJ

4

I

VIL
P2

VIJ

5

I

VIL

..

P3

i

VIJ

6

~tr°H
VOL
13V- 11
12V- 11
11V- h

00 1 4 01
02
03

TC

I

VIL
0

~1

2

4

3

I

5

6

I

7

I

B

I

I

I

10

9

12

11

I

13

-

I

I

I

1'5 0

14

-

I

-

J

-

I

15

to

t1

t2

t3 t4 t5 t6 t7

t8 t9

t10

t'11

t12

t13

t14

t15

t16

t17

t18

t19

t20

t21

t22

loV!.!!"ansition of CET and CEP, and the low to"high transition
of PE for correct logic operation.

·2. Pin conditio.ns reflected on timing diagram for tests at time
specified:
to: Paraliel (PI inputs high, Paraliel Enable (PE) low, asyn·
chronous Master Reset (MR) pulsed; 0 outputs make
transition from high to low.
tl : Measure both VOLl and VOL2 on QO, 01,02, 03 and
TC before Clock goes high.
t2: Clock has been pulsed, 0 outputs are high; measure VOH.
t3: Clock is in high state while transitions of PE and CET
occur (necessary condition). Parallel entry is now in-

hibited, P inputs are at the low level.

t4: Count enable (CET) is at the low level (disabled), count
cannot occur; check

a

outputs to see that they remain

at the low level.

t5: CET is set to a high level and CEP is set at the low level
while the Clock is high.

t6: Check Q outputs to see that count is disabled, outputs
remain low.

t7: CEP is set high while Clock is high; count is now enabled.
t8: Clock is pulsed, count begins from 0000 to 0001.
t9
thru Check 0 and TC output states.
t23:
t24: Outputs go to lowstate, count begins (0000).

-

t23 t24

NOTES
1. The Clock pulse must be in the high state during the high to

-

MC9316, MC8316 (continued)

SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

VIHX
3.0 V

00

01

02

PULSE

14

13

12

TPout

GENERATOR
03
PRF
PW

= 10 MHz typ

50

= 100 ns

TC

11

1/4 MC3000
or Equiv

15

CTI

t+ = t - :S:10 ns
Amplitude = 3.0 V

•

C-r = 15 pF = total parasitic capacitance, which includes probe, wiring, and load
capacitances.
*The cOax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 950-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuatar probe. Coax sha'lI be
CT-070-50 or equivalent.

3.0 V
TPin
Clock

OV

TP out
Q

TP out

TC

~VOH

SVOL
GND
2VOH
SVOL
GND

MC9300/MC8300 series
DUAL 8-BIT SHIFT REGISTER

MC9328L *
MC8328L,P*
The MC9328/8328 is a monolithic dual 8-bit serial shift register.
Each 8-bit register is provided with a 2-input multiplexer circuit and
complementary serial outputs. The two registers can be clocked together
with a common line, or clocked separately with separate lines. A common
Master Reset input is active in the low level and overrides all other inputs.

Input Loading Factors:
MR, ~O, 01 = 1

Os

=

2

Clock - Pins 7,10= 1.5
Pin 9 "" 3
Output Loading Factor"" 6
Total Power Dissipation = 250 mW typ/pkg
Propagation Delay Time = :
Clock to Output, tpd_ = 22 ns typ
tpd+ = 13 ns typ
MR to Output, tpd_ or tpd+ = 35 ns typ

Vee = Pin 16
GND = Pin 8

12

14 Q

Os 13
DO 11

15 Q

01

Clock

fO~

01

5

Os
DO

4
6

3

Q

2

a

MR

TIMING DIAGRAM

Pin

No.

7,10
Clock

{

~----------------------------------------------_+---VIL

9

---+--VIH
t---I--VIL

--------'
Os

4

Os

13

DO

6

DO

11

01

5

01

12

Q

14
X

=

:!i:VOH
';;VOL

May be high or low.

a

15

x

:!i:VOH
';;VOL

Q

3

x

:!i:VOH'
';;VOL
2: VOH
';;VOL

a
2

L

x
Precondition Cycle

• L suffix::: l6-pin dual in-line ceramic package (Case 620).
P suffix = l6-pin du'al in-line plastic package (Case 612).

t1

t2

t3

t4

t5

t6

t7

t8

t9

:s:

ELECTRICAL CHARACTERISTICS

(')

~

Test procedures are shown for only one input and one output of one half of the

device.

Co.)

To complete testing, sequence

through other inputs and outputs in the

I

MR

same manner

9

C

Q

N
~t:JJ

3

:s:

C
4

6

DS
DO

5

Dl

(')

t:JJ

Co.)

5

N
t:JJ

2

0o

10
13
11
12

~

~R

Qt---14

mA
@Test
Temperature

C

DS
DO
. Dl

MC9328

-55°e
{. +25 oe
+l25 o C

5f--15

OoC
{

MC8328.

+25 o e

+75°C

Characteristic

Leakage Current

Clamp Voltage

Under

Symbol

Test

'F

j

IR

4
7
9
1
4
7
9

Vo

:i"

c

CD

lOLl

IOL2

7.44
7.44
7A4

9.6
9.6
9.6
9.6
9.6
9.6

8.5
8.5
8.5

VIL

VIH

VF

VR

Vee

VceL

VeeH

-0.36
0.80
-0.36 -10 0.90
-0.36
0.80
-0.36
0.85
-0.36 -10 0.85
-0.36 0.85

2.0
1.7
lA
1.9
1.8
1.6

0.4
0.4
0.4
OA5
0.45
0.45

4.5
4.5
4.5
4.5
4.5
4.5

-

4.5
4.5
4.5
4.75
4.75
4.75

5.5
5.5
5.5
5.25
5.25
5.25

IOH

10

-

-

-

5.0

5.0

-

a.

-rEST eURRENT/vOL TAGE API 'LIED TO PINS LISTED BELOW:

·Pin

Input
Forward Current

....:::J

TEST eURRENT/VOLTAGE VALUES
Volts

1--=-<-'=-+-=-;:--"---+-...,.---,-1.6
-3.2
-2.4
-4.8
60
120
90

180

-

-

-

-

-1.6
-3.2
-2.4
-4.8
60
120
90
180
-1.5

-

Min I Max I Min I Max

-1.6 mAde
-3.2
-2A
-4.8
60 jJAdG
120
90
180
Vdc
-

~

+

-

-

-

-1.6
-3.2
-2.4
-4.8
60
120
90
180

-

-

-

-

-

-

-1.6
-3.2

-2.4
-4.8
60
120
90
180
-1.5

-

-

-

Unit

lOLl

IOL21 IOH 110

-1.6 mAde
-3.2
-2.4
-4.8

60

-

-

120
90
180

-

-

~

I

VIL

I VIH I VF I VR I Vee I VeCL I
41
97

1-_

1
4
7
9

jJ.Adc

+

-

Vdc

-

-

-

-

-

-

-

VeCH

Gnd

16

8

-

16

+ +

16

+
-

'8

+
8

Output

Output Voitage

VOLl
VOL2
VOH

3
3
3

0.40 1 - 1 0.40 1 -

1 OAO 1 Vdc I - 1 0.45
0040 1 -. 1 OAO 1 - 1 OAO 1 Vdc 1 - 1 0.45
2A 1 - 1 2A 1 - I 2.4 1 - 1 Vdc 1 2.4 1 - 1 2A

0.45 1 -

1 0.45 1 Vdc
1 0.45 1 Vdc

0.45 1 2A 1 -

3

1 Vdc

-1
31

See Timing Diagram

16

-

7.8.10

See Timing Diagram

-

16

See Timing Diagram

16

-

7.8.10
7.8.10

Power Requirements

(Total Device)

'pDH

16

Turn·On Delay C to Q

tpd-

3

Turn-Off Delay C to Q

tpd+

Turn·On Delay MR to Q

tpd-

Turn-On Delay MR to Q

Ipd-

3
3
3

Power Supply Drain

73

mAde

44
26
70
70

ns

-

73

mAde

44
26
70
70

ns

Switching Parameters

16
Pulse In·

ns
ns
ns

• Letters in parentflesis refer to waveform.
#These pins tied together
##These pins tied together

•

ns
ns

91WI
91W)
lIY).9IX)
lIZ),9IXI

Pulse Out

3
3
3
3

V .. x = 2.4 Vd.
1.4.6.11.13
1.4,6.11.13
4,5.6,11,12,13
4,5.6,11,12,13

16
16
16
16

8
#
2.5
2,5

##
12,15 7.8,10
12.15 7.8.10
7.8.10
7.B.l0

MC9328, MC8328 (continued)

SWITCHING TIME TEST CI RCUIT AND VOLTAGE WAVE FORMS

1 MR
9

Two pulse generators
are required to provide
the waveforms shown.

Q

3

C

Os
DO

PULSE
GENERATOR

Q

2

01
PRF : 1.0 MHz

typ

50

t+ = t- "S:10 ns
(10% to 90% points)
Amplitude = 3.0 V
PW"" ns
28

Pulse
W

100
30
56

X
Y

c,. ""

Z

15 pF "" total parasitic capacitance, which includes probe, wiring, and load

capacitances.
*The coax delays from input to scope and output to scope must be matched. The
scope must be terminated in 50-ohm impedance. The 95C-ohm resistor and the
scope termination impedance constitute a 20: 1 attenuatar probe. Coax shall be
CT-070-50 or equivalent.

CLOCK PROPAGATION DELAY
Pulse W

3.0 V

TPin
Clock

tpd+

TP out
Q

~=f==

TP out
Q

____________________________~____________________~~_____ ~~gL
~VOH

__4--t===========================================t~===~VOL
GNO

tpd_

MASTER RESET PROPAGATION DELAY
Pulse X

TPin

J\..J'JL.3.0

Clock

.

V

0 V

Pulse X J V L J L 3 . 0 V
TPin
Clock
0 V
PW(iiiiFl) (Clock Pulse Low)

PW(iiiii'i) (Clock Pulse High)

Pulse V

\r--------3.0 V

TPin

MR

Pulse Z

TPin

-----------------0 V

]-t

MR

Q

~,-------------OV

Jt

t Pd -

t Pd -

TP out

\r-------3.0 V

---------------;;,VOH

1.5V
~VOL

GNO

TP out
Q

------------;;,VOH

1.5 V

~VOL
GNO

MC9300/MC8300 series

RETRIGGERABLE
MONOSTABLE
MUL TlVIBRATOR

MC9601F, L~
MC8601F, L, p~

Input Loading Factor = 1
Output Loading Factor:

MC9601- 6
MC8601 = 8
Total Power Dissipation = 80 mW typ/pkg
Propagation Delay Time = 2~ ns typ

80
81 1
Vee = Pin 14
GND

= Pin

7

"-~.~-...

82 2 ~~"-__'
AI30-------;

6

A24o-----....I

a

The MC9601/8601 monostable multivibrator may
be triggered from either edge of an input pulse and
will produce accurate output pulse over a wide range
of widths. The duration and accuracy of the complementary output pulses are determined by the external
timing components, RX and CX. Each time the input
conditions ,for triggering are met the external timing
capacitor, CX, is discharged, starting a new output
pulse. The output goes to the high state while Cx is
being discharged and remilins there until the capacitor
recharges through RX, to a threshold determined by
an internal comparator. Input pulses applied during
the active state again discharge the capacitor, thus
adding another full timing cycle to the output pulse
width. This retriggering feature can be inhibited if
not required.

FUNCTIONAL TEST

1/4 MC3003

Bl
y

TIMING DIAGRAM
Y

-,I

r

...--.....;-~

3 ,OV
GND

4.5V

Device
SEQUENCE
1.
2.
3,
4.
5.

MC9601

Apply VIL to Bl.
Momentarilv grou nd Y.
Apply VIH to Bl.
Apply VIL to Bl,
Check V for logical "1" level.

MC8601

CIRCUIT SCHEMATIC

AI

30-.-------------'

GND

7
4o-~~----------'

A2

·F suffix = T0-86 ceramic flat package (Case 607).
L suffix = TOM116 cerl!lmic dual in-line package (Case 632).
P suffix = TO-1 fa plastic dual in-line package (Case 605).

Temperature

VIL

VIH

-55
+25
+125
0
+25
+75

0,85
0,9
0,85
0.85
0,85
0,85

2.0
1.7
1.4
1.9
1,8
1.6

•

MC9601, MC8601(continued)

ELECTRICAL CHARACTERISTICS

TEST (URRENT!VOLTAGE VALUES(')
Cx RX

Test procedures ar. shown for O~IV
on.
~VCC
:~~~r ~th.r inputs are tested in the sam.
i~

t=g:

o

81 1
82 2

Temperature IOL JOH
-SSO( 10.0 -0.72

I

80

MC9601·

VF
0.4

4.5

4.5

5.5

+25°C 1-"10"-,0+-0"'.7='+-:-'"'"0+:0--.,:-+-:-,.'"'5-tc5
=-.0:--t-:-,.-::5-tcC:-5."'5-i

l +12S C1-":.:0",.0+:-0__. 7;;:.2t--+~0':"'+.:;'.-:-5+_t-:".:::5:+.5".::5-1

6

,

1i

Pin

MC9601 Test limits

Leakage Current
Clamp Voltage

12.8 -0.96

0'(
+25'C
+ 75'C
Unit Min Max Min Max Min Max Unit
-1.6

-1.6

mAde

60

60

I..I.Adc

60

Yd,

-1.5

-1.5

0.45

4.5

~:!:

!::

5.0

4.75

5.25

::~:

::::

IOL

-1.6 mAde

-1.6

-l.6

-10

TEST CURRENT !VOLTAGE
APPLIED TO PINS LISTED BELOW,
V,

MC8601 Test limits

Under -55'(
+25'(
+ 125'(
Symbol Test Min Max Min Max Min Max
-1.6

O°C

t :~~:~ ~::: ~~:::

MC8601

Forward Current

10

o

A 1 3 ~=:=;=L~
il
A2 4~
L--

Characteristic
Input

Volts

mA

@Tost

60

Gnd
14

!-(Adc

14

Yd,

14

Vdc
Vdc

14
14

7,11
7

Vdc
Vdc

14
14

7
7,11
6,7
7811

Output
Output Voltage

0.4

0.4
0.4

O.A

2.4
2.4

Short-Circuit Current

2.4
2.4

0.4
0.4
2.4
2.4

Vdc
Vdc

-10 -40
-10 -40

ISC

Vdc
Vdc

0.45
0.45
2.4
2.4

0.45
0.45
2.4
2.4

-10
-10

mAde

mAde

0.45
0.45
2,4
2,4

-40
-40

mAdt·

14

mAde

14

Power Requirements
Power SUpply Drain

14

25

25

25

mAde

25

25

25

mAdc

14

(1) A la-kilohm resistor (RX) is placed between Pin 13 and Vee for all tests unless otherwise noted,

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Coax·

950

t+

=t- ~tOns

I __________ ...J1
L

• The coax delays from input to
scope and output to scope must
be matched. The scope must
be terminated in 50-ohm impedance. The 950-ohm resistor and the scope termination
impedance constitute a 20: 1
attenuator probe. Coax shall
be CT-070-50 or equivalent.
CT = '5 pF = total parasitic capacitance, which includes
probe, wiring, and load capacitances.

4.5 V

.z---±=±"",.,---------3.0 V
=~---+:::=========g'~~
When RX = 5.0 k!l,CX = 0:
PW :: 65 ns max, tpd+ :: 40 ns max, tpd_ = 40

ns

max

OND
=========~~~------~===SVOL

When RX = 10 k!l ±.1.0%, Cx = 1000 pF:
PW = 3.081ls min, 3.76 ils max

PW---..;

TPout

a

MC9601, MCS601 (continued)

TYPICAL CHARACTERISTICS

FIGURE 1 -INPUT LOAD CURRENT
versus INPUT VOLTAGE
+0.5

;(

!

IZ

1

I

0 t--vle~5'lv-0.5

w

T A ~ _55 0 e

II:
II:

::J

u

-1.5

..

I::J

\

I
-2.5

/
TA - -550 e

::J
U
w

w

.J

..

o

I

40
TA::

r-- -

20

I::J
Z

-0.5

TA - -S50C

«

"«

...-TA~+1250e

III

-3.5
-1.5

60

(.'I

_TA ~+250e

~

+0.5

1

I

-Vec~S.ov

II:
II:

TA = +2SoC

I

0

j
IZ
w

l.CJr\

'po-

a
«
.J

~1+12)e'":l.

TA

FIGURE 2 - INPUT LEAKAGE CURRENT
versus INPUT VOLTAGE
80

+1.5

Y+12rc \"

o

1

I

Vee~5.0V

!

- r-TA

Output Low

120

L.?"

IZ

w

II:
II:

§

80

~V

::J
U

.

I::J
I::J
0

~ +125Le~

2.0

o ~
o

~

r-

;(

.5

V~C-5.~V

I

Output High

1

0

IT A == +2SoC

Z

I

II:
II:

TA = _55°C, "'"

J#

W

I

-10

U

'-TA

~

..

I::J

_55 0 e

I::J
0

I#'
0.4

0.8

1.2

~

~20

1.6

o
~
w

130

z
i=
~

o

~

110

90

a

II:

w

..s:C

o

..

70

----

I

-

Vee

~

I
5.0 vide

4.5

~ r50
-55

5.5 Vde

-25

o

25

v~e
I
SO'

::;

---75

8.0

- --1.00

TA. AMBIENT TEMPERATURE (oC)

o

~

~

,....

I

' T A =+25 0 C

' T A =+125 0 e

1
I

+1.0

+2.0

+3.0

+4.0

+5.0

+6.0

+7.0

VOH.OUTPUT VOLTAGE (VOLTS)

FIGURE 5 - POWER DISSIPATION versus
AMBI ENT TEMPERATURE and SUPPLY VOL TAG E

.5

6.0

~

/#

-30
-1.0

VOL. OUTPUT VOLTAGE (VOLTS)

~

4.0

FIGURE 4 - OUTPUT CURRENT versus
OUTPUT VOLTAGE (HIGH STATE)
+10

::J

~~

40

~

INPUT VOLTAGE (VOLTS)

FIGURE 3 - OUTPUT CURRENT versus
OUTPUT VOLTAGE. (LOW STATE)

;(

':

/ / /f

INPUT VOLTAGE (VOLTS)

160

+250~

/

o

+2.5

T

..........

125

i=
>-

::)
w
a
II:

w

FIGURE 6 - NEGATIVE TRIGGER DELAY TIME
varsus AMBIENT TEMPERATURE
80

CL = 15
40

r--

II:

I-

r

to~

r--

(.'I

~

w

.l

I

VCC = 5.0 Vde
RX=5.0kf!
60 r-- Cx = 0 pF

20
'off

>

~

(.'I

w

Z

- Complementary

o
-55

-25

o

--

Output

'1 TrueOitput
25

50

75

100

T A. AMBIENT TEMPERATUR E (oC)

125

MC9601, MC8601 (continued)

TYPICAL CHARACTERISTICS (continued)

1O
f-

CI

1.2

§:
w
en
..J

:::>
f-

:::>
f-

1.0

:::>

o

aw

N

::;

1

--

1.1 _

0-

0-

FIGURE 8 - NORMALIZED OUTPUT PULSE WIDTH
versus SUPPLY VOLTAGE

FIGURE 7 - NORMALIZED OUTPUT PULSE WIDTH
versus AMBIENT TEMPERATURE
J:
f-

.1.

CI

VCC - 5.0 Vdc
RX- 1Okn
Cx -10 3 pF

--......

§:

w
en

..J

:::>

Z

---

- --.......

-

0.9

:::>
0-

f-

1.0

:::>

o
CI
w

~

0.8

..J

4:

::;
0.8
-55

II:

-25

a

25

50

75

100

125

o
Z

0.6
4.0

4.5

T A, AM81ENT TEMPERATURE (oC)

1O
f-

CI

§:
w
en
..J

:::>

FIGURE 9 - NORMALIZED OUTPUT PULSE WIDTH
versus OPERATING DUTY CYCLE
1.4r---,----r---,----~---r--_,----r_--,

r-1.2 r--

VCC - 5.0 V
RX - 10 kn
Cx - 10 3 pF
TA:= +25 0 C

f-

Z

w
en
f-

:::>
:::>
0

::;

65

r\

60

~

0.6~

20

__~__- L__- - '____~__- L__~~__~__~
40
60
80
100
OPERATING ClUTY CYCLE (%)

z

::;

~dC

5.0
RX = 5 kn

:::>

::;

o

Vc~ -

70 ~=OPF

f-

0.8f-~+----l----I----+---+---+----+---~

4:

II:

§:

0-

CI
W

75

0-

o

N
..J

oS

:::>

1.01--+--+-+--+--+--1--+--"1

:::>

6.0

FIGURE 10 - OUTPUT PULSE WIDTH
versus AMBIENT TEMPERATURE

..J

:::>
f-

.

CI

-l-----f---+---+---I-----j

5.5

5.0

V CC , SUPPLY VOLTAGE (VOLTS)

J:
f-

0-

0-

I.

f-

4:

o

1

-- TA _+25 0 C
RX -10 kn
1.2 - - Cx _10 3 pF

0-

::;
II:

1.4

55
-55

~

~

VV

"" ---25

o

25

/

-t--

50

75

100

125

T A, AMBIENT TEMPERATURE (oC)

PULSE WIDTH
For values of Cx less than 1000 pF, the output pulse width,
PW, is defined by the curves of Figure 11. For larger values of
eX use the equation:
PW - 0.32 RX Cx [1 + (0.7fRX)]
where PW is in nanoseconds,

OPERATING CHARACTERISTICS

RX is in kilohms,
eX is in picofarads.
Values of RX may vary from 5.0 kilohms to 50 kilohm. for
00 to +75 0 C operation of the MCS601, and from 5.0 kilohms to
25 kilohm. for -55° to +1250 C operation of the MC9601. The
range of capacitance values is unlimited, hence maximum pulse
width is limited only by the values of available capaCitors.

MC9601, MCS601 (continued)

10

5.

t--O~

Cx >1000 pF
PW= 0.32 RXCX [1 + (0.7/RXll

3.0

k"'.
VII'

~

1.0

~

J:

b

~

RX

:>

O. 3

I-

:>
0-

I-

~

:>

o

~.

0-

~WL

I--'"'

L

V

/'

V

'/

V V V
V V
V ~V
.L
L

L

L

V
lIEf:rL
I-- I-V VV
I--'
V
I-- I-- ~~

~ l-

0-

=5~lk~

V

L

IL
0.5

w

'1

V

L
/

FIGURE 11-0UTPUT PULSE
WIDTH versus TIMING RESISTANCE
AND CAPACITANCE

L

./

O. 1

10k!}

...-

0.05

~Ikh

0.03

0.0 1

1.b

3.0

5.0

10

30

50

100

300

500

Cx. TIMING CAPACITANCE (pF)

PULSE INITIATION
Output pulses are initiated by ahy combination of inputs satlS~

fying the logic expression AI. A2 • 181 + 82); A 1 and A2 must be
high and 'either 81 or B2 must be low. Output pulSes are generated

by transitions from low to high 00 A 1 or A2. and by transitions
from high to low on 81 or 82. Leading edge triggering may be
accomplished by either of the methods shown io Figure 12.
Similarly, trailing edge triggering may be accomplished by
either of the methods shown in Figure 13.

FIGURE 12-LEADING EDGE TRIGGERING

=j§

~40ns~ 3.0V

Input~

=J;

Input~
'\L
3.0 V
~
",--0.4 V
----t------------~------GNO

0.4 V

GNO
t p f o- ' - -_ _ _ _ _....
Output

~2.4

1.5 V

V
=:::::::::::::::~.==============0.4
GNO

la) INPUT TO 81 (B2. AI, AND A2 HIGH)

~40nS---j

tPdfo

V

Output

-------;;,,2.4 V
1.5 V

V
=:::::::::::::::~.==============0.4
GNO

Ib) INPUT TO A, (A2 HIGH, Bl OR 82 LOW)

MC9601, MCS601 (continued)

FIGURE 13-TRAILING EDGE TRIGGERING
r--------------------------------,
r--------------------------------,

J. :!:40n.~

----'"""+------3.0 v

Input

1.5 V

0.4 V

F

GND

:!:40n.~
--{:
~

...-----3.0 V

Input

tpd~

t Pd

Output

:!:2.4 V

GND

===================~=====0.4 V
(a) INPUT TO Bl (B2, AlAND A2 HIGH)

FIGURE 14 - NON·RETRIGGERABLE OPERATION

GND

:::V

I

Output

1.5 V

0.4V

====================~======GND
(b) INPUT AI (A2 HIGH, Bl OR B2 LOW)

In Figure 14(a), A2 is held low by the

a output during the

active state. Since both A inputs must be high for triggering to
occur, this configuration inhibits retriggering at all of the remain·

ing inputs.
The configuration of Figure 14(b) will be triggered active on
the trailing edge of a negative going pulse applied to either AI or
A2. B2 and 61 are then held high by the Q output. Since either
61 or 62 must be low for triggering to occur, further triggering
during a timing cycle is inhibited.
The feedback arrangement of Figure 14(c) holds 62 low during
the active timing cycle. Since this keeps the output of the inverted
OR gating circuitry high, subsequent input signals to 61 during the
active state do not retrigger the monostable. Noise immunity is
improved by returning unused "high" inputs to VCC through a
2.0 kilohm resistor instead of leaving them open (see Aland A2
of Figure 14(c), for example.)

i

II

(a)

Inputs

ASTABLE OPERATION
Astable applications requiring adjustable duty cycles may be
accomplished by the conventional method of cascading two onsshots as shown in Figure 15. In applications where narrow output
pulses are satisfactory, a single monostable may be used. One
method for dOing this is illustrated in Figure 16, monostable A.
The clock gener~tion for a simple pulse generator is accomplished
by connecting the
output of the "A" monostable back to an
AND input. The period of oscillation, or pulse repetition fre~
quency, PRF, is determined by the external timing components,
RXA and CXA. At the end of each timing cycle, the QA output
generates a low-to~high transition at the AND input and thus
triggers another cycle. The nominal output pulse width is approx~
imately 30 ns, and is determined by the propagation time through
the gating and discharge circuitry. The maximum PRF is approx~
imately 15 MHz, obtained with CXA = 0 pF and RXA = 5.0 kil.
The variable delay feature is controlled by the timing components
of monostable '"B'", CXB and RXB. The output pulse width is
determined ·by CXC and RXC, the timing components of monostable '"C".

a

(b)

Input

a

2 k

Vee
(c)

RETRIGGER INHIBIT
For applications where retriggering is not required .. appropriate
feedback from the outputs will inhibit trigger signals arriving
during the active timing cycle. Figure"4 illustrates three methods
for doing this.

ELECTROLYTIC CAPACITOR PROTECTION
If electrolytic capacitors are used they should be protected
from reverse voltage; either of the methods indicated in Figure 16
may be used. Any silicon switching diode, such as the lN4001
shown for monostable '"B", is adequate. The transistor method
of monostable lieu requires a silicon transistor with gain at low
currents.
This figure also illustrates the preferred method of using remotely located variable timing components. Noise pickup will be
minimized by locating RX and Cx physically close to the device.
Stray capacitance at pins 11 and 13 should be 50 pF or less.

MC9601, MCS601 (continued)

FIGURE 15 -ASTABLE OPERATION -ADJUSTABLE DUTY CYCLE

Vcc

Vcc

.....-oa2

~-

Vcc

Vcc

.-J

I

--------.-+1- 0.32

(1 ::2) -+I------·~I~.
+

-,

L

I

I

RX2

C (1 O
:2)
X2

+R

---'I

1...._ _ _

FIGURE 16 - PULSE GENERATOR

Vcc

Vcc

~"..

,

S Rx(max) - RXA2

Vec

~"'"
I

I
I

R

I

I
I

<

RX (0.7) hFE

I
I

I

I
RXA2 ~ RX(min)

RXB2

B

Qr---------------~
MC8601

MC8601

'""1·-----PRF------l'1
aAJn~

I
1

__________~n~__~------__~
I
II

I

11______

~D.,aY__l_pw~'---------I

•

•

BEAM~ LEAD
INTEGRATED CIRCUITS

MCBC5400/ MCB5400F SERIES

l

MCBC5400/MCB5400F SERIES

BEAM LEAD

INTEGRATED CIRCUITS

INDEX

Introduction
Beam Lead Technology
Beam Lead Reliability Assurance Steps
Packaging
Typical Characteristics
Breadboarding Suggestions
Maximum Ratings

DEVICE SPECIFICATJONS

II
I

MCBC5400
MCBC5401
MCBC5402
,MCBC5430
,.MCBC5440
MCBC5453
MCBC5454
MCBC5460
MCBC547~

MCB5400F
MCB5401F
MCB5402F
MCB5430F
MCB5440J;'..;
MCB5453F
'MCB5454F
MCB5460F
MCB5472F.

Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate (Open Collector Output)
Quad 2-lnput NOR Gate
8-lnput NAND Gate
Dual 4-lnput NAND Buffer
Expandable 4-Wide 2-lnput AND-OR-INVERT Gate
4-Wide 2-lnput AND-OR-INVERT Gate
Dual 4-lnput Expander for AND-OR-INVERT Gate
J-K Flip-Flop

GENERAL INFORMATION
MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUITS

.....-.~

FIGURE 1 - TYPICAL MTTL CIRCUIT
MCBC5400IMCB5400F Series

INTRODUCTION
The MTTL MCBC5400/MCB5400F series of transistortransistor logic is a medium-speed, high noise immunity
family of saturating integrated logic circuits designed for
digital logic apptications requiring clock frequencies to 30
MHz and switching speeds in the 12-15 ns range under
moderate capacitive loading.
The bel!m lead sealed-junction technology 'used in this
MTTL family makes the devices useful in military, aerospace, and commercial applications that require a high
degree of reliability under environmental conditions of
severe temperature extremes, mechanical shock, and high
humidity. The beam lead products employ a silicon nitride
dielectric that hermetically seals the chip,eliminating the
need for a hermetic package. The beam leads are gold
cantilevered structures extending from the chip. These
beams bond readily to a gold metalized substrate providing
one of the most reliable interconnection systems known for
semiconductor devices.
The circuits in the MCBC5400/MCB5400F series are
identified by a multiple emitter input transistor and an
active pullup in the upper output network as shown in
Figure 1.
The multiple emitter input configuration offers the
maximum amount of logic capability in the minimum
physical area and provides improved switching characteristics du.ring turnoff. Clamp diodes are provided at each
of the inputs to limit undershoot that occurs in typical
applications such as driving long interconnect wiring. The
active pullup output configuration provides low impedance
in the high output state. The resulting low impedances in
. both states provide excellent ac noise immunity and allow
high-speed operation while driving large capacitive loads.
These beam lead MTTL units have the same electrical
characteristics as the. conventional flat-pack units and may
be used interchangeably with them. This eliminates the
need for electrically redesigning equipment for improved
reliability after the successful performance of prototype or
pre-production units with conventional devices.
BEAM LEADTECHNOLOGY
Junction Sealing
In conventional integrated circuits, the p ..,N junctions are pr~
tected bV a layer of silicon dioxide. This oxide, while acting 85 an
simulator and. providing a degree of protection, is permeable to mo-

bite ions.· Ions- impinging on the surface of the finished circuit can
cause high leakage current and reduction of current gain. Silicon

nitride passivation applied over the oxide prevents contaminants
that can result in such degradation from reaching the oxide .

Metalization
The metalization on the Motorola beam lead integrated circuits
of platinum silicide ohmic contacts topped by layers of titanium
and platinum. These in turn are followed by two layers of gold.
The first ~old leyer providE.. ' the. chip intraconnection and the
second, thicker layer forms the cantilevered beams that connect the
chip to theo";tside world (see Figure 21. This metalization method
has .the ability to withstand conditions of high humidity over extended periods of time without degradation or the formation of
undesirable inter-metallics. It is also capable of being bonded to a
gold-metalized substrate and provides a highly relaible gold-ta-gold
bond, which is easily made and readily inspectable. Bonds have also been made to other substrate metal materials without difficulty.
Durihg the bonding process, beam read devices lift off the
substrate surface, which, with the ductility of the gold metal beams
and the high quality bond, allows the device to withstand wide

variations in temperature without,failure due to fatigue.

Separation Etch
Conventional integrated circuits are separated wi~h a "scribe and
break" technique v.hich not only results in a yield lo's' dul.to cracking of .the die, but can, also- result io minute cracks, which do, not
immediately. reveal. ,themselves ,and can cause· device . failure. at a
later date. The beam lead sealed-junction del/ices are separated by
chemically -etching through the silicon.from the back side, thereby
avoiding mechanical stresses and/or other latent defects.

•

Mlll

GENERAL INFORMATION
MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUITS

TABLE 1
Beam Lead Reliability Assurance Steps

I. Chips
A. Tests performed after wafer separation etch

1. Post separation etch visual inspection (backside)
2. Wafer electrical probe (100%dc testperdata sheet at 250 C.
B. Tests performed on a bonded sample after die transfer and
pick
1. Beam integrity

al Bond qualification samples to test header
b) Push die off haader from metallization side
c) Each beam must withstand 2.00 gm. min.
2. Junction seal integrity
a) Electrical test
b) Apply NaCI over die
c) Reverse bias input junctions at T A = 3000 C for eight
hours in forming gas atmosphere

d) Electrical test
3. Electrical qualification
a) Package sample
b) DC parameters at all temperatures per data sheet
c) AC test per data sheet
C. Inspection after die pick and sort
1. 100% high power visual inspection
2. Rand QA sample high power inspection
II. Packaged Devices
A. Inspection after die bond.
1. Sample visual inspection

B. Testing after encapsulation

1. Lot stress screening
a) Temperature cycling: -65 0 C to 1500 C min; 10 cycles
b) Water immersion: boiling water ("'1000 C; 1 hour)
c) Electrical measurements: dc leakage parameters
d) Stabilization bake: T A = 1750 C min; 24 hours min
e) High temperature reverse bias (cost option)
C. Testing after package cleaning and marking
1. Electrical tests
a) Final dc test per data sheet at 25 0 C (100%)
b) Final ac test per data sheet at 250 C (sample)
2. Rand QA final outgoing inspection
a) Burn in screen (cost option)

b) Group A - visual/mechanical .inspection per MIL·
STD-883. method 2009. Group A tests are performad
on every lot on a sample basis.

D.C. electrical measurements per data sheet (sample)
A.C. electrical measurements (sample)
c) Group B environmental testing per MIL-STD-883
Class A as applicable. These tests are performed
periodically during the manufacturing period on a
production lot of a representative circu it type. The
circuit type selected each per.ied is changed routinely
and is representative of all structurally similar devices
produced on the same line by the same processes

during that period.
d) Group C - life testing per MIL-STD-883 Class A as
applicable. These tests are performed periodically on
at least one lot of every circuit family produced during that period.

FIGURE 2 - BEAM LEAD SEALED JUNCTION TRANSISTOR

•

Thin Gold

m~====~11 Lij~~~f;:

Platinum
Titanium

Silicon Dioxide

Reliability Processing
Conventional integrated circuits have established an outstandi ng
reputation for reliability. Beam lead integ~ated circuits provide

even higher reliability by eliminating the major failure modes of
conventional circuits. Most failures in conventional 'Integrated circuits are due to contaminahts reaching the active chip or to fajlure .

Silicon Nitride

in the bonds between the package and the chip. Beam lead technology solves both of these problems. The silIcon nitride hermetically seals the chip so that even a leaking package causes no failure.
The all-gold beam lead interconnection system eliminates the
sources of conventional bond failure~ These processes, are completely documented by in-process specifications and are carefully
monitored' for·adherence to process requirements and inspection

I

GENERAL INFORMATION

MTTL

MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUITS

FIGURE 3 - 14-L••d Chip

FIGURE 4 - 1S-Laad Chip

leads true position within 0.002 total.

Leads true position witliin 0.062 total.

FIGURE 5 - Di. Size

Device
Number

Function
2~lnput

NAND Gate

Di.
Size

No_

Na_

Beem~

Plns_

Ceramic
Siz,"
14x%.

5400

Quad

35 x 45

14

14

5401

Quad 2-lnput NAND Gate Open Collector

35 x 45

14

14

14x14

5402

Quad 2-lnput NOR Gate

45x 45

16

14

5410

Triple 3"·lnp·ut NAND Gate

35 x 45

14

14x%.
14x%.

5440

Dual"4-lnput NAND Buffer

35 x 45

14

14

14x"%,

5453

Expandable AND/OR Inverter

35 x 45

14

14

14x14

5454

4 Wide 2-lnput ANDIOR Inverter

35 x 45

14

14

14x%.

5460

O"ual4-lnput Expander

36 x 46

14

14

5472

J-K Flip Flop

46 x 45

16

16

5473

Dual J.,.K Flip Flop

-

14

14x%.
14x%.
14x%.

-

14

standards by the Motorola Reliability and Quality Assurance Department. In addition, the tests itemized in Table 1 are conducted
on all lots from which die are taken for sale either as dice or packaged circuits.

FIGURES.

Mechanical Properties
0.045
0.055

00'3

oirnlcl1~
MIN

.1

ml'lm,~
~O'40..j 'T
Imll

lead 1 identifiedby£olor dot or by elbow(!n lead.
Top COV8r mad,ofsHastic material.

FSUFFIX
CERAMIC PACKAGE
CASE 651

The beam leads, which are cantilevered ·from each die, are
tested for beam-strength, hardness, ductil1ty and adhesion to the
chip by suitable tests to demonstrate that the die are readily bondable and will be reliable under extreme temperature and mechanical
stress conditions.

Packaging and Handling
The MCBCq400/MCB5400F series of beam lead sealed-junction
digital integrated circuits is. availabl~ in the. chip, form and in a
y.. .. x J(," ceramic flat package. Tlte shipping carrier for chips is.8
2" square glass pla~ pn which the chips are placed. A thin layer
of polymerfilm covers the plate and retains the chips in place, The
chips do not IIdhere to, the .film when it· is lifted to remove them
from the carrier. Call! must be exerci$~ "Yhen. r~moving t.he chips
from the carrier to ensure thatthe beams are not bent. This is most
easily done by using a vacuum pick'upfor this purpose.

•

GENERAL INFORMATION

MTTL

MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUITS

Standard beam patterns are used depending on the die size required. Figures 3, 4, and 5 show these configurations and list the
devices that are made from

~ach.

TYPICAL CHARACTERISTICS
The following summary presents the typical operating
characteristics of ttie MTTL MCBC5400iMCB54ooF series.
Unless otherwise indicated, the parameters are defined for
VCC = +5.0 volts and TA = +250 C.

Power and Ground Distribution
Spacial care should be taken to insure adequate distribution of
power and ground systems. The typical rata of change of currents
and voltages for a single MTTL gate is in the range of 107 Als and
108 Vis respectively. These figures reflect the necessity for alowimpedance power supply and ground distribution system, if transients are to be minimized and noise margins maintained. The use
of AWG No. 20 wire or larger i. often required. For printed cireu itry, lina widths of 100 mils or more are often necessary. A
ground plane is desirable when using a large number of units.

Bypassing
Supply Voltage Operating Range = 4.5 to 5.5 volts
Operating Temperature Range = -55 to +1250 C
Output Drive capability
Other Gate. (Output Loading Factor) = 10
capacitance = 600 pF
Output Impedance
High State = 70 ohms (unsaturated) nominal
Low State = 10 ohms nominal
Output Voltage Swing = 0.2 to 3.5 volts typical
Input Voltage Limits
+5.5 volts maximum

-0.5 volt minimum
Switching. Threshold = 1.5 volts nominal

Worst-case DC Noise Margin
High State - 0.400 volt minimum
Low State - 0.400 volt minimum
Power Dissipltion (1)
Basic Gate = 10 mW Iyp/gate
Basic Flip·Flop = 40 mW typ/pkg
Switching Speed. (2)
Average Propagation Delay = 13 ns per gate typical
30 ns per flip·flop typical
Rise Time = 2.5 ns typical
Fall Time = 1.5 ns typical
Maximum Flip-Flop Clock Frequency

Power Dissipation
The standard supply voltage of the MTTL logic circuits is +5.0
Vdc. The typical average de power diSSipation is given for each
MTTL circuit. (1) It should be noted that the totem pole output
common to all high laval MTTL circuits hes an associated ac power
dissipation factor. This factor results. from the timing overlap of
the upper and lower output transistors during the normal switching
operlition and is typically 0.30 mW/MHz/output for a 15 pF load.
This ac power dissipation should be added when calculating the
total power requirements of the MTTL circuits.

Input Impedance
High State = 400 k ohms nominal
Low State = 4.0 k ohms nominal

I

To reduce supply transients, the breadboard should be bypassed
at the point where power is supplied to the board and at intarvals
throughout the board. The use of a singla bypass capacitor at the
output terminal of the power supply is not adequate in a breadboard utilizing tha fest rise and fall time MTTL circuits. A comperetively large, low-inductance type capacitor (in tha 1.0 "F range)
is suggested at the point where power and ground entar tha board.
In many c.... it has been found that distributing 0.01 "F cepacitors for avary eight packages throughout a breadboard is adequate
to suppress normal switching transients. It is also suggested that a
bypass capacitor be placed in close proximity to any circuit driving
a large capacitive load.

Unused Inputs and Unused Gates
The unused inputs of any MTTL logic circuit should not be left
open, and can either be tied to the used inputs or returned to the
supply voltage. This will reduce any potential problems resulting

= 20 MHz typical
(11

Po

=

IpOL

+ IpOH
2

(Vee)

where IpOL and IpDH are the typical de current drains at Vee ""

±s.o v.
BREADBOARDING SUGGESTIONS
When breadboarding with any form of high-speed; high-performance TTL, tlie desigrier must continually bfi aware of the fact
that he is working with the fastest form of saturating logic avallabla in the industry today. The switching spaeds, espacially the
fraquencieS associated with the very fest -rise and fall timeS of the
circuits, are in the R F range and good high-frequency layout teChniques should be ·used. The following breadboarding ·suggestions
have been inCluded to help the designer in his initial circuit layout.
In many cases the breadboarding suggestions will hava to be modified to meet therequiremants of the designar's spacific application.

(2)The ,witching characteristics of the MTTL famllv are defined
with respect to the aSSociated translstions of the voltage waveforms.
The average propagation delay Is defined as the average of the turnon delay and the turn-off delay measured from the 1.6 V point of
the Input to the 1.5 V point of the associated output translt'on or:
ton + toff
tpd = - - 2 - - ns.
Rise time is defined as the positive going transition of the output
from the 10% to the 90% V level. Fall time is defined 8S the negative tr8nsitlon.of the output from the 90% to the ,1 0% V level.

MTTL

GENERAL INFORMATION
MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUITS

from external noise. If the inputs are returned to the supply volt-

age, care should be taken to insure that the supply voltage does
not exceed the maximum rated input voltage of 5.5 volts. If the
supply can exceed 5.5 volts, the unused inputs must be returned to
a lower voltage. The total number of inputs that can be tied to the

output of any driving gate is 50. (This is defined as high state output loading factor.) It should be noted that the low state output
loading rules must .still be maintained. The minimum logical "'"
level, VOH = 2.4 V minimum for the high-state output loading,
with Vtho =0.8 V, IOH = -0.4 mA, and VCCL.

SIGNAL LINE NOISE IMMUNITY
LOGIC "0" LEVEL

LOGIC "'" LEVEL

GROUND LINE NOISE IMMUNITY

POWER SUPPLY NOISE IMMUNITY

-1.
J"l:;.-GND
GND

)

oRl.J""t;;"
-i f-pw

)

r---'----,

•

SIGNAL LINE NOISE IMMUNITY
w

o

:l

LOGIC "0" LEVEL

6

LOGIC "'" LEVEL
LOGIC "1" REFERENCE
LEVEL = 3.5 VOLTS

LOGIC "0" REFERENCE
LEVEL = 0.2 VOLTS

I-

:::;

~Cij 4

1\

«~

wo

~~

.

2

III

0

:l

W

(5
z

w

o

0

l

......
50

100

150

~Cij2

«~

wO

~.~ 1
:l

..
z

:3
I-

150

300

6r-~------t---------r---------r-------~

~

5 4r-----". . __
=-+----~--+-------+---------!

~

2r--------+--~--~r_------~------~

w

100

250

: :;


.J-

PW. NOISE PULSE WIDTH (ns)

20.0

s:r-_PO_W_E_R--,-SU_P_P_L_Y,--N_O--,-IS_E_I_M_M_U_N_ITT_Y_ _--,

~~

'-....
50

150

:l

0

0

100

PW. NOISE PULSjO WIDTH (ns)

,

:::;

(5

50

GROUND LINE NOISE IMMUNITY

I-

w

250

3

:l

III

200

. PW. NOISE PULSE WIDTH (nsl

200

250

6z

\.

°0~------~10~0~------2~0~0~------3~00~-------4~00
PW. NOISE PULSE WIDTH (ns)

MTTL

GENERAL INFORMATION
MCBC5400/MCB5400F Series
BEAM LEAD INTEGRATED CIRCUIT5

The unused inputs of the various flip-flops mav be tied back to

trigger the flip-flop. In addition, clamp diodes have been provided

their associated outputs. To determine which outputs are related
to each set of inputs by internal feedback, refer to the circuit
schematics.

on all data inputs to limit any undershoot or negative ringing on the
data lines.

The inputs of any unused gate in a package should be grounded_
This places the gate in its lowest power condition and will help to

Dual J·K Flip-Flop - MCB5473F

eliminate unnecessary power drain.

edge of the clock. Each of the independent flip-flops has a single
J and a single K input. A direct RESET has been provided for preclearing the flip-flop regardless of the state of the clock. The op-

Expanders and Expander Nodes
The DRing nodes of all the MTTL AND-DR-INVERT gates are
made available for expanding the number of AN D gates to 6
(MC5450F) or 8 (MC5453F)_ Since these are cOmparatively highimpedance nodes. care should be taken to minimize capacitive loading on the expander terminals if switching speed is to be maintained.
When an expander is to be used with an expandable AND-ORINVERT gate, it should be placed as close as possible to the gate

being expanded. The increase in average propagation delay as a
function of capacitance added to the expander nodes is typically
1_0 ns/pF_

This dual master-slave J-K flip-flop also triggers on the negative

eration of this device is the same as the MCB5472F. Each of the
flip-flops has the special clamp circuit on the clock line as well as
clamp diodes on all the data inputs.

Noise Immunity
In a typical system noise begins to pose a problem when it is of
such a magnitude that it can change the state of a flip-flop in the

system or prevent a flip-flop from Changing state at the proper
time. Noise can be present on the ground line. the power supply
line or the signal line.
In designing a system using MTT L. particular care must be taken

Output OR (AND) Function

due to the extremely high rate of change of voltage and current

Unlike the MDTL family of logic circuits, the outputs of the
MTTL logic circuits cannot be tied together to perform the output OR, or more correctly, the output AND function_ If the.outputs of the MTTL family devices are tied together, it would be pos-

on the signal lines and current on the power supply and ground
lines (see sections on Power and Ground Distribution and By·
passing). Th~se factors increase the possibility of noise gener~tion
within the system itself in addition to externally generated noise.
Noise immunity in a digital system is a function of the propaga-

sible for the lower output transistor of one circuit and the upper
output transistor of another circuit to be "on" simultaneously.
This condition provides a lowwimpedance path from Vee to ground
and the current that flows (approximately ISC) exceeds the guar-

anteed sink current. As a result. the saturated state cannot be
maintained and the desired logic function is not satisfied.

Operating Characteristics of Flip-Flops
J-K Flip-Flop - MCBC5472/MCB5472F
This master-slave J-K flip-flop triggers on the negative edge of

the clock. An AND-input configuration is used. consisting ot three
J inputs ANDed together and three K inputs ANDed together. A
direct SET and RESET are provided to permit presetting data into
the flip-flop. The direct SET and RESET control the operation of
the flip-flop regardless of the state of the clock.
Information is '1orl)1aIlY.applied to, or changed at the clocked

inputs while the clock is in the low state since the master memory
is inhibited in this condition. Information may be stored in t~e
master flip-flop section when the clock goes high. Once the input

data has been stored in the master flipwflop section it cannot be
removed (or changed) by me~ns of the clocked inputs. The direct
SET or RESET provide the only means of removing previously
stored information. They override the clock input and can be
applied any time during the· clock cycle.
The state of the master flip-flop is transferred to the slave flipflop section· on the negative transition of the clock. and the outputs respond accordingly. The flip-flop can be set or reset by applying a low state to the direct 'SET or RESET inputs. A speci~1

clamp circuit has been included on the clock line to guarantee that
negative transients, such as ringing on the clock line. do no~ false-

tion delays of the gates and flip-flops in the system and the dc
threshold levels of these devices. The following block diagrams

show typical test set-ups for measuring signal line. ground line and
power supplV line immunity of a gate in a digital system.
The system is considered disturbed when the flip-flop begins
toggling. The curves show the tvpical noise amplitude a system can
accept as a function of noise pulse width. As the pulse widths bew
come narrower the amplitude can increase without disturbing the
system. This can begin occurring when the pulse width is less than
20 ns on the signal line or 50 ns on the power supply or ground
line. ,This pulse width·amplitude product is an indication of the
minimum noise energy that is required to disturb a system. The
low input and output impedances of MTTL gates and flip-flops re-

quires more energy on the s.ignal lines to distrub the system than in
DTL or RTL systems. With proper power and ground distribution

and bypassing. noise on power supply and ground lines can be main w
tained below levels which would be detrimental to system operation.

MAXIMUM RATINGS
Rating

Supply Voltage - Continuous
Supply Operating Voltage Range
Input Voltage
Output Voltage
Operating Temperature Range
Storage Temperature Range Ceramic Package
Maximum Junction Temperature
Therma1 Resistance Junction-to-Case. 8 JC
Ceramic Package

Value

Unit

+7.0
4.5 to 5.5
+5.5
+5.5
-55 to +125

Vdc
Vdc
Vdc
Vdc

-65 tD +150

DC

+175

DC

0.09

°C/mW

DC

MCBC5400/MCB5400F series

QUAD 2-INPUT "NAND" GATE

MCBC5400*
MCB5400F*

~

B[AMLEAD~
This device consists of four 2-input NAND gates that is
produced using beam lead sealed junction technology. These
devices are particularly useful in highly reliable systems using

1/4 OF CIRCUIT SHOWN

hybrid beam lead assembly techniques or standard flat pack·

age assembJy techniques.
4

Vee
4k

1.4 k

100

3

Positive Logic: 3 = ~
Negative Logic: 3 =

'1"+"2

1 k
Input Loading Factor

=

1

Output Loading Factor = 10

GND

TOtal Power Dissipation = 40 mW typ!pk.g

11
Propagation Delay Time

SWITCHING TIME TEST CIRCUIT

= 10 ns

typ

VOLTAGE WAVEFORMS AND DEFINITIONS

Vee
+5.0 Vdc

Coax"
950

r--v+-=:::--3.0 V

400

"ri----l.5 V
---~----~~~---OV

tPd_~.
tP.d+ 2.4 V

MMD6150

t+ ""-12
t-::::

or Equiv.

n5

6.0 ns

PRF = 1.0 MHz, 50% duty cycle
Generator ZoutR:50 ohms

MMD7000
or EQuiv.

+2.4 Vdc

CT = 15 pF =

tot.&1

parasitic capacitance, which includes

T-P out

-------====:------------~~ci max
pro~e,

wiring, and load

capacitances.
"The qoax delays from input to scope and output to scope must be matched.
Tt:'ascope must be terminated in 50-ohm impedance. The 9S0-ohm resistor and
the scope~termination impedance constitute a',20: 1 attenlJator probe. Coax shall
be CT-070-50 or equivalent.

"F suffix;:: 1/4" x 1/4u ceramic package (Case 651). MCBC-prefixed devices are un,.
encapsulated. Beam numbers are the same as the pin numbers for flat-packaged
devices. See General Information section for package and chij:rdetails.

min

1.5 V

III
s:

ELECTRICAL CHARACTERISTICS

n
to
n

Test procedures are shown for only one
gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.

To complete testing, sequence through remaining inputs.

~=C}-3

CJ1

~=C}-5

.0

~

o

1~=LJ--8

IOL

IOH

V1L

TEST CURRENT /VOlTAGE VALUES (All Temperatures)
Volts
VR2
V1H V1HH
VR1
V.h1
V.hO Vcc

16

-0.4

0.4

2.4

12=C}13
14

Characteristic
Input

mA

Test Limits
MCBC5400/MCB5400F
Pin
Under -55 to +125°C
Symbol Test Min Max Unit

IOL

5.5

4.5

5.0

2.0

0.8

5.0

s:

n

to

VCCL

VCCH

4.5

5.5

CJ1

~

o
o

"T1

nO

TEST CURRENT / VOLTAGE APPLIED TO PINS LISTED BELOW:

::l

::!".

IOH

V1L

V1H

V1HH

VR1

VR2

V. h1

V. hO

Vcc

VCCL

VCCH

Gnd

a.

Forward Current

IF

1

-

-1. 6

mAde

-

-

1

-

-

2

-

-

-

-

-

4

11*

Leakage Current

IRI

1

-

40

/lAde

-

-

-

1

-

-

-

-

-

-

-

4

2,11*

IR2

1

-

1.0

mAde

-

-

-

-

1

-

-

-

-

-

-

4

2,11*

VOL

3

-

0.4

Vde

3

-

-

-

-

-

-

1,2

-

-

4

-

11*

VOH

3

2.4

-

Vde

-

3

-

-

-

2

-

-

1

-

2,4

-

11*

ISC

3

-20

-55

mAde

-

-

-

-

-

-

-

-

-

-

-

4

1,2,3,11*

IpDH

4

-

22

mAde

-

-

-

-

-

1,2,6,7,9,
10,12,13

-

-

-

-

4

11

IpDL

4

-

8.0

mAde

-

-

-

-

-

-

-

-

-

-

-

4

1,2,11*

Pulse
In

Pulse
Out

Output
Output Voltage

Short-Circuit Current

Power Requirements
(Total Device)
Power Supply Drain

::l
C
C1l

Switching Parameters
Turn-On Delay

tpd_

1,3

-

15**

ns

1

3

-

2

-

-

-

-

-

4

-

-

11*

Turn-Off Delay

tpd+

1,3

-

22**

ns

1

3

-

2

-

-

-

-

-

4

-

-

11*

*Ground inputs to gates not under test.
**Tested only at 25° C.

MCBC5400/MCB5400F series

QUAD 2-INPUT "NAND" GATE
WITH OPEN COLLECTOR

MCBC5401*
MCB5401F*

,~
&Jj
.. ··0

BEAM LEAD

~

r

This device consists of four 2·jnput NAND gates with no

output pullup network that is produced using beam lead sealed

1/4 OF CIRCUIT SHOWN

junction technology. These devices are particularly useful in
highly reliable systems using hybrid beam lead assembly tech-

niques, or standard flat package assembly techniques.
4

Vee

1.4 k

Positive Logic: 3 =
Negative Logic: 3 ""

W
02

1 k
Input Loading Factor

Output Loading Fill;tor

10

Total Power Dissipation'" 40 mW tvp/pkg

GND

11

Propagation Delay Time'" 35 ns typ

VOLTAGE WAVEFORMS ANO DEFINITIONS

SWITCHING TIME TEST CIRCUIT

Vee
TP out

+5.0 Vdc

1,-----,.'f-f----3.0 V
90%

\t----1.5V
10%

------~+I------~~------OV

tPd~~~-1
. .
i:tPd+
I

t+

=

t- =

12ns

TP out

6.0 ns

PRF = 1.0 MHz,50%dutycycle

+2.4 Vdc

_~

1.5 V

_____===_-_-_---------~~6 max

Generator Zout ::::: 50 ohms

R L = 400 ohms for tpd_ test.

4.0 k ohms for tpd+ test.
CT "" 15 pF "" total parasitic capacitance, which includes probe, wiring, and load
capacitances'.
High impedance probes (>1.0 megohm) must be used for tests.

*F suffix"" 1/4" x 114" ceramic package (Case 651). MCBC-prefixed devices are unencapsulated. Beam numbers are the same as the pin numbers for flat-packaged
devices. See General Information section for package and chip details.

2.4 V min

•

•

ELECTRICAL CHARACTERISTICS

s:

n

Test procedures are shown for only one

to

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.

(')

~:::[>-3

To complete testing, sequence through re-

C11

~
....

~:::[>-5

maining inputs.

109:::[>-S
12:::[>-14
13
Test Limits
Pin MCBC5401/MCB54011
-SS to +12SoC
Under
Test Min Max Unit

mA
IOL

V1L

(All Temperatures)
TEST CURRENT!VOLTAGE VALUES
Volts
V1H V1HH
VR2
VR1
V'h 1
V'hO VCEX VCC

16

0.4

2.4

mAde

-

1

-

40

/lAde

-

-

1

-

1.0

mAde

-

-

3

-

0,4

Vde

3

I CEX

3

-

0.25

mAde

IpDH

4

-

22

IpDL

4

-

8.0

IF

1

-

-1. 6

Leakage Current

IRI

1

-

IR2

1

VOL

2.0

0.8

5.5

5.0

4.5

5.5

C11
~

....o
(")

o

:l

V1H

Forward Current

5.0

VCCH

"T1

V1L

Symbol

4.5

to

VCCL

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:
IOL

Characteristic
Input

5.5

s:

n

V1HH

....

VR1

VR2

V,h 1

V'hO

VCEX

Vee

VeCL

VeeH

Gnd

2

-

-

-

-

-

-

4

11'

-

-

-

-

-

-

-

-

4

2,11*

-

1

-

-

-

-

-

-

-

4

2,11'

-

-

-

-

-

1,2

-

-

-

4

-

11'

-

-

-

-

1

-

-

2

3

-

4

-

11'

mAde

-

-

-

-

-

1,2,6,7,9,
10,12,13

-

-

-

-

-

4

11

mAde

-

-

-

-

-

-

-

-

-

-

-

4

1,2,11'

Pulse
In

Pulse
Out

m

Q.

Output
Output Voltage

Output Leakage Current

Power Requirements
(Total Device)
Power Supply Drain

Switching Parameters
Turn-On Delay

t pd _

1,3

-

15**

ns

1

3

2

-

-

-

-

-

-

4

-

-

11

Turn-Off Delay

t pd +

1,3

-

45**

ns

1

3

2

-

-

-

-

-

-

4

-

-

11

.Ground inputs to gates not under test.
**Tested only at 25°C.

5'
c

MCBC5400/MCB5400F

QUAD 2-INPUT "NOR" GATE

series

MCBC5402*
MCB5402F*

This device consists of four 2-lnput NOR gates that is produced using beam lead sealed junction technology. These de-

1/4 OF CIRCUIT SHOWN

vices are particularly useful in highly reliable systems using
hybrid beam I.ead assembly techniques or standard flat package
assembly techniques.

4

Vee
4 k

4k

1.4 k

100

3

2
Positive Logic: 3 ""
Negative Logic: 3

1'+2

0:

;-;-2

Input Loading Factor'" 1
Output Loading Factor'" 10
Total POwer Dissipation
Propagation Delay'Time

GND

= 48 mW typ/pkg
='0 ns typ

11

Package No.11 I 21 31 41 51 61 7 I 8 I 9 110111112113114j
~m~
1 2131415161719110~111211311411~
Pin numbers on drawings are for devices in the flat package.

SWITCHING TIME TEST CIRCUIT

VOLTAGE WAVEFORMS AND DEFINITIONS

Vee
+5.0 Vdc

~--...- - - - - - 3 . 0

4011

gOilo.5"
..
10%

'----0 V
)O-H'-~-•. MMD6150

50%
50
t-

=:0

2.4 V min

or Equiv.

1.5 V

t+

15 ns
PRF = LO MHz
G~enerator Zout

t-

MMD7000
or Equiv.'

t-f :;:;

_I--+~==!~~==g.~~

+2.4 Vdc
~

V

'1<----1.5 V

50 ohms
CT = 15 pF

=total

parasitic capacitance, which includes·probe, wiring, and load

capacitanc~s.

·The coax delays from input to scope and output to ,scope must be matched.
The ~cOJ)J1I mt.!st be terminated in 60~ohm impedance. The 950~ohm resistor and
the scope termin~tion impedance constitute a 20: 1 attenuator probe. Coax shall
be C),-Q70..S0' or equivalent.

*F suffix =; 1/4" x 1/4" ceramic package (Case 651) MCBC-prefixed devices.are unencapsulated. See General Information section for package an'd chip details. •

max

•

•

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one

s

(')

~=D-3
~=D-5

gate. The other gates are tested in the same
manner. Further, test procedures are shown
for only one input of the gate under test.
To complete testing, sequence through re·
maining inputs. Pin numbers used are for
devices in the flat package.

OJ

n

CTI

,J:Io

o

9~8

10-----L-/-

~N

12~ 14
13~

(')

s

OJ
CTI

TEST CURRENT/VOLTAGE VALUES (All Temperatures)
Volts
VR2
VR,
V'hl
V'hO Vcc
V'H V'HH

mA
10H

10l
16

Characteristic
Input

Test limits
Pin MCBCS402/MCBS402F
-SS to +12S'C
Under
10l
Symbol Test Min Max Unit

Forward Current

IF

1

Leakage Current

IRI

1

~2

1

VOL

-

I

0.4

"Il

0.4

I

2.4

5.5

4.5

5.0

2.0

I

0.8

5.0

~

N

VCCl

VCCH

4.5

5.5

"T1

n-O
::J

~.

TEST CURRENT /VOLTAGE APPLIED TO PINS LISTED BELOW:

::J

c:

(1)

10H

VIl

V'H

V'HH

VRI

VR2

1

-

-

2

-

1

-

-

-

-1. 6

mAde

40

tlAdc

-

-

-

1.0

mAde

-

-

3

-

0.4

Vdc

3

-

VOH

3

2.4

-

Vdc

-

ISC

3

-20

-55

mAde

-

-

IpDH

4

-

27

mAde

-

IpDL

4

16

mAde

1

V'hl

VCCH

Gnd

-

4

11'

-

4

2,11*

-

4

2,11*

V'hO

Vcc

VCCL

-

-

-

1

-

4

-

2,11*

-

2

4

-

1,11 "'-

-

-

-

-

-

4

1,2,3,11*

1,2,6,7,9,
10,12,13

-

-

-

-

4

11

4

1,2,11*

-

2,11*

a.

Output
Output Voltage

Short-Circuit Current

3

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Power Requirements
(Total Device)
Power Sftpply Drain

Switching Parameters
Turn -On Delay
Turn-Off Delay

.

Pulse
In

Pulse
Out

-

-

-

'pd-

1,3

-

15**

ns

1

3

-

-

-

-

-

-

'pd+

1,3

-

22**

ns

1

3

-

-

-

-

-

-

Ground inputs to gates not under ,test.
**Tested only at 25 0 C.

-

4

-

4

-

2,11*
I

- - - - - - - ....

~----

MCBC5400/MCB5400F series
8-INPUT "NAND" GATE

MCBC5430*
MCB5430F*

~
,~

BEAM LEAD

This device is an 8 input NAND gate. It is useful when
processing a -large number of variables, such as in encoders
R

Vee

and decoders.

4

8eam lead sealed junction technology is used to manufacture these devices. They are particularly useful in highly
4k

1.4 k

t.....

1111, III
~f-

2
3
5
6
7
8

reliable systems using hybrid beam lead assembly techniques
or standard flat package assembly techniques.

100

2~

,

_ _..,

3
5

6

12

>--0 12
8
9
10-~----'

9
10

f'>o..
Positive Logic:

~.

12

1 k

•

=

2.3.5.6.7.8.9.10

NeQ"ative Logic:

12 = 2 + 3 + 5 + 6 + 7 + S • 9 I 10
.~

Input Loading .Factor:: 1
Output Loading Factor"" 10

Total Power Dissipation = 10 mW tvp/pkg
Propagation Delay Time = 10 ns typ

11
GND

•

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
+5.0 Vdc

[,---,+-+--:---3.0
90%

400

'irr----l.5V

--I~..:1..:0':':%~_GND

TP out

L ____ -'I

t+

t-

= 12

ns }
== 6.0 "ns
10% to 90% points

TP out

50

MMD7000
or Equiv

PRF = 1.0 MHz, 50% duty cycle
PW - 0.5/ls
Zout~50 ohms

tPd-~r

MMD6150
or Equiv

--I

'-----L=...1.5

V

- - -___-====::::c::::c::::--~~ci' max

"=

CT = 15 pF '" total parasitic capacitance, which includes probe, wiring, and load capacitances.
The coax delays from input to scope and output to scope must be matched. The scope must
be terminated in 50·ohm impedance. The 9S0·ohm resistor and the scope termination impedance constitute a 20: 1 attenuator probe. Coax shall be CT -070-50 or equivalent.

*F suffix = 1/4" x 1/4" ceramic package (Case 651). MCBC-prefixed devices are unencapsulated. Beam numbers are the same as the pin ntimbers for flat-packaged
dev}ces. ~ee General I nformation s~ction for package and chip details.

~2.4vmin

•

ELECTRICAL CHARACTERISTICS

s

(")

Test procedures are shown for only one in-

tXJ

put. To complete testing, sequence through

(")

c.n
~
w

remaining inputs in the same manner.

~o

S

3

(")

tXJ

c.n

12

~

w

:~
10L
16

Characteristic
Input

10H

V"

TEST CURRENT /VOLTAGE VALUES (All Temperatures)
Volts
Vth1
V.,
V.,
V,hO Vee
V'H V'HH

-0,4

0.4

2.4

mA

10

Test limits
Pin MCBC5430/MCB5430F
55 to +125°(
Under
Symbol Test Min Max Unit
-

Forward Current

IF

Leakage Current

IRI

2

40

pAde

IR2

2

1.0

mAde

VOL

12

0.4

Vdc

VOH

12

2.4

ISC

12

-20

IpDH

4

IpDL

4

2

-1. 6

I

5.5

4.5

I

5.0

I

2.0

I

0.8

I

5.01

o

."

Ven

VeeH

4.50

5.50

0o

=,
::J

::J

C

CD
Q.

TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:
10L

10H

mAde

V"

V'H

V'HH

2

-

V.,

V.,

V,hl

Vec

Vcn

3,5,6,7,8,
9,10

-

2

-

V,hO

-

-

2

VCCH

Gnd

4

11

4

3,5,6,7,8,9,10

4

3,5,6,7,B,9,10

-

11

Output
Output Voltage

Short-Circuit Current

-

12

Vdc

-

12

2

3,5,6,7,
8,9,10

-55

mAde

-

-

6.0

mAde

-

-

4

2,3,5,6,7,
B,9,10

4

-

11

-

4

2,3,5,6,7 ,B,9,10, 11,12

-

-

4

11

-

-

4

2,3,5,6,7,8,9,10,11

4

-

Power Requirements
Power Supply Drain

8,9,10

-

2.0

Turn-On Delay

tpd_

2,12

Turn -Off Delay

tpd+

2,12

-

-

-

mAde

Switching Parameters

**Tested only at 25°C.

-

2,3,5,6,7,

Pulse
In

Pulse
Out

15**

ns

2

12

-

3,5,6,7,
8,9,10

22**

ns

2

12

-

3,5,6,7,
8,9,10

-

-

-

4

11

11

MCBC5400/MCB5400F series

DUAL 4-INPUT "NAND"

BUFFER

BEAML"D~

MCBC5440*
MCB5440F*

This device consists of two 4-input NAND power gates that
are produced using beam lead sealed junction technology. These
devices are particularly useful in highly reliable systems using
hybrid beam lead assembly techniques or standard flat package
assembly techniques.

1/2 OF CIRCUIT SHOWN

100

lj=L}-2

g=C)-10
1
12

13cr-t-+~
14

Positive Logic: 2 - , • 12 .13'.14


1 3 W"l "

(Write "1")

X, 3
9 W"O" (Write "0")

~

"

1,1

I

~ ~

1,2

~

~

~

H

1.3

~ {;J

X2 2

~

2.1

I

~ ~

2.2

2.3

~

A

VCC=Pin4
GND- Pin 10

\

T T

Po = 260 mW tvp/pkg

X3 1

~,

tpel: Write Mode"'" 25 ns typ
Sense Mode"'" 16 ns typ

~ ~

3.1

I

3.2

~ ~

3.3

~

1

3,4

'~
125"1" (Sense "1")

X4 14

~,

4.1

I

~L1

4.2

~~

4.3

~y

4,4

~

,
,1 5"0" (Sense "0")

-OPERATING SEQUENCEFIGURE 1 - READ MODE TIMING DIAGRAM

X. Y Select Lines

I

----~-+--1

10

GNO

WRITE INVERTER

----"

-

-

, -

-- .--------

ELECllUCAL CHARACTERISTICS
@Test
Temperature
t -5S 0 (
M(4304*, MC430S

MC4004-, MC400S

Volts

1ST

Pr*

SId

Iw

'XY

Vln1

•

Write Jnputs

13

Leakage Current
Address Lines

'R

1~

Write Inputs
Breakdown Voltage
Address Lines

BVin

1~

Write Inputs

Output (Note

-11
-1.33
-1.33

0,85

0.9

4.5

~::

4.5
4.5

1.0

3.0

0.75

~:~

::~

~:~:

::::

(

40

20

1.0

3.0

0.8

1.0

1.0

,!~~:~:~

:~

~:~

~:~

~::

~~~

~:~

O°C

Vf

:::

Vout

Vee

2.2

5.5

5.0

~::

:::

::~

2.1

5.5

5.0

::~

:::

v..

v...

BVclt

r~"

7.0

::~

7.0

Vee

BV...

3:

TEST (URRENT/VOLTAGE APPLIED TO PINS LISTED BELOW,

-11
-11

-13.5
-13.5

-13.5
-13.5

-13.5
-13.5

mAde
mAd('

-1.33
-1.33

-1.3
-1.331

·1.66
-1.66

·1.66

-1.66
-1.66

mAde
mAde

1'"0"

Iw

IXY

Vin1

Vin2

Vo '

V,

V,
5,6,7,6
11,2,3,14

Gnd
1,2,9,10,13,14

6,7,8,9,10,13
1,2,3,5,6,7,8,10,13,14
1,2,3,5,6,7,8,9,10,14

9
13

I : I~:: I = I g:! I : Ig:! I : Ig:! I : Ig:! 1:~~~
I = Ig:! I = I ~:! I = I~:! I =I~:! 1= Ig:!
~:~I
I~:~I
It~1
lUI I~::I I;:~I
~~~
1;:;1 1:::1 1::;1 Inl Inl 1;:;1 .~~~
~::
Ig:~

Vth

:~

-11
-11

·1.66

V.

20

Unit
-11

Vin3

40

Characteristic
Input
IF

Vin2

I +~~~:~:~

Pin I-'::':':~'F':";'::=-T---=:=+--=::C-'-T-'-"-="T'-'-'==r-

Forward Current
Address Lines

~
t
g

TEST CURRENT/VOLTAGE VALUES
mA

Tilt prQc:edUres ... shown for only one bit.

Oth.. bits . . tested in the lime manner.

1,2,5,6,7,8,9,10,13,14
1,3,.3,6,7,8,9,10,13,14
1,2,3,5,6,7,8,10,13,14
1,2,3,5,6,7,8,9,10,14

9

I mAdl'

13

1,2,5,6,7,8,9,10,13,14
1,2,3,6,7,8,9,10,13,14
1,2,3,5,6,7,8,10,13,14
1,2,3,5,6,7,8,9,10,14

9
13

I)

Output Voltage
Write "I"
Logic "0" Level

Vout "0 ..1 12

0.45

0.45

0.45

0.45

0.45

0.45 I

Vde

12

Write "O"Inhibit
Logic "0" Level

Vout "0 •.1 12

0.45

0.45

0.45

0.45

0.45

0.451

Vde

12

Logic "0" Level

Vout "0 ..1 11

0.45

0.45

0.45

0.45

0.45

0.451

Vde

11

Write "1" Inhibit
Logic "0" Level

Vout "0 ..1 11

0.45

0.45

0.45

0.45

0.45

0.45 J

Vde

11

',5

0.45

0.45

0.45

0.45

0.45 I

Vdc

12

Leakage Current
Write "1"
Leakage Current

IOLK I 12

0.25

0.25

0.25

0,25

0.25

0,251 mAde

0.25

0,25

0.25

0.25

0.25

0.~51

mAdc

IoLK 1 11

0.25

0.25

0.25

0.25

0.25

0.251

mAde

Leakage Current
Write "0"
Leakage Current

IOLK I 12

0.25

0.25

0.25

0.25

65

65

65

72

0.25

0.25 I

mAd('

1,2,6,7,8,10,14

',5

1,2,6,7,8,9,10,13,14

3,5

1,2,6,7,8,9,10,13,14

3,5,13

1,2,6,7,8,10,14

3,5

1,2,8,7,8,9,10,13,14

3,5,13

1,2,6,'J,8,10,14

1,2,6,7,8,10,14

12

13,5,6,7,8
3,5,6,7,8

1,2,6,7,8,~,10.13,14

1,2,6,7,8,10,14
11

3,5
13

Write "1"

3,5,9

3,5,9

13

IOLK I 11

1,2,6,7,8,9,10,13,14

3,5

Write "0"

Leakage Current

3,5

13

Write "1"
0.45

1,2,6,7,8,9,10,13,14
1,2,6,7,8,10,14

13

Vout "0,,1 12

1,2,6,7,8,10,14

3,5
13

3,5

Write "0"

Logic "0" Level

3,5,13

11

1,2,6,7,9,10,13,14
1,2,9,10,14
1,2,9,10,13;14

3,5,6,7,8

1.2,10,13,14

3,5,6,7,8

1,2,9,10,13,14

Power Requirements

. (Total Device)

PoweJ;" Supply Drain

'pD

Power Supply Breakdown
Current

!"kt

95

72
105

72 I

mAde

1,2,3,5,8,7,8,9,10,13,14

mAdc

1,2,3,5,6,7,8,9,10,13,14

.Prime Fan-Out
Note 1. Output logic "0" voltage a.n<1leakage current measurements are made as part of a functional test of a memory.
Procedures identified by a double asterisk (... ) are preconditIoning procedures lor the subsequent test. AU
power supply and input voltages must be maintained between te;sts.

~

i

•

~

."

~

r-

~

~

g

~"
r;,
~

3:

(")

~
~

:nr-

;,

8"

...:i.
::::I
t:

~

MC4304F,L, MC4305F,L IMC4004F,L,P, MC4005F,L;P (continued)

SWITCHING TIME TEST CIRCUIT

Vcc

TPout

TPin

RI

R2

Two pulse generators are
required and must be
slaved to provide the
waveforms shown.

High·impadance probes ( >1.0 Megohm) must be
used when taking measurements.

DEVICE UNDER TEST

R1
OHMS

R2
OHMS

MC4304, MC4004
MC4305, MC4005

120
240

330
560

see Switching Time Test Procedures

table for value of CT-

VOLTAGE WAVEFORMS AND DEFINITIONS

10 ns max

10 ns max

~----------------~~~nv------3.0V
A

TPin
PRF = 1.0 MHz

PROPAGATION OELAY
TIME

=~~====:2~oo~~n'~====+~~====O.4 V

t=-- GND
!I.SV

tpd+
B

TP out

------~~============~------GND
~--~~=--ftT,-------------------3.0V

•

C

D

TPln
PRF= 5.0 MHz

==~~~=I':=================~'~~

TPout

--~~~~--~======+==~GND

RECOVERY TIME
E

TPln
PRF - 5.0 MHz

F

TPout

J<--,--:t±b",.,..--3.0 V

MC4304F,L, MC4305F,L /MC4004F,L,P, MC4005F,L,P (continued)

SWITCHING TIME TEST PROCEDURES

I Letters shown in test columns refor to waveformsl
Pin

Test
Tum-off Dalay Time
(Address Lines' to

Sen.. "0" Output)

Symbol Undor

....
tpd+

....

Test

11

(Address Lin.. to
Sen .. "1" Output)

Turn-On Delay Time
(Address Lines to
Sense ·'0" Output)

Turn-On Delay Time
(Addren Line. to
San .. "". Output)

Turn-Off Delay Time
(4 BiU) (Addres. Lines
to San ..

"0." Output)

Turn-Off Delay Time
{4 Bits) (Address Lin ..
to Sense "1" Output)

Write Recovery Time

Write Pulse Width

-

t"d+
tpd+

12
12.

tDdtpd_

11

....

....
....
....

'cdtpd_

tpd+

2
X2

,
X3

Input Pin

,4
X4

5
Y,

6
Y2

Limits
,2 CT" MC4304·5 MC4004·5
nsmax
nsmax
W"O" W",,, 5"0" 5",,, pF
Output

7

Y3

8
Y4

9

,3

3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0V 3.0 V Gnd 3.0V
3.0 V Gnd Gnd Goo 3.0 V Gn~ Gnd Gnd 3.0 V Gnd
A
A

tpd+
Turn-Off Delay Time

3
X,

Gnd
Gna

Goo
Gna

Gnd
Gnd

A

Gnd

Gnd

A

Gnd

Gnd

God
Gnd

Gnd

God

God

Gnd

3.0 V 3.0V 3.0 V 3.0V 3.DV 3.0V 3.0V 3.0 V 3.0 V Gnd
3.0 V Gnd Gnd Gnd 3.0 V Gnd Gnd Gnd Gnd 3.0 V
A
God Gnd Goo
A
Gnd Gnd Gnd Gnd Gnd
Gnd Goo Gnd Gnd Gnd
A
God Gnd Gnd
A

-

-

-

-

B
B

-

30

23

23

200

36

35

-

-

-

-

-

-

B

30

B'

200

23
35

36

-

-

23

3.0 V

-

-

-

-

Gnd
Gnd

-

-

B

30

23

23

n

3.0 V 3.0 V 3.0 V 3.0Y 3.0 V 3.0 V 3.0 V 3.0 V Gnd
3.0 V Gnd Gnd Gnd '3.0 V Gnd Gnd Gnd 3.0V
God Gnd Gnd
A
Gnd Gnd Gnd God
A
A
Gnd Gnd Gnd
A
Gnd Gnd Gnd 'Gnd

Gnd

B

200

36

35

Gnd

-

3.0 V 3.0V 3.0V 3.0V 3.0V 3.0 V 3.0 V 3.0V 3.0 V
3.0 V Gnd Gnd Goo 3.0V Gnd God Gnd Gnd

-

-

12
12

11

A
A

Gnd
Gnd

Gnd
Goo

Gnd
Gnd

A

Gnd

A

Goo

Gnd
Gnd

Gnd
Gnd

Gnd
Gnd

3.0 V, 3.0V 3.0V 3.11 V 3.0V 3.0 V 3.0 V 3.0V Gnd
3.0 V God Gnd God 3.0 V 3.0V 3.0 V 3.0 V 3.0 V
A
Gnd Gnd God
A
A
Gnd
A
A
3.0V 3.0 V 3.0 V 3.0Y 3.0V 3.0V 3.0V 3.0 V 3.0 V
3.0V God Gnd Gnd 3.0 V 3.0 V 3.0 V 3.0 V Gnd

-

Gnd
3.0 V

23

-

B

200

35

36

-

-

-

-

-

30

35

35

-

-

-

Gnd

-

3.0 V

,A

Gnd

Gnd

Gnd

A

A

Gnd

Gnd

Gnd

Gnd

Gnd 3.0V 'Gnd

Gnd

Goo

E

11

3.11 V

Gnd

Gnd

Gnd 3.0V

Gnd

Gnd

E

C
C

Testeq during 'twr tests.

-

23

B

3.0 V

Gnd

-

30

Gnd

12

A

-

B

-

12

-

-

-

-

Goo

'wr

-

A

3.0V
Gnd

tpd+

'wp

"

F

-

-

-

B

30

35

35

0

30

40

40

30

40

40

ns min

nsmin

26

25

·Capacitance value for load of the Switching Time Test Circuit
• ·Preconditioning procedures for subseq~uent test.

I

MEMORIES

16-BIT SCRATCH PAD,
MEMORY CELL
WITH GATED INPUTS

MC5484L*
MC7484L,P*
driving one of four X select lines and one of four '( select
lines above the select threshold. Two sense amplifiers are
shared by all 16 bits and provide a double rail output from
the selected bit. The sense output of many devices can be
"wired ORed" together since the output stage does not
have a pullup resistor or network. Two gated write am·
plifiers allow a "1" or a "0" to be written into a selected bit.

This 16-Bit memory cell serves as the basic building
block for Scratch pad memory systems having cycle times
of less than 100 ns. The basic cell provides 16 words of
orre-bit memory operating in the non-destructive readout
(NDRO) mode.
The memory contains 16 flip-flops arranged in a four·
by·four matrix. A single bit of the matrix is selected by
6

7

Yl

8

Y2

9

Y4

Y3

16 } W"l" (Write "I")
15
11
} W"O" (Write "0")
10

Xl 4

~.

1.1

I

~

2.1

~

~

~ ~

1.2

2.2

~

0

~

q

2,3

H
_~

I

1.4

H

2,4

~

~

v cc = Pin 5
= Piii-:2

Gt>10

"'d: Wrl te Mode = 2& ns typ
Sen.. Mode = 15 nl typ
PO= 260 mW typfpkg

X3 2

~

3,1

.I

~

r-

~

~ ~

3,2

3,3

~H ~
3.4

v

4,1

I

r-~

~~

4,2

4,3

~y

4,4

~

14 S"l" (Sense "I")

-{>----<> 13 S"O" (Sen.e "0")

"- OPERATING SEQUENCE FIGURE' - READ MODE TIMING DIAGRAM

x, V Select Lines

I
I.R -

1.0 Megohm) mUlt be

see Switching Time Test Procedures

used when talc. ;ng measurements.

table faT value of CT.

VOLTAGE WAVEFORMS AND DEFINITIONS

10 ns max
10 os max
r----------il=l::ariiiZ"'---3.0 V

A

TPin
PRF - 1.0 MHz

t - - - - - 200

n 5 - - - - - I t="'-_ _ _ O V

PROPAGATION DELAY
TIME
B

TP out

3.0 V

e

PRF

TPin
~ 5.0 MHz

OV
100 ns

0

TPout

--~
Output not

defined

GND

RECOVERY TIME
E

F

3.0 V

TPin,
PRF - 6.0 MHz

":Pout

OV

~·~.
.• 1.5;V
defined ..

GND

•

MC5484L, MC7484L,P (continued)

SWITCHING TIME TEST PROCEDURES
(Lette.. sho_ in test columns refer to waveforms)

Turn-Off oelay Time
(Address Lines to

Sense "0" Output)

Turn-Off Delav Time
(Address Lines to

Sense" 1" Output)

Turn-On Oelay Time
(Address Line, to
Sense "0" Output)

Turn-On Delay Time
(Address Lines to
Sense "1" Output)

Turn-Off ullIiay Tif(liii
(4 Bits) (Address Lines
to Sense "0" Output)
Turn-Off Delay Time
(4 Bits) (Address Lines

to Sense "1" Output)
Write Recovery Time

Write Pulse·Width

Symbol Unde,

....
....

Test

tpd+
tpd+

14

tpd+
tpd+

....
....

'pdtpd_

'pdtpd_

....
....

tpd+

-

-

13
13

14

13
13

14
14

13

-

Output

Input Pin

Pin
Test

4
Xl

3

2

X2

X3

1
X4

6

7

8

9

Yl

Y2

Y3

Y4

3.0 V 3.0V 3.0 V 3.0V 3.0 V Gnd 3.0 V
Gnd 3.0V Gnd Gnd Gnd 3.0 V Gnd
Gnd
A
Gnd Gnd Gnd Gnd
Gnd
una
A
Gnd Gnd Gnd Gnd Gnd

3.0 V 3.0V 3.0V
3.0V Gnd Gnd
A
Gnd Gnd
A
Gnd Gnd

3.0V 3.0 V 3.0V 3.0 V 3.0V 3.0 V Gnd
Gnd 3.0 V Gnd Gnd Gnd Gnd 3.0V
Gnd
A
Gnd Gnd Gnd Gnd Gnd
Gnd
A
Gnd Gnd Gnd Gnd Gnd

13

14

-

-

-

B
B

-

-

--

B

26
36

-

-

-

-

3.0 V
Gnd
Gnd

-

-

B

Gnd

-

tpd+

14

'wr

14
13

3.0 V
3.0 V

Gnd

Gnd 3.0 V

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd 3.0 V

Gnd

Gnd

Gnd

-

Tested during "twr tests.

E
E

-

35

25
35

3.0V 3.0 V 3.0V 3.0V 3.0 V 3.0 V 3.0 V 3.0 V Gnd
3.0V Gnd Gnd Gnd 3.0 V 3.0V 3.0 V 3.0 V 3.0 V
A
Gnd Gnd Gnd
A
A
A
A
Gnd

-

25

-

Gnd
3.0 V
Gnd
Gnd

-

26
36

nsrnax

15
200

3.0 V 3.0 V 3.0 V 3.0 V 3.0V 3.0V 3.0 V 3.0 V 3.0 V
3.0 V Gnd Gnd Gnd 3.0V God Gnd Gnd Gnd
Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd
A
Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd
A

B

-

15
200

-

B

3.0 V
Gnd
Gnd
Gnd

B

-

MC7484

-

3.0 V 3.0 V 3.0 V 3.0 V 3.0V 3.0 V 3.0 V 3.0 V Gnd
3.0 V Gnd Gnd Gnd 3.0V Gnd Gnd Gnd 3.0 V
A
Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd
A
Gnd Gnd Gnd Gnd
A
Gnd Gnd Gnd

3.0 V 3.0 V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0 V 3.0 V
3.0 V Gnd Gnd Gnd 3.0 V 3.0 V 3.0 V 3.0V Gnd
A
Gnd Gnd Gnd
A
A
A
Gnd
A

'wp

15

3.0 V 3.0V 3.0 V
3.0 V Gnd Gnd
Gnd Gnd
A
una una
A

Gnd

Limits

CT" MC5484
nsmax
W"O" W"I" S"O" S"I" pF
10

-

-

-

-

15

45

45

200

55

55

-

-

B

15
200

-

-

45

45

55

55

-

-

-

-

t5

30

30

-

-

-

-

-

B

15

30

30

B

-

-

-

-

3.0 V
Gnd

-

C
C

-

0

15

60

60

F

-

15

60

60

nsmin

nsmin

25

25

·Capacitance value for load of the Switching Time Test Circuit
• ·Preconditioning procedures for subsequent test.

OPERATING CHARACTERISTICS

Sixteen flip-flops are arranged in a 4-by-4 matrix with each
flip-flop representing one bit of 16 words. Each flip-flop, consisting of two cross-coupled triple-emitter transistors" is used to
store one bit. Memory status of a particular bit is determined by
sensing which of the two flip-flop transistors is conducting. One
emitter of each of these transistors serves as the sensing output.
All 16 of the logical "1" senSing outputs are connected to lhe
sense logic" 1" amplifier input, and all 16 of the logical "0" sensing outputs are connected to the sense logic '!O" amplifier input.,
The remaining emitters on each transistor provides the matrix
connections required for the X- and V-address lines. Address line
inputs are normally held at logic "0" and currents from all conducting flip-flop transistors flow out of these address lines.
To address a flip-flop both the X- and V-address lines associated
with that flip-flop are taken to a logic "1" voltage. Due to the
matrix nature of the circuit, at least one address line of all flip-flops
except the one being addressed will continue to remain at a logic "0"
level and no change will occur on those flip-flops. But, in the ad-

dressed flip-flop, the current in the conducting transistor diverts
from the address lines to the appropriate sense line and then to one
of the sense amplifiers. Thus, either the sense amplifier associated
with a logic "1" or the sense amplifier associated with a logic "0"
is activated. When this occurs, the output of the activated sense
ampl ifier drops from a logic "1" to a logic "0" level. The memory
is non-destructive as the states of the flip-flops are not disturbed
during sensing.
To store new information in a flip-flop, it is necessary to address
it and apply logic "1" voltage to the appropriate write amplifier
input. The output of the write amplifier responds by dropping to a
logic "0" level. Since all logic "0" sense lines are connected to the
output of the logic "0" write amplifier and all logic "1" sense lines
are conneoted to the output of the logic ,.'" write amplifier,
logic "0" VOltage on the output of a write amplifier will apply the
same voltage to emitters of all flip-flop transistors connected to that
amplifier. In all flip-flops except the one being addressed, this low
voltage has no effect since at least one other -emitter on each of the
flip-flop transistors is held low by the address lines. But two
possibilities .exist with the flip-flop that is addressed. The flip-flop
may already be in the desired state, in which case no change occurs.
But if the flip-flop must be changed from one state to the other, the
low voltage applied to the emitter of the transistor which is not
conducting turns that transistor on, causing the other transistor
to turn off.

a

MC5484l, MC7484l,P

(continued)

are enabled before a Y driver. However, if the memory accessing
sequence specifies that only a single bit may be selected at a time
and, consequently, that only one of the X (or Y) selection lines
may be high at a time, then the driver requirements can be relaxed
somewhat. This is possible because of current sharing in the mUltiemitters of the storage flip-flop transistors. If the voltages at the
emitters of the "on" transistor differ byno more than approximately
100 mV, then each emitter will carry an appreciable portion of the
transistor current. The saturation characteristics of the drivers determine the emitter potentials and, therefore, the division of eel(
current among the various drivers. Since the VOL of the driver
will increase if the collector current increases, the selection currents
will be almost evenly distributed among the drivers if the driver
saturation characteristics are reasonably uniform. If operation is
restricted to a single X selection line and a single Y selection line
and current sharing is assumed, then each select line must be capable
of. carrying the full current from a single cell plus approximately
one half of the current from three cells. Each line must, therefore, carry:

TYPICAL APPLICATIONS

A fast scratch pad memory offers the system designer several de~
sign alternatives. Temporary memory with a greater storage capacity
than simple registers can be distributed throughout a system. The

basic technique for expanding bit capacity is shown in Figure 3;
Figure 4 illustrates a method for expanding word capacity.

Optimum design of the selection Ihie drivers depends on the
specific system application. The maximum load presented to the
drivers by the selection lines is a function of the sequence used to
address the memory. The desired logic swing and noise immunity
should also be considered when designing the drivers. Each of the
16 flip-flops draws a maximum dc supply current of 2.75 mA
(for Vee = 5.0 Vdc). The total current flowing in all 16 flip-flops,

and consequently the summed current in the eight selection lines,
is 44 mAo (Each selection line is tested for a maximum of 11 mA).

11/4 + (3) (1/2) (11/4) = 6.88 mAo

Consider the sequence involved in selecting the four bits X1 y 1,
X1Y2, X1Y3, and X1Y 4 simultaneously. If the four Y select lines

Since the dc. output levels of the driver transistors determine
the noise immunity of the selection line, the system noise environment and the desired noise immunity should enter into the
driver selection.

are enabled before the X1 line then each of the four X lines must
carry the full current from four cells, i.e., 11 rnA. The Y drivers
must also have the capability of sinking 11 mA if the four X drivers

FIGURE 3 - 16 WORO, N BIT MEMORY

MEMORY ADDRESS REGISTER

J

I'

2

0

Decoder 2 Bit Binary to 1 of 4
Y, MC40Q7

Decoder 2 Bit Binary to 1 of 4
y, MC4007

Timing

Selection Line Drivers

Selection Line Drivers

J

X3

X2

Xl

Y4

Y3

Y2

y,

X4

1M

..l

,
>

•

:

:
Bit' Write

Bit 1 Sense

{i2J
{~

Timing

I

Bit 2

!~ ! ~

--,..-.---.,-'
Write Sense

Bit 3

bbbb

o ,

0

,

--,..-.---.,-'

Write

Sense

BitN

! ~ *~
-----

Write --..,-.'
Sense

C548417484

I

MC5484L, MC7484L,P (continued)

FIGURE 4 - 64 WORD, 4 BIT MEMORY

MEMORY ADDRESS REGISTER

Decoder 3 Bit Binary to 1 of 8
MC4006

Decoder 3 Bit Binary to 1 of 8
MC4006

Timing

Timing

0--,

Selection Line Driver.

Yl

Y2 Y3 Y4 Y5

Selection Line Drivers

Xl X2 X3 X4 X5 X6 X7 XB

Y6 Y7 YB

r-

'-

-

~

-

IXC5484174B4

I

~"

~
I'

l1'
----o

1 0

1

Sense Write

Bit 1

'" '"

~
"'-

i'\.

'\."1 ' "

." .."1

f\:

ll'
h'
-------- -------o

1 0

1

Sense Write
Bit 2

o

1 0

1

Sense Write
Bit 3

~
'."\ "\l f'(
..

o

l1'

-------1 0

1

Sense Write

8it4

.

~_____________________M_E_M__O_R_IE_S__~

MCM4002

256-BIT
READ ONLY MEMORY

256-BIT READ ONLY MEMORY
The MCM4002 is a monolithic 256·bit Read Only Memory (ROM)
that can be programmed for custom requirements. The basic organi·
zation of the memory is 32 eight·bit words, with each bit initially in
the logic "0" storage state established by the metal intraconnection.
By removing appropriate metal links on the device metalization,
these bits can be changed to the logic "1" state to meet specific
program requirements.
The MCM4002 also features optional 2.0 kilohm pul/up resistors
on the eight collector outputs. The open collector output option is
obtained by removing metal links to the 2.0 kilohm resistors on the
device metalization. Utilizing the open collector option at the buf·
fered output bit lines al/ows several memories to be "Wire ORed" to
form large arrays. In these cases an external pul/up resistor must be
connected from the open col/ector outputs to VCC.
The ROM truth table and the pul/up/open col/ector design options
are specified by the ordering information on a customer data card as
shown in this data sheet. The "scribe·it·yourself" feature al/ows the
design engineer to breadboard his pattern prior to submitting his final
design for production by Motorola, thljsminimizing costly design errors.

FEATURES:

_

.

PSUFFIX
PLASTIC PACKAGE

LSUFFIX
CERAMIC PACKAGE
CASE 6:(0

• • .
. - .

CASE 648

15

Enable

10

AO

B1

11

A1

B1

11

AZ

63

13

A3

B4

14

A4

B5

60

66

• Positive Logic for Both Inputs and Outputs:
Logic "0" = Output Device ON (VoLl
Logic "1" = Output Device OFF (VOH)
•

Logic Levels Compatible with MDTL and All
MTTL Families

• Address Times < 50 ns

67
VCC"'Pin16

GND '" Pin 8

UNPROGRAMMED MCM4002 ARRAY

• Outputs Sink 12 mA Open Col/ector, 10 mA with
Pul/up Resistors.
• Configuration al/ows mechanical programming ("scribe·
it·yourself") to verify pattern before processing

APPLICATIONS:
•

Look Up Tables

• Micro Programs
• Decode Functions
• Code Conversion
• Number Conversion
•

Random Logic

• Character Generation

I

MCM4002 (continued)

DESIGNING A CUSTOM FUNCTION FROM THE
MCM4002 READ ONLY MEMORY
A custom function may be designed with the MCM4002 by defining whether metalization links on the memory array should be
removed or left in place. The memory is originally programmed
with logic "O's" and with 2_0 kilohm pullup resistors on the collector
outputs. Logic "1's" may be programrred into the array by remov-

ing metalization links from the pattern. Open collectors may also
be programmed into the array by similar means. The following pro-

3. Scribe the pattern into the breadboard device.
Method A:

guide to placement of the metalization links.
Method B:

cedure ;s suggested for obtaining the f;nal, correct design.
1. Define tha required truth table, using the format shown in
Figure 1.
2. Select the output option desired:

either 2.0 kilohm pullup

Purchase lidless device from Motorola and
"scribe-it-yourself." Use Figures 2 and 3 as a

Purchase custom-scribed lidless device from
Motorola or selected Motorola franchised dis-

tributors.
4. Order custom function for production by following ordering

information on this data sheet.

resistors, or open collectors.
FIGURE 1 - TRUTH TABLE FORMAT
WORD 0
WORO 1
WORD 2
WORD 3
WORD 4
WORD 6
WORD 6
WORD 7
WORO 8
WORD 9
WOR010
WORD 11
WORD 12
WORD 13
WOR014
WORD 15
WORD 16
WORD 17
WORD 18
WORD 19
WORD 20
WORD 21
WORO 22
WORD 23
WORD 24
WORD 25
WORD 26
WORD 27
WORO 28
WORD 2JJ
WORD 30
WORD 31

-I

LSUFFIX
CERA.MIC PACKAGE
CASE 6.20

1'"'1 ~'I'"

I'"I"" l,rr'I"ll

PSUFFIX
PLASTIC PACKAGE
CASE 648

MCM4002 (continued)

FIGURE 2 - PASSIVATION MASK

The passivation mask indicates not only the positioning of the
metalization links for the ROM, but also defines bonding pads and
pullup resistor links. This figure, with Figure 1, should be used to
determine links to be removed in programming the memory.

Outputs must be specified as having either

••• ·. .•
PIN I (60)

•

PIN2
IB1)

•

PIN3
IB2)

•

PIN5
IB4)

•

PIN6
IB5)

..
•••
•• ••
PIN 7
IB6)

•

pullup resistors

•

PIN 15
IENABLE)

··..··..··..
··..·.·.
··.. ·.
·• .• ··..• • ·.
·.·. •• .• ·• .•
··.. • • ·.··..
·• .• ··..·• .• ··..
·• .• •• •• ·• .• ·• .•
·• .• •• •• ··.. • •
·• .• ·• .• ·• .• ·• .•
·• .• ·• .• ··..·• .•
·.• • ·• .• ··..
·• .• ·•• .•• ···...···...

I:
•

PIN 161Vee)

••
•• ~
BITOOF/' • • • • • • •
BIT 7 OF
WORO 0
• • WORO 0
••
•• •• •• ••
•• ••
••
••
•• ••
I:
•• •• ••

.PIN4
IB3)

!ill

or 2!! open collectors. Pullup resistor and open collector options
cannot be mixed on an individual chip.

PINI4 •
1A4)

I

PINI3.
IA3)

PINI2.
IA2)

"
"

/. • • • • • •

.•

"BIT 7 OF
WORO 31

BIT 0 OF
_ WORO 31
PIN B
(GNO)

•

PIN 9
IB7I

PIN 10
lAO)

.:.

*Metalization links which connect optional 2.0 kilohm pullup resistors to outputs.

PINll.
IA1)

•

MCM4002 (continued)

ORDERING INFORMATION
After the memory bit pattern is established by the user, the
explains how truth table information is converted from the binary
bit pattern to the hexadecimal numbering system. This is done to

The punched card provides the mask~making instructions utilizing Computer-Aided Design Techniques. This card accompanies
the manufactured parts to the Final Test and Quality Control
areas. Motorola's automatic testing facility compares the function
of the completed memory'circuits with the program specified on

accommodate most computer equipment presently in use for best

the card, and tests the input-output electrical characteristics.

information is transmitted to Motorola by supplying punched cards

(rectangular punched holes) as described in Figure 3.

Figure 4

user-supplier interfacing and to obtain standard Hollerith punch

throughout the card.
FIGURE 3 - PUNCHED CARD FORMAT
Two cards are required' card 01 defines words 0 thru 15 card 02 defines words 16 thru 31

Output Option:
Open Collectors Use BAA
2.0 kilohm Pullup
Resistors - Use BBA

Motorola Program
Identification; Fixed
- Use MKRS2

Each a·blt ROM word is expressed as two hexadecimal numbers - Bits 7, 6, 5, and 4 determine
the first hexadecimal digit and bits 3, 2, 1, and 0
determine the second (see Figure 5).

Part Number

I

1617 18 19 20 21 22 23 24 25 26 27

o 11

Revision

10

IIIIJ I

(Obtain

Number on Card 2

Customer Part Number

AAAAA ~8-C84::,2

Device
Marking

Word Number

Customer Identification Code
(Obtain from Motorola Sales Office)

/' MKRSc

Number
of Cards
Card
Number

ROM Words

I 2 I 31

41 51 6

I 71 81 9

a

293031

110 111 12 113114 15

Office I

-02 -02

fIl lJHHHr In i~; iH
BBA :~3'f~91~"r;40~Ol~EfA l~lt:f'(

J

from
Motorola
Sales

fj

BOTH (HOE.

:::100000000:0000000000000100000000000000000000000010100000000000000 000:1001010
12345'111111112I3M15I111111120%l22232425

27212130313233

353831

)40442

447

51

5354

51 I!! 01112

15

11111

11121n475

Jl

II

11111111111" , 11 , "1111111"1111'111111111'1111111'11111111111111111111111111111
21211222221222222122222222222222221122222122122222222222222222211222222122222221
3333333333333133333333333333333333333331333333133.33333.333333133.33333331333333
14444444444444414444444444444444444444444444444114444444414414444444444444444444
55555555555555551555555555555555555555155511555555555555555551555555555555555555
66666666666666666666666666666666666661666666666666661666166666666661166616666666

111171111711171117177717771111111111111111111111111777777717111771171~1717117117
8888 8 sa 8.88188 Is 8 8 8 888888888888888888.888888888 a8 8 I. 8 818 8 a8 8 8 8 8 88 8 8 8 88 8 88 8188.88
89199989999999999999999999999999999999991999999999999999999999999]99999999999999

' - t:l 3 4 5 ' ~ 1~!:ZI3MJ5~T~~:~~~);~,2ii212'29H31S23334]53637S13940414243444S414J484t$D5t525354S5S8S1511i'&oI1I2I3646&166168"lOnn1SJ415J1n}l1t~

•

FIGURE 4 - ROM WORD PROGRAMMING FORMAT FOR PUNCHED CARD

BINARY TO HEXA·
DECIMAL CON·
VERSION TABLE
INPUT (AI

OUTPUT (BI

43 2 1 0 7 .6 5 4 3 2 1 0
Word

0
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15

000001 1 1 1 1 1
o 0 0 0 1 00 1 1 1 0
o0 0 1 0 o 0 1 0 0 1
o 0 0 1 1 11 1 o 0 0
00 1 o 0 0 0 0 1 0 0
o0 1 o 1 1 1 o 1 o 1
o 0 1 1 0 ·1 1 o 0.1 0
o 0 1 1 1000011
0 1 0 o 00 o 0 0 0 0
0 1 o 0 1 1 1 0 0 0 1
0 1 o 1 o 1 1 0 1 1 0
0 1 o 1 100 0 1 1 1
0 1 1 o 0 1 1 1 o 1 1
0 1 1 o 1 o 0 1 o 1 o
0 1 1 1 o 0 0 1 1 0 1
0 1 1 1 1 1 1 1 1 0 0

CARD
COLUMN

--

COL 38 COL 39

BINARY
CARD
DATA CHARACTER

1 0 . . Transfer to 38 and 39 a s F and e (1111 11101 using conversion table o 0 0 0
o 1
40 and 41
00 0 1
00 1 0
o 1
42 and 43
00 1 1
44 and 45
1 0
0 ·1 o 0
1 1
46 and 4'7
0 1 o 1
48" and 49,
o0
50_and 51
0.0
O. .1 1 0
62 and.53
1·1
0 1 1 1
1 o 0 0
o 1
54 and 55
1 o 0 1
1 0
56 and 57
1 o 1 0
1 0
58 and 59
1 o 1 1
o 1
60 and 61
1 1 0 0
0 0
62 and 63
Note: Words 16 thru 31
1 1
64 and 65
1 1 0 1
transfer to card 02
1 1 1 0
1 1
66 and 67
in the same manner.
1 1 1 1
0 0
68 and 69

0
1
2

3
4
5
6
7
B
9
A
B

C
0
E
F

MCM4002 (continued)
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vec

-0.5 to +7.0

Vde

Input Voltage

Vin

-1.5 to +5.5

Vde

Output Voltage (Open eollectors)

VOH

-0.5 to +7.0

Vde

Rating

Operating Temperature Range
Plasti~

Package
Thermal Resistance, Junction to Ambient (Typical)

Ceramic Package

Thermal Resistance, Junction to Ambient (Typical)

Storage T emperatu re

TA

o to +75

°e

9JA

200

°e/w

TA

-55 to +125

°e

9JA

95

°e/w

T stg

-55 to +125

De

ELECTRICAL CHARACTERISTICS (Plastic Package, T A" oOe to 750 e unless otherwise notedl
Symbol

Min

Max

Unit

IF

-

1.6

mAdc

IR

-

·100

gAde

Open Coilectors

-

0.45

Pullup Resistors

-

0.45

2.5

-

-

200

-

80
95
65

Characteristic
InpLAt Forward Current

(Vin ~ 0.4 Vde, Vee ~ 5.25 Vde)
Input Leakage Current

(Vin ~ 4.5 Vde, Vee ~ 5.25 Vde)
Logic "0" Output Voltage
(10 ~ 12 mAde, VIL" 0.8 Vdc, VIH" 2.0 Vde,
VEnable: 0.8 Vde, Vee~ 4.75Vdel
(to" 10 mAde, VIL ~ 0.8 Vdc, VIH" 2.0 Vde,
VEnable: 0.8 Vde, Vee: 4.75 Vdc)

Vde

VOL

Logic "1" Output Voltage
(IOH ~ -0.5 mAd,e, VI L " 0.8 Vde, VIH " 2.0 Vde,
VEnable ~ 2.0 Vde, Vee" 5.25 Vde)

Vdc

VOH
Pullup Resistors

Output Leakage Current
(Vout ~ 5.25 Vdc, VEnable" ~.O Vde, Vee ~ 5.25 Vdel

leE

x

Open Collectors

Power Supply Drain Current
(Memory Enabled, VEnable" 0 Vde,Other Inputs" 0 Vde,
Vee: 5.25 Vde)
(Memory Disabled, VEnable: 2.0 Vde, Other Inputs ~ 0 Vde,
Vec " 5.25 Vdcl

/.lAdc
mAde

Ice
Open Collectors
Pullup Resistors

-

ELECTRICAL CHARACTERISTICS (Ceramic Package, T A" -55 0 e to +1250 e unless otherwise notedl
Symbol

Min

Max

Unit

IF

-

1.6

mAde

IR

-

100

/.lAde

Open Collectors

-

0.45

Pullup Resistors

-

0.45

2.5

-

-

200

-

80
95
65

tE+B+

-

50

ns

Characteristic

Input Forward Current

(Vin ~ 0.4 Vde, Vee: 5.5 Vde)
Input Leakage Current
(Vin : 4.5 Vde, Vee ~ 5.5 Vdcl

Logic "0" Output Voltage
(10 ~ 12 mAde, VI L : 0.8 Vdc,
VEnable" 0.8 Vdc, Vce: 4.5
(10 ~ 10 mAdc, VIL: 0.8 Vde,
VEnable" 0.8 Vde, Vee" 4.5

Vde

VOL
VI H : 2.0 Vde,
Vde)
VIH" 2.0 Vdc,
Vdel

Logic '1" Output Voltage
(lOH: -0.5 mAde; VIL~ 0.8 Vdc, VIH" 2.0 Vdc,
VEnable ~ 2.0 Vdc, Vee ~ 5.5 Vdc)

Vdc

VOH
Pullup Resistors

/.lAde

ICE'X

Output Leakage Current
Open Collectors

(Vout ~ 5.5 Vde, VEnable: 2.0 Vde, VCC: 5.5 Vdc)
Power Supply Drain Cur,rent

SWITCHING TIMES (Both Packages, VCC" 5.0 Vdc, T A

mAOe

Ice

(Memory Enabled, VEnable ~ 0 Vde, Other Inputs: 0 Vde,
Vce ~ 5.5 Vdc)
(Memory Disabled, VEnable" 2.0 Vde, Other Inputs" 0 Vde,
V ee ~ 5.5 Vde)

Open Collectors
Pullup Resistors

-

~ 25 0 el (see Figure 5)

Enable Input

Turn-Off Delay Time
Tu'rn-On Delay Time

tE-B-

.,...

50

ns

Address Input

Turn-Off Delay Time

tA+B+ or
tA-B+

-

50

ns

Turn-On Delay Time

tA+B- or
tA-B-

-

50

ns

MCM4002

(continued)

FIGURE 5 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

Vee
5.0 Vdc

PULSE
GENERATOR

~·r

Enable

80

AO

81

Al

82

A2

83

A3

84

A4

85

470

86
87

V1HX 3.0 V

Enable Input Test: Connect data inputs to VIHX.
Address Input Test: Inputs not under test left open.
High impedance probes must be used when making these measurements.

5.0 os max

5.0 os max

3.0 V

TPin
Enable
Input

OV

5.0nsmax

5.0 os max

3.0 V

TP;n
Address
Input
OV

~

TPout

tA-8-

T~o!Jt

'\

MEMORIES

MCM4064AL ~----------I
MCM4064L

Advance Infor:rnatton/New Product

MTTL

64-BIT RANDOM ACCESS MEMORY

64-BIT
RANDOM ACCESS
MEMORY

The MCM4064AL/4064L is a 64-Bit random access memory
organized as a 16-word by4-bit array_ Schottky-diode-clamped
transistors are utilized to obtain fast switching speeds, and Schottky
clamp diodes are used on all inputs to provide minimum line reflection_ The high speed of this memory makes it ideal in scratch pad
operation_
Address decoding is incorporated in the circuit providing 1-of-16
decoding from the four address lines_ Separate Data In and Data Out
lines, together with a Chip Enable, provide for easy expansion of
memory capacity _ A Write Enable is provided to enable data presented at the Data In lines to be entered at the addressed storage
cells_ When writing, Data Out is the complement of the Data In_
The open-collector output transistors are also Schottky barrier
devices and combine greater current sinking capability with lower
leakage currents, thereby increasing the wire-or capability of these
devices.
Features:
• Both Minimum and Maximum Access Times Specified
• Binary Addressing
• Chip Enable for Memory Expansion
• Outputs May Be "Wire ORed"
• Logic Levels Compatible with MDTL and All MTTL Families
• Low-Voltage Input Clamp Diodes
• Access Time < 60 ns
• Power Dissipation Typically 6 mW/bit
• Outputs Sink 15 rnA

MCM4064AL
CAS~

638

MCM4064L
CASE 620

MAXIMUM RATINGS
Symbol

Va1ue

Supply Voltage

VCC

7.0

Vdc

Chip Enable 2

CE

Input Voltage - All Inputs

Vin

5.5

Vdc

WriteEfNtble 3

WE

Output Voltage - All Outputs

Vo

5.5

Vdc

Addrass 0

AO

Output Current

10

100

mAde
Address 1

15

A1

TA
9JA

Oto +85
80

°c
°CIW

. Address 2

14

A2

Address 3;

13

A3

8JC

45

°CIW

Data In 1

D1

MCM4064L (Case 620)
Thermal Resistance, Jun"ction to
Ambient (Typical)

Dataln 2

Oto+70
110

°c
°CIW

D2

TA
9JA

Thermal Resistance, Junction to

8JC

60

°CIW

T stg

-65 to +160

°c

Rating

Unit

Operating Temperature Range

MCM4064AL (Ca.. 638)

Thermal Resistance, Junction to
Ambient (Typical)
Thermal Resistance, Junction to

Ca.. (Typical)

Dataln 3
Dataln 4

'"
t2

03
04

case ITypical)

Storage Temperature Range

Vee'" Pin 16
GND==Pin B

5

0ata0iii 1

7

Data Oul2

9

081&Out3

11

Data OUI4

MCM4064AL, MCM4064L (continued)

DC ELECTRICAL CHARACTERISTICS (MCM4064AL: (TA = a to +850 C, Case 638;
MCM4064L:

TA =

a to +100 C, Case 620)
Symbol

Min

Typ

Max

Unit

IF

-

-

1.6

mAdc

Input Leakage Current - All Inputs
(VIH = VCC = 5.25 Vdc)

IR

-

-

80

"Adc

Input Clamp Voltage - All Inputs
(lin = -5.0 mAdc, VCC = 4.75 Vdc)

Vc

-

-

-1.0

Vdc

VIL
VIH

-

-

0.8

2.0

-

-

Logic "0" Output Voltage - All Outputs
(Vec = 4.75 Vdc, IOL = .15 mAdc)

VOL

-

-

0.45

Vdc

Output Leakage Current - All Outputs
(VCC = VCEX = 5.25 Vdc)

ICEX

-

-

100

"Adc

Power Supply Current
(VCC = 5.25 Vdc, all inputs except WE grounded)'

ICC

-

-

105

mAde

Input Capacitance - All Inputs
(Vin =,2.0 Vdc, VCC = 5.0 Vdc)

Cin

-

6.0

-

pF

Cout

-

8.0

-

pF

Symbol

Min

Typ

Max

Unit

tA+8+
tA-8-

15
15

-

60
60

ns

tA+8-

15

-

60

tA-8+

15

60

tCE+8+

15

-

tCE-8-

15

-

60

Write Pulse Width (See Figures 1 and 3)

twp

40

-

-

ns

Write Recovery Time (See Figures 1 and 3)

Iwr

-

50

ns

tHAW

5.0

-

-

ns

Characteristic
Input Forward Current - All Inputs

(VIL = 0.4 Vdc, VCC = 5.25 Vdc)

Vdc

Input Logic Levels - All Inputs
"0" Level
(VCC = 5.0 Vdc)
"1" Level

Output CapaCitance - All Outputs
(Vout -- 2.0 Vdc, VCC - 5.0 Vdc)

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, TA = 250 C)
Characteristic
Access Times - Address Input or Chip Enable to Output Delay.
(See Figures 1 and 2)

Address and Data Hold Time After Write (See Figures 1 and 3)

60

·Worst-case de input condition.

BLOCK DIAGRAM
16 WORDS OF 4 BITS
STORAGE ARRAY
CHIP
ENABLE

CE
AD

"",w{
LINES

15
14
13

Al
A2

ADDRESS
DECODER
1 OF 16

A3
15

04

DATA
INPUT
LINES

r

WRITE
ENABLE

11

03

10

6

02

82

Bl

VCC = Pin 16, GND = Pin 8

QATA
OUTPUT
LINES

MCM4064AL, MCM4064L

(continued)

FIGURE 1 -SWITCHING TIME TEST CONDITIONS AND LOAD CIRCUIT

Vee = 5.0 Vdc, TA = 250 e

INPUT WAVEFORM
3.0>.0.5

LOAD CIRCUIT

v----------r----

Vee
300

-5.0 ns max

600

30 pF

FIGURE 2 -ACCESS TIME DEFINITIONS
CHIP
ENABLE

ADDRESS - - - -.. 1

ADDRESS - - - - - ' 1
DATA
OUT
CDThistfimlllJiol) is rnaasured from ttJ,llIIId ctlltan
at theteating pllnewith leads YfrtICII.

cr> ....d 1 identifiad by l;OIor dol. notch in lead.
or notch inca'imic.

CASE 620

FIGURE 3-' WRITE TIME DEFINITIONS
CE

a::r::I,
~D.815~
..... a:m .

HIl L

I-D.275~

WE---~-----~

10JiS1

IV VJVlU UITJID.~D.l60
IT
t.~

..98 1 I

o:m+---l

DATA
OUT

I

D.D45
IJli5II

tT'

t-i[i'if9

TVP

CASE 638

I

D.300

I

I-- REf;--i

MCM4064AL, MCM4064L

(continued)

TYPICAL ACCESS TIMES
ADDRESS TO OUTPUT

CHIP ENABLE TO OUTPUT

FIGURE 4 - VARIATIONS WITH SUPPLY VOLTAGE
70

]
I-

:::>

1=
:::>
'"

'"

I-

~

."'"
'"
;..

60

50

,...
1,... ' --

FIGURE 7 -VARIATIONS WITH LOAD CAPACITANCE

I~L=15mIA-

!

CL=30pF
TA=25 0 C -

1=:::>

40

r-

I-

:::>

60

'"'"

.

w

....
'"z

50

...
w

t-+

t++

;:::

40

..

30

~

30

1--

5w'
'"
;:::

t++

20
5.0

4.75

5.25

5.5

o

FIGURE 5 - VARIATIONS WITH LOAD CAPACITANCE

~
""
ui

.

-.

-,...,.,..

1--1+-

40

.

30 t--t++

-

r--

~
~ /""

......

..........

50

~

'"'"

......

I-

.....'"

w

....

50
I--

w

.-V

%
<..)

VCC = 5.0 VdcIOL=15mA
TA=25 0 C -

100

1

40

1e

'";:::

..

VCC = 5.0 Vdc
10L = 15 mA
CL=30pF

SO - I - -

9..

I-

~.

I
I
I

30

I
I

20
25

50

75

I

--+
I

I
I

30

50

:I

40

:
-lI

]
:z:
le

~
~

1e
w

I

I-

I

,:

I

1++

WRITE RECOVERY
30

~

ffi

I

I

WRITE PULSE WIDTH
20

I
I

10

VCC = 5.0 Vdc ----1
IOL=15mA
I

>

I
I

'"a:fil

I

l-

I

~

w

I

ii:

1=30 PF.--+
I

1

20
25

B5

FIGURE 9 - TYPICAL WRITE RECOVERY AND
WRITE PULSE WIDTH versus TEMPERATURE

t+-

40 I- 1-+

'";::

I
I

1++

I

200

t

:::>

'"'"
!iia:
""ui
l-

I

TA,AMBIENTTEMPERATURE (DC)

70

I-

I

~

ui

FIGURE 6 - VARIATIONS WITH TEMPERATURE

60

I-

~

4

<..)

150

]

-

60

z

I'

o

1=
:::>

CL, LOAD CAPACITANCE (pF)

I-

VCC =1 5.0 Vdc
10L = 15 mA
CL=30pF-

:::>

SO

20

200

FIGURE 8-VARIATIONSWITH TEMPERATURe

I-

60

I--- 1-+

1$

150

100

]

'";:::

!ii

L

70

]

'"'"
l-

I

CL, LOAD CAPACITANCE (pF)

70

1=
:::>

VCC = 5.0 Vdc_
10L = 15 mA
TA=25 0 C -

I--"'"

50

VCC, SUPPLY VOLTAGE (VOLTS)

:::>

.,....,....- V

,...,.,..

<..)

20
4.5

I-

.....

..........

I-

1- ' +-

w'

70

50

TA, AMBIENTTEMPERATURE (OC)

75

85

25

50

TA, AMBIENTTEMPERATU RE (DC)

75

B5

MCM4064AL, MCM4064L (continued)

TYPICAL DC CHARACTERISTICS
FIGURE 10 - TYPICAL SUPPLY CURRENT
versus TEMPERATURE

FIGURE 11 - TYPICAL OUTPUT LOW VOLTAGE
versus OUTPUT CURRENT

110

:
I

Vcc = 5.25 Vdc

;;

I

100

I

.g

I

....

~
'"~

I

I

90

I

I
I

~ 80

I

it

I

ijl

03

52 70

I
I
I
I
I

60

o

75

50

25

o. 5

~o

-:::: ~

0.4

1

to

~

0.3

~~

o

>

~
....
::>
:=::>

0.2

::::.-::: ::::--r----==
--:: ::::=-:::: ~

TA =ooc

~
w

Vcc = 5.0 Vdc

/ f-T
25 0 C

85 0 C

~ O. 1
o
>
5.0

85

10

15

20

lout, OUTPUT CURRENT (rnA)

TA, AMBIENT TEMPERATURE 10C)

APPLICATIONS INFORMATION
The MCM4064 64-bit MTTL RAM has several features which

should be considered when designing larger systems with this device.
1. Chip Enable - This input essentially turns off the device
when intii'e high state. The chip will neither read out nor write in
data when disenabled. The open collector 'output devices allow
Wire GRing or phantom logic for expansion into larger systems.

Graphs in this data sheet show the relationship between
and capacitance onJthe output due to"Wire DRing.

~cesstime

2. Write Enable - The WE input gates the data on the data
input leads into the memory cells. The output amplifiers are tied

directly to the. write amplifiers and follow as the inverse of the input for either state of CE as long as WE is low. There is, however,
a "glitch" on the output lines just after WE returns high or goes
low. For proper writing into the memory, the address and data
hold time after writing (tHAW) must be greater than 5.0 ns.
3. The address inputs have standard TTL-compatible input
thresholds and standard TTL loading rules can be used.

The data outputs have open-collector, Schottky-clamped transistors and can be wire ORed with the incumbent cost in propagation delay. Typical output capacitance is specifiec;l for aid in
system design.
Figure 12 shows a typical system desiQn using TTL logic and
the MCM4064 as a main frame store. This figure will be used to dis-

cuss several design considerations.

.

The four address inputs of tbe MCM4064 are common to all

devices in the system.

The gates driving these addresses have a

fanout of eight, which is a typical and reasonable TTL fanout. In

the diagram, each address driver shown represents four devices, one
for each address. Thus, 8 x 4 or 32 inverters are required for
address driving.
The chip enable inputs are used for further address expansion
and a one-of-eight decoder (MC4006) is used ·for selecting one chip
of eight with Wired OR outputs. Again a TTL fanout of eight is
used. This chip enable decodings adds three address bits, A5, A6
and A7.

The memory chips are Wire-ORed in sections of eight. This
figure of eight is used as a trade-off in decoding array time versus
increase in access time due to output capacitance. The eight out-

putsat B.O pF each, plusan average of 5.0 pF for board capacitance
give a total of slightly.more than 100 pF for a total typical access
time (from Figure 5) of about 50 ns. Each section of eight memory chips is connected to a one-of-four data selector (MC4000)

which selects one of four sections. This adds a further two address
bits, AB and A9, for a total of 512 address locations. kone-of-

four decc)der is required for each data output and eight selectors.
or four MC4000 devices, are required for the system. Four selectors give output bits 01 through 04 and the second set provides
05 through 08 from a secolJd 8 x 4 array of memory devices.
The input data drivers shown in Figure 12 also represent .four
inverters, on~ for each data input bit, in the same manrier as the
addre~s d'rivers and output selectors. The input data is distributed
in common to both a x 4 memory arrays. The particular column
of eight MCM4064's for which the data is intended is selected by
the MC4007 data selectors which drive the write enable inputs .
Only one olthe eight MCM4064's in the columns will actually write

in this data and is selected by the chip enable input. Thus only
one device in the a:x 4 array will actually accept the input data: that
daVic'e chosen by the coincidence of the CE and WE lines.
The· entire system shown, therefore, constitutes a 51 ~-word by
a-bit memory and requires ~he following devices:
64 bit !TIemories
64
MCM4064
One~of-four data selectors
4
MC4000
One-of-eight decoders
1
MC4006
One-at-four decoders
MC4007
11
MC7404
Hex inverters
The system access time is the total of the input decoding times,
memor:Y access times, and output selection delay times~ However,
this may be decreased for read~read cycles by utilizing the maximum and minimum access times. Thus, if one changes the address
or chip enable inputs every 60 ns, there is at least 15 ns of valid
data on the memory output. Therefore, an output buffering
scheme which can latch up the memory contents within 15 ns
could be used to reduce the read-read access time to 60 ns plus
the address/chip enable skew times which are invariably present. A
similar technique could be used for read-write and write-write cycles.

•

•
- -....- - - - - - - 1 r - - - - AO.Al.A2.A3
- 1 - - - - 05,06,07,08

:s:
(")
:s:
~
o

~

»
r

-:s:
(")

s:
~

Write

o
~
r-

n-O
:l

:::!.

:l
I::

~

Note: R'" 300 ohms

A9
01,02,03,04

APPLICATION NOTE ABSTRACTS

The application notes listed in this section have been prepared to acquaint the circuits and systems
engineer with Motorola TTL integrated circuits and their applications. To obtain copies of the notes,
simply list the AN number or numbers and send your request on your company letterhead to: Technical
I nformation Center, Motorola Semiconductor Products Inc., P.O. Box 20924, Phoenix, Arizona 85036.

AN-464

MTTL Designer's Note - The MC4004/
MC4005, A 16-8it Random Access Memory

High speed, non-destructive readout (N DRO)
memory systems can be constructed with the MTTL
16-bit memory chip. Information concerning the
chip that is pertinent to the design of a complete
memory system is herein presented. The topics
discussed are: (1) operation of the 16-bit memory
including typical read and write sequences, (2) typical dc and Switching characteristics as a function
of temperature, power supply, and output load, and
(3) examples of memory system organization uti·
lizing the 16-bit memory as the basic cell.
AN-465

MTTL Designer's Note MC4007 Decoders

The MC4006/

Two MTTL complex functions, the MC4006
Binary td One-of-Eight Decoder and the MC4007
Dual Binary to One-of-Foour Decoder are discussed.
Their basic modes of operation and expansion capahilities are described. Examples of the use of the
decoders in various systems, are presented.
AN-476

MTTL Designer's Note ~ The MC4000 Data
Selector and the MC4002 Data Distributor

Two MTTL complex functions, the MC4002
four and two-channel data distributor, and the
MC4000 dual four-channel data selector are discussed. Their basic modes of operation and expansion capabilities are described. Examples of the use
of the data distributor and the data selector in various systems are presented.
AN-488

High-SpeedAddition Using Lookahead Carry
Techniques

The use of the lookahead carry principle to
increase the operating speed of adder systems is described. Several adders of different sizes using
variations of lookahead carry are developed and the
logical implementation of these using the MTTL III
and MECL II and III logic families is given.

AN-492

Operating Characteristics of Motorola
MC3000/MC3100 Series TransistorTransistor Logic Gates

This application note explains the advantages
of using the MC3000/MC3100 Series of conventional TTL. Design data is included which should
allow determination of the operating characteristics
under almost any setoof conditions.
AN-493 ,The MC3000/MC3100 Series TransistorTransistor Logic Flip-Flops
This application note explainsthe basic operation of the various flip-flops available in the
MC3000/MC31 00 series of transistor-transistor logic
from Motorola. Typical operating characteristics
are included so that operation under different conditions can be determined.
AN-494

The Motorola Transistor-Transistor Logic
Lines

This application note contains aogeneral description and comparison of Motorola's MTTL I,
MTTL II, MTTL III, MTTL 5400/7400, and the
MC4000 lines. The basic gate and the MTTL III
bypass circuit are discussed and tables of electrical
characteristics are included. Two appendices provide
definitions of common MTTL terms, a discussion of
the effect of input diodes, and loading rules for the
MC4000 series complex functions.
AN-496

Error Detection and Correction Using
Exclusive OR Gates and Parity Trees

The availability of Exclusive OR gates and
parity trees allows digital system designers to use
error detection and correction codes to improve
their system reliability and maintainability without
the major cost penalty that has existed in the past.
Use of Exclusive-OR gates and parity trees available
in the MRTL, MTTL, MDTL, and MECL families
to design simple parity and single error Hamming
parity detection and correction circuits is discussed.

I

APPLICATION NOTE ABSTRACTS (continued)

AN-505

The MC4012, An MTTL 4-Bit Shift Register

The MC4012 is a 4-bit shift register consisting of four D-type flip-flops operated in the synchronous mode and may be used for temporary
storage of information. The MC4012 may be operated in either the parallel or serial mode input
depending upon the logic state of the mode control.
Circuit operation and various applications of the
device are the subject of this application note.
AN-516

Direct Di'gital Display Using MTTL Complex
Functions

This application note examines some of the
different design methods for digital readouts with
the added circuitry advantage of integrated circuit
complex functions; in particular the MC5400/7400
series.
AN-528

Binary-To-BCD-To-Binary Conversion With
Complex IC Functions

Complex function integrated circuits reduce
the cost of performing conversion from binary to
the BCD code or from the BCD code to binary.
Four methods of performing each conversion are
discussed and compared.

AN-534

This note describes the design and construction of commutating (digital) filters using Motorola
MECL II, MTTL III and MC7400 digital integrated
circuits. A short section on commutating filter
theory is included along with examples of filters
and their responses.
AN-535

Operation of the MC5491A/7491A8-bitshift
register and the MC5495/7495 4-bit universal shift
register is discussed. Typical applications are covered
for each device and use of the two devices in a data
transmission system is illustrated.
AN-532

MTTL and MECL Avionics Digital Frequency
Synthesizer

This application note discusses several approaches that illustrate applications of complex
digital integrated circuits directed toward avionics
frequency synthesizers, The techniques presented
point out the simplicity with which both MTTL
and MECL digital integrated circuits can be used to
produce frequency synthesis for avionic communications.

Phase-Locked Loop Design Fundamentals

The fundamental design concepts for phase
locked loops implemented with integrated circuits
are outlined. The necessary equations required to
evaluate the basic loop performance are given in
conjunction with a brief design example.
AN-537

The MC4023, An MTTL 4-Bit Universal
Counter

The MC4023 Universal Counter can be connected to count any number from two through
twelve except seven and eleven. For all settings,
counting is in a binary sequence from count zero
to the selected number. Operating characteristics
and applications of the device are the subject of
this application note.
AN-539

AN-530A The MC7491A Eight-Bit Serial Shift Register
and the MC7495 Four-Bit Shift Register

Commutating Filter Techniques

Interfacing With MOS I/C's

This application note discusses the problem
of interfacing MOS integrated circuits with the logic
levels of MECL, MDTL, MTTL, and MRTL. The
emphasis is placed primarily on the use of other
integrated circuits to achieve this interfacing.
AN-541

Medium Scale Integration in the Numerical
Control Field

Since medium scale integration means complex functions, the logic design engineer must understand both the product and its end use in order
that his design be optimized. Transistor-Transistor
Logic has a number of devices such as programmable
counters, phase detectors, voltage controlled multivibrators, comparators, etc., which are available
today in integrated circuit form. The devices can
be applied to the numerical controls field and are
the subject of th is paper.

NOTES

NOTES

IGENERAL INFORMATIONI

ITECHNICAL DATA I
•

~. Interchangeability Guide

MC3100/MC3000 Series

~ Packaging Information

ISELECTOR GUIDES
•

MC4300/MC4000 Series

•

MC5400/MC7400 Series

I

MTTL Complex Function

•

MC5400/MC7400 Series

MTTL III MC3100/MC3000 Series

MC8200/MC7200 Series

•

MC9300/MC8300 Series

•

MTTL II MC2100/MC2000 Series

•

MCBC5400/MCB5400F Series

~

MTTL I MC500/MC400 Series

TTL Memories

~

Beam Lead MCBC5400/MCB5400F Series

_'APPLICATION NOTES

~

I

Dielectrically Isolated
MCE54HOO/MCE74HOO Series

MTTL Memories
6649 PRINTED IN USA !;-71 IMPERIAL LITHO 822538



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