1972_Motorola_Linear_Integrated_Circuits_2ed 1972 Motorola Linear Integrated Circuits 2ed

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MOTOROLA

Selniconductor Products Inc_

mBBmmBBmmBBmmBBmmBBm

LINEAR
INTEGRATED CIRCUITS

DATA BOOK
~~~~~~~~~~

I GENERAL INFORMATION I
Master Index

Product Highlights

Selector Guides

Previews of Upcoming Linear
Integrated Circuits

•
•
•
•

Interchangeability Guide

Nonencapsulated Device
General Information

I DATA SHEET SPECIFICATIONS I
... in alpha-numerical sequence by
device type number. unless otherwise
noted. (See Master Index j(Jr page numbers.)
Packaging Information

•

I APPLICATION NOTES I •

LINEAR
INTEGRATED CIRCUITS

DATA BOOK
Linear Integrated Circuits have achieved a level of maturity which now rivals that of
their digital counterparts. In all market categories and for a wide variety of applications
functions, linear ICs are serving the needs of equipment manufacturers to reduce cost
and improve equipment form,factor and reliability.
They've matured, too, from the standpoint of availability. The number of off-theshelf linear circuits and their varying capabilities makes them highly useful as building
blocks for system design. Moreover, the now-prevalent practice of second sourcing
assures competitive pricing and quantity delivery.
The Motorola Semiconductor Products Division has been in the forefront of linear IC
development since the inception of integrated circuit technology. This Linear Integrated
Circuit Data Book, therefore, contains data sheets for one of the largest selections of
linear ICs in the industry. Included are devices that were developed by the various
Motorola R&D groups, as well as an extensive second-source inventory of the most popular
circuits developed elsewhere. In addition, some of the linear ICs available as packaged
units are also sold in the form of unencapsulated "chips", encompassing conventional
chips (MCC prefix), beam-lead chips (MCBC prefix) and flip-chips (MCCF prefix). The
chips described by data sheets included in this book are available as standard, off-the-shelf
product. Other Motorola manufactured linear circuits can be obtained as conventional
chips (designed for conventional wire bonding) on special order.
For easy reference, the data sheets in this book are in alpha-numeric sequence, without
regard as to product category or applications. However, to provide the user with a quick
overview of Motorola's complete line of standard linear ICs, the General Information
section (Section I) contains a number of selector guides in which the total line has been
split up into market and functional divisions. This provides a quick comparison of similar devices, spelling out the most significant differences. Other useful data included in
the General Information section consists of cross-reference tables of second-source devices
and other product-related information.
The information in this book has been carefully checked and is believed to be reliable;
however, no responsibility is assumed for inaccuracies. Furthermore, this information
does not convey to the purchaser of microelectronic devices any license under the patent
rights of any manufacturer.

Second Edition
December, 1972
©MOTOROLA INC., 1972

The following are trademarks of Motorola Inc.:
MDTL, MECL, MHTL, MRTL, MTTL

LINEAR INTEGRATED CIRCUITS
MASTER INDEX

Device Type
Number
MC1303
MC1304
MC1305
MC1306
MC1307
MC1310
MC1311
MC1312
MC1313
MC1314
MC1315
MC1326
MC1327
MC1328
MC1330
MC1339
MCl344
MC1345
MCl349
MC1350
MC1351
MC1352
MC1353
MC1355
MC1357
MC1358
MC1359
MC1364
MC1370
MC1371
MC1375
MCl391
MCl398
MC1406
MC1410
MC1414
MC1420
MC1430
MC1431
MC1433
MC1435
MC1436
MC1436C
MC1437

Circuit Function Description
Dual Stereo Preamplifier
FM Multiplex Stereo Demodulator
FM Multiplex Stereo Demodulator
1/2·Watt Audio Amplifier
FM Multiplex Sterllo Demodulator
Stereo Demodulator
FM Stereo Demodulator
Four·Channel SQt Decoder
Four·Channel SQ Decoder
CBS SQ Logic Circuit
CBS SQ Logic Circuit
Dual Doubly Balanced Chroma Demodulator with RGB
Output Matrix
Dual Double Balanced Chroma Demodulator with RGB
Output Matrix and PAL Switch
Dual Doubly Balanced Chroma Demodulator
Low·Level Video Detector
Dual Low·Noise Stereo Preamplifier
TV Signal Processor
TV Signal Processor
IF Amplifier
I F Amplifier
TV Sound Circuit
TV Video IF Amplifier
TV Video IF Amplifier
Limiting FM IF Amplifier
I F Amplifier and Quadrature Detector
TV Sound IF Amplifier
TV Sound System
Automatic Frequency Control
TV Chroma Subcarrier Regenerator
TV Chroma I F Amplifier
FM IF Circuit
TV Horizontal Processor
TV Color Processing Circuit
Six·Bit Multiplying Digital·to·Analog Converter
Video Amplifier
Dual Differential Comparator
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Dual Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier

tTrademark of Columbia Broadcasting Systems, Inc.

1-1

Selector Guide
(Section 3) or
Circuit Previews
(Section 4)
Page No.

Data Sheet
Page No.
(Section 7)

3·14
3·14
3·14
3·14
3·14
3·14
4-4
3·14
3·14
4-4
4-4
3·13

7·1
7·5
7·5
7-9
7·14
7·18
7·22
7·22
7·25

3·13

7·31

3·13
3·13
3·14
4·3
3·13
3·13
3·13,3·14
3·13
3·13
3·13
3·14
3·13,3·14
3·13
4·3
3·13
3·13
3·13
4-4
4·3
3·13
3-8
3·11
3-8
3·1
3·1
3·1
3·1
3·2
3·1
3·1
3·2

7·35
7-40
7·44
7-49
7·55
7·60
7·64
7·68
7·68
7·74
7·78
7-84
7-89
7·93
7·99

7·104
7·126
7·138
7·110
7·140
7·150
7·150
7·154
7·159
7·164
7·164
7·168

•

MASTER INDEX (continued)

Device Type
Number
MC1438
MCl439
MC1440
MC1441
MC1444
MCl445
MCl446
MC1454
MC1456
MC1456C
MC1458
MC1458C
MC1460
MC1461
MC1463
MC1466
MC1468
MC1469
MCl488
MCl489
MCl489A
MC1494
MC1495
MCl496
MC1504
MC1506
MC1507
MC1508
MC1510
MC1514
MC1520
MC1530
MC1531
MC1533
MC1535
MC1536
MC1537
MC1538
MC1539
MC1540
MC1541
MC1543
MC1544
MC1545
MC1546
MC1550
MC1552
MC1553
MC1554
MC1555
MC1556

Circuit Function Description
Power Booster
Operational Amplifier
Core-Memory Sense Amplifier
Sense Amplifier
AC-Coupled 4-Channel Sense Amplifier
Wideband Amplifier
Plated-Wire Sense Amplifier
1-Watt Power Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Positive Voltage Regulator
Positive Voltage Regulator
Negative Voltage Regulator
Voltage and Current Regulator
Dual ± 15-Volt Tracking Regulator
Positive Voltage Regulator
Quad MDTL Line Driver
Quad MDTL Line Receivers
Quad MDTL Line Receivers
Four-Quadrant Multiplier
Four-Quadrant Multiplier
Balanced Modulator-Demodulator
Quad Current Switch
Six-Bit Multiplying Digital-to-Analog Converter
A-to-D Converter Subsystem
Eight-Bit D-to-A Converter
Video Amplifier
Dual Differential Comparator
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Dual Operational Amplifier
Operational Amplifier
Operational Amplifier
Power Booster
Operational Amplifier
Core-Memory Sense Amplifier
Sense Amplifier
Dual Sense Amplifier
AC-Coupled 4-Channel Sense Amplifier
Wideband Amplifier
Plated-Wire Sense Amplifier
RF-IF Amplifier
Video Amplifier
Video Amplifier
1-Watt Power Amplifier
Adjustable Timer
Operational Amplifier

1-2

Selector Guide
(Section 31 or
Circuit Previews
(Section 41
Page No.
3·2
3-1
3-4
3-4
3-4
3-11
3-4
3-12
3-1
3-1
3-2
3-2
3-9
3-9
3-10
3-10
3-10
3-9
3-5
3-7
3-7
3-12
3-12
3-12
4-5
3-8
4-5
4-5
3-11
3-8
3-1
3-1
3-1
3-1
3-2
3-1
3-2
3-2
3-1
3-4
3-4
3-4
3-4
3-11
3-4
3-11
3-11
3-11
3-13
4-2
3-1

Data Sheet
Page No.
(Section 71
7·172
7-178
7-186
7-190
7-205
7-213
7-219
7-239
7-243
7-243
7-249
7-249
7-253
7-253
7-265
7-281
7-291
7-297
7-114
7-120
7-120
7-362
7-376
7-392

7-126
7-138
7-142
7-146
7-150
7-150
7-154
7-159
7-164
7-168
7-172
7-178
7-186
7-190
7-198
7-205
7-213
7-219
7-229
7-235
7-235
7-239
7-243

MASTER INDEX (continued)

Device Type
Number
MC1558
MC1560
MC1561
MC1563
MC1566
MC1568
MC1569
MC1580
MC1581
MC1582
MC1583
MC1584
MC1585
MC1590
MC1594
MC1595
MC1596
MC1709
MC1709C
MC1710
MC1710C
MC1711
MC1711C
MC1712
MC1712C
MCl723
MC1723C
MC1733
MC1733C
MC1741
MC1741C
MC1741S
MC1747
MC1747C
MC1748
MC1748C
MC1776
MC3301
MC3302
MC3401
MC5528
MC5529
MC5534
MC5535
MC5538
MC5539
MC7520
MC7521
MC7522

Selector Guide
(Section 3) or
Circuit Previews
(Section 4)
Page No.

Circuit Function Description
Operational Amplifier
Positive Voltage Regulator
Positive Voltage Regulator
Negative Voltage Regulator
Voltage and Current Regulator
Dual ±15-Volt Tracking Regulator
Positive Voltage Regulator
Dual Line Driver Receiver
Dual MECL Line Receiver
Dual MDTL, MTTL Line Driver
Dual Saturated Logic Receiver
Dual MDTL, MTTL Receiver
Dual MOS Clock Driver
Wideband Amplifier with AGC
Four-Quadrant Multiplier
Four-Quadrant Multiplier
Balanced Modulator-Demodulator
Operational Amplifier
Operational Amplifier
Differential Comparator
Differential Comparator
Dual Differential Comparators
Dual Differential Comparators
Wideband DC Amplifier
Wideband DC Amplifier
Positive Voltage Regulator
Positive Voltage Regulator
Differential Video Amplifier
Differential Video Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Dual Operational Amplifier
Dual Operational Amplifier
Operational Amplifier
Operational Amplifier
Programmable Low-Power Operational Amplifier
Quad Operational Amplifier
Quad Comparator
Quad Operational Amplifier
Dual High-Speed Sense Amplifier with Preamplifier
Dual High-Speed Sense Amplifier with Preamplifier
Dual Sense Amplifiers with Inverted Outputs
Dual Sense Amplifiers with Inverted Outputs
Dual High-Speed Sense Amplifier with Preamplifier
and I nverted Outputs
Dual High-Speed Sense Amplifier with Preamplifier
and I nverted Outputs
Dual Sense Amplifiers
Dual Sense Amplifiers
Dual Sense Amplifiers

1-3

Data Sheet
Page No.
(Section 7)
7-249
7-253
7-253
7-265
7-281
7-291
7-297
7-317
7-325
7-331
7-337
7-344
7-351
7-356
7-362
7-376
7-392
7-402
7-402
7-406
7-410
7-412
7-416
7-420
7-420
7-424
7-424
7-430
7-430
7-436
7-436

Test Points

3-2
3-9
3-9
3-10
3-10
3-10
3-9
3-5,3-7
3-7
3-5
3-7
3-7
3-6
3-11
3-12
3-12
3-12
3-1
3-1
3-8
3-8
3-8
3-8
3-1
3-1
3-9
3-9
3-11
3-11
3-1
3-1
4-2
3-2
3-2
3-1
3-1
4-2
3-2,3-14
3-8,3-14
3-2
3-3
3-3
3-3
3-3
3-3

Test Points

3-3

7-470

3-3
3-3
3-3

7-473
7-473
7-473

Test Points
Test Points

-

7-440
7-440
7-444
7-444
-

7-446
7-454
7-456
7-464
7-464
7-467
7-467
7-470

•

MASTER INDEX (continued)

•

Device Type
Number
MC7523
MC7524
MC7525
MC7528
MC7529
MC7534
MC7535
MC7538
MC7539
MC7805C:j:
MC7806C:j:
MC7808C:j:
MC7812C:j:
MC7815C:j:
MC7818C:j:
MC7824C:j:
MC55107
MC55108
MC55109
MC55110
MC55325
MC75107
MC75108
MC75109
MC75110
MC75113
MC75325
MC75450
MC75451
MC75452
MC75453
MC75454
MC75491
MC75492
MCB1709
MCB1710
MCBl723
MCB1741
MCB1748
MCBC1709
MCBC1710
MCBCl723
MCBC1741
MCBC1748
MCC1436
MCC1439
MCC1458
MCC1463
MCC1469

Selector Guide
(Section 3) or
Circuit Previews
(Section 4)
Page No.

Data Sheet
Page No.
(Section 7)

Points

3-3
3-3
3-3
3-3
3-3
3-3
3-3
3-3

7-473
7-476
7-476
7-464
7-464
7-467
7-467
7-470

Points

3-3

7-470

3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-7
3-7
3-5
3-5
3-6
3-7
3-7
3-5
3-5
3-5
3-6
3-6
3-6
4-6
4-6
4-6
4-6
4-6
3-1
3-8
3-9
3-1
3-1
3-1
3-8
3-9
3-1
3-1
3-1
3-1
3-1
3-10
3-9

-

Circuit Function Description
Dual Sense Amplifiers
Dual Sense Amplifiers
Dual Sense Amplifiers
Dual High-Speed Sense Amplifier with Preamplifier Test
Dual High-Speed Sense Amplifier with Preamplifier Test
Dual Sense Amplifiers with I nverted Outputs
Dual Sense Amplifiers with Inverted Outputs
Dual High-Speed Sense Amplifier with Preamplifier Test
and I nverted Outputs
Dual High-Speed Sense Amplifier with Preamplifier Test
and I nverted Outputs
Positive Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Dual Line Receivers
Dual Line Receivers
Dual Line Drivers
Dual Line Drivers
Dual Memory Driver
Dual Line Receivers
Dual Li ne Receivers
Dual Line Drivers
Dual Line Drivers
Differential Party-Line Driver
Dual Memory Driver
Dual Peripheral Driver
Dual Peripheral Driver
Dual Peripheral Driver, Positive NAND
Dual Peripheral Driver, Positive OR
Dual Peripheral Driver, Positive NOR
MOS-to-VLED Segment and Digit Quad Driver
MOS-to-VLED Segment and Digit Hex Driver
Operational Amplifier (encapsulated Beam-Lead)
Differential Comparator (encapsulated Beam-Lead)
Voltage Regulator (encapsulated Beam-Lead)
Operational Amplifier (encapsulated Beam-Lead)
Operational Amplifier (encapsulated Beam-Lead)
Operational Amplifier (non-encapsulated Beam-Lead)
Differential Comparator (non-encapsulated Beam-Lead)
Voltage Regulator (non-encapsulated Beam-Lead)
Operational Amplifier (non-encapsulated Beam-Lead)
Operational Amplifier (non-encapsulated Beam-Lead)
Operational Amplifier (Chip)
Operational Amplifier (Chip)
Dual Operational Amplifier (Chip)
Negative Voltage Regulator (Chip)
Positive Voltage Regulator (Chip)

Points
Points

:j:For complete Data Sheet information please contact your Motorola distributor or salesman.

1-4

-

-

7-478
7-478
7-483
7-483
7-490
7-478
7-478
7-483
7-483
7-492
7-490
7-496
7-501
-

-

7-504
7-508
7-510
7-512
7-516
7-504
7-508
7-510
7-512
7-516
7-518
7-520
7-522
7-524
7-526

MASTER INDEX (continued)

Device Tvpe
Number

Circuit Function Description

Selector Guide
(Section 3) or
Circuit Previews
(Section 4)
Page No.
3-12
3-1
3-1
3-1
3-10
3-9
3-12
3-1
3-1
3-8
3-8
3-8
3-8
3-9
3-9
3-1
3-1
3-1
3-1
3-2
3-2
3-1
3·1
3-1
3-1
3-12
3-2
3-2
3-12
3-14
3-14
3-15
3-14
3-9
3-9
3-9
3-9
3-14
3-15
3-9
3-9
3-9
3-9
3-15
3-15
3-15
3-14
3-15

Four-Quadrant Multiplier (Chip)
MCC1495
Operational Amplifier (Chip)
MCC1536
Operational Amplifier (Chip)
MCC1539
Dual Operational Amplifier (Chip)
MCC1558
Negative Voltage Regulator (Chip)
MCC1563
Positive Voltage Regulator (Chip)
MCC1569
Four-Quadrant Multiplier (Chip)
MCC1595
Operational Amplifier (Chip)
MCC1709
MCC1709C Operational Amplifier (Chip)
Differential Comparator (Chip)
MCC1710
MCC1710C Differential Comparator (Chip)
Dual Differential Comparator (Chip)
MCC1711
MCC1711C Dual Differential Comparators (Chip)
Positive Voltage Regulator (Chip)
MCCl723
MCCl723C Positive Voltage Regulator (Chip)
Operational Amplifier (Chip)
MCC1741
MCC1741C Operational Amplifier (Chip)
Operational Amplifier (Chip)
MCC1748
MCC1748C Operational Amplifier (Chip)
MCCF1458 Operational Amplifier (Flip-Chip)
MCCF1558 Operational Amplifier (Flip-Chip)
MCCF1709 Operational Amplifier (F lip-Chip)
MCCF1709C Operational Amplifier (F lip-Chip)
MCCF1741 Operational Amplifier (Flip-Chip)
MCCF1741C Operational Amplifier (Flip-Chip)
Darlington Power Driver
MCH2005
MCH2870C Power Operational Amplifier
MCH2870M Power Operational Amplifier
Dual Power Driver
MCH2890
MFC4000B %-Watt Audio Amplifier
MFC4010A Wideband Amplifier
Single Toggle Flip-Flop
MFC4040
Audio Driver
MFC4050
MFC4060A Voltage Regulator
MFC4062A Voltage Regulator
MFC4063A Voltage Regulator
MFC4064A Voltage Regulator
FM IF Amplifier
MFC6010
Dual Toggle Flip-Flop
MFC6020
MFC6030A Voltage Regulator
MFC6032A Voltage Regulator
MFC6033A Voltage Regulator
MFC6034A Voltage Regulator
Electronic Attenuator
MFC6040
MFC6050
Dual Toggle Flip-Flop with Reset
MFC6060
3-lnput AND Gate
MFC6070
Audio Power Amplifier
R-S Flip-Flop
MFC6080
Dual Differential Amplifier
MFC8000
MFC8001
Dual Differential Amplifier
Dual Differential Amplifier
MFC8002

-

1-5

Data Sheet
Page No.
(Section 7)
7-528
7-518
7-520
7-522
7-524
7-526
7-528
7-530
7-530
7-532
7-532
7-534
7-534
7-536
7-536
7-538
7-538
7-540
7-540
7-542
7-542
7-544
7-544
7-546
7-546
7-548
7-548
7-554
7-558
7-561
7-565
7-567
7-570
7-570
7-570
7-570
7-572
7-576
7-578
7-578
7-578
7-578
7-582
7-585
7-587
7-589
7-595
7-597
7-597
7-597

I

MASTER INDEX (continued)

I
Device Type
Number
MFC8010
MFC8020A
MFC8021A
MFC8022A
MFC8030
MFC8040
MFC8050
MFC8070
MFC9020
MHP401
MLM101A
MLM104
MLM105
MLM107
MLM108A
Series
MLM109K
MLM111
Series
MLM201A
MLM204
MLM205
MLM207
MLM209K
MLM210
MLM301A
MLM304
MLM305
MLM307
MLM309K
MLM310
MMH0026

Circuit Function Description
Audio Power Amplifier
Class B Audio Driver
Class B Audio Driver
Class B Audio Driver
Differential Cascade Amplifier
Audio Preamplifier
J-K Flip-Flop
Zero Voltage Switch
Audio Amplifier
MOS Clock Driver
Operational Amplifier
Negative Voltage Regulator
Positive Voltage R egu lator
Operational Amplifier
Operational Amplifiers

Selector Guide
ISection 3) or
Circuit Previews
ISection 4)
Page No.
3·14
3·14
3·14
3·14

3-14
3-15
3·12
3-14
3-6
3-1
3-10
3-9
3-1
4-2

Voltage Regulator
Voltage Comparators
Operational Amplifier
Negative Voltage Regulator
Positive Voltage Regulator
Operational Amplifier
Voltage Regulator
Operational Amplifier
Operational Amplifier
Negative Voltage Regulator
Positive Voltage Regulator
Operational Amplifier
Voltage Regulator
Operational Amplifier
Dual MOS Clock Driver

1-6

Data Sheet
Page No.
ISection 7)
7·599
7·602
7·602
7·602
7·606
7-608
7-611
7-613
7·617
7·621
7-624
7-626
7·628
7-630

-

3-9
4-6

7-632

3-1
3-10
3-9
3-1
3-9
3-1
3-1
3-10
3-9
3-1
3-9
3·7
4-6

7-624
7-626
7-628
7-630
7-632
7-634
7-624
7-626
7-628
7-630
7-632
7-634

-

-

UNDERSTANDING MOTOROLA'S DEVICE NUMBERING SYSTEM
A great deal of information is given in the device number on Motorola ICs. This section will
present the meanings of the prefixes, numbers and suffixes used to designate Motorola linear ICs.
Normally the package style and operating temperature range may be obtained from the device
number.
Although there are exceptions to many of the codes listed below, these codes are generally true
and can provide the user with pertinent information on the particular device type.
Prefix
MC

Packaged Integrated Circuits

MCC

Unencapsulated Integrated Circuit chips

MFC

Low cost Integrated Circuits packaged in Motorola's unique "Functional Circuits" plastic:
package. (Package suffix not used in this device series.)

MCBC

Beam-lead Integrated Circuit chips

MCB

Packaged Beam-lead Integrated Circuits. (Followed by F suffix when in flat pack.)

MCCF

Flip-Chip Linear Integrated Circuits

MLM

Pin-for-pin equivalent to Linear Integrated Circuits made by National Semiconductor

MCH

Hybrid Integrated Circuit in hermetic package

MHP

Hybrid Integrated Circuit in plastic package

Body Number for Motorola Proprietary Devices
1500-1599 Military temperature grade (-55 to +125°C) Linear ICs
1400-1499 Equivalent to devices above but with Industrial temperature range (0 to +70°C)
3400-3399
1300-1399 Linear ICs aimed at the Consumer industry
3300-3399
Package Suffix
L

Ceramic dual in-line case (14 or 16 pin)

G

Metal can package (TO-5 types)

R

Metal power package (TO-66 type)

K

Metal power package (TO-3 type)

F

Flat package

P

Plastic package

P1, P2

Used when an IC is available in more than one plastic package. i.e. P1 = 8 lead plastic
DIP, P2 = 14 pin plastic DIP

PO

ICs packaged in staggered-lead plastic DIP packages (Consumer device types only)

C

Designates limited temperature, or limited performance device. Followed by package
designation suffix, i.e. MC1709CL

A

Designates improved or modified IC type, followed by package suffix, i.e. MC1489AL.
1-7

•

I

Highlights
... A small cross-section of new
and/or unique devices from Motorola's
extensive linear IC product lines that
merit special attention.

2-1

•

linear IC Highlights (continued)

OPERATIONAL AMPLIFIERS
The operational amplifier has always been the most popular and versatile Linear Ie type. Op
amps have found wide usage in control circuitry, signal processing equipment, active filters for
communications systems, Modems, and many other types of equipment. With the addition of a
few external components, this basic feedback type amplifier can be transformed into a multitude
of functions ranging from summing amplifiers and simple inverters to integrating amplifiers and
Sample and Hold circuits.
Motorola offers a broad line of op amp types. Both proprietary and popular industry-standard
types are covered. The range of high precision to low cost plastic-packaged multiple op amps is
spanned by over 45 device types. Two representative devices are discussed here. An overview of
the entire line appears on page 3-1.

HIGH IMPEDANCE BRIDGE AMPLIFIER

10 k

+

100 k

10 k

6
VO~10Vin

100 k

=

Precision Op Amp (MC1556/1456)

power bandwidth of 40 kHz typical, a typical
voltage gain of 200,000, low power consumption
of 45 mW max, offset-voltage zeroing capability,
and output short-circuit and input overvoltage
protection. Unity gain slew rate is 2.5 V/p.s and
input offset voltage is 2.0 mV.
Applications include summing, high-impedance
bridge, and logarithmic amplifiers. The MC1556
can also be used as a high input-impedance,
high-speed voltage follower. In this application, the
device shows high tolerance to common-mode
voltages at its input, and has a well-balanced
large-signal response.

When very high source impedance and high slew
rate requirements must be met with an op amp, the
MC1556 is a logical choice. This advanced op amp
uses super-beta bipolar input transistors to
dramatically reduce input bias current (15 rnA
max). In the past, these low current ratings could
be achieved only through the use of field-effect
transistors at the input. However, unlike FET input
op amps, the super·beta approach does not require
that offset voltage drift with temperature be
compromised to obtain the low bias currents.
Other features of the MC1556 include a large

2-2

Linear IC Highlights (continued)

BASIC BANDPASS AND NOTCH FI LTER
R
C

390 k

I

R1
Vin C x 10

~

C

TBP
R2

t
Ir

2
2(R IIUR)

L---------~-----4------------------~----~---.VCC
R1

2(R111 R3)

TN R2

R2

><>-e---1 ~TC H

TBP = Center Frequency Gain
TN = Passband Notch Gain
1

wo=Rc

R1 = UR
R1
R2=TBP
R3= TN R2

voltages commonly available in these systems.
Specifically, the device can be used with 4 to 28
Vdc power supplies without the common mode
input voltage problems usually encountered when
conventional op amps are operated from a single
power supply. Output voltage swing is approximately one volt less than the power supply voltage,
while channel separation between the individual
amplifiers within a package is 65 dB at 1 kHz.
A number of common applications such as logic
gates, differentiators, flip-flops, and multivibrators
are given on the device data sheets.

Lowest Cost Quad Op Amp (MC3301/3401)
At a time when ultra-performance op amps for
specialized applications make up the majority of
new introductions, a need exists for a low cost,
modest performance op amp for industrial and
automotive uses. The MC33D1/MC34D1 provides
four such amplifiers in a single plastic package and
at cost of less than a dollar in 1DO-up quantities.
The new device is intended for use in industrial
control systems and active filters in communication systems. It operates from the power supply

2-3

I

Linear IC Highlights (continued)

VOLTAGE REGULATORS
The sensitivity of semiconductor devices to voltage and temperature changes makes the voltage
regulator circuit an important integral part of many critical systems and subsystems. Today's
designer has considereable choice in integrated regulators, with a variety of characteristics,
capabilities, and prices. The integrated circuit voltage regulator offers ease of design, simplified
assembly and improved performances over discrete transistor designs. Motorola offers a series of Ie
voltage regulators with a variety of specifications, see page 3-10. Highlighted here are two circuits
that merit special attention.
Op Amp Companion
Most IC operational amplifiers and analog multipliers require symmetrical ±15 V power supplies.
Although a multitude of low-cost IC op amps are
now available, the new MC1568 is one of the first
low-cost IC voltage regulators specifically designed
to supply the required symmetrical voltages. This
monolithic dual tracking regulator is preset for
±.15 V (within ±200 mV) although it may be programmed to outputs of .±14.5 V through .±20 V by
adding two suitable external resistors. At ±15 V,
the absolute value of output voltages agree within
a maximum of 1%.
Thus the designer needs only one IC package, a
few passive components (no precision resistors)
and a transformer-rectifier assembly capable of
providing between ±17 and ±30 V to obtain the
±15 V power source for control circuitry. Without
external current boosting transistors, this regulator
can provide output currents up to ±100 mA,
sufficient for most op amp applications. The device
features remote sensing and externally adjustable
current limiting.

BASIC SO-rnA REGULATOR

INPU T(+)

4(7)

VCC

VEE

vo+

Vo-

518)

6 (10)

3 (5)
RSC+

RSC2 (4)

SENSE
(+) GNO

COMPENH 1

10

(3) ) (1)
Cl-::~

SENSE
(-)

8

C3

COMPEN(+)

..,~ C2
--r-1500pF

+11'

~(

l.~~F

7 (11)

>(12)

1500 pF "r-

+VO
+15 Vdc

INPUT H

-==

l.~~F
C4

-VO
-15 Vdc

O-TO-250 VDC, O.1-AMPERE REGULATOR

Unique "Floating" Regulator
While most IC voltage regulators are limited to
output voltages less than 50 V and output currents
below a few amperes, the MC1566 uses a unique
approach that has virtually no limits in the range of
practical applications.
The regulator is designed to control an external
power transistor and will operate at any voltage or
current level that the power transistor can handle.
In addition, performance is on the level of
laboratory-type supplies.
Some of the features of the circuit include:
voltage andlor current adjustable to zero, automatic crossover (goes from constant voltage to
constant current regulation - not just current
limiting), remote sensing, remote programming,
line voltage regulation of 0.01% + 1 mV, load
voltage regulation 0.01% + 1 mV, current
regulation 0.1% + 1 mA, and a temperature
coefficient that is typically O.004%/"C.
The high voltage capability is due to the
"floating" nature of the circuit, with operating
voltage for the circuit obtained from a separate,
isolated supply (about 25 Vdc). Voltage regulation
is accomplished by comparing the power output
voltage to a reference voltage generated by passing

1N4005 OR EQUIV

an adjustable current through a voltage-setting
resistor. Since the entire output voltage is
compared to the reference voltage, the MC1566L
always operates at maximum loop gain, establishing excellent regulation over the entire voltage
range.
Since the series pass transistor is external to the
integrated circuit, power dissipation of the IC is
constant, preventing degradation of regu lation due
to heating.

2-4

Linear Ie Highlights (continued)

ENTERTAINMENT CIRCUITS
The high-volume, low-cost, and highly specialized requirements of the electronic components
for consumer entertainment equipment matches the capabilities of today's linear ICs. A great
variety of the necessary functional blocks for television, stereo phonographs, and radio receivers is
now available in low-cost plastic-packaged ICs. The need for improved performance and increased
reliability and, at the same time, for a lower selling price, is met by state-of-the-art monolithic
circuits.
Motorola's traditional leadership in plastic transistors for the customer electronics industry is
being extended with a complete lineup of low-cost ICs for those functions which can best be
accomplished with monolithic integrated circuits. Both original innovative designs and popular
second-source devices which have been well accepted by the industry are included in this diverse
family of products. Some typical examples are highlighted here.

For Tel e vis ion alone, Motorola offers better than 20 different types of ICs to give the
designer a wide choice of performance levels and partitioning approaches. To aid in the parade
toward fully solid-state sets, Motorola offers ICs for the video IF amplifier and detector, AFT,
chroma processor and detector, audio stages, and a combination device which supplies AGC, sync
separator and noise-suppression circuitry. Often these ICs permit circuit complexity and
performance which would not be technically and economically practical with discrete
components.
A selector guide to I Cs for use in television sets is provided on page 3-13.
180

120

+18 V
IO.002~F

-=

.--.......- .

TO
VIDEO
DETECTOR

56 pF

AGe

An Improved Video I F Amplifier
Packed into a small 8·lead plastic package, the
MC1349 is intended for use as the video IF
amplifier in television receivers. To meet the
stringent AGC requirements of video ampli-fiers
imposed by the wide range of television signal
levels in most locations, the device is designed to
provide a' minimum AGC range of 80 dB. Other
features of the new IC are typical power gain of 60
dB at 45 MHz and a low noise figure of 8.5 dB
measured at 45 MHz and 15 dB of AGC reduction.
The MC1349 is an improved version of the
popular MC1350. The new device offers higher

gain, a lower noise figure.and a greater AGC range.
Another circuit improvement permits the MC1349
to be used in video amplifiers which use untuned
input configurations.
The unique design of the new IC permits the
input amplifier stage to serve both as an IF
amplifier and as an AGC amplifier for the output
section.
To provide the user with needed design
information, the device data sheet includes
admittance parameter data for common AM/FM
radio and television I F frequencies.

2-5

I

I

Linear IC Highlights (continued)

For Audio . ..
Linear ICs are rapidly penetrating the audio amplifier stages of television, radio, and stereo
phonographs. Both low level and power amplifier applications are realizing greater performance
and lower total cost due to the reduced assembly requirements and the ability to use more
complex circuitry with these advanced ICs. A wide range of IC types permits the designer a wide
lattitude of flexibility to create the exact system performance and costs he requires.
New Audio devices include . ..
• The new MC1339 replacement for the popular 239 type preamplifier has joined the existing
MC1303 stereo preamp.
• Power audio amplifiers are presently limited to about two-watt levels, although higher power
units are on the drawing boards.
• Highlighted below is Motorola's entry into the Quad-Stereo field. This unit is the first in a series
of four channels I Cs. Upcoming quad-stereo products are previewed on page 4-1.

4.3 k
0.0391'F

'2~

0.0068

LB'

An IC for the Quad Sound

LF'
MC1312P
9

MC1313P

10 11 12 13 14

RB'

RF'
0.0391'F

Vee

2-6

The quad sound is the newest trend in audio!
To meet this trend, Motorola has introduced the
MC1312/1313 quadraphonic decoder - the first
IC for the CBS developed sa matrix system.
The device consists of two preamplifiers which
are fed with left total, LT, and right total, RT,
signals. The preamplifiers each feed two all-pass
networks which are used to generate two LT
signals in quadrature and two RT signals in
quadrature. The four signals are matrixed to yield
left front, left back, right front, and right back
signals (LF, LS, RF, RS)'
The MC1312 is expected to find wide use in
low-cost audio equipment and, with the addition
of logic circuitry to enhance quadraphonic
separation, it may be used in even the most
sophisticated "component type" systems. The
MC1313 version is specifically intended for use in
automotive audio equipment.

Linear

Ie Highlights (continued)

I

For Radio . . . .

Two sections in FM radios have lent themselves well to integration: The IF amplifier and
detector, and the stereo mUltiplex decoder sections. In both high-quality tuners and in low-priced
table radios, the high performance of these ICs and lower assembly costs they make possible,
permit more efficient designs.
Specifically highlighted is a new stereo decoder which promises to become the new industry
standard decoder circuit. Other devices for use in both AM and FM radio are listed in the selector
guide on page 3-14.

R4
19 kHz
OUTPUT

C6

C5

12

13

MC1310

CI

INPUT"f+t::+==~_J

tunable inductors, the new circuit offers a
significant savings in component and assembly
costs and improved long term performance.
The new device makes use of the advanced
phase locked loop principle to lock onto the 19
kHz pilot signal provided by the stereo broadcaster
and to create a signal which is in phase with the
pilot signal and of exactly double the frequency.
This 38 kHz subcarrier is then used to demodulate
the stereo information.
An automatic stereo-mono switching circuit is
provided to disable the decoder during monaural
broadcasts or weak stereo broadcasts. This switch
also controls a lamp driver which employs 6 dB of
hysteresis to avoid flickering of the stereo indicator
lamp due to variations in signal level.
Performance of the new decoder is as good or
better than the usual frequency doubler type of
stereo demodulators. Stereo separation is 40 dB at
1 kHz with total harmonic distortion at typically
0.3% for a 560 mV level of composite input.

C2
VCC __----4-----------~_4_+_+~~~
LEFT
CHANNF.L OUTPUT

RIGHT
CHANNEL OUTPUT

No coils needed with this Stereo Decoder
The new MC1310 is the second generation
stereo decoder circuit. This decoder provides high
performance, low external parts count and reduced
alignment requirements. It requires no tuned
circuits and only one non-critical adjustment is
necessary after assembly. Until now, IC decoders
usually required three tuned circuits which had to
be adjusted at the factory in each individual stereo
tuner. Performance could be degraded if anyone
of the tuned circuits became detuned due to
vibration or component aging. By eliminating the

2-7

Linear IC Highlights (continued)

INTERFACE CIRCUITS

I

Interface circuits is the name applied to devices that operate with both linear signals and digital
logic levels. Most have both linear and digital properties. Examples of interface circuits are D/A
and A/D converters, memory sense amplifiers, comparators, and line driver and receivers.
The rapidly expanding fields of data communications and digital instrumentation make wide
use of these interface devices. Line drivers, and receiver, for example, are used whenever data must
be transmitted over long distances in a computer or piece of peripheral equipment. Also, the
industry standard MC1488-89 devices provide the level translation between a Modem and a
computer terminal in accordance with the EIA RS-232C specifications. Likewise comparators are
used as voltage level detectors in control and instrumentation applications.
Motorola offers a broad line of interface circuits. Two of the newest interface devices are
discussed below while the complete lineup is outlined beginning on page 3-3.
New Line Driver for Computer Systems
The MC75113 was primarily designed to be
used for transmitting data at high speeds over long
distances in systems where numerous drivers and
receivers share a common twisted-pair line in a
"Party· Line" mode.
The device provides two output currents of
equal but opposite polarities. This technique offers
several advantages over most IC drivers employing
a single polarity output current. With the matched
currents used in the MC75113, both wires in the
twisted pair transmission line carry equal and
opposite currents thereby minimizing cross-talk
radiation. Likewise, the matched currents reduce
ground loop currents which can generate voltages
that reduce the useful common mode range of
drivers and receivers in a system.
This new technique produces twice the
differential voltage at the opposite end of the
transmission line as single-ended drivers of equal

MC75113

output rating, thus promoting reduced data errors
and greater noise immunity.
Specifically, the MC75113 features a TTL
compatible four input OR gate and output currents
of nominally ±20 mAo
prevented their manufacture on the same chip with
the active devices in the past. I n order to use
diffused resistors, unique design techniques were
adopted to avoid variations in conversion speed
due to the parasitic capacitances associated with
diffused resistors.
A current mode output was chosen for the IC
converter rather than a voltage mode output to
allow faster conversion speed. Nevertheless, a
voltage output is easily obtained by adding an
external operational amplifier. The device may also
be used as a digitally-controlled attenuator to
produce the product of a digital word and an
analog signal which is applied to the reference
input. This is possible due to the "multiplying"
nature of the converter.
In particular, the MC1506 features TTL and
DTL compatible inputs and a relative accuracy of
at least 0.78% over a range of -55 to 125°C.
Output current drift is held to about 0.002%/"C
and the output current is 2.0 mA maximum.
Settling time to within 1/2 of the least significant
bit is 200 ns.
Several other products are planned in the AID,
D/A area. An 8-bit D/A converter and a control
element for use with a DI A converter to produce
an AID converter are previewed on page 4-5.

+ 15 V

ANALOG

1-:---T6l-~~ho UTPUT

~MSB)

DIGITAL A3
INPUTS _

VOLTAGE
5.1k

A4

(LSB)

MC1583

A6

A Low Cost D/A Converter
Most D/A converters are either hybrid or
modular units. This often prevents them from
selling at a modest price. However, the MC1506,
6-bit converter uses a high-yield monolithic
fabrication technique whereby literally hundreds
of units are built on a single silicon wafer. This
allows the MC1506 to sell for much less than many
comparable units.
The MC1506 uses the popular R-2R resistor
ladder network whose stringent requirements have

2-8

INTEGRATED CIRCUITS

OPERA rlONAL AMPLIFIERS
These linear integrated circuits are available as single,
dual, and quad monolithic devices in a variety of
package styles as well as standard and beam-lead chips.

Motorola offers a broad line of operational amplifiers
to meet a wide range of usages. From low-cost, industry
standard types to high precision circuits the span
encompasses a large range of performance capabilities.

OPERATIONAL AMPLIFIERS
(See reverse side of sheet for dual and quad operational amplifiers and drivers.)

Listed in order of increasing input bias current within temperature group.

INTERNALLY COMPENSATED
Vo
@I RL II< Vee, VEE
IVpk mini Iknl
IVdcl

0.015
0.02
0.075
0.5

4.0
5.0
2.0
5.0

2.0
3.0
10
200

100.000
100.000
50.000
50.000

12
22
10
10

2.0
5.0
2.0
2.0

±15

±28
±15
±15

Case

1.0
1.0
1.0
1.0

40
23
10
10

2.5
2.0
0.5
0.8

601
601
601
601.606.632.665' ,

MC1556
MC1536'
MLM107
MC1741···t

0

601
601

0.007
0.03
0.04
0.09
0.09
0.25
0.5

7.5
10
10
12
12
7.5
6.0

-

Unity

10
10

70.000
70.000
25.000
50.000
25.000
20.000

JO
25
50
200

10
11
20
10
20
10
10

10
2.0
5.0
2.0
5.0
2.0
2.0

±15
±15

±28
±15
±28
±15
±15

20
1.0
1.0
1.0
1.0
1.0
1.0

JOO
40
23
40
23
10
10

30
2.5
2.0
2.5
2.0
0.57
0.8

601
601
601
601
601
601
601.606.626.632.646

MLM310
MC1456
MC1436'
MC1456C
MC1436C
MLM307
MC1741C',

NONCOMPENSATED
Vo
@I RL II< VCC. VEE
IVpk mini Iknl
IVdcl

0.Q75
0.15
0.5
0.5
0.5
1.0
2.0
5.0
10

2.0
10
3.0
5.0
5.0
5.0
10
2.0
5.0

10
25
60
200
200
150
100
500
2000

50.000
2.500
50.000
50,000
25.000
40,000
1,000
2,500
4.500

10
4.5
10
10
10
11
3.5
3.5
4.5

2.0
1.0
1.0
2.0
2.0
2.0
7.0
10
1.0

±15
±6.0
±15

±15
±15
±15

±6.0
+12,·6.0
±6.0

Case

1.0
2.0
2.0
1.0
0.5
0.8
10
7.0
3.0

10
100
50
10
4.0
2.0
150
10
100

0.5
1.4
4.2
0.8
0.25
2.0
5.0
1.5
1.7

601
602B.606
601.632
601,606"
601,606.632,665 ..
602B,606.632
602A,606
601,606,632
602B,606

MLM101A
MC1531
MC1539'
MC1748' ..
MC1709"'t
MC1533
MC1520
MC1712
MC1530

0

601

0.25
0.3
0.5
1.0
1.5
2.0
4.0
7.5
15

7.5
15
6.0
7.5
7.5
7.5
15
5.0
10

50
100
200
100
500
500
200
2000
4000

25,000
1,500
20,000
15,000
15,000
30,000
750
2,000
3,000

10
4.0
10
10
10
10
3.0
3.5
4.0

2.0
1.0
2.0
2.0
2.0
2.0
7.0
10
1.0

±15

±6.0
±15
±15
±15
±15

t6.0
+12,·6.0

±S.O

1.0
2.0
1.0
2.0
0.5
0.8
10
7.0
3.0

10
100
10
50
4.0
2.0
150
10
100

0.5
1.4
0.8
4.2
0.25
2.0
5.0
1.5
1.7

601,626
602B,606,646
601
601,632,646
601,606,626,632,646
6028,606,632,646
602A,606
601,606,632
6026,606,646

·Use MeC prefix for nonencapsulated chip.
"Use MCBC prefix for nonencapsulated beam· lead device, use MeB prefix for beam· lead device in flat ceramic package.
tUse MCCF prefix for nonencapsulated flip·chip.

DEFINITIONS
SA
VIO
liB
110

Slew Rate@ Unity Gain
Input Offset Voltage
Input Bias Current
Input Offset Current

Avol
Va
fc
BWp

3-1

Open-Loop Voltage Gain
Output Voltage Swing
Unity Gain Crossover Frequency
Power Bandwidth

MLMJ01A
MC1431
MC1748C'
MC1439'
MC1709C',
MC1433
MC1420
MC1712C
MC1430

•

INTEGRATED CIRCUITS
OPERATIONAL AMPLIFIERS (Continued)

DUAL OPERATIONAL AMPLIFIFRS
Listed in increasing ~rder of input bias cur:ter't.

. "Use 'Mec. prefix for nonencapslIlatect chip.
lU~ MCCF pt'efht for nonencapsulated flip~(:hip.

NONCOMPENSA TED

to+

emperature

200

~

0.5
••

oto +15
300

5.0
G

200

~

6.0

200

.'

12

300

±15

-

1500

75

614

50,000

12

300

±15

1.1

12

0.8

614 MC1741 with high current MCH2870M

.
850

11

300

e

".
±15

20,000

11

300

±15

MCI538

capabilitV. ±300 rnA max

.

'.

,

High current gain (10 dBI
op ampl power booster
10;:: 300 rnA max

~

1500

.....

75

614

1.1

12

0,8

,,',

High current gain (70 dBI
op ampl power booster.

10
0.5

."

.

900

C Temperature Range
~

.

..

ange

~

=

MCI438

:IlOmA max

614 MC1741 with high current MCH2870C
capability. ±300 rnA max

3-2

,i."

INTEGRATED CIRCUITS

INTERFACE CIRCUITS
Interface circuits fit in the gray area between the
linear and digital realms. Usually these IC's perform the
necessary translation between an analog signal input and
the required digital logic levels or vice versa. To aid in

selection, the devices have been divided into five main
categories: Sense Amplifiers, Drivers, Receivers, Comparators, and D/A Converters.

SENSE AMPLIFIERS
±5.0 volt power supplies. The output of these sense
amplifiers changes logic states when the differential
input voltage exceeds a specified threshold level,
regardless of input polarity.

The sense amplifiers listed provided the necessary
translation from the outputs of core or plated-wire
memories to MTTL (unless otherwise noted) logic levels.
Unless noted, all devices are designed to operate from
COREMEMORV

Function

~r~"~M'.""

independent gating, camp Iementary outputs, memory

data register

~
~
~

~
~
~
~

~
~

Dual channel with opencollector output, high sink

current capability

Dual with independent
strobing

Same as MC7524-25 except
amplifier test points included

Same as MC7524-25 except
NAND outputs

Same as MC7528-29 except
NAND outputs

Threshold
Voltage @
(mVI
min
max

Vref

(mVI

Type

Propagation
Delay
(ns max)

Case

·55 to +125°C

o to +70 oC

11
36

19
44

15
40

55

620

-

MC7520

8.0
33

22
47

15
40

55

620

-

MC7521

11
36

19
44

15
40

45

620

-

MC7522

8.0
33

22
47

15
40

45

620

-

MC7523

11
36

19
44

15
40

40

620

-

MC7524

8.0
33

22
47

15
40

40

620

-

MC7525

11
36

19
44

15
40

40

620.
648"

-

MC7528

10
35

20
45

15
40

40

620

MC5528

-

8.0
33

22
47

15
40

40

620,
648"

MC5529

MC7529

11
36

19
44

15
40

40

620.

-

MC7534

10
35

20
45

15
40

40

620

MC5534

-

8.0
33

22
47

15
40

40

620.
648"

MC5535

MC7535

11
36

19
44

15
40

40

620.
648"

-

MC7538

10
35

20
45

15
40

40

620

MC5538

-

8.0
33

22
47

15
40

40

"Case 648 used with commercial-temperature-range devices only.

3-3

648"

620.

648"

MC5539

MC7539

I

INTEGRATED CIRCUITS
INTERFACE CIRCUITS (Continued)

SENSE AMPLIFIERS (continued)'
CORE MEMORY (Continued)

.

.

'

'

.

....
Threshold
Voltage @

(mV!
max

Vref
(mVI

14

20

14

17

Type

Propagation
Delay
(ns max)

Case

-55 to +125°C

o to +75°C

-6.0V

30

6028,
606,
632

MC1540

MC1440

20

-5.0V

30

607,
632

MC1541

MC1441

23

540

35

632

MC1543

-

min

Function
.'

~

O.5~s

cycle time,
20n5 typ response time,
±6.0V power supply

it, C ext
2-

0.4",5 cycle time,
1.SV common-mode inputs,

1.0mV typ input offset

2-

:=[>--D=:

Compatible with MECL.
+5.0V. -S.2V power supplies,

threshold insensitive

:t>-o=:
.:

~LATEDWIRE

to supply variations,

complementary outputs

'.:

.•..

:

MEMORIES

Function

Threshold
Voltage

Propagation
Delay

(mV-typl

(ns -maxI

1.0

25

620

MC1544

MC1444

3.0

18

620

MC1546

MC1446

Type

AC-coupled,

decoded input channel selection,
wired-OR output capability.
output strobe capability,
+5.0V, -6.0V power supply

DC-coupled, decoded input, 0.5 mV input offset.
output strobe capability. +S.OV. -S.OV power supply

3-4

INTEGRATED CIRCUITS

INTERFACE CIRCUITS (Continued)

DRIVERS
terminals, peripheral drivers for driving lamps, relays
and memories, and MOS clock drivers for providing the
required clock pulses to highly-capacitive loads.

Several types of interface drivers are tabulated in this
section: twisted-pair drivers for transmitting data over
long lines, RS-232 drivers for interfacing modems and
TWISTED·PAIR LINE DRIVERS
lo(on)
rnA

Function

~

Dual Driver/Receiver

~ with MECL BiasSupply

~

~ Dual3-lnput Driver

~.,o..,.".,"",."
inputs for party-line
driver applications

~

Type

Case

·5510 +125°C

a to +70 oC

13/13

632

MC1580

-

5.0

15/13

632

MC1582

-

100

9.0/9.0

632.
646#

MC551 09

MC75109

MC55110

MC75110

-

MC75113t

(minImax)

MDTL.
MECL.
MRTL

6.9/10.4

5.0

MDTL.
MTTL.
MRTL

6.9/10.4

3.517.0
MTTL
6.5/15

100

9.0/9.0

632.
646#

18/26

-

25/15

632

Differential Party-Line

Driver with push-pull

IpLH/IPHL
Input to Output
10(0f!)
(ns -Iyp)
- max)

(~A

Compatibility

MDTL

outputs

#Case 646 used with indl,lstrial-temperature-range devices only.
tOto +15°C Temperature Range

RS-232 LINE DRIVER
VOL
Vdc

Function
Quad Line Driver

~
~

&

VOH
Vdc

&

&

Compatibility

min

min

VCC
Vdc

VEE
Vdc

MDTL. MTTL

·6.0
·9.0

+6.0
+9.0

+9.0
+13.2

·9.0
·13.2

:=D--a
:=D--a
"@3000ohms. 15 pF

3-5

tPLH/IPHL
ns
typ

Case

o to +75°C

150/65"

632

MC1488

Type

INTEGRATED CIRCUITS

INTERFACE CIRCUITS (Continued)
~T~'f" 'DI:flvEAS:i;~~iriJ~);-­
,1;

MOS'CLOCK~'Q"'VER$:~'
Function

Input
Compatibility

Switching Times
C = 1000 pF, ns-typ

Temperature

tPLH tTLH tpH L tTH L

(oCI

Caso

Typo

Dual MOS Clock
Driver with Strobe

MDTL,MTTL

2.0 MHz

5.0/·20

55

50

25

22

-55 to +125

632

MC1585

MTTL

4.0 MHz

5.0/·12

13

40

23

35

o to +70

646

MHP401

High-Speed Hybrid
MOS Clock Driver

Function

Dual Memory Driver with
logic inputs, 24·volt

Compatibility

MDTL,MTTL

600

25/25 (to source collectors)
20/20 (to sink outputs)

MDTL,MTTL

300'

21/16

620,

648#

MC55325

MC75325

output capability

1.J

~
rr
1'1

~

Dual Peripheral Positive
AND Driver, plus two
noncommitted NPN
output transistors

Dual Peripheral Positive

AND Driver with logic

632

MC75450

646

MDTL,MTTL

300'

gate outputs internally
connected

-=Case 648 used with industrial-temperature-range devices only.

*Each transistor

3-6

17/18

626

MC75451

INTEGRATED CIRCUITS
INTERFACE CIRCU.ITS (Continued)

RECEIVERS
Mating with the driver types listed in the previous
section are the receivers tabulated in this section:

twisted·pair receivers for computer applications, and
RS·232 receivers to interface with similar drivers.

TWISTED·PAIR LINE RECEIVERS
Input
Threshold
Compatibility ImV -typ)

Function

~

:[>0:

~""

(V-min)

Type
·55 to
Oto
+70 oC

tPLH/tpHL
Input to Output
Ins - typ)
Case

+12SoC

±40

±3.5

13/13

632

MC1580

-

MECL

±1O

±3.5

15/25

632

MC1581

-

MDTL,
MRTL,
MTTL

±2.0

±3.5

24/34

632

MC1583

-

Active Pullup

MDTL,
MTTL

±40

±3.5

32/28

632

MC1584

-

Active Pullup

MTTL

±25

±3.0

17117

Open

Dual Line Receiver

Mode Range

MDTL,MECL,
MRTL,MTTL

Dual Driver/Receiver

~ with MECL BiasSupply

:t:u::

Input Common

Collector
Outputs

632, MC55107 MC75107

646#

""" """.,

with strobe inputs

Open
Collector

±25

MTTL

±3.0

19/19

632,
646# MC55108 MC75108

Output

.::case 646 used with industrial-temperature-range devices only.

RS-232 LINE RECEIVERS
Input

Function

y
y
Y
Y

Quad Line Receiver

Input
Turn-Off

Turn-On
Threshold
IVdc - max)

(Vdc - max)

MDTL,MTTL

1.5

MDTL,MTTL

2.25

Compatibility

Threshold

3-7

Input

Hysteresis
ImV - typ)

tpLH/tpHL
Ins - typ)

Case

1.25

250

25/25

632

MC1489

1.25

1150

25/25

632

MC1489A

Type

o to +75°C

INTEGRATED CIRCUITS
INTERFACE CIRCUITS (continued)

supplies, and interface to saturated logic levels.
Maximum differential input voltage is ±5.0 V and
propagation delay time is 40 ns for all dev ice types
shown.

1.000

5.0

1.000

5.0

25

2.5

4.0

·1.0

700

5.0

100

2.5

5.0

·1.0

o
o

These comparators are designed specifically for single positive·power·supply operation from +2.0 to +28 Vdc. Each monolithic device
contains four independent comparators, yet total package power supply current drain is 1.5 mA max.
eUse Mec prefix for nonencapsulated chip .
• ·Use MCBC prefix for non encapsulated beam-lead device; use MeB prefix for beam-lead device in ceramic flat package.

DEFINITIONS
Open-Loop Voltage Gain
Differential Voltage Range
Input Offset Voltage
Input Bias Current

VOH
VOL
lOs

Positive Output Voltage

lp

Propagation Delay Time

Negative Output Voltage
Output Sink Current

Compatibility
MDTL,
MTTL

0.78

2.0

50

3-8

Case

-55 to +125o C

632

MC1506

MC1406

INTEGRATED CIRCUITS

REGULATORS
Motorola offers a broad line of voltage regulators
ranging from low-cost "Functional Circuits" to
high-precision units. Regulators for positive and negative
voltages are available as well as a unique floating

regulator, type MC1566L, whose maximum output
voltage and current are limited only by the external pass
transistor.

POSITIVE VOLTAGE REGULATORS

4.5

40

2.5

37

2.5

20
200
500
200
500

37

2.5

17

2.0

37

200
500
150

3.0

30

8.5

50

2.0

0.06

0.05 mV

-

0.68

601

MLM105

2.7

40

8.5

40

9.0

0.Q15

0.13
0.05

0.68
3.0

602A
614

MC1569'

0.Q15

0.13
0.05

1.8
17.5
1.8
17.5

0.68
3.0

602A
614

MC1561

0.68
3.0
0.8

602A
614

2.7

40

8.5

40

9.0

2.7

20

8.5

20

9.0

0.Q15

3.0

38

9.5

40

3.5

0.030

0.13
0.05
0.15

1.8
12

30

8.5

50

2.0

0.06

0.05 mV

-

9.0

35

0.2

9.0
9.0

35
35

0.03
0.06

0.2
0.4

9.0

35

0.06

0.4

20
20

0.03
0.03

0.2
0.2

0.06

0.4

0.06

0.4

-

1.0

9.0
9.0

-

0.03

-

0.06

-

,y.

:25 to +85 C Temperature Range

I 4.5 I 40 I

20

I 3.0 I

MC1560
MCl723' ••

603-03.
632.607"

0.68

601

-

1.0

-

1.0
1.0

206A
643A

I MLM205

-10 to +75°C Temperature Range
4.6
4.6

32
32

200
200

3.0
3.0

4.6

32

200

3.0

4.6

32

200

3.0

4.6
4.6

17
17
17
17

200
200

3.0
3.0

-

200

3.0

-

9.0

20

200

3.0

-

9.0

20

-

30

8.5

40

2.0

4.6
4.6

oto +70° C Temperature Range
4.5

30

20

2.5

17

200
500
200
500
200
500

2.0

37

150

2.5

32

2.5

32

3.0

3.0

20

9.0

20

12

0.030.

0.05 mV
0.13
0.05
0.13
0.05
0.13
0.05

3.0

38

9.5

40

4.0

0.030

0.20

3.0

35

9.0

35

12

0.030

3.0

35

9.0

35

12

0.030

• Also available as nonencapsulated chip. use MeC prefix.
"'·Also available as nonencapsulated beam~(ead device; use MCBC prefix. use

Mea prefix for device

-

1.0
1.0

MFC4060A

206A

MFC6030A
MFC4062A

643A
206A

MFC4063A

643A

MFC6033A

MFC6032A

1.0

206A

MFC4064A

1.0

643A

MFC6034A

-

0.68

1.8
17.5

601
602A
614

MC1469'

602A
614

MC1461

1.8
12

0.68
3.0
0.68
3.0
0.68
3.0

-

0.8

1.8
17.5

MLM305

602A
614

MC1460

603-03,
632

MCl723C'

in ceramic flat package.

FIXED OUTPUT POSITIVE VOLTAGE REGULATORS

4.8
4.8
5.75
7.7
11.5
14.4
17.3
23

5.2
5.2
6.25
8.3
12.5
156
18.7
35

1000
1500
1500
1500
1500
1500
1000
1000

2.0
2.0
2.0
2.5
2.5
2.5
3.0
3.0

30
30
29
27
23
20
17
16

7.0
7.0
8.0
10.5
14.5
17.5
21
27

35

10

50

100

20

3.5

11

I MLM1Q.9K

35

10

50

100

20

3.5

11

I MLM209K

35
35
35
35
35
35
35
40

10
8.0
8.0
8.0
8.0
8.0
8.0
8.0

50
100
120
160
240
300
360
480

100
100
120
160
240
300
360
480

20
15
10
10
10
10
10
10

3.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0

11
199-04
199-04
199-04
199-04
199-04
199-04
199-04

-For complete Data Sheet information please contact your Motorola salesman or distributor.

DEFINITIONS
VOR
10
IVin .
Vin
V ref

Vol

Output Voltage Range
Output Current
Input-Output Voltage Differential
Input Voltage

TCVO

Reference Voltage

Po

lIB
Regin
RegL

3-9

Input Bias (Standby) Current

Line Regulation Voltage
Load Regulation Voltage
Temperature Coefficient of Output Voltage
Power Dissipation

MLM309K
MC7805C •
MC7806C •
MC7808C •
MC7812C •
MC7815C •
MC7818C •
MC7824C •

I

INTEGRATED CIRCUITS

REGULATORS (Continued)

I

*Limited only by the characteristics of the external series pass transistor.

3-10

INTEGRATED CIRCUITS

HIGH FREQUENCY AMPLIFIERS
AGe capability or several gain options to provide extra
design flexibility.

Motorola's high-frequency amplifiers simplify the
design of receivers and signal processors. Many offer

HIGH FREQUENCY AMPLIFIERS
Bandwidth
IMHzl

de to 40

VOS
CVp·pl
4.5

Iz;"1
Ikl! @kHzl
6.0

20

Izol

Cl! @ kHzl
35

20

Gp
@60MHz
IdBI

AVS
CdBI

-

90
(fixed I

Type

Diff. Input
and Output
Ves

AGC
No

VCC, VEE
CVdcl

Case

-~~ to
+12SoC

u to
+7S 11 C

±6.0

601

MC1510

MC1410

602A.
607.
632

MC1545

MC1445

de to 75

2.5

10

50

25

50

18
(fixed)

-

Ves

Ves

±S.O

22 min

6.0

1.8

1.0M

100 k

1.0M

26
CAGC" 01

25

No

Ves

+6.0

6028.
606

MC1550

-

40@A v - 34dB
35@ Av" 40 dB

4.2

10

100

16

100

--

No

No

+6.0

602B

MC1552

--

35@ Av ~ 46 d8
15@A v =52dB
100@Av"4.0dB
60@A v " 25 dB
40@A v =52dB
90@A v "40dB
120@Av = 20 dB

4.2
7.0

4.0

10
3.0
4.0
30
250

100
1.0M
1.0
1.0
1.0

16
100 k

20

100
1.0M

1.0

30 -- 40
(fixedl
46 -- 52
(fixed)

44
IAGC = 01
52
40
20

--

No

No

+6.0

602B

MC1553

--

45

Ves

Ves

+12

601

MC1590

--

±6.0

603-02
632

MC1733

MC1733C

--

3-11

Ves

No

I

INTEGRATED CIRCUITS

SPECIAL-PURPOSE CIRCUITS
by the subheadings_ Temperature ranges and package
availability are also tailored to provide versatility_

The linear-integrated-circuits listed in this section
were developed by Motorola for the system design
engineer to fill special-purpose requirements as indicated

MULTIPLIERS'·
:.

.

'.

,

.'. .

I

Input Voltage
Range

Error
{typl

Function

0"

"

Linearity

Type

{Vdc mini

Case

·55 to +125°C
MC1594

A four-quadrant multiplier designed to operate with ±15-volt
supplies: has internal level-shift circuitry and voltage regulator.

±o.3%

±10

620

±o.5%

±10

620

Applications include mUltiply. divide. square root, mean square.
phase detector. frequency doubler. balanced modulator/demodulator. electronic gain control.

X Input - 0.5%
Y Input == 1.0%

±10

632

X Input - 1.0%

±10

632

Y Input = 2.0%

o to +70 oC
MC1494

MCI595·
MC1495·

" *Also ~lIallable as a nonenc:apsu,lated'chip. u,se.MCC prefix.

~BALANCED:'!fAODUlATORIDEMODULATOR
.
.....
.. '

..

Carrier
Suppression

;'

dB@1 {MHzI
{typl

Function
Balanced modulator/demodulator designed for use where the output
voltage is a product of an input voltage (signal) and a ~itching
function (carrier).

.

:.

.

65
50

,.

I

.

.'

Type

Common-Mode
Rejection
{dBtypi

0.5
10

85

,

,

>.

. '.

Case

·55 to +12SoC

602A,
632

MC1596

'.'

o to +75

O

C

MC1496

.

.'

LOWfREQUENCiC:lRCUl'fS

.':.

....

Function

',:
':'.

Darlington hybrid power driver
Dual power driver lor use with
hammer, solenoids, relavs, lamps,
paper tape punches, etc.

,
BVCEO
{Vdcl
30lVP

120 min

,,'

.'

10

•....

:.

.: .

".

.:

.

ton/toff

{Atypl

hFE
{typl

{nsl

Temperature

Ca..

Type

-

1000

3501450 max

·55 to +12SoC

628

MCH2005

6.0

-

26011800 tvp

o to +70 oC

685

MCH2890

3-12

".

,

INTEGRATED CIRCUITS

CONSUMER APPLICA TION SELECTOR GUIDE
... reflecting Motorola's continuing commitment to
semiconductor products necessary for consumer system
designs. The tabulation contains data for a large number
of components designed principally for entertainment

product applications. It is arranged to simplify first-order
of linear integrated circuit device lineups to satisfy primary functions for Television, Audio, Radio, Automotive
and Organ applications.

TELEVISION CIRCUITS
SOUND
Case

Type

80 jJ.V, 3 dB Limiting Sensitivity.
3.5 V(RMSI Output, Sufficient for Single Transistor
Output Stage

646.647

MC1351

Sound IF Detector

I nterchangeable with ULN2111 A

646.647

MC1357

Sound If Detector,

Excellent AMR,
Interchangeable with CA3065

646.647

MC1358

IF Gain @45 MHz - 60 dB typ
AGC Range - 70 dB min

626

MC1349

IF Gain@ 45 MHz - 46 dB typo
AGe Range - 60 dB min

626

MC1350

646,647

MC1352

Same as MC1352, with Opposite AGe for Tuner

646

MC1353

Low-Level Detection,

626

MC1330

Features

Function
Sound IF, Detector, Limiter,
Audio Preamplifier

DC Volume Control, Preamplifier

VIDEO
1st and 2nd Video IF Amplifier

1st and 2nd Video IF, AGe
Keyer and Amplifier

3rd I F and Video Detector

IF Gain @45 MHz - 53 dB typ, AGC Range - 65 dB min,
"Forward AGe" Provided for Tuner

Low Harmonic Generation,
Reduced Circuit Cost and Complexity,
Reduced Shielding
AGC Keyer, AGe Amplifier,
Noise Gate, Sync Separator

High-Quality Noise Gate,
One IF AGC Output and Two Tuner AGC Outputs,
Adjustable AGC Delay

646

MC1345

Automatic Fine Tuning

High Gain AFT System,
Interchangeable with CA3064

646
686

MC1364

Chroma IF Amplifier and
Subcarrier System

Includes Complete Chroma IF, AGe, de Gain
and Tint Controls, Injection Locked Oscillator,
Low Peripheral Parts Count

646

MC1398

Chroma Subcarrier System

Interchangeable with CA3070,
APC Chroma Reference System

64B

MC1370

Chroma IF Amplifier

Interchangeable with CA3071,
Automatic and Manual Gain Control

646

MC1371

Chroma Demodu lators

Similar to MC1328 but with Luminance and
Blanking Inputs,
Internal Matrix Providers RGB Outputs

646,647

MC1326

Industry Standard Demodulator,
Low Differential Output dc Drift

603-02
646,647

MC1328

Dual Doubly Balanced Demodulator with
RGB Output Matrix and PAL Switch

646,647

MC1327

CHROMA

Dual Chroma Demodulator

3-13

CONSUMER APPLICATION SELECTOR GUIDE (Continued I

PREAMPLIFIERS·
Function
..

Avol
(dB min)

THO
(%typ)

(Ohmstyp)

Case

Type

±15
16
33

80
63
80

0.1
0.1
0.1

100
100
100

632
646
644A

MCl303
MC1339
MFC8040

Dual Preamplifier
Dual Low-Noise Preamplifier
Low-Noise Preamplifier

DRIVERS
.

.' .

. ,'
..

, '.',

Zo

Vcc
(Vdc -max)

.,

....

.,

,

,

,

' ·r

',.

,.

,

....

...
....

•

Function
Class A Audio Driver
Class B Audio Drivers

VCC
(Vdc)

Drive Current

(rnA)

(dB)

Case

Type

18
35
20
45

30 min

42 min

150 peak
150 peak
150 peak

89 typ
87 typ
90typ

206A
644A
644A
644A

MFC4050
MFC8020A
MFC8021A
MFC8022A

Ayol

,.

.'
. POWER AMPLIFIERS
ein

Po
Function

(Watts)

Audio Power Amplifiers

0.5
0.25
1.0
1.0
2.0

@ rated Po
(mV-max)

VCC
(Vdc maxi

Po

RL

(mA-max)

(Ohms)

Case

Function

IF Amplifier
limiting FM-IF Amplifier
Limiting IF Ampl/Quadrature Detector
IF Amplifier
IF Amplifier, Nonsaturating Limiter

Lamp Driver
(mA -max)

Function
FM Multiplex Stereo Decoders

Four-Channel SO

Decoders

45
45
40
40

0.5
0.5
0.5
0.3

45

0.1

Quad Comparator

Features

Case

Type

Audio Muting
Audio Muting

646
646

MC1304
MC1305
MC1307
MC1310

646/647
646

Coiltess Operation

646

(Vdc)

VIOR
(Vdc)

(,uA-max)

Current
(rnA-max)

Sink Current

Case

Type

2.0 to 28

±,VCC

0.5

10

6.0

646

MC3302

Range

Function

40
40
40
75

liB

3-14

,

INTEGRATED CIRCUITS
CONSUMER APPLICATION SELECTOR GUIDE (Continued)

ORGAN CIRCUITS
FREOUENCY DIVIDERS
VCC
Range

(Vile)

iTog
(MHz -typ)

tVdc - min}

Case

Type

Toggle Flip·Flop

4.0 to 16

1.0

15.5

206A

MFC4040

Dual Toggle Flip-Flop

4.0 to 16

1.0

15.5

643A

MFC6020

Function

VOH

RHYTHM
Dual Toggle Flip-Flop with Reset

4.0 to 16

1.0

15.5

643A

MFC6050

3-lnput AND Gate

4.0 to 16

-

15

643A

MFC6060

R·S Flip·Flop

4.0 to 16

1.0

15.5

643A

MFC6080

J-K Flip-Flop

4.0 to 16

1.0

15.5

644A

MFC8050

ATTENUATOR

Function

VCC
Range
(Vdc)

(% - typ)

AV
(dB - typ)

Attenuation
Range
(dB - typ)

Ca..

Type

Electronic Attenuator

9.0 to 18

0.6

13

90

643A

MFC6040

THO

3-15

Preview

of
Upcoming
Products
The products described in this
section are presently under development and are expected to be introduced soon. All specifications are
tentative. Additional information on
these devices and their availability
may be obtained from your Motorola
representative.

4-1

I

Preview of Upcoming Devices (continued)

INDUSTRIAL PRODUCTS
Most of the traditional linear Ie types are designed for industrial applications. Several new op
amps and a timing circuit are discussed below. These devices further the diversity of Motorola's
product line-up.

•

MLM108A Operational Amplifier

MC1555 Adjustable Timer

The MLM108A series of high precIsion
operational amplifiers is designed to provide high
input impedance, low input bias currents and low
offset voltages, thus making it possible to eliminate
offset adjustments in most applications. The
devices operate on supply voltages from ±2 V to
±20 V and have sufficient supply rejection to use
unregulated supplies. Feed forward compensation
techniques can be applied to provide increased slew
rates for maximized performance in high speed
Sample-and-Hold circuits and precision high-speed
summing amplifiers.

The MC1555 is a highly stable timing circuit
designed to provide accurate time delays or
oscillations. Both trigger and reset provisions are
available for increased flexibility. In the time delay
mode of operation, the time is precisely controlled
by one external resistor and capacitor. For stable
operation as an oscillator, the free running
frequency and the duty cycle are both accurately
controlled with two external resistors and one
capacitor.
FEATURES:
• Timing from microseconds through hours
• Output can source or sink 200 mA
• TTL compatible
• Operates in both astable and monostable modes
• Adjustable duty cycle
• Temperature stability of 0.005% per °c
• Normally on and normally off output

FEATURES:
• Offset voltage guaranteed less than 0.5 mV
• Low input offset current - 400 pA maximum
• Low input bias currents - 3.0 nA maximum
• Guaranteed maximum input offset drift 5

}J.vtc

MCl776 Programmable Low Power Operational Amplifier

MC1741S Operational Amplifier
The MC1741S is an internally compensated,
high-performance monolithic operational amplifier
designed to provide a wide power bandwidth. It is
similar in other electrical characteristics and pin
compatible with the MC1741. Application possibilities include AID converters, oscillators, active
filters or general purpose amplifiers.

The MC1776 offers the user high-input
impedance, low-power supply currents, and lowinput noise over a wide range of operating supply
voltages. Power consumption. input current, and
noise resulting from both input voltage and current
can be optimized by the selection of a single
resistor or current source that sets the chip
quiescent currents for microwatt power consumption.

FEATURES:
• 10 V/p.s slew rate
• Pin compatible with MC1741 op amp
• 500 kHz power bandwidth

FEATURES:
• Micropower consumption
• ± 1.2 V to ± 18 V operation
• Low input bias currents
• High slew rate
• Offset null capability

4-2

Preview of Upcoming Devices (continued)

CONSUMER PRODUCTS
The rapid trend to ICs in television, stereo and FM radio equipment has permitted the
development of many new, advanced ICs for these product types. Particularly in television the
diversity of available functions is rapidly expanding. A number of device types which will be
introduced in the near future are summarized below.

MC1391 TV Horizontal Processor
The MCl391 TV horizontal processor packs the
phase detector, oscillator and pre-driver functions
into a single, convenient 8-lead plastic package.
The new unit provides the entire low-level
horizontal signal processing function and may be
used with either transistor or vacuum tube output
stages. This device is one of the first inroads of ICs
into the television deflection circuitry.

MC1344 TV Signal Processor

FEATURES:
• Internal shunt regulator
• Preset Hold control capability
• ±300 Hz typical pull-in range
• Balanced phase detector
• Variable output duty cycle for driving tube or
transistor
• Low thermal frequency drift
• Small static phase error

The MC1344 TV signal processor provides a
collection of common television processing functions. It combines the sync separator, advanced
noise inverter, AGC comparator and both positive
and negative-going RF AGC delay amplifier into a
single package.
This device is an improved version of the
MC1345. It features greater thermal noise performance and modified negative RF amplifier AGC
response. A number of important features are
tabulated below.
FEATURES:
• Video internally delayed for total noise
inversion
• Low impedance, noise cancelled sync output
• Refined AGC gate
• Small IF AGC output change during RF AGC
internal
• Positive and negative going RF AGC outputs
• Noise threshold may be externally adjusted
• Time constants for sync separator externally
chosen
• Stabilized for ±10% supply voltage variations

MC1359 TV Sound System
The MC1359 is a complete sound system for a
television receiver. It includes the IF amplifier,
detector, electronic volume control, and audio
amplifier. The IC provides two watts of audio
output. All this is packed into a single plastic
package with two heat dissipating tabs.
The dc voltage-controlled volume attenuator
saves the necessity of long lengths of shielded cable
between the volume control and the audio
amplifier circuitry. This advanced system provides
80 dB of audio attenuation range.
FEATURES:
• Excellent AM rejection
• DC volume control with 80 dB
attenuation range
• Signal to noise ra~io ~ 63 dB typical
• Few external components required

typical

4-3

I

Preview of Upcoming Devices (continued)

MC1315 CBS SO Logic Circuits

MC1314 CBS SO Logic Circuits

The MC1315 provides the basic logic function
for enhancing the front to back separation in the
CBS sa four channel decoding system. The new
IC is designed to interface with the MC1312
decoder and MC1314 balance control unit. The
MC1315 provides variable logic enhancement
control and supplies the dc gain control and
balance signals to the MC1314.
This unit extends the performance of the basic
sa system to the levels desired for top-of-the-line
systems.

The MC1314 is a gain control and balance
adjustment unit for use with the CBS sa system
decoders. It consists of four amplifiers, with the
gain of each being adjustable by varying a dc
voltage. Thus with four variable resistors, the
master volume and LFIRF LB/RB and FIB
balance may be controlled.
'
The unit also has inputs which may be
connected to the MC1315 logic enhancement unit
to provide increased front to back separation. This
feature is highly desirable in high performance four
channel stereo systems.

FEATURES:
• Provides logic enhancement to extend front to
back separation to 12 dB
• Low external parts count
• Provisions for enhancement controls
• Provides dc gain control signals to the MC1314

FEATURES:
• DC controlled gain
• Four separate audio preamplifiers
• Compatible with MC1312 decoder and MC1315
logic enhancement unit

MC1311 FM Stereo Demodulator

MC1375 FM IF Circuit

The MC1311 phase locked loop stereo demodulator is an modified version of the popular
MC1310 type. The new circuit provides emitter
follower outputs and 6 dB of gain. It retains the
low external parts count (no inductors). simplified
alignment and high performance of its predecessor.
The new IC also contains a stereo indicator
lamp driver which incorporates 6 dB of hysteresis
to avoid flickering due to noise.

Combining several functions required in solidstate FM receivers, the MC1375 provides the IF
amplifier, limiter, FM detector and audio preamplifier in a single 14-lead package. The unit
requires a minimum of external components.
The I F amplifier/limiter section provides
excellent AM rejection and uses an internal zener
diode voltage regulator. The detector is a
differential peak design which promotes simplified
single·coil alignment. The audio preamplifier
supplies a voltage gain of ten.

FEATURES:
• Emitter follower outputs
• Requires no inductors
• Low external part count
• Includes 6 dB typical gain

FEATURES:
• Good sensitivity: input limiting voltage (Knee)
= 250 jJV typical
• Excellent AM rejection: 55 dB typical at 10.7
MHz
• Internal zener diode regulation for the IF
amplifier section
• Low harmonic distortion
• Differential peak detection: permits simplified
single·coil timing
• Audio preamplifier voltage gain: 21 dB typical

4-4

Preview of Upcoming Devices (continued)

LINEAR DIGITAL INTERFACE PRODUCTS
The rapid expansion in computer·control, data communications and digital instrumentations
has led to the development of a myriad of new analog·digital interface ICs. A few of the most
recent developments in Motorola's efforts in this field will be discussed below.

MC1504 Quad Current Switch
The MC1504 is a monolithic quad current
switch designed for an optimum combination of
accuracy, switching speed and stability as required
in precision D/A converters. Several units may be
cascaded with a 16:1 interquad attenuation to
make complete converters with up to 12 bit
accuracy. The current switch is coupled with an
external ladder network to produce the D/A
function. A reference transistor is included for use
in termperature compensating circuitry.
FEATURES:
• ±0.01 % maximum nonlinearity
• 40 ns switching time
• 200 ns settling time
• 1 ppmtC temperature coefficient

MC1508 8·Bit DIA Converter
The MC1508 monolithic 8·bit D/A converter is
designed for use in applications requiring an output
current which is the linear product of an analog
input voltage and an 8·bit digital word. It is similar
to the MC 1506 6·bit D/ A converter in basic design
except that the new unit has non·inverting logic
inputs and a faster reference amp I ifier for
multiplying applications. An additional pin has
been provided for extending the output voltage
swing in the negative direction to ·5 V.
FEATURES:
• Fast settling time
• Non·inverting operation
• Low power consumption
• Maximum error of ±0.19%

MC1507 AID Converter Subsystem
The MC1507 is a monolithic subsystem
designed for use in A/D converters and instrumen·
tation applications. It consists of a high slew rate,
wide·bandwidth op amp and a dual threshold
voltage comparator. The comparator features low
input currents and separate outputs for both
thresholds. A very economical tracking A/D system
can be assembled using the MC1507 in conjunction
with the MC1508 8·bit D/A converter and a TTL
Up/Down counter.
FEATURES:
• Low input offset voltage
• Standard power supply: ±15 V and +5 V
• Differential reference input sets both thresholds
• Op amp has 20 MHz bandwidth in unity gain
mode

4-5

•

•

Preview of Upcoming Devices (continued)

MLMIII Series Voltage Comparator

MMH0026 Dual MOS Clock Driver

The M LM III voltage comparator is designed to
operate over a wide range of supply voltages. The
comparator may be operated from ±15 V supplies
as used with op amps or a single +5 V supply as
used with digital logic systems. Both the inputs and
outputs of the MLMIII can be isolated from system
ground and the output can drive loads referenced
to ground, the positive or the negative supply.
Offset balancing and strobe capability are provided
and outputs can be Wire-ORed.

The MMH0026 is a monolithic, high-speed,
two-phase MOS clock driver. The device accepts
standard DTL/TTL inputs and converts them to
MOS logic levels. It has the ability to drive large
capacitive loads. The MMH0026 is intended for
applications in which the output pulse width is
logically controlled; i.e. the output pulse width is
equal to the input pulse width.
FEATURES:
• Fast rise and fall times - 20 ns with 1000 pF
load
• 20 V output swing
• ± 1.5 amps output current drive
• Drives to within 0.4 V of ground for RAM
add ress drive applications

FEATURES:
• May operate from single 5 V supply
• Input current: 150 nA maximum
• Offset current: 20 nA maximum
• Differential input voltage range: ±30 V

MC75452-MC75453-MC75454
pheral Drivers

Dual

Peri-

MC75491, MC75492 MOS to VLED Segment & Digit Drivers

The MC75452, 453, 454 series of dual
peripheral drivers are designed for use as general
purpose interface functions in DTL/TTL systems.
The drivers consist of two logic gates whose
outputs are i nterna lIy con nected to the bases of
two high current, high voltage NPN transistors.
Typical applications include relay and lamp drivers,
power drivers, MOS and memory drivers. The
MC75452 is a positive NAND function, the
MC75453 is a positive OR function while the
MC75454 is a positive NOR function.

The MC75491 and MC75492 are monolithic
drivers for use with visable light emitting diode
(VLED) displays. They were designed to provide
the interface between MOS logic and common
cathode VLEDs in serially addressed, multi-digit
displays. This time multiplexed system using a
segment address and digit scan method of VLED
drive minimizes the number of derivers required.
The MC75491 devices have a separate connection
for the emitter of each output transistor while the
MC75492 devices have the emitters internally
connected to the VDD terminal.

FEATURES:
• 300 mA output drive capability
• High output breakdown voltage: BVCER = 30 V
minimum
• DTL/TTL compatible inputs

FEATURES:

MC75491
• 50 mA source or sink current capability
• Low input current for MOS compatibility
• Low stand-by power
• Quad high-gain Darlington circuits
MC75492
• 250 mA sink current capability
• Low input current for MOS capability
• Low stand-by power
• Hex high-gain Darlington Circuits

4-6

LINEAR
INTEGRATED CIRCUITS

INTERCHANGEABILITY GUIDE
This interchangeability guide describes equivalent circuits in two ways:
(1) the "Direct Replacement" which is both electrically and mechanically
a direct replacement; and, (2) the "Functional Equivalent" that is generally
superior in electrical characteristics, however may differ in package dimensions or lead configurations. When a functional equivalent circuit is used
for a replacement, the specific data sheet should be consulted.
Packaging availability information for each Motorola device is listed in
the Linear Application Selector Guides section and also appears on the
individual data sheet for the device. Exact outline dimensions are shown
in the Packaging Information section of this data book.
MANUFACTURERS REFERENCED
Fairchild Semiconductor
National Semiconductor
RCA
Signetics
Texas Instruments

5-1

•

FAIRCHILD INSTRUMENTS TO MOTOROLA
FAIRCHILD
DEVICE NUMBER
DEVICE
TYPE

ORDER CODE

JlA702

U3F 7702312
U3F 7702313
U5B 7702312
U5B 7702393
U6A 7702312
U6A 7702393

JlA703

U5D 7703312
U5D 7703393
U5D 7703394

JlA709

itA710

JlA711

JlA719

JlA723

JlA729
JlA732
JlA733

JlA739

JlA741

JlA746

JlA747

MOTOROLA
DIRECT
EQUIVALENT

DEVICE
TYPE

MC1712F
MC1712CF
MC1712G
MC1712CG
MC1712L
MC1712CL
MFC6010
MFC6010
MFC6010

U3F 7709311
U3F 7709312
U3F 7709313
U5B 7709311
U5B 7709312
U5B 7709393
U6A 7709311
U6A 7709312
U6A 7709393
U3F 7710312
U3F 7710313
U5B 7710312
U5B 7710393
U6A 7710312
U6A 7710393

MC1709F
MC1709F
MC1709CF
MC1709G
MCI709G
MC1709CG
MC1709L
MC1709L
MC1709CL
MC1710F
MC1710CF
MC1710G
MC1710CG
MC1710L
MC1710CL

U3F 7711 312
U3F 7711 313
U5F 7711 312
U5F 7711 393
U6A 7711 312
U6A 7711 393
U5F 7719312
U5F 7719393

MC1711F
MC1711CF
MC1711G
MC1711CG
MC1711L
MC1711CL

U5R
U5R
U6A
U6A
U6A
U6A

7723312
7723393
7723312
7723393
7729394
7732 394

MCI723G
MCI723CG
MCI723L
MCI723CL
MC1305P
MC1304P

U3F 7733312
U3F 7733313
U5F 7733312
U5F 7733393
U6A 7733312
U6A 7733393
U6A 7739312
U6A 7739393

MC1733F
MC1733CF
MC1733G
MC1733CG
MC1733L
MC1733CL
MC1303P
MC1303P

U3F 7741 312
U3F 7741 313
U5B 7741 312
U5B 7741 393
U6A 7741312
U6A 7741 393
U6T 7741393
U9T 7741 393

MC1741F
MC1741CF
MC1741G
MC1741CG
MC1741L
MC1741CL
MC1741CP2
MC1741CPl

U5E 7746394
U6A 7746394

MC1328P

U5F 7747312
U5F 7747393
U6W 7747 312
U6W 7747 393
U7A 7747 312
U7A 7747 393

FAIRCHILD
DEVICE NUMBER

MOTOROLA
FUNCTIONAL
EQUIVALENT

JlA748

U3F 7748312
U3F 7748313
U5B 7748 312
U5B 7748 393
U6A 7748 312
U6A 7748 393
U6T 7748393
U9T 7748 393

JlA754

U5E 7754393
U6A 7754394
U6A 7757 312
U6A 7757393
U6A 7780 394
U6A 7781 394
U6A 7795 312
U6A 7795312
U6A 7795 393
U5E 7796312
U5E 7796393
U7B 7524 392
U7B 7525393
UGH 7805 393
UGH 7806393
UGH 7808 393
UGH 7812 393
UGH 7815393
UGH 7818393
UGH 7824393

JlA757

JlA767
JlA780
JlA781
JlA795
JlA796
JlA7524
JlA7525
JlA7805
JlA7806
JlA7808
JlA7812
JlA7815
JlA7818
JlA7824

MC1357
MC1357

MC1558G
MC1458G
MC1558L
MC155BCL
MC1558L
MC1558CL

5-2

MOTOROLA
FUNCTIONAL
EQUIVALENT

MC174BF
MC174BCF
MC1748G
MC1748CG
MC1748L
MC1748CL
MC1748CP2
MC1748CPl
MC1355P
MC1355P
MC1350P
MC1350P
MC1307P
MC1370P
MC1371P
MC1595L
MC1595CL
MC1596G
MC1596CG
MC7524
MC7524
MC7805CP
MC7806CP
MC7808CP
MC7812CP
MC7815CP
MC7818CP
MC7824CP

JlA9614

U4L
U4L
U7B
U7B

9614 51X
961459X
9614 51X
9614 59X

MC1582L
MC1582L
MC1582L
MC1582L

JlA9615

U4L
U4L
U78
U7B

9615
9615
9615
9615

51X
59X
51X
59X

MC1584L
MC1584L
MC1584L
MC1584L

JlA9620

U31962051X
U31 962059X
U6A 9620 51X
U6A 9620 59X

MC1580L
MC1580L
MC1580L
MC1580L

JlA9621

U31
U31
U6A
U6A

MC1584L
MC1584L
MC1584L
MC1584L

JlA9622

U31 962251X
U31 962259X
U6A 9622 51X
U6A 9622 59X
CA 3064/5A
CA 3065/7F
CA 3075/

CA3064
CA3065
CA3075

MC1328P

ORDER CODE

MOTOROLA
DIRECT
EQUIVALENT

9621 51X
962159X
9621 51X
9621 59X

MC1583
MC1583
MC1583
MC1583
MC1364G
MC1358PQ
MC1375P

NATIONAL TO MOTOROLA
NATIONAL
TYPE
NUMBER
LH101F
LH101H
LH201H
LM100H
LM101H

MOTOROLA
DIRECT
REPLACEMENT

MC1748G
MLM101AG
MLMll0G
MLM104G
MLM105G

LM107H
LM108H
LM108AH
LM109K
LM110H

MLM107G

LM202H
LM204H
LM205H
LM206G
LM207H
LM208H
LM209K
LM210H
LM212H
LM218H
LM300H
LM301AH
LM301AN
LM302H
LM304H
LM305H
LM306H
LM307H
LM308H
LM308AH
LM309K
LM310H
LM312H
LM318H
LM350N
LM351N
LM370H
LM370N
LM371H

MC1710G

MC1556G
MC1556G
MLM109K
MLM110G
MC1556G
MC1539G
MCl723CG
MC1748CG
MLM201AG
MLM210G
MLM204G
MLM205G
MC1710CG
MLM207G
MC1456G
MLM209K
MLM210G
MC1456G
MC1439G
MCl723CG
MLM301AG
MLM301API
MLM310G
MLM304G
MLM305G
MC1710CG
MLM307G
MC1456G
MC1456G
MLM309K
MLM310G
MC1456G
MC1439G
MC75450P
MC75453P
MC1590G
MC1350P
MFC6010

LM376N
LM380N
LM381N
LM382N
LM703LN
LM709H
LM709CH
LM709CN
LM710H
LM710CH

NATIONAL
TYPE
NUMBER

MC1741F
MC1741G
MC1741G
MCl723G

LM101AH
LM102H
LM104H
LM105H
LM106H

LMl12H
LM118H
LM200H
LM201H
LM201AH

MOTOROLA
FUNCTIONAL
EQUIVALENT

MFC6030A
MFC9020
MC1339P
MC1339P
MFC6010
MC1709G
MC1709CG
MC1709CP2
MC1710G
MC1710CG

5-3

MOTOROLA
DIRECT
REPLACEMENT

LM710CN
LM711H
LM711CH
LM723D
LM723H

MC1710CP
MC1711G
MC1711CG
M:1723L
MCl723G

LM723CD
LM723CH
LM733D
LM733H
LM733CD

MC1723CL
MCl723CG
MC1733L
MC1733G
MC1733CL

LM733CH
LM741D
LM741F
LM741H
LM741CD

MC1733CD
MC1741L
MC1741F
MC1741G
MC1741CL

LM741CH
LM741CN
LM741CN-14
LM746N
LM747D

MC1741CG
MC1741CPl
MC1741CP2
MC1328P
MC1747L

LM747CC
LM748H
LM748CH
LM1303N
LM1304N

MC1747CL
MC1748G
MC1748CG
MC1303L
MC1304P

LM1305N
LM1310N
LM1307N
LM1351N

MC1305P
MC1310P
MC1307P
MC1351P

LM1414J
LM1414N
LM1458H
LM1458N
LM1489J

MC1414L
MC1414L
MC1458G
MC1458Pl
MC1489L

LM1489AJ
LM1496H
LM1496N
LM1514J
LM1558H

MC1489AL
MC1496G
MC1496L
MC1514L
MC1558G

LM1596H
LM2111N
LM3064H
LM3064N
LM3065N

MC1596G
MC1357P
MC1364G
MC1364P
MC1358P

LM3067N
LM3070N
LM3071N
LM3900N
LM3901N
LM5520J

MC1370P
MC1371P
MC3401P
MC3302P

MOTOROLA
FUNCTIONAL
EQUIVALENT

I

MC1328P

MC7520L

LM5521J
LM5523J
LM5525J
LM5528J
LM5529J

MC7521L
MC7523L
MC7525L
MC7528L
MC7529L

LM5534J
LM5535J
LM5538J
LM5539J
LM7520J

MC7534L
MC7535L
MC7538L
MC7539L
MC7520L

I

NATIONAL TO MOTOROLA
NATIONAL
TYPE
NUMBER

MOTOROLA
DIRECT
REPLACEMENT

LM7520N
LM7521J
LM7521N
LM7522J
LM7522N

MC7520L
MC7521L
ML7521L
ML7522L
MC7522L

LM7523J
LM7523N
LM7524J
LM7524N
LM7525J

MC7523L
MC7523L
MC7524L
MC7524L
MC7525L

LM7525N
LM7528J
LM7528N
LM7529J

MC7525L
MC7528L
MC7528L
MC7529L

LM7529N
LM7534J
LM7534N
LM7535J
LM7535N

MC7529L
MC7534L
MG7534L
MC7535L
MC7535L

LM7538J
LM7538N
LM7539J
LM7539N
LM75450AN

MC7538L
MC7538L
MC7539L
MC7539L

LM75451AN
LM75452N
LM75453N

(continued)
MOTOROLA
FUNCTIONAL
EQUIVALENT

MC75450P
MC75451P
MC75452P
MC75453P

5-4

RCA TO MOTOROLA
RCA
DEVICE NUMBER

MOTOROLA
DIRECT
EQUIVALENT

MOTOROLA
FUNCTIONAL
EQUIVALENT

RCA
DEVICE NUMBER

MOTOROLA
DIRECT
EQUIVALENT

MOTOROLA
FUNCTIONAL
EQUIVALENT

CA3000
CA3001
CA3002
CA3004
CA3005

MC1550G
MC1550G
MC1550G
MC1550G
MC1550G

CA3047A
CA3048
CA3052
CA3053
CA3055

MC1433L
MC3401P
MC1339P
MC1550G
MC1723G

CA3006
CA3007
CA3008
CA3008A
CA3010

MC1550G
MC1550G
MC1709F
MC1709F
MC1709G

CA3056
CA3056A
CA3058
CA3059
CA3064

MC1741CG
MC1741G
MFC8070
MFC8070

CA3010A
CA3011
CA3012
CA3013
CA3014

MC1709G
MC1590G
MC1590G
MC1355P
MC1357P

CA3065
CA3066
CA3067
CA3070
CA3071

CA3015
CA3015A
CA3016
CA3016A
CA3020

MC1709G
MC1709G
MC1709F
MC1709F
MC1554G

CA3072
CA3075
CA3076
CA3079
CA3085

CA3020A
CA3021
CA3022
CA3023
CA3028A

MC1554G
MC1590G
MC1590G
MC1590G
MC1550G

CA3085A
CA30858
CA3090Q
CA3741T
CA3741CT

CA30288
CA3029
CA3029A
CA3030
CA3030A

MC1550G
MC1709CP2
MC1709CP2
MC1709CP2
MC1709CP2

CA3031
CA3032
CA3033
CA3033A
CA3035

MC1533L
MC1533L
MC1352P
MC1709L
MC1709L
MC1709L
MC1709L
MC1510G

CA3041
CA3042
CA3043
CA3047

MC1351P
MC1357P
MC1357P
MC1433L

MC1358
MC1398P
MC1328P
MC1370P
MC1371P
MC1328P
MC1351P
MC1590G
MFC8070
MCl723G
MC1723G
MC1723G
MC1310P
MC1741G
MC1741CG

I

MC1712
MC1712L

CA3037
CA3037A
CA3038
CA3038A
CA3040

MC1364

5-5

I

SIGNETICS TO MOTOROLA
SIGNETICS
TYPE
NUMBER

MOTOROLA
FUNCTIONAL
EQUIVALENT

SIGNETICS
TYPE
NUMBER

MOTOROLA
DIRECT
REPLACEMENT

NE501A
NE501K
NE510A
NE510J
NE515A

MC1733CL
MC1733CG
MFC8000P
MFC8000P
MC1420G

N7523B
N7524B

MC7523P
MC7524P
MC7525P

NE515G
NE515K
NE516A
NE516G
NE516K

MC1520F
MC1420G
MC1420G
MC1520F
MC1420G

N7525B
SE501K
SE510A
SE510J
SE515G

NE518A
NE518G
NE518K
NE528B

MLM306G
MLM306G
MLM306G
MC1444L

NE528E
NE531G
NE531T
NE531V
NE533G

MCl444L
MCl439G
MC1439G
MC1439PZ
MCl776CG

NE533V
NE533T
NE537G
NE537T
PA239A

MCl776CG
MCl776CG
MC1456G
MC1456G

NE540L
NE550A
NE550L
N5070B
N5071A

MOTOROLA
DIRECT
REPLACEMENT

MC1339
MFC8020A
MFC6030A
MCl723CG
MC1370
MC1371

N5072A
N5111
N5556T
N5556V
N5558V

MC1328
MC1357
MC1456G
MC1458Pl

N5558T
N5558F
N5595A
N5595F
N5596A

MC1458G
MC1458L
MC1495L
MC1495L
MC1496L

N5596K
N5709A
N5709G
N5709T
N5709V

MC1496G
MC1709CP2
MC1709CF
MC1709CG
MC1709CP1

N5710A
N5710T
N5711A
N5711K
N5723A

MC1710CP
MC1710CG
MC1711CP
MC1711CG

N5723T
N5733K
N5741A
N5741T
N5741V

MCl723CG
MC1733CG
MC1741CP2
MC1741CG
MC1741CPl

N5747A
N5747F
N5748A
N5748T

MC1747CL
MC1747CL

N7520B
N7521B
N7522B

MC7520P
MC7521P
MC7522P

MC1733G
MFC8000P
MFC8000P
MC1520F

SE515K
SE516A
SE516G
SE516K
SE518A

MC1520G
MC1520G
MC1520F
MC1520G
MLM106G

SE518G
SE518K
SE528E
SE528R
SE531G

MLM106G
MLM106G
MC1544L
MC1544L
MC1539G

SE531T
SE533G
SE533T
SE537G
SE537T

MC1539G
MCl776G
MCl776G
MC1556G
MC1556G

SE540L
SE550L
S5556T
S5558T
S5558F

MFC8020A
MCl723G
MC1556G
MC1558G
MC1558L

S5595F
S5596K
S5596F
S5709G
S5709T

MC1595L
MC1596G
MC1596L
MC1709F
MC1709G

S5710T
S5711K
S5723T
S5733K
S5741T

MC1710G
MC1711G
MCl723G
MC1733G
MC1741G

MC1456G

MFC6030A

MC1747CG
MC1748CG

5-6

MOTOROLA
FUNCTIONAL
EQUIVALENT

TEXAS INSTRUMENTS TO MOTOROLA
T.I.
TYPE
NUMBER
SN5500F
SN5510F
SN5510L
SN5511 F
SN5511L
SN5524J
SN5525J
SN5528J
SN5529J
SN5534J

MOTOROLA
DIRECT
REPLACEMENT

MC1510F
MC1510G
MC1510F
MC1510G
MC7524L
MC7524L
MC5528L
MC5529L
MC5534L

SN5535J
SN5538J
SN5539J
SN7510F
SN7510L
SN7511L

MC5535L
MC5538L
MC5539L
MC1410F
MC1410G

SN7520J
SN7520N
SN7521J
SN7521 N
SN7522J

MC7520L
MC7520L
MC7521L
MC7521L
MC7522L

SN7522N
SN7523J
SN7523N
SN7524J
SN7524N

MC7522L
MC7523L
MC7523L
MC7524L
MC7524L

SN7525J
SN7525N
SN7528J
SN7528N
SN7529J

MC7525L
MC7525L
MC7528L
MC7528L
MC7529L

SN7529N
SN52101AL
SN52106L
SN52107L
SN52558L

MC7529L
MLM101AG
MLM106G
MLM107G
MC1558G

SN52702F
SN52702L
SN52702N
SN52702Z
SN52709F

MC1712F
MC1712G
MC1712L
MC1712F
MC1709F

SN52709L
SN52710J
SN52710L
SN52710N
SN52710S

MC1709G
MC1710L
MC1710G
MC1710P
MC1710F

SN52711J
SN52711L
SN52711S
SN52733L
SN52741J

MC1711L
MC1711G
MC1711F
MC1733G
MC1741L

SN52741L
SN52741Z
SN52747J
SN52748J
SN52748L

MC1741G
MC1741F
MC1747L

SN52770L
SN52771L
SN55107J
SN55108J
SN55109J

MOTOROLA
FUNCTIONAL
EQUIVALENT

T.I.
TYPE
NUMBER

MOTOROLA
DIRECT
REPLACEMENT

SN55110J
SN55325J
SN56514L
SN72301AL
SN72301AN
SN72301AP

MC55110L
MC55325L

SN72306L
SN72307L
SN72558L
SN72558P
SN72702F

MLM306L
MLM307G
MC1458G
MC1458Pl
MC1712CF

SN72702L
SN72702N
SN72709L
SN72709N

MC1712CG
MC1712CL
MC1709CG
MC1709CP2

SN72709P
SN72709S
SN72710J
SN72710L
SN72710N

MC1709CPl
MC1709CF
MC1710CL
MC1710CG
MC1710CP2

SN72710S
SN72711J
SN72711L
SN7271N
SN72611S

MC1710CF
MC1711CL
MC1711CG
MC1711CP2
MC1711CF

SN72720N
SN72733L
SN72733N
SN72741J
SN72741L

MC1414L
MC1733CG
MC1733CL
MC1741CL
MC1741CG

SN72741N
SN72741P
SN72741Z
SN72747J
SN72747N

MC1741CP2
MC1741CPl
MC1741CF
MC1747CL
MC1747CL

SN72748L
SN72770L
SN72771L
SN75107J
SN75107N

MC1748CG

MC75107L
MC75107L

SN75108J
SN75108N
SN75109J
SN75109N
SN75110J

MC75108L
MC75108L
MC75109L
MC75109L
MC75110L

SN75110N
SN75150J
SN75150N
SN75154J
SN75154N

MC75110L

MOTOROLA
FUNCTIONAL
EQUIVALENT

MC1596G
MLM301AG
MLM301APl
MLM301APl

MC1410G

SN75234J
SN75235J
SN75238J
SN75239J
SN75325J

MC1748G
MC1748G

SN75450N
SN75450AN
SN75451P
SN75451AP

MC1556G
MC1556G
MC55107L
MC55108L
MC55109L

5-7

MC1456G
MC1456G

MC1488L
MC1488L
MC1489AL
MC1489AL
MC7534L
MC7535L
MC7538L
MC7539L
MC75325L
MC75450P2
MC75450P2
MC75451P
MC75451P

TEXAS INSTRUMENTS TO MOTOROLA
T.I.
TYPE
NUMBER

MOTOROLA
DIRECT
REPLACEMENT

SN75452P
SN75453P
SN75454P
SN76104N
SN76105N

MC75452P
MC75453P
MC75454P
MC1304P
MC1305P

SN76107N
SN76242N
SN76243N
SN76246N
SN76514L

MC1307P
MC1370P
MC1371P
MC1328P

(continued)

MOTOROLA
FUNCTIONAL
EQUIVALENT

MC1496G

SN76514N
SN76530P
SN76564N
SN76600P
SN76642N

MC1330P
MC1364P
MC1350P
MC1350P

SN76650N
SN76651N
SN76653N
SN76665N
SN76675N

MC1352P
MC1351P
MC1353P
MC1358P
MC1375P

MC1496L

I

5-8

r------------------------GENERALINFORMATION----------------------~

STANDARD FEATURES for LINEAR INTEGRATED CIRCUIT CHIPS
(See MCC and MCCF prefix data sheets for device specifications)
All linear integrated circuit chips ....
• are 100% electrically tested to sufficient parameter limits (minimax) to permit distinct identification
as either premium or industrial versions
•

employ phosphorsilicate passivation which protects the entire active surface area including metaliza·
tion interconnects during shipping and handling

• are 100% visually inspected to the criteria of MIL·STD·883, Method 2010.1, Condition B
•

incorporate a minimum of 4000

A gold

backing to insure positive adherence bonding.

FEATURES for BEAM-LEAD CHIPS
(See MCBC prefix data sheets for device specifications)
Beam lead linear integrated circuit chips ....
•

are processed to the same criteria as the digital beam-lead integrated circuits to insure the same
reliability and performance features.

STANDARD CHIP PROCESSING
The industry·standard linear integrated circuits offered in Motorola's Microcircuit Components line
are subjected to the same in·process controls as Motorola's standard encapsulated devices. The chip
processing and quality control requirements are designed to insure reliability and performance of
the finished product.
The processing and quality control flow chart shows that all wafer processing is completed prior to
wafer assignment for subsequent encapsulation or special testing required for unencapsulated devices.

I
Wafer Assigned to Production

of Encapsulated Devices

Wafer
Processing

f---

100%
Visual Inspection

f--

Wafer
Classification
100% Probe

·Chips are visually inspected to MIL·STD·883,
Method 2010.1, Condition

a,

and rejects removed.

6-1

J

f--

Scribe
and
Break

L

Q.C. (Samplel

Visual
Inspection

--r---

100% Visual

Inspection·
Carrier Loading

Chip
Shipment

1

I

r-----------------------GENERALINFORMATION-----------------------.

NON-STANDARD CHIP PROCESSING
The industry standard unencapsulated integrated circuits are selected to meet a wide variety of
application requirements. Nevertheless, there may be occasions when a designer can benefit from a
non-standard device for a specific circuit requirement. To satisfy these requirements, almost any
device from Motorola's extensive line of linear integrated circuits may be obtained on a specially negotiated basis. Although the electrical specifications of these chips are limited by certain test limitations,
the customer may negotiate additional tests. Moreover, various chip technologies such as solder-bump
and chrome-silver backing are available on a specially negotiated basis.

HANDLING PRECAUTIONS
Metalization interconnect passivation on all chips provides protection in shipping and handling.
However, care should be exercised to prevent damaging the bonding pads. A vacuum pickup is useful
for th is purpose, tweezers are not recommended.
There are four basic requirements for handling devices in the customer's establishment:

1. Store devices in a covered or sealed container.
2. Store devices in an environment of no more than 30% relative humidity.
3. Process devices in a non-inert atomosphere not exceeding 1000 , or in an
inert atmosphere not exceeding 400 0 C.
4. Processing equipment should conform to the minimum standards of equipment
normally employed by semiconductor manufacturers.
Motorola's engineering staff is available for consultation in the event of correlation or processing
problems encountered in the use of Motorola semiconductor chips. For assistance of this nature,
please contact your nearest Motorola sales representative.

STANDARD CARRIER PACKAGES
The non-spill type shipping carrier consists of a compartmentalized tray and fitted transparent
cover. Each chip is placed in its compartment, geometry side up, so that incoming visual inspection
may be performed prior to breaking the carrier seal. The shipping carrier is designed to:
•

provide maximum device protection

•

permit the customer to remove only a portion of the devices - the carrier can be resealed

•

provide a storage container for the unused devices.

Additional package techniques are under development to facilitate handling, visual inspection and
chip storage.
Various packaging and shipping options are available on a negotiated basis. For more information
on thes~ options, please contact your Motorola sales representative.

RECOMMENDED INCOMING INSPECTION
Motorola certifies that the devices have been subjected to the visual criteria of MI L·STD-883,
Method 2010.1, Condition B.
Should the lot fail the customer's incoming visual inspection, the entire lot, with the package seals
intact, shall be returned to Motorola. Incoming visual inspection should be performed prior to breaking
the package seals. In no case will Motorola accept a partial return of devices.

6-2

MC1303L

~~_______D
__
U_A_L_S_T_E_R_E_O_P_R_E_A_M_P_L_I_F_IE_R~

DUAL
STEREO PREAMPLIFIER
INTEGRATED CIRCUIT

MONOLITHIC DUAL STEREO PREAMPLIFIER

... designed for amplifying low·level stereo audio signals with two
preamplifiers built into a single monolithic semiconductor.

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

Each Preamplifier Features:
•

Large Output Voltage Swing - 4.0 V(rms) min

•

High Open·Loop Voltage Gain = 6000 min

• Channel Separation = 60 dB min at 10kHz
• Short·Circuit·Proof Design

MAXIMUM RATINGS

=+ 25"C unless otherwise noted)

(TA

Rating

Symbol

Value

Unit

Power Supply Voltage

y+
Y-

+15
-15

Ydc
Ydc

Power Dissipation (Package Limitation)
Derate above 25° C

PD

625
5.0

mW
mW/'C

Operating Temperature Range

TA

o to +75

'c

MaXimum Ratings as defmed

In

-

C ERAMtC PACKAGE
CASE· 632

TO·116

MIL .S .19500. Appendix A •

CIRCUIT SCHEMATIC

INPUT LAG 1
10 11

OUTPUT LAG 1
12

EOUIVALENT CIRCUIT

14
INPUT
LAG 1

V+

1011 12
800
NON·INVERTING
INPUT 1 + 9
-8
INVERTING
INPUT 1
V- 7

15k

S.Bk

15k

S.8k

24k

OUTPUT 1
13

9
INPUT 1
8
V- 7

24k

OUTPUT 2
1

S
INPUT 2
5

INVERTING
INPUT 2 - S

800

4 3
INPUT LAG

INPUT
LAG2

2
OUTPUT LAG 2

See Packaging Information Section for outline dimensions.

7-1

MC1303L

(continued)

ELECTRICAL CHARACTERISTICS (Each Preamplifier) (V+

= +13 Vdc. V- = -13 Vdc.
T A = +25 0 C unless otherwise noted)

Characteristic Definitions (linear operations)

Lr=t>--F '.

Characteristic

Symbol

Min

Typ

Max

Unit

6,000

10,000

-

v!V

4.0

5.5

-

-

1.0

10

-

0.2

0.4

-

1.5

10

-

-

400

60

70

-

AVDL= RO.Ul

ein

-I-~

+

Open Loop Voltage Gain

AyOL

~

Output Voltage Swing
(R L = 10 kU)

;=t>----o
12~
I,
+

V
out

Input Bias Current

Ib

V(rms)

f1.A

~ = II + 12
2

12~
I,
+

~

Input Offset Current
(\0 = II - 12)

I.

Input Offset Voltage

V.

DC Power Dissipation
(Power Supply = ±13 V, Vout = 0)

Po

10

10

f1.A

mV

Vio

":"

+

Vout=O

~n~"ut'

f=t>---o

Channel Separation
(f = 10 kHz)

"u12

•
7-2

e
e

out 1
out 2

mW

dB

MC1303L

(continued)

TYPICAL PREAMPLIFIER APPLICATIONS
FIGURE 2 - BROADBAND AUDIO AMPLIFIER

FIGURE 1 - MAGNETIC PHONO PLAYBACK
PREAMPLIFIER/RIAA EQUALIZED

680pF

820 pF

INPUT ~-l~.....--{

'NPUT@--if;--,---z,
OUTPUT

OUTPUT

-+-__ v'

1-_ _

L--+-_v'

'1::..----+-_
v51k

v-

820k

6.8nF

'2 a

z

~

~

-

'::8

1--

a

0

N

I
if

Voltage Gain: 40 dB (l00)@1.0kHlreference
Output Voltage Swing: 5.0 V(rms)

"0



a

i

V'

14

V-

7

~t-

0
N

, --e

MC1303

r0

~



1

-20
30

50

lao

3ao

sao

151lF/3.0

III
1001)

f, FREQUENCY

3000500010,000

'---~

v

C" 1500 pF for 3 3/4 jols
C - 910 pF for 71/2 inls

20,000

(Hz)

-=

Voltage Gain: 35dB@1.0kHz
Output Voltage Swing: 5.0 V(rms}

7-3

I

I

MC1303L

(continued)

FIGURE 4 - POWER DISSIPATION versus
SUPPLY VOLTAGE

FIGURE 5 - OUTPUT LINEARITY

400

~ lOO

/

z

o

~
~

200

V

i5

'"~

o

c..

.E

g

/

o

/

o

~ 0.3

RL = 100 k ohm

i5
'-'

~ 0.2
~
«
:z:

/"

"

'"' 0.4
z
o

1
V+=±13V
Av = 100
1= 1.0 kHz

~

/

V

100

,

0.5

o

---

0.1

...J

;::o

I-

0' 0

4.0

8.0

1"

16

12

0

2.0

IV+I.IV-I. SUPPLY VOLTAGE (Vdc)

f-"

4.0

6.0

Vout• OUTPUT VOLTAGE (Vlrmsl)

--

FIGURE 6 - INFLUENCE OF OUTPUT LOADING
6.0

I

"" 5.0

E

?:
w
'"
~
~

THO =11.0%

",/

3.0

I-

:::>

~

.

....- ..,...,

4.0

2.0

o

",/

,} 1.0

./

/

./'

./

-

1.--'-

,,-

./

./

./

THD =0.1%
V+=±13V

./

AV=

../

/

/'

~L

100~*

1= 1.0 kHz
RF= 100kn
RS = 1.0 kn

V-

2.0

1.0

r----

"...-

5.0

-=

RS

20

10

-=

RF

50

100

RL. LOAD RESISTANCE (k ohms)

NOISE CHARACTERISTICS
FIGURE 7A - INFLUENCE OF SOURCE
RESISTANCE & BANDWIDTH
500

§
~

400

w

c5

~

RL

-=

;::'"

RS

-=

RF

300

~

AV=100~*
Low feo = 10 Hz I/"
high leo = 100 kH

:; 500
.5

~

w

'"~

-

z 200

f-

I-

~
1-

~ 100

o
100

200

i"""'"

500
1000
2000
RS. SOURCE RESISTANCE (OHMS)

RS

RF

/
./'

",."

~

~

~ 50

1.0 kHz

~
:::>
o

J:

o

lnHj
5000

-=

....

~ 100

10 kHz

--

~
-=

200

10 kHz

RL

o
>

,/

'"
i5

:::>

1000

I
V+=±13V

>

w

I-

FIGURE 7B -INFLUENCE OF VOLTAGE GAIN
& BANDWIDTH

./
20
10
10

10.000

./

V

/

1.0k~

~n..u
100 Hz
V+=±13V
RF
AV~RS

-

RS= 1.0 kn

low fco = 10 Hz
high leo = 100 kHz
20

50

100

200

AV. VOLTAGE GAIN (VN)

7-4

V

500

1000

\

MC1304P
MC1305P

_______
ST_E_R_E_O_D_E_M_O_D_U_L_A_T_O_R_.......I

FM MULTIPLEX
STEREO DEMODULATORS

MONOLITHIC FM MULTIPLEX
STEREO DEMODULATORS
. derive the left and right audio information from the detected
composite signal. The MC1304P eliminates the need for an external
stereo·channel separation control. The MC 1305P is similar to the
MC1304P but permits the use of an external stereo·channel separa·
tion control for maximum separation.
•

Operation Practicable Over Wide Power·Supply Range, 8·14 Vdc

•

Built·in Stereo-Indicator Lamp Driver

SILICON MONOLITHIC
INTEGRATED CIRCUITS

• Total Audio Muting Capability
• Automatic Switching - Stereo·Monaural
•

Monaural Squelch Capability

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating

Value

Power Supply Voltage (Pins
(Pin 7 is grounded)

1, 6, 9.*11,12)

Unit

+22

Vde

40
625

mAde

5.0
o to +75

mW/oC

Lamp Driver Current

Power Dissipation (Package Limitation)

PLASTIC PACKAGE
CASE 646
TO-116

mW

Plastic Package

Derate above T A = 2S o C
Operating Temperature Range (Ambient)
Storage Temperature Range
• Pin 8 for

-65 to +150

Me 1305P

CHANNEL SEPARATION versus FREQUENCY

0

0
z

~
~

w

-

/

V

0

........

0

0

--

r-

..........

f, 1.0 kHz

----. -.......

0

Input level-

200 mV(RMS) Composite
Signal, L= 1, R '" 0 or
R'I.L'O

0

Z
Z

'~"

CHANNEL SEPARATION versus COMPOSITE INPUT LEVEL

INPUT C' 5.0.F

c

S

°c
°c

0
0

0
50

100

200

500
1,000
FREQUENCY 1Hz)

2,000

5,000

10,000

See Packaging Information Section for outline dimensions.

7-5

10

100

150

200
250
300
350
400
COMPOSITE INPUT LEVEL (mVIRMSIl

450

500

MC1304P, MC1305P (continued)

ELECTRICAL CHARACTERISTICS (Vcc = 12 Vdc. T A

=

+25 0 C unless otherwise noted. Test made with 751's de·

emphasis network 13.9 kSl. O.02IJ.F) unl'Bss otherwise noted).
Min

Typ

Max

I "put Impedance
If = 20 Hz)

12

20

-

Stereo Channel Separation ISee Notes 1 and 2)
(f = 100 Hz)
II = 1.0 kHz)
11= 10kHz)

-

35
45
30

-

-

0.5

-

-

0.5

1.0

-

25
20

--

-

50

-

-

16
14

25

5.0
0.6
1.3

-

1.0
2.0

Charact.ristici

Unit

kO
dB

-

dB

Channel Balance
(Monaural Input = 200 mVIRMS)).
(Monoural. Left and Right Outputs)

Total Harmonic Distortion (See Notes 1 and 31
(Modulation frequency· 1.0 kHz)

%

Ultrasonic Frequency Rejection (See Note 4)

119kHz)
138 kHz)

dB

Inharent seA Rejection (without filter)

dB

@60 kHz. 67 kHz and 74 kHz
Lamp Indicator (RA = 1200)

mV(RMSI

Minimum 19 kHz Input Level for lamp on
Maximum 19 kHz Input Level for lamp off
Audio Muting
Mute on (Voltage rsquired at pin 5)
Mute off (Voltage required at pin 5)
Attentuation in Mute Mode (Note 5)

-

-

55

-

1.3

-

-

2.0
1.0

-

150
180

300
300

Vdc
Vdc
dB
Vdc

Stereo·Monaural Switching
Stereo (Voltage required at pin 4)
Monaural (Voltage required at pin 4)
Power Dissipation (Vee = 10 VI

mW

(Without lamp)
(With lamp)

Note 1 - Measurement made wIth 200 mV(RMSI Standard MultIplex ComposIte S'gnal and L = 1, R = 0 or R = 1, L = O. Standard MultIplex Composite signal is here defined as a signal containing left and/or right audio information with a 10% (19 kHzl pilot signal
in accordance with FCC regulations. ,Note 2 - Stereo channel separation is adjustable for the MC1305P with a resistor from pin 9 to ground.
Note 3 - Distonion specification also applies to Monaural Signal.
Note 4 - Referenced to 1.0 kHz output signal with Standard Multiplex Composite Input Signal.
Note 5 - This is referenced to 1.0 kHz output signal with either Standard Multiplex Composite Signal or Monaural I nput Signal.
Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

FIGURE 1 - DISTORTION COMPONENTS IN AUDIO SIGNAL
~1.6

4.0 ~

~
;::

g;

-

INPUT SIGNAL:
200 mVIRMSI STANOARO COMPOSITE SIGNAL

NOTE: BEAT FREQUENCY COMPONENTS IBFCI
RESULT FROM THE PRESENCE OF THE
19 kHz PILOT SIGNAL IN STEREO
BROADCASTS.

1.2

In
C

/

u

~ 0.8

~
~

THO. MONAURAL OR STEREO

./

V

I

o
100

200

300

400

1.0 k
FREQUENCY (Hzl

500

2.0k

FIGURE 2 - TOTAL HARMONIC DISTORTION
5

V

:Jfr
~

~

~

~

~

V

,..---1-"""

;;;

"

~ 15

V

r---

~
~

~

...g

10

t- ....... .....

t:-- ~MPO~

- ==--r--

LAMPOFF -

~

!E

~

~

~

10k

FIGURE 3 - MULTIPLEX SENSITIVITY

a::: 5.0

~

£

1.0 ~

o

5.0k

iS

20

I.l.~ kHz

0

4.0 k

3.0 k

2.0

-

-10.4

g
...

~

3.0 ~
BFC/

~

0

~

COMPOSITE INPUT LEVEL ImVIRMSIl

7-6

50
19 kHz GAIN

100
A~JUSTMENT.

r-- _ _

150
200
OHMS IPIN 1 TO 19 kHz FILTERI

250

MC1304P, MC1305P (continued)

FIGURE 4 - MC1304 CIRCUIT SCHEMATIC

:~:~~I~:
f--COMPOSITE
SIGNAL
INPUT

19kHz FILTER

,

1

38
lOr. kHz 13
TANK

19kHz

FILTER

I

1.0k

L(

v

.....
3

V

20k

~,~

ein

N

~

r---<

6.0k

B.Ok

5'(lk
S.Ok

(

~

14
DaUB LER
DECOU PliNG

500

2.0k

I

~
S.Ok

2.0k

'-....t

1.Ok

)--

~

'.Ok

(

500

4

6
LA MP

DRI VER

500

I.Ok

2.0k

5 AUDIO MUTE

·?lWi.:

l(~

~l"',

S.Ok

"

1.0k

V'

B.Ok

'j-

cc

~Wr>l

r-B.Ok

2.0k

1.0k

RIGHT CHANNEL
OUTPUT 9
V

V
r-

12

"'

~

S.Ok

LEFT CHANNEL
OUTPUT

11

1

GN

=

STEREO SWITCH

FIGURE 5 - MC1305 CIRCUIT SCHEMATIC

v
14
"'t---+----t---,Dc:D--------'

Volume
Control

3- +

O.002}.lf1.0 Megf1
Control

CIRCUIT SCHEMATIC
v,

Preamplifier

Power Amplifier

1.4k

Power Ampfifier
Output
3

SOD

1.6k

ONO
Preamplifier
Output

ONO

fDwerAmplifier
Input

See Packaging I nformation Section for outline dimensions.

7-9

I

MC1306P (continued)

MAXIMUM RATINGS (TA = +25 0C unless otherwise noted)
Symbol

Value

Power Supplv Voltage

Rating

V+

12

Vdc

Load Current

IL

400

mAde

Power Dissipation (Package Limitation)
TA = +250 C
Derate above T A =

+250

Po

C

625

mW

5.0

mW/oC

TA

o to +75

Tstg

-65 to +150

°c
°c

1/8JA

Operating Temperature Range

Storage Temperature Range

Unit

Maximum Ratings as defined in MI L-S-19500. Appendix A.

ELECTRICAL CHARACTERISTICS (V+ = 9.0 V, RL =8.00hms, f= 1.0 kHz, (using test circuit of Figure 3). TA =+250C
unless otherwise noted.)
Characteristic

Symbol

Open Loop Voltage Gain
Pre·amplifier R L = 1.0 k ohm

AVOL

Power·amplifier RL
(Po

TVp

Max

Unit

-

270

-

mVlrms)

V!V

= 16 ohms

Sensitivity

Min

-

360

S

-

3.0

= 500 mW)

Output Impedance (Power·amplifier)

Zo

-

Ohm

SIN

-

0.5

Signal to Noise Ratio
(Po = 150 mW, f = 300 Hz to 10 kHz)

55

-

dB

Total Harmonic Distortion
(Po = 250mW)

THO

-

0.5

-

%

Quiescent Output Voltage

Vo

-

v+12

-

Vdc

Output Power
(THO ,;;10%)

Po

-

mW

500

570

Current Drain (zero signal)

10

-

4.0

-

mA

Power Dissipation (zero signal)

Po

-

36

-

mW

FIGURE 3 - TEST CIRCUIT
1.0k

FIGURE 4 - ZERO SIGNAL BIAS CURRENT
10

V+

TA J25 0 C

----o
4.0

--

5.0

-

I--- ~

I---I---

6.0

7.0

I--'

8.0

9.0

10

V+. POWER SUPPLY VOLTAGE (Vdc)

7-10

11

12

MC1306P (continued)

TYPICAL CHARACTERISTICS

=9.0 V. f = 1.0 kHz. T A = +25 0 C unless otherwise noted)

(v+

FIGURE 5 - EFFICIENCY

FIGURE 6 - OUTPUT POWER

60

1.0

THOI= 1%
50

".

~
~

ffi

/

40

,.

f'

V ~

./

ffi

ipV

<3

~

30

20

V

10

3.0

4.0

RL -sn
THO = 10%

RL = s!o ohm,l

RL=sn
THO = 1%

s

RL = 16 n
THO=10%
I
RL =16 n
THO =1%

O. 6

~

I-

~ 0.4

V

............

o

/

/

~~

. / /": V

/

0.2

/

/ ..... r-.
/ I'-... V V
~ /' ~ lL'

L L

:::>

.E

r- Ii

I

/~ ~ V

:;;..-::

~

o

5.0

6.0

7.0

S.O

9.0

10

11

12

3.0

13

4.0

5.0

6.0

7.0

S.O

9.0

10

11

12

13

V+, POWER SUPPLY VOLTAGE IVdcl

V+, POWER SUPPLY VOLTAGE IVdcl

FIGURE 7 - TOTAL HARMONIC DISTORTION
4.0

\

~

Po=10~mW

\

z

0

;:: 3.2

RL = S.O Ohm,

1\

'"

0

~
C 2.4

\

<.>

CL=200~F

Z

0

:E

'":J::

'"

"" ""-

1.6

-'

'"

I0
I-

o·

f'.....

O.S

:J::

f-

t-- r-

I-

0.1

0.2

0.3

0.4

0.5

0.7

1.0

2.0

4.0

3.0

5.0

6.0

7.0 S.O 9.010

f. FREIlUENCY 1kHz)
FIGURE 8 - EFFECT OF BATTERY AGING
ON LOW·LEVEL DISTORTION

FIGURE 9 - DISTORTION

~ 4.0:===:====:===:===~rR-L-=-s-"'nlr__-_:
I~~~~~I~-_-=
i3
~

~

~
i§

/

/

I

Rl - 16 n

Simulated Battery

~

1.0

<.>

.!:
l!.=.

d

_V__

Cl - 30j"F

'"

~ 7.0

C 6.0

~

V

I-

If-lkHZI

~

i!:

~ 9.0
z
!: S.O

Cl=50~F Jo =loml' 3.01--+---+--\---;1'-+---+---' _

2.01--+---b,tL--I--7'1- Cl =50 ~F _r-~-~':""..J
./
RL =s
+s...:!J.'it___
Cl =300~F - yr"
Cl
./V
~ RL: 16h

:E

10

I

~

'" 4.0

J:

:J::

-=1

:=

~ 3.0

I I I

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1

2.0

Ii

ci

~ 1.0

o

OL-_~_~_~_~_~_~~_~_~

9.0

V+=9.0V
RL = S.O Ohm,

5.0

~

1.0

0.01

v+,SUPPLY VOLTAGE IVdcl

0.02

0.03

0.05

0.1

0.2

Po, POWER OUTPUT IWAITSI

7-11

0.3

0.5

1.0

•

MC1306P (continued)

FIGURE 10 - TYPICAL CIRCUIT CONNECTION

R,n

Rp/2

C2

I

Cp

1

Rl

,,

:
Cf=r
:
:
Cl

Rs

,

".",: ~]

RI

:

~

Preamplifier

Jrlput

3.~ 311~H
MC1306

:

1O:;R5
:
: O.05I'F=rC6

O.hF:*:C5

!

-;:-"

:

l

-f::

DESIGN CONSIDERATIONS
The MC1306P provides the designer with a means to control
preamplifier gain, power amplifier gain, input impedance, and
frequency response. The following relationships will serve as guides.

1. Gain
The Preamplifier Stage Voltaga Gain is:

Rf
AVA""R;
and is limited only by the open-loop gain (270 V/V). For good
preamplifier dc stability Rf should be no larger than 1.().megohm.
The Power Amplifier Voltage Gain is controlled in a similar
manner where:

10 k

AVB

""""R;

The 10-k ohm feedback resistor is provided in the integrated
circuit.
Recommended values of Rp range from 500-ohms to 3.3-k
ohms. The low end is limited primarily by low-level distortion and
the upper end is limited due to the voltage drive capabilities of the
pre-amplifier. (A resistor can be added in the dc feedback loop,
from pin 6 to ground, to increase this drive); The Overall Voltage
Gain, then, is:

2. Input Impedance
The Preamplifier Input I mpedance is:

and the Power Amplifier Input Impedance is:

3. Frequency Response
The low frequency response is controlled by the cumulative
effect of the series coupling capacitors Cl, C2, and C3. Highfrequency response can be determined by the feedback capacitor,
ct, and the -3.0 dB point occurs when
XCf = Rf
Additional high frequency roll-off and noise reduction can be
achieved by placing a capacitor from the center point of Rp to
ground as shown in Figure 10.
Capacitor C4 and the RC network shown in dotted lines may
be needed to prevent high frequency parasitic oscillations. The R F
choke, shown in series with the output, and capacitor C6 are used
to prevent the high-frequency components in a large-signal clipped
audio output waveform from radiating into the RF or IF sections
of a radio (Figure 10).
4. Battery Operation
The increase of battery resistance with age has two undesirable
effects on circuit performance. One effect is the increasing of
amplifier distortion at low signal levels. This is readily corrected by
increasing the size of the filter capacitor placed across the battery
(as shown in Figure 8; a 30().I'F filter capacitor gives distortions
at low-tonal levels that are comparable to the "stiff" supply). The
second effect of supply impedance is a lowering of power output
capability for steady signals. This condition is not correctable, but
is of questionable importance for music and voice signals.
5. Application Examples: (1) The audio section of the AM-FM
radio (Figure 1) is adjusted for a preamplifier gain of 100 with an
input impedance of 10-k ohms. The power amplifier gain is set at
10, which gives an overall voltage gain of 1000. The bandwidth
has been set at 1 ()'kHz. (2) The phono amplifier (Figure 2) is designed for a preamplifier gain of unity and a power amplifier gain
of 10. The input impedance is 1.().megohm. An adjustable treble
control is provided within the feedback loop,

7-12

MC1306P (continued)

TYPICAL PRINTED CIRCUIT BOARD LAYOUT

LOCATION OF COMPONENTS
C2

C3

Rl

R2

R3

C5

See Figure 3 for schematic diagram.

PARTS LIST
Component

Value

Cl
C2
C3
C4
C5
Rl
R2
R3
R4
MC1306
PC Board

200llF
O.lIlF
0.051lF
1.01lF
47 pF
lohm
1 k ohm
4.7 k ohms
270 k ohms

-

7-13

I

~____________S_T_E_R_EO__D_E_M_O_D_U_L_A_T_O_R__~

MC1307

FM MULTIPLEX
STEREO DEMODULATOR

MONOLITHIC FM MULTIPLEX
STEREO DEMODULATOR

SILICON MONOLITHIC
INTEGRATED CIRCUIT

· .. designed to derive the left and right channel audio information
from the detected composite signal.
•

Capable of Operation Over a Wide Power Supply Range 8.0 - 14 Vdc

•

Built·in Stereo·lndicator Lamp Driver

W
~

(top view)

PSUFFIX
PLASTIC PACKAGE
CASE 605

TO·116

PQSUFFIX

PLASTIC PACKAGE

CASE 647

FIGURE 1 - TYPICAL CIRCUIT CONFIGURATION

L1, L2:

=55.
~3~ ;~~~~I~uAL.

MILLER NO.1 361
OR EaUIV.
L3: 420 TURNS NO .38 AWG.
TAP AT 42 TU RNS.
au = 55,8.0 mH
NOMINAL. MI LLER
NO. 1362 OR EaUlv.

.F

I

f

19 kHz

Lin

V+

0.0022.F
II

"

O.01 • F

-

RA"

;:p; 0.02.F

3.9 k

38 kHz

;:r:- 0.02.F

3.9 k

I

L3

9

1

13

10

3

11

LEFT CHA NNEL
OUTPUT

12

RIGHT CH ANNEL
OUTPUT

MC1307

\

@

6

2

14

+12

STEREO INDICATOR LAMP
I(max) < 40 rnA

7

(Svlvania 12ESB or equiv.)

;;" 0.05.F

L2

H

TYPICAL DC VOLTAGES

I
I
I

Pin Numbers

v+ = 8.5 Vdc
v+ = 12Vdc

f

19 kHz

I
I
I

1
8.5
12

,--->-O.OI.F
·4.7 k

;::

"SEE FIGURE 3

2.0.F

(All measured using a VTVM with respect to Pin 7 (lamp on), RA = 180 ohms, see Figure 3)

I
I
I

2
2.7
2.9

I
I
I

3
3.6
3.9

I 4 I 5 I
I - J - I
I - I - I

6
0.8
0.9

See Packaging Information Section for outline dimensions.

7-14

I
j

I

7
0
0

I

8

I

L- I
I - I

9
8.5
12

I
I
I

10
4.4
4.7

I
I
I

11
6.2
9.7

I
I
I

12
6.2
9.7

I
I
I

13
4.4
4.7

I
I
I

14
1.5
1.7

I
I
I

MC1307 (continued)

FIGURE 2 - CIRCUIT SCHEMATIC

9

1.3 k

J
"

20 k

~¥>
l

V

I'"

"

5k

3
~

5k

~

6k

5k

V

'"

,r

t.....

'--------<

V

'" o-----Y"

"

,
~

1

~
V

U

6k

RIGHT CHANNEL
OUTPUT
12

LEFT CHANNEL
OUTPUT
11

38 kHz
LOW
13

1k

"

U

COMP OSITE
SIGN AL
INPU T

lst
2nd
19 kHz 19 kHz
FILTER FILTER
2
1

38 kHz
HIGH
10

V'

6k

1k

"

1k

1k

1k

~

330

"

~,

NO

7

LAM

~~

1-

( 14

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted)
Rating

Power Supplv Voltage (Pins 1, 6,
9,11,12)
(Pin 7 is grounded)
Lamp Driver Current

Power Dissipation (Package
Limitation)
Derate above T A = +2SoC
Operating Temperature Range (Ambient)

Value

Unit

+22

Vdc

40

mAde

625

mW

5.0

mWtOC

o to +75

°c
°c

-65 to +150

Storage Temperature Range
Maximum Ratings as defined In MI L-S-19500, Appendix A.

7-15

6

I

I

MC1307 (continued)

ELECTRICAL CHARACTERISTICS (v+ = 12 Vdc, TA =+25 0 C, tests made with a 75 J.ls de-emphasis network
(3.9 kn, 0.02 J.lF) unless otherwise noted)
Characteristic
I "put Impedance
(f = 1.0 kHz)
Stereo Channel Separation (See Note 1)
If = 100 Hz)
If = 1.0 kHz,
If = 10 kHz)

Min

Typ

Max

Unit

12

20

-

kn

-

35
40
30

-

0.5

1.0

%

-

0.5

-

dB

-

25
20

-

50

-

25

5.0

16
14

-

140
170

300
300

dB

20

Total Harmonic Distortion (See Notes 1 and 2)
(Modulation Frequency = 1.0 kHz)
Channel Balance
(Monaural Input = 200 mV [rmsl)
(Monaural, Left and Right Outputs)
Ultrasonic Frequency Rejection (See Note 3)
(19 kHz)
(38 kHz)

dB

Inherent SCA Rejection (without filter)
(f = 60 kHz, 67 kHz and 74 kHz) (See Note 3)
lamp Indicator (RA = 180 n)
(Minimum 19 kHz input level for lamp "on")
(Maximum 19 kHz input level for lamp "off")
Power Dissipation (V+
(Without lamp)
(With lamp)

Note 1 -

dB
mV(rms)

-

-

= 12 V)

mW

=

Measurement made with 200 mV(rms} Standard Multiplex Composite Signal where L ;; 1, R 0 or R :::: 1, L = O.
Standard Multiplex Composite Signal is here defined as a signal containing left and/or right audio information with a 10%

(19 kHz) pilot signal in accordance with FCC regulations.
Note 2 -

Distortion specification also applies to Monaural Signal.

Note 3 -

Referenced to 1.0 kHz output signal with Standard Multiplex Composite I "put Signal.

FIGURE 3 - DISTORTION COMPONENTS IN AUDIO SIGNAL

1.6

~
z

o
~ 1.2
o

INPU~ SIGNALI:
-

I

I

I

I

I

CO~PONENTS

NOTE: BEA+ FREQUENCY
IBFC)
RESULT FROM THE PRESENCE OF THE
19 kHz PILOT SIGNAL IN STEREO
BROADCASTS.

200 mV Irm,) STANDARO COMPOSITE SIGNAL

In
i5

~

z

THO. MONAURAL OR STEREO

~
~ 0.4

~

....
~

0
100

~

200

300

400

500

1.0 k
FREQUENCY 1Hz)

7-16

2.0 k

V

3.0 k

........

~
z
3.0 ~
~

"8

2.0~

L

"

4.0 k

4.0 ~

BFC/

L

0.8

o

o
,..

1

5.0 k

iii
=>

o

1.0~

o

10 k

~

MC1307 (continued)

FIGURE 4 - TOTAL HARMONIC DISTORTION

FIGURE 5 - MULTIPLEX SENSITIVITY

4. 0

100

~
z

0

~
t;;

01 \

o \

3. 0

0

\

0

Q
'-'

Z

2. 0

0

V+ = 12 Vdc

~

'"'";;1.

I-

1. 0

V

STE~ V

o

I-

/'

/"

~
V+= 12 Vdc

or-

f..-0
200

300

\

0

J'....

0

400
500
600
700
800
COMPOSITE INPUT LEVEL ImVlrm'l1

900

LAMP "OFf"

II

0
100

1000

150
200
RA, 19 kHz GAIN AOJUSTMENT IOHMSI

FIGURE 6 - CHANNEL SEPARATION

z
o

~

~

-'
w

'-'

0

0
0
0

t-

-l-

V

0

0
w

COMPOSITE INPUT = 300 mVrm,

Z
Z

~

250

FIGURE 7 - CHANNEL SEPARATION

0

;

LAMP "ON"

tl nlll
1

20

10
0.1

d

II II

Z
Z

II II
0.5

1.0
fREQUENCY IkHzl

O~

I--"""

~ 4

I I I I

FREQUENCY = 1.0 kHz
V+ = 12 Vdc

30

5.0

10

200

7-17

300

400

500
600
700
800
COMPOSITE INPUT ImVlrm'l1

900

1000

•

,-------",I

MC1310P ~_________S_T_E_R_E_O__D_EM__O_D_U_L_A_T_O_R____~

FM STEREO DEMODULATOR
· .. a monolithic device designed for use in solid·state stereo receivers.
•

Requires no Inductors

•

Low External Part Count

•

Only Oscillator Frequency Adjustment Necessary

FM STEREO
DEMODULATOR

•

Integral Stereo/Monaural Switch 75 mA Lamp Driving Capability

•

Wide Dynamic Range: 560 mV(RMS) maximum Composite
I nput Signal

•

Wide Supply Range: 8-16 Vdc

•

Excellent Channel Separation Maintained Over Entire Audio
Frequency Range

•

Low Distortion: Typically 0.3% THO at 560 mV (RMS)
Composite I nput Signal

•

Excellent SCA Rejection

MAXIMUM RATINGS ITA

MONOLITHIC SILICON
INTEGRATED CIRCUIT

= +250 C unless otherwise noted)

Rating

Unit

Value

Power Supply Voltage

16

Volts

Lamp Current
(nominal rating, 12 V lamp)

75

mA

Power Dissipation
(Package limitation)
Derate above T A = +25 0 C

625

mW

5.0

mW/oC

-40 to +85

°c
°c

Operating Temperature Range (Ambient)

-65 to +150

Storage Temperature Range

PLASTIC PACKAGE
CASE 646
TO·116

FIGURE 1 - TYPICAL APPLICATION
R4
19 kHz
OUTPUT
PIN FUNCTIONS
Pin 8 '" Switch Filter

Pin I =VCC

Pin 2:: Input

Pin 9 '" Switch Filter

Pin 3 = Amplifier Output
Pin 4 = left Channel Output
Pin 5 = Right Channel Output
Pin 6 = lamp Indicator

Pin
Pin
Pin
Pin

Pin 7 = Ground

Pin 14= Oscillator RC Network

C3 = O.OZ ~F
C4=0.Z5~F
C5 = 0.05 ~F

Cs = 0.5 ~F
C7 = 470 pF

14

10 = 19 kHz Output
11 = Modulator Input
12 = Loop Filter
13:: Loop Filter

PARTS LIST
CI=Z.O~F
Cz = O.OZ~F

C6

C8=0.ZS~F

RI = 3.9 kn

RZ = 3.9 kn
R3=1.0kn
R4 = IS kn
RS =·5.0 kn

13

C5
1Z

MC1310

CI

INPUT"'f!+t::I==~_J

VCC __----~----------~-4_+_+~~~
LEFT
CHANNEL OUTPUT

See Packaging Information Section for outline dimensions.

7-18

RIGHT
CHANNEL OUTPUT

MC1310P (continued)

ELECTRICAL CHARACTERISTICS Unless otherwise noted; VCC' = +12 Vdc. TA = +250 C. 560 mV(RMS) (2.B Vp-p)
standard multiplex composite signal with Lor R channel only modulated at 1.0 kHz and with 100 mV(RMS) (10% pilot levell.
using circuit of Figure 1.

Min

Max

Unit

-

V p .p

2.B

-

-

V p•p

Input Impedance

-

50

kll

Stereo Channel Separation (50 Hz - 15 kHz)

30

40

-

Audio Output Voltage (desired channel)

-

4B5

-

mV(RMS)

-

1.5

dB

0.3

-

34.4
45

-

BO

-

12

16

20

mV(RMS)

-

6.0
±3.0

-

dB

B.O

-

16

Vdc

-

13

-

mAdc

Characteristic
Maximum Standard Composite Input Signal (0.5% THO)

2.B

Maximum Monaural Input Signal (1.0% THO)

Monaural Channel Balance (pilot tone "off")
Total Harmonic Distortion
Ultrasonic Frequency Rejection

19 kHz
38 kHz

Inherent SC A Rejection
(f = 67 kHz; 9.0 kHz beat note measured

Typ

dB

%

dB
dB

with 1.0 kHz modulation "off")
Stereo Switch Level

(19 kHz input level for lamp "on")
Hysteresis
Capture Range (permissible tuning error of internal oscillator.
reference circuit values of Figure 1)

Operating Supply Voltage (loads reduced to 2.7 kll for B.O·volt
operation)
Current Drain (lamp "off")

%

·Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

FIGURE 2 - SYSTEM BLOCK DIAGRAM

INPUT

•
38 kHz

OUTPUTS

7-19

MC1310P (continued)

CIRCUIT OPERATION
ated 38·kHz signal is fed to the stereo decoder via an internal
stereo switch. The stereo switch closes when a sufficiently large
19-kHz pilot tone is received. The pilot tone level is detected and
the switch operated by the stereo switch section of the circuit in
the following manner:

Figure 2, on the previous page, shows the system block diagram.
The upper line, comprising the 38-kHz regeneration loop operates

as follows: the internal oscillator running at 76-kHz and feeding
through two divider stages returns a 19·kHz signal to the input
modulator. There the returned signal is multiplied with the in·
coming signal so that when a 19-kHz pilot tone is received a de
component is produced. The de component is extracted by the Jow

The 19-kHz signal returned to the 38-kHz regeneration loop

modulator is in quadrature with the 19-kHz pilot tone when the
loop is locked. With a third divider state appropriately connected,
a 19·kHz signal in phase with the pilot tone is generated. This is

pass filter and used to control the frequency of the internal oscillator

which consequently becomes phase-locked to the pilot tone. With
theoscillator phase·locked to the pilot the 3S-kHz output from the

multiplied with the incoming signal in the stereo switch modulator

first divider is in the correct phase for decoding a stereo signal. The
decoder is essentially another modulator in which the incoming

yielding a de component proportional to the pilot tone amplitude.
This component after filtering is applied to the trigger circuit
which activates both the stereo switch and an indicator lamp.

signal is multiplied by the regenerated 38-kHz signal. The regener·

APPLICATIONS INFORMATION
(Component numbers refer to Figure 1)
External Component Functions and Values

Cl

Input coupling capacitor; 2.0 IJF is recommended but a lower value is permissible if
reduced separation at low frequencies is acceptable.

Oscillator timing network, recommended values:

C7 = 470 pF
1%
R4= 16kn
1%
Preset
R5= 5 kn
These values give ±3% typical capture range.

Loads and de-emphasis capacitors, maximum
permissible load resistors are related to mini-

mum supply voltage as follows:
Min Supply
8.0 10 12 Volts
Max Load
2.7 4.3 6.2 Kilohms
(± 10% Tolerance)

Capture range may be increased by reducing

C7 and increasing R4, R5 proportionally but
at the cost of increased beat-note distortion

Filter capacitor for stereo switch level detec-

tor; time constant is C4 x 53 kilohms ±30%,

Stereo Lamp

maximum dc voltage appearing across C4 is

circuit includes surge limiting which restricts

0.25 V (pin S positive) at 100 mV(RMS) pilot
level. The signal voltage across C4 is negligible.
Internal coupling capacitor to modulators; 0.05
IlF is recommended. This gives 1.750 phase
lead at 19 kHz.

19 kHz·Output

cold·lamp current to approximately 250 rnA.
A buffered output providing a 3.0 VPK posi·
tive-going square wave at 19 kHz is available

at pin 10. A frequency counter may be can·
nected to this point to measure the oscillator
free-running frequency for alignment ..

Phase-lock loop filter components; the following network is recommended:

R3

(due to oscillator·phase jitter) at high·signal
levels.
Nominal rating up to 75 mA at 12 V; the

Cs

"~~"
0.25 ¢'
When less performance is required a simpler

network consisting of R3 = 100 ohms and C6
= 0.25 IlF may be used (omit CS).

7-20

MC1310P (continued)

APPLICATIONS INFORMATION (oontinued)
External MonaurallSterao Switching
The circuit can be maintained in monaural mode by connecting

phase lead can be obtained if required by reducing CS. which
couples into a S.D-kilohm load.
The circuit is so designed that phase lag may be generated by adding
a capacitor from pin 3 to ground. The source resistance at this
point is SOO ohms. A capacitance of 820 pF compensates the
S.So phase lead: increase above this value causes the regenerated
sub·carrier to lag the original.
Note that these phase shifts occur within the phase·lock loop and
affect only the regenerated 38-kHz sub·carrier: the circuit causes

pin 8 negative or pin 9 positive by 0.3 V. Pin 8 may be grounded
directly if desired. The dc impedance at pins 8 and 9 is 28 kilohms
±30%. Note that the. voltage across C4 increases to 2.2 V with
pin 9 positive when pin 8 is grounded.
Oscillator Killing
In AM·FM receivers it may be desirable to kill the 76-kHz internal
oscillator during AM reception to prevent interference. This may

be accomplished by either grounding pin 14 or by connecting it to

no significant phase or amplitude variation in the actual stereo

the positive line via a current limiting resistor (3.3 kilohms is recom-

mended).

signal prior to decoding.

Phase Compensation

Voltage Control Oscillator Compensation

Phase-shifts in the circuit cause the regenerated 38·kHz sub-carrier
to lead the original 38 kHz by approximately 20. The coupling
capacitor CSgenerates an additional lead of 3.So (for Cs = O.OS IlF)
giving a total lead of S.So.
It may be desirable that the regenerated 38 kHz lead or lag the

Figure 3 illustrates uncompensated Oscillator Drift versus temperature. The reoommended TC of the R4. RS. C7 combination
is -200 ppm. This will hold the oscillator drift to approximately
±-O.S% over a temperature range of -30 to +8So C. Acceptable

original to compensate for receiver IF characteristics.

performance is obtained with up to 2.5% oscillator detuning, which

with the oompensation given above. allows ±2% for aging of the
timing components.

Further

FIGURE 3
19.4 0

0

"'t'--..

.......

r-.....

0

18.60
-55

"~
...............

-35

-15

+5.0

+25

+45

TEMPERATURE lOCI

7-21

r-....

r-...
+65

+85

+105

~

*_D_E_C_O_D_E_R~I

____________________
SQ
__

MCI312P
MCI313P

MONOLITHIC CBS SQ* DECODER

FOUR-CHANNEL
SQ* DECODER

a matrix system designed to decode an SQ' encoded program
into four separate channels. These devices conform to specifications
for decoding quadraphonic records produced by the largest record
companies in the world.
•
•

MONOLITHIC SILICON
INTEGRATED CIRCUIT

Both Home Entertainment (MC1312) and Automotive (MC1313)
Versions Available
High Input Impedance
MC1312P - 3.0 Megohms typ, MC1313P -1.8 Megohmstyp

•

Low Harmonic Distortion
MC1312P - 0.1% typ, MC1313P - 0.25% typ

•

High Signal Handling Capability
MC1312P - 2.0 V(RMS) min, MC1313P - 0.8 V(RMS) min

•

MC1313 Provides Excellent Performance at VCC=+B.OVdc

FIGURE 1 - TYPICAL APPLICATION CIRCUIT
0.22/1F

t

0.039/1F

This component is sold without patent in-

3.6 k

deminity and any infringement resulting from

use or resale thereof shall be the sale responsibility of purchaser and shall not be the responsi-

bility of manufacturer ordistributor even though
such use is in accordance with manufacturer's
recommendations.

0.039/1F

~

3.6 k

MC1312P
MC1313P

r::::::::]
14

L-----~t-eLTINPUT
O.OS/I F

',",--,

-

PLASTIC PACKAGE
CASE 646

TO·116

0.039/1F

~

3.6 k

0.0068/1F

Circuit diagrams utilizing Motorola products are
included as a means of illustrating typical semiconductor appl ications; consequently. complete
information sufficient for construction purposes
is not necessarily given. The information has been
carefully checked and is believed to believed to
be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of
the semiconductor devices described any license
un-der the patent rights of Motorola" I nco or others.

Note: For optimum performance .±5% to lerance components Bre recommended with
the exception of the input capacitors.

OEFINITIONS
LT - Left total
LF' "" Left front
RF' "" Right front

RT "" Right total
LB' :::: Left back
RS' = Right back

*Trademark of Columbia Broadcasting Systems, Inc.
See Packaging Information Section for outline dimensions.

7-22

MC1312P, MC1313P (continued)

MAXIMUM RATINGS

IT A = +250 C unless otherwise noted)

Rating

Value

Unit

25

Vde

Power Supply Voltage

Power Dissipation (Package Limitation)

625
5.0

Derate above T A = +25 0 C

Operating Temperature Range

a

MC1312P
MC1313P

Storage Temperature 9ange

E LECTR ICA L CHARACTERISTICS

rnW
rnWfoC

to +75
-40 to +85

°c

-65 to +150

°c

IVCC for MC1312P = +20 Vde, Vin = 0.5 VI RMS), for MC1313P VCC ~ +12 Vde, Vin
VIRMS), TA = +25 0 C unless otherwise noted.) ISee Figure 3.)

Characteristic

= 0.2

Min

Typ

Max

Unit

Supply Current Drain

MC1312P
MC1313P

11
6.5

16
9.0

21
12.5

rnA

I nput Impedance

MC1312P
MC1313P

1.8
1.0

3.0
1.8

-

Ml!

-

5.0

-

kl!

-1.0

+1.0

dB

Output Impedance

Voltage Gaon LF /L Tor R F fRT

-1.0

a
a

+1.0

dB

Relative Voltage Gain LB'/LF', RB'/LF', LB'fRF', RB'/RF'

-2.0

-3.0

-4.0

dB

MC1312P
MC1313P

2.0
0.8

-

-

VIRMSI

MC1312P
MC1313P

-

0.1
0.25

-

-

80
74

-

Channel Balance

ILF/RF)

LF' measurements made with LT input, RF' measurements made with
RT input.
Maximum Input Voltage for l%THD at Output

RT or LT

Total Harmonic Distortion
RT or LT

Signal to Noise Ratio (Short-Circuit Input Vo- 0.5 VIRMS) MC1312P
with Output Noise Referenced to Output Vo = 0.2 VIRMS) MC1313P
VOltage, VOIIBW = 20 Hz to 20 kHz)

%

dB

Symbols conform to JEDEC Englneermg Bulletin No.1 when applicable.

TYPICAL CHARACTERISTICS

•

FIGURE 3 - TEST CIRCUIT
FIGURE 2 - CURRENT DRAIN

Vee

28

1.0J.LF

24

~

20

~

co

V""
l - I---

~ 12

"'~

-

MCI3~

z 16

B.o

........

f.--'"

....--

~

...-

I-

MCI313P
LT

4.0

INPUT

L-___._JI,NI,.....-1E-

o
6.0

80

10

12

14
16
18
20
SUPPL Y VOLTAGE IVdcl

22

24

26

LB'

OUTPUT
• Rl

LS

51
used for input impedance measurement.

S 1 is normally closed.

7-23

MC1312P, MC1313P(continued)

APPLICATIONS INFORMATION
FIGURE 4 - DECODING PROCESS DIAGRAM

--1

1/,1 _0°

0.707 RS

I
I

-0,707

--1

'" _90 0

-{

'" _90 0

LB' = LB

./

L

I

+ jO.707 LF -0.707 RF
0.707

0.707 LF

.f,\

RS' = RS

+ 0.707 LF -;0.707 RF

RS

+0.707
0.707 RF

Y _0°

I

I

LT

=

LF + 0.707 RS - j 0.707 La

RT

-=

RF -0.707 LS + j 0.707 RS

0.707 LS

LT and RT are composite signals from SO erocaded rec6"rds or SO broadcast.

It is generally desirable to enhance center-front to center-back
separation. This is accomplished by connecting a resistor between
pms 2 and 11 tfront outputs) and 3 resistor between pins 3 and
14 (back outputs). For a 10% front channel blending t and a 40%
back channel blendingt, 47 kilohms between pins 2 and 11 and
7.5 kilohms between pins 3 and 14 is required.

The decoding process is shown schematically in Figure 4. The

MC1312P/MC1313P circuits that perform this function consists of
two preampl ifiers which are fed with left total, LT. and right total,

RT, signals. The preampl ifiers each feed two all-pass* networks
that are used to generate two LT signals in quadrature and two
RT signals in quadrature. The four signals are matrixed to yield
left·front, left-back, right-front, and right-back signals (LF', LB',

RF', RB')·

tRF" = 0.9 RF' + 0.1 LF'

The all-pass networks are of the Wein bridge form with the
resistive arms realized in the integrated circuit and the RC arms
formed by external components. The values shown in Figure 1
are for a 10o. Hz to 10-kHz bandwidth and a phase ripple of ±8.5°
on a 90 0 phase difference.

LF" = 0.9 LF' + 0.1 RF'
RS" ~ 0.6 RS' + 0.4 LB'
LB" = 0.6 Ls' + 0.4 RS'

·An all-pass network produces phase shift without amplitude variations.

7-24

"'\

DUAL CHROMA DEMODULATOR

"-----------'

MC1326

DUAL DOUBLY BALANCED
CHROMA DEMODULATOR

DUAL DOUBLY BALANCED CHROMA
DEMODULATOR WITH R G B MATRIX
AND CHROMA DRIVER STAGES

WITH

R G B OUTPUT MATRIX

· .. a monolithic device designed for use in solid-state color tele-

MONOLITHIC SILICON
INTEGRATED CIRCUIT

vision receivers.
•

Luminance I nput Provided

•

Good Chroma Sensitivity. - 0.3 Vp-p Input for 5 Vp·p Output

•

Low Differential Output DC Offset Voltage - 0.6 V max

•

DC Temperature Stability - 3 mV/oC typ

•

Negligible Change in Output Voltage Swing with Varying
3.58 MHz Reference Input Signal

•

High Ripple Rejection Achieved with MOS Filter Capacitors

•

High Blue Output Voltage Swing - 10 Vp·p typ

•

Blanking Input Provided
PSUFFIX
PLASTIC PACKAGE
CASE 605
TQ-116

MAXIMUM RATINGS (T A = +2S o C unless otherwise noted)
Rating

Value

Unit

Power Supply Voltage

30

Vdc

Chroma Signal I nput Voltage

5.0

Vpk

Reference Signal Input Voltage

5.0

Vpk

Minimum Load Resistance

3.0

kohms

Luminance I nput Voltage

12

Vp-p

Blanking Input Voltage

7.0

Vp-p

625
5.0

mW
mW/oC

0'0 +75

°c
°c

Power Dissipation (Package Limitation)

Plastic Packages
Derate above T A

=+25 0 C

Operating Temperature Range (Ambient)

Storage Temperature Range

-65'0 +150

PO SUFFIX
PLASTIC PACKAGE
CASE 647

Maximum Ratings as defined in MI L-5-19500, Appendix A.

I

FIGURE 1 - MC1326 TYPICAL APPLICATION

I <~~In

0

0

BLANKING
INPUT

+2S0Vdc

-t24Vdc

1.DpF

MPS Ul0
OR EQUIV

~

IDk

IDk

10.

250",H

GREEN
REO

3.58 MHz

3.3k

Uk

3.3k

REFERENCE
SIGNAL INPUT
lVp·p

GaO

Atypicalapplicationisgivtnabovelllindicate
tharequlrementsandoutputfunctionsofthil
chroma demodulator.

See Packaging Information Section for outline dimensions.

7-25

330

..0

330

..0

330

L---~I----+-----"+20V

I

MC1326 (continued)

ELECTRICAL CHARACTERISTICS (v+ ~ 24 Vdc, R L ~ 3.3 k ohms, T A ~ +25 0 C unless otherwise noted)

I

I

Characteristic

Pin No.

I

Min

I

Typ

I

Max

Unit

Vdc

STATIC CHARACTERISTICS
Quiescent Output Voltage
See Figure 2

1,2,4

Quiescent Input Current from Supply (Figure 2)
(RL=oo)
(R L = 3.3 k ohms)

13

14.4

16

-

-

mA
16.5

6.0
19

Reference Input DC Voltage (Figure 2)

5,12,13

-

6.2

Chroma Reference Input DC Voltage (Figure 2)

8,9,10

3.4

-

Vdc

Differential Output Voltage
(Reference Input Voltage = 1.0 Vp·p)
See Note 1 and Figure 3

1,2,4

-

0.3

0.6

Vdc

Output Voltage Temperature Coefficient
(Reference I nput Voltage = 1.0 VP'p, +250 to +65 0 C)
See Note 1 and Figure 3

1,2,4

-

3.0

-

mV/oC

25.5
Vdc

DYNAMIC CHARACTERISTICS (V+ - 24 Vdc , R'L -- 33 k oh m,
s Reference Input Voltage - 10 Vp-p TA- +25 0 C unless otherwise noted)
Blue Output Voltage Swing
See Note 2 and Figure 4

4

8.0

10

-

Vp·p

Chroma I nput Voltage (B Output = 5.0 Vp·p)

8

-

0.3

0.7

Vp·p

3

100

-

-

k.l1

-

0.95
0.5

-

-

1.1
75

-

See Note 3 and Figure 4
Luminance Input Resistance

Luminance Gain From Pin 3 to Outputs
(@dc)
(@5.0MHz)

-

1,2,4

Blanking '"nput Resistance

k.l1

6

1.0 Vdc
OVdc
Detected Output Voltage (Adiust B Output to
5.0 Vp·p, Luminance Voltage = 23 V)
See Note 4
G Output
R Output

4
1
2

Relative Output Phase (B Output = 5.0 Vp·p,
Luminance Voltage = 23 V)
B to R Output
B to G Output
4.0 Vp.p

Vp·p
0.75
3.5

1.0
3.B

1.25
4.2

Degrees
4,2
4,1

101
24B

106
256

111
264

1,2,4

-

250

500

mVp·p

B·Y Phase Shift (B·Y Reference Input to B·Y Output)

4,13

-

Degrees

1,2,4

-

3

Residual Carrier and Harmonics Output Voltage (with
Input Signal Voltage, normal Reference Signal
Voltage and B Output = 5.0 Vp·p)

0.7

1.5

Vp·p

Reference I nput Resistance (Chroma Input = 0)

12,13

-

2.0

-

k.l1

Reference I nput Capacitance (Chroma Input = 0)

12,13

-

6.0

-

pF

Chroma Input Resistance

B,9,10

2.0

8,9,10

-

k.l1

Chroma I nput Capacitance

-

256 0
1060

I

5.0Vp.p

1.0Vp.p

I

Demodulator Unbalance Voltage (no Chroma Input
Voltage and normal Reference Signal I nput Voltage)

2.0

pF

NOTES:
1. With Chroma Input Signal Voltage = 0 and normal Reference Input Signal Voltage = 1.0 Vp-p, all output voltages will be within specified
limits and will not differ from each other by greater than 0.6 Vdc.
2. With normal Reference I nput Signal Voltage, adjust Chroma Input Signal Voltage to 0.6 Vp·p.
3. With normal Reference Input Signal Voltage, adjust Chroma Input Signal Voltage until the Blue Output Voltage = 5 Vp·p. The Chroma
Input Voltage at this point should be equal to or less than 0.7 Vp·p.
4. With normal Reference Input Signal Voltage, adjust the Chroma Input Signal until the Blue Output Voltage = 5 Vp·p. At this point, the
Red and Green voltages will fall within the specified limits.

7-26

MC1326 (continued)

(V+

= 24 Vdc,

TEST CIRCUITS

RL

= 3.3 Kilohms,

T A = +25 0 C unless otherwise noted)

FIGURE 2 - DC TEST CIRCUIT WITHOUT REFERENCE
INPUT SIGNAL VDLTAGE (B-Y AND R-Y)

FIGURE 3 - DC OUTPUT VOLTAGE TEST CIRCUIT
WITH NORMAL REFERENCE INPUT VOLTAGE
(B, R.AND G)

(For Testing Quiescent Current, DC Output Voltage,
Difference Voltage)

2.2 k

'------<~.

v+

'-----~~--__

Io.I"F

v+

B·Y REFERENCE INPUT

'------<

R-Y REFERENCE INPUT

FIGURE 4 - DYNAMIC TEST CIRCUIT
RED
OUTPUT

GREEN
OUTPUT

T

r~t=~==:;==~======~~O.I"F

LUMINANCE INPUT

lJLr OV

50

2.2 k

v+
'--~----~--t---~+Z4V

470

47pF
3.58 MHz
REFERENCE
INPUT

1.0 Vp·p

I

7-27

MC1326 (continued)

FIGURE 5 - CIRCUIT SCHEMATIC

8-V REFERENCE 13

DC REFERENCE

INPUT

INPUT

.-~r-

100

100

100

12 R-V REFERENCE

INPUT

5

______~~r-4-____-+__+--+____________-+__-+________-i______~____'-_'04 v+
".

R1
3k

3.n

Uk

2k
3k

B·Y CHROMA
8 INPUT

CHROMA
100CINPUT

R·Y CHROMA
9

INPUT

CIRCUIT OPERATION
high quiesoont current (>5 rnA) in order to pass large high frequency components without distortion. The filtering reduces the
quiescent current required in the emitter followers and thus 1'educes diSSipation in the integrated circu it.

A double sideband suppressed carrier chroma signal flows between

the bases ofthe two differential pairs, 016 and 017,018 and 019.
A reference signal of approximately 1 Vp·p amplitude having the
same frequency as the suppressed chroma carrier with an appro·
priate phase relationship is supplied between the bases of the upper
differential pairs 06 and 07, 08 and 09,010 and 011,012 and

If it is not required to mix the luminance signal via 01, this transistor can be used for brightness control. If the base of 01 is
connected to a suitable variable dc voltage, this will vary the de
output levels of the three detected outputs acoordi ngly and
thereby vary the picture brightness level.
Blanking of the picture during line and frame flyback may be
achieved by applying a positive-going blanking signal to the base
of 022. With an extra external resistor in series with the a1 base
of approximately 5 k ohms, when Q22 is turned on by the blanking pulse, the base of 01 will be pulled negative by the current in
R 1, thus forcing all three detected outputs to go negative by the
same amount. In a conventional solid·state receiver with a single
video output stage driving the picture tube cathode, a negativegoing signal at the base of the video output stage will blank the
picture tube. When using the blanking in~ut be certain the blanking pulse does not switch off the luminance input stage 01 completely; this would turn off the collector supply for the demodu·
lators and put the entire chroma demodulator out of lock at each
blanking pulse.

Q13. The upper pairs are switched between full conduction and
zero conduction at the carrier frequency rate. The collectors of
the upper pairs are cross-coupled so that "doubly balanced" or

"fu II-wave" synchronous detected chroma signals are obtained.
Both positive and negative p~ases of the detected signal are available at opposite collector pairs.
While the detector section is almost identical to other available
units, several excellent additionpl features ~re incorporated.
Transistor Q1 is used as an emitter follower to which the collector
load resistors of the detectors are returned. The collector impedances of the upper pair transistors are high compared with the
collector load resistors, and any signal at the emitter of Q1 appears
virtually unattenuated at the collectors of the upper pairs, and
hence at the three detector output terminals. This feature may be
used to mix the correct amount of the luminance portion of the
oolor TV signal with the color difference signals produood by the
detectors to give R·G·B outputs directly.
Capacitors Cl, C2, and C3 compensate for most of the high fre·
quency roll·off in the luminance signal, This is due to the collector
capacitances of the detector transistors and the input capacitances
of the emitter followers, 02, 03, 04, Capacitors Cl, C2, and C3
provide filtering of carrier harmonics from the detected color dif·
ference signals. This increases the available SWing before clipping
for the color difference signal, and reduces the high frequency
components which must pass through the emitter followers (02,
03, 04) into the video output stages. Since high capacitanoo·
(>100 pF) is characteristic of the input impedance of a video
output stage, the transistor emitter followers must operate at a

Matrix for MC 1326
R·Y ga.in = 0.77
8·Y gain
-G.y = 0.11 (B·Y) + 0.28 (R.y)
For indicated requirements and output functions of the MC 1326
chroma demodulator please refer to the typical application shown
on the first page of this specification.

7-28

MC1326 (continued)

TYPICAL CHARACTERISTICS
(TA = +25 0 C un less otherwise noted)
(Figures 6 through Figure 10 Reference Test Circuit of Figure 2)
FIGURE 6 - DC OUTPUT VOLTAGE

FIGURE 7 - POWER DISSIPATION

16

400

~
~

1i:
>-

V+= 24 Vdc

::>

'"
'"OJ

...'"
I

Iz

15

'"
;::

f..-- I---

14

~

200

'"

w
'-'

l...---

'"

v+= 20 Vdc

f..-o

2.0

1.0

3.0

n

4.0
5.0
6.0
7.0
LOAD RESISTANCE (k OHMS)

9.0

B.O

100

o

20

10

21

22

FIGURE 8 - DC OUTPUT VOLTAGE

15

~

RL = 3.3 k OHM/-"

'"'"

./

V

,/'

I

14

I

N-

'"z
Q;

13

/

12
20

V
21

I'--..

~

~ 200

/

'"\l!

~

25
23
24.
SUPPLY VOLTAGE (Vdc)

22

26

27

100

o
o

2B

I

~

~

14 -

::>

TOPIN3.

~

'"
'"OJ
'"1

B.O

a:
c.

10

V

B.O
19

20

~

'"fil

23

24

B.O

9.0

10

25

-

4.0

f...--

3.0

8t;;

2.0

'"

1.0

o

26

7-29

I.

_)

f0-

o

PIN 3 - LUMINANCE INPUT(Vdc)

Vd~

vl

= 24
RL =3.3kohms

5.0

::>

22

7.0 -

~

::>

21

4.0
5.0
6.0
7.0
LOAD RESISTANCE (k OHMS)

w

'">->

V
V
lB

3.0

OJ

.

./

RL =3.3 k OHMS./

N-

2.0

Chroma Input Signal = 300 mVp-p
6.0 r--luminance Input = 0

C

12

~

'"Q;z

V

I

I

::>

1.0

FIGURE 11 - DETECTED OUTPUT VOLTAGE
(Reference Test Circuit of Figure 4)

FIGURE 10 - DC OUTPUT VOLTAGE

V+ = 24 Vdc
,_
CHROMA INPUT VOLTAGE = 0
REFERENCE INPUT VOLTAGE = 0
CONNECT VARIABLE DC SUPPLY

r-+:t

r--.... N~L

C

16

C

2B

27

300

z

'"

::>

...'"

26

400

::>

OJ

23
24
25
SUPPLY VOLTAGE (Vdc)

FIGURE 9 - POWER DISSIPATION

16

~

V

~

13

12

C

/'"

~=3.3kOHMS

....-V

~

N

'"Q;z

.--

300

~

/'"
0.2

0.4
O.B
1.0
1.2
0.6
REFERENCE INPUT SIGNAL AMPLITUDE (Vp·pl

B

r---

R

l-

G

r--1.4

1.6

MC1326 (continued)

TYPICAL CHARACTERISTICS (continued)
(T A = +250 C unless otherwise noted)
(Figures 12 through Figure 17 Reference Test Circuit of Figure 4)
FIGURE 12 - OUTPUT VOLTAGE
10
9.0 I--

CH~OMA INJUT VOLtAGE = 1~ m'lp.pl

7.0

'"~

6. 0

BL~

~ 4.0

V

14

o

12

~

10

>

V

V
1. O~
oV
o

16

'"

~

~ ",/

~V

2.0

~

w

k:/: " / GREEN

3.0

18

~

V

V
~V

REO

I-

o

./
./

~ 5. 0
:::>

./

REFERENCE INPUT VOLTAGE = 1.0 Vp·p

~ 8. 0

~
w

FIGURE 13 - GREEN OUTPUT
20

:=g

8.0

z
~

6. 0

eI

4.0

REFEJNCE IINPUT JOLTAdE = 1.0IvP'p-

-- 6.0

1.0

2.0

ot-o

8.0

7.0

~
~

4.0

2.0
4.0
5.0
3.0
6.0
2.0
LUMINANCE INPUT VOLTAGE (Vp·p)

-

(CLIPPING)

'--

8.0 Vp·p LUM.

0.1

........

-

0.2

FIGURE 14 - RED OUTPUT

r-r--

1.0

'0

0.3
0.4
0.5
0.6
0.7
0.8
CHROMA INPUT VOLTAGE (Vp'p)

0.9

1.0

FIGURE 15 - BLUE OUTPUT
20

INPU~ VOLLGE =11.0 vp.J

18 f-REtERENfE
'?-

21 6
w

'"

~

.I.
(CLIPPING)

~ 1-...2' ~~- - r -

14 t-8.0tP'PLJM.

~

2-1k..~//
. / ' +-~ t:::::::
VV V-~ I '
1o

2:

,8.

~

6. 0

~

>

:=

1

w

4.

//K

O~~ V
~ ./V'"

/,I'.......:::V

k---:::~V

V /V/'t::-Y.
:VV:')V 21

1'0

2.
0.1

I

0.2

0.3
0.4
0.5
0.6
0.7
0.8
CHROMA INPUT VOLTAGE (Vp·p)

0.9

o~

1.0

o

FIGURE 16 - LUMINANCE BANDWIDTH
+2.0

-

+1.0

... V

~ -1.0
:::>

~

-2. 0

\

~

-3. 0

0:

REFERENCE INPUT VOLTAGE = 1.0 Vp·p
-4.
Of-- CHROMilNPUTVOLYGE =0.1 VP'PI

.........

1.0

CHROMAINPUTVOLTAGE=O.1 Vp·p

\

-

~ -t.Of------j--~
".___+----_t_---___i

~ -1.51-----+---\-''>+\----+------1
~ -2.0f------j----->t-----_t_---___i

\

~ -2.5f------+----t~~---t_---_1

~ -3.0f------t-----+-----',,"'--t----_1
0:

-5.0

-6. 0

0.9

f-----!......--- REFER1ENCE INPUT VOL ~AGE = 1.0 Vp·p_

-0.5f------t-~-"'," .LUMINANCEINPUT=O

\

>

0.3
0.4
0.5
0.6
0.7
0.8
CHROMA INPUT VOLTAGE (Vp·p)

FIGURE 17 - CHROMA BANDWIDTH

\

I-

1.0
0.2

+o.5,-----,-----,----,-------,

.........

V

0.1

-3.5!-----t----+--""'
.........
rl---_1
"

""":-------1

-4.0 t - - - - - t - - - - - - t - - - - - f....

o

1.0

4.0
2.0
3.0
LUMINANCE INPUT FREQUENCY (MHz)

-4.5~0-----::0.':-5---~1:':.0:------:'1'::.5-~---;:!2.0

5.0

CHROMA MOOULATION FREQUENCY (MHz)

7-30

,-----,I

'\

MC1327

CHROMA DEMODULATOR

'-_ _ _ _ _ _ _- - - - - - - - l

DUAL DOUBLY BALANCED
CHROMA DEMODULATOR

DUAL DOUBLY BALANCED CHROMA
DEMODULATOR WITH RGB MATRIX, PAL
SWITCH, AND CHROMA DRIVER STAGES

with
RGB OUTPUT MATRIX
AND PAL SWITCH
MONOLITHIC SILICON
INTEGRATED CIRCUIT

· .. a monolithic device designed for use in solid·state color television
receivers.
• Good Chroma Sensitivity - 0.28 Vp·p Input Typical
for 5.0 Vp·p Output
o Low Differential Output DC Offset Voltage - 0.6 V Maximum
•

Differential DC Temperature Stability - 0.7 mV/oC

•

High Blue Output Voltage Swing - 10 Vp·p Typical

P SUFFIX
PLASTIC PACKAGE
CASE 646
TO·116

• Blanking Input Provided
• Luminance Bandwidth Greater than 5.0 MHz
PQSUFFIX
PLASTIC PACKAGE
CASE 647

FIGURE 1 - TYPICAL APPLICATION CIRCUIT

+230 V

PAL
SWITCH

:~:ru1.JL

LUMINANCE SIGNAL Y
INPUT

1

+24 V

O.'"F~

O.1l41jJF
NC

6

14

41

? .. ~~,,?

12k

~

12

REFERENCE
SIGNAL

MC1321

6.8k,10W,5%

MPSU1D
OREDUIV
REFERENCE

SIGNAL
13

b~
..·.. B.Y"~ 0

10

41

MPS6544

DR EOUIV

2x470pH
4.7k

Uk

O.22,uF

I

D.OljJF

II
R·Y

MPSUIO
DR EQUIV

12k

O.DlpF

"

MPS6S44
OR EaUIV

H

CHROMA SIGNAL

Uk

See Packaging Information Section for outline dimensions.

7-31

MC1327 (continued)

MAXIMUM RATINGS (TA = +250C unl... otherwise noted)
Value

Rating

Unit

Power SupplV Voltage

30

Vdc

Chroma Signal Input Voltage

5.0

Vpk

Reference Signal Input Voltage

5.0

Vpk

Minimum Load Resistance

3.0

kohms

Luminance I nput Voltage

12

Vp-p

Blanking I nput Voltage

7.0

Vp-p

625
5.0

mW
mW/oC

-20 to +75

°c

-65 to +150

°c

Power Dissipation (Package Limitation)

Plastic Packages
Derate above TA = +25 0 C
Operating Temperature Range (Ambiend
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (Vce = 24 Vdc, RL = 3.3 k ohms, T A
Characteristic

= +250 C unless otherwise notad)

Pin No.

Min

Typ

Max

Unit

1,2,4

13.2

14.5

15.8

Vdc

16

7.5
19

26

STATIC CHARACTERISTICS

Quiescent Output Voltage
(See Figura 2)
Quiescent Input Current from Supply (Figure 2)

mA

(RL=CO)
(RL = 3.3 k ohms)

-

Reference Input DC Voltage (Figure 2)

5,12,13

-

6.2

-

Vdc

Chroma Reference Input DC Voltage (Figure 2)

8,9,10

-

3.4

-

Vdc

Differential Output Voltage
(See Note 1 and Figure 2)

1,2,4

-

0.3

0.6

Vdc

Differential Output Voltage

1,2,4

-

0.7

-

-

+0.5

±5.0

mV/oC

Temperature Coefficient (See Note 1 and Figure 2)

(+2SoC to +65 0 C)

Output Voltage Temperature Coefficient
(Sea Note 1 and Figure 2)
(+250 C to +65 0 C)
DYNAMIC CHARACTERISTICS (VCC

= 24 Vdc,

1,2,4

RL

= 3.3 k ohms, Reference Input Voltage = 1.0 Vp-p, TA = +250 C unless otherwise noted)

Blue Output Voltage Swing
(See Note 2 and Figure 3)
Chroma Input Voltage (B Output
(S.. Note 3 and Figure 3)

mV/oC

= 5.0 Vp-p)

Luminance Input Resistance
Luminance Gain From Pin 3 to Outputs

4

8.0

10

-

Vp-p

8

-

280

550

mVp-p

3

100

-

-

kn

-

0.95
-1.8

-

dB

-

0.3

-

-

1.1
75

-

-

1,2,4

(@dc)
(@ 5.0 MHz, reference at 100 kHz)
Differential Luminance Gain, RGB Outputs

dB

(@5.0MHz)
Blanking Input Resistance

6

(1.0 Vdc)
(OVdc)

kn

-

Detected Output Voltage (Adjust B Output to 5.0 Vp-p, Luminance
Voltaga = 23 V)
(See Note 4)
G Output
R Output

4

PAL Switch Operating Voltage Ranga
(7.8 kHz Square Wave)

11

1
2

Vp-p

1.4
2.5

1.8
2.9

2.2
3.3

0.3

-

3.0

Vp-p
mVdc

1,2,4

-

100

Demodulator Unbalance Voltage (no Chroma Input Voltaga and
normal Reference Signal Input Voltage)

200

300

mVp-p

Residual Carrier and Harmonics Output Voltage (with Input Signal

1,2,4

-

0.6

1.0

Vp-p

Reference Input Resistance (Chroma Input = D)

12,13

-

2.0

12,13

-

6.0

Chroma Input Resistance

8,9,10

-

2.0

Chroma I nput Capacitance

8,9,10

-

2.0

-

kn

Reference I nput Capacitance (Chroma Input = D)

R-Y Output dc Offset with PAL Switch Operation

Voltaga, normal Reference Signal Voltage and B Output

= 5.0 Vp-p)

pF
kn
pF

NOTES: 1. Chroma Input Signal Voltage"" 0 and normal Reference Input Signal Voltage = 1.0 Vp·P.
2. With normal Reference Input Signal Voltage, adjust Chroma Input Signal Voltage to 1.2 Vp-p.
3. With normal Reference Input Signal Voltage, adjust Chroma Input Signal Voltage until the Blue Output Voltage"" 5.0 Vp-p.
4. With normal Reference Input Signal Voltage, adjust Chroma Input Signal Voltage until the Blue Output Voltage'" 5.0 Vp-p. At this point, the
Red and Green voltages will fall within the specified limits.

·Symbols conform to JEOEC Engineering Bulletin No.1 when applicable.

7-32

MC1327 (continued)

MC1327 CHROMA DEMODULATOR (PAL)

,.y

DC
INJECTION

INJECTION
13

5

A·Y
B·Y OUTPUT

~:.

r---

02

LUMINANCE
INPUT

,

G-Y OUTPUT

INJECTION

R-Y OUTPUT

~:.

12

~:.
0'

0'

14
OJ

12pF

6.H

12pF;:

13k

10k

'Ok
12pF

'3k

2.4k

rk-¥~

4.2k

~3-

~-*

2.0k

?-

1 ..

--J:!' .'2k

BLANKING
INPUT

~'O.24k O.24k~

O.12k a * -

a~

l.Ok

~ -tf'

a~

an

"'"

1.0 ..

3.4k

3.4k

100

'Ok

2.0k

2.0k

a24

oo~
I.Sk

1

-:

,
B-Y CHROMA

10
CHROMA

,
R-YCHROMA

DC
REFERENCE

7-33

11
PAL SWITCH SIGNAL

t-

~
9.5k

D~

*
3.0k

,

3.6 ..

-

,

I.Sk
4.3k

2.0k

Vee

(+24Vdc)

13k

D2B

2.0k

~'

2.0k

,

~

1.0k

I

MC1327 (continued)

TEST CIRCUITS
(VCC

= 24 Vdc,

RL

= 3.3 kilohms, T A = +2SoC unless otherwise noted)

0.1

~F

RL

RL

RL

FIGURE 2 - DC OUTPUT VOLTAGE TEST CIRCUIT
WITH NORMAL REFERENCE INPUT VOLTAGE
(B, R, AND G)
Vee

FIGURE 3 - DYNAMIC TEST CIRCUIT
GREEN OUTPUT

RED OUTPUT

BLUED UTPUT

.,j;

0.'

.'

RL

RL

RL

. -1
O.l/-1F

*n'

TO'

,.'

CHROMA
INPUT

50

I,

3

4

5

1

,

MC1327

7'

10

o,J

"1

"

5.1k

I
12

13

=

LUMINANCE INPUT

lllJ

Uk
14

Vee
+24V

lO.01I-1 F

01

4.7k

"'1 1°'"
E

O.D47;.!F

7-34

:•

B·Y REFERENCE INPUT

RY REFERENCE INPUT
PAL SWITCH SIGNAL

OV

~f

MC1328

l _____

D_U_A_L_C_H_R_O_M_A_D_E_M_O_D_U_L_A_T_O_R_.....

DUAL DOUBLY
BALANCED CHROMA
DEMODULATOR
MONOLITHIC DUAL DOUBLY
BALANCED CHROMA DEMODULATOR

Monolithic Silicon
Integrated Circuit

o Good Chroma Sensitivity (0.3 Vp·p Input Produces 5.0 Vp·p
Output)
o Good dc Temperature Stability (3 mV fOC typ)
o Low Output dc Offset Voltages (0.6 V max)
• Pin Compatible with ULN·2114, ULN·2114A
o Negligible Change in Output Voltage Swing With Varying 3.58 MHz
Reference.Signal
o High Ripple Rejection Due To Built·ln MOS Filter Capacitors

G SUFFIX

PSUFFIX

METAL PACKAGE
CASE 603·02

PLASTIC PACKAGE

(TO·l00)

(TO·116)

CASE 605

o High Output Voltage Swing (10 Vp·p Typ) - B·Y

PQSUFFIX
PLASTIC PACKAGE
CASE 647

FIGURE 1 - MC1328 TYPICAL APPLICATION
+250Vdc
+24Vdc

10k

200J.lH

Number adjacent 10 terminal is the pin numherlor plastic packages•
number in 0 is the corresponding pin number for the metal package.

0.01
CHROMA INPUT
SIGNAL

~F

e-------1f-----:<>-i

3.58 MHz
CHROMA REFERENCE ....--.-~f--..-=.:c...:II-.....J
INPUT

A practical application is given above to indicate the requirements
and output functions of this chroma demodulator. There are other
methods of achieving the matrix of the Chroma-Y and the lumi·

nance compopents without degradation of performance other than
the one indicated. E.g., it is a common practice for color TV manu·
facturers to matrix in the picture,tube.
See Packaging Information Section for outline dimensions.

7-35

I

MC1328 (continued)
MAXIMUM RATINGS (TA

=+250 C unless otheowise specified)

Rating

Value

Power Supply Voltage

Unit

30

Vdc

Power Dissipation (Package Limitation)
Plastic Packages
Derate above TA .. +2SoC
Metal Package
Derate above TA .. +2SoC

625
5.0
650
4.5

Jrl{V

Chroma Signal Input Voltage

5.0

Reference Signal Input Voltage

5.0

Vpk

Minimum Load Resistance

3.0

k ohms

o to +75

°c

-65 to +150

°c

Operating Temperature Range (Ambient)

Storage Temperature Range

mW/oC

mW
mW/oC
Vpk

Maximum Ratings as defmed In MI L-S·19500, AppendIX A.

ELECTRICAL CHARACTERISTICS (V+ = 24 Vdc, RL = 3.3 k ohms, Reference Input
STATIC CHARACTERISTICS
Voltage = 1.0 Vp·p, TA = +250 C unless otheowise noted)
PinNa.
Suffix G Pkg
7,8,9

Characteristic
Quiescent Output Voltage
See Figure 2

PinNa.
Suffix p. PO Pkgs

Min

9,11,13

13

Quiescent Input Current (See Fi9Ure 2)

TV.
14.3

Ma.
16

6.0

(R L = co, Chroma and Reference
I "put Voltages'" O)
(AL = 3.3 k ohms, Chroma and

16.5

19

Unit

Vdc
mA

25.5

Reference Input Voltages"" 0)
Reference Input DC Voltage

4,5

6,7

6.2

Chroma Input OC Voltage

2,3

3,4

3.4

Differential Output Voltage
See Note 1 and Figure 3

7,8,9

9,11,13

0.3

Output Temperature Coefficient
(No Output Differential Voltage
> 0.6 Vdc, +2So C to +650 CI
See Note 1 and Figure 3

7,8,9

9,11,13

3.0

DYNAMIC CHARACTERISTICS (V+ = 24 Vdc, RL = 3.3 k ohms,
Referenced Input Voltage = 1.0 Vp-p, TA
13

Detected Output Voltage IB-YI
See Note 2

Vdc
0.6

Vdc
mV/oC

=+2SoC unless otherwise noted)
8.0

Chroma Input Voltage
IS-Y Output = 5.0 Vp-pl
See Note 3
Detected Output Voltage
(Adjust B·Y Output to 5.0 Vp-pl
See Note 4
G-Y

Vdc

Vp-p

9.0
0.3

0.7

Vp-p

0.75
3.5

1.0
3.8

1.25
4.2

Vp-p

11

9-8
9·7

13·11
13·9

101
248

106
256

111
264

Degrees

7,8,9

9,11,13

250

500

mVp-p

5-9

7·13

7,8,9

9,11,13

Reference Input Aesistance
(Chroma Input - 0)

4,5

6,7

2.0

kohms

Reference Input Capacitance
{Chroma Input'" 01

4,5

6.7

6.0

pF

Chroma Input Resistance

2,3,

3,4

2.0

kohms

Chroma Input Capacitance

2,3

'3,4

2.0

pF

R-Y

Relative Output Phase
IS-Y Output'" 5.0 Vp-p)
B-Y to R-Y
4.0 Vp-p
B·Y to G-Y

256°
106°

5.0Vp-p

,

, 1.0Vp-p

I
I
Demodulator Unbalance Voltage
(no Chroma Input Voltage and
normal Reference Signal
Input Voltage)
B-Y Phase Shift
(B-Y Reference Input to B-Y Outputl
Residual Carrier and Harmonics
(with Input Signal Voltage,
normal ReferenceSignal Voltage
and B- Y '" 5.0 Vp-pl

Degrees

1.5

Vp-p

NOTES:
1. With Chroma Input Signal Voltage"" 0 and normal Reference Input Signal Voltage (1.0 Vp-p l,all output voltages will be within specified
limits and will not differ fram each other by greater than 0.6 Vdc.
2. With normal Reference Input Signal Voltage, adjust Chrome I nput Signal Voltage to 0.6 Vp-p.
3. With normal Reference Input Signal Voltage, adjust Chroma Input Signal Voltage until the B·Y Output Voltage = 5 Vp·p. The Chroma Input
Voltage at this point should be equal to or less than 0.7 Vp-p.
4. With normal Reference Input Signal Voltage, adjust the Chroma Input Signal until the B·Y Output Voltage = 5 Vp-p. At this paint, the R-Y
and G-Y voltages will fall within the specified limits.

7-36

MC1328 (continued)

TEST CIRCUITS
(v+

= 24 Vdc,

RL

= 3.3 kn, TA = +25 0 C unless otherwise notedl

FIGURE 2 - TEST CIRCUIT WITH NO REFERENCE INPUT SIGNAL

V+

FIGURE 3 - TEST CIRCUIT WITH REFERENCE INPUT SIGNAL
(Quiescent Current, DC Output Voltage, Difference Voltage)

R·Y REFERENCE INPUT
B·Y REFERENCE
INPUT

V+ .....-

......----'

B·Y REFERENCE INPUT
V+ ::to.I"F
R·Y REFERENCE INPUT

TYPICAL CHARACTERISTICS
FIGURE 5 - DETECTED OUTPUT

FIGURE 4 - DETECTED OUTPUT
20
18 r--1V+ =

~

~
w

..
to

:;
0

...>

'"
I!:
'"
0

...ffi~
i;;

8.0

21

Vdc
RL=3.3kohm,

16

_I,

I

6.

r--- Reference Input Signal = 11.0 VP"r

14

B'~%

12

.Y

/'

10

..
w
to

V

:;
0

V./

6.0

/., V
/'

4.0

0

2.0

o~
o

-

0.2

0.4

0.6

4.0
3.0

ffi

-

r--

0.8

6.0

50

S

G·

~

)= 24VdCl
=

t--RL 3.3k ohm'
_I.
_I.
Chroma Input Signal = 300 mVp-p

-

5.0

...>
~

R·Y

./

/

8.0

~

7.0

1.0

1.2

1.4

1.6

1.8

2.0

R·Y ) - -

V-

2.0
1.0

o

CHROMA INPUT SIGNAL IVp·p)

B·Y ) - -

!--

o

G·Y

/
0.2

0.4

0.6

0.8

1.0

1.2

REFERENCE INPUT SIGNAL AMPLITUDE IVp·pl

7-37

1.4

1.6

I

MC1328 (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 7 - DC OUTPUT VOLTAGE

FIGURE 6 - DETECTED OUTPUT VOLTAGE

8.0

16

a.

7.0 f-- ch!oma Sigtl = 3001mVp·p

~
w

6.0

to

Reference Input Signal = 1.0 Vp·p

I-- RL: 3.3 k ohm,

15

~o

5. 0

B·Y

~

4. 0

R·Y

>

I!:
=>

C.

-

'"

"

~
c

-

>

3.0

!;

~ 2.0

=>

o

c

14

~

0

G·Y

1.0
20

21

22

24

23

25

27

26

13

-

o
28

12
2.0

29

-

V+

3.0

4.0

SUPPLY VOLTAGE (Vde)

-

RL:

3.L

V

ohms

/"

w

to

~

./

14

>
>-

0

~ 300

.sz

/"

0

V

i=

;::
iii

/

=>

I!:
=>

13

7.0

6.0

8.0

400

C.
c

5.0

FIGURE 9 - POWER DISSIPATION

FIGURE 8 - DC OUTPUT VOLTAGE

15

20 Vde

LOAD RESISTANCE Ik OHMS)

16

~

-

V+- 24Vde

I':

Ii:

:;;

-

w

V

200

i5

'"

~

/

100

-

~

RL: 3.t ohms

--

V

.- ~

....V

12
20

21

22

23

24

25

27

26

28

20

22

21

SUPPLY VOLTAGE IVde)

23

FIGURE 10 - POWER DISSIPATION
40 0

I

300

.......

z

o

~~

20

o ......

i5

'"\\!
~

"'I'--..........

---

--

r--

10 0

0
2.0

24

25

SUPPLY VOLTAGE IVde)

3.0

4.0

V+: 24 Vde

r---

5.0

V+

20 ide

6.0

LOAD RESISTANCE Ik OHMS)

7-38

7.0

8.0

26

27

28

MC1328 (continued)

FIGURE 11 - CIRCUIT SCHEMATIC

B-Y REFERENCE INPUT

R-Y REFERENCE INPUT

®)

®

6

,-------~r-~------~~--~----------+--4~------~----------~---.----¢v+
13k

®

al3

CHROMA INPUT

3k

2.3 k

14

GROUNOG)~l~--------~---------lr-----~------N-um-b-e-ra-di-ac-e~nt~to-t-er-m-in-al-is-t-he-p-in-n-u-m-be-r-fo-rt-h-ep-Ia-st-ic~-----4~------)
Q) 4
CHROMA INPUT

packages, number in
metal package.

0

is the corresponding pin number fer the

CIRCUIT OPERATION
Capacitors Cl, C2 and C3 provide filtering of carrier harmonics
from the detected color difference· signals. This increases the available swing before clipping for the color difference signal, and reduces the high frequency components which must pass through the
emitter followers (01, 02, Q3) into the video output stages. Since
high capacitance (>100 pF) is characteristic of the input impedance
of a video output stage. the transistor emitter followers must operate at a high quiescent current (>5 rnA) in order to pass large high
frequency components without distortion. The filtering reduces
the quiescent current required in the emitter followers and thus
reduces dissipation in the integrated circuit.

A double sideband suppressed carrier chroma signal flows between
the bases of the two differential pairs, 015 and 016, 017 and 018.
A reference signal of approximately 1 Vp-p amplitude having the

same frequency as the suppressed chroma carrier with an appropriate phase relationship is supplied between the bases of the upper
differential pairs 05 and 06, 07 and 08, 09 and 010, all and
Q12. The upper pairs are switched between full conduction and
zero conduction at the carrier frequency rate. The collectors of
the upper pairs are cross-coupled so that "doubly balanced" or
"full-wave" synchronous detected chroma signals are obtained.
Both positive and negative phases of the detected signal are available at opposite collector pairs.

7-39

I

MC1330P

1L~

_______________

V_I_D_E_O_D_E_T_E_C_T_O_R__~

LOW-LEVEL VIDEO
DETECTOR

MONOLITHIC LOW-LEVEL VIDEO DETECTOR

MONOLITHIC SILICON

. an integrated circuit featuring very linear video characteristics,
wide bandwidth. Designed for color and monochrome television reo
ceivers, replacing the third IF, detector, video buffer and the AFC
buffer.
•

INTEGRATED CIRCUIT

Conversion Gain - 34 dB typ

• Video Frequency Response @ 6.0 MHz

< 1.0 dB

•

I nput of 36 mV Produces 3.0 Vp-p Output

•

High Video Output - 7.7 Vp-p

•

Fully Balanced Detector

•

High Rejection of I F Carrier

•

Low Radiation of Spurious Frequencies
PLASTIC PACKAGE
CASE 626

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted I
Rating

Unit

Value

Power Supply Voltage

+24

Vdc

Supply Current

26

mAde

I "put Voltage

1.0

Vlrms)

625
5.0

mW
mW/oC

o to +75

°c
°c

Power Dissipation (Package Limitation)
TA = +25 0 C
Derate above T A

= +250 C

Operating Temperature Range (Ambient)

-65 to +150

Storage Temperature Range
MaXimum Ratings as defined

In

MIL-S-19500, AppendiX A.

FIGURE 1 - DETECTED COLOR BARS

FIGURE 2 - PULSE RESPONSE

,

Iii
3

p-p

III
-

I'

,I

-= I I::::=
,.
1.01's/DIV.

7.5I's/DIV.

See Packaging Information Section for outline dimensions.

7-40

OU PUT

OLT

GE

0.3 "

IN UT E

VEL

PE

MC1330P (continued)

ELECTRICAL CHARACTERISTICS (v+ = 20 Vdc, Q = 3D, fC = 45 MHz, T A = +25 0 C unless otherwise noted.)
Unit

Pin

Min

Typ

Max

Supply Voltage Range

6

12

20

24

Vdc

Supply Current

5,6

-

15

-

mA

Zero Signal dc Output Voltage

4

6.8

7.7

8.3

Vdc

Maximum Signal de Output Voltage

4

-

0

-

Vdc

Input Signal Voltage for 3.0 Vp-p Video Output

7

-

36

-

mV(rms)
Vp·p

Characteristic

(90% Modulation)
Maximum Output Voltage Swing

4

-

7.7

-

Carrier Rejection at Output

4

42

60

-

dB
mV(rms)

Carrier Output Voltage (at 3.0 Vp·p output!
f out = fC
f out = 2fC

-

1.0
3.0

-

3.0 dB Bandwidth of IF Carrier

7

-

80

-

3.0 dB Bandwidth of Video Output

4

12.3

-

MHz

Input Resistance

7

-

-

kilohms
pF

4

-

3.5
3.0
180

-

ohms

2,3

-

4.4
1.0

-

kilohms
pF

1

-

350

Input Capacitance

Output Resistance
I nternal Resistance }
(across tuned circuit)
Internal Capacitance

AFT Buffer Output at Carrier Frequency

G)

A FT Buffer dc Level

CD

1

MHz

-

6.5

mVp·p
Vdc

Measured with 10 times probe.

FIGURE 3 - CIRCUIT SCHEMATIC
TUNEO CIRCUIT

3

4.B k

~

I

1.1k

B.4 k

1.1k

6

6.4k

----<

V

~1~

3.6 k

1

r--.

~rt-~

::

~

k

Bk

V-

""

1.0k

4::

>-

3k

r--.

3k

H
6BO

5k

"0

1.5 k

15

15

.¥I

150

150

'vI
Bk

"-.i

~

~r
530

5k

1.5k

tk

GNO

7-41

I

AFT
BUFFER
0 UTPUT

s-: '"

~~~R

4pF

3 pF

Iv

V-

5.6k

VIOE o
UT
5

7
IF
INP UT

V+

11~ f1.5k

11k

;r;

11 k

PRIM ARY
VIO EO
OUTPUT

MC1330P (continued)

TYPICAL CHARACTERISTICS
(TA = +25 0 C unless otherwise noted)
FIGURE 5 - OUTPUT VOLTAGE

FIGURE 4 - TEST CIRCUIT
IF~
INPUT

B.O

O.OOl.F

"'- ~

4.3 k
AUXILIARY OUTPUT
~

O!
.,.

6.0

0:
ui

MC1330P
10V

-

r-..... f.....

t'--....

z

20V[:h:]

'"

---

'"':;

............

t--..

4.0

>

11

~

>=>

[tr----J

PRIMARY OUTPUT

6.8 k

3.3 k
Cl

7.7V

=

z

6.0

w·

':;
0

,/
4.0

L

...
>

=>

~
0

2.0

/

o

20

40

"-

I F Input = 40 mVlrms)

"'-

~
~

12

14

16

lB

20

22

o

24

10

20

3D

-

-6. 0

1'-...

'\

-6. 0
2.0

4.0

6.0

B.O

~~

1\

\

-10

o

i---

10

12

J.

60

70

BO

90

100

"'~

>-'"
=>'"
~~

-

...=>>-"
o

\

1\

14

~ 1.0

~

-t---

OUTPUT AMPLlTUOE

= 20 vJc
1M = 1 kHz
1---90% MOO
I F Input = 40 mV(rms)
2.0 I--- 0=30

~e 3.0

w'"
005
=>",
!:::z

T

>

~

........

~~

IC=45MHz
IF Input = 40 mV(rms)
70%MOO
V+=20Vdc
0= 30

~ -4.0

t=

o

V

50

1--+-

~
z

+2.0

40

FIGURE 9 - CARRIER FREQUENCY PERFORMANCE

+4.0

fil
o

.,/'"

/

INPUT CARRIER LEVEL ImVlrmsJ)

4.0

o

w

./
./

o
10

~
o
;; -2. 0

i;;

100

./

"'-

FIGURE 8 - VIDEO FREQUENCY RESPONSE

~

r--

BO

90% MOO I
1M = 1 kHz
IC = 45 MHz
0= 3D

/'

~ +6.0

...

60

...... r-...

V+ = 20 Vdc

/'"

SUPPLY VOLTAGE IVdc)

I

--

f--..::
.............

FIGURE 7 - DETECTOR LINEARITY

o
8.0

......
r::::
,..........,.

o

/"

./

............. f.......

15 1VdC

12rC

Y
. /V

"-l.

INPUT VOLTAGE ImVlrmsJ)

IF Input =0

/""

0:

'"'"

r-.....
r-- r-.

A
/'"

~

V+= 20 Vdc

0

FIGURE 6 - OUTPUT VOLTAGE

.,.O!

..........

2.0

O
L1, Cl: See
General Application Notes, #3, last page of this specification.

B.O

r--

r---.. f.......

0

AFT OUTPUT

IC =45 MHz
(unmodulated)_

.........

% OISTORTION

I----

>=>

o
16

0
25

MOOULATING FREnUENCY IMHz)

3D

35

40

45

50

CARRIER FREQUENCY IMHz)

7-42

55

60

65

MC1330P (continued)

APPLICATIONS INFORMATION
FIGURE 10 - COLOR IF AMPLIFIER TYPICAL APPLICATION
r-__~1~k~__-1~____________________-,________~_+~20V 20V - - - - - ]
TUNER
AND
IF INPUT
TRAPS

4.3k

10V-~

7.7V[--AGe 5·8 V

--I

AUXILIARY VIDEO OUTPUT

"'-'IIIIV---+
3.3k

PRIMARY
0].["_
VIDEO AND SOUND OUTPUT

TV-I F Amplifier Information
A very compact high performance IF amplifier constructed as shown
in Figure 11 minimizes the number of overall components and align.
ment adjustments. It can be readily combined with normal tuners
and input tuning-trapping circuitry to provide the performance demanded of high quality receivers. This configuration will provide

approximately 84 dB voltage gain and can accomodate the usual
low impedance input network or, if desired, can take advantage of
an impedance step-up from tuner to MC1350P input (2in ~7.0 kilohms). The burden of selectivity. formerly found between the third

IF and detector. must now be placed at the interstage. Tha
nominal 3 volt peak-to-peak output can be varied from 0 to 7.0 V
with excellent linearity and freedom from spurious output products.
FIGURE 11 - TRANSFORMER

t
~

~

T

lllTr
-1

3/8 ••

1-

Primary Winding: 8turnsof AWG 1126 close wound, CT
Secondary Winding: 6 turns of AWG #26 close wound. CT
Core: Arnold Type TH slugs or equiv.

specific features and information on systems design with this device
are given below:
1. The device provides excellent linearity of output versus input,
as shown in Figure 6. This graph also shows that video peak-to-peak
amplitude (ac) does not change with supply voltage variation.
(Slopes are parallel. Visualize a given variation of input CW and use
the figure as a transfer function.)
2. The dc output level does change linearly with supply voltage.
This can be accommodated by regulating the supply or by referencing the subsequent video amplifier to the same power supply.
3. The choice of a for the tuned circuit of pins 2 and 3 is not critical. The higher the Q, the better the rejection of 920 kHz products
but the more critical the tuning accuracy required. Values of a
from 20 to 50 are recommended. (Note the internal resistance.)
4. A video output with positive-going sync is available at pin 5 if
required. This signal has a higher output impedance than pin 4 so
it must be handled with greater care. If not used, pin 5 may be
connected directly to the supply voltage (pin 6),
5. An AFT output (pin 11 provides 350 mV of clipped carrier output, sufficient voltage to drive an AFT ratio detector, with only one
additional stage.

Alignment is most easily accomplished with an AM generator, set
at a carrier frequency of 45.75 MHz, modulated with a video frequency sweep. This provides the proper realistic conditions necessary to operate the low-level detector (LLD). The detector tank is
first adjusted for maximum detected dc (with a CW input), next,
the video sweep modulation is applied and the interstage and input
circuits aligned, step by step, as in a standard IF amplifier.
Note: A normal IF sweep generator, essentially an FM generator,
will not serve properly without modification. The LLD tank attempts to "follow" the sweep input frequency, and results in variations of switching amplitude in the detector. Hence, the apparent
overall response becomes modified by the response of the LLD tank,
which a real signal doesn't do.
This effect can be prevented by resistively adding a 45.75 MHz CW
signal to the output of the sweep generator approximately 3 dB
greater than the sweep amplitude.

MC1330P General Information
The MC1330P offers the deSigner a new approach to an old problem. Now linear detection can be performed at much lower power
signal levels than possible with a detector diode_
Offering a number of distinct advantages, its easy implementation
should meet with ready acceptance for television designs. Some

7-43

I

I

~f

Mel339P

"\

STEREO PREAMPLIFIER

'-------

DUAL LOW-NOISE
STEREO PREAMPLIFIER

MONOLITHIC DUAL STEREO PREAMPLIFIER

MONOLITHIC
SILICON EPITAXIAL PASSIVATED
INTEGRATED CIRCUIT

· .. designed for low noise preamplification of stereo audio signals.

•
•

Low Audio Noise
High Channel Separation

• Single Power Supply
•

High Input Impedance

...

• Built·ln Power Supply Filter
•

Emitter Follower Output

MAXIMUM RATINGS ITA

rwr~TJ~

= +250 C unless otherwise noted)

Rating

Value

Unit

Power Supply Voltage

+16

Vdc

Power Dissipation (Package Limitation)
(Derate above TA = +25 0 C)

625
5.0

mW
mW/oC

Operating Temperature Range

-40 to +85

Storage Temperature Range

-65 to +150

°c
°c

PLASTIC PACKAGE
CASE 646
TO·116

CIRCUIT SCHEMATIC

CONNECTION DIAGRAM

POWER SUPPLY
FILTER
VCC
+7.5 V
ZENER 2
UTILITY
POWER

ZENER

ROLL. 4
OFF 1
INPUT 1

10

7

3
2400

2400

See Packaging Information Section for outline dimensions.

7-44

RGLTR
GND

FEEDBACK I

FEEOBACK
2

ROLL·OFF I

ROLL·OFF
2

OUTPUT 1

OUTPUT 2

INPUT
RETURN
I
INPUT
I

6
INPUT
RETURN I
FEEDBACK
1

OUTPUT
2

AMPL
GND

INPUT
RETURN
2
INPUT
2

MC1339P (continued)

ELECTRICAL CHARACTERISTICS (Each Preamplifier) (VCC = +12 Vdc TA = +25 0 C unless otherwise noted.)
Min

Typ

Max

Unit

Power Supply Current

-

17.5

22

mA

Voltage Gain

63

66

71

dB

Gain Balance

-

0.3

2.0

dB

Channel Separation (f = 1.0 kHz) See Figure 1,51 in position 1.

45

70

I nput Resistance

100

250

-

kilohms

Characteristic

dB

Signal Output Voltage
No load
3.O-kilohm load

Output Resistance
Power Supply Rejection (f = 1.0 kHz) See Figure 2

33

-

-

1.2

-

-

1.5
1.0
100

V(RMS)
ohms
dB
%

Total Harmonic Distortion without Feedback

(0.5 V(RMS) into a 3.O-kilohm load, 1.0 kHz)
I nput Bias de Current

-

0.8

-

45

-

/lA

Gain to Feedback Terminals (pins 3 and 12)
Impedance at Feedback Terminals

-

2400

-

ohms

0.7

3.0

/lV(RMS)

Equivalent Input Noise Voltage (100 Hz to 10 kHz) See Figure I,
51 in position 2.

dB

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

TEST CIRCUITS
FIGURE 1 - CHANNEL SEPARATION AND
AUDIO NOISE

FIGURE 2 - POWER SUPPLY REJECTION

Vee

1_

11_

1

I
>-+o--_VOI

>--+-0---___ Vo 1

lO.oO'"F

10.00'"F

>+0---___ V02
680

SEPARATlON'VOliV02

7-45

>--+-0--_ V02

I

MC1339P (continued)

APPLICATIONS INFORMATION
The circuit diagrams shown in this section are examples of applica-

FIGURE 5 - TAPE PLAYBACK PREAMPLIFIER

tions for the MC1339P. Included are circuits for a broadband
preamplifier with tap. playback and record amplifiers, and a phono

preamplifier.
0.33JlF

Broadband Amplifiers
The MC1339P is useful as a broadband amplifier in applications
requiring a low-signal level low-noise amplifier. The circuit in Figure 3 fills these requirements with a voltage gain of 40 dB and an
input impedance of 10 kilohms.

TAPE·HEAD

II

OUTPUT

10 k

CI

FIGURE 3 - BROADBAND AMPLIFIER

f'

0.33 ~F
INPUT ..-...1f--___1>----o-l

-=

'>---<>--.-.. OUTPUT

10 k

~F

0.027

E
CF
RI

3.0 k
RF

100

-=

-=

The lower -3.0 dB corner frequency Ifl) is determined by the
value for capacitor C1 in accordance with equation 1.

lOk+lOo
Av=-,-o-o-

~

1

100

Cl

RL = 3 k

100

(1)

The minimum high-frequency gain (5 dB below reference gain of
33 dB) of the amplifier is determined by the ratio of Rl + RF while
Rl

the value of capacitor CF provides the bass boost corner frequency
in accordance with equation 2.

Figure 4 shows the response of the broadband amplifier with two

different values of compensation capacitors, C1. Other capacitor
values can be used; however, as the phase margin is reduced a
greater possibility of oscillation exists.

FIGURE 4 - BROADBAND AMPLIFIER RESPONSE

(2)

Based on measurements made on the amplifier (See Figure 5), the
value of C2 is chosen for a phase margin greater than thirty degrees.
The nearest 100,.6 tolerance component values were used in the
circuit of Figure 5.

70

11111111

60

U~~~ol ~
[llllfj:

50
!g 40

FIGURE 6 - FREQUENCY RESPONSE FOR TAPE PLAYBACK
PREAMPLIFIER ITAPE SPEED 1 7/8 OR 33/41N/S)
60

CI=IJ~

z

~

A3
21Tz3fl

where z3 is the impedance at pin 3 12.4 kilohms) and A3 is the
amplifier gain at pin 311781-

10 k

100JlF

=

30

IIIIIIIIIIJ
Ph,se Margin CI = 1000 pF-45°

50
r ti'[lilln=1 1 111Irl

10

o
10

1111111111
40

100

400 1.0 k

4.0 k 10 k

"'-

z

;;:
'"

111111111
4okl00k

"'-

50

i'

20

40

"-

r-...

4ookl.oM

r-

FREQUENCY (Hz)

30

Tape Playback Preamplifier
20

A low-noise, high-gain preampl ifier to properly process the low-level

output of the magnetic tape-heads is shown in Figure 5 illustrating

40

70100

200

400

7oo1.ok

2.ok

4.ok

7.oklok2ok

FREQUENCY 1Hz)

a tape-head preamplifier using the MC1339P.

Tape Record Preamplifier
The frequency response of a tape recording preamplifier must be
the mirror image of the NAB playback equalization characteristic,
so that the composite record and playback response is flat. Figure
7 shows the record characteristic superimposed on the NAB playback response and Figure 8 illustrates the output characteristic of

To faithfully reproduce recorded music from magnetic tape, special
frequency compensation is required to provide the NAB standard

tape playback equalization characteristics, see the response curves
shown in Figure 6. The circuit shown in Figure 5 is designed to provide an output of 100 millivolts with an input signal of 2.2 millivolts
at a frequency of 1.0 kHz. (Reference gain is 33 dB).

7-46

MC1339P (continued)

APPLICATIONS INFORMATION (continued)

a typical laminated core tape head.
Figure 9 shows the
necessary amplifier response characteristic to make a composite

FIGURE 10 - TAPE RECORD PREAMPLIFIER

signal of Figures 8 and 9 that will meet the proper NAB recording

characteristic of F igu re 7.
R4
33 k
10k
FIGURE 7 - NAB TAPE EQUALIZATION CHARACTERISTIC
CURVES

+25
+20

m~[)5~)~Z

+10

i'-

z

<1

~

REFERENCE
~AINI =1 IdB

n

"-

1111111

/

-5.0
-10

V

-R-f'

-20

II
40

-25
20

3ilor ,1 17/B in/,-

~

RECORD

-15

R3
15 k

""V-

PLAYBACK'

~+5.0

LO

-

,

+15

12 - 1770 H~~ !"<-.:: ~1

The circuit shown in Figure 10 will give the preamplifier response

I

as presented in Figure 9.

',-ct 'h-

1111

I IIII 13 = 31 83t; 7 il2 inl,
400 700 1.0 k 2.0 k 4.0 k 7.0 kiD k
1

70 100

200

1

20 k

The gain is established by the equation
1
R 2 (R 1 + 211 f C3)
R3 + zf
GAIN = - - - where zf =
211f C3

The high corner frequency. f2, is determined by equation 4.

FIGURE 8 - TYPICAL TAPE HEAD OUTPUT
CHARACTERISTICS (constant flux)

+5.0

~f"'"
~

LlI"

-10

.,

-15

z

-20

LO

3 3/4 or 1 718

~

~

<1

in~r\

\

~

-25

1

W~2in~'

,

-5.0

-30
-35

-45
20

40

At high frequencies the feedback impedance zf is Rl in parallel
with R2 and at low frequencies is R2. Again, capacitor Cl is
chosen by equation 1 to give the desired low frequency breakpoint,
fl. As an example, consider a recording head requiring 30 JJA is
used with a microphone with a 10-mV output. The ~O-.uA current
source is simulated by a 1.0 V(RMS) output driving a 33-kilohm
resistor, R4, at the reference frequency of 1.0 kHz. The gain
requirement is therefore 100 or 40 dB. The low-frequency gain is
calculated by letting R2 = 100 ohms and calculating the value of
R3 for frequencies below f2.
R2 + R3

Av=~

70 100

200

400 700 1.0 k 2.0 k

4.0 k 7.0 k10 k 20 k

FREQUENCY (Hz)
FIGURE 9 - TAPE RECORD AMPLIFIER RESPONSE
5
0

5

~

50

"

45

z

~

...-TAPE SPEED

40

33/4inJs
ort7f8in/s

5
30
20

40

70100

200

400

100 l.Ok

2.0k

IIIIII

4.0k 7.0k 10k 20k

(4)

C3 = 211 f2 R2

'"

-40

(3)

R2+(Rl+-~)

zf

FREQUENCY (Hz)

=125

R3 = 124 {R21

~

12 kn.

(5)

A 15-kilohm resistor is used to achieve the gain necessary since
the open-loop gain of the amplifier is not infinite.
The typical response for a quarter-track (3% in/s) tape-head is
3.0 dB down at 1770 Hz. Therefore, the high-corner frequency
(f2) of the record amplifier should be at the same frequency. Using
equation 4 the value of C3 is calculated to be 1.0 J.1.F. Resistor
Rl is not needed to roll-off the high-frequency gain at frequencies
above 20 kHz since the limited open-loop gain of the MC1339P
accomplishes the same thing. The parallel LC circuit at the amplifier output is used to trap the bias oscillator signal and is tuned to
that frequency.
Phonographic Preamplifier
Crystal and ceramic phono-cartridges seldom require a preamplifier
due to high-output signal levels (100 mV to 1.0 VI. However,
magnetic cartridges have output levels of from 2.0 to 12 mVand
require a preamplifier such as the MC1339P. Special equalization
of the preampl ifier is necessary to make the response match the
RIAA recording characteristic which is used universally. The
amplifier shown in Figure 11 does provide the proper response

FREQUENCY (Hz)

7-47

I

MC1339P (continued)

APPLICATIONS INFORMATION (continued)

FIGURE 11 - PHONOGRAPH PREAMPLIFIER
1
f2=--2" Rl C2

MAGNETIC
CARTRIDGE

II

and 13 is calculated from

"-_+---<>-1

Printed Circuit Board Layout

+ CI

"~I

1
f3=--2" Rl C3

RL
3k

C2

0.033 ~F

C3

Most of the circuits in the applications section can be built on
this printed circuit board layout. Printed circuit board design is

not particularly critical with the MC1339P. However, usual layout
practices such as keeping the input and output lines separated and
providing maximum ground plane area should be used. The layout

100

shown is for Figure 5 but it can easily be modified without any

8200 pF

problem for the other application circuits given.

FIGURE 12 - FREQUENCY RESPONSE
OF PHONO-PREAMPLIFIER
(compensated for RIAA Equalization)
+30

f\ ~15~ Hz

+2 0

- ..;,;"" ....

+10

13 = 2120 Hz

nmil

z

~

FIGURE 13 - PRINTEO CIRCUIT BOARO
(copper side shown)

-10

r--::~

I IWI I

Re[eri m
ii1.°

-20

kHi 41 dj

'-

1

-30
-40
20

40

70100

200

II IIII

400

7001.0k 2.0k

3"

I

4.0k7.0kIOk 20k

FREUUENCY (Hz)

for RIAA equalization. Figure 12 iliustrates the RIAA response
of the amplifier in Figure 11. The dashed line shows the
ideal response with the corner frequencies indicated. The lower

corner frequency (11) is determined by the input capacitance Cl
and the equation

AI
11=--2" Cl z3

(6)

where AI is the feedback gain of 45 dB and z3 equals the terminal
The corner frequency f2 is determined by

resistance at pin 3.

7-48

~~____________T_V__S_IG_N_A__L_P_R_O_C_E_S_SO__R~

MC1345P

TV SIGNAL
PROCESSOR

TV SIGNAL PROCESSOR

MONOLITHIC SILICON
INTEGRATED CIRCUIT
· .. a monolithic TV circuit with sync separator, advanced noise
inversion, AGC comparator, and versatile R F AGC delay amplifier
for use in color or monochrome TV receivers.

• Video Internally Delayed for Total Noise Inversion
.. Low Impedance, Noise Cancelled Sync Output
• Refined AGC Gate
o Small IF AGC Output Change During R F AGC Interval
• Positive and Negative Going R F AGC Outputs
o Noise Threshold May Be Externally Adjusted
• Time Constants for Sync Separator Externally Chosen
• Stabilized for ± 10% Supply Variations
PLASTIC PACKAGE
CASE 605

TO·116

FIGURE 1-TYPICAL MC1345 APPLICATION WITH VIOEO IF AMPLIFIER
0.D02/,F

470

220

+18 Vdc

3.3k

VID~80

AUXILIARY
OUTPUT

Vl-;\ --]
......,J h."vt..v.

T1

IOV
- --PRIMARY VIDEO

:GkcJ7r~J o ~ O·ll"4"
fi

MD SOUND OUTPUT

5

TURNS~

t-++---e

__

___

l

5
TURNS

All windings #30 AWG tinned nylon acetate
wire tuned with high permeaoilitycore,

Complele transformer is available from
Coikraft, Type R4786.

AFT OUTPUT

3.9

_-IS
+18 Vdc

+--1-'VV'v--+-----.. ~~ri~N~UllN:EuT
IF

AGC

]JIJ
2_2k

RF

AGC

50llF

.-+-------+---+-.. SYNC OUTPUT

20 k

1.

ns

II wound with
AWG tinned nylon
ilcetatewiretunedbydistortingwinding .

CI
C2

C3
LI

'--j--j-_~AFAGC

T~O~T~U:NE~A-':====!=t==t=;=~H~iOil

2,'

DELAY

See Packaging Information Section for outline dimensions.

7-49

Rl

39 MHz

45 MHz

24 pF
18pF
33pF

15pF
12pF
33pF

12

58 MHz
10pF
10pF
18pF

10 Turns
Turns
See Operating Characteristics,
"Noise Inverter"section.

•

MC1345P (continued)

MAXIMUM RATINGS (TA

=

+25 0 C unless otherwise noted I
Value

Unit

Power Supply Voltage (Pin 111

+22

Vdc

Video I nput Voltage (Pin 11

+10

Vdc

Negative R F AGC Supply Voltage (Pin 31

-10

Vdc

Gating Voltage (Pin 91

15

Vp-p

Sync Separator Drive Voltage (Pin 12)

7.0

Vp_p

625
5.0

mW
mW/oC

o to +70

DC

-55 to +150

DC

Rating

Power Dissipation (Package Limitation)

Plastic Package
Derate above T A

= +25 0 C

Operating Temperature Range (Ambient)

Storage Temperature Range
Maximum Ratings as defined in MI L-S·19500, Appendix A.

ELECTRICAL CHARACTERISTICS (v+ = +18 Vdc. TA = +25 0 C unless otherwise noted I
Unit

Min

Typ

Max

3.6

3.9

4.2

Vdc

-1.3
16

-2.5

mV/ C

Sync Output Amplitude

0
-

-

Vp-p

Sync Output Impedance

-

-

100

Ohms

0.45
-

0.7

0.95

Vdc

0.10

0.5

Vdc

-

15

mAde

-

0.9
-

-

Characteristic
Sync Tip de Level of Input Signal
Temperature Coefficient of Sync Tip (Input)

Sync Tip to Noise Threshold Separation (I "put)
IF AGC Voltage Change During RF Interval
Peak AGe Charge Current
Peak AGe Discharge Current

9.0

IF AGC Voltage Range (See Figures 2 and 31

mAde

Vdc
Vdc

10

Positive A F AGe Voltage Range
Positive A F AGe Minimum Voltage

Negative RF AGC Voltage Range
Negative RF AGC Maximum Voltage
Total Supply Current. IS (Circuit of Figure 1)

FIGURE 2 - TEST CIRCUIT FOR AGC
AMPLIFIER MEASUREMENTS

0.5
-

1.5

2.0

Vdc

10

-

Vdc

9.5
-

10.5

11.5

26

Vdc
mAdc

FIGURE 3 - AGC AMPLIFIER RESPONSE

'C

C
w

+18 Vdc

'"
~
'">

'"
'"«2:
.,.N~

IF AGe

'"
2:

5:

PIN 8 VOLTAGE (Vdc)

20 k

7-50

s(")
~

W

~

c.n

""C

nO

FIGURE 4 - CIRCUIT SCHEMATIC
r------------,r---------,r-AGrn~AND'

I

NOISE INVERTER SECTION

I
I

NOISE INVERTEO 013
VIDEO OUTPUT I

I

II
II 120 SYNC
II
I INPUT

SYNC SEPARATOR SECTION
II
COMPARATOR SECTION
+
lS
AGC
110 V
SYNC 100 II 90 FLYBACK
CHARGING 08
r 18 V
OUTPUT
r, . r INPUT
CAPACITOR

I
I

I ~F

-

-

IE:
I

5k

I
I

-1 ~.
:::l

: D - : : C : : : : : N : E - :::TlON- -

2.7 k

3.4 k

2.7k

5k

I
I

10k

I

10k

I

I

I
~

C11

I

I

6.8 k

I

I

I

800
I

r.

I

1023

I

4
L _ _ _.....

I

-=

I

-=

300

I
I

300

3k

300

300

2k

-=!:-II

-=!:-

' - - - - . . . . . , , . . . . . . - - - - - - - - - - - - < 0 IF AGC

5 OUTPUT

Ii

'1

L~

~

I

I I

_______________ ~L ______ -------~

•

I

I

I

-=
-=!:-

POSITIVE
RF AGC

6
RF AGC
I
' - - - - - - -.....0 OELAY INPUT I

I
I
I 03

5k

o

-=

I

2.3 k

I

22k

I
I

I

I
I

300

300

I

I

I
IL

I

14

I VIOEOOI
INPUT I

I

I

300

150

r

7 GNO

_ ____ _ __________
-=I
~

MC1345P (continued)

OPERATING CHARACTERISTICS
NOISE INVERTER
A composite video signal of from 1 to 3 volts peak-la-peak

or tropospheric sources is common. To prevent this type of interference from spuriously triggering the inverter, some RC filtering is
required between the video detector and the video input at pin 1.
For this filter, RC values of 10 kn and 18 pF are typical.

amplitude with negative-going sync, superimposed on a positive de
offset voltage, is required at the input. pin 1. The amplitude of
the de offset voltage will determine the allowable magnitude of the
video input. since the sync tip will always be clamped at 3.9 V.
See Figure 5.
The noise threshold is set by Q7'5 emitter voltage determined by
032 and the bias-chain Zener diode. The resulting de level (or

SYNC SEPARATOR
The noise-inverted video output at pin 13 is passed through an
external RC filter network, to the sync separator input at pin 12,
cutting off 035, 036, and 037, except during the positive sync
tips. Time constants for the filter are a matter of the designer's
preference, and are chosen as for discrete·circuit sync separators.
Operation of the sync separator is as follows. 035 conducts
only during the positive-going sync pulse. 036 amplifies and inverts
the sync pulse, driving 037 into saturation during the sync pulse
interval. The output of 037 drives the complementary pair,
038/039, which yield a low output impedance negative-going sync
pulse of greater than 15 V peak·to-peak amplitude. It should be
noted that the first sync pulse occurring after noise inversion ends,
will be slightly longer in duration than other sync pulses. Typical
resistance and capacitance values for the RC sync input network
are given in Figure 6A.

noise threshold) may be lowered by adding an external resistor.
Rl (Figure 1), connected from pin 14 to ground. With this arrangement, the lowered threshold would be given by:

Rl Vn
V= Rl + 12.000n
where Vn

= noise threshold without

Rl connected.

The noise threshold can also be raised to the same degree by
connecting R1 from pin 14 to the supply voltage level. However,
in this case, care should be exercised to insure that the resulting
voltage appearing at pin 14 does not exceed the sync threshold
(approximately 3.9 V).
Noise inversion is achieved as follows: first the composite input
signal is impedance-buffered by the 06 emitter-follower. Then,

FIGURE 6A - NORMAL SYNC
SEPARATION NETWORK
0.05"F
0.1 "F

FIGURE 5

..

4.0

8.0

2.2 k

3.0

?:
w

13

12

2.0 c

330 k

1.0 ~

+18

=>
>-

""c

FIGURE 68 -ALTERNATE OIOOE SYNC
SEPARATION NETWORK

c

;;
w

>-

~

8

NOISE
THRESHOLO

O.l"F

4)0

13

12

100 k

0.2"F
the buffered signal is fed to 010's base through an RC delay line
(21 - 24). Finally the signal appears, inverted and delayed by
approximately 300 ns, at the base of all.
If an interference pulse occurs, with an amplitude enough
above the sync tip level to reach the noise threshold, the pulse will
drive the emitter of 06 below its pre-set level. 07 will conduct,
and charge from the external capacitor connected to pin 14 will
pass through 07, turning on both 08 and 09. When 09 is on,
011's base is grounded, blanking the output of 010's collector.
The video signal with the interfering noise cancelled, emerges
at pin 13. Polarity is inverted, so the sync pulses are positive-going.
Blanking commences before the interference pulse itself emerges
from the delay line, and the blanking action persists for a short
time interval after the end of the· noise pulse, due to energy
stored in 09's junction.
For very long noise pulses, the rate of discharge of the external
capacitor sets the end of the blanking interval. In such a case,
blanking could extend over several horizontal line-sweep periods,
depending on the capacitor value used. The external capacitor is
typically 0.1 ,uF, and this value allows continuous cancellation for
approximately 4 line-sweep intervals.
Under weak signal conditions, high frequency nois~ from thermal

+18 .-+---"",,~--""----'

820 k

An alternate input network is shown in Figure 68, it uses a diode
to separate the sync pulses. In this case the pulses will be clamped
to +0.7 V above ground. As a result, 035 and the transistors following it serve as over·driven amplifiers.
KEYER AND COMPARATOR
The AGC system is internally connected to the video input at
010's emitter. The sync signal at 036 is internally connected to
the AGC sync keyerwhich consists of Q13 and Q14. An externallyderived negative-going fly back pulse (~ 12 V peak-to-peak) is
applied to Q15 for flyback keying the AGe. Since the detected
video output level is sampled only when the sync pulse and the
flyback pulse are coincident, true keyed AGC action occurs.
An AGe comparator is formed by 017 and Q 18. The base of
018 is connected to a fixed reference of 2.6 V. The base of Q 17 is
connected to the emitter of 010, where the video signal has
negative-going sync pulses. The emitters of both devices are supplied

7-52

MC1345P (continued)

from a gated current source, Q19. This current source conducts

FIGURE 7 - ALTERNATE RF AGC OUTPUT
FOR FET OR TUBE TUNER

p:

onlv when Q14 and 015 are simultaneously switched off. To do

this, a positive sync pulse is required on the base of Q13, coincident
with a negative flyback pulse on the base of Q15 (pin 9).

If the video signal at the eminer of 010 increases in amplitude,
the sync pulse becomes more negative. Thus, when 019 is gated

TO
GROUNO
OR
NEGATIVE

4.7k

on, Q1B conducts and turns on both Q20 and Q21, which charge

3

the external AGC filter capacitor connected at pin 8. A typical
value for this capacitor is 2.0 JJF.
If the video signal decreases, Q18 will not conduct. However,
022 will conduct and permit a current of Q.9 mA to flow out of
the capacitor at pin 8. In effect, this "charge dumping" through
022 promotes faster AGe action than could be attained with a
conventional "charge only" system. Coupling between the charging
capacitor and theAGC amplifier is through an emitter follower, 040.

R2

SUPPLY

(-10 VMAX)

sian. As 026 is now conducting, 028 and Q29 will also be turned
on supplying the forward RF AGC voltage to pin 4. Then, when
the A F AGe voltage excursion is complete, 024 will have reached
cutoff and will be unable to oppose the voltage rise at the base of
Q25, thus allowing the IF AGC voltage to begin increasing.
The negative AF AGe action is similar, except that Q30 and 031
are turned off as 028 and 029 are turned on. The RF AGC delay,
or turn-off of 027, can be adjusted by the delay control so that it
occurs at any selected point in the IF AGe range (see Figure 3).
The negative AGC swing may be level-shifted by connecting the
pin 2 and pin 3 resistors to a negative supply instead of to ground.
The value of the pin 3 resistor. R2, for a given voltage swing, can
be determined as:

The MC1345 will operate without flyback pulses if pin 9 is

grounded. However, the AGC noise immunity and aircraft flutter
rejection will be impaired.
THE AGC AMPLIFIER
AGC for the I F is supplied by the emitter of Q25. The RF AGC

is generated in the following way: Given a weak signal condition,
Q26 is barely conducting, while 027 passes the bulk of the current
flowing from the current source, 04. Assume that the base of 027
is biased "on" by the RF AGC delay control connected to pin 6.
The IF AGC will increase if the AGC input voltage from 040
increases. When this latter voltage increases to a predetermined

R2

level (set by the delay control), Q26 turns on. Then, when Q26

turns on, 027 turns off, which also turns 024 off. As Q24 turns
off, it will cancel any further increases at the base of Q25, which
would come from 023 through the 5.0 k!l resistor. The result is
that the IF AGC level is held constant during the RF AGC excur-

= 4000 flV

(See Figure 7 for component connections for negative AGe.)
A" external component values given' are only suggested values;
the final choices will depend on the designer's preferences.

FIGURE 8 -PRINTED CIRCUIT BOARD COMPONENT LAYOUT
OF IF ANO JUNGLE CIRCUIT OF FIGURE 1

CI
C2
C3
C4
C5
C6
C7
CB
C9
CIO
Cll
CI2
CI3
CI4
CI5
CIS
CI7
CI8
L1
T1

RI

See chart of Figure 1
See chart of Figure 1
See chart of Figure 1
0.001 .F
0.002.F
0.002.F
0.002.F
0.002.F
O.I.F
6BpF
18pF
0.001 .F
0.001 .F
2.FI10 V
O.I.F
0.05.F
O.I.F
50 .FI25 V
See Figure 1
See Figure 1

See Operating Characteristics
discussion, Noise Inverter

section
R2
R3
R4
R5
RS
R7
R8
R9
RIO
All
Al2
R13

RI4
R15

RIB
R17
AlB

470 ohms
8200 ohms
220 ohms
22 ohms
3300 ohms

3900 ohms
5 kilohm potentiometer
10 kilohms

4700 ohms
4700 ohms
2 kilohm potentiometer
50 ohms
2200 ohms
330 kilohms
18 kilohms
2200 ohms
4700 ohms

*See Noise Inverter Section
(part can be omitted).

7-53

I

MC1345P (continued)

FIGURE 9 - PRINTED CI RCUIT BOARD

(Scale'" 1: 1 )

7-54

MC1349P

~~___________________I_F_A_M_P_L_I_F_IE_R~

IF AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

MONOLITHIC IF AMPLIFIER
· .. an integrated circuit featuring wide range AGC for use as an
I F amplifier in radio and television applications over the temperature
range 0 to +7 DoC.
•

Power Gain -

60 dB
56 dB
61 dB
59 dB

typ
typ
typ
typ

at 45
at 58
at 45
at 58

MHz
MHz
MHz
MHz

(pin
(pin
(pin
(pin

•

AGC Range - 80 dB typ, dc to 45 MHz

•

High Output Impedance

•

Low Reverse Transfer Admittance

3 open)
3 open)
3 bypassed)
3 bypassed)

8

O

(top view)

o

•

15·Volt Operation, Single-Polarity Power Supply

•

Improved Noise Figure versus AGC

PLASTIC PACKAGE
CASE 626

FIGURE 1 - TYPICAL APPLICATION OF MC1349P VIDEO IF AMPLIFIER
and MC1330 LOW-LEVEL VIDEO DETECTOR CIRCUIT
+18 Vdc

VID~~V[ v..J
-AIvvw
--]

AUXILIARY
OUTPUT

t------------e14 v - - - - .

PRIMARY VIDEO
AND SOUND OUTPUT

3.9 k7.7

MC1330

rv]

56 pF

+---+-.... AFT OUTPUT
3.9 k

5.1 k

T1

AGC

_fs'

.J
Fl.,. ~ D
.

~

1

,~__

-...

TURNS"""

3

TURNS

3"'

r 1--.l
i6

l

(""""'=l---. 3"'

I
#10

10
TURNS

I

L_
16

All windings #22 AWG tinned nylon
L1 wound with :26 AWG tinned nylon
acetate wire tuned with Coilcraft #61
acptate wire tuned by distorting winding.
slugs, size 10·32. or equivalent.
*See Note 1 (page 3), and C4. Parts List (page 4) of this specification.
See Packaging Information Section for outline dimensions.

7-55

MC1349P (continued)

MAXIMUM RATINGS

(T A = +250 C unless otherwise noted).

Rating

Value

Unit

Power Supply Voltilge (VCC1)

+18

Vdc

Output Supply Voltage (VCC2)

+18

Vdc

~ VCCI (pin 2)

Vdc

Differential Input Voltage

5.0

Vdc

Power Dissipation (Package Limitation)
Plastic Package
Derate above T A = +250 C

625
5.0

mW
mWflC

o to +70

°c

-65 to +150



=--

o

10

;....-

~

rmal'A~~

,.--: t::::=- V

~

6.0
5.0

"

I-'-

o
30
FREQUENCY (MHz)

50

70

2000

____ L

r---:::::: :-<
"'"<

-

~z

~::
~«

«

400

'"

o

f-A= pin 3 open
B '" pin 3 bypassed to ground

10

20

-......;

~PINI30PEJ

IB

I

~
w

14

5'"

12

u:

10

/

B.O

-

6.0

~

r--.,

> ~~ t:?"

~

70

200

o

100

V

---- --

/

g22

20

10

30
FREQUENCY (MHz)

50

/

0.3

/'" b1-"

0.2

~

O.1

~

N-

o
70

100

•

\

~ -20

'j/

OmA
~ -30

t;

~ -40

45 MHz RS = 50 U

"-

\

z -50

~~

;;:

C!I

\

-60

40

-BO
4.0

50

7-59

+0.1 rnA

\ '\

45 MHz RS = 1.1 kU

4.5

5.0

5.5

6.0
6.5
VAGC (Vdc)

'-

7.0

~

~

IAGC = -0.1 mA",\
-10

-~

ffi"/

20
30
GAIN REDUCTION (dB)

«

0.4 ~

//

fi 0.0 I~

\

0.5 ~
z

b2y

c

~

EE

/

-70
10

100

V

=>
~ 0.0 2

4.0

o

70

~0.06

l-

J /

I

V

5B MHz RS = 50 U

w

'"~

I

5BMHz RS=700U_

50

FIGURE 10 - GAIN REDUCTION

I

---PIN 3 BYPASSED TO GROUND

16

I

0.7

8 0.03
1"::0;

50

30
FREQUENCY (MHz)

I

I

1I 0.6

FIGURE 9 - NOISE FIGURE
20

30
FREQUENCY IMHz)

~ 0.04

~ I'"
t--... ~

I-Iy211A

I

gllr max jGC r

c

-

800

=>,.

mm

I'

«

i'0 "-

c«
!=c

r" gil . AGe

~ 0.05

""'I ~

~'-'

-:.. J-

V

./

J..-" A

E
E

I": ~

c;;:;

20

V

0.07

y21 A

'-r-..,

~ 11200

--

......------ ...-:::: :.-

,..,...-

-7

./

FIGURE B - DIFFERENTIAL OUTPUT ADMITTANCE
(MAXIMUM AGC)

....--Ly2IB

f-ly211 B

~]"

.........-

V

10

100

FIGURE 7 - SINGLE-ENDED FORWARD
TRANSFER ADMITTANCE

1600

3.0
2.0
1.0

20

~

~

V

« 4.0

~gllminAGC

~

Z

,.
c

~

'/

.....-

\
I\V

oS 7.0

V

bl1 min AGe

lI-

c

E

/

oS

bill minlAGC
I
I
I
bl1 max AGe

B. 0

+0.2 rnA
7.5

B.O

~~_____________S_O_U_N_D__IF_A_M__P_L_IF_IE_R__~

MC1350P

MONOLITHIC IF AMPLIFIER

IF AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

... an integrated circuit featuring wide range AGC for use as an IF
amplifier in radio and TV over the temperature range a to +75 0 C.
The MC1352 is similar in design but has a keyed-AGC amplifier as an
integral part of the same chip.
8

O

• Power Gain - 50 dB typ at 45 MHz,
- 48 dB typ at 58 MHz
• AGC Range - 60 d8 min, dc to 45 MHz
•

(top view)

o

Nearly Constant Input and Output Admittance Over the Entire
AGC Range

• Y21 Constant (-3.0 dB) to 90 MHz

-«

•

Low Reverse Transfer Admittance

•

12-Volt Operation, Single-Polarity Power Supply

1.0 J.1mho typ

PLASTIC PACKAGE

CASE 626

FIGURE 1 - TYPICAL MC1350 VIDEO IF AMPLIFIER
and MC133D LOW-LEVEL VIDEO DETECTOR CIRCUIT

0.002 pF

470

220

+18 Vdc

3.3 k

AUXILIARY

VID~80V[ -;;: --]

OUTPUT

68 pF

t-------eIOV

".J Ivvw
- ---

rv ]

PRIMARY VIDEO
AND SOUND OUTPUT

77
Mel330

3.9k

t - - - t - - A F T OUTPUT

3.9 k

AGe

~J

3"

q~Plr'
TURNS~
TURNS

All windings =30 AWG tinned nylon
acetate wire tuned with Arnold Type
TH slugs.

See Packaging Information Section for outline dimensions.

7-60

4

r 1J
!:1L..r·
i6

TURNS

16

L 1 wound with .::-26 AWG tinned nylon
aCE'tatewiretuned by distorting winding.

MC1350P (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating

Symbol

Value

Power Supply Voltage

V+

+18

Vdc

Output Supply Voltage

Vl, V8

+18

Vdc

AGC Supply Voltage

Unit

VAGC

V+

Vdc

Differential Input Voltage

Yin

5.0

Vdc

Power Dissipation (Package Limitation)

Po
625
5.0

mW
mW/oC

Oto +75

°c

Plastic Package
Derate above 250 C
Operating Temperature Range

TA

ELECTRICAL CHARACTERISTICS (V+ = +12 Vdc; T A = +25 0 C unless otherwise noted)
Symbol

Characteristic
AGC Range, 45 MHz (5.0 V to 7.0 V)(Figure 1)

I
I

Typ

Max

Unit

60

68

-

dB

-

48
50
58
62

-

-

20
8.0

-

dB

Ap

Power Gain (Pin 5 grounded via a 5.1 krl resistor)

f = 58 MHz, BW = 4.5 MHz
f = 45 MHz, BW = 4.5 MHz
f = 10.7 MHz, BW = 350 kHz
f =455 kHz, BW = 20 kHz
Maximum Differential Voltage Swing
OdB AGC
-30 dB AGC

Min

See Figure 5

46

-

See Figure 6

-

Va

-

Output Stage Current (Pins 1 and 8)

-

11 + 18

Total Supply Current (Pins 1, 2 and 8)

5.6

Power Dissipation

-

Po

mA

14

17

mAde

168

204

mW

IS

DESIGN PARAMETERS, Typical Values (V+

V p. p

=+12 Vdc, T A =+25 0 C unless otherwise noted)
Frequency

Symbol

Parameter

Single-Ended Input Admittance

10.7 MHz

455 kHz

45 MHz

58 MHz

Unit

mmhos
"mhos

911
bll

0.31
0.022

0.36
0.50

0.39
2.30

0.5
2.75

A9ll
Abll

-

-

60
0

-

922
b22

4.0
3.0

4.4
110

30
390

60
510

"mhos

Output Admittance Variations with AGC
(0 to 60 dB)

A922
Ab22

-

-

4.0
90

-

"mhos

Reverse Transfer Admittance (Magnitude)

I Y12)

«1.0

«1.0

«1.0

«1.0

"mho

(Y211

< Y21
< Y21

160
-5.0
-3.0

160
-20
-18

200
-80
-69

180
-105
-90

mmhos
degrees
degrees

Single-Ended Input Capacitance

Cin

7.2

7.2

7.4

7.6

pF

Differential Output Capacitance

Co

1.2

1.2

1.3

1.6

pF

I nput Admittance Variations with AGC
(Oto 60dB)
Differential Output Admittance

Forward Transfer Admittance
Magnitude
Angle (0 dB AGC)
Angle (-30 dB AGC)

FIGURE 2 - TYPICAL GAIN REDUCTION
(Figures 5 and 6)
IAGC=O.lmA-

~
z
0
;=

'":::>

~

20

FIGURE 3 - NOISE FIGURE
IFigure 5)

:--....

40

z

;;;: 60

'"

22
20

'" "

'"
w
'"
:::>

4.0

B.O

5.0

./ ./
//

18

58MHzU

~

'"u:w
'"0
z

IAGC =10.2 m;:-"'"

80

-

16
14
12

B.O
7.0

VAGC IV)

L"2

10
8.0

V

o

~

~

45MHz

~ ;'

10

20
GAIN REDUCTION (dB)

7-61

30

40

MC1350P (continued)

GENERAL OPERATING INFORMATION

FIGURE 4 - CIRCUIT SCHEMATIC
AGCAMPLIFIER SECTION

The input amplifiers (01 and 02) operate at constant emitter
currents so that input impedance remains independent of AGC
action. Input .signals may be applied single'ended or differentially
(for ac) with'identical results. Terminals 4 and 6 may be driven
from a transformer. but a de path from either terminal to ground
is not permitted.
AGe action occurs as a result of an increasing voltage on the
base of 04 and 05 ca"sing these transistors to conduct more
heavily thereby shunting signal current from the interstage amplifiers 03 and 06. The output amplifiers are supplied from an active
current source to maintain constant quiescent bias thereby holding
output admittance nearly constant. Collector voltage for the output· amplifier must be supplied through a center-tapped tuning
coil to Pins 1 and 8. The 12-volt supply (V+) at Pin 2 may be used
for tl:lis purpose, but output admittance remains more nearly con·
stant if a separate 15-volt supply (V++) is used, because the base
voltage on the output amplifier varies with AGC bias.

1

G.,

FIGURE 5 - POWER GAIN, AGC and NOISE FIGURE TEST CIRCUIT
(45 MHz and 58 MHz)

INPUT AMPLIFIER SECTION

BIAS SUPPLIES

OUTPUT AMPLIFIER SECTION

FIGURE 6 - POWER GAIN and AGC TEST CIRCUIT
(455 kHz and 10.7 MHz)

-=

O.OOI"F O.OOI"F
·Connect to ground for maximum power gain test.
All power-supply chokes {lpl. are serf-resonate at
input frequency. lp ~ 20 kn
See Figure 10 for frequency response curve.

Note 1. Primary: 120 "H (center-tapped)
au = 140 at 455 kHz
Primary: Secondary turns ratio~13
Note 2. Primary: 6.0 "H
Primary winding = 24 turns #36 AWG (close-wound on
1/4" dia. form)
Core = Arnold Type TH or equiv.
Secondary winding = 1-1/2 turns #36 AWG, 1/4" dia.
(wound over center-tap)

~ 1 @45 MHz = 7 114 Turns on a 1/4" coil ~orm.
@58 MHz = 6 Turns on a 1/4" coil form
T1 Primary Winding =18 Tumson a 114" coil form, center-tapped
Secondary Winding =2 Turns centered over Primary Winding@45 MHz
= 1 Turn@58MHz
Slug =Arnold TH Material 1/2" long

Ll
Tl
Cl
Cz

45 MHz

58 MHz

n , 100
0.4"H
1.3-3.4"H I n ~100@2"H
50-160pF
8 - 60 pF

n ~ 100
0.3"H
1.2-3.8"H I n ~100@2"H
8-60pF
3 - 35 pF

I

I

Frequency
Component 455 kHz

Cl
C2
C3
C4
C5
C6
C7
L1
T1

7-62

10_7 MHz
80-450 pF
5.0-80 pF
0.05"F
0.001 "F
0.05"F
0.05"F
O.OOI,..F
36pF
0.051'F
0.05,..F
0.05,..F
iJ.05"F
4.6"H
Note 1
Note 2

-

MC1350P (continued)

TYPICAL CHARACTERISTICS
(v+

= 12 V. TA = +250 C)
FIGURE 8 - FORWARD TRANSFER ADMITTANCE

FIGURE 7 - SINGLE-ENDED INPUT ADMITTANCE
5.0

II

4.0

'1'1

E

500

blll/

3.0

,g
-: 2.0

1.0

10

--

. / I-""

.-'

,...-

1/

7

IJ

II

I Ir -,==::~

400

17

1:\

a 300
E

ffi

£ 200

./

-120

100

iY21 :

-160

V
~ I.---

o
20

30

40

70

50

3.0

2.0

1.0

100

5.0

b2t.-

0.6

,g
~

0.4

V

V

/

I---

V

V
./
I.--- l 20

50

30

-200

100

FIGURE 10 - TEST CI RCUIT RESPDNSE CURVE
(45 and 58 MHz)

V

N
N

10

20

N

~

I)

(Single.end;d output I
admittance exhibits
twice these values.)

0.2

10

e

FREQUENCY (MHz)

1.0

~



1=
0>

4.: "

o

;i 3.0
;::

i
C

'""-I--

VJ ,2V

I

2.0
1.0

10

20

30

40

50

60

70

80

GAIN REDUCTION (dB)

For additional Information see "A Hlgh·Performance Monolithic
IF Amplifier Incorporating Electronic Gain Control", by W. R.
Davis and J. e. Solomon, I EEE Journal on Solid State Circuits,

December 1968.

7-63

,-----f

TV SOUND CIRCUIT

~~_____________SO__U_N_D_I_F_A_M_P_L_I_F_IE_R__~

MC1351

TV SOUND CIRCUIT

WIDE-BAND FM-AMPLIFIER; LIMITER, DETECTOR,
AND AUDIO AMPLIFIER INTEGRATED CIRCUIT

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

· .. designed for IF limiting, detection, audio preamplifier and driver
for the sound portion of a TV receiver.
• Excellent Limiting with 80IlV(rms) Input Signal typ
• Large Output-Voltage Swing - to 3.5 V(rms) typ
• Higb I F Voltage Gain - 65 dB typ
• Zener Power-Supply Regulation Built-In
• Short-Circuit Protection
• A Coincidence Discriminator that Requires Only One RLC Phase
Shift Network
• Preamplifier to Drive a Single External-Transistor Class-A AudioOutput Stage

P SUFFIX
PLASTIC PACKAGE
CASE 605

TO·116

PO SUFFIX
PLASTIC PACKAGE
CASE 647

BLOCK DIAGRAM

1----,

r- -

.......---~ PHASE SHIFT

MULTIPLIER

L.:.XT~A~

--,

LOW PASS
FILTER
(EXTERNALI

900 iC'cf>

L - _ .....J

CIRCUIT SCHEMATIC

11o-----------__*-----------~~~._--~~._----~----~--_.~~_._+------~--._--~14
9.1 k

10

250

5.0 k

12
See Packaging Information Section for outline dimensions.

7-64

MC1351 (continued)

MAXIMUM RATINGS (TA = +25 0 unless otherwise noted)
Rating

Symbol

Value

Power Supply Voltage

V+

+16

Vde

Input Voltage

Vin

0.7

V(rms)

Po
1I8JA

625
5.0

mW
mW/oC

Unit

Power Dissipation (Package Limitation)

Plastic Packages
Derate above +25 0 C
Operating Temperature Range

TA

o to +75

°c

Storage Temperature Range

T stg

-65 to +150

DC

Maximum Ratings as defined

In

M I L·S-19500. Appendix A.

ELECTRICAL CHARACTERISTICS (V+ = 12 Vdc, TA = +25 0 C, f= 4.5 MHz, Deviation =±25 kHz unless otherwise noted)
Characteristic
Input Voltage (-3.0 dB Limiting)
AM Rejection (Vin - 20 mV(rms), AM = 30%) (See Note 1)
AMR = 20 I V OFM ( I = 4.5 MHz, Deviation = ±25 kHz, OL
og V OAM
f = 5.5 MHz, Deviation = ±50 kHz, 0L

Symbol

Min

Typ

Max

Unit

VL

-

80

160

!,\,\rmsl

-

45

-

45

-

THO

-

1.0

-

%

Vo(max)

-

3.5

-

V(rms)

0.35

0.50
0.80

-

dB

k!l.

AMR

= 24
= 30

Total Harmonic Distortion (QL = 24) (See Note 1)

dB

(7.5 kHz Deviation)
Maximum Undistorted Audio Output Voltage (Pin 10) (See Note I)
(Audio Gain Adjusted Externally) (0 = 24)
Recovered Audio (Pin 2) ISee Note 1)
If = 4.5 MHz, Deviation = ±25 kHz, 0L = 24)
If = 5.5 MHz, Deviation = ±50 kHz, OL = 30)

Vlrms)

VA

-

-

Audio Preamplifier Open Loop Gain

AVp

-

25

I F Voltage Gain

AVIF

-

65

Rin

9.0

-

Cin

-

6.0

-

pF

VReg

-

11.6

-

Vde

ID

-

31

-

mAde

Po

-

300

375

mW

Parallel Input Resistance
Parallel I nput Capacitance

Nominal Zener Voltage liZ - 5.0 mAde)
Power Supply Current II Z

= 5.0 mAde)

Power Dissipation liZ = 5.0 mAde)
Note 1: QL is loaded circuit

dB

Q.

FIGURE 1 - TEST CIRCUIT IV+ = +12 Vdc, TA = +2S0C)

10

3300 pF

12 VReg

--'1

i

r-----if-(
10

100 k

MC1351P, PQ

50

1.0 k

I-=

o.1!'F

47k

IO.

L = 45-80 ~H, (Coil·Craft 01030 or equiv.)
0= 60 nom at 2.5 MHz
Rdc = 3.8 ohms

7-65

01 /l F

10 k

MC1351 (continued)

TYPICAL CHARACTERISTICS
FIGURE 3 - DETECTED AUDIO OUTPUT versus INPUT
LEVEL@f=5.5MHz.±50kHzDEVIATION

FIGURE 2 - DETECTED AUDIO OUTPUT versus INPUT
LEVEL@f=4.5 MHz. ±25 kHz DEVIATION
1000

1000

II

II

I

,
10

10

100
Vin. INPUT VOLTAGE

10

10 k

1.0 k

100

10

FIGURE 5 - DETECTOR "s" CURVE @f = 5.5 MHz.
BW= 220 kHz.Q = 30

FIGURE 4 - DETECTOR "s" CURVE @ f = 4.5 MHz.
BW = 200 kHz. 0 = 24

FIGURE 6 - IF VOLTAGE GAIN versus FREQUENCY

~

z

;;:

to
W

+70

0

+60
iii' +5 0

70

°v

to

50

~

40

~

FIGURE 7 - AM REJECTION

90

_e--

«

~

t;
w

~

+4 O
+30

" +2a
«

t"-

V-

I--'

",'

a

" +10
«

20

10
1.0

r- 1- j..-V

os

t--

..l

o

>

10 k

1.0 k

Vin. INPUT VOLTAGE I~V[rms))

I~V[rms))

0
2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

11

-1 0
100

12

f. FREQUENCY (MHz)

1.0 k

10 k

Vin.INPUT VOLTAGE I~V[rms])

7-66

100 k

MC1351 (continued)

FIGURE B - 4.5 MHz TYPICAL APPLICATION
V+

140 Vd,

Po = 0.5 Wat 1.5 kHz Deviation
Po = 3.5 Wat 25 kHz Deviation
0.01

INPUT

---I

~F

liB]

10:1

.....- - - . ! I - - _ +240 V
lN4004 OR

eaulv

MJE340 OR EaUIV
1.0 k

50 pF

0.1 " "

I

0.01

.F

",FIl~;"
I ~5

27k

.,

47k

k

VOLUME
CONTROL

7-67

30

R =Vee - 11.6
0.031

"

MC1352
MC1353

TV VIDEO IF AMPLIFIER
""
_ _ _ _ _- - - - - J

TV VIDEO IF AMPLIFIER WITH
AGC AND KEVER CIRCUIT

TV VIDEO IF AMPLIFIER WITH AGC
AND KEVER CIRCUIT

MONOLITHIC SILICON
INTEGRATED CIRCUIT

· .. a monolithic I F amplifier with a complete gated wide-range AGC
system for use as the 1st and 2nd I F stages and AGC keyer and
amplifier in color or monochrome TV receivers.

•

Power Gain at 45 MHz, 52 dB typ

•

Extremely Low Reverse-Transfer Admittance

•

Nearly Constant Input and Output Admittance Over AGC Range

-«

P SUFFIX

1.0 j.lmho typ

PLASTIC PACKAGE
CASE 605

TO-Tl6

• Single-Polarity Power-Supply Operation
•

High-Gain Gated AGC System for Either Positive or NegativeGoing Video Signals

• Control Signal Available for Delayed AGC of Tuner
PQSUFFIX

• Two Complementary Devices - MC1352 and MC1353Offer Opposite Tuner AGC Polarity

PLASTIC PACKAGE
CASE 647

FIGURE 1 - TYPICAL VIDEO IF AMPLIFIER APPLICATION
r----1--------~----e~

12 Vdc
RF AGC
TO TUNER
-Cl
INDte2}

r

v+
IB Vdc
l.9 k

IBV[:i\:]
220

2k

10V
l.l k

-

---

l.9 k

AUXILIARY
t----1I----1-.. VIOEO
OUTPUT

4.7

MClllO

k

PRIMARY VIDEO
AND
SOUNO OUTPUT

'Jv]

33 pF

AFT
3.9 k

FLYBACK WINDING

OUTPUT

-B.O v PULSE
LI

-3"

M-.l
rYVV'\

~ltI

t

10

TURNS

See Packaging Information Section for outline dimensions.

7-68

16

Wound with 126 AWG tinned nylon
acetate wire tuned by distorting
winding.

MC1352, MC1353(continued)

MAXIMUM RATINGS (Voltages relerenced to pin 4, ground; T A = +25 0 C unless otherwise noted)
Value

Unit

Power Supply (Pin 11)

+18

Vdc

Output Supply (Pins 7 and 8)

+18

Vdc

10

V p. p

+6.0

Vdc

Rating

Signal Input Voltage (Pin 1 or 2, other pin ac grounded)
AGC Input Voltage (Pin 6 or 10, other pin ac grounded)
Gatirig Voltage, Pin 5
Power Dissipation
Derate above T A

+10, -20

Vdc

625
5.0

mW
mW/oC

o to +70

°c
°c

= +25 0 C

Operating Temperature Range
Storage Temperature Range
Maximum Ratings as defined

-55 to +150
In

M I L-S-19500, Appendix A.

ELECTRICAL CHARACTERISTICS (V+ :::: +12 Vdc, Voltages referenced to pm 4 , groun d T'A=+

un ess ot erwise note d)

Min

Typ

Max

Unit

-

75

-

dB

1= 35 MHz or 45 MHz

-

52

-

1= 58 MHz

-

50

-

-

16.8
8.4

-

Maximum

-

-

Minimum

-

I F Gain Change Over RF·AGC Range

-

7.0
0.2
10

-

dB

Output Stage Current 117 + 18)

-

5.7

-

mAdc

Total Supply Current 117 + 18 + 111)

-

27

31

mAdc

Total Power Dissipation

-

325

370

mW

Characteristic
AGC Range
Power Gain

dB

Maximum Differential Output Voltage Swing

OdS AGC
-30 dB AGC

-

Vp.p

Voltage Range lor RF·AGC at Pin 12

Vdc

DESIGN PARAMETERS, TYPICAL VALUES (V+ = 12 Vdc, TA = +25 0 C unless otherwise noted)
Parameters
Single-Ended Input Admittance

Input Admittance Variations with AGC (0 to 60 dB)
Differential Output Admittance

Output Admittance Variations with AGC

Reverse Transfer Admittance

(a to

60 dB)

Symbol

1=35MHz

1=45 MHz

f=58MHz

Unit

g11

0.70
2.80

1.1
3.75

mmhos

bll

0.55
2.25

C!.911
C!.bll

50
0

60

-

!J.mhos

a

g22
b22

20
430

40
570

75
780

.umhos

C!.922
C!.b 22

3.0
80

4.0
100

-

,u.mhos

IY121

«1.0

«1.0

«1.0

J..Lmho

IY121

260
-73
-52

240
-100

210
-135
-96

mmhos
degrees

Forward Transfer Admittance

Magnitude
Angle (Q dB AGC)
Angle (-30 dB AGC)

LY21
LY21

-72

Single-Ended Input Capacitance

9.5

10

10.5

pF

Differential Output Capacitance

2.0

2.0

2.5

pF

7-69

I

MC1352, MC1353(continued)

FIGURE 2 - CIRCUIT SCHEMATIC

KEVER AND AGe AMPLIFIER
RF·AGC Amplifier and

Keying Section

r - -- -- - - - - - -- ~

i

I
I

I

I
I
I

I

I

I
I

I
I
I

-ci!(---:4:-

c1'!{-- ~

14

:

I I
: I

16k

k: :

7.5

6.2 k

4k

I I
Keyer

I

01

--t:?-2

-<5rl ~

5

r:

.

--I;'~3;a -~

I

I

Sk

""'PH::
6.2 k

(MCI353.
Connection!

I I

01

Pulse

I

I

9

I I

I
I
I

I

I

Delav Section

iAGCs.o;;g.c.;C.i- - -"F":AGcFii"te;) - - - - - - - - - - - - - - --------,

.........- - . . . .

Connectionl 03

100

2k

<

200

.......

K~f--c
RF·AGC Line

100

12

To
Tuner

I
I

I

16 k

15 k

10.9 k

I

Video
and Reference

I

;f:

C3

I

I

~~

DC Inputs

I

300

I

I
I

300

I
I

I

L _____________

L __________ •______

I

13

~·~G~D~a'0'~g..:.

_______ _______ ...1

IF AMPLIFIER
AGe Controlled Section

~--

- - - --- --- - -- - --1

I

Bias Section

~

II
t'

I
I

'--_T--------__'FL..,.~c:~.:.C...,
I

, ,
I

I

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r----+

I

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~~7 ~

y2k: y I

I....--r;;:

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d

IF

..

';1'

5k

I

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..

I I

I

470

11 V+ OCSupply Voltage

S~p~yO~~~~e
9

I

,--

I I

- 4 - - .....

I:

~,

I

,

I

12.1k: :

7,?

1

r.J:......

-V-

"l

;

I
5.6k

-..,
IFOulput
c,_<>

~--~~

I

':

I

4.2k

470

IF Output Section

750: :
I I

470 I

e70

r- - - - - - - - - - -- - -"1

I:
~

----+--f-.....--,-'! -:--......---,~2'5k
t. .

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t

I
I

--- ------ ---"1

is
y

JlJi=~:~J1£~

l.S6k

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2 0 0 :

i

~--~_r--------------------+------~----~-------+~~---------+--~__,
L ___________________
3.4 _
I
~-----------------

.!

~

7-70

_____

I

I

~

MC1352, MC1353 (continued)

FIGURE 3 - POWER GAIN, AGC AND NOISE TEST CIRCUIT

VC, is maintained across the external capacitor, C2, for a particular
video level and dc reference setting. The voltage VC. is the result

v'
12Vdc

of the charge delivered through 01 and the charge drained by 01.

The charge delivered occurs during the time of the gating pulse,
and its magnitude is determined by the amplitude of the video
signal relative to the de reference level. The voltage Vc is delivered

0.001

r'

via the I F·AGC amplifier and applied to the variable gain stage of
the IF signal amplifier and is also applied to the RF·AGC amplifier,

where it is compared to the fixed A F-AGC delay voltage reference
by the differential amplifier, 02 and 03. The following stages
amplify the output signal of either 02 for MC1352, or 03 for

=

MC1353 and shift the dc levels causing the RF·AGC voltage to
vary (positive-going for MC1352 or negative-going for MC13531.

AGCINPUT

~

-8.0 V

AGe

IH'T-;:::~~=t0':;-~>--!lUNER
DELAY

FIGURE 4 - TEST CIRCUIT RESPONSE CURVE
(45 and 58 MHzl

v
TUNER AGe OUTPUT

C2
AH chokes (lpl areselt·rewnale
alinputfrequency.lp>ZOkU.
SeeFigure41orResponseCuive

11

"

,,/"
~
35and45MHl
O.4I1H
a,.loo
T1

1.J-3.4IJH

'"

"\

':oJ,

"

~

""""-

58MHz

O.3I'H

1l;;o100@2"H

0>100

1.2-3.S"H

Scale: 1 MHz/em

O;;'100@lZ/lH

40-80pF
12-45pF

48-100pF

C2

/

I

"""

8-60pF

LI and T1:126AWG Tinned NvlonAcetateWire
Ll @350r45MHz:

1·1I4Turns~na

1/4" co.1 form

@58MHz;:6Turnsonal/4"coiltorm
TI

PrimaryWinding~

18 Turnsona 1/4"coilform

SecondarvWinding~2TurnsWoundEyenlvoverPrimarv

WLndingior350r45MHzandi
Turn for S8 MHz
Slug~Arnold

THMatenall/2"long

GENERAL OPERATING INFORMATION

The input amplifiers (04 and 051 operate at constant emitter
currents so that input impedance remains independent of AGC
action. Input signals may be applied single-ended or differentially
(for ac). Terminals 1 and 2 may be driven from a transformer, but
a dc path from either terminal to ground is not permitted.
AGC action occurs as a result of an increasing voltage on the
base of 06 and Q7 causing those transistors to conduct more heavily
thereby shunting signal current from the interstage amplifiers 08
and 09. The output amplifiers are fed from an active current
source to maintain constant quiescent bias thereby holding output
admittance nearly constant.

Each device, MC1352 and MC1353, consists of an AGC section

and an I F signal amplifier (Figure 2) subdivided into different functions as indicated by the illustration.
A gating pulse, a reference level, and a composite video signal
are required for proper operation of the AGC section. Either
positive or negative-going video may be used; necessary connections
and signal levels are shown in Figure 1. The essential difference is
that the video is fed into Pin 10 and the AGC reference level is

applied to Pin 6 for a video signal with positive-going sync while
the input connections are reversed for negative-going sync.
The action of the gating section is such that the proper voltage,

FIGURE 5 - TYPICAL AGC APPLICATION CHART

NOTES:

1. The 12-V supply must have a low ac impedance to prevent lowfrequency instability in the RF·AGC loop. This can be achieved
by a 12·V zener diode and a large decoupling capacitor (5 "FI.

2. Choices of C1, C2 and C3 depend somewhat on the set designers'
preference concerning AGC stability versus AGe recovery speed.
Typical values are Cl

= 0.1 "F, C2 = 0.25 /IF, C3 = 10 /IF.

3. To set a fixed IF-AGC operating point (e.g., for receiver align·
ment) connect a 22 kn resistor from pin 9 to pin 11 to give minimum gain, then bias pin 14 to give the correct operating point
using a 200 kn variable resistor to ground.
4. Although the unit will normally be operating with a very high

power gain, the pin configuration has been carefully chosen so
that shielding between input and output terminals will not
normally be necessary even when a standard socket is used.

7-71

Video
Polarity
Negative·
Going
Syne.

Positive·
Going
Sync.

Pin 6
Voltage

Pin 10
Voltage

5.5JuC

Pin 5
RI (!II

Adj. 1.0-4.0 Vde
0

2.0 - 0

--

Adj. 1.0-8.0 Vde
Nom 4.5 V

Nom 2.0 V

4.:Jl

3.9 k

I

MC1352, MC1353 (continued)

TYPICAL CHARACTERISTICS

(V+ = +12 Vdc, TA = +25 0 C unless otherwise noted)

FIGURE 6 - SINGLE·ENDED INPUT ADMITTANCE
5.0

1/
/

4.0

bl1

Q

-g

FIGURE 7 - DIFFERENTIAL OUTPUT ADMITTANCE
1.0

3.0

I'

0.8

2.0

...... V

1.0

/

~

0.4

gil

20

30

40

0.2

50

70

100

----

!-10

20

30

-g
.5
w

c

II

r-.,

z

r'lt-,\

'" 200
«
!"

~

-60

«
f-

-100
-120

1\

~

-40

~ 6.0

80 'il

:::>

t::

c:~ 7.0 \

20

'\1\

300 r-ly211

>

~

f-

~

:::>

160
-180

o

1.0

2.0

5.0

20

10

-200
100

50

c:

~

-140

\

100

5.0

\

~ 4.0

f-

""'-"...........

~ 3.0

«

V++=14V

-

~ 2.0
~ 1.0

i5

o

o

10

~

'"
~

z

>
~

;..-;;

~

>

>

>

'"

~

'"
..:

~

:-..:

..:

TUNER

ACe

;.."";

c

t;

.......

:::>

~

20

~

40

'"
"-

60
80

r--.

1\

~

6,u

~
w

'"
'"«

'"

5.0 ':;

'">f-

'">=
g

3.0

"-.,

TUNER
AGC

I

C

w

~

U

U

U

n

u

'"'-'

'""-

'"

u

I I

~t;;;

~; ~

80

70

I I 1i

80
. U;

~-i;::!

o.U LU

5.0

0
If GAIN REDUCTiON

20

:---.

4.0

"

Z
;;' 40

:::>

1
w
r-.IF GAIN REDUCTION 1.0 z

u

l

'"

f-

60
80 -

:::>

U

60

--+---::-'~-r\-:;;+~-~-M\:;;....,\r-~-M\-:;;"""\f--+---11 :~

z

f-

U

50

-I

'"

I

H II
TUNEA
AGC

2.0 «

*Tuner AGe Delay -

100

U

7.0

4.0

r-.,

40

FIGURE 11- MC1353AGCCHARACTERISTICS

8.0

I

30

20

GAIN REDUCTION (dB)

FIGURE 10 - MC1352 AGC CHARACTERISTICS

'> > >
'"
~"' "u; u;

V++~ 12 V

>=

fREQUENCY (MHz)

I

100

70

8.0

Gain
~f-.. Ly21 @30dB
Reduction
I _1' ~
Ly21 @Max Gain

Q

50

,/

,/

FIGURE 9 - DIFFERENTIAL OUTPUT VOLTAGE

FIGURE B - FORWARD TRANSFER ADMITTANCE

400

40

fREQUENCY (MHz)

-

-

-

922

FREQUENCY (MHz)

500

/"

.......

,/

V

10

/

N
N

,/

~

0.6

~

V

~

b22

Q

-g
.5

........ V

~

V
/

/

V

.5

V

(SINGLE.E1NOEO OJTPUT
ADMITTANCE EXHIBITS
TWICE THESE VALUES)

oTluner ArC

3.0
"

oer

3.5

AGC INPUT VOLTAGE (VOLTS)

4.0

4.5

5.0

6.0

6.5

7.0

AGC INPUT VOLTAGE (VOLTS)

7-72

~
~

'"

1--..

Ir5.5

~

'"~

TUNER 2.0 ~
«
AGC

100

u

«
'"

7.5

8.0

8.5

1.0 '"
~
:::>
f-

MC1352, MC1353{continued)

TYPICAL CHARACTERISTICS (continued)
(v+ " +12 Vdc, T A " +25 0 C unless otherwise notedl

FIGURE 12 - TYPICAL NOISE FIGURE

v V

22
20

/

f=58MHY

18

~
'"
'"=>to

14

'"C;

12

u:
00

16

z

10

8.0

L
/ '/

', /

..---V

---

V

/
/

/"
f=35 MHzor45MHZ
I

See Test Circuit of Fjlgure 3.

6.0
10

20

30

40

AGC GAIN REDUCTION Id8)

I
For additional information see "A High·Performance Monolithic IF Amplifier
Incorporating Electronic Gain Control", by W. R. Davis and J. E. Solomon, IEEE
Journal on Solid State Circuits, December 1968.

7-73

I

~__________________FM__I_F_A_M_P_L_I_F_IE_R__~

MC1355

LIMITING FM
IF AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

BALANCED MONOLITHIC FOUR-STAGE
HIGH-GAIN FM/IF AMPLIFIER

· .. designed for use with Foster·Seeley discriminator or ratio detector
in high quality FM systems.
P SUFFIX

•

High AM Rejection (60 dB typ)

•

Wide Range of Supply Voltages (8 to 18 Vdc)

•

Low Distortion (0.5% typ)

PLASTIC PACKAGE
CASE 605
TO-116

PQ SUFFIX
PLASTIC PACKAGE
CASE 647

FIGURE 1 - TYPICAL FM·IF APPLICATION

TYPICAL PERFORMANCE

r

l

lo_01J.lF

100

-=

100
AUDIO

2.5

10.5iJH
1 pH
r----, pF r----,

5k

I

I

OUTPUT

I

33 PF

50pF

3.9k
50pF

When using the device as a non-saturating limiter the load must be chosen to prevent voltage saturation of the output stage. The
load impedance can be calculated from:
2(V+ -5.3)
R L ~ --5.-0- kilohms

See Packaging I nformation Section for outline dimensions.

7-74

MC1355 (continued)

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted)
Value

Unit

Output Voltage (pins 7 & 8)

40

Vdc

Supply Current to pin 11

20

mA

I nput Signal Voltage (single-ended)

5_0

Vp-p

Rating

Input Signal Voltage (differentiall

10

Vp-p

625
5_0

mW
mW/oC

o to +75

°c
°c

Power Dissipation (package limitation I
Derate above T A

= +250 C

Operating Temperature Range (Ambient)
Storage Temperature Range

-65 to +150

Maximum Ratings as defined in MI L·S·1950Q, Appendix A.

ELECTRICAL CHARACTERISTICS (V+ = 15 Vdc, f = 10_7 MHz,
T A = +25 0 C, RS = 820 ohms unless otherwise noted)
Characteristic

Min

Typ

Max

Power Supply Voltage Range

8.0

15

18

Vdc

Total Circuit Current

16

-

mAde

4_2

-

mA

Device Dissipation

-

125

-

mW

Internal Zener Voltage

-

5.2

-

Vdc

Total Output Stage Current

Input Signal for 3 dB Limiting
Output Current Swing
AM Rejection (10 mv to 1.0v (rms)
input, F M @ 100%, AM @ 80%, Foster Seeley detectorl

Units

-

175

250

ItV(rms)

3.5

4.2

5.0

mAp-p

-

60

-

dB

1.4

V(rms)

Maximum AM Signal before Breakup (FM @ 100%, AM @80%)

-

-

Admittance Parameters

-

120 + j320
jO.6
8 + j5.9

-

.umhos
Itmho

-

15 + j230

-

mhos
.umhos

Y11
Y12
Y21
Y22

-

FIGURE 2 - CI RCUIT SCHEMATIC

llyV+
7

500

500

500

14
IN

PUTK

500

OU TPUTS

500

~ r' 5.2 V

7k

7k

7k

'-I

'-I

'-l
,.-1

,.-1

500

3.4k

2k

7k

6k

8

>LK

f4;>Y f4;>)J r. ~ )~

;»

~

500

6k

6 ~.

500

'-I

~
6k

6k

P; n52,3,6,9, 12, and 13are not internally connected

10

but should be grounded for maximum stability.

FEEDBACK

500

,."
6k

4k

140

~,

4k

~,

4
GNO

5

7-75

MC1355 (continued)

TYPICAL CHARACTERISTICS
FIGURE 3 - TEST CIRCUIT

01

r--1~--"r-----~--~--~R4~--~---e0~~~~T
!

:}
r--

R5

R5

01
RFIi'NPUT
C2
R2

5 kilohms

12 kilohms

I
I

I
I

V+ =15 Vdc
Cl 50 pF
01 Small Signal Germanium Diode
C2 O.OI"F
{IN542orequivi
Specifications are' given for a Foster-Seeley discriminator. ImT1 10.1 MHz Foster-Seeley Discriminator.
proved AM rejection at low signal levels can be obtained with a
Primary Impedance = 3.9 k.
ratio
detector.
Peak-Io-Peak Separation = 600 kHz
For optimum circuit stability it is important to ground pins 2,

R1 820 ohms
R2 50 ohms
R3 100 ohms

AS

MHz
:I110.7
FILTER

L __ -.J

R3

R4

:
I

3,4,6,9, 12, and 13.
FIGURE 4 - AM REJECTION TEST BLOCK DIAGRAM

RF
{I0.7 MHz!

_L

HP 10514A
MIXER
DR EOUIV

Rr----

~rf- I

230·A
BOOTON
POWER AMPL.
DR EOUIV

I-

TEST CI RCUIT
(Figure 3)

HP 340014
RMS
METER
DR EOUIV

51 k

MODULATION
1 kHz

FM
GENERATOR

10 k

V DIODE BIAS

FIGURE 5 - LIMITING
1000

~

:;;-

FIGURE 6 - AM REJECTION
70

t--J+='.5V~C

1

VL1 5vJc

(Use Test Circuit of Figure 3)

800

.,.....

~

~ 600

l

BO%AM I
1..1
(Use Test Set-Up of Figure 3)

75 kHz Deviation

.sw

.1

60 1--100% FM (75 kHz)
50

o

>

~

I
II

t-

~ 400

::>

o
o

::>
<[

.L

o .:::::::.
0.01

-

~
0.1

. . . . 1-/

0

25 kHz Deviation

J

C 200

40

~
~

V

/

z

o

:;

V

0

L
1.0

3.0 5.0 10

100

10
0.01

1000

SIGNAL INPUT VOLTAGE (mVlrms])

0.1

1.0

3.0 5.0 10

SIGNAL INPUT VOLTAGE (mV[rms])

7-76

100

1000

MC1355 (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE B - SIGNAL-TO-NOISE RATIO SIGNAL

FIGURE 7 - OUTPUT DISTORTION
100

10

B.O

~

z

J V+=15Vdc 1.,1_

\
\

100r ('7f kHr Devi'lion)1

:s
0

;::
~ 60

0

~

6.0

~

....
~
....
:::>

w

(Use Test Circuit of Figure 3)

0

i5

4.0

0

2.0

,/

'"
i5
z
6 40

1\
\

~
'\

'"0;

20

,/

./
/' . /

~
«
z

/

--

0.1

1.0

3.05.0 10

100

2j kH( 0TATlr

L

J

r-

1

(Use Test Circuit of Figure 3)

J

V/

1 L
1 L 1

0.01

1000

1
1

71 kH~ DE~IATlbN r--

I

/'

oV

o
0.01

1 1 1
1 1 1

V+= 15Vdc

a; BO

1.0

0.1

3.0 5.0 10

100

1
1
1000

SIGNAL INPUT VOLTAGE (mV(rmsl)

SIGNAL INPUT VOLTAGE (mV(rmsll

FIGURE 9 - TOTAL SUPPLY CURRENT
20
lB

V

16
~

..s....

12

~

B.O

~

6.0

'"
13
!t

,..- V

14

~

10

V

(Use Test Circuit of Figure 3)

V
V

./'"

4.0
2.0

o
B.O

10

12

14

16

lB

SUPPLY VOLTAGE (VOLTS)

•
7-77

I

MC1357

~~_____________S_O_U_N_D__IF_A_M__P_L_IF_IE_R__~

IF AMPLIFIER
AND QUADRATURE
DETECTOR
MONOLITHIC SILICON
INTEGRATED CIRCUIT

MONOLITHIC TV SOUND IF OR FM IF AMPLIFIER
WITH QUADRATURE DETECTOR

NOVEMBER 1970 - DS 9164 Rl

• A Direct Replacement for the ULN2111A

P SUFFIX
PLASTIC PACKAGE
CASE 646
TO-116

• Greatly Simplified FM Demodulator Alignment

• Excellent Performance at V+ = 8.0 Vdc
PO SUFFIX
PLASTIC PACKAGE
CASE 647

FIGURE 1 - TV TYPICAL APPLICATION CIRCUIT

+22 V

820

+

~r"_F ~
____

__1-__LvlVV__

1-_3i·0~P_F,
MC131S

0.1 pF

13i-'-__--L________.l---L__.......,

--it-'-,-_-0-4-1

R2

INPUT

51

100 k

~3
I
I
I
I

'1-=

0.005 pF I

'I

1_

I

I

(Opllonall
Typical Performance:
2 Watts Output
2% Distortion

250 pV Sensitivity (3 d8 Lim.)

Cl=120pF
L1 = 14pH
Rl=20krl
Q = 30

See Packaging Information Section for outline dimensions.

7-78

-=

0.1 pF

MC1357 (continued)

MAXIMUM RATINGS (TA; +25 0 C unless otherwise noted)
Value

Unit

Power Supply Voltage

16

Vdc

Input Voltage (Pin 41

3.5

Vp

Power Dissipation (Package Limitation)

625

mW

5.0

mWflC

o to +75

°c
°c

Rating

Plastic Packages
Derate above T A = +25 0 C

Operating Temperature Range (Ambient I

-65 to +150

Storage Temperature Range
Maximum Ratings as defined in MIL-S-19500, Appendix A.

ELECTRICAL CHARACTERISTICS (V+ = 12 Vdc, TA = +25 0 C unless otherwise noted)
Pin

Min

Typ

Max

Units

13

10

-

12
15

19
21

rnA

Amplifier Input Reference Voltage

6

-

Vdc

2

-

1.45

Detector Input Reference Voltage

3.65

-

Vdc

Amplifier High Level Output Voltage

10

1.25

1.45

1.65

Vdc

Amplifier Low Level Output Voltage

9

-

0.145

0.2

Vdc

1

-

3.7
5.4

-

Vdc

-

5.0

kn

70

-

2.7

.-

pF

60

-

ohms

200

-

8.8

-

ohms
kn

Characteristic

V+ = 8 V
V+ = 12 V

Drain Current

V+= 8 V
V+ = 12 V

Detector Output Voltage
Amplifier Input Resistance

4

Amplifier Input Capacitance

4

Detector Input Resistance

12

Detector I nput Capacitance

12

Amplifier Output Resistance

10

-

Detector Output Resistance

1

-

De-Emphasis Resistance

14

-

= 1.0 kHz, Source
Peak Separation = 150 kHz)

DYNAMIC CHARACTERISTICS (FM Modulation Freq.
(V+ = 12 Vdc fo

= 4 5 MHz

Llf = ±25 kHz

Characteristics

Amplifier Voltage Gain (Vin ~ 50 IlV [rmsll
AM Rejection' (Vin = 10 mV[rmsll
Input limiting Threshold Voltage
Recovered Audio Output Voltage (V' n = 10 mV[rmsll
Output Distortion (Vin = 10 mV[rmsll

(V+

Resistance

pF

kn

= 50 ohms, T A = +25 0 C for all tests.)

Pin

Min

Typ

Max

Units

10
1
4
1
1

-

60

-

36
250
0.72

-

dB
dB
IlV(rmsl
V(rmsl

3

-

%

-

dB
dB
IlV (rmsl
V(rmsl

-

-

= 12 Vdc, fo = 5.5 MHz, Llf; ±50 kHz, Peak Separation = 260 kHz)
-

Amplifier Voltage Gain (Vin ~ 50 IlV[rmsll
AM Rejection' (Vin = 10 mV[rmsll

10
1

Input Limiting Threshold Voltage

4

-

Recovered Audio Output Voltage (Vin - 10 mV[rmsll
Output Distortion (Vin = 10 mV[rmsll

1
1

-

(V+

11

=B.O Vdc, fO = 10.7 MHz

-

60
40
250
1.2
5

-

-

%

Llf =± 75 kHz, Peak Separation = 550 kHz)

Amplifier Voltage Gain (Vin ~ 50 IlV[rmsll
AM Rejection' (Vin = 10 mV[rmsl)
Input Limiting Threshold Voltage
Recovered Audio Output Voltage (Vin = 10 mV[rmsll
Output Distortion (Vin = 10 mV[rmsl)

10
1
4
1
1

-

-

53
37
600
0.30
1.4

-

dB
dB
IlV (rmsl
V(rmsl

-

%

-

dB
dB
IlV(rmsl
V(rms)

-

(V+ = 12 Vdc, fo = 10.7 MHz, Llf = ±75 kHz, Peak Separation; 550 kHz)
Amplifier Voltage Gain (Vin ~ 50 IlV[rmsll
AM Rejection' (Vin - 10 mV[rmsl)
Input Limiting Threshold Voltage
Recovered Audio Output Voltage (Vin - 10 mV[rmsll
Output Distortion (Vin = 10 mV[rmsl)

10
1
4
1
1

·100% FM, 30% AM Modulation

7-79

-

-

-

53
45
600
O.4B
1.4

-

-

%

MC1357 (continued)

TYPICAL CHARACTERISTICS
(V+ = 12 V, TA = +25 0 C unless otherwise noted)
(fo = 4.5 MHz)
(Use Test Circuit of Figure 13)

(fa = 5.5 MHz)

FIGURE 2 - AM REJECTION
60

II 1111

",

0

\

0

...

60

-

REIF SllGJAlINVJi
(Pin fO)

REF SIGNAL INPUT
(Pin 10)

2:

~EF SIGNAL

o

i'"

INPUT
(Pin 9)

0

/
100% FM, 30% AM

Ifr ~.~ ~~zill

0

10
0.05

0.1

1/

........ ,

"

40

0

0.2

0.5

1.0

2.0

20

n

10
0.05

50

IT

0.1

0.5

0.2

5.0

10

20

50

1.3

O. 9

§

O. 8

w

~

O. 7

REF SIGNAL INPUT (PIN 9)

5 ]0.6

1.2

REF SIGNAL INPUT (PIN 9)

1.1

'"
~

1.0

>

0.9

I

0

~>-

o'='

o~O.5
=>w

0.8

/

=>

~ ~ 0.4

t::

~ o. 3

o

0.2

0
0

/

>-~

t;;

2.0

FIGURE 5 - DETECTED AUDIO OUTPUT

FIGURE 4 - DETECTED AUDIO OUTPUT

=>

1.0

INPUT VOLTAGE (mV )rm,))

1.0

1=-

REF SIGNAL
INPUT (PIN 9)

(fl' 515 ~~z:

20

II5.0 IIII10

7

"

100%FM,30%AM

INPUT VOLTAGE (mV(rm,))

>-

'"

II'

7

«

/'

-

....

50

/v

"'-

~

FIGURE 3 - AM REJECTION

«

iil

II IIII

O. 1

8t;;

II IIII

o
0.1

/

=> 0.6

±25kHz DEVIATION

0.04

0.7

i5

0.4

4.0

1.0

10

0

40

/

0.5

±50 kHz DEVIATION

II ITIT

I

0.4
0.3
0.02

TIm

0.1

INPUT VOLTAGE (mV)rm,))

1.0

0.2

10

20

FIGURE 7 - OETECTOR TRANSFER CHARACTERISTIC

FIGURE 6 - DETECTOR TRANSFER CHARACTERISTIC

1458MHl

Jj

2.0

INPUT VOLTAGE (mVlrm,))

[,5.63 MHz

r~

~

&I

II
liiiill ii:.'!

Iii:

4.50 MHz

III

.J

0

5.50 MHz

liiI\\\\!
1111!

24

~-

~

I

n

,J

~5.37

U 4.42 MH7

7-80

MHz

Q

30

MC1357 (continued)

TYPICAL CHARACTERISTICS (continued)
(fo = 10.7 MHz, TA = +25 0 C unless otherwise noted.)
(Use Test Circuit of Figure 13)

FIGURE.9 - AFC VOLTAGE DRIFT

FIGURE 8 - AM REJECTION

(1.0mV INPUT CARRIER@10.7MHzl

50

- 600

-

40

L
;i;

os
z

/,'

30

~
~

.s

~V+-

~

/

~ 100

1'\

~>-

100% FM. 30% AM

40

;j! 20
o

w

~

10

c::J

6.0

i;;

o
0.5

1.0

2.0

5.0

10

20

50

100

200

500

0.D1 0.02

0.05 0.1

INPUT VOLTAGE (mVlrmsll

100

1.04

N

Gl

1.0 1

~

1.00

~

0,99

~

/'

/

~ 0.98

>-

c3

0.97

~
>=

-

~

-

V

C
z

DC LEVEL = 5.36 V@+25 0 C
INPUT CARRIER = 1.0mV-I - v+ = 12 Vdc

6

12 v+

0.96

,,;

20

o~
+30

+50

+70

+90

+110

+130

A IV

0.01

+150 +170

0.02

0.05

'"

~

0.2

0.5

1.0

2.0

5.0

FIGURE 13 - TEST CI RCUIT

FIGURE 12 - DETECTOR TRANSFER CHARACTERISTIC
+1.5

o

0.1

INPUT SIGNAL VOLTAGE (mV)

AMBIENT TEMPERATURE (OC)

0;

"tV!

~'

«

>

-

~:::

40

z

'"in
+10

50 100

20

60

':;

/
-10

10

-'I =25 kHz
Mod 1 =1.0 kHz

w
w

V

0.95
-30

5.0

2.0

I IIII

BO

0

V

/

w

1.0

I IIII

i..--"""'"

/

1.02

0.5

FIGURE 11 - SIGNAL·TO·NOISE RATIO

FIGURE 10 - LIMITING

1.03

0.2

INPUT SIGNAL VOLTAGE ImVlrmsl)

1.05

N

±75 kHz DEVIATION

C
10

:=+

8V+

o

'"

«

'-'

V

60

5

20

I~-

12 v+

~ 200

8V+ "

r/

0

~
400
:;

I

vt

INPUT

+1.0

O"I'F

1

C1

L1

D.l"F

C21scOlllleclediOPII19
unle5sotherwlsenoted,

".

+0.5

w

'"
~
o
>

~

-0,5

>-

"o

OUTPUT

-1.0
-1.5
10.45

2k

10.5

10.55

10.6

10.65

10.7

10.75

10.8

10.B5

10.9

10.95

FREQUENCY (MHz)

7-81

10

MC1357 (continued)

FIGURE 14 - FM RADIO TYPICAL APPLICATION CIRCUIT
-I-12V
O=20@10.7MHz
'L= 1.5-3.0pH
"5 POLE FILTER,
TRW #25579 OR EOUIV

~O.IPF
50pF

AUDIO
OUTPUT

3.3 k
4.7 pF

120 pF
2k

50n
INPUT

0.1 pF

FIGURE 15 - OUTPUT DISTORTION

II II
1\ II II

~EF ~IG~AIL
INPUT
(Pin 10)

Note 1:

f-

Information shown in Figures 15. 16. and 17 was obtained
using the circuit of Figure 14.

Note 2:

f-,

REF SIGNAL
INPUT
(Pin 9)

\

Optional input to the quadrature coil may be from either
pin 9 or pin 10 in the applications shown. Pin 9 has commonly
been used on this type of part to avoid overload with various
tuning techniques. For this reason, pin 9 is used in tests on the

\.

..........

r'\

preceding pages (except as notedl. However, a significant improvement of limiting sensitivity can be obtained using pin 10,

;-...

see Figure 17, and no overload problems have been incurred
with this tuned circuit configuration.

o
30

10

100

300

1000

INPUT SIGNAL VOLTAGE ("Vlrm,])

FIGURE 17 - RECOVERED AUDIO OUTPUT

FIGURE 16 - SIGNAL·TO·NOISE RATIO
0

100 0

II II

11

:;

REF SIGNAL INPUT (Pin 10)

oS

60

W

'"

S
w

'"o
'"
S

'"

°v

1/
I--' V"
V

to

"

C;
0
>
>-

REF SIGNAL INPUT (Pin 9)

V

"

500
400

"
~>

to

Ui

30

§

20
10

30

100

300

1000

a:

-

600

'"

'"0=>

Z

700

s:>=>

o /

900
800

REF SIGNAL INPUT (Pin 10)

200

REF SIGNAL INPUT (Pin 9)

V~

30 0

~

V

100

o
10

30

100

300

INPUT SIGNAL VOLTAGE (pV Irm,])

INPUT SIGNAL VOLTAGE (pVlrm,])

7-82

1000

MC1357 (continued)

FIGURE 18 - CIRCUIT SCHEMATIC

INPUT SIGNAL VOLTAGE'(mV)

L

13 (

12

2

J

3k

..-1

8.8 k

'"

~r

r-

~~
0-

lk

-----t

<>

1k

lk

500

v

2k

500

""

2k

500

~~

~

......

~

8k

14

~

2.5 k

,r

4k

4:

~r

H
~r1 ~r1

1

200

r
~r

J200
200

200

~

~

450
~

2.5 k

(

50

10

11

7-83

5k

'F

a...--J

"'

MC1358

SOUND IF AMPLIFIER

'----------------'

IF AMPLIFIER, LIMITER,
FM DETECTOR, AUDIO DRIVER,
ELECTRONIC ATTENUATOR

TV SOUND IF AMPLIFIER

MONOLITHIC SILICON
INTEGRATED CIRCUIT

... a versatile monolithic device incorporating IF limiting, detection,
electronic attenuation, audio amplifier, and audio driver capabil ities.

•

Direct Replacement for the CA3065

•

Differential Peak Detector Requiring a Single Tuned Circuit

•

Electronic Attenuator Replaces Conventional ac Volume
Control - Range> 60 dB

•

Excellent AM Rejection

•

High Stability

•

Low Harmonic Distortion

@

PSUFFIX
PLASTIC PACKAGE
CASE 646
TO·116

4.5 and 5.5 MHz

• Audio Drive Capability - 6.0 mAp·p
•

Minimum Undesirable Output Signal

@

Maximum Attenuation

PO SUFFIX
PLASTIC PACKAGE
CASE 647

FIGURE I - TYPICAL TV APPLICATION CIRCUIT

v+ =24 V
RS
390

1I2W
50k"
DC
VOLUME

V+-l1

RS = [j]j3J In}

CONTROL

SOUND
TRANSFORMER 2

4·~-M-H-Z-Cl~..l...r--,

.lO.Q1~F

MC1358P,PQ

INPUT

IDE.EMPHAsls

L2

12

0.05.F

"L1 = 16.H NOMINAL.
QIUNLOADED}>50

_
I

-

10

13

U"

O.33J,1F

1 .".
25 k{

Cl and l2 component values are to be
selected atthe dtscretion of the designer

See Packaging Information Section for outline dimensions.

7-84

LY-J1.7W

r.~+--~"_+270

68pF

12 PF

11 [7(13.2"
40:1

TONE
CONTROL

V

MC1358 (continued)

MAXIMUM RATINGS (TA

~ +25 0 C unless otherwise noted I

Rating

Value

Unit

±3.0

Vdc

50

mA

625
5.0

mW
mW/oC

-20 to +75

°c
°c

Input Signal Voltage (Pins 1 and 21
Power Supply Current
Power Dissipation (Package Limitation)

Plastic Packages
Derate above T A "" +2SoC
Operating Temperature Range (Ambient)

-65 to +150

Storage Temperature Range
Maximum Ratings as defined in MIL-S'19500, Appendix A.

ELECTRICAL CHARACTERISTICS (v+

=24 Vdc. TA = +25 0 C unless otherwise notedl
Pin

Min

TVD

Max

Unit

Regulated Voltage

5

10.3

11

12.2

Vdc

DC Supply Current (V+ = 9 Vdc, R!; = 01

5

10

16

24

mA

Quiescent Output Voltage

12

-

5.1

-

Vdc

Characteristic

DYNAMIC CHARACTERISTICS (v+

~ 24 Vdc, T A ~ +25 0 C unless otherwise notedl

Characteristic

Min

Typ

Max

Unit

IF AMPLIFIER AND DETECTOR
fa = 4 5 MHz AI = -+25 kHz
AM Rejection' (Vin = 10 mV [rmsl I

40

51

-

dB

Input Limiting Threshold Voltage

-

200

400

I'V(rmsl

0.5

0.70

-

V(rmsl

Output Distortion (Vin = 10 mV [rmsl I
z
'0= 55MH z, Af-±50kH

-

0.4

2.0

%

AM Rejection' (Vin = 10 mV [rmsl I

40

53

-

dB

Input Limiting Threshold Voltage

-

200

400

I'V(rmsl

0.5

0.91

-

V(rmsl

-

0.9

-

%

-

17
4.0

-

kD.
pF

-

3.25
3.6

-

7.5
250

-

-

-

kD.
D.

60

-

-

dB

-

0.07

1.0

mV

Voltage Gain
(Vin = 0.1 V(rmsl. f = 400 Hz)

17.5

20

-

dB

Total Harmonic Distortion
(Va = 2.0 V(rms), f = 400 Hz)

-

2.0

-

%

2.0

3.0

-

V(,ms)

Recovered Audio Output Voltage (V;n = 10 mV[rmsl I

Recovered Audio Output Voltage (Vin = 10 mV [,msl I
Output Distortion (Vin = 10 mV [rmsl I
Input Impedance Components (f = 4.5 MHz, measurement between pins 1 and 21
Parallel I "put Resistance
Parallel Input Capacitance

-

Output I mpedance Components (f = 4.5 MHz, measurement between pin 9 and GN 01
Parallel Output Resistance

Parallel Output Capacitance

-

kD.
pF

Output Resistance, Detector

Pin 7
Pin B
ATTENUATOR
Volume Reduction Range (See Figu,e 81
(de Volume Control = 00 I
Maximum Undesirable Signal (See Note 1)

(de Volume Control

~

001

AUOIO AMPLIFIER

Output Voltage
(THO = 5%, f = 400 Hz)
Input Resistance (f = 400 Hz)

-

70

-

kD.

Output Resistance (f = 400 Hz)

-

270

-

D.

·100% F M, 30% AM Modulation.
Note 1. Undesirable signal is measured at pin 8 when volume control is set for minimum output.

7-85

I

Me 1358(continued)

TYPICAL CHARACTERISTICS
(v+

= 24

V, T A

= +25 0 C unless otherwise noted I

(fo = 4.5 MHz)

(fo

5.5 MHz)

=

FIGURE 3 - AM REJECTION

FIGURE 2 - AM REJECTION

60

0

50

0

,.....
0

./

'"

0
100% FM, 30% AM

0

0

20

0

V

100% FM. 30% AM

II

V
10
0.05

0.1

0.2

0.5

1.0

2.0

5.0

10

20

10
0.05

50

0.1

0.5

0.2

2.0

5.0

10

20

50

INPUT VO LTAGE {mV[rms])

INPUT VOLTAGE {mV[rmsl)

FIGURE 5 - DETECTED AUDIO OUTPUT

FIGURE 4 - DETECTED AUDIO OUTPUT

1000

1000

80 0

80 0

:;

J

:;

s

E

~ 60 0

~ 60 0

II

~

o

~

1.0

40 0

/

'"

/

~

o

±25 kHz DEVIATION

~ 40 0
=>

/

±50 kHz DEVIATION

II

'" 200

20 0

o
0.05

0.1

0.2

0.5

1.0

2.0

5.0

10

20

50

0.05

0.2

0.1

0.5

1.0

2.0

5.0

10

20

50

INPUT VOLTAGE {mV[rms]1

INPUT VOLTAGE {mV[rms])

FIGURE 7 -IF AMPLIFIER AND DETECTOR THO

FIGURE 6 -IF AMPLIFIER AND DETECTOR THO

2. 5

~

o

2.0 H++ift-----+++I+H+f--+-+-J-+++ill--I---j+

n

1.5 H+tIH--+++-I+f+tI---+-+-l-+++*--I-i1-+

5

~

o

to

C

'-'

;;;
o

~ 1.0

Modf=lkHz

:;;
=

'"

1/

o

t:;

0
0
0

V

3.0

f =400 Hz

C

)"

u

;;;

V

o

~ 2. 0

I

I)

'"
0:

/

~

g 1.0

0

f-

0
1.0

5.0

2.0

10

20

50

100

o

200

500

1000

DC VOLUME CONTROL (k OHMSI

0.05

0.1

0.2

0.5

1.0

2.0

90
0

'" 30
20
10
0
0.1

0.5

0.2

1.0

2.0

5.0

Pins6,7,8,10,11,12,lJ,14noconnection.

10

FREQUENCY (MHz)

FIGURE 13-AUDIO VOLTAGE GAIN,
AUDIO THO TEST Cf RCUIT

FIGURE 12 - AM REJECTION, DETECTED AUDIO,
THO, ATTENUATION TEST CIRCUIT

~I,E-,-,-,--<>--1

51

UNIVERTER

(BOONTON
TYPE207H
OR eQUIVALENT)
AM·FM
GENERATOR
(BOONTON
TYPE202H
OR eQUIVALENT!

ll"

0"1

O.l",F

IO-IS~H

Olullloaded);;.50

5.0

FIGURE 11 -IF FREQUENCY RESPONSE TEST CIRCUIT

FIGURE 10 -IF FREQUENCY RESPONSE
10 0

~

3.0

OUTPUT VOL TAGE (VOLTS [rms!)

Pins!l, 12,13, 14nocomuction.

7-87

MC1358(continued)

FIGURE 14 - CIRCUIT SCHEMATIC

BUFFER

ELECTRONIC ATTENUATQR

REGULATED POWER SUPPLY

4

DC VOLUME
- - - - -6

r------ - --- ---- -- --- ------------- -- ---

CONTROL
7
------

DE·EMPHASIS

I

I
I

,

"

I

I
I
GNO

,
I
I

1-----------r---

I

I
I

t----+OIC
SOUND
INPUT,

IF~
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

,r---- ---- ---- ------- - ----------18k
,,
"
IF AMPLIFIER LIMITER

_

I
I

I"
I

I
I

,I

I

150

I
I

'Ok

,
1390

_

'-AUDIO

14

':'

INPUT

TONE

13

CONTROL

I

I

AUDIO
OUTPUT

AUDIO AMPLIFIER

7-88

12

I
......I

I
L _______________ _

DETECTOR

I ______ ...J
L

,-----f

\ .......__A_U_T_O_M_A_T_I_C_F_R_E_Q_U_E_N_C_y_C_O_N_T_R_O_L-----J

MC1364

AUTOMATIC

FREQUENCY CONTROL
MONOLITHIC TV AUTOMATIC
FREQUENCY CONTROL

•

MONOLITHIC SILICON
INTEGRATED CIRCUIT

High Gain Amplifier - 18 mV Input for Full Output

•

Direct Replacement for the CA3064

•

Also Available in the 14·Lead Dual In·Line Package

c::::::]
I

~-

~
GSUFFIX
CASE 686

METAL PACKAGE

PSUFFIX
CASE 646
ITO·1161
PLASTIC PACKAGE

FIGURE 1 - TYPICAL APPLICATION CIRCUIT

10k
3W
r---t-~r-~~-----------~~---------------.+140V

L1
68pF

82
pF

1k

10

111

3

FRQM3rdVlOEOIF

141

AFC
OUTPUTS

151

AMPLIFIER

1121

4~·~~UMTHz ----llf---f-O--i
O.OOl.F

MC1364

18)

1k

191

See page 3 01 this specification for
Coil Data (L 1. L2, L3).

1141

8

The number without parenthesis is the pin number for
the metal package. The number in parenlhesis is the pin
number for the plastic package.

Metal Package, Pin 9 - no connection
Plastic Package,Pins6.7.10.11,13-no connection

See Packaging Information Section for outlino dimensions.

7-89

•

MC1364 ( continued)

MAXIMUM RATINGS (TA

=

+25 0 C unless otherwise noted, see Note 11

Rating

MC1364G

MC1364P

Input Signal Voltage (Pin 7 to 81

+2.0, -10

+2.0, -10

Vdc

Output Collector Voltage (Pins 2 and 8)

20

20

Volts

Power Dissipation (Package Limitation)
Derate above T A = +250 C

680
5.6

625
5.0

mW
mW/oC

-40 to +85

o to +75

-65 to +150

-65 to +125

°c
°c

Operating Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC

=

+30 Vdc, TA = +25 0 C, see Test Circuit

Unit

Figure 4 unless otherwise noted. 1

01

Min

Typ

Max

Unit

Total Device Dissipation

-

140

-

mW

Total Supply Current

-

12

-

mA

Currant Drain, Total
(Reduce V CC so that VI 0 = 10,5 Vdc)

4.0

6.5

9.5

mA

Zener Regulating Voltage

10.9

11.8

12.8

V

1.0

2.0

4.0

mA

5.0

6.6

8.0

V

-1.0

0

+1.0

V

Characteristic

Quiescent Current to Pin 2
Quiescent Voltage a! Pin 4 or Pin 5

Output Offset Voltage (Pin 4 to Pin 5)

DESIGN PARAMETERS, TYPICAL VALUES (VCC

=

+30 Vdc, RS

= 1.5 k, 1 = 45.75 MHzl
Symbol

Typ

Unit

Input Admittance

Vll

0.4 + jl

mmho

Reverse Transfer Admittance

V12

0+ i3.4

,umho

Forward Transfer Admittance

V21

110 + j140

mmhos

V22

0.02 + jl

mmho

Parameter

Output Admittance (Pin 2)

Note 1:

Pm numbers used

In

the above tables are for the metal package, Case 686. For correspondIng pm numbers for the plastic

package, Case 646. see the Test Circuit, Figure 4 .
Symbols conform to JEDEC Engineering Bulletin No._1 when applicable.

TYPICAL CHARACTERISTICS
(See Test Circuit of Figure 2)
FIGURE 3 - TYPICAL WIDE BAND
DYNAMIC CHARACTERISTICS

FIGURE 2 - TYPICAL NARROW BAND
DYNAMIC CHARACTERISTICS

__ ____

::I~ ~

16
Yin = 18 mVIRMSI
14

~
0

2:
w

-

12

t--- t-10

f--

~in5(8)

'"«

':; 8.0
0
>
I- 6.0
1[
l-

=> 4.0

0

2.0

o
45.71

--

45.72

in

Vpin4(5)

~/ '

//
V

45.73

"'"

':;

I

12

o

2:
w

10

':;

8.0

«
'"
o

>

~

6.0

Vrin5181

k:

l-

.........

=>

o

r--

45.74
45.75
45.76
45.77
INPUT FREOUENCY IMHzl

45.78

+-__-+lv_in_=_1_8~f_VI_R_M_Slbi__-4r-__4-__~

4. 0
2. 0
0
43.75

45.79

I
(

Pin 415i""-,

"'- ::::=

/

""

/

~Pin4151

44.75

Pin 5 (8l,./

45.75
INPUT FREQUENCY 1M Hz)

7-90

46.75

47.75

MC1364 (continued)

COIL DATA FOR DISCRIMINATOR WINDINGS
FOR FIGURES 1 AND 4

FIGURE 4 - TEST CIRCUIT
RS = 1.5 k

L1 - OiscriminatorPrimary: 3·1 16turns; AWG #20 enamel·covered
wire - close-wound. at bottom of coil form. I nductance of

L 1 = 0.165I'H; Q o = 120 at fa = 45.75 MHz.
Start winding at Terminal #6; finish at Terminal #1.
Notes below.

68
pF

See

L2 - Tertiary Windings: 2-1/6 turns; AWG #20 enamel·covered
wire - close-wound over bottom end of L 1.
Start winding at Terminal #3; finish at Terminal #4. See
Notes below.
L3 - Discriminator Secondary: 3-1/2 turns; AWG #20 enamelcovered wire, center-tapped, space wound at bottom of coil
form.

(4)

1k

50

(9)

Start winding at Terminal #2; finish at Terminal #5, connect
center tap to Terminal #7. See Notes below.

(5)

MCI364

O.OOl"F ~

I~~OI

AFC
OUTPUTS

Notes: 1. Coil Forms; Cylindrical; -0.30" Oia. Max.
2. Tuning Core: 0.250" Oia. x 0.37" Length.

1k
L -_ _- ,_ _ _- ' (8)

O.OOl"F

(14) 8

RS

VCC -11.8

=----o:ii'i'2

Material: Carbinal J or equivalent.

J

3. Coil Form Base: See drawing below.
4. End of coil nearest terminal board to be designated the
winding start end.
5. Mount the coils 3/4" apart. center to center.

to';8"j

0 hms

The number without parenthesis is the pin number for

the metal package. The number in parenthesis is the pin
number for the plastic package.
Metal Package, Pin 9 - no connection
Plastic Package, Pins 6,7,10, t 1,13 - no connection

(Boltomview
01 co;1 Io-----------3.15 i n . - - - - - - - - - - - - I

7-92

,--1

MC1370P

'l~

____

C_H_R_O_M_A
__S_U_B_CA
__
R_R_IE_R_S_Y_S_T_E_M__~

TELEVISION CHROMA
SUBCARRIER
REGENERATOR

TELEVISION CHROMA
SUBCARRIER REGENERATOR

MONOLITHIC SILICON
INTEGRATED CIRCUIT
· .. a monolithic device designed for solid·state television receivers,
provides a gated voltage controlled oscillator, phase· locked loop and
dc hue control.

• Sensitive Voltage Controlled 3.58 MHz Crystal Oscillator
•

High·Gain Automatic Phase Control (APC) Loop

•

Wide· Range dc Control of Regenerated Subcarrier Phase

• Synchronous Automatic Chroma Control (ACC) Detector
•

Internal Shunt Regulated Power Supply

•

Internal Gating for Color Burst

• Complements MC1371P Color IF Amplifier
•

PLASTIC PACKAGE
CASE 648

Direct Replacement for the CA3070

FIGURE 1 - MC1370P SYSTEM BLOCK DIAGRAM

15

16

11

12

--------,I

HUE CONTROL

I

A~J~T

I
I
13D--L--r------l

HORIZ
KEY 4
PULSE

r --------l

SHUNT
RGLR AND
BIAS CKT

I

L ________ _

7-93

I
I

I

I

---~
10

See Packaging Information Section for outline dimensions.

I

2}

./"'---l-O 3

OSCILLATOR
OUTPUTS

•

MC1370P (continued)

MAXIMUM RATINGS (TA

= +250 e unless otherwise noted)
Rating

Maximum Supply Voltage
(through 470 ohms to pin 10)
Power Dissipation (Package Limitation)
Plastic Package
Derate above T A = +2SoC

ELECTRICAL CHARACTERISTICS (Vee

= +24 Vdc, TA = +25 0 e

Characteristic

Unit

30

Vdc

625
5.0

mW
mW/oC

o to +75

°e

-65 to +150

°c

Operating Temperature Range (Ambient)

Storage Temperature Range

Value

unless otherwise noted.)

Min

TVp

Max

Unit

STATIC CHARACTERISTICS (See Test Circuit ~f Figure 2, S1, S2 and S3 in position 1 unless otherwise noted.)
Power Supply Current (52 in position 2)

-

27

-

mA

Regulator Voltage (pin 10)

11

11.8

12.9

Vdc

-

35

-

mVdc

Oscillator Current (pins 2 and 3, 52 in position 2)

4.1

6.5

7.5

mA

APe Detector Current (pin 11 or pin 12)

1.0

1.5

1.8

mA

ACe Detector Current (pin 15 or pin 16)

1.0

1.5

1.8

mA

APe Detector Leakage Current (pin 11 or 12,52 in position 31

-

40

IlA

ACe Detector Leakage Current (pin 15 or 16, 52 in position 31

-

-

-375

-40

+375

-300

-50

+300

-330

-10

+330

Load Regulation (pin 10) (Vee from +21 V to +27 V)

APe Detector Balance (voltage between pins 11 and 12)
ACe Detector Balance (voltage between pins 15 and 161
Oscillator Control Balance (voltage between pins 7 and 8, 82 in
position 3, 83 in position 2)

30

IlA
mVdc
mVdc

mVdc

Oscillator Gate Leakage (pin 2 and pin 3)

-

-

2.0

IlA

Voltage (pin 1)

-

100
7.7
6.5
6.5
2.8

300
8.2
7.0
7.0

mVdc
Vdc

(pin 13)
(pin 14)
(pin 6)

82
81
82
82
82

in position 2
and 82 in position 2
in position 2
in position 2
in position 2

DYNAMIC CHARACTERISTICS (Eburst

7.2

6.0
6.0

-

-

= 200 mVp·p at pin 13, see test circuit of Figure 3 and note for setup.)
-

1.6
1.6

-

Vp-p

-

10

-

Hz/mV

-

+400
-600

-

Hz

-

0.02

-

-

5.0

-

mV/Deg

1.4

-

mVdc/mVp-p

Oscillator Noise Bandwidth (fNNI

-

150

-

Hz

APC Filter Damping Coefficient (K)

-

0.5

-

-

Input Impedance (pin 13)
(pin 14)
(pin 6)

-

2.1
2.1
2.2

-

kn

Oscillator Output Voltage

(pin 2,81 in position 1)
(pin 3, 81 in position 3)

Oscillator Control Sensitivity (11)

(Above fa
(Below fa

Oscillator Pull-in Range

= 3.579545 MHz)
= 3.579545 MHz)

APC Loop Static Phase Error (with oscillator free-running
frequency offset)
APC Detector Sensitivity

b,tl

ACC Detector Sensitivity (ACC output level change for input
burst level change)

8ymbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-94

Deg/Hz

MC1370P (continued)

FIGURE 2 - STATIC CHARACTERISTICS TEST CIRCUIT
8'
21 Vto21 V
1k

~~
.,..

lk

0.01

~F

2k

~

2k

•-4:-

O.OlIJF

~~

0.01 jJF

O.OljJF

1

r---<
15

16

14

13

12

11

'70
2W

10

1

~r

91

'022k.,..

38k
MC1370P

,'1 U
2

5

6

7

8

4
I--

0.01 pF

OoOI"FJ

100 k

;; O.Ol/-lF
---<
12k

1
.2

510

0,01 J.lF

J,

J

2

S2 j3

J,

I .....SI

FIGURE 3 - DYNAMIC CHARACTERISTICS TEST CIRCUIT
NORMAL

1

r-I

NTSC BAR
SIGNAL (-YI

-=-

I

LINE
PULSE

I

Rl
20kJ

AND
DELAY

12pF

S2

I

O.05}.tF

62>

RJ. rF

100

1

15

14

13

2

Oo;;pF

1.5k

0005 "F

11

10

1:

6~r 1305795.5 MHz)
f-----lD

XTAl

I
t7

f8

65pf

J

GATE

INPUT

-=

The Set-up Procedure for Dynamic Characteristics Test
Circuit

The signal source is an NTSC color bar generator (minus lurni-

ina nee or Y content) applied through ,an adjustable 3.58 MHz
attenuator.

56 _
-

180

43k

f

12

51

4

3

36k

.J,.
NOTE:

1

lOpF 470

MC1370P

180

HU E

0005 "F

22kf
16

1.0 k

3!O, OIPF

±

62k

470
2W

22k
+O"F

I
270k

APe ADJUST

±65 PF

62k

100

OUTPUT

!, SI

~
20k -

1.aM

-=

62k

eleCTOR

2

50PFt
2.7k

689
±50 PF

ADJUST

PULSE
GENERATOR

'" I

•

1.2M

ACC

OUTPUT

SETUP

2

The generator horizontal output is used to trigger a

pulse generator set to give an output pulse of +4.0 volts, 4.5 p.s
wide, at a repetition rate of 15.734 kHz. The pulse delay is adjusted

to center the pulse during the burst of the color signal (compare
gated portion of output at pin 2 or 3 with burst pulse of signal).
With Sl set to position 2 and 52 set to position 2, the oscillator is
adjusted to 3.579545 MHz by R2. R 1 is adjusted to produce zero
offset between pins 15 and 16. When S2 is set to position 1, the
oscillator should synchronize to the incoming signal.

7-95

•

•

S

n
.....
w
~

o

FIGURE 4 - TYPICAL CHROMA APPLICATIONS CIRCUIT
(MC1370P. MC1371. MC1328 AND MPSU101

n-O

~IOlt~~

33

10 k ADJUST

·f

Vee = +24 V

m,u;v )

1

l

P
200 F

47 pF
2.7k

47PFT

470

~

MPS Ul0

0.01 /-IF

~
INPUT
CHROMA •

."

I

i

hfl=
pF 1 4
T2
220

1 +T

=

~4t5b6¢1

001
IlF

220pF

Vcc= +24 V

lk

0.05 ""

200"H

I

1c-

~10k

10 k

MPSU10
orequiv

Lk II~

200 pH

+24 V

-...J

::J

.+250 Vdc

33
.

LO.~l j.LF

I'~

1O.k

::J

!:!".

::: PICTURE
III
TUBE

2·7kf

I

CO
Ol

360 pF

180

l+

20 k •
APC
ADJUST

~

1.2M

~

20 k
ACC
AOJUST
30pF

~;

62k

~

t--~2k

O.05pF

t

lO.05IlF

IO.05.~

SWITCH 51

16

POSITION 2 = SET·UP

22k

15¢ 14¢13

lOJ.lF
470 25 V

62k

1.5k
47 pH

O.05,uF

r

22k

~1t141~,~

_0.05

11

100

MC1310P
1¢ 2¢ 3¢ 4

61

FERRITE
, BEAD
•

lk

43k

250 k

CONT~g~ ~t=;---~----<
HORIZ KEY PULSE

+4V.4.5fJS
INPUT

36

~

0.01 pF

- - - - - ) ' f - I_ _...J
O.EIIiF

1.5k

(OF

1

~J

1

MPS UID
orequiv

200 pH

r«J
3.3k ~100

~100

~100

250

9y

POSITION 1 • NORMAL

36k

15/lH

~

l"F
12

6.BJ.lH

J

S~~~~~~iJT o----fT1

T2

UNIVERSAL WINDING, AWG NO. 36 WIRE
62 TURNS WITH TAP AT 8 FROM GNO
L' 25.5.H. Q. 30
UNIVERSAL WINDINGS, AWG NO. 36 WIRE
PRIMARY: 77 TURNS. L = 11.8 /lH, Q'" 40
SECONOARY, 34 TURNS. CT. L' 9 "H.
20

a·

C

CD

a.

MC1370P (continued)

FIGURE 5 - CIRCUIT SCHEMATIC
ACC
CONTROL

OSCILLATOR
OUTPUT

2-3"

16-15

CHROMA
INPUTS

APC
CONTRO L

14---1-3-

OSCILLATOR
INPUT

12-11

6

OSCILLATOR
FEEO·BACK

7~

R14
10k

HUE 1
CONTROL

R13

2.2k

HUE
CONTROL
SECTION

-t_---,r--_..-_..--_....-_..--_...-......-'cl0BIAS

r-_ _ _ _

+24 V
BURST \4
GATE

R31
390

01

-4-_-1

21

1<>5_ _

BIAS
SECTION

GATING
SECTION
Pin 9 no connection.

CIRCUIT DESCRIPTION
The MC1370 monolithic circuit provides the sub-carrier regeneration function necessary for a color television receiver to

decode the NTSC color signal. An internal gate extracts the burst
voltage and this signal is processed in two-phase detectors, the

quadrature detector controls the phase of the local oscillator and
the in-phase detector is used to provide a noise immune ACe and

color killer control voltage. A shunt regulator sets the bias voltages
and ensures stable operation when there are supply voltage variations.
The basic 3.579545 MHz oscillator consists of the differential
amplifier (Q 1 and Q21 with a feed-back loop through a quartz crystal
operating in series resonance from 02 collector to the non inverting
input of the amplifier represented by Q1 base. To control the
oscillator frequency the phase shift of the feed-back path is made
variable by the addition of 05 and 06. A capacitor connected
between pins 7 and 8, together with the collector loads, forms a
RC phase-shift network. Consequently, the oscillator signal appearing at pin 7 can be moved in phase over a 45 0 range by the differential bias applied to 05 and 06 bases. The crystal between pins
7 and 6 completes the feed-back loop. The automatic phase control
to the upper differential pairs of the (Q5, 061 oscillator is through
the buffer stages Q7 and 08. The oscillator amplifier is buffered
by 03 and Q4. Output from the oscillator is obtained from the
collector of 1 and is essentially a square wave of 9 rnA peak-topeak with a frequency range of several hundred Hertz.
The control voltage for 05 and 06 is obtained from the phase
detector 09 and 010. As 01 is the current source for this pair,
the voltages appearing at pins 11 and 12 will correspond to the
phase difference between the oscillator current and the burst signal
applied to pin 13. The loop characteristics are controlled in part

a

by a filter connected between pins 11 and 12. This is usually a
double-time constant network to yield good pull-in times with a
low-noise bandwidth.
To ensure that the quadrature phase detector functions only
during the burst portion of the incoming chroma signal, the detector is gated into conduction by a pulse from the line flyback transformer - applied at pin 4. This has the additional advantage that
the average current in the phase detector has been reduced by the
gate duty factor thus relaxing the input offset stability requirements
of the differential pair and enabling them to be used with high dc
gain.
For the ACC control voltage and color-killer function a similar
phase detector, 015 and 016, is used. However, the chroma signal
input to pin 14 is phase shifted externally by'90 0 with respect to
pin 13. As a result, Q15 and 016 is an in-phase detector and the
control voltage at pins 15 and 16 will be proportional to the amp·
litude of the burst. Thus filtering of pins 15 and 16 provides the
control voltage for the gain control stage in the chroma I F and an
indication of the incoming signal strength for the color-killer circuit.
When the phase detectors are not gated "on" by a positive
pulse at pin 4, the bases of Q13 and Q14 are held above the bases
of the phase detector inputs. Therefore, between gate pulses, all
the current from the oscillator output Ql passes through Q13 and
014 to pins 2 and 3. When a phase-shift network is connected
between pins 2 and 3, the phase of the oscillator drive to the demodulators can be controlled by changing the relative conduction
of Q13 and 014 with a bias on pin 1. As a result the oscillator output is controlled in phase providing a dc hue control and is gated
"off" during the burst period, negating the need for burst blanking
in the chroma I F amplifier.

7-97

•

I

MC1370P (continued)

TYPICAL CHARACTERISTICS
FIGURE 6 - STATIC PHASE ERROR versus
FREOUENCY OFFSET

FIGURE 7 - PULL·IN FREQUENCY RANGE versus
BURST INPUT VOL TAGE LEVEL

+1 0

+8.0
~

en

"'w

V V
/ V
V _f..-

+6.0

~ ~ +4.0

zto

",w

~~ +2. 0

",0"''''
w'"

400 mV BU RST "-

0

~~

-2. 0

z'-'

~ ~ -4. 0
~'"

~ t:?'

+100 0

V

~ 'N +800

"'"
~ :; +60 0
~ii

...J co +400

I.e V

+20 0

s_

-20 0

-'"

'"

IA
BURST
VV'. 75200m~mVBURSt
-8.o
·1 oVI/
-300 -240 -IBO -120 -60

f

/

MAXIIMUM
AVAILABLE
FREQUENCY
RANGE

0

L.-?

f..-

V

-'~

~M

N

~ :; -40 0

~~ -6. 0

3!

-60 0

~

-80 0

-,",
M

\

~

-100 0
+60

+120

+180

+240

o

+300

200

OSCILLATOR FREE· RUNNING FREOUENCY
OFFSET FROM 3.579545 MHz 1Hz)

0

FIGURE 9 - OSCILLATOR SENSITIVITY

+3 0

to

;0

c3~ +2 0

/

>~

l:i::i

g +1 0

tt~

/

"'+

0

0'-

-1 0

<>ON

~~

/

l:i::i~-2 0

V

oV

L

+40

"'

/'

V

'"~

-3 0
-4

100

200

300

400

BURST INPUT LEVELlmVp·p)

lL

L

~

:~-400

-5
-500

k'"

V

lL

L

/"

-300

-200

-100

+100

+200

+300

+400

+500

OSCILLATOR FREQUENCY OFFSET
FROM 3.579545 MHz 1Hz I

DEFINITIONS
Oscillatur Sensitivity

800

+50

..,..- J..--

0

600

400
BURST INPUT LEVEL!mVp·p)

FIGURE 8 - ACC DETECTOR SENSITIVITY
400

0

,

1

r-

given change in burst input amplitude with the oscillator locked
in synchronism, measured in millivolts dc/millivolts (p-p).

1m

· .. the change in oscillator free-running frequency for a' change in

Noise Bandwidth IfN)

differential control voltage, measured in Hertz/millivolts.

... actually noise semibandwidth, fNN (= 2 X fN); a measure of
the susceptibility of the burst channel to thermal noise (i.e. dynamic phase errorl.

APe Detector Sensitivity (jJ)
· .. the differential voltage change produced at the detector output
for a given change in oscillator phase relative to burst phase, meas-

Filter Damping Coefficient (K)
. describes the shape of the loop input phase versus output
phase response (Ow) - K = 1 represents critical damping, K
1
over damping.

ured for a given burst input amplitude in millivolts/degrees.

>

ACe Detector Sensitivity
· .. the differential voltage produced at the detector output for a

7-98

MC1371P ~~__________C_H_R_O_M_A__IF_A_M__PL_I_F_IE_R____~

TELEVISION CHROMA
IF AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

TELEVISION CHROMA IF AMPLIFIER

· .. a monolithic device designed to provide the basic control and
color signal amplification stages of a solid-state .color television
receiver. The MC1371 is a combination of two wideband chroma
amplifiers and a color control circuit .

•

• Schmitt Color- Killer Circuit with Adjustable Trigger Level
• Linear Action dc Manual Gain Control
• Short-Circuit Protected
• Gain Stabilized Against Supply Voltage and Temperature Changes
• Low Phase Distortion
• Excellent Gain Linearity Over Full Output Range
• Direct Replacement for the CA3071

PLASTIC PACKAGE

CASE 646
TO-116

FIGURE 1 - MC1371P SYSTEM BLOCK DIAGRAM

KILLER
ADJUST

CHROMA
GAIN
10
CONTROL

13

1------

- - ---,

I
I
BIAS
CIRCUIT

I
I

I
I
1---+-012

I

I

CHROMA
INPUT o--t------~

2

I

) ___-1---09 CHROMA
OUTPUT

I

I

I

I

I
I

I
I

I

I

I

---~-

L_
14
ACC
INPUT

)---L--

IstSTAGE 2nd STAGE
OUTPUT
INPUT

See Packaging Information Section for outline dimensions.

7-99

II-b~-J

BYPASS

MC1371P (continued)

=+250 e

MAXIMUM RATINGS (TA

unless otherwise noted.!

Rating

Value

Unit

Power Supply Voltage

30

Vdc

Amplifier Output Short-Circuit Duration

30

s

625
5.0

mW
mwf'e

Power Dissipation (Package Limitation)

Plastic Dual In-Line Package

Derate above TA

=

+250 C

Operating Temperature Range (Ambient)

Storage Temperature Range

o to +75

°e

-65 to +150

°e

E LECTR ICA L CHARACTER ISTICS (Vee = +24 Vdc, T A = +250 e unless otherwise noted. See Test eircuit of Figure 2;
switch 51 in position 1, Rl wiper at ground, R2 = 10 kilohms.)

Characteristic

Min

Typ

Max

Unit

Quiescent Power Supply Current

17

28

31

mA

Short-Circuit Current
(pin 6 momentarily grounded)
(pin 9 momentarily grounded)

-

68
48

-

First Chroma Stage Input Bias Voltage (pin 2)

-

1.7

-

13.7
7.5

16.3
10.5

20
13.5

Static Characteristics
mA

First Chroma Stage Output Bias Voltage (pin 6)
ACe Balanced (51 in position 1)
ACe Unbalanced (51 in position 2)

Vdc
Vdc

-

1.4

-

Vdc

Second Chroma Stage Output Bias Voltage (pin 9)

16.6

17.6

18.6

Vdc

Quiescent Bias Voltage (pin 12)

13.B

14.8

15.7

Vdc

dB

Second Chroma Stage I nput Bias Voltage (pin 7)

Dvnamic Characteristics

(f

= 3 579545 MHz

input pin 2

= 35 mV

[RMS] unless otherwise noted 1

First Chroma Amplifier Stage Gain (ACC Balanced)

14

17

20

Second Chroma Amplifier Stage Gain
(R1 wiper at ground)

12

15.5

17

dB

Maximum Linear Output (output level at pin 9)

-

2.0

-

V(RMSI

Output Voltage, pin 9 (input pin 2 = 50 mV [RMS])
(R1 wiper at Vee)
(R 1 wiper at ground, R2 adj usted for abrupt ac change in
pin 9 output voltage)

-

-

12
12

16.7
2.5

20.2
3.2

21.6
4.5

Second Amplifier Gain Stability
(Vee+ 15%1
(Vee -15%1
(TA = +250 e to +750 el

-

+0.5
-0.5
+0.5

+1.5
-1.5

I nput Impedance
(pin 21

-

2.0
3.5

-

kn
pF

-

2.2
3.6

-

kn
pF

-

85
85

-

mV(RMSI

Pin 10 Bias Voltage
tRl set for 10% of pin 9 maximum output)
(Rl set for 90% of pin 9 maximum output)

Vdc

dB

-

(pin 71
Output Impedance
(pin 61
(pin 91

-

ohms

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-100

MC1371 P (continued)

TYPICAL CHARACTERISTICS
(Vee = +24 Vdc, fO = 3.579545 MHz, TA = +25 0 C unless otherwise noted.)
FIGURE 2 - TEST CIRCUIT

J.

6.8 k
0.05 pF,
62 k

2
I

390 k

100

; F'

13

t14

0.05
"F

J
J
J
J
J

I

5.8 k

10

L

2

2.7 k

t

4

I

-=

~7

6

~O~

100

005

1

8

9

MC1371P

+1

1

Y
Rl

11

12

I

1 "F

22 k

2~JJ
75k

o~o:

I

J
J
J

-=

*O.OlpF

Ik

18 k

SI

I

62 k

O~~

F'

J

24 V
VCC

33

10 k
R2

"F

-=

0.05"F

IN~UT k

2.2 k

lk

2

3
4

1
OUT:-:

S2

1

FIGURE 3 - MANUAL GAIN CONTROL LINEARITY
1. 0

v;

o.9

~
~

0, 7

'"~

0.6

.........

""-

O. 8

""-

KILLER "OFF"

"-

PIN 2 INPUT ~ 50 mV IRMS)

§; 0.5

"'-

>-

~

0.4

'"o

0.3

z
c::: 0.2

""-

""-

O. I

o
o

5.0

10

"

15
PIN 10 CONTROL VOLTAGE IVdc}

25

20

FIGURE 5 - AMPLIFIER LINEARITY

FIGURE 4 - FIRST STAGE GAIN WITH ACC BIAS
80 0

1

/

@70 0

"

en 3. 0

/

;- 600

£
~ 400
>
>-

~ 30 0

V

>-

'"~ 20 0

/

0
-200

V

~

/

/

~

z

c:

/
0

-100

/

+100

+200

ACC OFFSET VOLTAGE ImVdc)
(Voltage Between Pins 14 and 1)

7-101

1/

Rl WIPER AT GROUND
KILLER "OFF"

/

1/

>

~1. 0

/

z
c::: 100

/

o

PIN 21NPUT ~ 50 mV IRMS}

:/

,.

1

ffi

10

e

~

I

:::.
w
'"~ 2. 0

II

;0

I

/'

!

/

~ 50 0

If-

t;:
8.0 ~
w

~

/
II

6.0

«

~

>-

'"

4.0 ~
o

2.0 ~

1/PIN 9 PHASE

c:

C~ANGEI
200
100
PIN 2 INPUT VOLTAGE (mV IRMS))

'"
w

300

•

MC1371P (continued)

FIGURE 6 - CIRCUIT SCHEMATIC

COLOR KILLER CIRCUIT

BY PASS
11

R5
3.3 k

10

CHROMA GAIN
CONTROL

R17
10 k

R16
5.6 k

RS
2.4k

BIAS +24 V

R18
2.4 k

R19
1.2k

R20
3.7k

13
R9
Ik

KILLER
CONTROL

RIO
36

R13
500

01
12
BYPASS

CHROMA
OUTPUT
R23
1.3 k
R21
5k

SECOND CHROMA
AMPLIFIER

BIAS
CIRCUIT
R22
Ik

R24
3k

R25
15 k

R29
7.6 k
U8

R28
3.3 k
CHROMA
INPUT

RI
2.4 k

FIRST CHROMA
AMPLIFIER

R26
1.2 k

ZI

R2
220

04

R7
360

R27
Ik

7
SECOND STAGE
INPUT

6
FIRST STAGE
OUTPUT

CIRCUIT DESCRIPTION
The MC1371 is a monolithic wide-band amplifier circuit that

functions as the basic control and color signal amplification stages
of a color television receiver. The first stage contains the gain
control function of the ACe loop and the second stage performs
the de manual gain control function. Also included is a Schmitt
trigger circuit providing effective color-killer action during mono-

chrome transmissions.
Q1 is a current source modulated by the input signal applied
at pin 2. The current in Q1 is divided between the differential
pair (Q2 and Q3) in a ratio determined by the ACe voltage applied

through the buffer stages, 04 and 05. Pin 14 is usually offset
with respect to pin 1 by a resistor connected to ground so that at
low-signal levels most of the signal current is taken by 03 and
passed to the load resistor R5 (the input stage appears as a cascade
amplifier to the signal with the intrinsic ac stability of that configuration). The amplified signar is then buffered at pin 6 by the
emitter follower stage 06 which is protected from accidental
grounding at the output bV the current limiter 07.
At strong signals when the amplitude of the burst is high,
the ACe voltages at pins 1 and 14 divert most of the signal current
from 03. The signal is "dumped" into the collector load of
02. Q2 is connected externally at pin 13 and bypassed to ground
at signal frequencies by a capacitor. However. the dc voltage at the
collector of Q2 is dependent on the burst amplitude and therefore

on the input signal strength. As the input signal level falls, more
current is fed into 03 by the ACC loop and the output at pin 6
remains constant while Q2 collector voltage increases. At a point
predetermined by 02 collector load (the killer-control setting)
the input 012 of the color-killer circuit is biased "on", shutting
down the second chroma amplifier stage.
The second chroma stage is similar in configuration to the
first stage. The signal input at pin 7 (which is the output from
pin 61 modulates the current source 08. For a maximum gain
voltage setting on pin 10 the signal current passes through Q9 to
the output buffer stage 010. 010 is protected from short circuit
currents by Q 11. To reduce the stage gain, current is diverted from
09 by biasing the diode D2 into conduction. 02 can be regarded
as a transistor with 100% de negative feedback applied between
collector and base. Without the feedback path the gain characteristic of the second stage is that of a differential pair, this S shaped
curve would make tracking of ganged color level and contrast
controls quite difficult. In this limiting form the current through
02 is directly proportional to the voltage difference between the
supply and 02 anode and hence to the control voltage at pin 10.
When the input to the color-killer is biased "on", Q13 is turned
"off" and the voltage at the base of 014 rises abruptly. 02 then
takes all the current from QS and the output at pin 9 is suppressed.

7-102

s:

...

C')

...
CAl
-...J

"'C

FIGURE 7 - TYPICAL CHROMA APPLICATIONS CIRCUIT
IMC1370, MC1371, and MPS UIOI

C)

o

::s

COLOR KILLER ADJUST
10 k

33

~,

Vcc=+24V

CHROM \
INPUT

100

.~

f

1

2f 36

2.2 pF

~

390 k

-f~

I

S1 _2

=
200pF

"'\lflO

~~

2'
A

AD

T

100

"

62k

f-1~

f---

0,05 pF

Io05 pFf

~

SWI
POS
POS

16

15

1 Sl
)N 2 = SET-UP

t

22k

L-

OO~ ~

0.05 pF

62k

470 25 V

22k

l
12

14 13

11

1.5 k

re- t
0.05 JlF

43 pF

0.05
pF

47 pH

68p" (

10

f-1~

Vee'" +24 V

160pF

1

lk

43 k

'"

.

3

4

MPSU10
or equiv

1:

,

BEAD

I

3.3 k

470pF

=

250

=

O.Ol'pF

J
O.15}JF

100

nn
100

100

1

250

~:."o;
=

LUMINANCE
SIGNAL INPUT

"'q'"

l:PF 7t 65 pF 8t

~

=

200pH

~)

Tl

1.5 k

200 pH

"-------==

=

97

5

[WFERRlTE
36

250 k

HUE
CONTROL
lUlSE

2

10 k

-ED-

3.3 k

15pH

>--j~f--

c..

200 p"

MPS U10

360 pF

180

62k

CD

10k

0.01 pF

O.05pF

f470/1W
10/.lF

I
7

IN 1" NORMAL

36 k

+4 V,
INPUT

~4t566

v

MC1370P

HORIZ K

-

c

33
:

8?

MC1328

pF_

+24

=

0.05 pF

30 pF

I

pF

~

1

1~

13 12yll lOy 9

2.2 k

65 pF

62k
~

=

l~
=14

lk

2.7k
680

~
20 k
ACC
ADJUST

220pF

r--

w
"-

------1

7

6

41 56

,220
_

12.7 k

1.8 M

o

T2

8

9f

12 pF r - '5o;;'F

~~
~

5k

MC1371P

I

220pF

= Tl

f-1~

CONT~

fj~

orequiv

0.01 pF

0.05 pF

"J4?13 PF12

470 47 pF

CHROMA
BANOPAS
ADJUST 5 25 k

1k

r

~

CHROMA
GAIN

::s

'"'

MPS Ul0

UNIVERSAL WINDING, AWG NO. 36

62TURNS WITH TAP AT 8 FROM GN
L" 25.5 pH, Q" 30
T2

UNIVERSAL WINDINGS, AWG NO. 3f
PRIMARY: 77 TURNS. L = 11.8 ,uH, I

SECONDARY' 34 TURNS, CT, L" 9,

MC1398P

~______T_V_C_O_L_O_R__PR_O_C_E_S_S_I_N_G_C_I_R_C_U_IT__~

TV COLOR PROCESSING
CIRCUIT

TV COLOR PROCESSING CIRCUIT

MONOLITHIC SILICON
INTEGRATED CIRCUIT
... a chroma IF amplifier with automatic chroma control, color killer,
dc chroma control, and injection lock reference system followed by
dc hue control.
MC1398P is a monolithic device designed for use in solid-state
color television receivers.

•
•
•
•
•
•
•
•
•

Minimum Number of External Components
DC Control of Both Chroma Amplitude and Hue Shift
Crystal-Controlled Internal Feedback Oscillator
Built·in Noise Immunity
Schmitt Trigger Color Killer
Automatic Chroma Control
Internal Burst Gate and Gate Pulse Shaping Circuit
High Oscillator Lock·in Sensitivity
Built·in Supply Regulation

PLASTIC PACKAGE
CASE 646
(TO·116)

FIGURE 1 - TYPICAL CHROMA APPLICATIONS CIRCUIT
IMC1398P, MC1326 and MPSU10)
TO PIN 14

IMC1~98)

r-_+-_"-,[IKILlER CONTROL
8lA~KING

INPUT

lUMINANCE
INPUT

---1

~"
o

JL:!

H.2I1H

220pF

H'I-'-"'f"'--i

;:r

'""

l-J'"
fl,12 SH Flgu" 1010,co"

TO PIN 14

(MCll9S1

~'Ia

See Packaging Information Section for outline dimensions.

7-104

MC1398P(continued)

MAXIMUM RATINGS ITA

+250 e unless otherwise notedl

=

Value

Unit

35

mAdc

Horizontal Pulse Input Current

250

p.A Peak

Power Dissipation (package limitation)
Derate above T A = +25 0 e

625
5.0

mW
mW/oe

-20 to +75

ue

-65 to +150

ue

Rating
Power Supply Current

Operating Temperature Range (Ambient)

Storage Temperature Range

E LECTR ICA L CHARACTER ISTleS IVec

=

+20 Vdc RS ~ 390 ohms T A = +25 0 e unless otherwise noted.!

Min

Typ

Max

Unit

9.0

9.6

11.5

Vdc

-

9.2

-

Maximum Undistorted Chroma Output, See Note 1,Elpin 31 - Elpin 141

O.B

1.75

-

Vlp·pl

Maximum Chroma Gain

34

40

-

dB

Characteristic

Regulated Voltage liS

= 35

mAl

liS = 27 mAl

Elpin 31

= Elpin

141, See Note 1
dB

19

Automatic Chroma Control Range IACCI

-3.0 dB down from maximum undistorted output ,see Note 1

-

1.4

-

50

60

-

-

2.3

-

-

13

-

pF

15

-

ohms

Horizontal Input Pulse

2.2

3.0

4.0

Vp

Oscillator Output

100

-

mVIRMSI

-

15

-

Chroma Burst Level to Kill, See Note 1

mVlp-pl

Manual Chroma Gain Control Range

dB

16 Vlpin

31 IVlpin 141 to 0 Vdcl
Chroma Input Resistance
Chroma I nput Capacitance
Chroma Output Impedance

Oscillator Output Impedance

k ohms

ohms

degrees

Hue Control Range

I" Vlpin 121 IVlpin 141 to 4.3 Vdcl
Oscillator Pull-In Range

100

126

-

1200

-

-

-

900

-

Oscillator Noise Bandwidth IfNI

Hz
Hz

Static Phase Error with Oscillator Detuning

degreeslHz

-

25 mVlp·pl Burst Amplitude
2.0 mVlp-pl Burst Amplitude

-

0.20
0.25

-

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

Note 1: With 5.0 mVlp·pl burst input at pin 5
set Elpin 101 to just "unkill".
FIGURE 2 - MC139BP TEST CIRCUIT

18 OpF

OSCILLATOR
PEAKING
1.8 k

REGULATEO
VOLTAGE
1

1
14

1\

4",

11ki

CHROMA
CONTROL

t

o.05 "F

-'S

100~ OSC
1000 pF

lL8k
3

-=-

4

250pF

CHROMA
INPUT

•

~i

HUE PHASE
11

1ST ACC FilTER

CHROMA
BYPASS 6

9

2ND ACC
FILTER

~
ll: SEE FIGURE 10 FOR COil DATA.

7-105

,.------4
10k

-=b15k

ACC/KILLER
CONTROL

·U

B CRYSTAL :

HUE
CONTROL

4.7 k

~

10

7

OUTPUT

120pF

SHIFT

5

V
O.Olp.F

MC1398P

I
-=-

11

=10k

HORIZONTAL
INPUT

kilohms

+20 Vdt

13

1

CHROMA
OUTPUT

(VC~~ ~9.2

RS '"

RS ·390

0.01 "F

I~

0

O~~F

470

5.0pF
1\

•

S

n
.....

Co)

(D

CO
"'tI

FIGURE 3 - MC1398 CIRCUIT SCHEMATIC

8
CHROMA GAIN CONTROL

and OUTPUT

BIAS SECTION

CHROMA 1
OUTPUT

"

..

It,,.

US

CO,

"'

SOO

(l
-'

o

en

HORIZONT

"

PULSE1NP H

..

I

and FilL IN

I

QU G16

GO

"4~

'"
500

'"

1OO

~.

"

02

"

='"

n

CHROMA AMPLIFIER

.-'"

f-- ~038

5k

L--

:;;

*3.~Ok

V

,1,,'29

C1

'40'
13

=

~
~

"

019'

E"

02.

,,,

R24

.25

lPFJ
",.50

CHROMA BYPASS

=

'511O
42

t

'"

J

Uik

""

Q42

'06

rn

".

t5~=

"".....

,on

'"

Uk

~

..0

'"

=

~,

~ CRI3

, - t--

400

Uir.

D2B

400

,

~

CHROMA
INPUT

.41

R28

02'

""

..."
It~'"

p--

~"B

r--

Z.4k

5

Jl

200
'"

1122 016

J.

R12

:;;-1-=

~.J;~1I
"."
~

L~R~~-1

R3

CR'

1k

I
r.uRSC;-GAT;;;i ~~

018
CR2

BOO

125
'"

.21

I

r~J;t

'R>

'"

Al'

"

~

f-

OUTPUT

SHIft

jT::'::""'U

'"

=1.8k

130SCILtATOR

'16

~ "d
R4

e",

11 PHASE

CONTROL

'""

500

01

,>-

HUE

,,.

U14

UW

100

CR' ~

12

J CHROMA
CONTROL

rd:
"

'"
"."

5'
c
[

OSCILLATOR OUTPUT

B'

CRB

~

HUE CONTROL and

U5l1

...".
'"

'00

.'"

045

'"

25O

.--

'"

0.,

,..

15k

...

t-

'"
=
150

CR1(l

CAll

=
1ST ACC fiLTER

OSCILLATOR

FEEDBACK

""

"'0

l.Sk

=

325

I

)

Y041

'"

CRYSTAL

[flll

AND

10 ACCKllLER

9 FitTER

CONTROL ACe CIRCUIT

=

"

Me 1398P(continued)

TYPICAL CHARACTERISTICS
(T A

= +25 0 C unless otherwise

noted)

(Figures 4 through 9, See Test Circuit of Figure 2.)
FIGURE 5 -

FIGURE 4 -INPUT/OUTPUT CHARACTERISTICS

2.B
2. 6

REGULATED VOLTAGE

5

I

~2.4

f2.2

~ 2. 01- E(pin

10)

= Note I

~ 1.8
01. 6

>

t-

1.4

/

'"

>- 1. 2
~ 1.0
~ O. B
~ o. KILLER

5

V

6

0.4

ONr-

O. 2
0

3.0

--

I
/6 ~d~

....,

5

5.~ JdC
20

10

30

50

15
6.0

200

100

6.5

7.0

CHROMA INPUT VOLTAGE (mV[p.pll

7.5

/

/

./

I

5.0

/

L

KILLER
OFF

-

[

2.0

~

/'

0

E(pin 31 = E(pin 1 4 1 -

B.O

B.5

9.0

9.5

10

PIN 14 REGULATEO VOLTAGE (Vdcl

FIGURE 7 - OSCILLATOR OUTPUT versus
PIN 12 VOLTAGE

FIGURE 6 - HUE CONTROL OPERATION

160

lBO

-I--

1

160

I'-----

'in = 20 mV(p·pl

.........

E(pin 101 = Note 1 -

,.-

""-

~ 140

~
g

\.

\

.s>

/'

~ 120
>-

\

'in =20 mV(p·pl , _
E(pin 10) =Note 1

'" 100

o

~

o

I\,
4.0

5.0

6.0

7.0

B.O

10

9.0

BO
3.0

11

4.0

5.0

B.O

PIN 12 VOLTAGE (Vdcl

.,

+20

ffi

+1 5

ffi

+10

~

........

0>

;- +5.0
o
a:

--

Phase Error unacceptable

"

~

ffi

w
~

~
~

In

-5.0

Phase Error perceptible

·20
·25
·100

"Ii
(;OJ

Phase Error unacceptable

·BO

·60

-40

'r-...

~~
lQ.., ~

-10

-15

"-

Phase Error perceptible

'" I"

·20

+20

B.O

9.0

10

11

FIGURE 9 - TEMPERATURE STABILITY of the
MC1398 OSCILLATOR
(lIe only subjected to temperature change)

FIGURE 8 - STATIC PHASE ERROR

+25

7.0

PIN 12 VOLTAGE (Vdcl

+40

'"

I\.

'\

'\

ft>l;ji-"4"

<~ro:;;;--

I

+60

0..,._
-40
20

+BO +100

30

40

50

60

70

AMBIENT TEMPERATURE (OCI

FREQUENCY OFFSET (Hzl

7-107

BO

90

100

I

Me 1398P (continued)

FIGURE 10 - PRINTED CIRCUIT LAYOUT OF MC139BP, MC1326, and MPSU 10 TRANSISTORS
~-------------------------------------------6;n.------------------------------------------~

KILLER/ACC ADJUST

+24 Vdc

HUE CONTROL

I

.""
.,",.0

+250 Vdc

/

22
pF

GREEN OUTPUT

m "mm

. /sLU EO UTPUT

~

4 in.

om "F

---If-I
CHROMA
INPUT

220 pF 'r:.

.3.3 pF

~~.

JC

;~;f ~

~

T2

47k

~

BOTTOM
HORIZONTAL
HUE CONTROL
INPUT
LIMIT

LUMINANCE
INPUT

BLANKING
INPUT

NOlES:
All resistors are 1/4 W unlEss othenvif.!! noteil
1Coppef Sicre Sho'l'l'fl)

L1:

r-0.51-

iO.875]
0.25

SLUG
EXTRACTED ~
1
I
-----10.5

-j

TOP
0.1875

~~
1

·I=-J

1-1- 1.0~

L1:80TURNSOF
STANDARD #38 AWG
HEAVY POLYTHERMALEZ
WIRE.

MC1398P APPLICATIONS INFORMATION
MC1398P is a multifunction circuit with considerable_ gain associated with the chroma amplifier and oscillator sections. It is
important to the circuit layout utilizing the MC1398P that the

chroma amplifier, oscillator, and oscillator output/hue section

TAP

W

BOTTOM
VIEW

Ground loop problems
will interfere with oscillation stability and lock-up if this pre-

caution is not observed.
Care must be exercised to avoid coupling from the oscillator
output to the crystal circuitry connected to pin 8. Stray coupling
of these two points can result in excessive oscillator shift; or in
some cases, oscillator drop-out during adjustment of the hue
control.
A suitable circuit layout for the MCl398P is shown in Figure 10.
An adjustable capacitor (1.5-20 pF in parallel with a fixed

22 pF capacitor) is shown in series with the 3.58 MHz crystal. This
capacitor is used to adjust the oscillator exactly on frequency,
and ensures excellent oscillator lock-up. However, acceptable
oscillator performance can be obtained with a fixed value of capacitance (this value is dependent on the designers' choice of crystals).

7-108

}69.6TURNS

F}S.3TURNS

COILCRAFT FORM #10·32 OR EQUIV
UNIVERSAL AWG #36 WIRE OR EQUIV
L "26 JlH

INPUT

grounds are separated from each other,

1

OUTPUT

'foj
LBO~TOM
-

VIEW)

COILCRAFT FORM #10-32 OR EQUIV
UNIVERSAL AWG #36 WIRE OR EQUIV
Lp = 121lH primary winding
LS =8.8,uH secondary winding

K" 0.4

This coil data is intended as an aid only. It is
expected that many designers will want to use
other approaches.

MC1398P (continued)

MCl398P CIRCUIT DESCRIPTION

The MC1398P is capable of providing the entire co lor processing

response band of the crystal will appear equally at Q50 and Q29

function between the second detect,or and the demodulator for
television color receivers.
A band pass filter from the second detector provides a 50 mV

bases and be suppressed in the output by the differential amplifier
common-mode rejection ratio (about 40 dB).
To maintain
oscillation, a feedback signal with the correct phase is passed by

(p.p) signal (for a saturated color bar pattern) at the input to the
first chroma amplifier stage (Q2. Q3. QS. Q91. Because of Q2
emitter load resistor the input impedance is determined primarily
by the bias resistor (R3) and is about 2.3 kilohms. Since Q2 is the
current source for the differential pair (Q3 and Qg), the chroma
information will pass to the load resistor (R7) and then to the
second chroma amplifier (Qpl. To avoid overload of Q17. the
maximum gain to Q17 base is only X3 and by varying the bias at
the base of Q9 it is possible to reduce the stage gain by 23 dB

Q35 back to the input of Q27.

Careful control of the resistor

ratios ensures that Q29 and 050 are operated linearly with about
350 mV (p.p) at R33 and R42. due to self oscillation. A burst

without signal distortion; the signal being "dumped" by 09

signal as low as 2.0 mV (p.p) at the chroma input is sufficient to
cause the oscillator to lock to the reference phase and frequency.
As the burst amplitude increases, the level at 029 and 050
collectors changes and this shift is used to provide the automatic
chroma control function. 042 and 045 form a modified differential
amplifier and with zero offset bias 045 conducts most of the
current from 043. As an increasing burst level swings Q29 and

collector into the supply.

Q50 collectors. the current from Q43 is shunted into Q42. At a

Since this automatic chroma control

action will vary the de bias at 017 base the emitter load of 017 is
the current source 018, maintaining the dc operating current. 018
collector is bypassed externally to prevent ac signal attenuation.
During picture scan time, the chroma signal passes through the
output level control amplifier (Ql0. Qll. Q15. Q211. By changing

the bias on 011 and 015 bases the signal can either pass to the
output pin 2 or be "dumped" into the supply through Qll· The

use of buffer stages 010 and 021 prevent distortion at low·signal
levels and the control range is better than 70 dB. The signal output
is also buffered by a 14 and 020, thus providing a low impedance
drive of up to 2.0 V (p.p) to the demodulator, with an overall
gain between pins 5 and 2 of 40 dB. To enable the chroma signal
output to reach the amplifiers from 017 collector, 012 is held in
conduction by 05 which in the absence of any input on pin 4 is not
conducting.

This high collector voltage also holds Q26 in

conduction, clamping the input to the burst channel and preventing
chroma information reaching the oscillator. During picture retrace
time, a positive-going 4.0 fJS pulse from the line sweep transformer
will turn 05 "on" and 07 "off". When 05 collector goes low,
012 will become "cut·off" preventing the burst signal at 017
collector from reaching the output pin 2. At the same time, 026
turns "off" opening the burst channel. The high collector voltage

point predetermined by the setting of the automatic chroma control
connected to pin 10. the composite lateral PNP of Q47 and Q46

will be biased into conduction. This amplifier has a gain of unity
and a filter capacitor (connected to 046 base) prevents any
tendency to oscillations. Diode CR9 provides thermal campen·
sation to ensure a steady color·killer threshold paint. The increas·
ing current through 013 emitter is used to control 09 base,
attenuating the input signal as the burst amplitude increases. The
current from 013 also keeps 019 in saturation. When the input
signal becomes too small for satisfactory color rendition, 013
current falls and 019 comes out of saturation. This means 025
will saturate, clamping 021 base and "killing" the chroma output
stage. R24 in the Schmitt trigger circuit ensures that the color·
killer will have hysteresis to prevent fluttering between "on" and
"off" states.
The oscillator output voltages at R33 and R42 are used to
drive 038 and 039 into limiting so that as the burst amplitude in·
creases the oscillator activity to around 700 mV (p.p), there will
be no change in the oscillator output amplitude at pin 13. 038 and
Q39 are used as current sources with a 1800 phase difference for
the differential pairs Q30 and Q31. Q34 and Q37.

017 collector to the subcarrier regenerator and 022 "fills·in" for
012 during the gate period to prevent a dc shift in the pin 2
output voltage.
The gated burst signal is applied to the oscillator through 027
and Q2S.

Q29. Q50 and Q35 together with Q27 and Q2S form

an injection locked oscillator circuit. At series resonance of the
crystal connected to pin 8 the impedance of pin 8 is very low,
thereby reducing the 3.579545 MHz carrier level at the ba,se of

050. The signal at the base of 029 is not reduced but the output
voltages in R33 and R42 will change.

A small

capacitor attached externally to 039 collector adjusts the total
phase difference to 1350 . Since the signal appearing in the load
resistor R51 will be the vector sum of 031 and 037 signals,

of Q7 turns on Q16 and Q22. Q16 passes the burst signal from

varying the base bias of Q3g and Q34 will change the oscillator
output phase over the 135 range. Q40 and Q41 buffer the

oscillator output providing a low impedance drive at pin 13 for
the demodulator.
To minimize crosstalk between the burst and chroma channels,
separate bias chains are used. Further, the oscillator bias chain
is zener regu lated to prevent phase shifts in the reference output
with power·supply variations.

Any signals outside the

7-109

DUAL DIFFERENTIAL COMPARATOR

MC1414L

MONOLITHIC DUAL DIFFERENTIAL VOLTAGE COMPARATOR
· .. designed for use in level detection, low-level sensing, and memory
applications.
Typical Amplifier Features:
• Two Separate Outputs
• Strobe Capability
• High Output Sink Current - 1.6 rnA min Each Comparator
• Differential Input Characteristics:
Input Offset Voltage = 1.5 mV
Offset Voltage Drift = 5.0 /LV/oC
• Short Propagation Delay Time - 40 ns
• Output Compatible with All Saturating Logic Forms
Vout = +3.2 V to -0.5 V typical

MAXIMUM RATINGS (T, =2S'C unless otherwise noted)

Rating

Symbol

Value

Unit

Power Supply Voltage

V+
V-

+14
-7.0

Vdc
Vdc

Differential Input Signal

V.

!5.0

Volts

!7.0

Volts

10

mA

750
6.0

mW
mW/"C

In

Common Mode Input Swing

CMV.

In

Peak Load Current

IL

Power Dissipation (package limitation)
Ceramic Dual In-Line Package
Derate above T A = 50'C

PD

Operating Temperature Range

TA

Storage Temperature Range

T stg

o to

+75

-65 to +150

L SUFFIX
CERAMIC PACKAGE
CASE 632

TO·116

·C
·C

CIRCUIT SCHEMATIC

v+

STROBE

3

2

3.9 k

OUTPUTS

1

8

7

9

2.8 k

2.8 k

v-

STROBE

11

GNO

See Packaging Information Section for outline dimensions.

7-110

v+
10

3.9 k

14

v-

MC1414L (continued)

ELECTRICAL CHARACTERISTICS

(V+

= +12 Vdc V- = -6 Vdc TA = 2SoC unless otherwise noted) (Each Comoaratorl

Characteristic Definitions (Unear operation)

'
~

Vi.

VO",

R,

-;

Rs :S;2(lOn

Characteristic

Symbol

Min

Input Offset Voltage
Vout = 1. 4 Vdc, TA =- 25° C
V out = 1.8 Vdc, TA = O°C

Vout

=

1.0 Vdc, TA

Typ

Max

1.5

5.0
6.5

mVdc

+75°C

=

.6.5

Temperature Coefficient of
Input Offset Voltage

5.0

Input Offset Current
V out = 1. 4 Vdc, T A = 25" C
V out = 1.8 Vdc, TA = O°C

1.0

~Y/"C

/.LAde

5.0
7.5

Vout = 1.0 Vdc, TA = +75°C

7.5

Input Bias Current
Vout = 1.4Vdc, TA =25"C

15

25

V out = 1.8 Vdc, TA = O°C

18

40

,uAde

Vout = 1. 0 Vdc, TA = +75°C

.~"-~.~~:"'

Unit

40

Open Loop
Voltage Gain
TA = 25"C

Y/V
1000

1500

800

T A = 0 to +75°C

L~~-

-

-

Output Resistance

200

Rout

Differential Voltage Range

Yde

Positive Output Voltage
Vin ?; 5. a mY, 0;;;; 10 ~ 5.0 rnA

VOH

2.5

3.2

Negative Output Voltage
Vin ~ -5.0 mV

VOL

-I. 0

-0.5

Output Sink. Current
Vin ~ -5.0 mV, Vout
TA =Oto+75°C

ohms

±5.0

4.0

Yde

Is
~

Yde

mAde

0,

1.6

Input Common Mode Range

2.5

±S.O

Volts

Y- = -7.0 Yde
Common Mode Rejection Ratio

Y- = -7.0 Vde,

11;

~

200 n

70

100

dB

Propagation Delay Time
For Positive and Negative
Going Input Pulse

40

Total Power Supply Current
Vout ~ 0 Vdc

12.8

18

II

14

230

300

mAde

Total Power Consumption

7-111

mW

I

MC1414L

(continued)

TYPICAL CHARACTERISTICS
(Each Comparator)
FIGURE

FIGURE 1 - VOLTAGE TRANSFER
CHARACTERISTICS

3.0

4.0

3.0

~
~

'>

-"w

~ 2.0

~>

2.0

~
>

~

§

2 - INPUT OFFSET VOLTAGE
versus TEMPERATURE

0-

-I----

~

o

1.0

0~
~

z

•

~

1.0

:>

~

o
o

-1.0

-5.0

2.5

25

FIGURE 3 -

50

75

TA. AMBIENT TEMPERATURE (DCI

Vin,lNPUTVOLTAGE (mV)

5

FIGURE 4 - INPUT BIAS CURRENT
versus TEMPERATURE

INPUT OFFSET CURRENT

versus TEMPERATURE
.0

.0
0

5-----

0

.0

0

"'"

~

0

25

----

0

25

75

50

75

TA. AMBIENT TEMPERATURE 1°C)

FIGURE 6 - VOLTAGE GAIN
versus TEMPERATURE

FIGURE 5 - GAIN VARIATION
WITH POWER SUPPLY VOLTAGE
2500

300 0

2500

I
V'-7/

~200 0

V J.---

V Vi-'

"
~

V ./
V V V
~
~10 OO~ 1/ ~
V
"
~150 0

>

-5Vd1:

-

~2000
z

~

~

~

~
~1500 1 - - - -

~
oo~
V

11

12

----

>

./

0
10

I---

5. 0

50

TA. AMBIENT TEMPERATURE (DC)

I

----

"

13

1000
14

V+, POSITIVE SUPPLY VOLTAGE {Vdcl

o

25

r---...

50

TA. AMBIENT TEMPERATURE {OCI

7-112

75

MC1414L

(continued)

FIGURE 7 -

FIGURE 8 - POWER DISSIPATION
versus TEMPERATURE

RESPONSE TIME
300

4. 0

0

\

0

1~~15mvDvERDRIVE

20 mV OVERDRIVE 0

l:

~250~-----~-----~-----~

\

t~ \-:2mvDvER~RIVE

10 TV DVERDR:VE 0

\L'-~

~

ill
c

I
I

I

-1. 0

~

w

~200~-----~-----~-----~

~

0

> ..

.P

1'=-1
>=

0

r------,---------.-------,

I

1

40

20

I

I

I

80

~

t,

100

1501,-0-------:!:25,.-------!51,.0-----..,I75

120

TIME (nsl

TA. AMBIENT TEMPERATURE (OCI

FIGURE 10 - SINK CURRENT versus TEMPERATURE

FIGURE 9 - RECOMMENDED SERIES RESISTANCE
versus MRTL LOADS
10 0

4. 0

::t>t:;roB

0

3.0

"-

0

-

i".,
0

0

,

mW MRlL

5. 0

I,

"

MED. POWER

2. 0

1. 0

0.1

ITII

0.2

0.5

""

1.0

'"

2.0

0

,~
0
5.0

10

25

RS. SERIES RESISTANCE (k OHMS)

FIGURE 11 - CROSSTALKt

3

j
2
1

I

,

I

0

j

,
I

2
1

0

--

50

75

TA. TEMPERATURE (OCI

,-- - . j

- -

Induced oulput signal in
amplifier 12 due to output

signal al amplilierll.

TlME,SOns/div
tworu cas8conditionshown-no load.

7-113

I

______f

\,-~_I_N_E_A_R_/D_I_G_IT_A_L_IN_T_E_R_F_A_C_E_C_I_R_C_U_IT_S~

MC1488L

QUAD MDTL LINE DRIVER
RS-232C
QUAD LINE DRIVER

INTEGRATED CIRCUIT

The MC1488L is a monolithic quad line driver designed to inter·
face data terminal equipment with data communications equipment
in conformance with the specifications of EIA Standard No. RS·232C.

LOGIC DIAGRAM

2~3::::Lr"

Features:
•

Current Limited Output
10 rnA typ

•

Power·Off Source Impedance
300 Ohms min

•

Simple Slew Rate Control with External Capacitor

•

Flexible Operating Supply Range

•

Compatible with All Motorola DTL and TTL Logic Families

:::Lr'
,:::Lr,

-f

01

•

014

V'

v- ..

CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN

V'14

~

8.2k
INPUT 4
INPUT 5

10

300
6 OUTPUT

r~3"k
NO

I

'~

~

10k

t-...
r--....

r

V- 1

7k

10

-

TYPICAL APPLICATION
LINE DRIVER
MC1488L

INTERCONNECTING
CABLE

LINE RECEIVER
MC1489l

...r--, ""

-j

,

~-_/

(top view)

~

INTERCONNECTING

MOTllOGIC INPUT ~t--

CABLE

I

~MDTllOG1C OUTPUT

I
See Packaging Information Section for outline dimensions.

7-114

CERAMIC PACKAGE
CASE 632
TO·116

01

MC1488L (continued)

Maximum Rating (TA = +250 C unless otherwise noted)
Rating

Symbol

Yaluo

Unit

Power Supply Voltage

y+
Y-

+15
-15

Ydc

Input Signal Voltage

Vin

-15:SVin:S 7.0

Vdc

Output Signal Voltage

Vo

±15

Vdc

Power Derating (Package Limitation, Ceramic Dual-In-Line Package)

1000
6.7

mW
mW/oC

TA

o to +75

T stg

-65 to +175

°c
°c

Pe
li8JA

eerate above T A = +250 C

Operating Temperature Range

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (v+ = +9.0± 1% Vdc. V- = -9.0 ± 1% Vdc. TA = 0 to +750 C unless otherwise noted)
Characteristic

Figure

Symbol

Min

Typ

Max

Unit

Forward Input Current

(Vin = 0 Vdc)

1

IF

1.0

1.6

mA

Reverse Input Current

(Vin - +5.0 Vdc)

1

IR

-

-

10

2

VOH

Output Voltage High
(Vin =O.S Vdc. RL = 3.0 kn, V+= +9.0 Vdc, V- = -9.0 Vdc)

+6.0

+7.0

-

(Vin =0.8 Vdc, RL = 3.0kn, V+ =+13.2 Vdc, V- = -13.2 Vdcl

+9.0

+10.5

-

(Vin = 1.9 Vdc, RL = 3.0 kn, V+ = +9.0 Vdc, V- = -9.0 Vdcl'

-6.0

-7.0

-

(Vin = 1.9 Vdc, RL =3.0kn, V+= +13.2 Vdc, V- =-13.2 Vdc)

-9.0

-10.5

-

2

Output Voltage Low

Vdc

VOL

Positive Output Short-Circuit Current

3

ISC+

+6.0

+10

+12

Negative Output Short-Circuit Current

3

ISC-

-6.0

-10

-12

Output Resistance (V+ = V-

4

Ro

300

-

5

1+

-

+15

+20

+4.5

+6.0

0, Ivol- ±2.0 VI

Positive Supply Current (RI -(0)
(Vin = 1.9 Vdc, V+ - +9.0 Vdc)

(Vin = 0.8 Vdc, V''' = +9.0 Vdcl
(Vin = 1.9 Vdc, V+ =+12 Vdcl
(Vin = 0.8 Vdc,

V'" = +12

(Vin = 1.9 Vdc, V+ = +15 Vdc)
(Vin = 0.8 Vdc, V+ = +15 Vdcl
Negative Supply Current (R L

=co)

5

+19

+25

+5.5

+7.0

-

+12
-17

+34

1-

mA

-

-13

(Vin = O.B Vdc, V- = -9.0 Vdcl

-

0

0

(Vin = 1.9 Vdc, V- = -12 Vdc)

-18

-23

(Vin = 0.8 Vdc, V- = -12 Vdcl

-

0

0

(Vin = 1.9 Vdc, V- = -15 Vdc)

-

-

-34
-2.5

-

-

333
576

(Vin = 0.8 Vdc, V- = -15 Vdc)
Pe

(V+ = 9.0 Vdc, V- = -9.0 Vdc)
(V+ = 12 Vdc, V- = -12 Vdc)

rnA
Ohms

(Vin = 1.9 Vdc, V- = -9.0 Vdcl

Power Dissipation

mA

mA

-

Vdcl

IJ.A
Vdc

rnW

-

SWITCHING CHARACTERISTICS (v+ = +9.0 ± 1% Vdc, V- = -9.0 ± 1% Vdc, TA = +25 0 C)
Propagation Delay Time (ZL = 3.0 k and 15 pFI

6

tpd+

200

ns

(ZL = 3.0 k and 15 pF)

6

tf

-

150

Fall Time

45

75

ns

Propagation Oelay Time (ZL = 3.0 k and 15 pFI

6

tpd-

-

65

120

ns

Rise Time

6

tr

-

55

100

ns

(ZL = 3.0 k and 15 pFI

7-115

I

MC1488L (continued)

CHARACTERISTIC DEFINITIONS

FIGURE 2 - OUTPUT VOLTAGE

FIGURE 1 - INPUT CURRENT
+9V

+9 V

-9V

-9 V

Ih

+5 V

FIGURE 3 - OUTPUT SHORT·CIRCUIT CURRENT

v+

FIGURE 4 - OUTPUT RESISTANCE (POWER·OFF)

v-

+1.9 V

ISC -

I

Vo
±2 Vdc

•

:1:.6.6 mAMax

ISC+

+0.8 V

FIGURE 6 - SWITCHING RESPONSE

FIGURE 5 - POWER·SUPPLY CURRENTS

+1.9 V

Logic "1"

I

J,-----ov
,iK '~t

"~:I

logic "0"

"

+0.8 V

tr and tf Measured 10% tD 90%

7-116

MC1488L

(continued)

TYPICAL CHARACTERISTICS
(T A = +2SoC unless otherwise noted)
FIGURE 7 - TRANSFER CHARACTERISTICS

FIGURE 8 - SHORT·CIRCUIT OUTPUT CURRENT
versus TEMPERATURE

versus POWER·SUPPLY VOLTAGE

<"
~
15

+12
V+=V-=±I!V

+9.0

~o +60.

V+I= v- = i9 V

2:
~

«

~

o

-9.0

~

I

I

I

-3.0

O.SV

i3
~ -6.0
o

-=

I

Vin

t-

3k

::>

~ -6.0 I>

'0

:=::>

r-v~,
-3.0 I-

ISC+
+6.0

"....::> +3.0

+3.0

~
o

...>
...

~
::>

"v+-V-=±6V

+12
+9.0

I

ISC-

"

~ -9.0

-12

V-=9V

r

-

·12
0.2

0.4

0.6

O.S

1.0

1.2

1.4

1.6

I.S

-55

2.0

+75

+25

+125

T. TEMPERATURE ('CI

Vin.INPUT VOLTAGE (VOLTSI

FIGURE 10 - OUTPUT VOLTAGE
AND CURRENT·LIMITING CHARACTERISTICS

FIGURE 9 - OUTPUT SLEW RATE versus LOAD CAPACITANCE
1000

+20r----r---,r----r---,r---,----.----~--,

+16~--4----4----4----4----+----+----+_--~

~

!

100

w

10

'\-f--

+8.0

'\1\:

1-- __

~ lk
::;

~

'"~

li!

'>

">

12

f--

10

f--

S.O

f--

6.0

f--

v+

14
1

............

r-....

""-

3 3k
~

6 3k
S 3k
11 3k

4.0
2.0

1711v- I
f--':'I
·55

+25
"
T. TEMPERATURE
(oCI

7-117

+75

+125

•

MC1488L

(continued)

APPLICATIONS INFORMATION

FIGURE 13 - POWER·SUPPLV PROTECTION
TO MEET POWER-OFF FAULT CONDITIONS

The Electronic Industries Association (EIA) has released the
RS232C specification detailing the requirements for the interface

between data processing equipment and data communications

--.t~-..-------.--V+
14

.---'--..,

equipment. This standard specifies not only the number and type
of interface leads, but also the voltage levels to be used. The

- - --- -..- ---914

rMcl~8i.-~

I
I

,.. .........
I

I

I

\

MC1488L quad driver and its companion circuit, the MC1489L

0- T-~

quad receiver. provide a complete interface system between DTL

O-~-i-- .. '\ :
'
0-+-0
eraI
, ""1. ___ ...' ,I

I

or TTL logic levels and the RS232C defined levels. The RS232C

requirements as applied to drivers are discussed herein.
The required driver voltages are defined as between 5 and 15volts in magnitude and are positive for a logic "0" and negative for
a logic ",", These voltages are so defined when the drivers are
terminated with a 3000 to 7000-ohm resistor. The MC1488L ·meets
this voltage requirement by converting a DTLlTTL logic level into
RS232C levels with one stage of inversion.
The RS232C specification further requires that during transitions, the driver output slew rate must not exceed 30 volts per
microsecond. The inherent slew rate of the MC148BL is much too

L __ ....

,o--t""<)
I

0- .. -.1---"\

I!

I

0-.1--0
I

0-,-1. ___ -'

O-~-.f-- .. , :
o-~- ~ ___ ",o-~--o
,

I

';--r- ..J
V-

7~
--:

91
---I

-~-~>------=---------------.
FIGURE 12 - SLEW RATE versus CAPACITANCE
FOR ISC

= 10 mA
would be excessive. Therefore, if the system is designed to permit
low impedances to ground at the power-supplies of the drivers, a
diode should be placed in each power-supply lead to prevent overheating in this fault condition. These two diodes, as shown in
Figure 13, could be used to decouple all the driver packages in a
system. (These same diodes will allow the MC1488L to withstand
momentary shorts to the ±25-volt limits specified in the earlier
Standard RS232B.l The addition of the diodes also permits the
MC14B8L to withstand faults with power-supplies of less than the
9.0 volts stated above.
The maximum short-circuit current allowable under fault conditions is more than guaranteed by the previously mentioned
10 rnA output current limiting.

1000

""
-&

100

~

=

30 VI",

0

2w

~

~

I
I

10

3U,r F
I
1.0
1.0

10

100

11111
1000

10,000

C, CAPACITANCE (pF)

fast for this requirement. The current limited output of the device
can be used to control this slew rate by connecting a capacitor to
each driver output. The required capacitor can be easily determined
by using the relationship C = ISC x /).T//j. V from which Figure 12 is
derived. Accordingly. a 330 pF capacitor on each output will
guarantee a worst case slew rate of 30 volts per microsecond.
The interface driver is also required to withstand an accidental
short to any other conductor in an interconnecting cable. The worst
possible signal on any conductor would be another driver using a
plus or minus 15 volt, 500 mA source. The MC14B8L is designed
to indefinitely withstand such a short to all four outputs in a package as long as the power-supply voltages are greater than 9.0 volts
Ii.e., V+::'9.0 V; V-"-9.0 V). In some power·supply designs, a loss

of system power causes a low impedance on the power-supply outputs. When this occurs, a low impedance to ground would exist at
the power inputs to the MC1488L effectively shorting the 30G-ohm
output resistors to ground. If all 'four outputs were then shorted
to plus or minus 15 volts. the power dissipation in these resistors

Other Applications
The MC14BBL is an extremely versatile line driver with a myriad
of possible applications. Several features of the drivers enhance
this versatility:
1. Output Current Limiting - this enables the circuit designer
to define the output voltage levels independent of power-supplies
and can be accomplished by diode clamping of the output pins.
Figure 14 shows the MC14B8L used as a OTL to MOS translator
where the high-Jevel voltage output is clamped one diode above
ground. The resistor divider shown is used to reduce the output
voltage below the 300 mV above ground MOS input level limit.
2. Power-Supply Range - as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements
of the device are essentially independent and do not require matching power-supplies. In fact, the positive supply can vary from a
minimum seven volts (required for driving the negative pulldown
section) to the maximum specified 15 volts. The r.eg~tivc supply
can vary from approximately -2.5 volts to the minimum specified
-15 volts. The MC1488L will drive the output to within 2 volts of
the pOSitive or negative supplies as long as the current output limits
are not exceeded. The combination of the current-limiting and
supply-voltage features allow a wide combination of possible outputs within the same quad package. Thus if only a portion of the
four drivers are used for driving RS232C lines. the remainder could
be used for DTL to MOS or even DTL to DTL translation. Figure 15
shows one such combination.

7-118

MC1488L (continued)

FIGURE 14 - MDTL/MTTL-TO-MOS TRANSLATOR

FIGURE 15 - LOGIC TRANSLATOR APPLICATIONS

+12V
MOTL 2
INPUT

lo---'---'V1"kv---t--·

MOS OUTPUT
IWITH VSS· GNO)

10 k

-12V

-12 V

MOTL ~-'-r---..
MHTL
INPUT 10-;--<--"

MHTL OUTPUT

P-+-o---.---- -0.7 v to 10 V

°

12
MOTL n....-l-r---..

~N~3~

P-+-o-.-'IN',..--1o--_
13

10 k

-12V

7-119

+12V

MOS OUTPUT
-10 v to 0 V

\ . LINEAR/DIGITAL INTERFACE CIRCUITS

MC1489L
MC1489AL

QUAD MDTL
LINE RECEIVERS
RS-232C

QUAD LINE RECEIVERS

INTEGRATED CIRCUIT
The MC1489 monolithic quad line receivers are designed to interface data terminal equipment with data communications equipment
in conformance with the specifications of E IA Standard No. RS-232C.

lOGIC DIAGRAM

•

Input Resistance - 3.0 k to 7.0 kilohms

•

Input Signal Range -±30 Volts

•

Input Threshold Hysteresis Built In

•

Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering

1~313~11

2~

12~

45~6
~

Vee --.------<014

-1-,----<0

'~y8
CIRCUIT SCHEMATIC 11/4 OF CIRCUIT SHOWN)
14

Vee
5k

9k

1.6 k

RF
RESPONSE CONTROL 2

3 OUTPUT

3.55 k

I'---

INPUT 1 "-

I'---

10 k
MC1489L
RF lOkn

MC14 89Al
2k Q

7 GROUND

TYPICAL APPLICATION
LINE RECEIVER
MC1489l

LINE DRIVER
MC148Bl

S--,

---i

- Ir

INTERCONNECTING

Mon LOGIC INPUT

I

CABLE

I

- - J . - MOll lOGIC OUTPUT

I

CERAMIC PACKAGE
CASE 632

TO-llG

See Packaging Information Section for outline dimensions.

7-120

7

MC1489L, MC1489AL (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted I
Symbol

Value

Unit

Power Supply Voltage

VCC

10

Vdc

I nput Signal Range

Vin

±30

Vdc

IL

20

mA

Po
1MJA

1000
6.7

mW
mW/oC

TA

o to +75

T stg

-65 to +175

uc
vc

Rating

Output Load Current
Power Dissipation (Package Limitation, Ceramic Dual I n-Line Package)

Derate above T A = +25 0 C

Operating Temperature Range
Storage Temperature Range

E lECTR ICAl CHARACTER ISTICS (Response control pin is open.1 (VCC = +5.0 Vdc ± 1 %, T A = 0 to +75 0 C unless otherwise noted I
Figure

Symbol

Min

Typ

Max

Unit

(Vin = +25 Vdcl
(Vin = +3.0 Vdcl

1

IIH

3.6
0.43

-

8.3

mA

(Vin = -25 Vdcl
(Vin ~ -3.0 Vdcl

1

-3.6
-0.43

-

-8.3

-

-

-

1.5
2.25

Characteristics
Positive I nput Current

Negative Input Current

2

Input Turn-On Threshold Voltage
(T A = +25 0 c, Va L ,;; 0.45 VI

IlL

1.0
1.75
2

Output Voltage High

(Vin ~ 0.75 V, IL ~ -0.5 mAl
(Input Open Circuit, IL ~ -0.5 mAl

Output Voltage Low

IVin ~ 3.0 V, IL ~ 10 mAl

Output Short-Circuit Current

1.95

Vdc

VIL

MC1489L
MC1489AL

mA
Vdc

VIH

MC1489L
MC1489AL

Input Turn·Off Threshold Voltage
IT A ~ +25 0 C, VOH :;" 2.5 V, I L = -0.5 mAl

-

-

0.75
0.75

0.8

1.25
1.25

2.6
2.6

4.0
4.0

5.0
5.0

Vdc

2

VOH

2

VOL

-

0.2

0.45

Vdc

3

-

3.0

-

mA

-

20

26

mA

Power Supply Current

(Vin ~ +5.0 Vdcl

4

ISC
1+

Power Dissipation

(Vin ~ +5.0 Vdcl

4

Po

-

100

130

mW

5

tPLH

-

25

85

ns

SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc ± 1%, T A ~
Propagation Delay Time

(RL=3.9kl1l

+250

CI

Rise Time

(RL = 3.9 kl1l

5

tr

-

120

175

ns

Propagation Delay Time

(RL - 390 111

5

tPHL

-

25

50

ns

Fall Time

(RL - 390 111

5

tf

-

10

20

ns

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-121

I

MC1489L, MC1489AL (continued)

TEST CIRCUITS

FIGURE 1 - INPUT CURRENT

FIGURE 2 - OUTPUT VOLTAGE
and INPUT THRESHOLD VOLTAGE

•

OPEN

11

13

FIGURE 4 - POWER-SUPPLY CURRENT

FIGURE 3 - OUTPUT SHORT -CIRCUIT CURRENT

VCC

11

FIGURE 5 - SWITCHING RESPONSE

I

+5

VRd:lh.L

Ein

FIGURE 6 - RESPONSE CONTROL NODE

1

All diodes
MC833
orequiv

-D------4"t>----r..--.. . .

c.

Eo

::r

T

1/4
MC1489A

tr and t1

RESPONSE NODE
~------------eVO

measured
EO

10% - 90%

C, capacitor is for noise filtering.
R, resistor is for threshold shifting.

1.5 V

CT

= 15 pF = total parasitic capacitance, which includes
probe and wiring capacitances

7-122

MC1489L, MC1489AL (continued)

TYPICAL CHARACTERISTICS

= 5.0 Vdc, T A = +250 C unless otherwise noted)

(Vee

FIGURE 8 - MC1489 INPUT THRESHOLD
VOLTAGE ADJUSTMENT

FIGURE 7 - INPUT CURRENT
6. 0

+10
+8.0
~

.s
I-

~

./

+6.0

+2.0

1-

-4.0

;:,

-6.0

o
>
~

""Y

./'

/
fo""

-8.0

I

-10
-25

-20

-15

-10

-5.0

+5.0

f-RT

f-f--

~ 3. o f-5k

,,- V

I

I

I

+10

+15

+20

I- V,h f-

2.

o 1-+5 V f-

RT
13 k
V,h
+5 V

5
c3
>

w

3.0

-RT
_5k

2.0

-V'h
+5 V

OJ

«

~

0

>
I-

5:

RT
~

-

RT
11k
V,h
-5 V

+25

-3.0

0

c3
>

1.0

1

1
1

I

I

.f

I-

2.4
2.2

~
w

1.6

0

>

:l
0

ttl

'"
l:I:

--

. -.1-VIL -VIH

5:

--

;:,
~

J
-3.0

1.8

~

«

V,h

-2.0

-1.0

+1.0

+2.0

+3.0

2.0

OJ

I-

-

-2.0

:i

->

+4.0

1.4
1.2

-

-

r---

-

-

~

+2.0

+3.0

-

MC1489A VIH

r---

~

0.8
MC1489 VIL

0.6

j

0.4

'I'
+60

T, TEMPERATURE 10C)

VIH MC148SA

w

OJ

«

~

0

1.0 I-- VIH MC1489
VIL MC1489
f--VIL MC1489A

lI-

5:

;:,

8.0

VCC, POWER SUPPL Y VOLTAGE IV de)

7-123

MC14~9A

VIL 1

0.2
-60

4.0

=

MC1489 VIH

2:

ttl
'"
'"

.f

1.0

~

:l
0

-

=-V'h_

fo-

,,'-

FIGURE 11 -INPUT THRESHOLD versus
POWER,SUPPLY VOLTAGE

>

-

RT-

VIL VIH

+1.0

-1.0

Vin,lNPUT VOLTAGE IVde)

2.0

I-I--

y=

FIGURE 10 - INPUT THRESHOLD VOLTAGE
versus TEMPERATURE

RT

:::>

V,h
-5 V

-

"-

0

Y

2: 4.0

I--

I-- 11k I - -

Vin,lNPUT VOLTAGE IVde)

"

:g

RT

f--

~

1.0

FIGURE 9 - MC1489A INPUT THRESHOLD
VOLTAGE ADJUSTMENT

5.0

RT

I-

Vin, INPUT VOLTAGE (VOLTS)

6.0

I

4 .0

w
OJ

/~

I-

-2.0

2:

.....V

a:
:::>
'-'
~

:g

/

+4.0

"

5.0

12

+120

MC1489L, MC1489AL (continued)

APPLICATIONS INFORMATION

General Information
The Electronic Industries Association (E IA) hasreleasedthe AS-232C
specification detailing the requirements for the interface between
data processing equipment and data communications equipment.
This standard specifies not only the number and type of interface
leads, but also the voltage levels to be used. The MC1488L quad
driver and its companion circuit, the MC1489L quad receiver,
provide a complete interface system between DTL or TTL logic
levels and the AS-232C defined levels. The AS-232C requirements
as applied to receivers are discussed herein.
The required input impedance is defined as between 3000 ohms

and 7000 ohms for input voltages between 3.0 and 25 volts in
magnitude; and any voltage on the receiver input in an open circuit

condition must be less than 2.0 volts in magnitude. The MC1489
circuits meet these requirements with a maximum open circuit voltage of one VBE (Aef. Sect. 2.41.
The receiver shall detect a voltage between -3.0 and -25 volts
as a logic "1" and inputs between +3.0 and +25 volts as a logic "0"
(Ref. Sect. 2.3). On some interchange leads, an open circuit or
power "OFF" condition (300 ohms or more to ground) shall be
decoded as an "OFF" condition or logic "1" (Aef. Sect. 2.51. For
this reason, the input hysteresis thresholds of the MC1489 circuits
are all above ground. Thus an open or grounded input will cause
the same output as a negative or logic "1" input.

Device Characteristics
The MC1489 interface receivers have internal feedback from the
second stage to the input stage providing input hysteresis for noise

reiection. The MC1489L input has typical turn-on voltage of 1.25
volts and turn-off of 1.0 volt for a typical hysteresis of 250 mV.
The MC1489AL has typical turn-on of 1.95 volts and turn-off of
0.8 volt for typically 1.15 volts of hysteresis.
Each receiver section has an external response control node in
addition to the input and output pins, thereby allowing the designer to vary the input threshold voltage levels. A resistor can be
connected between this node and an external power-supply. Figures 6, 8 and 9 illustrate the input threshold voltage shift possible
through this technique.
This response node can also be used for the filtering of highfrequency, high-energy noise pulses. Figures 12 and 13 show
typical noise-pulse rejection for external capacitors of various sizes.
These two operations on the response node can be combin.ed
or used individually for many combinations of interfacing applications. The MC1489 circuits are particularly useful for interfacing
between MOS circuits and MDTLlMTTL logic systems. In this
application, the input threshold voltages are adjusted (with the
appropriate supply and resistor valuesl to fall in the center af the
MOS voltage logic levels. (See Figure 14)
The response node may also be used as the receiver input as
long as the designer realizes that he may not drive this node with
a low impedance source to a voltage greater than one diode above
ground or less than one diode below ground. This feature is
demonstrated in Figure 15 where two receivers are slaved to the
same line that must still meet the RS-232C impedance requirement.

FIGUAE 13 - TUAN-ON THRESHOLD versus CAPACITANCE
FROM RESPONSE CONTAOL PIN TO GND

FIGUAE 12 - TUAN-ON THAESHOLD versus CAPACITA-NCE
FROM RESPONSE CONTROL PIN TO GND

10

100

1000

10,000

10

100

1000

PW, INPUT PULSE WIDTH (ns)

PW, INPUT PU LSE WIDTH (ns)

7-124

10,000

MC1489L, MC1489AL

(continued)

APPLICATIONS INFORMATION

(continued)

FIGURE 14 - TYPICAL TRANSLATOR APPLICATION MOS TO DTL OR TTL
+5 Vdc

,...-- ,

---I

I

L. __ '

OTl or TTL

r- -,

-_J

)

+5VdC~-+
FIGURE 15 - TYPICAL PARALLELING OF TWO MC1489,A RECEIVERS TO MEET RS·232C
VCC

RESPONSE·CONTROl PIN
INPUT

r------------ - - - - - l
1/2 MCI489

9k

2k

OUTPUT

8k

4.2 k

VCCO-~----------------,

2k
INPUT L....__

-'\8"ktv-~>_+----------.....--t'Vvv-H

RESPONSE·CONTROl PIN

4.2 k

7-125

OUTPUT

MC1506L
MC1406L

~~_______________D_"T_O_-_A_C_O_N_V__E_R_T_E_R~

Specifications and Applications
InforD1.ation

SIX BIT, MUL TIPL VING
01 G IT AL-TO-ANALOG
CONVERTER
MONOLITHIC
SILICON INTEGRATED CIRCUIT

MONOLITHIC SIX BIT, MUL TIPL VING
OIGITAL-TO-ANALOG CONVERTER

I.

... designed for use where the output current is a linear product
of a six-bit digital word and an analog input voltage.

1

•

Digital I nputs are MDTl and MTTl Compatible

•

Relative Accuracy - ±0.78% Error maximum

•

low Power Dissipation - 85 mW typical

•

Adjustable Output Current Scaling

•

Fast Settling Time - 150 ns typical

@

'.

CJ
"

.....

±5.0 V

• Standard Supply Voltage: +5.0 V and -5.0 V to -15 V

CERAMIC PACKAGE
CASE 632

TO·116

FIGURE 1 - OUTPUT CURRENT SETTLING TIME
IALL BITS SWITCHED, RL = 50.n)

FIGURE 2 - D·to-A TRANSFER CHARACTERISTICS

2.0V
OV

ornA

1.0 rnA

2.0 rnA

I

(000000)

100 ns/DIV.

INPUT WORD

TYPICAL APPLICATIONS
•
•

Tracking A-towD Converters
Successive Approximation A-to-D Converters

•
•

Digital-ta-Analog Meter Readout
Sample and Hold

•

Peak Detector

•
•

•

•

Stepping Motor Drive

•

CRT Character Generation

Programmable Gain and Attenuation
Digital Varicap Tuning

•
•
•
•
•

Digital Addition and Subtraction
Analog-Digital Multiplication
Digital-Digital Multiplication
Analog-Digital Division
Programmable Power Suppl ies

Video Systems

•

Speech Encoding

See Packaging I nformation Section for outline dimensions.

(MC1506 - Page 11

7-126

(111111)

MC1506L, MC1406L (continued)

MAXIMUM RATINGS (TA

= +25 0 C unless otherwise noied.)

Symbol

Value

Unit

Power Supply Voltage

VCC
VEE

+5.5
-16.5

Vdc

Digital Input Voltage

Rating

V5 thru VlO

+8.0, VEE

Vdc

Applied Output Voltage

Vo

±5.0

Vdc

Reference Current

'12

5.0

rnA

V12, V13

VCC, VEE

Vdc

1000
6.7

rnW
mW/oC

-55 to +125
o to +75

°c

-65 to +150

°c

Reference Amplifier Inputs

Power Dissipation (Package limitation)

Po

Ceramic Package

Derate above T A

= +25 0 C

Operating Temperature Range

TA
MCI506L
MCI406L

Storage Temperature Range

T stg

~ef = 2.0 mA, TA = T,ow'

ELECTRICAL CHARACTERISTICS (VCC = +5.0 Vdc, VEE = -15 Vdc,
All digital inputs at low logic levels I

Characteristic
Relative Accuracy (Error relative to full scale 101

Settling Time (within 1/2 LSB [includes ldl T A

Figure

Symbol

Min

Typ

Max

10

Er

-

-

±0.78

%

9

ts

-

150

300

I\S

9

tPHL,
tPLH

-

10

50

ns

ITClol

-

80

VIH
VIL

2.0

-

-

-

-

-

0.8
0.5

IIH
I·

-

0
-0.7

+0.01
-1.5.

-

-0.002

-0.01

0
0

2.0
2.0

2.1
4.2

1.9

1.97

2.1

-

0

10

-

-

±0.4

-

2.0

-

PSRR (-I

-

0.002

0.010

ICC
lEE

-

+7.2
-9.0

+11
-11

-

85
175

120
240

= +25 0 CI

Propagation Delay Time

TA

= +25 0 C

Output Full Scale Current Drift
Digital Input Logic Levels

Digital Input Current

Vdc·

3,13

High Level, VIH = 5.0 V
Low Level, VI L = 0.8 V

mA

Reference I nput Bias Current (Pin 13)

3

113

Output Current Range
VEE = -5.0 V
VEE = -6.0 to -15 V

3

lOR

Output Current

3

= 2.000 V, R12 = 1.000 kn

Output Current
(all bits high)

3

Output Voltage Compliance

(E r <;;±0.78% at TA

3,4,5

= +25 0 CI

Reference Current Slew Rate

(TA

8,15

= +25 0 CI

Output Current Power Supply Sensitivity

10

Power Supply Current

Al thru AS; VIL
Al thruA6; V,H

Power Dissipation (all bits highl
VEE = -5.0 Vdc
VEE = -15 Vdc

10

mA

lo(min)

I'A

Vo

Vdc

SR Iref

mAIl's

(MC1506 -- Page 2)

7-127

mAN
mA

Po

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.
'Thigh = +75 0 C for MCI406L
T,ow = oDc for MCI406L
= +125 0 C for MCI506L
= -55 0 C for MCI506L

mA
mA

3,11,12

= 0.8 V
= 2.0 V

Unit

PPM/oC

3,14

High Level, Logic "I" (MCI406L, MCI506L)
Low Level, Logic "0" (MCI406L)
(MCI506L)

Vref

to Thigh' unless otherwise noted.

12

mW

•

MC1506L, MC1406L

(continued)

The MC1506L consists of a reference current amplifier,
and R-2R ladder, and six high-speed current switches_ For
many applications, only a reference resistor and a reference
supply voltage need be added.
The switches are inverting in operation, therefore a low
state at the input turns on the specified output current
component. The switches use a current steering technique
for high speed and a termination amplifier that consists of
an active load gain stage with unity gain feedback. The
termination amplifier holds the parasitic capacitance of the
ladder at a constant voltage during switching and provides
a low impedance termination of equal voltage for all legs
of the ladder.
The R-2R ladder divides the reference amplifier current
into binarily-related components which are fed to the
switches. Note that there is always a remainder current
that is equal to the least significant bit. This current is
shunted to ground, and the maximum current is 63/64 of
the reference amplifier current, or 1.969 mA for a 2.0 mA
reference current if the NPN current source pair is
perfectly matched.

BLOCK DIAGRAM
MSB
Al

A2

A3

A4

AS

lSB
AS

REFERENCE
CURRENT

H

BIAS CIRCUIT

AMPLIFIER

Vrefo--+-~

NPN CURRENT
SOURCE PAIR

COMPLETE CIRCUIT SCHEMATIC
(Digital Inputs; pins 5,6,7,8,9,10)
lSB

MSB
A 5

A2 S

L.

l.

"'U -

4k

c-

A4 8

A3 7

"'4k

l.
r"

f--

tf~ f ~ ~
CURRENT

R-2R
LADDER

BOD

800

..c..

Vref (":")

/,

12

400

.

~

r

.

~~

(compensation)

y

--<

800
400

20k

"f

I-"

,.5kf

I

100

I

L

13
14 Vrefl)
-

IMC1506 - Page 3)

7-128

'"

N H

Vee

~

l.

.--l

f~ ~

800
400

5.6k

400

l.
I--

I

~

~

-

---<

400

~

CURRENT
AMPLIFIER

r" 4 k

800

400

REFERENCE

l.

r1k

~ f.

BOD

400

'"'

y f
K

~

K

l.
!--

*

SWITCHES

4k

veer"

AS 10

A5 9

Pin I no connection.
BIAS
CIRCUIT

2

-

BOO

OUTPUT

4
I

MC1506L, MC1406L (continued)

TEST CIRCUITS AND TYPICAL CHARACTERISTICS
FIGURE J - NOTATION DEFINITIONS TEST CIRCUIT

FIGURE 4 - OUTPUT CURRENT versus OUTPUT VOL TAGE

Vee

~ lee

,

II
RI2

I--!!'O-:=------'Wv--.-_

Al

.0Vref

L~W

Al =
A2-A6 ~ High

A2
DIGITAL
INPUTS

Mel506L
Mel406L

A3
A4

r

I

6-BitAccuracy
@2s oe
0

R12" RI3

/'

/

AS

I--'O--::---;-:---.......-=--....

+, ~L---r-----'

A6

10

j

OUTPUT
0

:

Vin

--!-

-2.0
ID ~

VI and II apply to inputs Al
thru AS

-1.5

-1.0

-0.5

+0.5

+1.5

+1.0

+2.0

VO. OUTPUT VOLTAGE PIN 4lVdc)

KJiU
~+g+~
+~} ~ K{Po}
1 2 +~+
4
B 16 32 64

~;~
AN = 0 jf AN isat high Jevel

whereK:!
and

AN = 1 if AN is at low level
FIGURE 6 - POSITIVE Vref

FIGURE 5 - MAXIMUM OUTPUT VOLTAGE
versus TEMPERATURE
Vec

+1. 0

~

+0. 6

...z

~

+0.4

~
o

0

;: -0. 2
~
~

\

\\\

-0.4

o

ci -0. 6
>

\

A2

\ 1\ \ '\ :-\h

Allowable Range
\
"or G-Bit Accuracy \

\ 1\
\ \ f\\ 1\ \
".y ~ ~

AS
A6

vref..I"L

14

Mel50BL
Mel406L

A4

~ ~ f-'""""

1+)

13

A3

\\ \
\ 1\ \

RI2

12

Al

r-.--

\

\

0:
~ +0.2

R12" RI3

11

+0. B

-=-

Ne

10

RL

-10

"""l..J

-O.B

-=-

-1.0
-55

+50

+100

VEE

+150

T, TEMPERATURE laC)

FIGURE 8 - REFERENCE CURRENT SLEW RATE
MEASUREMENT TEST CIRCUIT

FIGURE 7 - NEGATIVE Vref

Vee

Vee
R12" R13

11
12

_

11

R12

Al
A2

13

A3

Me1506L
Me1406L

A4
A5
AB

12

Al
A2

See text for values of C.

Me1506L
Me1406L

A4

14 20 pF
1k

f--:--':'O-----,

A5
10

J"C.~.OV

13

A3

14

1k

Ne

10

A6

-=VEE

(MC1506 - Page 4)

7-129

-=-

Slewing
Tim.

Jvr=-L=-~.o
.

mA

MC1506L, MC1406L (continued)
TEST CIRCUITS and TYPICAL CHARACTERISTICS (continued)
FIGURE 9 - TRANSIENT RESPONSE

2.4V

2.0 Vdc
11
1k

12

0.1

13
1k

14
MC150SL

0.4 v-l--~:::::::::~-1,= 11,,10 ns

~F

-=

50 pF

51

-=

10

'0

-= -=

'0

NC

50%

50%

-100 mV
tPHL

FIGURE 10 - RELATIVE ACCURACY TEST CIRCUIT

Al
A2
A3
A4
AS
AS

MSB
12·Bit D-to-A Converter

.....
":"

50 k

A7Y AB

A9?AIO All?AI2

L

",FI
S·BfT
COUNTER

CAL
100

--0--

VCC

950
RI2
MSB
5
S
7
B
9
10

HEX
INVERTER

LSB

*

Vref =+2.0 V

LSB

11

12

~

ERROR
1.0 V= 1%

+

2k
":"

MCI50SL
MCI40SL

14
13
t~

4

3

2

61
NC

20 pF I k
":"

":"

VEE
FIGURE 12 - TYPICAL POWER SUPPLY CURRENT versus VEE

FIGURE 11- TYPICAL POWER SUPPLY CURRENT
versus TEMPERATURE

10

IS

i-V CC L5.0 V

14

<"

13

!2:

12

.§
w

11

'"'

10

::>

8: 9.0
~

IX:

B.O

~

7.0

w

9.0

Z

W
IX:
IX:

::>

I--

~ 7.0

IX:
W

-

S.O
-55 0 C

B.O

~

1--___
1-~lIbitsl~

5.0

IEEICC-

'"'

I:.z.' bits hig1h

+ 50 0 C

;0

-

lEE
ICC

~ S.O

+ 1000C +125 0C

5.0

--- ----!---

I-

IX:
IX:

~

<"
.§

Vcc = +5.0 V
VEE=-15V

o

-4.0

..... AII bilshigh

f.---

-S.O

-B.O

-10

-12

/ . All bits low

-14

VEE, NEGATIVE POWER SUPPLY (Vdc)

T, TEMPERATURE (OC)
(MC1506 - Page 51

7-130

-IS

"

MC1506L, MC1406L (continued)

GENERAL INFORMATION

TYPICAL CHARACTERISTICS (continued)
FIGURE 13 - LOGIC INPUT CURRENT versus INPUT VOLTAGE

Output Current Range
The output current maximum rating of 4,2 mA may be
used only for negative supply voltages below -6,0 volts,
due to the increased voltage drop across the 400-ohm
resistors in the reference current amplifier.

1. 0

\

0'

so. 8
~
~

~

G o. 6

~
z
w

>

\

\
\

o. 4

~z o.

Output Voltage Compliance

\

2

The MC1506L current switches have been designed for
high-speed operation and as a result have a restricted output voltage range, as shown in Figures 4 and 5. When a
current switch is turned "off", the follower emitter is
near ground and a positive voltage on the output terminal
can turn "on" the output diode and increase the output
current level. When a current switch is turned "on", the
negative output voltage range is restricted. The base of
the termination circuit Darlington amplifier is one diode
voltage below ground; thus a negative voltage below the
specified safe level will drive the low current device of the
Darlington into saturation, decreasing the output current
level.
For example, at +25 0 C the allowable voltage compliance
on pin 4 to maintain six-bit accuracy is ±0.4 volt. With a
full scale output current of 2.0 mA, the maximum resistor
value that can be connected from pin 4 to ground is
200 ohms.

\

1\

0_--1.

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Vin. LOGIC INPUT VOLTAGE (Vdc)

FIGURE 14 - MSB TRANSFER CHARACTERISTICS
versus TEMPERATURE (MSB IS "WORST CASE")
1.4
1.2

0'

s

~
~

~

1.0

'\

\

=>

'"f-

0.6

~

0.4

~

9

'\

t125 0 C\ +75 OC\+25 0 C\

0.8

\

0.2

\
\
\
\ \
\
\
\
\ \
\

\
\
\
\
'\

o

o

0.2

0.4

\ -55°C

\

\

1\
\

1\
\OOC

.'.

\

'--'"

\

\.

1.2
1.4
1.6
Vin, LOGIC INPUT VOLTAGE (Vdc)

0.6

0.8

1.0

Accuracy
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full scale current. The relative accuracy of
the MC1506L is essentially constant with temperature due
to the excellent temperature tracking of the monolithic
resistor ladder. The reference current may drift with
temperature, causing a change in the absolute accuracy
of output current.

1.8

2.0

FIGURE 15 - REFERENCE INPUT FREQUENCY RESPONSE
+2.0

A

I I 1111111
I I I III [II

::7"'\1
r-.

Unless otherwise specified:
R12" R13" 1.0k!'l
Ao--IC\
RL" 50 !'l(pin 4 to GNO)
~
Curve A: Large Signal Bandwidth
111\\
~ -4.0
(Method of Figure 6)
Vref" 2.0 V(p·p) offset 1.0 V above GNO \
!;
o -6.0 Curve B: Small Signal Bandwidth
w
(Method of Figure 6)
\
>
;::
Vref ==50 mV{p-p) offset 200rnVaboveGND
~ -8.0 Curve C: large and Small Signal Bandwidth
(Method of Figure 22with no op-ampl, RL=50n)
RS" RL" 5011
- 10
-2.0

Vref

-12
0.01

11111

=2.0 V

VS" 120 mV(pp) centered at 0 V
0.1
0.02
0.2

IIIII
1.0

I
I
I
~

The best temperature performance is achieved with a
-6.0 V supply and a reference voltage of -3.0 volts. These
conditions match the voltage across the NPN current source
pair in the reference amplifier at the lowest possible voltage, matching and optimizing the output impedance of
the pair.
The MC1506L1MC1406L is guaranteed accurate to within ±1/2 LSB at +25 0 C at a full scale output current of
1.969 mAo This corresponds to a reference amplifier output current drive to the ladder of 2.0 mA, with the loss of
one LSB ~ 31 fJA that is the ladder remainder shunted to
ground. The input current to pin 12 has a guaranteed
current range value of between 1.9 to 2.1 mA, allowing

1\
\

2.0

5.0

10

f, FREUUENCY (MHz)

(MC1506 - Page 6)

7-131

•

MC1506L, MC1406L (continued)

GENERAL INFORMATION (continued)

some mismatch in the NPN current source pair. The
accuracy test circuit is shown in Figure 10. The 12-bit
converter is calibrated for a full scale output current of
1.969 mAo This is an optional step since the MC1506L
accuracy is essentially the same between 1.5 to 2.5 mAo
Then the MC1506L full scale current is trimmed to the
same value with R 12 so that a zero value appears at the
error amplifier output. The counter is activated and the
error band may be displayed on an oscilloscope, detected
by comparators, or stored in a peak detector.
Two 6-bit D·to-A converters may not be used to construct a 12-bit accurate D-to-A converter. 12-bit accuracy
implies a total error of ±1/2 of one part in 4096, or
±D.012%, which is more accurate than the ±O. 78% specification provided by the MC1506L.

around circuit or current mirror for feeding the ladder.
The reference amplifier input current, 112, must always
flow into pin 12 regardless of the setup method or reference
voltage polarity.
Connections for a positive reference voltage are shown
in Figure 6. The reference voltage source supplies the full
current 112. Compensation is accomplished by Miller feedback from pin 14 to pin 13. This compensation method
yields the best slew rate, typically better than 2.0 mA/lls,
and is independent of the value of R 12. R 13 must be used
to establish the proper impedance for compensation at
pin 13. For bipolar reference signals, as in the mUltiplying
mode, R 13 can be tied to a negative voltage corresponding
to the minimum input level. Another method is shown
in Figure 22.
It is possible to eliminate R 13 with only a small sacri·
fice in accuracy and temperature drift. For instance when
high-speed operation is not needed, a capacitor is connected
from pin 14 to VEE. The capacitor value must be increased
when R 12 is made larger to maintain a proper phase
margin. For R 12 values of 1.0, 2.5, and 5.0 kilohms,
minimum capacitor values are 50, 125, and 250 pF.
Connections for a negative reference voltage are shown
in Figure 7. A high input impedance is the advantage of
this method, but Miller feedback cannot be used because
it feeds the input signal around the PNP directly into the
high impedance node, causing slewing problems and high
frequency peaking. Compensation involves a capacitor
to VEE on pin 14, using the values of the previous paragraph. The negative reference voltage must be at least
3.0 V above VEE. Bipolar input signals may be handled
by connecting R 12 to a positive reference voltage equal to
the peak positive input level at pin 13.
When a dc reference voltage is used, capacitive bypass
to ground is recommended. The 5.0 V logic supply is not
recommended as a reference voltage. If a well regulated
5.0 V supply which drives logic is to be used as the reference, R 12 should be decoupled by connecting it to +5.0 V
through another resistor and bypassing the junction of
the two resistors with 0.1 IlF to ground. For reference
voltages greater than 5.0 V, a clamp diode is recommended
between pin 12 and ground.
If pin 12 is driven by a high impedance such as a
transistor current source, none of the above compensation
methods apply and the amplifier must be heavily compensated, thus decreasing the overall bandwidth.

Multiplying Accuracy
The MC1506L may be used in the multiplying mode
with six-bit accuracy when the reference current is varied
over a range of 64: 1. The major source of error is the
bias current <>f the termination amplifier. Under "worst
case" conditions these six amplifiers can contribute a total
of 6.0 IlA extra current at the output terminal. If the
reference current in the multiplying mode ranges from
60 IlA to 4.0 mA, the 6.0 IlA contributes an error of
0.1 LSB. This is well within six-bit accuracy.
A monotonic converter is one which supplies an increase
in current for each increment in the binary word. Typically, the MC1506L is monotonic for all values of reference
current above 0.5 mAo The recommended range for
operation with a dc reference current is 0.5 to 4.0 mAo
Settling Time
The "worst case" switching condition occurs when all
bits are switched "on", which corresponds to a high-to-Iow
transition for all bits. This time is typically 150 ns to
within ±1/2 LSB, while the turn "off" is typically under
50 ns.
The s!mrJcst single $'v~.:itch is the least significant bit,
which turns "on" and settles in 50 ns and turns "off" in
30 ns. I n applications where the D-to-A converter functions in a positive-going ramp mode, the "worst case"
switching condition does not occur, and a settling time
of less than 150 ns may be realized.
Reference Amplifier Drive and Compensation
The reference amplifier provides a voltage at pin 12 for
converting the reference voltage to a current, and a turn-

(MC1506 - Page 7)

7-132

MC1506L, MC1406L

(continued)

APPLICATIONS INFORMATION
FIGURE 16 - OUTPUT CURRENT VOL TAGE CONVERSION
VCC
II
RI2
f-....:.::.o---~vylr----1>-_Vref

MSB Al

Vref =2.0 Vde
R12= R13", 1.0kn
RO=5.0kn

A2
MCI506L
MCI406L

A3

Theoretical

1) Adjust Aref so that

Vo =H15

-

A5
10

KRol1A}

Va with all digital inputs at

low level is equal to 9.844 volts.

RO

A4

LSB A6

Va

Vf
-----Vo = -"'-IRoll!ll +~+ ~ +M +~+~I=
RI2
2
4 B 16 32 64

KII~+~+i+~+ ~ +s'41 = 10 V I~I =9.644 V

10

VEE

An alternative method is to use the MC1539G and input
compensation. Response of this circuit is also on the
order of 2.0 /lS. See Motorola Application Note AN-459
for more details on this concept.
Voltage· outputs of a larger magnitude are obtainable
with this circuit which uses an external operational amplifier as a current to voltage converter. This configuration
automatically keeps the output of the MC1506L at ground
potential and the operational amplifier can generate a
positive voltage limited only by its positive supply voltage.
Frequency response and settling time are primarily determined by the characteristics of the operational amplifier.
In addition, the operational amplifier must be compensated
for unity gain, and in some cases overcompensation may
be desirable.
Note that this configuration results in a positive output
voltage only, the magnitude of which is dependent on
the digital input.
The following circuit shows how the MLM301AG can
be used in a feedforward mode resulting in a full scale
settling time on the order of 2.0 /lS.

FIGURE 18
VCC
+15 V

35 pF

5k
10 k

ITo pin 4

>---<>--__ Vo

of MCI506LI

240

The positive voltage range may be extended by cascoding the output with a high beta common base transistor, Q1, as shown.
VCC

FIGURE 17
65 pF

5.1 k
Ge

10

(!; ~~1~06Ll ...- -.....-

....-0---1

IJ>--o---_ vo

The output voltage range for this circuit is 0 volts to
BVCBO of the transistor. Variations in beta must be
considered for wide temperature range applications. An
inverted output waveform may be obtained by using a
load resistor from a positive reference voltage to the
collector of the transistor. Also, high-speed operation is
possible with a large output voltage swing.

IMC1506 - Page 8)

7-133

•

MC1506L, MC1406L

(continued)

APPLICATIONS INFORMATION (continued)
Bipolar or Negative Output Voltage

Combined Output Amplifier and Voltage Reference

For many of its applications the MC1506L requires a
reference voltage and an operational amplifier. Normally
the operational amplifier is used as a current to voltage
converter and its output need only go positive, with the
popular MCl723G voltage regulator both of these functions
are provided in a single package with the added bonus of
up to 150 mA of output current, see Figure 19. Instead
of powering the MCl723G from a single positive voltage
supply, it uses a negative bias as well. Although the refer·
ence voltage of the MCl723G is then developed with
respect to that negative voltage it appears as a commonmode signal to the reference amplifier in the D-to·A converter. This allows use of its output amplifier as a
classic current-to·voltage converter with the non-inverting
input grounded.
Since ±15 V and +5.0 V are normally available in a
combination digital·to-analog system, only the -5.0 V
need be developed. A resistor divider is sufficiently accu·
rate since the allowable range on pin 5 is from -2.0 to
-S.O volts. The 5.0 kilohm pUlidown resistor on the amplifier output is necessary for fast negative transitions.
Full scale output may be increased to as much as 32 volts
by increasing RO and raising the +15 V supply voltage to
35 V maximum. The resistor divider should be altered to
comply with the maximum limit of 40 volts across the
MCl723G. Co may be decreased to maintain the same
RoCa product if maximum speed is desired.

The circuit of Figure 20 is a variation from the standard
voltage output circuit and will produce bipolar output
signals. A positive current may be sourced into the sum·
ming node to offset the output voltage in the negative
direction. For example, if approximately 1.0 mA is used
a bipolar output signal results which may be described
as a 6-bit "1 's" complement offset binary. Vref may be
used as this auxiliary reference. Note that RO has been
doubled to 10 kilohms because of the anticipated 20 V
(p-p) output range.
FIGURE 20 - BIPOLAR OR NEGATIVE OUTPUT
VOLTAGE CIRCUIT
Vref +6.0 Vdc AS

6k

Programmable Power Supply

AO

R8"'2 RI2

10k

R12=R13

Polarity Switching Circuit, 6-Bit Magnitude Plus
Sign D-to-A Converter

The circuit of Figure 19 can be used as a digitally
programmed power supply by the addition of thumbwhee)
switches and a BCD·to·binary converter. The output voltage can be scaled in several ways, including 0 to +6.3 volts
in O.l·volt increments, ±0.05 volt; or 0 to 31.5 volts in
0.5-volt increments, ±O.25 volt.

Bipolar outputs may also be obtained by using a polarity
switching circuit. The circuit of Figure 21, gives 6-bits
magnitude plus a sign bit. In this configuration the operational amplifier is switched between a gain of +1.0 and
-1.0 .. Although another operational amplifier is required,
no more space is taken when a dual operational amplifier
such as the MC155SG is used. The transistor should be
selected for a very low saturation voltage and resistance.

FIGURE 19 - COMBINED OUTPUT AMPLIFIER and
VOLTAGE REFERENCE CIRCUIT
RO=5k

I
fMSB

•

::

NC

:

1 NC'<>---i

.,

f-o--4-(~

2

A4

FIGURE 21 - POLARITY SWITCHING CIRCUIT
(6-Bit Magnitude Plus Sign D-to-A Converter)

r- ---,

A3

MC1723G

I

I
I
I

;>-r~----~

LSB AS

__ Vo

10k
FROM Vo
OUTPUT ....---t--'lMr-~>-l
OP·AMPL

+15V

Vo" Vol' - voP

'"

3.Sk

Uk

5k

R13

3.Sk

Uk

VO=Vref

~{A}

Sel1lingtimefor 10V step
VEE

il!!

I.OIlS

-15V

(MC1506 - Page 91

7-134

p: 1:
p= O.

A~
A~

=-1
= +1

MC1506L, MC1406L (continued)

APPLICATIONS INFORMATION (continued)
Programmable Gain Amplifier or Digital Attenuator
The best frequency response is obtained by not allowing
112 to reach zero. RS can be set for a '±1.0 mA variation
in relation to 112. 112 can never be negative.
The output current is always unipolar. The quiescent
dc output current level changes with the digital word that
makes ac coupling necessary.

When used in the mUltiplying mode the MC1506L can
be applied as a digital attenuator. See Figure 22. One ad·
vantage of this technique is that if RS = 50 ohms, no
compensation capacitor is needed and a wide large signal
bandwidth is achieved. The small and large signal band·
widths are now identical and are shown in Figure 15.

FIGURE 22 - PROGRAMMABLE GAIN AMPLIFIER OR
DIGITAL ATTENUATOR CIRCUIT

FIGURE 24 - DC COUPLED DIGITAL ATTENUATOR
and DIGITAL SUBTRACTION
Vee VEE

Vre!

WhenVs
Vo:

~O.112 ~

2mA

[V"' V']l-f
-

Rl2

t -

AS

A

RO

Vre f2

RO

~15 Vd~

Vo

Panel Meter Readout
The MC1506L can be used to read out the status of
BCD or binary registers or counters in a digital control
system. The current output can be used to drive directly
an analog panel meter. External meter shunts may be
necessary if a meter of less than 2.0 mA full scale is used.
Full scale calibration can be done by adjusting R12 or Vref.

10 '01- 102 = ~r,e;~ {A} - ~7;~ {El}
=

DigitalSubtraClion;
let

Vrell = Vref2
RI21
RIl2
VO"

~',';:

Vo

=

JA,
1

FIGURE 23 -

RO

HAf -{'fl

Programmable Amphfier:
ConnectdigitalinpulssoA= B

f

IVrefl _ VlelXI
Rl21

Rill

This digital subtraction application is useful for indio
cating when one digital word is approaching another in
value. More information is available than with a digital
comparator.

PANEL METER READOUT CIRCUIT

Bipolar inputs can be accepted by using any of the
previously described methods. or applied differentially to
R121 and R 122 or R131 and R132. Va will be a bipolar
signal defined by the above equation. Note that the circuit
shown accepts bipolar differential signals but does not have
a negative common·mode range. A very useful method is
to connect R 121 and R 122 to a positive reference higher
than the most positive input, and drive R 13, and R 132.
This yields high input impedance, bipolar differential and
common·mode range. The compensation depends on the
input method used, as shown in previous sections.

(MC1506 -

Page 10)

7-135

•

MC1506L, MC1406L (continued)
APPLICATIONS INFORMATION (continued)
FIGURE 25 - DIGITAL SUMMING and CHARACTER
FIGURE 26 - PEAK DETECTING SAMPLE and HOLD
GENERATION
(Faatures indefinite hold time and optional digital output.)

Vre fl

(Features Indicate hold time~nd
opllDnaldigitaioutput.)

Va

CLOCK

OETECTfRO'Eii

VO"UOI +1021 RO

.[V.11 {At. v." J,tlf '0
Rill'

Rll]l

Vre l2

In a character generation system one MC1506L circuit uses a
fixed reference voltage and its digital input defines the starting
point for a stroke. The second converter circuit has a ramp input
for the reference and its digital input defines the slope of the
stroke. Note that this approach does not result in a 12-bit D-to-A
converter (see Accuracy Section).

Positive peaks may be detected by inserting a hex inverter between
the counter and MC1506L, reversing the comparator inputs, and
connecting the output amplifier for unipolar operation.

FIGURE 27 - PROGRAMMABLE PULSE GENERATOR

FIGURE 28 - PROGRAMMABLE CONSTANT CURRENT SOURCE

Vee

Vee

01

+--___..VOJL
{Dlo 1 Volt

R5

50

in 16mV stepsl

Fast rise and fall times require the use of high speed switching
transistors for the differential pair, Q4 and 05.

Linear ramps

and sine waves may be generated by the appropriate reference
input.

Current pulses, ramps, staircases, and sine waves may be generated
by the appropriate digital and reference inputs. This circuit is
especially useful in curve tracer applications.

FIGURE 29 - ANALOG DIVISION BY DIGITAL WORD

FIGURE 30 - ANALOG QUOTIENT OF TWO
DIGITAL WORDS

o ~~_ _ _ _--(>--I
Vee ...._""iil

Va

10 = CCflSTAtlT
Vo

=1*

NC

This circuit yields the inverse of a digital word scaled by a
constant. For minimum error over the range of operation, 10 can
be set at 621lA so that 112 will have a maximum value of 3.938 mA
for a digital bit input configuration of 000001.
Compensation is necessary for loop stability and depends on
the type of operational amplifier used.

If a standard 1.0 MHz

operational amplifier is employed, it should be overcompensated
when possible. If this cannot be done, the reference amplifier
can furnish the dominant pole with extra Miller feedback from
pin 14 to 13.

If the MCI723 or another wideband amplifier is

used, the reference amplifier should always be overcompensated.

(MC1506 - Page 11)

7-136

MC1506L, MC1406L (continued)

APPLICATIONS INFORMATION (continued)

FIGURE 31 - ANALOG PROOUCT OF TWO OIGITAL WORDS
(High-Speed Operation)

-

101

R121

12

Vref '---',IIIv-<>-;

NC

NC

13

14
20pF
RI3

Vo

=:

102"

101 AO

~1

=:

RI21

{A} RO

K can be an analog variable.

Jol

IVOI
R122

. ~~12

[RO

G'l';;) {ill]

since RO = R122 and K " Vref/R 121

Two Digit BCD Conversion
resistive current divider. If current output IS desired, the
units may be operated at full scale current levels of 4.0 mA
and 0.4 mA with the outputs connected to sum the currents.
The error of the D-to-A converter handling the least significant bits will be scaled down by a factor of ten.

MC1506L parts which meet the specification for l-bit
accuracy can be used for the most significa~t word when
building a two digit BCD D-to-A or A-to-D converter. If
both outputs feed the virtual ground of an operational
amplifier, 10:1 current scaling can be achieved with a

FIGURE 32 - DIGITAL QUOTIENT of TWO ANALOG VARIABLES
or ANALOG-TO-DIGITAL CONVERSION

I

RESET

The circuit shown is a simple counterramp converter. An UP/DOWN counter
and dual threshold comparator can be

used to provide faster operation and
continuous conversion.

11
V"I ,---,\R,.,1,.,2_0-"12'-1
13

HEX
INVERTER

14
20pF

R13

C:~

Vref

c - Vin/AO
1

2

3

-~2

----LSB

MSB

C

(MC1506 - Page 12)

7-137

'\

MC1510G
MC1410G

HIGH-FREQUENCY CIRCUITS

\..-----------'

MONOLITHIC WIDEBAND VIDEO AMPLIFIER

VIDEO AMPLIFIER
INTEGRATED CIRCUIT

.. designed for use as a high-frequency differential amplifier with
operating characteristics that provide a flat frequency response from
dc to 40 MHz.
• High Gain Characteristics
AV = 93typ
• Wide Bandwidth - dc to 40 MHz typ

METAL PACKAGE
CASE 601
TO-99

• Large Output Voltage Swing
4.5 V POp typical @±6.0 V Supply
• Low Output Distortion
THO';; 1.5% typ

~I
8
(bottom view)

FIGURE 2 - LIMITING CHARACTERISTICS

FIGURE 1 - VOLTAGE GAIN vorsus FREQUENCY
0

I

0

r-

~

;S

.

v+ = +6.0 Vdc
V- :-6.0 Vdc

w

~20

r--

i

r--

"f

>

.
em......

_

51

1.0k

'\

eout
AV:lIin

o1.0

2.0

II III

I

5.0

I

10

~

'\.

"="

51

10

v+ = +6.0 Vdc

:;2.0

,

"~'
To...
~

o

r-T""'T"""T""""'"
2.5H-I4-+++++-+-4--H-l-+-l

~

z

~30

11-'-'1

3.0........,../~I"""""

5
i=
g

,

50

1.0Hi-

~0.5~1-

200

100

500

°0~~20~~1~~1~1~1~~1~~~1~
'~. IN~~T SI:~AL ~OS"."\ 120

1000

f fREQUENCY MHz

1.0

EQUIVALENT CIRCUIT

CIRCUIT SCHEMATIC

I

-6.0 Vdc

1.51-f/-

\
20

v-"

II

,-----------------------------

V+

1

I
1510

:

750

750

510

~--1I----f

I
INPUT
f+) 1

I

11
43

l _ _-+_l.:I0;oUTPUT 1
7 (+)

OUTPUT 1

5 I-I

II~i~T·o2'T1---I_--....J
6.8k

INPUT 1

r

43

2.0k

2.0kiOUTPUT 2

I

670

I

I

I

i

~0L-_ _ _ _ _~_ _ _ _ _~270

L_ - - - - - ---v~ . - - - - - - - - -CASE6-- GND-...1
4

•

See Packaging Information Section for outline dimensions.

7-138

OUTPUT 2
3
INPUT 2

MC1510G, MC1410G (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Power Supply Voltage

Differential I nput Signal
Common Mode Input Swing

Symbol
V+

Value

Unit

+8.0

Vdc

V-

-B.O

Vdc

Vin

±5.0

Volts

CMVin

±6.0

Volts

Load Current

IL

10

rnA

Output Short Circuit Duration

ts

5.0

s

680
4.6

mW
mW/oC

Power Dissipation (Package Limitation)

Po

Metal Can
Derate above T A = +25 0 C
Operating Temperature Range
MC1410
MC1510

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (V+

TA

o to +75

°c

-55 to +125
T stg

-65 to +150

°c

= +6 Vdc, V- = -6 Vdc, RL = 5.0 kohms, T A = +25 0 C unless otherwise noted)
MC1510

Characteristic
Single Ended Voltage Gain

Min

Typ

Max

Min

Typ

Max

Unit

AV(se)

75

93

110

60

90

120

V/V

-

35

-

35

-

-

6.0

-

6.0
40

-

4.5

-

-

4.5

-

1.6

5.0

-

2.0

-

-

±1.0

-

-20

-40

-

-

85

-

Output Impedance
(f= 20 kHz)

Zout

I nput Impedance
(f = 20 kHz)

Zin

Bandwidth (-3.0 dB)

BW

Output Voltage Swing
( f = 100 kHz)

Vout

Single Ended Output Distortion
(ein < 0.2% Distortion)

THO

1nput Common Mode Voltage Swing

CMVin

Common Mode Voltage Gain
(ein = 0.3 V rms. f = 100 kHz)

AVCM

Common Mode Rejection Ratio

CMrej

I nput Bias Current

(Ib= 11 ;12)

MC1410

Symbol

-

40

-

±1.0

-30

-45

-

85

-

fI.

Input Offset Current
(lio = 11 -12)
Output Offset Voltage
Differential Mode (Vin = 0)

80

-

50

100

-

3.0

20

-

5.0

30

-

0.5

1.3

-

0.5

2.0

Common Mode (Differential Output = 0)

Vout(CM)

2.6

3:1

3.5

2.0

3.0

4.0

tf
tpd
tr

9.0
9.0

12

-

-

15

9.0

12

10
9.0
10

Step Response

Average Temperature Coefficient of
Input Offset Voltage

-

-

/lA
Vdc

ns

-

-

-

-

15
/lV/oC

TCVio

-

(RS = 50 fl., TA = Tlow' to Thigh")
(RS';; 10 k fl., TA = Tlow to Thigh)

-

DC Power Dissipation
(Power Supply = ±6.0 V)

Po

Equivalent Average Input Noise Voltage
(f = 10Hz to 500 kHz)
(RS =0)

Vn

'Tlow = OOC for MC1410
or -55 0 C for MC151 0

Vpeak

/lA
20

Vout(DM)

%

dB

Iliol

MHz
Vp-p

IIbl
Differential Output = 0

kfl.

-

-

-

±3.0
±6.0

-

150

220

-

165

220

5.0'

-

-

5.0

±3.0
±S-O

mW

"Thigh = +750 C for MC1410 or
+1250 C for MC1510

7-139

/lV

-

MC1510G, MC1410G (continued)

TYPICAL CHARACTERISTICS

(V+ ; +6.0 Vdc, V- ; -6.0 Vdc, T A ; +25 0 C unless otherwise noted)
FIGURE 4

FIGURE 3
POWER DISSIPATION versus SUPPLY VOLTAGE

VOLTAGE GAIN versus SUPPLY VOLTAGE

30 0

0

42~--~-----r----~----~--~~--~----~

~
V-

0

o

o

----

V

V

6.0

/

V

8.0
10
12
IV+I + IV-I, SUPPLY VOLTAGE (Vdc)

/

~40

~38~---+----~----~~{f7T~~~--~--~
w

to

;0

~3G~---4----~~--~~

>

i
14

34~---+~~~----~~

32l"---"J~--"Jl,,..---.,J~J::::.:====::>:=:::::!J.
4.0
6.0
8.0
10
12
14
16
18

16

IV+I + IV-I, SUPPLY VOLTAGE (Vdc)

FIGURE 6
DC OUTPUT VOL TAG E versus TEMPERATURE

FIGURE 5
VOLTAGE GAIN versus TEMPERATURE
5

~

«
to

3. 5

?w

- ---

40

w

to

~
o

>3 5

i

to

~

o

...>

~ 3. 0

o

./

--

-=

Q

>
-55

o

-25

+25
+50
+75
+100
TA, AMBIENT TEMPERATURE (DC)

+125

2. 5
-55

+150

+25
+50
+75
TA, TEMPERATURE (DC)

+100

+125

OUTPUT NOISE VOLTAGE versus SOURCE IMPEDANCE

0

7. 0

J''-

I"'" ~
IB = Ii ; 12

h
..sw

">

"::[:2:

~

o
z

-25

0
BANDWIDTH - 5.0 Hz to 10 MHz

5.0

V

...

12 - -

~
... 4.0
:::>

o

~ r-.

+25
+50
+75
TA, TEMPERATURE (DC)

I,;-

~

-E 3.0

L-

>

10

-55

-25

Vout 2

FIGURE 8

FIGURE 7
INPUT BIAS CURRENT versus TEMPERATURE

0

~'"
51

~

30

-----

+100

2. 0

+125

1.0

7-140

10

100
1.0k
10k
RS. SOURCE RESISTANCE (OHMS)

100 k

MC1510G, MC1410G (continued)

TYPICAL APPLICATIONS

FIGURE 10
TWO STAGE VIDEO AMPLIFIER WITH ADJUSTABLE GAIN

FIGURE 9
ENVELOPE OETECTOR

+7.5 Vdc

+6 Vdc

~O.lPF

100

':'

100

100

':'

100

lk

-6 Vdc

0.1
':'

*"F

0.1 "F

i

-7.5 Vdc

FIGURE 11

FIGURE 12

SINGLE STAGE WIDEBAND AMPLIFIER

WEIN BRIDGE OSCILLATOR
V+=+6 Vdc
f = 10 kHzto 10 MHz'"

lIz.Re

+6 Vdc
(AV = 39 dB)

0.1 "F
'in

I

"""f-1"'--<>-i

-6 Vdc
V-= -6 Vdc

7-141

DUAL DIFFERENTIAL COMPARATOR

MC1514L

MONOLITHIC DUAL DIFFERENTIAL VOLTAGE COMPARATOR
· .. designed for use in level detection, low-level sensing, and memory
applications.
Typical Amplifier Features:
• Two Separate Outputs
• Strobe Capability
• High Output Sink Current - 2.8 mA min Each Comparator
• Differential Input Characteristics:
Input Offset Voltage = 1.0 mV
Offset Voltage Drift = 3.0 /LV'oC
• Short Propagation Delay Time - 40 ns
• Output Compatible with All Saturating Logic Forms
Vout = +3.2 V to -0.5 V typical
MAXIMUM RATINGS (TA =25°C unless otherwise noted)

Symbol

Rating

Value

Unit

Y-

+14
-7.0

Vdc
Ydc

Yin

±S.O

Yolts

CMVin

±7.0

Yolts

Peak Load Current

IL

10

mA

Power Dissipation (package limitation)
Ceramic Dual-In-Line Package
Derate above T A = +25°C'

PD

1000
'6.7

mW
mW/"C

Operating Temperature Range

TA

-55 to +125

·C

Tstg

-65 to +150

°c

y+

Power Supply Yoltage
Differential Input Signal
Common Mode Input Swing

storage Temperature Range

CERAMIC PACKAGE
CASE 632

TO-116

CIRCUIT SCHEMATIC
v+

STROBE

3

2

3.9 k

OUTPUTS
1

B

2.B k

7

v-

STROBE
9

2.B k

11

GND

See Packaging I nformation Section for outline dimensions.

7-142

v+
10

3.9 k

14

v-

MC1514L (continued)

ELECTRICAL CHARACTERISTICS

(V+

= +12Vdc, Y-;;: -6 Vdc, TA = 25°C unless otherwIse noted) (Each Comparator)

Characteristic Definitions (linear operation)

~

Via

Yo ••

RsS200n

'-;::'"

Max

-

1.0

2.0

Vout :::: 1.8 Vdc, TA = _S5 D e
Vout = 1.0'Vdc, TA = +125"C

-

-

3.0
3.0

-

3.0

-

1.0

3.0

ViO

TCVio
I io

Vout = 1.4 Vdc, TA = 2SoC
Vout = 1.8 Vdc, TA = _S5 D e

-

V out = 1.0Vdc, TA =+125"C

Input Bias Current
Vout = 1.4 Vdc, TA = 25"C

1;0=1 1 -12

1,

-

Vout = 1. 8 Vdc, T A = _55" C

-

Vout = 1.0 Vdc, TA = +125 D C

Unit
mVdc

-

MV/'C

J..I.Adc

7.0
3.0
jJAdc

12

20

-

20

45

Open Loop

r ~;~
4--

Typ

Input Offset Current

Ib=~

L

Min

Temperature Coefficient of
Input Offset Voltage

:=r>:.
~

Symbol

Input Offset Voltage
v out = 1. 4 Vdc, T A = 25" C

Rs

":"

Characteristic

Voltage Gain
TA =25"C

AVOL

1000

T A = -55 to +125"C

eou.

1250

V!V

1700

-

-

R•••

-

-

~=

Vj"

e,n

.I.
'":

95mV-Vio

3.2

4.0

Vde

Negative Output Voltage
Vin f; -5.0 mV

VOL

-1.0

-0.5

0

Vde

out

I
i;

0,

-

200

ohms

Vde

mAde

5

= -55 to +125°C

Input Common Mode Range

CMV.

In

2.8

3.4

±5.0

-

Volts

V- = -7.0 Vde.

Common Mode Rejection Ratio
V-

....

"="

i4V~
"1lOamY

.;.:::::l

,.~
":'"

-

2.5

R

= -7.0 Vdc,

CMrej
80

100

-

dB

-

40

-

n5

1,+

-

12.8

18

mAde

1,-

-

11

14

-

230

300

RS:;;;: 2000

eOgt

~

v,·

±5.0

VOH

TA

W
r0-[>:=
"="

V in

Positive Output Voltage
Vin ~ 5.0mV, 0 ~ 10 ~ 5.0mA

Output Sink Current
Yin f; -5.0 mV, Vout

'0

-=-V,

Differential Voltage Range

-

Output Resistance

':"

",-

Propagation Delay Time
For Positive and Negative
Going Input Pulse

tpd

v,

Total Power Supply Current
Vout :; ;: 0 Vdc

Total Power Consumption

7-143

mW

I

MC1514L

(continued)

TYPICAL CHARACTERISTICS
(Each Comparator)

FIGURE 1 - VOLTAGE TRANSFER
CHARACTERISTICS

FIGURE 2 - INPUT OFFSET VOLTAGE
versus TEMPERATURE
3.0

.0

r

-55 DC

-'-

.0

+25 0 C

~\

1\\
\'

\. +125 DC
.0

0

-r--

0

\
t\

0

0

+125 11&

-~

+25°C

-55°C

-1.0
-8.0

6.0

~o

4.0

2.0

4.0

i\\
'-'
6.0

~

/

h
o

ao

- 25

-55

5

4. 0

O~

ot\.

"- r'\.

o

-55

25

5

"""

'-......

25

50

--

75

0

r--

100

5.0
-55

125

'" "- "
-25

lA. AMBIENT TEMPERATURE (DC)

I

I

V-=-7Vdc

,/"

~2000

~

~
.-~
..,/"

z

~

/

~150 0

~

>

~1000 /

500

125

~
25

............

50

r---

75

100

125

FIGURE 6 - VOLTAGE GAIN
versus TEMPERATURE
250 0

250 0

.

100

TA. AMBIENT TEMPERATURE (OCI

FIGURE 5 - GAIN VARIATION
WITH POWER SUPPLY VOLTAGE

300 0

75

FIGURE 4 - INPUT BIAS CURRENT
versus TEMPERATURE

FIGURE 3 - INPUT OFFSET CURRENT
versus TEMPERATURE
5.0

0

50

TA! AMBIENT TEMPERATURE (DC)

Vin,lNPUTVOLTAGE (mV)

0

25

--

~

0
10

/""

-

~

~200

f....-

'"

~ / "V

~>

~15D0

..

,/"

11

0 ___

"
~

12

13

1000
-55

14

V+. POSITIVE SUPPLY VOLTAGE (Vdc)

--

:-.....
...............

~
............

25

25

50

75

TA. AMBIENT TEMPERATURE (OCI

7-144

~

100

125

MC1514L (continued)

FI.GURE 8 - POWER DISSIPATION
versus TEMPERATURE

FIGURE 7 - RESPONSE TIME
4. 0

3D0

0

~

0
20mV OVERORIVE0
ID mV OViRORIVE-

0

\\~

\-\\\

" "'

-I. 0

>" 150

0

5mV OVERDRIVE

2 mV OVErDRIVE

~

r-

I
0

I

Hlf---------+----If---------+---I1f----l-----11I
:5 -5°);-0--""'2-!'0---4"'0:---~60;-----;;8\;-0--"1D~0--"";'20

150
-55

- 25

t. TIME (nsl

25

50

75

100

125

lA. AMBIENT TEMPERATURE (OCI

FIGURE 9 - RECOMMENDED SERIES RESISTANCE
versus MRTL LOADS

FIGURE 10 - SINK CURRENT versus TEMPERATURE

ID0

4.0

~~

0

~
3.0

0

1'-1'
0

0
mWMRTl

.0

I......

.0

I Mn I

1.0

0.1

"' ......

MEO. POWER

'"

0.5

0

I"
1'1'

1.0
2.0
RS. SERIES RESISTANCE (k OHMS)

0.2

5.0

0
-50

ID

FIGURE 11 - CROSSTALKt

3

!
I

2

,

···

In=±SOmV

I
j

i
I

2
1

~

r-- rrl-

-

Inducad output signal in
amplifier 12 duato output
signal at amplifier II.

TIME, 50 ns/div
tWOBt case condition shown - no load.

7-145

-25

25
50
75
lA. TEMPERATURE (OCI

100

125

"-------I

l . . ____

O_P_E_R_A_T_IO_N_A_L_A_M_P_L_IF_I_E_R_S----'

MC1520
MC1420

MONOLITHIC DIFFERENTIAL OUTPUT OPERATIONAL
AMPLIFIER

OPERATIONAL AMPLIFIER
MONOLITHIC SI LICON
INTEGRATED
CIRCUIT

· .. designed for use in general·purpose or wide·band
differential amplifier applications, especially those requiring differential outputs.

Typical Characteristics
•
•
•
•
•

Differential Input and Differential Output
Wide Closed-Loop Bandwidth; 10 MHz
Differential Gain; 70 dB
High Input Impedance; 2.0 megohms:
Low Output Impedance; 50 ohms

MAXIMUM RATINGS ITA

=

Pin 3 connected to case

GSUFFIX
METAL PACKAGE
CASE 602A

+25 0 C unless otherwise noted)

Rating

Symbol

Value

Unit

V+
V-

+8.0
-8.0

Vdc

Vin

±8.0

Vdc

IL1,IL2

15

mA

680
4.6

mW
mW/oC
mW
mW/oC

Power Supply Voltage
Differential Input Signal
Load Current

Power Dissipation (Package limitation)
Metal Package
Derate above T A = +250 C
Flat Package
Derate above T A = +250 C
Operating Temperature Range
MC1520
MC1420

Po

TA

-55 to +125
o to + 75

°c

Storage Temperature Range

T stg

-65 to +150

°c

500
3.3

FSUFFIX
CERAMIC PACKAGE
CASE 606
TO-S1

CIRCUIT SCHEMATICS
FIGURE 1 - CIRCUIT SCHEMATIC
'@[j]

OconlainIPlnnumbeclormetalcanpack'91

o contains pin number lor IlatpICklgt

See Packaging Information Section for outline dimensions.

7-146

MC1520, MC1420 (continued)

SINGLE-ENDED ELECTRICAL CHARACTERISTICS
(v+ - +6 0 Vdc V-.-6 0 Vdc TA - +25 0 C unless otherwise noted)
MC1520
Characteristic
Open LOOR Voltage Gain
(Tlow @ ~ TASThigh ~)
Output Impedance
(f = 20 Hz)

MC1420

Svmbol

Min

TVp

MaM

Min

TVp

Mal(

Unit

AVOL

1000
60

1500

-

750

-

1500
64

-

V/V
dB

Zout

-

64

-

50

100

-

50

-

0_5

2.0

-

-

2.0

-

±3.0

±4.0

-

-

±3.0

-

ohms

I nput Impedance
(f = 20 Hz)

Zin

Output Voltage Swing
(R L = 7.0 kn[FigureS))

Va

±3.5

±4.0

-

I nput Common-Mode Voltage Swing

CMVin

±2.0

±3.0

Common-Mode Rejection Ratio

CMrej

75

90

-

60

90

-

-

O.S

2.0

-

2.0

40

-

30

-

-

200

-

-

30

-

100
200
200

-

-

-

5.0

10

-

5.0

15

SO
70
5.0

-

-

-

SO
70
5.0

-

-

-

-

80
70
15

-

-

ns
ns

-

V//Js

-

ns
ns

-

V//Js

-

ns
ns

-

V//Js

Input Bias Current

([Ib

~

11; 12 ]. TA

lIiol

I

IViol

-

Input Offset Voltage
(TA = +25 0 C)
Step Response

G""' '.0, ",. Ow"",",
Rl=10kn
R2=10kn
R3 = 5.0 kn
Cs = 39 pF

Rl = 10kn
/"""'
,", ''''' 0 "".,"'

I

R2= 100kn
R3=10kn
Cs ~ 10 pF

Rl=I.0kn
R2=100kn
R3= 1.0kn
Cs = 1.0pF

r~"
COO"
Rl = 50
n

R2 =co
R3 = 50 n
Cs = 0
Bandwidth:
(Open Loop[Figure 4j)
(Closed Loop[Unity Gain])
(Figure 5)

-

80
70
15

SO
70
30

-

.

Max

Unit

3000
70

-

-

V/V
dB

-

2.0

-

100

200

-

100

-

0

+0.5

-

0

-

±B.O

-

±6.0

±8.0

-

megohms

,

I
-0.5

Typ

1500
64

-

Va (CM)

Output Voltage Swing
(RL = 7.0 kn)

--

Min

2.0

Zin

= 20 Hz)

Output Impedance
(f

MC1420
Max

TVp

.2000

AVOL

I nput Impedance
(f

Min' ,.

Symbol

ohms
Vdc

0

Va

±7.0 ...

Vpeak

TYPICAL CHARACTERISTICS
(v+

= +6.0 Vdc, V- = -6.0 Vdc, T A = +25 0 C, unless otherwise

FIGURE 3 - LARGE SIGNAL SWING
versus FREQUENCY

TEST CIRCUIT

"

INVERTING __o'W'v-*-s>:-l

+8. 0

~

+6. 0

-2-1

NON·INVERTING ...- -.....

5 +4. 0
2:
w

C!J

~

o

,..
>

2

CURVE:!\

CURVE 4

+2. 0
I

O

1

"t-

1/

~-2.0

V

=>
o

'" -4. 0
~
-6. 0

NO.

-8.0
0.1

3

1.0

10

100

1000

10,000

f, FREQUENCY (kHz)
4

FIGURE 4 - OPEN LOOP VOLTAGE GAIN

5

70

f\..

50

40

~

>
..:;
o

JuW'~

1\

r\.1
i'.
31'\

to

o

GAIN

OUTPUT

R,lnl R21n1 R31n I CSlpFI mVlrms

100
10
1,0
1.0

1.0k
10k
10k

NON·JNVERTING
NON·INVERTING
NON· INVERTING

AVOL

0
0
0

NON·INVERTING
NON·INVERTING
NON·INVERTING

100
10
1.0

INVERTING

1
2

INVERTING

3

INVERTING

4

NON-INVERTING

1
2
3
1
2

AVOL

AVOL

~

1.0k
10k

1,0
10

S.Ok

10k

3.
3.

50
50
50

3.

1.0
2.0
5.2

100
.,0
10k

1,0
10
39

2.0
0.55
0.17

~
~

~

100
l.Qk
~

100k
100k
10k
10k

10k
9.1k
10k

1,0
10

2,0
0.55
0.17
0.17

III

'"
;;:
W

VOLTAGE

I'Nt

60

to

MODE

NO.

3

~

NOISE

TEST CONDITIONS

FIGURE CURVE

D..

I

noted.!

30

'\.
FIGURE 5 - CLOSEO LOOP VOLTAGE GAIN
versus FREQUENCY
+60

1'\

"'
;
;;:
to
w

~ 20

(,!l

1"'-

~o

CURVE 1

+20

2

>

0

0.1

11 ,

+40

~

1.0

10

100

1000,

10,000

f, FREQUENCY (kHz)

-20
1.0

~'I"
10

100

1000

f, FREQUENCY (kHz)

7-148

'I"

10,000

100,000

MC1520, MC1420

(continued)

TYPICAL OUTPUT CHARACTERISTICS
(v+

= +6.0 Vdc, v- = -6.0 Vdc, unless otherwise noted.1

FIGURE 7 - OPEN LOOP VOLTAGE GAIN
versus SUPPLY VOLTAGE

FIGURE 6 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE
25

1000~W..
800~

0
'-'

50

~

w

'"=>

a

""

~
i';'i

100

""

125

a

0/

~
z

;;:

'"w
w

'"'"
ti

:t

'"

'"

':;
0
>

'"ti

:t

----

V

'"

w

/'

V

a

..l
0

'"

~
0

a
a
5.0

6.0

8.0

7.0

4.0

2.0

9.0

V+ and V-, POWER SUPPLY VOLTAGE (Vdcl

6.0

8.0

V+ and V;- SUPPLY VOLTAGE IVdc)

FIGURE 9 - OUTPUT NOISE VOLTAGE
versus SOURCE RESISTANCE

FIGURE 8 - SINGLE ENDED OUTPUT VOLTAGE
versus LOAD RESISTANCE
100 a

10

~
R2

8.0

"'-I

~6. a
w

'"

'"':;

/

o

>

~ 4.0

!;

0

>

1

_ Rl _ R3

C,

Open Loop

..!-++

IIII

Cr~pt

a

Cs

1.0 pF

~

IIII

>

/

I UJ...-

I II

1.0
Cs

2.0

4.0

6.0

8.0

10

RL, LOAO RESISTANCE IK-OHMSI

fdlB

I"IT

I II
1.0

10

100

RS,SOURCE RESISTANCE IK·OHMSI

7-149

rr

R3= R1R2

I

R2

20 dBI- RS - R3

10 pF

Cs 39 pF
O. 1
0.1

AV=*

40 dB

.-l-H

V

o
6

2. a

V

v

V

II

II
1.0 M

•

j

\

OPERATIONAL AMPLIFIERS

'----- MCIS30, MC1430 - - - - - - - - - - - - - - '
MCIS31, MC1431
MONOLITHIC OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIERS
INTEGRATED CIRCUIT

. . . designed for use as a summing amplifier, inte·
grator, or amplifier with operating characteristics as a
function of the external feedback components.
The MC1531 (MC1431) is provided with Darlington
inputs to increase input impedance; otherwise the
MC1531 (MC1431) circuit is identical with the MC1530
(MC1430) circuit.
•

High Open Loop Voltage Gain - 4500 min (MC15301
- 2500 min (MC1531)

•

High Input Impedance - 10 Kilohms min (MC1530)
- 1.0 Megohm min (MC1531)

•

Low Output Impedance - 50 Ohms max

•

High Slew Rate - 6.0 V!/lS typ@A vs = 10

•

High Open Loop Bandwidth - 2.0 MHz typ (MC1530)
0.4 MHz typ (MC1531)

G SUFFIX
METAL PACKAGE
CASE 602B

MAXIMUM RATINGS (T A" 25°C unless otherwsie noted)
Rating

Symbol

Power Supply Voltage MC1530. MC1531
MC1430, MC1431
Differential I nput Signal

VID{max)

Load Current

Value

Unit

+9.0, -9.0
+8.0. -8.0

Vdc

F SUFFIX
CERAMIC PACKAGE

±5.0

Volts

10

mA

680
4.6
500
3.3

mW
mW/oC
mW
mWJOC

400
3.3

mW
mW/oC

CASE 606
TO·91

Power Dissipation (Package Limitation)
Metal Package
Derate above T A = +250 C

Flat Package
Derate above T A = +250 C
Dualln·Line Plastic Package
MC1430. MC1431

Derate above +25 0 C
Operating Temperature Range

Storage Temperature Range

P SUFFIX
PLASTIC PACKAGE
CASE 646
TO-116
(MC1430P/MC1431P onlvl

°c

MC1530. MC1531
MC1430, MC1431

-55 to +125
o to +75
T stg

°c

Metal and Ceramic Package
Plastic Package
MC1430. MC1431

-65 to +175
-55 to +150

CIRCUIT SCHEMATICS
FIGURE 1 - EQUIVALENT CIRCUIT
BOTH TYPES

FIGURE 2 - MC1530/MC1430
(STANDARD INPUT)

FIGURE 3 - MC1531/MC1431
{DARLINGTON INPUT!

E

+--++--+-oOUTPUT
OUTPUT

PIN CONNECTIONS

Schematic
"F"& "G"Pkgs.
"P"Package

ABCOEFGHJK
1 2 3 4 5 6 7 8 9 10
4 6 8 7 11 12 13 14 1 2

o

VEE

See Packaging Information Section for outline dimensions.

7-150

MC1530, MC1531, MC1430, MC1431 (continued)
ELECTRICAL CHARACTER ISTICS (VCC = +6.0 Vde, VEE = -6.0 Vde, T A = +25 0 C unless otherwise noted)
MC1430

MC1530

Characteristic

Symbol'

Min

Typ

Max

Min

Typ

Max

Unit

liB

-

3.0

10

-

5.0

15

"Ade

110

-

0.2

2.0

-

0.4

4.0

"Ade

VIO

-

1.0

-

10
11
12

mVde

-

-

2.0

-

5.0
6.0
6.0

-

kll

I nput Bias Current

Input Offset Current
TA - +25 0 C

I nput Offset Voltage

TA =TIOW~
TA = Thigh 1

zis

10

20

-

5.0

15

± 2.0

± 2.7

-

±2.0

± 2.5

Vpk
I'V(rms)

Equivalent I nput Noise Voltage
(Open-Loop, Rs = 50 ohms, BW = 5.0 MHz)

eN

Common-Mode Rejection Ratio (f = 100 Hz)

CMRR

Open-Loop Voltage Gain,
TA = +25 0 C
TA = Tlow to Thigh

-

-

VICR

Single-Ended Input Impedance (Open-Loop, f - 30 Hz)
Common-Mode Input Voltage Swing

-

-

10

70

75

Avol

-

-

-

-

4500

5000

12,500

-

10

-

65

75

-

dB
V/V

3000

5000

-

-

MHz

Bandwidth (Open-Loop. -3.0 dB, no roll-off capacitance)

BW

1.0

2_0

1.0

2.0

Output Impedance (f = 100 Hz)

zo

-

25

50

-

25

50

Output Voltage Swing (RL = 1.0 k ohms)

Vo

±4.5

± 5.2

-

±4.0

±5.0

-

Vpk

Power Supply Sensitivity (Rs';;; 10 k nI

PSRR

100

-

-

100

-

"V/V

10,10-

-

9.2

12.5

12.5

mAde

-

110

150

-

9.2

Po

110

150

mW

Power Su pply Current
DC Quiescent Power Dissipation (VO = 0)

ohms

ELECTRICAL CHARACTERISTICS (VCC = +6.0 Vde, VEE = -6.0 Vde, TA = +25 0 C unless otherwise noted)
MC1431

MC1531

Characteristic

Symbol'

Min

Typ

Max

Min

Typ

Max

Unit

liB

-

0.025

0.150

0.1

0.3

"Ade

0.003

0.025

0.01

0.1

"Ade

3.0

10

5.0

-

-

zis

1000

2000

-

-

15
18
16_5

mVde

-

-

300

600

-

kll

VICR

±2.0

± 2.4

-

± 2.0

±2.2

-

Vpk

20

-

-

20

-

60

75

-

Input Bias Current
I nput Offset Current

110
TA - t25 0 C
TA =TlowG)
TA = Thi9hG)

I nput Offset Voltage

Via

Single-Ended Input Impedance (Open-Loop. f = 30 Hz)
Common-Mode I nput Voltage Swing

-

"V(rms)

Equivalent I nput Noise Voltage
(Open-Loop, Rs = 50 ohms, BW = 5.0 MHz)

eN

Common-Mode Rejection Ratio (f - 100 Hz)

CMRR

Open-Loop Voltage Gain
TA = +25 0 C

-

65

65

Avol

dB
V/V

-

-

-

1500

3500

2500

3500

7000

-

-

Bandwidth (Open-Loop, -3.0 dB, no roll-off capacitance)

BW

-

0.4

-

-

0.4

-

Output Impedance (f = 30 Hz)

zo

-

25

50

-

25

50

Output Voltage Swing (RL = 1.0 k ohms)

Vo

.±.4.5

±5.2

±5.0

-

Vpk

PSRR

-

100

-

.±.4.0

Power Supply Sensitivity (RS';;; 10 k n)

-

100

-

"V/v

-

9.2

12.5

9:2

12.5

mAde

-

110

150

-

110

150

mW

TA = Tlow to Thigh

Power Supply Current

10,10

DC Quiescent Power Dissipation (VO = 0)

-

Po

MHz
ohms

STEP RESPONSE, TYPICAL CHARACTERISTICS
tVee

=

+6.0 Vdc. vee

c

-6.0 Vdc, Vo "" 400 mVdc, TA '" +2SoCI

Step Response
{Gain;; 100,0% overshoot,

\~
"

OVERSHOOT
\-"SLEW RATE

\.-

MC1530

MC1531

Symbol-

MCI430

MC1431

'THL

0.13
0.11

VIlli

.s,..
.s,..

A1 = 1.0kohm, R2'" 100 k ohms.
R3'" 1.0 k ohm. Cl ;: 750pF

tPH~

SA

33

0.36
0.21
16

{Gain'" 10. 10% overshoot.
Rl '" 10 k ohr:ns•. R2 '" 100 k ohms,
R3'" 10 k ohms, Cl '" 6800 pF

'THL
tPHL
SA

0.34
0.25
6.0

0.30
0.28
5.5,

VI,..

{ Gain'" 1.0, 5.0% overshoot,
R1 '" 10 k ohms, A2::: 10 k ohms,
R3 = 5.0 k ohms, C1 '" 33.000 pF

'THL
tPHL
SA

0.28
0.16
1.7

0.37
0.17
1.4

VI,..

CD Tlow:

aOc for MC1430
-55 0 C for MC1530
Thigh: +75 0 C for MC1430
+1250C for MC1530

7-151

Tlow: OOC for MCt431
_55 0 C for MC1531
Thigh: +750C for MC1431
+125 0C MC1531

,..,..

·Symbols used conform to
JEOEC Engineering Bulletin
No.1 where applicable.

I

MC1530, MC1531, MC1430, MC1431 (continued)

TYPICAL OUTPUT CHARACTERISTICS
IVee '" +6.0 Vdc, Vee'" -6.0 Vdc, T A:' +2SoCI

FIGURE 4 - TEST CIRCUIT
DEVICE
NO.
MCI530/MCI430. MC15311MCI431
MCI530/MCI430. MC15311MCI431
MCI530/MCI430. MC15311MCI431

CURVE VOLTAGE
NO.
GAIN
100
1.2
10
3
1
4
100
1
10
2
10
3
1
4
1
5
100
1
10
2
3
1
1
AVOL
2
AVOL
3
AVOL
4
AVOL

FIG.

R2

NO.
6

6

7

S

CI

1
2
3
4

9

MC1530/MC1430

MCI530/MCI430
MCI530/MCI430
MC1530/MC1430
MCI530/MCI430
MC15311MC1431
MC1531/MCI431
MC15311MCI431
MCI530/MCI430

------

MC1530/MC1430

MC1530/MC1430
MC1530/MCI430
MCI53l1MCI431
MCI5311MCI431
MC15311MCI431
MCI531/MC1431

AVOL
AVOL
AVOL

AVOL

FIGURE 5. - LARGE SIGNAL SWING
versus FREQUENCY

TEST CONDITIONS
R, lklll R21klll R31111
1.0
100
1.0k
10k
100
10
5.0 k
10
10
100
1.0k
1.0
100
10k
10
1.0k
1.0
10
5.0k
10
10
500
1.0
1.0
1.0 k
1.0
100
10k
10
100
5.0k
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

c, lpFI
750
6800

33.000

750
6800
6800

33,000
33,000

750
6800
33.000
0

750
6800

33,000
u

750
6800
33.000

FIGURE 6 - MC1530/MC1430 VOLTAGE
GAIN versus FREQUENCY
45

14

4D
~

~
~

~

w
to

~

o

...
>

::I

r=

2
10

\r\

......

B.O

CURVE 4

2

3

l

6.0
4. 0

\

o

30

;;:

25

z

to

w

1

to

'"!::;
0

>

.t

I\.

~ 2.0
10 k

'"
:s

1\

\

::I

0
1.0 k

CURvrlr-.

35

100 k

20
15

IIII
l1U

5.0

10 k

10M

1.0M

5

f, FREQUENCY

tI+l

5

:s
'"
z

;;:

CURVE

0

to

5

l'

'"
:s

r'\

to

to

0

w

5

'"!::;

i

10

60

to

CURVE

i"-.

CURVE4

45

~

i'

3

i'

CURJn
1.0M

10M

100

r-...
r-...i'
1.0 k

10 k

100 k

f, FREQUENCY (Hz)

f, FREQUENCY (Hz)

7-152

1

2

30

o

I.......

r-...

15

........

100 k

~

0

II

0

I........

>

.t

II

5.0

10 k

75

z

;;:

o

>

10M

(Hz)

90

w

~

\

4"'\ "'-.:5

FIGURE B - MC1530/MC1430 OPEN LOOP VOLTAGE GAIN
versus FREQUENCY
105

II

40

:1\

'\

CURVE
1.0M

100 k

f, FREQUENCY (Hzl

FIGURE 7 - MC1531/MC1431 VOLTAGE
GAIN versus FREQUENCY

2'\.

CURVE

10

~

r-......

~

r-......

~

1.0M

10M

MC1530, MC1531, MC1430, MC1431

(continued)

FIGURE 9 - MC1531/MC1431 OPEN LOOP VOLTAGE GAIN
versus FREQUENCY
iO 5
0

~ 75
z

;;:
to

~

45

i

30

o
>

"
)r-.-

i'-..

60

CURVE~

w

to

,
,

2'

" r-.-

-

FIGURE 10 - VOLTAGE GAIN versus POWER SUPPLY VOLTAGE
90

w
to

....... ~

~

TA=+25 0 C

80

MCI530/MCI430

o

> -70

.,.'"
oOS

t-....

t-....

g

~ Cl

t-....

5

.....-: ~

~ 60

z

~

-6.0
10

100

1.0 k

0L-_L-_L-~_~~~~~~~_L-~L-~

;;;

10 k

0

1.0

RL. LOAO RESISTANCE (0 HMS)

2.0
3.0
7.0
8.0
VCC and VEE. POWER SUPPLY VOLTAGE (VOLTS)

9.0

10

FIGURE 13 - POWER DISSIPATION versus
POWER SUPPLY VOLTAGE
100 0
80 0
600
40 0

200

V

10 0
:; 80
;
60
o
0

~

~

c
'"
~
~

I

:1

V

I

V

/

~ 8. 0
6. 0
4. 0

2. 0
I. 0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

VCC and VEE. POWER SUPPLY VOLTAGE (Vdc)

7-153

I

I------'f

MC1533
MC1433

~~_________O_P_E_R_A_T_IO_N_A_L__A_M_P_L_IF_I_E_R_S~

OPERATIONAL AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

MONOLITHIC OPERATIONAL
AMPLIFIER

... designed for use as a summing amplifier, in·
tegrator, or amplifier with operating character·
istics as a function of the external feedback
components.

• High·Performance Open Loop Gain Characteristics
AVOL = 60,000 typical
•

G SUFFIX
METAL PACKAGE

CASE 6028

Low Temperature Drift - ±5 JlV10C

FSUFFIX

~
'·'Ylr~Y1( ¥ ~

•

Large Output Voltage Swing ± 13 V typical @±15 V Supply

•

Low Output Impedance - Zout = 100 ohms typical

CERAMIC PACKAGE

CASE 606
TO-91

LSUFFIX
CERAMIC PACKAGE

CASE 632
TO-116

PSUFFIX
PLASTIC PACKAGE

CASE 646
TO-116

(MC1433P Only)

FIGURE 1 - CIRCUIT SCHEMATIC

FIGURE 2 - EQUIVALENT CIRCUIT

v-+

G
n

n

"

DUTPUT

lAG

C

DC

PIN CONNECTIONS
Sehematic
"G" Package
"F" Peck age
"L" & "P" Packar'

See Packaging Information Section for outline dimensions.

7-154

ABC
1
2
3
10 1

D
4
3

E
5
4

4

7

11

5

10
9

12

3

MC1533, MC1433 (continued)

ELECTRICAL CHARACTERISTICS IV+ = +15 Vde, V- = -15 Vde, TA = +25 0 C unless otherwise noted)
MC1533
Symbol

Characteristic
Open Loop Voltage Gain

IT A = +25OCiD
ITA=Tlow 1 toThigh
Output Impedance
If = 20 Hz)

Typ

Max

Min

Typ

Max

40,000
35,000

60,000
50,000

-

30,000
20,000

60,000
50,000

-



'\.

+10

:.......

dURVE I

o

-5.0

0

10 k

1.0 k

100 k

1.0M

1.0 k

100

10

t, FREQUENCY 1Hz)

lOOk

10 k

t, FREQUENCY IHzl

1.0 M

FIGURE 7 - OPEN LOOP VOLTAGE GAIN versus FREQUENCY
(HIGH GAIN CONFIGURATION)

FIGURE 6 - OFFSET ADJUST CIRCUIT

11 0
10 0
0
A

~
'"
~

R3

§;

l""-

I'-

........

CURVE 1

0

f'.

4

I'-

......

~
RI

t--.

......
.........

1f'.

3~

I'-

......

I'-

0

.t
0

I'-

f'.

I'-

I'-

I'--

0

10

100

1.0 k

10k

100 k

1.0 M

t, FREQUENCY IHzl

I

v-

PIN CONNECTIONS

o

G

H

"G"Package

1

2

3

5

6

7

8

J
9

"F"Package

10

1

2

4
11

5
12

6
13

7
14

8
2

Schematic

"L"& "P"Packages

7

E

7-157

F

10

9

MC1533, MC1433

(continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 9 - VOLTAGE GAIN

FIGURE 8 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE

70 0
500 I--

versus POWER SUPPLY VOLTAGE

11 0

I
I I
~AFE O~ERATI~G AR~

t- AT REDUCED TEMPERATURE

30 0

/

200

V

V

0

1/

/

/

----

~

/

0

..... V

0

//

/
0

/

I'
70 0

5.0

10

15

20

V+ AND V-, POWER SUPPLY VOLTAGES (VOLTS)

/

/

/

/

' - E"i QUIESCENT

~

~

'"~

j

J

8.0

//
./ /'
+CMVil'l

10

~

lEA

ry

SAFl OpJTING
AT
TErERAyRE

10

12

14

16

/'
",,//

,.8 6.0

-

z

§l 4.0

18

'/

~ 2.0
00

20

,/cMV;,

,/

~

-

PErlNG ;VOlTAiE RANt E-

I

./

12

'" 8.0
~

/

6.0

~

-V..,

.L "II~ 0 V..I
"-... ~ E..1 , aUIEISCENT

IV

10 4.0

14

I

/'

I

20

/

i('...

0

30

FIGURE 10 - COMMON MODE SWING
versus POWER SUPPLY VOLTAGE

I

0

10

5.0

V+ and V-, POWER SUPPLY VOLTAGE (Vdc)

15

20

V+ AND V-, POWER SUPPLY VOLTAGES IVOlTS)
FIGURE 11 -INPUT NOISE VOLTAGE
versus SOURCE RESISTANCE

6

I

CURVE

4 BANOWIDTH
C,
2 R,

o

.0

1
2
3
50 Hz 500 Hz 50 kHz
0.1 uF 0.01 uF lOOpF
100 100 109

0
10

~

c'rl
Rs

A

'ol~
Rs B

.0 _
.0

)NPUT NOISE~
!--OUTPUT NOISE

II II

~
K

E",,,,OVdc
E

C

iJ-l
~

100

1.0 k
Rs, SOURCE RESISTANCE (OHMS)

7-158

~

10 pF

10k

100 k

~~_________O_PE_R_A_T__IO_N_A_L__A_M_P_L_IF_I_E_R_S~

MC1535
MC1435

MONOLITHIC DUAL OPERATIONAL AMPLIFIERS

MONOLITHIC DUAL
OPERATIONAL AMPLIFIERS
INTEGRATED CIRCUIT
EPITAXIAL PASSIVATED

. . . designed for use as summing amplifiers,
integrators, or amplifiers with operating characteristics as a function of the external feedback components. Ideal for chopper stabilized
applications where extremely high gain is
required with excellent stability.

~

F SUFFIX

~

CERAMIC PACKAGE
CASE 607

Typical Amplifier Features:

TO·86

•

High Open Loop Gain Characteristics - AVOL = 7,000

•
•

Low Temperature Drift - ±10 IJ.V /"C

•

Low Input Noise Voltage - O.5IJ.V

(bottom view)

,.
(top view)

Low Input Offset Voltage - 1.0mV

'.

c:J

G SUFFIX
METAL PACKAGE
CASE 6026

L SUFFIX

CERAMIC PACKAGE
CASE 632

TO-116

LARGE OUTPUT SWING CONFIGURATION (FLOATING LOAO)

HIGH Zin. OIFFERENTIAL TO SINGLE-ENOEO AMPLIFIER
10k

lin = 70 Mn min
(differential)

4.7

O.l/lF

,---I
I~

2

o.~~,

"

I

I

I

3

I

I

6

I

9

:

I
I

l:('~

~

I
I

0::'

1

10k

1\

7

I

10k
Vo=-2Vin

v-6 Vd,

8

O.l/lF

v+

I

5

I

I
I
I

"
~~~C~5~

10

-

1

47

O.Ol/lF

4

10k

+

10k

O.Ol,.,F
4.7

47

9k

-

6Vdc

See Packaging Information Section for outline dimensions.

7-159

.L

MC1535, MC1435 (continued)

EQUIVALENT CIRCUIT

CIRCUIT SCHEMATIC
INPUT LAG 1
10 11

OUTPUT LAG 1
12(4)

14(6)
INPUT
LAG 1

i'Ol; 12(4) ~~~P1UT

-I

+ (3)9

INPUT 1 _ (2)8 <>--+----'

OUTPUT 1

13(5)

v-

(1)7

<>--t-----t----H---t

(3)9

: OUTPUT 1

INPUT 1
(2)8

>-+---013(5)

vOUTPUT 2
1(7)

i

v+

+--+---<> 14(6)

(1)7

OUTPUT 2

(10)6

>-+---o

INPUT 2

1(7)

(9)5

- (10)6 <>--t---,
INPUT 2 + (9)5

~

2(8)

~~JP2UT

INPUT
LAG 2

4

3

INPUT LAG 2

2(8)
OUTPUT LAG 2

Number at end of terminal is pin number for ceramic packages.
Number in parenthesis is pin number for metal package. Input Lag available only in ceramic packages.

MAXIMUM RATINGS (T A = +250 C unless otherwise noted)
Rating

Svmbol
V+
V-

Power Supply Voltage

I

Differential I nput Signal
Common-Mode I nput Swing

MC1435

Unit

+10
-10

+9.0
-9.0

Vdc

Vin

±5.0

±5.0

Volts

CMVin

+5.0 -4.0

Volts

IL

20

+5.0 -4.0
20

Load Current
Output Short Circuit Duration

TSC

POlller Dissipation {Package Limitation!

Flat Ceramic Package
Derate above T A = +25 0 C
Metal Package
Derate above T A = +25 0 C
Ceramic Dual In-line Package
Derate above T A = +25 0 C

MC1535

rnA

Continuous

PD
MC1535F, MC1435F

500
3.3
680
4.6
625
5.0

MC1535G, MC1435G
MC1435L

Operating Temperature Range

TA
T stg

Storage Temperature Range

7-160

-55 to +125
-65 to +150

I

mW
mW/oC
mW
mW/oC
mW
mW/oC

o to +75
-65 to +150

°c
°c

MC1535, MC1435 (continued)

ELECTRICAL CHARACTERISTICS (Each Amplifier) (V+ = +6.0 Vdc V-

= -6.0 Vdc, TA = +2SoC unless otherwise noted)
MC1535

Symbol

Characteristics
Input Bias Current

11 + 12 TA = +25 0 C
Ib=-2-'TA = Tlow to Thigh

MCII135

Min

Typ

Max

Min

Typ

Max

Unit

-

1.2

3.0
6.0

-

"Ade

Ib

-

(j)

Input Offset Current
TA = +25 0 C
TA = +25 0 C to Thigh
T A = Tlow to +25 0 C

lIiol

I nput Offset Voltage
TA = +25 0C
T A = Tlow to Thigh
Differential Input Impedance (Open· Loop, f = 20 Hz)

IViol

Parallel Input Resistance
Parallel Input Capacitance

Rp
Cp

Common·Mode Input Impedance (f - 20 Hz)
Common·Mode I nput Voltage Swing
Equivalent Input Noise Voltage

Dpen Loop Voltage Gain
(T A = Tlow to Thigh)
Power Bandwidth
(AV = 1, RL = 2.0 kohms, THD~ 5%, V o =20Vp·p)

50

-

-

-

-

-

5.0
10

-

50

500
1500
1500

300
300
900

-

-

3.0
5.0

-

1.0

-

5.0
7.5

-

10

45

-

-

-

-

kohms
pF

250

-

Meg ohms

+3.0
-2.0

+3.9
-2.7

-

Vpk

-

45

-

nVI(Hz)}I

7,000

-

V/V

-

kHz

-

-

10

45
6.0
250

+3.0
-2.0

+3.9
-2.7

en

-

45

CMrej

-70

-90

AVOL

4,000

7,000

PBW

-

40

-

-

-70
10,000 3,500

40

-

1.0

-

MHz

75

-

18

-

degrees
dB

-

-

-

0.3
0.1
0.167
1.9
0.3
0.111
27
0.25
0.013

-

1.7

-

-

1.0

-

75

-

18

-

-

-

-

--

-

~ Gain = 100, 30% overshoot,
Rl = 4.7 kn, R2 = 470 kn,
R3 = 150 n, Cl = 1,000 pF

tf
tpd
dVout/dt@

~ Gain = 10, 10% overshoot,

tf
tpd
dVout/dt@

-

tf
tpd
dVout/dt@

-

0.3
0.1
0.167
1.9
0.3
0.111
27
0.25
0.013

Output Impedance (f = 20 Hz)

Zout

-

1.7

Short-Circuit Output Current

ISC
Va

-

±17

±2.5

±2.8

Rl = 47 kn, R2 = 470 kn,
R3= 47 n, Cl = 0.01 "F

~ Gai n = I, 5% overshoot.
RI = 47 kn, R2 = 47 kn,
R3=4.7n,Cl =O.I"F

Output Voltage Swing (RL = 2.0 kohms)
Power Supply Sensitivity
V- = constant, Rs ~ 10 kohms
V+ = constant, Rs~ 10 kohms
Power Supply Current (Totail
DC Quiescent Power Dissipation (Total!

5+
5ID+
ID
PD

(Vo= 0)

--

-

dB

-90

-

Unity Gain Crossover Frequency (open-loop)

Gain Margin

-

-

Phase Margin (open· loop, unity gain)

Step Response

-

mVde
1.0

CMVin

ZOn)

1.2

-

nAde

--

-

(A

= 100, Rs= 10 kohms, f= 1.0kHz, BW= 1.0 Hz)
Common·Mode Rejection Ratio (f - 100 Hz)

-

-

-

--

-

-

-

-

-

±17

±2.3

±2.7

lIS
lIS

-

VI"s

-

lIS
lIS

-

VI"s
lIS
lIS

V/"s
kohms
mAde

-

Vp

-

50
100

--

"V/V

-

8.3
8.3

15
15

mAde

-

100

180

mW

-

50
100

-

-

8.3
8.3

12.5
12.5

100

150

MATCHING CHARACTERISTICS

-

-

-

+1.0
±0.I5
±0.02
±0.1

Viol- V i02

-

±O.I

Average Temperature Coefficient

TcViol - TCVi02

-

±0.5

-

Channel Separation (See Fig. 10)
(f = 10 kHz)

eout 1

-

-60

-

Ooen Laao Voltaae Gain
Input Bias Current
Input Offset Current
Average Temperature Coefficient

Input Offset Voltage

(DTlow: OOC for MC1435

A\lnl ,-A\lnl
Ibl-l b2
liol- l i02
TCliol-TC 1i02

eout 2
®dVout/dt = Slew Rate

_55°C for MC1535
Thigh; + 7SoC for Me 1435
+12SoC for MC1535

7-161

-

±I.O
±0.15
±0.02
±'O~ I

-

dB

-

-

"A
"A
nAloC

-

±O.I

-

±0.5

-

"VlaC

-

-60

-

mV
dB

MC1535, MC1435 (continued)

TYPICAL OUTPUT CHARACTERISTICS
(v+ = +6.0 Vdc, V- = -6.0 Vdc, T A = +25 0 C
FIGURE 1 - TEST CIRCUIT
TEST CONDITIONS
FIGURE
NO.

CURVE
NO.

2

3
3A

>-<>-+---e Sout
R

L

2

I
-'_

3

'T' CL

4

__ J1< 5.0 pF

1
2
3

,,

lor

, Ior

3

--,

VOLTAGE
GAIN

100

100

10
10

lor
lor

1

1

IorAVOL
IorAVOL
AVOL
AVOL

lor:~~~

R,{,,)

R2{,,)

C,{pF)

R3{n)

47 k
47k

47 k
47k

'00,000
0

4.7

4.7k
4.7 k
47k
47k
47 k
47 k

470k
470 k
470k
470 k
47 k
47 k

',ODD
0
10.000
0
100,000
0

150

00
00

1.000
0
10.000
0
100,000
0

150

100
100
100
100
100
100

00
00
00
00

OUTPUT
NOISE

C2{pF)

00

00

47
00

4.7
00

00

47
00

4.7
00

(mVrms)

0
50,000

0.12
0.46

0
510
0
5,000
0
50.000

2.'
1.0
2.1
0.12
0.46

0
510
0
5.000
0
50.000

8.1
8.1
5.5
5.5
4.4
4.4

1.7

*Ceramic packages only.

FIGURE 2 - LARGE SIGNAL SWING
versus FREQUENCY

"'"?:
z

iiiw
«
'"':;

+60

6.0

+50

5.0

~ +40

'"
;;;:

4.0

w

f-

3.0

\

~
f-

:>
0

c

>

2.0

~

o
1.0 k

100

10 k

100 k

+20

I'

>
~ +10

\

-

1.0

'r2

o

3A

[\

1

+30

C!:I

'"

3

0

>

FIGURE 3 - VOLTAGE GAIN versus FREQUENCY

7.0

1.0 k

10k

f, FREQUENCY (Hz)

•

I'.

3

-10
100

1.0M

1.0M

100 k

FIGURE 4·- OPEN LOOP VOLTAGE GAIN
versus FREQUENCY

FIGURE 5 -INPUT OFFSET VOLTAGE
versus TEMPERATURE

140

+1.2

/

:>

5+0.8

120

'" +0.4
:i

~ 100

'";;;:

':;
0

..l

>

... V

w

3

60

r--.,2

>
0

./

~

80

r-...

40

'"
~

l'

"........

«

~

tt -0.8

1.0 k

10 k

100 k

Slope can be either polarity

... V

o

f-

........

20

100

....-V

§! -0.4

........

....

V

w

'"w
'"
«

10M

f, FREQUENCY (Hz)

:>

~ -1.2

"

1.0 M

10M

"

~--1.6
-60

1-r-MCI135-40

-20

+20

+40

-I

+60

+80

TA, AMBIENT TEMPERATURE ('C)

f, FREQUENCY (Hz)

7-162

+100

+120 +140

MC1535, MC1435 (continued)

FIGURE 6 - VOLTAGE GAIN versus
POWER SUPPLY VOLTAGE
0

w

TA =+25 0 C

~"'

0

o

,.--

>

~

o

g

0

Z

0/

W

~

o

..:.

FIGURE 8 - POWER DISSIPATION versus
POWER SUPPLY VOLTAGE

---

70 0
600
50 0

-

400

«

~

g

----- ----- --

(ii4.0

wI-

~ ~J.O

~

z'"

~ ~2.0

8
1.0
0.5
2.0

1l

--t;;""on B.O

B0

'"

60

~

40

/

0/

L
L

6.0

4.0

---

10 0

~
C

~

..-:t;;on -

~

oZ

>-

V

Z

5.0

«

20 0

o

FIGURE 7 - COMMON MODE SWING
versus POWER SUPPL Y VOLTAGE

~

50

50
75

25
50
75

100
100

0

:;

-

25
75

/

o
>

25
SAFE OPERATING AREA
AT REOUCEO TEMPERATURE

10
2.0

10

V+ and V-, POWER SUPPLY VOLTAGE (VOLTS)

/

Vi'"

'out OUIESCENT = 0 V -

..........

100

125

125

125

-

AMBIENT
T EMPERATURE
OEGREES
CENTIGRAOE

L
SAFE OPERATING AREA
rANi TEMPIERATiRE

3.0
4.0
5.0
6.0
7,0
8.0
9.0
V and V-, POWER SUPPLY VOLTAGE (Vdc)

10

FIGURE 9 - OUTPUT WIDEBAND NOISE VOLTAGE
versus SOURCE RESISTANCE

:>
.5
~

10 0
(5.0 Hz to 10 MHz)

«

C1 -l,OOOpf R3'

:;

'1~

0

o

>

f= OPEN LOOP

w

~

~

r-

~

g

C1 -l,OOOpF R3-~50!!

Av= 100

1.0

~

FAv

10

r-

1-

>t:: O. 1
100

Av

C1 - O.OI"F

R~ T17

>-.....- . eout
OUTPUT LAG

1
,\

I:;r

C1 -O.l.F R3 =5.0!!
1.0 k
10 k
Rs' SOU RCE RESISTANCE (OHMS)

100 k

RS = RB

FIGURE 10 - INDUCED INPUT SIGNAL
(CHANNEL SEPARATION) versus FREQUENCY
1000

./

00

/

10

Induced input signal (J,N of induced input signal inamplifier.:e2
per volt of output signal atamplifier:tl)

r100

e' Dul2 = e'in2

Io"
1.0 k

10k
f, FREQUENCY (Hz!

100 k

(~l, where e'out2 is the component of

eout2 due only to lack of perfect separation between the

1.0M

two amplifiers.

7-163

I

MC1536G
MC1436G
MC1436CG

~__________O_P_E_R_A_T_IO_N_A__L_A_M_P_L_I_FI_E_R_.~

HIGH VOLTAGE,INTERNALLY COMPENSATED
MONOLITHIC OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

· .. designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components.
•
•

EPITAXIAL PASSIVATED

Maximum Supply Voltage - ±40 Vdc (MC1536G)
Output Voltage Swing ±30 Vpk(min) (V+ = +36 V, V- = -36 V) (MC1536G)
±22 Vpk(min) (v+ = +28 V,
= -28 V)
Input Bias Current - 20 nA max (MC1536G)
Input Offset Current - 3.0 nA max (MC1536G)
Fast Slew Rate - 2.0 V//ls typ
Internally Compensated
Offset Voltage Null Capability
Input Over-Voltage Protection
AVOL - 500,000 typ
Characteristics Independent of Power Supply Voltages(±5.0 Vdc to ±36 Vdc)

v-

•
•
•
•
•
•
•
•

METAL PACKAGE
CASE 601
TO-99

'~
8
(bottom view)

FIGURE 1 - DIFFERENTIAL AMPLIFIER WITH ±.20 V
COMMON-MODE INPUT VOLTAGE RANGE

FIGURE 2 - VOLTAGE CONTROLLED CURRENT
SOURCE or TRANSCONDUCTANCE AMPLIFIER
WITH 0 TO 40 V COMPLIANCE

R1
lOOk

Vo = 10 (Va-VA!

RTC

R3

510

1-_ _ _ _'''''00...'--1 ~"Rk -2 mA/V
R4

-28V

R4
4.7k

FIGURE 3 - TYPICAL NON-INVERTING Xl0
VOLTAGE AMPLIFIER

Vin

~4.4

t ZO" ::~;TCCt:~;)R4~2 R4

'00'

FIGURE 4 - LOW-DRIFT SAMPLE AND HOLD

vp_p

....

>--c>-~

eOUI

9k
Ik

SAMPLE
COMMAND

See Packaging Information Section for outline dimensions.
See current MCC1536/1436 data sheet for standard linear chip information.

7-164

'Onlt due 10 biascufrent
istypiullyBmV/s

-l8V

MC1536G, MC1436G, MC1436CG (continued)

MAXIMUM RATINGS ITA = +2SOC unless otherwise noted)

I

Symbol

MCl536G

I

MC1436G

Power Supply Voltage

V+
V-

+40
-40

I

+34
-34

Differential Input Signal

Vj"

±IV+ + Iv-I-31

Volts

CMVin

+v+. -llv-I-31

Volts

TSC

5.0

Po

680
4.6

Rating

Common·Mode Input·Swing
Output Short Circuit Duration (V+

::::I

Iv-l- 28 Vdc, Va -

0)

Power Dissipation (Package Limitationl
Derate above T A'" +2SoC

-55 to +150

Operating Temperature Range

TA

Storage Temperature Range

Tst9

I

MC1436CG

Unit

+30
-30

Vde

J

,

mW
mWf'C
DC

o to +75

DC

-65 to+150

ELECTRICAL CHARACTERISTICS IV+ = +28 Vdc. V- =-28 Vdc. T A = +2SoC unless otherwise noted)
MCl536G
Characteristics

Min

SYmbol

Input Bias Current
TA = +2SoC

Ty.

MCl436G
Mo.

Min

Ty.

MC1436CG
Ma.

Min

Ty.

Max

Ib
8.0

20
35

15

40
55

25

90

1.0

3.0
4.5
7.0

5.0

10
14
14

10

25

2.0

5.0
7.0

5.0

10
14

5.0

12

T A'" Tlow to Thigh ISee Note 1)

I"put Offset Current

11;01

nAdc

TA '" +250 C

T A = +2SoC to Thigh
T A = Tlow to +25 0 C
I nput Offset Voltage

Unit
nAdc

IV;ol

mVdc

TA'" +2SoC

-

TA::: Tlow to Thigh
Differential Input Impedance IOpen-Loop, f S5.0 Hz)
Parallel Input Aesistance

10
. 2.0

Rp
Cp

Parallel Input Capacitance
Common-Mode Input Impedance (f S5.0 Hzl

ZOnl

Common-Mode Input Voltage Swing

U4

CMVin

Equivalent Input Noise Voltage

-

±25

-

±22

10
2.0

Megohms

250

250

Megohms

±18

US

pF

±20

V k

en

nV/IHz)%

(AV'" 100, As '" 10 k ohms, f = 1.0 k.Hz, BW '" 1.0 Hz)

50

Common-Mode Aejection Aatio Idcl

CMrej

Large Signal dc Open Loop Voltage Gain

AVOL

80

=+25 0 C)

Power Bandwidth (Voltage Followed

Unity Gain Crossover Frequency (open·loop)

Ie

Phase Margin (open-loop, unity gainl

cp

Gain Margin

50

110

50

90

d8
VIV

-

70,000 500.000

50.000 500.000

SO,OOO

200,000

200.000

200.001

'23

23

23

1.0

1.0

MHz

50

50

degrees

kHz
"1.0

'"

I'

;,~

. ,,50'

Output Impedance (fS 5.0 Hzl

Zout

1.0

S"ort-Circuit Output Current

ISC

·:tn,·

O"tput Voltage Swing IAL = 5.0 k ohms)

Va

V~ = +36 Vdc, V- :: -36 Vdc

:,"<

ie"

,"=:;~;

v-:: constant, As S 10 k ohms
V+ = constant, As S 10k ohms

S-

PO\l\l8r Supply Current (See Note 2)

10+

2.2

10-

:.c 2.1

5+

DC Quiescent Power Dissipation

Po

(V OI = D)

Note 2:

-

,:

...

.-

18

18

dB

2.0

2.0

V//J.s

1.0

1.0

k ohms

±17

±19

mAdc

Vpk
".;1.23 .
±22
±3Cl . ,:;.±32·

Power Supply SenSitivity (dc)

"

2.0.,

dVout/dt

V+ '" +28 Vdc, V- = -28 Vdc

~'"

,.:.

·18

AGM

Slew Aate (Unity Gainl

Thigh: +7S o C for MC1436G,CG
+1ScPC for MC1536G

70

PBW

IAV = 1, AL "" 5.0 k ohms, THDS 5%, Va = 40 Vp-p)

NOt81: Tlow: DOC for MC1436G,CG
_550 C for MC1536G

50

110

100.000. 500,000
50.000

{TA '" +250 C
TA = Tlow to Thigh

(Va"" ± 10 V, AL '" 100 k ohms)
IV o =±10V, AL '" 10k ohms, TA

250 I

10
2.0

".::

.. _>

±20

~

±22
~VIV

35

200
200

50
50

4.0:

2.6
2.6

5.0
5.0

2.6
2.6

5.0
5,0

224

146

280,

146

280

4:q

35

,:'. -:,','

!~:;::-. ,'. '124 "

mAdc

mW

V+ .. I v-I", 5.0 Vdc to 36 Vdc for MC1536G
V+ '" lv-I", 5.0 Vdc to 30 Vdc for MC1436G
V+ '" lv-I'" 5.0 Vdc to 28 Vdc for MC1436CG

7-165

±20

,',

',15:, '''100''
',15,' :'00'

"

... 22

MC1536G, MC1436G, MC1436CG (continued)

FIGURE 6 - PEAK OUTPUT VOLTAGE SWING • .,....
POWER SUPPLY VOLTAGE
35

FIGURE 5 - POWER BANDWIDTH
70

~
~
!;

40

5r;

30

w

I

0

I II

.?tf
2

50

..........

i2

:0

o

!:J

-

7

'"

4

'="

-28V

-

10k

40

20

'"

15

~

10

:=

r-

o
20

i'"
5

r6.0 8.0 10

25

60 80100

200

0

i

/
/
RL=5kn/

/

/

5.0

:0

10

4.0

~

~

"' r-.

:: 20

r- T~ = 25

w

-

'="

30

o

6 -Yo -

3

'\
'\.

~

-

/

o

-

,j

±10

400

±3o

±20

±4o

V+, V-, POWER SUPPLY VOLTAGE (Vdc)

f, FREQUENCY (kHz)

FIGURE B - OUTPUT SHORT-CIRCUIT CURRENT
.ersus TEMPERATURE

FIGURE 7 - OPEN-LOOP FREQUENCY RESPONSE
-

+140
'+'120

~ +100
z

;;:

'"w
'"

+80

:;
""

+60

>

+40

0

.....

I
~

~
a:
a:

.~

r--

24

r-...

> +20

""

-20
100

~ 20
::;
~ 16

~

0

10

28

:0

.J

1.0

32

1.0k

,.:.

"'" "'" "

10k

100 k

tOM

ili
I-

8.0

~

4.0

~

~
10M

12

100M

0
-75

+25

-25

-50

f, FREQUENCY (Hz)

.ersu. TEMPERATURE

3.2
~

:::;

2.8

! 2.4

o
l!; 2.0

i'..

"' "'

IZ

w

~ 1.6
:0

'"'

1.2

i

O.8

~
iD

...........

r--

z

~ O.4

0
-75

~

+50

-50

-25

+25

+50

+75

TA, AMBIENT TEMPERATURE (DC)

7-166

+100

+125

-

-::::::: ::---

+75

TA, AMBIENT TEMPERATURE (OC)

FIGURE 9 - INPUT BIAS CURRENT

Ei

-. ...............
SOURCE

.............

L;

:;

------ --

+100

+125

MC1536G, MC1436G, MC1436CG (continued)

FIGURE" - NON·INVERTING FEEDBACK MODEL

FIGURE 10 - INVERTING FEEDBACK MODEL

FIGURE 12 - AUDIO AMPLIFIER
lOOk
CURRENT DRAIN,
10 .. 100 mAde@!
R1

E

SHl

01.D2.D3= lN40Dl
- - - - COMMON
HEAT SINK

"k

I,·",

Vo =48 Vp-p
Po =72WlrmsIPRl=4U

Po "'3SW,rmsl@RL-8n

• .1

v- = -30 Vdc

FIGURE 13 - CIRCUIT SCHEMATIC

FIGURE 14 - EaUIVALENT CIRCUIT

v'

1

INVERTING

Vin

Zin

v.

t-+-4-'!e OUTPUT
NON
INVERTING
5

L~...J

___ ..Jt OFFSET
ADJUST
v·

7-167

MC1537
MC1437

\

....._ _ _ _O_PE_R_A_T_I_O_N_A_L_A_M_P_L_I_F_IE_R_S----'

HIGHLY MATCHED
MONOLITHIC DUAL OPERATIONAL AMPLIFIERS
DUAL MC1709
MONOLITHIC SILICON
OPERATIONAL AMPLIFIERS
INTEGRATED CIRCUIT

... designed for use as summing amplifiers, integrators, or amplifiers
with operating characteristics as a function of the external feedback
components. Ideal for chopper stabilized applications where ex·
tremely high gain is required with excellent stability.
Typical Amplifier Features:
• High·Performance Open Loop Gain Characteristics AVOL = 45,000 typical
•
•

Low Temperature Drift -±3p.V/oC
Large Output Voltage Swing ± 14 V typical @± 15 V Supply

MAXIMUM RATINGS

(T

P SUFFIX
PLASTIC PACKAGE
CASE 646

°

TO·116

= +25 C)

Rating

Symbol

Value

Unit

Power Supply Voltage

V+

+18

Vdc

V-

-18

Vdc

Differential I nput Signal

Vin

±5.0

Volts

CMVin

±V+

Volts

Output Short Circuit Duration

ts

5.0

5

Power Dissipation (Package Limitation)
Ceramic Package

PD
750
6.0
625
5.0

mW
mW/oC
mW
mW/oC

Common Mode I nput Swing

Derate above T A

=+25 0 C

Plastic Package
Derate above T A = +25 0 C

Operating Temperature Range
MC1537
MC1437

Storage Temperature Range

-55 to +125
o to +75
T stg

-65 to +150

c::J

14
(top view)

1

°c

TA

(MC1437 only)

L SUFFIX
CERAMIC PACK·AGE
CASE 632
TO-116

.....,.:
~WtllF

°c

FIGURE 1 - CIRCUIT SCHEMATIC

FIGURE 2 - EQUIVALENT CIRCUIT

'---'-'+~+--+__-""':::TP.:.:"'.o' "

,-+--:+---0"
OUTPUT I

""

INVERTINGo-!----F=--'
INPUT I

INVERTING

INPUT 2o-!'----f':-,
NON-n'WERTING

See Packaging Information Section for outline dimensions.

7-168

MC1537, MC1437 (continued)
ELECTRICAL CHARACTERISTICS -

Each Amplifier IV+ = +15 Vdc, V- = -15 Vdc, T A = 250 C unless otherwise noted)

MC1537
Symbol

Characteristic

Open Loop Voltage Gain
IRL = 5.0 kn, Vo = ± 10 V,

MC1437

Min

Typ

Max

Min

Typ

Max

25,000

45,000

70,000

15,000

45,000

-

Zo

-

30

-

-

30

-

n

Zin

150

400

-

50

150

-

kn

±14
±13

-

±12

±14

-

Vpeak

±12
±10

Unit

-

AVOL

TA = Tlow(j)to Thigh@)
Output Impedance

"If = 20 Hz)
I nput Impedance

If = 20 HzI
Output Voltage Swing

Vo

IRL = 10 knl
IRL = 2.0 knl
Input Common-Mode Voltage Swing

CMVin

±8.0

±10

Common-Mode Rejection Ratio

CMrej

70

100

Input Bias Current

~b=ll;12),

-

-

-

±8.0

±10

65

100

-

Ib

-

ITA = +250 CI

0.2

0.5

0.5

1.5

-

0.05

0.2

l1io= 11- 12. TA =Tlow(j)1

-

-

l1io = 11 - 12, TA = Thigh@1

-

-

-

0.4

1.5

-

2.0

-

0.05

0.5

-

0.75

-

0.75

-

1.0

7.5

-

10

Iliol

j.lA

l1io = II - 121

Input Offset Voltage
ITA = +25 0 CI

dB
j.lA

IT A = Tlow (j) I

Input Offset Current

Voeak

IViol

-

IT A = Tlow(j)to Thigh@1

0.5

-

0.2

1.0

5.0

-

6.0

mV

Step Response

{Gain = 100,5% overshoot,
Rl = 1 kn, R2 = 100 kn,

}

-

dVout/dt @

-

12

-

-

0.6

-

0.34

-

dVout/dt @

-

tf

-

2.2

tpd
dVout/dt@

-

1.3

-

0.26

tpd

~ R3= 1.5 kn, Cl = 500pF, C2 =20pF

l

-

0.38

-

tf

Rl = 1 kn,R2= 10kn,

~ Gain = 1, 5% overshoot,
Rl = 10kn, R2= 10kn,

-

tf

R3 = 1.5 kn, Cl = 100pF, C2 = 3.0 pF
( Gain = 10, 10% overshoot,

0.8

tpd

}

J

R3 = 1.5 kn, Cl = 5000 pF, C2 = 200 pF

Average Temperature Coefficient of

-

-

-

j.lS

12

-

V/j.ls

-

0.6
0.34

-

j.lS

-

1.7

-

V/j.ls

-

2.2

-

1.3

j.lS

-

0.25

-

ITCViol

j.lS

j.lS

j.lS
V/j.ls
j.lV/oC

I nput Offset Voltage
IRS = 50 n, T A = Tlow CD to Thigh @I
IRS~10kn, TA = TlowCDto Thlllh @I
Average Temperature Coefficient of

1.7

0.8
0.38

-

-

1.5
3.0

-

0.7

-

-

-

1.5
3.0

-

-

ITCliol

nA/oC

Input Offset Voltage
(T A = Tlow (j) to +25 0 C)
ITA = +25 0 C to Thigh @)

-

0.7

-

-

-

0.7

-

0.7

-

DC Power Dissipation ITotal1
(Power Supply = ± 15 V, Vo = 01

Po

-

160

225

-

160

225

mW

Positive Supply Sensitivity

S+

-

10

150

-

10

200

j.lVN

S-

-

10

150

-

10

200

j.lVN

IV- constant)
Negative Supply Sensitivity

IV+ constant I



~ -6.0
0._ 8.0

>0 -10

I

+10

i

1/

-12
-14

1

-5.0
10

100

10 k

1.0 k

100 k

1.0 M

10

1.0 k

100

f, FREQUENCY (Hz)

~

II
I1ilJ

80

IIII
fIti

CURVE 11'.

z

:;;:

..

'"w
'"'::;
0

>

1'-.... .....

4

r-.....~
r-.....
,,~

..:l

..

3

.....

60

40

I(RL=~)
'i

I
'-l

21'-

0

>
20

1.0 M

500

U

I

300

10

5

1'-.. .

I

200 ( - - I-

gj

,,~

'"w

i5 50

~

/

30

/

C

... 20

I

~~s~T~~~;OA~~~~I~~T~~:~~~~ ~~~~~~ ~g~~~~~D¢~~!ig~s ~URVE I

10
1.0k 2.0k 5.0kl0k

100 k

V

l/

z

~ 100

~ .....

,..

I

V.=OVOLT

oS

~~
100

100 k

FIGURE 7 - TOTAL POWER DISSIPATION
venus POWER SUPPLY VOLTAGE

o
10

10 k

f, FREQUENCY (Hz)

FIGURE 6 - OPEN LOOP VOLTAGE GAIN
venus FREQUENCY
100

=~)

CU RVE 4

I

w

-

FIGURE 5 - VOLTAGE GAIN versus FREQUENCY

3&4

2

R3(1l)

1
2
3
4

II

I'\.

R2(1l)

4

FIGURE 4 - LARGE SIGNAL SWING
versus FREQUENCY
+14
_ +12

OUTPUT
NOISE

TEST CONDITIONS
Rl(ll)

1.0M

4.0

f, FREQUENCY (Hz)

6.0

8.0

V+ ANO

7-170

10

I

I

I

12

14

16

v-; POWER SUPPLY (Vdc)

18

MC1537, MC1437 (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE B - VOLTAGE GAIN ve,sus
POWER SUPPLY VOLTAGE

-

TA"'25 0C

z
~

90

'"'"
~

>

80

V
/

o
o

z

w

70

o

2! 16

'"z
illw
'"

~

o

v

V/
/ / ~+CMVjn
f'

0

10

4

",

2

il

20

15

0

o

AND V-, POWER SUPPLY VOLTAGE (VOLTS)

FIGURE 10 -INPUT OFFSET VOLTAGE
versus TEMPERATURE

10
15
5.0
v+ AND V-, POWER SUPPLY VOLTAGE (VOLTS)

20

FIGURE 11 - OUTPUT NOISE VOLTAGE
versus SOURCE RESISTANCE

:;+0. 6
.§

100~~~~~~~~~~~~~~~~~~l!1
~C,"'0pFC2"3.0pFR3"0

~tO. 4

>"

......1'--.

'"G+o. 2
'"~

-CMY V

8

,.
,.z

0
0

8•
5.0

t

./

10

;o-

60

/'

14
12

>

/

~

'"

/

V-

FIGURE 9 - COMMON INPUT SWING
versus POWER SUPPLY VOLTAGE

18

~

100

.......

............

~-O.4

~

o

-20

+20 +40
+60
+80
+100 +120
TA. AMBIENT TEMPERATURE (DC)

_ _ AV=100 C,=100pF C2=3.0pF R3=1.Sk

AV=10 C,"510pF C2=20pF R3=1.Sk

><

-40

III

~10~.~.~~1
~

-..........

...... ~

-.-0.6
~
-o.B
-60

1111

>

..........
.........

o

OPEN LOOP

~ 10 = = AV=1000 C,"10pF C2=3.0pF R3=0

.........

0

>
~-O. 2

~

Slope can be either polarity.

+140

~A~V~"~1~.0~C'~"EO£'Of05E"rnF~C~2~"320~0~PFER!33"~'3·5ik~~~~Elii~

0.1
100

1.0k
10k
RS. SOU RCE RESIST ANCE (OHMS)

lOOk

FIGURE 12 - INDUCED OUTPUT SIGNAL
(CHANNEL SEPARATION) ve,sus FREQUENCY
10,00 0

~

.3

•

mlmllmll

~

~
....

1000

in

=>
~

g
c

w
u

10 0

=>
c

z

1 0 " 1.0 k
10 k
lOOk
100
f. FREQUENCY 1Hz!

7-171

Induced output signal (SJ,V of induced output signal in
amplifier #2 per volt of output signal at amplifier #1).

MC1538R
MC1438R

1L~

_______________

P_O_W_E_R__B_O_O_ST_E_R__~

MONOLITHIC POWER BOOSTER
The MC1538/MC1438 is designed as a high current gain amplifier
(70 dB), with unity voltage gain that can deliver load currents up to
±300 mAdc. This device is ideally suited to follow an operational
amplifier (such as MC1556/MC1456) for driving low impedance loads
and improving the overall circuit performance.
• High Input Impedance - 0.4 Meg·Ohm typ - when driving the
MC1538/MC1438, the gain of an operational amplifier will
approach the unloaded open·loop gain. Internal power dissipa·
tion of the operational amplifier will be independent of output
voltage and therefore thermal drift will be reduced.

POWER BOOSTER
INTEGRATED CIRCUIT FOR
OPERATIONAL AMPLIFIERS
EPITAXIAL PASSIVATED

CASE 614

• Large Power Bandwidth -1.5 MHz typ - considerably better than
present operational amplifiers. Bandwidth and slew rate will be
limited by the operational amplifier, not the MC1538/MC1438.
•

Low Output Impedance - 10 Ohms typ - allows the MC1538/
MC1438 to drive a capacitive load with greatly reduced phase
shift compared with an operational amplifier. Output voltage
swing capability is much increased when driving small load im·
pedances.

• Adjustable Current Limit - ±5.0 mAdc to ±300 mAdc
• Excellent Power·Supply Rejection - 1.0 mV!V typ
• Current Gain - 3000 typ

Welllht~6.315

grams

elise connected to V-

TYPICAL APPLICATIONS
OPERATIONAL AMPLIFIER BOOST CIRCUIT

DIGITAL OR ANALOG LINE DRIVER

r-r----

•

Vout",Vin

RA

39

Vout

Yin

Zout"50n

RD -Z Ou t-10n

POWER SUPPLY SPLITTER

SERVO/POWER AMPLIFIER

See Packaging Information Section for outline dimensions.

7-172

MC1538R, MC1438R (continued)

MAXIMUM RATINGS (TC = +25 0 C unless otherwise noted)
Symbol

MC153BR

MC143BR

V+
V-

+22

+18

-22

-18

Vin- Vout

-14.5, +44

-14, +36

Rating
Power Supply Voltage
Input-Qutput Voltage Differential

Unit
Vde
Vdc

IVinl

V+or V-

Vdc

IL

350

mAde

Thermal Resistance, Junction to Air

Po
1/9JA
9JA

3.0
24
41.6

Watts
mW/oC
°C/W

TC = +250 C
Derate above T C = +250 C
Thermal Resistance, Junction to Case

Po
1I9JC
9JC

17.5
140
7.15

Watts
mW/oC

TJ,Tstg

-65 to +150

°c

TA

o to +75
-55 to +125

°c

Input Voltage Swing
Load Current

Power Dissipation and Thermal Characteristics
TA = +2SoC
Derate above T A = +250 C

Operating and Storage Junction Temperature Range

°C/W

OPERATING TEMPERATURE RANGE
Ambient Temperature

MCI438R
MCI538R

ELECTRICAL CHARACTERISTICS
(RL = 300 ohms, TC = +2S'c unless otherwise noted.)
MCI538R
V+ -+5V to +20 V, V-· -5Vto -20 V

Characteristic (Lina.r Operation)

MCI438R
V+.+15V,V-·-15V

Fig

Not.

Symbol

Min

Typ

Mox

Min

Typ

Max

Unit

Voltage Gain If = 1.0 kHz)

1

-

AV

0.9

0,95

1.0

0.85

0.95

1.0

V/V

Current Gain (AI = Alo/Alin)

1

-

AI

3000

-

-

3000

-

Output Impedance (f - 1.0 kHz)

1

-

Zout

-

10

-

-

400

±11

±12
60

300

"Adc

150

-

25

200

mVdc

8.0

-

-

8.0

-

MHz

1.5

-

1.5

-

MHz

0.5

-

-

0.5

-

Input Impedance (f = 1.0 kHz)

1

-

Zin

-

400

Output VoltageSwingl

1

3

Vout

±12

±13

Input Bias Current

2

-

Ib

-

60

200

-

25

-

Output Offset Voltage

2

1

Voo

Small Signal Bandwidth
(RL = 300 ohms)
(Vin=OVdc,vin= lOOmV[rmsl)

1

-

BW3dB

Power Bandwidth
(Vout = 20 V p_p, THO = 5%)

1

3

P8W

Total Harmonic Distortion
(f = 1.0 kHz, V out = 20 V~)

1

3

THO

Shan-Circuit Output Current

-

3
3
4,5

2

Power Supply Sensitivity
(V- constant!
(V+ constant)

2

-

Power SupplV Current
(RL = co, Yin = 0)

2

Power Dissipation
(RL = co, Yin = OJ

2

75

--

95

300
5.010 300

125

-

65

-

kohms
Vdc

%

140
95
300
5.0 to 300

-

mV/v

S+
S-

-

-

1.0
1.0

-

-

1.0
1.0

-

ID+orID

4.5

6.0

10

2.5

6.0

15

mAde

3

Po

150

180

300

75

180

450

mW

-

-

Note 1.

Output offset Voltage II the quiescent dc output voltage with the Input grounded.

Note 2.

Short·Circult Current. ISC. Is adJultable by varying R1. R2, R3 and R4. The pOlitive current limit Is set by R 1 or A3. and
the negative current limit il set bV A2 or A4. See Figures 4 and 5 for curve. of .hort~lrcuit current versus R 1, A2, A3 and A4.
V+=+15V,V-=-15V.

Note 3.

Ohms

mAde

ISC

(Rl = R2=co)
(Rl = R2 = 3.3. ohms)
Adjustable Range

A/A

-

-

10

7-173

MC1538R, MC1438R (continued)

TEST CIRCUITS

CIRCUIT SCHEMATIC

v·
.--.----------~----------~----------~--~--~8

300

400

300

Positive Current
Limit Adjust
7.0

500

Positive Output
Positive Current

Sense

Input 9 0 - - + - - - - - - - - - + - - - - + - - - - 4

Negative Current
Sense
Negative Output

Negative Current
limit Adjust

7.0 V

300

300

300

v-

~

L--------~~--~~--~------~~~~~-OCase

~
(bottomv;!lw)

Case isc:onnec:ted toV-

TYPICAL CHARACTERISTICS
(V+ = + 15 Vdc, V- = -15 Vdc, T A = +250 C unless otherwise noted)
FIGURE 4 - SHORT-CIRCUIT CURRENT versus Rl OR R2

FIGURE 5 - SHORT-CIRCUIT CURRENT versus R3 OR R4

(100 rnA to 300 rnA)

400

(5.0 rnA to 100 mAl

r---r--,--,--'---r--r-~--r---r--

I 300 1-"'-+-+--+j

120

I 100

'Yin

i"

!: 2001--+-'<;+--+-

~

~

100~-+-+-+_=r=t=I=:j:=:I==l=~
1---t-+-+--+-+---1 ~~ t:~:::~

!..

A1 OR R2(OHMS)

SO
4D

R3 OR R4 (OHMS)

7-174

MC1538R, MC1438R (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 6 - POWER SUPPLY
FIGURE 7 - SMALL SIGNAL GAIN AND PHASE RESPONSE

CURRENT versus SHUNT RESISTANCE
13

:1l

""-

12

.5
>-

~

11

~

10

~

~

'"

~

E

~

O-r-.

lIin =10

--

TA = +125 0C

!
~
o

>

i
8.0

t--

1-55ac

TA

-3. a

PhaseShifl

'

I

II

1111
2.0

1.0

50~

\

1\

-6.0

16

>-

1\

-9.0
4.0

20"ffi

i\.

-5,0

-8.0

7.0

10

,,~

-2. a

~ -4.0

t-- TA -+25 aC

9.0

-1.0

Rl- R2 •
R3- R4 - 0 -

!

5.0

80

1\
20

10

30

90

50

100

f. FREOUENCY (MHz)

Rl OR R2. SHUNT RESISTANCE (OHMS)

FIGURE 8 - POSITIVE OUTPUT

FIGURE 9 - NEGATIVE OUTPUT
VOLTAGE SWING versus LOAD CURRENT

VOLTAGE SWING ve,sus LOAD CURRENT
10
Rl-I R2-ool •

t - - t - - t - - t - - r - R3 _ R4 _ a

~

..
W

to

t--t--+--+-

~

0

>

I---+-+-+-- ~~: ~~:~. -+-+-+H

-+--+--++---1

~

l

Vin adjUsted for

with Il - O.

Vo~t = +10 Vdc +-+t--i

.

t--t--t--+- Vin I'djuste~ far Va~t - -1 0 Vde--+_~H---1

W

to

~

with Il = O.

0

5.0

> -5.0

>=>

~

0

0

~

~

:==>

~
~

a

-10
0

20

40

BO

60

100

a

40

20

Il. lOAD CURRENT (mAde)

60

80

100

Il. lOAD CURRENT (mAde)

FIGURE 10 - OUTPUT OFFSET VOLTAGE

versus TEMPERATURE
30

~
> 25

.5

.

y+ - 5.0 Vde. V- - -5.0 Vde
~y+

'"
~

0

>

i
>=>

10

I

0

:l

I
I
I

I

15

:=g

~

-20 Vde

,,

20

I
I
I

I
I

I

I
I

I

5.0

-50

-25

~

\

I

~
-75

~

I

I

>

70

,

15 Vde. V- - -15 Vde

v+ - 20 Vde. V- -

w

FIGURE 11 - INPUT BIAS CURRENT versus TEMPERATURE
I
I

MC1438
LIMITS

25

e.---:

50

75

40L-__

100

-75

125

~

-50

__

~

____L-__

-25

~

25

__

~

____L-__

50

75

TA. AMBIENT TEMPERATURE (a C)

TA. AMBIENT TEMPERATURE (a C)
·See figures 4 and 5 for definition of A 1, R2.R3, and R4.

7-175

~

100

__

~

125

MC1538R, MC1438R (continued)

TYPICAL CHARACTERISTICS (continued)
(V+

=+15 Vdc. V- =-15 Vdc. TA =+25 0 C unless otherwise noted)

FIGURE 12 - PULSE RESPONSE CHARACTERISTICS

:r

10
B.O
~
0

w~

4.0

~~ 2.0

~~
>0

.... >

~!;

~J~:

C;::;J

>0

I

6.0

o:~

0

FIGURE 13 - DC SAFE OPERATING AREA
500
400
300
_ 250
~ 200
E 150

r--

I

:\output

if
1

Input l

RL = 300 ohms

~ 10 0

-2.0

--0-........ eout

v-

See Packaging Information Section for outline dimensions.
See current

MeC' 539/1439 data

sheet for standard linear chip information.

7-178

MC1539, MC1439 (continued)

ELECTRICAL CHARACTERISTICS (v+ '" +15 Vdc, V-

=

-15 Vdc, TA

=

+2SoC unless otherwise noted)

MCI539
Characteristic

Symbol

Input Bias Current

ITA

=

Min

0.20
0.23

0.50
0.70

20

75
60

Min

TVp

Ma.

0.20

0.23

1.0
1.5

20

150
100

nA

11;01

Tlcw)

(TA = +2S0C)

150

75

ITA=Th;ghQ)1
Input Offset Voltage
(TA = +2SoC)

mV

IV;ol

1.0

IT A = Tic....,. Thigh)
Average Temperature Coefficient of Input
Offset Voltage {T A = Tlcw to Thigh}

3.0
4.0

2.0

7.5

jJV/oC

ITCV;ol

IRS = 50 nl
IRS<10 knl

3.0
5.0

Input Impedance
(f = 20 Hz)
Input Common-Mode Voltage Swing
Equivalent Input Noise Voltage

Unit

.A

+2SoC)

ITA = TlowQ) 1
=

Ma.

Ib

Input Offset Current

ITA

MC1439

tvp

3.0
5.0

Zin

150

300

100

300

CMVin

±Il

±12

±-II

±12

Vpk

30

nV/(Hz)%

dB

30

en

kn

(AS"" 10 kn, Noise Bandwidth"" 1.0 Hz,
f = 1.0 kHz)

Common-Mode Rejection Ratio
(f = 1.0 kHz)
Open-Loop Voltage Gain (Va -

10kn, RS=OOj

IT A =

80

110

80

110

50.000
25.000

120.000
100.000

15.000
15.000

100.000
100.000

10

50

CMrej

± 10 V, RL

AVOL

+2SD C to Thigh)

(TA '" Tlow)
Power Bandwidth IAv - 1, THO .$5%,
Vo'" 20 Vp-p}

kH,

PBW

IRL = 2.0 knl
IRL = 1.0 knl

50

20

Step Response

{ Ga;n = 1000. no ov."hoot.
Rl

f

=

}

1.0k!l, R2= 1.0M!1, R3= 1.0kfl.

R4.:: 30kn, RS = 10 kIl. Cl

=

1000 pF

Ga;n = 1000. 15% ov",hoot.
Rl

=

}

1.0 kil, R2::; 1.0 Mil, R3= 1.0 kn.

, R4=O,R5=10kn,Cl = 10pF

tf

130

130

tpd

190

190

dVout/dt(£

6.0

6.0

tf

80

80
100

tpd

100

dVout/dt

14

14

{ Ga;n = 100. no ove"hoot.
}
Rl = 1.0kn, R2 = lOOkn, R3= 1.0 kil.

tf

60

60

tpd

100

100

R4 = 10 kil. AS= 10 kil. Cl '" 2200pF

dVout/dt

34

34

tf

120

120

{ Ga;n = 10. 15% ove"hoot.

}

V/J.ls

V/jJs

V/lls

tpd

80

80

R4 = 1.0kn, AS = 10 kn. Cl = 2200pF

dVout/dt

6.25

6.25

{ Ga;n = 1. 15% omshoot.
}
Rl = 10 kn. R2= 10 kfl. R3 = 5.0 kil.

tf

160

160

tpd

R4= 390 n. RS = 10kn. Cl = 2200pF

dVout/dt

80
4.2

4.2

V/lls

Zout

4.0

4.0

kn

Rl

=

1.0k11, R2::: 10 kn. R3= 1.0kn.

Output Impedance

V/p,s

80

If = 20 H,I
Output Voltage Swing
(RL = 2.0 kil. f = 1.0 kHz)
tRL

=

V out

Positive Supply Sensitivity

Vpk
±10
±-10

1.0 kn. f = 1.0 kHz)

±13

±13

S+

50

150

50

200

.VlV

S-

50

150

50

200

.VIV

10+

3.0

5.0

3.0

6.7

mAde

10-

3.0

5.0

3.0

6.7

(V- constant!

Negative Supply Sensitivity
fV+ constant)
Power Supply Current

IVo =01

(!)Tlow = OoC for MC1439
- 55°C for MC1539

Thigh = +750 C for MC1439
+ 125°C for MC 1539

®dVout/dt = Slew Rate

7-179

MC1539, MC1439 (continued)

MAXIMUM RATINGS (TA

=+25 0 C unless otherwise noted)

Rating

Svmbol

Value

Unit

V+
V-

+18
-18

Vdc
Vdc

Power SupplV Voltage

Vin

±[v++lv-U

Vdc

CMVin

+V+.-Iv-I

Vdc

15

mA

Differential Input Signal
Common Mode I nput Swing
Load Current

IL

Output Short Circuit Duration

ts

Power Dissipation (Package Limitation)

Po

Continuous
680
4.6
750
6.0
625
5.0

mW
mW/oC
mW
mW/oC
mW
mW/oC

-55 to +125
Oto+75

°c

Metal Can

Derate above T A

=+2SoC

Ceramic Dual In-Line Package

Derate above T A = +2SoC
Plastic Duslln-Line Package
Derate above T A = +2So C

Operating Temperature Range MC1539

TA

MC1439

Storage Temperature Range

°c

T stg

Metal and Ceramic Packages
Plastic Package

-65 to +150
-55to+125

FIGURE 5 - EQUIVALENT CIRCUIT

FIGURE 4 - CIRCUIT SCHEMATIC

11111·o;V·:-----,,-"""1---""1'-,,------"'1"----,

1 (n)

8(12)

INPUT
LAG

13} 10-------+-+---+--+--,
INPUT LAG
(12)8
(4)2

INVERTING INPUT

1.I2O--w......,.....,.-{.

40

"

I"-\Mr-':;;"-.os

6001

Rout

~-__+-t--OOUTPUT

15130--"""-'-<>--+---'
"

40

nO)

1M3

NON-INVERTING INPUT

19150-------+-----\------'

OUTPUT LAG

(9) 5

vI" .0---____
.....__-4-_ _ _ _ _ _ _ _-4-_ _.....- - '

OUTPUT
LAG

Pin numbers.djKenllD t.rmlnalslpplv to 8-pin plll:kage,.numbersinparenlhesit.ppIYl0 14-pin,oackagts.
Pln7iselettricllllyconnectlldlolhBsubstrataandY- for C. . 6461p1astic packagl) only.
·PalentPlndir.;r.

TYPICAL CHARACTERISTICS
(v+

=+15 Vdc. V- =-15 Vdc. TA = +250 C)

FIGURE 6 - TEST CIRCUIT
R,

TYPICAL OUTPUT CHARACTERISTICS
IV+-+15Vd<:,V---1SVctc,TA-2SoCI
TEST CONDITIONS (FIGURE II
FIGURE

NO.

CURVE
NO.

..
.....,

VOLTAGE
GAIN

AVOL

7,B,10,12

I~

.000

""

ALL
ALL

.000

R, tnl

R21rt1

R31nl

Igk
1.0k
1.0k
I.Ok
I.Ok
.Ok

10k
.Ok

S.Ok
1.0k

1.0M

1.0k
S.Ok

.."
I.OM
'Ok

.""

1.0M

0

tg~

Rel nl

m

~~
0

."

!;'Sml

C,(pFI

,;;\

".,

'Ok
'Ok
IO.
'Ok

..

.",

0

2200

"'"
'~

".,

7-180

MC1539, MC1439 (continued)

TYPICAL CHARACTERISTICS (continued)
(V+ = +15 Vdc. V-

=-15 Vdc. TA = 25°C. unless otherwise noted)

FIGURE 7 - LARGE SIGNAL SWING versus FREQUENCY

FIGURE 8-0PEN LOOP VOLTAGE GAIN versus FREQUENCY

110

24
22

11

0
S

W

6

':;
0

>

14
12

~

10

~

8.0

~

'"'"

o

"-

'"
'"
'"'"':;

I\.

1\

.
..

2 ' 3

0

z

40

0

30

>

\ 1\

6

50 60

g

4

4.0
2.0

-

o

RL=I.OkO HM

.0

20

'"

10

>

II

"'n71 III
10 k

0

100 k

~

I.OM

10 k

1.0 k

i!:

o

J

~

40

6

4

l

~12 ~O( T SLpplLIks

r- H-

::--.

20

±15 VOLT SUPPLIES

60

:--0::

ti: 80

5.0

'"

~

fy~'f~ft

e ....

160
180

1"-.

200

300

500 700 1.0 k
2.0k 3.0k
RL. LOAD RESISTANCE 10HMS)

5.0k7.0kIOk

100

10

,

1.0 k

100 k

1.0 M

FIGURE 12 - CLOSED LOOP GAIN versus FREQUENCY

I Rr30kOH~

50

~.

.!>

:;;

z

..g
;;'

12~-t--+--4--~--~~~~~

'"o

r--':-""""~--.

'W

10 k

f. FREQUENCY IHzl

~

11

......

~

200

.:!l
]. 13

f--t---t---t--7'f-

!;

~

.'\
2

60

~

3

......

a.. 140

FIGURE II-OUTPUT VOLTAGE SWING
Ito clipping) versus SUPPL Y

o
>

5

~ 120

~

0
100

'"~

~

w

~V
.&~

10M

11111
II
~I~I~ 2.0U~~~

~

~

~ 100

15

10

I

I.OM

FIGURE 10 -OPEN LOOP PHASE SHIFT versus FREQUENCY

25

:>
:>

100 k

f. FREQUENCY 1Hz!

±IS VOLT SUPPLIES

...

I

3

30

'"
~
g

5\,
4

21

100

FIGURE 9 - OUTPUT VOLTAGE
SWING versus LOAD RESISTANCE

20

I'-

o

f. FREnUENCY 1Hz)

W

I'

w

-

1.0k

t

t'-

1\6

~

ARR OWS INDICATE
UNC OMPENSATEO
POL E LOCATIONS

II

II
RL - 2.0 k OHMS

!'

70

0

1111111
111111

i"'-.

80

w

\.

5

t--.

90

;;'

1\

~ 6.0

>

~ 100

1.0 k

o

.j

CI = 1000pF

~

10~W IJ I = 2ioo ~F

R4 Id k
40

JllllillL IL
I

0
R4

~
~

0

d

10

'"

I

J

I IIUIII
I 11111111

10 k

I L

~
4

~

\

I I

\

I 1111111
I I
lOOk
f. FREQUENCY IHzl

I.OM

O~~~~ ~\I= 220h

• ACL '" Closed Loop Gain

Pin numbers adjacent to terminals apply to 8-pin package. numbers in parenthesis apply to 14·pin packages.

7-181

5

~

i

R4 =139J

1.0k

R4=0~IJ

CI = 10 pF

~ I.~ JdJJ~ ~II = 22ho JF

I

9.0 ......--'-_I--......._'--'-_.L-...J..._'--'-_.L-...J...---J
±13
±IS
±14
±12
±15
±16
±17
SUPPLY VOLTAGE IVOLTS)

,~

3

\
2
10M

•

MC1539, MC1439(continued)

FIGURE 13 - ACL· = 1 RESPONSE versus TEMPERATURE

FIGURE 14 - ACL = 10 RESPONSE versus TEMPERATURE
+40
+3 5

+15

~ +30

~ +10
z

z

~ +2 5

~ +5.0

gc.. +20

~

""-'
~ -5.0

cj +10

ci

:t-' t5.0

-10

<

'rn

-

15)
+
I
10k 3
13) 1.0 k

10k

FIGURE 15 - ACL = 100 RESPONSE versus TEMPERATURE

60

ein

'"
~

z

50

I--~ 45 I--~

~
!jl

f

-

85

I~

1.0 k

6

~

eout

z
:;: 70

13) 10 k

-55°C

40

~

35

+250 C

\\

d 30
cl

20

+llirll

15

11111
10

1.0

'"
"g

65

!

55

~

< 25

em

;;;
:s 75

8 112)
2200 pF

+
3 I

1111'

80

(10)

14)

100

cl

\

w

o
z

150

\

10M

~

~

60

~
i

10

100

1.0k

11
+25 DC

.....

+125 DC
100

10

~

--"

14)

=
==~ I
~

~

~

V

-

10

w

~

(5) +
A3 3 I

~ 13)

6
8112)
CI

II
,,

_~5olc

1.0M

10 M

R4

Vo

R _ AI A2
3 AI + AZ
AV = A2
AI
AS= R3

=FAV=IOOO

~

oz

~

-

1000 pF

13) 30k

"""":

AV -100

~

50

81121

FIGURE 18 -OUTPUT NOISE versus SOURCE RESISTANCE

~

f'.

eout

6

50

100

§ 100
<
>

~I
-

f. FREQUENCY 1kHz)

F?t>

1\

10M

I

(4)

(5) +

35
1.0

1111' ~~ =IJO I /I

~

I III

1.0M

< 45

FIGURE 17 -SPECTRAL NOISE DENSITY

1200

+125 0 C

1.0 k 3 I

f. FREQUENCY 1kHz)

25 0

ill
IIII

40

1.0M

~J50C
ITII!

\

FIGURE 16 - ACL = 1000 RESPONSE versus TEMPERATURE

f-t~l;~ i

55 f--

out

100 k
f. FREQUENCY 1kHz)

f. FREQUENCY 1kHz!

65

8112)
2200 pF

~

-5.0
1.0 k

~

110)
6

10 k

-15
-20 '---'-LLlllJLlL-LJ.JLJ..LUlL_L....L..J....L1ill'---'-.L.J...Lll.lJJ
1.0k
100 k
1.0 M
10 M

~ f-- 55OC

'~~,,

~ +15 f--

ffi

1.0

AV -10

>
~ rAv=1

I,

O. I
10k

100 k

f. FREQUENCY 1Hz)

0.1

/I II
1.0
10
RS. SOURCE RESISTANCE (k OHMS)

• ACL = Closed Loop Gain

Pin numbers adjacent to terminals apply to B-pin package, numbers in parenthesis apply to 14'pin packages.

7-182

100

MC1539, MC1439(continued)

TYPICAL CHARACTERISTICS (continued)
(V+ = +15 Vdc, V- = -15 Vdc, TA = 250 C, unless otherwise noted)
FIGURE 20 - POWER DISSIPATION versu'
POWER SUPPLY VOLTAGE

FIGURE 19 - POWER DISSIPATION versu,TEMPERATURE
130

20 0

I

Va =0
±15 V SUPPLlES-

120

L:1.0kil
THO: 5% _ _

-_li

0

11 0

z
o

-- -----Vo:O-

~

0

100

gj
0:.---

'"
~
w

---

..-

0

i5

RL : -

0

~ 70
60

srE OPERATING AIREA (-55 to +125T

50
-55

+25

-25

+50

+75

+100

10
10

+125

12

14

16

18

TA, AMBI ENT TEMPERATURE (OCI
V+ AND V-, POWER SUPPLY VOLTAGE (VOLTS)

FIGURE 22 - COMMON·MODE INPUT VOLTAGE
versus SUPPL Y VOLTAGE

FIGURE 21 - POWER BANDWIDTH
(LARGE SIGNAL SWING versus FREOUENCY)
+12

~

18

+10

~

17 -

Q.

+8.0

w

'"z

+5.0

~

~
w

'"~

0

«
'"':;

+4.0
+2.0

I

13
12

w

-4.0

'?
z

.j

-8.0

0

'"
S
.5

-6.0

1.0 k

10 k

...--

1----10

~

9.0

12

1.0M

100 k

.~

120

r---t-

z

o

>=

~ 10 0

~

;::o

UNITY GAIN

11111

~~~PENSATION

-----13

80

16
15
14
V±, SUPPLY VOLTAGE (VOLTS)

17

18

.

('0)
em eM

AVCM : 10 log -:-

5

~ 120

CMrej: lAVCM - AVOL]

~
~
w

1'\

w

o
o

11111111

---

130r-----.-----~----.---------~----------,

OS
o

1111

~

FIGURE 24 - COMMON·MODE REJECTION RATIO
versus TEMPERATURE

FIGURE 23 - COMMON·MODE REJECTION RATIO
versus FREQUENCY

o

..-

"---- PfSITIVE INPrT L1MIT-

f. FREQUENCY (Hz)

14 0

~

~

>
~ 8.0
100

.....-

------ -- --

14

~

>

g

~

I

....

~

Vin

> -2.0

~

COrpENSATlO~

15 -NEGATIVE INPUT LIMIT

0

-10
-12
10

+25 OC

0

':;

~

UNity GAIN

16

o
o

110~----+_----+_----~--~~---+----_+----~

'"oZ

~ 100 f-----+-----+-----f------1~--- ± 15 V SUPPLIES

'" 60
S

13

140

10

~

~
100

1.0 k

10 k·

lOOk

1.0 M

90L-____J-____L-____L-__~L-__- l_____1____~
-55

f, FREQUENCY (Hz)

-25

+25

+50

+75

TA, AMBIENT TEMPERATURE (OC)

Pin numbers adjacent to terminals apply to S-pin package, numbers in parenthesis apply to 14·pin packages.

7-183

+100

+125

I

MC1539, MC1439 (continued)

FIGURE 25 - VOLTAGE-FOLLOWER PULSE Rr;:SPONSE

+5.0

~
o
>

-5.0

5.0

10

15

20

TIME (ps)

TYPICAL APPLICATIONS
Pin numbers adjacent to terminals applv to B-pin package, numbers in parenthesis apply to 14-pin packages.

FIGURE 26 - VOLTAGE FOLLOWER

FIGURE 27 - 01 FFERENTIAL AMPLIFI ER
RF

Rl
'I

2200 pF
112)
8

6 (10)

FIGURE 28 - SUMMING AMPLIFIER

14)

R2

2

'2
'oul

R3

ZOUI.-J

'3
eout::: ein± Vio
Zin > 40 M OHMS
Zoul CL • ZOUI OL

+fl£1 4 k [11ii5fO.04
+Q1
[1AO~r
OHM

eout:-[~ el +~ e2] + [1 +~1 e3
Rl. R2

"Properly Compensated

RS" Parallel Combination of
eout=-

[ RF

R1

el+

RF

ii2

For R3'" R1 + R2

R"

e2+

A2. RJ. RF.
RF

R3

e3

"Properly Compensated

FIGURE 29-+15VOLT REGULATOR
'30 V

+20V.._..----4'==-:.,.....":::::",~==--_.q.,,.

10~

__

-4.S

~

___

-S.O

~

___

-S.S

~

-6.0

H.6

_ _- J_ _ _ _
-6.S

~~"'.0-------"'S:':.S~------:l6.0:---------~6.""S---------:7.0

~

-7.0

THRESHOLD ADJUST VOLTAGE AT PIN 6 (VOLTS)
For a mora detailed discussion regarding application of sense amplifiers. see Motorola Application Note AN-245.
"The MC1540 - An Integrated Cor. Memory Sense Amplifier."

7-189

I

~J

1L~

IC1541
IC1441

______________S_E_N_S_E_A_M_P_L_IF_I_E_R_S~

Dual-channel gated sense amplifier with separate wideband differential input amplifiers. Either input can be gated on from saturated logic
levels. The sense amplifier features adjustable threshold, saturated
logic output levels, and a strobe input that accommodates saturated
logic levels. Designed to detect bipolar signals from either of two
sense lines. Operates with core memory cycle times less than 0.5 ,,"s.
FSUFFIX
CERAMIC PACKAGE
CASE 607
TO-S6

Typical Amplifier Features:
• Nominal Threshold - 17 mV
• Input Offset Voltage - 1.0 mV typical
• Propagation Delay
Input to Gate-Output - 20 ns
Input to Amplifier-Output - 10 ns
Gate Response Time - 15 ns
Strobe Response Time - 15 ns
• Common Mode Input Range - 1.5 Volts

LSUFFIX

• Differential Mode Input Range
With Gate On - 600 mV
With Gate Off - 1.5 Volts

CERAMIC PACKAGE
CASE 632
TO-116

• Power Dissipation - 140 mW typical
See Peckaging Information Section for outline dimensions.

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Power Supply Voltage

V+
Y-

+10
-10

Vdc
Ydc

Differential Input Signal

Yin

i5

Vdc

CMYin

:':5

Vdc

Load Current

IL

25

mA

Power Dissipation (Package Limitation)
Flat Package
Derate above 25°C
Ceramic Dual In-Line Package
Derate abov~ 25°C

PD

Operating Temperature Range
MC1541F, MC1541L
MC1441F, MC1441L,

TA

Common Mode Input Voltage

Storage Temperature Range

T stg

7-190

500

mW

3.3

mWiC

600
4.8

mW
mW/'C
°c

-55 to +125
o to +75
-65 to +150

°c

MC1541, MC1441 (continued)

CIRCUIT SCHEMATIC
INPUTB

(614

V'

l(51

III

13

121141

21r.

61r.

SIB)

J.Bk

4.6k

l.8k

L---~B~1I0~,~----~----~------~--------~~--~~--4-4-'~I2~,rlO~------~5~;
B CHANNEL GATE INPUT

STROBE

Number at terminal end denotes pin number Illr flat (F) package.
Number in parenthesis denotes pin number for dual in·lineteramic III package,

LOGIC DIAGRAM
mil

1-----------------1(3)

-i{-

12 (141

-------i

I

I

I

I

1

I 719'
I OUTPUT
I
I

INPUT A

I

2(41

A

CH~~;~L ,,':;."'::..'--'-'1____-'---'
INPUT

315)

1

+:____-I

INPUT 80-';..;'''__

L ______________________ _
THRESHOLD
ADJUST

11 (13)

I
_ _ _ _ --.l
TO (12)
STROBE

Number at terminal end denotes pin number lor flat package. Number in pau~nthtsis denotes pin numbtr for dual in-line package.

elLannel
Gateinpul

Inpul
Signal

Amplifier

Output

Snobe
Input

Vertical
Scale

'1")
2DmV/div

2V1div

2V/div

1

J

FIGURE 1 - TYPICAL OPERATION

~

/
II

""2

Amplifier

Output

2V/div

-I--'

HorilOnt1IScaI.
50ns/div

7-191

MC1541, MC1441 (continued)
ELECTRICAL CHARACTERISTICS
(v+ ~ +5.0 Vdc± 1%, V- = 5.0 Vdc± 1%, Vthlpin 111 = -S.OVdc ± 1%, Cext = 0.01 pF. TA = 25°C unless otherwise noted)
{Tlow = -55°C for MCl541 or OCc for MC1441, Thigh = +125°C for MC1541 or +7SoC for MC1441. Pin numbers referenced in table
denote flat package' to ascertain corresponding pin number for dual in-line package refer to the equivalent cirC\lit}

Characteristic
Input Threshold Voltage
(T A = +25° C)
(T low ;; T A;; Thigh)

Fig. No.

Symbol

8

Vth

MCI441
MCI541

Input Offset Voltage

8

Input Bias Current
(V I = V2 = V 3 = V4 = 0)

9

V.

10

Ib

(VI =V 2 =V 3 =V 4 =0, TA = T low)
Input Offset Current

9

Output Voltage High
(V I = V2 = V3 = V4 = 0, IOH = 200 p.A)

Iio
VOH

Output Voltage Low
(VI =V 2 =V 3 =V4 =0, V I2 = +5.0Vde, 17 = 10 mAde)

10

VOL

(V 12 = +5.0 Vde, 17 = 10 mAde, T A = + Thigh)
Strobe Load Current
(V 10 = 0)

IS

Strobe Reverse Current
(V 10 = +5.0 Vde)

ISR

(V 10 = +5.0 Vde, T A = Thigh)
Input Gate Voltage Low
(V I = V3 = 25 mVde, V2 = V4 = 0)

11

Input Gate Voltage High
(VI =V 3 = 25 mVde, V2 =V 4 = 0)

11

Input Gate Load Current
(V 8 or V9 = 0)

VGL
VGH
IG

Input Gate Reverse Current (V 8 or V9 = 5.0 Vde)
(TA = 25°C)

IGR

(T A = Thigh)
Common Mode Range
Input Gate High
Input Gate Low

13

Differential Mode Range
Input Gate High

14

VCM

Min

Typ

Max

14
13
12

17

17

20
21
22

-

1.0

6.0

-

5.0

25

-

50

-

1.0

2.0

3.0

-

-

-

-

350

-

-

400

-

-

1.5

-

-

2.0

-

0.7

-

-

1.6

-

-

-

2.5

-

-

2.0

mV

VDH
VDL

Power Dissipation

PD

mV
p.A

p.A
Vde
mVde

mAde
p.Ade

-

Input Gate Low

Unit

"I. 5
"I. 5

25
Vde
Vde
mAde
p.Ade
25

-

Vde

-

-

,,600

-

mV

±1. 5

-

Vde

140

180

mW

Min

Iyp

Max

Unit

SWITCHING CHARACTERISTICS

Fig. No.

Symbol

8

tIA

Input to Output
(VI = 25 mV pulse, V 10 = +2.0 Vde)

8

tIO

Strobe to Output
(V I = V 2 = V3 = V4 = 0, V 10 = +2.0 V puise)

12

Gate Input to Amplifier Input
(V 1 = 25 mV pulse, V9 = 2.0 V pulse)

11

Gate Input to Amplifier Output
(VI = 25 mVde, V9 = 2.0 V pulse)

11

Characteristic
Propagation Delay
Input to Amplifier Output
(V 1 = 25 mV pulse, V 10 = +2. 0 Vde)

ns

Recovery Time
Differential Mode
Input Gate High V or V = 400 mV pulse
Input Gate Low
1
3
Common Mode

tso
tGI
tGA

-

10

15

-

20

30

-

15

20

-

10

15

-

30

35

-

30
0

-

-

15
15

30
30

ns

I
I

14

13

Input Gate High V or V = 1. 5 V pulse
Input Gate Low
1
3

7-192

tDR

tCMR

-

MC1541, MC1441 (continued)

FIGURE 3 - TYPICAL THRESHOLD versus THRESHOLD
VOL TAGE ADJUST

FIGURE 2 - TYPICAL INPUT THRESHOLD versus
TEMPERATURE
19

r--

25

I I

vJ +5.0 Vdc

v+ = +5.0 Vdc
V- = Vth adj = -5.0 Vdc

1 - - V- = -5.0 Vdc

/

TA=+25 0 C
20

18

--

:>
.§
Q

c5

~
cc

17

">-

16

IS
-50

-25

-

MCI441
LIMITS

---

25

50
75
TA, AMBIENT TEMPERATURE (OC)

/
/

,./

10

V

5.0
-3.5

125

100

FIGURE 4 - TYPICAL INPUT THRESHOLD versus V-

.......... .....

r

TA=+ 25 C -

.......... r-.

17

Q

16

;;:

15

>>~

- --

---

-

r--

-6.0
-4.5
-5.0
-5.5
THRESHOLD ADJUST VOLTAGE (VOLTS)

-6.5

I

-

TA = +250 C

r-....V+ =+4.5 V

25

--r-.,

I

S

.§
Q
....
Q

v+ =+5.0 v

r-r--r-

ili
~
>>~

20

\\...

"

;;:

t--

r-- t--

14

-4.0

V!h adj = [5.0 V

.......... ..........

----r-r- .....

18

s.§
ili
~

/

/

30

19

9

/

FIGURE 5 - TYPICAL INPUT THRESHOLD
versus INPUT PULSE WIDTH

I

20

1/

v+= +5.5 V

r-r-t--

15

13

12
-4.5

10
-5.0
V- (VOLTS)

-5.5

o

50

100

150

200

t,lNPUT PULSE WIDTH, (ns)

7-193

250

300

I

MC1541, MC1441 (continued)

FIGURE 6 - INPUT-OUTPUT TRANSFER
CHARACTERISTICS

5.0 r---,---,-.r-;..;;.;.;.,;,;.,;..;....;...;;,;,,;,;,,;;,..;,..;..;;~-.,-----,

FIGURE 7 - CHANNEL GATE INPUT-AMPLIFIER
OUTPUT TRANSFER CHARACTERISTICS

5.0

I

4.0
4.0

g

s

0

2

2

w

to

0

w

3.0

to

«

«

S
0

S
0

,..>
,..:::>~

,..
>

,..:::>~
s

0

/

u;

3.0

0

2.0

w
'"
u:

"

)

~
::E
« 2.0

/

./

1.0

1.0

O~--~--~--~--~--~-~

-30

-20

-10

10

20

30

o

1.0

0.5

'in. INPUT VOLTAGE (mV)

1.5

2.0

2.5

3.0

CHANNEL GATE INPUT VOLTAGE (VOLTS)

FIGURE 8 - INPUT THRESHOLD FOR OUTPUT VOLTAGE SWING FROM VOH TO VOL
PROPAGATION DELAY FROM INPUT TO OUTPUT
(a) Threshold Test Waveforms

(b) T,st Circuit
AMPLIFIER
OUTPUT
TO SCOPE

20 nsmax
INPUT Vth

Vin

---j-::F==""\,,- 90%

TO SCOPE

+5 Vdc

PULSE
OV--=-,---

4.9V----~

~~~~~T

0.35 V - - - - INPUT
PULSE
GENERATOR

(c) Waveforms for Propagation Delay Test

2.5V--r,"\
INPUT

AMPLIFIER
OUTPUT

n

GATE
OUTPUT TO
SCOPE

50

tr:::; 20 ns

1+-+--50%

~
IO

OUTPUT

+5 Vdc

1.5 V
Note: Vth =

OV------

Number at terminal end denotes the pin number
for flat package only; to ascertain the corresponding pin number for the dual in line packages refer

to the circuit schematic on the second page.

7-194

+5 Vdc

Vin

filii

-5 Vdc

-=

MC1541, MC1441 (continued)

FIGURE 9 - INPUT BIAS CURRENT TEST CIRCUIT

FIGURE 10 - OUTPUT VOLTAGE LEVELS
+5 Vdc

+----.------,
510

510

I b
I
I a

11

-5 Vdc
lk

Vout

10

11

-5 Vdc

11 + 12:: Ib for "A" channel when SlNitch is in "a" position
-Z-

:: Ib for "B" channel when switch is in "b" position

IIHZI= liD

FIGURE 11 - MINIMUM TIME FROM CHANNEL GATE INPUT TO AMPLIFIER INPUT
PROPAGATION DELAY FROM CHANNEL GATE INPUT TO AMPLIFIER OUTPUT
(A) Minimum Time from Gate Input to Amplifier Input - tGI
(See Definitions)
AMPLIfiER
OUTPUT
TO SCOPE

(B) Test Circuit
+5 Vdc

+2.5 Vdc

TO SCOPE
IA)

lZ

10

I
I
A_mplifier

I
I
I
IL _ _ _ _ _ _

I\.

~

L-

\

INPUT
PULSE
GENERATOR

I

\

\
GATE
PULSE
GENERATOR

(e) Propagation Delay from Channel Gate

Input to Amplifier Output

11

\

'

Z.O V
Gate

Ir:S 20 os

TO SCOPE

51

10±O.1%

1O± 10%

-5 Vdc

10 ± 10%

(Pin numbers shown on this page denote the pin numbers for the
flat package only; to ascertain the corresponding pin numbers for

the dual in·line package. refer to the circuit schematic on the
second page.)

7-195

50

50

MC1541, MC1441 (continued)

FIGURE 12 - PROPAGATION DELAY FROM STROBE INPUT TO OUTPUT

(a) Propagation Delay from Strobe Input to Output

+5 Vd,

(bl Test Circuit

510

2.0 V
Strobe 1.5 V

tr

Input

~

Strobe
Pulse Generator

20 ns

51

Gate 1
Output

to Scope

8

tso

11

9

-5 Vdc

FIGURE 13 - COMMON-MODE RECOVERY AND COMMON-MODE RANGE
0.01

± VCM

~F

trand tf ~ 25 ns

Input

10%

Output for input
less than common
mode input range

51
200 n'

Output for input
greater than common
mode input range

LY$v

f'-

'::"

lk

lk
+5 Vdc

FIGURE 14 - DIFFERENTIAL RECOVERY AND DIFFERENTIAL RANGE

±400 mV
Overload
Generator 2
10%
± Vth

Strobe

V,h
Generator 1

Output to

Scope

Input

Generator
11

+2.0 V

Strobe
Generator 3

+5 Vdc

(Pin numbers shown on this page denote the pin numbers for the
flat package only; to ascertain the corresponding pin numbers for
the dual in-line package • refer to the circuit schematic on the
second page.)

7-196

MC1541, MC1441 (continued)

DI;FINITIONS

Pin numbers referenced in the definitions below denote the flat package only; to ascertain the corresponding pin
number for the dual in-line package refer to the circuit schematic.
Input Bias Current - The average input current
defined as (11 + 12 + 13 + 14)/4.

pulse at pin 13 to achieve 50% of its final value
referenced to 50% of the input pulse at pins 1
and 2 or 3 and 4.

Channel Gate Load Current - The amount of
current drain from the circuit when the channel
gate input (Pin ',8 or 9) is grounded.
Channel Gate Reverse Current - The leakage
current when the channel gate input (Pin 8 or 9)
is high.

Propagation Delay, Input to Output - The time
required for the gate output pulse at pin 7 to
reach the 1.5 Volt level as referenced to 50% of
the input pulse at pins 1 and 2 or 3 or 4.

tso

Input Offset Current - The difference between
amplifier input current valueslll -1210r113 -141.
IS

Strobe Load Current - The amount of current
drain from the circuit when the strobe pin is
grounded.

Maximum Common Mode Input Range - The
common mode input voltage which causes the
output voltage level of the amplifier to decrease
by 100 mV. (This is independent of the channel
gate input level.)

Strobe Reverse Current - The leakage current
when the strobe input is high.
PD

Power Dissipation - The amount of power dissipated in the unit.

tcMR

Common Mode Recovery Time - The time required for the voltage at pin 12 to be within
100 mV of the dc value (after overshoot or
ringing) as referenced to the 10% point of the
trailing edge of a common mode overload signal.

VDH

Minimum Time Between Channel Gate Input
and Signal Input - The minimum time between
50% point of channel gate input (Pin 8 or 9)
and 50% point of signal input (Pins 1, 2, 3, or
4) that still allows a full width signal at ampli·
fier output.
Propagation Delay, Channel Gate Input to Am
plifier Output - The time required for the amplifier output at pin 13 to reach 50% of its final
value as referenced to 50",(, of the input gate
pulse at pin 8 or 9 (Amplifier input= 25 mVdc).

Maximum Differential Input Range, Gate Input
High - The differential input which causes the
input stage to begin saturation.
Maximum Differential Input Range, Gate Input
Low - The differential inpl!t signal which
causes the output voltage level ,of the amplifier
to decrease by 100 mV.

Differential Recovery Time - The time required
for the device to recover from the specified
differential input prior to strobe enable as referenced to the 10% point of the trailing edge of
an input pulse. The device is considered recovered when the threshold with the overload
signal applied is within 1.0 mV of the threshold
with no overload input.

tGl

Strobe Propagation Delay to Output - The time
required for the output pulse at pin 7 to reach
the 1.5 Volt level as referenced to the 1.5 Volt
level of the strobe input at pin 10.

Channel Gate Input Voltage High - Gate pulse
amplitude that allows the amplifier output
pulse to just reach 100% of its final value. (Am·
plifier input is set at 25 mVdc).
Channel Gate Input Voltage Low - Gate pulse
amplitude that allows the amplifier output to
just reach a 100 mV level. (Amplifier input is
set at 25 mVdc).
Input Offset Voltage - The difference in Vth
between inputs at pins 1 and 2 or 3 and 4,
VOH

Output Voltage High - The high-level output
voltage when the output gate is turned off.

VOL

Output Voltage Low - The low-level output
voltage when the output gate is saturated and
the output sink current is lamA.
Input Threshold - Input pulse amplitude at
pins 1, 2, 3 or 4 that causes the output gate to
just reach VOL.

Vth

Propagation Delay, Input to Amplifier Output The time required for the amplifier output

7-197

~_____________D_U_A_L_S_E_N_S_E_A__M_P_L_IF_I_E_R~

MC1543L

DUAL MECL CORE-MEMORY SENSE AMPLIFIER
A dual dc ~oupled sense amplifier. Output levels are compatible
with emitter coupled logic levels. MC1543L offers adjustable thresh·
old and excellent' threshold stability over a wide range of power·
supply voltage variation.

Typical Amplifier Features:
• Input Threshold
Adjustable from 10 to 40 mV (Positive or Negative Signals)
• Both OR and NOR Outputs Available
• Low Power Dissipation
• Threshold Insensitive to + or - Supply Variation
•

Each Amplifier is Separately Strobed
CERAMIC PACKAGE
CASE 632

MAXIMUM RATINGS (TA

TO·116

= 250 C unless otherwise noted)

Rating
Power Supply Voltage

Symbol
V+
V-

Value
+10
-10

Unit
Vdc
Vdc

Vin

±5.0
±5.0
25

Vdc
Vdc
rnA

100'0
6.7
-55 to +125
65 to +150

mW
mW/oC

Differential Input Signal
Common Mode Input Voltage

CMVin

Load Current

IL
Po

Power Dissipation (Package Limitation)
Ceramic Dual-in-Line Package

Derate above 250 C
Operating Temperature Range

TA
Tstg

Storage Temperature Range

uc
uc

CI RCUIT SCH EMATIC
v+

OUTPUT

Normally
LOW

6

1

14

GND

,- 1

"lJ"
Normally
HIGH

Normally
HIGH

See Packaging Information Section for outline dimensions.

7-198

Normally

LOW

MC1543L (continued)

EQUIVALENT CIRCUIT

INPUTS

REFERENCE 13
VOLTAGE

ELECTRICAL CHARACTERISTICS (Each Amplifier)

(v+ = +5 0 Vde +5%

V- = -5 2 Vde +5% Vref = 0 54 V +1% TA = +250 C unless otherwi ... noted)
Symbol
Min
Char_ristle
Fig. No.

Typ

Max

Unit

I nput Threshold Voltage

8

Vth

17

20

23

Power Supply Currents
(V2=V3= VII =VI2=V14=0)

6

ICC

-

9.5

12

mV
mAde

6

-

33

mAde

7

lee
Ib

26.5

Input 8ias Current

3.5

10

"Ade

Input Off...t Current

7

lio

-

0.05

Output Voltage High

9

VOH

-0.85

-0.8

0.5
-0.67

"Ade
Vde

Output Voltage Low
Strobe Threshold Level

9
10

VOL
VST

-

Vde

Strobe Input Current High

10

ISH

Strobe I nput Current Low

10

ISL

Input Common Mode Range

14

VCM

Input Threshold Range (by varying Vref)
Power Dissipation
Reference Supply Input Current (Pin 13)

8

VthR
Po
Iref

-

6
6

-1.7

-1.46

-1.30
25

-

Vde

50

"Ade

-

0.01

0.1

3.0

4.0
1()'4O

-

"Ade
Vde

185
10

230
40

mW

28

35

ns

16

20

ns

18
10

30

ns

15

ns

-

mV
"A

SWITCHING CHARACTERISTICS
Propagation Delay (I nput to Output)

11

tlO

Propagation Delay (Strobe tb Output)

12

tso

Strobe Relea... Time

12

Recovery Time (Differential Mode)
(ein = 400 mVde)

13

tsR
tOR

-

Recovery Time (Common Mode)
(ein = 4.0 Vde)

14

tCMR

-

3.0

15

ns

Strobe Width Minimum

12

ts

-

8.0

-

ns

8

Vth

18
15

21.5
18.5

mV
,.Ade
"Ade

TEMPERATURE TESTS (-550 Cto +125 0 C)

Input Bias Current

7

Ib

2.2

7.0

25
22
20

Input Offset Current

7

lio

0.02

0.1

1.0

I nput Threshold Voltage

{(-550 C)
(+1250 CI

7-199

MC1543L (continued)

TYPICAL. CHARACTERISTICS
FIGURE 2 -TYPICAL INPUT THRESHOLD
versus REFERENCE VOLTAGE

FIGURE 1 - TYPICAL INPUT THRESHOLD
versus TEMPERATURE

45

24

r-- r---

0

Vref set lor 20 mV hreshold
atTA =250C
II'" =5.0 Vd.
V- =-5.2 Vd.

-25

;;;

..sc
'"w
ili

------

r--

8

16
-55 -50

40

25
50
75
TA. AMBIENTTEMPERATURE (OCI

100

1\

35

~

a: 25

......
~

'~

:J:

20
15

==

;tS

,~

5.0

o

0.2

FIGURE 3A - TYPICAL INPUT THRESHOLD versus V+

--

,......

10

125

1-

-

\

30

....I

I I

I.

TA 250J
11'" .. 5.0 Vd.
V- = -5.2 Vd.
Re.ommended voltage for 20 mV
Threshold: Vref = 0.S4 Volt -

0.4

r-

0.6
0.8
1.0
Vref. REFERENCE VOLTAGE (VOLTS)

1.2

1.4

FIGURE 38 - TYPICAL INPUT THRESHOLD versus V-

24

24
TAl. 250C
V- = -5.2 Vd.
Vrefsetfor 20 mVThreshold

2

TA = 25 0C
11'"= 5.0 Vd.
Vre lsetfor20mVThreshold

2

0

0

8

16
4.5

5.5

5.0

B.O

16
-4.5

6.5

•

FIGURE 5 - INPUT·OUTPUT TRANSFER CHARACTERISTICS

..

:J:

a:

...i=~
==

~

0

\

\

0
10

o

-0. S

25~C

TA =
II'" =5.0 Vd.
V-= -5.2 Vd.
Vref "tlor 20 mV
Threshold

;;;

..sw 0
'"
!:;
'"9 40
'"f3

(one output)

!!\JPUT PULSE W!DTH

0

10

B.O

V-. NEGATIVE SUPPLY VOLTAGE (VOLTS)

FIGURE 4 - TYPICAL INPUT THRESHOLD
\le!"s!.!!

5.5

5.0

v+. POSITIVE SUPPLY VOLTAGE (VOLTS)

-

I

TA = 25 0C
II'" = 5.0 Vd.
V-=-S.2 Vd•
Vrel set for 20 mV
Threshold

~

'"w

~-1. 0

"NOR" Output

~

'"...>
~

"""'20

5-1.5

'"11;
.?

-I f-O.5 my Tr.n~tiOt Width
-2. 0
30

40

50

60

t. INPUT PULSE WIDTH (n.1

-40

30

20

10

10

0in.INPUT VOLTAGE (mVI

7-200

20

30

40

MC1543L (continued)

FIGURE 7 - INPUT BIAS CURRENT
INPUT OFFSET CURRENT

FIGURE 6 - POWER SUPPLY CURRENT ORAIN
+5.0 Vdc

+5.0 Vdc

Vref

13

Unless otherwise specified

Vref

13
14

Vref should b. set for
20 mV threshold
(V ref = 0.52 V)

10
14

-=

12
11
10

12
11

-=

A

-5.2Vdc

-5.2 Vdc

FIGURE 8 - INPUT THRESHOLD LEVEL
+5.0Vdc

ref

to voltmeter

990
±0.1%

13
14

11
50

10

3
12

-5.2 Vdc

tovoltmater

FIGURE 10 - STROBE THRESHOLD LEVEL
STROBE INPUT CURRENTS

FIGURE 9 - OUTPUT VOLTAGE LEVELS
+5.0 Vdc

-=

Vref

+5.0 Vdc

5.1 k

51

7-201

•

MC1543L (continued)

FIGURE 11 - PROPAGATION DELAY INPUT TO OUTPUT

+5.0 Yd.

Vre!

Z5mV

(to dual·trace
oscilloscope)
13

INPUT

14
101---.
IZ

Ir:<;;ZO ns

( 25% overdrive)

41--.....

OUTPUT

---I-~

10
±0.1%

tiD

ho dual-trace
oscilloscope}
-5.ZVd.

FIGURE 12 - PROPAGATION DELAY STROBE TO OUTPUT and STROBE RELEASE TIME

+5.0 Yd.

Vre!

-0.7V

5.1 k

±1%

1

OC

131----11
51

ho dual·trace
oscilloscope}

•

STROBE
INPUT

-

_ _ _ _ _ -1.7 V

141---~

±1%

t---,12

101---.---.--4--,
OUTPUT

tso
Ito dual·trace
DStilloscope)

-5.2 Yd.

7-202

tSR

MC1543L (continued)

FIGURE 13 - DIFFERENTIAL MODE RECOVERY TIME
(See definition section)

+5.0 Vdc

Vref

400mV
DIFFERENTIAL
INPUT

10%

Ita oscilloscope)

Ita oscilloscope)
13
11

14

-=

3
12

10

-=
51

STROBE

(to oscilloscope)

-=

-1.7 V

OUTPUT

-=

-5.2 Vdc

FIGURE 14 - COMMON MODE RECOVERY TIME
COMMON MODE INPUT RANGE

(See definition section)

+5.0 Vdc

10%

(to oscilloscope)

Ito oscilloscope)

'---l11
3
~~~~~----~12

13
141-_ _,
10r---~~-'--~~

51

STROBE

-1.7 V

100mV
max

*
\Lr---"-f- - - - -

(to oscilloscope)

OUTPUT

-5.2 Vdc

7-203

MC1543L (continued)

DEFINITIONS
180 Propagation Deley, Strobe Input to Amplifier Output - The
time required for the amplifier output pulse to achieve 50%
of its final value referanced to 50% of the strobe input pulse
at pins 4 or 10.

I io Input Offset Current - The difference between amplifier
input current values lilA - 12AI or 1118 - 1281.
ISH Strobe High Current - The amount of input current when
the strobe pin is grounded.

tsR Strobe Release Time - The time required for the output to
change to 50% of its swing eftar the strobe reaches 50% of
its level going low. A dc leval of 50 mV is the input signal.

ISL Strobe Low Current - The leakage current when the strobe
input is tied to the negative supply.
Po Power Dissipation - The amount of power dissipeted in the
unit.
tCMR Common Mode Recovery Time - The minimum time by
which the strobe input may follow the high level common
mode input signel without causing a signal to appear at the
amplifier output.
tOR Differential Mode Recovery Time - Differential recovery
time, the minimum time by which the strobe input may
follow the high level differential input signal without causing
a signal to appear at the amplifier output.

VCM Maximum Common Mode Input Range - The common mode
input voltage which causes the output voltege level of the
amplifier to change by 100 mV (strobe hlghl.
VOH Output Voltage High - The hlgh·level output voltage at pins
6 and 8 with no input - or at pins 5 and 9 with input
above threshold.
VOL Output Voltage Low - The low·level output voltage at pins
5 and 9 with no Input - or at pins 6 and 8 with input above
threshold.

·tlO Propagation Delay, Amplifier Input to Amplifier Output The time required for the amplifier output to reach 50% of
its final value as referenced to 50% of the level of the pulse
input (Amplifier Input = 25 mVdc or 25% OYer set
thresholdl.

VST Strobe Threshold Level - The voltage at wh Ich the strobe
turns the amplifier to the ON state.

18 Strobe Width - The amount of time the strobe must be high
to obtain a given output. Minimum strobe width is thet min·
imum time required to cause the output to complete a full
swing VOL to VOH or VOH to VOL.

Vth Input Threshold - Input pulse amplitude at pins 2, 3,11, or
12 that causes the output gate to just reach Its new value,
VOL or VOH.
VthR Input Threshold Range - The maximum spread of input
threshold level that can be attained by varying the threshold
voltage reference, Vref.

7-204

~f

MC1544L
MC1444L

"'

SENSE AMPLIFIERS

'""-------~

AC·COUPLED
FOUR·CHANNEL
SENSE AMPLIFIER

IDEAL FOR PLATED·WIRE, THIN·FILM AND OTHER
HIGH·SPEED LOW·LEVEL SENSING APPLICATIONS
MC1544L1MC1444L features four input channels with decoded
selection, two stages of gain employing capacitive coupling, and a
MTTL compatible output gate. AC coupling reduces access times by
eliminating the problems usually associated with input line offset
voltages.

MONOLITHIC SILICON
EPITAXIAL PASSIVATED
INTEGRATED CIRCUIT

Threshold Level - 1.0 mV typ
Propagation Delay Time - 18 ns typ
Decoded Input Channel Selection
MTTL Compatible Inputs and Outputs
Wired OR Output Capability
DC Level Restore Gate on Capacitors Eliminates Repetition Rate
Problems Common to ac·Coupled Circuits
• Output Strobe Capability

•
•
•
•
•
•

CERAMIC PACKAGE
CASE 620

FIGURE 1 - BLOCK DIAGRAM
13
14

,....,...--..
o---+-L;,.L...--H

15 o---+~

16

9 OUTPUT

~~~~C~EL j
INPUTS

7

Is

6STROBE

~lDGROUND

CAPACITOR
RESTORE 1 1 0 - - - - - 1 - - - - - - '
INPUT

L . - - - - - - - - - - -....- - - - - o 5VEE
TRUTH TABLE
PIN

PIN

7

8

HI
LO
HI
LO

HI
HI
LO
LO

See Packaging Information Section for outline dimensions.

7-205

CHANNEL
SELECTED
A
B

C
D

MC1544L, MC1444L (continued)

MAXIMUM RATI NGS (TA = +250 C unless otherwise noted I
SYMBOL

VALUE

UNIT

VCC
VEE

+7.0
-8.0

Vdc

Common-Mode Input Voltage

VCM+
VCM-

+5.0
-6.0

Vdc

Differential-Mode Input Voltage

VOM+
VOM-

+5.0
-6.0

Vdc

VCR. Vcs. Vs

+5.5

Vdc

Po

1.0
6.7

W
mW/oC

TA

-55 to +125
o to +75

°c

T 51g

-65 to +150

°c

TJ

+175

°c

RATING
Power Supply Voltage

Capacitor Restore, Channel Select, and

Strobe I"put Voltage
Power Dissipation (Package Limitation)
Derate above T A = +25 0 C

Operating Temperature Range

MC1544L
MC1444L

Storage Temperature Range

Junction Temperature

FIGURE 2 - CIRCUIT SCHEMATIC
13

14

15

16

rt--~~----------~--~~~~----~--~--~12VCC

9 OUTPUT

•

10 GROUND

J----~ 6 STROBE

CAPACITOR
RESTORE

II~

'-__--4_+--_-+-____ 5 VEE

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.-J

INPUT

7-206

MC1544L, MC1444L

(continued)

TEST CURRENTNOL TAGE VALUES

VOLTS

ELECTRICAL CHARACTERISTICS
200

IT A = +2SDC unless otherwise noted)

Pin
Under
Symbol T,st Min Typ

CHARACTERISTIC
Input Threshold Voltage (Note

n

MC1544L

VTH

MCl444L

Mu Unit

.,

12

IOL IOH VIL V'H

Output Voltage

Power Supply Currents

VIH2

eel

Vee VCCH VeEL Vee VeEH GND

mV

12

13

1.0

_

mV

12

20

-

jJ.A

13,14

7,8

12

10

13, 14

7,8

10

10

_

jJ.A

12

10

3.0

rnA

12

10

Law Level

'CSL

0.6

1.0

rnA

12

10

High lel/el

leAH

10

jJ.A

12

10

Low Level

'CAl

13,14

t1

11

-2.5 -3.5 rnA

IS

40

High Level VCSH

2.1

200

10

/JA

12

1.6
1.2

VCSL

High Level VCSH
Low Level

Strobe Input Voltage
(Note 4)

VIL2

-

1.0

Low Level

Capacitor Restore Input Voltage
(Note 4)

-5.7 -6.0 -6.3

1.0

2.1

VCSL
11

Low Level VCAl

11

High Level

VSH

Low Level

VSL

High Level

VOH

low Level

VOL

Positive

ICC

Negative

lEE

2.0

12

7

7

-

-

8

8

-

-

11

-

0.8

11

-

-

6

11

6

-

11

6

-

0.8

3.6

1,3

7.13
1,7

13,15

10

12

10

12

10

12

10

12

10

12

10

12

10

12

10

12

10

12

10

12

0,4

0.5

15

22

30

rnA

-

6,13,14

7.B.l1

12

10

15

20

30

rnA

-

6,13.14

7.B,11

12

10

4.7
-6.0

-

Vdc 13,14
Vdc 13.14

3.7

-

Vdc

Common·Mode Range Voltage (Note 11

VCM+ 13,14
VCM- 13,14 -

Differential·Mode Range Voltage

VDM

13

V

1.5
1.5

2.4

0.7

1.5
1.5

2.0

V

1.5
1.0

High Level VCRH

0.7

3,8
13,15
1,8
13,15

-

(Note 3)
Channel Select Input Voltage
(Note 3)

525

1.8

Low/High Level

Channel Select Input Voltage

5.0

ICSH

lio

Strobe Input Current

I 4.75

High Level

Input Offset Current

Capacitor Aestore Input Current

3.5

10 -0.4 0.8 2.0

TEST CURRENT/VOL TAGES APPLIED TO PINS LISTED BELOW:

13

Input Bias Current INote II

Channel Select Input Current
(Note 21

I -10

Only one ,nput ten Ii shown. other mpuls are tested
in the same manner and are selected according to the
truth table in Figure 1
Pin 8 is tested in the same manner.
This requirement IS considered satisfied it the input
bias currents of all unselected channels total less
than 1,0 iJA which guarantees that these ch"nnels are
"off,"

-

13

14

10

7,8
7,8

12
12

10
10

7,8

12

10

This requirement .. evaluated during the ac threshold
test (Figures 1,21: A 10mV Signal (einl) is applied
to the input. VCAH will result In VOH at the output
while VCRL Will allow normal operation.
This requirement IS evaluated as in Note 4 except
VSH allows normal operation and VS L causes VOH
at the output

SWITCHING CHARACTERISTICS IT A = t25 0 C unless otherWise noted)
Symbol

Figure

Min

TV.

M ••

Propagation Delay Time

1,5

18
40

25

Strobe to I nput Lead Time

1,5

10

Strobe to Output Delay Time

1,6

Characteristic

18
30

Channel Select to Input Lead Time

tcsi

Channel Select to Output Delay Time

1.5

15

1.7

25
40

Capacitor Restore to Input Lead Time

1,5

10

Capacitor Restore Time (50 mV Offset)

1,8

15

Common·Mode Recovery Time

ejn

"+2.0V

19

50
50

Differential·Mode Recovery Time

ein

"+1 ,OV

20

65
65

ein~ "-2.0V

e' ' " -1.0V

'"1

7-207

25

Unit

•

MC1544L, MC1444L (continued)

FIGURE 3 - AC TEST CIRCUIT
VCC

560
r-- - ----- - ----- - ----,
I

I

:

I

eout

11

CT

15Pfl
MTTlIlI GATES
(used onlv for
VTH tests, MC3110 or .quiv)
LATCH RESET LINE
CAPACITOR RESTORE

CHANNEL SELECT A

50
STROBE

CHANNEL SELECT B
Diodes are 1N916 or equivalent.

CT includes probe, wiring, and load capacitance.

FIGURE 4 - THRESHOLD VOLTAGE TEST

!!in'INPUT
SIGNAL

VI:~

FIGURE 5 -teoi. teri. toi. tpd_. tpd+

ein11NPUT
SIGNAL

5mV---~5~-II%--~~~-

------=:.:..7:

o

f-------/--IOO_____
ns
_

3V--"~

einz CHANNEL
SELECT A

oJ~

eina CHANNEL

3V

SElECTB

0

tin

____ ...JL--

-,~-----

--1'L.. ____ ...JL--

4 CAPACITOR 3V~
.
RESTORE

"'5STAOBE

tout MTTlIll
GATE
OUTPUT

0 ___ _

3:~
1.5VVOL ----------

as necessary tosetect desired chilnnel. For
ein,-einS tr=tf<;IOns

tinllNPUT

~

L-

----'

ein2 CHANNEL 3 V ---,

~I-I-L-

SHEelA

5mV,-----r---\

SIGNAL

I

3V--I:~:-=-~_

elO2CHANNEL

SELECT A

\

L

D~

-.l"r------,L
,

"'3eHANNEL 3~--~-=)~_:_\

tin3 CHANNEL 3 V

e·

tin4CAPACITORl\{~

SELECT B

0
3V

'"4 CAPACITOR

RESTORE

•. I
·I::.I~

~

STIlOBE

r-

~I_J_
o--:':=~

RESTORE

___

~

~:5V-f-U

VOl--tpi_~~tPd+
NOTE: tio2-ejo5 Ir=tt< IOns

7-208

0----

3V~

o~II-1--

VOH~!
enul

SELECTB

I

r- I

3V __ ..!.c!.!.::::l1- I
--r:.~OL-_~

eio 5

VOH~

NOTE: einZ andein3 to be normal or inverted (dotted line}

J

FIGURE 6 - t so _. '00+

,

eoulOUTPUT

J

VO"--=+,

'

j r

VOL-~~~~-S-tw+

NOTE: tint - Sin;,

Ir ='If <::. 10 os

MC1544L, MC1444L

(continued)

DEFINITIONS
Ib

I nput current to the base of any input transistor when the base of the other transistor

lee

Positive power supply current
The current into the channel select input when the input is at a high-level of 3.5 volts
The current out of the capacitor restore input when the input is at a low-level of

of the differential pair is at the same voltago

FIGURE 7 -teso+' teso-

leRH

ICAl
5mV-----~

ein'INPUT

o ---..l

SIGNAL
fin,

CHANNEL
SELEelA

e.

'--

3V~------_
_ __

0

SELECT B

I

I:
0 ---1
:

ein4CAPACITOA3V,:
RESTORE

einS STROBE

Negative power supply current

I
I

\

:
!

I

L

____~

J~-~~~~:
I
I
I
o

'

,

The difference between the base currents of any input differential pair of transistors
when the base voltages are equal
10L

Output logic " ' " state source current
Output logic "0" state sink current

ISH

The current into the strobe input when the input is at a high-level of 3.5 volts

10H

ISL

The current into the strobe input when the input is at a low-level of 0 volts

teMA±.

The minimum time between the 50% level of the trailing edge of a + or - 2 volt
common-mode signal (t r = tf $'5 ns) and the 50% level of the leading edge of a 5 mV
input pulse when the capacitor restore and strobe inputs are used in a normal manner
as shown in Figure 21

-jj---ini

''''OUTPUT ::: _____
ttso+

--t--l

The minimum time between the 50% level of the leading edge of a 50 mV input
offset Signal and the 50% level of the leading edge of the capacitor restore pulse as
shown in F igu re 8

H-tcsa-

NOTE: To test olher thannel select inlll.ll,
reverse ein2 andein3'

The minimum time between the 50% level of the leading edge of the capacitor restore
signal and the 50% level of the leading edge of a 5 mV input signal as shown in
Figure 5

filiI-tins tr= 11.0; IOns

FIGURE 8 - ter
ein

INPUT
SIGNAL

e.
InZ CHANNEL
SELECT A
ein3 CHANNEl

SELECTB

ein4CAPAClTOR
RESTORE
•

tcsi

The minimum time between the 50% level of the leading edge of the channel select
and the 50% level of the leading edge of a 5 mV input signal as shown in Figure 5

tcso+

The delay time from the 50% level of the trailing edge of the channel select Signal
to the '.5 volt level of the positive edge of the output when the input to the selected
channel is held at the "1" level as shown in Figure 7

tcso-

The delay time from the 50% level of the leading edge of the channel select Signal
to the 1.5 volt level of the negative edge of the output when the input to the selected
channel is held at the "1" level as shown in Figure 7

tOMR±.

The minimum time between the 50% level of the trailing edge of a + or - , volt
differential-mode signal (tr = tf'S 15 ns) and the 50% level of the leading edge of a
5 mV input pulse when the capacitor restore and strobe inputs are used in a normal
manner as shown in Figure 22
The delay time from the 50% level of the trailing edge of a 5 mV input signal to the
1.5 volt level of the positive edge of the output as shown in Figure 5
The delay time from the 50% level of the leading edge of a 5 mV input signal to the
1_5 volt level of the negative edge of the output as shown in Figure 5
The minimum time between the 50% level of the leading edge of the strobe and the
50% level of the leading edge of the input signal as shown in Figure 5
The delay time from the 50% level of the trailing edge of the strobe to the 1.5 volt

flrnV

I COMPOSITE

in5 STROBE

~nG5I:ale)15(ij'-

SOmV---0 50%

I
I

I

I

Jo

3V

3V

3~

\

I

L

JrTl,---+',-----,\L
f.-I cr

:

~.!

I

---1I

\L-

o:~~~~~
3V O

VOH

""OUTPUT

I
I

~

,

level of the positive edge of the output when the input is held at the " ' " level as
shown in Figure 6

'_5

The delay time from the 50% level of the leading edge of the strobe to the
volt
level of the negative edge of the output when the input is held at the " ' " level as
shown in Figure 6

I

VOl~
tpd-l

f---

o volts

The input current to a channel select input when that input is at a high-level of
3_5 volts
The current into a channel select input when the input is at a low-level of 0 volts

I

3V

\n3 CHANNEL

ICSH

Vee

Positive power supply voltage

VCCH

Maximum operating positive power supply voltage

.VCCL

Minimum operating positive power supply voltage

VCM+
VCM-

The maximum common-mode input voltage that will not saturate the amplifier

VCRH

The minimum high-level voltage at the capacitor restore input required to insure
that the capacitors are clamped i.e_. the input threshold voltage is greater than 10 mV

VeAL

The maximum low-level voltage at the capacitor restore input which will allow normal
operation during the threshold test

VCSH

The minimum high-level voltage at a channel select input required to insure that the
total of the base currents of all unselected inputs is less than 1.0 IlA

VCSL

The maximum low-level voltage at a channel select input required to insure that the
total of the base currents of all unselected inputs is less than '.0 IlA

VOM

The maximum differential-mode input voltage that will not saturate the amplifier

Vee

The minimum common-mode input voltage that witt not break down the amplifier

Negative power supply voltage

VeEH

Maximum operating negative power supply voltage

VeEL

Minimum operating negative power supply voltage

VOH
VOL

Logic " ' " state output voltage
Logic "0" state output voltage

VSH

The minimum high-level voltage at the strobe input which will allow normal operation during the threshold test

VSL

The maximum low-level voltage at the strobe input which will result in VOH at the
output regardless of input signals

Vth

The minimum input signal (ein 1) required to drive the MTTL III gate$ to obtain
the eo waveform shown in Figure 4

7-209

MC1544L, MC1444L (continued)

TYPICAL CHARACTERISTICS
fTA = +250 C unless otherwise noted)
FIGURE 10 - THRESHOLD VOLTAGE versus POWER SUPPLIES

FIGURE 9 - THRESHOLD VOLTAGE versus TEMPERATURE

1.6,--r-----r---,---,--,---,---.,--,.---,----,

2.0

;;;

;;;

1.4f_~--+--+-+-+-+--+-~f_--+-___l
VEE = -6.6 V

~~ 1.2tl=t=l~g~~:Jj~

.§
w

'"«
C;

~

0

>

1.0

VEE = -5.4 V

9 0.8 f_-I-~I__If_--+-_I---+---+---+-__+-__l

9 1.0

~

o

""'.c"

"':;
->

~ O.6~-~~-~~_4-_4-_4-_4-_4-_+-___l

~

:>
-75

-25

+25

0.4 ~-~~-~~_4-_4--_+-_4-_+-_+-___l
0.2~~-_+-_+-+_-+_-+_-l--____l-_+-_I

+125

+75

4.5

7.0

;;;

;;;
~ 6.0

.§
w

5.0

9 4.0
~

--- ------

3.0

;: 2.0

}

'"~

1.0

o

o

9
o

/'"

\

'\

2.0

"

~"

",...

"

!'-.....

l"- I---

1-1: 1.0

:>

40

20

3.0

o
>

,/"

o
o

5.5

4.0

8.0

::I:

5.25

FIGURE 12 - THRESHOLD VOLTAGE versus PULSE WIDTH

FIGURE 11 - THRESHOLD versus INPUT OFFSET VOLTAGE

'"~

5.0

4.75

VCC: POWER SUPPLY VOLTAGE (VOLTS)

T. TEMPERATURE rC)

o
o

80

60

20

60

40

Vio.INPUTOFFSET VOLTAGE (mV)

80

PW. PULSE WIDTH (ns)
(10% LEVEL OF TRIANGLE)

FIGURE 13 - OUTPUT VOLTAGE
versus CURRENT and TEMPERATURE

FIGURE 14 - SENSE AMPLIFIER RESPONSE
vorsus TEMPERATURE (See Figures 3 and 5)

800

1-•. 1

'"1
(5mV)

;;;
E

- 600

~w

'"

~o

400

>
~

~

o 20
.:.
o

>

/
1\

55°C

L--J3-::: t;;;. ~

\

OH~
4.0

f - - I--Vr6.0

8.0

10

+25°C

eout

of--+To c
2.0

"

12

14

16

18

20

~ t:::::
THRESHO~
--- V
t---. y ~

MTTL
LEVEL

\

L '/

20nsJOIV.

IOL. OUTPUT CURRENT LOW (mA)

7-210

-55°C-,

"'+125°C

100

MC1544L, MC1444L (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 16 - CAPACITOR RESTORE
TIME versus INPUT OFFSET VOL TAGE

vo"us FREQUENCY

FIGURE 15 - INPUT IMPEDANCE

50
3.0

]:

g

~

r-..

z

2.0

'~"

"\

"~

30

'"

20

~
U

'\

;;; 1.0

'"o

~

'\

:'i

-"

o
1.0

0.1

,/"

V
,/"

10

o
o

10

20

f, FREQUENCY, MHz

~
~

80

FIGURE 18 - STROBE TO
OUTPUT TRANSFER CHARACTERISTICS
5. 0

'"\

4.0

o

60

40

Vio,lNPUT OFFSET VOLTAGE (mV)

FIGURE 17 - AMPLIFIER INPUT TO
OUTPUT TRANSFER CHARACTERISTIC
5.0

V

:::

"

c

",-

,/"

/'"

>=
w

w

u

.L

40

~ 4, 0
o

~
w

z

~. 3.0

'"
~

;;
>~
~

o
>0

~ 3. 0

\
\
2.0
APPROXIMATE
\
I - - - - MTTL THRESHOLO_
1.0 I - - - _
ILEVEL I -\

~

o
>

~ 2. 0

o

~

~

1.0

0.5

1.5

1. 0

0

2.0

1.0

Vin , INPUT VOLTAGE (mV)

I

c:;;:; 4. 0
~
o

+1250 C, VEE" -6.3 V

-

+125 0 C, VEE = -6.0 V

~

3. 0

-

ii:
w'

'"~

-

>

~~

-55 0 C, VEE

g

-6.3 V

...=>

I

>-

g

o

I - -55°C, VEE" -6.0 V

0;

o

o

2.0

3.0

+1250 C, VEE" -5.7 V

-

+125 0 C, VEE" -6.0 V

-

+125 0 C, VEE" -6.3 V

I

I
-5.7 V

-55 0 C, VEE

1.0

a

-55°C, VEE

-6.0 V

-55°C, VEE

-6.3 V

I

o
4.0

1.0

2.0

I
3.0

VCS ' CHANNEL SELECT INPUT VOLTAGE, Pin 8 (VOLTS)

VCS, CHANNEL SELECT INPUT VO LTAG E, Pin 71VO LTS)

7-211

•

+25 0 C, VEE" -6.0 V

2. 0

>

I
1.0

-

I

-

'"'"~

I
=

I

\

~. 3. 0

+25 0 C, VEE" -6.0 V

I

1.0

o

>

I

I

2. 0

5. 0

0

I

4.0

FIGURE 20 - CHANNEL SELECT B to
OUTPUT TRANSFER CHARACTERISTICS

I

f--

~

3.0

2.0

VSlin), STROBE INPUT VO LTAGE IVO LTS)

FIGURE 19 - CHANNEL SELECT A to
OUTPUT TRANSFER CHARACTERISTICS
5.0

55°C and +25°C

o

\

o

+125 0 C

4.0

MC1544L, MC1444L (continued)

FIGURE 21 - COMMON-MODE CHARACTERISTICS
Note: The 5mV Input Signal (Differential) is superimposed on the
Common-Mode I nput and is shown separately for reference
only.

FIGURE 22 - DIFFERENTIAL-MODE CHARACTERISTICS
Note: The 5mV Input Signal is superimposed on the Differential
I nput and is shown separately for reference only .

•
7-212

MC1545
MC1445

l ______

H_I_G_H_"F_R_E_Q_U_E_N_C_Y_C_1R_C_U_.I_T_S---,

GATE CONTROllED TWO-CHANNEL-INPUT
WIDEBAND AMPLIFIER

GATE CONTROllED
TWO-CHANNEL-INPUT
WIDEBAND AMPLIFIER

... designed for use as a general-purpose gated wideband-amplifier,
video switch, sense amplifier, multiplexer, modulator, FSK circuit,
limiter, AGC circuit, or pulse amplifier. See Application Notes
AN475 and AN491 for design details.
• Large Bandwidth; 75 MHz typical
o Channel-Select Time of 20 ns typical
• Differential Inputs and Differential Output

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

TYPICAL APPLICATIONS
VIDEO SWITCH OR
DIFFERENTIAL AMPLIFIER WITH AGC

MULTIPLEX OR FSK

ANALOG SWITCH

SIGNAL INPUT..,

SIGNALINPUT .....-t"~"':O:"i

'V

1011)
eout

6111

AMPLITUDE MODULATOR

PULSE-WIOTH MODULATOR

BALANCED MODULATOR

Op!n

CIRCUIT SCHEMATIC

GSUFFIX
Output

METAL PACKAGE

CASE 602A

L--------i--------<>--_+-~>-_+

Number in parenthesis denotes pin for F and L packages, number
at left in each case denotes corresponding pin for G package.
See Packaging Information Section for outline dimensions.

7-213

_

_oVEE

~

,.'Yt~yn~

LSUFFIX
CERAMIC PACKAGE

CASE 632
TO-116

I

MC1545, MC1445 (continued)
MAXIMUM RATINGS (TA = +250 e unless otherwise noted)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC
VEE

+12
-12

Vdc
Vdc

VID

±5.0

Volts

Load Current

IL

25

mA

Power Dissipation (Package Limitation)
Flat Package
Derate above T A = +25 0 C

Po
500
3.3

mW
mW/oC

Derate above T A = +25 0 C

625
5.0

mW
mWfOC

Metal Can
Derate above T A = +25 0 C

680
4.6

mW
mW/oC

TA

o to +75
-55 to +125

°c

T stg

-65 to +150

°c

Differential I nput Signal

Ceramic Dualln·Line Package

Operating Temperature Range

MC1445
MCl545

Storage Temperature Range

ELECTRICAL CHARACTERISTICS

= +25 0 e,

(Vee = +5.0 Vdc, VEE = 5.0 Vdc, at T A
specifications apply to both input channels unless otherwise noted)

Characteristic

Fig. No.

Symbol*

Single·Ended Voltage Gain

MCl445
MCl545

1,12

Avs

Bandwidth

MCl445
MCl545

1,12

BW

MCl445
MCl545

5,14

Input Impedance
(f= 50 kHz)

Min

Typ

Max

Vnit

16
16

19
18

22
20

dB

-

75
75

-

MHz
k ohms

50

10
10

-

25

-

Ohms

Output Impedance
(f = 50 kHz)

6,15

zos

3.0
4.0
-

Output Voltage Swing
(RL = 1.0 k ohm, f = 50 kHz)

4,13

VOD

1.5

2.5

-

V p. p

MCl445
MCl545

16

liB

15
15

30
25

"Adc

16

11101

-

2.0

MCl445
MCl545

17

IVlol

-

1.0

Quiescent Output dc Level

17

Vo

-

0.2

Output dc Level Change
(Gate Voltage Change: +5.0 V to 0 V)

17

I"-Vo I

-

9,18

CMRR

I nput Common-Mode Voltage Swing

18

VICR

Gate Characteristics

8

VGOL

Input Bias Current
(lIB = (11 + 12)/2)
Input Offset Current
Input Offset Voltage

Common-Mode Rejection Ratio
(f = 50 kHz)

Gate Voltage Low (See Note 1)

MC1445
MC1545

Gate Voltage High (See Note 2)

MCl445
MC1545

zis

VGOH

Gate Current Low
(Gate Voltage = 0 V)

MCl445
MCl545

18

IGOL

Gate Current High
(Gate Voltage = +5.0 V)

MCl445
MCl545

18

IGOH

Step Response
(ein = 20 mV)

MCl445
MCl545

19

MCl445
MC1545

tPHL

MCl445
MCl545

tr

MCl445
MCl545

tf

Wideband I nput Noise
(5.0 Hz - 10 MHz, RS = 50 ohms)
DC Power Dissipation

tpLH

MCl445
MCl545

10,20

VN(in)

11,20

Po

-

- -

"Adc

7.5
5.0

mVdc

-

Vdc

15

-

85

-

dB

-

±2.5

-

0.20
0.45
-

-

Vp
Vdc

0.40
0.70

-

1.3
1.5

3.0
2.2

-

4.0
2.5

mA

-

-

-

4.0
2.0

"A

-

6.5
6.5

-

ns

10

-

6.3
6.3

10

6.5
6.5

10

-

-

7.0
7.0

10

-

25

-

"V(rms)

-

70
70

150
110

mW

-

-

-

Note 1 VGOL Is the gate voltage which results in channel A gain of unity or less and channel B gam of 16 dB or greater.
Note 2 VGOH is the gate voltage which results in channel B gain of unity or less and channel A gain of 16 dB or greater.
*Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-214

mV

MC1545, MC1445 (continued)

FIGURE 2 - SINGLE·ENDED
VOLTAGE GAIN versus TEMPERATURE

FIGURE 1 - SINGLE·ENDED
VOLTAGE GAIN versus FREQUENCY
25

25

:s
'"
z
;;:

'"w
'"«

!:;
0
>

fil
0
ffi

'"
:s

20

z

;;:
15

!:;
0

>

~

0

i\'i

w
....

\

5.0

'"z

10

;;;;

\

«

o

15

fil

10

~

'"z
;;;;

20

'"w
'"«

~

«

5.0

0.01

1.0

0.1

100

10

1000

-55

~

z

;;:

'"w

'"
«

20

!:;
0
>

fil
0
ffi

~

f..-- f..--

~

~

,..-

5.0

~

~

2:
z

4.0

w

3.0

,/

'"
~

«
'"

!:;
>

V

~

15

/

/

0

f-

2.0

f:::>

'"
z

0

;;;;

ci

J

>

0

1.0

~

/'

f = 50 kHz

IIIII

10

±4.o

±5.o

±6.o

±7.o

±8.o

±9.o

±lo

±11

±12

0.1

0.5

0.2

VCC. VEE. POWER SUPPLY VOLTAGE IVdc)

14
~ 12
o
~

10

7.0

I---

~

~

r---.... ~P

en 8.0
w
a:

1'1\

f-

j

4.0

«
a:

:

~

2.0

r- 'inl,m'i = 30
1.0

5.0

10

'"

~ 160

,..

'"

10

20

1'-1"-

z

«

3.0~

~

200i

~

I .0

I50

'out I,m,} = 20 mV

I

'-'

o
~

~

11111 I I III I

;;; 140
120

~ 100

~ ~

....... .......

5.0

x

4.0 ~
c:

-t
n

I'-.

r

180

6.0 "

5.0 ~

~ 6.0
~

....

200
n

,.~

.......

2.0

FIGURE 6 - OUTPUT IMPEDANCE versus FREQUENCY

C~

0;

1.0

RL. LOAD RESISTANCE Ik OHMS)

FIGURE 5 - INPUT Cp AND Rp versus FREQUENCY
(BOTH CHANNELS)

z

+125

FIGURE 4 - OUTPUT VOLTAGE SWING
versus LOAD RESISTANCE

---

'"

+100

+75

TA. TEMPERATURE IDC)

FIGURE 3 - VOLTAGE GAIN
versus POWER SUPPLY VOLTAGES
25

+50

+25

-25

f. FREQUENCY IMHz)

80

60
:i 40

~

20

o
100

0.01

0.1

1.0
I. FREQUENCY IMHz)

I. FREQUENCY IMHz)

7-215

10

100

I

MC1545, MC1445 (continued)

FIGURE 7 - CHANNEL SEPARATION versus FREQUENCY

FIGURE 8 - GATE CHARACTERISTICS

140

~
z

;(
to

w

z

'"
«

o

>=

80

~

'"
0

-10
-20

>

~

60

~

~

-40

ffi

w

z
z

g

~

-30

40

to

z

on

-50

~

20

«

-60
-70
0.5

1.0

fin, INPUT FREQUENCY (Hz)

FIGURE 9 - COMMON MODE
REJECTION RATIO versus FREQUENCY

100

~

90

0

>= 80
~
z

0

i
w

g

'"

i'--

'"«

29

vV'

o

>
w

~

o

z

'"

7

>~
~

]
z
>

",'

'"
i'j

31

'"

'"

111111

Bandwidth'" 5.0 I-tz to 10 MHz

~

~
w

40

20

2.5

FIGURE 10 - INPUT WIDEBAND NOISE
versus SOURCE RESISTANCE

1111111111

50

8'"

'"

'"

60

30

2.0

33

70

6

1.5

VG, GATE VOLTAGE (VOLTS)

10

V

25

23
0.01

0.1

10

1.0

100

100

10

f, FREQUENCY (MHz)

FIGURE 11 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE

+5.0 V

t~;i;o~~~;i~gArea at.

-75

Redu;;d T eI1lPer:t~re.

~

-75

E

:; 250

-100

o

~ 200

•

~eout =

o~ 150

'"

[7

~

~ 100

~

I

/
4.0

-100

-100
75

t

-125

1- 125

B

I

-125

~
to

Ambient Temperature

/

Degrees Centigrade

6.0

8.0

10

10 k

100 k

FIGURE 12 - SINGLE·ENDED VOL TAGE GAIN AND
BANDWIDTH TEST CIRCUIT

500
400

50

1.0 k

RS, SOURCE RESISTANCE (OHMS)

12

VCC AND VEE, POWER SUPPLY VOLTAGE (Vdcl

Number in parenthesis denotes pin for F and L packages, number at left in each case denotes corresponding pin for G package.

7-216

-5.0 V

MC1545, MC1445 (continued)

FIGURE 13 - OUTPUT VOLTAGE SWING TEST CIRCUIT

+5.0 V

FIGURE 14 -INPUT IMPEDANCE TEST CIRCUIT

+5.0 V -5.0 V

-5.0 V

10111

Toat
Voltmeter

Vo
6171

ein =SOmV(rms) "-I

1= 50 kHz

FIGURE 15 - OUTPUT IMPEDANCE TEST CIRCUIT

FIGURE 16 - INPUT BIAS CURRENT AND INPUT
OFFSET CURRENT TEST CIRCUIT
+5.0 V -5.0 V

+5.0 V -5.0 V

10111
ein =50mV(rms)

f= 50 kHz

6171

110 is the difference in current
reading when either 51 or 82
is switched.
Open

+5.0 V

FIGURE 17 - INPUT OFFSET VOLTAGE AND QUIESCENT
OUTPUT LEVEL TEST CIRCUIT

FIGURE 18 - GATE CURRENT (HIGH AND LOW).
COMMON·MODE REJECTION AND
COMMON-MODE INPUT RANGE TEST CIRCUIT

+5.0 V -5.0 V

+5.0 V -5.0 V

Adjust Rt until VI
reads 0 Volts then
read Edt.

+5.0 V

RI
100 k

tDTums
51
11%1

-5.0 V

CMRR

Switch 51 and readjust Rt for V1 = 0
Il VOldel =

+5.0 V

+5.0 V

7-217

log [Avs ]
Ave

Change in V2 Reading

Number in parenthesis denotes pin for F and L packages. number at left in each case denoles corresponding pin for G package.

= 20

MC1545, MC1445 (continued)

FIGURE 20 - POWER DISSIPATION AND WIDEBAND
INPUT NOISE TEST CIRCUIT

FIGURE 19 - PROPAGATION DELAY AND RISE AND
FALL TIMES TEST CIRCUIT

+5.0 V -5.0 V
To "A" Channel

of Scope

+5.0 V

-5.0 V
7 (8)

4 (5)

Scope -

Tektronix 567

Pulse
Gen.
ein

orequiv

=2D mV

tr=tf<5.0 ns

True rms Voltmeter
6 (7)

with Bandwidth of

To "B" Channel

5.0 Hz to 10 MHz

of Scope

Vo

VN(in)=Avs

Open

~r-tPHL
J'U~
\[
I
I

I
90%

Open

FIGURE 21 - LIMITING CHARACTERISTIC
_
~

5.0~--'-~---.---r--"---~--'-~---'-~

~

4.0 f--t---t---+--+--+-+-±=~--l---I

~

~>

....
~
....
::>

c

-'

Number in parenthesis denotes pin for F and l packages.

number at left in each case denotes corresponding pin for Gpackage.

""

10k Bout

!
Q

500
'in. SINGLE·ENDED INPUT VOLTAGE (mVp·p)

I

7-218

MC1546L
MC1446L

~~_____________S_E_N_S_E_A_M_P_L_I_F_IE_R_S~

FOUR-CHANNEL PLATED-WIRE SENSE AMPLIFIER
· .. a sense amplifier designed to convert positive or negative 3.0 mV
signals from plated-wire memories to transistor·transistor logic levels
(MTTL). The problems encountered with ac·coupled plated-wire
sense amplifiers are eliminated with this direct-coupled sense amplifier.
• Positive or Negative 3.0 mV Signal to Any of Four Input Channels
Produces a Logic 1 or 0 Output (MC1446 ~ Positive or Negative
4.0mV).
• Low Input Offset Voltages Apply to All Four Channels - 0.5 mV
typ
• Wired "OR" Capability at Amplifier Output Results in Fewer
Associated Circuits
• 2 by 4 Internal Decoder Simplifies Channel Selection
•

Fast Recovery Time from Overload Signals - 40 ns typ

• Good Isolation Between ON and OF F Channels

FOUR-CHANNEL PLATED-WIRE
SENSE AMPLIFIER
MONOLITHIC SILICON
EPITAXIAL PASSIVATED
INTEGRATED CIRCUIT

~"'M'O'AO"O'
CASE 620

• Channel Select and Strobe Operate from Standard MTTL Levels
BLOCK DIAGRAM

3.0.
TRANSFER
CHARACTERISTICS

j~

2.5
o Ci)2.0

~~1.5
;:>0

~~1.0

5

.;
>

0.5

0
-6.0 -4.0 -2.0 0 +2.0 +4.0 +6.0
Vin,lNPUT VOLTAGE (mV)

CIRCUIT SCHEMATIC

Se8 Packaging Information Section for outline dimensions.

7-219

I

I

MC1546L, MC1446L (continued)

MAXIMUM RATINGS (TA = +250 C unless otherwise notedl
Rating
Power Supply

Vol~

Symbol

Volue

Unit

V+
V-

+10
-10

Vdc

Differential Input Signal
Common·Mode Input
Output Current
Power Dissipation (Package Limitation)
Ceramic Package
Derate above T A • +250 C

:1:5.0

Volts

CMVin

:1:5.0

Volts

lout

25

mA

575
3.85

mW
mWI"C

-55 to +125
o to +75

Dc

-65 to +175
-55 to +125

°c

Po

Operating Temperature Range

MCI546L
MCI446L

Storage Tempereture Range

MCI546L
MCI446L

Tstg

ELECTRICAL CHARACTERISTICS
(V+ = +5.0 Vdc ± 1%, V- = -6.0 Vdc ± 1%, T A = +250 C unless otherwise noted I
Fig.
Vol~Gain

Output Voltage Level

MCI446L

Symbol

Min

MCI546, MCI446
ein=
0, 0
.
T A = Tlow' to Thigh' ein = +3.0, +4.0 mV
ein = -3.0, -4.0 mV

t

Max

2

Unit

Vdc
0.4
2.0

1.4

2.4
0.4

Input Bias Current

3

Input Offset Current

3

Channel Select Current
High Level
Low Level
Channel Select Voltage
High Level
Low Level

4

Strobe Voltage
High Level
Low Level
Strobe Input Current
Output Source Current
Output Sink Current
Positive Supply Current

5

Negative Supply Current
Input Common-Mode Vol~ Range
Channel Selected

Typ

600

AV

lio

',:4:"
"':OJ!.

5

VCH
VCL

'2.0 I"
""~' ...... I

"
0.8 ,"

15

60

,.A

0.1

4.0

,.A

1.7
0.6

2.6
1.0

mA

Volts

2.0

O.S
2_0

4

4.0
-2.5

6
6
6
6

Volts
30
S.O
-4.0
19
-17

O.S
160

,.A

mA
mA
27

rnA

-24

rnA

7
+2.7
-1.0
+2.7

Channel. Not Salected

Volts

..,6.0

Input Differential-Mode Vol~ Range
Channel Selected
Channel. Not Salectad
'Tlow

= _55°C for MC1546, OOC for MCI446;

Volts

7

:1:0.6
:1:2.0
Thigh· +1250 C for MCI546, +750 C for MCI446

SWITCHING CHARACTERISTICS

n.

Propagation Delav Time

8

tpd

14

Output Rise or Fall Time

8

t, ortf

30

n.

Strobe Delay Time
Strobe Width (min)

9

Ids

14

n.
ns
ns

Channel Salect Time
Common-Mode Recovery Time (channel selected
Differential-Mode Recovery Time
(channel .. Iected)

9
10
7

!gemini
te.el
teMR

20
14
60

8

tDMR

40

7-220

ns

ns

MC1546L, MC1446L (continued)

TEST CIRCUITS
FIGURE 1 - VOLTAGE GAIN

FIGURE 2 - OUTPUT OC LEVELS
+O.4V

-0.4 V (MC1441i1

"l~-T IM"'''I

+5V -BV

+5V -BV

±:91~"~
10
±D.l%

FIGURE 4 - CHANNEL SELECT AND STROBE
INPUT CURRENTS

FIGURE 3 - INPUT CURRENTS

+5V -BV

FIGURE 5 - CHANNEL SELECT TRANSFER
CHARACTE R ISTICS

FIGURE 6 - OUTPUT CURRENTS
+5V -6Y

-1l.3V +O.3V

+5V

990
:0.1%

-sv

+-+-.,-----o-.!..j
99'

0.1%
10
±0.1%

1Ot-J-r---t-~====~
±D.1K

SWlinposilion 1 tor '0'"
SIN! in position 2for ' 0 •

7-221

+3.5 V

•

MC1546L, MC1446L (continued)

FIGURE 7 - INPUT COMMON·MODE CHARACTERISTICS

FIGURE 8 - CIRCUIT PROPAGATION DELAY, OUTPUT RISE AND
FALL TIMES, AND DIFFERENTIAL-MODE RECOVERY TIME

t5V -BY

+5V -BV

T.
",,.

"'I

To5top1

",

lin

SWI dmed for diflerllltiJl modi rKovery lime.
lin":t.5ODmV

FIGURE 9 - STROBE CHARACTERISTICS

I.d

+3.SV

FIGURE 10 - CHANNEL SELECT TIME



~

5

~ 200

i

0
-75

1 - MC1446
LIMITS
-50

-25

+25

~

.,:::>

-

1.0

-

.,'-'
,j

+50

+75

+100

+125

0
-75

-50

-25

T, TEMPERATURE IOC)

r--

+50

+75

+100

+125

FIGURE 16 - CHANNEL SELECT versus OUTPUT
TRANSFER CHARACTERISTICS

4. 0

4.0

~
.,

~

~ 3. 0

~

w

~

/

~ 2.0

~

Q

1. 0

.,~

2. of---CHANNEL I

V
-6.0

-1.0

(Pin 10)-

>

I. 5

~
:::>

I.0

.,

-"lL

3. 0

2.5

...

l/

3.5

w

to

to

0
-8.0

+25

T, TEMPERATURE (DC)

FIGURE 15 - AMPLIFIER TRANSFER CHARACTERISTICS

oj

MCI446
LIMITS

,j

I
t"""-

0.5

-

-0. 5

-I.0
-2.0

1
AMPLFIER INPUTS
CONNECTED TO APPROPRIATE _
I
dclVOLTAGIES
I

JJ

0

CHANNEL 2
(Pin II)

+2.0

+4.0

+6.0

o

+B.O

0.5

1.5

1.0

2.0

2.5

3.0

3.5

4.0

V"I, CHANNEL SELECT INPUT VOLTAGE (VOLTS)

Vin,lNPUT VOLTAGE (mV)

FIGURE 17 - STROBE INPUT TRANSFER
CHARACTERISTICS (Input High)

FIGURE 18 - COMMON-MODE GAIN versus FREQUENCY
-251'

4.0

3.5
In

~
o 3.0

~
W

~

to

... 2.5

~~

2.0

5

1.5

C>

I.0

S
,j

~

I

-20

r-. . . .

...... iGGmVirnai

"-

-I 5

Q

...

>

I

~

I.......

-I 0

.,:::>

II

.;

> -5. 0

"

0.5
0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.4

0.6 O.B 1.0

2.0

4.0

6.0 B.O 10

f, FREQUENCY (mH.)

VS(in), STROBE INPUT VOLTAGE (VOLTS)

7-224

"'"

20

40

MC1546L, MC1446L (continued)

TYPICAL CHARACTERISTICS (continued I
FIGURE 19 - VOLTAGE GAIN .....s FREQUENCY
1110

FIGURE 20 - ADJACENT CHANNEL ISOLATION versus
FREQUENCY
-25

II II
II II

80

a

ein = 1.0 mV(rmsl

'"
;;:

'"w
'"
~
0

.....

w

'"
~
0

60

...

i'

-15

>

........

40

:::>

1=
:::>

>

i

-

-20

:2

:2

z

II
lin = 100 mV (rms) to
CHANNEL 1 (CHANNEL
2 SELECTED)

I'...

-10

..............

0

Q

> -5.0

20

o
0.5

1.0

5.0

10

0.5

50

f, FREQUENCY (MHz)

1.0

5.0

10

50

f, FREQUENCY (MHz)

above ground that is fairly independent of the positive supply.
6. The current in the second stage of the amplifier is set by
the 18Q.ohm resistor in the emitter of the current source.
It can be seen that this resistor has one diode drop
(approximately 750 mV) across it. Therefore. an analysis
will show that the voltage drop across the 775-0hm load
resistor in the second stage will be approximately two diodes
when the differential amplifier is balanced. Accounting for
the additional diode voltage drop of the emitter-follower output transistor will set the output dc level at two diodes
above ground or very near the center of MTTL threshold.

CIRCUIT DESCRIPTION OF THE MC1546L/MC1446L
The MC1546L/MC1446L was designed to translate a positive
3.0 mV signal from a plated wire memory to an MTTL "1" ' ..e',
or a negative 3.0 mV to an MTTL "0" I..el. This sense amplifier
also eliminates the requirement for a bipolar switch in series with
the plated wire be;cause the bit selection is done inside the
sense ampl ifiar.
The circuit operation can be described in sections as follows:
1. All channels have been designed for low input offsets 0.5 V typical.
2. Channel "ORing" is accomplished by using common collector load resistors for four differential amplifier pairs.
3. Channel selection is accomplished bV current steering
through the four differential pairs. The circuit below the
four differential pairs forms a matrix tree which can be
thought of as a 2-by-4 decode matrix. The bottom transistor
is the current source for the first stage of gain.
4. DC translation between the first and second stages of gain
is done through an emitter-follower stage, two diodes and
another emitter follower for each side of the differential
amplifier. The currents in these translator legs are combined
and run through diodes to the negative supply. These
diodes are used to bias both the first and second gain stages.
This also gives the appropriate gain versus temperature and
dc output lavel versus temperature characteristics.
5. The top of the second stage amplifier is regulated at a voltage
equal to five diode drops 'above ground. It can be seen that
if the 700 ohm resistor in the regulator has one diode (or
VBE) across it then the 2.8 k ohm resistor will have four
diode drops across it. This makes a five diode drop voltage

APPLICATIONS INFORMATION
The MC1546/MC1446 devices are designed to convert Signals
from plated-wire memories as small as positive or negative 3 mV
to MTTL logic I..els. The output level of the sense amplifiar with
no input Signal present and with the strobe high is typicallv 1.4
volts (typical input threshold of MTTL logic). Hence, if the
strobe goes high during the absence of an input signal from the
plated-wire memory, the sense amplifier output will rise to 1.4
volts. This condition could cause false outputs; therefore careful
considerations must be given to strobe timing. Figure 21 illustrates
a typical timing sequence of the MC1546/MC1446 device as
recommended for proper operation.

7. The strobe circuit works by steering current in the second
stage. When the strobe is low. the entire current of the second stage current source is steered through the 775-ohm
load resistor. This clamps the output to a low state so that
an input signal cannot cause an output. When the strobe is
high, the current is steered through the second stage differential amplifier pair and the output will go to a level
dictated by the presence of an input Signal.
8. The output circuit of the sense amplifier may be thought
of as a push-pull type. The emitter of the push transistor is
brought out to a separate pin from the collector of the
pull transistor. This will facilitate "Wire ORing" the outputs of several sense amplifiers. Several emitter outputs
can be wired together along with only one collector pulldown transistor. The unused collectors of the pulldown
transistor must be grounded. An example of the use of
"Wire ORing" is to have four MC1546 devices wired-OR into
a 16-channel sense amplifier in which a channel may be
selected by selecting channels in parallel at the amplifier
inputs and strobing the proper sense amplifier.

Figure 22 shows how these sense amplifiers are used in an
N-word~line-by-32-bit basic memory plane organized as 4-N words
of 8 bits each. During a read cycle, the read current is pulsed
through a selected word-line and thus generates outputs to all of
the 32-bit pOSitions in the line. The internal one-of-four decoder
selects the desired channels of the eight sense amplifiers for a
particular system word. When the strobe goes high. the sense
amplifier outputs switch according to the data present at the amplifier inputs. The data readout on the other 24-bit lines is not lost
due to the Non-Destructive Read-Out properties of a plated-wire
memory. On the next read cvcle the decoder of the sense amplifier
in combination with the selected word-line determines the 8-bits
of data to read.

7-225

•

MC1546L, MC1446L (continued)

APPLICATIONS INFORMATION (continued)
FIGURE 21 - TYPICAL TIMING SEQUENCE
OF THE MCI546/MCI446

3.5VO~5""

Memory organizations that have more than four words per

word-line require that the sense amplifier outputs be wired-OR.
Ta wire-OR the outputs of several sense amplifiers all of the

Ch,"",S"~II,.",

\

emitters of the output-pullup transistors are tied together. Only

-\

one collector of the pulldown transistors is tied to the wired-OR
eminers of the pullup transistors. The remaining pulldown transistors must be grounded as noted in Figure 23. Ten or more

3.0 mV=:J "'"
o

sense amplifiers may be wired-OR together,without any reduction
in usable logic levels since only one sense amplifier per bit is on at

-3.0mV

any given time. Variations in propagation delay time (tpd). versus

the number of wired-OR sense amplifiers and the output capacitance are given in Figure 24.
I n Figure 25, eight are required for each bit of a 32-word/wordline memory. For those sense amplifiers that have wired-OR
outputs, the strobe is: used for decoding by attaching each strobe

'----

I-,C.,
\"'"

\'

1~------AmplilieflnPUI

F\

__ _ _+1,I'---....J'''-...''0''

3.0V,------'-1

_

,.
1

_ _ _1 1 - ' 1

i

'_- -_ _ _ _ _- 'SlrobelnputO
-_-"

50%

--+--1="8

--L.i

to a 3-bit-binary-to-1-of-8-bit decoder (MC4006). Thus only one

I-

3.0V-----+-'-+.

sense amplifier per bit can be strobed at a given time. High fan-out
gates are required on the channel select lines since a high current
must be supplied to the select lines to drive them to the logic "1"
level. The strobe current is low, thereby allowing many strobe
lines to be driven with only one gate.

1' -

"'"

50%

,

_

----1--- 1-II

Id

I-

"0"

_

-

Sense Amplifief Output

----T""m-'"'"Su-:",.-:"lO=-""....,O",V"".

-The strobe pulse width is smaller than the amplifier input pulse width,

FIGURE 22 - N-WORO-LINE-BY-32-BIT MEMORY PLANE ORGANIZED AS 4-N WORDS OF 8 BITS EACH

~ II ! mI ttllill [ l]IIm I mI IIITI :~
MEMO RY PLANE

WORD
LINES

W2
W,

o

1 2 3

8 9 1011 12 13 14 15

4 5 67

16 17 18 19 20 21 22 23

24 25 26 27

28 29 30

;!.....-

=

TO DIGIT
DRIVERS

I
-

-

-

.--

frr frr- .Ifr-

"'~

MC1446

MC1546
MC1446

~'546

MC1446

~'546
MC1446

~'546

MC1446

-

-ill ~ll
rr\'546
MC1446

MC1546
MC1446

-

)

~ll

~'546

MC1446

STROBE

2·81T
} ADDRESS

7-226

MC1546L, MC1446L (continued)

APPLICATIONS INFORMATION (continued)

FIGURE 23 - WIRED "OR" MC1546/MC1446 DEVICES

FIGURE 24 - TYPICAL PROPAGATION DELAY TIME VARIATION

(per number of devices at stated

capacitanc8~

I

!

~

;::

>-

~

v-

z

'''m

0

MlmoryPIIIII

~
to

V'

~

~

j.

v-

ZO

19
B

rL

7
6
15

V
/'

V

"

/'

-

C = 50pF

--

-.l
.d:::::::

C= Z5

I--

l--

....-

t

.1

4

10
NUMBER OF MC1546/MCI446 DEVICES
(WIRED DR)

FIGURE 25 - 32 WORDS/WORD - LINE ORGANIZED MEMORY

Ltllt

w:

I ttL1111

1111Jj~

MEMORY PLANE

JEl

1111 III~ ~

TO WORD DRIVERS

W3

w,
W,
I

MEMORY

•

PLANE

ICONTINUED)

11

TO DIGIT DRIVERS

17

"
31

CIt.NNELSELECTl1NES7\

ADDRESS

'0,
'BlTSO'{
DECODING

--

m

\:~lr~7<~=
m~ "7{
~

.--

r--

MC4006

TWO

MCI446

m- '~~ Im7<
MCI446

MCl446

MCI446

i

~~~:i- t1\

CONTINUED

-

(I-of-8
Dtc:odlr)

'---

TO REMAIN·
INGMEMORY

PLANE BITS

MC30Q4

'--BITII

7-227

MC1546L, MC1446L (continued)

DEFINITIONS
AV

the voltage gain from a channel input to amplifier
output (input signal is 2 mV peak-to-peak and the
strobe is high)

CMVin maximum input common-mode voltage on any
channel that will not cause the amplifier to saturate
DMVin maximum input differential-mode voltage on any
channel signal that will not saturate the amplifier
current from the positive supply with no load
(pin 12 shorted to pin 13)

tDMR

time required for the amplifier to recover from
maximum specified differential-mode input, (recovery - output within 10% of its quiescent state)

tds

delax time from the 50% point of the strobe input
leading or trailing edge to the corresponding 50%
point of the output

tpd

time rise (and time fall) of the input signal must
be less than 10 ns
the delay time from the 50% point of a 5.0 mV
input leading or trailing edge to the corresponding
50% point of the amplifier output

tSmin

time from 10% to 90% of the rise and fall times
respectively of the output signal with a 5.0 mV
input signal
minimum pulse width at 50% points at strobe
input allows a full output (pulse rise times of less
than 10 ns, amplifier differential input equal to
3mV)

current into the negative supply with both channel
select pins at +3.5 volts
input current into the base of any input transistor
when the opposite transistor of the differential
pair is at the same voltage
input current at channel select pin when the
channel select voltage is at VCH
input current at channel select pin when the
channel select voltage is at VeL

10+

tc sel

difference between base currents of any input
differential pair of transistors
output sou rce cu rrent to a load with the output
remaining above2.4 volts,excludingthe amplifier's
own sink current
the current that the amplifier will sink into pin 12
time required for the amplifier to recover from
the maximum specified common-mode input,
(recovery - output within 10% of its quiescent
state)
time between the 50% point of the channel gate
input and the 50% point of the signal input that
still allows a full width signal at the amplifier
output

VCH

minimum voltage required at the channel select
pin to cause a given channel to give 99% of the
maximum gain through the amplifier

VCL

maximum voltage allowable at the channel select
pin to cause a given channel to give 1% or less of
the gain when channel is fully selected

VoH

output dc level with inputs grounded and strobe
high
minimum output high level

VoL

maximum output low level

VSH

the minimum voltage required at the strobe pin to·
allow 99% of a full output

VSL

the maximum voltage allowable at the strobe pin
to allow 1% or less of a full output

7-228

~f

~~________H_IG__H-_F_R_E_Q_U_E_N_C_Y_C_I_R_CU__IT_S~

MC1550

RF -IF AMPLIFIER
INTEGRATED CIRCUIT

INTEGRATED CIRCUIT LINEAR AMPLIFIER

MONOLITHIC SILICON
EPITAXIAL PASSIVATED
... a versatile. common-emitter, common base cascade
circuit for use in communications applications. See
Application Notes AN·215, AN·247 and AN·299 for
additional information.

•

Constant Input Impedance over entire AGC range

•

Extremely Low Y12 -4.3/lmhosat60 MHz

•

High Power Gain - 30 dB

•

Good Noise Figure - 5 dB

@
@

Pin 7 connected to case

60 MHz (0.5 MHz BW)
60 MHz
GSUFFIX
METAL PACKAGE
CASE 6028

MAXIMUM RATINGS ITA· +2SoC unless otherwise noted)
Rating
Power Supply Voltage, Pin 9

AGC Supply Voltage
Differential Input Voltage, Pin 1 to Pin 4

IRS

Symbol

Value

Unit

V+

20

Vdc

VAGC

20

Vdc

Vin

±S.O

Vlrms)

680
4.6
500

= 500 ohms)

Power Dissipation (Package Limitation)

Po

3.3

mW
mW/oC
mW
mW/oC

Operating Temperature Range

TA

-55 to +125

°C

Storage Temperature Range

T stg

-65 to +150

DC

Metal Can

Derate above T A = +25 0 C
Flat Package
Derate above T A

=

+250

C

CIRCUIT DESCRIPTION

CIRCUIT SCHEMATIC

r-----I

I

R,

3k

R,

--------...,

10 o-(,.....-+---,,3k--~

3k

I

L _____ _
CASE-----'

The MC1550 is built with monolithic fabrication techniques
utilizing diffused resistors and small- geometry transistors.
Excellent AGe performance is obtained by shunting the signal
through the AGe transistor QJ maintaining the operating point
of the input transistor QI. This keeps the input impedance
constant over the entire AGe range.
The amplifier is intended to be used in a common·emitter,
common· base configuration (QI and Qz) with QJ acting as an
AGe transistor. The input signal is applied between pins 1 and
4, where pin 4 is ac·coupled to ground. DC source resistance
between pins 1 and 4 should be small (less than 100 ohms).
Pins 2 and 3 should be connected together and grounded. Pins
8 and 10 should be bypassed to ground. The positive supply
voltage is applied at pin 9 and at higher frequencies, pin 9
should also be bypassed to ground. The output is taken be·
tween pins 6 and 9. The substrate is connected to pin 7 and
should be grounded. AGe voltage is applied to pin 5.

I
I
I
I
I
I

R,
R,

V+

I

18k

2

F SUFFIX
CERAMIC PACKAGE
CASE 606
TO·91

-----!

7

See Packaging Information Section for outline dimensions.

7-229

I

MC1550 (continued)

ELECTRICAL CHARACTERISTICS (v+ - +6 Vde, TA - +25 0 CI

Conditions

Characteristic
DC CHARACTERISTICS
Output Voltage

VAGC- 0 Vde
VAGC - +6 Vde

1

Test Voltage.

VAGC-O Vde

1

Vo
V8

VAGC - +6 Vde
Supply Drain Current

1

VAGC - 0 Vde

10

VAGC - +6 Vde
AGC Supply Drain Current

1

VAGC - 0 Vde

IAGC

VAGC - +6 Vde

3.80
5.90

-

4.65
6.00

Vde

-

Vde

2.85

-

3.40

3.25

-

3.80

-

-

2.2

-

-

2.5

-

-

-0.2

-

0.18

mAde

mAde

SMALL-5IGNAL CHARACTERISTICS
Small-Signal Voltage Gain

f-500kHz

2

-

29

dB

-3.0 dB

2

AV
BW

22

Bandwidth

22

-

-

MHz

Transducer Power Gain

f - 60 MHz, BW = 6 MHz

3

Ap

-

25
21

-

d8

-

f - 100 MHz, BW = 6 MHz

TYPICAL CHARACTERISTICS
(v+ - 6.0 Vde, T A = +25 0 C unless otherwise noted I
FIGURE 1 - DC CHARACTERISTICS TEST CIRCUIT

FIGURE 2 - VOLTAGE GAIN AND BANDWIDTH TEST CIRCUIT

VAGC +6 Vde

VAGC HVde
R, =500
R, = 6200
C,thruC,~O.lI'F

". . ,"' P"
c,

--11--+--+--.--:-0-;

FIGURE 4 - DRAIN CURRENT TEMPERATURE
CHARACTERISTICS

FIGURE 3 - POWER GAIN TEST CIRCUIT @60MHz

1.20

V+ ~16V
VAGC~OV

1.1 0
C,

o
; 1.00

R, ~500
C" C,and C, ~ 0.001 pJ
C, andC, ~ O.lI'F
C, and C, ~ 9·35 pF
C, ~ 9-180 pF
C, ~ 25·280 pF
l, ~0.22I'H
l, ~ 0.261'H

7-230

'"

0.9 0

0.80
-55

25

+25

+50

+75

TA , AMBIENT TEMPERATURE 1°C)

+100

+125

MC1550 (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 6 - INPUT RESISTANCE AND
CAPACITANCE versus AGC VOLTAGE

FIGURE 5 - INPUT RESISTANCE AND CAPACITANCE
versus FREQUENCY
2800

1
I""-..

2400

800

1

V+~6V

r\
\

e~2000

1

0

~

I

'-'
z

'-'

:;;

1\

~1200
~

C;,

-,800

'\.

R;, '\.

"

400

o

1.0

0.1

1

6

0

8.0 !5

~

i~

<5

Ri ,

40 0

r-

0
1000

4 .0

o

1.0

VAse

VAGc =6V

k

110

~

5.0

1

R,.,@30MHz

\

90

70

!5

Cout

!;

1

j

\ /

30

R..,@60MHz \

1.0

T

!5

e::
is

J

o

0.1
1000

100

~

2.0

I

C,.,@30 and 60 MHz

0

J

\

\

50

~

3.0 13

\11 /

i\

~

VAGc~Oand6V

4.0 ~
/

7

\ 7

'-'
z

V

V

\

\

~

r;j

1.0

t. FREQUENCY IMHz)

2.0

3.0

5.0

4.0

VAGC. AGC VOLTAGEIVOLTS)

FIGURE 10 - TRANSDUCER POWER GAIN
versus TEMPERATURE

FIGURE 9 - MAXIMUM TRANSDUCER POWE R GAIN
versus FREQUENCY

0

0
VAGC ~ 0
BW~6MHz

I,I~ 60 M~Z

-

BW~6MHz

5

5,....

1\

5

6.0

OV

~\

\\

0

5.0

FIGURE B - OUTPUT RESISTANCE AND
CAPACITANCE versus AGC VOLTAGE

100
Rout

10

4.0

3.0

2.0

VAGC. AGC VOLTAGEIVOLTS)

100 k

1.0

6.0

1

30 0

FIGURE 7 - OUTPUT RESISTANCE AND CAPACITANCE
versus FREQUENCY

0.1

J

60 MHz

Ci,

t, FREQUENCY IMHz)

100

~

,



~

l/NF'."II

'"
'"
~

u

600 ~

,.

~.

4.0

I"--1'-

2.0
0
10

20

RS(optl

200

100

50

400

'1'

200

S1
~

II...........

l-- f-'""

0

--

6. a

D£

105 MHz

I'--.

5.0
~

1000

~

~

I

~21

+30

~ +25

~

!/

~ -10

-g
1i

25

w

20 ---b211

.s
~

~

z

«
a:

-

~

-=
30 MHz

m

~

I
.~
_921@30MHz

~

r

~

~ -15
60

100

~
~

f, FREQUENCY (MHz)

0

-

921@SOMHz

o

1.0

,,

'~

10

~

30

J+=6V~C-

Hz

=-b21 @30 MHz

~ 5.0
a:

10

@ 60

..,.

=

6.0

~

FIGURE 15 -Y21. FORWARD·TRANSFER ADMITTANCE
versus AGC VOLTAGE

~

1\

f--y riC
3.0

~

a:

921, -b21 VAGC = 6 Vdc [\

1.0

~

~ 15
«

\.

/

~ +5.0

..,.a:

~ -5.0

"L~J W-ll

..... 1\

:E

c
a:

I

-b21

+20

c +15
«
a:
~ +10

~

.L.

Rs, SOURCE RESISTANCE (OHMSI

FIGURE 14 -Y21. FORWARD·TRANSFER ADMITTANCE
versus FREQUENCY
+35

-

4.0

t, FREQUENCY (MHzI

S
.s1i

........ I '

r-

60 MHz

r-

200 MHz

9.0

~ 8.0
u:
.. 7. a

o

500

--

2

52

I OOO~

0

2.0

~

~

.........
3.0

VAGC,AGC VOLTAGE (VOLTS)

7-232

~

4.0

5.0

MC1550 (continued)

TYPICAL CHARACTERISTICS
(v+ ~ 6.0 Vdc. T A = +2S o C unless otherwise noted)
FIGURE 17 -Y11.INPUT·ADMITTANCE versus FREQUENCY

FIGURE 16 -Y12. REVERSE TRANSFER·ADMITTANCE
versus FREQUENCY

1l

10

10

E

.3

.:::
..~
.....'"

"§"

w

<.>

"§

r- V+=6Vdc

z

j--V+

..sw

~

-b12

.

V

z

....
....

1m

1.0

6 Vdc

<.>

ic

z

b1';'"

~

w

~

'"'"w

V

..:

~

."
'-"911

1.0

;:

./

L

N
>

./

0.1

0.1
3.0

1.0

6.0

30

10

60

100

1.0

3.0

6.0

10

30

60

f. FREQUENCY (MHz)

f. FREQUENCY (MHz)

FIGURE 19 - 511 AND s22.INPUT AND OUTPUT
REFLECTION COEFFICIENT

The V12 shown in Figure 16 illustrates the extremely lowfeedbatk of theMC1550
wjth no contribution from the external mounting circuitry. However, in many
cases the external circuitry may contribute as much or more to the total feedback
than does the MC1550.
To perform more accurate design calculations of gain, stability, and input - output
impedances it is recommended that the designer first determine the total feedback of device plus circuitry.
This can be done in one of two ways:
(11

Measure the total V12 or 512 of the MC1550 installed in its mounting

(2)

circuitry. or
Measure the V12 of the circuitry alone (without the MC1550 installed) and
add the circuit V12 to the Y12 for the MC1550 given in Figure 16.

FIGURE 18 -Y22.0UTPUT·ADMITTANCE versus FREQUENCY
1.0

1l

'---V+ = 6 Vdc

E

b22

..sw

..:::

(.)

z

V

0.1

ic

;£

;;:
....
:::>
c

S
0.01

922

V
1.0

3.0

6.0

10

30

60

100

f. FREQUENCY (MHz)

7-233

100

MC1550 (continued)

TYPICAL CHARACTERISTICS (continued)
(V+ =6.0 Vdc. T A =+2So C unless otherwise noted)
FIGURE 21-522.0UTPUT REFLECTION
COE FFICIENT versus FREQUENCY

FIGURE 20 -511.INPUT REFLECTION
COEFFICIENTvarsus FREQUENCY
0.95
0.90

,"",,'111

15
~ en
it ~
w'"
tz: t!J

-20
-18
-16
I- w
-14 ~

e.

""I-

0.65
0.60
1.0

-7.0

0.9998

............

--

3.0

on....... i/
V

0.999 4
I-

I-w

wo

1-1-

0,-,

-100 U
-8.0 ~



0.9970
6.0

10

30

60

"'<0

-4.0 ~ 9

~ ~ 0.998 6
~ ~ 0.998 2

2.0

~w

W'"

g~

~w

-4.0 :::

6.0 ~
;:::

-5.0 ~ ~

1'221

~ ~ 0.999 0

-12:::: z

-6.0 ~ 8

I

1.0

100

-3.00:::>z
UJ
~u

0..:

/

~ ~
-2.0 <00

022

zu

-1.0 '"~

~

V
-l3.0

6.0

I

I

10

o
30

60

100

I. FREQUENCY (MHz)

I. FREUUENCY (MHz!

FIGURE 23 -s12. REVERSE TRANSMISSION
COEFFICIENT (FEEDBACK)

FIGURE 22 -521. FORWARO TRANSMISSION
COEFFICIENT (GAIN)

•
7-234

'"

HIGH-FREQUENCY CIRCUITS

'-""-----_----.-.

MC1552G
MC1553G

MONOLITHIC VIDEO AMPLIFIER

HIGH FREQUENCY
INTEGRATED CIRCUITS

. . . a three·stage, direct·coupled, common·
emitter cascade incorporating series·series
feedback to achieve stable voltage gain, low
distortion, and wide bandwidth. Employs a
temperature·compensated dc feedback loop
to stabilize the operating point and a current·
biased emitter follower output. I ntended for
use as either a wide·band linear amplifier or
as a fast rise pulse amplifier.

SILICON
EPITAXIAL PASSIVATED

• High Gain - 34 dB ± 1 dB (MC1552)
52 dB ± 1 dB (MC1553)
• Wide Bandwidth - 40 MHz (MC1552)
35 MHz (MC1553)
• Low Distortion - 0.2% at 200 kHz
• Low Temperature Drift - ±0.002 dB/oC

MAXIMUM RATINGS

CTA =+2S'C unless ctherw;se ncted)

Rating

Symbol

Value

METAL PACKAGE
CASE 6028

Unit

Power Supply Voltage, Pin 9

Y·

Input Voltage, Pin 1 to Pin 2
(RS ~ 500 ohms)

V in

1.0

Power Dissipation (Package Limitation)
Derate above T A = +2SoC

PD

680
4.6

TA

-55 to +125

"c

T stg

-65 to +150

"c

Ydc

Pin 6 connected to case

Operating Temperature Range
Storage Temperature Range

V(rms)

CIRCUIT SCHEMATICS
FIGURE 1 - MC1552 (LOW GAIN)

FIGURE 2 - MC1553 (HIGH GAIN)

+--+-~-o Vo .'

ISO

GNOo2-+_-<1_~_ _...J

80

3k

6k

12k

12k

130
6

3

4

5

6

GAiNOPiiiiN EXT. C GNO

GNO

See Packaging I nformation Section for outline dimensions_

7-235

MC1552G, MC1553G (continued)

ELECTRICAL CHARACTERISTICS
Characteristic
Voltage Gain

MC1552

(V+ = HVde. T. =+25'C unless otherwise noted)

Fig.
No.

Gain.
Option

3

50
100

MC1553
3

All
3,6

MC1552

50
100

MC1553

-

(f = 100 kHz, RL'" 1 k\1)

All

-

Output Impedance
(f :: 100 kHz, RS = 50 rl)
DC Output Voltage

3

DC Output Voltage Variation
(T A :: -55"C to ... 125"C)

3

Output Voltage Swing
(ZL:?: 1 kSlj Yin = 100 mV[rllls])

3

All
All
All
All

Power Dissipation
MC1552

3,4

MC1553

Rise Time

3,4

Overshoot

3,4

-

= 1 kn)

Vou/Vin

V/V

175
350

200
400

225
450

-

21
17

40
35

17
7.5

35
15

-

7

10

-

16

50

2.9

3.2

Vde

=0, 05

-

Vde

3.6

4.2

-

-

75

120

mW

8
9

--

ns

BW

IZinl

2.5

V Qut (de)
b.V out (de)

-

Vout

Pn
tpd

t

All

~0.2

MHz

kQ
Q

IZoud

50
100

dB

--

-

r

200
400

Noise Figure
(RS = 400 n, fa = 30 MHz, BW

Total Harmonic Distortion
(V out :: 2 Vp_p,' f '" 200 kHz, RL

Unit

56
113

All

50
100

MCI553

3 MHz)

Max

50
100

200
400

MC1552

=

Typ

44
87

200
400

Input Impedance

Delay Time

Min

200
400

Voltage Gain Variation
(T A:' _'55°C to .,.125°C)
Bandwidth

Symbol

IVe/Vp) 100'

NF
All

THD
All

10
25

Vp_p

-

-

9
12

18
20

11
30

20
45

5

-

%

-

dB

-

5

-

0.2

ns

%

NOTES
*To obtain the voltage-gain characteristic de·
sired , use the following pin connections:

Type
MC1552
MC15 53

Voltage
Gain

50
100
200
400

Pin Connections

Pin 3 Open
Ground Pin 3
Connect Pin 3 to Pin 4
Pins 3 and 4 Open

1. Ground Pin 6 as close to can as possible to minimize
overshoot. Best results by directly grounding can.

Figure 8. Under these conditions. the lollowing equations
must be used to determine C1 and C2 rather than the circuits

2. If large input and output coupling capacitors are used,

shown in Figure 5.

place shield between them to avoid input-{lutput coupling.
3. A high·frequency capacitor must always be used to by·
pass the power supply. This capacitor should be as close to

Fig. 5b C,

the circuit as possible.

r 5

,g. c C,

=

=

2171,11 17 x 10') Farads; C, =
SC, IV",/V;,j Farads
V.,,/V;,
F d
2".1,11.5 x 10-1 ara s

4. Voltage gain can be adjusted to any value between 50 and
3000 by connecting an external resistor from Pin 4 to ground

on MC1552. or from Pin 3 to ground on MC1553. as shown in
FIGURE 3 - TEST CiRCUiT

F' d
V.,,/V;, F d
'g.5 C, = 2.".f,13 x 10'1 ara s

FtGURE 4 - PULSE RESPONSE DEFINITIONS

~

1

V;,

0.5 V;,

Vout

lk

~

~

C>

0.9 V,
O.5V,
0.1 V,

7-236

MC1552G, MC1553G (continued)

TYPICAL CHARACTERISTICS
T... ==+2S·C

FIGURE 6 - VOLTAGE GAIN versus FREQUENCY

FIGURE 5a - FREQUENCY RESPONSE

0

0

f=Curv.

IA

2A

3A

f-

IB

2B

38

Vout
~A V"

V.~'/J"U 400

400
0

o~;t
I-

IC
ID

It

I:;t

3C

2D++

3D

2C

;t

200

4C

100

4D

+-50

~

200

0

~B

V+ ~ +6Vde
50n

Rs

0

100

~

50

r---r-,

0

~
i~ "

0

0
0
20
10

100

Ik

4k 10k

10M

1M

lOOk

0
0.1

100M

1.0 2.0 4.0

TEST CIRCUITS FOR FREQUENCY RESPONSE
C, ( F!
0.01
0.01
0.01
0.01
( F!
1000
1000
1000
1000
100
100
100
100

2A
2B
2C
20

0",

0

FIGURE 5c - CAPACITIVE COUPLED INPUT IRs <500 nl

0

Y+

~

3A
3B
3C
3D
4A
4B
4C
40

0.4
0.2
0.1
0.06
0.04
0.02
0.01
0.007

10

5.0

15

300 0
250 0

1\

z

Curv. Na. C, (IlF!
3A
3B
3C
3D
4A
48
4C
40

25

FIGURE 8 - VOLTAGE GAIN ADJUSTMENT BY
USE OF EXTERNAL RESISTOR

FIGURE 5d - TRANSFORMER COUPLED INPUT

200
100
70
30
20
10
7.0
3.0

20

LOAD CAPACITANCE (pF!

\

~

Curv. Na. C, (uF!

-

0

C, (uf) Curv. Na. C, (uF!
20
10
7.0
3.0
3.0
1.0
0.8
0.5

~1+6 Yde

i'-- r---

0

;ji2000

IA
IB
lC
1D
2A
2B
2C
20

1000

0

3.0
1.8
0.8
0.4
0.3
0.18
0.08
0.04

3A
3B
3C
3D
4A
4B
4C
40

lA
IB
lC
10
2A
2B
2C
20

100

FIGURE 7 - MAXIMUM NEGATIVE SWING SLEW RATE
versus LOAD CAPACITANCE

FIGURE 5b - CAPACITIVE COUPLEO INPUT IR s <5 knl

Curv. Na.

10

f, FREQUENCY (MHz!

I, FREQUENCY (Hz)

2.0
1.0
0.7
0.3
0.2
0.1
0.07
0.03

=150

0

J
,..11000

\

(Ext Rfram pin 3 ta gnd!

MC1552

l'\. (Ext Rfram pin 4 to g.d!

500
0
1.0

i,\C1553

1\

~J
2.0 4.0

10

"

100
EXTERNAL RESISTANCE IOHMS!

7-237

,.......
lk

10 k

MC1552G, MC1553G (continued)

INPUT ADMITTANCE

v+ = 6 Vdc, RL = I Hl, T. =+25°C

FIGURE 10 - GAIN = 100

FIGURE 9 - GAIN = 50

o. 5

-

~

Cp
4

0.7

I

f.-'/
8.0 ~
w
u

z

~

3

6.0

~

~
<3

is 0.4

'"z

~

Gp

~ o. 1

V/

~.

0
1.0

2.0

5.0 7.0

10

;

;;:
u'

1

/

O. 1

0
1.0

2.0

FIGURE 11 - GAIN = 200

r--...

/

9

1

II

I

[').v
V

I'

2.0

5.0 7.0

10

u
z

;'"

20

~
~

§
w
u
z

I. 2

~

z
9.0 '"

Is

6.0

~

~

3.0

u'

~

~

V

,.V

-

o

20

50 70 100

Gp

2.0

3.0

I---' V

5.0 7.0 10

~

J-

0
50 70 100

20

FIGURE 14 - BANDWIDTH versus SOURCE RESISTANCE

FIGURE 13 - OUTPUT IMPEDANCE versus FREQUENCY

70

if

0

0

Ii

60

F~

V+ =J6Vdc
TA =+25°C

'" eg

I

/

0

..........
~

100.200

100 M

t, FREQUENCY (Hz)

0
10

20

--

50

70

100

200

Rs, SOURCE RESISTANCE 10HMS)

7-238

:..'

~

"

400

10
10M

I
56

V",/V;,:= 50

0
0

2

"=

I

0

J

0

1M

6.0

t, FREQUENCY IMHzl

0

100 k

9

I

.3
0
1.0

1

/

~.

0
50 70 100

-"

Cp

o. 6

t, FREQUENCY IMHzl

0
10 k

J-

1

~ o. 9

~

--I--'

0
1.0

~

~

p

3

2.0

I. 5

U

1

kI

6

4.0 ~

FIGURE 12 - GAIN = 400

2

2

'"~

t, FREQUENCY (MHzl

2. 1_

r'\.

/

5.0 7.0 10

t, FREQUENCY IMHzl

Cp

~

6.0

'"

~
CJo... o. 1

70 100

1

I

Gp

o

50

20

~

~

2.0

-

V

Jf-.

f-"""

~ 0.3

~

4.0

o. 5~

~

8

~

2

~
~ 0.6
§
w
~

1
Cp

,:::- .....

"r-.
500 700 1000

MC1554G
MC1454G

~________________P_O_W_E_R_A__M_P_L_IF_I_E_R~

1-WATT
POWER AMPLIFIER
INTEGRATEO CIRCUIT

MONOLITHIC 1-WATT POWER AMPLIFIERS

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

... designed to amplify signals to 30()'kHz with
l·Watt delivered to a direct coupled or capac·
itively coupled load.

•

Low Total Harmonic Distortion - 0.4% (Typ)

•

Low Output Impedance - 0.2 Ohm

•

Excellent Gain - Temperature Stability

@

1 Watt

METAL PACKAGE
CASE 6026

(bottom view)

Pin 1 connected to case

VOLTAGE GAIN ••nus FREQUENCY CRL

m

16 OHMS)

5

0

5

z

;;:
to

0

W

to

~o

15

i

10

~

'"
'"",,'"'"

Gain Option #1

AV = 36 V/V

TTlJ.
Gam Option #2

AV=IS V/V

~.1alO U.
Option #3

AV=IOV/V

.1

>

PDut = 1.0 Wlrms)
RL = 16 OHMS

v+ = 16 V

5.0

IS .. FigI'" 711

o
10

100

1.0 k

2.0 k

10k

5.0 k

lOOk

1.0M

f. FREQUENCY 1Hz)

MAXIMUM AVAILABLE OUTPUT POWER
CSINEWAVE)

CIRCUIT SCHEMATIC
8

II 1.5:wf V
V /V

6

0.5 A PEAK CU1RRrNtt
4

IfIf'UT

I

J-"t"''''-f---f-l---++-oOUIM

tOW

2
0.75t:!'

,,,. {o-:-1---+--4

OPTlOHS

S

BIASA[f.~::t==j::==--J

:} C(WPE/tSATIQfI
m"."

.

0
~ 8. 0
+

>

6. 0

O'/~

..P

~

4. 0

1.0

~--+----+--~~--+-~--o',-

-

o.II W
2.0

5.0

V
V

10

....

./

20

RL. LOAD RESISTANCE (OHMS)

See Packaging Information Section for outline dimensions.

7-239

V

,/

-,....;

VlI

V

V

~~

50

100

MC1554G, MC1454G (continued)

ELECTRICAL CHARACTERISTICS (TC = +250 C unless otherwise noted)
Frequency compensation shown in Figures 6 and 7.

CharllCteriltic

RL
(Ohms)

Figura

Output Power (for eout<5.D% THO)

16

Power Dissipation (@Pout =I.DW)

16

Voltage Gain

16
16
16
1

Power 8andwidth
(for eou t<5.0% THO)

2

Total Harmonic Distortion
(for ein<0.05% THO. f =20 Hz
to 2DkHz)
Pout = I.D Watt (sinewave)
Pout =D.l Watt (sinewave)

2

MC1454
(Oto+700C)
Symbol

10
18

AV

36
10

Zin

lD

lout

3.0

10
18

16
16
16

Max

Typ

Min

Pout
Po

Input Impedance
Output I mpadance

Gain
Option-

36

Unit

1.0

Watt

0.9

Watt

10
18
36

VIV

10

kG

D.4

G

27D
250
210

kHz

THO

16
16

Zero Signal Current Drain

3

00

Output Noise Voltage

3

16

Output Quiescent Voltage
(Split Supply Operation)

4

Positive Supply Sensitivity
(V- constant!
Negative Supply Sensitivity
(V+ constant!

%

0.4
0.5

10
10

2D

10

11

Vn

0.3

mVo-ms

16

Vout(de)

:tID

mVdc

5

00

S+

-40

mVIV

5

00

S-

-40

mVIV

10

mAde

Pin Connection
-To obtain the voltage gain characteristic d •• ired. use the following pin connections: Voltage Gain
Pins 2 and 4 open, Pin 5 to Be ground
10
Pin. 2 and 5 open, Pin 4 to Be ground
18
36

Pin 2 connected to Pin 5, Pin 4 to ac ground

Charac:teristic Definitions
(Linear Operation)
FIGURE 4

FIGURE 3

FIGURE 1
+16V

o

+I6Y

I
-=

~
•

V"",!dc)

R,

)

I

-IV

-

V+

'.

~
1 '1~
R:J"'

':'

open

I

FIGURE 5

+l6Y
10

,.~'
,or

K!.

~'~r"
~)
~!

FIGURE 2

+BY

Vo-t IdC!"2

":'

'~_L\Q_f_OVd'
12 V"
L....i..

7-240

>-.0-_'.

""

st

,-

t:::.Vo",

- ZV=

MC1554G, MC1454G (continued)

MAXIMUM RATINGS (TC = +250 C unless otherwise noted)
Symbol

Value

Iv+1 + lv-I

18

Vdc

Peak Load Current

lout

0.5

Ampere

Audio Output Power

Paut

1.8

Watts

Po
1/8JA

600
4.8

mW
mW/oC

Po

1.8
14.4

Watts
mW/oC

TA

o to +70
-55 to +125

DC

T stg

-55 to +150

DC

Rating
Total Power Supply Voltage

Unit

Power Dissipation (package limitation'
TA
TC

= +250 C
Derate above 250 C
=+250 C
Derate above 25°C

1I8Jc

Operating Temperature Range

MC1454
MC1554

Storage Temperature Range

TYPICAL CONNECTIONS
FIGURE 6 - SPLIT SUPPLY OPERATION VOLTAGE
GAIN IAV) - 10, fLOW "'25 Hz

v+

FIGURE 7 - SINGLE SUPPLY OPERATION VOLTAGE
GAIN IAV) = 10, fLOW'" 100 Hz

v.

39 pF

39 pF

RECOMMENDED OPERATING CONDITIONS
In order to avoid local VHF instability, the following set of rules must be
adhered to:
1. An R·C stabilizing network (0.1 p.F in series with 10 ohms) should be
placed directly from pin 9 to ground, as shown in Figures 6 and 7, using
short leads, to eliminate local VHF instability caused by lead inductance

to the load.
2. Excessive lead inductance from the V+ supply to pin 10 can cause high
frequency instability. To prevent this, the V+ by·pass capacitor should
be connected with short leads from the V+ pin to ground. If this capacitor is remotely located a series R·C network (0.1 p.F and 10 ohms) should
be used directly from pin 10 to ground as shown in Figures 6 and 7.

3. lead lengths from the external components to pins 7, 9, and 10 of the
package should be as short as possible to insure good VHF grounding
for these points.
Due to the large bandwidth of the amplifier, coupling m!Jst be avoided be·
tween the output and input leads. This can be assured by either (a) use of
short leads which are well isolated. (b) narrow· banding the overall amplifier
by placing a capacitor from pin 1 to ground to form a low· pass filter in com·
bination with the source impedance. or (c) use of a shielded input cable. In
applications which require upper band·edge control the input low-pass filter
is recommended.

TYPICAL CHARACTERISTICS
FIGUR~

3.0

~
~ 2. 5
;::
=
o

t\

t;; 2.0

c;

~~

~

O. 5

AV=IOV/v

o

IIII

... I. 0

~

1=

5.0

If I'-

7.0

Alll!,lll~ = loin

z

o

--10% MAX POWER OUTPUT
--90% MAX POWER dUTP"uT

:=c:::i

§l

FIGURE 9 - TOTAL HARMONIC DISTORTION
versus FREQUENCY

~

lit

.='"

Z

2. 0

f= I kHz

AV=36V/V

~
1.5
r--- r-.. ~"

u

8 - TOTAL HARMONIC DISTORTION
versus LOAO RESISTANCE

~

o

t;;

c;

AV =18ViV

Z

.1 ...................

o

....'"
~

r::::

~ ~ t"--- f:::: S
20

30

50

1. 0

AV·IS,

-

-

R'~ = 16n

AV= 10, RL = Ion

g O.5

~

l-

e
1=

r---:.; ~ ~ ::::-~ t-- ~ ~~

10

~v=ld'~=lon

u

~.

~

I
III
~V ~~~,I ~I~ = 161n

1. 5

70

100

RL. LOAD RESISTANCE (DHMSI

0
10

AnlMrT
100

f, FREQUENCY (Hzl

7-241

Pout'" 1 W Irms)

loOk 2.0k 5.0k 10k

lOOk

MC1554, MC1454G (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 10 - VOLTAGE GAIN v.rsusTEMPERATURE

FIGURE 11 - OUTPUT VOLTAGE CHANGE

"
i+4·0

0

z

0

§;

:>

~

+2.0

'"
~
o

5V-

25
20



~

AV=18V/V

0

:::>

~

o

I-

I5

Z

~ ~2.0

AV=IOV/V

10

fa
::;

5.0

o

-55

-

..-

V

d

-25

25

50

~--4.0

125

100

75

;;
,;'

TA. AMBIENT TEMPERATURE (DC)

·55

·25

25

50

75

100

125

TA. AMBIENT TEMPERATURE (DC)

FIGURE 12 - VOLTAGE GAIN v.rsus FREQUENCY (RL -00)
5

Av =36V/V

O/..

Av= 18 V/V

5"

AV =10V/v

0.."

5
0

RL = CIO
VO", = 12 Vp·p

5. 0
0
10

v+= 16 V
(See Figure 7)
100

1.0k

2.0k

5.0 k

10k

lOOk

f. FREQUENCY (Hz)

•

FIGURE 13 - MAXIMUM DEVICE DISSIPATION
(SINE WAVE)

~
~

2. 0
1. 8

z

1. 0

~

O. 7

DEVI E OISS P TI

ABS LU E MAXIM

..........

0

76
25 !?..
40!i
60 w

'\.

C O. 5

"" ,

0:

I'\. '\.,

l\:

~ O.3

1
1

\

~



~

o

12

/"

~ 9.0

o

.,'"~

.......-

6.0

100

~

50

z

30

0

I-

±3.0

1M

..

,/

>
:;
w

±9.0
±12
±15
±18
'1'". V-. POWER SUPPLY VOLTAGE (Vdc)

±21

~

_

±24

6

-...........

o

~ 100
a:

~

"-

z

o

80

~
a:

g

,"-

60

~

to
~

I,

"-

20
1.0k

10k

lOOk

1.0M

/'

~
o

~
10M

-75

100M

+25

+50

+75

+100

+125 +150 +175

FIGURE 5 - OPEN-LOOP FREQUENCY RESPONSE

FIGURE 6 - OPEN-LOOP VOLTAGE GAIN
versus SUPPLY VOLTAGES

~ 350k

I""

+60

~

+40

..l

0

> +20

10

I

z
~ 300k

"" ""

~
~

~

100

1.0k

250k
200k

o

~

-20
1.0

-25

TA.AMBIENT TEMPERATURE (DC)

+120

w

-50

f. FREQUENCY (Hz)

400k

to

/

.......----

o
..l lOOk

+140

~ +100
z
:;;: +80

0

g 200k

""-

.~

100

/

...J

~ 40

10

./

.......-

300k

o
>

'\,

1.0

MCI456CG

W

.,o

>

lOOk

~cl456b

:;;:

z

to

10 k

1.0 k

to

o

..
..

III

FIGURE 4 - OPEN-LOOP VOLTAGE GAIN
versus TEMPERATURE

;;; 400k

'i'

1'i

-'0

500 k

120

w

VM

I. FREQUENCY (Hz)

FIGURE 3 - COMMON-MODE REJECTION
RATIO versus FREQUENCY

t

""~

7

10 k
-

3
5.0 ;:::: '=' '=' + 4 BW = 10 Hz
'-IS V
'. = '0/316
3.0
10
100

:}

±6.0

~.~

10

<:I

,/

.,~

"

~

......- V

~ 3.0
;;:
c 0

~
~

to

10k

9

150k

:5

100 k

~

I""f"
lOOk

1.0M

.......---- V

..l

o

~

10M

100M

50k
±5.0

±IO

±15

v+. V-.SUPPLY VOLTAGES (Vdc)

f. FREQUENCY (Hz)

7-245

±20

±25

MC1556G, MC1456G, MC1456CG (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 7 - OPEN·LOOP PHASE SHIFT

FIGURE 8 - OUTPUT SHORT·CIRCUIT CURRENT

versus TEMPERATURE

ffi

-45

a:

ffi

:g

""

'"

.5 45
~ 40

~

1\

-90

35

"'"

~

<>-135

~ 20
~ 15

1.0k
10k
lOOk
f, FREQUENCY (Hz)

....:::>
1= to

-"'-

-180
100

25

o

\

il:

tOM

'"

10M

~

SINK

::t--=; t---SOURCE

5.0

100M

-75

-50

-25

+25

+50

+75

+100 +125

+150

+175

TA, AMBIENT TEMPERATURE (OC)

FIGURE 10 - OUTPUT VOLTAGE SWING versus
LOAD RESISTANCE

40

28

w

---

:::>

FIGURE 9 - POWER BANDWIDTH

~

--

,

'-'

13

w

10

MC1456CG

~ 30

"'-

....

1.0

~C1456b

....

\

e

~

50

24

\

20

to

~

o

16

>

....
:::>
1=
:::>

)---

12

~~

r--

2_

,.: 8.0 )--:::>
)--o

+

o

>

3

4.0 )--- =

I

o
1.0

6

f---

4

-15V

VOt'

2k

'" r--.

~

II IIII

1.0 k

10
100
f, FREQUENCY (kHz)

I

100

200

500

1.0 k

FIGURE 11 - POWER DISSIPATION versus
POWER SUPPLY VOLTAGE

!z
0

;;:>=
iii

100
70
50
40
30

V .......

20

......
Vou' = 0

V ....

10

Q
a: 7.0

!i::

5.0

~ 4.0

~ 3.0
2.0

±2.0

2.0k

RL, LOAO RESISTANCE (OHMS)

0104.0

±6.0

±8.0

01010

±12

±14

0101'6

V+, V-, POWER SUPPLY VOLTAGE (Vdc)

7-246

±lB

±20

01022

5.0 k

10 k

MC1556G, MC1456G, MC1456CG (continued)

TYPICAL APPLICATIONS
Where values are not given for external components they must be selected by the
designer to fit the requirements of the system.
FIGURE 12 - INVERTING FEEDBACK MODEL

FIGURE 13 - NON·INVERTING FEEDBACK MODEL

lout

Zout ::: Zo

1 + Z2/Z 1
Ao (wI

Zout- O

FIGURE 14 - LOW·DRIFT SAMPLE AND HOLD
+15 V

SWITCH
>--O---<~.....

SAMPLE
COMMAND

eout

*Orift due to bias current
is typically 8 mV/s
-15 V

FIGURE 15 - HIGH IMPEDANCE BRIDGE AMPLIFIER

10 k

100 k

10 k
Va

100 k

7-247 !

=-10 Vin

MC1556G, MC1456G, MC1456CG (continued)

TYPICAL APPLICATIONS (continued)

FIGURE 16·- LOGARITHMIC AMPLIFIER

FIGURE 17 - VOLTAGE OFFSET NULL CI RCUIT

MC1456, C
MCI556

lOOk

>-0---...._

Vou •

Vou! = Kiln (K2 Vinl
33 k

OFFSET
ADJUST

See Application Note AN-261 for further detail.

FIGURE 18 - HIGH INPUT IMPEDANCE, HIGH OUTPUT
CURRENT VOL TAGE FOLLOWER

Vin

---<>----1
~ 250 Mn

Zin

Vout

Fl-0.1 pF
~-1------------~------~-1V-

7-248

;); 470 pF

Zo=lOOpn
10 = 100 mA (maxi

MCISS8 ~_________O_P_E_R_A_T_IO__N_A_L_A_M_P_L_IF_I_E_R_S~
MCI4S8
MCI4S8C

(DUAL MC1741)

DUAL MC1741
INTERNALLY COMPENSATED, HIGH PERFORMANCE
MONOLITHIC OPERATIONAL AMPLIFIER
· .. designed for use as a summing amplifier. integrator. or amplifier
with operating characteristics as a function of the external feedback
components.

DUAL
OPERATIONAL AMPLIFIER
MONOLITHIC SILICON'
INTEGRATED CIRCUIT

• No Frequency Compensation Required

G SUFFIX

• Short·Circuit Protection

METAL PACKAGE
CASE 601

• Wide Common·Mode and Differential Voltage Ranges

TO·99

• Low·Power Consumption
• No Latch Up
LSUFFIX
CERAMIC PACKAGE
CASE 632

TO·116

FIGURE 1- TYPICAL FREQUENCY·SHIFT
KEYER TONE GENERATOR
P1 SUFFIX

..

PLASTIC PACKAGE
CASE 626
MC1458.C (onlv)

:>
i5

>

P2 SUFFIX

rrt'(rrl l

PLASTIC PACKAGE
CASE 605
MC1458.C (only)

'"
on

PIN CONNECTIONS
I

J

Schematic
G & Pl Packages

ABC

0

E

F

G

H

L&P2Packages

1
2 3

4

2
5

3
6

4
7

5
8

6 7 8
910"1214

K

L

0.5 ms/DIV.

I
Ik

1k

See Packaging Information Section for outline dimensions.

See current MCCF1558/1458 data sheet for flip-chip information.

7-249

MC1558, MC1458, MC1458C(continued)

MAXIMUM RATINGS (TA = +250 C unless otherwise noted)
Rating
Power Supply Voltage

Symbol

MC1558

V+

+22

V

For supply voltages of less than ±.15 V, the maximum differential input voltage is equal to ±.(v+ +

lv-\).

(3) For supply voltagat of less than ±.15 V, the maximum input voltage is equal to the lupply voltage (+V+ ,·-Iv-I).

7-250

@TIOW: OoC for MC1458,C
_55°C for MC1558
Thigh: +75 0 C for MC1458,C
+12SoC for MC1558

MC1558, MC1458, MC1458C (continued)

FIGURE 2 - CIRCUIT SCHEMATIC

FIGURE 3 - EQUIVALENT CIRCUIT
WITH OFFSET ADJUST

r-_r----------~--~------------~----------_r--ov'
l

25
OUTPUT
A1K)

v'

v- F

50

l

OUTPUT '2
V·

Theletterswithoul parellthesisreprtsenl Ihe pin numbers for 112 of the dual circuit,
letters in parenthesis represent Ihe pinflumbersforthe olher half.

PIN CONNECTIONS
SCh.8rp8tic
G & P1 Packages
L & P2 Packages

ABC

1

2

3

4

0
2

5

E
3

6

F
4

7

I

G
5

8

H
6

I

J

K
7

10kn

J

V-._L_,. ..A"·'ViO

L
8

ADJUST

Offset Adjuslis available on1v in 14'pinpackaged devices.

9 10 11 1214

TYPICAL CHARACTERISTICS
(v+ = +15 Vdc, V- == -15 Vdc, TA == +2SD C unless otherwise noted,)
FIGURE 4 - OPEN· LOOP VOLTAGE GAIN
versus POWER·SUPPLY VOLTAGE

FIGURE 5 - OPEN· LOOP FREQUENCY RESPONSE

120

+120

CD 115
OS

+100

w

:s
'" +8 0

z
~ liD

'"

~

~

~

----

IDS

o
~ 100

V

95

--~

~

z

;;:

~ +6 0

'"""~ +40

o

~

>

~+20

90

~

~

..l

o

~

85

80

o

3.0

6.0

9.0

12

IS

18

21

-20
1.0

24

100

10

1.0 k

~

lOOk

10k

FIGURE 6 - POWER BANDWIDTH
(LARGE SIGNAL SWING versus FREQUENCY)

'"

I.OM

f, FREOUENCY (Hz)

V+and V-, POWER·SUPPLY VOLTAGE (VOLTS)

FIGURE 7 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE

10M

I

100
70

24r--r1-HK~---r~~H*--+-~++~~+-t++HtH

~ 20r--+-r++H+~-4-+44+H*---~-+~~--+-t+++~

3: 50
z

~ 16r--+-+~+H#-~~-hHt~--+-~++H#i\4r~~hH~

o

~iii

~ 12~-+-+44tH#-~-4-rH+~--+-~+rH*_\~-4-rH+~
~

c::

6

>

8.0

r--

1111

./

30

'"~
li!

Vo = 0

-

/'

20

C

(VOLTAGE FOLLOWER)
± IS VO LT SUPPLI ES 1tt---+-~+rH*---1'c+-HK+ttI

11111~HO<15%1

./

.§ 40

/

10

/

~ 7.0

1\

4.01--+-+++1ftHt--11111-+-+It+t+tt
III r--+-r++1+ttI---t-+''kH+Itl

1

°1~0--~~~~10~0--~-U~I~.07k~~-U~1~0~k~~~~1~00k

5.0
4. 0
3. 0
2.0

/
6.0

10

14

18

If' and V-, POWER SUPPLY VOLTAGE (VOLTS)

f, FREOUENCY (Hz)

7-251

22

MC1558, MC1458, MC1458C (continued)

TYPICAL CHARACTERISTICS (continuedl

(v+ = +15 Vdc, V- = -15 Vdc, TA

= +250 C unless otherwise noted.l

FIGURE 8 - OUTPUT VOLTAGE SWING
versus LOAD RESISTANCE

FIGURE 9 - OUTPUT NOISE versus SOURCE RESISTANCE

1.4 ~~~~~~-~~~~A-v-=-IO-OO~I~I~I~r~lT~n

1:

i

1l1+--- RS = R3 = RI R2
1.21--+-+-+++-H+I--I-II-+-I.I-
~ 121-----f--f--l-l-l

1 t==tf~~~~~~~~~Av~=~R~lt=t~ltl~II~1
.!:.

1.0

~-~
~
~ 0.8 _

....

....
::>

_

~O.6_

";; 8.0 1---~tL__+-4-4-l
>

-

RI

+

AV _ 100

R2

Vo

1+1+I+---.f--h!4++!-H

R3

~
1..,.-,'
In-r...--,...-.--r+-Hdl.l-+o'=-+-+-++t+++l
~~~~I~r~IIT~91=*+II+R~--~Ar~

o
~ 0.41---+.1.,....1~

4.0~-+-I--H--t

A~
0.1 L-L....bd",bl,:bbbbd:ddbbl:dd:l:r==::::r:...J..b!::I:ttIJ
100
1.0 k
10 k
100 k

0.2

RL, LUAU RESISTANCE (OHMS)

RS, SOU RCE RESISTANCE 10HMS)

FIGURE 10 - HIGH-IMPEDANCE, HIGH-GAIN
INVERTING AMPLIFIER

v·

I

7-252

POSITIVE VOLTAGE REGULATORS

MC1S60, MelS61
MC1460, MC1461

MONOLITHIC VOLTAGE REGULATOR

POSITIVE-POWER-SUPPL Y
VOLTAGE REGULATOR
INTEGRATED CIRCUIT

· .. designed to deliver continuous load current up to 500 mA without
use of an external power transistor.
•

Electronic "Shut·Down" Control and Short·Circuit Protection

EPITAXIAL PASSIVATED

• Excellent Load Regulation (Low Output Impedance = 20 milliohms
typ from dc to 100 kHz)
• High Power Capability: To 17.5 Watts
•

Excellent Transient Response and Temperature Stability

• High Ripple Rejection = 0.002 %IV typ
• Single External Transistor Can Boost Load Current to Greater
than 10 Amperes
• Input Voltages to 40 Volts (MC1561)

Pin 10 electrically

connected
to case

Case is ground terminal

through substrate.

TYPICAL APPLICATION
+Vin

G SUFFIX

R SUFFIX

METAL PACKAGE
CASE 602A

METAL PACKAGE
CASE 614

+Vo

RSC

MC1560/MC1561
MC1460/MC1461
4.7 k

Co

Rl
Case
110)

~"I

R2
6.8 k

-=

-=

Select Rl to give desired Vo:
Rl~(2Vo

-7.0)kn

CIRCUIT SCHEMATIC
+Vlno--.----~----~--------------~~----------~----------~--__

3

OUTPUT

60 k

4
'-----------+---+-"-pt~ro CU R R EN T LI MIT

rr----<>

OUTPUT SENSE

5
rc'---------+----I----+----t---~9 DC SH I FT OUTPUT

Li--~~---------J '----t::::~::~--~60UTPUTREFERENCE
+----------'\...,.,----------t---------~7 NOISE F I L TE R

~------------------t---------~8 OCSHIFTSENSE

5.0
k
GNO
10·0---·~~~--~~------~~

______

~

______________________

·"G" package - pin 1 0 is ground. "A" package - case is ground.
See Packaging Information Section for outline dimensions.

7-253

~

•

MC1560, MC1561, MC1460, MC1461 (continued)

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Load Current = 100 mA for "R" Package device.
1
h'
d)
= 10 mA for "G" Package device, un ess at erwrse note
Ch.recteristic Definitions Uine.r operation)
IRse'" 2.7 ohms unless oth.rwise noted)

.".-'~
Rl
Vref

fl2 • 6.8 k

J
-=

~('
2

(10) CASE
C

-= -= 0.1 ~F

1 Cal ~

I

10"F

IL

Output Voltage Range

Units

Typ

Vdc

9.0
8.5
9.0
8.5

20
20
35
40

MC1460. MCI560

2.5
2.5
2.5

32
37

MC1461

MC1561
RL

Min

MCI460
MCI560
MCI461
MCI561

I-SSoC to +12SoCI
(0 to +7S0C)
(-5S0C to +12So CI

CONNECTION FOR Va ~ 3.5 V

I'

Symbol

Ch.racteristk:
Input Voltage (See Note 11
(0 to +7soCI

7;:~~~:'g~:~~~~(Vin"'15VJ

Vref

3.2

17

3.5

3.8

Vdc

Vdc

f---.:..--------------+--+-+--f----f-----I
Minimum Input-Output Voltage

-=-=

Differential (See Note 21
1Rsc = 01

Vdc

MC1460. MC1461
MC1560. MC1561

2.1
2.1

3.0

5.0
4.0

12

2.7

Select R1 to give desired Vo: R 1:::::: 12 Vo - 71 kG

Bias Current (Vin = 15 VJ

mAde

IS

ilL" 1.0 mAde. R2"'6.8 kn,
IS'" lin ~ ILl

MC1460. MC1461
MC1560. MC1561

Output Noise
(Cn = 0.1 ",F. f= 10 Hz to 5.0 MHz)

RL Temperature Coefficient of Output
Voltage (See Note 3)
(0 to +750 CI
(_55° to +125 0 C)

Select A2 to give delired Va! R2~(2 Vol kn
Select R1: R1~ (7.0 kG - R21 kn

mV(rms)

0.150

MC1460. MC1461
MC1560. MC1561

"-0.002
±O.OO2

Operating Load Current Range·
IASC ~ 0.3 ohms) R Package
(ASC 1! 2.0 ohms) G Package

mAdc
1.0
1.0

Input Regulation (% change in output voltage
per 1·voltchange in inputvoltagel
MC1460. MC1461
vo(rms) (100)
Regin '" vin Irmsl Vo Vin (rmsl

9.0

Vn

Regin

MC1560, MC1561

500
200

0.003
0.002

0.030
0.015

%lV o

ISee Note 4i

+16V

I L - Vo "10V

~__~3'---17,o-~I~.D~~,-_~o

:::?nIF-"t _

Load Regulation
TJ "'Constant (1.0mASILS20mAI

T C '" 25°C (See Note 51
(1.0mASILS' 50mA)

Output Impedance (See Note 61
IRsc'" 1.0ohms.f= 10 kHz, Vin'" 14 Vdcl
(I L = 25 mAdc for G Package)

mV

MC1460
MCI560
MCI461
MCI561

0.5

0.3
0.7
0.4

R Package

0.005

G Package

0.01

{V in '" 35 Vdcl

0.05
0.13

Zout

MC1460
MCI560
MC1461

25
15
35
20

100
60
120

MC1460
MC1560

80
20

300

MC1461
MC1561

140

500
150

MCI561
Shutdown Current
(Vin'" 20 Vdc)

2.0
1.2
2.4
1.6

%

milli·
ohms

80
J'Adc

IscI

70

50

·Operating Load Current is also limited by dc Safe Operating Area (see Figures 15A and 1581. Care must be taken not to exceed the dcSafa Operating Area at any time.

7-254

MC1560, MC1561, MC1460, MC1461 (continued)

MAXIMUM RATINGS (TC = +25 0 C unless otherwise noted)
Rating
Input Voltage

Symbol

Value

Unit

Vi"

20
35
40

Vdc

MC1460, MC1560
MC1461
MC1561

G Package

R Package

Load Current

IL

250

600

mA

Current. Pin 2

Ipin 2
Iping

10
5.0

10
5.0

mA

Po
1/8JA
8JA
Po
1/8JC
8JC

0.68
5.44
184
1.8
14.4
69.4

3.0
24
41.6
17.5'
140
7.15

Current, Pin 9
Power Dissipation and Thermal Characteristics
TA = 25°C
Derate above T A = 25°C

Thermal Resistance, Junction to Air
TC = 25°C
Derate above T C

= 25°C

Thermal Resistance, Junction to Case
Operating and Storage Junction Temperature

TJ, Tstg

-65 to +150

Watts
mW/oC
°C/W

Watts
mW/oC
°C/W

°c

Range

·The MC1460R and MC1560A are limited to 12 watts maximum by the \/oltage and current
maximum ratings.

OPERATING TEMPERATURE RANGE
Ambient Temperature

o to +75
-55 to +125

MC1460. MC1461
MC1560, MC1561

Note 1.

"Minimum Input Voltage" is the minimum "total instantaneous input voltage" required to properly bias the
internal zener reference diode. For output voltages greater
than approximately 5.5 Vdc the minimum "total instantaneous input voltage" must increase to the extent that it
will always exceed the output voltage by at least the
"input-output voltage differential".

Note 4.

The input signal can be introduced by use of a transformer
which will allow the output of an audio oscillator to be
coupled in series with the de input to the regulator. (The
large ac input impedance of the regulator will not load
the oscillator.) A 24 V, 1.0 ampere filament transformer
with the audio oscillator connected to the 110 V primary
winding is satisfactory for this test. vin ~ 1.0 V (rms).

Note 2.

This parameter states thatthe MC1560/1561 and MC14601

Note 5.

Load regulation is specified for small (S+17 0 C) changes
in junction temperature. Temperature drift effect must
be taken into account separately for conditions of high
junction temperature changes due to the thermal feedback
that exists on the monolithic chip.

1461 will regulate properly with the input·output voltage
differential (Vin - Vol as low as 2.7 Vdc and 3.0 Vdc reo

spectively. Typical units will regulate properly with (VinVol as low as 2.1 Vdc as shown in the typical column.
Note 3.

"Temperature Coefficient of Output Voltage" is defined as:

Load Regulation

VO)lL = 1.0 rnA SO)lL = 50mA

=

X 100

V o )lL=1.0mA

Note 6.

MC1460, TC
= ± (Vo max - Vo min)(loo) = %/oC
MC1461
Vo
2 (750 C)(V o @ 250C)
The output-voltage adjusting resistors (Rl and R2) must

have matched temperature characteristics in order to maintain a constant ratio independent of temperature.

The resulting low level output Signal (va) will require the
use of a tuned voltmeter to obtain a reading. Special care
should be used to insure that the measurement technique
does not include connection resistance, wire resistance,
and wire lead inductance (i.e., measure close to the case).
Note that No. 22 AWG hook-up wire has approximately
4.0 milliohms/in. dc resistance and an inductive reactance
of approximately 10 milliohms/in. at 100 kHz. Avoid use
of alligator clips or banana plug-jack combination.

GENERAL OPERATING INFORMATION
There is a general tendency to consider a voltage regulator as
simplv a de circuit and to prepare breadboard con~uction accordingly. The excellent high-frequency performance and fast response
capability of this integrated-circuit regulator, however, makes extra
breadboarding care worthwhile when compared with the limited
performance achieved in other regulators when low-frequencv transistors are used in the feedback amplifier. Due to the use of VHF
transistors in the integrated circuit, some VHF care (short~ weildressed leads) must be exercised in the construction and wiring of
circuits ("printed·circuit" boards provide an excellent component
interconnection technique).

The circuit must be grounded by a low-inductance connection to
the case of the "R" package, or to pin '10 of the "G" package.

A series4.7·k!1 resistor at Pin 5 (Figure 1) will eliminate any VHF
instability problems which may result from lead lengths longer than
a few inches at the regulator output. The resistor body should be as
close to Pin 5 as physically possible «1/2 inch) although the length

of the lead to the load is not critical. If temperature stability is of
major concern, a 4.7·kn resistor should also be placed in series with
Pin 6 in order to cancel any drift due to bias current changes.

7-255

I

MC1560, MC1561, MC1460, MC1461 (continued)

allel resistance_ Further, no match to a diffused-resistor temperature
coefficient is required; but R1 and A2 should have the same temperature coefficient to keep their ratio independent of temperature.
Cn values in excess of 0.1 #IF are rarely needed to reduce noiss.
In cases where more output noise can be tolerated, a smaller capacitor can be used (Cn min. "" 0.001 "Fl.
The connection to Pin 5 can be made by a separate lead directly
to the load. Thus "remote sensing" can be achieved and undesired
impedances (including that of a milliammeter used to measure ILl
can be greatly reduced in their effect on Zout. A 10-ohm resistor
placed from pin 1 to pin 5 (close to the IC) will eliminateundesirable
lead-inductance effects.
Short-circuit current-limiting is achieved by selecting a value for
RSC which will threshold the internal diode string when the desired
maximum load current flows (see Figure 5). If the device dissipation
and dc safe area limits (Figure 15) are not exceeded, it can be continuously short-circuited at the output without damage.

If long input leads are used. it may be necessary to bypass Pin 3
with a O.1-,..F capacitor (to ground).
The "Shut·Down Control", Pin 2, can be actuated for all possible
output voltages and any values of Co and Cn with no damage to the

circuit. The standard logic levels of RTL, DTL, or TTL can be used
(see Figure 20). This control can be used to eliminate power consumption by circuit loads which can be put in a "standby" mode, as
an ae and de "squelch" control for communications circuits. and as

a dissipation control to protect the regulator under sustained output
short·circuiting (see Figures 21 and 25). As the magnitude of the
input-threshold voltage at 'Pin 2 depends directly upon the junction

temperature of the Ie chip. a fixed de voltage at Pin 2 will cause
automatic shut-down for high junction temperatures (see Figure 23.
a and b). This will protect the chip, independent of the heat sinking

used, the ambient temperature, or the input or output voltage levels_
Due to the small value of input current at Pin 8, the external
resistors. R1 and R2. can be selected with little regard to their par-

TYPICAL CONNECTIONS
FIGURE 1 - CONNECTION FOR Vo :. 3.5 V
60,--..,.--.---.----,,--..,.----,,---..,
(RIJ (ZVo -7ik!l1
5 0 / - - - + - - + - (RZ = 6.8 knl

~
~
B
RI

E

40

~

Co

r-L--_.---_--r_..J

V

w
'-'

z

30

'"
In
~

RL

V

ZO

V

'"
10

RZ
6.B k

//

0
0

-•

V

V

5.0

10
15
ZO
Z5
Vo, OUTPUT VOLTAGE (VOLTS)

-=

30

35

Select RI to give desired Vo: R1o:::s (2 Va -7.0) kn

FIGURE 2 - CONNECTIONS FOR Vo S +3.5 V
Z.O
+Vin
0

~
RI

l

R-rV

I-

+ IL
CD

O.I/IF
RZ

-=

i

~r
Iw 1

~:SE

(101

Z

t

IO/IF

-=

-=

'::'

RL

w

'-'

z

'"

In

1.0

I-

"

ili

'"

w

RZ

'-'

z

6.0

-=-=

:if

'(rZ ~ Z (Vol kill
0
0

RZ

7-256

Z.5

3.0
Vo. OUTPUT VOLTAGE (VOLTSI

'"

In

~

"'

'"

(Z Vol kll

~7.0kll-

g

R1

~

Sel.ct RI:

RI

(7kIl- RZI knl

t-

E

Select R2 to give desired Va:
RZ~

7.0
(RI~

5.0
3.5

MC1560, MC1561, MC1460, MC1461 (continued)

TYPICAL CHARACTERISTICS
Unless otherwise stated:

Cn = 0.1 f.LF. Co = 10 f.LF. Vo nom = +5.0 Vdc. Vin nom = +9.0 Vdc.
TC = +25 0 C. IL > 200 mA for "R" Package only.

FIGURE 3 - INPUT TRANSIENT RESPONSE

FIGURE 4 - LOAD TRANSIENT RESPONSE

~~IBmglml ;I'OO~~'OO
-.<

s:~

U50~~90

Ir"II""20n$

Ir=tf=2IlS

>

13
~ 10.005

-

w

~

......

o

~ 10.000 "

w

"'

I<-

o

~

-

'" ......

!;

~ 10.000

9.950

FIGURE 6 - CURRENT·LIMITING CHARACTERISTICS

FIGURE 5 - SHORT-CIRCUIT CURRENT versus RSC

1.01

600

"<

.§

w

500

:==>

,

300

0

"

~

i:i

100

' ..

............

0

~

o

o

1.00

>
!; 0.99

,,

400

ZOO

~

0

0

~

to

_1- _ R ~ackag. ol'IV

\,

<

::...

1.0

Z.O

3.0

"'""--

4.0

~
N
:::;

--

5.0

< 0.97
~

0

z

-

oj 0.96

oi

6.0

7.0

B.O

9.0

10 0

0

]

w
u

z

<

0

~

!!

...=>

:==>

0

--'

0

j

0

0
0.001

0.01

V

/

0.1

ZO

40

-r-:::'II
60
BO

100

IL. LOAO CURRENT (rnA)

. FIGURE 8 - DEPENDENCE OF OUTPUT IMPEDANCE
ON OUTPUT VOLTAGE

FIGURE 7 - FREQUENCY·DEPENDENCE
OF OUTPUT IMPEDANCE

~

RSC =6.B OHMS

0.9B

RSC. EXTERNAL CURRENT·L1MITING RESISTOR (OHMS)

~

9.999

lOpS/DIV

O.lpS/Div

10J.l.S/DIv

2.0pS/DIV

1:l

10.000

~

9.99 5

~

J

>

.j

...

1~

~~ 0

0

/
V

~~'=~~5~~ 3.0 V

_ I--

RSC =0 Ohms
10 rnA to 500 rnA

I--

0

1.0

10

f. FREQUENCY (MHz)

7-257

16
B.O
Vo• OUTPUT VOLTAGE (VOLTS)

Z4

3Z

•

MC1560, MC1561, MC1460, MC1461 (continued)

TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: Cn = 0.1 J.lF, Co = 10 J.lF, Vo nom = +5.0 Vdc, Vin nom = +9.0 Vdc,
TC = +25 0 C, IL > 200 mA for "R" Package only.
FIGURE 9 - OUTPUT IMPEDANCE versus RSC

FIGURE 10 - FREQUENCY·DEPENDENCE
OF INPUT REGULATION

,

40

0.009

J

§

~ 0.00 6

w
u

z

~

~

20

:!
!;

~....

:=

/

MCI460
MCl461

~ 0.003

- 'l

;:;

:0
0

MCI560
MCI561

~

0
5.0

0

o

15

10

0.001

0.0001

2.5,,----,----=="""'--'T'"----,

/'

-

l!

\

'"
«

~~2'3

~ ~ :..>(".

.s....

I
~
a;

\

.,<'

/'"

R2=6.Bk

..... ..........10

2.2hL.---+---:;."L.::..........Jr-!--....".."L.:::.....-+-----l

15

~ ~ 2.11---.",..4----,7"~-----+-----l

/'"

":'2

:ow

~ ~

20

i

I

25

30

2.0!--,,,.L---+...,.,.q-,--+-----+-----l

~~ 1.9!--,---F--f-----+-----+-----l

\TJ =·55 0 C

4.0
5.0

~ ~

~­
....
~

TJ= DoC

I- IL=1.0mA

!E

>~

TJ=+25 0 C. /

~

4.5

2.41-....:...---1II".o"""-----f----~-=--_l

w

. / "/
...? " /

TJ = +750 C AND +125 oC

;;
35

40

125

Vin. INPUT VOLTAGE (VOLTS)

,
~

0.004

~
~

~

;:;
.E

OF SHORT·CIRCUIT LOAD CURRENT

~"

TJ - +1250 C
5

../

r-- I--

TJ '" +25 0 C

............ j...,

I--

0

I

b-- +--

0.00 2

500

500

1""-"
.....

"-

375

FIGURE 14 - TEMPERATURE DEPENDENCE

DIFFERENTIAL ON INPUT REGULATION

l"-

:0

....

,

250
IL. LOAO CURRENT (mAde)

FIGURE 13 - EFFECT OF INPUT-DUTPUT VOLTAGE

0.006

1.0

0.1

FIGURE 12 - EFFECT OF LOAD CURRENT ON
INPUT·OUTPUT VOLTAGE DIFFERENTIAL

FIGURE 11 - BIAS CURRENT versus INPUT VOLTAGE
5.0

0.01
f. FREQUENCY (MHz)

RSC. EXTERNAL CURRENT·L1MITING RESISTOR (OHMS)

TJ· -550 C

+--

I

-FF

I--

RSC = 3.0 OHMS
RSC· 610 OHMS

5
IL=1.0mA

~
0

f4-

RSC = 2h OHMS
Vo = 3.5 Vde

o=10Vd

8.0

16

24

32

0
·55

·25

+25

+50

+75

TJ. JUNCTION TEMPFRATURE (DC)

Vin - Vo. INPUT·OUTPUT VOLTAGE DIFFERENTIAL (VOLTS)

7-258

+100

+125

+150

MC1560, MC1561, MC1460, MC1461 (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 15. - DC SAFE OPERATING AREA I"G" PACKAGE)

FIGURE 15b - DCSAFE OPERATING AREA I"R" PACKAGE)

0.3

O. 7

0.2

i o.
~

I

0.6

,

,

,,

---·Secondary Breakdown Limitation
- - - Bonding Wire limitation

.2 0.08
0.07
0.0 6
0.0 5

0.03
3.0

i

r~

- - - - - Thermal Limitation IT C=250 C)
TJ ,"':

',i

"

MC1463

",C

,Ma~

1_" ..500
200
'0.002

O.OU'

:7,.0
...• ,.

1.0
1.0

-

±a.002

-

-

-

%/oC
mAde

500
200

0.003

0.030

%IVO

-

0.7
0.005
0.01

2.4
0.05
0.13

mV
%

-

35

120

milliohms

!:,:1,5 ,' -

14

50

/1Adc

'0;4
',.6,
,0.005 '.',0.•05,:
,0;01
0.,\3

20

-

.

"V(rmsl

'·80

,;

-

-

MC1563, MC1463 (continued)

Note 1.

Note 2.

"Minimum Input Voltage" is the minimum "total instantaneous input voltage" required to properly bias the internal
zener reference diode.

Input Regulation =

The following example illustrates how to compute maxi-

IVin - Vol as low as 2.7 Vdc and 3.0 Vdc respectively.

mum output voltage change for the conditions given:
Regin = 0.015%IVO
Vo = 10Vdc
vin = 1.0 Vlrms)

"Temperature Coefficient of Output Voltage" is defined
as:

(Regin)lvin)lVO)

± (VO max - Vo mini (1001

t:. T A

(0.015)11.0)(10)
100

= 0.0015 V(rms)

= +180o C for the MC1563
+750 C for the MC1463

Temperature drift effect must be taken into account
separately for conditions of high junction temperature
changes due to the thermal feedback that exists on the

Note 5.

The output-voltage adjusting resistors (RA and RS) must
have matched temperature characteristics in order to maintain a constant ratio independent of temperature.
Note 4.

100

Vo =

TCVO = - : - - - - - - - - - : : - - I:; TA (VO @TA = +250 CI
where

100 1%lVo)

where Vo is the change in the output voltage Va for the
input change vin.

This parameter states that the MC1563/MC1463 will regulate properly with the input-output voltage differential
Typical units will regulate properly with IVin - Vol as low
as 1.5 Vdc as shown in the typical column.

Note 3.

~

Vo IVin)

monolithic chiD.

I nput regulation is the percentage change in output voltage
per volt change in the input voltage and is expressed as

TEST CIRCUITS

(lL = 100 mAde, TC = +25 0 C unless otherwise noted)
FIGURE 4 - GENERAL TEST CIRCUIT

FIGURE 5 - LOAD TRANSIENT RESPONSE

r-.---------~_1--;r----_4r---~--;r.'NO

O.TpF
C,
0.1 ~F

CASE/TO Re

r.---..L........Ic,

CASE/IO

B.8k

S.8k

1
Vref

~

RA

-

MC1SS3
MCT4S3

:t:""'"';';:~-r-i.,..,...-;:----:-t-<>::-~--=~--"~vo

VO"-10Vdc

Select RAlogiv.de~ired YO: RA"" (2IVOr -1) tn

FIGURE 6 - INPUT REGULATION

FIGURE 7 - LOAD REGULATION

~'-----------~~~-r----~--~--~.GND

r---------~--~_4r-----~--_1----~GNO

O.lpF
Regin =

CASE/TO

6.8k

v~~~~s; ~~O

II.Bk

+ IOj.lF

13k_

10'

RL
MCI563
MCl463

MClS63
MCl4S3

VO=-10Vdc

VO=-10Vdc

FIGURE 8 - OUTPUT IMPEOANCE

FIGURE 9 - SHUTDOWN CURRENT

..

...--------------~~_r------~--~--~

...--________,'.1"

GND

O.ljJF
CASEIlO

CASE/lO

6.Bk
36k

1

R""IVinlknfor
1 mAde

Uk

10.
RL

~I"
MCIS63
MG1463

MGI5S3
MCI463

10

Vo
J 1=5mAfrms)
~~~~~~L-------~~-+~~~,,~t:~~~"
Vinll-15Vdc
Zo=5mA
VO"'-10Vdc

O.OOlpF

~~~"f-L

Vin'"-35Vde 1.0

(MC1563 - Pg. 3)

7-267

__rrr-""'---"~""""v,

•

MC1563, MC1463

(continued)

GENERAL DESIGN INFORMATION
1. Output Voltage, Vo
a) Output Voltage is set by resistors RA and RB (see Figure 10).
Set RB = 6.B.k ohms and determine RA from the graph of
Figure' 11 or from the equation:

FIGURE 10 - TYPICAL CIRCUIT CONNECTION

r-e----------1~-1~_t------~---1~--~GND

RA"" (2iVoi-7) kn

Co
O.l"F

b) Output voltage can be varied by making RA adjustable as
shown in Figures 10 and 11.

6.8 k R8
CASEIlD

c) Output voltage, VO, is determined by the ratio of RA and RB
therefore optimum temperature performance can be achieved
if RA and RS have the same temperature coefficient.

MC1563
MCl463

d) Vo = Vref (1 + RA); therefore the tolerance on
Cc
D.DD1,.F

RB
output voltage is determined by the tolerance of Vref and
RA and RB.
2. Short-Circuit Current, Isc
Short-Circuit Current, 150 is determined b.y Rsc. Rsc may
be chosen with the aid of Figura 12 when using the typical
circuit connection of Figure 10. See Figure 29 for current
limiting during NPN current boost.

Rsc.
VI".-4-..;;,i,,-....

O--l____.J-s<)--<~_:~:li"A":
... VD
6
RA

Select AA tD Give Desired VO:

3. Compensation, Cc
A 0.001 "F capacitor (Cc ' see Figure 10), will provide

4. Noise Filter Capacitor, Cn
A 0.1 "F capacitor, Cn , from pin 3 to ground will typically
reduce the output noise voltage to 120 "V(rmsl. The value
of Cn can be increased or decreased, depending on the noise
voltage requirements of a particular application. A minimum

value of 0.001 "F is recommended.
5. Output Capacitor, Co
The value of Co should be at least 10 "F in order to provide
good stability.

Vo 1-71 kn

VOIII# -3.5 (1 +iB)

FIGURE 11 - RA versus Vo

adequate compensation in most applications, with or without

current boost. Smaller values of Cc will reduce stability and
larger values of Cc will degrade pulse response and output
impedance versus frequency. The physical location of Cc
should be close to the MCI563JMCI463 with short lead
lengths.

,AA ~ (2(

60
50

g

(R~ '" (2 Vo JI kn)

/'

I--- (RB = 6.B kll)

V

40

V

w
<.>

z

~
ill
'"
'"

.

30

V

20

//

10

//

6. Shutdown Control
One method of turning "OFF" the regulator is to draw 1 mA
from pin 2 (See Figure 9.) This control can be used to

-15

-10

-5.0

-20

-30

-25

-35

VO.OUTPUT VOLTAGE (VOLTS)

eliminate power consumption by circuit loads which can be

put in "standby" mode.

Examples include, an ac or dc

"squelch" control for communications circu its, and a dissi~
pation control to protect the regulator under sustained out-

•

put short-circuiting. As the magnitude of the input-threshold
voltage et pin 2 depends directly upon the junction temperatureof the integrated circuit chip, a fixed de voltage at pin 2
will cause automatic shutdown for high junction temperatures (see Figure 37). This will protect the chip, independent of the heat sinking used, the ambient temperature, or
the input or output voltage levels. Standard logic levels of
MECL , MRTL ,MOTL or MTTL can also be used to
turn the regulator "ON" or "OFF" (see Figures 32 and 33).
7. Remote Sensing
The connection to pin 8 can be made with a separate lead
direct to the load. Thus, "remote sensing" can be achieved
and the effect of undesired impedances (including that of
the milliammeter used to measure IL) on Zo can be greetly
reduced (see Figure 35).

FIGURE 12 - 150 versus Rsc
500

«

.§.

lz
w
'"'"

400

..

i'$

c 300

g

....

B 200
~

'"

~ 100

j

Te

1\

\
\

"

t'-....

10

"""'"'-

=i+250e

-

20

30

40

Rsc. EXTERNAL CURRENT-LIMITING RESISTOR (OHMS)

(MC1663 - Pg. 4)

7-268

50

MC1563, MC1463 (continued)

TYPICAL CHARACTERISTICS
Unless otherwise noted: Cn = 0.1 pF,Ce = 0.001 pF, Co = 10pF, TC = +25 0 C,
Vin(nom) = -15 Vde, VO(nom)= -10 Vde,IL = 100 mAde
FIGURE 13 - TEMPERATURE DEPENDENCE
OF SHORT·CIRCUIT LOAD CURRENT

FIGURE 14 - FREQUENCY DEPENDENCE
OF OUTPUT IMPEDANCE

2000

800
1700

!z:
~

cr:

:::>

3n ..

...9 400
::;

4n

«

~ 200
~

-75

: 500

'--

-50

:i!c

-- -- ............ .......

r--....

r-- I--

Ion
13n

100

r-..

r- t"" ...........

5n

~ 300

U

'"

'"~

50

./

30
20
1.0

+150 +175

10

100

TJ. JUNCTION TEMPERATURE (DC)

FIGURE 15 - DEPENDENCE OF OUTPUT
IMPEDANCE ON OUTPUT VOLTAGE

FIGURE 16 - OUTPUT IMPEDANCE versus Rsc

50

0
5

!

IVin - tOI = 3.0 Iv. TJ = +150 c
Rsc=0.IL=IOmAto500mA != 1.0 kHz

30

w

u

z

5

~

20

«

...:!!~
~

a

..sw

""'-.

15

«

30

...~
...

20

fil
~

........

10

r--

:::>

'"~

5.0

o

o

-10

40 -

-20

-30

IL =lamA
!=I.OkHz

u

z

:::>

'"

----

~

10

o
o

-40

3.0

VO. OUTPUT VOLTAGE (VOLTS)

~

9.0

6.0

V

/

15

12

R". CURRENT LIMITING RESISTOR (OHMS)

FIGURE 17 - FREQUENCY DEPENDENCE
OF INPUT REGULATION

FIGURE 18 - CURRENT LIMITING CHARACTERISTICS

_cl.ooo~~~mlll~l*m,"~~~~;11
F
~

1000

!. FREIlUENCY (kHz)

Vin=-17 V

t-::=t=t=l=l+tm==I==I=t+VO
=-10 V-+:::j::::j:#~
tIL=50mA-t

S
~ 0.100!~"III~~~;III~lfll;
:::>

'"
w

...cr:

1.03

~ 1.02

c:

R~= 130~MS

1.01

>
~ 1.00

...

"""\

:::>

'" 0.99
c

w

;:j

I~0'010~1I1I

«

""z 0.97
~

• •

0.001
1.0

0.98

~0.96

o
10

100

1000

!. FREIlUENCY (kHz)

o

20

40

60

80

100

IL. LOAO CURRENT (mA)
(MC1563 - Pg. 5)

7-269

120

140

160

MC1563, MC1463 (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 20 - EFFECTS OF LOAD CURRENT
ON INPUT.QUTPUT VOLTAGE DIFFERENTIAL

FIGURE 19 - BIAS CURRENT .....us INPUT VOLTAGE
6.0

-

TJ = -55 0 C

-

..- ~

i:-<

4. 0

-5.0

6

-

4

TJ :+125 0 C

TC=+250 C

-

2

-20

-15

-30

-25

-40

!I:I

1= l)kHz

~ 0.00 2
c!!
TJ = -550 C ..;;.
0

2

r-- kL

~

>

I

VO=-3.6V
15

-9.998 f---.JI---1--1--+--+--+--+-+-+--1

~ -10.00°r-~r----j-"i---t--t--t--t:=::::l:==::f:=9

~ b..L

10

20

25

30

~

-10.004

~

-10.006f--I1---1---11--+--+--+--+-+-+--1

~

-10.0081-_l...---.JL---JL---1_--1_--l._--l._--L_-L_....l

o

35

40

IVin -VOl. INPUT·OUTPUT VOLTAGE DIFFERENTIAL (VOLTS)

100 ""OIV

.

FIGURE 24 - DC OPERATING AREA

FIGURE 23 - LOAD TRANSIENT RESPONSE
+125

+105

O. 6

01+10 0

+100

O. 4

""'"
g~ ~

=a

(

+751---1-1, = II

i 20 ns- I - -

I

+5 0

~o

+2 5

~

-9.750

I

1,=11=500",

~

+95

\

+90

-

-

Z

500

400

300

200

-+--+--r--4--i--1--l
o -100021--+-+-.......
.

TJ =+250 C

VO--l0V
5.0

~

TJ=+125 0 C

~

~

Tr=+ITC-

lUi111J

I

o -25
>

o

~

1'//

FIGURE 22 -INPUT TRANSIENT RESPONSE

c

~z 0.00 6

...

V

V/ V

IL. LOAD CURRENT (mAde)

0.008

~

"

I-- t:::.: ~ ~ t-....

100

FIGURE 21 - EFFECT OF INPUT.QUTPUT VOLTAGE
DIFFERENTIAL ON INPUT REGULATION

0.004

Y V

1.0

-35

Vin. INPUT VOLTAGE (Vde)

~
"
~

v' V

TC = -55 0 C

J..-r"'

-10

V)

I..--

~

TJ = +250 C

J

V-

110..- ~ V-

-

1. 8

l---.._

IL=I.0mA
RB =6.8 kn

+85

-9.998

PACKAGE

O. 3
w

~ O. 2

I

'"
S

"L

G PjCKjGj

,

~O.05

-----SECONDARY

MC1463R
MC1563R

......

~ O. I
~ 0.0 7

o

~
o

~

'" ,

BREAK~OWN

,

:--

f-- l-

LIMITATI10NS

""90.0 3 ---BONDING WIRE LIMITATIONS

;:: -10.00 0

-10.000

I

:="

"~ -10.250

-10.002

>
10 ",/OIV

.:? 0.02

-

- -

THERMAL LIMITATIONS

f-TC = 25 0 C
I
0.0 1
4.0 5.0
3.0

1.0ms/OIV

MC1463G
MClj63G

I

1

1
7.0

10

20

30

40

IVin - VOl. INPUT·OUTPUT VOLTAGE DIFFERENTIAL (VOLTS)

(MC1563 - Pg. 6)

7-270

50

MC1563, MC1463 (continued)

OPERATION AND APPLICATIONS
This section describes the operation and design of the MC1563 (MC1463) negative voltage regulator and also
provides information on useful applications.
SUBJECT SEQUENCE INDEX

Specification Pg. No.
7
Theory of Operation
NPN Curren t Boosting
9
10
PNP Current Boosting
11
Positive and Negative Power Supplies
Shutdown Techniques
11
Voltage Boosting
12

Specification Pg. No.
Remote Sensing
12
An Adjustable Zero·Temperature·Coefficient 13
Voltage Source
Thermal Shutdown
13
Thermal Considerations
13
15
PC Board Layout and Information

THEORY OF OPERATION

is exactly the same approach used in the first option. That
is, the output is being resistively divided to match the
reference voltage. There is however, one big difference in
that the output of this "regulator" is driving the input of
another regulator (the error amplifier). The output of the
reference amplifier has a relatively low impedance as com·
pared to the input impedance of the error amplifier.
Changes in the load of the output of the error amplifier
are buffered to the extent that they have virtually no effect
on the reference amplifier.. If the feedback resistors are
external (as they are on the MC1563) a wide' range of
reference voltages can be established.
The error amplifier can now be operated at unity gain
to provide excellent regulation. In fact, this "regulatorwithin-a-regulator" concept permits the load regulation to
be specified in terms of output impedance rather than as
some percentage change of the output voltage. This approach was used in the design of the MCl563 negative
voltage regulator.

The usual series voltage regulator shown in Figure 25,
consists of a reference voltage, an error amplifier, and a
series control element. The error amplifier compares the
output voltage with the reference voltage and adjusts the
output accordingly until the error is essentially zero. For
applications requiring output voltages larger than the reference, there are two options. The first is to use a resistive
divider across the outP\,lt and compare only a fraction of
the output voltage to the reference. This approach suffers
from reduced feedback to the error amplifier due to the
attenuation of the resistive divider. This degrades load
regulation especially at high voltage levels.
The alternative is to eliminate the resistive divider and
to shift the reference voltage instead. To accomplish this,
another amplifier is employed to amplify (or level shift)
the reference voltage using an operational amplifier as
shown in Figure 26. The gain·determining resistors may
be external, enabling a wide range of output voltages. This
Series Control Element

Error

Amplifier

.
FIGURE 25 - Series Voltage Regulator

FIGURE 26 - The "Ragulator-Within·A·Ragulator" Approach

(MC1563 - Pg. 7)

7-271

MC1563. MC1463 (continued)

FIGURE 27

(Recommended External Circuitry is Depicted With Dotted Lines.)

Vref
and

6

I re1

Bias

Case/lO

·~T--~

,,
CoJ:t"

+

10/JF"r'

7 Vdc

r
L

8

,
I __

6

~ __

,
J

Vo

920

Output
~r-----o8

Sense

•

MCIS63 (MCI463) Operation

input voltage. It makes use of two zener diodes having
the same breakdown voltage. A first or auxiliary zener is
driven directly from the input voltage line through a
resistor (60 kn) and permits the regulator to initially
achieve the desired bias conditions. This permits the
second, or reference zener to be driven from a current
source. When the reference zener enters breakdown, the
auxiliary zener is isolated from the rest of the regulator
circuitry by a diode disconnect technique. This is necessary
to keep the added noise and ripple of the auxiliary.zener
from degrading the performance of the regulator.

Figure 27 shows the MCIS63 (MCI463) Negative Regulator block diagram, simplified schematic, and complete
schematic. The four basic sections of the regulator are:
Control, Bias, DC Level Shift, and Output (unity gain)
Regulator. Each section is detailed in the following paragraphs.
Control
The control section involves two basic functions, startup and shutdown. A start-up function is required since
the biasing is essentially independent of the unregulated

(MCl563 - Pg. 8)

7-272

MC1563, MC1463 (continued)

The shutdown control, in effect, consists of a PNP transistor across the reference zener diode. When this transistor
is turned "ON", via pin' 2, the reference voltage is reduced to
essentially zero volts and the regulator is forced to shutdown. During shutdown the current drain of the complete IC regulator drops to Vin/60 kn or 500 /lA for a
-30 V input.
Bias
A zener diode is the main reference element and forms
the heart of the bias circuitry. Its positive temperature
coefficient is balanced by the negative temperature coefficients of forward biased diodes in a ratio determined
by the resistors in the diode string. The result is a reference voltage of approximately -3.5 Vdc with a typical
temperature coefficient of 0.002%/oC. In addition, this
circuit also provides a reference current which is used to
bias all current sources in the remaining regulator circuitry.
DC Level Shift
The reference voltage is used as the input to a Darlington
differential amplifier. The gain of this amplifier is quite
high and it therefore may be considered to function as a
conventional operational amplifier. Consequently, negative
feedback can be employed using two external resistors (RA
and RB) to set the closed-loop gain and to boost the reference voltage to the desired output voltage. A capacitor,
Cn , is introduced externally into the level shift network
(vla pin 3) to stabilize the amplifier and to filter the zener
noise. The recommended value for this capacitor is 0.1 /IF
and should have a voltage rating in excess of the desired
output voltage. Smaller capacitors (0.001 p.F minimum)
may be used but will cause a slight increase in output
noise. Larger values of Cn will reduce the noise as well as
delay the start-up of the regulator.
Output Regulator
The output of the shift amplifier is fed internally to the
noninverting input of the output error amplifier. The

inverting input to this amplifier is the Output Sense connection (pin 8) of the regulator. A Darlington connected
NPN power transistor is used to handle the load current.
The short-circuit current limiting resistor, Rsc , is connected in the emitter of this transistor to sample the full
load current. This connection enables a four-diode string
to limit the drive current to the power transistors in a
conventional manner.
Stability and Compensation
As has been seen, the MC1563 employs two amplifiers,
each using negative feedback. This implies the possibility
of frequency instability due to excessive phase shift at high
frequencies. Since the error amplifier is normally used at
unity gain (the worst case for stability) a high impedance
node is brought out for compensation. For normal o.peration, a capacitor is connected between this point (pin 7)
and pin 5. The recommended value of 0.001 p.F will insure
stability and still provide acceptable transient response
(see Figure 23). It is also necessary to use an output capacitor, Co, (typically 10 /IF) directly from the output (pin
6) to ground. When an external transistor is used to boost
the current, Co = 100 p.F is recommended (see Figure 28).
NPN CURRENT BOOSTING
For applications requiring more than 500 rnA of load
current, or for minimizing voltage variations due to temperature changes in the Ie regulator arising from changes
of the internal power dissipation, the NPN current-boost
circuits of Figure 2 or 28, are recommended. The circuit
shown in Figure 28 can supply up to approximately 4.0
amperes (subject to safe area limitations). At higher currents the VBE of the pass transistor may itself exceed the
threshold of the current limit even for Rsc = O. Figure 2
illustrates the use of an additional external diode from pin
4 for higher current operation or for pass transistors exhibiting higher VBE's. It will probably be necessary to
determine Rsc experimentally for each case where a pass
transistor is used because VBE varies from device to device.
The circuit of Figure 28 when set up for a -10 V.output

•

5.0
4.5

GND

\
\

4.0

,

3.5

3.0

\

2.5

\.

2.0
/-IF

i'....

1.5

1.0

...........

r-

0.5
2N3771
or Equiv

o

Vo

o

.0.2

0.4

0.6

0.8

1.0

-

1.2

1.4

1.6

Rsc_ Current Limiting Resistor (Ohms)

FIGURE 28 - Typical NPN Current Boost Connection

FIGURE 29 - Isc versus Rsc .(reference Figure 28)

IMC1563 - Pg. 9)

7-273

1.8

2.0

MC1563, MC1463 (continued)

GND

FIGURE 30 - PNP Current
Boost Connection

0.001
IlF

In

~J:'J Vdc ........-R:i's~c':"l--<~::c?::-I,.=-===,....J
MJ450
OR EOUIV
y . - - - - - - - < l ' - V o ""·5.2
Vdc

(RA = 13 kn) supply and operating with a-IS V input,
with a Rsc of 0.1 n, will yield a change in output voltage
of only 26 mV over a load current range of from I rnA
to 3.5 A. This corresponds to a dc output impedance
of only 7.5 milliohms or a percentage load regulation of
0.26% for a full 3 .S-ampere load current change. Figure 29,
indicates how the short circuit current varies with the value
of Rsc for this circuit.

30 this represents a savings of 22 watts when compared
with operating the regulator from the single -9 V supply.
It can supply current to 10 amperes while requiring an
input voltage to the collector of the pass transistor of -6.8
volts minimum. The pass transistor is limited to 10 amperes
by the added short-circuit current network in its emitter
(Rsc2) and the IC regulator is limited to 500 rnA in the
conventional manner (Rscl). The MJ450 exhibits a minimum hFE of 20 at 10 amperes, thus requiring only 500
rnA from the MC1563R. Regulation of this circuit is comparable to that of the NPN boost configuration.
For higher output voltages the additional unregulated
power supply is not required. The collector of the PNP
boost transistor can tie directly to pin 5 and the internal
current limit circuit will provide short-circuit protection
using Rsc (see Figure 12). Transistor Q2 and Rsc2 will
not be required and pin 2 should be returned to ground.

PNP CURRENT BOOSTING
A PNP power transistor can also be used to boost the
load current capabilities. To improve the efficiency of the
PNP boost configuration, particularly for small output
voltages, the circuit of Figure 30, is recommended. An
auxiliary -9 volt supply is used to power the IC regulator
and the heavy load current is obtained from a second supply
of lower voltage. For the 10-ampere regulator of Figure

(10 +",,400 mA max)
Rsc = 1.5

+20 Vdc
2N3055
or Equiv

•

Vo = +15 Vdc

3

VO= +5 V
Q2

9

MC1569R
MC1469R

8

POsitive Regulator

4

5

12 k
Cas.

+VO= I-Vol ""
RA(kSl) +7

2

6.8 k
-::-

-::-

O.lIlF

2

5.fv

~

~

MZ4625
or equiv

Ca..

RA = 22k

4

n

MC1563R
MC1463R
8

7
5

3k

620

9

Negative Regulator

_101lF
Vo = -15 Vdc

6

-20 Vdc
0 0-",,400 mA max)

R. = 1.8

FIGURE 31 - A .:t15 Vdc Complementarv Tracking Regulator With Auxiliarv +5.0 V SupplV

(MC1563 - Pg. 10)

7-274

MC1563, MC1463 (continued)

Pins not shown ara not connected.

Vee f+5 Vdc

0--

FIGURE 32 - Saturated Logic

0--

MOTLt

0--

MTTL

-

10

0--

Level Shutdown Circuit

2

MC1563
MC1463

lN400t ,
ar Equiv

JtGata must be capable of 10
(For MOTL MC930/830 add

>

10 kil from +VCC to output.)

POSITIVE AND NEGATIVE POWER SUPPLIES

470

1k

Output

R(20 kl

i

-=
1 rnA

4

1 rnA

Vi"
(-20 Vdcl

R (in km~ IV;nl

is not short-circuit protected)_ The -IS-volt supply varies
less than 0.1 mV over a zero to -300 mAde current range
and the +15-volt supply tracks this variation. The +15-volt
supply varies 20 mV over the zero to +300-mAdc load
current range. The +5-volt supply varies less than 5 mV
for 0 .;;; IL .;;; 200 rnA with the other two voltages remaining unchanged. See MC1561 data sheet (OS9104 R3), or
MC1569 data sheet (OS9152 R2) for information concerning latch-up when using plus and minus regulations.

If the MC1563 is driven from a floating source it is
possible to use it as a positive regulator by grounding the
negative output terminal. The MCI563 may also be used
with the MC 1569 to provide completely independent
positive and negative power regulators with comparable
performance. When used in this manner a silicon diode
such as the I N400 1 must be connected as a clamp on the
output with the cathode to ground and the anode to the
negative output voltage. This is to prevent the positive
voltage in the system from forcing the output to a positive
value and preventing the MCI563 from starting up.
Some applications may require complementary tracking
in which both supplies arrive at the voltage level simultaneously, and variations in the magnitudes of the two voltages track. Figures 3 and 31 illustrate this approach. In
this application, the MCI563 is used as the reference regulator, establishing the negative output voltage. The MCI569
positive regulator is used in a tracking mode by grounding
one side of the differential amplifier (pin 6 of the MC 1569)
and using the other side (pin 5 of the MC1569) to sense
the voltage developed at the junction of the two 3 k-ohm
resistors. This differential amplifier controls the MCI569
series pass transistor such that the voltage at pin 5 will be
zero. When the voltage at pin 5 equals zero, + IVa I must
equal-IVai·
For the configuration shown in Figure 31, the level
shift amplifier in the MCI569 is employed to generate an
auxiliary +5-volt supply which is boosted to a 2-ampere
capability by QI and Q2. (The +5-volt supply, as shown,

SHUTDOWN TECHNIQUES
Pin 2 of the MC 1563 is provided for the express purpose of shutting the regulator "OFF". Referring to the
schematic, it can be seen that pin 2 goes to the base of a
PNP transistor; which, if turned "ON", will deny current
to all the biasing current sources. This action causes the
output to go to essentially zero volts and the only current
drawn by the IC regulator will be the small start current
through the 60 k-ohm start resistor (Vin!60 ki1). This
feature provides additional versatility in the applications
of the MC1563. Various sub-systems may be placed in a
"standby" mode to conserve power until actually needed.
Or the power may be turned "OFF" in response to other
occurrences such as over-heating, over-voltage, shorted
output, etc.
As an illustration of the first case, consider a system
consisting of both positive-supply logic (MTTL) and
negative-supply logic (MECL). The MECL logic may be
used in a high-speed arithmetic processor whose services
are not continuously required. Substantial power may

CSge/10

FIGURE 33 - MECL Logic

MECL
Gate

Output

2N706
or Equiv

2

MC1563
MC1463

Level Shutdown Circuit
VEE

-5.2 Vdc

Pins not shown are not connected.

(MC1563 - Pg.ll)

7-275

•

MC1563, MC1463 (continued)

0.001
IlF
Vin = -35 V

e-.......-'v";4Ir-+--~--L_____-.J-::>-----'I/'VIr---~>------jrl

.......-----4--~

-100V __----------------_4--~~-

r-----<......... -90 v

FIGURE 34 - Voltage Boosting Circuit

thus be conserved if the MECL circuitry remains unpowered except when needed. The negative regulator can
be shutdown using any of the standard logic swings. For
saturated logic control, Figure 32 shows a circuit that allows
the normal positive output swing to cause the regulator
to shutdown when the logic output is in the low voltage
state. The negative output levels of a MECL gate can also
be used for shutdown control as shown in Figure 33.

A reduced input voltage can be provided by using a separate
supply. The output voltage may be zener-level shifted, and
the sense line can tie to a portion of the output voltage
through a resistive divider. The voltage boost circuit of
Figure 34 uses this approach to provide a -90 volt supply.
This circuit will exhibit regulation of 0.00 1%over a 100 rnA
load current range.

VOLTAGE BOOSTING
Some applications may require a high output voltage
which may exceed the voltage rating of the MC1563. This
must be solved by assuring that the IC regulator is operated
within its limits. Three points in the regulator need to
be considered:

The MC 1563 offers a remote sensing capability. This
is important when the load is remote from the regulator,
as the resistances of the interconnecting lines (VEE and
GND) are added directly to the output impedance of the
regulator. By remote sensing, this resistance is included
inside the control loop of the regulator and is essentially
eliminated. Figure 35 shows how remote sensing is accomplished using both a separate sense line from pin 8 and a
separate ground line from the regulator to the remote load.

REMOTE SENSING

1. The input voltage (pin 4),
2. the output voltage (pin 6) and,
3. the output sense lead (pin 8).

I

,

1-

"
0.1
IlF
2

GN o

6.8 k
3

Case/10

+

1
4
MC1563
MC1463

9

7

0.001 IlF+

8

Vin
A sc

5

6

FIGURE 35 - Remote Sensing Circuit

(MC1563 - Pg. 12)

7-276

RA

-

10llF

RL

MC1563, MC1463 (continued)

GND

~

0.1

IlF
2

RS = 6.8 k
10

3

1

RA= 1 k

-

4
Vin == -10 Vdc

MC1563G
MC1463G

9

Vz= -4 Vdc

I Z = 1 mA (max)

70f-08
f-06

50-

RA
Vz = -3.5 (1 + RS

FIGURE 36 - An Adjustable ··Zero·TC" Voltage Source

AN ADJUSTABLE ZERO-TEMPERATURECOEFFICIENT (O-TC) VOLTAGE REFERENCE
SOURCE

1O-3V/oC). By setting -0.61 Vdc externally, at pin 2, the
regulator will shutdown when the chip temperature reaches
approximately 1400 C. Figure 37 shows a circuit that uses
a zero-TC zener diode and a resistive divider to obtain
this voltage.
In the case where an external pass transistor is employed;
its temperature, rather than that of the IC regulator, requires control. A technique similar to the one just discussed can be used by directly monitoring the case temperature of the pass transistor as is indicated in Figure 38.
The case of the normally "OFF" thermal monitoring
transistor, Q2, should be in thermal contact with, but
electrically isolated from, the case of the boost transistor, QI.

The MC1563, when used in conjunction with low-TC
resistors, makes an excellent reference-voltage generator.
If the -3.5 volt reference voltage of the IC regulator is a
satisfactory value, then pins 1 and 9 can be tied together
and no resistors are needed. This will provide a voltage
reference having a typical temperature coefficient of
0.002%/oC. By adding two resistors, RA and RB, any
voltage between -3.5 Vdc and -37 Vdc can be obtained
with the same low TC (see Figure 36).
THERMAL SHUTDOWN
By setting a fixed voltage at pin 2, the MC1563 chip
can be protected against excessive junction temperatures
caused by power dissipation in the IC regulator. This is
based on the negative temperature coefficient of the
base-emitter junction of the shutdown transistor (-1.9 x

THERMAL CONSIDERATIONS
Monolithic voltage regulators are subjected to internal
heating similar to a power transistor. Since the degree of
internal heating is a function of the specific application,

'" .,,, t,

~

GND

6.8 k

-0.61 Vdc

lN3826 ~t-

12

o r Equiv

3

Case/lO

+

2k

RA

4
5.6 k
5 rnA

1

I

l

1

MC1563
MC1463

9
8

7

O.OOI Il F f

Vdc
Rsc

5

6

FIGURE 37 - Junction Temperature Limiting Shutdown Circuit

(MC1563 - Pg. 13)

7-277

lDIlF

RL

MC1563, MC1463 (continued)

the designer must use caution not to exceed the specified
maximum junction temperature (+l75 0 C). Exceeding this
limit will reduce reliability at an exponential rate. Good
heatsinking not only reduces the junction temperature for
a given power dissipation; it also tends to improve the dc
stability of the output voltage by reducing the junction
temperature change resulting from a change in the PQwer
dissipation of the IC regulator. By using the derating factors
or thermal resistance values given in the Maximum Rati~gs
Table of this data sheet, junction temperature can be com·
puted for any given application in the same manner as for
a power transistor*. A short-circuit on the output terminal
can produce a "worst-case" thermal condition especially
if the maximum input voltage is applied simultaneously
with the maximum value of short-circuit load current
(500 rnA). Care should be taken not to exceed the maximum junction temperature rating during this fault condition and, in addition, the dc safe operating area limit (see
Figure 24).
Thermal characteristics for a voltage regulator are useful
in predicting performance since dc load and line regulation
are affected by changes in junction temperature. These
temperature changes can result from either a change in
the ambient temperature, TA, or a change in the power
dissipated in the IC regulator. The effects of ambient

temperature change on the dc output voltage can be estimated from the "Temperature Coefficient of Output
Voltage" characteristic parameter shown as ±0.002%/oC,
typical. Power dissipation is typically changed in the IC
regulator by varying the dc load current. To estimate the.
dc change in output voltage due to a change in the dc load
current, three effects must be considered:
I. junction temperature change due to the change in
the power dissipation
2. output voltage decrease due to the finite output
impedance of the control amplifier
3. thermal gradient on the IC chip.
A temperature differential does exist across a power IC
chip and can cause a dc shift in the output voltage. A
"gradient coefficient," GCVO, can be used to describe this
effect and is typically +0.03%/watt for the MC1563R. For
an example of the relative magnitudes of these effects,
consider the following conditions:
Given:
with

and

MCI563R

=-10 Vdc
Vo =-S Vdc
IL =100 rnA to 200 rnA

Vin

(AIL = 100 rnA)

*For more detailed information of methods used to compute junction temperature, see Motorola Application
Note AN·226, Measurement of Thermal Properties of
Semiconductors.

assume

T A = +2S o C
TO-66 Type Case with heatsink

r-'-~--------------------------------------~--~~------~~--~~---.---eGND
10 k
10 k

0.1
/IF

220
lN4001
or Equiv

2

3

Case/10

6.8 k

390

4

MC1563
MC1463

5

9

- 100
/IF

8
6

O.OOI/1 F

Vin'---~--~~-4~~

2N3771
or Equiv
~--~--------------------------------~----~--~~-4Vo

L _____ J-Common Heat Sink

FIGURE 38 - Thermal Shutdown When Using External Pa .. Transistors

(MC1563 - Pg. 14)

7-278

MC1563. MC1463 (continued)

assume
and

Ilcs = 0.2 0 C/W
3. 6 Va due to gradient coefficient, GCVO

IlSA = 20 C/W

It. Vol = (GCVO)(VO)(t.PD)
It is desired to find the 6 Va which results from this 61L.

It. vol = (+3 x 1O-4/W)(5 volts)(5 x IO- I W)

Each of the three previously stated effects on Va can now
be separately considered.

It. vol=+0.8mV

1. 6 Va due to 6 TJ

OR

Therefore the total t. Va is given by

6 Va = (Va) (cl'J)(TCVO)(IlJC+IlCS+llsA>
6 Va = (5 V)(5VxO.l A)(±0.002%/oC)(l9.2 0 C/W)

OR

6VO""± 1.0mW
2. 6Voduetoz o

It. Va total I = ± 1.0-2.0 +0.8 mV
-2.2 mV ..;;Ivo totall..;; -0.2 mV

Other operating conditions may be substituted and computed in a similar manner to evaluate the relative effects
of the parameters.

16 Vol =(-zo)(IL)
16 VOl = -(2 x 10- 2)(10- 1) = -2 mV

Typical Printed Circuit Board Layout

2"

(MC1563 - Pg. 15)

7-279

MC1563, MC1463 (continued)

FIGURE 39 - Location of Components

Note I:
When Radj is used it is necessary to remove the copper
which shorts out Radj·
Note 2:
Extra holes are available in the circuit board to permit two
resistors to be paralleled to obtain the desired value of Rsc.
Note 3:
If pin 2 is used to shut down the regulator, remove the
copper which shorts pin 2 to ground.
Note 4:
Remote sensing can be achieved by removing the copper
which shorts pin 8 to pin 6 and connecting pin 8 directly
to the "minus" load terminal. The circuit board ground
should be conneded to the unregulated power supply
ground at the "plus" load terminal.

Typical Circuit Connection for Output Voltages Between -3.5 and -37 Volts
GND

CASE

6.8

k

r----L--.. . . .l-!.-<;f-__

RS

~V'ef

RA +
Q1

4

MC1563R
MC1463R

- 10l'F
VO",-3.5(1 + RA + Radii
RS

9

8

__-~~VV~--~---~-L-______~~6~----~-~--4--.. VO
Select RA

+ Radj to Give Desired VO:

RA

+ Radj ~(21 Vo 1-7) kn with AS ~ 6.8 kSl

PARTS LIST
Componant

Value

RA
Rs

Select
6.8 k
Select

Radj

Description

}

1/4 or 1/2 watt carbon

IRC Model X-201,Mallory Model MTC·l

,

or equivalent

Rsc
R'L
Co

Select
Select
lO,.F

112 watt carbon
For minimum current of 1 mAde

Sprague 1500 Series, Dickson Dl0C series
or equivalent

Cn
Cc
Jl

O.l,.F }
O_OOlI'F

Jumper

01

MC1563R or MC1463R

'HS
'Socket

PC Board

Ceramic Disc - Centralab DOA 104. or equivalent
Sprague TG-Pl0, or equivalent

Heatsink Thermalloy #6168 B or equivalent
(Not 'Shown)

Robinson Nugent #0001306 or equivalent
Electronic Molding Corp. #6341·210-1,
6348-188-1, 6349-188-1 or equivalent
Ci,euit DOT. Inc. #PCll13 or equivalent
1155 W. 23rd St.
Tempe. Arizona 85281

·Optional
(MC1563 - Pg. 161

7-280

MC1566L
MC1466L

\

______M_U_LT_I_-P_U_R_P_O_S_E_R_E_G_U_L_A_T_O_R_S_--,

Specifications and Applications In:forIllation
MONOLITHIC VOLTAGE AND
CURRENT REGULATOR
This unique "floating" regulator can deliver hundreds of volts limited only by the breakdown voltage of the external series pass tran·
sistor. Output voltage and output current are adjustable. The MC1466/
MC 1566 integrated circuit voltage and current regulator is designed to
give "laboratory" power·supply performance.

PRECISION WIDE-RANGE
VOLTAGE and
CURRENT REGULATOR
EPITAXIAL PASSIVATED

• Voltage/Current Regulation with Automatic Crossover
•

Excellent Line Voltage Regulation, 0.01% +1.0 mV

•

Excellent Load Voltage Regulation, 0.01% +1.0 mV

•

Excellent Current Regulation, 0.1% +1.0 mA

","".'0",0,.0.
_•
CASE 632

• Short·Circuit Protection
•

- .

TO·116

• Output Voltage Adjustable to Zero Volts
Internal Reference Voltage

• Adjustable Internal Current Source
TYPICAL APPLICATIONS
FIGURE 1 - O·TO·15 VDC, lO·AMPERES REGULATOR

FIGURE 2 - O·TO·40 VDC, O.5·AMPERE REGULATOR

tlllVdc

lN4IJOl

•.S

OREDmv

50~FJ'

FIGURE 3 - O·TO·250 VDC, O.l·AMPERE REGULATOR

v,

'l

1--

I

FIGURE 4 - REMOTE PROGRAMMING

+Vin

112

IN4C11JI
DREaUiV

1hFr

CR5

2.'

'l

INPUTVp

v,

-1-

r

(MC1566L - Pg. 1)

See Packaging Information Section for outline dimensions.

7-281

(R=~FORVp<20Vdc,R.D)
Pinsl,Z,3,and4noconllllction.

RS

MC1566L, MC1466L (continued)

MAXIMUM RATINGS ITA = +25 0 C unless otherwise noted)
Rating

Symbol

Auxiliary Voltage

Value

Unit
Vdc

Vaux
MC1466
MC1566

30

36

Power Dissipation (Package Limitation)

750
6.0

Po
1/8JA

Derate above T A = +500 C
Operating Temperature Range

TA

mW
mW/oC
C

o to +75

MC1466
MC1566

-55 to +125

Storage Temperature Range

°c

-65 to +150

T stg

ELECTRICAL CHARACTERISTICS ITA = +25 0 C, Vaux = +25 Vdc unless otherwise noted)
Characteristic Definition

,~,

5

It!

D.•

1l

-L

III
2Nmz~

DREQUIV

j,l:.

.,

V.UJ

Characteristic

10pF

'r

6

MCI46SMCI566

ZN305S
OR EOUIV

240pf

)

Vaux

Auxiliary Current

laux

MC1466
MC1566
Internal Reference Voltage
(Voltage from pin 12 to pin 7)

11

l'rI' 'j'

~ ,...
.9'"''

Rl·USt~I'J(,

c~

Symbol

Auxiliarv Voltage (See Notes 1 & 2)
(Voltage from pin 14 to pin 7)
MCI466
MC1566

::k
fJ

l:L

v+

~~

Input Current-Pin 8

18
MC1466
MCI566

Power Dissipation

, ~,ru~

S~OREQUIV

JtT "

te.!l'.

1 .,

MC1466-

MCI56&

V

I

-~

1

•

j'm

j

29.R~212
B.55t.t:1%

~~

II

240 f SI

11

'

~ ~k
11k

Po

UU.I'J!,

:L

Ii

Load Voltage Regulation
(See Note 5)

OREQUIV

Line Voltage Regulation
(See Note 6)

!.Uk

OREQUIV

2HIOSII

OREQUIV

.o.Viov
MC1466
MC1566

)

.o.Viov
MC1466
MC1566

-

30

-

35

-

9.0
7.0

12
8.5

17.3
17.5

18.2
18.2

19.7
19

0.8
0.9

1.0
1.0

1.2
1.1

-

6.0
3.0

12
6.0

-

-

360
300

0
3.0

15
15

40
25

-

1.0
0.7

3.0
1.0

mV

0.015
0.004

0.03
0.01

%

1.0
0.7

3.0
1.0

mV

0.015
0.004

0.03
0.01

%

Temperature Coefficient of Output Voltage
(T A = 0 to +750 C)
MC1466
(TA = -65 to +250 C)
MC1566
0
(TA = +25 to +125 C)
MC1566

TCV o

-

-

0.01
0.006
0.004

-

Input Offset Voltage, Current Control
Amplifier (S.. Note 4)
MC1466
(Voltage from pin 10 to pin 11) MC1566

Vioi

0
3.0

15
15

40
25

-

-

Units
Vdc

mAdc

Vdc

mAdc

!lAdc

mW

mVdc

-

-

-

MC1466 .o.VrefIVref
MC1566

v~-!

""n~

~.
s·
nopE

Viov

MC1466 .o.VrefIVref
MC1566

b

IOpF

Me'."

Input Offset Voltage, Voltage Control
Amplifier (See Note 4)
MC1466
MC1566

2N3055

c
1:,L
1.1I:Fl'
...60

R2

~ru

III

21
20

-

MCI466
MC1566

.

Max

I ref
MC1466
MC1566

-=-50

Typ

VIR
MC1466
MC1566

Reference Current (See Note 3)

1.0P

Min

%/oC

mVdc

MCI568

'~,'Y
'Iref
RZ

-=UkSl"

I

~-~t:~
11

'9.'1!i?"
I.SSk*I" lit

..

u,"

.

Load Current Regulation
(See Note 7)

'*"~i v,"-!L.;;~ C.1.0~~

Pins 1 and 4 no connectIon.

.o.IL/IL
MC1466
MC1566
MC1466
MC1566

(MC1666L - Pg. 2)

7-282

.0.1 ref

-

-

-

0.2
0.1

%

1.0
1.0

mAdc

MC1566L, MC1466L (continued)

NOTE 1:
The instantaneous input voltage, Vaux • must not exceed
the maximum value 01 30 volts lor the MC1466 or 35
volts for the MC1566. The instantaneous value of Vaux
must be greater than 20 volts lor the MC1566 or 21
volts for the MC1466 for proper internal regulation.
NOTE 2:
The auxiliary supply voltage Vaux • must "float" and be
electrically isolated from the unregulated high voltage
supply. Vin.
NOTE 3:

Load Voltage Regulation
CiVrel (100%)
Vrel

=

+ CiViov •

NOTE 6:
Line Voltage Regulation is a function of the same two
additive components as Load Voltage Regulation, AViov
and aVref (see note 5). The measurement procedure is:
a. Set the auxiliary voltage, V aux , to 22 volts for
the MC1566 or the MC1466. Read the value of
Viov (1) and Vref (1)'
b. Change the Vaux to 28 volts for the MC1566 or
the MC1466 and note the value of Vlov (2) and
Vref(2)' Then compute Line Voltage Regulation:

Reference current may be set to any value of current
less than 1.2 mAde by applying the relationship:
Irel (rnA) = B.55
Rl (kll)
NOTE 4:
A built-in offset voltage (15 mVdc nominal) is provided
so that the power supply output voltage or current may
be adjusted to zero.
NOTE 5:
Load Voltage Regulation is a function of two additive
components, aViov and tlVref. where .1Viov is the
change in input offset voltage (measured between pins 8
and 9) and .6.V re f is the change in voltage across R2
(measured between pinS and ground). Each component
may be measured separately or the sum may be
measured across the load. The measurement procedure
for the test circu it shown is:
a. With S 1 open (14 = 0) measure the value of Viov (1)
and Vre! (1)
b. Close S I. adjust R4 so that 14 = 500 I'A and note
Viov (2) and Vre! (2).
Then t.viov = Viov (1) - Viov (2)
% Reference Regulation =

CiViov = CiViov (1) - Viov (2)
% Reference Regulation =
[Vrel (1) - Vrel (2)1 (100%)= CiVrel (100%)
Vrel(1)
Vre!
Line Voltage Regulation =
CiV re !
- - (100%) + Ci.Yiov •
Vrel
NOTE 7:
Load Current Regulation is measured by the following
procedure:
.
a. With 52 open, adjust R3 for an initial load current,
IU1). such that Va is B.O Vdc.
b. With S2 closed. adjust RT lor Vo = 1.0 Vdc and read
I L(2). Then Load Current Regulation =

[IL(2) -IL(1)1 (100%) + I
rei
IL(1)
where Iref is 1.0 mAde, Load Current Regulation is
specified in this manner because Iref passes through
the load in a direction opposite that of load current
and does not pass through the current sense resistor, Rs_

[V r.! 111 - Vr.! 1211 (100%) = CiVrel (100%)
vrel (1)
,
Vrel
FIGURES

tVlUlI'C"i-------l

OUTPUT

10
CURRENT
SENSE'NPUT

CIRCUIT SCHEMATIC :

I

19.Bk

u.

4.3k

'"

'6k

CR2

15'
CR!
7.25 V
,~.

IITfRIIAL
VOLTAIE
REGULATOR

REFERENCE
CURRENT
SOURCE

VOLTAGE
COITROL
AMPliFIER

(MC1566L - Pg. 3)

7-283

CURRENT
CONTROL
AMPLIFIER

OR

OUTPUT
AMPLIFIER

MC1566L, MC1466L (continued)

FIGURE 6 - TYPICAL CIRCUIT CONNECTION

CRG

Q,

Vin

"
l.B

MC1466
MC1566

240pF
11

10

"'

92
R1

CR5

SOD

12

",

18k

PhllI arll4no CDnneclion.

Cor

Hl

.

,'lVo

1-

NORMAL DESIGN PROCEDURE AND DESIGN CONSIDERATIONS
6. The RC network (10 pF, 240 pF, 1.2 k ohms) is used for

1. Constant Voltage:

compensation. The values shown are valid for all applications.

For constant voltage operation, output voltage Va is given by:

However, the 10 pF capacitor may be omitted if fT of al and
a2 is greater than 0.5 MHz.

Va ~ (tref) (R2)
where R2 is the resistance from pin 8 to ground and 'ref is the
output current of pin 3.

7. For remote sense applications, the positive voltage sense termi~
nal (pin 9) is connected to the positive load terminal through a
separate sense lead; and the negative sense terminal (the ground
side of R2) is connected to the negative load terminal through
a separate sense lead.

The recommended value of Iref is 1.0 mAde. Resistor R 1 sets
the value of Iref:
Iref

~ 8.5

R,

a.

where R 1 is the resistance between pins 2 and 12.
2. Constant Current:
For constant current operation:

Co may be selected by using the relationship:
Co ~ (100 "F) IUmax), where I L(max) is the maximum load

current in amperes.
9. C2 is necessary for the internal compensation of the MC1466/
MC1566.

(a) Select Rs for a 250 mV drop at the maximum desired regu-

lated output current, I max'
(bl Adjust potentiometer R3 to set constant current output at
desired value between zero and I max'

10.

:~:e~d~~U:A~~~~~~~~~~~~~~~o~~ ~~:~25;u~l; tS~~~ld
PI p2 .;;; 0.5 mAde

where: I max

conditions.

PI

4. In applications where very low output noise is desired, R2 may

= maximum short-circuit
~

load current (mAdcl

minimum beta of al

f32 = minimum beta of Q2

be bypassed with Cl (0.1 "F to 2.0 "F). When R2 is bypassed.

CR1 is necessary for protection during short-circuit conditions.

Although Pin 5 will source up to 1.5 mAde, 15

will result in a degr.adation in regulation.

5. CR5 is recommended to protect the MC1466/MC1566 from

simultaneous pass transistor failure and output short-circuit.

not

Imax

3. If Vin is greater than 20 Vdc, CR2, CR3, and CR'4 are necessary
to protect the MC1466/MC1566during short·circuit or transient

> 0.5 mAde

11. CR6 is recommended when Va..> 150 Vdc and should be rated
such that Peak Inverse Voltage? Va.

(MC1566L - Pg. 4)

7-284

MC1566L, MC1466L (continued)

OPERATION AND APPLICATIONS
This section describes the operation and design of the MC1566/MC1466 voltage and current regulator and also provides
information on useful applications.

SUBJECT SEQUENCE

Theory of Operation
Applications
Transient Failures
Voltage/Current-Mode Indicator

THEORY OF OPERATION

yields a good working PNP from a lateral device working
at a collector current of only a few microamperes. Its base
voltage (V B2) is derived from a temperature compensated
portion of the diode string and consequently the overall
current is dependent on the value of emitter resistor RI.
Temperature compensation of the base emitter junction
of Q3 is not important because approximately 9 volts
exists between VB2 and V12, making the ~VBE's very
small in percentage. Circuit reference voltage is derived
from the product of IR and RR; if IR is set at I mA
(RI = 8.5 kn), then RR (in kn) =Yo. Other values of
current may be used as long as the following restraints are
kept in mind: I) package dissipation will be increased by
about 11 mW/mA and 2) bias current for the voltage control
amplifier is 3 /lA, t~mperature dependent, and is extracted
from the reference current. The reference current should

The schematic of Figure 5 can be simplified by breaking it down into basic functions, beginning with a simplified
version of the voltage reference, Figure 7. Zener diodes
CRI and CR'S'with their associated forward biased diodes
CR2 through CR4 and CR6 through CR8 form the stable
reference needed to balance the differential amplifier. At
balance (VBI = VB2), the output voltage, (V12 - V7),
is at a value that is twice the drop across either of the two
diode strings: V12 - V7 = 2 (VCRI + VCR2 + VCR3 +
VCR4). Other voltages, temperature compensated or otherwise, are also derived from these diodes strings for use in
other parts of the circuit.
The voltage controlled current source (Figure 8) is a
PNP-NPN composite which, due to the high NPN beta,
FIGURE 7 - REFERENCE VOLTAGE REGULATOR

12
14

Equivalent

FIGURE 8 - VOLTAGE CONTROLLED CURRENT SOURCE

T
1

Diode VZ:::::::9 V

J

Regulated

Vaux

Voltage
IBV

VBI

Equivalent

Diode

VZ""9V

7

R1

12

T

VZ""9 V

~)..4..-------1

(MC1566L - Pg. 51

7-285

2

03

IIR~ VZ-VBE""B.55
,

R1

R1

MC1566L, MC1466L(continued)

be at least two orders of magnitude above the largest expected bias current.
Loop amplification in the constant voltage mode is
supplied by the voltage controlled amplifier (Figure 9), a
standard high-gain differential amplifier. The inputs are
diode-protected against differential overvoltages and an
emitter degenerating resistor, Ros, has been added to one
of the transistors. For an emitter current in both QS and
Q6 of 1/2 milliampere there will exist a preset offset voltage in this differential amplifier of 15 mV to insure that
the output voltage will be zero when the reference voltage
is zero. Without ROS, the output voltage could be a few
millivolts above zero due to the inherent offset. Since the
load resistor is so large in this stage compared with the
load (Q9) it will be more instructive to look at the gain on
a transconductance basis rather than voltage gain. Transconductance of the differential stage is defined for small
signals as:
(1)
where
0.026
re""-- and
IE
RE = added emitter degenerating resistance.
For IE =0.5 rnA,

1

gm = 104 + 30

1

(2)

=134 =7.S rnA/volt.

FIGURE 9 - VOLTAGE CONTROL AMPLIFIER
12

6

Preregulated

18V

FIGURE 10 - CURRENT CONTROL CIRCUIT
12

6
o-~----~-----------

S

10

V2

Vo
9

This level is further boosted by the output stage such that
in the constant voltage mode overall transconductance is
about 300 rnA/volt.
A second differential stage nearly identical to the first
stage, serves as the current control amplifier (Figure 10).
The gain of this stage insures a rapid crossover from the
constant voltage to constant current modes and provides
a convenient point to control the maximum deliverable
load current. In use, a reference voltage derived from the
pre regulator and a voltage divider is applied to pin 10
while the output current is sampled across RS by pin 11.
When IL RS is IS mV below the reference value, voltage
VI begins to rapidly rise, eventually gaining complete
control of Q9 and limiting output current to a value of
V2/RS. If V2 is derived from a variable source, short
circuit current may be controlIed over the complete output current capability of the regulator. Since the constantvoltage to constant-current change-over requires only a few
millivolts the voltage regulation maintains its quality to
the current limit and accordingly shows a very sharp
"knee" (1% +1 rnA, Figure 11). Note that the regulator
can switch back into the constant voltage mode if the
output voltage reaches a value greater than YR. Operation
through zero milliamperes is guaranteed by the inclusion
of another emitter offsetting resistor.
FIGURE 11 - VI CURVE FOR O-TO·40 V,
0.5-AMPERE REGULATOR

;;;
I-

40

.J

7

0

~ 30

w

t!l

SOD

B
Reference Voltage

«

I-

SOD

20

.J

o·
>

10

;;

+7.2SV 9
+ Output Sense

0.1

VR

0.2

0.3

0.4

O.S

I, CURRENT IAMPERES)

IMC1S66L - Pg. 6)

7-286

MC1566L, MC1466L (continued)

Transistor Q9 and five diodes comprise the essential
parts of the output stage (Figure 12). The diodes perform
an "OR" function which allows only one mode of operation
at a time - constant current or constant voltage. However,
an additional stage (Q9) must be included to invert the
logic and make it compatible with the driving requirements
of series pass transistors as well as provide additional gain.
A 1.5 rnA collector current source sets the maximum deliverable output current and boosts the output impedance
to that of the current source.
Note that the negative (substrate) side of the MC1566/
MC 1466 is 7.25 volts lower than the output voltage, and
the reference regulator guarantees that the positive side is
11 volts above the output. Thus the IC remains at a voltage
(relative to ground) solely dependent on the output, "floating" above and below Vo. VCE across Q9 is only two or
three VBE's depending on the number of transistors used
in the series pass configuration.
Performance characteristics of the regulator may be
approximately calculated for a given circuit (Figure 2).
Assuming that the two added transistors (Q12 and Q13)
have minimum beta's of 20, then the overall regulator
transconductance will be:
gmT = (400) 300 rnA/volt = 120 A/volt.

(3)

For a change in current of 500 rnA the output voltage
will drop only:
0.5
/:'V=-=4.2mV.
120

(4)

FIGURE 12 - MC1566 OUTPUT STAGE

.....- - - - - - prer~~u~tad--------<~
1
From CUrrent
Control Amplifier

C:~~';I ~~:I~:ier

The analysis thus far does not consider changes in VR
due to output current changes. If IL increases by 500 rnA
the collector current of Q9 decreases by 1.25 rnA, causing
the collector current of Q5 to increase by 30 p.A. Accordingly, I R will be decreased by ""0.30 p.A which will drop
the output by 0.03%. This figure may be improved considerably by either using high beta devices as the pass
transistors, or by increasing IR. Note again, however, that
the maximum power rating of the package must be kept
in mind. For example if IR = 4 rnA, power dissipation is
PD = 20 V (8 rnA) + (11 V x 3 rnA) = 193 mW. (5)
This indicates that the circuit may be safely operated up
to 1180 C using 20 volts at the auxiliary supply voltage.
If, however, the aUxiliary supply voltage is 35 volts,
PD = 35 V (8 rnA) + 26 V (3 rnA) = 358 mW.

(6)

which dictates that the maximum operating temperature
must be less than 91 °C to keep package dissipation within
specified limits.
Line voltage regulation is also a function of the voltage
change between pins 8 and 9, and the change of Vref. In
this case, however, these voltages change due to changes in
the internal regulator'S voltages, which in turn are caused
by changes in Vaux . Note that line voltage regulation is
not a function of Vin. Note also that the instantaneous
value of Vaux must always be between 20 and 35 volts.
Figure 6 shows six external diodes (CRI to CR6) added
for protective purposes. CRI should be used if the output
voltage is less than 20 volts and CR2, CR3 are absent. For
Vo higher than 20 volts, CR 1 should be discarded in favor
of CR2 and CR3. Diode CR4 prevents IC failure if the
series pass transistors develop collector-base shorts while
the main power transistor suffers a simultaneous open emitter. If the possibility of such a transistor failure mode
seems remote, CR4 may be deleted. To prevent instantaneous differential and common-mode breakdown of the
current sense amplifier, CR5 must be placed across the
current limit resistor Rs.
Load transients occasionally produce a damaging reversal
of current flow from output to input Vo > 150 volts (which
will destroy the IC). Diode CR6 prevents such reversal
and renders the circuit immune from destruction for such
conditions, e.g., adding a large output capacitor after the
supply is turned "on". Diodes CRl, CR2, CR3, and CR5
may be general purpose silicon units such as IN4001 or
equivalent whereas CR4 and CR6 should have a peak inverse
voltage rating equal to Yin or greater.

APPLICATIONS
Figure 2 shows a typical 0-to-40 volts, 0.5-ampere regulator with better than 0.01 % performance, The RC network between pins 5 and 6 and the capacitor between pins
13 and 14 provide frequency compensation for the MC1566/
MC1466. The external pass transistors are used to boost
load current, since the output current of the regulator is
less than 2 rnA.

(MC1566L - Pg. 7)

7-287

MC1566L, MC1466L (continued)

Figure I is a 0-to-15 volts, IO-ampere regulator with the
pass transistor configuration necessary to boost the load
current to 10 amperes_ Note that Co has been increased to
1000 /-IF following the general rule:

tible with a short-circuit current of 100 rnA. Yet current
foldback allows us to design for a maximum regulated load
current of 500 rnA. The pertinent design equations are:
Let R2 (kU) =Vo

Co =100 /-IF/A IL.

a =0.25
Vo

The prime advantage of the MC1566/MC1466 is its use
as a high voltage regulator, as shown in Figure 3. This
0-to-250 volts O.l-ampere regulator is typical of high voltage applications, limited only by the breakdown and safe
areas of the output pass transistors.

[.!!L
- I]
ISC
a

Rl(kU)=I_a Vo

Rs

The primary limiting factor in high voltage series regulators is the pass transistor. Figure 13 shows a safe area curve
for the MJ 413. Looking at Figure 3, we see that if the
output is shorted, the transistor will have a collector current of 100 rnA, with a VCE approximately equal to 260
volts. Thus this point falls on the dc line of the safe area
curve, insuring that the transistor will not enter secondary
breakdown.

0.25
C =(l - a) ISC

FIGURE 13 - SAFE AREA CURVE FOR THE MJ413

iii
w

~ 10~~~~~~1I~~~~1!~~~~~~~
,

..,

1001's

~
~

Z

~~

TJ
1.0

o

In this respect (Safe Operating Area) the foldback circuit
of Figure 14 is superior for handling high voltages and yet
is short-circuit protected. This is due to the fact that load
current is diminished as output voltage drops (VCE increases
as V 0 drops) as seen in Figure 15. By careful design the
load current at a short, ISC can be made low enough such
that the combined VCE (Vin) and ISC still falls within the
dc safe operating area of the transistor. For the illustrated
design (Figure" 14), an input voltage of 210 volts is compa-

tJ

150°C

'\r... 1.0 ms

de

~~III~~'~~III

PERCEPTIBLE ABOVE Ie = 5 A. J

~

W
-l
.J

=

---J~~~I~~~~T~~~~~::IJN;S
SECONDARY BREAKDOWN LIMITATION
25°C

cat:r~::!: ,~~f,~a::\~~~c~~:~~~; ++t+ttl+--'\~-H+t-H+t

will not enter secondary breakdown. Col·

O.1~
leclorwithin
load lines
lor specilic Safe
circuilsmusl
E fall
the applicable
Area to ~~~II~~~~III

o
o

E

a'loid causing a catastrophic failure. To
insure operation below the maximum TJ.
power·!emperature derating must be

~~~:;~~~~~i~~~h steady state and pulse

++t+t+I+---t-++t+1+H

0.01 '::--::'-::-'-:-'=-,=,=",~_=-'--:::"'::'::~=-:::=--'-::=,""'--'-::~
1.0 2.0 4.06.0 10
20
4060 100 200 400
1000
VCE. COLLECTOR-EMITTER VOLTAGE (VOLTS)

FIGURE 14 - A 200 V. O.5-AMPERE REGULATOR WITH CURRENT FOLDBACK

lN4005
OR EaUIV

MJ421
OR EaUIV

T''''

+ 14

5

13

6

1.2 k

MC1466
MC1566

25 V

I

,..,":>.---......-+1...... VI" = 210 V

1)-----0---1-

240 pF

15 k

11

1k

10

7

8

RSC 2.5 nl1w
18 k
500

lN4001
OR EaUIV

+-~r-~--------------------------~----------------i---~

+
Vo= 200 V

+

200 k

RL

-=

(MC1566L - Pg. 8)

7-288

1

MC1566L, MC1466L (continued)

from hundreds to thousands of volts in magnitude and only
microseconds in duration. Under some conditions this energy is dissipated across the internal zener connected between pins 9 and 7. This transient condition may produce
a total failure of the regulator device without any apparent
explanation. This type of failure is identified by absence
of the 7-volt zener (CRI) between pin 9 and pin 7. To prevent this failure mode, two solutions have been successfully
applied. The first method involves the use of an external
zener and resistor that shunt more of the transient energy
around the IC (Figure 17). The second method is a transient suppression network consisting of capacitors that
equalize high frequency components across both the auxil·
iary and main supply. Figure 18 illustrates the use of five
capacitors for the full wave rectified main supply and
Figure 19 uses six capacitors when a full wave bridge is used.

The terms ISC and Ik correspond to the short-circuit
current and maximum available load current as shown in
Figure 15.
FIGURE 15 - TYPICAL FOLDBACK PERFORMANCE
250

U

"0
~

200

/

w

Cl

~
o-'

150

j

100

>

1=
:::l

0" 50

>

o

o

V

/

ISC

V

/

V

/

/

200

VOLTAGE/CURRENT - MODE INDICATOR

800

600

There may be times when it is desirable to know when
the MC1566/MC1466 is in the constant current mode or
constant voltage mode. A mode indicator can be easily
added to provide this feature. Figure 20 shows how a PNP
transistor has replaced a protection doide between pins 8
and 9 of Figure 2. When the MC1566/MC1466 goes from
constant voltage mode to constant current mode, Vo will
drop below V8 and the PNP transistor will turn on. The
I-rnA current supplied by pin 8 will now be shunted to
ground through R1 in parallel with R2, which provides a
control voltage, VC. This voltage Vc can then control a
Schmitt trigger which drives front panel lamps to indicate
"constant current" or "constant voltage."

10 , OUTPUT CURRENT (mAde)

Figure 16 shows a remote sense application which should
be used when high current or long wire lengths are used.
This type of wiring is recommended for any application
where the best possible regulation is desired. Since the
sense lines draw only a small current, large voltage drops
<10 not destroy the excellent regulation of the MC1566/
MC1466.

TRANSIENT FAILURES
In industrial areas where electrical machinery is used
the normal ac line often contains bursts of voltage running

F(GURE 16 - REMOTE SENSE
MJE340
OR EQUIV

T. "
1

+ 14

5

13

6

MJ413
OR EQUIV

1.2 k

240pF

MCl466
MC1566

25V

-

11

7

10
RS

8
18 k

8.55 k

+

All diodes are

lN40010r
equivalent.

500

+

Rref

Note: All Ground Connections at Load Site.

(MC1566L - Pg. 9)

7-289

MC1566L, MC1466L (continued)

FIGURE 17 - A ()..TO-250 VOLT, O.l-AMPERE REGULATOR
MJE340 OR EaUIV

r,--:;>___- -.....If-O
+

14

MJ413 OR EaUIV

1.2 k

fo.1l'F

6

MC1466
MC1566

25 V

1

Yin = 260 V

5

100 _

240pF

15k

1 k

11

10

7

8

Vz~

2.5

1Itk

8.55 k

8 V

500

+
Vo

All diodes are
250 k

lN40010r

+

Va Adjust

""I

equ;valent~

FIGURE 18 - HALF-WAVE RECTIFIER
WITH TRANSIENT SUPPRESSION

C

= 0.331'F

14

J

C

C

-=

Vaux

C

J
J

MAIN
SUPPLY

C

C

FIGURE 20 - O-TO-40 Vdc, 0.5-AMPERE REGULATOR WITH MODE .INDICATOR
MPS6565
14

r
25 Vdc
I

0.1
I'F
13

1

FIGURE 19 - FULL·WAVE RECTIFICATION
WITH TRANSIENT SUPPRESSION
MAIN
SUPPLY

r-

RL

5

+50 Vdc

MC1466
MC1566

7
0.5

VC. (CONTROL VOL TAGE TO SCHMITT TRIGGER)

·Select 01 such that VCEO

(MC1566L - Pg. 10)

7-290

> Va'

"\

MC1568
MC1468

DUAL VOLTAGE REGULATORS

'--------------'

DUAL±15-VOLT
TRACKING REGULATOR

DUAL±15-VOLT REGULATOR
The MC1568/MC1468 is a dual polarity tracking regulator designed
to provide balanced positive and negative output voltages at currents
to 100 mAo Internally. the device is set for ±15-volt outputs but a
single external adjustment can be used to change both outputs simultaneously from 14.5 to 20 volts. Input voltages up to ±30 volts can
be used and there is provision for adjustable current limiting. The
device is available in three package types to accomodate various power
requirements.

MONOLITHIC SILICON
INTEGRATED CIRCUIT

~o
•

~~

Internally set to±15 V Tracking Outputs

• Output Currents to 100 mA
• Outputs Balanced to within 1% (MC1568)

~
$..

0- ~:-0

(bottom view)

9

• Line and Load Regulation of 0.06%
• 1% Maximum Output Variation due to Temperature Changes
• Standby Current Drain of 3.0 mA

CASE 603·3
METAL PACKAGE
G SUFFIX

CASE 614
METAL PACKAGE
R SUFFIX

• Externally Adjustable Current Limit
• Remote Sensing Provisions
• Case is at Ground Potential (R suffix package)
CASE 632
CERAMIC PACKAGE

TO·116
L SUFFIX

14
Vee
~1I

"I

,--------------<>Vo·
--=~__+_+==::;:__;:;;:::;_----t-:f
SENSE(+)
r
2(4)

COMPEN(+)

(2IBALANCE

.J----±;--o ADJUST

H31

fLplckag.on1vl

1(111
SENSE H
61101

,.....IVV-~

t----..-o Vo-

5(8)

GNO

1011)

VOLTAGE
ADJUST
9(14)

Pin numben adjacent to 1erminalsare lor lhe G
and R sullix packages only. PinnumlieninparentheseJll, for Ihe Lsulfix packaglonly. Pin 10

COMPENH
81121

isgroundfortheGsuflilpackageanly. Forthe
R package,lhtCISI is ground,

See Packaging Information Section for outline dimensions.

7-291

1

(top view)

I

MC1568, MC1468 (continued)

MAXIMUM RATINGS (TC = +25 a C unless otherwise noted.)
Symbol

Rating

Input Voltage

Value

Unit
Vdc

VeC,lVEEI
30

Peak Load Current
TA = +25 a C
Derate above T A

Thermal Resistance, Junction to Air

TC = +25 0 C
Derate above T C

G Package

R Package

L Package

0.8
5.4
185
2 ..1
14
70

2.4
16
62
9.0
61
17

1.0
6.7
150
2.5
20
50

Po
I/BJA
BJA
Po

= +25 a C
= +25 0 C

llBJC
BJC

Thermal Resistance. Junction to Case

Watts
mW/oC
°C/W
Watts
mW/oC
°C/W

TJ,Tstg

-65 to +175

aC

Rsc(min)

4.0

Ohms

Storage Junction Temperaturl;' Range
Minimum Short-Circuit Resistance

mA

100

IpK

Power Dissipation and Thermal Characteristics

OPERATING TEMPERATURE RANGE
Ambient Temperature

o

to +75
-55 to +125

MC1468
MC1568

ELECTRICAL CHARACTERISTICS IVcc = +20 V, VEE = -20 V, el = C2 = 1500 pF, C3 = C4 = 1.0 IlF, RSC+ = RSC- = 4.0
IL +

= IL- = 0

TC

= +25 0 C unless otherwise noted)
.':
," MC1568 :.. .'

Symbol'

Characteristic
Output Voltage

Vo

I nput Voltage

Min:
:1,t8

Output Voltage Balance

VBal

';.""':;.

Line Regulation Voltage
(Vin = 18 V to 30 V)

Regin

)

i2l

I

Output Voltage Range (See Figures 2 and 12)

VOR

Ripple Rejection If

RR
~tability

ISC

Output Noise Voltage
(BW= 100Hz.' 10kHz)

VN

Positive Standby Current

IB

+

= +30 V)
IB -

Negative Standby Current
(Vin = -30 V)

Tlow = DoC for MC1468
= -55 a e for MC 1568

15

15.5

'Vdc

..Voht

®

-

-

30

Vdc

2.0

-

-

Vdc

,:±150

-

±50

±300

mV

"

-

-

10
20

-

-

-

-

10
30

14.5

-

20

Vdc

-

75

-

dB

-

0.3

1,0

-

60

-

-

100

-

-

2.4

4.0

-

1.0

3.0

-

0.2

-

30 '
',-

10
20

:-

;1' -

10
,30

20,
::,.. ,:
" ':!:' 1':ZEi> :"§,,,:,;.
::,1:4.5

"

,f.:

O;~.,
'

"

-

,~~~:i)
,

60

i,' .'':,;'

100
,

-',

"''"' t+.

Thigh = +75 0 C for MC1468
= +125 a C for MC1568

7-292

...

O,~:,

mV

mV

%
mA
IlV(RMS)

"

!:,:~;\~',
I,,·
~.,
." .2.4 :.::).0
.... '.':
I..... ~
3,0
1.0

Ii

Long·Term Stability



mA
mA
%/k Hr

·Symbols conform to JEDEC Engineering

Bulletin No.1 when applicable.

MC1568, MC1468 (continued)

TYPICAL APPLICATIONS

FIGURE 2 - VOLTAGE ADJUST AND
BALANCE ADJUST CIRCUIT

FIGURE 1 - BASIC 50-mA REGULATOR
INP UT (+)

4(7)

5 (8)
VCC

VEE

Vo+

Vo-

3 (5)

417)
RSC+ 315)

6(10)

518)
VCC

VEE

VO+

VO-

214)

RSC+

SENSE
(+)

RSC2 (4)

SENSE
SENSE
(+) GNO H

CaMPEN (-) 1
(3)
Cl
1500 pF

10

8
(12)

(I)

'----< ~

l.d~F
C3

9(14)

100
k

7(11)

COMPEN(+)

CaMPEN (+)

6!).,O) RSC7(11)
12)

Baladj

100
k

10

COMPEN H

1(3)
8(1;i (1)
, 1500 pF
1500 pF 1
>---

C2
1500 pF

'----<

C4

Cl and C2 should be located as close
to the device as possible. A 0.1 ~F ceramic
capacitor may be required on the input lines
if the device is located an appreciable distance from the rectifier filter capacitors.

INPUT I -)

GNO

1.0~F

-

SENSE
H

Vadj

+IL

+"
+Vo
+15 Vdc

NPUT 1+)

INPUT H

+

+1/
C4 I~.O~F

"

-Va
-15 Vdc

C3 1.0 ~F

C3 and C4 may be increased to improve load ,transient response and to
reduce the output noise voltage. At
low temperature operation, it may be
necessary to bypass C4 with a 0.' J.LF
ceramic disc capacitor.

-=

+Vo
+15 Vdc

Balance adiust available in Me IS6el, Me 1468L ceramic
dual in-line package only.

FIGURE 3-±1.5·AMPERE REGULATOR
(Short·Circuit Protected, with Proper Heatsinkingl.
INPUT 1+)
(+20 V to +30 V)

MJ2955
DR EIlUIV

+VO

x--f-.JVVIr-1'-------.....---e+15 Vdc
0.33il
2.0W

47

VCC
ISC = 0.6 V
RSC

VO+
MC1568R
MC1468R

SENSE 1+)
COMPEN I+)I---<~-lf--,
1500 pF
GNO~~--~~~~~

CASE
COMPEN I-l ~:r--t
Vo- SENSE 1-)
8 1500 pF

r---'
+

lO~F

47
)L--4~Mr_--------~-.

INPUT (-I
1-20 V to -30 V)

2N3055
DR EIlUIV

0.33il
2.0W

7-293

-VO

-15 Vdc

-Va
-15 Vdc

MC1568, MC1468 (continued)

TYPICAL CHARACTERISTICS
(Vee = +20 V, VEE = -20 V, Vo = ± 15 V, TA = +25 0 C unless otherwise noted.)

FIGURE 4 - LOAD REGULATION

FIGURE 5 - REGULATOR DROPOUT VOLTAGE
4,0

w
to

~

~

0~~+=::t;;1
1-

~ 1.0 t---t--"""1I'<::::....;JI::---t--'=f=-t---t=-t--t--I

~

a:;

2.0

1--1--1r--1r-~--=-~""",,-+--I-=:-+=--+=c:1

..

~ 3.0 f--f---Ic---I:--+--+--=~--=--f~...!:--+--l

to

!:; 4.01--f--1--1L----+r--+--I--~_"'j.-==-_+-=""i

'">

~ en 3.0
... >>--'
::>0
0>

~~i=
Z

i~

~ 5.0

2.0

~

::>'"

:!~

~

:Eo 1.0

RSC = 4.0 OHMS + - - t - - t - - f - - t - TJ =TA

0

6.01--f--1--1--+--+--+--+--+-_+--j

~
c
;>

O~MS

RScl= 4.0
llVO I" 100

POSITIVE

Zu-

~

5

)--

'">

REGULATO~,

~
~
~h

-

0

FIGURE 6 - MAXIMUM CURRENT CAPABILITY

.!

I

>-

~
'"~

..'"
~
-'

;0

'\

G PACKAGE""
.120

'\

~

20

BO

-

-' 40

a
-55

R PACKAGE-

\
I.----

>Z

\i

a'"'"

\

+50

+25

,

l.i

~\
~

MC156B)
+75

+100

\
\

«

.5 160
W

..

•

'"

90

.5 BO

+125

::>
'"'" a

'\..

u

'"
,.:.
g;
~

~

a

r--.. ........

t---...

0
0

4.0

' .....

R PACKAGE--

I'-...

--

:-- 1""-_

2,0

4.0

6.0

B.O

10

12

14

16

FIGURE 9 - CURRENT·LIMITING CHARACTERISTICS

-

a

30

0

r-- ......

'\. i'-.

- - - NO HEATSINK .......... 1'-... ........ .............
- - - - INFINITE HEATSINK
........

a

>:; 50
U

'-...

G PACKAGE-

BO

........

100

'\

u

lOa

i Vin' Vo I. INPUT·OUTPUT VOLTAGE DIFFERENTIAL IV)

'\

~ 70

~

\ \

r--,. ........

a

.\
_\

>-

\

_ VCC=(EEI

,

FIGURE 8 - ISC versus RSC

«

BO

_LPACKAGE~

~

o

~
-'
>o
>-

\

120

TA, AMBIENT TEMPERATURE 1°C)

100

60

40

:: 4a

,

IMCI46B)r--

-25

,

\

~ ~

L PACKAGE"'"

'">-

200

....\ !

:'\

" -"

- - - - NO HEATSINK
- - INFINITE HEATSINK

~~

FIGURE 7 - MAXIMUM CURRENT CAPABILITY

\

'\

"

VCC = IVEE I

~~

IL lOAD CURRENT ImA)

200

«

-

-

"NEGATIVE REGULATOR

IL, LOAD CURRENT (rnA)

.5 16 a I---Vin' Vo = 3.0V

~

~

I.----

a

7.00~-'----:!20;;---'--!;40;----'-""6;!,0:---L-...,;!,:--.....L-~
100

r

B.O

12

16

-20

24

a

-

-

~SC=100HMS

t--- r--

RSC - 20 OHMS

a
2B

a

32

-75

-50

-25

+25

+50

+75

TJ. JUNCTION TEMPERATURE 1°C)

RSC, SHDRT·CIRCUIT RESISTOR 10HMS)

7-294

+100

+125

MC1568, MC1468 (continued)

TYPICAL CHARACTERISTICS (continued)
(Vee = +20 V, VEE = -20 V, Vo =±15 V, TA = +25 0 e unless otherwise noted.)

FIGURE 10 - STANDBY CURRENT DRAIN

FIGURE 11 - STANDBY CURRENT DRAIN
0

5.0

9. 0

-VCC=IIVEEI

1...
E5
a:

rPOSITIVE STANDBY CURRENT

3. 0

a:

a...
2. 0

5.0

I

+125 0 C

~ 4.0
~

-55°C
+25 0 C
+125 0 C

1. 0

'/

-NEGATIVE
STANOBY CURRENTP

24

22

20

18

7. 0

5
6. 0
a:

a

;5

16

1
-55°C
+25 0 C

~

o

r----

~

!§

26

3. 0

!§

NEGATIVE STANOBY CURRENT

2.0
1.0

o

3D

28

--- ---

POSITIVE STANO BY C~N..1--

16

15

32

FIGURE 13 - LOAD TRANSIENT RESPONSE

.I

6
I
I
VCC = VEE = 30 V
0.0 5 -RSC = 4.0 OHMS

>
i5

:;

1\

E

0.04

G

0.0 3

~

0.02

~

0.0 1

a:

UJ
:I:

...

----

~

z·

'"
;::

" ,~
'"

~

-

UJ

~

I

II

16

15

17

I

1 II
18

...=>
'"

I

19

NEGATIVE REGULATOR

...>'"a:

% CHANGE IN Vo
THERMAL SHIFT = CHANGE IN JUNCTION TEMPERATURE-

I

II

t>IL=0-10mA
RSC = 10 OHMS

'"

V

0

~OSITIJE REG~LATO~

-

C>

_V

:;:

20

19

±VO, OUTPUT VOLTAGE I±V)

FIGURE 12 - TEMPERATURE COEFFICIENT OF
OUTPUT VOL TAf:iE
0.0

18

17

±Vin,INPUT VOLTAGE I±V)

~

---

8. 0

4.0

20

TIME, 20 ~s/DiV

±VO, OUTPUT VOLTAGE I±VI

FIGURE 15 - RIPPLE REJECTION

FIGURE 14 - LINE TRANSIENT RESPONSE

>
i5

:;

III

t>VCC = +20 V to +23 V

~OSITIv'E REGJLATO~

E

C>

z·

~

'"
'""
:;
UJ

...>'"=>
:=

NEGATIVE
REGU~OR
RSC = 10 OHMS
IL=lOmA

~ -3 0

N

;::

'"
~

-10
~ -20

~ -40

_

z

t>Vin = +20 to +23 V
RSC = 10 OHMS
I
I
I

~ -50

/

t>VEE = -20 V to -23 V

NEGATIVE REGULATOR-

~

-60

~

-70

V

/

~ -90

=>

'"

1.0 k

10k
f, INPUT FREQUENCY 1Hz)

7-295

..... b-- I-"'"

-

-100
100

TIME, 50 IISI'DiV

/'
PO~ITIVE
REGULATOR

_ _ i"'" / '

~ -80

/

/

lOOk

1.0M

MC1568, MC1468 (continued)

TYPICAL CHARACTERISTICS (continued)
(VCC = +20 V. VEE = -20 V. Va =±15 V. TA = +2S o C unless otherwise noted.)

FIGURE 16 - OUTPUT IMPEDANCE
10

III-

'"
:J::

'"o

RSC 4.0 OHMS
IL= 10mA

~ 1.0

z

«

~

~

to-

~ O. 1
:::>

o

"'

III

0.0 1

100

NEGATIVE REGULATOR
POSITI,Y,E REGULATOR

1.0 k

10 k
f, TEST FREIlUENCY (Hz)

7-296

III
100 k

1.0M

'l____

MC1569
MC1469

P_O_S_I_T_IV_E_V_O
__
LT_A_G_E__R_E_G_U_L_A_TO
__
R_S~

Specifications and Applications InforITIation
MONOLITHIC VOLTAGE REGULATOR
POSITIVE VOLTAGE REGULATOR
INTEGRATED CIRCUIT

The MC1569/MC1469 is a positive voltage regulator designed to
deliver continuous load current up to 500 mAdc. Output voltage is
adjustable from 2.5 Vdc to 37 Vdc. The MC1569 is specified for
use within the military temperature range (-55 to +125 0 C) and the
MC1469 within the a to +700 C temperature range.
For systems requiring a positive regulated voltage, the MC1569
can be used with performance nearly identical to the MC 1563 negative
voltage regulator. Systems requiring both a positive and negative
regulated voltage can use the MC1569 and MC1563 as complementary
regulators with a common input ground.
• Electronic "Shut·Down" Control
•

Excellent Load Regulation (Low Output Impedance - 20 milli·
ohms typ)

•

High Power Capability: up to 17.5 Watts

•

Excellent Temperature Stability: ±0.002 %tc typ

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

~

*
..

0-"'-0

(Bottom View)!
CASE 602A
METAL PACKAGE

• High Ripple Rejection: 0.002 %/V typ

CASE 614
METAL. PACKAGE

G SUFFIX

FIGURE 1 - TYPICAL CIRCUIT CONNECTION
(3.5  3.5 Vdc - Output voltage is set by resistors Rl
and R2 (see Figure 4). Set R2 = 6.8 k ohms and determine
Rl from the graph of Figure 10 or from the equation:
Rl""(2VO-7)kU

7. Remote Sensina
The connection to pin 5 can be made with a separate lead
direct to the load. Thus, "remote sensing" can be achieved
and the effect of undesired impedances (including that of
the milliammeter used to measure I L) on Zo can be greatly

reduced (see Figure 37).

b) For 2.5 .,;; Vo .,;; 3.5 Vdc - Output voltage is set by resis·
tors Rl and R2 (see Figure 51. Resistors Rl and R2 can be

FIGURE 10 - Rl versus Vo
(Vo ;;;>3.5 Vd., See Figure 4)

determined from the graph of Figure 11 or from the
equations:

0

R2""2 (VO) kU
R 1 "" (7 kU-R2) kU
c) Output voltage, VO. is determined by the ratio of Rl and
R2, therefore optimum temperature performance can be

achieved if Rl
coefficient.

~

(R 1 (2 Vo - ;) kn)
IR2 = 6.8 kn)

0

0

V

and R2 have the same temperature
0

/'

d) Output voltage can be varied by making R 1 adjustable as
shown in Figure 43.

e) If Vo = 3.5 Vdc (to supply MRTL"for example), tie pins 6,
8 and 9 together. Rl and R2 are not needed" in this case.
2. Short Circuit Current, Isc
Short Circuit Current, Isc. is determined by Rsc. Rsc may

0

./V

0

.//

be chosen with the aid of Figure 12 or the expression:
0

Rsc""~ ohm

V

V

5.0

10

sc

15

20

30

25

35

VO, OUTPUT VOLTAGE (VOLTS)

where Isc is measured in amperes. This expression is also
FIGURE 11 - Rl and R2 versus Vo
12 5 .,;; Vo .,;; 3.5 Vd., See Figure 5)

valid when current is boosted as shown in Figures 2,29 and

30.
3. Compensation, C c
A O.OOlIJ.F capacitor, C c , from pin 4 to ground will provide
adequate compensation in most applications, with or without current boost. Smaller values of C c will reduce stability
and larger values of Cc will degrade pulse response and output impedance versus frequency. The physical location of
Cc should be close to the MC1569/MC1469 with short lead
lengths.
4. Noise Filter Capacitor, eN
A 0.1 J.LF capacitor, CN, from pin 7 to ground will typically
reduce the output noise voltage to 150J1V(rms). The value
of eN can be increased or decreased, depending on the
noise voltage requirements of a particular application. A
minimum value of 0.001 J1F is recommended.
5. Output Capacitor, Co
The value of Co should be at least 1.0 J.LF in order to
provide good stability. The maximum value recommended
is a function of current limit resistor Rsc:

7.0

2.0
IR1~17

I-l-

I--

kn - R2) kn)

R1

~w

~

w
u

L

Z

u

~ 1.0

iii
'"

z

6.0

"'

./

I-I--

'"

I;;

iii
'"
'"

~

N"

l-

I--

...,

. (IR2 ~ 2 IVO) kn)

-"3.55.0

0

3.0

2.5

VO, OUTPUT VOLTAGE (VOLTS)

Co max "" 250 J.LF
Rsc
where Rsc is measured in ohms. Values of Co greater than
this will degrade the pulse response characteristics and
increase the senl ing time.

6. Shut-Down Control
One method of turning "OFF" the regulator is to apply a
dc voltage at pin 2. This control can be used to eliminate
power consumption by circuit loads which can be put in
"standby" mode. Examples include, an ac or dc "squelch"
control for communications circuits, and a dissipation control to protect the regulator under sustained output shortcircuiting (see Figures 34,39 and 401. Asthe magnitude of
the input-threshold voltage at Pin 2 depends directly upon
the junction temperature of the integrated circuit chip. a
fixed dc voltage at Pin 2 will cause automatic shut-down for
high junction temperatures (see Figure 391. This will pro·
tect the chip, independent of the heat sinking used, the ambient temperature, or the input or output voltage levels.
Standard logic levels of MRTL ,MDTL or MTTL can
also be used to turn the regulator "ON" or "OFF".

FIGURE 12 - Isc versus Rsc

1 700
I-

~
~

i:l

500

\

\

o

'"~
I-

1'l
'"<:;

300

~
o

~ 100

ii
1.0

\

"" --

2.0

3.0

t---

4.0

5.0

6.0

7.0

Rs<, EXTERNAL CURRENT·lIMITING RESISTOR IOHMS)

MC1569-Pg.4

7-300

8.0

MC1569, MC1469 (continued)

TYPICAL CHARACTERISTICS
Unless otherwise noted:

CN

= 0.1

Vin nom

fJF, Cc = 0.001 J-lF, Co = 1.0 J-lF, TC = +25°C,
= +9.0 Vdc, Vo nom = +5.0 Vdc,

IL >200 rnA for R package only.
FIGURE 13 - DEPENDENCE OF OUTPUT
IMPEDANCE ON OUTPUT VOLTAGE

FIGURE 14 - QUTPUT IMPEDANCE versus Rsc

50r---,----r---,r---,----,---,----,---,

30~--+---4---~--~---4----~--+---~

O~

o

__ __ __ ____ __ __ ____L _ - - J
10
5.0
15
35
40
20
25
30
~

~

~

~

~

~

2.0

VO, OUTPUT VOLTAGE (VOLTS)

6.0

0.005

I

0.005

IL=50mA
CO=IO.F

~ 0.004
~
o

:::>

:::>

cp = ~.~

1'\

';;000 1

~

0.00 1

C,=O.lI'F
1.0

1000

100

FIGURE 18 - BIAS CURRENT versus INPUT VOLTAGE

5. 0

1.03
1.02

fil

~

./
./ ./

TJ = +75 0 C AND +125 0 C

1.01

\

0
> 1.00

N

V t:::::::::

0.99
0.98 I--+--+---t-Rsc = 6.8 ohms --I--+-+-jH---1

.- ~

5

i=

I-IL=1.0mA

0.961--+--+--+-+-+-+-+-+-++--1

R2=6.8k

~ 0.951--+--+--+-+-+-+-+--+-#--1

o~ I:TT
a

w

~

w

I : IJ
80

k::7 /

PO.O;~

1000

I, FREQUENCY (kHz)

FIGURE 17 - CURRENT·LIMITING CHARACTERISTICS

0

100

10

t, FREUUENCY (kHz)

:=:::>

r-..

C,= 0.01 I'F

~

Cc =O.lI'F
10

-

c, = 0.001 I'F

1

C, O.Ol.F

'---t" T

1.0

I I I

-

;:;

r;.'

~

16

I

:: 0.002
~

"""=:

;:;

>:::>

14

IL=50mA

ffi

Cc = 0.001 I'F

~ 0.002
~

«

12

~ 0.003

ffi

to

10

z

z

o
~ 0.003

w

B.O

FIGURE 16 - FREQUENCY DEPENDENCE
OF INPUT REGULATION, Co = 2.0 fJF

FIGURE 15 - FREQUENCY DEPENDENCE
OF INPUT REGULATION, Co = 10 fJF

~0.004
~

4.0

Rsc. EXTERNAL CURRENT LIMITING RESISTOR (OHMS)

. . .v

V

/

\
Tr- 55ocl

4.0

5.0

100

10

15

20

25

Vin.INPUT VOLTAGE (VOLTS)

Il, LOAD CURRENT (rnA)

MC1569-Pg. 5

7-301

30

35

40

I

MC1569, MC1469 (continued)

TYPICAL CHARACTERISTICS (continued)
Unless otherwise noted:

CN

= 0.1 jl.F, Cc = 0.001

j!.F, Co = 1.0 jl.F, T C = +25°C,

Vin nom = +9.0 Vdc, Vo nom = +5.0 Vdc,
IL

> 200 mA for R package only.

FIGURE 19 - EFFECT OF LOAD CURRENT ON
INPUT-OUTPUT VOLTAGE DIFFERENTIAL

FIGURE 20 - EFFECT OF INPUT -OUTPUT VOLTAGE
DIFFERENTIAL ON INPUT REGULATION

0.004

2.5,---,-----::::r;:;==--r----,
2.4t_-----;1'7"'~--1---__::;..!_"""'=--_1

w

'0
>

~

~ O.OOl

~ ~2.3t--7r-.-i---~:;;;;+""""----+-:;;-=-..,

~

-

:: 0.002

i5 ~ 2.1 t_--7"'--t--~7"''4t-----_+----_1

'"w
'"

":'z

::>w

~ ~

"-

z

o

>-'

~ 2.2h~---t--:;;>"""'------'H--_=....,;:.'--_l_----_1
...
f--'

!;

,
......

'""1"'

1i:

0.00 I

~

ci~

~ Ci 1 . 9 t _ - - 7 " ' - - t - - - - - + - - - - - j - - - - - _ 1
c
VO=+10Vde
;;
Rsc=O OHM

/

""'-.~

TJ=+250C

r--"-

-.............. r~ r---

I-

2.0t---:-r----t""7"Y;----+-----+-------1

TJ = +1250C

I

TJ - -55°C

.~

I

IL = 1.0 mA
VO= 3.5 Vde

f4VO= 10 Vd
125

250
IL, LOAO CURRENT (mAdel

375

I I

400

E --------

~115;:~+--+--+--+---1

«

.5

'"'"

::>

:;

!;;:;; 10.001 r--1I--t--4......--+---+--+--+--+---+---1

<:;;

~ :::::: r--1I--1-~I"---+_C_'_=.0._1

~=Qm~

0",

~~ 10.000 r - - - i i - - t - - ' r - 1 - - + - - j - - - + - - + - - + - . . ,

~ 9.999 r--1I--f--f--+--+--+---+---+---+----1
9.998

350

f-

ill 300

~_F-I-_-,j--_-+-_-+-_--f
---'--_.l-_

... >

32

FIGURE 22 - TEMPERATURE DEPENDENCE OF
SHORT-CIRCUIT LOAD CURRENT

~1--'20'5~
~ 18 t _ - - i i - - j - - / - 1 - - t - - + - - t - - - j - - - j - - . . ,

!;

24

Vin - VO,INPUT·OUTPUT VOLTAGE OIFFERENTIAL (VOLTSI

FIGURE 21 - INPUT TRANSIENT RESPONSE

~

16

8.0

500

'-'

-r--

250

Q

'"

0

-' 200

r---

f-

~

150

f-

100

'"

0

ili
j

50
-75

Rsc = 2.4 n
Rsc

-r---

o

'-----'_-'-_--'--_--"-_-1-_'-----I_---'-_-'-_~

r----

-

Rsc ' = IOn

-25

-50

~ 3.3n

+25

+50

+75

+100

+125

TA, AMBIENT TEMPERATURE (OCI

I

FIGURE 23 - FREQUENCY DEPENDENCE
OF OUTPUT IMPEDANCE, Co = 10 jl.F

on
:;

":::;
0

1000

FIGURE 24 - FREQUENCY DEPENDENCE
OF OUTPUT IMPEDANCE, Co = 2.0)lF

II II
CO=ID~FII

800

II

Ce=O.I~F

-'

~

...-

w

'-' SOD
z

Ce - 0.01

....--nl

...'"
Q

w

Ce = 0.001

! 400
f-

~F

II
~F

::>

~

200

..,.., V

ill
CO=2.0pF

" 800
3
~
~ 600
z

Ce = 0.1

'"~
Q

~ 200

..-

,.....

.... i-""

..-/

o
1.0

10

100

0.5

1000

1.0

5.0

10

50

f, FREQUENCY (kHzl

f, FREQUENCY (kHzl

MCI569-Pg.6

7-302

-

Ce = 0.001 pF

,I

::>

V

-

c, = 0.01 pF

:=

'I

......

~F

! 400
!;

::>

:=

1000

on

:;

100

500

MC1569, MC1469 (continued)

OPERATIONS AND APPLICATIONS
This section describes the operation and design of the MCI569 positive voltage regulator and also provides information on
useful applications.
SUBJECT SEQUENCE

Theory of Operation
NPN Current Boosting
PNP Current Boosting
Switching Regulator
Positive and Negative Power Supplies

Shutdown Techniques
Voltage Boosting
Remote Sensing
An Adjustable-Zero-TemperatureCoefficient Voltage Source

THEORY OF OPERATION
The usual series voltage regulator shown in Figure 25,
consists of a reference voltage, an error amplifier, and a
series control element. The error amplifier compares the
output voltage with the reference voltage and adjusts the
output accordingly until the error is essentially zero. For
applications requiring output voltages larger than the reference, there are two options. The first is to use a resistive
divider across the output and compare only a fraction of
the output voltage to the reference. This approach suffers
from reduced feedback to the error amplifier due to the
attenuation of the resistive divider. This degrades load
regulation especially at high voltage levels.
The alternative is to eliminate the resistive divider and
to shift the reference voltage instead. To accomplish this,
another amplifier is employed to amplify (or level shift)
the reference voltage using an operational amplifier as
shown in Figure 26. The gain-determining resistors may
be external, enabling a wide range of output voltages. This

FIGURE 25 - SERIES VOLTAGE REGULATOR

Thermal Shutdown
Thermal Considerations
Latch-Up

is exactly the same approach used in the first option. That
is, the output is being resistively divided to match the
reference voltage. There is however, one big difference in
that the output of this "regulator" is driving the input of
another regulator (the error amplifier). The output of the
reference amplifier has a relatively low impedance as compared to the input impedance of the error amplifier.
Changes in the load of the output of the error amplifier
are buffered to the exten t that they have virtually no effect
on the reference amplifier. I f the feedback resistors are
external (as they are on the MC 1569) a wide range of
reference voltages can be established.
The error amplifier can now be operated at unity gain
to provide excellent regulation. In fact, this "regulatorwithin-a-regulator" concept permits the load regulation to
be specified in terms of output impedance rather than as
some percentage change of the output voltage. This approach was used in the design of the MC 1569 positivevoltage regulator.

FIGURE 26 - THE uREGULATOR·WITHIN·A·REGULATOR·· APPROACH
Va

SERIES CONTROL ELEMENT

MC1569-Pg.7

7-303

MC1569, MC1469

(continued)

FIGURE 27
(Recommended External Circuitry is Depicted With Dotted Lines.)

MC1569/MC1469 BLOCK DIAGRAM

"
'--1:"-1
1

eN

r------~

*

:;~

Vot

9

f)

.,.-.!~--,

rOo

I

t

:

I

5
I

,---------..'.h·----..J

I

I

Rl

' D C lEVEL SHIFT

BIAS

~- '-~'

i
I

0

~::::.

~ ~ 10.000

."
>5
01-

> 9.95 0

MC1569-Pg.9

7-305

I I

-t'~tf·l0Ins- ~
J J

I

I 1

I-- I--t,:".lcins- r - 95

J

I

I

1

1-

,

105
100

l

1

I

L

90

85

10.001

\\

II
ff

II

10.000
9.999

MC1569, MC1469 (continued)

TYPICAL NPN CURRENT BOOST CONNECTIONS
FIGURE 29A - 5 VOLT 5-AMPERE REGULATOR

.

·Vinl >6.0V

Vinl

I
I

~ IOmA

IDD"1
"F(lrrillplert!dllttionorintleaud

efficiencvallcwoulpulvoltages,
Ihe colleclor 01 (l1 canlielDB
separate low-vollage suppty as

PNP CURRENT BOOSTING

shown.

A typical PNP current boost circuit is shown in Figure
30_ Voltages from 25 Vdc to 37 Vdc and currents of
many amperes can be obtained with this circuit.
Since the PNP transistor must not be turned on by the
MCl569 bias current (lIB) the resistor Rin must meet the
following condition

FIGURE 29B - 5-VOLT 5-AMPERE REGULATOR
2N3055 OR enulv

boost configuration, particularly for small output
voltages, the circuit of Figure 29 is recommended_ An
auxiliary 9 _5-volt supply is used to power the IC regulator
and the heavy load current is obtained from a second
supply of lower voltage_ For the 5_0 ampere regulator of
Figure 29 this represents a savings of 17_5 watts when
compared with operating the regulator from the single 9_5
V supply_ It can supply current to 5_0 amperes while
requiring an inpu t voltage to the collector of the pass
transistqr of 6_0 volts minimum_ The pass transistor is
limited to 5_0 amperes by the added short-circuit current
network in its emitter (Rsc), (Figure 29B)_

-+5.0 V

Vo

R.
In

V

<--'ill.
lIB

where VBE is the base-to-emitter voltage required to turn
on the PNP pass transistor, (typically 0.6 Vdc for silicon
and 0.2 Vdc for germanium).
For germanium pass transistors, a silicon diode may be
placed in series with the emitter to provide an additional
voltage drop. This allows a larger value of Rin than would
be possible if the diode were omitted. The diode will,
however, be required to carry the maximum load current.

FIGURE 30 - PNP CURRENT
BOOST CONNECTION

SELF-OSCILLATING SWITCHING
REGULATOR
In all of the current boosting circuits shown thus far it
has been assumed that the input-output voltage differential can be minimized to obtain maximum efficiency in
both the external pass element as well as the MC1569.
This may not be possible in applications where only a
single supply voltage is available and high current levels
preclude zener diode pre-regulating approaches. In such
applications a switching-mode voltage regulator is highly
desirable since the pass device is either ON or OFF. The
theoretical efficiency of an ideal switching regulator is
100%_ Realizable efficiencies of 90% arc within the realm
of possibility thus obviating the need for large power dissipating components. The output voltage will contain a
ripple component; however, this can be made quite small
if the switching frequency is made relatively. high so filtering techniques are effective. Figure 31 shows a functional
diagram for a self-oscilla ting voltage regulator. The
comparator-driver will sense the voltage across the inductor, this voltage being related to the load current, IL, by

NPN CURRENT BOOSTING
For applicat!ons requiring more than 500 rnA of load
current, or for minimizing voltage variations due to temperature changes in the IC regulator arising from changes
of the internal power dissipation, the NPN current-boost
circuits of Figure 2 or 29 are recommended_ The transistor shown in Figure 29A, the 2N3055 can supply
currents to 5_0 amperes (subject, of course, to the safe
area limitations)_ To improve the efficiency of the NPN

MC1569-Pg.10

7-306

MC1569, MC1469 (continued)

FIGURE 31 - BASIC SELF'OSCILLATING
SWITCHING REGULATOR

For a first approximation this can be assumed to be a
linear rela tionship.
Initially, Vo will be low and QI will be ON. The voltage at the non-inverting input will approach ~I Yin, when:

-

III

Il

~-1~--~-ryY~-.----.---~~.--evo
CRI

When this output voltage is reached the comparator will
switch, turning QI OFF. The diode, CRI, will now become
forward biased and will supply a path for the inductor cur·
rent. This current and the sense voltage will start to de·
crease until the outpu t voltage reaches

where the comparator will again switch turning QI ON,
and the cycle repeats. Thus the output voltage is approximately Vref plus a ripple component.
The frequency of oscillation can be shown to be

I max

Illavg)

VO(Vin - yO)
f= L Vc I(max)- 10)

(I)

where

10

Vo

I (max) = The maximum value of inductor current
10 = The minimum inductor current.
Normally this frequency will be in the range of approximately 2 kHz to 6 kHz. In this range, inductor values can
be small and are compatible with the switching times of
the pass transistor and diode. The switching time of the
comparator is quite fast since positive feedback aids both
turn·on and turn-off times. The limiting factors are the
diode and pass transistor rise and fall times which should
be quite fast or efficiency will suffer.
Figure 32 shows a self oscillating switching regulator
which in many respects is similar to the PNP curren t boost
previously discussed. The 6.8 H2 resistor in conjunction
with RI sets the reference voltage, Vref. QI and CRI are
selected for fast switching times as well as the necessary
power dissipation ratings. Since a linear inductor is assumed, the inductor cannot be allowed to saturate at
maximum load currents and should be chosen accordingly.
If core saturation does occur, peak transistor and diode
currents will be large and power dissipation will increase.

MC1569-Pg. 11

7-307

FIGURE 32 - MC1569 SELF'()SCILLATING
SWITCHING REGULATOR
Rc

CR3

CR2. CR3
lN4001
OR eGUIV

8>--........_---+vo

•

MC1569, MC1469 (continued)

speed. When the output stage of the error amplifier
approaches saturation, CR2 becomes forward biased and
clamps the error amplifier. Resistor Rc should be selected
to supply a total of 1 mAdc to CR2 and CR3.
To show correlation between the predicted and tested
specifications the following data was obtained:

As a design center is required for a practical circuit,
assume the following requirements:
Yin = +28 Volts
Vo = +10 Volts

lWo=50mV
f~5

Yin = +28 (±I %) Volts

kHz

Vo = +10 Volts

I{max)= 1.125 A

~Vo=60mV

f= 7 kHz

10= I A

(2)
which checks quite well with the predicted values. Rb
can be adjusted to minimize the ripple component as well
as to tr,im the operating frequency. Also this frequency
will change with varying loads as is normal with this type
of circuit. Pin 2 can still be used for shut-down if so
desired. Rsc should be set such that the ratio of load current to base drive current is 10: I in this case II "" 100 rnA
and Rsc = 6.5n.

Using Equation (I), the inductor value can be found:
L- (28-10) 10( I )
2{1.125-1)28 5 x 10 3
""7mH.

POSITIVE AND NEGATIVE POWER
SUPPLIES

For the test circuit, a value of 6 mH was selected. Using
for a first approximation
C - (Vin - VO){VO) .
0- 8L f2 Yin (~V)

(28 - 10)10

As shown, a value of 100 ILF was selected. Since little current is required at .pin 6, Ra can be large. Assume Ra =
47 kn and then use Equation (2) to determine Rb:

Since the internal impedance presented by pin 9 is on
the order of 60n, a value of Rb = IOn is adequate.
Diodes CR2, CR3, and Rc may be added to prevent
saturation of the error amplifier to increase switching

If the MC 1569 is driven from a floating source it is
possible to use it as a negative regulator by grounding the
positive output terminal. The MCI569 may also be used
with the MCI563 to provide completely independent positive and negative voltage regulators with comparable
performance.
Some applications may require complementary tracking
in which both supplies arrive at the voltage level simultaneously, and variations in the magnitudes of the two
voltages track. Figures 3 and 33 illustrate this approach.
In this application, the MCI563 is used as the reference
regulator, establishing the negative output voltage. The
MC 1569 positive regulator is used in a tracking mode by
grounding one side of the differential amplifier (pin 6 of
the MC 1569) and using the other side (pin 5 of the
MC1569) to sense the voltage developed at the junction of
the two 3-k ohm resistors. This differential amplifier
controls the MCI569 series pass transistor such that the
voltage at pin 5 will be· zero. When the voltage at pin 5
equals zero, +VO must equal I-VOl.
For the configuration shown in Figure 33, the level
shift amplifier in the MCI569 is employed to generate an
auxiliary +5-volt supply which is boosted to a 2-ampere
capability by QI and Q2. (The +5-volt supply, as shown,

MC1569-Pg.12

7-308

MC1569, MC1469 (continued)

is not short-circuit protected.) The -15-volt supply
varies less than 0.1 mV over a zero to -300 mAde current
range and the + 15-volt supply tracks this variation. The
+15-volt supply varies 20 mVover the zero to +300 mAde
load current range. The +5 -vol t supply varies less than
5 m V for 0 .;; I L .;; 200 rnA with the other two voltages remaining unchanged. See page 19 for additional information.

zero volts and the only current drawn by the IC regulator
will be the small start current through the 60-k-ohm start
resistor (Vin/60 kQ). This feature provides additional
versatility in the applications of the MC1569. Various subsystems may be placed in a "standby" mode to conserve
power until actually needed. Or the power may be turned
"OFF" in response to other occurrences such as overheating, over-voltage, shorted output, etc.
To activate shutdown, one simply applies a potential
greater than two diode drops with a current capability of
I rnA. Note that if a hard supply (i.e., +3 V) is applied
directly to pin 2, the shutdown circuitry will be destroyed
since there is no inherent current limiting. Maximum
rating for the drive current into pin 2 is 10 rnA, while
1 rnA is adequate for shutdown.

SHUTDOWN TECHNIQUES
Pin 2 of the MCI569 is provided for the express purpose of shutting the regulator "OFF". Referring to the
schematic, it can be seen that pin 2 goes to the base of an
NPN transistor; which, if turned "ON", will turn the
zener "OFF" and deny current to all the biasing current
sources. This action causes the output to go to essentially

FIGURE 33 - A ±15 Vdc COMPLEMENTARY TRACKING REGULATOR WITH AUXILIARY +5.0 V SUPPLY

, ,. rh

3
+20 Vdc

-,,~

~Ibi
;J)

MJ3101
OR EUUIV

OR EaUIV
Vo

U2

=+5 V

-

-"/

MC1569R
MCI469R
POSITIVE REGULATOR

B

12 k

I

;;:r:

~

~400

rnA MAX)

l··,

(2N5223)
OR EUUIV
4

9

~

(10

Rsc = 1.5

I

0.001 .F

Vo =+15Vdc

3k

5

7

?

CASE

62

+Vo = 1- VOI~
RA{kn) +7

F: O.I.F

6.B k

r

MZ4625
OR EOUIV

-=-

2

~,

5.,'V

-b
~

...13k

RB =6.B k

CN
O.I.F,r=3

f2

CASE

620

I
RA = 22 k

9
4
Cc = 0.001 .F
RS = I.B
-20 Vdc

1

MCI563R
MCI463R
NEGATIVE REGULATOR

+

7

B

5

6

/I

T-

-::lO F
•
VO=-15Vdc

(I -",400 rnA MAX)

MC1569-Pg.13

7-309

MC1569, MC1469 (continued)

FIGURE 34 - ELECTRONIC SHUT-DOWN USING A MDTL GATE
+VO
5.0 V

The MC1469 is "Shut-Down" when any

of the Logic Inputs are at the "0" Leval.

+
1.0 JJ F J

IOUAl MOll GATE)

FIGURE 35 - AUTOMATIC LATCH INTO SHUT-DOWN WHEN
OUTPUT IS SHORT-CIRCUITED WITH MANUAL RE-START
Rsc

+Vo

Figure 34 shows how the regulator can be controlled
by a logic gate. Here, it is assumed that the regulator
operates in its normal mode - as a positive regulator
referenced to ground - and that the logic gate is of the
saturating type, operating from a positive supply to
ground. The high logic level should be greater than about
1.5 V and should source no more than lOrnA into pin 2.
The gate shown is of the MDTL type. MRTL and
MTTL can also be used as long as the drive current is
within safe limits (this is important when using MTIL,
where the ou tput stage uses an active pull-up).
In some cases a regulator can be designed which can
handle the power dissipation resulting from normal operation but cannot safely dissipate the power resulting from a
sustained short-circuit. The circuit of Figure 35 solves
this problem by shutting down the regulator when the
output is short-circuited.

,-,!t:-"'IV-~_.. (+10 V)

VOLTAGE BOOSTING
+Vin (+15VI
11k

5.1k

tNormally"ON", ':"

·Clisundtoallowautomatic
"STAAT·UP" when Vin is
first applied.

FIGURE 36 - VOLTAGE BOOSTING CIRCUIT
2N3738
DR EOUIV

VO' 100 Vd.

68k
100.F

150 V

I--<:>----.....~ 25 k

20 k

The MCI569 has a maximum output voltage capability
of 37 volts which covers the bulk of the user requirements.
However, it is possible to obtain higher output voltages.
One such voltage boosting circuit is shown in Figure 36.
Since high voltage NPN silicon devices are readily
available, the only problem is the voltage limitations of the
MC I 569. This can be overcome by using voltage shift
techniques to limit the voltage to 35 volts across the
MC I 569 while referencing to a higher output voltage.
The zener diode in the base lead of the NPN device is
used to shift the output voltage of the MCI569 by approximately 75 volts to the desired high voltage level, in
this case 100 volts. Another voltage shift is accomplished
by the resistor divider on the output to accommodate the
required 25 volt reference to the MC1569. The 2 kn
resistor is used to bias the zener diode so the current
through the 4.7 kn resistor can be controlled by the
MC1569. The IN4001 diode protects the MCI569 from
supplying load current under short circuit conditions and
Q2 serves to limit base current to QI. For Rsc as shown,
the short circuit current will be approximately 100 rnA.
In order to use a single supply voltage, Vin(2) can be
derived from Vin(I) with a zener diode, shunt preregulator.
It can be seen that loop gain has been reduced by the
resistor divider and hence the closed loop bandwidth will
be less. This of course will result in a more stable system,
but regulator performance is degraded to some degree.

REMOTE SENSING
The MCI569 offers a remote sensing capability. This
is important when the load is remote from the regulator,

MC1569-Pg.14

7-310

MC1569, MC1469 (continued)

as the resisl3nce of the interconnecting lines (YO and
GND) are added directly to the output impedance of the
regulator. By remote sensing, this resistance is included
inside the control loop of the regulator and is essentially
eliminated. Figure 37 shows how remote sensing is accomplished using both a separate sense line from pin 8 and a
separate ground line from the regulator to the remote
load.

AN ADJUSTABLE ZERO-TEMPERATURECOEFFICIENT (O-TC) VOLTAGE
REFERENCE SOURCE.
The MC1569, when used in conjunction with low TC
resistors, makes an excellent reference-voltage generator. If the 3.5 volt reference voltage of the IC regulator is
a satisfactory value, then pins 8 and 9 can be tied together
and no resistors are needed. This will provide a voltage

FIGURE 37 - REMOTE SENSING CIRCUIT

reference having a typical temperature coefficient of
0.002%/oC. By adding two resistors, Rl and R2, any
voltage between 3.5 Ydc and 37 Ydc can be obtained
with the same low TC (see Figure 38).

THERMAL SHUTDOWN
By setting a fixed voltage at pin 2, the MC 1569 chip
can be protected against excessive junction temperatures
caused by power dissipation in the IC regulator. This is
based on the negative temperature coefficient of the baseemitter junction of the shutdown transistor and the diode
in series with pin 2 (-3.4 x 1O-3y/oC). By setting 1.0
Ydc externally at pin 2, the regulator will shutdown when
the chip temperature reaches approximately + 1400C. Figure 39 shows a circuit that uses a zero-TC zener diode and
a resistive divider to obtain this voltage.

FIGURE 38 - AN AOJUSTABLE "ZERO·TC" VOLTAGE SOURCE
+Vin ...----a-:~----_,
1+10 Vdc)

1-'-0--.....- . +vz
Rl (+4.0 Vdc)
1.0k

6.8 k
R2

FIGURE 39 - JUNCTION TEMPERATURE LIMITING SHUTDOWN CIRCUIT
FIGURE 398 - USING A TA REFERENCE

FIGURE 39A - USING A ZERO TC REFERENCE

Vpin 2 (for shutdown) ~ 1.38 - 3.4 X 10-3 (TJ - 25 0C)
+Vin (15 V)

+Vin

1.5 k

Rl

2.0mA
+1.0 V

+5.1 V
2.0 k
lN3826

OR eaulv

(15 V)

R2

560

+1.0 V

510

820

MC1569-Pg. 15

7-311

Rsc

+VO

•

MC1569, MC1469 (continued)

fiGURE 40 - THERMAL SHUTDOWN WHEN USING
E XTER NA L PASS TRANSISTORS

FIGURE 41 - DC SAFE OPERATING
0.7 .--_,----,_.,-,-..,..:=A,..,Rc=E;A'-_,-_,-_.,-,-_-,
0.6 1---l--+--+-+~-I---I--f--,\r+--+-----1

10k

0.5

f--+--j-+-+-+-+-+---+--j-->r-+--j

0.4

:~-

------THERMAL LIMITATION ITc " 25°CI
----SECONOARY BREAKOOWN LIMITATION
W
1 - _ _ _ BONOING WIRE LIMITATION
~ 0.3
1
1

+Vin

(',o.v:t
l +-------------+-70,.:..:...tJ./w;....'"0

'"

:>

TJ';; 150°C

!2 0.2

r"

_

\

\

"

i---+--t-f-'MC1469G -1f--""I-:Y+.-+-+-+-~H
MC[156[9G
,~C1469,R ____
[
' . MC1569R---'

0.1 L-_.L.--.J_.L...L..LL-..I-_--'-_..!....<,_--'---:'-_LJj

3.0

4.0

5.0 6.0 7.0 8.0

10

20

30

40

Vin - Vo (VOLTSI

In the case where an external pass transistor is employed, its temperature, rather than that of the IC regulator, requires controL A technique similar to the one just
discussed can be used by directly monitoring the case
temperature of the pass transistor as is indicated in Figure 40_ The case of the normally "OFF" thermal monitoring transistor, Q2, should be in thermal contact with,
but electrically isolated from, the case of the boost transistor, QI_

exceed the maximum junction temperature rating during
this fault condition and, in addition, the dc safe operating
area limit (see Figure 41).

THERMAL CONSIDERATIONS
Monolithic voltage regulators are subjected to internal
heating similar to a power transistor. Since the degree of
internal heating is a function of the specific application,
the designer must use caution not to exceed the specified
maximum junction temperature (+150 0 C)_ Exceeding
this limit will reduce reliability at an exponential rate_
Good heatsinking not only reduces the junction temperature for a given power dissipation; it also tends to improve
the dc stability of the output voltage by reducing the
junction temperature change resulting from a change in the
power dissipation of the IC regulator. By using the deratin~ factors or thermal resistance values given in the
Maximum Ratings Table of this ---/
I

I
O.OI.F;:!::; ·C i
I
I

[11

I

MC1569R
MC1469R

*
Rl

CASE

R2=6.Bk

Select RI to give desired VO: Rl

~

12 Vo -7) kn

·C j - May be required if long input leads are used.

Me 1569-Pg. 18

7-314

MC1569, MC1469 (continued)

PARTS LIST
Component

Description

Value

Rl
R2

Select
6.8 k

114 or 1/2 watt carbon

*RA

Select

I RC Model X-201 Mallory Model MTC-l

Rsc

Select

1/2 watt carbon

or equivalent
*RL'

Select

For minimum current of 1 mAde

Co

1.0 pF

Sprague 1500 Series, Dickson 0 10C series

CN
Cc
*Cj

0.1 pF
0.001 pF
pF

QI
Q2

MC1569R or MC1469R
2N5223, 2N706, or equivalent

*HS

-

Heatsink Thermalloy 116168B

*Socket

(Not Shown)

Robinson Nugent 110001306
Electronic Molding Corp. 116341·210-1,
6348-188-1,6349-188-1

PC Board

-

Circuit Dot, Inc. IIPC1113
1155 W. 23rd St., Tempe, Ariz. 85281

or equivalent

~

Ceramic Disc - Centralab ODA 104,
Sprague TG·Pl0, or equivalent

om

·Optional

LATCH-UP
Latch-up of these and other regulators can occur if:
1. There are plus and minus voltages available
2. A load exists between

Vo+ and Vo- (This "common load" may be something inconspicuous

- e.g. an operational amplifier. Nearly everyone who uses + and - voltages will have a
common load from VCC to VEE.)
3. Vin + and Vin - are not applied at the same time.

The above conditions result in one of the two outputs becoming reverse-biased which prevents the
regulator from turning ON . Latch-up can be prevented by the circuit configurations shown in
Figures 44 and 45.

FIGURE

44

Vint

lN4001 OR EDUIV

R1

Nate: Thiscanfiguralianillcreasesminimurn
input-llutput differential va1tage by" 0.1 V.

FIGURE

45

MC1569-Pg. 19

7-315

MC1569, MC1469 (continued)

INDEX

MC1569 Specification
Page No_
Circuit Schematic (MC1569)
Complementary Tracking Voltage Regulator
Dual Power Supplies
Electrical Characteristics
General Design Information

Latch-Up

Maximum Ratings
Mechanical Outline Drawings

NPN Current Boost
PNP Current Boost
Printed Circuit Board Layout
Shutdown Techniques
Switching Regulator
Theory of Operation

Test Circuits
Thermal Considerations

Thermal Shutdown
Typical Characteristics (Curvesl
Typical Circuit Connection

Voltage Boosting
Zero TC Voltage Reference Source

MC1569-Pg_ 20

7-316

8
1,12
1,12

2
4
19
2
2
1,10
10
17
4,13
10
7,8,9
3
16
15
5,6
1.4,18
14
15

________I

"\

LINEAR/DIGITAL INTERFACE CIRCUITS

"---------------'

MC1580L

MONOLITHIC DUAL LINE DRIVER/RECEIVER

DUAL LINE DRIVER/RECEIVER
INTEGRATED CIRCUIT
MONOLITHIC SILICON

The output current of the MC1580L switches in response to a
differential input voltage. A wide common·mode input and output
voltage range makes this device ideal for transmission of digital infor·
mation in a noisy environment. Typical applications include driving
a twisted·pair transmission line, line sharing, voltage comparator, and
logic level translation.

EPITAXIAL PASSIVATED

• High Input and Output Impedance - 5.0 k ohms at 10 MHz typ
• Low Propagation Delay - 18 ns max
• Wide Common·Mode Input and Output Voltage Range ± 3.5 V Input min and -3.0/+9.0 V Output min
• Input Gating Ability
• Bias Driver for MECL Applications, plus Interfacing Capability
with MRTL, MDTL, and MTTL
• Compatible with Other Devices of the Line Driver/Receiver
Series

(top view)

Ceramic Package
Case 632
(TO·116)

BLOCK DIAGRAM

OUTPUT OUTPUT
'2

MECL 81AS
•

OUTPUTOU1PU1
12
Il

r---------~----~--~------+_--------~--------r__r------~--------~-------o8VCC
INPUT 5

!INPUT

\OINPIST
!!INPUT

L

---------+------~--------t=~======~===:t======:t====:==:t========j:======~14GND
1V EE

OUTPUT OUTPUT

,

2

OUTPUT OUTPIIT
11
13

MECl81AS

•

r--.----~--~--_+--~--~--------~----------+_--r_--~--~----~~--------o8VCC
600

INPUT 5 o-----~,-[

600

. ] - + - - - - - 0 9 INPUT

rt---i--------oIO INPUT
tllNPUT

INPUT 3

rl4GND

DIFFEAENTIALGAIN
INPUT AMPLIFIER

LEVEL
TfiANSLAT(lIt

QU1?UT
STAGE

OUTPUT
STAGE

See Packaging Information Section for outline dimensions.

7-317

LEVEL

OIFFEilENTtALGAIN

TRANSLATOR

INPUT AMPLIFIER

MC1580l (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating

Symbol

Value

Unit

VCC

+7.0

Vdc

VEE

-7.0

Vin

±7.0

Volts

CMVin

±10

Volts

lI()JA

575
3.85

mW
mW/oC

Operating Temperature Range

TA

-55 to +125

°c

Storage Temperature Range

Tstg

-65 to +175

°c

Power Supply Voltage
Differential-Mode I nput Signal Voltage
Common-Mode Input Signal Voltage
Power Dissipation (Package Limitation)

PD

Ceramic Dual I n-Line Package
Derate above T A = +25 0C

ELECTRICAL CHARACTERISTICS (Each Line Driver/Receiver, Vee = +5.0 V, VEE = -5.0 V, TA
unless otherwise noted)
Characteristic
Operating Supply Currents

Figure
1

Symbol

Min

Typ

Max

Unit

ICC

-

5.0
25

8.0

mA

0.01

0.1

lEE
I "put Leakage Current

1

IR

I "put Current

1

lin

TA = -55°C
TA = +25 0C
TA=+1250C
Output Leakage Current

1

ICEX

Output Load Current
TA = -55°C
TA = +25 0C
TA=+125 0 C

1

IOL

Output Load Current Match
TA = -55°C
TA = +250 C
TA=+1250C

6

30

J1A
mA

-

0.04
0.02
0.01

0.2
0.1
0.1

-

O.S

5.0

J1A
mA

6.5
6.9
6.8

8.1
8.6
8.5

9.8
10.4
10.2

-

0.25
0.2
0.15

0.5
0.5
0.5

VCC

+4.75

+5.0

-4.75

-5.0

+6.00
-6.00

Vdc

VEE
MECL Bias Voltage IVEE - -5.2 Vdcl

VBB

-1.11

-1.175

-1.24

Vdc

Input Voltage Transition Width"
TA = -55°C
TA = +25 0C
TA=+1250 C

VTR

-

30
35
40

50
50
50

Switching Times
Propagation Delay Time

2

Input Resistance

Output Capacitance
Output Resistance

Common-Mode Voltage Gain
f = 60 MHz

-

13

18

tpd-

13

18

tr
tf

-

11
7.0

-

Cp lin)
Rp lin)
Cp (out)
Rp(out}

-

9.0
8.0
10
10

CMVRin

+3.5
-3.5
+9.0
-3.0

-

tpd+

Parallel Impedance (f = 5.0 MHz)
Input Capacitance

Output

mV

-

Rise Time
Fall Time

Common-Mode Voltage Range (-55 to +1250 C)
Input

mA

610L

Power Supply Operating Range

I

= +250 e

3

4

CMVR out

5

ACMV

Power Dissipation

PD

*Measurement taken from pOints of Unity Gain.
Ground unused output pins and their corresponding inputs to assure correct device biasing.

7-318

-

ns

-

-

pF
k ohms
pF
k ohms

+4.4
-4.2
+10
-3.3

-

Volts

-40

-

150

180

-

dB
mW

MC1580L (continued)

CHARACTERISTIC DEFINITIONS

FIGURE 1 - TERMINAL CURRENTS

FIGURE 2 - TRANSIENT RESPONSE

+5.0 Vdc
+5.0 Vdc
.-~t---.-.---.-.,....-,

ein: trand If";;5 os
AU Ir and If measured 10% to 90%
All tpdHnd tpd_ measured 50%to 50%
+0.1 Vdc
-0.1 Vdc

ICEX

1
51

51
tpd-

-5.0 Vdc

eout

FIGURE 4 - COMMON-MODE OUTPUT VOLTAGE RANGE
+5.0 Vdc
e~'n
+O.10Vdc
- -OVdc
-0.10 Vdc

FIGURE 3 - COMMON-MODE INPUT VOLTAGE RANGE
+5.0 Vdc

ein -

+0.10 Vdc

C:\':'~' 0 Vdc

"--1 - -

L-O.l0VdC

Common-Mode Input Voltage

causes a 10% shift in the level of
eout oreout whichever occurs

Common-Mode Output Voltage
Range;:; The Value of .\I<"'"which
causes a 10% shift in the de level
eout oreout whichever occurs

first.

first.

Range 2 The Value of .lI""which

-5.0 Vdc
51

51

51

1k

51

± POWER SUPPLY JJ"

eout

eout

FIGURE 6 - OUTPUT CURRENT MATCH
+5.0 Vdc

FIGURE 5 - COMMON-MODE VOLTAGE GAIN
+5.0 Vdc

ACMV = 20 log 10

'out p.p
em pop

MEASURED WITH 'in POp = 1.0 Volt

+0.050 Vdc

eout

-

-5_0Vdc

.....- -.....- -..... ein

7-319

MC1580L (continued)

TYPICAL CHARACTERISTICS
FIGURE 8 - EXPANDED OUTPUT LOAD CURRENT versus
SUPPLY OPERATING VOLTAGE AT +25 0 C

FIGURE 7 - OUTPUT LOAD CURRENT versus SUPPLY
OPERATING VOLTAGE AND TEMPERATURE
10

;;
oS
I15
c:

+25a e

"

8.0

«

I

4.0

c

...l

I

II

=>

:==>
2.0

f"

I
./

:2
8.25

8.50

8.75

9.25

6 1

'

10

1;

:==>

-

Vdo

R;COrder

9.75

«

g

-

c

...l

8.4

I
II
8.2

.---

/

8.0
9.4

10.25 10.50 10.75

IVeel + IVEE!. SUPPLY OPERATING VOLTAGE IVOLTS)

;;
oS

~

1.0

I-

~
c:

a
c

«

g

l-

2.0
3.0
4.0
5.0

=>

:=

=>
c

\

r-

6.0

8.0
9.0
-1 DO

51

-

10.2

10.6

10.4

10.8

11

x
R~corder

~

~

4

~

13

~

2

c

z
o

~

;;:'"

\.

1

\"-..

0

"- ........... r--..

.0

1/'PdjC--

........... ........

o

g: 8. 0

-

0"

a. 7. 0
j. 6. 0

I.
"" 'pd+-

5.0

-80

-60

-40

-20

+20

+40

+60

+80

+100

-0.4

+0.4

VTR. DIFFERENTIAL INPUT VOLTAGE (mV)

I

10

9.B

9.6

FIGURE 10 - PROPAGATION DELAY versus
DIFFERENTIAL INPUT VOLTAGE

w

5 . OVd t:

\ Ii
I
J
->=

14

::5w

'pd-

c

z

0

~

13

........-:

;;:'"
0

g:

12

~

--

V

/
\

./'
......V

tpd+

I--

.!1-

~

.!1-

11
-75

-50

+1.2

+1.6

+2.0

'in. DIFFERENTIAL INPUT VOLTAGE (VOLTS)

-25

+25

+50

+75

TA. AMBIENT TEMPERATURE (0 C)

7-320

+100

+125

+2.4

+2.8

MC1580L (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 12 - INPUT IMPEDANCE versus FREQUENCY
-

~

10

~

B.O

z

--

5.0

- -- -

.........

~
~

6.0

~
z

+5 0 Vdc

I---

C

I----

~ 4.0 I---I----

;Ii

I

2.0 I - - -

~

1

_

~

4

I

"""

eRX(rms) = 100 mV

!

I

-S.OVdc

TO HP2508

-

~

a: 1.0

1

:- L

t'--

RX ]TER or iQU'V.

-I'

1.0

I

~

I

5.0

-

3.0

r-.....

Rp in

"",

4.0 ~

Cp in

---

~

...
~

c

r--.....

2.0 ~

i'-

~
;;!

1.0 ~

r--

10

~
z

50

100

f, FREQUENCY IMHzl

FIGURE 13 - OUTPUT IMPEDANCE versus FREQUENCY

i

20

1

.1

I

I
I

eRXlrms) = 100 mV

""z
w
u

15

~

I

~
~
~

10

g
~

w

~

~

~

5.0

f'\
+S.OVdc

~~

t----

'""-

--

'"

r- r-

1

r-~
~

........

r---.. ..........

11l'~61

)Ioutl

.......

"--

;!t
TO HP250B AX METER

o

£-

''"0"'',

0
1.0

I

-S.OVdc

I
5.0

10
t, FREQUENCY

IMHzl

Lutl

'-Z

8

r-

--

- r--

r--

-

i- i-

50

•

FIGURE 14 - COMMON·MODE GAIN RATIO versus FREQUENCY

--

-45

" -40

~

z

--

~ -35

--

r.......

...............

w

g

~

'" -30
'"8'"
,; -25
~

...............

---

1'i

«

-20
10

15

25

40

70

100

f, FREQUENCY (MHzl

7-321

150

250

400

700

1000

MC1580L (continued).

APPLICATIONS INFORMATION
The output stage of the driver switches a current source between
the two driver outputs in response to the input logic signals. Hence,
a voltage differential that is a function of the line termination im·
pedances is created on the twisted pair and at the input of the .re-

Line Driver/Receiver Family Characteristics
The Motorola line driver/receiver series provides interface cir-

cuits for driving digital data transmission lines e.g., coaxial cable or
twisted pair. The digital data transmission isvia a balanced differential mode. The line drivers and receivers are designed to provide

ceiver. The receiver is designed to reject +3.5/-3.5 Volts of comm~n­
mode voltage signals which may be present due to ground loop
currents and noise coupled from nearby transmission lines.
While common·mode noise is the major concern in a twisted
pair transmission line; a good data transmission system must offer

high common-mode noise rejection, present high impedances to the

transmission line and have low propagation times. A feature of the
drivers is the capability to operate in a party-line mode whereby a
number of drivers can be connected to a single line. This series pro-

some immunity from differential-mode voltages that may be present

vides drivers and receivers compatible with MRTL, MDTL, MTTL
and MECL. The five circuits of the family are:

due to mismatches in termination impedances. The drivers and re.ceivers of the MC1580 Series are designed with this requirement in

mind. The exact amount of noise immunity depends on line im-MC1580L
MC1581L
MC1582L
MC1583L
MC15B4L

Dual
Dual
Dual
Dual
Dual

Line Driver/Receiver
MECL Receiver
MDTLlMTTL Driver
Receiver (Open Collector)
Receiver (Active Pullup)

pedances but the following example shows how differential-mode

noise immunity is calculated for a given system. For a line with a
characteristic impedance of 20 calculate the minimum differential
input voltage from the equation.
1

lo(min) x Zo

Figure 15 indicates line drivers and receivers recommended for in·
teriacing with each of the various digital logic families. The

± Vin = -=---::4--=

MC1580L serves as a basic building block and can be used as a

(6.9) (170)
For a 17O-ohm line, Vin = - - 4 - - = 0.29 Volts.

driver or receiver with any of the indicated digital logic families by
adding the appropriate external components.
FIGURE 15

Since the MC1580L requires 50 mV maximum input differential
to maintain the output state, the worst case differential·mode noise

Digital Logic Family

Driver

Receiver

MECL

MC15BOL

MC15B1L

MDTL

MC15B2L

MCI5B3L·
MC15B4L

MTTL

MC15B2L

MC15B3L
MC15B4L

MRTL

MC15BOL
MC15B2L

immunity is 0.26 V. (See Figure 171.
FIGURE 17

<
E
>-

MC15B3L

~

=

These five circuits are extremely useful in numerous applications
other than line drivers and receivers. The differential amplifier in·
put of 1he receiver makes it useful in applica1ions such as voltage
comparators, waveform generators and high·input·impedance buf·
fers. The drivers and receivers are useful as logic level translators.

a>::>

:=::>
0

\

1.0
2.0

\

\

3.0
4.0

NOISE MARGIN
I
I

5.0
6.0

NOISE MARGIN
I
I

t--

1\

7.0

1\

.J

E? 8.0
9.0
10

The MC1580L in Figure 16 serves as the line driver and line
receiver for a balanced differential transmission line. The driver
input and receiver outputs of Figure 16 are compatible with MRTL.

-0.5

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

Vin, DIFFERENTIAL INPUT VOLTAGE (VOlTSI

FIGURE 16

1------,
1

1/2 MCI580l

I

- - - - , +3.6 V

MRTl

1

1/2 MCI580l

INPUT

1

I

640

/"'---;0-+-_ D
640
+3.6 V

7-322

MC1580L (continued)

APPLICATIONS INFORMATION (continued)
If additional drivers are connected to the line, a matching current
source is connected for each added driver. The current sources are
connected to the line so that when all drivers are transmitting logic
"O"s, the difference in current drawn from the terminating resistors
of the two wires in the twisted pair is equal to one current source
(8.6 mAl. The current sources should also be connected so that
when any driver transmits a logic "1" then a current difference of
the opposite polarity exists. The matching current source should

Hence the direct coupling of the driver and receiver to the line provides a built-in differential-mode noise immunity. The direct coup-

ling also matches the line at all frequencies (often a problem with
ae coupling lines). The recovery problem in ae coupling devices
at high-signal repetition rates is also eliminated.
High input and output impedances of the MC1580L minimize

impedance discontinuities on the transmission line and allow many
drivers and receivers to be connected to the line.

be the companion circuit on the MC1580L driver chip. The differ-

Use of the MC 1580L in a bi-directional MECL compatible transmission system is shown in Figure 18. The MC1580L has an internal
MECL bias network that allows the circuit to be used as a MECL

ence in amplitude of the current sources on a single chip is specified
to allow the system designer to calculate the maximum current
source mismatch. AIOL. and hence the maximum number of drivers
that can be connected to a given transmission line.

line driver. The drivers of Figure 18 are connected so that the current sources from both drivers pull current from the same wire of
the twisted pair when both drivers are transmitting logic "0" signals.
The external current source, IS, supplies the current required by
one driver. The current for the other driver is drawn from the termination impedances, creating a voltage differential across the line.
When either driver transmits a logic "1", a voltage difference of the
opposite polarity is created across the line. For a system with two
drivers the current source (IS) can be supplied by a 60o-ohm resistor connected to +5.0 Volts.

The MC1580L has many other uses in a digital system. The high

input impedance suggests its use as a buffer for delay lines and in
waveform generation circ:uits. Figure 19 shows the MC1580L used
as a differential comparator in a double-ended limit detector. When
the input signal amplitude is between the two reference voltages, the
output signal will be a logic "1"; otherwise a logic "0" output is
obtained. The voltage transition region is typically less than 40 mV.
External components R 1 and CR 1 establish an MDTL compatib'le
signal.

FIGURE 18 - BI·DIRECTIONAL TRANSMISSION

r REcEiVER --,

I
I

1/2 MC1581 L

I
I
MECL
LOGIC
OUTPUTS

MECL
LOGIC "--<:>--=:---+---L.L---+~D--~
INPUT

MECL

+-<>'-'--+-----"...-1--+....::..0-_ LOGIC

INPUT

MECL
LOGIC
OUTPUTS

Zo
2
I

DRIVER

L 2.0. MC1580L --.l

FIGURE 19 - DOUBLE·ENDED LIMIT DETECTOR

+5.0 V

Rl
LOW VO LT AG E ........--(~+---\"
REFERENCE

2.0 k

~IL---~- mJ~~~CE

INPUT
VOLT.;.A;.:G;.:E_ _./~JL--l----+-~- LOW VOLTAGE REFERENCE

INPUT
VOLTAGE
HIGH
VOLTAGE
REFERENCE

HIGH

",:--+~.........~... OUTPUT

5.0V

CRI

OUTPUT
VOLTAGE

-0.7 V

7-323

~

MC1580L (continued)

APPLICATIONS INFORMATION (continued)
Voltage Translator
Translation of voltage levels from MECL (best suited for the highspeed portion of a digital system) to MHTL (tailored for the noisy
output portion of the system) is often required. The MC1580
performs this function as indicated in Figure 20.

FIGURE 20 - MECL TO MHTL VOLTAGE LEVEL TRANSLATOR

r- -

;nM~5;'

--j
I

MEC L INPUT ........_-{>---.J'---\

I
I
)
MECL BIAS DRIVER

I

L ______ I
~

I

7-324

12

MHTL OUTPUT
MHTL GATE

L...--ooo'f

"

MC1581L

LINEAR/DIGITAL INTERFACE CIRCUITS
"_ _ _ _- - - J

DUAL MECL
LINE RECEIVER
INTEGRATED CIRCUIT

MONOLITHIC DUAL MECL LINE RECEIVER

... designed with output emitter follower voltage levels that switch
in response to a differential input voltage. The device output voltage
levels are compatible with that of the MECL digital logic family.
With its excellent common·mode input voltage range, the MC1581 Lis
ideally suited for receiving digital data in noisy environments. Typical
applications include line sharing, voltage comparator, and level
translation.
•

High Input Impedance - 8.0 k ohms @ 10 MHz

•

Low Propagation Delay Time - 20 ns max

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

CASE 632
CERAMIC PACKAGE

TO·116

• Wide Common·Mode Input Voltage Range - ± 3.5 Vdc
•

Device Compatability with Other Members of the Line
Driver/Receiver Series

14

1

hop view)

BLOCK DIAGRAM

CIRCUIT SCHEMATIC

,

OUTPUT

OUTPUT

OUTPUT
8

r-_,------T_--_,-------------------++-~--------~;_------------------~--~------T__,---oVCC
600

6DD

600

60D

EMITTER FOLLOWER

OUTPUTS

See Packaging Information Section for outline dimensions,

7-325

I

•

MC1581 L (continued)

MAXIMUM RATINGS (TA

=+25 0 e unless otherwise noted)

Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

+7.0

Vdc

Vee

-7.0

Vin

±7.0

Volts

CMVin

±10

Volts

575

mW
mW/oC

Differential-Mode Input Signal Voltage
Common·Mode Input Signal Voltage
Power Dissipation (Package Limitation)
Ceramic

Dualln~line

Po

Package

Derate above T A = +250 C
Operating Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (Each Receiver, Vee
Characteristic
Operating Supply Currents

l/BJA

3.85

TA

-55 to +125

°c

T stg

-65 to +175

°c

=+5.0 Vdc, VEE = -5.2 Vdc, T A =+25 0 C unless otherwise noted)

Figure

Symbol

Min

Typ

Max

Unit

1

ICC

-

5.3

8.0

mA

lee

-

22.2

28.1

-

-

0.1

Input Leakage Current

1

IR

I nput Current

1

lin

TA = -55°C

-

0.020

0.1

TA = +25 0 C

-

0.014

0.1

TA = +125 0 C

-

0.012

0.1

TA = -55°C

-0.825

-0.900

-0.990

TA = +250 C

-0.690

-0.780

-0.850

TA = +1250 C

-0.535

-0.62

-0.700

TA = -55°C

-1.580

-1.83

-

TA = +25 0 C

-1.500

-1.70

-

TA = +125 0 C

-1.380

-1.73

-

TA = -55°C

-

20

50

TA = +25 0 C

-

20

50

TA = +125 0 C

-

30

50

Output Voltage High

Output Voltage Low

1

Volts

VOL

I nput Voltage Transition Width'

Switching Times

Volt

VOH

1

I'A
mA

mV

VTR

2
tpd+
tpd_

-

15

20

-

25

30

Rise Time

tr

-

12

~

Fall Time

tf

-

23

-

Propagation Delay Time

ns

Parallel Input Impedance (f - 5.0 MHz)

Capacitance

Cp (in)

-

4.5

-

pF

Resistance

Rp (in)

-

14

-

k ohms

CMVRin

+3.5
-3.5

+4.4
-4.2

-

Volts

VCC

+4.75

+5.0

+6.00

Vdc

Vee

-4.75

-5.2

-6.00

145

185

Common·Mode I nput Voltage Range
(TA = -55 to +1250 C)

3

Power Supply Operating Renge

Total Power Dissipation

Po

*Measurement taken from points of Unity Gain.

Ground unused inputs to assure correct device biasing.

7-326

mW

MC1581 L (continued)

CHARACTERISTIC DEFINITIONS

FIGURE 1 - TERMINAL CURRENTS AND VOLTAGES

FIGURE 2 - TRANSIENT RESPONSE

+_-;

eout ..-._ _

-5.2 Vdc

eout..-.--...
To Five MECl Gates
{MC101O or Equiv.}
To Five MECL Gates
{MC10l0 or Equiv.}

FIGURE 3 - COMMON·MODE INPUT VOL TAGE RANGE

eout

-5.2 Vdc
51

eout
0.1

eout

-

eout

I

lk

-=

+D.1DVdc

ein'

VOH

~F

0 Vdc -

-= -=

~
-

-

-

-

-

-0.10 Vdc -

Common-Mode Input Voltage

Range is that value of the
variable supply
which
causes a 10% shift in eout or
eoutwhichever occurs first.

prr

7-327

MC1581 L (continued)

TYPICAL CHARACTERISTICS
FIGURE 4 - OUTPUT VOLTAGE var.,. INPUT VOLTAGE AND

FIGURE 5 - OUTPUT VOLTAGE var.,s INPUT VOLTAGE AND

TEMPERATURE

SUPPLY VARIATION
+0.25 r---,--r---.,.---,--,--....,.--,---,

+0.25

g-0.25

VEE =-5.2 Vd,
VCC =+5.0 Vd,

'----

+1250C

~ ·0.50
w
~

-0.75

~

-1.00

~

-1.25

./

.

/,

~ -1.5 0

./

1«.."

8

,./

"

-2.00
-2.2 5
40

-30

-20

-10

~

.0.751===F==f==/;;;;;;Z

~

·1.00

~

0-

~ -1.50

~-1.75
-2.00

-55 0C
+10

1----t--+--1f-

~ -1.25

+250 C

'A. '\., ~

~ ·1.75

·0.25

~ -0.50

~ A
~~

>

.!S

+20

+30

-2.25-4~0:---=---::---7:--~~-':'C+l~0~~+-:20:--:+::30:--+4:'-0

+40

'in. DIFFERENTIAL INPUT VOLTAGE (mV)

'in. DIFFERENTIAL INPUT VOLTAGE IVOLTS)

FIGURE 6 - PROPAGATION DELAY varsus
DIFFERENTIAL INPUT VOLTAGE

FIGURE 7 - PROPAGATION DELAY versus
AMBIENT TEMPERATURE

19

2

9

31

18

2

8

30

7

2

16

2

7~

3

15

J..
\ I'....

14
13

\

12

'-....

11

'pd-

'"""--

o

2

5

2

4

"- r--'pd-

2

r--

3

r--

2

'p;-

10

9.0

6

2

2

2
1
2.0

1.0

11
-75

29~

tpd+

-50

~

- I---

-

-25

'in p.p. DIFFERENTIAL INPUT VOLTAGE IVOLTS)

"

28 ..
~
21 '"
~

o

26 ;;:
m

25~

24

+25

+50

+75

+100

!

23
+125

TA. AMBIENT TEMPERATURE 10C)

FIGURE 8 - PARALLEL INPUT IMPEDANCE versus FREOUENCY
+6.0

+24

a
:!: +20

-d'

w

'"~Z +16

t--.

~ +12

Cp{in)

r-...

~

~ +8. 0
~+4. 0

to:
.f..

-----

....... 1'-.

.......
Rplin)

~

ein =\00 mVllrms)

0

0:

-4.0
1.0

2.0

5.0

10
f. FREQUENCY (MHz)

7-328

-r-

+5.0:[

~

+4.0 ~

........

..........

-

20

+3.0

r-

~
c:

I--

+2.0 ;::

~

+1.0 ~

o

~

~
~

-1.0
50

100

.:!!

MC1581 L (continued)

APPLICATIONS INFORMATION
Line Driver/Receiver Family Characteristics
The Motorola line driver/receiver series provides interface circuits for driving digital data transmission lines, e.g., coaxial cable
or twisted pair. The digital data transmission is via a balanced differential mode. The line drivers and receivers are designed to pro-

vide high common-mode noise rejection, present high impedances
to the transmission line and have low propagation times. A feature
of the drivers is the capability of operating in a party-line mode

whereby a number of drivers can be connected to a single line. The
series provides both drivers and receivers compatible with MRTL,
MDTL, MTTL and MECL. The five circuits of the family are:
MC1580L
MC1581L
MC1582L
MC1583L
MC1584L

While common-mode noise is the major concern in a twisted pair
transmission line, a good data transmission system must offer some
immunity from differential-mode voltages that may be present due
to mismatches in termination impedances. The drivers and receivers
of the MC1580 series are designed with this requirement in mind.
The exact amount of noise immunity depends on line impedances
but the following example shows how differential-mode noise immunity is calculated for a given system. For a line with a character·
istic impedance of 2 0 , calculate the minimum differential input
voltage from the equation:

lo(min) X Zo
± Vin = -'---4

Dual Line Driver/Receiver
Dual MECL Receiver
Dual MDTLlMTTL Driver

(6.9) (170)

Dual Receiver (Open Collector)
Dual Receiver (Active Pullup)

For a 17(}.ohm line. Vin

- 0.29 Volts

4

Figure 9 indicates the line drivers and receivers recommended for
interfacing with each of the various digital logic families.

Since the MC1581 L requires a 50 mV maximum input differential to maintain the output state, the worst case differential-mode
noise immunity is 0.26 V. (see Figure 11),

FIGURE 9

Digital Logic Family
MECL
MDTL

Driver

Receiver

MC1580L
MC1582L

MC1581L
MC1583L
MC1584L

MTTL

MC1582L

~g1~m

MRTL

MC1580L
MC1582L

MC1583L

These five circuits are extremely useful in numerous applications
other than line drivers and receivers. The differential amplifier input
of the receiver makes it useful in such applications as voltage comparators, waveform generators and high-input impedance buffers.
The drivers and receivers are useful as logic level translators.
The MC1581 L in Figure 10 serves as the line receiver in a bal·
anced differential transmission line. The outputs of the MC1581 L
receiver and the inputs to the MC1580L driver are compatible with

FIGURE 11

:<

.s

~

3.0

G

5.0

~

~

~

0

\
I
I

1.0
2.0
4.0

NOISE MARGIN
I
I

6.0

I--

II
\

7.0

-" 8.0

0

9.0
10
-0.5

NOISE MARGIN
I
I

-0.3

-0.4

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

V;n. DIFFERENTIAL INPUT VOLTAGE (VOLTS)

MECL.

FIGURE 10 - MECl COMPATIBLE TRANSMISSION SYSTEM

r--------,

r--------,

I

1/2 MC1581L

I

(

I

(

I
I

I
(
(

I

10

I

MECL

11

OUTPUTS

I

20

I

'2

I
I
I
)

1/2MC1580L

L _________ -l
The output stage of the driver switches a current source between
the two driver outputs in response to the input logic signals. Hence.
a VOltage differential that is a function of the line termination impedances is created on the twisted pair and at the input of the receiver. The receiver is designed to reject +3.5 V/-3.5 V of commonmode voltage signals which may be present due to ground loop
currents and noise coupled from nearby transmission lines.

)

L _ _ _ _ _ _ _ ..J

Hence the direct coupling of the driver and receiver to the line provides a built-in differentialwmode noise immunity. The direct coupling also matches the line at all frequencies (often a problem with
ac coupled lines). The recovery problem in ac coupling devices
at high-signal repetition rates is also eliminated.
High input impedance of the MC1581 L and high output impedance of the MC1580L minimize impedance discontinuities on the

7-329

•

MC1581 L (continued)

APPLICATIONS INFORMATION (continued)
transmission line and allow many drivers and receivers to be con·
nected to the line.

are connected to the line so that when all drivers are transmitting
logic "O"s, the difference in current drawn from the terminating
resistors of the two wires in the twisted pair is equal to one current
source (8.6 mA1. The current sources should also be connected so
that when any driver transmits a logic "1" a current difference of
the opposite polarity exists. The matching current source should
be the companion circuit on the MC1580L driver chip. The difference in amplitude of the current sources on a single chip is
specified to allow the system designer to calculate the maximum
current source mismatch, .6.IOL, and hence the maximum number
of drivers that can be connected to a given transmission line.

Use of the MC1581 L and the MC1580L in a bi-directional
MECL compatible transmission system is shown in Figure 12. The
MC1580L has an internal MECL bias network that allows the circuit to be used as a MECL line driver. The drivers of Figure 12 are

connected so that the current sources from both drivers pull current
from the same wire of the twisted pair when both drivers are trans·
mitting logic "0" signa1s. The external current source, IS. supplies
the current required by one driver. The current for the other driver
is drawn from the termination impedances creating a voltage differ-

ential across the line. When either driver transmits a logic "1", a
voltage difference of the opposite polarity is created across the line.
For a system with two drivers the current source (IS) can be
supplied by a 600-ohm resistor connected to +5.0 Volts. If additional drivers are connected to the line, a matching current source
must be connected for each added driver. The current sources

Voltage Translator
Translation of voltage levels from MHTL (tailored far the noisy
input/output system portions) to MECL (best suited for the high-

speed logic circuits) is often required.
this function as shown in Figure 13.

The MC1581 L performs

FIGURE 12 - 81-DIRECTIONAL TRANSMISSION

r RECEIVER --,

I
I

liZ MCI581 L

I
I
MECL
LOGIC
OUTPUTS

MECL
LOGIC
INPUT

"'--<>-"--+--j /""'---~r_'_'-<>___,

MECL
LOGIC
OUTPUTS

......=>-"'-t---::'?""I----1r-''-<>--4

Zo

Z
)

ORIVER

L~M~5~..J
FIGURE 13 - MHTL-TO-MECL VOLTAGE LEVEL TRANSLATOR

i - - i7ZMC;S8;;: ---;
I
MHTL

)

ZO k
0'

Input ,--...Jo""",--~---~-----o-t--;

MECL OUTPUT

•

ZO k

~~---r--o--~

-5.Z V

I

_____ -.I

7-330

IT

MECL
LOGIC
INPUT

l ..

_L_1N_E_A_R_I_D_I_G_IT_A_L_IN_T_E_R_F_A_C_E_C_I_R_C_U_IT_S----J

MC1582L

DUAL MDTLlMTTL
LINE DRIVER
INTEGRATED CIRCUIT
MONOLITHIC DUAL MDTL/MTTL
LINE DRIVER

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

· .. designed with a three· input AND gate input circuit. The differen·
tial output current switches in response to an MDTL or MTTL compatible
input voltage level. Typical applications include driving twisted'pair
transmission lines, line sharing, and logic level translation.

•

Low Propagation Delay Time - 20 ns max

• Wide Common·Mode Output Voltage Range +9.0/-3.0 Volts
•

High Output Impedance - 7.0 k Ohms@ 10 MHz

• 3-lnput AND Gate
•

Device Compatibility with Other Members of the Line
Driver/Receiver Series

(top view)

CERAMIC PACKAGE
CASE 632
TO-116

OUTPUT OUTPUT
13

12

,---r-;._ 9

INPUT 3
INPUT 4

INPUT

10 INPUT

r - - - " - - ' - - 1 1 INPUT

INPUTS

L-----+---_4------~---__<'----~---_4

_ _ _ _ _ _ _ __o1VEE

CIRCUIT SCHEMATIC

OUTPUTOU1PUl
13
12

OUTPUT OUTPUT

2

,

600

600

S.Ok

S.lJk

INPUT 4»-14-+--J+--+----t:

J---1H~---__<>---____---<0--+_ ___<0-_ _
"AND" INPUT

THRESHOLD

DIFFERENTIAL

LEVEL

GATE

SET

AMPLIfiER

TRANSLATOR

OUTPUT
STAGE

tURftENT$OURt;E
REGULATOR

See Packaging Information Section for outline dimensions.

7-331

~-+_---+---_0_

OUTPUT

LEVEL

DIFFERENTIAL

STAGE

TRANSLATOR

AMPLIFIER

_____o1 VEE

THRESHOLD
SeT

"AND" INPUT
GATE

MC1582L

(continued)

MAXIMUM RATINGS (TA ~ +25 0 e unless otherwise noted)
Symbol

Value

Unit

VCC

+7.0

Vdc

VEE

-7.0

Input Signal Voltage

Vin

+30

Volts

Power Dissipation (Package Limitation)

Po
l/(JJA

575
3.85

mW
mW/oC

Operating Temperature Range

TA

-55 to +125

°c

Storage Temperature Range

Tstg

-65 to +175

°c

Rating
Power Supply Voltage

Ceramic Dual In-line Package
Derate above T A ~ +25 0C

ELECTRICAL CHARACTERISTICS (Each Line Driver, Vee ~ +5.0 Vdc, VEE ~ -5.0 Vdc. TA ~
unless otherwise noted)
Characteristic

Operating Supply Currents

Max

·Unit

8.0

10

rnA

25

30

0.04

0.1

Figure

Symbol

Min

Typ

1

ICC
lEE

-

-

I nput leakage Current

1

IR

I nput Current

1

lin

Output leakage Current

1

ICEX

Output load Current
TA = -55°C
TA=+250C
TA=+1250C

1

IOl

Output load Current Match
TA = -55°C
TA = +250 C
TA=+1250C

2

AIOl

-

0.72
0.70
0.63

1.0
1.0
1.0

-

0.8

5.0

VTR

J.IA.
mA

6.5
6.9
6.8

8.1
8.6
8.5

9.8
10.4
10.2

-

0.7
0.8
0.8

-

-

-

-

50
40
50

-

mA

-

Input Voltage Transition Width'
TA = -55°C
TA = +250C
TA = +125 0C

J.IA.
mA

-

TA = -55°C
TA = +250 C
TA=+1250C

+25 0 e

mV

Switching Times

Propagation Delay Time

•

3

Rise Time
Fall Time
Threshold Voltage
TA =_550 C
TA = +25 0C
TA=+1250C

3

Parallel Output Impedance If = 5.0 MHz)
Capacitance

-

15

20

-

13

18

tr
tf

-

8.0
7.0

-

0.9
1.1
0.9

1.74
1.45
1.16

2.0
1.8
1.5

-

10

+9.0
-3.0

+10
-3.3

-

RDlout)
4

Power Supply Operating Range

Input Breakdown Voltage
Power Dissipation
'Measured from points of unity gain with a 50 ohm load.
Ground all unused input pins to assure correct device biaSing.

7-332

CMVRout

ns

Volts

VTH

Cplout)

Resistance
Common-Mode Output Voltage Range
T A = -55 to +1250C

tpd+
tpd-

18

pF
k ohms
Volts

-

VCC

+4.75

+5.0

+6.0

VEE

-6.0

-5.0

-4.75

VIHH

15

30

-

Volts

Po

-

140

170

mW

Vdc

MC1582L (continued)

CHARACTERISTIC DEFINITIONS

FIGURE 1 - TERMINAL CURRENTS

FIGURE 2 - OUTPUT CURRENT MATCH

+5.0 Vdc

t

10L 1

-=

-5.0 Vdc

-=

-=+5 Vdc

FIGURE 3 - TRANSIENT RESPONSE
All tr and If measured 10% to 9(}l11o
+5.0 Vdc

51

51

eoul

FIGURE 4 - COMMON·MODE OUTPUT VOL TAGE RANGE
+5.0 Vdc
n:Ft
'
+3.0Vdc
'

-

-

-

-+1.5Vdc

oVdc
Common-Mode Output Voltage
Range ~ The Value of -V-which
causes a 10% shift in the de level
eout or eOul whichever OCcurs
first.

-5.0 Vdc
51

51

± POWER SUPPLY

eout

7-333

r

-

I

MC1582L (continued)

TYPICAL CHARACTERISTICS

FIGURE 5 - OUTPUT LOAD CURRENT versus SUPPLY
OPERATING VOLTAGE AND TEMPERATURE
4.5

;;:

.s....

5.0
5.5

~

6.0

~

6.5

~

7.0

....
~

7.5

:l
~

8.0

~

8.5

o

r----

FIGURE 6 - OUTPUT LOAD CURRENT versus
INPUT VOLTAGE AND TEMPERATURE

.mJ
" " " "y ..y.y.

8; Vccm+5.00Vdc

~

;;:

14D'.' .
:a
~
I

51

~

-=- ,'- \

Recorder

'.\

V/ ~~;~~

~

6.4

~

8.0

....
-'

9

9.25

9.50

9.75

10

10.25

10.50

11.2
1.0

11

10.75

o

1.2

1.1

~

14

:t

~

3

i'--..

-.............

r---

'pd-

2

1.4

1.5

1.7

1.6

1.8

1.9

----

~

:'l:

tpd+

/1

./

Rpl au.)
15

5.05

~
....w
........

9 .0 ].

;;:

8.0

;t

0

o

-25

+25

+50

+75

+100

+125

~

6.0

~....

~
4.0 ~

......

10

o

1

~

7.0 ;:

l;;

=>

-~

8.0

o

CpI Du.)

"'-

3.0 ~
2.0 ~

~ 5. 0

-50

2.0

9.0

~
w
<.>

1

].1 1
9. 0
-75

1.3

o

5

to

\

~ 20

1

18

z

~

FIGURE 8 - PARALLEL OUTPUT IMPEDANCE
versus FREQUENCY

19

6

-55 DC -

'in, INPUT VOLTAGE IVOLTS)

FIGURE 7 - PROPAGATION DELAY TIME versus
AMBIENT TEMPERATURE

~o

....-

',.V

I

VCC + VEE ,SUPPLY OPERATING VOLTAGE IVOLTS)

7

+250 C

+125 DC

9.6

9.0
9.5
9.0

V

4.8

:l

+125 DC

II

3.2

o
'"

VI~

1\ (

1.6

a

VE,--5oo
Vd,

..,.

\ f

'I

.s

TA,AMBIENT TEMPERATURE IDC)

1, 0
1.0

1,0 :.

2.0

5.0

10

f, FREQUENCY IMHz)

I

7-334

20

50

100

MC1582L (continued)

APPLICATIONS INFORMATION
Line Driver/Receiver Family Characteristics
The Motorola line driver/receiver series provides interface circuits for driving digital data transmission lines e.g .• coaxial cable or

twisted pair. The digital data transmission isvia a balanced differential mode. The line drivers and receivers are designed to provide
high common-mode noise rejection, present high impedances to the

transmission line and have low propagation times. A feature of the
drivers is the capability to operate in a party-line mode whereby a
number of drivers can be connected to a single line. This series provides drivers and receivers compatible with MRTL. MDTL, MTTL

and MECL. The five circuits of the family are:
MC1580L
MC1581L
MC1582L
MC1583L
MC1584L

Dual Line Driver/Receiver
Dual MECL Receiver
Dual MDTLlMTTL Driver

Dual Receiver (Open Collector)

The output stage of the driverswitches a current source between
the two driver outputs in response to the input logic signals. Hence,
a voltage differential that is a function of the line termination im~
pedances is created on the twisted pair and at the input of the re~
ceiver. The receiver is designed to reject +3.51-3.5 Volts of common~
mode voltage signals which may be present due to ground loop
currents and noise coupled from nearby transmission lines.
While common~mode noise is the major concern in a twisted
pair transmission line; a good data transmission system must offer
some immunity from differential~modevoltages that may be present
due to mismatches in termination impedances. The drivers and re~
ceivers of the MC1580 Series are designed with this requirement in
mind. The exact amount of noise immunity depends on line impedances but the following example shows how differential-mode
noise immunity is calculated for a given system. For a line with a
characteristic impedance of Zo, calculate the minimum differential
input voltage from the equation.

Dual Receiver (Active Pullup)

Figure 9 indicates line drivers and receivers recommended for
terfacing with each of the various digital logic families.

±Vin

in~

=

IO(min) x Zo
-=---'4-'::
(6.9) (170)

For a 17Q..ohm line, Vin = - - 4 - - = 0.29 Volts.
FIGURE 9

Since the receivers recommended for use with the MC1582L
driver require 50 mV maximum input differential to maintain the
output state, the worst case differential-mode noise immunity is

Digital Logic Family

Driver

Receiver

MECL

MC1580L

MC1581L

MDTL

MC1582L

MC1583L
MC1584L

MTTL

MC1582L

MC1583L
MC1584L

.5

MC1583L

ffi

MRTL

MC1580L
MC1582L

0.26 V. (See Figure 111.
FIGURE 11

;;(

~

1.0

\

2.0

\

3. 0
~ 4. 0

a....
These five circuits are extremely useful in numerous applications
other than line drivers and receivers. The differential amplifier in·
put of the receiver makes it useful in applications such as voltage
comparators, waveform generators and high-input-impedance buf~
fers. The drivers and receivers are useful as logic level translators.

~

5
..J

NOISE MARGIN
I
I

5. 0

6. 0
7.

r--

11

0

11

}9 B. 0

The MC1582L in Figure 10 serves as the line driver for a balanced
differential transmission line. The driver input and receiver outputs of the MC1584L receiver are compatible with MTTL circuits.

NOISE MARGIN
I
I

9. 0
10

-0.5

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

Vin, DiffERENTIAL INPUT VOLTAGE (VOLTS)

FIGURE 10 - MDTL, MTTL COMPATIBLE TRANSMISSION SYSTEM

"",---+<:J--_ 0

MDTl or MTTL
INPUTS

I

112

MTTlDUTPUT

r----;-I-<>---e D

I

_R~V~_J

DRIVER
BALANCED TRANSMISSION LINE

7-335

MC1582L (continued)

APPLICATIONS INFORMATION (continued)
Hence the direct coupling of the driver and receiver to the line provides a built·in differential·mode noise immunity. The direct COUP4
ling also matches the line at all frequencies (often a problem with

driver transmits a logic "1", a voltage difference of the opposite
polarity is created across the line. For a system with two drivers

ac coupling lines).

connected to +5.0 volts.
If additional drivers are connected to the line. a matching current
source is connected for each added driver. The current sources are
connected to the line so that when all drivers are transmitting logic
"O"s. the difference in current drawn from the terminating resistors
of the two wires in the twisted pair is equal to one current source
(8.6 mAL The current sources should also be connected so that
when any driver transmits a logic "1" then a current difference of
the opposite polarity exists. The matching current source should
be the companion circuit on the MC1580l driver chip. The differ~
ence in amplitude of the current sources on a single chip is specified
to allow the system designer to calculate the maximum current
source mismatch, alOl, and hence the maximum number of drivers
that can be connected to a given transmission line.

The recovery problem in ac coupling devices

at high-signal repetition rates is also eliminated.

The high output impedance of the MC1582L and the high
input impedances of the MC1584L drivers minimize impedance
discontinuities on the transmission line and allow many drivers and

receivers to be connected to the line.
Use of the MC1584L in a bi·directional MDTL or MTTL com·
patible transmission system is shown in Figure 12. The MC1582L
drivers of Figure 12 are connected so that the current sources from
both drivers pull current from the same wire of the twisted pair
when both drivers are transmitting logic "0" signals. The external
current source,ls. supplies the current required by one driver. The
current for the other driver is drawn from the termination impedances, creating a voltage differential across the line. When either

the current source (IS) can be supplied by a 600·ohm resistor

FIGURE 12 - BI·DIRECTIDNAL TRANSMISSION

r------I
1

1/2 MC15B4L
RECEIVER

I

I
)

I

120--..;.1----7"'"'
130---'-----~

)
L ___ _

r----------,
112 MC15B4L
I

-l

_____ J

I

I
10

10

Zo

Zo

"2

"2

r-----

RECEIVER

I

~:----.:..I----012

I

/"-----'-----013

)
L __ _ _ _ _ _ _ _ J

r- -

-

--..,

I

1

I

I
1

L

112 MC15B2L
___ ~R~~ _ _

I

I

)

I
1

1
J

J

7-336

\

LINEAR/DIGITAL INTERFACE CIRCUITS

MC1583L

MONOLITHIC DUAL LINE RECEIVER
The MC1583L is a dual open collector output line receiver designed
for use in line sharing, differential voltage comparator, and level translator applications. The output transistors switch in response to a
differential input voltage. Output logic voltage levels are compatible
with MTTL, MDTL, and MRTL logic levels when a suitable external
pullup resistor is connected to the device output. Excellent commonmode input voltage range makes this device ideal for receiving digital
data in a noisy environment.

•

High Input Impedance - 12 Kilohms@ 5.0 MHz

•

Low Propagation Delay Time - 40 ns max

•

Excellent Common-Mode Input Voltage Range - ± 3.5 V min

•

Compatible with Other Members of the Line Driver/Receiver
Series - MC1580 thru MC1584

DUAL SATURATED LOGIC
RECEIVER
(OPEN-COLLECTOR)
MONOLITHIC SI LICON
EPITAXIAL PASSIVATED

CERAMIC PACKAGE
CASE 632

TO-l'6

(top view)

Block Diagram

r---------t-------~------+-~r_----~------_r--_r------T_------T_--------~----08

Vee

Input 4

9 Input

Input5

10 Input

1 VEE

14Gnd

Circuit Schematic
Output
I

8 Vee
600

600

600

1.61k

Input 4 o---~~t-..,

r----1I--I------<> 9 Input

Input 5

10 Input

r14Gnd

~--~----~------~----------~~~--4-------~--------~----4-----~-------o7VEE
Differential
Input Amplifier

Lllllel
Translator

Differential Amplifier
and Output Transistors

Current Source
Regulator

See Packaging Information Section for outline dimensions.

7-337

OifferentialAmplifier
and Output Transiston

levil
Translator

Differential
Input Amplifier

I

I

MC1583L

(continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Power Supply Voltage

Differential·Mode I nput Signal Voltage

Symbol

Value

Unit

VCC

Vdc

VEE

+7.0
-7.0

Vin

±7.0

Vdc

CMVin

±10

Vdc

Static Output Load Current

IOL

20

mA

Power Dissipation (Package Limitation)

PD

575
3.85

mW
mW/oC

Common-Mode I nput Voltage

Derate above T A

= +25 0 C

Operating Temperature Range
Storage Temperature Range

TA

-55 to +125

T stg

-65 to +175

°c
°c

ELECTRICAL CHARACTERISTICS (Each Receiver)
(VCC

= +5.0 Vdc, VEE = -5.0 Vdc, T A = +25 0 C unless otherwise noted)
Figure

Symbol

Min

Max

Unit

1

ICC

-

15

18

mA

lEE

-

16

20

-

0.012

0.1

= -55 0 C
= +25 0 C
= +125 0 C

-

0.033

0.1

-

0.025

0.1

0.020

0.1

Output Leakage Current

-

0.8

5.0

Characteristic
Operating Supply Currents

I nput Leakage Current

1

IR

I nput Current

1

'in

TA
TA
TA

Output Voltage Low (IOL
TA
TA
TA

= 20 mA)

1

ICEX

1

VOL

= -550 C
= +25 0 C
= +125 0 C

Input Voltage Transition Width:!:

Typ

mA

= -55°C
TA = +250 C
TA = +125 0 C

-

0.23

-

0.25

-

0.28

DAD
DAD
DAD

-

12

50

mV

-

4.0

50

-

8.0

50

tpd+
Ipd_

-

30

Rise Time

'r

-

24
34
16

Fall Time

tf

-

5.0

Parallel Input Capacitance

Cp

-

4.0

Parallel I nput Resistance

Rp

-

12

CMVin

+3.5

+4.3

-3.5

-4.2

Switching Times

2

Propagation Delay Times

Parallel Input Impedance (f

-

ns

40

-

= 5.0 MHzl

Common-Mode Input Voltage Range

TA

J.!A
Volt

VTR

TA

J.!A

3

= -55 0 C 10 +125 0 C

Power Supply Operating Range

Total Power Dissipation

Ground unused input pins to assure correct device biasing.
tMeasurement taken from points of Unity Gain with 3.9-kilohm load resistor.

7-338

-

pF
k ohms

-

Volts

Vdc

VCC

4.75

5.0

6.0

VEE

-6.0

-5,0

-4.75

PD

-

140

175

mW

MC1583L (continued)

TEST CIRCUITS AND TYPICAL CHARACTERISTICS
(Vee

= +5.0 Vdc, VEE = -5.0 Vdc, T A = +25 0 C unless otherwise noted)

FIGURE 1 - TERMINAL CURRENTS

FIGURE 2 - TRANSIENT RESPONSE
+5.0 Vdc

+5.0 Vdc

All tr and tf measured 0.4 V to 2.4 V
All tpd+and tpd- measured 50%10 1.5 V
+O.OIOVdc--~----..

oVdc

oVdc

-5.0 Vdc

tpd-

MC833 or Equiv

FIGURE 3 - COMMON-MOOE INPUT VOL TAGE RANGE

FIGURE 5 - OUTPUT VOLTAGE versus DIFFERENTIAL
INPUT VOL TAGE AND TEMPERATURE

+5.0 Vdc
5.0

O.IOVdC

~
- - - - 0 Vdc

eir) -

~

-0.10 Vdc

4.0

0

Common-Mode Input Voltage
Range - The Value of .\I'""which
causes a 10%shift in the level of

eout or eout whichever occurs
first.

~
w

'"«
~
0
>

+125 0 C

3.0

r--

+25 0C - -550C

!; 2.0

~
0

3.9 k 3.9 k

m

eoul

1.0

o

eoul

-10

-8.0

-6.0

-4.0

-2.0

+2.0

+4.0

+6.0

+8.0

+10

'in, OIFFERENTIAL INPUT VOLTAGE (,.VI

FIGURE 4 - SUPPL Y OPERATING CURRENT versus SUPPLY
OPERATING VOLTAGE AND TEMPERATURE

I

5.0

:1
I-

16

f--+--+-_+-_f~ 4.0

~

15f--+--+_-~~~-~--f--+-

'"
B

14f--+--~~_+-_f--~~~~+--_r--+--t

'"z
~

*

i
;

o

~

~

3.0

r-- _-55°C -

o

13

>

~

12f--~~+_-_r
11

w

'"

r--+ 25 OC r--

+125 0C

2.0

l-

=>
o

f---tf-+-+

I~

1.0

10 1--+--+---+
9.0 L----'_---'-_...L_-'-_"-_'------'_-'-_~---'
8.75 9.00 9.25 9.50 9.75 10
10.25 10.50 10.75 II 11.25

-10

-8.0

-6.0

-4.0

-2.0

+2.0

+4.0

+6.0

'in. DIFFERENTIAL INPUT VOLTAGE (mVI

VCC + VEE. SUPPLY OPERATING VOLTAGE (VOLTSI

7-339

+8.0

+10

I

MC1583L

(continued)

- TYPICAL CHARACTERISTICS (continued)
(VCC

= +5.0 Vdc, VEE = -5.0 Vdc, TA = +25 0 C unless otherwise noted)

FIGURE 6 - OUTPUT SATURATION VOLTAGE versus
OUTPUT LOAD CURRENT AND TEMPERATURE

FIGURE 7 - PROPAGATION DELAY versus
DIFFERENTIAL INPUT VOLTAGE

;;; 0.50

17
16

I-

i5

0.45

>
~ 0.40

~

0.35

+150 C

./

../ V

a

;:; 0.30
a
~ 0.25

i=
~

+115 0 C

./

../

-55 0 C

a

+'

16

a

'"

i

~

:~

2-, 5

..l 0.05

>

~

22
1
20
19

z

....... ~ V

=>
~ 0.10
=>
a

24
13

a

. / ~V

0.15

25

~

~
~

V . . . . ........- ...........

0.10

]:

\
.1
\\
\
........

-.......... 1---..3.9 k!! Load

I,

r-- t--39~n Loa~-

0

o

5.0

10

15

10

15

30

35

40

45

50

0.1

0.4

10L, OUTPUT LOAD CURRENT (rnA)

>-

~a

19

33

2B

\

1

z

30

~

19

a

'"
~
~

_

\

I'\..

17

'"I"-.. -

390 n load
Dr
3.9 kn Load

"&. 26

~
~

15

~

14

'"~

3

a

1\

21

1.0

1.2

1.4

'1.6

~

~

5
0.4

0.6

O.B

1.0

1.1

1.4

2.0

1.6

I.B

1.0

42

""-

26

~

40

"'

39

tpd+

......,390!! Load

3B

i---

~

........

3.9 k!! Load

37

L

36

..........

~

35

l'---.

I r---=:and

c,

>-

3.9 k Load

't..

22 I-:-,..tpd-

41

tpd!

...........-.

390!l Load

20

14
0.1

I.B

'i~(P'P) = J.l V_

>-

1B

O.B

FIGURE 9 - PROPAGATION DELAY
versus AMBIENT TEMPERATURE

34

31

0.6

'in(p·p), DIFFERENTIAL INPUT VOLTAGE (VOLTS)

FIGURE 8 - PROPAGATION DELAY versus
DIFFERENTIAL INPUT VOLTAGE

~

.-

14
3

34

~

a
z
a

;::

'"
'"
~
~
~
~

33

9
-75

32
-50

-15

'inlp·p). DIFFERENTIAL INPUT VOLTAGE IVDL IS)

+25

+50

+75

+100

+125

TA.AMBIENT TEMPERATURE IOC)

FIGURE 10 - PARALLEL INPUT IMPEDANCE versus FREQUENCY

r- r-.

14
~

w

11

r-.

u

Z

'"

In

~

I-

7.0

1

r---..

10

~
~

1

6.0

z

Rplin)

.......

~

w

6.0

""""

~
~

~
~

4.0

~

1.0

..........

- t:----....
.......

...........

4.0

5.0

6.0

7.0 B.O 9.0 10
f. FREQUENCY (MHz)

7-340

;'3

U

20

30

I-

-----

40

~
~

w

........

0:

3.0

4.0
3.0

r1.0

I-

~

Cp(in)

........

1.0

'"

5.0

~

B.O

~
~

w
u

50

2.0

b

60

~
~

~
~

1.0

o
70 BO 90 100

£"

J-

MC1583L (continued)

APPLICATIONS INFORMATION
Line Driver/Receiver Family Characteristics

output device and hence eliminates the need for an external resistor
for MTTL and MDTL compatible systems. The MC1584L has a

The Motorola line driver/receiver series provides interface cir-

6-mA output sink current limitation.
The output stage of the MC1582L driver switches a current
source between the two driver outputs in response to the input
logic signals. Hence, a voltage differential that is a function of the
line termination impedances is created on the twisted pair and at
the input of the receiver. The receiver MC1583L is designed to
reject +3.5/-3.5 Volts of common-mode voltage signals which may
be present due to ground loop currents and noise coupled from
nearby transmission lines.
While common-mode noise is the major concern in a twisted
pair transmission line; a good data transmission system must offer
some immunity from differential-mode voltages that may be present
due to mismatches in termination impedances. The drivers and receivers of the MC1580 Series are designed with this requirement in
mind. The exact amount of noise immunity depends on line impedances' but the following example shows how differential-mode
noise immunity is calculated for a given system. For a line with a
characteristic impedance of 20> calculate the minimum differential
input voltage from the equation.

cuits for driving digital data transmission lines e.g., coaxial cable or
twisted pair. The digital data transmission isvia a balanced differential mode. The line drivers and receivers are designed to provide
high common-mode noise rejection, present high impedances to the

transmission line and have low propagation times. A feature of the
drivers is the capability to operate in a party-line mode whereby a
number of drivers can be connected to a single line. This series provides drivers and receivers compatible with MRTl, MDTL, MTTL
and MECL. The five circuits of the family are:
MC1580L
MC1581L
MC1582L
MC1583L
MC1584L

Dual line Driver/Receiver
Dual MECL Receiver
Dual MDTLlMTTL Driver

Dual Receiver (Open Collectod
Dual Receiver (Active Pullup)

Figure 11 indicates line drivers and receivers recommended for interfacing with each of the various digital logic families.
These five circuits are extremely useful in numerous applications
other than line drivers and receivers. The differential amplifier input of the receiver makes it useful in applications such as voltage

±V.

Digital Logic Family

= -=lo:..l_m_i_n_1_x_Z-"o

4

In

FIGURE 11

Driver

16.9111701
For a 17O-ohm line, Vin = - - 4 - - = 0.29 Volts.

Receiver

MECL

MC1580L

MC1581L

MDTL

MC1582L

MC1583L
MC1584L

MTTL

MC1582L

MC1583L
MC1584L

MRTL

MC1580L
MC1582L

MC1583L

Since the MC1583L requires 50 mV maximum input differential
to maintain the output state, the worst case differential-mode noise
immunity is 0.26 V. (See Figure 13).
FIGURE 13

comparators, waveform generators and high-input-impedance buffers. The drivers and receivers are useful as logic level translators.

.s~

\

\

f0-

BS 3.0
~

The MC1583L in Figure 12 serves as a line receiver for a
balanced differential transmission line. The driver inputs and
receiver outputs of Figure 12 are compatible with MTTL and MDTL
circuits. The MC1583L has an open collector output circuit which
is designed to sink 20 rnA. The open collector allows the user to
interface with MRTL, MDTL, or MTTL by supplying the appropriate external resistor and power supply connection. A 9-volt
BVCEO rating on the open collector transistor allows the MC1583L
to interface with MHTL also.
The MC1584L receiver can also be used to interface with
MOTL and MTTL. The MC1584L contains an active pullup on the

"\

1.0
2.0

4.0

NOISE MARGIN
I
I

G

~ 5.0
~

6. 0

o

7.0

NOISE MARGIN
I
I

f--

II

1\

9-' 8.0

9.0
10
-0.5

-0.3

-0.4

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

Vin, OIFFERENTIALINPUT VOLTAGE IVOL TSI

FIGURE 12 - MDTL, MTTL COMPATIBLE TRANSMISSION SYSTEM
+5.0 Vdc

r-----112 MC15B2L

-,
I

I"" - ~/2-;:;C1;3;:- -~

S!
2

I

10

MDTl
OR
MTTl
INPUTS

I
I

I

2k
13

I

I
I
Zo

"2

-=
BALANCED
TRANSMISSION
LINE

7-341

12

I
I
I

L

.1

RECEIVER

I
I

2k

- - - - - - -1
. +5.0 Vdc

MOTl
OR
MTTL
OUTPUTS

•

MC1583L (continued)

APPLICATIONS INFORMATION (continued)
Hence the direct coupling of the driver and receiver to the line provides a built-in differential-mode noise immunity. The direct coup-

ances creating a voltage differential across the line. When either
driver transmits a logic "1", a voltage difference of the opposite
polarity is created across the Une. For a system with two drivers the

ling also matches the line at all frequencies (often a problem with
ac coupling lines). The recovery problem in ae coupling devices
at high-signal repetition ratas is also eliminated.
High input impedance of the MC1583L and high output imped·

current source (IS) can be supplied by a SOO-ohm resistor connected
to +5.0 Volts. If additional drivers are connected to the line, a
matching current source must be connected for each added driver.
The current sources are connected to the line so that when all drivers
are transmitting logic "O"s, the difference in current drawn from
the terminating resistors of the two wires in the twisted pair is equal
to one current source (8.6 rnA). The current sources should also
be connected so that when any driver transmits a logic"1" a current
difference of the opposite polarity exists. The matching current
source should be the companion circuit on the various driver chips.
The difference in amplitude of the current sources on a single chip
is specified to allow the system designer to calculate the maximum
current source mismatch, ~IOL, and hence the maximum number
of drivers that can be connected to a given transmission line.

ances of the MC1582L minimize impedance discontinuities on the
transmission line and allow many drivers and receivers to be

connected to the line.
Using MC1580L as a driver and MC1583L as the receiver in a
MRTL compatible transmission system is shown in Figure 14.
Use of the MC1583L in a bi·directional MOTL or MTTL com·
patible transmission system is shown in Figure 15. The MC1582L
drivers of Figure 15 are connected so that the current Sources from
both drivers pull current from the same wire of the twisted pair
when both drivers are transmitting logic "0" signals. The external
current source. IS. supplies the current required by one driver. The
current for the other driver is drawn from the termination imped-

FIGURE 14 - MRTL COMPATIBLE TRANSMISSION SYSTEM

r - - - - - ---,
I
I
112 MC1583l
I
I
DRIVER
I
I

r------I
I

1/2 MC1580l
DRIVER

z.
T

I

MRTl
lO'GlC

-=

z.
T
10

INPUT

640

r

I

I 13

1

0

I

I
I

I
I

MRTL
INVERTER

+3.6 Vdc

z.
T

1
1

L _______ .JI

z.
T

I
I
I
1
1
1

MRTL'
OUTPUTS

12

1i
640
I

L _____ .J

-=

+3.6 Vdc

FIGURE 15 - BI·DIRECTIONAL TRANSMISSION
+5 V

r------

I
1

2k

1/2 MC1583l
RECEIVER

120-<4.;.-1- - - - - : ; > , /

I

130-~"':"'----~

1

L ___ _

I

1
1 10

2k

_____ J 1

+5 V

r----------.,

-1

I

+5.0 Vdc

10

IS 8mA
rURRENT
SOURCE
2

I
I

2k

+ ......--012

'-.,,....----!..I

-=
~

112 MC1583l
RECEIVER·

2k
2.

T

1

L __ _

r- -

_ _ _ _ _ _ .1I

- ---,
I

\-1'----010

........_---1-----011

I

I

I
1

I

112 MC1582l

L ___

I

~R~~ __

J

7-342

MC1583L (continued)

APPLICATIONS INFORMATION (continued)
12 mV. External component R1 establishes an MDTL compatible
output signal.

The MC1583L has many other uses in a digital system. The
high input impedance suggests its use as a buffer for delay lines and
in waveform generation circuits. Figure 16 shows the MC1583L
used as a differential comparator in a double-ended limit detector.
When the input signal amplitude is between the two reference voltages, the output signal will be a logic "1"; otherwise a logic "0"
output is obtained. The voltage transition region is typically 8 to

VOLTAGE TRANSLATOR
Translation of voltage levels from MECL (best suited for the highspeed portion of a digital system) to MHTL (tailored for the noisy
output portion of the system) is often required. The MC1583L
performs this function as indicated in Figure 17.

FIGURE 16 - DOUBLE·ENDED LIMIT DETECTOR

,--------

+5.0 Vdc

-,
RI

2k

13
OUTPUT

LOW
10
VOLTAGE ...-----CI--+-----I
REFERENCE
12

LOW
VOLTAGE
REFERENCE

INPUT
VOLTAGE
MC15B3L
INPUT
+5.0 Vdc

OUTPUT
VOLTAGE
-0.7 Vdc

HIGH

I

VOLTAGE
REFERENCE

I

L_ - - - - - -

I
...J

FIGURE 17 - MECL TO MHTL VOLTAGE LEVEL TRANSLATOR
r-------

I
10
MECL
INPUT

112 MC1583L

I

13

12

Ii ...__-clll--_I~_

I

I
(
L ________ .J

7-343

I

I

\ . LINEAR/DIGITAL INTERFACE CIRCUITS

L---...-f

MC1584L

MONOLITHIC DUAL MDTL/MTTL RECEIVER
... designed with an active pull·up output that switches in response
to a differential input voltage. This silicon device is compatible
with the MDTL and MTTL digital logic families. Excellent common·
mode. input voltage range makes the device ideal for receiving digital
information in a noisy environment. The "totem·pole" output
(active pullup configuration) affords satisfactory response coupled
with power savings for operation with a small number of unit loads.
Typical applications include line sharing, voltage comparator, and
logic level translation.
• High Input Impedance - 7.0 k ohms@ 10 MHz typ

DUAL MDTL/MTTL RECEIVER
(ACTIVE PULLUP)
INTEGRATED CIRCUIT
MONOLITHIC SILICON
EPITAXIAL PASSIVATED

-

CERAMIC PACKAGE
CASE 632

TO·116

• Low Propagation Delay Time - 37 ns max

f::::::]

• Wide Common-Mode Input Voltage Range ±. 3.5 Volts min
• Device Compatibility with other Members of the Line Driver/
Receiver Series

(top view)

BLOCK DIAGRAM

OUTPUT
I

600

CIRCUIT SCHEMATIC

600

INPUT';"---=F-+~

6.0-1(.

,

L----~--~~----~----~~~CU~'~"~NT~------4-----4---~---4--~VEE
DlfFERfNTlAL GAIN

lEVEL

OIFFERENTIAl AMPLIFIER GAIN STAGE

INPUT AMPLIFIER

TRANSLATOR

WITH "TOTEM POtE" OUTPUT

SOURCE
REGULATOR-

Sea PackaginG Information Section for outline dimensions.

7-344

DIFFERENTIAL AMPLIFIEA GAIN STAGE

lEVEl

DIfFERENTIAL GAIN

WITH "'TOTEM -POLE" OUTPUT

TRANSLATOR

INPUT AMPLIFIER

MC1584L (continued)

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted)
Rating

Symbol

Value

Unit

VCC

+7.0

Vdc

VEE

-7.0

Vi"

±7.0

Volts

CMVin

±10

Volts

l/eJA

575
3.85

mW/oC

Operating Temperature Range

TA

-55 to +125

°c

Storage Temoerature Range

T stg

-65 to +175

°c

Power Supply Voltage

Differential-Mode I nput Signal Voltage
Common-Mode Input Signal Voltage

Po

Power Dissipation (Package limitation)

Ceramic Dual In-line Package
Derate above T A = +25 0 C

mW

ELECTRICAL CHARACTERISTICS (Each Receiver, VEE = +5.0 V, VCC = -5.0 V, TA = +25 0 C unless otherwise noted)
Characteristic
Operating Supply Currents

Figure

1

Min

Typ

Max

Unit

ICC

-

11.5

15

mA

lEE

-

25

31

-

Symbol

Input Leakage Current

1

IR

I "put Current

1

lin

TA
TA
TA

= -55°C
= +25 0 C
= +125 0 C

Output Voltage High (lOH
TA = -55°C
TA = +25 0 C
TA = +125 0 C

= -0.7

Output VOltgge Low (lgL
T A = -55 C to + 125 C

= 4.0 mAl

mAl

Output Short-Circu it Current

1

1
1

I "put Voltage Transition Width *

TA
TA
TA

Parallel Input Impedance If
Capacitance
Resistance

-

0.024
0.016
0.011

0.1
0.1
0.1

2.4
2.4
2.4

4.0
4.0
4.0

-

-

100

400

30

40

-

20
25
30

60
60
60

32
28
14
12

37
33

-

5.0
11

-

CMVRin

3.5
3.5

+4.3
-4.2

-

Volts

VCC

+4.75

+5.0

+6.0

Vdc

VEE

-4.75

-5.0

-6.0

Po

-

170

200

Volts

VOH

VOL
ISC

mV

2
tpd+
tpdtr
tf

mA
mV

-

Rise Time
Fall Time

J..IA
mA

-

Switching Times
Propagation Delay Time

0.1

-

VTR

= -55°C
= +25 0 C
= +125 0 C

0.009

-

ns

-

-

= 5.0 MHz)

Common-Mode I nput Voltage Range
T A = -55 to +125 0 C

Cplin)
Rplin)
3

Power Supply Operating Range

Power Dissipation
Ground all unused input pins to assure correct device biasing.
*Measured from points of unity gain.

7-345

-

pF
k ohms

mW

MC1584L

(continued)

CHARACTERISTIC DEFINITIONS
FIGURE 2 - TRANSIENT RESPONSE

FIGURE 1 - TERMINAL CURRENTS

ein: Ir and If =e,;;; 5 ns
All Ir and If measured 0.4 V to 2.4 V
All tpd+ and tpd- measured 50%10+1.5 V
+0.1 Vdc

+5.0 Vdc

= t-S_C-=----;+5=.0=Vl-d_C-+..:l~1 cc

ein
-0.1 Vdc

eout

eout

oVdc

- - -

I-j.\___~
tpd+

FIGURE 3 - COMMON·MODE INPUT VOLTAGE RANGE
+5.0 Vdc
ein

+0.10 Vdc

~ ~:"'~I OVdc

::J- - - L-0.l0VdC
Common'Mode Input Voltage
Range =' The Value of .li""'which
causes a 10% shift in the level of
eout or eout whichever occurs
first.

DlTI
0.1 "F

1k

I

eout eout

ein

-=-

7-346

-=

MC1584L

(continued)

TYPICAL CHARACTERISTICS

= +5.0 Vdc, Vcc =-5.0 Vdc, T A = +250 C unless otherwise noted)

(VEE

FIGURE 5 - OUTPUT VOLTAGE vers,.. DIFFERENTIAL
INPUT VOL TAGE AND TEMPERATURE

FIGURE 4 - OUTPUT VOLTAGE HIGH versus SUPPLY
OPERATING VOLTAGE ANO TEMPERATURE

vee' 'sao v~,.

11 ,,1 ,,7 ,,7 ,,7 ..7 ,1 J
,:·1
5.0

~

0

4.0

~

"
'"
;:
w

~
>

or
0

5.0

~
w

\\

2.0

>

,',. hE1

.,a"·''''''''

~f

V

"

I
1/

\

f-

:::>

0

.j 1.0

~

9.25

2.0

f-

~

\\

o
9.5

-55 0 e

0001

0

\\

>

9.75

+25 0 e

I~

-

3.0

'"«~

\\

1.0

'"

+125 0 e

0

\\

f-

0

-

I:""'' '

'42Vdc

g 4.0

3.0

:::>

:=:::>

I

-

-55 0 e +25 0 e

'"
«
0

100 ~

+125 0 C

1

'6.1 '~_~_~EF""
E:~
~1<

'U

500.)iVd<

9.0

8.75

8.25

8.5

8.0

7.75

Vee + VEE .SUPPLY OPERATING VOLTAGE (VOLTS)

-80

-60

-40

-20

1\

/,

l\\.

J1J
+20

+40

+60

+80

VTR. DIFFERENTIAL INPUT VOLTAGE (mV)'

FIGURE 6 - OUTPUT VOLTAGE versus DIFFERENTIAL
INPUT VOLTAGE AND VARIOUS LOADS

FIGURE 7 - OUTPUT VOLTAGE versus DIFFERENTIAL INPUT
VOLTAGE AND VARIATIONS IN NEGATIVE SUPPLY

VCC··5.DOV

2.0

~

1.5

\

0

1.0
0.5

o
-48

-36

-24

-12

3.5
3.0

'"

« 2.5
~
0

I

> 2.0
f-

-

:::>

:=:::>

1.5

0

N=4- .'i ~
rt
N=3 \
N=2 N= 1
Vv. )

:::>

oj

~

w

I

\

f-

f-

~0

I

\

w

•

4.5
4.0

"
~

1.0
0.5

+12

+24

+36

+48

0
-40

-30

-20

-10

+10

+20

VTR. DIFFERENTIAL INPUT VOLTAGE (mV)
VTR. DIFFERENTIAL INPUT VOLTAGE (mV)

7-347

+30

+40

MC1584L (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 9 - PROPAGATION DELAY
versus AMBIENT TEMPERATURE

FIGURE 8 - PROPAGATION DELAY versus
DIFFERENTIAL INPUT VOLTAGE

33
32

]
w

'"

31

~

30

;::
>c

z

0

~
:t
to

~
~

.!J-

~

29
28
27

\
\
\

34

\

\

33

~

32

>-

~

\
~

26
25
24
23
-0.4

~

+0.4

i""---

'" --+0.8

+1.2

tpd+_

tpd+

1

~

30

~

29

o

.......

.............

""'- r--

to

-

~

~

28
27

f...-tpf

~

.9-

tpd--

+1.6

+2.0

~

-

+2.4

f...--

V

26

See Figure Two
25

24
-75

+2.8

--

-25

-50

'in. DIFFERENTIAL INPUT VOLTAGE (VOLTS)

+25

+50

+75

+100

+125

TA. AMBIENT TEMPERATURE (DC)

FIGURE 10 - PARAL.LEL INPUT IMPEDANCE versus FREQUENCY

g

14 ,----,---,--"""'::---r-,--,---,---,,--,--,--,--,----,--

- 7.0
-

13r----+---t--+~-~~'''~-_+-1_~-+-1_+_---t_-

! :~ ~===:::~:::::t::~t~~~~~~~~$~~~l~;~~;~;:l=~:l::~c~p~(in~)~~t~=-=~=-=--t-!1
!2 !3 !
r----+---t-_+-1_~-t_-+_~-+,~~_+-----'=F=--..j;;==_-,
iii

9.0
:: 8.0
ii: 7.0

'~"
_

«a:
~

I'..

),5 ),6

),7~~~VdC

-

To *250B •

-

RXMeter

r-

== :::

!
;t

_ _

;3
4.0

~

3.0

'~_"

......... " . . . . . . . . . . . .

6.0

5.0 f---+--t--t-+-+-+--+-+--+-+-++--~""---R (
4.0
......... p in)

~

1----+---+-+--t-+--+----II--+-+--t-++---+--"'.......:tL-'--+--t-+--+---II--+-+--t~
...:-l 2.0
3.0
1__......
~-

«a:

:t.

~ 2.0~====:j=====t==:j==~~==t===t=~==~:j~=t=======t=====t===t==~:t::~::~;t~t::t:t~1.0
1.0 I-.~

a:

1.0

2.0

5.0

10
f. FREQUENCY (MHz)

7-348

20

50

100

MC1584L (continued)

APPLICATIONS INFORMATION
Line Driver/Receiver Familv Characteristics
The Motorola line driver/receiver series provides interface circuits for driving digital data transmission lines, e.g., coaxial cable or
twisted pair. The digital data transmission is via a balanced differential mode. The line drivers and receivers are designed to provide

The MC1584L in Figure 12 serves as the line receiver in a bal-

anced differential transmission line. The outputs of the receiver
and the inputs to the driver are compatible with MTTL and MDTL

circuits. The MC1584L contains an active pullup circuit in the

high common-mode noise rejection, present high impedances to the

output stage_ The MC1583L receiver can also be used for MTTL
or MDTL systems. The open collector outputs of the MC1583L

transmission line and have low propagation times. A feature of the
drivers is the capability to operate in a party-line mode whereby a
number of drivers can be connected to a single line. This series pro-

require external pullup resistors but is designed to sink up to 20 mAo
While common-mode noise is the major concern in a twisted
pair transmission line; a good data transmission system must offer
some immunity from differential-mode voltages that may be present
due to mismatches in termination impedances. The drivers and receivers of the MC1580 Series are designed with this requirement in
mind. The exact amount of noise immunity depends on line impedances but the following example shows how differential-mode
noise immunity is calculated for a given system. For a line with a
characteristic impedance of Zoo calculate the minimum differential
input voltage from the equation.

vides drivers and receivers compatible with MRTL. MDTL. MTTL
and MECL. The five circuits of the family are:
MC1580L
MC1581L
MC1582L
MC1583L
MC1584L

Dual
Dual
Dual
Dual
Dual

Line Driver/Receiver
MECL Receiver
MDTLlMTTL Driver
Receiver (Open Collector)
Receiver (Active Pullupl

Figure 11 indicates the line drivers and receivers recommended for
interfacing with each of the various digital logic families.
These five circuits are extremely useful in numerous applications
other than line drivers and receivers. The differential amplifier input of the receiver makes it useful in applications such as vOltage

10(minl x Zo

± Vin

= -=---4--=(6.91 (1701

For a 17O-ohm line. Vin

FIGURE 11

= - - - - = 0.29

Volts.

4

Digital Logic Family

Driver

Receiver

MECL

MC1580L

MC1581L

MDTL

MC1582L

MC1583L
MC1584L

MTTL

MC1582L

MC1583L
MC1584L

MRTL

MC1580L
MC1582L

MC1583L

Since the MC1584L requires a 50 mV maximum input differ-

ential to maintain the output state. the worst case differential-mode
noise immunity is 0.26 V. (See Figure 131.
High input impedance of the MC1584L and high output imped-

ance of the MC1582L minimize impedance discontinuities on the
transmission line and allow many drivers and receivers to be connected to the line.

comparators, waveform generators and high-input·impedance buffers. The drivers and receivers are useful as logic level translators.

FIGURE 12 - MDTL. MTTL COMPATIBLE TRANSMISSION SYSTEM

r------I
111 MCI581L

I
MOTL

MOll

I

OR

M~~l

11

40----'---j
INPUTS 50----'---i

IL

MTll

/''''-------'-0---.... '0 OUTPUTS

I
I

DRIVER
___
___ _

..J
BALANCED
----TRANSMiSSiON - - - - - \
LINE

7-349

•

MC1584L (continued)
APPLICATIONS INFORMATION (continued)

are transmitting logic "O"s, the difference in current drawn from
the terminating resistors of the two wires in the twisted pair is equal
to one current source (S.6 rnA). The current sources should also
be connected so that when any driver transmits a logic "'" a current
difference of the opposite polarity exists. The matching current
source should be the companion circuit on the various driver chips.
The difference in amplitude of the two current sources on a single
chip is specified to allow the system designer to calculate the maximum current source mismatch, Il.IOL. and hence the maximum
number of drivers that can be connected to a given transmission line.
The MC1584L has many other uses in a digital system. The
high input impedance suggests its use as a buffer for delay lines
and in waveform generation circuits.

Use of the MC1584L in a bi-directional MDTL or MTTL compatible transmission system is shown in Figure 14. The drivers of

Figure 14 are connected so that the current sources from both
drivers pull current from the same wire of the twisted pair when
both drivers are transmitting logic "0" signals. The external current
source, IS. supplies the current required by one driver. The current

for the other driver is drawn from the termination impedances

creating a voltage differential across the line. When either driver
transmits a logic "1", a voltage difference of the opposite polarity
is created across the line. For a system with two drivers the current
source liS) can be supplied by a 600-ohm resistor connected to
+5.0 Volts. If additional drivers are connected to the line. a matching current source must be connected for each added driver. The
current sources are connected to the line so that when all drivers

FIGURE 13



Vee

Vee
SWITCHING CHARACTERISTICS (CL = 1000 pF)
Symbol

Min

Typ

Max

Unit

tTLH

-

55

75

ns

tr

-

50

75

ns

lTHL

-

25

50

ns

tf

-

22

50

ns

Pulse Repetition Rate

PRR

0

-

2.0

MHz

Peak Output Current

IO(peak)

-

400

500

mA

Characteristic
Propagation Delay Time before Rise Time
Rise Time

Propagation Delay Time before Fall Time
Fall Time

Symbols conform to JEDEC Engineering Bulletim No.1 when applicable .
The above characteristics were measured with VCCl = 5.0 volts, VEE = -20 volts, VCC2 = 0 volts, CL = 1000 pF (with a 10-ohm series
resistor). The minimum values and maximum values apply from -55°C to +125 0 C. Typical values are for TA = 25°C. The transition times are
measured as shown in Figure 5 and 6.

FIGURE 5 - SWITCHING TIME WAVEFORM

FIGURE 6 - AC TEST CIRCUIT

2'4vmin~____1.5V---0.4 V max

I

I
'THL ---1

VOH

I

r--

tTLH-t----j I,

~ If f-I
90%
I

I
I

I
I
I
I

I--

i

I

7-352

MC1585L (continued)

ELECTRICAL CHARACTERISTICS
!TA

==

TEST CURRENT AND VOLTAGE VALUES

+2SoC unless otherwise noted I

Function

Currents

Symbol

'DH
'DL
rnA

V,L

-1.0

1.1

I

Unit

Pin

Value

Test

Min

TVp

Max

Unit

IlL

8

rnA

8

-

-1.6
+50

Output Voltage: High Output

"H
VOH

-

7

+3.7

-

Low Output

VOL

7

-

-

"A
Volts

-13.4

Volts

High Output

ICC1H

12

10

rnA

Low Output

'CC1L

12

7.0

rnA

VeE High Output

'EEH

11

25

rnA

Vee

'EEL

11

64

rnA

VCC2 High Output

'CC2H

4

15

rnA

VCC2 Low Output

ICC2L

4

57

rnA

Revers~

Supply Current

Vee1
Veel

Leakage

Low Output

Supply Voltages

IVCC1L I VCC1H I VEE

V,H

VCC2

Volts

+1.0

4.5

1.78

5.5

-15

+5.0

Test Limits

Under
Symbol

Characteristic
Input Currents: Forward

Input
Voltages

Load

(Pin 2 is shorted to pin 3 and pin 5 is short·
ed to pin 6.1

-

-

-

-

TEST CURRENT/vDLTAGE APPLIED TO PINS LISTED BELOW:

-

GND

8

9

-

12

11

4

10

-

8,9

-

12

11

4

10

7

--

8

9

12

-

11

4

10

-

7

-

8,9

-

12

11

4

10

8,13

9,14

12

11

4

10

-

8,9,13,14

12

11

4

10

8,13

9,14

12

11

4

10

-

-

8,9,13,14

12

11

4

10

-

8,13

9,14

12

11

4

10

8,9,13,14

12

11

4

10

-

-

-

-

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

TYPICAL CHARACTERISTICS
FIGURE 7 - PACKAGE LIMITATION ON POWER DISSIPATION

2.0
I.B

~

:;:

1.6

~ 1.4

...........

z

~ 1.2

..............

...........

~
~ 1. 0

.................

~ 0.8
~ 0.6

-............

~

~

...........

0.4

r--......

0.2

o
-55

-35

-15

+5.0 +25
+45 +65
+B5 +105
TA, AMBIENT TEMPERATURE lOCI

3:

io

~
~

C

a:

~
~

~

VEE - 0 VOltl

200

I

IBO

VCCI 5,5 V
VCC2 -Independent

11 0

~EE -~5Voltl-

10 0
90

VEE - -20 Volts

.sz

-15 Volts

~

0

VEE

0
0
0
0
0

3:

~ 120

~EE jlo vOlll

+5.0
+25
+45 +65
+B5 +105
TJ, JUNCTION TEMPERATURE lOCI

I--- r-

-

I I

~

~-25IV
VE1E= _201V
VJE = _Isiv

~

BO

vJP

60

I

~

+125 +145

7-353

1

VCCI = 5.5)

-- r---r---

VCC2 '" Independent

I--

r--

I--

a: 100

~

-15

- --

C

VEE = -5,0 Vails

-35

t---

160

0
;:: 140

0

0
0
-55

+145

FIGURE 9 - MAXIMUM DIFFERENTIAL LEVEL SHIFT
POWER DISSIPATION (At least one input low)

FIGURE 8 - MAXIMUM DIFFERENTIAL LEVEL SHIFT
POWER DISSIPATION (WITH BOTH INPUTS HIGH)
140
13 0
12 0

+125

--=

_IOlv

I

VEE = -5.0 V

40

-55

-35

-15

+5.0 +25
+45
+65
+B5 +105
JC, JUNCTION TEMPERATURE lOCI

+125 +145

I

MC1585L

(continued)'

TYPICAL CHARACTERISTICS (cant.)

FIGURE 11 - MAXIMUM POWER DISSIPATION OF
INTERNAL RESISTOR (R31

FIGURE 10 - MAXIMUM BIAS CURRENT versus VOLTAGE AND
TEMPERATURE WHEN USING INTERNAL BIAS RESISTOR
8.0

vLI 1v-

7.0

;r:

6.0

S
~ 5.0

'"'"
a

4.0

= 5. 5

---

(VCC2 - VEE) = 20 V

Ifcc::tt=

r-- r---

IJ CC1 - EE ) = ~.o V

J

1.0

-55

§<

S
2:

8.0
7.0

0

;=

:;;on

on

0

'"

w

'~"

6.0
5.0

r--

-35

- 15

+5.0 +15
+45
+65
+85
TJ, JUNCTION TEMPERATU RE lOCI

+105

+115 +145

-....... -....

----

4.0

-

;--

3.0

-....... -....... 'b,·s<)O

~"80. "'A

,

IVc'C2 - VJEI = 10 V

IV~C2 - V~E) = 56 V

I--

~

r-- r---:.

bi" = 4.0 rnA

~ 2.0

lbias -

1.0

I

o
-55

I/bi,,=L- r--

-35

-15

J.o rnA

r--

§<

'"

500

~

450
400

~

-..... -....

-- r---r--

~

~
~o..

t--

I

+5.0
+25
+45
+65
+85
TJ,JUNCTION TEMPERATURE (DC)

-35

700
650 I 600
550

S

-.... t--..

-15

+5.0
+15
+45 +65
+85
TJ, JUNCTION TEMPERATURE (DC)

+105

+125 +145

~

--5~OC < iJ < +12 5 C
1 0

'0<:>
\'00;

\\)

350
300

./'

150
20 0

/'
./

150

100
50

+115 +145

V

V

2.0

4.0

6.0

/"

;....----

--

% V

~
~

+105

-

FIGURE 13 - POWER DISSIPATION OF OUTPUT CURRENT
OF ACTIVE PULLUP versus BIAS CURRENT versus VOL TAGE

I I

I~

-

IvJC2 - VJE)- 15 V

-55

FIGURE 12 - MAXIMUM BIAS POWER DISSIPATION IN 09,
010 (INDEPENDENT OF OUTPUT STATE I
10

~ - VEE) ='20 V

o

o

9.0

-

r---

~

IVCC2 -VEE) - 10 V

:c 1. 0

v~cI=5dv-

:;;

on

~ 3.0

140
130
110
§< 110
S
2: 100
0
;= 90
80
on
on
70
0
60
'" 50
40
~ 30
10
10

<$'~./'

/'

~~tr

."X:..

V,,,,,,' _~~<$'y
./ \Ii",;::r-

..-

-

8.0
10
11
IVCC11- (VEE) IVO LTSI

\bia!'.

/

.v
V

:lb~

14

16

18

10

APPLICATIONS INFORMATION
The total power dissipation in the MOS clock driver is the sum
of a de and an ac component. The total of these components must
not exceed the package power dissipation limit at the maximum
temperature of operation. The package limitation on power dissipation is shown in Figure 7.
AC Power Dissipation

Differential level Shift Power
In Figure 1 it may be seen that the differential level shift consists
of the input PNP transistors, 01, Q2, 03, and bias resistor, R1. The
values of maximum level shift power versus junction temperature
are given in Figures 8 and 9 for several values of VEE and both
input conditions. If the duty cycle is defined as in equation 2, the
total level shift power is given in equation 3.

The ac component of power dissipation is given in equation 1.
Duty

(11
where CL is the load capacitance and PRR is the pulse repetition rate.
DC Power Dissipation
For ease of calculation, the dc power dissipation is divided into
two parts:
1) differential level shift power 2) output pullup
current source power.

,7-354

C
Time Both I nputs are High
ycle =
Total Time

Level Shift Power = IValue from Figure 81. 11·Duty Cycle)+
IValue from Figure 9)' (1·Duty Cycle)

121
(31

Output Pullup Current Source
The output pullup current source consists of transistors Q9, 010
and resistor R3. The power dissipated in the output pullup current

MC1585L

(continued)

APPLICATIONS INFORMATION (continued)
source depends upon temperature, supply voltages, bias current
drawn from the collector-base short of transistor 010 and output
logic level. Neglecting the emitter-base drop of transistor 010 the
value of bias current is determined from equation 4.
118= VCC2- V EE
(4)
R3
If the internal bias resistor is used the maximum value of bias
current versus temperature is as shown in Figure 10. The maximum
power dissipated in the internal bias resistor and the maximum
power dissipated in 09 and 010 (due to bias current) are
independent of output logic level and are shown in Figures 11 and
12. The maximum power dissipation due to collector current in
09 is approximately zero when the output is high but when the
output is low the power dissipation is as shown in Figure 13. The
total output pullup current-source power dissipation is thus
defined by equation 5.
P(max) current source::; (Value from Figure 11) + (Value from
Figure 12)
(5)
+IValue from Figure 13)xlDuty Cycle)
Example Calculation
Suppose it is desired to use the MOS clock driver in an application
which requires the following:
VCC1 = +5.0 volts
VEE = -15 volts
VCC2 = +5.0 volts
PRR = 1.0 MHz
Duty Cycle = 0.1 %

Load capacitance, 500
pF @ TAlmax) +70 0 C

A calculation of dc and ae power is necessary to find whether or
not package limitations will be exceeded. Since each power dissipation figure either deciesases or remains constant with temperature,
it is assumed that TJ ~ +25 0 C and points at +25 0 C will be used in
this calculation. The total differential level-shift power may be
found from Figures 8 and 9 and equation 3 to be:
Level-Sh ift Power

= 92.5 mW

If the internal bias resistor is used, Figure 10 shows the value of
the bias current to be 4.9 rnA, and the power dissipation of the
internal bias resistor is found from Figure 11 to be 90 mW.
The power dissipation in 09 and 010 due to bias current is
found from Figure 12 to be 4.0 mW.
The power dissipation in 09 when the output is low is found
from Figure 13 to be 490 mW.
The total power dissipated in the output pullup current source'
can now be found from equation 5 to be:
Power (current source) ::; 143 mW
The total dc dissipation, the sum of differential level-shift dissipation and output pullup current-source dissipation, is 235.5 mW.
The ac dissipation may be found from equation 1 to be 200 mW.
The total power dissipation for one clock driver is thus 435.5
mW. If both clock drivers are used in an identical fashion the
total package dissipation is 871.mW. Referring to Figure 7 it is
seen that safe operation to approximately +45 0 C is possible.
If external resistors are used for R3 to produce the same bias
current as above, a net total savings in power dissipation of 180
mW can be made reducing the total package dissipation to 691 mW
and permitting safe operation at +70 0 C.

I

7-355

I

'\

HIGH-FREQUENCY CIRCUITS

'--"-------------'

MC1590G

WIDEBAND AMPLIFIER
WITHAGC

MONOLITHIC RF/IF/AUDIO AMPLIFIER
· .. an integrated circuit featuring wide-range AGC for use in RF/IF
amplifiers and audio amplifiers over the temperature range, - 55 to
+125 0 C. See Motorola Application Note AN·513 for design details.

SILICON
EPITAXIAL PASSIVATED

• High Power Gain - 50 dB typ at 10 MHz
45 dB typ at 60 MHz
35 dB typ at 100 MHz
• Wide· Range AGC - 60 dB min, dc to 60 MHz
•

Low Reverse Transfer Admittance -

METAL PACKAGE
CASE 601

<10 j.lmhos typ at 60 MHz

TO·99

• 6.0 to 15·Volt Operation, Single-Polarity Power Supply

~
8

(bottom view)

FIGURE 1 - UNNEUTRALIZED POWER GAIN versus FREQUENCY
ITuned Amplifier, sea Figure 161
0

FIGURE 2 - VOLTAGE GAIN versus FREQUENCY

rVcc"IZVdc
0

,
,

0
0

"

0

Amplifier, see Figure 17)

II 111111
II 111111
VCC~UVdc

.......

0

~Vid80

0

,
Rl-l.Dkfl

"

0

0
20

10

50
f. FREOUENCY (MHz)

CIRCUIT SCHEMATIC

100

11111

200

Rl"l00n

Vee

~\
I\,

1111
1111

0

RL-l0n

1

,.

0

,.I

1.5k

10

100

1000

f,FREQUENCY(NHzl

5.5Jr.

12.lk

FIGURE 3 - TYPICAL GAIN REDUCTION
1+)5

versusAGC VOLTAGE

,
,

.

5.6.
Uk

I.1k

'-

'" .~~
" RAGeT

,
,
,

S.Ok

5.0k

~

C-

I'\AGC-l00kn
RAGC"S.8kn

RAGe·On

1\

\

,

B.4k

80
3.0
Pins 4 Ind 8ilhould bOlh be connectld to cin:uit ground.

Subslllli

See Packaging Information Section for outline dimensions.
See MCBC1590/MCB1590F for beam-lead device information.

7-356

8.0

9.0

12

15

18

21

VAGC. AGC VOLTAGE IVdcl

24

27

30

MC1590G (continued)

MAXIMUM RATINGS ITA = +25 0 C unless otherwise noted)
Rating

Symbol·

Value

Unit

VCC

+18

Vde

Output Supply

V5,V6

+18

Vde

AGCSupply

VAGC

VCC

Vde

Yin

5.0

V_de

Po

680
4.6

mW
mW/oC

TA

-55 to +125

T stg

-65 to +150

°c
°c

Power Supply Voltage

Differential I nput Voltage
Power Dissipation (Package Limitation)

Derate above T A = +250 C
Operating Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC =+12 Vdc, f = 60 MHz, BW = 1.0 MHz, T A
see Figure 16 for test circuit.)
Symbol·

Characteristic
AGC Range, V2 = 5.0 Vde to 7.0 Vde

=+25 0 C unless otherwise noted,

Min

Typ

Max

Unit

60

68

-

dB

Single-Ended Power Gain

Gp

40

45

Noise Figure

NF

-

6.0

-

14
6.0

-

-

7.0
3.0

-

dB

dB

(Rs = 50 ohms)
Output Voltage Swing (Pin 5)
OdBAGC
Differential Output
-30dB AGC
Single-Ended Output -

V p _p

V5

-

OdB AGC
-30 dB AGC

-

15 + 16

-

5.6

-

rnA

Total Supply Power Current
(Vo=O)

10

-

14

17

mAde

Power Dissipation (Vin = 0)

Po

-

168

200

rnW

Output Stage Current (Pins 5 and 6)

·Symbols conform to JEOEC Engineering Bulletin No.1 when applicable.

ADMITTANCE PARAMETERS (Vee - +12 Vd., TA - +2S·CI

SCATTERING PARAMETERS (VCC - +12 Vdc, TA - +25.C,
Z.-501l1

Typ
Parameter
Single-Ended Input
Admittance
Smgle-Ended Output

Admittance
orward

rans er

Admittance (Pin 1 to Pin 51

Reverse Transfer
Admittance·

Symbol

'''30MHz

gIl
bll
g22
b22
21
821
g12
b12

0.4
1.2
0.05
0.50

~;~
-0
-5.0

'·60MHz
0.75
3.4
0.1
1.0
150
-105
-0
-10

Unit

Paramater

mmhos
mmho

Input Raflection Coefficient
Iuutput Reflection

mmhos
degrees

J.lmhos

Coefficient
Forward Transmission
Coefficient
"BVerse ransmlSSlon
Coefficient

-The val ... e of Reverse Transfer Admittance Includes the feedback admittance
of the test circuit used in the measurement. The total feedback capacitance
(including tast circuit) is 0.025 pF and Is a more practical valu. for design
calculations than the Intarnal feedback of the d.... lc. alone. (See Figure 6)

7-357

Svmbol

"'111
8"
"'22

"22
18211
"21
S12
812

Typ
I z 30MHz t-60MHz
0.95
0.93
-7.3
-16
0.99
u.9~
-3.0
-5.5
16.8
128
U.U0048

84.9

14.7
64.3

Unit
dog....
degrees
dog....

u."""'"
79.2

degrees

•

MC1590G (continued)

TYPICAL CHARACTERISTICS
(Vce = 12 Vdc, TA = +2Soe unless otherwise noted)
FIGURE 4 - FIXED TUNED POWER GAIN versus
TEMPERATURE (See test circuit, Figure 161

FIGURE 5 - POWER GAIN versus SUPPLY VOLTAGE
(See test circuit, Figure 161

BO

BO

70

70

'<1z"'

"'a:

30

~

Q.

'"

./

.ff

,....;-

30

20

20

10

10

Y

-25

+25

+50

+75

+100

+125

'/

1

'/

I

o
-50

V

Ap

40

~

-75

Jo MHz

50

40

~

60

z
<1

50

'"
'"~

f=

.,

60

iii

24

o

+150 +175

2.0

4.0

TA. AMBIENT TEMPERATURE [OCI

6.0

B.O

10

12

14

FIGURE 6 - REVERSE TRANSFER ADMITTANCE versus
FREQUENCY (See Parameter Table, page 2 of MC1590 specification I

FIGURE 7 - NOISE FIGURE versus FREQUENCY

-0 -50

10

]

9.0

/'

w

~ -40

.,

~;;;

'a:"'

L

'"w
~

/

-20

0-

-

~
a:
~

B.O

./

7.0

--

w

~ -30

'"z~
~
N

-I--

;:

30

10

"i,.V

::>

6.0

"'u:w

5.0

'"
i5

4.0

z

/'

~.

z

n

-10

3.0

1.0
100

15

200

20

25

30

,/

2.0

.§
w
z

/'b22_

..,

0-

1:1

>-

V

1.5

1.0

0.5

60

70 80 90 100

150

FIGURE 9 - SINGLE·ENDED INPUT ADMITTANCE

./'

/'

--

20

..-

r---

B.O
7.0

;;;

5.0

.§

~

./

/'
/"

-

'E

..,wz

/'
/ ' / bll -

6.0

i-'"

c

V

40

9.0

'i1

/

c

50

10

'i1

::>

35 40

f. FREQUENCY [MHz)

FIGURE 8 - SINGLE·ENDED OUTPUT ADMITTANCE

I!:
::>

V

912 ~O

2.5

«
00;;;
C
«

./

V

2.0

f. FREQUENCY [MHzl

'E

16

VCC. POWER SUPPLY VOLTAGE [Vdc)

,/

« 4.0
0..:

g2r-

;:

-

2.0

~

1.0

I-100

20

200

f, FREQUENCY [MHz)

......

....... ..........

40

/"

,. . . . ., gll100

f. FREQUENCY (MHz)

7-358

/

...... 1/'

~
:!: 3.0

200

MC1590G (continued)

TYPICAL CHARACTERISTICS (continued)

FIGURE 10 - Y21, FORWARD TRANSFER ADMITTANCE,

FIGURE 11 - Y21, FORWARD TRANSFER ADMITTANCE,

RECTANGULAR FORM

13

200

~ 160

.sw
u

z

~

~
-

I/" ......

r....

:t -160

~

w

1

t- IY2':

~u

1\

.......

~ -40

.

~ ~140

1\
b21

;;

"

+45

'21

'80

~ ~'GO

'\

80
40

~

POLAR FORM
200

'\.. -3GO~

'0

20

50

'00

-405
200

f. FREUUENCY (MHz)

FIGURE 13 - S11,and S22, INPUT AND OUTPUT
REFLECTION COEFFICIENT

FIGURE 12 - S11 and S22, INPUT AND OUTPUT
REFLECTION COEFFICIENT

•
7-359

MC1590G (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 15 - S12. REVERSE TRANSMISSION
COEFFICIENT (FEEDBACK)

FIGURE 14 - S21. FORWARD TRANSMISSION
COEFFICIENT (GAIN)

TYPICAL APPLICATIONS
FIGURE 17 - VIDEO AMPLIFIER

FIGURE 16 - 60-MHz POWER GAIN TEST CIRCUIT

C4

.--.. . _·0

l2
Input
(50n)

1.0 k

VAGC
CI
-~~

_ _ _""_ _ +12Vdc
0_001

~F

VAGC
II =7 Turn•• #20 AWG Wire. 5116" Oi._,
5/B"long·
l2 = 6 Turns, #14 AWG Wir., 9116" Di•. ,
3/4" long

CI,C2,C3 = (I-3~) pF
C4=(I-IO)pF

0.001 ~F +12 Vdc

FIGURE 18 - 3D-MHz AMPLIFIER
(Power Gain = 50 dB. BW '" 1_0 MHz)

FIGURE 19 - 100-MHz MIXER

Input from
local Oscillator
(70 MHz)
100

TI

(I-30)pF

:;~~) -ll~-+--""+---.+

(1·101 pF

0.002.F

r r~
IO.H

T2: Primary Winding = 10 Turns, #22 AWG Wire, 1/4" 10 Air Core

T1: Primary Winding = 15 Turns, #22 AWG Wire, 1/4" 10 Air Core
Secondary Winding = 4 Turns, #22 AWG Wire,

Secondary Winding = 2 Turns, #22 AWG Wire,
Coefficient of Coupling;::= 1.0

Coefficient of Coupling ~ 1.0

FIGURE 21 - SPEECH COMPRESSOR
Audio

AGe

Input

e---------~----~--~~--~~~---------10 k

___ vee

10 k

5.6 k
200

I.O.F

........:::---<>-.....-f----Ul·- -....... ~~~!~t

Microphone

llO.F

+
1.0.FI

7-361

~f

~~___________________M_U_L_T_I_P_L_IE_R__~

MC1594L
MC1494L

Specifications and Applications InforITIation
MONOLITHIC FOUR-QUADRANT MULTIPLIER
· .. designed for use where the output voltage is a linear product of
two input voltages. Typical applications include: multiply, divide,
square root, mean square, phase detector, frequency doubler, balanced
modulator/demodulator, electronic gain control.
The MC1594/1494 is a variable transconductance multiplier with
internal level·shift circuitry and voltage regulator. Scale factor, input
offsets and output offset are completely adjustable with the use of four
external potentiometers. Two complementary regulated voltages are
provided to simplify offset adjustment and improve power·supply
rejection.

LINEAR FOUR-QUADRANT
MULTIPLIER INTEGRATED
CIRCUIT
MONOLITHIC SILICON
EPITAXIAL PASSIVATED

• Operates With ± 15 V Supplies
• Excellent Linearity - Maximum Error (X or V): ± 0.5% (MC1594)
± 1.0% (MC1494)
• Wide Input Voltage Range - ± 10 volts
• Adjustable Scale Factor, K (0.1 nominal)
• Single· Ended Output Referenced to Ground
• Simplified Offset Adjust Circuitry
• Frequency Response (3 dB Small·Signal) - 1.0 MHz
• Power Supply Sensitivity - 30 mV!V typical

(top view)

CERAMIC PACKAGE
CASE 620

TYPICAL LINEARITY ERROR
versus TEMPERATURE

FOUR·QUADRANT
MULTIPLIER TRANSFER CHARACTERISTIC

100,---,---,-----,--,---,.---,----,
~ +6.0 I-.::---,f-~.....-I

~

~ +4.0 r----;p-....j;::-~,,-j---l
~ +2.0 r-=i:::::,-1--'1"'-<02'1...--t-7i's"...-f'---~
o

~ 0.50 f - - - t - - - - j - - - - t - - + - - - j - - - t - - - - j

>

z

~ -1.0f-=F=i---jr~L-+-~~...J:,---;

5....

0.751---t---1----j---j----+---t------1

~

,......

w

-4.Of-----1b...-""j'---"""71"'---j---t---t--"Io..,-

;:-....~I--~

"~
~

-----r---~~--~--_+---+--~
0.25 f----f----j---+--+--+---f----j

;;:

w

-4.0

-2.0

+2.0

°5L5--~-2L5--~--+~25,---~+5~0--+775~-+~1~OO,---+~1~25

+4.0

TA. AMBIENT TEMPERATURE (OC)

VX.INPUT VOLTAGE (VOLTS)

CONTENTS
Subject Sequence

Specification
Page No.
Subject Sequence

Specification
Page No.

Maximum Ratings

AC Operation

Electrical Characteristics

DC Applications

9

AC Applications

11

Test Circuits

3

Characteristic Curves

4

Circuit Description

Circuit Schematic

5

DC Operation

6

8

Definitions

13

General Information Index

14

Package Outline Dimensions

14

See Packaging Information Section for outline dimensions.

7-362

MC1594L, MC1494L

(continued)

MAXIMUM RATINGS IT A = +2SOC unless otherwise noted)

Rating
Po .....er Supply Voltage

Differential Input Signal

Symbol

Value

Unit

V+
V-

+,B

Vd,

Vg-VS

± 16+1, Ayl<30
± 16+1, Rxl<30

VlO-V ,3

-'B
Vd,

Common-Mode Input Voltage

Vd,

VCMY" Vg = Va

VCMY

VCMX = V,0 = V,3

VCMX

POVller Dissipation (Package Limitation!
TA=+250C
Derate above T A = +2SoC

Operating Temperature Range

±11.5
±11.S
750
5.0

Po
1/0JA

mW
mW/oC
DC

TA
-5510+125
Oto + 75

MC1594
MC1494

Storage Temperature Range

Tst9

DC

-65 to +150

ELECTRICAL CHARACTERISTICS IV+" +15 V, V- =-15V, TA"
unless otherwise noted)

+25 0 C,

A1 = 16 kil, AX = 30 k1!. Ry" 62 kH. RL '" 47 kH,
MC1594

Characteristic

Fig.

Linearity
Qutputerror in Percent of fuJI scale
-10 V----::-..... V.

+---,-e..,

Vy __

7k
-15V
4

-

20k

,8.2k
Vyofl

10k

V,·.~,,~--------~r---~50k
Voalf

FIGURE 5 - FREQUENCY RESPONSE

Vx

FIGURE 6 - COMMON·MODE

I-<>_----........ V.

-15V

47k
Rl

S.H

S.H

FIGURE 7 - POWER·SUPPLY SENSITIVITY

FIGURE 8 - BURN·IN

Vin,,+10V

(MC1594 - Pg. 3)

7-364

MC1594L, MC1494L (continued)

TYPICAL CHARACTERISTICS
(Unless otherwise noted, V+ =+15 V, V- =-15 V, R1 = 16kn, RX =30kn, Ry =62 kn, RL =47 kn, TA =+25 0 C)
FIGURE 9 - FREQUENCY RESPONSE OF Y INPUT
versus LOAD RESISTANCE

FIGURE 10 - FREQUENCY RESPONSE OF
X INPUT versus LOAD RESISTANCE

+15
1

+10

~I~I= I k~

RILl ~ IIIJ k!! I....

~ +5.0

?~

z
;;:

RL=33k!l

to
w

b\

>
i= -5. 0

~

10 5

104

II,r

-20
10 3

107

106

Vx = I V(rmsl. Vy = 10 Vdc
RX = 30 kll, Ry = 62 kll

-I 5

_20'-::----'--l-l..1ilIIIlll:-rDI=6--'---lPII--U.JIII.I..LU.;-IIIII---'--'-I...J.~~
103

1"-.....

-10

Vy = 1 Vlrmsl, Vx = 10 Vdc
-151---++++1 RX = 30 k!l, Ry = 62 kll -+-+++ttH+--+-++++tttt

6P

FIGURE 12 - LINEARITY versus RX OR Ry WITH K

o. 6

to;

0.1

~

c

E

r--

..........

r-

20

30

40

50

RX Ikn)

40

60

80

100

Ry (k-----~--+~

~

-VR=-4.3V

V-

5,o---~~~~--+-------T-----~~----~------~----~

______~----------~

l5,o-~~----~r---~~~~tT----------~----------------------------~r_------~~r_----t_--_;
V'

COMPLETE CIRCUIT
SCHEMATIC

GN0 3

500

V-O-~~~

__+-~~~---4~~--_-_--_--_-_~_--_-_~_--_-_--_--_-_~__
~_--_._--_-_--_-~~--------~

REGULATOR

MULTIPLIER

(MC1594· Pg ..5)

7-366

OIFFERENTIAL
CURAENTCONVERTER

MC1594L, MC1494L (continued)

1.2

Regulator IFigure 15)
or

The regulator biases the entire MC1594 circLiit making it
essentially independent of supply variation. It also provides

2VXVy
10" RXRyll

two convenient regulated supply voltages which can be used
in the offset adjust circuitry. The regulated output voltage
at pin 2 is approximately +4.3 V while the regulated voltage
at pin 4 is approximately -4.3 V. Foroptimum temperature
stability of these regulated voltages, it is recommended that

The output current can be easily converted to an output
voltage by placing a load resistor R L from the output (pin
14) to ground (Figure 17) or by using an op-ampl. as a
current-to-voltage converter (Figure 16). The result in both
circuits is that the output voltage is given by:

1121 " 1141 " 1.0 mA (equivalent load of 8.6 kQI. As will be
shown later, there will normally be two 20 k-ohm potenti-

ometers and one 50 k-ohm potentiometer connected between
pins 2 and 4.
Vo"

The regulator also establishes a constant current reference that
controls afl of the constant current sources in the MC1594.
Note that all current sources are related to current 11 which
is determined by R 1. For best temperature performance,
R1 should be 16 kn sothat '1 ~ 0.5 mA for all applications.
1.3

2RL Vx Vy
RXRyll "KVX Vy

where K (scale factor!

=

2RL
RXRyll

Multiplier (Figure 15)
The multiplier section of the MC1594 (center section of
Figure 15) is nearly identical to the MC1595 and is discussed
in detail in Application Note AN-4S9, "Analysis and Basic
Operation of the MC1595". The result of this analysis is
that the differential output current of the multiplier is given
by:

2.

DC OPERATION

2.1

Selection of External Components
For low frequency operation the circuit of Figure 16 is
recommended. For this circuit, RX = 30 kfL Ry = 62 kD.,
R 1 = 16 kn and hence 11 ~ 0.5 rnA. Therefore, to set the
scale factor, K, equal to 1110, the value of RL can be calculated to be:
1

2RL

K"-"--10

Therefore, the output is proportional to the product of the
two input voltages.
1.4

RXRyll

RXRyll

or

Differential Current Converter (Figure 15)
This portion of the circuitry converts the differential output
current (I A-I B) of the multiplier to a single·ended output
current (10):

RL"

I2iIiOI "

(30 kl 162 kllO.5 mAl
20

RL "46.5 k
Thus, a reasonable accuracy in scale factor can be achieved
by making R L a fixed 47 kD. resistor. However, if it is desired

FIGURE 16 - TYPICAL MULTIPLIER CONNECTION
t15 V

-15 V
Rl
~
5Dk
22k

1

Vx

P4

1O PF

R1

R'

510

16k

30 k

10pF

Vy

"]

>-o---+-..... Vc

R'

510

PI

20k

0.'"F1
t15 V
-15 V
Vo"-VXVy
10
·A

IS

not

-10V,,;VX<+lOV
-10 V,,; Vy';;;+l0 V

MC1594 - Pg. 6)

7-367

•

MC1594L, MC1494L (continued)

offset voltage can be adjusted to zero (see offset and scale
factor adj ustment procedure).
The input offset adjustment potentiometers, P1 and P2 will
be necessary for most applications where it is desirable to
take advantage of the multiplier's excellent linearity characteristics. Depending upon the particular application, some
of the potentiometers can be omitted (see Figures 17. 19,

that the scale factor be exact, AL can be comprised of a
fixed resistor and a potentiometer as shown in Figure 16.
It should be pointed out that there is nothing magic about
setting the scale factor to 1/10. This is merely a convenient
factor to use if the Vx and Vy input voltages are expected
to be large, say ± 10 V. Obviously with Vx = Vy = 10 Vand
a scale factor of unity, the device could not hope to provide
a 100 V output, so the scale factor is set to 1/1 Oand provides
an output scaled down by a factor of ten. For many applications it may be desirable to set K = 1/2 or K = 1 or even
K = 100. This can be accomplished by adjusting RX. Ry

22, 24 and 251.

2.5

The adjustment procedure for the circuit of Figure 16 is:

and RL appropriately.
The selection of R L is arbitrary and can be chosen after
resistors RX and Ry are found. Note in Figure 16 that Ry
is 62 kn while RX is 30 kn. The reason for this is that the
"y" side of the multiplier exhibits a second order nonlinearity whereas the "X" sideexhibitsa simple non-linearity.
By making the Ry resistor approximately twice the value
of the RX resistor, the linearity on both the "X" and "y"
sides are made equal. The selection of the R X and R y
resistor values is dependent upon the expected amplitude of
Vx and Vy inputs. To maintain a specified linearity,
resistors RX and Ry should be selected according to the
following equations:
RX~

Offset and Scale Factor Adjustment Procedure
A. X Input Offset

(a) connect oscillator (1 kHz, 5 Vpp sinewavel to the "Y"
input (pin 91

(bl connect "X" input (pin 101 to ground
(c) adjust X-offset potentiometer, P2 for an ac null at
the output

B. y I nput Offset
(a) connect oscillator (1 kHz, 5 Vpp sinewave) to the "X"
input (pin 101

(b) connect "Y" input (pin 9) to ground
(cl adjust V-offset potentiometer. P1 for an ac null at
the output

3 Vx (max) in kn when Vx is in volts

C. Output Offset
(a) connect both "X" and "V" inputs to ground
(bl adjust output offset potentiometer, P3, until the output voltage Va' is zero volts de
D. Scale Factor
(a) apply +10 Vdc to both the "X" and "Y" inputs
(bl adjust P4 to achieve -10.00 V at the output

Ry ~ 6 Vy (max) in kn when Vy is in volts
For example, if the maximum input on the "X" side is
±1 volt, resistor RX can be selected to be 3 kn. If the maximum input on the "Y" side is also ±1 volt, then resistor
Ry can be selected to be 6 kn (6.2 kn nominal value). If a
scale factor of K = 10 is desired, the load resistor is found to
be 47 kn. In this example, the multiplier provides a gain

(cl apply -10 Vdc to both "X" and "Y" inputs and check
for Va = -10.00 V

of 20dB.

2.2

Operational Amplifier Selection

E. Repeat steps A through 0 as necessary.

The operational amplifier connection in Figure 16 is a simple
but extremely accurate current-to-voltage converter. The
·output current of the multiplier flows through the feedback
resistor RL to provide a low impedance output voltage from
the op-ampl. Since the offset current and bias currents of
the op-ampl. will cause errors in the output voltage, particularly with temperature, one with very low bias and offset cur-

The ability to accurately adjust the MC1594 is dependent
on the offset adjust potentiometers. Potentiometers should
be of the "infinite" resolution type rather than wirewound.
Fine adjustments in balanced·modulator applications may
require two potentiometers to provide "coarse" and "fine"
adjustment. Potentiometers should have low temperature
coefficients and be free from backlash.

rents is recommended. The MC1556/MC1456 or MC17411

MC1741 C are excellent choices for this application.
Since the MC1594 is capable of operation at much higher
frequencies than the op-ampl., the frequency characteristics
of the circuit in Figure 16 will be primarily dependent upon
the op-ampl.
2.3

2.6

While the MC1594 provides excellent performance in itself,
overall performance depends to a large degree on the quality
of the external components. Previous discussion shows the
direct dependence on RX, Ry, and RL and indirect dependence on R1 (through 11). Any circuit subjected to temperature variations should be evaluated with these effects in mind.

Stability

The current-to-voltage converter mode is a most demanding
application for an operational amplifier. Loop gain is at its
maximum and the feedback resistor in conjunction with
stray or input capacitance at the multiplier output adds additional phase shift. It may therefore be necessary to add
(particularly in the case of internally compensated op-ampls.)
a small feedback capacitor to reduce loop gain at the higher
frequencies. A value of 10 pF in parallel with RL should be
adequate to insure stability over production and temperature
variations, etc.
An externally compensated op-ampl. might be employed
using sl ightly heavier compensation than that recommended
for unity-gain operation.

2.7

Bias Currents
The MC1594 multiplier, like most linear IC's. requires a dc
bias current into its input terminals. The device cannot be
capacitively coupled at the input without regard for this bias
current. If inputs Vx and Vy are able to supply the small bias
current (=:::: 0.5 IJAI resistors, R (Figure 161 can be omitted.
If the Me 1594 is used in an ac mode of operation and
capacitive coupling is used the value of resistor R can be any
reasonable value up to 100 kn. For minimum noise and
optimum temperature performance, the value of resistor R
should be as low as practical.

2.8
2.4

Temperature Stability

Offset Adjustment

Parasitic Oscillation
When long leads are used on the inputs, oscillation may occur.
In this event, an RC parasitic suppression network similar to
the ones shown in Figure 16 should be connected directly
to each input using short leads. The purpose of the network

The non-inverting input of the op-ampl.provides a convenient
point to adjust the output offset voltage. By connecting this
point to the wiper arm of a potentiometer (P3), the output

(MC1594 - Pg. 7)

7-368

MC1594L, MC1494L (continued)

"zeros" is seen in Figures 9 and 10. The reason for this
increase in gain is due to the bypassing of RX and Ry at
high frequencies. Since the Ry resistor is approximately
twice the value of the RX resistor, the zero associated with
the "Y" input will occur at approximately one octave below
the zero associated with the "X" input. For R X 30 kf2. and
Ry = 62 kf!, the zeros occur at 1.5 MHz for the "X" input
and 700 kHz for the "Y" input. These two measured breakpoints correspond to a shunt capacitance of about 3.5 pF.
Thus, for the circuit of Figure 17, the "X" input zero and
"Y" input zero will be at approximately 15 MHz and
7 MHz respectively.
It should be noted that the MC1594 multiplies in the time
domain, hence, its frequency response is found by means
of complex convolution in the frequency (Laplace) domain.
This means that if the "x" input does not involve afrequency,
it is not necessary to consider the "x" side frequency
response in the output product. likewise, for the "Y" side.
Thus, for applications such as a wideband linear AGC amplifier which has a dc voltage as one input, the multiplier frequency response has one zero and one pole. For applications
which involve an ac voltage on both the "x" and "Y" side,
such as a balanced modulator, the product voltage response
will have two zeros and one pole, hence, peaking may be
present in the output.
From this brief discussion, it is evident that for ac applications; (1) the value of resistors RX, Ry and RL should be
kept as small as possible to achieve maximum frequency
response, and (2) it is possible to select a load resistor R L
such that the dominant pole (RL, Co) cancels the input zero
(RX, 3.5 pF or Ry, 3.5 pF) to give a flat amplitude characteristic with frequency. This is shown in Figures 9 and 10.
Examination of the frequency characteristics of the "X"
and "~V"~ inputs will demonstrate that for wideband amplifier
applications, the best tradeoff with frequency response and
gain is achieved by using the"Y" input for the ac signal.
For ac applications requiring bandwidths greater than those
specified for the MC1594, two other devices are recom·
mended.
For modulator-demodulator applications. the
MC1596 may be used up to 100 MHz. For wideband multiplier applications, the MC1595 (using small collector loads
and ac coupling) can be used.

is to reduce the "Q" of the source-tuned circuits which cause
the oscillation.
Inability to adjust the circuit to within the specified accuracy
may be an indication of oscillation.

3.

AC OPERATION

3.1

General

;=;

For ae operation, such as balanced modulation, frequency
doubler, AGe, etc., the ap-ampl. will usually be omitted as

well as the output offset adjust potentiometer. The output
offset adjust potentiometer is omitted since the output will
normally be ae-coupled and the de voltage at the output is
of no concern providing it is close enough to zero volts that
it will not cause clipping in the output waveform. Figure 17

FIGURE 17 - WIDEBAND MULTIPLIER
Uk

Jk

+15 V -15 V

I

I

:.~ k-~~ Co
I

i
OJ

51k

-"/'/",r"
20k

3.3
shows a typical ae multiplier circuit with a scale factor K:::::: 1.
Again, resistor RX and Ry are chosen as outlined in the
previous section, with R L chosen to provide the required
scale factor.
The offset voltage then existing at the output will be equal to
the offset current times the load resistance. The output offset current of the MC1594 is typically 17 p.A and 35 p.A
maximum. Thus, the maximum output offset would be
about 160 mV.
3.2

Slew-Rate
The MC1594 multiplier is not slew·rate limited in the ordinary sense that an op-amp!. is. Since all the signals in the
multiplier are currents and not voltages, there is no charging
and discharging of stray capacitors and thus no limitations
beyond the normal device limitations. However, it should
be noted that the quiescent current in the output transistors
is 0.5 rnA and thus the maximum rate of change of the output voltage is limited by the output load capacitance by
the simple equation:

Bandwidth
The bandwidth of the MC1594 is primarily determined by
two factors. First, the dominant pole will be determined by
the load resistor and the stray capacitance at the output
terminal. For the circuit shown in Figure 17, assuming a
total output capacitance (Co) of 10 pF, the 3 dB bandwidth
would be approximately 3.4 MHz. If the load resistor were
47 kn, the bandwidth would be approximately 340 kHz.
Secondly, a "zero" is present in the frequency response
characteristic for both the "X" and "Y" inputs which causes
the output signal to rise in amplitude at a 6 dB/octave slope
at frequencies beyond the breakpoint of the "zero". The
"zero" is caused by the parasitic and substrate capacitance
which is related to resistors RX and Ry and the transistors
associated with them. The effect of these transmission

Slew-Rate

tJ.V o

10

-.;-:r = e-

Thus, if Co is 10 pF, the maximum slew-rate would be:

6.V o
-

6.T

0.5xl0- 3
= ---- =

50 V/MS

lOx 10-12

This can be improved if necessary by addition of an emitterfollower or other type of buffer.
3.4

Phase-Vector Error
All multipliers are subject to an error which is known as the
phase-vector error. This error is a phase error only and does
not contribute an amplitude error per se. The phase-vector

(MC1594 - Pg. 8)

7-369

•

MC1594L, MC1494L (continued)

efror is best explained by an example. If the "X" input is
described in vector notation as

4.

DC APPLICATIONS

4.1

Squaring Circuit

X=A ~ 00

If the two inputs are connected together, the resultant
function is squaring:

and the "V" input is described as

Vo

Y=B1(00
then the output product would be expected to be
Vo = AB

1\

= KV 2

where K is the scale factor (see Figure 19).
However, a more careful look at the multiplier's defining
equation will provide some useful information. The output
voltage, without initial offset adjustments is given by:

00 (see Figure 18)

However, due to a relative phase shift between the "X" and
Vo = K(V x + Viox -Vxoff) (Vy + Vioy - Vy off) + Voo

"V" channels, the output product will be given by

(See "Definitions" for an explanation of terms).
With Vx = Vy = V (squaring) and defining

Notice that the magnitude is correct but the phase angle of
the product is in error. The vector, V, associated with this
error is the "phase·vector error". The startli ng fact about
the phase-vector error is that it occurs and accumulates much
more rapidly than the amplitude error associated with frequency response. In fact, a relative phase shift of only 0.57°
will result in a 1% phase-vector error. For most applications,
this error is meaningless. If phase of the output product is
not important, then neither is the phase·vector error. If
phase is important, such as in the case of double sideband
modulation or demodulation, then a 1% phase-vector error
will represent a 1% amplitude error at the phase angle
of interest.

EX

~
I
I

p..'Ot.

•

Vo = K V~ + KV x (EX + Ey) + K€xe:y + Voo
This shows that all error terms can be eliminated with only
three adjustment potentiometers, eliminating one of the input offset adjustments. For instance, if the "X" input offset
adjustment is eliminated, EX is determined by the internal
offset, Viox, but Ey is adjustable to the extent that the
(EX + Eyl term can be zeroed. Then the output offset adjustment is used to adjust the Voo term and thus zero the remaining error terms. An ac procedure for nulling with three
adjustments is:
A. AC Procedure:
1. Connect oscillator (1 kHz, 15 Vpp) to input
2. Monitor output at 2 kHz with tuned voltmeter and
adjust P4 for desired gain (Be sure to peak response
of voltmeter)
3. Tune voltmeter to 1 kHz and adjust Pl for a minimum
output voltage
4. Ground input and adjust P3 (output offset) for zero
volts dc out
5. Repeat steps 1 through 4 as necessary.

v

1
1

ABI{OO

3.5

Vx off

The output voltage equation becomes

FIGURE 18 - PHASE·VECTOR ERROR
y. B~ 0 0 .

= Viox -



TOpF
MC1594L

(MCI494l)
14

·v 2
Va ="'i'i)

'I

1

3

6

13

4 511::.

P
10

510

16k

20k

INPUT

OFFSET

'3
-15 V

(MC1594 - Pg. 9)

7-370

+15 V

MC1594L, MC1494L

(continued)

B. DC Procedure:

Vx being near zero is a result of the transfer through the
multiplier being near zero. The op-ampl. is then operating

1. Set Vx = Vv = 0 V and adjust P3 (output offset
potentiometer) such that Vo = 0.0 Vdc

potentiometer) such that the output voltage is

with a very high closed loop gain and error voltages can thus
become effective in causing latch-up.
The other mode of latch-up results from the output voltage

-0.100 volts

of the op-ampl. exceeding the rated common-mode input

2. Set Vx = Vv = 1.0 V and adjust Pl (V input offset

voltage of the multiplier. The input stage of the multiplier

3. Set Vx = Vv = 10 Vdc and adjust P4 (load resistorl

becomes saturated, phase reversal tesults, and the circuit is

such that the output voltage is -10.00 volts

latched up.

4. Set Vx = Vv = -10 Vdc and check that Vo =-10V

4.2

Divide
Divide circuits warrant a special discussion as a result of their
special problems. Classic feedback theory teaches that if a
multiplier is used as a feedback element in an operational
amplifier circuit, the divide function results. Figure 20 illustrates the theoretical simplicity of such an approach and a
practical realization is shown in Figure 21.
The characteristic "failure" mode of the divide circuit is
latch-up. One way it can occur is if Vx is allowed to go
negative or. in some cases, if Vx approaches zero.
Figure 20 illustrates why this is so. For Vx >0 the transfer
function through the multiplier is non-inverting. Its output
is fed to the inverting input of the op-ampl. Thus, operation
is in the negative feedback mode and the circuit is dc stable.
Should Vx change polarity, the transfer function through
the multiplier becomes inverting, the amplifier has positive
feedback and latch-up results. The problem resulting from

1. Set Vz = 0 volts and adjust the output offset potentio-

meter (P3) until the output voltage (Vol remains at
some (not necessarily zero) constant value as Vx is varied
between +1.0 volt and +10 volts.
2. Maintain Vz at 0 volts, set Vx at +10 volts and adjust the Y input offset potentiometer (Pl) until Vo = 0
volts.
3. With Vx = VZ, adjust the X input offset potentiometer
(P2) until the output voltage remains at some (not necessarily -10 volts) constant value as Vz = V X is varied
between +1.0 volt and +10 volts.

FIGURE 20 - BASIC DIVIDE CIRCUIT USING MULTIPLIER
Vx

4. Maintain Vx = Vz and adjust the scale factor potentiometer (R L) until the average value of Vo is -10 volts as
Vz = Vx is varied between +1.0 volt and +10 volts.
5. Repeat steps 1 through 4 as necessary to achieve optimum performance.

K VXVy
VZ" -KVXVy

MC1594l
(MC149411

The circuit of Figure 21 protects against this

happening by clamcing the output swing of the op-ampl. to
approximately ± 10.7 volts. Five-percent tolerance, 10-volt
zeners are used to assure adequate output swing but still
limit the output voltage of the op-ampl. from exceeding the
common-mode input range of the MC1594.
Setting up the divide circuit for reasonably accurate operation is somewhat different from the procedure for the
multiplier itself. One approach, however. is to break the
feedback loop, null out the multiplier circuit, and then close
the loop.
A simpler approach, since it does not involve breaking the
loop (thus making it more practical on a production basis), is:

Repeat steps 1 through 4 as necessary.

OR

·Vz
Vo " -

Users of the divide circuit should be aware that the accuracy
to be expected decreases in direct proportion to the denomi-

KVx

Vz

>--~-""V,

FIGURE 21 - PRACTICAL DIVIDE CIRCUIT

62.

30.

Vz

,---'I""'-----'VIN---t-<. MZ91 ·I1B.

<

OREQUIV

lN961B/
(IN5240BI_

IIOVI

-

OR EOUIV
MCI594l
(MCI494l)

Vx

1

10 PF

15

13

-IOVZ

PI20k

Vo"

510

+15 V

"'"VX

-15 V

0< Vx

< +10 V

-10 V,.;; Vz,.;; +10 V

-15 V +15V

(MC1594 - Pg. 10)

7-371

I

MC1594L, MC1494L (continued)

Steps 1 through 3 may be repeated as necessary to achieve

FIGURE 22 - BASIC SQUARE ROOT CIRCUIT

desi red aceu racy.

Note: Operation near zero volts input may prove very in·
accurate, hence, it may not be possible to adjust Va

MC1594l
!MC1494l1

KV02

to 0 but rather only to within 100 to 400 mV of zero.
KV02= - Vz

OR

vo=F.

5.

AC APPLICATIONS

5.1

Wideband Amplifier With Linear AGe
If one input to the MC1594 is a de voltage and a signal
voltage is applied to the other input. the amplitude of the
output signal can be controlled in a linear fashion by varying
the de voltage. Hence, the multiplier can function as a de
coupled, wideband amplifier with linear AGe control.

Vz""OV

Vz

>--~-_Vo

In addition to the advantage of Linear AGe control, the

multiplier has three other distinct advantages over most other
types of AGe systems. First. the AGe dynamic range is
theoretically infinite. This stems from the basic fact that
with zero volts dc applied to the AGe, the output will be
zero regardless of the input. In practice. the dynamic range
is limited by the ability to adjust the input offset adjust
potentiometers. By using cermet multi-turn potentiometers,
a dynamic range of 80 dB can be obtained. The second
advantage of the multiplier is that variation of the AGe voltage has no effect on the signal handling capability of the
signal port. nor does it alter the input impedance of the
signal port. This feature is particularly important in AGe
systems which are phase sensitive. A third advantage of the
multiplier is that the output-voltage-swing capability and
output impedance are unchanged with variations in AGe
voltage.
The circuit of Figure 24 demonstrates the linear AGe amplifier. The amplifier can handle 1 V(rms) and exhibits a gain

nator voltage. As a result, if V X is set to 10 volts and 0.5%
accuracy is available, then 5% accuracy can be expected
when Vx is only 1 volt.
In accordance with an earlier statement, Vx may have only
one polarity, positive, while Vz may be either polarity.
4.3

Square Root
A special case of the divide circuit in which the two inputs
to the multiplier are connected together results in the square
root function as indicated in Figure 22. This circuit too
may suffer from latch-up problems similar to those of the
divide circuit. Note that only one polarity of input is allowed
and diode clamping(see Figure 231 protects against accidental
latch·up.

This circuit too, may be adjusted in the closed-loop mode:

of approximately 20 dB.

I. Set Vz = -0.01 Vdc and adjust P3 (output offset) for
Vo = 0.316 Vdc.

2. Set

Vz

to -0.9 Vdc and adjust P2 ("X" adjust) for Va ""

+3 Vdc.
3. Set Vz to -10 Vdc and adjust P41gain adjust) for Vo
+10 Vdc.

It is AGC'd through a 60 dB

dynamic range with the application of an AGe voltage from
o Vdc to 1 Vdc. The bandwidth of the amplifier is determined by the load resistor and output stray capacitance. For
this reason, an emitter-follower buffer has been added to
extend the bandwidth in excess of 1 MHz.

=
5.2

Balanced Modulator

When two-time variant signals are used as inputs, the resultFIGURE 23 - SQUARE ROOT CIRCUIT

62k

30k

IN962B

'I

Vo

P
10

-=

(IN52418)
(11 VJ
OR EQUIV

510

15

13

51k
P3 20 k
+15 V

-15V
-10 V,.;: VZ";: 0 V

-15 V +15 V

(MC1594 -Pg. 11)

7-372

MC1594L, MC1494L

(continued)

ing output is suppressed-carrier double-sideband modulation.
In terms of sinusoidal inputs, this can be seen in the following

FIGURE 25 - BALANCED MODULATOR
"15 V -15V

equation:
3k

6.2k

O.l/-1 F

I

where wm is the modulation frequency and We is the carrier
11

frequency. This equation can be expanded to show the
suppressed carrier or balanced modulation:

15

Ke,e2

Vo = - 2 - (cos(wc+wm)t+cos (we - wm)tJ
14

MC1594L
(MC1494l)

Unlike many modulation schemes, which are non-linear in

nature, the modulation which takes place when using the
MC1594 is linear. This means that for two sinusoidal inputs,
the output will contain only two frequencies, the sum and
difference, as seen in the above equation. There will be no
spectrum centered about the second harmonic of the carrier,
or any multiple of the carrier. For this reason, the filter
requirements of a modulation system are reduced to the
minimum. Figure 25 shows the MC1594 configuration to
perform this function.

eo = Kecem
K= I

RL
13

Ok

51k
20k

16k

ec.:;±l Vpk
em<:±2 Vpk

FIGURE 24 - WIDEBAND AMPLIFIER
WITH LINEAR AGe
-15

3k

6.2k

v "15 V
The adjustment procedure for this circuit is quite simple.
(1)
Place the carrier signal at pin 10. With no signal
applied to pin 9, adjust potentiometer P1 such that an ac
null is obtained at the output.
12)
Place a modulation signal at pin 9. With no signal
applied to pin 10, adjust potentiometer P2 such that an ac
null is obtained at the output.
Again, the abil ity to make careful adjustment of these offsets
will be a function of the type of potentiometers used for
Pl and P2. Multiple turn cermet type potentiometers are
recommended.

O.I/-lF

I

11

2N3946
12N3904J
OR EQUIV

14

MC1594l
(MC1494L!
10

5.3

VAGC

51k
13

16k

Frequency Doubler
If for Figure 25 both inputs are identical;

3'

em = ec = Ecoswt
51k

-15V

Then the output is given by

20k

eo

= emec = E 2 cos2wt

which reduces to

E2

eo
Notice that the resistor values for RX, Ry, and RL have
been modified. This has been done primarily to increase the
bandwidth by lowering the output impedance of the MC1594
and then lowering RX and Ry to achieve a gain of 1. The
ec can be as large as 1 volt peak and em as high as 2 volts
peak. No output offset adjust is employed since we are
interested only in the ac output components.
The input R's are used to supply bias current to the mUltiplier inputs as well as provide matching input impedance.
The output frequency range of this configuration is determined by the 4.7 k ohm output impedance and capacitive
loading. Assuming a 6 pF load, the small-signal bandwidth

=""2 (1

+ cos2wtl

This equation states that the output will consist of a dc term
equal to one half the peak voltage squared and the second
harmonic of the input frequency. Thus, the circuit acts as a
frequency doubler. Two facts about this circuit are worthy
of note. First, the second harmonic of the input frequency
is the only frequency appearing at the output. The funda·
mental does not appear. Second, if the input is sinusoidal,
the output will be sinusoidal and requires ~ filtering.
The circuit of Figure 25 can be used as a frequency doubler
with input frequencies in excess of 2 MHz.
5.4

is 5.5 MHz.

Amplitude Modulator
The circuit of Figure 25 is also easily used as an amplitude
modulator. This is accomplished by simply.varying the input
offset adjust potentiometer IP1) associated with the modu-

The circuit of Figure 25 will provide a typical carrier rejection
of ;;,70 dB from'O kHz to 1.5 MHz.

(MC1594 - Pg. 12)

7-373

MC1594L, MC1494L (continued)

lation input. This procedure places a de offset on the modu-

Vy off

lation input of the multiplier such that the carrier still passes
thru the multiplier when the modulating signal is zero.
The result is amplitude modulation. This is easily seen by
examining the basic mathematical expression for amplitude

V 00

modulation given below.
with K = 1.

=(E + Em coswmt)

80

= Eo

FIGURE 26

(E e caswetl

~~
'

I

{1 + M coswct] coswct

M

Em

=E

- - --L

Linearity
Linearity is defined to be the maximum deviation of output
voltage from a straight line transfer function. It is expressed
as a percentage of full-scale output and is measured for Vx
and Vy separately either using an "X-V" plotter (and checking
the deviation from a straight line) or by using the method
shown in Figure 1. The latter method nulls the output signal
with the input signal, resulting in distortion components
proportional to the linearity.

input offset potentiometer, P1, until the output exhibits the
familiar amplitude modulation waveform.

Phase Detector
If the circuit of Figure 25 has as its inputs two signals of
identical frequency but having a relative phase shift the output will be a de signal which is directly proportional to the
cosine of phase difference as well as the double frequency

Example: 0.35% linearity means

term.
Vo =

em
eo
or

=

Emcoslwct+¢}

6.3

6.

EcEm
eO=-2-[coS+cosI2wct+<1>1

Input Offset Voltage

Volac ) = K IO±Viox -Vx offllsinwtl

6.4

Output Offset Current and Voltage
Output offset current (100) is the de current flowing in the
output lead when Vx = Vy = 0 and "x" and "Y" offset voltages are adjusted to zero.

DEFINITIONS OF SPECIFICATIONS

Output offset voltage (V 00) is:
Voo = 100 RL

where R L is the load resistance.
Note: Output offset voltage is defined by many manufacturers with all inputs at zero but without adjusting
"x" and "Y" offset voltages to zero. Thus it includes
input offset terms, an output offset term and a scale
factor term.

Multiplier Transfer Function
The output of the multiplier may be expressed by this
equation:
Va = K IVx ± Viox -VxoffllVy± Vioy -Vyoff)± Voo 111

---;-0 ± 10.0035) 110 voltsl

adjust Vx off so that (± Viox -Vx offl = O.

Because of the unique nature of a multiplier, Le., two inputs
and one output, operating specifications are difficult to
define and interpret. I ndeed the same specification may be
defined in several completely different ways depending upon
which manufacturer is doing the defining. I n order to clear
up some of this mystery, the following definitions and
examples are presented.
6.1

VxVy

The input offset voltage is defined from Equation (1), It is
measured for Vx and Vy separately and is defined to be that
de input offset adjust voltage ("x" or "y") that will result in
minimum ac output when ac (5 Vpp, 1 kHz) is applied to the
other input ("y" or "x" respectively). From Equation (1)
we have:

= ecem = EcEm coswct cos(wct + q,)

The addition of a simple low pass filter to the output (which
eliminates the second cosine term) and return of R L to an
offset adjustment potentiometer will result in a dc output
voltage which is proportional to the cosine of the phase difference. Hence, the circuit functions as a synchronous
detector.

_I~VY

(V X =± 10 VI

!Vv =± 10 V)

6.2

Offset

,",J L

..

= modulation Index

This is the standard equation for amplitude modulation.
From this, it is easy to see that 100% modulation can be
achieved by adjusting the input offset adjust voltage to be
exactly equal to the peak value of the modulation, Em- This
is done by observing the output waveform and adjusting the

~

'IO"",t
I
I

Output
Offset

Eo = EEc

and

5.5

input offset adjust voltage

output offset voltage

For the case under discussion,

where E 15the de input offset adjust voltage. This expression
80

=

The voltage transfer characteristic below indicates "X", "y"
and output offset voltages.

can be written as:

where

= "y"

6.5

Scale Factor

Scale factor is the K term in Equation (1). It determines the
"gain" of the multiplier and is expressed approximately by
the following equation.

where K = scale factor (see 6.5)

vx =

"x" input voltage
Vy = "y" input voltage
Viox = "x" input offset voltage
Vioy = "y" input offset voltage
Vx off = "x" input offset adjust voltage

2RL
K = RxRyll where Rx and Ry

and 11 is the current out of pin 1.

(MC1594 - Pg. 13)

7-374

kT

»CiI1

MC1594L, MC1494L

6.6

(continued)

GENERAL INFORMATION INDEX

Total DC Accuracy
The total dc accuracy of a multiplier is defined as error in
multiplier output with de (± 10 Vdcl applied to both inputs.
It is expressed as a percent of full scale. Accuracy is not
specified for the Me 1594 because error terms can be nulled
by the user.

6.7

Temperature Stability (Drift)

Each term defined above will have a finite drift with temperature. The temperature specifications are obtained by readjusting the multiplier offsets and scale factor at each new
temperature (see previous definitions and the adjustment
procedure) and noting the change.

Assume inputs are grounded and initial offset voltages have
been adjusted to zero. Then output voltage drift is given by:
6V O
(6T)

6.8

= ±(K±K (TCKI (6TI
I ± (TCVool (~Tl

I ( (TCVioxl (6TI I ( (TCVioyl

Total DC Accuracy Drift
This is the temperature drift in output voltage with 10 volts
applied to each input. The output is adjusted to 10 volts at
T A = +2SoC. Assuming initial offset voltages have been
adjusted to zero at T A = +25 0 C. then:
Vo

=

(K±K (TCKI (6TI 1(10 ± (TCVioxl (6TI 1(10

(TCVioyl (6TI I

6.9

±.

± (TCVool (6TI

Power Supply Rejection
Variation in power supply voltages will cause undesired
variation of the output voltage. It is measured by superimposing a l-valt, 100-Hz signal on each supply (±15 VI

with each input grounded. The resulting change in the output is expressed in mV/V.

6.10

Output Voltage Swing

Output voltage swing capability is the maximum output
voltage swing (without clipping) into a resistive load (note-

output offset is adjusted to zero).
If an op·ampl. isused, the multiplier output becomes a virtual
ground - the swing is then determined by the scale factor
and the op-ampl. selected.

(MC1594 ~P9. 14)

7-375

1.

CIRCUIT DESCRIPTION

1.1
1.2
1.3
1.4

Introduction
Regulator
Multiplier
Differential Current Converter

2.
2.1
2.2

Selection of External Components
Operational Amplifier Selection

2.3

Stabil ity

2.4
2.5
2.6
2.7
2.8

Offset Adjustment
Offset and Scale Factor Adjustment Procedure
Temperature Stability
Bias Currents
Parasitic Oscillation

DC OPERATION

3.

AC OPERATION

3.1
3.2

General
Bandwidth

3.3

Slew· Rate

3.4
3.5

Phase· Vector Error
Circuit Layout

4.

DC APPLICATIONS

4.1
4.2
4.3

Squaring Circuit
Divide
Square Root

5.

AC APPLICATIONS

5.1
5.2
5.3
5.4
5.5

Wideband Amplifier with Linear AGC
Balanced Modulator
Frequency Modulator
Amplitude Modulator
Phase Detector

6.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9

DEFINITIONS OF SPECIFICATIONS

6.10

Multiplier Transfer Function
Linearity
Input Offset Voltage

Output Offset Current and Voltage
Scale Factor
Total DC Accuracy

Temperature Stability (prift)
Total DC Accuracy Drift
Power Supply Rejection
Output Voltage Swing

•

•

,-------I

'l~

MC1595L
MC1495L

_____________________

M_U__
LT__
IP_L_IE_R~

Specifications and Applications InforIllation
WIDEBAND MONOLITHIC
FOUR-QUADRANT MULTIPLIER

LINEAR FOUR-QUADRANT
MULTIPLIER INTEGRATED
CIRCUIT

. designed for uses where the output is a linear product of two
input voltages. Maximum versatility is assured by allowing the user
to select the level shift method. Typical applications include: multiply, divide', square root', mean square', phase detector, frequency
doubler, balanced modulator/demodulator, electronic gain control.

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

·When used with an operational amplifier.

• Wide Bandwidth
•

Excellent Linearity - 1% max Error on X-Input, 2% max Error on
Y-Input - MC1595L

•

Excellent Linearity - 2% max Error on X-I nput, 4% max Error on
Y-Input - MC1495L

•

Adjustable Scale Factor, K

•

Excellent Temperature Stability

~
~~~tDry~ ~

(top view)

CERAMIC PACKAGE
CASE 632
TO-116

• Wide I nput Voltage Range - ±. 10 Volts

• ±. 15 Volt Operation

FIGURE 1 - FOUR-OUADRANT
MULTIPLIER TRANSFER CHARACTERISTIC

FIGURE 2 - TRANSCONDUCTANCE BANDWIDTH
'2

~

.1

-1-6_011-.:::-+-0;...:--

~ +4.0 1--+"""""'-"\.;:--+----'
1

1·2.0'f--+--f=E==li3~~==:f=-P:t.:.f~
~ -2.0
~ -4.011--+-:7+""7r-+-+--i-~:-

0
0
0
0
0
0

~

I:

y

IIVx

-2
-3
-4.0

-2.0

+2.0

+4.0

1.0

100

10
I, FREQUENCY (MHz)

Vx. INPUT VOLTAGE (VOLTS)

FIGURE 3 - CIRCUIT SCHEMATIC

r-1==:;::=r===I='1~2 Output
14

(KXY)

X Input

Y Input

12

V- 7~----~--~-~-----~-~-~
See Packaging Information Section for outline dimensions.

See current MCC1595/1495 data sheet for standard linear chip information.

7-376

1000

MC1595L, MC1495L (continued)
ELECTRICAL CHARACTERISTICS (v+ = +32V, V- = -15 V, TA

= +25 0 C, 13
R L = 11 kil unless otherwise noted)

Characteristic

Linearity:
Output Error in Percent of Full Scale:
TA = +25 0 C
-10< VX< +10 (Vy =±10 V)
-10< Vy< +10 (VX =±10 V)
T A = 0 to +700 C
-10< VX< +10 (Vy =±10
-10< Vy< +10 (VX = tl0
T A = -55°C to +1250 C
-10< VX< +10 (Vy =±10
-10< Vy< +10 (VX =±10

Figure

= 113 = 1 rnA,

RX

= Ry = 15 kil,

Symbol

Min

Typ

Max

ERX

-

± 1.0
±0.5
±2.0
± 1.0

± 2.0
± 1.0
±4.0
±2.0

± 1.5
±3.0

-

5
MC1495
MC1595
MC1495
MC1595
MC1495

%

_.

ERY

V)
V)

ERX
ERY

-

-

MC1595
V)
V)

Unit

.-

ERX
ERY

_.

:!C. 0.75
± 1.50

-

-

-

Squaring Mode Error:

Accuracy in Percent of Full Scale After
Offset and Scale Factor Adjustment
TA = +250 C
TA=Oto+700C
TA

= -55°C to +125 0 C

5

MC1595

MC1495
MC1595
MC1495
MC1595

I nput Resistance

= 20 Hz)

!.

-

--

+ 0.75
0.5
± 1.0

± 0.75

.-

0.1

-

-

_.
-

MegOhms

-

Scale Factor (Adjustable)
2RL
(K=---)
13 RX Ry
(f

%

ESQ

MC1495
MC1595
MC1495

Differential Output Resistance (f = 20 Hz)

-

K

7

RINX

-

RINY

.-

8

Ro

MC1495
MC1595
MC1495
MC1595

6

Ibx

MC1495
MC1595
MC1495
MC1595

6

-

-

20
35
20
35

-

300

-

k Ohms

-

2.0
2.0
2.0
2.0

12
8.0
12
8.0

I'A

0.4
0.2
0.4
0.2

2.0
1.0
2.0
1.0

I'A

-

-

Input Bias Current

(19+ 112)
(14+ 18)
Ibx = - - 2 - - , Iby = - 2 -

I nput Offset Current
119 -1121
114 -lsi

Iby

Ilioyl

6

6

kn
n

Common Mode I nput Swing
(Either Input)
Common Mode Gain
(Either Inpull
Common Mode Quiescent
Output Voltage

-

2.0
2.0

-

-

20
10

100
50

20
20

.-

I'A

11001

nA/oC

ITClooi

MC1495
MC1595

3.0 dB Bandwidth, RL = 11
3.0 dB Bandwidth, R L = 50
(Transconductance Bandwidth)
3° Relative Phase Shift Between Vx and Vy
1% Absolute Error Due to Input-Output Phase Shift

nA/oC

-

Average Temperature Coefficient of

Frequency Response

-

ITCliol

MC1495
MC1595

Output Offset Current
(T A = 0 to +70 0 C)
(T A = -55°C to +125 0 C)

-

6
MC1495
MC1595

Output Offset Current
1114 -121

-

Average Temperature Coefficient of

I nput Offset Current
(T A = 0 to +700 C)
(T A = -55°C to +1250 C)

Ilioxi

-

_.

9,10

3.0
80
750
30

-

±10.5
±11.5

±12
±13

-

-40
-50

-50
-60

-

12

Vol
V02

-

21
21

-

dB

ACM

MC1495
MC1595

MHz
MHz
kHz
kHz
Vdc

CMV

MC1495
MC1595
II

_.

-

BW3dB
TBW3dB
f---0""""" V,
33k

13

OFFSET
ADJUST
SEE FIGURE 13

12k

-----'
SCALE
FACTOR
ADJUST

5k

10k

OUTPUT
OFFSET
ADJUST

+---------''------.....------------~------.. V· •• ''V
NOTES:

'I'D.1J.1F

Adjust "SclI.FattorAdjustHforanullinVe.
This schematic for illultr.ivt purposes only-

notspecifild for tilt condilions.

FIGURE 5 - LINEARITY (USING X·Y PLOTTER TECHNIQUE)

32V
R1
19.1k

Vv
Vx

OFFSET ADJUST.
(SEE FIGURES 13& 14)

t

v
X

-15V

7-378

PLOTTER

x-v

Y·INPUT

PLOTTER

MC1595L, MC1495L

(continued)

TEST CIRCUITS (continued)

FIGURE 7 - INPUT RESISTANCE

FIGURE 6 - INPUT AND OUTPUT CURRENT
+32 V

Ry=15k RX=15k

'I = 1.0 V Irm,)
20 Hz

+32 V

Ry=15k Rx=15k
5

1.0 M

11

4

I

9.1 k

1.0 M
Ilk
'2

-=

'2

-=

T

1.0M

RINX = RINY = R 1~ .21

-=

·15 V

FIGURE 9 - BANDWIDTH (Rl = 11 k11)
+32 V

Ry=15k Rx=15k

13.75 k

-= -=

FIGURE 8 - OUTPUT RESISTANCE

II k

14

12

+32 V

Ry=15k RX=15k
9.1 k
Ilk
MCI595L
IMCI495L)

Ilk

14

*

13

0.1

RI3k
13.7

~F

SCALE
FACTOR
ADJUST.
·15V

FIGURE 10 - BANDWIDTH (Rl = 50 11)

FIGURE 11 - COMMON-MODE GAIN and
COMMON-MODE INPUT SWING

Ry=510

15 k

RX=510

I

+32 V

15 k

9.1 k

Ik
50

+ II k

50
11k

K = 40

Vo

SCALE
FACTOR
ADJUST.

ACM

=20 log CMVy
Vo

·15 V

·15V

7-379

or 20 log CMVX

MC1595L, MC1495L(continued)

TEST CIRCUITS (continued)
FIGURE 13 - OFFSET ADJUST CIRCUIT

FIGURE 12 - POWER SUPPL Y SENSITIVITY
+32 V
15 k
15 k

+32 V

v+

9.1 k

R

2.0 k
11k

2.0 k

POH2

11k

lN753

6.2 V

4.3 k

10 k 10 k

'*

0.1

13.7k

-=
-15 V

-15V

~F

s+ =

fA (Vol - Vo2)l
t:.V+

s- =

It:. (Vol - Vo2)1
t:.V-

2.0 k
10 k

-15 V

FIGURE 14 - OFFSET ADJUST CIRCUIT (ALTERNATE)
V+

5.1 V

5.1 V

I

....... ~OO~I~S~~ ADJ

2k

-15V

7-380

-=

MC1595L, MC1495L (continued)

TYPICAL CHARACTERISTICS

FIGURE 16 - SCALE FACTOR versus TEMPERATURE

FIGURE 15 - LINEARITY versus TEMPERATURE

2. 0

0.110

I.Br'\.
I.6 " -

~

~
~
w
~

I.

(1f

0.105

1. 2

1.0

E O.
x

"'

4

B

~

"'

-

'-......

............

0.6

ERY

.....;.;.;-ERX

0.4

:='"

---

~

--

; 0.100

~

K ADJUSTED TO 0.100 AT +25DC

........

~

r--

",'

0.095

~

0.2

o

-55

o
+25
+50
+75
TA. AMBIENT TEMPERATURE (DC)

-25

+100

·55

+125

~

-'
:::>
u.
u.

0

~

0.6

0.4

0.2

13'=113 =1.0 mAde

o. B

~

O.B

0

''"'""

I

13 =113 = 1.0 mAde

I-

15
..,
'"
~

Vx = Vy =±5.0 V Max

Vx = Vy = ± 10 V Max
I

'"-'

+125

1.0

1.0

w

+100

FIGURE 18 - ERROR CONTRIBUTED BY
INPUT DIFFERENTIAL AMPLIFIER

FIGURE 17 - ERROR CONTRIBUTEO BY
INPUT DIFFERENTIAL AMPLIFIER

..,«-'

o
+25
+50
+75
TA. AMBIENT TEMPERATURE (DC)

·25

--

~

\

\

-'
-'
~ 0.6
u.

o

I-

~

w

12

\

\

ffi 0.4
..,

---

[\..

~

'"

~

0.2

~

I---lB

14
16
RX OR Ry (k OHMS)

o

4.0

20

6.0

'"

.........

'--- -

B.O
10
RX OR Ry (k OHMS)

12

14

I

FIGURE 19 - MAXIMUM ALLOWABLE INPUT VOLTAGE versus VOLTAGE AT PIN 1 OR PIN 7
14

::.

10

x
« B.O
::e

'"
0

x~

......

......

~

):
~

-----------v----- --,

12
~

~

MLNIM~

......

6.0

............ ---~
......, ~
RECiMMENOED

4.0
2.0

......,
2.0

---

-

...... ~

......

.....................

......
.... ~
4.0

6.0

B.O
10
IV11 OR IV7I1VOLTS)

7-381

12

14

16

lB

I

MC1595L, MC1495L (continued)

OPERATION AND APPLICATIONS INFORMATION

2.1.2 3 dB·Bandwidth and Phase Shift

1. Theory of Operation
The MC1595 (MC1495) is a monolithic, four-quadrant multi·

plier which operates on the principle of variable transconductance.
The detailed theory of operation is covered in Application Note
AN·489, Analysis and Basic Operation of the MC1595. The result
of this analysis is that the differential output current of the multi-

plier is given by
2VXVy
IA ·IB = "I = AXAy l 3
where IA and 18 are the currents into pins 14 and 2, respectively.
and Vx and Vy are the X and Y input voltages at the multiplier

input terminals.

2. Design Considerations

Bandwidth is primarily determined by the load resistors and
the stray multiplier output capacitance and/or the operational
amplifier used to level shift the output. If wideband operation
is desired, low value load resistors andlor a wideband operational
amplifier should be used. Stray output capacitance will depend
to a large extent on circuit layout.
Phase shift in the multiplier circuit results from two sources:
phase shift common to both X and Y channels (due to the load
resistor-output capacitance pole mentioned above) and relative
phase shift between X and Y channels (due to differences in
transadmittance in the X and Y channels). If the input to output
phase shift is only O.So, the output product of two sine waves
will exhibit a vector error of 1%. A 3 0 relative phase shift between Vx and Vy results in a vector error of 5%.
2.1.3 Maximum Input Voltage

2.1 General
The MC1595 (MC1495) permits the designer to tailor the
multiplier to a specific application by proper selection of ex-

VX(max). VY(max) maximum input voltages must be such
that:
VX(max) <113 Ay

ternal components. External components may be selected to
optimize a given parameter (e.g. bandwidth) which may in turn

VY(max) <13 Ay.

restrict another parameter (e.g. maximum output voltage swing).
Each important parameter is discussed in detail in the following
paragraphs.
2.1.1 Linearity, Output Error, EAX or EAY
Linearity error is defined as the maximum deviation of output voltage from a straight line transfer function. It is expressed
as error in percent of full scale (see figure below).

Exceeding this value will drive one side of the input amplifier to
"cutoff" and cause non-linear operation.
Currents 13 and 113 are "chosen at a convenient value (observing power dissipation limitation) between 0.5 mA and 2.0 rnA,
approximately 1.0mA. Then RXand Ry can be determined by
considering the input Signal handling requirements.
For VX(max) = VY(max) = 10 volts;
AX = Ay

ijf:f"'/

fVEmax

>~
= 10 kll,
1.0 mA

2VXVy
The equatLon IA - 18 = RxRy I 3

----7/r--'"'Vx+ 1ora vVy

2VXVy
is derived from I A . I B =

2kT
lAX

For example, if the maximum deviation, VE(max), is
±100 mV and the full scale output is 10 volts, then the
percentage error is
EA = VE(max) x 100 = 100 x 10-3 x 100 = ±.1.0%,
Vo(max)
10

with the assumption

2kT

\;113) (Ay + .;13) 13

AX~2kT

and

Ay~2kT

ql13

•

ql3

AtTA = +250 Cand 113= 13= 1 mA,

Linearity error may be measured by either of the following
methods:
1. Using an X - Y plotter with the circuit shown in Figure 5,
obtain plots for X and Y similar to the one shown above.
2. Use the circuit of Figure 4. This method nulls the level
shifted output of the multiplier with the original input.
The peak output of the null operational amplifier will be
equal to the error voltage, VE(max)'
One source of linearity error can arise from large signal nonlinearity in the X and Y -input differential amplifiers. To avoid
introducing error from this source, the emitter degeneration
resistors R X and Ry must be chosen large enough so that nonlinear base-emitter voltage variation can be ignored. Figures 17
and 18 show the error expected from this source as a function
of thevaluesof RX and Ry with an operating current of 1.0 rnA
in each side ofthe differential amplifiers (i.e., 13 = 113 = 1.0 mA).

7-382

2kT =2kT = 52 II.
ql13 q l 3
Therefore, with RX = Ry = 10 kS1 the above assumption is valid.
Reference to Figure 19 will indicate limitations of VX(max) or
VY(max) due to Vl and V7' Exceeding these limits will cause
saturation or "cutoff" of the input transistors. See Step 4 of
Section 3 (General Design Procedure) for further details.
2.1.4 Maximum Output Voltage Swing
The maximum output voltage swing is dependent upon the
factors mentioned below and upon the particular circuit being
considered.
For Figure 20 the maximum output swing is dependent
upon V+ for positive swing and upon the voltage at pin 1 for
negative swing. The potential at pin 1 determines the Quiescent level for transistors 05, 06, 07. and aS. This potential

MC1595L, MC1495L (continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

If an operational amplifier is used for level shift, as shown
in Figure 21, the output swing (of the multiplierl is greatly
reduced. See Section 3 for further details.

should be related so that negative swing at pins 2 or 14 does

not saturate those transistors. See Section 3 for further inform·
atian regarding selection of these potentials.

3. General Design Procedure

Selection of component values is best demonstrated by the
following example: assume resistive dividers are used at the X and

FIGURE 20 - BASIC MULTIPLIER

Y inputs to limit the maximum multiplier input to ±5.0 volts (Vx =

Vy [maxylor a ± 10-volt input IVX' = Vy'[maxll. ISee Figure 21).
V'
RX

RL

RI

Ry

If an overall scale factor of 1/10 is desired, then

v _ VX' Vy' (2V Xi (2Vyi
0-

10
RL

VX

Vy

!

Therefore, K
network).
12

} v,

14

MC1595L

2RL
K"-AX Ay 13

t'

for the multiplier (excluding the divider

except the power dissipation of the device. 13 and 113 will normally
be one or two milliamperes. Further, 13 does not have to be equal
to 113. and there is normally no need to make them different. For

Vo" K Vx Vy

3

= 4/10

= 4/10 VXVy ,

10

Step 1. The first step is to select current 13 and current 113.
There are no restrictions on the selection of either of these currents

(MC1495U

I

10

this example, let

13

3

R3

RI3

To set currents 13 and 113 to the desired value, it is only
necessary to connect a resistor between pin 13 and ground, and be·
tween pin 3 and ground. From the schematic shown in Figure 3,
V-

FIGURE 21 - MULTIPLIER WITH OP-AMPL, LEVEL SHIFT
-15V

-15 V

, - - -.......- -.......- - - - - . - - - - f - - -......_
RI
3k

R,

R,

3k

3k

0.1

14

12
RL
RL{

:8kk
OUTPUT
OFFSET
AOJUST

P4

X OFFSET
ADJUST

P2

2k
...'W......-+-----'\M-~-'II''''''"
10k

.. -15V

5.1 V

7-383

+15V

O.lf./F
~F

•

•

MC1595L. MC1495L (continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

it can be seen that the resistor values necessary are given by:
A13 + 500 n = IV-I-O.7 V
113

region when the maximum input voltages are applied (VX' = VV' =
10 V or Vx = 5.0 V. Vy = 5:0 VI. their respective collector voltage
should be at least a few tenths of a volt higher than the maximum

input voltage. It should also be noticed that the collector voltage
of transistors 03 and C4 are at a potential which is two diode-drops

A3 + 500 n = Iv-I-O.7 V
13

below the voltage at pin 1. Thus, the voltage at pin 1 should be about
two volts higher than the maximum input voltage. Therefore, to
handle +5.0 volts at the inputs, the voltage at pin 1 must be at least

Let Ir= -15 V

+7.0 volts. Let VI = 9.0 Vdc.
Since the current following into pin 1 is always equal to
213, the voltage at pin 1 can be set by placing a resistor, R1 from
pin 1 to the positive supply:

14.3 V
Then AI3+ 5OO = lmA orAI3=13.8kn
Let A13= 12kn
Similarly. R3 = 13.8 kn
Let A3 = 15 kn
However, for applications which require an accurate scale factor,

Let

V+=+15V

Th

A

the adjustment of R3 and consequently. '3. offers a convenient
method of making a final trim of the scale factor. For this reason,
as shown in Figure 21, resistor R3 is shown as a fixed resistor in

en

_ 15V-9V
1 -12) 11 mAl

series with a potentiometer.
For applications not requiringan exact scale factor (balanced

Al =3kn.

modulator. frequency doubler. AGe amplifier. etc.l. pins 3 and 13
can be connected together and a single resistor 1rom pin 3 to ground
can be used. In this case, the single resistor would have a value of
one-half the above calculated value for R13.

Step 2. The next step is to select RX and Ry. To insure
that the input transistors will always be active, the following conditions should be met:

Note that the voltage at the base of transistors 05. 06. 07 and 08
is one diode-drop below the voltage at pin 1. Thus, in order that
these transistors stay active, the voltage at pins 2 and 14 should be
approximately halfway between the voltage at pin 1 and the positivesupply voltage. For this example, the voltage at pins 2 and 14 should
be approximately 11 volts.

Step 5. Level Shifting

A good rule of thumb is to make 13Ay;;' 1.5 VYlmaxl and
113 AX ;;'I.5VXlmax)·
The larger the 13A Y and 113A X product in relation to Vy

For dc applications, such as the multiply, divide and squareroot functions, it is usually desirable to convert the differential
output to a single-ended output voltage referenced to ground.
The circuit shown in Figure 22 perfqrms this function. It can be
shown that the output voltage of this circuit is given by:

and Vx respectively, the more accurate the multiplier will be (see

Figures 17 and 181.
Let A X

= Ay = 10 kn

21Xly _ 2 VXVy
And since IA -18 = 12 -114 = -1-3- -13 A XAy
2ALVX'Vy'

Then Vo

= --:-:-:::--=-'-..,.....'4AXAXI3

where VX'Vy' is the voltage at the

input to the voltage dividers.

sinceVXlmaxl

= VYlmax) = 5.0voltsthevalueof RX = Ry = 10 kn

is sufficient.

FIGURE 22 - LEVEL SHIFT CIRCUIT

Step 3. Nowthat AX. Ay and 13 have been chosen. AL can
be determined:

v+
2AL

4

AXAyl3

10

K=---=R,

R,

4

or
110 k) 110 kill mAl

10

12

v2
V,

Thus AL = 20 kH.
114

Step 4. To determine what power-supply voltage is necessary
for this application, attention must be given to the circuit schematic
shown in Figure 3. From the circuit schematic it can be seen that
in order to maintain transistors 01. 02. 03 and 04 in an active

7-384

V14

RL

RL

MC1595L, MC1495L(continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

The choice of an operational amplifier for this application

possible as shown in Figure 23 where RV has been increased substantially to improve the Y linearity. and RX decreased somewhat
so as not to materially affect the X linearity, this avoids increasing
R L significantly in order to maintain a K of 0.1.
The versatility of the MC1595 IMC1495) allows the user to
to optimize its performance for various input and output signal
levels.

should have low bias currents, low offset current, and a high
common-mode input voltage range as well as a high common-mode
rejection ratio. The MC1556, and MC1741 operational amplifiers

meet these requirements.
Aeferring to Figure 21. the level shift components will be de·
termined. When Vx = Vy = 0, the currents 12 and 114 will be equal
to 113. I n Step 3. A L was found to be 20 kn and in Step 4. V2 and
V14 were found to be approximately 11 volts. From this information, Ro can be found easily from the following equation (neglect-

4. Offset and Scale Factor Adjustment

ing the operational amplifiers bias current):

And for this example. ~
20 kn
Solving for Ao. Ao
Thus. select Ao

+ 1 mA

4.1

Offset Voltages
Within the monolithic multiplier (Figure 31 transistor baseemitter junctions are typically matched within 1 mV and resistors
are typically matched within 2%. Even with this careful matching, an output error can occur. This output error is comprised
of X-input offset voltage, V-input offset voltage, and outputoffset voltage. These errors can be adjusted to zero with the techniques shown in Figure 21. Offset terms can be shown analytically by the transfer function:

= 15 V -11 V

Ao

= 2.6 kn

111

= 3.0 kn

Where K
= scale factor
Vx
= X input voltage
Vv
= V input voltage
VIOX = X input offset voltage
VIOV = Y input offset voltage
Vx off= X input offset adjust voltage
Vy off= Y input offset adjust voltage
Voo
= output offset voltage.

For Ao = 3.0 kn. the voltage at pins 2 and 14 is calculated to be
V2

= V14 = 10.4 volts.

The linearity of this circuit (Figure 211 is likely to be as good
or better than the circuit of Figure 5. Further improvements are

FIGURE 23 - MULTIPLIER WITH IMPROVED LINEARITY
-15V

-15V

+15V

7.5k

3k

27k

3k

3k

10

14

10k

V'y
10k

-VX Vy

MC1595l

± 10 v

VO

(MC1495LJ
10k

V'X
10k

13

12

13k

40k
33k

12k
5k

OUTPUT

10k

OFFSET
ADJUST

SCALE
FACTOR
ADJUST

Y OFFSET
ADJUST

X OFFSET
ADJUST
20k

15k

15k

+15V

-15V
20k
2k

2k

7-385

=---w-

I

..
MC1595L, MC1495L(continued)

OPERATION AND APPLICATIONS INFORMATION

5.2 Squaring Circuit

x, Y and Output Offset Voltages

o

~

If the two inputs are tied together, the resultant function is
squaring; that is Vo = KV2 where K is the scale factor. Note
that all error terms can be eliminated with only three adjustment
potentiometers, thus eliminating one of the input offset adjustments. Procedures for nulling with adjustments are given as
follows:

Output
Offset
Vx

X Offset

(contjnued)

1. AC Procedure:
(a) Connect oscillator (1 kHz. 15 Vpp) to input
(b) Monitor output at 2 kHz with tuned voltmeter
and adjust P3 for desired gain (be sure to peak response
of the voltmeter)
Ic) Tune voltmet~r to 1 kHz and adjust P1 for a minimum output voltage
(d) Ground input and adjust P4 (output offset) for
zero volts dc output
(el Repeat steps a through d as necessary.
2. DC Procedure:
(a) Set Vx = Vv = 0 V and adjust P4 (output offset
potentiometer) such that V 0 = 0.0 Vdc
(b) Set Vx = Vv = 1.0 V and adjust P, (V input
offset potentiometer) such that the output voltage is
+0.100 volts
(c) Set Vx = Vv = 10 Vdc and adjust P3 such that the
output voltage is + 10.00 volts
(d) Set Vx = Vv = -10 Vdc. Repeat steps a through
d as necessary.

Y Offset

For most de applications. all three offset adjust potentiometers
P2. P4) will be necessary. One or more offset adjust

(P,.

potentiometers can be el iminated for ae applications (See Figures

2S. 29. 30. 31),
If well regulated supply voltages are available. the offset adjust circuit of Figure 13 is recommended. Otherwise, the circuit
of Figure 14 will greatly reduce the sensitivity to power supply
changes.
4.2 Scale Factor
The scale factor. K. is set by P3(Figure 21), P3varies 13which
inversely controls the scale factor K. It should be noted that
current 13 is one-half the current through R 1. R 1 sets the bias
level for aS. as. 07. and aS (See Figure 3). Therefore. to be
sure that these devices remain active under all conditions of input
and output swing. care should be exercised in adjusting P3 over
wide voltage ranges (see Section 3, General Design Procedurel.
4.3 Adjustment Procedures

FIGURE 24 - BASIC DIVIDE CIRCUIT

The following adjustment procedure should be used to null
the offsets and set the scale factor for the multiply mode of
operation. (See Figure 21)

,. X I nput Offset
(a) Connect oscillator (1 kHz. 5 Vpp sinewave) to the
"V" input (pin 4)
(b) Connect "X" input (pin 9) to ground
(c) Adjust X offset potentiometer, P2, for an ac null
at the output
2. V Input Offset
(a) Connect oscillator (1 kHz. 5 Vpp sinewave) to the
"X" input (pin 9)
(b) Connect "V" input (pin 4) to ground
(c) Adjust "V" offset potentiometer. P,.for an ac null
at the output
3. Output Offset
(a) Connect both "X" and "V" inputs to ground
(b) Adjust output offset potentiometer. P4. until the
output voltage Vo is zero volts dc
4. Scale Factor
(a) Apply +10 Vdc to both the "X" and "V" inputs
(b) Adjust P3 to achieve + 10.00 V at the output.
5. Repeat steps 1 through 4 as necessary.

V, __

Vy

Consider the circuit shown in Figure 24 in which the multiplier is placed in the feedback path of an operational amplifier.
For this configuration, the operational amplifier will maintain
a "virtual ground" at the inverting 1-) input. Assuming that the
bias current of the operational amplifier is negligible, then '1 =
12 and

Solving for VV.

5.1 Multiply
The circuit shown in Figure 21 may be used to multiply
Signals from dc to 100 kHz. Input levels to the actual multiplier are 5.0 V (max). With resistive voltage dividers the maximum could be very large - however, for this application twoto-one dividers have been used so that the maximum input
level is 10 V. The maximum output level has also been designed
for 10 V (max).

>--0. . . . >---..

5.3 Divide Circuit

The ability to accurately adjust the MC1595 (MCI495)
depends upon the characteristics of potentiometers P 1
through P4. Multi-turn, infinite resolution potentiometers with low-temperature coefficients are recommended.
5. DC Applications

-.,I,

--~~--_*--o_~

If

KVXVV

-VZ

Rl

R2

-Rl Vz
Vv =R2 K VX·

7-386

(2)

Rl = R2
-VZ
VV=-KVX

If

(1)

(3)

Rl = KR2
-VZ
VV=-_·
Vx

(4)

MC1595L, MC1495L (continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

Hence, the output voltage is the ratio of Vz to Vx and provides
adivide function. Thisanalysis is, of course, the ideal condition.

From equation 7, the percentage error is inversely related to
voltage Vz O.e., for increasing values of VZ, the percentage
error decreasesl.
A circuit that performs the divide function is shown in

If the multiplier error is taken into account. the output voltage
is fau nd to be

Figure 25.
Vy

= _

[~] Vz
R2 K Vx

+ "E

•

Two things should be emphasized concerning Figure 25.
1. The input voltage (V'X) must be greater than zero and
must be positive. This insures that the current out of
pin 2 of the multiplier will always be in a direction com-

(5)

KVX

where l":I.E is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of Vy. For example, assume
that Rl = R2. and K = 1/10. For these conditions the output

patible with the polarity of VZ.
2. Pins 2 and 14 of the multiplier have been interchanged
in respect to the operational amplifiers input terminals.
I n this instance, Figure 25 differs from the circuit connection shown in Figure 21; necessitated to insure negative
feedback around the loop.

of the divide circuit is given by:
-10 Vz
10 <>E
Vy=--- +-Vx
Vx
From equation 6, it is seen that only when Vx

A Suggested Adjustment Procedure for the Divide Circuit

(6)

1. Set Vz =- 0 volts and adjust the output offset potentio=

meter (P 4) until the output voltage (Va) remains at some
(not necessarily zero) constant value as VX' is varied
between +1.0 volt and +10 volts.

10 V is the

error voltage of the divide circuit as low as the error of the
multiply circuit. For example, when Vx is small, (0.1 volt)
the error voltage of the divide circuit can be expected to be a
hundred times the error of the basic multiplier circuit.
I n terms of percentage error,

2. Keep Vz at a volts, set VX' at +10 volts and adjust the
Y input offset potentiometer (P1) until Va =- a volts.
3. Let Vx' =- Vz and adjust the X input offset potentiometer (P2) until the output voltage remains at some (not
necessarily - 10 volts) constant value as Vz =- VX' is
varied between +1.0 and +10 volts.

percentage error = error x 100%
actual

4. Keep VX' =- Vz and adjust the scale factor potentiometer
(P31 until the average value of Vo is -10 volts as Vz =VX' is varied between +1.0 volt and +10 volts.

or from equation (5),

5. Repeat steps 1 through 4 as necessary to achieve optimum performance.

"E
P.E·o

[R2]"E
or R1KVX
] Vz = AI VZ'

[R2 K

5.4 Square Root
A special case of the divide circuit in which the two inputs to
the multiplier are connected together is the square root function

Vx

7-387

MC1595L, MC1495L(continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

FIGURE 26 - BASIC SQUARE ROOT CIRCUIT

6. AC Applications
The applications that follow demonstrate the versatility of the
monolithic multiplier. If a potted multiplier is usad for these
cases, the results generally would not be as good because the potted
units have circuits that, although they optimize de multiplication
operation. can hinder ae applications.

6.1 Frequencv doubling often is done with a diode where the
fundamental plus a serie. of harmonics are generated. However,
extensive filtering is required to obtain the desired harmonic,

Vz

>----<>-....._v,
KV[l2: -VZ

and the second harmonic obtained under this technique usually
is small in magnitude and requires amplification.

When a multiplier is used to double frequency the second
harmonic is obtained directly, except for a dc term, which can
be removed with ac coupling.

="
"

eo = KE2 co,2 wt

O
V

eo = KE2 (1 + cos 2wt).
2
as indicated in Figure 26. This circuit may suffer from
latch-up problems simllar to those of the divide circuit. Note
that only one polarity of input is allowed and diode clamping
(see Figure 27) protects against accidental latch-up.
This circuit also may be adjusted in the closed-loop mode as
follows:

1. Set Vz to - 0.01 volts and adjust P4 (output offsell for
Va = +0.316 volts, being careful to approach the output
from the positive side to preclude the effect of the output diode clamping.

2. Set Vz to -0.9 volts and adjust P2 (X adiust) for Va =
+3.0 volts.
3. Set Vz to -10 volts and adjust P3 (scale factor adjust)
for Va = +10 volts.
4. Steps 1 through 3 may be repeated as necessary to achieve
desired accuracy.

A potted multiplier can be used to obtain the double frequency component, but frequency would be limited by its
internal level-shift amplifier. In the monolithic units, the amplifier is omitted.
In a typical doubler circuit, conventional ± 15·volt supplies
are used. An input dynamic range of 5.0 volts peak-to-peak is
allowed. The circuit generates wave-forms that are double frequency; less than 1% distortion is encountered without filtering.
The configuration has been successfully used in excess of 200
kHz; reducing the scale factor by decreasing the load resistors
can further expand the bandwidth.

A slightly modified version of the MC1595 (MC14951 the MC1596 (MC14961 - has been successfully used as a doubler
to obtain 400 MH z. (See Figure 28.1
6.2 Figure 29 represents an application for the monolithic
multiplier as a balanced modulator. Here, the audio input signal

is 1.6 kHz and the carrier is 40 kHz.

7-388

MC1595 L, MC1495 L (continued)

OPERATION AND APPLICATIONS INFORMATION (continued)

The defining equation for balanced modulation is

FIGURE 28 - FREQUENCY DDUBLER
Hy

HX
8.2k

B.2k

VCC=+15V

H,
1

KEcEm
- 2 - - [cos Iwc + wmlt + cos Iwc - wmltl

3.0k

Ecoswt

H,

I
~

0.5
0.25

O.3J/lF

2 rnA

~

3

00

13
11k

3k

~IIlF

"

1
50

"

-12V

7-390

0.2 0.' 0.6 O.B 1.0
VAGC(VOlTS)

NOTE
Linear gaincrmtrol ola l-voltpeak·ta-peak signal is
perfarmed with a O·to·l-volt control voltage. IfVCis
O.5volttheoulputwill be O.5volt p.p.

1.2

MC1595L, MC1495L (continued)

OPERATIONS AND APPLICATIONS
INFORMATION INDEX
1. THEORY OF OPERATION
2. DESIGN CONSIDERATIONS

2.1 General
2.1.1 Linearity, Output Error, ERX or ERY
2.1.2 3·dB Bandwidth and Phase Shift
2.1.3 Maximum Input Voltage
2.1.4 Maximum Output Voltage Swing
3. GENERAL DESIGN PROCEDURES
4. OFFSET AND SCALE FACTOR ADJUSTMENT

4.1 Offset Voltages
4.2 Scale Factor
4.3 Adjustment Procedure
5. DC APPLICATIONS

5.1
5.2
5.3
5.4

Multiply
Squaring Circuit
Divide Circuit
Square Root

6. AC APPLICATIONS

6.1 Frequency Doubler
6.2 Balanced Modulator
6.3 Amplitude Modulation
6.4 Linear Gain Control

7-391

MC1596
MC1496·

BALANCED MODU LATOR-DEMODU LATOR

Specifications and Applications
InforIllation

BALANCED
MODULATOR - DEMODULATOR
INTEGRATED CIRCUIT
SILICON
EPITAXIAL PASSIVATED

MONOLITHIC BALANCED
MODULATOR - DEMODULATOR
· .. designed for use where the output voltage is a product of an input
voltage (signal) and a switching function (carrier). Typical applications
include suppressed carrier and amplitude modulation, synchronous de·
tection, FM detection, phase detection, and chopper applications.
Excellent Carrier Suppression - 65 dB typ @ 0.5 MHz
- 50 dB typ@ 10 MHz
• Adjustable Gain and Signal Handling
• Balanced I nputs and Outputs
• High Common· Mode Rejection - 85 dB typ
•

FIGURE 1 - SUPPRESSED-CARRIER
OUTPUT WAVEFORM

"""

to,_

through substrate.

Pin 14elllctrically

connected
to substrate

L SUFFIX

G SUFFIX
METAL PACKAGE

CERAMIC PACKAGE

CASE 602A

CASE 632 CTO·116)

FIGURE 2 - AMPLITUDE·MODULATION
OUTPUT WAVEFORM

FIGURE 3 - SUPPRESSED-CARRIER SPECTRUM

•

\\

Pin 10 electTlcally
connected

FIGURE 4 - AMPLITUDE·MODULATION SPECTRUM

FIGURE 6 - TYPICAL MODULATOR CIRCUIT

FIGURE 5 - CIRCUIT SCHEMATIC
HI

r-_I====:::;:=+===~vo. OUTPUT
I+)F

RL
3.9k

i-cH'-+.

+v,

MC159SG

DH

~~~~~L VSA'~":;-)----1======t:==~=:iGAIN

f'-o--.... -v,
ADJUST

C

BIAS

Eo--~--+-------I

500

v- J o - - - 4 - - - 4 -_ _ _ _--J

PIN CONNECTION CHART
ABC D E F G H I J
G Pkg. 1 2 3 4 5 6 7 8 9 10
L Pkg. 1 2 3 4 5 6 8 1012 14

See Packaging Information Section for outline dimensions.

7-392

L..-----=----+v·-8Vd,

15

S.ak

MC1596, MC1496 (continued)
MAXIMUM RATINGS* (TA = +2SoC unless otherwise noted)
Rating

Symbol

Value

Unit

av

30

Vdc

V7 - Vs
V4- V ,

+S.O
±(S+15Re l

Vdc

Maximum Bias Current

IS

10

mA

Power Dissipation (Package Limitation)
Ceramic Dual In-Line Package

Po
57S
3.SS

mW
mW/oC

6S0
4.S

mW
mW/oC

Applied Voltage
(VS - V7. Vs - VI. V9 - V7. V9 - VS. V7 - V4. V7 - VI.
Vs - V4. Vs - VS. V2 - VS. V3 - VSI
Differential Input Signal

Derate above T A = +2S o C
Metal Package
Derate above T A

= +2S o C

Operating Temperature Range

°c

TA
MC1496
MC1596

o to +70
-55 to +125

Storage Temperature Range

T stg

-65 to +150

°c

ELECTRICAL CHARACTERISTICS* (V+ = +12 Vdc, V- = -8.0 Vdc, IS = 1.0 mAde, R L = 3.9 kn, Re = 1.0 kn.
TA = +2SoC unless otherwise noted) (All input and output characteristics are single·ended unless otherwise noted.)
MC1596
Characteristic
Carrier Feedthrough

Vc = 60 mV(rms) sine wave and

Fig

Note

Symbol

7

1

VCFT

-

fC = 1.0 kHz
fC= 10MHz

offset adjusted to zero

Min

-

Typ

MC1496
Max

Min

-

40
140

-

0.04
20

0.2
100

-

Typ

Max

-

-

40
140

-

-

0.04
20

0.4
200

Vc = 300 mVp·p square wave:
offset

mVlrms)

adjusted to zero

-

fC= 1.0kHz
fC = 1.0 kHz

offset not adjusted

7

Carrier Suppression

2

fS = 10 kHz. 300 mVlrms)
fC = 500 kHz. 60 mVlrms) sine wave
fC = 10 MHz. SO mVlrms) sine wave

fS

= 1.0 kHz.

-

= 50 ohms)

10

S

Vc = 60 mV(rms) sine wave

Signal Gain
Vs = 100 mV(rms), f

= 300 mV(rms)

sine wave

= 1.0 kHz; IVcl = 0.5

Single·Ended Input Impedance. Signal Port. f

-

40

-

-

65
50

-

k
MHz

-

300

-

-

300

-

-

80

-

-

so

-

12

3

8

-

Single-Ended Output Impedance. f
Para lie I Output Resistance
Parallel Output Capacitance

= 5.0 MHz

= 10 MHz

8

Input Bias Current

11+14
IbS ~ - 2 - ; IbC

AVS

2.5

3.5

-

2.5

3.5

-

V/V

200
2.0

-

200
2.0

-

kfl.
pF

40
5.0

-

-

40
5.0

-

-

kfl.
pF

-

12
12

25
25

-

12
12

30
30

Vdc

Parallel I nput Resistance
Parallel I nput Capacitance

9

fjp

-

cip

-

rap
cop

-

-

Average Temperature Coefficient of Input Offset Current

9

Output Offset Current
116- 19)
Average Temperature Coefficient of Output Offset Current

-

-

J.lA
IbS
IbC

9

-

-

-

17+18
=-2-

Input Offset Current
liaS = 11- 14; lioC = 17 -IS

ITA

BW3dB

S5
50

300 mV(rms) sine wave

Signal Input Port, Vs
Ivel = 0.5 Vdc

ITA

dB

VCS
50

Transadmittance Bandwidth (Magnitudel I R L
Carrier Input Port,

Unit

IN(rmsl

-

-

J.lA

IliaSl
Iliael

-

-

0.7
0.7

5.0
5.0

-

0.7
0.7

7.0
7.0

-

ITCliol

-

2.0

-

-

2.0

-

nA/oC

9

-

11001

-

14

50

-

14

80

J.lA

9

-

ITClool

-

90

-

-

90

-

nA/oC

= -55a C to +125 0 C)

= -55 0 C to + 125 0 C)

Common-Mode I nput Swing. Signal Port, fS

11

4

CMV

-

5.0

-

-

5.0

-

Vp-p

Common-Mode Gain. Signal Port. fS
Ivel = 0.5 Vdc

11

-

ACM

-

-85

-

-

-S5

-

dS

Common-Mode Quiescent Output Voltage (Pin 6 or Pin 9)

12

-

Va

-

8.0

-

-

8.0

-

Vdc

Differential Output Voltage Swing Capability

12

-

V out

-

8.0

-

-

S.O

-

Vp-p

9

S

+

-

2.0

-

2.0

4.0

10

-

3:0

:4.0

-

3.0

5.0

Po

-

33

',"",-.:.

-

33

-

= 1.0 kHz
= 1.0 kHz,

Power Supply Current

16+ 19

10

110
DC Power Dissipation

* Pin

number references pertain to this deVice when packaged
device refer to the PIN CONNECTION CHART
on the first page of this specification.

9
In

5

3.0,
"

mAdc

mW

a metal can. To ascertain the corresponding pin numbers for a ceramic packaged

7-393

I

MC1596, MC1496 (continued)

GENERAL OPERATING INFORMATION'
Note 1 - Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at carrier
frequency with only the carrier applied (signal voltage = 0).
Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R 1 of
Figure 71.

Note 2 - Carrier Suppression

Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels speci-

base current. PD = 215 (V6'- Vl01 + 15 (V5 - Vl01 where subscripts refer to pin numbers.
Note 6 - Design Equations
The following is a partial list of design equations needed to
operate the circuit with other supply voltages and input conditions. See Note 3 for Re equation.
A. Operating Current
The internal bias currents are set by the conditions at pin 5.
Assume:

fied.
Carrier suppression is very dependent on carrier input level, as
shown in Figure 24. A low value of the carrier does not fully

switch the upper switching devices, and results in lower signal
gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The
MC1596 has been characterized with a 60 mV(rms) sinewave
carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is
generally recommended for balanced modulator applications.
Carrier feedthrough is independent of signal level, VS. Thus
carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained
in the signal-input transistor pair - or harmonics of the modulating
signal will be generated and appear in the device output as spurious
sidebands of the suppressed carrier. This requirement places an
upper limit on input-signal amplitude (see Note 3 and Figure 22).
Note also that an optimum carrier level is recommended in Figure 24 for good carrier suppression and minimum spurious sideband generation.
At higher frequencies circuit layout is very important in order
to minimize carrier feedthrough. Shielding may be necessary in
order to prevent capacitive coupling between the carrier input
leads and the output leads.

I B« I C fa r all transistors
then:
where:

The MC1596 has been characterized for the condition 15 = 1.0
mA and is the generally recommended value.
B. Common-Mode Quiescent Output Voltage

Note 7 - Biasing
The MC1596 requires three dc bias va Itage levels which must be
set externally. Guidelines for setting up these three levels include
maintaining at least 2 volts collector-base bias on all transistors
while not exceeding the voltages given in the absolute maximum
rating table;

Note 3 - Signal Gain and Maximum I nput Level

30 Vdc;;' [(V6. VgI - (V7. vsIl ;;, 2 Vdc

Signal gain (single-ended) at low frequencies is defined as the
voltage gain,

30Vdc;;' [(V7.VsI-(Vl.V4Il;;, 2.7Vdc

VA

AVS

RL

= Vs = Re + 2re where

30Vdc;;' [(Vl.V41-(V5Il;;' 2.7Vdc

26 mV
re = 15 (mAl

The foregoing conditions are based on the following approximations:

A constant dc potential is applied to the carrier input terminals to
fully switch two of the upper transistors "on" and two transistors
"off" (VC = 0.5 VdcJ. This in effect forms a cascade differential
amplifier.
Linear operation requires that the signal input be below a critical value determined by RE and the bias current 15

I

R5 is the resistor between pin
5 and ground
V at T A = +250 C

¢ = 0.75

Vs ,; 15 RE (Volts peakl

Bias currents flowing into pins 1, 4, 7, and 8 are transistor base
currents and can normally be neglected if external bias dividers
are designed to carry 1.0 mA or more.
Note 8 - Transadmittance Bandwidth

Note that in the test circuit of Figure 12, Vs corresponds to a
maximum value of 1 volt peak.
Note 4 - Common-Mode Swing
The common-mode swing is the voltage which may be applied
to both bases of the signal differential amplifier, without saturating
the current sources or without saturating the differential amplifier
itself by swinging it into the upper switching devices. This swing
is variable depending on the particular circuit and biasing conditions chosen (see Note 6).

Carrier transadminance bandwidth is the 3-dB bandwidth of
the device forward transadmittance as defined by:

Y21C =

io (each sideband)
Vs {slgnali

I

Va = 0

Signal transadmittance bandwidth is the 3-d B bandwidth of the
device forward transadmittance as defined by:
io (signall
Y21S = Vs {signali

I

V c = 0.5 Vdc. Va = 0

Note 5 - Power Dissipation
Power dissipation, PD. within the integrated circuit package
should be calculated as the summation of the voltage-current products at each port, i.e. assuming V9 = V6, 15 = 16 = 19 and ignoring

7-394

*Pin number references pertain to this device when packaged in a
metal can. To ascertain the corresponding pin numbers for a
ceramic packaged device refer to the PIN CONNECTION CHART
on the first page of this specification.

MC1596, MC1496 (continued)

connected directly to each input using short leads. This will reduce

Note 9 - Coupling and Bypass Capacitors C1 and C2

the Q of the source-tuned circuits that cause the oscillation.

Capacitors C1 and C2 (Figure 7) should be selected for a re-

actance of less than 5.0 ohms at the carrier frequency.
SIGNAL INPUT
(PINS' &4)

Note 10 - Output Signal, Va

1

O'---~~Ir'---~

I,oPF

The output signal is taken from pins 6 and 9, either balanced
or single·ended. Figure 14 shows the output levels of each of the
two output sidebands resulting fram variations in both the car·
rier and modulating signal inputs with a single-ended output

connection.
An alternate method for low·frequency applications is to insert

Note 11 - Signal Port Stability

a 1 k-ohm resistor in series with the inputs, pins 1 and 4. In this
case input current drift may cause serious degradation of carrier
suppression.

Under certain values of driving source impedance, oscillation
may occur. In this event, an RC suppression network should be

TEST CIRCUITS
FIGURE 7 - CARRIER REJECTION AND SUPPRESSION

Ik

FIGURE 8 - INPUT-OUTPUT IMPEDANCE

+12 Vdc

I k

R, = I k

R,
RL
3.9 k

C2
CARRIER 0.1 ~F
INPUTVC --.)
Vs
MODULATING
SIGNAL
10 k
INPUT

0.5 V

7
8

+Vo

MCI596
MCI496
51

'liD IS

-Zout
-Vo

Zirl-

-Vo

,

10

+Vo

MCI596
MCI496
10
6.8 k

6.8 k

V-8 Vdc
-8 Vdc

FIGURE 10 - TRANSCONDUCTANCE BANDWIDTH

FIGURE 9 - BIAS AND OFFSET CURRENTS

+12 Vdc

Ik

Ik

R,
2k

CARRIER O.I"F
INPUT VC--.)f-4-------<>-':-I
VS~--r_--~r_-~~

MODULATING
SIGNAL
INPUT
10 k

10

~ liD

MCI596
MCI496

1-:c.--4-...,-vo

r--t:'-lr5~1~~rl-0--,J

6.8 k

6.8 k

L-------1V-8 Vdc

-8 Vdc

Pin number references pertain to this device when packaged in a metal can. To ascertain the corresponding pin numbers for a ceramic
packaged device refer to the PIN CONNECTION CHART on the first page of this specification.

7-395

MC1596, MC1496 (continued)

TEST CIRCUITS (continued)
FIGURE 12 - SIGNAL GAIN AND OUTPUT SWING

FIGURE 11 - COMMON·MODE GAIN
+12 Vdc

+12 Vdc

1k
0.5 V

1k

t-c......-+... +Vo

..... +Vo
t-c>--......... -Vo
t-c>-4~+

Vs

Vs'---~------~

t-c>--........ -Vo
10

10

6.8 k

50

15=
ACM = 20 log

-8 Vdc

1 rnA

vs

t

6.8k

IVol

-8 Vdc

Pin number references pertain to this device when packaged in a metal can. To ascertain the corresponding pin
numbers for a ceramic packaged device refer to the PIN CONNECTION CHART on the first page of this specification.

TYPICAL CHARACTERISTICS
Typical characteristics were obtained with circuit shown in Figure 7, fc

z:::

500 kHz (sine wavs) ..

Vc = 60 mV(rms), fS "" 1 kHz, Vs = 300 mV(rms), TA = +2SoCunlessotherwise noted.

FIGURE 14 - SIGNAL·PORT PARALLEL·EQUIVALENT
INPUT RESISTANCE versus FREQUENCY

FIGURE 13 - SIDEBAND OUTPUT versus CARRIER LEVELS
1.0M

~ 2.0

0;

z:

5

~ 1.6

+rip

i!

~

w
'-'

~ 100

SIGNAL INPUT = 600 rnV

Q

51.2

....... ~

;:s

u..

/1-""

~ 0.8
=>
t::;
~ 0.4

~~

'"=>t-

l

[ij

400 rnv

'"t-

300rnV

!!:

200 rnV

-'
w
-'

100rnV

;i;

~

r-

0

'"

~

50

0

0

-rip

"-

150

100

200

"

10
5.0

1.0
1.0

5.0

10

50

100

f. FREQUENCY (MHz)

CARRIER LEVEL (rnVlrrns))

•

1.

~

/ ~
V f.--"

Q

~
=>

-

,. 500

FIGURE 15 - SIGNAL-PORT PARALLEL·EQUIVALENT
INPUT CAPACITANCE versus FREQUENCY

FIGURE 16 - SINGLE·ENDED OUTPUT
IMPEDANCE versus FREQUENCY

5.0

140

1

~4.0

120

12~

U

100

1

'-'

80

~

u..

;::

0;::'"

'"~ 3.0
t-

~
;;; 20

;i;
t-

....... 1-""

60

~.

'"'" 1.0

40

j-

20

~
6.o~

cop

'"-'

4.D~

-'

~

o
1.0

u

8.05

rop

2.0

5.0

10

20

50

o

100

f. FREQUENCY (MHz)

"
o

1.0
f. FREQUENCY (MHzi

7-396

10

~

i"

2.Of
0
100

MC1596, MC1496 (continued)

TYPICAL CHARACTERISTICS (continued)
Typical characterlstici were obtained with circuit shown In Figure 7. fC = 500 kHZ' (sina wave).
Vc = 60 mV(rms). 1S = 1 kHz, Vs - 300 mV(rms). T A =+250 C unless otherwise noted.

FIGURE 17 - SIDEBAND AND SIGNAL PORT
TRANSADMITTANCES versus FREQUENCY
1.0
0.9

o.S

:;

1=

0.5

";;\z

0.4

-

IV:"I(:II~~tL)

I

0.3

'"

FIGURE 18 - CARRIER SUPPRESSION
versus TEMPERATURE

v:- IVout

V21 '" lout

0.1

I

o

0.1

=

0

!z

MCI596

20

"

I

m
g: 30
~
'"w

40

5'"

50

a:

I11111

IIIIII

_MCI496~

(+10 0 C)

IVel;; 0.5 Vdc

100

"

\.. /

-50

-25

fC, CARRIER FREQUENCY (MHz)

~ +10

f

'"w

;'"
">
"w
~

-

RL=3.9k (Standard
- Re= I k Test Circuit)

-10

~

'"~

"-

"'

~

-30
0.01

+125

~

I
RL=3.9k
Re = 2 kl

21C

~

'/

r-....

./

Re = I k
fC

IIIIII AV=-~J
IIIIIII I I ~el+1 ~~ell

3fC

~

1.0

0.1

+150 +115

RL=3.9k
Re=500n
I'

I~~I= todn
IVCI = 0.5 Vdc

-20

+25
+50
+15 +100
TA. AMBIENT TEMPERATURE (OC)

FIGURE 20 - CARRIER SUPPRESSION versus FREQUENCY

FIGURE 19 - SIGNAL·PORT FREQUENCY RESPONSE

+ 20

.....1--

...........

10
-15

1000

-

........

~
> 60

I I I IIIII

1"1 '111111
10

1.0

V
0
out"

"'
1\
'"

10

10

100

0.5

0.1

---

1.0

5.0

f--

10

50

IC. CARRIER FREQUENCY (MHz)

f, FREQUENCY (MHz)

FIGURE 22 - SIDEBAND HARMONIC SUPPRESSION
versus INPUT SIGNAL LEVEL

FIGURE 21 - CARRIER FEEDTHROUGH versus FREQUENCY

~

1O . . . .

-'

~

10

ffi
;5

'" CD 20
z:E

~ ~ 30

u;:li

:!i,,;;;~ 40

IC± 31S...........

0",

uj

!::!::!

50

L--- ~

"''''
ez'"t3 60

fC~ V

[il
0.5

1.0

5.0

10

~

70

~

80

o

50

IC, CARRIER FREQUENCY (MHz)

V

200

400

V
V
600

VS. INPUT SIGNAL AMPLITUDE (mV[rms[)

7-397

800

MC1596, MC1496 (continued)

TYPICAL CHARACTERISTICS (continued I
FIGURE 23 - SUPPRESSION OF CARRIER HARMONIC
SIDEBANDS versus CARRIER FREQUENCY

FIGURE 24 - CARRIER SUPPRESSION
versus CARRIER INPUT LEVEL

.,
:=!
0

~
il::

21C: IS

::l

21C ± 21S

;3 50

~

- -

a;

0.5
1.0
5.0
IC. CARRIER FREQUENCY (MHz)

10

30
40



I--

0.1

20

IIIII

lit--

70
0.05

10

z

3IC:IS

60
70
50

- " "'

IC=10MHz- r--

./'"
./

,~

~

o

..-

100

-

IC = 500 kHz

I--

200

--r

300

400

500

VC. CARRIER INPUT LEVEL (mV[rmsJ)

OPERATIONS INFORMATION

The MC1596/MC1496. a monolithic balanced modulator circuit, is shown in Figure 5.
This circuit consists of an upper quad differential amplifier

driven by a standard differential amplifier with dual current
sources. The output collectors are cross-coupled so that full-wave
balanced multiplication of the two input voltages occurs. That is.

the output signal is a constant times the product of the two input
signals.
\
Mathematical analysis of linear ae signal multiplication indicates that the output spectrum will consist of on IV the sum and
difference of the two input frequencies. Thus, the device may be
used as a balanced modulator, doubly balanced mixer, product
detector, frequency doubler, and other applications requiring
these particular output signal characteristics.
The lower differential amplifier has its emitters connected to
the package pins so that an external emitter resistance may be
used. Also, external load resistors are employed at the device
output.

The upper quad differential amplifier may be operated either
in a linear or a saturated mode. The lower differential amplifier
is operated in a linear mode for most applications.
For low-level operation at both input ports, the output signal
will contain sum and difference frequency components and have
an amplitude which is a function of the proouct of the input signal
ampli tudes.
For high-level operation at the carrier input port and linear
operation at the modulating signal port, the output signal will
contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of
the carrier frequency. The output amplitude will be a constant
times the modulating signal amplitude. Any amplitude variations
in the carrier signal will not appear in the output.

The linear signal handling capabilities of a differential amplifier
are well defined. With no emitter degeneration, the maximum
input voltage for linear operation is approximately 25 mV peak.
Since the upper differential amplifier has its emitters internally
connected, this voltage applies to the carrier input port for all
conditions.
Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range may be
adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression:

V =(15) (RE)VOlts peak.
This expression may be used to compute the minimum value of
Re for a given input voltage amplitude.

The gain from the modulating signal input port to the output is
the MC1596/MC1496gain parameter which is most often 01 interest
to the designer. This gain has significance only when the lONer
differential amplifier is operated in a linear mooe, but this includes
most applications of the device.
As previously mentioned, the upper quad differential amplifier
may be operated either in a linear or a saturated mode. Approximate gain expressions have been developed for the MC15961
MC1496 lor a low-level modulating signal input and the following
carrier input conditions:

1)
2)
3)
4)

Low-level dc
High-level dc
Low-level ac
High-level ac

These gains are summarized in Table 1, along with the frequency components contained in the output signal.

Pin number references pertain to this device when packaged in a metal can. To ascertain the corresponding pin numbers for a ceramic
packaged device refer to the PIN CONNECTION CHART on the first page of this specification.

7-398

MC1596, MC1496 (continued)

OPERATIONS INFORMATION (continued)
FIGURE 25 - TABLE 1
VOLTAGE GAIN AND OUTPUT FREQUENCIES

Carrier Input
Signal (VC)
Low-level de

Approximate
Voltage Gain

Output Signal
Frequency(s)

the gain expression given is for the output amplitude of
each of the two desired outputs. fC + fM and fC - fM3. All gain expressions are for a single-ended output. For

RL Vc
2(RE + 2re)

High-level dc

NOTES:
1. Low-level Modulating Signal, VM. assumed in all cases.
Vc is Carrier I nput Voltage.
2. When the output signal contains multiple frequencies,

(~T)

RL
RE + 2re

fM

~ differential output connection, multiply each expression by two.
4. R L = Load resistance.
5. RE = Emitter resistance between pins 2 and 3.
6. re = Transistor dynamic emitter resistance. At +250 C;

fM

26 mV
re"" 15 (mA)

RL Vc(rms}
Low-level ae

High-level ac

2.J2(~T)(RE + 2re}
0_637 RL
RE + 2re

fC±fM

7. K = Boltzmann's Constant, T = temperatur"e in degrees
Kelvil.'1. q = the charge on an electron.

fC±fM. 3fC±fM.
5fC±fM. ___

qKT ~ 26 mV at room temperature

APPLICATION INFORMATION

Double sideband suppressed carrier modulation is the basic
application of the MC1596/MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1596/MCl496 with a single dc supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed for
operation with a single +12 Vdc supply. Performance of this circuit is similar to that of the dual supply modulator.

carrier signal at the carrier input and an AM signal at the SSB
input.
The carrier signal may be derived from the intermediate frequency signal or generated locally. The carrier signal may be introduced with or without modulation, provided its level is
sufficiently high to saturate the upper quad differential amplifier.
If the carrier signal is modulated. a 300 mV(rms} input level is
recommended.

AM Modulator

Doubly Balanced Mixer

The circuit shown in Figure 27 may be used as an amplitude
modulator with a minor modification.
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the proper
amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range. Therefore,
the modulator may be modified for AM operation by changing
two resistor values in the null circuit as shown in Figure 28.

The MC1596/MC1496 may be used as a doubly balanced
mi'xer with either broadband or tuned narrow band input and
output networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mV(rms).
Figure 30 shows a mixer with a broadband input and a tuned
output.

Product Detector
The MC1596/MC1496 makes an excellent SSB product detector (see Figure 29)_
This product detector has a sensitivity of 3.0 microvolts and a
dynamic range of 90 dB when operating at an intermediate frequency of 9 MHz_
The detector is broadband for the entire high frequency range.
For operation at very low intermediate frequencies down to 50
kHz the 0_1 JIF capacitors on pins 7 and B should be increased to
1.0 /-IF _ Also. the output filter at pin 9 can be tailored to a
specific intermediate frequency and audio amplifier input impedance.
As in all applications of the MC1596/MC1496. the emitter
resistance between pins 2 and 3 may be increased or decreased to
adjust ~ircuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector by introducing

Frequency Doubler
The MC1596/MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency daub ler and a
tuned output very high frequency (VHF) doubler, respectively.
Phase Detection and FM Detection
The MC1596/MC1496 will function as a phase detector_ Highlevel input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1596/MC1496 will deliver an
output which is a function of the phase difference between the
two input signals.
An FM detector may be constructed by using the phase detector principle. A tuned circuit is added at one of the inputs to
cause the two input signals to vary in phase as a function of frequency_ The MC1596/MC1496 will then provide an output which
is a function of the input signal frequency.

Pin number references pertain to this device when packaged in a metal can. To ascertain the corresponding pin numbers for a ceramic
packaged device refer to the PIN CONNECTION CHART on the first-page of this specification.

7-399

•

MC1596, MC1496 (continued)

TYPICAL APPLICATIONS
FIGURE 26 - BALANCED MODULATOR
1+12 Vdc SINGLE SUPPL Y)
810

lk

FIGURE 27 - BALANCED MODULATOR·DEMODULATOR
+12Vdc

1.3k

3k

3k
O.l/-1F

O.l/-1F

MC1596G
MC1496G

MC1596G
MC1496G

SIGNAL INPUT
300 mV(rms)

t-O--........ · V,

MODULATING
SIGNAL
INPUT

MOOULATI~ +

10

10

10 jJF
15 V

25jJF
15V

15

S.ak

'----'=-----;V·

CARRIER NUll

CARRIER

10k

NUll
50k

100

-8 Vde

100

FIGURE 29 - PRODUCT DETECTOR
(+12 Vdc SINGLE SUPPLY)

FIGURE 28 - AM MODULATOR CIRCUIT

+12 Vdc

Uk

820
RL
3.9k
I-:-()-<~-+" +V,

MC1596G

MCI496G

rO---4.. ·V,

MODULATING
SIGNAL
INPUT

10

15

S.ak

'-----~----~V·
CARRIER ADJUST
-8Vdc

FIGURE 30 - DOUBLY BALANCED MIXER
IBROADBAND INPUTS, 9.0 MHz TUNED OUTPUT)
1k

0.001
LOCAL

1k
lk

.'e
100pH

"'I

-=

FIGURE 31 - LOW·FREQUENCY DOUBLER

51

OSCILLATOR 0.001 /-IF

~~;~~(r~'f--+---O:-l
9

RF INPUT

·fl
001 "'
9.51JH

l1

51

5-80 pF
S.ak

t...:::===. . .·~;Vd'-

OUTPUT

MC1596
MC149S

9.0 MHz
OUTPUT

Rl =50n

90-480 pF

":"

-=

10
100

f

II = 44 TURNS AWG NO. 28 ENAMELED WIRE, WOUND
ON MICRQMETALS TYPE 44·6 TOROID CORE.

S.8k

'5
-8Vdc

Pin number references pertain to this device when packaged in a metal can. To ascertain the corresponding pin numbers for a ceramic
packaged device refer to the PIN CONNECTION CHART on the first page of this specification.

7-400

MC1596, MC1496 (continued)

TYPICAL APPLICATIONS (continued)

FIGURE 32 - 150 to 300 MHz DOUBLER
lk

300 MHz
Ir-'----'I-~>-I-_+~~ OUTPUT
1-10pF

O.OOl/-1 F
150MHz

Rl "50n

1-10pF

INPUT_ri----<>-'-j
100
6.ak

Ll" 1 TURNAWG
NO. IBWIRE,7/32" 10

DEFINITIONS

t

~
I

'-'

::

~
+

'-'

:§
I

'"
N
I

'-'

t'i

'" 0;
+
'-'
N
+

M

FREUUENCY - - - -....... BALANCED MODULATOR SPECTRUM
IC
CARRIER FUNDAMENTAL
IS
MODULATING SIGNAL
IC ± Is FUNDAMENTAL CARRIER SIDEBANDS

IC ± nls FUNDAMENTAL CARRIER SIDEBAND HARMONICS
nlc
CARRIER HARMONICS
nlc ± nls CARRIER HARMONIC SIDEBANDS

•
7-401

I

MCI109
MCI109C

~~_________O_P_E_R_A_T_IO_N_A_L_A_M__PL_I_F_IE_R_S~

MONOLITHIC OPERATIONAL AMPLIFIER

. . . designed for use as a summing amplifier, inte·
grator, or amplifier with operating characteristics as
a function of the external feedback components.
• High·Performance Open Loop Gain Characteristics
AVOL = 45,000 typical

MONOLITHIC SILICON

G SUFFIX
METAL PACKAGE
CASE 601
TO-99

• Low Temperature Drift - ±3.0 IlV 10C
•

Large Output Voltage Swing - ± 14 V typical

•

Low Output Impedance - Zout = 150 ohms typical

@

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

± 15 V Supply
LSUFFIX
CERAMIC PACKAGE
CASE 632
TO-116

MAXIMUM RATINGS ITA = +250 C unless otherwise noted)
Rating
Power Supply Voltage
Differential Input Signal
Common Mode I "put Swing

Symbol

Value

Unit

V+

Vdc

V-

+18
-18

Vi"

±5.0

Volts

CMVin

±v+

Volts

P2 SUFFIX

Load Current

IL

10

mA

Output Short Circuit Duration

ts

5.0

s

Power Dissipation (Package Limitation)
Metal Can
Derate above T A = +25 0 C
Flat Package

Po
680
4.6
500
625
5.0

mW
mW/oC
mW
mW/oC
mW
mW/oC

750
6.0

mW
mWI"C

-55 to +125
o to +75

°c

Derate above T A

:::0

Derate above T A

=+2SoC

Ceramic Dual In-Line Package

Derate above T A

= +2SoC

Operating Temperature Range

MC170S
MC1709C

Storage Temperature Range

TA

°c

T stg

Metal and Ceramic Packages
Plastic Packages

CASE 646
TO-116
(MC1709C onlyl

FSUFFIX

3.3

+2SoC

Plastic Dual I n-Line Packages

PLASTIC PACKAGE

-65 to +150
-55 to +125

CERAMIC PACKAGE
CASE 606
TO-91

~

P1 SUFFIX
PLASTIC PACKAGE
CASE 626
(MCn0ge only)

PIN CONNECTIONS

Schematic
A
"G" & "P'" Packages'
"F" Package
2
"P2" & "L" Packages 3

B

C

0

2

4

E
5

3

3
4

5

6

4

5

6

9

G H
7 8
7 8 9
1011 12
F

6

FIGURE 1

OUTPUT

LAG

2.4k

CIRCUIT SCHEMATIC

D

See Packaging Information Section for outline dimensions.

7-402

V·

EQUIVALENT CIRCUIT

MC1709, MC1709C (continued)

ELECTRICAL CHARACTERISTICS IV+ = +15 Vdc, V- = -15 Vdc, TA = +25 0 C unless otherwise noted)
MC1709
Characteristic

Symbol

Open Loop Voltage GainlRL - 2.0 knl
IVa = ±10 V, TA = Tlow to Thigh)@

AVOL

Output Impedance
If = 20 Hz)

MC170ge

Min

Typ

Max

Min

Typ

Max

25,000

45,000

70,000

15,000

45,000

-

-

150

-

-

150

-

150

400

-

50

250

-

±12
±10

±14
±13

-

±14
±13

±8

±10

±8.0

±10

-

70

90

-

±12
±10

65

90

-

-

0.2
0.5

0,5
1.5

-

0.3

1.5
2.0

0.05

0.2
0.5
0.2

-

0.1

-

-

5.0
6.0

-

2.0

-

7.5
10

-

-

-

0.8
0.38
12

-

p.s
p.s
VII's

0.6
0.34
1.7

-

-

-

-

p.s
p.s
VII's

2.2
1.3
0.25

-

-

0.6
0.34
1.7

-

-

-

2.2
1.3
0.25

-

3.0
6.0

-

-

-

-

3.0
6.0

-

-

80

165

-

80

200

-

25

150

-

25

200

-

25

.150

-

25

200

n

Zout

Input Impedance

kn

2in

If = 20 Hz)
Output Voltage Swing

Va

IRL = 10 kn)
IRL = 2.0 kn)
Input Common-Mode Voltage Swing

CMVin

Common-Mode Rejection Ratio

CMrej

(f = 20 Hz)
I nput Bias Current

Vpeak

Vpeak
dB

Ib

IT A = +25 0 C)
ITA =Tlow)

p.A

-

Input Offset Current
ITA = +25 0 C)
ITA = Tlow)
ITA = Thigh)

Iliol

Input Offset Voltage
ITA = +25 0 C)
IT A = Tlow to Thigh)

IViol

Step Response

1Gain = 100, 5.0% overshoot,
Rl = 1.0 kn, R2 = 100 kn,
R3= 1.5kn,Cl = 100pF,C2=
3.0 pF

1Gain
= 10, 10% overshoot,
R 1 = 1.0 kn, R2 = 10 kn,

i

tf
tpd
dVou,/dt

1Gain = 1,5.0% overshoot,

Rl=10kn,R2=10kn,R3=
1.5 kn,cl =5000pF,C2= 200pF

f

'f
tpd
dVout/dt

-

1.0

-

-

-

0.8
0.38
12

-

-

(j)

-

(j)

0.5
0.75
0.75

-

mV

-

(j)

-

p.A

-

~

tf
tpd
R3= 1.5kn,cl = 500pF,C2= 20pF dVou,/dt

Unit

-

-

-

-

p.s
p.s
VII's

-

Average Temperature Coefficient of

Input Offset Voltage
(RS = 50 n,TA = Tlow to Thigh)
IRS"'; 10 kn, T A = Tlow to Thigh)
DC Power Dissipation

p.V/oC

ITCViol

-

Po

IPower Supply = ± 15 V, Va = 0)
Positive Supply Sensitivity

S

(V- constant)
Negative Supply Sensitivity
(V+ constant)



2:

AT rvTERAr

,;,-

14

2. 0

~

SAFE OPERLNG tEA

12

+40

FIGURE 10 - INPUT NOISE
VOLTAGE versus SOURCE RESISTANCE

"- E", QUIESCENT = -V.. ,
"- E,:, QUIESCENT;" 0 V

10

.........

~

L

i/',,/

.........

5j-O. 2

,3

/

j

.........

~



16

18

10 kHzl\
1.0kHZ1\

\I

100 Hj.X \

•

/\

1. 0

20

V+ and V-, POWER SUPPLY VOLTAGE IVdc)

0
1.0

100

1.0 k

Rs. SOURCE RESISTANCE 10HMS)
See current MCC1709/1709C'data sheet for standard linear chip information.
See current MCBC1709/MCB1709F data sheet for Beam-Lead device information.
See current MCCF1709, 1709C data sheet for flip-chip information.

7-405

10k

~~_____D_I_F_F_ER__EN_T_I_A_L_C_O_M__PA_R_A_T_O__R__~

MC1710

DIFFERENTIAL
COMPARATOR
INTEGRATED CIRCUIT

MONOLITHIC DIFFERENTIAL
VOLTAGE COMPARATOR
· .• designed for use in level detection, low-level sensing, and memory
applications.
•

Differential Input CharacteristicsInput Offset Voltage = 1.0 mV
Offset Voltage Drift = 3.0 p.V!oC

•

Fast Response Time - 40 ns

•

Output Compatible With All Saturating Logic Forms Vo = +3.2 V to -0.5 V typical

•

Low Output Impedance - 200 ohms

GSUFFIX
METAL PACKAGE
CASE 601
TO-99
Lead 4 connected to case

F SUFFIX
CERAMIC PACKAGE
CASE 606
T0-91

MAXIMUM RATINGS (TA : +25°C unless otherwise noted)
Rating

Symbol-

Value

Unit

Vee max
Vee max

+14
-7.0

Vdc
Vdc

Differential I"put Signal Voltage

VID

±5.0

Volts

Common Mode Input Swing Voltage

Power Supply Voltage

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

L SUFFIX
CERAMIC PACKAGE
CASE 632
TO-116

VICR

±7.0

Volts

Paak Load Currant

IL

10

rnA

Power Dissipation (package limitations)

Po
mW
mWf'C
mW
mWf'C
mW
DC

UF" Package

DC

"L·· Package

Darat. abova T A = +25 OC
Flat Package
Darata above T A = +25OC
Ceramic Dual I n-Line Package
Derate above T A =+25°C
Operating Temperature Range

TA

680
4.6
500
3.3
625
5.0
-55 to +125

Storage Temperature Range

Tstg

-65 to +150

Metal Package

mW/oC

PIN CONNECTIONS
Schematic

A B C

0

2

3

4

2

3

5

6

8

3

4

6

9

11

"G" Package

2

'·Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

CIRCUIT SCHEMATIC

EQUIVALENT CIRCUIT

Vee

GND
See Packaging I nformation Section for outline dimensions.
See current MCC1710/1710C data sheet for standard linear chip information.
See current MCBC1710/MCS1710F for beam-lead device information

7-406

VEE

E

F
8

MC1710

(continued)

ELECTRICAL CHARACTERISTICS
Characteristic Definitions (linear operation)

VIO

E

RS

C

Characteristic
Input Offset Voltage
Vo = 1.4 Vde, TA = +25O C
Vo = loS Vde, TA = ·55°C
VO= 1.0Vde, TA =+125 OC

'[7-:

RS

(Vcc = +12 Vde VEE ~·6 Vde. TA = +250 C unless otherwise noted)

va

Svmbol*
VIQ

Min

Typ

Max

-

1.0

-

-

2.0
3.0
3.0

-

3.0

-

-

1.0

3.0
7.0
3.0

Unit
mVde

-

A

~

Rs<21l0n

Temperature Coefficient of

o.VIO/o.T

/lV/oC

I nput Offset Voltage

J
_

E

C

12

va

A
':"

110:: I, -12
11+12
IIB=~

eOul

r~~.
!- ""'
C

-

-

"

A

liB

-

-

12

-

-

20
45
20

1250
1000

1700

-

-

-

ro

-

200

-

ohms

Differential Voltage Range

VIQ

±S.O

-

-

Vde

Positive Output Voltage

VOH

2.5

3.2

4.0

Vde

VOL

·1.0

-0.5

0

Vdc

Output Sink Current
VIQ ;;'·5.0 mV, Vo ';;;0,
TA=+25°C
VIQ ;;'·5.0 mV, Vo ;;'0,
TA = ·55°C

r~
-Vb

':'

~

'":'

14V

VIO

J-

::J
TR-j

lOOmV
Vb =95mV-VIO

2.5

-

1.0

2.0

-

-

-

Volts

SO

100

-

dB

tp

-

40

-

ns

ID+
ID-

-

6.4
5.5

9.0
7.0

mAdc

-

-

115

150

mW

VICR

Common-Mode Rejection Ratio

CMRR

Propagation Delay Time

2.0

±S.O

Input Common·Mode Voltage Range

VEE = ·7.0 Vdc, RS ';;;200n

""'~

mAdc

lOs

~[;c:

;.

VIV

Avol

.Negative Output Voltage
VIQ;;'.5.0mV

10

A

/lAde

VIQ;;'S.O mV, 0';;;10 ';;;5.0 mA

'C?4
C

Input Bias Current
Vo = 1.4 Vde, TA = +25 O C
Vo = loS Vdc, TA = ·55°C
Vo = 1.0 Vde, TA = +125°C

/lAde

-

Output Resistance

E-

VIO

110

Open Loop
Voltage Gain
TA = +25°C
TA = ·55 to +125°C

B

1--

Input Offset Current
Vo = 1.4 Vde, TA = +25°C
VO= 1.SVde, TA =·55°C
Vo = 1.0 Vde, TA = +125°C

For Positive and Negative
GOing Input Pu lse

Vb

ein

'~
f
C

,":,A 0

10-

Power Supply Current
Vo ""OVdc

Power Consumption

*Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-407

I

MC1710 (continued)

TYPICAL CHARACTERISTICS
FIGURE 2 -INPUT OFFSET VOLTAGE
_ " TEMPERATURE

FIGURE 1- VOLTAGE TRANSFER
CHARACTERISTICS
.0

0

r

I

-55'e
-25'e

,.

.0

"'\
\\'
\'

+125 DC

.0

•

;;; 4..0

~>

i,..

.0

~

\\

0

~
+2.0

+4.0

P
+6.0

0
55

+8.0

25

'25

.0

I\.
'"

5

.0

"- I"'.:

.0

0
-55

25

'"

l'.~

i'--..

0

"'-..

'25

r-+75

'50

-

+100

TA. AMBIENT TEMPERATURE (DC)

5.0
-55

+125

-25

+25

...........

+50

t----

+75

+100

+125

TA. AMBIENT TEMPERATURE (DC)

FIGURE 6 - VOLTAGE GAIN
versus TEMPERATURE

FIGURE 5 - GAIN VARIATION
WITH POWER SUPPLY VOLTAGE
3000

2500

VEE'1, We

2,00

~2000

z

~
1500

g
00/

00

+125

01\

.0

~10

+100

5

.0

..l

+75

FIGURE 4 - INPUT BIAS CURRENT
versus TEMPERATURE

FIGURE 3 - INPUT OFFSET CURRENT
versus TEMPERATURE

~

'50

1--

lA. AMBIENT TEMPERATURE (DC)

Vin,lNPUTVOlTAGE (mVI

w

-t--

V

/

;:

h\

+25°C

-55°e

.0

1.0

ci

h

+IUoC

~

0
10

t::-

./
V V

~ ./

V
V
......

~
V

V

l...l...~z

I--

~

Or--

J"-... r-.......
..............

0

V

11

200

12

13

1000
-55

14

~
...........

-25

>25

'50

+76

TA. AMBIENT TEMPERATURE (DC)

Vee. POSITIVE SUPPLY VOLTAGE (Vdc)

7-408

~

+100

+125

MC1710 (continued)

TYPICAL CHARACTERISTICS (Continued)
FIGURE B - POWER DISSIPATION
versus TEMPERATURE

FIGURE 7 - RESPONSE TIME
+4.0,---,---,.-----.---,----,---,

'50,---,------r----,----,,---,---,---,

S+3.0I---=::::!=::::::::l~---+---+---+-----l

~

'~

~ +2.01---+----W~-+---+---I------l

~

20 mV OVERORIVE-

1\~

5 mV OVERDRIVE

~ +1.01---,J-f-,--*U-\-\1\~.' \ r - I - - - J + - - - - + - - - - l
~

10 mV OViRORIVE-

r\\

~ 2 mV OVErORIVE

~ or----+-----H,r\.,~~'~.---'I-----r-----l

r~1:1~==
I ~==I
I i~:=:=:1I

:s

~

E
z

'251----f---i---r-~r_--+--+--~

"
~

ill
Q

'"~

"~

.P

'00~--+---1---r--~--+--+--~

~5~5----2~5--~0--~+2~5---C+5~0-'--+~75'--'--+~'0~0'--+~'2~5

-50'!:-0---2:!:0,-----:'
4U:-O----,S':c
0 --""S:!::0---:,.::00,...---':-:!20
t, TIME Ins)

TA. AMBIENT TEMPERATURE 1°C)

FIGURE 9 - RECOMMENDED SERIES RESISTANCE
versus MRTL' LOADS

FIGURE 10 - FAN-OUT CAPABILITY
WITH MDTL' OR MTTL' OUTPUT SWING
+5.0,.----------,-1-,--,-------. ~ ACTUAL OUTPUT
SWING

~~
MRTl

50

MC1710

20

'"

~

"'"

3

10

f3.0
til

t'-.

w

~

~>

mW MRTL

.........

"

MEO. POWE/;'
2.0

I
0.2

Mn

I

""

+2.0

~

0.5
2.0
1.0
RS, SERIES RESISTANCE (k OHMS)

>

5.0

10

MOll

~

~~------------.
R,=I----------i

VOlTAG~.

12'7k_~ L..a
Vo ....JMiiTl\..
r

MC1710
_ _ _ _ _ _ _\ _

MAXIMUM lOW

o

"

---:::~
INPUT
LIMITS

:= +1.0
~

"'-I"

-r-

MINIMUM HIGH STAT2.

~

5.0

1.0
0.1

~

+4.0't----------"I'7.:or--------j

--~
-

-6.0 V

STATE~

MTTl. MDTL

I

~

-1.0'----------'-0J...
R-2- - - - - - - - - '
FAN·O UT CAPASI L1TY

7-409

R,

~J

1L~

MC1710C

______

D_I_F_F_E_R_E_N_T_IA_L__
CO
__
M_P_A_R_A_T_O_R__~

DIFFERENTIAL
COMPARATOR

MONOLITHIC DIFFERENTIAL
VOLTAGE COMPARATOR
· .. designed for use in level detection, low·level sensing, and memory
appl ications.
•

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

Differential Input CharacteristicsInput Offset Voltage = 1.5 mV
Offset Voltage Drift = 5.0 J.lV IOC

•

Fast Response Time - 40 ns

•

Output Compatible With All S.aturating Logic FormsVo = +3.2 V to -0.5 V typical

•

Low Output Impedance - 200 ohms
G SUFFIX
METAL PACKAGE
CASE 601-2
TO·99

F SUFFIX
CERAMIC PACKAGE
CASE 606
TO·91

MAXIMUM RATINGS ITA = +2SoC unless otherwise noted I
Rating
Power Supply Voltage

Differential-Mode Input Signal Voltage
Common-Mode Input Swing
Peak Load Current

Power Dissipation (package limitationsl
Metal Package
Derate above T A ;:; +25 0 C
Flat Package

Symbol

Value

Unit

VCC
VEE

+14
-7.0

Vdc
Vdc

VID

±S.O

Volts

VICR

±7.0

Volts

IL

10

mA

680
4.6
SOO
3.3
625
5.0

mW
mW/oC
mW
mW/oC
mW
mW/oC

°c
°c

PD

Derate above T A = +25 0 C
Ceramic and Plastic Dual In-Line Packages
Derate above T A = +25 0 C

Operating Temperature Range*

TA

o to +75

Storage Temperature Range

Tstg

-65 to +150

-.-LSUFFIX

_

A
I
I

C

3
3

2

EQUIVALENT CIRCUIT

Vee

+ ra
INVERTING INPUT e
NON.INVERTING 80-----11--..J
INPUT

OUTPUT

A
GNO

See Packaging Information Section for outline dimensions.
See currant MCC171 0/171 OC data sheet for standard linear chip information.

7-410

-

PIN CONNECTIONS
Schematic

Symbols conform to JE DEC Engineering Bulletin No.1 when applicable.

CIRCUIT SCHEMATIC

•

P SUFFIX
PLASTIC PACKAGE
CASE 646
TO·116

"G" PackaD'
"F" Packag,
"L" and "P" Packages

-For fuel temperature range (-5SoC to +12S o C) and characteristic curves,
see MC1710 data sheet.

>

CERAMIC PACKAGE
CASE 632
TO-116

0
VEE

D
4
5
6

E
7
6
9

8
11

MC1710C (continued)

ELECTRICAL CHARACTERISTICS (Vee = +12 Vde, VEE = -6.0 Vde, TA = +25 0 e unless otherwise noted I

Characteristic Definitions

Characteristic

Input Offset Voltage
Vo = 1.4 Vde, TA = +25 0 C
Va = 1.5 Vde, TA = OoC
VO= 1.2Vde, TA=+700C

~V:.

Vin

Vo

R,

~

Symbol
Via

A

'=

Temperature Coefficient of Input

Rs.;;;200n

6.vI O/6.T

Min

Typ

Max

-

1.5

Unit
mVde

-

-

5.0
6.5
6.5

-

5.0

-

-

1.0

-

-

5.0
7.5
7.5

-

/lV/oC

Input Offset Voltage
I nput Offset Current

~
,

_

C

12

A

Va
Va
Vo

Input Bias Current

Avol ,,~

Voltage Gain

r~"
~

/lAde

-

15
25

-

25
40
40

V/V

Avol

= +25 0 e
= 0 to +70 0 e

-

1000
800

1500

ro

-

200

-

Differential-Mode Voltage Range

VIDR

±.5.0

-

-

Positive Output Voltage

VOH

TA
TA

'0",

L

liB

Vo = 1.4 Vde, TA = +25 0 e
Vo = 1.5 Vde, TA = oOe
Va = 1.2 Vde, TA = +700 e

11+12
Ila"'~

B

-

Vo

110"1"'2

-=

/lAde

110

= 1.4 Vde, TA = +250 e
= 1.5 Vde, TA = oOe
= 1.2 Vde, TA = +70 0 e

-

'0

-=

C-=A

Output Resistance

--.!~

Vin:> 5.0 mV, 0';; 10 .;; 5.0 rnA

,--

Vin

~e

Negative Output Voltage
Vin :> - 5.0 mV

10

A

Output Sink Current

W
e

:

Vin

-=

,

Input Common-Mode Range

A

Common-Mode Rejection Ratio

RS';; 200

~[?:

~ ''''~
-=

-Va

-:VB

.I.
-=

14V

lOOmV

95mV·VIO

tRl~

ein---.J

.~
t,:,

Vin~

~

3.2

4.0

-1.0

-0.5

0

Vde
mAde
1.6
0.5

2.5

-

-

-

±.5.0

-

-

70

100

-

-

40

-

-

6.4
5.5

9.0
7.0

mAde

-

110

150

mW

Volts

VieR

eMRR

n

Propagation Delay Time
For Positive and Negative GOing
Input Pulse

2.5

Is

VEE = -7.0 Vde

Vde
Vde

VOL

Vin:> 5.0 mV, VO:> 0
TA = +25 0 e
TA = oOe

ohms

dB

ns

tpHLlLH

Va

Power Supply Current

VO';;OVde

-:-A 0

Power Consumption

7-411

lee
lEE

I

L----J

Mel711

~~______D_I_F_F_E_R_EN_T_I_A_L_C_O_M_P_A_R_A_T_O_R_S~

MONOLITHIC DUAL
DIFFERENTIAL VOLTAGE COMPARATOR
· .. designed for use in level detection, low-level sensing, and memory
applications.

DUAL DIFFERENTIAL
COMPARATOR
INTEGRATED CIRCUIT

Typical Characteristics:
• Differential Input Input Offset Voltage = 1.0 mV
Offset Voltage Drift = 5.0 IlV10C
• Fast Response Time - 40 ns
• Output Compatible with All Saturating Logic Forms Vout = +4.5 V to -0.5 V Typical
• Low Output Impedance - 200 Ohms
MAXIMUM RATINGS

(TA

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

=25'C unless otherwise noted)

Rating

Symbol

Value

Unit

Power Supply Voltage

V+
V-

+14
-7.0

Vdc
Vdc

Differential Input Signal

Vln

±5.0

Volts

Common Mode Input Swing

CMVln

±7.0

Volts

Peak Load Current

IL

50

mA

Power Dissipation (package limitation)
Metal Can
Derate above TA = 25' C

PD

680
4.6

mW
mW(,C

Ceramic Dual In-line Package
Derate above T A = 75'<;

670
6.7

mW
mW/"C

Flat Package
Derate above TA = 25· C

500
3.3

mW
mW(,C

Operating Temperature Range

TA

-55 to +125

·C

Storage Temperature Range

Tstg

-65 to +150

·C

FSUFFIX
CERAMIC PACKAGE
CASE 606
TO-9l

GSUFFIX
METAL PACKAGE
CASE 603·02
TO·l00

LSUFFIX
CERAMIC PACKAGE
CASE 632
TO·116

CIRCUIT SCHEMATIC

EQUIVALENT CIRCUIT

120

240

•

~----------~~--f,r,~~im----------------+---ov-

o

®m



>- +1.0

\\..

:::>

!;o
~
>

0

I - - C-

I'--r-

-

:---:---

2. 0

-

-1.0

-2. D

-10

-B.D

-6.D

-4.D -2.D
+2.0 +4.0
Vi •• INPUT VOLTAGE.lmV)

+6.0

+B.D

D
-60

+lD

>

~ 17DO

;;:

'"

~

~

'~ ~PUTPINS®0

15DO

o

g
~ 1400

'\

o

g13DD

~

+5 0

~

0

+120 +140

l-

~E+2
0
~§; .

~

~-

>
+40

+6D

+BD

+10D

+12D

1

"I

+6.0

o

+20

k.l12v
V-= -6.0 V
TA =+25'C -

'"+150

... 16DO

~

+20

.§

I~PUT JINS~ ~

z

0

FIGURE 4 - RESPONSE TIME
FOR VARIOUS INPUT OVERDRIVES

==bU

o

-20

TA.AMBIENT TEMPERATURE.I'C)

FIGURE 3 - VOLTAGE GAIN
versus TEMPERATURE
lBD

-40

~ 4.0

140

o

~

...

~z

o 130

~

ill
i5

-

~ 2.0

o

>

r--... ~

I-

~

o

120

.lj

to

;;;

"'" "'-

ffi

~

3.0

'"

.P

UJ

'"

TA. AMBIENT TEMPERATURE.I'C)

I~

.IV+=+12V
V-= -6.0 V
TA=+25'C.-

I

5.0m~
.0mV

-1.0
-10

OmV

~

~

+10

-1.0mV
+20

t. TIME Ins)

7-414

I

+3.0

~Ci)

r"

/
V

V

/

+30

+40

-tii0

MC1711 (continued)

FIGURE 8 - OUTPUT PULSE STRETCHING
WITH CAPACITIVE LOADING

FIGURE 7 - COMMON MOOE PULSE RESPONSE
+3.0,---,,-...- , - - - - , - - -...-

+4 .0

...- , - - - , -.........- - ,

50P~"rt' ~

~

opO!! 4::o PJ

.0

~ '-...

~100PF V1\
CL = 50 pF-'

0

~

~rHiIIII,111
-20

0

+20

+-40

+60

+80

t,

+100

+120 +140

+160

~-2. 0

Cl

I

=

'"

)+=+12l
V-=-B.OV _
TA ;;+25°C

1~~=200jF

1\ ~L=1001~~

"'

OpF

I

~

II

.....

5.1k
Vout

-:;rCL

-4. 0

+180

100

200

300

400

500

t, TIME (ns)

TIME Ins)

FIGURE 9 - SERIES RESISTANCE
versus MRTL FAN·OUTS

FIGURE 10 - FAN-OUT CAPABILITY
WITH MDTL OR MTTL OUTPUT SWING
+5.0,---------,----------,

+4.0t-----------,m.---------i
Vi

~>

~ +3.0 1------'M"'r"'T'-L--~r--l

20

1Jj
w

'"~ +2.0
MOTL. MTTLINPUT VOLTAGE

>
>=>

~
-~

§

5.0

+1.0

2.01----+-::;..• . /

MTTL. MOTL

- 1 . 0 1 ' - - - - - - - - - : - 1oL'2::-----------l
FAN·OUT CAPABILITY

RS. SERIES RESISTANCE Ik OHMSI

7-415

1L~

MC1711C

_______

D_IF_F_E_R_E_N_T_I_A_L_C_O_M_P_A_R_A_T_O__
R_S~

MONOLITHIC .DUAL
DIFFERENTIAL VOLTAGE COMPARATOR
· .. designed for use in level detection,low·level sensing, and memory
applications.
Typical Characteristics:
• Differential Input
Input Offset Voltage = 1.0 mV
Offset Voltage Drift = 5.0 IlV10C
• Fast Response Time - 40 ns
• Output Compatible with All Saturating Logic Forms
Vout = +4.5 V to -0.5 V typical
• Low Output Impedance - 200 ohms

MAXIMUM RATINGS

(TA

MONOLITHIC
SILICON EPITAXIAL PASSIVATED

= 2S"C unless otherwise noted)

Rating

Symbol

Value

Unit

V+

+14
-7.0

Vdc
Vdc

Differential Input Signal

.5.0

Volts

Common Mode Input SWing

.7.0

Volts

50

rnA

Power Supply Voltage

V-

Peak Load Current
Power DisSipation (package limitation)
Metal Can
Derate above TA = 25°C

680
4.6

mW
mW/oC

Flat Package
Derate above TA = 25° C

500
3.3

mW
mW,C

Ceramic Dualln-Line Package
Derate above TA = 25°C

625
5.0

mW
mWj"C

o to +75

°c

Operating Temperature Range

°c

Storage Temperature Range
Metal and Ceramic Packages

I

DUAL DIFFERENTIAL
COMPARATOR
INTEGRATED CIRCUIT

-65 to +150

GSUFFIX
METAL PACKAGE
CASE 603-02
TO·l00

F SUFFIX
CERAMIC PACKAGE
CASE 606
TO·91

-

~

LSUFFIX
CERAMIC PACKAGE.
CASE 632
TO·116

EQUIVALENT CIRCUIT

CIRCUIT SCHEMATIC

I

1®1II
10
IOUTPUT

I
I
I
I

4.5k

I

I

120

24

_...I

v-

L -____________________~--~--~------------------~~--Q4

Number.t.ndoftermin.1


:-

rr>

Input Common Mode Range

V- = -7.0 Vdc

1st

CMVin

mAde

Volts

vln

>On

Bout

J:.+

-=- 'J'
Vin

= 100 mVde

ein~v

OV~
1.4V

"~

K

Vb =5.0mV+V io

it

8stro be

'S"

eout

cr-- -

Response Time

ID+

r-0

Strobe Release Time

tSR

Power Supply Current
Vout ~ 0 Vdc

~+

1.4V

~tI0 -

Power Consumption

7-417

ns

ns

mAde

mW

I

,

MC1711C

(continued)

TYPICAL CHARACTERISTICS
FIGURE 1 - VOLTAGE
TRANSFER CHARACTERISTICS

FIGURE 2 - INPUT BIAS. CURRENT
versus TEMPERATURE

+5.0

10

-hI.O

\

$

~+3. 0

c:
~.

<+2.0

~
>

~+l. 0

~

o

8. 0

TA' 25'C

\

0

r---

1\

0

\... -

>

f-

-

2. 0

-1. 0

-2. 0
-10

o
-B.O

-s.o

+2.0
+4.0
-2.0
Vin,lNPUT VOLTAGE, (mVI

-4.0

+6.0

+8.0

+10

o

20
40
TA, AMBIENT TEMPERATURE, ('C)

FIGURE 3 - VOLTAGE GAIN
versus TEMPERATURE

:>

+150

~

+100

~
>

+50

~c

0

.s
;;

? 17001;;;::::"----==---_t_----+--__

-

-50

"'

+S0

'"~

:l

20L

+4. 0

lom~74V

>$

!;~
~~

11300~---_+----_+----~--~

+2. 0

o

1200'-----'------'------'----='
o
20
40
SO
15

/~ V

0
-2. 0
-10

0

+20

V
/'

FIGURE 5 - VOLTAGE GAIN VARIATION
WITH POWER SUPPLY VOLTAGE

en

+4.0

.=:.

+3.0

~

"'

r--

'"~

+2.0

o
>
~

+1. 0

~
~

0
+3 0

~_

+2.0

./

2,Or V

+100

+BO

+120

TIME (ns)

/

I

V

/

.IV+'+12V I V-· -S.O V
TA·+25'C._

I
OmV

~c:: +1.0

~2:

o

0

€;
>Q

11 0
15

-1. 0
-10

/£

~

1.0mV
+10

+20
!,TIME(ns)

7-418

j

I
5.0mVfr
2. mV

>~

SO

I

FIGURE 6 - STROBE RELEASE TIME
FOR VARIOUS INPUT OVERORIVES

14 0

--

I



-1.0

!:;

!=
:::J
0

~rHi~~III~1J ~III
-20

0

+20

+40

+60

+80

+100

+120 +140

g

:> -2. 0

-4.0 .L--'---:'10"'0
--'---'2~00~-L--:3-!"00:---L--40L,0-~-::-!500
0

+160 +180

t, TIME (n,)

t. TIME (ns)

FIGURE 9 - RECOMMENOEO SERIES RESISTANCE
versus MRTL • LOAOS

FIGURE 10 - FAN-OUT CAPABILITY
WITH MDTL' OR MTTL' OUTPUT SWING

10 0

~ ACTUAL OUTPUT

~~

SWING

MRTl

0

MC1711C

~o

MINIMUM HIGH

OUT< _ __

2:

'-

0

i'-.

00

c

«

:l

MTlL
~+3.('I-----~~--~~f-~}--------~

10

~
w

"

mW MRlL

I........

"- .........

'"~+2.[I~----~~_ _~Hl=~--------~
o

:>

t;

5. 0

~

~+ln~-----~----4
o
~

-6.0 V

c

MEa. POWER
MRTl

2.0

1.0

0.1

0.2

I III ~
0.5

:>

..............

1.0

2.0

"

r"-"
5.0

10

lor 2
FAN·OUT CAPABILITY

RS. SERIES RESISTANCE (k OHMS)

7-419

I

'\

MC1712
MC1712C

OPERATIONAL AMPLIFIERS

'---------------'

WIDE-BAND DC AMPLIFIER
INTEGRATED CIRCUIT
MONOLITHIC SILICON
EPITAXIAL PASSIVATED

MONOLITHIC WIDEBAND DC AMPLIFIER
. designed for use as an operational amplifier utilizing operating
characteristics as a function of the external feedback components.
•

Open Loop Gain AVOL = 3600 typical

•

Low Temperature Drift - ±2.5 !lV/oC

•

Output Voltage Swing ±5.3 V typical @+12 V and -6 V Supplies

•

Low Output Impedance - Zout

MAXIMUM RATINGS ITA

=

+250 C

GSUFFIX
METAL PACKAGE
CASE 601
TO·99

= 200 ohms typical

Lead 4 connected to case

unless otherwise notedl

Rating

Symbol

Value

Unit

Power Supply Voltage
(Total between V+ and V- terminals!

Iv+I+lv-1

21

Vdc

Vin

±5.0

Volts

CMVin

+1.5
-6.0

Volts

Peak load Current

IL

50

mA

Power Dissipation (Package Limitation)
Metal Package
Derate above T A = +250 C

PD
680
4.6
500
3.3
625
5.0

mW
mW/oC
mW
mW/oC
mW
mW/oC

TA

-55 to +125
Oto +75

°c

Tstg

-65 to +150

Differential Input Signal
Common Mode Input Swing

Flat Ceramic Package

Derate above T A == +250 C
Dualln·Line Ceramic Package

Derate above TA

==

+25 0 C

Operating Temperature Range MC1712
MC1712C
Storage Temperature Range

CIRCUIT SCHEMATIC

°c

FREQUENCY
COMPENSATION

LAG

4BO

PIN CONNECTIONS
Schematic

ABC

0

"G" Package

1

4

"F" Package
"L" Package

v+

LEADj EXTERNAL
F

L SUFFIX
CERAMIC PACKAGE
CASE 632
TO·116

3
3

3

4

4

240

L-----------~----~----__ov-

See Packaging Information Section for outline dimensions.

7-420

G
5
6

6

EQUIVALENT CIRCUIT

H

_:...t==:;--'fr:-:----r-r-,--ov+
B.Ok

.-

+---t-o

F SUFFIX
CERAMIC PACKAGE
CASE 606
TO·91

9

H
8

8
10 12

10
13

MC1712, MC1712C (continued)
ELECTRICAL CHARACTERISTICS IT A = +25 0 C unless otherwi'" notedl
MCI112C

MC1112

Min

Typ

Max

Min

Typ

Max

(V+ ::: 12 Vdc, V- = -6.0 Vdc, V 0 = ±5.0 VI

600
2500

900
3600

1500
6000

500
2000

800
3400

1500
6000

(V+:: 12 Vdc, V-::: -6.0 Vdc, Vo =±5.0 Vdc,
TA =T,owCD, Thi9hQ)I

2000

7000

1500

7000

500

1750

400

1750

Characteristic

Symbol

Open-Loop Voltage Gain IRL = 100 knl
(V+ = 6.0 Vdc, V- = -3.0 Vdc, Vo = ±2.5 VI

(v+

=

6.0 Vdc, V- '" -3.0 Vdc. Vo

=

±2.S V.

TA = Tlow to Thighl

Output Impedance
IV+ = 6.0 Vdc, V- = -3.0 Vdc, f '" 20 Hz)

ohms

Zout

300
200

(V+ '" 12 Vdc, V- = -6.0 Vdc, f = 20 Hz)
I nput Impedance
(V+ ==- 6.0 Vdc, V- = -3.0 Vdc, f = 20 Hzl
(V+ = 6.0 Vdc v-::: -3.0 Vdc, f = 20 H 2,

300
200

700
500

800
600
k ohms

lin

TA == TiolN. Thigh)
(V+ = 12 Vdc, V- = -6.0 Vdc, f = 20 Hzl
(V+ = 12 Vdc, V- = -6.0 Vdc, f = 20 Hz,

22

70

B.O
16

40

16

55

10

32

±2.5
±5.0
±1.5

±2.7
±5.3
±2.0

±3.5

±4.0

6.0

TA '" Tlow. Thigh)

Vo

Output Voltage Swing

Vpeak

IV+ = 6.0 Vdc, V- = -3.0 Vdc, RL = 100 knl
IV+ = 12 Vdc, V- = -6.0 Vdc, RL = 100 knl
IV+ = +6.0 Vdc, V- = -3.0 Vdc, RL = 10 knl

±2.5
±5.0
±1.5
±3.5

(V+ = +12 Vdc, V- = -6.0 Vdc, RL = 10 kn)
Input Common-Mode Voltage Swing
(V+ '" 6.0 Vdc, V- = -3.0 Vdc)

±2.7
±5.3
±2.0
±4.0

CMVin

Vpeak

+0,5
-1.5
+0.5
-4.0

+0.5
-1.5

(V+ = 12 Vdc, V- "" -6.0 Vdc)

+0.5

-4.0
Common-Mode Rejection Ratio
(V+ = 6.0 Vdc, V- == -3.0 Vdc, f :5: '.0 kHz)
(V+ = 12 Vdc, V- '" -6.0 Vdc, f ~ 1.0 kHz)

dB

CMrej

80
80

Input Bias Current

100
100

70
70

95
95

Ib

/iA

T A = +2S o C
fV+ == 6.0 Vdc, V- == -3.0 Vdc)
'1 + '2 (V+ '" 12 Vdc, V- = -6.0 Vdcl
Ib=-2- ,
TA=T,ow
(V+ = 6.0 Vdc, V- = -3.0 Vdc)

(v+ "" 12 Vdc, V- '" -6.0 Vdc)
Input Offset Current (lio -', -12)
(V+ '" 6.0 Vdc, V- '" -3.0 Vdcl
(V+ '" 6.0 Vdc, V- = -3.0 Vdc,

1.2
2.0

3.5
5.0

1.5
2.5

5.0
7.5

2.5
4.0

7.5
10

2.5
4.0

8.0
12

0.1

0.5

0.3

2.0

0.2

1.5
0.5

0.5

2.5
2.0

/i A

I'iol

T A = T,ow to Thigh)
(V+ = 12 Vdc, V- =, -6.0 Vdc)
tV+ '" 12 Vdc, V- = -6.0 Vdc,

1.5

T A "- T,ow to Thighl
Input Offset Voltage IRS - 2.0 k!!l
(V+ ::: 6.0 Vdc, V- == -3.0 Vdd
(V+ = 6.0 Vdc, V- '" -3.0 Vdc,
TA :: Tlow• Thigh)
tV+ "" 12 Vdc, V- '" -6.0 VdcJ
(V+ '" 12 Vdc, V- = -6.0 Vdc,

2.5
mV

IViol
1.3

3.0

1.7

6.0

1.1

4.0
2.0

1.5

7.5
5.0
6.5

3.0

TA '" Tlow, Thigh)
Step Response
V+ '" 12 Vdc, V- = -6.0 Vdc
Gain = 100. Vin =: 1.0 mV,

Vas

Rl = 1.0 kn, R2 = 100 kn,
C2'" 50 pF, R3 == 00, C1 = open
V+ '" 12 Vdc, V- '" -6.0 Vdc
Gain = La, Yin '" 10 mY,

R,= 10kn,R2= 10kn,
C, = 0.01 /iF, R3 = 20n, C2 = open

tf
tpd
dVout/dt@
Vas
tf
tpd
dVout/dt@

Average Temperature Coefficient of
Input Offset Voltage (AS = SOn)
IT A == +2SoC to Thigh)
(T A = Tlow to +2SoC)
ITA'" Trow, Thigh)

ITCviol

Average Temperature Coefficient
Input Offset Current
ITA = +250 C to Thigh)
(T A = Tlow to +25 0 C)

ITCliol

20
10
10
12
10
26
16
1.5

40
30

50
120

20
10
10
12
10
25
16
1.5

40
30

%

V//iS

50
120

%

ns
ns
V//is
p.V/oC

2.5
2.0
5.0
nA/oC

0.05
1.5

DC Power Dissipation
(V out '" 0, V+ =: 6.0 Vdc, V- = -3.0 Vdc)
(V out '" 0, V+ '" 12 Vdc, V- = -6.0 Vdc)

Po

Positive Supply Sensitivity
(V- constant = -6.0 Vdc,
V+ = 12 Vdc to 6.0 Vdcl

s+

Negative Supply Sensitivity
(V+ constant = 12 Vdc,
V- == -6.0 Vdc to -3.0 Vdc)

s-

4.0
6.0
mW

70

30
120

17
70

30
120

60

200

60

300

60

200

60

300

17

/iVIV

/iVIV

Q) T,ow = OOC for MC1712C, Thigh = +750 C for MC1712C
-5SoC for MC1712

Unit

VIV

AVOL

Q)dVout/dt '" Slew Rate

+12SoC for MC1712

7-421

I

MC1712, MC1712C (continued)

TYPICAL OUTPUT CHARACTERISTIC.~
(v+

= 12 Vdc, V- = -6.0 Vdc, T A = +25 0C)
FIGURE 2 - OPEN LOOP VOLTAGE GAIN
versus FREQUENCY

FIGURE 1 - OPEN LOOP GAIN versus
POWER SUPPLY VARIATIONS
4500'r----.----~--~--~--~

80

I~: ~ 430 pm

'"'

C, ~ 0 R, ~ '" ~
V-~-7.0V

, _ _- - V-

~

-6.0 V
iii

60

i'-,

'"z

iii

;'"

"

i'

j

~K

"i'
40

§;

20 t -

25001L-_ _.....J..._ _ _L-_ _-L_ _---l_ _-----"
14
10
11
12
13
15
V+. POWER SUPPLY VOLTAGE (VOLTS)

eg

~
~

R, ~ 3900
C, ~ 1500 pF
IR, ~ 150011
"C, ~ 0.01 p.F
r"-R, ~ 22 0
i'

r'-.[l

~

~~

eout

C F
= RIC'

r"-i'

"

Ni'

o
10 k 20 k 50 k100 k
1.0M
t, FREQUENCY (Hz)

1.0 k

10M

100M

FIGURE 3 - VOLTAGE GAIN versus FREQUENCY
+40

RI

+30
iii

:9.

z:

=1.0 k, R2 =100 k, R, ~ 390 O. C, - 430 pF
I I f I I II I I I I I'

III
=

+20
~

R,

iii

1.0 k, RZ 10 k, R,

~ +10

1500, C,

= 1500 pF

R,

I

§<

.i

~

I

~

0

R,

I t'
1.0

Ri

~11.~ ~'ti 122 g, C ~ 0jOlfF

i

2.0
5.0
t, FREQUENCY (MHz)

I

Curve AYOL

0

1
2
3

Curve 2

0

\.

Curve 3

0
0.01

1.0 k

1.0k

I'\..
t-0.1

"

1--.,1"-

:mn

2

CI
390 430 pF
150 1500 pF
22 0.01 ~F
R,

C

!

I--

10

Y

~
~
w

].I

~

G

~ 6. 0

F

r

5~
~

11 1 TIn

ttfffI TT 1 TIn

0.5
1.0
0.2
t, FREQUENCY (MHz)

200

IJ,I~ 2.01k

"" 8.0

R,

=

I II

100

10

R](W

R,
B
..........,

R, R,
R, + R,

1\

2. O~

!.Ok

R2<{!1
100 k
10 k

.

I'

0
0

100
10
1.0

RJ en)
1.0 k

IR'

FIGURE 5 - OUTPUT VOLTAGE SWING
versus LOAO RESISTANCE

FIGURE 4 - MAXIMUM OUTPUT SWING
versus FREQUENCY
Curve 1

=

11111
1.0

0.1

2

tr
F G
C,

C

R, +R,

III

om

I

R, R,

-10

-20

I I11I

11111
111II

4. 0
2.

7-422

yo);

100

I-rT I
RI =

QCI

I111

~.,

Or-o

10

l,.--J..-

I.-~

-6.0 Vdc
11111
5.0kl0k
1.0k 2.0k
RL, LOAD RESISTANCE !OHMS)

I III

1111
100 k

MC1712, MC1712C (continued)

TYPICAL CHARACTERISTICS(continued)
FIGURE 7 - INPUT OFFSET CURRENT
versus TEMPERATURE

FIGURE 6 - INPUT BIAS CURRENT
versus TEMPERATURE
4.0

!

t-

ill

'"
~
~

'"

2.0

'\

0.6

~

J JsUPPJ

+ 12

;;(

.OJ

-6.0

,\ ""-

t-

~

" '" s:;;;r- -

;;;

........

i"-. I"---.

t-

~

".i>

+6.0

~

0

t-

~

0.1

"

r--

1\

""
"
'" --I-

+11 V. -6.0 V Supplies

'-'

'-r-- t--

Vi -3.0 VI

0.4

:::>

~

......

I'----

""'-

r--

+6.0 Vi -3.0 VI SUPPliy

o
-60

-40

-10

+10

+40

+60

+BO

+100

+110

-60

+140

-40

-10

+10

+40

+60

+BO

+100

+110

+140

TA' AMBIENT TEMPERATURE (DC)

TA. AMBIENT TEMPERATURE (DC)

FIGURE 8 -INPUT OFFSET VOLTAGE
versus TEMPERATURE

FIGURE 9 - OUTPUT NOISE VOLTAGE
versus SOURCE IMPEOANCE

_ lOr--.-.-.rnorr- - - , - , , ,. .n r - - , - , - , , r n m

2.0

i

~

/
+6.0 V, -3,0 V SU PP

./"

0

V V

5_

1.0
-60

-

~

-10

to

~

c3

>

~

V

o

/'"

Z

~

+40

+60

+80

4.0

i--+-+H-t

t-

5g1.0 ~-.J--l-W::j:\;1+!:::-J

~1~IVSUPPlt

+10

6.0

w

~

I-~~

-40

V

B.O

w

,/

Z

>
+100

+110 +140

TA • AMBIENT TEMPERATURE (DC)

50

100

1.0 k

RS.SOURCE RESISTANCE (OHMS)

7-423

10 k

MC1723
MC1723C

l ___

PO_S_I_T_IV_E_V_O_L_T_A_G_E_R_E_G_U_L_A_T_O_R_S_....

MONOLITHIC VOLTAGE REGULATOR

VOLTAGE REGULATOR
MONOLITHIC SILICON
EPITAXIAL PASSIVATED
INTEGRATED CIRCUIT

The MCI723 is a positive or negative voltage regulator designed
to deliver load current to 150 mAdc. Output current capability can
be increased to several amperes through use of one or more external
pass transistors. MC 1723 is specified for operation over the military
temperature range (-55 0 C to +125 0 C) and the MC1723C over the
commercial temperature range (0 to +75 0 C)
• Output Voltage Adjustable from 2 Vdc to 37 Vdc
• Output Current to 150 mAdc Without External Pass Transistors
• 0.01 % Line and 0.03% Load Regulation

through substrate.

• Adjustable Short-Circuit Protection

G SUFFIX
METAL PACKAGE
CASE 603·03

FIGURE 1 - TYPICAL CIRCUIT CONNECTION

L SUFFIX
CeRAMIC PACKAGE
CASE 632
(TO-1161

FIGURE 2 - TYPICAL NPN CURRENT BOOST CONNECTION

(7--l
fsc"O.33

r--------==-<-'l.-r-"""~r_e
(614

VO"+15

Vd~

IL -2Adcm3";

MC1723
(MC1723CI

Vin=20Vdc

R3

-+-~~:-f"--4

(513
12k

10k

For best results 10 k< A2< 100 k
For minimum drift RJ = Rl11R2

FIGURE 3 - CIRCUIT SCHEMATIC

Vee

r-_r---......-"t--1o--_--~-_t-t--~11.::21_=_f'

vee
71111

S.2V

J r-___'_OI02ICURRENT
LIMIT
'------:-0 CURRENt
1 (3)SENSE
INVERTING
INPUT
PIN NUMBERS ADJACENT TO TERMINALS ARE FOR THE METAL PACKAGE;
PIN NUMBERS IN PARENTHESIS ARE FOR THE CERAMIC DUAL IN-LINE PACKAGE.

Sea Packaging Information Section for outline dimensions.
See current MCC1723/1723C data sheet for standard linear chip information.
See current MCBC1723/MCB1723F data sheet for beam-lead chip information.

7-424

MC1723, MC1723C (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Pulse Voltage Irom VCC to VEE (50 ms)

MCI723

Continuous Voltage Irom VCC to VEE
I nput-Output Voltage Differential

Symbol

Value

Unit

Vin(pl

50

Vin
Vin-VO

40
40
150
15

Vpeak
Vdc
Vdc
mAde
mAde

Maximum Output Current

'L
Irel

Current Iro m VreI
Power Dissipation and Thermal Characteristics

Meta I Package
TA = +250 C
Derate above T A = +250 C

0.8
5.4
185
2.1
14
70
1.0
6.7
150

Po
1/6JA
6JA
Po

Thermal Resistance, Junction to Air

TC = +250 C
Derate above T A = +2sDc

1/6JC

Thermal Resistance, Junction to Case

6JC
Po
1/6JA
6JA
TJ,T stg

Dual In-Line Ceramic Package
Derate above T A = +250 C
Thermal Resistance, Junction to Air
Operating and Storage Junction Temperature Range

Metal Package

Watt
mWPC
°CIW
Watts

mWPC
°CIW
Watt
mWPC
°CIW
°c

-65 to +150
-65 to +175

Dual In-Line Ceramic Package

OPERATING TEMPERATURE RANGE
Ambient Temperature

o to +75
-55 to +125

MCI723C
MC1723

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: TA = +250 C, Yin = 12 Vdc, Vo = 5 Vdc, 'L = 1 mAde, rsc = 0,
Cl = 100 pF. eref

=

a and divider impedance as seen by the error amplifier ~ 10 kn connected as shown in Figure 11

Characteristic

Input Voltage Range
Output Voltage Range
Input·Output Voltage Differential
Reference Voltage
Standby Current Drain (ll = 0, Yin = 30 VI
Output Noise Voltage (f - 100 Hz to 10 kHz)
Cref = 0
Crel = 5.0 /IF
Average Temperat(f) Coefficient 01 Output
Voltage(TIOw 1 1
Line Regulation

Symbol"

Min

Vin
Vo
Vin-VO

9.5
2.0
3.0
6.95

Vrel
liB
Vn

-

Regin

(T

=+250 C){12VThi h = +750 C for MC1723C
9 = +1250 C for MC1723

7-425

%VO

74
86
65

-..§.ymbols conform to JEDEC Bulletin No.1 where applicable.

Q)Tlow = OOCofO. MC1723C
= -55 C for MC1723

MC1723C
Typ

Max

20
2.5
0.002

-

TCVO

MC1723
Typ

dB

-

MC1723, MC1723C (continued)

TYPICAL CHARACTERISTICS
(Vin = 12 Vde, Va = 5.0 Vde, I L = 1.0 mAde, rse = 0, T A = +25 0 C unless otherwise noted)
FIGURE 4 - MAXIMUM LOAD CURRENT AS A FUNCTION
OF INPUT·OUTPUT VOLTAGE DIFFERENTIAL

FIGURE 5 - LOAD REGULATION CHARACTERISTICS
WITHOUT CURRENT LIMITING

200

".5

+0.05
TJ max = 150DC
'th = 150DC/W PSTANOBY = 60 mW

160

0-

ffi

:::>
<.>

\

0

«
g

80

E

TA=+25DC

1\ '\J I

"\. I"

j

o
o

~

~

TA~~D;

~

~ -0.05

10

--

a:
o

«

:::-

20

-

-r-- -r-

"'"

:::>

~t +125:t--- '-...

40

~ t:,-.

z

o

\

I'-

~

::;

~

\ \

120

~

"0

(No neat sink)

"T"""T"""tl

g
~ -0.1

-0.15
30

40

o

20

40

--

z
o

-0.05

>

f':: ~

a:

-0. 1

--

z

r- r- r-~

r-

0

TA=-55 DC
TA=+25 DC

~

.,;

«

g

!
o

15

10

20

'sc= 10n

r\"-

TA=+25 DC\

20

1"-

\
"\
1\
1
60

40

0.8

1.2
rsc= 10n

S
0

0



>

~
0-

TAi+25DC

z

w
a:
a:

0.2
TA = -55 DC
20

40

200

""

...........

~
~

/

0.6

V

"--

160 "
.§.
0-

N~

LIMIT CU RRENT 'sc = 5!l

60

80

0.5

:::>
<.>

I

o

o

80

SENSE VOLTAGE

;;;

TA = +125 DC

0.4

0.7

':;
0
>

0

g

"

\

FIGURE 9 - CURRENT LIMITING CHARACTERISTICS
AS A FUNCTION OF JUNCTION TEMPERATURE

0>

.,

100

10 • OUTPUT CURRENT (mAl

FIGURE 8 - CURRENT LIMITING CHARACTERISTICS

w

"t.........

NA=-55DC

TA =+125Dcl

o

10 • OUTPUT CURRENT (mA)

0

80

~

\

-0.3

30

25

\

-0.2

-0.4
5.0

"-

;1
.9

,

~~

-0.1

1;3
0

TA=+125 DC

rsc= lOn

:3
:::>
a:

~

g

j-O.15

~

_I

r-.

......... ~ r-...

.,'"

."....

1;3

:::>

60

"0

:::>

0-

~~

........

+0.1

"0
>

>

r---

FIGURE 7 - LOAD REGULATION CHARACTERISTICS
WITH CURRENT LIMITING

+0.05

-0.2

TA=-55 DC

10 • OUTPUT CURRENT (mAl

FIGURE 6 - LOAD REGULATION CHARACTERISTICS
WITH CURRENT LIMITING

~

...........

~25DC

a:

Vin-VO.INPUT·OUTPUT VOLTAGE (VOLTS)

'~"

............

g;

-----

r---

........

0.4
100

~ r-LIMIT CURRENT
-50

-

'sc = 10 n

+50

ffia:
"I:;;

~ .......

7-426

r--

"
r-- r-- r-+100

aa:

.,;;;'"
z

80

~

TJ.JUNCTION TEMPERATURE IDC)

10 • OUTPUT CU RRENT (mAl

120

40
+150

~

MC1723, MC1723C (continued)

TYPICAL CHARACTERISTICS (continued)
FIGURE 11 - LOAD REGULATION AS A FUNCTION
OF INPUT-OUTPUT VOLTAGE DIFFERENTIAL

FIGURE 10 - LINE REGULATION AS A FUNCTION
OF INPUT·OUTPUT VOLTAGE DIFFERENTIAL
+0.2

+0.1

I

liVin =+3 V

~

""oz

I

~

-

- r--

=>

8c:
~

J I

I = 1 rnl to I L 50 rnA

~

o

'" -0.1

g

--

i"'--....,

............

"

-g
.E

lil'
c:

-0.1

-0.2
15

5.0

35

25

o

10

Vin - VO,INPUT·OUTPUT VOLTAGE (VOL TSI

FIGURE 12 - STANDBY CURRENT DRAIN AS
A FUNCTION OF INPUT VOLTAGE
4.0

'.

IL

=

3.0

~

2.0

~

!;; 1.0

...---



~
'"

TA = +25 0 C

'/

---

=>

:==>

r-...

-2.0
-5.0

40

30

+ 10

Vin,lNPUT VOLTAGE (VOLTSI

1\

o

~ +2.0

1'\

o

'"'"~

.)

o

~ -4.0
=>
o

-8.0
-5.0

V

\

+20

+30

+ 40 +45

I

10

S

"
;::

z

0


I-

~
;!;

FIGURE 15 - OUTPUT IMPEDANCE AS
FUNCTION OF FREQUENCY

+10

z

>

I-

IL=40rnA

1\

.5

- '-

OUTPUT VOLTAGE

t, TIME (psi

FIGURE 14 - LOAD TRANSIENT RESPONSE

LOAO CURRENT

iEo
'"'"
~
o

o

20

z

~

/'

~

o

>

?

o

+2.0

l-

TA = +125 0 C

~o

+2.0

1/

o

;::

~

;;

+4.0

L

;;

TA = -55°C

,..-

10

50

IN~UT VJL TAG~

~

I-

B

0

40

FIGURE 13 - LINE TRANSIENT RESPONSE

e---- Va = Vref

<
.5

30

20

Vin -VO.INPUT·OUTPUT VOLTAGE (VOLTSI

w
u

50 rnA
CI = 0

ur

1.0



I-

V

O. 1

0

.§

+ 10

+20

+30

+40

0.0 1
100

+45

t,TIME""1

1.0 k

10 k
f. FREOUENCY (HzI

7-427

100 k

1M

MC1723, MC1723C (continued)

TYPICAL APPLICATIONS
Pin numbers adjacent to terminals are for the metal package; pin
numbers in parenthesis are for the ceramic dual in-line package.
FIGURE 16 - TYPICAL CONNECTION FOR 2
rsc
(12) 8
6(10)
+Vin

< Vo < 7

FIGURE 17 - MC1723,C FOLDBACK CONNECTION
roc
(12) 8
6(10)

Vo

+Vin

Vo
(11)7

r.

1012)

Rl

MC1723
IMC1723C)

16) 4
Al

MC1723
IMC1723C)

R3

15) 3
eref

10 k
214)

100 pF

R2

R2

1 -=

llOOOPF

(7)5

1(3)
5(7)

R2]
Vo") [ Rl+R2

_ Vsense _ 0.66
Isc ---;;- ~ -;; .tTJ=+250C

R.=~'0kn
l--a

For best results 10 k < Rl + R2 < 100 k.
Far minimum drift R3 = R1UR2.

Vin 1
+6.5 V ...

-=

11218

MC1723
IMC1723C)
2.2 k

10

0. 1 • F

6 (10)

+5 V
(6) 4

10(2)

2k

MC1723
(MC1723C)

15) 3

2(4)
15) 3

9(13)

5.1k

5.1k

5(7)

-=

I'000PF

(7) 5

-=

FIGURE 20 - +15 V, I·AMPERE REGULATOR
WITH REMOTE SENSE
0.33

FIGURE 21 - -15 V NEGATIVE REGULATOR
6(10)

(12) 8
(11))

2141

10 (2)
(6) 4

1(3)

MCI723
IMC1723C)

MC1723
(MC1723C)
O.I.F

0.33

1(3)

1M
1k

O.,.Fl

:r
-=

Vin2
(12)8
+10 V ......::'-..-:.--<>--i
Vo

61101

(6) 4

[ Iknee
Isc

(614

2141

-1]

Vo

....,---------::=:::::--,(

lN4001
OR EOUIV
100

Vo

FIGURE 19 - +5 V, I·AMPERE HIGH
EFFICIENCY REGULATOR

=lmH

Vin
+10 V

Vsanse
a= _
_

where

Vsense
rsc=--(1-0) Isc

FIGURE 18 - +5 V, I·AMPERE SWITCHING REGULATOR

Vin
+20 V

-=

(5) 3

12 k

+ Sense

Vo

~-

+15 V
10 k

Load

-Sense

-=

7-428

Vin = -20 V

+5 V

MC1723, MC1723C (continued)

TYPICAL APPLICATIONS (continuedl
FIGURE 22 - +12 V. 1-AMPERE REGULATOR
USING PNP CURRENT BOOST

Vin

+15

2N3791
OR EaUIV

ve--r--'( x-----------op-'Wv-.,.....VO ·+12 V
0.33

100

10k
100pF

12 k

Pin numbers adjacent to terminals are for the metal package; pin
numbers in parenthesis are for the ceramic dual in-line package.

7-429

~_________H_IG__H_-F_R_E_Q_U_E_N_C_Y_C_I_R_CU__IT_S~

MC1733
MC1733C

MONOLITHIC DIFFERENTIAL VIDEO AMPLIFIER

· .. a wideband amplifier with differential input and differential output. Gain is fixed at 10, 1.00, or 400 without external components
or, with the addition of one external resistor, gain becomes adjustable
from 10 to 400.

•

Bandwidth - 120 MHz typical

•

Rise Time - 2.5 ns typical @ AVd = 10

•

Propagation Delay Time - 3.6 ns typical @ AVd = 10

@

DIFFERENTIAL VIDEO
WIDEBAND AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

AVd = 10

FIGURE 1 - BASIC CIRCUIT

GSUFFIX
METAL PACKAGE
CASE 603-02
TO-l00

FIGURE 2 - VOLTAGE GAIN
ADJUST CI RCUIT

GAIN SelECT

LSUFFIX
CERAMIC PACKAGE
CASE 632
TO-116

Radj

INPUT 1

OUTPUT 1

O.2pF
INPUT
1

TOUT,'UT
Ik

INPUT 2

OUTPUl2

,

~OUTPUT
~1k
2

INPUT

0.'"

CONNECTION DIAGRAMS

V- GZA G2B

v-

GAIN SELECT

G2A G2B

G1A
GAIN SELECT

GZA
GAIN SELECT

FIGURE 3 - CIRCUIT SCHEMATIC

If'"

I

8 (10)

1.1 k
Z.4 k

INPUT 1

OUTPUT I

INPUT 2

OUTPUT 2

Z.4 k

(top view)

Z(11

G1B
GAIN SELECT

7 (B)

OUTPUT 1

7k
9 (11) {

GAIN
SELECT

G'A
GZA

50

3 (3) {

SELECT

GZB

14

INPUT 2
6 (7)

10 (1Z)

GAIN

G SUFFIX, METAL PACKAGE
Pin 5 connected to case.

OUTPUT Z

7k

NC
G2B GAIN SELECT

12 G2A GAIN SELECT

G1B GAIN SELECT 4

;',Gl~B_~=+=~+=:j
4 (4)

v-

5

NC

6

OUTPUT 2

INPUT 1

13 NC
11 G1A GAIN SELECT

10

v+

9 NC

(top view}

OUTPUT 1

400
L SUFFIX, CERAMIC PACKAGE

See Packaging Information Section for outline dimensions.

7-430

MC1733, MC1733C (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating

Symbol

Value

Unit

V+
V-

+8.0
-8.0

Volts

Power Supply Voltage
Differential Input Voltage

Vin

±.5.0

Volts

CMV;n

±.6.0

Volts

Output Current

10

10

mA

Internal Power Dissipation (Note 11
Metal Can Package
Ceramic Dual In-line Package

Po
500
500

mW

TA

o to +75
-55 to +125

DC

Tstg

-65 to +150

°c

Common-Mode Input Voltage

Operating Temperature Range

MC1733C
MC1733

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (V+; +6.0 Vdc, V-

=

-6.0 Vdc. at TA = +25 0 C unless otherwise noted)
MC1133

Characteristic

MC1133C

Symbol

Min

Typ

Max

Min

Typ

Max

AVd

300
90
9.0

400
100
10

500
110
11

250
80
8.0

400
100
10

600
120
12

-

40
90
120

-

-

40

-

Units

Differential Voltage Gain

Gain 1 (Note 21
Gain 2 INote 31
Gain 3 (Note 4)
Bandwidth

(R s =50n)

BW

Gain 1
Gain 2
Gain 3

Rise Time

MHz

IR s =50n, Vo = 1 Vp.p)

tr

Gain 1
Gain 2
Gain 3

tpd

Input Resistance

Ain

Ib

10

-

-

2.0

-

-

2.0

-

pF

0.4

3.0

0.4

5.0

"A

9,0

20

9.0

30

12

-

-

12

-

"A
"V(rms)

Input Voltage Range

-

-

+1.0

-

-

Vin

±1.0

Supply Voltage Rejection Ratio
Gain 2
({lVs = ±.0.5 VI

5+,5-

Output Offset Voltage
Gain 1
Gain 2 and Gain 3

Voo

Output Voltage Swing
Output Sink Current
Output Resistance
Power Supply Current

-

-.

CMrej

Output Common·Mode Voltage

-

Vn

Common·Mode Rejection Ratio
Gain 2
(VCM = ±'1 V, f ,,100 kHz)
Gain 2
(VCM=+l V,f=5MHzl

-

4.0
30
250

-

(R s = 50 n,
BW = 1 kHz to 10 MHz)

7.5
6.0
3.6

-

20

Input Noise Voltage

-

4.0
30

Gain 2
Gain 3

Input Bias Current

-

ns

10

-

I'iol

-

10.5
4.5
2.5

7.5
6.0
3.6

Gain 1

I nput Offset Current

-

-

-

Cin

10
-

120

10.5
4.5
2.5

-

Input Capacitance (Gain 21

90

-

-

Propagation Delav IRs = 50n, Vo = 1 Vp·p)
Gain 1
Gain 2
Gain 3

-

-

-

12

ns

250

~

10

kn

-

-

V
dB

-

60

-

86
60

-

70

-

50

70

-

--

0.6
0.35

1.5
1.0

-

0.6
0.35

1.5
1.5

CMV o

2.4

2.9

3.4

2.4

2.9

3.4

V

Vo

4,0

-

3.0

4.0

-

Vp·p

2.5

3.6

-

mA

-

20

-

n

18

24

mA

60

-

86
60

50

dB
V

10

3.0
2.5

Rout

-

20

10

-

. 18

7-431

'-

3.6

24·

-

•

MC1733, MC1733C (continued)

FIGURE 4 - MAXIMUM ALLOWABLE POWER DISSIPATION
800

~

NOTES

Note 1: Derate metal package at 6.5 mWJDC for operation at
ambient temperatures above 7SoC and dual in-line package at 9 mWfJC for operation at ambient temperatures

above 100°C (see Figure 4). If operation at high ambient temperatures is required (MC1733) a heatsink

may be necessary to limit maximum junction temperature to lS00C.

Thermal resistance, junction-fa-case,

Note 2:
Note 3:

for the metal package is 69.4o C per Watt.
Gain Select pins G1A and G1B connected together.
Gain Select pins G2A and G28 connected together.

Note 4:

All Gain Select pins open.

~

~

60 0

",

~

c

a:

~

400

I---

~

<£

ffi

MET:'5L~~~oKtGE _

,
\

" "",\~

200

\

~

~

CERAMIC OUAL_
IN-LINE PACKAGE
..... 9 mW/oC I---

\

\

,

~\

o

o

+50

+150

+100

+200

TA, AMBIENT TEMPERATURE I'C)

TYPICAL CHARACTERISTICS
(v+ = +6.0 Vdc. V-

= -6.0 Vdc, T A = +25 0 C unless otherwise noted,)
FIGURE 6 - SUPPLY CURRENT versus SUPPLY VOLTAGE

FIGURE 5 - SUPPLY CURRENT versus TEMPERATURE
20

B

4

,/

./

0

/
/

...........

""

.........

7

16
-60

-20

+20

+60

6

'" ""
+100

2

./
B.O

3.0

+140

TA, AMBIENTTEMPERATURE (DC)

/""

/'

v'"

../

../
4.0

5.0

6.0

V±,SUPPLY VOLTAGE (VOLTS)

7-432

7.0

8.0

MC1733, MC1733C (continued)

TYPICAL CHARACTERISTICS (continued)
(V+ : +6.0 Vdc, V-: -6.0 Vdc, T A : +25 0 C unless otherwise noted.!
FIGURE 7 - GAIN verus TEMPERATURE
1.15

"

1.10
z

1
~AINI

~ 1.05

"''"
~
§!
w

>

0

....

GAIN3_

"

0.95

g

"-

0.90

....... ~lIN2-

-

0.85

~

0

-20

+20

+60

\

\0
\

GAIN 3

0
0

"-

0.80
-60

GAIN 2

0

......

."-

~L): Uri

L!ft.

0

"-

1.0

FIGURE 8 - GAIN versus FREQUENCY
60

+100

+140

\

10

1.0

T, TEMPERATURE lOCI

100

1.0k

I, FREQUENCY (MHzl

FIGURE 9 - GAIN versus SUPPLY VOLTAGE

FIGURE 10 - GAIN versus RADJUST

1. 4

1000

z
1. 2

z

;;:

'""'~

--

~

>

~

_GAIN 3

1.0 -

o

g

.-'

~ t-

GAINJ.-O. 8 ......

'"

"''"'"
'"

....--"'~
"'"

,/

~

'"

",- V

;::

c

6/

O. 4
3.0

~
100

~

./

GAINy
O.

........

~
0
>

i

............ .......

10
5.0

4.0

6.0

7.0

8.0

10

Radj,("1

FIGURE 12 - GAIN versus FREQUENCY
and TEMPERATURE

FIGURE 11 - GAIN versus FREQUENCY and
SUPPLY VOLTAGE
+60

R~~I~ :,,1

m

z

tOO

"''"

+40

0

+30

'"

~

>

"''"

\

+20

"'

+10

~

'"inz

v~!l~

~

'"

~
~

Vs =±6 V

-10
1.0

10

II II

100

RL: 1 k"

>

30

~

in

rti

50

'"~

;

~

60

40

0

0

"'

'"
1(i

~
'"
;ji

VS!±8~

;ji

10k

1.0k

100

V±,SUPPLY VOLTAGE IVOLTSI

T~-550C

V

20

I

I, FREQUENCY (MHz!

'\

I II

TA=+750 C

-10
1.0

..#

Ti'i51i
10

100

I, FREUUENCY (MHz!

7-433

TA: DoC

~

TA: +25 0 C

10

j
1.0k

2L

1.0k

MC1733, MC1733C (continued)

TYPICAL CHARACTERISTICS (continued)

= +6.0 Vdc, V- = -6.0 Vdc, T A = +25 0 C unless otherwise noted.)

(v+

FIGURE 13 - PULSE RESPONSE versus GAIN

FIGURE 14 - PULSE RESPONSE versus SUPPLY VOLTAGE

+1.6

+1.6

~ +1.2
2w
~

>
~ +0.4

IV
1/

5o
0
-0.4
-15

-10

-5.0

0

+5.0

'-

~s = ±slv

2-

?

w

~+O.8

GAIN 2_

o

~+1.2
o

"".J-JVL

+0.6

~

~

JL=lk~-

ir""--

GAIN 3

o

IGAIN21_
RL = 1 kll

o

>

~tO.4

('GAIN 1

+10

+15

+20

+25

+30

-10

+5.0

-5.0

J.

>1.6

GAIN 2
RL=lkriTA = -55 0 C_

~ +0.8

ITA -

~

////.. r

o

"/

>

~ +0.4

..........

.....

160

/'
/'

./

;;
~

«

SO

!

40

/'

;:

( T

(

C

-10

o

-5.0

+5.0

+10

+15

+20

+25

+30

o

+35

I,TIME Insl

FIGURE 17 - PHASE SHI FT versus FREQUENCY

............

GAIN 2

-50

........
..........

w

~

iE

i

\
l\ \

-250

I\~GAIN
G~INII1

-300

2.0

4.0

so

GAIN 3

w

.......

o

70

"- "i'.

-2 0
-25

60

~~

....
~-200

..........

~ -1 5

50

'"e- 150

"-...

t;:

40

30

20

~ -100

~

'" -10
ffi
e.

10

FIGURE 18 - PHASE SHIFT versus FREQUENCY

.......

w
w

I
I

OVERORIVE RECOVERY TIME Ins)

............
-5.0

+35

/'

~

-

-0.4

-15

+30

,/

GAIN 2

.sw

> 120
rA=+25 0 C _
I

TA=+,i5 0 C

J'

.j 0

+25

/'

'>

~0

TA = +75 0 C

I 'r- r--..

~

+20

200

'"

'If/.,

olc

+15

FIGURE 16 - DIFFERENTIAL OVERDRIVE
RECOVERY TIME

FIGURE 15 - PULSE RESPONSE versus TEMPERATURE

~+1.2
o

+10

I. TIME In,)

. I,TIMEln,1

2-

VS=±3V

y

0

-0.4
-15

+35

\
VS~±6V- -

i\

IV

5o
.j

~

II
/

6.0

s.O

-350
1.0

10

10

100
I, FREQUENCY IMHz)

I. FREQUENCY IMHz)

7-434

1.0 k

MC1733, MC1733C (continued)

TYPICAL CHARACTERISTICS (continued)
(V+

= +6.0 Vdc, V- =-6.0 Vdc, T A = +2So C unless otherwise noted.)
FIGURE 20 - INPUT NOISE VOLTAGE

FIGURE 19 -INPUT RESISTANCE versus TEMPERATURE
70

0

BWG=A:~ ~Jl

I-GAIN 2

0

60

0

./

~

./'"

~ 50

./

0

'" 40

~

../

o

./

0

./

./

0

/

o

./

0

/

~ 30

/'

~

20

:!::

10

o

o

-60

-20

+20

+60

+140

+100

1.0

10

100

TA,AMBIENTTEMPERATURE IDC)

FIGURE 22 - OUTPUT VOLTAGE SWING versus
LOAD RESISTANCE

FIGURE 21 - OUTPUT VOLTAGE SWING and
SINK CURRENT versus SUPPLY VOLTAGE
B. 0

7.0

-p-~\\<",
"G~
~\l\.1p

p

J.......-.

~V

~

--

~ 5.0

1Ji

I---

w

'"
~
0
>

.--:: b;:::: ~

4.0
3.0

V

~

!; 2.0
0

.;

o
3.0

6.0

~

>
4.0

5.0

6.0

7.0

1.0

,/

o
B.O

7.0
RIL =

FIGURE 24 - COMMON·MODE REJECTION RATIO

Ik~

GIAIINIJ
o

;:

~

0

;'i

~ 5. 0

~

~~

1Ji

...... r--.,

0

........

70

I""'-r-.

w

o
o

3.0

"~
'"
"8

2.0

.;
> 1.0

o
1.0

10

100

10k

0

~ 6.0

~Ig

1.0 k

RL, LOAD RESISTANCE In)

FIGURE 23 - OUTPUT VOLTAGE SWING versus FREQUENCY

~ 4.0

/

100

10

V+.SUPPLY VOLTAGE IVOLTS)

~
>

10 k

1.0 k

SOURCE RESISTANCE In)

1.0 k

I

0

..........
50
40

30
10k

100 k

1.0 M
f, FREUUENCY 1Hz)

f. FREUUENCY IMHz)

7-435

10M

100 M

'\

MC1741
MC1741C

OPERATIONAL AMPLIFIERS

'-------~

INTERNALLY COMPENSATED, HIGH PERFORMANCE
MONOLITHIC OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

... designed for use as a summing amplifier, integrator, or amplifier with
operating characteristics as a function of the external feedback
components.
•
•
•
•
•
•

No Frequency Compensation Required
Short-Circuit Protection
Offset Voltage Null Capability
Wide Common-Mode and Differential Voltage Ranges
Low-Power Consumption
No Latch Up

MAXIMUM RATINGS ITA

=

G SUFFIX
METAL PACKAGE
CASE 601

TO-99

L SUFFIX

+25 0 C unless otherWise noted)
Symbol

Rating

Power Supply Voltage

V+
V-

Differential Input Signal

Vin

Common Mode Input Swing (Note 1)

Value

Unit

MC1741C

MC1741

+18
-18

+22
-22

Vdc
Vdc

±30

Volts
Volts

CMVin

.±15

Output Short Circuit Duration (Note 2)

ts

Continuous

Power Dissipation (Package Limitation)
Metal Can

Po
mW
mW/oC
mW
mW/oC

Derate above T A = -+ 25°C

500
3.3
625
5.0

Ceramic Dual In-line Package
Derate above T A = +2SoC

750
6.0

mWPC
mW/oC

o to +751-55 to + 125

°c
°c

Flat Package
Derate above T A = +25 0 C
Plastic Dual In-Line Packages

Operating Temperature Range

TA

Storage Temperature.R ange
Metal, Flat and Ceramic Packages
Plastic Packages

T stg

Note 1.
Note 2.

F SUFFIX
CERAMIC PACKAGE
CASE 606
TO-91

mW
mW/oC

-65 to +150
-55 to +125

P1 SUFFIX
PLASTIC PACKAGE
CASE 626

IMC1741C onlyi

PIN CONNECTIONS

For supply voltages less than ± 15 V, the absolute maximum input voltage is equal
to the supply voltage.
Supply voltage equal to or less than 15

P2 SUFFIX
PLASTIC PACKAGE
CASE 646
TO-116

IMC1741C only)

680
4.6

Derate above T A = +25 0 C

CERAMIC PACKAGE
CASE 632
TO-116

v.

Schematic

A
··G" & ··P1·' Packages 1
"F" Package
2
"P2" & "L" Packages 3

B
2
3
4

C
3

4
5

0

E

4
5
6

5
6

9

G
6
8
10 11

CIRCUIT SCHEMATIC
r-~----------~----~----------~------------~-CV'
G

FIGURE 1 - OFFSET ADJUST CIRCUIT

v+
25
OUTPUT

MC 1741 ,C

>-<>---.....

"
OFFSET
NULL

0---+---+----4
V-

See Packaging Information Section for outline dimensions.
See current MCBC1741/MCB1741 F data sheet for beam·lead chip information.
See current MCCF1741,C data sheet for flip-chip information.

7-436

v-

MC1741, MC1741C (continued)

ELECTRICAL CHARACTERISTICS ~v+

=

Ch.r.:t,ristic

+15 Vdc, V- '" 15 Vdc, TA" +2S oC unless otherwIse noted I
MC 741
Symbol

Open Loop Voltage Gain (RL" 2.0 knl
IVo = ±. 10 V. T A = +2S u CI

Min

Typ

50.000

200.000

MC1741C 4

Mox

AVOL

IVo = ± 10 V, T A = TJOWCD to ThighQ)'

OutpUt Impedance

Min

Ty.

20.000

100,000

Max

15,000

25.000

n

20
75

(f - 20 Hz)

Input Impedance
(f- 20 Hz)

75
Megn

Zin

Output Voltage Swing

0.3

1.0

0.3

1.0

±12
±10
±10

±14
±13

±12
±10
±10

±14
±13

CMVin

±12

±13

±12

±13

Vpeak

CMrej

70

90

70

90

dB

Vpeak

Va

tRl'" lDkn. TA- +2SoC)
(RL'" 2.0 kn. T A" +2So C)

(Rl = 2.0 kn. T A = TIOW(!) to Thigh~1

Input Common·Mode Voltage Swing
Common-Mode Rejection Ratio

Unit

If = 20 Hz)
Input Bias Current

'b

ITA = +2S0C)

pA

0.6
1.6

0.2

0.6

0.5
0.8

0.03

0.2

0.03

0.2
0.3

2.0

6.0

0.2

ITA = TIOWQ) I

I nput Offset Current

pA

I'io I

ITA'" +2SoCI
IT A = Tlow(D to Thigh@1

Input Offset Voltage (RS"
ITA" +2SoCI

~

0.6

10 kol

mV

IViol

1.0

5.0

ITA = TIOWC!) to Thigh®)

Step Response

8.5

29
8.5

p'
p'

1.0

1.0

VIps

If

3.0

3.0

p'

Ipd

1.0

1.0

29

If
Ipd

Gain = 100, ti,,, 1.0 kn,
R2" 100 kn, R3 = 1.0 kn

dVout/dt @

Gain - la, R, = 1.0 kn,
R2 = 10 kn, Ra = 1.0 kn

dVout/dt ~
I

If

Gain-l, R, = 10kO,

Ipd

R2" 10 kn, R3 =-5.0 kn

dVout/dt
Average Temperature Coefficient of
Input Offset Voltage

n, T A = Tlow

~

!;

12

0

.; B.O - f -

>

(VOLTAGE FOLLOWER)
THO < 5%

~ +60

'"
!:i +40
<[

o

>

~

\

I

4.0

;;:

,

16

0-

~

o
100

10

10 k

1.0 k
f. FREQUENCY (Hz)

"'-

~ +8 0
z

\
\

to
<[

+2 0

-20
1.0

100 k

10

"" '"

100

1.Ok

'"'"

10 k

lOOk

f. FREQUENCY (Hz)

I

10M

FIGURE 5 -INPUT OFFSET VOLTAGE versus TEMPERATURE

FIGURE 4 - OUTPUT NOISE versus SOURCE RESISTANCE
AV= lOOO

"

1.0M

>+2.0
,g

IIIII

W

to

~

0+1.0

>

-

t;;

1£o
0-

~

~

,/

.2

>

--

53-l. 0
N

~~~~~~~~t+W+U--+-+Ar~
10 k

---

~
SLOPE CAN BE EITHER POLARITY

::J
<[

~
100 k

1i!

~ -2.0

I

BO
+5. 0

i
o

0-

.........- V-

~

Z

j
::J

I .....

./

-10
-55

--

I--

1

- -

0-

-25

+25

+50

70

~
'"
B

60

~

50

iii

'""

+125

I'-,.

0-

~
:!: 40

+75

...........

r--....

~ ......

~

SLOPE CAN BE EITHER POLARITY

<[

'"'"~

+100

90

0-

-5.0

+75

FIGURE 7 - INPUT BIAS CURRENT versus TEMPERATURE

FIGURE 6 - INPUT OFFSET CURRENT versus TEMPERATURE

53
N

+50

TA. AMBIENT TEMPERATURE (OC)

~ +10

~
="
'"
'-'

+25

-25

·55

RS. SOU RCE RESISTANCE (OHMS)

30

+100

+125

20
-55

-25

+25

+50

-r--1---+75

TA. AMBIENT TEMPERATURE (OC)

TA. AMBIENT TEMPERATURE (OC)

7-438

+100

+125

MC1741. MC1741C (continued)

FIGURE 9 - OUTPUT VOLTAGE SWING
versus LOAD RESISTANCE

FIGURE 8 - POWER OISSIPATION
versus POWER SUPPLY VOLTAGE

100
70

.......r

§: 50
40

.sz

::! 30

V

~ 20
C

3!'"

/

10

V

1.......-

241-----+-++-f--,~H_1-Q.

i>.

VOUl=O- r--

~ 20~----+---~4-~~~~-----+--~-4-4-+~~
to

~ 16j-----t---~~J_tJtttt:::::±::tt:i:i:±JJtH

V

>

~

':; B.O ~----,?--~++-l
>

~
~ 1.0

5.0
4.0
3.0

2.0

II
6.0

121-----+-~f_+_H

t:::>

10

14

18

~~00~--~2~00~-L~-5~0~0~=C1D.OCk=====2.~0=k==C=~5~.0=k~=dlJOk

22

RL, LOAD RESISTANCE (OHMS)

V+ and V-, POWER SUPPLY VOLTAGE (VOLTS)

FIGURE 10 - COMMON-MODE REJECTION
RATIO versus FREQUENCY
~ 100

"

I""--

~z

0

~

60

"
~
""z~
"
~

40

I

20

'r-.
"I--

8

10

100

1.0 k

10 k

100 k

1.0 M

f, FREnUENCY (Hz)

I

7-439

"

MC1747L
MC1747CL

OPERATIONAL AMPLIFIER

'------------'
(DUAL MC1741)

DUAL MC1741
INTERNALLY COMPENSATED, HIGH PERFORMANCE
MONOLITHIC OPERATIONAL AMPLIFIER
· .. designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components. The MC1747L and MC1747CL are functionally, elec·
trically, and pin·for·pin equivalent to the p.A747 and p.A747C respec·
tively.

DUAL
OPERATIONAL AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

• ·No Frequency Compensation Required
• Short·Circuit Protection
• Wide Common·Mode and Differential Voltage Ranges
•

Low·Power Consumption

•

No Latch-Up

• Offset Voltage Null Capability

FIGURE 1 - TYPICAL FREQUENCY-SHIFT
KEYER TONE GENERATOR

CERAMIC PACKAGE
CASE 632

TO·116

r--+-+--+-+-----+-- - --- --- - -- - --0.5 ms/DIV.

Terminals 001 shown are not connecled.

1k

See Packaging Information Section for outline dimensions.

7-440

MC1747L, MC1747CL(continued)

MAXIMUM RATINGS ITA = +250 C unless otherwise noted)
Rating

Symbol

MC1747L

MC1747CL

Unit

V+

+22

+18

Vdc

V-

-22

-18

Power Supply Voltage

Differential Input Signal

CD

Vin

±30

Volts

Common-Mode Input Swing

~

CMVin

± 15

Volts

Output Short Circuit Duration

Continuous

ts

Po

Power Dissipation (Package Limitation)

750
6.0

Ceramic Dual In-Line Package
Derate above T A = +60o C

mW
mW/oC

+ 0.5

Voltage (Measurement between Offset Null and V-I

Volts

Operating Temperature Range

TA

-55 \0 +125

o to +75

°c

Storage Temperature Range

Tst9

-65 to +150

-65 to +150

°c

ELECTRICAL CHARACTERISTICS IV+ = +15 Vdc. V- = -15 Vdc T A =
Characteristics

Symbol

Input Bias Current

TA

Ib

= +250 C

Mm

-

-

I nput Offset Current

Iliol

TA':: +250 C

-

I nput Offset Voltage (AS ~ 10 kn)

IViol

TA "" +2SoC
T A"" Tlow to Thigh

-

-

-

Offset Voltage Adjustment Range

Rp
Cp

Common-Mode I nput Voltage Swing

Tlow~TA~Thigh

TA = +250 C
TA "" T,ow to Thigh

_
(V o -

±

_
10 V. RL - 2.0

500
800
800

20
7.0
85

200
200
500

-

20
7.0
7.0

20Q
300
300

1.0
1.0

5.0
6.0

-

6.0
7.5

± 15

-

-

1.0
1.0
+ 15

-

mV

0.3

-

-

0.3

-

Megohms

-

mVdc

2.0
1.4

-

2.0
1.4

-

-

pF
Volts

± 12

±.13

-

± 12

70

90

-

70

90

-

--

25.000
15.000

200.000

-

-

-

0.3
5.0

-

0.5

-

75

-

ohms

25

-

mAde

50.000 200.000
25.000
-

knl

Unit

80
30
30

AVOL

Open· Loop Voltage ~}~

Mon

-

CMrej

Tlow~ TA ~ Thigh

MC1747CL
Typ

500
500
1500

CMVin

Common·Mode Rejection Ratio (RS - 10 kill

Min

80
30
300

Differential Input Impedance (Open-loop. f - 20 Hz'
Parallel Input Resistance
Parallel I nput Capacitance

Max

nAdc

-

-

TA = Thigh
TA = Tlow

C unless otherwise noted)

MC1747L
Ty.

nAdc

-

TA = Thigh@
TA=Tlow @

+250

±

13

dB
Volts

Transient Response (Unity Gain)

(Vin = 20 mV. RL = 2.0 kn. CL .;; 100 pF)
Rise Time

-

tr

-

Overshoot Percentage

dVoJdt

Slew Rate (Unity Gain)
Output I mpedanee

Zo

Short-Circuit Output Current
Channel Separation

< Th'igh)

RL=10kn
RL=2.0kn

Vo

I

Power Supply Sensitivity (T,ow to Thigh)
V- = Constant. RS ~ 10 kG
V+ = Constant. AS ~ 10 kn
Power Supply Current teach amplifier}

TA

-

I

Output Voltage Swing (Trow ~ TA

=+250

-

ISC

S+
S10+. 10-

C

TA=T,ow

®

120

30

-

-

± 12

-

~s

%
VJ~,

dB
Vpk

-

-

30

30
30

150
150

2.8
3.3
2.5

-

-

1.7
20
1.5

1.7
2.0
2.0

2.8
3.3
3.3

-

50

85
100
75

-

50
60

-

60

85
100
100

~VIV

-

mAde

-

-

mW

-

60
46

15 V, the maximum differential input voltage is equal to ±. tV+ + lv-I).
15 V, the maximum input voltage is equal to the supply voltage (+V+. -IV-I).

7-441

± 14
+ 13

150
150

-

@ Tlow: OoC for MC1747CL
-55°C for MC1747L
Thigh: +750 C.for MC1747CL
+1250 C for MC1747L

120

-

.:!: 10

-

Po

-

-

-

-

TA=Thigh

±
±

25

-

TA =Tlow

For supply voltages of less than
For supply voltages of less than

15

± 14
± 13

TA =+250 C

 100

~

0

..

-'
0

>

z

;;:

~

V

c..
0

g

"' +8 0

~

-

w

95

.

~ +60

I~

'"

~ +40

o

I~

>

"'"

~+2 0

90

~

0

85
80
3.0

6.0

9.0

12

15

18

21

-2 0
1.0

24

100

10

1.0 k

10 k

~

100 k

~

1.0 M

10 M

f, FREQUENCY (Hzl

V+and V-, POWER·SUPPL Y VOLTAGE (VOLTSI

FIGURE 6 - POWER BANDWIDTH
(LARGE SIGNAL SWING versus FREQUENCY)

FIGURE 7 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE

100

1:

24~+~4+~--~~+#~-+++H~--~+++Hffl

~ 20~+~++~~-+-t++~~-1-+-HHt~--~~tHffl

~ 16~+~++~~-+-t++~~-1-+-HHt~I~\+~++HtH
...~ 12~-+~++~+--+-+++~~-1-+-HH+~-\\+-~+HtH
:::>

o

g 8.0~

>

(VOLTAGE FOLLOWER)
± 15 VO LT SUPPLI ES -It---H-ttttttt----l\-H-ttH-tl

11111~HO<15%1

4.:::1:11111::111:11::::::
10

100

II1II

loOk

\

10k

70

l< 50

..sz
o

~

40
30

/'

~ 20

C

'"~

/

0

L

L.

Vo =0 -

-

/

~
~7. 0

5. 0
4. 0
3. 0
2.0

lOOk

I, FREQUENCY (Hzl

J
6.0

10

14

18

V+ and V-, POWER SUPPLY VOLTAGE (VOLTSI

7-442

22

MC1747L, MC1747CL(continued)

TYPICAL CHARACTERISTICS (continued)
(V+

= +15 Vdc.

V-

= -15

Vdc. TA

= +25 0 C unless otherwise noted.)

FIGURE B - OUTPUT VOLTAGE SWING
versus LOAD RESISTANCE

..
?

w

'"

..s

16

~ 0.8

0

o
z

>

....

....

12
~
....
=>
~ 8.0

~

!;
o

c:

>

>

f---f----

0.6

f---f----

0.4

4.0
0.2
O. 1
100

1.0 k

III

---

:Lo i -

20

~

111

Rl

I IIIIIII
1.0 k

'/

I
10 k

-

RS. SOURCE RESISTANCE (OHMSI

FIGURE 10 - HIGH·IMPEDANCE. HIGH·GAIN
INVERTING AMPLIFIER
V+

10 Eo=-100Ein

1k

100 k

V-

Terminals not shown are not connected.

7-443

I

AV - 100

Vn

I IIIIII

12

I I

Rl

R3

RL. LOAD RESISTANCE (OHMS)

II II

~ Rl R2

S- 3iRJ+R2

AV = ~~

~
+

_~

AU;

......

l~
100 k

I~f

"\

OPERATIONAL AMPLIFIERS

'----_------J

MC1748G
MC1748CG

HIGH PERFORMANCE MONOLITHIC
OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

· .. designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components.
•

MONOLITHIC
SILICON EPITAXIAL
PASSIVATED

Noncompensated MC1741G

• Single 30 pF Capacitor Compensation Required For Unity Gain
• Short·Circuit Protection
• Offset Voltage Null Capability
• Wide Common·Mode and Differential Voltage Ranges
•

METAL PACKAGE
CASE 601

Low·Power Consumption

TO·99

• No Latch Up

'$-

B
(bottom view)

FIGURE 1 - POWER BANOWIDTH
ILARGE SIGNAL SWING varsus FREQUENCY)

..

FIGURE 2 - OPEN LOOP FREQUENCY RESPONSE

28

+12 0
+100

24

;;;

2! 20
w

«

~

16

§

12

-; 8.0

--

:;:
~ +6 0

TA"+250 C
CC '30pF_

~

~

~ +40

~

>

IVOLTAGE FOLLOWERI

~+20

±15VOLTSUPPLIES

~

~

THD<5%

~

~

z

\

>

0-

=>

:s +8 0

\

~

4.0

0

o
10

I IlfTFl1
100

1.0k

lOOk

10k

-2 0
1.0

t, FREQUENCY 1Hz!

1.0k

10k

lOOk

~

1.0M

10M

FIGURE 4 - OFFSET ADJUST AND
FREQUENCY COMPENSATION

15
OUTPUT

"
__

100

t, FREQUENCY 1Hz!

FIGURE 3 - CIRCUIT SCHEMATIC

L-~---+----~--~

10

~

I---

~-+

____

~

V·
________-+--o4

See Packaging Information Section for outline dimensions.

See cunent MCC1748/1748C data sheet for standard linear chip information.

7-444

MC1748G, MC1748CG (continued)

MAXIMUM RATINGS (TA

= +250 C unless otherwise noted)

Rating
Power Supply Voltage

Symbol

MC1748G

MC1748CG

Unit

V+

+22

+18

Vdc

-22

-18

VVi"

±30

Volts

CMVin

±15

Volts

Output Short Circuit Duration

ts

Continuous

Power Dissipation (Package Limitationl
Derate above T A = +2SoC

Po

680
4.6

Differential I nput Signal
Common-Mode Input Swing

CD

Operating Temperature Range

Storage Temperature Range

mW
mW/oC

TA

-55 to +125

o to +75

T stg

-65 to +150

-65 to +150

°c
°c

ELECTRICAL CHARACTERISTICS (V+ = +15 Vdc V- = -15 Vdc TA = +25 0 C unless otherwise noted)
MC1748G
Characteristics
Input Bias Current

Symbol
Ib

TA = +250 C
TA = Tlow to Thigh

@

Input Offset Current

Typ

MC1748CG
Max

Min

Typ

Max

T A = Tlow to Thigh
Input Offset Voltage (RS';; 10 k !II

-

0.08

0.5

-

0.08

0.5

-

0.3

1.5

-

-

0.8

-

0.02

0.2

0.02

0.2

-

0.08

0.5

-

-

0.3

-

1.0

5.0

1.0

6.0

6.0

-

-

7.5

0.3

2.0

-

~Adc

mVdc

IViol

TA = +250 C

= Tlow to Thigh

Unit
~Adc

Iliol

TA = +250 C

TA

Min

-

Differential Input Impedance (Open-Loop. f = 20 Hz)
Parallel Input Resistance

Rp
Cp

Parallel Input Capacitance
Common-Mode Input Impedance If"" 20 Hz)
Common-Mode Input Voltage Swing
Common·Mode Rejection Ratio (f

= 100 Hz)

Open· Loop Voltage Gain, (V o =;t10 V, RL d 2.0k ohms)

-

±13

-

;t12

;t13

-

90

-

70

90

-

-

-

200,000

-

0.3
5.0

20,000
15,000

-

-

-

-

-

200,000

0.8

-

-

0.3
5.0
0.8

75

-

-

75

-

25

-

±12

;t14

-

;t12

;t14

±13

-

;tID

±13

-

30

150

30

150

S-

-

-

30

150

-

30

150

+

-

1.67

2.83

1.67

2.83

-

1.67

2.83

-

1.67

2.83

-

50

85

-

50

85

Vo

-

25

-

V+

constant, Rs ~ 10 k ohms

= constant, Rs ~ 10 k ohms

Power Supply Current

S+

10

10
DC Quiescent Power Dissipation

IV o

d8

~s

%
V/~s

ohms
mAdc

Vpk

~V/v

Power Supply Sensitivity

v- =

Vpk

-

-

±10

ISC

pF

V/V

-

Zout

Megohm

Megohms

AVOL

dVout/dt

= 10 k ohmsl
= 2 k ohms (T A =T/ ow to thigh)

200

70

t,

RL

-

;t12

Overshoot Percentage

Output Voltage Swing (RL

-

CMrej

25,000

= 20 Hzl

-

CMVin

50,000

Output Impedance (f

1.4

200

= +25 0 C
= Tlow to Thigh
Step Response (Vin =20 mV, Cc =30 pF, RL =2 k!l, CL =100 pFI

Short-Circuit Output Current

-

-

-

TA

Slew Rate

2.0

-

ZOnl

TA

Rise Time

0.3

1.4

-

Po

= O}

mW

CD For supply voltages less than ±.15 V. the Maximum I nput Voltage is equal to the Supply Voltage.
oOC for MC1748CG
_5S o C for MC1748G
+75 0 C for MC1748CG
+125 0 C for MC1748G

7-445

mAdc

I

~_________O_P_E_R_A_T_I_O_N_A_L_A_M__PL_I_F_IE_R__~

MC3301P

MONOLITHIC QUAD
OPERATIONAL AMPLI FI ER

MONOLITHIC QUAD SINGLE-SUPPLY
OPERATIONAL AMPLIFIER
FOR AUTOMOTIVE APPLICATIONS

INTEGRATED CIRCUIT
EPITAXIAL PASSIVATED

These internally compensated operational amplifiers are designed
specifically for single positive power supply applications found in
automotive and consumer electronics. Each MC3301 P contains four
independent amplifiers - making it ideal for automotive safety, pollution, and comfort controls. Some typical applications are tacho·
meter, voltage regulator, logic circuits, power control and other
similar usages.

PLASTIC PACKAGE
CASE 646

ITO·116)

• Wide Operating Temperature Range - -40 to +85 0 C
FIGURE 1 - EQUIVALENT CIRCUIT

• Single-Supply Operation - +4.0 to +28 Vdc
•

I nternally Compensated

•

Wide Unity Gain Bandwidth - 4.0 MHz typical

•

Low Input Bias Current - 50 nA typical

•

High Open· Loop Gain - 2000 V/V typical

6~8~
AMPl #2

1

5

+

AMPU3

13

3~11~
AMPl #1

+

2

4

AMPl #4

12

vee - PIN 14

+

GROUND - PIN 7

FIGURE 2 - SMALL-SIGNAL TRANSIENT RESPONSE

+15 V
510 k

vee

"

c

;;;

'>
0;

510 k

:>E
:;l

1.0M

+15 V

I

FIGURE 3-INVERTING AMPLIFIER

FIGURE 4 - NONINVERTING AMPLIFIER

Rf

510 k

Rf

AV=-~

510k

fordc---71-'1""'...........,~
e 5~ik

+15 V

T

1.0.F

. ~'""

BW = 250 kHz

Va

+~Va

+5.0.F

10 k

AV = 10 BW = 150 kHz

See Packaging Information Section for outline dimensions.

+15 V

I MC3301-Page I)

7-446

9

+

10

MC3301 P

(continued)

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted)
Rating

Symbol

Value

Unit

VCC

+28

Vdc

Ir

5.0

mA

'sink

50

mA

Power Supply Voltage

Noninverting Input Current
Sink Current

Sou rce Cu Trent

'source

50

mA

Po

625
5.0

mW
mW/oC

TA

-40 to +85

°c

T stg

-65 to +150

°c

Power Dissipation (Package Limitation)

Derate above T A

=

+25 0 C

Operating Temperature Range

Storage Temperature Range

ELECTRICAL CHARACTER ISTICS [VCC = +15 Vdc, Rl = 5.0 k!l, T A = +25 0 C (each amplifier) unless otherwise noted I
Fig.No.

Characteristic
Open-Loop Voltage Gain

Note

5

Symbol

Min

Typ

Max

TA = +25 0 C
-40°C';; T A .;; +85 0 C

Unit
VIV

Avot

1000

-

-

2000
1600

-

6.9
7.8

10
14

-

50
100

300

0.80

0.98

1.16

-

±.2.5

-

'source

3.0

'sink

0.5

10
7.0
0.B7

-

VOH
VOllinvl
VOLlnonl

13.5

-

-

14.2
0.03

0.1

-

0.6

-

Input Resistance (Inverting input only)

Rin

0.1

1.0

-

Meg!l

= 100 pF,

SR

-

0.6

-

VII's

Quiescent Power Supply Current (Total for four amplifiers)
Noninverting inputs open·
Noninverting inputs grounded

6

Input Bias Current, RL -

7

mAdc
100
lOG

00

2

7

3

nAdc

118

TA = +25 0 C
-40°C';; T A .;; +85 0 C
Current Mirror Gain (lr - 200 I'Adc)

-

1

AI

-

-40°C';; T A .;; +85 0 C

mAdc

B

Output Current

Source Capability (VOH
(VOH
Sink Capability
(VOL

= 0.4 Vdcl
= 9.0 Vdc)
= 0.4 Vdcl

Output Voltage
High Voltage

-

Vdc

6

Low Voltage (Inverting Input Driven)
(Noninverting Input Driven)

Slew Rate (Cl

AlA

%

Current Mirror Gain Drift

Rl

= 5.0 kl

Unity Gain Bandwidth

4

BW

-

4.0

-

MHz

Phase Margin

4

.pm

-

70

-

Degrees

PSSR

-

55

-

dB

eo 1le 0 2

-

65

-

dB

= 100 Hzl
= 1.0 kHzl

Power Supply Rejection (f
Channel Separation (f

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

NOTES:

input does not have a requirement for input bias current.
3. Current mirror gain is defined as the current demanded at the
inverting input divided by the current into the noninverting
input.
4. Bandwidth and phase margin are defined with respect to the
voltage gain from the inverting input to the output.

1. The quiescent current drain will increase approximately 0.3
rnA for each inverting or noninverting input that is grounded.
2. I nput bias current can be defined only for the inverting input.
The non inverting input is not a true "differential input" - as
with a conventional Ie operational amplifier. As such this

(MC3301-Page 2)

7-447

•

MC3301P

(continued)

TYPICAL CHARACTERISTICS

(Vcc = +15

Vdc, RL = 5.0 k!l, TA = +250 C

{each amplifier] unless otherwise noted,}

FIGURE 5 - OPEN·LOOP VOLTAGE GAIN

FIGURE 6 - QUIESCENT POWER SUPPLY CURRENT

VCC
+15 Vdc

,...-----+------......_ein

A

1.0V

4.0 Vp·p
1.0 kHz

10k

B

51

100 k

10 ~F 100 k

-li.:r --11--'\11i"Y---+-~

>-~--~o----.eout

8,1 k

16 k

All four amplifiers operate in the same
configuration simultaneously.
'00; 51 = A 51 = OPEN
lOG; SI = A 51 = CLOSED
VOHI-); 51 = C S1 = CLOSED
VOll-); SI = B S1 = CLOSED
VOll+); SI =A S1 =CLOSED

eout
Avol=ein

FIGURE 7 - INPUT BIAS,CURRENT ANO
CURRENT MIRROR GAIN

FIGURE 8 - OUTPUT CURRENT

VCC
+15 Vdc

100~A

100 k
S1

>--0---_....."

VCC
+15 Vdc

=0.4 Vdc
or 9.0 Vdc

Vo

lOOk

10 k

A

liB; SI = A S1 = A
A" 51 = B S1 = B

'sink; Sl '" A
'source; Sl = B

IMC3301-Page 3)

7-448

MC3301P (continued)

TYPICAL CHARACTERISTICS
(Vcc

= +15

Vdc. RL

= 5.0 kn. TA = +25 0 C

(each amplifier] unless otherwise noted.)

FIGURE 10 - OPEN·LOOP VOL TAGE GAIN
versus SUPPLY VOLTAGE

FIGURE 9 - OPEN·LOOP VOL TAGE GAIN versus FREQUENCY
0

250 0

0

z

~

)I,

0

;;:

;;:

to

to
w
to

w

;o

0

>

20

~o

0

/

~
o
;;: 1000
o

0..

~

1500

~

0

V

/

50 0

0

10k

1.0 k

lOOk

1.0 M

3.0

10 M

6.0

9.0

FREQUENCY (Hz}

FIGURE 11 - OUTPUT RESISTANCE versus FREQUENCY

15

0

« 8.Of--IPdSlTlvJ

g:

E

z

24

27

30

~ 6.0

...

u

~~

a:

f-

!;o

1---1-

.....- ~

:::>

:::>

~

_V

100 ..l
......- V .d::::
(POSITIVE INPUTS OPEN}

ffi

~

t;;
fi31.0 k

21

INPUT~ GRO~

f-

w
u

«

18

FIGURE 12 - SUPPL Y CURRENT versus SUPPL Y VOL TAGE

~

4. a

ci

E

~ 2. a

I'.
10 0
0.5 k 1.0 k

5.0 k 10 k

I--

50 k 100 k

0

5.0 M

500k1.0M

3.0

6.0

9.0

12

15

18

21

24

27

30

SUPPLY VOLTAGE (Vdc}

FREQUENCY

FIGURE 13 - LINEAR SOURCE CURRENT versus
SUPPL Y VOLTAGE

FIGURE 14 - LINEAR SINK CURRENT versus
SUPPLY VOLTAGE

20

100 0

16

r-

0

~

E
f-

~

12

SUPPLY VOLTAGE (Vdc}

10 k

~

~

:3

~o

0
100

«

I'

L,-

2000

z

..-.........

2

a:

:::>

u

..-- V

w

~ 8. 0

V

~

/

,/

~

0
VOL = 0.4 Vdc

VOH = 0.4 Vdc
0

200

4. 0

3.0

6.0

9.0

12

15

18

21

24

27

30

a

3.0

6.0

9.0

12

15

18

SUPPLY VOLTAGE (Vdc}

SUPPLY VOLTAGE (Vdc}
IMC3301-Page 4)

7-449

21

24

27

30

MC3301 P (continued)

OPERATION AND APPLICATIONS
Basic Amplifier

linear operation at the output. The sink current of the device can
be forced to exceed the specified level by keeping the output de
voltage above:=::::: 1.0 volt resulting in an increase in the distortion

The basic amplifier is the common emitter stage shown in Figures
15 and 16. The active load I, is buffered from the input transistor
by a PNP transistor, Q4, and from the output by an NPN transistor,
Q2. Q2 is biased class A by the current source 12' The magnitude
of 12 (specified Isink) is a limiting factor in capacitively coupled

appearing at the output. Closed loop stability is maintained by an
on-the-chip 3-pf capacitor shown in Figure 18 on the following
page. No external compensation is required.

FIGURE 15
BLOCK DIAGRAM

'"
CAl
ORO
OR<

G7N~

Mul1'ple emllter (8) tranmtor

one f"uiter curm8CTe,1 ro each IIlpU!

current gain of Q3 ~ 1, its collector current is approximately equal
to Ir also. In operation this current flows through an external
feedback resistor which generates the output voltage signaL For
inverting applications, the noninverting input is often used to set
the dc quiescent level at the output. Techniques for doing this are
discussed in the "Normal Design Procedure" section.

A noninverting input is obtained by adding a current mirror as
shown in Figure 17. Essentially all current which enters the noninverting input, Ir' flows through the diode CR1. The voltage
drop across CR 1 corresponds to this input current magnitude and
this same voltage is applied to a matched device, Q3. Thus 03 is
biased to conduct an emitter current equal to I r. ·Since the alpha

FIGURE 17 - OBTAINING A NONINVERTING INPUT

FIGURE 16 - A BASIC GAIN STAGE

OUTPUT

OUTPUT

I-I

--

INPUTS

I+IQ--.....- - {
Ir

Biasing Circuitry
The circuitry common to all four amplifiers is shown in Figure 19,
see next page. The purpose of this circuitry is to provide biasing
voltage for the PNP and N PN current sources used in the amplifiers.

CRI

Q6. Transistor Q7 reduces base current loading. The voltage
across resistor R2 is the sum of the voltage drops across CR2, CR3
and CR4, minus the VBE drops of transistor Q9 and diode CR5.
The current thus' set is established by CR5 in all the NPN current
sou rees (Q 10, etc.)" This technique results in current source magnitudes which are relatively independent of the supply voltage. Qll
(Figure 15) provides circuit protection from signals that are negative
with respect to ground.

The voltage drops across diodes CR2, CR3 and CR4 are used as
references. The voltage across resistor R 1 is the sum of the drops
across CR4 and CR3 minus the VSE" of 08. The PNP current
sources (Q5, etc.) are set to the magnitude VBE/R 1 by transistor
IMC3301-Page 51

7-450

MC3301P

(continued)

OPERATION AND APPLICATIONS (continued)
FIGURE 18 - A BASIC OPERATIONAL AMPLIFIER

H

FIGURE 19 - BIASING CIRCUITRY

'----_._-0 OUTPUT

INPUTS

1+)

CRI

NORMAL DESIGN PROCEDURE
1. Output Q-Point Biasing

C. Reference Voltage other than

Vec

(see Figure 20)

A. A number of techniques may be devised to bias the quiescent
output voltage to an acceptable level. However, in terms of
loop gain considerations it is usually desirable to use the
non inverting input to effect the biasing as shown in Figures
3 and 4 (see the first page of this specification). The high
impedance of the collector of the noninverting "current
mirror" transistor helps to achieve the maximum loop gain
for any particular configuration. It is desirable that the noninverting input current be in the 10 p,A to 200 IJA range.

The biasing resistor Rr may be returned to a voltage (V r )

B. Vee Reference Voltage (see Figures 3 and 4)

current mirror gain.

other than

Vec.

By setting Rf

= Rr,

(still keeping Ir be-

tween 10 JJA and 200 pA) the output dc level will be equal
to Yr. The expression for determining VOdc is:

where ¢ is the VRF drop of the input transistors (approxi-

mately 0.6 Vdc @ +25 0 C and assumed equal).
The noninverting input is normally returned to the Vee
voltage (which should be well filtered) through a resistor,
R r • allowing the input current. I r • to be within the range of
10 p.A to 200 p.A. Choosing the feedback resistor, Rf, to be
~qual to Yz Rr will now bias the amplifier output dc level to
approximately

V~C.

2. Gain Determination
A. Inverting Amplifier
The amplifier is normally used in the inverting mode. The
input may be capacitively coupled to avoid upsetting the
dc bias and the output is normally capacitively coupled to
eliminate the dc voltage across the load. Note that when
the output is capacitively coupled to the load, the value of

This allows the maximum dynamic

range of the output voltage.

FIGURE 20 - INVERTING AMPLIFIER WITH
ARBITRARY REFERENCE

FIGURE 21 - INVERTING AMPLIFIER WITH
Av = 100 AND Vr = Vec

C*

T

0.1 IlF 5.1 k
Vin ~I--'IIIIV-_-o>---1

Ri

~~""'I'Ir-""'-o>---I

I

510 k

Rf

Vin

AI is the

0.1 IlF

>-O-.....-.VO

-= 10 k

Rr

Vr

*Select for low

Av = 100

frequency response.

IMC3301-Page 6)

7-451

+15 V

fL =300 Hz, fH

=50 kHz

VO

MC3301P (continued)

NORMAL DESIGN PROCEDURE(continuedl
'sink becomes a limitation with respect to the load driving
capabilities of the device. The limitation is less severe if the

B. Noninverting Amplifier

The MC3301 P may be used in the noninverting mode (see
Figure 4, first page). The amplifier gain in this configuration

device is direct coupled. In this configuration, the ae gain
is determined by the ratio of Rt to Ri. in the same manner
as for a conventional operational ampl ifier:

is subject to the current mirror gain. In addition, the resistance of the input diode must be included in the value of

~ ohms,
r
where Ir is input current in milliamperes. The noninverting
ac gain expression is given by:
the input resistor. This resistance is approximately

The lower corner frequency is determined by the coupling

capacitors to the input and load resistors. The upper corner
frequency will usually be determined by the amplifier in·
ternal compensation. The amplifier unity gain bandwidth
is typically 4.0 MHz and with the gain roll-off at 20 dB per
decade, bandwidth will typically be 400 kHz with 20 dB of
closed loop gain or 40 kHz with 40 dB of closed loop gain.
The exception to this occurs at low gains where the input
resistor selected is large. The pole formed by the amplifier
input capacitance, stray capacitance and the input resistor
may occur before the closed loop gain intercepts the open
loop response curve. The inverting input capacity is typi-

The bandwidth of the noninverting configuration for a given
Af value is essentially independent of the gain chosen. For
Rf = 510 kn the bandwidth will be in excess of 200 kHz
for non inverting gains of 1, la, or 100. This is a result of
the loop gain remaining constant for these gains since the
input resistor is effectively isolated from the feedback loop.

cally 3.0 pF.

TYPICAL APPLICATIONS
FIGURE 22 - TACHOMETER CIRCUIT
VCC~+12V

MAGNETIC PICKUP
HYSTERISIS AMPLI FIER

MONOSTABLE MULTIVIBRATOR

PULSE AVERAGING

t30
Cl
O.tpF

tOOk
MS06too

orequiv

6.1 V

tOOk

MAGNETIC
PICKUP

4.1 k

,>-o-~-<>OUTPUT

MS06tOO
orequiv

VH

~ A~~2

Vp·p'" IVo·O.S} . AI • t

Timing.lnterval: t "" 0.7 RI CI

Hysterisis Voltage for Switching

RyCt
(VCC - 1.S)

FIGURE 24 - LOGIC "OR" GATE

FIGURE 23 - VOLTAGE REGULATOR

ZI

R2

+Vee
150 k
+VCC ~ +t5 Vdc "'---'\IV\~--o----t
15 k

75 k

at
Rl

75 k

NOTE:

For positive Te zeners R2 and Rl can be
selected to give 0 Te output.

(MC3301-Page

7-452

7)

f~A+B+C

MC3301 P (continued)

TYPICA L APPLICATIONS (continued)

FIGURE 25 - LOGIC "NAND" GATE (Large Fan-In)

FIGURE 26 - LOGIC "NOR" GATE

+Vee "+15 Vdc

75 k

A _---.J\~-_--o-_j
75 k

75 k

75 k

150 k

f=A+B+C+O

75 k
+Vee" +15 Vdc

150 k

f"'A-B-C-O-E···

+Vee

FIGURE 27 - R-S FLIP-FLOP

FIGURE 28 - ASTABLE MUL TlVIBRATOR

Vee" +15 V

Vee

Vee

-0--<

t

>--o-...._Q

00-....

0_1

~F

100 k
51 k

>--o---+--evo

RESET SET

FIGURE 29 - POSITIVE-EDGE DIFFERENTIATOR

FIGURE 30 - NEGATIVE-EDGE DIFFERENTIATOR
0.001

~F

Output Rise Time ~ 0.22 ms

Input Change Time Constant ~ 1.0 ms

0.001

~F

I

100 k
100 k

tWin

~ ~~2~_F~~~

6.Vin

~~~2~~F~~5Nlk~~

>--o-~-evo

150 k

Vee

(MC3301-Page 8)

7-453

=

+15 Vdc

VO(dc) ~ 7.0 Vdc
Output Rise Time ~ 0.22 ms
Input Change Time Constant <;:: 1.0 ms

,---,,1

~_______________Q_U_A_D__C_O_M_P_A_R_A_T_O_R~

MC3302P

Product Previe-vv
MONOLITHIC QUAD
COMPARATOR
INTEGRATED CIRCUIT

MONOLITHIC QUAD SINGLE-SUPPL Y
COMPARATOR
These comparators are designed specifically for single posltlvepower-supply Consumer and Industrial electronic applications. Each
MC3302P contains four independent comparators - suiting it ideally
for usages requiring high density and low·cost.
•

Wide Operating Temperature Range - -40 to +85 0 C

•

Single-Supply Operation - +2.0 to +28 Vdc

•

Differential Input Voltage =±VCC

•

Compare Voltages at Ground Potential

•

MTTL Compatible

•

Low Current Drain - 600 IlA @ VCC= 5.0 Vdc

•

Outputs can be Connected to Give the Implied AND Function

EPITAXIAL PASSIVATED

TO-116
PLASTIC PACKAGE

MAXIMUM RATI NGS (TA = +25 0 C unless otherwise noted.1
Rating
Power Supply Range

Output Sink Current (See Note 1)

Symbol

Value

Unit

VCC

+2.0 to +28

Vdc

10

20

mA

FIGURE 1 ~ EQUIVALENT CIRCUIT

6~IO~

Different I"put Voltage

VIDR

±VCC

Vdc

Common· Mode I nput Voltage Range (See Note 21

VICR

-0.3to+VCC

Vdc

Po

625
5.0

mW
mW/oC

TA

-40 to +85

Tstg

-65 to +150

°c
°c

Power Dissipation (Package Limitation)
Derate above T A = +2S DC

Operating Temperature Range
Storage Temperature Range

Note 1.

Requires an external resistor, RL. to limit current below maximum rating.

Note 2.

If either (+) or (-) inputs of any comparator go more than several tenths of a volt
below ground, a parasitic transistor turns "on" causing high input current and possible faulty outputs.

eO~PTR

7

+

eO~PTR

1

-

11

4~ 8~
eOMPTR

5

+ 2

eO~PTR

2

9

Vee - PIN 3

FIGURE 2 - CIRCUIT SCHEMATIC

I
10-H~~~~:i5

11+
J-

9+

INPUTS

5+
4-:$=$=i====$===~l---r---l
67+ o-f---t--t-'-{

See Packaging Information Section for outline dimensions.

7-454

13

+

+

GROUNO - PIN 12

14

MC3302P (continued)

ELECTRICAL CHARACTERISTICS (Vee = +15 Vdc, TA = +25 0 e [each comparator] unless otherwise noted.)
Characteristic
Power Supply Current Itotal for four comparators)

VCC = 5.0 V}
VCC = 15 V
VCC = 28 V

Symbol

3

10

Min

-

Max

Unit

0.6
0.7
0.8

1.5
1.5
1.5

-

150
150

400
400

-

6.0

-

-

-

10

liB
TCIIB

-

30
0.16

500

nAdc

-

nA/oC

110
TCIIO

-

3.0
0.035

100

nAdc

-

nA/oC

VIO
TCVIO

-

3.0
7.0

10

mVdc

-

"V/oC

26

-

-

3

Typ

mAdc

(SI = A, S2 = A)

Output Voltage Low (10 = 1.6 mAl
VCC = 5.0 V}
VCC=15V

Fig. No.

mVdc

VOL

-

(SI = B S2 = B)
'

Output Sink Current
TA = -400C, VOL = 400 mV

-

Output Leakage Current
Vo high, S 1 = A, S2 = e

3

Input 8ias Current (both inputs)
(SI = A,B; S2 = A)
Temperature Coefficient

3

Input Offset Current
Temperatu re Coefficient

3

Input Offset Voltage (VIO = [Vref - Vinl )
VRef = 1.2 Vdc
Temperature Coefficient

4

Common-Mode Input Voltage Range
Vin = 50 mVp·p, VCC = 28 Vdc

5

Common-Mode Rejection Ratio

-

CMRR

-

60

-

dB

Differential Input Voltage Range (SI = A,B; S2 = A)

3

VIDR

±VCC

-

-

Vdc

mAdc

10

"Adc

loff

Vdc

VICR

Transconductance

-

-

2.0

-

mhos

Voltage Gain (RL = 15 kilohms)

-

Avol

-

30,000

-

V/V

Propagation Delay Time

-

td

-

2.0

-

"s

Slew Rate

-

tSRtSR+

-

200
50

-

VI"s

-

Symbols conform to JEDEC Bulletin No.1 when applicable.

TEST CIRCUITS
(1/4 Circuit Shown)

FIGURE 4 - INPUT OFFSET VOLTAGE

FIGURE 3 - DC TEST CIRCUIT

Vee

Vee

Vee

Vee

15k~IOff j~%lk
1%

15 k 1%
100 k

,

B
r-----~--~~--__,

e

S2

Vee

0.1 /IF
A

>--'-0>--.....--. 0 UTPUT
VR.!

.-+--+-0--1

FIGURE 5 - INPUT COMMON·MODE
VOLTAGE RANGE

Vee

15 k 1%

7-455

•

~f

,,---------'

')

MC3401P

OPERATIONAL AMPLIFIERS

MONOLITHIC QUAD
OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

Specifications and Applications
InforII1ation

EPITAXIAL PASSIVATED

MONOLITHIC QUAD SINGLE-SUPPLY
OPERATIONAL AMPLIFIER
•

These internally compensated operational amplifiers are designed specifically for single positive power supply applications
found in industrial control systems and automotive electronics.
Each MC3401 P device contains four independent amplifiers making it ideal for applications such as active filters, multi·channel
amplifiers, tachometer, oscillator and other similar usages.

•

I nternally Compensated

•

Wide Unity Gain Bandwidth - 5.0 MHz typical
Low Input Bias Current - 50 nA typical

•

High Open·Loop Gain - 1000 V/V minimum

- PLASTIC PACKAGE
CASE 646
ITO·116)

6~8~

9

3~11~

10

AMPL ~2

•

"

•

FIGURE 1 - EQUIVALENT CIRCUIT

Single·Supply Operation - +5.0 Vdc to +18 Vdc

•

>

•

1

5

AMPl ~I

+

2

Vee - pin 14

AMPl13

13

+

4

+

AMPLI4

12

+

Ground - pin 7

FIGURE 2 - SMALL·SIGNAL TRANSIENT RESPONSE

510 k

510 k

>-<>-+-r-eVo
5.1 k

1.0 M

FIGURE 3 - INVERTING AMPLIFIER

FIGURE 4 - NONINVERTING AMPLIFIER

RI

Rt

510 k

Ri
O.l/lF 51 k
Vin ~I-"""''''''''>-O--I
C

RI

AV =-R;

+15 V

1
lor

wC

510 k

Ri
O.l/lF 510 k

Vin ---71--""fv-......o--I
1M
+15 V

AV=10

AV = _ _R::;I,-- ",1
26
Ri+-IrlmA)
BW = 250 kHz

« Ri

BW=150kHz

7-456

MC3401 P (continued)

MAXIMUM RATINGS (TA

=

+25 0 C unless otherwise noted.)

Rating

Symbol

Value

Unit

Vce

+18

Vdc

lin

5.0

mA

PD

625
5.0

mW
mW/oe

TA

o to +75

°e

T stg

-65 to +150

°e

Power Supply Voltage
Non~inverting

Input Current

Power 0 issipation

Derate above T A

= +25 0C

Operating Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS [Vee = +15 Vdc Rl = 5.0 kn, TA = +25 0 e (each amplifier! unless otherwise noted.)
Characteristic
Open-loop Voltage Gain
TA = +25 0 e

Fig. No.

Note

Symbol

5,9,10

1

Min

Typ

Max

Avol
1000
800

2000

-

-

-

-

6.9
7.8

10
14

-

50

-

-

300
500

5.0
0.5

10
1.0

-

VOH
VOL
VO(p_p)

13.5

0.1

10

14.2
0.03
13.5

-

VIp-pi

Rin

0.1

1.0

-

MEG n

SR

-

0.6

-

V/!"s

5.0

-

MHz

-

Degrees

OOe~TA ~+750e

6,12

Quiescent Power Supply Current (Total for four amplifiers)
Noninverting inputs open
Noninverting inputs grounded

Input Bias Current, RL
TA = +25 0 e
OOC~TA ~+750e

5

3

Output Current
Source Capability
Sink Capability

5
13
14

4

Output Voltage
High Vol tage
low Voltage
Undistorted Output Swing (O°e

7
7
8

5
5
6

= 100pF,

mAdc
Isink

< TA < +750 e)

= 5.0k)

Unity Gain Bandwidth

BW

Phase Margin
Power Supply Rejection (f

nAdc

liB

Isource

5
Rl

mAdc

Vdc

Input Resistance

Slew Rate (Cl

V/V

2
IDO
IDG

= 00

Unit

= 100 Hz)

7

Channel Separation (f = 1.0 kHz)

-

--l

r

~<>--------~----.Vo

'source

~Vin

6TIB

Rm =

>-.....-.Va

100 is total supply current with "+" input open.
IDG is total supply current with "+" input grounded.

"'VO
Avol = ~ t.Vin

Amplifier must be biased (by Vin) in the
linear operating region.

FIGURE 8 - PEAK-TO-PEAK OUTPUT VOLTAGE

FIGURE 7 - OUTPUT VOLTAGE SWING

Rf
510 k
10 k

+1.0Vde

I

><>---~-----
~

./

,-

>

30~~~##~~ii##~~ii~~tdii##rt~iiHffi

----

./

L.

~ 100 0

g
~ 2ort~ii##~~ii##~~ii~~~ii~rt~iiHffi

g

~

o

J

~

~200 0
z

z

o

10~~-H#H~~-H#H~~-H#H~~rH#Hrt~-HBffi

"

50 0

~

0
2.0

4.0

6.0

8.0

10

12

14

16

18

20

f. FREQUENCY (Hz)

Vcc. SUPPLY VOLTAGE IVdc)

FIGURE 11 - OUTPUT RESISTANCE versus FREQUENCY

FIGURE 12 - SUPPLY CURRENT versus SUPPL Y VOLTAGE

10

10 k

-

lOG (Positive inputs grounded)
~

8.0

I-

~

~

k

a:

.....

6. 0

13
~

8:::

--

\
V

.§.

~

f-

I-- ~

r-r

~

\

100 (Positive inputs open)

4. 0

i5l
ci

E?

c5 2. 0

/'-..

E?

100

0.5 k 1.0 k

0

5.0k 10k

50kl00k

500 k 1.0 M

5.0 M

2.0

4.0

8.0

10

12

14

16

18

FIGURE 13 - LINEAR SOURCE CURRENT versus
SUPPLY VOLTAGE

FIGURE 14 - LINEAR SINK CURRENT versus
SUPPL Y VOLTAGE

1.4

14

--

12

,...........

-

0
0

20

Vcc. SUPPLY VOLTAGE (Vdc)

f. FREQUENCY

~

/

1.2

~ 1.0
«

I

.L

/

.§.
I-

~

0.8

13

0.6

./

a:

'"u;z

0

-;1
:E

0

o

6.0

-=- r--

/'

./

0.4
0.2

o

2.0

4.0

6.0

8.0

10

12

14

16

18

o

o

20

2.0

4.0

6.0

8.0

10

12

14

Vcc. SUPPLY VOLTAGE IVdc)

Vcc. SUPPLY VOLTAGE IVdc)

7-459

16

18

20

MC3401 P (continued)

OPERA·nON AND APPLICATIONS
Basic Ampl ifier
The basic amplifier is the common emitter stage shown in Figures
15 and 16. The active load 11 is buffered from the input transistor
by a PNP transistor, Q4. and from the output by an N PN transistor,
02. Q2 is biased class A by the current source '2. The magnitude
of 12 (specified 'sink) is a limiting factor in capacitively coupled

linear operation at the output. The sink current of the device can
be forced to exceed the specified level with an increase in the

distortion appearing at the output. Closed loop stability is maintained by an on-the-chip 3-pF capacitor shown in Figure 18. No

external compensation is required.

FIGURE 15
BLOCK DIAGRAM
VCCo+--------~-------+--------~------~--------~--------+_------~--------~------_,

14

I
I

10

BIASING CIRCUITRY
OPERATIONAL
OPERATIONAL
OPERATIONAL
Vcc~~______~____~__~~__~~~~~~~+f~__~A=M=P=LI=FI=E~R~#2~4r~~~__=A~M=PL=I~FI~E~R~#3~~~~~~A~M~P~LI~F=IE=R~#~4~,
14

I
I

I
I
10k

I
I
I
I

I

I .i;---------t---;:

CR~ o,-------r:
CR3
I

IL _ _ _ _ _ _ _ _

CR4

12

13

I

A noninverting input is obtained by adding a current mirror as
shown in Figure 17. Essentially all current which enters the noninverting input. I in2. flows through the diode CR 1. The voltage
drop across CR 1 corresponds to this input current magnitude and
this same voltage is applied to a matched device, 03. Thus 03 is

alpha current gain of" 03 ~ 1, its collector current ~ I in2 also.
In operation this current flows through an external feedback resis-

biased to conduct an emitter current equal to I in2.

"Normal Design Procedure" section.

Since the

tor which generates the output voltage signal. For inverting applications, the noninverting input is often used to set the de quiescent
level at the output. Techniques for doing this are discussed in the

FIGURE 17 - OBTAINING A NONINVERTING INPUT

FIGURE 16 - A BASIC GAIN STAGE

I

linl---...

OUTPUT

I-I

-

INPUTS

1+) o--t----[
tin2

CRI

Biasing Circuitry

The circuitry common to all four amplifiers is shown in Figure 19.
The purpose of this circuitry is to provide biasing voltage for the
PNP and NPN current sources used in the amplifiers. .
The voltage drops across diodes CR2. CR3 and CR4 are used as

references. The voltage across resistor R 1 is the sum of the drops
across CR4 and CR3 minus the VSE of QB. The PNP current
sources (05. etc.! are set to the magnitude VBE/R1 by transistor

Q6.

Transistor Q7 reduces base current loading.

The voltage

across resistor R2 is the sum of the voltage drops across CR2, CR3
and CR4. minus the VSE drops of transistor Q9 and diode CR5.
The current thus set is established by CR5 in all the NPN current
sources (Q10, etc.1. This technique results in current source magnitudes which are relatively independent of the supply voltage.

7-460

MC3401 P (continued)

OPERATION AND APPLICATIONS Icontinued)
FIGURE 18 - A BASIC OPERATIONAL AMPLIFIER

FIGURE 19 - BIASING CIRCUITRY

H
........_ - -.....-0 OUTPUT
CR2
INPUTS
1+)

CR3

CRI

CR4

NORMAL DESIGN PROCEDURE
other than VCC. By setting Rf = Rr,lstili keeping Ir between
SIlA and 100 IlAI the output de level will be equal to V r .
Neglecting error terms, the expression for determining VOdc

1. Output Q-Point Biasing

A. A number of techniques may be devised to bias the quiescent

output voltage to an acceptable level. However, in terms of
loop gain considerations it is usually desirable to use the

is:

non inverting input to effect the biasing as shown in Figures
3 and 4. The high impedance of the collector of the non·
inverting "current mirror" transistor helps to achieve the
maximum loop gain for any particular configuration. I t is
desirable that the noninverting input current be in the 5p.A
to 100 IlA range.

VOdc

2

2. Gain Determination
A. Inverting Amplifier

This allows for maximum dynamic

The amplifier is normally used in the inverting mode. The
input may be capaeitively coupled to avoid upsetting the
de bias and the output is normally capacitively coupled to
eliminate the de voltage across the load. Note that when
the output is capacitively coupled to the load, the value of

C. Reference Voltage other than VCC ISee Figure 201.
The biasing resistor Rr may be returned to a voltage (V r )

FIGURE 21 - INVERTING AMPLIFIER WITH
Av = 100 AND Vr = VCC

FIGURE 20 - INVERTING AMPLIFIER WITH
ARBITRARY REFERENCE

510 k

RI

C*

0.1 p.F

Ai

~I-"'W-......-o-----t

5.1 k

--11--'VI~---o>---f

Vi"

>-o-.....- - - _ V O

t

R,

I,

V,
VO= V,Rf +

R,

Rr

The error terms not appearing in the above equation can
cause the dc operating point to vary up to 20% from the
expected value. Error terms are minimized by setting the
input current within the range of 5 #lA to 100 #lA.

range of the output voltage.

Vi"

IVr ) IRf)

where rp is the VBE drop of the input transistors (approximately 0.7 Vdc @ +2So CI.

B. VCC Reference Voltage Isee Figures 3 and 4)
The noninverting input is normally returned to the Vee
voltage (which should be well filtered) through a resistor,
Rr • allowing the input current, I r • to be within the range of
S p.A to 100 IlA. Choosing the feedback resistor, RI, to be
equal to ~ Rr will now bias the amplifier output dc level to
approximately Vee.

=

*Select for low

11-'!t)~

A,

=100

. frequency response.

R,

7-461

+15 V

fL = 300 Hz, fH = 50 kHz

MC3401 P (continued)

NORMAL DESIGN PROCEDURE (continued!
6. Noninverting Amplifier

'sink becomes a limitation with respect to the load driving
capabilities of the device. The Iimitation is less severe if the
device is direct coupled. rn this configuration, the ae gain

Although recommended as an inverting ampJifier, the Me
3401P may be used in the non inverting mode (see Figure 4!.
The amplifier gain in this configuration is subject to the
same error terms that affect the output Q point biasing so
the gain may deviate as much as ±20% from that expected.
In addition, the resistance of the input diode must be included in the value of the input resistor. This resistance is

is determined by the ratio of Rt to Ri. in the same manner
as for a conventional operational amplifier:

26

approximately - ohms, where 'r is input current in mill iIr
amperes. The noninverting gain expression is given by:

The lower corner frequency is determined by the coupling

capacitors to the input and load resistors. The upper corner
frequency will usually be determined by the amplifier in~

ternal compensation.

The amplifier unity gain bandwidth

=

A

is typically 5.0 MHz and with the gain roll·off at 20 dB per
decade, bandwidth will typically be 500 kHz with 20 dB of
closed loop gain or 50 kHz with 40 dB of closed loop gain.

Rf

v

26

±.20%.

Ri+ Ir (rnA!
The bandwidth of the non inverting configuration for a given
Rf value is essentially independent of the gain chosen. For
Rf = 510 kn the bandwidth will be in excess of 200 kHz
for noninverting gains of 1, 10, or 100. This is a result of
the loop gain remaining constant for these gains since the
input resistor is effectively isolated from the feedback loop.

The exception to this occurs at low gains where the input
resistor selected is large. The pole formed by the amplifier
input capacitance, stray capacitance and the input resistor
may occur before the closed loop gain intercepts the open
loop response curve. The inverting input capacity is typically 3.0 pF.

TYPICAL APPLICATIONS
FIGURE 22 - AMPLIFIER AND DRIVER FOR A 50·0HM LINE
510 k

51 k
Vin --11-JV\~""'--o>---l
0.1 pF

10

10

1.2 M

Av = 10

Va

=

5.6 k

6 Vlp·p!

+rva
20pF

2N4403
or equiv

50

+15 V

FIGURE 23 - BASIC BANDPASS AND NOTCH FILTER

Rl

t-----VV~-.--4BP

Tap = Center Frequency Gain

TN

=

Passband Notch Gain
1

wa=Rc
Rl

~TCH

=OR
RI

R2=-

TBP

R3 = TN R2

7-462

MC3401 P

(continued)

TYPICAL APPLICATIONS

(continued)

FIGURE 24 - BANDPASS AND NOTCH FILTER
62 k

100 k
300 k

100 k

62 k

300 k

120' k

100 k
Vee

100 k

Vee

300k

Vee

300k

Vec (Pin 141 = +12 Volts
Ground - pin 7

11

10

300 k

Center Frequency 500 Hz

>--c.--....- _ NOTCH

11=5

Bandpass Gain::: 1

300 k

Vin

Vce ....-'l/V'I.----<>-....

OUTPUT

7-463

OV

•

MC5528
MC5529
MC7528
MC7529

~~_________D_U_A_L_S_E_N_S_E_A_M_P_L_IF_I_E_R_S__~

DUAL HIGH-SPEED
SENSE AMPLIFIER
WITH PREAMPLIFIER
TEST POINTS

MONOLITHIC DUAL SENSE AMPLIFIERS
WITH PREAMPLIFIER TEST POINTS
This dual sense amplifier is designed for use with high-speed
memory systems. low level pulses originating in the memory are
converted to logic levels compatible with MDTl and MTTl circuits.
External preamplifier test points provide for very accurate timing
of the strobe with the input signal.
•

Adjustable Threshold Voltage levels

•

High-Speed, Fast Recovery Time

MONOLITHIC SILICON
INTEGRATED CIRCUIT

16

• Time and Amplitude Signal Discrimination
•

High dc logic Noise Margin
1.0 Volt typ

• Good Fan-Out Capability
•

Independent Strobing

L SUFFIX
CERAMIC PACKAGE
CASE 620

• Separate logic Outputs
• Test Points Available for Accurate Strobe Timing

SCHEMATIC DIAGRAM

P SUFFIX
PLASTIC PACKAGE
CASE 648
(MC7528 and MC7529 only)

}--,---t-+--+-+----t-o',"

r--r-r---('"'

TEST
Vee

Cext

See Packaging Information Section for outline dimensions.

7-464

POINT
A

TEST
STROBE OUTPUT OUTPUT STROBE POINT
A
A
B
B
B

-DIFFERENTIAL
INPUT A

~

REFERENCE

INPUT

--

DIFFERENTIAL
INPUTB

GND

Vee

MC5528, MC5529, MC7528, MC7529 (continued)

MAXIMUM RATINGS ITA

=

+2SOC unless otherwise noted.)
Svmbol

Value

Units

VCC
VEE

+7.0
-7.0

Vdc
Vdc

Vin or Vref

±5.0

Vdc

PD

575
3.85

mWoC

Rating
Power Supply Voltage

Differential I nput Voltages
Power Dissipation

Derate above T A = +2SoC
Operating Temperature Range

mW
°c

TA

-55 to +125
o to +70

MC5528. MC5529
MC7528, MC7529

-55 to +150

T stg

Storage Temperature Range

°c

ELECTRICAL CHARACTERISTICS IVcC = +5.0 V ±5%, VEE = -5.0 V ±5%. TA = Tlow# to Th;gh# unless otherw;se noted.1

CD

MC7528 #
MC7529

MC5528
#
MC5529

Characteristic

Symbol

Differential Input Threshold Voltage IVinS - +5.0 V, VID - ±Vth'

Min

Typ

Max

Min

Typ

MC5528,MC7528
MC5529,MC7529

10
8.0

15

11
8.0

15

IVre! = 40 mV, IL = 16 mA, Va <0.4 VI

MC5528,MC7528
MC5529,MC7529

35
33

40

36
33

40

-400~A,

Va >2.4 VI

MC5528,MC7528
MC5529,MC7529

15

20
22

15

19
22

IVre! = 40 mY. IL = -400~A, Va >2.4 VI

MC5528,MC7528
MC5529,MC7529

40

45

40

44
47

30

75

0.5

-

Differential and Reference Input Bias Current

47

~A

liB

IVID = V re ! = OV, V;nS = +5.25 V, Vs = ±5.25 VI

30

Differential Input Offset Current
IVID = V re ! = 0 V, V;nS = +5.25 V, Vs = ±5.25 VI

100

IIOD
0.5

Input VOltage, Logic "1"
(VlD "" 40 mV, Vref = 20 mV. VinS = 2.0 V, 'L = 400 JJ.A.

Unit
mV

IVre! = 15 mY. IL = 16 mAo Va <0.4 VI

IVre! = 15 mV, IL =

Max

Vth

~A

V

Vin"l"
2.0

2.0

Vs = ±4.75 V. VO>2.4 VI
Input VOltage, Logic "0"
(VID = 40 mV, Vref == 20 mV, VinS '" 0.8 V, IL

V

Vin"O"

= 16 mA,

O.B

0.8

Vs = ±4.75 V, VOL <0.4 VI
Input Current, Logic "1"

lin"1"

5.0

IVID = 0 V, V re ! = 20 mY. V;nS = 2.4 V, Vs = ±5.25 VI MC5528,MC5529
IVID '" a v, Vref '" 20 mV, VinS::: +5.25 V,
MC7528,MC7529
Vs = ±5.25 VI
Input Current, Logic "0"

lin"O"

IVID = 40 mV, V re ! = 20 mY. V;nS = 0.4 V, Vs = ±5.25 VI
Output Voltage, Logic "".
Output Voltage. Logic

"a"

~1.0

-1:6

2.4

3.9

-

Short·Circuit Output Current

= +5.25 V,

-1.0

-1.6

0.25

0.40

-2.8

-3.5

29
-13

3.9
V
0.25

0.40

-2.8

-3.5

40

29

40

-18

-13

-18

rnA
-2.1

-2.1

mA

ICC

IVID = V;nS = 0 V, V re! = 20 mY. Vs = ±5.25 VI
VEE Supply Current

mA

lEE

IVID = V;nS = 0 V, V re! = 20 mY. Vs = ±5.25 VI
For OOC STA S70 0 C operation; electrical characteristics for MC5528 and
MC5529 are guaranteed the same as MC7528 and MC7529 respectively.

7-465

mA

V
2.4

IOSC
Vs = ±5.25 VI

Vee Supply Current

CD

1.0

VO"O"

IVID = 40 mV, V re ! = 20 mV, V;nS = 0.8 V, IL = 16 mA, Vs = ±4.75 VI
IVID = 40 mV, V re ! = 20 mV, V;nS

0.02

mA

-

VO"I"

IVID = 40 mV, V re! = 20 mY. V;nS = 2.0 V, IL =-400~. Vs =±4.75 VI

~A

40

# Tlow

= -55°C for MC5528, MC5529, OOC

for MC7528. MC7529

Th;gh = +125 0 C for MC5528, MC5529; +70 0 C for MC7528, MC7529

I

MC5528, MC5529, MC7528, MC7529 (continued)

ElECTR IcAl CHARACTER ISTICS I vcc :

+S,D V ±S%, VEE: -S,O V ±S%, TA : +2SoC unless otherwise noted,)
MC5628
MC56,29

Characteristic
AC Common-Mode Input Firing Voltage

Symbol

Typ

Min

Propagation Delay Time, Differential Input to logic "1" Output

tPLHD

,

Propagation Delay Tirne, Strobe Input to Logic "0" Output

(Vref

= 20 mV)

Overload Recovery Time, Differential Input

28
tpHLS
tPHLS

":,,,
'

,20'
tRD

5:0

tRCM

',':.:c7,

Minimum Cycle Time

t{min)

,-

@
@

"

10.

Positive current is defined as current into the referenced pin.

Pin 1 to have 2::100 pF capacitor connected to ground.
Each test point to have ~15 pF capacitive load to ground.

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

I

7-466

.,-'

Max

Unit

±2,S

",

4b'

"20,0.

20

40
ns

"I' ,,-,

°'10'

',-

Overload Recovery Time, Common-Mode Input



,"
20.,

"

tpHLD

IV,e!: 20 mV)
IV,e!: 20 mV)

Typ

V

:±2,5

IV,e!: 20 mV)

Propagation Delay Time, Strobe Input to Logic "1" Output

Min

Max

,

VCMF

IV,e!: 20 mV, VinS: S,O V)

Propagation Delay Time, Differential Input to Logic "0" Output

MC7528
MC7529

,

28
ns

3D

10

,',"

30
ns

20
10

ns

:~

5,0

ns

',"""

20.0

ns

',,-:

'

MC5534
MC5535
MC7534
MC7535

l ________

D_U_A_L_S_E_N_S_E_A_M_P_L_'_F_'E_R_S_----'

MONOLITHIC DUAL SENSE AMPLIFIERS
WITH INVERTED OUTPUTS

DUAL HIGH-SPEED
SENSE AMPLIFIER
WITH
INVERTED OUTPUTS

This dual sense amplifier is designed for use with high-speed
memory systems_ Low level pulses originating in the memory are
converted to logic levels compatible with MDTL and MTTL circuits_
These circuits are identical to the MC7524 except that an additional
stage has been added to each output gate to provide an inverted
output_
•

Adjustable Threshold Voltage Levels

•

High-Speed, Fast Recovery Time

[::::::1
16

• Time and Amplitude Signal Discrimination
•

MONOLITHIC 51 LICON
INTEGRATED CIRCUIT

High dc Logic Noise Margin
1.0 Volt typ

• Good Fan-Out Capability
•

Independent Strobing

• Separate Logic Outputs
•

(top view)

-

L SUFFIX
CERAMIC PACKAGE
CASE 620

Normally High Outputs Accomodate the Wired-OR of
Several Sense Amplifiers

SCHEMATIC DIAGRAM

P SUFFIX
PLASTIC PACKAGE
CASE 648
(MC7528 and MC7529 only)

STROBE
A

OUTPUT
A

liND 1

OUTPUT STROBE
B
B

Cext
DiffERENTIAL
INPUT A

See Packaging Information Section for outline dimensions.

7-467

REFERENCE
INPUT

N.C.

DIFFERENTIAL
INPUTB

GNO 1

MC5534, MC5535, MC7534, MC7535 (continued)

MAXIMUM RATINGS (TA = +2SoC unless otherwise noted.)
Rating
Power Supply Voltage

Symbol

Value

Units

VCC
VEE

+7.0
-7.0

Vdc
Vdc

Vin or Vref

±5.0

Vdc

Power Dissipation
Derate above T A = +2SoC

Po

575
3.85

mW
mWoC

Operating Temperature Range

TA

Differential Input Voltages

°c
-55 to +125

MC5534. MC5535
MC7534. MC7535

o to +70

Storage Temperature Range

-55 to +150

T,tg

'C

ELECTRICAL CHARACTERISTICS IVCC = +5.0 V ±5%. VEE = -5.0 V ±5%. T A = T,ow# to Th;gh# unless otherw;se noted.1
MC5534·(1).
M~.36

Characteristic

Symbol : ." Min

Differential Input Threshold Voltage (VinS::: +5.0 V, VID::: ±Vth)
IV,el = 15 mV. VL = +5.25 V. 'L <250~AI
MC5534. MC7534
MC5535. MC7535
IV,el = 40 mV. VL ="5.25 V. 'L <250~AI

10

S.O'
1,'36

MC5534. MC7534
MC5535. MC7535

IV,el = 15 mV. 'L = 20 mAo Va =<0.4 VI

MC5534. MC7534
MC5535. MC7535

IV,el = 40 mV. 'L = 200 mAo Va =<0.4 VI

MC5534. MC7534
MC5535. MC7535

Differential Reference Input Bias Current

"';','

"

','40 .

Min

Typ

11
8.0

15

36
33

40

20,

15

Max

15

19
22

40

46
47

40

44
47

30

100

30

75

0.6

-

0.5

~A

',8

',00

V. Vs = ±5.25 VI

Vin"O"

Input Voltage, Logic "1"
IV,D = 40 mV. V,el = 20mV. V;nS = 2.0 V. 'L = 20 mAo
Vs = ±4.75 V. Va =<0.4 VI

Vin"l"

Input Current, Logic "0"
(VID = 40 mV, Vref = 20 mV, VinS '" 0.4 V, Vs = ±5.25 VI

lin"O"

Input Current, Logic "1"
IVID = 0 V. Vrel = 20 mV. VinS = 2.4 V. Vs = ±5.25 VI MC5534. MC5535
MC7534, MC7535

lin"1"

Output VOltage, Logic "0"
IV,D = 40 mV. V,el = 20mV. VinS = 2.0 V. 'L = 20 mAo Vs = ±4.75 VI

VO"O"

Unit
mW

22:

Input Voltage, logic "0"
IV,D = 40 mV. V,el = 20 mV. V;nS '" 0.8 V, VL = +5.25 V.
Vs = ±4.75 V. 'L =<250~AI

~A

V
0.8

0.8

'~

V

:2.0:

2.0

-1.0,

'\:0
L

:-;

'OL

VCC Supply Current
IV,o,;, V;nS = 0 V. V,el = 20 mV. Vs = ±5.25 VI

'CC

VEE Supply Current
IV,D = VinS = 0 V, V,el = 20 mV. Vs = ±5.25 VI

lEE

For OOC"

20 mV)

Propagation Delay Time, Differential Input to Logic "0" Output
!Vref = 20 mV)

tpHLD

Propagation Delay Time, Strobe Input to Logic "1" Output
IV,e! = 20 mVI

tPLHS

Propagation Delay Time. Strobe Input to Logic "0" Output
IV,e! = 20 mVI

tPHLS

Min

Typ

24

24

t(min)

200

Pin 1 to have ):100 pF capacitor connected to ground,

20

30

10

40

16

ns
10

Minimum Cycle Time
Positive current is defined as current into the referenced pin.

40.

16

10
6.0

®

Unit

ns

tRCM

@

Max

v
±2.5

20

tRD

Min

±2.5

Overload Recovery Time, Common-Mode I "put

Overload Recovery Time, Differential Input

Max

MC7534
MC7535
Typ

30

10
5.0
200

ns
ns

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable,

•
7-469

MC5538
MC5539
MC7538
MC7539

\

D_U_A~L_S_E_N_S_E_A_M_P_L_IF_I_E_R_S_---I

......_ _--'-__

DUAL HIGH-SPEED
SENSE AMPLIFIER

MONOLITHIC DUAL SENSE AMPLIFIERS
WITH PREAMPLIFIER TEST POINTS
AND INVERTED OUTPUTS

WITH
PREAMPLIFIER TEST POINTS
AND
INVERTED OUTPUTS

This dual sense amplifier is designed for use with high-speed
memory systems_ Low level pulses originating in the memory are
converted to logic levels compatible with MDTL and MTTL circuits_
These devices are identical to MC5528/MC7528 with the exception
of the inverted outputs.
•

Adjustable Threshold Voltage Levels

•

High-Speed, Fast Recovery Time

•

Time and Amplitude Signal Discrimination

•

High dc Logic Noise Margin
1.0 Volt typ

•

Good Fan-Out Capability

MONO LITHIC SI LICON
INTEGRATED CIRCUIT

16

•

I ndependent Strobing

•

Separate Logic Outputs

•

Test Points Available for Strobe Timing

•

Inverted Outputs to Accomodate Wired-OR Outputs of
Several Sense Amplifiers

L SUFFIX
CERAMIC PACKAGE

CASE 620

SCHEMATIC DIAGRAM

P SUFFIX

l--t---.--+----t---1----f--o c,,'

PLASTIC PACKAGE

CASE 648
(MC7538 and MC7539 only)

Vee

TEST
POINT
A

STROBE
A

TEST
OUTPUT OUTPUT STROBE POINT
A
B
B
B

Cext

See Packaging Information Section for outline dimensions.

7-470

-DIFFERENTIAL

REFERENCE

DIFfERENTIAL

INPUTA

INPUT

INPUTS

GND

VEE

MC5538, MC5539, MC7538, MC7539 (continued)

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted.)
Symbol

Value

Units

VCC
Vee

+7.0
-7.0

Vdc
Vdc

Vi" or Vref

±5.0

Vdc

Po

575
3.85

mW

Rating
Power Supply Voltage

Differential I nput Voltages
Power Dissipation

Derate above T A = +2SoC
Operating Temperature Range

mWoC

°c

TA

MC5538, MC5539
MC7538, MC7539

-55 to +125

a to +70
T stg

Storage Temperature Range

°c

-55'0 +150

ELECTRICAL CHARACTERISTICS IVcc = +5.0 V ±5%. VeE = -5.0 V ±5%, TA = Tlow# to Thigh# unless othe",i,e noted.1
MC5538 G) #
MC5539
Charactoristic

Symbol

Differential Input Threshold Voltage IVinS - +5.0 V, VID - ±Vth)
MC5538, MC7538
IV,el = 15 mV, VL = +5.25 V, IL <250 ~AI
MC5539, MC7539

= +5.25

Typ

10
8.0

15

35
33

40

MC753B*
MC7539
Ma.

Min

TVp

11

15

Ma.

8.0

IV,el

= 40 mV,

VL

IV,el

= 15 mV,

IL

= 120 mA,

VL <0.4 VI

MC5538, MC7538
MC5539. MC7539

15

20
22

15

19
22

IV,el

= 40 mV,lL = +20 mA,

VL <0.4 VI

MC5538, MC7538
MC5539, MC7539

40

45
47

40

44
47

30

100

30

75

V, I L < 250 ~AI

MC5538. MC7538
MC5539. MC7539

IVID

= V,el = 0

V, VinS

= +5.25 V,

Vs

Input Voltage, Logic "0"
(VID = 40 mV. Vref = 20 mV, VinS:: +0.8 V, VL::: +5.25 V,
Vs = ±4.75 V, IL < 250~A)

Vin"Q"

I nput Current, Logic "1"
IVID = 0 V, V,el = 20 mV, VinS = 2.4 V, Vs
IVID::: 0 V, Vref::: 20 mV, VinS::: +5.25 V,
Vs =±5.25 V)

lin"1"

= 0.4

uutput Voltage, Logic "U"
IVIO = 40 mV, V,el = 20 mV, VinS

= 2.0 V.

vCC ~upplV <.;u"en,
(VIO = VinS;:; a V, Vref
VEE Supply Current
IVID = VinS = 0 V, Vs

= 20 mV,

V, Vs
IL

~A

0.5
V

2.0

V

MC5538, MC5539
MC7538, MC7539

Vs

2.0

0.8

0.8

5.0

=±4.75 V)

~A

40
0.02

1.0

-1.0

-1:6

-1.0

-1.6

0.25

0.40

0.25

0.40

V

VO"O"

mA

ICC
VS;:: ±5.25 V)

=±5.25 V)

28

38

28

38

-13

-18

-13

-18

mA

lee

For OOC~T A~70oC operation, electrical characteristics for MC5538 and
MC5539 are guaranteed the same as MC7538 and MC7539 respectively.

Tlow
Thigh

7-471

mA
mA

lin"O"

= ±5.25 V)
= 20 rnA.

~A

0.5

Vin"'"

Input Current, Logic "0"
IVIO = 40 mY. Vrel = 20 mV, VinS

40

1100

Input Voltage, Logic "1"
(VID = 40 mV, Vref = 20 mV, VinS = +2.0 V, IL = 20 rnA,
Vs = ±4.75 V, VL <0.4 V)

=±5.25 V)

36
33

liB

= ±5.25 V)

Differential Input Offset Current
IVIO = V,el = 0 V, VinS = +5.25 V. Vs = ±5.25 V)

Unit
mV

Vth

Differential and Reference Input Bias Current

CD

Min

= -55°C 10' MC5538, MC5539; OoC 10' MC7538, fvlC7539
= +125 0 C 1o, MC5538, MC5539; +700 C 10' MC7538, MC7539

•

MC5538, MC5539, MC7538, MC7539 (continued)

ELECTRICAL CHARACTER ISTICS (Vcc = +5.0 V ±5%, VEE = -5.0 V ±5%, T A = +25 0 C unle" otherwise noted.1

Characteristic
AC Common-Mode Input Firing Voltage

(Vref

=

Symbol

20 mV, VinS '" 5.0 VI

Propagation Delay Time, Differential Input to Logic "0" Output
(Vref = 20 mVl

tpHLD

Propagation Delay Time, Strobe Input to Logic "1" Output
(Vref = 20 mVI

tpHLS

Propagation Delay Time, Strobe I nput to Logic "0" Output
(Vref:' 20 mV)

tPHLS
tRD

Overload Recovery Time, Common-Mode Input

'RCM

Minimum Cycle Time

t(min)



Positive current is defined as current into the referenced pin.
Pin 1 to have ~100 pF capacitor connected to ground.

@)

Each test point to have $15 pF capacitive load to ground.

Min

MI'

Symbols conform to JEDEC Engineering Bulletin No.1 when applicable.

7-472

Unit

V

±2,5

±2,5
tPLHD

@

MI.

MC7538
MC7539
Typ

VCMF

Propagation Delay Time, Differential Input to Logic "1" Output
IVref '" 20 mV)

Overload Recovery Time, Differential Input

Min

MC5538
MC5539
Typ

ns

24

24

20

40

20

16

-

16

10

30

10

10
5,0
200

-

ns

40
ns
ns

..

30

10
5.0

ns

200

ns

ns

'\

MC7520L

DUAL SENSE AMPLI F I ERS

'--------------'

thru

MC7523L
MONOLITHIC DUAL SENSE AMPLIFIERS
These dual sense amplifiers are designed for high-speed core memory
systems. Low-level pulses originating in the memory are converted to
logic levels compatible with MTTL and MDTL circuits_ Each of the
two basic device functions has two different threshold specifications_
The dual-input preampl ifiers are connected to a common output stage,
with each preamplifier output strobed independently_
The output circuit of the MC7520LlMC7521 L is comprised of
two cascaded NAN D gates, each having an external gate input. The
external gate inputs may be used to connect the Ei output to the
Gate Q input to achieve a flip-flop or register that responds to the
sense and strobe input conditions. Output pulse stretching may be
accomplished by resistive/capacitive coupling from the 6 output to
the Gate Q input.
The output circuit of the MC7522L1MC7523L features an opencollector output, permitting the wired-OR function. Load resistor
RL may be used as the output pullup resistor.
•

DUAL HIGH-SPEED
SENSE AMPLI FI ER
INTEGRATED CIRCUITS
MONOLITHIC SILICON
EPITAXIAL PASSIVATED

CERAMIC PACKAGE
CASE 620

MC7520L and MC7521 L

Adjustable Threshold Voltage Levels

•

High Speed, Fast Recovery Time

•

Time and Amplitude Signal Discrimination

•

High de Logic Noise Margin - 1.0 Volt typical

•

Good Fanout Capability

MC7522L and MC7523L

,:;t>co ~ "'''''0''
STROBEB"~
moo"

GA n

COMMON TO ALL OEVICES

Y 14

0--------

MC7520L and MC7521 ON L Y
V'
r----~----oIOGATEQ

12 OUTPUT

5

0:

Vref ~

40-----+-----.J
~-------r---t---o13

A2 3

OUTPUT Q

L--------------OI4GATEQ

r

AI 20--1--+_------'
AI50--1--+_--+--~------'

9GNO

STROBE

MC7522L and MC7523L ONLY

[
'

10 RL

B2 7 c>--+--t--1L
BI

6c>--+--+--i-~

BII

C>--+_-+--+------+~

12 OUTPUT Y

STROBE

See Packaging Information Section for outline dimensions.

7-473

•

MC7520L thru MC7523L (continued)

ELECTRICAL CHARACTERISTICS (v+

= 5.0 V, v-" -5.0 V, TA =

a to +700 C unless otherwise noted)
Min

TVp

Max

MC7520L,MC7522L
MC7521 L,MC7523L

11
8.0

15
15

19
22

MC7520L,MC7522L
MC7521 L,MC7523L

36
33

40
40

44
47

Svmbol

Characteristic

Input Threshold Voltage
Vrel = 15 mV
Vrel

= 40 mV

Unit
mV

Vth

VCMF

-

±3.0

-

Volts

Input Bias Current

lin

-

30

75

Il A

Input Ollset Current

lio

-

0.5

-

IlA

ZOn) D

.-

2.0

-

k ohms

Common-Mode Input Firing Voltage

Input I mpedance (I

= 1.0 kHz)

Input Voltage Logic "1" Level (Strobe Inputs)

Vin "0" - 0.8 V

Vin "1"

2.0

-

-

Volts

Input Voltage Logic "0" Level (Strobe Inputs)

Vin "1"

V

Vin "0"

-

-

0.8

Volt

Input Current Logic "0" Level (Strobe Inputs)

Vin

V

lin "0"

-

-

-1.6

mA

Input Current Logic "1" Level (Strobe Inputs)

Vin
Vin

V

lin "1"

-

-

40
1.0

IlA
mA

Output Voltage Logic "1" Level

Vin

Output Voltage Logic "0" Level

Vin

Short-Circuit Output Current

= 2.0
"0" = 0.4
"1" = 2.4
"1" = V+
"1" = 2.0
"0" = 0.8

V

Vout "1"

2.4

3.9

-

Volts

V

Vout "0"

-

0.25

0.4

Volt

ISC

3.3
2.1
2.1

-

5.0
3.5
3.5

mA

a Output MC7520L,MC7521 L
Output MC7520L,MC7521 L
Output MC7522L,MC7523L

o

= +25 0 C)

MC7520L,MC7521 L
MC7522L,MC7523L

1+

-

28
27

-

mA

V- Supply Current (T A = +25 0 C)

MC7520L,MC7521 L
MC7522L,MC7523L

1-

-

-14
-15

-

mA

V+ Supply Current (T A

-

-

SWITCHING CHARACTERISTICS (v+ = 5.0 V, V- = -5.0 V, TA = +25 0 C unless otherwise noted)
Symbol

Min

TVp

Max

Unit

Differential-Mode Input Overload Recovery Time

tOR DM

-

20

-

ns

Common-Mode I nput Overload Recovery Time

tOR CM

-

20

-

ns

Minimum Cycle Time

tc (min)

-

200

-

ns

tpd "1" DO

.-

20

40

tpd "0" DO

-

30

-

tpd "1" DO

-

25

-

tpd "0" DO

-

35

55

tpd "1"50

-

15

30

tpd "0" SO

-

25

-

tpd "1"50

-

15

-

tpd "0" SO

-

35

55

tpd "1" Goa

-

10

20

tpd "0" Goa

15

-

tpd "1" Goa

-

15

-

tpd "0" Goa

-

20

30

tpd "1" GaO

-

15

-

tpd "0" GOO

-

10

20

tpd "1" D

-

20

-

tpd "0" D

-

30

45

tpd "1" 5

-

15

-

tpd "0"5

-

25

40

tpd "1" G

-

10

-

tpd "0" G

-

15

25

Characteristic

MC7520L MC7521 L
ns

Propagation Delay Time
(Differential Input to a Outputi

(Differential Input to OO"tput)

(Strobe I nput to a Output)

(Strobe I nput to

Q Outputi

(Gate a I nput to a Output)

(Gate a I nput to a Output)

(Gate a Input to a Output)

MC7522L MC7523L
ns

Propagation Delay Time
(Differential Input to Output)

(Strobe I nput to Output)

(Gate I nput to Output)

7-474

MC7520L thru MC7523L (continued)

MAXIMUM RATI NGS

ITA = +25 0 C unless otherwise noted)

Rating
Power Supply Voltage

Differential I nput Signal Voltage
Strobe and Gate I nput Voltage
Power Dissipation

Derate above T A

Symbol

Value

V+
V-

+7.0

Vdc

-7.0

Vdc

Vin

±5.0

Vdc

t5.5

Vdc

VinS,G

575
3.85

mW
mWoC

TA

a to +70

T stg

·65 to +150

°c
°c

Po

= + 25 0 C

Operating Temperature Range
Storage Temperature Range

Units

7-475

•

MC7524L
MC7525L

"\

DUAL SENSE AMPLIFIERS

, ,_ _ _ _ _ _ _- - - - l

MONOLITHIC DUAL SENSE AMPLIFIERS
This dual sensE!" amplifier is designed for use with high-speed
memory systems. Low level pulses originating in the memory are
converted to logic levels compatible with MDTL and MTTL circuits.

DUAL HIGH-SPEED
SENSE AMPLIFIER
INTEGRATED CIRCUIT
MONOLITHIC SILICON
EPITAXIAL PASSIVATED

Features:
•

Adjustable Threshold Voltage Levels

•

High-Speed, Fast Recovery Time

•

Time and Amplitude Signal Discrimination

•

High dc Logic Noise Margin
1.0 Volt typ

• Good Fan-Out Capability
•

Independent Strobing

• Separate Logic Outputs

CERAMIC PACKAGE
CASE 620

16

VREF

Equivalent
Circuit

A,

,-----,

INPUTS

A,
OUTPUTA
STROBE A

15

2

STROBE A

"
"

INPUTS BI
B2
OUTPUTB
11

15

I

I

I

I

I
:

I

V'

INPUTS

I

INPUTsAI~114
A2
OUTPUT A

STROBE B

~
7

11

112

I

I

I .

I

L _____ J

STROBE B

See Packaging Information Section for outline dimensions.

7-476

OUTPUT B

MC7524L, MC7525L (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Power Supply Voltage

Differential I nput Voltages
Power Dissipation

Derate above T A

= +2SoC

Operating Temperature Range
Storage Temperature Range

Symbol
V+
V-

Value

Units

+7.0
-7.0

Vdc
Vdc

Vin or Vref

±5.0

Vdc

Po

575
3.85

mW
mWoC

TA

o to +70

Tstg

-55 to +150

°c
°c

ELECTRICAL CHARACTERISTICS (V+ = 5.0 V. V- = -5.0 V. TA = 0 to +70oC unless otherwise noted)
Symbol

Characteristic
Input Threshold Voltage

Vrel

= 15 mV

Vrel

= 40 mV

Min

Typ

Max

11
8.0
36
33

15
15
40
40

19
22
44
47

MC7524L
MC7525L
MC7524L
MC7525L

Unit
mV

Vth

VCMF

-

±3.0

-

Volts

Input Bias Current

lin

30

75

"A

Input Offset Current

lio

0.5

-

"A

ZOn! 0

-

2.0

-

k ohms

Common-Mode Input Firing Voltage

Input Impedance (I

= 1.0 kHz)

=0.8 V
= 2.0 V
Input Current Logic "0" Level (Strobe Inputs)
Vin(O) = 0.4 V
Input Current Logic "1" Level (Strobe Inputs)
Vin(l) = 2.4 V
Vinll! = V+
Output Voltage Logic "1" Level Vin(1) = 2.0 V. Vin(O) = 0.8 V
Output Voltage Logic "0" Level
Vin(O! = 0.8 V
Input Voltage Logic "1" Level (Strobe Inputs)

Vin(O)

Vin (1)

2.0

-

-

Volts

Input Voltage Logic "0" Level (Strobe Inputs)

Vin(l)

Vin (0)

-

-

0.8

Volt

lin (0)

-

-1.0

mA

lin (1)

-

-

-

-

-1.6
40
1.0

Short-Circuit Output Current

"A
mA

Vout (1)

2.4

3.9

-

Volts

Vout (0)

-

0.25

0.4

Volt

Isc(out)

2.1

-

3.5

mA

1+

_.

25

-

mA

1-

-

-15

-

mA

= +25 0 C
V- SupplV Current @ T A = +25 0 C
V+ Supply Current @TA

SWITCHING CHARACTERISTICS (V+ = 5.0 V. V- = -5.0 V. TA = +25 0 C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

Propagation Delay Time

tpd (1) 0

-

ns

tpdJOIO

-

15
40

40

(Oifierential Input to Output)
Propagation Delay Time

tpd (1) S
tpd (0) S

15
35

30

ns

(Strobe Input to Output)

20

-

ns

20

-

ns

200

-

ns

Characteristic

-

Differential-Mode Input Overload Recovery Time

toR OM

Common-Mode I nput Overload Recovery Time

tORCM

-

Minimum Cycle Time

tc (min)

-

7-477

-

I

MC55107
MC55108
MC75107
MC75108

'l~

_____

T_W
__
IS_T_E_D_'P_A_I_R_L_I_N_E_R_E_C_E_IV__
ER_S__~

MONOLITHIC DUAL LINE RECEIVERS
The MC55107/MC75107 and MC55l08/MC75108 are MTTL compatible dual
line receivers featuring independent channels with common voltage supply and
ground terminals.

DUAL LINE RECEIVERS

The MC55107/MC75107 circuit features an active pull-up

(totem-pole) output. The MC5510S/MC75108 circuit features an open-collector
output configuration that permits the Wired-OR logic connection with similar

MONOLITHIC SILICON
INTEGRATED CIRCUITS

outputs (such as the MC5401/MC7401 MTTL gate or additional MC55l0S1

MC75108 receivers), Thus a level of logic is implemented without extra delay.
Both receivers feature double-protected input stages to guard against line loading
under zero value supply conditions.

The MC55107/MC75107 and MC55l0S/MC7510S circuits are designed to
detect input signals of greater than 25 millivolts

amplitu~e

and convert the po-

larity of the signal into appropriate MTTL compatible output logic levels.
•

High Common·Mode Rejection Ratio

•

High Input·lmpedance

•

High Input Sensitivity

•

Differential Input Common-Mode Voltage Range of ±3.0 V

•

Diode·Protected Input Stage

•

Differential Input Common·Mode Voltage of More Than ± 15 V
Using External Attenuator

•

Strobe Inputs for Receiver Selection

•

Gate Inputs for Logic Versatility

•

MTTL or MDTL Drive Capability

•

High DC Noise Margins

PLASTIC PACKAGE
L SUFFIX
CASE 646
CERAMIC PACKAGE
(TO-116)
CASE 632
(TO-116)
(MC75107. MC75108 only)

CIRCUIT SCHEMATIC
VCCO-~--~--~--~------~------~------~~--~

14

850

850

186

4 k

1.6 k

INPUTS

2A

I

L-----+-----I---<>
2.5 k

OUTPUT STROBE
2 V
2G

1G

2.5 k

STROBE
S

INPUTS
1A
18

STROBE
2G

.-----------+_~

28

2B

0--+---1---,

TRUTH TABLE
DIFFERENTIAL
INPUTS
A-B

2A

OUTPUT STROBE STROBE
1 V
1G
S

STAOBES

OUTPUT
y

V I O;;.25 mV

-25 mV +--l +

I

I

11Y

I

I
I
I

I
I
I

1G

S

Vcc

2G

-=

See Note 4

390

390

1

STROBE
INPUT e---------t-----~~----~

5 PF

~s.e Note 3

See Note 2

r------.----------"

INPUT~
A

100 mV

100 mV

I

I

I

~----~

I

I

I

~tp1 ~

I

STROBE
INPUT
G or S

I

I

--t

"";;",

I

3V
1.5 V

I

t-

--------0--1

I
I

I
I

I

OV

~I.~-- tp2

I

I
I
I

tpLH(D) ~

200 mV

I-- tpHUD)

I

OV

I

!c-,J,,:'""'--; fr1.-5-V----------f.~HVL~~

~ "~'

~J~------J

NOTES: 1. The pulse generators have the following characteristics:
tp2 = 1 ms, PAR = 500 kHz.

20 = 50

~

n,

tr

= tf = 10 ±5

VOL

ns, tpl = 500 ns, PRR == 1 MHz

2. Strobe input pulse is applied to Strobe 1 G when Inputs 1 A-' B are being tested, to Strobe S when Inputs lAo' B or 2A-2B
are being tested, and to Strobe 2G when inputs 2A-2B are being tested.
3. CL includes probe and jig capacitance.
4. All diodes are lN916 or equivalent.

TYPICAL APPLICATION
FIGURE 8 - MOS-TO·TTL TRANSLATOR
+5 V

1/2 MC75107 OR MC7510B

18 k

, -__________, DATA
OUT

D+-+-LJ

VIHJT~~~e
VIL

See

OUTPUTS

Table

J--.o-+---l_.J

VIH:=(see
VI L
Table

)---C>+-LJ
2BL__

_

__

GN~

.J 2Z
Arrows indicate actual direction
of current flow.

-=

TEST TABLE
TEST

INHIBITOR INPUTS
1C or 2C

D

VIH

VIH

VIL
VIL

VIH

VIH

VIL

VIH

VIH

VIH

VIH

VIH

VIH

VIH

VIH

VIL

VIL

VIL

VIH

VIH

VIH

VIH

VIL

at output

Either

Either

VIL

VIL

lY.2Y.1Z.or2Z

state

state

VIL

VIH

VIH

VIL

at output
10(on)

LOGIC INPUTS
1Aor2A
1Bor2B

1Y or 2Y

VIL

at output
1010n)
1010ff)

1Z or 22

at output
lY or 2Y
at output

1010fl)

1010ff)

12 or 2Z

FIGURE 4 -ICC and lEE

TEST TABLE

ICC lon )

TEST
Driver enabled

ALL LOGIC
INPUTS

ALL INHIBITOR
INPUTS

VIL

VIH

IEElon)
ICCloff)

Driver enabled

VIL

VIH

Driver inhibited

VIL

VIL

IEE(off)

Driver inhibited

VIL

VIL

7-487

•

MC55109, MC75109, MC55110, MC75110 (continued)

TEST CIRCUITS (continued)
FIGURE 5 - PROPAGATION DELAY TIMES TEST CIRCUIT AND WAVEFORMS

890

890

Iz

I
I

I
D

I

I TO OTHER

lJ CHANNEL

L-_.,....__

ip-. OU~UT

I

~

-G-:-Dr--

3V

LOGIC
INPUT
A or B

OV
tp

2---3V

INHI81T
INPUT
Cor 0

OV

OUTPUT
Y

on

f-------------OUTPUT
Z

I
NOTES:

off

I-----------------------on

1. The pulse generators have the following characteristics: Zo = 50 H. tr = tf == 10 ±5 ns, tpl :: 500 ns, PA R "" 1 MHz,
tp2 = 1 ms, PAR = 500 kHz.
2. CL includes probe and jig capacitance.
3. For simplicity. only one channel and the inhibitor connections are shown.

7-488

~

C")

CJ'1
01

....
0

,-.. OPEN

Each gate Is tested separately

Both gates are tested simultaneously,

(Arrows indicate actual direction of current flow. Current into a terminal is a positive value.)

FIGURE 7 - PROPAGATION DELAY TIMES. EACH GATE
+2.4 V

Vee

OUTPUT +5.0 V

RL

= 400

1N3064

I
_

NOTES:

OR EQUIV
eL

= 15 pF

(See Note BI

A. The pulse generator has the following characteristics: tw
B. CL includes probe and jig capacitance.

=- 0.5 Jjs, P RA =- 1.0 MHz, Zo

VOLTAGE WAVEFORMS

3.0 V
INPUT
~------~~~~----OV

r-----------~-~---VOH

OUTPUT

7-499

~

50

n.

MC75450 (continued)

TEST CIRCUITS (continued)
FIGURE 8 - SWITCHING TIMES, EACH TRANSISTOR
10V

-1.0 V
.....- -....INPUT
loOk

O.lI'F

50

r- I
I

t--+~-I!-""""",f\/\,--o--i----I

.....- . OUTPUT

1

CL=15pF

(Se. Note B)

I
I

L_ --1
62

NOTES:

....._ _----' SUBSTRATE

A. The pulse generator has the following characteristics: tw == O.3IJs, duty cycle

< 1 %, Zo R::: 50 n.

8. CL includes probe and jig capacitance.

VOL TAGE WAVEFORMS
I----tw------I

Ir-------:::='lI.-i----3.O V
INPUT

10%...,"'-_ __

OUTPUT

FIGURE 9 - SWITCHING TIMES, GATE AND TRANSISTOR
10V

VCC

2.4 V

.....- - + - -.. OUTPUT
INPUT

-, I

CL

= 15 pF

(See Note B)

I
I

-.J

I

NOTES:

A. The pulse generator has the following characteristics: tw
B. CL includes probe and jig capacitance.

= O.5IJ.s, PRR

= 1.0 MHz, Zo R::: 50

VOLTAGE WAVEFORMS
~5.0

';;10 ns

ns

lr-----3.O V
1.5

INPUT

V

~-----~~+----------OV

tPH

L-t::==:::;~-----~~~-4_--VOL

7-500

n.

~~___________PE_R_I_P_H_E_R_A_L_D_R_I_V_E_R____~

MC75451P

DUAL PERIPHERAL
POSITIVE "AND" DRIVER

DUAL PERIPHERAL
POSITIVE "AND" DRIVER

MONOLITHIC SILICON
INTEGRATED CIRCUITS
· .. designed for use as a general·purpose interface circuit in MDTL
and MTTL type systems. The MC75451 P is a dual peripheral positive
AND driver consisting of logic gate outputs internally connected to
the bases of two high·current, high·voltage NPN transistors. Typical
applications include relay and lamp drivers, power drivers, MOS and
memory drivers.
•

MDTL and MTTL Compatibility

•

300 mA Output Current Drive Capability
(each transistor)

p". ., .
B

o High Output Breakdown Voltage;
VCER = 30 Volts minimum
PLASTIC PACKAGE
CASE 626

CIRCUIT SCHEMATIC
(1/2 circuit shown)

r-----~__--~----------~vcc

y

A

~~--------~----~~----~--oGND

Positive Logic: Y = AB

MAXIMUM RATINGS (T A = +25 0 el
Rating

Symbol

Value

Unit

Power Supply Voltage ISee Note 11

Vee

+7.0

Vdc

Input Voltage (See Notes 1 and 2)

Vin

5.5

Vdc

Output Voltage (See Notes 1 and 31

Vo

30

Vdc

Outp~t Current (continuous)

10

300

mA

Power Dissipation (Package Limitation)
Plastic Dual In-Line Package

PD

830
6.6

mW
mw/oe

TA

o to +70

°e

T stg

-65 to +150

°e

Derate above T A = +25 0 C
Operating Temperature Range
Storage Temperature Range

NOTE 1. Voltage values are with respect to network ground terminal.
NOTE 2. I nput voltage should be zero or positive with respect to device ground terminal.
NOTE 3. This is the maximum voltage which should be applied to <[Iny output when it is in

the "off" state.
See Packaging Information Section for outline dimensions.

7-501

TRUTH TABLE
AB

Y

L ("on" state)
H l ("on" state)
H L L ("on" statel
H H H ("off" state 1

l
l

l

H = high level, L ::: low level

•

MC75451P (continued)

RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage

ELECTRICAL CHARACTERISTICS (TA = 0 to +70 0 C unless otherwise noted)
Symbol

Test Fig.

Min

Typ'

Max

Unit

High-Level I nput Voltage

VIH

1

2.0

-

-

Vdc

Low-Level Input Voltage

VIL

2

-

-

0.8

Vdc

Input Clamp Voltage
(Vec = 4.75 V, lin = -12 mAl

Vin

4

-

-

-1.5

Vdc

High-Level Output Current
(VCC = 4.75 V, VIH = 2.0 V, VOH = 30 V)

IOH

1

-

-

100

Low· Level Output Voltage
(Vce = 4.75 V, VIL = 0.8 V, IOL = 100 mAl
(Vce=4.75 V, VIL =0.8 V,IOL =300mA)

VOL

2

Characteristic

High-Level Input Current
(Vce = 5.25 V, Vin = 2.4 V)
(Vee = 5.25 V, Vin = 5.5 V)

IIH

Low· Level Input Current

IlL

/LA
Vdc

-

0.25
0.5

0.4
0.7

-

-

40
1.0

/LA
mA

-

-1.0

-1.6

mA

-

-

7.0
52

11
65

Min

Typ

Max

3

4

(Vee = 5.25 V, Vin = 0.4 V)
Supply Current

mA

5

(Vee = 5.25 V, Vin = 5.0 V)
(Vce = 5.25 V, Vin = 0)

High·Level Output
Low·Level Output

ICCH
ICCL

'TYPical values are at Vee = 5.0 V, T A = +25 0 e.

SWITCHING CHARACTERISTICS (Vec = 5.0 V, TA = +25 0 C unless otherwise noted.)
Symbol

Characteristic
Propagation Delay Time
(10"" 200 mA, CL = 15 pF, RL = 50 ohms)
Low-to·High·Level Output
High-to-Low·Level Output

Test Fig.

-

tpLH
tPHL

Transition Time
(10"" 200 mA, CL = 15 pF, RL = 50 ohms)
Low·to·High·LeveIOutput
High-to·Low-Level Output

17
18

ns

6

-

tTLH
tTHL

6.0
11

Symbols conform to JEOEe Engineering Bulletin No.1 when applicable.

TEST CIRCUITS
FIGURE 2 - VIL, VOL

FIGURE 1 - VIH, 10H

Vee

Vee
VOH

Each input is tested separately.

7-502

Unit
ns

6

-

MC75451P (continued)

TEST CIRCUITS (continued)
FIGURE 3 - IIH

4.5 V
Vee

Vee

OPEN

IlL

Vin~}
lin

I!

~

OPEN

biTsUBSTRATE

Vln~

-=-1I
-=Each input is tested-=separately.
":"

Each input is tested separately.

FIGURE 5 - ICCH. ICCl

Both gates are tested simultaneously.

FIGURE 6 - SWITCHING TIMES AND WAVEFORMS

2.4 V

Vee

10V

~

IOns

J.-'' 'O"''",---lOV

50

/'-to-t-- OUTPUT

I~~::::::::~:::::::I=O%~::~
____
Iw

J..

90%

NOTES: A. Pulse generatorcharacteristits: tw = 0.5 JiS, PAR
B. Cl includes probe and test fixture capacitance.

=

1.0 MHz,

Zo "'"

OV
VOH

~~-------~~~r----VOl

50 n.

tTHl

7-503

tTlH

•

I

\'-----~OPERATIONAL AMPLIFIERS

MCBC1709
MCB1709F

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

MONOLITHIC OPERATIONAL AMPLIFIER
Beam-lead sealed-junction technology and fabrication make the
MCBC1709 and MCB1709F devices excellent choices for military,
aerospace, and commercial applications; usages requiring a high degree
of reliability under environmental conditions of severe temperature
extremes, mechanical shock, and high humidity. Beam-lead products
employ a silicon-nitride dielectric that hermetically seals the chip,
eliminating the need for a hermetic package. The beam leads are gold
cantilevered structures extending from the chip. These beams bond
readily to a gold metalized substrate providing one of the most reliable
interconnection systems known for semiconductor devices.
•

High-Performance Open Loop Gain Characteristics
AVOL = 45,000 typical

•

Low Temperature Drift - ±3.0 JlV loe

•

Large Output Voltage Swing - ± 14 V typical @ ± 15 V Supply

•

Low Output Impedance - Zout = 150 ohms typical

MAXIMUM RATINGS ITA

MONOLITHIC SILICON

....

BEAM-LEAD CHIP
MCBC1709

= +250 C unless otherwise notedl

Rating

Symbol

Value

Unit

V+
V-

+18
-18

Vdc

±5.0

Volts

±V

Volts

Power Supply Voltage

Differential I "put Signal

Vin

Common Mode I nput Swing

CMVin

Load Current

IL

10

Output Short Circuit Duration

ts

5.0

5

Power Dissipation

PD

500

3.3

mW
mW/oC

-55 to +125

uc

Derate above T A

LE.D~

= +2SoC

Operating Temperature Range

TA

Storage Temperature Range

T stg

mA

CASE 665
CERAMIC PACKAGE

°c

-65 to +150
FIGURE 1

CIRCUIT SCHEMATIC

EQUIVALENT CIRCUIT

v' 8

OUTPUT
LAG

2.U

5

v'

Pin numbers shown are for Case 665, refer to Figure 10 for ch ip bonding diagram.
See Packaging Information Section for outline dimensions.

7-504

·1

MCBC1709, MCB1709F (continued)

ELECTRICAL CHARACTERISTICS IV+ = +15 Vdc, v- = -15 Vdc, TA = +250 C unless otherwise noted)

Characteristic

Symbol

Open Loop Voltage Gain
IVa = ± 10 V, T A = -55 0 C to +1250 C)

AVOL

Output Impedance

Min

MCBC1709 and MCB1709F
Typ

Unit

Max

25,000

45,000

70,000

-

150

-

150

400

-

±12
±10

±14
±13

-

n

Zout

If = 20 Hz)
Input Impedance

kn

Zin

If = 20 Hz)
Output Voltage Swing
IRL = 10 kn)
IRL = 2.0 kn)

Vpeak

Va

Input Common-Mode Voltage Swing

CMVin

Common-Mode Rejection Ratio

CMrej

-

70

90

-

-

0.2
0.5

0.5
1.5

-

0.05

0.2
0.5
0.2

Vpeak
dB

If = 20 Hz)
Input Bias Current

±10

±B.O

!,A

Ib

ITA = +25 0 C)
ITA = -55 0 C)

Input Offset Current

!'A

Iliol

ITA =+25 0 C)
ITA =-55 0 C)

-

ITA=+125 0 C)
Input Offset Voltage
ITA = +25 0 C)
ITA = -55 0 Cto+1250C)

-

-

-

-

1.0

-

-

-

O.B
0.3B
12

-

!,S
!,S
V/!'s

-

0.6
0.34
1.7

-

!,S
!,S
V/!'s

2.2
1.3
0.25

-

!,S
!,S
V/!'s

-

3.0
6.0

-

-

BO

165

-

25

150

-

25

150

mV

IViol
5.0
6.0

Step Response

~ Gain = 100,5.0% overshoot,
Rl = 1.0kn, R2= 100kn,
R3 = 1.5 kn, C 1 = 100 pF, C2 =
3.0 pF

~
~

Gain = 10, 10% overshoot,
Rl = 1.0kn, R2 = 10 kn,
R3= 1.5 kn,cl = 500pF,C2= 20pF
Gain = 1,5.0% overshoot,
Rl=10kn,R2=10kn,R3=
1.5 kn,cl =5000pF,C2= 200pF

(
f
f

tf
tpd
dVout/dt
tf
tpd
dVout/dt
tf
tpd
dVout/dt



6

'"

2

1\ '

\ \

\

CURVJ~

'"
«
..,.~

1\

-

\

o

I

Unity Gain

~

r'I.

Power Bandwidtfl

~ 8.0

~ .....

~ 4. 0

>
0
1.0 k

2.0 k

3.0 k

~ I~

2\

\

5.0 k

r-

10k

RL

1\

r-.

I'-...

---

\

=10 k

,i'..."
I\.

~
r-.... .... t"-

i""'-- I-

~ t- f-

t--

100 k

10M

loOM

f. FREQUENCY (Hz)

FIGURE 5 - OPEN LOOP
VOLTAGE GAIN versus FREQUENCY

FIGURE 4 - VOLTAGE GAIN
versus FREQUENCY
100

+65
+60

CURVE 1

....... r-..,

'"

;

80

R!.l

+5 0

+40

2

~

0

'

~ +30

~

........~

.i +20

;-..~

1.0 k 2.0 k 5.0 k 10 k

100

lOOk

0
100

loOM

........."
......... ~

1.0 k 2.0 k 5.0 k 10 k

FIGURE 7 - COMMON SWING
versus POWER SUPPLY VOLTAGE

100

18

a;

:g

90

w

~

$! 80
0-

:§
is

~
.l

1.0 M

lOOk

f. FREQUENCY 1Hz)

FIGURE 6 - VOLTAGE GAIN
versus POWER SUPPLY VOLTAGE

70

~ ....

4

f. FREQUENCY 1Hz)

~

~
3

0

0

~

............
~ ....

1'--....

3

+1 0

z:

2

0

$!

-5. 0

....

RLL

........

J

/

/

....-- -

~

16

~

14

~

12

~

L
./V
-CMVy

10

V/"

w

~ 8.0

~ I"";.CMV;,

~ 6. 0

8'"

/

4. 0

>~

V

".

#'"

~ 2. 0

5.0

10

15

0

20

V+ and V-. POWER SUPPLY VOLTAGE (VOLTS)

5.0

10

15

V+ and V-. POWER SUPPLY VOLTAGE IVOLTS)

7-506

20

MCBC1709, MCB1709F (continued)

TYPICAL CHARACTERISTICS (continued)
(V+ = +15 Vdc, II"" = -15 Vdc, TA = +250 C unless otherwise noted.)
FIGURE 8 - POWER DISSIPATION
versus POWER SUPPLY VOLTAGE

700
600

SAF~ OPER1TING lREA
AT REOUCEO TEMPERATURE

500
400
300

200

V

~z
c

~ I~~

/

/

BW

/

/'

100 Hj/<[\

•
~

V

1.0

I ~ '-E..,
6.0

8.0

1.0 k

100

10k

Rs. SOURCE RESISTANCE IOHMSI

'E." QUIESCENT - -V..,
QUIESCENT - 0 V

10 4.0

~~

I. 0

0

~I

V
VI

10 kHr\

0

/

/
/

=

1.0 kH'I\1\I

/

50

20

0

V

I

II
L

30

5. 0

/

/

~ 60

40

FIGURE 9 - INPUT NOISE
VOLTAGE versus SOURCE RESISTANCE

I

I

~ 80
i5
0
a:

~
~

/

/

SAFE OPERlTING tEA
AT j"Y TErERTRE
10

12

14

16

18

20

V+ and V-, POWER SUPPLY VOLTAGE (Vdc)

IS·LEAD

FIGURE 10-BONDING DIAGRAM

....L[;,;;::::===;;:;<=bb
J
=

0.0040
MAX

f

r,nput Frequency CompensatIOn
NC

t

I

V+ OutDut
Output Lag

NC
NC
NC

NC
NC
NC

NC

leadslrl,llposilipn\NilhinD.002Iolal.

Input Frequency Compensation
Silicon Thickness =2.0 mits nominal

PACKAGING AND HANDLING
The MCBC1109 beam-lead sealed-junction linear integrated circuit is available in chip form (non-encapsulated)
as shown in the outline dimensional drawing. The shipping

carrier for chips is 8 2" square glass plate on which the
chips are placed. A thin layer of polymer film covers the
plate and retains the chips in place. The chips do not adhere
to the film when it is lifted to remove them from the
carrier. Care must be exercised when removing the chips
from the carrier to ensure that the beams are not bent.
A vacuum pickup is useful for this purpose.

7-507

•

1L________

D_I_F_F_E_R_E_N_T_IA_L_C_O_M
__PA
__R_A_T_O_R~

MCBC1710
MCB1710F

Advance Inforn"lation
DIFFERENTIAL COMPARATOR
INTEGRATED CIRCUIT
MONOLITHIC SILICON

MONOLITHIC DIFFERENTIAL

VOLTAGE COMPARATOR

~

Beam-lead sealed-junction technology and fabrication make the
MCBC1710 and MCBI710F devices excellent choices for military,
aerospace, and commercial applications. These devices are designed
for use in level detection, low-level sensing, and memory applications.

•

Differential Input CharacteristicsInput Offset Voltage = 1.0 mV
Offset Voltage Drift = 3.0 IlVtC

•

Fast Response Time - 40 ns

.EAML"D~

BEAM-LEAD CHIP

• Output Compatible With All Saturating Logic Forms Vo = +3.2 V to -0.5 V Typical
•

Low Output Impedance - 200 ohms
MCBC1710

MAXIMUM RATINGS ITA = 25°C unless otherwise noted)
Rating
Power Supply Voltage

Svmbol-

Value

Unit

VCC

+14

Vdc

F SUFFIX

VEE

-7.0

Vdc

CERAMIC PACKAGE
CASE 606
(TO-91)

VIC

is.o

Volts

VICR

±7.0

Volts

Peak Load Current

IL

10

mA

Power Dissipation (package limitations)

Po
500

mW
mW/oC

Differential Input Signal
Common Mode I nput Swing

Flat Package

MCB1710F

3.3

De.rate above T A:: +2SoC
Operating Temperature Range

TA

-55 to +125

Storage Temperature Range

Tstg

-65 to +150

°c
°c

I

SCHEMATIC PIN CONNECTIONS

Chip

·Svmbols conform to JEDEC Engineering Bulletin No.1 where applicable.

CIRCUIT SCHEMATIC

EQUIVALENT CIRCUIT

Vee

A

God

This is advance information on a new introduction and specifications are sUbject to change without notice.
See Packaging Information Section for outline dimensions.

VEE

MCBC1710, MCB1710F (continued)

ELECTRICAL CHARACTERISTICS (VCC - +12 Vdc VEE -- --6 0 Vdc TA -- 25 0 C unless otherwise noted)
Symbol

Characteristic

I nput Offset Voltage
(VO = 1.4 Vdc)
Input Bias Current
(Va = 1.4 Vdc)

MCBC1710/MCBI710F
Min
Typ
Max

Unit

Via

-

1.0

2.0

mVdc

liB

-

12

20

"Adc

ro

-

200

-

Ohms

Positive 0 utput VOltage
(Vin ;;>5.0 mV, 0 <10 <5.0 rnA)

VOH

2.5

3.2

4.0

Vdc

Negative Output Voltage
(Vin ;;>-5.0 mV)

VOL

-1.0

-0.5

0

Vdc

Is

2.0

2.5

-

mAdc

CMRR

-

100

-

dB

tpd

-

40

-

ns

Power Supply Current
(Va <0 Vdcl

10+
ID-

6.4
5.5

9.0
7.0

mAdc

DC Quiescent Power Dissipation

PD

-

115

150

mW

Output Resistance

Output Sink Current
(Vin ;;>-5.0 mV, V out ;;>0)
Common Mode Rejection Ratio
(Va = -7.0 Vdc, RS <200 rl)

Propagation Oelay Time
For Positive and Negative GOing I nput Pulse

·Symbols conform to JEDEC Engineering Bulletin No.1 where applicable.
See current MC1710/1710C data sheet for additional information.

BONDING DIAGRAM

12 - BEAM CHIP
0.0004
0.0006

NC

VCC

u::£

NC

NC

J.-

NC

-t

GROUND

== o=Lb+

ffi
0.035
BSC

U.042
0.049

0.0020
0.0045

PACKAGING AND HANDLING
The MCBC1710 beam-lead sealed-junction linear integrated circuit is available in chip form (non-encapsulated) as shown in the
outline dimensional drawing. The shipping carrier for chips is a 2"
square glass plate on which the chips are placed. A thin layer of

polymer film covers the plate and retains the chips in place. The
chips do not adhere to the film when it is lifted to remove them
from the carrier. Care must be exercised when removing the chips
from the carrier to ensure that the beams are not bent. A vacuum
pickup is useful for this purpose.

7-509

MCBC1723 ~~___________V_O_L_T_A_G_E_R__EG_U__LA__TO__R_S~
MCB1723F

<---f

Advance

Inforn~atioIl.

VOLTAGE REGULATOR
INTE,GRATED CIRCUIT

MONOLITHIC VOLTAGE REGULATOR

~

The MCBC 1723/MCB 1723F is a positive or negative voltage
regulator designed to deliver load current to 150 mAdc. Output
current capability can be increased to several amperes through use of
one or more external pass transistors. Beam-lead products employ a
silicon-nitride dielectric that hermetically seals the chip. eliminating
the need for a hermetic package. The beam leads are gold cantilevered structures extending from the chip. These beams bond readily
to a gold metalized substrate providing one of the most reliable
interconnection systems known for semiconductor devices.

B"MLEAD~

• Output Voltage Adjustable from 2 Vdc to 37 Vdc
• Output Current to 150 mAdc Without External Pass
Transistors
• 0.01% Line Regulation
• Adjustable Short-Circuit Protection
MAXIMUM RATINGS

(TA

= +250 C

BEAM-LEAD
CHIP

unless otherwise noted I
Symbol *

Rating
Pulse Voltage from VCC to VEE (50 msl
Continuous Voltage from Vee to VEe

Input-Output Voltage Differential
Maximum Output Current

Value

Unit

Vin(pl

50

Vpeak
Vde

Vin

40

Vin-VO

40

Vde

'L

150

mAde

Current from Vref

Iref

15

mAde

Operating Temperature Range

TA

-55 to +125

Junction Temperature Range

TJ

-65 to +150

°c
°c

·Symbols conform to JEDEC Engineering Bulletin No.1 where applicable.

FIGURE 2 - CIRCUIT SCHEMATIC

FIGURE 1 - TYPICAL CIRCUIT CONNECTION

Vee

r---'---~--'-T-~r--~---,_t-___K-+

Vc

v,.

~---.:...oCOMPENSATION

VO~7elR+/2)

Ise.

V~I~sen~~tTJ -250[;

For best results 10 k-

::>

'"

~

n

(VOLTAGE FOLLOWER)

8.Of--+-

IIIII ~H 0 <

4.:

1,11111

1111i+-----+--+--+++tH1t----!\-1
\r++HtH

~

~ +60

~

~ +40
'">
~ +2 0
>

-20
1.0

10

100

1.0 k

100 k

10 M

100

.......

'"
S

80

>

i

60

C;;

'"
'"
'"z
'"

24r-----r--+~~~~++----

6.

~ 20~----t-~--+-~r++++-----~--t_~~4-~~

'"
«

~ 16~----t-~~~t-~jj±=====j:==±::t:t±=ttH

'"'"
w

~ 12 r-----t---;l'-+--H
!;
8.0 r----,r~--+--H

'"
8'"

>

100

'"

1.0 M

FIGURE 6 - COMMON-MODE REJECTION
RATIO versus FREQUENCY
~

5.0 k

10k

!

"'
....... r-,

40

20
100

10

1.0 k

10 k

100 k

1.0M

f, FREQUENCY (Hz)

RL, LOAD RESISTANCE (OHMS)

FIGURE B -INPUT BIAS CURRENT
versus TEMPERATURE

FIGURE 7 - INPUT OFFSET CURRENT
versus TEMPERATURE
90

+10

~
'"
G

80

----

~ +5.0

'">~

....-V

'"

~

N

::::; -5.0

'"'"

10 k

~

f, FREQUENCY (Hz)

FIGURE 5 - OUTPUT VOLTAGE SWING
versus LOAD RESISTANCE

«
~

~

«

I, FREUUENCY (Hz)

>-

~

'"
«

100 k

10 k

1.0 k

~

+8 0

'"
;;:

1111

100

10

+10 0
;;;

I .....

-10
-55

/

-

I-"

+2,5

+50

+75

>-

70

~

'"G

60

~
a;
>-

50

~

40

~

-'""'"

"'- ..........

""'-

r---

r-..,

E

SLOPE CAN BE EITHER POLARITY

-25

~

30

+100

+125

TA, AMBIENT TEMPERATURE (DC)

20
-55

-25

+25

+50

r-- r--+75

TA, AMBIENT TEMPERATURE (DC)

7-514

+100

+125

MCBC1741, MCB1741F (continued)

TYPICAL CHARACTERISTICS (continued)
(V+ = +15 Vdc, V- = -15 Vdc, TA = +25 0 C unless otherwise noted.)
FIGURE 9 - POWER DISSIPATION versus
POWER SUPPLY VOLTAGE

FIGURE 10 - OUTPUT NOISE versus SOURCE RESISTANCE

I 1-'1nil'ITnII
rfl
L~.~ Rl R2
1.2 1--+--+--+-t-+1++I---+--+-+--bI'Ht+ --RS - R3i R1 + R2

100

1.4 ,---,-.--r-rTTTTl--'---'-'-""'r.AcV- ;l-;;;OO;;CO"'"

.......,..

70
50

/"

40

./

30

Vout=O- -

r-'"'" 0.8 r-~

.§

V

20

/

10

V

....~
::>

0.6

0

7.0
5.0
4. 0
3. 0
2.0

C
> 0.4

I--I--I---

IIl

---

~ 1.0
:>

AV =

R2 t--+-t-tT1"rn

R1

AV

rP

Rl

+

I II II
=1001

Vn

R3

I IIIII
~-+-++H1I++F===!=1=Fi+++++-_HAV
= 10

I I
I IIIIII
1--+-+-+-t+l-Ht-+-t-+tt+tt+-t-l-Li"'f.Wv
=1
I- J:H..t.+

/
6.0

10

14

18

22

0.2
O. 1
100

V+ and V-, POWER SUPPLY VOLTAGE (VOLTS)

1.0 k

10k

RS, SOU RCE RESISTANCE (OHMS)

FIGURE II-BONDING DIAGRAM

Silicon Thickness = 2.0 mils nominal

PACKAGING AND HANDLING
The MCBC1741 beam-lead sealed-junction linear integrated circuit is available in chip form (non-encapsulated)

as shown in the outline dimensional drawing. The shipping

carrier for chips is a 2" square glass plate on which the
chips are placed. A thin layer of polymer film covers the
plate and retains the chips in place. The chips do not adhere

to the film when it is lifted to remove them from the
carrier. Care must be exercised when removing the chips
from the carrier to ensure that the beams are not bent.
A vacuum pickup is useful for this purpose.

7-515

lOOk

~f

'"

MCBC1748
MCB1748F

OPERATIONAL AMPLIFIERS

'---------------'

Advance Inforxnation

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

HIGH PERFORMANCE MONOLITHIC
OPERATIONAL AMPLIFIER

~

Beam-lead sealed-junction technology and fabrication make the MCBC1748
and MCB1748F devices excellent choices for use as a summing amplifier,
integrator, or amplifier with operating characteristics as a function of the
external feedback components_ Beam-lead products employ a silicon-nitride
dielectric that hermetically seals the chip, eliminating the need for a hermetic
package_ The beam leads are gold cantilevered structures extending from the
chip_ These beams bond readily to a gold metalized substrate providing one of
the most reliable interconnection systems known for semiconductor devices_
• Noncompensated MCBC1741
• Single 30 pF Capacitor Compensation Required For Unity Gain
• Short-Circuit Protection
• Offset Voltage Null Capability
• Wide Common-Mode and Differential Voltage Ranges
• Low-Power Consumption
• No Latch Up
MAXIMUM RATINGS

ITA

BEAM-LEAD CHIP

= +25 0 C unless otherwise notedl

Rating
Power Supply Voltage

Differential Input Signal

CD

MCBC1748

Symbol

Value

Unit

v+
v-

+18
-18

Vdc

±5_0

Volts

±v

Volts

Vin

Common Mode I "put Swing

B"ML.AD~

CMVin

CASE 606
ITO-911

rnA

Load Current

IL

10

Output Short Circuit Duration

ts

5.0

s

Power Dissipation

Po

500

3.3

rnW
rnW/oC

Operating Temperature Range

TA

-55 to +125

uC

Storage Temperature Range

T 5Ig

Derate above TA = +250 C (Flat Package)

F SUFFIX
CERAMIC PACKAGE

MCB174BF

SCHEMATIC PIN CONNECTIONS

°c

-65 to +150

CD For supply voltages less than ± 15 V. the Maximum I nput Voltage

I~~~~

Package

I ~ I~I; I~ I~ I~ I~ I~ I

is equal to the Supply Voltage.

FIGURE 2 - OFFSET ADJUST AND
FREQUENCY COMPENSATION

FIGURE 1 - CIRCUIT SCHEMATIC

•

15
OUTPUT

OFFSET E
NUll

50

OFFSET NULL
A.ND
1.0t
vCOMPENSATION
L-~--~~---+----~-4--~----~----------~-OD

This I. advance information on a new introduction and specifications are subject to change without notice.
See Packaging Information Section for outline dimensions.

7-516

MCBC1748 r MCB1748F(continued)

ELECTRICAL CHARACTERISTICS (v+ = +15 Vde, V- = -15 Vde TA = +250 C unless otherwise noted)
Unit

Symbol

Min

Typ

Max

AVOL

50,000

200,000

-

-

Output Impedance ( f = 20 Hz)

Zo

-

75

-

ohms

Common Mode I nput Impedance (f = 20 Hz)

lin

-

200

-

Megohms

Output Voltage Swing (R L - 10 k ohms)
RL = 2 k ohms (T A = -55 to +1250 C)

Va

±12
±10

±14
±13

-

Vpk

CMVin

-

±13

-

Vpk

CMrej

-

90

-

dB

Ib

0.08

0.5

/lAde

Characteristics
Open-Loop Voltage Gain, (Va = +10 V, RL =2.0·kohms)

Cornman-Mode Input Voltage Swing
Common-Mode Rejection Ratio (f - 100 Hz)

I nput Offset Current

lio

-

0.02

0.2

/lAde

Input Offset Voltage (RS ';;10 kn)

Vio

-

1.0

5.0

mVde

tr

-

-

ISC

-

25

-

/lS
%

dVout/dt

0.3
5.0
0.8

mAde

Rp
Cp

-

2.0
1.4

-

Megohms

I nput Bias Current

Step Response (Vin - 20 mV, Ce - 30 pF,
RL =2kn,cL = 100pF)
Rise Time
Overshoot Percentage

Slew Rate
Short-Circuit Output Current

V//ls

Differential I nput Impedance (Open·Loop, f - 20 Hz)
Parallel I nput Resistance

Parallel Input Capacitance

-

-

pF
/lV/V

Power Supply Sensitivity
V- = oonstant, RS';; 10k ohms
V+ = oonstant, RS';;lO k ohms
Power Supply Current
DC Quiescent Power Dissipation

S+
S-

-

30
30

150
150

ID+
ID-

-

1.67
1.67

2.83
2.83

mAde

-

PD

-

50

85

mW

(Vo=O)

16-BEAM CHIP

BONDING DIAGRAM

Nitride
Lip

Offset Null
NC

!
I

NC

0.052

0.059

NC
NC

Offset Null andCompensalion
Silicon Thickness = 2.0 mils nominal

Silicon Thickness = 2.0 mils normal

PACKAGING AND HANDLING
The MCBC174B beam-lead sealed-junction linear integrated
circuit is available in chip form (non-encapsulated) as shown in the
outline dimensional drawing. The shipping carrier for chips is a 2"
square glass plate on which the chips are placed. A thin layer of

7-517

polymer film covers the plate and retains the chips in place. The
chips do not adhere to the film when it is lifted to remove them
from the carrier. Care must be exercised when removing the chips
from the carrier to ensure that the beams are not bent. A vacuum
pickup is useful for this purpose.

•

I

L---...-f

~___________O_P_ER_A_T__IO_N_A_l_A__M_P_l_IF_I_E_R_S~

MCC1536
MCC1436

HIGH VOLTAGE, INTERNALLY COMPENSATED
MONOLITHIC OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

· .. designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components.
The MCC1536 and MCC1436 employ phosphorsilicate passivation
that protects the entire die surface area, including metalization interconnects. All dice have a minimum gold-backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.
• Maximum Supply Voltage - ±40 Vdc
• Output Voltage Swing ±30 Vpk(minl(V+ = +36 V, V- = -36 VI
±22 Vpk(minl(V+ = +28 V, V- = -28 VI
• Input Bias Current - 20 nA max
• Input Offset Current - 3.0 nA max. Offset Voltage Null Capability
• Fast Slew Rate - 2.0 VIlls typ
• Input Over-Voltage Protection
• Internally Compensated
• AVOL - 500,000 typ
• Characteristics Independent of Power Supply Voltages (±5.0 Vdc to ±36 Vdc)

EPITAXIAL PASSIVATED

6

4

(Substrate)
3
2

MCC1536iMCC1436

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Power Supply Voltage

Svmbol

MCC1536

MCC1436

Unit

V+

+40

+34

Vdc

V-

-40

-34

Differential I nput Signal 11)

Vin

±IV+ + IV-I-3)

Volts

Common-Mode I nput Swing

CMVin

+v+. -IIV-I-3)

Volts

TSC

5.0

s

TA

-55 to +125
o to +75

°c

T stg

-65 to +150

°c

Output Short Circuit Duration (V - Iv-I- 28 Vdc. Vo

!operating Temperature Range

= 0)
MCC1536
MCC1436

Junction Temperature Range
(llThe absolute voltage applied to either input terminal must not exceed +V+, -(

Iv - 1-3).

CIRCUIT SCHEMATIC

EQUIVALENT CIRCUIT
v'

7

INVERTING

lin

'-t----~6 OUTPUT

v,
NON

INVERTING

1

5
10k

..J

L'f:FSET

___ -1

4 V(SUBSTRATE)

7-518

ADJUST

MCC1536, MCC1436 (continued)
ELECTRICAL CHARACTERISTICS IV+ = +28 Vdc, V- =-28 Vdc, T A = +25 0 C unless otherwise noted I
MCC1436

MCC1536
Characteristics

Svmbol

Min

Typ

Max

Min

TVp

Max

Input Bias Current

Unit
nAde

8,0

20

15

40

1.0

3.0

5.0

10

2.0

5.0

5.0

10

Input Offset Current

nAde

Input Offset Voltage

mVdc

Differential Input Impedance IOpen·Loop. f S'5.0 Hz)

Parallel Input Resistance

10

10

Parallel Input Capacitance

2.0

2.0

pF

250

250

Megohms

±-25

±25

110

110

Common-Mode Input Impedance If S' 5.0 Hz)

Zfinl

Common-Mode Input Voltage Swing
Common-Mode Rejection Ratio (dc)

CMrej

Large Signal de Open Loop Voltage Gain

AVOL

(V o '" ±. 10 V. RL " 100 k ohms)

Power Ban,dwidth lVoltage Follower)

Megohms

d9

v/V
100,000 500,000

70,000 500.000

200,000

200.000

P9W

(AV = 1, AL;: 5.0 k ohms, THO$' 5%, Vo '" 40 Vp-pl
. Unity Gain Crossover Frequency (open-loop)
Phase Margin (open-loop, unity gain)

-

Gain Margin
Slew Rate (Unity Gain)

23

23

1.0

1.0

ivlHz

50

50

degrees

18

-

2.0

dVout/dt

18

d9

2.0

V/lls

Output Impedance (f S' 5.0 Hz)

Zout

1.0

1.0

k ohms

Short-Circuit Output Current

ISC

±.17

±17

mAde

Output VOltage Swing (RL '" 5.0 k ohms)
V+ ;; +28 Vdc, V- ;; -28 Vdc

±22
±30

V+ = +36 Vdc, V- ;; -36 Vdc

±23
±32

±20

±22

Power Supply Sensitivity (dc)

IlVIV

V- = constant, Rs -S 10 k ohms

S+

V+= constant, Rs S'10 k ohms

S-

Power Supply Current

15

100

15

100

35
35

200
200

2.2
2.2

4.0

2.6

5.0

4.0

2.6

5.0

124

224

146

280

DC Quiescent Power Dissipation

mAde

mW

See current MC1536/1436 data sheet for additional information.

MCC1536/MCC1436 BONDING DIAGRAM

5

98

PACKAGING AND HANDLING
The MCC1536/MCC1436 operational amplifier is now available
in die (chip) form. The phosphorsilicate passivation protects the
metalization and active area of the die but care must be excercised
when removing the dice from the shipping carrier to avoid scratching the bonding pads. A vacuum pickup is useful for the handling
of dice. Tweezers are not recommended for this purpose.
The non-spill type shipping carrier consists of a compartmentalized tray and fitted cover. Die are placed in the carrier
with geometry side up.

4

3

1--1--

69

---l~1

All dimensions are nominal and
in mils (10-3 inches).
Die Dimensions
Thickness = 8.0
Bonding Pads = 4.0 x 4.0

7-519

I

I

l-._____

O_P_E_R_A_T_I_O_N_A_L_A_M_PL_I_F_IE_R_S-----'

MCC1539
MCC1439

MONOLITHIC OPERATIONAL AMPLIFIER CHIP
OPERATIONAL AMPLIFIER CHIP
INTEGRATED CIRCUIT

... designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components. For detailed information see Motorola Application
Note AN-439.

MONOLITHIC SI LICON

The MCC1539 and MCC143gemploy phosphorsilicate passivation
that protects the entire die surface area,. including metalization inter·
connects. All dice have a minimum gold-backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.
•

Low Input Offset Voltage - 3.0 mV max

•

Low Input Offset Current - 60 nA max

•

Large Power-Bandwidth - 20 Vp-p Output Swing at 20 kHz min

• Output Short-Circuit Protection
•

Input Over-Voltage Protection

•

Class AB Output for Excellent Linearity

• Slew Rate - 34 V Ills typ

MAXIMUM RATINGS (TA

=

+25 0 C unless otherwise noted)
Symbol

Rating

Differential Input Signal

Curr~nt

OutputShort Circuit Duration

Value

Unit

+18
-18

Vdc
Vdc

IJ

±IV++ Iv

Vi"

Common Mode I "put Swing
Load

I

V+
V-

Power Supply Voltage

Vdc

CMVin

+V+, -Iv-I

Vdc

IL

15

mA

All dimensions are nominal and
in mils (10-3 inches).
Die Dimensions
Thickness = 8.0
Bonding Pads = 4.0 x 4.0

Continuous

ts

Operating Temperature Range MCCI539
MCCI439

TA

-55 to +125
o to +75

°c

Junction Temperature Range

TJ

-65to+150

°c

FIGURE I-CIRCUIT SCHEMATIC

FIGURE 2 -EQUIVALENT CIRCUIT

lO------4r-~-----~--.-----------~------_.

v'

v'

r-"VV"v- -,
I

,I
'7'
I

INPUT LAG
8o------~-+---,
INVERTING INPUT
40

lo-'WI'-'---1"""
Ik

26k
Ik
Jo-~~~~---4-----"
NON INVERTING INPUT

40
NON
INVERTING

v-

v-

SUBSTRATE 4o-_ _ _ _ _ _....._ _....._ _ _ _ _ _ _ _ _

,

+---1~-+-O OUTPUT

~--_+-...J

7-520

4

MCC1539, MCC1439 (continued)
ELECTRICAL CHARACTERISTICS IV+ = +15 Vdc. V- = -15 Vdc. T A = +250 C unless otherwise noted 1
MCC1439

MCC1539
Symbol

Characteristic
Input Bias Current

Min

Ib

I nput Offset Current

Iliol

Input Offset Voltage

..

IViol

Average Temperature Coefficient of Input
Offset Voltage

nput Common-Mode Voltage Swing
Common Mode Rejection Ratio

Ma.

Min

Typ

Ma.

0.20

0.50

-

0.20

1.0

MA

20

60

20

100

nA

1.0

3.0

2.0

7.5

-.

3.0

..

..

3.0

..

300
±12

-

-

300
±12

-

CMrej

..

110

-

AVOL

50.000

Zin
CMVin

Unit

mV
MV/oC

ITCViol

IRS=50nl
Input Impedance

Typ

..

110

k<>
Vpk
dB

If = 1.0 kHzl
Open Loop Voltage Gain

120.000

..

15.000

100.000

-

..

50

..

..

IV o = ± 10 V. RL = 10 knl
Power Bandwidth (Av -1, THD ~ 5%,

PBW

IV o = 20 Vp·P. RL = 1.0 knl

kHz

-

50

Step Response
Gain::: 1000, no overshoot,

tf

-

130

..

..

130

-

ns

tpd

-

190

..

-

190

..

ns

..

6.0

..

..

6.0

..

V/MS

tf

..

80

-

-

80

..

ns

tpd

..

100

..

..

100

dVout/dt

..

14

..

14

..
..

V/MS

ns

dVout/dt
Gain = 1000, 15% overshoot.

Gain = 100, no overshoot,

tf

..

60

tpd

..

100

_.
..
..

34

..

dVout/dt
Gain::: 10, 15% overshoot,

Gain = 1, 15% overshoot,

..

-

ns

..

34

-

VIMS

ns

.-

120

..

..

120

..

..

80

..

-

80

..

tf

6.25

-

-

dVout/dt

Output Impedance
(f = 20 Hzl

Zout

Output Voltage Swing

V out

_.

6.25

160

-

ns
VIMS

-

160

..

ns

-

80

ns
VIMS

kn

4.2

..

..

4.2

-

4.0

-

..

4.0

-

80

Vpk

..

±10

±13

±13

..

..

..

..
-

50

150

~

50

200

"VIV

-

50

150

50

200

"VIV

10+

-

3.0

5.0

..

3.0

6.7

mAdc

10-

..

3.0

5.0

..

3.0

6.7

90

150

-

90

200

..

IRL = 2.0 kil. f = 1.0 kHzl
(RL = 1.0 kn. f = 1.0 kHzl

±10

Positive Supply Sensitivity
(V- constant)

S+

Negative Supply Sensitivity
(V+ constant)

S

Power Supply Current

DC Quiescent Power Dissipation

60
100

If

tpd

(V o = 01

..
..

tpd
dVout/dt

ns

~

Po

-

IV o = 01
See current MC1539/1439 data sheet for additional information.

PACKAGING AND HANDLING
The MCCl539iMCCl439 operational amplifier is now available
as a single monolithic die or encapsulated in the TO·99 and TO·116

hermetic and plastic packages. The phosphorsilicate passivation
protects the metalization and active area of the die but care must
be exercised when removing the dice from the shipping carrier to
avoid scratching the bonding pads. A vacuum pickup is useful for
handling of dice. Tweezers are not recommended for this purpose.
The non-spill type shipping carrier consists of a compartmentalized tray and fitted cover. Die are placed in the carrier
with geometry side up.

7-521

mW

•

\~_ _ _ _O_P_E_R_A_T_I_O_N_A_L_A_M_P_Ll_F_1E_R_S~

<------J

MCC1558
MCC1458

(DUAL MC1741)

DUAL
OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

DUAL MC1741
INTERNALLY COMPENSATED, HIGH PERFORMANCE
MONOLITHIC OPERATIONAL AMPLIFIER

MONOLITHIC SILICON

· .. designed for use as a summing amplifier, integrator, or amplifier
with operating characteristics as a function of the external feedback
components.
The MCC1558 and MCC1458 employ phosphorsilicate passivation
that protects the entire die surface area, including metalization interconnects. All dice have a minimum gold-backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.
•

No Frequency Compensation Required

•

Short-Circuit Protection

•

Wide Common-Mode and Differential Voltage Ranges

•

Low-Power Consumption

•

No Latch Up

2

14 12

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating
Power Supply Voltage

Symbol

MCC1558

V+

+22

+18

-22

-18

V-

Differential Input Signal
Common-Mode I nput Swing
Output Short Circuit Duration

Operating Temperature Range

MCC1558
MCC1458

Junction Temperature Range

MCC1458

Unit
Vdc

Vin

.±30

Volts

CMVin

±.15

Volts

ts

Continuous

TA

-55 to +125
o to +75

°c

TJ

-65 to +150

°c

FIGURE 1 - CIRCUIT SCHEMATIC

FIGURE 2 - OFFSET ADJUST

r-~----------~--~------------~-----------'--oV+
14

15
OUTPUT

21121

V-70----+

50
11

vTheletterswithoul parenthesis represent the pin numbers for 112 oft hedualcin:uit,
letters in parenthesis represent the pin numbers for the other half.

7-522

MCC1558, MCC1458 (continued)

ELECTRICAL CHARACTERISTICS (v+ = +15 Vdc, V- = -15 Vdc, TA = +25 0 C unless otherwise noted)
MCC1558
Characteristic

MCC145B

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Ib

-

0.2

0.5

0.2

0.5

I'Adc

0.03

0.2

I'Adc

2.0

6.0

mVdc

I nput Offset Current

II·

I

-

0.03

0.2

-

Input Offset Voltage
(RS ~ 10 k ohms)

IViol

-

1.0

5.0

-

Parallel I nput Resistance

Rp

-

1.0

-

1.0

-

Megohm

(:p

-

6.0

-

-

Parallel Input Capacitance

-

6.0

-

pF

200

-

-

200

-

Megohms
Vpk

I nput Bias Current

Differential Input Impedance
(Open·Loop, f = 20 Hz)

Common-Mode Input Voltage Swing

CMVin

-

±13

-

-

CM r..

-

90

-

-

±13

Common-Mode Rejection Ratio (f = 100 Hz)

90

-

dB

Open-Loop Voltage Gain
(V o =±10V, RL =2.0 k ohms)

AVOL

50,000

200,000

-

20,000

100,000

-

V!V

PBW

-

14

-

-

14

-

kHz

-

1.1

-

-

1.1

-

MHz

65

-

65

-

degrees

VII'S

75

-

ohms

Common-Mode Input Impedance (f = 20 Hz)

Power Bandwidth
(AV = 1, RL = 2.0 k ohms, THO ~ 5%,
Vo = 20 Vp.p)

Z(jn)

Unity Gain Crossover Frequency (open-loop)

Phase Margin (open-loop, unity gain)

-

11

-

-

11

dVout/dt

-

0.8

-

-

0.8

20

-

mAde

-

Vpk

Gain Margin

Slew Rate (Unity Gain)

Zout

-

75

-

Short-Circuit Output Current

ISC

-

20

Output Voltage Swing
(RL = 10 k ohms)

Vo

±12

±14

-

±12

±14

S+

30

150

-

30

150

30

150

-

30

150

10+

-

2.3

5.0

-

2.3

5.6

10

-

2.3

5.0

-

2.3

5.6

'-

70

150

-

70

170

Output Impedance (f = 20 Hz)

Power Supply Sensitivity
V- = constant, Rs ~ 10k ohms
V+ = constant, Rs ~ 10k ohms
Power Supply Current

DC Quiescent Power Dissipation

dB

p.V!V
S-

-

Po

mAde

mW

(V o =0)
See current MC1558/MC1458 data sheet for additional information.

PACKAGING AND HANDLING

MCC1558/MCC1458 BONDING DIAGRAM

The MCC1558/MCC1458 dual operational amplifiers are now
available as a single monolithic die or encapsulated in a variety of
hermetic and plastic packages. The phosphorsilicate passivation
protects the metalization and active area of the die but care must
be exercised when removing the dice from the shipping carrier to
avoid scratching the bonding pads. A vacuum pickup is useful for
the handling of dice. Tweezers are not recommended for this
purpose.
The non-spill type shipping carrier consists of a compartmentalized tray and fitted cover. Die are placed in the carrier
with geometry side up.

All dimensions are nominal and

in mils (10-3 inches).
Die Dimensions
Thickness = 8.0
Bonding Pads = 4.0 x 4.0

7-523

I

I

\~_ _N_E_G_A_T_IV_E_V_O_L_T_A_G_E_R_E_G_U_L_A_T_O_R_S-----,
MCC1563
MCC1463

MONOLITHIC NEGATIVE VOLTAGE REGULATOR

NEGATIVE-POWER-SUPPL Y
VOLTAGE REGULATOR

The MCC1563/MCC1463 is a "three terminal" negative regulator
designed to deliver continuous load current up to 500 mAdc and
provide a maximum negative input voltage of -40 Vdc. Output current capability can be increased to greater than 10 Adc through use
of one or more external transistors.
The MCC1563 and MCC1463 employ phosphorsilicate passivation
that protects the entire die surface area, including metalization interconnects. Ali dice have a minimum gold-backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.
•

Electronic "Shutdown" and Short-Circuit Protection

•

Low Output Impedance - 20 Milliohms typ

•

Excelient Temperature Stability - TCV o = ±0.002%/oC typ

•

High Ripple Rejection - 0.002% typ

•

500 mA Current Capability

FIGURE 1 - TYPICAL CIRCUIT CONNECTION

1-3.5\'5 Vo 51-37IVdc, 151 L5 500 mA

MONOLITHIC SILICON
INTEGRATED CIRCUIT

,

(Substrate)

FIGURE 2 - TYPICAL NPN CURRENT BOOST CONNECTION

(Va = -5.2 Vdc, I L = 10 Adc [maxi I

GN,

~~----------~--~--~------~--~-t

S.ak
10

6.a~

RB

R,
IL=

v'"
RA

C,
10

Co

ILl

100

RL

MCC146J

MCC146J

v,

I
I
I

I

Vo =-5.2 Vdc

FIGURE 3 - CIRCUIT SCHEMATIC

-ShUt-OOW-;'Co-;;-t~il

2

III

v,
Zo"'S.Omiliiohms

I

10Amax

"

MCC1S63

"

MCC1563

1-- -

__ GND

:-- - - - - -OCStiiitOUiPu't- - - ,
DC Shift Sense 1
9
3 Noise Filter I

I

Unity Gain Regulator

10~---+1-~~~~4C----~r-~~~1----r+1~~~r-~~------~

Ground

510

Zl

1.5k

920

I
I

I
I

I

Output

I
I
I
I

~t--------o

8
Sense

I
I

I
I

I(Substrate)

60 k

-+__ ______

14~~______

L __ ..Yin _______ J

~

~~-7

____~____~__4 -__~__~~__~~~~~

7-524

MCC1563, MCC1463 (continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted)
Rating

Symbol

MCC1563

Vin

-40

Input Voltage
Peak Load Current

Current, Pin 2

I

MCC1463

Unit

-35

Vdc

IL pk

600

mA

Ipin 2

10

mA

TA

-55 to +125
to +75

°c

TJ

-65 to +175

°c

MCC1563
MCC1463

Operating Temperature Range

I

Junction Temperature Range

o

ELECTRICAL CHARACTERISTICS ilL = 100 mAde, TA = +25 0 C unless otherwise noted)
MCC1463

MCC1563
Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Input Voltage

Vi"

-

-

-40

-

-35

Vdc

Output Voltage Range

Vo

-3.6

-

-37

-3.8

-

-32

Vdc

Reference Voltage IPin 1 to Ground)

Vref

-3.4

-3.5

-3.6

-3.2

-3.5

-3.8

Vdc

IVin - Vol

-

1.5

2.7

-

1.5

3.0

Vdc

Bias Current
ilL = 1.0 mAde, Ib = lin -ILl

Ib

-

7.0

11

-

7.0

14

mAde

Output Noise
IC n =O.l !IF,f= 10Hzt05.0 MHz)

vn

-

120

-

-

120

-

!lV(rms)

±0.002

-

-

±0.002

0.002

-

-

0.003

-

%/v o

0.4

-

-

0.7

-

mV

-

35

-

milliohms

15

-

14

50

Characteristic

Minimum Input-Output Voltage Differential
IRSC = 0)

Temperature Coefficient of Output Voltage

TCVo

Input Regulation

Regin

Load Regulation

RegL

-

%/oC

IT J = Constant [1.0 mA:::: I L-== 20 mAl)
Output Impedance If = 1.0 kHz)

Zo

-

20

Shutdown Current

Isd

-

7.0

!lAde

IVin = -35 Vdcl
See current MC1563/1463 data sheet for additional information

MCC1563/MCC1463 BONDING DIAGRAM

PACKAGING AND HANDLING

(Substrate) "

5

4

3

The MCC1563/MCC1463 voltage regulator is now available as

2

1
75

a single monolithic die or encapsulated in the Case 602A and Case
614 hermetic packages. The phosphorsilicate paSSivation protects
the metalization and active area of the die but care must be exercised when removing the dice from the shipping carrier to avoid
scratching the bonding pads. A vacuum pickup is useful for the
handling of dice. Tweezers are not recommended for this purpose.
The non-spill type shipping carrier consists of a compartmentalized tray and fitted cover. Die are placed in the carrier

with geometry side up.

1~'-------68------~
All dimensions are nominal and

in mils (10-3 inches).
Die Dimensions
Thickness = 8.0

Bonding Pads = 4.0 x 4.0

7-525

I

\

_____
PO_S_I_T_IV_E_V_O_L_T_A_G_E_R_E_G_U_L_A_T_O_R_S---'

MCC1569
MCC1469

POSITIVE VOLTAGE REGULATOR
INTEGRATED CIRCUIT

MONOLITHIC VOLTAGE REGULATOR
The MCC1569 and MCC1469 are positive voltage regulators de·
signed to deliver continuous load current up to 500 mAdc. Output
voltage is adjustable from 2.5 Vdc to 37 Vdc. Systems requiring
both a positive and negative regulated voltage can use the MCC1569
and MCC1563 as complementary regulators with a common input
ground.
The MCC 1569 and MCC 1469 employ phosphorsilicate passivation
that protects the entire die surface area, including metalization inter·
connects. All dice have a minimum gold·backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.
•
•
•
•
•

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

Electronic "Shut·Down" Control
Excellent Load Regulation (Low Output Impedance - 20 milli·
ohms typ)
High Power Capability: Up to 17.5 Watts
Excellent Temperature Stability: ±0.002%/oC typ
High Ripple Rejection: 0.002%/V typ

FIGURE 1 - CIRCUIT SCHEMATIC

CONTROL

Yin

C>1----+......- - -.....--'-----~~.....----I_--~~-~

1 OUTPUT

60k

COMPENSATIDN AND
CURRENT LIMIT

..H~--o

.

5 OUTPUT SENSE

~-l-~---==:::t====::g 68

::::

1 -Ho~-;:"
SHUTDOWN 0CONTROL

5.0k
10

GND ~~~-~-T~---~~---~---~----~----~
SUBSTRATE

7-526

DC SHIFT OUTPUT
NOISE FILTER

OUTPUT REFERENCE
DCSHIFTSENSE

MCC1569, MCC1469 (continued)

MAXIMUM RATINGS ITA = +250 C unless otherwise notedl

I

Symbol

MCC1569

Input Voltage

Vin

40

Peak Load Current

Ipk

600

mA

Current, Pin 2

loin 2

10

mA

Current, Pin 9

Ipin 9

5.0

TA

-55 to +125
o to +75

°c

TJ

-65 to+150

°c

Rating

MCC1569
MCC1469

Operating Temperature Range
Junction Temperature Range

MCC1469

Unit

35

Vde

I

ELECTRICAL CHARACTERISTICS ITA = +25 0 C unless otherwise noted I
MCC1469

MCC1569
Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Input Voltage

Vin

-

-

40

-

-

35

Vde

Output Voltage Range

Vo

2.5

-

37

2.5

-

32

Vde

Vref

3.4

3.5

3.6

3.2

3.5

3.8

Vdc

Vin - Va

-

2.1

2.7

-

2.1

3.0

Vdc

Bias Current
ilL = 1.0 mAde, R2 =6.8 k ohms, Ib = lin -ILl

Ib

-

4.0

9.0

-

5.0

12

mAde

Output Noise

vn

-

0.150

-

-

0.150

-

mVlrmsl

±0.002

-

-

±0.002

-

-

0.003

%/Vin

-

35

milliohms

-

140

Characteristic

Reference Voltage (Pin 8 to Ground)
Minimum Input-Output Voltage Differential

ICn =O.l/lF, f= 10Hz to 5.0 MHzl
Temperature Coefficient of Output Voltage

TCV o

I nput Regulation

Regin

-

0.002

Output Impedance

Zout

-

20

Isd

""'

70

%loC

ICc = O.OOl/lF, RSC = 1.0 ohm, f = 1.0 kHz,
Vin = +14 Vdc, Vo = +10 Vdcl
Shutdown Current

IVin = +35 Vdcl

150

500

/lAde

See current MC1569/1469 data sheet for additional information.

PACKAGING AND HANDLING

MCC1569/MCC1469 BONDING DIAGRAM

~
66

Die Center)

The MCC1569/MCC1469 voltage regulator is now available as
a single monolithic die or encapsulated in the Case 602A and Case
614 hermetic packages. The phosphorsilicate passivation protects
the metalizatian and active area of the die but care must be exercised when removing the dice from the shipping carrier to avoid
scratching the bonding pads. A vacuum pickup is useful for the
handling of dice. Tweezers are not recommended for this purpose.
The non-spill type .shipping carrier consists of a compartmentalized tray and fitted cover. Die are placed in the carrier
with geometry side up.

All dimensions are nominal and
in mils 11 0-3 inchesl.
Die Dimensions
Thickness = 8.0
Bonding Pads = 4.0 x 4.0

7-527

I

~~____________________M_U_L_T_IP_L_I_E_R_S~
MCC1595
MCC1495

LINEAR FOUR-QUADRANT
MULTIPLIER INTEGRATED
CIRCUIT

MONOLITHIC FOUR-QUADRANT MULTIPLIER
· .. designed for uses where the output voltage is a linear product of
two input voltage!;. Typical applications include: multiply, divide',
square root', mean square', phase detector, frequency doubler,
balanced modulator/demodulator, electronic gain control.
The MCC1595 and MCC1495 employ phosphorsilicate passivation
that protects the entire die surface area, including metalization interconnects. All dice have a minimum gold-backed thickness of 4000
Angstroms. The interconnecting metalization and bonding pads are
of evaporated aluminum.

MONOLITHIC SILICON
EPITAXIAL PASSIVATED

·When used with an operational amplifier.

•

Excellent linearity - 0.5% typ Erroron X-Input, 1% typ Error on
V-Input - MCC1595

• Excellent linearity - 1% typ Error on X-Input, 2% typ Error on
V-Input - MCC1495
•

Adjustable Scale Factor, K

•

Excellent Temperature Stability

• Wide Input Voltage Range - ± 10 Volts
MCC1595/MCC1495 Die

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Applied Voltage

IV2-VI, VI4-VI, VI-V9, VI-VI2, VI-V4,
VI-Va, V12-V7, V9-V7' va-v7' V4-V71
Differential Input Signal
Maximum Bias Current
Operating Temperature Range

MCC1595
MCC1495

Junction Temperature Range

I

Symbol
6V

Value

Unit

30

Vdc

VI2 Vg
V4-Va
13
113

+16+113 RXI
±16+13 Ryl
10
10

Vdc
Vdc

TA

°c

-65 to +150

°c

o

TJ

mA

-55 to +125
to +70

CIRCUIT SCHEMATIC

r-+===:;:=1===:I;-~) 142

IKXYI

X Input

Ylnput

12

+--~----<> II

L--~---+-------o10

r--+-+--+-------0 13

v-

Output

7~--------~~--~--~

____________ __ __
~

ISUBSTRATEI

7--528

~

~

MCC1595, MCC1495 (continued)
ELECTRICAL CHARACTERISTICS IV+

=+32 V.

V- = -15 V. TA

= 25°C. 13 = '13 = 1 rnA. RX = Ry 0'15 kn.

R L '" 11 kG unless otherwise noted)
Characteristic

Symbol

Min

Ty.

Max

Unit

Linearity:

Output Error in Percent of Full Scale:
-10-O-3-+evo

Vo 2. Zout.:.eRA+RB 1O-4n
RA

~.H~~~~~~~~~I~~IVo

3. Zin""RA

~
-=-

4.lsc""ZOOmA

-15Vdc O.lpf

See Packaging Information Section for outline dimensions.

7-548

- Vin) 102..0.001%
Vin
2. Zout"" ur4n, f <20 Hz
3. lin ~ 30 Megohms, f <20 Hz
4.lsc ... 200mAdc

MCH2870MR, MCH2870CR (continued)
MAXIMUM RATINGS (TC = +25 0 C unless otherwise noted)
Symbol

Rating

MCH2870MRI MCH2870CR

Unit

I

Vdc

V
V-

Power Supply Voltage

Vi"

±30

Volts

±15

Volts

ts

Continuous

Po
1/0JA
°JA
Po
liOJC

2.4
16
62

Watts
mW/oC
°C/W

9.0
60
16.7

mW/oC
°C/W

Output Short Circuit Duration

Power Dissipation and Thermal Characteristics
TA = +25 0 C
Derate above T A = +250 C
Thermal Resistance, Junction to Air

TC = +250 C
Derate above T C = +2SoC
Thermal Resistance. Junction to Case

°JC

Operating Temperature Range

-55 to +125

TA

ELECTRICAL CHARACTERISTICS (V+

MCH2870MR
Input Bias Current
TC = +250 C
TC = Tlow to Thigh (See Note 1)

Symbol

I"put Offset Current
TC = +250 C
T C = Tlow to Thigh

Iliol

I nput Offset Voltage (RS ,; 10 k!:J.l
TC = +25 0 C
TC = Tlow to Thigh

IViol

Min

Typ

Parallel I nput Resistance
Parallel Input Capacitance

Common-Mode Input Voltage Swing
Equivalent Input Noise Voltage

0.5
1.5

-

-

0.2

0.5
0.8

-

0.03

0.2
0.5

-

0.03

0.2
0.3

-

1.0

5.0
6.0

-

2.0

-

-

0.3

1.0
6.0

-

-

1.0
6.0

lin

-

200

CMVin

±12

±13

OC Open· Loop Voltage Gain, (V out =± 10V, RL = 300 ohms)
TC = +250 C
TC = Tlow to Thigh

AVOL

PBW

90

.-

Phase Margin (closed loop. unity gain)
Gain Margin (closed loop. unity gain)

dVout/dt
Zout

-

-

-

6.0
7.5

-

-

200

-

±12

±13

-

-

200,000

-

12
1.1
65
11

-

-

-

-

-

-

45

-

70

90

-

20,000 100,000
15,000

dB

-

-

12

-

1.1

-

MHz

-

65

-

degrees

-

kHz

-

11

-

dB

0.8

-

V/~s

-

10

-

ohms

65

100
200
00-300

140

t.12

-

-

'-

10

-

100
200
10()..300

125

-

-

±12
±10

±13

-

±11
±10

-

30
30

150
150

-

7.7
7,7

-

225

-

-

V out

Po

Vpk

-

0.8

75

10

pF
Megohms

mAdc

Rl=R2=oo

10+

Megohm

V/V

ISC

Pins 2 and 4 shorted
Adjustable Range

Vin = 0

45

-

Unity Gain Crossover Frequency (open-loop)

DC Quiescent Povwr Dissipation

70
50,000
25,000

AV = I, RL = 300 ohms, THO$ 5%, V out = 20 Vp-p

Power Supply Current

-

nV/(Hz)lS

en

S+
S-

Unit

mVdc

0,3

CMrej

Power Supply Sensitivity (de)
V- = constant, RsS 10 k ohms
V+ = constant, Rs510 k ohms

Max

-

-

AV = 100, Rs = 10 kohms, 1= 1.0kHz, BW = 1.0 Hz

Output Voltage Swing
RL = 300 ohms
RL = 300 ohm (TC = Tlow to Thigh)

Typ

0.2

-

Common· Mode Rejection Ratio (I = 100 Hz)

Power Bandwidth

Min

J.l.Adc

Rp
Cp

= 20 Hz)

MCH2870CR
Max

-

Oillerentiallnput Impedance (Open' Loop, I = 20 Hz)

Short-Circuit Output Current (See Figure 6)

°c

-

-

Output Impedance (open loop 1= 20 Hz)

°c

~Adc

Ib

Slew Rate (Unity Gain)

o to +75

= +15 Vdc, V- = -15 Vdc, TC = +25 0 C unless otherwise noted)

Characteristics

Common-Mode Input Impedance (f

I

Watts

-65 to +175

TJ, T stg

Operating and Storage Junction Temperature Range

+18
-18

CMVin

Differential Input Signal
Common·Mode Input Swing

+22
-22

-

Note 1: TJow: aOc for MCH287aCR
_55 0 C for MCH2870MR
+75 0 C for MCH287QCR
+125 0 C for MCH287QMR

7-549

-

-

-

-

-

-

-

~V/V

-

30

30

200
200

13
13

-

7.7
7.7

16.5
16.5

390

-

225

500

-

Vpk

mAdc
mW

MCH2870MR, MCH2870CR (continued)

FIGURE 5 - MCH2870M/C DEVICE CONFIGURATION

I
I

J_____ :R:'T :S:R

BLOCK DIAGRAM

OPERATIONAL A:": __ 51 v~

MCH2870MfC

--,
I

POSITIVE
CURRENT
LIMIT
ADJUST

(MC1538/1438 CHIP)

(MCl741/C CHIP)

OP·AMPL
OUTPUT

-- -- ~A~bv-- i --

L
OFFSET NUll

_ _ _ _ _ _ _ _ _ -.1

NEGATIVE
CURRENT
LIMIT
ADJUST

I

COMPLETE SCHEMATIC DIAGRAM

5 v+ I

I

300
POSITIVE
CURRENT
LIMIT
ADJUST

NON·

,
INPUT

OUTPUT

3

INVERTING

7

50

INPUT

NEGATIVE
CURRENT
LIMIT
ADJUST

6

OFFSET NUll

1k

50k

5k

50k

50

300

CASE

v-

SIMPLIFIED FUNCT ONAl SCHEMATIC

5

V.

I

OUTPUT

CASE

DlFF.INPUT AMPL.
AND OIFF.-TO·
SINGLE-ENDED

CONVERTER

COMMON EMITTER
2NO STAGE
WITH INTERNAL FREn.

vDp·AMPL.
OUTPUT
STAGE

COMPLEMENTARY

COMMON·COLLECTOR
POWER AMPl.

(ClASSAB)

COMPENSATION CAP.

Ic,l

7-550

MCH2870MR, MCH2870CR (continued)

TYPICAL CHARACTERISTICS
(v+ = +15 Vdc, V- = -15 Vdc, TA = +25 0 C unless otherwise noted)
FIGURE 6 - SHORT·CIRCUIT CURRENT versus
Rl OR R2 (100 mA TO 300 mAl

FIGURE 7 - DC SAFE OPERATING AREA
500
400
300
_ 250
~ 200
150

400
."

~

.s...

4
&R
l
70-- 1-)
2
R2

300

\

~

r\

'":::>
:: 200
~

...

,c

'"
c

6

...ffi

1

r--

100

'"'"
13

9

I'...

:::>

~

80-- 1+)

.s

3

CASE

70
50

c

~

I

:::;

100

20

Rl Limits 1+
R2littSI-

+-

MtH28170M

o

o

MCH2870C

==

10
10

30

20

50

40

1.0

5.0

2.0

10

20

30

40 50

Rl OR R210HMS)

FIGURE 8 - POWER BANDWIDTH
(LARGE SIGNAL SWING versus FREQUENCY)

FIGURE 9 - OPEN LOOP FREQUENCY RESPONSE
+120

28

+100

24

~

~ 20

~+80

1\

to


:::>

>

~

iii

-

o
10

IVOLTAGE FOLLOWER)
±15 VOLT SUPPLIES

111111
100

~

to

"~ +40

~

.~

c

>

~+20

1\

I I111 JHO <1 5%1 I I II

4.0

TC = +25 0 C

"

11111
1.0 k

~

>

10 k

-20
1.0

100 k

100

10

10 k

1.0 k

100 k

Hl

I

~~--~~H+~--~~4-~HI+II~I-

~B

AV =

A

IR

I I 1111

400

RAR8
S=~

360

IV+= 15V, V-=-15V)

320

I I III
AV

10 M

FIGURE 11 - INPUT BIAS CURRENT versus TEMPERATURE

FIGURE 10 - OUTPUT NOISE versus SOURCE RESISTANCE
AV - 1000 I

'"

1.0 M

t, FREQUENCY 1Hz)

t, FREQUENCY 1Hz)

~ 280

1001

~

240

r-...

:::>

~ 200



/

!;
~

:::>

>

0

>=

0

a:

~

1C

V

4.0

V

/

TC - +250 C

~

/

/

==

!--

-

300
200

;t
~ 100

L

/

B.O

0

g

Iz

ISC= 300mA-

/

1);

..'"

1000
700
500

/'

24

70
50
30
20

20

40

80

60

10
4.0

100

6.0

8.0

10

12

14

16

18

20

22

24

v+ and V-, POWER SUPPLY VOLTAGE (VOLTS)

RL, LOAO RESISTANCE (Ohms)

TYPICAL APPLICATIONS
FIGURE 15 - CONSTANT CURRENT SOURCE
OR TRANSCONDUCTANCE AMPLIFIER

FIGURE 14 - PROGRAMMABLE VOLTAGE SOURCE

v+

V+

RS

CHARACTERISTICS

>--0____.. Voul
CHARACTERISTICS

FOR OPTIMUM LINEARITY

Vout = Vin
Zout «1.0 MILLIOHM

RB=RC"

(f~20

RA

Hz)

RO

L--+-----~-"""--1IIL
RL =

V-

FIGURE 17 - WIEN BRIDGE OSCILLATOR

FIGURE 16 - POWER SUPPLY SPLITTER

FREn
AOJUST
fa = 1.0 kHz

>--<>-t.. Zout
CHARACTERISTICS

30 Rs
v-=--

fa =_1_
27TR oCo
FROM 0.01 Hz
TO 10 kHz

RA + RS

v-~--~----~-------------e

ISC = 100 rnA

7-552

MCH2870MR, MCH2870CR (continued)

TYPICAL APPLICATIONS (continued)

FIGURE 18 - EXTERNAL CURRENT BOOSTING

.... +15 Vd<:

r-----..---~

2N3767
(MJE205)

OR EQUIV

-15 Vdc
lin

~

for

100 MEGOHMS

RB

RA " 100

AV~~
RA

Zoul < 1 MILLIOHM

I

7-553

I

MCH2890R ~~____________D_U_A_L_P_O_W__E_R_D_R_I_V_E_R~

DUAL POWER DRIVER
HYBRID DUAL POWER DRIVER

HYBRID SILICON
INTEGRATED CIRCUIT

The MCH2890 Dual Power Driver is capable of driving a wide
variety of inductive and resistive loads; included are hammer
solenoids in high·speed digital printers, relays, lamps, paper·tape
punches, and stepper motors in computer·operated plotters.

•

High Current - to 6.0 Amperes

•

High Breakdown Voltage - BVCEX

•

MTTL Compatibility

= 120 Volts min

• Separate Integrated Circuit and Darlington Power Grounds
bottom view

•

Low V sat at 3.0 and 6.0 Amperes

•

Low Leakage Current - 0.1 /lA typ

CASE 685
METAL PACKAGE

MAXIMUM RATINGS (T A = +25°C unless otherwise noted)
Rating
Collector CUffent

Symbol

Continuous

Collector Emitter Breakdown Voltage

Ie ~O.5

rnA

Power Supply Voltage (I ntegrated Circuit)

Unit

A
8.0
1.0

Peak

Minimum at

Value

IC

120

Vdc

VCCl

7.0

Vdc

PD

3.75
25
40
25
167
6.0

mWfC
°C/W
Watts
mW/oC
°C/W

BVCEX
1, 51

(pins

Power Dissipation and Thermal Characteristics

TA = 25°C
Derate above T A "'" 25°C
Thermal Resistance. Junction to Air

TC = 25°C
Derate above T C :: 25°C
Thermal Resistance, Junction to Case

1/0JA

o JA
PD
JC
o JC

110

Watts

Operating Temperature Range

TA

o to +70

°c

Storage Temperature Range

T stg

-55 to +175

°c

Gnd

Gnd

See Packaging Information Section for outline dimensions.

7-554

3

s(')

ELECTRICAL CHARACTERISTICS
Test procedures are shown for only one power driver. The other power driver
is tested in the same manner.

::J:

I\)

00
to

o

t5.0Vdc

:D

ByvccI

8::J
....

:i"
c:::
C1l

c..

'
10

=PRe
MellOI

I

I

I
I

God

'

Gnd!3

TEST CURRENT/VOL TAGE VALUES
AMPERES

VOLTS

mA

-..J

0,

aOe

01
01

+2SoC
+7SoC

VAH
4.0
4.0
4.0
TEST CURRENT/VOLTAGE APPLIED TO PINS LISTED BELOW:

Pin
Under

Characteristics

Symbol

Input Forward Current

'F

Input Leakage Current

'A

Input Breakdown Voltage
Input Clamp Voltage

Test

6.

BVin

Output Voltage
(See Figure 1)

VOLl
VOL2
BVCEX

Output Leakage Current

'CEX

Output Power Supply Drain Current

IpDL

Output Power Supply Drain Current

Switching Parameters (See Figure 2)
Turn-On Delay Time
Turn-Off Delay Time

~.

IPDH

5.6

2,3,4

}lAde

2,3,4.7

1.8

•

'0

lin

IOl2

IClmax)

V,"

V'H

VF

VR

Vee1

VCC2

VCCIL

VRH

VCCIH

2.3.4.7
2.3,4

1.5
2.5

Vdc

-t0.26

IOL1

Vdc

30
120

tpd+

mAde

Vdo

-l-

5,6

-2.0

-1.5

0.1

'pd-

Unit

5015-51-1501-150

Vo

GND

Max

5

-

I

I

6

I -

I - I - I

-

I

-

I

I

7

2.3.4
2,3,4
2,3,4

}lAde

1

-

6

-

1

mAde

1

-

1

1

1

1 -

1

-I

7

-

1

1 -

1

2,3,4
2,3,4,6,

7.9.10
mAde

I

-

1

1

PU~~ 1 PU~~ 1
In

"'
"'

Out

-

1

-I

- 1- 1

-I

-

8

1

-

1

16;7';- I

2.3.4

1
2,3,4
2,3.4

I

MCH2890R

(continued)

TEST CIRCUITS
FIGURE 2 - PROPAGATION DELAY
TIME TEST CIRCUIT

FIGURE 1 - VOL TEST CIRCUIT
t15V

"

CARBON RESISTOR LOAD
ADJUST FOR 3.0A Dr6.DA.

TYPICAL CHARACTERISTICS
FIGURE 3 - COLLECTOR-EMITTER VDL TAGE

FIGURE 4 - COLLECTOR-EMITTER VOLTAGE

versus NEGATIVE EMITTER VOLTAGE

~

0

~
w

versus POSITIVE EMITTER VOLTAGE

12
ID

'"<

!:; 8.0
0
>

'"w

l-

I-

~
'"

~
8

~

>

6.0
4.0
2.0
0
0

3.0
VI. NEGATIVE EMITTER VOLTAGE (VOLTS)

VI. POSITIVE EMITTER VOLTAGE (VOLTS)

SAFE OPERATING AREA
FIGURE 5 - COLLECTOR-EMITTER VOLTAGE
versus COLLECTOR CURRENT

FIGURE 6 - COLLECTOR-EMITTER VOLTAGE
versus COLLECTOR CURRENT

0

ID

g

"0

r- 0

1.0

~1:l

"-

'"
0

~

PIN=10~s

II II

10

~

- : DJi-°ym;YCLE

3

5% DUTY CYCLE

"

1.0

o
100

1.0

VCE ' COLLECTOR·EMITTER VOLTAGE (VOLTS)

10
VCE ' COLLECTOR-EMITTER VOLTAGE (VOLTS)

7-556

100

MCH2890R (continued)

SAFE OPERATING AREA (Continued)
FIGURE 7 - COLLECTOR-EMITTER VOLTAGE

versus COLLECTOR CURRENT
10

!!:
I-

~

'"
a
'"

1.0

0

~

8
_u

1"\
PW-25ms
5% DUTY CYCLE

100

10

1.0

VCE_ COLLECTOR·EMITTER VOLTAGE (VOLTS)

APPLICATIONS INFORMATION
levels required of hammer drivers. When the Darlington power
drivers are switched "off", even a small inductance at the
Darlington ground generates a negative voltage spike which tends
to turn the Darlington power driver "on" rather than "off". This
negative excursion of the emitter can result in oscillations. The
oscillation can be stopped by tieing the integrated circuit ground
(pin 3) to the Darlington ground (pins 2 and 4) with as short a line
as possible. (See Figure 8). This circuit configuration pulls the
gate output lower when the negative spike is present on the power
ground line which guarantees "turn off" of the Darlington power
driver.
To insure that the Darlington power driver does not go into
secondary breakdown and latch up, a diode clamp is employed as
shown. For high-speed printers, the addition of a zener diode can
aid in dissipating the stored inductive power (during "turn off") in
the hammer solenoid.
Additional features of the MCH2890 indude fast switching and
low leakage for minimum standby power.

The MCH2890 is designed for high-current and high-voltage

applications such as hammer-drivers in high-speed printers, relay
drivers, lamp drivers. paper tape punches, stepping motors, and
other high current inductive and resistive loads.
This dual hybrid driver, which consists of a monolithic MTTl
"AND" gate and two power Darlington drivers, is capable of
supplying up to 6.0 amperes at a maximum duty cycle of 10%
with pulse widths up to 25 ms. In addition to the high-current drive

capability the MCH2890 offers high collector-ta-emitter breakdown (BVCEX "" 120 Volts min) which is desirable when dr.iving
inductive loads at high currents.
A typical high~peed hammer driver application is illustrated in
Figure 8. The number of drivers per printer is large, and
considerable electrical noise is generated when they are switched
simultaneously. The ground line, which terminates all of the
Darlington power drivers, may be several feet in length resulting in
substantial inductance and series resistance. The effect of this
inductance and resistance becomes appreciable at the high·current

FIGURE 8 - TYPICAL HAMMER DRIVER APPLICATION
VCC

8

--<>+I

DATA IN ...
INHIBIT

_....,7~HIL

.r"

I

L - - ---t-.J
3

INTEGRATED CIRCUIT GNDI

.....

I

1

- %MCH1890 I
-~
I
JX>-t-O-.....
--''Y'IrY''---'I/'>/V-....._

,-

t=:::===:1

The Darlington power driver ground should be conne:ed 10 Ihe
integrated circuit ground with a short line.

HAMMER

4

~

7-557

+80 V

RL
(CURRENT LIMITING RESISTOR)

Ground to other Darlington power drivers.

•

s-----f

'\

AUDIO AMPLIFIER

MFC4000B '--""--_ _ _ _ _ _

----l

1/4-WATT AUDIO AMPLIFIER
SILICON MONOLITHIC
FUNCTIONAL CIRCUIT

1/4-WATT AUDIO AMPLIFIER

· .. designed for the output stage of battery-powered portable radios.

•

250 mW of Audio Output Power

•

Low Standby Current - 3.5 mA typical

•

Low Harmonic Distortion

•

Reduces Component Count in Portable Radios by Two
Transformers and Two Transistors

•

Eliminates Costly Component Matching Requirements
PLASTIC PACKAGE
CASE 206A

TYPICAL APPLICATION

RF
STAGE

MIXER
OSCILLATOR

MFC4000B

IF
STAGE

AUOIO
AMPLIFIER

AGC

MAXIMUM RATINGS (TA = 25 0 C unless otherwise noted)
Unit

Svmbol

Value

Power SupplV Voltage

V+

12

Vdc

Power Dissipation (Package Limitation)
(Soldered on a circuit board and held in free air)

Po

1.0

Wan

10

mW/oC

TA

-10 to +75

DC

Rating

Derate above T A

= 25°C

Operating Temperature Range

See Packaging Information Section for outline dimensions.

7-558

MFC4000B (continued)

ELECTRICAL CHARACTERISTICS* (V+

= 9.0 Vdc,

RL

= 16 Ohms, T A = 25°C unless otherwise noted)

Symbol

Min

Typ

Max

Unit

Zero Signal Current Drain

ID

-

3.5

6.0

mAde

Sensitivity

ein

-

-

15

mVlrms)

Pout

250

350

-

mWlrms)

-

0.7

-

Characteristic

Pout

= 50 mWlrms)

Output Power
Total Harmonic Distortion

~

10%

THD

Total Harmonic Distortion

= 50 mWlrms)
Pout = 50 mWlrms),

%

Pout

V+

= 6.0 Vde

4.5

• As measured in test circuit shown in Figure 1.

FIGURE 1 - TEST CIRCUIT

v+

r-----------

3

---------,
MFC4000B

3.9 k

360
5.0 k

4

5.0!,F

2
1.0 k

+

I

I

I

AUDIO

ase

I
I
L _________ _

_ _ _ _ _ _ _ _ .JI

16
ohms

10 k

7-559

I

MFC4000B (continued)

TOTAL HARMONIC DISTORTION versus OUTPUT POWER

v+ =9.0 Vdc

FIGURE 2 10

10

>fl.

II

>fl.

Z

z·

o

>= 8.0

~ B.O

I;;

o
I;;

a:
o

~

v+ = 6.0 Vdc

FIGURE 3 -

6.0

~ 6.0

I

Z

o
a:

'" 4.0

Z

o

~

~

~

II

~

"

\I

4.0

.....

"

o

o

..... 2.0
o

.... 2.0
0"

I--"

:>:

....

V

~

i=

a
20

10

30

50
100
200 300
Pout, OUTPUT POWE R, mW(rms)

500

3.0

1000

5.0

10

20
30
50
100
Pout, OUTPUT POWER, mW(rms)

200 300

FIGURE 5 - TOTAL HARMONIC DISTORTION
versus SUPPLY VOLTAGE

FIGURE 4 - CURRENT DRAIN versus OUTPUT POWER
100

10

80

z·
~ 8.0

«

I;;

V

60

~ 6.0

./

Z
o

/'

40

'"

~ 4.0

:>:

13
E

\
\

a:
o

E

'"
~
....
~
a:

\

20

~
10

20

"

---

~

2.0

0"

:>:
....

30

50

100

200

300

500

1000

~~
I
100~F

-

~

-

a

=

Pout =10 mW
R~ =16 D1hms

a

I

1\

\

\

~

",-

~

I

8.0

4.0
6.0
Vl,SUPPlYVOlTAGE. Vdc

2.0

Pout, OUTPUT POWER, mWlrms)

FIGURE 6 - TYPICAL CIRCUIT APPLICATION

r----------l r -

--------l
V+

56 k

I
II
I I
II
33 k

10 k

+

I

15

II
II
II

1.0 k

+
100l'F

I

L _________ .1
PREAMPLIFIER

I

~L

__

POWER AMPLIFIER
I
_________________

~

~

7-560

10

'\

MFC4010A

HIGH FREQUENCY CIRCUIT

"-----------'

WIDE-BAND AMPLIFIER

WIDE-BAND AMPLIFIER

Silicon Monolithic
Functional Circuit
· .. designed for FM/I F and low-level audio applications.
•

High Audio Gain - 60 dB minimum

•

Useful as a Microphone Amplifier and in Tape Recorders and
Cassettes

•

Excellent Performance as a 10.7 MHz FM/IF Amplifier

o High Transconductance (gm) Ideally Suited to Low Impedance
Ceramic Filters

~~

PLASTIC PACKAGE
CASE 206A

V

~

TYPICAL APPLICATIONS
FIGURE 1 - FM/IF AMPLIFIER
V+=12Vdc

INPUT
10.7 MHz

50 OHMS

20 pF

-----11---..-----.

3.0 k
0.01 pF

O.OlpF

OUTPUT
10.7 MHz

L1~I---O--l

20 pF

I

13 k

390

1.8 k

L1 - 5.4 pH
36 Turns, #30 AWG Wire Wound on 1/4" Slug Tuned
Form, Tapped 8 Turns from Ground End.

Slug: T,H. Material 1/4" [)ja., 1/2" Length

FIGURE 2 - RECORD/PLAY PREAMPLIFIER FOR CASSETTE AND PORTABLE TAPE RECORDERS

560k

loOk
INPUT ....-"NI.-~-'-I~-?-o--l

>-<>-+-_
27'

I.Ok

.
50pf

.

l'

~PLAY

RECORO~

See Packaging Information Section for outline dimensions.

7-561

XO.I~F

7.5k

OUTPUT

330

MFC4010A (continued)

MAXIMUM RATINGS (T A = 25°C unless otherwise noted)

Rating

Symbol

Value

Power Supply Voltage

V+

18

Vdc

Power Dissipation @ T A = 25°C
(Package Limitation)
Derate above 25°C

PD

0.5

Watt

5.0

mW/oC

Operating Temperature Range

TA

-10 to +75

°c

ELECTRICAL CHARACTERISTICS (V+

= 6.0

Vdc, T A

Characteristic
Open Loop Voltage Gain (Figure 3)

If

= 25°C unless otherwise

Unit

noted)

Symbol

Min

Typ

Max

Unit

AVOL

60

68

-

dB

hl1

-

1.0

-

k ohms

h12

-

10-6

-

-

h21

-

1000

-

-

h22

-

10-5

-

mhos

enlout!

-

3.0

-

mVlrms)

ID

-

3.0

-

mA

= 1.0 kHz)

h Parameters 11 )
If = 1.0 kHz)

Output Noise Voltage IFigure 3)
IBW = 20 Hz to 20 kHz, RS = 1.0 k ohms)

Current Drain

HIGH FREQUENCY CHARACTERISTICS IV+

= 12 Vdc, f = 10.7 MHz, T A = 25 0 C unless otherwise noted)

Power Gain (Figure 1)
lein = 0.1 mVrms)

-

-

42

-

dB

Noise Figure (Figure 1)
IRS",740 Ohms)

NF

-

6.0

-

dB

y Parameters( 1)

Yl1

-

1.3+ jl.5

-

mmhos

Y12

-

-3.4 + j8.1

-

J,lmhos

Y21

-

-0.33 + jO.68

-

mhos

Y22

-

120 + jO

-

J,Lmhos

If

= 10.7 MHz, 12 = 2.0 mAl

(1) Device only, without external passive components.

FIGURE 3 -AUDIO TEST CIRCUIT

FIGURE 4 - BIASING RECOMMENDATIONS

v+

V+

6.0Vdc

o.I,u F

l

I--~-­

I

I

I

I

I

1.5k

I
I
I
4

--------l
1.8 k

I

B.n

MFC4010A

1.5k

I
~--v'v2°~~1~2~-~t__e
~---4--_{
I
O.'"F
I
100

I

L _____________

~lo/51

RI

I

L-_ _ _ _ _ _ _ _ _ _ _....

Ein' 0.74 V

I
I

Select:

R2

I
~

1.0 k

50 pF

7-562

33k

Solve for:
let:
Then:

V+, Eo, and 10
10/5
RL' IV+ - Eoilio
R2' 510.741/10
RI ' R2 lEo - 0.74110.74

1

MFC4010A (continued)

TAPE PREAMPLIFIER PERFORMANCE

AUDIO PERFORMANCE CHARACTERISTICS

(for Circuit Figure 2)

(for Test Circuit Figure 3)
FIGURE 5 - VOLTAGE GAIN versus FREOUENCY

FIGURE 7 - RECORD VOLTAGE GAIN versus FREOUENCY

0

+30

0

:E +25

a;
a;

:s
z

;;:

to
W

z

;;:
0

to

U.J

:---

to

'I'-,

0

oS

<[

o

Bl
N

0

>

::>
<[

:::;

1\

0

+10

V

<[

~ +5.0

o

V

z

::>

0

<[

20

10

40 100

400 loOk 4.0k 10k

-5.0
0.02

40kl00k 400k1.0M 4.0MlOM

0.05

0.3

0.1

f. FREQUENCY (Hz)

FIGURE 6 -VOLTAGE GAIN versus POWER SUPPLY

to

~
o

0

5.0

10

20

a;

:E +2 0

/

z

;;:

/

to

w

+1 5

V

1,\

to
<[

II

S

f = 1.0 kHz

0

+1 0

>
'" +5. 0
):!j

>

V+ =6.0 V
AV 500 Hz =35.6 dB

1\

<[

~

0

0

~
~-5. 0

0
4.0

B.O

12

16

r-----

1\

:::;

::>

<[

3.0

+2 5

0

W

to

1.0

F)GURE 8 - PLAYBACK VOLTAGE GAIN versus FREQUENCY

~

;;:

0.5

f. FREQUENCY (kHz)

0

;z

/

V+=6.0V
AV 500 Hz = 30 dB

+1 5

>

to

S

+20

<[

............

-I 0

20

0.02

V+.SUPPLY VOLTAGE (VOLTS)

0.05

0.1

0.3

0.5

1.0

3.0 5.0

10

20

f. FREQUENCY (kHz)

Note:
The record/playback characteristics shown in Figures 8 and 9
were taken with the preamplifier driven by a 50 ohm source. The
curves are typical of a desired response for the preamplifier; however, every type of tape recording and playback head is different
and this circuit will not necessarily satisfy all requirements. No par-

ticular tape head was used as a basis for circuit design. The circuit
is only an example showing the equalization network configuration.
The ideal preamplifier will have an input impedance approximately 10 times the highest impedance of the tape head and every
preamplifier circuit must be designed using a test tape to verify

the response of the design.

7-563

•

MFC4010A (continued)

10.7 MHz V PARAMETERS
FIGURE 10 - REVERSE TRANSFER ADMITTANCE

FIGURE 9-INPUT ADMITTANCE

"1i
~

.sw
'"'
~

3.5

~

3.0

!

1.5

"

1.0

>-

0.5

8.0

:E
o

6.0

«

2.0

'"w
""

~

bll

f-

~

b12

~
z

~

2.5

:E
~

10

00

~ I""'"

~

"ji12

4.0

f-

gIl

w

f-""

00

ffi

2.0

Ii;

'"

o
0.1

0.2

0.5

1.0

5.0

2.0

10

E

0
0.1

0.2

0.3

"1i
0.8

./

0.6

0.4

~

~
~

E

V

0.2

0~
0.1

5.0

10

'z"'
~

:E
co
«

"ji21

1/

f-

~ 100

......

~z
:

10

f-

~

f-

:::>

80

g22

\.
\.

0

A

0 ........

\.

co

~

./ 1--1-'"'"
0.2

0.3

0.5

1.0

2.0

,..-

.....-

120

~

b211

:E

~

5.0

FIGURE 12-0UTPUT ADMITTANCE

w

~

3.0

140

1.0

:[
~

2.0

12. PIN 2 CURRENT (rnA)

FIGURE ll-FORWARDTRANSFERADMITTANCE

"1i

1.0

0.5

12.PIN 2CURRENT (rnA)

3.0

5.0

10

~

20

0.1

'E

0.2

12.PIN 2 CURRENT (rnA)

1.0

0.5

2.0

12. PIN 2 CURRENT (rnA)

10.7 MHz PERFORMANCE
(Circuit of Figure 1)
F(GURE 13 -POWER GAIN versus SUPPLY VOLTAGE

FIGURE 14 - VOLTAGE TRANSFER CHARACTERISTIC

80

40 0

70

20 0

!.s

60

!z

«to

'"
;;:
'"
co
a.

ein = 0.1 mVrms

50

w

10 0
0
0-

to

«

40

':;
co
>

"

30

10

f-

6. 0
4. 0

~

co
~

10
0
4.0

f-

:::>

20

20

-

2. 0
6.0

8.0

10

12

14

16

18

1.0
0.01

20

V·. SUPPLY VOLTAGE (VOLIS)

0.03

0.1

0.3

1.0

3.0

10

30

ein.INPUTVOLTAGE (mVrms)

7-564

100

300 1000

~__________S_IN_G__LE__T_O_G_G_L_E_F_L_I_P-_F_L_O_P~

MFC4040

SINGLE TOGGLE FLIP-FLOP

SINGLE TOGGLE
FLIP-FLOP

• Wide Operating Voltage Range - 4.0 to 16 Volts
•

Regulated Supply Not Required

•

Compatible with TTL and OTL

•

Economical 4·Lead Plastic Package

Single Monolithic
Functional Circuit

MAXIMUM RATINGS
Symbol

Value

Volts

Power Supply Voltage

Vee

19

Vdc

Output Sinking Current

'sink

10

mA

Negative I nput Voltage

Vin

0.5

Vdc

PD
1/0JA

1.0
10

mW/oe

TA

-10to+75

°e

Rating

Power Dissipation @ T A :::; 2SoC
Derate above 2SoC

Operating Temperature Range

Watt

TYPICAL APPLICATION
470 pF
CASE 206A
PLASTIC

a 1--4-.() fout = 113 fin
4.7k
INPUT O--'W".-.....--iT
MFC4040

MFC4040

Divide·by·3 Circuit

FIGURE 1 - CIRCUIT SCHEMATIC

BLOCK DIAGRAM

a

Vee" Pin 2
GNO = Pin 1
GNO

See Packaging Information Section for outline dimensions.

7-565

•

MFC4040 (continued)

ELECTRICAL CHARACTERISTICS (Vee = 12 Vdc. Vin = 4.0 Vp-p Square Pulse. f = 10 kHz. 50% Duty Cycle. tf= 1.0 VII's (Min).
T A = 250 e unless otherwise noted)

Unit

Symbol

Min

Typ

Max

Operating Power Supply Voltage

Vee

4.0

-

16

Vdc

Toggle Frequency

fTog

-

3.0

-

MHz

Output Voltage (High)
(Vee = 4.0 Vdc)

VOH

3.5

-

-

15.5

-

-

-

0.5

Characteristic

Vdc

(Vee = 16 Vdc)
Output Voltage (Low)
(Vee = 4.0 Vdc)

Vdc

VOL

-

-

Operating Drain Current

ID

-

-

32

mAdc

Output Sinking Current
(Va'; 1.0 Vdc)

'sink

-

2.0

-

mAdc

(Vee = 16 Vdc)

1.0

Rise Time

tr

-

250

-

ns

Storage Time

ts

-

350

-

ns

Fall Time

tf

-

60

-

ns

Rin

10

-

-

kn

ROH

-

-

2.8

kn

I nput Resistance
Output Resistance (Output High)

INPUT PULSE REQUIREMENTS

VH

JEADING
EDGE

TRAILING
EDGE

Characteristic

Symbol

Min

Max

Unit

Pulse Magnitude

VH

+4.0

-

Volts

Zero Level

VL

-

+1.0

Volts

No Requirement

Leading Edge

VL •
0

dv

-

Trailing Edge

t

-1.0

dt

FIGURE 2 - RMS CURRENT DRAIN

16

~
'«

12

Max

.sz
~

"'"

~
'"=>
'"9

V

8.0

4.0

o
4.0

..V

--I--" -

V

6.0

Typ

~

8.0

V

V

l/

----:..-- -

10

~

12

Vee. SUPPL Y VOLTAGE (VOLTSI

7-566

14

16

-

Volts
-I'S

~__________________A__U_D_IO__D_R_IV_E_R__~

MFC4050

Advance InforIllation
CLASS "A" AUDIO DRIVER
Silicon Monolithic
Functional Circuit

CLASS "A" AUDIO DRIVER
· .. designed for driving Class "A" PNP power output transistor
stage applications.
•

Drives to 4 Watts of Output Power

•

Ideal for 12 Volt Automotive Equipment

•

No Gain Selection of Power Transistors Necessary

•

Economical 4·Lead Package

CASE206A

~~
V ~

PLASTIC PACKAGE

MAXIMUM RATINGS (TA = 2S o C unless otherwise noted)
Unit

Symbol

Value

Power Supply Voltage

V+

18

Vdc

Power Dissipation @ T A = 2SoC
(Package Dissipationl
Derate above 2SoC

PD

1.0

Watt

1/8JA

10

mW/oC

TA

-10to +75

°c

Rating

Operating Temperature Range

FIGURE 1 - TYPICAL 4·WATT AMPLI FIER CIRCUIT APPLICATION

3.3 M
22 k

1.0 k

0.33"F 15k

~r-~'~~~~4

2N176 or

1.8 V

Equiv
8.0 n
Load

----...,
330
Supply line
Filtering

See Packaging Information Section for outline dimensions.

7-567

I

.

13.6 V
-

•

MFC4050 (continued)

ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted I
Characteristic

Circuit

Symbol

~""

Min

Max

Unit

ID

,

4

2

3

C>-~

Current Drain
No Load

ID

-

10

mA

I nput Voltage

Vin

1.9

2.5

Vdc

lout

30

-

mAde

AVOL

130

-

VIV

V+ = 10.6 Vdc

lOOk

-t

~

2

Vin

i

V+ = 10.6 Vdc

-1-*'

13.6 Vdc

2

47

l out -:

-= 1

-=

=- 10

J~F

Output Current

lein = 1.0 mVlrmsl

@

1.0 kHzl

V+ = 13.6 Vdc

300

100 ~F

P~>3

~F

5.0

2

\1

0

22 k

Vo

4

-

-"

1

ein

-

47

./'(1

1.0k_,

10 k

Open Loop Voltage Gain

lein = 1.0 mVlrms)
30

@

1.0 kHzl

Q1: MPS65140r equiv.

-:~100
~
T~F
-=

7-568

MFC4050 (continued)

FIGURE 2 - CIRCUIT SCHEMATIC

7-569

~f

"'\

MFC4060A
MFC4062A
MFC4063A
MFC4064A

VOLTAGE REGULATORS

\..-------------'

VOLTAGE REGULATORS

MONOLITHIC VOLTAGE REGULATORS
This series of voltage regulators is designed to deliver load currents to 200 mAde. Output current capability can be increased to
several amperes through the use of external pass transistors. These
devices are industrial qual itt regulators designed for consumer applications requiring high volume and low cost.
•

Excellent Line and Load Regulation

•

Economical Four-Lead Package

Silicon Monolithic
Functional Circuit

'M""~

PLASTIC PA~;AGE""\Ill

FIGURE 1 - TYPICAL CIRCUIT CONNECTION
AND TEST CIRCUIT

FIGURE 2 - 5-VOLT. 5-AMPERE REGULATOR WITH
REMOTE SENSING PNP CURRENT BOOST
MJ900 OR EQUIV

Z

Vin

""'1

vo=(

3
MFC4060A
MFC4062A
MFC4063A
MFC4064A

Tk+1) VRef

~1

r:r-=

RI
R2
2k

r~

Vo
OUTPUT
+5.0V
330

Rl~(~-2)kn

FIGURE 3 - CIRCUIT SCHEMATIC

See Packaging I nformation Section for outline dimensions.

7-570

MFC4060A, MFC4062A, MFC4063A, MFC4064A

(continued)

MAXIMUM RATINGS (T A = +25 0 C unless otherwise noted.)
Rating
I nput Voltage

Symbol

Value

Unit

Vin

38
22

Vdc
Vdc

IL

200

mAdc

Po

1.0
10

Watt
mW/oC

°c
°c

MFC4060A/MFC4062A
MFC4063A/MFC4064A

Maximum Load Current
Power Dissipation (Package Limitation)
Derate above T A = +25 0 C
Operating Temperature Range (Ambient)

TA

-10to+75

Storage Temperature Range

Tstg

-65 to +150

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: TA = +25 0 C, Vin = 12 Vdc, Vo = 5.0 Vdc, IL = 10 mAdc, See Figure 1.)
MFC4062A

MFC!W60A

Characteristic

Symbol

Min

I nput Voltage Range

Vin

9.0

Output Voltage Range

Vo

Input·Output Voltage

Vin'Vo

Typ

MFC4063A
Max

Min

38

Typ

MFC4064A
Typ

Max

Min

Max

Unit

9.0

22

9.0

22

Vdc

35.. Vref

19

Vref

19

Vdc

3.0

Vdc

3.0

Differential

Reference Voltage
Standby Current Drain

Vref

4.6

liB

7.0

3.75

4.1

4.35

4.1

4.6

Vdc

3.7

6.0

3.7

7.0

mAdc

0.003

0.03

0.003

0.03

%/oC

0.01

0.03

0.06

0.03

0.2

0.4

3.6

(IL=O,Vin=20V)

Average Temperature Coefficient of Output
Voltage (T A = -10 to
+750 C)

TCVO

Line Regulation

Regin

%/Vin

(VO = 7.5 V)
12V

'x"

«

'"

TA=+75~

o

i

o

5.0

5

TA=+250C

~

40

t:..Vin = +3.0V

~ 0.03

\ \ \

80

0.04
",-

;;;

\

c

=:

TJ(max) = +125°C
ROJA =+100oCIW

1

=>

--

ffi

~TA-+500C

~ ..............

1'-10

15

0.0 2

'"
w

Z

:::;

0.0 I

~ 1---

20

25

30

35

40

o

5.0

--r--

t-.....

10

15

20

INPUT·OUTPUT VOLTAGE (Vdc)

INPUT·OUTPUT VOLTAGE (Vdc)

7-571

25

30

I

1L________________F_M__IF_A__M_P_L_IF_IE_R__~

MFC6010

FM LIMITING IF AMPLIFIER
· .. a monolithic silicon integrated circuit designed especially for
10.7 MHz I F applications.

Silicon Monolithic
Functional Circuit

Highlights Include:
• High Stable Gain
•

FM IF AMPLIFIER

@

10.7 MHz (40 dB typ)

Low Feedback Capacitance (lY121 = 0.01 mmho typ)

• Non·Saturating Limiting (With Suitable Load)
• Compatible With CA3053 and IlA703 (See Figures 7 and 8)
MAXIMUM RATINGS (T A

= +25 0 C unless otherwise noted.)
Symbol
V+

Rating
Power Supply Voltage
Output Collector Voltage

Input Voltage·
Power Dissipation @TA - 25 C
(Package Limitation)
Derate above 2SoC

Operating Temperature Range

Unit
Vdc

Value

20

V4

20

V2. V5

±S.O

PD

1.0

1/8JA
TA

10
-10 to +75

Vdc
Volts
Watt
mW/oC

uc

CASE 643A
PLASTIC PACKAGE

• Differential Voltage Swing.

FIGURE 1 - Typical Application (10.7 MHz Limiting Amplifier)

v+ e-----i

10k

100

Audio
Output

100% FM

Boonton
207H
or Equiv

10 k

51

___ ...1

Boonton
202H

1.0 k

47k

68

or Equiv

-=
T1 - Ratio Detector Primary Impedance

:;:j

1.5 kn

7-574

-=

r

MFC6010,(continuedj

APPLICATIONS INFORMATION

chosen to ensure that current limiting occurs before the collector
voltage drops to a value low enough to forward bias the collectorbase junction. In a transformer coupled circuit. the maximum
allowable load can be derived from

Because of the low reverse transfer admittance of the MFC601 0,
stability will be dependent mainly upon circuit layout. With
careful design, very high gain (in the order of 40 dB) may be

achieved at 10.7 MHz. The bias and supply currents may be varied
from their normal values (shown in Figure 4) by shunting addi·
tional resistance from pin 6 to ground or to the supply line.

Although less gain may be realized when using the MFC6010
as a Jimiter, it is recommended that it be operated in a non-saturated
mode. This mode of operation results in a high output impedance

where values for 10 may be determined from Figure 4 (providing
the bias currents have not been altered from their normal values).
In order to avoid degradation of AM rejection, the input signal
should not exceed one volt (rms).

at limiting. Therefore the operation of the demodulator circuit is
not subject to variable loading of the limiter output.
In order to avoid driving the amplifier transistor components
of the MFC6010 into saturation, the load resistance must be

~;~':;:9)

5~

0

7

2

1

4~ ~3
50

o

Motorola terminal and pin number position

• Foil patterns shown are intended to show pin-for-pin interconnection.
ments of the individual design.

•

I1A703 or CA3053 terminal and pin number
position

Anv change in the number of components is dictated by the require-

•
7-575

•

"\

MFC6020

DUAL TOGGLE FLIP-FLOP

'-----------'

DUAL TOGGLE FLIP-FLOP
DUAL TOGGLE
FLIP-FLOP

• Wide Operating Voltage Range - 4.0 to 16 Volts
•

Regulated Supply Not Required
Silicon Monolithic
Functional Circu it

• Compatible with TTL and DTL
•

Economical 6·Lead Plastic Package

MAXIMUM RATINGS
Rating

Symbol

Value

Volts

Power Supply Voltage

Vee

19

Vdc

Output Sinking Current

Isink

10

mA

Negative I nput Voltage

Vin

0.5

Vdc

Po
lIBJA

1.0
10

Watt
mwl"e

TJ,Tstg

-40 to +125

°c

TA

-IOta +75

°c

Power Dissipation @ T A ::: 2SoC

Derate above 25°C
Operating and Storage Junction
Temperature Ranne
Operating Temperature Range

TYPICAL APPLICATION - ELECTRONIC
ORGAN DIVIDER
C5

C4

C3

,--- ----,
I
I
I

I
I

·C·

OSCILLATOR

T

I

C2

CASE 643A
PLASTIC PACKAGE

CI

r

I
I

Q

T

I
I

L _______ II

I
L
______ ...JI

MFC6020

MFC6020
C4= 261 Hz

FIGURE 1 - CIRCUIT SCHEMATIC (One Half of Circuit Shown)

BLOCK DIAGRAM

TI

T2

~3QI

Wu
_

J.l-04 Q2
5'U
Vcc=Pin6

GND=Pinl

See Packaging Information Section for outline dimensions.

7-576

MFC6020

(continued)

ElECTR ICAl CHARACTERISTICS (Vee = 12 Vdc, Vin = 4.0 V,Square Pulse, f = 10 kHz, 50% Duty Cycle, tf = 1.0 V!/-IS (Min),
T A = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Operating Power Supply Voltage

Vee

4.0

-

16

Vdc

Toggle Frequency

fTog

-

3.0

-

MHz

Output Voltage (High)
(Vee = 4.0 Vdc)

VOH
3.5

-

-

15.5

-

-

-

-

0.5

(Vee

(Vee

Vdc

= 16 Vdc)

Output Voltage (Low)
(Vee = 4.0 Vdc)

= 16

Unit

Vdc

VOL

Vdc)

-

-

1.0

Operating Drain Current

10

-

-

32

mAde

Output Sinking Current
(V o -

~
'"=>
'-'

V

0 B.O

~

r-

-

V
~

Typ

/

/
......

--

~

~

o
4.0

6.0

B.D

10

12

Vee, SUPPLY VOLTAGE (VOLTS)

7-577

14

16

-

Volts

-/-IS

MFC6030A
MFC6032A
MFC6033A
MFC6034A

~~_________V_O__LT_A_G_E__R_E_G_U_L_A_T_O_R_S__~I

VOLTAGE REGULATORS
MONOLITHIC SILICON
FUNCTIONAL CIRCUITS

MONOLITHIC VOLTAGE REGULATORS

This series of voltage regulators is designed to deliver load currents
to 200 mAdc. Output current capability can be increased to several
.amperes th~ough the use of external pass transistors. These devices
are industrial quality regulators intended for consumer applications
requiring high volume and low cost.
• Excellent Line and Load Regulation
• Current· Limit Feature Available
• Economical Six· Lead Package

ITOP VIEWI

PLASTIC PACKAGE

CASE 643A

FIGURE 3 - CIRCUIT SCHEMATIC

FIGURE 1 - TYPICAL CIRCUIT CONNECTION
AND TEST CIRCUIT

~""",_-o3

~~~:g~~~

1-<>4_ _-,

MFC6033A
MFC6034A

Vo=

(~+ 1)

Vref

Rl '"

(~O -2)

kO

25 k

;: r

4

.......+-.....- .....--.-.-0 5

1.6 k

FIGURE 2 -15-VOL T. 1.O-AMPERE REGULATOR
(with short-circuit protection)

6
MJE521

1.4 k

OR EQUIV

7.50.10W

INPUT
+24 V to
+32 V

2

MFCeQ30A
MFC6032A

2200

6
500

820

See Packaging Information Section for outline dimensions.

7-578

1.2 k

1.1 k

MFC6030A, MFC6032A, MFC6033A, MFC6034A (continued)

MAXIMUM RATINGS (TA: +25 0 C unless otherwise notedl
Symbol

Rating

Input Voltage
MFC6030A, MFC6032A
MFC6033A, MFC6034A

Value

Unit
Vde

Vin

38
22

Maximum Load Current

IL

200

mAde

Power Dissipation (Package Limitation)

Po

1.0
10

Watt
mW/oC

°c
°c

Derate above T A : +25 0 C
Operating Temperature Range (Ambient)

TA

-10to+75

Storage Temperature Range

T stg

-65 to +150

ELECTRICAL CHARACTERISTICS (Vin : +12 Vde, Vo : +5.0 Vde, I L = 1.0 mAde, Rse: 0, T A: +25 0 C unless otherwise noted.1
(See Figure 11
MFC6030A

Characteristic

Symbol

Min

I nput Voltage Range

Vin

9.0

Output Voltage Range

Vo

VRel

Input·Output Voltage
Differential

Vin'VO

3.0

Reference Voltage
(Rl : 01

V re !

Typ

-

Mal(

Min

Typ

Max

Min

Typ

Max

Unit

38

9.0

-

38

9.0

-

22

9.0

-

22

Vde

35

VRel

35

VRe!

-

19

VRe!

-

19

-

3.0

-

-

3.0

-

3.0

-

4.35

3.6

4.1

4.6

3.75

4.1

4.35

3.6

4.1

4.6

-

3.7

7.0

-

3.7

6.0

-

3.7

7.0

liB
3.7
TCVO

Line Reg. (VO: 7.5 VI
(12V ...•

Ise

Limit (Rse: 100 ohms,
VO: 01

-

I. · •·••• ~•.

-.'

0.03

-

0.003

0.03

-

0.003

0.03

-

-

0.01

0.03

-

0.06

-

-

-

-

0.03

0.2

-

6.5

-

-

%/Vin

0.06

"~

-

-

%/VO

-

'.

5

0.003

I·····

1"< I;~~ I:h.;

:;>~ liiio.

mAde

%loC

~

,I:iiili:[
...... I)·OJ I"b;;,
1':--'

Short-Circuit Current

Vde
Vde

'.'

0.03

0.003

• ":C ••.

(1.0mA

~

\TA =+25 0 C

120

0

'"~

._
ROJA ~ +100 oCIW

\1\

z
0

0.03

;::

~Vin =

S
=>

""

I'-10

~

. / TA ~ +50 oC

--

f'-..d r--15

20

z
::;

25

0.01

INPUT·OUTPUT VOLTAGE (Vdc)

30

35

40

-

---r--

w

to--

+3.0 V -

0.02

o
5.0

10

15

20

INPUT·OUTPUT VOLTAGE (Vdc)

25

30

MFC6030A, MFC6032A, MFC6033A, MFC6034A (continued)

TYPICAL APPLICATIONS

TYPICAL CHARACTERISTICS (continued)

FIGURE 9 - MFC6030A -15 VOLT REGULATOR with
CURRENT LIMIT
FIGURE 6 - LOAD REGULATION versus
INPUT·OUTPUT VOLTAGE

-16 V

-20 V
INPUT

02

+0.1

'0

~z

IL = 1.0 to 50 mA-

0

10

-

2 ,..------,

;::

:s
~

-

r-..

0

<

g

-0.1

5

6
2 k

0.01 p.F

1.0M

5.3 k

Rl

+

·0.2
10

5.0

IS

20

NOTE: For other output voltages:
(-9 V';;;VO";;'-35 V)
21 v ol
Rl (k!l) = - - -2

30

25

INPUT·OUTPUT VOLTAGE Nd,)

V re !
Vz

FIGURE 7 - LOAD REGULATION WITH
CURRENT LIMITING
+0.1

z

0

~
~

-......

Rsc- 0

.............

-0.1

........

"

-0.2

0

-0.3

-0.4

o

20

+24 V to
+32 V

Rsc=IOn

1\
\

40

2

60

I,e = 0.37 A

80

=

Vo R2 + 0.6 (R2 + R3)
Rl R3

I

I

I
./.

R2= 1.8kl'l

./ "/.."

Vref= 4.1 V
(typical)

10

~

"'

6.0

x.

./.
//'J' /'

o

820

MJ1000
OR EOUIV

INPUT
(POWER)
+9.0 V

./

~ Z~
~ V'/' , / '\..V ref- 4.6V
Vref = 3.6 V....."
A ~ k""
¥.h :;'l('
Vref = 3.75 V '"

4.0
2.0

Z /'/

\

JO.OOI p.F

FIGURE 11 - 6.D-VOL T, 5.D-AMPERE HIGH
EFFICIENCY REGULATOR

FIGURE 8 - OUTPUT VOLTAGE versus Rl

12

MFC6030A
MFC6032A

2200

\

10

14

OUTPUT
+15 V

INPUT

\

OUTPUT CURRENT (mA)

8.0

+1

MJE521
OR EOUIV

-

Rsc = 3.25 n

<

g

IVol
-2-

FIGURE 10 - 15·VOLT, 2.D-AMPERE REGULATOR
(with current foldback)

'0
>
~
;::

= IVinl-

~~

=~

o

3.0

6.0

9.0

Vref = 4.35 V

12
15
18
21
OUTPUT VOLTAGE (Vd,)

INPUT
(RGLTR)
+18 V 2

0.11:
p.F ':'

24

27

MFC6030A
MFC6032A
MFC6033A
MFC6034A

330

5
6
680

30

7-580

MFC6030A, MFC6032A, MFC6033A, MFC6034A (continued)

TYPICAL APPLICATIONS (continued)
FIGURE 12 - CURRENT BYPASS
(Load current range, 400-to-SOO mAl

FIGURE IS - VOLTAGE BOOSTED 40-VOLT.
100 mA REGULATOR
(with short-circuit current limiting)

25 n, 5_0 W

INPUT
(POWER)
+60 V

OUTPUT
+5_0 V
INPUT
+15 V

OUTPUT
+40 V

5_1

2

MPS-A55
OR EQUIV
10 k
18 k

INPUT
(RGL TR)
+15 V 2
o.I/lFl

2

MFC6030A
MFC6032A

0_1

"F

0_001

5

~/lF

2 k

MPS-U05
OR EQUIV

INPUT

+28 V

4

10.001 /IF

FIGURE 13 - 100 mA CONSTANT CURRENT SOURCE

,--------,3

27

3
MFC6030A
MFC6032A
MFC6033A
MFC6034A

6

5
43
lW

FIGURE 14 - S_O-VOLT, S.O-AMPERE REGULATOR with
REMOTE SENSING, PNP CURRENT BOOST

CONSTANT

llL

••--------:1..,-:->--------...

g~~:~;T
(0 to +20 V)

MJ900
OR EQUIV

Pin 4 not connected

0.1 n
MFC6030A
MFC6032A
MFC6033A
MFC6034A

OUTPUT
+5 V

4

330
680

7-581

RL

•

MFC6040

'l. . ____

E_L_EC_T_R_O_N_I_C_A_T_T_E_N_U_A_T_O_R_..,,1

ELECTRONIC ATTENUATOR

ELECTRONIC ATTENUATOR

•

Silicon Monolithic
Functional Circuit

Designed for use in:
DC Operated Volume Control
Compression and Expansion Amplifier
Applications

• Controlled by DC Voltage or External Variable Resistor
•

Econo"';ical 6-Lead Plastic Package

·CASE 643A
PLASTIC PACKAGE

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Unit

Symbol

Value

Power Supply Voltage

V+

21

Vdc

Power Dissipation @ T A = 25°C
(Package Limitation)
Derate above T A = 25°C

PD

1.0

Watt

10

mW/oC

Rating

1/8JA

Operating Temperature Range

°c

-10 to +75

TA

FIGURE 1 - TYPICAL DC "REMOTE" VOLUME CONTROL

1.0",F

3

~
MFC6:40

.I,

5

"",/

/'
Remotely
Located
Pot.

V .

/.

@'V

2
r--<

1

50 MF;::i'

50 k

-:::-

-:::-

See Packaging Information Section for outline dimensions.

7-582

6

eout

"=-1

MFC6040 (continued)

ELECTRICAL CHARACTERISTICS (ein = 100 mV, f = 1.0 kHz, Rl = 0,
Circuit

v+ =

16 Vdc,TA = 25°C unless otherwise noted)
Symbol

Characteristic
Operating Power Supply Voltage

,1--O---I~4+ ~

~I

~'~F
1

1-=

3

5

2./

.-~--..,~~

,

....

50l'F

'.

~

~t RC

1

6

-=

~ les

Typ

Max

Unit

18

Vdc

2.0

mAde

0.5

Vlrms)

9.0

Control Terminal S;nk Current

__________le_in__
=_O_)______________________

'~____~r-__r-__~__-r__--;

Maximum Input Voltage

ein

-

-

Voltage Gain

AV

11

13

~------------------------------------~-------r---r--~----r----;

1

eout

Min

~-=620pf ~-----------------------------------T------T---T---T---~---1
Attenuation Range
IRc = 33 k ohms)

70

Total Harmonic Distortion
lein

THD

90

-

dB

0.6

1.0

%

= 100 mV, eo = 100 mV)

FIGURE 2 - CIRCUIT SCHEMATIC

K

6

Jy

ROl lOff

to.

5
OU TPUT

~

-=

2

co NTROl

1

~
-

1

r

INPUT

dB

f-L-

)--- -=

V'

"'=

-=.F

-=
3

"

I
-

-

7-583

~r

-

MFC6040 (continued)

TYPICAL ELECTRICAL CHARACTERISTICS

(v+ = 16 Vdc, T A = 25°C unless otherwise noted)

-

FIGURE 3 - ATTENUATION ve,susOCCONTROL VOLTAGE

20

r-...

-.......

FIGURE 4 - ATTENUATION ve,susCONTROL RESISTOR

rI'-...

20

...........

'"

'"

:E

z

0

40

«>=
:::>
~
>>-

60

«

odB Reference = 13 dB Gain
f = 1.0 kHz

""

"-

80

100
3.5

0

1,\
."\.

4.5

5.5

5.0

6.0

6.0

r--

~

'\

~
Z

1);

Input voltage (ein) = 10 mV
Pin 6 uncompensated

w

to

"'"

I.........

20

30

40

-~

6.0

- --

«

1\

6. 0

........ l--"

~
0
> 4.0
>-

o

ii:

>

>-

:> 4. 0
«

:::>
0

11

2. 0

0
100

15

8.0

to

to

~

10

""

FIGURE 6 - OUTPUT VOLTAGE SWING

10

8. 0

8.0

10

2

z

"'- I'-.

Re. CONTROL RESISTOR (k OHMS)

FIGURE 5 - FREQUENCY RESPONSE

w

1"-

Re is from pin 2 to ground

100
4.0

14

~

f\

odB Reference = 13 dB Gain
f =1.0 kHz

V2, CONTROL VOLTAGE (VOLTS)

~

......

0

~

4.0

'"

1.0 k

10 k

1\
100 k

10 M

1.0 M

.; 2.0

>

o

B.O

100M

9.0

10

11

f, FREQUENCY (Hz)

12

13

14

15

V+, SUPPLY VOLTAGE (VOLTS)

FIGURE 7 - TOTAL HARMONIC DISTORTION
4.0

3.0

L

V

2.0

""

I---

odB Reference = 13 dB Gain

1

f =1.0 kHz
'0 =2.5 V(rms)

/
1

1. 0

---I'
0

10

20

30

40

50

ATTENUATION (dB)

7-584

60

70

80

16

17

18

"\

MFC6050

DUAL TOGGLE FLIP-FLOP

'------------

DUAL TOGGLE FLIP-FLOP
WITH RESET

DUAL TOGGLE FLIP-FLOP
WITH RESET

• Wide Operating Voltage Range - 4.0 to 16 Volts

Silicon Monolithic
Functional Circuit

•

Regulated Supply Not Required

•

Compatible with TTL and DTL

•

Economical 6-Lead Plastic Package

•

Reset (R) Available to Set Output to 0 Regardless of Previous
History

MAXIMUM RATINGS
Rating

Symbol

Value

Volts

Power Supply Voltage

Vee

19

Vdc

Output Sinking Current

'sink

15

mA

Negative Input Voltage

Vin

0.5

Vdc

Po
lIeJA

1.0
10

Watt
mw/oe

TA

-10to +75

°e

Power Dissipation @ T A = 2SoC
Derate above 25°C
Operating Temperature Range

TYPICAL APPLICATION - DIVIDE BY 60 COUNTER
CASE 643A

NDte: Enahle

mUSlblgr~unde~

ENABLE

10 $ta,1 count

OUTPUT

SIMPLIFIED CIRCUIT SCHEMATIC

BLOCK DIAGRAM

(One-Half of Circuit Shown)
Q1

ONO
See Packaging Information Section for outline dimensions.

7-585

•

•

MFC6050

(continued)

ELECTRICAL CHARACTERISTICS (Vee = 12 Vdc. Vin = 4.0 V.Square Pulse. f = 10 kHz. 50% Duty Cycle. tf = 1.0 Vllls (Min).
T A = 25°C unless otherwise noted)
Characteristic

Symbol

Min

'Typ

Max

Operating Power Supply Voltage

Vec

4.0

-

16

Vdc

Toggle Frequency

fTog

-

3.0

-

MHz

Output Voltage (High)
(Vee = 4.0 Vdc)

VOH
3.5

-

-

0.5

32

mAde

-

mAde

Vdc

(Vec = 16 Vdc)

15.5

Output Voltage (Low)
(Vee = 4,0 Vdc)

Unit

Vdc

VOL

Operating Drain Current

10

-

-

Output Sinking Current
(Va 1.0Vdc)

Isink

-

8.0

-

(Vec =16 Vdc)

1.0

Rise Time

tr

-

250

-

ns

Storage Time

ts

-

350

-

ns

Fall Time

tf

-

60

-

Cross Talk
(Vin = 15 V,Square Pulse. Vee = 16 Vdc)

Vo

ns
mV

T1 to 02
T2toOl

-

-

-

-

15
15

1.0

-

Vdc

I "put Resistance

Rin

10

-

-

kn

Output Resistance (Output High)

ROH

-

-

2.8

kn

Max Vin at R for ryo effE!ct@750C

,

INPUT PULSE REQUIREMENTS

VH

)EADING
EDGE

TRAILING
EDGE

Characteristic

Symbol

Min

Max

Unit

Pulse Magnitude

VH

+4.0

-

Volts

Zero Level

VL

-

+1.0

Volts

Leading Edge

No Requirement

VL·

0

dv

-

Trailing Edge

t

-

-1.0

dt

FIGURE 2 - RMSCURRENT DRAIN versus SUPPLY VOLTAGE
32

§

24

';(

Max

.§.

«
'"CJ

16

,/'

I-

~
~

13
E

8,0

/

../

z

V
~

..-

o
4.0

6,0

...-...-

--Typ

~

8,0

V

10

f-"'"

12

VCC,SUPPL Y VOLTAGE (VOLTS)

7-586

v
...- ~

14

16

Volts

-IlS

'\

MFC6060

3-INPUT "AND" GATE

'-_ _ _ _ _ _- - - - - - 1

3-INPUT "AND" GATE
•

Wide Operating Voltage - to 16 Volts

•

Compatible with TTL and DTL

•

Economical 6-Lead Plastic Package

•

Regulated Supply Not Required

3-INPUT "AND" GATE
Silicon Monolithic
Functional Circuit

MAXIMUM RATINGS
Rating
Power Supply Voltage

Power Dissipation @ T A

=

Unit

Symbol

Value

VCC

19

Vdc

Po

1.0

Watt

1/0JA

10

mW/oC

TA

o to +75

°c

TJ,T stg

-40 to +125

°c

25°C

(Package Limitation)

Derate above 25°C
Operating Temperature Range
Operating and Storage Junction

Temperature Range
CASE 643A
PLASTIC PACKAGE

TYPICAL APPLICATION
FIGURE 1 - OIVIDE-BY-l0

,-----,
MFC6050

I

Input

.-o-+---j

MFC6050

r-- - - - ,

I

I
I

I
5

I

I

I

4

I

I

I

I

I

I

BLOCK DIAGRAM

I

~+--o--. Output = '7~t
I
L _ _ _ _ -1
MFC6060

See Packaging Information Section for outline dimensions.

7-587

VCC=Pin4
GND = Pin 1

•

M FC6060 (continued)

ELECTRICAL CHARACTERISTICS (Vee = 16 Vde, TA = +2Soe unless otherwise noted)
Characteristic

Figure

Symbol

2

VOL

Output Voltage - Low

Min

Max

0.6

Unit

Vde

Pin

3 = Vee; Pin 5 = Vee; Pin 6 =GNO

Pin

5 =GNO; Pin 6 = Vee; Pin 3 = Vee

-

Pin

3 =GNO; Pin 5 = Vee; Pin 6 = Vee

-

0.6

0.6

Output Voltage - High

3

VOH

15

-

Vde

Drain Current

3

10

-

10

mAde

FIGURE 3 - OUTPUT VOLTAGE (HIGH)
TEST CIRCUIT

FIGURE 2-0UTPUTVOLTAGE (LOW)
TEST CIRCUIT

~
ee=16VdC

3

5

2

10 k

v!,

6
Vee = Pin 4
GNO = Pin I

Vee = Pin 4
GNO=Pinl

i

FIGURE 4 -CIRCUIT SCHEMATIC

4

Vee

GNO

7-588

~~_________A
__
U_D_IO__
PO_W
__
ER__A_M_P_L_IF_I_E_R~

MFC6070

1-WATT
AUDIO POWER AMPLIFIER

1-WATT AUDIO POWER AMPLIFIER
· .. designed primarily for low-cost audio amplifiers in phonograph,
TV and radio applications.
•

100 mV Sensitivity for 1-Watt*

•

Low Distortion - 1% @ 1-Watt typ *

Silicon Monolithic
Functional Circuit

• Short-Circuit Proof - Short Term (10 seconds typ)
•

No Heatsink Required for 1-Watt Output at T A ~ 55 0 C*'

•

Excellent Hum Rejection
·Circuit Dependent

•• Voltage Dependent

MAXIMUM RATINGS ITA = +25 0 C unless otherwise noted)
Symbol

Value

V+

20

Vdc

PD
1/BJA

1.0
8.0

Watt
mW/oC

Operating Temperature Range

TA

-lOto +55

Storage Temperature Range

T stg

-40 to +150

°c
°c

Rating
Power Supply Voltage
Power Dissipation
Derate above T A = +2SoC

Unit

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Ambient
"Thermal resistance is measured in still air with fine wires connected to the leads, representing

the "worst case" situation.
For a larger power requirement, pin 1 must be soldered to at least one sq. in. of copper
foil on the printed circuit board. The 8 JA will be no greater than +90 o C/W. Thus, 1.39
Watts could be dissipated at +2SoC, which must be linearly derated at 11.1 mW/oC from
+2SoC to +1S00C.

FIGURE 1 - TYPICAL 1·WATT PHONOGRAPH AMPLIFIER
(Ceramic cartridge input)

v'

INPUT

loOM

1.5M

510k

See Packaging Information Section for outline dimensions.

7-589

CASE 643A
PLASTIC PACKAGE

MFC6070

(continued)

ELECTRICAL CHARACTERISTICS IV+= 16 Vdc, See Figure2 for test circuit, TA = +25 0 C
unless otherwise noted)

Characteristic
Quiescent Output Voltage

Quiescent Drain Current (ein

= 0)

Sensitivity. Input Voltage
(ein adjusted for eo

= 4.0 V(rms)

@

Symbol

Min

Typ

Max

Unit

Vo

-

8.0

-

Vdc

10

-

5.0

18

mA

ein

-

100

150

mV

-

1.0

10

1.0

3.0

-

-40

-

1.0 kHz. Power Output = 1.0 Watt)

THO

Total Harmonic Distortion
leo = 4.0 V(rms) @ 1.0 kHz, Power Output = 1.0 Watt)
(ein adju~ted for eo = 1.26 V{rms) @1.0kHz,PowerOutput=100mW)

%

-

Hum and Noise UHF Standard A201, 1966)

FIGURE 2 -I-WATT AUDIO POWER AMPLIFIER TEST CIRCUIT

O.lIl F

6BO k

16!l LOAO
15 k

470pF
6
Vo

1.5 M

510 k

Circuit Schematic

7-590

t

r

dB

MFC6070

(continued)

TYPICAL CHARACTERISTICS
(v+ = 16 Vdc, T A

= +2SoC unless otherwise noted)

FIGURE 3 - TOTAL HARMONIC DISTORTION
versus OUTPUT POWER
5.0.---,---,.---,---,r---,---,r----,----,----,----,

4.0 I---I----,I---I---jl---j--jl---j--j--j--j

FIGURE 4 - POWER DISSIPATION versus OUTPUT POWER

1.0,----.---,---,--,-----.---.-.1---,-----,
V+ = 18 V

~-

ZO

3.0 I - - - + - - + - - + - + - + - V + = IS Vdc - + - - + - - 1
f = 1.0 kHz
2.01---1---j1---1---j--j--j--j--j--j--j

z

0.8

......V

V

IS V

-----

~~

-_r-

- O.6r.,....-""--r----=:::I::=*=::!::=j--t-:-:-::-T-i
14
.-f..--

'"

r---

AV=40
1.0 I--+--F:=,t--+-+-+--+=~=+=-l
=20
0.4

0.2

0.8

O.S

V

~ 0.41---+--+---+--+----;1--+--+---1
~

1.0

f =1.0 kHz
1
0.20'=.2--.l..---'0"'.4:---"---:f
0.",s--L---:0'=.8---;--"---:I-:.0

po. OUTPUT POWER (WATTSI

po. OUTPUT POWER (WATTSI

FIGURE 5 - TOTAL HARMONIC DISTORTION versus FREQUENCY

5.0

i&
z

0

~
to

4.0

It Vdc
1---+--I--1-:-+--I--1-+-+-I-I-I-- V+=
Po =1.0W -+--+-+---+--+-+--+-+-+-+---+---j

0

i5

u

3.0

~
~
~

2.0 1----+--I---1--r--I----1--r-+-I--I--I-----r--1--+-+---1--+-+-+-1--1-+-AV=40 ~

;;(

6fci

LO

t----

'"f0
100

""""-

--- ~~

200

300

500

1.0 k

3.0 k

2.0 k

5.0k

10 k

20 k

I. FREQUENCY (Hzl

APPLICATIONS INFORMATION
Shown in Figures 7 and 11 are low cost 1 W phono amplifiers with
~. sensitivity (@ 1 kHz) of approximately 450 mV. The input impedance of both amplifiers is approximately equal to R4 and the
gain is determined by (R7 + Rl0)/R5. To change the gain of the
amplifier, change the value of RS and hold (R7 + R10) between
1 M and 2.2 M. This allows the use of a small and less.expensive
capacitor for C2.
The bass boost effect shown in the frequency response curves
(Figures 10 and 141 is provided by the parallel combination of C4
and A 10 and can be eliminated by removing C4 and replacing (R7 +
A101 with a 2.2 Megohm resistor. High frequency compensation
is provided by C6 and the low frequency roll-off is determined by
the impedance network of C2 and R5, C3 and A4, and C8 and
the speaker. The series combination of RA and CA from pin 6 to
ground may be required for stability, depending on printed circuit
board layout, speaker reactance, and lead lengths.
Device ac short-circuit capability was tested in both the a-ohm
and 16-ohm amplifiers by shorting pin 6 thru a 500 microfarad
capacitor to ground for a period of ten seconds with the amplifier
operating at full rated output.

7-591

The speaker can be connected to V+ (alternate connection shown
below) or ground (Figures 7 and 111. Printed circuit board art
work (1:1 pattern) is shown for both systems in Figures 16 and
18. A picture of the completed board for the grounded speaker
system is shown in Figure 21.

ALTERNATE CONNECTION FOR SPEAKER TO V+
(See Figure 20 for Parts List)

....

• V+

R9

~~
2
0-

~

~

RII
;fCS

'F'C7
RA
CA*

•

I

•

MFC6070 (continued)

APPLICATIONS INFORMATION (continued)
(R L = 8.0 ohms, T A

=+25 0 C unless otherwise noted)

FIGURE 6·- POWER SUPPLY

~

1

RS

Motor"
Overwind
Or

v+

or Equiv

l

Transformer

±500"f

RS

1

Motor
Overwind
Or
Transformer

v+
IN4001
or Equiv
;j'IOOO"f

or

RS - Series resistance of winding

-=l::-

VAC for Vee;; 16 V is approximately 12 V

FIGURE 8 - TOTAL HARMONIC DISTORTION
versus OUTPUT POWER FOR FIGURE 7

FIGURE 7 -PHONOGRAPH AMPLIFIER 1 WATT -80HM
(See Figure 15 for Parts List)
5.0

~

01

O,W-

04

TONE

"1_

z
e

r-~--1"""NV~-------""""V=+13V

1;
0',:"

oi ±cs"'
-=

':"3

~
In

"

4

C6

C7

~

C8

__

+-~I/'0",'~""'-'W1r---""'1..J
",,0

1_ C2

,:"06

i:~-

)CA
I

/

II

§'"

rVO_"U_ME~ ~2~~~6+--:-'A~~I~

R5

1= 1.0 kHz

C 3.0

'"

"" 5

4.0

e

012

I

g

1.0

/

13 V
0
0.4

0.2

0

':"

0.6

-

V

V+'i.I~ I--""

f-

an

II

71'TiON~

2.0

....
"....e

I

':"

""-'

V
1.0

O.B

Po, OUTPUTPOWER (WATTS)

FIGURE 9 - TOTAL HARMONIC DISTORTION
versus FREQUENCY FOR FIGURE 7

FIGURE 10 - FREQUENCY RESPONSE FOR FIGURE 7

20

-~

15/

--

V

z

;;:

"'

10

Po

=250mWat 1.0 kHz

V+'12V
5.0

III
III

13 V

~~00~~2~0~0~~~5~070LL~1.0~k-~2~.0~k~~~5~.0~k~~I~OLk-~20~k
t, fREQUENCY (Hz)

0
100

200

500

1.0 k

2.0 k

t, fREQUENCY (Hz)

7-592

5.0 k

10 k

20 k

MFC6070 (continued)

APPLICATIONS INFORMATION (continued)
(RL = 16 ohms, TA = +25 0 C unless otherwise noted)
FIGURE 11 -1.0WATT, 16 OHM LOAD PHONOGRAPH AMPLIFIER

FIGURE 12 -TOTAL HARMONIC DISTORTION
versus OUTPUT POWER FOR FIGURE 11

(See Figure 15 for Parts List)

5.0 r-----r----,----.-----,--,----,----,---r---,----,
AI

,,:T
TONE

C6

R5

~

z
o

C8

~
~ 2.0

I RA

I
IrC

RlO

g

6

R7

I

f--j---+---+--+--+--+---t---f--j--1

~ 3.0 f---f---+---+---f+-~-IO-k-Hiz --+-+---t--jf--j

C7

R3=VOLUME

r-~~__~2~~_O)~

4.0

o
>-~

RlI
4

"1_

23
~

RI1

I

I

'I )

: AI:

g

/
i----I__-4--_+---r--+--+--+---+--,I-/~-1

1.0 i----I__-4--_+---r---t-V+ ~ IS V+_--t,..£--I__-i

>-)Gil

16 V

°OL---L--JO.1~~--~0~.4---L--~0.6~~--~0~.B---L--I~.0

L_---1
OPTIONAL

Po, QUTPUT PQWER IWATTS)

FIGURE 13 - TOTAL HARMONIC DISTORTION
versus FREQUENCY FOR FIGURE 11

FIGURE 14 - FREQUENCY RESPONSE FOR FIGURE 11

20
~

z

0

~

16

20

0

V

t;

"
u

11

~

:;;

~

Po = 1 W

~

B.O

z

1\

~

~

151__--+-4_++++~1__--+-4_+++++H----~

10 1__--+-4_+++++1-1__--+ Po ~ 250 mW@ 1.0 kHz -

~

~'"

00"

4.0 " -

or

>--

t'-....

5.0

t---... t--

f---+--+--+++++I'f---+--+-+++++tl------j

oL--J-L~ItttC==t=~~±tt~:J

°1'::00:-----::10~0--'--'O::50~OLL..LI:-:.0~k-----::1.0~k:--'~5;:-:.0~k..w...LI~0-;-k----;1:;;'0k

I, fREQUENCY IHzl

I, fREQUENCY (Hz)

100

100

500

10k

1.0k

5.0k

10k

10k

FIGURE 15 - PARTS LIST FOR FIGURES 7 AND 11

Rl = 180 k ohms
R2 = 5.0 Megohms
R3 = 5.0 Megohms
R4 = 1.0 Megohm
R5 = 150 k ohms*
R6 = 910 k ohms*
R7 = 680 k ohms
R8 = lS0 k ohms

R9 = 1.0 Megohm
R10 = 1.5 Megohms
R11 = 6.S kilohms
R12 = 6.S kilohms
RA = 10 ohms*'
Cl = 470 pF
C2=0.1/lF

C3 = 0.05 /IF
C4 = 470 pF
C5 = 0.1 /IF
C6 = 470 pF
C7 = 0.1 /IF
CS = 500 /IF*
CA = 0.1 /IF**

*For Figure 11 (l6-ohm load) change R5 to 100 k ohms, R6 to S20 k ohms
and CS to 250 /IF.
**Optional- Not included on board. (See Applications Information Note)

7-593

•

MFC6070 (continued)

APPLICATIONS INFORMATION (continued)
FIGURE 16-PRINTEDCIRCUITBDARD (Foil Side)
(Speaker Grounded)

FIGURE 18 - PRINTED CIRCUIT BOARD (Foil Side)
(Speaker to v+)

FIGURE 20 - PARTS LIST FOR FIGURE.19
(See Applications Information Note)

Rl
=180kohms
R2,R3 = 5.0 Megohms
R4,R9 = 1.0 Megohm'
R5
= 82 k ohms .
R6
= 820 k ohms
R7
= 680 k ohms
R8
= 180 k ohms
Rl0 = 1.5 Megohms
Rl1 = 15 k ohms
RA = 10 ohms*

Cl,C4,C6 = 470 pF
C2,C5
= O.lIlF
C3'
= 0.05 IlF
C7
= 250 IlF
CA
= O.lIlF*
*Optional- Not included on
board. (See Applications
Information Note)

FIGURE 17 - COMPONENT DIAGRAM FOR fiGURE 16

FIGURE 19 -COMPONENT DIAGRAM FOR FIGURE 18

FIGURE 21 - COMPLETED BOARD
(Speaker Grounded)

~~_________________R_S__F_L_IP_-F_L_O_P____~
MFC6080

RS FLIP-FLOP
RS FLIP-FLOP
... designed fqr use in high·level, low·speed logic and timing systems.
•

Wide Operating Voltage Range - 4.0 to 16 Volts

•

High Current Buffered Outputs Allows Direct Drive of Medium
Current Lamps and Relays

•

Compatible with TTL and DTL

•

Regulated Supply Not Required

Silicon Monolithic
Functional Circuit

MAXIMUM RATINGS
Rating
Power Supply Voltage
Power Dissipation @TA "" 2SoC
(Package Limitation)

Symbol

Value

Vec

19

Vdc

Po

1.0

Watt

Unit

I/oJA

10

mW/oe

Operating Temperature Range

TA

a to +75

Operating and Storage Junction
Temperature Range

TJ,Tstg

-40to+125

°c
°c

Derate above 2SoC

CASE 643A
PLASTIC PACKAGE

TYPICAL APPLICATION
FIGURE 1 - BOUNCELESS SWITCH

BLOCK DIAGRAM

VCC

N.C.
\-o---eDUTPUT

SWITCH
OR

RELAY
CONTACT

N.D.

_--0-1

t[Jj
R

a

S

fi

6

3

Vee = Pin 5
GNO = Pin 1

See Packaging Information Section for outline dimensions.

7-595

4

I

M FC6080 (continued)

ELECTRICAL CHARACTERISTICS (Vee

= 16 Vde. Vin = 4.0 to

Characteristic
Output Voltage
R Input
Pin 2 = Vin. Pin 3

Saturation Voltage
R Input
Pin 2 = Vin. Pin 4

Figure

Min

Typ

Max

Unit

Vout

1

14

-

-

Vde

Vsat

1

-

-

1.0

Vde

lin

2

-

170

-

"Ade

Isink

-

-

-

120

mAde

10

2

-

-

20

mAde

= V out • Pin 6 = Vin

= V out • Pin 6 = Vin
= Vsat. Pin 6 = GNO

S Input
Pin 2 = GNO. Pin 3
R S Input
Pin 2 = Vin. Pin 3

= 2S oC unless otherwise noted)

Symbol

= V out • Pin 6 = GNO

S Input
Pin 2 = GNO. Pin 4
R S Input
Pin 2 = Vin. Pin 4

16 Vde. T A

= V sat • Pin 6 = Vin

= V sat • Pin 6 = Vin

Input Current
R Input
lin measured at Pin 2 with 4.0 Vde applied to Pin 2 and
Pin 6 grounded

S Input
lin measured at Pin 6 with 4.0 Vde applied to Pin 6 and
Pin 2 grounded
Output Sinking Current
Current into Pin 3 or Pin 4 with Q or

a. in low state

Drain Current
Pin 2 and 6 = GNO

FIGURE 2 - VOLTAGE TEST CIRCUIT

FIGURE 3 - CURRENT TEST CI RCUIT

150

a I--O---w___....

a

150

QI-~--------------~

I

FIGURE 4 -CIRCUIT SCHEMATIC
5

Vee

TRUTH TABLE

R

6

2
1

GND

7-596

S

R

S

Q

0
0
1
1

0
1
0
1

x
1
0
1

x - the state of Q is
undetermined

MFC8000
thru
MFC8002

"

HIGH-FREQUENCY CIRCUITS

\.._-------'

DUAL DIFFERENTIAL AMPLIFIER
(Stereo Input Amplifier)
MONOLITHIC DUAL STEREO AMPLIFIER

SILICON MONOLITHIC
CONSUMER CIRCUIT

... designed for the input stage of stereo power amplifiers.

•

Excellent Channel Separation - 60 dB minimum

• High Gain - hFE ~ 75 minimum
• Satisfies Both Channel Requirements with One Compact Package
• Selection of Breakdown Voltages to Meet the Particular
Applications

CASE 644A
PLASTIC PACKAGE

TYPICAL APPLICATION

r------------.--------------------~--------~~------------~

CHANNEL
"A" IN

-

y, MFC8000

v+

FEEDBACK "A"

.------------.----------.---------------4V·
y, MFC8000

CHANNEL
"8" IN

~-----------e--------------------~--------~~------------__ev+

See Packaging Information Section for outline dimensions.

7-597

I

MFC8000, MFC8001, MFC8002 (continued)

MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)
Symbol

Value

Unit

v+

40
50
60

Vde

PD

1.0

Watt

Derate above T A == 2SoC

10

mW/oC

Operating Temperature Range

TA

-10 to +75

°c

Rating
Maximum Supply Voltage - MFC8000

MFC8001
MFC8002
Power Dissipation (Package Limitationl
(Soldered on a circuit board)

-

ELECTRICAL CHARACTERISTICS (TA

=25°C unless otherwise noted)

Collector-Emitter Breakdown Voltage
flC = 1.0 mAde, IB = 0)

Min

Typ

Max

40
50
60

-

-

hFE

75

100

-

-

-11 VBE21

-

-

15

mVde

-

-

1.0

/lAde

60

-

-

dB

Symbol

Characteristic

MFC8000
MFC8001
MFC8002

DC Current Gain
(VCE = 20 Vde, IC = 1.0 mAde)

III VBE3

Base Differential Voltage
(VCE = 20 Vde, IC = 1.0 mAde)

Unit

Vde

BVCEO

-

lav8E8 - aVBE71

Base Differential Current
(VCE = 20 Vde, IC = 1.0 mAde)

II1IB 3-I1IB21
II1IB 8 -I1IB71

Channel Separation
(Pins 2,3,8 grounded, signal at pin 7,
Bout 1 at pin 6, Bout 2 at pin 4)

9 0u t

1

80UI-2

CIRCUIT SCHEMATIC

I

~5
680

680
4

y

~6

e>------<

~'
2

!I

7-598

8

l . . _____

A_U_D_I_O_P_O_W_E_R_A_M_P_L_1F_I_E_R-----.J

MFC8010

l-WATT AUDIO POWER AMPLIFIER

l-WATT
AUDIO POWER AMPLIFIER

· .. designed to provide the complete audio system in television, radio
and phonograph equipment.
•

Silicon Monolithic
Functional Circuit

One Watt Continuous Sine Wave Power at +55 0 C

•

High Gain - 10 mV (Max) for 1 Watt'

•

Extremely Low Distortion - 1% @ 1 Watt (Typ)'

•

Economical 8-Lead Plastic Package

•

Short-Circuit Proof (Short Term)

•

No Special Heat-Sinking Required

*Circuit Dependent.

CASE 644A
PLASTIC PACKAGE

MAXIMUM RATINGS (T A

= 25 0 C unless otherwise

noted)
Symbol

Value

Power Supply Voltage

v

22

Vdc

Power Dissipation @ T A - 25°C
(Package Limitation)
Derate above T A =: 25°C

PD

1.2

Watt

10

mW/OC

-1010+55

-Vc

Rating

1/8JA

Operating Temperature Range

UOit

FIGURE 1 - TYPICAL l-WATT AUDIO POWER AMPLIFIER CI RCUIT

v+ ~ 16 Vd, . - . - - - - - - - - - . . . , - - - - - - - - ,

r-t~. ~16"
R4

N

10 k

f5

1.U M

'7

~'"

6

P

t" , : ~r:l:c l~lO"F:
=

NOTE:

=

=

C2

pF
U

pF

R1
kohms

R2
ohms

ohms

10

100

0
100

10
51

10 k
100

R3
81
1.1 k

FI

---1f---.__-----i--o-,..-----i
0.1 "F

C1

4UU

mV

+ C3
5UU"F

I[
200

Sensitivity For
1 Watt

=

Dependent upon lead lengths, printed circuit board layout and output loading, a stabilization network conSist-

Alternate connection to permit connecting speaker to
ground instead of to V+:
V+

X
-

ing of a 0.1 ,uF capacitor in series with a 10 ohm resistor
may be required from pin 8 to ground.

Tn Pin 6

See Packaging Information Section for outline dimensions.

7-599

To Pin 8

MFC8010 (continued)

ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Circuit

'DV+=16Vdc

Symbol

Min

Typ

Max

Unit

Quiescent Output Voltage

Vo

7.0

8.0

9.0

Vde

Quiescent Drain Current

ID

-

10

18

mAde

Sensitivity. Input Voltage

Bin

-

-

10

mV

-

1.5

5.0

-

1.0

1.5

-

5.0

-

Characteristic

J:t
1

10 k

fl00.F 1.0M
4

6

,/

1.2 M

.F

1'00'

1

2

8

3r'~~k
82

~

Va

~

1

1.0k

~'0.F

V+"'16Vdc

~~16[

lein adjusted for Yout =4.0 V(rms)
: LOAD
J

@ 1.0 kHz, Power Output = 1.0

Wattl

to k

100.FI

1.0M

4

'If'I..
;, - I
I~

f = 1.0 kHz

~

1.2M

pF

rZ7

?l:
6

r:1,l ·
"'-

o., • F

1

2.2 k

500
.F

Total Harmonic Distortion

THD

(Vout = 4.0 Vrms@ 1.0 kHz,

%

Power Output = 1.0 Watt)
5,.

(Vin adjusted for Vout = 2.8
Vlrms) @ 1.0 kHz, Power
Output = 500 mW)

~

AV::::::500

100

:J

10.F

Output Noise
lein = 0)

FIGURE 2 - CIRCUIT SCHEMATIC

7-600

enlout)

mV

MFC8010 (continued)

FIGURE 3 - DISTORTION
4. 0

~
z
o

~

o

FIGURE 4 - DISTORTION
4.0

)= 16V~C
-16 Ohm Load

)= 12V~C

I--B Ohm load

3. 0

0

to

is

l -I'-- t--!Y~OO

'-'

Z 2. 0
~
~

o

0

II-- I--

~

6"">g

AV - 500

l. 0

I'-- r-

.0

AvLo

>0

r-

0
0.2·

O.B

0.4
0.6
po. OUTPUT POWER (WATTS)

- I--r-

10

AV
1.0

0.2

FIGURE 5 - EFFICIENCY

0.4
0.6
Po, OUTPUT POWER (WATTS)

__1-

Con~inuous~perati~n not

I

I

recommended at these levels.

f = 1.0 kHz

0
5

THO~10%1

I

0

0

j;

0
RL'" 16 Ohms, V+ '" 16 Vdc

r.:-

I/i--'

20

30

5V

~ I--'"
AL =8.0 Ohms, V+= 12 Vdc

I I

Ot-'
10

50

100

200

1.0

300

500

BOh~~ V

-

./' V

",

I

V

L

/V

_l-

O.B

FIGURE 6 - POWER OUTPUT

2.0

100

0

t:::::

L

L

16 Ohms

./

V

0

1000

B.O

10

12

14

V+, SUPPLY VOLTAGE (VOL TS)

Po, OUTPUT POWER (mW)

7-601

16

IB

I

L...---..o'f MFC8020A

~__________________A_U_D_I_O_D_R_I_V_E_R_S~

MFC8021A
MFC8022A
CLASS B AUDIO DRIVERS
SILICON MONOLITHIC
FUNCTIONAL CIRCUITS

CLASS B AUDIO DRIVERS
· .. designed as preamplifiers and driver circuits for complementary
output transistors.
•
•
•
•
•

Driver for Auto Radios - and up to 20-Watt Amplifiers
High Gain - 7.0 mV for 1.0 Watt, RL = 3.2 Ohms
High Input Impedance - SOO-Kilohm Capability
Output Biasing Diodes Included
No Special hF E Matching of Outputs Required

MAXIMUM RATINGS ITA" +250 C unless otherwise noted I
Rating

MFCB020A

Value
MFCB021A

MFCB022A

Unit

20

45

Vdc

Power Dissipation
Derate above T A = +250 C

35
1.0
10

1.0
10

1.0
10

Watt
mW/oC

Peak Output Current (pins 5 & 8)

150

150

150

mA

-10to+75

-10to+75

-10 to +75

°c
°c

Power Supply Voltage

Operating Temperature Range
Storage Temperature Range

CASE 644A

-55 to +125 -55 to +125 -55 to +125

THERMAL CHARACTERISTICS
Value

Unit

Thermal Resistance

Characteristic

100

°CIW

Junction Temperature

125

°c

FIGURE 1 - CIRCUIT SCHEMATIC

I

See Packaging Information Section for outline dimensions.

7-602

PLASTIC PACKAGE

MFC8020A, MFC8021A, MFC8022A (continued)

ELECTRICAL CHARACTERISTICS

(TA = +250 C unless otherwise notedl (See Figure 21
Min

Typ

Max

MFC8020A
MFC8021A
MFC8022A

-

10
7.0
12

30

MFC8020A
MFC8021A
MFC8022A

-

89
32
126

112
40
160

Vce = 30 V, eo = 8.95V(RMSI, RL = 165 n

MFC8020A

-

0.7

5.0

Vce = 14 V, eo = 3.2V(RMS),RL =65n

MFC8021A

-

1.0

5.0

VCC = 40 V, eo = 12.65 V(RMSI, RL = 165n

MFC8022A

-

1.5

5.0

MFC8020A
MFC8021A
MFC8022A

-

89
87
90

-

-

27

-

-

18

-

-

15
7.0
20

-

Characteristic

o rai n

Current

(ein = 01
Vee = 30 Vdc
VCC = 14 Vdc
VCC = 40 Vdc

Unit
rnA

Sensitivity (PO = 1.0 Watt, f = 1.0 kHz)
eo = 8.95 V(RMSI, RL = 165 n
eo = 3.2 V(RMSI. RL = 65 n
eo = 12.65 V(RMSI, RL = 165 n

-

-

30
30
rnV

-

%

Total Harmonic Distortion (f = 1.0 kHzl

dB

Open-Loop Gain

VCC = 30 V, RL =165 n
VCC=14V,RL= 65n
Vec = 40 V, RL =165 n

dB

Ripple Rejection
f = 60 Hz, Av '" 100, ein = 0, Power Supply

Ripple = 1.0 V(RMSI
J'V

Equivalent Input Noise

ein = 0, RS = 1.0 k n, BW = 100 Hz - 10 kHz

Vdc

Quiescent Output Voltage (ein = 0)

MFC8020A
MFC8021A
MFC8022A

Vec = 30 V
Vec = 14 V
Vee = 40 V

-

Symbols conform to JEDEC Bulletm No.1 where applicable.

FIGURE 2 - TEST CIRCUIT

270 k

+
IlO0PF

3.0 k
1N4002

10 J'F

----.:) 1---+---0-1
'in

t

1

100 pF

11'

270 k

=

orequiv

=
100 k
1.0 k

10

7-603

I

MFC8020A, MFC8021A, MFC8022A (continued)

TYPICAL AUTO RADIO AUDIO APPLICATION and CHARACTERISTICS
(T A - +250 C unl... otherwise noted.)
FIGURE 4 - TOTAL HARMONIC DISTORTION
versus OUTPUT POWER

FIGURE 3 - APPLICATION CIRCUIT FOR MFC8021A

10
82'

68'
'2

'1

111

~ 8.a

100

1'1

1= 1.0 kHz

II I OUTPUT DEVICE hFE
/I I--hFE=80

o

~
~ 6.a

~~'1------t---<~

'H

o

<.>

..
:J:

-'

2. 0

;:
o

I-

a

a

-hFE=50
hFE = 25

Z
~ 4.a

-

1.0

FIGURE 5 - TOTAL HARMONIC DISTORTION
versus FREQUENCY

~ i-'""
2.0

II 7
./ /I

'.J

3.0
4.0
5.0
OUTPUT POWER (WATTS)

6.0

7.0

8.0

FIGURE 6 - FREQUENCY RESPONSE

5.0

+5.0
+4.0

~
z 4.0

+3. 0

0

~

OdB = 2.0 WATTS AT 1.0 kH!

0

0

t; 3.0

0

Po = 1 WATT
hFE = 50

0
<.>

Z

'"a:..
0

..

2.0

:J:

-'

I0
I-

1.0

50

I

-

100

200

a
a

V

-3.0
-4. a
-5. 0

500
1.0 k 2.0 k
FREaUENCY (Hz)

5.0 k

10 k

20 k

APPLICATIONS INFORMATION for MFC8021A
(AUTO RADIO AUDIO)

50

100

200

500

1.0 k 2.0 k
5.0 k 10 k
FREIlUENCY (Hz)

20 k

50 k

FIGURE 7 - PRINTED CIRCUIT BOARD for AUTOMOTIVE
RADIO AUDIO 10-and·20 WATT AMPLIFIERS (COPPER SIDE)

The MFCB021A combines all the voltage gain required for an
automotive radio audio amplifier into one package reducing the
circuit-board area requirement. The circuit shown in Figure 3
has an input sensitivity of approximately 7.2 millivolts for a one'watt output. Sensitivity can be adjusted by changing the value of
R4- The circuit performance is a function of the output device
hFE, as shown in Figure 4. Figure 4 can be used to determine the
minimum hFE of the output transistors. The bandwidth of the
amplifier is determined by the capacitor, Cl. If Cl is increased to
390 pF the high frequency 3.0 dB point is typically 20 kHz.
An illustration of the copper side of the printed-circuit board
layout is shown in Figure 7. The output transistors are mounted
on the heatsink which for auto radio audio applications should have
a maximum thermal resistance of 1SOC/W for each device or
9.0o CIW when both output transistors are mounted on the same
heatsink.

7-604

MFC8020A, MFC8021A, MFC8022A

(continued)

TYPICAL 10-and-20WATT AMPLIFIER APPLICATION AND CHARACTERISTICS
IT A = +250 C unless otherwise noted.)
f'lGURE 9 - TOTAL HARMONIC DISTORTION
•
versus OUTPUT POWER

FIGURE 8 - APPLICATION CIRCUIT for
MFC8D2DA/and MFC8D22A
Vee

10

.n
810k

~

"

z

"

o

II
1= 1.0 kHz

I

8. 0

I

;:::

'B'

a:

~

o

~II-F+-_---i_-o.-l

~

....

6.0

Z

o

~

~
;:'

4.0

<[

-'

g
2.0
....

RS"f.ltSl
Re"O.33!1
Vee'JOV
20-WIlIAmphllll'
RB-4.7kfl

RE-O.4JU
VCC- 4lIV

1.0

0.5
lSaleuClI0pro.id.desirrdhindw,dlh,

Cl-41pFminimum.l

FIGURE 1D - TOTAL HARMONIC DISTORTION
versus FREQUENCY

z

o

'--

1/

10

20

1111

odB =2.0 WATTS at 1.0 kHz

~ +2.0

;; +1.0

1. 5

~
~

Z

o

~

II

+3.0

k
hFE =50

Po 12.o

~

;:'

:;a

II IIII

+4.0

o

~
....

2.0
5.0
OUTPUT POWER (WATTS)

+5.0

2. 0

I-~ f--

FIGURE 11 - FREQUENCY RESPONSE

2. 5

~

'-'--

~

s

:r
10·WmAmpllhl'

I--?1-"....

~

::,

~ -1.0

1.0

....
g

<[

:r
-'

g
O. 5
....

-2.0
-3.0

1

-4.0
50

100

200

500
1.0 k 2.0 k
FREQUENCY (Hz!

5.0 k

1.0 k

-5.0
20

20 k

50

100

200

500
1.0 k 2.0 k
FREQUENCY (Hz)

5.0 k

APPLICATIONS INFORMATION for MFC8D2DA and MFC8D22A
(lD,Watt and 2D,Watt Amplifiers)

The MFCB020A and MFCB022A are high,voltage parts capable
of driving 10-to-20 watt audio amplifiers. The gain of the circuit
shown in Figure 8 changes when the value of R4 is varied and the

where
8SA

= Heatsink thermal resistance

T J = Maximum junction operating temperature

bar"Jdwidth is determined by Cl. Emitter resistors are required at
the higher voltages used for 10-to-20 watt audio amplifiers to
provide thermal stability. The value of RE is a function of the
heatsink thermal resistance and supply voltage. The heatsink
requirements for operation at +65 0 C (with both devices mounted
on the same neatsink) is about 140 C/W for the 10·watt amplifier
and S.OoC/W for the iO-watt amplifier. If the maximum ambient
operating temperature is reduced then the heatsink can be reduced
in size as calculated by

8JS = Junction to heatsink thermal resistance
(includes all surface interface components for thermal
resistance such as the insulating washer)

Po = Maximum power dissipation of transistors
(This occurs at about 60% of maximum output power)
6.0 W for 10 W. 7.2 W for 12 W
TA

= Maximum ambient temperature

The printed circuit board layout is shown in Figure 7.

7-605

10 k

20 k

I

~J

MFC8030

l . . ____

H_IG_H_F_R_E_Q_U_E_N_C_y_C_I_R_C_U_IT_----I

DI FFERENTIAL/CASCODE
AMPLIFIER
DIFFERENTIAL/CASCODE AMPLIFIER

Silicon Monolithic
Functional Circuit

... designed for applications requiring differential or cascode amplifiers.
•

Extremely Flexible Amplifier

•

Diode Available for Biasing

•

Economical 8-Staggered Lead Package

CASE 644A

PLASTIC PACKAGE

MAXIMUM RATINGS (TA

= 250 C unless otherwise noted)

Rating

Power SupplV Voltage
Differential Input Voltage
Power Dissipation @TA

= 2SoC

Svmbol
V+

Value

Unit

20

Vdc

Vin

±5.0

Vdc

Po

1.0

Watt

1I8JA

10

mW/oC

TA

-10 to +75

°c

(Package Limitation)

Derate above 25°C
Operating Temperature Range

I
FIGURE 1 - CIRCUIT SCHEMATIC

Substrate

See Packaging I nformation Section for outline dimensions.

7-606

MFC8030 (continued)

ELECTRICAL CHARACTERISTICS ITA = 2SOC unless otherwise noted I
Circuit

Characteristic

~I-:':-+'------?---<:>-l~
1
rLAV'°VdC

~rDi~~(rms)

5U

-J,

/'

98

l.Ok

1 5

Min

Typ

Max

35

AC Common-Mode Rejection

Unit

dB

1.01;

7

f--4.3k

Symbol

lein)

CMR"'20Iog~

SOD

L--...e-a.aVdc
r-~VdC

r0-t-

3.Ok

:~

*

......Nv---O-'--1//
1.0k

dB

Differential-Mode Voltage Gain
J.Ok

AV Diff = 20 log

\:7~:

>-

1

5

r

4.3k

500

32

lein = 1.0 kHz, 1.0 mV[rmsll
lein = 10 MHz, 1.0 mV[rms])
lein = 50 MHz, 1.0 mV[rms] I

26
10

-S.OVdc

r-~VdC

f' -, //)- 1
3.0k

J

.f=t=~

100,'

1.01;

4.3k

ein -

-=

-=

1

Cascode-Mode Voltage Gain

3.Ok

AV Cascode '" 20 log

t

l'

~

5

36
31.5
15

lein'" 1.0 kHz, 1.0 mVlrmsl)

+r- 1

lODI'

(eo

dB

AV(cscdl

lein = 10 MHz, 1.0 mVlrmsl)
(ein = 50 MHz, 1.0 mVlrmsJ J

F

500

-6.DVdc

270

y~

~:'O'"<50mv.

«v:;.j ri::,/
3

220 Vio M) r-'

~II~

~

J.OVdc

l.Ok
_

4.3k

V

~8

:::

1 5

'6.0Vd,

5.0

Input Offset Voltage

10

7

500
~-6.0VdC

270

1 ~.7~.7'813~1".
_

10

_

2.1

-2.1

~II~

-

6

-

I
::.

~182~,/

V

220
l.Ok

J.OVdc

cj>8

'6.0Vd,

DC Current Gain Match

(101

15
7

_
4.31;

500

~-6.0VdC

7-607

=

1021

0.8

1.1

mV

1L_____________A_U_D_I_O_P_R_E_A_M_P_L_I_F_IE_R~

MFC8040

LOW NOISE
AUDIO PREAMPLIFIER

LOW NOISE AUDIO PREAMPLIFIER

Silicon Monolithic
Functional Circuit

· •. designed for high'gain, low·noise applications.
• Special Monolithic "State·of·the·Art" Process to Insure Low
Noise - 1.0 IlV (Typ)
• Can be Externally Equalized for NAB, RIAA
•

Low Distortion - 0.1 % (Typ)

•

Large Dynamic Range - 7.0 V (rms) Out

•

Low Output Impedance - 100 Ohms (Max)

@

AV = 100

CASE 644A

PLASTIC PACKAGE

MAXIMUM RATINGS (TA = 250 C unless otherwise noted)
Rating

Power Supply Voltage
Power Dissipation @ T A

Svmbol

Value

V+

33

Vdc

Po

1.0

Watt

1!6JA

10

mW!oC

TA

-10 to +75

°c

= 2SoC

Unit

(Package Limitation)

Derate above T A

= 2SoC

Operating Temperature Range

FIGURE 1 - TYPICAL WIDEBAND AMPLIFIER CIRCUIT IAV

I

1.0.F

~1-:+-_-00--1

270k

75 k

See Packaging Information Section for outline dimensions.

7-608

=60 dBI

MFC8040 (continued)

ELECTRICAL CHARACTERISTICS (TA

= 25°C unless otherwise noted)

Circuit

Characteristic

Drain Current

1.0~F

Symbol

Min

10

Typ

Max

8.0

12

rnA

<0.1

0.25

%

Unit

>--1
Vin "0

270k

75k

-=Total Harmonic Distortion

(va

1.0~F

THO

-

=1.0 V, f = 1.0 kHz)

>--)
Zin_

75 k

Input Impedance

Zin

75

k ohms

Output I rnpedance

Zout

100

ohms

Open Loop Voltage Gain
(Vin = 100"V(rms)@f= 1.0 kHz)

AVOL

-=-

Wideband I nput Noise
(-3.0 dB Bandwidth, 10 Hz to
16 kHz,AV= 60dB@ 1.0 kHz,

7-609

dB

80

1.0

3.0

"V
(rms)

I

MFC8040 (continued)

FIGURE 2 - CIRCUIT SCHEMATIC

FIGURE 3 - INPUT NOISE

FIGURE 4 - OPEN LOOP TOTAL HARMONIC DISTORTION

5.0

~

2.0

z

o

4.0

:;

o~
In

-AV=60dB

-3
w

'"
az

~
~

/

=

1.5

/

a
u
z

3.0

''""

L

i

~

;0
o

>-

1.0

0.5

V

a
'">-

o

/

./

~ 1.0

lL

2.0

0.1

f--O~EN
LOO~
RL 22 k ohms
V

V

0

0.3 0.5

1.0

3.0 5.0

10

30

50

100

4.0

2.0

RS. SOURCE RESISTANCE Ik ohms)

FIGURE 5 - AVAILABLE OUTPUT VOLTAGE

10

i

~
w

'"
~
~

- )JJdC
f = 1.0 kHz

B.O

_r6.0

V

>-

5

..... 1-

,..

>-

~

4.0

w

~

"'
:5

;;: .2.0

~

o
1.0

6.0

Vo• OUTPUT VOLTAGE IVlrmsll

2.0

3.0

5.0

10

20

RL, LOAD RESISTOR Ik ohms)

7-610

30

50

100

B.O

"\

J-K FLIP FLOP

~------------'

MFC8050

J-K FLIP-FLOP
· .. designed for use in high·level, low·speed logic and timing systems.
• Wide Operating Voltage Range - 4.0 to 16 Volts
•

J-K FLIP-FLOP
Silicon Monolithic
Functional Circuit

Regulated Supply Not Required

• Compatible with TTL and DTL
• J and K Inputs Allow Control of Desired State
•

Direct Clear (Col Allows Reset to Zero at Any Time

MAXIMUM RATINGS
Symbol

Value

Volts

Power Supply Voltage

Vee

19

Vdc

Output Sinking Current

Isink

10

mA

Negative Input Voltage

Vin

0.5

Vdc

PD
1/0JA

1.0
10

mwtDe

TA

-1010+75

°e

Rating

Power Dissipation @ T A

= 2SoC

Derate above 2SoC
Operating Temperature Range

TYPICAL APPLICATION - DIVIDE BY 3 CIRCUIT

Watt

CASE 644A

OUTPUT

INPUT ~r---C"'"

CLEAR

CASE 644A

BLOCK DIAGRAM

CIRCUIT SCHEMATIC

Q

Co

Vee =Pin 3
GND =Pin 1

See Packaging Information Section for outline dimensions.

7-611

MFC8050

(continued)

ELECTRICAL CHARACTERISTICS (Vin = 4.0 V, Square Pulse, f = 10 kHz, 50% Duty Cycle, tf = 1.0 VI/ls (Min),
T A = 250 C unless otherwise noted)
Svmbol

Min

Typ

Max

Vee

4.0

-

16

Vde

Toggle Frequency

fTog

-

3.0

-

MHz

Output Voltage (High)
(Vee = 4.0 Vdc)

VOH
3.5

-

15.5

-

-

-

0.5

-

-

1.0

-

20

mAde

5.0

-

mAdc

250

-

ns

350
60

-

ns

Characteristic
Operating Power Supply Voltage

= 16 Vdc)

(Vee

Output Voltage (Low)
(Vec = 4.0 Vdc)

= 16 Vdc)

(Vee

ID

Output Sinking Current

Isink

Vdc

Vdc

VOL

Operating Drain Current

Unit

(Vo '" 1.0 Vdc)
Rise Time

tr

Storage Time

ts

Fall Time

tf

I nput Resistance

Output Resistance ·(Output High)

-

ns

Rin

10

-

-

kn

ROH

-

-

2.8

kn

INPUT PULSE REQUIREMENTS
Characteristic
VH

VL

J
-

Symbol

TRAILING
EDGE

UEADING
EDGE

tn

dv

Trailing Edge

1
1
0
0

t"+l

K
1
0
1
0

a
an
1
0
an

dt

Explanation
a
an
0
1
On

No change in output

Set to a = 1 state regardless of orevious historv
Set to a = 1 state regardless of previous history
Output reverses (toggle action)

tn = time period just before and during the negative transition of the clock pulse (Pin 5).

tn+1 :; the time subsequent to that transition.
Q n = state of the

a

Unit
Volts
Volts

No Requirement

TRUTH TABLE

J

Max

+1.0

Zero Level

Leading Edge

O~--------------

Min

+4.0

Pulse Magnitude

-

output in time period tn-

7-612

-1.0

Volts
/lS

,-----"f

~~___________Z_E_R_O__V_O_L_T_A_G_E_S_W_I_T_C_H~

MFC8070

ZERO VOLTAGE SWITCH
... designed for use in ac power switching applications with output
drive capable of triggering triacs. Other operational features include:

ZERO VOLTAGE SWITCH

_ A built·in voltage regulator that allows direct ac line operation

Silicon Monolithic
Functional Circuit

._ A differential input with dual sensor inputs capable of testing the
condition of two external sensors and controlling the gate pulse to
a triac accordingly. Hysteresis or proportional control to this
section may be added if desired.
- Sensor input "open and short" protection. This insures that the
triac will never be turned "on" if either of the sensors are shorted
or opened.
- A zero crossing detector that synchronizes the triac gate pulses with
the zero crossing of the ac line voltage. This eliminates radio fre·
quency interference (rfiJ when used with re.sistive loads.
Typical Applications Include:
- Heater Controls
.• Photo Controls

- Valve Control
- ON·OFF Power Controls

- Threshold Detector - Relay Driver
- Lamp Driver

PLASTIC PACKAGE

- F lasher Control

CASE 644A

MAXIMUM RATINGS
Symbol

Value

Unit

DC Voltage

V5·8

15

Vdc

DC Voltage

V4-8

15

Vdc

DC Voltage

V7-8

15
1.0

Vdc
Watt

10

mW/oC

Rating

Power Dissipation @TA = 25°C

Derate above 2SoC

Po
1/9JA

Operating Temperature Range

TA

-10 to +75

Storage Temperature Range

T stg

-55 to + 150

See Packaging Information Section for outline dimensions.

7-613

uc
°c

I

M FC8070 (continued)

ELECTRICAL CHARACTERISTICS

(TA

= 250

C unless otherwise noted)

Characteristic

JII

r

r--91k

+

Vs

l~~

l

10 k
2 Watt

120 V+S) 60 Hz

SW111-

MFC807o

rp~
T
SW 1

B2

J.---

r

l

~4on
~ ~ lOp

MFC807o 3

-1,.
8k-

9.1 k

;j'

IDO 360
"F

9.1 k

~~
SWI

7

J

40n
I lOS
•

-=-I

8

Vref
+10mV

Vdc

6.0

8.5

Vdc

B k'"

mA

50

-10 mV
T A.

TB

-100 mV

70

JlS

11

lOS
Input Short Protection
(Sw.l:A;Sw.2:B)

5.0

100

-

"A

~

1-:---c-=--,-::--.-....".--+--:-----i--+--::-::---+----:c=-+---:---1

BSW21 MFC807o
B
2
t<'-3---iV re f

.!

VSP

Vref
+100 mV

(SW. 1: A or B)
Output Pulse Width
(SW. 1: A or B)

8k

6

15

~P-UI~~-T~hr-e~sh~0~I~d------1~v7T-P----r-----~r-~V~re-f--r--U-Vlre~f--+--"v.~a,c--;

(See Figure

45

JlA

5.0

Peak Output Current
(SW. 1: A or B)

Vref

8

r-->.A

100

(Sw. 1: A or B)

II'tI-I_20_V_'1..L':m_sl_60_H.z------1 VIOl

12-~

Typ

(Sw. 1: A or B)

~~J4on
7
~loL

~

VTI .O!-<).

IDO 360
"F
9.1 k

Min

Vs with I nhibit Output

360

9.1 k

Symbol

I nput Short Protection
(Sw. 1: B; Sw. 2: A)

lOS

-

5.0

100

8k

FIGURE 1 - OUTPUT PULSE DEFINITION

FIGURE 2 - CIRCUIT SCHEMATIC
Ground

Collector
Reference

Input

Input

-VS

7-614

JlA

MFC8070 (continued)

FIGURE 3 - CIRCUIT FOR MEASURING
OUTPUT PULSE WIDTH versus SOURCE
RESISTANCE

FIGURE 4 - OUTPUT PULSE WIDTH
versus SOURCE RESISTANCE
500

Suggested circuit to vary output pulse
width by value of RS (See Figure 4)

40 0

Pulse 0 utput
0

l/

0

-

10 0

IN5240
OA EQUIV
Vz = 10 V

f.- fRref

A2

r- r--

L

o
4.0 k

6.0 k

10 k

20 k

30 k 40 k

60 k

100 k

AS. PROGRAM RESISTOR (OHMS)

TYPICAL ZERO VOLTAGE SWITCH APPLICATIONS FOR TRIAC CONTROL

FIGURE 6 - TRIAC CONTROL CIRCUIT
WITH CURRENT BOOST UTILIZING
DC SUPPLY

FIGURE 5 - TRIAC CONTROL CIRCUIT

Al
100"F +
15Vdc
120Vlrm,)
60 Hz

Rref

Al

3

8V
DC
SUPPLY

lor2
R2

Rref

A2

Basic DC trigger application using the input comparator
Basic triac trigger circuit utilizing the zero crossing
to control a PNP capable of furnishing gate drive of
detector and the input comparator to control the
approximately 0.5 Amp.
gate of the triac.
A1 is an external sensor
R2 must be the external sensor for the internal short and open protection to be operative.
FIGURE 7 - TRIAC CONTROL CIRCUIT WITH CURRENT BOOST UTILIZING AC SUPPLY

Recommended Motorola triacs for use in circuit.
10k

Zero crossing triac control circuit for gate current
requirements greater than 50 rnA.

7-615

Maximum Continuous

Triac

(Current (Amp Irms} )

Familv

10

2N6151/2N6153
(MAC 10)

90 (Plastic)

10

2N6139/2N6144
(MAC 1,2,3)

85,86,87L

30

2N6157/2N6165
(MAC 35, 36)

174,175

Case
No.

I

M Fe 8070(continued)

PIN COMPARISON OF MFC8070 AND GEL300F1 (PA424)/CA3059

-vs

•

INPUT

-vs

INPUT

OUTPUT

INPUT

OUTPUT

B+
B+

REFERENCE

GROUND

COLLECTOR

REFERENCE
GROUNO

COLLECTOR
GEL300F1/CA3059

MFC S070

COMPATIBLE PRINTED CIRCUIT FOIL PATTERN

1.

FOR MFC8070 FOR MFC8070, GEL300F1 (PA424) AND CA3059

s!JZ

.3

Number MFC8070

7~4

I

5~6~5
•

o Motorola Pin

6

7

• GEL300F1/CA3059 Pin Number

Foll patterns shown are intended to show pin-for-pin
interconnection. Any change in the number of components
is dictated by the requirements of the individual design .
The MFC8070 requires two external reference
resistors; one resistor between pin 3 and 5 and the
other between pin 3 and pin B.

7-616

~~_______________A__U_D_IO__A_M_P_L_IF_I_E_R~

MFC9020

2-WATT AUDIO AMPLIFIER
2-WATT
AUDIO AMPLIFIER

· .. designed to provide the complete audio system in television, radio
and phonograph equipment.
•

2-Watts Continuous Sine Wave Power

•

Minimal Heat-Sinking Required for Operation

@

TA

Silicon Monolithic
Functional Circuit

= 55 0 C

o Short Circuit Proof (Short-Term)
o High Gain - 200 mV for 2·Watts Output Power
•

High I nput Impedance - 500 k Ohms

MAXIMUM RATINGS (TA = 25 0 C unless otherwise noted)
Rating

Symbol

Value

Power Supply Voltage

V+

24

Vdc

Output Peak Currer:lt

Ip

1.05

Amperes

Maximum Power Output
T A = 5SoC (Free Air Mounting)

Po

2.0

Watts

Symbol

Max

Unit

BJC

10
100

°CIW
mWloC

eJA

60
8.0

°CIW
mWloC

Unit

HERMAL CHARACTERISTICS
Characteristic
Thermal Resistance (Junction to Tabl

Derate above 2SoC
Thermal Resistance (Junction to Ambient) (1)
Derate above 2SoC

CASE 641
PLASTIC PACKAGE

(1 )Thermal resistance is measured in still air with fine wires connected to the leads, representing the "worst case" situation.
For a larger power requirement. the tab (pin 9) must be soldered to at least one square
inch (effective areal of copper foil on the printed circuit board. The 8 JA will be no
greater than +45 0 C/W. Thus, 2.0 Watts of audio power is allowable under "worst case"
conditions at an ambient temperature of +65 0 C. which must be linearly derated at 22.2
mW/oC from +65 0 C to +150 0 C.

FIGURE 1 - TYPICAL CIRCUIT APPLICATION

R8

1.0M

v+ =22 V
12k

RIO

330pF

C5

2.2M

RJ

See Packaging Information Section for outline dimensions.

7-617

MFC9020 (continued)

ELECTRICAL CHARACTERISTICS (v+ = 22 Vdc. TA = 25°C unless otherwise specified)
Min

Quiescent Drain Current

10

-

12

20

rnA

O.l.u

Sensitivity

ein

-

-

200

mV

Unit
Vdc

10

vt

1.0M

r-~12Vk~~'_60_Jl~" r-_(e_in_=__O}____________-i_______+------+-----~------_+----__4

,JL

180k

Typ

Quiescent Output Voltage

"1 r

Max

Symbol

Characteristic

Circuit

F

10M

ro-1~-_.....<'7)-'-li'-4 ~L3°L
INPU+~"
-

150,'

Input Voltage

(eo =4.0 V(rms) @1.0kHz.
Po =2.0W}

,,~± ~'i ·~~

Total Harmonic Distortion
(Po

= 2.0 W.

THO

%

1.0 kHz)

(Po = 100 mW. 1.0 kH z)

Hum and Noise *

1.0

10

1.0

3.0

dB

-40

1.3 M

·'HF STANDARD IHF-A-2011966

Performance Curves for Circuit Shown Above.
FIGURE 3 -POWER DISSIPATION

FIGURE 2 - TOTAL HARMONIC DISTORTION
1.0

1.0

6

u;

1.6

>-

f = 1.0 kHz

0>

i

~ 1.2

o

~

>-

'"

u

Z

~ 0.8
~

:="">-

--l-

........ ......

0>

0.4

./
,.../'

~

v+ = 24 V

1.6

./'

./V
7'V

1.2

ill

~ 0.8
~

V

L-- e--

11

v

10 V

10-

//. /'

f = 1.0 kHz

y

~

~ 0.4

~.

>-

o
o

0.4

0.8

1.1

1.6

o
o

1.0

po. OUTPUT POWER (WATTS)

0.4

0.8

1.1

1.0

1.6

po. OUTPUTPOWER (WATTSI

FIGURE 5 - CIRCUIT SCHEMATIC

FIGURE 4 - TOTAL HARMONIC DISTORTION
1.0

1.6
Po =2W

I.1

I-

o. 8
o. 4

o
100

100

500

1.0 k

1.0k

5.0k

10k

-o'.2.9

L-_ _ _ _ _ _ _ _ _ _ _.....

f. FREQUENCY (Hz)

7-618

MFC9020

(continued)

Applications Information for Circuit Shown in Figure 1.
FIGURE 6 - ALTERNATE SPEAKER CONNECTION
FOR SPEAKER TO GROUND

Figures 7 thru 11 pertain to the 2-watt amplifier with a 16-ohm load
connected to V+ as shown in Figure 1. The sensitivity of this amplifier is approximately 250 mV and the input impedance at 100 Hz
is approximately 800 k ohms. R7/R5 determines the approximate
gain that can be best altered by changing the value of RS and holding R7 to a large value. This allows the use of a smaller and less expensive capacitor for C2.

6.8 k
6.8 k

The speaker can also be connected to ground as shown in Figure
6, and the printed circuit board art work is shown in Figure 13.
The maximum operation voltage for the amplifier should reflect a
consideration of at least a 10% high-line condition. Under highline conditions, the power supply voltage should be less than the
maximum rating of the device.

FIGURE 7 - TOTAL HARMONIC DISTORTION

FIGURE 8 - POWER DISSIPATION

1.0

~
z
0

1.0

~
z

0.8

0

0.6.

0

~ 0.75

~

0

to

0

u

~
~
~

.......

i'-

V+~22V

Po

;;; 0.50
~
~

2W

0

0.4

.......

g

...

v+ ~ 22 V
f ~ 1.0 kHz

i'-.

u

~

~

0

\

to

0

0.2

0.25

e"
:c

...

0
100

0
500

200

1.0 k

2.0 k

5.0 k

10k

0

0.4

0.8

1.2

1.6

2.0

po. OUTPUT POWER (WATTS)

f. FREUUENCY (Hz)

FIGURE 9 - FREQUENCY RESPONSE
50

40
V+~22V

'"
z

30

'"

20

;;:

Po

-

~

500 mW

r-- rFull
Treble Cut

r-..

r---....

10

20

50

100

200

500

1.0 k

f. FREQUENCY (Hz)

7-619

2.0 k

5.0 k

10 k

20 k

MFC9020 (continued)

FIGURE 10 - PRINTED CI,RCUIT BOARO
1:1 PATTERN (Speaker to V+I

FIGURE 11 - COMPONENT DIAGRAM FOR FIGURE 10

FIGURE 12 - COMPLETED BOARD
(Speaker to V+I

FIGURE 13 - PRINTED CIRCUIT BOARO
1:1 PATTERN (Speaker to Groundl

7-620

'\

MHP401

MaS CLOCK DRIVER

'---------

TTL TO MaS CLOCK DRIVER
HYBRID CIRCUIT

TTL to MaS
CLOCK DRIVER

· .. designed for medium to high capacitive loads.
•

High Operating Voltage - V2 -V1 = 32 Vdc (Maxi

•

High Clock Rates - 5.0 MHz (Maxi

•

Fast Switching Times - (Typi

HYBRID CIRCUIT

RS
Ohms

tpLH

tTLH

tpHL

tTHL

pF

ns

ns

ns

ns

500
1000
2000

0
5.0
10

10
13
19

30
40
67

21
23
28

28
35
69

CL

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

V2 -V1

32

Vdc

V1

-3.0 to -32

Vdc

Po

2.0
44

Watts

TJ

o to +70

Storage Temperature Range

T stg

-55 to +150

°c
°c

Thermal Resistance, Junction to Ambient

eJA

0.022

°C/mW

Operating Voltage
Negative Supply Voltage

Total Device Dissipation
Derate above 2SoC

@

T A = 2SoC

Operating Junction Temperature Range

mW/oC

CIRCUIT SCHEMATIC

14

6,10

B,9

Vee

0.710

V2

V2'

----------j

[---0.740;-]

n n

I

R3
Rl

7
Vo
4,5

[11

Rx

R2

R4

I -IL-1I.cQ.li
1-+11-

-=

0.020

'Dimension is to lead centerline when formed parallel

11

Pins 2,3 and 12 are connected internally and
must be electrically isolated.

CASE 646

See Packaging Information Section for outline dimensions.

7-621

I

I

MHP401 (continued)

ELECTRICAL CHARACTERISTICS (TA

~ 25°C unless otherwise noted)

All pins not characterized on this table must be electrically open and isolated from each other for each test, Pin 1 is grounded for all tests.
Characteristic

STATIC CHARACTERISTICS (VCC

~ 5.25 Vdc, Vl ~ -29 Vdc)

Input Forward Current (1)
~

(Vin

Input Leakage Current (1)

(Vin

~

IlL

-

-

1.6

mA

IIH

-

-

100

I'A

ICCL
ICCH

-

-

20
15

0.4 Vdc)
5.5 Vdc)
mA

Power Supply Drain Current (1)
(Vin ~ 0.4 Vdc)
(Vin ~ 2.4 Vdc)

-

~ 5.0 Vdc, Vl ~ -12 Vdc, V2 ~ V2' ~ +5.0 Vdc, CL ~ 1000 pF,
5.0 Ohms, 2.0 Watts, Figure 1)

DYNAMIC CHARACTERISTICS (V in supplied by MC7400, VCC
RS

~

15

-

-

Vdc

Turn-On Time (2)

ton

-

-

75

ns

Turn-Off Time (2)

toff

-

-

75

ns

Output Voltage Swing (2)

VOH-VOL

SWITCHING TIMES (Vin supplied by MC7400, 1.0 MHz, 20%)
Delay Time
Vl ~ -12 Vdc, V2 ~ Vi ~ +5.0 Vdc
(CL ~ 500 pF, RS ~ 0)
(CL ~ 1000 pF, RS ~ 5.0 Ohms)
(CL ~ 2000 pF, RS ~ 10 Ohms)
Vl

-

-29 Vdc, V2 ~ V2' ~ Gnd
(CL ~ 500 pF, RS ~ 0)
(CL ~ 1000 pF, RS ~ 5_0 Ohms)
(CL ~ 2000 pF, RS ~ 10 Ohms)

-

12
16
23

-

30
40
67

-

-

ns

tTLH

-

-

Storage Time

41
54
89

-

-

ns

tpHL

~ -12 Vdc, V2 = Vi ~ +5.0 Vdc
(CL ~ 500 pF, RS ~ D)
(CL = 1000 pF, RS = 5.0 Ohms)
(CL ~ 2000 pF, RS ~ 10 Ohms)

-

= -29 Vdc, V2 ~ Vi ~ Gnd
(CL = 500 pF, RS = 0)
(CL = 1000 pF, RS ~ 5.0 Ohms)
(CL = 2000 pF, RS ~ 10 Ohms)

-

-

Fall Time
Vl = -12 Vdc, V2 = Vi ~ +5.0 Vdc
(CL ~ 500pF, RS ~ 0)
(CL = 1000 pF, RS ~ 5.0 Ohms)
(CL ~ 2000 pF, RS = 10 Ohms)
Vl

10
13
19

~

Vl ~ -29 Vdc, V2 ~ V~ ~ Gnd
(CL = 500 pF, RS = )
(CL ~ 1000 pF, RS = 5.0 Ohms)
(CL ~ 2000 pF, RS = 10 Ohms)

Vl

-

-

-

Rise Time
Vl ~ -12 Vdc, V2 ~ Vi ~ +5_0 Vdc
(CL ~ 500 pF, RS ~ 0)
(CL ~ 1000 pF, RS ~ 5.0 Ohms)
(CL ~ 2000 pF, RS ~ 10 Ohms)

Vl

ns

tpLH

21
23
28

-

22
25
32

-

-

ns

tTHL

= -29 Vdc, V2 = Vi = Gnd
(CL = 500 pF, RS = 0)
(CL = 1000 pF, RS ~ 5.0 Ohms)
(CL ~ 2000 pF, RS = 10 Ohms)

-

28
35
69

-

-

46
49
78

-

-

-

<

(1) Pulse Test: Pulse Width
50 ms.
(2) MC7400 used in test to be loaded with device under test only.

7-622

-

MHP401 (continued)

FIGURE 1 - SWITCHING TIME TEST CIRCUIT

Vcc = +5.0 V

JlJ1
1.0 MHz

20% Duty Cycle

Pins 2,3.4,5,12
Not Connected
+5.0 V

Vp-12 V

MAXIMUM OPERATING FREQUENCY

The following limits apply with the unit soldered to a printed circuit board and
force air cooled at T A = 25 0 C.
V2 -V1 = 17 Vdc
Maximum Frequency
@
@
@

500 pF and 20% Duty Cycle
1000 pF and 20% Duty Cycle
2000 pF and 20% Duty Cycle

5.0 MHz

4.0 MHz
2.0 MHz

Maximum Frequency
@ 500 pF and 20% Duty Cycle
@ 1000 pF and 20% Duty Cycle

3.0 MHz
1.5 MHz
1.0MHz

@ 2000 pF and 20% Duty Cycle

OPERATING CHARACTERISTICS
For best performance, all leads of the MHP401 should be soldered to a printed circuit board or substrate. This results in better
heat sinking.

Pins 2 and 3 may be common with each other, but must be electrically open and isolated from all other pins. Pin 12 must be
electrically open and isolated from all other pins.
Three pairs of pins in this package are used in circuit operation: V2' (Pins 8 and 9), V2 (Pins 6 and 10) and Rx (Pins 4 and 5).
Electrical connection to these points may be made at either pin or both. If electrical connection is made to only one pin of a pair,
the other pin must be left electrically open and isolated and should be soldered to the substrate for heat sinking.
Series resistance (RS) is for absorption of switching power ... failure to use it for loads over 500 pF may result in package
overheating.
RS

@

1000 pF = 5.0 ohms, 2.0 watts

RS @ 2000 pF = 10 ohms, 2.0 watts

DYNAMIC OPERATION
For dynamic operation, Vi (Pins 8 and 9) is tied to V2 (Pins 6 and 10) and Rx (Pins 4 and 5) is left electrically open and isolated.
If desired, Vi (Pins 8 and 9) may be left electrically open and isolated and an external 2.0 watt resistor to replace R 3 mey be tied
from Rx (Pins 4 and 5) to V2 (Pins 6 and 10).
For V2 -V, < 20 V, the maximum duty cycle is 50%; at V2 -V, =20 to 30 V, tha mexlmum dulY cycle is 20%. By replacing R3
with a 2.0·watt, 5QO-ohm resistor, the circuit may be operated in a static mode If the following conditions exist:
V,

~-13

V and V2 -V,

~30V

Or, R3 may be replaced with a 2.0-watt re.istor Ie.. than 500 ohms to speed fall time.

7-623

•

I

'\

OPERATIONAL AMPLIFIERS

'-----------

MLMIOIA
MLM201A
MLM301A

MONOLITHIC OPERATIONAL AMPLIFIER
The MLM lOlA, MLM201A, and MLM301A are functionally, electrically, and pin-for-pin equivalent to the LM101A, LM201A, and
LM301 A respectively.

•

Low Input Offset Current - 20 nA maximum Over Temperature
Range

•

External Frequency Compensation for Flexibility

OPERATIONAL AMPLIFIER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

G SUFFIX
METAL PACKAGE
CASE 601
(TO·99)

• Class AS Output Provides Excellent Linearity
• Output Short-Circuit Protection

Case connected to pin 4 through substrate

• Guaranteed Drift Characteristics

FIGURE 1 - STANDARD COMPENSATING
AND OFFSET BALANCING CIRCUIT
Pl SUFFIX
PLASTIC PACKAGE
CASE 626

INVERTING
INPUT

(M LM301 A Only)
OUTPUT

NON.INVERTING

3

5 BALANCE

INPUT

10MU

30pF

5.1 Mn

+----'lM-..

VEE

10 k

FIGURE 2 - DOUBLE-ENDED LIMIT
DETECTOR

FIGURE 3 - CIRCUIT SCHEMATIC

OUTPUT

VO=4.8Vfor
4

VEE

VLT";; Vin";; VUl
VO""*O.4V
Yin VUT

See Packaging Information Section for outline dimensions.

7-624

MLM101A, MLM201A, MLM301A

MAXIMUM RATINGS (TA

=

(continued)

+25°C unless otherwise noted)

VALUE
Rating

Power Supply Voltage

Differential Input Voltage

Symbol·

MLM101A

I

MLM201A

I

MLM301A

vcc,Vee

±22

1

±22

1

±IB

Vin

Common·Mode I nput Swing (Note I)

VICR

Output Short Circuit Duration

ts

Power Dissipation (Package Limitation)

Po

Metal Can
Derate above T A
Plastic

= +75°C

Dual In-Line Package

Oerate above T A

.

TA

For supply voltages less than

±

.
....

Continuous

...

500
6.B

T stg

..

+15

.

only)

Operating Temperature Range

Vdc

,..

±30

(MLM301A

= +250 C

Storage Temperature Range
Note 1.

.

..

-

625
5.0

-

·55 to +125

·25 to +B5

1

Unit

o to

1

+75

-65 to +150

Volts

Volts

mW
mW/oC
mW
mW/oC
C

.

°c

15 V. the absolute maximum Input voltage IS equal to the supply voltage.

ELECTRICAL CHARACTERISTICS (TA = +25 0 C unless otherwise noted) Unless otherwise specified, these specifications apply for
supply voltages from ±5.o V to ±2o V for the MLMlOlA and MLM201A, and from ±5.0 V to
±15 V for the MLM301A.
MLM101A
MLM201A

Characteristics

MLM301A

Symbol·

Min

Typ

Max

Min

Typ

Max

Unit

Input Offset Voltage (RS';;50 kll)

IVlol

-

0.7

2.0

-

2.0

7.5

mV

I "put Offset Current

11101

1.5

10

-

3.0

50

nA

I "put Bias Current

liB

30

75

-

70

250

nA

0.5

2.0

-

-

1.8

3.0

-

25

160

-

"put Heslstance

Rin

Supply Current
VS=±2ov
Vs = ±15 V

10

Large Signal Voltage Gain

AV

-

-

1.5

4.0

-

1.8

50

160

-

VS=:!:15V,VO=±10V,RL>2.0kn

-

3.0

Megohms

-

mA

V/mV

The followIng specifications apply over the operating temperature range.

Input Offset Voltage (RS';; 50 kn)

IVIOI

-

I nput Offset Current

11101

-

-

-

3.0

Average Temperature Coefficient of

I nput Offset Voltage
TA(min) ';;TA ';;TA(max)
Average Temperature Coefficient of
I nput Offset Current

liB
AV

-

Vin

Vs = ±2ov
Vs = ±15 V

nA

15

-

6.0

30

0.01
0.02

-

0.3
0.6

-

300

-

15

-

-

-

-

-

-

±12

BO

96

-

70

90

-

BO

96

70

96

-

±t2
±10

±14
±13

±12
±1O

+14
±13

-

1.2

-

-

Vo

10

100

0.01
0:02

-

PSSR

VS=±15V,RL=10kH
RL=2.0kH

-

'7

CMRR

RS';;50 kn

0.1
0.2

-

±15

RS';;50 kll

Isupply Current (TA = TAlmax), Vs = ± 20 V)

mV

70

nA/oC

25

Vs =:!: 15V, Va = ± 10 V, RL > 2.0 kn

Output Voltage Swing

10

-

jJ.V/oC

--

Input Bias Current

Supply Voltage Rejection Ratio

-

-

1f'.IIQIf'.TI

Large Signal Voltage Gain

Common-Mode Rejection Ratio

-

20

If'. V,OIMI

+25 0 C .;; T A ';;T A Imax)
T A(min)';; T A';; 25°C

I nput Voltage Range

3.0

·Symbols conform to JEDEC Engmeermg BulletIn No.1 when applicable.

7-625

2.5

nA
V/mV
V

dB
dB

-

V

-

mA

I

~f

MLMI04G
MLM204G
MLM304G

l . . ___

N_E_G_A_T_IV_E_V_O_L_T_A_G_E_'R_E_G_U_L_A_T_O_R---'

MONOLITHIC NEGATIVE VOLTAGE REGULATOR
The MLM104G, MLM204G, and MLM304G are functionally,
electrically, and pin·for·pin equivalent to the LM 104, LM204 and
LM304 respecitvely.
•

Regulation No Load to Full Load - 1.0 mV

•

Line Regulation - 0.01 %/V

•

Ripple Rejection - 0.2 mV/V

NEGATIVE VOLTAGE
REGULATOR
MONOLITHIC SILICON
INTEGRATED CIRCUIT
NOVEMBER1971 - OB·l03

• Temperature Stability Over Temperature Range - 0.3%

CIRCUIT SCHEMATIC

9

,--,-----..,..---f-------f"""1t""""4 GROUND

NO
CONNECTION
ADJUSTMENT
GROUND
REGULATED
REFERENCE '
OUTPUT
REFERENCE ,
BOOSTER
SUPPLY
COMPENSATION
' CURRENT LIMIT
UNREGULATED
INPUT
TOP
VIEW

2

REFERENCE

REFERENCE

4

SUPPLY

Pin 5 Electrically
Connected to Case
Through Substrate

COMPENSATION

METAL PACKAGE
CASE 603·02
(TO·l00)

TYPICAL APPLICATIONS
FIGURE 1 - BASIC REGULATOR CIRCUIT
~~---f--~--1~.GND

FIGURE 2 - SEPARATE BIAS
SUPPLY OPERATION

-GND

r----~p-,-~t---.....

FIGURE 3 - HIGH CURRENT REGULATOR
,---1~-..,..----_t--eGND

4.7 jJFt

'-----e--....- - . V i n
tSolid Tantalum
Trim Rt forexaci
scale factor.

tSolidTantalum
tSolidTantalum

See Packaging Information Section for outline dimensions.

7-626

MLM104G, MLM204G, MLM304G (continued)

MAXIMUM RATINGS (TA = +250 C unless otherwise notedl
Rating

Svmbol

MLM104G

MLM204G

MLM304G

Vin

50

50

40

Vdc

50

50

40

Vdc

680

mW

I nput Voltage
Input-Output Voltage
Differential

,

Vin-Vo

Power Dissipation (See Note 11

Po

/680

680

Operating Temperature Range

TA

-55 to +125

-25 to +85

o to +70

Storage Temperature Range

T stg

-65to,,+150

-65 to +150

-65 to +150

Lead Temperature

TS

300

300

300

'"

Unit

°c
°c
°c

(soldering, t = 10 sl

ELECTRICAL CHARACTERISTICS (See Note 21
Characteristic

Svmbol

Min

MLM104G
MLM204G
TVp

Max

Min

MLM304G
TVp

Max

Unit

Input Voltage Range

Vin

-8.0

-

-50

-8.0

-

-40

Volts

Output Voltage Range

Vo

-0.01-5

-

-40

-0.035

-

-30

Volts

-

50
50

2.0
0.5

-

40
40

-

1.0

5.0

-

1.0

5.0

-

0.056

0.1

-

0.056

0.1

Output-Input Voltage Dilferential
10=20mA
10= 5.0mA

IVin-Vol

Load Regulation
0";;;1 0 ";;;20 mA, RSC = 15.11

Regload

Line Regulation

Regin

Vo";;;-5.0V,6Vin=0.1 V
Ripple Rejection (See Figure 11
(Cl = lOjlF, I = 120 Hzl
Vin< -15V
-7.0 V;;' Vin;;' -15 V
Output Voltage Scale Factor
R 1 = 2.4 k .11 (See Figures 1,2 and 31
Temperature Stability
Vo";;; -1.0V
Vo";;; -1.0 V, DOC";;; TA";;; +700 C

RejR

Volts

mV
%

I,

mV/V

,cr.2

0.5
1.0

-

0.5

-

0.2
0.5

0.5
1.0

1.8

2.0

,2.2

1.8

2.0

2.2

'--

0.3

1.0

-

-

-

-

0.3

1.0

-,
-

-

0.007
15

-

1.7

2;5

1.7

2.5

-

-

3.6

5.0

-

-

-

-

3.6

5.0

-

0.1

1.0

-

0.1

1.0

'-

-

V/k.l1

SF
TCV o
6VO /6T

Output Noise Voltage (See Figure 11
(10 Hz";;; f";;; 10 kHzl
Vo";;; -5.0V,Cl =0
Cl=10jlF

Vn

Standby Current Drain (I L - 5.0 mA I
Vo=O
Vo=-40V
Vo=-30V

16

Long Term Stabilitv
Vo";;; -1.0V

S

Note 1.

-

2.0
0.5

I

-

-,

%

,

-

-

I, _

,0.007
15

-

%
jlV
mA

-

-

%

The maximum junction temperature of the MLM104G is +150 o C. for the MLM204G -

+100 o C. and for the MLM304G - +8SoC.

For operating at elevated temperatures. the package must be derated based on a thermal resistance of 1500 C/W - junction to ambient,
or 4SoC/W - junction to case.
Note 2.
These specifications apply for junction temperatures of - 5SoC to +150 o C for the MLM 104G; -2SoC to +1000 C for the MLM204G;
and 0 to +85 0 C for the MLM304G. The specifications also apply for input and output voltages within the indicated ranges (unless
otherwise specified). Load and line regulation specifications given are for constant junction temperature. Temperature drift effects
must be taken into account separately when the device is operating under conditions of high power dissipation.

7-627

I

I

MLMI05G
MLM205G
MLM305G

\

....._ _ _P_O_S_IT_I_V_E_V_O_LT_A_G_E_R_E_G_U_L_A_T_O_R.....J

MONOLITHIC POSITIVE VOLTAGE REGULATOR
The MLM10!iG, MLM205G, and MLM305G are functionally,
electrically, and pin-for-pin equivalent to the LM105, LM205, and
LM305 respectively_
• Output Voltage Adjustable from 4_5 V to 40 V
• Output Currents in Excess of lOA Possible by Addition of
External Transistors
• Load Regulation Better than 0.1%, Full Load with Current
Limiting
• DC Line Regulation, 0.03%/V
• Ripple Rejection, 0.01 %/V

POSITIVE VOLTAGE REGULATOR
MONOLITHIC SILICON
INTEGRATED CIRCUIT

fi
REGULATED OUTPUT

BOQSTERDUTPUT2

.

GROUND
Note Pm4connec'edtocaSli!
(TOP VIEW)

METAL PACKAGE
CASE 601
(TO·99)

TYPICAL APPLICATIONS
FIGURE 1 - BASIC REGULATOR CIRCUIT

47pF

"

FIGURE 3 - 1.0 A REGULATOR with PROTECTIVE DIODES
IN4001 QREQWVt

"

Al +R2

,--M---.,--,.-----,.-.,-....._evo = 28V

Vo

e-~~_+-~~C'~._____~-e~=U

31.

D.'

lN401l1 OR EQUIVt

1%

2N3055OR EOUIV

FIGURE 2 - 10 A REGULATOR with FOLDBACK CURRENT LIMITING
0.16
!i.55k

"

2.13k

",

J5V

"
tProtect$lllgainslshortedinpullJ1
inductive'oads(lnunregulated
wpply.
'PrOltclsagain$tinpulvollage
IlM'rsa!

iProlectsagain$loutpu,voltage
reverSiilI

=

tSolidTantalllm

-EtacITa'vlic

See Packaging Information Section for outline dimensions.

7-628

MLM105G, MLM205G, MLM305G (continued)

MAXIMUM RATINGS (TA

0

+25 0 C unless otherwise notedl
Symbol

Rating
I nput Voltage

Input-Output Voltage
Differential

MLM105G

MLM205G

MLM305G

Unit

Vin

50

50

40

Vdc

[Vin-Vo[

40

40

40

Vdc

680

mW

Power-Dissipation (See Note 11

PD

660

680

Operating Temperature Range

TA

-55 to +125

-25 to +85

StOI age Temperature Range

T sto

-65 to +150

Lead Temperature
(soldering, t 10 sl

TS

300

65 to +150

o to +70

°e

65to+150

°e
°e

300

300

0

ELECTRICAL CHARACTERISTICS (See Note 21
Characteristic

Symbol

Min

I nput Voltage Range

Vin

8.5

Output Voltage Range

Va

4.5

I Vin-Vol

3.0

Output-Input Voltage Differential

Load Regulation (See Figure 1)

MLM105G
MLM205G
Typ

-

-

Max

Min

50

8.5

40

4.5

30

3.0

MLM305G
Typ

-

Max

Volts

30

Volts

30

Volts

%

Regload

<10 <12 mAl
Rse ~ 18 !!, TAo +25 0 e
Rse 10 !I, TAo Thigh:.
Rse o18!!, TA - Tlow

Unit

40

(0

0.02
0.03
0.03

0.05
0.1
0.1

-

-

0.02
0.03
0.03

0.05
0.1
0.1

--

-

0.025
0.015

0.06
0.03

-

0.025
0.015

0.06
0.03

-

0.003

0.D1

1.0

0.003

0.01

0.3

1.0

-

0.3

1.0

1.7

1.81

1.63

1.7

1.81

0

Line Regulation

-

Vin-Vo < 5.0 V
Vin-Vo> 5.0 V
Ripple Rejection (See Figure 11
erel o 10 IlF, I" 120 Hz
Temperature Stability

%iV

Regin

/:'V o
Vn/:'V'
TeV o

%iV
%

Tlow** ~·TA ~ Thigh*
Feeciback Sens~ Voltage

Output Noise Voltage (See Figure 1 J

Vrel

(10 Hz < 1< 10 kHzl
eRel 0
eRel> O.lIlF
IS

Vin'-50V
Vin =40V
Long Term Stability

*Thigh -, +125 0 e lor MLM105G
+85 0 e lor M LM205G
+ 70 0 e lor M LM305G
Note 1.

S

Volts
%

0.005
0,002

-

-

0.005
0.002

-

-

0.8.

2.0

-

-

-

-

-

0.8

2.0

-

0.1

1.0

-

0.1

1.0

-

0

Standby Current Drain

1.63

Vn

mA

%

• 'Tlow" -55 0 e lor MLM105G
-25 0 e lor MLM205G
oOe lor MLM305G

The maximum junction temperature 01 the MLM105G is +150 0 e, lor the MLM205G - +100 0 e. and lor the MLM305G - tS5 0 e.

For operating at elevated temperatures, the package must be derated based on a thermal resistance of 150 0 C/W - junction to ambient,
or 45 0 C/W - junction to case.

Note 2.

These specilicationsapply lor junction temperatures 01 -55 0 e to +150 0 e lor the MLM105G. -25 0 e to +850 e lor the MLM205G.
and 0 to +70 0 C for the MLM305G. Specifications also apply for input and output voltages within the indicated ranges and for a divider
impedance sensed by the feedback terminal of 2.0 kilohms (unless otherwise specified). Load and line regulation specifications given are
for constant junction temperature. Temperature drift effects must be taken into account separately when the device is operating under
conditions of high power dissipation.

7-629

MLMI07G
MLM207G
MLM307G

~~_________O_P_E_R_A_T_IO_N_A_L__A_M_P_L_IF_I_E_R_S~

OPERATIONAL AMPLIFIER
INTEGRATED CIRCUIT

INTERNALLY COMPENSATED
MONOLITHIC OPERATIONAL AMPLIFIER
The MLM107G. MLM207G. and MLM307G are functionally.
electrically. and pin·for·pin equivalent to the National Semiconductor
LM 107. LM207. and LM307 respectively.
•
•

Internally Compensated
Low Offset Voltage: 2.0 mV max (MLM107G)

•

Low Input Offset Current: 10 nA max (MLM107G)

•

Low Input Bias Current: 75 nA max (MLM107G)

EPITAXIAL PASSIVATED

fi

TYPICAL APPLICATION
HIGH IMPEDANCE BRIDGE AMPLIFIER

Vo=-10Vin

METAL PACKAGE
CASE 601
TO·99

Pin 4 connected to case.

EQUIVALENT CIRCUIT

v+

7

Vout

See Packaging Information Section for outline dim/ilnsions.

7-630

MLM107G, MLM207G, MLM307G (continued)

MAXIMUM RATINGS ITA = +25 0 C unless otherwise noted)
Rating

Symbol

MLM10'1G

MLM207G

MLM307G

Unit

V+
V-

+:22
-22

+22
-22

+18
-18

Vdc

Vin

±!lO

±30

±30

Volts

CMVin

±15

±15

±15

Volts

Power Supply Voltage
Differential Input Signal
Common-Mode Input Swing INote 1)

Output Short Circuit Duration

Indefinite

TSC

Power Dissioation (Packaae Limitation) INote 2)

PD

500

500

500

mW

Operating Temperature Range

TA

-55. to +125

-25 to +85

o to +70

°c
°c

-65 to +150 -65 to +150 -65 to +150

T stg

Storage Temperature Range

ELECTRICAL CHARACTERISTICS TA = +250 C unless otherwise noted

See Note 3
MLM107.G
MLM207G

Characteristics

Min

Symbol

Input Offset Voltage

MLM307G

Typ

Max

0.7

2.0
3:0

-

-

Min

Typ

Max

-

-

-

.-

2.0

7.5
10

mV

IViol

RS'; 10 krl. T A = +25 0 C
RS'; 10 krl. T A = Tlow to Thigh
RS'; 50 kl!. T A = +25 0 C

-

-

-

RS'; 50 krl. T A = Tlow to Thigh

I "put Offset Current

-

-

-

-

-

1.5

10
20

-

3.0

-

-

75
100

-

70

-

250
300

-

0.5

2.0

-

3.0
2.5

-

-

-

--

-

-

1.8

3.0

25
15

160

-

-

-

15.

-

6.0

30

0.1

-

0.2

-

0.01
0.02

0.3
0.6

±12
±10

+14
±13

-

-

-

nA

Iliol

-

TA = +250 C

-

T A = Tlow to Thigh

-

50
70
nA

Ib

Input Bias Current

T A = +25 0 C
TA = Tlow to ThiQh

30

~

Input Resistance

Rin

Supply Current

ID

-

-

1.5

4.0

+25~C

1.8
1.2

.AV

Average Temperature Coefficient of Input Offset Voltage

ITCViol

50
25.

160

-

3.0

_.

0,01
0.02

Input Voltage Range ITA = Tlow to Thigh)
Vs = ±20 V
Vs =±15 V

Vin

nA/oC

±12
.±14
±10' ±13

-

--

I ... SO

96

±15

Common-Mode Rejection Ratio IT A = Tlow to Thigh)
RS<;;10krl
RSS 50 kH

CMrej

Supply Voltage Rejection Ratio ITA = Tlow to Thigh)
RS<;;10kH
RSS 50 kH

st. S-

-

I

Nota 1. For supply voltages less than ±.15 V, the absolute maxi·
mum input voltage is equal to the supply voltage.

~

7·

..

1TCIioi

Vo

-

/J.V/oC

+25 0 CS T A S Thigh
Tlow~ T AS +25 0 C
Output Voltage Swing ITA = Tlow to Thigh)
VS=±15 V. RL = 10krl
RL=2.0kH

'-

V/mV

Tlow';TA S Thigh
Average Temperature Coefficient of Input Offset Current

Megohms

mA

...

-

Vs = ±20 V. T A = +25 0 C
Vs = ±20 V. T A = Thi h
Vs = ± 15 V. T A =
Large Signal Voltage Gain
VS=±15 V. V o =±10V. RL>2.0kl!. TA = +25 0 C
Vs = ±15 V. V o = ± 10 V. RL~ 2.0 kl!. T A = Tlow

Unit

SO

-

96

-

..

_-

-

V

-

-

V

. 1,

-

±12

-

-

-

-

70

90

-

-

70

96

-

-

dB

dB

Note 3. Unless otherwise noted, these specifications apply for:

Note 2. For operating at elevated temperatures, the device must
be derated basad on a maximum junction temperature of
+1500 C for the MLM107G,and 1000 Cforthe MLM207G
and MLM307G. The TO-99 package is derated based on
8 thermal resistance of + 1500 C/W, junction to ambient,
or +4SoC/W, junction to case.

7-631

Tlow

Thigh

±5.0 V'; Vs ~±20 V. -550C ~TA'; +125 0 C. MLM107G
±S.O V'S Vs !S'±20 V, -25°C 'ST A

±5.0 V,; Vs ",,±15 V.

S

+8SoC, MLM207G

OOC';TA'; +70o C. MLM307G

I

MLMI09K
MLM209K
MLM309K

\

VOLTAGE REGULATOR
\..~_

_ _- - - - l

MONOLITHIC VOLTAGE REGULATOR
The MLM109K, MLM209K, and MLM309K are functionally,
electrically, and pin·for·pin equivalent to the National Semi·
conductor LM109, LM209, and LM309 respectively.
•

Fixed 5.0 Volt Output Voltage

•

Output Current in Excess of 1.0 Ampere

•

Internal Thermal Overload Protection

VOLTAGE REGULATOR
MONOLITHIC SILICON
INTEGRATED CIRCUIT

FIXED 5.0 V REGULATOR

INPUT

~"'--4>--<>---I{

MLM109K

il-o--..--5eV 0 UTPUT

METAL PACKAGE

CASE 11
ITO·31
BOTTOM VIEW

Leads 1 and 2 electrically isolated from
case,
Case is third electrical connection.
Leads are gold-plated copper cored kovar .

NOTES:
• Required if regulator is located an appreciable
distance from power supply filter.
Although no output capacitor is needed for
stability. it does improve transient response.

Package weight

~

7.4 grams.

ADJUSTABLE OUTPUT REGULATOR
CIRCUIT SCHEMATIC

r---.,...--~t------1r----+---'-<>' INPUT

INPUT ........--c>-l

1--0--....- ... OUTPUT
RI
300
1%

R2
lk
0.3

I

CURRENT REGULATOR

INPUT ...-..---<>--<..... OUTPUT

OUTPUT

R4_RS

jf2-Rl

AV=~

See Packaging Information Section for outline dimensions.

7-634

MLM210G, MLM310G

(continued)

MAXIMUM RATINGS (TA = +25 0 C unless otherwise noted'!
Symbolt

MLM210G

MLM310G

Unit

Power Supply Voltage

Vcc(maxl
VEE (maxi

+18
-18

+18
-18

Vdc

Input Voltage (Note 1)

VIC

±15

±15

Volts

Output Short Circuit Duration (Note 2)

Tsc

Indefinite

Rating

Power Dissipation (Package limitation) (Note 3)

Po

1;00

500

mW

Operating Temperature Range

TA

-25 to +85

o to +70

°c

Storage Temperature Range

T stg

Lead Temperature

-65 to +150' -65 to +150
300

300

TS

°c
°c

(soldering. t = lOs)

ELECTRICAL CHARACTERISTICS (See Note 41
Characteristic

Symbolt

Input Offset Voltage
TA = +250 C
TA=Tlow'toThigh"

Via

Input Bias Current

liB

Max

Min

MLM310G
Typ

4.0
'6.0

-

2.5

MLM210G
Typ

Min

Max

mV

-

1.5'

-

~

-

-

7.5
10
nA

-

1.0

3.0
10

-

2,0

-

-

7.0
10

ri

10'0

10 12

10 10

10 1;1

-

I"put Capacitance

Ci

-

-

1.5

-

1.5

-

Large-Signal Voltage Gain
(VS = ± 15 V. Va = +10 VI
TA = +25 0 C. RL = 8.0 k ohms
TA = Tlow to Thigh. RL = 10 k ohms

AVS

TA = +250 C
T A = Tlow to Thigh

Input Resistance

Output Resistance
TA = +250 C

Small,Signal Bandwidth

10

-55 0 C .;;;; T A';;;; +85 0 C
T&=+125 0 C
OC';;;;TA';;+700C

0.999:
0.999

0':9999

-

,0.75,

~

:-:.'

BW

Supply Current
TA = +250 C
TA = Thigh

Supply Voltage Rejection Ratio
±5/0V';;;;VS';;;;±18V

PSRR

;-:'.,
2.5'

.-

'.

,,'.

Va

-

,

30

.

:.,'c.,

Output Voltage Swing
Vs=± 15V. RL = 10k ohms

..

,20

,~

l!. vlOll!.T

-

ohms
pF
V!V

ro

SR

Offset Voltage Temperature Drift

-

-

Slew Rate

Unit

-:

:

..

'

-

-

-

-

0.75

2.5

ohms

-

20

-

MHz

-

30

-

V//ls

5.5

mA

5.5
4.0

-

3.9

-

-

-

6,0

-

-

-

-

10

-

-

±10

-

-

70

80

-

12.

-

.

-

/lv7"'c

Volts

.:~

sO"

'Tlow = -25°C for MLM210G
=
OoC for MLM310G

0.9999

3.9
';2.0

, ;±10 .... ::~

. 70

0,999
0.999

.>.
-

dB

"Thigh = +850 C for MLM210G
= +700 C for MLM310G

tSymbols conform to JEDEC Bulletin No.1 where applicable.
Note 1. For supply voltages less than ±. 15 volts, the absolute
maximum input voltage is equal to the supplV voltage.
Note 2. A continuous short·circuit duration capability is specified
for MLM210G as follows:
case temperatures up to
+125 0 C and ambient temperatures up to +70 o C; for the
MLM310G up to +70 o C case temperature and +5SoC
ambient temperature apply. A resistor (greater than 2.0
kilohms) must be inserted in series with the input when
the amplifier is driven from a low impedance source, thus
preventing damage when the output is shorted.

Note 3. The maximum junction temperature of the MLM210G is
+100o C, and for the MLM310G - +8SoC. For operating
at elevated temperatures, the package must be derated
based on a thermal resistance of 1S0oC/W - junction to
ambient, or 45°C - junction to case.
Note 4. All listed specifications apply fa ... ±. 5.0 V ~ Vs ~ ±.18 V
and T A'" +2SoC unless otherwise noted.
Note 5. Increased output swing under load can be obtained by
connecting an external resistor between the booster and
Vee te ... minals (pins 4 and 5).

7-635

7-636

CASE OUTLINE DIMENSIONS
DIMENSIONS ARE IN INCHES UNLESS OTHERWISE NOTED.

The packaging availability for each device type is indicated on the individual data sheets
and the Linear Selector Guide. All of the outline.dimensions for the packages are given in
this section. Outline dimensions for non-encapsulated standard linear device chips, flipchips, and beam-lead devices are found on the individual data sheets (see MCC, MCCF, or
MCBC prefix followed by type number).

CASE 11 (TO-3l

CASE 199·04

Weight;::::: 2.48 grams

Weight;::::: 7.4 grams

STYLE 1:
PIN I. BASE
2. EMITTER
CASE COLLECTOR

A
B
C
D

-0.250
0.039

1.550
0.830
0.300
0.043

6.350
0.991

t1

~E~]1QLp'0.~13~5+TI!LR3~",,"-.

I- F

0.205

G
H
J
K
L
M

1.177
0.151
0.440
0.655
0.420

0.225
1.050
1.197
0.161
0.480
0.675
0.440

5.2lD

5.7 0
26.670
30.400
4.0S0
12.1S0
17.150
11.180

29.900
3.840
11.180
16.640
10.670

CASE 206A
Plastic Package

K

14.73

All JEDEC dimensions and notes apply

R
S
T
U

1.91
0.81
6.99
6.22

2.16
0.86
7.24
6.48

J
K
L
M
N
S

II

L

--1-J

0.085
0.034
0.285
0.255

MILLIMETERS
MIN
MAX
3.81
3.30
3.94
3.43
0.64
0.89
0.20
0.30
2.18
1.88
0.64
0.89
1.50
1.75
3.18
2.92
15.75 16.76
10
2.03
1.78
8.64
9.65

Weight;::::: 0.92 gram

G Suffix

Metal Package

F:1 ' ,""""

~

[H

'
L

~

F-

H

I

, ,
D--H+
-..-lG

CASE 601·02 TO·99

R

0
F

0.075
0.032
0.275
0.245

I--s

K

NOTES:
1. DIM "G" ISTD CENTER OF LEADS

'lJr

G

30 TYP

~~Nt+~I"".~4i!-7"
"-t!..!--il~.7~3~~""0"".0~5~8~0~.0~6,,--i8H
Q
4.78
5.03
0.188 0.198

t~i
~IG

C

H

0.580 0.5S0

30 TYP

M

Weight;::::: 0.2 gram

A

14.99

HL~-='2ri.l-F6+2"'.4IT1 -+-iC
O.iii
08""5+oiii.0'"Sn5

r--- s ;;;;=:l_t

DIM

----r

HJH70~.4*3-+i0",.6*9-+-*,0.0"1,,,7+0",.0",2,,"7

39.370
21.0BO
7.620
1.090

INCHES
MIN
MAX
0.130 0.150
0.135 0.155
0.02 u.u ••
0.008 0.012
0.074 0.086
0.025 0.035
0.059 0.069
0.115 0.125
0.620 0.660
IOU
0.070 0.080
0.340 0.380

I_I

1"
=1l

STYLE 3: (WAS 601CI
PINS 2 & 6 OMITTED

All JEOEC dimensions and notes apply

DIM
A

INCHES
MIN
MAX
0.335
0.370

MILLIMETERS
MIN
MAX
8.510
9.390

~

~.~~~ ~.~~~

~.~~~

D
E
F
G
H
J
K
M
N
P

0.016
0.021
-0.040
0.016
0.019
0.200 TP
0.02B
0.034
0.029
0.045
0.500
-45° TYP
-0.050
0.250
0.500
0.140
0.160
0.010
0.040

4.070

Q

R

8-1

STYLE 2: (WAS 60181
PINS 5 & 7 OMITTED

K

- j 1- D

--

/PLANE

STYLE 1: 601
ALL PINS USED

:.~~~

0.533
1.020
0.406
0.482
5.0BO TP
0.712
0.864
0.737
1.140
12.700
450 TYP
-1.270
6.350 12.700
3.560
4.060
0.254
tOlD

I

CASE 602A

Weight

DIM
A
B

C

D

E
G
H
J
K
M

MILLIMETERS
MIN
MAX
8.510
9.390
8.500
7.750
4.570
0.407
0.481
1.010
5.840 TP
0.712
0.863
1.140
0.736
12.700
36° TP

gram

~:L
r- .

,

E
INCHES
MIN
MAX
0.370
0.335
0.305
0.335
0.180
0.016
0.019
0.040
0.130 TP
0.018
0.034
0.029
0.045
0.500
360 TP

~0.918

CASE 6028

I

SEATINJ
PLANE

D-

DIM
A
B

C
0
E
G
H
J
K
M

K

-

~

~'L
I

M

'0

~

MILLIMETERS
MIN
MAX
8.510
9.390
8.500
7.750
4.570
0.407
0.481
1.010
5.840 TP
0.712
0.863
U.I36
1.14"
19.050
36 TP

O-

G

,

G Suffix
Metal Package
OJ05 0lA

0.010
0.040
0.016 01A
0.019

CASE 603·03

0.165

DIM
A

0.500 MIN

B

C
0
E
F

AUJEOEC dimensions and notesapp1v

G
H

d ".
;---t--0.230 T.P.

36~

Weight ~ 0.918 gram

G Suffix
Metal Package

~

J
K
L
M

~~b.l60
6

2

l

__

'~nojL

.
'
"
~

"'t~q[
~

H

70~~OJO

J

Weight ~0.918 gram

DIA

.

'

M

',°00°,"
' ,

CASE 603·02 TO·l00

K

~

H

-

I

SEATlJ
PLANE

6o~~O~~

t

gram

{Th

C

INCHES
MAX
MIN
0.335
0.370
0.335
0.305
0.180
0.016
0.019
0.040
0.230 TP
0.Q18
0.034
0.019
0.045
0.750
36° TP

~0.918

Weight

G Suffix
Metal Package

INCHES
MIN
MAX
.335
.370
.305
.335
.240
.260
.016
.019
.040
.040
.230 TVP
.028
.034
.029
.045
.500
.140
.160
360 TP

';T

-ft- i

MI LLiMETERS
MIN
MAX
8.51
9.39
7.75
8.50
6.09
6.60
.482
.407
1.01
1.01
5.84 TVP
.712
.863
.736
1.14
12.70
3.56
4.06
360 TP

L","

j

PLANE

H---JI-o

/

XI
.;/ &0-01 3

M

~4_
.."k--;"Q

!d

J,

""'-.: 8q"Oi-osli"

10· ... -

"

LBG

~0
0.028

0.029
0.045

0.034
Weight"" 0.918 gram

CASE 606 TO·91

Weight ~ 0.127 gram

F Suffix
Ceramic Package

~E

CASE 607 TO·86

Weight

F Suffix
Ceramic Package

~

DIM
A
B

C
0
E
F

G
H

K

INCHES
MIN
MAX
0.290
0.240
0.240
0.260
0.070
0.030
0.003
0.006
0.005
0.035
0.045
0.055
0.019
0.010
0.D15
0.070

-

MILLIMETERS
MIN
MAX
6.100
7.360
6.600
6.100
0.762
1.770
0.152
0.077
0.127
0.889
1.390
1.150
0.254
0.482
0.381
1.780

G-r-

C

SEATING
PLANE

j~

:J1I~~

i=Ttj

N

F

All JEDEC dimensions and notes apply

0.218 gram

7····'---.i

t=IC CCCc1=:U
o

~

NOTE:

G

M

0

K

J

All JEDEC dimensions and noles apply.

~.~

DIM
A
B

C
0
E
G
H
J
K
L
M
N

NOTE:
1. LEAD "I" IS IOENTIFIED BV A TAB ON THAT LEAD.

8-2

INCHES
MIN
MAX
0.240
0.275
0.260
0.240
0.070
0.030
0.010
0.019
0.006
0.003
0.005
0.035
0.D15
0.050 TP
0.070
0.015
0.100 TP
0.150 TP

-

-

MILLIMETERS
MIN
MAX
6.100
6.980
6.100
6.600
1.770
0.762
0.482
0.254
0.152
0.077
0.127
0.889
0.381
1.270 TP
1.770
0.381
2.540 TP
3.810 TP

-

~

t

.~:

I * ~,t

LI1f-"

H

f ~r[~]]~ ~c+
i--A-

K

CASE 614

r--F-:

'I

'''''""y
4

R Suffix
Metal Package

PLANE

. T

K

~6.315

grams

F

G
H

J
K
L
M

-

J

r J -t-J-+-j

,ryo:o~
0 j

+

INCHES
MAX
MIN
1.252
.700
.200
.265
.032
.028
.500
.470
.1520
.142
.075
.050
.958
.962
.483
.477
.360
.325 TYP R
36' TYP

---.i

....-lk-D

F
DIM
A
B
C
D
E

~AAA AAA~

G

L

+

\

95M

~o.o~ i

MILLIMETERS
MIN
MAX
31.80
17.78
5.08
6.73
.813
.711
11.94
12.70
3.61
3.86
1.27
1.90
24.43
24.33
12.12
12.27
9.14
8.25 TYP
36 0 TYP

12 II 10.

1

5

2

3

4

6

t

F

H

11

J
K
L
M
N
S

1

78

DV~FV VVV~

B

I.lJ

j-A

SEATING
PLANE
.

~I- D ~

H

B

C
D
E
F
G

.370
.240
.135
.015

.390
.250
.155
.019
.045
O.IOOTP
.030
.060

9.39
9.90
6.09
6.35
3.43
3.94
.381
.483
1.14
2.54TP
.762
1.52

L Suffix·
Ceramic Package
Weight ~ 1.954 grams
~

I

~

U

UI

~I-

~:i~ -rr:~~1 :9~j 1.

f - - 0.470• T.P.
0° to 10 0 1--_ _ _ o.750*

I 1
S

P

t

SEATING
PLANE

N

Weight

-.II--

1\
~

0.31 gram

t~: ~~j~
II-- 0.260
I
0.280 --i

~

0.210

l\\.-~:m
I

!

100

---.J
I

MA~.340

8-3

-=- =

=r- :.lt
0.020

~~0.030

0.380

~:~~~

T.P.
*Dimension is to lead centerline when formed parallel.

0.135

~ j1-llC~
] .T

oJ:l~1
b~
L

,.

~:~~; ~:~~~

Ot5
0.085

0.059
0.069 0.025

0.125

0·r:-]n0I1R~~I~I
--i -

0.762

AIIJEDECTO-116 dimensionsand notes apply.

0.025
[0.035

0 755

I

0.508

Plastic Package

-'-~: :~
~[~~lrG

I

CASE 643A

_~

~0295~

I
I-

--j

0. 5

9

u

---inl1

A

tiM

Weight ~ 1.85 grams
0.080

1

~.~~~

09g;0

~J11-f1.\

NOTES: I. DIMENSION "P"IS TO LEAD CENTER LINE
WHEN FORMED PARALLel:
2. FOUR 141 INSULATING STANDOFFS ARE
PROVIDED.

Plastic Package

MILLIMETERS
MIN
MAX
17.400 19.900
5.080
0.381
0.584
0.770
1.770
2.290
2.790
4.830
5.330

NOTE
1. "H" -lnSialied Position of Lead Centers.
2. ''S'' - OveIillllnstalledWidth.

-----1 I- F
I

I

CASE 641

1.97 grams

~K~~0.~10~0~~-...+-~2.5~4~04-~~

I

r-

L

P\N~\-~Ll

~N~TEC~ c "~"~, p~ ~E ~ ~~
o

MIN

-

INCHES
DIM MIN
MAX
A 0.660
0.780
C
0.200
D 0.015
0.023
F
0.030
0.070
H
0.090
0.110
J
0.190
0.210

CASE 632 TO·116
A

'.!

0.130
0.250

4.190
1.650
TP
0.889
0.381
3.430
2.930
IS'
0'
7.620TP
0.305
0.203
8.260

NOTES:
1. DIM. "M"IS MEASURED AT CENTER OF
LEADS WHEN FORMED PARALLEL
2. "J"·INDEX:
NOTCH IN LEAD. INK DOT. OR
NOTCH IN CERAMIC.
Weight ~

CASE 626
P Suffix
Plastic Package
Weight ~ 0.446 gram

~

r;:s~

Ti1mi1M[i-?
J L

.1

H

16 15 14 "

MILLIMETERS
MAX
MIN
18.790 19.810
6.990
6.100
5.080
4.320

INCHES
MAX
MIN
0.780
0.740
0.275
0.240
0.200
0.170
0.015
0.020
0.165
0.135
0.065
0.055
0.100 TP
0.035
0.D15
0.135
0.115
IS'
0'
0.300 TP
0.012
0.008
0.325

DIM
A
B
C
D
E

L Suffix
Ceramic Package

~

~.

Weight

j

CASE 620

.I

0.008
0.012

0.065
0.080

CASE 644A

Weight

~

CASE 646

0.45 gram

P Suffix
Plastic Package
Weight ~ 0.911 gram

Plastic Package
0.025

O~cc:::::o:: ~3

===::I:J=1i
I

F

G
H
J

5
6 ::II:
0.290
7 - - - , - , 0.075 0.310

,..,..-- 2

K

~
__~1____~8~~~
_____
0._08_5~1

L

~
Inn
n

l-~:~~~~

0.025
0.D3~ '---- 0.059

Td

Dimension "L"to lead centerline when
,formed parallel.

1-

b

:;Jlv

I

O~jnn....~i,.L:F=f~~=t~
[T:.:::..h
" ~

0.210

L~~~~lr 0.J25
I
0.340 0.135

10'
MAX-)

~

~~~-fii'~~

~:~~~ ~:~~~

1\\

f--- O.38f i -

0.008

-L\I,1--0.012

SEATING
PLANE

~------~~:~~~O·O·------~·

CASE 647

Weight

G

~

0.911 gram

PO Suffix
Plastic Package

.

~~ ~H--- 0

K

M

~0.93

n

r1

0.755 n

n

n

gram

I

'W~
-$-1

NOTES:
I. OIM "L" TO CENTER OF LEAOS
WHEN FORMED PARALLEL.

0.240

0.250

14

0190

I--~

~~ c .t: c .t:
IT

of
0025

--.i.

---11--~~~~
~I
%
IITL
f::::I

t:' tJ+- .-T
0.115

0125

0.100--j
J.P.

I.

--l1---0.015

r--

0.020

0.014

r::--

u

~0

-

0040

ii1!6D
0.009t- o.190

0035

v-

---j

0.210

H

J~
_

Weight ~0.188 gram

CASE 665
F Suffix
Ceramic Package

VVJ[

v

!

y ---n

.1 r

~l'rl U..-f

G'--

JLo

G Suffix
Metal Package

tt

~'l'

fl-

SEATlN~!jl'

M

PLANE

CASE 686

O.OlD 0045
0.019 0:055

INCHES
MIN
MAX
.815
.835
.240
.260
.160
.180
.015
.020
.045
.055
.100 BSC
.052
.072
.008
.012
.115
.135

HG7-t~c:i'~-'-:TrR~-"~'=_T--;;;.~O~~~r~~"i~""...__1

A

I

I

0.410

J-\\-

H~;--t~7",.3~7-t-~71iii·~i;-~_T~.~29~°-t--'i·:;;,d~H
H N".--t--'.6"4-t----";;.B"9-T~.n.02"'5-t--;.0;;;35;-i

,\J..L\ J-U-U·..\.J-I.J-U-lJ1.

0.390

N

I~ f\~ =V'-.L~.1"'3....L---"'.3"-8_'_~.""OO"'5_L._".0'_'15"__J

yv

jr--

J

MILLIMETERS
DIM MIN
MAX
A 20.70
21.21
B
6.09
6.60
C
4.07
4.57
D
.38
.51
F
1.14
1.40
G
2.54 BSC
H
1.32
1.B3
J
.20
.30
K
2.92
3.43

CASE 648
Weight

~0.730------1.

I"

INCHES
MIN
MAX
.710
.740
.240
.260
.160
.180
.015
.020
.040
.065
.100 BSC
.052
.072
.009
.014
.115
.135
.290
.3lD

------l~MN~~~*v.Fl0~°_T~~~FlD~'~
:-l n n I '
.64
.89
.025
.035

i[jjjjj

I

I

A

MILLIMETERS
MIN
MAX
18.03
18.79
6.09
6.60
4.06
4.57
.38
.51
1.02
1.65
2.54 BSC
1.32
1.83
.23
.36
2.92
3.43
7.37
7.B7

ft[s: : : : : ::141~u~ .13~:~~~3B .0·g~;~~015

0.135

~0.069

.

DIM
A
B
C
D

Weight

~

0,918 gram

OIM
A

INCHES
MIN
MAX
0.335
0.370

MILLIMETERS
MIN
MAX
8.51
9.40

F
G

0.120
0.150
0.230 TP

3.05
3.81
5.84 TP

I

0.020
0.030

...i.- r-0.025
REF

I

9& 10,10& 11

I j

0.250MIN
_________
I

*Seven places; {between all leads except 5 & 6,

0.030
0.070
I

t

Ol03
0.006

8-4

APPLICATION NOTE ABSTRACTS
The application notes listed in this section have been prepared to acquaint the circuits and systems
engineer with Motorola Linear integrated circuits and their applications. To obtain copies of the notes,
simply list the AN number or numbers and send your request on your company letterhead to: Technical
Information Center, Motorola Semiconductor Products Inc., P.O. Box 20912, Phoenix, Arizona 85036.

AN·204A The MC1530, MC1531 Integrated
Operational Amplifiers
Two monolithic operational amplifiers feature
exceptionally high input impedance and high open
loop gain. This note describes the function of each
stage in the circuit, methods of frequency compen·
sating and dc biasing. Four applications are discussed:
a summing circuit, an integrator, a de comparator, and
transfer function simulation.

large common mode input signal, and low drift. The
function of each stage in the circuit is analyzed, and
methods for frequency compensating the amplifier
are discussed. DC biasing parameters are also examined. Four applications using the amplifier are discussed: a source follower, a twin tee filter and oscillator. a voltage regulator, and a high input impedance
voltmeter.

AN·245A An Integrated Sense Amplifier
for Core Memories

AN261A Transistor Logarithmic Conversion Using
An Integrated 0 peratio nal Amplifier

This application note discusses core memories and
related design considerations for a sense amplifier.
Performance and environmental specifications for the
amplifier design are carefully established so that the
circuit will work with any computer using core memo·
ries. The final circuit design is then analyzed and
measured performance is discussed. The amplifier
features a small uncertainty region (6 mY max.),
adjustable threshold and fast cycle time (0.5 J.l.s).

AN·247

The design of a log amplifier using a common base
transistor configuration as the feedback element of an
integrated circuit operational amplifier circuit is discussed in this application note. Five decades of logarithmic conversion are obtained with less than 1%
error of output voltage. The Me 1556 op amp proves
superior in this application due to its very low bias
current. A design using the MC 1539 op amp is also
discussed.

An Integrated Circuit RF·I F Amplifier
AN-273A Getting More Value Out of An Integrated
Operational Amplifier Oata Sheet

A new, versatile integrated circuit for RF-IF applications is introduced which offers high gain, extremely low internal feedback and wide AGe range.
The circuit is a common-emitter, common-base pair
(the cascade connection) with an AGe transistor and
associated biasing circuitry. The amplifier is built on
a very small die and is economically comparable to a
single transistor, yet it offers performance advantages
unobtainable with a single device. This application
note describes the AC and DC operation of the circuit, a discussion of V-parameters for calculating optimum power and voltage gain, and a variety of applications as an IF single-tuned amplifier, IF stagger-tuned
amplifier, oscillator, video-audio amplifier and modulator. A discussion of noise figure is also included.

The operational amplifier has become a basic building block in present day solid state electronic systems.
The purpose of this application note is to provide a
better understanding of the open loop characteristics
of the amplifier and their significance to overall circuit
operation. Also each parameter is defined and reviewed
with respect to closed loop considerations. The importance of loop gain stability and bandwidth is discussed at length, Input offset voltage and current and
resultant drift effects in the circuit are' also reviewed
with respect to closed loop operation.

AN-299
AN·248

An IC Wideband Video Amplifier With AGC

This application describes the use of the MC 1550
as a wide band video amplifier with AGe. The analysis
of a single stage amplifier with 28 dB of gain and 22
MHz bandwidth is given with the results extended to
a 78 dB video amplifier with 10 MHz bandwidth.

A High Voltage Monolithic Operational
Amplifier

This note introduces a high voltage monolithic
operational amplifier featuring high open loop gain,

I
9-1

APPLICATION NOTE ABSTRACTS (continued)

tion of the device itself. The final sections of the
note discuss such topics as operation from single and
split power supplies. frequency compensation. and
various feedback schemes.

AN·400 An Operational Amplifier Tester
A simple and inexpensive tester for Motorola's
line of operational amplifiers is described which will
measure the open loop voltage gain, the equivalent input offset voltage, the maximum positive and negative output voltage swing, and a view of the transfer
function which shows the linearity of the device.
Included is an elementary discussion of the
parameters measured and their relationship to closed
loop performance.

ANA11 The MC1535 Monolithic Dual Op Amp
This note discusses two dual operational amplifier applications and an input compensation scheme
for fast slew rate for the MC 1535. A complete ac
and dc circuit analysis is presented in addition to
many of the pertinent electrical characteristics and
how they might affect the system performance.

AN·401 The MC1554 One·Watt Monolithic Integrated
Circuit Power Amplifier
This application note discusses four different
applications for the Me 1554. along with a circuit description including dc characteristics. frequency response. and distortion. A section of the note is also
devoted to package power dissipation calculations including the use of the curves on the power amplifier
data sheet.

AN·421 Semiconductor Noise Figure Considerations
A summary of many of the important noise
figure considerations related with the design of low
noise amplifiers is presented. The basic fundamentals
involving noise, noise figure, and noise figure-frequency
characteristics are then discussed with the emphasis
on characteristics common to all semiconductors. A
brief introduction is made to various methods of data
sheet presentation of noise figure and a summary is
given for the various methods of measurement. A
discussion of low noise circuit design, utilizing many
of the previously discussed considerations, is included.

AN·403 Single Power Supply Operation of IC Op Amps
A split zerier biasing technique that permits use
of the MC 1530/1531. MC 1533. and MC 1709 operational amplifiers and their restricted temperature
counterparts MC 1430/1431. MC 1433 and MC I 709C
from a single power supply voltage is discussed in detail. General circuit considerations as well as specific
ac and dc device considerations are outlined to mini·
mize operating and design problems.

AN·432B Integrated Circuit
FM Stereo Decoding
Present day monolithic stereo demodulators in
addition to decoding the audio information, provide
many auxiliary functions. This note describes the
basic demodulator and several interesting accessory
capabilities available on the MCI304, MCI305, and
MC1307.

AN·404 A Wideband Monolithic Video Amplifier
This note describes the basic principles of ac
and dc operation of the MCI552G and MC1553G.
characteristics obtained as a function of the device
operating modes. and typical circuit applications.

AN·439 MC1539 Op Amp and its Applications

AN-405 DC Comparator Operations Utilizing Monolithic
IC Amplifiers

This application note discusses the MC 15 39, a
second generation operational amplifier. The general
use and operation of the amplifier is discussed with
special mention made of improved operation over
that of its first generation predecessor-the 709 type
amplifier.
In addition to the detailed discussion on the
dc and ac operation of the device, considerable emphasis is placed on operational performance. Many
applications are offered to demonstrate the device
capability, including a high frequency feed·forward
scheme, and a source follower application.

The use of the MC I 533 operational amplifier
and the MC 171 0 differential comparator are discussed. The capabilities and performance are given
along with typical operating curves for both devices.

AN·407 A General Purpose IC Differential Output
Operational Amplifier
This application note discusses four different
applications for the MC 1520 and a complete descrip-

I
9-2

APPLICATION NOTE ABSTRACTS (continued)

AN-459

A Simple Technique for Extending Op Amp
Power Bandwidth
The design of fast response amplifiers is presented without the use of "tricky" compensation
procedures or calculations using data sheet information. Circuit analysis for compensation procedure
is given.

AN-475

AN-460

Using the MC1545 - A Monolithic, GatedVideo Amplifier
Because of the unique design of the MC1545,
this amplifier can be used as a gated video amplifier,
sense amplifier, amplitude modulator, frequency shift
keyer, balanced modulator, pulse amplifier, and many
other applications. This note describes the ac and dc
operation of the circuit and presents applications of
the device as a video switch, amplitude modulator,
balanced modulator, pulse amplifier, and others.

AN-471

AN-480 Regulators Using Operational Amplifiers
The theory of op amp voltage regulator design is
discussed. The problem areas associated with such
designs are also detailed. The MC 1560 is used as a
OTC voltage reference in the op amp regulator designs
that are shown_ It is shown that regulation from
0.01% to 0.001% is possible.

Using Transient Response to Determine
Operational Amplifier Stability
This application note describes a technique for
evaluating the stability of any particular feedback
amplifier configuration by analyzing its response to a
step-function input. A theoretical analysis is given
along with an example.

Analog-To-Digital
Conversion Techniques
The subject of analog-to-digital conversion and
many of the techniques that can be used to accomplish
it are discussed. The paper is written in general terms,
from a system point of view, and is intended to assist
the reader in determining which conversion technique
is best suited for a given application_

Analysis and Basic Operation of the MC1595
The MCI595 monolithic linear four-quadrant
multiplier is discussed. The equations for the analysis
are given along with performance that is characteristic
of the device. A few basic applications are given to
assist the designer in system design.

AN-489

The MC1561 - A Monolithic High Power
Series Voltage Regulator
A complete series voltage regulator circuit capable
of delivering 1/2 ampere 'of current has been built on
a single 63 x 66-mil die using the conventional alldiffused processing technology. Improved performance has been achieved by using an internal low-power
voltage regulator to supply the desired de output voltage reference directly to a second main regulator _ This
permits the dc and ac characteristics of the regulator
to be separately optimized with the result that
excellent transient characteristics are realized simultaneously with low drift and excellent regulation.

AN-473

AN-491

Gated Video Amplifier Applications
The MC1545
This application note reviews the basic operation
of the MC 1545 and discusses some of the more popular applications for the MC 1545. Included are several
modulator types, temperature compensation of the
active gate, AGC, gated oscillators, FSK systems, and
single supply operation.

AN-513

A High Gain Integrated Circuit RF-IF Amplifier
With Wide Range AG C
This note describes the operation and application
of the Me 1590G. a monolithic RF-IF amplifier. Included are several applications for IF amplifiers, a mixer,
video amplifiers, single and two-stage RF amplifiers.

AN-474

The MC1541 - A Gated Dual-Channel Sense
Amplifier for Core Memories
The MCI541 sense amplifier can proVide many
magnetic core memory systems with lower system
cycle times and a lower package count than previous
sense amplifiers. The MC 1541 circuit operation, design
considerations, interface problems, and typical applications are herein discussed_

AN-522

The MC1556 Operational Amplifier
and its Applications
This application note discusses the MC 1556, a
second generation, internally compensated monolithic
operational amplifier. Particular emphasis is placed

I
9-3

I
I

APPLICATION NOTE ABSTRACTS (continued)

AN-547

on its distinct advantages over the early 709-type amplifier and the more recent 741-type amplifier.
Along with a description of its operation this
note presents a discussion on various applications of
the MC 1556, high-lighting its capabilities, and points
out its characteristics so the reader may make effective
use of the device.

This application note discusses a few of the many
uses for the MCI514 dual comparator. Manyapplications such as sense amplifiers, multivibrators, peak
level detectors are presented_

AN-557
AN-531

MC1596 Balanced Modulator

Semiconductor for Plated-Wire Memories

An introduction to the operation and electrical
characteristics of plated-wire memories is provided in
conjunction with the applications of semiconductors
that interface with the plated-wire memories.
Devices discussed include drivers, sense amplifiers,
and decoders. Memory organization and memoryrelated semiconductor applications are also mentioned.

AN-543

AN-559

A Single Ramp
Analog-to-D igital Converter

A simple single ramp AID converter which incorporates a calibration cycle to insure an accuracy of
12 bits is discussed. The circuit uses standard ICs
and requires only one precision part - the reference
voltage used in the calibration. This converter is useful
in a number of instrumentation and measurement
applications.

Integrated Circuit IF Amplifiers For AM/FM
and FM Radios

This application note discusses the design and
performance of four IF arnplifiers using integrated
circuits. The IF amplifiers discussed include a high
performance circuit, a circuit utilizing a quadrature
detector, a composite AM/FM circuit, and an economy
model for use with an external discriminator.

AN-545

Analog-to-Digital
Cyclic Converter

The AID cyclic converter discussed in this note
provides medium speed (1-5 J1s/bit) and medium accuracy (7 or 8 bits) operation. A cyclic converter uses
the successive approximation technique in which an
unknown analog input voltage is successively compared
to a reference voltage to determine each bit of the
digital output.
The cyclic converter offers continuous operation,
automatic generation of the digital output in Graycode form, and a building block structure. This structure uses a separate but identical circuit for each resolution bit. The cyclic converter finds use primarily in
control and process applications.

The MC 1596 monolithic circuit is a highly versatile
communications building block. In this note, both
theoretical and practical information are given to aid
the designer in the use of this part. Applications include modulators for AM, SSB, and suppressed carrier
AM; demodulators for the previously mentioned
modulation forms; frequency doublers and HF /VHF
double balanced mixers.

AN-533

The MC1514 - A High Speed
Dual Differential Comparator

Television Video IF Amplifier Using Integrated
Circuits

This a pplica tions note considers the requirements of the video I F amplifier section of a television
receiver, and gives working circuit schematics using
integrated circuits which have been specifically designed for consumer oriented products. The integrated
circuits used are the MC 1350, MC1352, MC 1353 and
the MC1330.

9-4

I GENERAL INFORMATION I
•

Master. Index

Product Highlights

Selector Guides

•
•

Previews of Upcoming Linear
Integrated Circuits

Interchangeability Guide

Nonencapsulated Device
General Information

IDATA SHEET SPECIFICATIONS I
... in alpha-numerical sequence by
device type number, unless otherwise
noted. (See Master Index for page numbers.)

Packaging Information

I

IAPPLICATION NOTES I
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