1972_National_Linear_Applications_Handbook 1972 National Linear Applications Handbook

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NATIONAL
LINEAR APPLICATIONS
HANDBOOK
January 1972

PREFACE
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear
integrated circuit applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one
particular device or to detail various methods of accomplishing a given function. The organization of
this handbook takes advantage of this innate coherence by keeping each application note intact,
arranging them in numerical order, and providing a detailed Subject Index composed of approximately
1000 references to the main body of the text. This Subject Index provides the key to
efficient access to the applications experience accumulated over the last five years by National Semiconductor.

APPLICATION LITERATURE NUMERICAL LIST
APPLICATION NOTES·
AN-1
AN-2
AN-3
AN-4
AN-5
AN-6
AN-8
AN-10
AN-13
AN-15
AN-20
AN-21
AN-23
AN-24
AN-28
AN-29
AN-30
AN-31
AN-32
AN-33
AN-34
AN-38
AN-41
AN-42
AN-46
AN-48
AN-49
AN-51
AN-53

DATE

A Versatile Monolithic Voltage Regulator . . . . . . . . . . . .
Designing Switching Regulators
............... .
Drift Compensation Techniques for I ntegrated DC Amplifiers
,Monolithic Op Amp - The Universal Li'near Component
A Fast Integrated Voltage Follower with Low Input Current
Tuned Circuit Design Using Monolithic RF/IF Amplifiers .
...... .
New Uses for the LM 100 Regulator
Low Power Operational NH0001 Amplifier . . . . . . . . .
NH0002 Current Amplifier . . . . . . . . . . . . . . . . . . .
A Complete Monolithic IF Strip for AM/AGC Applications
An Applications Guide for Op Amps
Designs for Negative Voltage Regulators
The LM105 - An Improved Positive Regulator
...... .
A Simplified Test Set for Op Amp Characterization
High Speed MOS C.ommutators
.
IC Op Amp Beats FETs on Input Current
Log Converters
Op Amp Circuit Collection
FET Circuit Applications .
Analog-Signal Commutation
How to Bias the Monolithic JFET Dual
Applications of MOS Analog Switches
Precision IC Comparator Runs from +5V Logic Supply
IC Provides On-Card Regulation for Logic Circuits . . .
The Phase Locked Loop IC as a Comm. System Building Block
Applications for a New Ultra-High Speed Buffer
PIN Diode Drivers
................. .
A Unique Monolithic AGC/Squelch Amplifier .. .
High Speed Analog Switches . . . . . . . . . . . . .

11/67
3/69
11/67
4/68
5/68
3/68'
6/68
12/68
9/68
8/68
2/69
12/68
1/69
6/69
1/70
12/69
11/69
2/70
2/70
2/70
3/70
5/70
10/70
2/71
6/71
8/71
8/71
9/71
9/71

LINEAR BRIEFS
LB-1
LB-2
LB-3
LB-4
LB-5
LB-6
LB-7
LB-8
LB-9
LB-10
LB-11
LB-12
LB-13
LB-14
LB-15
LB-16
LB-17

Instrumentation Amplifier
............ .
Feedforward Compensation Speeds Op Amp
Worst Case Power Dissipation in Linear Regulators
Fast Compensation Extends Power Bandwidth
High Q Notch Filter
............... .
Fast Voltage C'omparators with Low Input Current
Tracking Voltage Regulators
Precision AC/DC Converters
Universal Balancing Techniques . . . . . . . .
IC Regulators Simplify Power Supply Design
The LM11O-An Improved Ie Voltage Follower
An IC Voltage Comparator for High Impedance Circuitry
Applications of the LM173/LM273/LM373
....... .
Speed Up the LM108 Feedforward Compensation
High Stability Regulators
Easily Tuned Sine Wave Oscillators
LM 118 Op Amp Slews 70 V / p,sec

3/69
3/69

4/69
4/69

3/69
5/69

8/69
8/69
8/69
1/70
3/70
1/70
11/70
11/70
1/71
3/71
9/71

DEVICE VERSUS APPLICATION
LITERATURE CROSS-REFERENCE
DEVICE
NUMBER

APPLICATION
LITERATURE

AM1000 . . . . . . . . . . . . . . . . . . . . . . . . AN-53
DH0035 . . . . . . . . . . . . . . . '. . . . . . . . .' AN-49
FETS . . . . . . . . . . . . . . . . . . . . . AN-32, AN-34 .
LH0001 (NH0001)
. . . • . . . . . . . . . . . . AN-10
LH0002 (NH0002) . . . . . . . . . . . . . . . . . . AN-13
LH0014 (NH0014) . . . . . . . . . . . . . . . . . . AN-38
LH0019 (NH0019) . . . . . . . . . . . . . . . . . . AN-38
LH0033 . . . . . . . . . . . ; . . . . . . . . . . . . AN·48
LH101
. . . . . . . . . . . . . . . . . . . . . . . AN-20
LM100 . . . . . . . • . . . . . . AN·1, AN-2~ AN-8, LB·3
LM101 . . . . . . . . . . .. AN-3, AN-4; AN-20, AN-24
LM101A . . . AN-30, AN-31, LB-2, LB-4, LB-8, LB-16
LM102 . . . . . . . . . . AN-5, AN-31, LB-1, LB-5, LB-6
LM104
. . . . . . . . . . . AN-21, LB-3, LB-7, LB-10
LM105
. --;-0 • • • • • • • • • • • • AN-23, LB-7, LB-10
LM106
. . . . . .. .. . .. .. .. .. .
LB-6

ii

DEVICE
NUMBER
LM107
LM108 ·
LM109 ·
LM110 ·
LM111 ·
LM118 ·
LM170 ·
LM171
LM172
LM173
LM565
LM703
LM709
MM450 .
MM451 .
MM454.

APPLICATION
LITERATURE

. . . . . . AN-31
. . . . . . AN-29, AN-30, AN-31, LB-14,LB-15
. . . . . . . . . . . . . . . . . . . AN-42, LB-15
. . . . . . . . . . . . . . . . . . . AN-31, LB-11
. . . . . . . . . . . . . . . AN-41, LB-12, LB-16
. . . . . . . . . . . . . . . . . . . . . . . . LB-~7
. . . . . . . . • . . . . . . . . . . . . . . . AN-51
. AN-6
AN-15
LB-13
AN-46
; AN-6
AN-24
. . . . . . . . . . . . . . . . . . . . . . . . AN-33
. . . . . . . . . . . . . . . . . . . • . . . . AN-33.
. . . . . . . . • . . . . . . . . . . AN~28, AN-33 .

SUBJECT INDEX
Ato D
Converter: LB6-1
Ladder Driver: ANS-7

ANALOG SIGNAL, DEFINITION: ANS3-1
ANALOG SWITCH:ANS-S, AN2S, AN32-4, AN32-S, AN32-9
AN32-10, AN32-12, AN33, AN3S, ANS3

ABSOLUTE VALUE AMPLIFIER: AN31-12
AC AMPLIFIERS: ANS-9, AN31-1, AN31-1S, AN4S-4
AC TO DC CONVERTER: AN31-12, LB-S
ACTIVE FILTERS (see Filter, Active)
AGC
AGC/Squelch amplifier: ANSl
AM/IF AGC: AN1S
Circuit description, LM170/LM270/LM370: ANSl-3
Element comparison: ANS1-l
FET amplifier: AN34-2
Hints: ANSl-4
Methods: ANS1-1
RF Cascode amplifier: AN6-3
Temperature compensation: ANS1-l1

ANALOG TO DIGITAL
Converter: LB6-1
Ladder driver: ANS-7

AM/FM DEMODULATOR: AN3S-7, AN46-11, LB-13
AM/IF STRIP: AN1S
AMPLIFIER
AC: ANS-9, AN31-1, AN31-1S, AN4S-4
Absolute Value: AN31-12
Anti-Log Generator: AN30-3, AN31-20
Audio, J-FET: AN32-S
Bridge: AN29-12, AN31-11
Buffered High Current Output: AN4-3, AN13-3, AN29-1S,
AN31-16, AN4S-1, AN4S-4
Cascode, FET: AN32-2, AN32-6
Cascode, RF: AN6-1, AN6-3, AN6-4, AN32-9
Chopper stabilized: AN3S-4
Circuit description: LH00033: AN4S-1
Circuit description: LM10S/LM20S/LM30S: AN29-2,
AN29-1S
Circuit description: LMl18/LM21S/LM31S: LB-17
Circuit description: NH0001: AN10-l
Circuit description: NH0002: AN13-2
Clamping: AN10-2, AN31-11, LBS-l
Difference: AN20-3, AN29-12, AN31-1, AN31-9, AN31-10
Differentiator: AN20-3, AN31-2
FET: AN34
FET input: AN4-3, AN29-1, AN32-9, AN34-3
Follower (see Voltage Follower)
High current buffer: AN4-3, AN13, AN29-1S, AN31-16,
AN4S-1, AN4S-4
High input impedance: AN29-14, AN31-1, AN31-11, AN31-1S
AN32-1, AN32-7, AN4S-4, LBl-2
IF: AN6-S, AN1S-2, AN1S-S, LB13
Input guarding: AN29-16
Instrumentation: AN29-11, AN31-9, AN31-1 0, AN 31-11, LB 1
Instrumentation shield/line driver: AN4S-3
Integrator: AN20-4, AN29-7, AN31-2, AN31-3, AN31-13,
AN3S-4
Integrator, J-FET AC coupled: AN32-1
Inverting: AN20-1, AN31-1, AN31-4, LB17-2
Level shifting: AN4-2, AN13-4, AN32-S, AN41-3, AN48-3
Line driver: AN13-4
Logarithmic converter: AN29-12, AN30, AN31-1S, AN31-20
Low power: AN10
Non-inverting amplifier: AN20-2, AN31-1, AN31-4
Non-linear: AN4-4, AN31-16
Output resistance: AN29-S
Photocell: AN20-S, AN20-S
Photodiode: AN20-S, AN29-13, AN31-3, AN31-1S, LB12-2
Photoresistor bridge: AN29-12
Phototransistor: ANS-S
Piezoelectric transducer: AN29-13, AN31-17
Power:· ANS-6 (~ee -;I~o- Buffer, High Current)
Pulse: ANS-l1, AN13-4
Rejection, power supply: AN29-6
Reset stabilized: AN20-7, AN3S-4
RF (see RF Amplifier)
Sample and hold: AN4-3, ANS-S, AN29-6, AN31-12, AN32-1
AN32-6, AN32-7, AN4S-3, LBll-2
Servo preamplifier: AN4-4, AN31-16
Squelch, AGC: ANSl
Solar cell: AN4-S
Summing: AN20-3, AN31-1, AN31-13
Temperature probe: AN31-17
Variable gain: AN31-9, AN31-1S, AN32-S, LBl-2 (see also AGC)
ANALOG COMMUTATOR (see Analog Switch)
ANALOG DIVIDER: AN4-S, AN30-4, AN31-19
ANALOG MULTIPLIER: AN4-S, AN20-S, AN30-4, AN31-15,
AN31-17, AN31-19

ANTI-LOG GENERATOR: AN30-3, AN31-20
AUDIO J-FET AMPLIFIER: AN32-S
AUTOMATIC GAIN CONTROL (see AGC)
BANDPASS FILTER: LB11-2 (see also Notch Filter)
BANDWIDTH, EXTENDED: AN29-S, LB2, LB4, LB14
BIAS CURRENT COMPENSATION (see Drift Compensation)
BIAS CURRENT TEST SET: AN24-2
BIASING, FET: AN34
BOARD LAYOUT: AN29-16
BOOTSTRAPPED SHUNT FREQUENCY COMPENSATION:
AN29-16
BRIDGE AMPLIFIER: AN29-12, AN31-11
BUFFER, HIGH CURRENT: AN4-3, AN13-3, AN29-15, AN31-16,
AN4S-1, AN4S-4
BYPASSING, SUPPLY TERMINAL:AN4-S, LB2-2, LB1S-1
CAPACITANCE MULTIPLIER: AN29-10, AN31-14, AN31-15
CAPACITOR
Bypass: AN4-S, LB2-2, LB1S-1
Compensation: AN29-4 (see also Frequency Compensation)
Dielectric polarization: AN29-7
Filter, power supply: AN23-7, LB10-2
Multiplier, capacitance: AN29-10, AN31-14, AN31-1S
Switching regulator filter: AN21-11
Tantalum bypass: LB1S-1
CASCODE AMPLIFIER: AN6-1, AN6-3, AN6-4, AN32-2, AN32-6,
AN32-9
CHOPPER STABILIZED AMPLIFIER: AN3S-4
CIRCUIT DESCRIPTIONS
AM1000 Analog switch series: ANS3-2
DH003S, PIN diode driver: AN49-2
LH00033 Buffer amplifier: AN48-1
LM100/LM200/LM300 Positive voltage regulator: ANl-2,
ANS-1
LM102/LM202/LM302 Voltage follower: ANS-l
LM104/LM204/LM304 Negative voltage regulator: AN21-1
AN21-1S
LM10S/LM20S/LM30S Positive voltage regulator: AN23-1,
AN23-2
LM10S/LM20S/LM30S Operational amplifier: AN29-2,
AN29-1S
LM109/LM209/LM309 Three terminal regulator: AN42-1
LM110/LM210/LM310 Voltage follower: LBll
LM111/LM211/LM311 Voltage comparator: AN41-1, LB12
LM11S/LM21S/LM31S High slew rate op. amp.: LB17
LM170/LM270/LM370 AGC squelch amplifier: ANS1-3
LM172 AM/IF strip: AN15-1, AN1S-4
LM173/LM273/LM373, IF amplifier/detector: LB13
LMS6S Phase locked loop: AN46-S
NH000110wpowerop.amp.: AN10-1
NH0002 Current amplifier: AN13-2
CLAMP
Operational amplifier: AN10-2
Precision: AN31-11, LBS-l
Voltage follower input: AN5-S
COMPARATOR (see Voltage Comparator)
COMPENSATION, DRIFT (see Drift Compensation)
COMPENSATION, FREQUENCY (see Frequency Compensation)
COMPENSATION, TEMPERATURE (see Drift Compensation)
CONVERTER
100 MHz: AN32-3
AC to DC: AN31-12, LBS
Analog to digital: LB6-1
Current to voltage: AN20-S, AN31-2, AN31-16
Digital to analog: AN4S-3
Logarithmic: AN29-12, AN30, AN31-1S, AN31-20
CRYSTAL OSCILLATOR: AN32-2, AN32-S, AN41-4
CUBE GENERATOR: AN30-3, AN31-19
CURRENT LIMITING
Adjustable: AN21-7
External: AN21-9, AN29-16
Foldback (see Foldback Current Limiting)
Output short circuit: AN10-3
Sense voltage reduction: AN21-4, AN21-7, AN31-16, AN32-11

iii

SUBJECT INDEX (cont'd)
Switchback (see Foldback Current Limiting)
Switching regulator: AN2·8, AN8-4, AN21·12
Voltage regulator, positive: AN l·S
CURRENT MODE MULTIPLEXING: ANS3·S
CURRENT MONITOR: AN31·16,AN32·11 (see also Current to
Voltage Converter)
CURRENT SINK, PRECISION: AN20·6, AN31·8, AN32-6
CURRENT SOURCE
Bilateral: AN29-14, AN31·6
Floating: AN8-4
Focus control current source: AN8·3
High current: AN8-4, AN42-6
Precision: AN20-6, AN31·8, AN32-12
Switching current regulator: AN8-4
CURRENT-TO-VOL TAGE CONVERTER: AN20-S, AN31-2
AN31-16
D TO A CONVERTER: AN48·3
DEMODULATOR
AM-FM: AN38·7, AN46-11, LB13
DSB: AN38-S, AN38·6
Frequency shift keying: AN46-9
IRIG Channel: AN46-8
SSB: LB13·2
Weather satellite picture: AN46·11
DIELECTRIC POLARIZATION, CAPACITOR: AN29-7
DIFFERENCE AMPLIFIER: AN20·3, AN29·12, AN31-1,
AN31·9, AN31-10
DIFFERENTIATOR: AN20-3, AN31-2
DIGITAL TO ANALOG CONVERTER: AN48-3
DIODE
Catch: AN21-11
PIN driver: AN49
Precision: AN31-11, LB8·1
Protective: AN21-8
DISCRIMINATOR, MULTIPLE APERTURE WINDOW: AN31·3
DIVIDER, ANALOG: AN4-5, AN30-4, AN31-19
DOUBLE ENDED LIMIT DETECTOR: AN31-3
DOUBLER, FREQUENCY: AN41-4
DRIFT COMPENSATION
AGC Gain: AN51-11
Bias current: AN3-1, AN10·3, AN20-1, AN29-8, AN31-3
Board layout: AN29-16
Chopper stabilized amplifier: AN38-4
Gain,AGC: ANS1-l1
Integrator, low drift: AN31-13
Non-linear amplifiers: AN4-4, AN31-16
Offset voltage: AN3·3, AN20-1, AN31-4
Reset stabilized amplifier: AN20-7
Sample and hold: AN4-4, AN29-7
Voltage regulator: AN1-l0, AN8-ll, AN21-4, AN23-4
AN42-6, LB1S
DRIFT, VOLTAGE AND CURRENT: AN29-1 (see also Drift
Compensation)
DRIVER (see Amplifier, High Current Buffer)
DSB MODULATION-DEMODULATION: AN38-5, AN38·6
EMITTER COUPLED RF AMPLIFIER: AN6-1, AN6·2
FET
Amplifier: AN32, AN34
Biasing: AN34
Operational amplifier input: AN4-3, AN29-1, AN32-9, AN34·3
Switches: AN5-8, AN28, AN32-4, AN32-8, AN32-9, AN32-10
AN32-12, AN33, AN38, AN53
Voltage comparator: AN34·2
Voltmeter, FETVM: AN32·2
FEEDFORWARD COMPENSATION: LB2, LB14, LB17-2

FOLDBACK CURRENT LIMITING
Negative voltage regulator: AN21-5, LB3·2
Positive voltage regulator: AN1-S, AN23·S,
Power dissipation curve: AN23-6
Temperature sensitivity: AN23-6
FREQUENCY COMPENSATION
Bandwidth, extended: AN29-5, LB2, LB4, LB14
Bootstrapped shunt: AN29-16
Capacitance, stray: AN4·S, AN31-3
Capacitive loads: AN4-S, LB14-1
Differentiator: AN20-4
Feedforward: LB2, LB14, LB17·2
Ferrite bead: AN23·6
Hints: AN4·7, AN20-2, AN23·6, AN41-5, LB2, LB4
Multivibrator: AN4-1
Oscillation, involuntary: AN4·8,AN20·2, AN29-5
FREQUENCY DOUBLER: AN41-4
FREQUENCY RESPONSE (see Frequency Compensation)
FREQUENCY SHIFT KEYING DEMODULATOR: AN46-9
GAIN TEST SET: AN24·4
GENERATOR (see Oscillator)
GUARD DRIVER: AN4S·3
GUARDING AMPLIFIER INPUTS: AN29·16
HIGH PASS ACTIVE FILTER: AN5-10, AN31-16, LBll-2
IF AMPLIFIER: AN6·5, AN15·2, AN15·S, LB13
INDUCTOR
Core, switching regulator: AN21·11
Ferrite bead: AN23·6
Simulated: AN31-15
INSTRUMENTATION AMPLIFIER: AN29·11, AN31·9, AN31·10
AN31-11, LBl
INTEGRATOR: AN20·4, AN29·7, AN31-2, AN31·3, AN31·13
AN32-1, AN38-4
INTERNAL TIMER: AN31·17
INVERTING AMPLIFIER: AN20-1, AN31·1, AN31-4, LB17-2
ISOLATION, DIGITAL: AN41·3
LAMP DRIVER, VOLTAGE COMPARATOR: AN4-2, LB12·2
LEVEL SHIFTING AMPLIFIER: AN4·2, AN13-4, AN32-S,
AN41·3, AN48·3
LlGHT·INTENSITY REGULATOR: ANS·S
LIMIT DETECTOR: AN31-3
LIMITER, (see Clamp)
LINE DRIVER: AN13-4, AN4S-3
LOGARITHMIC AMPLIFIER: AN29·12, AN30, AN31-18,
AN31·20
LOW PASS ACTIVE FI L TER: AN5·9, AN20·4, AN31·16
MICROPHONE PREAMPLIFIER: AN51-7
MODULATION
Voltage regulator, switching: AN8·6
MODULATOR
AM/lF: ANSl-9
DSB: AN38-5
Pulse width: AN31·5
SSB, high efficiency: AN8·6
MUL TlPLEXER (see Analog Switch)
MULTIPLEXING, DEFINITION: ANS3·1
MULTIPLIER
Analog: AN4·5, AN20·8, AN30·4, AN31-15, AN31·17, AN31-19
Capacitance: AN29-10, AN31-14, AN31-15
Cube generator: AN30·3, AN31-19
Resistance: AN29·14
MUL TIVIBRATOR: AN4-1, AN24·6, AN31-6, AN41·4
NEGATIVE AND POSITIVE VOLTAGE REGULATORS (see
Symmetrical Voltage Regulators)
NEGATIVE SWITCHING VOLTAGE REGULATOR: AN2·10,
AN21·10, AN21-11, AN21-12, AN21·13
NEGATIVE VOLTAGE REFERENCE: AN20-6, AN31-8

FERRITE BEAD: AN23-6
FIL TER
Adjustable Q: AN31-14, LBS-2
Bandpass: LBll-2 (see also Filter, Notch)
Full wave rectifying and averaging: AN20·S, AN31-12
High pass active filter: ANS-l0, AN31-16, LBll-2
Low pass active filter: ANS-9, AN20-4, AN31·16
Notch: AN31·14, AN48-4, LB5, LB11-2
Notch, adjustaole Q: AN31·14, LB5-2
Power supply:-AN23-7, LB10·2
Tone Control: AN32-3, AN32-11

iv

NEGATIVE VOLTAGE REGULATOR
Circuit description LM104/LM204/LM304: AN21·1, AN21-15
Drift compensation (see Drift Compensation, Voltage Regulator)
Foldback current limiting: AN21-5, LB3·2
High current: AN21-3, AN21-4, AN21-5, LB10
High voltage: AN21-9
Hints: LB10-2, LB1S
LM100 as a negative regulator: ANl-9
Line regulation improvement:- AN21-7
Overvoltage protection: AN21-S
Power dissipation: AN21-3, AN21-5

SUBJECT INDEX (cont1d)
Precision, stable: LB15-2
Programmable: AN20-11, AN31-7
Protective diodes: AN21-S
Remote sensing: AN21-4, AN21-9
Ripple: AN21-2, AN21-6
Shunt regulator: AN8-1
Transient response: AN21-2
NIXIE DRIVER: AN32-6
NON-IN'VERTING AMPLIFIER: AN20-2, AN31-1, AN31-4
NON-LINEAR AMPLIFIER: AN4-4, AN31-16
NOTCH FILTER: AN31-14, AN4S-4, LB5, LBll-2
OFFSET CURRENT TEST SET: AN24-3
OFFSET VOLTAGE ADJUSTMENT: LB9
OFFSET VOLTAGE COMPENSATION (see Drift Compensation)
OFFSET VOLTAGE TEST SET: AN24-3
OPERATIONAL AMPLIFIERS: AN4, AN20, AN29, AN31 (also
see Amplifiers)
OPERATIONAL AMPLIFIER TEST SET: AN24
OSCILLATION, INVOLUNTARY (see Frequency Compensation)
OSCILLATOR
Crystal: .AN41-4
Crystal J-FET: AN32-2, AN32-S
Mod.ulated RF: AN51-9
Multivibrator: AN4-1, AN24-6, AN31-6, AN41-4
Quadrature output: AN31-5, LB16
RF J-FET: AN32-2, AN32-S
Sine Wave: AN20-9, AN29-9, AN31-5, AN31-6, AN31-7,
AN32-7, AN32-S, AN51-8, LB16
Triangle wave: AN20-10, AN24-6, AN31-6
Tunable frequency: AN.51-9, LB16
Wein Bridge: AN20-9, AN31-6, AN31-7, AN32-7, AN51-S
PEAK DETECTOR: AN4-4, AN31-12, AN51-5, AN51-6
PHASE LOCKED LOOP: AN46
Circuit description, LM565: AN46-5
Damping: AN46-3
Locking: AN46-5
Loop filter: AN46-2
Noise performance: AN46-5
Theory: AN46-.1
PHASE SHIFTER: AN32-S
PHONO PREAMPLIFIER: AN32-4, AN32-11
PHOTOCELL AMPLIFIER: AN20-5, AN20-S
PHOTODIODE
Amplifier: AN20-5, AN29-13, AN31-3, AN31-18, LB12-2
Level detector: AN41-2
PHOTOMULTIPLIER TUBE SUPPL Y: ANS-9
PHOTORESISTOR BRIDGE AMPLIFIER: AN29-12
PHOTOTRANSISTOR AMPLIFIER: ANS-S
PIN DIODE DRIVER: AN49
POLARIZATION, DIELECTRIC: AN29-7
POSITIVE AND NEGATIVE VOLTAGE REGULATORS (see
Symmetrical Voltage Regulators)
POSITIVE VOLTAGE REFERENCE: AN20-6, AN31-2, AN31-S
POSITIVE VOLTAGE REGULATOR
Adjustable output, LM109: AN42-5
Circuit description, LM100/LM200/LM300: ANl-2, ANS-l
Circuit description, LM105/LM205/LM305: AN23-1, AN23-2
Circuit description, LM109/LM209/LM309: AN42-1
Current limit: ANl-5
Drift compensation (see Drift Compensation, Voltage Regulator)
Efficiency: AN1-S
Failure mechanisms: AN23-7, LB3
Filtering, power supply: AN23-7, LB10-2
Fixed output: AN42-5
Foldback current limiting: AN1-S, AN23-5, LB3-2
Heat dissipation: AN1-8, AN23-3, AN23-6, AN23-7, LB3
High current: ANl-7,;AN23-4, AN23-5, AN23-6, LB3, Ll31O-1
High voltage: ANS-S,- ANS-9
Hints: AN23-7, LB3, LB10-2,LB15
Impedance, output: ANl-6
Noise reduction: ANl-6
NPN pass transistors: ANS-l0, LB10-1
Power limitations: AN23-3, LB3
Precision: AN42-6, LB 15
Programmable low-power: AN20-11, AN31-7
Protection: AN23-7
Regulation; load: ANl-5
Remote sensing: ANS-l0
Ripple induced failures: AN23-7, LB10-2
Shunt regulator: AN8-1

Shutdown: ANS-4
Switching regulator (see Switching Regulatod
Temperature compensation: AN1-l0, ANa:11, AN42-6, LB15
Transient response: ANl-6
POWER AMPLIFIER (see Buffer, High Current)
PREAMPLIFIER
Microphone, squelched: AN51-7
Phono: AN32-4, AN32-11
Servo: AN4-4, AN31-16
VOX: AN51-S
PROGRAMMABLE VOLTAGE REGULATOR: AN20-11, AN31-7
PULSE AMPLIFIER: ANS-ll, AN13-4
PULSE REGULATOR: ANS-ll
PULSE WIDTH MODULATOR: AN31-6
QUADRATURE OSCILLATOR: AN31-5, LB16
RECTIFIER, FAST HALF-WAVE: AN31C1 1 ,LB.-?:l
RECTIFIER, FULL-WAVE: AN20-S, LBS-2
REFERENCE VOLTAGE REGULATOR: AN20-6,
AN31-2, AN31-S
REMOTE SENSING
High current negative regu lator: AN21-4
High negative voltage: AN21-9
Line resistance compensation: ANS-l0
RECEIVER IF STRIP: AN6-5, AN15-2, AN15-5, LB13
RESET STABILIZED AMPLIFIER: AN20-7, AN3S-4
RESISTANCE MULTIPLICATION: AN29-14
RF AMPLIFIER
AM/IF strip: AN15
Biasing: AN6-1
Cascode: AN6-1, AN6-3, AN6-4, AN32-9
Emitter coupled: AN6-1, AN6-2
Forward transadmittance: AN6-3
Gain: AN6-2
IF amplifier: AN6·5, AN15-2, AN15-5, LB13
Input impedance: AN6-2, AN6-3
Tuned interstage circuits: AN6-4, LB 13
RF OSCILLATOR (see Oscillator, RF)
RIPPLE, POWER SUPPLY: AN21-2, AN21-6, AN23-7, LB10-2
ROOT EXTRACTOR: AN4-6, AN31-1S
SAMPLE AND HOLD: AN4-3, AN5-8, AN29-6, AN31-12,
AN32-1, AN32-6, AN32-7. AN4S-3, LBll-2
SCHMITT TRIGGER: AN32-12
SENSE VOLTAGE (see Current Limiting)
SERVO PREAMPLIFIER: AN4-4, AN31-16
SETTLING TIME: LB17-2
SHUNT REGULATOR: ANS-l
SINE WAVE OSCILLATOR: AN20-9, AN29-9, AN31-5, AN31-6
AN31~,AN32~,AN32~,AN51~,LB16

SINGLE SUPPLY OPERATION: AN31-2, AN4S-4
SLEW RATE: AN5-5, LB 17 (see also Frequency Compensation,
Feedforward)
SOLAR CELL AMPLIFIE'R: AN4-5
SQUARE ROOT CIRCUIT: AN4-6, AN31-1S
SQUELCH AMPLIFIER, AGC: AN51
SQUELCH RELEASE TIMING: AN51-12
SQUELCHED PREAMPLIFIER: AN51-7
SSB
Demodulator: LB13-2
Modulator: ANS-6
SUMMING AMPLIFIER: AN20-3, AN31-1, AN31-13
SUPERHETERODYNE RECEIVER IF STRIP: AN15-5
SUPPLY VOLTAGE SPLITTING: AN31-2
SWITCH, ANALOG: AN5-8, AN2S, AN32-4, AN32-S, AN32-9
AN32-10, AN32-12, AN33, AN38, AN53
SWITCHBACK CURRENT LIMITING (see Foldback Current
Limiting)
SWITCHING AND LINEAR REGULATOR
COMBINATION: AN2-11
SWITCH CURRENT REGULATOR: ANS-4
SWITCHING REGULATOR
Capacitor selection: AN21-11
Catch diode selection: AN21-11
Current limiting: AN2-S, ANS-4, AN21-12
Dissipation: AN21-11
Driven: AN2-7, AN21-14
Efficiency: AN2-5, AN2-6, AN2-7, AN21-10
Frequency of operation: AN2-4, AN2"5, AN2-6, AN2-7
High negative current: AN21-11, AN21-12, AN21-13

v

SUBJECT INDEX (cont'd)
High positive current: AN1-11, AN2-6, AN8-2,
High voltage: AN2-11
Hints: AN21-11
Inductor core selection: AN21-11
Line regulation: AN2-6, AN21-11
Modulation: AN8-6
Negative: AN2-10, AN21-10, AN21-11, AN21-12, AN21-13
Overload shutdown: AN8-2, AN21-13
Overvoltage protection: AN8-3
Ripple: AN2-4, AN21-11
Self-oscillating: AN2-2, AN21-10
Shutdown: AN8-2, AN21-13
Symmetrical: AN2-10
Synchronous: AN2-7, AN21-14
Theory: AN1-11,AN2-2,AN21-10
SYMMETRICAL SWITCHING VOLTAGE REGULATOR: AN2-10
SYMMETRICAL VOLTAGE REGULATOR
lM100 as a symmetrical regulator: AN1-9
Regulation: AN21-6
Tracking regulator: AN20-10, AN21-6, LB7
TEMPERATURE COMPENSATION (see Drift Compensation)
TEMPERATURE CONTROLLER: AN8-5
TEMPERATURE PROBE AMPLIFIER: AN31-17
TEST SET, OPERATIONAL AMPLIFIER: AN24
THRESHOLD DETECTOR: AN20-10, AN31-3
TIME DOMAIN MULTIPLEXING: AN53-1
TIMER, INTERVAL: AN31-17
TONE CONTROL: AN32-3, AN32-11
TRACKING VOLTAGE REGULATOR: LB7 (see also Symmetrical
Voltage Regulators)
TRANSADMITTANCE, RF AMPLIFIER: AN6-3
TRANSFER FUNCTION TEST SET: AN24-4
TRIANGLE WAVE OSCillATOR: AN20-10, AN24-6, AN31-S
TRIGGER, SCHMITT: AN32-12
TUNED RF CIRCUITS (see RF Amplifiers)
UNITY-GAIN BUFFER: AN20-2
.
VOLTAGE COMPARATOR
Analog to Digital converter circuit: LBS-1
AC coupled: LBS-2
Buffered output: AN29-15
Circuit description: LM111/lM211/LM311: AN41-1, lB12

vi

Comparison: lB 12-2
DTL driver: AN4-2, AN10-2, AN29-15, AN31-3, lB12-2
Dual limit, high speed: AN48-3
Fast: LB-S
FET: AN34-2
Hints: AN41-5
Lamp driver: AN4-2, LB12-2
MOSdriver: AN10-2, AN41-2, AN41-3, LB12-2
Op. amp. voltage comparator: AN4-2
TTL driver: AN4-2, AN10-2, AN29-15, AN31-3, AN41-2,
AN41-3, LB12-2
Zero crossing: AN31-17, AN41-2,

AN~1-3,

LBS-:;;> , LB12-2

VOLTAGE FOLLOWER
A to D ladder driver: AN5-7
Bandwidth, full power: AN5-5
Bias current: AN5-3, AN20-3
Buffer, voltage reference: AN5-7
Circuit description LH0033: AN48-1
Circuit description LM102/LM202/LM302: AN5-1
Circuit description LM110/LM21O/LM310: LB11
Clamping, input: AN5-S
Comparison: LB11-2
Frequency response: AN5-3
Gain: AN5-5
Hints, operating: AN5-S, AN20-2
Increased output swing: AN5-5
Offset adjustment: AN31-4, LB9-2
Resistance, output: AN5-5
Slew rate: AN5-5
Source resistance effect: AN5-5
Transient response: AN5-7
Voltage reference: AN20-S, AN31-2, AN31-8
Voltage reference buffer: AN5-7
VOLTAGE REGULATOR (see Positive, Negative, or Switching
Voltage Regulator)
VOLTMETER, FETVM: AN32-2
VOX PREAMPLIFIER: AN51-8
WEIN BRIDGE OSCILLATOR: AN20-9, AN31-6, AN31-7
AN32-7, AN51-8
WINDOW DISCRIMINATOR, MULTIPLE APERTURE: AN31-3
ZERO CROSSING DETECTOR: AN31-17, AN41-2, AN41-3
LB6-2, LB 12-2

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November 1967

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INTRODUCTION
The great majority of linear· integrated circuits
being produced today are DC amplifiers, particularly operational amplifiers. This has come about
both because the DC operational amplifier is a
basic analog building block and because this
device makes good use of the well-matched characteristics of monolithic components, character is. tics which are normally expensive to duplicate
with discrete parts. A voltage regulator is a circuit which requires similar precision. As shown in
the diagram of Figure 1, a basic regulator circuit
employs. an operational amplifier to compare a
reference voltage with a fraction of the output
voltage and control a series-pass element to
regulate the output.

UNREGULATED

INPUT

FIGURE 1. Basic Series·Regulator Circuit

to 250 mAo A second external power transistor
will enable the regulator to deliver currents in
excess of 2A.
The regulation is better than 1-percent for widely
varying load and line conditions. The device
also features 1-percent temperature stability over
the full military temperature range, externally
adjustable short-circuit-current limiting, fast response to both load and line transients, a small
standby power dissipation, freedom from oscillations with varying resistive and reactive loads,
and the ability to self start with any load.

VOLTAGE REFERENCE
The voltage reference of a regulator is normally
a temperature compensated avalanche diode. Commercially available diodes have a breakdown voltage
temperature coefficient of O.Ol-percent;oC to
o
0.0005/ C, depending on selection. Normal integrated circuit processing yields an avalanche diode
with acceptable characteristics for this application ..
The reversed-biased emitter-base junction of the
transistors has a breakdown voltage of approximately 6.5V and an unusually uniform temperature
coefficient of +2.3 mV fc. Hence, the positive
temperature coefficient of the avalanche diode can
be very nearly balanced out by a forward biased,
diode-connected transistor to produce a temperature compensated reference. However, exact compensation requires surface impurity concentrations
in the transistor-base diffusion which are higher
than desired to produce optimized transistors. One
design objective of an integrated regulator is, then,
to develop a reference element which permits
nearly-exact compensation without requiring process alteration.

Perhaps the reason that monolithic regulators
have not appeared sooner is because it is difficult to make one design flexible enough to
satisfy an appreciable percentage of the market.
Different systems require vastly different output
voltages and currents, as well as varying degrees
of regulation. In addition, the current handling
ability of monolithic circuits is limited because
of the large physical die size of high-current
transistors. Power dissipation is also a factor,
since there are no readily available multi-lead
power packages for integrated circu its.

Another design objective is also centered around
the reference. I n the regulator circuit of Figure 1,
the output voltage can be adjusted down to, but
not lower than, the reference voltage. This means
that, unless additional circuitry is incorporated,
the reference restricts the use of the regulator to
applications requiring output voltages above about
8V. It is therefore desirable to obtain as low as
possible a reference voltage.

A design is presented here which is versatile
enough to overcome many of these problems. It
is able to deliver regulated voltages which are
externally adjustable from 2V to 30V, operating
as either a linear, dissipating regulator or a high
efficiency switching regulator. This covers the
range from low-level logic circuits to the majority
of solid-state linear systems. Although the output
currentofthe integrated circuit is limited (12 mAl,
an external transistor can be added for currents

A circuit which provides a simple solution to the
temperature compensation problem in addition
to supplying a low reference voltage is shown in
Figure 2. In this circuit, the breakdown diode is
supplied by a current source from the u,nregulated supply. An emitter follower, Q1, buffers
the output voltage of the diode. The positive
temperature coefficient of this buffered output
is increased to approximately 7 mV/oC by the
addition of the diode connected transistor, ~.

A.Nl-2

A resistor divider reduces this voltage as well as
the temperature coefficient to exactly compensate for the negative temperature coefficient of
0 3 , producing a temperature compensated output. With the integrated circuit process used, this
output voltage is about 1.8V for optimum compensation.

The gain of this stage is made much higher than
would normally be expected by the use of 0 3
and 0 4 as collector loads. If very large PNP
current gain and good matching are assumed,
the collector current of 0 4 will be equal to the
collector current of 0 1 . Therefore, the differential
stage will be in balance independent of the
magnitude of the collector currents of 0 1 and
O2 and for the complete range of output voltage
settings and input voltage variations. Even this
simple circuit gives a no load to full load regulation of 0.2-percent and a line regulation of 0.05percent per volt.
The complete schematic of the regulator in Figure 4
shows several additions. First, an emitter follower,

2 BOOSTER
OUTPUT

FIGURE 2. Voltage Reference Circuitry

One feature of this integrated reference is that
the reverse emitter base breakdown, must have
an extremely sharp knee (even in the 1 MA region)
in order for the transistors in the circu it to be
acceptable. Therefore, the diodes can be reliably
operated at low currents where the noise is low·
and has a nearly uniform frequency spectrum.
At higher currents (above about 100 MA for these
particular devices) the noise becomes a sensitive
function of current with low-repetition-rate pulsations. At even higher currents, the noise reduces
in amplitude and loses its current sensitivity but
still retains a heavy fluctuation component.
REGULATOR CIRCUIT

A simplified schematic of the regulator is shown
in Figure 3. It is a single-stage differential amplifier with a Darlington, emitter-follower output.
,..-----.--.---+--v,.

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FIGURE 3. Simplified Schematic of the Regulator

H~NV-+-~I~~~RENT
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FIGURE 4. Complete Schematic of the LM100

0 3 , and a level-shifting diode, Q1, have been added
to increase the effective current gain of the PNP
transistor, 02. This device is a lateral PNP which
has a low current gain (0.5 to 5) but has the advantage that it can be made without adding any steps
or process controls to the normal NPN integrated circuit process. One collector of the PNP
serves as a collector load for:. the error-sensing
transistor, Og. A second collector supplies current
for the breakdown diode, 0 1 . A third collector,
which determines the output current of the other
two, maintains a current nearly equal to the
collector current of 0 4 by means of negative
feedback to the PNP base through 0 3 and 0 1 .
The collector current of 0 4 is established at a
known fraction of the resistive divider current
through R1 and R2 by the second emitter on 0 5 .
This emitter-base junction of 0 5 , which is five
times larger than that of 0 6 , bypasses most of
the divider current, at a ratio determined by the
relative geometries, to the collector of 0 5 . This
current, combined with the collector current of
0 8 through the other em itter of 0 5 , suppl ies
current for the emitter of 0 3 to drive the base
of Q2.

AN1-3

R4 and Rg serve the sale purpose of starting the
regulator. They only need to supply enough base
current to O2 to bring the breakdown diode, 0 1 ,
up to voltage. Since it can supply many times the
required current under worst-case conditions, starting i-s ensured.
The clamp diode, O2 , reduces the current variation seen by 0 3 with changes in input voltage,
improving line regulation. Rg is a pinch resistor 2
which has a sheet resistivity more than two orders
of magnitude higher than diffused base resistors,
so it can be made quite small physically. Pinch
resistors do have the disadvantages of non-linear
voltage-current characteristic, a large temperature
coefficient, a low breakdown voltage and rather
large production variations in sheet resistivity.
However, as shown in Reference 3, these characteristics can be designed around and actually put
to good use, .as they are here.
The start-up network is connected to the regulator
output terminal, rather than ground, so that the
internal power dissipation is minimized without
requiring large resistance valu~s. Because of this,
the load current ofthe regulator cannot drop below
the current supplied from the unregulated input
through R4. If it does, the circuit will no longer
regulate. This is not usually a problem, since
the resistive divider which sets the output voltage
will normally draw enough current. However, it
should be kept in mind in applications where the
regulator might be lightly loaded and the difference
between the unregulated input voltage and the regulated output voltage is apt to be high.
The collector of the output transistor, 0 12 , is
brought out separately to permit the addition of
an external PNP transistor for higher currents.
An emitter-base resistor for the external PNP, Rs,
is also included. This resistor is shorted out when
the regulator is used without the external transistor.
The output of the voltage reference is brought
out so that the inherent noise of the breakdown
diode can be bypassed o.ut. Since the low operating
current of the diode minimizes low-frequency
noise, adequate bypassing can be provided by a
capacitor as small as 0.1 JJ.F.

0 10, it removes base drive from 0 11 to prevent
any further increase in output current. tt can be
seen from Figure 4 that the voltage turning' on
010 is the voltage drop across the external current limit resistor plus a fraction of the emitterbase voltage' of the series pass transistor, 012.
This arrangement was used for two reasons.
First, less voltage is dropped across the current
limit resistor, permitting the circuit to regulate
with lower input voltages. Second, since in current limit 0 12 , is operated at a much .higher
emitter-current density than is 0 10 , it has a lower
negative temperature coefficient of emitter~base
voltage. The negative temperature coefficient of
the emitter-base voltage of 010 along with this
difference in temperature coefficients causes the
current limit to decrease by a factor of 2as the
chip temperature increases from 25°C to 150°C.
This enables the regulator to deliver maximum
current to room temperature but still be protected
when the output is shorted and the dissipation
increases: the current will decrease as the chip
heats, holding the dissipation to a safe level.
It is interesting to note that this current limit
scheme will only work when the two transistors
are in close thermal contact, as they are in a
monolithic integrated circuit.
Since a regulator is an operational amplifier with
a large amount of feedback, frequ,ency compensation is required to prevent oscillations. However,
a voltage regulator has compensation problems in
addition to those encountered in an operational
amplifier. For one, the compensation method must
provide a high degree of rejection to input voltage
transients. Secondly, it must be stable with reactive
loads which are far heavier than those normally encountered with operational amplifiers, ThirdlY,it
must minimize the overshoot caused bylarge"rbad
and line transients.
A compensation method satisfying thoserequrr·ements is shown in Figure 5. The operational
plifier is connected as an integrator and isolated

am-

The purpose of the clamp diode, 0 3 , is to keep
Og from saturating when the circuit is used as a
switching regulator. It plays no functional role
in linear operation.
OLitput- current limiting is provided by 0 10 . The
value of current limit is determined by an external
resistor between the current limit, and regulated
output terminals. When the voltage drop across
this resistor becomes high enough to turn on

FIGURE 5. Simplified Schematic Showing Regulator
Fr~quency Compensation

from the loac;f with an emitter follower, which
,.serves as a ser:ies pass transistor. If the feedback
loop is opened, at point A and the frequency
response measured, it can be seen that the feedback at high frequencies where the loop response
must be cOl1trolled, is through C F . Reactive loads
have ,little effect since they are isol?lted from the
high frequency feedback path by 0 5 ,

APPLICA TIONS
The basic regu lator circu it for the LM 100 is shown
in Figure 7. The output voltage is set by R1 and

UNREGULATED

This compensation method provides excellent
response to load transients. That part of a load
transient which is not absorbed by the output
capacitor, eL , sees the output impedance of 0 5
which is quite low since it is driven by an operational amplifier with a low AC output impedance.
In the actual regulator (Figure 4) the operational
. amplifier is a single stage amplifier (0 9 ), Hence,
it is stable in the integrator connection, with a
collector base capacitor on 0 9 , without additional compensation which might degrade either
the load or 'line. transient response. The series
PCiSS ,transistor is a compound emitter follower
to insure isolation from reactive loads. In addition, the stability of the circuit is not dependent
on the output impedance of the unregulated
supply. It is also stable with no bypass capacitance on the output (if external booster transistors are not used) so it is possible to obtain
extremely rapid current limiting as might be
required with sensi~ve transistor loads.
A PhotomiCrOgra6'h of the monolithic regulator
die is shown in Figure 6. Since the design requires a minimum of resistance, substituting active
devices where possible, the entire circuit has been
constructed on a 38-mil-square die. This die size is
comparable to that of a single silicon transistor.

INPUT

FIGURE 7. Basic Regulator Circuit

R 2, with a fine adjustment provided by the potentiometer, R3 . The resistance seen by the feedback
terminal should be approximately 2.2k to minimize
drift caused by the bias current on this terminal.
Figure 8 is based on this and gives the optimum
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20 30 50

OUTPUT VOL TAGE (V)

FIGURE 8. Optimum Divider Resistance Values as a
Function of Output Voltage

values for R1 and R2 as a function of design-center
output Voltage. The potentiometer should be least
1/4 of R2 to insure that the output can be set to
the desired voltage.
It is possible to operate the'regulator with or
without internal current limiting. If current limiting
is not needed, improved load regulation can be realized by shorting together the current limit terminals (Rsc = 0). Figure 9 gives the load regulation
for this condition. Short circuit protection is
obtained by connecting a resistor between the
current limit terminals. The resistor value is determined from the current limit sense voltage which
is plotted asa function oftemperature in Figure 10,
for low output currents which corresponds to the
case where external booster transistors are used.
The current limit sense voltage is the voltage
across the current I im it term inals when the regu lator
is current limiting with the output shorted. The
regulation and current limit characteristics with a
current limit resistor are given in Figures 11
and 12, respectively.

10n

FIGURE 6. Photomicrograph of the l-M100 Regulator

AN1-5

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FIGURE 10. Current Limit Sense Voltage as a Function
of Junction Temperature

,A bypass capacitor is not required on the regulator output in the circuit of Figure 7. This permits
extremely fast current limiting. The output impedance as a function of frequency is plotted in
Figure 13 for this condition. The output impedance
at high frequencies can be reduced somewhat by
the addition of a bypass, as shown in Figure 13.
However, it is necessary to use a low-inductance
capacitor (such as a solid-tantalum capacitor) to
gain any real advantage. Similarly, bypassing on the
unregulated input is not normally needed, although
it may be advisable to use a small (0.01 fJ.F)
ceramic capacitor when the regulator is fed through
long leads which can look like a high-Q resonant
circuit.
A reduction in the output noise can be realized

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OUTPUT CURRENT (rnA)

FIGURE 12. Current Limiting Characteristics

by the addition of a 0.1 fJ.F capacitor on the reference bypass terminal. This reduces the noise
inherent in the reference diode.
The transient response of the regulator is shown
in Figures 14 and 15. Figure 14 shows the
response to a current step from 3 rnA to 15 rnA,
without any output bypass capacitor and with a
10[2 current limit resistor. The overshoot can be
reduced both by the addition of an output bypass
capacitor and by the removal of the current limit
resistor since the overshoot is developed across
the resistor. The response to a line voltage transi,ent
is shown, in Figure 15. Neither the line transient
response nor the load transient response is affected
by the output voltage setting. Therefore, the over~
shoot becomes a smaller percentage of the output
voltage as this voltage is increased.

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OUTPUT CURRENT (A)

B. SCHEMATIC DIAGRAM
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FIGURE 19. Circuit for Obtaining Switchback Current
Limiting with the LM100

In this circuit, the voltage drop across the currentsense resistor at full load is 1.5V as compared to
about O.37V when the bucking arrangement is
not used. However, this does not increase the
minimum input-output voltage differential since
the output ofthe LM 100 does not see th is increased
voltage. With a 10V output and a 2A load, the
circuit will still work with input voltages down to
13V, worst case.
In addition to providing the switchback characteristics, R4 and R5 also give a 20 mA preload on the
regulator so that it can be operated without a load.

FIGURE 20. Positive and Negative Regulators using
the LM100

Figure 21 shows a somewhat simpler circuit. Split
secondaries are used on a power transformer to
create a floating voltage source for the negative
regulator. With this floating source, the conventional regulator is used, except that the output is
grounded.

.,

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1

R3
161K

NEGATIVE VOLTAGE REGULATORS
A schematic diagram for using the LM100 as
both a positive and a negative regulator is shown
in Figure 20. With this circuit, the inputs and
outputs of both regulators have a common
ground.
The positive regulator is identical to those described previously. For the negative regulator, the
normal output terminal (pin 8) of the LM100 is
grounded, and the ground terminal (pin 4) is
connected to the regulated negative output. Hence,
as in the usual mode of operation, it regulates the
voltage between the output and ground terminals.
A PNP booster transistor, 02, is connected in the
normal manner; and it drives a NPN series-pass
transistor, 03' The additional components (R 7 , Rs,
Rg , R 10 and Q4) are included to provide current
limiting.

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FIGURE 21. Circuit for using the LM100 as Both a
Positive and a Negative Regulator

AN1~9

TEMPERATURE COMPENSATING REGULATORS

In the majority of applications, it is desired that the
output voltage of the regulator be constant over the
operating temperature range of equipment. However, in some applications, improved performance
can be realized if the output voltage of the regulator
changes with temperature in such a way as to
operate the load at its optimum voltage.

An

example of this in integrated logic circuitry.
Optimum performance can be realized by powering
the devices with a voltage that decreases with
increasing temperature. A circuit which does this
is shown in Figure 22. Silicon diodes are used in
A. CIRCUIT DIAGRAM'

.---+-------_-VOUT

have the advantages of fast response to load
transients as well as low noise and ripple. However, since they must dissipate the difference
between the unregulated supply power and the
output power, they sometimes have a low efficiency. This is not always a problem with AC
line-operated equipment because the power loss
is easily afforded, because the input voltage is
already fairly well regulated, and because losses
can be minimized by adjustment of transformer
ratios in the power supply. In systems operating
from a fixed DC input voltage, the situation is
often much different. It might be necessary to
regulate a 28V input voltage down to 10V. In
this case the power loss can quickly become
excessive. This is true even if ef.ficiency is not
one of the more important criteria, since the high
power dissipation requirements will necessitate
expensive power transistors and elaborate heat
sinking methods.

v"
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A. CIRCUIT DIAGRAM

r---+-------......-

VOUT

AI
13K
1%

-BasmgdlagramlsTopVlew

B. OUTPUT VOLTAGE AS A FUNCTION OF TEMPERATURE

A'

2.6K
1%

~ 6

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5
4

-..... ~

~ 3
g 2

-I'-

B. OUTPUT VOLTAGE AS A FUNCTION OF TEMPERATURE

.-

~ 6

....

o
-55

+25

+125

TEMPERATURE (oC)

FIGURE 22. Temperature Compensating Voltage
Regulator with Negative Temperature
Coefficient

~ 5

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5

3

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the feedback divider to give the required negative
temperature coefficient. The advantage of using
diodes, rather than thermistors or other temperature sensitive resistors, is that their temperature
coefficient is quite predictable so it is not necessary to make cut-and-try adjustments in temperature testing. Reference 6 gives a method of predicting the voltage change in the emitter base voltage of a transistor with in 5 m V over a 100° C tem perature change. Diodes are not quite this predictable, but diode connected transistors (base shorted
to collector) can be used if greater accuracy is
required.
SWITCHING REGULATORS

The dissipating-type regulators described already

AN1-l0

+25

+125

TEMPERATURE (OC)

FIGURE 23. Temperature Compensating Voltage
Regulator with Positive Temperature
Coefficient

One way of overcoming this difficulty is to go to a
switching regulator. With switching regulators, efficiencies approaching gO-percent can be realizeq
even though the regulated output voltage is only a
fraction of the input voltage. By proper design,
transient response and ripple can also be made
quite acceptable.
A circuit using the LM100 as a switching regulator
is given in Figure 24. It is designed for an application where a 28V DC power source must supply a
system operating at 1OV.

As shown in Figure 24, the LM100 is connected in
much the same way as a linear regulator when

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FIGURE 24. High Current Switching Regulator

it is used as a switching regulator. Two external
transistors, a NPN and a PNP,are connected in
cascade to handle the output current. The regulated output is fed back through a resistive divider
which determines the output voltage in the normal
manner. The regulator is made to oscillate by
applying positive feedback to the reference terminal through R4 (from Figure 4, the reference
terminal is the non-inverting side of the input
differential amplifier).
In operation, the switching transistors, 0 1 and 02,
turn on when the voltage on the feedback terminal
is less than that on the reference termi nal. This
action raises the reference voltage since current
is fed into this point from the switch output
through R4. The switching transistors remain on
until the voltage on the feedback terminal increases to the higher reference Voltage. The regulator then switches off, lowering the reference
voltage. It remains off until the voltage on the
feedback terminal falls to the lower reference
voltage.
When the switch transistors are on, power is
delivered from the power source to the load
through L 1 . When the transistors turn off, the
inductor continues to deliver current to the load
with 0 1 supplying a return path. Since fairly fast
rise and fall times are involved, 0 1 cannot be an
ordinary silicon rectifier. A fast-switching diode
must be used ,to prevent excessive switching transients and large power losses.
Additional details of the circuit are that R5 limits
the output current of the LM 100, wh ich drives
the base of 02' C3 causes the full output ripple
to be delivered to the feedback terminal of the
regulator. The bypass capacitor, C 1 , is used on the
input line both to minimize the voltage transients
on this line and to reduce power losses in the
line resistance.

A far more complete description of switching
regulators is given in Reference 7.
CONCLUSIONS
A regulated power supply is required in practically
every piece of electronic equipment. A monolithic
integrated circu it was described here which covers
an extremely wide voltage range and can supply
virtually unlimited power by the addition of external transistors. As indicated in Table 1, its
performance is more than adequate for the majority of applications. It is flexible enough to be
used as either a linear dissipating regulator or as a
high efficiency switching regulator without sacrificing performance in either application. The LM100
also has fast transient response in that overshoot
and recovery time can be made vanishingly small
in most applications. I n addition, the frequency
stabil ity is indicated by the fact that it is virtually
impossible to make the regulator oscillate in a
properly designed circuit.
The suitability of the design to monolithic construction is demonstrated by the fact that it is
built on a 38-mil-square silicon die - a size comparable to modern silicon transistors. This small
size helps to achieve high yields which are necessary to realize low manufacturing costs and insure
off-the-shelf availability.
REFERENCES
1. H. C. Lin, T. B. Tan, G. Y. Chang, B. Van der
Leest and N. Formigoni, "Lateral Complementary Transistor Structure for the Simultaneous
Fabrication of Functional Blocks," Proc. IEEE,
Vol. 52, No. 12, pp. 1491-1495, Dec. 1964.
2. G. E. Moore, "Semiconductor Integrated Circuits," Chap. V, Microelectronics, Edward
Keonjian, ed., McGraw Hill, Inc., New York,

1963.
3. R. J.Widlar, "Some Circuit Design Techniques
for Linear Integrated Circuits," IEEE Trans on
Circuit Theory, Vol. CT-12, No.4, pp. 586590, Dec. 1965.
4. Leslie Solomon, "Ferrite Beads," Electronics
World, pp. 42-43, October, 1966.
5. R. J. Widlar, '7he Operation and U$e of a Fast
Integrated Circuit Comparator," Fairchild Semiconductor APP-116, February, 1966.
6. R. J. Widlar, "An Exact Expression for the
Thermal Variation of the Emitter Base Voltage
of Bi-Polar Transistors," Proc. IEEE, Vol. 55,
No.1, pp. 96-97, Jan. 1967.
7. R. J. Widlar, "Designing Switching Regulators,"
National Semiconductor AN-2, April, 1967.

AN1-11

TABLE 1. Typical Performance of the National LM100 Voltage Regulator

PARAMETER

CONDITIONS

Input Voltage Range

8.5-40V

Output Voltage Range

2.0 -30V

Output-Input Voltage Differential

3.0 -30V

Load Regulation

Rsc = 0, 10 < 15 rnA

Line Regulation
Temperature Stability

AN1-12

VALUE

0.1%
0.05%/V

-55°C ~ T A::; + 125°C

0.3%

Output Noise Voltage

0.005%

Long Term Stability

0.1%

StandbY Current Drain

1 rnA

Minimum Load Current

1.5 rnA

l>

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March 1969

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DESIGNING SWITCHING REGULATORS

INTRODUCTION
The series pass element in a conventional series
regulator operates as a variable resistance which
drops an unregulated input voltage down to a
fixed output voltage. This element, usually a transistor, must be able to dissipate the voltage difference between the input and output at the load
current. The power generated can become excessive, particularly when the input voltage is not we"
regulated and the difference between the input
and output voltages is large.
Switching regulators, on the other hand, are capable of high efficiency operation even with large
differences between the input and output voltages.
The efficiency is, in fact, negligibly affected by the
voltage difference since this type of regulator acts
as a continuously-variable power converter.
Switching regulators are, therefore, useful in
battery-powered equipment where the required
output voltage is considerably lower than the
battery voltage. An example of this is a missile
with a 30V battery as its only power source, containing a large number of integrated logic circuits
which require a 5V supply. Switching regulators
are also useful in space vehicles where conservation
of power is extremely important. In addition, they
are frequently the most economical solution in
commercial and industrial applications where the
increased efficiency reduces the cost of the seriespass transistors and simplifies heat sinking.

en
One of the disadvantages of switching regulators is
that they are more complex than linear regulators,
but this is often a substitution of electrical complexity for the thermal and mechanical complex:ity
of high power linear regulators. Another disadvantage is higher output ripple. However, this can
be held to a minimum (about 10 mY) and it is at a
high enough frequency so that it can be easily filtered out. Another limitation is that the response
to load transients is not always as fast as with
linear regulators, but this can be largely overcome
by proper design. The rejection of line transients,
however, is every bit as good if not better than
I inear regulators. Lastly, switching regulators
throw current transients back into the unregulated
supply which are somewhat larger than the maximu m load current. These, in some cases, can be
troublesome unless adequate filtering is used.
This article will demonstrate the use of a monolithic voltage regulator in a number of switching
regu lator appl ications. These include both selfoscillating and synchronously driven regu lators in
the O.lA to 5A range. Circuits are shown for both
positive and negative regulators with output voltages in the 2V to 30V range. Methods of isolating
the integrated circuit from the input voltage are
given, permitting input voltages in excess of 100V.
Further, current limiting schemes which keep peak
currents and dissipation well within safe limits for
both over-load and short-circuit conditions are presented. Finally, component selection details peculiar to switching regulators are co~ered.

AN2-1

SWITCHING REGULATOR OPERATION
The method by which a switching regulator produces a voltage conversion with high efficiency can
be explained with the aid of Figure 1. Q, is a
switch transistor wh ich is turned on and off by a
pulse waveform with a given duty cycle, and 0, is
a catch diode which provides a continuous path
for the inductor current when Q 1 turns off. The
voltage waveform on the collector of Q 1 will be as
shown in the figure. The output of the LC filter
will be the average value of the switched waveform, V 1. If the voltage drops across the transistor
and diode are neglected, the output voltage will be

01
l1

( 1)

+ ____ V

L-_ _ _ _ _ _ _ _ _

and it is independent of the. load current. It is
obvious from the equation that changes in input
voltage can be compensated for by varying the
duty cycle of the switched waveform. This is what
is done in a switching regulator.

OUT

=V
REF

FIGURE 2
Self-oscillating Switching Regulator

V'N

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I IL

~tON~tOFF-=:j
t---.

FIGURE 1

I n operation, when the circuit is first turned on,
the output voltage is less than the reference voltage so the switch transistor is turned on. When this
happens, current flow through R 1 raises the voltage on the non-inverting input of the operational
amplifier slightly above the reference voltage. The·
circuit will remain sw1tched on until the output
rises to this voltage. The amplifier now goes into
the active region, causing the switch to turn off.
A t this point, the reference voltage seen by the
amplifier is lowered by feedback through R 1, and
the circuit will stay off until the output voltage
drops to this lower voltage. Hence, the output
voltage oscillates about the reference Voltage. The
amplitude of this oscillation (or the output ripple)
is nearly equal to the voltage fed back through R1
to R2 and can be made quite small.

THE LM100

Switching Circuit for Voltage Conversion

Figure 2 shows a self-oscillating switching regulator which produces this duty-cycle control. A
reference Voltage, V ref, equal to the desired output
voltage, is supplied to one input of an operational
amplifier, A 1 . The operational amplifier, in turn,
drives the switch transistor. The resistive divider,
arranged such that R1
R2 , provides a slight
amount of positive feedback at high frequencies to
make the circuit oscillate. At lower frequencies
where the attenuation of the LC filter is less than
the attenuation of the resistive divider, there is net
negative feedback to the inverting input of the
operational amplifier.

»

AN2-2

The switching regulator circuits described here use
the LM 100 integrated voltage regulator as the control element. This device contains, on a single
silicon chip, the voltage reference, the operational
amplifier and the circuitry for driving a PNP
switch transistor. Discrete switch transistors, catch
diodes and reactive elements are employed since
these components are not easily integrated.
A complete circu it description of the LM 100 is
given in Application Note AN-1 along with a number of its applications as a linear regulator. However, a brief description will be included here in
order to facilitate understanding of the regulator
circuits which follow.

Figure 3 shows a schematic diagram of the LM 100.
The voltage reference portion of the circuit starts
with a breakdown diode, 0 1 , which is supplied by
a current source from the unregulated input (one
of the collectors of O 2 ), The output of the refer·
ence diode, which has a positive temperature
coefficient of 2.4 mVtC, is buffered by an emitter follower, 0 4 , which increases the temperature
coefficient to +4.7 mVtC. This is further increased to 7 mVtC by the diode-connected
transistor, Q6' A resistor divider reduces this voltage as well as the temperature coefficient to exactly compensate for the negative temperature
coefficient of Q7, producing a temperature-compensated output of 1.8V.

output current of 0 12 to the value required for
driving a PNP transistor connected on the booster
output. This current is determined by a resistor
placed between the current limit and regulated
output terminals. The value of the drive current
can be determined from Figure 4 which plots the
output current as a function of temperature for
various cu rrent lim it resistors.

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u

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a:
c::;

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a: 10

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:I:

en

-40

40

80

120

160

JUNCTION TEMPERATURE (OC)
l -....--.,.~.-1

CURRENT LIMIT

~1'VIttIw..1+e-:------4~8 REGULATED OUTPUT

...-_---7

COMPENSATION

FIGURE 4
Switched Output Current as a Function of
Temperature for Various Values of Current
Limit Resistors

~----- 6 FEEDBACK

+ _______

L.-_ _

'--.......-+----+--------

5 REFERENCE BYPASS

4 GROUND

As for the remaining details of the circuit, Q5, Q 3
and 0 1 are part of a bias stabilization circuit for
Q 2 to set its collector currents at the desired value.
Rg , R4 and O2 serve the sole function of starting
the regulator. Lastly, 0 3 is a clamp diode which
keeps Q g from saturating when it is switching.

REGULATED
OUTPUT

SWITCHING REGULATOR CIRCUITS

GROUND

Note: Pin4 connected to case

FIGURE 3
Schematic and Connection Diagrams of the
LM100 Voltage Regulator

The transistor pair, Oa and Q g , form the input
stage of the operational amplifier. The gain of the
stage is made high by the use of a current source,
one of the collectors of O 2 , as a collector load.
The output of this stage drives a compound emitter follower, Q 11 and Q12' The output of 0 12 is
taken across Ra to drive the PNP switch transistor.
An additional transistor, 0 10 , is used to limit the

Fi\:lure 5 demonstrates the use of the LM 100 as a
switching regulator. Feedback to the inverting
input of the operational amplifier (Pin 6 of the
LM 100) is obtained through a resistive divider
which can be used to set the output voltage anywhere in the 2-30V range. R3 determines the base
drive for the switch transistor, 0 1 , providing
enough drive to saturate it with maximum load
current. R4 works into the 1 kr2 impedance at the
reference terminal, producing the positive feedback. C2 serves to minimize output ripple by
causing the full ripple to appear on the feedback
terminal. The remaining capacitor, C3 , removes
the fast-risetime transients which would otherwise
be coupled into Pin 5 through the shunt capaci"
tance of R4 .lt must be made small enough so that
it does not seriously integrate the waveform at this
point.

AN2-3

The circuit shown in Figure 5 is suitable for output currents as high as 500 mAo This limit is set by
the output current available from the LM 100 to
saturate the switch transistor, Q1' For lower currents, the value of R3 should be increased so that
the base of Q 1 is not driven unnecessarily hard.

(3)

I n order for the peak current to be about 1.2 times
the maximum load current, it is necessary that

R4
2M

01
F06666

peak currents which are significantly' larger than
the load current. The change in inductor current
can be written as

L1

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2.5 VOUTtoff
lOUT

(max)

.

(4)

A value for toft can be estimated from

R2
2.27K
1%

toff =

f1

(

VOUT)
1- ~ ,

(5)

r

V1N

18-4DV

where f is the desired switching frequency and V 1N
is the nomi nal input voltage.

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The size of the output capacitor can now be determined from

FIGURE 5
Switching Regulator Using the.LM100

C = (VIN - VOUT) (VOUT)2
1
2L1 ~VOUT
fV 1N '
The optimum switching frequency for these regulators has been determined to be between 20 kHz
and 100 kHz. At lower frequencies, the core
becomes unnecessarily large; and at higher fre. quencies, switching losses in Q 1 and D1 become
excessive. It is important, in this respect, that both
Q 1 and D1 be fast-switching devices to minimize
switching losses.
The output ripple of the regulator at the switching
frequency is mainly determined by R4 . It should
be evident from the description of circu it operation that the peak-to-peak output ripple will be
nearly equal to the peak-to-peak voltage fed back
to Pin 5 of the LM 100. Since the resistance looking into Pin 5 is approximately 1000n, this voltage will be

(2)

(6)

where ~ V OUT is the peak-to-peak output ripple
and V IN is the nominal input voltage.
.

It now remains to determine if the component
values obtained above give satisfactory loadtransient response. The overshoot of the regulator
can be determined from
L1 (~IL)'2
LlVOUT=C 1 (V IN - V OUT )

(7)

for increasing loads, and
2

L1 (Llld
~VOUT=CV
1 OUT

(8)

for decreasing loads, where Lli L is the load-current
transient. The recovery time is
2L1~IL

In practice, the ripple will be somewhat larger than
this. When the switch transistor shuts off, the current in the inductor will be greater than the load
current so the output voltage will continue to rise
above the value requ ired to shut off the regu lator.
An important consideration in choosing the value
of the inductor is that it be large enough so that
the current through it does not change drastically
during the switching cycle. If it does, the switch
transistor and catch diode must be able to handle

AN2-4

tr = V

IN -

V

(9)

.
OUT

and
2L1~1 L
t =--r
V OUT

(10)

for increasing and decreasing loads respectively.
In order to improve the load transient response, it
is necessary to allow larger peak to average current

ratios in the switch transistor and catch diode.
Reducing the value of inductance given by Equation (4) by a factor of 2 wi II reduce the overshoot
by 4 times and halve the response time. This, of
course, assumes that the output capacitance is
doubled to maintain a constant switching frequency.
The above equations outline a design procedure
for determining the value for R 4 , L 1 , and C1 ,
given the switching frequency and the output
. ripple. These equations are not exact, but they do
provide a starting point for designing a regulator to
fit a given application.

More exact expressions would involve a design
procedure which is too cumbersome to be of
practical value.

The variation of switching frequency with input
voltage and load current is shown in Figures 6 and
7. The sharp rise in frequency .at low output currents happens because the output transistor of the
LM 100 (Q12) begins to supply an appreciable
portion of the load current directly.

The efficiency of the regulator over a wide range
of input voltages and output currents is given in
Figures 8and 9.

As ar) example, this design method will be applied
to a regulator which must deliver 15V at a maximum current of 300 mA from a 28V supply. To
start, a 40 kHz switching frequency will be
selected along with an output ripple of 14 mV,
peak-to-peak.
tOO

From (2), R4 is calculated to be 2 MD. In determining L 1 , toff is found to be 11.6 ps from (5).
Inserting this into (4) gives a value of 1.45 mH for
L 1 . The value of C1 obtained from (6) is then 57.5
pF.

90

1

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70

60
:;:: 50

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-

~

40

i: 30

VIN = 2BV

Co)

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iiiii"'"

1.,..00 j...ooo ....

~
::I

t:I

In the actual circuit of Figure 5, a standard value
of 47pF is used for C1 ; and L1 is adjusted to 1.7
mH. The switching frequency obtained experimentally on this circuit is 60 kHz and the peak-topeak output ripple is 20 mV. The fairly-large disagreement between the calculated and experimental values is not alarming since many simplifying assumptions were made in the derivation of the
equations. They do, however, provide a convenient
method of handling a large number of rnutuallydependent variables to arrive at a working circuit.

[\

N

20
10

o
o

100

200

300

400

500

OUTPUT CURRENT (mA)

FIGURE 7
Switching Frequency as a Function of Output
Current

100

90

........

~- ~

§!

70 f - - f - -

IL = 300 mA

60
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~

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-,..

..-

80

-

40

f--

30
20
10

20~~-k--~~~~--~~

10

15

20

25

30

35

40

45

o

50

INPUT VOLTAGE (V)

o

5

10

15

20

25

30

35

40

INPUT VOLTAGE (V)

FIGURE 6
Switching Frequency as a Function of Input
Voltage
.

FIGURE 8
Efficiency as a Function of Input Voltage

AN2-5

lOO

90
80

~

10

-

~~-

,

~

60
>
u
~ 50
40
30

VIN = 28V

~

20
10

o
o

100

200

300

400

500

OUTPUT CURRENT (mA)

FIGURE 9
Efficiency as a Function of Output Current

HIGHER CURRENT REGULATORS

FIGURE 11

If output currents greater than about 500 mA are
required, it is necessary to add another switch
transistor to obtain more current gain. This is
illustrated in Figure 10. With the exception of the
added NPN power switch, Q2, this circuit is the
same as that described previously.
A photograph of a high-current regulator is shown
in Figure 11. It is capable of delivering output currents of 3A continuously with only a small heat
sink. Figure 12 shows that the efficiency is better
than 80 percent at this level. Output currents to
5A can be obtained at reduced efficiency. However, the case temperature of the power switch and
catch diode approach 10aoe under this condition,
so continuous operation is not recommended
unless more heat sink is provided.

High Current Switching Regulator

100
90

~

-.

80
70

T"""-"'-

r- ~ I'--

VIN = 28V

> 60
~ 50
U
40
u

~

30
20
- - ----

10

--f--

0
0

1.0

4.0
2.0
3.0
OUTPUT CURRENT (A)

5.0

FIGURE 12
Efficiency as a Function of Output Current

Your

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FIGURE 10
Switching Regulator for Higher Output
Currents

AN2-6

Figure 13 shows that the efficiency is not significantly affected by input voltage. In Figure 14 it
can be seen that the switching frequency is fairly
constant over a wide range of input voltages. F igure 15 shows that the switching frequency
increases with increasing load current. The higher
dc current through the inductor reduces the incremental inductance causing the frequency to go up.
The last graph, Figure 16, illustrates the line regulation of the device. this can be improved by
putting a small capacitor (0.01 I1F) in series with
the positive feedback resistor, R3 , to isolate the
reference termi nal from the de input voltage
changes.

100

10.30

90 - - ,
10.20

--

80

~

70

w

IL = 1A

C. 60
>

t:I

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~ 50

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30

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10.10

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10.00

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9.90

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20

9.80

10
0

9.70
0

10

5

15

25

20

30

35

40

INPUT VOLTAGE (V)

/
I(

::)

d

-

........

"

~

i

5

o

o

10

15

20

15

20

25

30

35

40

The use of solid tantalum capacitors for C1 and C3
is recommended when the regulator is expected to
perform over the full military temperature range.
The reason for using 35V capacitors on the output, even though the output voltage is only 1OV, is
that the 40 mV peak-to-peak ripple on the output
would, for example, exceed the ratings of a
100 pF, 15V capacitor.

,I

~ 10

t.)

10

At low output currents the inductor current can
drop to zero at some time after the switch transistor turns off. When this happens, ringing occurs
on the switching waveform. This is perfectly
normal and causes no ill effects.

IL = 1A

J

~ 15

t:I

5

FIGURE 16
Line Regulation

30

>
~ 20

o

INPUT VOLTAGE (V)

FIGURE 13
Efficiency as a Function of Input Voltage

~ 25

-- -

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ct

t.)

c:;

I

IL = 1.0A

25

30

35

40

INPUT VOLTAGE (V)

Aluminum electrolytic capacitors have been used
successfully over a limited temperature range. And
there is basically no reason why wet foil or wet
slug tantalums could not be used as long as their
equivalent series resistanc~ is low enough so that
they behave like capacitors with the high frequency switched-current waveform. It is also
important that manufacturer's data be consulted
to insure that they can withstand the high frequency ripple.

FIGURE 14
Variation of Switching Frequency with
Input Voltage

50
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15
10

As was mentioned with the low current regulator,
it is necessary to use fast-switching diodes and
transistors in these circuits. Ordinary silicon rectifiers or low-frequency power transistors will
operate at drastically-reduced efficiencies and will
quickly overheat in these circuits.

DRIVEN SWITCHING REGULATOR

o

1.0

2.0

3.0

4.0

OUTPUT CURRENT (A)

FIGURE 15
Variation of Switching Frequency with Output Current

5.0

When a number of switching regulators are used
together in a system it is sometimes desirable to
synchronize their operation to more uniformly
distribute the switched current waveforms on the
input line. Synchronous operation is also wanted

AN2-7

when a switching regulator is operated in conjunction with a power converter.
A circuit for synchronizing the switching regulator
with a square wave drive signal is shown in Figure 17. In this circuit, positive feedback is not
used. I nstead, the square wave drive signal is
integrated; and the resulting triangular wave
(about 40 mV peak-to-peak) is applied to the
reference bypass termi nal of the LM 100. This triangular' wave will cause the regulator to switch
since its gain is so high that the waveform overdrives it. The duty cycle of the switched waveform
is controlled by the voltage on the feedback
terminal, Pin 6. If this voltage goes up, the duty
cycle will decrease since it is picking off a smaller
portion of the triangular wave on Pin 5. By the
same token, the duty cycle will decrease if the
voltage on Pin 6 drops.

01
lN3880

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*Basing diagram is Top View
tSolid tantalum
t'00 turns #22 on Arnold Engineering
A930157·2 molybdenum permalloy core

FIGURE 17

Driven Switching Regulator

This.action produces the desired regulation: if the
output voltage starts to go up, it will raise the
voltage on Pin 6 such that ~ smafler portion of the
triangular wave is picked off. This reduces the
duty cycle, counteracting the output voltage
increase.
In order for this circuit to work properly, the
ripple voltage on Pin 6 should be less than a
quarter of the peak-to-peak amplitude of the triangular-wave. I f this condition is not satisfied, the
regulator will try to oscillate at its 9wn frequency.
Further, since the resistance looking into Pin 5 is

about 1 kn, the integrating capacitor, C 3 , shou Id
have a capacitive reactance of less than 100n at
the drive frequency. The value of R3 is determined
so that the amplitude of the triangular wave on
Pin 5 is about 40 mV.
Driven regu lators also have other advantages. For
one, it is possible to design the LC filter independent of switching frequency considerations.
Hence, lower output ripple and better transient
response can be realized. A second advantage is the
frequency stability. In ,a self-oscillating regulator,
the switching frequency is controlled by a relatively large number of factors. As a resu It, it is not
well determined when normal tolerances are taken
into account. With low and medium power
regulators, this is not usually a problem since the
efficiency does not vary greatly with frequency.
However, high power regulators tend to be more
frequency sensitive and it is desirable to operate
them at constant frequency.

CURRENT LIMITING
I n the circuits described previously, the regulator
is not prote'cted from overloads or short-circuited
output. Providing short-circuit protection is no
simple problem, since it is necessary to keep the
regulator switching when the output is shorted .
Otherwise, the dissipation will become eKcessive
even though the current is limited.
A circuit that does this is shown in Figure 18. The
peak current through the switch transistor is
sensed by R6 . When the voltage' drop across this
resistor becomes large enough to turn on Q3, the
oU1:putvoltage begins to fall since current is being
supplied to the feedback terminal of the regulator
from the collector of 0 3 so less has to be supplied
from the output through R l ' Furthermore, the circuit will continue to oscillate, even with a shorted
output, because of positive feedback through R6
and the relatively-long discharge time constant of
C2 ·
It is necessary to put a resistor, R 7 , in series with
the base of 0 3 to insure that excessive current will
not be driven into the base. I n addition, a
capacitor, C4 , must be added across the input of
0 3 so that i,t does not turn on prematurely on the
large current spike (about twice the load current)
through the switch transistor caused by pu II ing the
stored charge out of the catch diode. A zener
diode bias supply must also be used on the output
of the LM 100 since the current lim iting will not
work if the voltage on this point drops below
about1V.
'

..-------,------'

~-------~---------:--------------:--------:-~---~-~-

AN2-8

1.0

R4
10K

VIN >8.5V

01
5V

R3
L11'

~,

_ .75

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~

....z

22
VOUT

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+

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5.5K
1%

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...

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V

~ .50

~

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u

....

VIN ~ 28V

c:a.

~ .25

V- -

f--- -

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~

V

::I

\
\

-----

o

0.5 1:0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

R2
3.1K

OUTPUT CURRENT (AI

1%

FIGURE 20
Illustrating Drop in I nput Current as Regulator Goes Into Limiting
R9
lK

*Basing diagram is Top View
tSolid tantalum
f70 turns #20 on Arnold Engineering
A930157·2 molybdenum permalloy core

FIGURE 18
Switching Regulator with Current limiting

The current limiting characteristics of this circuit
are shown in Figure 19. Figure 20 shows how the
average input current actually drops off as the circuit goes into current limiti.ng.

difficult to prove that the circuit will sustain a
continuous short circuit under worst-case conditions. This is particularly true with high current
regulators where the required amount of overdesign can become quite expensive.
Figure 21 shows a circuit which is more easily
designed for continuous short-circuit protection
under worst-case conditions. I n this circuit, the
current-sensing resistor is located in series with the
inductor. Therefore, the peak-limiting current can
be more precisely determined since the current
spike generated by pulling the stored charge out of
the catch diode does not flow through the sense
resistor.

This current limiting scheme protects the switching transistors from overload or short-circuited
output. However, the drop-out current and shortcircuit current are not well controlled, so it is

,

5.05
5.00

E

4.95

Cl:I

4.90

...

....c
....
Q

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....
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Q

~
V

4.0

VIN = 28V

3.0
2.0
1.0

o

,

1\
\

\

0.5 1.0 1.5

2;0

2.5 3.0 3.5 4.0 4.5

*Basing diagram is Top View
tSolid tantalum
1'70 turns #20 on Arnold Engineering
A930157·2 molybdenum permalloy core

OUTPUT CURRENT (AI

FIGURE 19
Current limiting Characteristics

FIGURE 21
Switching Regulator with Continous Short·
Circuit Protection

AN2-9

NEGATIVE REGULATORS

5.05
5.00
~ 4.95

~

4.90

~
o
>

/'t-

/'To

4.0

~

I

V1N =28V

I-

3.0

All circuits discussed thus far are for regulators
with positive outputs. Although negative regulators can be obtained by floating the unregulated
supply and grounding the output, this is not
always convenient.

I-

g

2.0
1.0

o

.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (A)

FIGURE 22
Current Limiting Characteristics

Figure 24 shows a circuit for a negative switching
regulator where the unregulated input and regulated output have a common ground. The only
limitation of the circu it is that there must be a
positive voltage greater than 3V available in order
to properly bias the negative regulator.

,--.f-......--...-'I1I1I1'..........- -....- - - - - VOUT =5V

1.0

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.75

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~ .25

/

/

/

/

~.~V to 35V -1-+-..----(A_

V1N = 28V
C4 ":"
0.1 IlF

/
o
.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (A)

.....--+----+-- VOUT = -5V

FIGURE 23
Plot of I nput Current as Regulator Goes
I nto Limiting

Rll
750

Operation of this circuit is essentially the same as
the previous one in that an NPN transistor, 0 4 ,
senses the overcurrent condition and turns on 0 3
which supplies the current-limit signal to the feedback terminal. The zener diode, D 3 , is required on
the feedback terminal to guarantee that this terminal cannot go more than O.5V higher than Pin 1.
If this does happen, the circuit can latch up and
burn out. The performance of this current-limiting
scheme is illustrated in Figures 22 and 23.

FIGURE 24
Positive and Negative Switching Regulators

With this circuit it is not only possible to more
accurately determine the limiting current, but as
can be seen from Figures 22 and 23, the limiting
characteristic is considerably sharper. One disadvantage of this circuit is that the load current
flows continuously through the current sense
resistor, reducing efficiency. As an example, with a
5V regulated output the efficiency will be reduced
by 10 percent at full load.

In this circuit, the normal output terminal of the
LM100 (Pin 8) is grounded and the ground terminal (Pin 4) is connected to the regulated negative output. Hence, as before, it regulates the voltage between the output and ground terminals. The
unregulated input terminal (Pin 3) is run from a
positive voltage for proper biasing. A PNP booster

AN2-10

~6~ to - 3 5 V - + - - -.....-.....,

*Basing diagram is Top View
tSolid tantalum

t60 turns #20 on Arnold Engineering
A930157·2 molybdenum p.ermilloy core

transistor, 03, is connected in the normal manner;
and it drives a Darlington-connected NPN switch.
Positive feedback is developed by the resistive
divider, Ra and R12.
It is necessary to use a Darlington switch even
though the current gain is not needed. The power
switch transistor, 04, cannot be operated with a
fixed base drive: if the base drive is made large
enough to insure saturation at maximum load current, it will overstore so badly at lower currents
that the output ripple will increase radically. With
the extra transistor, however, it is kept out of saturation at lower output currents, eliminating the
problem.

SWITCHING AND LINEAR REGULATOR
COMBINATION
I n certain applications, the output ripple and load
transient response requ irements ru Ie out the use of
a switching regulato'r, yet the input-output voltage
differential is still high. In th is case, a power converter might be used to reduce the input voltage
and this reduced voltage would be regulated by a
linear regulator. This arrangement, however, is not
nearly as efficient as the switching and linear regulator combination shown in Figure 26. The
switching regulator not only reduces the input
voltage with high efficiency, but it also regulates
it. Therefore, the linear regulator operates with a
fixed input-output voltage differential which holds
dissipation to a minimum.

HIGH VOLTAGE REGULATORS
With switching regulators, an application can easily
arise where the input voltage can be higher than
the 40V maximu m rating of the LM 100, even
though the output voltage is within the 30V maximum. As shown in Figure 25, it is possible to
isolate the LM100 from the unregulated supply so
that it can be used with input voltages limited only
by the switch transistors and the catch diode.

-+-...........--oooo{31.

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• Basing diagram is Top View
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.....- -.....-.-+-V,N >40V

t60 turns #20 on Arnold Engineering
A9J0157·2 molybdenum permalloy core

*Basing diagram is Top View
tSolid tantalum
t50 turns Jt20 on Arnold Engineering
A9J0157·2 molybdenum permalloy core

FIGURE 25
Switching Regulator for High-voltage Inputs

I n this circu it, the voltage seen by the LM 100 is
ma intained at a fixed level within ratings by the
zener diode, D 2 . The zener voltage must be at least
3V greater than the output voltage. The output of
the LM100 is level-shifted up to the input voltage
by an additional NPN transistor, 0 3 , which is
operated common base. This drives the PNP switch
driver in the normal manner.

FIGURE 26
Switching and' Linear Regulator Combination for Obtaining Very Low Ripple and Fast
Transient Response

In this circuit, the linear regulator is biased by a
zener pre-regu lator (R 9, D 2 and 0 5 ) to isolate it
from. noise on the unregulated supply. This
separate bias supply permits the linear pass transistor, 0 3 , to operate right down into saturation.
The collector of 0 3 is supplied by the output of a
switching regulator which is made enough higher
than the linear regulator output to allow for the
maximum overshoot of the switching regulator
plus the saturation of 0 3 ,

AN2-11

SUMMARY
A number of switching regulator circuits which use
a readily-available monolithic voltage regulator as
the voltage reference and control circuitry have
been described. These regulators are useful over a
2V to 30V range for either positive or negative
supplies. Although the discussion was limited to
circuits providing maximum output currents from
100 mA to 5A, it is possible to obtain even higher
output currents. The output current is, in fact,
limited by the discrete components - not by the
basic design or the integrated circuit.

The majority of the circuits shown were selfosc i lIating regulators; however, a method of

AN2-12

driving the regulator in synchronism with an
external clock signal was given. I n addition, circuits which provide overload protection, limiting
both the output current as well as the power dissipation, were presented. The performance of the
regulator circuits was described in detail, and a
design procedure was outlined. Suggestions were
also made on the selection of components for
switching regulators.
The circuits which have been described here for
the LM 100 work equally well with the LM200
or the LM300. These devices are identical, except
that the LM200 is specified over a -25°C to 85°C
temperature range and the LM300 is specified from
O°C to 70°C instead of the -55°C to 125°C
temperature range for the LM 100.

»

z
November 1967

I

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o
3:

DRIFT COMPENSATION TECHNIQUES
FOR INTEGRATED DC AMPLI FI ERS

"'0

m
Z

INTRODUCTION

en

With DC amplifiers, it is usually possible to
substantially improve drift performance by using
additional circuitry along with some form of adjustment. In fact, one of the reasons that discretecomponent operational amplifiers have better input'
current specifications than monolithic amplifiers'
is that current compensation is used. Monolithic
circuits cannot incorporate these techniques because it is not possible to select components or
make adjustments. These adjustments can, however, be made external. to the amplifier. This
article will discuss a number of compensation
methods which can substantially reduce the input
currents of monolithic amplifiers, especially in
lim ited-temperature-range appl ications.
Bias current compensation reduces offset and drift
when the amplifier is operated from high source
resistances. With low source resistances, such as a
thermocouple, the drift contribution due to bias
current can be made quite small. In this case, the
offset voltage drift becomes important.
A technique is presented here by which offset voltage drifts better than 0.5 J.1V;oC can be realized.
The compensation technique involves only a single
room-temperature balance adjustment. Therefore,
chopper-stabilized performance can be real ized,
with low source resistances, in a fairly-simple amplifier without tedious cut-and-try compensation
methods.
BIAS CURRENT COMPENSATION
The simplest and most effective way of compensating for bias currents is shown in Figure 1. Here,
R2
lOOK

..

lOOK

AJ
lSDK

CI
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FIGURE 1. Summing Amplifier with Bias-Current
Compensation for Fixed Source
Resistances.

the offset produced by the bias current on the
inverting input is cancelled by the offset voltage
produced across the variable resistor, R3 . The
main advantage of this scheme, besides its simplicity, is that the bias currents of the two input

transistors tend to track well over temperature so
that low drift is also achieved. The disadvantage
of the method is that a given compensation setting
works only with fixed. feedback resistors, and the
compensation must be readjusted if the equivalent
parallel resistance of R 1 and R2 is changed.
Figure 2 shows a similar circuit for a non-inverting
amplifier. The offset voltage produced across the
DC resistance of the source due to the input
.2

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FIGURE 2. Non-Inverting Amplifier with Bias-Current
Compensation for Fixed Source Resistances.

current, is cancelled by the drop across R3 . For
proper adjustment range, R3 should have a maximum value about three times the source resistance
and the equivalent parallel resistance of R1 and R2
should be less than one-third the input source
resistance.
This circuit has the same advantages as that in
Figure 1, however, it can only be used when the
input source has a fixed DC resistance, In many
applications, such as long-interval integrators, sample-and-hold circuits, switched-gain amplifiers or
'Ioltage followers operating from unknown source,
the source impedance is not defined. In these cases
other compensation schemes must be used.
Figure 3 gives a compensation technique which
does not depend upon having a fixed source resistance. A current is injected into the input terminal
from the base of a PNP transistor. Since NPN input
transistors are used on the integrated amplifier, *
the base current of the PNP balances out the base
current of the NPN. Further, since a silicon-planar
PNP transistor has approximately the same currentgain versus temperature characteristic as the integrated transistors, an improvement in temperature
drift will also be realized. t However, perfect

*This is true for all monolithic operational amplifiers presently available.
tlf the operational amplifier uses a Darlington input stage,
however, the drift compensation will not be nearly as
good.

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30pF

FIGURE 3. Summing Amplifier with Bias·Current
Compensation.

. compensation should not be expected because of
unit-to-unit variations in the temperature characteristics of both the PNP transistor and the integrated circuit.
Although the circuit in Figure 3 works well for the
summing amplifier connection, it does have limitations in other applications, It could, for example,
be used for the voltage follower configuration by
connecting the base of the PNP to the non-inverting
input. However, this would reduce the input impedance (to about 150 MS1) because the current
supplied by the PNP will vary with the input
voltage level.

10' lifO

,nputcun.nt

FIGURE 5. Voltage Follower with Bias-Current
Compensation.

compensating current does not change appreciably
with signal level, giving input impedances about
1000 MS1. The negative temperature coefficient of
the diode voltage also provides some temperature
compensation.
All thecircuitsdiscussed thus far have been tailored
for particular applications. Figure 6 shows a completely-general scheme wherein both inputs are

If this characteristic is objectionable, the morecomplicated circuit shown in Figure 4 can be used.

"

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tor lelO onput CUII!nt on

non 'flyt.lln~ onput
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FIGURE 6. Bias-Current Compensation for
Differential Inputs.

FIGURE 4. Bias-Current Compensation for Non-Inverting
Amplifier Operated Over Large Common
Mode Range.

The emitter of the PNP transistor is fed from a
current source so that the compensating current
does not vary with input-voltage level. The design
of the current source is such as to give it about the
same characteristics as those on the input stage of
the better monolithic amplifiers:!: to give closer compensation with changes in temperature and supply
voltage. The circuit makes use of the emitter base
voltage differential between two transistors operated at different collector currents. 1 ,2 Although it
is recommended ih the references that these transistors be well matched, it is not really necessary
since the devices are operated at much different
collector currents.

current compensated over the full common mode
range as well as against power supply and temperature variations. This circuit is suitable for use
either as a summing amplifier or as a noninverting amplifier. It is not required that the DC
impedance seen by both inputs be equal, although
lower drift can be expected if they are.
As was mentioned earlier, all the bias compensation circuits require adjustment. With the circuits
in Figures 1 and 2, this is merely a matter of
adjusting the potentiometer for zero output with
zero input. It is not so simple with the other
circuits, however. For one, it is difficult to use
potentiometers because a very wide range of resistance values are required to accommodate expected
unit-to-unit variations. Resistor selection must
therefore be used. Test circuits for selecting bias
compensation resistors are given in Figure 7.
CI
10{JpF

Figure 5 shows another compensation scheme for
the voltage follower connection .. This circuit is
much simpler than that shown in Figure 4, but the
temperature compensation is not quite as good. The
compensating current is obtained through a resistor
connected across a diode which is bootstrapped to
the output. The diode acts as a regulator so that the
:j:The 709 and the LM101.

AN3-2

FIGURE 7. Test Circuits for Selecting
Bias-Compensation Resistors.

OFFSET VOLTAGE COMPENSATION
The highly predictable behavior of the emitter-base
voltage of transistors has suggested a unique drift
compensation method; it is shown in Reference 3
that the offset voltage drift of a differential transistor pair can be reduced by about an order of
magnitude by unbalancing the collector currents
such that the initial offset voltage is zero. The basis
for this comes from the equation for the emitterbase voltage differential of two transistors operating
at the same temperature:

,"

'M'"

8

>--OU,"UI

~----'+

CI
30pf

(1)
FIGURE 8. Example of a DC Amplifier Using
the Drift-Compensation Technique.

where k is Boltzmann's constant, T is the absolute
temperature, q is the charge of an electron, Is is a
constant which depends only on how the transistor
is made and Ie is the collector current. This
equation is derived in Reference 2.
It is worthwhile noting here that these expressions
make no assumptions about the current gain of the
transistors. It is shown in Reference 5 and 6 that
the emitter-base voltage is a function of collector
current not emitter current. Therefore, the balance
will not be upset by base current (except for
interaction with the DC-source resistance).
The first '~erm in Equation (1) is the offset voltage
of the two transistors for equal collector currents.
It can be seen that this offset voltage is directly
proportional to the absolute temperature - a fact
which is substantiated by experiment. 4 The second
term is the change of offset voltage which arises
from operating the transistors at unequal collector
currents. For a fixed ratio of collector currents,
this is also proportional to absolute temperature.
Hence, if the collector currents are unbalanced in
a fixed ratio to give a zero emitter-base voltage
differential, the temperature drift will also be zero.
Experiment indicates that this is indeed true. Thermal drifts less than 100 J1V over the _55° C to
+125°C temperature range have been realized consistently. In order to obtain these low drifts,
however, it is almost necessary to use a monolithic transistor pair, since a 0.05°C temperature
differential will give a 100 J1V drift. With a monolithic pair, the physical proximity of the devices as
well as the high thermal conductivity of silicon
holds this differential to an absolute minimum.
For low drift, the transistors must operate from a
low enough source resistance that the voltage drop
across the source due to base current (or base
current differential if both bases see the same
resistance) is insignificant. Furthermore, the transistors must be operated at a low enough collector
current that the em itter-contact and base-spreading
resistances are negligible, since Equation (1) assumes
that they are zero.

output for zero input, unbalances the collector load
resistors of the transistor pair such that the collector currents are unbalanced for zero offset. This
gives minimum drift. An interesting feature of the
circuit is that the performance is relatively unaffected by supply voltage variations: a 1 V change
in either supply causes an offset voltage change of
about 10 J1V. This happens because neither term in
Equation (1) is affected by the magn itude of the
collector currents.
In order to get low drift, it is necessary that the
gain of the preamplifier be high enough so that the
drift of the operational amplifier does not degrade
performance. The gain can be determined from the
expression for the transconductance of the input
transistors:

(2)

The voltage gain is
(3)

(4)

where R L is the average value of the two collector
load resistors on the input stage and Ie is the
average of the two collector currents.
Substituting Equation (2), this becomes
(5)

=

qV RL
kT

(6)

The input referred drift is then
A complete amplifier using this principle is shown
in Figure 8. A monolithic transistor pair is used as
a preamplifier for a conventional operational amplifier. A null potentiometer, which is set for zero
AN3-3

SUMMARY

where I:l. Vas is the offset voltage drift of the
operational amplifier and I:l.las is its offset current
drift.

A number of compensation circuits designed to
increase the DC resolution of monolithic operational amplifiers have been presented. Both current
compensation techniques for high impedance levels
as well as methods of achieving chopper-stabilized
drift performance at low impedance levels have
been covered.

Using Equation (7);

·1

With the circuit shown in Figure 8, Equation (8)
gives a 25 J1V input-referred drift for every 10 mV
of offset voltage drift or for every 100 nA of offset
current drift. It is obvious from this that the offset
current drift rs most important if an operational
ampl ifier with bipolar input transistors is used.
Another important .consideration is the matching
of the collector load resistors on the preamplifier
stage. A O.l-pe~cent imbalance in the load resistors
due to thermal mismatches or any other cause will
produce a 25 J1V shift in offset. This includes .the
bi;llancing potentiometer which. can introduce an
error that will depend on how far it is set off midpoint if it has a different temperature coefficient
than the resistors.
.
The most obvious use of this type of low drift
amplifier is with thermocouples, magnetometers,
current shunts, wire strain gauges or similar signal
sources where very low drift· is required and the
source resistance is low enough that the bias
currents do not cause a problem. The 0.5 to 1 J1V /
°c drift * realized with this relatively simple amplifier over a -55°C to +125°C temperature range
compares favorably with the drift figures achieved
with chopper amplifiers: 0.4 jJvfc for mechanical
choppers, 0.5 J1V;oC with photoelectric choppers
over a O°C to 55°C temperature range and 2 J1V
with field-effecHransistor choppers over a -55°C
to +125°C temperature range. In order to give some
appreciation of the level of performance, it is
interesting to note that no substantial improvement
in performance would be realized by operating the
amplifier in a temperature-controlled oven. Any
improvement would be masked by various thermoelectric effects not directly associated with the
amplifier unless extreme care were taken in the
choir.e of input lead material, the method of making connections and the balancing of thermal paths.
These Jactors are, in fact, important when making
oven tests to verify the drift of the amplifier since
thermoelectric effects can easily produce drift
voltages larger than those of the amplifier if they
are not properly handled.

tc

*Drifts of 0.05 J..tvtc over a 0-50°C temperature range
were reported in Reference 3 using matched discrete
transistors in one can.

AN3-4

Fairly-simple current compensation which requires
that the impedance levels be fixed have been described along with compensation which is effective
in cases where the source impedance is not well
defined. This latter category includes long-interval
integrators, sample-and-hold circuits, switched-gain
amplifiers or voltage followers which operate from
an unknown source. The application of these
schemes is generally limited to integrated amplifiers
since modular amplifiers almost always incorporate
current compensation.
The drift-reduction techniques provide stabilities
better than 0.5 J1V
for low impedance sources,
such as thermocouples, current shunts or strain
gauges. With a properly designed circuit, compensation depends only on a single room temperature
adjustment, so excellent performance can be. obtained from a fairly-simple amplifier.

tc

REFERENCES
1. R. J. Widlar, "A Unique Circuit Design for a
High Performance Operational Amplifier Especially Suited to Monolithic Construction," Proc.
of NEC, Vol. XXI, pp. 85-89, October, 1965.

2. R. J. Widlar, "Some Circuit'Design Techniques
for Linear Integrated Circuits," IEEE Trans. on
Circuit Theory, Vol. XII, pp. 586-590, December, 1965.
3. A. H. Hoffait and R. D. Thorton, "Limitations
of Transistor DC Amplifiers," IEEE Proc., Vol.
52, pp. 179-184, February, 1964.
4. A. Tuszynski, "Correlation Between the BaseEmitter Voltage and Its Temperature Coefficient," Solid State Design, pp. 32-35, July,
1962.
5. C. T. Sah, "Effect of
and Channel on P-N
Characteristics," IRE
vices, Vbl. ED-9, pp.

Surface Recombination
Junction and Transistor
Trans. on Electron De94-108, January, 1962.

6. J. E. Iwersen, A. R. Bray, and J. J.Kleimack,
"Low-Current Alpha in Silicon Transistors,"
IRE Trans. on Electron Devices, Vol. ED-9,
pp. 474-478, November, 1962.

l>

2
April 1968

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MONOLITHIC OPERATIONAL AMPLIFIERSTHE UNIVERSAL LINEAR COMPONENT

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INTRODUCTION

OPERATIONAL-AMPLIFIER OSCILLATOR

Operational amplifiers are undoubtedly the easiest
and best way of performing a wide range of linear
functions from simple amplification to complex
analog computation. The cost of monolithic amplifiers is now less than $2.00, in large quantities,
which makes it attractive to design them into circuits where they would not otherwise be considered. Yet low cost is not the only attraction of
monolithic amplifiers. Since all components are
simultaneously fabricated on one chip, much higher
circuit complexities than can be used with discrete
amplifiers are economical. This can be used to give
improved performance. Further, there are no insurmountable technical difficulties to temperature stabilizing the amplifier chip, giving chopper-stabilized
performance with little added cost.

The free-running multivibrator shown in Figure 1
is an excellent example of an application where one
does not normally consider using an operational
amplifier. However, this circuit operates at low frequencies with relatively small capacitors because it
can use a longer portion of the capacitor time constant since the threshold point of the operational
amplifier is well determined. In addition, it has
a completely-symmetrical output waveform along
with a buffered output, although the symmetry can
be varied by returning R2 to some voltage other
than ground.

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m

Operational amplifiers are designed for high gain,
low offset voltage and low input current. As a result, dc biasing is considerably simplified in most
applications; and they can be used with fairly simple design rules because many potential error terms
can be neglected. This article will give examples
demonstrating the range of usefulness of operational amplifiers in linear circuit design. The examples
are certainly not all-inclusive, and it is hoped that
they will stimulate even more ideas from others. A
few practical hints on preventing oscillations in
operational amplifiers will also be given since this
is probably the largest single problem that many
engineers have with these devices.

Although the designs presented use the LM101 operational amplifier and the LM 102 voltage follower
produced by National Semiconductor, most are
generally applicable to all monolithic devices if the
manufacturer's recommended frequency compensation is used and differences in maximum ratings
are taken into account. A complete description of
the LM101 is given elsewhere;l but, briefly, it differs from most other monolithic amplifiers, such
as the LM709,2 in that it has a ±30V differential
input voltage range, a +15V, '-12V common mode
range with ±15V supplies and it can be compensated with a single 30 pF capacitor. The LM102,3
which is also used here, is designed specifically as a
voltage follower and features a maximum input
current of 10 nA and a 1OV /J.1s slew rate.

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FIGURE 1. Free-Running Multivibrator

Another advantage of the circuit is that it will
always self start and cannot hang up since there is
more dc negative feedback than positive feedback.
This can be a problem with many "textbook"
multivibrators.

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Since the operational amplifier is used open loop,
the usual frequency compensation components are
not required since they will only slow it down. But
even without the 30 pF capacitor, the LM101 does
have speed limitations which restrict the use of this
circuit to frequencies below about 2 kHz.

The large input voltage range of the LM101 (both
differential and single ended) permits large voltage
swings on the input so that several time constants
of the timing capacitor, Cl, can be used. With most
other amplifiers, R2 must be reduced to keep from
exceeding these ratings, which requires that C1 be
increased. Nonetheless, even when large values are
needed for Cl, smaller polarized capacitors may be
used by returning them to the positive supply voltage instead of ground.

AN4--l

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LEVEL SHIFTING AMPLIFIER

VOLTAGE COMPARATORS

Frequently, in the design of linear equipment, it is
necessary to take a voltage which is referred to
some dc level and produce an amplified output
which is referred to ground. The most straightforward way of doing this is to use a differential
amplifier similar to that shown in Figure 2a. This
circuit, however, has the disadvantages that the
signal source is loaded by current from the input
divider, R3 and R4, and that the feedback resistors must be very well matched to prevent erroneous outputs from the common mode input signal.

The LM 101 is well suited to comparator applications for two reasons: first, it has a large differential input voltage range and, second, the output is
easily clamped to make it compatible with various
driver and logic circuits. It is true that it doesn't
have the speed of the LM71 04 (10 /1s versus 40 ns,
under equivalent conditions); however, in many
linear applications speed is not a problem and the
lower input currents along with higher voltage capabil ity of the LM 101 is a tremendous benefit.

A circuit which does not have these problems is
shown in Figure 2b. Here, an FET transistor on
the output of the operational amplifier produces
a voltage drop across the feedback resistor, R 1,
which is equal to the input voltage. The voltage
across R2 will then be equal to the input voltage
multiplied by the ratio, R2/R 1; and the common
mode rejection will be as good as the basic rejection of the amplifier, independent of the resistor
tolerances. This voltage is buffered by an LM 102
voltage follower to give a low impedance output.

Two comparator circuits using the LM 101 are
shown in Figure 3. The one in Figure 3a shows a
clamping scheme which makes the output signal
directly compatible with DTL or TTL integrated
circuits. An LM 103 breakdown diode clamps the
output at OV or 4 V in the low or high states, respectively. Th is particular diode was chosen because it
has a sharp breakdown and low equivalent capacitance. When working as a comparator, the amplifier
operates open loop so normally no frequency compensation is needed. Nonetheless, the stray capacitance between Pins 5 and 6 of the amplifier should
be minimized to prevent low level oscillations when
the comparator is in the active region. If this becomes a problem, a 3 pF capacitor on the normal
compensation terminals will eliminate it.

An advantage of the LM101 in this circuit is that
it will work with input voltages up to its positive
supply voltages as long as the supplies are less than
±15V.
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a. Standard Differential Amplifier

b. Level-Isolation Amplifier

FIGURE 2. Level-Shifting Amplifiers

+28V

OUTPUT

a. Comparator for Driving DTL
and TTL Integrated Circuits

FIGURE 3. Voltage Comparator Curcuits

AN4-2

b. Comparator and Lamp Driver

OUTPUT

(

Figure 3b shows the connection of the LM 101 as a
comparator and lamp driver. 01 switches the lamp,
with R2 limiting the current surge resulting from
turning on a cold lamp. R 1 determines the base
drive to 01 while 01 keeps the amplifier from putting excessive reverse bias on the emitter-base junction of 01 when it turns off.

......_ _- - - - - - - 1 5 V

OUTPUT

MORE OUTPUT CURRENT SWING
Because almost all monolithic amplifiers use class-B
output stages, they have good loaded output voltage swings, delivering ±10V at 5 mA with ±15V
supplies. Demanding much more current from the
integrated circuit would require, for one, that the
output transistors be made considerably larger. In
addition, the increased dissipation could give rise
to troublesome thermal gradients on the chip as
well as excessive package heating in high-temperature applications. It is therefore advisable to use
an external buffer when large output currents are
needed.
A simple way of accomplishing this is shown in
Figure 4. A pair of complementary transistors are
used on the output of the LM 101 to get the increased current swing. Although this circuit does
have a dead zone, it can be neglected at frequencies below 100 Hz because of the high gain of the
amplifier. R 1 is included to eliminate parasitic oscillations from the output transistors. In addition, adequate bypassing should be used on the collectors
of the output transistors to insure that the output
signal is not coupled back into the amplifier. This
circuit does not have current limiting, but it can be
added by putting 50Q resistors in series with the
collectors of 01 and 02.

OUTPUT

FIGURE 4. High Current Output Buffer

AN FET AMPLIFIER
For ambient temperatures less than about 70°C,
junction field effect transistors can give exceptionally low input currents when they are used on the
input stage of an operational amplifier. However,
monolithic FET amplifiers are not now available
since it is no simple matter to diffuse high quality
FET's on the same chip as the amplifier. Nonetheless, it is possible to make a good FET amplifier
using a discrete FET pair in conjunction with a
monolithic circuit.
Such a circuit is illustrated in Figure 5. A matched
FET pair, connected as source followers, is put in
front of an integrated operational amplifier. The

-15V

FIGURE 5. FET Operational Amplifier

composite circuit has roughly the same gain as the
integrated circuit by itself and is compensated for
unity gain with a 30 pF capacitor as shown. Although it works well as a summing amplifier, the
circuit leaves something to be desired in applications requiring high common mode rejection. This
happens both because resistors are used for current
sources and because the FET's by themself do not
have good common mode rejection.

STORAGE CIRCUITS
A sample-and-hold circuit which combines the low
input current of FET's with the low offset voltage
of monolithic amplifiers is shown in Figure 6. The
circuit is a unity gain amplifier employing an operational amplifier and an FET source follower. In
operation, when the sample switch, 02, is turned
on, it closes the feedback loop to make the output
equal to the input, differing only by the offset voltage of the LM101. When the switch is opened, the
charge stored on C2 holds the output at a level
equal to the last value of the input voltage.
Some care must be taken in the selection of the
holding capacitor. Certain types, including paper and
mylar, exhibit a polarization phenomenon which
causes the sampled voltage to drop off by about
50 mV, and then stabilize, when the capacitor is
exercised over a 5V range during the sample interval. This drop off has a time constant in the order
of seconds. The effect, however, can be minimized
by using capacitors with teflon, polyethylene, glass
or polycarbonate dielectrics.
Although this circuit does not have a particularly
low output resistance, fixed loads do not upset the
accuracy since the loading is automatically compensated for during the sample interval. However,
if the load is expected to change after sampling, a
buffer such as the LM 102 must be added between
the F ET and the output.
A second pole is introduced into the loop response
of the amplifier by the switch resistance and the
holding capacitor, C2. This can cause problems with
overshoot or oscillation if it is not compensated for
by adding a resistor, R 1, in series with the LM 101
compensation capacitor such that the breakpoint
of the R 1C1 combination is roughly equal to that
of the switch and the holding capacitor.

AN4-3

OUTPUT-.....-

01
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C1
30pF

FIGURE 6. Low Drift Sample and Hold

It is possible to use an MaS transistor for 01
without worrying about the threshold stability.
The threshold voltage is balanced out during every
sample interval so only the short-term threshold
stability is important. When MaS transistors are
used along with mechanical switches, drift rates
less than 10 mY/min can be realized.

Additional features of the circuit are that the amplifier acts as a buffer so that the circuit does not
load the input signal. Further, gain can also be provided by feeding back to the inverting input of
the LM 101 through a resistive divider instead of
directly.

The peak detector in Figure 7 is similar in many
respects to the sample-and-hold circuit. A diode is
used in place of the sampling switch. Connected as
shown, it will conduct whenever the input is greater
than the output, so the output will be equal to the
peak value of the input voltage. In this case, an
LM 102 is used as a buffer for the storage capacitor,
giving low drift along with a low output resistance.

As with the sample and hold, the differential input
voltage range of the LM101 permits differences between the input and output voltages when the circuit is holding.

OUTPUT -

....--::.C

When a non-I inear transfer function is needed from
an operational amplifier, many methods of obtaining it present themself. However, they usually require diodes and are therefore difficult to temperature compensate for accurate breakpoints. One way
of getting around this is to make the output swing
so large that the diode threshold is negligible by
comparison, but this is not always practical.
A method of producing very sharp, temperaturestable breakpoints in the transfer function of an
operational amplifier is shown in Figure 8. For
small input signals, the gain is determined by R1
and R2. Both 02 and 03 are conducti ng to some
degree, but they do not affect the gain because
their current gain is high and they do not feed any
appreciable current back into the summing mode.
When the output voltage rises to 2V (determined
by R3, R4 and V-), 03 draws enough c.urrent to
saturate, connecting R4 in parallel with R2. This
cuts the gain in half. Similarly, when the output
voltage rises to 4V, 02 will saturate, again halving
the gain.
Temperature compensation is achieved in this circuit by including 01 and 04. 04 compensates the
emitter-base voltage of 02 and 03 to keep the
voltage across the feedback resistors, R4 and R6,
very nearly equal to the output voltage while Q1
compensates for the emitter base voltage of these
transistors as they go into saturation, making the
voltage across R3 and R5 equal to the negative supply voltage. A detrimental effect of 04 is that it
causes the output resistance of the amplifier to increase at high output levels. It may therefore be
necessary to use an output buffer if the circuit
must drive an appreciable load.

SERVO PREAMPLIFIER

01
F0300

C2

1""'

INPUT--~

C1
30pF

FIGURE 7. Positive Peak Detector with
Buffered Output

AN4-4

NON-LINEAR AMPLI FI ERS

In certain servo systems, it is desirable to get the
rate signal required for loop stability from some
sort of electrical, lead network. Th is can, for example, be accomplished with reactive elements in
the feedback network of the servo preamplifier.
Many saturating servo amplifiers operate over an
extremely wide dynamic range. For example, the
maximum error signal could easily be 1000 times
the signal required to saturate the system. Cases
like this create problems with electrical rate networks because they cannot be placed in any part

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FIGURE 8. Nonlinear Operational Amplifier with Temperature-Compensated Breakpoints

of the system which saturates. If the signal into the
rate network saturates, a rate signal will only be
developed over a narrow range of system operation;
and instability will result when the error becomes
large. Attempts to place the rate networks in front
of the error amplifier or make the error amplifier
linear over the entire range of error signals frequently gives rise to excessive dc error from signal
attenuation.
These problems can be largely overcome using the
kind of circuit shown in Figure 9. This amplifier
operates in the linear mode until the output voltage
reaches approximately 3V with 30 pA output current from the solar cell sensors. At th is point the
breakdown diodes in the feedback loop begin to
conduct, drastically reducing the gain. However, a
rate signal will still be developed because current is
being fed back into the rate network (R1, R2 and
C1) just as it would if the amplifier had remained
in the linear operating region. In fact, the amplifier
will not actually saturate until the error current
reaches 6 mA, which would be the same as having
a linear amplifier with a ±600V output swing.
01

LM103
2.4V
02

:>O--4r.-- OUTPUT

C2
30pF

FIGURE 9. Saturating Servo Preamplifier with
Rate Feedback
COMPUTING CIRCUITS
In analog computation it is a relatively simple
matter to perform such operations as addition,
subtraction, integration and differentiation by in-

corporating the proper resistors and capacitors in
the feedback circuit of an amplifier. Many of these
circuits are described in reference 5. Multiplication
and division, however, are a bit more difficult.
These operations are usually performed by taking
the logarithmsof the quantities, adding or subtracting as required and then taking the antilog.
.
At first glance, it might appear that obtaining the
log of a voltage is difficult; but it has been shown 6
that the emitter-base voltage of a silicon transistor
follows the log of its collector current over as many
as nine decades. This means that common transistors can be used to perform the log and antilog
operations.
A circuit which performs both multiplication and
division in this fashion is shown in Figure 10. It
gives an output which is proportional to the prodcut of two inputs divided by a third, and it is about
the same complexity as a divider alone.
The circuit consists of three log converters and an
antilog generator. Log converters similar to these
have been described elsewhere,7 but a brief description follows. Taking amplifier A1, a logging transistor, 01, is inserted in the feedback loop such
that its collector current is equal to the input voltage divided by the input resistor, R 1. Hence, the
emitter-base voltage of 01 will vary as the log of
the input Voltage, E 1.
A2 is a similar amplifier operating with logging
transistor, 02. The emitter-base junctions of 01
and 02 are connected in series, adding the log
voltages. The third log converter produces the log
of E3. This is series-connected with the antilog
transistor, 04; and the combination is hooked in
parallel with the output of the other two log convertors. Therefore, the emitter-base of Q4 will see
the log of E3 subtracted from the sum of the logs
of E 1 and E2. Since the collector current of a transistor varies as the exponent of the emitter-base
voltage, the collector current of 04 will be proportional to the product of E 1 and E2 divided by
E3. This current is fed to the summing amplifier,
A4, giving the desired output.

---------------------------------_._------AN4--5

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FIGURE 10. Analog Multiplier/Divider

This circuit can give 1-percent accuracy for input
voltages from 500 mVto 50V. To get this precision
at lower input voltages, the offset of the amplifiers
handling them must be individually balanced out.
The zener diode, 04, increases the collector-base
voltage across the logging transistors to improve
high current operation. It is not needed, and is in
fact undesirable, when these transistors are running
at currents less than 0.3 mA. At currents above
0.3 mA, the lead resistances of the transistors can
become important (0.25[2 is 1-percent at 1 mAl
so the transistors should be installed with short
leads and no sockets.

The logging transistors provide a gain which is dependent on their operating level, which complicates
frequency compensation. Resistors (R3, R6 and
R71 are put in the amplifier output to limit the
maximum loop gain, and the compensation capacitor is chosen to correspond with this gain. As a
result, the amplifiers are not especially designed for
speed, but techniques for optimizing this parameter
are given in reference 6.
Finally, clamp diodes 01 through 03, prevent exceeding the maximum reverse emitter-base voltage
of the logging transistors with negative inputs.

ROOT EXTRACTOR *

An important feature of this circuit is that its operation is independent of temperature because the
scale factor change in the log converter with temperature is compensated by an equal change in the
scale factor of the antilog generator. It is only required that 01, 02, 03 and 04 be at the same
temperature. Oual transistors should be used and
arranged as shown in the figure so that thermal mismatches between cans appear as inaccuracies in
scale factor (0.3-percenttCI rather than a balance
error (8-percenttCI. R 12 is a balance potentiometer which nulls out the offset voltages of all the
logging transistors. It is adjusted by setting all input
voltages equal to 2V and adjusting for a 2V output
voltage.

AN4-6

Taking the root of a number using log converters
is a fairly simple matter. All that is needed is to
take the log of a Voltage, divide it by, say 1/2 for
the square root, and then take the antilog. A circuit which accomplishes this is shown in Figure 11.
A 1 and 01 form the log converter for the input
signal. This feeds 02 which produces a level shift
to give zero voltage into the R4, R5 divider for a
1 V input. Th is divider reduces the log voltage by
the ratio for the root desired and drives the buffer
amplifier, A2. A2 has a second level shifting diode,
03, its feedback network which gives the output
voltage needed to get a 1 V output from the antilog
generator, consisting of A3 and Q4, with a unity
*The "extraction" used here doubtless has origin in the
dental operation most of us would fear less than having
to find even a square root without tables or other aids.

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FIGURE 11. Root Extractor

input. The offset voltages of the transistors are
nulled out by imbalancing R6 and R8 to give 1 V
output for 1 V input, since any root of one is one.
02 and 03 are connected as diodes in order to
simplify the circuitry. This doesn't introduce problems because both operate over a very limited current range, and it is really only required that they
match. R7 is a gain-compensating resistor which
keeps the currents in 02 and 03 equal with changes
in signal level.
As with the multiplier/divider, the circuit is insensitive to temperature as long as all the transistors
are at the same temperature. Using transistor pairs
and matching them as shown minimizes the effects
of gradients.
The circuit has 1-percent accuracy for input voltages between 0.5 and 50V. For lower input voltages, A 1 and A3 must have their offsets balanced
out individually.

FREQUENCY COMPENSATION HINTS
The ease of designing with operational amplifiers
sometimes obscures some of the rules which must
be followed with any feedback amplifier to keep
it from oscillating. In general, these problems stem
from stray capacitance, excessive capacitive load-

ing, inadequate supply bypassing or improper frequency compensation.
In frequency compensating an operational amplifier, it is best to follow the manufacturer's recommendations. However, if operating speed and
frequency response is not a consideration, a greater
stability margin can ususally be obtained by increasing the size of the compensation capacitors.
For example, replacing the 30 pF compensation
capacitor on the LM101 with a 300 pF capacitor
will make it ten times less susceptible to oscillation
problems in the unity-gain connection. Similarly,
on the LM709, using 0.05 pF, 1.5 kn, 2000 pF
and 51 n components instead of 5000 pF, 1.5 kn,
200 pF and 51 n will give 20 dB more stability
margin. Capacitor values less than those specified
by the manufacturer for a particular gain connection should not be used since they will make the
amplifier more sensitive to strays and capacitive
loading, or the circuit can even oscillate with worstcase units.
The basic requirement for frequency compensating
a feedback amplifier is to keep the frequency rolloff of the loop gain from exceeding 12 dB/octave
when it goes through unity gain. Figure 12a shows
what is meant by loop gain. The feedback loop is
broken at the output, and the input sources are
replaced by their equivalent impedance. Then the
response is measured such that the feedback network is included.

A2

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a. Measuring Loop Gain

b. Typical Response

FIGURE 12. Illustrating Loop Gain

AN4-7

Cl

Figure 12b gives typical responses for both uncompensated and compensated amplifiers. An uncompensated amplifier generally rolls off at 6 dB/octave,
then 12 dB/octave and even 18 dB/octave as various frequency-limiting effects within the amplifier
come into play. If a loop with this kind of response
were closed, it would oscillate. Frequency compensation causes the gain to roll off at a uniform 6 dB/
octave right down through unity gain. This allows
some margin for excess roll off in the external
circuitry.
Some of the external influences which can affect
the stability of an operational amplifier is shown in
Figure 13. One is the load capacitance which can
come from wiring, cables oran actual capacitor on
the output. This capacitance works against the output impedance of the amplifier to attenuate high
frequencies. If this added rolloff occurs before the
loop gain goes through zero, it can cause instability.
It should be remembered that this single rolloff
point can give more than 6 dB/octave rolloff since
the output impedance of the amplifier can be increasing with frequency.

R2

FIGURE 14. Compensating Stray Input
Capacitance
shown in Figure 15. The capacitive load is isolated
from the output of the amplifier with R4 which has
a value of 50n to lOOn for both the LM10l and
the LM709. At high frequencies, the feedback path
is through the lead capacitor, Cl, so that the lag
produced by the load capacitance does not cause
instability. To use this circuit, the ampl ifier must
be compensated for unity gain, regardless of the
closed loop dc gain. The value of C1 is not too
important, bu~ at a minimum its capacitivereactance should be one-tenth the resistance of R2 at
the unity-gain crossover frequency of the amplifier.
Cl

R3
R2
Rl
Rl
R4

R2

>--4~"""'''''-EOUT

FIGURE 13. External Capacitances That Affect
Stability

FIGURE 15. Compensating for Very Large
Capacitive Loads

A second source of excess rolloff is stray capaci- '
tance on the inverting input. This becomes extremely important with large feedback resistors as
might be used with an FET-input amplifier. A relatively simple method of compensating for this stray
capacitance is shown in Figure 14: a lead capacitor,
Cl, put across the feedback resistor. Ideally, the
ratio of the stray capacitance to the lead capacitor
should be equal to the closed-loop gain of the amplifier. However, the lead capacitor can be made
larger as long as the amplifier is compensated for
unity gain. The only disadvantage of doing this is
that it will reduce the bandwidth of the amplifier.
Oscillations can also result if there is a large resistance on the non-inverting input of the amplifier.
The differential input impedance of the amplifier
falls off at high frequencies (especially with bipolar input transistors) so this resistor can produce
troublesome rolloff if.it is much greater than 10K,
with most amplifiers. This is easily corrected by bypassing the resistor to ground.

When an operational amplifier is operated open
loop, it might appear at first glance that it needs
no frequency compensation. However, this is not
always the case because the external compensation
is sometimes required to stabilize internal. feedback
loops.

When the capacitive load on an integrated amplifier
is much greater than 100 pF, some consideration
must be given to its effect on stability. Even though
the amplifier does not oscillate readily, there may
be a worst-case set of conditions under wh ich it
will. However, the amplifier can be stabilized for
any value of capacitive loading using the circuit

Problems encountered with -supply bypassing are
insidious in that they will hardly ever show up in a
Nyquist plot. This problem has not really been
thoroughly investigated, probably because one sure
cure is known: bypass the positive and negative
supply terminals of each amplifier to ground with
at least aO.Ol pF capacitor.

AN4-8

The LM10l will not oscillate when operate(j open
loop, although there may be problems if the capaCitance between the balance terminal on pin 5 and
the output is not held to an absolute minimum.
Feedback between these two points.is regenerative
if it is not balanced au.t with a targer feedback
capacitance across the compensation terminals~
Usually a 3 pF compensation capacitor will completely eliminate the problem. The LM709 will oscillate when operated open loop unless a 10 pF
capacitor is connected across the input compensationterminalsand a 3pF capacitor is connected on
the output compensation terminals.

For example, a LM101 can take over 1 mH inductance in either supply lead without,oscillation. This
should not suggest that they should be run without
bypass capacitors. It has been establ ished that 100
LM 101's on a single printed circuit board with common supply busses will oscillate if the supplies are
not bypassed about every fifth device. This happens
even though the inputs and outputs are completely
isolated.

it is not too helpful in determining if the amplifier
is indeed stable. The. reason is that most problems
in a well-designed system are caused by secondary
effects - which occur only under certain conditions
of output voltage, load current, capacitive loading,
temperature, etc. Making frequency-phase plots
under all these conditions would require unreasonable amounts of time, so it is invariably not done.

The LM709, on the other hand, will oscillate under
many load conditions with as little as 18 inches of
wire between the negative supply lead and a bypass
capacitor. Therefore, it is almost essential to have a
set of bypass capacitors for every device.

A better check on stability is the small-signal transient response. It can be shown mathematically that
the transient response of a network has a one-forone correspondence with the frequency domain
response. t The advantage of transient response tests
is that they are displayed instantaneously on an
oscilloscope, so it is reasonable to test a circuit
under a wide range of conditions.

Operational amplifiers are specified for power supply rejection at frequencies less than the first break
frequency of the open loop gain. At higher frequencies, the rejection can be reduced depending
on how the amplifier is frequency compensated.
For both the LM10l and LM709, the rejection of
high frequency signals on the positive supply is
excellent. However, the situation is different for
the negative supplies. These two amplifiers have
compensation capacitors from the output down to
a signal point which is referred to the negative supply, causing the high frequency rejection for the
negative supply to be much reduced. It is therefore
important to have sufficient bypassing on the negative supply to remove transients if they can cause
trouble appearing on the output. One fairly large
(22 J1F) tantalum capacitor on the negative power
lead for each printed-circuit card is usually enough
to solve potential problems.

When high-current buffers are used in conjunction
with operational amplifiers, supply bypassing and
decoupling are even more important since they can
feed a considerable amount of signal back into the
supply lines. For reference, bypass capacitors of at
least 0.1 J1F are required for a 50 mA buffer.

Exact methods of analysis using transient response
will not be presented here. This is not because these
methods are difficult, although they are. Instead, it
is because it is very easy to determine which conditions are unfavorable from the overshoot and ringing on the step response. The stability margin can
be determined much more easily by how much
greater the aggravating conditions can be made
before the circuit oscillates than by analysis of the
response under given conditions. A little' practice
with this technique can quickly yield much better
results than classical methods even for the inexperienced engineer.

SUMMARY
A number of circuits using operational amplifiers
have been proposed to show their versatility in circuit design. These have ranged from low frequency
oscillators through circuits for complex analog
computation. Because of the low cost of monolithic
amplifiers, it is almost foolish to design dc ampli. fiers without integrated circuits. Moreover, the price
makes it practical to take advantage of operationalamplifier performance in a variety of circuits where
they are not normally used.

When emitter followers are used to drive long cables, additional precautions are required. An emitter
follower by itself - which 'is not contained in a
feedback loop - will frequently oscillate when connected to a long length of cable. When an emitter
follower is connected to the output of an operational amplifier, it can produce oscillations that
will persist no matter how the loop gain is compensated. An analysis of why this happens is not very
enlightening, so suffice it to say that these oscillations can usually be eliminated by putting a ferrite
bead 8 between the emitter follower and the cable.

Many of the potential oscillation problems that
. can be encountered in both discrete and integrated
operational amplifiers were described, and some
conservative solutions to these problems were presented. The areas discussed included stray capacitance, capacitive loading and supply bypassing.
Finally, a simplified method of quickly testing the
stability of amplifier circuits over a wide range of
operating conditions was suggested.

Considering the loop gain of an amplifier is a valuable tool in understanding the influence of various
factors on the stability of feedback amplifiers. But

tThe frequency-domain characteristics can be determined
from the impulse response of a network and this is directly relatable to the step response through the convolution integral.

AN4-9

REFERENCES
1. R. J. Widlar, "Monolithic Op Amp with Simplified Frequency Compensation," EEE, Vol. 15,
No.7, pp. 58-63, July, 1967.

5. "Handbook of Operational Amplifier Applications," Burr-Brown Research Corporation,
Tucson, Arizona.

2. R. J. Widlar, "A Unique Circuit Design for a
High Performance Operational Amplifier Especially Suited to Monolithic Construction," Proc.
of NEC, Vol. XXI, pp. 85-89, October, 1965.

6. J. F. Gibbons and H. S. Horn, "A Circuit with
Logarithmic Transfer Response over Nine Decades," IEEE Trans. on Circuit Theory, Vol.
CT-11, pp. 378-384, September, 1964.

3. R. J. Widlar, "A Fast Integrated Voltage Follower with Low Input Current," National Semiconductor AN-5, March, 1968.

7. R. J. Widlar and J. N. Giles, "Avoid OverIntegration," Electronic Design, Vol. 14, No.3,
pp. 56-62, Feb. 1, 1966.

4. R. J. Widlar, "The Operation and Use of a Fast
Integrated Circuit Comparator," Fairchild Semiconductor APP-116, February, 1966.

8. Leslie Solomon, "Ferrite Beads," Electronics
World, pp. 42-43, October, 1966.

AN4-10

»z
May 1968

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A FAST INTEGRATED VOLTAGE
FOLLOWER WITH LOW INPUT
CURRENT

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INTRODUCTION
Most integrated operational amplifiers on the market today have serious limitations in many voltage
follower applications. They are often too slow
because a voltage follower requires maximum
frequency compensation, reducing slew rate to
somewhere between 0.1 V //1s and 1 V //1s.1,2
Secondly, voltage followers are most frequently
used as buffer amplifiers from high impedance
sources; but the input current of popular amplifiers gives excessive dc offset when operated with
sou rce resistances much above 10 Kn.
The design of a monolithic voltage follower which
combines low offset voltage with an input current
of 2 nA and a 10 V //1s slew rate is described here.
This performance is realized using improved bipolar transistors along with an operational amplifier circuit design which is optimized for the
voltage follower configuration. The device, which
is designed to operate from supply voltages between ±12V and ±15V,features a 10MHz bandwidth along with a 3 pF input capacitance and a
minimum input resistance of 10,000 Mn. In addition, it requires no external components for frequency compensation and incorporates continuous
short circuit protection.

follower output. Since current sources are used on
the emitter of the differential pair and as a collector load, it is practical to get an open loop
voltage gain of 3000 from a single stage. The
collector of the input transistor, 01, is bootstrapped to the output to increase gain and raise
the input resistance. It also eliminates leakage
currents by operating the input at zero collectorbase voltage. A class-A output stage is used since it
behaves better at high frequencies with capacitive
loads. Although frequency compensation is not
always required with this configuration, R 1 and
Cl have been included to improve stability with
capacitive loading. The compensation network is
placed such that the circuit has good transient rejection on both the positive and the negative
supplies.

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CIRCUIT DESCRIPTION
There are fewer problems encountered in designing
a high performance voltage follower than a similar
general purpose amplifier. For one, no level shifting is required so complementary transistors are
unnecessary as gain stages. Hence, it is possible to
get better high frequency performance since this
has been limited in the past by the performance of
the PNp3 transistors that can be made in monolithic circuits. Secondly, because lOa-percent feedback is used, the open loop gain does not have to
be as high as a general purpose amplifier; so a
simpler circuit, which is easier to frequency compensate, can be used. Finally, with a fixed configuration such as a voltage follower, the input stage
can be included within the compensation network.
This makes it easier to get fast slewing without
having to provide unreasonably large small-signal
bandwidths which would make the amplifier more
prone to instabilities.
Figure 1 demonstrates how s~llple a voltage
follower circuit can be. This circuit uses a singlestage differential amplifier with an emitter-

INPUT

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FIGURE 1. Basic Configuration of the Voltage
Follower

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INPUT STAGE
In order to get fast slewing, it is necessary to
operate the differential amplifier at a fairly high
current for an input stage. Therefore, a Darlington
connection is used on the input transistors to get
low input current. However, as can be seen from
Figure 2, bleed resistors, R 1 and R2, operate the
input transistors at a current which is large by
comparison to the base current of 03 and 04. This
keeps 01 and 02 from seeing mismatches in the
base currents of 03 and 04, wh ich is the largest
source of offset voltage in an ordinary Darlington
differential stage. This bleed current also doubles
the gain of the stage and improves the high frequency performance.
AN5-1

Using a Darlington stage is not the entire secret to
getting low input currents. 4 With the· integrated
circuit transistors that have been available in the
past, reducing the collector current by a factor
of 10 would only reduce the base current by a
factor of 3, since the current gain falls off rapidly
at low collector currents. In order to get any real
improvement from operating at low currents, it
was necessary to make better transistors. The
devices used here have a tYpical current gain of
1000 at 2 p.A collector current.

circuitry which is represented by current sources
in Figures 1 and 2. In order t.o realize low offset
voltage, the current source on the collector of 02
must supply a current which is exactly one-half of
the input pair emitter current.
To do th is, diode-connected transistors, 014 and
015, provi de a bi as vol tage wh ich is regu Iated
against supply voltage variations for the current
source transistors, 010, 012 and 013. 012 is the
current source for the input pair, while 013 gen-

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FIGURE 2. Partial Schematic of the
LM102 Voltage Follower
Operating at 2 p.A currents requires large resistance
values which are not easily fabricated in integrated
circuits. Therefore, the bleed circuit on the input
stage had to be designed to minimize this resistance. Rl and R2 are operated with a 160 mV
drop across them, which is determined by the drop
across R3 plus the emitter-base voltage difference
between 05 and the differential transistors, 03
and 04. This difference is 100 mV since the differential transistors are operated at rough Iy 35 times
the current through 05. 5

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FIGURE 3. Simplified Schematic of
Biasing Circuitry
erates a current which is one-half the output current of 012. This is accomplished by making R9
twice as large as R8 and 013 one-half the size of
012. The output current of 013 is fed to 018,
which biases 019. If it is assumed that 018 and
019 are well matched and have large current gains,
the output current of 019 will be equal to the
collector current of 013 - or one-half the emitter
current of the input pair, as required.
ADDITIONAL DETAI LS

Pinch resistors had to be used for R 1 and R2 to
get 80 Kn within a reasonable surface area. They
were also necessary to keep the parasitic capacitance of the resistors small, as it could severely
degrade the large signal pulse response. However,
pinch resistors have a large positive temperature
coefficient which causes the operating current of
01 and 02 to increase to 3.5 p.A at -55°C and
decrease to 1.4 p.A at 125°C.
Figure 2 shows that an extra transistor, 08, has
been added on the collectors of 02 and 04. This
forms a cascode stage wh ich operates 02 at near
zero collector base voltage, as is 01. An additional
emitter follower is included on the output to
further reduce output resistance.
BIASING CIRCUITRY
Figure 3 is a simplified schematic of the biasing
AN5-2

In practice, it cannot be assumed that the current
gain of the PNP transistors, 018 and 019, is
large. 6 In fact, the current gain could be as low as
unity. As a result, additional circuitry is required
to get proper operation. Figure 4 shows how this is
done.
Instead of connecting the base directly back to the
collector, emitter follower buffers, 016 and 017,
are used to isolate the base current from the collector of 018. Level shifting diodes, Dl and D2,
are included so that 018 is operated at approximately the same collector base voltage as 019,
when the output of the amplifier is at zero, further
improving the match.
The RC network, R 11 and C2, is included to suppress oscillations in this feedback loop. The voltage drop across C2 is less than a couple of volts so

a junction capacitor can be fabricated from the
emitter and base diffusions of the NPN transistors.
With this, the required capacitance can be obtained in a reasonable area of the chip with no
additional process steps, as would be required if an
MOS capacitor were used. The same is true, incidentally, for C1.
A class-A output stage is used primarily for simplicity, although the higher quiescent current in
the output stage improves stability with capacitive
loads. The emitter of the current sink, 010, is
brought out so that an external resistor can be
connected between it and the negative supply for
increased output current in applications where the
BALANCE

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creasing gain. Taps on these resistors are brought
out to provide for offset balancing. The tap point
is selected to give a smooth ±20 m V adjustment
range when a 1 K potentiometer, is connected between the balance term,inals and' the. positive
supply.
The output is inherently short-circuit proof in the
negative direction. Current limiting for positive
outputs is provided by 09 and R6. However, when
operating from low source resistances, a 2 Kn to
10 Kn resistor must be added in series with the
input, since the input is clamped directly to the
output through 03 and 011 which protect the
input transistors from overvoltage. This resistor
was not included on the chip because it is difficult
to locate a diffused resistor in an isolation region
where it would be effective yet not contribute to
input leakage 'current at high temperatures.
A photomicrograph of the LM 102 is shown in Figure 5. Although the schematic diagram of the
circuit appears complicated, it fits neatly on a
49 x 49 mil-square die.
PERFORMANCE

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The electrical characteristics of the LM 102 are
summarized in Table I. It is evident from this that
the primary design objectives, high speed and low
input current, have indeed been achieved.
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FIGURE 4. Complete Schematic Diagram

Offset Voltage
I nput Current
Input Resistance
Voltage Gain
Output Resistance
Output Voltage Swing
Slew Rate
Bandwidth
I nput Capacitance
'Supply Current

2.5 mV
3 nA
1012n
0.9995
1.0n
±13V
10 V /fJ.s
, 10 MHz
3 pF
3.5mA

TABLE I. Typical Electrical Characteristics of the
LM102

FIGURE 5. Photomicrograph of the LM102
higher dissipation can be tolerated. The current
source is biased from the collector of a low gain
lateral PNP transistor, 014, so that the bias voltage
for. the input stage current sources will not be
greatly affected wh en 010 satu rates on negative
signals.
Resistors are included in series with the, emitters of
the PNP current source transistors, 018 and 019,
to reduce their output conductance, thereby in-

The low input bias current of the voltage follower
is illustrated in Figure 6. It can be seen that the
input curr,ent reaches, a minimum at 85°C but
remains low up to 125°C. This suggests operating
the UVll02 in a temperature stabilized component
oven for wide ,temperature range applications. If
this is done; the LM102 will give input currents
wh ich are considerably better than can be real ized
with FET amplifiers over a -55°C to 125°C temperature range. In addition, the temperature stabilization will .gr~atly reduce the offset voltage drift.
Figure 7 is a plot of the frequency response of the
LM102. The low frequency gain figure corresponds to an open loop gain of about 2000.
Although this sounds low for an operational amplifier, it should be remembered that a voltage
follower has 100-percent feedback so the gain
error is only 0.05-percent. Further, because of its

AN5-3

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TEMPERATURE

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AN5-4

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while a 100n resistor will enable the amplifier to
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shows the effect of temperature on the drive capability .

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FIGURE 14. Supply Current
better high frequency response, the LM102
actually has 10 times more gain than either the
LM 101 or the LM709 at frequencies greater than
10 kHz. The gain of all these amplifiers is equal at
500 Hz.

It should be remembered that increasing the drive
current will increase dissipation in the microcircuit. For example, when the amplifier is set up
to drive ±10V into a 2K load at 125°C, the worst
case dissipation increase wi" be 150 mW (for a
steady +10V output with load).
Figures 12 and 13 show the current limiting characteristics of the LM102. Figure 12, which gives
the positive output level as a function of load current demonstrates the sharpness of the current
limiting. The short circuit current also drops as the
chip heats up, reducing power dissipation.

It is difficult to measure the low frequency gain of
a voltage follower directly because the gain error is
so small. However, it can be accomplished by
grounding the input of the amplifier and driving
both power supplies simultaneously with the
desired input signal. The amplifier error can then
be observed directly on the output.

Figure 13 gives the limiting characteristics in the
negative direction. The circuit begins to limit at
lower currents since the available current is determined by a fixed-current source. It should be
noted that after the output swing first starts to fall
off, further increases in load current are supplied
by the input through the protective clamp diodes,
D3 and Q11.

Figure 8 gives the response of the amplifier at frequencies up to 10MHz. With a 10K source resistance, the bandwidth is nearly 10 MHz. Some
peaking is evident, although it is not serious. At
higher source resistances, the bandwidth is reduced
by the 3 pF input capacitance as shown in the
figure.

Figure 14 is a plot of the current drain over a
-55°C to 125°C temperature range. The supply
current does not increase appreciably over the
entire output voltage range, including saturation.
It is evident here that fast operation is obtained in
the follower without excessive power dissipation.

Feedback amplifiers generally have a full-signal
bandwidth which is considerably less than the
small signal bandwidth. The LM102 is no exception. It can only deliver its rated output swing at
frequencies less than 60 kHz, as shown in Figure 9.
There is no standard way of measuring the frequency limited output swing'? but the criterion
used here was that the total harmonic distortion
be less than 5-percent.
The output resistance of the follower is about 1n
as shown in Figure 10. This gives a gain error less
than 0.01-percent with load resistances above 10K.
At high frequencies as well as high temperatures,
the output resistance increases because the open
loop gain of the amplifier falls off.
INCREASED OUTPUT SWING
Figure 11 illustrates the function of the booster
terminal on the output stage current sink. By
itself, the amplifier can only deliver its rated ±10V
output swing into load resistances greater than
5.7 Kn at 25°C. With heavier loads, it will clip in
the negative direction. A 300n resistor between
pins 5 and 4 extends the drive capability to 2.5K

SLEWING
The fast slewing of the follower is demonstrated in
Figure 15. A fairly large overshoot is evident for
positive-going input signals above about 4V. As
shown in the figure, this can be eliminated by
using a high speed clamp diode between the input
and the output (with the anode on the input).
Although there is an internal clamp diode in this
position (D3 in Figure 4), it is of necessity a collector base diode which stores excess charge when
it turns on with input signals which rise faster than
the output can fo"ow. Th is stored charge causes
the oversh oot.
If the LM 102 is driven from source resistances
higher than 30K, the leading edge of the input
pulse wi" always be slowed down enough by the
input capacitance that the output can follow the
input and the clamp diode is not needed. This is
shown in Figure 15a.
Figure 15b demonstrates that the slew rate is about
10 V IllS in the slowest direction even including the
effects of overshoot. But because of its restricted
output current swing in the negative direction, the
device will not give this slew rate with capacitive
loads greater than 100 pF unless the output sink
AN5-5

b. 30K Source Resistance

a. 3K Source Resistance
FIGURE 15.

Large Signal Pulse Response With and Without a Clamp Diode

b. 30K Source Resistance

a. 3K Source Resistance

FIGURE 16. Error Signal for 8V Input Pulse - With and Without a Clamp Diode

current is increased with an external resistor on
the booster terminal.
Figure 16 illustrates the fact that the settling time
of the LM102 to within 5 mV of its final value is
less than 1.5 ps for an 8V input pUlse. These
photographs show the error signal, which is the
difference between the input and the output, with
a ±4 V rectangular pulse appl ied.
STABILITY

Figures 17 through 19 are indicative of the stability of the amplifier under varying conditions of
capacitive loading, temperature and supply bypassing. 8 Figure 17 gives the small signal transient
response with capacitive loading. These pictures
were taken with both supplies bypassed to ground
with 0.01 pF ceramic capacitors. With loads
approaching 200 pF, the circuit tends toward
instability. With capacitive loads much above this
it will oscillate, although it will be stable again
with more than 0.01 pF on the output. With the
larger capacitances, however, both the small signal
risetime and the slew rate will be reduced.
Figure 18 shows how the stability is affected over

AN5-6

a -55°C to +125°C temperature range. Again, the
conditions here are 200 pF capacitive load with
bypassed supplies.
The effect of unbypassed supplies is demonstrated
in Figure 19. The response was measured under
the same conditions as Figure 17, except that
there is 16" of wire between the device and the
bypass capacitors on the power supply. It is
evident that the circuit is on the verge of becoming
unstable with capacitive loading. This clearly
proves the advisability of properly bypassing the
supplies on any high frequency amplifier.

OPERATING HINTS

A number of precautions concerning the proper
use of the LM 102 have already been given along
with hints on optimizing the performance in pertain applications. These are worth repeating here.
•

The output is short circuit protected; however, the input is clamped to the output to
prevent excessive voltage from being developed across the input transistors. If the
ampl ifier is driven from low source imped-

ances, excessive current can flow through
these clamp diodes when the output is
shorted. This can be prevented by inserting a
resistor larger than 3 Kn in series with the
input.
•

The circuit cannot deliver its full slew rate
into capacitive loads greater than 100 pF
unless more sink current is provided on the
output with a resistor between pins 4 and 5.

•

The amplifier may oscillate when operated
with capacitive loads between 200 pF and
0.01 IlF.

•

As is the case with any high frequency
amplifier, the power supply leads of the
LM 102 should be bypassed with capacitors
greater than 0.01 IlF located as close as
possible to the device. This is particularly
true if it is driving capacitive loads.

Figure 20a gives the connection for getting full
output swing into loads less than BK. The external
resistor, Rl, should not be made less than lOOn as
this could cause limiting on positive peaks. Figure 20b shows how to connect a potentiometer to
balance out the offset voltage. Figure 20c gives the
placement of a clamp diode which can be used to
reduce the overshoot that occurs when the follower is driven with large input pulses with a
leading-edge slope greater than 10 V!lls. The diode
is only neede~, however, when the source resistance is less than 30K since the slope seen by the
amplifier will be reduced by the input capacitance
with the higher source resistances.
FIGURE 17. Small Signal Transient Response for
C L = 10 pF (Top) and C L = 200 pF
(Bottom)

APPLICATIONS*
The use of the LM102 in a switch circuit for
driving the ladder network in an analog to digital
converter is shown in Figure 21. Simple transistor
switches, connected in the reverse mode for low
saturation voltage, generate the OV and 5V levels
for the ladder network. The switch output is
buffered by A2 and A3 to give a low driving
impedance in both the high and low states.

FIGURE 18.

Transient Response for C L = 200 pF
at 125°C (Top) and _55°C (Bottom)

The switch transistors can be driven directly from
integrated logic circuits. Resistors R7 and RB limit
the base drive; the values indicated are for operation with standard TTL or DTL circuits. If necessary, the switching speed can be increased somewhat by bypassing the resistors with 100 pF
capacitors.
Even with operation at maximum speed, clamp
diodes are not needed on the voltage followers to
reduce overshoot. The pullup resistors on the
switches, R5 and R6, can be made large enough so
that the LM 102 does not see a positive-going input
pulse that is much faster than the output slew rate.
The main advantage of this circuit is that it gives
much lower output resistance than push-pull
switches. Furthermore, the drive circuitry for
these switches is considerably simpler.
The LM 102 can also be used as a buffer for the
temperature compensated voltage reference, as
shown in Figure 21. The output of the reference
diode is divided down with a resistive divider, and
it can be set to the desired value with R3.

FIGURE 19. Transient Response With Unbypassed
Supplies, C L = 10 pF (Top) and
C L = 200 pF (Bottom)

*Other applications are given in reference 8.

AN 5"'-7

v'

Rl
lK

01

F06666

a. For Increased Swing

b. For Offset Balancing

c. For Eliminating Overshoot

FIGURE 20. Auxiliary Circuits for the LM102

.15V

Rl
3.6K

01
lN4611

6.6V

. . ._ _ _ _ _ _ _ _ _ _...._ _ _ _ _ _. .

RS
5K

DIGITAL

SWITCH

~~I~~~~~NING

R7
5K

-'VV\,,-.-....

DRIVE

FIGURE 21. Using the LM102 to Drive the Ladder
Network in an AID Converter

ANALOG COMMUTATOR
The low input current and fast slewing of the
LM 102 make it well suited as a buffer amplifier in
high speed analog commutators. The low input
current permits operation with switch resistances
even higher than 10. Kn without affecting the dc
stability.
. Figure 22 shows an expandable four-channel
analog commutator. Two DM7501 dual flip flops
form a four-bit static shift register. The parallel
outputs drive DM7800 level translators which convert the TTL logic levels to voltages suitable for
driving MOS devices, and this is coupled into an
MM451 four-channel analog switch. An extra gate
on· the input of the translator can be used, as
shown, to shut off all the analog switches.
I n operation, a bit enters the register and cycles

AN5-8

through at the clock frequency, turning on each
analog switch in sequence. The "clear" input is
used to reset the register such that all analog
switches are off. The channel capacity can be
expanded by connecting registers in series and
hooking the output of additional analog switches
to the input of the buffer amplifiers.
When the output of a large number of MOS
switches are connected together, the capacitance
on the output node can become high enough to
reduce accuracy at a given operating speed. This
problem can be avoided, however, by breaking up
the total number of channels, buffering these segments with voltage followers and then subcommutate them into the AID converter.
SAMPLE AND HOLD
Although there are many ways to make a sample
and hold device, the circuit shown in Figure 23 is

TO AID
CONVERTER
+5V -15V

+15V

><~-~-tl~~"::'-_

INPUT4

;>o-t--t.... ~+--+..:......-

INPUT 3

~--+-- INPUT2

i151 rH
I

1

L-

10

7

4

':'

5

"'--1-MM451
SUBSTRATE

INPUT 1

I

I

L __ -.J

+5V -15V +15V

DISABLE

CLEAR

V
J\JLJ\..

u

CLOCK

FIGURE 22. Analog Commutator With Buffered
Output

undoubtedly one of the simplest. When a negative
going sample pulse is applied to the MaS switch, it
will turn on hard and charge the holding capacitor
to the instantaneous value of the input voltage.
After the switch is turned off, the capacitor is
isolated from any loading by the LM 102; and it
will hold the voltage impressed upon it.

Figure 24 illustrates a method of bootstrapping
the bias resistor to get higher input resistance.
Even though a 200 KQ bias resistor is used for
good dc stability, the input resistance is about
12 MQ at 100 Hz, increasing to 100 MQ at 1 kHz.

ACTIVE FI LTERS
The maximum input current of the LM102 is
10 nA, so with a 10 /J.F holding capacitor the drift
rate in hold will be less than 1 mV /sec. If accuracies of about 1-percent or better are requ ired, it
is necessary to use a capacitor with polycarbonate,
polyethylene or teflon dielectric. Most other
capacitors exhibit a polarization phenomenon 9
which causes the stored voltage to fall off after the
sample interval with a time constant of several
seconds. For example, if the capacitor is charged
from a to 5V during the sample interval, the magnitude of the falloff is about 50 to 100 mV.

AC AMPLIFIER

The LM 102 has a minimum input resistance of
10,000 MQ, so for dc ampl ifier appl ications th is
can be completely neglected. However, with an ac
coupled amplifier a biasing resi~tor must be used
to supply the input current. This drastically reduces the input resistance.

Active RC filters have been replacing passive LC
filters at an ever-increasing rate because of the
decl ining price and smaller size of active components. Figure 25 is a low-pass filter which is one of
the simplest forms of active filters. The circuit has
the filter. characteristics of two isolated Refilter
sections and also has a buffered, low-impedance
output.

The attenuation is roughly 12 dB at twice the
cutoff frequency and the ultimate attenuation is
40 dB/decade. A third low-pass RC section can be
added on the output of the amplifier for an ultimate attenuation of 60 dB/decade, 1a although
this means that the output is no longer buffered.

There are two basic designs for this type of filter.
One is the Butterworth filter with maximally flat
frequency response. For this characteristic, the
component values are determined from 11
.

AN5-9

C1
0,01 ~F

>-6....-+-OUTPUT
INPUT

INPUT--i

~;"""-+-OUTPUT

~-+-""I

'Polycarbonate·dielectric capacitor,

FIGURE 23. Sample and Hold Circuit

FIGURE 24. High Input Impedance ac Amplifier

CI'

Rl
110K

940 pF

>"--...... OUTPUT

R1

C1'
0,02 ~F

24K

I

C2'
470
PF

INPUT--1I--e-....

'Values are for 10KHz cutoff, Use
silvered mica capacitors for good
temperature stability,

FIGURE 25. Low Pass Active Filter

Cl =

.>"-o-~OUTPUT

n .-............

INPUT-~"""'''''~~_'''''''''''''

Rl + R2
V2 Rl R2we

and

C2 = (Rl + R2) we .

The second kind is the linear phase filter with
minimum settling time for a pulse input. The
design equations for this are

'Values are for 100 Hz cutoff, Use
metalized polycarbonate capacitors
for good temperature stability,

FIGURE 26. High Pass Active Filter

CONCLUSIONS
The LM 102 represents a significant advance in the
state of the art of linear circuits manufacturing.
The device incorporates transistors which have
higher current gain than is available with discrete
components. Further, a factor of three to five
improvement over this can be expected in the near
future.
The performance realized challenges that of field
effect transistors, if operation over the mil itary
temperature range is considered. This is especially
true if the components are included in a
temperature-stabilized oven.

and

Although the circu it introduced here is restricted
to voltage follower applications, many of the techniques used here can be applied to general purpose
ampl ifiers. Th is is indicative of the performance
that can ultimately be realized with monolithic
ampl ifiers.

Substituting capacitors for resistors and resistors
for capacitors in the circuit of Figure 25, a similar
high-pass filter is obtained. This is shown in F igure 26.

Even though it's only a voltage follower, the
LM 102 can be used in a wide variety of applications ranging from low drift sample and hold circuits to a buffer amplifier for high-speed analog
commutators. Its usefulness is enhanced by the
fact that it is a plug-in replacement for both the
LM10l and the LM709 in voltage follower applications. The circuit will work in the same socket,
unaffected if the compensation components for
the other amplifiers are installed or not.

Cl =

Rl + R2
..j3 Rl R2we

C2= (Rl + R2)we

AN5-10

REFERENCES
1. R. J. Widlar, "A Unique Circuit Design for a
High Performance Operational Amplifier
Especially Suited to Monolithic Construction," Proc. of N EC, Vol. XXI, pp.85-89,
October, 1965.
2. R. J. Widlar, "Monolithic Op Amp with Simplified Frequency Compensation," EEE,
Vol. 15, No.7, pp. 58-63, July, 1967.
3. J. Lindmayer and W. Schneider, "Theory of
Lateral Transistors," Solid State Electronics,
Vol.l0,pp. 225-234,1967.
4. R. J. Widlar, "Future Trends in DC Amplifiers," National Sem iconductor Corporation
TP-4.

8. R. J. Widlar, "Monolithic Operational Amplifiers - The Universal Linear Component,"
National Semiconductor Corporation AN-4.
9. Paul C. Dow, Jr., "AnAnalysis of Certain
Errors in Electronic Differential Analyzers,
II - Capacitor Dielectric Absorption," IRE
Trans. on Electronic Computers, pp. 17-22,
March, .1958.
10. L. Scott, "Criteria for the Design of Active
Filters Using Resistance and Capacitance Elements in Feedback Circuits," Solid State Electronics, Vol. 9, pp. 641-651, 1966.
11. R. S. Melsheimer, "If You. Need Active Filters," Electronic Design, pp. 78-82, April 12,
1967.

5.R. J. Widlar, "Some Circuit Design Techniques for Linear Integrated Circuits," IEEE
Trans. on Circuit Theory, Vol. CT-12, No.4,
pp. 586-590, December, 1965.
6. H. C.Lin, T. B. Tan, G. Y. Chang, B. Van Der
Leest, and N. Formigoni, "Lateral Complementary Transistor Structu re for the Simu Itaneous Fabrication of Functional Blocks,"
Proc. of the IEEE, pp. 1491-1495, December,
1964.
7. R. Stata, "User's Guide to Applying and Measuring Operational Amplifier Specifications,"
Analog Dialogue, Vol. 1, No.3, pp.1-8,
September, 1967.

ACKNOWLEDGMENTS
The author would like to recognize the contributions of Dave Talbert in developing and establishing the manufactu·ring processes for this integrated
circuit. In addition, the invaluable contributions of
Mineo Yamatake in the design, development and
evaluation of the device must be gratefully
acknowledged.

AN5-11

»
z
March 1968

I

0)

-t
C
Z
m

C
(")

TUNED CIRCUIT DESIGN USING
MONOLITHIC RF/IF AMPLIFIERS

:lJ
(")

c

=t

INTRODUCTION
VAGC = 0
FOR GAIN TEST

In replacing conventional tuned high frequency
stages, monolithic RF/IF amplifiers can provide
performance, as well as economic advantages. Large
available gain per stage, inherent stability, self-contained biasing, and excellent limiting or AGC capabilities allow such amplifiers to improve conventional designs, while their very small chip size makes
them competitive with single transistor stages.

c

Vcc=+12V

m

-

CJ)

G)

Z
r---

C

son
OUT

CJ)

Z

C)
Vee = l1V

3:

1

o
2
or=t

I

10
L1

1

Q3

r----

-,

I
I

I
I
1

OUT

son

I

:I:

I

I

(")

.J

1-=

:lJ

sOH

."

IN

"-

1

I

Q3

."

I
I

»
3:

FIGURE 2. Cascode RF Amplifier

1

1

I
.J

FIGURE 1. Emitter Coupled RF Amplifier

is permanently connected as an emitter coupled
amplifier, in an economical six pin package, or as
the more versatile type LM171 (Figure 4), in which
a ten pin package allows the user to select either
emitter coupled or cascode configurations. Since
the 171, when externally connected as an emitter
coupled amplifier, is essentially identical in performance to the 703, references will be made only to
"cascode" or "emitter coupled" configurations.

Two especially useful RF/IF amplifiers are the
"emitter coupled" differential amplifier, Figure 1,
and the modified "cascode", Figure 2. Emitter
coupled operation is advantageous because of its
symmetrical, non-saturated limiting action, and corresponding fast recovery from large signal overdrive,
making a nearly ideal FM IF stage. The "cascode"
combines the large available stable gain and low
noise figure, for which the configuration is well
known, with a highly effective remote gain control capability, via a second common-base stage,
which overcomes many of the interstage detuning
and bandwidth variation problems found in conventional transistor AGC stages.

DC Biasing

The "emitter coupled" and" cascode" configurations contain essentially the same components; they
are available as either type 703 (F igure 3), which

Both the 703 and 171 are biased by using the
inherent match between adjacent monolithic components. They are designed for use with conven-

R1

SOH

FIGURE 3. LM703 Configuration

AN6-1

"'tJ

r-

."

m
:lJ

en

tional tuned interstages, in which DC bias currents
flow through the input and output tuning inductances.

-~

""

~+ =~2V

",
~

R2
2.5K

f--

TA = 25°C f--

\

\

-250

-150

\.

" t'-.

50

-50

150

250

INPUT VOLTAGE - mV

FIGURE 5. Emitter Coupled Transfer
Characteristic
FIGURE 4. 171 Configuration
In either case, a resistor forces DC current from
the positive supply into a chain of diodes (two for
the 703, three for the 171), proportional to the
difference between supply and forward diode-chain
voltages, and inversely to the value of the resistor.
The forced current, Ibias establishes a voltage drop
across the bottom diode (in reality, an NPN transistor with collector-base short), which is identical
to the base-emitter voltage required to force a collector current of Ibias in a matched common-emitter
stage. Since the transistor is monolithically matched
to the bottom diode, and of fairly high DC "beta",
an efficient, reliably biased current source is created.

Total current through an NPN differential pair is
determined by the current source, while current
"split" depends on the differential base voltage.
Common-mode base voltage is readily available by
using the tap at the top of the diode chain. In the
703, the differential emitters operate at a forced
voltage of one forward diode drop, V be' the current source still being effective with zero volts,
collector to base. Because the 171, as a cascode,
requires high frequency performance of the current source, three biasing diodes are used, fixing
the differential emitters at 2 V be'
Both 703 and 171 function as ordinary differential
amplifiers, splitting available current source drive
equally, when base voltages are equal, and being
capable of either complete cutoff, or full conduction of available current into one of the pair, depending on differential input. In emitter coupled
service, the input signal is injected in series with
the differential pair's DC bias, while, in the cascode,
it is in series with the current source's base bias.

The transfer characteristic of Figure 5 is represented
by the equation:
.
I (current source) == 1 +
I (output)

(1)

Calcu lating the difference in V IN required to change
this ratio from 10% to 90%, it may be seen that:
V IN (10%) - V IN (90%)

= 2kqT

(In e 9)

=

(2)

0.384T (mV)
This quantity, the transition width of an emitter
coupled amplifier, is independent of supply voltage
and current, and proportional to absolute temperature, varying from 84 mV at-55°C to 153 mV at
+125°C, and is approximately 114 mV at 25°C.
Forward transconductance, however, is directly proportional to total supply current, taking the approximate form:
! Y21!

= 3.6

(lsupply, rnA)

mmhos

(3)

at 25°C, 10.7 MHz, for either 703 or emitter-coupled 171. Thus, emitter coupled amplifier gain may
be controlled by externally varying "bias chain"
current, changing the current source by the same
amount, but without affecting transition width.
Because an emitter coupled amplifier's input impedance is a function of drive level (Figure 6),
interstages designed with small-signal y-parameters
may exhibit center frequency shifts and bandwidth
decreases as signal level increases. This is less of a
problem in FM I F strips, where input signal amplitude is essentially constant, dictated by the limiting characteristics of the previous stage (F igure 7).
14

35
Vee = +12V, 10.1 MHz

~

30
25

Emitter Coupled Operation
To assure symmetrical limiting, and maximum sma 11signal linearity, it is necessary that the differential
pair be closely balanced, so that quiescent operation
occurs in the center of the amplifier's transfer characteristic (Figure 5). Typical V be matches better
than ±0.3 mV, for both 703 and 171 assure this,
provided that DC resistance of the input inductor
is so low that input bias currents in the 50 IlA
region do not induce appreciable input offset voltages;

Jq:~N)

~-

20

~

15

--

:::>

~~

"-.

z:

0

100

200

300

400

500

frns INPUT VOLTAGE ImV)

FIGURE·6.

Effect of Drive Level on Emitter
Coupled Input Impedance

'--------------------------------------.~------------~~

AN6-2

tE-

10.7 MHz MATCHED TD 50 OHM SOURCE

-20
-50

'" fiIi"ffn
-40

-30

-20

-200

-10

INPUT POWER (dBm)

FIGURE 9. Tuned Cascode Power Gain vs AGC

FIGURE 7. Emitter Coupled Limiting
Characteristics
Cascode Operation
The cascode configuration exh ibits the same input
characteristics asa common-emitter stage, and nearly the same output characteristics, but has superior
available gain and stability; thus, it may directly replace many existing AM-IF designs. The modified
cascode possible with the 171 allows the effective
forward transconductance to be controlled by a
small DC voltage, applied differentially between
Pins 1 and 7, as in Figure 2. With the AGC input
near ground, and the base of the output commonbase transistor at 3 V be (from the bias chain), the
output transistor acts as it would in an ordinary
cascode circuit. As the AGC transistor's base voltage is increased, it begins to conduct part of the
available DC current and a proportional amount of
signal, from the input stage. As emitter current increases in the AGC transistor, its emitter resistance
decreases, while the emitter resistance of the output
transistor increases proportionally; when the d ifferential pair is balanced, output is reduced by half,
and increased AGC voltage causes all DC current,
as well as nearly all signal, to be shunted to the
AGC transistor (Figure 8). Infinite gain reduction
is not possible, because of capacitive leakages in the
cut-off output transistor; nevertheless, large AGC
range per stage is possible (Figure 9).
50

50

40

40

30

30

and 100 MHz, for example, 171 Yo is about
50 mmhos. From Equation (4), it may be seen
that balanced conditions (V age == 3 V be) result in
the exponential term equaling unity, so that forward transconductance is half of its maximum
value.
The combined second-stage input admittance seen
by the collector of the input transistor remains
essentially constant, as balance of the differential
pair is varied; thus, input admittance of the cascode
remains constant over a wide AGC range, allowing
interstages to be sharply tuned without fear of
center frequency or bandwidth shift when AGC
is applied (Figure 10). Moreover, the exceptionally
low reverse transconductance (.001 mmhos or less
at 200 MHz) allows high-Q interstages to be aligned
in an I F strip with minimal interaction between
succeeding tuning operations.

I I

1400

en

~

~

455
. 1200
1000 r-155

~.

800

~

600

f--

400

~

r

k1

24

Rp

20

I

I I

o

250 MHz Rp

-200

-100

~
U

12

~.

8

~

Vee = +12V

45 MHz Rp
200

u:

16 ~

f5 MHt Cp

:::>

z

28

k~Z Cp

~MHzCp

+100

+200

o

VAGC (mV) PIN 1 TO 7

~

E

.§.

.§.
{
1
R;- ~ \21rfoRsC2
thus,

AN6-4

)2

(10)

C2

llpF
lS0n

90001!

=~3pF

C4

L1

C3

Cl

Rs·son

RL'SOll

OUTPUT

INPUT

FIGURE 11. Equivalent 100 mHz Cascode Networks

(11 )

and

( 12)

eters must be weighed against each other. Since
design techniques are well covered in the literature(4,5,6, 7), only a brief discussion of design considerations wi II be included in this report.
Maximum available power gain may be calculated
for either 171 or 703 as emitter coupled amplifier,
using the formula of the preceding example. At
10.7 MHz, 25°C, and Vee = 12V, using 703 values,
y" = 0.35 +j 0.61 mmho (R 1N =2.9k, C1N ==9pF)

substituting,

Y2' = -33.4 + j 5.88 mmho (note negative
real part)
Y'2~

0.002 + j 0 mmho

Y22:= 0.03 + j 0.18 mniho

solving,

(ROUT
COUT

C, = 6.8 pF,

C2

= 9.4 pF

The same procedure and equivalent circuit may be
used to determine values for the output network;
in this case, however, the choice of total output
capacitance is not arbitrary, since a known bandwidth is desired. For a 5 MHz bandwidth, conjugate
matched to 9000 ohms,

MAG:=

I
~
12

49 11 g22

==

(X

== 33k,
:= 2.6 pF)

-3 2

34 10 )
== 2.75Xl03
4(.35XlO- 3 X .03X 10-3 )

:= 34.4 dB
(Due to somewhat different typical y-parameters,
MAG for an Emitter Coupled 171 == 39 dB.) .
Calculating the stability criterion:

100
fo
Q= BW = 5 = 20
.
20
21T(108 ) (4500)

= 7.1

pF
(.002Xl 0-3X34Xl 0- 3 )

6.8Xl0-8
C,

C2

~

j

2.1Xl0-8+ 6. 7Xl0-8
9000 _ 1= 13.4-1 = 12.4
50

solving,
C, = 4.4 pF,

C2 = 55 pF

Laboratory measurements, in which circuit values
given above were used as design centers for adjustment, give typical cascode power gain of 27.5 dB,
with the desired 5 MHz bandwidth, using carefully
constructed, low loss inductors.
10.7 MHz FM IF Using Emitter Coupled Amplifiers
Complete design of a high quality FM I F strip is a
painstaking process, in which a number of param-

:= 0.775
For the conditions given, 0 < C < 1, making the
device unconditionally stable for all sources and
loads. In a practical 10.7 MHz I F strip, however,
external coupling, especially from the strip's output
to its input, can cause instability without careful
physical design.
A modern FM tuner I F strip capable of low-distortion multiplex reception, requires:

A. Bandwidth at least 300 kHz. In a four stage
design, with five interstage networks, bandwidth per stage may be calculated from overall
bandwidth by use of the "shrinkage" formula:
BW (per stage:=
___ (n== num b er 0 f
) BW(overall)
V2'/n -1
interstages)

AN6-5

300

y21/5 -1

300
.388

(13)

= 773 kHz

B.

C.

Sharp skirt selectivity without phase/frequency
nonlinearity within the passband. This usually
implies double-tuned interstage transformers.
Stover, et. al. (5), show that a transformer coupling factor between 0.6 and 0.8 gives minimum
phase nonlinearity, the higher value being preferred for higher gain per stage.
Overall power gain of at least 100 dB, or 25 dB
per stage in a four stage strip, to obtain adequate sensitivity and AM rejection.

D. A maximum value of load resistance across the
output of each stage, given by:

( 14)
where N = number of bias chain diodes

N

= 2 for the 703,

or 3 for the 171

IOUT(MAX) is approximately 5 mA, for
both types.
This relationship assures that maximum output
current limiting is reached before the output
transistor can saturate, guaranteeing non-saturated limiting action.
E.

AN6-6

The input admittance used in making interstage
calculations should be the value resulting from
a given value of input swing, (see Figure 6),
rather than the small-signal value. The input
swing, however, depends upon the transformer
ratio, so that transformer optimization is a
mu Iti-approx imation procedure.

F.

The interstages should be designed to minimize
the effects of varying drive levels upon center
frequency and bandwidth, since very weak signa Is may operate the first one or two stages
linearly, rather than as limiters.

References

1. R. Hirschfeld, "Design Freedom Through User
Options in Monolithic RF/IF Amplifiers", Proceedings EEE linear I/C Clinic, 3/24/67, Mactier
Pub. Corp.

2. J. Robertson and R. Hirschfeld, "Application of
Microelectronics to IF Amplifiers", IEEE Trans.
Vehicular Communications, Vol. VC-14, No.1,
pp. 162, 3/65.
3. J. Solomon and J. Narud, "Final Report, Vol. II,
USAF contract No. AF33(657) 11664", WrightPatterson AF B, 9/64.
4. J. Lin viii and J. Gibbons, "Transistors and Active
Circuits", Ch. 9-18 McGraw Hill, Inc., New York,
1961.
5. W. Stover, et. aI., "Circuit Design for Audio,
AM/FM, and TV", Ch. 7-11 McGraw Hill, Inc.,
New York, 1967.
6. W. Gartner, "Transistors: Principles, Design and
Applications", Ch. 14,15 D. Van Nostrand, Inc.,
New York, 1960.
7. J. Lauchner and M. Silverstein, "Design HighFrequency Amplifiers Graphically", Electronic
Design, 4/12/66.

June 1968

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NEW USES FOR THE LM100 REGULATOR
INTRODUCTION

THE LM100

One might think that an integrated circuit like a
voltage regulator would be limited to one specialized application. Such is not the case, as was
proven by the results of an applications contest
that was conducted recently for our LM 1 00 voltage regu lator.

Before going into the various circuits, it is in order
to describe briefly the operation of the LM 1 00. A
schematic diagram of the integrated circuit is given
in Figure 1. Generation of the reference voltage
starts with zener diode, D 1, which is supplied with
a fixed current from one of the collectors of 02.
This regulated voltage, which has a positive
temperature coefficient, is buffered by 04, divided
down by R 1 and R2 and connected in series with a
diode-connected transistor, 07. The negative temperature coefficient of 07 cancels out the positive
coefficient of the voltage across R2, producing a
temperature-compensated 1.8V on the base of 08.
This point is also brought outside the circuit so
that an external capacitor can be added to bypass
any noise from the zener diode.

The LM100 is a monolithic integrated circuit that
was designed as a series regu lator to operate in
either a linear or a switching mode. Its output voltage can be set anywhere between 2 and 30V with a
pair of external resistors. By itself it can deliver
output currents of 10 to 20 mA, but discrete transistors can be added to boost the output current to
any desired level. The integrated circuit design is
described along with its applications as a series
regulator in references 1 and 2.
The contest brought out a number of novel ways
to use the LM 1 00 in other voltage-regu lator appl ications such as a shunt regulator. Included were
temperature regulators and light-level regulators. It
was also shown that the LM 1 00 could effectively
be used as an operational amplifier, especially if
the application required a reference voltage or if it
was necessary to add transistors for increased output power.
It is appropriate to point out that all the circuits
described here for the LM100 will work equally
well with the LM200 or LM300, within their
respective temperature and operating-voltage
ranges.

,.--...- - - -......- -....--~..- UNREGULATED INPUT

Transistors 08 and 09 make up the error amplifier
of the circuit. A gain of 2000 is obtained from this
single stage by using a current source, another
collector on 02, as a collector load. The output of
the ampl ifier is buffered by 011 and used to drive
the series-pass transistor, 012. The collector of
012 is brought out so that an external PNP transistor, or PNP-NPN combination, can be added for
increased output current.
Current limiting is provided by 010. When the
voltage across an external resistor connected between Pins 1 and 8 becomes high enough to turn
on 010, it removes the base drive from 011 so the
regulator exhibits a constant-current characteristic.
As for the rema ining details, the collector of the
amplifier, 09, is brought out so that external
co II ector- base capacitance can be added to
frequency-stabilize the circuit when it is used as a
linear regulator. R9 and R4 are used to start up
the regulator, while the rest of the circuitry establishes the proper operating levels for the current
source transistor, 02.

BOOSTER OUTPUT

l -....""oN\re- CURRENT LIMIT
"""""'W'HI~---+- REGULATED OUTPUT

e.------

Now that some understanding of the internal
workings of the LM100 has been established, we
can discuss the applications for the circuit.

COMPENSATION

SHUNT REGULATOR
"'1-----

FEEDBACK

L-_ _~_ _ _ _ _ _ REFERENCE BYPASS

L-----1~--.....- - - - - - - GROUND

FIGURE 1. LM100 Schematic

Shunt regulators are sometimes substituted for
ser i es regulators even though they are less
efficient. The reason is that they are not as sensitive to input voltage transients, they do not feed
load current transients back into the unregulated
supply, they are inherently short-circuit proof and
they are less prone to failures where the output
voltage becomes excessive.

AN8-1

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Although the LM 100 was designed primarily as a
series regulator, it can also be used in shuntregulator applications. Figure 2 shows a 3A shunt
regulator. The output of the LM100 drives a com-

r------------.-----.---.-GROUND
R3
100

Rl
IS.7K
1%

Cl

47 pF
R5

lK
R4

R2

3

2.27K

50W

1%

RS
VIN-JVVv-.....- - - - - - - -......- - - - - - - - - -......- -......-VOUT

FIGURE 2. Negative Shunt Regulator

pound emitter follower which conducts the excess
input current. A zener diode, D 1, provides a level
shift so that the output transistors within the
LM100 are properly biased. R5 supplies base drive
for 02 and also the minimum load current for the
LM 100. R4 is included to minimize dissipation in
the power transistors when the regulator is lightly
loaded. The output voltage is determined in the
normal fashion by R 1 and R2. Although no output capacitor is used, it may be advisable to
include one to reduce the output impedance at
high frequencies.

Because a shunt regulator-is a two terminal device,
one design, using an LM 100, can be used as either
a positive or a negative regu lator.

This circuit was submitted by Bob Dobkin of
Philbrick/Nexus Research, Dedham, Massachusetts
and R. F. Downs of LTV Research Center,
Anaheim, California.

SWITCHING REGULATOR WITH OVERLOAD
SHUTOFF
It is difficult to current limit a switching regulator
because the circuit must continue to operate in a
high efficiency switching mode even when the output is short circuited. Otherwise, the power dissipation in the switch transistor will be excessive,
more than ten times the full load dissipation, even
though the current is limited.

A unique solution to this problem is the overload
shutoff scheme shown in Figure 3. When the
output current becomes excessive, the voltage
drop across a current sense resistor fires an SCR
which shuts off the regulator. The regulator
remains off, dissipating practically no power, until
it is reset by removing the input voltage.

I n the actual circuit, complementary transistors,
01 and 02, replace the SCR since it is difficult to
find devices with a low enough holding current
(about 50 pA). When the voltage drop across R4
rises to about O.7V, 02 turns on, removing the
base drive to the output transistors on the LM 100
through Pin 7: Then 01 latches 02, holding the
regulator off until the input voltage is removed. It
will then start when power is applied if the overload has been removed.

This circuit was designed by Dan Lubarsky of
Moore Associates, San Carlos, California.

R4
0.1

,.....-....- - -....-------~...'V\"'". .--.-'VOUT

+ CIt

T

IOO PF
35V

Dl
lN3880

C2
0.1 pF

VIN
8.5 -35V
R8
1M

FIGURE 3. 3A Switching Regulator With Overload Shutoff
AN8-2

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FIGURE 4. Switching Regulator with Crowbar Overvoltage Protection

OVERVOl TAGE PROTECTION

FOCUS CONTROL CURRENT SOURCE

A switching regulator can be used in place of a
power converter to reduce high input voltages
down to a considerably lower output voltage with
good efficiency. In addition, it simultaneously
regulates the output voltage. As a result, a
switching regulator is simpler and more efficient
than a power converter/regulator combination.
One objection brought up against switching regulators is that they can fail with the output voltage
going up to the unregulated input voltage which is
frequently several times the regulated output voltage. This can destroy the equipment that the
regulator is supplying. A power converter has the
advantage that it will usually fail with the output
voltage going to zero.

Although the LM 100 is most frequently used as a
voltage regulator, it is also useful as a current regulator. A current regulator can be made by regulating the voltage across a known resistor, producing
a fixed current.

A circuit whkh protects the load from overvoltages is shown in Figure 4. If the output voltage
should rise significantly above 6V, the zener diode,
D2, breaks down and fires the SCR, 013, shorting
the output and blowing the fuse on the input line.
C3 keeps the SCR from firing on the voltage transients which can be present around a switching
regulator, and R7 is included to make sure that
excessive gate current does not flow when it fires.
Since the SCR is located on the output of the
regulator, it is not prone to dV /dt firing on fast
transients wh ich mi ght be present on the u nregulated input.

It is important to design the regulator so that the
overshoot in the output voltage 2 caused by
suddenly removing full load current does not fire
the SCR. If this is done, about the only thing that
can cause an overvoltage output is failure of the
regulator switching transistors.

This circuit comes from E. S. Madson of ESM,
Copenhagen, Denmark and Don learned, Heath
Company, Benton Harbor, Michigan.

The focus control current source shown in
Figure 5 is an example of such a current regulator.

V1N = 30V----'
C3

Io.1/.1F
tSolid Tantalum

FIGURE 5. Focus Control Current Source

The output current from the pass transistor, 01, is
set by selecting an appropriate value for R5 and
then adjusting the voltage drop across it with R4.
With the arrangement: used, most of the power is
dissipated in R5 rather than the control potentiometer. R2 is included in the adjustment circuit so
that the LM 100 feedback terminal operates from
approximately 2.2 kSl source resistance. This is
the optimu m design value for minimum thermal
drift and proper frequency compensation.
The regulator is protected against shorts to
ground, from the focus coil or its leads, by R 1. D 1

AN8-3

prevents voltage reversals on the integrated circuit
or the pass element, caused by the inductive kickback of the focus coil, when the input voltage is
switched off. C2 and C3 are required to keep the
circuit from oscillating.
A particu lar advantage of the LM 100 in th is appl ication is that its low reference voltage enables it to
regulate a current with a minimum of voltage
dropped across the sense resistor. This is important
both to increase the efficiency and to minimize
dissipation in the sense resistor which usually must
be a precision resistor.
This design was submitted by H. J. Weber of
EG&G, Boston, Massachusetts. Similar circuits
were sent in by C. M. Katkic of Michigan Bell
Telephone Company, Southfield, Michigan and C.
H. Ristad.

1A CURRENT SOURCE
Another current source circuit is shown in Figure 6. Here the LM 100 regu lates the emitter cur-

The maximum supply voltage (V+) that can be
used with this circuit is limited only by the breakdown voltage of the control transistors. If this
voltage is less than 40V, this supply can also be
used to power the LM 100.

The regulator can be switched off electrically by
clamping Pin 7 of the LM 100 with a 1 kU resistor,
a diode,anda transistor to ground. If it is desirable
to operate the circuit as a fast switch, however, 01
should be replaced with a faster transistor like,the
2N3445 and Cl should be reduced to 47 pF. It
would also be advisable to use a 1N3880, which is
a faster device, for D 1.

This circuit was contributed by Bob Dobkin of
Philbrick/Nexus Research, Dedham, Massachusetts; Tom Hall of Bausch and Lomb, Bellaire,
Texas and Steve Menasian of the University of
Washington, Seattle, Washington.

SWITCHING CURRENT REGULATOR
Current regulators generally operate with a large
voltage drop across the control transistors since
they must accommodate large variations in the
voltage across the load. Consequently, the power
dissipation in the transistors can be qu ite high.

VIN

> B.5V

FIGURE 6. 1A Current Source

rent of a Darlington-connected transistor, and the
output current is taken from the collectors. The
use of a Darlington connection for 01 and Q2
improves the accuracy of the circuit by minimizing
the base-current error between the emitter and
collector current.
The output of the LM 100, wh ich drives the control transistors, must be short-circuit protected
with R6 to limit the current when 02 saturates.
R7 is required to provide the minimum load current for the integrated circuit. Dl is included to
absorb the kickback of inductive loads when
power is shut off. The output current of the circuit is adjusted with R2.
AN8-4

The switching regulator principle can be applied to
a current regulator to greatly increase efficiency
and reduce the power dissipation in the control
transistors. Figure 7a gives the schematic of a
switching current regulator wherein the input
power, I for a fixed load current, is roughly proportional to the voltage across the load. A
standard switching regulator is used, except that
the load is connected from the output to the feedback term inal of the LM 100. A current sense resistor, R 1, is connected from the feedback terminal
to ground to set the output current. If desired, an
adjustment potentiometer can be connected across
the current sense resistor as shown in Figure 6.

An additional filter capacitor, C2, is put across the
load terminals to reduce output ripple.)f it is not
needed, it can be removed if' an 0.1 /IF capaeitoris
connected from the top of Cl to Pin 6 of the
LM 100 to make sure all the output ripple of the
regulator appears at the feedback terminal.

An alternate scheme which has the current output
referenced to ground is given in Figure 7b. This
circu it is identical to that in Figure 7a except that
the load is inserted in the ground line. The
quiescent current of the regu lator, flowing out of
Pin 4, introduces an error term. However, since
this current is only about 2 mA and is reasonably
independent of changes in the input or load voltages, the error is usuallY not significant.

01
1N3880

OUTPUT

R5
1M

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t 60 Turns #20 on Arnold

Engineering
A 930157·2 Molybdenum Permalloy Core

a. Current Source With Floating Load

01
1N3880

G2
-2N3445 '

R2
2K

R1
0.9

VIN--+---.........-~...- - - - - -....

R5
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t 60 Turns #20 on Arnold Engineering
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----r-

~+ ..-(
C2t
47 J1F
35V

OUTPUT

b. Current Source With Grounded Load

FIGURE 7. Switching Current Regulators

With this circuit, the difference between the input
voltage and the load voltage cannot drop below
8.5V, or the circuit will drop out of regulation
because the voltage across the LM 100 is insufficient to bias the reference circuitry.

This circuit was sent in by T. H. Lynch of BunkerRamo Corporation, Canoga Park, California.

TEMPERATURE CONTROLLER
A circuit for an oven-temperature controller using
the LM100 is given in Figure 8. Temperature
changes in the oven are sensed by a thermistor.
This signal is fed to the LM100 which controls
power to the heater by switching the series pass
transistor, Q2, on and off. Since the pass transistor
will be. nearly saturated in the on condition, its
power dissipation is minimized.

AN8-5

27±4V V+

POWER AMPLIFIER

~~

~02

118v

01
10V
Q2

2NJ055

* Approximatelv 10K @ +85°C

FIGURE 8. Switching Temperature Controller

In operation, if the oven temperature should try to
increase, the thermistor resistance will drop,
increasing the voltage on the feedback terminal of
the regulator. This action shuts off power to the
heater. The opposite would be true if the temperature dropped.

Variable-duty-cycle. switching action is obtained
by applying positive feedback around the regulator
from the output to the reference bypass terminal
(which is also the non-inverting input to the error
amplifier) through C1 and R4. When the circuit
switches on or off, it will remain in that state for a
time determined by this RC time constant.

Additional details of the circuit are that base drive
to 01 is limited, to a value determined by R2, by
th e internal current-limiting circuitry of the
LM 100. 02 provides a roughly regulated supply
for 01 in addition to fixing the output level of the
LM100 at a level which properly biases the intern a I transistors. The reference diode for the
thermistor sensor, 01, need not be a temperaturecompensated device as long as it is put in the oven
with the thermistor. Finally, the temperature is
adjusted with R5.

Using a thermistor with a temperature coefficient
higher than 1%tC, control accuracy should be
better than ±1°C for a wide range of ambient conditions, even if the LM 100 is not put inside the
oven.

This circuit was contributed by C. W. Andreasen
of Stromberg-Carlson, San Diego, California and
A. B. Williams of Stelma Incorporated, Stamford,
Connecticut.
ANS-6

The versatility of the LM 100 is demonstrated by
the power amplifier circuit in Figure 9. The
LM 100 is used as a high-gain amplifier and connected to a quasi-comp lementary power output
stage. Feedback around the entire circuit stabilizes
the gain and reduces distortion. In addition, the
regulation characteristics of the LM 100 are used to
stabi I ize the qu iescent output voltage and
minimize ripple feedthrough from the power
supply.
The LM 1 00 drives the output transistors, 05 and
06, for positive-going output signals while 01,
operating as a current source from the 1.SV on the
reference termi nal of the LM 1 00, suppl ies base
drive to 03 and 04 for negative-going signals. 02
el imi nates the dead zone of the class-B output
stage, and it is bypassed by C5 to present a lower
driving impedance to 03 at high frequencies. The
voltage drop across 02 will be a multiple of its
emitter-base Voltage, determined by R9and R10.
These resistors can therefore be selected to give
the desired quiescent current in 04 and 06. It is
important that 02 be mounted on the heat sink
with the output and driver transistors to prevent
therma I runaway.
Output current limiting is obtained with 02 and
03. 02 clamps the base drive of 03 when the
voltage drop across R6 exceeds one diode drop,
and 03 clamps the base of 05 when the voltage
across R7 becomes greater than two diode drops.
R 11 is needed to limit the output current of the
LM 100 when 03 becomes forward biased.
The power supply ripple is peak detected by 01
and C1 to get increased positive output swing by
operating the LM 100 at a higher voltage than 05
and 06 during the troughs of the ripple. This also
reduces the ripple seen by the LM 100. C5 bypasses
any zener noise on the reference terminal of the
LM 100 that would otherwise be seen on the output.
The quiescent output voltage is set with R2and
R3 in the same way as with a voltage regu lator.
The ac voltage gain is determined by the ratio of
R 1 and R3, since the circuit is connected as a
summing amplifier~
This circuit was designed by Bob Dobkin of
Philbrick/Nexus Research, Oedham, Massachusetts
and H. D. Carlstrom, Sanders Associates, Nashua,
New Hampshire.

HIGH EFFICIENCY SINGLE-SIDEBAND
TRANSMITTER

A circuit which can be used to improve the efficiency of a single-sideband transmitter is shown in
Figure 10. A switching regulator 'operates the
linear output amplifiers of a conventional singlesideband transmitter at a voltage just higher than
that required to accommodate the envelope 'of the,

V+--"~------------------------------------------------__~--~

36V

01
1N4002

TO LOW
LEVEL STAGES

....~----......f
Q1

2N2219

+

T

C1
500 J.l.F
R1
2.2K
C2
10 J.l.F

T

R3
22K

* Mount on Heat Sink With
Power Transistors
t Can be Selected for Desired
Ouiescent Current

INPUT

FIGURE 9. Power Amplifier With Current Limiting

AUDIO INPUT

BALANCED
LOW LEVEL
MODULATOR I-------IH
LINEAR AMP
AND FILTER

DRIVER
AMPLIFIER

LINEAR
OUTPUT AMP

ENVELOPE
DETECTOR
AND 2.5 KHz

RF SIGNAL
SOURCE

LP FILTER

1.BV-NO MODULATION
20V - PEAK FOR MODULATION

L1*

+

01
1N3BBO

I

C2
0.02J.1.F _

R4
2.2K

t
C1
3.9 J.1.F
35V

02
2N3B79

UNREGULATED
INPUT
+2BV

--+-------1....----..-------......

* 95 Turns #22 on Arnold Engineering
'A 193105·2 Molybdenum Permalloy Core
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FIGURE 10. High Efficiency Modulation Scheme for Single Sideband Transmitter

rf output signal. With no modulating signal, the
driver and output amplifiers are operated at 1.BV,
which is the reference voltage of the LM100. When
modulation is present, the envelope of the rf wave-

form is detected and used to drive the regulator so
that its output voltage follows the shape of the
envelope. Hence, the amplifiers are always
supplied just enough voltage to keep them from
ANB-7

saturating. Since the switching regulator converts
the dc input voltage down to the lower voltage
driving the amplifiers with high efficiency, the
overall transmitter efficiency is increased.
The amplitude of the envelope on the output of
the switching regulator is determined by R5, as the
detected envelope will be multiplied by the ratio
R4/R5. The output signal ofthe envelope detector
must be negative-going so that the drive voltage
will be positive-going. In addition, it is necessary
to dc couple or clamp the detected envelope so
that the supply voltage to the ampl ifiers does not
drop below their minimum operating level on the
troughs of the signal. It is also important that the
output amplifiers be designed so that their gain
does not vary with the voltage supplied to them or
distortion will be introduced.
This technique can be used to increase efficiency
with AM transmission. Here, the switching regulator is driven with a negative-going modulation
signal, which has been clamped to 1.8V, instead of
the detected envelope. The regulator output drives
a class-C rf power stage. The output waveform of
the regulator must accurately follow the modulating signal, and the ripple on the output of the
switching regulator must be eliminated because the
drive signal to the output amplifier appears directly on the envelope of the rf output. These conditions can be satisfied by operating the switching
regulator at 100 kHz and using additional filtering
between the regu lator and the output stage.
With either modulation'scheme, the output voltage
of the regulator/amplifier can be limited by
putting a zener diode across R4. This protects the
rf output amplifier from excessive voltage caused
by overmodulation or high dc input voltage.
This design comes from Ben Stopka of Collins
Radio, Cedar Rapids, Iowa.

LIGHT-INTENSITY REGULATOR
Figure 11 gives the circuit for a light-intensity
regu lator using the LM 100. A phototransistor
senses the light level and drives the feedback
terminal of the LM 100 to control current flow
into an incandescent bulb. R 1 serves to limit the
inrush current to the bulb when the circuit is first
turned on.
The current gain of the phototransistor, 02, is
fixed at 10, to make it less temperature sensitive,
by R3 and the temperature compensating diode,
D 1. A photodiode, such as the 1N2175, could be
substituted for the phototransistor if it had sufficient light sensitivity; and R3 and D 1 could be
eliminated. The input voltage does not have to be
regulated as the sensitivity of a phototransistor or
photodiode is not greatly affected by the voltage
drop across it. A photoconduc(or can also be used
in place of the phototransistor, except that input
voltage would have to be regulated.
ANS-8

VIN-4I~--------------""

FIG U R E 11. Light Intensity R egu lator

This circuit is adapted from one submitted by
Geoffrey Hedrick of Lear Siegler/Astek Division,
Armonk, New York.

HIGH VOLTAGE REGULATOR
Although the LM 100 was designed primarily for
appl ications with output voltages below 30V, it
can be used as a high voltage regulator under
certain ciTcumstances. An example of this, a circuit regulating the output of a 2 KV supply, is
given in Figure 12.
The LM100 senses the output of the high voltage
supply through a resistive divider and varies the
input to a dc/dc converter, which generates the
high voltage. Hence, the circuit regulates without
having any high voltages impressed across it.

Under ordinary circumstances, the feedback
termi nal of the LM 100 wants to operate from a
2K divider impedance. Satisfying this condition on
a 2 KV regulator would require that about 2W be
dissipated in the divider. This, however, is reduced
to 40 mW by the addition of 01 which acts as 'a
buffer for a high impedance divider, operating the
LM 100 from the proper source resistance. The
other half of the transistor, 02, is required to compensate for the temperature drift in the emitterbase voltage of 01, so that it is not multiplied by
the divider ratio. The circuit does have an uncompensated drift of 2 mV
but this is added
directly to the output, not multiplied by the
divider ratio, so it will be insignificant with a 2 KV
regulator.

tc;

This circuit was contributed by Don Sobel .of
Federal Scientific Corporation, New York, New
York and A. A. Frank of the University of
Southern California, Los Angeles, California.

R4
0.2

+

VOUT
2 KV

C1 t

¥35V

03
2N3055

DC/DC
CONVERTER
12V/2 KV

R1
100M
1%

VIN
18V

t Solid Tantalum

FIGURE 12. High Voltage Regulator

SIGNAL
OUTPUT

CATHODE

C1
0.01 J.lF

C2
0.01 J.lF

C3
0.01 J.lF

C5
0.01 J.lF

C4
0.01 J.lF

Rl
ANODE
R1
DY9
DY1
20K
10W
DYNODE
DIVIDER
STRING

* RCA

R2
20K
10W

01*
40425

02*
40425

03*
40425

04*
40425

05*
40425
R8
2K
1%

R9
500
1%

R3
100K

R10
390
1%

20 J.lF
600V

+
09
06

FIGURE 13. Photomultiplier Tube Supply

PHOTOMULTIPLIER TUBE SUPPLY
A second high voltage supply is diagrammed in
Figure 13. This is a high voltage supply for a
9-dynode photomu Itiplier tu be. I n this circuit, a
full wave rectifier operating off one winding of a
power transformer provides a 15V bias voltage for
the LM 100. The high voltage is produced from a
voltage doubler which operates from a second
winding. The circuit actually functions as a current
regulator similar to that shown in Figure 6. The
output current is passed through a resistive divider
which develops the operating voltages for the
cathode and dynodes of the photomultiplier tube.

L..-----------..... __ 15V J

Five cascode-connected transistors, Q 1 through
05, are used as the pass transistors. This is presently the lowest-cost solution to the problem of
handling the required voltage and power levels.
Base drive is provided for: the cascode string, by
R3 through R7, in a manner which does not affect
regu lation. Capacitors, C1 through C5, suppress
and equalize transients across the pass transistors;
and clamp diodes across the sensitive emitter-base
junctions of the transistors prevent damage from
voltage transients.
This circuit was designed by J. P. Ekstrand of
Spectra Physics, Mountain View, California.

AN8-9

LINE RESISTANCE COMPENSATOR
Remote sensing of the load voltage to eliminate
the effects of line resistance can be done with the
L M 100 by connecting the feedback resistors
directly across the load, rather than at the regulator output. However, it may be necessary to
increase the size of the frequency compensation
capacitor ordinarily used with the regulator. In
certain applications, remote sensing is undesirable
or the actual load is not directly accessible. An
example of this is a dc motor application where it
is desirable to reduce the effects of the armature
resistance.

This circuit was suggested by W. J. Godsey of
Hayes International Corporation, Birmingham,
Alabama.

USING ALL NPN PASS TRANSISTORS
The LM 100 was designed t6 use a PNP or
PNP/NPN combination for the series pass element.
With this configuration, the minimum outputinput voltage differential is not increased by the
addition of booster transistors. However, the
device can also be used with all NPN pass transistors as shown in Figure 15.

R3
. - - -......-

0.1

.......:.I\I'II\r-......- - - - -......- . . . - V OUT

+

Cl
47 pF

Rl

r----------.--t.....

- - - V IN

cz t

T-:: 4.7 f.lF

RZ

R6

t Solid Tantalum

R4

0.1
--e--VOUT

FIGURE 14. Line Resistance Compensator for
High Current Regulators

A circuit which permits compensation of line resistance is shown in Figure 14. A negative-going voltage which is proportional to the load current is
produced across R6. Divider resistor, R2, is
returned to this voltage so that the output voltage
will increase with increasing load current. The
ground terminal of the regulator is returned to the
arm of the potentiometer connected across R6 so
that the compensation can be set to exactly cancel
out the line resistance. With the arm of the
potentiometer on ground, the output resistance
will be reduced by R6 multiplied by the ratio of
R 1 to R 2. With the potentiometer set to the
opposite extreme, the output resistance will be
increased by the value of R6.
There is a reason why R5 is included, and R6 is
not just made a potentiometer. It is practically
impossible to find a potentiometer with a low
enough resistance value and high enough power
rating. In fact, with higher currents, it is even hard
to find a suitable resistor for R6. A O. Hl, lOW
resistor is not easy to find. One way of getting it is
to take a ln, lOW, adjustable, wire-wound resistor
and put two taps at the 1/3 resistance points. The
three resistor segments are then connected in
parallel to make a 0.1 H1, lOW resistor.
AN8-10

FIGURE 15. Circuit for Using the LM100 With all
NPN Pass Elements

With this configuration, it is not possible to use
the internal current limiting of the LM100, so an
external transistor, 03, must be added to provide
this function. Limiting occurs when the voltage
drop across R4is equal to the emitter-base voltage
of Q3~ R5isalso required to make sure that the
LM100 is operated above its minimum load current.
The main advantage of using all NPN pass
transistors is that the circu it can be operated with
less capacitance on the output of the regu lator.
When NPN and PNP transistors are used, relatively
large (1-10 J1F) bypass capacitors must be connected on both the input and output of the regulator. Without these, the circuit is susceptible to
oscillations.
This design w~s based on a circuit submitted by E.
F. Donner of Lockheed, San Jose, California ..

HIGH STABILITY REGULATOR
The performance of regulators with output voltages above 10V can· be improved considerably by
the addition of an external temperaturecompensated reference diode. Normally, the voltage change at the feedback terminal of the LM 100
due to changes in temperature, load or input voltage are mu Itipl ied by the divider ratio of the feedback resistors which determine the output voltage.
This effect can be reduced by putting a reference
diode in the feedback divider as shown in Figure 16. The diode permits a lower divider ratio to
be used and, therefore, improves regulation and
drift characteristics.

Although the circuit shown is a low current regulator, this idea is equally useful for high-power
linear regulators and even switching regulators.

14

.1 ,
I.

12

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10

t-

--25°C

Z

~

a:

8

;:)

Co)

~
~
N

6
4

o

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100°C-- ~/T-55°C
I
I I I'

"e

V

I

10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8
ZENER VOLTAGE (V)

~----4I""---------1"'-VoUT=15V

FIGURE 17. Drift Characteristics of an 1N944A as
a Function of Operating Current

C1
47 pF

This contribution was made by Ahti Aintila,
Helsinki, Finland.

R2

10K

PULSE REGULATOR
Because of the relatively fast ope~ation possible
with. the LM 100, it can be used as a pulse squarer
or pulse regulator. A circuit which accomplishes
this is shown in Figure 18.

t May be Adjusted to Improve

Temperature Orift

~--~""------4IJ-----4""OUTPUT

FIGURE 16. High Stability Regulator

The regulation of the circuit in Figure 16 is given
by
R5

V+-~-'"

at
2N2369

where V z is the breakdown voltage of D 1 and V FB
is the voltage on the feedback terminal of the regulator. Hence, the improvement in regulation and
temperature drift (assuming no driftin the external diode) will be V

V

OUTV
OUT Z

,which is equal to

R4
PULSE
INPUT

FIGURE 18. Pulse Regulator

4.5 in the example given.
The temperature drift can be improved still further
by adjusting R3 to compensate for the combined
drift of D1 and the LM100. Changing the diode
current changes its drift, as shown in Figure 17.
Larger values of R3 make the output voltage temperature coefficient more negative, while decreasing the resistor makes the temperature coefficient
more positive.

In this circuit, R2and R3 are set up to give the
desired pulse height (dc) from the LM 100. A
positive-pulse input turns on 01, which disables
the LM 100 by grounding the base of the NPN
emitter followers on the output of the integrated
circuit. At the same time, 02 grounds the regulator output, providing current-sinking capability.
AN8-11

If additional output-current drive is needed, an
NPN buffer, similar to that shown in Figure 15,
should be used on the LM 100 in place of a PNP
because of the difficulties encountered in stabilizing the PNP circuit without capacitance on the
output.
This method of pulsing the circuit on and off, that
is pulling Pin 7 down within one diode drop of
ground, can be used as an electrical shutoff for any
of the voltage or current regulators.
Credit for this circuit is given to Don Maurer of
Medtronic Incorporated, Minneapolis, Minnesota
and E. E. Cunningham of Ectron Corporation, San
Diego, California.

CONCLUSION
These examples show that certain integrated circuits can be treated like a component, rather than
a specialized circuit funCtion. This seems to be
particularly true for linear integrated circuits. It is
possible to use almost any standard circuit in a
wide variety of applications by designing imaginatively. If this is done, it is possible to reap the
rewards of standard circuits - low cost and
immediate availability - in practically any equ'ipment design.
REFERENCES
1. R. J. Widlar, "A Versatile, Monolithic Voltage
Regulator," National Semiconductor Corporation AN-1, February, 1967.
2. R. J. Widlar, "Designing Switching Regulators,"
National Semiconductor Corporation AN-2,
April, 1967.

AN8-12

»
2
December 1968

.....
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LOW POWER OPERATIONAL
NHOOOl AMPLIFIER

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INTRODUCTION

CIRCUIT OPERATION

Although many Integrated Circuit Operational
Amplifiers are available with excellent characteristics, two areas leave considerable room for
improvement; namely, offset voltage and power
requirements. The NH0001 operational amplifier
has been designed to provide extremely low offset
voltages (typically 0.2 millivolts at 25°C) and quiescent supply currents in the 100 pA range, while
still providing reasonable loaded output swings and
a compensated gain bandwidth in the 0.5 to
1.0 MHz range. The circuit diagram (Figure 1A and
1B) shows the simplicity of the NH0001; the only
unusual characteristic being the use of PNP transistors in the input stages for improved beta vs.
temperature linearity and lower noise.

01,02, R 1 and R2 form a simple constant current
supply of ~16 pA at 25°C, 8 pA at +125°C and
22 pA at -55°C. This current is supplied to the
common emitters of the input pair 03 and 04
which, along with their load resistors R3 and R4,
form a simple differential amplifier. The low frequency gain of this stage is approximately 30,
minimizing the effect on the input of changes in
offset voltage in the second stage pair, 05 and 06.

o

The second stage differential pair with high impedance load, 08, form the main voltage gain of the
amplifier. Typical values of collector currents in
05 and 06 are 20 pA each and the voltage gain of
this stage is approximately 2000.
The output section is simply a compound
NPN - PNP pair providing isolation between the
high impedance junction of the collectors of 06
and 08, and the load.

R6
SDK

R7
SDK

CLAMP
AND
COMPENSATION

CDMP
R3
3DOK

R4
3DDK

RS
SDK

When operating from ±V supplies, pin 7 is
normally returned to ground. When operating
from a single supply, or when no ground is available, pin 7 may be directly connected to pin 3, for
voltages equal to or less than 20 volts between
pins 3 and 9. This will increase the quiescent current since the effect of connecting pin 7 to pin 3 is
to connect the 600K resistor, R 1, across the full
power supplies. Since the minimum current required from pin 7 is 10 pA, an external resistor
(Rx) may be inserted in series with R 1 from pin 7
to pin 3.

L..-~~------~~------~~-3

V-

Figure 1A. NH0001 Schematic.

Recommended range for value of Rx is shown in
Figure 2.

..,oj

I/~

COMPENSATION

'I---

<.:I

~

2 i---- i---- f - MAX. ~

V

~

V

~

1/

~

100""

~l-1/
Iiii"'"
~
~ ~ Ii-"
o
~

~

~

COMPENSA TlON

20

10

30

40

VOLTAGE BETWEEN PINS 3 & 9

,

.. J

TOPVIEW

Figure 1B. NH0001 Pin Configuration.

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Operation from Single Power Supply

L..--t---l0

COMP

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Figure 2. Range of Resistor Values Inserted from Pin 7
to Pin 3 when Pin 7 is not grounded.

AN10-1

Clamped Output Swing
The output voltage can be quite effectively held
between specified limits by means of diode clamps
on pin 10. From Figure 3 which is the output section of the NH0001, clamping pin 10 will maintain
the output within one V SE of pin 10. Since I S (+)
and Is (-) are I imited to approximately 75 pA at
25°C, the extra quiescent current is quite nominal.

I
VOUT
~ r-- -

~

4

VREF

>

:\
\

J
I
II

,

V,N

I
o

2

\
4

6

8 10 12 14 16 18 20

TIME (I'sec)

OUTPUT
PIN 8

Figure 58. Output Waveform When Used in Circuit of
Fig. ~A.

For driving MOS inputs or clocks, the NH0001 is
connected as follows:
tlOV

Figure 3. Output of NH0001

A specified output range may be obtained by
appropriate connection of diodes from pin 10 to
the reference limits. Figure 4 shows the connections for various reference levels.
A typical use of a clamp on pin 10 is to provide
compatible drive for either DTL or T2 L logic circuits. This is usually accomplished with a 5 volt
Zener diode or the emitter-base junction of a

OUTPUT

+V1

-V2

INPUT

+3V

-30V

Figure 6A. NH 0001 As Comparator For Driving MOS.

Delay and storage times of 3 to 5 11 sec will be
observed with rise and fall voltage rates of 2 to
4 volts/psec. Capacitance loads of up to 1000 pF
will not noticeably increase the switching times.

Output range mavvarv berween+V, and-V2

+10 f - INPUT

+5
INPUTS

OUTPUT

'"....

,

-25

\

!\

-15

-30

o

'1

Vz ; 7.5V

-20

> -10

OUTPUT

1-

\

-5

0

Output Will vary between +V z , and -Vz]

---

~

10

20

II

J,

Vz ; 15V

I

Vz ; 25V

30

40

50

60

70

80

TlME!1sec

Figure 68. Output Waveform For Circuit of Fig. 6A.

Outputbetwetn+Vzilndground

Figure 4. Methods of Restricting Output Voltage Swing.

switching transistor such as the 2N2369. Figure 5
shows the NH0001 used as a comparator with a
diode clamp on pin 10.

Input Offset Voltage Balancing
Although the offset voltage of the NH0001 is
quite low, it is possible that even lower values are
required. Figure 7 shows the recommended balancing technique.

tl&V
+V

OUTPUT

-15V

Figure 5A. NH 0001 As Comparator For Driving DTL or T2l,

AN10-2

Figure 7. Method of Balancing Input Offset Voltage.

Input Bias Current Compensation
Methods of compensation recommended in NS
Application Note AN-3 can all be successfully used
with the NHOOOl with the exception that all polarities are reversed and NPN bias transistors substituted for the PNP units. Transistor type 2N 2484
units are recommended, For optimum compensation over a wide temperature range, the method of
generating the emitter current of the compensating
transistor shown in Figure 4 and 6 of AN-3 should
be modified to be similar to the current source
used in the NHOOO1. Figure 8 shows the recommended circuit.

pins 1 to 5 in opposite directions, the short circuit
current will be reduced in both the positive and
negative direction.
Figure 9 shows the connections and F igu re 10
gives the typical short circuit currents available
both with and without the diode clamps.

Figure 9. Method of Reducing Output Short Circuit
Current.

OUTPUT

If this control is not adequate, external limiting as
shown in Figure 11 can be used to limit lOUT to
less than 1 mAo

-v

Figure 8. Method of Compensating for I nput Bias Current.

Referring to Figure 2, in the limiting mode, the
V BE of the conducting output transistors (09 or
Q 10) wi II add to the drop across R LIM to be equal
to the sum of the two forward drops of conducting diodes between pin 10 and the output. Thus
the output current will be limited to that value
which causes approximately one diode forward

I ncreasedOutput Swing
For lightly loaded outputs (RL 2:: 10K), the maximum negative output swing will exceed the positive swing by approximately a volt. If the maximum positive swing is required, it may be obtained
by 'connecting a low capacitance (C :s; 2 pF at zero
volts) diode between pins 1 and 5, with the cathode on pin 1. Table 1 shows the typical positive
and negative swing with RL = 100 Kn both with
and without the diode clamp.

1
POS1T1VE OUTPUT

1

~

r'"

~
10

o
-50

100

50

150

°c

Figure 10A. Short Circuit Output Current.
40

Supply Voltage

±5V

±10V

±15V

±20V

Typical Negative
Output

3.8

8.8

13.5

18.4

±15V

=

WITH LAMP

TEMPERATURE

TABLE 1 Maxim,um Output Swings vs Supply
Voltage

Vs

WITHOUT CLAMP

Vs

= ±15V

NEGAT1J OUTPUT

30

Typical Positive
Output without
Diode Clamp

2.7

7.6

12.2

17.0

Typical Positive
Output with
Diode Clamp

3.6

8.4

13.0

18.0

WITHOUT CLAMP

",-

TA

= 25°C

As explained in the following section, the inclusion of a diode from pin 1 to 5, in addition to
increasing the available positive output voltage,
will also reduce the maximum positive short circuit current.

-r--.

o~
0
-50

-

WITH1CLAMP

50
TEMPERATURE

150

100

°c

Figure 10B. Short Circuit Output Current.

drop across R LIM' I n addition, the diode current
which may be as high as 75/lA at 25°C will be
added to the output current.

Reducing the Short-Circuit Current
As mentioned above, a diode connected from
pin 1 to pin 5 will reduce the positive output short
circuit current. If the polarity of the diode is reversed, the negative short circuit current will be
similarly reduced. If 2 diodes are connected from

lOUT

Figure 11. Alternate Method of Limiting Output Short
Circuit Current.

AN10-3

Typical Performance of the NHOOOl Operational
Amplifier (V s ; ; ; ±15V, T;;;;; 25°C)
PARAMETER

Input Offset
Voltage

CONDITION

VALUE

Rs :::;5K

0.2 mV

Input Offset
Current

3 nA

Input Bias
Current

30 nA

Positive Supply
Current

80pA

Negative Supply
Current

55pA

Voltage Gain

RL = lOOK

60,000

Output Voltage

RL = lOOK

±12V

CMRR

Rs~5K

90 dB

PSRR

Rs :::;5K

96 dB

Temperature
Range

-55°C to 125°C

Temperature
Drift

4/J.V;oC

Supply Voltage
Range

±5V to ±20V

REFERENCE:

R. J. Widlar, "Drift Compensation Techniques for
Integrated DC Amplifiers" AN-3, National Semiconductor, April, 1968.

AN10-4

l>

:2
September 1968

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r-

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APPLICATION OF THE NH0002
CURRENT AMPLIFIER

l>

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INTRODUCTION

:2

The NH0002 Current Amplifier integrated building block provides a wide band unity gain amplifier capable of providing peak currents of up to
±200 mA into a 50 ohm load.
The circuit uses thick film technology to integrate
2 NPN and 2 PNP complementary matched silicon
transistors with 4 cermet resistors on a single
alumina ceramic substrate. A circuit schematic is
shown in Figure 1. The negative thermal feedback
provided by the close proximity of the components on a single substrate eliminates any thermal
runaway problem that could occur if this circuit
were constructed using discrete components.

V+

V+

1

2

o

"T1

-I

:I:
m

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:I:

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INPUT 8

o

4 OUTPUT

N

n

C

:xJ
:xJ

A typical circuit features a dynamic input impedance of 200 Kohms, an output impedance of
6 ohms, DC to 50 MHz bandwidth, and an output
voltage swing that approaches supply voltage. A
complete list of the guaranteed and typical values
for the electrical characteristics under the stated
conditions is given in Table 1. These features make
the NH0002 ideal for integration with an operational amplifier inside a closed loop configuration

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3:

6

'"'C

v-

v-

r-

FIGURE 1. Circuit Schematic

"T1

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TABLE 1. Electrical characteristics, specification applies for TA = 25°C with +12.0Von pins 1 and 2; -12.0V on pins 6 and 7.

PARAMETERS
Voltage Gain

CONDITIONS

MIN

TYP

.95

Rs = 10 kn, RL = 1.0 kn

MAX

UNITS

-

kn

10

n

V

.97

V 1N = 3.0 V pp , f = 1.0 kHz
T A = _55°C to 125°C
Input Impedance

180

200

-

6

RL = 1.0 kn, f = 1.0 kHz

±10

±11

-

Rs = 10 kn, RL = 1.0 kn

-

±40

±100

mV

±10

p.A

Rs = 200 kn, V 1N = 1.0 V rms ,
f = 1.0 kHz, RL = 1.0 kn

Output Impedance

V 1N = 1.0 V rms ' f = 1.0 kHz
R L = 50n, Rs = 10 kn

Output Voltage Swing
DC I nput Offset Voltage

T A = _55°C to 125°C
DC Input Offset Current

Rs = 10 kn, RL = 1.0 kn

-

±6.0

T A = _55°C to 125°C
Harmonic Distortion

V 1N = 5.0 V rms ' f = 1.0 kHz

-

Bandwidth

V 1N = 1.0 V rms , RL = 50n,
f = 1 MHz

30

Positive Supply Current

Rs =10kn,R L =lkn

-

Negative Supply Current

Rs = 10 kn, RL = 1 kn

-

-

%

-

MHz

+6.0

+10.0

mA

-6.0

-10.0

mA

0.1
50

AN13-1

to increase its current output. The symmetrical
class B output portion of the circu it also provides
a constant low output impedance for both the positive and negative slopes of output pulses.
CIRCUIT OPERATION
The majority of circuit applications will use
symmetrical power supplies, with equal positive
voltage being applied to pins 1 and 2, and equal
negative voltage applied to pins 6 and 7. The reason that pin 2 and pin 6 are not connected internally to pin 1 and pin 7, respectively, is to increase
the versatility of circuit operation by allowing a
decreased voltage to be applied to pins 2 and 6 to
minimize the power dissipation in 03 and 04. The
larger voltage applied to the input stage also provides increased current drive as required to the
output stage.
The operation of the circuit can be understood by
considering that the input pin 8 is at VIN' The
emitter of 01 will be approximately 0.6 volt more
positive than V IN at 25° C, and the converse is true
for 02. This 0.6 volt will provide a forward bias on
03 to cancel out· the 01 base to emitter drop
which in turn would provide VIN at the output if
all junctions, resistors, power supplies, etc., were
electrically identical. The greatest error is introduced because the forward drops ·in the baseemitter junctions for the NPN and PNP devices are
slightly different. For example, the V BE of the
NPN will be typically 0.6V and the V BE of the
PNP will be typically 0.64V under the same conditions of I c = 2.4 mA at V CE = 12.0V at 25° C.
These are the approximate input stage circuit conditions for 01 and Q2 for plus and minus 12V
supplies. Fortunately, this error in both input and
output offset voltage is almost always negligible
when it is used inside the closed loop of a high
gain operational amplifier.
A plot of input impedance vs frequency is shown
in Figure 2. I nspection of th is plot shows that the
input impedance can be closely approximated to
that of a simple first order linear network with a
45° phase lag at 0.6 MHz and a 90° phase lag at
approximately one decade higher in frequency.
This information is very useful for designers who
have to integrate circuits which have large source
INPUT IMPEDANCE (MAGNITUDE AND PHAS~

-100

rms. RL .. 50 ohms, Y." !12.0V
R."10Kohms.r A "'25°C

YIN'" O.3V

1

1000

~
~

z

VPHASE

100 r---.

CI

!

........ MAGNITUDE

10

f

t-

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A.

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0.1

0.2

~

-20

L
0.5

10

o

FREQUENCY (MHz)

FIGURE 2. Input Impedance vs Frequency

AN13-2

impedances over a wide frequency range. The output impedance of the amplifier is very low,
6 ohms typically, and in conjunction with a voltage bandwidth of approximately 50 MHz can be
considered to be insignificant for most applications for this type of device.
A plot of the voltage bandwidth is shown in Figure
3. I nspection of this plot shows that phase information as well as gain information was included to
assist users of this device. For example, at 10 MHz,
less than an 8° phase lag would be subtracted from
the phase margin of an operational amplifier when
it is integrated with th is device. The open loop
gain of the operational amplifier would be decreased by less than 10010 at 10 MHz and therefore
can be considered to be insign ificant for most applications.
-40

1.0

VOLTAGE GAIN

~

"'% 0.8

"

>

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::l

~ 0.6

z
:;;:

FREQUENCY RESPONSE
VIN =1.0V .ms. Rl
TA =25°C

0(

:;
0.2

./

,

./

2.0

5.0

CI

:3

/

-16 ""

PHASE _

-8

CI)

0(

it

I

~
1.0

~

)'r-

u

0.1

"if

=50 ohms. V. =!12.0V r - - -24 ~

~ 0.4
~

-32

o
10.0

20.0

50.0

100

FREQUENCY (MHz)

FIGURE 3. Frequency Response

APPLICATIONS
Figure 4 shows the N H0002 integrated with the
NH0005 to provide differential inputs and outputs. In order for this circuit to funtion properly,
a load must be floated between the outputs of the
two devices to provide a complete loop of feedback. A differential head on a scope across the
load presents a true waveform of the actual signal
being applied to it. If only one end of the load is
displayed, it will appear distorted because this information is being fed back negatively to the input
in order to cancel out the loop distortion of the
overall amplifier. With the compensation shown, a
20V peak to peak signal can be applied to a
100 ohm load to 80 KHz. The overall circuit is
approximately 33% efficient under these conditions. A derating factor and/or heat sink must be
used at higher temperatures, as shown by the
NH0002 and NH0005 data sheets.
Additional output power could also be obtained
by connecting another NH0002 to pin 9 of the
operational amplifier. The overall load distortion
under high circuit voltage gain configurations
would also be reduced using two NH0002's because the NH0002 is more linear than the simple
output circuits of these particular operational
amplifiers.

lOOK ± 1/4%
+12V

"'---I~ VOUT (1)
100

LOAD
....-

-12V

.....~ V OUT (2)

Diff. V OUT (V OUT (1) - VOUT (2»)

= 10

(V 1N (2)

- V 1N

(1»

lOOK ± 1/4%

FIGURE 4. Differential Input-Output Operational Amplifier Integration

A breadboard of this configuration was assembled
to empirically check the increase in offset voltage
due to the addition of the NH0002. The offset
v 0 I tage was measured with and without an
NH0002 inside the loop with a voltage gain of
100, at -55°C, 25°C and 125°C. The additional
offset voltage was less than 0.3% for all three temperature conditions even though the offset voltage
of the NH0002 is much higher than that of the
LH101. The high open loop gain of the LH101
divides out this source of circuit error. The integration of this device also allows higher closed loop
circuit gain without excessive cross-over distortion
than would be obtainable with the simple booster
amplifier shown in Figure 6.

Figure 5 shows the NH0002 integrated with the
LH101 in a booster follower configuration. The
configuration is stable without the requirement for
any external compensation; however, it would behoove the designer to be conservative and bypass
both the negative and positive power supplies with
at least a 0.01 J1f capacitor to cancel out any
power supply lead inductance. A 100 ohm
damping resistor, located right at the input of the
NH0002, might also be required between the operational amplifier and the booster amplifier. The
physical layout will determine the requirement for
this type of oscillation suppression. Current limiting can be added by incorporating series resistors
from pins 2 and 6 to their respective power supplies. The exact value would be a function of
power supply voltage and required operating temperature.

R2

Vs = ±5V TO ±15V

Rl
INPUT -","",,/v\~""''''

~4""''''''OUTPUT

" , - - o V OUT

V-

FIGURE 5. LH101-NH0002 Booster Amplifier Integration

FIGURE 6. Simple Booster Amplifier

AN13-3

Figure 7 shows the NH0002 being used as a level
shifter with a high pass filter on the input in order
to reference the output to zero quiescent volts.
The purpose of the 10 Kohm resistor is to provide
current bias to the circuit's input transistors to
reduce the output offset voltage. Figure 3, Input
Impedance vs Frequency, provides a useful design
aid in order to determine the value of the capacitor for the particular application. The 10 Kohm
resistor, of course, has to be considered as being in
parallel with the circuit's input impedance.
For a pulse input signal, the output impedance of
the circu it remains low for both the positive and
negative portions of the output pulse. This circuit
provides both fast rise and fall times for pulse
signals, even with capacitive loading. The NH0002
data sheet shows typical rise and fall times for
both positive and negative pulses into a 50 ohm
load.

PU LSE-TRANSFO RMER

FIGURE 8. Driver for a Pulse-Transformer

The N H0002 can also be used to drive long transmission lines. Figure 9 shows a circuit configuration to match the output impedance of the amplifier to the load and coaxial cable for proper line,
termination to minimize reflections. A capacitor
can be added to empirically adjust the time r,esponse of the waveform.

Select capacitor to adjust time response of pu lse.

~-""--4""'-O

V

OUT

50n CABLE

FIGURE 7. Level Shifter

FIGURE 9. Transmission Line Driver

Figure 8 shows the NH0002 being used to drive a
pulse-transformer. The low output offset voltage
allows the pulse transformer to be directly coupled
to the amplifier without using a coupling capacitor
to prevent saturation. The pulse transformer can be
used to change the amplitude and impedance level
of the pulse, the polarity of the pulses, or, with
the aid of a center-tapped winding, positive and
negative pulses simu Itaneously.

AN13-4

SUMMARY
The mu Ititude of different applications suggested
in this article shows the versatility of the NH0002.
The applications specially covered were for a differential input-output operational amplifier, booster amplifier, level shifter, driver for a pulsetransformer, and transmission line driver.

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August 1968

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A COMPLETE MONOLITHIC IF STRIP

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FOR AM/AGC APPLICATIONS

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INTRODUCTION
Intermediate-frequency ampl ifiers in superheterodyne receivers and signal-frequency amplifiers in
T.R.F. receivers have traditionally been partitioned into a number of discrete power-gain stages,
with interstage networks performing both DC
decoupling and bandpass shaping functions. As
long as the active components (vacuum tubes or
transistors) comprised a substantial part of the
"strip's" total cost, it made sense to design on a
"cost-per-stage" basis.
.

Economics dictated the simplest detector schemes,
usually a single diode, biased from a tuned transformer secondary. AGC voltage was usually
obtained directly from the diode detector. Generally, because of large tuned gain and, often, marginal stability in the conventional common-emitter
stage, power-supply decoupling was required for
each stage.

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Suppose, howeve,r, that the above requirements are
largely eliminated by availability of almost unlimited monolithic ·complexity and inherent internal biasing. It would be much more efficient to
put all power gain in a single, lumped stage, preceded by a single (perhaps multisection, for selectivity) bandpass filter. This would considerably
reduce the assembly and alignment labor in an AM
receiver. Rather than deal with the sizeable problems of AGe in direct-coupled, high-gain amplifiers, a simp ler approach is to achieve full gaincontrol range through a high-performance variable
attenuator stage, between the input bandpass filter
and the input to the lumped gain stage, leaving the
lumped gain stage at its maximum gain at all times.
Finally, an AM detector is desirable which can be
directly coupled to the gain stage output, which is
insensitive to DC biasing, and which reliably provides a DC AGC voltage compatible with the input
variable attenuator. A bloc;k diagram of. the new
subsystem appears in Figure 1.

A number of currently available microcircuits,
such as types LM 70.3 and LM 171, provided a
transitional opportunity for RF system designers
to use proven interstage network designs, substituting the self-contained, inherently stable, high
gain-bandwidth product microcircuit directly for a
conventional common-emitter I F stage. While the
excellent FM . limiting and AGC characteristics of
such monolithic stages have already proven themselves in commercial and entertainment equipment, they have usually constituted performance,
rather than cost, advantages to the system manufacturer.
Monolithic technology has already emerged, in the
digital area, from an initial period of novelty and a
subsequent period of superior performance, into
the current realization that, against MSI or LSI,
discrete transistor computing systems cannot be
competitive. The linear circuit to be described, a
multifunction I F strip, is a step in the same direction, in which a number of discrete circuit functions have been combined, replacing not only the
active elements and DC biasing components, but
eliminating many of the peripheral IF elements as
well.

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A SYSTEM APPROACH

Monolithic techniques allow a rethinking of traditional IF strip partitioning. Previously, the
most efficient utilization of available power gain
was obtained by matched, tuned, interstage networks. Because of the limited AGC range obtainable by varying DC emitter current in a conventional common-emitter I F stage, several stages
received AGC voltage from the detector at once.
This dictated combersome DC biasing to obtain
the desired AGC characteristic, and made an input
and an output transformer mandatory for each
stage, to decouple DC-operating point shifts due to
AGC operation.

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AUDIO
OUT

C4

T

C5

C3

Cl

IN~

FIGURE 1. LM172 Block Diagram

AN15-1

A PRACTICAL MONOLITH
A complete schematic for National Semiconductor's AM I F Strip, the LM 172/272, appears in
Figure 2. All capacitors shown are external to
the 8 pin, T05 package; these capacitors establish
the minimal amount of decoupling and time constants required to operate such a complex, high
gain-bandwidth product microcircuit.

Examining first the AGCsection, Figure 3, it may
be seen that an emitter-coupled pair is used as a
series-shunt variable attenuator. The base of 02 is
held at a DC voltage of two forward diode drops,
2 V be, by emitter foilowerQ1 and R1, with only
AC signals coupled through an input capacitor. If
V AGC is held below 3 V be , 03 will becompletely
off, and 02 behaves as an ordinary emitter

follower, with R2 as load. When V AGe equals 3 V be,
02 and 03 form a balanced differential pair, conducting equal emitter currents from "current
source" R2, and as V AGC increases, 03 turns
increasingly on, with 02· turning off. As this
occurs, the effective emitter resistance' of 02
increases, in series with the input signal, while the
emitter resistance of 03 decreases, shunting across
the signal. Thus, 02 and 03 form a series-shunt
attenuator, with minimum attenuation of 0 dB.
Since the base of 02 remains at a fixed bias, while
that of 03 increases with AGC, the DC output
voltage at the common emitter point rises slightly
as gain is decreased. Consequently, a decoupling
capacitor is needed between the AGC stage and
the lumped-gain stage, to prevent unbiasing the
gain stage with AGC variations.

Vee

R5
2DK

07

06

05

04

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GNO

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R4
5DK

C4

FIGURE 2. LM172 AGe AM IF Strip

AN15:"'2

AGC
TIME

~CONSTANT

GAIN
STAGE
IN

pin numbers appear in circles

r - - - -...- -.........- ...... +vcc
4V bo

2V be

R9
6.8K

Rl
3K

Rl0
6.8K

RF--1
IN -)

Cl

~

RF IN

r--1

C2

C3

C2

FIGURE 3. AGe Section

FIGURE 4. Lumped Gain Stage

The lumped-gain stage, Figure 4, is basically a cascade of three common-emitter amplifiers, directcoupled. A conventional, discrete transistor version of this cascade would require much more
complex, less-efficient DC biasing. Notice that no
emitter resistors are used; this gives maximum voltage gain per stage, but still allows reliable biasing,
since an overall DC feedback loop, R8, C3, 05 and
R6, automatically sets the DC output voltage of
each transistor to exactly the right level to correctly bias the following transistor. The feedback
loop is effective only for DC; because of the
R8-C3 rolloff; thus maximum AC gain is always
attained with DC stability. Notice that the. collectors of 06 and 07 are operated at V be, to satisfy
biasing of following stages; thus, they operate with
zero volts collector to base, and still exhibit excellent current gain and gain-bandwidth product, by
virtue of their very small geometries and lowsaturation voltages. The three collector-load resistances, R9, R10 and R11, are biased from their
own emitter-follower voltage regulators, which
eliminate supply decoupling problems, and allow
the active part of the circuit to operate with constant bias conditions, regardless of power-supply
voltage. Since each part of the circuit is supplyregulated in this way, supply current does not
increase linearly with supply Voltage, as in most
designs, but remains relatively constant. Thus, the
circuit remains highly efficient at low-supply voltages, without excessive drain at higher voltages.

A number of improvements may be made over the
conventional AM diode detector. Unless simple
diodes are slightly forward-biased by additional
circuitry, they will not respond to small-input sig~
nals, because of the voltage required to overcome
forward V be' Moreover, diode detectors are inefficient, generally giving less audio output than is
available from· the modulated carrier. A more
nearly ideal detector, Figure 5, is one found in
most operational amplifier handbooks. If gain of
the operational ampl ifier is sufficiently high, audio
output exactly follows modulation envelope; since
the diode is inside a feedback loop, the operational
amplifier. will automatically bias the diode to
respond to sma II signals. When no carrier is present, DC output voltage is zero. An unmodulated
carrier causes DC output voltage to rise to one-half
the peak-to-peak RF level. Superimposing audio
modulation on the carrier has no effect on the
average, or DC output voltage, but causes the RC
network to "foHow" the modulation envelope
on the positive side of the carrier.

A simple modification to the active detector of
Figure 5 is the addition of a resistive divider,
Fig u re 6. While basic operation remains unchanged, the active detector now has an audio and
DC voltage gain equal to (R 1 + R2)/R2. Such a
detector can perform some of the audio preamplification necessary in the radio receiver.

AN15-3

...,-.-... -~-.,..-.-.....,...---------------------------------------,,.....,..,

- -........- - -. .- - +Vcc

FIGURE 5. Unity Gain Active Dector

OUT

RFIND--.....

FIGURE 6 ..Active Detector with Voltage Gain

FIGUR.E 7. Active Detector

The actual active detector used in the LM 172 is a
differential amplifier, Figure 7, with an emitter
follower performi ng the fu nction of the feedback
diode. While not an operational amplifier, the
circuit's voltage gain of about 40 dB is sufficient
to provide excell~nt detection. Because an emitter
follower was substituted for the diode, output
impedance is low; it WOUld, in fact, be too low for
effective carrier ripple filtering by C5, if it were
not for the addition of R 16. A resistive divider,
R 14 and R 15, give the detector an audio voltage
gain of 3, with D8 and D9 compensating for the
DC voltage (2 V be ) superimposed on the RF ihput
voltage by the preceding lumped gain stage. 013
acts as a supply regulator for the differential
amplifier.
The entire circuit fits on a small 33 x 33.5 mil
monolithic chip (Figure 8), and in view of the
self-contained feedback loops, which automatically compensate for component parameter variations, is an unusually reproducible microcircuit.

'~

FIGURE 8. Chip Photo

__
..____. -.,,--,-_ _ _ _ _-.,.-_ _ _ _ _ _ _ _--...,._ _ _ _ _ _ _ _ _ _ ___,_-----_-_-..,..--,....,---,..--J

AN 15-A

LM172 APPLICATIONS

SUPERHETERODYNE RECEIVER IF STRIP

By far the most popular receiver configuration, in
military, two-way-radio and entertainment use, is
one in which the incoming signal is amplified, and
then translated, via a mixer, to a standard intermediate frequency, where most of the receiver's
voltage gain and selectivity is achieved. A typical
system appears in Figure 9. Conventional circuitry
may be used ahead of the LM 172; although a
double-section 455 kHz ceramic filter is shown,
LC filtering may be used if desired. The circuit
works effectively for I F frequencies between
50 kHz and 2 MHz, depending on input bandpass
components. Capacitors C2, C3 andC5 should be
scaled proportionately at frequencies other than
455 kHz.

The circuit of Figure 9 exhibits the following IF
characteristics:
AGC Range (referred to Pin 2) from 50 pV to
50 mV: 60 dB
Audio output for 80% modulated carrier, within AGC range: 0.8V p-p

Total Supply drain into LM 172, Vee == +6V:
1.4 rnA, or 8.4 mW.
Improved selectivity may be obtained by substituting another ceramic filter between Pins 1 and 3,
instead of C2. The 3K impedances at Pins 1, 2
and 3 are especially suited to the inexpensive
Murata filters. While audio distortion occurs for
voltages at Pin 2 much above 100 mV rms. distortion is low for signals within the AGC range of the
circuit. Gain in the RF amplifier and mixer must
therefore be chosen to provide signals less than
100 mV into Pin 2 for the desired range of RF
input levels. Additional AGC is possible by using
the DC voltage appearing at Pin 7 to control the
gain of the input RF amplifier. Since AGC action
occurs at and above 3 V be' the National LM 171
RF/IF Amplifier, operated as a cascode, is ideally
suited to such front-end control, as its gain-control
voltage region coincides with that of the LM 172.
Because of the built-in supply regulation, the strip
operates with supply voltage varying from +6 to
+15 volts with no perceptible changes in receiver
performance.

-~.....- - -. .- - - - - - - - - - . . . . , Vee

MURATA
SF455D

CERAMIC
FILTER

FIGURE 9. Superheterodyne Block Diagram

AN15-5

LOW FREQUENCY T.R.F. RECEIVER
Because the LM 172 is a broadband functional
module, it may be used to amplify and detect signals below 2 MHz directly, without the more complex frequency conversion of superheterodyne
receivers. In the AM Broadcast Band
(550-1650 kHz), the strip has sufficient sensitivity
to operate alone in urban reception areas, since
AGe action is useful down to about 50 microvolts
at Pin 2. With additional gain either preceding the
module, or inserted between Pins 1 and 3, it may
also be useful in monitoring Loran (1.8-2.0 MHz),
or the numerous directional and informational
channels below 550 kHz.
While the complete T.R.F. (Tuned Radio Frequency) broadcast receiver of F igu re 10 has relatively poor selectivity, because only a single, low
"Q" tuned circuit is used in the entire receiver, it
serves to illustrate the straightforward design possible in T.R.F. construction. More sophisticated
designs might use multisection tuning, ahead of
the strip. The prototype was constructed using
very inexpensive imported "transistor-radio" components.

A ferrite "Ioopstick" antenna, L 1, resonates with a
small, polyethylene dielectric tuning capacitor
within the broadcast band. The LM 172 performs
its gain function just as it would in an I F application, but in this case, directly drives a class A
power amplifier. Since the De output voltage at
Pin 6 is relatively constant (from 2.1 to about
2.4 volts as a function of AGe), it is used to bias
the class A stage directly, eliminating a number of
components. C7 and C8 are needed to prevent
regenerative audio oscillations with weak batteries.
Total receiver drain from the 9-volt supply is
10 mA, of which only 1.9 mA is used in the
LM172; the rest is needed for the audio amplifier.

A volume control was not provided in the proto-,
type, as volume was excellent with the small (2"
diameter) speaker used, and AGC was so effective
that no perceptible difference in stations was
heard. Volume control is possible by inserting a
potentiometer between the emitter of .the audio
output transistor and R 1.

+9V BATTERY

FERRITE
LOOPSTICK
L1

5

C4
C3 ~ 1.01lf
~O.1Ilf~ 3V

L1
C9
T1
SPKR

-

Ferrite Loopstick - Phil more FF15 (packaged as set of 3 sizes)
SU,b·miniature variable capacitor - Philmore 1949G - 365 pF mal(.
Midget Audio Transformer, 1000n:Sn - Archer ..13·13SO (Radio Shack, Inc.)
Z" PM Speaker, sn, 0.1 watt - Phil more TSZO

FIGURE 10. T.R.F. Broadcast Receiver

AN15-6

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February 1969

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AN APPLICATIONS GUIDE FOR
OPERATIONAL AMPLI FI ERS

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INTRODUCTION
The general utility of the operational amplifier is
derived from the fact that it is intended for use in
a feedback loop whose feedback properties determine the feed-forward characteristics of the amplifier· and loop combination. To suit it for this
usage, the idea! operational amplifier would have
infinite input impedance, zero output impedance,
infinite gain and an open-loop 3 dB point at
infinite frequency rolling off at 6 dB per octave.
Unfortunately, the unit cost-in quantity-would
also be infinite.
Intensive development of the operational amplifier, particularly in integrated form, has yielded
circuits which are quite good engineering approximations of the ideal for finite cost. Quantity prices.
for the best contemporary integrated amplifiers
are low compared with transistor prices of five
years ago. The low cost and high quality of these
amplifiers allows the implementation of equipment and systems functions impractical with
discrete components. An example is the low frequency function generator which. may use 15 to
20 operational amplifiers in generation, wave
shaping, triggering and phase-locking.
The availability of the low-cost integrated amplifier makes it mandatory that systems and equipments engineers be familiar with operational
amplifier applications. This paper will present'
amplifier usages ranging from the simple unity-gain
buffer to relatively complex generator and waveshaping circuits. The general theory of operational
amplifiers is not within the scope of this paper and
many excellent references are available in the
I iterature. 1,2,3,4 The approach will be shaded
toward the practical, amplifier parameters will be
discussed as they affect circuit performance, and
application restrictions will be outlined.
The applications discussed will be arranged in
order of increasing complexity in five categories:
simple amplifiers, operational circuits, transducer
amplifiers, wave shapers and generators, and power
supplies. The integrated amplifiers shown in the
figures are for the most part internally com pen-

sated so frequency stabilization components are
not shown; however, other ampl ifiers may be used
to achieve greater operating speed in many circuits
as will be shown in the text. Amplifier parameter
definitions are contained in Appendix I.

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THE INVERTING AMPLIFIER

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The basic operational amplifier circuit is shown in
Figure 1. This circuit gives closed"loop gain of
R2/R 1 when this ratio is small compared with the
amplifier open-loop gain and, as the name implies,
is an inverting circuit. The input impedance is
equal to R 1. The closed-loop bandwidth is equal
to th~ unity-gain frequency divided by one plus
the closed-loop gain.
The only cautions to be .observed are that R3
should be chosen to be equal to the parallel combination of R1 and R2 to minimize the offset voltage error due to bias current and that there will be
an offset voltage at the amplifier output equal to
closed-loop gain times the offset voltage at the
amplifier input.

R2

"'''''''
"' ......

R3 = Rtll R2
FOR MINIMUM ERROR OUE
TO INPUT BIAS CURRENT

FIGURE 1. Inverting Amplifier

Offset voltage at the input of an operational amplifier is comprised of two components, these components are identified in specifying the amplifier
as input offset voltage a-nd input bias current.
The input offset voltage is fixed for a particular
amplifier, however the contribution due to input

AN20-1

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bias current is dependent on the circuit configuration used; For minimum offset voltage at the
amplifier input without circuit adjustment the
source resistance for both inputs should be equal.
In this case the maximum offset voltage would be
the algebraic sum of amplifier offset voltage and
the voltage drop across the source resistance due
to offset current. Amplifier offset voltage is the
predominant error term for low source resistances
and offset current causes the main error for high
source resistances.

I n high source resistance applications, offset voltage at the ampl ifier output may be adjusted by
adjusting the value of H3 and using the variation in
voltage drop across it as an input offset voltage
trim.
Offset voltage at the amplifier output is not as
important in AC coupled applications. Here the
only consideration is that any offset voltage at the
output reduces the peak to peak linear. output
swing of the amplifier.
The gain-frequency characteristic of the amplifier
and its feedback network must be such that oscillation does not occur. To meet this condition, the
phase shift through amplifier' and feedback
0
network must never exceed 180 for any frequency where the gain of the amplifier and its
feedback network is greater than unity. In
practical applications, the phase shift should not
0
approach 180 since this is the situation of conditional stability. Obviously the most critical case
occurs when the attenuation of the feedback network is zero.
Amplifiers which are not internally compensated
may be used to achieve increased performance in
circuits where feedback network attenuation is
high. As an example, the LM 101 may be operated
at unity gain in the inverting amplifier circuit with
a 15 pF compensating capacitor, since the feedback
network has an attenuation of 6 dB, while it
requires 30 pF in the non-inverting unity gain connection where the feedback network has zero
attenuation. Since amplifier slew rate is dependent
on compensation, the LM 101 slew rate in the
inverting unity gain connection will be twice that
for the non-inverting connection and the inverting
gain of ten connection will yield eleven times the
slew rate of the non-inverting unity gain connection. The compensation trade-off for a particular
connection is stability versus bandwidth, larger
values of compensation capacitor yield greater
stability and lower bandwidth and vice versa.
The preceding discussion of offset voltage, bias
current and stability. is applicable to most amplifier applications and will be referenced in later
sections. A more complete treatment is contained
iii Reference 4.

THE NON-INVERTING AMPLIFIER
Figure 2 shows a high .input impedance noninverting circuit. This circuit gives a closed-loop
gain equal to the ratio of the sum of R1 andR2 to
Rl and a closed-loop 3 dB bandwidth equal to the
amplifier unity-gain frequency divided by the
closed-loop gain.
The primary differences between\this connection
and the inverting circuit are that t~ output is not
inverted and that the input impedance is very high
and is equal to the differential input impedance
multiplied by loop gain. (Open loop gain/Closed
loop gain.) In DC coupled applications, input
impedance is not as important as input current and
its voltage drop across the source resistance.
Applications cautions are the same for this amplifier as for the inverting amplifier with one
exception. The amplifier output will go into saturation if the input is allowed to float. This may be
important if the amplifier must be switched from
source to source. The compensation trade off discussed for the inverting ampl ifier is also valid for
this connection.

Your

R2

Your = RIR+1 R2 VIN
RIll R2 = RsouRcE
FOR MINIMUM ERROR DUE
TO INPUT BIAS CURRENT

FIGURE 2. Non-Inverting Amplifier

THE UNITY-GAIN BUFFER
The unity-gain buffer is shown in Figure 3. The
circuit gives the highest input impedance of any
operational amplifier circuit. Input impedance is
equal to the differential input imr;edance multiplied by the open-loop gain, in parallel with common mode .input impedance. The gain error of this
circuit is equal to the reciprocal of the amplifier
open-loop gain or to the common mode rejection,
wh ichever is less.
'

VOUT

Your = VIN
Rl =RsouRcE
FOR MINIMUM ERROR DUE
TO INPUT BIAS CURRENT

FIGURE3. Unity Gain B\.Iffer

Input impedance is a misleading concept in a DC
coupled unity-gain buffer. Bias current for the
amplifier will be supplied by the source resistance
and will cause an error at the amplifier input due
to its voltage drop across the source resistance.
Since this is the case, a low bias current amplifier
such as the LH 1026 should be chosen as a unitygain buffer when working from high source resistances. Bias current compensation techniques are
discussed in Reference 5.

is shown in Figure 5 and is useful as a compu,tationa I amplifier, in making a differential to singleended conversion or in rejecting a common mode
signal.

Rl
VOUT
R3

The cautions to be observed in applying this circuit are three: the amplifier must be compensated
for unity gain operation, the output swing of the
amplifier may be limited by the amplifier common
mode range, and some amplifiers exhibit a latch-up
mode when the a~plifier common mode range is
exceeded. The LH 1 01 may be used in this circuit
with none of these problems; or, for faster operation, the LM 102 may be chosen.

VI

Rl

R4

V2
112
V3
R3

VOUT

V1 V2 V3)
VouT.=-R4 ( ITI+iI2+R"3
R5 = Rl11R211R311R4
FOR MINIMUM OFFSET ERROR
DUE TO INPUT BIAS CURRENT

FIGURE 4. Summing Amplifier

SUMMING AMPLIFIER
The summing amplifier, a special case of the inverting amplifier, is shown in Figure 4. The circuit
gives an inverted output which is equal to the
weighted algebraic sum of all three inputs. The
gain of any input of this circuit is equal to the
ratio of the appropriate input resistor to the feedback·. resistor, R4. Amplifier bandwidth may be
calculated as in the inverting amplifier shown in
Figure lby assuming the input resistor to be the
para"el co~bination of Rl,R2, and R3. Application cautions are the same as for the inverting
amplifier. If an uncompensated amplifier is used,
compensation is calculated on the basis of this
bandwidth as is discussed in the section describing
the simple inverting amplifier.
The advantage of this circuit is that there is no
interaction b~tween inputs and operations such as
summing and weighted averaging are implemented
very easi Iy.

R2
Rl +R2) R4
VOUT = ( R3 + R4 iff V2 -Ai V1
FOR Rl = R3 AND R2 = R4
VOUT = ~ (V 2 -V 1)

-

RlIIR2= R31iR4
FOR MINIMUM OFFSET ERROR
DUE TO INPUT BIAS CURRENT

FIGURE 5. Difference Amplifier

Circuit bandwidth may be calculated in the same
manner as for the inverting amplifier, but input
impedance is somewhat more complicated. Input
impedance for the two inputs is not necessarily
equal; inverting input impedance is the same as for
the inverting. amplifier of Figure 1 and the
non-inverting input impedance is the sum of 'R3
and R4. Gain for either input is the ratio of R lto
R2 for the special case of a differential input
single-ended output where R 1 = R3 and R2 = R4.
The general expression for gain is given in the
figure. Compensation should be chosen on the
basis of amplifier bandwidth.
Care must be exercised in applying this circuit
since input impedances are not equal for minimum
bias current error.
01 FFERENTIATOR

The differentiator is shown in Figure 6 and; as the
name implies, is usedto perform the mathematical
operation of differentiation .. The form shown. is
not the practical form, it is a true differeritiator
and is extremely susceptible to high frequency
noise since AC gain increases at the rate of 6 dB per
octave. In addition, the feedback network of the
differentiator, R2C1, is an RC low pass filter
which contributes 90° phase shift to the loop and
may cause stability problems even with an ampiifier which is compensated for unity g~in.

VIN~

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~"-VOUT

THE DIFFERENCE AMPLIFIER

VOUT = -R1Cl!t (V 1N )
Rl = R2

The difference amplifier is the complement of the
summing amplifier and allows the subtraction of
two voltages or, as a special case, the cancellation
of a signal common to the two inputs. This circuit

-

FOR MINIMUM OFFSET ERROR
DUE TO INPUT BIAS CURRENT

FIGURE 6. Differentiator

AN20-3

C2

circuit is essentially a low-pass filter with a frequency response decreasing at 6 dB per octave. An
amplitude-frequency plot is shown in Figure 10.
60 __--~--~----T---~

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VIN-VV~
40~--~---+----+---~

Cl
Ie

=2rr ~2Cl

~

'h

11
=2rr R1Cl =2rr R2C2

;;:

'e

«Ih «

z

20

~--_+_--~,-----+---~

t:I

'uni',v gain

FIGURE 7. Practical Differentiator

A practical differentiator is, shown in Figure 7.
Here both the stability and noise problems are corrected by addition ,of two additional components,
Rl and C2. R2 and C2 form a 6 dB per octave
high frequency roll-off in the feedback network
and R1C1 form a 6 dB per octave roll-off network
in the input network for a total high frequency
roll-off of 12 dB per octave to reduce the effect of
high frequency input ar:ld amplifier noise. I n addition R1C1 and R2C2 form lead networks in the
feedback loop which, if placed below the amplifier
unity gain frequency, provide 90° phase lead to
0
compensate the 90 phase lag of R2C1 and prevent loop instability. A gain frequency plot is
shown in Figure 8 for clarity.
60.------..------------,

-20 L-__-J-__--L_ _ _ _~_ _....::.
101
100'
1000'
100001
RElATIVE FREQUENCY

FIGURE 10. Integrator Frequency Response

The circuit must be provided with an external
method of establishing initial conditions., This is
shown in the figure as $1. When $1 is in
position 1, the amplifier is connected in unity-gain
and capacitor C1 is discharged, setting an initial
condition of zero volts. When $1 is in position 2,
the amplifier is connected as an integrator and its
output will change in accordance with a constant
times the time integral of the input voltage.
The cautions to be observed with this circuit are
two: the amplifier used should generally be
stabilized for unity-gain operation and R2 must
equal R 1 for minimum error due to bias current.

40~--_+_--~----~--~

...z
CD

;;:

SIMPLE LOW-PASS FILTER

20 I-----l------..I..::---'"Ir-

c:I

101
IDOl
10001
RELATIVE FREQUENCY

The simple low-pass filter is shown in, Figure 11.
This circuit has a 6 dB !Jer octave roll-off after a,
closed-loop 3 dB point defined by f c . Gain below
this corner frequency is defined by the ratio of R3
to R 1. The circuit may be considered as an AC
integrator at frequencies well above f c; however,
the time domain response is that of a single RC
rather than an integral.

100001

FIGURE 8. Differentiator Frequency Response

INTEGRATOR
The integrator is shown in Figure 9 and performs
the mathematical operation of integration. This
~------..,

I

I

I

S1b

Rl

I

_ _ _ _--VOUT

I
I

I

I
VIN--U2

IL = 2rr ~ICl

I

t

Ie = 2rr ~3Cl
V OUT

'I

rl2

VOUT = -R1Cl J,

VIN

dl

AL=~
FIGURE 11. Simple Low Pass Filter

1,

Ie

=

2rr

~ICl

Rl = R2
FOR MINIMUM OFFSET ERROR
DUE TO INPUT BIAS CURRENT

FIGURE 9. Integrator

AN20-4

R2 should be chosen equal to the parallel combination of R1 and R3 to minimize errors due to
bias current. The amplifier should be compensated
for unity-gain or an ir:lternally compensated amplifier can be used.

-

60

ICELL

~=100
40

Rl

PCl

~
z

:;;:

20

VOUT

(:>

-20 '--_...I.-_--'-_ _J.-_~
1001
10001
100001
101

FIGURE 14. Amplifier for Photoconductive Cell

RElATIVE FREOUENCY

FIGURE 12. Low Pass Filter Response

PHOTOCELL AMPLI FI ERS
A gain frequency plot of circuit response is shown
in Figure 12 to illustrate the difference between
this circuit and the true integrator.

Amplifiers for photoconductive, photodiode· and
photovoltaic cells are shown in Figures 14, 15, and
16 respectively.

THE CURRENT-TO-VOL TAGE CONVERTER
Current may be measured in two ways with an
operational ampl ifier. The current may be converted into a voltage with a resistor and then
amplified or the current may be injected directly
into a summing node. Converting into voltage is
undesirable for two reasons: first, an impedance is
inserted into the me"asuring line causing an error;
second, amplifier offset voltage is also amplified
with a subsequent loss of accuracy. The use of a
current-to~voltage transducer avoids both of these
problems.
The current-to-voltage transducer is shown in Figure 13. The input current is fed directly into the
summing node and the amplifier output voltage
changes to extract the same current from the summing node through R1. The scale factor of this

All photogenerators display some voltage dependence of both speed and linearity. It is obvious that
the current through a photoconductive cell will
not display strict proportionality to incident light
if the cell terminal voltage is allowed to vary with
cell conductance. Somewhat less obvious is the
fact that photodiode leakage and photovoltaic cell
internal losses are also functions of terminal voltage. The current-to-voltage converter neatly sidesteps gross linearity problems by fixing a constant
terminal voltage, "zero .in the case of photovoltaic
cells and a fixed bias voltage in the case of photoconductors or photodiodes.

Rl

01

VOUT

Rl
V-

VOUT = R110
V OUT

FIGURE 15. Phot()diode Amplifier

FIGURE 13. Current to Voltage Converter

circuit is R 1 volts per amp. The only conversion
error in this circuit is I bias which is summed
algebraically with 'IN.
This basic circuit is useful for many applications
other than current measurement. It is shown as a
photocell amplifier in the following section.

Photodetector speed is optimized by operating
into a fixed low load impedance. Currently available photovoltaic detectors show response times in
the microsecond range at zero load impedance and
photoconductors, even th.ough sloW, are materially
faster at low load resistances.
Rl

ICELL . . ~_ _--VOUT

The only design constraints are that scale factors
must be chosen to minimize errors due to bias
current and since voltage gain and source impedance are often indeterminate (as with photocells)
the amplifier must be compensated for unity-gain
operation. Valuable techniques for bias current
compensation are contained in Reference 5.

FIGURE 16. Photovoltaic Cell Amplifier

A 1\1 20-5

The feedback resistance, R 1, is dependent on cell
sensitivity and should be chosen for either maximum dynamic range or for a desired scale factor.
R2 is elective: in the case of photovoltaic cells or
of photodiodes, it is not required in the case of
photoconductive cells, it should be chosen to
minimize bias current· error over the operating
range.

where the output current is highand the base current of the Darlington input would not cause a
significant error.
The amplifiers used must be compensated for
unity-gain and additional compensation may be
required depending' on lacid reactance and external
transistor parameters.
. 01

PRECISION CURRENT SOURCE

lN4611
6.6V

The precision .current source is shown in Figures 17 and 18. The configurations shown will sink
or source conventional current respectively.
>-----4...-V OU T

FIGURE 19a. Positive Voltage Reference

ADJUSTABLE VOLTAGE REFERENCES

FIGURE 17. Precision Current Sink

Caution must be exercised in applying these
circuits. The voltage compliance of the source extends' from BV CE R of the external transistor to
approximately 1 volt more negative than V 1N • The
compliance of the current sink is the same in the
positive direction.
The impedance of these current generators· is
essentially infinite for small currents and they are
accurate so long as V 1N is much greater than Vos
and
is much greater than I bias'

Adjustable voltage reference circuits are shown in
Figures 19 and 20. The two circuits shown have
d ifferen t areas of applicability. The basic
difference between the two is that Figure 19 illustrates a voltage source which provides a voltage
greater than the refere~ce diode while Figure 20
illustrates a voltage source which provides a voltage lower than the reference diode. The figures
show both positive and negative voltage sources.
01

lN4611
6.6V

'0

The source and sink illustrated in Figures 17 and
18 use an FET to drive a bipolar output transistor.
It is possible to use a Darlington connection in
place of the FET-bipolar. combination in cases
Rl

FIGURE 1.9b. Negative Voltage Reference

FIGURE 18. Precision Current Source

AN20-6

High precision extended temperature applications
of the circuit of Figure 19 require that the range
of adjustment of V OUT be restricted. When this is
done, Rl may be chosen to provide optimum
zener. current for minimum zener T.C. Since I z is
not a function of V+, reference T.C. will be independent of V+.

Rl
lOOK

VIN~

rt~Sl
O.l/-1 F

2

01
lN4611
6.6V

C2

O.l/-1F~

FIGURE 20a. Positive Voltage Reference
FIGURE-21. Reset Stabilized Amplifier

01
lN4611
6.6V

VOUT

FIGURE 20b. Negative Voltage Reference

The circuit of Figure 20 is suited for high precision
extended temperature service if V+ is reasonably
constant since I z is dependent on V+. R 1, R 2, R3,
and R4 are chosen to provide the proper I z for
minimum T.C. and to minimize errors due to I bias .
The circuits shown should both be compensated
for unity-gain operation or, if large capacitive
loads are expected, should be overcompensated.
Output noise may be reduced in both circuits by
bypassing the,amplifier input.
The circuits shown employ a single power supply,
this requires that common mode range be considered in choosing an amplifier for these applications. If the common mode range requirements are
in excess of the capability of the amplifier, two
power supplies may be used. The LH 101 may be
used with a single power supply since the common
mode range is from V+ to within approximately
2 volts of V-.

THE RESET STABILIZED AMPLIFIER
The reset stabilized amplifier is a form of
chopper-stabilized amplifier and is shown in Figu re 21. As shown, the amplifier is operated
closed-loop with a gain of one.

The connection is useful in eliminating errors due
to offset voltage and bias current. The output of
this circuit is a pulse whose amplitude is equal to
VIN. Operation may be understood by considering
the two conditions corresponding to the position
of S1. When S1 is in position 2, the ampl ifier is
connected in the unity gain connection and the
voltage at the output will be equal to the sum of
the input offset voltage and the drop across R2
due to input bias current. The voltage at the inverting input will be equal to input offset voltage.
Capacitor C1 will charge to the sum of input offset
voltage and VIN through R 1. When C1 is charged,
no current flows through the source resistance and
R 1 so there is no error due to input resistance. S1
is then changed to position 1. The voltage stored
on C1 is inserted between the output and inverting
input of the amplifier and the output of the amplifier changes by VIN to maintain the amplifier input
at the input offset voltage. The output then
changes from (Vas + I bias R2) to VIN + I bias R2) as
S1 is changed from position 2 to position 1.
Amplifier bias current is supplied through R2 from
the output of the amplifier or from C2 when S1 is
in position 2 and position 1 respectively. R3 serves
tc reduce the offset at the amplifier output if the
amplifier must have maximum linear range or if it
is desired to DC couple the amplifier.
An additional advantage of this connection is that
input resistance approaches infinity as the
capacitor C1 approaches full charge, eliminating
errors due to loading of the source resistance. The
time spent in position 2 should be long with
respect to the changing time of C1 for maximum
accuracy.
The amplifier used must be compensated for unity
gain operation and it may be necessary to overcompensate because of the phase shift across R2
due to C1 and the amplifier input capacity. Since
this connection is usually used at very low switching speeds, slew rate is not normally a practical
consideration and overcompensation does not
reduce accuracy.

AN20-7

R5

VOUT

R5

=

Rl

(¥ff)

v, >0

v,

FIGURE 22. Analog Multiplier

THE ANALOG MULTIPLIER
A simple embodiment of the analog multiplier is
shown in Figure 22. This circuit circumvents many
of the problems associated with the log-antilog circuit and provides three quadrant analog multiplication which is relatively temperature insensitive and
which is not subject to the bias current errors
which plague most multipliers.
Circuit operation may be understood by considering A2 as a controlled gain amplifier, amplifying
V 2 , whose gain is dependent on the ratio of the
resistance of PC2 to R5 and by considering A 1 as a
control amplifier which establishes the resistance
of PC2 as a function of V l ' I n this way it is seen
that V OUT is a function of both V 1 and V 2 •

A1, the control amplifier, provides drive for the
lamp, L 1, When an input voltage, V 1, is present,
L 1 is driven by A 1 until the current to the summing junction from the negative supply through
PC1 is equal to the current to the summing junction from V 1 through R 1. Since the negative
supply voltage is fixed, this forces the resistance of
PC 1 to a value proportional to R 1 and to the ratio
of V 1 to V-. L 1 also illuminated PC2 and, if the
photoconductors are matched, causes PC2 to have
a resistance equal to PC1.
A2, the controlled gain amplifier, acts as an inverting amplifier whose gain is equal to the ratio of the
resistance of PC2 to R5. If R5 is chosen equal to
the product of R 1 and V-, then V0 UT becomes
simply the product of V 1 and V 2' R 5 may be
scaled in powers of ten to provide any required
output scale factor.
PC1 and PC2 should be matched for best tracking
over temperature since the T.C. of resistance is
related to resistance match for cells of the same
geometry. Small mismatches may be compensated
by varying the value of R5 as a scale factor adjustment. The photoconductive cells shou Id receive
equal illumination from L 1, a convenient method

AN20-8

is to mount the cells in holes in an aluminum
block and to mount the lamp midway between
them. This mounting method provides controlled
spacing and also provides a thermal bridge between
the two cells to reduce differences in cell temperature. This technique maybe extended to the use
of FET's or other devices to meet special resistance or environment requirements.
The circuit as shown gives an inverting output
whose magnitude is equal to one-tenth the product
of the two analog inputs. Input V 1 is restricted to
positive values, but V 2 may assume both positive
and negative values. This circuit is restricted to low
frequency operation by the lamp time constant.
R2 and R4 are chosen to minimize errors due to
input offset current as outlined in the section
describing the photocell amplifier. R3 is included
to reduce in-rush;eu,rrent when first turning on the
lamp, L1.

THE .FULL-WAVEHECTIFIER
AND AVERAGING FU.:TER
The circuit shown in Figure 23 is the heart of an
average reading, rms calibrated AC voltmeter. As
shown, it is a rectifier and averaging filter. Deletion of C2 removes the averaging function and provides a precision full-wave rectifier, and deletion of
C1 provides an absolute value generator.
Circuit operation may be understood by following
the signal path for negative and then for positive
inputs. For negative signals, the output of amplifier A 1 is clamped to +0.7V by D 1 and disconnected from the summing point of A2 by D2. A2
then functions as a simple unity-gain inverter with
input resistor, R1, and feedback resistor, R2,
giving a positive going output.
For positive inputs, A 1 operates as a normal amplifier cO,nnected to the A2 summing point through
resistor, R5. Amplifier A 1 then acts as a simple
unity-gain inverter with input resistor, R3, and

R1
20K
1%

C1

AC
INPUT

--1H
4.7 pF

+

RJ
20K
1%

R2
20K
1%

DC
OUTPUT

R4
20K
1%

CAL

R5
10K
1%

4.7 pF

2.5K

C2
4.7 pF

R6
10K

FIGURE 23. Full-Wave Rectifier and Averaging Filter

feedback resistor, R5. A 1 gain accuracy is not
affected by D2 since it is inside the feedback loop.
Positive current enters the A2 summing point
through resistor, R 1, and negative current is drawn
from the A2 summing point through resistor, R5.
Since the voltages across R 1 and R5 are equal and
opposite, and R5 is one-half the value of R 1, the
net input current at the A2 summing point is equal
to and opposite from the current through R 1 and
amplifier A2 operates as a summing inverter with
unity gain, again giving a positive output.
The circuit becomes an averaging filter when C2 is
connected across R2. Operation of A2 then is
similar to the Simple Low Pass Filter previously
described. The time constant R2C2 should be
chosen to be much larger than the maximum
p~riod of the input voltage which is to be averaged.
Capacitor C1 may be deleted if the circuit is to be
used as an absolute value generator. When this is
done, the circuit output will be the positive
absolute value of the input voltage.

The Wien Bridge oscillator is widely used and takes
advantage of the fact that the phase of the voltage
across the parallel branch of a series and a parallel
RC network connected in series, is the same as the
phase of the applied voltage across the two networks at one particular frequency and that the
phase lags with increasing frequency and leads
with decreasing frequency. When this networkthe Wi en Bridge-is used as a positive feedback element around an amplifier, oscillation occurs at the
frequency at which the phase shift is zero. Additional negative feedback is provided to set loop
gain to unity at the oscillation frequency. To
stabilize the frequency of oscillation, and to
reduce harmonic distortion.
C2
0.068 pF

VOUT = 16.5 Vpp
10 Hz

The amplifiers chosen must be compensated for
unity-gain operation and R6 and R7 must be
chosen to minimize output errors due to input offset current.
SINE WAVE OSCILLATOR

An amplitude-stabilized sine-wave oscillator is
shown in Figure 24. This circuit provides high
purity sine-wave output down to low frequencies
with minimum circuit complexity. An important
advantage of this circuit is that the traditional
tungsten filament lamp amplitude regulator is
eliminated along with its time constant and
linearity problems.
In addition, the reliability problems associated
with a lamp are eliminated.

FIGURE 24. Wien Bridge Sine Wave Oscillator

The circuit presented here differs from the classic
usage only in the form of the negative feedback
stabilization scheme. Circuit operation is as
follows: negative peaks in excess of -8.25V cause
01 and 02 to conduct, charging C4. The charge

AN20-9

stored in C4 provides bias to Q1, which determines
amplifier gain. C3 is a low frequency roll-off
capacitor in the feedback network and prevents
offset voltage and offset current errors from being
multiplied by amplifier gain.
Distortion is determined by amplifier open-loop
gain and by the response time of the negative feedback loop filter, R5 and C4. A trade-off is necessary in determining amplitude stabilization time
constant and oscillator distortion. R4 is chosen to
adjust the negative feedback loop so that the FET
is operated at a small negative gate bias. The circuit shown provides optimum val~es for a generalpurpose oscillator.
TRIANGLE-WAVE GENERATOR

A constant ampl itude triangu lar-wave generator is
shown in Figure 25. This circuit provides a variable
frequency triangular wave whose amplitude is independent of frequency.
INTEGRATOR
Cl
G.lIlF

RI

R2

10K

1M
R5
B.2K

FIGURE 25. Triangular-Wave Generator

The generator embodies an integrator as a ramp
generator and a threshold detector with hysterisis
as a reset circuit. The integrator has been described
in a previous section and requires no further
explanation. The threshold detector is similar to a
Schmitt Trigger in that it is a latch circuit with a
large dead zone. This function is implemented by
using positive feedback around an operational
amplifier. When the amplifier output is in either
the positive or negative saturated state, the positive feedback network provides a voltage at the
non-inverting input which is determined by the
attenuation of the feed-back loop and the saturation voltage of the amplifier. To cause the amplifier to change states, the voltage at the input of
the amplifier must be caused to change polarity by
an amount in excess of the amplifier input offset
voltage. When this is done the amplifier saturates
in the opposite direction and remains in that state
until the voltage at its input again reverses. The
complete circuit operation may be understood by
examining the operation with the output of the
threshold detector in the positive state. The
detector positive saturation voltage is applied to
the integrator summing junction through the combination R~nd R4 causing a current 1+ to flow.

AN20-10

The integrator then generates a negative-going
ramp with a rate of 1+/C1 volts per second until its
output equals the negative trip point of the thresh 0 Id detector. The threshold detector then
changes to the negative output state and supplies a
negative current, 1-, at the integrator summing
point. The integrator now generates a positivegoing ramp with a rate of 1-/C1 volts per second
until its output equals the positive trip point of
the threshold detector where the detector again
changes output state and the cycle repeats.
Triangular-wave frequency is determined by R3,
R4 and C1 and the positive and negative saturation
voltages of the amplifier A 1. Amplitude is determined by the ratio of R5 to the combination of
R 1 and R2 and the threshold detector saturation
voltages. Positive and negative ramp rates are equal
and positive and negative peaks are equal if the
detector has equal positive and negative saturation
voltages. The output waveform may be offset with
respect to ground if the inverting input of the
threshold detector, A 1, is offset with respect to
ground.
The generator may be made independent of
temperature and supply voltage if the detector is
clamped with matched zener diodes as shown in
Figure 26.
The integrator should be compensated for unitygain and the detector may be compensated if
power supply impedance causes oscillation during
its transition time. The current into the integrator
should be large with respect to I bias for maximum
symmetry, and offset voltage should be small with
respect to VOUT peak.

(MATCHED ZENERS)

~-f\l\j~-_"" TO INTEGRATOR INPUT

R6
10K

AMP

Rl

R2

10K

1M

R5
8.2K

FROM INTEGRATOR
OUTPUT

FIGURE 26. Threshold Detector with Regulated Output

TRACKING REGULATED POWER SUPPLY

A tracking regulated power supply is shown in Figure 27. This supply is very suitable for powering
an operational amplifier system since positive and
negative voltages track, eliminating common mode
signals originating in the supply voltage. I n addition, only one voltage reference and a minimum
number of passive components are required.

+40V UNREGULATED

PROGRAMMABLE BENCH POWER SUPPLY

The complete power supply shown in Figure 28 is
a programmable positive and negative power
supply. The regulator section of the supply comprises two voltage followers whose input is provided by the voltage drop across a reference
resistor of a precision current source.

T1
TRIAD 90X

01
lN4001

':::'':':':'''-1I~''''''''---<'''--I~ +41V

~~"'--"'----41""--"'~"""-~

P.S.C.

T

300 pF
R7
39K

a.

C2
50 l'F
50V

>------......

~-VOUT (REG)

+41V
OUTPUT VOL TAGE IS VARIABLE
FROM ~5V TO ±35V.
NEGATIVE OUTPUT TRACKS
POSITIVE OUTPUT TO WITHIN
THE RATIO OF R6 TO R7.

FIGURE 27. Tracking Power Supply

Power supply operation may be understood by
considering first the positive regulator. The positive regulator compares the voltage at the wiper of
R4 to the voltage reference, D2. The difference
between these two voltages is the input voltage for
the amplifier and since R3, R4, and R5 form a
negative feedback loop, the amplifier output voltage changes in such a way as to minimize' this
difference. The voltage reference current is
supplied from the amplifier output to increase
power supply line regulation. This allows the regulator to operate from supplies with large ripple
voltages. Regulating the reference current in this
way requires a separate source of current for
supply start-up. Resistor R 1 and diode D1 provide
this start-up current. D1 decouples the reference
string from the amplifier output during start-up
and R 1 supplies the start-up current from the unregulated positive supply. After start-up, the low
amplifier output impedance reduces reference current variations due to the current through R 1.

03
lN759
12V

___

.- 01

JiO~~'OO.A

2N2605

R6

C3
300 pF

b.

-41 V

Rll
UK
1%
05
lN759
12V

]

TRIM
FOR
IC4 =1.00 rnA

03
2N2484

The negative regulator is simply a unity-gain inverter with input resistor, R6, and feedback
resistor, R7.
The amplifiers must be compensated for unity-gain
operation.
The power supply may be modulated by injecting
current into the wiper of R4. In this case, the
output voltage variations will be equal and
opposite at the positive and negative outputs. The
power supply voltage may be controlled by replacing D 1, D2, R 1 and R2 with a variable voltage
reference.

c.

FIGURE 28. Low-Power Supply for Integrated
Circuit Testing

AN20-11

Programming sensitivity of the positive and negative supply is 1 V /1
of resistors R6 and R 12
respectively. The output voltage of the positive
regulator may be varied from approximately +2V
to +38V with respect to ground and the negative
regulator output voltage may be varied from -38V
to OV with respect to ground. Since LH10l amplifiers are used, the supplies are inherently short circuit proof. This current limiting feature also serves
to protect a test circuit if this supply is used in
integrated circuit testing.

ooon

I nternally compensated amplifiers may be used in
this application if the expected capacitive loading
is small. If large capacitive loads are expected, an

externally compensated amplifier should be us~d
and the amplifier should be overcompensated for
additional stability. Power supply noise may be
reduced by bypassing the amplifier inputs to
ground with capacitors in the 0.1 to 1.0 fJ.F range.

CONCLUSIONS
The foregoing circuits are illustrative of the versatility of the integrated operational amplifier and
provide a guide to a number of useful applications.
The cautions noted in each section will show the
more common pitfalls encountered in amplifier
usage.

APPENDIX I
DEFINITION OF TERMS
Input Offset Voltage: That voltage which must be
applied between the input terminals through two
equal resistances to obtain zero output voltage.

Power Supply Rejection: The ratio of the change
in input offset voltage to the change in power
supply voltage producing it.

Input Offset Current: The difference in the currents into the two input terminals when the output is at zero.

Slew Rate: The internally-limited rate of change
in output voltage with a large-amplitude step function applied to the input.

Input Bias Current: The average of the two input
currents.
Input Voltage Range: The range of voltages on
the input terminals for which the amplifier
operates within specifications.
Common Mode Rejection Ratio: The ratio of the
input voltage range to the peak-to-peak change in
input offset voltage over this range.
Input Resistance: The ratio of the change in input
voltage to the change in input current on either
input with the other gounded.
Supply Current: The current required from the
power supply to operate the ampl ifier with no
load and the output at zero.
Output Voltage Swing: The peak output voltage
swing, referred to zero, that can be obtained
without clipping.
Large-Signal Voltage Gain: The ratio of the output voltage swing to the change in input voltage
required to drive the output from zero to this voltage.

AN20-12

REFERENCES
1. D.C. Amplifier Stabilized for Zero and Gain;
Williams, Tapley, and Clark; AI EE Transactions, Vol. 67,1948.
2. Active Network Synthesis; K. L. Su, McGrawHill Book Co., Inc., New York, New York.
3. Analog Computation; A. S. Jackson, McGrawHill Book Co., Inc., New York, New York.
4. A Palimpsest on the Electronic Analog Art;
H. M. Paynter, Editor. Published by George A.
Philbrick Researches, Inc., Boston, Mass.
5. Drift Compensation Techniques for Integrated
D.C. Amplifiers; R. J. Widlar, EON, June 10,
1968.
6. A Fast Integrated Voltage Follower With Low
Input Current; R. J. Widlar, Microelectronics,
Vol. 1 No.7, June 1968.

l>

:2
December 1968

I

N

~

C

m

en
C)

:2

en

DESIGNS FOR NEGATIVE
VOLTAGE REGULATORS

o"jJ
:2
m
C)

l>

-I

<
m

<
or-I

l>

C)

m
INTRODUCTION

jJ

m

C)

C
A number of IC voltage regulators have been
introduced to date, but these have been designed
primarily to regulate positive voltages. Most can be
adapted as negative regulators, at some sacrifice in
complexity, performance and flexibility. This
note, however, describes an IC, which is designed
specifically as a negative regulator. It is intended
to complement the LM 100 and LM 105 positive
regulators, providing a line of IC's for practically
every regulator application.

r------------

-- .. -

I

ADJ

R

I
I
I
I

Rl
15K

I

~:K

~
I

+

In the circuits described, emphasis is placed on
practical considerations for the design of reliable
regulators. Many of the pitfalls which cause unexpected failures are explained, and protection
schemes for many of the hazards facing regu lators
are given. Most of the design hints are sufficiently
general to apply equally to other IC's or even regulators designed entirely with discrete components.

-I

o

I

..J.- Cl

~4.7"F

B

jJ

en

I
I
I

--t-

OUTPUT

I
I

7_{Q3

I

I

I

Unique features of the circuit are that it supplies
any output voltage from OV down to -40V, while
operating from a single unregulated supply. The
output voltage is proportional to a single programming resistor, and remote sensing can be done
at the load. It also regulates within 0.01 % in circuits using a separate, floating bias supply, where
the maximum output voltage is limited only by
the breakdown of external pass transistors. The
device is designed for either linear or switching
regulator applications.

GROUND

I

I

I
I

rl>

9

I
6_ _ oJI

5

- - - - INPUT

A functional diagram of the LM104 regulator and
external circuitry (dash line) is shown in the figure.
The internal reference is a temperature compensated current source, I ref. A voltage which is
proportional to an external programming resistor,
Radj , is fed into an error amplifier, A 1. This drives
an internal series pass transistor, 01, to supply an
output voltage equal to twice the voltage across
the programming resistor. External pass transistors
can be added, as is 03, to increase the outputcurrent capabil ity. Short-circuit protection makes
the circuit exhibit a constant-current characteristic
when 02 is turned on by the voltage drop across
an external current-limit resistor, Rlim . A more
complete description of the integrated circuit itself
is given in the back of the text.

AN21-1

LOW POWER REGULATOR
OR BIAS SUPPLY

This circuit can provide output voltages between
OV and -40V at currents up to 25 mAo The output
voltage is linearly dependent on the value of R2,
giving approximately 2V for each 1 KSl of resistance. The exact scale factor can be set up by
trimming R1. This should be done at the maximum output voltage setting in order to compensate for any mismatch in the internal divider
resistors of the integrated circuit.
Short-circuit protection is provided by R3. The
value of this resistor should be chosen so that the
voltage drop across it is 300 mV at the maximum
load current. This insures worst-case operation up
to full load over a -55°C to 125°C temperature
range. With a lower maximum operating temperature,the design value for this voltage can be increased linearly to 525 mV at 25°C.
For an output voltage setting of 15V, the regulation, no load to full load, is better than 0.05%; and
the line regulation is better than 0.2% for a ±20%
input voltage variation. Noise and ripple can be
greatly reduced by bypassing R2 with a 10 J1F
capacitor. This will keep the ripple on the output
less than 0.5 mV for a 1V, 120 Hz ripple on the
unregulated input. The capacitor also improves the
line-transient response by a factor of five.

AN21-2

An output capacitor of at least 1 J1F is required to
keep the regulator from oscillating. This should be
a low inductance capacitor, preferably solid
tantalum, installed with short leads. It is not
usually necessary to bypass the input, but at least
a 0.01 J1F bypass is advisable when there are long
leads connecting the circuit to the unregulated
power source.

r--......- -...- -

GND

J-.....- - VOUT=~

Rl*
2.4K
1%
tSolidTlntllum

-

....- - -. .-0000004....- - -

VIN

*Trim R1 for exact
alef.ctor

It is important to watch power dissipation in the
integrated circuit even with load currents of
25 mA or less. The dissipation can be in excess of
1W with large input-output voltage differentials,
and this is above ratings for the device.

INCREASED OUTPUT CURRENT

When output currents above 25 mA are requ ired
or when the dissipation in the series pass transistor
can' be higher than about 0.2W, under worst-case
conditions, it is advisable to add an external transistor to the LM 104 to handle the power. The connection of an, external booster transistor is shown
here. The output current capability of the regulator is increased by the current gain of the added
PNP transistor, but it is still necessary to watch
dissipation in the external pass transistor. Excessive dissipation can burn out both the series pass
transistor and the integrated circuit.
r - - -....- -....-

r-....-

GND

VOUT = -15V
lOUT

S 200 mA

transistor will be 300 mA; and the dissipation in it
will be 7.5W. This clearly establishes the need for
an efficient heat sink.
For lower-power operation, a 2N2905 with a clip
on heat sink can be used for the external pass
transistor. However; when the worst case dissipation is above 0.5W, it is advisable to employ a
power device such as the 2N3740 with a good heat
sink.
The current limit resistor is chosen .so that the
voltage drop across it is 300 mV, with maximum
load current, for operation to 125°C. With lower
maximum ambients this voltage drop could be
increased by 2.2 mV tC. If possible, a fast-acting
fuse rated about 25% higher than the maximum
load current should be included in series with the
unregulated input.

tSolidT..talum

' - - - - - - - 4.....- _ - - -

V1NS -IIV

For example, with the circuit shown, the worstcase input voltage can be 25V. With a shorted output at 125°C, the current through the pass

When a booster transistor is used, the minimum
input-output voltage differential of the regulator
will be in~reased by the emitter-base voltage of the
added transistor. This establishes the minimum
differential at 2 to 3V, depending on the base
drive required by the external transistor.

AN21-3

HIGH CURRENT REGULATOR

When output currents in the ampere range are
needed, it is necessary to add a second booster
transistor to the LM104 circuitry. This connection
is shown in the accompanying figure. The output
current capability of the LM 104 is increased by
the product of the current gains of 01 and 02.
However, it is still necessary to watch the dissipation in both the series pass transistor, 02, and its
driver, 01. A clip-on heat sink is definitely
required for 01, and it is advisable to replace the
2N2905 with a 2N3740 which has a good heatsink when output currents greater than 1A are
needed. A 1000 pF capacitor should also be added
between Pins 4 and 5 to compensate for the
poorer frequency response of the 2N3740. The
need for an efficient heat sink on 02 should be
obvious.
Experience shows that a single-diffused transistor
such as a 2N3055 (or a 2N3772 for higher currents) is preferred over a double diffused, highfrequency transistor for the series pass element.
The slower; single-diffused devices are less prone
to secondary breakdown and oscillations in linear
regulator applications.
As with the lower-current regulators, C1 is
required to frequency compensate the regulator
and prevent oscillations. It is also advisable to
bypass the input with C2 if the regulator is located
any distance from the output filter of the unregulated supply. The resistor across the emitter base
junction of 02 fixes the minimum collector current of 01 to minimize oscillation problems with
light loads. It is still possible to experience oscillations with certain physical layouts, but these can
almost always be eliminated by stringing a ferrite
bead, such as a Ferroxcube K5-001-00/38, on the
emitter lead of 02.
The use of two booster transistors does not
appreciably increase the minimum input-output
voltage differential over that for a single transistor.
The minimum differential will be 2 to 3V, depending on the drive current required from the integrated circuit.
With high current regulators, remote sensing is
sometimes required to eliminate the effect of line

AN21-4

resistance between the regulator and the load. This
can be accomplished by returning R2 and Pin 9 of
the LM 104 to the ground end of the load and
connecting Pin 8 directly to the high end of the
load.
The low resistance values required for the current
limit resistor, R3, are sometimes not readily available. A suitable resistor can be made using a piece
of resistance wire or even a short length of kovar
lead wire from a standard TO-5 transistor.
The current limit sense voltage can be reduced to
about 400 mV by inserting a germanium diode (or
a diode-connected germanium transistor) in series
with Pin 6 of the LM 104. This diode wi II also compensate the sense voltage and make the short circu it cu rrent essential I y independent of
temperature.

,....---....- - 4......- - - - 4......-

GND

R2
5K
1%

) -..............-4.....-

You> = -10V
IOUT< lA

Rl
2.4K
1%

tSolidTln.. lum

' - -. . . ._ __

112
2NJ055

Rl
O.l

'---_e_-----

VIN5:-12V

With high current regulators it is especially important to use a low-inductance capacitor on the output. The lead length on this capacitor must also be
made short. Otherwise, the capacitor leads can
resonate with smaller bypass capacitors (like
0.1 J.lF ceramic) which may be connected to the
output. These resonances can lead to oscillations.
With short leads on the output capacitor, the 0 of
the tuned circuit can be made low enough so that
it cannot cause trouble.

FOLDBACK CURRENT LIMITING
High current regulators dissipate a considerable
amount of power in the series pass transistor under
full-load conditions. When the output is shorted,
this dissipation can easily increase by a factor of
four. Hence, with normal current limiting, the heat
sink must be designed to handle much more power
than the worst case full load dissipation if the circuit is to survive short-circuit conditions. This can
increase the bulk of the regulator substantially.

~-----e----~----~'---------~-GND

Rl
2.4K
1%

tion of the full load current, minimizing dissipation in the pass transistor.
The circuit shown here accomplishes just this.
Normally 03 is held in a non-conducting state by
the voltage developed across R4. However, when
the voltage across the current limit resistor, R7,
increases to where it equals the voltage across R4
(about 1V), 03 turns on and begins to rob base
drive from the driver transistor, 01. This ca.uses an
increase in the output current of the LM 104, and
it will go into current limiting at a current determined by R5., Since the base drive to Q1 is'
clamped, the output voltage will drop with heavier
loads. This reduces the voltage drop across R4 and,
therefore, the available output current. With the
output completely shorted, the current will be
about one-fifth the full-load current.
I n design, R7 is chosen so that the voltage drop
across it will be 1 to 2V under full load conditions.
The resistance of R3 should be one-thousand times
the output voltage. R4 is then determined from

~....- - - - - - - - - - -.....- -....-

V'NS-15V

tSolidTantalum

This situation can be eased considerably by using
foldback current limiting. With this method of current limiting, the available output current actually
decreases as the maximum load on the regulator is
exceeded and the output voltage falls off. The
short-circuit current can be adjusted to be a frac-

where
occur.

IFL

is the load current at which limiting will

If it is desired to reduce the ratio of full load to
short circuit current, this can be done by connecting a resistance of 2 to 10 Kn across the emitterbase of 03.

AN21-5

SYMMETRICAL POWER SUPPLIES

In many applications, such as powering operational amplifiers, there is a need for symmetrical
positive an'd negative supply voltages. A circuit
which is a particularly-economical solution to this
design problem is shown in the adjoining figure. It
uses a minimum number of components, and the
voltage at both outputs can be set up within ±1.5%
by a single adjustment. Further, the output voltages will tend to ~rack with temperature and variations on the unregulated supply.
The positive voltage is regulated by an LM 105,
while an LM104 regulates the negative supply. The
unusual feature is that the two regulators are interconnected by R3. This not only eliminates one
precision resistor, but the reference current of the
LM 104 stabi Iizes the LM 105 so that a ± 10% variation in its reference voltage is only seen as a ±3%
change i.n output voltage. This means that in many
cases the output voltage of both regulators can be
set up with sufficient accuracy by trimming a
single resistor, R 1.

RS

~---4I~O~.7SI\,-_ _ _ _ _ _ _" '_ _' " VouT ="SV
IOUT~200

R2

Il.2K
Cl

1%

47pF
Q2

2NJ740

Rl'
2.4K
R4
I.S

1%

tSolid TO.hllum
·Trimto.toutputs

The line regulation and temperature drift of the
circuit is determined primarily by the LM 104, so
both output voltages will tend to track. Output
ripple can be reduced by about a factor of five to
less than 2 m V IV by bypassi ng Pi n 1 of the

AN21-6

V, .S-IIV . .-

. .- -. . .-~......

of bOlh ",uIaIO"

LM 104 to ground with a 10 fJ.F capacitor. A
center-tapped transformer with a bridge rectifier
can be used for the unregulated power source.

mA

ADJUSTABLE CURRENT LIMITING

I n laboratory power su pplies, it is often necessary
to adjust the limiting current of a regulator. This,
of course, can be done by using a variable resistance for the current limit resistor. However, the
current-limit resistor can easily have a value below
that of commercially-available potentiometers.
Discrete resistance values can be switched to vary
the limiting current, but this does not provide
continuously-variable adjustment .

.----....- -....- -....-

GNO

C2
lhF

..........- - - - - 4 t - -

VIN

The circuit shown here solves this problem, giving
a linear adjustment of limiting current over a
five-to-one range. A silicon diode, 01, is included
to reduce the current limit sense voltage to
approximately 50 mY. Approximately 1.3 mA
from the reference supply is passed·:through a
potentiometer, R4, to buck out the diode voltage.
Therefore, the effective current limit sense voltage
is nearly proportional to the resistance of R4. The
current through R4 is fairly insensitive to changes
in ambient temperature, and 01 compensates for
temperature variations in the current limit sense
voltage of the LM 104. Therefore, the limiting current will not be greatly affected by temperature.

IMPROVING LINE REGULATION

The line regulation for voltage variations on the
reference supply terminal of the LM 104 is about
five times worse than it is for changes on the
unregulated input. Therefore, a zener-diode preregulator can be used on the reference supply to
improve line regulation. This is shown in the fig~
ure.

.---....------e----...-----e---GNO
01
lN964

13V

Rl

UK
1%

It is important that a potentiometer be used for
R4 and connected as shown. If a rheostat connection were used, it could open while it was being
adjusted and momentarily increase the current
limit sense voltage to many times its normal value.
This could destroy the series pass transistors under
short-circuit conditions ..
The inclusion of R4' will soften the current
limiting characteristics of the LM 104 somewhat
because it acts as an emitter-degeneration resistor
for the current-limit transistor. This can be
avoided by reducing the value of R4 and developing the voltage across R4 with additional bleed
current to ground. .,

)---411~- VOUT : -15V

R4

tSohd Tlnglum

UK

.......--------e--....------ VINS,-lBV
The design of this circuit is fairly simple. It is only
necessary that the minimum current through R4
be greater than 2 mA with low input voltage.
Further, the zener voltage of 01 must be five volts
greater than one-half the maximum output voltage
to keep the transistors in the reference current
source from saturating.

AN21-7

USING PROTECTIVE DIODES

It is a little known fact that most voltage regulators can be damaged by shorting out the unregulated input voltage while the circuit is operatingeven though the output may have short-circuit
protection. When the input voltage to the regulator falls instantaneously to zero, the output
capacitor is still charged to the nominal output
voltage. This appl ies voltage of the wrong polarity
across the series pass transistor and other parts of
the regulator, and they try to discharge the output
capacitor into the short. The resulting current
surge can damage or destroy these parts.
When the LM 104 is used as the control element of
the regulator, the discharge path is through internal junctions forward biased by the· voltage
reversal. If the charge on the output capacitor is in
the order of 40 volt· I1F, the circuit can be
damaged during the discharge interval. However,
the problem is not only seen with integrated circuit regulators. It also happens with discrete regulators where the series-pass transistor usually gets
blown out.

Heavy loads operating from the unregulated
supply can also destroy a voltage regulator. When
the input power is switched off, the input voltage
can drop faster than the output voltage, causing a
voltage reversal across the regulator, especially
when the output of the regulator is lightly loaded.
Inductive loads such as a solenoid are particularly
troublesome in this respect. In addition to causing
a voltage reversal between the input and the output, they can reverse the input voltage causing
additional damage.
In cases like this, it is advisable to use a multiplepole switch or relay to disconnect the regulator
from the unregulated supply separate from the
other loads. If this cannot be done, it is necessary
to put a diode across the input of the regulator to
clamp any reverse voltages, in addition to the protective diode between the input and the output.
...-_ _...._ _...._ _ _ _. . ._ _-GNO

01

UTR3305

The problem can be eliminated by connecting a
diode between the output and the input such that
it discharges the output capacitor when the input
is shorted. The diode should be capableqf handling large current surges without excessive voltage
drop, but it does not have to be a power diode
since it does not carry current continuously. It
should also be relatively fast. Ordinary rectifier
diodes will not do because they look like an open
circuit in the forward direction until minority
carriers are injected into the intrinsic base region
of the PIN structu reo
This problem is not just caused by accidental
physical shorts on the input. It has shown up more
than once when regulators are driven from highfrequency dc-dc converters. Tantalum capacitors
are frequently used as output filters for the rectifiers. When these capacitors are operated near their
maximum voltage ratings with excessive high frequency ripple across them, they have a tendency
to sputter-that is, short momentarily and clear
themselves. When they short, they can blowout
the regulator; but they look innocent after the
smoke has cleared.
The solution to this problem is to use capacitors
with conservative voltage ratings, to observe the
maximum ripple ratings for the capacitor and to
include a protective diode between the input and
output of the regulator to protect it in case
sputtering does occur.

AN21-8

r--e--e-~'--VOUT

02
UTR3305

....--tlI-....- -...- - - - -...- V ON

-=

03
UTR3305

Yet another failure mode can occur if the regulated supply drives inductive loads. When power is
shut off, the inductive current can reverse the output voltage polarity, damaging the regulator and
the output capacitor. This can be cured with a
clamp diode on the output. Even without inductive loads it is usually good practice to include this
clamp diode to protect the regulator if its output
is accidentally shorted to a negative supply.
A regulator with all these protective diodes is
shown here. D1 protects against output voltage
reversal. D2 prevents a voltage reversal between
the input and the output of the regulator. And D3
prevents a reversal of the input-voltage polarity. In
many cases, D3 is not needed if D 1 and D2 are
used, since these diodes will clamp the .input voltage within two diode drops of ground. This is
adequate if the input voltage reversals are of short
duration.

HIGH VOLTAGE REGULATOR

In the design of commercial power supplies, it is
common practice to use a floating bias supply to
power the control circuitry of the regu lator. As
shown here, this connection can be used with the
LM 104 to regulate output voltages that are higher
than the ratings of the integrated circuit. Better
regulation can also be obtained because it is a
simple matter to preregulate the low current bias
supply so that the integrated circuit does not see
ripple or line voltage variations and because the
reduced operating voltage minimizes power dissipation and associated thermal effects from the
current del ivered to the booster transistor.

~_""_"'

_ _ _ _ _""'_GND

........-~t-----+------4t--....-

....-VOUT = ~

01

lN961
10V

UNREGULATED
BIAS
SUPPLY

R4
330

supply, and its breakdown voltage will determine
the maximum operating voltage of the complete
regulator.
The connection of the LM 104 is somewhat different than usual: the internal divider for the error
amplifier is shorted out by connecting Pins 8 and 9
together. This. makes the output voltage equal to
the voltage drop across the adjustment resistor,
R2, instead of twice this voltage as is normally the
case. C2 and C3 must also be added to prevent
oscillation. The value of C3 can be increased to
4.7 f.1F to reduce noise on the output.
It is necessary to add 02 and R5 to provide current limiting. When the output current becomes
high enough to turn on 02, there will be an abrupt
rise in the output current of the LM 104 as 02 tries
to remove base drive from the booster transistor .
Any further increases in load current will cause the
LM 104 to limit at a current determined by R3,
and the output voltage will collapse. The value of
R3 must be selected so that the integrated circuit
can deliver the base current of 01, at full load,
without limiting.

tSolidTantllum

The bias for the LM 104, which is normally
obtained from a separate winding on the main
power transformer, is preregulated by 01. R4 is
selected so that it can provide the 3 mA operating
current for the integrated circuit as well as the
base drive of the booster transistor, 01, with fu II
load and minimum line voltage. The booster
transistor regulates the voltage from the main

A second, NPN booster transistor can be used in a
compound connection with 01 to increase the
output current of the regulator. However, with
very-high-voltage regulators, the most economical
solution may be to use a high voltage PNP driving
a vacuum tube for the series pass element.
Remote sensing, which eliminates the effects of
voltage dropped in the leads connecting the regulator to the load, can be provided by connecting
R2 to the ground end of the load and Pins 8 and 9
to the high end of the load.

AN21-9

SWITCHING REGULATOR

Linear regulators have the advantages of fast
response to load transients as well as low noise .and
ripple. However, since they must dissipate the
difference between the unregulated·supply power
and the output power, they isometimes have a low
efficiency. This is not always a problem with ac
line-operated equipment bec~use the power loss is
easily afforded, because the input voltage is
already fairly-well regulated and because losses can
be minimized by adjustment of transformer ratios
in the power supply. In systems operating from a
fixed dc input voltage, the situation is often much
different. It might be necessary to regulate a 28V
input voltage down to 5V. In th is case, the power
loss can quickly become excessive. This is true
even if efficiency is not one of the more important
criteria, since high power dissipation calls for
expensive power transistors and elaborate heat
sinking methods.
Switching regulators can be used to greatly reduce
dissipation. Efficiencies approaching 90% can be
realized even though the regulated output voltage
is only a fraction of the input voltage. With proper
design, transient response and ripple can also be
made quite acceptable.
This circuit, which uses the LM 104 as a selfoscillating switching regulator, operates in much
the same way as a linear regulator. The reference
current is set up at 1 rnA with R 1, and R2 determines the output voltage in the normal fashion.
The circuit is made to oscillate by applying positive feedback through R5 .to the non-inverting
input on the error amplifier of the LM 104. When
the output voltage is low, the internal pass transistor of the integrated Circuit turns on and drives
01 into saturation. The current feedback through
R5 then increases the magnitude of the reference
voltage developed across R2. 01 will remain on
until the output voltage comes up to twice this
reference voltage. 'At this point, the error amplifier
goes into linear operation, and the positive feedback makes the circuit switch off. When this
happens, the reference voltage is lowered by feedback through R5, and the circuit will stay off until
the output voltage drops to where the error amplifier again goes into linear operation. Hence, the
circuit regulates with the output voltage oscillating
about the nominal value with a peak-to-peak ripple
of around 40 mV.
The power conversion from the input voltage to a
lower output voltage is obtained by the action of

AN21-10

the switch transistor, 01, the catch diode, 01, and
the LC filter. The inductor is made large enough so
that the current through it is essentially constant
throughout the switching cycle. When Q1 turns
on, the voltage on its collector will be nearly equal
to the unregulated input voltage. When. it turns
off, the magnetic field in L 1 begins to collapse,
driving the collector voltage of 01 to ground
where it is clamped by D1.
If, for example, the input voltage is 10V and the
switch transistor is driven at a 50% duty cycle, the
average voltage on the collector of 01 will be 5V.
This waveform will be filtered by L 1 and C1 and
appear as a 5V dc voltage on the output. Since the
inductor current comes from the input while 01 is
on but from ground through D1 while 01 is off,
the average value of the input current will be half
the output current. The power output will therefore equal the input power if switching losses are
neglected.
~--"'--"'--""~---4"""'-GNO

tSolid Tlnt.lum
-125 turns No. 22 on
Arnold Engineering
A262123·2
Molybdenum Perm.lloy Core

R1

UK
1%

01
UTX210

L...--e_ _ _ _ _..._ _ _---1It-_ _ V,N,,-lIV

In design, the value of R3 is chosen to provide
sufficient base drive to 01 at the maximum load
current. R4 must be low enough so that the bias
current coming out of Pin 5 of the LM104
(approximately 300 pA) does not turn on the
switch transistor. The purpose of C2 is to remove
transients that can appear across R 2 and cause
erratic switching. It should not be made so large
that it severely integrates the waveform fed back
to this point.
For additional information on switching regulators
see "Designing Switching Regulators," National
Semiconductor AN-2, August, 1968.

HIGH CURRENT SWITCHING REGULATOR

Output currents up to 3A can be obtained using
the switching regulator circuit shown here. The circuit is identical to the one described previously,
except that 02 has been added to increase the
output current capabil ity by about an order of
magnitude. It should be noted that the reference
supply terminal is returned to the base of 02,
rather than the unregulated input. This is done
because the LM104 will not function properly if
Pin 5 gets more than 2V more positive than Pin 3.
The reference current, as well as the bias currents
for Pins 3 and 5, is supplied from the unregulated
input through R5, so its resistance must be low
enough so that 02 is not turned on with about
2 mA flowing through it.
The line regulation of this circuit is worsened
somewhat by the unregulated input voltage being
fed back into the reference for the regulator
through R6. This effect can be eliminated by connecting a 0.01 f.1F capacitor in series with R6 to
remove the dc component of the feedback.
~----~'----4~-------4~----~----IGNO

C2
lDDpf

Al
2.4K
1%

} -....__.....,._ _ _ _ _~--_ VOUT : -5V
IOUT$3A

01
1Nl88D

tSolidT.nt.lum

-60 turns No. 20 on
Arnold Engmeering

A9lD151·2
Molybdenum
Pet'mliloy Core

L..-----. . .----V'N S -B.5V

There are a number of precautions that should be
observed with all switching regulators, although
they are more inclined to cause problems in highcurrent appl ications:
For one, fast switching diodes and transistors must
be used. If D1 is an ordinary junction rectifier,
voltages in the order of 10V can be developed
across it in the forward direction when the switch
transistor turns off. This happens because lowfrequency rectifiers are usually manufactured with
a PIN structure which presents a high forward
impedance until enough minority carriers are
injected into the diode base region to increase its
conductance. This not only causes excessive dis-

sipation in the diode, but the diode also presents a
short circuit to the switch transistor, when it first
turns on, until all the charge stored in the base
region of the diode is removed. Similarly, a high
frequency switch transistor must be used as excessive switching losses in low frequency transistors,
like the 2N3055, make them overheat.
It is important that the core material used for the
inductor have a. soft saturation characteristic.
Cores that saturate l'abruptly produce excessive
peak currents in the switch transistor if the output
current becomes high 'enough to run the core close
to saturation. Powdered molybdenum-permalloy
cores, on the other hand, exhibit a gradual reduction in permeability with excessive current, so the
only effect of output currents above the design
value is a gradual increase in switching frequency.
One thing that is frequently overlooked in the
design of switching circuits is the ripple rating of
the filter capacitors. Excessive high-frequency
ripple can cause these capacitors to fail. This is an
especially-important consideration for capacitors
used on the unregulated input as the ripple current
through them can be higher than the dc load current. The situation is eased somewhat for the filter
capacitor on the output of the regulator since the
ripple current is only a fraction of the load current. Nonetheless, proper design usually requires
that the voltage rating of this capacitor be higher
than that dictated by the dc voltage across it for
reliable operation.
One unusual problem that has been noted in working with switching regulators is excessive dissipation in the switch transistors caused by high
emitter-base saturation voltage. This can also show
up as erratic operation if 01 is the defective
device. This saturation voltage can be as high as 5V
and is the result of poor alloying on the base contact of the transistor. A defective transistor will
not usually show up on a curve tracer because the
low base current needed for linear operation does
not produce a large voltage drop across the
poorly-alloyed contact. However, a bad device can
be spotted by probing on the bases of the switch
transistors while the circuit is operating.
It is necessary that the catch diode, D1, and any
bypass capacitance on the unregulated input be
returned to ground separately from the other parts
of the circuit. These components carry large current transients and can develop appreciable voltage
transients across even a short length of wire. If C1,
C2, or R2 have any common ground impedance
with the catch diode or the input bypass capacitor,
the transients can appear directly on the output.

AN21-11

SWITCHING REGULATOR WITH
CURRENT LIMITING

The switching regulator circuits described previously are not protected from overloads or a
short-circuited output. The current limiting of the
LM 104 is used to IimitJhe base drive of the switch
transistor, but th is does not effectively protect the
switch transistor from excessive current. Providing
short circuit protection is no simple problem,
si nc e it is necessary to keep the regulator
operating in the switching mode when the output
is shorted. Otherwise, the dissipation in the switch
transistor will become excessive even though the
current is limited.
r----~....--4I~---....- -.....-GNO
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A resistor, R7, is included so that excessive base
current will not be driven into the base of 03. C4
insures that 03 does not turn on from the current
spikes through the switch transistor caused by
pulling the stored charge out of the catch diode
(these are about twice the load current). This capacitor also. operates in conjunction with C2 to
produce sufficient phase delay in the feedback
loop so that the circuit will oscillate in current
limiting. However, C4 should not be made so large
that it appreciably integrates the rectangular waveform of the current through the switch transistor.
As the output voltage falls below half the design
value, D1 pulls down the reference voltage across
R2. This permits the current limiting circuitry to
keep operating when the unregulated input voltage
drops below the design value of output voltage,
with a short on the output of the regulator.

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A circuit which provides current limiting and protects the regulator from short circuits is shown
here. The current through the switch transistor
produces a voltage drop across R9. When this volt-

AN21-12

age becomes large enough to turn on 03, current
limiting is initiated. This occurs because 03 takes
over as the control transistor and regulates the
voltage on Pin 8 of the LM 104. This point,which
is the feedback terminal of the error amplifier, is
separated from the actual output of the regulator
by not shorting the regulated output and booster
output terminals of the integrated circuit. Hence,
with excessive output current, the circu it still operates as a switching regulator with 03 regulating the
voltage fed back to the error amplifier as the output voltage fCllls off.

A transistor with good high-current capability was
chosen for 03 so that it does not suffer from
secondary breakdown effects from the large peak
currents (about 200 mA) through it. With a
shorted output, these peak currents occur with the
full input voltage across 03. The average dissipation in 03 is, however, low.

SWITCHING REGULATOR WITH
OVERLOAD SHUTOFF

An alternate method for protecting a switching
regulator from excessive output currents is shown
here. When the output current becomes too high,
the voltage drop across the current-sense resistor,
R8, fires an SCR which shuts off the regulator.
The regulator remains off, dissipating practically

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no power, until it is reset by removing the input
voltage.
In the actual circuit, complementary transistors,

03 and 04, replace the SCR since it is difficult to
find devices with a low enough holding current
(about 25 f.1A). When the voltage drop across R8
becomes large enough to turn on 04, this removes
the base drive for the output· transistors of the
LM 104 through Pin 4. When this happens 03
latches 04, holding the regulator off until the
input voltage is removed. It will then start when
power is applied if the overload has been removed.
With this circuit, it is necessary that the shutoff
current be 1.5 times the full load current. Otherwise, the circuit will shut off when it is switched
on with a full load because of the excess current
required to charge the output capacitor. The shutoff current can be made closer to the full load
current by connecting a 10 f.1F capacitor across R2
which will limit the charging current for C1 by
slowing the risetime of the output voltage when
the circuit is turned on. However, this capacitor
will also bypass the positive feedback from R6
which makes the regulator oscillate. Therefore, it
is necessary to put a 270[2 resistor in the ground
end of the added capacitor and provide feedback
to this resistor from the collector of 01 through a
1 M[2 resistor.

AN21-13

DRIVEN SWITCHING REGULATOR

When a number of switching regulators are operated from a common power source, it is desirable
to synchronize their operation to more uniformly
distribute the switched current waveforms in the
input line. Synchronous operation can also be
beneficial when a switching regulator is operated
in conjunction with a power converter.

RS
lOOK

...n.rL -.JVvv-.....- .
10 V•• i' SO KHz

input of the error amplifier. The waveform is
obtained by integrating the square wave synchronizing signal. This triangular wave causes the error
amplifier to switch because its gain is high enough
that the waveform easily overdrives it. The switching duty cycle is controlled by the output voltage
fed back to the error amplifier. If the output voltage goes up, the duty cycle will decrease since the
error amplifier will pick off a smaller portion of
the triangular wave. Similarly, the duty cycle will
decrease if the output voltage drops. Hence, the
duty cycle is controlled to produce the desired
output voltage.

tSolid T.nt.lum

Rl
2.4K
1%

Dl
UTX210

A circuit which synchronizes the switching regulator with a square wave drive signal is shown here.
It differs from the switching regulators described
previously in that positive feedback is not used.
I nstead, a triangular wave with a peak-to-peak
amplitude of 25 mV is applied to the noninverting

AN21-14

Without a synchronous drive signal, the circuit will
self oscillate at a frequency determined by L 1 and
C1. This self-oscillation frequency must be lower
than the synchronous drive frequency. Therefore,
more filtering is required for a driven regulator
than for a self-oscillating regulator operating at the
same frequency. Th is also means that a driven
regulator will have less output ripple.
The value of C2 is chosen so that its capacitive
reactance at the drive frequency is less than onetenth the resistance of R2. The amplitude of the
triangular wave is set at 25 mV with R5. It is advisable to ac couple the drive signal by putting a
capacitor in series with R5 so that it does not
disturb the dc reference voltage developed for the
error ampl ifier.

THE LM104 REGULATOR

The basic reference for the regulator is zener diode
01. The reference diode is supplied from a PNP
current source, 08, which has a fixed current gain
of 2. This arrangement permits the circuit to
operate with unregulated input voltages as low as
7V, substantially increasing the efficiency of lowvoltage regulators.

The reference supply terminal is normally connected to the unregulated supply. However,
improved line regulation can be obtained by preregulating the voltage on this terminal. This
improvement occurs because 01, 02, and 07 do
not see changes in input voltage. Normally, it is
the change in the emitter-base voltage of these
transistors with changes in collector-base voltage
which determines the line regulation.

The reference supply is temperature compensated
by using the neg~tive temperature coefficient of
the transistor emitter-base voltages to cancel the
positive coefficient of the zener diode. The design
produces a nominal 2.4V between the reference
and reference supply terminals of the integrated
circuit. Connecting an external 2.4 KS1 resistor
between those terminals gives a 1 mA reference
curr~nt from the collectors of 01 and 02, which is
independent of temperature. The reference voltage
suppl ied to the error ampl ifier is developed across
a second external resistor connected between the
adjustment terminal and ground.
ADJUSTMENT

When the reference supply and unregulated input
terminals are operated from separate voltage
sources, it is important to make sure that the unregulated input terminal of the integrated circuit
does not get more than 2V more positive than the
reference supply terminal. If this happens, the
collector-isolation junction of 06 becomes
forward biased and disrupts the reference.
The error amplifier of the regulator is quite similar
to the LM 101 operational amplifier. Emitter

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R16
15K

R17
7.5K

R15
15K
8 REGULATED
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OUTPUT

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REFERENCE

REFERENCE
SUPPL Y

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COMPENSATION

AN21-15
.
.,

follower input transistors, 018 and 019, drive a
dual PNP which is operated in the common-base
configuration. The current gain of these PNP transistors is fixed at 4 so that the base can be driven
by a current source (013). Active collector loads
are used for the input stage so that a voltage gain
of 2000 is obtained. 021 and 022 provide enough
current gain to keep the internal, series-pass transistor from loading the input stage. R14 limits the
base drive on 023 when it saturates with low, unregulated input voltages. The collector of 023 is
brought out separately so that an external booster
transistor can be added for increased output current capability. R13 established the minimum
operating current in 023 when booster transistors
are used.
One feature of the error amplifier is that it operates properly with common mode voltages all the
way up to ground. Because of this, the circuit will
regulate with output voltages to zero volts.
Current limiting is provided by 024. When the
voltage between the current limit and unregulated
input terminals becomes large enough to turn on
024, it will pull 010 out of saturation and remO\ie
base drive from 021 through 020. This causes the
series pass transistor to exhibit a constant current

AN21,...16

characteristic. The pre-load current, provided for
024 by 010 before current limiting is initiated,
gives a much sharper current-limit characteristic.
Cl and Rll are included in the limiting circuitry
to suppress oscillations.
The error amplifier is connected to a divider on
the output (R 15 and R 16) to keep the reference
current generator from saturating with low inputoutput voltage differentials. A compensating
-resistor, R17, which is equal to the equivalent
resistance of the divider is included to minimize
offset error in the error amplifier.
The major feedback loop is frequency compensated by the brute-force method of rolling off the
response with a relatively large capacitor on the
output. C2 is included on the integrated circuit to
compensate for the effects of series resistance in
the output capacitor. A compensation point is also
brought out so that more capacitance can be
added across C2 for certain regulator configurations. R8 improves the load-transient response,
especially when compensation is added on Pin 4.
The purpose of 09, which is a collector FET, is to
bias the current-source transistors, 012 and 013.
It also supplies the preload current for the
current-limit transistor, 024, through 010.

»
z
January 1969

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THE LM105 - AN IMPROVED
POSITIVE REGULATOR

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INTRODUCTION
IC voltage regulators are seeing rapidly increasing
usage. The LM 100, one of the first, has already
been widely accepted. Designed for versatility, this
circuit can be used as a linear regulator, a switching regulator, a shunt regulator, or even a current
regulator. The output voltage can be set between
2V and 30V with a pair of external resistors, and it
works with unregulated input voltages down to
7V. Dissipation limitations of the IC package restrict the output current to less than 20 mA, but
external transistors can be added to obtain output
currents in excess of 5A. The LM 100 and an
extensive description of its use in many practical
circuits are described in References 1-3.
One complaint about the LM 100 has been that it
does not have good enough regu lation for certain
applications. In addition, it becomes difficult to
prove that the load regulation is satisfactory under
wo rst-case design conditions. These problems
prompted development of the LM 105, which is
nearly identical to the LM 100 except that a gain
stage has been added for improved regulation. In
the great majority of appl ications, the LM 1 05 is a
plug-in replacement for the LM 100:

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The current limiting characteristics of a regulator
are important for two reasons: First, it is almost
mandatory that a regulator be short-circuit protected because the output is distributed to enough

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b. Ti

The load regulation of the LM 1 00 is about 0.1 %,
no load to full load, without current limiting.
When short circuit protection is added, the regulation begins to degrade as the output current
becomes greater than about half the limiting current. This is illustrated in Figure 1. The LM 105, on
the other hand, gives 0.1 % regulation up to currents closely approaching the short circuit current.
As shown in Figure lb, this is particularly significant at high temperatures.

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THE IMPROVED REGULATOR

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FIGURE 1. Comparison Between the Load Regulation of
the LM100 and LM105 for Equal Short Circuit Currents

places that the probability of it becoming shorted
is quite high. Secondly, the sharpness of the limiting characteristics is not improved by the addition
of external booster transistors. External transistors
can increase the maximum output current, but
they do not improve the load regulation at currents approaching the short circuit current. Thus,
it can be seen that the LM 105 provides more than
ten times better load regulation in practical power
supply designs.

AN23-1

Figure 2 shows that the LM 105 also provides
better line regulation than the LM100. These
curves give the percentage change in output voltage for an incremental. change in the unregulated
input voitage. They show that the line regulation is
worst for small differences between the input and
output voltages. The LM 105 provides about three
times better regulation under worst case conditions. Bypassing the internal reference of the regulator makes the ripple rejection of the LM 105
almost a factor of ten better than the LM 100 over
the entire operating range, as shown in the figure.
This bypass capacitor also eliminates noise generated in the internal reference zener of the IC.
VOUT = 10V
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REGULATED OUTPUT

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FEEDBACK

FIGURE 4. Schematic Diagram of the LM105 Regulator.

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LM105 RlprL~ ~E,JECTION

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0.001
10

20

50

INPUT·OUTPUT VOLTAGE DIFFERENTIAL (V)

FIGURE 2. Comparison Between the Line Regulation
Characteristics of the LM 100 and LM 105.

The LM 105 has also benefited from the use of new
IC components developed after the LM 100 was
designed. These have reduced the internal power
consumption so that the LM 105 can be specified
for input voltages up to 50V and output voltages
to 40V. The minimum preload current required by
the LM 100 is not needed on the LM 105.

. CI RCUIT DESCRIPTION
The differences between the LM 100 and the
LM 105 can be seen by comparing the schematic
diagrams in Figures 3 and 4. 04 and 05 have been
added to the LM 105 to form a common-collector,
common-base, common-emitter amplifier, rather
than the single common-emitter differential amplifier on the LM 100.

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2.2K
4

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FIGURE 3. Schematic Diagram of the LM100 Regulator.

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CURRENT LIMIT

1.-..........4 - - - + - - 4 -........_ _ _ _ _ GROUND

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AN23-2

BOOSTER OUTPUT

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UNREGULATED INPUT

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1.-+-4----+-----.:... REFERENCE BYPASS

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I n the LM 100, ~eneration of the reference voltage
starts with zener diode, D1, which is supplied with
a fixed current from one of the collectors of 02.
This regulated voltage, which has a positive temperature coefficient, is buffered by 04, divided
down by R 1 and R2 and connected in series with a
diode-connected transistor, 07. The negative temperature coefficient of 07 cancels out the positive
coefficient of the voltage across R2, producing a
temperature-compensated 1.8V on the base of 08.
This point is also brought outside the circuit so
that an external capacitor can be added to bypass
any noise from the zener diode.
Transistors 08 and 09 make up the error ampl ifier
of the circuit. A gain of 2000 is obtained from this
single stage by using a current source, another collector on 02, as a collector load. The output of
the amp I ifier is buffered by 011 and used to drive
the series-pass transistor, 012. The collector of
012 is brought out so that an external PNP transistor, or PNP-NPN combination, can be added
for increased output current.
Current limiting is provided by 010. When the
voltage across an external resistor connected
between Pins 1 and 8 becomes high enough to turn
on 010, it removes the base drive from 011 so the
regulator exhibits a constant-current characteristic.
Prebiasing the current limit transistor with a portion of the emitter-base voltage of 012 from R6
and R7 reduces the current limit sense voltage.
This increases the efficiency of the regulator,
especially when fold back current limiting is used.
With foldback limiting; the voltage dropped across
the current sense resistor is about four times larger
than the sense voltage.
As for the remaining details, the coltector of the
ampl ifier, 09, is brought out so that external
collector-base capacitance can be added to
frequency-stabilize the circuit when it is used as a
linear regulator. This terminal can also be grounded
to shut the regulator off. R9 and R4 are used to
start up the regulator, while the rest of the circuitry establishes the proper operating levels for
the current source transistor, 02.

The reference circuitry of the LM 105 is the same,
except that the current through the reference
divider, R2, R3 and R4, has been reduced by a
factor of two on the LM 105 for reduced power
consumption. I n the LM 105, 02 and 03 form an
emitter coupled amplifier, with 03 being the
emitter-follower input and 02 the common-base
output amplifier. R6 is the collector load for this
stage, which has a voltage gain of about 20. The
second stage is a differential amplifier, using 04
and 05. Q5 actually provides the gain. Since it has
a current source as a collector load, one of the
collectors of Q12, the gain is quite high: about
1500. Th is gives a total ga in in the error ampl ifier
of about 30,000, which is ten times higher than
the LM 100.
It is not obvious from the schematic, but the first
stage (02 and Q3) and second stage (04 and 05)
of the error amplifier are closely balanced when
the circuit is operating. Thiswill be true regardless
of the absolute value of components and over the
operating temperature range. The only thing
affecting balance is component matchi ng, wh ich is
good in a monolithic integrated circuit, so the
error amplifier has good drift characteristics over a
wide temperature range.
Frequency compensation is accomplished with an
external integrating capacitor around the error
amplifier, as with the LM 100. This scheme makes
the stability insensitive to loading conditionsresistive or reactive-while giving good transient
response. However, an internal capacitor, C1, is
added to prevent minor-loop oscillations due to
the increased gain.
Additional differences between the LM 100 and
LM 105 are that a field-effect transistor, 018, connected as a current source starts the regulator
when power is first applied. Since this current
source is connected to ground, rather than the output, the minimum load current before the regulator drops out of operation with large inputoutput voltage differentials is greatly reduced. This
also minimizes power dissipation in the integrated
circuit when the difference between the input and
output voltage is at the worst-case value. With the
LM 105 circuit configuration, it was also necessary
to add Q17 to eliminate a latch-up mechanism
which could exist with lower output-voltage settings. Without Q17, this could occur when 03
saturated and cut off the second stage ampl ifiers,
04 and Q5, causing the output to latch at a voltage nearly equal to the unregulated input.

POWER LIMITATIONS
Although it is desirous to put as much of the regulator as possible on the IC chip, there are certain
basic limitations. For one, it is not a good idea to
put the series pass transistor on the chip. The
power that must be dissipated in the pass transistor is too much for practical IC packages. Further, IC's must be rated at a lower maximum operating temperature than power transistors. This
means that even with a power package, a more-

massive heat sink would be required if the pass
transistor was included in the IC.
Assuming that these problems could be solved, it is
still not advisable to put the pass transistor on the
same chip with the reference and control circuitry:
changes in the unregulated input voltage or load
current produce gross variations in chip temperature. These variations worsen load and line regulation due to temperature interaction with the control and reference circuitry.
To elaborate, it is reasonable to neglect the package problem since it is potentially solvable. The
lower, maximum operating temperatures of IC's,
however, present a more basic problem. The control circuitry in an IC regulator runs at fairly low
currents. As a result, it is more sensitive to leakage
currents and other phenomena which degrades the
performance of semiconductors at high temperatures. Hence, the maximum operating temperature
is limited to 150°C in military temperature range
applications. On the other hand, a power transistor
operating at high currents may be run at temperatures up to 200°C, because even a 1 mA leakage
current would not affect its operation in a properly designed circuit. Even if the pass transistor
developed a permanent 1 mA leakage from channeling, operating under these conditions of high
stress, it would not affect circuit operation. These
conditions would not trouble the pass transistor,
but they would most certainly cause complete failure of the control circuitry.

These problems are not eliminated in applications
with a lower maximum operating temperature.
I ntegrated circuits are sold for limited temperature
range appl ications at considerably lower cost. This
is mainly based on a lower maximum junction
temperature. They may be rated so that they do
not blow up at higher temperatures, but they are
not guaranteed to operate within specifications at
these temperatures. Therefore, in applications with
a lower maximum ambient temperature, it is
n,Jcessary to purchase an expensive full temperature range part in order to take advantage of the
theoretical maximum operating temperatures of
the IC.

Figure 5 makes the point about dissipation limitations more strongly. It gives the maximum short
circuit output current for an IC regulator in a
TO-5 package, assuming a 25°C temperature rise
between the chip and ambient and a quiescent current of 2 mAo Dual-in-line or flat packages give
results which are, at best, slightly better, but are
usually worse. If the short circuit current is not of
prime concern, Figure 5 can also be used to give
the maximum output current as a function of
input-output voltage differential. However, the
increased dissipation due to the quiescent current
flowing at the maximum input voltage must be
taken into account. In addition, the input-output
differential must be measured with the maximum
expected input Voltages.
AN23-3

base transistor like the 2N3740 is recommended
because it causes fewer oscillation problems than
double-diffused, planar devices. In addition, it
seems to be less prone to failure under overload
conditions; and low cost devices are available in
power packages like the TO-66 or even TO-3.

1.0

10

When the maximum dissipation in the pass transistor is less than about 0.5W, a 2N2905 may be
used as a pass transistor. However, it is generally
necessary to carefully observe thermal deratings
and provide some sort of heat sink.

100

OUTPUT CURRENT (rnA)

FIGURE 5. Dissipation Limited Short Circuit Output
Current for an IC Regulator in a TO-5 Package.

The 25°C temperature rise assumed in arriving at
Figure 5 Is not at all unreasonable. With military
temperature range parts, this is valid for a maximu m j unctibn temperature of 150°C with a 125° C
ambient. For low cost parts, marketed for limited
temperature range applications, this maximum differential appropriately derates the maximum junction temperature.
In practical designs, the maximum permissible
dissipation will always be to the left of the curve
shown for an infinite heat sink in Figure 5. This
curve is realized with the package immersed in
circulating acetone, freon ,or mineral oil. Most heat
sinks are not quite as good.
To summarize, power transistors can be run with a
temperature differential, junction to ambient, 3 to
5 times as great as an integrated circuit. This
means that they can dissipate much more power,
even With a smaller heat sink. This, coupled with
the fact that low cost, mu Itilead power packages
are not available and that there can be thermal
interactions between the control circuitry and the
pass transistor, strongly suggests that the pass transistors be kept separate from the integrated circuit.

In the circuit of Figure 6, the output voltage is
determined by R 1 and R2. The resistor values are
selected based on a feedback voltage of 1.SV to
Pin 6 of the LM 105. To keep thermal drift of the
output voltage within specifications; the parallel
combination of R 1 and R2 should be approximately 2K. However, this resistance is not critical.
Variations of ±30% will not cause an appreciable
degradation of temperature drift.
The 1 fJ.F output capacitor, C2, is required to suppress oscillations in the feedback loop involving
the external booster transistor, 01, and the output
transistor of the LM 105. C 1 compensates the
internal regulator circuitry to make the stability
independent for all loading conditions. C3 is not
normally required if the lead length between the
regulator and the output filter of the rectifier is
short.
Current limiting is provided by R3. The current
I imit resistor should be selected so that the maximum voltage drop across it, at full load current, is
equal to the voltage given in Figure 7 at the maxi"
mum junction temperature of the IC. This assures
a no load to full load regulation better than 0.1 %
under worst-case conditions.
260

>

~
~. .

USING BOOSTER TRANSISTORS
Figure 6 shows how an external pass transistor is
added to the.lM 105. The addition of an external
PNP transistor does not increase the minimum
input output' voltage differential. This would
happen if an NPN transistor was used in a compound emitter follower connection with the NPN
output transistor of the IC. A single-diffused, wide

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VOUT

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R3

0.65
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2N3740

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......-GROUND

FIGURE 6. 0.2A Regulator.

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20 40 60 80 100 120 140 160
JUNCTION TEMPERATURE (OC)

FIGURE 7. Maximum Voltage Drop Across Current
Limit Resistor at Fult Load for Worst Case
Load Regulation of 0.1% .
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--.-..,----~t_---~~

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lo$12mA
220 t-+l-"k:
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The short circuit output currentis also determined
by R3. FigureS shows the voltage drop across this
resistor, when the output is shorted, as ~ function
of junction ttmperature in the IC.

lMl05

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,....,..-..."T"""......,......,........................,......,..._ _

With the typJ bf current limiting used in Figure 6,
the dissipation under short circuit conditions can
be more than three times the worst-case full load
dissipation. Hence, the heat sink for the pass tran\

AN23-4

R3. Therefore, more voltage must be developed
across R3 before current limiting is initiated. After
the output voltage begins to fall, the bucking
voltage is reduced, as it is proportional to the output voltage. With the output shorted, the current
is reduced to a value determined by the current
limit resistor and the current limit sense voltage of
the LM1 05.

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JUNCTION TEMPERATURE (OCI

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FIGURE 8. Voltage Drop Across Current Limit Resistor
Required to Initiate Current Limiting.

sistor must be designed to accommodate the increased dissipation if the regulator is to survive
mor-e than momentarily with a shorted output. It
is encouraging to note, however, that the short
circuit current will decrease at higher ambient temperatures. This assists in protecting the pass transistor from excessive heating.

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OUTPUT CURRENT (AI

FIGURE 10. Limiting Characteristics of Regulator Using
Foldback Current Limiting.

FOLDBACK CURRENT LIMITING
With high current regulators, the heat sink for the
pass transistor must be made quite large in order
to handle the power dissipated under worst-case
conditions. Making it more than three times larger
to withstand short circuits is sometimes inconvenient in the extreme. This problem can be solved
with foldback current limiting, which makes the
output current under overload conditions decrease
below the full lo.ad current as the output voltage is
pulled down. The short circuit current can be
made but a fraction of the full load current.
A high current regulator using foldback limiting is
shown in Figure 9. A second booster transistor,
01, has been added to provide 2A output current
without causing excessive dissipation in the
LM 105. The resistor across its emitter base junction bleeds off any collector base leakage and·
establishes a minimum collector current for 02 to
make the circu it easier to stabilize with light loads.
The foldback characteristic is produced with R4
and R5. The voltage across R4 bucks out the
voltage dropped across the current sense resistor,

where V lim is the current limit sense voltage of the
LM105, given in Figure 8, and Isc .is the design
value of short circuit current. R5 is then obtained
from

R5 =

V OUT + V sense
,
I bleed + I bias

(2)

R2

Finally, R4 is given by

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In design, the value of R3 is determined from

where V OUT is the regulated output voltage, V sense
is maximum voltage across the current limit resistor for 0.1% regulation as indicated in Figure 7,
I bleed is the preload current on the regulator output provided by R5 and I bias is the maximum current coming out of Pin 1 of the LM105 under full
load conditions.lbiaswill be equal to 2 mA plus the
worst-case base drive for the PNP booster transistor, 02. Ibleed should be made about ten times
greater than I bias'

C4
O.OSIlF

V ,N

Figure 10 illustrates the limiting characteristics.
The circuit regulates for load currents up to 2A.
Heavier loads will cause the output voltage to
drop, reducing the available current. With a short
on the output, the current is only 0.5A.

;

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+ C2t

2.lK
1%

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herroxcube KS·OOI-OO/lB

FIGURE 9. 2A Regulator with Foldback Current limiting.

(3)

where IFL is the output current of the regulator at
full load.

AN23-5

With foldback limiting, power dissipation in the
pass transistor reaches a maximum at some point
between full load and short circuited output. This
is illustrated in Figure 11. However, if the
maximum dissipation is calculated with the
worst-case input Voltage, as it should be, the power
peak is not too high.

It is recommended that a ferrite bead be strung on
the emitter of the pass transistor, as shown in Figure 9, to suppress oscillations that may show up
with certain physical configurations. It is advisable
to also include C4 across the current limit resistor.
I n some applications, the power dissipated in 02
becomes too great for a 2N2905 under worst-case
conditions. This can be true even if a heat sink is
used, as it should be in almost all applications.
When dissipation is a problem, the 2N2905 can be
replaced with a 2N3740. With a 2N3740, the ferrite bead and C4 are not needed because this transistor has a lower cutoff frequency.

25

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f-Ise = 0.5A
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12

HIGH CURRENT REGULATOR
The output current of a regulator using the LM 105
as a control element can be increased to any desired level by adding more booster transistors, increasing the effective current gain of the pass transistors. A circuit for a 10A regulator is shown in
Figure 12. A third NPN transistor has been included to get higher current. A low frequency
device is used for 03 because it seems to better
withstand abuse. However, high frequency transistors must be used to drive it. 02 and 03 are both
double-diffused transistors with good frequency
response. This insures that 03 will/present the
dominant lag in the feedback loop through the
booster transistors, and back around the output
transistor of the LM 105. This is further insured by
the addition of C3.

R3
0.16

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03

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5,55K

= ""'"

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10V

R2
3,15K
C4 t

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35V

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160

FIGURE 12. 10A Regulator
Limiting.

AN23-6

16

FIGURE 11. Power Dissipation in Series Pass Transistors
Under Overload Conditions in Regulator
Using Foldback Current Limiting.

~---_e-'V\,."..~....-----~....- -...-VOUT= 5V

I

14

OUTPUT VOLTAGE (V)

Figure 10 shows that foldback limiting can only be
used with certain kinds of loads. When the load
looks predominately like a current source, the load
line can intersect the foldback characteristic at a
point where it will prevent the regulator from
coming up to voltage, even without an overload.
Fortunately, most solid state circuitry presents a
load line which does not intersect. However, the
possibility cannot be ignored, and the regulator
must be designed with some knowledge of the
load.

15V
3.3~F

15

3:

Even though the voltage dropped across the sense
resistor is larger with foldback limiting, the minimum input-output voltage differential of the complete regulator is not increased above the 3V specified for the LM 105 as long as this drop is less than
2V. This can be attributed to the low sense voltage
of the IC by itself.

C3 t

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2

June 1969

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A SIMPLIFIED TEST SET FOR

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OPERATIONAL AMPLIFIER CHARACTERIZATION

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INTRODUCTION

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The test set described in this paper allows complete quantitative characterization of all dc operational amplifier parameters quickly and with a
minimum of additional equipment. The method
used is accurate and is equally suitable for laboratory or production test-for quantitative readout
or for limit testing. As embodied here, the test set
is conditioned for testing the LM709 and LM 101
amplifiers; however, simple changes discussed in
the text will allow testing of any of the generally
available operational amplifiers.
Amplifier parameters are tested over the full range
of common mode and power supply voltages with
either of two output loads~ Test set sensitivity and
stability are adequate for testing all presently
available integrated amplifiers.
The paper will be divided into two sections, i.e., a
functional description, and a discussion of circuit
operation. Complete construction information will
be given including a layout for the tester circuit
boards.

FUNCTIONAL DESCRIPTION
The test set operates in one of three basic modes.
These are: (1) Bias Current Test; (2) Offset
Voltage, Offset Current Test; and (3) Transfer

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Function Test. In the first two of these tests, the
amplifier under test is exercised throughout its full
common mode range. In all three tests, power
supply voltages for the circuit under test may be
set at ±5V, ±10V, ±15V or ±20V.

."

POWER SUPPLY

::!l

Basic waveforms and dc operating voltages for the
test set are derived from a power supply section
comprising a positive and a negative rectifier and
filter, a test set voltage regulator, a test circuit
voltage regulator, and a function generator. The
dc supplies will be discussed in the section dealing
with detailed circuit description.

(")

The waveform generator provides three output
functions, a ±19V square wave, a -19V to +19V
pulse with a 1% duty cycle, and a ±5V triangular
wave. The square wave is the basic waveform from
which both the pulse and triangular wave outputs
are derived.
The square wave generator is an operational amplifier connected as an astable multivibrator. This
amplifier provides an output of approximately
±19V at 16 Hz. This square wave isused to drive
junction FET switches in the test set and to generate the pulse and triangular waveforms.

AN24-1

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FIGURE 1. Functional Diagram of Bias Current Test
Circuit

The pulse generator is a monostable multivibrator
driven by the output of the square wave generator.
This multivibrator is allowed to swing from negative saturation to positive saturation on the
positive going edge of the square wave input and
has a time constant which will provide a duty
cycle of approximately 1%. The output is approximately -19V to +19V.
The triangular wave generator is a dc stabilized
integrator driven by the output of the square wave
generator and provides a ±5V output at the square
wave frequency, inverted with respect to the
square wave.
The pLirpose of these various outputs from the
power supply section wi II be discussed in the functiona.1 description.

BIAS CURRENT TEST
A functional diagram of the bias current
circuit is shown in Figure 1. The output of
triangular wave generator and the output of
test circuit, respectively, drive the horizontal
vertical deflection of an oscilloscope.

test
the
the
and

The device under test, (cascaded with the integrator, A 7 ), is connected in a differential amplifier

AN24-2

configu ratio n by R 1, R 2, R 3, and R4 . The inputs
of this differential amplifier are driven in common
from the output of the triangular wave generator
through attenuator R8 and amplifier A 8 . The
inputs of the device under test are connected to
tlTe feedback network through resistors R sand
R 6 , shunted by the switch Ss a and Ss b'
The feedback r·letwork provides a closed loop gain
of 1,000 and the integrator time constant serves to
reduce noise at the output of the test circuit as
well as allowing the output of the device under
test to remain near zero volts.
The bias current test is accomplished by allowing
the device under test to draw input current to one
of its inputs through the corresponding input resistor on positive going or negative going halves of
the triangular wave generator output. This is
accompl ished by closing Ss a or Ss b on alternate
halves of the triangular wave input. The voltage
appearing across the input resistor is equal to input
current times the input resistor. This voltage is
multiplied by 1,000 by the feedback loop and
appears at the integrator output and the vertical
input of the oscilloscope. The vertical separation
of the traces representing the two input currents
of the amplifier under test is equivalent to the
total bias current of the amplifier under test.

The bias current over the entire common mode
range may be examined by setting the output of
A8 equal to the amplifier common mode range. A
photograph of the bias current oscilloscope display
is given as Figure 2. In this figure, the total input

current test. The only difference is that the
switches Ss a and Ss b are closed on the same halfcycle of the triangular wave input.
The synchronous operation of Ss a and S5 b forces
the amplifier under test to draw its input currents
through matched high and low input resistors on
alternate halves of the input triangular wave. The
difference between the voltage drop across the two
values of input resistors is proportional to the difference in input current to the two inputs of the
amplifier under test and may be measured as the
vertical spacing between the two traces appearing
on the face of the oscilloscope.
Offset voltage is measured as the vertical spacing
between the trace corresponding to one of the two
values of source resistance and the zero volt baseline. Switch S6 and Resistor R9 are a base line
chopper whose purpose is to provide a basel ine
reference· which is independent of test set and
oscilloscope drift. S6 is driven from the pulse output of the function generator and has a duty cycle
of approximately 1% of the triangular wave.

FIGURE 2. Bias Current and Common Mode Rejection
Display

current of an amplifier is displayed over a ±10V
common mode range with a sensitivity of 100 nA
per vertical division.

Figure 3 is a photograph of the various waveforms
presented during this test. Offset voltage and offset current are displayed at a sensitivity of 1 mV
and 100 nA per division, respectively, and both
parameters are displayed over a common mode
range of ±1 OV.

The bias current display of Figure 2 has the added
advantage that incipient breakdown of the input
stage of the device under test at the extremes of
the common mode range is easily detected.
If either or both the upper or lower trace in the
bias current display exhibits curvature near the
horizontal ends of the oscilloscope face, then the
bias current of that input of the amplifier is shown
to be dependent on common mode voltage. The
usual causes of this dependency are low breakdown voltage of the differential input stage or
current sink.

OFFSET VOLTAGE, OFFSET CURRENT TEST
The offset voltage and offset current tests are
performed in the same general way as the bias

FIGURE 3. Offset Voltage, Offset Current and Common
Mode Rejection Display

AN24-3

r------------------- 45V

FIGURE 7. Test Circuit

from the output of 0 1 l' During the transfer function test, 0 6 and 0 7 are switched on continuously
by turning off 011. R42 and R45 maintain the
gates of the F ET switches at zero gate to source
voltage for maximum conductance during their on
cycle. Since the sources of these switches are at
the common mode input voltage of the device
under test, these resistors are connected to the
output of the common mode driver amplifier, As.

The input for the integrator-feedback buffer, A7 ,
is selected by the FET switches 0 4 and 05' During
the bias current and offset voltage offset current
tests, A7 is connected as an integrator and receives
its input from the output of the device under test.
The output of A7 drives the feedback resistor,
R4 o. In this connection, the integrator holds the
output of the device under test near ground and
serves to amplify the voltages corresponding to

AN24-7

bias current, offset current, and offset voltage by a
factor of 1,000 before presenting them to the measurement system. F ET switches Q 4 and Q s are
turned on by switch section S1 bduring these tests.
FET switches Q4 and Os are turned off during the
transfer function test. This disconnects A7 from
the output of the device under test and changes it
from an integrator to a non-inverting unity gain
amplifier driven from the triangular wave output
of the function generator through the attenuator
R33 and R34 and switch section Sla' In this connection, amplifier A7 serves two functions; first,
to provide an offset voltage correction to the input
of the device under test and, second, to drive the
input of the device under test with a ±2.5 mV
triangular wave centered about the offset voltage.
During this test, the common mode driver amplifier is disabled by switch section SI a and the
vertical input of the measurement oscilloscope is
transferred from the output of the integratorbuffer, A 7 , to the output of the device under test
by switch section SI d. S2 a allows supply voltages
for the device under test to be set at ±5, ±10, ±15,
or ±20V. S2 b changes the vertical scale factor for
the measurement oscilloscope to maintain
optimum vertical deflection for the particular
power supply voltage used. S4 is a momentary
contact pushbutton switch which is used to change
the load on the device under test from 10kSl
to 2kSl.
A delay must be provided when switching from
the input tests to the transfer function tests. The
purpose of this delay is to disable the integrator
function of A7 before driving it with the triangular
wave. If this is not done, the offset correction voltage, stored on C 1 6, will be lost. This delay between opening FET switch Q4, and switch Qs, is
provided by the RC filter, R 3 sand C 19·
Resistor R41 and diodes 0 7 and 0 8 are provided
to control the integrator when no test device is
present, or when a faulty test device is inserted.
R41 provides a dc feedback path in the absence of
a test device and resets the integrator to zero.
Diodes 0 7 and 0 8 clamp the input to the integrator to approximately ±.7 volts when a faulty
device is inserted.
FET switch Q l and resistor R28 provide a ground
reference at the beginning of the 50-ohm-source,
offset-voltage trace. This trace provides a ground

AN24~8

reference which is independent of instrument or
oscilloscope calibration. The gate of Q 1 is driven
by the output of monostable multivibrator As,
and shorts the vertical oscilloscope drive signal to
ground during the time that As output is positive.
Switch S3, R 27 , and R 28 provide a 5X scale
increase during input parameter tests to allow
measurement of amplifiers with large offset
voltage, offset current, or bias current.
Switch Ss allows amplifier compensation to be
changed for 101 or 709 type amplifiers.
CALIBRATION
Cal ibration of the test system is relatively simple
and requires only two adjustments. First, the output of the main regulator is set up for 20V. Then,
the triangular wave generator is adjusted to provide ±5V output by selecting R adj . This sets the
horizontal sweep for the X-V oscilloscope used as
the measurement system. The oscilloscope is then
set up for 1 V /division vertical and for a full 10
division horizontal sweep_
Scale factors for the three test positions are:
1. Bias Current Display (Figure 2)
Ibias total
100 nA/div. vertical
Common Mode Voltage Variable horizontal
2. Offset Voltage-Offset Current (Figure 3)
Ioffset
100 nA/div. vertical
Voffset
1 mV /div. vertical
Common Mode Voltage Variable horizontal

3. Transfer Function (Figure 5)
V in
0.5 mV /div.
V out
5V/div. @ Vs
5V/div. @ Vs
2V/div. @ Vs
1V/div.@ V s
.

Gain

±20V
±15V
±10V
± 5V

~Vout

=--

~Vin

CONSTRUCTION
Test set construction is simplified through the use
of integrated circuits and etched circuit layout_
Figure 8 gives photographs of the completed
tester. Figure 9 shows the parts location for the
components on the circuit board layout of Figure 10. An attempt should be made to adhere to

this layout to insure that parasitic coupling between elements will not cause oscillations or give
calibration problems.
Table 1 is a listing of special components which
are needed to fit the physical layout given for the
tester.
TABLE 1. Partial Parts List
T1

TriadF-90X

S1

Centraiab PA2003 non-shorting
Centralab PA2015 non-shorting

5 3 ,5 4 Grayhill 30-1 5eries 30 subminiature
pushbutton switch
5 5 ,5 6 Alcoswitch MST-1050 SPOT
CONCLUSIONS
A semi-automatic test system has been described
which will completely test the important operatioral amplifier parameters over the full power
supply and common mode ranges. The system is
si m p Ie, inexpensive, easily calibrated, and is
equally suitable for engineering or quality assurance usage.

FIGURE Sa. Bottom of Test Set

AN24-9

FIGURE 8b. Front Panel

FIGURE 8c. Jacks

AN24-10

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/"

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FIGURE 9. Component Location, Top View

AN24:"'11

FIGURE 10. Circuit Board Layout

AN24-12

»
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January 1970

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HIGH-SPEED MOS COMMUTATORS

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Speed and accuracy of MOS analog commutators
are being improved sharply by techniques initially
developed to make large-scale MOS digital integrated circuits compatible with bipolar logic circuits. Now, TTL logic can drive an MOS commutator at rates up to 20 MHz, with signal accuracies better than 90%. And at lower frequencies,
accuracies very close to 100% can be achieved.
In t,he past, MOS monolithic commutators and
multiplexers were recommended for precision analog switching only at relatively low rates, on the
order of 10 kHz. Commutation at higher rates was
considered risky because of large noise transients
produced by the MOS switching transistors. Considerable time had to be allowed for the transients
to settle down before the signal could be sampled
accurately.
Transient noises have been reduced to at least half
their former level by processes that lower the
switch ing-voltage threshold of the MOS transistors.
The processes also cut impedance and leakage current, permitting low-impedance designs that further enhance commutator performance.

Although they switch analog voltages, the MOS
field-effect transistors in these commutators can
be interfaced with logic ICs almost as readily as
low-voltage MOS ICs. Either MOS or bipolar logic
can control the MOSFET gate Voltages. Only a few
volts change in the gate voltage will turn the
MOSFETs on or off.
Examples of new multichannel designs for analog/
digital data-gathering applications are shown in
Figures 1 and 2. Circuit impedances have been
optimized in each so that commutation rates are
much higher than the normal 200 to 500 kHz
rate of low-voltage MOS commutators (rates, incidentally, about twice as high as the maximum
rates of high-threshold commutators). The all-MOS
system in Figure 1 operates at 1 MHz, while the
MOS/TTL system in Figure 2 achieves 20 MHz.
LOWERING THRESHOLD VOLTAGES
Reducing the MOSFET switching-threshold voltage, VTH, improves most of the characteristics that
affect commutator performance. Chief result is a
reduction in the gate-voltage change needed to

Vx=±10V
ANALOG INPUTS
(Z'N=2 Kn)

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A2
A3
A4

- - - - o ~~~~8ACK

L.----:.;.;=....- - - - - I f - - - - -...

81~§

82

83
84

ANALOG

1--+----0 OUTPUT
(ZOUT =

41K)

Cl~§

C2
C3

C4

(250 KHz)

02
01~E3
03

E4

04

CLOCK INPUT
(Fmax = 1 MHz)

Voo= OV
VGG =-24W
Va = Vss = +12V FOR ±10V ANALO,G INPUTS
RON = 200n

FIGURE 1. AII-MOS 1-MHz Multiplexer or Commutator

AN28-1

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Yx = ±lY TO ±2Y
ANALOG INPUTS
(Z'N <200.11)

ANALOG
OUTPUT

,.......-----.....~--------..._o

(ZOUT '" 10 Kn)

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Fmax = 20 MHz
Y+ = +10Y OR +12Y
Yss = +1 OR +2Y
RON =200.11

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FIGURE 2. Hybrid MOS/TTL 20-MHz Commutator for Low-Level Signals

switch the MOSFET on and off. I n turn, switching
times and the noise. transients and circuit impedances that produce signal errors can all be reduced. The benefits of lowering V TH are additive,
particularly in multichannel commutators. The
signal may go through several switches in series.

source and drain (the source is the most positive
termi nal). V THis the bias at wh ich the layer of
intrinsic semiconductor, with no surplus of electrons or holes, and the p-channel reach the drain
diffusion. Conduction begins at this point and
increases as VG goes more negative than VTH
(that is, when the gate-to-source voltage -VGS is
more than V TH ).

The importance of the threshold voltage is illustrated in Figure 3, which shows schematically the
operation of a p-channel enhancement type of
MOSFET (the basic element of most MOS integrated circuits). It conducts when the gate voltage
is more negative than the potential of the source
and the bulk semiconductor substrate Vss by at
least V TH . The oxide under the gate electrode acts
as the dielectric of a capacitor. The electric field
applied to the gate electrode cause holes (absence
of electrons) to appear in the channel region
starting from the source. The n-type silicon there
is converted to p-type, eliminating the p-n diode
junctions that had blocked current flow between

The (1-0-0) silicon process described in the appendix produces MOSFETs whose V T H is 1.8 to 2.5
volts when there is no bias between bulk (substrate) and source (V BS = 0). In comparison, a
conventional MOSFET made with (1-1-1) silicon
has a V TH of about 4V. Practical MOS circuits do
have some V BS bias and usually some additional
signal voltage at the source, which raise the working value of V TH . As the typical V TH curves in
Figure 4 show, the threshold of a device rises with

VBS'

OXIDE

SUBSTRATE
(BULK)

OFF
(IMPEDANCE ROFF '" 10' °n)

THIN INTRINSIC
LAYER UNDER
HYPE SILICON

YB (Y ss )
THRESHOLD

ON
(IMPEDANCE RON'" 200.11)

FIGURE 3. Channel Enhancement in MOS Transistors (P Channel)

AN 26-2

A general equation describing these relationships is

accurate commutation. I n contrast, a 2V threshold
makes the necessary swing only from +10V to
about -20V. The difference becomes more significant at lower signal voltages. At V x = ± ~ V, for
instance, the high V TH device requires a sWing
from at least +lV to -10V, while the low V TH
device does the job with +1 V to -6V - about a
third less. High-speed, low-impedance TTL gates
can control a commutator in the latter voltage
range, as shown in Figure 2, because such small
transitions can be made very rapidly. They are
close enough to bipolar logic transitions for the
use of simple, high-speed TTL-to-MOS interfaces.

where K is a device constant (usually 0.8 to 1.2)
and ±2¢F is the zero-bias threshold. This equation
produces curves such as those in Figure 4.
10
9

r--- VTH =4V

.A

o

!
~

V

>

L

"....

---- --

;I"~=2V

V
10

15

20

Multichannel switches made with (1-0-0) silicon
typically operate with a maximum change in
control voltage of from +14V to -30V, which
permits Vx = ±14V. Relatively few practical applications require so large a swing. If larger signal
voltage must be handled, it would be cheaper to
use a scaler than to pay the cost of a high-voltage
multiplexer with beefed-up control circuitry.

25

VBULK TO SOURCE

FIGURE 4. Typical Threshqld-Voltage Curves

The MOSFET equivalent circuit (Figure 5) offers
further insight into the importance of lowering
VTH. The smaller change in VG means that smaller
transient voltages will appear at source and drain.
The transients are caused by charging and discharging of the capacitances. The time required to
change V G and the duration of the transients will
be smaller, too. The value of RON, the MOSFET's
impedance while conducting, will also be less at
any given value of V G more negative than V TH.
Any reduction in RON will make V OUT more
nearly equal to V IN . The accuracy of an analog
switch is determined by the ratio VOUT/VIN.

ON AND OFF RESISTANCES
For best signal accuracy and maximum switching
rate, impedances should be low. The resistance of
a MOSFET while on, RON, varies with signal voltage, so it cannot be compensated readily. This produces a variable error term called RON modulation.
MOS commutators are usually structured as series
switches (Figure 6a). Two or more ranks of commutators are generally used, as in Figure 1, to
minimize the control circuitry. The added ranks
put additional MOSFETs in each signal channel
and enlarge the amount and variation in RON of
the conducting channel. I f V x varies, the error
ratio VouT/VIN tends to vary because RON is a
function of the effective switching threshold
which rises and falls with V x .

CONTROL VOLTAGES
Signal voltage V x often varies between positive
and negative values in commutator applications.
To make certain that the MOSFET switches on
under all signal conditions, V G must swing from at
least Vx to (VSS-VTH-AV-VX), where ±Vx are
the signal limits and AV is the overdrive needed to
lower the switch's series resistance to the desired
level (mainly, reduction in Ro N obtained by
making -V GS more negative).

There is no simple way of keeping RON constant.
Usually, the effect of the variation is reduced by
increasing the other impedances, but that lowers
the maximum switching rate. A low-VTH eases this
problem greatly. All other conditions being equal,
the MOSFET with the lowest V TH will conduct
better at any given value of V G more negative than
V TH . The p-channel enhancement will be greater

If the signal range is fairly wide, say ±10V, the
gate voltage of a MOSFET with a 4V to 6V threshold must swing from +10V to about -26V for

CDB

CSB

BULK

FIGURE 5. Equivalent Circuit of P-Channel MOSFET

::AN28-3

and the channel electrically larger. Figure 6c is a
typical curve of RON versus gate bias. Low-VTH
analog switches made with (1-0-0) silicon by National Semiconductor as integrated circuits achieve
RON values comparable to those of larger, but
higher-V TH , discrete MOSFETs--from 250 to 300
ohms at V x = -10V and about 100 ohms when
V x = +10V. The RON of a high-VTH integrated
commutator, in contrast, is typically a few hundred ohms higher and some reportedly reach a few
kilohms.
To swamp out the voltage-divider effect in Figure
6b, it has been customary to make the load, R L,
much larger than the combination of RON and
Rs. Output impedances in the megohm range
are often used with high-V TH devices. But note in
Figure 2 that very low values of source and load
impedance can be used with low-VTH commutators. These low impedances and the very low
impedance of the TTL circuit controlling the gate
are two of the main reasons for this commutator's
exceptionally high speed.
Source impedance is usually made equal or less
than RON so that leakage ,currents of the turnedoff MOSFETs can return to a low-impedance
turned-on channel signal source. Leakage per
switch is small in an integrated circuit commutator, but there are several switching devices with a
common output in the same semiconductor substrate. Leakage currents could add up to a value
that seriously degrades signal accuracy. I n any
semiconductor device, leakage increases,' rapidly
with temperature. However, the leakage specification is so small in our commutator made with
(1-0-0) silicon that they will work well up to a
temperature of 125°C, while commutators made
with (1-1-1) silicon have been specified for a
maximum operating temperature of only 85°C.
Regardless of the process, the 0 F F resistance,
RoFF , of a well-made MOSFET is generally high
enough to prevent the signal in the OFF channel
(channel V y in Figure 6a) from appearing at the

output and degrading the accuracy of the signal
through the on channel (V x in thefigure). ROFF
is usually around 10 10 ohms. If V y is a highfrequency signal, there may be significant AC
feedthrough, but this can be prevented by techniques to be discussed shortly.

SWITCHING SPEED AND NOISE
The absolute switching speed of a commutator is
limited by the time required to charge and discharge the device capacitances. Circuit impedances
affect speed by contributing to the RC time constants. However, the practical switching rate of a
precision commutator depends upon the time required for the output signal to, recover from
the noise transients produced during the chargedischarge cycles. Low-V TH processing cuts transient recovery time because the ,transients' duration and amplitude are reduced. Some designs
make the recovery time negligible.
In all MOSFETs, transmission of a t!Jrn-on or turnoff signal is followed by a delay whose length depends upon the magnitude and rate of change of
the gate-control voltage. At turn-on, the delay is
lengthened by the RC time constant of the gate-'
bulk capacitance (see Figure 5) and the impedance in the control circuit. Capacitances and impedances in the signal path cause a similar delay at
turn-off. As V GS goes negative, turning the switch
on, energy is pulled from the source and load
impedances through the gate-source and gate-drain
capacitances, as in the simplified equivalent circuit
of Figure 7a. At turn-off; V G S goes to zero volts
or positive, and energy is pushed out through the
same paths.
Thus, negative turn-on and positive turn-off transients appear at the summing node. The transient
waveforms of low V TH and high. V TH MOSFETs
are shown simplified and superimposed in Figure
7b. The levels are typical for devices with V TH
= 2V and V TH = 4V at Vx = ±1 V. The larger gate
voltages used at higher signal voltages would make
durations and amplitudes proportionately larger
2,0
1.9

1\

,

Y'N = VX

SUMMING NOOE
VOUT "V x
Rs
ROFF./
Vy~.

TO OTHER
SUBMULTIPLEXERS

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(6b) VOLTAGE OIVIOER EFFECT

TESTCONO'TIONS

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(6a) MOS SERIES SWITCHES

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O~~~~~-L-L-L~~~~~

-14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25-26 -27
VGG VOLTS
(6c) CHANGE IN RON WITH VGG

FIGURE 6. MOS Commutator Switching Impedances

AN28-4

tlOV

BULK OR SUBSTRATE

TC

GS

VIN = ±IV
~---~-VOUT

-6V

-IOV

(7.) EQUIVALENT CIRCUIT

(7b) TRANSIENT NOISE VOL TAGE

FIGURE 7. Transient Noise Generation

(another reason why the Figure 2 circuit is faster
than the Figure 1 circuit).
The transients can be much larger than signal voltages, so even the relatively small transients of a
low-VTH MOSFET can saturate the buffer amplifier.One of the ways that designers of discrete
commutators minimized transients at the summing
node was to drive adjacent channels with coincident turn-on and turn-off signals. In this way,
negative-going transients from the channels turning
on will partially cancel out positive-going transients from the channels turning off. When the
output amplifier is an integrator, the amounts of
energy pulled through the summing node will be
minimized by, in effect, being averaged out.
Coincident drive, discrete component circu its are
fairly complex and expensive. Essentially the same
effect is obtained in the Figure 2 commutator, at
much less cost. The TTL decoder selects channels
at such a high rate of speed that a channel is turning on while another channel is turning off. Transitions of the control voltage occur in less time than
the turn-on and turn-off delays of the MOSFETs.
So the transients are suppressed in a matter of
nanoseconds. I n fact, when the gate voltage is
going negative or positive simultaneously, the
transient is practically invisible at the output. That
is, the transient actually helps change the output
signal to the correct level more rapidly.
You might say that the high commutation rate
makes the high commutation rate possible, but it
is more pertinent to stress that the TTL decoder
could not directly control a high-V TH commutator. Low-impedance drivers are essential for high
commutation rates, because they quickly source
and sink transients. I n this respect, TTL integrated
circuits make almost ideal drivers.
In principle, the gate turning on and the gate turning off in a multichannel IC commutator are part
of a closed-loop circuit charging the gate capac-

itance. The noise energy that does get into the
summing node should be dissipated quickly to
improve the data channel's recovery time. The
energy is dissipated in the parallel combination of
the summing node resistance and channel-source
impedance. The RC time constant of the equivalent circuit in Figure 8 should be optimized to
obtain the maximum commutation frequency.
Fmax

= [(Rs/Rnode) Cnode] [(C 1 + C2 )/2C no de]
[V G1 -V GO] to 1

This equation relates the time constants, gate and
transient voltages and transient recovery tolerance.
V G 1 and V GO are the turncon and turn-off values
of V G; other terms are defined in Figure 8.

Rs
Vx o--"IJVtv--4I--"v\O"'""-....-

r

SUMMING
NOOE

__~_--O VOUT

o/~
C, = CGO
C2 = CGS

GATE

FIGURE 8. RC Network Governing Switching Frequency

HIGH-FREQUENCY NOISE CONTROL
In some cases, the analog input signal is AC rather
than DC. That is, it may fluctuate rapidly between
positive and negative values. This can vary the
effective values of V SG , RON and perhaps R oFF ,
and may also cause spurious charging or discharging of the MOSFET capacitance. The condition
results in output-voltage fluctuations due to the
appearance at the summing node of signal voltages from a channel that is supposed to be offa problem known as AC feedthrough or channelfeedthrough noise. The main cause is charge transfer through the gate-source and gate-drain capacitances of the turned-off MOSFETs.

AN28-5

Fortunately, most transducer voltage outputs are
below 10 kHz in frequency and simply using a
low-impedance gate driver prevents the problem.
The transients sink into the driver rather than go
to the output. A high signal source impedance
would make this technique more effective, but
would also cause larger transients in the turnedon channel, imposing longer recovery times and
slower commutation rates.
There is a simple detour around this impasse, too.
The dynamic impedance of the gate driver is allowed to approach a zero-ohm impedance when
the channel is turned off (Figure 9). Theoretically,
this will prevent any channel feedthrough noise at
signal frequencies up to 2 MHz. In practical circuits, signal frequency is limited by loadimpedance, but can usually be pushed above 1 MHz.
The driver impedance itself must also be low at
high frequencies, of course.

(90)

LOW·IMPEOANCE GATE ORIVER

interface. and its voltage levels are shown in Figure 10. The author used discrete components, but
all 16 resistors in the network could be made as a
thick-film printed circuit because the values are
not large and the tolerances are not critical.
TTL logic outputs are positive, while MOSFETs
require negative or positive gate biases to turn on
or off. The necessary voltage changes are made
with the capacitor in Figure 10.
Assume first that the TTL output is at a logic "1".
R1 will pull the decoder output up to V+ = +10V.
With Vss := +2V, there will be +8V across the capacitor, V G will be equal to V ss , and that channel
will be held off.
When the TTL output switches from a logic "1" to
a logic "0" level, the decoder output will go from
V+ = 10V to about OAV. Bias on the gate will
therefore drop from +2V to about -6V, turning
the channel on. The commutator is controlled,
then, by selecting the location of an "0" bit in the
decoder output and making all other outputs "1".
R1 is connected to a voltage higher than +6V to
assure that the TTL output rises rapidly during a
transition from logic "0" to logic "1". This is
needed for quick, clean turnoff of a channel (a
similar technique of interfacing TTL and lowV TH MOS digital circuits enables the MOS circuits
to operate at about twice the normal MOS rate).
The opposite transition, to the more negative
level, is normally quite fast and is assisted by the
excellent current-sinking capability of TTL.

-:d:"

:

RL

FIGURE 9. Zero-Impedance Driver Return
Prevents AC Feedthrough
Vss =VSULK

HIGH-SPEED SYSTEMS

=+2V

(lao) INTERFACE NETWORK (1 CHANNel)

All of these factors have been optimized in the
Figure 2 system. At 20 MHz, its accuracy with
V x = ±1 V is nearly as good as 99%. Source and
load impedance are made very low because Ro N is
not greater than about 200 ohms per channel. The
gate change is only 8V (from +2V to -6V), and
the high-speed TTL control makes the transients
coincide.

OFF
+IDV

DECODER
OUTPUT

I

I
I
I

I
I

I
I

+ 0.4V

10 TO 15 NS DElAY

-.J

ON
+O.4V

~

The 8-channel configuration shown can be the
building block of very large solid-state commutators. Each 4-channel MOSFET switch is a monolithic chip (National Semiconductor MM451). The
TTL channel selector is a decoder (DM7842)
designed to convert 4-bit binary-coded-decimal
inputs into decimal-number outputs. Only 8 outputs are needed here, so the decoder's fourth input is grounded.

FIGURE 10. High-Speed TTL-to-MOS Control Interface

The TTL outputs are translated to MOS control
signals with an interface network consisting of
identical passive circuits on each control line. An

Care must be taken to select TTL drivers that do
not break down when their outputs are puiled up
to +10V or +12V. The DM7842 has a diode in the

AN28-6

OFF

I VSULK ' - - - - - -...

ON
- VSULK -8V
(lab) VOLTAGE TRANSLATION

output stage that protects the output transistor at
high voltages, and other devices in the National
TTL family have similar output stages. These are
equivalent to Series 54 TTL. Suitable TTL control
logic can be assembled from other I Cs, but the
DM7842 is convenient because only one driver
chip is needed for every eight channels in the
commutator system.
There is a delay of 10 to 15 nanoseconds between
a transition in the TTL output and the switching
of a channel on or off, mainly due to the RC time
constant of the RC interface. However, the delay
occurs equally on all channels and does not affect
the commutation rate or significantly reduce the
50 ns sampling time permitted by a 20 MHz rate.
Commutator output can be kept synchronized to
any following data processing subsystem by putting a comparable delay in the line from the system clock to the processor.
The MM451 chip is also available with a DTL
monolithic driver in a flatpack. This hybrid IC,
the MH453, does not require an external interface network. It will operate at frequencies to
500 kHz and switch analog signals of ±10V under
direct control of TTL or DTL logic. The four
MOSFETs of the MM451 are connected in a dual
differe.ntial configuration, useful for combining
and comparing signal voltages.
AL~MOSCOMMUTATORS

Commutators built entirely of MOS devices need
not be limited to low-frequency operation, despite
their larger voltage swings and transients. The
system in Figure 2 has better than 99% accuracy at
1 MHz with Vx = ±10V when the previously
discussed characteristics of low-VTH devices in this
signal range are optimized.
Similar systems, optimized for smaller signalvoltage ranges, have not been built by the author
but it is reasonable to expect higher frequencies or
accuracies in such systems. Accuracy, of course,
would be further improved by operating the

optimized designs at lower than their maximum
frequency. Longer recovery times would be per·
mitted.
Each of the MM454 4-channel commutators contains four MOSFETs like those in the MM451 and,
in the same chip, a 2-bit MOS counter and decoder
for channel selection and all-channel blanking
( F i gu re 11).
As shown, the system samples the 16 channels
sequentially, much like a rotary driven mechanical
commutator. The MM454 is designed as a building
block for large sequential sampling systems. However, any particular channel could be selected
with ex te.rn aI output-gating logic. If random channel selection were the normal operating mode, the
MM451 and external selection logic can be used.
Two ranks of commutators, similar to Figure 1,
simplify the control logic. For example, one gate
driver would turn on channels A 1, B 1, C1 and D 1,
and a second driver would select channel A 1 by
turning on channel E 1-which takes a lot less
control circuitry than selecting lout of 16
channels directly and requires only one more
monolithic commutator.
Either way, a very critical system design requirement is to guarantee that only the selected channel
conducts during the sampling interval. The single
3-input NOR gate in Figure 1 accomplishes that.
Commutator C is used as the master element. It
divides down the 1 MHz clock signal through a 4: 1
countdown circuit, which is provided in the
MM454 to facilitate submultiplexing. Commutator
E's four channels therefore sequence at a 250 kHz
rate. Meanwhile, the four channels in commutators
A, B, C and D are each sequencing at 1 MHz. The
analog sequences through A 1, A2, A3 and A4 in
order when. E 1 is on, B 1 through B4 when E2 is
on, and so forth.
The 4: 1 count-down output of commutator E
(1/16 MHz) is fed back through the NOR gate to
the reset inputs of commutators A, Band D. The
reset every cycle keeps them in step with commu-

ANALOG
INPUTS

4
ANALOG
OUTPUT

CLOCK
INPUT

OUTPUT
4:1
COUNTDOWN

RESET·-----4I~------.....I

FIGURE.11. MM454 Four-Channel MOS Submultiplexer

AN28-7

tator C and therefore commutator E. The NOR
gate's output also can be used to maintain
synchronization of the commutator with other
signal processing systems.
ANALOG/DIGITAL SYSTEMS
Techniques developed, and being developed, to
directly couple bipolar and large-scale MOS pigital
circuits also depend heavily upon the lowering of
threshold voltages. A report compiling and detailing coupling techniques is in preparation. In general, the ability of the MaS digital circuit to accept small, positive transitions in signal voltage,
and to operate with smaller differentials in bias
and gate voltages are the critical requiremehts for
direct coupling.
Directly coupling MOS digital outputs to bipolar
logic also enhances operating speed, again because
impedances are lowered. Some of the high-speed
TTL/MOS hybrid systems that have been devel-

AN2S-S

oped are similar in principle to commutators,
except that V x is digital data and scores of
MOSF ET switching stages are used in each MOS
chip. One data-storage system built by the author
has achieved data transfer rates up to 16 MHz, by
multiplexing high-speed bipolar data into parallel
MaS storage circuits.
With all three classes of bipolar/MOS interfacesanalog/digital, logic/logic and logic/analog-now·
available, system designs can exploit more fully
the many speed/cost tradeoffs offered by hybrid
bipolar/MaS systems. Bipolar control logic and
MaS large-scale storage is an extremely efficient,
minimum cost combination suitable for mediumto-high-speed systems.

I n other words, low-threshold processing has enabled MOS to move out of the low-frequency
range and into the ranges where most modern
analog/digital systems operate.

»

z
I

December 1969

N
CD

(")

o

'"tJ

IC OP AMP BEATS FETs
ON INPUT CURRENT

»

s:'"tJ
aJ

m

»
-I
en

ABSTRACT
A monolithic operational amplifier having input
error currents in the order of 100 pA over a-55° C
to '125°C temperature range is described. Instead
of FETs, the circuit uses bipolar transistors with
current gains of 5000 so that offset voltage and
drift are not degraded. A power consumption of
1 mW at low voltage is also featured.

transistors match much better than F ETs with
typical offset voltages of 1 mV and drifts of
3fJ.Vfc.

5
~

~

A number of novel circuits that make use of the
low current characteristics of the amplifier are
given. Further, special design techniques required
to take advantage of these low currents are explored. Component selection and the treatme~t of
printed circuit boards is also covered.

-

10-7

LM709

10-3

a:
a:

B

...ffi

~

10-9 t--- j - - LM101A
I

0

~

~

10- 10

~

A year ago, one of the loudest complaints heard
about IC op amps was that their input currents
were too high. This is no longer the case. Today
ICs can provide the ultimate in performance for
many applications-even surpassing FET amplifiers.
F ET input stages have long been considered the
best way to get low input currents in an op amp.
Low-picoamp input currents can in fact be obtained at room temperature. However, this current,
which is the leakaJ]e current of the gate junction,
doubles every 10 C, so performance is severely
degraded at high temperatures. Another disadvantage is that it is difficult to match FETs
c1osely.l Unless expensive selection and trimming
techniques are used, typical offset voltages of
50 mV and drifts of 50 fJ.V fc must be tolerated.
Super gain transistors 2 are now challenging FETs.
These devices are standard bipolar transistors
which have been diffused for extremely high
current gains. Typically, current gains of 5000 can
be obtained at 1 fJ.A collector currents. This makes
it possible to get input currents which are competitive with F ETs. It is also possible to operate
these transistors at zero collector base voltage,
eliminating the leakage currents that plague the
FET. Hence they can provide lower error currents
at elevated temperatures. As a bonus, super gain

-

- :-+-...

C

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-75 -50 -25

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LM,108

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-,FET I--

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10- 11

INTRODUCTION

-

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"-Im

75 100 125

TEMPERATURE (Oe)

FIGURE 1. Comparing IC Op Amps With FET-Input
Amplifier

Figure 1 compares the typical input offset currents
of IC op amps and FET amplifiers. Although FETs
give superior performance at room temperature,
their advantage is rapidly lost as temperature
increases. Still, they are clearly better than early
IC amplifiers like the LM709. 3 Improved devices
like the LM101A, 4 equal FET performance over a'
-55°C to 125°C temperature range. Yet they use
standard transistors in the input stage. Super gain
transistors can provide more than an order of
magnitude improvement over the LM101A. The
LM108 uses these to equal FET performance over
a O°C to 70°C temperature range.
In applications involving 125°C operation, the
LM 108 is about two orders of magnitude better
than FETs. In fact, unless special precautions are
taken, overall circuit performance is often limited
by leakages in capacitors, diodes, analog switches
or printed circuit boards, rather than by the op
amp itself.
EFFECTS OF ERROR CURRENT
In an operational amplifier, the input current
produces a voltage drop across the source resis-

Reprinted from EEE, December 1969.

AN29-1

tance, causing a dc error. This effect can be minimized by operating the amplifier with equal
resistances on the two inputs. s The error is then
proportional to the difference in the two input
currents, or the offset current. Since the current
gains of monolithic transistors tend to match well,
the offset current is typically a factor of ten less
than the input currents.
:; 100

.§
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Vos =Vos + Rs los

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ffi

lk

10k

lOOk

1M

10M

INPUT RESISTANCE

100M

lG

(m

FIGURE 2. Illustrating The Effect Of Source Resistance
On Typical Input Error Voltage

Naturally, error current has the greatest effect in
high impedance circuitry. Figure 2 illustrates this
point. The offset voltage of the LM709 is degraded
significantly with source resistances greater than
10 kn. With the LM101 A this is extended to
source resistances high as 500 kn. The LM 108, on
the other hand, works well with source resistances
above 10 Mn.
High source resistances have an even greater effect
on the drift of an amplifier, as shown in Figure 3.
The performance of the LM709 is worsened with
sources greater than 3 kn. The LM 101 A holds out
to 100 kn sources, while the LM108 still works
well at 3 Mn.

G

;;

100

3ex:
Q
ex:

~

=
a:

10

c

1.0

L.---L._-'-_.L.----I_--L._-I

lk

10k

lOOk

1M

10M 100M

INPUT RESISTANCE

1G

(m

FIGURE 3. Degradation Of Typical Drift Characteristics
With High Source Resistances

It is difficult to include FET amplifiers in Figure 3
because their drift is initially 50 IlV fe, unless

AN29-2

they are selected and trimmed. Even though their
drift may be well controlled (5 IlV te) over a
limited temperature range, trimmed amplifiers
generally exhibit a much higher drift over a -55°e
to 125°e temperature range. At any rate, their
average drift rate WOUld, at best, be like that of the
LM101A where 125°e operation is involved.
Appl ications that require low error currents
include amplifiers for photodiodes or capacitive
transducers, as these usually operate at megohm
impedance levels. Sample-and-hold circuits, timers,
integrators and analog memories also benefit from
low error currents. For example, with the LM709,
worst case drift rates for these kinds of circuits is
in the order of 1.5V/sec. The LM108 improves this
to 3 m V /sec.-worst case over a-55° C to 125° e
temperature range. Low input currents are also
helpful in oscillators and active filters to get low
frequency operation with reasonable capacitor
values. The LM108 can be used at a frequency of
1 Hz with capacitors no larger than 0.01 IlF. In
logarithmic amplifiers, the dynamic range can be
extended by nearly 60 dB by going from the
LM709 to the LM108. In other applications,
having low error currents often permits an entirely
different design approach which can greatly simplify circuitry.
THE LM108
Figure 4 shows a simpl ified schematic of the
LM108. Two kinds of NPN transistors are used on
the IC chip: super gain (primary) transistors which
have a current gain of 5000 with a breakdown
voltage of 4 V and conventional (secondary) transistors which have a current gain of 200 with an
80V breakdown. These are differentiated on the
schematic by drawing the secondaries with a wider
base.
Primary transistors (a} and O2 ) are used for the
input stage; and they are operated in a cascode
connection with Os and 0 6 , The bases of Os and
0 6 are bootstrapped to the emitters of O} and O2
through 0 3 and 0 4 , so that the input transistors
are operated at zero collector-base voltage. Hence,
circuit performance is not impaired by the low
breakdown of the primaries, as the secondary transistors stand off the common mode voltage. This
configuration also improves the common mode
rejection since the input transistors do not see
variations in the common mode voltage. Further,
because there is no voltage across their collectorbase junctions, leakage currents in the input transistors are effectively eliminated.
The second stage is a differential ampl ifier using
high gain lateral PNPs (09 and a} 0).6 These devices have current gains of 150 and a breakdown
voltage of 80V. R} and R2 are the collector load
resistors for the input stage. 0 7 and 0 8 are diode
connected laterals which compensate for the

COMPENSATION

r-----~------~---+------------~._+__e~----v+
R2
20K

_--OUTPUT

INPUTS 01

+-41..........-+-----+------[

L-----~----------------_4~----~._--_4~----v-

FIGURE 4. Simplified Schematic Of The LM108

emitter-base voltage of the second stage so that its
operating current is set at twice that of the input
stage by R4 •
The second stage uses an active collector load
(Q15 and Q16) to obtain high gain. It drives a
complementary class-B output stage which gives a
substantial load driving capability. The dead zone
of the output stage is eliminated by biasing it on
the verge of conduction with Q 1 1 and Q 12 •

make high-impedance circuits fast; and low power
circuits are very resistant to being made fast. In
other respects, it was desirable to make the LM 108
as much like the LM101 A as possible.
2.0
1.5

1
~

~

.......

1.0

r-.....

........ r-!!AS

r-- .....

0.5

a::

-I--

a::

Two methods of frequency compensation are
available for the amplifier. In one a 30 pF capacitor is connected from the input to the output of
the second stage (between the compensation
terminals). This method is pin-compatible with the
LM101 or LM101A. It can also be compensated
by connecting a 100 pF capacitor from the output"
of the second stage to ground. This technique has
the advantage of improving the high frequency
power supply rejection by a factor of ten.
A complete schematic of the LM l08 is given in the
Appendix along with a description of the circuit.
This includes such essential features as overload
protection for the inputs and output.
PERFORMANCE
The primary design objective for the LM108 was
to obtain very low input currents without sacrificing offset voltage or drift. A secondary objective
was to reduce the power consumption. Speed was
of little concern, as long as it was comparable with
the LM709. This is logical as it is quite difficult to

B
~

~
~

0.15
0.10

""'-

.............

0.05

o

I'--

OFFSET

lMl08

-55 -35 -15

5

25 45

65 85 105 125

TEMPERATURE (OC)

FIGURE 5. Input Currents

Figure 5 shows the input current characteristics of
the LM108 over a ~55°C to 125°C temperature
range. Not only are the input currents low, but
also they do not change radically over temperature. Hence, the device lends itself to relatively
simple temperature compensation schemes, that
will be described later.
There has been considerable discussion about using
Darlington input stages rather than super gain transistors to obtain low input currents. 6 ,7 It is appropriate to make a few comments about that here.

AN29-3

Darlington inputs can give about the same input
bias currents as super gain transistors-at room
temperature. However, the bias current varies as
the square of the transistor current gain. At .low
temperatures, super gain devtces have a decided
advantage. Additionally, the offset current of
super gain transistors is considerably lower than
Darlingtons, when measured as a percentage of
bias current. Further, the offset voltage and offset
voltage drift of Darlington transistors is both
higher and more unpredictable.
Experience seems to tell the real truth about Darlingtons. Quite a few op amps with Darlington
input stages have been introduced. However, none
have become industry standards. The reason is that
they are more sensitive to variations in the manufacturing process. Therefore, satisfactory performance specifications can only be obtained by sacrificing the manufacturing yield.

volt of the supplies, which is especially important
when operating at low voltages. The output falls
off rapidly as the current increases above a certain
level and the short circuit protection goes into
effect. The useful output drive is limited to about
±2 rnA. It could have been increased by the addition of Darlington transistors on the output, but
this would have restricted the voltage swing at low
supply voltages. The amplifier, incidentally, works
with common mode signals to within a volt of the
supplies so it can be used with supply voltages as
low as ±2V.
120
180
100

~

80

135

<
c.:J

60

c.:J

40

...
C(

>

l>

r-

90

l>

C')

co.

...

~

Q

...:z:
~

Z

20

45

!

600

0
SOD

TA = -5So.C

~
I-

400

a:
a:

300

ffi

:;:)

c.o

~ 200
AA-

:;:)

en

-20

I

lOO

10

100

~

/

lk

10k lOOk

1M

10M

FREQUENCY (Hz)

-

TA = 2SoC

~

--.".""...

FIGURE 8. Open Loop Frequency Response

TA = 12SoC

LM1~8

10

15

20

SUPPL Y VOLTAGE (±V)

The open loop frequency response, plotted in
Figure 8, indicates that the frequency response is
about the same as that of the LM709 or the
LM101A. Curves are given for the two compensa-

FIGURE 6. Supply Current
Rl

The supply current of the LM108 is plotted as a
function of supply voltage in Figure 6. The operating current is about an order of magn itude lower
than devices like the LM709. Furthermore, it does
not vary radically with supply voltage which
means that the device performance is maintained
at low voltages and power consumption is held
down at high voltages.
15

....... ~

:;.:!:!.
c.:J

10

-, -,
"

R2

VOUT
R3

Rl Co

C'LRT+R2
Co =30 pF
a. Standard Compensation Circuit

Vs= ±15V

r-...

1\

R2

Rl

z

iiI-

LM l08

:;:)

A-

I-

:;:)

Q

1

~

TA = 12S0C
TA ~ 25 JC /'
TA ~ -S5°C
I

~

lM'

' / /v

./

./

V

I

VOUT

R3

Cs
*"100 PF

OUTPUT CURRENT (±mA)
b. Alternate Compensation Circuit

FIGUBE 7. Output Swing

The output drive capability of the circuit is illustrated in Figure 7. The output swings to within a

FIGURE 9. Compensation Circuits

tion circuits shown in Figure 9. The standard
compensation is identical to that of the LM101 or
LM101A. The alternate compensation scheme
gives much better rejection of high frequency
power supply noise, as will be shown later.
With unity gain compensation, both methods give
a 75-degree stability margin. However, the shunt
compensation has a 300 kHz small signal bandwidth as opposed to 1 MHz for the other scheme.
Because the compensation capacitor is not included on the IC chip, it can be tailored to fit the
application. When the amplifier is used only at low
frequencies, the compensation capacitor can be
increased to give a greater stability margin. This
makes the circuit less sensitive to capacitive loading, stray capacitances or improper supply bypassing. Overcompensation also reduces the high frequency noise output of the amplifier.
With closed-loop gains greater than one, the high
frequency performance can be optimized by
making the compensation capacitor smaller. If
unity-gain compensation is used for an amplifier
with a gain of ten, the gain error will exceed
1-percent at frequencies above 400 Hz. This can be
extended to 4 kHz by reducing the compensation
capacitor to 3 pF. The formula for determining
the minimum capacitor value is given in Figure 9a.
It should be noted that the capacitor value does
not really depend on the closed-loop gain. Instead,
it depends on the high frequency attenuation in
the feedback networks and, therefore,· the values
of R 1 and Rz . When it is desirable to optimize
performance at high frequencies, the standard
compensation should be used. With small capacitor
values, the stability margin obtained with shunt
compensation is inadequate for conservative designs.
The frequency response of an operational ampl ifier is considerably different for large output signals than it is for small signals. This is indicated in
Figure 10. With unity-gain compensation, the
small signal bandwidth of the LM108 is 1 MHz.
Yet full output swing cannot be obtained above
2 kHz. This corresponds to a slew rate of 0.3V /Ils.
Both the fu II-output bandwidth and the slew rate
can be increased by using smaller compensation
capacitors, as is indicated in the figure. However,
this is only applicable for higher closed loop gains.
The results plotted in Figure 10 are for standard
compensations. With unity gain compensation, the
same curves are obtained for the shunt compensation scheme.
Classica I op amp theory establ ishes output resistance as an important design parameter. This is not
true for IC op amps: The output resistance of
most devices is low enough that it can be ignored,
because they use class-Boutput stages. At low frequencies, thermal feedback between the output

16

~

,

12

t:l

z

....~

'Cf

4

IIII

TA =25°C
VS =±15V

IIII

Cf =3 pF

\

,

8

~
....
::::>
0

,

\

=30 pF

\

lMlo8

.........

""'"

oWllilillL..li:r:tt±l:y;;;;;;;j:¥
lOOk

10k

lk

1M

FREQUENCY (Hz)

FIGURE 10. Large Signal Frequency Response

and input stages determines the effective output
resistance, and this cannot be accounted for by
conventional design theories. Semiconductor manufacturers take care of this by specifying the gain
under full load conditions, which combines output
resistance with gain as far as it affects overall circuit performance. This avoids the fictitious problem that can be created by an amplifier with
infinite gain, which is good, that will cause the
open loop output resistance to appear infinite,
which is bad, although none of this affects overall
performance significantly.

103

§

...z

10

f

~

w

c(

~

!

....
....::::>~
0

~;;r-

lMlo8

2

101

'\

/

~'
/'

~

),\

~ ~ Cf~ 30pF
'J I~ AvAv=1000,
Cf =0 pF

\ I

10°
10-1

--'

V

/

' \1Av =1000,
. Cf =. 3D pF
II

lOUT

10-2
10

100

I

=25°C
=±1 rnA
Vs =±15V

TA

lk

10k

lOOk

1M

10M

FREQUENCY (Hz)

FIGURE 11. Closed Loop Output Impedance

The closed loop output impedance is, nonetheless,
important in some applications. This is plotted for
several operating conditions in Figure 11. It can be
seen that the output impedance rises to about
500n at high frequencies. The increase occurs
because the compensation capacitor rolls off the
open loop gain. The output resistance can be reduced at the intermediate frequencies, for closed
loop gains greater than one, by making the capacitor smaller. This is made apparent in the figure by
comparing the output resistance with and without
frequency compensation for a closed loop gain
of 1000.

AN29-5

The output resistance also tends to increase at low
frequencies. Thermal feedback is responsible for
this phenomenon. The data for Figure 11 was
taken under large-signal conditions with ± 15V
supplies, the output at zero and a ±1 mA current
swing. Hence, the thermal feedback is accentuated
more than would be the case for most applications.
In an op amp, it is desirable that performance
be unaffected by variations in supply voltage.
IC amplifiers are generally better than discretes
in this .respect because it is necessary for one
single design to cover a wide range of uses. The
LM108 has a power supply rejection which is
typically in excess of 100 dB, and it wi II operate with supply voltages from ±2V to ±20V.
Therefore, well-regulated supplies are unnecessary, for most applications, because a 20-percent variation has little effect on performance.

The overall performance of the LM108 is
summarized in Table 1 *. It is apparent from the
table and the previous discussion that' the device is ideally suited for applications that require low input currents or reduced power consumption. The speed of the amplifier is not
spectacular, but this is not usually a problem in
high-impedance circuitry. Further, the reduced
high frequency performance makes the amplifier
easier to use in that less attention need be paid
to capacitive loading, stray capacitances and
supply bypassing.
APPLI CA TI ONS
Because of its low input current, the LM108
opens up many new design possibilities. However, extra care must be taken in component
selection and the assembly of printed circuit
boards to take full advantage of its performance. Further, unusual design techniques must
often be applied to get around the limitations
of some components.

120

SAMPLE AND HOLD CIRCUITS

100

~
z

The holding accuracy of a sample and hold is
directly related to the error currents in the
components used. Therefore, it is a good circuit
to start off with in explaining the problems in-

80

0

i=

60

~a:

40

~

20

Zil

SAMPLE-----4..-.....,

-20
100

1k

10k

100k

1M

10M

OUTPUT

FREQUENCY (Hz)
INPUT-"'--'

C2

FIGURE 12. Power Supply Rejection

The story is different for high-frequency noise
on the supplies, as is evident from Figure 12.
Above 1 MHz, practically all the noise is fed
through to the output. The figure also demonstrates that shunt compensation is about ten
times better at rejecting high frequency noise
than is standard compensation. This difference
is even more pronounced with larger capacitor
values. The shunt compensation has the added
advantage that it makes the circuit virtually
unaffected by the lack of supply bypassing.
Power supply rejection is defined as the ratio
of the change in offset voltage to the change in
the supply voltage producing it. Using this definition, the rejection at low frequencies is unaffected by the closed loop gain. However, at
high frequencies, the opposite is true. The high
frequency rejection is increased by the closed
loop gain. Hence, an amplifier with a gain of
ten wi II have an order of magnitude better rejection than that shown in Figure 12 in the
vicinity of 100 kHz to 1 MHz.

30 pF

FIGURE 13. Sample And Hold Circuit

volved. Figure 13 shows one configuration for a
sample and hold. During the sample interval,
Q I is turned on, charging the hold capacitor,
C I , up to the value of the input signal. When
Q I is turned off, C I retains this voltage. The
output is obtained from an op amp that buffers
the capacitor so that it is not discharged by
any loading. In the holding mode, an error is
generated as the capacitor looses charge to
supply Circuit leakages. The accumulation rate
for error is given by
dV
dt

!.E.
CI

'

where dV /dt is the time rate of change in output voltage and IE is the sum of the input
current to the op amp, the leakage current of
the holding capacitor, board leakages and the
"off" current of the FET switch.

*See Appendix, page 19.

AN29-6

When· high-temperature operation is involved,
the FET leakage can limit circuit performance.
This can be minimized by using a junction
FET, as indicated, because commercial junction
FETs have lower leakage than their MOS counterparts. However, at 125°C even junction devices are a problem. Mechanical switches, such
as reed relays, are quite satisfactory from the
l)tandpoint of leakage. However, they are often
undesirable because they are sensitive to vibration, they are too slow or they require excessive drive power. If this is the case, the circuit
in Figure 14 can be used to eliminate the FET
leakage.

INPUT

OUTPUT

tT eflon, polyethylene or polycarbonate
dielectric capacitor
Worst case drift

less than 3 mV/sec

FIGURE 14. Sample And Hold That Eliminates Leakage
In FET Switches

When using P-channel MOS switches, the substrate must be connected to a voltage which is
always more positive than the input signal. The
sou rce-to-substrate junction becomes forward
biased if this is not done. The troublesome
leakage current of a MOSdevice occurs across
the su bstrate-to-drain junction. In Figure 14,
this current is routed to the output of the buffer amplifier through R 1 so that it does not
contribute to the error current.
The main sample switch is 0 1 , while O2 isolates the hold capacitor from the leakage of
0 1 • When the sample pulse is applied, both
FETs turn on charging C 1 to the input voltage.
Removing the pulse shuts off both FETs, and
.the output leakage of 0 1 goes through R 1 to
the. output. The voltage drop across R 1 is less
than 10 mV, so the substrate of O2 can be
bootstrapped to the output of the LM108.
Therefore, the voltage across the substrate-drain
junction is equal to the offset voltage of the
amplifier. At this low voltage, the leakage of
the F ET is reduced by about two orders of
magnitude.
It is necessary to use MOS switches when bootstrapping the leakages in this fashion. The gate
leakage of a MOS device is still negligible at

high temperatures; this is not the case with
junction FETs. If the MOS transistors have protective diodes on the gates, special arrangements
must be made to drive O2 so the diode does
not become forward biased.
In selecting the hold capacitor, low leakage is
not the only requirement. The capacitor must
also be free of dielectric polarization phenomena. 8 This rules out such types as paper, mylar,
electrolytic, tantalum or high-K ceramic. For
sma II capacitor values, glass or silvered-mica
ca pa c itors are recommended. For the larger
values, ones with teflon, polyethylene or polycarbonate dielectrics should be used.
The low input current of the LM108 gives a
drift rate, in hold, of only 3 mV /sec when a
1 J...LF hold capacitor is used. And this number is
worst case over the military temperature range.
Even if this kind of performance is not needed,
it may still be beneficial to use the LM 108 to
reduce the size of the hold capacitor. High
quality capacitors in the larger sizes are bulky
and expensive. Further, the switches must have
a low "on" resistance and be driven from a low
impedance source to charge large capacitors in a
short period of time.
If the sample interval is less than about 100 J...Ls,
the LM 108 may not be fast enough to work
properly. If this is the case, it is advisable to
substitute the LM102A,9 which is a voltage follower designed for both low input current and
high speed. It has a 30V /J...Ls slew rate and will
operate with sample intervals as short as 1 J...Ls.
When the hold capacitor is larger than 0.05 J...LF,
an isolation resistor should be included between
the capacitor and the input of the amplifier
(R 2 in Figure 14). This resistor insures that the
IC will not be damaged by shorting the output
or abruptly shutting down the supplies when
the capacitor is charged. This precaution is not
pe;;uliar to the LM 108 and should be observed
on any IC op amp.
INTEGRATORS
Integrators are a lot like sample-and-hold circuits and have essentially the same design problems. In an integrator, a capacitor is used as a
storage element; and the error accumulation
rate is again proportional to the input current
of the op amp.
Figure 15 shows a circuit that can compensate
for the bias current of the amplifier. A current
is fed into the summing node through R 1 to
supply the bias current. The potentiometer, R 2 ,
is adjusted so that this current exactly equals
the bias current, reducing the drift rate to zero.

AN 29-:-7

,
I''''
i

turns on Q 1 and Q2, shorting the integrating capacitor. When the switches turn off, the leakage
current of O2 is absorbed by R2 while 0 1 isolates
the output of O2 from the summing node. 0 1 has
practically no voltage across its junctions because
the substrate is grounded; hence, leakage currents
are negligible.

RJ
l50K

INPUT-"'V\I\r_e-------,
Rs

OUTPUT

FIGURE 15. Integrator With Bias Current Compensation

The diode is used for two reasons. First, it acts
as a regulator, making the compensation relatively insensitive to variations in supply voltage.
Secondly, the temperature drift of diode voltage
is approximately the same as the temperature
drift of bias current. Therefore, the compensation
is more effective if the temperature changes.
Over a O°C to 70°C temperature range, the compensation will give a factor of ten reduction in
input current. Even better results are achieved if
the temperature change is less.
Normally, it is necessary to reset an integrator to
establish the initial conditions for integration. Resetting to zero is readily accomplished by shorting
the integrating capacitor with a suitable switch.
However, as with the sample and hold circuits,
semiconductor switches can cause problems because of high-temperature leakage.
A connection that gets rid of switch leakages is
shown in Figure 16. A negative-going reset pulse
R2
lOOK

L..--f--e-RESET

>-....~I--OUTPUT

'Uland Q3 should not ha.e
internal gate-protection diodes,

FIGURE 16. Low Drift Integrator With Reset

AN29-8

The additional circuitry shown in Figure 16 makes
the error accumulation rate proportional to the
offset current, rather than th~ bias current. Hence,
the drift is reduced by roughly a factor of 10.
During the integration interval, the bias current of
the non-inverting input accumulates an error
across R4 and C2 just as the bias current on the
inverting input does across R 1 and C 1 • Therefore,
if R4 is matched with R 1 and C 2 is matched with
C 1 (within about 5 percent) the output wi II drift
at a rate proportional to the difference in these
currents. At the end of the integration interval, 0 3
removes the compensating error accumulated on
C2 as the circuit is reset.
I n applications involving large temperature
changes, the circuit in Figure 16 gives better results than the compensation scheme in
Figure 15-especially under worst case conditions.
Over a -55°C to 125°C temperature range, the
worst case drift is reduced from 3 mY/sec to
0.5 mV /sec when a 1 J..LF integrating capacitor is
used. If this reduction in drift is not needed, the
circuit can be simplified by eliminating R 4 , C2 and
0 3 and returning the non-inverting input of the
amplifier directly to ground.
In fabricating low drift integrators, it is again necessary to use high quality components and minimize leakage currents in the wiring. The comments
made on capacitors in connection with the
sample-and-hold circuits also apply here. As an
additional precaution, a resistor should be used to
isolate the inverting input from the integrating
capacitor if it is larger than 0.05 J..LF. This resistor
prevents damage that might occur when the supplies are abruptly shut down while the integrating
capacitor is charged.
Some integrator applications require both speed
and low error current. The output amplifiers for
photomultiplier tubes or solid-state radiation detectors are examples of this. Although the LM 108
is relatively slow, there is a way to speed it up
when it is used as an inverting amplifier. This is
shown in Figure 17.
The circuit is arranged so that the high-frequency
gain characteristics are determined by A 2 , while
Al determines the dc and low-frequency characteristics. The non-inverting input of Al is connected to the summing node through R 1. Al is operated as an integrator, going through unity gain at
500 Hz. Its output drives the non-inverting input

01

Rs
INPUT-.JVVv-_~-----------tt----i

R5
ZK

1---_

R1
150K

C1
0.002 !1F

C3
0.002 !1F

R2
1M

RJ
1M

FIGURE 17. Fast Integrator

of A 2 . The inverting input of A2 is also connected
to the summing node through C 3 . C 3 and R3 are
chosen to roll off below 750 Hz. Hence, at fre·
quencies above 750 Hz, the feedback path is directly around A 2 , with Al contributing little.
Below 500 Hz, however, the direct feedback path
to A2 rolls off; and the gain of Al is added to that
of A 2 •
The high frequency amplifier, A 2 , is an LM 101 A
connected with feed-forward compensation. I 0 It
has a 10 MHz equivalent small-signal bandwidth, a
1OV /,us slew rate and a 250 kHz large-signal bandwidth, so these are the high-frequency characteristics of the complete amplifier. The bias current of
A2 is isolated from the summing node by C3 .
Hence, it does not contribute to the dc drift of the
integrator. The inverting input of Al is the only dc
connection to the summing junction. Therefore,
the error current of the composite amplifier is
equal to the bias current of AI.
If A2 is allowed to saturate, A I wi II then start
towards saturation. If the output of Al gets far off
zero, recovery from saturation will be slowed drastically. This can be prevented by puttin~ zener
clamp diodes across the integrating capacitor. A
suitable clamping arrangement is shown in
Figure 17. D I and D2 are included in the clamp
circuit along with Rs to keep the leakage currents
of the zeners from introducing errors.
In addition to increasing speed, this circuit has
other advantages. For one, it has the increased output drive capability of the LM101A. Further,

thermal feedback is virtually eliminated because
the LM 108 does not see load variations. Lastly,
the open loop gain is nearly infinite at low frequencies as it is the product of the gains of the
two amplifiers.

SINE WAVE OSCILLATOR
Although it is comparatively easy to build an oscillator that approximates a sine wave, making one
that delivers a high-purity sinusoid with a stable
frequency and amplitude is another story. Most
satisfactory designs are relatively complicated and
require individual trimming and temperature compensation to make them work. In addition, they
generally take a long time to stabilize to the final
output amplitude.
A unique solution to most of these problems is
shown in Figure 18. Al is connected as a two-pole
low-pass active filter, and A2 is connected as an
integrator. Since the ultimate phase lag introduced
by the amplifiers is 270 degrees, the circuit can be
made to oscillate if the loop gain is high enough at
the frequency where the lag is 180 degrees. The
gain is actually made somewhat higher than is required for oscillation to insure starting. Therefore,
the amplitude builds up until it is limited by some
nonlinearity in the system.
Amplitude stabilization is accomplished with zener
cia mp diodes, D I and D2 . Th is does introdu ce d istortion, but it is reduced by the subsequent low
pass filters. If D I and D2 have equal breakdown
voltages, the resulting symmetrical clipping will

AN29-9

C2

0.021'F
1%

C5

30 pF

fa = 1 Hz

R2
22M
1%

01

6.3V

R4
50K

02

6.3V

FIGURE 18. Sine Wave Oscillator

virtually eliminate the even-order harmonics. The
dominant harmonic is then the third, and this is
about 40 dB down at the output of A I and about
50 dB down on the output of A2 . This means that
the total harmonic distortion on the two outputs
is 1 percent and 0.3 percent, respectively.

but uses capacitors in the order of 0.01 fJ.F. This
makes it much easier to find temperature-stable
precision capacitors. However, some judgment
must be used as large value resistors with low
temperature coefficients are not exactly easy to
come by. *

The frequency of oscillation and the oscillation
threshold are determined by R I , R 2 , R 3 , C I , C2
and C 3 • Therefore precision components with low
temperature coefficients shou Id be used. If R 3 is
made lower than shown, the circuit will accept
looser component tolerances before dropping out
of oscillation. The start up will also be quicker.
However, the price paid is that distortion is increased. The value of R4 is not critical, but it
should be made much smaller than R2 so that the
effective resistance at R2 does not drop when the
clamp diodes conduct.

The LM108s are useful in this circuit for output
frequencies up to 1 kHz. Beyond that, better performance can be realized by substituting an
LM102A for Al and an LM101A with feedforward compensation for A2 . The improved
high-frequency response of these devices extends
the operating frequency out to 100 kHz.
CAPACITANCE MULTIPLIER
Large capacitor values can be eliminated from
most systems just by raising the impedance levels,
if suitable op amps are available. However, sometimes it is not possible because the impedance
levels are already fixed by some element of the
system like a low impedance transducer. If this is
the case, a capacitance multiplier can be used to;
increase the effective capacitance of a small capacitor and couple it into a low impedance system.

The output amplitude is determined by the breakdown voltages of 0 I and O2 , Therefore, the clamp
level should be temperature compensated for
stable operation. Diode-connected (collector shorted to base) NPN transistors with an emitter-base
breakdown of about 6.3V work well, as the positive temperature coefficient of the diode in reverse
breakdown nearly cancels the negative temperature coefficient of the forward-biased diode. Added advantages of using transistors are that they
have less shunt capacitance and sharper breakdowns than conventional zeners.

Previously, Ie op amps could not be used effectively as capacitance multipliers because the equivalent leakages generated due to offset current were
significantly greater than the leakages of large
tantalum capacitors. With the LM108, this has
changed. The circuit shown in Figure 19 generates

The LM108 is particularly useful in this circuit at
low frequencies, since it permits the use of small
capacitors. The circuit shown oscillates at 1 Hz,

*Large-value resistors are available from Vic1oreenlnstrument, Cleveland, Ohio and Pyrofilm Resistor Co.,
Whippany, New Jersey.

AN29-10

an equivalent capacitance of 100,000 IlF with a
worst case leakage of SIlA-over a -55°C to
125° C temperature range.

C=~Cl
IL

=

R2
10M

Vos + ~l Rl

Rs = R3

C2
30 pF

R3
lK
1%

...--01\""',----__-

~C

Rl
Cl
10J.l

F

J

10M
1%

FIGURE 19. Capacitance Multiplier

The performance of the circuit is described by the
equations given in Figure 19, where C is the effective output capacitance, IL is the leakage current
of this capacitance and Rs is the series resistance
of the multiplied capacitance. The series resistance
is relatively high, so high-Q capacitors cannot be
realized. Hence, such applications as tuned circuits
and filters are ruled out. However, the multiplier
can still be used in timing circuits or servo compensation networks where some resistance is
usually connected in series with the capacitor or
the effect of the resistance can be compensated
for.

sistor matching and by balancing of the source resistances. A 1-percent deviation in anyone of the
resistor values reduces the common mode rejection
to 46 dB for a closed loop gain of 1, to 60 dB for a
gain of 10 and to SO dB for a gain of 100.
Clearly, the only way to get high input impedance
is to use very large resistors in the feedback network. The op amp must operate from a source
resistance which is orders of magnitude larger than
the resistance of the signal source. Older IC op
amps introduced excessive offset and drift when
operating from higher resistances and could not be
used successfully. The LM 1OS, however, is rela. tively unaffected by the large resistors, so this
approach can sometimes be employed.
With large input resistors, the feedback resistors,
R3 and R4 , can get quite large for higher closed
loop gains. For example, if R 1 and R2 are 1 Mr2,
R3 and R4 must be 100 Mr2 for a gain of 100. It is
difficult to accurately match resistors that are this
high in value, so common mode rejection may
suffer. Nonetheless, anyone of the resistors can be
trimmed to take out common mode feedthrough
caused either by resistor mismatches or the amplifier itself.

Rl

R3

INPUTS

One final point iSJhat the leakage current of the
multiplied capacitance is not a function of the
applied voltage. It persists even with no voltage on
the output. Therefore, it can generate offset errors
in a circuit, rather than the scaling errors caused
by conventional capacitors.

OUTPUT
R2

R'N = R2 + R4 ~

+
-#V\"-...
---t

INSTRUMENTATION AMPLIFIER
In many instrumentation applications there is frequently a need for an amplifier with a highimpedance differential input and a single ended
output. Obvious uses for this are amplifiers for
bridge-type signal sources such as strain gages, temperature sensors or pressure transducers. General
purpose op amps have satisfactory input characteristics, but feedback must be added to determine
the effective gain. And the addition of feedback
can drastically reduce the input resistance and
degrade common mode rejection.
Figure 20 shows the classicalop amp circuit for a
differential amplifier. This circuit has three main
disadvantages. First, the input resistance on the
inverting input is relatively low, being equal to R 1.
Second, there usually is a large difference in the
input resistance of the two inputs, as is indicated
by the equations on the schematic. Third, the
common mode rejection is greatly affected by re-

FIGURE 20. Feedback Connection For a Differential
Amplifier

Another problem caused by large feedback resistors is that stray capacitance can seriously affect
the high frequency common mode rejection. With
1 Mr2 input resistors, a 1 pF mismatch in stray
capacitance from either input to ground can drop
the common mode rejection to 40 dB at 1500 Hz.
The high frequency rejection can be improved at
the expense of frequency response by shunting R3
and R4 with matched capacitors.
With high impedance bridges, the feedback resistances become prohibitively large even for the
LM 1OS, so the circuit in Figure 20 cannot be used.
One possible alternative is shown in Figure 21. R2
and R3 are chosen so that their equivalent parallel
resistance is equal to R 1. Hence, the output of the
ampl ifier wi II be zero when the bridge is balanced.

AN29-1.1

r - - -....-v+

OUTPUT

This circuit has the same sensitivity to resistor
matchin~ as the previous circuits, with a 1 percent
mismatch between two resistors lowering the common mode rejection to 80 dB. However, matching
is more easily accomplished because of the lower
resistor values. Further, the high frequency common mode rejection is less affected by stray capacitances. The high frequency rejection is limited,
though, by the response of AI'
LOGARITHMIC CONVERTER

FIGURE 21. Amplifier For Bridge Transducers

When the bridge goes off balance, the op amp
maintains the voltage between its input terminals
at zero with current fed back from the output
through R 3' This circuit does not act like a true
differential amplifier for large imbalances in the
bridge. The voltage drops across the two sensor
resistors, SI and S2, become unequal as the bridge
goes off balance, causing some non-linearity in the
transfer function. However, this is not usually
objectionable for small signal swings.

Rl
lOOK
0.1%

R2
lK
0.1%

-

_

R3
lK
0.1%

R4
lOOK
0.1%

INPUTS-+

Rl

=R4; R2 =R3

Av = 1 + ~

FIGURE 22. Differential Input Instrumentation Amplifier

Figure 22 shows a true differential connection that
has few of the problems mentioned previously. It
has an input resistance greater than 10 10 [2, yet it
does not need large resistors in the feedback circuitry. With the component values shown, Al is
connected as a non-inverting amplifier with a gain
of 1.01; and it feeds into A2 which has an inverting gain of 100. Hence, the total gain from the
input of Al to the output of A2 is 101, which is
equal to the non-inverting gain of A 2 • If all the
resistors are matched, the circuit .responds only to
the differential input signal-not the common
mode voltage.

AN29-12

A logarithmic amplifier is another circuit that can
take advantage of the low input current of an op
amp to increase dynamic range. Most practical log
converters make use of the logarithmic relationship between the emitter-base voltage of standard
double-diffused transistors and their collector
current. This logarithmic characteristic has been
proven true for over 9 decades of collector current. The only problem involved in using transistors as logging elements is that the scale factor has
a temperature sensitivity of 0.3 percentf C. However, temperature compensating resistors have
been developed to compensate for this characteristic, making possible log converters that are accurate over a wide temperature range.
Figure 23 gives a circuit that uses these techniques.
Q 1 is the logging transistor, while Q2 provides a
fixed offset to temperature compensate the
emitter-base turn on voltage of Ql' Q2 is operated
at a fixed collector current of 10 IlA by A 2 , and
its emitter-base voltage is subtracted from that of
Q 1 in determining the output voltage of the circuit. The collector current of Q 2 is established by
R 3 and V+ through A2 .
The collector current of Q 1 is proportional to the
input current through Rs and, therefore, proportional to the input voltage. The emitter-base voltage of Q 1 varies as the log of the input voltage.
The fixed emitter-base voltage of Q 2 subtracts
from the voltage on the emitter of Q 1 in determining the voltage on the top end of the temperaturecompensating resistor, SI'
The signal on the top of SI will be zero when the
input current is equal to the current through R3 at
any temperature. Further, this voltage will vary
logarithmically for changes in input current, although the scale factor will have a temperature
coefficient of -0.3%fc. The output of the converter is essentially multiplied by the ratio of R 1
to SI' Since SI has a positive temperature coefficient of 0.3 percentfC, it compensates for the
change in scale factor with temperature.
In this circuit, an LM101A with feedforward compensation is used for A2 since it is much faster
than the LM108 used for AI' Since both amplifiers are cascaded in the overall feedback loop, the
reduced phase shift through A2 insures stability.

V+ = 15V

2N2920

~----t.---.... 02

Rs
INPUT~M..--4t----U---.......,

A3*
1.5M
1%

A2
2K

Al
15.7K
1%
A4*
1.5M
C4
150 pF
OUTPUT
CI
300 pF
10 nA < liN < I mA
Sensitivity is I V per decade.

tAvailablefromTel Labs, Inc.,
Manchester, N.H., Type OHf.

*Determines current for zero
crossing on output: 10 MA
as shown.

FIGURE 23. Temperature

Compensated One-Quadrant Logarithmic Converter

Certain things must be considered in designing this
circuit. For one, the sensitivity can be changed by
varying R l' But R 1 must be made considerably
larger than the resistance of SI for effective temperature compensation of the scale factor. Q 1 and
O 2 should also be matched devices in the same
package, and SI should be at the same temperature as these transistors. Accuracy for low input
currents is determined by the error caused by the
bias current of AI' At high currents, the behavior
of Q 1 and O 2 limits accuracy. For input currents
approaching 1 mA, the 2N2920 develops logging
errors in excess of 1 percent. If larger input currents are anticipated, bigger transistors must be
used; and R2 should be reduced to insure that A2
does not saturate.
TRANSDUCER AMPLI FIERS
With certain transducers, accuracy depends on the
choice of the circuit configuration as much as it
does on the quality of the components. The amplifier for photodiode sensors, shown in Figure 24,
illustrates this point. Normally, photodiodes are

operated with reverse voltage across the junction.
At high temperatures, the leakage currents can
approach the signal current. However, photodiodes
deliver a short-circuit output current, unaffected
by leakage currents, which is not .significantly
lower than the output current with reverse bias.
The circuit shown in Figure 24 responds to the
short-circuit output current of the photodiode.
Since the voltage across the diode is only the offset voltage of the amplifier, inherent leakage is
reduced by at least two orders of magnitude. Neglecting the offset current of the amplifier, the
output currerit of the sensor is multiplied by Rl
plus R2 in determining the output Voltage.
Figure 25 shows an amplifier for high-impedance
ac transducers like a piezoelectric accelerometer.
These sensors normally require a high-inputresistance amplifier. The LM 108 can provide input
resistances in the range of 10 to 100 MQ, using
conventional circuitry. However, conventional
designs are sometimes ruled out either because
r - - -....-------t~ OUTPUT

Al
SM
1%

CI
10MF

SI

c::::::J

TAANSOUCEA

J
FIGURE 24. Amplifier For Photodiode Sensor

FIGURE 25. Amplifier For Piezoelectric.Transducers

AN29.;..13

large resistors cannot be used or because prohibitively large input resistances are needed.
Using the circuit in Figure 25, input resistances
that are orders of magnitude greater than the
values of the dc return resistors can be obtained.
This is accomplished by bootstrapping the resistors
to the output. With this arrangement, the lower
cutoff frequency of a capacitive transducer is determined more by the RC product of R 1 and C 1
than it is by resistor values and the equivalent
capacitance of the transducer.
RESISTANCE MULTIPLICATION

When an inverting operational amplifier must have
high input resistance, the resistor values required
can get out of hand. For example, if a 2 Mr2 input
resistance is needed for an amplifier with a gain
of 100, a 200 Mr2feedback resistor is called for.
This resistance can, howev~r, be reduced using the
circuit in Figure 26. A divider with a ratio of 100
to 1 (R 3 and R4 ) is added to the output of the
amplifier: Unity-gain feedback is applied from the
output of the divider, giving an overall gain of 100
using only 2 Mr2 resistors.
This circuit does increase the offset voltage somewhat~ The output offset voltage is given by

CURRENT SOURCES

Although there are numerous ways to make current sources with op amps, most have limitations
as far as their application is concerned. Figure 27,
however, shows a current source which is fairly
flexible and has few restrictions as .far as its use is
concerned. It supplies a current that is proportional to the input voltage and drives a load referred to ground or any voltage within the outputswing capability of the amplifier.
Rl

RJ

2M
1%

1M
1%

lOUT

=

~IV~~

RJ = R4 + R5
Rl = R2

R5
2K
1%

R4
1M
1%

FIGURE 27. Bilateral Current Source

With the output grounded, it is relatively obvious
that the output current will be determined by Rs
and the gain setting of the op amp, yielding
The offset voltage is only multiplied by Av + 1 in
a conventional inverter. Therefore, the circuit in
Figure 26 multiplies the offset by 200, instead
of 101. This multiplication factor can be reduced
t0110 by increasing R2 to 20Mr2 and R3
to 5.55k.

Rl

R2

2M
1%

2M
1%

RJ
505
1%

INPUT.- -vVY-tI~-""",..,..--tl~WI,r-,

R4
50K
1%

R2>Rl
R2» RJ
Av

= R2~~JR; R4)

OUTPUT

R5
1M

J

Cl
100P
f

FIGURE 26. Inverting Amplifier With High Input
Resistance

Another disadvantage of the circuit is that four
resistors determine the gain, instead of two.
Hence, for a given resistor' tolerance, the worstcase gain deviation is greater, although this is
probably· more than offset by the ease of getting
better tolerances in the low resistor values.

AN29-14

When the output is not at zero, it would seem that
the current through R2 and R4 would reduce
accu racy. Nonetheless, if R 1 = R2 and
R3 = R4 + Rs, the output current will be independent of the output voltage. For
R 1 + R 3 >> As, the output resistance of the circuit is given by

where.R is anyone of the feedback resistors (R 1,
R2 , R 3 or R4 ) and ~R is the incremental change
in the resistor value from design center. Hence, for.
the circu it in Figure 27, a 1 percent deviation in
one of the resistor values will drop the output.
resistance of 200 kr2. Such errors can be trimmed
out by adjusting one of the feedback resistors. In
design, it is advisable to make the feedback resistors as large as possible. Otherwise, resistor tolerances become even more critical.
The circuit must be driven from a source resistance
which is low by comparison to R 1, since this resistance will imbalance the circuit and affect both
gain and output resistance. As shown, the circuit

gives a negative output current for a positive input
voltage. This can be reversed by grounding the
input and driving the ground end of R2 • The
magnitude of the scale factor will be unchanged as
long as R4
Rs.

+5V

»

VOLTAGE COMPARATORS
Like most op amps, it is possible to use the LM108
as a voltage comparator. Figure 28 shows the
device used as a simple zero-crossing detector. The
inputs of the Ie are protected internally by backFIGURE 29. Voltage Comparator With Output Buffer
Rl
1M

INPUT-~"",,"".::.j

FIGURE 28. Zero Crossing Detector

to-back diodes connected between them, therefore, voltages in excess of 1 V cannot be impressed
directly across the inputs. This problem is taken
care of by R 1 which limits the current so that
input voltages in excess of 1 kV can be tolerated.
If absolute accuracy is required or if R 1 is made
much larger than 1 MQ, a compensating resistor of
equal value should be inserted in series with. the
other input.
In Figure 28, the output of the op amp is clamped
so that it can drive DTL or TTL directly. This is
accomplished with a clamp diode on pin 8. When
the output swings positive, it is clamped at the
breakdown voltage of the zener. When it swings
negative, it is clamped at a diode drop below
ground. If. the 5V logic supply is used as a positive
supply for the amplifier, the zener can be replaced
with an ordinary silicon diode. The maximum fan
out that can be handled by the device is one for
standard DTL or TTL under worst case conditions.
As might be expected, the LM 108 is not very fast
when used as a comparator. The response time is
up in the tens of microseconds. An LM103 11 is
recommended for D 1, rather than a conventional
alloy zener, because it has lower capacitance and
will not slow the circuit further. The sharp breakdown of the LM 103 at low currents is also an
advantage as the current through the diode in
clamp is only 10,uA.

The LM108 can also be used as a differential comparator, going through a transition when two input
voltages are equal. However, resistors must be
inserted in series with the inputs to limit current
and minimize loading on the signal sources when
the input-protection diodes conduct. Figure 29
also shows how a PNP transistor can be added on
the output to increase the fan out to about 20
with standard DTL or TTL.

POWER BOOSTER
The LM108, which was designed for low power
consumption, is not able to drive heavy loads.
However, a relatively simple booster can be added
to the output to increase the output current to
±50 mA. This circuit, shown in Figure 30, has the
added advantage that it swings the output up to
the supplies, within a fraction of a volt. The increased voltage swing is particularly helpful in low
voltage circuits.

_ - - -.....-V+

OUTPUT

' - - - - - - - 4 1...... V·

FIGURE 30. Power Booster

Figure 29 shows a comparator for voltages of
opposite polarity. The output changes state when
the voltage on the junction of R 1 and R2 is equal
to VT H' Mathematically, this is expressed by

In Figure 30, the output transistors are driven
from the supply leads of the op amp. It is important that R 1 and R2 be made low enough so 0 1
and O 2 are not turned on by the worst case quiescent current of the amplifier. The output of the op
amp is loaded heavily to ground with R3 and R4 •

AN29-15

When the output swings about 0.5V positive, the
increasing positive supply current will turn on Q 1
which pulls up the load. A similar situation occurs
with Q 2 for negative output swings.

vapor when operating in the vicinity of O°C. This
can usually be accomplished by coating the board
as mentioned above.
GUARDING

The bootstrapped shunt compensation shown in
the figure is the only one that seems to work for
all loading conditions. This capacitor, C 1 , can be
made inversely proportional to the closed loop
gain to optimize frequency response. The value
given is for a unity-gain follower connection. C2 is
also required for loop stability.
The circuit does have a dead zone in the open loop
transfer characteristic. However; the'jow frequency gain is high enough so that it can be neglected.
Around 1 kHz, though, the dead zone becomes
quite noticeable.
Current limiting can be incorporated into the circuit by adding resistors in series with the emitters
of Q 1 and Q 2 because the short circuit protection
of the LM1081imits the maximum voltage drop
across R1 and R2 •

Even with properly cleaned and coated boards,
leakage currents are on the verge of causing
trouble at 125°C. The standard pin configuration
of most IC op amps has the input pins adjacent to
pins which are at the supply potentials. Therefore,
it is advisable to employ guarding to reduce the
voltage difference between the inputs and adjacent
metal runs.

COMPENSATION

", f)

OUTPUT ' 6

7

1

BOARD CONSTRUCTION

As indicated previously, certain precautions must
be observed when building circuits that are sensitive to very low currents. ·If proper care is not
taken, board leakage currents can easily become
much larger than the error currents of the op amp.
To prevent this, it is necessary to thoroughly .clean
printed Circuit boards. Even experimental breadboards must be· cleaned with trichloroethlene or
alcohol -to remove solder fluxes, and blown dry
with compressed air. These fluxes may be insulators at low impedance ·Ievels-like in electric
motors-but they certainly are not in high impedance circuits. In addition to causing gross errors,
their presence can make the circuit behave
erratically, especially as the temperature is
changed.
At elevated temperatures, even the leakage of
clean boards can be a headache. At 125°C the
leakage resistance between adjacent runs on a
printed circuit board is about 10 11 n (0.05-inch
separation parallel for 1 inch) for high quality
epoxy-glass boards that have been properly cleaned. Therefore, the boards can easily produce error
currents in the order of 200 pA and much more if
they become contaminated. Conservative practice
dictates that the boards be coated with epoxy or
silicone rubber after cleaning to prevent contamination. Silicone rubber is the easiest to use. However, if the better durability of epoxy is needed,
care must be taken to make sure that it gets
thoroughly cured. Otherwise, the epoxy will ma.ke
high temperature leakage much worse.
Care must also be exercised to insure that the circuit board is protected from condensed water

AN29-16

BOTTOM VIEW

FIGUaE31; Printed Circuit Layout For Input Guarding
With TO-5 Package

A board· I.ayout ,that includes input guarding is
shown in Figure 31 for the eight lead TO-5 package. A ten-,Iead pin circle is used, and the leads of
thel.C are. formed so that the holes adjacent to the
inputs are vacant. when it is inserted in the board.
The guard, which is a conductive ring surrounding
the inputs, is then connected to a low impedance
point that is at the same potential as the inputs.
The leakage currents from the pins at the supply
potentials are absorbed by the guard. The voltage
difference between the guard and the inputs can
be made approximately equal to the offset voltage,
reducing the effective leakage by more than three
Qrders of magnitude. If the leads of the integrated
circuit, or other components connected to the
input, go through the board, it may be necessary
to guard both sides.

Figure 32 shows how the guard is committed on
the more-common op amp circuits. With an integrator or inverting amplifier, where the inputs are
close to ground potential, the guard is simply
grounded. With the voltage follower, the guard is
bootstrapped to the output. If it is desirable to put
a resistor in the inverting input to compensate for
the source resistance, it is connected as shown in
Figure 32b.

Rl
INPUT

Guarding a non-inverting amplifier is a little more
complicated. A low impedance point must be
created by using relatively low value feedback resistors to determine the gain (R 1 and R2 in
Figure 32c). The guard is then connected to the
junction of the feedback resi stors. A resi stor, R 3,
can be connected as shown in the figure to compensate for large source resistances.

R2

-A"AI\r.....~-~w"'""--..,

OUTPUT

With the dual-in-line and flat packages, it is far
more difficult to guard the inputs, if the standard
pin configuration of the LM709 or LM101A is
used, because the pin spacings on these packages
are fixed. Therefore, the pin configuration of the
LM108 was changed, as shown in Figure 33.

a.lnvertlOg Amplifier

CONCLUSIONS
OUTPUT

IC op amps are now available that equal the input
current specifications of FET amplifiers in all but
the most restricted temperature range applications.
At operating temperatures above 85°C, the IC is
clearly superior as it uses bipolar transistors that
make it possible to eliminate the leakage currents
that plague FETs. Additionally, bipolar transistors
match better than FETs, so low offset voltage and
drifts can be obtained without expensive adjustments or selection. Further, the bipolar devices
lend themselves more readily to low-cost monolithic construction.

Cl
, b. Follower

R2

OUTPUT

These amplifiers open up new application areas
and vastly improve performance in others. For
example, in analog memories, holding intervals can
be extended to minutes, even where -55°C to
125°C operation is involved. Instrumentation
amplifiers and low frequency waveform generators
also benefit from the low error currents.

Rl

Cl
c.Non·lnvertingAmplifier

FIGURE 32. Connection Of Input Guards

NO CONNECTION

NO CONNECTION

COMPENSATION

BALANCE /COMPENSATI ON
INPUT

.C:=-J.::......--I

y+

INPUT

C:::J=----I

OUTPUT

Y-

BALANCE

>COMPENSATION

NO CONNECTION
GUARO
INPUT .r:::::J.":""-I
INPUT.s:::::::::Jo~-I

Y-

NOTE: Pin 6 connected to bottom of package

NOTE: Pin 5 Connected to bottom of package.

TOP YIEW

TOP YIEW

14

14
13
12 COMPENSATION

BALANCE / COMPENSATION 3

OUTPUT

GUARO

COMPENSATION

2

13

GUARO

3

12 COMPENSATION
y+

INPUT

4

11

y+

INPUT

4

11

INPUT

5

10 OUTPUT

INPUT

5

10 OUTPUT

Y-

6

9

GUARO

6

Y-

7

BALANCE

NOTE: Pin 6 connected to bottom of package.

NOTE: Pin 7 connected to bottom of package

TOP YIEW

TOP YIEW

FIGURE 33. Comparing Connection Diagrams Of The

LM101A And LM108, Showing Addition Of Guarding

AN29-17

When operating above 85°C, overall performance
is frequently .limited by components other than
the op amp, unl.ess certain precautions are oLserved. It is geflerally necessary to redesign circuits
using semiconductor switches to reduce the effect
of their leakage currents. Further, high quality
capacitors must be used, and care must be exercised in selecting large value resistors. Printed circuit board leakages can also be troublesome unless
the boards are properly treated, And above 100°C,
it is almost mpndatory to employ guarding on the
boards to protect the inputs, if the full potential
of the amplifier is to be realized.

compensate for the current gain falloff of the
input transistors at low temperatures without
creating stability problems at high temperatures.
The biasing circuitry for the input current source
is nearly identical to that in the LM101A, and a
complete description is given in Reference 4. However, a brief explanation follows.

A complete schematic of the LM108 is given in
Figure A 1. A description of the basi.c circuit is
presented along with a simplified schematic earlier
in the text. The purpose of this Appendix is to
explain some of the more subtle features of the
design.

A collector F ET, 6 O2 3, wh ich has a satu rati on
current of about 30 pA, establishes the collector
current of 0 24 , This FET provides the initial
turn-on current for the circuit and insures starting
under all conditions. The purpose of R 14 is to
compensate for production and temperature variations in the FET current. It is a collector resistor
(indicated by the T through it) made of the same
semiconductor material as the FET channel. As
the F ET current varies, the drop across R 14 tends
to compensate for changes in the emitter base voltage of 0 24 •

The current source supplying the input transistors
is 0 29 , It is designed to supply a total input stage
current of 6 pA at 25°C. This current drops to
3 pAat -55°C but increases to only 7.5 pA at
125°C. This temperature characteristic tends to

The collector-emitter voltage of 0 24 is equal to
the emitter base voltage of 0 24 plus that of 0 25 ,
This voltage is delivered to 0 26 and 0 29 , 0 25 and
0 24 are operated at substantially higher currents
than 0 26 and 0 29 • Hence, there is a differential in

APPENDIX

COMPENSATION

COMPENSATION

__------~-4--.-~~--~+_--~~--------------~-------v+

, ~......_ A J V \ . _ _

0 UTPUT

+-----+-------e~

FIGURE A1. Complete Schematic Of The LM108
.;

AN29-18

~

.,.

...

their emitter base voltages that is dropped across
R 19 to determine the input stage current. R 18 is a
pinched .base resistor, as is indicated by the slash
bar through it. This resistor, which has a large
positive temperature coefficient, operates in conjunction with R17 to help shape the temperature
characteristics of the input stage current source.
The output currents of 0 26 , 0 25 and 0 23 are fed
to 0 12 , which·is a controlled-gain lateral PNP. 6 It
delivers one-half of the combined currents to the
output stage. 011 is also connected to 0 12 , with
its output current set at approximately 15 J.1A by
R 7 . Since this type of current source makes use of
the emitter-base voltage differential between
similar transistors operating at different collector
currents, the output of O l lis relatively independent of the current delivered to 0 12 . 12 This current is used for the input stage bootstrapping circuitry.
0 20 also supplies current to the class-B output
stage. Its output current is determined by the ratio
of R 15 to R12 and the current through R 12· R13
is included so that the biasing circuitry isnot upset
when 0 20 saturates.
One major departure frpm the simplified schematic is the bootstrapping pf the second stage active
loads, 0 21 and 0 22 , to t-he output. This makes the
second stage gain dependent only on how well 0 9
and 0 10 match with variations in output voltage.
Hence, the second stage gain is quite high. In fact,
the overall gain of the amplifier is typically in
excess of 10 6 at dc.
The second stage active loads drive 0 14 , A highgain primary transistor is used to prevent loading
of the second stage. Its collector is bootstrapped
by 0 13 to operate it at zero collector-base voltage.
The class-B output stage is actually driven by the
emitter of 0 14 ,
A dead zone in the output stage is prevented by
biasing 0 18 and 0 19 on the verge of conduction
with 0 15 and 0 16 , R9 is used to compensate for
the transconductance of 0 15 and 0 16 , maki ng the
output stage quiescent current relatively independent of the output current of 0 12 , The drop
across this resistor also reduces quiescent current.
For positive-going outputs, short circuit protection
is provided by RIO and 0 17 , When the voltage
drop across RIO turns on 0 17 , it removes base
drive from 0 18 , For negative-going outputs, current limiting is initiated when the voltage drop
across R 11 becomes large enough for the collector
base junction of 0 17 to become forward biased.
When this happens, the base of 0 19 is clamped so
the output current cannot increase further.

Input protection is provided by 0 3 and 0 4 which
act as clamp diodes between the inputs. The collectors ,of these transistors are bootstrapped to the
emitter of 0 28 through R 3' This keeps the collector-isolation leakage' of the transistors from
showing up on the inputs. R3 is included so that
the bootstrapping is not disrupted when 0 3 or 0 4
saturate with an input overload. Cu'rrent-limiting
resistors were not connected in series with the
inputs, si nce diffused resistors cannot be employed
such that they work effectively, without causi ng
high temperature leakages.

Table I. Typical Performance of the LM108
Operational Amplifier (T A = 25°C and
Vs = ±15V).
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Input Common Mode Range
Common Mode Rejection
Offset Voltage Drift
Offset Current Drift
Voltage Gain
Small Signal Bandwidth
Slew Rate
Output Swing
Supply Current
Power Supply Rejection
Operating Voltage Range

0.7 mV
50 pA
0.8 nA
70 Mn
±14V
100 dB

3J.1VtC
0;5 pAtC
300V/mV
1.0 MHz
0.3V /J.1s
±14V
300J.1A
100 dB
±2V to ±20V

REFERENCES
1. R. J. Widlar, "Future Trends in Integrated
Operational Amplifiers," EDN, Vol. 13,
No.6, pp. 24-29, June, 1968.
2. R. J. Widlar, "Super Gain Transistors for ICs,"
lEE E Journal of Solid-State Circuits,
Vol. SC-4, No.4, August, 1969.
3. R . .J. Widlar, "A Uni,que Circuit Design for a
High Performance Operational Amplifier
Especially Suited to Monolithic Construction," Proc. of NEC, Vol. XXI, pp.85-89,
October, 1965.
4. R. J. Widlar, "I.C. Op Amp with Improved
I nput-Current Characteristics," EEE,
pp. 38-41, December, 1968.
5. R. J. Widlar, "Linear IC's: part 6; Compensating for Drift," Electronics, Vol. 41, No.3,
pp. 90-93, February, 1968.

AN 29.:.. 19

6. R. J. Widlar, "Design Techniques for Monolithic Operational Amplifiers," IEEE Journal
of Solid-State Circuits, Vol. SC-4, No.4,
August, 1969.
7. D. R. Sullivan and M. A. Maidique, "Characterization and Application of a New High
Input I mpedance Monolithic Amplifier,"

Transitron Electronic Corporation Application Brief.
8. Paul C. Dow, Jr., "An Analysis of Certain
Errors in Electronic. Differential Analyzers,
II-Capacitor Dielectric Absorption," IRE
Trans. on Electronic Computers, pp. 17-22,
March, 1958.

9. R. J. Widlar, "A Fast Integrated Voltage Follower with Low Input Current," Microelectronics, Vol. 1, No.7, June, 1968.
10. R. C. Dobkin, "Feedforward Compensation
Speeds Op Amp," National Semiconductor
LB-2, March, 1969.
11. R. J. Widlar, "A New Low Voltage Breakdown Diode," National Semiconductor TP-5,
April, 1968.
12. R. J. Widlar, "Some Circuit Design Techniques for Linear Integrated Circuits," IEEE
Transactions on Circuit Theory, Vol. CT-12,
No.4, pp. 586-590, December, 1965.

»
z
November 1969

I

eN

o

r-

o

C')

»

LOGARITHMIC CONVERTERS

:D

One of the most predictable non-linear elements
commonly available is the bipolar transistor. The
relationship between collector current and emitter
base voltage is precisely logarithmic from currents
below one picoamp to currents above one milliamp. Using a matched pair of transistors and integrated circuit operational amplifiers, it is relatively
easy to construct a linear to logarithmic converter
with a dynamic range in excess of five decades.

tron. Combining these two equations and writing
the expression for the output voltage gives

(3)

for EI N ~ O. This shows that the output is proportional to the logarithm of the input Voltage. The
coefhcient of the log term is directly proportional
to absolute temperature. Without compensation,
the scale factor will also vary directly with temperature. However, by making R2 directly proportional to temperature, constant gain is obtained.
The temperature compensation is typically 1%
over a temperature range of _25° C to 100° C for
the resistor specified. For limited temperature
range applications, such as O°C to 50°C, a 430n
sensistor in series with a 570n resistor may be
substituted for the 1 K resistor, also with 1% accuracy. The divider, Rl and R2 , sets the gain while
the current through R3 sets the zero. With the
values given, the scale factor is 1 V/decade and

The circuit in Figure 1 generates a logarithmic out~
put voltage for a linear input current. Transistor
0 1 is used as the non-linear feedback element
around an LM 108 operational amplifier. Negative
feedback is applied to the emitter of 0 1 through
divider, R 1 and R2 , and the emitter base junction of
O2 , This forces the collector current of 0 1 to be
exactly equal to the current through the input resistor. Transistor O 2 is used as the feedback element of an LM 101 A operational ampl ifier. Negative feedback forces the collector current of O2 to
equal the current through R 3 . For the values
shown, this current is 10/lA. Since the collector
current of O2 remains constant, the emitter base
voltage also remains constant. Therefore, only the
VB E of 0 1 varies with a change of input current.
However, the output voltage is a function of the
difference in emitter base voltages of 0 1 and O2 :
E

- Rl + R2 (V
- V
).
SE2
SE1
R2

OUT -

(4)

where the absolute value sign indicates that the
dimensions of the quantity inside are to be
ignored.

(1)

Log generator circuits are not limited to inverting
operation. In fact, a feature of this circuit is the
ease with which non-inverting operation is obtained. Supplying the input signal to A2 and the
reference current to Al results in a log output
that is not inverted from the input. To achieve the
same 100 dB dynamic range in the non-inverting
configuration, an LM 108 shou Id be used for A 2 ,
and an LM 101A for AI' Since the LM 108 cannot
use feedforward compensation, it is frequency
compensated with the standard 30 pF capacitor.

For matched transistors operating at different collector currents, the emitter base differential is
given by

(2)

where k is Boltzmann's constant, T is temperature
in degrees Kelvin and q is the charge of an elec-

E

REF

15V

Rl
15.7K
1%

"Tel LABS TYPE 0. ,
MANCHESTER, N.H.
tOFFSET VOL TAGE ADJUST

FIGURE 1. log Generator with 100 dB Dynamic Range

AN30-1

=i
3:
n
n
o
z
J:

<

m

:D

-t
m

:D
(f)

The only other change is the addition of a clamp
diode connected from the emitter of Q 1 to
ground. This prevents damage to the logging transistors if the. input signal should go negative.

the. transfer function. With the values shown the

scal~ factor is t'V /decade 'an~

The log output is accurate to 1% for any current
between 10 nA and 1 mAo This is equivalent to
about 3% referred to the input. At currents over
500/J.A the transistors used deviate from log characteristics due to resistance in the emitter, while at
low currents, the offset current of the LM 108 is
the major source of error. These errors occur at
the ends of the dynamic range, and from 40 nA to
400/J.A the log converter is 1% accurate referred
to the input. Both of the transistors 'are used in the
grounded base connection, rather than the diode
connection, to eliminate errors due to base current. Unfortunately, the grounded base connection
increases the loop gain. More frequency compensation is necessary to prevent oscillation, and. the log
converter is necessarily slow. It may take 1 to 5ms
for the output to settle to 1% of its final value.
This is especially true at low currents.

from less than.1 OOnA to 1 mAo
Anti-log ..or ,exponential .generation is simply. a
matter of rearranging the circuitry. Figure 3 shows
the circuitry of the .Iog converter connected to
generate an exponential output from a linear
input. Amplifier At: in conjunction with transistor
Oldrives the emitter of Q2 in proportion to the
inpu{voliage.'Ttle'collector current of Q 2 varies
exponentially with the emitter-base Voltage. This
. current i~ converted to a voltage by amplifier A 2 •.
, With :the v~lues give'n

'E O}JT,. :::; 10-[EIN]

(6)

•

3
Many non-linear fu~ctio~ssuch as X
, X , X ,
,1/X" XV, and X/Yare easily generated with the use
of logs. Multiplication becomes addition, division
1/2

2

."R2·, .
lK '
'1%

Cl
300 pF

C2
'15 pF

C3
1 pF

"TEL LABS TYPE 0. ,
MANCHESTER, N.H.

FIGURE 2. Fast Log Generator

The circuit shown in Figure 2 is two orders of.
magnitude faster than the previous circuit and has
a dynamic range of 80 dB. Operation is the Si3me
as the circuit in Figure 1, except the configuration
optimizes speed rather than dynamic range. Transistor Q 1 is diode connected to allow the use of
feedforward compensation! on an LM101A operational ampl ifier. This compensation extends the
bandwidth to 10 MHz and increases the slew rate.
To prevent errors due to the finite hF E of Q 1
and the bias current of the LM 101 A, an LM 102
voltage follower buffers the base current and
input current. Although the log circuit will operate
without the LM 102, accuracy will degrade at
low input currents. Amplifier A2 is also compensated for maximum bandwidth. As with the
previous log converter, R 1 and R2 control the
sensitivity; and R3 controls the zero crossing of

AN30-2

..becomes subtraction and powers become gain
coeffiCients Of log terms: Figure 4 shows a circuit
whose,pkJtPut .is the cube of the input. Actually,
any power· function is available from this circuit
by ch,anging 'thevalu,es of R9 and RIo in accorcJance;with,tr~·expression :

(7)

Note that when log and. anti-log circuits are used
to perform an operation with a I inear output, no
temperature compensating resistors at all are
needed. I f the log and anti-log transistors are at the
same temperature, gain changes with temperature
cancel. It is a good idea to use a heat sink which
couples the two transistors to minimize thermal
gradients. A 1°C temperature difference between

the log and anti-log transistors results in a 0.3%
error. Also, in the log converters, a lOe difference
between the log transistors and the compensating
resistor results in a 0.3% error.

tional to the log of E 1 /E 2 . Transistor 0 3 adds a
voltage proportional to the log of E3 and drives
the anti-log transistor, 0 4 , The collector current of
0 4 is converted to an output voltage by A4 ahd
R7 , with the scale factor set by R7 at E I E3/l OE 2 .

Either of the circuits in Figures 1 or 2 may be used
as dividers or reciprocal generators. Equation 3
shows the outputs of the log generators are actually the ratio of two currents: the input current
and the current through R3 . When used as a log

Measurement of transistor current gains over a
wide range of operating currents is an application
particularly suited to log multiplier/dividers. Using
the circuit in Figure 5, PNP current gains can be

EREF 15V

EOUT

CI
150 pF

C3

ISO pF

*R2
IK
1%

'TEL LABS TYPE 0 81
MANCHESTER, N.H.

FIGURE 3. Ai;'ti-Iog Generator

generator, the current through R3 was held constant
by connecting R3 to a fixed voltage. Hence, the output was just the log of the input. If R3 is driven by
an input voltage, rather than the l5V reference,
the output of the log generator is the log ratio of
the input current to the current through R3 . The
anti-log of this voltage is the quotient. Of course,
if the divisor is constant, the' output is the
reciprocal.

measured at currents' from 0.4 J1A to 1 mAo The
collector current is the input signal to AI, the base
current is the input signal to A 2 , and a fixed voltage to Rs sets the scale factor. Since A2 holds the
base at ground, a single resistor from the emitter
to the positive supply is all that is needed to establish the. operating current. The output is proportional to collector current divided by base current,
or hF E'

A complete one quadrant multiplier/divider is
shown in Figure 5. It is basically the log generator
shown in Figure 1 driving the anti-log generator
shown in Figure 3. The log generator output from
Al drives the base of 0 3 with a' voltage propor-

In addition to their application in performing
functional operations, log generators can provide a
significant increase in the dynamic range of signal
processing systems. Also, unlike a linear system,
there is no loss in accuracy or resolution when the
15V

FIGURE 4_ Cube Generator

AN30-3

input signal is small compared to full scale. Over
most of the dynamic range, the accuracy is a
percent-of-signal rather than a percent-of-full-scale.
For example, using log generators, a simple meter
can display signals with 100 dB dynamic range or
an oscilloscope can display a 10 mV and 10V pulse
simultaneously. Obviously, without the log generator, the low level signals are completely lost.

zeroed, if necessary, to improve accuracy with low
input voltages.
The log converters are low level circuits and some
care should be taken during construction. The
input leads should be as short. as possible and the
input circuitry guarded against leakage currents.
Solder residues can easily conduct leakage currents, therefore circuit boards should be cleaned
before use. High quality glass or mica capacitors
should be used on the inputs to minimize leakage
currents. Also, when the +15V supply is used as a
reference, it must be well regulated.

To achieve wide dynamic range with high accuracy,
the input operational amplifier necessarily must
have low offset voltage, bias current and offset
current. The LM108 has a maximum bias current
of 3 nA and offset current of 400 pA over a -55°C
to 125°C temperature range. By using equal source
resistors, only the offset cl,Jrrent of the LM 108
causes an error. The offset current of the LM 108 is
as low as many FET amplifiers. Further, it has a
low and constant temperature coefficient rather
than doubling every 1Q°C. This results in greater
accuracy over temperature than can be achieved
with FET amplifiers. The offset voltage may be

REFERENCES:
1. R. C. Dobkin, "Feedforward Compensation
Speeds Op Amp," National Semiconductor
Corporation, Linear Brief 2, April, 1969.
2. R. J. Widlar, "Monolithic Operational Amplifiers- The Universal Linear Component,"
National Semiconductor Corporation, AN-4,
April, 1968.
2N2920

R6
2K
.......

_~_EOUT=~
FOR
E,.E 2.E 3 >O

C7
30 pF

C6
150 pF

FIGURE 5. Multiplier/Divider

AN30-4

»
z
February 1970

o
"'tJ
»

:s:"'tJ

op amp circuit collection
section 1 -

basic circuits

(")

II
(")

A2

C

---4
(")

orInverting Amplifier

rm

Non-Inverting Amplifier

(")

---4

o

R2

Z

R4
Rl

V2
VOUT

R3

VOUT

A3
AI + A2) R4

VOUT = ( ii3+R4

A2

iii V2 - iii V,

VOUT=-R4(~+~+~)

FOR Rl = R3 AND R2 = R4
VOUT = ~ (V 2 -V,)

A5 = Al IIAUR3#R4
':"

A1#A2 = R3#A4
FDA MINIMUM OFFSET EAROR
DUE TO INPUT BIAS CURRENT

FDA MINIMUM OFFSET ERAOA
DUE TO INPUT BIAS CUARENT

Inverting Summing Amplifier
Difference Amplifier
Cl
3pF
Al
10M

1%

INPUT

-JV\iI\r-....~--'V""--.

·Soufceimpedance

OUTPUT

10" than lOOK
gwelessthan 1%
g8lRerrOJ.

R3
5.1M

Non-Inverting Summing Amplifier
Inverting Amplifier with High
Input Impedance
Cl
5pF

AI
1M

OUTPUT

A2
10M

VOUT

A3
910K

...JVl.I'v-.....-.::..j
VOUT = R1 ; R2 V
1N
R

R,• = R3
A3 = A1#R2

Fast Inverting Amplifier With High Input Impedance

Non-Inverting AC Amplifier

AN31-1

C2

INTEGRATE

R3
100

VIN~

Rl

Cl
I, =
I'; =

VOUT

2~ ~2Cl

2~ ~1 Cl = 2~ ~2C2

12

J

VIN dl

I,

30 pF
'_

1
"'=bR 1Cl

Rl = R2

Practical Differentiator

FOR MINIMUM OFFSET ERROR
DUE TO INPUT -BIAS CURRENT

Integrator

C3

Rl

VIN

--"'11""-...--.----1 1------.

.----4 1-----4It--

Rl
V OUT

VOUT

'FOR MINIMUM ERROR OUE TO
BIAS CURRENT R2 = Rl
Cl
150pF

Current to Voltage Converter

Fast Integrator

Rl

_------4....

R2

+20V

Rl
10K
1%
+10V
V IN

R2
R3

-=

Cl
30pF

10K
1%

+10V .....I-....~--------...-.

Circuit for Operating the LM101
without a Negative Supply

AN31-2

Circuit for Generating the
Second Positive Voltage

Rl

r--"'-""'''''''-V·

R2

R4
75K

Rl

OUTPUT

Y'N

--"\;M,......--------.
VOUT
*Adjust for zero integrltor drih.
Current drift typitlllV 0.1, nAtC
over -55"C to 125°C temper.ture r.nge.

Neutralizing Input Capacitance to
Optimize Response Time

Integrator with Bias Current Compensation
v·

Threshold Detector forPhotodiodes

INPUTS

Voltage Comparator for, Driving
DTL or TTL integrated Circuits

v,
01

02

03

VOUT = 4.6V lor
VLT ::;V'N ::;VUT

!

VOUT = OVlor
VIN V UT

v,

t
Double-Ended Limit Detector

Multiple Aperture Window biscriminator

AN31-3

RJ

R4

RS

INPUT~NIr-4t-f

OUTPUT

Rl
200K

S~~ :>II-JVVY. .
R2
lOOn
RANGE = ,y

(~)

Offset Voltage Adjustment for Non-Inverting
Amplifiers

Offset Voltage Adjustment for Inverting Amplifiers
Using Any Type of Feedback Element

R2

Rl
El-'V\,..,.. . .~
RJ
lK

OUTPUT

INPUTS
E2

R2
lOOK

+

Rl

R3
OUTPUT

INPUT

RANGE = !V

R4
10

(W,)

RANGE = ±y

(~) (~)

GAIN=~

Offset Voltage Adjustment for Differential Amplifiers

Offset Voltage Adjustment for Voltage Followers

, .y
Rl

OUTPUT
Rl = 2000 R3#R4
R4#R3<10kn

RANGE~ ,y (Rl:t4)

Offset Voltage Adjustment for Inverting
Amplifiers Using 10 kn Source Resistance
or Less

AN31-4

R2 = R3. R4

section 2 -

signal generation

C2
0.02 ~F
1%

COSINE
OUTPUT

C5
JOpF

R2
22M
1%

10 = 1 Hz

R4
50K

01

6.JV
02

6.JV

Low Frequency Sine Wave Generator with Quadrature Output

C2

CJ

200 pF
1%

100 pF
1%

SINE OUTPUT

RJ
lOOK
1%

R4
5K

t - -........- COSINE

OUTPUT

Rl
220K
1%

C5
150pF

R6
220K

01

t%

6.JV

R5
2K
fo

==

10 kHz

02

6.JV

High Frequency Sine Wave Generator with Quadrature Output

AN31-5

R3
750

Rl
160K

>-+--E

OUT

L1-

CP

O.Ol~FI
R2
910K

Rl
200K
1%

Rl = R2
Cl = C2
1

·Chosen for oscillation at 100 Hz

f = 2~Rl Cl

Free-Running Multivibrator
Wein Bridge Sine Wave Oscillator

Rl
lOOK

V,N
±5V

R2
lOOK

.-----t~- VOUT

R5
10K

Triangle Wave
Output

01
6.2V
R3

loon

R5
8.2K

02
6.2V

Function Generator
Pulse Width Modulator

Rl
2M
1%

R3
1M
1%

V,N
I

_ R3 V,.
RI RS

OUT -

R3 = R4 + RS
Rl = R2

R5
2K
1%

':"
lOUT

R3 = R4+ R5
Rl = R2

0.1%

Bilateral Current Source
i

AN31-6

R4
1M
1%

Bilateral Current Source

3K

51K

1.1K

R2
10K

Rl = R2
Cl = C2

f=h~l Cl

'---"'--4.--15

Wein Bridge Oscillator with FET Amplitude Stabilization

t41V

-41V

J

TRIM

lN759
12V

01

2N2605

Rll

1.2K
1%

FOR

le2= 1.00mA

03

]

TRIM

FOR
IC4 = 1.00 rnA

05

lN759
12V

03
2N2484

C3
300 pF

'V OUT = lV/Krl

Low Power Supply for Integrated Circuit Testing

AN31-7

01

lN4611
6.6V

r--------e--V+
Rl

Your

RZ

Your

01

lN4611
6.6V
'--_ _ _ _ _....

~R3

R4

Positive Voltage Reference

Positive Voltage Reference

01

lN4611
6.6V

01

Your

lN4611
6.6V

Rl
R4
V-

Negative Voltage Reference

Negative Voltage Reference

Rl

IO=~

Rl

V'N::O:0V

Precision Current Sink

AN31-8

Precision Current Source

section 3 -

signal processing

OUTPUT

Ay

=

~

Differential-Input Instrumentation Amplifier

+INPUT

0.1%

-GAIN ADJUST
Ay = 10- 4 R6

Cl
150 pF

Variable Gain, Differential-Input Instrumentation Amplifier

AN31-9

RJ
SKt
0.1%

R6
SDK
0.1%

R4
SKt
0.1%

OUTPUT

RI = RS= IOR2
R2 = RJ

RI'
SDK
0.1%

R7*
SDK

RJ= R4
RI = R6= 10RJ

0.1%

Av=~

+ .....I-----INPUTS - - - -

*tMltchingdetermlnescommon
mode rejection.

Instrumentation Amplifier with ±100 Volt Common Mode Range

RZ'
10K

R6 t
lOOK

0.1%

0.1%

RI
4SK
1%

OUTPUT

INPUTS

RJ
10K
1%

CJ

R4
4SK RS'
1% 10K
0.1%

+
C2
,*'OOPF

JOpF

RI = R4
RZ = RS
R6 = R7
t*Matchmg Determines CMRR

R7t
lOOK
0.1%

Av

=~(I +~n

Differential Input Instrumentation Amplifier with High Common Mode Rejection

AN31..:m

RP

R2t

RJt

R4 •

lOOK
0.1%

lK
0.1%

lK
0.1%

lOOK
0.1%

v'
R6
1M
0.1%

Rl
lK

S2
lK

T

RJ

1M
0.1%

R1

SOK
1%

OUTPUT
R4

>-"'---OUTPUT

1M
0.1%
Sl
lK

R2

lK
-

__

INPUTS _

Cl'

"Reduces leed ttlrou ... 01
power supply nollo by 20 dB
and makes supply bypatlint

100pF

t~;i~::::~ common mode

T

+

rejection
tGainadjust
*tMltching determines CMRR
t May be deleted to maximize bandwidth

High Input Impedance Instrumentation Amplifier

Bridge Amplifier with low Noise Compensation

Rl

v+

Rl _ R2

Rs,-Rs;
vOUT=V+(l-.!!!)
Rs.

Precision Diode

Bridge Amplifier

C2
JpF

E'N--IVVV-. .- - - - - - - 4 t - - E oUT
01
lN914

...--""/\,----4I....----EOUT
01
lN914

02
lN914
E.EF·--. .-

.....I--~
02
lN914

Precision Clamp

must have a SOUTce
impedance of less than
20012il 02 is.sed.

*EREF

Fast Half Wave Rectifier

AN31-:-11

C2

R6
20K
1%

10)!F

R3
10K
1%

R2
20K
1%

..

..-.....~Mw-4~.-..oJ\NIr-......~-"""'II\r-R7
22.2K

01
lN914

02

-Eour

*Feedforward compenSltion

lN914

can be used to make. fast

full

Wive

rectifietwlthout

a filter.

C3'
30 pF

Precision' AC to DC Converter

R3
20K

OUTPUT

INPUT

Cl
30pF

Low Drift Peak Detector
R2
Rl
INPUT-. .v..,.",.. .--....J\M~----,

OUTPUT
INPUT

SAMPLE

*Polycarbonate-dielectric capacitor

Sample and Hold

OUTPUT

R4

v·

Rl
1M

INPUT
R3

6

POlARITY
SIGNAL

OUTPUT

·Worstca. drift less than

Your

=-*

R2=

2.5mV/sec
Y'N

R~\~4

Absolute Value Amplifier with Polaritv Detector

AN31-12

tTofIon,Polyethylono 0'
Polycarbonate Dtelectric
CoPlcit.,

C2
30 pF

Sample and Hold

R2
lOOK

Rs

INPUT-"",..,......_--------~....--I

'---+-+-RESET

OUTPUT
>"-+-OUTPUT

• In addition to increlsingweed..

the lMl01A rai1es high and low
frequency gain, increases output
drive capability Ind elimil1ltes
*01 and Q3 should not hilve
mternalgate-protectiondiodes.

Worst case drift h!ssthan
500 ~V/set over _55°C
to +12SoC.

thermal feedback.

t

Power Bandwidth: 2S0 KHz
Sm,lI Sign,' Bandwidth: 3.S MHz
Slew Rite: 10Vll"

t CS= 6X :0-

S

R

Fast t Summing Amplifier with Low Input Current

Low Drift Integrator

Dl

RS
2K

-----------4I------II----....

INPUT---'\M,._. .

Rl
IS0K

Cl
0.002

~F

CJ

0.002

~F

R2
1M

RJ
1M

Fast Integrator with Low Input Current

AN31-13

R3
4K
0.1%

Rl
10M

V,N

C3
540 pF

10=

21T~'C'

= 60 Hz
Cl
270 pF

RI = R2 =2R3
Cl = C2 = C23
R4= R5
Rl = R3
R4= 1/2 Rl

R4
2K
0.1%

to= 21TR4Jcm-

R5
2K
. 0.1%

Adjustable Q Notch Filter

Easily Tuned Notch Filter

VOUT

OUTPUT

10= _ _'_ _
21TJii1R2C1C2"

v.
10= 21T;fR;R2C1C2
INPUT

Tuned Circuit
Two-Stage Tuned Circuit

R3
lK 1%

Rl
10M

V,N

-~""'-'V\I\r-"'I---N\r--.~
C3
540 pF
Rl
10M
1%

lo=rn

R3
5M

RI = R2 =2R3
Cl = C2 = C3/2

C2
30pF

C2
270pF

High Q Notch Filter

Negative Capacitance Multiplier

Rl

R2

lK

10K

Cl
O.IIlF

c __

Variable Capacitance Multiplier
R2
10M

R2
100

RJ
10M

C=~Cl
Vos + los Rl
i L =--R3--

i~~OPF

1

CJ

R4

Rs = RJ
RJ
lK
1%

C2

.

JOpF,

30 pF . -: 10K

L "'Rl R2 Cl
Rs= R2
Rp = Rl

__

C

Rl
10M
1%

Simulated Inductor

Capacitance Multiplier

R6

OUTPUT

Vy

CONTROL

Rl
15K

Two Quadrant Multiplier

Voltage Controlled Gain Circuit

AN31-15

RI
IIOK

CP

940 pF

>--+_ OUTPUT

CI*
0.021'F

"'>--...._-

Rl
24K

INPUr--1

C2'
"I470PF

'Values ... Ior 100 Hz cutoll. Use
rnmlizedpolYCIrboniteClPlcitors
forgoodtemperaturesubility.

R5
187.5K

·Values are for 10kHz cutoff. Use
silvered mica capacitors for good
temperature stability.

High Pass Active Filter

Low Pass Active Filter

R6
50K

02
2N2605
03

Rl
0.1
1%

R4

'-.~NIf--+_ _ _ _-\2N260,.5_ _~Vl0VOK"""_ _" , ,
R2
100

1r = -15V

1%

R2
lOOK
Rl
10K

OUTPUT

INPUT---JIt,JI/Y------4t----i

01
MONITOR
OUTPUT
5V/A

Cl
30 pF

Current Monitor
Nonlinear Operational Amplifier with
Temperature Compensated Breakpoints

r--------4~V+

INPUTS

C2
30 pF

OUTPUT

R2
470

.....- - - - - -. .-V-

Saturating Servo Preamplifier with
Rate Feedback

AN31-16

OUTPUT

Power Booster

R5

R2

Rl

v, :>0
Your = V;OV2

v,

V-

V2

Analog Multiplier

INPUT ~WV-.'i
OUTPUT t

R2
300K

R2

':'

03
lM103
3.3V

R3
15M

Rl
75K

~---4"'-V-

= -15V

R3
5.1K

*lowleakage-O,017 IJF per second delay.

long Interval Timer

PropagatIOn delay approximately 200ns
tOll or TTl fanout 01 three.
Minimizest,aycapacitance
Pin 8

Fast Zero Crossing Detector

...- - - - - - 4 I J - OUTPUT

,....-~

C1
10;tF

T

~ TRANSDUCER

low frequency cutoff

=

R1

Cl

R5
24.3K
1%

R2
12K

'Setlor OV,tO"C
tAdjustlor 100mV/'C

-15V - -. .-------~

Amplifier for Piezoelectric Transducer

Temperature Probe

AN31-17

Rl
5M
1%

>--+- OUTPUT

Cl
0.01 ~F

INPUT
VOUT

--1

OUTPUT

T

1%

":"

Cl
100 PF
*Operatmgphotodiodewithless
than 3mV across it eleminates

leakage currents.

Photodiode Amplifier

Photodiode Amplifier

High Input Impedance AC Follower

V+= 15V
2N2920

RJ'
1.5M

1%

Rs

INPUT-W"""""+----l

1---.....,

R4"
105M
C4
150 pF

Cl
JOO pF
10nA -..- -

R9
10K

R2
10K

• t2NJ728 matched pairs

Root Extractor

"AN31-18

OUTPUT

R4

lOOK
1%

2N2920

Rl
lOOK
1%

E,

E, ~~~a-------------~

EOUT

= E~:J

for

E,;:O:OandE,?O

R8
tOOK

Mu Itiplier/Divider

R4
1.5M

~--------~

Rl
lOOK

__

Ql

--~

2N2920

~--~----~

Q2

1%
,--~----------~~~v-

15V~MM""------------.'"

EOUT

R8
1.5M

Cube Generator

AN31-.19

A3
IS0K
1%

2N2920

AS

IS0K
CS

IS0pF
'A2
lK
1%

Cl
300 pF

C2
7SpF

C3
lpF

·Tel·Lab.Type081
Manchester, N.H.

Fast Log Generator

ER . .

ISV
A3
IS0K
1%

2N2920

A6
10K
1%

EOUT

*Tel·labs Type Qll
Manchester, N.H

Anti-log Generator

AN31-20

:t>

z
February 1970

I

W
N
'TI

m

~

FET circuit applications

n
:lJ

n

c:
~

:t>

."
"0

........- " " ' - - - - - 4.....-oV+

>-.......-0 OUTPUT
INPUT

r-

n

2N3684

l>

0-"'-""'"

o-

~

z

r-----4~-oOUTPUT

en
R1

INPUT

*Polycarbonate
dielectric

o-"'VII\r+--....-~h

2N3686

SAMPLE

...., I +15V
W -15V

SAMPLE
HOLD

Sample and Hold With Offset Adjustment

JFET AC Coupled Integrator

The 2N4339 JFET was selected because of its low
IGSS «100 pAl, very-low lo(oFF) «50 pAl and
low pinchoff voltage. Leakages of th is level put
the burden of circuit performance on clean, solderresin free, low leakage circuit layout.

This circuit utilizes the ",u-amp" technique to
achieve very high voltage gain. Using C 1 in the circuit as a Miller integrator, or capacitance multiplier, allows this simple circuit to handle very
long time constants.

RESET
+30V
10K .. 1JJf
2.2M
.001JJf

<>---II--+~~~
R'N
C'N

2

100M

<::.. 25 pf

10M
10K

OUTPUT
OUTPUT
1M

-15V

Long Time Comparator

The 2N4393 is operated as a Miller integrator. The
high Y fs of the 2N4393 (over 12,000 ,umhos @
5 mAl yields a stage gain of about 60. Since the
equivalent capacitance looking into the gate is C
times gain and the gate source resistance can be
as high as 10 Mn, time constants as long as a
minute can be achieved.

Ultra-High ZIN AC Unity Gain Amplifier

Nothing is left to chance in reducing input capacitance. The 2N4416, which has low capacitance in
the first place, is operated as a source follower
with bootstrapped gate bias resistor and drain. Any
input capacitance you get with this circuit is due
to poor layout techniques.

AN32-1

SHUNT

PEAKING COIL
+V

t--....--QOUTPUT

2N3823

FET Cascode Video Amplifier

JFET Pierce Crystal Oscillator

The FET cascode video amplifier features very low
input loading and reduction of feedback to almost
zero. The 2N3823 is used because of its low capacitance and high Y fs . Bandwidth of this amplifier is
limited by R L and load capacitance.

2M

.SV

The JFEi Pierce crystal oscillator allows a wide
frequency range of crystals to be used without circuit modification. Since the JFET gate does not
load the crystal, good Q is maintained thus insuring
good frequency stabil ity.

SI

10M
S2C
IV

OFF

BM

SV
1M

-

1M
10V

9V

BOOK
3.3M
IK

SOV
lOOK
100V
80K
500V
10K

100V
10K

FETVM-FET Voltmeter

This FETVM replaces the function of the VTVM
while at the same time ridding the instrument of
the usual line cord. In addition, drift rates are far
superior to vacuum tube circuits allowing a 0.5 volt

AN32-2

full scale range which is impractical with most vacuum tubes. The low-leakage, low-noise 2N4340 is
an ideal device for this application.

.------------------------------------_._---'_... _-----....,

V+

.OII'F

INPUT

0---1 t--_-~. . . .
10K

lOOK

10K

.0331'F

':'

.0331'F

10K

>-....- 0 OUTPUT

10K

lOOK
.OO33I'F

.OO33I'F

':'

HI-FI Tone Control Circuit (High Z Input)

The 2N3684 JFET provides the function of a high
input impedance and low noise characteristics to

buffer an op amp-operated feedback type tone
control circuit.

RFC
+12Vo--....-

....

RFC

BYPAs.t"
fC~~

Lc:

AGC

100 MHz Converter

The 2N4416 JF ET will provide noise figures of less
than 3 dB and power gain of greater than 20 dB.
The JFETs outstanding low crossmodulation and
low intermodulation distortion provides an ideal
characteristic for an input stage. The output feeds

into an LM 171 used as a balanced mixer. This configuration greatly reduces L.O. radiation both into
the antenna and into the I. F. strip and also reduces R F signal feedthrough.

AN32-3

As
DIFFEAENTIAl
INSTAUMENT
Rs
INPUT Q..-'\JVV--:....

~~~OUTPUT

TOGGLE
ORIVE

- - - TO ADDITIONAL
_ _ _ MULTIPLEX STAGES

0----'\1\"'""---....

DIFFERENTIAL
INSTRUMENT
Rs
INPUTQ..---#\AIu-------'

As-SCALING AESISTOAS

Differential Analog Switch

wide temperature ranges (-25 to +125°C), this
makes it an unusual but ideal choice for an
accurate multiplexer. This close tracking greatly
reduces errors due to common mode signals.

The FM1208 monolithic dual is used in a differential multiplexer application where R DS (0 N)
should be closely matched. Since RDS(O N) for the
monol ith ic dual tracks at better than ± 1% over

lK

...--.J\IV\,--.....(') +15V

.01/1F

~OUTPUT
.. 004/1F

INPUT

-::-

ro+--....-a.-.'-

. . .- - - - - - -....-.JIIA/I_-(")-15V

lK

Magnetic-Pickup Phono Preampiifier

This preamplifier provides proper loading to a reluctance phono cartridge. It provides approximately
35 dB of gain at 1 kHz (2.2 mV input for 100 mV
output), it features S + N/N ratio of better than

AN32-4

-70 dB (referenced to 10 mV input at 1 kHz) and
has a dynamic range of 84 dB (referenced to 1 kHz).
The feedback provides for R IAA equalization.

+5V
R2

OUTPUT

MOS
lOGIC
elEMENT

WITH
NEGATIVE
SUPPl V

-v
GAIN CONTROL

-v

Negative to Positive Supply Logic Level Shifter

Variable Attenuator

The 2N3685 acts as a voltage variable resistor with
an ROS(ON) of 800n max. The 2N3685 JFET will
have linear resistance over several decades of resistance providing an excellent electronic gain control.

2N4391

This simple circuit provides for level shifting from
any logic function (such as MOS) operating from
minus to ground supply to any logic level (such as
TTL) operating from a plus to ground supply. The
2N3970 provides a low rds(ON) and fast switching
times.

2N4391

~--------~--~V+

VIOEO
INPUT

VIOEO
OUTPUT

2N3684

1-+--oVOUT
-10V
lM~~~----------~---t

2N3686

\

\

-= \
\

-=

Av =

lM.>oIIt-T------....

\'--- --.l........()
\

i

= 500 TYPICAL

~=2

Voltage Controlled Variable Gain Amplifier

Ultra-High Gain Audio Amplifier

The 2N4391 provides a low RDS(ON) (less than
30n). The tee attenuator provides for optimum
dynamic linear range for attenuation and if complete turnoff is desired, attenuation of greater than
100 dB can be obtained at 10 MHz providing proper R F construction techniques are employed.

Sometimes called the "JFET J.1 amp," this circuit
provides a very low power, high· gain amplifying
function. Since fJ. of a JFET increases as drain current decreases, the lower drain current is, the more
gain you get. You do sacrifice input dynamic
range with increasing gain, however.

lK
1%

INPUT
OUTPUT

Level-Shifting-Isolation Amplifier

The 2N4341 JFET is used as a level shifter between two op amps operated at different power

supply voltages. The JFET is ideally suited for this
type of application because I D = Is.

AN32-5

r--"'VIoI'v--Q+V

+50V
PREBIAS
LINE

+5V

o---a

O-...- - I - - -....- f - -....- -

DTl"TTl
BIPOLAR
LOGIC

*Trademark of the
Burroughs Corp"

Precision Current Sink
FET Nixie* Drivers

The 2N3684 JFETs are used as Nixie tube drivers.
Their V p of 2-5 volts ideally matches DTL-T"TL
logic levels. Diodes are used to a +50 volt
prebias line to prevent breakdown of the JFETs.
Since the 2N3684 is in a TO-72 (4 lead TO-181
package, none of the circuit voltages appear on the
can. The JFET is immune to almost all of the
failure mechanisms found in bipolar transistors
used for this application.

The 2N3069 JF ET and 2N2219 bipolar have inherently high output impedance. Using R 1 as a current sensing resistor to provide feedback to the
LM 101 op amp provides a large amount of loop
gain for negative feedback to enhance the true current sink nature of this circuit. For small current
values, the 10k resistor and 2N2219 may be eliminated if the source of the JFET is connected to

R1 .

OUTPUT

+JOV

0-....---11-----....- - -......."

+15V

INPUT

Cl
01 pF*

....

.--I~-----

o

ry-..",~. . .

1_

FROM
VIDEO
DETECTOR

n

*Polycarbonate
dielectric capacitor

r-+ 15V (SAMPLE)

....J L.J

-20V (HOLD)

Low Drift Sample and Hold
JFET -Bipolar Cascode Circuit

The JFET-Bipolar cascode circuit will provide full
video output for the CRT cathode drive. Gain is
about 90. The cascode configuration eliminates
Miller capacitance problems with the 2N4091
JFET, thus allowing direct drive from the video
detector. An m derived filter using stray capacitance and a variable inductor prevents 4.5 MHz
sound frequency from being amplified by the
video amplifier.

AN32-6

The JFETs, Q 1 and Q2, provide complete buffering to C l , the sample and hold capacitor. During
sample, Q 1 is turned on and provides a path,
rds(ON), for charging Cl. During hold, Q 1 is
turned off thus leaving Q 1 ID(oFF) «50 pAl and
Q 2 IGSS «100 pAl as the only discharge paths.
Q 2 serves a buffering function so feedback to the
LM 101 and output current are supplied from its
source.

+5V
R2

OUTPUT
MOS
LOGIC
ELEMENT
WITH
NEGATIVE
SUPPL Y

-v
GAIN CONTROL

-v

Negative to Positive Supply Logic Level Shifter

Variable Attenuator

The 2N3685 acts as a voltage variable resistor with
an ROS(ON) of 800n max. The 2N3685 JFET will
have linear resistance over several decades of resistance providing an excellent electronic gain control.

This simple circuit provides for level shifting from
any logic function (such as MOS) operating from
minus to ground supply to any logic level (such as
TTL) operating from a plus to ground supply. The
2N3970 provides a low rds(ON} and fast switching
times.

2N4391

2N4391

~--------~--~V+

VIDEO
OUTPUT

1--~---oVOUT

-10V
1M~~~----------~---e
\

\

-= \\ 1M>4.......--=- - -.....
\'-- --.l........Q

Jo00111F
Av = ~ = 500 TYPICAL

\

Voltage Controlled Variable Gain Amplifier

Ultra-High Gain Audio Amplifier

The 2N4391 provides a low ROS(ON} (less than
30n). The tee attenuator provides for optimum
dynamic linear range for attenuation and if complete turnoff is desired, attenuation of greater than
100 dB can be obtained at 10 MHz providing proper R F construction techniques are employed.

Sometimes called the "JFET J1 amp," this circuit
provides a very low power, high gain amplifying
function. Since J1 of a JFET increases as drain current decreases, the lower drain current is, the more
gain you get. You do sacrifice input dynamic
range with increasing gain, however.

1K
1%

INPUT
OUTPUT

Level-Shifting-Isolation Amplifier

The 2N4341 JFET is used as a level shifter between two op amps operated at different power

supply voltages. The JFET is ideally suited for this
type of application because 10 = Is.

AN32-5

_JV\"",,-o+V

+50V
PREBIAS~-_

LINE

+5V

O-~~""""--"-""""--4II"--

DTl-TTl
BIPOLAR
LOGIC

"Trademark of the
Burroughs Corp.

Precision Current Sink
FET Nixie* Drivers

The 2N3684 JFETs are used as Nixie tube drivers.
Their Vp of 2-5 volts ideally matches DTL-lTL
logic levels. Diodes are used to a +50 volt
prebias line to prevent breakdown of the JFETs.
Since the 2N3684 is in a TO-72 (4 lead TO-18)
package, none of the circuit voltages appear on the
can. The JFET is immune to almost all of the
failure mechanisms found in bipolar transistors
used for this application.

The 2N3069 JFET and 2N2219 bipolar have inherently high output impedance. Using R 1 as a current sensing resistor to provide feedback to the
LM101 op amp provides a large amount of loop
gain for negative feedback to enhance the true current sink nature of this circuit. For small current
values, the 10k resistor and 2N2219 may be eliminated if the source of the JF ET is connected to
RI ·

OUTPUT

-I----....-----+t

O-....

+15V

INPUT

FROM
VIDEO
DETECTOR

"Poly.arbonate
dielectric capacitor

n
.....J

.+15V (SAMPLE)

L...I

-20V (HO LD)

Low Drift Sample and Hold
JFET -Bipolar Cascode Circuit

The JFET-Bipolar cascode circuit will provide full
video output for the CRT cathode drive. Gain is
about 90. The cascode· configuration eliminates
Miller capacitance problems with the 2N4091
JFET, thus allowing direct drive from the video
detector. An m derived filter using stray capacitance and a variable inductor prevents 4.5 MHz
sound frequency from being amplified by the
video amplifier.

AN32-6

The JFETs, Q I and Q2, provide complete buffering to C 1 , the sample and hold capacitor. During
sample, Q I is turned on and provides a path,
rds(ON), for charging C I • During hold, Q 1 is
turned off thus leaving Q I 10 (0 F F) «50 pAl and
Q 2 IGSS «100 pAl as the only discharge paths.
Q 2 serves a buffering function so feedback to the
LM 101 and output current are supplied from its
source.

+15V ON
-20V OFF

1M

.001

SIGNAL o----~

>-"'--0

Wien Bridge Sine Wave Oscillator

The major problem in producing a low distortion,
constant amplitude sine wave is getting the amplifier loop gain just right. By using the 2N3069
JFET as a voltage variable resistor in the amplifier
feedback loop, this can be easily achieved. The
LM 103 zener diode provides the voltage reference
for the peak sine wave amplitude; this is rectified
and fed to the gate of the 2N3069, thus varying its
channel resistance and, hence, loop gain.

OUTPUT

1..-.---0

+15V

.......- - - - - - 0

-15V

JFET Sample and Hold Circuit

The logic voltage is applied simultaneously to the
sample and hold JFETs. By matching input impedance and feedback resistance and capacitance, errors due to rds(ON) of the JFETs is minimized.
The inherent matched rds(ON) and matched leakage
currents of the FM1109 monolithic dual greatly
improve circuit performance.

, . . . . . - -. . .- o V +

2N5139

"--_~OVOUT

High Impedance Low Capacitance Wideband Buffer

High Impedance Low Capacitance Amplifier

The 2N4416 features low input capacitance which
makes this compound-series feedback buffer a
wide-band unity gain amplifier.

This compound series-feedback circuit provides
high input impedance and stable, wide-band gain
for general purpose video ampl ifier appl ications.

AN32-7

. - - - -....- - - - - -. . .- - - - - -...._Ot12V

+28V

4.7K

r - - - -....- -...- -...~O OUTPUT

2N3823

1M

Stable low Frequency Crystal Oscillator

o to 360° Phase Shifter

This Colpitts-Crystal oscillator is ideal for low frequency crystal oscillator circuits. Excellent stability is assured because the 2N3823 JF ET circuit
loading does not vary with temperature.

Each stage provides 0° to 180° phase shift. By
ganging the two stages, 0° to 360° phase shift is
achieved. The 2N3070 JFETs are ideal since they
do not load the phase shift networks.

VOUT

I
IANALOG
I INPUT

OTl
TTl

:
I

INPUT
CONTROL

2

2N4860

I
I

10K

L _________ ..JI
DM7800
VOL TAGE
TRANSLATOR

I

ADOITIONAL STAGES
IF REQUIREO

DTl-TTl Controlled Buffered Analog Switch

This a~alog switch uses the 2N4860 JFET for its
25, ohm ro N and low leakage. The LM 102 serves
as a voltage buffer. This circuit can be adapted to

a dual trace oscilloscope chopper. The DM7800
monolithic I.C. provides adequate switch drive
controlled by DTL-TTL logic levels.

-VG
20 MHz OSCillATOR VALUES
Cl '" 700 pF
C2 = 75 pF
Voo = 16V

OUTPUT

U

6.8K

__"V'>JVo~ Vo 0

11 = 1.3JJH
L2 = lOT 3/8" DIA 3/4" LONG
10 = 1 rnA

20 MHz OSCillATOR PERFORMANCE
LOW DISTORTION 20 MHz OSC.
2NO HARMONIC - 60 dB
3RO HARMONIC> -70 dB

47 pF

low Distortion Oscillator

The 2N4416 JFET is capable of oscillating in a circuit where harmonic distortion is very low. The

AN32-8

JFET local oscillator is excellent when a low harmonic content is required for a good mixer circuit.

1"---i--r-.......Q
-AGC

INPUT l

o-....JV\IV. . .~. . .-.)

OUTPUT
AGC RANGE 59 dB
POWER GAIN 17 dB

U'''''''''''I-1'-'''
':'

II = .07 I1Hy CENTER TAP
l2 = .07 I1Hy TAP '.4 UP FROM GROUNO

200 MHz Cascode Amplifier

This 200 MHz JFET cascode circuit features low
crossmodulation, large-signal handling ability, no
neutralization, and AGe controlled by biasing the

upper cascode JFET. The only special requirement
of this circuit is that loss of the upper unit must
be greater than that of the lower unit.

OUTPUT

30 pF

-v

FET Op Amp

The FM3954 monolithic-dual provides an ideal
low-offset, low-drift buffer function for the
LM101A op amp. The excellent matching charac-

teristics of the FM3954 track well over its bias
current range thus improving common mode
rejection.

High Toggle Rate High Frequency Analog Switch

This commutator circuit provides low impedance
gate drive to the 2N3970 analog switch for both
on and off drive conditions. This circuit also approaches the ideal gate drive conditions for high

frequency signal handling by providing a low ac
impedance for off drive and high ac impedance
for on drive to the 2N3970. The NH0005 op amp
does the job of amplifying megahertz signals.

AN32-9

2N4091 JFETS
,.Jo.-...._ [ ) INPUT 1

1M

...- o INPUT 2

~-

1M

~-

__- o INPUT J
1M

.....-

. . .- 0 INPUT 4
1M

,

. . . ------0

I

L _ _ _ _ _ -.J

OUTPUT

OM7800
VOL TAGE TRANSLATOR

4-Channel Commutator

This 4-channel commutator uses the 2N4091 to
achieve low channel ON resistance «30n) and
low OFF current leakage. The DM7800 voltage
translator is a monolithic device which provides

from +10V to -20V gate drive to the JFETs while
at the same time providing DTL-TTL logic compatability.

R5

2N4392

OIFFERE~:~~~

o-....J\jRI\4,..,... .---------.~

~-...-o VOUT

2N4J40

"SCALING"
RESISTORS

1

,~"

R2

-------+,

OIFFERE~J~~~ l)-.JV'V"w---~-.......
RJ

Rl

2N4340

Rl = R2
RJ = R4

~
AOOITIONAL
CHANNELS

FROM OM7800
r'1 +10
VOL TAGE TRANSLATOR....J
L.. -20V

Wide Band Differential Multiplexer

This design allows high frequency signal handling
and high toggle rates simultaneously. Toggle rates

AN32-10

up to 1 MHz and MHz signals are possible with this
circuit.

RI
0,1
POSITIVE
1%
INPUT o--4II-.IV\.,..,.-4II......- O TO LOAD
VOLTAGE

MONITOR
OUTPUT
5V/A
VOUT = R~2R3IL

Current Monitor

the output monitor voltage accurately reflects the
power supply current flow:

Rl senses current flow of a power supply. The
J F ET is used as a buffer because I D = Is, therefore

TO COMPANION CHANNEL
FOR STEREO CIRCUIT

r----.---4II.----..

...- - _ + _ -...

-~

__O +15V

VOLUME
1 "F

~

10K
LINEAR
TAPER
2N4249

OUTPUT

":"

68K

1M

'·~:'ll

'"

2N3565

L-_ _ _~-----------~-~~----------~-~~----~~ -15V

'low Cost High level Preamp and Tone Control Circuit

This preamp and tone control uses the JFET to its
best advantage; as a low noise high input impedance device. All device parameters are non-critical
yet the circuit achieves harmonic distortion levels

of less than .05% with a SIN ratio of over 85 dB.
The tone controls allow 18 dB of cut and boost;
the amplifier has a 1 volt output for 100 mV input
at maximum level.

AN32-11

Rl
r---------4I~_o+12V

OUTPUT

INPUT o-~*'~

Precision Current Source

The 2N3069 JFET and 2N2219 bipolar serve as
voltage isolation devices between the output and
the current sensing resistor, R 1. The LM 101 provides a large amount of loop gain to assure that the
circuit acts as a current source. For small values of
current, the 2N2219 and 10k resistor may be eliminated with the output appearing at the source of
the 2N3069.

Schmitt Trigger

This Schmitt trigger circuit is "emitter coupled"
and provides a simple comparator action. The
2N3069 JFET places very little loading on the
measured input. The 2N3565 bipolar is a high hF E
transistor so the circuit has fast transition action
and a distinct hysteresis loop.

VIOEO INPUT

50n

2N4391

2N4391

+ SUPPL Y

VIDEO OUTPUT

50n

GOS = 5;unho max.

r - - " , - - - o V OUT

-10V

Low Power Regulator Reference

This simple reference circuit provides a stable voltage reference almost totally free of supply voltage
hash. Typical power supply rejection exceeds
100 dB.

AN32-12

High Frequency Switch

The 2N4391 provides a low on-resistance of
30 ohms and a high off-impedance «.2 pF) when
off. With proper layout and an "ideal" switch, the
performance stated above can be readily achieved.

»

:2
February 1970

I

W
W

l'>
Z

»
r

ANALOG-SIGNAL COMMUTATION

o

C)

INTRODUCTION

MOS IC STRUCTURE

Telemetry and other data-acquisition systems have
become very compact and efficient, particularly
when built with integrated circuits. To keep in
step, small, low-power commutators are needed to
multiplex large numbers of analog signals. Metaloxide-semiconductor field-effect transistors do the
job well.

MOS IC's generally provide four or more channels
in a monolithic chip, but two are enough to illustrate the basic construction that governs switch
operation. The cutaway view of Figure 1 shows
two complete MOSFET's, one of which may be on
while the other is off. Figure 2 is the schematic.

I

(J)

• Power dissipation is essentially zero in most
applications. No DC power is consumed in the
control gate, and practically no signal power is
dissipated in the switch.
• Offset voltage is zero in a well-designed switch.
• Resistance is reasonably low when the channel
is conducting.
• Resistance of an OFF channel is practically
open-circuit (R oFF is on the order of 10 12
ohms and leakage currents are very small, about
100 pAl.
•

Analog signals are well
switch-control signals.

isolated

from

the

With all of these things in their favor, MOS analog-switching IC's will come into much wider use,
especially in large, multichannel instrumentc:tion
and data-transmission systems.

N
Mechanical
Switch

Bipolar

Transistor

Photocell

Junction
FET

PMOS
FET

"On" Resistance

10-2n

Ion

1 Kn

30n

lOon

"Off" Leakage

10pA

loopA

10 nA

loopA

loopA

Offset Voltage

0

10- 2 V

0

0

0

Commutation Rate

1 KHz

100 KHz

100Hz

10MHz

50 MHz

Table 1
Comparison of Switches

Z

»
r
n

o

~
~

MOS IC's containing several MOSFET switching
channels are presently available in production
quantities and perform excellently as low-level
analog commutators if the system designer understands their limitations and exploits their advantages. This report will describe the DC characteristics involved in switching analog signals when the
signal input range varies between -10V and +10V.
MOSFET's size up very well against earlier switching devices when their overall characteristics are
considered (see Table 1 and the discussion of competitive devices). I n addition to being fabricated
easily as multichannel IC's-in some cases, complete with switching-control circuitry on the
chip-MOSFET's have several significant electrical
advantages:

C)

c:
-I

~
o

:2

"SUBSTRATE" OR
"BULK" CONNECTION

FIGURE 1. Cross-section of Two MOSFET's in an Integrated Circuit.

_-_~-oBUlK

INPUTI

INPUT2

GATE 2

_ _ _--QOUTPUT

o-------:r-

FIGURE 2. Schematic Diagram of Two-Channel Analog
Switch.

Both MOSFET's have a common substrate, the
"bulk" consisting of lightly doped N type silicon.
Thermally grown silicon oxide covers the entire
chip surface, except where the oxide was etched
away to allow ohmic connections of input and
output electrodes to stripes diffused with P+
dopants. These stripes are the MOSFET drain and
source regions. Each gate is defined by the gate
electrode, which lies over a channel region and is
isolated from it by the oxide (hence, MOSFET's
are sometimes called insulated-gate FET's or
IGFET's).
All electrodes are etched from a thin film of
deposited aluminum. Each MOSFET has separate
input and gate electrodes, but the output electrodes may be paired as shown, connected to a
common output pin, or connected to separate output pins on the package. The same basic MOSFET

AN33-1

structure can be used, whether the circuit is a
differential switch, a multiplexer, or independent
switches in a single package (see Figure 3).

Rs

DATA INPUT
!IOV SWING

T ~"

SWITCH CONTROL
+10V (OFF)
-20V toN)

FIGURE 4. Biases on Single MOS Channel at Maximum
Signal Range of ±10V.
BULK
NOTE PIO 5 connected to case and devICe bulk

BULK
NOTE' Pin 5 connected to case and devICe bulk.

MM450, MM550

MM451, MM551

The applied biases are those that would be used at
an analog signal range of ± 1OV. At any signal
range, the following guidelines apply:

1. Bulk bias

VB B must equal or be more .positive
than the most positive excursion of the analog
signal. This bias must be maintained at all
times, so is taken from a DC supply.

BULK

NOTE: Pins I and 8 connected to case and device bulk.
MM452, MM552

FIGURE 3. Connection Diagrams of Dual Differential
Switch, Four-Channel Switch and Quad MOS
Transistor.

MOSFET's are, for practical purposes, bilaterally
symmetrical. The drain (or source) can be either
the input or output. By strict definition, the drain
is the electrode to which majority-carrier current
flows. The majority carriers are "holes" in the
channel of P-channel MOSFET's (N-channel
MOSFET's are not commonly used in MOS IC's).
In most analog switching applications, the signal
contains AC components, so the direction of current flow frequently alternates.

SWITCHING AND ISOLATION
A P-channel MOSF ET turns on when negative voltage is applied between gate and source. The gate is
biased negative with respect to the bulk. Electrons
accumulate on the gate, creating positive charges
in the channel region. This inverts the electric
charge thus creating an "enhanced" P type channel
in the n-type semiconductor. When the gate is
several volts more negative than threshold, a conducting channel is formed, allowing majority
carrier current (holes) to flow freely between
source and drain. The channel is said to be "enhanced," so these MOSFET's are called P-channel
enhancement MOSFET's.

Operating voltages in a typical switching channel
are illustrated in Figure 4. In most schematics, the
bulk connection would not be shown.

AN33-2

2. To turn the switch ON and make Ro N low, the
voltage applied to the gate should be at least
5V more negative than the most negative excursion of the analog signal (1 OV is desirable). The
actual gate voltage is VG G and the gate bias is

-V GB ·

3. To ensure that the switch turns OFF fully,
VGG should be as positive as V BB making
VG B = O.
The first rule must be followed to get good performance from the switch. With VB B most positive, the p-n junctions are kept reverse-biased.
When the channel is OFF, this condition isolates
the drain from the source. When the switch is
turned ON and the P-channelis enhanced, the
drain-channel-source region is isolated by the p-n
junction from the substrate because the substrate
is "reverse biased" from all of these regions at all
times.
The voltage across the switch, from drain to
source, is caused by I R drop whether the switch is
on or off. The MOS analog switch does not have
any inherent offset voltage. To get V au t = V in in a
MOSFET switch merely requires that load resistance R L be much larger than the resistance in the
conducting channel, Ro N. Since R L is generally
about 100 kilohms in most high-accuracy analog
commutator applications, the requirement is easily
met.
Figure 5 helps clarify rules (2) and (3). This curve
shows how the gate-source threshold voltage
changes with bulk-source bias voltage. Channel resistance is high and current flow at the output can
only be a few microamperes. A forward bias higher
than threshold is needed to enhance the channel.
Making gate bias much more negative than V TH at
turn-ON does this. Then, at turn-OF F, the gate
bias becomes more positive than V T H when
V G G = VB B· The channel must revert to N-type
silicon thus preventing majority carrier current
flow.

./

family of National Semiconductor's
MM450/MM550 MOS switching IC's). The "bipolar" family in Figure 6c shows what happens
when Vos is allowed to go positive.

~

/

"

;

,-,

I

>

/

10

15

20

V. ULK TO SOURCE

FIGURE 5. Variation in Switching-Threshold Voltage
with Changes in BUlk-to-Source Bias Voltage.

The circuit designer must use biases that prevent
the drain from having a positive potential when
the switch is OFF. For example, V in = +10V and
VB B = +9V should not be allowed. Operating with
Vos = +lV won't harm the MOSFET, but some of
the signal will appear at the output. Effects of
improper biasing can be seen in Figure 6. With
the source and bulk grounded while Vos varies,
output currents at different gate biases are measured to produce the "drain family of curves."
The normal family looks like Figure 6b (the drain

During small excursions of Vos, the MOSFET acts
as a voltage-variable resistor. But when Vos rises
to about +0.6V, there is an abrupt increase in
drain current. At this point, the diode drop is
exceeded and the drain-bulk junction becomes
forward biased. Minority carriers are injected into
the n-type channel region, causing grounded-base
pnp bipolar transistor action (note in Figure 1 that
a MOSFET resembles a lateral pnp transistor in the
OFF condition). Output current will be (X times
the input current. In most MOS devices, the amplification factor will be 0.5 to 0.9.
It is absolutely mandatory that the V os 2. +0.6V
be avoided. Otherwise the effective Ro F F will be
poor and the channel will seem to have abnormally
high leakage current.
Only the upper right corner of the graph in
Figure 6b, detailed in the third quadrant of
Figure 6c, is useful in practical circuit designs. The
useful characteristics are to the right of -Vos =-1
and above a load line at about 10 = 0.5 mAo
ON AND OFF RESISTANCE
Both Ro Nand Ro F F normally vary with signal
voltage and operating temperature. A positive
signal voltage improves channel enhancement by
making the gate more negative with respect to
drain and source.

6a

::::;;

-5

C
.!
...

l.- I -

-10

....-

-15

~ -20
a:
Z

~

-=

-30

~

~ -40

/,

~

,~

~

~
-It:; t?
-13.5

];I'

'I---:f.::::::f:::::=P

,

-45
-50
-100

l./

~~

~

-35

'--...,.II!

-6

~ --:-7,5

.6"" b==

a ~25

~5

-80

VGs =-15V-

-60

-40

~20

Ro N is minimum at the most positive signal level.
It will increase slowly with temperature, since high
temperatures reduce the mobility of majority carriers. Neverthless, Ro N will have little effect on
signal quality if R L is much larger. Ro N does vary
nonlinearly, though, so we investigated its effect
upon signal quality. Figure 7 proves that the effect
Total Harmonic Distortion vs VDS
10

--

Vos - DRAIN TO SOURCE VOLTAGE - VOLTS

Y'N = -10vl

7

Y'N = +10V

6b

V'

/
I
1/
I
,/ Y'N = -5~
I
I Y'N = OV ~
Y

Dynamic RON

il

,A~

/1

......r

"--~

~~
Y'N =+5V

<
.!

VOS - RMS (V)

z

FIGURE 7. Small-Signal Harmonic Distortion (Measured
with Only About 100 Ohms Load
Resistance).
-0.6

-0.2
llV

+0.2

,N

+0.6

+1.0

(V)

6c

FI GURE 6. Drain-Current Measuring Circuit, Normal
Drain Family of Curves, and "Bipolar" Drain
Family of Curves.

is negligible provided that the biasing rules are
observed.
The curves of small-signal harmonic distortion in
Figure 7 were measured with practically no load
resistance. AC signals at various voltages were

AN33-3

Worst-case Ro N can be expected at a -1OV input.
Figure 8 gives the change in RON of the
MM450/MM550 series devices when the analog
input is at +10V, OV and -10V. If lower impedance is essential, the gate can be biased more
negative. For instance, at V BB = +10V, VGG can
be made -25V or -30V instead of -20V, increasing -V G B to -35V or -40V. Don't go over
the specificed maximum bias, which is usually
-45V, because excessive bias could reduce the
device operating life.

applied to the MOSFET input and the current
flow was measured at the output with the help of
a 100-ohm current-sensing resistor. Distortion
levels less than 0.1% could not be measured with
available instruments. The anomaly in the +10V
curve is due to diode distortion of the type illustrated in Figure 6c. The input signal's AC plus DC
com po n en t sex c e ed edt h e b u I k v 0 I t a ge,
V BB = +10V, by more than the +0.6V diode drop.
The harmonic distortion is amply low for practical
applications. With a 1-kilohm load, the small-signal
distortion typically would be less than 0.5%, with
V in = ±10V and Vos almost ±1V. A load of
1 kilohm is unusually small. Small signal distortion
would be almost unmeasurable with a 10-kilohm
load. When signal accuracy must be very high,
100 kilohms are used by some designers.

Conversely, all biases can be reduced if the signal
voltage range is less than ± 1OV. The gate-drive
circuit will not have to swing as far, the switch can
be operated faster, and switching transients will be
smaller. Or, the bulk bias can be reduced and the
gate bias maintained at the previous ON level. This

CONOITION 1:
ANALOG INPUT VOL TAGE
AT +10 VOL TS
10.000

Vee = +10V

"" --ur
1 ,
T
+10V

Dynamic RON

RON vs VGG

OUT

1000

j

i

~~: :::~~~

.....

z

o

a::

TA - 5 5 ° C - = =
--zt2=T A =25°C - - ~;=TA =on - - - -

~~

100

10

-0

+0

-16

-0.6

-22

-0.2

VGG (V)

CONOITION 2:
ANALOG INPUT VOL TAGE
ATOVOlTS

+{).6

. +1.0

Dynamic RON

RON vs VGG
10

Vee+ 10V

"" --ur
i
T

+{).2

"VIN (V)

r-~~-'-'~~~-r~

o

VOUT

OV

10 L......JL-lL-lL-l--l.--L--L-L-L....J

o

-4

-0

-12

-16

-0.6

-20

-0.2

VGG (V)

CONDITION 3:
ANALOG INPUT VOL TAGE
AT -10 VOL TS

-10V

10

VOUT

I
I

Vee = +10V
VIN = -10V

o

.1

II_

r-

=-

=. VGG = -11V

1

VGG = -16V

I ..... ~ f!f.

;::. =:;~ ~I

.... .....'" 1\"~

'-...'--

100 L-L-...l.-......L-L--.l_L-...l-....J
-11

-10
VGG (V)

-19

-20

10
-1.0

~

::

V~G = -10V_ VGG = -19V
VGG = -20V- -

~

:--

-

I
-0.6

-0.2

+0.2

,~VIN (V)

FIGURE 8. Typical RON Characteristics of MM450/MM550 MOS Devices at Most Positive, Zero and Most Negative
Signal Voltages.

AN33-4

+1.0

VOUT = -10V

I-~

-16

+0.6

Dynamic RON

RON vs VGG

Vee +10V

"" --ur
1
T

+0.2

"VIN (V)

+0.6

+1.0

will give the effect shown in Figure 9-an improvement in channel enhancement and reductions in
Ro N at the various signal levels.
RON vs VGG
10,000

Channel leakage is measured with the test circuit
in Figure 11a. At V in = +10V, the leakage at the
output is at its maximum positive value. As V in
goes more negative than +1 OV, channel leakage
decreases, goes through zero, and becomes negative,
as in Figure 11 b.

V BB - 5V

. l - - t-+- f-I-+-t- IWVBB=7,5V~
VBB = 10V

1000
80 pA

+10V

I
2

0

~

100

a:

....

~

VBB-OV=

- -

f-- VB1B - ~.5V

la

OUTPUT LEAKAGE
CURRENT

-

+10V

-

V'N

J
o

-4

-40 pA
-8

-12

-16

-20

VGG (V)

-=

FIGURE 9_ Bulk Bias Effect on RON.

When the gate is turned OFF, impedance between
source and drain becomes very high
(R OFF ~ 10 12 ohms). A MOSFET's only significant DC conduction is leakage current. Total
leakage in MM450/MM550 devices is typically less
than 100 pA at 25°C. It rises more rapidly than
Ro N with increasing temperature, approximately
0
doubling with every 10 e rise in temperature.
However, the MM450 devices are low-leakage types
that are specified for use to 125°C. At the maximum temperature, leakage will usually be less than
100 nA. (At very high signal frequencies, another
conduction mechanism may occur-analog signal
feedthrough in the device capacitances, which can
be prevented by making the gate-driver impedance
low when the switch is OFF.)
The two significant forms of DC leakage are leakage from source and drain to bulk, and leakage
through the channel from input to output. When
all channels in the multiplexer are OFF, and the
outputs of each MOSFET are connected to a common package pin, total leakage will be the sum of
the bulk and channel leakages.
Worst-case leakage is measured with the circuit in
Figure 10. The pin at which the leakage current
is measured is biased to -25V and all other pins
are grounded. This is equivalent to the bulk being
biased at +10V, all gates at +10V, and all analogsignal inputs at +1OV, with the output at -15V.

-25V

FIGURE 10. Worst-Case Leakage Test Circuit and Typical Worst-Case Total Leakage of MM451 at
25°C.

11a

-80 pA

11b

FIGURE 11. Channel-Leakage Test Circuit and Variation
in Leakage with Signal Voltage.

The designer of switching systems that require
very high Ro F F values under all signal conditions
should anticipate the possibility of worst-case leakage. But average leakage will generally be considerably less than worst case. First, leakage currents in
each switch are voltage-sensitive, and will be less
than maximum at signal voltages less than +10V.
Secondly, when the analog signals on some channels are positive and those on other channels are
negative, the negative currents will subtract from
the positive currents, further reducing the total
leakage at the output, Also, when a switch is ON,
it would not be contributing to the leakage.
Assuming signal voltages vary randomly between
+10 and -10V, total leakage will run about half
that of worst case. Of course, leakage will be still
less if the analog signal limits are less than ±10V.
CONCLUSION
Integrated MOSFET switching circuits make excellent low-level analog commutators. Power dissipation is essentially zero, capacitance is reasonably low (typically 8 pF at the analog input), the
Ro F F IRo N ratio is high, and the control signal is
isolated from the input. MaS Ie's with four or
more switching channels are readily available in
production quantities.
Conventional bipolar drive circuitry can control
channel switching at rates in the megahertz range.
Hybrid integrated circuits containing monolithic
MaS multiplexers and bipolar drivers are being
manufactured for medium-speed applications
(NH0014 and NH0019). Level-changing circuits in
these devices allow external TTL or DTL IC's to
control the commutator at analog signal levels to
±10V. MaS commutator systems can be built with
building-block circuits such as the MM454F in
Figure 12. This monolithic IC can commutate at
rates to 1 MHz, depending on the range of signal
voltages. The control logic on the chip includes a
clock-countdown chain that facilitates submultiplexing.

AN33-5

ANALOG
INPUTS

4
ANALOG
OUTPUT

CLOCK
INPUT

OUTPUT

4:1
COUNTOOWN

RESET------4~--------'

FIGURE 12. logic Diagram of MM454F Four-Channel
MOS Multiplexer. Switches and Control
Circuitry Are Fabricated in the Same Monolithic Chip.

MOSFET switches are generally used to commutate low-frequency analog signals. Today, the
preferred device for R F-signal multiplexing is the
N-channel junction FET, which can handle signal
frequencies in the VHF range. MOS IC's have operated successfully, however, in some R F application. The high-frequency capabilities of MOS IC's
are being investigated by the author and will be
the subject of a future report.
Although the most outstanding feature of
MOSFET's is the ease with which they can be fabricated as multichannel monolithic IC's, their electrical characteristics compare quite favorably with
those of other switching components. An "order
of magnitude" comparison of MOSFET's and
other devices that cou Id be used for low-level
analog switching is given by Table 1. Better characteristics might be obtained in each case, but
these values are typical.
Each type of analog switch has advantages and
limitations that must be considered for practical
use. No switch is perfect. If a switch were perfect,
it would have zero resistance when ON, infinite
resistance when OFF, and be 100% efficient-that
is, it would consume no power.
Electrically, the mechanical switch comes close to
this ideal. It has the highest Ro F F IRo N ratio and
totally isolates the analog signal from the switching-control function. However, it has mechanical
drawbacks that make it noisy and unsuitable for

AN33-6

low-level commutation: contact bounce, conta.ct
pitting, susceptibility to vibration, and the necessity to move a physical mass to turnthe.switch on
or off. I t cannot commutate very fast and con-'
sumes more power than a solid-state switch, as a
rule.
Bipolar transistors make excellent digital switches,
the fastest ever developed, but they are usually a
poor choice for multiplexing low-level analog
signals. Their main disadvantages are an inherent
offset voltage and the impossibility of isolating the
switching control signal from the analog signal
being switched. Furthermore, analog switching
rates are slower than FET's. Their Ron is low,
though-typically 10 ohms in analog switches
(versus milliohms in power transistors). Bipolar
transistors fare much better in high-level switching,
where DC offset is not a problem.
Photocells make fairly good analog switches.
Because light is used as the control signal, the control is completely isolated from the analog electrical signal. However, Ro N is high and the
ROFF/RoN ratio is relatively poor. Even at
moderate Ro F F IRo N ratios, photocells cannot
commutate much faster than 100 Hz. After exposure to intense light, a photocell made with a
semiconductor such as cadmium sulfide or cadmium selenide exhibits a long turn-off decay time.
Photocell turn-off time constants may stretch out
for many seconds before R 0 F F reaches an acceptable level. Faster switches can be made with combinations of electroluminescent diodes and photot ran s i st 0 rs, but these dev ices are sti II very
expensive.
Some N-channel junction F ET' s come close to
being ideal switches. Offset voltage is zero, and the
admittance-to-input capacitance ratio Y fs/C;ss is
the highest of any contemporary device. These
two parameters govern commutation rate, which
can be very high if the impedances of the. signal
source and the load are made very low. Theoretically, the high majority-carrier mobility in an
N-channel J-FET enables it to operate at a frequency higher than any other type of FET. A
good example is the 2N4391: ROFF/RoN is
about 10 9 , Rds (on) is a maximum of 30 ohms,
and maximum leakage at 25°C is 100 pA. The one
major disadvantage of N-channel J-FET's is that
they are extremely difficult to make in the form
of multichannel IC's. For high-frequency commutation, the P-channel type of J-FET is a poor
choice because its majority carrier mobility is
lower than N channel J-FET's.

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March 1970

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HOW TO BIAS THE MONOLITHIC JFET DUAL

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The National Semiconductor monolithic JFET
dual is a unique device. Its unusual intertwined
geometry results in a very good matching characteristic and exceptional thermal tracking characteristic plus the fact that its drain currents may be
biased over a broad range without seriously affecting matching and tracking. FM1100 through
FM1111, FM1200 through FM1211, and FM3954
through FM3958 (similar to 2N3954 through
2N3958) are the device numbers for the monolithic JFET dual.
A typical National monolithic JFET dual's differential gate match i ng (A V G s) is less than 10m V
and temperature drift is typically less than
10 ,LtV t C. What drain current you use for biasing
is not critical, so you needn't even bother biasing
the unit to its zero T.C. drain current, as far as
AV GS matching and tracking are concerned.
ROS(on), Y fs , and loss track better than 1% over
the full specified temperature range (-55°C to
+125°C). The FM1100, FM1105, FM1200, and
FM1205 are specified at 2 mV(max) AV GS with a
drift of 5,LtV tC(max). There are specs available
which are less string~nt than these, but many of
the devices exceed this tough spec.
In order to obtain this performance advantage over
separate matched JFET die, the two JFETs must
be made such that there is one diffused "top" gate
for each of the devices and a "bulk" gate which is
common to both of the devices. (See Figure 1.)
Normally, single triode JFETs have the diffused
top gates internally connected to the bulk and this
bulk is used as the gate connectior,. There are a
few tetrode JFETs available with both the diffused

GATE 1

gate and substrate gate brought out separately.
The National monolithic JFET dual could be
called a "siamese tetrode". This unique configuration presents several alternatives for proper
biasing.

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BIAS SCHEMES

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If the bulk were ohmically connected to each gate,
all gates would be common. The dual would turn
into a differential switch, like the one in Figure.2,

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rINPUT

SCALING
RESISTORS

OUTPUT

FIGURE 2. Dual Differential Analog Switch.

and would not be a true dual. This switch, incidentally, is an excellent application of the FM 11 00,
FM 1200, and FM3954 series. When the gates are
tied externally, the near-perfect match of the
JFETs assures precision in analog switching and
multiplexing.

GATE 2

ti~4--.....,.-:::::-:;zj.~r- SOURCE 2
DRAIN 2
DRAIN 1
OXIDE

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P GATE

SUBSTRATE

FIGURE 1. Simplified Section of Monolithic JFET Dual

AN34-1

AGC CONTROL
One of the most obvious uses of the bulk gate is
AGC control because it is almost completely isolated from the signal path. The bulk bias voltage
affects 10 , VGS(off), and Y fs , but it does not
significantly affect V G S matching and tracking.
The diffused gates (G I and G 2 ) could be called the
differential mode gates and the bulk could be
called a common mode gate.

Figure 5. Common mode rejection is very poor
since the bulk gate is degenerative; it could become forward biased on positive common mode
swings and cut off both channels on negative common mode swings.

+V

..----n02

+V

~---~----~01

OUTPUT

Gl

-- - -

02

OUTPUT

01

-=8

INPUT

S2

SI

G2
G1 ().---It..._

INPUT

8

S2
'--_"'-"-_0
AGC

G2~--------~---------~

FIGURE 5. Substrate Bias, No Common-Mode Range.

For comparator applications, the bulk terminal
may be connected to the comparison voltage along
with gate 2. If the input varies over many volts (in
excess of VGS(off)), a 1M ohm resistor in series
with gate 1 wi II prevent excessive gate current in
the positive gate source forward bias situation or
the negative gate-bulk reachthrough breakdown
mode. Reachthrough breakdown will be covered
later.

FIGURE 3. Automatic Gain Control.

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+V

G2

.....SI
S2

r-.-_"'--"--~Io-O AGC

. .---.....c:l02
"---~----<)01

o

OUTPUT

_*+-.......... VOLTAGE
COMPARISON
SI ' - - _. . ._

.... S2

FIGURE 4. AGC Connections for Frequencies to 30 MHz.

OPERATIONAL AMPLI FI ER BIASING

FIGURE 6. Biasing for Comparator Applications.

In operational amplifier applications which do not
require any common mode rejection, biasing is
fairly simple. The most straightforward biasing
method is to simply ground the bulk as shown in

For special applications where very low leakage is
desirable, drain-gate voltage should be kept as low
as possible but in excess of pinchoff and drain

AN34-2

current should be at 100 /lA or less. Figure 7 uses
the bulk to bias the monolithic JFET dual so that
gate-source voltage is zero, thus eliminating that
leakage component. The gates must be operated at
or very close to ground potential; the LM101A is
used for feedback biasing to force the source voltage to ground, using the bulk gate to control
source voltage.

+V

G1 0--"""1"1"'""..
INPUT

G2~-------+------r-----+-----~

+V

OUTPUT

.----0o2
~------~----------....-

lOOK

OUTPUT

RJ

SOK
SOUARE
~""""WAVE

OUTPUT*
R4

47K

FIGURE 9. Crystal-Controlled Oscillator
-TTL or

on Fanout of two.

minimize loading of the crystal and contribute to
frequency stability. As shown, the oscillator
del ivers a 100 kHz square-wave output.

FIGURE 8. Free·Running Multivibrator

The frequency of osciUation depends almost
entirely on the resistance and capacitor values
because of the precision: of the comparator. Further, the freql,Jency changes by only 1% for a 10%
change in supply voltage. Waveform symmetry is
also good, but the symmetry can be varied by
changing the ratio of R 1 to R 2 •

FREQUENCY dOUBLER
In a digital system, it is a relatively simpl e matter
to divide, by any integer. However, multiplying by
an integer is quite another story especially if
operation over a wide frequency range and
waveform symmetry are requ ired.

A crystal-controlled oscillator that can be used to
generate the clock in slower digital systems is
shown in Figure 9. It is similar to the free running

A frequency doubler that sati'sfies the above
requirements is shown in Figure 10. A com par-

V+ = sv

Rl
10K

INPUT---+--~

R6

S.lK

1/4DM5486
OUTPUT

FREQUENCY RANGE
INPUT -S kHz to SO kHz
OUTPUT - 10 kHz to 100 kHz

FIGURE 10. Frequency Doubler

AN41:"'4

ator is used to shape the input signal and feed it to
an integrator. The shaping is required because the
input to the integrator must swing between the
supply voltage and ground to preserve symmetry
in the output waveform. An LM 108 op amp, that
works from the 5V logic supply, serves as the
integrator. This feeds a triangular waveform to a
second comparator that detects when the waveform goes through a voltage equal to its average
value. Hence, as shown in Figure 11, the output

FIRST COMPARATOR
OUTPUT

INTEGRATOR OUTPUT

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L...J
L...J

SECOND COMPARATOR...,
OUTPUT

CIRCUIT OUTPUT

LJ1J1JlJ

FIGURE 11. Waveforms for the Frequency Doubler

of the second comparator is delayed by half the
duration of the input pulse. The two comparator
outputs can then be combined through an exclusive-O R gate to produce the double-frequency
output.
With the component values shown, the circuit
operates at frequencies from 5 kHz to 50 kHz.
Lower frequency operation can be secured by
increasing both C 1 and C 2 .

APPLICATION HINTS
One of the problems encountered in using earl ier
IC comparators like the LM710 or LM106 was
that they were prone to erratic operation caused
by oscillations. This was a direct result of the high
speed of the devices, wh ich made it mandatory to
provide good input-output isolation and lowinductance bypassing on the supplies. These oscillations could be particularly puzzling when they
occurred internally, showing up at the external
terminals only as erratic dc characteristics.
In general, the LM111 is less susceptible to spurious oscillations both because of its lower speed
(200 ns response time vs 40 nsl and because of its
better power supply rejection. Feedback between
the output and the input is a lesser problem with a
given source resistance. However, the LM 111 can
operate with source resistances that are orders of
magnitude higher than the earlier devices, so stray
coupling between the input and output should be
minimized. With source resistance.s between 1 kn
and 10 kn, the impedance (both capacitive and
resistivel on both inputs should be made equal, as
this tends to reject the signal fed back. Even so, it
is difficult to completely eliminate oscillations in
the linear region with source resistances above

10 kn, because the 1 MHz open loop gain of the
comparator is about 80 dB. However, this does not
affect the dc characteristics and is not a problem
unless the input signal dwells within 200 /lV of the
transition level. But if the oscillation does cause
difficulties, it can be eliminated with a small
amount of positive feedback around the comparator to give a 1 mV hysteresis.
Stray coupl ing between the output and the balance terminals can also cause oscillations, so an
attempt should be made to keep these leads apart.
It is usually advisable to tie the balance pins
together to minimize the effect of this feedback. If
balancing is used, the same result can be accomplished by connecting a 0.1 /IF capacitor between
these pins.
Normally, individual supply bypasses on every
device are. unnecessary, although long leads between the comparator and the bypass capacitors
are definitely not recommended. H large c~.Jrrent
spikes are injected into the supplies in switching
the output, bypass capacitors should be included
at these points.
When driving the inputs from a low impedance
source, a limiting resistor should be placed in series
with the input lead to limit the peak current to
something less than 100 mAo This is especially
important when the inputs gO outside a piece of
equipment where they could accidentally be
connected to high voltage sources. Low impedance
sources do not cause a problem unless their output
voltage exceeds the negative supply voltage.
However, the suppl ies go to zero when they are
turned off, so the isolation is usually needed.
Large capacitors on the input (greater than 0.1 ,uFI
should be treated as a low source irnpedance and
isolated with a resistor. A charged capacitor can
hold the inputs outside the supply voltage if the
supplies are abruptly shut off.
Precautions should be taken to insure that the
power supplies for this or any other IC never
become reversed-even under transient conditions.
With reverse voltages greater than 1 V, the I C can
conduct excessive current, fuzing internal aluminum interconnects. This usually takes more than
0.5A. If there is a possibility of reversal, clamp
diodes with an adequate peak current rating
should be installed across the supply bus.
No attempt should be made to operate the circuit
with the ground terminal at a voltage exceeding
either supply voltage. Further, the 50V outputvoltage rating applies to the potential between the
output and the V- terminal. Therefore, if the
comparator is operated from a negative supply, the
maximum output voltage must be reduced by an
amount equal to the voltage on the V- terminal.
The output circuitry is protected for shorts across
the load. It will not, for example, withstand a

AN41-:-5

short to a voltage more negative than the ground
terminal. Additionally, with a sustained short,
power dissipation can become excessive if the
voltage across the output transistor exceeds
about 10V.
The input terminals can exceed the positive supply
voltage without causing damage. However, the
30V maximum rating between the inputs and the
V- terminal must be observed. As mentioned
earlier, the inputs should not be driven more
negative than the V- terminal.
CONCLUSIONS
A versati Ie vol tage comparator that can perform
many of the precision functions required in digital
systems has been produced. Unlike older comparators, the I C can operate from the same supply
voltage as the digital circuits. The comparator is
particularly useful in circuits requiring considerable sensitivity and accuracy, such as threshold
detectors for low level sensors; data transmission
circuits or stable oscillators and multivibrators.

AN41-6

The comparator can also be used in many analog
systems. It operates from standard ±15V op amp
suppl ies, and its dc accuracy equals some of the
best op amps. It is also an order of magnitude
faster than op amps used as comparators.
The new comparator is considerably more flexible
than older devices. Not only will it drive RTL,
DTL and TTL logic; but also it can interface with
MOS logic or deliver ±15V to FET analog
switches. The output can switch 50V, 50 mA
loads, making it useful as a driver for relays, lamps
or light-emitting diodes. Further, a unique output
stage enables it to drive loads referred to either
supply or to ground and provide ground isolation
between the comparator inputs and the load.
The LM111 is a plug-in replacement for comparators like the LM710 and LM 106 in applications
where speed is not of prime concern. Compared to
its predecessors in other respects, it has many
improved electrical specifications, more design
flexibility and fewer application problems.

:t>

2:
February 1971

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IC PROVIDES ON-CARD REGULATION
FOR LOGIC CIRCUITS

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INTRODUCTION
Because of the relatively high current requirements
of digital systems, there are a number of problems
associated with using one centrally-located regulator. Heavy power busses must be used to
distribute the regulated voltage. With low voltages
and currents of many amperes, voltage drops in
connectors and conductors can cause an appreciable percentage change in the voltage del ivered
to the load. This is aggravated further with TTL
logic, as it draws transient currents many times the
steady-state current when it switches.
These problems have created a considerable interest in on-card regulation, that is, to provide local
regulation for the subsystems of the computer.
Rough preregulation can be used, and the power
distributed without excessive concern for line
drops. The local regulators then smooth out the
voltage variations due to line drops and absorb
transients.
A monolithic regulator is now available to perform
this function. It is quite simple to use in that it
requires no external components. The integrated
circuit has three active leads-input, output and
ground-and can be suppl ied in standard transistor
power packages. Output currents in excess of 1 A
can be obtained. Further, no adjustments are
required to set up the output voltage, and overload
protection is provided that makes it virtually
impossible to destroy the regulator. The simplicity
of the regulator, coupled with low-cost fabrication
and improved .reliability of monolithic circuits,
now makes on-card regulation quite attractive.

DESIGN CONCEPTS
A useful on-card regulator should include everything within one package-including the powercontrol element, or pass transistor. The author has
previously advanced arguments against including
the pass transistor in an integrated circuit regulator. 1 First, there are no standard multi-lead
power packages. Second, integrated circuits necessarily have a lower maximum operating temperature, because they contain low-level circuitry. This
means that an Ie regulator needs a more massive
heat sink. Third, the gross variations in chip
temperature due to dissipation in the pass transistors worsen load and line regulation. However, for
a logic-card regulator, these arguments can be
answered effectively.

en
For one, if the series pass transistor is put on the
chip, the integrated circuit need only have three
terminals. Hence, an ordinary transistor power
package can be used. The practicality of this
approach depends on eliminating the adjustments
usually required to set up the output voltage and
limiting current for the particular application, as
external adjustments require extra pins. A new
solid-state reference, to be described later, has
sufficiently-tight manufacturing tolerances that
output voltages do not always have to be
individually trimmed. Further, thermal overload
protection can protect an Ie regulator for virtually
any set of operating conditions, making currentlimit adjustments unnecessary.
Thermal protection limits the maximum junction
temperature and protects the regulator regardless
of input voltage, type of overload or degree of
heat sinking. With an external pass transistor, there
is no convenient way to sense junction temperature so it is much more difficult to provide
thermal limiting. Thermal protection is, in itself, a
very good reason for putting the pass transistor on
the chip.

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When a regulator is protected by current limiting
alone, it is necessary to limit the output current to
a value substantially lower than is dictated by
dissipation under normal operating conditions to
prevent excessive heating when a fault occurs.
Thermal limiting provides virt'ually absolute protection for any overload condition. Hence, the
maximum output current under normal operating
conditions can be increased. This tends to make up
for the fact that an Ie has a lower maximum
junction temperature than discrete transistors.
Additionally, the 5V regulator works with relatively low voltage across the integrated circuit.
Because of the low voltage, the internal circuitry
can be operated at comparatively high currents
without causing excessive dissipation. Both the
low voltage and the larger internal currents permit
higher junction temperatures. This can also reduce
the heat sinking required-especially for commercial-temperature-range parts.
Lastly, the variations in chip temperature caused
by dissipation in the pass transistor do not cause
serious problems for a logic-card regulator. The
tolerance in output voltage is loose enough that it

AN42-1

n

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en

is relatively easy to design an internal reference
that is much more stable than required, even for
temperature variations as large as 150°C.

Conditions for temperature compensation can be
derived starting with the equation for the emitterbase voltage of a transistor which .is 2

CIRCUIT DESCRIPTION
The internal voltage reference for this logic-card
regulator is probably the most significant departure from standard design techniques. Temperature-compensated zener diodes are normally used
. for the reference. However, these have breakdown
voltages between 7V and 9V which puts a lower
limit on the input voltage to the regulator. For low
voltage operation, a different kind of reference is
needed.
The reference in the LM 109 does not use a zener
diode. Instead, it is developed from the highlypredictable emitter-base voltage of the transistors.
In its simplest form, the reference developed is
equal to the energy-band-gap voltage of the
semiconductor material. For silicon, this is
1.205V, so the reference need not impose minimum input voltage limitations on the regulator.
An added advantage of this reference is that the
output voltage is well determined in a production
environment so that individual adjustment of the
regulators is frequently unnecessary.

(1 )

nkT
To
kT
Ie
+--Iog - + - I o g q
e T
q
e leo '
Where V gO is the extrapolated energy-band-gap
voltage for the semiconductor material at absolute
zero, q is the charge of an electron, n is a constant
which depends on how the transistor is made
(approximately 1.5 for double-diffused, NPN
transistors), k is Boltzmann's constant, T is
absolute temperature, Ie is collector current and
V B EO is the emitter-base voltage at To and leo.
The emitter-base voltage differential between two
transistors operated at different current densities is
given b y 3
.

(2)

where J is current density.
A simplified version of this reference is shown in
Figure 1. In this circuit, Q 1 is operated at a

Referring to Equation (1), the last two terms are
quite small and are made even smaller by making
Ie vary as absolute temperature. At any rate, they
can be ignored for now because they are of the
same order as errors caused by nontheoretical
behavior of the transistors that must be determined empirically.
If the reference is composed of VB E plus a voltage
proportional to ~ VB E, the output voltage is
obtained by addi ng (1) in its simpl ified form to
(2):

...... ...
~

--~--41.-

V ref = V90 (1

Figure 1. The Low Voltage Reference in One of Its Simpler
Forms.

-~)+
VBEO(~)+ kT
loge ~.
T o T0
q
J

Differentiating with respect to temperature yields
aV ref

VgO

aT

To

--= - -

relatively high current density, The current density
of Q 2 is about ten times lower, and the
emitter-base voltage differential (~V BE) between
the two devices appears across R 3 . If the
transistors have high current gains, the voltage
across R2 will also be proportional to ~VBE' Q 3 is
a gain stage that will regulate the output at a
voltage equal to its emitter base voltage plus the
drop across R 2 . The emitter base voltage of Q 3 has.
a negative temperature coefficient wh i Ie the ~ VB E
component across R2 has a positive temperature
coefficient. It wi II be shown that the output
voltage will be temperature compensated when the
sum of the two voltages is equal to the energyband-gap vol tage.

AN42-2

(3)

2

GROUNO

V BEO k
J1
+ - - +- loge - .
To
q
J2

(4)

For zero temperature drift, this quantity should
equal zero, giving

The first term on the right is the initial emitter-base
voltage while the second is the component
proportional to emitter-base voltage differential.
Hence, if the sum of the two are equal to the
energy-band-gap voltage of the semiconductor, the
reference wi II be temperature-compensated.

A simplified schematic for a 5V regulator is given
in Figure 2. The circuitry produces an output
voltage that is approximately four times the basic
reference voltage. The emitter-base voltage of Q3,
Q4, 0 5 and Q8 provide the negative-temperaturecoefficient component of the output voltage. The
voltage dropped across R3 provides the positivetemperature-coefficient component. Q 6 is operated at a considerably higher current density than
Q7, producing a voltage drop across R4 that is
proportional to the emitter-base voltage differential of the two transistors. Assuming large
current gain in the transistors, the voltage drop
across R3 will be proportional to this differential,
so a temperature-compensated-output voltage can
be obtained.

the output voltage is developed across Rs by the
collector current of Q7' The emitter-base voltage
differential is produced by operating Q 4 and Q 5 at
high current densities while operating Q 6 and Q 7
at much lower current levels. The extra transistors
improve tolerances by making the emitter-base
voltage differential larger. R3 serves to compensate
the transconductance 4 of 0 5 , so that the ~ VB E
component is not affected by changes in the
regulator output voltage or the absolute value of
components.
The voltage gain for the regulating loop is provided
by Q10, with 0 9 buffering its input and 0 11 its
output. The emitter base voltage of Q9 and 0 10 is
added to that of 0 12 and 0 13 and the drop across
Rs to give a temperature-compensated, 5V output.
An emitter-base-junction capacitor, C 1 , frequency
compensates the circuit so that it is stable even
without a bypass capacitor on the output.

r - - - -...- - -...---INPUT

I~

. . -.. .

--_~Vv

-OUTPUT

The active collector load for the error amplifier is
Q17' It is a multiple-collector lateral PNP4. The
output current is essentially equal to the collector
current of O 2, with current being suppl ied to the
zener diode controlling the thermal shutdown, D 2 ,
by an auxiliary collector. Q 1 is a collector FET4
that, along with R 1, insures starting of the
regulator under worst-case conditions.
The output current of the regulator is limited
when the voltage across R 14 becomes large enough
to turn on Q14' This insures that the output
current cannot get high enough to cause the pass
transistor to go into secondary breakdown or
damage the aluminum conductors on the chip.
Further, when the voltage across the pass transistor exceeds 7V, current through R 15 and D3
reduces the limiting current, again to minimize the

L - -....--4~--. .- - - GROUND

, - -........- - -........- - - - - . - - -.......-.--INPUT

Figure 2. Schematic Showing Essential Details of The 5V
Regulator.

. I - - - - -.......-+---t----+-OUTPUT

In this circuit, Os is the gain stage providing
regulation. Its effective gain is increased by using a
vertical PNP, Q9, as a buffer driving the active
collector load represented by the current source.
Q9 drives a modified Darlington output stage (Q1
and O 2 ) which acts as the series pass element. With
this circuit, the minimum input voltage is not
limited by the voltage needed to supply the
reference. I nstead, it is determi ned by the output
voltage and the saturation voltage of the Darlington output stage.
Figure 3 shows a complete schematic of the
LM109, 5V regulator. The ~VBE component of

D4
6.3V

L....---t---4--........-

........---

S
Q

TO·3:-+-t--+-t--i
VOUT = 4.5V
0L.--'-_"---'-_.4..---L.----J
5
10
15
20
25
30
35
INPUT VOL TAGE (V)

Figure 4. Current·Limiting Characteristics.

Even though the current is limited, excessive
dissipation can cause the chip to overheat. I n fact,
the dominant failure mechanism of solid state
regulators is excessive heating of the semiconductors, particularly the pass transistor. Thermal
protection attacks the problem directly by putting
a temperature regulator on the IC chip. Normally,
this regulator is biased below its activation
threshold; so it does not affect circuit operation.
However, if the chip approaches its maximum
operating temperature, for any reason, the temperature regulator turns on and reduces internal
dissipation to prevent any further increase in chip
temperature.
The thermal protection circuitry develops its
reference voltage with a conventional zener diode,
D 2 . 0 16 is a buffer that feeds a voltage divider,
del ivering about 300 m V to the base of 0 15 at
0
175 C. The emitter-base voltage, 0 15 , is the actual
temperature sensor because, with a constant
voltage applied across the junction, the collector
current rises rapidly with increasing temperature.

protect the load from damage. The regulator is
also designed so that it is not damaged in the event
the unregulated input is shorted to ground when
there is a large capacitor on the output. Further, if
the input voltage tries to reverse, D1 will clamp
this for currents up to 1A.
The internal frequency compensation of the
regulator permits it to operate with or without a
bypass capacitor on the output. However, an
output capacitor does improve the transient
response and reduce the high frequency output
impedance. A plot of the output impedance in
Figure 5 shows that it remains low out to 10 kHz
even without a capacitor. The ripple rejection also
remains high out to 10kHz, as shown in Figure 6.
The irregularities in this curve around 100 Hz are
caused by thermal feedback from the pass transistor to the reference circuitry. Although an output
capacitor is not required, it is necessary to bypass
the input of the regulator with at least a 0.22 fJ.F
capacitor to prevent oscillations under all conditions.

10'
Y'N = 10V

TA = 25°C

Another protective feature of the regulator is the
crowbar clamp on the output. If the output
voltage tries to rise for some reason, D4 will break
down and limit the voltage to a safe value. If this
rise is caused by failure of the pass transistor such
that the current is not limited, the aluminum
conductors on the chip will fuse, disconnecting the
load. Although this destroys the regulator, it does

AN42-4

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!==i
10-2
10

I/V

IL = 50~ mA

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100

lk

10k

lOOk

1M

FREQUENCY (Hz)

Figure 5. Plot of Output Impedance As A Function of
Frequency.

100

~

.----,-.---r--.-.,......--,

80

zQ

t
Although some form of thermal protection can be
incorporated in a discrete regulator, IC's have a
distinct advantage: the temperature sensing device
detects increases in junction temperature within
milliseconds. Schemes that sense case or heat-sink
temperature take several seconds, or longer. With
the longer response times, the pass transistor
usually blows out before thermal limiting comes
into effect.

I

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60 r-~---r--~~~~

a:
w

...
-'

~

40

I L =200mA
Y'N = 10V
I:;V ,N = 3V pop
20 L......---'_--L._-'-_-'---I
10
100
lK
10K
lOOK"
1M
FREQUENCY (Hz)

Figure 6. Ripple Rejection of The Regulator.

Figure 7 is a photomicrograph of the regulator
chip. It can be seen that the pass transistors, which
must handle more than 1 A, occupy most of the
chip area. The output transistor is actually broken
into segments. Uniform current distribution is
insured by also breaking the current limit resistor
into segments and using them to equalize the

currents. The overall electrical performance of this
Ie is summarized in Table 1.

Although the LM 109 is designed as a
regulator, it is also possible to use
adjustable regulator for higher output
One circuit for doing this is shown in

fixed 5V
it as an
voltages.
Figure 9.

~-4t--OUTPUT

INPUT-"'-~

Cl
0.221JF

Figure 9. Using The LM109 As An Adjustable-Output
Regulator.

Figure 7. Photomicrograph of The Regulator Shows That
High Current Pass Transistor (Right) Takes More
Area Than Control Circuitry (Left).

TYP

CONDITIONS

PARAMETER

5.0V

Output Voltage
Output Current

1.5A

Output Resistance

0.03D

Line Regulation

7.0V:::; V'N :::; 35V

0.005%/V

Temperature Drift

-55°C:::; TA :::; 125°C

0.02%i"C

= lA

6.5V

Minimum Input Voltage

lOUT

Output Noise Voltage

10 Hz :::;.f:::; 100 kHz

40,uV

Thermal Resistance
Junction to Case

LM109H (TO·5)
LM109K (TO·3)

3°C/W

The regulated output voltage is impressed across
R1 , developing a reference current. The quiescent
current of the regulator, coming out of the ground
terminal, is added to this. These combined
currents produce a voltage drop across R2 which
raises the output voltage. Hence, any voltage above
5V can be obtained as long as the voltage across
the integrated circuit is kept within ratings.
The LM 109 was designed so that its quiescent
current is not greatly affected by variations in
input voltage, load or temperature. However, it is
not completely insensitive, as shown in Figures 10
and 11, so the changes do affect regulation
somewhat. This tendency is minimized by making
the reference current through R 1 larger than the
quiescent current. Even so, it is difficult to get the
regulation tighter than a couple percent.

15¢C/W

Table 1. Typical Characteristics of The Logic-Card Regulator: T A = 25°C.

c

,g
..... 5.5
z
a:
a:
u

:::>

~

APPLICATIONS

5.0

:;

Because it was designed for virtually foolproof
operation and because it has a singular purpose,
the LM109 does not require a lot of application
information, as do most other linear circuits. Only
one precaution must be observed: it is necessary to
bypass the unregulated supply with a 0.22 pF
capacitor, as shown in Figure 8, to prevent

d

4.5
10

15

20

25

INPUT VOLTAGE (V)

Figure 10. Variation of Quiescent Current With Input
Voltage At Various Temperatures_

6.0
V'N = 10V

INPUT-"--I

OUTPUT

Cl
0.221JF

/::-..-

I
IL = 0
~~

I

IL=l~

~

~~

~

Figure 8. Fixed 5V Regulator
4.5
-75 -50 -25 0

oscillations that can cause erratic operation. This,
of course, is only necessary if the regulator is
located an appreciable distance from the filter
capacitors on the output of the dc supply.

25 50

75 100 125 150

JUNCTION TEMPERATURE (C)

Figure 11_ Variation of Quiescent' Current With Temperature For Various Load Currents.

AN42-.5

The LM 109 can also be used as a current regulator
as is shown in Figure 12. The regulated output
voltage is impressed across R" which determines
the output current. The quiescent current is added
to the current through R" and this puts a lower
limit of about 10 mA on the available output
current.

bypassing the non-inverting input to ground. A
100 pF capacitor should also be included between
the output and the inverting input to prevent
frequency instability. Temperature drift can be
~educed by adjusting R 4 , which determines the
zener current, for minimum drift. For best
performance, remote sensing directly to the load
terminals, as shown in the diagram, should be
used.

INPUT-....-~

CONCLUSIONS
R1
L..._--4I"--OUTPUT

Figure 12. Current Regulator.

The increased failure resistance brought about by
thermal overload protection make the LM 109
attractive as the pass transistor in other regulator
circuits. A precision regulator that employs the IC
thusly is shown in Figure 13. An operational
amplifier compares the output voltage with the
output voltage of a reference zener. The op amp
controls the LM109 by driving the ground
terminal through an FET.

The LM109 performs a complete regulation
function on a single silicon chip, requiring no
external components. It makes use of some unique
advantages of monolithic construction to achieve
performance advantages that cannot be obtained
in discrete-component circuits. Further, the low
cost of the device suggests its use in appl ications
where single-point regulation could not be justified
previously.
Thermal overload protection significantly improves the reliability of an IC regulator. It even
protects the regulator for unforseen fault conditions that may occur in field operation. Although
this can be accomplished easily in a monolithic
regulator, it is usually not completely effective in a
discrete or hybrid device.
The internal reference developed for the LM 109
also advances the state of the art for regulators.
Not only does it provide a low voltage, temperature-compensated reference for the first time, but
also it can be expected to have better long term
stability than conventional zeners. Noise is inherently much lower, and it can be manufactured
to tighter tolerances.

REFERENCES
1. R.J. Widlar, "Designing Positive Voltage Regulators," EEE, Vol. 17, No.6, pp.90-97,
June 1969.
2. J.S. Brugler, "Silicon Transistor Biasing for
Linear Collector Current Temperature Dependence," IEEE Journal of Solid State Circuits,
pp. 57-58, June, 1967.

Figure 13. High Stability Regulator.

The load and line regulation of this circuit is better
than 0.001 %. Noise, drift and long term stability
are determined by the reference zener, D,. Noise
can be reduced by inserting 100 kn, 1% resistors
in series with both inputs of the op amp and

AN42-6

3. R.J.Widlar, "Some Circuit Design Techniques
for Linear Integrated Circuits," IEEE Trans. on
Circuit
Theory,
Vol. Xll,
pp.586-590,
December, 1965.
4. R.J. Widlar, "Design of Monolithic Linear
Circuits," Handbook of Semiconductor Electronics, Chapter X, pp 10.1-10.32, L.P. Hunter,
ed., McGraw-Hili Inc., New York, 1970.

l>

z
June 1971

I

~
0')

-t

::I:
m
"'tJ

::I:

l>

THE PHASE LOCKED LOOP I C AS A

CJ)

COMMUNICATION SYSTEM BUILDING BLOCK

m

INTRODUCTION

o

r-

(")

The phase locked loop has been fou nd to be a
useful element in many types of communication
systems. It is used in two fundamentally different
ways: (1) as a demodulator, where it is used to
follow phase or frequency modulation and (2) to
track a carrier or synchronizing signal which may
vary in frequency with time.

The output of the VCO is related to its input
control voltage by
(4)

for ef

= 0,

let 8 2

= w8,

then

"
m
C

r-

o
o

"'tJ

(5)

When operating as a demodulator, the phase locked
loop may be thought of as a matched filter operating as a coherent detector. When used to track a
carrier, it may be thought of as a narrow-band
filter for removing noise from a signal.
Recently, a phase locked loop has been built on a
monolithic integrated circuit, incorporating the
basic elements necessary for operation: a double
balanced phase detector and a highly linear voltage
controlled oscillator, the frequency of which can
be varied with either a resistor or capacitor.

BASIC PHASE LOCK LOOP OPERATION
Figure 1 shows the basic blocks of a phase locked
loop. The input signal ej is a sinusoid of arbitrary
frequency, while the VCO output signal, eo, is a
sinsuoid of the same frequency as the input but of
arbitrary phase. If

=.J2
eo =.J2
ej

Ej [sin wot + 8 1(t)]

(1)

Eo [sin wot+ 8 2 (t)]

(2)

the output of the multiplier (phase detector) is
ed = ej . eo = 2E jEo sin. [wot + 8 1(t)]
cos [Wot + 8 2 (t)]

= EjE o sin [8 1(t) - 8 2 (t)]
+sin [2w ot+8 1(t) +8 2 (t)]

(3)

the low pass filter of the loop removes the ac
components of the multiplier output; the dc term
is seen to be a function of the phase angle between
the VCO and the input signal.

INPUT

PHASE
DETECTOR

eof

l1

ed

FILTER
F(S)

r VOLTAGE CONTROLLEO
OSCILLATOR

(")
It can be seen that the action of the VCO is that
of an integrator in the feedback loop when the
phase locked loop is considered in servo theory.
A better understanding of the operation of the
loop may be obtained by considering that initially,
the loop is not in lock, but that the frequency of
the input signal ej and VCO eo are very close in
frequency. Under these conditions ed will be a
beat note, the frequency of which is equal to the
frequency difference of eo and ej. This signal is
also applied to the VCO input, since it is low
enough to pass through the filter. The instantaneous frequency of the VCO is therefore changing
and at some point in time, if the VCO frequency
equals the input t'requency, lock will result. At
this instant, ef will assume a level sufficient to
hold the VCO frequency in lock with the input
frequency. If the tuning of the VCO is changed
(such as by varying the value of the tuning capacitor) the frequency output of the VCO will
attempt to change; however, this will result in an
instantaneous change in phase angle between ej and
eo, resulting in a change in the dc level of ed which
will act to maintain frequency lock: no average
frequency change will result.
Similarly, if ej changes frequency, an instantaneous
change will result in a phase change between ej and
eo and hence a dc level change in ed. This level
shift will change the frequency of the VCO to
maintain lock.
The amount of phase error resulting from a given
frequency shift can be found by knowing the
"dc" loop gain of the system. Considering the
phase detector to have a transfer fu ncti on:

~
.-

II

FIGURE 1. Basic Phase Locked Loop

and the voltage controlled oscillator to have a
transfer function:
(6)

AN46-1

l>

CJ)

l>
(")

o

3:
3:

c

z
(")

l>
-t

o
Z

CJ)

-<

CJ)

-t

m

3:
OJ

C

r-

C
Z

C)

OJ

r-

o(")

"

or taking the Laplace transform

(7)

the phase of the VCO output will be proportional to the integral of the control voltage.

scribed above, but the "ac" or transient performance which is governed by the components of the
loop filter placed between the phase detector and
the voltage controlled oscillator. In fact, it is this
loop filter that makes the phase locked loop so
powerful: only a resistor and capacitor are all that
is needed to produce an arbitrarily narrow bandwidth at any selected center frequency.

Combining these equations:

(8)

s

The simplest filter is a single capacitor, Figu re2,
and is used for wide bandwidth appl ications, such
as where wideband data modulation must be
followed. The transfer function of the filter is
simply:

(9)

s + KoKo F(s)

(13)
Application of the final value theorem of Laplace
transforms yields

substitution into (8) results in

(10)

(14)

With a step change in phase of the input 6.8 1 , the
Laplace transform of the input is
8 1 (s)

6.8 1
-s- which gives 8 e(s) = 8 1 (s) - 8 2 (s)
lim
s-+o

s6.8 1

o

I n terms of servo theory, the damping factor and
natural frequencies are

(11 )
(15)

the loop will eventually track out any change of
input phase, and there will be no phase error in
the steady state solution.

]1/2
1
[ 2 (R 1 C1 KoKo)

(16)

I f the input is a step infrequency, of magn itude
6.0.), the change in input phase will be a ramp:
8 1 (s) = 6.w/s2

ed

Rt

substitution of th is value 8, into (10) results in
6.w
----KoKo F(o) (12)

VOLTAGE CONTROLLEO
OSCILLATOR

T, = RtCt

this result shows the resulting phase error is
dependent on the magnitude of the frequency
step and the "dc" loop gain KoKo, which is also
called the velocity error coefficient Kv. It should
be noted that the dimensions of Ko Ko are 1/sec.
This can also be seen by considering Ko = volts/
radian, while Ko = radians/sec/volt. The product is
volts
radians/sec
volt
radian x

sec

this can be thought of as the "dc" loop gain. (Note
that additional de gain between the phase detector
and the voltage controlled oscillator will increase
the loop gain and hence reduce the steady state
phase error resulting from a change in frequency
of the input.)
THE LOOP FI L TER
In working with phase locked loops, it is necessary
to consider not only the dc" performance deII

AN46-2

FIGURE 2. Phase Locked Loop with Simple Filter

From this it can be seen that large time constants
for R 1 C 1 or high loop gain will reduce the damping
factor and hence decrease stability. Therefore, if a
narrow bandwidth is desired, the damping factor
will t;>ecome very small and instability will result.
It is· not possible to adjust bandwidth, loop gain,
and damping independently with this simple filter.

With the addition of a damping resistor R2 as
shown in Figure 3, it is possible to choose bandwidth, damping factor and loop gain independently;
the transfer function of this filter is

11)4

....
10'

105

....

....

( 17)

~4

KoK~~
(RAO)
RAO

~m

E

N

Nil' ....

103

IIII

10'

the loop transfer function becomes:

~

10. 4

10-3

~illN lin....
10-2
T, +T2

10-'

10

(sec)

FIGURE 4. Filter Time Constant vs Natural Frequency

_____
K-=.o_K-=o_(s 72 + 1) (7, + 72)
s2 + s(1 + KoKd 72)/(7, :- 7.2) + KoKo/(7, + 72 )
(18)

the loop natural frequency is

(19)

while the damping factor becomes

(20)
FIGURE 5. Damping Time Constant vs
Natural Frequency

(21 )

DESIGN CONSIDERATIONS
R2
ef

VOLTAGE CONTROLLEO
OSCILLATOR

T, = R1Cl

T2=

R2Cl

BOOE PLOT

I

I
I
I

:

-6',

1-12
dB/ocr,
I dB/OCT I

I

Considering the above discussion, there are really
two primary considerations in designing a phase
locked loop. The use to which the loop is to be put
will affect the design criterion of the loop components. The two primary factors to consider are:

I

1. Loop gain. As pointed out previously, this
affects the phase error between the input signal
and the voltage controlled oscillator for a given
frequency shift of the input signal. I t also determines the "hold in range" of the loop providing
no components of the loop go into limiting or
saturation. This is because the loop will remain
in lock as long as the phase difference between
the input and the VCO is less than ±90°. The
higher the loop gain, the further the input can
change in frequency before the 90° phase error
is reached. The hold in range is
(22)

FIGURE 3. Phase Locked Loop with Damping
Resistor Added

In practice, for a fixed loop gain KoKo, the natural
frequency of the loop may be chosen and will be
dependent mainly on 7" since 72« 7, in most
cases. Then, according to (21), damping may be
determined by 72 and for all practical purposes,
will be an independent adjustment. These equations are plotted in Figures 4 and 5 and may be
used for design purposes.

(prov i d in g saturation or limiting does not
occur).
2. Natural Frequency. The bandwidth of the loop
is determined by the filter components R" R,
and C, and the loop gain. Since the loop gain
is normally selected by the criterion in 1. above,
the filter components are used to select the
bandwidth. The selection of loop bandwidth
may be governed by several things: noise bandwidth, modulation rates if the loop is to be

AN46-3

used as an FM demodulator, pull-in time and
hold-in range. There are two conflicting requirements that wi II have an affect on loop bandwidth:

0.7 -

2~
~~ ~
I

(a) Loop bandwidth must be as narrow as
possible to minimize output phase jitter
due to external noise.
(b) The loop bandwidth should be made as
large as possible to minimize transient error
due to signal modulation, output jitter due
to internal oscillator (VeO) noise, and to
obtain best tracking and acquisition properties.
These two principles are in direct opposition and,
depending on what it is that the loop is to accomplish, an optimum solution will lie somewhere
between the two extremes.
If the phase locked loop is to be used to demodulate frequency modulation, the design should proceed with the criterion of b above. It is necessary
to provide sufficient loop bandwidth to accommodate the expected modulation. It must be
remembered that at all times, the loop must remain
in lock, (peak phase error less than 90°), even
under extremes of modulation, such as peaks or
step changes in frequency.

a:
a:
a:

0.3

0

1.6

-

1.2

.~c

'" 3
.liL' = 2.0

-0.1

/
,=1.0!-- !--

'/

'I..

Z ,=0.707-!-f--,=~.o~
"-=b- ,=
' = 0.3
o.~
!-1-

-0.3
-0.5
0

1

F

2

3

4

5

6

7

8

FIGURE 9. Phase Error 8e (t) Due to a Step in Phase 68

In designing loops to track a carrier or synchronizing signal, it is desirable to make the loop bandwidth narrow so that phase error due to external
noise will be small. However, it is necessary to
make the loop bandwidth wide enough so that
any frequency jitter on the input signal will be
followed.

NOISE PER FORMANCE
200
100
50

The phase locked loop, as mentioned earlier, may
be thought of as a filter with a fixed, adjustable
bandwidth. We have seen how to calculate the loop
natural frequency Wn (15), (19), and the damping
factor S (16), (20). Without going through a derivation, the loop noise bandwidth BL may be shown
to be

c

3.0

..2

~ 2.5

~

2.0

- - - -------- - -

~ 1.5

;ii

~

1/

I I I
V

I I VI

5

I I I I
0

1.0

0.5

1.5

2.0

LOOP SIGNAL·TO·NOISE RATIO

FIGURE 11. Unlock Behavior of High-Gain, SecondOrder Loop, = 0.707

S

When design ing the loop filter components, enough
bandwidth in the loop must be allowed for instantaneous phase change due to input noise. In the
previous section, the filter was selected on the
basis that the peak error due to modulation would
be less than 90° (so the loop would not loose lock).
However, if noise is present, the peak phase error
will increase due to the noise. So if the loop is not
to lose lock on these noise peaks, the peak allowable error due to modulation must be reduced to
something less, on the order of 40° to 50°.

1-+--+-.-+--+-- . _ -

~

~ 1.0

I

20
10

for a high gain, second order loop. This equation is
plotted in Figure 10. It should be noted that the
dimensions of noise bandwidth are cycles per
second while the dimensions of Wn are radians
per second.

,

500

Since one of the main uses of phase locked loops
is to demodulate or track signals in noise, it is
helpful to look at how noise affects the operation
of the phase locked loop.

1./

I+-+--+-- -~

D.5

--+--

.Y -~ --,--

\..

o

V"---

0.5

1.0

1.5

2.0

2.5

3.0

LOCKING
Initially, a loop is unlocked and the veo is running
at some frequency. If a signal is applied to the
input, locking mayor may not occur depending on
several things.

3.5

OAMPING fACTOR -,

FIGURE 10. Loop-Noise Bandwidth (For High-Gain,
Second-Order Loop)

Noise threshold is a difficult thing to analyze in a
phase locked loop, since we are talking about a
statistical quantity. Noise will show up in the input
signal as both amplitude and phase modulation. It
can be shown that near optimum performance of a
phase locked loop can be obtained if a limiter is
used ahead of the phase detector, or if the phase
detector is allowed to operate in limiting. With the
use of a limiter, amplitude modulation of the input
signal by noise is removed, and the noise appears
as phase modulation. As the input signal to noise
ratio decreases, the phase jitter of the input signal
due to noise increases, and the probabil ity of losing
lock due to instantaneous phase excersions will
increase. In practice it is nearly impossible to
acquire lock if the signal to noise ratio in the loop
(SNR)L = 0 dB. In general, (SNR)L of +6 dB is
needed for acquisition. If modulation or transient
phase error is present, a higher signal to noise ratio
is needed to acquire and hold lock.

A computer simulation performed by Sanneman
and Rowbotham has shown the probability of
skipping cycles for various loop signal to noise
ratios for high gain, second order loops. Their
data is shown in Figure 11.

If the signal is within the bandwidth of the loop
filter, locking will occur without a beat note being
generated or any cycles being skipped. This frequency is given by

If the frequency of the input signal is further
away from the veo frequency, locking may still
occur, with a beat note being generated. The greatest frequency that can be pulled in is called the
pull in frequency" and is found from the approximation
J/

which works well for moderate and high gain loops
(wn/KoKo
.4).

<

An approximate expression for pull in time (the
time required to achieve lock from some frequency
offset 6.w) is given by:

A MONOLITHIC PHASE LOCKED LOOP
A complete phase locked loop has been built on a
monolithic integrated circuit. It features a very

AN46-5

linear voltage controlled oscillator and a double
balanced phase detector.
A simplified schematic of this voltage controlled
oscillator is shown in Figure 12. O 2 is a voltage
controlled current source whose collector current
is alinear function of the control voltage ef. I nitialIy Q 5 is 0 F F and the collector current of Q 2 passes
through O2 and changes C in a linear fashion. The
voltage across C is therefore a ramp, and continues to increase until Q 7 is turned ON; this turns
OFF Q8, causing Q 9 and Q 11 to turn ON. This in
turn turns ON 0 5 , With 0 5 ON, the anode of 0 1
is clamped close to -V cc and O2 stops conducting,
since its cathode is more positive than its anode.

All of the current supplied by Q 2 is diverted
through 0, and 0 3 , which sets up an equal current in Q4' This current is supplied by the charged
capacitor C (which now discharges linearly), causing the voltage across it to decrease. Th is continues
until a lower trip point is reached and Q 7 turns
OFF and the cycle repeats. Due to the matching of
Q 3 and Q4, the charge current of C is equal to the
discharge current and therefore the duty cycle is
very nearly 50%. Figure 13 shows the wave forms
at (1) and (2).
Figure 14 shows the double balanced phase detector and amplifier used in the microcircu it. Transistors Q 1 through Q 4 are switched with the output

FIGURE 12. Simplified Voltage Controlled Oscillator

VOLTAGE

-O.6~

FIGURE 13. VCO Waveforms

+Vcc

FIGURE 14. Phase Detector and Amplifier

AN46.:.6

of the vea, while the input signal is applied to
the bases of 0 5 and 0 6 , The output current in
resistors R3 and R4 is then proportional to the
difference in phase between the vea output and
the input; the ac component of this current will
be at twice the frequency of the vea due to the
full wave switching action transistors 0 1 through
0 4 , The waveforms of Figure 15 illustrate how
the phase detector works. Diodes D1 and D2 serve
to limit the peak to peak amplitude of the collector
voltage. The output of the phase detector is further
ampl ified by 010 and 0 11 , and is taken as a voltage at pin 7.

Ra serves as the resistive portion of the loop filter,
and additional resistance and capacitance may be
added here to fix the loop bandwidth. For use as
an FM demodulator, the voltage at pin 7 will be
the demodulated output; since the dc level here
is fairly high, a reference voltage has been provided so that an operational amplifier with differential input can be used for additional gain and
level shifting.

The complete microcircuit, called the LM565, is
shown in Figure 16.

hHH4--1-+-++++- ~~~gRVOlTAGE

r--'L------'---"---L..--'--

I"
ERROR VOLTAGE

POSlrlVE
~=1'O°

r-----,c---,----.---y---,-

I"

ERROR VOLTAGE
NEGATIVE

FIGURE 15. Phase Detector Waveforms, Showing Limit Cases for Phase Shift Between Input and VCO Signals

R.

5.7K

R12

3.6K

R10
1.15K

R1
7.2K

R14

IK

R3

200

R'

200

R15

205

FIGURE 16. LM565 Phase Locked Loop

AN46-7

USING THE LM565
Some of the important operating characteristics of
the LM565 are shown in the table below. (Vee
±6V, T A = 25°C).
Phase Detector

5kSl

I nput Impedance
Input Level for Limiting
Output Resistance
Output Common Mode Voltage
Offset Voltage (Between pins 6 and 7)
Sensitivity KD

10mV

3.6 kSl
4.5V
100mV
.5Vlrad

tion regardless of center frequency. I RIG channel
13 has been selected as an example of demonstrate the usefulness of the LM565 as an FM
demodulator.
I RIG Channel
Center Frequency
Max Deviation
Frequency Response
Deviation Ratio

13
14.5 kHz
±7.5%
220 Hz

5

Voltage Controlled Oscillator
Stability
Temperature
Supply Voltage
Square Wave Output Pin 4
Triangle Wave Output Pin 9
Maximum Operating Frequency
Sensitivity Ko

200 ppmtC
200 ppm/%

5.4 V

pp

2.4 V pp
500 kHz
4.5 fo rad/secN
(fo: osc. freq. in Hz)

Closed Loop Performance
Loop Gain KoKD
2.8 fo/sec
300 mV
Demod. Output, ±10% Deviation
(A .001 pF capacitor is needed between pins 7 and 8 to stop
parasitic oscillations).

To best illustrate how the LM565 is used, several
applications are covered in detail, and should provide insight into the selection of external components for use with the LM565.

Since with a deviation of ±10%, the LM565 will
produce approximately 300 mV peak to peak
output, with a deviation of 7.5%, we can expect
an output of 225 mV. It is desirable to amplify
and level shift this signal to ground so that plus
and minus output voltages can be obtained for
frequency shifts above and below center frequency.
An LM 107 can be used to provide the necessary
additional gain and the level shift. In Figure 17,
R4 is used to set the output at zero volts with no
input signal. The frequency of the VCO can be
adjusted with R3 to provide zero output voltage
when an input signal is present.

IRIG CHANNEL DEMODULATOR

The design of the filter network proceeds as
follows:

In the field of missile telemetry, it is necessary to
send many channels of relatively narrow band data
via a radio link. It has been found convenient to
frequency modulate this information on a set of
subcarriers with center frequencies in the range of
400 Hz to 200 kHz. Standardization of these frequencies was undertaken by the I nter- Range I nstrumentation Group (IRIG) and has resulted in several
sets of subcarrier channels, some based on deviations that are a fixed percentage of center frequency and other sets that have a constant devia-

I t is necessary to choose wn such that the peak
phase error in the loop is less than 90° for all
conditions of modulation. Allowing for noise modulation at low levels of signal to noise, a desirable
peak phase error might be 1 radian or 57 degrees,
leaving a 33 degree margin for noise. Assuming
sinusoidal modulation, Figure 6 can be used to
estimate the peak normalized phase error. It
will be necessary to make several sample calculations, since the normalized phase error is a
function of W n .

r-------~-.~------------~----~

.01

IN~ ~_-I-_~

__--O+6V

470K

OUTPUT

~----------------------------------~~-----t---o-6V

FIGURE 17. IRIG Channel 13 Demodulator

AN46-8

Selecting a worst case of wn/w m = 1, Wn = 27TX
220 Hz; selecting a damping factor of .707,

e

== .702

of approximately +6 dB because of the bandwidths
involved. The above number of -8.4 dB signal to
noise for threshold was obtained with a noise
spectrum 100 kHz wide. The noise power in the
loop will be reduced by the ratio of loop noise
bandwidth to input noise bandwidth

or
.702 -

=

BLOOP
1890 Hz
BINPuT = 100 kHz = .02 or -17 dB

27T X 1088 Hz
.702
27T X 220 Hz

= 3.45 radians
this is unacceptable, since it would throw the loop
out of lock, so it is necessary to try a higher value
of Wn. Let Wn = 27TX 500 Hz, then wmlw n = .44,
o.,d
27T X 1088
.44 X 2 IT X 500

=

the'equivalent signal to noise in the loop is -8.4 dB
+17 dB = +8.6 dB which is close to the abovementioned limit of +6 dB. It should also be noted
that loss of lock was noted with full modulation
of the signal which will degrade threshold somewhat (although the measurement is more realistic).

lOOK

.95 radians

r----------,

10K -

this should be a good choice, since it is close to
radian. Operating at 14.5 kHz, the LM565 has a
loop gain KoKo of

lK -

100

-

10

-

Wl=250~

2.28 x 14.5 x 103 = 33 x 103 sec

W2

1

the value of the loop filter capacitor, C 1 , can be
found from Figure 4:

w_

I

= 2500

I

I

10

100

I

I

lK

10K

lOOK

FIGURE 18. Bode Plot for Circuit of Figure 1;7
71

+

72

= 3.5 x 10- 3 sec

from Figure 5, the value of
a damping factor of .707)
72
71

C1

72

can be found (for
FSK DEMODULATOR

= 4.4 X 10-4 sec

=

4

(35-4.4) X 10- sec

__ 71

R

=

=

31.4 X 10-

4

31.4 X 10- sec

4.4 X 10- 4 sec
1 X 10-6 J1F

=

=

4

sec

1 J1F

440 S1

Looking at Figure 10, the noise bandwidth BL can
be esti mated to be
BL

=

.6wn = .6 X 3150rad/sec
= 1890 Hz

the complete circuit is shown in Figure 17. Measured performance of the circuit is summarized
below with a fully modulated signal as described
above and an input level of 40 mVrms:
f 3 dB
~

Frequency shift keying (FSK) is widely used for
the transmission of Teletype information, both in
the computer peripheral a.nd communications field.
Standards have evolved over the years, and the
commonly used frequencies are as follows:
a)

mark
space

2225
2975

Hz
Hz

b)

mark
space

1070
1270

Hz
Hz

c)

mark
space

2025
2225

Hz
Hz

a) is commonly used as subcarrier tones for radio
Teletype, while b) and c) are used as carriers for
data transmission over telephone and land lines.
As a design example, a demodulator for the 2025
Hz and 2225 Hz mark the space frequencies will
be discussed.

200

Q8

Output Level
770 mVrms
Distortion
0.4%
Signal to Noise at verge of loss of lock
(bandwidth of noise = 100 kHz)
-8.4 dB
It will be noted that the loop is capable of demodulating signals lower in level than the noise;
this is not in disagreement with earlier statements
that loss of lock occurs at signal to noise ratios

Since this is an FM system employing square wave
modulation, the natural frequency of the loop
must be chosen again so that peak phase errors
do not exceed 90° under all conditions. Figure 7
shows peak phase error for a step in frequency;
if a damping factor of .707 is selected, the peak
phase error is

.45

AN46-9

FIGURE 19. FSK Demodulator (2025-2225 cps)

FIGURE 20. FSK Demodulator with DC Restoration

or

ae

.45

Wn

.45

2

in our case, 6.w
radian,

.45

1TX

values calculated above caused too much roll off
of a square wave modulation signal of 150 Hz. The
two 10k resistors and .02 J.1F capacitors at the
input to the LM 111 comparator provide further
filtering of the carrier, and hence smoother operation of the circuit.

!:'w
Wn

!:'w

e:

200 Hz

1250 rad/sec
1 radian

= 1250,

if

ae = 1

500 rad/sec

fn = 80 Hz
The final circuit is shown in Figure 19. The values
of the loop filter components (C 1 = 2.2 J.1F and
R1 = 700[2) were changed to accommodate a
keying rate of 300 bauds (150. Hz), since the

AN46-10

A problem encountered with this simple demodulator is that of dc drift. The frequency must be
adjusted to provide zero volts to the input of the
comparator so that with modulation, switching
occurs. Since the deviation of the signal is small
(approximately 10%), the peak to peak demodulated output is only 150 mY. It should be apparent
that any drift in frequency of the VCO will cause
a dc change and hence may lock the comparator
in one state or the other. A circuit to overcome
this problem is shown in Figure 20. While using
the same basic demodulator configuration, an

FIGURE 21. Block Diagram of Weather Satellite Demodulator

~b

?l"
TO
HORIZ

SYNC

FIGURE 22. Weather Satellite Picture Demodulator

LM 111 is used as an accurate peak detector to
provide a dc bias for one input to the comparator.
When a "space" frequency is transmitted, and the
output at pin 8 of the LM565 goes negative
and switching occurs, the detected and filtered
voltage of pin 3 to the comparator will not follow
the change. This is a form of "dc. restorer" circuit:
it will track changes in drift, making the comparator self compensating for changes in frequency, etc.

WEATHER SATELLITE PICTURE
DEMODULATOR
As a last example of how a phase locked loop can
be used in communications systems, a weather
satellite picture demodulator is shown. Weather
satellites of the Nimbus, ESSA, and ITOS series
continually photograph the earth from orbits of
100 to 800 miles. The pictures are stored immediately after exposure in an electrostatic storage
vidicon, and read out during a succeeding 200
second period. The video information is AM modu-

lated on a 2.4 kHz subcarrier which is frequency
modulated on a 137.5 MHz RF carrier. Upon
reception, the output from the receiver FM detector will be the 2.4 kHz tone containing AM video
information. It is common practice to record the
tone on an audio qual ity tape recorder for su bsequent demodulation and display. The 2.4 kHz
subcarrier frequency may be divided by 600 to
obtain the horizontal sync frequency of 4 Hz.

Due to flutter in the tape recorder, noise during
reception, etc., it is desirable to reproduce the
2.4 kHz subcarrier with a phase locked loop, which
will track any flutter and instability in the recorder,
and effectively filter out noise, in addition to providing a signal large enough for the digital frequency divider. In addition, an in phase component
of the VCO signal may be used to drive a synchronous demodulator to detect the video information.
A block diagram of the system is shown in Figure 21, and a complete schematic in Figure 22.

AN46-11

The design of the loop parameters was based on
the following objectives
fn
BL

10Hz, Wn

=

75 rad/sec

40 Hz (from Figure 10)

the complete loop filter, calculated from FigWes
4 and 5, is shown in Figure 22. When the loop is
in lock and the free running frequency of the VCO
is 2.4 kHz, the VCO square wave at pin 4 of the
565 will be in quadrature (90°) from the input
signal; however, the zero crossings of the triangle
wave across the timing capacitor will be in phase,
and if their signal is appl i,ed to a double balanced
demodulato'r, such as an LM 1596, switching will
occur in the demodulator in phase with the 2.4
kHz subcarrier. The double balanced demodulator
will produce an output proportional to the amplitude of the subcarrier applied to its signal input.
An emitter follower, Q 1, is used to buffer the
triangle wave across the timing capacitor so excessive loading does not occur.
The demodulated video signal from the LM 1596
is taken across a 25k potentiometer and filtered to
a bandwidth of 1.4 kHz, the bandwidth of the
transmitted video. Depending qn the type of display to be used (oscilloscope, slow scan TV monitor, of facsimile reproducer), it may be necessary
to further buffer or amplify the signal obtained.
If desired, another load resistor may be used
between pin 6 and VCO to obtain a differential
output; an operational amp could then be used to
provide more gain, le)lel shift, etc.

AN46-12

A vertical sweep circuit is shown using an LM308
low input current op amp as a Miller rundown
circuit. The values are chosen to produce an output
voltage ramp of -4.5V 1220 sec, although this may
be adjusted by means of the 22 meg. charging
resistor. If an oscilloscope is used as a readout,
the horizontal sync can be suppl ied to the trigger
input with the sweep set to provide a total sweep
time of something less than 250 ms. A camera is
used to photograph the 200 second picture.

SUMMARY AND CONCLUSIONS
A brief review of phase lock techniques has bef:!n
presented and several useful design tools have been
presented that may be useful in predicting ~h.e
performance of phase locked loops.
A phase locked loop integrated circu it has been
described and several applications have been given
to illustrate the use of the circu it and the design
techniques presented.

REFERENCES
1. Floyd M. Gardner, "Phaselock Techniques",
John Wiley and Sons, 1966.
2. Elliot L. Greenberg, "Handbook of Telemetry
and Remote Control", McGraw-Hili, 1967.
3. Andrew Viterbi, "Principles of Coherent Communication", McGraw-Hili, 1966.

»

:2
I

~

CO

l>

"'0
"'0

-

r-

APPLICATIONS FOR A NEW ULTRA-HIGH SPEED BUFFER

('")

INTRODUCTION

from the output 0 1 and O2 wiH drif.t a't.diffe~ent
rates. A circuit which overcomespJfse~; voltage
drift is used in a ,new high speed b4ffer~amp'liFer,
the LH0033. Initial o.ffset is typically 5 mV a'nd
offset drift is 20l1V
Resistor R;is' us~d to
establish the drain current of currEm't, ~ource transistor" O2 at 10 mAo
: ; ;,

Voltage followers have gained in popularity in
applications such as sample and hold circuits,
general purpose buffers, and active filters since
the introduction of IC operational amplifiers. Since
they were not specifically designed as foHowers,
these earlylC's had limited usage due to low bandwidth, low slew rate and high input current. Usage
of voltage followers was expanded in 1967 with
the introduction of the LM 102, the first IC designed specifically as a voltage follower: With the
LM102, engineers were able to obtain an order of
magnitude improvement in performance and extend usage into medium speed applications. The
LM110, an improved LM102, was introduced in
late 1969. However, even higher speeds and lower
input currents were needed for very fast sample
and holds, A to D and D to A converters, coax
cable drivers, and other video appl ications.

;oe.
v'

»
o
-4

Z

(J)

."

o

::D

l>
:2

~
C
r-f
~

FIGURE

i.

l>

Simple VoltageFollower'Scileiriatic

I

::r:

The same drain current'flows through: 0 1 causinfg
a voltage at the source of app'ro*lmaiel'{' '1. lV.
The 10 mA flowirlgthrough R1 plus 03's VeE of
0.6V causes the ()utput'to ,sit at zero vOlts, for
zero volts in. 0 3 and 0 4 eliminate loadin'g'the
input stage (except for base Gurrent) 'and CR 1' and
CR 2 establish the output stage collector current.

The solution to this application problem was
attained by combining technologies. into a single
package. The result, the LH0033 high speed buffer,
utilizes JFEr and bipolar technology to produce
a ultra-fast voltage follower and buffer whose
propagation delay closely approaches speed-oflight delay across its package, while not compromising input impedance or drive characteristics.
Table I compares various voltage followers and
illustrates the superiority of the LH0033 in both
low input current or high speed video applications.

r---,v-

(fj

."
m
m
C
to

C

v12

-

C)

:t

."
."

I

m

::rJ

CIRCUIT CONSIDERATIONS
R3
2<>

The junction FET makes a nearly ideal input device
for a voltage follower, reducing input bias current
to the picoamp range. However, FET's exhibit
moderate voltage offsets and offset drifts which
tend to be difficult to compensate. The simple
voltage follower of Figure 1 eliminates initial
offset and offset drift if 0 1 and O2 are identically
matched transistors. Since the gate to source
voltage of O2 equals zero volts, then 0 1' S gate to
source voltage equals zero volts. Furthermore as
V P1 changes with temperature (approximately
2.2 mV/oC), VP2 will change by a corresponding amount. However, as load current is drawn

11
OUTPUT

OFFSET
AOJ.

I'

6 C>'VI~---'

FIGURE 2. LH0033 Schematic

If 0 1 and O2 are matched, the resulting drift is
reduced to a few 11 V/ ° C.

TABLE I COMPARISON OF VOLTAGE FOLLOWERS

PARAMETER

CONVENTIONAL
MONOLITHIC OP AMP
LM741

FIRST GENERATION
VOLTAGE FOLLOWER
LM102

SECOND GENERATION
VOLTAGE FOLLOWER
LM110

SPECIALL Y DESIGNED
VOLTAGE FOLLOWER
LHOO33

INPUT BIAS CURRENT

200 nA

3.0 nA

1.0nA

0.05 nA

SLEW RATE

0.5V/).ls

10V/liS

30V/lis

1500V/liS

BANDWIDTH

1.0 MHz

10 MHz

20 MHz

100 MHz

PROP. DELAY TIME

350 ns

35 ns

18 ns

1.2 ns

OUTPUT CURRENT CAPABILITY

±5mA

±2mA

±2 rnA

±100 mA

AN48-1

PERFORMANCE OF THE LH0033
FAST VOLTAGE FOLLOWER/BUFFER
IStICS. Other typical performance curves are illustrated in Figures 4 through 10. Of particular
interest is Figure 8, which demonstrates the performance of the LH0033 in video applications
to over 100 MHz.

The majdr electrical characteristics of the LH0033
are summarized in Table II. All the virtues of a
ultra-high speed buffer have been incorporated.
Figure 3 is a plot of input bias current vs temperature and shows the typical FET input characterTABLE II
CONDITIONS

PARAMETER
Output Offset,Voltage

Rs = 100 kn

, Input 'Sias Current

V'N = 1.0 Vims
R L = 1k,f= 1 kHz,Rs= lOOk

0.98

Output Voltage Swing

Vs = ±15V, Rs = lOOk
RL = 1k

±13V

0;

~

.010

"'"

V

c

•

E
w
'"

'*'

"

~
>

"Vs = ±15V='

i

!

~,

I
25

75

50

100

-......,
6.0

Vs = ±15V

~

'"

~

>

~

!~

i

-4
-6

-8
-10

,

20

~

f"'

2

'"

10

-

50

/
10

150

100

r•

:::>

,

Q.

:::>
0

I-

:::>

FIGURE 5. Output Voltage vs
Supply Voltage

2

~

Avt/

.............

'"

0.6

-

/

0.4

>

\~

40

~

0,8

~

\\
30

0,2

50

V
1,0

60

2,0

FIGURE 7. Positive Pulse Response

FIGURE 6. Negative Pulse Response

5.0

Vs = ±15V
Rs = 50n

-w

20

~

~

19
u

l

4.0

0
2

cr
w

18

'"a:

RL = lk

6.0

::;;
;::

.E

...-..--

...- ~ t;'"

-

t,

2.0

17
5 I:

10

15

20

Supply Voltage (±V)

FIGURE 9. Supply Current vs
Supply Voltage

AN48--2

50

15
10

A
20.0

20

100

FIGURE 8. Frequency Response

B.O

21

C[

10,0

f'

25

FREQUENCY (MHz)

TIME (ns)

TIME (ns)

30

1.0

2

\1

20

35

I- Rs = son
f- RL = son
Y'N = 1.0V rms

~

'INPUT - - \\
>-- OUTPUT

10

60

40
Vs = ±15V

,

j

Q.

20

15

SUPPL Y VOL TAGE (±V)

Vs = ±15V
Rl = 1 kn. Rs = son ~
TA =+25'C

~

I-

50

,l .
r-

I:!

~>

I-

40

/

o

12

w

I:,

~I'

~

vs Temperature

,

30

/

:::>

1--- -

-12
10

10

>

2,0

/
/

V

I-

FIGURE 4. Output Offset Voltage

--

-

12

~

......... ........

I

TEMPERATURE rC)

I;

. . - . - OUTPUT

I

RL = 1 kn
Rs = 100 kn
TA = +25'C

14 -

'"

i'-..~

-50

~

~,IINPUT ---.

~w

'i'..

vs Temperature

fRS =50n
RL = 1 kSl
-2
r-T A = +25'C
.1
I

18
16 -

--I- Rs = lOOk

4.0

100MHz

V'N = 1.0 Vrms
Rs =50n,R L =lk

Vs = ±lS,OV

125

Curr~nt

1500V!lls
1.2 ns

Bandwidth

TEMPERiITURE (OC)

FIGURE 3. Input Bias

Rs = 50n, RL = 1k

Propagation Delay

:>

~Vs = ±lDV

,001

±100mA peak

B.O

- -"

...
./l/

VALUE

CONDITIONS

Slew Rate

Vo:ltage Gain

~ o.ioo

~

Output Current Capabil ity

10"n

Vs = ±20V

:~

5mV

V'N = 1.0 Vrms
R,: = lk, f = 1 kHz

1.00

.

PARAMETER

50 pA

I nput Impedance

1

VALUE

-50

50

100

150

TEMPERATURE (OC)

FIGURE 10. Rise and Fall Time
vs Temperature

~

~

0-

~
c
m

."

~

APPLICATIONS FOR ULTRAFAST FOLLOWERS
The LH0033's high input impedance (10" n,
shunted by 2 pF) and high slew rate assure minimal
loading and high fidelity in following high speed
pulses and signals. As shown below, the LH0033
is used as a buffer between MOS logic and a high
speed dual limit comparator. The device's high
input impedance prevents loading of the MaS
logic signal (even a conventional scope probe will
distort high output impedance MaS). The LH0033
adds about a 1.5 ns to the total delay of the comparator. Adjustment of voltage divider R 1, R2
allows interface to TTL, DTL and other high
speed logic forms.

FIGURE 13.

Another application that utilizes the low input
current, high speed and high capacitance drive
capabilities of the LH0033 is a shield or line
driver for high speed automatic test equipment.
In this example, the LH0033 is mounted close to
the device under test and drives the cable shield
thus allowing higher speed operation since the
device under test does not have to charge the cable.

FIGURE 14. Instrumentation Shield/Line Driver

FIGURE 11. High Speed Dual Limit Comparator for
MOS Logic

The LH0033 was designed to drive long cables,
shielded Cables, coaxial cables and other generally
stringent line driving requirements. It will typically
drive 200 p F with no degradation in slew rate and
several thousand pF at a reduced rate. In order to
prevent oscillations with large capacitive loads,
provision has been made to insert damping resistors
between V+ and pin 1, and V- and pin 9. Values
between 47 and lOOn work well for C L
1000 p F.
For non-reactive loads, pin 12 shou Id be shorted to
pin 1 and pin 1(j shorted to pin 9. A coaxial driver
is shown in Figure 13. Pin 6 is shorted to pin 7,
obtaining an initial offset of 5.0 mV, and the 43n
coupled with the LH0033's output impedance
(about 6n) match the coaxial cable's characteristic impedance. C, is adjusted as a function of
cable length to optimize rise and fall time. Rise
time ,.for the circuit as shown in Figure 12, is
10 ns.

The LH0033's high input impedance and low
input bias current may be utilized in medium
speed circuits such as Sample and Hold, and D to
A converters. Figure 15 shows an LH0033 used
as a buffer in medium speed D to A converter.
Offset null is accomplished by connecting a lOOn
pot between pin 7 and V-. It is generally a good
idea to insert 20n in series with the pot to prevent
, excessive power dissipation in the LH0033 when
the pot is shorted out. I n non-critical or AC
coupled applications, pin 6 should be shorted
to pin 7. The resulting output offset is typically
5 mV at 25°C.

>

FIGURE 15.

The high output current capabil ity and slew rate
of the LH0033 are utilized in the sample and hold
circuit of Figure 16. Amplifier, A 1 is used to
buffer high speed analog signals. With the configuration shown, acquisition time is limited by the
time constant of the switch "ON" resistance and
sampling capacitor, and is typically 200 or 300 ns.
A 2's low input bias current, results in drifts in
50 mV
°
lV
hold mode of - - - at 25 C and at 125°C.
sec
sec

FIGURE 12. LH0033 Pulse Response into 10 Foot
Open Ended Coaxial Cable

The LH0033 may be utilized in AC applications
such as video amplifiers and active filters. The
circuit of Figure 17 utilizes boot strapping to
achieve input impedances in excess of 10 Mn.
AN48-3

where:

Av

= No

load voltage gain, typically 0.99~

V+ = Positive Supply Voltage.
ANALOG

V-

OUTPUT

INPUT

= Negative'Supply Vol,tage.

For the foregoing application, 6 V 0 would be
-100 mY. This apparent "offset" may be adjusted
to zero as outlined above.

"POIVClfboolteor Tetlon

LOGIC
INPUT

L

Figure 19 shows a high' a; notch filter which takes
advantage of the LH0033's wide bandwidth. For
the values shown, the center frequency is 4.5 MHz.

1/2DH00J4

1
FIGURE 16. High Speed Sample & Hold
I
to =2I1'R1Cl

Rl-2R2

C2

Cl-2"

FIGURE 19. 4.5 MHz Notch Filter

.801pF

INPUT~

fH;;::100MHz

FIGURE 17. High,lnputlmpedance AC Coupled
Amplifier
.

A single supply, AC coupled amplifier is shown
in Figure 18. Input impedance is approximately
500k and output swing is in excess of 8V peakto-peak with a 12V supply.
Vee = 12.0V

The LH0033 can also be used in conju nction with
an operational ampl ifier as current booster as
shown in Figure 20. Output currents in excess of
100 mA may be obtained. Inclusion of 150n
resistors between pins 1 and 12, and 9 ,and 10
,provide short circuit protection, while decoupling
pins 1 and 9 with 1000 pF capacitors allow near
full output swing.

'The

v~,lue fo~ the, short circuit cu'rrent isgiveh by:
V+
I c=---

s -

where:

Isc

RLiMIT

s: 100 rnA.

.OO1/1F

INPUT~

. > - - - -......-0

OUTPUT

FIGURE 18. Single Supply AC Amplifier
'ouT>100mA

,15

The LH0033 may be readily used in applications
where symmetrical supplies are unavailable or may
not be desirable. A typical application might be
an interface to an MOS shift register where V+ =
5.0V and V- = -25V. In this case, an apparent
output offset occurs. I n real ity, the output voltage
is due to the LH0033's voltage gain of less than
unity. The output voltage shift due to asymmetrical supplies may be predicted by:

AN48--4

Isc

2!:

i50i'i"

100mA

FIGURE 20. Using lH0033 as an Output Buffer

SUMMARY
The advantages of ,a FET input buffer have been
demonstrated. The LH0033' combines very high
input impedance, wide bandwidth, very high slew
rate, high output capability, and design flexibility,
making it an ideal buffer for applications ranging
from DC to in excess of 100 MHz.

»2
A~gust

I

1971

~

CD

-2'1J
-C
'0
C
m
C
:::D

<
m

PIN DIODE DRIVERS

:::D

en

,IN'TRODUCTION
"'ThEf DH00351DH0035C is a TTL/DTL'compati,ble,
DC" coupled, high speed PIN diode driver. It is

'capable of delivering peak currents in excess: of
:one.ampere at speeds up to 1O'MHz.' This article
demonstrates how the DH0035' may be appJied to
d~iving PIN diodes and comparable loads which
'require high peak curreritsat hi'ghrepetition rates.
The salient characteristics of the device are summarized in Table I.

There are essentially two considerations of interest
in the "ON" condition. Fir's~, the amount of
"ON" control current must be sufficient such that
RF signal current will not significantly modulate
the "ON" impedanCe of the 'diode. 'Secondly, the
time required to achieve the "ON" condition must
be minimized.
"

C2

Cl

RFINC·

RF

OUT

RFC,

PARAMETER

CONDITIONS

VALUE

Differential Supply
Voltage(V+ -V-I:

30V Max.

Output (:;urrent

1000 mA

Maximuni Power

1.5W

tdelay

PRF

trise :,

v+ - V-

=

5.0 MHz
=

20V

,v+~

V-:, 20V

CONTROL NOOE

FIGURE 1. Simplified PIN Diode Switch

10 ns
15 ns

10% to 90%
tfait"

E-'. . . . . . - . . . .

10' ns

90% to 10%

The charge control model of a diode 1 ;2 leads to
the charge continuity eqLiation given inequa~
tion(1 ).

dt
where:

0

Figure 1 shows a simplified schematic of a PI N
diode switch. Typically, the PI N diode is used in
R F through microwave frequency modulators and
switches. Since the diode is in shunt with the R F
path, the R F signal is attenuated when the diode
is forward biased ("ON"), and is passed unattenuated when the diode is reversed biased ("OFF").

+

(1)

T

= charge due excess minority carriers

T ==

, PIN DIODE SWITCHING REQUIREMENTS

0

dO

: Table I ,DHQ035 Characteristics

mean life time of the minority carriers

Equation (1) implies a circuit model shown in FigdO
ure 2. Under steady conditions dt == 0, hence:
Q

IDe ==

where:

7" or 0 =

IDe T

(2)

== steady state "ON" current.

AN49

1

The time response of the charge, hence the time
for the diode to achieve the "ON" state coutd be
shortened by applying a current spike, I pk, to the
diode and then dropping the current to the steady
state value, loc, as shown in Figure 3b. The
optimum response would be dictated by:

I = TOTAL CURRENT
IDe = SS CONTROL CURRENT
iRF = RF SIGNAL CURRENT

(Ipk) .(t)

=

T'l oc

(5)

FIGURE 2. Circuit Model for PIN Switch

The conductance is proportional to the current, I;
hence, in order to minimize modulation due to the
RF signal, loc »
i RF • Typical values for loc
range from 50 rnA to 200 rnA depending on PI N
diode type, and the amount of modulation that
can be tolerated.
.' The time response of the excess charge, 0, may be
evaluated by taking the Laplace t'ransform of
equation (1) and solving for 0:

O(s)

=

71(s)
1 + S7

IDe - -

a

I

I
I

(3)

Solving equation (3) for Ott) yields:
Ott)

=

L-1 [O(s)]

=

17(1 _ €-tlT)

(4)

The time response of Q is shown in Figure 3a. As
can be seen, several carrier lifetimes are required
to achieve the steady state "ON" condition (0 =
loc· 7).

FIGURE 3b.

The turn off requirements for the PIN diode are
quite similar to the turn on, except that in the
"OF F" condition, the steady current drops to the
diode's reverse leakage current.
A charge, loc'7, was stored in the diode in the
"ON" condition and in order to achieve the "OFF"
state this charge must be removed. Again, in order
to remove the charge rapidly, a large peak current
(in the opposite direction) must be applied to the
PIN diode:

IDe - - ' - - - - - - - -

a

I

I

I

'~'~-Vi

a

-lpk»T"

(6)

It is interesting to note an implication of equation
(5). If the peak turn on current were maintained
for a period of time, say equal to T, then the diode
would acquire an excess charge equal to Ipk·T.
This same charge must be removed at turn off,
instead of a charge loc'7, resulting in a considerably slower turn off. Accordingly, control of the
width of turn on current peak is critical in achieving rapid turn off.

APPLICATION OF THE DH0035 AS A
PIN DIODE DRIVER

FIGURE3a.

AN49-2

The DH0035 is specifically designed to provide
both the current levels and timing intervals required to optimally drive PI N diode switches. Its

v'

R1

OUTPUT

250n

R2

3 kn

FIGURE 4. DH0035 Schematic Diagram

5.0V

r-

_...!.1 ----,

I

I
Ia

I
I

I
I

I
lOGIC
INPUT

II

~~

I

I

I

I-

__a______~__-+~

1/2 OM7830iOM8830

!

L---.:r-----'

Ch

120 pF

-=

V- = -10.IIV

FIGURE 5. Cathode Grounded Design

schematic is shown in Figure 4. The device utilizes
a comp.lementary TTL input buffer such as the
DM7830/DM8830 or DM5440/DM7440 for its
input signals.
Two configurations of PIN diode switch are possible: cathode grounded and anode grounded. The
design procedures for the two configurations will
be considered separately.

ANODE GROUND DESIGN
Selection of power supply voltages is the first consideration. Table I reveals that the DH0035 can
withstand a total of 30V differentially. The supply
voltage may be divided symmetrically at ±15V, for
example. Or asymmetrically at +20V and -10V.
The PIN diode driver shown in Figure 5, uses ±1 OV
supplies.

AN49-3

When the 0 output of the DM8830 goes high a
transient current of approximately 50 mA is applied
to the emitter of 0, and in turn to the base of 0 5,
0 5 has an hfe = 20, and' the collector current is
h fe X 50 or 1000 mA.. This peak current, for the
most part, is delivered to the PIN diode turning it
"ON" (RF is "OFF").

where: D.C. = Duty Cycle =
("ON" time)
("ON" time + "OF F" time)
Pmax = 1.5W
In terms of loc:

Ipk flows until C2 is nearly charged. This time is
given by:

,~

where:

=

loc

C26.V
Ipk

for V-

For the circuit of Figure 5 and a 50% duty cycle,
P diss = 0.5W.

6. V = the change in voltage across C2.

Iv-I- Vf(PI N Diode) - Vf cR , - V sat05
=i'

~10V,

6.V

'7

(8)

BV.

Once C2> is charged, the current will drop to the
steady state value, I DC, wh ich is given by:
V

V+ Vec
loc = RM -".R - ~

Turn-off of the PIN diode begins when the 0 output of the DM8830 returns to logic "0" and the
Q output goes to logic "1". O 2 turns "ON", and
in turn, ca\Jses 0 3 to saturate. Simultaneously, 0,
is turned "OFF" stopping the base drive to 0 5,
0 3 absorbs the stored base charge of 0 5 facilitating its rapid turn-off. As 05'S collector begins to
rise, 04tLirns "ON". At this instant, the PIN
diode 'is still in conduction and the emitter of 0 4
is held at approximately -0.7V. The instantaneous
current available
clear stored charge out 6f the"
PI N diode is:

to

(9)

3

where:

Vcc = 5.0V
R, = 250n
R3 = 0n

59

(13)

. R
(R 3 ) (6.V) (R,)
.. M = R,V++foC R 3 R ,+VCC R3

(9a)
where:

For the driver of FigU(e 5, and loc = 100 mA, RM
is 56 ohms (nearest standard value).
Returning to equation (7) and combining it with
equation (5) we obtain:
TIOC

Ipk

(12a)

(7)

Prior to 05'S turn on, C2 was charged to the minus
supply voltage of ~10V. C2'svoltage will rise to
within two diode drops plus a V sat of ground:
V =

s:

(Pmax) _ (V+ - V-)2]
[ (D.C.)
500
Iv 1-.6.V

C2 V
Ipk

(10)

Solving equation (10) for C2 gives:

hfe + 1 = current gain of 0 4 = 20
V BE 04 = base-em itter drop of 0 4 = 0.7V
Vf(PIN), =.forward drop of the PIN "
diode = 0.7V
For typical values given, Ipk = 400 mAo Increasing
V+ above 10V will improve turri-off time of the
diode, but at the expense of power dissipation in
the DH0035. Once turn-off of the diode has been
achieved, the DH0035 output current drops to the
reverse leakage of the PI N diode. The attendant
power dissipation is reduced to about 35, mW.

(11 )

CATHODE GROUND DESIGN
For

7

= 10 ns, C2 = 1 20 p F .

One last consideration should be made with the
diode in the "ON" state. The power dissipated by
the DH0035 is limited to 1.5W (see Table I). The
DH0035 dissipates the maximum power with 0 5
"ON". With 0 5 "OFF", neglible power is dissipated by the device. Power dissipation is given by:

Figure 6 shows the DH0035 driving a cathode
grounded PIN diode switch. the peak turn-on
current is given by:

= 800 mA for the values shown.
The steady state current, I DC, is set by Rp and is
given by:
loc =

x (D.C.)

AN49-4

~

Pmax

(12)

V+ - 2V BE

R3

tl+".1
+ Rp
fe

5.0V

c~-:!-

r---l,~ __ -,

1
250 :F'

I
1

I
I

1

I

I
I
Iii

I

I

I

Q

---~.--~

IN

!.

'....11
~--1--1/2 D;"8830

FIGURE 6. Anode Grounded Driver

where:

2V BE = forward drop of 0 4 base emitter
junction plus V f of the PI N diode = l.4V.

In termsof Rp, equation (15) becomes:

Rp

=

(h fe + 1) (V+ - 2V SE )
(h fe + 1) loc

-

Again, the power dissipated by the DH0035 must
be considered. I n the "0 F F" state, the power
dissipation is given by:

(20)

loc R3
(15a)

For the circuit of Figure 6, and loc = 100 mA,
Rp is 62 ohms (nearest standard v.alue).
It now remains to se~ect the value of C1 . To do
this, the change in voltage across C 1 must be
.evaluated. In the "ON" state, the voltage across
C1 , Vc, .is giver by:
(16)

where:

D.C.

= duty cycle =

"OFF" time
"OF F" time + "ON" time
The "ON" power dissipation is given by:

PON

= [(V~~N2 +

IDe x (VC)ON

1

(1 - D.C:)
(21 )

For the values indicated above, (VC)ON = 3.8V.
where:

(VC)ON is defined by equation (16).

In the "OFF" state, Vc is given ·by:

= 8.0V

( 17)

Total power dissipated by the DH0035 is simply
PON + POFF ' For a 50% duty cycle and the circuit of Figure 6, P diss = 616 mW.

(18)

The peak turn-off current is, as indicated earlier,
equal to 50 mA x hfe which is about 1000 mAo
Once the excess stored charge is removed, the
current through 0 5 drops to the diodes leakage
current. Reverse bias across the diode = V- - V sat ==
-10V for the circuit of Figure 6.

for the circuit of Figure 6.

Hence, the change in voltage across C 1 is:
V

(VC)OFF - (VCloN
8.0 - 3.8

REPETITION RATE CONSIDERATIONS

4.2V
The v~ lue of C1 is given, as before, by equation
(11) :
( 19)

Although ignored until now, the PRF, in particular,
the "OFF" time of the PIN diode is important in
selection of C2 , R M , and C 1 , Rp. The capacitors
must recharge completely during the diode "OFF"
time. In short:
(22a)

Fora diode with
C 1 = 250 pF.

7

=

10 ns and loc

= 100

mA,
(22b)

AN49-5

FIGURE 7. RF Turn-On (10 ns/em)

FIGURE 8. RF Turn-Off (10 ns/em)

CONCLUSION

,
)

The circuit of Figure 6 was breadboarded and
tested in conjunction with a Hewlett-Packard
33622A PIN diode.
IDe was set at 100 rnA, V+ = 10.0V, V- = 10V.
Input signal to the DM8830 was a 5V peak,
100 kHz, 5 /J..S wide pulse train. RF turn-on was
accomplished in 10-12 ns while turn-off took
approximately 5 ns, as shown in Figures 7 and 8.
I n practice, adjustment C2 (C,) may be required
to accommodate the particular PI N diode minority
carrier life time.

SUMMARY
A unique circuit utilized in the driving of PI N
diodes has been presented. Further a technique

AN49-6

has been demonstrated which enable the designer
to tailor the DH0035 driver to the PI N diode
appl icati on.

REFERENCES
1. "Pulse, Digital, & Switching Waveforms", Jacob
Millman & Herbert Taub, McGraw-Hili Book
Company, Inc., New York, N.Y.
2. "Models of Transistors and Diodes", John G.
Linvill, McGraw-Hili Book Company, Inc., New
York, N.Y.

3. National Semiconductor AN-18, Bert Mitchell,
March 1969.

4. Hewlett-Packard Application Note 914, January
1967.

»
2

September 1971

..
I

U'1

»
c::
2

o

A UNIQUE MONOLITHIC
AGe/SQUELCH AMPLIFIER

c::
m

~

o
2

o

r~

:t
INTRODUCTION

o

As complexity and usage of communication
systems increases, there is _a growing use of a
special class of circuitry, designed to make the
system more convenient to the user, as well as
allowing it to adapt to changes in the transmission
channel. The most common function is voltagevariable gain, used in volume compression and
expansion, and a specialized case, squelch, in
which gain remains either in its maximum or
minimum state.

transients onto the signal during periods of rapid
gain changing. Two mechanisms may be defined
for these elements; either effective resistance or
effective transconductance is varied by the DC
control voltage. Because the variation is accomplished by changing quiescent operating pqint~,
DC decoupling is required at the output, and only
ACsignals may be handled. DC decoupling,
however, still allows rapid changes in DC operating
point to be transmitted as switching transients.
While linearity is claimed for FET and the lampphotocell schemes, such linearity is still only part
of a large-signal nonlinear char'acteristic~ With any
of- the elements, quasi-linearity is obtained by
traversing a small segment of the overall element
range; hence, variable gain elements must precede
any system voltage gain.

The main problem in such circuitry is finding a
suitable nonlinear element to do the job. Conventional elements, appe?ring in Table 1, share
common problems of distortion, cost, limited
signal handling capability, sometimes limited gain
reduction range, and usually insert unwanted

TABLE 1. Conventional Gain Control Elements

ELEMENT

MECHANISM

CONTROL
RANGE

CONTROL!
LARGE
OUTPUT
SIGNAL
ISOLATION HANDLING

COMMENTS

P-N Junction

Forward Resistance

Good

Poor

Poor

Bipolar Transistor

Saturation Resistance

Fair

Poor

Fair

Beta Dependent

FET

Channel Resistance

Good

Poor

Fair

Unpredictable gate
control voltage
requirements; for
driving fairly high
impedance loads

Photocell-Lamp

Photocell Resistance

Good

Good

Good

Requires power to
drive lamp; cell must
be shielded from
ambient light

FET

Transconductance

Fair

Poor

Poor

Unpredictable gate
control voltage
requirements; for
driving fairly high
impedance loads

Bipolar Transistor

Transconductance

Fair

Poor

Poor

Commonly used in
AM-I F appl ications

Tetrode Vacuum Tube

Transconductance

Fair

Poor

Good

Filament Power

Simple, predictable

AN51-1

»
C)
o

.........
CJ)

o
c::

m
r-

o

:t

»
~

-a
r-

."

m
;:x,

A. MONOLITH IC APPROACH

A feedback circuit senses common-mode output
from the' emitter followers, and compares it with
the DC control voltage, to reliably set attenuation
characteristics. For maximum gain, 0 3 and 06
behave as ordinary emitter followers. As the control voltage rises, 0 4 and 0 5 begin to conduct,
effectively "robbing" 0 3 and 06 of available DC
emitter current. Consequently, dynamic emitter
resistances of 0 3 and 06, in series with the signal,
increase, while those of 0 4 and 0 5 decrease,
shunting across the signal. In the limit, 0 3 and 06
are com~letely cut off, and the shunt pair fully
conducting.

Because of . the inexpensive complexity possible
with monolithic construction, techniques may be
used which circumvent many of the shortcomings
of discrete gain 'control circuits. The balanced
diode attenuatof of Figure 1 allows variable serieso'lFfERfNTIAl - - - - - - _ ,
INPUT

GAIN

CONTROL

FIGURE 1. Balanced Diode Attenuator

shtintattenuation, and if used in a differential circuit, 'with monolithic matching, can cancel all
sptl'rious control~signal effects at the output. Figure 2 gives
subsystem block diagram, for effectively controlling' the balanced arrangement of
Figure LAn input differential amplifier provides
differential diode drive even if only single ended
inputs are available, and keeps the common-mode
DC level to 0 3 and 06 at a constant level. Notice
that emitter followers have been substituted for
simple diodes! giving higher input impedance, and
superior gain reduction range. The input diff.-amp.
also prevents gain changes from affecting the input
impedance. Since the control elements are quasilinear only for small signal voltages, the input diff.amp. has unity gain, with all circuit gain being
performed after the variable elements.

a

FIGURE 2. System Block Diagram

Emitter follower output is fed into a differential
input, single-ended output amplifier, where common-mode changes resulting from the gain control
voltage are rejected, and the signal is amplified to
usable levels. Thus, the system is a variable gain
DC amplifier.

....- -...- ....-___it____....- _ _ _ i t _ - -. . .___it__t.____t~___it__{)

r-----t~--

R6
20K

+Vee

PIN9

...- t - - t....-oOUT
PIN 8

....~--...---~t----~~t--~~.-----~~~~~~~~--~-e-oGND

~-

PIN 5

I.,

AN51-2

FIGURE 3. LM170 Schematic

MONOLITHIC REALIZATION

A practical version of Figure 2's block diagram,
National's LM170 appears as a schematic in Figure 3. Despite its apparent complexity, and its use
of 34 junction devices and 20 resistors, the entire
circuit has been compressed onto a 39 x 42 mil
monolithic chip, Figure 4, smaller than. most
operational amplifiers.

control feedback amplifier; 0 22 and 0 23 are
matched constant current sources, whose operation is stabilized by the same circuit that regulates
the input stage. Rather than obtain a commonmode feedback voltage with resistors as in Figure
2,010 and 0 11 are used, saving chip space reducing
emitter follower loading, and giving a fixed voltage
drop at the summing point. Two emitter followers,
0 24 and 0 32 are available as gain control inputs,
allowing considerable control versatility, and may
be used as peak detectors, as well. Control input
overvoltage protection is provided by zener diodes
(reverse base-emitter junctions), 0 33 and 0 34,
while feedback amplifier excursion is limited by
another zener, 0 35 , Bias levels are set so that AGC
action begins when the applied control voltage
equals three forward diode drops, about +2.1V. As
control voltage is further increased, gain is reduced
by progressively shunting current from 0 3 and 0 6
into 0 4 and Q5; the "transition width" of the
system is about 400 mV, so that above approximately +2.5V, minimum gain is obtained. These
control levels were chosen to be compatible with
tuned gain control amplifiers, such as the LM171
RF/IF amplifier, elsewhere in the system, and to
allow the circuit to· be driven, in switched-gain
applications, by standard monolithic 5V logic,
such as TTL, DTL, or RTL.

FIGURE 4. LM110 Chip

Examining first the input circuit, Figure 5, one
may notice that the configuration is essentially
that of the highly successful LM 101 operational
amplifier. Emitter followers, 0 1 and O2, combine
with an unusual lateral PNP configuration, 0 12
and 0 13, to allow large common-mode input range
(up to and including the positive supply voltage),
low input offset voltage, and the ability to withstand large differential input overvoltages without
damage. Common-mode feedback to a differential
current source, 0 14 and 0 15 , along with a stable,
diode determined reference, automatically biases
the differential input configuration to give constant
and predictable DC common-mode output voltage,
despite variations in the relatively unpredictable
lateral PNP "beta". The input circuit draws constant power supply current regardless of power
supply voltage, and consequently exhibits predictable input impedance and bias currents.

"15

1son

"16
JK

FIGURE 6. LM170 AGC Section

To increase usable dynamic input range, and decrease distortion, R2, R3, R4 and R5 are added
to the differential gain control section. These
resistors have little effect on other circuit parameters, but help to "Iinearize" the transfer characteristic throughout the gain control region.
The output stage, Figure 7, provides large commonmode rejection, and a single-ended output, which
has a quiescent value halfway between ground and
the positive supply. Output stage voltage gain is a
function of supply voltage, being approximately
100 (40 dB) at Vee = 12V. Thus, except for its
lower gain, the LM170 has the same configuration
and essential characteristics as an operational amplifier.

FIGURE 5. LM170 Input Differential Amplifier

The gain control circuit, Figure 6, operates as outlined in Figure 2; 0 25 , 0 26 and 0 27 form the

Output impedance is intentionally high (5000
ohms), and short-circu it resistant. Thus, any numAN51-3

charge of the time constant capacitor, so that
effective fast-attack, slow-release squelch occurs.
Since 0 21 is part of a Darlington, and has a base
current limiting resistor, R20 , it will neither saturate nor damage itself when large electrolytic
capacitors are used; however, it will draw sufficiently large currents to bring the capacitor below
the 2.1V gain control threshold, and then taper
off in discharge rate.
GENERAL APPLICATION CONSIDERATIONS
FIGURE 7. LM170 Output Stage

ber of LM 170' s may be directly tied together at
their outputs, for multi-channel mixing or switching applications.
For AGC systems, output signal voltage is usually
peak-detected, and fed back to the gain control
input, maintaining essentially constant output voltage with widely varying input signals. In the case
of squelch, however, the output is normally completely off, in the absence of input signals; thus,
control voltage for squelch operation cannot be
derived from the output, but must be sampled
before the gain-reduction stage. Figure 8'shows the
built-in squelch amplifier and detector. Lateral
PNP transistors 0 12 and 0 13 are constructed with
two collectors. each, so that differential signals
drive the gain control stage, across R 13 and R 14,
and separately, from the second pair of collectors,
drive 0 20 , 0 36 , and 0 21 . The quiescent current
from the extra collectors is regulated by the same
feedback circu it that controls operation of the
input stage. If an external resistor (or potentiometer) is connected from Pin 7 to ground, it will
serve as collector load for 0 12 , and can be user
adjusted so that 0 20 , normally saturated, turns off
for peak signal voltages exceeding any desired
value. When this happens, 0 36 and 0 21 turn on,
discharging an external capacitor, and bringing the
voltage at Pin 6 below the threshold required to
turn the amplifier fully on. Since the collector
load for 0 20 is a current source, in parallel with a
high impedance Darlington pair, 0 36 and 0 21 , the
voltage gain of the squelch detector is very high,
and abrupt action occurs with even small incoming
signals.

As with any device capable of producing gain,
when using the LM 170, consideration must be
given to proper layout of the device and its external circuitry to prevent any undesirable feedback
that may cause oscillation. Since the inputs may
be biased either directly from Vee or indirectly
through a divider network, effective power supply
bypassing is essential. To guarantee effective bypassing at all frequencies, mUltiple bypassing should
be used. A large capacitor, 10 IlF or greater, should
be used to absorb all low frequency power supply
variations and a smaller capacitor, approximately
.01 IlF, to prevent any high frequency feedback
through Vee. These should be located as physically
close to the device as possible.
Vee

FIGURE 9. Input Biasing

FIGURE 10. Input Biasing

and Decoupling Network

and Decoupling Network

Additional DC input stability may be necessary.
This is most easily accomplished by a series RC
roll-off from Vee to the inputs to ground. If the
inputs are to be biased directly from Vee, the
network should be connected as in Figure 9.
Values of 1k ohms and 10 IlF give a roll-off that
is 3 dB down, at approximately 17Hz. Since the
input bias current is typically around 8.0 IlA, the
voltage drop across the 1 k ohm resistor will be
negligible. If the inputs are biased at some common
mode voltage less than Vee, then the addition of a
single capacitor from the common mode input
point to ground accomplishes the same thing (see
Figure 10). Again, a value of approximately 10 IlF
will give effective roll-off.

FIGURE 8. LM170 Squelch Detector

The input stage exhibits the same high tolerance to
abuse as does the LM 101; large currents forced into
either input (when input voltage exceeds the positive supply by more than 0.7V, for example)
should be avoided. If such transients normally
occur in the system, as frequently is the case
during turn on or turn off, protect the inputs with
series input resistance.

The external capacitor and large charging resistor
can be chosen for time constants up to several seconds, for releasing the .squelch; .the geometry of
0 21 , however, is large, allowing a very fast dis-

An inspection of the self-balancing action within
the LM 170 explains how large gain changes can be
achieved, without appreciable DC output shift.
Obviously, if all components in the 'circuit are

TO GAIN CONTROL
INPUT
COMMON·MODE

FEE:A: 0

SQUELCH!

THRESHOLD

{ext}

AN51-4

exactly matched, this will work perfectly. There
are two possible sources of DC output shift in the
LM170. The first is an unavoidable small V SE mismatch between critical components, causing small
differential shifts to appear ahead of the output
gain stage, along with the usual large commonmode shifts. Units are selected, to various specifications, at the factory, for low output shift. The
second source of DC shift is externally induced input offset voltage. As with any operational-type
amplifier, a certain bias current must flow into each
input, in the microampere range, to operate the
input transistors. While input offset current (the
difference between the two input currents) is very
low, use of unequal source resistances will cause
different voltage drops across each input resistor
or a net input offset voltage. For critical applications, then, especially if large input resistance is
used, it is recommended that equal input resistors
be. used. Conversely, if the least expensive graded
units are used, and minimum output shift is still of
importance, input offset voltage may be individually trimmed for each unit, to give nearly ideal
characteristics, as observed on an oscilloscope.
Another serious source of offset can occur when a
large capacitor is used to couple to the input of the
LM 170. This may cause brief periods of positive
feedback during a portion of the input waveform
cycle, during which the device may oscillate. This
may be easily prevented, however, by connecting a
capacitor of approximately the same value as the
input capacitor from the unused input terminal
to ground.
Gain control inputs, Pins 3 and 4, are shunted by
6.5V zener diodes. If control voltage is anticipated
to go above +6.5V, and if the driving source is
capable of providing more than about 10 mA
under these conditions, it is advisable to protect
the zeners with a series resistance at each gain
control input.
While the large geometry squelch output transistor,
0 21 , is capable of sinking large instantaneous
discharge currents from electrolytic capacitors, it
is not advisable to attempt sinking large (more
than 50 or 100 mAl continuous currents from
"stiff" voltage sources, which may cause large
dissipation on the chip.
The LM170's ability to accept common-mode
input voltage equal to the positive supply can be a
great convenience to the circuit designer, and saves
several components, in such applications as direct
dynamic microphone drive. It should be realized,
however, that this system w~rks only with the
small (under 100 mV) input signals for which the
circuit was intended. While input transistors Q 1
and O 2 still are effective as emitter fol·lowers with
zero, and even less than zero volts collector-tobase, .large positive base voltages (more than about
400 mV above the positive supply, will allow 0 1 .
and O 2 to saturate, degrading amplifier gain, input
impedance, bandwidth, and· input· bias current.
Normal operation should never see ,more' than
about 50 mV of input signal, so that this is not a
problem.
.

AGC APPLICATIONS
AGC Using Built in Detectors
In most systems, the LM170 will be followed by
further voltage amplification. This may be advan··
tageous, as it can provide increased forward gain in
the AGC loop, resulting in tighter output regulation. I n systems having widely varying load imped·
ances, AGC derived from the system output can
automatically compensate for additional output
loading:- Connected as in Figure 11, the emitter
follower at Pin 4 is used as a high impedance
detector, with detector smoothing performed by a
capacitor at Pin 2. DC threshold for the detector is
set at any desired level by a potentiometer, determining the positive peak output voltage which
initiates gain regulation.

500,'

~

001
' - -_ _---i 1'f-'- - 0 - - - . . . . 1

FIGURE 11. LM170 AGe Using Internal Peak Detector
and Additional System Gain

A word of caution is necessary here. When operating the LM 170 with an external gain stage to
provide very high AGC loop gains (on the order of
several hundred), proper layout is essential. As
with any high gain circuitry, good power supply
regulation isa necessity. Multiple bypass capacitors
are used (Figure 11) to give effective wide band
filtering. This should prevent any undesirable ripples or transient spikes from being transferred from
one device to another through V cc.
Depending on the amount of external loop gain
desired, several other steps may be necessary. As
with many other AGC circuits, there is a DC shift
in output voltage associated with the change in
,applied AGC control voltage. If this shift is fast
enough and of sufficient magnitude, it may be
coupled from the output of the LM 170 to the
following gain stage. This may cause severe spiking
in the output of the LM 170 which may swing the
gain stage into limiting causing extreme distortion.
This can be prevented by providing a given amount
of offset in a given direction to the input of the
LM 170:-Jf an increase in AGC voltage at the AGC
threshold causes a positive shift in output voltage,
it may be fed back through the system to cause
a further increase in AGC control voltage. If,
however, an increase in AGC voltage causes a
negative shift in output voltage, when this shift
is fed back it will tend to decrease AGC voltage
which shpuld help to prevent the spike from
occurring. In normal application, the LM 170 inputs
are biased with approximately 2 kr2 resistors. If a
resistor on the order of 5 Mr2 is tied from the
inverting .input (Pin 1) to ground, it will provide
enough offset to control both the direction and
AN51-5

magnitude Qfthe output shiff A potentiomete'~,
may be . substituted to trim the offset to .a;ny ,
desired' value.
The other problem that mayoccur'cantesu'i1:from'
tOQI,arge an AC swing at theAGC cpntrol point.,
Pins 3 'and 4 are protected
posi'ti~e: 'ovet
voltCiges, bya 6.3V ze;"er~ If' th~ Ac'"svVfngi~so
large, that .i,t ~wj'ngs negative below . 7y ,the ~en'~r ~
wiU be forward bi·ased.lf this occurs, a parasitit'
NPN tr~n~ist~r' can b~ fgrmed ~aus)ng at:1'u~desi~'~(L
transistor action.To· prevent this,'two soluti6ns~rf{
available. In 'th~ first a germani:~~ diode: can "~e;
used to shunt all negative swings from the AGe'
pin to ground, It is tied directly from the AOC pin
(Pin,3ar Pi,n '4) to groLlnd, beingfo~~arqbia~~d,.if
t~e AC signal triesto.swing negative. The~ alteriJa~e'
method..
:i,hown in Fig\.Jre1 J is asiljc9n.dio9~:'in,
series withttie AGCpin. It i's forwarcf bias:eq for'ali,'
positive'voltages sD,DC b'ias is provid~d and all.
tive gOing AC swings provide prop~r A~C ac~idri::
All. negative SWing' are promptly c'ut off' at +().,7V.;/

'+12'V

from'

FIGURE 13. Internal Full Wave AGC Detection

8~tp'ut6f" the·l..M~;ib'or of fo'liowing gci'in stages if
th~ya'~eused: If'driven dir~ctlyfrorii the output of
th'i{' LM 170, 'a 'primary 'iri1p~dance greatertlian'
kn
shows that AGC

as

posi-

"

"

,

"

'

>,'

•

~ I.'

~

":

Car~shouid be 'taken to avoid eXposing th;:e circu;i'~:
to any' RF ':adia~ion or 60 Hz power iine fields
theyniayg~t 'in'to the high g?linioop 'and 'cause
erratic AGe' action.' Coupling' cap'aciiors'shoulcf
be" selected to give.' propel" 'op~ratiofi'over 'the)
desireq range, of freq\.Jencies. 'In Figur'e' 11, 'tHe loW'
frequency'lirniting factor is the.O; A:GC'fe~dback
capacitor which gives a roll
near '160 Hi:!
Increasing its size would proportionally lower the
, low frequ'ency c u t o f ( '
,,

as:

off

Figure 12 shows the output regulati6i1"resultirig'
from this' system with an added 46 dB of voltage
'
gain follbwing the LM 170.

. V<;>lt~g~(P!n 3 or Pin. 4~ .

fore ·if the trahsfOrmeY' output' 'prov ides a voltage
swing of approximately ,3,!, peak,,,.it will be more
than adequate. to . operate, the", LM 170 over its
entire AGC range.

AGCCJRG~jitWITHTRANSISTORDETECTOR
111', F igufe 15;'-ah externalPNP transistbractsas a
negative peak i detector, with· threshold selby a
potentiometer .,1 nits quiescent state', the PNP tran~
sistO'{is ; 'off.; .negative: goi ng 'signal' peaks," AC
coupledAo'thedeteotor, cause momentary conduc·
ti6n,"Whichturns ·'on'the' high, rmpedancegain
control input, Pih4>Pin' 2: is bypassed by. a ,rela~
tively large capacitor which will charge, and
maintain a sufficientp'c, ,voitage,tp\ operCJteth~
amplifier's gain at the correct level. This le~el, set
by the thresho~d 't)'Ote'nt'ibmeter; is'the' pOii:\Lat
VXbiQIl neQatiye,pe~!<~margina,Oy, turrton:the,P!"P
tran~lstor~ Jous,~ afihput'~~'gl)aJley~I)t:1creas~s; the

FIGURE 12. AGC Transfer Characteristics, ,Internal ..
Detector, For Varying Inputs'
Vert. = output, 10 mV/cm
Horiz. = input, JO mV/cm

Both 'available AGC' inpllts may be used, as in
Figure: 13, to prov'ide fu II-wave output detection,
which responds to both positive' and n~gative
output peak voltages.
If a transformer is used to provide ful'l wave AGe
detectiC)n as showl) in F igu re 13, it must b~ chosen
to meet twC) criteria. First, it must have a: high
enough input impedance to avoidloading down the'
"

AN51-6

circuhautori1atlcallY',I~wer.s. 9~in,. to 'rriai~tain '.~
~o'~~ta ~t peak ~to-peak' o~tP~ 'le~~1.' Si n~'e the'capacitor at Pin .2 c,annot follow instantaneous audio

t

Variations, audio frequency linearity is not disturbed, although charging from the low impedance
of Pin 2 and discharging through a much higher
resistance, causes fast attack, slow release AGe
action.

of an unused transmission channel must be removed, until. useful information is received. The
squelch circuit of ..Figure 17 includes a number of
refinements, which make it smooth-acting, and
easy on the ear of the listener.

In .this example, common-mode input bias is obtained directly .from Vee, through equal resistors,
to minimize offsets resulting from input bias
current.

The threshold potentiometer at Pin 7 is manually
set to cut in at any desired input level. The large
capacitor at Pin 6, and its associated charging
resistor, may be chosen to give squelch release'
times of as much as several seconds, while the
large current sinking capability into Pin 6 assures
fast attack, so that first speech ,syllables are not
lost.

The fam ily of transfer characteristics, F igu re 16,
shows that some output increase occurs as the
input increases, but by only a small percentage.

A portion of the voltage at Pin 6 is fed back to
the threshold potentiometer; since there are two
stable voltage states at Pin 6, this creates a controlled amount of hysteresis in the squelch circuit.
Thus, there exists a "dead band" of squelch
sensitivity, which greatly enhances the circuit's
immunity to rapid transmission channel fading, or'
erratic speeth patterns. Combined with the slowrelease characteristic, hysteresis gives a very wellbehaved squelch system. A typical threshold co.ntrol setting might be one at which amplificatiO.rl
begins above a 20 mV Pop input. With the feedbac.k
values shown, the input level must consistently
stay below 12 mV Pop before gain is cut off. The
small feedback resistor may be eliminated if hysteresis is not required.
FIGURE 16. AGC Transfer Characteristics Transistor
D.etector. For'Varying Inputs
Vert. =output, 10mV/cm
Horiz. =input, 10mV/cm

When .usingan .external peak detector, proper
layout and biasing are essential to prev~nt the
transistor from oscillating. As always multiple
bypassing of the power supplV should be used. In
addition, a capacitor of approximately .01 p,F
should be .connectedfrom the base of the PNP to
the collector and from the base to Vce. These
prevent any positive feedback from causing the
external. peak detector to oscillate.
SQUELCH APPLICATIONS

Squelch Preamplifier with Hysteresis
Audio squelch is useful in noisy acoustic environments, to suppress backgroundiTl'icrophone noises,
and in receivingsystert:ls, where the constant clatter

While squelch attack is abrupt, release follows the
slow charging contour of the time constant capacitor, through the logarithmic gain control region.
Thus, gain "fades out" follpwing cessation of
speech, rather than the .Iessear-pleasing effect of
conventiol1al squelch circuits, in which a rush of
background noise may be heard, fol1owed by·an
abrupt and often percussive cutoff ..
The time constant capacitor is charged by a voltage. divider, rather than a single resistor,
thatits
quiescent charged voltage is about· +3V, with .the
values shown, from 'g +12V supply. There is no
need to charge the capaci~or much above ·this
point, because gain has already been completely
cut off, and further charging only makes more
work for the large geometry transistor at Pin .6,. in
performing its rapid discharge function. In any
event, if a single charging resistor is used, the
timing capacitor cannot charge above about +6.'pV"
because both Pins 3 and 4 are shunted internally
by protective zener diodes .

so

..--___~------_4I~-.12V

lOOK

OUT

SQUELCH
THRESijOlD

2~!!C~::~
(SHORT TO GROUND TO
OEFEAT.HYSTERESISI
:~,~

,

CHARGING
RESISTOR

I

SO.F

.

-=-

FIGURE 1.1. Squelched Preamplifier with Hysteresis

In Figure 17, the LM170 appears in another of its
many possible input configurations. It is directly
driven by a low resistance dynamic or controlledmagnetic microphone, with no other input biasing
components required. The amplifier is compact
enough to fit inside even the smallest commercial
microphone cases; its low current drain from supplies between +4.5 and +6.OV would permit inclusion of batteries within the same case.
Figure 18 illustrates how a large number of such
microphones could be directly connected to a
AN51-7

OSCILLATORS
,

I

'

,

Wien-Bridge. Oscillator Using the LM170·
The classic Wien-Bridge Oscillator is still a popular
choice for many designs.

I

I

A brief review of the principle of this form of
oscillator will show how· ideally suited is the
LM 170 to this configuration.

I

I

MORE
MIC,ROPHONES

FIGURE 18. Random Access Microphone System

common bus, at their outputs, to give a random
access, automatic break-in pwblic address or paging
system, which might be useful, for example, at a
large. conference table, or. in a. courtroom. While
background noises at each microphone location
would be suppressed, close talking would immediately allow one or more speakers to be heard. Because squelch switching levels are compatible with
TTL logic, a priority logic system couJd be devised,
which would not only give certain speakers "breakin" priority, but allow them to automatically cut
off certain other speakers at the same tim·e.
TRANSMITTER OR TAPE RECORDER VOX·
In addition to squelching its own gain, the LM170
can become a voice~operated-relay control, or
VOX, to switch high powered electronic or electr.omechan.ical devices. Automatic transmit-receive
operation is possible in two waycommunicatiop
systems, or tape recorder motors may be switched
on at the first syllable of infrequent speech, such
as in dictation, conserving tape.
To handle large amounts of power, all that is
needed is a small PNP power transistor, driving a
relay, which can have multiple poles. Action is
essentially the same as in squelch operation, except
that the capacitor discharged by Pin 6 is charged
by the relay driving circuitry. The amplifier may
simultaneously be used as a continuous-running
preamplifier, may be squelched along with the
relay, or may even operate with an independent
AGC signal, into Pin 3 or 4.

FIGURE 19. VOX Preamp

A reed relay is shown in the schematic of Figure 19, but any fast acting relay may be used. The
relay coil is shunted by a diode, to protect the
PNPtransistor. If power supply impedance is high
the circuit may tend to oscillate; bypassing the
supply with a fairly large capacitor will eliminate
the problem.

AN51-8

Figure 20 shows the general configuration of the
Wien-Bridge oscillator.

FIGURE 20. General Wien-Bridge Oscillator Configuration

The componentsR 1 C 1 and R 2 C2 form a positive
feedback network whose transfer, it can be shown,
is a 'maximum wheri the lead produced by R 1 C1
and the lag afforded by R2C 2 have the same value.
At this condition the "gain" of the network's is

1
"Av =
...
.
. (1+R 1/R 2 +C 2 /Ci)
and .the frequency is given by the expression:
f

=
27TVR1 R 2 C 1 C2

R3 and R4 form a negative feedback loop and
control the gain of ·the amplifier. For sustained
oscillation, the loop gain of the system must equal
unity (in practice slightly greater), therefore the
condition for oscillation is
R3 + R4 == 1 + ~ + C 2
R4
R2

c;-

or

Amplitude control of an oscillator assists in stabilizing its frequency as well as amplitude since it
prevents the poles from wandering ~bout on their
root locus plot with gain' changes ande~sures
starting.
Practically, one of the negative feedback resistors
is often made voltage sensitive to ensure reliable
starting and to control the output.amplitude. If R3
is chosen to be voltage sensitive, its characteristic
has to be negative (such as a thermistor) or more
usually R4 is the control element, using, very
often, a light bulb which has a positive voltageresistance characteristic.
The simple elements such as the thermistor and
light bulb rely for their action on their thermal
characteristics. The response time for these devices
limits their usefulness.
Alternatively the gain Qf the amplifier itself may
be varied to afford amplitude stability.

It can now be seen how the LM 170 dovetails
nicely with the Wien-Bridge Oscillator configuration. It has gain, plus and minus inputs and· ~m
auxiliary control of gain via its "AGe Control
inputs".
Figure 21 shows a suitable low-frequency oscillator
design embodying the principles just discussed.

Decade Tunable Oscillator
By using a modifi~d twin-tee feedback network,
the LM 170 will produce a sine wave oscillation,
tunable over one decade in frequency. The technique used is shown in Figure 23 where wideband
positive feedback is applied to the non-inverting
input by the capacitive divider C 1 & C 2 . Capacitor
C 1 also decouples the input from supply noise.
vcc~-.-----------.,

R3
8Z0K

R28
J90K

R1
200K

R'A
390K

R48

RlA

390K

390K

Cl,C2=.1~F-8Hz

Cl.C2::.01IJF-BOHz

C2
001

FIGURE 21. Wie~-Bridge OsciUator

FIGURE 23. Decade Tunable Oscillator

The positive feedback loop from Pin.8, the outpyt,
to Pin 10 uses R =200k andC = .1.for 8 Hz. The
R of the lag arm is formed from two. resistors
which provide bias for Pin 10, they are of course
in parallel with regard to signal. The bias for Pin t
is provided in the same manner. The 820k resistor
together with the bias resistors provides amaxtmum loop gain of about4, the· system needs a gain·
of three for oscillation since the attenuation ·of .
the positive feedback loop at resonance is 3.

Negative feedb~ck occurs through the twin T at all
frequencies except the null frequency of the T
network, allowing the circuit to oscillate there.
The nominal low frequency of oscillation for the
cir~uit is approximately 320 Hz with the assymmetric parallel T shown. At this frequency and 1V
rms out, the total harmonic distortion is under
0.25%. At the upper frequency limit, 3300 Hz the
output has dropped less than 1.5 dB and the
distortion is 0.45%.

The resulting output is peak detected. at constant
Pin 4 of the device which is the base of an emitter
follower biased by the external adjustable potentiometer chain, the amplitude adjustment. Detector
smoothing is provided by the 1000MF capacitor
connected to Pin 2, the emitter of the detector
emitter follower. The large value is dictated in
this particular design by the desire to. achieve
regulation at about 10 Hz.

A Modulated 455 kHz Signal Generator
An inexpensive, high "Q", 455 kHz ceramic filter
may be substituted for the twin-tee feedback netMURATA
SFII5S0
CERAMIC
FILTER

The frequency may be changed by changing only
the capacitors up to a few kHz, beyond that it is
desirable to reduce the bridge resistor values so
that the input current offset characteristics of
the LM170 do not limit the performance. Oscillators.up to a few MHz may then be fabricated.

,

'"o

FIGURE 24. 455 kHz Modulated Constant Output

Oscillator.

\

~
o

!;;
C
u

~

\

~

~

.....:

~

...... ~

b

F-.:8~
r-

ff-

'"w~

~

~=80Hz

0
100

200

400

600

800

1000

OUTPUT AMPLITUDE (mVrms)

FIGURE 22. Oscillator Distortion vs Output Level

Figure 22 shows the distortion versus output
amplitude of the circuit shown in Figure 3 for
8 Hz and 80 Hz .versions of the oscillator.

FIGURE 25. 455 kHz Modulated by 100 Hz

AN51-9

circuitry, shown in Figure 27.connects one of the
AGC control pins, Pin 4, to the. collector of a
saturating switch, 0 21 , at Pin 6. With no signal,.
0 20 is saturated and 0 21 is off, and Pin 6 sits at
the voltage determined by the supply and resistive
dividing network, or by the internal zener.

work of the previous example, to create a regulated-output AM I F alignment generator, Figure
24. If the AGC threshold voltage, which determines
stabilized output, is varied at a low (audio) rate,
the output amplitude will be forced to track the
audio modulation, as in Figure 25.
The input configuration shown in Figure 19 may
be used when two power supplies are available
elsewhere in the system, as it allows the inputs and
output of the LM170 to be referred to ground. Of
course, any other suitable input biasing scheme
maybe used instead, for the 455 kHz signal
generator.
Simultaneous Squelch & AGe Using theLM170

SOUElCH
THRESHOLO

An interesting application of the. LM 170 involves
simultaneously obtainingAGC and a fast .attack,
slow release squelch. It has been contributed by
B. Chandler Shaw of Bendix Electrodynamics,
North Hollywood, California.
Vee

Vee

Vee

FIGURE 27. Normal Squelch Circuit

Note that no capacitor is connected to Pin 2. When
the combination of peak decreasing signal currents
and low enough shunt-values of SquelCh Thr~shold
control are such that the base drive for 0 20 no
longer causes saturation, 0 36 and 0 21 immediately
turn on, rapidly discharging the capacitor at Pin 6,
lowering the vO.ltage at Pins 4 and 2, and bringing
the amplifier quickly up to full gain. Upon cessation of the' signal, 0 20 saturates ,again turning
0 36 and 0 21 off, and the voltage at Pin 4 rises
according to the RC time constant of the network,
giving some delay, and finally a smooth turn-off'
of the amplifier.

IOAGe
ARRAY

DC
FE~OBACK

I
I

,/0
lM110

L:'

B

- 3

AUDIO
'DC
INPUT

FIGURE

.2

----

Cl~FIlTER

26. Internal AGe Conte.ol Circuitry

In normal AGe operation, a filter capacitor is
required on Pin ~ to store the peak AGe control
signal. The circuitry involved, shown in Figure 26,
uses the emitter follovver.Q24 as a ,buffer and peak
detector. ObVIously, the voltage on the filter capacitor can be rapidly increased (lowering the gain)
by the current available through the emitter follower but decreases slowly by discharging through
the 50k resistor (increasing the gain). This is exactly opposite of what we requ ire. The normal squelch

If a filter capacitor were connected from Pin 2 to
ground, it would not be possible to lower quickly
the voltage at Pin 2 to obtain a fast attack squelch.
HOVl(ever, if the capacitor C1 is connected to Pin 6,
as shown in Figure 28, Pin 2 is drawn down
rapidly when unsquelching and the low impedance path through 0 21 provides the ground for the
filtering action required for AGe with signal and
threshold level applied at Pin 3. With no signal,
0 21 turns off and the voltage at Pin 4 rises norVee

Vee

Vee

TO AGC
ARRAY

DC
FEEDBACK

r---'I
Vee

I
I

_

2,5K

~...;...L~O_ - _
SQUElCH
THRESHOLD

L.. lOOK

-

4' A

-

3

B

-

_----I ...- - - -..111-'-

L-..-----'w'V-----+- DC THRESHOLD
33K

. FIGURE 28. Simi.altaneous Squelch andAGC

AN51-10

AUDIO FEEDBACK

.J

mally; slowly squelching the amplifier. Note that
C1 becomes reverse biased with no signal. Since
the volt;:lge between Pin 4 and 2 is only one diode
drop, this is insufficient to forward bias the capacitor and no deforming occurs. Hysteresis is provided by the positive feedback to the bottom end
of the threshold control through the 33k resistor.

AI
10K

A"

zso!!

Temperature Compensating Techniques
The LM 170 AGC control circu it is designed for a
"transition width" of approximately 400 mV, to
go from full gain to practically zero output swing.
Due to this narrow control voltage width and to
the AGC control stage being biased essentially
from a three diode chain, the gain of the LM 170 is
subject to large variation with temperature. (See
data sheet for curves of Av vs Control Voltage at
different temperatures;) With approximately a 2
mV per degree C shift per diode the three diode
chain,bias voltage:can vary by 600 mV over a.6T
of1 OOo'C.Asa worst case, at a given control voltage of "2.4V at room temperature, the gain may
vary front +40 dB at ~55°C to "':'30 dB at +125°C.
This' 'necessitates the use of an external voltage
compe'nsation circuit that can stabilize gain variations Over -any; temperature range from _55° C- to
+125°C. '
Two drcuitswerefound to be quite effective';n
reduoing voltage gain drift. The first has less components but is less flexible, while the second is
slightly more difficult to adjust but gives a wide
degree of compensation over the guaranteed temperature operating range.
The ftrst circuit is shown in Figures 29A and 29B.
Figure' 29A has onlVtwo diodes and is used only
where a maximum .shift of 4 mV
in AGC controlvoltage is 'required; This will be effective at
gain level'S only slightly below maximum. From the
curves itean be -seen that at lower gai n levels, more
than·4'mVtC'of compensation is required so the
three diode chain shown in Figure 29B is used.
Adjustment is simple. Once the amount of compensation needed is found from the curves and
the correct circuit is chosen, potentiometer R1 is
adjusted to give the desired gain.

tc

Vee

Vee

~

~,

10K

10K

R1

Rt

2.SK

2.5K

-=
FIGURE 29A. Temperature
Compensating Circuitry

X

X

FIGURE 29B. Temperature
Compensating Circuitry

If a more flexible circuit is desired, the one shown
in Figure 30 can be used. Transistor T 1 biased by
R4 and 2R4 provides a maximum of 6 mVtC
thermal coefficient. Potentiometer R, shunting T"
is adjusted to provide the amount of compensation
needed. Potentiometer R2 then sets the AGC con-

FIGURE 30. Temperature Compe,,!sating Circuitry

trol voltage going to Pin 30r Pin 4 of the LM170
to give the desired gain. To, adjust 'this circuit, the
amount of thermal compensation needed is determined from the curves as before. The temperature
shift over the desired operating, .range and the
amount of g;:liri needed are also known. Therefore,
the amount of DC shift in AGe control ~6ltageis
also known by taking it st"raightfrom the Av VS
ControlVoftage curves~ Thisgiv:s the 'number of
mV per deg~ee C required. Potentiometers B,and
R2 are then set to give proper operation~ An example is shown below:
Gain Required
Operating Temperature
Range:

30 dB
-55° C to +125° C

Change in AGC Control
Voltage (from Av vs
Control Voltage Curves
in data sheet)

1.9V to 2.7V

This means

800mV'
°
1800C or 4.4mV/ C

=

800 mV

Potentiometer R1 shunts T 1 thereby 'reducing the
compensation from a maximum of 6mV/oC.The
value of R, was chosen to be approx imately 10k
ohms to prevent an unnecessary waste of current
from Vee.'
Let R,

= 10 kS1

To set for a T.C. of 4.4 mV, set Ri to 4.4/6.0 or
74% of its total value or 7400 ohms.
Now potentiometer R2 is used to set the AGC
control voltage to give a gain of 30 dB.
The relative displacement of the three temperature
curves on the Av vs Control voltage plot clearly
shows that the relation between control voltage
and temperature is not linear. Therefore, since
both of the compensating techniques described
above are approximately linear, some gain change
with temperature is to be expected. This shift is
minimized however, by either of these simple,
easily adjusted, circuits so that total variations in
gain less than ±3 dB over the' entire operating
range is possible.
Conclusion
The LM 170 is an extremely versatile system component, allowing squelch and AGC in inexpensive
communication systems. As a general purpose variable gain element, the device opens up many new

AN51':'11

areas of circuit design, in which closed loop gain
feedback may be used to control other parameters,
heretofore - never considered as convenient variables. Its compatibility with ordinary monolithic
logic creates possibilities in digital-communi~ation
system interfacing. The applications discussed in
this report should stimulate fresh thinking, in
finding new ~nd useful services for a unique variable circuit element made possible only by monolithic technology.
APPENDIX
Squelch Release Timing
The timing capacitor from Pin 6 to ground in
Figure 17 is charged by an external resistor (nominally 100 kr2), to determine the delay between
cessation of speech and turnoff of the LM 170.
Figures 31, 32 and ,33 show timings available from
5, 10 and 25 f..tF capac,itors. The upper trace is the
input, 1520 mV/cm. Notice that the input does
not have to be completely shut off, but must only
remain below the externally set squelch threshold
long enough for the timing capacitor to charge to
the gain control region. Both traces are shown at
200 ms per division.
The lower trace is the amplifier's output. At first,
since input level is below the, squelch threshold,
output is zero. An abrupt increase in input level
above the threshold causes almost immediate turnon of the amplifier. When input level is decreased
to its original value, amplifier~output follows
linearly, because gain is still at its maximum value.
A delay period follows, during which the timing
capacitor charges from the low voltage (less than
1V) previously forced by the squelch output,- Pin 6,
up to the gain control region, which begins at
about +2.1 V. The capacitor is still charging along
an exponential RC curve while it passes through
the gain control region, so that a gradual turnoff
is observed, rather than the less pleasant abrupt
turnoff of conventional squelch systems.
As an alternative to choosing different tIming
capacitor values for different release times, a single
value may be used along with a potentiometer
which would replace the lOOk charging resistor.
This would allow a front panel variable delay
control, accessible by the system user.

AN51-12

FIGURE 31. 5 p,F Capacitor Timings

,FIGUR-E 32. '10 p,F Capacitor Timings

: FIGURE :33. 25 p,F CapacitorTimings

»

z
September 1971

I

U1
to\)

-

::J:
G')

:t
(A

"'tI

HIGH 'SPEED ANALOG SWiTCHES

m
m
C

»
z
»
ro

C)
(A

~

=i

SUMMARY

("')

"

'"

.'

.

hi the past, many fac'tors cort\l;)ined it> n;H~ke
precision, high speed analog sWitchi:hg cirC:uit&iomplex and 'expensive, if not impossible.:'A~~f~~e
monolithic J-FET family opens \lew a~albgsVlfhch­
ing applications which require 'h'igh toggle'rates,
high frequency signaL handling,ability,:arid;6igh
level analog signals with br~ad dynami6'ra.n~.. ,
Galled the AM 1000, AM1 001 :andAM10d2~rla}og
switches,the'se devices vitfkedevelbp~dsp'edti:caily
for high speed analog switching applications. The
AM 1000 series overcomes the problem of slow
switching speed normallvassociCl~ed with junction
FET anarog'switCh~s;WhiieMOS'*lal'9g switc~es
are noted Jor 'their high speed,., they,':hav:e: ;~he
peculiar problernof their 'ON resistance ~b,eing
modulated by the analog signal level. TheAM1000
series elj'minatesthisproblemtoo. . .'
'
National.'s ,AM 1000 series ~a~ida9.: sWitches'~re
simple N-channel moriolithicintegrated circuit
J-FETs: They are packaged in T0-72(4:pjnTO~18)
headers to reduce circuit board' sp1lC8,and< yet
retain the. advantages of· a ,herm'eticaily seal~d
package.

WHAT 'IS AN ANALOG .SIGNAl?'
An analog signal is an electrical voltage (or
current) whose level is an analog of certain in~
formation. This information can be an electrical
level itself, a voice signal, an electrical analog
of a pressure, temperature, position, etc., or any
other data source. The analog information may
also be preconditioned by logarithm ic compression or expansion, or other desired "distortion."
If the analog information does not vary quickly
with time and if many analog signals have to
be handled in a system, the analog information
may be sampled periodically rather thah monitored
continuously. Sampled data systems can dramatically reduce cost and weight by proper utilizati'On
of available information channel bandwidth where
the cost of additional data channels becomes
expensive.

The telephone companies are probably, the most
adept at signal mUltiplexing, but other applications
are beginning to appear. Modem airc~aft are using
multiplexing to reduce weight in wire harnesses.
Any applications requiring long multiconductor
cable funs are prime targets for econom ic use of
analog signal 'multiplexing.

TIME DOMAIN MULTIPLEXING
There are two basic types of multiplexing: frequency domain mUltiplexing and time domain
multiplexing. Frequency domain multiplexing is
common in RF communications, it uses a number
of subcarriers on a data channel, each subcarrier
being modulated in some manner. An example
would be FM radio standard broadcast which has
home stereo multiplex information (a suppressed
carrier double sideband subcarrier) and the SeA
commerc'ial ."background music" multiplex information (an FM modulated subcarrier). When
the number of data channels becomes great, frequency domain multiplexing becomes difficult to
implement.
In time domain multiplexing, a certain time, slot
is allowed for sampling of a particular data line.
Thus, if you sample some analog information
during a 10 J..Ls timeslot at a 10 kHz rate, you
have time "Ieft over" to sample nine other signals
at 10 J..LS intervals at a 10kHz rate. If you can
improve the analog switch device to execute a
suitable sample in only 1 J..Ls, you have made a
tenfold improvement and you have the choice of
increasing system channel capability to 100 channels (with no change in analog signal bandwidth),
increasing analog signal frequency bandwidth by
10 times (with no increase in channels), or a compromise between increasing signal bandwidth and
increasing the number of data channels. This is
what the AM1000 family of analog switches is
all about; they allow shorter sampling times for a
given signal accuracy.

AN53-1

:t

m

en

WHAT

MAKE~

A ,GOOD ANALOG ,SWITCH?

There are five principle parameters wh ich determine how good an analog switch is:

There is at least -10V from gate to sou rce of 0 1
so it is pinched off and leakage from input to
output is in the pA range. O2 has -10V from gate
to source so it is also pinched off and its current
which shunts the input signal is in the pA range.

ON .resistance,
ON resistanc:e modulation
• OF F resistance
'Offset voltage
Commutation rate
There are other considerations which, may also be
significant ,for special cases, but, these five will
almost always have significant bearing'on a system
design. For most applications, there are two devices which are the most popular-MaS switches
and J-FET switches. Relays normally would be
a good choice but they won't toggle very fast.
In general, the MaS switches have had a speed advantage, and ease of fabrication advantage, whereas theJ-FET switches have an advarltage of lower
ON resistance, no ON resistance modulation, higher
voltage ci;lpabili'ty.4,5,6 The AM ,1 000 family of
analog switches have all of the advantages of the
J-FET plus high speed which makes it superior to
any MaS switch in a precision system.

'lOVON

'----....-.t--Q ~2~~~FF

FIGURE 2. AM1000'Circuit

FIGURE 3. AM1000 Turned ,Off

WHAT MAKES THE AM1000 FAST?'

Figure 1 shows a typical J-FET circuit used in
analog switching. Diode 0 1 allows the gate drive
signal to drive. the gate negative thus turning off
the J-FET switch. When' the 'gate' drive signal goes
positive, diode 0 1 decouples the drive from the
gate and resistor Rg discharges the gate-source
capacitance. Rg must be large so it doesn't load
the analog signal, typical vcl.lues for Rg are 100 kQ
and up; thus the gate capacitance-Rg time constant is large which precludes high switching rates.
If C iss of the J-FET is 15 pF nominal and Rg is
100 kQ,the time constant is 1.5 /J-S thus making
megacycle toggle rates impossible.

0 3 is operated at OV gate-source so it draws saturation current, loss. The bias supply for D 1 ffiust be
10V more positive than the negative drive signal.

During turri-on, the drive signal, ideally ,'makes a
step fu nction change from -20V to +10V thus
turning D2 off. The gates of 0 1 , O2 and 0 3 are
then driven positive by the saturation current of
0 3 through diode D 1 . The rate that this voJtage
slews is dependent on gate capacitance and I DSS
of 0 3 , Ciss(off) of the AM 1000 is about 10, pF so
the voltage slews at:
dv
dt

ANAlOG~
SlG,NAl'"\...
10V

Rq

.

01

.

,

s~;JH ~~:~LfL

Rl

-=
01

.

F

FIGURE 1. Typical J-FET Analog Switch

The AM 1000 consists of three J-FETs. One large
and two small ones. The large one acts as the
analog signal pass transistor. The two smaller
FETs act as a turn-on circuit which reduces
switching transients.
The pinchoff voltage of all these FETs are almost identical and are ,all less than 1 OV. In F igure 3 (ignoring diode drops), the gates of all three
FETs are at -20V and the AM 1000 is turned off.

AN53-2

Within 5V of rise (about 10 ns), O 2 begins to turn
on and 0 1 turns off. The remainder of. the gate
capacitance charge is discharged' into the- input
(or source) of 0 1 via the ON· resistance of Q:;iarid
0 3 , During this time' interval the' average series
resistance of O 2 and 0 3 is about 2kU .and the
gate capacitance ischariging' from about: 10 pF
to about 25 pF. The approximate RC time 'constant is 20 pF and 2 kQ, or 40 ns, depending on
the level of the analog signal. Total turn on time
is therefore about 50 ns. For a +10V analog
signal, the correct analysis is a little more complex,
but the AM 1000 will turn on in about 70 ns for
this circuit condition. The reason that the turn-on
transient at RL is drastically reduced ,is that the
discharge path of gate capacitance does not flow
through R L. The small transient that may appear
at R L is due to the time that 0.1 is on dl1ring
turn-on.

FIGURE 4. AM1000 Turning On

So, the AM1000 achieves its high switching speed
because its Rg (see Figure 1) is very low during
turn on, yet its Rg during the 0 FF state is in the
G ohm range and thus doesn't load the signal.

The capacitance of the AM 1OOO'is about twice that
of the MaS switch but the system load resistance
is 25 times lower thus giving the AMl 000 a toggle
rate advantage of about 12 times over the MaS
"high speed" analog switch. In orderto graphically
illustrate the superiority of the AM 1DOD, two
simple series switches were constructed; one with
the MOS switch and one with an AM 1000. The
MaS analog switch was set up to sample a +10V
DC signal, after being switched off, the output
returns to ground level. The AM 1000 was set up
to sample a portion of the turn off transient of
the MOS analog switch, each switch with a 0.5%
system accuracy! Figure 5 shows the circuit used
to obtain the oscillograph shown in Figure 6A.

TOGGLE RATE

The toggle rate (how fast the switch can be turned
on and off) of an analog switch is not a simple
straightforward parameter for a real system design.
The reason is 'that most analog switches are specified at a ridiculously low impedance level; this is
done in order to show the highest speed that the
device can possibly go; This speed is not normally
real istic for most systems designs. 1n order to
demonstrate a real istic comparison, the AM 1000
will be pitted against an MOS analog switch for a
system with a ±10V analog signal swing.

TABLE 1: AM1000 - MOS Parameter Comparison

PARAMETER

AM1000

MOS
ANALOG SWITCH

ROS(qn)

(Max)

30[2

Ros(on)

(Min)

20[2

150[2

Ros(on)

(Nom)

25[2

275[2

C isS

(Nom)

Breakdown Volts

15 pF
40V

FIGURE 5. Analog Switch Comparison Circuit

400[2

7 pF
35V

ROS(on) and Ciss indicate the basic speed capabitity
of the devices assuming low source and load
impedance, here the AM 1000 has a speed advantage
of about 5: lover the MaS switch.

The parameter that affects toggle rate the most,
however is ROS(on) variation with analog signal
level. At an analog signal of +10V, the MaS
switch has an R OS(on) of 150n and for a -10V
analog signal it has an on resistance of 400ft This
variation of ON resistance is caused by the bulk
gate to channel voltage modulating the ON resistance of the MOS switch. 5 Thus, the MOS
switch has a design on resistance characteristic of
275il ± 125n. The AM 1000 has an ROS(on) of 25n
±5il and its resistance does not vary with analog
signal level.
For a system of a given accuracy, the load impedance is determined by the variations expected in
channel resistance. Assuming a system accuracy of
±0.5%, the AM 1000 load resistance could be as
low as 1 kn; the MaS switch load resistance would
have to be 25 kil (±125il being 0.5% of 25 kill.

A National LH0033 high speed buffer was used
to sense the analog voltage at the load resistor of
the MOS switch and drive the analog input of the
AM 1000. F igu re 6A sh0ws the oscillogram; the
upper trace is the MOS switch turning off; its load
voltage heading toward ground; the lower trace
(oscilloscope vertical gain reduced slightly for
photo Clarity) shows the AM1000 sampling this
switching transient. Figure 6Bshows the timing
pulses, the upper trace being the MOS drive timing
and the lower is the AM 1000 drive timing (positive indicating off for both devices). It is interesting
to note tbat the turn-on delay or "apertu re time"
of the AM 1000 is primarily caused by the DH0034
translator. Maximum specified turn on time is
100 ns and turn off time is specified at 100 ns for
the AM 1000. F ig,ure 6 shows absolute superiority
of the AM1000 in switching ability for a given
system accuracy.
AM1000 DRIVE CIRCUITS

Normally, analog switches will be selected by some
digital control means which will usually mean OV
add +5V power, supply levers. The AM 1000 needs
a driver capable of handl ing the fu II analog voltage
swing, plus lOV; Therefor~ a Circuit known as an
analog switch translator is normally requried. There
are several types available. All of the. following
circuits feature "break before make" action which
is desirable for ~ultiplexing.

AN 53-3

+10V

+8V

:::-

+6V

C

~

....c:C

+4V

c.,)

i=

ffi

:::-

+2V

HORIZONTAL - 200 ns/DiV

FIGURE SA. AM1000 Sampling the Switching Transient of anMOS Analog Switch

OFF
MUS
ANALOG

SWITCH
ON

Off
AM1000

ON
HORIZONTAL - 200 ns/DiV

FIGURE S8. AnaJog Switch Drive Timing

Analog switch translator-drivers fall into two basic
categories. Those with pullups and. those without.
If the translator-driver has a pullup, such as the
National DM7800, then a switching diode must be
used to decouple the driver from the AM 1000
when the driver goes positive.

wh ich the AM 1000 must charge. Usually th is
additional capacitance is not excessive.

on
TTL
INPUTS

FIGUR.E 8. Translator-Driver without Pullup
on
TTL
INPUTS

FIGURE 7. Translator-Driver with Voltage Pullup

The AM1000 does not require a driver with a pullup. Figure 8 shows the circuit for this configuration. Note that the driver decoupling diode is not
required. This configuration eliminates one power
supply but adds the capacitance of the driver

AN53-4

In some systems, the cost of monolithic or hybrid
drivers is not worth the space they save. Figure 9
shows a four channel driver using low cost discrete
components. The ON channel is selected by binary
coding and. is DTL-TTL compatible. If A and B
are "high" then drive is removed from 0 5 allowing
channell AM1001 to pull up and turn on. 0 6 , 0 7
and 0 8 have drive applied which pull down on
CH2, 3 and 4 thu~ turning them off. The voltages
and devices indicated in Figure 9 allow ± 15V
analog signals .to be handled.

CURRENT

MOD~;~UCtIPLbhN~>:.::

; -. :

'

;'~I ':

:. '::;';~';':~":,',\::~+~e,10Yri:;fe:~q~~ql<~eSi$t9r shown results in 10V

diSCusS'i~ri:Of:'r11Li~tiPfexl.n'9:'cit~di~~,,~~,s'.r

;,oUhNt'.f6r,}:rl1~JjjPc,U~i::rhus

So far, the
,,;
lhescaling resistor at
been confined tos,'"ahlP,.'I'ing,:,'var,i.o,J,,',J :$"a,',n,jl.o,'~,\,\ih",',P,:,;~,t:,{.;,,!,,;;·:;~1hei:q~ut:iss~r~4~~~ fo!rTmA for 100V input, or
",
"
' " " , , , ',' :",to,'p'lVV:.::A'jQOby:',an~(og'signal would use a
voltages. Voltage,:m,q~:l:e,analog:?W.it{}nI~:g'"lil,:IPYvs,,'r·
;,":""v"l,':;".M,'",'~l :,s"ca,',I)i1,','g,",.i~,,~,is,~o,r,:,f,:, F'o,r, lower voltage signals,
maximum toggle'tates'but 'tin1ited'vohage':range' ~",:
'
','
','
,
'
"t;he,'~ori"9fthe~l\'Il0()(}WOUld have to be con(±10V for AM 10'00/ AM1'002 and' ±15V"for
,
,- , ,
,-::-1;' .~ s;ide.r'ed.f,or 'preGj'sion!,~ystems. The bound limit
AM 1 001).
."
,:
"
,:.' ' , "
~ , 'diodescornected)o' +1 OV and -'-10V prevents
If large analog vQI\fage~:nii:Js(b,e,:,:handled~:¢urr~nJ,,;<~~\,,~~:e*cessh,eVoIJage,'fro01:~ppearing at the AM 1000.
mode multiplexing:rjtus,tqe:4sed;,to,9!;1{e''f~te,!s:,::' ';'T Inputimpedaru;;e ;f:o;tl1e-current to voltage conreduced because ~ac'cllra~~!'c:LJxr~nt~\(c>Jta,ge>.C6f\i~r~""
;,:~~rtef' is' Rfdiv;iC1~d: by' Jh e, open, loop op am p ga in
ters are not as fast 'as non-inverting"voltage'ampli" (5000 'for the LH0032); the input impedance
fiers. Analog signal loading can also be a problem.
would be 2Q in Figure 10.
Nevertheless current mode multiplexing allows
OTHER APPLICATIONS
sampling of very high analog voltages. This is
accomplished byusing scaling resistors and bound
Analog computer circu its' can make good use of
limit diodes at the, input of the,ar)alog switch.
an'alog" switches. A few examples are sample and
Also, in this case the current to voltage converter
holdcircu its, reset stabilized circuits, integrator
should be the lowest impedance point in the
reset switches, and chopper stabilized amplifiers. 4
system, so the AM 1000 musf be "turned around",
so its analog "output"is used for the signal input
Video signal switching can be done with ,a miniand vice versa.
mum of switching transients. More unusual applications such as qouble sideband suppressed carrier
modulators can be constructed pl,us double sideband suppressed carrier demodulation and FM
quadrature demodulators. 5
tNP~TN~l~~~ ,o-_-JV\J.".........-......---.~--, r--~..............-i"
TOOTHER'
DATA SWITCHES

110,.,AIV

CONCLUSION
Where precision, high speed analog switching is
required, the AM 1000 series of analog switches
"rewrites the book."
FIGURE 10. Current Mode MUltiplexing

The system sensitivity in, Figure 10 is determined
by R f in the cu rrent to voltage converter op amp.
The LH0032 J-FET input opamp is selected
because of its high slew rate and low input current.

Time domain multiplexing can be dramatically
improved in channel capability and/or analog signal
bandwidth capability. Sample and hold circuits can
be improved, chopper stabilized amplifiers can be
improved and virtually any other circuit which
requires precision, high level, high speed analog
switching can be improved.

AN53-5

BIBLIOGRAPHY
1. Mrazek, Dale "High SpeedMOS Commutators"
National Semiconductor AN-2-8.

2. Wollesen, Donald L. "Analog Signal CommutatiQn" National Semiconductor AN-33.

3. Wollesen, Donald L. "Ana/og Switching - High
Speed with J-FETS" EDN t January 15; 1970.

AN 53'-6

4.

~ohen, Joel!Vf. "Sampieandi-Idld CircuifsUsing
FErAnalog iiates",EEE,'JanlJary1 971.

5. Stump" Ronald and 'Wollesen, Donald, . NMOS
Ahalag Switches" National Semiconductor
38;

Ai\J-

6. Gordon, Bernard, "Digital Sampling and Re~
co very of Analog Signals" EEE, May 1970;

March 1969

I
~

2:

C/J
-4
::0

; It

C
':)

3:

,..

",

\

m
2:

-4

l>

::::t

o

2:

l>

3:
"tJ

r-

INSTRUMENTATION AMPLIFIER

"T1
The differential input single-ended output instrumentation amplifier is one of the most versatile
signal processing amplifiers available. It is used for
precision amplification of differential dc or ac
signals while rejecting large values of common
mode noise. By using integrated circuits, a high
level of performance is obtained at minimum cost.

LM 102 is specifically designed for voltage follower
usage and has 10,000 Mr2 input impedance with
3 nA input currents. This high of an input impedance provides two benefits: it allows. the instrumentation amplifier to be used with high source
resistances and still have low error; and it allows
the source resistances to be unbalanced by over
10,000 ohms with no degradation in common
mode rejection. The followers drive a balanced differential amplifier, as shown in Figure 1, which
provides gain and rejects the common mode voltage. The gain is set by the ratio of R4 to R2 and
Rs to R 3 . With the values shown, the gain for
differential signals is 100.

Figure 1 shows a basic instrumentation amplifier
which provides a 10 volt output for 100 mV input,
while rejecting greater than ±11 V of common
mode noise. To obtain good input characteristics,
two voltage followers buffer the input signal. The

R2

.R4

1K
0.1%

100K
0.1%

>--....-

BALANCE

R3
1K
0.1%

R5
100K0.1%

FIGURE 1. Differential-Input Instrumentation Amplifier

OUTPUT

m
::0

mode rejection of 60 dB, independent of gain. In
either circuit, it is possible to trim anyone of the
resistors to obtain common mode rejection ratios
in excess of 100 dB.

Figure 2 shows an instrumentation amplifier where
the gain is I inearly adjustable from 1 to 300 with a
single resistor. An LM101A, connected as a fast
inverter, is used as an attenuator in the feedback
loop. By using an active attenuator, a very low
impedance is always presented to the feedback
resistors, and common mode rejection is unaffected by gain changes. The LM 101 A, used as
shown, has a greater bandwidth than the LM107,
and may be used in a feedback network without
instability. The gain is linearly dependent on R6
and is equal to 10-4 R6 .

For optimum performance, several items should be
considered during construction. R 1 is used for
zeroing the output: It should be a high resolution,
mechanically stable potentiometer to avoid a zero
shift from occurring with mechanical disturbances.
Since there are several ICs operating in close proximity, the power suppl ies should be bypassed with
.01 ,uF disc capacitors to insure stability. The resistors should be of the same type to have the same
temperature coefficient.

To obtain good common mode rejection ratios, it
is necessary that the ratio of R4 to R2 match the
ratio of Rs to R3 . For example, if the resistors in
circuit shown in Figure 1 had a total mismatch of
0.1 %, the common mode rejection would be 60 dB
times the closed loop gain, or 100 dB. The circuit
shown in Figure 2 would have constant common

R3
10K
0.1"

A few applications for a differential instrumentation amplifier are: differential voltage measurements, bridge outputs, strain gauge outputs, or low
level voltage measurement.

R5
10K
0.1"

v+
BALANCE

R2

10K

OJ,,

R4

10K

OJ,,

-GAIN ADJUST
Av = 10-4 R&

C1
150pF

FIGURE 2. Variable Gain, Differential-Input Instrumentation Amplifier

LB1-2

r-

m
I

March 1969

N
."

m
m
C

."

o

::D

~

l>

::D

o

n

FEEDFORWARD COMPENSATION
SPEEDS OP AMP

o

3:

"'tJ
A feedforward compensation method increases the
slew rate of the LM101A from 0.5/ps to 10V/ps as
an inverting amplifier. This extends the usefulness
of the device to frequencies an order of magnitude
higher than the standard compensation network.
With this speed improvement, Ie op amps may be
used in applications that previously required discretes. The compensation is relatively simple and
does not change the offset voltage or current of
the ampl ifier.

nals, Pin 1, as shown in Figure 2. This eliminates
the lateral PNP's from the signal path at high frequencies. Unity gain bandwidth is 10 MHz and
the slew rate is 10V/ps. The diode can be added to
improve slew with high speed input pulses.

m
2

(A

~

o
2

C2
3 pF

(A

R2
30K

"'0

m

C2 '" 6 X 10-8
R2

m

C
In order to achieve unconditional closed loop stability for all feedback connections, the gain of an
operational amplifier is rolled off at 6 dB per
octave, with the accompanying 90 degrees of
phase shift, until a gain of unity is reached. The
frequency compensation networks shape the open
loop response to cross unity gain before the amplifier phase shift exceeds 180 degrees. Unity gain for
the LM 101 A is designed to occur at 1 MHz. The
reason for this is the lateral PNP transistors used
for level shifting have poor high frequency response and exhibit excess phase shift about
1 MHz. Therefore, the stable closed loop bandwidth is limited to approximately 1 MHz.

R2
30K

Rl
30K

(A

o

>--_-VOUT

"'tJ

l>

Cl
150 pF

3:

'OPTIONAl TO IMPROVE RESPONSE
WITH FAST·RISING INPUT STEPS.

"'tJ

FIGURE 2 .. Feedforward Frequency Compensation

Figure 3 shows the open loop response in the high
and low speed configuration. Higher open loop
gain is realized with the fast compensation, as the
gain rolls off at about 6 dB per octave until a gain
of unity is reached at about 10 MHz. Figures 4
and 5 show the small signal and large signal transient response. There is a small amount of ringing;
however, the amplifier is stable over a -55°C to
+125°C temperature range. For comparison, large
signal transient response with 30 pF frequency
compensation is shown in Figure 6.

> - -....- V OUT

120

Cl
30 pF

FIGURE 1. Standard Frequency Compensation

Usually, the LM 101 A is frequency compensated
by a single 30 pF capacitor between Pins 1 and 8,
as shown in Figure 1. This gives a slew rate of
0.5V/ps. The feedforward is achieved by connecting a 150 pF capacitor between the inverting
input, Pin 2, and one of the compensation termi-

100

225

co

80

180

~

60

135

~

'"

40

90

~

:>

20

45

.

."

::I:

w

~

-20 '----'----'-----'----'--'----'----'
10 100 lk 10k lOOk 1M 10M 100M
FREUUENCY (Hz)

FIGURE 3. Open Loop Response for Both Frequency
Compensation Networks

LB2-1

by the addition of 3 pF between Pins 1 and 8. A
small capacitor C2 is needed as a lead across the
feedback resistor to insure that the rolloff is less
than 12 dB per octave at unity gain. The capacitive
reactance of C2 should equal the feedback resistance between 2 and 3 MHz. For integrator applications, the lead capacitor is isolated from the
feedback capacitor by a resistor, as shown in
Figure 8.
FIGURE 4. Small Signal Transient Response with Feedforward Compensation

Feedforward compensation offers a marked improvement over standard compensation. In addition to having higher bandwidth and slew, there is
vanishingly small gain error from DC to 3 kHz, and
less than 1% gain error up to 100 kHz as a un ity
gain inverter. The power bandwidth is also extended from 6 kHz to 250 kHz. Some applications
for this type of amplifier are: fast summing amplifier, pulse amplifier, 01 A and AID systems, and
fast integrator.
RZ
30K

FIGURE 5. large Signal Transient' Response with Feedforward Compensation
R3

loon

VOUT

Cl
150 pF

FIGURE 7. Capacitive load Isolation

Rl

FIGURE 6. large Signal Transient Response with Standard Compensation

As with all high frequency, high-gain amplifiers,
certain precautions should be taken to insure
stable operation. The power supplies should be
bypassed near the amplifier with .01 pF disc capacitors. Stray capacitance, such as large lands on
printed circuit boards, should be avoided. at Pins 1,
2, 5, and 8. Load capacitance in excess of 75 pF
should be decoupled, as shown in Figure 7; however, 500 pF of load capacitance can be tolerated
without decoupling at the expense of bandwidth

LB2-2

C3

-----I

V'N...J\jVtv-.....

Cl
150 pF

FIGURE 8. Fast Integrator

April 1969

WORST CASE POWER DISSIPATION
IN LINEAR REGULATORS

The most frequent cause of failures of voltage
regulators is excessive dissipation in the semico.nductor components. Regulators using integrated
circuits are no exception to. this. In fact, IC regulators are more prone to overdissipatio.n because
they are not generally available in power packages,
because complete integrated circuits must be operated at a lower, maximum junction temperature
than sil icon power transistors, and because the
package must be able to dissipate the quiescent
operating po.wer of the control circuitry in addition to the power in the pass transistor.
The problems and solutions presented here give
examples of the worst case calculations that
should be used in designing voltage regulators with
ICs. These questions were used in a contest spon:
sored by National Semiconductor. The entries
received clearly showed that engineers have a
marked tendency to be overly optimistic about the
dissipation capability of. the IC regulators as well
as the power ratings of the external power transistors used with them. In a surprising number of
cases the errors were of such a magnitude to cause
almost certain, premature failure of the regulator
under the conditions specified. The questions and
answers follow:
1. What is the power limited full-load current for
a 24V regulator using the LM 100 (without a
heat sink) when the worst case operating conditions are 125°C ambient and 40V input
voltage?
The maximum chip temperature of the LM 100
is 150°C, and the thermal resistance of the
TO-5 package is 150°C/W when no heat sink is
used. The permissable, junction-to-ambient
temperature rise is 25°C with a 125°C ambient,
so the maximum allowable package dissipation
is 167 mW.
The worst case quiescent current of the LM 100
is 3.0 mAo With a 40V input voltage, this produces an internal dissipation of 120 mW, even
With no load. Therefore, the device can only
dissipate another 47 mW in supplying the load
current. With 40V in and 24V out, the inputoutput voltage differential is 16V. Th is means
that 2.95 mA can be supplied through the internal pass transistor without exceeding the
ratings.

The divider resistors required on the LM 1 00
feedback to. give a 24V output are 26.6k and
2.1 k. For a 1.8Vsense voltage on the feedback
terminal, the divide(current will be 0.85 mAo
Since this current mqst be supplied by the integrated circuit, it must be subtracted from the
available lo.ad curret:1t. Hence the maximum
output current, takin,g into account worse case
conditions, is 2.1 mJf:

-

2.95 mA (MAX)

-

2.1 mA(MAX)

...---4.--------4.---

Vo = 24V

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FIGURE 1. Circuit Used in the Solution of Question 1.

2. What is the maximum allowable short-circuit
current for an LM104 regulator circuit, with a
2N2905A series pass transistor (without a heat
sink) when the worst case input is 20V at an
ambient of 85°C?
The 2N2905A, without a heat sink, can dissipate a maximum of· 0.6W at 25°C. However,
this must be derated by 3.42 mW/C for operation at higher temperatures. Since an 85°C
ambient is 60° C higher than the temperature at
which the transistors are specified, the maximum power rating must be reduced by
205 mW, to 395 mW. With a shorted o.utput,
the voltage dropped across the current limit
sense resistor is 0.5V, so the voltage across the
external pass transistor will be 19.5V for 20V
input. This means that the 395 mW maximum
dissipation rating will be exceeded for shortcircuit currents greater than 20.2 mAo
3. In the previo.us example, what is the maximum
current when the case temperature of the
2N2905A is held to 100°C?

LB3-1

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The maximum dissipation of the 2N2905A is
3W at 25°C case temperature, but this must be
derated by 17.2 mWtC for higher case temperatu res. With a 100° C case tem peratu re, the
allowable dissipation is reduced by 1.29W to
1.71W.
As in the previous example, the voltage across
the pass transistor will be 19.5V. This gives a
d i ssi pat i on-limited short-circuit current of
BBmA.

Cl
4.7 J.lF

Rl

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--vo=O

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The voltage dropped across the PNP driver will
be the 12V input output voltage differential,
less the 1V dropped across the current sense
resistor and the 1V dropped across the emitterbase junction of the 2N3772. Therefore, the
PNP driver operates with 10V across it and dissipates about 3.5W.
5. Could a 2N2905A be used in the example
above if the maximum ambient were 85°C?
Even with an infinite heat sink, the 2N2905A
can dissipate only 2W at 85°C. Therefore, it
cannot be used.

R3

.....- - - - -. . .- - - - ' _ - - Y'N

where dissipation is most significant. This
means that the base .current for a 5A load current will be 0.33A. The worst case emitter-base
voltage of the 2N3772 at- 5A will be about 1 V,
so the current through the 68Q emitter-base
resistor will be 15 mAo Hence, the PNP driver
must supply a total current of 345 rnA.

=-20V

FIGURE 2. Circuit Used in the Solution of Questions 2
and 3.

4. In the negative regulator with foldback current
limiting, what will be the worst case dissipation
in the PNP driver, 0 1 , with full load and a 24V
input voltage?
The 2N3772 is specified to have a minimum
current gain of 15 at 10A and 25°C. It would
be reasonable to assume a minimum current
gain of 15 at 5A for elevated temperatures

The answers to these questions show that the
maximum output current of a regulator can be
substantially less than might be expected from a
cursory analysis of the circuit. Detailed analysis
under worst case conditions is necessary to insure
a reliable design. These calculations are more
important than most other design calculations
because errors do not result in somewhat degraded
performance that usually shows up in checking out
the equipment. Instead, these errors cause failures
that do not always show up during checkout, but
can occur in field operation.
Additional information on the design of reliable
voltage regulators is given in application notes
AN-21 and AN-23, available from National
Semiconductor.

SA

)----+-...---~-4---VouT=-12V
R7
0.2

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Q2

2N3722

..........- - - - - - - - -. . .- -....- - - V ,N =-24V

FIGURE 3. Circuit Used in the Solution of Questions 4 and 5.

LB3-2

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FAST COMPENSATION EXTENDS
POWER BANDWIDTH

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In all Ie operational amplifiers the power bandwidth depends on the frequency compensation.
Normally, compensation for unity gain operation
is accompanied by the lowest power bandwidth. A
technique is presented which extends the power
bandwidth of the LM101A for non-inverting gains
of unity to ten, and also reduces the gain error at
moderate frequencies.
In order to achieve unconditional stability, an
operational ampl ifier is rolled off at 6 dB per·
octave, with an accompanying 90 degrees of phase
shift, until a gain of unity is reached. Unity gain·in
most monolithic operational amplifiers is limited
to 1 MHz, because the lateral PNP's used for level
shifting have poor frequency response and exhibit
excess phase shift at frequencies above 1 MHz.
Hence, for stable operation, the closed loop bandwidth must be less than 1 M Hz where the phase
shift remains below 180 degrees.
For high closed loop gains; less severe frequency
compensation is necessary to roll the open loop
gain off at 6 dB per octave until it crosses the
closed loop gain. The frequency where it crosses
must, as previously· mentioned, be less than

1 MHz. For closed loop gains between 1 and 10,
more frequency compensation must be used to
insure that the open loop gain has been rolled off
soon enough to cross the closed loop gain before
1 MHz is reached.
The power bandwidth of an operational ampl ifier
depends on the current available to charge the frequency compensation capacitors. For unity gain
operation, where the compensation capacitor is
largest, the power bandwidth of the LM 101 A is
6 kHz. Figure 1 shows an LM101A with unity gain

>----VOUT

30 pF

FIGURE 1. LM101A With Standard Frequency Com-

pensation.

LB4-1

compensation and Figure 3 shows the open loop
gain as a function of frequency.

A two-pole frequency compensation network, as
shown in Figure 2, provides more than a factor of

than the impedance of the 300 pF capacitor and
the gain rolls off at 6 dB per octave. The open
loop gain plot is shown in Figure 3. To insure sufficient drive to the 300 pF capacitor, it is connected to the output, Pin 6, rather than Pin 8.
With this frequency compensation method, the
power bandwidth is typically 15-20 kH'z as a follower, or unity gain inverter.

120

>---41-- VOUT

100

C1

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C2
30 pF

300~F

R1
10K

FIGURE 2. LM101A with Frequency Compensation to
Extend Power Bandwidth.

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FREQUENCY (Hz)

two improvement in power bandwidth and reduced gain error at moderate frequencies. The network consists of a 30 pF capacitor, which sets the
unity gain frequency at 1 MHz, along with a
300 pF capacitor and a 10k resistor. By dividing
the ac output voltage with the 10k resistor and
300 pF capacitor, there is less ac voltage across the
30 pF capacitor and less current is needed for
charging. Since the voltage division is frequency
sensitive, the open loop gain rolls off at 12 dB per
octave until a gain of 20 is reached at 50 kHz.
From 50 kHz to 1 MHz the 10k resistor is larger

LB4-2

FIGURE 3. Open Loop Response for Both Frequency
Compensation Networks.

This frequency compensation, in addition to extending the power bandwidth, provides an order of
magnitude lower gain error at frequencies from DC
to 5 kHz. Some applications where it would be
helpful to use the compensation are: differential
amplifiers, audio amplifiers, oscillators, and active
filters.

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HIGH Q NOTCH FI LTER
The twin liT" network is one of the few RC filter
networks capable of providing an infinitely deep
notch. By combining the twin liT" with an LM 102
voltage follower, the usual drawbacks of the network arf3 overcome. The 0 is raised from the usual
0.3 to something greater than 50. Further, the
voltage follower acts as a buffer, providing a low
output resistance; and the high input resistance of
the LM 102 makes it possible to use large resistance
values in the liT" so that only small capacitors are
required, even at low frequencies. The fast response of the follower allows the notch to be used
at high frequencies. Neither the depth of the notch
nor the frequency of the notch are changed when
the follower is added.

The junction of R3 and C3 , which is normally
connected to ground, is bootstrapped to the output of the follower. Because the output of the
follower is a very low impedance, neither the
depth nor the frequency of the notch change;
however, the 0 is raised in proportion to the
amount of signal fed back to R3 and C3 . Figure 2
shows the response of a normal twi n "T" and the
response with the follower added.

Figure 1 shows a twin liT" network connected to
an LM102 to form a high 0,60 Hz notch filter.

100

lK

FREQUENCY (Hz)

VOUT

Rl
10 MEG

FIGURE 2. Response of High and Low

to • Z!tll',C'

= 60 Hz
Rl = R2 = 2 R3

Cl
210 pF

C2
210 pF

FIGURE 1. High

Cl=C2=~

a Notch Filter

a Notch Filter

In appl ications where the rejected signal might
deviate slightly from the null of the notch network, it is advantageous to lower the 0 of the
network. This insures some rejection over a wider
range of input frequencies. Figure 3 shows a circuit where the 0 may be varied from 0.3 to 50. A
fraction of the output is fed back to R 3 and C3 by
a second voltage follower, and the notch 0 is
dependent on the amount of signal fed back. A
second follower is necessary to drive the twin liT"

from a low-resistance source so that the notch frequency and depth will not change with the poten-

~""-"""""4t-VOUT

to"68Hz

FIGURE 3. Adjustable Q Notch Filter

tiometer setting. Depending on the potentiometer
setting, the circuit in Figure 3 will have a response
that falls in the shaded area of Figure 2.

LB5-2

An interesting change in the high Q twin I'T"
occurs when components are not exactly matched
in ratio. For example, an increase of 1 to 10 percent in the value of C3 will raise the 0, while
degrading the depth of the notch. If the value of
C 3 is raised by 10 to 20 percent, the network provides voltage gain and acts as a tuned amplifier. A
voltage gain of 400 was obtained during testing.
Further increases in C 3 cause the circuit to oscillate, giving a clipped sine wave output.

The circuit is easy to use and only a few items
need be considered for proper operation. To minimize notch frequency shift with temperature,
silver mica, or polycarbonate, capacitors should be
used with precision resistors. Notch depth depends
on component match, therefore, 0.1 percent resistors and 1 percent capacitors are suggested to
minimize the trimming needed for a 60 dB notch.
To insure stability of the LM102, the power supplies should be bypassed near the integrated circuit
package with .01 JlF disc capacitors.

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May 1969

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FAST VOLTAGE COMPARATORS
WITH LOW INPUT CURRENT
Monolithic voltage comparators are available today
which are both fast and accurate. They can detect
the height of a pulse with a 5 mV accuracy within
40 ns. However, these devices have relatively high
input currents and low input impedances, which
reduces their accuracy and speed when operating
from high source resistances. This is probably a
basic limitation since the input transistors of the
integrated circuit must be operated at a relatively
high current to get fast operation. Further, the
circuit must be gold doped to reduce storage time,
and this limits the current gain that can be
obtained in the transistors. High gain transistors
operating at low collector currents are necessary to
get good input characteristics.
One way of overcoming this difficulty is to buffer
the input of the comparator. A voltage follower is
available which is ideally suited for this job. This
device, the LM 102*, is both fast and has a low
input current. It can reduce the effective input
current of the comparator by more than three
orders of magnitude without greatly reducing
speed.
A comparator circuit for an AfD converter which
uses this technique is shown in Figure la. An
LM 102 voltage follower buffers the output of a
ladder network and drives one input of the comparator. The analog signal is fed to the other input
of the comparator. It should come from a low
impedance source such as the output of a signal
processing amplifier, or another LM 102 buffer
amplifier.
Clamp diodes, D 1 and D 2 , are included to make
the circuit faster. These diodes clamp the output
of the ladder so that it is never more than 0.7V
different from the analog input. This reduces the
voltage excursion that the buffer must handle on
the most significant bit and keeps it from slewing.
If fast, low-capacitance diodes are used, the signal
to the comparator will stabilize approximately
200 ns after the most significant bit is switched in.
This is about the same as the stabilization time of
the ladder network alone, as its speed is limited by
stray capacitances. The diodes also limit the voltage swi ng across the inputs of the comparator,
increasing its operating speed and insuring that the
device is not damaged by excessive differential
input voltage.
The buffer reduces the loading on the ladder from
45/J.A to 20 nA, maximum, over a -55°C to
125°C temperature range. Hence, in most applications the input current of the buffer is totally
insignificant. This low current will often permit

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b. Using a Binary-Weighted Network
FIGURE 1. Comparator Circuits for Fast AID Converters

the use of larger resistances in the ladder which
simplifies design of the switches driving it.
It is possible to balance out the offset of the
LM 102 with an external 1 kSl potentiometer, R 9 .
The adjustment range of this balance contrpl is
large enough so that it can be used to nu II out the
offset of both the buffer and the comparator. A
10 kSl resistor should be installed in series with
the input to the LM 102, as shown. This is required
to make the short circuit protection of the device
effective and to insure that it will not oscillate.
This resistor should be located close to the integrated circuit.
A similar technique can be used with AfD converters employing a binary-weighted resistor network. This is shown in Figure 1b. The analog input
is fed into a scaling resistor, R 1. This resistor is
selected so that the input vol tage to the LM 102 is
zero when the output of the Df A network corresponds to the analog input voltage. Hence, if the
Df A output is too low, the output of the LM 106
will be a logical zero; and the output will change
to a logical one as the Df A output exceeds the
analog signal.
The analog signal must be obtained from a source
impedance which is low by comparison to R 1.
Th is can be either another LM 102 buffer or the
output of the signal-processing amplifier. Clamp
diodes, D 1 and D 2 , restrict the signal swing and
speed up the circuit. They also limit the input
signal seen by the LM 106 to protect if from over-

LB6-1

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loads. Operating speed can be increased even
further by using silicon backward diodes (a degenerate tunnel diode) in place of the diodes shown,
as they will clamp the signal swing to about
50 m V. The offset voltage of both the LM 102 and
the LM 106 can be balanced out, if necessary,
with R 6 •
The binary weighted network can be driven with
single pole, single-throw switches. This will result
in a change in the output resistance of the network
when it switches, but circuit performance will not
be affected because the input current of the
LM 102 is negligible. Hence, using the LM 102
greatly simplifies switch design.
Although it is possible to use a 710 as the voltage
comparator in these circuits, the LM 106 offers
several advantages. First, it can drive a fan out of
10. with standard, integrated DTL or TTL. It also
has two strobe terminals available which disable
the comparator and give a high output when either
of the terminals is held at,alogical zero. This adds
logic capability to the comparator in that it makes
it equivalent to a 710 and:8 two-input NAND gate.
If not needed, the strobe, pins can be left unconnected without affecting performance. The voltage
gain of the LM 106 is about 45,000, which is
30times higher than that of the710. The increased gain reduces the error band in making a
comparison. The LM 106 wi II also operate from the
same supply voltage as the LM 102, and other operational amplifiers, for ±12V supplies. However, it
can also be operated from ±15V supplies if a 3V
zener diode is connected in series with the positive
supply lead.
It is necessary to observe a few precautions when
working with fast circuits operating from relatively
high impedances. A good ground is necessary, and
aground plane is advisable. All the individual
points in the circuit which are to be grounded,
including bypass capacitors, should be returned
separately to the same point on the ground so that
voltages wi II not be developed across common lead
inductance. The power supply leads of the integrated circuits should also be bypassed with low
inductance 0.01 f.1F capaci,tors. These capacitors,
preferably disc ceramic, should be installed with
short leads and located close to the devices. Lastly,
the output of the comparator should be shielded
from the circuitry on the input of the buffer, as
stray coupling can also cause oscillation.
Although the circuits shown so far were designed
for use in AID converters, the same techniques
apply to a number of other applications. Figure 2
gives examples of circuits which can put stringent
input current requirements on the comparator.
The first is a comparator for signals of opposite

LB6-2

a. Comparator for Signals of Opposite Polarity

b. Zero Crossing Detector

c. Comparator for AC Coupled Signals
FIGURE 2. Applications Requiring Low Input Current
Comparators

polarity. Resistors (R 1 and R 2 ) are required to
isolate the two signal sources. Frequently, these
resistors must be relatively large so that the signal
sources are not loaded. Hence, the input current of
the comparator must be reduced to prevent inaccuracies. Another example is the zero-crossing
detector in Figure 2b. When the input signal can
exceed the common mode range of the comparator (±5V for the LM106), clamp diodes must be
used. It is then necessary to isolate the comparator
from the input with a relatively large resistance to
prevent loading. Again, bias currents should be
reduced. A third example, in Figure 2c, is a comparator with an ac coupled input. An LM 106 will
draw an input current which is twice the specified
bias current when the signal is above the comparison threshold. Yet, it draws no current when the
signal is below the threshold. This asymmetrical
current drain will charge any coupling capacitor on
the input and produce an error. Th is problem can
be eliminated by using a buffer, as the input current wi" be both low and constant.
The foregoing has shown how two integrated
circuits can be combined to provide state-of-theart performance in both speed and input current.
Equivalent results wi II probably not be achievable
in a single circuit for some time, as the technologies required are not particularly compatible.
Further, considering the low cost of monolithic
circuits, approaches like this are certainly
economical.

August 1969

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TRACKING VOLTAGE REGULATORS

Z

regulators are adjusted. The bottom resistor of the
divider, R2 , is fixed at 2K. The top of the divider,
R 1, is then calculated for the output voltage using
1.6V as the reference voltage. To help compensate
for the inaccuracies in the adjustment, output voltages are calculated slightly off from the desired
values. For the 5 and 15V regulators, R 1 is calculated to give a 2% low output voltage on the 5V
regulator and a 2% high output voltage on the 15V
regulator.
(V OUT -: 1.6V) 2000[2
Rl =
1.6V

Integrated circuit voltage regulators are available
today which are economical and offer a high
degree of performance. There are both positive
and negative regulators capable of achieving better
than 0.1% regulation under normal fluctuations in
input supply and load. Due to production variations, the internal reference voltage in these regulators may vary as much as 10% from unit to unit.
Normally, this causes no problems as most power
supply circuits have an adjustment potentiometer
which is varied to obtain the correct output voltage. I n systems wi th more than one regu lated output voltage, it is sometimes desirable to adjust all
supplies with a single potentiometer. This results
in savings by eliminating one or more potentiometers as well as eliminating the need to adjust the
supplies individually.

Rs will now adjust both regulators to within 2% of
the desired output for reference variations from
1.6V to 2.0V. From the previous calculations, a
1.6V reference yields outputs of 4.9V and 15.3V.
If the reference is 2.0V, Rs is adjusted to
324 ohms and the output voltages are 5.1 V and
14.9V. If the reference is near the typical value of
1.8V, both outputs are within 1% of nominal.

Figure 1 shows a 5V and a 15V regulator with
both outputs adjusted with a single potentiometer.
Although the technique is not exact, the error is
typically under 2%. As shown in Figure 1, the
internal reference voltages for the LM 105 * regulators, available at pin 5, are tied together. This
insures that both regulators operate with the same
reference voltage. The lower resistors of the output divider, R2 , are connected through a common
adjustment potentiometer to ground. Rs adjusts
both regulators for variations in the 1.8V reference. Note that the wiper of Rs is connected to
one side of the potentiometer. If a rheostat connection were used, the arm might open circuit
during adjustment, causing large transients on the
output.

These calculations do not account for resistor inaccuracies. If 1% resistors are used there is an
additional worst case error of 2% for each regulator. Resistor errors are inherent in any type of
tracking regulator system, even if the adjustment is
theoretically exact.
Actually, any number of regulators may be connected to a single adjustment resistor. The adjustment accuracy of this technique depends on the
output voltage differences among the regulators.
The previous example was a severe difference, and
had only 2% accuracy. With close output voltages,
such as 12V and 15V, the error is much smaller.
The 12V regulator is calculated to 1/2% low and
15V regulator 1/2% high with the 1.6V reference.
Both regulators are then within 1/2% for reference
variations of 1.6 to 2.0 volts. This adjustment
method is, of course, exact if two regulators have
the same output.

The calculations of resistor values for the output
divider resistors are made with the consideration
that the adjustment is not exact and that two
*R. J. Widlar, "The LM105-An Improved Positive Regulator," National Semiconductor Corporation, AN 23,
January, 1969.

R6

0.75

"-

VOUT + 5V
lOUT ~200 mA

VOUT + 15V
lOUT :S200 mA

R7

0.75

+ C4

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V'N
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R2'
2.0K
1%

'Solid Tantalum

FIGURE 1. Tracking Positive Regulators

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Using a negative regulator to track a positive regulator is a somewhat easier task. An inverting
operational ampl ifier may be used to provide a
negative output voltage while using a positive voltage as a reference. The LM104 t negative regulator
is easily adapted for use as an inverting amplifier
and provides several advantages over conventional
operational ampl ifiers. I t is designed to drive boost
transistors for higher output current as well as
providing a convenient method of current limiting
the output. Further, the frequency compensation
used on the. LM 104 is optimized for transient
response to line and load changes. Figure 2 shows
tracking ±15V regulators.

l----'_-VOUT = -15V
lOUT ::;200 mA

V,N::;-18V-....- - - '

'Solid Tantalum

fiGURE 2. Tracking Positive and Negative Regulators

Operation is most easily understood by referring
to the functional schematic of the LM 104 in
Figure 3. The non-inverting input of the internal
amplifier, pin 1, is connected to ground. The positive' 15V reference is connected through an internal 15K ohm input resistor, R} 6, to the inverting
input. Feedback resistor, R} 5, is also 15K ohm.
This forms a unity gain inverting amplifier with a
negative output voltage equal to the positive input
voltage. The 15K ohm resi"~tors in the LM104 are

typically matched to 1%. This means that-the out~
put of both regulators may be adjusted with 1%
accuracy by changing R1 in Figure 2.
The LM 104 may also be used with inverting gain
for negative output voltages greater than the positive reference voltage. Figure 4 shows a circuit
where the -15V supply tracks a +5V supply. In
this configuration the non-inverting input is not
grounded, but tied to divider, Rs , R 6 , between the
negative output and ground. The output voltage
equals

VOUT=V

+ [Rs + R6]
--R 6 - Rs

where V+ is the positive reference.
The line regulation and temperature drift are
determined primarily by the positive reference,
with the negative output tracking. The reference
must be a low impedance source, such as an
LM 105 regulator, to insure that current drawn by
pi n 9 of the LM 104 does not affect the reference
voltage. Since the LM 104 is connected to a positivevoltage instead of ground, it sees a total voltage equal to the sum of the unregulated negative
input and the positive reference voltage. This
reduces the maximum unregulated negative input
voltage allowable, and should be considered during
design. If the negative output voltage must be less
than. the positive reference or the decrease in maximum unregulated input voltage cannot be tolerated, an alternate method of constructing tracking regulators is given elsewhere t. Of course, many
negative regulators may be slaved to a single positive regulator.
Using standard linear integrated circuits, multiple
output positive and negative supplies may be adjusted to within 2% or less by a single resistor.
Although the absolute output is not exact, the
regulation accuracy is still within 0.1%. These
techniques can result in savings by the elimination
of both time and materials when used.

tR. J. Widlar, "Designs for Ne'g-~tive Regulators," Nation~
al Semiconductor Corporation,; AN-21, December, 1968.
9
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LM104

IL ________
L--,,---o-~""---V'N
_
FIGURE 3. Functional Diagram of the LM104 Used as
an Amplifier

LB7-2

FIGURE 4. Tracking Regulators With Different Output
Voltages

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August 1969

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PRECISION AC/DC CONVERTERS
Although semiconductor diodes available today
are close to "ideal" devices, they have severe limitations in low level applications. Silicon diodes
have a 0.6V threshold which must be overcome
before appreciable conduction occurs. By placing
the diode in the feedback loop of an operational
amplifier, the threshold voltage is divided by the
open loop gain of the amplifier. With the threshold
virtually eliminated, it is possible to rectify
millivolt signals.
Figure 1 shows the simplest configuration for eliminating diode threshold potential. If the voltage at
the non-inverting input bf'1he amplifier is positive,
~-----~"'-EOUT

FIGURE 1. Precision Diode

the output of the LM 101 A swi ngs positive. When
the amplifier output swings 0.6V positive, 0 1
becomes forward biased; and negative feedback
through 0 1 forces the inverting input to follow
the non-inverting input. Therefore, the circuit acts
as a voltage follower for positive signals. When the
input swings negative, the output swings negative
and 0 1 is cut off. With D1 cut off no current
flows in the load except the 30 nA bias current of
the LM 101 A. The conduction threshold is very
small since less than 100 J.1V change at the input
will cause the output of the L M 101 A to swi ng
from negative to positive.
A useful variation of this circuit is a precIsion
clamp, as is shown in Figure 2. In this circuit the

output is precisely clamped from going more positive than the reference voltage. When EIN is more
positive than E REF , the LM101A functions as a
summing amplifier with the feedback loop clos~d
through 0 1 • Neglecting offsets, negative feedback
keeps the summing node, and therefore the output, within 100 J.1Vof the vol~ageat the noninverting input. When EI N is about 100 J.1V more
negative than ER E F, tb.e output. swings positive,
reverse biasing 0 1 • Since! 0 1 now prevents negative
feedback from controlling the voltage. at the
inverting input, no clamping action is obtained. On
both of the circuits in Figures 1 and 2 an output
clamp diode is added at pin 8 to help speed
response. The clamp prevents the operational
amplifier from saturciiting when" 0 1 is reverse
biased.
When 0 1 is reverse biased in either circuit, a large
differential voltage maY·appear between the inputs
of the LM 101 A. This is necessary for proper operation and does no damage since the LM101A is
designed to withstand large input voltages, These
circuits will not work with amplifiers protected
with back to back diodes across the inputs. Diode
protection conducts when the differential input
voltage exceeds 0.6V and would connect the input
and· output together. Also, unprotected devices
such as' the LM709, are damaged by large differential input signals.
The circuits in Figures 1 and 2 are relatively slow.
Since there is 100% feedback for positive input
signals, it is necessary
use unity gainfrequency
compensation. Also, when 0 1 is reverse biased, the
feedback loop around the amplifier is opened and
the input stage saturates. Both of these conditions
cause errors to appear when the input frequency
exceeds 1.5 kHz. A higher performance precision
half wave rectifier is shown in Figure 3. This circuit will provide rectification with 1% accuracy at
frequencies from dc to 100 kHz. Further, it is easy
to extend the operation to full wave rectification
for precision ac/dc converters.

to

C2
3 pF
EIN

-""A"-....- - - - - -....-EOUT
01
lN914

_-.....I\~_--_-EOUT

R2
20K
01
lN914

02

lN914
02

lN914

*E R E F must have a source
impedance of less than
200n n 02 is used.

FIGURE 2. Precision Clamp

FIGURE 3. Fast Half Wave Rectifier

L88-1

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the output of A 2 is - R7 E 1N • For positive input
6
.

This precision rectifier functions somewhat differently from the circuit in Figure 1. The input signal
is applied through Rl to the summing node of an
inverting operational amplifier. When the signal is
negative, D 1 is forward biased and develops an
output signal across R 2 . As with any inverting
amplifier, the gain is R2 IR 1. When the signal goes
positive, Dl is non-conducting and there is no output. However, a negative feedback path is provided
by D 2 . The path through D2 reduces the negative
output swing to -O.7V, and prevents the amplifier from saturating.

signals, A2 sums the currents througl1 R'3 and R 6-;
and

EOUT = R7 [E~~ - E~~J .

. R7
If R3 is 1/2 R6 , the output IS R6 E 1N • Hence, the
output is always the absolute value of the input.
Filtering, or averaging, to obtain a pure dc output
is very easy to do. A capacitor, C2 , placed across
R7 rolls off the frequency response of A2 to give
an output equal to the average value of the input.
The filter time constant is R7C2 , and must be
much greater than the maximum period of the
input signal. For the values given in Figure 4, the
time constant is about 2.0 seconds. This converter
has better than 1% conversion accuracy to above
100 kHz and less than 1% ripple at 20 Hz. The
output is calibrated to read the rms value of a sine
wave input.

Since the LM 101 A is used as an inverti ng ampl ifier,
feedforward * compensation can be used. Feedforward compensation increases the slew rate to
1OV Ips and reduces the gain error at high frequencies. This compensation allows the half wave
rectifier to operate at higher frequencies than the
previous circuits with no loss in accuracy.
The addition of a second amplifier converts the
half wave rectifier to a fUll wave rectifier. As is
shown in Figure 4,the half wave rectifier is connected to inverting amplifier A 2 . A2 sums the half
wave rectified signal and the input signal to
provide a full wave output. For negative input
signals the output of Al is zero and no current
flows through R 3 . Neglect-ing for the moment C2 ,

As with any high frequency circuit some care must
be, taken during construction. Leads should be
kept short to avoid stray capacitance and power
supplies bypassed with .01 fJF disc ceramic capacitors. Capacitive loading of the fast rectifier
circuits must be less than 100 pF or decoupl ing
becomes necessary. The diodes should be reasonably fast and film type resistors used. Also, the
amplifiers must have low bias currents.

*R. C. Dobkin, "Feedforward Compensation Speeds Op
Amp," National Semiconductor Corporation, LB-2, April,
1969.

R6
20K
1%

C2
IOI'F
Rl
10K
1%

R2
20K
1%

Eour

01
lN914

02
lN914

Cl"
lO pF

FIGURE 4. Precision ACto DC Converter

LBS-2

"Fe.dforwa,d compensation
can be used to mIke a fIst
full wave ,ectifie, without
a filte,_

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August 1969

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UNIVERSAL BALANCING TECHNIQUES

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op amps are widely accepted as a universal
analog component. Although the circuit designs
may vary, most devices are functionally interchangeable. However, offset voltage balancing
remains. a personality trait of the particular amplifier design. The techniques shown h.ere allow
offset voltage balancing without regard to the
internal circuitry of the amplifier.

('")

This adjustment method is also useful when the
feedback element is .~ capacitor or non-linear
device.

+v
R3

R4

>-__-OUTPUT
R1 = 2000 R31i R4
R41iR3<10kn
RANGE

=-±V (R3~1R4)

FIGURE 1. Offset Voltage Adjustment for I nverting Amplifiers Using 10 kn Source Resistance or
Less

The circuit shown in Figure 1 is used to balance
out the offset voltage of inverting amplifiers havi ng a sou rce resistance of 10 kn or less. A small
current is injected into the summing node of the
amplifier through R 1 . Since RI is 2000 times as
large as the source resistance the voltage at the arm
of the pot is attenuated by a factor of 2000 at the
summing node. With the values given and ±15V
supplies the output may be zeroed for offset voltages up to ±7.5 mV.
If the value of the source resistance is much-larger
than 10 kQ, the resistance needed for R I becomes
too large. I n this case it is much easier to balance
out the offset by supplying a small voltage at the
non-inverting input of the amplifier. Figure 2
shows such a scheme. Resistors R I and R2 divide
the voltage at the arm of the pot to supply a
±7.5 mV adjustment range with ±15V supplies.

RANGE

= ±V

(M)

FIGURE 2. Offset Voltage Adjustment for Inverting Amplifiers Using Any Type of Feedback Element

This technique of supplying a small voltage effectively in series with the input is also used for
adjusting non-inverting amplifiers. As is shown in
Figure 3, divider R 1 , R2 reduces the voltage at the
arm of the pot to ±7.5 mV for offset adjustment.
Since R2 appears in series with R4 , R2 should be
considered when calculating the gain. If R4 is
greater than 10 kn the error due to R2 is less
than 1%.

R5

R3
50K
OUTPUT
RANGE = ±v
INPUT

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R2
100K
-v
INPUT

2

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R3

>-__-OUTPUT
R1

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GAIN=1+~

R4+ R2

FIGURE 3. Offset Voltage Adjustment for Non-Inverting
Amplifiers

LB9-1

A voltage follower may be balanced by the technique shown in Figure 4. R 1 injects a current
wh ich produces a voltage drop across R 3 to cancel
the offset voltage. The addition of the adjustment
resistors causes a gain error, increasing the gain by
0.05%. This small error usually causes no problem.
The adjustment circuit essentially causes the offset
voltage to app~ar at full output, rather than at low
output levels, where it is a large percentage error.

R2

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El

-'V\I\r_~

INPUTS

____-OUTPUT

E2-+~~---'"

R2 = RJ + R4
R2

RANGE = ±V ( : )

lOOK
GAIN

~

INPUT

__-OUTPUT

RANGE =

±v (~)

FIGURE 4. Offset Voltage Adjustment for Voltage
Followers

Differential amplifiers are somewhat more difficult
to balance. The offset adjustment used for a differential ampl ifier can degrade the common mode
rejection ratio. Figure 5 shows an adjustment circuit which has minimal effect on the common
mode rejection. The voltage at the arm of the pot
is divided by R4 and Rs to supply an offset correction of ±7.5 m V. R4 and Rs are chosen such
that the common mode rejection ratio is limited
by the ampl ifier for values of R 3 greater than

LB9-2

(~)

=~

FIGURE 5. Offset Voltage Adjustment for Differential
Amplifiers

1 kQ. If R3 is less than 1 K the shunting of R4 by Rs
must be considered when choosing the value of
R3 ·
The techniques described for balancing offset voltage at the input of the amplifier offer two main
advantages: First, they are universally applicable
to all operational amplifiers and allow device interchangeability with no modifications to the balance
circuitry. Second, they permit balancing without
interfering with the internal circuitry of the amplifier. The electrical parameters of the amplifiers
are tested and guaranteed without balancing.
Although it doesn't usually happen, balancing
could degrade performance.

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January 1970

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Ie REGULATORS SIMPLIFY
POWER SUPPLY DESIGN

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Although power supply requirements vary, IC
voltage regulators can fulfill the majority of needs.
Power supplies designed with ICs can give predictable regulation better than 0.1% with a minimum
of engineering effort. Output voltages between 0
and 40V at currents of lOA are easily ach ieved.
Further, with a minimum of changes, a single
regulator circuit can be used for a wide variety of
output voltages and currents.

-s:

(J)

To regulate negative voltages, the circuit in
Figure 2 is used. An LM104 2 contains the voltage
reference and control circuitry while an external

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'0
~

-15V

0

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A basic 200 mA positive regulator circuit is shown
in Figure 1. The LM105 1 contains the voltage
reference and control circuitry while the external

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Y,N '" -IIV -

....----4....-....

.........

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·Solidtantelum

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FIGURE 2. 200 rnA Negative Regulator

Rl
0.15

r--~~Nv""------4I""--""'~VOUT

0

15V

·Solidt.nt.lum

FIGURE 1. 200 rnA Positive Regulator

components set the output voltage, current limit
and increase power handling capacity of the IC.
The output voltage is set by R2 and R3 . A fraction
of the output voltage is compared by an error
amplifier with an internal 1.8V reference. Any
error is amplified and used to drive the 2N3740
power transistor. Since the open loop gain is large,
there is little error and a high degree of regulation.

transistor is used to increase the power handling
capacity. A reference voltage is generated by
driving a constant current, determined by R I ~
through R2 . The voltage across this resistor is fed'
into an error amplifier. The error amplifier controls the output voltage at twice the voltage across'
R2 . The output voltage is resistor programmable
with R2 and adjustable down to zero.

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Current limit in the LM 104 is similar to the
LM 105. Voltage across R3 turns on an internal
transistor that decreases drive to the output transistors. This current limit sense voltage is also
temperature dependent, decreasing from 0.65V at
25°C to 0.45V at 125°C.
Boosting the available output current from
200 mA is relatively simple. Figure 3 shows posiRJ

----_e-....... VOUT

0.1
r----4I....----4I~..,.,.....

0

15V

I4.1"F
+

Rl

Current limiting is set by R I. The voltage drop
across R I is applied to the emitter base junction of
a transistor in the IC. When the transistor is turned
on, it removes drive from the series pass transistor;
and the regulator output exhibits a constant current characteristic. Since the turn on voltage of a
transistor is temperature dependent, so is the current limit. The current limit sense voltage is about
O.4V at 25°C decreasing linearly to 0.3V at 125°C.
Therefore, the current limit resistor must be
chosen to provide adequate output current at the
maximum operating temperature.

0,

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16.1K
1%
":"

Y'N "UV .....-

. . .- - (

R2
2.JK
1%

-Solldt.ntllum

FIGURE 3a. 2APositive Regulator

tive and negative 2A regulators. An additional
power transistor increases the current handling
capability of the regulator. Adding the. boost tran-

LB10-1

',!2.

r - - - -....- -.....---~~GROUNO

l - -....-4I.... YOUT· -lOY

Ground loops are worst yet, since voltage drops
can be amplified and appear at the regulator's output. In Figure 3, voltage drops between Pin 4 of
the LM105 and the bottom of R3 are amplified by
the ratio of R2/R3 and appear at the output.

R2

UK
1%

V,N <-12Y

-Solidtlntllum

FIGURE 3b. 2A Negative Regulator

sistors increases the output current without
increasing the minimum input-output voltage
differential. The minimum differential will be 2 to
3V, depending on the drive current required from
the integrated circuit and operating temperature.
Low input-output voltage differential allows more
efficient regulation.
Although the regulators are relatively simple, some
precautions must be taken to eliminate possible
problems .. First, when the regulator is used with
boost transistors, a solid tantalum output capacitor is needed. Unlike electrolytics, solid tantalum
capacitors have low internal impedance at high
frequencies. This suppresses possible high frequency minor loop oscillations as well as providing
low output impedance at high frequency. Also, for
the LM 104, the output capacitor frequency compensates the regulator and must have good
frequency characteristics.
The power transistors recommended are singlediffused, wide-base devices. These devices have
fewer oscillation problems than double-diffused,
planar transistors. Also, they seem less prone to
failure under overload conditions. Of course, like
the power transistors in any regulator, adequate
heat sinking is necessary. The heat sink should
keep the transistor junction temperature at an
acceptable level for worst case conditions of
maximum input voltage, maximum ambient
temperature and shorted output. Byfar, the major
cause of regulator failures is inadequate heat
sinking.
Good construction techniques are also important
for regulator performance. If proper care is not
taken, ground loop errors and lead resistance drops
can easily become greater than regulator errors.
For example, 0.05" wide, 2 oz. printed circuit
conductor has a resistance of about 0.007D per
inch. For a 200 mA, 15V regulator, ten inches of
conductor would decrease the regulation by a
factor of 2.

LB10-2

When the regulator is powered from ac that is
rectified and filtered, current flowing in the filter
can sometimes cause an unusual ground loop
problem. For capacitor input filters, the peak
charging current is many times the average load
current. Even a fewmilliohms of resistance can
cause appreciable voltage drop during the peak of
the charging. When the charging current produces
a voltage drop between R3 and Pin 4 of the
LM 105, it appears as excessive ripple on the output of the regulator.
Of course, single point grounding eliminates these
problems, but this is not always possible. Usually
it is sufficient to insure that load current does not
generate a voltage drop between the ground side of
the voltage setting resistor and the ground of the
IC.
I n most cases, short circuit protection is the only
fault protection needed. However, for some regulator circuits, such as positive and negative regulators used together, additional protection is necessary. If the positive and negative supplies are
shorted together, it is possible to cause the output
voltage of one of the supplies to reverse, blowing
the IC. This is especially true if the current capabilities are different, such as a 200 mA negative
supply and a 2A positive supply. A clamp diode
between the output and ground of each supply
will prevent such polarity reversals. Also, clamp
diodes should be used to prevent input polarity
reversal and input-output voltage differential
reversal.
The use of ICs in regulator circuits can enhance
power supply performance while minimizing cost
and engineering time. Since only one IC is needed
for a wide range of outputs, the part cost, board
space and purchasing problems are less when compared to discrete designs. Also engineering time is
saved since typical and worst case performance
data, as well as application data, is available from
the manufacturer before design is begun.
REFERENCES:

1. R.J. Widlar, "An Improved Positive Regulator,"
National Semiconductor A N-23 , January,

1969.
2. R.J. Widlar, "Designs for Negative Regulators,"
National Semiconductor AN-21, October,

1968.

March 1970

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I

THE LM110-AN IMPROVED
Ie VOLTAGE FOLLOWER
There are quite a few applications where op amps
are used as voltage followers. These include sample
and hold circuits and active filters as well as
general purpose buffers for transducers or other
high-impedance signal sources. The general usefulness of such an amplifier is particularly enhanced if it is both fast and has a low input bias
current. High speed permits including the buffer in
the signal path or within a feedback loop without
significantly affecting response or stability. Low
input current prevents loading of high impedance
sources, which is the reason for using a buffer in
the first place.
The LM102, introduced in 1967, was designed
specifically as a voltage follower. Therefore, it was
possible to optimize performance so that it
worked better than general purpose Ie amplifiers
in this application. This was particularly true with
respect to obtaining low input currents along with
high-speed operation.
One secret of the LM 102' s performance is that
followers do not require level shifting. Hence,
lateral PNP's can be eliminated from the gain path.
This has been the most significant limitation on

3:
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the frequency response of general purpose
amplifiers. Secondly, it was the first Ie to use
super-gain transistors. With these devices, high
speed operation can be realized along w~th low
input currents.
The LM 11 0 is a voltage follower that has been
designed to supersede the LM 102. It is considerably more flexible in its application and offers
substantially improved performance. In particular,
the LM 11 0 has lower offset-voltage drift, input
current and noise. Further, it is faster, less prone
to oscillations and operates over a wider range of
supply voltages.
The advantages of the LM 11 0 over the LM 102 are
described by the following curves. Improvements
not included are increased output swing under
load, larger small-signal bandwidth, and elimination of oscillations with low-impedance sources.
The performance of these devices is also compared
with general-purpose op amps in Tables I and II.
The advantages of optimizing an Ie for this particu.lar slot are clearly demonstrated. LastlY,.some
typical applications for voltage followers with the
performance capability of the. LM 11 0 are given.

BALANCE

r--,,--+-~,---------~--

LM1'10

'"~

100

~
~
z

10
10k

Power bandwidth of the LMll 0 is five times larger
than the LM102.

OFFSET**
VOLTAGE
(mV)

LM110
LM102
MC1556
pA715
LM10S
LM10SA
LM101A
pA741

6.0
7.5
6.0
7.5
3.0
1.0
3.0
6.0

'"
i

1M

LMll0

5

~

-5

40
10
2.5
20
0.3
0.3
0.6
0.6

20
10
1
10
1
1
1
1

5.5
5.5
1.5
7.0
0.6
0.6
3.0
3.0

~l.L
\~

-10
-15

10M

0123456
TIME (liS)

Eliminating zeners reduces typical high frequency
noise by nearly a factor of 10. Worst case noise is
reduced even more. High frequency noise of
LM102 has cau'sed problems when it was included
inside feedback loop with other leap amps.

SLEWt
SUPPLY*
BIAS"
CURRENT RATE BANDWIDTHt CURRENT
(nA)
(MHz)
(rnA)
(Vips)
10
100
30
4000
3
3
100
1500

lOOk

VS = J;15V
TA "'25°C

1/

~
z

FREQUENCY (Hz)

FREQUENCY (Hz)

DEVICE

~j
LM102~
i

C(

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I-

M1\ L~'0J

LMll0

10

~m[llil

a:

1\

f-

DEVICE

LM310
LM302
MC1456
pA715C
LM30S
LM30SA
LM301A
pA741C

Large signal pulse response shows 40V//1S slew for
LMll0 and 10V/ps for LM102. Leading edge over·
shoot on LMll0 is virtually eliminated, so exter·
nal clamp diode frequently required on the LM102
is not needed.

OFFSET*
BIAS*
VOLTAGE CURRENT
(mV)
(nA)
7.5
15
10
7.5
7.5
0.5
7.5
6.0

7.0
30
30
1500
7.0
7.0
250
500

SLEWt
SUPPL y*
RATE BANDWIDTHt CURRENT
(MHz)
(rnA)
(Vips)
40
20
2.5
20
0.3
0.3
0.6
0.6

20
10
1
10
1
1
1
1

5.5
5.5
1.5
10
O.S
O.S
3.0
3.0

"Maximum for _55°C <:::: T A <:::: 125°C
tTypical at 25°C

'Maximum at 25°C
tTypical at 25°C

Table I. Comparing Performance of Military Grade IC
Op Amps in the Voltage-Follower Connection.

Table II. Comparison of Commercial Grade Devices.

Rl

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OUTPUT

INPur---1
fTeHon.polyethyleneo,polytJlbonlte
drelKll1cup.CltOf
·Value~

lIe 101 100 Hl cutoll Un
mtllhndpolyt,ubon.ltUplc,tors
tOllJoodttmprliluremb,hty

High Pass Active Filter

·WorstClwdnh
IHsth.n3mV'sec

Low Drift Samp'e and Hold*

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R2

1

-21'l'R1CI
~ 60H,
RI' R2'2RJ

Cl
C1

210pF

C2
21BpF

High Q Notch Filter

LB11-2

C2'g,
2

Bandpass Filter

January 1970

»
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(")

AN IC VOLTAGE COMPARATOR
FOR HIGH IMPEDANCE CIRCUITRY
The IC voltage comparators available in the past
have been designed primarily for low voltage, high
speed operation. As a result, these devices have
high input error currents, which limit their usefulness in high impedance circuitry. An IC is described here that drastically reduces these error
currents, with only a moderate decrease in speed.
This new comparator is considerably more flexible
than the older devices. Not only will it drive RTL,
DTL and TTL logic; but also it can interface with
MOS logic and FET analog switches. It operates
from standard ± 15V op amp suppl ies and can
switch 50V, 50 mA loads, making it useful as a
driver for relays, lamps or light-emitting diodes. A
unique output stage enables it to drive loads referred to either supply or ground and provide ground
isolation between the comparator inputs and the
load.

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o
voltage. The PNPs drive a standard differential
stage. The output of this stage is further amplified
by the Q s -Q 6 pair. This feeds a lateral PNP, Q9,
that provides additional gain and drives the output
stage.
The output transistor is Q 1 r which is driven by
the level shifting PNP. Current limiting is provided
by R6 and Q10 to protect the circuit from intermittent shorts. Both the output and the ground
lead are isolated from other points within the circuit, so either can be used as the output. The Vterminal can also be tied to ground to run the
circuit from a single supply. The comparator will
work in any configuration as long as the ground
terminal is at a potential somewhere between the
supply Voltages. The output terminal, however,
can go above the positive supply as long as the
breakdown voltage of Q 1 1 is not exceeded.·

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Another useful feature of the circuit is that it can
be powered from a single 5V supply and drive
DTL or TTL integrated circuits. This enables the
designer to perform linear functions on a digitalcircuit card without using extra supplies. It can,
for example, be used as a low-level photodiode
detector, a zero crossing detector for magnetic
transducers, an interface for high-level logic or a
precision multivibrator.

::I:

100

t-- LM710

LMlll

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10

3:

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LM106/

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-55°C ::;TA ::; 125°C

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FIGURE 2. Illustrating the Influence of Source Resis-

tance on Worst Case, Equivalent I nput Offset
Voltage.

:::D
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Figure 2 shows how the reduced error currents of
the LM 111 improve circuit performance. With the
LM710 or LM 1 06, the offset voltage is degraded
for source resistances above 200D. The LM 111,
however, works well with source resistances in
excess of 30 kD. Figure 2 applies for equal source
resistances on the two inputs. If they are unequal,
the degradation will become pronounced at lower
resistance levels.
Table I gives the important electrical characteristics of the LM 111 and compares them with the
specifications of older ICs.
FIGURE 1. Simplified Schematic of the LM111

Figure 1 shows a simplified schematic of this
versatile comparator. PNP transistors buffer the
differential input stage to get low input currents
without sacrificing speed. Because the emitter base
breakdown voltage of these PNPs is typically 70V,
they can also withstand a large differential input

A few, typical applications of the LM 111 are illustrated in Figure 3. The first is a zero crossing
detector driving a MOS analog switch. The ground
terminal of the IC is connected to V-; hence, with
±15V supplies, the signal swing delivered to the
gate of Q 1 is also ±15V. This type of oircuit is
useful where t~e gain or feedback configuration of

LB12-1

:::D

-<

Table I. Comparing the LM111 with earlier IC comparators. Values given are worst case over a -55°C to
125°C temperature range, except as noted.

Parameter

LM111 LM106 LM710 Units

Input Offset
Voltage

4

3

3

mV

I nput Offset
Current

0.02

7

7

f.lA

Input Bias
Current

0.15

45

45

f.lA

±14

±5

±5

V

Differential Input
Voltage Range
±30

±5

±5

V

40
40

1.7 V/mV
40
ns

Common Mode
Range

Voltage Gain t
Response Time t
Output Drive
Voltage
Current
Fan Out
(DTLlTTL)
Power
Consumption

cent lamp, ~hich is the load here, has a coldresistance eight times lower than it is during normal
operation. This produces a large inrush. current,
when it is switched on, that can damage the
switch. However, the current limiting of the
LM 111 holds this current to a safe value.

.---.---+-v·

a. Zero Crossing Detector Driving Analog Switch

.------4.-.....- .....-v·· 'v
R1

200
200

4.5K

2.R'
TO TTl

R2

50
50

24
100

8

16

80

145

2.5
1.6

V
mA

LOGIC

"

MAGNETIC
PICKUP

b. Detector for Magnetic Transducer

160

mW

tTypical at 25°C.

an op amp circuit must be changed at some precisely-determined signal level. Incidentally, it is a
simple matter to modify the circuit to work with
junction FETs.

R1
25M

c. Comparator for Low Level Photodiode
v·

The second circuit is a zero crossing detector for a
magnetic pickup such as a magnetometer or shaftposition pickoff. It delivers the output signal
directly to DTL or TTL logic cire-uits and operates
from the 5V logic supply. The resistive divider, R 1
and R2 , biases the inputs O.5V above ground,
within the common mode range of the device. An
optional offset balancing circuit, R3 and R4 , is
included.

·lnpulpol.lltYlsrevlrsedwhen
uSlAg pIA 1 as output

d. Driving Ground-Referred Load
FIGURE 3. Typical Applications of the LM111.

The next circuit shows a comparator for a lowlevel photodiode operating with MOS logic. The
output changes state when the diode current
reaches 1 pA. At the switching point, the voltage
across the photodiode is nearly zero, so its leakage
current does not cause an error. The output
switches between ground and -10V, driving the
data inputs of MOS logic directly.

The applications described above show that the
output-circuit flexibility and wide supply-voltage
range of the LM 111 opens up new fields for Ie
comparators. Further, its low error currents permit
its use in circuits with impedance levels above
1 krl. Although slower than older devices, it is
more than an order of magnitude faster than op
-amps used as comparators.

The last circuit shows how a ground-referred load
is driven from the ground terminal of the LM 111.
The input polarity is reversed because the ground
terminal is used as the output. An incandes-

The LM 111 has the same pin configuration as the
LM710 and LM106. It is interchangeable with
these devices in applications where speed is not of
prime concern.

LB12-2

November 1970

»

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»

APPLICATIONS OF THE
LM 173/LM273/LM373

-I

FM OPERATION

The LM 173 family of multi-mode IF amplifier/
detectors has been designed for AM, FM and SSB
applications in the communications market. It consists of two amplifier sections, a gain control stage,
a fully balanced FM/SSB detector, and an active
AM/SSB peak detector whose output matches the
AGe input characteristics.

Grounding the AGe input, pin 1, closes the
switch connecting the quadrature capacitor to the
quadrature network terminal pin 6. This network,
tuned to the nominal center frequency of the IF
strip gives a phase shift that varies with frequency
at pin 6 (input A of the quadrature detector) with
respect to the signal at input B. This produces a

Z

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-I

J:
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r-

s:

AGCSTAGE

lOWL£VEl
RFIN

o

OUT

...10

-.....I
W

.........

AGCINPUTI
QUAD CAPACITOR SWITCH

r-

s:N

FIXED GAIN
STAGE I"

-.....I
W

OCFEEDIACK
BYPASS

.........

r-

s:W

FMQUADRATUREoi

AMMIXERUIUAlAIICEI
SSI IFQ INPUT

-.....I
W

PEAK

QUADRATURE
DETECTOR!

DETECTOR
OUTPUT

AMf'UFIERI
HlODUCT
DETECTOR
OUTPUT

FIGURE 1. Block Diagram of LM173

To convert between modes of operation, one
simply makes the appropriate dc connections and
takes the recovered signal trom the output of the
desired detector. Two pins are involved in programming the mode of operation, pin 1 and pin 6.
Since AGe is not normally used for FM, grounding
pin 1 closes the quad capacitor switch to enable
the balanced mixer to function as an FM
quadrature detector. Since the balanced mixer is
-not required for AM, connecting a resistor from
pin 6 to ground unbalances the mixer allowing it
to pass signal. Also, this transfers the balance
sensing circuitry from the input of the balanced
mixer in FM (or SSB) mode to the input of the
AM detector. For example, FM operation is
achieved as shown in Figure 2.

pulse duration modulation of the detector output
current which is integrated by the capacitor on
pin 7. This capacitor may also be used for
de-emphasis. A considerable range .for compromise
exists in the choice of Q of the quadrature
network. Increasing the Q results in greater output
level and distortion for a given frequency deviation. Also, the parallel resonant impedance of the
network should be such that ~50 mV rms signal
appears on the quadrature phase terminal to ensure
switching action of the detector and maximum
output. An alternate higher level audio signal may
be taken from the peak detector output pin 8.
Precise dc balance of input B of the quadrature
detector is maintained -by an active dc feedback

r-------------~--------~----l

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I

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,-----1

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1
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FIGURE 2. FM IF Connection

LB13'-1

network. The dc feedback bypass pin must be
decoupled at low frequencies to ensure stability of
this loop. A 1.0,uF shunted by a .01 ,uF for good
high frequency decoupling is quite adequate. Note
that a dc path through the input or interstage filter
is not necessary (or desirable).

network to the input of the active peak detector
for optimum AM performance. Pin 6 should not
be grounded directly or excessive device current
drain may result. Lifting the AGC input from
ground opens the quad capacitor switch, as
described earlier.

AM OPERATION
In Figure 3, the LM 173 functions as an AM IF
amplifier and detector by unbalancing the balanced mixer and connecting the peak detector

An improvement in signal to noise ratio may be
obtained when interstage filtering is not used, or is
fairly broad, by connecting a parallel resonant
circuit in shunt with the signal path at pin 7.

>

,-----------------------------------------1
I
,--------1
I

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I
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I"'~~ ""I

I
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I

I

I
I

I

.~l.O-O_ _L~-.......
i~~- --.---~

,J

1

*"'

'l"K
"MAUDIO
OUTPUT

FIGURE 3. AM IF Connection

output to the AGC input through an RC network
with a suitable attack/decay time constant. Decreasing the value of Rl will increase the AGC
range of the system at the expense of recovered
output level due to the reduced dc drop across R 1 .
This voltage drop results from the AGC bias
current.

SSB OPERATION
In single sideband operation, we require both AGC
and balanced mixer functions and therefore we do
not ground pin 1 or pin 6. By injecting 25 mV rms
or greater BFO signal into balanced mixer input A
at pin 6, the mixer acts as a product detector, and
we obtain our recovered audio at pin 7. The peak
detector may then be used to generate an audio
derived AGC voltage as shown in Figure 4. The
connection of a manual gain control for CW operation is also illustrated.

The balanced mixer is disabled by applying an
offset voltage to input A with resistor R2 to
ground. Th is also transfers the active dc balance

,----I

-

--- --- -

-

---

I-----l

-

-

---------,
I

I '

I

I

I

I

I

I

I

I

_L.-.-P_P_'
i

1

.~i~Oo--

~:F"

_"UAl
GAIN
COJITROL

FIGURE 4. SSB and CW IF Connection

LB13-2

SSI"UDIO
OUT

November 1970

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C

c:

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-t

SPEED UP THE LM108 WITH
FEEDFORWARD COMPENSATION
Feedforward frequency compensation of operational amplifiers can provide a significant increase
in slew rate and bandwidth over standard lag compensation. When feedforward compensation is
applied to the LM 101 A operational ampl ifier,l an
order of magnitude increase in bandwidth results.
A simple feedforward network has also been developed for use with the LM 108 micropower amplifier to give a factor of five improvement in speed.
It uses no active components and does not degrade
the excellent dc characteristics of the LM 108.

When the LM108 is used with feedforward compensation, it is less tolerant of capacitive loading
and stray capacitance. Precautions must be taken

100

'"

.....

OUTPUT

I

I .........

"

80

z

~

60

c.:>

40

>

20

~

I

I

I'-

=i

COMPENSAT~

'r1-f-~

'...

"

.,

~j=

"-

,

- f - - STANOARO

135

:z:

90

~
~
.f

11', ~ 5 ~;05 pF

FIGURE 3. Oecoupling Load Capacitance

As with any externally compensated amplifier,
increasing the compensation of the LM108 increases the stability at the expense of slew and
bandwidth. The circuit shown is for the fastest
response. I ncreasing the size of C2 to 20 or 30 pF

LB14-1

C

o

o

3:

"'0

m
2

fJ)

-o~
2

will provide .2 or 3 times greater stability and
capacitive load tolerance. Therefore, the size of
the compensation capacitor should be optimized
for the bandwidth of the particular application.
The stability of the LM1 08 with feedforward compensation is indicated by the small signal transient
responses shown in Figure 4. It is quite stable since
there is I ittle overshoot and ringing even though
the amplifier is loaded with a 50 pF capacitor.
Large. signal transient response for a 20V square
wave is shown in Figure 5. The small positive overshoot is not severe and usually causes no problems.
FIGURE 5. Large Signal Transient Response of LM108
with Feedforward Compensation

ever, it is still wise to bypass the supplies for drill
since noise on the V+ line can be injected to the
summing junction by the 500 pF feedforward
capacitor.

FIGURE 4. Small Signal Transient Response of LM108
with Feedforward Compensation

The LM 108 is unusually insensitive to power supply bypassing with the new compensation. Even
with several feet of wi re between the device and
power supply, it does not become unstable. How-

The new feedforward compensation is easy to use
and offers a factor of five improvement over standard compensation. Slew rate is increased to
1.3V lJ.1s and power bandwidth extended to
20 kHz. Also, gain error at high frequencies is
reduced. This makes the LM 108 more useful in
precision applications where low dc error as well as
low ac error is desired.

REFERENCE:
1. Robert C. Dobkin, "Feedforward Compensation Speeds Op Amp," National Semiconductor
LB-2, March, 1969.

~----------------------------------------~---------------------------------'.r-

l:XJ
I

January 1971

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(J'I

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(J)

HIGH STABI LlTY REGULATORS

-I

Monolithic IC's have greatly simplified the design
of general purpose power supplies. With an IC
regulator and a few external components 0.1 %
regulation with 1% stability can be obtained. However, if the application requires better performance, it is advisable to use some other design
approach.

The negative regulator shown in Figure 2 operates
similarly, except that discrete transistors are used
for the pass element. A transistor, Ql, level shifts
the output of the LM 108 to drive output transistors, Q 3 and 0 4 .. Current limiting is provided by
Q2. Capacitors C3 and C4 frequency compensate
the regulator.

Precision regulators can be built using an IC op
amp as the control ampl ifier and a discrete zener
as a reference, where the performance is determined by the reference. Figures 1 and 2 show
schematics of simple positive and negative regulators. They are capable of providing better than
0.01 % regulation for worst case changes of line,
load and temperature. Typically, the line rejection
is 120 dB to 1 kHz; and the load regulation is
better than 10 J1V for a 1A change. Temperature is
the worst source of error; however, it is possible to
achieve less than a 0.01 % change in the output
voltage over a -55°C to +125°C range.

In the positive regulator the use of an LM 109
instead <;>f discrete power transistors has several
advantages. First, the LM 109 contains all the biasing and current limit circuitry needed to supply a
1A load. This simplifies the regulator. Second, and
probably most important, the LM 109 has thermal
overload protection, making the regulator virtually
burn-out proof. If the power dissipation becomes
excessive or if there is inadequate heat sinking, the
LM 109 will turn off when the chip temperature
reaches 175°C, preventing the device from being
destroyed. Since no such device is available for use
in the negative regulator, the heat sink should be
large enough to keep the junction temperature of
the pass transistors at an acceptable level for worst
case conditions of maximum ambient temperature,
maximum input voltage and shorted output.

YOUT = lOY
lOUT

tDetermineszenercurrent.
May be adjusted to
minimize therm3l1 drift.

:S;lA

":'"

,Solid tantalum

FIGURE 1. High Stability Positive Regulator

The operation of both regulators is straightforward. An internal voltage reference is provided
by a high-stability zener diode. The LM108A 1
operational ampl ifier compares a fraction of the
output voltage with reference. I n the positive regulator, the output of the op amp controls the
ground terminal of an LM109 2 regulator through
source follower, 0 1 • Frequency compensation for
the regulator is provided by both the R 1 C2 combination and output capacitor, C 3 •

Although the regulators are relatively simple, some
precautions must be taken to eliminate possible
problems. A solid tantalum output capacitor must
be used. Unlike electrolytics, solid tantalum capacitors have low internal impedance at high frequencies. Low impedance is needed both for
frequency compensation and to eliminate possible
minor loop oscillations. The power transistor
recommended for the negative regulator is a
single-diffused wide-base device. This transistor
type has fewer oscillation problems than double
diffused transistors. Also, it seems less prone to
failure under overload conditions.
Some unusual problems are encountered in the
construction of a high stability regulator. Component choice is most important since the resistors, ampl ifier and zener can contribute to
temperature drift. Also, good circuit layout is
needed to eliminate the effect of lead drops,
pickup, and thermal gradients.
The resistors must be low-temperature-coefficient
wirewound or precision metal film. Ordinary 1%
carbon film, tin oxide or metal film units are not
suitable since they may drift as much as 0.5% over
temperature. The resistor accuracy need not be
0.005% as shown in the schematic; however, they
should track better than 1 ppm(C. Additionally,
wirewound resistors usually have lower thermoelectric effects than film types. The resistor driving
LB15-1

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R2
1.SK

tOetermines zener
current. MaV be
adjusted to minimize
thermal drift.

tSolid tantalum

2.2,.,F

--e---4I.-..-----_e-__...

INPUT-. . .

FIGURE 2. High Stability Negative Regulator

the zener is not quite as critical; but it should
change less than 0.2% over temperature.
The excellent dc character istics of the LM 108A
make it a good choice as the control amplifier. The
conoffset voltage drift of less than 5 J1.V
tributes I ittle error to the regulator output. Low
input current allows standard cells to be used for
the voltage reference instead of a reference diode.
Also the LM 108 is easily frequency compensated
for regulator applications.

tc

Of course, the most important item is the reference. The I N829 diode is representative of the
better zeners available. However, it still has a
temperature coefficient of 0.0005%tC or a maximum drift of 0.05% over a -55°C to 125°C
temperature range. The drift of the zener is usually
linear With temperature and may be varied by
changing the operating current from its nominal
value of 7.5 mAo The temperature coefficient
changes by about 50 J1.V
for a 15% change in
operating current. Therefore, by adjusting the
zener current, the temperature drift of the
regulator may be minimized.

tc

LB15-2

Good construction techniques are important. It is
necessary to use remote sensing at the load, as is
shown on the schematics. Even an inch of wire will
degrade the load regulation. The voltage setting
resistors, zener, and the amplifier should also be
shielded. Board leakages or stray capacitance can
easily introduce 100 J1.V of ripple or dc error into
the regulator. Generally, short wire length and
single-point grounding are helpful in obtaining
proper operation.

REFERENCES:

1. R.J. Widlar, "IC Op Amp Beats FETs on Input
Current," National Semiconductor AN-29,
December, 1969.
2. R.J. Widlar, "New Developments in IC Voltage
Regulators," in 1970 International Solid-State
Circuits Conference Digest of Technical Papers,
Vol. XIII, pp. 158-159.

March 1971

m

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(J)

!(
-4

c:

EASILY TUNED
SINE WAVE OSCILLATORS
amplitude of the square wave fed back to the filter
input. Starting is insured by R6 and C5 which provide dc negative feedback around the comparator.
This keeps the comparator in the active region.

One approach to generating sine waves is to filter a
square wave. This leaves only the sine wave fundamental as the output. Since a square wave is easily
amplitude stabilized by clipping, the sine wave
output is also amplitude stabilized. A clipping oscillator eliminates the problems encountered with
agc stablized oscillators such as those using Wein
bridges. Additionally, since there is no slow agc
loop, the oscillator starts quickly and reaches final
amplitude within a few cycles.

If a lower distortion oscillator is needed, the circuit in Figure 2 can be used. Instead of driving the
tuned .circuit with a square wave, a symmetrically
clipped sine wave is used. The clipped sine wave,
of course, has less distortion than a square wave
and yields a low distortion output when filtered.

Rl

l>

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m
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en
n

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lK

:D

01
7V

C4
.OlpF

R6

10M

(J)

t Cl = C2
I Frequency Adjust
• Amplitude Adjust
Fo,,_I_
2" Cl "jR3 Rl

FIGURE 1. Easily Tuned Sine Wave Oscillator

An operational amplifier is used as a tuned circuit,
driven by square wave from a voltage comparator.
Frequency is controlled by R" R2 , C" C2 , and
R3 , with R3 used for tuning. Tuning the filter
does not affect its gain or bandwidth so the output
amplitude does not change with frequency. A
comparator is fed with the sine wave output to
obtain a square wave. The square wave is then fed
back to the input of the tuned circuit to cause
oscillation. Zener diode, 0" stabilizes the

~

-4

+15,..----.-e---, R8'

The circuit in Figure 1 will provide both a sine and
square wave output for frequencies from below 20
Hz to above 20 kHz. The frequency of oscillation is
easily tuned by varying a single resistor. This is a
considerable advantage over Wein bridge circuits
where two elements must be tuned simultaneously
to change frequency. Also, the output amplitude is
relatively stable when the frequency is changed.

Z
m

l>

C2 t

C3
150pF

(J)

rr-

R2
50K

330K

Z
m
C

This circuit is not as tolerant of component values
as the one shown in Figure 1. To insure oscill.ation,
it is necessary that sufficient signal is applied to
the zeners for clipping to occur. Clipping about
20% of the sine wave is usually a good value. The
level of clipping must be high enough to insure
oscillation over the entire tuning range. If the clipping is too small, it is possible for the circuit to
cease oscillation due to tuning, component aging,
or temperature changes. Higher clipping levels increase distortion. As with the circuit in Figure 1,
this circuit is self-starting.
Table 1 shows the component values for the
various frequency ranges. Distortion from the circuit in Figure 1 ranges between 0.75% and 2%
depending on the setting of R3 . Although greater
tuning range can be accomplished by increasing
the size of R3 beyond 1kn, distortion becomes

LB16-1

C5
5pF

R5

10K

R2*
200K

Rl
330K
R6
10K

R4
50

t Cl
j

= C2
FrequencyAd,u Sl

*. Clipping Level Adjust

Fo=~
2" Cl VRJ RI

FIGURE 2. Low Distortion Sine Wave Oscillator

excessive. Decreasing R3 lower than 50n can
make the filter oscillate by itself. The circuit in
Figure 2 varies between 0.2% and" 0.4% distortion
for 20% clipping.
About 20 kHz is the highest usable frequency for
these. oscillators. At higher frequencies the tuned
circuit is incapable of providing the high.o bandpass characteristic needed to filter theinput into a
clean sine wave. The low frequency end of oSo
cillation is not limited except by capacitor size.
TABLE 1

C1 , C2

MIN.
FREQUENCY

MAX.
FREQUENCY

0.47 J.1F
0.1 J.1F
.022 J.1F
.0047 J.1F
.002J.1F

18 Hz
80 Hz
380 Hz
1.7 kHz
4.4 kHz

80 Hz
380 Hz
1.7 kHz
8 kHz
20 kHz

In both oscillators, feed forward compensation 3 is
used on the LM1 01 A amplifiers to increase their
bandwidth. Feedforward increases the bandwidth
to over 10 MHz and the slew rate to better than
1 OV /J.1s. With standard compensation the
maximum output frequency would be limited to
about 6 kHz.
Although these oscillators
tricky, good construction
portant. Since the amplifiers
are both wide band devices,

LB16-2

are not particularly
techniques are imand the comparators
proper power supply

bypassing is in order. Both the positive and
negative supplies should be bypassed with a 0.1J.1F
disc ceramic capacitor. The fast transition at the
output of the comparator can be coupled to the
sine wave output by stray capacitance, causing
spikes on the output. Therefore the output of the
comparator with the associated circuitry shou.ld be
shielded from the inputs of the op amp.
Component choice is also important. Good quality
resistors and capacitors must be used to insure
temperature stability. Capacitor should be mylar,
polycarbonate, or polystyrene - electrolytics will
not work. One percent resistors are usually
adequate.
The circuits shown provide an easy method of
generating a sine wave. The frequency of oscillation can be varied over greater than a 4 to 1
range by changing a single resistor. The ease of
tuning as well as the elimination of critical agc
loops make these oscillators well suited for high
volume production since no component selection
is necessary.
References:
1. N.P. Doyle, "Swift, Sure Design of Active
Bandpass Filters," EDN, Vol. 15, No.2, January
15,1970.
2. R.J. Widlar, "Precision IC Comparator Runs
from 5V Logic Supply," National Semiconductor AN-41, October, 1970.
3. Robert C. Dobkin, Feedforward Compensation
Speeds Op Amp," National Semiconductor
. L8-2, March, 1969.
II

September 1971

LMl18 OP AMP SLEWS 70 V//lS
One of the greatest limitations of today's monolithic op amps is speed. With unity gain frequency
compensation, general purpose op amps have
1 MHz bandwidth and 0.3 V /Ils slew rate. Optimized compensation as well as feedforward compensation can improve op amp speed for some
appl ications. Specialized devices such as fast, unitygain buffers are available which provide partial
solutions. This paper will describe a new high
speed monolithic amplifier that offers an order
of magnitude increase in speed with no loss in
flexibility over general purpose devices.

Figure 1 shows a simplified schematic of the
LM 118. Transistors 0 1 and O2 are a conventional
differential input stage with emitter degeneration
and resistive collector loads. 0 3 and 0 4 form the
second stage which further amplify the signal and
level shift the signal towards V-. The collectors of
0 3 and 0 4 drive a current inverter, 0 10 and 0 11
to convert from differential to single ended. 0 9 ,
which has a current source load for high gain,
drives a class B output. The collectors of the input
stage and the base of 0 9 are available for offset
balancing and external compensation.

The LM 118 is constructed by the standard six
mask monolithic process and features 15 MHz
bandwidth and 70 V /Ils slew rate. It operates over
a ±5 to ± 18V su pply range with Iittle change in
speed. Additionally, the device has internal unitygain frequency compensation and needs no external components for operation. However, unlike
other internally compensated amplifiers, external
feedforward compensation may be added to approximately doubl.e the bandwidth and slew rate.

Frequency compensation is accomplished with
three internal capacitors. C 1 rolls off on half the
differential input stage so that the. high frequency
signal path is single-ended. Also, at high frequencies, the signal is fed forward around the
lateral PNP transistors by a 30 pF capacitor, C 2 .
This eliminates the excessive phase shift. Overall
frequency response is then 'set by capacitor, C3 ,
which rolls off the amplifier at 6 dB/octive. As
previously mentioned feedforward compensation'
for inverting applications can be applied to the
base of 0 9 . Figure 2 shows the open loop frequ ency response of an' LM 118. Table 1 gives
typical specifications for the new amplifier.

DESIGN CONCEPTS

In general purpose amplifiers the unity-gain bandwidth i's limited by the lateral PNP transistors used
for level shifting. The response above 2 MHz is so
poor that they cannot be used in a feedback
amplifier. If the PNP transistors are used for level
shifting only at DC or low frequencies and the
signal is fed forward around the PNP transistors at
high frequencies, wide bandwidth can be obtained
without the excessive phase shift of the PNP
transistors.

_-....- ...---......-_--_--411.....-7·

120
100
CD

80

~

60

~

40

5

20

;=
>

-

"-

~

"

~

I"-

"""

-20
10

100

lk

"

"

10k lOOk 1M 10M 100M

FREQUENCY (Hz)

FIGURE 2. Open Loop Voltage Gain as a Function of
Frequency for LM118.

T ABL E 1. Typical Specifications for the LM 118

FIGURE 1. Simplified Circuit of the LM118

Input Offset Voltage
Input Bias Current
Offset Current
Voltage Gain
Common Mode Range
Output Voltage Swing
Small Signal Bandwidth
Slew Rate

2mV
200 nA
20 nA
200K
±11.5V
±13V
15 MHz
70 V/Ils

LB17-1

OPERATING CONFIGURATION
Although considerable effort was taken to make
the LM 118 trouble free, bigh frequency amplifiers are more prone to oscillations than low
frequency devices such as the LM101A. Care must
be taken to minimize the stray capacitance at the
inverting input and at the output; however the
LMl18 will drive a 100 pF load. Good power
supply bypassing is also in order-O.l J-lF disc
ceramic capacitors should be used within a few
. inches of the amplifier. Additionally, a small
. capacitor is usually necessary across the feedback
resistor to compensate for unavoidable stray
capacitance.
Figure 3 shows feed forward compensation of the
LM 118 for fast inverting appl ications. The signal
is fed from the summing junction to the output
stage driver by C 1 and R4 . Resistors R5, R6 and
R7 have two purposes: they increase the internal
operating current of the output stage to increase
slew rate and they provide offset balancing. The
current boost is necessary to drive internal stray
capacitance at the higher slew rate. Mismatch of
the external resistors can cause large voltage offsets
.so offset balancing is necessary. For supply voltages other than ±15V, R5 and R6 should be
selecteo to draw about 500 J-lA from Pins 1 and 5.
R2
5K

At high gains, or with high value feedback resistors
R4 can be quite low-but not less than 100[2When the LM 118 is used a fast integrator, with
a large feedback capacitor or with low values
of feedback resistance, R4 must be increased to
8 kS1 to insu re stabi Iity over a fu II _55° C to
125°C temperature range.
One of the more important considerations for a'
high speed amplifier is settling time. Poor settling
time can cancel the advantages of having high slew
rate and bandwidth. For example-an amplifier can
have severe ringing after a step input. A relatively
long time is then needed before the output voltage can be read accurately. Settling time is the
time necessary for the output to slew through a
defined voltage change and settle to within a defined error of its final output voltage. Figure 4
shows optimized compensation for settling to
R2
5K

Rl
5K

tSlew and settling time to 0.1%
for a 10V step change is 800 ns.

C2
0.01 ~F

Rl
5K

FIGURE 4. Compensation for Minimum Settling t Time

tSlew rate typically 120V/~s.

FIGURE 3. Feedforward Compensation for Greater
Inverting Slew Rate t

When using feedforward, resistor R4 should be
optimized for the application. It is necessary to
have about 8 kS1 in the path from the output of
the amplifier through the feedback resistor and
through feedforward network to Pin 8 of the
device. The series resistance is needed to limit the
,bandwidth and prevent minor loop oscillation.

within 0.1% error.. Typically the settling time is
800 ns for a simple inverter circuit as shown.
Settling time is, of course, subject to operating
conditions external to the IC such as closed loop
gain, circuit layout, stray capacitance and source
resistance. An optional offset balancing circuit,
R3 and R4 is included.
The LM118 opens up new fields for IC operational
amplifiers. It is more than an order of magnitude
faster than general purpose amplifiers while retaining the ease of use features. It is ideally suited for
analog to digital converters, active filters, sample
and hold circuits and wide band amplification.
Further, the LM 118 has the same pin configuration
as the LM 101 A or LM741 and is interchangeable
with these devices when speed is of prime concern.

National does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied; and National reserves the right, at any time without notice, to change said circuitry.

ACKNOWLEDGEMENTS
The following engineers have contributed to the authorship of the applications
information in this handbook: R.C. Dobkin, T. Hanna, R. Hirschfeld, T.B. Mills,
W.B. Mitchell, D. Mrazek, W.S. Routh, B. Siegel, T. Smathers. R. Stump,
L. VanDerGaag,R. J. Widlar, C. M. Wittmer, D. L. Wollesen, M. Yamatake.
Editing: 'Marvin VanderKooi.



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