1972_National_MOS_Integrated_Circuits 1972 National MOS Integrated Circuits
User Manual: 1972_National_MOS_Integrated_Circuits
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MOS
INTEGRATED
. CIRCUITS
February 1972
II N
,National Semiconductor Corporation
_____
2900 Semiconductor Drive, Santa Clara, California 95051
(408) 732-5000/ TWX (910) 339-9240
Introduction
Here is National's newest handbook on MOS products. Extra copies of this handbook,
~plus those on our other major product lines - digital, linear and transistors - are also
available. To receive our handbooks, contact a National sales office, representative or
distributor; to keep current on our growing product lines ask to be placed on our
mailing list.
Table of Contents
MOS Selection Guide
.......................................................
vi
MAPS (Microprogrammable Arithmetic Processor System) . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . .
MM5704AA MOS/LSI Keyboard Interface Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
Dynamic Shift Registers
MM400/MM5'00 Dual 25·Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM401/MM501 Dual 25-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM402/MM502 Dual 50-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM403/MM503 Dual 50-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM406/MM506 Dual 100-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM407/MM507 Dual 100-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1402A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM1403A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
MM1404A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4001A/MM5001 A Dual 64-Bit Dynamic Shift Register ......... o. • . • • . . . . . • . • . . . . . . . ..
MM4006A/MM5006A Dual 100-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4007/MM5007 Dual 100-Bit Programmable Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4010A/MM5010A Dual 64-Bit Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4012/MM5012 Dual 256-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4013/MM5013 1024-Bit Dynamic Shift Register/Accumulator . . . . . . . . . . . . . . . . . . . . . . . . .
MM4015A/M M5015A Triple 60 + 4-Bit Accumulator/Register . . . . . . . . . . . . . . .. . . . . . . . . . . ..
MM4016/MM5016 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4017/MM5017 Dual 512-Bit Dynamic Shift Register. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
MM4018/MM5018 Triple 64-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4019/MM5019 Dual 256-Bit Mask Programmable Shift Register. . . . . . . . . . . . . . . . . . . . . . . ..
MM4020/MM5020 Quad 80-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4021/MM5021 Triple 80-Bit Dynamic Shift Register. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ..
MM5024A 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5081 10-Bit Serial I n-Parallel Out Lamp Driver/Register.. . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4104/MM5104 MUlti-Length Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4105/MM5105 Quad 64-Bit Dynamic Shift Register/Accumulator. . . . . . . . . . . . . . . . . . . . . ..
9
9
9
9
9
9
12
12
12
15
18
18
15
21
25
28
31
34
37
18
40
40
12
43
45
48
Static Sh ift Registers
MM404/MM504 Dual 16-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
MM405/M M505 Dual 32-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4040/MM5040 Dual 16-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . .
MM4050A/MM5050A Dual 32-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . .
MM4051 A/MM5051 A Dual 32-Bit Static Shift Register-Split Clock. . . . . . . . . . . . . . .
MM4052/MM5052 Dual 80-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . .
MM4053/MM5053 Dual 100-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . .
MM5054 Dual 64/72/80-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
54
57
57
60
60
63
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..
..
..
..
','
..
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ROMs
MM3501 1024-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBA
MM4203/MM5203 2048-Bit Electrically Programmable Static Read-Only Memory (pROM) . . . . . . ... 67
MM4210/MM5210 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71
MM4211/MM5211 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 75
MM4213/MM5213 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBA
MM4220/MM5220 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 79
MM4221/MM5221 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83
MM4230/MM5230 2048-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 87
MM4231/MM5231 2048-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 91
MM4232/MM5232 4096-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95
MM4240/MM5240 2560-Bit Static Character Generator/Read-Only Memory. . . . . . . . . . . . . . . . . .. 99
MM4241/MM5241 3072-Bit Static Character Generator/Read-Only Memory. . . . . . . . . . . . . . . . . .. 103
iii
RAMs
MM 1101 256-Bit Fully Decoded Static Random-Access Memory . . . . . . . . . . . . :. . . . . . . . . . . . . ..
MM11011 256-Bit Fully Decoded Static Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MM1101A 256-Bit Fully Decoded Static Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1101A1 256-Bit Fully Decoded Static Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MM1101A2 256-Bit Fully Decoded Static Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MM 11 03 1024-Bit Fully Decoded Dynamic Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . .
MM5260 1024-Bit FlJlly Decoded Dynamic Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . .
MM5262 2048-Bit Fully Decoded Dynamic Random-Access Memory . . . . . . . . . . . . . . . . . . . . . . .
107
107
107
107
107
111
114
TBA
Clock Drivers
MH0007/MH0007C Single Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0009/MH0009C Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0012/MH0012C High Speed MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0013/MH0013C Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0025/MH0025C Two Phase MaS Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0026/MH0026C 5 MHz Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0027C Dual High Speed MOS Interface Driver
117
119
121
123
127
130
138
Analog Switches
MM450/MM550 Dual Differential Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451/MM551 Four-Channel Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM452/MM552 Four MaS Transistor Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM454/MM554 Four-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM455/MM555 Three MaS Transistor Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0120 Series High Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH0130 Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0140 Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0150 Medium Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0160 Medium Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH2114/AH2114C DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1000 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . .
AM1001 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1002 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . .
AM3705/AM3705C 8-Channel MaS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NH0014/NH0014C DTL/TTL Compatible DPDT Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .
NH0015/NH0015C Quad Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NH0019/NH0019C (MH453/MH533) DTL/TTL Compatible Dual DPST Analog Switch . . . . . . . . . . .
141
141
141
145
141
148
148
148
148
148
155
157
157
157
159
163
TBA
163
Logic Elements
MM480/MM580
MM481/MM581
MM482/MM582
MM483/MM583
Dual 3-lnput NOR Gate
Dual Exclusive OR Gate
Dual Digital Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
JK Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
167
167
167
ROM Character Generators
MM4220NP/MM5220NP 7x9 Horizontal Scan Display Character Generator . . . . . . . . . . . . . . . . . .. 173
MM4230NN/MM5230NN 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . .. 173
MM4230NO/MM5230NO 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . .. 173
MM4240AA/MM5240AA 7x5 Horizontal Scan ASCII-7 Character Generator. . . . . . . . . . . . . . .. 99,267
MM4240AE/MM5240AE ASCII-7 and. Lower Case Character Generator . . . . . . . . . . . . . . . . . . . . . 267
MM4240ABU/MM5240ABU Hollerith Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 175, 267
MM4240ABZ/MM5240ABZ EBCDIC-8 Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 177,267
MM4240ACA/MM5240ACA EBCDIC Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178,267
MM4241ABL/MM5241ABL Vertical Scan ASCII-7 Character Generator . . . . . . . . . . . . . . . . . . . . . 267
MM4241ABV /MM5241ABV Vertical Scan ECMA-7 (Scandinavian) Character Generator . . . . . . . . . . . 267
MM4241ABW/MM5241ABW Vertical Scan ECMA-7 (German) Character Generator • . . . . . . . . . . . . 267
MM4241ABX/MM5241ABX Vertical Scan ECMA-7 (French, British, Italian) Character Generator. . .. 267
MM4241ABY /MM5241ABY Vertical Scan ECMA-7 (Spanish) Character Generator . . . . . . . . . . . . . . 267
iv
For information on the following character generators contact National,Santa Clara:
MM4240AD/MM5240AD Katakana Alphabet Character Generator
MM4240AF/MM5240AF 5x7 ASCII-6 with Low True Outputs Character Generator
MM4240AH/MM5240AH 5x7 ASCII-6 with High True Outputs Character Generator
MM4240AK/MM5240AK 5x7 ECMA-6 (French, British, Italian) Character Generator
MM4241 AAN/MM5241 AAN ASCII Vertical Scan Character Generator
ROM Code Converters
SK0003 Sine/Cosine Look-Up Table Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
MM422DAE/MM5220AE ASCII-7 to Hollerith Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220AP/MM4220AP BCDIC to ASCII Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220BL/MM5220BL Baudot to ASCII Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220BM/MM5220BM Sine Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220BN/MM5220BN Arctangent Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220DF/MM5220DF "Ouick Brown Fox" Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220EK/MM5220EK BCDIC to EBCDIC and ASCII to EBCDIC Code Converter . . . . . . . . . . . . .
MM4220LR/MM5220LR BCDIC to ASCII-7, ASCII-7 to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4221 RO/MM5221 RO ASCII-7 to EIA RS244A, EIA RS244A to ASCII-7 Code Converter ...... ,
MM4221 RR/MM5221 RR ASCII-7 to EBCDIC Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4230BO/MM5230BO Hollerith to ASCII Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4230FE/MM5230FE Selectric to EBCDIC, EBCDIC to Selectric Code Converter . . . . . . . . . . . . ;
MM4230JT/MM5230JT BCDIC to EBCDIC, EBCDIC to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4230KP/MM5230KP ASCII-7 to Selectric Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM42300W/MM52300W Hollerith to EBCDIC Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM42300X/MM52300X EBCDIC-8 to ASCII-8Code Converter . . . . . . . . . . . .
MM42300Y /MM52300Y ASCII-8 to EBCDIC-8 Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM523o.RS Binary to Modulo-n Divider Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4231 RP/MM5231 RP IBM 1130 EBCDIC to ASCII-7 Code Converter . . . . . . . . . . . . . . . . . . . . .
DM5488AA/DM7488AA (SN5488/SN7488) 256-Bit Sine Look-Up Table Read-Only Memory .......
DM7598AA/DM8598AA TRI-STATETM 256-Bit Sine Look-Up Table Read-Only Memory . . . . . . . . .
For information on the following code converters contact National, Santa Clara:
MM3501TL ASCII to Baudot, Baudot to ASCII Code Converter
MM4213UW/MM5213UW EBCDIC-8 to HoHerith Code Converter
MM4221TM/MM5221 TM ASCII to Baudot, Baudot to ASCII Code Converter
MM4230JC/MM5230JC ASCII to Hollerith Code Converter*
MM423o.JP/MM523o.JP ASCII to MDS Code Converter
MM423o.JO/MM5230JO Hollerith to EBCDIC Code Converter*
MM4230JR/MM5230JR Selectric to EBCDIC Code Converter*
MM4230JS/MM5230JS EBCDIC to Selectric Code Converter*
MM4230S0/MM5230S0 ASCII-8 to Hollerith Code Converter
<
I
••••••••••••••
179
181
183
185
187
189
191
193
195
197
199
201
202
205
207
209
210.
212
214
216
218
222
Custom MOS/LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 225
Application Notes
AN-40 The Systems Approach to Character Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-44 High Voltage Shift Registers Move Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-50. Dynamic MOS Random Access Memories System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-52 Using the MM5704 Keyboard Interface in Keyboard Systems Consideration . . . . . . . . . . . . .
AN-55 Low Frequency Operation with Dynamic ShiftRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-57 American and European Fonts in Standard Character Generators . . . . . . . . . . . . . . . . . . . . .
229
241
245
251
263
267.
MOS Briefs
MOS Brief 10. Trig Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
MOS Brief 14 Mask Programming Specializes MOS Shift Register Designs . . . . . . . . . . . . . . . . . . . . . 275
Ordering Information and Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . , 279
*Not recommended for new designs.
T6A - To Be Announced
v
MOS Selection Guide
MAX FREQ
PRODUCT TYPE NO.
DESCRIPTION
MIL/COM
a::
enu
·f
(Q
c:
>-
0
e:en
u
.;:;
(Q
U5
~
a::
~
«a::
0
...J
VDD
VDD2
OR
CLOCK
SWING
VGG
1.0 MHz
1.0MHz
1.0 MHz
1.0 MHz
1.0 MHz
1.0 MHz
+10
+10
+10
+10
+10
+10
GND
GND
GND
GND
GND
GND
None
None
None
None
None
None
16
16
16
16
16
16
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
None
None
None
None
None
None
None
None
None
None
None
None
None
None
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
17
17
17
17
17
17
17
17
17
17
17
17
17
17
1.0
2.5
2.2
5.0
5.0
5.0
MHz
MHz
MHz
MHz
MHz
MHz
+5
+5
+5
+5
+5
+5
None
None
None
-9
-9
-9
-12
-12
-12
None
None
None
17
17
17
14
14
14
5.0 MHz
+5
-9
None
14
Dual 16 Bit
Dual 32 Bit
1.0 MHz
1.0 MHz
+10
+10
GND
GND
-6
-6
16
16
MM4040/MM5040
MM4050/MM5050
MM4051/MM5051
MM4052/MM5052
MM4053/MM5053
MM4054/MM5054
MM5081
Dual
Dual
Dual
Dual
Dual
Dual
High
2.2.MHz
1.6 MHz
1.6 MHz
1.6 MHz
1.6 MHz
2.2 MHz
250 kHz
+5
+5
+5
+5
+5
+5
GND
GND
GND
GND
GND
GND
GND
-20
-12
-12
-12
-12
-12
-12
-20
17
17
17
17
17
TTL
-20
MM4203/MM5203
2048 Bit ROM (Pin Compatible
MM4213) TSL
1024 Bit (256 x 4)
1024 Bit (256 x 4)
2048 Bit ROM (Pin Compatible
MM4203) TSL
1024 Bit (256x4 or 128x8)
1024 Bit (256x4 or 128x8)
2048 Bit (512x4 or 256x8)
2048 Bit (512x4 or 256x8)
4096 Bit (1024x4 or 512x8) TSL
2560 Bit Character Generator
3072 Bit Character Generator
Sine Look-Up Table
1.0 JJ,S
650 ns
950 ns
+5
+12
+5
-12
-12
-12
-12
-12
-12
None
None
None
750 ns
650 ns
950 ns
725 ns
950 ns
1.0 JJ,S
600 ns
900 ns
1.0MHz
+5
+12
+5
+12
+5
+5
+12
+5
+12
-12
-12
-12
-.12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
-12
None
None
None
None
None
None
None
None
None
1.5 JJ,S
1.0 JJ,S
1.5 JJ,S
1.0 JJ,S
500 ns
350 ns
360 ns
+5
+5
+5
+5
+5
+5
+5
-7
-7
-9
-9
-9
-10
-10
-9
-9
-9
-12
-15
None
None
None
None
None
15
18
390 ns
+5
+16
GND
-15
12
+10
+10
+10
+10
GND
GND
GND
GND
None
None
None
None·
Dual
Dual
Dual
Dual
Dual
Dual
MM4001 A/MM5001 A
MM4006A/MM5006A
MM4007/MM5007
MI\II4010AlMM5010A
MM4011 A/MM5011 A
MM4012/MM5012
MM4013/MM5013
MM4015A/MM5015A
MM4016/MM5016
MM4017/MM5017
MM4018/MM5018
MM4019/MM5019
MM4020/MM5020
MM4021/MM5021
Dual 64 Bit Split Clock
Dual 100 Bit
Dual 100 Bit Mask Programmable
Dual 64 Bit Accumulator
Dual 64 Bit Common Clock
Dual 256 Bit Accumulator
1024 Bit Accumulator
Triple 60 + 4 Accumul~tor
500/512 Bit
Dual 500/512 Bit
Triple 64 Bit
Dual 256 Mask Programmable
Quad 80 Bit
Triple 80 Bit
MM4100/MM5100
MM4104/MM5104
MM4105/MM5105
MM1402A
MM1403A
MM1404A
MM5024A
144/156 Bit
360/359 + 288/287, 40/32 Bit
Quad 64 Accumulator
Quad 256 Bit
Dual 512 Bit
Single 1024 Bit
Single 1024 Bit with
Internal Pullup Resistor
MM404/MM504
MM405/MM505
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
MM4231/MM5231
MM4232/MM5232
MM4240/MM5240
MM4241/MM5241
SKOO03
MM1101
MMll0l1
MMll01A
MM1101Al
MM1101A2
MM5260
MM5262
MM5263
MM1103
u
.0,
VSS
ACCESS TIME
MM400/MM500
MM401/MM501
MM402/MM502
MM403/MM503
MM406/MM506
MM407/MM507
MM4210/MM5210
MM4211/MM5211
MM4213/MM5213
0
OR MIN
MM480/MM580
MM481/MM581
MM482/MM582
MM483/MM583
25 Bit
25 Bit
50 Bit
50 Bit
100 Bit
100 Bit
16 Bit
32 Bit Common Clock
32 Bit Split Clock
80 Bit
100 Bit
64172/80 On Chip Clock
Voltage (VL =-55V) MM413
256 Bit Static (256 xl)
256 Bit Static (256 xl)
256 Bit Static (256 xl)
256 Bit Static (256 xl)
256 Bit Static (256 xl)
1024 Bit Dynamic (1024x1)
2048 Bit Dynamic (2048x1)
2048 Bit Dynamic with
TSL Output (On Chip Sense Amp)
1024 Bit Dynamic (1024x1)
Dual 3 Input NOR Gate
Dual Exclusive OR ·Gate
Dual Digital MUX Switch
JK Flip Flop
200 ns
400 ns
400 ns
2.4 MHz
18
19
None
None
None
10V
vi
"
MAPS
microprogrammable arithmetic processor system
general description
M icroprogrammable Arithmetic Processor System
devices (MAPS) are MOS/LSI elements that represents a general purpose serial data processor (see
Figure 1). The system can be programmed to operate in binary or BCD up to a 76 bit one cycle data
word. The system provides a wide variety of data
word formating and is appl icable to any serial
arithmetic control system from machine and process control to business mach ines.
•
MM5701 Register Unit
•
MM5702 Timing and Control Unit
•
MM5704 Keyboard Interface Unit
•
MM5705 Control Read Only Memory
Additional elements for system expansion are:
The basic system is comprised of five MOS/LSI
SUb-system elements:
•
MM5703 Control Read Only Memory
•
•
MM5706 Static Data Monitor
MM5700 Arithmetic Un,t
DATA MEMORY
(ACCUMULATOR)
CONTROL LOGIC
(TIMING)
1a. General Computer Organization
CONTROL READ ONLY MEMORY
REGISTER ELEMENTS (MODULAR)
FOR DATA MEMORY RU
CONTROL LOGIC
T&C
1b. MAPS Organization
FIGURE 1. General Purpose Computer Organization Compared to MAPS
.1
The five basic e_lements are interconnected by a
serial bit bus-organized distribution system with
three data buses, and three command buses (see
block diagram Figure 2). The basic cycle of the
system is 76 bits, controlled by a set of 32 data
micro-instructions stored in the arithmetic and
register unit.
packages for easy handl ing and test. Compatibility
with the keyboard, data codes, timing arid programs requ ired for the system appl icaticinis ok>"
tained during wafer fabrication by mask programming. A preprogrammed calculator kit with 14'digit display outputs is available for evaluation
and general use.
MICRO INSTRUCTION
BUSY
ALARM
Y-+-_ _ _-+--11--_ _ _-+--11--_-+_-+-+-----I1/0 BUS I
' - -_ _ _ _ _ _ _ _~_ _ _- +_ _ _----I 1/0 BUS II
(4)
(5)
~
_ _---,I
•
OATA TRANSFER LINE
SIGNAL OR CONTROL DATA LINE
FIGURE 2. MAPS Block Diagram
Data between these elements is passed serial over
the three data buses. The logic sequence of data
handling is programmed in the CRaM element,
each CRaM provides the system 256 words of a
10-bit command. The T&C element interpolates
each command and generates proper time synchronization and time enable signals for performing the
command, thus allowing the data in the AU and
RU. elements to be acted upon. To perform data
result tests and control operations, 32 command
microinstructions are stored in the T &C element.
The format and fu nction performed by each command instruction is programmable by storing the
proper bit pattern for the op-code in CRaM storage. This allows the same basic command instruction to be programmed differently for a wide
variety of machine applications. The keyboard
encoder will accept up to 32 dynamic keys and 8
static switch inputs and the static data monitor
will scan two banks 'of 8 data points.
The speCific system configuration is expandable
since additional RU, CROM, KI and SDM elements
can be added on the data and command bus system. The system will accommodate up to 32
CRaMs or a total of 8192 microprogrammed instructions. Access from microprogrammed instructions in RAM and mass storage can be performed
and controlled. This allows the MAPS elements to
function as mini-processors within a larger system.
The system is dynamic two phase logic fabricated
with National's bipolar compatible, P-channel enhancement mode, low threshold technology. All
elements are in small 16 and 24 pin dual-in-line
':2
features
•
Bus-organized for easy expansion and
face with external systems
inter~
• Keyboard input
• Static data monitor binary or BCD input
• Error-free keyboard decoding (see MM5704AA
data sheet)
• Data and display control outputs
• Clock rates to 750 kHz two phase logic
• DTL/TTL compatible on output for display
• Standard +5V and -12V supplies
• Standard 16-pin and 24-pin DIPs
applications
• General purpose serial computers
• "Smart" data terminals
• Numerical controls
• Electronic business machines
• Point of sales equipment
• Electronic scales
• Electronic calculators
• Traffic controls
• Medical electronics (analyzers, patient monitoring, etc.)
MAPS
MM5704AA MOS/LSI keyboard interface subsystem
general decription
The MM5704AA keyboard interface subsystem is
a monolithic MOS/LSI circuit utilizing P-Channel
enhancement mode low threshold voltage technology. It self-scans 32 dynamic keys (4 x 8
matrix) and 8 static keys for switch closure. The
dynamic key positions are encoded into a 9-bit
code that is transmitted bit serial. The static keys
are encoded into an 8-bit code. A read~only memory' allows customer programming of the character
code for the 9-bit code. Control logic provides
programmable delay times to match the switch
bounce characteristics and key matrix capacjtance
for a wide selection of keyboard elements. Two
"busy" lines are provided so several keyboard
interface chips can be paralleled to decode larger
key matrixes. Two key "roll over" is provided
along with positive lock-out for ambiguous key
depressions.
features
Bipolar compatibility
•
Standard supplies
•
Bit serial data transmission
•
Character code selection
Error-free decode
High speed
Keyboard element flexibility
•
large keyboard
•
Expandable
Busy line 0 Red output
(expandable in multiples of
32 dynamic8 static keys)
•
Timing control
Provides "character ready"
command and responds
on "transmit" command
•
Standard package
Programmable
key bounce delay
Programmable key
matrix capacitance delay
Programmable keys
for alarm clear
Programmable idle
key reset delay
32 dynamic keys
8 static keys
24-pin dual-in-line
package
Minimum external
components required
•
•
0.75 MHz
•
•
+5V, -12V
Uptoa
9-bit code
Program mabie character code ROM
Provides two key
"roll over" mUltiple
key lock-out by an alarm
busy line for active
decode indication
applications
Terminal interface
Calculator
Accounting machine
Typewriter
•
Keyboard decode
•
Binary multiplexer/encoder
Binary remote
sensing
block and connection diagrams
Dual-In-Line Package
ArAlIliOijf 1
lJi"ii1V1\ Nottl
" 11m2
21~
'"
CVClEMARKER
15
(eM)
15~
CASESH:~~
...;'+-------t----'
VsslZ
llCoUT
"I
V"-r
V _
U
"I_
I
Notet· Bury I and BusyZ ".conneettd onlywh.n'tqulldoncuttomkeyboa.dintertlCtUnlt"
Busyl.ndBlIsy2.,connecttdonMM5704.AA.
1
I
K£VBOARDINTEAFACE(KII
I
~-------------------------~
3
absolute maximum ratings
Voltage at Any Pin
Bulk Reference (substrate)
Package Power Dissipation at 70°C
O°C to +70°C
-55°C to +125°C
Operating Temperature Range
Storage Temperature Range
Vss + 0.3V to Vss - 20.0V
Vss
500mW
electrical characteristics
TA = 25°C; Vss = +5V, VGG = -12V; or Vss = OV, VGG = -17V; all supplies ±5%, unless otherwise noted
PARAMETER
Clocks (¢IN ¢OUT)
Repetition Rate (¢I)
Pulse Width (¢pw)
1 Min (90%)
o Min (10%)
Amplitude
Logic Level "0"
Logic Level" 1"
Delay Times
CONDITIONS
0.02
Min·¢1
0.3
0.4
With Respect to V ss
Min. ¢I and
Min. ¢pw
¢IN
¢OUT
Leakage Current
VIN = O.OV
f=1.0MHz
¢IN
¢OUT
Data Inputs
Amplitude
Logic Level "0"
Logic Level "1"
Setup Time (t ds )
Hold Time (t dh )
Capacitance
@25°C
V IN =-18V
Data Outputs
Amplitude
Logic Level "0"
Logic Level "1"
Transition Times
Tpdo
Tpdl
Amplitude
(Alarm Outputs)
TTL
Logic Level" 1"
Logic Level "0"
Transition Times
T pdO
Tpdl
Power Consumption
DC Supply Current Drain
IGG
Key Matrix Lines
Ro through R7 Lines
Amplitude
Log ic Level "0"
Logic Level" 1"
T 1 through T s Lines
Amplitude
Logic Level "0"
Logic Level "1"
TYP
Min. ¢pw
¢d
¢d
Input Capacitance
Leakage Current
MIN
0.75
UNITS
MHz
0.5
0.6
0
-16
-17
-1.5
-19
0.35
0.35
V
V
Ils
125
125
With Respect to Vss
0
-6
50
25
VIN = 0.0 V
f = 1.0 MHz
VIN = -18V @ 25°C
All pins are grounded except
data input pin under test.
With Respect to Vss
MOS Load
(1.0Mr2 and50pF)
III and Alarm
MOS Load
(1.0 Mr2 and
50 pF)
MAX
175
175
0.1
0.1
2.0
2.0
-0.7
-8
100
2.0
pF
v
V
ns
ns
pF
15
0.1
-1.0
-10
0
-7
150
150
(Measured from ¢IN "one to zero" transition)
TTL Load@
VGG = -12V; Vss = +5V
IL=0.5mA
IL = 1.6 mA
Ambient Temp. 25°C
TTL Load @
IL = 1.6 mA
IL = 0.5 mA
350
350
2.4
0.4
ns
V
150
150
350
350
ns
15
20
mA
-1.5
Vss
-2.0
Vss
-7
-10
V
V
-8
With Respect to Vss
V
V
V
Average cu rrent at
¢I = 0.75 MHz
VGG = -20V
¢IN ¢OUT = 20V
With Respect to Vss
-1.5
V
V
PROGRAMMABLE FEATURES
Key Bounce Delay
Key Matrix Capacitance Delay
Character Code
Control Features
Keyboard Clear Switches
Key Rollover
Idle Key Reset Capacitor CR
Static Switch Form
Static Transmit Bit Interval
Static Key Form
E counter programmed for
modulus = 6 (Note 1)
D counter programmed for
modulus = 4 (Note 2)
ASCII 8th bit odd parity
T4 R7 & T 1 R 7; T4 Rs Note 3
Programmed for two
key rollover
External Capacitor tied from
Pin 9 (Note 4)
Normally Open (No) (Note 5)
Bit Time 5 (Note 6)
Normally Closed (NC) (Note 5)
Note 1: Key bounce delay is total delay defined as D counter programmed modulus = 4 driven from
cycle marker {(in and E counter programmed modulus = 6. See programming section and typical
application.
Note 2: Key matrix capaci_tance is the total lead capacitance from the "T" and "R" lines excluding
keyboard package capacitance. This is the total capacitance that must be charged before scanning
starts. 0 counter is programmed for this delay.
Note 3: Three keys on the keyboard have been programmed to clear on "alarm" condition if present.
These are (T4R7), & (Tl R7) and (T4RS) keys. This programming does not affect normal key operation.
Note 4: Idle Key Reset is programmable by an external capacitor CR. This reset is applied only
during the idle mode to enable control logic for first key detection.
Note 5: Shift and static switches can be programmed as normally open or normally closed. (NO) gives
logic "1" out on III bus (NC) gives logic "0" out on III bus.
Note 6: Static Xmit signal duration is one bit time. This is programmable for each keyboard chip to
accrue at a unit bit interval between bit times 5 through 8.
4
I
ms
pF
See code pattern
pF
typical applications
TTL/DTL Logic Compatible - Bit Serial Data Output
BUSY 1 )
SEE ELECTRICAL
SPECIFICATIONS
__
~
BUSY 2
J
IDLE KEY RESET
~ CR NOTE3
KEYBOARD INTERFACE
SUBSYSTEM (KI)
MM5704
Vss OR OPEN
VGG
ALARM OUT
CASE SHIFT
(CS)
---<>
NOTEI
TTL COMPATIBLE
VGG (-12V)
Vss
16K
Vss (+5V)
CYCLE
MARKER
(CM)
V3 (OPEN)
V2 (V GG )
1/20M8800
TTL COMPATIBLE
V3 (OPEN)
V2 (V GG )
Note 1: With single keyboard interface application, if busy lines are not used in system, leave open. If
system will use busy signal, it will require MOS to TTL interface. In multiple (Ki) subsystem
applications, busy lines are connected busy 1 to busy 1 and busy 2 to busy 2.
Note 2: Data on data bus is in RZ format. Data should be strobed at ¢OUT.
Note 3: CR value dependent on keyboard scan frequency.
TTL/DTL Compatible - Output Bit Parallel
l
BUSY 1
_ _ ( NOTEI
BUSY 2
SEE ELECTRICAL
SPECIFICATIONS
IDLE KEY RESET
~ CR NOTEl
KEYBOARD INTERFACE
SUBSYSTEM (KI)
MM5704
Vss OR OPEN
VGG
---<>
J
ALARM OUT
CASE SHIFT
(CS)
TTL COMPATIBLE
VGG (-12V)
Vss
16K
CYCLE
MARKER
(CM)
¢IN
DATA STROBE
r-----~----~~---Vss
NOTE 2
15
1/2DM8800
~
DATA BUS
11.<1)
V3 (OPEN)
V2 (V GG )
PARALLEL
OUTPUT DATA
SERIAL OUTPUT
(COMMAND SIGNALS)
Note 1: With single keyboard interface application, if busy lines are not used in system, leave open. If
system will use busy signal, it will require MDS to TTL interface. In multiple (KI) subsystem
applications, busy lines are connected busy 1 to busy 1 and busy2 to busy 2.
Note 2: Data on data bus is in RZ format. Data should be strobed at ¢OUT'
Note 3: CR value dependent on keyboerd scan frequency.
5
timing diagrams
Sequence of Command and Data Transfer
alTTIMES -
0
1
4
5 6
7 8
9
1011 1213 14 15 18 17 181920212223
CYCL~~~RKER:l~__~r______________________
-___
J~
XMIT KEY
:.--J1'--______=~-----------------
STATlCXMIT ________.....n-rT1NOTE3
_ _ _ _ _ _ _ _ _ _-....In~_ _ _ _ _ _ _ _ _ _ _ _ _ ____
ALARM RESET ________________....InL...--,-_______________
CHAR~~!~~
________________-....InL_ _ _ _ _ _ _ _ _ _ _ _ _ __
KEYBOARD
ALARM
n;::;:::;:::::;:::;:::;:::;::::;:::;:::;-_
CHARAg!~: ____________________---! : : : : : : : :
~'ST.TlC/81----l
(FordtfinitiolloftllmsSteplll6)
code patte rn
Keyboard Interface ASCII Code Program
Static Key Form
Key
Identity
Q
W
E
R
T
y
U
(5)1
A
S
D
F
G
H
J
K
Z
X
C
V
B
N
M
L
0
P
[
\
)
(5)r>
@
(5)-
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
6
Scan
Line
T
R
T1
T1
T1
T1
n
T1
T1
T1
T2
T2
T2
T2
T2
T2
T2
T2
T3
T3
T3
T3
T3
T3
T3
T3
T4
T4
T4
T4
T4
T4
T4
T4
RO
R1
R2
R3
R4
R5
R6
R7
RO
R1
R2
R3
R4
R5
R6
R7
RO
R1
R2
R3
R4
R5
R6
R7
RO
R1
R2
R3
R4
R5
R6
R7
No X
NC
Upper C~ Logic
Level + -
Counter
Program
X
NC
Device 11 mel 2 0
No.
3 0 4 0
No
Pin No. 2(+)
(Alpha)
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
Modulo
Driving
Function
D Counter
4
CM
E Counter
6
-Key
Iden' tity
1
7
%
2
4
9
5
)
!
3
$
&
.
(,
+
:
8
#
6
"
I
0
;
<
=
>
SP
?
Timing
Units
Pin No. 2(-) (Numeric)
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
-0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
0
A logic "1" or "X" ~ "most negative vOltuge".
A logic "0" = "most positive voltage".
All "Don',t Care" cases must be defined as a "1" or "0".
If less than 9 bits are used unused bits will be programmed logic "1".
These locations are programmed for clearing the keyboard alarq:l.
Bit eight (column 7) is odd parity bit for ASCII code shown.
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
I
I---:-OYNAMIC/91---j
Notel: CycltM,"'"clnnotoccursoonerthln228itTimlL
Note 2: BitTin,= 1/;' -LIVtI"Yss -8V minimum: + LflllI-V•.
Note 3: Stlti: Xmit Signll is one Bit Tim, - Progr__ med for Bit Timt 5 in MMI7Q4.AA.
Case Shift
Control (CS)
L
0
0
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
programming of MM5704
Keyboard Scan Cycle
The matrix scan cycle includes:
Counter advancing through each liT" quadrant line T 1 through T 5 each with D c9untet
delay to charge . "T" line capacitance.
condition to repeat, in hopes of voiding the keyboard logic, as soon as the keys are released and
bounce delay timed out the idle key reset enables
the control logic. The value of the reset capacitor
is dependent on the keyboard scan cycle. The value
of the external capacitor is:
2 Counter advancing through eight switches in
each liT" quadrant except for T 5 static switch
quandrant.
i1 X tc
v:;average charging current
3 Dcounter advances on either system clock
4>IN or Cycle Marker (programmable feature).
The keyboard scan frequency
= 1 rnA
reset voltage = 3.0V
E+n
tc
charging time interval tc
E
modulo of E counter
n
number of scan cycles beyond bounce
out delay
~
r
fscan = Kd
+ ([>f
where
K
d
5 (five T quandrants)
=
D counter delay time
ulus x
= (D
counter mod-
;s)
33 (Four quandrants times eight switch
scans + 1 bit time for T 5 static switch
transfer).
4>f = The frequency at wh ich the clock 4>IN is
shifting data through the device.
4>s
=
4>f when D counter driven by 4>1 or 4>f/ X
when x is bit times between Cycle Markers.
Key Bounce Delay Time
Since the M counter advances the E counter once
each complete keyboard scan the modulo of the E
counter determines the key bounce delay
r
E . (Kd + ([>f)
4>1 = frequency of clock 4>IN
Standard Keyboard Timing
National has programmed a keyboard interface element with the following conditions:
Static Switch Form Normally Open (NO)
Device Number one: static Xmit during bit
time 5
Case shift form Normally Open (NO) (alpha
characters)
Character Code ASCII (8 bits with 9th bit
odd parity)
E counter modulus = 6
D counter modulus = 4
D counter driven by Cycle Marker CM
Identified as MM5704-AA (see code pattern)
Typical Application
E = modulus of E counter
The key bounce delay time is the total time elapsed
from the first detected key depression until the
load flip-flop signals transfer of the character code
from ROM to the 9 bit shift register. The E counter
controls the number of times the entire keyboard
is scanned before a valid key depression is accepted.
Variations in timing are obtained from programming of the D counter, E counter, 4>1 (system
operating frequency) and Cycle Marker rep rate
provide flexibility for the keyboard interface ele~
ment to interface with a wide variety of key
switch elements.,
The two main questions in most applications are:
a. How much key matrix capacitance can be
charged?
b. What is.the key bounce delay time?
c. What is value of idle key reset capacitor?
Using MM5704-AA in system with following characteristics
4>1 = 200 kHz 4>OUT(PW)
Cycle Marker frequency
transfer case)
= 0.5 f.1S
4>f/21 (maximum data
Key bounce delay
Idle Key Reset
During an idle key mode (power on) an automatic
reset signal is generated by charging an external
capacitor C R which enables the control logic to
detect first key depression. This reset prevents
keyboard lock-up by mass depression of keys or
any attempt to void the integrity of the keyboard
encoding. As an example, if a person attempts to
hold down three or more keys to force an alarm
=
E . (Kd +
6 . [5(4
r
-;p;)
x;s )+ !~ ]
21)
6 . [5(4 x +
200
X
3
10
33
200
X
103
]
=
13.5 ms
7
programming of MM5704 (con't)
D counter is programmed to charge key matrix
capacitance
D counter delay
1
21
d =4 x - = 4 x
= 420 p.s
.1
T2
I
1
OATA~.7
I1
INPUT
TA
I
I
I
F
'* * See chart
A
GNO--~I_
Vss
below
Note: Pin 4 connected to Clse
_ . - -.....- - - : - -. . . .- -.....- - - : - - _ . - -......
- - - . . .....- - CLOCK
n·1 STAGE
TOP VIEW
---t---
4>. ON PIN 3
typical applications
FIGURE 1 - TTL/MOS Interface-Low Frequency
(see clock timing graph for detail)
FIGURE 2 - TTL/MOS Interfaces
+lOV
+5V
3.9K
3.9K
3K
Vss
3K
Vss
NA BIT REGISTER
NA BIT REGISTER
No BIT REGISTER
Voo
3.6K
CLOCK V¢,. 2 REQUIREMENTS WITH Vss ~ +lOV
CLOCK V,. 02 REQUIREMENTS WITH Vss ~ +5V
-5V
CLOCK REP RATE 650 kHz TYP.
+4.5V
LOGIC "0:' IV ss )
LOGIC "1" IVss - VOL)
-6V
LOGIC "0" IV ss)
+9.5V
LOGIC "1" IVss - VOL)
-6.0V
-lOY
Waveforms for Applications
(complete timing diagrams on page 11)
Standard Register Configurations t
I
CLOCK,
CLOCK2
TYPICAL DATA IN
V
I
V
I
vss-:'~
ss~
I
I
Vss-V.
IV.. -2.5V)
~\
"...-=:-\I"
OPEN DRAIN OUTPUT
CONFIGURATION
20 KnOUTPUT
-SSoC to
+12SoC
- 2SOC to
o
+70 C
-SSOCto
+12SoC
- 2SoC to
+70°C
Dual 25 bit
MM400
MM500
MM401
MM501
Dual 50 bit
MM402
MM502
MM403
MM503
• Dual 100 bit
MM406
MMS06
MM407
MM507
IV ss -4.5V)...........
I
IVSS-l.5V)====~I-_I=~
TYPICAL DATA OUT IV..
_8.0V)_N_B_IT_OE_L_AY_~'=-=J-_---\L=
t For other length registers consult your National representative.
* For New Designs, See MM4006A/MM5006A Data Sheet
9
(/)
G)
...
absolute maximum ratings
G)
Drain Voltage (-V DO)
Clock Inputs (V1>, , V1>2)
Data Inputs
Power Dissipation (Note 1)
Operating Temperature MM400 Series
MM500 Series
Storage Temperature
en
0
0
it)
:E
:E
,0
+0.5V to -25V
+0.5V to -25V
+0.5V to -25V
500mW
-55°C to +125°C
_25°C to + 70°C
-65°C to +150°C
electrical drive requirements
PARAMETER·
0
~
Clock Pulse Width
=-16V - -
.1
~
I
MM406
z
ct
0.
Cii
10
I
--
=
'"S
-'
II:
~
>
./
MM402~
u
~ ~~
1.AiI
~
~
~
0.1
[/'
500
~
1/
50
10
/
/
iii
Z
C)
~
ct
II:
~
f
.,-.
CD
I
o~L=~~~~~~
20
-20
100
60
o
140
-1
-2
-3
-4
-5
-6
-7
CD
-8
(I)
OUTPUT VOL TAGE (VOLTS) (BELOW Vss )
Clock Timing, Direct-Coupled TTL or DTL
1.8
~
1.4
.!
1.2
0.8
ct
0.
'"S
0.6
II:
0.4
w
0.4
5:
V
1.0
~
0.8
5.0
w
a:I
ct
Z
C)
1.0
1.4
1.2
~
iii
0.
Cii
'"S
I
Power Dissipation/Bit vs. Clock Amplitude
1.8
~
o
o
en
.1
TEMPERATURE (OC)
Power Dissipation/Bit vs. Supply Voltage
~
I
Voo = -10V_
V4>l = V4>;z = -16V
I
OPERATING FREQUENCY (kHz)
.!
4 I--+----.f-
TYPICAL -
~~
/
l/
10
-60
1000
100
s:
s:
en
/
~
20
"
o
........
/
~
./
~ 100
V'~
f
GUARANTEED
1K
~ 200
;:)
MM400=
o
7
2K
N
C)
~
Output Sink/Source Current
8~~~--r-r--r-'--~~
V
5K
~Voo=-1OV
~
Minimum Operating Frequency
1oK-
1
I
0
0
-9
-8
-10
-11
-12
-12
-16
-14
-18
ons
-20
CLOCK AMPLITUDE (VOLTS)
Voo (VOLTS)
200 ns
400 ns 0.6
j.LS
0.8
j.LS
1 IlS
CLOCK 1' V cf>2
600
4.5 N
:I:
~
>
~
;:)
4.0
FREQ.
(MHz)
-
3.5 f-
u
3.0
d
w
2.5
~
xct
2.0
=e
1.5
1.0
Power Dissipation/Bit vs. Temperature
Maximum Package Power Dissipation
vs. Maximum Frequency
5.0
"-
pw
-25
25
75
125
TEMPERATURE rC)
TEMPERATURE (OC)
V2pw = 0.2 p,s; cf>d = 0.1
p,s; f
= 1 MHz; except as otherwise
noted.
timing diagram
operation
Each bit of delay shown in the circuit schematic consists
of two inverters T1 and T4 accompanied by clocked load
resistors T2 and T5 and two coupling devices T3 and T6.
The circuit functions as follows: When cf>2 goes negative
(one state) the coupling unit TA and the load resistor
T2 are clocked ON allowing information at the input to
be transferred to node A turning T1 ON or OFF depending on the state of the input. For example, if a negative
potential (near -VOO levei) is transferred from the input
to the gate to source capacitance at node A, then T1
-VOO
turns ON allowing node F to be at --2-' When cf>2 returns to its zero state (ground level) T2 turns OFF allowing node F to discharge to zero volts. When cf>1 goes negative (one state) the coupling unit T3 and the load resistor T5 are clocked ON allowing information at node F
to be transferred to node B. T4 is held OFF if node F was
at ground potential and is turned ON if node F had been
at -Voo potential. Continuing the example above, T4 is
!:leld OFF and node G is at -Voo since T5 is ON during
cf>1 clock pulse. When cf>1 returns to its zero state, node G
maintains a -Voo voltage level. This voltage level is
~aintained at node G until the cf>2 clock appears. The
bit delay demonstrated in this example is repeated
through each half of the dual register.
I
DATA OV
INPUT -v_
I
--I. t-t.l.
I
I
--i
NODEA
_ _ _ _.I
NODE B
NODE C
DATA
OUTPUT
11
Dynamic Shift Registers
..
~
MM1402A/MM1403A/MM1404A/MM5024A
1024-bit dynamic shift register
o~
~
~
~
general description
The MM1402A/MM1403A/MM1404A/MM5024A
1024-bit dynamic shift registers are MOS monolithic integrated circuits using silicon gate technology to achieve bipolar compatibility. 5 MHz
data rates are achieved by on-chip mUltiplexing.
The clock rate is one-half the data rate; i.e.,
one data bit is entered for each 1>1 and 1>2 clock
pulse.
•
All devices in the family can operate from +5V,
-5V, or +5V, -9V power supplies.
applications
•
Radar and sonar processors
features
•
CRT displays
•
•
•
Terminals
Desk top calculators
Disk and drum replacement
Four standard configurations
MM1402A
MM1403A
MM1404A
MM5024A
Quad 256-bit
Dual 512-bit
Single 1024-bit
Single 1024-bit
with internal 4.7k
pull-down resistor
•
Guaranteed 5 MHz operation
•
Low power dissipation
•
DTL/TTL compatible
•
Computer peripherals
Low clock capacitance
125 pF
•
Low clock leakage
~
•
•
•
Inputs protected against static charge
Buffer memory
Special purpose computers-signal processors,
digital filtering and correlators, receivers, spectral compressors and digital differential analyzers
•
Operation from +5V, -5V or +5V, -9V power
supplies
•
.1 mW/bit at 1 MHz
1 pA
•
Telephone equipment
•
Medical equipment
connection diagrams
Dual-In-Line Package
Metal Can Packages
Voo
Voo
Voo
16
NC
15
NC
INI
14
OUT4
13
NC
Vss
12
Voo
OUT2
11
92
NC
10
TOP VIEW
TOP VIEW
MM1403A
MM1404A
MM5024A
TOPVIEW
MM1402A
typical application
DTL/TTL to MOS Interface
+5V
3K , . . - _ - : : ' - _ - - ,
RL Load Resistor Value
for Different V DO Suppl ies
d
Logical HIGH Level (Vrt>H)
Logical LOW Level (V rt>d
Logical HIGH Level (Vrt>H)
Clock Leakage Current
Clock Capacitance
Data Output Levels
Logical LOW Level (VOL)
Logical HIGH Level (V OH )
Logical LOW Level (Vod
Logical HIGH Level (V OH )
Logical HIGH Level (V OH )'
Logical HIGH Level (V OH )
Power Supply Current (I DD )
Data Output Leakage Current
Internal Resistor (MM5024A)
Output Capacitance
ae characteristics
TA =
-25°C
to
Voo
PARAMETER
MIN
Note 1
Clock Frequency (t(min) '" rt>d + tf
«
rt>PW
«
rt>d or ¢d), where the variables may not
exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by periodic testing.
13
performance characteristics
Guaranteed Minimum Data
Frequency vs Temperature
(Note 1)
Guaranteed Maximum Data
Phase Delay Times vs
Temperature (Note 1)
10k
]: 100
I~
N
a:
c
"-
~
~.
10
::.
>
W
1k
Co.)
~
~
ffi
...c
/
~
1,=tt=10ns
x
0.1
;
-60
-20
20
c
::E
::E
/
10
::I
'-'d=4Jd r-- I--
/
100
d OR d = 10 ns
::I
/
Z
¢pw = 130 ns
:E
==
<1>1, - t, -10 ns-
1
-20
-60
100
60
100
60
20
AMBIENT TEMPERATURE, TA (oC)
AMBIENT TEMPERATURE, TA rC)
switching time waveforms
Multiplexed 4-Bit MOS Shift Register
BIT TIMES
0,
I
BITl
-u
02
I
BIT2
I
I
I
I
I
I
I
I
I
LJ
LJ
I
LJ
I
LJ
U
1
1
LJ
1
1
1
1
1
1
I
1
I
I
I
I
1
I
LJ
I
U
I
LJ
I
LJ
I
LJ
I
U
I
U-
1
1
I
I
I
1
f
1
I
1
I
I
I
I
I
I
I
1
I
I
I
I
I
1
I
1
I
I
I
I
I
I
-fFl
"1"
DATA IN
BIT4
BIT3
I
2
DATAIN
"0"
I
DAT3AIN
Fl
"1"
"0"
"1"
"1"
·1
DATA OUT
enters the register at 1>1 time, it exits at ¢1 time.
(Beginning on 1>1'5 negative going edge and ending
on the succeeding 1>2'5 negative going edge.)
Shown is a simplified illustration of the timing of
a 4-bit multiplexed register showing input output
relationships with respect to the clock. If data
timing diagram
81Tl
81TZ
8ITN+l
BITl
8ITN
BITN+2
BITZ
e------
v,.
1011U-/>,
CLOCK
9011-1
/>~
I
.
CLOCK
II
II
--l---------V4L
II
II
-ll-- ---II-- />~
:~I v,"
I!
:
""i 'I -- 9011
i
. . -l-l 1 - : : :
I I ---I .... I-OATA PERIOO-i
;;;::"'1.
:
9011
--
i
---v
I:
"
I
9011
--
:
X------------~~----------i4-----:-----. Vo<
'-iNiiiT
INBITZ
1
tpdH_:
:__
_:
\--tpdl.
1L
V
----------------------j~---------l
1I----vOH
DATA OUT
1 / .\ ______ J ' " - - V
OUT 81T 1
14
OUT 81TZ
OL
Dynamic Shift Registers
MM4001A/MM5001A dual 64-bit dynamic shift register
MM4010A/MM5010A dual 64-bit accumulator
general description
features
The MM4001A/MM5001A dual 64-bit dynamic
shift register is a monolithic MaS integrated circuit utilizing P-chann~1 enhancement mode low
threshold technology. The device consists of two
64-bit registers with independent two phase clocks
and is guaranteed to operate at a 2.5 M Hz operating frequency for CRT display appl ications.
•
High frequency operation
•
Low power consumption 0.4 mW/bit at 1 MHz
•
DTL/TTL compatibility
•
Minimum operating frequency
The MM401 OA/MM501 OA is a dual accumulator
function capable of operating at very high frequency. The device is also constructed on a single
silicon chip utilizing MaS P-channel enhancement
transistors. With the recirculate control line at an
MaS logic 1/01/ state, the device functions as an
accumulator. A logic 1/11/ state at the recirculate
control line allows external information to enter
the register serially. It is important to note that
recirculation of data is performed internally, independent of the output circuit thus making it
insensitive to output loading.
•
Application versatility
+5V, -12V power
supplies, push-pull
output stage
guaranteed
250 Hz at 25°C
I/Split clock" operation, independent
control of each
register for
MM4001 A/MM5001 A
applications
•
Business machine
•
CRT refresh memory
•
Delay line memory
•
Arithmetic operations
load control truth table
connection diagrams
MM4001A/MM5001A
3.3 MHz typ
MM4010A/MM5010A
MM4010A/MM5010A
VGG
VGG
LOGICAL HIGH LEVEL
(V LCH )
LOGICAL LOW LEVEL·
Reci rcu Iates " old" data
Loads "new;' data -
(VLCL);
Vss
Note: Pin 5 connected to case.
TOP VIEW
Note: Pin 5 connected to case.
TOP VIEW
typical applications
MM4001A/MM5001A TTL/MOS Interface
MM4010A/MM5010A TTL/MOS Interface
L.::--------I MM4010A/MM5010A
V-:.
fo
-12V
OIN
OOUT
15
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM4010A/MM4001 A
MM5010A/MM5001A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22V
_55° C to +125°C
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating temperature range, Vss
PARAMETER
=
+5.0V ±5%, V GG
CONDITIONS
Data I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (Vld
=
-12.0V ±1 0%, unless otherwise stated.
MIN
Vss - 2.0
Vss - 18.5
Data Input Leakage
V IN = -20V, T A = 25°C
All Other Pins GND
Data Input Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND
Note 2
Load Control Input Levels
Logical HIGH Level (V LCH )
Logical LOW Level (V LCt!
V IN = -20V, T A = 25°C
All Other Pins GND
Load Control Input Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND
Note 2
Clock I nput Levels
Logical HIGH Level (VH)
Logical LOW Level (VL)
V¢ = -20V, T A = 25°C,
All Other Pins GND
Clock Input Capacitance
V¢ = O.OV, f = 1 MHz,
All Other Pins GND
ISOURCE = -0.5 mA
ISINK = 1.6 mA
Vss + 0.3
Vss - 4.2
v
V
JlA
3.0
5.0
pF
Vss + 0.3
Vss - 4.2
V
V
0.01
0.5
JlA
3.0
5.0
pF
Vss + 0.3
Vss - 14.5
0.05
17
MM4001A/MM5001A Note 2
MM4010A/MM5010A
UNITS
0.5
Vss - 1.5
Vss - 18.5
Clock Input Leakage
MAX
0.01
Vss - 2.0
Vss-18.5
Load Control Input Leakage
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod
TYP
34
2.4
1.0
V
V
JlA
20
40
pF
pF
Vss
0.4
V
V
Power Supply Current
IGG
TA = 25°C, VGG = -12V,
¢pw = 150 ns, Vss = 5.0V,
V¢L = -12V, Data=0-1-0-1
0.01 MHz:S::: ¢f:S::: 0.1 MHz
¢f = 1 MHz
¢f = 2.5 MHz
Clock Frequency (¢f)
¢t, = ¢tf = 20 ns, Note 1
0.01
Clock Pulsewidth (¢pw)
¢t, + ¢pw + ¢t,:S::: 10.5 JlS
0.15
Clock Phase Delay Times (¢d'¢d)
Note 1
Clock Transition Times (¢t" ¢tf)
¢tf + ¢pw + ¢t,:S::: 10.5 JlS
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
Note 1
2.0
3.0
3.0
5.0
4.5
7.0
mA
mA
mA
3.3
2.5
MHz
10
10
Jls
ns
Jls
0.20
0.20
100
100
Jls
JlS
Data Input Setup Time (td.)
80
30
ns
Data Input Hold Time (tdh)
20
o
ns
Load Control Input Setup Time
80
30
ns
20
o
ns
(tLcs)
Load Control Input Hold Time
(t LCh )
Data Output Propagation Delay
From ¢OUT
Delay to HIGH Level (t pdH )
Delay to LOW Level (tPdL)
See ac test circuit
150
150
200
200
Note 1: Minimum clock frequency is a function of temperature and partial bit times, TIN and TOUT,
as shown by the
t..:I
ffi
I' ~
I-
:::l
....0
~
10.0
10
V /
0.1
t..:I
..... TIN = TOUT - -
f--
"-
-;; 1.0
~
~
x
H)
Logical LOW Level (VL)
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss - 18.5
Clock Input Leakage
v'" = -2.0V, T A = 25°C,
All Other Pins GND
Clock I nput Capacitance
v = O.OV, f = 1 MHz,
All Other Pins GND
(Note 1)
0.05
1.0
V
V
pA
MM4006A/MM5006A &
MM4007/MM5007
50
65
pF
MM4019/MM5019
95
125
pF
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VOL)
ISOURCE = -0.5 mA
ISINK = 1.6 mA
2.4
Vss
0.4
~
3:
~
o
o
en
l>
.........
3:
~
V
V
U1
o
Power Supply Current
IGG
TA = 25°C, VGG
ct>pw = 150 ns
= -12V,
Vss = 5.0V, V"'L
Data = 0-1-0-1
= -12V,
o
en
»
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019
0.Q1 MHz::;:;: 1::;:;: 0.1 MHz
2.0
2.5
3.0
3.5
mA
mA
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019
ct>f = 1.0 MHz
4.0
5.0
6.0
7.0
mA
mA
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019
ct>f = 2.5 MHz
6.0
9.0
9.0
12.0
mA
mA
3.3
2.5
MHz
Clock Frequency (f)
ct>t, = tf = 20 ns
Clock Pulsewidth (pw)
tf + pw + t,:S:;;: 10.5 J.ls
Clock Phase Delay Times (ct>d' ¢d)
(Note 2)
Clock Transition Times (t" tf)
ct>tf + pw + t,:S:;;: 10.5 ps
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
(NotIl2)
.01
10
0.15
1.0
0.20
0.20
Data Input Setup Time (t ds)
Data Input Hold Time (tdh)
J.ls
ns
10
ps
100
ps
100
J.lS
80
30
ns
20
o
ns
Data Output Propagation Delay
(See ac test circu it)
from ct>OUT
Delay to High Level (t pdH )
Delay to Low Level (tpdd
150
150
200
200
ns
ns
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT)
as shown by the ¢f versus temperature and TIN, TOUT versus temperature,curves. The lowest guaranteed clock frequency for any temperature can be attained by making TIN equal to TOUT. The
mjnimum guaranteed clock frequency:
1
¢f(min) =
, where TIN and TOUT do not exceed the guaranteed maximums.
TIN +TOUT
19
performance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 2)
.
-;;;
r-
>
TIN or TOUT - 200 ns
(,)
~
]
~
...
.Y V
1.0
:J
0
I-
~
""
10
Z
~
~
(,)
~
Typical Data Output Source
Current vs Voltage
100
10
~
~
Guaranteed Maximum TIN
and TOUT vs Temperature
(Note 2)
.
/
0.1
TIN = TOUT -
/
..=
r- -
::E
~
::E
xex
::E
~
::E
"
1.0
::E
"-
:2
.......
:E
"
0.1
0.01
-60
-20
20
60
100
60
TEMPERATURE
100
n)
~--r---r---r-~r-~r-~
10
9
-.... .......
-
Vss = 5.0V
VGG = -12.0V
V¢L = -12.0V
.......
4
14
-1
15
_H4
~
~
~
-r
3.0
16
-
~
..s
CJ
1.0
I
_
....... ~
~i""'"
-
125~C
18
17
19
14
15
16
17
18
19
Typical Power Supply Current vs Clock
Frequency MM4006A/MM5006A/
MM4007/MM5007
10.0
=:tlik55 °C
-
1111
-
TA - 25°C
I
3.0
<"
..s
TA =25°C
125°C
.E
=25°C
.......
I I
J I
I-
'\
- ...... -
-..-r-il
...... .l-+~
I I
~
~
TA
_i""'"
-;t;J
I I
-~5oJ
-
...... ~ 1"1
1-
....... ..-i""'"
~~
-
-55°C
~-
Of= 1.0MHz
9pw = 150 ns
Vss =5.0V
_
V,'L ~ -12.0V
DATA = 0-1-0-1
TA =25°C_ ....... .......
Typical Power Supply Current
vs Clock Frequency MM4019/
MM5019
10.0
Typical Power Supply Current
vs Voltage MM4019/MM5019
9
.......
<"
-1
10
-55°C
f=
140
Typical Power Supply Current vs
Voltage MM4006A/MM5006A
MM4007/MM5007
Typical Data Output Sink
Current vs Voltage
12
20
-20
140
AMBIENT TEMPERATURE rC)
=
CJ
1.0
.E
-- --
=
--=
L.;I""
1/
~
t""~
I'
125°C
= 150 ns
Vss= 5.0V
VGG = -12.0V
VOL = -12.0V
DATA = 0-1-0-1
¢PW
0.3
0.3
'--
0.1
0.001
0.1
I-.
0.01
0.10
1.0
CLOCK FREQUENCY, ¢tlMHz)
switching waveforms
10.0
0.001
'"''
0.01
0.10
1.0
10.0
ClOCKFREQUENC~~(MH~
ac test circuit
+5V
4K~1
ou~~~~ o--...- ...-tOUT
OUTPU~i:~~~~
5
>--i-OOUTPUTB
DATA~;~Ti
0-,- - - - - - - - '
6
11
INPUT ENABLE
DATA INPUT B
7
10
INPUT ENABLE
Vss
8
9
~~~;R~EllECT
-
CONTROL 13
~~!:~~ ~=========:::1::>>----------.J
TOP VIEW
typical application
TT LIM as Interface
I
I
I
JTA
INPUT
,US
LINE
(TTUOll)
21
absolute maximum ratings
Voltage at Any Pin
Operating Temperature MM4012
MM5012
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3 to VSS - 22
-55°C to +125°C
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +5.0V ±5%, VGG = -12.0V ±10%, unless otherwise noted.
PARAMETER
CONDITIONS
Data I nput Levels
Logical HIGH Level (V ,H )
Logical LOW Level (V ,L )
MIN
TYP
Vss - 2.0
Data I nput Leakage
Y'N '" -20.0V, TA = 25°C,
All Other Pins GND
Data I nput Capacitance
Y'N = O.OV, f = 1 MHz,
All Other Pins GND
Note 2
Control I nput Levels
Logical HIGH Level (V CH )
Logical LOW Level (V CL )
0.01
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
0.5
p.A
5.0
pF
Vss + 0.3
Vss - 4.2
Vss - 2.0
V
V
Control I nput Leakage
Y'N = -20.0V, T A = 25°C,
All Other Pins GND
0.01
0.5
p.A
Control I nput Capacitance
Y'N = O.OV, f = T MHz,
All Other Pins GND
Note 2
7.0
10.0
pF
Vss + 0.3
Vss - 14.5
V
V
Clock I nput Levels
Logical HIGH Level (VH)
Logical LOW Level (V L)
Vss - 1.5
Vss - 18.5
Clock I nput Leakage
V = -20V, TA = 25°C,
All Other Pins GND
Clock I nput Capacitance
V=O.OV,f= 1 MHz,
All Other Pins GND
Note 2
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod
Data Bus Output Leakage
ISOURCE = -0.5 mA
ISINK = 1.6 mA
0.05
110
2.4
1.0
125
Vss
0.4
10
Vss - 5V:S: Bus VOUT:S: Vss
Bus Output Disabled, T A = 2SoC
p.A
pF
V
V
p.A
Power Supply Current
IGG
TA = +25°C, VGG = -12V,
<.>
'-
i= 10
....
~
"~
ex
.§.
.....VV
1.0
Cl
~
Z
::iE
~
:;::
..=
:::I
TIN or TOUT =MINIMUM
:::I
::J
0
I-
::iE
I-
" 'TIN=ToUT- t-- -
::.::
1.0
g<.>
x
c(
"
::iE
0.1
-60
-20
20
~
100
60
0.1
:e
:::I
:e
Z
:E
w
g
c.:I
V V
<.>
'1'0...
2
~
Vss = +S;OV
VGG =-12.0V
V"'L =-12.0V
DATA = 1-0-1-0 1UI---+-l+l+HII--~+
18.0
16.0
14.0
12.0
10.0
8.0
~::P4mll=ij~l::~+
6.0'
4.0 I2.0
0.01
0.0
140
-60
AMBIENT TEMPERATURE rC)
-20
20
60
100
10
140
AMBIENT TEMPERATURE rC)
Typical Data Output Sink
Current vs Voltage
6 r---;r----r----,.---.""'T'"-.""'7'....,
20.0
ex
16.0
I-
~
4
ex
14.0
Cl
12.0
.§.
:::I
<.>
2
w
w
<.>
c.:I
c(
a:
:::I
~
>
c(
I:)
en
I-
~
I
10.0
8.0
6.0
I--- ....
-
:::I
2.0
I:)
~---I_----L_--I.._--l.._--'--_.....J
S
4
-1
w
<.>
2:
S.O
\
c(
I0:; 4.0
c(
%:
<.>
~
~
t:::
16.0
17.0
18.0
19.0
ac test circuit
.............
3.0
DELAY
R1
C1
tpdL
35k
20 pF
tpdH
35k
20 pF
tOH
2.5k
5.0 pF
t'H
2.5k
5.0 pF
DATA
I-
our:~~ 0-_--+---..............
~ 2.0
I:::I
C)
-
~~
Vss - VGG (V)
V"'L =VGG
TA = +2SoC
Vss = S.OV
"
-
I
IS.o
Typical Bus Output
Capacitance vs Voltage
...... 6.0
I--±::: ~
0
4
-1
7.0
-slsoC
--+-""'" ~
~1i"+12S0C
I TA =+2SoC
4.0
I-
o
10,000
DATA = 1-0-1-0
TRI-STATE Output Enabled
¢ipw = ISO ns
¢if = 1.0 MHz
18.0
.§.
a:
a:
1000
Typical Power Supply
Current vs Voltage
Typical Data Output Source
Current vs Voltage
12 ----~--~--~--~--~--~
100
OPERATING FREQUENCY (kHz)
1.0
*tOH and t'H only tested on
5.0
3.0
1.0
-1.0
-3.0
TR I·STA TE bus output.
-5.0
VOUT (V)
timing diagram
DATA INPUT OR
DATA BUS
h'
-----,,4---+---+-:---+-:....:..."----+-------------------OU~~!:i;:~J:; V~-4.2
OUTPUT ENABLE
SeleCT cg~;~~~ ---------.,.,.V~.....-.,..,2.0~
(1+25&8115)
:~T+A2~~~~S~----------j--!v~f--.,il',=::-'~--~------~----------------_______
23
logic table
(Notes 3, 4)
MODE
REGISTER
SELECT
CONTROL
PIN 9
ENA/3 LE
CONTROLS
PIN 10
PIN 11
INPUT
SELECTION
A
A
A
A
A
A
B
A
PIN 3
OUTPUT
SELECTION
FUNCTION
PIN 4
Register
Register
Register
Register
Register
Register
Register
Register
to
to
to
to
to
to
to
to
A input, B Register to B input
A input, B Register to B input
A input, B Register to B Input
A Input, B Register to B Input
A Input, B Register to B Input
A input, B Register to B input
Data Bus input, A Register to A Input
Data Bus input, B Register to B input
PIN 13
TRI-STATETM output in high Impedance state
TRI-STATE output in high impedance state
TRI-STATE output in high Impedance state
TRI-STATE output in high impedance state
TRI-STATE output in high impedance state
TRI-STATE output in high impedance state
TRI-STATE output connected to A Register
TRI-STATE output connected to B Register
Note 3: The output controls are sampled by H)
Logical LOW Level (VLl
Vss -1.5
Vss - 18.5
Clock Input Leakage
V", ~ -20.0V, TA ~ 25°C,
All Other Pins GND
Clock Input Capacitance
V", ~ O.OV, f ~ 1 MHz
All Other Pins GND
(Note 1)
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VoLl
ISOURCE ~ -0.5 mA
ISINK ~1.6 mA
Data Output Leakage
V OUT ~ -5.0V, T A ~ 25°C
Output in High Impedance State
Power Supply Current
TA ~ 25°C, VGG ~ -12V,
1Jpw ~ 150 ns, Vss ~ 5.0V,
V",L ~ -12V, Data ~ 0-1-0-1
0.01 MHz ~ 1J, ~ 0.1 MHz
1J, ~ 1.0 MHz
1J, ~ 2.5 MHz
IGG
Clock Frequency (ip,)
1Jt,
Clock Pulsewidth (1Jpw)
1Jtf + 1Jpw + 1Jt, ~ 10.5 ps
Clock Phase Delay Times (1Jd, ¢d)
(Note 2)
Clock Transition Times (1Jt,,1Jtf)
1Jtf + 1Jpw + 1Jt, ~ 10.5 ps
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
(Note 2)
~
1Jtf
~
20 ns, (Note 2)
Vss + 0.3
Vss - 14.5
0.05
140
2.4
1.60
5.3
10.3
0.01
3.3
0.15
1.0
160
V
V
/lA
pF
Vss
0.4
V
V
10.0
IlA
3.0
8.0
15.0
mA
mA
mA
2.5
MHz
10
10.0
IlS
ns
1.0
0.2
0.2
100
100
IlS
ps
IlS
Data Input Setup Time (t ds )
80
30
ns
Data Input Hold Time (tdh)
20
0
ns
Write Setup Time (tds)
80
30
ns
Write Hold Time (t dh )
20
0
ns
Read Setup Time (tRs)
0
ns
Read Hold Time (tRh)
0
ns
Data Output Propagation Delay
from 1JOUT
Delay to HIGH Level (t pd ,)
Delay to LOW Level (tpdO)
(see ac test circuit)
150
150
200
200
ns
ns
150
150
200
200
ns
ns
150
150
200
200
ns
ns
Propagation Delay From
Read Control Disable to
HIGH Impedance State:
Delay From HIGH Level (t'H)
Delay From LOW Level (t OH )
Propagation Delay From
Read Control Enable to
LOW Impedance State:
Delay to HIGH Level (t H ,)
Delay to LOW Level (tHO)
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of temperature and partial bit times (T I N and TOUT)
as shown by the <1>f versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TIN equal to TOUT. The
minimum gu.aranteed clock frequency:
1
t(min) ~ TIN + TOUT
where TIN and TOUT do not exceed the guaranteed maximums.
Note 3: Minimum clock frequency. and pa,rtial bit time curves are guaranteed by testing at a high
temperature point.
26
perforrt.ance characteristics
\
Guaranteed Minimum Clock
Frequency vs Temperature
, (Note 2)
....
Guaranteed Maximum TIN
and TOUT vs Temperature
(Note 2)
y
>
~ 10k
w
100
100
lOOk
=
:§
l'\..
10
10
I-
w
a:'
~ l.ok
:l
0
l-
j /"f
..=i
1,1
TIN=Tou~~ ~
Co)
g
~1~
~ 100
<"
.§
,~
1.0
..P
1.0 ~
~
xc:t
1 1
~
:IE
'"
0.1
Z
I
10 I '
-60
I
20
-20
I, I I
I
100
140
60
0.01
-60
AMBIENT TEMPERATURE (OC)
20
60
100
7.0
5.0
4.0
-n- --S5°C
6.0
Cl
=
0.1
0.001
0.01
0.1
1.0
10.0
CLOCK FREGUENCY, ¢f (MHz)
Typical Data Output Sink
Current vs Data Output
Voltage
12
8.0
.J!
140
Typical Data Output Source
Current vs Data Output
Voltage
9.0
<
.§
~l~
= 25°C
AMBIENT TEMPERATURE rC)
Typical Power Supply Current
vs Voltage
I--
r--
'.
-20
I
-55°C
~
Cl
~
:::)
L"
Co)
1>Pw - 150 ns
Vss - 5.oV
VGG = -12.oV
V",L = -12.oV
VI/>H = 3.5V
DATA" 0-1-0-1
y
~TI~ D~TO~T=12oolns 1/1/
a
!iii
Typical Power Supply Current
vs Clock Frequency
........ ........
- -12SoC
-
A
2.0
1,0
16
tS
18
17
~
4
a:
a:
Co)
w
a:
¢pw=15Ons
Vss = S.OV
VL = -12.oV
V",H = 3.5V
DATA = 0-1-0-1
3.0
I-
:::)
:: """T""=i50cl ¢f= I MH,z'
-
10
<
.§
Co)
Vss = 5.oV
VGG = -12.oV
'I-~+--+--+-- V¢L = -12.0V
:::)
0
Vol
VH = 3.SV
o ~~~--~--~--~~--~
5
19
~1
4
VOUT (V)
VOUT (V)
Vss - VGG (V)
Typical Tri-State Data Output
Capacitance vs Voltage
ac -test cir.cuit
truth table
SI
S2
Rl
tpdO
Closed
Closed
35K
20 pF
tpdl
Closed
Closed
35K
-20 pF
5 pF
DELAY
"-r---
tOH
Closed
Closed
25K
t'H
Closed
Closed
25K
5 pF
tHO
Closed
Open
35K
20pF
tHl
Open
Clored
35K
20 pF
TA =25°C
Test freq. = 1 MHz
All Other Pins GND
I
I
-1
4
VOUT (V)
switching time waveforms
~
t, \::.--.,,-----.£f
----~~,
- j ',.
The level of the output when it is m the high impedance state is
determined by the external circuitry. The correct data will always
appear, after$Ome proplP,tion delay, when the read control is
enabled. The guaranteed delay from the high impedance state to
the low impedance state requires that the reid control isenablad
on or before the leading edge Of ¢lOUT-
Cl
;.'1-
'--_______..Jy:;-
Dynamic Shift Registers
MM4015A/MM5015A triple 60+4 bit accumulator/register
general description
The MM4015A/MM5015A triple 60+4 bit dynamic
accumulator is a monolithic MOS integrated circuit utili~ing P-channel enhancement mode 10Vli
threshold technology. The device consists of three
independent shift registers with logic to control
the entry of external data or to recirculate the
data stored in that register. A common two phase
clock is required to operate the device.
•
Low frequency operation
250 Hz at 25°C
guaranteed
•
Low power consumption
0.4 mW/bit
typically at 1 MHz
•
Recirculate logic on-chip
•
BCD correction look ahead tap
applications
features
•
•
•
No p.ull-up
or pull-down
resistors requ ired
Data storage registers in BCD arithmetic applications
•
Basic accumulator functions
•
Business machine memory applications
2.5 MHz guaranteed
•
Recirculating delay line
Direct DTL and TTL compatibility
High frequency operation
connection diagram
Dual-In-Line Package
INPUT 1
16 VGG
1
.------1f--150UTPUT1A
LOAD CONTROL 1 2
OUTPUT 18 J
-+-_____= - - - - - - - '
14 OUTPUT 2A
13 OUTPUT JA
INPUT 2 4 -l--------4'--,
12
LOAD CONTROL 2 5
('OUT
OUTPUT 28 6
10 OUTPUT 38
INPUT J 7
L''======:::_\-_
Vss 8
9 LOAD CONTROL 3
Note Pm8 cOllllected to case.
TOPVIEW
typical applications
Typical Arithmetic Configuration
TTL/MOS Interface
r
-I~
TT(/DTL
,
r
I I
28
______
'Iss______ , r-l~l
MM4015AIMM5015A
TTl/DTl
I I
I
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4015A
MM5015A
Storage Temperature Range
Vss + O.3V to Vss - 22.0V
-55°e to +125°e
0
,...25°e to + 70 e
o
-65°e to +150 e
electrical characteristics
= 5.0V ±5%,
T A within operating temperature range, Vss
PARAMETER
VGG
CONDITIONS
= -12.0V ±1O%, unless otherwise stated
MIN
Data I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (Vld
TYP
Vss - 2.0
Vss - 18.5
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data I nput Leakage
V IN = -20.0V, T A = 25°C,
All Other Pins GND
0.01
0.5
J.l.A
Data I nput Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND
3.0
5.0
pF
See Note 2
Load Control I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (Vld
Vss - 2.0
Vss - 18.5
Vss + 0.3
Vss - 4.2
V
V
Load Control Input Leakage
V IN = -20.0V, T A = 25°C,
All Other Pins GND
0.01
0.5
J.l.A
Load Control I nput Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND
See Note 2
3.0
5.0
pF
Clock Input Levels
Logical HIGH LeveI(Vet>H)
Logical LOW Level (Vet>L)
Clock Input Leakage
Vet> = -20V, T A = 25°C,
All Other Pins GND
Clock Input Capacitance
Vet> = O.OV, f = 1 MHz,
All Other Pins GND
See Note 2
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VOL)
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss - 18.5
0.05
45.0
2.4
IsOU RCE = -0.5 mA
ISINK = 1.6 mA
V
V
1.0
J.l.A
60.0
pF
Vss
V
0.4
V
Power Supply Current
TA = 25°C, VGG = -12V,
et>pw = 150 ns, Vss = +5.0V,
VL =-12V,Data=0-1-0-1
IGG
0.01 MHz ~ et>f ~ 0.1 MHz
2.2
3.0
mA
1 MHz
4.5
5.5
mA
et>f = 2.5 MHz
7.0
8.5
mA
3.3
2.5
MHz
et>f =
= 20 ns, Note 1
Clock Frequency (<1>f)
tr = tf
Clock Pulsewidth (et>pw)
tf + pw + et>tr ~ 10.5 J.l.S
Clock Phase Delay Times (et>d, ¢d)
Note 1
Clock Transition Times (et>t r, et>tf)
et>tf + et>pw + et>tr ~ 10.5 J.l.S
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
Note 1
0.01
10.0
0.15
J.l.S
ns
10
1.0
100
100
0.20
0.20
J.l.S
J.l.s
J.l.S
Data Input Setup Time (~.)
80
Data Input Hold Time (tdh)
20
Load Input Setup Time (tl.)
80
30
ns
Load Input Hold Time (tlh)
20
o
ns
ns
30
o
ns
Data Output Propagation Delay
From et>OUT
Delay to HIGH Level (tpdH)
Delay to LOW Level (tPdd
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit times, TI N and TOUT,
as shown by the (/>t versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TIN equal to TOUT. The
minimum guaranteed clock frequency is:
1
y
zw
!
or TouT 200 ns
x: V
1.0
:::0
d
I:::l
a:
....
::.:
" '"TIN = TouT-
V V
0.1
y
3.0
~
10
<"
0
I-
./I
II""
y
f--
'"
Z
..=
-
:a:
:::0
:a:
.......
1.0
~
,
'"
::!1
Z
i
0.01
0.1
-60
-20
20
60
100
140
-60
-20
60
20
0.3
"
100
Power Supply Current
vs Voltage
'~
-'
'-.-55°C
TA = 25° C
~125°e
0.1
140
'Vss = 5.OV
VGG = VtjJL = Vss -12.oV f
¢PW = 150 ns
DATA PATTERN: 1-0-1-0
LOAD CONTROL = Vss
=
=
-
-
III
0.01
0.001
AMBIENT TEMPERATURE (Oe)
AMBIENT TEMPERATURE ee)
-
~
1.0
~
-
.2
x<
::!1
:::0
2-
=,.
10.0
'-
:iE
1=
-w
3
Power Supply Current vs
Clock Frequency
0.1
1.0
10.0
eLOCKFREaUENC~~(MHd
Data Output Source
Current vs Voltage
Data Output Sink
Current vs Voltage
6.0 r-----"T""".......,..-..---r'---..,,....-...
tjJf= 1 MHz
12
Vss =+5.oV
10 I--_I--_I--~I--_ VGG = -12.oV
VtjJL = -12.oV
5.0
<"
..s
CJ
4.0
J:
3.0
2.0
15
16
17
18
19
4
2
1
OUTPUT VOL rAGE (V)
Vss - VGG (V)
switching time waveforms
-1
4
1.
OUTPUT VOLTAGE (V)
ac test circuit
DATA INPUT/LOAD INPUT
'5V
4Kfl
OOUT
CLOCK
~"'.Lt
DATA O U T P U T _
1.5V
30.
-1
"'.J:-H
'-_ _ _ _ _ _ _ _..J
.
·1.5V
-1
Dynamic Shift Registers
MM4016/MM5016 512-bit dynamic shift register
general description
• Military and Commercial' Temperature Ranges
MM4016
-55°C to +125°C
MM5016
-25°C to +70°C
The MM4016/MM5016 512-bit dynamic shift register isa monolithic MOS integrated circuit utilizing P channel enhancement mode low threshold
technology to achieve bipolar compatibility. An
input tap provides the option of using the device
as either a 500 or 512-bit register.
•
Low power dissipation
< 0.17 mW/bit
at 1 MHz max.
30 J,lW/bit
at 100 kHz typo
<
features
•
Bipolar compatibility
•
Package option
•
Fewer clock drivers required
•
System flexibility
+5V, -12V operation
No pull-up or pull-down
resistors required.
TO-l00 or choice of two
Dual-I n-Line Packages
applications
• Glass and magnetostrictive delay line replacement.
• CRT refresh memory.
Clock line
capacitance of
100pFtyp
• Radar delay line.
300 Hz guaranteed min.
operati ng frequency at 25° C.
500 or 512-bit register length.
• Drum memory storage (silicon store)
•
Long serial memory.
connection diagrams
Metal Can Package
Dual-I n-Li ne Package
Dual-In-Line Package
NC
VGG
512·INPUT
OUTPUT
Vss
Note: Pin 5 connected to case.
(l,N
500·INPUT
Vss
90UT
TOP VIEW
TOP VIEW
,
"
typical application
TT LIMOS
Interface
+5V
--------..,
Vss
I
I
I
I
I
I
L _____ -
MM4016/MM5016
I
TV;G----,--...J
-12V
Note: The unused input pin must be connected to Vss.
31
CD
.-
0
Lt)
absolute maximum ratings
~
~
Voltage at Any Pin
Operating Temperature Range
.........
CD
.-
Vss + 0.3V to Vss -22V
~55°C to +125°C
-25°C to +70°C
-65°C to +150°C
MM4016
MM5016
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
0
~
.~
300°C
electrical characteristics
~
T A within operating temperature range, Vss
PARAMETER
= +5.0V ±5%, V GG = -12.0V ±10%, unless otherwise specified.
CONDITIONS
Data I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (V IL )
TYP
Vss - 2.0
Vss - 18.5
Data Input Leakage
V IN = - 20V, T A = 25°C,
All Other Pins GN D
Data I nput Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND, (Note 2)
Clock I nput Levels
Logical HIGH Level (V,pH)
Logical LOW Level (V <'t>L)
V¢ = -20V, T A = 25°C,
All Other Pins GND
Clock I nput Capacitance
V¢ = O.OV, f = 1 MHz,
All Other Pins GND, (Note 2)
ISOURCE = -0.5 mA
ISINK = 1.6 mA
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
0.01
0.5
p.A
3.0
5.0
pF
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss - 18.5
Clock I nput Leakage
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod
MIN
0.05
100
2.4
1.0
120
Vss
0.4
V
V
J.,LA
pF
V
V
Power Supply Current
IGG
T A = 25°C, VGG = -12V,
¢pw = 150 ns
Vss = 5.0V, V¢L = -12V,
Data = 0-1-0-1
0.01 MHz ~ ¢f ~ 0.1 MHz
1.0
2.0
mA
= 1 MHz
= 2.5 MHz
3.5
5.0
.rnA
7.0
10.0
mA
3.3
2.5
MHz
¢f
¢f
Clock Pulsewidth (¢pw)
= ¢tf = 20 ns, (Note 1)
¢tf = ¢pw + ¢tr ~ 10.5 J.,LS
Clock Phase Delay Times (¢d, ¢d)
(Note 1)
Clock Transition Times (¢t r , ¢tf)
¢tf + ¢pw + ¢tr ~ 10.5 J.,LS
Partial Bit Times (T)
(Note 1)
Clock Frequency (¢f)
¢tr
0.15
Data Input Setup Time (tds )
Data Input Hold Time (tdh)
J.,Ls
1
J.,LS
100
100
J.,LS
J.,Ls
ns
80
30
ns
20
0
ns
See ac test circuit.
150
150
Note 1: Minimum clock frequency is a function of temperature and partial bit times, TIN and TOUT,
as shown by the ¢f versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TIN equal to TOUT. The
1
minimum guaranteed clock frequency is: ¢f(min) =
, where TIN and TOUT may not
TIN + TOUT
exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by statistical lot sample testing.
32
10
10
0.20
0.20
Input Partial Bit Time (TIN)
Output Partial Bit Time 'TOUT)
Data Output Propagation Delay
from ¢OUT
Delay to HIGH Level (tpdH )
Delay to LOW Level (tpdd
0.01
200
200
ns
ns
performance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 1)
Guaranteed Maximum TIN
and TOUT vs Temperature
(Note 1)
10K
g
5K
>~
(.)
2K
~ 1K
r-rr-r-
MM501S "'5-=~~-r-~-t7'9-~--+--I
-
"-!F, ... ,...
~IY;
200
:l
100
:::l
...t.
/?~
TIN
or TOUT
:E
50
20
10
5.0
Z
""~TIN-ToUT=
..=
==
x==
=200 ns
Il-
3.0
"
c:C
==
IL
-SO
-20
100
1.0
~
-so
-20
TEMPERATURE re)
20
so
100
140
<
I-
~
a:
a:
2.5
(.)
2.0
CI
0.01
.§
~
::;)
(.)
I--
<"
.§
.§ 3.0
CI
.2
¢ipw= 150ns
Vss =5.0V
VGG = -12.0V
V¢iL = -12.0V
DATA = 0-1-0-1
'"''
0.10
1.0
10.0
-
Typical Data Output Sink
Current vs Voltage
I-
3.5
l-
..... ~
=
t--
I--
~~
~~
"J
eLDeKFREQUENe~~(MHd
Typical Data Output Source
Current vs Voltage
5.0 r---=-:":"!':--,....~-:'::':":'~-r-...,
¢i,= 1 MHz
4.5
¢ipw = 150 ns
Vss= 5.0V
4.0
~~
'-
0.1 "0.001
TEMPERATURE re)
Typical Power Supply
Current vs Voltage
<"
I-
~~
0.3
MM501S~ ji.,.MM401S=
I
."1. I
0.5
140
.§ 1.0 I::::
CI
~~
.2
l-
'"I"'
2.0
0.1
so
. 20
=tm1tJ~-55oe
II
- TA = 25°e
125°e
<"
0.2
20
10
I'I-
::;)
(.)
==
::;)
==
Z
i....
0
I-
L
~
50
::;)
~
10.0 F""
100
MM4016
fficr; soli
(.)
Typ~~Pow~Sup~y
Current vs Clock Frequency
a:
a:
::;)
(.)
w
:00:
2
1i)
a:
::;)
CI)
1.5
4
Vss = 5.0V
VGG = -12.0V
V¢iL = -1.~.OV
1.0
15
lS
17
18
19
-1
4
-1
V OUT (V)
Vss - VGG (V)
ac test circuit
switching time waveforms
DATA INPUT
+5V
4K
IP1NCLOCK
IPOUT
CLOCK
- -","t
DATA OUTPUT
1.5V
"d~
'-_ _ _ _ _ _ _- - - '
1.5V
i33
Dynamic Shift Registers
MM4017/MM5017 dual 512-bit dynamic shift register
general description
The MM4017/MM5017 dual 512-bit dynamic shift
register is a monolithic MOS integrated circuit
utilizing P channel enhancement mode low threshold technology to achieve bipolar compatibility.
An input tap provides the option of using either
register in a 500-bit or 512-bit configuration.
•
System flexibility
•
Military and Commercial Temperature Ranges
MM4017
-55°C to +125°C
MM5017
-25°C to +70°C
features
•
Low power dissipation
•
Standard +5V, -12V supplies
Bipolar compatibility. No pull-up
or pull-down
resistors requ ired.
•
Package option TO-1 00 or Dual-I n-Line Package.
•
F ewer clock
drivers required
400 Hz guaranteed
min. operating frequency
at 25° C. 500 or
512-bit register length.
<0.17 mW/bit
at 1 MHz max.
< 30 pW/bit at
100 kHz typo
applications
Clock line
capacitance of
140 pF typo
•
Glass and magnetostrictive delay line replacement
•
CRT refresh memory
•
•
Radar delay line
Drum memory storage (silicon store)
•
Long serial memory
connection diagrams
Metal Can Package
Dual-I n-line Package
Vss
TOP VIEW
TOP VIEW
typical applications
1000 or 1024 Bit Accumulator
RECIRCULATEIWRITE---I~----L.-J
OA~~_t--'--_ _-L_--1
TTL/MOS Interface
1
I 1
MM4011IMM5011
JI
L----l~Vo"G-----
L-1,:"-J
OTLffiL
-12V -10%
Note: Unused input(s) should be tied to Vss.
34
I
)
s:
s:
absolute maximum ratings
Voltage at Any Pin
Vss
Operating Temperature MM4017
MM5017
Storage Temperatu're
Lead Temperature (Soldering, 10 sec)
~
...0
+ 0.3 to Vss - 22
-55°C to +125°C
-25°C to +70°C
-65°C to 150°C
300°C
"3:'"
3:
electrical characteristics
TA
(,J1
...
0
within operating temperature range, Vss = +5.0V ±5%, VGG = -12.0V ±10%, unless otherwise specified.
-...I
CONDITIONS
PARAMETER
MIN
Data I nput Levels
LogiCal HIGH Level (V IH )
Logical LOW Level (V IL )
TVP
Vss - 2.0
Vss -18.5
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data I nput Leakage
V IN = -20V, T A = 25°C,
All Other Pins GND
0.01
0.5
JJ.A
Data Input Capacitance
V IN = OV, f= 1 MHz,
All Other PinsGND
3.0
5.0
pF
Clock I nput Levels
Logicc;l1 HIGH Level (VC/>H)
Logical LOW Level (V C/>L~
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss -18.5
Clock I nput Leakage
Vcp = -20V, T A = 25°C,
All Other Pins GND
Clock I nput Capacitance
Vcp=OV,f= 1 MHz,
All Other Pins GND
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VoLl
0.05
140
2.4
ISOURCE = -0.5 mA
ISINK = 1.6 mA
1.0
160
Vss
0.4
V
V
JJ.A
pF
V
V
Power Supply Current
T A = 25°C, VGG = -12V, ¢pw = 150 ns
Vss = 5.0V, V,pL = -12V,
Data = 0-1-0-1
0.01 MHz ~ ¢f ~ O. ~ MHz
IGG
¢f =
>
1 MHz
¢f = 2.5 MHz
Clock Frequency (¢f)
¢t r = ¢tf
Clock Pulsewidth (¢pw)
=
20 ns, Note 1
¢tf + ¢pw + ¢tr
-
Clock Phase Delay Times (¢d, ¢d)
Note 1
Clock Transition Times (¢trr ¢tf)
¢tf + ¢pw + ¢t r
~
10.5 /.lS
0.01
3.2
mA
10.5
mA
10.0
14.0
mA
2.5
MHz
3.3
10
0.15
~
10.5 /.lS
0.20
0.20
Data Input Setup Time (tds)
Data I nput Hold Time (tdh )
JJ.S
ns
10
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
Data Output Propagation Delay
from ¢OUT
Delay to HIGH Level (tpdH)
Delay to LOW Level (tpdd
I
2.1
7.0.
1.0
/.lS
Note 1
Note 1
/.lS
JJ.S
80
30
ns
20
0
ns
See ac test circuit
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit time, TIN and TOUT,
as shown by the cf>f versus temperature and TIN, TOUT versus temperat\Jre curves. The lowest
guaranteed clock' frequency for any temperature can be attained by making TIN equal to TOUT.
The minimum guaranteed clock frequency is:
cf>f(min)
=
TIN + TOUT
where TIN and TOUT may not exceed the guaranteed maximums.
Note 2: The curves are guaranteed by testing at a high temperature point. '
Note 3: Capacitance is guaranteed by periodic testing.
35
performance, characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Notes 1 and 2)
Guaranteed Maximum
TIN and TOUT
(Notes 1 and 2)
100k
Typical Power Supply
Currerit vs Clock Frequency
100
100
=
N
>
~ 10k
1
J
1
~ ETINORTouT
:g
/ V
1,.1
200ns
~
/~
t.:I
TIN
, ,
~
t.:I
~
~
::::I
:;;
10
-60
-20
'"
c:(
,
~
1.0
:;;
:;; 0.1
:!:
2
..=
X
'r'f'
~ 100
I"
2
TOUT~
20
60
100
0.01
-60
140
AMBIENT TEMPERATURE (DC)
Typical Power Supply
Current vs Voltage
-20
20
60
100
140
6.0
0.1
1.0
10.0
Typical Data Output Source
Current vs Data Output Voltage
Typical Data Output Sink
Current vs Data Output Voltage
12
11::'""-.---....--.---.---.,.----,
10
~
.§
5
I---I---:l~-t:::.....,--+--+-,
~
.§ 5.0 1-::.ioo'=-II---+----1-+--+-+_--I
0.01
CLOCK FREQUENCY, ::>
::::I
" "-
4
a:
a:
::::I
t.:I
(!l
w
.2 4.0 1--+--i~-+----1-
t.:I
a:
::::I
o
3.0 1---1----11---1---1-
CI)
2.0 I--+--+--II--+1.0
1...-.........- - - ' ' - -..........--'_....1----'"_....1..---1
15
16
17
18
19
Vss - VGG (V)
switching time waveforms
4
-1
-1
VOUT (V)
VOUT (V)
ac test circuit
+5V
DATA INPUT
4K~!
"'IN
CLOCK
. DATA OUTPUT
------------------
36
3:
3:
Dynamic Shift Registers
~
o
.....
00
.......
3:
3:
U'1
o.....
MM4018/MM5018 triple 64 ·bit
dynam ic shift reg ister
00
general description
The MM4018/MM5018 triple 64-bit dynamic shift
register is a monolithic MOS integrated circuit
utilizing P-channel enhancement mode low threshold technology to achieve bipolar compatibility.
features
•
Bipolar compatibility
Guaranteed minimum
operating frequency of
600 Hz at 25°C
•
System flexibility
•
Military and commercial temperature ranges
MM4018
-55°C to +125°C
MM5018
-25°C to +70°C
applications
•
+5V, -12V operation
No pull-up or pull-down
resistors required
Calculator storage register
•
CRT refresh memory
•
Serial data storage.
connection diagram
Metal Can Package
Vss
TOP VIEW
typical application
TTL/MOS Interface
+5V
-,
Vee
r- -,
Vee
5 Vss
64·BITS
64·BITS
64·BITS
-12V
37
absolute maximum r~tings
Voltage at Any Pin
Operating Temperature Range. MM4018
MM5018
Storage Temperature Range
Lead Temperature (Soldering, ~O sec)
Vss + O.3V to Vss - 22.0V
-55°C to +125°C
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
(T A within operating temperature; range,
Vss = +5.0V ±5% and VGG == -12.0V ±10%, unless otherwise specified.)
PARAMETER
CONDITIONS
Data I nput Levels
Lo~ical High Level (V IH )
Logical Low Level (V IL )
MIN
TYP
Vss - 2.0
Vss - 18.5
Vss + 0.3
Vss - 4.2
UNITS
v
V
Data I nput Leakage
V IN = -20V, T A = 25°C,
All other pins GN D
0.01
0.5
J.1A
Data Input Capacitance
V'IN "" O.OV, f = 1 MHz,
All other pins GND
3.0
5.0
pF
Vss + 0.3
Vss - 14.5
V
V
Clock Input Levels
. Logical High Level (VH)
Logica~ Low Level (VipLl
Vss - 1.5
V ss - 18.5
'Clock Input Leakage
VI = -20V, T A = 25°C,
All other pins GND
Clock Input Capacitance
VI'" O.OV, f = 1 MHz,
All other pins GND
Data Output Levels
Logical High Level (V OH )
Logical Low Level (VoLl
ISOURC~ = -0.5 rnA
ISINK = 1.6 mA
Power Supply Current (IGG)
0.05
45
2.4
TA = 25°C, V GG :;: -12V,
pw = 0.15 J.1S, V1:.. = -12V
0.01 MHz ~ f.~ 0.1 MHz
f:;: 1 MHz
f = 2.5 MHz
2.9
t r =' tf ,,;, '20 IlS (Note 1)
0.01
Clock Pulsewidth (pw)
tf + pw + t r ~ 10.5 fJ.S
0.15
Clock Phase Delay Times (o or d)
Note 1
Clock Transition Times
Risetime (t r )
Falltime (¢tf)
tf + pw + t r ~ 10.5 fJ.S
tf + pw + t r ~ 10.5 fJ.S
1.0
60
3.3
pF
0.4
V
4.5
5.5
7.0
mA
rnA
rnA
2.5
MHz
10
10
Note 1
J.1A
V
Vss
3.8
5.8
Clock Frequency (f)
Partial Bit Times
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
fJ.S
ns
0.20
0:20
2
2
}1S
100
100
fJ.s
fJ.s
}1
Data Input Setup Time (tds) ,.
?O
30
ns
Data I nput Hold Time (tdh)
20
o
ns
Data Output Propagation
Delay from ouT
Delay to Output High Lev~1 (tpdH)
Delay to Output Low Level (tpdLl
See AC TestCircuit
150
150
Note 1: Minimum clock frequency is a function of temperature and) partial bit times (TI N and TOUT)
as shown by the ¢t versus temperature and TI N, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TI N equal to TOUT. The
.
1
minimum guaranteed clock frequency:
c:t
2.0 I---+-+---+-+-- ¢pw =150 ns
2.0
Vss =+5V
o
-25
75
25
1.0
0.001
125
TEMPERATURE (OC)
0.1
0.01
1.0
1.5 r..--+-t--+--t-- V¢ L = -12V
DATA =1·0·1·0
1.0
19
15
16
18
17
10.0
CLOCK FREQUENCY ¢I (MHz)
Guaranteed Maximum TIN
and TOUT vs Temperature
Vss - VGG (V)
Data Output Sink Current
vs Data Output Voltage
Data Output Source Current
vs Data Output Voltage
100
!....
:::l
....0
10
12
ct
.5
~
c:
a:
i
..=
"'"
:E
;:)
:E
xc:t
10
....
'\
1.0
:E
::::0
c..>
:.::
2!
"
en
....
....~
;:)
"'0.1
-60
-20
20
60
0
"
100
TEMPERATURE (OC)
o ~--~--~~~--~--~--~
140
-1
5
-1
VOUT (V)
VOUT (V)
Guaranteed Minimum Clock
Frequency vs Temperature
10
'N
~
f - - TIN
>
DR
TOUT
= 200 ns
~
~
::::0
~
~
" 10"
:.::
~
-'
~
)~ I"
La
~
::
"
I" ~
0.1
TIN
= TOUT
:E
::::0
:E
2
SE
0.01
-60
-20
20
60
100
140
TEMPERATURE (OC)
timing diagram
ac test circuit
Vss
4K
tP'NClOCK
oouTClOCK
------.1
Vss-15V
VS:$-14.SV
39
Dynamic Shift Registers
MM4020/MM5020 quad SO-bit dynamic shift register
MM4021/MM5021 triple SO-bit dynamic shift register
o
oit)
N
general description
The MM4020/MM5020, and MM4021/MM5021
shift registers are monolithic MOS integrated circuits utilizing P-channel enhancement mode low
threshold technology to achieve bipolar compatibility. The MM4021/MM5021 is a metal mask
option of the MM4020/MM5020 which eliminates
one of the 80-bit registers. Power and clock capacitance are reduced proportionally.
~
~
........
o
N
o
~
~
~
System flexibility
•
Military and commercial temperature ranges
MM4020, MM4021
-55°C to +125°C
MM5020, MM5021
-25°C to +70°C
applications
features
•
Guaranteed minimum
operating frequency of
250 Hz at 25°C
•
Bipolar compatibi I ity
+5V, -12V operation
No pull-up or pull-down
resistors required
•
Calculator storage register
•
CRT refresh memory
•
Serial data storage
connection diagrams
Dual-In-Line Package
Metal Can Package
Dual-In-Line Package
H)
Logical LOW Level (V",L)
~
o
UNITS
o
....
N
V
V
J1A
90
70
pF
pF
Vss
0.4
V
V
Power Supply Current
IGG
T A = +25°C, VGG = -12.0V,
¢pw = 150 ns, Vss = +5.0V,
V¢L = Vss - 17.0V, Data = 0-1-0-1
MM4020/MM5020
0.01 MHz::;: 9f::;: 0.1 MHz
f::;: 0.01 MHz
¢f = 1.0 MHz
¢f = 2.5 MHz
2.9
6.4
10.1
2.2
4.8
7.7
Clock Frequency (CPf)
tr = ¢tf = 20 ns (Note 1)
0.01
Clock Pulsewidth (OUT
Delay to HIGH Level (tpdH)
Delay to LOW Level (t Pdt.!
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit time, TIN and TOUT,
as shown by the f(min) =
TIN + TOUT
where TIN and TOUT may not exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by periodic testing.
41
performanc.e cha'ra~teristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 1)
Guaranteed Maximum Partial
Bit Times vs Temperature
(Note 1)
100
40.0
10
....
~
]
t-
:>
0
"10
ai
::::I
z
:!;
it)
:!;
x
o
1.0
I--- f--
::::I
:!;
I
o
2
I
-20
20
60
100
5.0
:E
'-
0.1
-60
..........
I'TIN = TouT -
:!;
c(
~
~
V V
0.1
0.01
140
-60
-20
AMBIENT TEMPERATURE (OC)
20
/,
rJ,
1
-' -'
..,::.:
::..,
I,
::::I
:!;
... V V
~
..=
N
or TouT - 200 ns
1.0
~
~
o
~
Typical Power Supply Current
vs Clock Frequency
60
100
ioI'
IIII'I"IIT!'
rMI~5°~ ,
111111111'1
111111111
I
1111111
1111111
0.0,1
0.001
140
AMBIENT TEMPERATURE (OC)
f
,.
0.1 '
I
I
1.0
10.0
CLOCK FREQUENCY (MHz)
N
o
~
Typical Data Output Source
Current vs Data Output
Voltage
Typical Power Supply Current
vs Voltage
~
~
Typical Data Output Sink
Current vs Data Output
Voltage
28.0 ,--,--,--,----,--,----;-,,--,
26.0
:.::; 22.0
II:
II:
::::I
::t
ai
I-----+---~""""''---If_---+--___t---+..~
20.0
~4---------~t=----+-L
CJ
~
18.0
.§
.§
~
3
~
~
I-----+---~-__+__-
24.0
, 9f= 1.0MHz
16.0 F-----+-::..",...."'-=~-+-9pw= 150ns
Vss = 5.0V
14.0 I-----+--------j-+_ -----V,'L ='-12.0V
DATA = 1-0-1-0
12.0 L---L.........;L...-....I....---l_...l...----I._...L...---I
15.0
16.0
17.0
18.0
19.0
..,
~
,ai
II:
II:
4
B
..,w
::.:
2
en
II:
::::I
~
~
::::I
~
~
a..
~
Vss = 5.0V
VGG = -12.0V -+--+---I--~
V= -20.0V
All other pins
GND. T A = 25°C
kHz
kHz
10
fls
<.
1-'>
2
flS
Trailing edge
2
flS
2
fls
IlL
Input Leakage Current
5.0
flA
CIS
Input Capacitance (Data)
7
pF
C ise
Input Capacitance (Clock)
18
pF
Parallel Output Leakage
Current
40
flA
VL=-55V
Vss = GND
Dynamic Shift Registers
MM4104/MM5104 dynamic shift register
general description
The MM4104/MM5104 360/359, 228/287, 40/32
bit dynamic shift register is a monolithic MOS
integrated circuit utilizing p-channel enhancement
mode low threshold technology to achieve bipolar
compatibil ity. The register lengths are lengthened
or shortened by hard wiring the length select line
to V GG or Vss. The lengths available are: 40,
288, 328, 360, 400, 560, 688; or 32, 287, 319,
•
Multiple length registers
Electrically adjustable
360/359, 288/287, 40/32 bit
registers
•
Wide frequency range
250 Hz min. guar.
at25°C
2.5 MHz max. guar.
over temp.
359, 391, 446, 678.
features
applications
+5V, -12V power
supply. No pull-up
or pull-down
resistors requ ired
• ,DTLlTTL compatibility
•
Data store
•
CRT displays
•
Business machine
connection diagram
Metal Can Package
DATA OUTPUT 2
(40/32 OUT)
DATA INPUT lA
(360,288 IN)
Vss
TOP VIEW
typical applications
TTL/MOS Interface
+5V
r
L,
r------ - - - 17'
I
I I
L2T~T!;J
L __ -
_.t_
3 - - - - _~M~4~~:=
(SHORT) 0 0 (LONG)
VGG I Vss
+5V
-12V
-
-9f a l--- -
_.J
¢'N
NOTE:
VGG on pin 3 results in a 288·bit register
between pin 7 and pin 4 and a 287·bit
register between pins 6 and 4. The unused
input (6 or 7) must be returned to Vss.
Also, there is a 32·bit register between
pins 1 and 2.
Vss on pin 3 results in a 360·bit register
between pin 7 and pin 4 and a 359·bit
register between pins 6 and 4. The unused
input (6 or 7) must be returned to Vss.
Also, there is a 40·bit register between pins
1 and 2.
45
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range M'M4104
MM5104
Storage Temperature Range
Lead T~mperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22V
-55°e to 125°e
0
-25°C to 70 e
0
-65°e to 150 e
300°C
electrical characteristics
(T A within operating temperature range, Vss
PARAMETER
= +5.0V, ±5%, VGG = -12.0V ±10%, unless otherwise specified.)
CONDITIONS
Data Input Levels
Logical HIGH Level (V IH )
Logical LOW Level (Vld
MIN
TYP
MAX
Vss + 0.3
Vss -4.2
Vss - 2.0
Vss - 18.5
UNITS
V
V
Data I nput Leakage
VIN = -20.0V, T A:; 25°C,
All Other Pins GND
0.01
0.5
pA
Data I nput Capacitance
VIN = O.OV, f = 1 MHz,
All Other Pins GND, (Note 3)
3.0
5.0
pF
+ 0.3
V
V
Length Select Input Levels
Logical HIGH Level (V LSH )
Logical LOW Level (V Lsd
Vss
Vss
Vss - 18.5
VGG
Length Select Input Leakage
VIN :; -20V, T A:; 25°C,
All Other Pins GND
0.01
0.5
pA
Length Select Input Capacitance
VIN :;'O.OV, f = 1 MHz,
All Other Pins GND, (Note 3)
6.0
9.0
pF
Clock I nput Levels
Logical HIGH Level (VepH)
Logical LOW Level (V cpL)
Clock I nput Leakage
Vep = -20V, T A = 25°C,
All Other Pins GND
Clock I nput Capacitance
Vep=O.OV,f= 1 MHz,
All Other Pins GND, (Note 3)
Data Output Levels
logical HIGH Level (V OH )
•
.
_ _ : __ ,
.
.
.
I
"""
1
_. __ I
.
.
1\ I
Vss + 0.3
Vss - 14.5
Vss-l.5
Vss -18.5
1.0
0.05
85
2.4
ISOURCE = -0.5 mA
100
V
V
pA
pF
V
Vss
\
"
A
Power Supply Current
TA = 25°C, VGG = -12V, ¢pw = 150ns
Vss = 5.0V, VepL = -12V, Data = 0-1-0-1
IGG
1.5
-2.5
mA
·1 MHz
3.5
5.0
mA
¢f = 2.5 MHz
7.0
10.0
mA
3.3
2.5
MHz
0.01 MHz::::;: f::::;: 0.1 MHz
¢f =
¢t r
Clock Pulsewidth (¢pw)
¢tf + ¢pw + ¢t,.::::;: 10.5 ps
:;
¢tf
= 20 ns, (Note 1)
Clock Frequency (¢f)
Clock Phase Delay Times (¢d. ~d)
(Note 1)
Clock Transition Time (¢tr, ¢tf)
¢tf + (ppw + ¢t r ::::;: 10.5 ps
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
(Note 1)
0.01
10
0.15
10
ns
ps
0.20
100
0.20
100
ps
ps
Data Input Setup Time (t ds)
80
30
ns
Data Input Hold Time (tdh)
20
o
ns
Data Output Propagation. Delay
from ¢OUT
See ac test circuit.
Delay to HIGH Level (tpdH)
Delay to LOW Level (tpdd
150
150
200
ns
200
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit times, TIN and TOUT,
as shown by the ¢f versus temperature and TIN, TOUT versus temperatur.e curves. The least guaranteed
clock frequency for any temperature can be attained by making TIN equal to TOUT. The minimum
guaranteed clock frequency is:
1
¢f (min) '"
TIN
+ TOUT
where TIN and TOUT may not exceed the guaranteed maximum.
Note 2: The curves are guaranteed by testing at a high temperature point.
Note 3: Capacit~nce is guaranteed by periodic testing.
46
ps
performance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Notes 1,2)
Guaranteed Maximum TIN
and TOUT vs Temperature
(Notes 1,2)
100
10
:Z
ffi
::I
or
TOUT
1.0
3.0
::I
c.>
"-
1.0
~
cc
-~5~~1 -~
V /
0.1
1.0
<.!l
II'" TIN = TOUT- r - -
20
Z
Vss = 5.0V
VGG'=-12.0V
, V¢L= -12.0V
DAT~,~ 0-1-0-1
~
~
"-
100
60
r- ¢pw = 150 ns
:2
""...."
-20
8~
0.3
::I
0.1
-60
125°C
f-f--
.!?
:2
:2
TA = 25°C\
~
..§
/
:..:
II
lUll
200 ns
. ."V V
~
:2
x
11111
TIN
8
..=
:2
r-
~
"
I-
::l
10.0
10
~
.§
0
I-
Typical Power Supply
Current vs Clock Frequency
0.1
0.001
0.01
140
TEMPERATURE (OC)
-60
-20
20
60
100
140
0.10
1.0
10.0
Typical Output Sink
Current vs Voltage
Typical Output Source
Current vs Voltage
Typical Power Supply
Current vs V GG
0.01
CL,DCK FREQUENCY, ¢,(MHz)
AMBIENT TEMPERATURE rC)
5.0
~
4.5
..§ 10 """=-I------'1......:--t--:
I-
4.0
~
..§
ffi
a:
a:
3.5
~
:..:
3.0
;::
(i;
<.!l
.!?
2.5
l-
i'.:
¢ipw = 150 ns
2.0 t----t--t----t-----1r- Vss = 5.0V
Vq,L=-12.0V
1.5 t----t--t---I-----'r- DATA = 0-1-0-1
I-
::I
o
o
1.0
15
16
-1
19
18
17
-1
5
V OUT (V)
Vss - VGG (V)
switching time waveforms
ac test circuit
DATA INPUT/LOAD INPUT
+5V
4KH
EITHER
DATA
OUTPUT
o---4~--4"""""""""+-I"'''''''''''''
Q1NCLOCK
":>OUT
CLOCK
Vss-14.5V
i
-4
DATA OUTPUT
tpdLt
-------------------15V
"""r1/
~______________~~
47
Dynamic Shift Registers
MM410S1MM5105 quad 64-bit
dynamic shift register/accumulator
general description
The MM4105/MM5105 quad 64-bit dynamic shift
register/accumulator is a monolithic MOS integrated circuit utilizing P-channel enhancement
mode low thr~shold'technology to achieve bipolar
compatability on input/output and control lines.
Anyone of four recirculating shift registers may
be selected, by external logic control, for interrogation at the single common output or for
writing in new data at the common input data line.
•
• Versatile operation
• Disc/drum memory replacement
• Register for arithmetic units
connection diagram
truth table
Metal Can Package
Logic Definition
"1" Logical HIGH Level
"0" Logical LOW Level
VGG
~WRITE
iNPUT
ou~~~~
~ ~~NTRDL
2-
recirculation and register
select logic on-chip
• Data buffers
+5, -12V power supplies
no pull up or pull down
resistors required
internal pull up
resistors on inputs
ADDRESS ~
chip select allows
control of data entry
from common bus line
applications
features
• TTL compatability
Input bus capability
CODING AND MODE TABLE
8 - SELECT
Address
3
1
2
Write Control
Write
Recir
Chip Select
Active
Inactive
Output Level
Chip
Select
Input
Output
a a
a 1
1 a
Vss
TOP VIEW
1
1
typical application
+5.0V
5.0V"
r----~------------l-----------------1
A,
8,
8,
8,
ADORESS2
NO.2
DATA
IN
WRITE
CONTROL
I
I
CHIP
SElECT
cs
L ________________
~l~M~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
6
VGG
-12V
48
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4105
MM5105
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22V
-55°C to +125°C
-25°C to +70°C
_65°C to +150°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ±10%, unless otherwise specified.
CONDITIONS
PARAMETER
Data I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (V IL )
Data Input Leakage
(Vld
Data I nput Capacitance
V IN = -20V, T A = 25°C,
All Other Pins GND
Chip Select, Write Control and
Address 2 I nput Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND
Note 2
Data, Chip Select, Write Control
and Address 2 Input Pull-up
Resistance
Vss = 5.0V
VGG=-12.0V
V IN = 0.5V
T A = 25°C
Clock I nput Levels
Logical HIGH Level (V",H)
Logical LOW Level (V pw)
V
0.1
V f)
Vss + 0.3
Vss - 4.2
.~
V ss - 1.5
Vss -18.5
ISOURCE = -0.5 mA
ISINK = 1.6 mA
UNITS
3.0
Vss - 1.5
Vss -18.5
V IN = -20V, T A = 25°C,
All Other Pins GND
MAX
.01
V IN = O.OV, f = 1 MHz,
All Other Pins GND
Note 2
Chip Select, Write Control and
Address 2 I nput Leakage
Clock I nput Leakage
TYP
Vss - 1.5
Vss-18.5
Chip Select, Write Control and
Address 2 I nput Levels
Logical HIGH Level (V CH)
Logical LOW Level (Vcd
Clock Input Capacitance
MIN
1.0
Note 1
Data I nput Setup Time (t ds )
Data Input Hold Time (t dh )
Chip Select, Write Control and
Address Setup Time (t ds)
Chip Select, Write Control and
Address Hold Time (tdh )
100
100
0.35
0.35
J.1S
J.1s
200
20
o
ns
ns
300
200
ns
20
o
ns
300
Data Output Propagation Delay
from OUT
Delay to HIGH Level (.tpdH)
Delay to LOW Level (tpdd
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit times (TI N and TOUT)
as shown by the rfJf versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TI N equal to TOUT. The
minimum guaranteed clock frequency: (/Jf(min) =
1
where TIN and TOUT do not
exceed the guaranteed maximums.
TIN + TOUT
Note 2: Capacitance is guaranteed by periodic testing.
49
ac test circuit
performance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 1)
100
10
'N
~
TIN or TOUT = MINIMUM
-$.
>
c.,)
~
Guaranteed Maximum Partial
Bit Times vs Temperature
]
V'
Y V
1.0
~
:J
....0
z
::::I
d
w
10
'"
..=
ff:
::.::
c.,)
::
V
0.1
V
"TIN = TOUT -
-
I--
::::I
:!i
x
c:(
c.,)
""
:!i
1.0
:!:
:!i
::::I
"
:!i
"'"l"'l
Z
:E 0.01
0.1
-60
-20
20
60
100
140
-20
AMBIENT TEMPERATURE (;C)
20
60
100
140
TEMPERATURE rC)
timing diagrams
For Reading Di3ta
For Writing Data
.'N
¢OUT
CHIP
SELECT
OR
ADDRESS
---~-.-,--
DATA
OUTPUT
Explanation of Timing Diagrams
'4;n":on:::lE~r to write-in or. read-out of the MM41Q5/
.' '!"IViM5105,
the chip select line must be low during
the appropriate clock cy~le. If the chip select line is
held high during the H"
Logic "Vct>L"
Vss-14.5
Data Input Voltage Levels
Logic "V'H"
Logic "V'L"
Vss -7.0
V
V
Data Setup Time, tds
0.2
J.(s
Data Hold Time, tdh
0.03
J.(s
electrical characteristics
PARAMETER
Clock Repetition Rate
Udld "'!JUl \"d!JiI\;'ldll\;e
(EactllnpUt\ .
Clock Line Capacitance
Vss -0.5
Vss -16.0
(Note 2)
CONDITION
Fan·Out "1"
MIN
TYP
dc
Data Output Voltage Levels
Logic "VOH"
Logic "VOL"
MAX
1.0
, -
V ,N
f
I.:>
I IVIM£
UNITS
MHz
Vss -1.5
V
V
.i.v
pt-
Vss -8.0
= OV
= 1 MHz, -20V Bias'
OV Bias
Output Impedance
Outputs at Logic "0"
Output Impedance Pins 2 & 6
Outputs at Logic" 1"
Impedance Pin 8
All Other' Pins at GND
Breakdown Voltage
1.0 J.(A Test Current
TA = 25°C
MM404, MM504
MM405, MM505
9.5
18
15
30
pF
pF
MM404, MM504
MM405, MM505
15.0
25
20
40
pF
pF
0.5
15
7.5
1.0
kD
20
25
kD
10
12.5
kD
On Pin 1
GND on Pins 2,3,4,5,6, 7
-llVon Pin 8
-25
V
On Pin 7
,GND on Pins 1,2,3,4,5,6
-llV on Pin 8
-25
V
Leakage Current .
Pin 1
T A = 25°C
V.lN = -18V, Va = -llV
, All Other Pins at GND
0.5
J.(A
Pin 7
V ,N = 18V, Va = -llV
All Other Pins at GND
0.5
J.(A
Pin 8
V ,N = -8V
All Other Pins at GND
0.5
J.(A
10.0
15.0
rnA
rnA
Power Supply Current Drain
(voo)
Outputs at Logic "0"
1 MHz 'Operation
T A = 25°C
MM404, MM504
MM405, MM505
5.5
10.0
Note 1: For operating at .elevated temperatures, the device must be derated based on a 150°C maxio
mum junction temperature and a thermal resistance of 150 C/W junction to ambient. The full rating
applies for case temperatures to +125°C.
Note 2: These specifications apply over the specified temperature ranges for -11V =VGG
-14
-11
~
-18
-16
-55
25
16
3:
s:c.n
2.2
14
2.0
N
['0'"
12
,,~
10
I-
~
/
a:
a:
....
.........
°c
Max. Frequency vs Supply Voltages
VOUT vs Load Current
<
..s
125
TEMPERATURE
Voo
o
c.n
;:)
4I
~
:z:
;:;:;;; ~
/
~
....>
1.8
;:)
1.6
~
~
~
./
/
4K EXTERNA
:r
i L LfAD/S!!,!!
~
1.2
~
1.0
x
c:c
V
c.n
/
/
1.4
~
;:)
o
"".
/
V4>=0.4J.!sec:@1 MHz
V4> = 0.3 J.!sec: @1.5 MHi V4> = 0.2 J.!sec: @2.0 MHz
Voo= -10V
-
I I I I
-14
-16
VOUT
-20
.-18
VGG & V4> (Volts)
operation
A diagram of a one-bit static register employing
two clock phases (1), ¢) is shown in the schematic.
The register requires only one external clock phase
(1)) since the second clock (¢) is generated internally by T 19 and 15K; this configuration simplifies
the input drive requirements.
The basic cell functions as follows. Each bit of
delay consists of three inverters T 2, T 4,. and T 8 in
conjunction with three MOS load resistors T 3, T 5,
and T 9 followed by three coupling devices T 1, T 6,
and T 7. The timing diagram shows the sequence of
operation. Assume the input is at a logic "1" level
during tl time. When the clock (1)) goes to a logic
"1" level, two operations take place simultaneously. Fjrst, transistor T 1 turns "ON", transferring
the input data (logic "1" level) to the gate to
source capacitance (C 1 ) of T 2. The voltage stored
on C 1 is sufficient to turn T 2 "ON" discharging
node B. With the gate to source capacitance (C 2 )
of T4 discharged, T4 turns "OFF" placing a logic
"1" level at node C. Concurrently 1> turns T 19
"ON" genera'ting the complement of 1>, that is 1>
and in turn (ji is used to turn T6 and T7 "OFF".
This action allows the register's previous information to be temporarily stored on the gate to source
capacitance C3 of T 8. The output at node E during this timing sequence remains unchanged. However, during t2 time, clock 1> returns to ground;
concurrently (jj goes to a logic "1" level turning T 1
"OFF" allowing T6 and T7 to turn "ON". The
information which was previously stored on the
gate of T 8 discharges to a logic "0" level causing
the output at node E to switch to a logic" 1" level
thereby obtaining the required one-bit of delay.
Likewise the information at node C is fed back to
node A latching T 2 in the "ON" state.
When a logic "0" level is presented at the register
input, the sequence is once again repeated. The bit'
delay.demonstrated in this example is rep.eated for:
each half of the dual static register.
timing diagram
I
I
INPUT DATA
I I
~I~.--+1IIHI!,.----r~
I "",1
r
~~--+-I~'I
I
I
NODE A
NDDE
I
I
I
I I
---ttf t--- t d • I
\1 I
1/ :
i
::
II
:i
I
I I
I I
~:
I I
II:
i+-
---rr~ :I
---+-1
I
:
l
-f~
NODE D_-+-I_ _...
:
I I
NODE E - - ; - - - - t - \
'I IIII
~:
~
, :
:r-
~
:
I I
I I
I
I
11'---""'"
I
I I
----loNE BIT DELAYt--
I
I
.
tdh
I
B:
NODE C
---r-1 r--
I
I I
I I
I~I.·
I
NODE G ...... n·l DELAy .... ~
.
1 I
-\~
DATA OUTPUT ..... N BIT DELAY :. ..:..
........-.. -'-.
I
I\of--
I
.
I
r
I.'
II
53
Static Shift Registers
MM4040/MM5040 dual 16-bit static shift register
general description
The MM4040/MM5040 dual 16-bit static shift
register is a monolithic integrated circuit ulilizing
P channel enhancement mode low threshold technology to achieve direct bipolar compatibility on
the inputs and outputs. The device requires only
a single phase clock.
Bipolar compatibility
High frequency operation
•
Single phase clock
+5, -12V operation
No pull-up or pulldown resistors needed
•
Static data buffer
•
Serial memory storage
•
Printer memory
•
Telemetry systems and data sampling
connection diagram
Metal Can Package
Voo
Vss
TOP VIEW
typical application
+5V
-,
Vee
I
I
I
I
I
4
1
7
Vss
16 ·BIT S.R.
16 ·BIT S.R.
L_J;_J
ANY DTlITTl DEVICE
54
2.2 MHz guaranteed
applications
features
•
•
-12V de
ANY DTlITTl DEVICE
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4040
MM5040
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22
-55°C to'+125°C
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A'within operating temperature range, Vss = +5.OV ±5%, Vss - Voo = 9V to 18.5V, VGG = -12V ±10%, unless otherwise specified
PARAMETER
CONDITIONS
Data I nput Levels
Logical High Level (V IH )
Logical Low Level (V I d
Vss - 2.0
Vss - 18.5
Data Input Leakage
V IN = - 20V, T A = 25°C,
All Other Pins GND
Data I nput Capacitance
V IN = O.OV, f = 1 MHz,
All Other Pins GND (Note 1)
Clock Input Levels
Logical High Level (VcPH)
Logical Low Level (VcPd
VcP = -20V, T A = 25°C,
All Other Pins GND
Clock Input Capacitance
VcP = O.OV, f = 1 MHz,
All Other Pins GND (Note 1)
Power Supply Current
IGG
ISOURCE = -0.5 mA
ISINK = 1.6 mA
Clock Frequency (cPf)
V
V
~
2.5
0.5
J.LA
5.0
pF
V
V
Vss + 0.3
Vss - 14.5
1.0
J.LA
pF
22
19
0.4
V
V
2.4
T A = +25°C, VGG = -12V,
cPpw = 200 ns', Vss =5V,
V DO = -12V, VcPL = -12V,
Data = 0-1-0~ 1
0.01 MHz ~ cPf::::; 0.1 MHz
1.0
2.0
mA
cPf = 1.0 MHz
1.8
3.0
mA
= 2.0 MHz
3.0
4.0
mA
0.01 MHz ~'cPf~' 0'.1 MHz
5.0
9.0
mA
cPf
= 1.0 MHz
5.1
9.0
mA
cPf
=
5.2
9.0
mA
3.0
2.2
cPf
IDD
UNITS
MAX
Vss + 0.3
Vss - 4.2
Vss - 1.5
Vss - 18.5
Clock I nput Leakage
Data Output Levels
Logical High Level (V OH )
Logical Low Level (V ad
TYP
MIN
2.0 MHz
cPtr = cPtf = 20 ns
Clock Pulsewidth (cPpw)
cPtr + cPtf + cPpw
~ 10.5 ns
Clock Transition Times (cPtr + cPtf)
cPtr + cPtf + cPpw
~ 10.5 ns
DC
MHz
.,
.200
:100
1'0.0
p-s
1.0
J.Ls
Data Input Setup Time (tds )
120
60
ns
Data Input Hold Time (tdh)
20
0
ns
Data Output Propagation Delay from cP
Delay to High Level (tpdH)
Delay to Low Level (tpdL)
See test circuit
'.
200
200
300
300
ns
ns
Note 1: Capacitance values are guaranteed by statistical lot sample testing.
...
,
-~
"
"
55
guaranteed performance characteristics'
Data I nput Levels vs
Supply Voltage
1.0 MHz Operating Curve
2.0 MHz Operating Curve
1000 r--"T""--,---r--.,.---r--,----r---,
~
en
.....
w
;
]
]
o
~ 300
~
:;:)
.... 400
::.:::
:!:
C(
t---t--t--t--"-+-.;.;;;;;:t=---i
1.0
o
400
I-
o
~ 600
2.0
13
14
15
16
17
18
",
~ 200
t.)
t.)
o
~
~
200
-...--
--..r-
::.:::
~~---'---~~---'---~~
12
¢t, = rJ>t, = 20 ns
¢,= 2.0 MHz
TA = -55°C to +125°C
Vss = +5.oV
::z:::
I-
~
o
800
::z:::
I-
~
500
100
-
V,L = 0.8V
V,H = 3.oV
VrJ>H= 3.5V-
r
l_
TlMIN ¢pw
o
13
19
Vss - V¢L = Vss - Voo = Vss - VGG (V)
14
15
16
17
18
19
20
15
16
18
17
19
Vss - Voo = Vss - VGr3 = Vss - V¢L (V)
Vss - Voo = Vss - VGG = Vss - VrJ>L (V)
typical performance characteristics
Data Output Source
Current vs Voltage
Power Supply Current
vs'Voltage
Data Output Sink
Current vs Voltage
10.0 "'--'---'-"'---'--"'---'--"T""--'
rJ>f= 1.0 MHz
rJ>pw = 400 ns
.§ 8.0
DATA =l-o-l-o+----t-+----t---::1114
C(
C(
.§ 10 ~-+----"I"""""'-+-I-
~
I-
~
a:
a:
~
:;:)
t.)
6.0
:;:)
t.)
::.:::
2:
o
CiS
.E 4.0
I-
w
~
1--+----1f-::.o,-"F:,....,:::...,,JoII!~--+----1
(:J
C(
I-
~ 2.0
>
:;:)
o
I::=.....~f__+---!--+---t--+---!
C(
o ~-'---'--~--'--~~---'---'
o ~~~--'--~--~--~--~
-1
5
12
-1
V OUT (V)
V OUT (V)
14
16
18
20
Vss - VGG = Vss - Voo = Vss - VrJ>L (V)
Pow",r S'}p"IV Gllrr",n1"
Power Supply Current
vs Oplirating Frequency
5.0
rJ>pw = 2oo'~~
Vss= +5.oV
VGG = -12.oV
VrJ>L = -12.oV
VrJ>H = 3.5V
DATA = 1-0-1-0
14.0
I2:
~
3.0
:;:)
t.)
w
~
,1".
1.0\'
~
'0
. 10
:;:)
CI
~
c
TA - +25 C
I IIIII
b .......=---+--=-"',\'"""--+---:::!;;_-I
t.)
~
+125°C
100
~ 3.0
J
-~
C(
I-----t---+--+-\--f\:--+----:::~
I-
(:J
C(
8.0 ....---,..----.,..---,-----,----,----,
VGG = -12.OV
Vss = +5.oV
DATA = 1-0-1-0
VrJ>L = -12.oV
rJ>pw = 200 ns
VrJ>H = 3.5V
C(
.§ 4.0.
IIIIIII
_55°C __ ;-.
CI
.2 2.0
Power Supply Current
5.0 r----,----,.---.,.---,----,-----,
IIIII
IIIII
1000
;; 2.0 r-=-+---t---+- rJ>, = 2.0 MHz
(:J
rJ>pw = 200 ns
C(
~
> 1.0 1---+_-+_-+ DATA = 1-0-1-0
C(
Vss = +5.oV
VrJ>H = 3.5V
o
10,000
L-~~__'
14
____'__
16
~
__
18
~
__
~
20
10
switching time waveforms
DATA
OUTPUT
------------~~
56
12
14
16
Vss - Voo (V)
OPERATING FREQUENCY (kHz)
test circuit
18
20
~
s:
Static Shift Registers
~
o
(J1
o
»
........
s:
s:
MM4050A/MM5050A dual 32-bit static shift register
MM4051A/MM5051A dual 32-bit static shift register-split clock
(J1
o
al'
o
..»
general description
The MM4050A/MM5050A and MM4051A/
MM5051A dual 32-bit static shift registers are
monolithic MOS integrated circuits utilizing P
channel enhancement mode low threshold technology to achieve bipolar compatibility. Operation
to 22 MHz is achieved with a single phase clock.
The MM4051A/MM5051A is a bonding option
of the MM4050A/MM5050A to provide independent clock control of each register.
High frequency operation
•
•
•
Single phase clock
Push-pull outputs
Improved drive capability
Military and commercial temperature ranges
MM4050A, MM405.1A
-55°C to +125°C
MM5050A, MM5051A
-25°C to +70°C
~
o(J1
~
»
........
s:
s:
(J1
o
applications
features
•
s:
s:
dc to 2.2 MHz
•
Bipolar compatibility
+5V, -12V operation
No pull-up or pulldown resistors needed
(J1
~
•
Serial memory storage
•
•
Printer memory
Telemetry systems and data sampling
»
logic and connection diagrams
Dual-In-Line Package
Metal Can Package
Metal Can Package
14
Voo
Voo
NC
INPUT B
OUTPUT B
NC
NC
VGG
Vss
Vss
TOP VIEW
TOP VIEW
TOP VIEW
MM5050A
MM4050A/MM5050A
MM4051A/MM5051A
typ.ical applications
TTL/MOS Interface
TTL/MOS Interface
+5V
+5V
-,
Vee
Vee
r- TTL--'
I
1
I
I
7
I
L_l_J
I
ANY OTL/TTL
OEVICE
-12V
, MM4050A/MM5050A
ANY OTL/TTL
OEVICE
ANY OTL/TTL
'DEViCE
ANT OTL/TTL
DEVICE
MM4051A/MM5051A
57
absolute maximum ratings
Voltage at Any Pin
Vss + 0.3V to Vss - 22V
Operating Temperature Range MM4050A/MM4051A -55°e to +125°e
0
MM5050A/MM5051 A -25°e to + 70 e
o
-65°e to +150 e
Storage Temperature Range
0
300 e
Lead Temperature (Soldering, 10 sec)
electrical characteristics
T A within operating temperature range, Vss
= +5.0V
±5%, Vss - V DD
= 9V to
1S.5V, VGG
CONDITIONS
PARAMETER
= -12V
MIN
Data I nput Levels
Logical HIGH Level (V IH )
Logical LOW Level (V IL )
±10%, unless otherwise stated.
TYP
Vss - 2.0
Vss-1S.5
Data Input Leakage
V IN = -20V, T A = 25°C,
All Other Pins GN D
Data I nput Capacitance
V IN = O.OV, f
(Note 1)
= 1 MHz,
2.5
All Other Pins GND
Clock I nput Levels
Logical HIGH Level (VH)
Logical LOW Level (Vd
V
= -20V,
Clock I nput Capacitance
V
= O.OV, f
(Note 1)
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod
ISOURCE = -0.5 mA
ISINK = 1.6 mA
TA
= 25°C,
= 1 MHz,
UNITS
Vss +0.3
Vss - 4.2
V
V
0.5
J.1A
5.0
pF
Vss + 0.3
Vss -14.5
Vss - 1.5
Vss - 18.5
Clock Input Leakage
MAX
1.0
All Other Pins GND
25
All Other Pins GND
35
V
V
J.1A
pF
0.4
V
V
2.4
Power Supply Current
I GG .
T A = +25°C. V GG = -12.0V, ¢pw = 200 ns
Vss = +5.0V. VL = -12.0V, Data = 0-1··0-1
V DD = -12.0V
0.01 MHz ~ ¢f:S 0.1 MHz
¢f
IDD
3.5
mA
3.S
8
mA
¢f = 2.0 MHz
4.6
11.0
mA
0.01 MHz:S ¢f:S 0.1 MHz
2.7
5.0
mA
¢f:S 1.0 MHz
2.9
5.0
mA
¢f:S 2.0 MHz
3.1
5.0
mA
3.0
2.2
MHz
10.0
J1s
1:0
J.1s
= ¢tf = 20 ns
Clock Frequency (¢t)
¢tr
Clock Pulsewidth (¢pw)
¢t r + ¢tf + ¢pw :S 10.5 J.1s
Clock Transition Times (¢tr, ¢tf)
¢tr + ¢tf + ¢pw :S 10.5 J.1s
DC
0.2
0.100
Data Input Setup Time (tds)
SO
50
ns
Data Input Hold Time (tdh)
20
0
ns
Data Output Propagation Delay
From ¢
Delay to HIGH Level (t pdH )
Delay to LOW Level (t pdL )
See ac test circu it
Note 1: Capacitance values are guaranteed by periodic testing.
(58
1.6
= 1.0 MHz
150
150
300
300
ns
ns
guaranteed performance characteristics
Data Input Voltage vs Supply
1.0 MHz Operating Curve
2.0 MHz Operating Curve
400
1000
]
~
en
.....
w
800
]
....:z::
~
....
2.0
~
~ 200
1.0
CI
~
~
I¢PWMIN
I
¢,= 2.0MHz I
1
- VIL = 0.8lt, = tt = 20 ns
TA = _55°C to +125°C_ V1H =3.0V _
V,*, = 3.5V
Vss=+5.0V
~
:.:
c.,)
:.:
c.,)
CI
GUARANTEED ~~
;:
~
::::I
... 400
....c:tc:t
~ 100
200
c.,)
OL-.--'-_...J...._L.---'-_...J....---J...........
12
13
14
15
16
17
18
....
¢PWMAX
CI
~ 600
~
....
300
....:z::
CI
13
19
Vss - V¢L = Vss - Voo = Vss - VGG (V)
14
15
16
18
17
19
20
18
17
16
15
19
Vss - Voo = Vss - VGG = Vss = V¢I. (V)
Vss - Voo = Vss - VGG = Vss - V¢L (V)
typical performance characteristics
Data Output Source
Current vs Voltage
Output Sink Current
vs Voltage
Power Supply Current
.5.0
12 I'IO:"--,r------y---r---,--.-...,
<'
14.0
....
"".
.s
....
~
a:
c:::
~ 3.0
c.,)
::::I
w
c.,)
".~
¢,= 2.0 MHz
c:t
ffi> 1.0 ¢PW = 200 ns
¢t,= ¢tt = 20 ns
c:t
Vss= +5.0V
w
....::::I
...
....
::::I
Q
o
q;, = 2.0 MHz
¢PW = 400 ns
DATA = 1-0-1-0-+-t--+---1f---l
.; 6.0
:
>
c:t
<
.s
....
5.0
.2 3.0 1-----1f----j---j-¢PW = 200 ns
~
~
~ 2.0
1.0 ....."""""=--+--+--+--+--+-+--I
12
13
14
15
16
17
18
19
20
Vss - VGG = Vss - Voo (V)
switching time waveforms
I
CI
CI
2.0
+125°C
c.,)
c.,)
3.0
:
Voo =-5.0V
Vss= +5.0V
¢, = 2.0 MHz
V,*, = 3.5V
14
15
16
17
18
19
2.0
~
c:t
ffi
>
c:t
;:::: ...
1.0
~
18
20
/,1
~
"'"
~
V
VGG =-12.0V
DATA = 1-0-1-0
¢pw = 200 ns
Voo= -12.0V
Vss = +5.0V
I VL = -12.0V
V,*, = 3.5V
I
10
20
Vss - V¢I. = Vss - VGG (V)
100
1000
10,000
OPERATING FREQUENCY (kHz)
ac test circuit
EITHER
ou~:~~ O-.....-
DATA
16
TA =25°C--l--1-.IJ
~ 3.0
::::I
::::I
4.0
14
I lllli I 10111 /,
I 11111 15~ ICrn "h
4.0
~
~ 4.0 1:;;;ooo"""9=----::::;;;;oI--=C-f--t--t--;
~
ffi
5.0
~
~
a: 5.0
a:
12
Power Supply Current
vs Operating Frequency
6.0 ,..---,---,.---r---r---,-....,
1....
VGG =-12.0V
V¢I. =-12.0V V,*, = 3.5V
DATA = 1-0-1-0
Vss= Voo (V)
Power Supply Current
8.0 ,--""""--'-"T""--,.--r---r-...-----,
7.0
10
-1
VOUT (V)
VOUT (V)
Power Supply Current
vs Voltage
-
L-.---J"--~_--'-_~_~_~
5
-1
4
c
+12~OC
.E 2.0
en
c.,)
"".
i-""""
c
c.,)
a:
::::I
CI
::::I
~A = +2~OC
~
::::I
<'
-5~OC
~
-I*"",
.....-+4..................--t....
+---.
OUTPUT_ _ _ _ _ _
59
Static Shift Registers
MM4052/MM5052 dual 80 bit static shift register
MM4053/MM5053 dual 100-bit static shift register
general description
The MM4052/MM5052 dual aO-bit and MM4053/
MM5053 dual 1DO-bit static shift registers are
monolithic integrated circuits utilizing P channel
enhancement mode low threshold technology to
achieve direct bipolar compatibility on the inputs
and outputs. The devices require only a single
phase clock.
• High frequency operation
• Single phase clock
• Improved drive capability
• Static data buffer
• Serial memory storage
+5, -12V operation
No pull-up or pulldown resistors needed
• Printer memory
• Telemetry systems and data sampling
connection diagram
Metal Can Package
Vss
lOP VIEW
typical application
+5V
Vee
r- - ,
I
I
I
I
I
Vss
1
9
N·BIT S.R.
N·Bll S.R.
L_J_J
-12V
ANY OTLITTL DEVICE
60
push-pull outputs
applications
features
• Bipolar compatibility
1.6 MHz guarantee
ANY DTLITTL DEVICE
s:
s:
absolute maximum ratings
Voltage @ Any Pin
Operating Temperature Range
MM4052/MM4053
MM5052/MM5053
Storage Temperature Range
~
o
U1
Vss +O.3V to Vss -22V
N
........
s:
s:
U1
-55°C to +85°C (Ambient)
-55°C to +125°C (Case)
-25°C to +70°C (Ambient)
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
o
.N
U1
300°C
s:
s:
~
o
U1
electrical characteristics
W
TA within operating temperature range, Vss
PARAMETER
VIN = -20V, T A = 25°C
All other pins GND
Data Input Capacitance
VIN = O.OV, f = 1.0 MHz
All other pins GND
Clock Input Levels
Logical High Level (V tPH)
Logical Low Level (V tP L ,
VIN = -20V, T A = 25°C
All other pins GND
Clock Input Capacitance
VIN = O.OV, f = 1.0 MHz
All other pins GND
(IGG) MM4052/MM5052
.01
3.0
Vss - 1.5
Vss - 18.5
Clock Input Leakage
Power Supply Current
UNITS
Vss - 4.2
V
'V
ISOURCE = -500pA
ISIN K = 1.6 mA
ISOURCE = -10 J,J.A
ISINK = 10J,J.A
0.5
J,J.A
5.0
pF
Vss
Vss - 14.5
V
V
1.0
J,J.A
22
28
pF
2.4V
4.8
-3.0
Vss
0.4
Vss - 1.0
Vss
Vss - 12.0
Vss
Vss - 7.0
V
V
V
V
9.5
12.5
mA
12.0
16.0
mA
200
200
300
300
ns
ns
T A = 25°C
4.0 t--t--+--+--+----"'k:-""'l
Q
rn
I-
I-
==
~
~
1.0 ...----IW~'----+---+--+---i
ct
4.0
l.O
2.0
1.0
0.0
-1.0
II:
...---+--+---+--+--+-~
2.0
5.0
4.0
l.O
VOUT (V)
2.0
1.0
0.0
.02
ct
VGG = -12V
Vss = 5.0V
Q
5.0
-
.04
c:1
Q
==
/~
Cl
~
/
~~
o
-1.0
12
14
VOUT (V)
TA = -55°C
o
111111111 I 11111111
I++H++I~I-+-++++Hf
L-~~UW_~
10
100
__________w
1000
10,000
OPERATING FREQUENCY (kHz)
switching time waveforms
ac test circuit
DATA INPUT
DATA OUTPUT
0
10'F
¢It.. =tf>tt"'20ns
62
16
Vss - VGG (V)
Power Supply Current
111111111
I 1111111
",
V
.06
ct
==
2.0 1------i1----+-+-#--,.I4--+-----i
Vss = 5.0V
q,pw = 250 ns
TA = +25°C
q" = 1.0 MHz
DATA = 1-0-1-0
.08
A-
6.0 "'---+--F-"'::+---""~~~~
Co)
Co)
§
~-+--""....r-~:__-+---I-----4
8.0
I-
II:
§
1
1
T
18
20
Static Shift Registers
MM5054 dual 64/72/80 bit static shift register
general description
The MM5054 dual 80-bit static shift register is a
monolith.ic MOS integrated circuit utilizing silicon
gate low threshold technology to achieve complete
bipolar compatibility. The device has input and
output taps that also provide register lengths of
64 or 72 bits.
The single phase bipolar compatible clock lines
may be driven by any conventional DTL or TTL
circu it. The registers may be operated as a dual
register by connecting the clock lines A and B
together, or as two independent registers. Two
clock control lines provide independent logical
control of the shift register clock lines.
+5V,-12V
DC to 3.0 MHz typ
•
High freq operation
•
Single phase clock
•
Low clock line capacitance
•
System flexibility
•
Low power dissipation
DTL/TTL compatible
on-chip clock driver
8 pF max
Split clock or common
clock operation. Logical
control of clock lines
<600 IlW/bit typ
applications
features
•
., Standard supplies
Complete bipolar compatibility
DTL/TTL
input/output and
clock line compatibility
without additional
components
•
•
Teletype data buffers
Printer memory - 80, 128, 136, 144 bit lengths
•
Telemetry and data sampling systems
•
Serial memory storage.
logic and connection diagrams
DATA
INPUT
1.15
DATA
OUTPUT
3,13
Dual-In-Line Package
INPUT-A-72/BO 1
DATA
INPUT
2,140----.....1
4,12
CLOCK
7,9"'--~~-
16 Veo
INPUT-A-64172 2
15 INPUT-B-72/S0
OUTPUT-A-72/BO 3
14 INPUT-B-64172
OUTPUT-A-64172 4
13 OUTPUT-B-72/S0
N.C. 5
12 OUTPUT-B-64172
CLOCK CONTROL A 6
11
CLOCK
CONTROL
6,10
VGG
10 CLOCK CONTROL B
CLOCK A 7
9
V,. S
CLOCK B
TOP VIEW
The unused data inputs and clock controls should
be connected to Vssto ensure proper operatIOn.
logic diagram shows f/2 of the unit.
truth table
CLOCK
CONTROL
CLOCK
Low
Inhibited
High
Active
Positive Logic
63
.-
absolute maximum ratings
Voltage at AllY Pin
Operating Ambient Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 20.0V
0
-25°e to + 70 e
o
-65°e to +150 e
0
300 e
electrical characteristics
TA within operating range, VGG = -12V ±10%, Voo = GND, Vss = 5V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Data, Clock Control, and Clock Levels
Logical High Level (V IH )
See Input Level vs VGG Curve
Vss - 2.0
TYP
Logical Low Level (V I d
I nput Leakages
V IN = -10V, T A = 25°C
All Other Pins GND
Data I nput Capacitance
V IN = O.OV, f = 1 MHz
All Other Pins GND (Note 1)
Clock & Clock Control Capacitance
V IN = O.OV, f = 1 MHz
(Note 1)
Data Output Levels
Logical High Level (V OH )
See Figure 1
ISOURCE = -0.5 mA
Logical Low Level (Vod
Power Supply Current
( I G-G + 100 = Iss) IGG
100
Vss + 0.3
V
Vss - 4.2
-V
0.5
J.1A
4.5
6.0
pF
6.0
8.0
pF
2.4
Vss
V
0.15
0.4
V
rpf = 2.0 MHz, T A = 25°C
Vss = 5V, V OD = GND
7.0
10.0
mA
VGG = -12V
5.0
8.0
mA
3.0
2.2
MHz
See Operating Curves
Clock Pulsewidth (rppw)
See Operating Curves and
Figure 1
rpt r = rptf = 10 ns
DC
0.25
10
J.1s
Clock Transition Times
Clock Risetime (rpt r )
500
ns
Clock Falltime (rptf)
500
ns
Clock Control Setup Time (tcs)
See Figure 1, rpt r = rptf = 10 ns
0
ns
Clock Control Hold Time (tch )
See Figure 1, rpt r = rptf = 10 ns
0
ns
Data Input Setup Time (tds)
See Figure 1,rptr =rpt f = 10ns
60
30
ns
Data Input Hold Time (tdh)
See Figure 1, rpt r = rptf = 10 ns
40
20
ns
Data Output Propagation Delay
From Clock
See Figures 1 & 2,
rpt r = rptf = 10 ns
Delay to Output High Level (tpdH)
200
300
ns
Delay to Output Low Level (tpdd
200
300
ns
Note 1: Capacitance is guaranteed by periodic testing.
64
UNITS
ISINK = 1.6 mA
Clock Frequency (rpf)
Clock Pulsewidth
MAX
performance characteristics
Typical Data Output Source
Current vs Data Output Voltage
,
5.0
~
~~
4.0
'"
I-
ffi
a:
10.0
3.0
~
+70°C
a:
~
c.;I
"- ~
~
0
1.0
o
o
1.0
8.0
~
6.0
a:
a:
5.0
c.;I
4.0
2.0
~
~
~
3.0
CiS
~
~ II'
h V
3.0
2.0
1.0
~
"
,
'/
4X
+70°C
/
~
Typical Power Supply
Current vs V GG
9.0
~
.§
I-
/
8.0
ffi
7.0
~
6.0
a:
a:
c.;I
~
.I.V~ V
5.0
:;:)
en
~'
Iss = IGG + 100
Voo = GND
Vss =+5.0V
DATA = 1-0-1-0
,= 1 MHz
TA = +25°C
a:
....
4.0
~
3.0
3:
~
~
V
0.2
IIII
0.4
0.6
~
.§
c
.E
~~
--
3.0
.§
<:I
.2
TA =+70°C
DATA = 1-0-1-0
Vss = +5.0V
Voo = GND
VGG = -12.0V
2.0
1.0
o
10 k
100 k
1M
13
14
::c
e
~
~
19
18
19
Guaranteed Input Levels
vsVGG
LH~~
10M
~
10k
100 k
~
1.0
t,=t,= 10 ns
VL = 0.8V
VH = 3.0V
12
10M
1M
13
1000
-
::c
700
~
~
~
600
~~~
r-"-~--~
Vss = +5.0V -25°C,,,:, (Note 1\
I nput Leakage
VIN = Vss -12V
Input Capacitance
f = 1.0 MHz
Access Time (Notes 2, 3)
T A = 25°C
(See Timing Diagram)
Vss = +12V VGG=-12V
T ACCESS
Output AND Connection
mA
1
.uA
1
J1A
5
VIN = OV
150
500
MOS Load
TTL Load
Note 1: The V GG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.)
Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = the
specified time + (N-l) (50) ns where N = number of AND connections. The number of AND ties in
the MOS load configuration can be increased at the expense of MOS "0" level.
·80
25
pF
650
3
8
ns
performance characteristics
Typical Access Time vs
Supply Voltages
Guaranteed Access Time vs
Supply Voltages
--
'TA '" 12~0~
T-'_ TA ", 75°C
1000
800
~
1000
- ...TA ~;fof
600
- ...
~ 600
i-...
~
<{
I-
BOD
]
400
400 f-r-
I-
'--
200
200
10.8
12.0
13.2
·7
125 C'+ili
+
III
25°C~
~ 18
16
,
~
26
1...00'
~
~YPlCAl
Vss = +12.0V
VGG = -12.0V
r\.
I..'"
J'
,
f-
22
C(
.§
o
.E 18
""
14
'\
'\
I
"",-
12.0
13.2
""
"'.....
""j'...
"'-
TYPICAl' ~
-50 -25
Vss & VGG (V)
I
'~UARANTEED
14
10,8
13.2
12.0
Power Supply Current vs
Temperature
~ TA=25°C
.§
'I
Vss & VGG (V)
24 - r - GUARANTEE~
~
I
'-f-70°C
10.8
Power Supply Current vs
Voltage
,
C( 20
I""~
O
Vss & VGG (V)
22
-l- I--
/7- ~I-~
0
25
50
75 100 125
TEMPERATURE (OC)
timing diagramladdress time
+12V
+3V-
rt
UV..J
L
-12V
t12V
OV
E'N
+12V
OV
+3V
"=",
L5V
EOUT
+3V
1.5V
I
OV
time
81
I\IIO~'"R,OMprogram format
The memory contents for individual requirements must be submitted on a tape or card format as shown·
below. An 8-1/2" X 11" size pattern selection form is also acceptable. For copies of the MM4220/MM5220
selection form, write or call any National sales office or National, Santa Clara.
Punched Paper Tape or Cards. (See Note 5.1
COLUMN NO.
1
2
3
4
A
0
0
0
A
0
0
0
0
1
2
1
1
I
I
I
1
A
1
j
I
I
I
I
I
A
T
T
T
1
B
B
B
2
8
7
6
1
7
I
I
I
I
I
I
I
I
I
I
I
I
T
B
1
1
1
(f)
u
~
5
(f)
u
6
(f)
u
"
~ ~
7
8
9
10
11
12
13
14
B8
B7
B6
B5
B4
B3
B2
B1
1
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
0
1
0
0
0
0
8
0
1
1
0
7
6
1
2
I
I
I
I
I
I
I
I
I
I
I
I
0
3
0
1
1
1
1
(NOTE 41
1
0
15
16
17
18
(f)
4
6
4
~
r
~.
~
~
~.
"T1
CD
:IJ
C.
~
5
Z
~
w
Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with
25 or more "RUBOUT" punches.
Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.
Note 3: The total number of "1 's" bits in the outP.ut word.
Note 4: The total number of "1 's" bits in each output column or bit position.
Note 5: The punched card format is as shown except that col umns 17 and 18 are not necessary.
Program one address per card. All columns beyond those specified may be used by the customer.
H2
ROMs
MM4221/MM52211024-bit read only memory
general description
The MM4221/MM5221 is a '1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 128-8-bit words or
256-4-bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.
•
Static operation
no clocks required
•
Common data busing
•
Chip enable output control
output wire AND
capability
applications
•
features
Code conversion
•
Random logic synthesis
•
Table look-up
•
Bipolar compatibility
+5V, -12V operation
•
Character generators
•
High speed operation
<700 ns typ
•
Micro-programming.
block and connection diagrams
Dual-In-Line Package
B,
A,
,.
INPUTA 3
A,
v"
INPUTA 2
B,
INPUT A,
MEMORY
OUlPUTD,
ADDRESS
DECODER
INPUTA 4
OUTPUTB 2
A,
B,
B,
DUTPUTB 3
INPUIA 6
OUTPUTB 4
INPUTA 7
OUTPUTB s
v"
MODE
OUTPUTB6
B,
OUTPUTD]
CONTROL
10
OUTPUTSe
A.--......---'
v"
'-+------~~~BlE
CHIP
ENABLE
tNPUTA s
"
typical application
Operating Modes
128-8 Bit ROM Showing TTL Interface
128x8 ROM connection
Control - Logic "0"
As
- Logic "1"
256x4 ROM connection
Control - Logic" 1"
As
- Enables the odd (B I
(B 2 ••• Bs) outputs.
A.
.••
B7
)
or even
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
B,
A,
: ANYOTLITTL
I
LOGIC
The outputs are connected to ground through an
internal MOS resistor when "Disabled."
B.
Logic levels are negative true MOS logic.
B,
Mode control should be "hard"wired" to either
Voo (logical "1") or Vss (logical "0").
B,
A.
A,
A,
v"
tsu opelltlnll mode notes
l
A,
1
83
absolute maximum ratings
V GG Supply Voltage
V DO Supply Voltage
Input Voltage
(Vss - 20)V
Storage Temperature
Operating Temperature MM4221
MM5221
Lead Temperature (Soldering, 10 sec)
Vss - 20V
. Vss - 20V
< V 1N < (Vss +0.3)V
-65°C to +150°C
-55°C to +125°C
-25°C to + 70°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
Output Voltage Levels
MOS to TTL
Logical" 1"
Logical "0"
6.8 kS1 ±5% to V GG Plus One
Standard Series 54/74 Gate
Output Current Capability
Logical "0"
VouT=2.4V
Input Voltage Levels
Logical" 1"
Logical "0"
Power Supply Current
100
IGG (Note 1)
UNITS
+0.4
V
V
+2.4
2.5
mA
T A = 25°C
Vss = +5V
VGG = V DO = -12V
I nput Capacitance
V GG Capacitance
f = 1.0 MHz, V 1N = OV
f = 1.0 MHz, V 1N = OV
Address Time (Note 2)
See Timing Diagram
TA = 25°C,
Vss = 5V
VGG = Voo = -12V
6.5
mA
IlA
1
IlA
5
15
25
pF
pF
700
950
ns
6.8 kS1 ±5% to V GG Plus One
Standard Series 54/74 Gate
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 3: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns
Where N = Number of AND conne<;:tions.
V
V
12.0
1
Note 2: Address time is measured from the change of data on any input except mode control or Chip
Enable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit
over temperature.
84
MAX
Vss - 4.2
V 1N = Vss - 12V
Output AND Connections
(Note 3)
TYP
Vss - 2.0
I nput Leakage
T ACCESS
MIN
8
~.
~
performance characteristics
~
N
Power Supply Current vs
Power Supply Voltages
Power Supply Current vs
Ambient Temperature
I I
I I I
14
I
Vss =+5.DV
I
I
14
Vee =VGG =-12V
~.I
I
I r"'o4o....J
12
r - -MAXIMUM ~
r-~ ....
10
VD~ = ~GG
""
TA - 25 C
l~
12
I,.ooo~
MAXIMUM
r'---
lD
.5
...... "'"
o
..P
........
l
r-"""
o
17.D
18.0
1400
- ...
Vee =VGG
12DO
]
w
::iE
+70°C
i=
8
+125°C
I I
+25°C
........
60D
~
w
r.)
r.)
ct>
0-
~
5
~
w
a
Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with
25 or more "RUBOUT" punches.
Note 2:
Note 3:
Note 4:
Note 5:
The ROM input address is expressed in decimal form and is preceded by the letter A.
The total number of "1 's" bits in the output word.
The total number of "1 '5" bits in ,each output column or bit position.
The punched card format is as shown except that columns 17 and 18 are not necessary.
be used by the customer.
Program one address per card. All columns beyond those specified
86
may
ROMs
MM4230/MM5230 2048-bit read only memory
general description
The MM4230/MM5230 is a 2048-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 256-8 bit words or
512-4 bit words. Programming of the memory contents is accomplished by changing one mask during
the device fabrication. Customer programs may be
supplied in a tape, card, or pattern selection format.
features
•
Bipolar compatibility
•
High speed operation
500 ns typ
no clocks required
•
Static operation
•
Common data busing
•
Chip enable output control.
output wire AN 0
capability
applications
•
Code conversion
•
Random logic synthesis
•
Table look-up
•
Character generators
•
Micro-programming.
block and connection di-agrams
Dual-In-Line Package
(LSB) A,
v__
A,
INPUTA3
B,
INPUT Az
A,
B,
INPUT Al
B,
MEMORV
OUTPUT8 ,
INPUT",
OU1PU18 2
INPUT As
OU1PU18 3
INPUT ..
QUTPUTB 4
INPUT A1
OUTPUTS!;
INPUT As
ADDRESS
DECODER
B,
A,
B,
B,
OUTPUTB 6
B.
VGG
MODE
OUTPUTS 7
CONTROL
CHIP
OUTPUTB o
CHIP
ENABLE
A,
Vss
ENABLE
12
INPUT A9
TOP VIEW
typical application
256 x 8 Bit ROM Showing TTL Interface
256x8 ROM connection
Mode Control - Logic "0"
A9
- Logic "1"
Vss
t A,
t
Operating Modes
CHIP
ENABLE
B,
t MODE
CONTROL
J»K
VGG
..
A,
B,
A,
B.
..
B,
A,
20
A,
OM.'10
v__
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line .
The outputs are connected to V DO through an
internal MaS resistor when "Disabled."
B,
22
TTL GATES
B,
6.BK
512x4 ROM connection
Mode Control - Logic "1"
A9
- Logic "0" Enables the odd
(B" B3 ... B9 ) outputs
- Logic "1" Enables the even
(B 2 , B4 ... B8 ) outputs.
A,
A,
A,
87
absolute maximum ratings
VGG Supply Voltage
V D D Supply Voltage
Input Voltage
(V ss -20)V
Storage T emperatu re
Operating Temperature MM4230
MM5230
Lead Temperature (Soldering, 10 sec)
Vss-30V
V ss -15V
< VIN < (Vss +0.3)V
-65°C to +150°C
-55°C to +125°C
-25°C to +70°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +12V ±5% and V GG = -12V ±5%, unless oth,erwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"
MIN
CONDITION
1 MS1 to GND Load (Note 1)
6.8 kS1 to V GG Plus One
Standard Series 54/74 Gate Input
TYP
MAX
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
V
Vss -1.0
+2.4
Input Voltage Levels
Logical "1"
Logical "0"
Vss -2.0
Power Supply Current
Vss
VGG (Note
TA
= 25°C
24
I)
= Vss -12V
Input Leakage
VIN
Input Capacitance
f
Access Time (Notes 2, 3)
T A = 25°C
(See Timing Diagram)
Vss = +12V VGG = -12V
T ACCESS
Output AND Connection
= 1.0 MHz
VIN
= OV
150
500
MOS Load
TTL Load
Note 3: The. access time in the TTL load configuration follows the equation: T A'CCESS = the
specified time + (N-1) (50) ns where N = number of AND connections. The number of AND ties in
the MOS load configuration can be increased at the expense of MOS "0" level.
mA
j
JJ.A
1
fJ..A
pF
5
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.)
88
40
725
3
8
ns
performance characteristics
Guaranteed Access Time
vs Supply Voltages
"'"
1000
Typical Access Time vs
Supply Voltages
!
TJ!I '" 1250C
1000
TJ!I"'~
~
C
800
--, .... -
800
~........
-~ .... ""'1
r-
~ 600
~ 600
~
~
«
«
~ 400
~
400
.... r-7,'''
--
-f--
10.8
12.0
I I
-70°C
-I 1
Power Supply Current
vs Te'mperature
Power Supply Current
vs Voltages
~Ak:.,..10'
~,
36
"<
~
32
.§.
o
.E 28
:,;
24
60
I
TA =25°C
~
13.2
12.0
Vss & VGG (V)
Vss & VGG (V)
40
I
r-r-
25°C':--:- I
10.8
13.2
t
:ll
0-
<1>
c:
:>
a
a a
8
1
1
7
6
1
2
I
I
I
I
I
I
I
I
I
I
I
I
a
3
1
1
1
1
(NOTE 4)
1
a
5
~w
a
Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with
25 or more "RUBOUT" punches.
Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.
Note 3: The total number of "1 's" bits in the output word.
Note 4: The total number of "1's" bits in each output column or bit position.
Note 5: The punched card format is as shown except that columns 17 and 18 are not necessary.
Program one address per card. All columns beyond those specified may be used by the customer.
90
ROMs
MM4231/MM5231 2048-bit read only memory
general description
The MM4231/MM5231 is a 2048-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as a 256-8 bit words or
512-4 bit words. Programming of the memory
contents. is accomplished by changing one mask
during the device fabrication.
features
•
Static operation
•
Common data busing
•
Chip enable output control
No clocks required
Output wire AND
capability
applications
•
Code conversion
•
Random logic synthesis
•
Table look-up
•
Bipolar compatibility
+5V, -12V operation
•
Character generator
•
High speed operation
640 ns typo
•
Micro-programming
block and connection diagrams
Dual-In-Line Package
OUTPUTS t
INPUTA l
(LSB)
A,
INPUTA 2
8,
A,
INPUTA,
A,
8,
8,
A,
OUTPUTS,
INPUTA 4
ourpurB 2
INPUT As
OUTPUTS 3
INPUT As
OUTPUTB 4
INPUT A7
OUTPUT Dr,
INPUT As
8,
8,
8,
OUTPurss
VGO
OUTPUTS 7
MODE
CONTROL
OUTPUTSs
CHIP
ENABLE
V"
INPUT Ag
CHIP
A,
ENABLE"
tTheoutputsareconnected to Voo
through an Inlernal MOS resistor
whenOtsabled.
"The output is Enabled by applVtng
a logIc "1" to the ChIp Enable line.
typical application
256 x 8 Bit ROM Showing TTL Interface
Operating Modes
256x8 ROM connection (shown)
Mode Control - Logic "0"
- Logic "1"
Ag
A,
512x4 ROM connection
Mode Control - Logic" 1"
Ag
- Logic "0" Enables the odd
(B 1 , B3 ... B9 ) outputs
- Logic "1" Enables the even
(B 2 , B4 ... B8 ) outputs.
v"
t
CHIP
ENABLE
8,
t MODE
CONTROL
S.8K
8,
The outputs are "Enabled" when a logic
applied to the Chip Enable line.
"1"
is
A.
8,
Logic levels are negative true MaS logic.
A,
8,
Mode Control should be "hard wired" to V DD
(Logical "1") or Vss (Logical "0").
A,
8,
A,
8,
A,
8,
A,
A,
VDD
A,
tSee openttng mode notes.
1
1
9l
absolute maximum ratings
V GG Supply Voltage
Voo Supply Voltage
Input Voltage
Vss - 20V
Vss - 20V
(Vss - 2Q)V < V 1N < (Vss + 0;3)V
Storage Temperature !
-65°C to +150°C
-55°C to +125°C
Operating TemperaturE! MM4231
-25°C to +70°C
MM5231
Lead Temperature (Soldering, 10 sec)
300°C
electrical characteristics
PARAMETER
CONDITIONS
MIN
Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"
6.8 kn ±5% to V DO Plus One
Standard Series 54/74 Gate
2.4
V
V
Output Current Capability
Logical "0"
V OUT = 2.4V
2.5
mA
I nput Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
100
IGG (Note 1)
TYP
+0.4
V
V
15
30
1
mA
J.1A
1
J.1A
VIN=-12V
Input Capacitance
f = 1.0 MHz, V 1N = OV
5
pF
V GG Capacitance
f = 1.0 MHz, V 1N = OV
15
pF
Address Time (Note 2)
See Timing Diagram
TA = 25°C Vss = +5.0V
VGG = Voo = -12.0V
Output AND Connections
(Note 3)
640
6.8 kn ±5% to Voo Plus One
Standard Series 54/74 Gate
Note 1: These specifications apply forVSS = +5V ±5%, VGG = VDD = -1~V, ±5%, and T A = -55°C
to +125°C (MM4231), T A = -25°C to + 70°C (MM5231 ) unless otherwise specified.
Note 2: The VGG 'su~ply m~y be clocked to reduce device power without affecting access time.
Note 3: Addr~~;·tim~·is'~e~~~redfrom th~'~hange of data on any input or Chip Enable line to the
outP4t of a 'TTL 'ga,te~:(SeeT!ming Diagram.! ~ee curves for guararteed limit over temperature.
Note 4: The ",ddr,ess time in the TTL IQad configuration follows the equation:
TACCESS '= The specified limit + (N -:-1) (50) ns.
Where N = Number qf AND connections.
Note 5: Capacitances are meas~red on a lotsample basis only.
,92
Vss - 4.2
Vss - 2.0
TA = 25°C
Vss = +5V
VGG = Voo = -12V
UNITS
I nput Leakage
TACCESS
!,
MAX
950
8
ns
performance characteristics
Guaranteed Access Time (TAl
vs Power Supply Voltage
1400
Typical Access Time (TAl
vs Power Supply Voltage
1400
Voo = vGG
-----
1200
r- __
1000
I
«
+125°C
+70 o 'C
+25°'C
1000
800
800
600
~ 600
400
400
200
200
17.0
16.0
,
I
'
+25°C
18.0
17.0
16.0
Vss - VGG (V)
.
,
l'
.§
Q
Ambient Temperature
,40
-~ TA =25°C
36
32
GUARANTEED
20
.E
lZ
Vss =+5.0V'lJ- '
Voo =VGG =-12V .
f""'or-."
,....~
28
16
-
TYPICAL
---
C(
24
.§
20
Q
I't-- ....
i""1'-0
I II r
4
-
~~I'-
1111
-50 -25
18.0
IIII
-+-Ul
TYPICAL
8
17.0
-
MA~~;;;t: - f-
.E , 16
4
--...111 I
GUARANTEED
12
16.0
.
PowerS~pply CurrEmtvs
~MAXIMUM
24
C(
I I
.-1--1"""
I
~10~C
18.0
Power Supply Current vs
Power Supply Voltage
28
I
+l,W C
Vss - VGG (V)
31-
I
1200
]
I-
I
Voo =VGG
I
0
+25 +50 +75 +100+125
TA (OC)
Vss - VGG (V)
timing diagram/address time
'.~.. ~,---1.5V
1.5V
f - - - - - - - - - - - - - - - - - - - - time
+5V
+3V-
rI
OV..J
JO--4II......-o
L
EOUT
-12V
93
MOS ROM program format
The memory contents for individual requirements must be submitted on a tape or card format as shown
below. An 8-1/2" x .11" size pattern selection form is also acceptable. For copies of the MM4231/MM5231
selection form, write or call ~my National sales office or National, Santa Clara.
Punched Paper Tape or Cards. (See Note 5.)
COLUMN NO.
1
2
3
4
A
A
A
I
a a a
a a 1
a a 2
I
I
I
I
I
I
I
7
I
I
I
I
I
I
A
1
B
B
B
I
I
2
8
7
6
T
T
T
I
I
I
I
T
I
I
I
I
I
I
I
I
B
1
5
C/)
6
C/)
~ ~
~ ~
a a
1
1
Cf)
"0
~
(')
I
I
I
I
~ a
7
6
I
I
I
I
3
7
8
9
10
11
12
13
14
B8
B7
B6
B5
B4
B3
B2
Bl
1
1
1
a
1
1
1
a
1
a
a
a
a
8
1
2
1
a
1
)
1
1
1
1
a
1
a
a
a
1
1
1
(NOTE 4)
1
I
I
a
15
16
C/)
4
6
4
~
b'
g.
17
18
&>
•
=l
~.
f
~.
."
it
5
Z
*
~
I
I
a
Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with
25 or more "RUBOUT" punches.
Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.
Note 3·: The total number of "1's" bits in the output word.
Note 4: The:total number of"1's" bits in each output column or bit position.
Note 5: The punched card format is as shown except that columns 17 and 18 are not necessary.
Program one address per card. All columns beyond those specified may be used by the customer.
94
ROMs
MM4232/MM5232 4096-bit static read-only memory
general description
features
The MM4232/MM5232 4096-bit static read-only
memory is a P-channel enhancement mode monolithic MOS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility. TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organized in a 512 word x 8-bit or 1024 word x 4-bit
memory organization that is controlled by the
mode control input. Programmable Chip Enables
(CE 1 and CE 2 ) provide logic control of up to 16K
bits without external logic. A separate output
supply lead is provided to reduce internal power
dissipation in the output stages.
'.
•
Bipolar compatibility
•
Standard supplies
No external
components required
+5V, -12V
TRI-STATE outputs
•
Bus ORable output
•
Static operation
No clocks required
•
Multiple ROM control
Two-programmable
Chip Enable lines
applications
•
Customer programs may be submitted for production in a paper tape or punched card format.
Character generator
•
Ranoom logic synthesis
•
Micro-programming
•
Table look-up
logic and connection diagrams
A,
A,
A,
Dual-In-line Package
MODE CONTROL
1
24
CE,
2
~----j~-+--() 8,
CE,
3
23
22
V"
VGG
8,
~----j~-+-()
8,
8,
AlO
4
21
~---1c..--I-o() B,
A,
t------1~-t-o()85
~---1~~o()8.
A,
5
6
20
19
A,
1
18
8.
8,
A,
~----jl>_-+-()B,
A,
8
11
8,
A,
~----jI>_-+-()8,
As
9
10
16
8,
As
15
8,
A,
11
As
Vss
12
14
13
MEMORY
ARRAY
A,
A,o
B.
A,
TOP VIEW
CE,o--------I
CE,o---------I
typical applications
TTl/MOS Interface
FIGURE 1. Power Saver for
Small Memory Arrays
FIGU RE 2. Power Saver for
large Memory Arrays
--,
VGG
r----,
I
I
I
I
I
L ___ ..J
VGG
I
I
"::' I
I
I
I
I
I
L ___ ..J
ASSUME IIV" IIMIN < 11-3V II
VOG - V LL MIN = R (1.6 rnA) (N)where N =4 for 1024 x 4 organization
N=8for512x8 organization
Operating Modes
CE,o------'
eE,O-------'
512 x 8 ROM connection
Mode Control - Logic HIGH
A,o
- Logic LOW
1024 x 4 ROM connection
Mode Control - Logic LOW
AID
- Logic HIGH enables the odd
(B 1 . . . B7 ) outputs
Logic LOW enables the even
(B 2 .•• B8 ) outputs
When CE, = 1, CE 2 = 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the third
state when' disabled. The logic states of the chip enables are specified on the program tape. Mode Control must be hard wired to
VGG or V LL for a logic LOW or to Vss·for a logic HIGH.
95
absolute maximum ratings
VGG Supply Voltage
V LL Supply Voltage
(V ss - 20)
I nput Voltage
Storage Temperature Range
Operating Temperature Range MlVi4232
MM5232
Lead Temperature (Soldering, 10 sec)
v<
Vss - 20V
Vss - 20V
V IN
(V SS + .03)V
-65°C to +150°C
-55°C to +125°C
-25°C to +70°C
300°C
<
electrical characteristics
T A within operating temperature range, V ss = +5V ±5%, V GG = V DD = -12V ±5%, unless otherwise noted.
PARAMETER
Output Voltage Levels
Logical LOW
Logical HIGH
CONDITIONS
IL = 1.6 mA Sink
IL = 100/lA Source
Input Voltage Levels
Logical LOW
Logical HIGH
MAX
.4
2.4
Vss = 5, VGG = -12, V LL = -12, TA = 25°C
Vss = 5, VGG = -12, V LL = -3, TA = 125°C
Input Leakage
V 1N = Vss - lOV
In!"lut Capacitan~f! (Nntp ?l
f=1 OIlJlHl.V,'" =OV
Output Capacitance (Note 2)
f = 1.0 MHz, V 1N = OV
Address Time (Note 1)
TA = 25°C, Vss = 5
VGG = V LL = -12V
23
12
5
4
150
Output AND Connections (Note 3)
Note 1: Capacitances are measured periodically only.
Note 2: Address is measured from the change of data on any input or chip enable line to the output
of a TTL gate. (See Timing Diagram.)
Note 3: The address time follows the following equation: T ACCESS = The specified limit + (N-l) x
25 ns where N = Number of AND connections.
Note 4: Outputs open.
96
TYP
UNITS
V
V
Vss - 4.0
V
V
37
mA
mA
Vss - 2.0
Power Supply Current
Iss (Note 4)
Iss (Note 4)
TACCESS
MIN
20
1
/lA
10
pF
10
pF
1000
ns
20
performance characteristics
Typical Access Time vs
Supply Voltage
Guaranteed Access Time vs
Supply Voltage
1600
1400
1600
I I I
I I
VLL = Voo
1400
I 1'25~C
I""~ ....
1200 TA=70°C ~I-o
25°C 1""1-]1000
~
....
1200
VLL = VGG
I I
I I
I I
125°C ~I-o
1000 TA=70°C .... 1-0
25°C .... 1000
1""- ....
.... 1-0
~ BOO
Ll
]
I""~
i"""1-1ooo
BOO
r-I-I-o
c(
600
I-
600
400
400
200
200
o
16.2
17.0
16.2
17.B
17.0
17.B
Vss + IVGG I (V)
Power Supply Current vs
Voltage
Power Supply Cu rrent vs
Temperature
80
Vss= 5.0V
VGG=VLL=-12V
70
.5
~
40
30
l TA= 25°CVLL =V GG -
·1-
60
60
C 50
Bo
70
I
C 50
"'"
~
i""1-_
MAXIMUM
I I I
i""""""
~I--
20
10
MAXIMU'M ...... f-
.540
J!
........ r-Tl
30
TYPII:AL
TTT
20
I I I I
I I I
10
.... """-
--
I
T~p:cAl r-f- ,...-
J Llt
-50 -25
0
25
50
16.2
75 100 125
TEMPERATURE rC)
17.0
17.B
Vss + IVGG I (V)
timing diagram/address time
TIME
97
(Program a "1" or "0")
2 Spaces
Note 2
.'1M4?32
CEI=O
CE2=O
AOOO
AOOI
.1\002
A003
AOO4
AOOS 00011100
AOO6 O()OOOOon
AOO? 00111100
AOOR 00000000
ASII
01010101
TBR 140
TB7 150
TB6 250
. TR5 40f)
T84 010
T83 100
TB2 299
TBI 197
0
4
6
1 Space
3
0
4
0
4
Note 4
' - - - - - - - - - - - ' - - - - - i - - 1 Space
Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape
should begin and end with 25 or more "RUBOUi" ·punches.
Note 2: The ROM input address is ex'pressed in decimal form and is
preceded by the letter A.
Note 3: The total number of "1's" bits in the output word.
Note 4:, The total number of "1's" bits in each output column or
bit position.
The MM5232 can be programmed as a 512 x 8 or a 1024 x 4. The
tape would print out as shown for the 512 x 8 code.
98
ROMs
MM4240/MM5240 2560-bit static character generator
general description
'features
The MM4240/MM5240 2560-bit static character
generator is a P-channel enhancement mode
monolithic MaS integrated circuit utilizing a low
threshold voltage technology. Six character address and three row address input lines provide
access to 64-8 x 5 characters. Customer-generated
single or multiple package character fonts are easily
programmed by completing a pattern selection
form. A standard 7 x 5 raster scan font is available by
ordering the MM4240AA/MM5240AA. (See page
102.)
•
•
•
•
•
Bipolar compatibility
High speed operation-600 ns max.·
± 12 volt power suppl ies
Static operation-no clocks required
Multiple ROM logic application-chip enable
output control
• Standard fonts available-off-the-shelf delivery
applications
•
•
•
•
The MM4240/MM5240 may be used as a
512 x 5-bit read only memory for applications
other than character generation.
Character generation
Random logic synthesis
Micro-programming
Table look-up
connection diagram
ROW
ADDRESS
INPUTS
L'
Voo
L,
NC
L.
NC
{
DATA
OUTPUTS
[
NC
A.
NC
A.
NC
A,
B'
A,
B,
A,
B,
A.
B.
V ••
6 LINE
INPUTS
CHIP
ENABLE
B.
NC
Vss
TOPVIEW
typical application
+12V
B,
INPUT
I
INPUT
Vee
LOAD/RECIRCULATE
CONTROL
MM5016',
DM7400's
LOAD/RECIRCULATE
CDNTROL
'---------.,.
PAGE REFRESH
MEMORY
~_
L,
_ _~
CLOCK
OMB812',
-12V
~---.J
LINE REFRESH
MEMORY
L, 2
Note: For addition,l,nformltlon refer to AN40
99
.-
absolute maximum ratings
'
VGG Supply Voltage
'
":,
~
"
",
... ~
VSS - 30V,
Voo Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
,
VSS -15V
(VSS - 20)V
< VI N < (V SS +0.3)V
-65°C to +150°C
MM4240
MM5240
-55°C to +125°C
0
_25° C to + 70
e
Lead Temperature (Soldering, 10 sec)
300
0
e,
,
electrical characteristics
PARAMETER
'.
(Note 1)
CONDITIONS
MIN
TYP
MAX
UNITS
.'
,
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
IMS1 to GND
V
\Iss - 9.0
V
Vss - 1.0
MOS to TTL
6.8 Hi to VGG Plus One
Standard Series 54/74 Gate
Logical "1"
Logical "0"
Output Current Capability
Logical "0"
V O l)l
= Vss
+0.4 ,
V
V
+2.5
mA
2.5
- 6.0V
,Input Voltage Levels'
Logical "1"
Logical "0"
P~":,. . :~r S;--~r:p!~: ~:..~:.: c;·~~
100
"
'T'
'A
...,,0,_
'v v
MOS Load
25·
IGG (Note 2)
V IN
I nput Capacitance
f = 1.0 MHz, V IN = OV
f = 1.0 MHz, V IN = OV
Address Time (Note 3)
TACCESS
Output AND Connection
(Note 4)
= V ss
- 12 V
'I
rnA
pA
1
pA
5
25
8
40
pF
450
600
ns
pF
See Timing Diagram
TA
= 25°C
MOS Load
TTL Load
150
4
10
"
'.
Note 1: These specifications apply for VSS = +12V ±5%, V GG = -12V ±5%, and T A = -55°C to
+125°C (MM4240), TA =-25°Cto +700 C (MM5240) unless otherwise specified,
Note 2: The VGG supply may be clocked to reduce device power without affecting access time,
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns
Where N = Number of AND connections.
The number of AND ties in the MOS load configuration yao'be increased at the expense of MOS "0"
level.
100',
40
1
Input Leakage
,V GG Capacitance
V
V
Vss - 8.0
V ss - 2.0
performance ,characteristics
Guaranteed'Access Time (TAl
vs Supply Voltage
1200
1000
800
]
«
600
I-
Typical Access Time (TAl vs
Supply Voltage
12~ori
.j
1000 I-+-+--+-+-+---I-+--+-+-+-f-+-t--t
~....,;
10°C
r-I-~
---
2~ ..... 100..
800
-I"-~
200
200
13.2
12.0
"0.8
10.8
12.0
Vss & -VGG (V)
Voo Power Supply Current vs
Temperature'
Power Supply Current vs
Voltage
60
,
TA
50
--
40
C(
.§.
c
..E
--
30
20
10
13.2
Vss & -VGG (V)
10.8
=
-....
~-
25°C
50
~
40
Tlvp~CAl I-I-~
.....
I-'-
VGG =,.12.oV
I
T"'---
r-. I"'"-
TYPICAL
C(
.§.
c
..E
Vss = +12.oV
MA~
~ ..
30
.....
....... 100..
20
-r-.
- r-. _
--
...
10
13.2
12.0
-50 -25
0
25 50 15 100 125 150
TEMPE~ATURE
Vss & -VGG (V)
n;)
timing diagram/address time
+12V
OV
EON
14----TAccess ----4~
+12V
OV
+3V
1.5V
EOUT
+3V
1.5V
OV
I - - - - - - - - - - - - - - - - - -__ time
+12V
+3V-r--l
OV-.J
L
-12V
101
MM4240AA/MM5240AA character font
•••
• •••• •••••••••••••••••••••
:·111:.:1
I··! I · .1I••II··
I·· I ·11
·.1.·
• ••••
00
000000
I
I .1••• • ••••
~
000001
~
000010
~
000011
I
••••
~
000111
.... ....... .
·1·
M
000100
H
000101
"
000110
11.·1
1••11. II··..
I:·.:
: . : : .:: :
•....: •• :....: I: I 1•••1
.1.
12
13
14
15
16
17
11
I
001001
'
001010
,001011
001100
001101
001110
001111
•••• •••I:••••I ·•••
•••••• •• •• •
!:.
. · .1 .1 1.1••11. •I
•••• 1 . _• • •
!
ROW
OUTPUTS
ADDRESS
B, B2B3B. B5
001
010
011
100
101
110
111
••• ••
•• ••••
••• •••
I.:.: ! ••••••:.
~
n
n
IN
~
H
I···!
V
010000
010001
010010
010011
010100
010101
010110
010111
30
011000
31
011001
32
011010
33
011011
34
011100
35
011101
36
011110
37
011111
40
100000
41
100001
42
100010
100011
~
1•••1 ·1·
.. ..
.
:• •.:.
•• • •••••• : :•
•••••••
•• !
••
•
•• ••• I•
...
I
I .•:-.
•
•
•• •• •• •••••• •••
• ••• •
••
• • • •• •• II
i• ••
I I .1 I. ••••••••·1 I
•
•
••::•• •••
••
•
••
•
:. : ::
•
u
"
~
"
~
•
•
•
•
•
••
• • ••• •
i
I
•• ••
:••: ·1•
50
101000
51
.101001
.... ...
... ...
e
I
60
110000
I
61
110001
~
100101
~
~
~
100110
II
"
100111
I···
~
.....• .....•••.: I····
•••• •... ····1
•
101010
101011
101100
101101
101110
101111
••••
• •• 1••1.
I I···. ••
1_.. •••••
I •••••••••• I
~
110010
••••• ••• ••
71
111001
._..
100100
::1:: ··i·· :! .....
I •••
.' I ••':I II
•
••
70
111000
..
72
111010
~
M
H
110011
110100
••
••
•
••• •••••
• •••••
••
I:
••
73
111011
74
111100
110101
75
111101
"
110110
••
•
••
••
76
111110
~
..;:
110111
•
77
111111
Input ,ddreaes Ire in sill bit ASCII cod•• nd er. sflown in the sequence A5, A..... Ao; the octal equiwII.ntis.tso stlown for
"1,,,,1('.
102
ROMs
MM4241/MM5241 3072-bit static read-only memory
genera I description
features
The MM4241/MM5241 3072-bit static read-only
memory is a P-channel enhancement mode monolithic MOS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility. TRI-STATETM outputs provide wire ORed
capability without loading common data' lines or
reducing system access times. The ROM is organized in a 64 x 6 word by 8-bit memory organization. Programmable Chip Enables (CE 1 and CE 2 )
provide logic control of multiple packages without
external logic. A separate output supply lead is
provided to reduce internal power dissipation in
the output stages.
•
Bipolar compatibility
•
Standard supplies
No external
components required
+5V, -12V
TRI-STATE outpu.ts
•
Bus ORable output
•
Static operation
•
Multiple ROM control
No clocks required
Two programmable
Chip Enable lines
applications
•
Customer programs may be submitted for production in a paper tape or punched card format.
Character generator
•
Random logic synthesis
•
Micro-programming
•
Table look·up
logic and connection diagrams
Dual-In-Line Package
24
2
23
VGG
3
22
8,
B,
NC
4
21
8,
B,
B,
As
A,
MEMORY
ARRAY
Lo
VLL
1
CE,
CE,
NC
A,
A,
5
20
8,
8,
A,
6
19
8s
Bs
B,
A,
7
18
8,
L,
8,
L,
8s
A,
17
8,
16
B,
A,
10
15
8,
Lo
11
14
L,
Vss
12
13
L,
As
TOPVIEW
CE,o--------I
CE,o--------I
typical applications
TTL/MOS Interface
Vss
FIGURE 1. Power Saver for
Small Memory Arrays
FIGURE 2. Power Saver for
Large Memory Arrays
--,
r----,
I
I
I
I
I
L ___ -.J
I
I
-=
I
I
I
I
VGG
I
I
L ___ -.J
ANY TTL/DTL
DEVICE
CE,-----'
CE,------'
ASSUME IIV LL :IMIN = 11-3V II
VGG - VLL MIN = A (1.6 mA) (N) where N = 7 for 5 x 7 font.
N= Sfor6 x 8 font.
When CE 1 = 1, CE 2 = 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the third
state when disabled. The logic states of the chip enables are specified on the program tape.
103
absolute maximum ratings
VGG Supply Voltage
V LL Supply Voltage
Input Voltage
Storage Temperature Range
Operating Temperature Range
(V ss - 20) V
MM4241
MM5241
Lead Temperature (Soldering, 10 sec)
<
Vss - 20V
Vss - 20V
V IN
(V ss + .03)V
-65°C to +150°C
-55°C to +125°C
-25°C to +70°C
300°C
<
electrical characteristics
T A within operating temperature range, V ss
PARAMETER
Output Voltage Levels
Logical LOW
Logical HIGH
= +5V ±5%, V GG = V DO = -12V ±5%, unless otherwise specified.
CONDITIONS
IL
IL
= 1.6 rnA sink
= 100 J1A source
Input Voltage Levels
Logical LOW
Logical HIGH
MIN
TYP
.4
2.4
Vss
Vss
= 5, VGG = -12, V LL = -12, T A = 25°C
= 5, VGG = -12, V LL = -3, TA = 125°C
Input Leakage
VIN
= Vss - 10V
23
UNITS
V
V
Vss - 4.0
V
V
37
20
rnA
rnA
Vss - 2.0
Power Supply Current
Iss (Note 4)
Iss (Note 4)
1
J1A
Input Capacitance (Note 1)
f
= 1.0 MHz, VIN = OV
5
10
pF
Output Capacitance (Note 1)
f
= 1.0 MHz. VIN = OV
4
10
pF
Address Time (Note 2)
TA = 25°C, Vss = 5
VGG = V LL = -12V
700
900
ns
TAccEss
150
Output AND Connections (Note 3)
Note 1: Address is measured from the change of data on any input or chip enable line to the output
of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 2: Capacitances are measured periodically only.
Note 3:. The address time follows the following equation: T ACCESS = The specified limit + (N-1) x
25 ns where N = Number of AND connections.
Note 4: Outputs open.
104
MAX
20
performance characteristics
Guaranteed Access Time vs
Supply Voltage
Typical Access Time vs
Supply Voltage
1400
:; BOO
13.0
Pvo
c..>
c..>
r
1/
I
TYPICAL
OPERATING REGION
I I
(Y;~
~~
LLGUARA~TE~D
I-- I
OPERATING
I
It-
12.0
~
REGION.
I
I
11.0
8;0
10.0
12.0
14.0
16.0
Access Time vs Supply Voltage
IMM1~
---
I
1500 (")
~
1400
SEE SWITCHING TIME
TEST SET UP
-t-"'T
> 14.0
I
7
AMBIENT TEMPERATURE, TA ("C)
Vo - -9.0V ±5%
VOD = -9.0V ±5%
Vss =+5.0V -5%
f-M~l,2!~ ...
r-
Pvo - t - I
-Ir-1-.
15.0
0
-30-20 -10 0 10 20 30 40 50 60 70
I
~
2:
r-t-
L
150 I-- Vo = Voo = -9.0V ±5%
I-- PVoo ~ (lv~o X V'OO) = MEMORY ~R RAY I POWER DISSIPATION 100 I-I-- PVo = (lvo x yo)
= ~~:~rp~~~~~ POWER -
I
--
16.0
~~
I...
Access Time vs Ambient
Temperature
700
17.0
300
VOLTAGE (V o , Voo ) (V)
N
TA = _25°C to +7QoC
=GU~RANTEED
200
Pvoo _
Operating Region
= TYPICAL
\0.
I......
_~ Pvo
~
-9.0
g
Pvo~_
""" .
10'
150
~
....,1 ....
...., ....,
200
C
a:
~
= GUARANTEED
k::: V
:;:
c;:;
= TYPICAL
I
I I
~Ni11.!llAl
- - = TYPICAL
- - = GUARANTEED
~
~
:E~
1200 P1_
c:
1100 ~
;::
1300
800
1500 (")
~
700
1400
600
1300
N
~-I
s:
s:
~
:;
~
u
u
500
1200 ~
400
1100 ~
300
tODD ~
200
900 C;
s:
:;
~
c:t
~
0 10 20 30 40 50 60 70
~
"
CI)
1000 ~
~
900 <=
~
-I
-- =
GUARANTEED
-7.0
-8.0
-9.0
~
-10.0
-11.0
Vo (V)
AMBIENT TEMPERATURE eC)
test circuit
OUTPUT
CONDITIONS OF TEST
Input pulse amplitudes: OV to +5.0V
Input pulse rise and fall times <:: 10 ns
Speed measurements are referenced'to the
the TTl gate (tpd <:: 10 ns) CL .<:: 20 pF.
1.5V level
(unless otherwise noted), at the output of
Test Setup for MM1101 and MM1101A Speed Measurement
Note 1: All inputs of the MM11 01 A accept standard TTL outputs with VCC = +5.0V ±5%.
Note 2: Access time degradation as a function of load capacitance may be determined from the
following equations:
a) ta (T A = +25°C) = t0 1 + 0.32 CL ns
b) ta (T A = +70°C) = t0 + 0.35 CL ns
2
Where t0 1 , t0 = access time in ns for 1 TTL load at T A
2
respectively.
and
=
+25°C, and T A
=
+70°C
CL = pF
109
N
«
....
o
........
definition of timing parameters
ta Access Time: The time required for the output
to be valid from the initiation of an address
change.
~
~
....
«
....
o
........
twd Address Input to Write Pulse Delay: The
minimum time required after the initiation of an
address change and the start of the Write mode of
operation .
~
~
twp Write Pulse Width: The minimum pulse width
required for writing.
«....
tdh Data-Write Overlap: The minimum overlap
between the R/W and the data-in pulse .
....~
switching time ~aveforms
o
....
tt Chip Select to TRI-STATE Delay: The maximum delay from Chip Select to the attainment of
the high impedance state at the output during
chip deselect operation.
tc Chip Select to Address Bit Overlap: The maximum overlap between the initiation of address
change and the transition of the Chip Select to
the select mode.
~
tOORE~S
INPUT
A
---------_oJ:
1
1
:~ORE~; ~,.INPUT
1 . . . . ._ _ _ _ _ _
SELECT
:
r-
'-------.)'
CONT:r:.~1.~._____ 1--"1
___
DATA OUT
~
~
I
~t.===.J
I
--------------
_ _ _ _ _ _ _ __
1
1
CHIP-R
....
o
....
....
_-'~I.....
CHIP~
:
\ ' -_ _ _ _ _ __
1-,,-1
SELECT
I
1
R/W
1
--'-.0--'1
CONTRO'_-:-II
1
'----_.1
HIGS~~~~E~;:CE
BOTHORIVERS
1
"'"
1
"0"
'-_+_..JL
I
T ---------"
O.T.,N-I
f..::,,,. --t-",,--j
1
.
1
Note 1: tc must be less than 50 ns for minimum access times.
Note 2: While reading, data is guaranteed to remain true for a further 50 ns after the address is
changed if chip select is kept low.
110
,RAMs
MM1103 1024-bit fully decoded
dynamic random access read/write memory
general description
The MM1103 fully decoded dynamic 1024 word
x 1-bit per word read/write random access memory
is a monolithic MOS integrated circuit using silicon
gate low threshold technology. This device provides a non-destructive read out memory cell with
chip enable for easy selection when many outputs
are "OR"ed. Low power is achieved by the use of
dynamic logic and power dissipation occurs primarily during precharge. The MM 1103 is used for
main memory applications where large bit storage,
high performance and low cost are important.
Fast access time
Fast cycle time
Refresh cycle
Fully decoded
Easy memory expansion
Device protection
•
"OR"ing output
capability
Low power dissipation
Small package size
•
•
features
•
•
•
•
•
•
2 ms
Chip enable input
All I/O lines have
protection against
static charge
250 mW
18pinDIP
applications
300 ns max
480 ns read cycle
580 ns write cycle
•
•
Mainframe memory
Large buffer memory
connection diagram
Dual·1 n-Line Package
READ!
WRITE
A3
1-
r--18
A2
2-
r-- 17
Vss
A,
3-
r--16
CHIP
ENABLE
Ao
4-
r--15
PRECHARGE
5-
r--14
A.
6-
r--13
As
A6
7-
r--12
DATA
IN
A5
B-
r--ll
Voo
A7
9-
r--10
Vee
A.
-
DATA
OUT
TOP VIEW
111
absolute maximum ratings
All Input or Output Voltages With Respect
to the Most Positive Supply Voltage Vss
Supply Voltage V DD and Vss With
Respect to Vss
Power Dissipation at Room Temperature
Operating Temper
:!:
20
125
I
9.1'
M
?!
10
400
150 175
..........
-
Figure 1.
I
f II-i-I-r-I-I-n
I I I I
~
w
-....
........
1200
800
:
:;: 20 r- TA =25°C
:;; 15
i=
~ 10
_I-'"
a:
1600
MAXIMUM OUTPUT LOAD (pF)
AMBIENT TEMPERATURE (OC)
c
~
::::: 25 r-v+ _ V- = 20V-+-t-+'-+-t--I
J'9J'
N
>
~
.5
25
' , 'Ii
C - Ipeak tr
I I I I I
g:
o
Rise and Fall Times vs
Load Capacitance
2~
400
600
800
1000
LOAD CAPACITANCE, CL (pF)
Figure 2.
applications information
Power Dissipation Considerations
Where:
The power dissipated by the MH0012 may be
divided into three areas of operation = ON, OFF
and switching. The OF F power is approximately
30 mW and is dissipated by R2 when Pin 3 is in
the logic "1" state. The OFF power is neglible and
will be ignored in the subsequent discussion. The
ON power is dissipated primarily by 0 3 and R g .
and is given by:
(1)
122
ON Time
DC = Duty Cycle = ON Time & OFF Time
..
VIN-VSE3
liN IS given by
R1
and equation (1)
becomes:
PON = [
(VIN - V SE3 )IV-1
R1
The transient power incurred during switching is
given by:
PAC = .(v+ - V-)2 CL f
(3)
For V+ = OV, V- = -20V, C L = 200 pF, and
f = 5.0 MHz, PAC = 400 mW.
The total power is given by:
+
(V+ - V-)2]
~-
DC (2)
For VIN =2.5V, V SE3 =0.7V, V+ =OV, V- = -20V,.
and DC = 20%, PON == 200 mW.
PT = PAC + PON
PT
~
PMAX
For the above example, PT = 600 mW.
(4)
Clock Drivers
MH0013/MH0013C two phase MOS clock driver
general description
features
The MH0013/MH0013C is a general purpose clock
driver that is designed to be driven by DTL or
TTL line drivers or buffers with high output current capability. It will provide fixed width clock
pulses for both high threshold and low threshold
MOS devices. Two external input coupling capacitors set the pulse width maximum, below which
the output pulse width will closely follow the
input pulse width or logic control of output pulse
width may be obtained by using larger value input
capacitors and no input resistors.
• High Output Voltage Swings-up to 30V
• High Output Current Drive Capability-up to
500mA
• High Repetition Rate-up to 5.0 MHz
• Pin Compatible with the MH0009/MH0009C
• "Zero" @uiescent Power
j
schematic and connection diag,rams
12-Lead TO-8 Package
02
r--........---4..... 12 OUTPUT A
INPUT A,
INPUT A2 4 - - -....-
. . .--f
01
V-
5-----~--e---4
.....-
..... llV+
03
INPUT8,
& - - -.....-
....---t
INPUT 82
&...--111_-4-10 OUTPUT 8
TOP VIEW
04
typical applications:;
~t
+Vcc
r--
-----1
I
I
I
I
f
V-
INPUT
PULSE
I
I
OUTPUT:
:
PUlSE~r------;U"'---INPUT
PULSE
OUTPUT
:
:
PUlSE------;U,..----~U_
123
CJ
M
absolute maximum ratings
o"""
o
(y+ -
V-I Yoltage Differential
Input Current (Pin 2.4.6 or 8)
Peak Output Current
Power Dissipation (Figure 7)
Storage Temperature
Operatlnq Temperature MH0013
MH0013C
Lead Temperature (Soldering. 60 sec 1/16" from Case)
J:
~
..........
M
o"""
o
30Y
±75 mA
±600 mA
1.5W
-65°C to +150°C
_55°C to +125°C
O°C to +85°C
300°C
electrica I cha racteristics
J:
(Note 1 and Figure 8)
~
Logical "0" Output Yoltage
y+
lOUT = -50 mA liN = 1.0 mA
IOUT=-10mA I'N=1.0mA
Logical "1" Output Yoltage
lOUT = 50 mA
Power Supply Leakage Current
(y+ -
TYP
MIN
CONDITIONS
PARAMETER
MAX
UNITS
1.0
0.7
y+ - 0.5
Y
Y
Y- + 1.5
Y- + 2.0
Y
Y
100
J1A
y+ y+ -
-3.0
liN = 10 mA
V-I = 30Y
1.0
IOUT=I,N=OmA
Negative Input Yoltage Clamp
Y- - 1.2
I'N=-10mA
Y- - 0.8
Y
20
35
ns
35
50
ns
30
60
ns
40
50
80
ns
40
70
120
ns
340
420
490
ns
C, N = 0.0022 }1F
td 0 F F (Note 2)
R'N =
tfall (Note 2)
on
CL = 0.001 }1F
tfall (Note3)
Pulse Width (50% to 50%) (Note 3)
C'N = 500 pF
R'N =
tfall
On
Pulse Width (50% to 50%) (Note 3)
15
ns
20
ns
110
ns
Positive Output Yoltage Swing
y+ - 0.7Y
Y
Negative Output Yoltage Swing
Y- + 0.7Y
Y
Note 1: Min/Max limits apply oyer guaranteed operating temperature range of -55°C to +125°e for
MH0013 and oOe to +85°e for MH0013e. with V- = -20V and V+ = OV unless otherwise specified.
Typical values are for 25°C.
Note 2: Parameter values apply for clock pulse width determined by input pulse width.
Note 3: Parameter values apply for input pulse width greater than output clock pulse width.
TABLE I. Typical Drive Capability of One Half MH0013 at 70°C Ambient
0!f!'P'.!T OR!VF
CAPABILITY IN pF'
28
20
16
28
20
16
2.0
200
28
20
16
1.0
200
28
20
16
0.5
500
10
10
RISF TIMF
LlMITns2
750
50
200
350
10
1600
100
400
700
14
19
2300
400
1000
1700
19
34
45
4000
2800
5500
9300
130
183
248
100
4.0
!
Note 1: Output load is the maximum load that can be driven at 70°C without exceeding the package
rating under the given conditions.
Note 2: The rise time given is the minimum that can be used without exceeding the peak transient
output current for the full rated output load.
performance characteristics
FIGURE 1. Output Load vs Voltage
Swing
FIGURE 2. Transient Power vs Rep.
Rate vs CL
FIGURE 3. Transient Power vs Rep.
Rate vs CL
100
700
I, =
10 ns
§:
30
§:
E 600
a:
~ 500
~
t- 400
~
u; 300
20
z
ct
a:
10
20 ns 30 ns 40 ns 50 ns 60 ns
t-
1000
2000
3000
124
600
~
500
a:
~
t-
~
u;
z
ct
a:
200
t-
100
MAXIMUM OUTPUT lOAO (pFI
E
400
300
200
100
1~
2~
3D
4~
5~
6~
1D
REPETITION RATE (MHz)
1~
2~
3~
4~
5D
6~
REPETITION RATE (MHz)
7D
s:
:::E:
o
o
typical performance (cont.)
FIGURE 4. Average Internal Power vs
Output Swing vs Duty Cycle
FIGURE 5. Typical Clock Pulse Variations
vs Ambient Temperature
FIGURE 6. RIN vs CIN vs Pulse Width
~
w
"-
s:
600
20%
30%
30
::c
c
I-
~
,
>
I
TEST CIRCUIT (FIG. 8)
CIN = 2200 pF
CL = 1000 pF --.......
c:
!!E
500
w
...
20
~
~
:..:
(.)
g
10
(.)
400
~~
-
300
V
400
-55 -35 -15
I
5
I
I
25 45
I
65
~3000 1-+--+---I__-+------u.~I__.......~
Z
c(
~
t:1
l/
w
~ 2000
5
(")
~4_-+~~~~~~~~
I-
~ 1000 1-+--404'-A~4::.~-I___._~
!:
I
85 105 125
100
AMBIENT TEMPERATURE (OC)
AVERAGE POWER (mW)
o
o
w
(.)
I-
~~
FOR TYPICAL APPLICATION
f-OM7830/8830 DRIVER
CIN = 4300 pF
300 I--r-CL = 1000 pF
-
I
200
100
-
"",
~
::I:
200
300
400
PULSE WIDTH (n5)
FIGURE 7. Package Power Derating
1.5
~
~
1.0
pulse width
"
~
IX
;:
~
.5
25
50
75
~
100
125
150 175
AMBIENT TEMPERATURE (Oc)
Maximum output pulse width is a function of the
input driver characteristics and the coupl ing
capacitance and resistance. After being turned on,
the input current must fall from its initial value
II N peak to below the input threshold current
liN min ~VBE/R1 for the clock driver to turn
off. For example, referring to the test circuit of
Figure 8, the output pulse width, 50% to 50%, is
given by
circuit operation
Input current forced into the base of 01 through
the coupling capacitor CIN causes 01 to be driven
into saturation, swinging the output to
V- + VeE (SAT) + VOIOOE'
When the input current has decayed, or has been
switched, such that 01 turns off, 02 receives base
drive through R2, turning 02 on. This supplies
current to the load and the output swings positive
to V+ - V SE '
II N peak
+ ROC IN In - - liN min
== 400
ns.
For operation with the input pulse shorter than
the above maximum pulse width, the output pulse
width will be directly determined by the input
pulse width.
It may be noted that 01 always switches off
before 02 begins to supply current; hence, high
internal transient currents from V+ to V-: cannot
occur.
Typical maximum pulse width for various CI Nand
RIN values are given in Figure 6.
ac test circuit
timing diagram
-5V
A Input pulse width
WI:!~kPUlse
B '"",,,'.. w,dlh
sets clock pulse
-
g~~~~:UlSE
~
V,,..
4
1
90 % - - - - -
10%
--
"0' --10%
v,.
r--"o"
111%
011
5V
W
~----
11
3
'
all
"OUf
r.-;..:...:....-=...,-l----~- Vz' 20Y
_",J\i=OtoSVpulse,f=SOOkHz,DC=50%,t,andt,,,IOIl5
Figure 8
125
fan-out calculation
The drive capability of the MH0013 is a function
of system r~quirements, i.e., speed, ambient temperature, voltage swing, drive circuitry, and stray
wiring capacity.
The following equations cover the necessary calculations to enable the fan-out to be calculated for
any system condition. Some typical fan-outs for
conditions are given in Table 1.
maintained for the full duration of the pulse
width.
4. Package Power Dissipation
Total Average Power = Transient Output Power +
Internal Power + Input
Power
Transient Current
The maximum peak output current of the MH0013
is given as 600 mAo Average transient current required from the driver can be calculated from:
C L (V+ - V-)
I
=
TR
(1)
This can give a maximum limit to the load.
Figure 1 shows maximum voltage swing and
capacitive load for various rise times.
1. Transient Output Power
The average transient power (PAC) dissipated is
equal to the energy needed to charge and discharge
the output capacitive load (C L ) multiplied by the
frequency of operation (F).
PAC = C L x (V+ - V-)2 xF
(2)
Figures 2 and 3 show transient power for two different values of (V+ - \/-) versus output load and
frequency.
2. Internal Power
"0" State
.::>ldlt:1
PINT
=
(V+ - V-)2
R2
x Duty Cycle.
(3)
Figure 4 gives various values of internal power
versus ouptut voltage and duty cycle.
3. Input Power
The average input power is a function of the input
current and duty cycle. Due to input voltage
clamping, this power contribution is small and can
therefore be neglected. At maximum duty cycle of
50%, at 25° C, the average input power is less than
10mW per phase for RINC IN controlled pulse
widths. For pulse widths much shorter than
R IN C I N, and maximum duty cycle of 50%, input
power could be as high as 30 mW, since II N peak is
126
Power Dissipation
From the graph of power dissipation versus temperature, Figure 7, it can be seen that an
MH0013C at 70°C can dissipate 1W without a heat
sink; therefore, each half can dissipate 500 mW.
Transient Peak Current Limitation
From Figure 1 (equation 1), it can be seen that
at 16V and 30 ns, the maximum load that can be
driven is limited to 1140 pF.
Ayerage Internal Power
Figure 4 (equation 3) gives an average power of
102 mW at 16V 40% duty cycle.
Input power will be a maximum of 8 mW.
Transient Output Power
Negligible «3 mW)
I
Typical Example Calculation for One Half
MH0013C
How many MM506 shift registers can be driven by
an MH0013C driver at 1 MHz using a clock pulse
width of 400 ns, rise time 30-50 ns and 16 volts
amplitude over the temperature range 0-70°C?
Fc.- onG hu~f of the !\~~i0013C
500 mW = 102 rnW + 8 mW
+ transient output power
390 mW = transient output power
Using Figure 2 (equation 2) at 16V, 1 MHz and
390 mW, each ha"lf of the MH0013C can drive a
1520 pF load. This is, however, in excess of the
load derived from the transient current I imitation
(Figure 1, equation 1), and so a maximum load
of 1140 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load is 80 pF. Therefore the number
·
d·
. 1140
.
a f d eVlces riven IS 80 or 14 registers.
For nonsymmetrical clock widths, drive capability
is improved.
s:
::I:
o
o
Clock Drivers
N
c.n
.........
s:
::I:
MH0025/MH0025C two phase MOS clock driver
o
o
N
c.n
n
general description
features
The MH0025/MH0025C is monolithic, low cost,
two phase MOS clock driver that is designed to be
driven by TTL/DTL line drivers or buffers such as
the DM932, DM8830,or DM7440. Two input
coupling capacitors are used to perform the level
shift from TTL/DTL to MOS logic levels. Optimum
performance in turn-off delay and fall time are
obtained when the output pulse is logically controlled by the input. However, output pulse widths
may be set by selection of the input capacitors
eliminating the need for tight input pulse control.
• 8-lead TO-5 or 8-lead dual-in-line package
• High Output Voltage Swings-up to 30V
• High Output Current Drive Capability-up to
1.5A
• Rep. Rate: 1.0 MHz into> 1000 pF
• Driven by DM932, DM8830, DM7440(SN7440)
• "Zero" Quiescent Power
connection diagrams
Dual-In-Line Package
Metal Can Package
v'
N.C. I
8 N.c.
">0---1-- 7
INPUT A 2
6
:>o---+-- 5
INPUT B 4
OUTPUT A
v'
OUTPUT B
Note: Pin4 connected to case.
TOPVIEW
TOPVIEW
MH0025H, MH0025CH
MH0025CN
typical application
ac test circuit
timing diagram
-
A.ln.putpuisewidth
> clock pulse
Input waveform:
PRR=0.5MHz
Vp .p = 5.0V
t r =t,-S;10ns
Pulse width:
A. 1.0p,
B.200n,
8. In.put pulse w,dth
:1~t~IOCk pulse
Clock pulse
output
~
5V
V
1N
~
90%
~
-----5V
V'N
.~_ _ _ _ _ OV
10%
-tdON
10%
rrtd_OF_F_ _ _ _
V3=OV
10%
VOUT
*01 is a selected high speed NPN switching transistor.
1'----'1-+------
V2 = -16V
127
(J
Il)
N
absolute maximum ratings
o
o
(v+ - V-I Voltage Differential
I nput Current
Peak Output Current
Power Dissipation
Storage Temperature
Operating Temperature MH0025
MH0025C
Lead Temperature (Soldering, 10 sec)
:t
~
..........
Il)
N
o
o
:t
~
30V
100 mA
1.5A
See Curves
-65°C to +150°C
-55°C to +125°C
to +85°C
300°C
aOc
electrical characteristics
PARAMETER
(Note 1) See test circuit.
CONDITIONS
TYP
MIN
.....
30
ns
25
50
ns
30
60
ns
60
90
120
ns
100
150
250
ns
CIN = .001 fJ.F
TdoFF (Note 2)
RIN =
>-
on
C L = .001 fJ.F
T fall (Note 2)
T fall (Note 3)
P.W. (50% to 50%) (Note 3)
Positive Output Voltage Swing
V IN = OV, lOUT
-1 mA
=
UNITS
15
TdoN
T rise
MAX
V+ - 1.0
500
ns
V+ - 0.7V
V
V- + 1.5V
V- + 0.7V
Negative Output Voltage Swing liN = 10 mA, lOUT = 1 mA
V
Note 1. Min/Max limits apply across the guaranteed operating temperature range of -55°C to +125°C
for MH0025 and O°C to 85°C for MH0025C. Typical values are for +25°C.
Note 2. Parameter values apoly for clock pulse width determined by input pulse width.
Note 3. Parameter values apply for input pulse width greater than output clock pulse width.
performance characteristics
Package Power Derating
Transient Power vs Rep. Rate
DC Power (PDC) vs Duty Cycle
400
~
z
1.4 -
i=
~
1.2
~
1.0
a:
0.8
~
0.6
Q
--
~
xc(
::!E
0.4
E
~
~
25
E
200
~
Q
~
,~
40
100
20
75 100 125 150
.5
1.0
1.5
(V+ - V-)2f CL
~ 2000
I-
~ 1600
5 1200
o
~
~ K.
\\ 'k' ~
\\
\0
V = 20V, TA
1100
~
""i'... .........
........ 1'0.......
0.. r--....
::I:
I0
w
.::::
- v'
= 16V, TA ~ 70 C
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
~
~
--
I--
L
12-8
.
(PMAX ) (lk) - (V+ - V-)2 (OC)
<
(lpk)
--
(t) (1 k) (V+ - V-)2
-
V+ - V-
(t r )
lk
In :::x
-;--
INPUT PULSE WIDTH r-f-'/
..... ~ ;...r
V ....-::: ~ i-<
50llPUll UP
~~ ~
200
-f--
DRIVER
/
300
~
RaCIN
1
I
600
1000 1400
1800
CIN (pF)
<
60
(V+ - V-)2 (DC)
V
I-- - I - ~44D
.
./ ~
~
V
J> ~ ~i"'"
FREOUENCY (MHz)
C
50
oJ932 bRIJR
500
100
,65+
OUTPUT PULSE WIOTH
PLUS9Dn..
700
§i:
MH0025CN'V'-V"16V.TA070~": f"'B"
MH0025C, v'
900
25 C
-r.......
........ -7."""
=
OUTPUT PULSE WIOTH VS Co. FOR LONG
INPUT PULSES.
FOR INPUl PULSE
c
...... ~ t'....
800
400
~
40
Output P.W. Controlled by CIN
j~H0025lN. v·!v·.,Jv,T A ol15C
MH0025C; V'
30
Poc
OC=211'"
[\,
20
OUTY CYCLE (%)
Maximum Load Capacitance
3200
10
2.0
PULSE REPETITION RATE (MHz)
PAC =
~. 2400
80
c(
I-
TEMPERATURE (OC)
~ 2800
100
60
a:
50
120
z
o
i=
~
en
z
"
0
300
a:
I-
0.2
-25
~
~
~
"
"
::!E
::!E
140
MH0025CN SOLDERED INTO PC
BOARO WITH 8 Cu CONOUCTORS
2 OZ, .03 IN. WIDE
0
~
160
---MH0025H &MH0025CH STILL AIR
IMAX
::
IMIN
==~:::~
Peak current delivered by driver
R,
lk
2200
70 85
3:
o
::J:
applications information
o
N
Circuit Operation
Input current forced into the base of 01 through the
coupling capacitor CIN causes 0, to be driven into
saturation, swinging the output to V- + V CE(sat) +
VDiode·
When the input current has decayed, or has been
switched, such that 0, turns off, O2 receives base
drive through R 2 , turning O 2 on. This supplies
current to the load and the output swings positive
to V+ - V BE .
It may be noted that 0, must switch off before
O2 begins to supply current, hence high internal
transients currents form V- to V+ cannot occur.
...---.......- 0 v'
R~
~
l
112
,.,..,.C'N
~.....
I ...
_ _~-
CI)
7.5
-
~-
E
I-
~
a:
a:
12
5.0
-75 -50 -25
0
25
50
u
~/
/'
~
-
_.......
75 100
BO
V
L
~
1.0
0.5
125
2.0
1.5
2.5
INPUT VOLTAGE (V)
TEMPERATURE rC)
FREQUENCY (MHz)
70
10
/'
V+ -V- = 17V
60
c
~
6.5
50
TA = 25 'C
V+ = 20V
V- = OV
-
I-
~I"""
4.0
40
=>
7.0
6.0
3,0
30
Input Current vs Input Voltage
;;t
./
V+ -V- = 20V
100
2.0
20
DUTY CYCLE (%)
14
=>
1,0
10
150
16
B.5
BOO
~
100
(V+ _ V-)2
Poe = ~(DC)
~
Supply Current vs Temperature
900
E
75
V
~V"
AMBIENT TEMPERATURE (OC)
Transient Power (PAC) vs
Frequency
§'
50
.JtIc
/~
/~
I/I\"
40
AMBIENT TEMPERATURE
V
V
V/V' lY
BO
0.5
/
~
V
V
v: - V== 17V~ V
V -V =12V
120
~
0.2
V+ - V- = 20V --,
2BO
~
,J'f'
TA = 25°C
CL = 0
360
Optimum Input Capacitance vs.
()!ltPI!t P;I!"P V\!jr!th
25
25
BOO
V+ - V- = 20V
V+ - V- = 15V to 20V
20
.~
I-
20
...... ~ ~ ~"""
c:
V+ - V-= 20~
15
~~
CI)
a:
V+ - V- = 17V
~
15
~
10
./
Ro = 5012
TA =25°C
I
5
200
400
600
BOO
I
I
1000
5
1200
c:
13
~
;::::
12
u...
u...
11
0
;2
a:
=>
Io/l
Z
0
;2
a:
=>
-
1+
1_
1
V - V = 204
CIN = CL = 1000 pF
Ro= 5011
1
10
./
. /~
tOFF
I-
-75 -50 -25
0
20
c:
o
UJ
CI)
50
I-
300
=>
400
600
0
200
100
,....
1..,..0'
-+-:::r:
CL~~
15
-
~
BOO
-
200
1000
""","
400
600
100 125
25
-
I-
vi -
I
20
c:
15
:lE
.....I
.....I
CL = 0
~
10
C
L
V~ = 2riv
0
25
50
75
TEMPERATURE (OC)
100 125
... V
-
I
~OOO 1 F
~
L.J..-...11
CL = 500 pF
f-~ ~
I
~
~i""'"
-
~
I
I
-75 -50 -25
1000 1200
Fall Time. vs Temperature
-...r-..
75
BOO
INPUT CAPACITANCE, CIN (pF)
;::::
10
~I'"
... V
~
V+ - V- = 20V
CL = 1000 pF
~
vV'
CL = 0
i '1-0...
25
400
~
~
200
~
I-
;::::
a:
.........
j
500
UJ
~
Ro = 5012
TA = 25°C
:lE
TEMPERATURE (OC)
132
/'
V
,/
~
V
~
Rise Time vs Temperature
V
tON
V'
25
1
-
600
LOAD CAPACITANCE (pF)
Turn-On & Turn-Off Time
vs Temperature
CI)
V
V
",.
~
/
LOAD CAPACITANCE (pF)
14
x
CL = 1000 pF
TA = 25°C
0
.....I
.....I
~
o
:lE
;::::
~V
10
700
I-
c:
/~~
w
g
-75 -50 -25
0
25
50
.,,-
75
TEMPERATURE (OC)
/'
100 125
3:
:r:
o
o
N
m
.........
3:
:r:
o
o
typical applications
DC Coupled MOS Clock Driver
Transistor Coupled MOS Clock Driver
TTL INPUTS {
"
INPUT
"
}
N
TOSHIF'
REGISTERS
m
INPUT
n
Logically Controlled AC Coupled Clock Driver
TOAD,nIONAl
SHIFT REGISTERS
}
f'_----I
~
a
b
ClOCKINPUT-lf"
ONESHOTOUTPUI -AOJPULSEWIDTH
PHASE ONE OUTPUT
PHASE TWO OUTPUT
Precharge Driver for MOS RAM Memories
ac test circuit
switching time waveforms
~RNF:~VMHI
PW:O.5#s
. ,,-I,<10ns
133
(.)
CD
N
application information
::E:
~
1.0 Introduction
o
o
........
The MH0026 is capable of delivering 30 watts
peak power (1.5 amps at 20V needed to rapidly
charge large capacitative loads) while its package is
limited to the watt range. This section describes
the operation of the circuit and how to obtain
optimum system performance. If additional design
information is required, please contact your local
National field application engineer.
CD
N
o
o
::E:
~
a simplified diagram, Dl (Figure 3) provides 0.7V
dead zone so that 0 3 is turned ON for a rising
input pulse aOd O2 OFF prior to 0 1 turning ON a
few nanoseconds later. D2 prevents zenering of the
emitter-base junction of O 2 and provides an initial
discharge path for the load via 0 3 . During a falling
input, the stored charge in 0 3 is used beneficially
to keep 0 3 ON thus preventing O2 from conducting until 0 1 is OFF. 0 1 stored charge is quickly
discharged by means of common-base transistor
04 .
2.0 Theory of Operation
Conventional MOS clock drivers like the MH0013
and similar devices have relied on the circuit
configuration in Figure 1. The AC coupling of an
input pulse allows the device to work over a wide
range of supplies while the output pulse width
may be controlled by the time conStant - R 1 X C1 .
The complete circuit of the MH0026 (see schematic on page 130 basically makes Darlingtons out
of each of the transistors in Figure 3.
-o v+
r - - - -....
_ -....-<>v+
EXTERNAL
C1
'No1~
~~""'-<>OUT
EXTERNAL
C1
0-1 ~
IN
"""""""""'-""0
FIGURE 1. Conventional MOS
CI~ck
.. ! .. .... 1
.
~
. !
. . . . . . . . . . _ . . . . . . . . . . . . . . . :::) .......... VII ..... VII ...... '"I \i 10.0
tv ..... ""'u,
FIGURE 3. Simplified MH0026
.. ~
!""'!
UII"'-A
......
-..
..... 1
1.
are large geometry devices but Cob now limits
useful output rise time. A high voltage TTL output
stage (Figure 2) could be used; however, during
switching until the stored charge is removed from
O}, both output devices conduct at the same time.
This is familiar in TTL with supply line glitches in
the order of 60 to 100 mAo A clock driver built
this way would introduce 1.5 amp spikes into the
supply lines.
_ -....-<>v+
EXTERNAL
C1
IN
OUT
o1l--o
D1
L-.....- -....~....Ov-
FIGURE 2.
When the output of the TTL input element (not
shown) goe!i to the logic "1" state, current is
~uf.Jf.Ji;tJ dit0u~h C'N tv lli" i..;ci~t 0f Q} oi,J O 2
turning them ON, and 0 3 and 0 4 OF F when the
input voltages reaches 0.7V. Initial discharge of
the load as well as E-8 protection for 0 3 and 0 4
are provided by D 1 and D 2 . When the input
voltage reaches about 1.5V, 0 6 and 0 7 begin to
conduct and the load is rapidly discharged by 0 7 .
As the input goes low, the input side of C, N goes
negative with respect to V- causing 0 8 and 0 9 to
conduct momentarily to assur~ rapid turn-off of
O2 and 0 7 respectively. When O} and O2 turn
OFF, Darlington connected 0 3 and 0 4 rapidly
charge the load toward V+ volts. R6 assures that
the output will reach to within one VB E of the
V+ supply.
The real secret of the device's performance is
proper selection of transistor geometries and resistor values so that 0 4 and 0 7 do not conduct at
the same time while minimizing .delay from input
to output.
3.0 Power Dissipation Considerations
Alternate MOS Clock Drive
Unique circuit design and advanced semiconductor
processing overcome these clasic problems allowing the high volume manufacture of a device, the
MH0026, that delivers 1.5A peak output currents
with 20ns rise and fall times into 1000pF loads. In
134
v-
Drive
D2 provides 0.7V of dead-zone thus preventing 0 1
and O 2 from conducting at the same time. In
..... _
OUT
There are four considerations in determining
power dissipations.
1. Average DC power
2. Average AC power
3. Package and heat sink selection
4. Remember-2 drivers per package
~
::I:
application information (con1t)
The total average power dissipated by the MH0026
is the sum of the DC power and AC transient
power. The total must be less than given package
power rati ngs.
o
o
N
en
Thus for RAM address line applications, package
type and heat sink technique will limit drive
capability rather than AC power.
.........
~
::I:
o
o
N
en
3.2 AC Transient Power (per driver)
AC Transient power is given by:
Since the device dissipates only 2mW with output
voltage high (MaS logic "0"), the dominating
factor in average DC power is duty cycle or the
percent of time in output voltage low state (MaS
logic "1"). Percent of total power contributed by
PDC is usually neglible in shift register applications
where duty cycle is less than 25%. PDC dominates
in RAM address line driver applications where
duty cycle can exceed 50%.
where: f = frequency of operation
C l = Load capacitance (including all
strays and wiring)
Example 3: (V+
= +5V,
V-
= -12V)
C l (nF) X 10-9
DC Power is given by:
(lS(LOW))
X
(
ON time
)
OFF time-ON time
or Poc = (Output Low Power) X (Duty Cycle)
+
_
Vs
where: IS(Low) = Is @ V - V = 20V
Example 1: (V+ = +5V, V- = -12V)
a) Duty cycle = 25%, therefore
PDC
= 17V X
PDC
= 145mW worst-case, each side
40mA X 17/20 X 25%
PDC = 109mW typically
b) Duty cycle = 5%
PDC =21mW
c) See graph on page 132
The above illustrates that for shift register applications, the minimum clock width allowable for the
given type of shift register should be used in order
to drive the largest number of registers per clock
driver.
Example 2: (V+ = +17V, V- = GND):
a) Duty cycle = 50%
PD C
(")
PAC = 17 X 17 X f(MHz) X 10 6 X
3.1 DC Power (per driver)
POC = (V+ -V-) X
PAC = (V+ - V-)2 X f X C L
= 290mW
worst-case
PDC = 218mW typically
b) Duty cycle = 100%
POC = 580mW
PAC = 290mW per MHz per 1000pF
Thus at 5MHz, a 1000pF load will cause any driver
to dissipate one and one half watts. For long shift
registers, a driver with the highest package power
rating will drive the largest number of bits for the
lowest cost per bit.·
3.3 Package Selection
Power ratings are based on a maximum junction
rating of 175°C. The following guidelines are
suggested for package selection. Graphs on page 132
illustrate derating for various operating temperatures.
3.31 TO-5 ("H") Package: Rated at 600mW still
air (derate at 4.0mWtC above 25°C) and 900mW
with clip on heat sink (derate at 6.0mWtC above
25°C). This popular hermetic package is recommended for small systems. Low cost (about 10¢)
clip-on-heat sink increases driving capability by
50%.
3.32 8-Pin ("N") Molded Mini-DIP: Rated at
600mW still air (derate at 4.0mW/oC above 25°C)
and 1.0 watt soldered to PC board (derate at
6.6mWtC). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly
where automatic insertion is used. (Please note for
prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down.)
3.33 TO-8 ("G") Package: Rated at 1.5 watts
still air (derate at 1OmWtC above 25°C) and 2.3
watts with clip on heat sink (Thermal loy type
215-1.9 or equivalent-derate at 15mWtC).
Selected for its power handling capability and
moderate cost, this hermetic package will drive
very large systems at the lowest cost per bit.
135
u
co
N
application information (con't)
J:
3.4 Summary-Package Power Considerations
4.0 Pulse Width Control
The maximum capacitative load that the MH0026
can drive is thus determined by package type, heat
sink technique, ambient temperature, AC power
(which is proportional to frequency and capacitive
load) and DC power (which is principally determined by duty cycle). Combining equations previously given, the following formula is valid for
any clock driver with negligible input power and
negligible power in output high state:
The MH0026 is intended for applications in which
the input pulse width sets the output pulse width;
i.e., the output pulse width is logically controlled
by the input pulse. The output pulse width is given
by:
o
o
~
........
CO
N
o
o
J:
~
Two external input coupling capacitors are required to perform the level translation between
TTLiDTL and MOS logic levels. Selection of the
capacitor size is determined by the desired output
pulse width. Minimum delay and optimum performance is "ttained when the voltage at the input
of the MHOb26 discharges to just above the
devices threshold (about 1.5V). If the input is
allowed to discharge below the threshold, to F F
and t f will be degraded. The graph on page 132
shows optimum values for CIN vs desired output
pulse width. The value for CIN may be roughly
predicted by:
3
CIN = (2 X 10- ) (PW)OUT
10- 3
C L (max in pF) = -n- X
Pmax(mw)(T A,pkg) X Req - (V+ - V-)2 X (Dc) X 10 3
(V T
- V )2 X Req X
f(MHz)
C L (max in pF) = .5 X 10- 3 X
Pmax (mW) X 500 - V S 2 X Dc X 103
V S 2 X 500 X f(MHz)
Where: n = number of drivers per pkg. (2 for
the MH0026)
For an output pulse width of 500ns, the optimum
value for CI N is:
Pmax(mw)(T A , pkg) = Packagepower
rating in milliwatts for given package,
heat sink, and max, ambient temperature (See graphs)
The MH0026's peak output current is limited to
1.5A. The peak current limitation restricts the
maximum load capacitance which the device is
capable of driving and is given by:
= (V+ - V-)/IS(Low) = 500 ohms (worst
case over temperature for the MH0026 or
660 ohms typically)
Req
dv
1= C L dt
The rise time,
predicted by:
Vs = (V+ - V-I = total supply voltage across
device
< 1.5A
tp for various loads may be
= (IlV) (250 X 10- 12 + C L )
IIV = The change in voltage across C L
tr
= Duty Cycle =
Where:
Time in output low state
Time in output low + Time in output high state
:=:: V+ - VC L = The load capacitance
For V+ - V- = 20V, C L = 1000pF, tr is:
Table I illustrates MH0026 drive capability under
various system conditions.
tr:::: (20V)(250 X 10- 12 + 10- 12 )
= 25ns
TABLE 1. Worst Case Maximum Drive Capability for MH0026*
PACKAGE TYPE
Max.
Operating
Frequency
TO-8WITH
HEAT SINK
TO-8
FREE AIR
MINI-DIP
SOLDERED DOWN
.
~
60°C
85°C
60°C
85°C
60°C
TO-S AND MINI-DIP
FREE AIR
Max.
Ambient
85°C
60°C
85°C
...
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.5k
500kHz
10%
6.5k
5.1k
4.1k
3.2k
2.7k
2k
1.5k
lMHz
20%
2.9k
2.2k
1.8k
l.4k
1.1k
5.8k
1.1k
840
600
430
2MHz
25%
850
650
550
400
280
190
5MHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
l.4k
Uk
-
*NOTE: Values in pF and assume both sides in use as non-overlaping 2 phase driver; each side
operating at same frequency and duty cycle with (V+ -V-) ~ 17V
136
1000pF
5.0 Rise & Fall Time Considerations(Note 3)
Req = equivalent internal resistance
Dc
= (2 X 10- 3 )(500 X 10-9 ) :=::
CI N
3:
::J:
o
o
application information (con/t)
For small values of C L , equation above predicts
optimistic values for t r . The graph on page 132
shows typical rise times for various load capacitances.
The output fall time (see Graph) may be predicted
by:
t f == 2.2R(C s + ~
hF E + 1
6.0 Clock Overshoot
The output waveform of the MH0026 can overshoot. The overshoot is due to finite inductance of
the clock lines. It occurs on the negative going
edge when 0 7 saturates, and on the positive edge
when 0 3 tu rns OFF as the output goes through
V+ - V be . The problem can be eliminated by
placing a small series resistor in the ouput of the
MH0026. The critical valve for Rs = 2v'LCL where
L is the self-inductance of the clock line. In
practice, determination of a value for L is rather
difficult. However,R s is readily determined emperically, and values typically range between 10 and
51 ohms. Rs doe's reduce rise and fall times as
given by:
7.0 Clock Line Cross Talk
At the system level,voltage spikes from ¢i may be
transmitted to ¢2 (and vice-versa) during the
N
transItIon of --~- OUTPUT A
0-...--.....-1
V-
V'
~~~-~-oOUTPUT 8
5
~--~~---4~----~---
OUTPUT 8
INPUT 8
09
__-oV-
TOP VIEW
typical applications
TTL to MM1103 High Speed Memory Interface
"1'
7
T:tl'
2
TTL
INPUTS
B
INPUTS B
.,/
.,
TTL to Negative level Interface
(DC Coupled MOS Clock)
TTL
INPUTS
I'
B
3
To MM11034k by 16 bit memory.rr.y. Rise
Indf.Utimeare25nstypmto6DOpFlold
Q1
¢;Z
nLJA
INPUTSlB
13
Not.: Minimize may bOlrd ClPlcitince on interconnlCtioDI be1WHn lM75451 A .nd MH0Q27CN
=rn:~~tlIrnaIPUII.upres!JtOr$(Rx·lkJm'Ybe'ddedtoimproverisetimebvabout.
138
Note', RxUkl OptIOnal to dec,ease rise time
lOutputswrng--flVto4V,delaYtime-20ns
j Rrselndfllltrme-25nsforCl =800pF
~bsolute
maximum ratings
Continuous Supply Voltage
Peak Supply Voltage (10 ms)
Input Voltage
Output Voltage
Peak Output Current (each side)
Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
25V
30V
25V
Vee
1.2A
1.0W
O°C to 85°C
-65°C to +150°C
300°C
(T A
= +25°C, v+ = 24V,
CONDITIONS
~
Low Level Input Current (Ill)
V IN
High Level Output Voltage (V OH )
= 4 mA
IOl = 100 rnA
Cl = 600 pF
Cl = 600 pF
Cl = 600 pF
Cl = 600 pF
Low Level Output Voltage (VOL)
Turn-On Time (t dON )
Turn-Off Time (t dOFF )
Rise Time (t r )
Fall Time (tf)
OV
IOH
VeL
= 21V; unless otherwise
LIMITS
UNITS
MIN
TYP
MAX
18
25
32'
20.75
21.0
21.25
0.7
5
specified)
1.0
rnA
V
V
15
ns
5
15
ns
20
45
ns
15
35
ns
Note 1: Rating applies for device soldered to a printed circuit board with 8 copper conductors
,.03 inches wide. For ambient temperatures above 25°C, derate linearly at 6.7 mwtOC,
For specificatiQns on other National MOS clock
drivers and interface circuits, see the following
data sheets:
MOS Clock Drivers
Single Phase, TTL Input DC Coupled - MH0007
Two Phase DC Coupled - MH0009
Single Phase, High Speed DC Coupled - MH0012
Two Phase AC Coupled - MH0013
Two Phase Low Cost - MH0025
Two Phase High Speed AC Coupled - MH0026
MOS Interface Circuits
Dual Voltage Translator - DM7800/DM8800
Dual High Sp~ed Translator - DH0034/DH0034C
Quad 2-lnput NAND TTL/MOS InterfaceDM8810,DM8811
Quad 2-lnputAND TTL/MOS Interface - DM8810
Hex Inverter TTL/MOS, Interface - DM8812
Dual Peripherial Drivers - LM3QO,LM351/
LM75450A,LM75451A
'
Analog Comparator to MOS - LM 111 series
Dual Analog Comparator to MOS - LH2111 series
139
3:
3:
~
c.n
Analog Switches
o
3:
3:
.........
c.n
c.n
MM450/MM550, MM451/MM551
MM452/MM552,MM455/MM555 MOS analog switches
..o
general description
The MM450, and MM550 series each contain
four p channel MaS enhancement mode transistors built on a single monolithic chip. The four
transistors are arranged as follows:
MM450, MM550
(V TH = 2 volts) permits operations with large analog input swings (± 10 volts) at low gate voltages
(-20 volts). Significant features, then, include:
Dual Differential
Switch
Four Channel
Switch
Four MaS Transistor Package
Three MaS Transistor Package
MM451, MM551
MM452, MM552
MM455, MM555
•
Large Analog Input Swing
•
Low Supply Voltage
±10 Volts
V BU LK
VGG
These devices are useful in many airborne and
ground support systems requiring multiplexing,
analog transmission, and numerous signal routing
appl ications. The use of low threshold transistors
•
Low ON Resistance
•
Low Leakage Current
•
I nput Gate Protection
•
Zero Offset Voltage
VI N
V IN
= +10
= -20
-:-10V
Volts
Volts
150Q
+10V
75[2
200 pA @ 25°C
Each gate input is protected from static charge
build-up by the incorporation of zener diode protective devices connected between the gate input
and device bulk.
schematic and connection diagrams
TOP VIEW
TOPVIEW
TOPVIEW
BULK
OUTPUT
(SOURCE)
N.C.
GATE 2
GATE 1
ORAIN4
ORAIN2
GATE2
SOURCE 2
BULK
NOTE: Pin 5 connected to case and device bulk.
NOTE: Pin 5 connected to case and device bulk.
MM450, MM550
TOPVIEW
SOURCE 4
GATE 4
SOURCE 1
BULK
14
ORAIN 1
SOURCE J
GATEJ
ORAINJ
NOTE 1: Pins 1 and 8 connected to case and
device bulk. Drain and Sou roe may be
interchanged. MM452F, MM552F.
NOTE 2: MM452D and MM552D (dual·in·line
packages) have same pin connection~ as
MM452F and MM552F shown above.
MM451. MM551
typical applications
BULK
BULK
NOTE: Pin 5 connected to case and device bulk.
Drain and Source may be interchanged.
MM455, MM555
EQUIVALENT
~p
l
TOGGLE o--t--+---+-"'--+~I---f-""'"
INPUT
0--+-.--+----+---'
I
I
I
I
I
_J
rMM451------- i
r------..,I
I
I
, - - - -. . . 1
1
OUTPUT
INTELLIGENCE
DPDT Analog Switch
VIDEO
INPUT #1.
o--+--+-....
VIOEO
r-IH_O OUTPUT #1.
4-Channel Multiplexer*
TOGGLE
INPUT
'Expansion in the number of data input lines is
possible by using multiple level series switches
allowing the same decode gates to be used for
all lower rank decoding.
DPST Hi h-Frequency Switch
141
absolute maximum ratings
MM450, MM451, MM452, MM455
Gate Voltage (VGG)
Bulk Voltage (V BULK)
Analong Input (V IN )
Power Dissipation
Operating Temperature
Storage Temperature
MM550, MM551, MM552, MM555
+10V to -30V
+10V
+10V to -20V
+10V to -30V
+10V
+10V to -20V
200 mW
_55°C to +125°C
-65°C to +150°C
200 mW
_25° C to 70° C
_65°C to +150°C
electrical characteristics
STATIC CHARACTERISTICS (Note 1)
PARAMETER
CONDITION
Analog Input Voltage
Threshold Voltage (V GS(T))
V OG = 0, 10 = 1 J1A
ON Resistance
V IN = -10V
MIN
TYP
1.0
2.2
ON Resistance
OFF Resistance
Gate Leakage Current (I GSS)
I nput (Drain) Leakage Current
'MM450, MM451, MM452, MM455
Input (Drain) Leakage Current
MM550, MM551, MM552, MM555
MAX
UNITS
±10
3.0
V
V
150
600
n
75
200
n
n
V GS = -25V, Vss
= 0, T A = 25°C
pA
TA = 25°C
TA = 85°C
TA = 125°C
TA
TA
= 25°C
= 70°C
Output (Source) Leakage Current
MM450, MM451, MM452, MM455
.025
.002
.025
100
1.0
1.0
nA
J1A
J1A
0.1
.030
100
1.0
nA
J1A
100
nA
.040
Output (Source) Leakage Current
MM450
MM451
MM452, MM455
MM450, MM451, MM452, MM455
TA = 85°C
TA = 85°C
TA = 85°C
T A = 125°C
1.0
1.0
1.0
1.0
Output (Source) Leakage Current
MM550
MM551
MM552, MM555
TA=70°C
T A = 70°C
TA=70°C
1.0
1.0
1.0
DYNAMIC CHARACTERISTICS
Large Signal Transconductance
VOS = -10V, 10 = 10 rnA
. f = 1 kHz
4000
J1rnhos
CAPACITANCE CHARACTERISTICS (Note 2)
PARAMETER
DEVICE TYPE
Analog Input (Drain) Capacitance (Cos)
ALL
Output (Source) Capacitance (Css )
MM450,
MM451,
MM452,
MM455,
Gate Input Capacitance (C Gs )
MM450,
MM451,
MM452,
MM455,
Gate to Output Capacitance (C Gs )
MIN
TYP
UNITS
8
10
pF
MM550
MM551
MM552
MM555
11
20
7.5
7.5
14
24
11
11
pF
pF
pF
pF
MM550
MM551
MM552
MM555
10
5.5
5.5
5.5
13
9
pF
pF
pF
pF
3.0
5
pF
ALL
Note 1: The resistance specifications apply for -55°C ::;;TA::;;+ 85°C, VGG = -20V, V SULK =
+10V, and a test current of 1 mAo Leakage current is measured with all pins held at ground except
the pin being measured which is biased at -25V.
Note 2: All capacitance measurements are made at 0 volts bias at 1 MHz.
142
MAX
8
9
typical dynamic input characteristics
s:
s:
(TA=25°CUnlessOtherwiseNoted)
~
C1I
o
.........
CONDITION 1:
ANALOG INPUT VOL TAGE
AT +10 VOL TS
s:
s:C1I
Dynamic Ron
Ron vs VGG
(J'I
.o
10,000
VBB = +10V
r '"'
+lOvLlJ
v"
v
55°C
TA
- ~TA=25°C
7'
°
1000
!
I
~rTA =85 C
;;2::
VBB +10~=
VIN - +10V-
"~ ~~
c
co
a:
100
T
r-- f---
10
-8
+8
-22
-16
VGG (VI
CONDITION 2:
ANALOG INPUT VOL TAGE
ATOVOLTS
Dynamic Ron
10,000
VBB +10V
10
+10V
E ~VBB
- ~VIN-OV
f::::::
8
I
I
1000
!
'b
~~
c
co
1";;-
a:
100
~""-""'--'--""'---r,--,--",,---,--r....
I£":TA ~85°C=
~TA =25°C~
4FTA = _55°C
/
~~~
10
o
-4
-8
-12
-0.6
-20
-16
-0.2
CONDITION 3:
ANALOG INPUT VOLTAGE
AT -10 VOLTS
VON
V
10,000
c
co
"
1000
:7;-+ - TA = -55°C-
--
::""" ~
r"'-_ ~
100
-16
-17
-19
-18
-!I.6'
-20
-02
VGG (VI
t:,
10,000
-50
10
~
-40
~
~
a:
a:
~
a: -35
a:
:::I
-30
.
.'~
c:
a::
100
10
;;:
..,~~=~~
==
-==
:::I
I
I' I
.E
I
~
8.0
I
J
6.0
L
;;:
a:
CI
4.0
I
I
-15
.E
-10
'(
2.0
-5
~
0
o
-4
-8
-12
-16
-20
1
L
- VBS = ov
Z
-25
a: -20
CI
Vaa = OV
vaa = 2.5V
II
Co)
Co)
z
I
-v,os ~ -2~V
-45
VBB - 5V
VBB=7.5V
Vaa = 10V
+0.2
VIN {VI
Drain Current vs
Gate To Source Voltage
Typical Drain Characteristics
Ron vsVGG
j
+1.0
=
===
TA = 85°C
t?=-TA - 25°C -
j
T
..!.
+0.6
VBB - +10V
=V IN - 10V
a:
-or
+1.0
Dynamic Ron
r
-1OvLlJou,
,If
+0.6
10
100,000
VBB +10V
1000
+02
t:,V in (VI
VGG (VI
-20
-40
-60
-80
-100
Vos - DRAIN TO SOURCE VOLTAGE - VOL TS
-1.0
-2.0
/
~3.0
-4.0
-5.0
. VGS - GATE TO SOURCE VOL TAGE -:VOL TS
143
typical input capacitances
MM450, MM550
C 1N vs V 1N
50
40
30
-20
...
Vaa - +10v
"-V GG = _110V
10
_.... ....
(.)
I
~
VGG = OV
......
50
40
30
~
VGG = -20V -;-,.
Yo
i::
MM451, MM551
C 1N vs V 1N
-~
r
/
u
..,-
VGG=+10V
50
40
30
20
~
...L
10
5
4
3
I
1- VGG = -10V I
I
I I I I
Yo
z
\
Vaa = +10V
VGG = -20V ~ ~
20
...
MM452, MM552 , MM455, MM555
C 1N vs V 1N
...
.-
--
VGG = +IJ~-
VGG
10V
...... ~
10
U
VGG - OV
+10V
VGG = -2~~
Yo
z
Vaa
5
4
3
•
j
L
io .... ",'"
-
-6
-2
+2
VIN (V)
144
+6
+10
-10
-6
-2
+2
VIN (V)
+6
+10
-10
-6
-2
/1
I
VGG = +10V
,
1
-10
.;r
VGG = OV_
+2
VIN (V)
",
+6
,
+10
Analog Switches
MM454/MM554 four-channel commutator
general description
The MM454/MM554 is a four-channel analog commutator capable of switch ing four analog input
channels sequentially onto an output line. The
device is constructed on a single silicon chip using
MaS P Channel enhancement transistors; it contains all the digital circuitry necessary to sequentially turn ON the four analog switch transistors
permitting multiplexing of the analog input data.
The device features:
• High Analog Voltage Handling
• High Commutating Rate
±10V
Low Leakage Current (T A = 25°C)
(T A = 85°C)
• All Channel Blanking input provided
• Reset capability provided
• Low ON Resistance
•
200 pA
50 nA
200[2
In addition, the MM454/MM554 can easily be
applied where submultiplexing is required since a
4: 1 clock countdown signal is provided which can
drive the clock input of subsequent MM454/MM554
units.
500 kHz
schematic and connection diagrams
ANALOG
INPUTS
4
ANALOG
OUTPUT
CLOCK
INPUT
CP
OA
OUTPUT
4:1
COUNTDOWN
A
OB
RESET----+-----------'
14
NO CONNECTION
13
VGG
12
CLOCK INPUT
11
RESET
10
ALL CHANNEL BLANKING
Voo
OUTPUT 4:1 COUNTDOWN
NO 1 ANALOG INPUT
NO.2 ANALOG INPUT
NO.3 ANALOG INPUT
NO.4 ANALOG INPUT
NO CONNECTION
Vss
ANALOG OUTPUT
NOTE': Pin 1 connected to case and to device bulk. Nominal Operatmg Voltages: VGG = -24V;
Voo 0 OV; Vss 0 +12V, RESET BIAS 0 +12V 10V for RESEll, ALL CHANNEL
BLANKING BIAS +12V IOV for BLANKING)
0
145
absolute maximum ratings
(Note 1)
+10V to -30V
+10V
+10V to -20V
200mW
-55°C to +125°C
-25°C to +70°C
-65°C to +150°C
Gate Voltage (V GG)
Bulk Voltage (V ss )
Analog Input (V IN)
Power Dissipation
Operating Temperature MM454
MM554
Storage Temperature
static characteristics
(Note 2)
PARAMETER
CONDITION
MIN
TYP
Analog Input Voltage
ON Resistance
ON Resistance
OFF Resistance
Analog Input Leakage Current
V IN = -10V
170
90
10
10
V IN = Vss
MM454
MM454
-T A =25°C
T A = 85°c
MM554
Analog Output Leakage Current MM454
MM454
T A =25°C
TA=70°C
T A = 25°c
T A =85°C
MM554
T A = 25°c
MM554
TA=70°C
MM554
Vss Supply Current Drain
V GG Supply Current Drain
.050
.006
.0001
.030
0.100
30
.0001
.030
MAX
±10
V
600
200
n
n
n
100
1.0
100
1.0
100
1.0
100
3.8
Vss = +12V
VGG = -24V
UNITS
2.4
nA
J..lA
nA
J..lA
nA
J..lA
1.0
nA
J..lA
5.5
3.5
mA
mA
capacitance characteristics
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Analog Input Capacitance Channel OFF
liN = 0
4
6
pF
Analog Input Capacitance Channel ON
liN = 0
20
24
pF
Analog Output Capacitance
liN = 0
20
24
pF
Clock Input
V cL =+12V
2.0
pF
Reset Input
V RESET = +12V
2.0
pF
Blanking Input
VSLANK = +12V
2.0
pF
clock characteristics
(Note 3)
PARAMETER
Clock Input (HIGH)(4)
Clock Input (LOW)
CONDITION
MIN
TYP
Vss -2
-5
Clock Input Rise Time (POSGOING)
MAX
UNIT
Vss
v
+5
V
20
J..lsec
0
No requirement
Clock Input Fall Time (NEG GOING)
Countdown Output (POS) V OH
Vss -2
Countdown Output (NEG) VOL
Maximum Commutation Rate
Vss
Vss
+10.0
MHz
2.0
+12
Note 1: Maximum ratings are limiting values above which the device may be damaged. All voltages
referenced to VOO = o.
Note 2: These specifications apply over the indicated operating temperature range for VGG = -24V,
VOO = OV, VSS = +12V, VRESET = +12V, VSLANK = +12V. ON resistance measured at 1 mA,
OFF resistance and leakage measured with all analog inputs and output common. Capacitance measured
at 1 MHz.
Note 3: Operating conditions in Note 2 apply. VSS to VOO (OV) voltage is applied to counting and
gating circuits. VGG is required only for analog switch biasing. Arllogic inputs are high resistance and
are essentially capacitive.
Note 4: Logic input voltage must not be more positive than VSS.
146
V
0
0.5
V
+14
V
typical performance characteristics
RON vs Analog Voltage
...
260
I
(.)
c:C
I-
220
en
~
a:
?zi
fJ!
:z::
180
i"
ien
::'"c:C
."
"-..... f'
~ a:a 140
100
z
I
I
30
28
26
24
22
20
18
16
14
12
10
8
I
Voo = OV
VBUL K = +12V
VGG = -24V Vss = +12V -
z
~
II
, "-
TA = +85"C
_ iA
=1+25~C_ f - - f--
r--.... ~ i'~
""" r--... ,...."" ~ 1"-00.. -~ 1"-00..
TA = -55°C-- r--. 1"'--0 ~ r--. r-
60
-10 -8 -6 -4 -2
o
-10 -8 -& -4
0 +2 +4 +6 +8 +10
~
'"
12
/
2!'"
...'::l"
11
/
III
>
10
+9
/
V
v
~
CI
CI
>
12
13
V," MAXIMUM POSITIVE GOING
ANALOG EXCURSION (V)
14
U~
/.~
I
-20
-16
-12
-8
11
0 +2 +4 +6 +8 +10
I
-24 f-- ~TA
o
10
I
I
Minus VIN (max) vs VGG
-30
-28
= +85°~
I
•
fffJ
~W
r7l
;=--TA =+25°C-
;--T~ = ~55JC-
~~
::;;:::::;
-4
+9
-2
I
I
Vin ANALOG INPUT VOL TAGE (V)
Plus VIN (max) vs VBULK
13
~
~
1,.....00 10"'"
CHANNEL "OFF":;;;' ~
Vin ANALOG INPUT VOL TAGE (V)
14
-
.~ po-
6
4
2
r--
c:C
r r
r r
CHANNEL "ON"
o
....
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
Von MAXIMUM NEGATIVE
ANALOG EXCURSION (Ron =1 KS1) (V)
timing diagram
CLOCK 0
IN 1
CH1
CH2
CH3
CH4
..___. . . nL.
. _____nL.___
O~~
nL._____n
n
rL....o~~ _ _ _ _ _n
n
n
rL
o~:------__r-1L.________r-1..-----.......r--1L.--------rO~: ---1I~~
__...n
_ _....
~
OUTPUT
"0" - - ,
COUNTDOWN "1"
I
NOTE:
"0" LEVEL =+12V
''1'' LEVEL =
OV (GND)
147
f/)
Q)
'-
Analog Switches
Q)
(/)
o
....
CQ
o
::t
«
AH0120/ AH0130/ AH0140 / AH0150/ AH0160
series analog switches
o
Lon
....
o
general description
The AH0100 series represents a complete family
of junction FET analog switches. The inherent
flexibility of the family allows the designer to
tailor the device selection to the particular application. Switch configurations available include dual
OPST, dual SPST, OPDT, and SPOT. r ds(ON) ranges
from 10 ohms through 100 ohms. The series is
available in both 14 lead flat pack and 14 lead
cavity DIP. Important design features include:
J:
«
o
~
~
o
::t
«..
o
M
....
•
TTL/DTL and RTL compatible logic inputs
o
•
Up to 20V p-p analog input signal
J:
«
•
rds(ON) less than lOr!
AH0145, AH0146)
o
•
Analog signals in excess of 1 MHz
•
"OFF" power less than 1 mW
....
J:
«
N
o
(AH0140, AH0141,
•
Gate to drain bleed resistors eliminated
•
Fast switching, tON is typically .4l1s, tOFF is
1.0 /J.s
•
Operation from standard op amp supply voltages, ±15V, available (AH0150/ AH0160 series)
•
Pin compatible with the popular DG 100 series.
The AH0100 series is designed to fulfill a wide
variety of analog switching applications including
commutators, multiplexers, 0/ A converters, sample
and hold circuits, and modulators/demodulators.
The AHOl 00 series is guaranteed over the temperature range -55°C to +125°C;· whereas, the
AHOl OOC series is guaranteed over the temperature
range _25° C to +85° C.
schematic diagrams
DUAL DPST and DUAL SPST
Note: Dotted'line portion's are not applicable to the duaiSPST.
DPDT (diff.) and SPDT (diff.)
Note: Dotted line
portio~s are notapplicab(e to the SPOT (differential).
logic and connection diagrams
DUAL DPST
DPDT (Diff)
SPDT (Diff)
HIGH LEVEL (±10V) .
HIGH LEVEL (±10V)
HIGH LEVEL (±10V)
HIGH LEVEL (±10V)
AH0140(10n)
AH0129 (30n)
AH0126 (80n)
AH0141 (1on)
AH0133 (30n)
AH0134 (80n)
AH0145 (10n)
AH0139 (30n)
AH0142 (80n)
MEDIUM LEVEL (±7.5V)
MEDIUM LEVEL (±7.5)
MEDIUM LEVEL (±7.5V)
AH0163 (15n)
AH0164 (50n)
AH0161 (15n)
AH0162 (50n)
MEDIUM LEVEL (±7.5V)
AH0153 (15n)
AH0154 (50n)
148
DUAL SPST
AH0151 (15n)
AH0152 (50n)
AH0146 (10n)
AH0144 (30n)
. AH0143 (80n)
»
::t:
o.....
N
o
absolute maximum ratings
Total Supply Voltage (V+ - V-)
Analog Signal Voltage (V+ - V A or V A - V-)
Positive Supply Voltage to Reference (V+ - V
Negative Supply Voltage to Reference (V R
-
High
Medium
Level
Level
36V
34V
30V
25V
R)
25V
25V
V-)
22V
22V
Positive Supply Voltage to Input (V+ - VIN)
25V
25V
Input Voltage to Reference (V IN - V R)
Differential I nput Voltage (V IN - V IN2 )
±6V
±6V
±6V
±6V
30mA
Input Current, Any Terminal
Power Dissipation
o.....
w
o
»
:J:
o.....
~
o
30mA
See Curve
AH0100 Series
Operating Temperature Range
AH0100C Series
-55°C to +125°C
-25°C to +85°C
Lead Temperature (So'ldering, 10 sec)
300°C
electrical characteristics
DUAL
DPST
o
....
(J'1
o
for "HIGH LEVEL" Switches (Note 1)
DEVICE TYPE
SYMBOL
»
:::J:
-65°C to +150°C
Storage Temperature Range
PARAMETER
»
::t:
DUAL
SPST
DPDT
(DIFF)
SPOT
(DIFF)
»
LIMITS
CONDITIONS
:J:
UNITS
v+
=12.0V. V- = -la.ov. VR =O.OV
typ
MAX
2.0
60
120
o.....
CJ)
;
Logic "1"
Input Cur-rent
IIN(ON)
All Circuits
Note 2
T A =25°C
Over Temp. Rang!'
Logic "0"
Input Current
IIN(OFF)
All Circuits
Note 2
TA = 25°C
Over Temp. Range
2.2
.01
.1
2.0
IJ.A
IJ.A
3.0
3.3
mA
mA
Positive Supply Current
Switch ON
I+(ON)
All Circuits
One Driver ON Note 2
TA = 25°C
Over Temp. Range
Negative Supply
Current Switch ON
I-(ON)
All Circuits
One Driver ON Note 2
TA = 25°C
Over Temp. Range
-1.0
-1.8
-2.0
mA
mA
Reference In pu t
(Enable) ON Current
IR(ON)
All Circuits
One Driver ON Note 2
TA = 25°C
Over Temp. Range
-1.0
-1.4
-1.6
mA
mA
Positive Supply
Current Switch OFF
I+(OFF)
All Circuits
VIN1 = VIN2 = 0.8V
TA = 25°C
Over Temp. Range
1.0
10
25
JJ.A
IJ.A
Negative Supply
Current Switch OFF
I-(OFF)
All Circuits
V IN1 = VIN2 = O.SV
TA = 25°C
Over Temp. Range
-1.0
-10
-25
IJ.A
IJ.A
Reference Input
(Enable) OFF Current
IR(OFF)
All Circuits
VIN1 = VIN2 = O.SV
TA= 25°C
Over Temp. Range
-1.0
";10
-25
IJ.A
IJ.A
Switch ON Resistance
rds(ON)
AH0126
AH0134
AH0142
AH0143
Vo = 10V
ID = 1 mA
T A =25°C
Over Temp. Range
45
SO
150
Switch ON Resistance
rds(ON)
AH0129
AH0133
AH0139
AH0144
VD = 10V
ID = 1 mA
TA = 25°C
Over Temp. Range
25
30
60
n
n
n
n
Switch ON Resistance
rds(ON)
AH0140
AH0141
AH0145
AH0146
VD = 10V
IF = 1 mA
TA = 25°C
Over Temp. Range
S
10
20
n
n
Driver Leakage Current
(lD + IS)ON
_ VD = Vs = -10V
TA = 25°C
Over Temp. Range
1
100
nA
nA
Switch Leakage
Current
IS(OFF) OR
ID(OFF)
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
VDS = ±20V
TA = 25°C
Over Temp. Range
0.8
1
100
nA
nA
Switch Leakage
Current
IS(OFF) OR
ID(OFF)
AH0140
AH014l
AH0145
AH0146
VDS = ±20V
TA = 25°C
Over Temp. Range
4
Switch'Turn'ON Time
tON
AH0126
AH0129
AH0134
AH0133
AH0143
AH0142
AH0139 ' AH0144
See Test Circuit
VA = ±10V TA = 25°C
Switch Turn·ON Time
tON
AH0140
AH0141
AH0145
AH0146
Switch Turn·OFF Time
tOFF
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
Switch Turn·OFF Time
tOFF
All Circuits
AH0140
AH0141
AH0145
.01
o
en
JJ.A
IJ.A
10
1.0
nA
IJ.A
0,5
0,8
IJ.S
See Test Circuit
VA = ±10V TA = 25°C
0,8
1.0
IJ.S
AH0143
AH0144
See Test Circuit
VA = ±10V TA = 25°C
0.9
1.6
IJ.s
AH0146
See Test Circuit
VA = ±10V TA = 25°C
1.1
2.5
lJ.'s
CD
~.
CD
fA
Note 1: Unless otherwise specified these limits apply for -55°C to +125°C for the AH0100 series
and -25°C to +85°C for the AHOl OOC series. All typical values are for T A = 25°C.
Note 2:, For the DPST and Dual DPST. the ON condition is for VIN = 2.5V; the OFF condition
is for VIN = O.8V. For the differential switches and SWl and 2 ON. VIN2 = 2.5V, VINl = 3.0V.
For SW3 and 4 ON, VIN2 = 2.5V, VINl = 2.0V.
149
\
~" .---~------~~------------~--------------------------~--------------------~~----~--~
Q)
electrical characteristics
"""
Q)
(J)
forUMEDIUM LEVEL" Switches (Note 1)
,
o
CD
'
CONDITIONS
DEVICE TYPE
~
PARAMETER
o
SYMBOL
J:
«
DUAL
DPST
DUAL
SPST
DUAL
DPDT
SPOT
(DIFF)
LIMITS
UNITS
V+
= +15.0V, V- = -15V, VR = OV
TYP
MAX
Logic "1"
Input Current
IIN(ON)
All Circuits
Note 2
Logic "0"
'Input Current
IIN(OFF)
All CircuitS
Note 2
Positive Supply
Current Switch ON
All Circuits
One Driver ON Note 2
T A = 25°C
Over Temp. Range
2.2
3.0
3.3
«
Negative Supply
Current Switch ON
All Circuits
One Driver ON Note 2
T A =25°C
Over Temp. Range
-1.0
-1.8
-2.0
mA
mA
o
Reference Input·
(Enable) ON Current
All Circuits
One Driver ON Note 2
T A =25°C
Over Temp. Range
-1.0
-1.4
-1.6
mA
mA
1.0
o
Lt)
Over Temp. Range
120!J.A
_.-+_._0_1+---:0::-._1-+---"-!J.--:-A_
T A = 25°C
Over Temp. Range
2!J.A
~
o
::r:
~
~
IA(ON)
o
Positive Supply
Current Switch OFF
All Circuits
V IN1 = V IN2 = 0.8V
T A =25°C
Over Temp. Range
«
Negative Supply
Current Switch OFF
All Circuits
V IN1 = V IN2 = 0.8V
TA = 25°C
-1.0
-10
""O'-'-ve-r-:;T;-e-m-p--.""R-an-g-e-+---+-""""'-2-g--
o
Reference Input
(Enable) OFF Current
I A(OFF)
All Circuits
V IN1 = V IN2 = 0.8V
TA = 25°C
Over Temp. Range
-1.0
~
Switch ON Resistance
10
rdslON)
.«::r:
Switch ON Resistance
::r:
M
o
o
N
~
o
::r:
o
....
::I:
typical performance characteristics
N
100
2.4
500
I""~
Z
Q
j:::
~
400
en
i5
JOO
a:
~
f
C( 2.0
t--
.§
"
...
::
:t
""
200
100
0.8
==
§
--
~ 0.4
10
t-
50
75
100
-75 -50 -25
125
0
25
50
~
AHI01J~
~~~
100 125
_~H01~5, A~014~_
Vo = 10V
10 = 1 rnA
V+ = +12V
V~ = -18V
Q
75
l>
J:
AH0140, AH0141,=
o....
~
o
~
0
~H
1~1~
l>
TEMPERATURE rC)
TEMPERATURE (OC)
TEMPERATURE rC)
o....
w
...o
.--
"7'
..". ~H0129, AH01J3,
~
a:
z
1.0
25
::J:
_I""'"
~
V
Z
oct
el)
l>
AH0143, AH0142,
AH0126, AH01J4
V
...w
.-- ~I""'"
IRtON)
~
=
~
~ 1.6
a:
~ 1.2 t-- f-1-tON)
~
o
rds(ON) vs Temperature
AH0120 thru AH0140 Series
ON Supply Current
vs Temperature
Power Dissipation
vs Temperature
::I:
Leakage Current vs Temperature
rds(ON) vs Temperature
AHOl50/ AH0160 Series
AH0120, AH0130, & AH0140
1000
100
v+
.-
i-- ~H0154, AH0152- -
§
...
AHOl64, AH0162_ -
w
eI)
10
z
Q
r
v+
= +15V
Y- = -15Y
rvo = 7.5V
Is = 1 rnA
1.0
-75 -50 -25
~
o
.:§ 1.0
0
25
50
I
25
75 100 125
45
TEMPERATURE rC)
I
65
I
I
TEMPERATURE
::
t-
:l:
t-
125
25
45
nl
65
I
I
85
105
TEMPERATURE
::::!.
CD
I
en
125
n)
~
>
a:
Z
>"
I
0.1
""""lo
~ 1.0
1.0
1.0
"'"
ffl
a:
~
a:
I
en
CD·
AH0152,...... ~ ~ AH0154,
AH0164, AH0162=
Q
-
I
~
AL( swrtcHE~ ON ~ ~~
~~ ~
@ ~ ~.
I-- ALL SWITCHE~
:l:
Q
o....
en
o
",...
~
2.0
Q
::
::I:
Differential Switch Input
Threshold vs Temperature
~
2.0
~
I
105
85
Single Ended Switch Input
Threshold vs Temperature
:l:
~
o
...... ~CEPT AH0140, AH0141,:
AH0145, AH0146
0.1
.......r
-I
~~
Q
AH0153, AH0151,=
AH0163, AH0161
a:
l>
1,.-1
..5 100
;:::: AH0153, AH0151,
=.AH016J, AH0161
....... - '
a: 10
=
i?j
= +15V
V- = -15V
Vo OR Vs = ±7.5V
AH0140, AH0141,
f= AH0145, AH0146
j
o
v+
C(
..A
F
~
IIJ:....-
Z
oct
I-
(J'I
AH0150 & AH0160
1000
= 12.0V
V- = -18.0V
Vo OR Vs = +10V
o....
Leakage Current vs TemperatlJre
Q
IV IN1 - VIN2 1;;:: O.JV
VR=OV
~I---r~-~
y+ - V- =JOV
Z
>"
o
-75 -50 -25
0
25
50
75 100 125
-75 -50 -25
TEMPERATURE (OC)
25
50
75 100 125
TEMPERATURE rc)
switching time test circuits
Single Ended Input
Differential Input
3V
YIN1
~2.5V
~!I
V'
SW1&2
OUTPUT
VIN2 = 2.5V
L,,---+-~;.......J
OUTPUT
VA
iLI
ov
I
I
I
I
I
I
I
OUTPUT
SW3&4
OUTPUT
SW1 &2
SW3&4
OUTPUT
151
en
Q)
...
applications information
, Q)
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oU)
1. INPUT LOGIC COMPATIBILITY
~
o
A. Voltage Considerations
«
In general, the AH0100 series is compatible with
most DTL, TTL, and RTL logic families. The ONinput threshold is determined by the V SE of the
input transistor plus the V f of the diode in the
emitter leg, plus I x R 1, plus V R. At room
temperature and V R = OV, the nominal ON threshold is: O. 7V +0. 7V+0.2V,= 1.6V.Over temperature
and manufacturing tolerances, the threshold may
be as high as 2.5V and as low as 0.8V. The rules
for proper operation are:
:I:
o
Ln
~
o
:I:
«
o
~
~
o
V 1N - V R 2 2.5V All switches ON
«..
V 1N - V R ::; 0.8V All switches OFF
:I:
o
M
~
o
:I:
«..
terminal will open all switches. The V R (ENABLE)
signal must be capable of rising to within 0.8V of
V1N(ON) in 'the OFF state and of sinking IR(oN)
milliamps in the ON state (at V1N(ON) - V R
2.5V). The V R terminal can be driven from most
TTL and DTL gates.
>
3.
DIFFERENTIAL INPUT CONSIDERATIONS
The differential switch driver is essentially a differential amplifier. The input requirements for proper
operation are:
IV 1N1 - V IN2 12: 0.3V
2.5 ~ (V 1N1 or V 1N2 ) - V R ~ 5V
The differential driver may be furnished by a DC
level as shown below. The level may be derived
from a voltage divider to V+ or' the 5V Vee of
the DTL logic. I n order to assure proper operation,
the divider should be "stiff" with respect to IIN2'
Bypassing R 1 with a 0.1 pF disc capacitor will
prevent degradation of tON and t OFF '
o
N
~
o
v.
~
:I:
«
B.
Input Current Considerations
IIN(ON), the current drawn by the driver with
V 1N = 2.5V is typically 20 pA at 25°C and is guaranteed less than 120 pA over temperature. DTL,
such as the DM930 series can supply 180 pA at
logic" 1" voltages in excess of 2.5V. TTL output
levels are comparable at 400 pA. The DTL and
TTL can drive the AH0100 series directly. However, at low temperature, DC noise margin in the
logic "1" state is eroded with DTL. A pull-up resistor of 10 kD. is recommended when using DtL
over military temperature range.
OhF
Alternatively, the differential driver may be driven
from a TTL flip-flop or inverter.
If more than one driver is to be driven by a DM930
series (6K) gate, an external pull-up resistor should
be added. The value is given by:
Rp
11
=N_
1 for N
>2
where:
Rp = value of the pull-up resistor in kD.
N
C.
= number of drivers.
Input Slew Rate
The slew rate of the logic input must be in excess
of 0.3V Ips in order to assure proper operation of
the analog switch. DTL, TTL, and RTL output
rise times are far in excess of the minimum slew
rate requirements. Discrete logic designs, however,
should include consideration of input rise time.
2.
ENABLE CONTROL
The appl ication of a positive signal at the V R
152
Connection of a 1 mA current source between V R
and V- will allow operation over a ±1 OV common
mode range. Differential input voltage must be less
than the 6V breakdown, and input threshold of
2.5V and 300mV differential overdrive still prevail.
'IOVI
CMRANGE
»
::J:
VA ~ V+ - V SAT - V SE
4. ANALOG VOLTAGE CONSIDERATIONS
-
V SE
-
o
1.0V or
~
N
The rules for operating the AH0100 series at
supply voltages other than those specified essentially breakdown into OFF and ON considerations.
The OFF considerations are dictated by the maximum negative swing of the analog signal and the
pinch off of the JFET switch. In the OFF state,
the gate of the FET is at V- + V SE + V SAT or
about 1.0V above the V- potential. The maximum
V p of the FET switches is 7V. The most negative
analog voltage, VA, swing which can be accomodated for any given supply voltage is:
IVA I~ Iv-I- V p
-
o
V A ~ v+ - 2.0V or V+? V A + 2.0V
For the standard high level switches, VA
2.0V = +10V.
»
= 12 -
::J:
o
w
~
5. SWITCH ING TRANSI ENTS
..o
»
::J:
Due to charge stored in the gate-to-source and
gate-to-drain capacitances of the FET switch, transients may appear in the output during switching.
This is particularly true during the OFF to ON
transition. The magnitude and duration of the
transient may be minimized by making source
and load impedance levels as small as practical.
V SAT or
Iv AI~IV-I-8.0 or IV-I~IV AI+8.0V
For the standard high level switches, VA <1- 181
+8 = -10V. The value for V+ is dictated-by the
maximum positive swing of the analog input voltage. Essentially the collector to base junction of
the turn-on PNP must remain reversed biased for
all positive value of analog input voltage. The base
of the PNP is at V+ - V SAT - V SE or V+ - 1.0V.
The PNP's collector base junction should have at
least 1.0V reverse bias. Hence, the most positive
analog voltage swing which may be accommodated
for a given value of V+ is:
o
~
~
o
»
~
:=r-rv-
:I:
o
~
......- ' ,
~:
res
-v-.J
':'
INPUT
C1I
o
»
::J:
o
Furthermore, transients may be minimized by
operating the switches in the differential mode;
i.e., the charge delivered to the load during the
ON to OFF transition is, to a large extent, cancelled by the OF F to ON transition.
~
0)
o
fJ)
CD
~.
CD
typical applications
(J)
Programmable One Amp Power Supply
81
r-;: -
1.1
:
I
!
:
l
.....-----..:~-+---+---.:......
I
I
I
I
I
15v
r
:
+15V~
-
----;HO~ 7
I
4
Eour
ZERO
ADJUST
VOUT =(±Polarity) x (BCD Code) x V. EO
lOUT - 2A peak. 1A continuous
VOUT Range - ±12V
Full Scale Acquisition Time - 8 ~s
TTL/OTlBCDINPUTS
Four to Ten Bit D to A Converter (4 Bits Shown)
ANALOG
OUTPUT
2.
20K
2.
2.
20K
20K
r----+-......---+--......--I--~...__oV"EF
,
I
1$1,$2,$3,"
I AREAHD1.6
I
.J
2"
Setting Time: 1 IJ$
Accuracy: 0.2%
"Note: All resisto11 are 0,1%
(
153
typical applications (con't)
Four Channel Differential Transducer Commutator
a~';;- Q"'(~'
TRANSD~~E~ {
61
:
O
TRANSDUCER
NO.2 {
o
°
TRANSDUCER{O
NO.3
0
t.n
~
o
:t:
0-1' I,
,.1 C)"'(.
I,
I:
I
2 ~_ _;---:-,-3-+""_-,\NIr""'''''i
aj.H;;;--a-(.I:
I,
I
:
I
I
~
6
I
I
I"
I
NO.4L~1
·,,1
+15V~
o
\,
r ~:1
I:
I
TRANSDUCER \
«
EOUT
5
I
I
I
I
~
I
~
o
3
~
Gain: ZZ
Commutation Rate: 500 kHz
I
I
'0
:t:
«
o
M
4
~
o
X
4 Cross Point Analog Switch
ALL CHANNel
:t:
BLANKING
«
I-I
I
r-1-+-:.....-~'
o ,I
o
I
~N'
I
I
N
~
o
I
21
:t:
~N2
«
DM74164
4T016
r--,....-+.....:..--:-~4
DECODER
I
I
~N3
I
I
.1
I
I
L __
,
2
Switching Time - 800 ns
"ON" Ruist.nca - 45n
"OFF" Resistance -10,on
"B"CHANNElS
Delta Measurement System for Automatic Linear Circuit Tester
EOUT
Analog Input Range - ±1.5V
EOUT =lOx (Analog Input Z - Analog Input 1)
error Rate - 0.01% F.S./sec
Note: $1 must be optn for 50 jJS min to tlke fril1lUdinll with IL = 50 rnA. Second rllding is tlken with S2 closed.
With S1 end other set·up forcing functlom under computer control, system will measure line Ind load r,..lltian on
yoltlgeFellllatoB,volt.gelllin,otfsetcurrent,CMRRlndPSRRonoplmpslswelllsothercircuitsrequirinllmelsurementofthechlngeoflpllrlmeterwiththechlngeof.forcinllfunction.
Precision Long Time Constant Integrator with Reset
Four Channel Commutator
C (UWLEAKAGE!
a '~F
INHIBIT nTLI
Integration Internal = 105ec
*Integration Error = 100j..N
Reset Time: 30"s
154
o---I-+--H>---!-+--'
------SElICTV 1N (V)
DYNAMIC RON
<
E
-loV~-loV
~
RON vs V minus
-,-
0
-4
ON
~
-
.
2
-2
-6
-8
...- ~ ~
::;~
-
."
.-:: --
z
+0.2
-0.2
+0.6
~
0
II:
1000
TA = +85°C
TA +25°C
~
I
100
+1.0
Vp1us
+loV
50
20
~
CHANNEL "ON" - CHANNEL "ON"Vmonus =/-2oV - Vminu~ = oV
l~
~iI"
~
z
cS
5
1/
1&
~
rot
el:
2
Pc~NE~ "ON"- I-- CHA~~El "OFF"
1
-10 -8 -6 -4 -2
t"-
RON vs Temperature
...... ~
"" f'.
25
eI:
0
w
Z
z
:z:
t.)
500
Vp1us = +loV
Vminus-NO EFFECT _
-25
1
w
"
eI:
fI
Vminus = -loV
c:I
~
.....
c:I
~
eI:
z
~
w
:.:
~
j
10
I"
50
-50
t.)
z
400 I--
Vp1us = +loV
Vminus = -22V
300
eI:
""'~
-
I-
en
""
~
200
2
F
100
-75
ANALOG V1N (V)
+8 +10
+10
0
ANALOG V1N (V)
-10
0
-55
+- ~ .....
V1N - -lOV
II:
V1N = OV
.J-I:::: t::V1N -loV
Vminus = -2OV
0 +2 +4 +6
t--
Vmonus(V)
Leakage vs VIN (Channel "OFF"
75
...
-19 -20 -21 -22 -23 -24 -25 -26
t:,V'N (V)
CIN vs VIN
-
~~
TA - -55°C'"
Vmmus=-22V - - - -0.6
Vp1us +loV
V1N -loV
I
---------
"""
!==
I--
10,000
~ ~ ":':I-
Vmonus = -18V
i-Vmonus = -19V
I - - i- Vm,nus = -2oV
I-- t- Vminus = -21V
-10
-1.0
-22 -24 -26
100,000
.1
1 ,
f- Vp1us = +loV
8
V1N =-10V
6
VOUT = -loV
4
VOUT
~2o
Vminus (V)
10
V1N
1 TA =-55°C- I--
?
~.,
-10
CONDITION 3 AT -loV
+25°C
TA
7
~,,-,
0
II:
~~W ;-Vminus=-12V
V
L
(D
RON vs V minus
10
-15
25
65
105
145
AMBIENT TEMPERATURE (OC)
165
(.)
0')
~
o
o
selecting power supply voltage
Z
The graph shows the boundary conditions which
must be used for proper operation of the unit .
0')
The range of operation for power supply V minus
is shown on the X axis. It must be between -26V
and -8V. The allowable range for power supply
V plus is governed by supply Vminus' With a
value chosen for V minus' V plus may be selected
as any value along a vertical line passing through
the V minus value and terminated by the boundaries of the operating region. A voltage difference
between power supplies of at least 5V should be
maintained for adequate signal swing.
::I:
.........
~
o
o
::I:
Z
..
(.)
~
~
o
o
::I:
Z
.........
~
~
o
o
level shifter characteristics
::I:
Z
~
w
~
~.
0
:>
w
>
~
0
CI)
0
+10 ....----.----.-...,.----.------,
Vee = 5.0V
Vminus =-22V
L
+5
Vp1us =10.0V
0
-5
-10
:E
.....
cz:
z
~
I-
-15
-20
~
-25
0
O~
1~
1~
2~
2~
INPUT VOL TAGE (V)
166
3~
3~
~
V+=::
- 15
OPERATING
V-.
-25
I
I
I
I
I
I
-15
7
EGION
-
10
-
5
I
0
-5 - -5
- -10
I
- -15
-
-20
- -25
Logic Elements
MM480/MM580 series MOS logic elements
general description
National's line of monolithic .MOS gates and flipflops are built utilizing P channel enhancement
mode transistors. Zener diodes are used on all inputs to protect against static discharge. These
devices are members of a family of compatible
logic functions that feature low threshold voltage
transistors, enabling operation at a V DD supply of
-10 volts and low power consumption in systems
that operate at frequencies up to 2 MHz.
The JK flip-flops are particularly suited for counter and register applications in MOS systems. Both
true and complement outputs are buffered to prevent false triggering from the outputs and also provide the capability to "wire AND" at the outputs.
schematic and connection diagrams
_VOO...:.'0~_..._--...._---_--____,
10
-Voo-----------...,
13K
13K
OUT 1 - -........- - 4 - - - .
.---~-........-
OUT 1 - - " " ' "
OUT2
GNO ..:.5-++---4......._+.......-4--+--++-+-+-_1-......
Bl
Al
A2
Cl
82
C2
Al
Note: All resistor values shown Ife nominal
81
A2
82
Note: All resistor VlluH Ire nomin.1
-Voo
GNO
GNO
TOP VIEW
Note: Pin 5 connected to ClW
TOP VIEW
NOTE: Pin 5 connected to
Clse
MM480/MM580 dual 3-input NOR gate
MM481/MM581 dual exclusive OR gate
10
_V oo ..::: . . - - - - _ . _ - - . - - - - - . - - - _ _ _ _ . - - - - - ,
13K
Cl
57K
81
20K
13K
Al
C2
57K
82
20K
A2
-Voo
GND
TOPVIEW .
NOTE:Pin5connec1edtoCltl
NOTE: Pin 5 connected to cue.
MM482/MM582 dual digital multiplex switch
MM483/MM583 JK flip flop
167
absolute maximum ratings
Supply Voltage (VDD)
Data Inputs
Operating Temperature (MM480, MM481, MM482, MM483)
(MM580, MM581, MM582, MM583)
Storage Temperature
electrical characteristics
PARAMETER
+0.5V to -25V
+0.5V to -25V
-55°C to +125°C
- 25°C to +70°C
-65°C to +150°C
(Note 1)
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage
Logic "0"
Logic "1"
VIN = -7.0V for Logic "1"
V IN = -1.5V for Logic "0"
Input Leakage
VIN = -11.0V
Fan Out
-0.2
-10.0
-1.0
V
V
<1.0 nA
-3.0
J.l.A
7.5
7.5
12.7
12
12
20
mW
mW
mW
13.0
20.5
mW
10
Power Dissipation, Each Half
MM480/MM580
MM481/MM581
MM482/MM582
MM483/MM583
Propagation Delay (Gate Circuits)
MM480/MM580
TpD1
MM480/MM580
TpD2
MM481/MM581
TpD1
MM481/MM581
TpD2
MM482/MM582
TpD1
MM482/MM582
TpD2
Toggle Rate
MM483/MM583
Transient Response MM483/MM583
Rise Time, T R
Fall Time, TF
-
Propagation Delay
TpD1
TpD2
TpD3
TpD4
-8.0
VO UT = Logic "0"
VA = VB = -10V
VA = VB = OV
Vc = -10V
Toggle Mode
Clock Frequency = 100 kHz
25
250
425
130
230
350
CLOAD = 10 pF
TA = 25°C
CLOAD
= 10 pF
CLOAD = 10 pF
TA = 25°C
1.0
2.0
ns
ns
ns
ns
ns
ns
MHz
120
200
ns
300
450
ns
600
400
280
350
850
550
400
500
ns
ns
ns
ns
MM483/MM583
CLOAD = 10 pF
TA = 25°C
Note 1: These specifications apply over the specified operating temperature range for Voo = -10V
±10% unless otherwise specified. Typical values are for Voo = -10.0V and T A = 25°C.
168
50
400
600
200
350
600
typical performance characteristics
MM480/MM580
-10
en
....
.,~~
-8 r-- _1+25~C
t:I
-55°C
~
~
r-- r--~125'°C
-'
Q
~
w
~
,
-6
l
I.
> -4
~
~
/
~ 250
....
....a.
~ ........+125°C
-2
o
..
I
-1
Q
-2
-3
-4
INPUT VOLTAGE (VOLTS)
,
175
-5
~
.
!
~
o 24
20
18
po
,,"'"
;I'
~
60
~~
V
V
w -.7
t:I
!
c:(
....
-'
+125°Cj
-.6
> -.5
~
325
c.'I
CD
-.4
Q
-'
275
-.3
-.2
-50 -25 0 25 50 75 100125
TEMPERATURE (OC)
~
~
~5°C
~"~ V
V. V
Q
300
:.,..0 ~
\
VDD (VOLTS)
~
375 ~
350 ~
'f"
~
~ ~ ~0~2~4~6~8-ro
-' -.8
~
~V
~
o
1
2
3
NUMBER OF WIRE AND CONNECTIONS
MM481/MM581
Voltage Transfer Characteristics
Average Propagation Delay vs
Power Supply Voltage (VDD)
(See Figure 2) .
Output ON Resistance vs Temperature
I
-10.0V
V
e
:! 1.1
w
c.'I
z
~ 1.0
~ .9
CI
....
~
~
,
.8
,
I
,
"i
V
.7
\.
;- 240
\
c:(
~ 220
J
CI
\.
~ 200
~~
~
~ 180
~ 160
a.
V
~
"-
~ 140
a.
~ 120
~
~
CI
-5
/
I
/
CiS
w
-1
-2
-3
-4
INPUT VOLTAGE (VOLTS)
~~
70
Q
~
~
80
-.9
en
....
~ Tp~/ e--
'/
~ 22
f
:f
~
"I\..
CI
-1.0
A
26
t:I
Logic "0" Voltage vs Wire AND
Connections (See Figure 4)
I rTPD17
/
30
\
~ 90
-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)
J
28
CI
~ 100
'D~
Propagation Delay vs Temperature
"---
\
~ 110
RON
~
~
-55°C ~ ~
+25°C
~
o
J
~
130
~ 120
1/
w
:;;
,
,
140
!
I
z
a: 300
o
c.'I
Q
Q
350
g
c:(
....
a.
....
,"
375
-
\'-,
....-'
Average Propagation Delay vs Power
Supply Voltage (VDD) (See Figure 1)
Output Device RON vs Temperature
Voltage Transfer Characteristic
~
c:(
ffi
......... ~
100
...
>
c:(
-50 -25 0 +25 50 75 100 125
TEMPERATURE (OC)
-6 -8 -10 -12 -14 -16 -18 -20
VDD (VOLTS)
logic "0" vs
Wire AND Connectors (See Figure 5)
Propagation Oelay vs Temperature
540
II
160
I
TpD2
~V
140
j
120
100
1/11
~
..
~
.J
~
~
~
~V
~
~'"
TpDl
520
1.4
480
w
460
!
440
j
c:(
....
-'
400
~
t:I
CI
>
c:::I
c.'I
CD
0 +25 50 75 100 125
TEMPERATURE rC)
L
1/
1.2
+125°C
1.0
.8
.6
CI
-'
380
·50 ·25
1.6
CI
-'
420
I
en
....
500
~
I:
~
/ /fI'"
V+25°C
~
~.,..
.4
o
NUMBER OF WIRE AND CONNECTIONS
169
MM482/MM582
-
Voltage Transfer Characteristics
. ...
-10
.
f-INPUT IS A. C = O.OV
OR B. C = -10.0V
in
I-
-8
-I
c
=
Output Device RON vs Temperature
600
-6
0(
w 500
Co)
:;
-I
C
>
w
c
-4
I-
I-
;::)
,
450
I-
;::)
C
-2
+125°C,
+~5°C
o
.
r-....
~
a..
I-
;::)
C
400
~
-55°C
-1
-2
-3
-4
INPUT VOLTAGE (VOLTS)
W
c
z 300
c
j: 275
V
\
~
0(
250
=
c 225
0(
a..
~
a::
a..
w
200
~
=
175
a::
0(
1'10..
r--~
w
150
>
0(
-50 -25 0 +25 50 75 100125
TEMPERATURE (OC)
-6 -8 -10 -12 -14-16-18
Voo (VOLTS)
Logic "0" Output Voltage vs
Wire AND Connection (See Figure 6)
Propagation Delay vs Temperature
in
I-
450
-I
I~
tpo~
!
--;. 350
.J ~
j
... ~
~
c
~
w
280
~~
400
300
&
-I
l/
350
-5
>
0(
~".
;::)
a..
j
1/
,
!
j"
z
0
a::
I-
l/
j
~ 550
-55°C
~
w
Average Propagation Delay vs
Power Supply Voltage VDD
(See Figure 3)
~~ V
= 1.01.2
V
0(
~,.,
l/!Po 1
260
!
240
j
I-I
C
>
I-
;::)
a..
I-
;::)
.8
b
:
220
I-'
Co)
c:;
~
~
~ ~~ ~
.6
~ ~ II"" +25 C
0
c
~~
V
+125°C ~
.4
~~
.2
c
-I
-50 -25 0 25 50 75 100125
TEMPERATURE (OC)
2
3
NUMBER OF WIRE AND CONNECTIONS
MM483/MM583
Voltage Transfer Characteristics
Set and Clear Inputs
Toggle Frequency vs
Output Device Ron vs Temperature
.,
in
I-
-I
c
~ 600
-8
~
w
~
= -6
I-I
C
>
I-
;::)
a..
I!
-4
550
~
I-
;::)
t~---.I
-2 I--+-+-+--+--+-+~ 25}C
C
1
ICI
-.1.0
a::
c
~+-4-~~-+_1 I -+~i!.-~
CI
~
-1
-2
-3
-4
INPUT VOL TAGE (VOL TS)
0
300
250
+25°C-rt.=
0
350
;::)
c
z
~
~"
l"
2.8
~
2.6
~ 2.4
~'f'
400
~f'
3.2
CI
I/'
J
2.2
I
~ 2.0
~..,.
~
:Iii
i1.B
~~
J
~ 1.6
IT
:Iii
-55 -25 0 25 50 75 100 125
TEMPERATURE (OC)
-5
IT
I(
-I
g
~,.,
;::)
I-
Power Supply Voltage (VDD)
~ 3.0
~II'
~
500
Co)
:; 450
0(
.
~
-6 -8 -10 -12 -14 -16-18
POWER SUPPL Y Voo (VOLTS)
Logic "0" Voltage vs
Wire AND Connection (See Figure 7)
Propagation Delay vs Temperature
~
~
300
i..,...o- ~
280
~
!
260
~ 240
~.,
200
~
~
V
;: -1.4
I...-
T pd3
II'
~
- 220
~
"""""
""I'
~
c: -1.6
>
"....
T pd4
,V
=
.0(
400 -;;- ~ -1.2
..:. c
-1.0 I - - f--+125°V
~ ;:
;::)
350 ~
-.8
;::)
c
300
?-.6
V"
VV
a
-.4
c
-I
-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)
170
V
V
1
V
V
"
~
Propagation Delay vs Temperature
Tp~ ~
~~OC
~
~
~
450
350
,~
~
~
..... ~
I""""",
I~
l/
~ r/
If
I~
!
650 -:
j
Tpd1
~
-.2
2
NUMBER OF WIRE AND CONNECTIONS
700
-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)
600
550
propagation delay
test circuits (gates)
transient response test circuits
MM483/MM583
MM480IMM580
r
TZ
Tl1 ~~
Ir-\I
r-IOV ---Y
""---'
ov
E'N
E'N
~
IN
V
,....._ _
.r
...,.,)D~--1--vOUT
-:;r ..
,F
-IOV
OV
DORII
-IOV
MM482/MM582
,N
(c=OV)
:~.--1
....-
-IOV
II OR D
VOUT
J ~
.:::2J
r- T
pD 4
I-IOV
MM480/MM580,MM481/MM581,MM482/MM582
TF
-IV
-IV
OV----~
~_'0Pf
_ ----V
Y'N (C =-IOV) B
-IV
-IV
OV
CP
-IOV
SET OR CLEAR
V
A
OV
D OR II
-IOV
MM481/MM581
DORII
-IOV
OV
II~~O~----~
wire" AN 0" test circuits
MM480/MM580
OV
-10.0 VOLTS
OV--
YOUT
MM481/MM581
-IOV _ _ _---'
-10.0 VOLTS
-10.0 VOL TS
MM480/MM580
-VOOo--O-1...-------+1--1..------.-1----,1
FIGURE 5. Test Circuit for Wire "AND"ing
FIGURE 1. Ring Oscillator for Measuring
Average Propagation Delay
MM482/MM582
-IOV
MM481/MM581
fosc. = ~
10Pf~
T,o AVE.
3
FIGURE 6. Test Circuit For Wire "AND"ing
FIGURE 2. Ring Oscillator for Measuring
Average Propagation Delay
MM483/MM583
MM482/MM582
-IOV
-IOV
-IO.OV
-IOV
I
1
-IOV
.-VDD
-IOV
lose.. =1\ TPD AVE.
FIGURE 3. Ring Oscillator For Measuring
Average Propagation Delay
FIGURE 7. Test Circuit For Wire "AND"ing
171
R OM Character Generators
MM4220NP/MM5220NP, MM4230NN/MM5230NN,
MM4230NO/MM5230NO,7 x 9 horizontal scan
display character generator
s:
s:
general description
The MM4220NP/MM5220NP isa 1024-bit read-only
memory and the MM4230NN/MM5230NN and
MM4230NO/MM5230NO are 2048-bit read-only
memories programmed to generate a font of 64
7x9 dot-type raster or horizontal-scan characters.
The typical application shows the ASCII-address
system. The display refresh memory, built with
MOS dynamic shift registers, and the TTL control
techniques are similar to those described in Application Note AN-40. Designs for vertical-scan fonts,
printer character generators, and designs for fonts
larger than 7x9 are also outlined in AN-40.
~
N
eN
o
Z
Z
For full electrical, environmental and mechanical
details, refer to the M M 4 2 2 0 / M M 5220 and
MM4230/MM5230 data sheets.
"s:
s:
(J'I
N
eN
o
Z
Z
typical application
s:
s:
7x9 Character Generator System
~
N
eN
o
Z
o
"s:
s:
(J'I
N
eN
o
Z
o
LINE REFRESH
MEMORY
.
+1·. 1
~.
MM5230 NN
I.
I
-L.
MM5230 NO
MM5220 NP.
~
1
•.I
•
•
173
o
z
o
character font
M
N
Ln
:E
:E
..........
o
z
o
.. ·.·.. ..... ··..... .....
....... ....... ...
.....
.. J:::~: ···.... .....···· .... J:::.: ··I.... . ···............ ··i·····i . ·L ·....··· ···.......... .L. . i:···:!. ·r····i. ·i·•••••.....!
···................ ··.......
· .
· .
00
000000
M
N
01
100000
02
03
010000
110000
04
001000
........ ·.... ·........ ·.... .......
··......
. · . · . ..
·· .. ··........... ··............ ·............... ···:
~
:E
:E
16
11
000010
100010
32
000001
100001
o
:E
:E
..........
.....
···.....···
z
z
48
000011
o
33
..··
J.
49
100011
:E
:E
c..
Z
o
N
N
Ln
:E
:E
..........
c..
z
o
N
N
~
:E
:E
174
08
000100
09
100100
10
010100
11
110100
18
19
20
21
22
23
24
25
26
110010
001010
101010
011010
111010
000110
100110
010110
3)
101001
38
39
111001
40
43
000101
41
100101
42
011001
010101
110101
34
35
36
010001
110001
001001
............. ............ .·..·. ·......
....... ·......... ··.......... ...................
....·.......... ............... .......
· .· ......... · ··.............
..... . ··....... ......·
·
50
51
52
53
54
55
56
010011
110011
001011
101011
011011
111011
000111
N
Note. Input addresses are
0)
111000
010010
M
~
06
011000
12
13
001100
101100
14
011100
15
111100
.· ··... .. ... ·.··.... .::::::
.·
·· ··.... ·............. ·..... . .· .......
.........
.
.....· ·.. · . ·· . ·· ........
· ··... ·· J ·· ·
··.. ......
·· .. .......
.
. ·........... ··..... .... ... .· .·.....
..
·
...... . ....... . ..
.
.....
......
...
.
· . ......· . · .... ·.......
·
:..
· ·... : ·
···
·
z
z
M
N
Ln
05
101000
In SIX
bit ASCII code and are shown
In
the sequence Ao. A,
A5
5)
100111
58
01~
111
2)
110110
28
29
30
31
001110
101110
011110
111110
44
001101
45
46
4)
101101
011101
111101
·
.. .··.···
59
110111
60
001111
61
101111
··.·.
···
··........
62
63
011111
111111
ROM Character Generators
MM4240ABU/MM5240ABU hollerith character generator
general description
The MM4240ABU/MM5240ABU is a 64 x
read-only memory programmed to display
character subset of the Hollerith 12-line
normally used in punching 80 column cards.
pre·ssion from 12 I ines to the six needed to
up a 64-character set may be accompl ished as
shown in the typical appl ication.
8 x 5
a 64code,
Commake
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
typical application
OW
12
SERIAL
DATA
OUT
~
I
11
'F[>-
vec
Lbc>-
D-~>-
HOLLERITH
CODE
INPUT
>-
:l
::J
.;:J
~>-
- A5
B,
"'-- A"
B,
-A3
LINE
AND
PAGE
STORE
(SEE AN40)
B3
-
L--
MM4240ABU!
MM5240ABU
DM8590
-A,
B4
r--
B5
A,
r---
J
R ~ 6.8K
r--
f--
Ao
L,
....L,
Lo
0---
I I I
-12V
Vee
CJCK
LINE
COUNTER
12
A5,A4
11
As
A4
A3 , Ao
A3
o
9
8
Note Hole plesentglVesc!osure to GNO
*For additional application mformation on incorporating this device
"A Systems Approach to Character Generators"
In
a display system, see AN40
175
::J
co
«
0
code table/
character font
~
Ln
~
~
HOLLERITH
INPUT CODE
(NON-COMPRESSED)
GRAPHIC
OCTAL
SEQUENCE DISPLAY
"CO
00
01
02
03
::)
«
0
MM4240ABU/MM5240ABU
(space~
1
2
3
04
05
06
07
~
N
~
~
~
0
0
8
7
9
8
8
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
176
2
3
4
5
6
7
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
2
3
4
8
11
11
11
11
11
11
11
11
11
11
11
11
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
8
8
8
11
8
8
8
11
11
11
8
8
8
8
8
2
3
4
5
6
7
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
00
000000
•••• •••••• •••••• •••••
•
••• ••••• • •••• ••••••
•
•••••
•••
•••
03
01
02
04•
000001
000010
••••••• ••••••• ••••••
••• •••• ••
••••••• •• ••
10
001 000
T
U
V
W
X
Y
Z
11
001 001
12
001 010
20
010000
21
010001
22
010010
30
011 000
N
0
P
31
011 001
32
011 010
13
001 011
23
010011
41
100001
42
100010
05
000101
14
001 100
15
001 101
06
000 110
07
000111
33
011 011
43
100011
16
001 110
17
001 111
••• ••• ••• ••• ••• ••• ••• •••
••••••••• ••••• ••••••••• •••••
• • •• •
24
010100
25
010101
• ••
••••
•• •••
••••
••
••• ••••• •••••
•
• • ••
•• •• •• ••
•• •••• ••
•••••
•••••• ••• ••• •••••••
40
100000
000100
•
••••• ••••• •••••• ••••• •••• •••
••
•• •• •••• •• •••• •• ••
••• ••••
••••
•• •••
• •• ••
•••••• ••• ••••
•
• •••••
•• •• •• ••• •••
•••• •• ••••• ••
•• •• •••••• •••••
••• ••
• •••••
•••
••• ••••••
•
M
000011
•••••• •••• •••••
•
••••
•• •••••• •••
••••• ••••• ••
34
011 100
35
011 101
26
010 110
••
••
••
••
36
011 110
27
010111
••••••
•
••••
•
37
011 111
••• ••• ••• •• ••••••• ••••• •
• •
•• • •• •• •••• •• :• ••••
••• 44 ••• ••• ••• •••••••• •••
100100
45
100101
46
100110
47
100111
Q
••••••• •••••••• •• •••••••••
•• • •• •••••
• • •
••••• •• ••• •••••••• •••••••••
50
101 000
A
D
F
51
101 001
52
101 010
53
101 011
•• ••• ••••• ..:•
•••
• •
•• ••• ••••••• ••
..
54
101 100
55
101 101
56
101 110
57
101 111
••••
•• ••••• ••••
• •• •••••• •••••
• •• •••••••
••••
•••••
•
•
•
•
• •••
••••
• • •••••••• ••••
•• •• •••••• •• •• •••••••
•••••
• ••••••
••••
• ••
•••
•• :•
••
••• •••••
•• •••••
••
•• •••
• •• ••
•
•••••
•
..
60
110000
61
110001
62
110010
63
110011
....
64
110100
65
110101
66
110110
...
67
110111
G
_ (period)
••• •••
•••••
• •
•• ••
70
111 000
••••
••
••
•• ••
••• •••
72
73
•••
•
••
••
71
111001
111 010
111011
74
111 100
75
111 101
76
111 110
77
111111
ROM Character Generators
MM4240ABZ/MM5240ABZ EBCDIC-8 character generator
general description
The MM4240ABZ/MM5240ABZ is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC8, an Extended Binary Coded Decimal Interchange
Code with character assignments and locations conforming to the American Standard x 3.26-1970
(see MM52300X data sheet for full EBCDIC-8
table).
plished by simply ignoring the two most significant
EBCDIC bits, bit 0 and bit 1.
The octal character address digits are then formed
as shown below.
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
Compression of the eight bits of EBCDIC-8 to the
six needed for a 64-character subset is accom-
character font
• •••• ••• •••• ••••••
••• ••• •••••••• ••• • ••• ••• •••
•
•••••• •• •• •• • •• •• :•
•
•03•• ••••
• 01 • ••••
02
04
05
00
....
000000
• •
•••••••••
•• ••
000001
000010
000011
000100
000101
•••••••
•••••
• 06
000110
•••
••• •
• ••:
....
07
000111
••••
•• •• •• •••
••• ••• •••••
•
••
••
• •••• ••
•• •• •• ••
• • •••
• ••••
•• • ••••• ••••
•
••• •••••••• ••• :••
•••••
: : : :• ••• ••• :•....•
•
•
•• ••
•••••••• •••••• ••• ••• ••••••• ••• ••
••
•• •• ••••••• ••
10
001000
•••
•
•
••
11
001 001
12
001 010
13
001 011
14
001 100
15
001 101
16
001 110
17
001 111
..
20
010000
21
010001
22
010010
23
010011
24
010100
25
010101
011 000
011001
•••••
• •••
•• ••• •
•
••
•
•• ••••
42
41
100001
••••• •• •••••
•••
•• ••
• •••••
50
101000
011010
51
101 001
100010
•••
••
•
52
101 010
011011
•••••
••
•••
•
43
100011
26
010110
011 100
44
100100
011101
45
100101
101 100
36
011 110
60
61
110001
62
110010
63
110011
64
110100
567
'-./
1
2
LSB
LSD
"-/
OCTAL DIGITS
46
100110
37
011111
47
100111
1015~01
101 110
65
110101
110110
101111
••••• •• • ••••
•••• ••• ••••• ••••• ••••• •••••
•
•
••• ••• ••• •••• • •••• •••••
• •
• •••••• •••
•
•••• •••
• •••••• ••••• •• •••• • ••••• ••
110000
MSD
~
234
'-/
••
••
••
•• •••••
•• •••
•
••
••
••• •••••
• ••
•
•
••
•
•53 54 • • • • • 56 •57
101011
MSB
27
010111
•••
:: • •
••
•• ••
•• •• •• •• ••
•• ••
••
• •• •• •••
•
••
• •••• •• ••
••••••• ••
•• •••
•• •
••• •••• •••
• • • ••
•••
••• ••• •••••••• :• •••••
• ••••••
•
•••
•• ••• •• •• •• ••••
• • ••• •••
••30 • • 31 • •32•• 33• • ••
•35
34
40
100000
EBCDIC BITS
I)
66
OUTPUTS
Bl B2 B3 B4 B5
000
010.. .
001.
•
ROW
011 • • •
ADDRESS 100.
• •
101.
110.
111.
•
•
•
67
110111
••• ••• •• • • •••
• • •• ••• ••••• ••• •••
•••••••
••••••• •••••••• ••
• ••• ••
•• •• •• ••
•• .....
•••••
•• •• •••••
••
••
...
70
71
111 000
111001
72
111010
73
74
75
111011
111100
111 101
76
111 110
77
111111
177
ROM Character Generators
MM4240ACA/MM5240ACA EBCDIC character generator
general description
plished by simply ignoring the two most significant
EBCDIC bits, bit zero and bit one.
. The MM4240ACA/MM5240ACA is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC,
an Extended Binary Coded Decimal Interchange
code typically used in I BM systems.
The octal character address digits are then formed
as shown below.
Compression of the eight bits of EBCDIC to the
six needed for a 64-character subset is accom-
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
character font
••• ••••••• ••••• • •••••••• •••••
••
•:• :•• •••••
•
•• •• •• • ••• ••• :•••
• • •••• ••• ••••
• •
•• •• •••
•
•• •••
••••••• ••• •••••••
•
••• •••
•• •• •• •••• ••
••
• • •••
...
00
000000
10
001 000
01
000001
11
001 001
02
000010
12
001010
·
.
03
04
000011
000100
13
001 011
14
001 100
....
05
000101
15
001 101
•••••••
•••••
•
06
000110
•
•
•••••
•
•
16
001 110
•••
• •
••• ••
••••••
07
000111
••
••
•••
17
001 111
• ••••
•• •• •••••
• •• •••••
• •
•••••
•• ••• ••• :•• :••
•
:
:
:
:
:
••••••
•
•
••
•
•
•
•
••
•
•• •• •• •• • •• • ••••••• •
••••20•••• ••••
• 22 • •••••
• 24 •• 25 • 26 • 27
23
21
..
010000
010001
010010
010011
010100
••• ••••• • ••
••• ••• •••••
• •
•• ••• •• •• ••
••30 • • 31 • 32•
010101
010110
100000
011001
41
100001
•
••• ••• •••••
•• •••
•
•• •••••
50
101 000
51
101001
011 010
42
100010
..:•••..
•••••
52
101 010
011 011
100011
••
••
••
53
101 011
011 100
100100
••
•• ••
••
••• ••
••
54
101 100
•••• ••• •• ••• •••• • •••••
••• ••• ••• •••• • •••• •••••
• •
•••• •••
• •••••• ••••• ••
60
·110000
61
110001
62
110010
63
110011
64
110100
35
011 101
45
100101
36
011 110
46
100110
56
101 110
100111
57
101 111
••••• ••• ••••••
•••••
••
•••
•••••• ••••••
•
•
••• •
65
110101
66
110110
67
110111
•• •• •••• ••
••
•• •••••
••••••• ••••••• ••
••••••• • ••••• •• ••
•••
••••
•
•
••
•••••
•
••
•
••••
•• •• •• •• • • •
••• ••
• • •••
178
70
71
72
73
111 000
111 001
111 010
111011
74
111 100
75
111 101
76
111 110
234
567
'-./
'-./
1
2
LSB
LSD
~
OCTAL DIGITS
011111
•• •••••
•
••
••
•
•
•
••:5•• •
101 101
MSB
MSD
010111
• • • • •• ••••
•••
•••
••••••
•
••• • ••••••
•••
•• ••• ••
• • ••••••
••••
•
•
•33
37
34
•• •
•• ••••• •••••
••
• •• •• •• ••
•• ••• •••••
••••• ••• ••• ••• ••• ••• ••••
•• ••••
••••• ••• •••
• ••
••••• 43•• ••••
••
47
44
40
011 000
EBCDIC BITS
~
77
111111
OUTPUTS
8 1 8 2 8 3 84 85
000
001.
•
010..
•
ROW
011 • • •
AOORESS 100.
• •
101.
•
110.
•
111.
•
CJ)
"ooo
ROM Code Converters
tAl
S K0003 sine/cosine look-up table kit
general description
The SK0003 Sine/Cosine Look-Up Table Kit consists of four MaS ROMs: three MM421 0/MM521 O's
and one MM4220/MM5220-1024 bit static read
only memories. They are P-charinel enhancement
mode monolithic MaS integrated circuits utilizing
a low threshold technology.
THE SINE FUNCTION
The SK0003 implements the equation sine = sin
M cos L + cos M sin L. Cos L was assumed to be
1 in the equation. However, it is a variable between
1 and 0.99998 and is a fu nction of rou nd off error.
Worst case error is 1-5/8 bits in LSB at address
1415 (62.25°). The error increases from zero to
.002% every 8 bits, therefore, the MM4220/
MM5220 provides the error correction factor
cos(M - 2.81°)sin L in the equation sine = sinM +
cos (M - 2.81°) sin L. The circuitry to perform this
function is shown in Figure 1. Additional information is available in MOS Brief 10.
THE COSINE FUNCTION
To generate the cosine function cose = sin (e90°), the input must be complemented and a
logical "1" added. Figure 2A is a logic diagram
of the circuitry used to provide the cosine function, as well as providing both sine and cosine
functions in the same system. ll-bit resolution
and 12-bit accuracy ± 1-5/8-bits is ach ieved in th is
configuration.
A reduction in logic can be achieved as shown in
Figure 2B if a loss in resolution of l/2-bit in an
ll-bit input or 1/4-bit in a 10-bit input is acceptable.
ELECTRICAL CHARACTERISTICS
Refer to the appropriate data sheet for each
device shown in the figures. The devices noted are:
MM4210/MM5210, MM4220/MM5220, DM5483/
DM7483, DM7812/DM8812 and DM5486/DM7486.
logic diagram
GATES
~l--
1-!-_ _ _ _ _ _ _
~
A,
8,
2'
A3
~--------'"~i 83
2'
DM148l
7 A,
~---------4----:..t8,
A,
{
{
~l
,
~'6
2"
A.
B,
A5 MM&210
83
A4 MKOO8
B,
A,
DM7483
"
"
2'
"
2'
2'
CARRY INPUT
2'
2"
2"
2"
{II :~",,' ,
o---D-}
o---D~
{'
~~2A1
R "(TO EACH OUTPUT)
MKOlD8'6
3~:
J lSB
12Bx8MODE
FIGURE 1. SK0003 Logic Diagram (Kit Includes ROMs Only). This Circuit Provides 11-Bit Resolution and 12-Bit
Accuracy in a to Sin Converter.
e
e
179
M
o
logic diagram
o
o
~
en
+12V
2·'
2·'
2·'
2·'
2. 5
SKOOO]
ROMS
AND
OUTPUT
ADDERS
2.6
2. 8
2"
2- 10
2- 11
2,12
SINE/COSINE
ENABLE o-~~----+--1
SIGNAL
"O"=Sme
"J"=Cosine
R ~ ].OK
B,
A,
CARRY
" ,_ _.......1 IN
FI GU R E 2A. Sine/Cosine Conversion Provides 11·Bit Resolution, 12-Bit
± 1-5/8
Bit Accu racy.
+12V
2·'
2·'
2'
2·'
25
SKOOO]
ROMS
AND
OUTPUT
ADDERS
2. 6
2·'
2. 8
2·'
LSB
SINE/
COSINE
SIGNAL
J
2- 10
2"
"0" ~ Sin,
"1" ~ COSIO'
2,12
FIGURE 2B. Sine/Cosine Conversion with Cosine Approximated. (Cosine Conversion has 10-Bits Input Resolution
and 12·Bit ±1.-5/8-Bit Accuracy.)
180
s:
s:
ROM Code Converters
~
N
N
o
»
m
........
s:
s:U1
MM4220AE/MM5220AE ASCII-7 to hollerith code converter
N
N
o
»
m
general description
The MM4220AE/MM5220AE 1024-bit read-only
memory has been programmed to convert the
128 entries of the American Standard Code for
Information Interchange in seven bits (ASCII-7) to
Hollerith code (compressed to eight bits). The
conversion performed follows the recommendation
of American National Standard ANSI x 3.261970, Hollerith punched card code.
The typical appl ication shows a recommended
circuit for re-expansion of the Hollerith code to
twelve lines.
For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet.
typical application
PUNCH
,
~
DM88lO
orDM8812
A,
b,
b,
ASCII·7
INPuTS
2
A,
1
II,
b,
3
A,
2'
ROW
17~
8s
r
r-
i"-'<
87
21
9 8,
I-
f - --<
20
a a,
11
10
b,
As
bs
.. 19
7 B,
A7
6 B,
18
FAN
our AVAILABLE
1 TTllDAO
I
1
FAN OUT AVAILAaLE
l.OK
TYPiCAL
JUNES
j10TILLOADS
B,
>--
19:1
Vss
LOGic Levels
DTLITTl (except at MOS/ROM interface)
Loglc",",+5V, NOM,Logic".()"ground,NOM
MOS/ROM inpUl$and outputs
logic "''',more negative, logic "O",more positIVe
.CHIPENABlE
~6BK
1 6 ' 8,
~~"'l-~------l"""-1-4-1.--l--l--l.-12V
HOllERITHPUNCI-ICOMMA.N DS
(ACTIVE LEVEl, LOW'PUNCHI
·ChipEnable=logic"'''toobtamoutputs
181
code conversion tables
1
1
o
-I
1
o
0
8-4
11-7
1
~OL
RO~
NUL
0000
0001
0010
0011
0100
12-11-9-8-1
DCl
12-9-1
11-9-1
STX
DC2
12-9-2
11-9-2
ETX
DC3
12-9-3
11-9-3
ECT
DC4
9-7
9-8-4
ENG
0101
0110
SP
NO PCH
9-8-5
SYN
0-9-8-6
9-2
P
0
8-1
12-11-7
a
q
'
12-8-3
11-0-1
DEL
0-1
0-8-7
11-6
12-9-7
maybe "I"
maybe","
The top tine in each entry to the table represents an assigned character (Columns 0 to 71.
The bottom line in each entry is the corresponding card hole-pattern.
OUTPUT CODE
86 85
0-9-7
1100
1111
AOORESS
12-9-8-3
83
B2
81
ADD_
RESS
43
44
Be
OUTPUT CODE
93
82
81
ADD_
RESS
87
OUTPUT CODE
86 85 94 83 82
86
00
87
88
45
89
90
91
49
8
92
50
93
51
.,
94
52
10
11
95
53
54
97
55
98
13
14
56
99
16
17
100
18
59
60
61
19
62
20
63
21
64
101
102
103
104
105
106
107
66
109
67
110
68
111
69
112
113
2'
23
24
25
26
27
28
29
30
31
108
70
71
72
114
115
116
117
118
73
74
32
33
34
35
37
38
39
40
41
42
182
76
77
78
79
80
81
82
83
84
85
119
120
121
122
t
i
123
124
125
126
127
0
I 1
1
0
1
1
81
s:
s:
ROM Code Converters
~
N
N
o
»
"s:
.........
s:
c,n
N
N
MM4220AP/MM5220AP
o
»
BCDIC-to-ASCII code converter
"
general description
The MM4220AP/MM5220AP is used for the conversion of the Binary Coded Decimal Interchange
Code(BCDIC) to the American Standard Code for
Information Interchange (ASCII).
The output is a seven-bit ASCII code, with an
eighth bit generated for even parity.
device characteristics
The input is a seven-bit BCDIC code with the
exception of the parity (check) bit (pin 18) which
is returned to +12V dc. The alternate set of input
symbols is also shown in the Conversion Table for
reference.
For full electrical, environmental, and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
typical application
connection diagram
- 1 2 V - - - - - - - - - - - - - - - -. .---4.........,
--------------f--f--+--....- -
+ 5 V - -....
6.8K,
TYPICAL,
8 LINES
GATES DM7400
A,
B,
A2
Q
Q
...
::.
z
B2
A.
B
20
MM4220AP/
MM5220AP
7
N.C.
A,
N.C.
B,
A.
3.0K,
As
b.
B3
A.
8.
A,
Bs
VGG
8.
MODE
CONTROL
b,
8,
CHIP
ENABLE
PARITY
8,
A,
V ••
N.C.
b.
10~8.;..'- - - - - 4 - _ 1
TYPICAL,
7 LINES
B2
bs
9 B6
C (NOT USED)
----~
A2
b3
B.
B Bs
A. 19
+12V
b2
B3
21
As
Voo
b,
A3
4
A3
8,
_ _ ____4~~
llj-:------4~_I
DTLITTL LOGIC
tAB
'CHIP ENABLE - - _....
TOPVIEW
tMDDE CONTROL - - - -.......
logic Levels
DTLITTL (except .t MOS/ROM interface)
Logic"1",+5V. nom. Logic "O",ground,nom.
tMode Control = Logic "0"
As= Logic"l"
"'Chip Enable
= Logic"l" to obtain outputs
MOS/ROM Inputs & Output
Logic"l", more negative. logic"O", more positive
183
code conversion table
FUNCTION
INPUT
CODE
INPUT
OUTPUT
OUTPUT
C
ROM
ADDRESS
BCOIC
SYMBOL
ASCII
SYMBOL
0
1
2
3
4
5
Space
1
2
3
4
5
6
7
8
9
0
# or
Space
1
2
3
4
5
6
7
8
9
0
#
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32,
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
184
@or'
@
>
>
J
Blank
?
[
/
S
/
S
T
T
U
U
V
V
W
X
Y
W
X
Y
Z
Z
*
LF
%or(
v
%
HT
..-
"
J
J
K
K
L
M
L
M
N
N
0
0
P
P
Q
Q
\
-
R
R
I
I
$
$
J
)
;
'"
& or +
J
A
&
A
B
B
C
C
0
0
E
E
F
F
G
G
H
H
I
I
?
Il or)
[
<
*
~
I
<
CR
0
0
E
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BCOIC
8
4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
,
E
P
ASCII
b7
bS
bS
b4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
,
0
B8
B7
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A7 AS AS A4 A3 A2 A,
1
1
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
U
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
BS
BS
0
0
0
0
0
0
0
0
0
1
1
1
0
1
b3
0
0
0
·0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
b2
b,
0
0
1
0
1
0
1
0
1
0
1
0
1
0
U
1
1
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
u
1
0
0
U.
u
0
1
0
1
0
u
0
1
1
1
1
u
1
u
u
1
1
0
1
1
1
1
0
0
0
1
1
0
u
u
u
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
B4
B3
B2
B,
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
ROM Code Converters
,MM4220BL/MM5220BL baudot-to-ASCII code converter
general description
The MM4220B LIM M 5220B L is used for conversion
of the Communications Set Baudot code to the
American Standard Code for Information Interchange (ASC II ) .
feedback and latch circuits, can be deleted (as
shown with the X's).
The accompanying table is applicable for the code
conversion scheme as shown (or its alternate)
rather than for the device itself. The input and
output codes are defined at the TTL gates with the
logic trues high (Logic "1" = +5 volts, nominal;
Logic "0" = Ground, nominal).
The Baudot and ASCII codes have different formats. ASCII has a unique code combination for
each alphabetic, numerical, or control character.
The correct interpretation of a five bit Baudot is
dependent upon knowing its previous history;
whether upper or lower case was last selected. In
effect a sixth-bit, which can be called the Case Bit,
is required to uniquely identify the Baudot input.
The latch circuit shown in the typical application
can store this information and will generate the
Case Bit. If the bit is externally supplied, the
device characteristics
For full electrical, environmental, and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
typical application
Baudot to ASCII
+12Vdc
BAUDOT
(ALL l.OK)
CG
Lsl!- -
INPUTS
A, l 12
BIT 5
17
4
A,
8ITl
As 20
BIT1
b,
~rD'
B3
I
6
B,
A4 21
BIT2
~.-o
8,
5r--
A, 2
81T4
INPUT GATES
ARE DM8812
24
MM4220Bl
OR
MM5220BL
b,
7
OUTPUT GATES
DM7400SERIES
8
Bs
OPTIONAL SIXTH 81T
F.2!l.!!!'!.!~L..'!~'!.E~E
~'9
B,
9
~
B,
r:=:::I
10
18
14
l!
16
B.
II
15
(ALL6.8K)
-12Vdc
GATES.DM8000SERIES
~
Vss
PARITY
f
Loglt levels of Inpuland Output Codes
"J"=+5VoltsNornmal
"0"= Ground,Nomllll1
)
logtClevels
"'''More Negative Output
"0" More Positive Output
185
code conversion tables
connection diagram
COOE
FUNCTION
INPUT
ROM
ADDRESS
BAUDOT
SYMBOL
OUTPUT
ASCII
SYMBOL
INPUT
C
A
S
E
0
0
LF
L
5
0
0
0
0
0
0
0
0
0
0
0
0
EP b7
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
0
0
a
a
a
0
1
1
0
0
17
0
18
1
22
a
a
a
23
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
Upper
IS1/Can
u
Delete
Blank
NULL
0
1
1
0
0
1
0
1
1
0
1
a
1
1
0
a
0
a
0
0
0
a
0
0
1
a
1
a
a
a
a
1
a
1
1
a
a
1
a
1
1
1
1
0
1
1
0
1
a
1
a
1
a
0
1
a
1
1
a
0
a
1
0
1
1
0
a
1
1
1
0
1
a
a
a
a
a
a
a
a
a
0
0
1
a
a
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
1
BS/FE
1
1
1
0
a
a
a
1
1
1
a
1
a
0
1
0
51
BeH
Bell
6
6
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
1
1
1
1
Upper
7
1
1
1
1
1
1
a
a
a
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
.1
0
0
0
0
0
0
1
1
,0
1
0
0
1
1
1
0
0
0
0
0
~: = ~~~: :::~y
186
~a;~~;le Return
SIS
~
as'"
Stop/Start
Back Space
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
a
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
0
1
1
Can .,
0
0
1
1
151" Information Separator =1
\
1
1
1
1
1
a
a
0
0
1
1
1
1
0
0
0
0
0
0
a
1
1
1
1
0
0
1
1
1
1
a
0
1
55
0
0
1
0
54
1
0
1
1
1
a
1
&
1
1
0
a
LF
)
4
0
1
Space
LF
1
a
1
I
0
1
35
42
a
1
1
38
1
a
1
81- 4
211--A4
82- 5
20~A5
83- 6
19 ..... A6
84- 7
18~A7
86- 9
16 ..... ~g~iROL
87- 10
151--~~~8LE
88- 11
0
a
a
34
37
a
a
1
Lower
22 .....
85- 8
0
0
1
1
1
1
1
u
33
Al- 3
I--
0
0
a
a
a
1
0
0
0
0
25
23
0
1
1
1
1
0
a
0
1
1
1
a
1
1
1
24
52
0
0
0
1
14
41
1
1
0
0
0
0
1
0
12
32
bs bs b4 b:! b2 b,
1
0
11
13
241-- Voo
AZ- Z
BAUOOT
0
0
0
A3- 1
OUTPUT
1
1
13 .....
Vss- 12
TOP VIEW
ROM Code Converters
MM4220BM/MM5220BM sine look-up table
general description
"1" it carried into the LSB of the eight bit code,
where Ag was a binary "0" it was simply dropped.
The MM4220BM/MM5220BM is a 1024-monolithic MaS read only memory that has been
programmed to solve for the sine value x of a
known angle 0; i.e., to obtain the solution of the
equation x = sin o.
EXAMPLE
Find the sine of 45~
Values of 0 are defined in the look up table for
0° ::; 0
90° (quadrant I) which has corresponding solutions of 0 ::; x
1. For values of
90°
0
180° (quadrant II), enter the complement (180° - 0) to obtain the correct solution.
Solutions for quadrants III and IV differ in sign
with I and II. This is summarized in Table 1.
<
< <
The input address is (45/90) 128 = 64 or
1000000, as expressed in binary. The converter
generates the output .10110101 whose decimal
equivalent is 0.707131. Thus, sin 45° = 0.707.
<
Find the sine of 21 O?
This value is in quadrant III; therefore 0 1 = 210° 180° = 30°. The input address is then (30/90)
128 ~ 43 to the nearest whole integer. The binary
input to the ROM is then 0101011. The output
value is .10000001 or 0.503906. Thus, sin 210° =
-0.504, with the sign generated by the external
logic. The solution is within 1%; note that address
43 is actually equal to 30.23°.
This input is divided into 128 parts for 0 in each
quadrant. Thus, the appropriate input address is
1
(8 /90°) (128) to the nearest whole integer. The
actual input code to the ROM is the input address
expressed in binary, with A1 being the most
significant bit.
The output is the value of X expressed in binary.
The output lines B 1 , B2 , . . . . . B8 are binary place
values 1/2, 1/4, . . . . . . 1/256. The sign for negative values of X is externally generated.
device characteristics
For full electrical, environmental and mechanical
details refer to the MM4220IMM5220 1024-bit read
only memory data sheet.
The 8 bit output code has been rounded off from
a larger word code, i.e., where Ag was a binary
typical application
- 1 1 V - - - - - -_ _ _ _ _ _ _ _.....- - . . - - .
.....-
. 5 V - -.....------~=---+_-+---lf---
Vo;
A,
A,
VGG
14
---
6.8K.
TYPICAL.
8UNES
GATESDM7400
8,
1
b,
A,
8,
A,
8,
b,
b,
A,
10
MM4220BMI
MM5220BM
7
8,
b,
8,
A6 19
b,
A7 18
9
l.OK.
TYPICAL.
JUNES
10
86
b6
B,
b,
8,
Vss
. 1 2 V - - - -.....-4-......::.:.j 11
b,
DTlITTllDGIC
TA,
'CHIPENABlE--~
TMODE CONTROl---~
lOIKlanls
DTlITTl (except at MOStROM 1n.....Ka)
l . . . ' ... +5V.nom.lotic .. O.....ound.nom.
tMod.Control=lOfIC"O"
As'" lop:","
·Ch.p Enable
=
Lotfc "l"to ebtlln outputs
MOS/RDM Inputs & Output
lOlIC",".moren.tiwe.Lottc"O",morepoSltrYe
187
pattern selection form
4781
4852
84'
0
:~9
0
0
0
~ ~+~~
0
1
~---*---- --:~:~------1*- -1--k---~ -~ ~--- -~74
5203
908
-+-+
0
f-i
5:>44
5414
54.84
55,55
19
951
969
80
0
5836
20
2'5
258
8'
85
1617
282
1688
295
B'
BB
5906
5977
6047
22
1043
1,055
1068
61.87
1080
6258
1828
lB9B
2J
28
1969
3"
356
"
368
380
32
9'
95
+
393
A05
3'
--
6961
7031
~~
101
+
1.239
1.252
102
0
+-
315
7312
1,276
7383
74.53
1,289
7523
++
lOB
.5
.6
0
+-
109
77.34
7805
112
1331
1399
113
----.------
111
82.27
118
82.97
!~~;
---~:~
~- -i-~,O,-+__"_+-~+---'-__!-''_+___'_____!
4078
~--
1
0
1
()
--f-
121
122
~-.~-~-~~-~C·~1. ~'B-~-"J2o~·~21~~__"_+~~O.+2+~~~
---
--'----+ + +
'"
:~~_ _ _ ~
iS6
-
-1H~~
~~-+ -,,-O_l-'_+-'~---"--+--'-+-"-+__'_____!
12'
125
85.78
1.497
86.48
87.19
1509
8789
--+~
1
-+ -+~ -~- -i=
1,534
1.546
connection diagram
1
241-- Voo
-
2
231-- N.C.
A, -
3
22
A3
-
A2
Table 1. SINE
Quadrant
t--
N.C.
II
III
8,- 4
IV
82
-
5
83 -
6
20
85
-
a
86
-
9
> 0° < 90°
> 90° < 180°
> 180° < 270°
> 270°:-::; 360°
15
Vss -
V(t)
------_.....
13 -
TOPVIEW
188
180° - X
Direct Reading
X-180°
Direct Reading
360° - X
Direct Reading
N.C.
IV
I
I
:
!(+)~
;90
~180
1270·
I
I
I
I
HI H
I
I
I
0
-~~~8LE
14 - A .
12
Direct Reading
III
~1
8.-11
Direct
tll~:
MOOE
l(c)" CONTROL
8,-10
OUTPUT
Binary Value
I-- As
la-A,
8.- 7
Range
INPUT
Entry to ROM (81 )
I
I
I
360'
Sign
+
ROM Code Converters
MM4220BN/MM5220BN arctangent look-up table
general description
The MM4220BN/MM5220BN is a 1024-bit monolithic MaS read only memory that has been programmed to solve for the angle () whose tangent
value x is known; i.e., to obtain the solution to the
equation: () = arctan x.
greater than unity, either complement the output
binary code and add a 1, or complement the
resultant angular value (i.e., subtract from 90°).
The 8-bit output code has been rounded off. That
is, if another bit of even lower significance had
been computed for the given arctangent value was
a binary "1", it would have carried over into the
LSB of the eight bit code. If it was a binary "0", it
would have been dropped.
Values of x are defined in the Look Up table for
o < x < 1 with angles corresponding from
Oo~ () < 45°. For values x ~ 1, the reciprocal of x
(i.e., 1/x) must be entered and the output angle
must be complemented to obtain the actual value.
EXAMPLE
The input is divided into 128 equal parts for x.
Thus, the appropriate input address is (128) (x) to
the nearest whole integer for obtaining the appropriate ROM address. The input code is the ROM
address expressed in binary with A1 being the least
significant bit. For input values greater than unity,
the decimal reciprocal is to be taken prior to entry
of the binary address.
Find the angle whose tangent is 0.258.
The input address is 128 x 0.258, or 33 to the
nearest integer. Expressed in binary, this is
0100001, and is the actual input code to the
converter. The converter will generate the binary
value .01010010, whose decimal equivalent is
0.3203125.
The output has been normalized for 45°. To obtain the true angular reading, the output should be
multiplied by 45°, i.e.: () = (()output) x 45° where
() output is the decimal equivalent of the output.
The output code is the normalized value of the
angle () expressed in binary. The output lines B 1 ,
B 2 , •••• B8 are binary place values 1/2, 1/4, ....
1/256. To obtain angles between 45° and 89.6°
which occur when input values of x are equal to or
Thus, () = 0.320 x 45° = 14.4°
device cliaracteristics
For full electrical, environmental and mechanical
details refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
typical application
- 1 2 V - - - - - - - - - - - - - - - - - 4 t -. . ........,
-------------I--+--+--.....- -
+ 5 V - -....
6.8K,
A,
"
11
VGG
- - - TYPICAL,
8 LINES
GATES DM7400
B,
'2
A3
B2
"3
"4
A,
JO----+--~21
B3
B,
JO-_ _- +_ _A..:..js 20
MM4220BN/
MI'!'5220BN
'.
Bs
A. 19
A, 18
'7
9
3.0K,
TYPICAL,
1 LINES
+12V
10
-------4......
B6
8,
B,
Vss
~_----::~12
11
oTL/TTL LOGIC
tA,
'CHIP ENABLE - - - - '
tMOoE CONTROL - - - - - - '
logic levels
OTL/TTL (except.t MOS/ROM interf.ce)
logic "1",+5V, nom.logic"O",ground,nom.
tModeControl = logic "0"
As logiC"'"
0:
·Chip Enable = logic"1" to obtain outputs
MOS/ROM Inputs & Output
logic"l",morenegative.Logic"O",morepositive
189
---
pattern selection form
1281d
0
I
2
3
4
5
6
7
R
9
10
17
13
14
15
16
17
18
19
20
21
77
23
24
25
2'
2'
?
29
30
31
32
33
34
3<
"37
38
39
An
1
42
e O~7TP~: ~~D:4(8~~T:~T~ 1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
o
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
128(.)
43
44
45
4'
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.,
48
49
50
51
52
53
54
55
56
57
58
9
60
61
62
63
64
65
66
67
..
9
70
'I
72
73
"
"
76
77
78
79
80
81
82
83
84
85
B8 o~:p~:
1 0
0 0
0 1
0 0
01
1 0
1 1
1 0
1 1
0 1
0 0
0 1
0 0
0 1
0 0
0 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
1 1
1 0
0 1
0 0
0 1
0 0
0 1
0 0
1 0
1 1
1 0
1 1
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
C~5D~!80~JP;'2Tl B 1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUTPUT CODE (80UTPUT)
1281.1
86
87
88
89
90
91
92
93
94
95
o.
97
98
99
100
101
102
103
104
105
106
107
108
100
110
III
112
113
114
115
116
117
118
110
120
121
122
123
124
125
126
127
Be
NOTE'
connection diagram
A3 -
1
241-- Voo
A2 -
2
23 .....
A,_ 3
22~
8,- 4
21~A.
82 -
5
20_A.
83 -
6
19~A.
8.-7
18~A7
8.- 8
111-- VGG
8.- 9
16
I-- ~g~;ROL
15
~~=~8LE
8,-10
8.-11
141-- A.
131--
Vs s_12
TOPVIEW
190
8786
as
848382
Bl
10010100111
0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1
0 1 I 0 0 0 ; 1
1 1 1 0 0 0 1 1
1 0 0 1 0 0 1 1
1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 1
0 1 1 1 0 0 1 1
0 0 0 0 1 0 1 1
1 0 0 0 1 0 1 1
1 1 0 0 1 0 1 1
1 0 1 0 1 0 1 1
0 1 1 0 1 0 1 1
0 0 0 1 1 0 1 1
1 0 0 1 1 0 1 1
1 1 0 1 1 0 1 1
1 0 1 1 1 0 1 1
0 1 1 1 1 0 1 1
0 0 0 0 0 1 1 1
1 0 0 0 0 1 1 1
1 1 0 0 0 1 1 1
0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 1
1 1 1 0 0 1 1 1
1 0 0 1 0 1 1 1
0 1 0 1 0 1 1 1
1 1 0 1 0 1 1 1
1 0 1 1 0 1 1 1
0 1 1 1 0 1 1 1
0 0 0 0 1 1 1 1
1 0 0 0 1 1 1 1
1 1 0 0 1 1 1 1
0 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1
0 0 0 1 1 1 1 1
1 0 0 1 1 1 1 1
1 1 0 1 1 1 1 1
0 0 1 1 1 1 1 1
1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1
d :::g:~
~~~tTT"V\E aO:;;:VUTT
,'
~
,
ROM Code Converters
MM4220DF/MM5220DF
"quick brown fox" generator
general description
along with an even parity bit, for a binary count
input of 64 to 127.
The MM4220DF/MM5220DF is designed for exercising and rapid testing of ASCII and Baudotcoded keyboards, typing mechanisms, and data
communications links by generating the internationally accepted "Quick Brown Fox" message.
device characteristics,
The input is a 7-bit binary sequential count. The
output of a 6 stage up-counter can be used; a
seventh bit selects the desired code. The message
is generated in the 5-bit Baudot Communications
Set code with a binary count input of 0 to 63. The
message is generated in the 7-bit American Standard Code for Information Interchange (ASCII)
The message generator is fu Ily contained on a
monolithic MOS integrated circuit chip utilizing
low threshold voltage technology for increased
DTLlTTL compatibility. For complete electrical,
environmental, and mechanical details, refer to the
MM4220/MM5220 1024-bit read only memory
data sheet.
typical applications
connection diagram
- 1 2 V - - - - - - - - - - - - - - - - -........I--...,
vo'F
A,
VGG
A,
8,
A3
8,
-
6.8K.
TYPICAL.
8UNES
j~
24
A3
A,
22
A,
8,
83
A,
~
20
8,
As
20
MM42200FI
MM52200F
~
8,
7
85
A,
A,
A,
B,
A,
VGG
b,
16
B,
8,
- - - - -. .-
....-~12 14
15
MODE
CONTROL
b,
B,
CHIP
ENABLE
B,
A,
ANY OTl/TTl lOG IC
Vss
B,
Vss
A5
83
85
JOK.
TYPICAL
7UNES
V DD
A,
16 111-'-----4.....-.....,
'----.--r----,---'
lA,
TOPVIEW
·CHIPENABlE---~
tMODE CONTROL - - - - - - '
tMode Control = loglc"D"
OutputsforclfcUitshown
logic levels
Oll/TTl (except ilt MOS/ROM interface)
logic "1",+5V, nom. Loglc"O",ground,nom.
Baudot'Logic"O":"punch"
ASCII' logic inversIOn
As" logiC "1"
·ChlpEnable= logic "l"to obtam outputs
MOS/ROMlnputs& Outputs
loglc",",morenegative loglc"O",moreposttrve
A typical application showing the ASCII-coded test
message as received at a computer terminal.
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
QUICK
QUICK
QUICK
QUICK
QU ICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
BR0"N
BR0WN
BR0WN
BR0"N
BR0WN
BR0"N
BR0WN
BR0WN
BR0WN
BR0WN
BR0"N
BR0WN
1'0X
1'0X
1'0X
1'0X
1'0X
F0X
1'0X
1'0X
1'0X
1'0X
1'0X
1'0X
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JUI":PS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
0VER
0VER
0VER
0VER
0VER
0VER
0VER
0VER
0VER
0VER
0VER
0VER
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 lJE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
D0G 1234567890 DE
191
LL
C
o
code conversion table
N
N
Lt)
OUTPUT CODE
OUTPUT CODE
P
A
R
:E
:E
.........
I
Baudot
ASCII
ADDRESS
OUTPUT
CHARACTER
-
-
-
S
4
3
2
1
ADDRESS
OUTPUT
CHARACTER
T
y
b7
b6
bS
b4
b3
b2
LL
0
CR
1
1
1
1
0
1
1
1
64
NULL
0
0
0
0
0
0
0
0
C
1
CR
1
1
1
1
0
1
1
1
65
CR
0
1
1
1
0
0
1
0
2
LF
1
1
1
1
1
1
0
1
66
CR
0
1
1
1
0
0
1
0
3
o
N
N
~
:E
:E
L"
1
1
1
0
0
0
0
0
67
LF
1
1
1
1
0
1
0
1
4
T
1
1
1
0
1
1
1
1
68
T
0
0
1
0
1
0
1
1
5
H
1
1
1
0
1
0
1
1
69
H
1
0
1
1
0
1
1
1
6
1
0
E
1
1
1
1
1
1
0
70
E
0
0
1
1
1
0
1
7
SP
1
1
1
1
1
0
1
1
71
SP
0
1
0
1
1
1
1
1
8
Q
1
1
1
0
1
0
0
0
72
Q
0
0
1
0
1
1
1
0
9
U
1
1
1
1
1
0
0
0
73
U
1
0
1
0
1
0
1
0
I
0
1
1
1
1
1
0
I
0
0
1
1
11
C
1
1
1
1
0
0
0
1
75
C
0
0
1
1
1
1
0
0
12
K
1
1
1
1
0
0
0
0
76
K
1
0
1
1
0
1
0
0
13
SP
1
1
1
1
1
0
1
1
77
SP
0
1
0
1
1
1
1
1
10
1
1
0
1
0
1
14
8
1
1
1
0
0
1
1
0
78
8
1
0
1
1
1
1
0
R
1
1
1
1
0
1
0
1
79
R
0
0
1
0
1
1
0
1
16
0
1
1
1
0
0
1
1
1
80
0
0
0
1
1
0
0
0
0
17
W
1
1
1
0
1
1
0
0
81
W
0
0
1
0
1
0
0
0
1
0
1
1
1
0
0
N
82
N
0
1
19
SP
1
1
1
1
1
0
1
1
83
SP
0
1
0
1
1
1
1
1
F
1
1
1
1
0
0
1
0
84
F
0
0
1
1
1
0
0
1
0
1
1
1
0
0
1
1
1
85
0
0
0
1
1
0
0
0
0
22
X
1
1
1
0
0
0
1
0
86
X
0
0
1
0
0
1
1
1
23
SP
1
1
1
1
1
0
1
1
87
SP
0
1
0
1
1
1
1
24
J
1
1
1
1
0
1
0
0
88
J
0
0
1
1
0
1
0
1
25
U
1
1
1
1
1
0
0
0
89
U
1
0
1
0
1
0
1
0
26
M
1
1
1
0
0
0
1
1
90
M
1
0
1
1
0
0
1
0
21
1
1
1
0
1
1
18
20
0
1
P
1
1
1
0
1
0
0
1
91
1
0
1
0
1
1
1
1
28
S
1
1
1
1
1
0
1
0
92
S
1
0
1
0
1
1
0
0
29
SP
1
1
1
1
1
0
1
1
93
SP
0
1
0
1
1
1
1
1
30
0
1
1
1
0
0
1
1
1
94
0
0
0
1
1
0
0
0
0
31
V
1
1
1
0
0
0
0
1
95
V
1
0
1
0
1
0
0
1
32
E
1
l'
1
1
1
1
1
0
96
E
0
0
1
1
1
0
1
0
33
R
1
1
1
1
0
1
0
1
97
R
0
0
1
0
1
1
0
34
SP
1
1
1
1
1
0
1
1
98
SP
0
1
0
1
1
1
1
1
35
T
1
1
1
0
1
1
1
1
99
T
0
0
1
0
1
0
1
1
1
100
H
1
0
1
1
0
1
1
1
1
0
P
1
H
1
1
1
0
1
0
1
37
E
1
1
1
1
1
1
1
0
101
E
0
0
1
1
0
1
38
SP
1
1
1
1
1
0
1
1
102
SP
0
1
0
1
1
1
1
39
L
1
1
1
0
1
1
0
1
103
L
0
0
1
1
0
0
1
1
40
A
1
1
1
1
1
1
0
0
104
A
1
0
1
1
1
1
1
0
41
Z
1
1
1
0
1
1
1
0
105
Z
1
0
1
0
0
1
0
1
42
y
1
1
1
0
1
0
1
0
106
Y
1
0
1
0
0
1
1
0
43
SP
1
1
1
1
1
0
1
1
107
SP
0
1
0
1
1
1
1
1
44
D
0
G
1
47
48
49
1
36
45
46
1
1
1
1
0
1
1
0
108
0
1
1
1
0
1
1
1
1
0
0
1
I
1
109
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
1
110
D
0
G
1
1
1
0
1
1
1
0
0
0
SP
1
1
1
1
1
0
1
1
111
SP
0
1
0
1
1
1
1
1
Fog
1
1
1
0
0
1
0
0
112
1
0
1
0
0
1
1
1
0
1
1
1
0
1
0
0
0
113
2
0
1
0
0
1
1
0
1
0
50
2
1
1
1
0
1
1
0
0
114
3
1
1
0
0
1
1
0
51
3
1
1
1
1
1
1
1
0
115
4
0
1
0
0
1
0
1
1
52
4
1
1
0
1
0
1
116
5
1
1
0
0
1
0
1
0
5
1
'1
1
1
53
1
0
1
1
1
1
117
6
1
1
0
0
1
0
0
1
0
54
6
1
1
1
0
1
0
1
0
118
7
0
1
0
0
1
0
0
55
7
1
1
1
1
1
0
0
0
119
8
0
1
0
0
0
1
1
1
56
8
1
1
1
1
1
0
0
1
120
9
1
1
0
0
0
1
1
0
57
9
1
1
1
0
0
1
1
1
121
0
1
1
0
0
1
1
1
1
58
0
1
1
1
0
1
0
0
1
122
SP
0
1
0
1
1
1
1
1
59
SP
1
1
1
1
1
0
I
1
123
D
1
0
1
1
1
0
1
1
60
L"
D
1
1
1
0
0
0
0
0
124
E
0
0
1
1
1
0
1
0
1
1
1
1
0
1
1
0
125
SP
0
1
0
1
1
1
1
1
62
E
1
1
1
1
1
1
1
0
126
DEL
0
0
0
0
0
0
0
0
63
SP
1
1
1
1
1
0
1
1
127
DEL
0
0
0
0
0
0
0
0
67
66
65
64
63
62
61
68
67
66
6S
64
63
62
61
61
68
Baudot: logiC "0"
= "punch"
Spdce
WHEN CHIP ENABLE INPUT IS AT A LOGICAL O. ALL
OUTPUTS ARE AT A LOGICAL 1
192
74
15
27
SP
b1
ASe II. LogiC mverslon
s:
s:
ROM Code Converters
~
N
N
o
m
"s:
.........
s:
(J'I
MM4220EK/MM5220EK
N
N
BCDIC-to-EBCDIC and ASCII-to-EBCDIC code converters
o
m
"
general description
TheMM4220EK/MM5220EK isa 1024-bitread only
memory that has been programmed to convert
both Binary Coded Decimal Interchange Code
(BCD I C) and the American Standard Code for
Information Interchange (ASCII) to Extended Binary Coded Decimal Interchange Code (EBCDIC).
ASCII code in addresses 64 through 127 has a "1"
in the most significant (A 7 ) bit which is used with
the selection logic. The resulting 6-bit ASCII input
is for display-only upper case and numerical
codes, since it will not accept the control commands or the lower case characters.
The BCDIC-to-EBCDIC converter is located in the
first 64 8-bit bytes of the ROM. The unused parity
check bit (the most significant input BCDIC bit) is
always a "0".
device characteristics
For full electrical, environmental and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
The ASCII-to-EBCDIC converter is located in the
second 64 8-bit bytes of the ROM. Thus, the input
typical application
connection diagram
---4.-....---,
- 1 2 V - - - - - - - - - -_ _ _ _ _
b,
1
b,
2
b,
4
b,
bs
bo
8
A
B
6.8K.
TYPICAL.
8 LINES
GATES DM7400
24
A,
23
Voo
B,
A,
A,
B,
A,
B,
)0----+---121
)O-_ _- +_ _A~S 20
B,
~~~~~~~~/
A,
8 Bs
A, 18
9 Bo
)O----+--~19
"COOE"
3.0K.
TYPICAL.
7 LINES
+12V
A,
B,
101-'-----+----t
-------4....
B,
1 1 1 - ' - - - -.....~
Vss
--e----.;~12
OTL/TTL LOGIC
tA,
A,
8,
As
B,
A,
B,
A,
Bs
VGG
B,
MOOE
CONTROL
B,
CHIP
ENABLE
B8
A8
13
Vss
TOPVIEW
'CHIP ENABLE - - _....
tMOOE CONTROL - - - - - - - '
logu::levels
OTL/TTL (except at MOS/ROM interfacel
logic "1",+5V, nom. logic "O",ground, nom.
tModeControl=logic"O"
As= Logic"1"
·ChipEnable=logic"1"toobtainoutputs
MOS/ROM Inputs & Output
logic"l",morenegative.Logic"O",moreposltive
193
'code conversion tables
FUNCTION
CODE
INPUT
OUTPUT
ROM
ADDRESS
BCDIC
SYMBOL
EBCDIC
SYMBOL
,
Space
2
0
C
0
D
E
,
Space
0
2
B
2
, ,
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
,
3
3
0
0
0
0
4
4
0
0
0
0
5
5
5
0
0
0
0
6
6
0
0
0
7
6
7
0
7
0
0
0
0
8
9
8
8
0
0
0
9
0
0
·0
'0
9
. 0
0
0
0
0
,
,
"
# or-
#
0'
0
0
@or'
@
0
0
0
0
>
0
0
0
0
0
TM
Space
0
0
0
0
0
>
'6
JITMI
Space
'7
/
/
0
0
'8
S
T
S
T
0
0
0
0
U
U
0
0
'9
20
2'
22
V
V
0
0
W
W
0
0
23
X
0
0
24
y
X
y
0
0
25
Z
Z
0
0
26
tlRMI
AM
0
0
%-or (
%
27
28
0
29
0
0
0
0
0
\
!If
33
J
J
0
34
K
K
0
35
L
L
0
0
36
M
M
0
37
N
N
0
38
0
P
0
P
0
C
R
Q
0
R
0
39
40
4'
42
43
45
$
$
48
1
I
A
50
8
C
53
0
0
0
f\
& or
49
5'
52
0
0
46
47
0
0
44
t
0
E
&
0
A
0
8
0
C
0
E
0
0
0
F
F
55
G
G
0
0
56'
57
H
H
0
I
I
0
54
58
0
59
0
60
tI or)
D
0
6'
62
[
(
0
<
<
0
63
194
0
0
30
~
*
0
0
3'
32
0
CODE
INPUT
OUTPUT
ROM
ADDRESS
ASCII
SYMBOL
EBCDIC
SYMBOL
0
64
@
0
66
B
INPUT
OUTPUT
C
3
'4
15
OUTPUT
BCDIC
A 8 4
4
'2
13
FUNCTION
INPUT
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
, .'
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
,
1
0
0
,
0
0
,
0
0
0
0
0
,
0
0
0
0
,
,
,
0
1
0
0
,
,
, ,
, ,
,
, ,
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
, ,
, ,
, , ,
,
,
, ,
,
, ,
,,
, , ,
,
,
, ,
,
, ,
, ,
, , ,
,
,
, ,
,
, ,
, ,
, , ,
0
0
0
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
,
,
,
,
,
,
,
1
0
0
0
,
,
,
,
,
,
,
,
1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
0
0
0
0
0
0
,
,
,
,
,
,
,
,
0
,
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
, ,
, ,
, ,
, , ,
, ,
, , ,
, ,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
7
0
0
0
0
0
0
1. 1
1
1
1
0
0
B
1
0
0
0
0
1
0
1
1
0
0
0
0
1
0
2
EBCDIC
3 4 5
67
e e l
0
0
0
0
1
1
1
1
0
0
0
a
1
1
68
DOl
a
0
0
1
0
0
1
1
0
0
0
1
0
0
70
F
FlO
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
~--,7c.:.'_--+-_.:::G_--+-_-=G'------+-',-+-,0,+-,,0,+-,,0+1
72
H
H
1
0
0
1
a
1
0
1
0
1
1
.1
1
0
0
0
0
0
1
1
0
a
1
0
1
0
0
0
74
J
J
1
a
1
0
1
1
0
'1
0
0
0
"
K
K
1
a a
a a
1
75
1
tJ
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
77
M
M
1
0
0
1
1
0
1
1
1
0
1
0
1
a
0
78
N
N
1
a a
1
1
1
0
1
1
0
1
0
1
a
1
0
0
0
0
0
80
P
P
101000011010111
0
0
0
0
0
0
,
1
81
a
0
0
0
1
1
0
82
A
R
1
1
0
a
1
a
1
1
a
1
1
a a
a
0
0
a
a
1
,
0
1
83
S
S
1
0
1
0
0
1
1
1
1
,
0
0
0
0
0
0
84
T
T
101010011100011
1
85
0
86
V
V
101011011100101
87
W
W
1
88
X
X.
1
89
Y
Y
101100111101000
Z
Z
101101011101001
,
,
0
0
0
0
1
0
0
1
0
0
,
,
,
,
0
0
,
,
,
,
,
0
0
0
0
0
0
0
,
0
0
,
,
, ,
, , ,
,
, ,
,
, ,
0
0
0
0
90
91
[
0
0
0
92
93
1
0
94
,....., or
--,
0
95
-
-
96
Space
Space
0
0
0
0
0
0
0
0
,
0
0
0
1
97
0
0
0
,
- 98
0
0
1
0
0
,
,
0
0
0
0
0
0
,
, ,
,
0
0
0
,
,
,
0
0
0
0
0
0
1
0
,
,
0
0
,
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
,
0
0
0
0
0
0
0
,
1
0
,
1
,
,
0
1
a
1
1
1
1
1
1
0
1
1
0
0
a
1
1
1
0
1
0
a
a
1
,
0
1
0
1
1
0
1
1
1
0
,
,
0
1
1
0
1
0
0
,
1
0
a
1
,
1
,
1
1
a
0
1
0
0
1
,
0
0
0
1
a
,
0
1
a a
0
a
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
,
0
0
0
1
0
0
1
0
1
1
..,
1
1
1
1
1
0
,
1
1
1
1
0
1
0
0
0
0
1
0
1
0
,
1
1
,
110001101111011
,
'00100010110"
110010101101100
"001100'010000
104
"0'0000100"0'
110100101011101
0
110101001011100
0
110110001101011
110101101001110
110110101100000
110111001001011
0
0
0
1
\
0
0
1
1
I '
0
0
0
..
1\
0
a
a
I ' 0
0
0
0
\
1
, , ,
,
,
, ,
,
, ,
, ,
, , ,
,
,
, ,
,
, ,
, ,
, , ,
,
, , ,
, ,
,
, ,
,
, ,
0
0
0
1
u,
U
0
0
,
, ,
, ,
, ,
, ,
, ,
, ,
, ,
, ,
, ,
, ,
, , ,
, ,
,
,
,
,
,
,
,
,
,
, ,
,
, ,
,
,
, , ,
Q
0
0
, ,
, ,
0
S
0
0
1
0
0
,
1
0
0
0
0
@
,
0
0
ASCII
E bS bS b4 b3 b2 b,
0
0
1
,
, ,
, ,
, ,
,
, ,
,
,
, ,
g
0
0
0
,
,
,
7
,
,
, ,
0
1
0
S
0
,
,
,,, ,, ,
,
, , , ,
,
, ,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
,
,
,
,
,
,
0
1
0
0
0
0
0
,
,
,
,
, , ,
,
, ,
, ,
, ,
,
0
0
0
0
0
1
0
,
,
,
, ,
,
, ,"
0
0
, ,
0
1
,
,
,
,
,
1
0
,
,
0
,, ,
,
,
, , ,
,
,
, ,
,
,
, ,
,,
,
, ,
, ,
, ,
0
0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
, ,
1
,
0
EBCDIC
2 3 4 S
110111101100001
111000011110000
0
111000111110001
0
0
0
1
116
1
1
0
0
1
1
1
1
1
1
0
0
1
1
111010011110100
0
0
0
0
0
0
0
0
119
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
<
>
0
0
1
1
1
111101001111010
123
0
0
1
0
0
127
1
1
1
0
1
1
0
1
0
1
1
1
1
0
<
1""000'001100
1 1 1 1 1 0
1 0
1
1 1
1
1 1 0
>
1
1
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
3:
s:
ROM Code Converters
~
N
N
o
r-
::D
"3:
MM4220LR/MM5220LR BCOIC to ASCII-7/
ASCII-7 to BCOIC code converter
3:
C1I
N
N
genera I description
o
The MM4220LR/MM5220LR is a 128 x 8 read
only memory which has been programmed to convert the 64 characters of the Binary Coded Decimal
Interchange Code (BCDIC) to the American Standard code for I nformation I nterchange in seven
bits (ASCII-7).
r-
address 63, converts the 64 character ASCII
graphic subset to BCDIC. The tables show the
character assignments and their binary equivalents.
::D
For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet.
The first half of the ROM, from address 0 to
connection diagram
Dual-In-Line Package
A3
1
A,
2
24
VOD
15
~~:BlE
MODE
CONTROL
Vss
12
14
As
13
NC
typical applications
ASCII to BCDIC
BCDIC to ASCII
195
code conversion tables
ASCII to BCOIC
CODE
FUNCTION
ROM
ADDRESS
INPUT
OUTPUT
ASCII
SYMBOL
BCOle
SYMBOL
"
:
11
"
"
"
"
"
..
" 's
ASCII
b4
b3
: : : :
: : : :
,
.
: :
%
:
"
,e
Blank
V,
I
CR
I
:
:
20
23
"
.
:
:
f
"
"
"
@
A
0
"
@
A
~
~
.0
;
: :
; ;
~
~
0
~
V
~
W
w
I
I
\
I
: :
:
:
:
I
:-+ :
;
A,
Ao
AS
A4
;
'3
A,
BCOle
SYMBOL
aCOIe
8
SYMBOL
,
0
0
:
:1+
0
0
o
,
0
o
;
:
:
;
-;,
:
0-
o
0
-:--~~- ~~~
:
:
;
+
~- ~
: :
.,
"
i-+-
r+
;
I-+-
-~-~~ --?s- --%- f-6 A,
: :
:
:
:
.-~~ r+ :
: :
:
:
;
--
-~
\
;
; ;
;
-T-~~~
BCOIC to ASCII
196
;
: :
0-
:
;
:
: :
:
~: : -is; -+ f-+~t
: f-i-- I-': r+
:
0
:
:
:
;
;
,
: : ::
"
:
:
: ::
:
: : : : ;;
,
:
;
-~
"
"
""
,."
'"
.2
"
;
:
;
'0
"
"
"
;
A
:
:
: :
:
: : : :
BCOle
;
; ;
:
:
:-: :
:
--1--
28
:
MCI
DATA
:
: :
:
" "
~~f--T
:
11
.: :
OUTPUT
INPUT
0
0
;
;
:
;
..
:
;
;
·S
·4
·3
·2
.,:
ROM Code Converters
MM4221RQ/MM5221RQ ASCII-7 to EIA RS244A/
EIA RS244A to ASCII-7
general description
The MM4221 RO/MM5221 RO is a 1024-bit read
only memory that has been programmed to convert between the American Standard Code for
Information Interchange, compressed to six bits,
and the: Electronic I ndustries Association numerical control standard code, RS244A. The second
group of addresses; from 64 to 127, effects the
reverse conversion.
applications information
In the first 64 entries, compression of ASCII-7 to
six bits has been accomplished by dropping bit b6 ,
and substituting the control codes listed for certain
unused ASCII graphic symbols.
In the second 64 entries, the RS244A parity check
bit, C5 is ignored. The bit Cs , used only for the
end of block code (EOB) is used externally to detect existence ofthis symbol, and to insert a redundant code, C4 . C2 (ROM address 74). This code
will be translated arbitrarily as an ASCII EXT.
typical application
lOWTRUE
~
RS244A
lOW TRUE
~
ASCII
RS244A
I
Vss
B,
A,
B,
c,
A,
c,
B,
b,
A,
c,
B,
A,
B,
A,
B,
c,O-+----i
c,
All
6.aK
c,Q------i
INPUT
MULTIPLEXER
CODE
SELECT
Q=RS244AtoASCIl
1" ASCII to RS244A
*lOW=Gra:phlc
HIGH "Contfol
197
code conversion tables
ASCII to RS244A
.,.
ROM
ADDRESS
b,!b,!b,1 b3!b2!bl
SYMBOL
~
~
~
~
:
eOR
,.
TAB
~
:
~
: :
~
~
~
:
~
:
~
:
~
InCfeas,ngB,nary
Sequence
~
~
:
: :
~
~
~
~
~
~
~
~
~
~
:
:
:
:
~
:, .:. , .. I',
..
:
:
: :
:
~
:
~
"3' '2'."
RS244A to ASCII
ADDRESS
SYMBOL
<,
SYMBOL
:
"
~
~
'"
~
CCfG
b,
: :
: :
b,
:
~
~
~
~
:
:
".
-----B-
bJ
: :
bz
b,
~
~
~
~
~
~
~
:
f-i-
B.
:
:
:
~
"
B'
InU""""'g B,n"ry
Se'1ue"L~
"
BB
~
"
---+-
:
~
~
:
~
~
:
~
~
~
~
:
f-i-
"
~
..
,.,
:
5B
,
:
,.,
=ffi=
:
:
~
....l..
....l..
-+
f-------ifi-
~
'"
:
:
'"
'"
~
198
Cc
:
: : :
OS
-+
.,
.. " .. '3 '2
"
.:
., .. :. .,
~
·3 ~ .,
ROM Code Converters
MM4221RR/MM5221RR ASCU-7 to EBCDIC code converter
general description
The MM4221RR/MM5221RR is a 1024-bit readonly memory that has been programmed-to convert between the 128 characters of ASC 11-7" the
American Standard Code for Information Interchange in seven bits, and EBCDIC, an extended
binary coded decimal interchange code. This conversion follows the EBCDIC character assignments
used in the IBM 1130 computer.
Certain arbitrary assignments have also been made
for maximum usefulness, and in these two areas
the part differs from the MM4230QY /MM52300Y,
which follows American National Standard ANSI
X3.26 recommendations for character assignments.
For electrical, environmental and mechanical details, refer to the MM4221/MM5221 data sheet.
typical application
ASCII-7 to EBCDIC
+5V
ASCII·7
EBCDIC
BINARY
HIGH TRUE
12,16
MSB
b7
b6
18
A7
B8
19
0
MSB
B7
A6
B6
20
bs
11
10
As
21
b.
A.
b3
A3
b2
A2
b,
A,
MM4221RRi
MM5221RR
Bs
B.
B3
LSB
B2
LSB
B,
15,17,24
6.8K
6.8K
LOW
TRUE
-12V
199
a:
a:
....
code conversion tables
N
N
Lt)
:E
:E
SYMBOL
o
'"a:
....Na:
o
o
0
o
0
,
Bee
BS
0
,
0
0
0
0
,
,
0
0
0
o
,
0
0
,
,
1
0
0
0
0
o
0
0
0
0
0
82
0
0
0
CF
N
~
SO
:E
:E
DC'
SO
AS
,
23
, ,
CONTINUING BINARY
SUB
SeQUENCE
ESC
2B
FS
GS
GS
o
0
,
38
1
1
~
8,
ROM
ASCII
EBCDIC
ADDRESS
SYMBOL
SYMBOL
0
0
~
~
~
:
8S
8,
83
0
0
o
0
8,
, 1010 10 10 10 10
I
I
I
,
0
0
1
0
0
,
0
0
0
CONTINUING BINARY
SEQUENCE
1
1
0
0
0
1
1
0
0
1
o
,
o
,
o
,
o
~
A,
200
I As I AS I A4 I A3 I A2 I A,
,;;.
B,
0
~
:.
~
8S
8,
~
~
~
83
82
8,
~
~
ROM Code Converters
ll1S
~
N.
W
o
tXJ
o
........
MM4230BO/MM5230BO hollerith to ASCII code converter
~
~
<.n
general description
N
W
used to compress the 12 Hollerith lines to eightline binary encoded form suitable for use by the
read-only memory. This appl ication is shown
below.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
The MM4230BO/MM5230BO 2048-bit MOS readonly memory has been programmed to convert the
12 line Hollerith punched card code to eight level·
ASCII. This conversion conforms to the American
National Standard (ANSI x 3.26 - 1970). Three
TTL 4-input NAND gates, and three inverters are
o
tXJ
o
connection diagram
typical application
Dual-In-Line Package
QINPUTNANDGATESARE
OM14JOTYPES
ROW
2_
3-
:~
:-+
,
PUNCHED
CARD
..c
!
==:I
OMB812 TVPES
~"
./'
41K
41K
47K
A1
gJo.-l'--.
./'
A2
~[>
A4
r
I
A7
11
A'
12
NOTES.
1 Vss=+12.QV10%,V oo =GNO,V oo --1Z0V'l)'I,
2
~:~:~:~:~:,;~~~:;o~:~0~rr:~!~n!~~:~ ~~~~~~;·Ddf
~~:::K
I
12
3
a
OUTPUT
0-;'::'
15
A,-3
22r- NC
B,-'
21r-A4
'f-7f--
f.
'r--
f,
'r--
f,
B,-9
O>-:f'
88 _11
82 - 5
20~A5
83 - 6
19r A6
84 - 7
lSI-- A7
85
87
18
"
I
"
"
("
"
-
11~A8
8
16r-VGG
15t--~g~iROl
10
14r-~~~BlE
t3t-- A9
TOP VIEW
ANYOTL/TTl
'OK
\6
"
-
Vss _l2'
,-
DEVICE
j.7K
23r-NC
f,
MM5230BO
"
24~VOD
Az-Z
f,
21
10
A]-l
Sf--
2
"
AS
ZONE
CONTROL
A3
9
PUNCHES
v"
INVERTERS ARE
68K
TRUE
'OK
I 1
E~!~PLE v!o v1,
rUNES8T012
code conversion table
Hollerith to ASCII
12
12
12
11
11
0
0
1>
SP
t
:
!
12
11
0
12
12
11/10
10/8
11/1
11/9
11
0
12
11
0
12/3
11
0
12
11
0
12/10
13/1
13/8
1
A
J
/
1
a
j
-
13/9
SOH
DC1
8/1
9/1
10/0
10/9
9/15
11/11
9
-1
2
B
K
5
2
b
k
s
13/10
STX
DC2
8/2
SYN
10/1
10/10
11/2
11/12
9
-2
3
C
L
T
3
c
I
t
13/11
ETX
DC3
8/3
9/3
10/2
10/11
11/3
11/13
9
-3
4
0
M
U
4
d
m
u
13/12
9112
9113
8/4
9/4
10/3
10/12
11/4
11/14
9
-4
5
E
N
V
5
e
n
v
13/13
HT
8/5
LF
9/5
10/4
10/13
11/5
11/15
9
-5
6
F
0
W
6
f
0
w
13/14
8/6
BS
ETB
9/6
10/5
10/14
11/6
12/0
9
-6
&
8-2
11
0
8-1
7
G
P
X
7
9
P
x
13/15
DEL
8/7
ESC
EOT
10/6
10/15
11/7
12/1
9
-7
8
H
G
Y
8
h
q
y
14/0
9/7
CAN
8/8
9/8
10/7
11/0
11/8
12/2
9
-8
9
I
R
Z
9
I
r
z
14/1
8/13
EM
8/9
9/9
NUL
OLE
8/0
9/0
9-8-1
I
\
[
8-3
$
8-4
<
8-5
(
8-6
+
8-7
!CD
%
12/11
13/2
14/2
8/14
9/2
8/10
9/10
14/8
14/14
15/4
15/10
9-8-2
12/5
12/12 13/3
14/3
VT
8/15
8111
9/11
14/9
14/15
15/5
15/11
9-8-3
@
12/6
12/13 13/4
14/4
FF
FS
8/12
DC4
14110
15/0
15/6
15/12
9-8-4
12/7
12/14 13/5
14/5
CFt
GS
ENG
NAK
14/11
15/1
15/7
15/13
9-8-5
12/8
12/15 13/6
14/6
SO
RS
ACK
9/14
14/12
15/2
15/8
15/14
9-8-6
12/9
13/0
14/7
51
US
BEL
SUB
14/13
15/3
15/9
15/15
9-8-7
-
I
>
CD may be 'r
®mav be
12/4
=
®
>
=
13/7
Note: The entrees of Form AlB refer to the unassigned locations In the right hand Side of the ASCII table (bit Ea
deSignated for specialist use. (See National Bureau of Standards Techntcal Note No. 478,)
==
1)
"I"
Note: For the full ASCII-S Code Table, see MM42300Y/MM5230QY data sheet
201
w
u..
o(It)
ROM Code Converters
N
Ln
~
~
"W
u..
o
(It)
MM4230FE/MM5230FE selectric-to-EBCDICI
EBCDIC-to-selectric code converter
N
q~
~
general description
counterparts, it is not necessary to encode bit
position 0 (A8), which is used instead as the code'
converter selection bit. I n addition to the Selectric
Correspondence output code bits there is a bit to
indicate upper or lower case. The odd parity bit
generated does not account for the case bit.
The MM4230FE/MM5230FE provides for the conversion of I BM Selectric Correspondence Code to
Extended Binary Coded Decimal Interchange Code
(EBCDIC) in both directions. These two decoders
are contained on a monolithic MOS device.
The Selectric-to-EBCDIC converter is located in
binary addresses 0 through 127. Input bit A7 is
used as a single I ine command to determine
whether upper (denoted by a "1") or a lower
(denoted by a "0") case has been selected.
device characteristics
For full electrical, environmental, and mechanical
details refer to the MM4230/MM5230 2048-bit read
only memory data sheet.
The EBCDIC-to-Selectric converter is located in
binary addresses 128 through 255. Since not all
EBCDIC control commands have Selectric code
typical application
connection diagram
-12Vde _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....
........
~~
....
'12V de -----~___t~
• 5 V d e - -.....--+---i~_t_-------_+_-t__+--...- VD
3.0K.
TYPICAL.
BliNES
Vss
12
?
24
16
A,
A,
A,
A,
A,
VGG
6.BK,
TYPICAL,
BliNES
B,
B,
2
MM4230FEI
MM5230FE
7
B,
20
lB
A, 17
OMBB12
TTl GATES
NC
A,
22
NC
B,
21
A,
B,
20
A,
B,
A.
B,
A,
B,
AB
B.
VGC
B,
MOOE
CONTROL
B,
10 ~-----i~-4
11
B,
11
Vss
12
B,
DM7400 SERIES
TTl GATES
-12V de
'CHIP ENABlE---.......
+12V de -';';;';';;"';";";';''';;';;'--1
logic Levels
OTLITTl (eKeept at MaS/ROM IOterface'
logiC "1", +5V, nom, logic "0", ground, nom.
MaS/ROM Inputs & Outputs
loglc"l",morenegative.loglc"O", more pOSitive
·ChipEnable=loglc"l"toobtalnoutputs
202
A,
23
B,
As 19
A,
24
B,
1
21
VDD
A,
TOP VIEW
14
CHIP
ENABLE
13
A9
3:
s:
code conversion table-selectric-to-EBCDIC
~
N
OUTPUT
INPUT
C
SELECTRIC EBCDIC
ADDRESS SYMBOL
SYMBOL
ROM
0
1
2
3
4
5
5
7
8
.
10
11
'2
13
14
15
15
. .
b
b
w
w
5
0
5
5
'8
NULL
4'
50
51
52
53
54
55
55
57
58
5.
50
51
52
53
...
.
..
55
67
68
NULL
2
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
8
8
I
I
4
d
7
d
7
NULL
NULL
NULL
,
3
,
NULL
3
NVLL
NULL
NULL
NULL
9
m
m
1
!
-
-
8
8
w
w
(
(
Q
a
y
.
H
H
7'
7.
76
77
78
5
5
E
E
7'
80
81
82
83
"
NULL
85
86
87
88
8.
90
91
92
93
N
70
71
72
73
..
...
..
95
K
I
"'
"'
I
y
1
1
p
p
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20
21
22
23
24
25
25
27
28
2.
30
31
32
33
34
35
35
37
38
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40
41
42
43
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47
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4
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6
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0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
1
~
~
0
0
0
1
0
B3
~
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
B2
B,I
ROM Code Converters
M~4230JT/MM5230JT
BCDIC to EBCDIC/
EBCDIC to BCDIC code converter
general description
Character assignments for the EBCD,C are given
to IBM 1130 specifications. All the non-alphanumeric assignments in BCDIC are subject to specialist usage, and care should be taken over them.
The MM4230JT /MM5230JT is a 2048-bit read-only
memory that has been programmed to convert from
the 64-entry, 6-bit Binary Coded Decimal Interchange Code (BCDIC) to the eight-bit extended
BCD interchange code (EBCDIC) and back again.
The tables show the two translations in binary.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
connection diagram
Dual-In- Line Package
MODE
CONTROL
CHIP
typical applications
BCOIC to EBCDIC
',,- "
"~~.,,
I
'"
'"
." ." ." ."
EN;~~-
14
co~~~g~-
15
"'~'''I''''~::
1
"
A,
10M".
I
o
I
0,
-n
EBCDIC
HIGH
OU1PUTSTRUE
:~:
I
1"
==),..-.0,
==),..-.0,
i~.
20
,,- "
"0
f>-->'
1~,
~"
A,HIGH
A,HIGH
t
." I
O.
I
,~
J---o,'co,
:11
!
I
~
EBCDIC to BCOIC
·:::=Fl=====~F~~~~~fB~t.:."i:,"
,
".-"
~."." ."
'"
'"
":;."::-,,
,,:~::~- "
.---1~~~---'--' ~"
'M,,,,
'" '" '" '" ,,,t,, ,,,.~,,
M:0a---:'~)o-"-r-+--t--+-+-+----'r-.,~
==<.)c>--t----i---+-+-t--l~---+-""'_i,,
~Ja---r---I--+--+-+----_+_"--i" '"
'0--
'0--
'0-
r=(Ja---+-----f--+-+-------+--==,.'--I"
~.
"r"
I
I
l
"1-"
I--"--'>--+-+--+-t---+--rl~
~--~~-+-r-!~~
~---------+-~II~,
,--.!!-.-
NC-23
I
I
: 1
I
ts. •• p...""gmod,"ol><
(MM4230dm,h .. tl
205
code conversion tables
BCDIC to EBCDIC
FUNCTION
ROM
ADDRESS
:
;
"
"
"
"
INPUT
OUTPUT
SYMBOL
SYMBOL
NULL
NULL
~BCDIC
;
;
:
c·
.
Space
Space
~
~
w
~
2J
;
NULL
B,
NULL
~
"
.
OUTPUT
EBCDIC
..
:
:
"
J6
B,
:
: : :
:
: : :
: :
~ :
: :
: :
: : :
: :
27
"
:
FUNCTION
CODE
B,
B,
:
:
:
:
:
:
: : :
:
:
: :
: ~ :
: :
:
: :
;
:
:
:
: : : :
..
"
"
"
"
"
"
"
EBCDIC
CODE
OUTPUT
EBCDIC
B,
B,
B,
..
B,
t-
'"
"
"
"
"lUlL
:
NUll
NULL
NUlL
NULL
NUll
NUll
NUll
:
:
:
:
:
NUlL
NUll
NUll
NULl
NULL
:
:
:
:
NUll
NULL
NUll
NULL
NUll
NUll
NUll
NULL
NUll
NULL
NUll
NUll
"
'"
NULL
NUll
NUll
NVll
NULL
NUll
NULl
NULL
NULl
NULL
NULL
NVLI
NUlL
('\jUtL
'"
'02
NULL
'"
'"
'"
NULL
NULL
NULL
NULL
'"
NULL
NULL
NliLL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
:
:
: :
:
:
~
: :
NVlL
NULL
'"
'"
'"
'"
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
'"
NULL
NULL
,n
,CO
NULL
NULL
'"
NULL
'"
on
,,,
'"
'"
'"
: :
: : : :: ::
: :
:
:
:
: : :
:
:
:
:
: :
:
:
NULL
"0
'"
'"
;
; ;
; ;
:
NUll
NULL
NULL
"'"
'"
B,
NULL
~- ~i~-
"
B2
--
NULL
"
;
;
'0
"
"
"
"
"
"
B,
: :
(i!)
~
~
OUTPUT
r-:';-'"
: :
:
:
: :
: :
M
INPUT
BCOle
~YMBOl
C,'
:
:
: :
:
:
:
:
"
ROM
ADDRESS
B,
~
~
"
"
B2
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NUtl
:
:
:
:
:
:
:
EBCDIC to BCDIC
FUNCTION
ROM
EBCDIC
ADDRESS
SYMBOL
ROM
AODRESS
SYMBOL
CODE
INPUT
OUll'UT
OUll'UT
EBCOIC
SYMBOL
BCOIC
SYMBOL
BCDIC
BS
B4
B,
B,
B6
B,
B2
B,
:
:
:
: ;
:
: ;
: : : :
;
'"
:
CO,
:
'00
,.>
: ;
'"
: :
'"
: :
:
:
"'"
:
: : :
"'"
:
'"
~ ~- ~f..+
'"
i;:i- ~ f-~ : : : : t-~
'"
:
'"
'"
'"
:
'"
'"
'"
'"
'"
'"
,~
205
NUll
NULL
NULL
NULL
NULL
NULL
NtlLL
NULL
NUll
NULL
NULL
NULL
NULL
-N
'"
NULL
"0
-
N
NUll
NUll
NULL
NUll
NULL
NULL
NULL
NULL
m
NULL
NULL
",
NULL
NUll
'"
NUll
NUlL
: :;
'"
'"
'"
n'
'"
'"
",
",
",
'"
'"
'"
'"
'"
245
o
'"
'"
'"
'"'"
,
,
0
,
0
;
w
;
NULL
NULL
NULL
NUl\"
NULL
NULL
NULL
NULL
NULL
NULL
:
:
NUll
:
251
NULL
NULL
'"
'"
",
NULL
NUll
255
206
w
NUll
NULL
NUlL
NULL
NULL
NULL
:
: :
: :
:
:
:
:
:
:
:
: ::
~
~
~
~
:
;
;
:
: : : : :
: : : :
;
:
: : ; ;
;
:
~
~
: :
: :
: ~
ROM Code Converters
MM4230KP/MM5230KPASCII-7 to selectric code converter
general description
characters, ± and ri exist only for Selectric, and>
and
only for ASCII. The former problem is
handled in the MM4230KP/MM5230KP by exploiting the inherent redundancy of the bail code
(see Table 2). The latter inconsistency is resolved
by making arbitrary equivalences between the
unique characters. The two tables show the treatment of both the characters which have equivalents
in both codes, and those characters, and the functions, which do not. Encoding and decoding the
Selectric functions that the user requires is a
matter of conventional Boolean logic. A typical
example is shown below.
The MM4230KP/MM5230KP MOS read-only memory has been programmed to perform the conversion between the American Standard Code for
Information Interchange in seven bits (ASCII)
and the Selectric correspondence bail code transmitted and received by the I BM Series 7 input/
output printers.
<
application hints
The ASC II field and Selectric bail code field as
defined do not map exactly: for instance "space"
is handled as a normal 7-bit code in ASCII, but is
handled as a unique switch and solenoid pair in the
Selectric printer. And even among the graphic
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical application
d
L~I!
ICINPUT
2
,
I,~
A
BAil
CODE
INPUTS
FROM
SElECTRIC
:~
01'
R
,.- -
~I'
~
3K
Z"
v"
z.
01·
rEsZ.,
-=U-:01'
Z'I-Qr----;,'--'-
z,1-
~
~
T
)
PLACES
!b OM8322 Ze
-----f I
~
+lr
--A,
B,
A,
B,
A,
B,
"-
:.c:v:.
B,
ASCUTO
A
S:~~~~~~~~O
B,
C
,-----2. f b OM83Z2 Zb~!-----
_
A,
:iI'
rt ;[
B,
A9
Me
CE
Voo VGG
Iii!
+llV
-
S.8K
~~c~s_f
1'fi
~~~l:ESPONDENCE
R2
~~~~;~
TO
;::tY
-L-.J>-
.... LY- ...,
c{:::---
B,
A,
~A,
'p->
~
B,
ASCII
lOW TRUE
SELECTRIC
R-->
"-
MM52JOKP
A.
,
' A~
MACHINECOOEORNON
PRINTING CHAR (SElECTAIC)
...L'>-+
...,=>----b.
i>.f>-
ASCII INPUT
LQWTRUE
-L....,/
...,~
--i~
-12V
H....J
B-
A-
AHIGHASClitoSelectllcOutput
A lOWSeler.IIIC to ASCII Input
Encoding 'Space' by Gating In on Input
Decoding 'Space' on Output
SPACE MAGNET
r----'
I
I
I
I
I
L
LMl5~~~RAl ..J
8AIl CODE FROM
CONVERTER
lOW TRUE
-:!:-
TYPICAL
BAIL SWITCH
CLOSURE
207
code conversion tables
Table 1. ASCII-7 to Selectric
~".
ts
0
0
b4
b3
I
I
I
0
0
0
b2
1
~
0
0
b1
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
A
1
0
1
1
8
1
1
0
0
1
1
0
1
0
1
1
1
0
E
1
1
1
1
F
0
1
0
2
DLE
NUL
SP
OA
02
62
'2
DC3
32
3A
EaT
DC4
03
S
OB
ENQ
NAK
'3
'B
SYN
ACK
23
2B
BEL
@
P
I
A
Q
3B
33
42
B
R
b
C
S
c
s
4
D
T
d
t
e
U
,v
f
7
G
W
9
I
8
H
X
h
I
9
I
Y
25
J
6A
ESC
+
7A
72
FF
48
72
CR
40
GS
53
-
58
SO
63
50
U5
73
I
78
,
\
7F
:
I
60
I
77
48
m
I
n
-
A
68
51
j
k
7F
M
>
RS
Z
L
w
y
[
K
<
FS
q
2
E
?
N
70
a
1
P
25
a
3
SU8
53
7
F
4A
VT
6
5
5A
LF
1
6
EM
52
1
1
0
%
CAN
HT
1
1
&
ETB
8S
0
0
2A
ETX
1
0
5
DC2
22
1
0
4
IA
STX
1
3
DCI
SOH
C
1
1
1
0
Rowl -
0
0
0
0
DEL
00
0
-
77
58
Table 2. Selectric to ASCII-7
0
RS
T2----
S
R2A
R2
Rt
I I I I
K
Row - -
0
0
0
Tt
0
1
1
I
0
1
0
0
0
.
1
0
1
2
1
0
1
1
1
1
1
0
1
0
1
3
4
5
6
7
~ 0~ ~ W~
a
0
0
0
0
0
0
0
1
1
a
0
1
0
2
0
0
1
1
3
0
1
0
0
4
Q
k
6
0
1
0
1
5
P
e
217
5
0
1
1
0
6
2/E
2
0
1
1
1
7
J
1
0
0
0
8
-
8
W
I
1
0
0
1
9
Y
H
5
I
1
0
1
0
A
1
0
1
1
8
1
1
0
0
C
1
1
0
1
0
P
E
%
0
R
1
1
1
0
E
+
N
@
F
U
V
1
1
1
1
F
J
T
Z
G
X
M
2/D
y
b
w
h
s
9
0
3/0
I
I
4
6/F
6/C
~ ~ ~ j~ ~~ ~~ ~~ ~
~ ~~
~ ~~ ~~~ ~
m
3/D
t
2/C
3/8
Y2'
2/'
Z
c
8
a
7
d
f
v
3
9
m
1
~V# ~:0 ~;0
,
L
0
$
4/F
~ ~ ~ ~ W~ ~ ~~ ~
~ ~ ~ ~ ~ ~# ~ ~
"
Q
K
I
4/9
2/E
6/3
2/C
C
A
%0
F/F
&
#
±[
5/8
ASCII shown thus. Column No.lRow No.
208
ROM Code Converters
MM4230QW/MM5230QW hollerith to EBCDIC code converter
general description
lines to eight line binary encoded form suitable
for use by the ROM.
The MM42300W/MM52300W 2048-bit MOS read
only memory has been. programmed to convert the
12 line Hollerith Code to the 8 line EBCDIC Code.
Three TTL 4-input NAND gates and three TTL
inverters are used to compress the 12 Hollerith
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical application
connection diagram
Dual-tn-Line Package
Hollerith to EBCDIC
4 INPUT NAND GATES AAE
INVERTERS ARE
DM7430TVPES
OM8812 TYPES
Vss
CONTROL
-Io-:
EBCDIC
T UT
:
I - -_ _
2_
lS6
3-
A,-3
22r-- NC
PUNCHED
CARD
DATA
INPUT
,---------------"'1"
A5
'1--
--------"1::"
PUNZC~ ; {
lINES1T07
":"
a
l1r- Ae
'I-15 r 8 8 -11
~g~iROl
14r-~~~BlE
VSS -L,..12_ _ _ _ _'...J3~A9
"f--.......-+-I--I
:j:·=:::r
-=-
-
16r-VGG
::-'-0"-'___________---"'1" ::
1 Vss '.,20V 11)%,V Do 'GNO,V GG
85
-120V 1(1'%
lINESBTOl2
code conversion table
Hollerith to EBCDIC
12
12
12
11
11
o
o
12
11
0
12
12
11
12
11
o
12
11
0
11
8-1
SP
I
:
I
70
49
59
69
80
90
AD
BO
1
A
J
I
1
a
j
-
Bl
SOH
DCl
21
31
41
51
El
71
9
-1
2
B
K
S
2
b
k
s
B2
STX
DC2
22
SYN
42
52
62
72
9
-2
3
C
L
T
3
cit
B3
ETX
DC3
23
33
43
53
63
73
9
-3
4D
M
U4dmu
B4
04
14
24
34
44
54
64
74
9
-4
5E
N
V5
B5
HT
15
LF
35
45
55
65
75
9
-5
6F
0
W6fowB6
06
BS
ETB
36
46
56
66
76
9
-6
7.G
P
X
B7
DEL
17
ESC
EOT
47
57
67
77
9
-7
8H
G
Y8hqy
58
-8
9
I
R
Z
I
I
\
1>
8-2
11
0
7
8-5
I
I
8-6
+
;
8-7
! CD
- Q)
p
B8
08
CAN
28
38
48
68
78
9
r
z
B~
09
EM
29
39
NUL DLE
20
30
9-8-1
8A
9A
AA
BA
OA
lA
2A
3A
CA
DA
EA
FA
9-8-2
8B
9B
AB
BB
VT
lB
2B
3B
CB
DB
EB
FB
9-8-3
%@8C9CACBC
FF
FS
2C
DC4
CC
DC
EC
FC
9-8-4
9
it
<
9
I
8-3
8-4
e
8D
9D
AD
BD
CR
GS
ENG
NAK
CD
DD
ED
FD
9-8-5
>
8E
9E
AE
BE
so
RS
ACK
3E
CE
DE
EE
FE
9-8-6
"?
8F
9F
AF
BF
51
US
BEL
SUB
CF
DF
EF
FF
9-8-7
<
o
o
ROM Code Converters
M
N
Ln
:E
:E
.........
><
o
o
M
N
~
MM4230QX/MM5230QX
:E
:E
EBCDIC-8 -to-ASCII-8 code converter
general description
The MM42300X/MM52300X is a 2048-bit read
only memory that has been programmed to convert Extended Binary Coded Decimal Interchange
Code (EBCDIC) to the American Standard Code
for I nformation I nterchange extended to eight bits
(ASCII-8).
The conversion conforms to the practice estab-
lished by the American National Standard ANSlx
3.26-1970. Exact details are shown in the code
table.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 2048-bit read
only memory data sheet.
typical application
connection diagram
-12V-----------------4~................
INPUT Al
14
INPUT A,
13
NC
INPUT Al
11
NC
+5V-,--. .--------------+--+--+---4I~-A.
6,8K,
TYPICAL,
8 LINES
GATES OM7400
LSB
8,
Voo
OUTPUTS 1
11
INPUT A-1
OUTPUT B.,
10
INPUT Ac
OUTPUT B!
19
INPUT AI,
OUTPUT B.\
IB
INPUT A,
E,
8,
E,
8,
E,
8,
MM4230QX
MM5230QX
E,
B.
E.
J>
OUTPUT B"
.;,
OUTPUTB"
OUTPUTS,
INPUT AI;
10
16
Vt • l •
15
MOOE
CONTROL
CHIP
ENABLE
OUTPUT BII
8.
E.
V~:-.
B,
E,
10
MSB
+12V----~._....~....~
·CHIP ENABLE
"
B.
-+---....
----..I
MOOE CONTROL . . .
La.ielev,ls
OTLITTL (except at MOS/ROM interfacel
Logic"1",+5V. nom. Logic"O", ground. nom.
MaS/ROM Inputs & Output
Logic"l",morenegatjye.logic"O",morepositive
210
·Chlp Enable'" logic "1" to obtain outputs
E.
OTLITTL LOGIC
13
TOP VIEW
INPUT A,
s:
s:
code conversion table
~
w
o
0---0
0
0
1---0
, , , ,~
4
5
6
7
0
0
0
0
0
0
0
1
0
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
5
1
0
A
1
0
1
1
B
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
C
0
E
F
11
DC2
02
ETX
12
DC3
13
03
9C
90
HT
0
90
81
97
80
8E
VT
08
FF
19
CA
01
08
I
A9
BB
Al
AA
B2
BC
84
94
A3
AC
B4
BE
17
95
A4
96
A5
EOT
88
A6
04
98
A7
a
AD
B5
AE
B6
AF
B7
80
B8
BF
CO
Cl
C2
89
99
A8
8B
9B
lC
10
06
IF
24
2C
61
62
I
c
23
25
40
-
28
+
)29
5F
>
28
I
1A
3A
t
63
u
v
n
65
f
w
0
x
P
78
70
Y
Q
79
71
66
r
69
77
6F
67
I
76
6E
66
h
75
60
64
e
74
6C
m
d
73
6B
Z
72
7A
; 3B
3E
21
..
3D
3F
5E
22
DA
DB
DC
DO
DE
OF
EO
El
I
J
A
4A
41
K
B
47
37
58
8
38
59
51
9
Z
52
36
7
Y
R
49
6
57
50
48
I
35
56
X
0
H
5
4F
P
34
55
V
W
46
33
4
U
0
G
3
4E
45
F
32
54
40
N
E
31
53
T
44
1
2
4C
M
0
9F
S
L
43
30
5C
4B
42
C
0
\
70
7B
5A
0
1
W
2
o
F
39
6
7
8
9
E8
EE
F4
FA
A
C5
CC
03
E3
E9
EF
F5
FB
B
C6
CD
D4
E4
EA
FO
F6
FC
C
C7
CE
05
E5
EB
Fl
F7
FD
0
C8
CF
06
E6
EC
F2
F8
FE
E
DO
07
E7
ED
F3
F9
FF
X
5
E2
C9
o
4
02
EO
N
3
CB
=
>
1\
27
D9
I
s:
s:
c.n
1
0
E
0
C
C4
@
%
I
9E
60
s
k
b
7E
6A
it
2A
3C
15
SUB
07
7C
<
14
BEL
50
$
05
IE
89
:
2E
NAK
ACK
US
5B
OC4
8C
ENO
81
I
I
-
j
2F
BD
8F
RS
OF
C3
B3
9A
OE
BA
20
AB
8A
FS
SI
B
A2
92
00
A
I
GS
SO
9
93
lB
18
OC
CR
16
8
.........
1
1
1
0
1
0
1
0
7
83
A
EM
26
AO
1
0
6
&
20
SYN
82
1
X
1
1
0
0
1
o
1
1
1
1
0
1
0
1
1
1
0
0
0
1
1
5
SP
91
ESC
87
0
0
1
1
0
4
80
ETB
CAN
1
1
1
1
0
0
0
1
3
08
7F
1
2
OA
BS
86
DEL
0
1
LF
85
09
9
0
OCI
STX
8
1
10
01
6
7
OLE
00
SOH
0
1
1
NUL
0
1
0
0
Rowt
0
0
2---0
3---0
0
F
G)
I ",,-
Ii - - - - - ,
IjE
I
L
45,
____
Location
In
C5
Hexadecimal EBCDIC
Character Address
"- "
:~0
I
ASCII-8 IROM Cont)
Character Assignment
III Any)
211
ROM Code Converters
MM4230QY /MM5230QY
ASCII-8 -to- EBCDIC-8 code converter
general description
The MM42300Y /MM52300Y is a 2048-bit read
only memory that has been programmed to convert the American Standard Code for Information
Interchange extended to eight bits, (ASCII-8) to
Extended Binary Coded Decimal Interchange Code
(EBCDIC-8). The conversion conforms to the practice establ ished by the American National Standard
ANSlx3.26 1970. Exact details are shown in the
code table.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 2048-bit read
only memory data sheet.
connection diagram
typical application
-12V
INPUT AJ
24
INPUT A]
23
NC
INPUT Al
22
NC
OUTPUTS]
20
INPUT A5
OUTPUT Bj
19
INPUT AG
OUTPUTB 4
18
Voe
'5V
A.
LS8
VGG
E,
16
6.8K,
TYPICAL,
8 LINES
GATES DM74DO
OUTPUT 8 1
8,
INPUT A4
E,
8,
EJ
8,
0
0
INPUT As
OUTPUTS,
>-
::>
z
8,
MM423DOY/
MM52300Y
E.
OUTPUTSI>
16
0
8
E.
;:;
8.
3
CHIP
ENASLE
OUTPUTS,
Vss
8,
E,
10
+12V
11
OTL/TTL LOGIC
·CHIP ENA8LE
MODE CONTROL
-f---...1
+ ____...1
LOIK:Leveis
OTLITTL (except.t MOS/ROM ,.tert,ce)
logic "1",+5V. nom. Logic"O",ground,nom.
MOS/ROM Inputs & Output
logic "1", more negative. Logic"O",morepositlYe
212
·Chip Enable
= Logic "1" to obtain outputs
12
L.-_
_ _ _ _t3
.....
TOP VIEW
S,
VGG
MOOE
CONTROL
OUTPUTS]
8.
E,
MS8
INPUT A]
E,
INPUT A.
s:
s:
code conversion table
~
N
W
o
0
b7-0
~
~
~ ~ ~
ROW+-
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
A
1
0
1
1
B
1
1
0
0
C
1
1
0
1
D
1
1
1
0
E
1
1
1
1
0
F
NUL
SP
10
SOH
DCl
STX
12
DC3
ECT
3C
ENQ
NAK
ACK
SVN
F5
6C
6
&
32
2E
7
26
2F
(
CAN
BS
18
16
EM
HT
05
IF
G
)
19
50
F9
3F
5C
7A
VT
J
+
ESC
DB
27
4E
DC
lC
6B
<
CR
-
GS
00
10
60
lE
4B
DE
SI
US
OF
I
lF
0
?
61
6F
1 may be "1"
2 may be " - , "
3 The top line in each entry to the table represents an
assigned character (Columns 0 to 71. The bottom
line in each entry is the corresponding EBCDIC Code,
in hexadecimal notation.
DO
95
A1
DEL
0
60
6A
I
n
5F
-
06
:
94
5A
05
CO
93
m
/\0
N
6E
I
I
J
A9
92
EO
04
7E
>
RS
SO
4A
03
M
91
k
\
l
4C
A8
z
j
I
A7
Y
89
E9
02
5E
88
I
Z
A6
x
h
E8
01
K
FS
FF
C9
w
87
E7
V
I
9
A5
86
g
X
A4
v
f
E6
C8
F8
SUB
25
C7
H
8
40
85
E5
W
A3
u
e
V
A2
t
E4
C6
F7
70
U
F
s
84
E3
C5
F6
50
ETB
BEL
E
5
%
3D
20
99
83
d
C4
98
r
c
T
0
F4
q
82
E2
C3
97
81
b
S
C
4
5B
a
09
C2
p
79
08
R
B
F3
7B
$
DC4
37
Cl
F2
3
#
Q
A
2
\
96
1
1
1
0
1
F
~
B8
DC
0
AO
B9
DO
1
78
AA
BA
DE
2
63
80
AB
BB
OF
3
45
64
8A
AC
BC
EA
4
35
46
65
8B
AD
BD
EB
5
06
36
47
66
BC
AE
BE
EC
6
17
08
48
67
80
AF
BF
ED
7
28
38
49
68
8E
BO
CA
EE
8
29
39
51
69
8F
B1
CB
EF
9
2A
3A
52
70
90
B2
CC
FA
10
2B
3B
53
71
9A
B3
CD
FB
11
2C
04
54
72
9B
B4
CE
FC
12
09
14
55
73
9C
B5
CF
FD
13
OA
3E
56
74
90
B6
DA
FE
14
C
0
58
76
9F
42
59
77
lA
43
62
23
33
44
24
34
15
9
A
B
20
30
41
21
31
22
E1
57
75
9E
B7
s:
s:
U'1
1
1
1
0
~
........
1
1
0
0
1
0
8
lB
07
1
1
1
0
0
0
0
7
S
07
7C
Fl
7F
13
03
1
5
P
@
o FO
4F
"
DC2
02
ETX
!CD
11
01
0
40
4
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
3
0
0
0
1
2
OLE
00
1
0
1
0
1
1
1
bS-O
0
0
0
0
bS-O
b4 b3 b2 b1
0
0
0
bS-O
E
DB
N
W
tRow
EO
o
o
-<
15
FF
The Irtexadecimal EBCDIC entry is formed thus:
Eight EBCDIC bits
MSB
o
1 2 3
4 56 7
1st Digit
2nd Digit
Example: 0 1 0 1
5
1 100
LSB
or *
C
To convert ASCII-8 asterisk (*j to EBCDIC-8
E8
El
* in ASCII is a 2A or binary 0010 1010
applying this as an.address to the MM5230QV/MM4230QV
bit-O bit-7
gives the output 0101 1100, which is an EBCDIC-S asterisk.
213
ROM Code Converters
MM4230RS/MM5230RS binary to
modulo-n divider code converter
general description
Applying the required division ratio, in binary, to
the inputs of the ROM as shown, generates two
sets of four program inputs, one for each of the
2 DM7520/DM8520 dividers.
The MM4230RS/MM5230RS binary to modulo-n
divider code converter is set up to generate the
program input settings for a pair of DM7520/
DM8520 modulo-n dividers, in order to divide by
any binary number from one to 255. Detailed
instructions for use of the DM7520/DM8520 are
given in its data sheet.
For electrical, environmental and mechanioal details, refer to the MM4230/MM5230 data sheet.
connection diagram
Dual-In-Line Package
INPUTAl
24~VDO
1
-
INPUTA 2 - 2
231--NC
INPUTA,-3
22-NC
OUTPUTB I - 4
21-INPUTA 4
OUTPUTB 2 - 5
20_INPUTA s
OUTPUTB 3 - 6
'9f--INPUTA s
OUTPUTB 4 - 7
18~INPUTA7
OUTPUTB s - 8
17_INPUTAa
OUTPUTB 6 - 9
16-V GG
OUTPUTB 7 - 1 0
15 -~g~iROl
14_~~~BlE
OUTPUTS e _ l 1
lJ~INPUTA9
Vss -12
TOP VIEW
typical application
Binary to Modulo-n Divider
CONNECT
DIRECT TO
OM1520fOMB520
Msa
BINARY
DIVISOR
,'<>,"
i>
V"
A.
A,
0,
"
"
0,
~
0,
A,
MMS230RS
0,
A,
0,
A,
0,
A,
214
INPUTS
0.
A,
"~
HIGH
MODE
CONTROL
"<>-1>
A,
TRUE
PROGRAM
L
l,
OMBBIO
4_n.
CHIP
0,
T
l/'>---o P,
~:_---et_6.8_K*--e----4I---+--+---1~-J 6SK ...
code conversion table
-;- BY
SETTING
I
DIVIDER 1
B8
B7
B6
B5
a
1
1
1
1
a
1
1
1
1
a
a
1
a
a
1
0'
a
a
a
a
a
a
1
1
1
a
1
1
a
a
a
a
a
a
1
a
a
1
1
a
1
0'
a
a
a
a
1
1
a
a
a
a
a
a
a
a
a
a
a
1
1
1
a
1
1
a
a
a
a
a
a
1
a
a
1
1
a
1
a
a
a
a
a
1
1
1
1
a
1
0'
0'
1
0'
0'
0'
0'
a
a
a
0'
0'
a
a
a
a
a
a
1
a
0'
1
1
a
1
a
a
1
1
1
0'
1
1
a
a
a
0'
a
a
1
0
a
1
1
a
a
a
a
a
a
a
a
a
a
1
a
1
a
1
a
1
1
1
1
a
a
1
a
a
a
1
1
1
a
a
a
1
a
1
1
0'
0'
1
0'
a
1
0'
0'
1
1
1
a
1
a
1
1
1
a
a
a
1
a
a
a
1
1
1
a
1
1
a
a
a
a
a
a
1
a
a
1
1
a
1
a
a
a
a
a
1
1
1
a
1
1
1
a
a
1
1
1
1
a
a
a
a
a
a
1
1
1
a
1
1
a
a
a
a
a
a
1
a
a
1
1
a
1
a
1
1
1
0'
1
a
0'
0'
a
1
a
a
1
1
1
1
a
0'
0'
1
1
1
1
1
a
a
0'
1
0'
0'
a
a
a
0'
0'
1
1
1
1
1
1
a
a
a
1
0'
1
a
a
a
1
a
1
1
1
a
a
a
1
0'
a
1
a
a
1
1
1
1
a
1
1
1
0'
a
a
0'
0'
1
0'
0'
1
1
1
0'
1
1
1
a
a
a
a
1
0'
0'
1
0'
0'
0'
1
1
1
0'
0'
1
a
a
a
1
a
a
0'
1
a
a
1
1
1
0'
1
0'
1
1
0'
1
1
1
1
1
a
a
1
a
a
0'
0'
1
a
a
1
a
a
1
1
a
a
a
a
1
1
0'
1
1
0'
1
1
1
1
1
1
1
a
1
a
a
a
a
1
1
1
a
1
1
0'
1
1
,.
a
a
1
a
a
1
0'
a
1
1
a
a
a
1
1
a
1
a
a
1
1
1
1
1
1
1
1
1
a
1
1
a
1
1
1
a
0'
1
1
1
a
a
a
a
a
1
1
a
1
0'
1
1
1
0'
1
0'
0'
1
1
1
a
1
1
a
a
1
1
a
1
a
a
a
a
a
1
1
a
1
0'
1
1
a 1
a a
a a
a a
1
a
0'
1
1
1
1
0'
0'
1
a
a
a
1
1
1
0'
a
a
1
a
1
a
1
1
1
1
0'
a
1
a
a
a
1
1
1
a
a
a
1
1
1
a
1
0'
1
1
a
a a
a 1
a a
1
a
a 1
a a
1
a
1
1
1
a
1
1
0'
a
1
0'
a 1
a a
a a
a a
a a
a a
1
a
a
a
a
a
a
a
a
a a
a a
a a
a 0'
a
0'
1
a
a
a
1
0'
0'
a
a
a
1
1
1
1
1
1
1
0'
1
a
a
a
0'
0'
0'
0'
1
1
1
0'
1
1
1
a
a
a
a
1
a
a
a
0'
0'
a
1
1
1
1
1
1
1
0'
0'
1
a
B,
1
1
1
1
1
1
a
1
1
1
1
1
B2
1
1
1
1
1
0'
1
0'
a
a
B3
1
1
1
1
0'
1
0'
a
a
1
1
1
1
I B4
1
1
1
0'
1
255
254
253
252
251
250'
249
248
247
246
245
244
243
242
241
240'
239
238
237
236
235
234
233
232
231
230'
229
228
227
226
225
224
223
222
221
220'
219
218
217
216
215
214
213
212
211
210
20'9
20'8
20'7
20'6
20'5
20'4
20'3
20'2
20'1
20'0'
199
198
197
196
195
194
193
192
191
190'
189
188
187
186
185
184
183
182
181
180'
179
178
177
176
175
174
173
172
171
170'
169
168
167
166
-;-BY
SETTING
I
DIVIDER 1
DIVIDER 2
B8
B7
B6
B5
I B4
B3
B2
B,
1
a
1
1
a
1
a
1
1
1
1
1
1
1
0'
1
a
a
a
1
1
1
1
a
1
a
a
1
1
1
1
a
1
a
1
0'
0'
1
1
1
1
a
0'
1
1
1
1
a
1
0'
1
1
a
1
1
a
1
a
0'
1
1
1
1
0'
1
1
1
0'
1
0'
0'
1
1
0'
1
1
1
0'
1
0'
a
1
0'
a
0'
1
1
a
1
1
a
a
1
1
1
a
a
1
a
1
1
a
a
1
1
a
1
1
a
a
1
1
1
a
a
1
a
1
1
1
a
1
a
a
a
0'
1
a
1
1
1
a
1
1
1
1
1
a
1
1
1
a
a
1
1
0'
a
a
a
1
1
a
a
1
0'
1
0'
1
0'
a
a
1
a
1
0'
1
1
1
1
1
1
0'
a
1
1
a
a
1
1
a
1
1
a
a
1
1
1
a
a
1
a
1
1
1
a
1
a
a
a
1
1
a
1
1
1
0'
1
1
1
1
1
0'
1
1
1
0'
0'
1
1
0'
0'
0'
0'
1
1
a
a
1
a
1
0'
1
0'
a
0'
1
0'
1
0'
1
1
1
1
1
1
0'
0'
1
1
a
a
1
a
1
1
1
0'
1
1
1
1
1
a
1
1
1
a
a
1
1
a
a
q
0'
1
1
0'
0'
1
0'
1
a
1
a
a
0'
1
0'
1
a
1
1
1
1
1
1
a
a
1
1
a
1
1
1
a
1
a
a
a
1
1
a
1
1
a
a
1
1
1
a
a
1
a
1
1
1
a
a
1
1
1
a
a
a
a
1
1
1
1
0'
1
1
1
1
1
0'
1
a
a
a
a
1
0'
0'
1
1
0'
1
1
a
a
1
1
1
a
a
1
a
1
1
1
a
a
1
1
a
1
1
0'
a
1
1
1
a
a
1
1
1
0'
1
a
a
a
1
0'
0'
165
164
163
162
161
160'
159
158
157
156
1
1
1
1
0'
1
1
0'
1
1
155
154
153
152
151
150'
149
148
147
146
1
0
1
145
144
143
142
141
140'
139
138
137
136
1
1
1
1
a
1
1
a
1
1
1
a
1
a
a
a
1
1
1
0'
a
1
1
1
a
1
1
a
1
a
1
1
a
a
1
0'
1
1
1
a
1
1
1
1
1
a
1
1
1
a
a
1
1
a
a
0'
a
1
1
a
a
1
a
1
0'
1
0'
0'
0
1
a
1
a
1
1
1
1
1
1
0'
a
1
1
a
1
a
a
a
a
a
1
1
a
a
1
1
a
a
a
a
1
1
1
1
1
0'
1
1
01
0'
1
a
1
1
a
a
1
0'
a
1
1
1
a
a
1
1
1
a
1
a
1
a
a
a
0
1
1
1
a
a
1
1
1
a
1
1
a
1
a
a
1
0'
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
0'
a
1
1
1
a
a
1
1
0'
0'
1
1
a
a
a
1
1
a
a
1
0'
1
a
a
a
a
a
1
1
1
1
1
1
1
1
a
0'
1
1
1
1
1
a
a
1
1
0'
0'
1
1
1
0'
0'
1
a
a
a
1
a
1
a
1
a
1
a
1
1
1
1
1
1
0'
1
a
1
a
a
a
a
a
a
a
a
1
1
1
1
1
a
a
a
1
a
a
a
a
1
1
a
1
a
1
1
1
1
1
1
1
a
a
1
1
a
1
a
a
a
a
1
0'
1
a
1
1
1
1
1
1
a
a
a
1
a
1
a
1
1
a
135
134
133
132
131
130'
129
128
127
126
125
124
123
122
121
120'
119
118
117
116
115
114
113
112
111
110'
10'9
10'8
10'7
106
10'5
104
10'3
10'2
10'1
laO'
99
98
97
96
95
94
93
92
91
90'
89
88
87
86
-;-BY
SETTING
DIVIDER 1
DIVIDER 2
B8
B7
B6
B5
1
1
1
1
1
1
1
0'
1
1
1
1
1
0'
a
a
a
a
a
a
1
a
1
a
a
a
a
1
a
a
a
a
1
1
1
1
a
a
a
1
1
a
a
a
1
a
a
a
a
a
a
a
a
0'
1
a
0'
1
a
a
a
a
1
0'
0'
a
a
1
1
1
1
a
0'
a
1
1
a
0'
a
1
a
a
a
0'
1
0'
1
a
a
0'
0'
1
0'
a
a
a
1
1
1
1
1
0'
a
0'
1
a
1
a
a
a
a
1
1
a
a
1
1
a
1
1
1
1
a
1
0'
1
0'
1
0'
1
1
0'
0'
0'
1
1
1
1
1
1
1
1
a
a
1
1
a
a
1
1
0'
1
1
1
1
0'
1
0'
1
a
1
a
1
1
a
a
a
1
a
a
0'
a
1
a
a
a
a
1
1
1
1
0'
0'
1
a
0'
1
a
a
a
1
0'
1
1
a
a
a
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
a
1
1
a
a
a
1
a
a
a
1
a
a
1
I
I B4
a
a
1
1
1
1
1
a
0'
0'
a
0'
1
a
1
a
1
1
1
1
a
a
0'
1
1
a
a
a
a
a
1
0'
0'
0'
1
1
0'
1
1
1
1
0'
1
0'
1
a
a
1
1
0'
1
a
0'
1
1
a
1
1
0'
0'
1
0'
1
1
1
1
1
1
1
1
1
1
1
1
a
a
1
a
1
0'
0'
1
1
1
1
a
a
0'
1
1
1
0'
1
1
0'
1
1
1
1
0'
1
1
a
a
a
a
a
a
a
a
1
1
a
0'
0'
a
1
1
1
0'
a
0'
1
1
1
1
1
0'
a
a
a
1
0'
1
0'
0'
1
1
1
1
1
1
1
1
1
1
1
0'
1
1
1
0'
0'
1
1
1
1
1
a
a
a
a
a
a
a
B,
1
1
a
a
a
a
a
a
a
B2
1
1
0'
a
a
1
1
B3
1
0'
0'
0'
0'
0'
1
1
a
DIVIDER 2
1
a
1
a
1
0'
1
1
0'
a
a
1
1
1
a
0'
a
a
1
a
1
0'
0'
a
0'
1
a
0'
a
a
1
1
1
1
a
0'
a
1
1
1
a
a
a
1
a
a
a
a
a
1
a
1
a
a
1
1
a
a
1
1
a
1
1
1
1
0'
1
0'
1
0'
1
a
1
1
a
0'
0'
1
1
1
1
a
a
1
0'
1
0'
a
0'
a
1
0'
1
a
a
a
a
1
0'
0'
a
a
1
1
1
1
0'
a
a
1
1
a
a
a
1
a
a
a
1
0'
0'
1
0'
1
a
a a
1
1
a
0'
1
1
0'
1
1
a
a
0'
1
1
1
1
1
1"
1
1
a
1
1
75
74
73
72
71
70'
69
68
67
66
65
64
63
62
61
60'
59
58
57
56
55
54
53
52
51
50'
49
48
47
46
45
44
43
42
41
40'
39
38
37
36
35
34
33
32
31
30'
29
28
27
26
25
24
23
22
21
20'
19
18
17
16
1
a
1
a
1
0'
1
1
1
0'
1
0'
1
15
14
13
12
11
10'
9
8
7
6
1
0'
0'
0'
5
4
3
2
a
a
a
a
a
a
1
1
85
84
83
82
81
80'
79
78
77
76
215
0..
a:
po
ROM Code Converters
M
N
in
~
~
.........
0..
a:
~
MM4231RP/MM5231RP EBCDIC to ASCII-7 code converter
M
N
~
~
~
general description
The MM4231RP/MM5231RP is a 2048-bit readonly memory that has been programmed to convert from EBCDIC, "n extended binary coded
decimal interchange code used in the IBM 1130
computer, to ASCII-7, the American Standard
Code for I nformation I nterchange in seven· bits.
This conversion differs from the ANSI x 3.26
conversion of the MM4230QX/MM5230QX in that
it follows certain earl ier IBM 1130 character assignments. Also certain EBCDIC control codes are
arbitrarily preserved and translated (see translation chart on truth table).
For electrical, environmental and mechanical details, refer to the MM4231/MM5231 data sheet.
typical application
EBCDIC TO ASCII-7
+5V
EBCDIC
LOW TRUE
BIT
MSB
0
ASCII
HIGH TRUE
12,15
17
As
B8
B7
11
HIGH = Graphic
LOW= Control
10
b7
Bs
Ils
lis
bs
B,
b,
B3
b3
A2
B2
b2
A,
B,
MM5231RP
Ao
LSB
b,
DM7404
16,24,13
-12V
216
6.8K
6.8K
6.8K
6.8K
6.8K
code conve rsion tables
ASCII
ASCII
SYMBOL
SYMBOL
o
0
0
o
0
0
;
0
1
1
1
1
1
so
-*-----£E-~
CONTINUING BINARY
SEQUENCE
CONTINUING BINARY
SEQUENCE
1-;
0
1
1
1
1
I
52
PN
-T.-~--~
=+.=
I
I
I
I
[I"!~~ . ,'" ". +-,., . ,.: 6~liB'6.f 3~~B3EB2EB~'
a.
B B
~8 I A7 I A6 I AS I A.t I A3 I A2 I
A:
~"--+=-B'+-"+-B-.4-B-t,-B---j3I-B
-2!--B,--1
ROM
ADDRESS
CONTINUING BINARY
SEQUENCE
:
~, I " I'. I" I.. 1'3 I '2
I .;
B,
~
:
~
:
:
B, B. B. B, '3 B2 B,
217
«
«
co
ROM Code Converters
co
~
I'
~
C
""
«
«
co
DM5488/DM7488 (SN5488/SN7488)
co
~
an
256-bit read-only memory
~
C
general description
The DM5488/DM7488 is a custom-programmed
256-bit read-only memory organized as 32 8-bit
words. A 5-bit input code selects the appropriate
word which then appears on the eight outputs.
An enable input overrides the address inputs and
turns off all eight output transistors.
•
Open collector outputs provide expansion to
greater numbers of words
•
On-chip decoding
•
30 ns typical access time
features
•
250 mW typical power dissipation
•
•
I nput clamp diodes
Organized as 32 8-bit words
connection diagram
BINARY SELECT
typical application
BINARY
C
SELECT
VB
YL
Y6
OUTPUTS
218
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
(Note 1)
~
00
00
7V
5.5V
5.5V
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
DM5488
DM7488
Storage Tern peratu re Range
Lead Temperature (Soldering, 10 sec)
.-
electrical characteristics
s:
C1I
»
»
c
s:
-...J
..........
~
00
00
»
(Note 2)
PARAMETER
»
CONDITIONS
MIN
TYP
MAX
UNITS
Logical" 1" I nput Voltage
DM5488
DM7488
Vee
Vee
= 4.5V
= 4.75V
Logical "0" I nput Voltage
DM5488
DM7488
Vee
Vee
= 4.5V
= 4.75V
Logical "1" Output Current
DM5488
DM7488
Vee
Vee
= 5.5V
= 5.25V
Va
Logical "0" Output Voltage
DM5488
DM7488
Vee
Vee
= 4.5V
= 4.75V
10 = 12 mA
Logical "1" I nput Current
DM5488
DM7488
Vee
Vee
= 5.5V
= 5.25V
VI
= 2.4V
40
IlA
DM5488
DM7488
Vee
Vee
= 5.5V
= 5.25V
VI = 5.5V
1
rnA
Logical "0" I nput Current
DM5488
DM7488
Vee
Vee
= 5.5V
= 5.25V
VI = O.4V
-1.6
rnA
Supply Current
DM5488
DM7488
Vee
Vee
= 5.5V
= 5.25V
80
rnA
Input Clamp Voltage
DM5488
DM7488
Vee
Vee
=
= 4.5V
4.75V
V
2.0
0.8
100
40
= 5.5V
0.4
50
II
= -12 rnA
V
IlA
Il A
V
-1.5
V
Propagation Delay to a Logical "0" from
Address to Output, tpdO .
Vee = 5.0V
T A = 25°C
C L = 15 pF
32
50
ns
Propagation Delay to a Logical "0" from
Enable to Output, tpdO
Vee = 5.0V
T A = 25°C
CL
=:
15 pF
34
50
ns
Propagation Delay to a Logical "1" from
Address to Output, tpdl
Vee = 5.0V
T A == 25°C
CL
= 15 pF
28
50
ns
Propagation Delay to a Logical "1" from
Enable to Output, tpdl
Vee = 5.0V
T A = 25°C
CL
= 15 pF
27
50
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature
range for the DM5488 and across the O°C to 70°C range for the DM7488. All typicals are given for
VCC = 5.0V and T A = 25°C.
219
truth tables
DM5488A/DM7488A SINE LOOK-UP TABLE
A pattern has been generated for the DM5488/DM7488. The AA pattern provides a sine table. The 5-bit input
code linearly divides 90° into 32 equal segments. Each 8-bit output is therefore the sine of the angle applied.
EXAMPLE: Input 11010 means 26/32 of 90°, or about 73°. The corresponding output 11110100 indicates
(.1/2+ 1/4+ 1/8+ 1/16+ 1/64) or about .95, which is close to the sine of 73°. Rounding-off has not been
employed, since without rounding-off it is possible to extend the accuracy with additional ROMs.
INPUTS
WORD
X
OUTPUTS
BINARY SELECT
ENABLE
E
D
C
B
A
G
Y8
Y7
Y5
Y4
Y3
Y2
Y1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
2
0
0
0
1
0
0
0
0
0
1
1
0
0
1
3
0
0
0
1
1
0
0
0
1
0
0
1
0
1
4
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
Y6
5
0
0
1
0
1
0
0
0
1
1
1
1
1
6
0
0
1
1
0
0
0
1
0
0
1
0
1
0
7
1
0
0
0
1
1
1
0
0
1
0
1
0
1
8
0
1
0
0
0
0
0
1
1
0
0
0
0
9
0
1
0
0
1
0
0
1
1
0
1
1
0
1
10
0
1
0
1
0
0
0
1
1
1
1
0
0
0
11
0
1
0
1
1
0
1
0
0
0
0
0
1
1
12
0
1
1
0
1
1
0
0
0
1
1
1
13
0
1
1
0
1
0
1
0
0
1
1
0
0
0
14
0
1
1
1
0
0
1
0
1
0
0
0
1
0
15
0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
0
16
1
0
0
0
0
0
1
0
1
1
0
1
0
1
17
1
0
0
0
1
0
1
0
1
1
1
1
0
1
18
1
0
0
1
0
0
1
1
0
0
0
1
0
1
19
1
0
0
1
1
0
1
1
0
0
1
1
0
1
20
1
0
1
0
0
0
1
1
0
1
0
1
0
0
21
1
0
1
0
1
0
1
1
0
1
1
0
1
22
1
0
1
1
0
0
1
1
1
0
0
0
0
1
23
1
0
1
1
1
0
·1
1
1
0
0
1
1
1
24
1
1
0
0
1
1
0
0
0
0
1
1
1
1
25
1
1
0
0
1
0
1
1
1
1
0
0
0
1
26
1
1
0
1
0
0
1
1
1
1
0
1
0
0
27
1
1
0
1
1
0
1
1
1
1
1
0
0
0
0
28
1
1
1
0
0
0
1
1
1
1
1
0
1
29
1
1
1
0
1
0
1
1
1
1
1
1
0
1
30
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
31
1
1
1
1
1
0
1
1
1
1
1
1
1
1
All
X
X
X
X
X
1
1
1
1
1
1
1
1
1
Don't Care
DM5488/DM7488 TRUTH TABLE
The output levels are not shown on the truth table since the customer specifies the output condition he desires
at each of the eight outputs for each of the 32 words (256 bits). The customer does this by filling out the truth
table on this data sheet, and sending it in with his purchase order.
INPUTS
WORD
BINARY SELECT
OUTPUTS
ENABLE
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
10
12
15
16
18
19
20
21
23
24
25
26
27
28
29
30
31
X
=:
Don't Care
Notice Thl'> sheet must be completed and signed by an authOrlLed representative of the customer's company before an order can be entered
Authorlze~
To be used by National only
_ _ _ _ _ _ _ Part Number
_
~
_ _ _ _ _ SO Number
_ _ _ _ _ _ _ Date Received
220
Representatlve· _ _ _ _ _ _ _ _ _ Date _ _ _ __
Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o
o
DM5488
DM7488
c
s:
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Logical "0" Output Voltage vs
Sink Current
Delay from Address to
Output vs Temperature
Delay from Enable to
Output vs Temperature
I
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re)
4
8
TEMPERATURE (Oe)
ac test c i rcu it
12
16
20
24
28
lOUT (rnA)
switching time waveforms
INPUT PULSES
t,..:10ns
tf"10ns
f= 1 MHz
- - + - - -......
- - - -t- - -
ADDRESS
~
INPUTS _ _ _ _ ..2..5V.JI~
390
_ _ _+-__
OM5488/~
'I----...... fcc
OM7488
r--=
15pf
OUTPUTS
1.5V \ ' - -_ _--J" 1.5V
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221
ROM Code Converters
DM7598AA/DM8598AA TRI-STATETM
sine table look-up read only memory
general description
state allows many outputs to be connected in
parallel for expansion to greater numbers of words
and/or connection to a common bus line.
The DM7598AA/DM8598AA is a 256-bit bipolar
read-only memory organized as 32 8-bit words.
The 5-bit input code linearly divides 90° into 32
equal segments. Each 8-bit output is therefore the
sine of the angle applies.
features
EXAMPLE: Input 11010 means 26/32 of 90°, or
about 73°. The corresponding output 11110100
indicates (1/2 + 1/4 + 1/8 + 1/16 + 1/64) or about
.95, which is close to the sine of 73°. Roundingoff has not been employed, since without rounding-off It is possible to extend the accuracy with
additional ROM's.
•
The DM8598 is identical to the SN7488 except
that the Enable input on the SN7488 simply places
all outputs in the logical "·1" state, whereas the
Enable input on the DM8598 places the outputs
in a high impedance state. This high impedance
Organized as 32 8-bit words
•
Party line capability
•
On-chip decoding
•
Pin compatible with SN7488
•
Typical access time 30 ns
•
Total power dissipation 350 mW
•
Compatible with Series 74 TTL and 930 DTL
•
•
Strobe input
I nput clamp diodes
connection diagram
Dual-In-Line Package
15
14
12
13
11
10
A
G
G
/
ENABLE
r-- V1 OUTPUT
VB OUTPUT
OUTPUTS
,
V2
V4
V3
V5
OUTPUTS
ENABLE
BINARV SELECT
o
I--
NORMAL
Hi-Z
,
V6
V7
TOP VIEW
typical system connection
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OUTPUTS
Word
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
All
Binary Select
Enable
E
0
C
B
A
G
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
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0
1
0
1
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0
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1
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0
0
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1
1
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1
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0
0
0
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0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
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1
1
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1
1
1
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0
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0
1
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1
0
1
0
0
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1 0
1' 1
1
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1
1
1
1
1
1
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1
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0
0
1
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1
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0
0
0
0
0
0
0
1
1
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1
1
1
0
0
1
1
1
1
1
1
1
X
1
X
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
0
0
0
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1
0
1
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0
1
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1
1
1
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0
1
0
0
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0
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1
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1
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1
0
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0'
1
0
1
0
0
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
HI-Z
1
1
1
1
1
1
1
1
1
1
1
1
HI-Z
1
1
1
1
HI-Z
1
1
1
1
HI-Z
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
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1
0
1
0
1
1
1
0
0
0
0
1
0
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1
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0
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1
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HI-Z
HI-Z
HI-Z
HI-Z
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223
nc
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Custom MOS/LSI
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Custom MOS/LSI Product Flow
Interface between
Customer and
Design/Production
Engineers
Product Definition
Time Sharing Computer
Simulates
Static and Dynamic
Performance and
Worst Case Parameters
Partitioning
Simulation
Macrodata FEDIS
LSI Design System
Drafting
Digitizing
David Mann
Reticle Generator
lOX Reticle Generation
David Mann Camera
6-Barrel Step & Repeat
Mask Making On-House)
Wafer Fabrication
Volume Wafer Production
Santa Clara Facility
Assembly
Volume Assembly,
Worldwide
Macrodata J259, J277
100,230-2 LSI Tester
100% Wafer Probe Test
100% Finished Product
Test
Quality Assurance
Internal Spec to MIL-STD 883
/
Reliability
High Rei Processing
Available on all Products
Shipping
225
INTRODUCTION
While custom and standard MOS have advantages
over each other for specific applications, there is a
high demand for both in today's electronics industry. In most cases, the true test of whether a system can most economically be implemented with
standard, custom, or both, can only be det.ermined
after partitioning. If the quantities in question do
not exceed a few hundred units per year, the standard product approach is probably the best solution. However, if the total number of units is
several thousand per year, then customizing is
usually the best approach.
Custom MOS circuits are designed to do a specific
job. You are not buying capability that is not
needed. The entire ch ip is devoted to performing
your specific function. Advantages are:
1)
2)
3)
4)
Fewer Packages
Lower Power Dissipation
Smaller P .C. Boards
Proprietary Design
These advantages result in lower system costs and
protection of your system design.
RESOURCES
National has brought together a group of experienced circuit and system designers, separate from
the standard product group, to offer a custom
MOS/LSI design service to the industry. This group
is prepared to aid in the logic design of a system,
partition the system into feasible LSI circuits if
the design requ ires more than one chip, develop
the chips, assist the customer in prototype system
checkout, and put the design into production.
National has one of the most advanced IC manufacturing facilities in the industry. Your custom
design will go through the same production facilities where National's standard MOS products are
manufactured, and thus benefit from our long
experience in MOS processing.
As with its bipolar circuits, the key to National's
MOS program is volume production. We are a
leading producer of shift registers, read-only memories, and random access memories. I n the latter
category, National is supplying many second source
and proprietary static and dynamic RAMs as well
as several advanced large-capacity RAMs. National
is also exploring other MOS device applications,
such as MAPS (Microprogrammable Arithmetic
Processor System). This unit contains five LSI
chi'ps which, with very few added parts, can comprise a high sophisticated electronic calculator, an
"intelligent" computer terminal; or even a lowcost microprocessor.
National was the first company to offer MOS circu its that operate at voltage levels directly compa'tible with TTl. (Previously, level-shifters were
needed if high-voltage MOS and low-voltage TTL
were to work together). To achieve this so-called
low-level MOS operation, National pioneered in
the fabrication of circuits' made from silicon cut
226
along the (1-0-0) axis of the crystal. Subsequently,
other companies developed bipolar compatible
MOS circuits also. Today, National is investigating
a variety of MOS technologies to determine the
best process to use a specific function. During the
past year, National introduced the silicon gate
process to the MOS product line; other tech"
nologies such as ion-implantation, N-channel and
CMOS are also being investigated. The company
will use any available technology as a tool to
achieve necessary performance for a given function.
1-0-0 P-channel metal gate and 1-1-1 silicon selfaligned gate enhancement mode MOS technologies
are presently utilized by National in our standard
MOS products. Tnese processes have become industry standards. All of the P-channel MOS process
devices offer bipolar compatibility.
Metal gate devices operate to 3.3 MHz. This technology is well-suited to random logic and ROM
applications. Higher logic densities and operating
frequencies approaching 10 MHz can be achieved
by using silicon gate technology. This process lends
itself to RAMs, registers, and random logic applications.
Static and dynamic logic is available in both metal
and silicon gate devices (including ion-implants).
I n general, less power is dissipated if dynamic logic
is employed, which also offers the advantage of
synchronous operation and eliminates hazards due
to race conditions. In any event, power dissipation
of typical LSI functions (up to 1000 gate functions) approach 500 mW in devices fabricated with
either metal gate or silicon gate technology.
Complementary MOS (CMOS) technology is presently being used on many standard products and
will soon be available for custom products. Structured logic, ROMs, RAMs, and registers, designed
with CMOS cannot ach ieve the density of Pchannel MOS. However, quiescent power and dissipations are less than one microwatt per gate.
Operation to 10 MHz can be achieved. One of the
advantages of CMOS is that power dissipation is a
function of frequency, with the DC (quiescent)
state consuming the least power.
The N-channel process is also undergoing development at National. This process allows higher density and high frequency operation than P-channel.
This process is slated for production capability
before June 1972.
Ion implantation is a tech nique that can be appl ied
to any of the previously mentioned processes. It
allows threshold voltages to be adjusted to a desired
level by implanting ions in the gate region. Depletion load devices and large value ohmic resistors are
also being made with ion implantation, which
greatly improves packing density on LSI chips.
DESIGN
Your custom design will benefit from National's
longtime experience in the MOS business. Extensive use of computer-aided design (CAD) and
computer simulation programs assure proper operation of your circuit before it goes into production.
n
c:
All designs are verified with a circuit analysis program to assure proper operation. Worst case signal
paths are checked to see that no signal race conditions ex ist.
Circuit layouts are performed using both manual
and CAD techniques. Manual artwork generation
is produced on rubylith cut and peel material. The
CAD system bypasses this step entirely and goes
directly from a digitized layout to lOX recticles
eliminating the need for rubylith and intermediate
reduction steps. National's photomask generation
laboratory is one of the best equipped in the
industry including the Macrodata FEDIS System,
the David Mann Pattern Generator, Reticle Generator, and 6-barrel step and repeat camera.
TESTING
National has a number of LSI testers that allow
complete checkout of structured logic (ROMs,
RAMs, shift registers, etc;) and random combinational logic. The random logic testers are computer
programmed to test to the custome(s input/output
logic specifications. On-line testers include Teradyne J259, J277, Macrodata 230-2 LSI tester and
Macrodata 100 memory system exercisors.
After fabrication, each wafer is checked for threshold voltage, breakdown voltage, oxide rupture
and sheet resistivity. The wafer then goes into
functional test. The logic on each die is thoroughly
exercised. This 100% test of each wafer eliminates
any functional defective die from being packaged.
After packaging, all devices are stressed to environmental extremes. The packaged devices are then
returned for another functional test.' Depending
on the customer's requirement, packages can be
tested under a variety of environmental conditions
and can be SUbjected to a burn-in cycle. Full M I LSTD 883 processing is offered on all National
custom and standard MOS devices.
QUALITY ASSURANCE
National's quality assurance department has a complete and comprehensive qual ity control program
which effectively controls component parts and
vendors at a qual ity level of fu nctional, workmanship and dimensional criteria. The OA program also
covers in-process controls of assembled devices,
final electrical test, marking and final shipment of
approved product. All procedures are documented
at specification control and at respectiVe quality
inspection stations. Weekly and monthly reports
are generated for qu ick feedback of information
for corrective action purposes.
All inspections are performed to specified internal
AOL inspection levels wh ich meet or exceed MI LSTD 883.
RELIABILITY
The reliability evalu.ation program .in effect at
National is a continuous monitor on .the process
stability of assembled devices 01') extended life
en
lest. Tests which are performed on a continuous
basis on each process are:
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(a) High Temperature Operating Life Test (extended life)
(b) High Temperature Storage Test (extended
life)
r-
MIL-STD 883, which specifies testing procedures
for i'ntegrated circu its, was innovatively handled by
National. The company adopted 883 specs as its
own, rather than to set up one procedure for
military orders and another for industrial customers. Therefore, there are no dual standards at
National. All devices are given the same quality
control treatment and the company inventories
devices with guaranteed 883 specs.
en
All standard devices undergo M I L-STD 883 testing.
They are 100% subjected to a temperature cycle
per Method 1003 Condition D, fine leak test per
Method 1014 Condition A, Helium 5 x 10-7 , and
gross leak test per Method 1014 Condition C.
The company has been informed by the National
Aeronautics and Space Administration that it has
received line certification under M I L-M-38510, the
new military standard defining acceptable procedures for producing devices.
A customer may request any special rei processing
per Document NSC/0002. The intent of this document is to provide the user with the ability to
procure any integrated circuit manufactured by
National to any class of M I L-STD 883 processing.
PACKAGES
National offers a variety of dual-in-line packages
(DIPs), metal cans, flat packs, and specialized
packages. Both ceramic and molded packages are
available.
All packages meet the standard JEDEC registered
outlines. Lead finishes are available in either gold
or tin. The ceramic packages meet a leakage of
5 x 10-7 std cc He/sec leak rate. National's molded
packages are the most advanced in the industry
and afford reliability which rivals the ceramic
packages.
FACILITIES
I n addition to its 150,000-square foot Santa Clara
facility, National has operations 'in Connecticut,
Singapore, Hong Kong, Scotland, Germany and
Australia totaling over 300,000 square feet. Personnel is presently over 3,000 worldwide.
In Singapore, National completed its 90,000-square
foot facility prior to fiscal 1971 but assembly and
test functions were substantiallv expanded during
the past year. The Hong Kong plant doubled in
size and will again expand in 1972. In Europe, test
and warehousing facilities in Scotland and West
Germany continued to grow in fiscal 1971 in preparation for future assembly operations. The establishment of NS Electronics Pty. in Australia provides the company with an assembly operation in
that part of the world.
227
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2
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Application Notes
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THE SYSTEMS APPROACH TO CHARACTER GENERATORS
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Large capacity, high speed, and bipolar compatibility strike directly at the problems involved in
lowering data terminal costs. To generate and update readouts with many characters and symbols
takes thousands of bits of storage and fast manipulation of data and control signals. If this capability
is supplied in a central processor, it must be paid
for in the form of central system overhead and
communications costs. Using pre-LSI memory
techniques in the terminals, however, can easily
double the cost of each console. 1
MaS integrated circuit producers are in the thick
of this competition. They have begun making
read only memories and shift registers with enough
storage capacity to put an appreciable dent in
terminal and printer costs. Entire alphanumeric
character fonts and CRT refresh channels now can
be fabricated as single-chip arrays. Low threshold
MaS processes and designs have been refined to
make the storage arrays more compatible with
bipolar logic and standard power supplies.
Storage capacities per MaS chip have increased at
least tenfold in the past few years, with comparable reductions in assembly costs. By the close of
1969, MOS/TT L character generators cost about
half as much as those built with bipolar devices.
The newest ROMs (read only memories) for character generation represent the integration of some
3,000 diodes and 50 packages of IC gates. One
terminal manufacturer who made the changeover
late in 1969 replaced six large printed circuit
boards with one plug-in card.
These developments have won MaS a place on the
alphanumeric side of the readout family tree in
Figure 1 (and some inroads are being made on the
other side-see Appendix on Page 239. I n fact,
MaS has pushed beyond the state of the art.
MaS/TTL assemblies can generate characters
faster than they can be handled by moderately
priced CRT video circuitry or printer mechanisms.
However, the increased storage capacity and speed
also make higher performance systems feasible.
For example, designers are considering larger fonts
that make characters more legible. Large fonts
have generally been economically impractical in
the past because even a small increase in font size
can double the memory size needed.
The largest MaS ROMs mass produced last year
stored 1024 and 2048 bits-general purpose sizes
used for table lookup, microprogramming and
random-logic functions as well as character generation. A typical generator contained three 1024-bit
ROMs, such as National Semiconductor's SK0001
and SK0002 kits (see Table 1 and Figures 2 and
3). Generating the standard 64· ASCII-selected
characters in a 5 x 7 font requires a storage capac-
FILAMENT
TUBE
GAS
DISCHARGE
GAS
READOUT
(I)
MaS ROMS AND REGISTERS
A huge new market for man/machine interfaces is
being created by the increasing availability of low
cost data processing through computer time
sharing, LSI calculators, minicomputers and digital
business and control systems. In turn, the pressure
is on to design CRT terminals, displays and teleprinters that are at least as compact and inexpensive as the new data processors.
"TICKER TAPE"
DISPLAYS
SEGMENTED
El
SCAN TYPE
El PANELS
(FUTURE)
FLUORESCENT
DISPLAY
RASTER SCAN
DISPLAY
TERMINALS
TYPEWRITERS
STElE·PRINTERS
(HAMMER OR BALL}
VEATICAlSCAN
DISPLAYS
TAPE PUNCHES
SPRINTERS
VECTOR
DISPLAYS
THERMAL,
ELECTROSTATIC,
ETC
OSCilLOSCOPES
RADAR,
MILITARY'
ETC
lE-liGHTEMITTING
El-ElECTROlUMINESCENT
Figure 1. Display Family Tree
229
ity of at least 5x7x64. Each logical "1" bit
stored in the ROM produces a black dot on a
printout or a bright spot on a CRT screen, and
each "0" bit a b.lank space.
Table 1.
ROM Combinations for Various Fonts
FONT
CHARACTERISTICS
5x7
Raster Scan
SKOOO1
or MM5240
7x5
Vertical Scan
static ROM required
SKOO02
or MM5241
7x9
Raster Scan
MM5241
(2 required)
9x7
Vertical Scan
static ROM required
MM5240
(2 required)
8 x 10
Raster Scan
MM5241
(2 required)
10 x 8
Vertical Scan
static ROM required
MM5240
(2 required)
E
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9 x 11
Raster Scan
MM5240
(3 required)
+'"
11 x 9
Vertical Scan
static ROM required
MM5241
(3 required)
12 x 16
Raster Scan
MM523
(6 required)
16 x 12
Vertical Scan
static ROM required
MM5241
(4 required)
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PARTS REQUIRED
Two new soon-to-be-announced ROMs are the
MM5240, storing 64 x 8 x 5 bits, and the MM5241
storing 64 x 6 x 8 bits. Each chip also contains
decoding logic and sense amplifiers (as do the
1024 and 2048-bit chips). Thus, one ROM is
ample for a standard 5 x 7 or 7 x 5 font. The
added capacity can implement special needs, such
as dropping comma tails below the other characters and symbols. But its main purpose is in
providing the logic and programming flexibility
that enables ROMs to be operated in tandem to
generate the larger font sizes indicated in Table 1.
The additional capacity costs little in terms of
silicon real estate because these devices are made
by low-threshold processes with p-channelenhancement mode MOSFETs as the storage
elements-the most LSI-able type of MOS.
I n the past, when diode matrixes were used as
character generators, the 5 x 7 or 7 x 5 fonts gave
the best cost/legibility tradeoff. Because the new
ROMs lower the cost per function, the 8 x 10 font
will probably become the most attractive.
The input-output configurations of the MM5240
and MM5241 are outlined in Figure 4 for a standard ASCII-addressed font. The 6-bit ASCII code
words will address any of 64 characters (2 6 ). The
control logic generates the three additional address
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B,-.O.O.
B,-:gg::
B,/.OOO.
B,/
All GATES ARE
DMIOOO OR DMlll0
LINE RATE
CLOCK INPUT
Figure 2a. Three-ROM Raster Scan Character Generators
230
Figure 2b. Character Generator For Tape Printers and
Other Vertical Scan Applications
»
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CHARACTER SELECT
I,
0
0
0
0
I,
0
0
0
0
CHAR
8
0
4
12
o
0
o
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0
1
1
0
2
10
6
14
1
. .. . .
16
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1
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1
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0
0
1
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0
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0
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0
1
0
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ROW
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Also, special requirements of data entry and output for display formatting and editing can be
implemented much more easily with registers than
with physical delay lines. Data bit positions in the
recirculation loops are maintained in alignment
and can be monitored and modulated precisely by
the control logic (one recirculation loop is needed
for each data bit-six loops, for example, in an
ASC II-addressed system). Data entry and output
for display or transmission thus becomes a
straightforward exercise in logic design.
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BIPOLAR COMPATIBILITY
A dynamic register is one that must be clocked at
some minimum frequency. Data is retained in the
form of charge storage and the charges would
eventually leak out of the storage nodes if not
re-established. In contrast, the ROMs being discussed are static devices, generating an output only
when addressed. Specifically, they are designed
and programmed to be sequenced by TTL ICs.
Furthermore, the new generations of ROMs and
registers accept and put out bipolar level signals
and operate off +5 volt and -12 volt power
supplies.
These features eliminate any need for special
level-translating circuits between the MaS and
bipolar devices. Also, special power supplies are
not generally required because ±12V as well as
±5V supplies are usually provided in terminals for
other parts of the system. Such compatibility is a
convenience and a cost saver in any digital system
containing MaS storage subsystems and bipolar
logic, since it mi.limizes the interface and drive
complexity. In terminals, though, compatibility is
practically essential for efficient operation and
lowest cost per function.
First, as the detailed system diagrams show, many
of the interconnections have a MaS device at one
232
end and a TTL device at the other, so that a large
number of level translators would be needed if
they were not compatible.
Second, several control logic operations must
occur between memory outputs, and the outputserializing device must operate at least six or eight
times as fast as the word (dot line or column)
output rate of the ROM. Obviously, if high speed
control logic-preferably TTL MSI devices such as
single-chip binary counters and 8-bit parallelinput/serial-output shift registers-were not used,
the character generating process would be slowed
excessively. This would limit the number of characters that could be displayed in a CRT refresh
cycle or printed out in a given time. The new
generation of MaS ROMs can deliver up to eight
bits in parallel in about 700 nanoseconds, compared with a microsecond or more for last year's
models. Logic speeds around 10 MHz are therefore
desirable (several times higher than the speed that
can be achieved by MaS gates.) Likewise, dynamic
registers can now easily be run at rates above
2 MHz-double the speed of early mass produced
registers-so the logic controlling refresh storages
must also be faster.
The improved compatibility and higher speed are
largely due to better design and processing of the
input and output stages of the registers and the
sense amplifiers of the ROMs. They don't increase
the complexity of the MaS circ'u itry, unl ike other
techniques for increasing MaS speed, and therefore they have permitted the capacity increases
cited.
The net benefit to the system designer, of this
approach to MaS design is that it enables the
~ystem designer to capitalize on the best features
of each technology-MaS storage for high density
and low cost, and TTL for high speed processing
of data and control signals. This is what produces
lowest cost per function in most digital systems.
CRT RASTER SCAN DISPLAYS
The basic refresh mode in Figure 5 limits the
number of characters that can be displayed. A
better way of generating and refreshing raster scan
displays, particularly those with many rows or
lines of characters, is outlined in Figure 6. Figure 7
illustrates the timing and logical implementation
for a multiple row system.
As before, coded data from a communications link
or the console keyboard passes through the registers and addresses the character generator. I n these
examples, the 6-bit ASCII input and the 3-bit
control logic input generate raster scan character
formats that allow a conventional TV monitor to
be used as a display. Communications codes other
than ASCII can be used.
If the ROM contains a 5 x 7 font, each 5-bit character line output will form five horizontal bright
spots on the CRT. That is, each ROM output
generates one-seventh of each character in a row of
displayed characters. The output is serialized by
the TTL register and uSE;!d to intensity modulate
the CRT beam as it sweeps across the screen.
M LOOP
DATA
INPUT
(6 BITS)
LINE
SELECT
Figure 6. (M-N)+N Technique for Large Page Displays
The refresh memory registers are divided into M-N
and N sections to facilitate page displays. M is the
total number of characters displayed in several
rows (lines of the page) and N is the number of
characters in each row. To form such a display
with single-loop registers, as in Figure 5, would
take seven recirculations of all M data words
during each refresh cycle of the CRT. The technique in Figures 6 and 7 only requires high speed
recirculation of N bits at a time, with advantages
that will be discussed shortly.
Assume that on the first sweep of the CRT beam,
the ROM is being addressed by the six register
outputs representing characters N 1, N 2 , N 3 , etc.
The first horizontal, 5-dot line of each character in
the display row are displayed in sequence. Then
the line address inputs to the ROM from the control logic change to their second state at the time
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2
thatN 1 has completed its recirculation to the N
register's outputs. Thus, on the second CRT
sweep, the second series of 5-dot lines are displayed horizontally for all N characters. At the
end of seven recircu lations, the complete row of N
characters is on the display.
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Now, the contents of the N register are not returned to the input of the N register. Instead, they
are fed back to the input of the M-N register and
this register is clocked to load the N register with
the second group of N characters. The M-N register
is then held still while the N register recirculates
seven times to generate the second row of characters on the display. After all M characters are on
the display, the first group of N characters is
reloaded into the N register and the entire process
is repeated to refresh the display.
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The M-N-N technique does not require any more
register stages than the M-Ioop technique and
significantly reduces control and drive circuit
requirements-again producing a lower cost per
function.
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1
10
1,000
100
MAXIMUM OPERATING FREQUENCY (KHz)
Figure 8. Power vs Frequency Plot of
Dynamic Register
Typical
MOS
the registers can safely be quiescent for as long as
2 msec. (The typical MM register will actually hold
data for 10 msec.) Suppose the N register stores 40
characters and operates at 2 MHz. The quiescent
period can be as short as 40 x 7 x 0.5 = 140 J.1s. If
standard TV raster timing is maintained then the
quiescent period will be 7 x 63 J.1s = 441 J.1s.
Obviously, the designer has great leeway in character rates, operating temperatures, and register
capacities.
Other applications in displays for clock modulation include input-output buffering of data during
data reception and transmission,2 or during display editing and formatting through the console
keyboard. The register rates can be adjusted via
control logic to accommodate differences between
I/O and recirculation rates. Note that the gating in
Figure 7 permits data entry under TTL control
into either register section.
CHARACTER GENERATION
The first generally available MaS character generators were kits such as those in Figure 2, using
three 1024-bit ROMs (MM521). Although singlechip generators were being developed in 1969,
they were in very short supply. The kits cost about
half as much as diode generators and thus allowed
terminal manufacturers to start the changeover to
MOS.
The kits are also a good place to begin describing
character generator operation in this appl ication
note, because they provide an "exploded view" of
multi-ROM generator operation. Similar techniques will be needed to build larger fonts with the
new devices. The external gating functions shown
in Figure 2 are not needed for these fonts when
the MM5240 and MM5241 are used. The "assembly" of the dot patterns is taken care of in the
programming of the ROMs. However, to generate a
large font, such as 8 x 10 or 12 x 16, with the new
ROMs will require operation of two to four ROMs.
••
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•
•
For a 5 x 7 font, the new single-chip character
generators are simply programmed to generate all
5 bits in each dot line, from a 9-bit address. Standard programming provides the 64-character
ASCII set, but special characters can be substituted by changing the stored dot patterns. The
reprogramming process consists of altering an
etching mask that controls gate insultation thickness in the MaS field effect transistors of the
storage array. If the oxide is left thick, the transistor will not switch when selected by the'decoding
logic, generating a "0" output from that location.
Figure 9 indicates why the storage capacity of the
MM5240 is 5 x 8 x 64 rather than 5 x 7 x 64-each
ROM can generate half of the 8 x lOx 64 character set. The ROMs can be addressed simultaneously, as before, and be commutated by the
control logic to put out the 8-dot horizontal lines
in the correct sequence. For very high speed character generation, the addressing of the ROMs can
be skewed or overlapped so that the outputs from
one are generated while the inputs to the other are
being decoded. The only real limitations to the
character generation rates achievable with such
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VERTICAL SCANNERS AND PRINTERS
connected to the output buses in the reverse order
(i.e., output 1 to bus 7"output 2 to bus 6, etc.) .
Vertical scan character generators are generally
used in hard copy applications. Also, a vertical
scan type of character generator can sometimes be
more suitable for CRT displays than raster scan.
SAW TOOTH DISPLAY
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Displays or printouts of calculators and small
business machines often show only numerals and a
limited variety of symbols-not enough for a full
alphanumeric generator. Such fonts are easily
programmed into a small ROM such as the
1024-bit MM522, which stores 1288-bit words.
There's room for 16-5 x 7 dot characters on the
chip .
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Figure 10a. Two Techniques for Vertical Scan
These ROMs are also used in the SK0002 kit for a
64-character ASCII-addressed font (Figures 2b and
3b), which requires the storage of 3207-dot
columns and a 7-bit address. Connected as shown,
the DM8533 TTL binary counter will reset on the
count of 16. And with the gating and interconnections shown, the column select cycle is:
Counter Outputs DCB
ROMs Enabled
DCB
000
001
010
011
100
101
MK004
MK005
MK004
MK005
MK006
reset (instantaneous)
Figure 10b. Example of Character Generation
Pedestal-type Scan.
A CRT beam can be intensity modulated by the
serialized output, as in the raster scan technique.
However, the electron beam traces either a saw'tooth' or pedestal-type scan pattern on the screen
(Figure 10). Every column of each character in the
display line is scanned in sequence, starting at the
left-hand side of the screen.
The sawtooth scan is straightforward, but the
pedestal scan requires that the bit order be reversed in the second and fourth columns. To do
this, the outputs of the M K005 ROM are simply
In the new single ROM (MM5241) version of this
system, (Figure 11), a 9-bit address is needed,
6 bits for the ASCII code and 3 bits for dot col-
CHARACTER
GENERATOR
INPUT
CHARACTER
DATA
LINE
COUNTER
LINE
DIVIDER
Using
Long shift registers, operating at relatively slow
rates can be used. The character rate-the, register
shift rate-is no more than 1/6 of the columnselect rate for a 5 x 7 font, since the beam traces
one complete character before going on the next
one. A dot counter loads spacing bits between
characters via the TTL shift register, a character
counter triggers the sawtooth or pedestal scanning
patterns, and a row counter would control positioning of the beam in a page display system.
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PEDESTAL DISPLAY
COLUMN
COUNTER
DDT/COLUMN
DIVIDER
Figure 11. Vertical Scan Display System
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Since a display utilizing the vertical scan techniques has input address changes at some multiple
of the display character rate, a clocking system for
a dynamic ROM character generator must be
supplied. This requires the addition of a frequency
divider and clock generator which results in a
higher system cost when dynamic ROMs are used.
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A second consideration which should not be overlooked in systems cost is the compatibility of
ROMs in mUlti-package character fonts. Optimum
ROM usage and organization will result in lower
systems cost. ROMs will also find applications in
micro-programming and code conversion where
synchronous operation is preferred.
The 8 x 10 font is much better and 12 x 16 is
almost optimum for legibility. Small, lower case
characters can be sharply defined, too, and they
almost appear to be drawn with continuous
strokes.
System designers considering these fonts for lowcost displays run, at present, into CRT cost problems. The least expensive displays are televisiontype CRTs with limited video bandwidth. Bandwidth also limits the number of characters that can
be displayed simultaneously. Not counting the
times required for beam retrace and functions
other th~m character generation, which reduce the
time available in a refresh cycle for dot handling,
the necessary bandwidth is roughly:
BW = (dots and spacing bits per character)
X (characters per display row or page)
X (refresh rate)
238
Obviously, the designer can drop the refresh rates.
New CRTs with longer persistence phosphors
facilitate this. Also, CRT manufacturers have been
responding to the new terminal market by working
on bandwidth improvements, and they are apparently going to reach 10 MHz in moderately priced
video systems soon.
Finally, the designer is not obligee! to display his
characters digitally just because he uses a MaS
ROM. Don't forget that the ROM is really working
as a code converter, generating a 35-bit machine
language code from a communications code. The
language translation can be whatever the situation
requires.
All 'that need be done is update methods used in
analog displays, which form characters with
strokes rather than dot lines or columns. The
ROMs can be programmed such that the bit outputs, when integrated, control X and Y ramp
generators. The slopes of the ramp functions are
determined by the number of bits in a sequence
and the lengths are determined by the locations
chosen for turn-off bits. As in the vertical scan
technique, the ROM is addressed at the character
rate.
Even though some characters can be formed with
one or two strokes (I, L, etc.), equal time should
be given to all characters in a page display to keep
the character rows aligned. A standard sized area
of the MOSFET array, such as 6 x 8 or 5 x 8
should be used for each character. Most patterns
would thus be a combination of stroke and nostroke outputs. The single-chip fonts have an
8-stroke capacity for each of 64 characters which
is more legible than the standard segmented type
of instrument readout, since slant lines could be
generated wherever needed.
I
APPENDIX
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WHAT ABOUT INSTRUMENTS
AND CONTROLS?
While it is safe to predict that 1970 will be "the
year of the MaS" in alphanumeric terminals, MaS
applications in numeric readouts are just beginning
to emerge.
A new device with considerable promise in this
field is a high voltage, MaS static shift register, the
MM5081. Developed by National, it has a TTLcompatible serial input, 10 parallel outputs that
can stand off -55V, 10 latching-type storage
stages, and a serial output.
This novel combination of functions means that
the MM5081 can drive lamps, numeric indicator
tubes, filament tubes in segmented number and
symbols displays, electroluminescent panels, and
the new gas-cell arrays. In short, it provides MaS
with a good foothold on the numeric side of the
readout family tree in Figure 1.
The register stages can either shift the bits to the
serial output for recirculation or store the data
indefinitely. Hence, displayed characters can be
swept along a line of indicators, "frozen" on a
stationary display, or made to reappear periodically at any desired repetition rate.
A code-converting/character-generating ROM can
be placed at the register input, to display numbers
and symbols or alphanumerics. A designer can get
almost as much flexibility from a lamp or panel
display as from a CRT display. In fact, the first
application of the MM5081 is controlling a matrix
of neon lamps in a moving billboard display.
Some applications for character generators in instruments are also cropping up. Displaying range
scales on an oscilloscope is a good idea that can be
improved upon with the new ROMs. The display
frees the operator of the chores of mentally calculating scale factors and manually writing these on
scope photos. With an alphanumeric font, the
camera can also record information such as test
conditions, date and time of test, identification
numbers, etc. Photo sequences and the data
needed to analyze the curves can be coordinated
automatically.
Similarly, a ROM can be programmed to display
standard curves for go-no-go equipment checkout
operations_ For example, if a radar's pulse amplifier should have ce~tain output characteristics, the
ROM generates the correct output curves through
a digital-to-analog converter and stroke generator.
When an actual operating characteristic and the
reference curve are displayed simultaneously, the
operator can tell at a glance whether the radar is
functioning properly. Many curves or general purpose curve segments can be programmed into a
ROM and picked out as needed with selector
switches or a ROM microprogrammer.
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ROMs can be programmed as lookup tables,
random-logic synthesizers,4 encoders, decoders,
and microprogrammers as well as character generators. A single ROM can perform limited combinations of these functions, virtually qualifying it as a
microcomputer. It has been suggested that this
capability be used in control panels to perform
functions like actuating an alarm when a transducer level goes out of range and initiating corrective action. ROM addresses can be derived from
digital meter circuitry. In multi-point measuring
systems, this would provide the solid state equivalent of a rack of meter relays.
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The use of high-speed logic for control is facilitated by making the MM5081 with low-threshold,
p-channel, enhancement-mode MOS transistors. As
a rule, a low threshold device allows data to be
entered at bipolar logic levels.
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The output transistors do not need a large gatevoltage change to turn on and off. They are also
low-threshold devices in this sense. But they have
to withstand transients up to 100 volts and stand
off steady state voltages up to 55V to operate
lamp-type displays reliably. Adequate gate logic
voltages for the output transistors must be ensured
to make the lamps glow brightly when they should
be on or to make them free of any residual glow
due to switch leakage when the switching transistors are turned off. That is, a low RON and high
ROFF must be ensured despite very high voltage
on the MOSFET drains. Because a pullup resistor
is used, the input gate should be a TTL or DTL
device with an uncommitted-collector output able
to withstand at least 1OV. Among such devices are
the DM881 0, DM8811 or DM7426 (SN7426) quad
NOR.gates, or the DM8812 hex inverter. All these
TTL devices will stand off to 14V.
The other two gates used in the input switch can
be any TTL or DTL types. The arrangement shown
brings the serial output back to the serial input
through the top gate when the "new data enable"
line is low (DTL/TTL logical "0") or permits the
registers to be reloaded with new data when the
enable line is high. A pull-down resistor is placed
on the register output to handle 1.6 mA the current sinking required for operation of the TTL or
DTL recirculation control gate.
TICKER-TAPE DISPLAY
A straightforward type of moving lamp display is
illustrated in Figures 2 and 3. Simple messages such
as CALLING DR. CASEY ... CALLI NG DR.
CASEY ... DR. CASEY, PLEASE REPORT TO
SURGERY ... or stock quotes, or a series of
instrument readings would be displayed as 7X5
characters by this system. That is, each character
would be a lighted lamp pattern selected from a
moving matrix seven lamps high by five lamps
with a movingcolumn of lampsturned off between
characters. The off colu mn is a space bit in each
lamp row.
'Assume that the display is long enough for 33
characters. Each row requires 33X6 lamps and
198 register stages. Each row is a cascade of 20
MM5081's. The input of the first register and the
FIGURE 2. 7XN Bit Shift Register and Display
242
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output of the last register are connected as in
Figure 1, and the registers in between are simply
daisy-chained by connecting each serial output to
the next serial input. All seven rows would use
140 register packages.
The character data for th is type of system can be
formatted by a standard character generator. For
instance, the standard ASCII code can address a
bipolar compatible read-only memory such as
National's MM5241AA, which is programmed to
generate 5X7 dot-type characters for CRT display.
However, in the lamp display system, the display
refresh function is handled without an additional
memory. The column bits are entered in each
register chain, as before, through the input gating
at a rate determined by the clock rate supplied
the MH0025C clock driver. The MH0025C is a
two-phase driver. However, since the MM5081
takes a single-phase clock input (converted to a
two-phase clock inside the register package), only
one of the dual drivers in the MH0025C package
is shown (the other half can be used to share the
clock-drive load).
After the registers are loaded, the clock into the
driver is dropped to a frequency of 2 Hz, if the
register was loaded at a higher frequency. This rate
is stabilized by the coupling capacitor Ce . The
coupling capacitor on this type of driver determines the maximum pulse width, but the minimum pulse width is established by the clock
signal. So, at the lower frequency, the characters
sweep smoothly from right to left across the display lamps. They repeat the message every 100
seconds because 200 register stages are in each of
the seven parallel rows.
Both the clock driver and the registers operate off
the 10V and -6V power su ppl ied.
150Hz
1
~:5--U-UON
OFF
NEW DATA
INPUT
I
switch. The purpose is to limit the current and
voltage across the lamps and the MaS output transistors to ensure that they operate reliably and
have long lives. Also, the method reduces power
consumption and allows lower power, inexpensive
high-voltage power supplies to be used.
~
~
The high-voltage switch seen in Figure 3 and
detailed in Figure 4 switches at a rate of 50 Hz and
a duty cycle of 25%. Thus, when any of the MaS
output transistors is on, the lamp that is "on"
during that 250 msec display-rate interval ~ 100%
duty cycle at 2 Hz) is actually on for only 5 msec
at a time. Then it turns off for 15 msec. This refresh rate was chosen because it provides a good
lamp intensity with no apparent flicker.
+5V
-45V
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FIGURE 4. High Voltage Switch
The -125V supply turns' on the lamps, and the
-45V supply turns them off. But what is actually
being used is the voltage difference, or bias. Most
glow-discharge lamps require a 65V starting voltage
'and a 60V holding voltage. The switch keeps the
lamps alternating between these levels while the
MaS transistors are on, but imposes a maximum
voltage of only -65V on the MaS transistors (that
is, 125-60V) for the 5 msec "on" time. The
MM5081 can easily take this - the spec allows
-100V at 60 Hz (or 16.66 msec) and they are
stress-tested to this level.
INDUSTRIAL DISPLAYS
FIGURE 3. System Block Diagram
DISPLAY DRIVE
The high voltage supply (shown in the block diagram in Figure 3) is generated from a high voltage
The characters displayed can be any kind of
symbol within the resolution of the lamp array from letters to cartoon characters - and within the
flexibility of the controls. Getting patterns to
move back and forth while changing shape is
technically feasible, but would require complex
clocking techniques to put the bits in the desired
location. Static pictorial displays wou Id be fairly
simple to implement, merely requiring loading of
the registers at a high rate followed by storage at
a DC display rate for the desired time. Although
the characters would appear static, the high-voltage
switch would keep the actual duty rate low.
243
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There are many potential new applications for
moving-lamp displays in industrial control systems.
Functions such as process flow rates through
several feeder pipelines or subassembly line rate
in an assembly plant, cannot easily be set up on a
CRT display. Complex computer graphic techniques or very expensive mUlti-gun displays may
be needed.
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The clock rates and lengths of a number of rows
of lamps can readily be adjusted by hand-operated
controls, such as voltage-controlled oscillators and
gating between registers chosen by selector switches. Any feeder-line display rate that can be represented by the display rate could therefore be varied
at a compressed scale of time and distance until the
display operator arrived at the optimum balance
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244
of rates. This is a visual approach to a problem that
generally requires complex mathematics and analog computers to solve.
Nor do the rows of lamps have to be aligned.
Individual rows might represent route sections in
a transportation network between junctions. By
driving each section at a display rate simulating
the speed of a particular train, and switching the
"train" of moving lights from row to row via
switches at the junctions (serial output to serial
input register connections), control personnel
could simulate system operation. Problems such
as tie-ups - or worse - at junctions could be worked out by varying display rates for the trains whose
schedu les confl icted.
I
Application Notes
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AUGUST 1971
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DYNAMIC MOS RANDOM ACCESS
MEMORIES SYSTEM CONSIDERATIONS
(")
ABSTRACT
A new TRI-STATETM common I/O configuration,
capable of precharge decoding without losing system performance and bipolar compatibility, is
employed in a 1024-bit MOS RAM. In combination, the techniques reduce typical memory module
power dissipation some 66%, number of overhead
circuits by 50%, and overhead costs by 66%
without sacrificing system speed. Performance and
cost of the new RAM are compared with those of
an earlier design in a similar system application.
MOS supplies, and other cost reductions. Chiefly,
dissipation is reduced by 66%, overhead circuits
by 50%, and overhead cost by 66% with no loss
of speed.
To make these points realistic, the new design will
be compared, in a system environment, with another MOS RAM design with slightly faster access
and cycle times specified at the device level.
MOS STORAGE DEVICE
The internal design of the new MM5260 (Figure la) is fairly standard except for its bipolar
compatibility, I/O structure, and precharge decoding.
\ INTRODUCTION
Unlike earlier advances in MOS memories, the
advantages offered by the MM5260 MOS RAM
do not stem from a new process. Instead, a new
combination of operating techniques is used to
solve system cost/performance problems. The techniques are a TRI-STATE I/O structure at a common I/O terminal, precharge decoding, and bipolarcompatibility.
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The 1024 storage cells are in a 32 x 32 array. A
10-bit address is X- Y decoded on the chip to
access a cell. In each cell, Q, is the storage element;
Q 2 a read gate, and 0 3 a write gate. An MOS "1"
is stored by charging the capacitance of Q, and an
"0" by not charging it. Read consists of sensing
the data level after an access is made.
Memory size, cost and propagation delay of the
monolithic MOS random-access device were not
decreased. These savings could have been realized
quite easily at the device level by foregoing some
of the system advantages. The result at the system
level though is very low average power dissipation, simplified timing control, fewer and faster
interface devices with the external system, reduced
cooling requirements; elimination of high-level
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Bipolar compatibility means that all data and
address inputs sense bipolar data levels and that
data is read out at the original data levels. This
eliminates external level translators at inputs and
sense amplifiers at outputs. Previous MOS designs
required these interface circuits in a typical memory module. The common I/O terminal on the
MM5260 is made possible by the I/O structure
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FIGURE lb. MM5260 Connection Diagram
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FIGURE la. Internal Design of the MM5260
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seen in Figure 1a. The I/O gating and sensing elements are TRI-STATE MOS. As the name implies,
each element has three operating states. Two are
the bipolar-compatible "1" and "0" states. The
third is a high-impedance state that disables that
element. I n the third state, only a ~mall leakage
current flows at no definable logic level.
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that stored charges leak from the storage transistors and must be refreshed periodically. Each
cell must receive the refresh clock at intervals of
2 ms. Refresh is applied column by column at
62.5 /J.S clock intervals (an access also refreshes all
other cells in a column). Since accesses are made
every 600 ns, refresh overhead is less than 1% and
does not significantly affect system efficiency.
Refresh signals are given precedence over addresses
in the system control logic.
The third state prevents data transfer, allows one
element to look into the other, and permits outputs of several packages to be bus-connected with
no significant change in memory cycle time. One
pin serves for I/O because the read output buffer
is in the third state when write is enabled, and
vice-versa. When these outputs are bus-connected,
read speed is high because the disabled elements
on the bus load the enabled output very lightly.
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The chief advantage of dynamic MaS RAMs is
small cell size, about 4 or 6 square mils, which
makes packing density high and cost low. Static
MaS devices have latching cells that are not
refreshed but are most costly since the cell size
is 16 to 20 square mils. Therefore, fewer bits
may be placed within the same package. Bipolar
RAM cells are also large and costly, but operate
in about 50 ns.
In addition, the MM5260 uses two standard supplies (+5V and -12V) instead of three high-level
and non-standard supplies (+20V, +16V and +5V).
A possible additional negative supply (-5V) will be
required for a high speed sense amp.
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A conventional MOS output could not share a
common terminal with an input. Separate data-in
and data-out terminals may be required. Several
outputs also may be bus-connected. However, this
multiplies the capacitive loading, causing a proportional increase in output transition times: To
accommodate this, system cycle times must be
increased. For maximum speed, each conventional
MOS output should look directly into a low-level
sense amplifier which also has a low impedance
resistor at its input to minimize the data transfer
time constant.
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Dynamic RAMs require some special considerations. The storage cells are dynamic, meaning
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Dynamic MaS RAMs fit quite well into large
memories and higher system memory hierarchies
such as fast store, virtual memory and main memory. Their low cost, high density and relatively low
power dissipation suit them to main memory.
SYSTEM ORGANIZATION
Having ten address inputs, the MM5260 is effectively a memory of 1024 1-bit words. Lengthening
the bits per word merely require parallel access
of several devices, such as nine for 1024 9-bit
words. A chip-select input, enabled by decoding
additional address bits, allows expansion of word
capacity.
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Figure 2 is a MM5260 module storing 4096 16-bit
words (4k x 16) in four 1k x 16 submodules. One
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MEMORY
SELECT
REFRESH
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FIGURE 2. Main Memory Module Storing 4096 16-Bit Words Using MM5260
246
submodule is selected at a time by two bits of the
DM7442 TTL decoder address. The same decoder
could access eight submodules with a 3-bit address,
and so forth. This is standard decoding practice.
The external data selectors (DM8123) and read/
write bus buffers (DM8093 and DM8094) are
TRI-STATE TTL devices. 1 These have high-speed,
active-pullup outputs when enabled. The two types
of buffers can operate in parallel with the internal
MOS input/output mode read/write gates. One
control line gates both in complementary fashion
because one is enabled by an "0" and the other by
a "1". The data selectors hold off accesses during
a submodule's refresh intervals. Figure 3 is the
TTL clock forming and timing control circuit for
the module.
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2
is selected. This is implemented by having the
chip-enable of the decoder gate the precharge clock
via the TRI-STATE TTL data selectors in the
clock circuitry. Simultaneously, the I/O directions
are controlled. Selective precharge decoding can
yield an ultimate average power dissipation of
77 mW.
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MEMORY TIMING
The MM5260 timing control is quite simple because of precharge decoding and the I/O structure.
As indicated in Table 1, maximum cycle time is
600 ns. A delay of 100 ns before precharge is
allowed for address settling and decoder operation.
This allowable delay will not affect the access time
under worst case conditions. This element design
characteristic permits a very straightforward selective precharge decoding technique wh ich does not
affect the performance of the memory system.
Precharge goes low for 250 ns to set up the
decoders, then returns to conserve power.
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FIGURE 5. Main Memory Module with Conventional 1103·Type MOS RAMs
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TABLE 1: Comparison of Major Characteristics of MM5260 and 1103
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MM5260
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Organ ization
Chip Select
Input Data Levels
Output Data Levels
Common I/O Bus
Power Supplies
Package Pins
Access Time
Read Cycle Time
Write Cycle Time
Refresh Intervals
Power Dissipation During Access
Standby Power
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Yes
TTL
TTL
Yes
+5, -12V
16
350 ns
450 ns
600 ns
2 ms
400mW
75mW
1k xl
Yes
High (+20V)
Low (800IlA)
No
+20, +16, +5, -5
18
300-390 ns
540 ns
580 ns
2 ms
300mW
75 mW
TABLE 2: Components in Typical4k x 16 Memory Module
MOS RAM Packages
Total for Storage
MM5260
UNITS
1103
UNITS
64
64
64
64
2
1
3
2
1
Interface and Control Devices
DM8123 Quad Data Selector
DM7442 BCD-to-Decimal Decoder
MH0026 Clock Drivers
MH0027 Clock Drivers
DM74451 Power Translator
DM8093/DM8094 Bus Buffers
DM7402 Gates
DM7400 Gates
DM7404 Gates
DM7408 Gates
DM7420 Gates
DM8281 Counter
DM86L76 Counter
DM74L73 Flip-Flops
DM9601 Monostable Multivibrator
LM7524 Dual Sense Amplifiers
Total for External Parts
248
10
2
18
18
4
2
2
5
1
1
2
1
3
26
1
1
2
1
4
8
69
REFRESH
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2
Important differences between the MM5260 and
1103 characteristics are summarized in Tables 1
and 2. Their individual device cosJs are comparable
and the 1103 appears to enjoy a performance edge
(50 ns) at the device level. However, let's examine the 1103 specifications at the system level.
Major modules, though not submodules, are almost
interchangeable. As proof, compare the typical
1103 4k x 16 module in Figure 5 with Figure 2.
Both are very similar conceptually.
MODULE COMPARISON
Power Dissipation
One significant difference is in the power requirements. The 1103 uses two high-level supplies and
dissipates about three times as much power as
the MM5260 module. Total dissipation in the MOS
RAMs and by the circuitry outside the RAMs in
Figure 5 is around 30W, while that of the MM5260
module is about lOW. As a benchmark, core memories with the same capacity dissipate about 25W.
Clearly, the MM5260 has the advantage. The power
dissipation factors are standby power-the same
75 mW for both device-precharge dissipation,
and external dissipation.
A quick calculation shows that the MM5260 has
precharge dissipation in only 16 out of 64 devices,
due to precharge decoding. With standby dissipation in the other 48, total memory dissipation is
about lOW. Dissipation in the logic devices is not
large in either device.
Precharge dissipation in the 1103 is 300 mW,
100 mW less when it is accessed at a 600 ns rate.
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Precharge is used to reduce access time as well as
average dissipation in the 1103, which compromises precharge power savings. Using precharge to
save time precludes precharge decoding. Figure 6,
the 1103 timing diagram, shows that precharge
sets up the decoders to receive the addresses.
Therefore, it must be applied to all 64 RAM circuits since the chip-enable portion of the address
is not decoded until after precharge begins. After
chip-enable decoding, precharge may be turned
off for the unselected submodules. By then, these
49 circuits will have been precharged for some
100 ns, consuming an extra six watts.
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A total of about 14W are dissipated in precharge
and standby power in the 1103 memory module.
In other words, the MM5260 memory solution
has already saved 30%.
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The extra amplifying devices account for the rest
of the increase. Address, chip-enable and data inputs must be pulled up to +16V. These level
translators must drive heavy capacitive loads. For
example, each address input capacitance is 7 pF,
a total of 450 pF for 64 in parallel. To avoid
making input delays very long, high-power transistor drivers must be used. The low-level outputs
must be detected with sense amplifiers to drive
logic in the processor. Furthermore, the highlevel supplies increase dissipation elsewhere in the
system and add to the system cost since they are
nonstandard.
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100 ns might result in some system designs. This
easily offsets the access specification of 350 ns in
the MM5260. This included an output delay of
some 40 to 50 ns in the MM5260 access and
cycle times because of on chip output TTL compatible buffering. This delay in the TRI-STATE
sense amplifier in the MOS chip was considered
a worthwhile tradeoff to achieve the benefits
already cited for the common TRI-STATE I/O
technique.
Effective packing density is higher, because the
MM5260 has two less pins than the 1103 (obtained
by common I/O), one less supply, ard less stringent
cooling requirements. More RAM circu its can be
packed into the same volume; more also can be
added on bigger boards when system designers
want to increase word length or module word
capacity. Smaller boards, of course, further reduce
system packaging costs.
It might be noted that the TRI-STATE TTL bus
buffers will drive long buses at high speed with
high t')oise immunity. Therefore, the common I/O
bus can extend well into the system structure.
CONCLUSIONS
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SYSTEM COST SAVINGS
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The obvious savings in system costs are listed in
Table 2. These consist of 17 interface and control
circuits, 8 dual sense amplifiers, 14 resistors, and
a need for only two supplies (+5, and -12) instead
of high-level supplies of (+20, +16, +5 and -5). One
can also add proportional savings in printed-circuit
board costs, cooling hardware, assembly, component test, inventory control, and so forth.
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Savings using the MM5260 in a typical memory
system module are 66% less pOVl.er dissipation,
50% fewer overhead circuits,. and 66% less, overhead cost. Speed performance is not curtailed and,
in many applications, an improvement may be
achieved.
These advantages stem from a combination of
three techniques: TR I-STATE common I/O structure with an internal sense amplifier, precharge decoding, and bipolar compatibility. All are oriented
toward system advantages, rather than cost/speed
improvements at the device level.
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FIGURE 7. 1103-Type and MM5260 Modules. The 1103 memory module utilizes NH0026
level translators in place of 36 DM74451 and NH0027 elements.
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Application Notes
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NOVEMBER 1971
USING THE MM5104 KEYBOARD
INTERFACE IN KEYBOARD SYSTEMS
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INTRODUCTION
When one contemplates the design of an MaS-LSI
chip to perform the keyboard interface function,
several elements immediately stand out for consideration. Among these is the obvious problem
of encoding a key closure, and whether the bit
pattern produced should be presented in a parallel
or serial fashion. One must also consider what
happens if more than one key is depressed, or
more than two. How fast can keys be physically
depressed and released? One at a time, or in a
series? What is required to be compatible with the
dynamic characteristics of the many different
keyboards being manufactured? What is the best
way to match the switch closure characteristics,
i.e., switch bounce, etc.? How may various keyboard capacities best be accommodated, or what
is required to allow for expansion of keyboard
capacity? All of these considerations and more
have been answered in the design of the first MOSLSI chip manufactured, by National, the MM5704.
It is called the keyboard interface (KI) chip and
it is one of a total of five chips, called MAPS Microprogrammable Arithmetic Processing System,
being designed to implement all the functions required of bit serial calculation systems.
All of these chips are unique in that they are
designed to perform their functions in a defined
system, hence implying a standard design. Yet
each may be as individualized and as varied as there
are ways to perform their functions. To explain
how this apparently paradoxical situation is possible, let's take an example. The keyboard interface chip, MM5704, will accept 32 character key
closures and provide 64, 9-bit encoded words in
the output. Each key closure will generate and
output a code up to 9-bits long for lower or upper
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case depending upon the state of the shift key.
Thus, a standard function is performed, that of
providing a 9-bit pattern with each key closure.
However, the bit pattern itself may be programmed
according to the desires of the individual user. This
ability is possible because the 9-bit pattern is
generated through the use of a read-only memory
(ROM) located within the chip. The key closure
merely addresses the ROM and its output becomes
the custom encoded word.
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Timing
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MM5702
Keyboard
Interface
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MM57 04
Control
ROM
(CROM)
MM5703
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5
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7
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9
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11
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15
16
17
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Idle Key Reset
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FIGURE 1. MAPS Pin Assignments
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WHAT IT DOES
TWO KEY ROLLOVER
In addition to the 32 character key switch closures
that may be encoded, there are 8 static switches
that may be interrogated. These static switches
may be controlled by the user to form an 8-bit
word which upon command will be sent via the
keyboard interface output to the rest of the system. These switch closures are used to perform
control functions. They may be used to form any
desired data word especially if it is to be varied
from time to time.
If a second key is depressed before the first key
is released, a condition exists that is defined as two
key rollover. In this situation, the device wiU acknowledge and transmit the encoded word generated by the initial key closure then acknowledge
and transmit the encoded data word generated by
the second key closure. At the time that the system responds to the initial key closure, the "busy
1" signal line becomes true (MOS logic "1" condition). This informs any parallel keyboard interface
chips that a key closure has been detected. The
"busy 1" signal will remain true until the encoded
data word resulting from initial key closure has
been transmitted and the key released.
The output of this device is presented at Pin 21 in
a bit serial fashion. This organization was required
to be compatible with the bus structured organization of the five chip MAPS. The bit serial, digit
serial, organization of this system was designed
to keep to a minimum the number of pins required
for each MOS-LSI chip used in this system. Actually, Pin 21 is a bidirectional bus, with input
capability for controlling static switch interrogation, data interrogation, or control of the alarm
and shift functions. In a system this is accomplished
with time multiplexing. (Figure 5)
If a system contains more than 32 character key
closures, the functions performed by the MM5704
may be expanded by paralleling two or more of
these devices. Two devices will provide 64 key
closures (128 data words), three prov ide 96, etc.
The two key rollover and three key alarm functions
will continue to function by paralleling the busy 1
(Pin 22) and busy 2 (Pin 23) signal lines. The
alarm signal will be available at Pin 1 of the
devices. This signal is not OR-~eable.
252
If during the time that the "busy 1" signal is true
and a second key closure is detected, the system
will flag this condition by causing "busy 2" to go
true. "Busy 2" will remain true until the encoded
data word generated by the initial key closure has
been transmitted and one key released. "Busy 1"
will remain true until all keys are released. A key
once depressed and acknowledged by the system
must be released and depressed ~gain before it will
be accepted and acknowledged as valid by the
system for the second time.
THREE KEY ALARM
If three or more keys are depressed, a condition
exists that will be detected by the system and
interpreted as the alarm condition. Because the
KI chip cannot process more than two key closures, depression of more than two must alarm
the system. When the alarm condition exists, a
signal is generated at the alarm output (Pin 1) and
an alarm pulse may be transmitted .to the rest of
the system via the data bus. The ability to signal
the alarm condition on the data bus is a programmable feature. The signal made available at
Pin 1 may be used to inform the operator of the
existence of the alarm condition. The alarm condition will also be triggered if two or more keys
are depressed simultaneously, such that the second
key closure is detected before the first key closure
can be processed and transmitted.
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The value of the reset capacitor (CR) is dependent
on the keyboard scan cycle.
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CR
Where:
average charging current:::: 1 rnA
reset voltage 23.0V
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charging time interval
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IDLE KEY RESET (PIN 9)
Where:
An automatic reset signal is generated during the
idle key mode of operation. This mode is defined
as no keys depressed and power is on. The reset
signal is created by charging an external capacitor
(CR) which enables the control logic to detect
first key closure. The purpose of the reset is to
prevent keyboard lock-up due to mass depression
of the keys, or any other attempt to void the
integrity of the keyboard interface chip. An example of this might be, depressing three or more
keys (including the clear key) to force an alarm
condition to repeat thereby voiding the keyboard
logic. When such an attempt occurs, as soon as the
keys are released and the bounce delaY'is timed
out, the idle key reset enables the control logic.
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number of scan cycles beyond
bou nce out delay:::: 2
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Typical values for CR, that would fit most applica-tions, range from 0.001 J1F to 0.1 J1E
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FIGURE 3. Scan Logic of MM5704
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The Scan· Logic will sequentially interrogate each
key of the keyboard. It provides the timed interrogation pulses. The detection of a key closure is
accomplished by the ROM input control logic.
This results due to the Rand B line being com-·
bined in an AND condition at the input to the
ROM control logic. The rate at which the keyboard is scanned is basically determ ined by the
clock input. Provision has been made internal to
this logic block to compensate for the various
capacitive loads that different keyboards might
present. This is a programmed feature. The scan
logic is shown in greater detail in Figure 3. It is
designed to sequentially scan 32 keyboard switches
in a 4 x B matrix as shown in Figure 2. The T lines
enable each of the four quadrants in sequential
fashion. The B lines are then used to sequentially
decode the B R lines at the ROM input. As the
A counter changes from state N to N+1 a programmable delay times out before the B counter
is allowed to decode the R lines within the quadrant. This delay is necessary to allow the T line to
charge the capacitance, associated with that quadrant of the keyboard switch matrix, to its full
value, and discharge the capacitance associated
with the last quadrant to be scanned.
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FIGURE 4. Housekeeping Logic of MM5704
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The delay required to avoid switch bounce is
accomplished through the use of the E counter.
This counter is incremented each time the M
counter completes a cycle. The E counter will
continue to advance until it counts out its programmed modulus at which time all switch bounce
is a thing of the past and the system is allowed
to accept the· initial key closure as valid. When
the first key is released, the E counter is again set
to its initial state and allowed to advance to its
terminal state. Upon reaching its terminal state for
the second time, when all switch bounce associated
with the first key release is over, the reset procedure for the "1 st character" and "busy 1"
latches will take place; The modulus of the E
cou nter may be varied to accommodate the switch
bounce times of the various switches that may be
used with this device. This is a parameter specified
by the customer. The modulus of the E counter
may be anything from 1 to 15.
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If a second key is depressed, while the first key
is held down, a sequence of events very similar
to that already described will occur. The basic
differences are that detection of 1he second key
will occur as a function of the "any key" signal
and the M counter not equal to O. The data ready
signal, from the first key closure, must have been
serviced by the system. Otherwise, this is an alarm
condition (two keys depressed simultaneously).
After transmission of the first key data and detection of the second key depression, the "2nd character" and "busy 2" latches will be set. The E
counter will inject its delay and the system will
acknowledge and transmit the second character.
Should the system be processing two key closures
and receive yet a th ird, the alarm latch will go
true. The third key depression is detected when
the "any key", M =1= 0", and "second chClracter" in
process" signals occur simultaneously. When the
alarm latch goes true, a signal may be transmitted
to the rest of the system on the data bus. The
alarm latch is reset through the use of the clear
key or by a reset pulse on the data bus.
The remainder of the housekeeping logic accepts
the input signals from the data bus .and transmits
data out on the bus at the proper time. The timed
sequence for the data bus associated with this
device is shown in Figure 5. We have already
discussed the nature of the keyboard alarm, character ready, and Xmit key signals. The alarm set
and reset signals are inputs from the rest of the
system that cause or remove the alarm condition.
The test input is for testing purposes only. It is
used to speed up the testing of this device when
the inputs to the device are generated from controlled (bounce free) sources. Therefore there is
no need for the normal system delays.· The system
could conceivably be used by the O.E.M, manufacturer for incoming receiving inspection, just as
the factory uses it. A more exact understanding .of
its use should be acquired from the factory before
it is used.
The static Xmit inputs are used to cause the keyboard interface to deliver the data stored in the
static switch holding register at the immediate
next appropriate time. There are four of these
static Xmit input pulses to permit use of up to
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FIGURE 7. ASCII Keyboard Encoder Using the MM5704
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command. This will cause the keyboard to send
its data from the keyboard shift register out onto
the data bus (microinstruction) during time slot 22
through 30 immediately following the receipt of
the transmit command. The data bits are received
by the T & C chip. The static switch information,
from the keyboard, is handled in a similar manner
by the system. It is the intent of this section to
only deal with the interaction of the KI chip with
the rest of the system. Therefore, a more detailed
treatment of the operation beyond this point
belongs in a description of the T & C chip, as
related to MAPS.
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2
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THE KEYBOARD INTERFACE ELEMENT
AS A STANDARD ASCII ENCODE SYSTEM
The MM5704 may be used quite conveniently in
applications other than as part of the calculator
chip system for which it was designed. To illustrate
how this may be done, a small keyboard system
was designed to perform the keyboard to ASCII
encoding function. Only one of the MM5704s
was requ ired to provide for all 128 characters in
the ASCII 7-bit communications code. This system
is illustrated in Figure 7.
258
A two phase clock must be generated and a master
counter designed to operate from the clock system. A DM8850 (9601) is used to drive a JK
flip-flop in the toggle mode of operation. This
forms a master clock that has an equal duty cycle.
One eight bit shift register and one SN74107 is
used to form a twisted ring counter. This type of
counter was chosen because of the ease with
which its states maybe decoded. One and 1/2 quad
2 input NAND gates are used to decode the
counter outputs into the discrete time slots required for the bit serial operation of the KI.
Because there is no need to concern ourselves
with anything other than the time slots required
to operate the KI chips, the time slots have been
reorganized and the word length shortened. This is
more clearly defined and illustrated in Figure 8.
The cycle marker signal is generated by setting a
latch at time 0 and resetting it at time 1. eM is
only used, in this system, by the KI chip.
The keyboard switch entry operation is accomplished exactly as described in a previous section
of this application note. The KI chip will interrogate the keyboard switch matrix. The alpha/
numeric control is accomplished externally by a
Toll
2
3
4
I5I6 I7I8
9 10 11112113114115116117118 191 0 1
»
z
1
I
c.n
U-
CML
XM1TKEY JL
N
RESET XM1T LATCH
CHARACTER READY
FIGURE 8. ASCII Keyboard I/O Time Slots
mechanical latch on the keyboard. If the keyboard
should lack this facility, an integrated circuit latch
could be added to perform this function.
slot 11 and ending with time slot 18 (8 bits long).
The Xmit latch will automatically be reset at time
T2. The generation of the Xmit latch will automatically be reset at time T2. The generation of
the Xmit key signal at T1 also causes another
latch to be energized (prepare for data). This latch
will enable a gate which at time T11 (the beginning
of the data word) will set a clock control latch.
This action enables the clock to the output shift
register for 8 clock pu Ises. The clock enable latch
is reset at time T 19. The eight clock pu Ises to the
shift register will permit the entry of the data
coming from the KI pi bus and accomplish the
serial to parallel conversion. At time T19, the data
prep. latch is reset.
At character read time (T9), the data bus (pI) is
gated to an RS flip-flop. For the sake of illustrating
the action sequence, let's assume that a character
ready (T9) signal appears on the pi data bus and
the Xmit latch is set. The data bus line is the data
input to an eight bit shift register. This shift
register is used to perform the serial to parallel
conversion. Nothing further occurs until the next
word cycle is initiated and time slot 1 is reach~d.
The Xmit flip-flop has enabled a gate that will
generate the Xmit key signal at T1 and place this
on the J,ll bus. This will be received by the KI chip
and trigger the transmission of data from the keyboard holding shift register beginning with time
::l
r+
CD
...
.....
Q)
n
The character and control codes associated with
the KI device are illustrated in Table 1. The con-
CD
::l
"
TABLE 1. ASCII Keyboard Assignments
b7 =0
b6 =1
0
1
SP
1
2 "
3 .#
4 $
5 %
6 &
7
8 (
9 )
10 *
11 +
12
13 14
15 /
16 0
17 1
18 2
19 3
20 4
21
5
22 ()
23 7
24 8
25 9
26 :
27 ;
28 <
29 =
30 >
31 ?
~
C"
b7 =1
o
CON.
b6 =0
UC
b6 =0
LC
b6 =1
N+1
S04
STX
ETX
EOT
ENG
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
Sl
DLE
DCl
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
@
\
a
b
c
d
e
T4
T2
T3
T3
T2
f
T2
T2
T2
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
9
h
i
j
k
I
m
n
0
P
p
Q
q
R
S
T
U
V
r
s
t
u
W
v
w
X
Y
x
y
Z
[
z
\
:
1
.-..
-
!
I
~
DEL
...
c.
Q)
T1
T1
T2
T2
T3
T3
T3
T4
T4
T1
T1
T2
Tl
T1
T3
R1
T3
Tl
T3
T4
T4
T4
T4
T4
R6
RO
R4
R2
R2
R2
R3
R4
R5
R7
R6
R7
R7
R6 ..
R5
RO
R1
RO
R3
R1
R4
R6
R3
R1
Rl
R5
RO
R2
R3
R4
R5
R7
b7 =1=Alpha
b7 =0=Numerics
en
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LC=alpha • b6= 1
UC=alpha • b&",O
r+
CD
Numbers=Numerics. b6=1
Control=Numerics. b6=0
(I)
3
~
Key Legend
example
259
en
E
...,
Q)
en
>
en
TABLE 2. American Standard Code for Information Interchange
"'C
..,;
co
0
b7
o
bs
r----.
.Jl
>
Q)
Bit s
~
Q)
CJ
....CO
~
...,
Q)
c
0
b4
b3
~
b2
b1
~
!
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
~
ROW
~
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
1
0
0
b5
t
c
0
0
0
1
1
0
1
2
3
NUL
SOH
STX
ETX
EaT
ENO
ACK
BEL
BS
HT
LF
DLE
DCl
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
SP
!
"
0
1
-
VT
FF
CR
SO
SI
#
$
%
&
2
3
4
5
)
6
7
8
9
*
+
:
;
(
<
-
=
>
/
1
?
1
1
0
4
1
1
0
0
1
5
@
P
A
B
C
D
E
F
G
H
I
0
J
Z
K
L
M
N
a
[
R
S
T
U
V
W
X
Y
\
1
.-.
-
1
1
0
6
7
a
b
c
d
e
f
g
h
i
j
k
I
m
n
q
p
0
r
s
t
u
v
w
x
y
z
I
:
I
~
DEL
This cod~d ~haracter set is to be used for the general interchange of information among information processing systems,
commUnication systems, and associated equipment.
trol codes are identical with the numerics section
of this device, except that bit b6 is a logic I/O"
instead of "1". The lower case letters are the same
as the capital letters (alpha section) except that
bit b6 is a logic 1/1" instead of "0". A glance at
the 7-bit ASCII standard MAPS (Table 2) will
show this to be consistent with the accepted
standard. The manner in which this is implemented
in our stand alone system is as follows: When the
control key is depressed bit b6 is slaved low in the
output of the serial to par.a.llel shift register, then if
the numeric characters are being generated by the
KI, control codes will result in the output of the
shift register. If character key $, for example, was
depressed, the resulting data code from the serial
to parallel converter would be modified from
01001000 ($) to 00001000 (EDT).
N
Ln
I
Z
«
The features of the KI chip will permit a more
elaborate system than this, but this is all that is
required to accomplish the use of the KI chip into
a bipolar system. The total parts count is as
follows:
11211241-
260
MM5704·
DM8850
SN74107
MH0025
DM8800
DM8570
DM7400
SN7404
PROGRAMMING THE KEYBOARD
INTERFACE CHIP
Within this device, there are nine areas that may be
specified, or programmed, by the customer. The
largest of these is the encoding ROM with its 64
9-bit words. The ROM is actually programmed
during the process with a masking step that either
leaves or removes gate oxide from a given node
depending upon whether a 1 or 0 is desired from
that node. To assist in programming the modulus
of 0 and E counters, which may vary from 1 to
15, vital information pertaining to keyboard performance is required. This information will enable
the KI chip to overcome T line delays and switch
bounce as explained in an earlier section of this
article. The 0 counter clock may also be specified
to be either () in or CM. The fifth area to be specified as the static switch recognition code. If more
than one chip is used in any given system, each
chip must be given a unique internal code that will
enable it to respond when the system calls for
static switch data from a specific device.
The sixth area to be defined is an option that will
permit the static switch information to be generated from normally open, or normally closed,
switch contacts. The seventh programmable function permits specifying the shift key switch as
either normally open or closed. Within the chip
itseif, these functions are implemented by inserting, or not inserting an inverter in the appropriate
place. Programmable function number eight per-
l>
2
I
c.n
Figure 9 is a copy of the form used to manually
program this device. Because a great deal of the
actual process involved in programming this device
is accomplished with' the use of a computer, a
normal computer input such as I BM cards may be
submitted by the customer to program this device.
mits the user to inhibit or transmit the alarm pulse
on the JlI bus. Number nine specifies whether the
system will accept or reject, set and reset alarm
pulses from the JlI bus. These latter conditions
result from making or not making the appropriate
internal connections.
II N
National Semiconductor Corporation
IlL~ 2900 Semiconductor Drive, Santa Clara, California 95051
........ (408) 732-5000/TWX (910) 339-9240
N
KEYBOARD INTERFACE PROGRAM SHEET MM5704
NAME:
DATE:
CUSTOMER PRINT OR ID NO.
ADDRESS:
PURCHASE ORDER NO.
CITY:
STATE:
ZIP:
AUTHORIZED SIGNATURE
PHONE:
TOTAL KEY MATRIX CAPACITANCE
MIN
TYP
MAX
UNITS
FOR NATIONAL SEMICONOUCTOR USE ONLY
1-------~_+_~~f---~+---~~-+--~~-._,_~~~___,_~~--___,~~_,_____1
pF
COUNTER
PROGRAM
MHz
CLOCK FREQUENCY
DRIVING
FUNCTION
TIMING
UNITS
KEY BOUNCE 'OELAY
D COUNTER
kHz
CYCLE MARKER FREQUENCY (CMI
_ _ ~~
MODULO
_~
____ ~_________
CASE SHIFT CONTROL (CSI
NO
~
E COUNTER
______ ..L~~~+_~~~~L-~~~.L..~~~....L.----.JL-_____i
Upper Case Logic
Level + -
NC
COMMENTS-
--
STATIC KEY FORM
~----~----
KEY
IDEN·
TITY
De::--G 0
r,c
NO
SCAN
LINE
T
R
20
_NO~ 130 40
.. _.. L
_. __.-
PIN NO.2 (+1
o
PIN NO.2 1-1
-KEY
IDEN·
TITY
:::l
~~~-'_+~'-~'-~'--'~-T~-'--'~T---~~'---1~--'~'-~'-~'--'~-'~-'-~'-~
f-~__+___l__-+~+_--+-----'---
"
-- --f_-
----t---
(1)
--
f-~+_+_+_~+--
en
...
"'C
ca
(Tx, Rx) is specified by card number and output
digit location. Only the ROM portion of the
keyboard interface chip may be programmed. All
other programmable features must be specified
in another fashion.
o
.Q
>
Q)
~
TABLE 3. Computer Programming Format
c
Q)
u
ca
...
..,
L.C.
~
Q)
c
U.C.
R7
R
R5
Rl
R2
R3
R4
R6
xxx
xxx
xxx
xxx
xxx
xxx
xxx
T2
T3
T4
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1st Card
2nd Card
3rd Card
4th Card
T2
T3
T4
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXy-
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
5th
6th
7th
8th
r
r
COlumnl~
Example (for column 1)
Number R7, T1
Bit 8
Output Conversion Example
256
Bit 0 (1st out)
o
0
128
64
0
32
16
0
8
4
2
2
4
8
32
256
302
L.C.
U.C.
N
In
I
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<
262
= lower case
= upper case
Card
Card
Card
Card
»
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I
Application Notes
C1I
C1I
OCTOBER 1971
r-
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~
."
~
CD
J:2
C
CD
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LOW FREQUENCY OPERATION WITH DYNAMIC
SHIFT REGISTERS
o
"C
CD
~
Q)
~,
o
::l
In many dynamic shift register applications, it is
advantageous to operate the circuit at low clock
frequencies or in clock burst modes where high
frequency clock rate periods are followed by long
intervals in which the clocks are absent. To insure
that his system will operate correctly under these
conditions, the designer should be aware of the
limitations of the type of shift register he is using.
There are two basic forms of dynamic shift register
cells: the ratio less and the ratio. The ratioless
circuit of Figure 1a is based on a capacitor precharge concept. During 1>IN clock time, node B is
precharged by transistor Q3; i.e., Q 3 is turned on
by 1>IN, creating a low impedance path from node
B to V GG which charges the node capacitor C2 to
a negative voltage. Data is coupled at the same time
through transfer transistor Q 1 to node A, the gate
of Q2. If the incoming data is a positive or "0"
level, Q 2 will be in a high impedance off state, and
node B will charge to a negative voltage one threshold more positive than the 1>IN clock amplitude.
When 1>IN returns to a positive level. Q 3 is shut
off, isolating the precharged voltage of node B.
The stored charge of node B, coupled with an
additional increment contributed by C4 , redistributes between nodes Band C when the 1>0 UT
clock turns on transistor Q4. The redistributed
charge develops a negative voltage" 1" level across
C3 which becomes isolated when 1>OUT returns to
a "0" level. The "1" level turns on 0 5 , resulting
in a low impedance path between the output of the
cell and Vss, establishing a "0" level at the output.
r+
::r
C
<
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Q)
3
(i'
rn
::r
~
r+
In the ratioless cell, there are two nodes which
become isolated from any charge replenishing
source during normal operation of the circuit:
nodes Band C. These are the nodes which establish
the low frequency limitations of the cell. In most
designs node C, the gate of the logic transistor Q5,
is the limiting node because total capacitance is
less. If we had assumed the initial data coupled by
Q, during rf>IN to be a "1" level, then node A
would of course be the limiting node of the cell.
OUTPUT
Vss
FIGURE 1a. Ratioless Dynamic Shift Register Cell
263
Voo
...
t--o 4>.N
\l,N
1
'to-
.s::.
Ul
" , , - - 0 OUTPUT
"~
E
as
c
>
Vss
C
.s::.
...
FIGURE 1b. Ratio Type Dynamic Shift Register Cell
..
c
o
as
DATA INPUT
"
~
Q)
C-
O
>
(.)
c
Q)
j
cr
Q)
~
u..
~
o
...I
LO
LO
\lOUT
CLOCK
I
Z
«
_ _ t"dt
DATA OUTPUT
1.5V
Ipd}.-
'-_ _ _ _ _ _ _ _---J
1.5V
FIGURE 2. Timing Diagram For Two Phase Dynamic Shift Registers
The ratio dynamic shift register cell of Figure 1 b
has only one isolated node which limits minimum
frequency operation. It, like the ratio less cell, is
the gate node of the logic transistor. The ratio cell
does not rely on stored precharge to establish a
"1" level on a succeeding logic gate mode. If a
"0" level had been transferred to node A of the
ratio cell by 0 1 during
Z
I
CJ1
CJ1
....
o
(1 )
OUT
Obviously the lowest operating frequency can be
attained when TIN and TOUT are each at their
maximum limit and therefore equal. This says that
for minimum frequency, 50% clock phasing should
be used, i.e., the clocks should be equally spaced
within the bit time.
The ratio cell has a similar storage requirement,
but with one difference. During the time the transfer clock (q,OUT in Figure 1b) is on, a source of
charge is available to node C through the ON
transistors 0 3 and 0 4 , assuming O2 is OFF.
Therefore, charge must be stored on the critical
capacitor C2 only after the transfer clock has returned to a "0" level, and isolated the node. This
required storage time is usually referred to as Clock
Phase Delay Time (q,d). The phase delay time between the trailing edge of q,IN and the leading
edge of q,OUT is q,d; the time between the trailing
edge of q,OUT and the leading edge of q,IN is (Pd
(Figure 2). Minimum clock operating frequency is:
Therefore Partial Bit Times and Clock Phase Delays
will be a definite function of temperature. Figure 3
shows a curve for Partial Bit Times as a function of
temperature for a typical shift register using a
ratio-less cell. Figure 4 gives the corresponding
minimum operating frequency versus temperature
for two cases: when TIN = TOUT (50% clock
phasing), and when one of the Partial Bit Times is
minimized, the other maximized. Minimum Partial
Bit Time is:
~
-n
~
(1)
.c
c
(1)
:J
(')
<
o
"tS
(5)
(1)
Any Partial Bit Time between minimum and maximum at a given temperature can be used. The
minimum clock rate would be calculated using
Equation 1.
:J
T(MIN)
= q, PW (MIN) + q,tr + q,tf + q,d(MIN)
~
m
~.
o
-.
r+
':1'
o
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m
100
]
"-
w
:;;
~
3
-,....
10
c:;"
,2
Z
en
..=
assuming clock rise and fall time«
~
q,pw.
x
1.0
':1'
'"
....
:;;
Optimum low frequency operation can be obtained
when the clock pulsewidths and phase delays are
maximized and made equal. In most cases this
would mean 10 J.ls clock pulsewidths and 50%
clock phasing. For power or system application
reasons it is usually not convenient to use such
wide pulsewidths, and the minimum clock frequency is simplified to
r+
I'.
0.1
-60
-20
20
60
100
140
AMBIENT TEMPERATURE ("C)
FIGURE 3. Maximum Partial Bit Time vs
Ambient Temperature
(3)
~
10
.,;:
Maximum Partial Bit Times and Clock Phase Delays
for a given circuit are' a measure of the ability
of the critical nodes within the cell to store a
minimum voltage level. Charge is usually lost due
to leakage currents associated with the semiconductor junctions of the nodes. The total reverse
leakage current for a p-n junction is the sum of
three components; the bulk diffusion current,
charge generation current and surface leakage current. Within the normal operating junction temperature range of MOS shift registers (-55°C to
150° C), the charge generation current is the primary component of leakage. Charge generation is
usually attributed to recombination centers within the depletion layer of the junction. Leakage
current generated in this manner is usually approximated by the expression
IL
:::: KT3/2 € -
7020/T
(4)
i
T'N or TOUT = MINIMUM
I%" V
1.0
~
""
~
TIIN=~OUI- - -
... v
Co>
0.1
~
:;;
z
1 I
:i 0.01
-60
-20
20
60
100
140
AMBIENT TEMPERATURE ("C)
FIGURE 4. Minimum Clock ·Frequency vs
Ambient Temperature
If the shift register utilizes a ratio cell, a curve
identical to Figure 3 could be used to obtain maximum Clock Phase Delays for any required temperature. Equation 2 or Equation 3 could then be used
to calculate minimum clock frequency at that
temperature.
265
The shift register user can often increase his margin of safety when operating at low frequency, or
for long periods of time with the clocks stopped,
by designing the system with that operation in
mind. The ambient operating temperature of the
registers should always be minimized. The cell requires a minimum voltage at the critical node to
operate, and the time to discharge the node to that
value is dependent upon the initial voltage, as well
as capacitance and leakage:
...,
'to-
J:
f/)
.~
E
«S
C
>
C
...,
to stay away from very high supply voltages. When
both the clock driver reference voltage and V GG
or Voo are the same supply, the best tradeoff is
toward the higher end of the specified range, however. One other consideration which applies during
operation at any frequency, but particularly at low
frequency, is excursions of the clock line more
positive than Vss. This forward biases internal
junctions which results in parasitic PNP transistors .
If the collector of the parasitic PNP happens to be
a critical node, the circuit will fail. Because critical
nodes are often closer to the minimum required
voltage during low frequency operation, registers
are usually more sensitive to positive clock spikes.
TIN or TOUT for ratioless cells;
J:
d or d for ratio cells
Total capacitance at critical node
c
o
VINITIAL
.~
«S
~
CI)
C-
Voltage at critical node immediately
after isolation of that node by transfer clock.
O
Minimum voltage required at critical
node for operation.
>
I L = Total leakage current at critical node.
CJ
C
CI)
The initial voltage can be optimized in two ways:
by using the highest clock amplitude possible and
by allowing something greater than minimum clock
pulsewidth to insure that the maximum amount of
charge is coupled to the node (and in the case of
the ratioless cell, that the maximum precharge
voltage is obtained before transfer). A high value
of V GG or V oo , the negative supply voltage, increases on-chip power and therefore junction temperature, as well as increasing the minimum required node yoltage. It is a good idea, therefore,
::l
C'
CI)
~
LL
~
o
...J
LD
LD
I
Z
c:(
266
When calculating temperature effects of a system
operating in the clock burst mode, the designer
must remember that power dissipation in the shift
register is approximately double at 2.5 MHz what
it is at 100 kHz. High frequency bursts will heat
the chip, causing high junction temperatures which
reduce the time the clocks can be off.
SUMMARY
Dynamic shift registers can be operated at very
low clock rates if manufacturers data sheets are
consulted and the proper clock phasing is used.
Added margin can be designed into systems by
keeping clock amplitudes high, the clock pulsewidths 10 to 20% wider than specified minimums,
power supplies low and temperatures as low as
possible. Beware of circuit board hot spots which
increase the temperature of individual packages,
or extensive interlead coupling or ringing which
could result in positive clock spikes.
»
z
I
Application Notes
CTI
-.....I
JANUARY 1971
AMERICAN AND EUROPEAN FONTS IN
STANDARD CHARACTER GENERATORS
Ten popular American and European 64-character
subsets for displays and printers are now available
from National as single-ch ip, standard character
generators. These parts, listed in T abl e 1, are sold
off-the-shelf without a ROM masking charge.
The ROMs are static, bipolar-compatible types,
operating without clocks on standard power supplies. Rowand column access times are typically
450 and 700 ns respectively. An MM4240/MM5240
2560-bit ROM is used for the 5 x 7 horizontal-scan
fonts and an MM4241/MM5241 3072-bit ROM for
the 7 x 5 vertical-scan fonts. The M M4240 and
MM4241 operate at -55°C to +125°C and the
MM5240 and MM5241 at -25°C to + 70°C.
TYPE NUMBER
CODE
Input-output configurations and character formats
for the ROMs are shown in Figures 1 and 2. Application Note AN-40 The Systems Approach to
Character Generators gives examples of line and
column address-control logic, and CRT and printer
operating techniques.
Note that each ROM has a chip-enable input to
permit multi-ROM operation with common control
logic. For instance, two horizontal-scan ASCII
character generators may be operated in tandem to
obtain upper and lower-case characters. In this
Ciilse, chip-enable would be controlled with bit b 6
of the normal 7-bit ASCII code, and its complement, b6 .
64-CHARACTER SUBSET
FIGURE
Horizontal Scan (5 x 7)
MM4240AA/MM5240AA
ASCII
Upper-case alphanumeric
3
MM4240AE/MM5240AE
ASCII
Lower-case alpha and symbols
4
MM4240ABU/MM5240ABU
Hollerith
Upper-case alphanumeric
5
MM4240ABZ/MM5240ABZ
EBCDIC-8
Upper-case alphanumeriC
6
MM4240ACA/MM5240ACA
EBCDIC
Upper-case alphanumeric (I BM)
7
G)
CD
Vertical Scan (7 x 5)
j
MM4241ABLlMM5241ABL
ASCII
Upper-case alphanumeric
8
MM4241 ABV IMM5241 ABV
ECMA
Upper-case A/N, Scandinavian
9
CD
MM4241ABW/MM5241ABW
ECMA
Upper-case A/N, German
10
Q)
MM4241ABX/MM5241ABX
ECMA
Upper-case A/N, general
European (French, British, Italian)
11
o...
MM4241ABY/MM5241ABY
ECMA
Upper-case A/N, Spanish
12
...
~
en
TABLE 1. Single-Chip, Standard Ho(izontal-Scan and Vertical-Scan Character Generators
IN~~~~
ICHARACTER
ADDRESS)
:
!
b,
IN~~~~
b,
ICHARACTER
ADDRESS)
8,
b4
b,
!
b,
8,
bJ
MM42401
MM5240
8,
b4
b,
ROW
OUTPUTS
hl
b,
OUTPUTS
8,8 2 8 3 84 85
000
001.
•
010 • • •
011 • • •
ROW
ADDRESS 100.
101.
••
•
110.
•
111.
•
CHARACTER FORMAT
FIGURE 1. HorizQntal-Scan Character Generator ROM
COLUMN
ADDRESS
INPUTS
4
8
COLUMN
COLUMN
8,
8,
8,
C
1
8,
1
j
8,
C,
Co
PROGRAMMABLE
CHIP ENABLE
:1
\
OUTPUTS
ADDRESS
gg~E~§
8,.
•
:;:•• I
OUTPUTS8, •
8,.
B,.
8,.
8,
••
•
•
•
CHARACTER FORMAT
I
FIGURE 2. Vertical-Scan Character Generator ROM
267
..
..
c::
..
....
..
en
..-o
HORIZONTAL SCAN FONTS
CQ
The subsets of 64 5 x 7 characters in the horizontal-scan fonts are the ones most commonly
used in low-cost TV and CRT raster-scan displays
and dot-matrix line printers.
Q)
Q)
(!J
MM4240ANMM5240AA contains the ASCI 1-6 pre~erred graphic subset, formed from ASCII-7 by
ignoring bit b6 . The remaining six bits form two
octal address characters. One is formed by the
three more significant bits, b 7 , b 5 and b4 , and the
seco nd by b 3 , b 2 and b 1 .
Q)
(,)
CQ
CQ
.r:.
(.)
Also, charac:ters 36 and 37 in ASCII (x3.4 1968)*
are respecti~ely a carat (or circumflex), and an
underscore. These are awkward in a video display,
so they are replaced by the more useful arrows.
(The arrows are related to characters in an older
teletypewriter set.) This font, shown in Figure 3,
is also described on the MM4240/MM5240 data
sheet (which should be referred to for operating
characteristics of all the horizontal-scan character
generators) .
"'0
cO
"'0
c::
..-
CQ
en
c::
..-en
c::
o
LL
. .....
........
..... ...... .....
··............ .....
..
.....
..
.
..
..
.
.
..
... ..... ..
. ..
.
..
..
.
..
. ........... ........
...... .. ....
....
c::
CQ
Q)
..
Co
··........ ...· .::: ...
..: .
:...::.
...:..:....::
:..: .....
: . :: -:: .
·· .. ·· . ....
• 13 •
• 15 • • 16 •
o
00
01
000001
02
000010
03
000011
04
000100
05
000101
06
000110
07
000111
001011
··1~··
001100
001101
001110
··~7··
001111
,
:::s
w
III
00l1l0Q
"'0
C
.~.
.~.
001010
i···: :...: i···: ·:... ··i··: ::..:! :
i···~:· i·.: ie:: •..• : : : ••• :•••:
CQ
.~
?2.
·2~·
2~
.~.
2~
·...·....
........ ... .. .... ...· .:...
..
.
.. ·:... ··· ..1 ·!. ..·
· . .. ......
"
.:.. :: :... ::
··.. :i..i: ::;:.
:..;: ;::.: ..
·. ...
.
...:.....:.. ..
..
i·· ·· .....
.
·
·· .·· . .. .... ··
·...: .·i I:::· .... ....::
... :..::. ..........
: ,.... .
··!..••··· .....··· :...........: .....
:
··............: .........·· ..:: ..::.: .···· ·..··. ·..:·
· · ·· · ·
c::
]0"
..
CQ
.~
Q)
E
(')
Q)
N
a>
en
Vss
TOP VIEW
FIGURE 1. Dual Shift Registers
Up to metal masking, wafer design and fabrication
are standardized. No time is lost-or money spentin developing custom arrays or tuning up the
process. Automatic test systems further reduce
turnaround time and production costs.
Programming the metallization mask mainly involves routing signal connections past selected
storage cells to adjust total register length to the
desired number of cells. Wire-bonding changes
provide output tap options.
DUAL REGISTER DESIGNS
Basically, each of the variable-length types is a
dual register (Figure 1 and Table 1A).
An MM4019/MM5019 chip is similarly organized,
except that MA and Ms are 40 bits and PA and
Ps vary from 0 to 216 bits. Again, lengths may
be unequal, such as 240 bits in the A half and 136
bits in the B half.
Clock and supply line pin locations are standardized, but I/O pinouts are selectable. The I/O
terminals on the chip may be bonded to package
pins which are more convenient for the PC board
layout. For example, a couple of board feedthroughs might be eliminated by bonding -the A
register input to Pin 7 (rather than Pin 1) if data
comes in from the right and ex its on the left. Or,
A and B could share an input pin when they have
the same signal source.
:lJ
a>
CO
en
r+
a>
~
TABLE 1 Register Length Options
MM4007/MM5007
M
(BITS)
P
(BITS)
MM4019/MM5019
TOTAL
(BITS)
M
(BITS)
P
(BITS)
TOTAL
(BITS)
40 to 256
A. DUAL REGISTERS
A Register
20
Oto 80
20 to 100
40
B Register
20
Oto 80
20 to 100
40
o to 216
o to 216
MA + Ma
PA + Pa
MA +Ma
PA + Pa
80
o to 432
40 to 256
B. SINGLE REGISTERS
40
o to 160
40 to 200
80t0512
C. TAPPED SINGLE REGISTERS
Total register length same as single registers with tap locations determined by either half of the dual registers.
275
SINGLE-REGISTER OPTIONS
Since clock rates are synchronized by the common
clock inputs, the registers may also be serially
connected inside the package, as diagrammed in
Figure 2. One output is internally connected to
the Other input.
This extends the maximum length of an MM4007/
MM5007 to 200 bits and the MM4019/MM5019
maximum to 512 bits. However, each half still
has the same minimum, so the minimums become
40 and 80 bits, respectively (Table 1B). Again,
the customer specifies the most convenient I/O
pin connections.
OUT~~!
2
6
OUTPUT B
6
OUTPUT
TAP
Vss
TOP VIEW
FIGURE 3a
NC
OUTPUT A
2
TOP VIEW
FIGURE 3b
FIGURE 3. Output Tap Options
Vss
TOP VIEW
FIGURE 2a
OPERATING CHARACTERISTICS
All specifications, except bit lengths, are the same
as those of other MM4000/MM5000 series dynamic
shift registers with the same number of I/O stages.
Clock-line capacitance, power dissipation, as well
as other AC and DC parameters, are independent
of the lengths programmed. This is accomplished
by standardizing clock and supply wiring patterns
to achieve minimum turnaround time and cost.
Vss
TOP VIEW
FIGURE 2b
FIGURE 2. Single Registers
Going to the output tap designs of Figure 3
takes only one more wire bond; from the first
register output to any available pin. Tap locations
are selected by specifying the bit lengths of each
of the dual registers. For example, an MM5007
105 bits long may be tapped at any stage from
20 to 85 bits. Generally, this flexibility makes
input taps unnecessary-an output at 29 bits in
a 105-bit register usually serves the same purpose
as an input at 76 bits.
276
The MM4007/MM5007 and MM4019/MM5019 are
fabricated using a low-threshold, p-channel enhancement-mode technology developed for the
MM4000/MM5000 series of registers. This means
that they are bipolar compatible, sensing TTL or
DTL data without input pull-up resistors and
driving TTL or DTL loads without output pulldown resistors. They operate on standard +5V
and -12V supplies. The clock frequency range
is also the same, from 300 Hz to 2.5 MHz,
guaranteed.
Either TO-99 or dual-in-line packages may be
specified. MM4007 and MM4019 operate at -55°C
to +125°C. MM5007 and MM5019 are commerical
types, specified for -25°C to +70°C.
o
~
c.
Ordering Information/
Physical Dimensions
CD
ORDERING INFORMATION
When ordering, indicate the appropriate
part number followed by the package
designation, e.g., MM5230D.
PACKAGE
DESIGNATION
N
D
Q
F
H
G
230
" n-:-i~
J.- "
SEATtNGPLANEq,
PACKAGE TYPE
1
170
~t-+
019
.500
:oi6TOO~M'N
Molded Dual-In-Line Package
Cavity Dual-In-Line Package
Quartz Lid Cavity Dual-in-Line Package
(MM4203/MM5203 only)
Flat Package
Metal Can Package
12-Lead Metal Can Package (Hybrids Oniy)
c
l4-Pin Flat Package (F)
4-Lead Metal Can Package (H)
3
CD
::l
r--.!-
tJ)
-I
M~~
ICJ187
651
o
_____
-T
310
'ioo,
___ ,
1
d-~T
R
~ ~
1
3
-T--T
.065. 130 ,.002
. ~; ~:
.010
i __
4
~---_l
III
·~r-'.001
tJ)
,150
005
::-T
085__
~
::l
-or
[=i'~;;f~
_1100
TVP
"1
rI --JIllf
~.040TVP.
.315
--'.025-
8-Lead
Metal Can Package (H)
8-Pin
Molded Mini-Dual-In-Line Package (N)
l2-Lead
Metal Can Package (G)
10·Lead
Metal Can Package (H)
T
ff-.08rO,........,:-r-r~r-:T-T:T"-r:-r~~r-'
L '_~_3
.030
175~
TYP
.010
_:
.89o~ ~ ~L
.
___
__
MAX
l!.J
I
~.140
r=lj'~-·
·:::CI
,]-
,.001.
L-.315 ',015------J
I -
- 015
I
. ,03 0 1
TYP
r-
---1.1001
I
~.OlD
" ,
.075
II_
-L
t--_,_ 010---j r- '
l6-Pin Molded Dual-In-Line Package (N)
14-Pin Cavity Dual-In-Line Package (D)
T
~~~~~~~~~~~
I.'
I
7
l6-Pin Cavity Dual-In-Line Package (D)
8
l6-Pin Cavity Dual-I n-Line Package (D)
277
eI)
c
,-o
ei)
cGo)
E
c
1200--j
I '
ctI
2
3
(.)
R
eI)
>
.r::.
Il.
........
18-Pin Molded Dual-In-Line Package (N)
ctI
I
I
~mmmm~B
I
~.330
I
.010
040!.OlO
.190
TVP
-I ;~: I~
j l:~:
18-Pin Cavity Dual-In-Line Package (D)
...oE
'+-
C
1
C)
C
1-
...
"C
...
l~~~
Go)
I'
o
24-Pin Molded Dual-In-Line Package (N)
24-Pin Cavity Dual-In-Line Package (D)
T
1
~I'2~~'~91D~11121
-tr·"4
r-~~:~
.•
1.110
'
$V~~~~~~~~~VVl
~OT~O~~
-----1~O.017
24-Pin Cavity Dual-I n-Line Package (D)
24-Pin Quartz Lid Cavity Dual-I n-Line Package (Q)
278
j
------'-Rr--'-_
1--.300_1
c
12
....
r-------.~
.070 TVP
Definition of Terms
-I
Clock Repetition Rate: The range of clock frequencies for which register operation is guaranteed.
Data Output Voltage Levels: The output voltage
levels (logic VOL or V OH ) which the output will
assume under normal operating conditions.
Clock Frequency ¢f: The range of clock frequencies which register operation is guaranteed.
Maximum clock frequencies are dependent upon
minimum and maximum clock pulse width restrictions, as presented by the Guaranteed Operating
Curves.
Data Input Capacitance: The capacitance between
the data input terminal and ground reference
measured at 1 MHz.
Clock Delay ¢d: ¢d is defined to be that minimum
amount of time that must expire after ¢1 has
undergone a V tjJ L to V tjJ H transition and the start
of a ¢2 VtjJH to VtjJL transition. The same spacings
apply, when ¢2 preceeds ¢t .
Clock Pulse Risetime, trtjJ: The time delay between
the 10% and 90% voltage points on the clock pulse
as it traverses between its logic VtjJL and logic VtjJH
levels.
Output Source Current: The current which flows
out of the output terminal of the register when the
output is a logical High level. Conventional current
flow is assumed.
Clock Pulse Falltime, tftjJ: The time delay between
the 10% to 90% voltage points on the clock pulse
as it traverses between its logic V tjJ H and logic V tjJ L
levels.
'
Input Voltage Levels: The logical Low level, V 1L
or V¢L is the more negative level. This level is
generally referred to as a TTL or DTL logical "0"
and an MOS logical "1". The logical High level,
.VIH or V~H is the more positive level. This1level is
generally referred to as a TTL or DTL logical "1"
and an MOS logical "0".
Clock Control Setup Time, 'tcs: The time prior to
the clock Low to High transition at which the
clock control must be at its desired logic level.
Output Voltage Levels: The logical Low level,
VOL, is the more negative level. This is the state in
which the output is capable of sinking current.
The logical High level, V OH , is the more positive
level. This is the state in which the output is
capable of sourcing current.
Clock Control Hold Time, 'tch: The time after the
High to Low transition for which the clock control
must be held at its desired logic level.
VGG Current Drain: The average current flow out
of the V GG terminal of the package with the output open circuited.
Data Setup Time, tds: The time prior to the clock
High to Low transition at which the data input
level must be present to guarantee being clocked
into the register by that clock pulse.
Power Supply Voltage, VGG: The negative power
supply potential required for proper device operation; referenced to Vss.
Data Pulse Width, tdw: The time during which the
data pulse is in its VI H or V I L state.
Data Hold Time, tdh: The time after the clock
High to Low transition which the data input level
must be held to guarantee being clocked into the
register by that clock pulse.
Data Input Voltage Levels: The voltage levels
(logic V 1L or V 1H ) which the data input terminal
must assume to insure proper logic inputs.
til
Partial Bit Times TIN, TOUT: The time between
leading edges of clocks, measured at the V ¢H
levels. TIN is the time between the leading edge of
¢IN and the leading edge of ¢OUT. TOUT is the
time between the leading edge of ¢OUT and the
leading edge of H VL: The voltage
levels (logic "1" or "0") which the clock driver
must assume to insure proper device operation.
c:
o
....,
c:
Data Output Voltage Levels, VO H , VOL: The output voltage levels (logic " 1" or "0") which the
output will assume with a specified load connected
between output and Vss line.
.....(I)
c
Data I nput Voltage Levels, V I H V I L: The voltage
levels (logic "1" or "0") which the data input
terminal must assume to insure proper logic
inputs.
Control Release Time, ter: The maximum time
that a load command signal can be changed prior
to the VL to VH transition of the output clock,
0 UT, without affecting the data during bit
time tn'
Control Initiate Window: The time in which a load
command signal must be appl ied to affect bit time
tn- This time extends from the start of ter to the
start of tes'
Control Hold Time: The time that the load command signal must remain stable during tn bit time.
See control timing diagram.
logical "0": The logical zero voltage is the voltage state occurring near ground. At the output of
the device the logical zero voltage is guaranteed to
be not more than -1.0 volt under worst case conditions of power supply and ambient temperature.
The input requirements are guaranteed so that any
voltage up to -1.5 volts will be interpreted as a
logical zero. This implies a 0.5 volt noise immunity
for the logical zero state.
logical "1": The logical one voltage is the more
negative voltage state occurring near the negative
supply (VD D) value. At the output of the device
the logical one voltage is guaranteed to be not less
than -S.O volts under worst case conditions of
power supply and ambient temperature. The input
requirements are· guaranteed so that any voltage
more negative than -7.0 volts will be interpreted
as a logical one. This implies a 1.0 volt noise
immunity for the logical one state.
ACKNOWLEDGEMENT
The fol'lowing individuals have contributed to the authorship of
the application notes and MOS briefs in this handbook: Dilip
Bapat, Gene Carter, Don Femling, Bob Johnson, Dale Mrazek,
Richard Percival and Carl Ross.
National does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied; and National reserves the right, at any time without notice, to change said circuitry.
2S0
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