~~
,/
--
.yV
88
:0
82
~q.."
~'l~'::;1
I
V
< TA <; 125"C _
I
I
o
15
--
LM107: -55"C'; T A'; 125"C _
76
I
I
J
70
5
20
V
,....... V
--
LM107: -55"C <; TA <; 125"C
o
5
_~\~\~\l~"""'"
-
~q.."
~\~\~.::;
LM1J7: -55"C
V
94
~ ;/
".-
./
15
10
5
20
15
SUPPLY VOLTAGE (,VI
SUPPLY VJLTAGE (>VI
20
SUPPLY VOLTAGE (WI
LM307
OUTPUT SWING
INPUT VOL liAGE RANGE
VOLTAGE GAIN
20
20
r--
~
16
./
/
12
vo,,~ /
.....
,,/
./'VI,,\-J~./' V
--r--~-
,.",
./'
V V
......~".~\\"
V
V
10
~\~\~.::;
~:,.;.-'
'"
./'
./'
15
,.",
./
/
r- 'I
/~.'l-,,"--
./
O°C <; T A
? I--
< 70"C
--
__
~\~\~\l~
82
I---I---
~1---t-r--+--+~~~-~--r-
o"f -
10
15
SUPPLY VOLTAGE (±VI
SUPPLY VOLTAGE (±VI
SUPPLY VOLTAGE (!VI
TYPICAL PERFOFIMANCE CURVES
SUPPLY CURRENT
INPUT CURRENT
INPUT NOISE VOLTAGE
100
~
--
I--
e--
80
1A" J55"C
~T
i--r;;;ts"c
-
~
r--
0
.<>
4
3
LM
2r1
20
SUPPLY\lOL1AGE ('VI
- -
_r-LMl07-
BIAS
40
LM107
........- ~~ r--
-
N-..
0
0
-75
r
-50
-25
t-......
OFFSET
r-.
f'.
r->
-
r---..
,- -
" -to-
LM307
--
1-,,-
.-
-
J-i--->25
50
TEMPERATURE ("CI
75
100
125
100
100k
FREQUENCY (HzI
6·177
LINEAR INTEGRATED CIRCUITS. LM107/207/307
","'/i'!CAL PERFORMANCE CURVES (cont'd)
VOLTAGE GAIN
INPUT NOISE CURRENT
CURRENT LIMITING
~
15.0 ,...---.,...--..-----.--""T""""-""T""--..,
I\,
110
,,''\
'\
1"A-·SS" C _
100
90
~
----
~
-- i
/
A 25C
•
I
TA-125"C--=
5.0
"- ........
1--+--+--++--+-+-+-+--1
(~
I-
~
t-
I
80
10
5
IS
10
SUPPLY VOLTAGE (tV)
20
16
25
30
100
10
lK
FREOUENCY (Hz)
OUTPUT CURRENT (imA)
OPEN LOOP
FREQUENCY RESPONSE
LARGE SIGNAL
FREQUENCY RESPONSE
VOLTAGE FOLLOWER
PULSE RESPONSE
10
100
VS= :!.15V
VS=.!lSV
""
60
TA"25"C
TA = 25"C
r--....
-
~
40
~
~
\
~
100
lOOk
1M
IV
V
I
lK
\
f'. i'.r-.
10K
~
-
-6
OUTPUT
'"
TA"25"C
-8
lOOK
-10
-10
t'1jV-
0
Ie
20
30
40
50
60
70
TIME (",I
APPLICATIONS
INVERTING AMPLIFIER
R2
VIN'~'
2 3 +
-=-
6
VOUT
VOUT=*VIN
RIN
6-178
I /
r\
.. 2
FREQUENCY (Hz)
FREQUENCY (Hzl
'~L;~l
1\
\
1\
10
~NLT r-- -
r
= R,
NON-INVERTING AMPLIFIER
NON-INVERTING
AC AMPLIFIER
80
90
!ii!lnotiC!i
-=YOLT REGIlAIDRS
LINEAR INTEGRATED CIRCUITS
i ,~HGRjPTION
PIN CONFIGURATIONS
The LM 109 and LM309 are complete 5 volt regulators
fabricated on a single silicon chip. These regulators are
designed for local "on card" regulation to eliminate many
of the noisEl and ground loop problems associated with
single-point regulation. They employ internal current limiting, thermal shutdown, and safe-area compensation which
makes the circuitry essE!ntially blow-out proof. If adequate
heat sinking is providE!d, the devices can deliver output
currents in excess of 200m A from the TO-5 package, and
1A from the TO-3 package. In addition to their use as
fixed 5 volt regulators, these devices may be used with
external components 10 obtain adjustable output levels.
They may also be uSl3d as the power pass· element in
precision regulators.
;~1.1TURES
•
•
OUTPUT CURRENTS IN EXCESS OF 1 amp
INTERNAL THERMAL OVERLOAD PROTECTION
•
INTERNAL CURRENT LIMITING
•
NO EXTERNAL COMPONENTS REOUIRED
.~K$OlUTE
LM109
LM209
LM309
H PACKAGE
(Bottom View)
1.
Input
2. Output
3. Ground
ORDER PART NOS. LM109H/LM209H/LM309H
K PACKAGE
(Bottom View)
MAXIMUM RATINGS
Input Voltage
Power Dissipation
Operating Junction Temperature Range
LM109
LM309
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
1. Input
35V
Internally Limited
-55°C to 150°C
O°C to 125°C
-65°C to 150°C
300°C
2. Output
Case is connected to ground.
ORDER PART NOS. LM109K/LM209K/LM309K
fCHiVAUENT CIRCUIT
Q'9
D.
6.3V
6-179
LINEAR INTEGRATED CIRCUITS. LM109/309
(Note 1)
PARAMETER
CONDITIONS
TYP
MIN
Output Voltage
T
Line Regulation
T
Load Regulation
T
j
= 25°C
= 25°C
j
7V ':;;;;V
j
4.7
MAX
MIN
5.3
5.05
':;;;;25V
IN
LM309
LM109
4
4.8
UNITS
TYP
MAX
5.2
5.05
4
50
V
50
mV
= 25°C
TO-5
5mA':;;;; lOUT ':;;;;0.5A
20
50
20
50
mV
TO-3
5mA':;;;; lOUT':;;;; 1.5A
50
100
50
100
mV
Output Voltage
7V ':;;;;V
':;;;;25V
IN
5mA':;;;; lOUT':;;;; Imax
4.6
P
I
r--t-t-i----:~~§$§§§l
5.0
~
§!
I-
~ 4.51------+-'---t-----J~y_lr--·-+
0.5
I-----t-_If----f--_I---+---t-+''''''t-......j
~7=5~-5~0~-2~5~-~25-~50~~75~1~OO-1~25~150
JUNCTION TEMPERATURE -
°0~--2=5---~50~--~7~5---1~00--~125
'c
JUNCTION TEMPERATURE -
OUTPUT VOLTAGE
INPUT VOLTAGE -
V
OUTPUT NOISE VOLTAGE
OUTPUT VOLTAGE
5.1
1
-",
>
5.0
--
-
-
"~
V IN - 10V
-
V I N'10V
IL = 20mA
I---
i
'c
IL - 20rnA
--~
>
I
5.0
J:
.........
""""-
~
g
\
I-
:>
~ 4.9
5
~
'"
~
r'--.. .......
I-
0.1
§!
~
---
~
..
4.R
-75
-50
25
-25
50
76
100
125
0.01
150
25
'c
JUNCTION TEMPERATURE _
.-
50
75
JUNCTION TEMPERATURE _
126
100
lk
100
Hz
QUIESCENT CURRENT
QUIESCENT CURRENT
6.0
10
FREQUENCY -
'c
I
I
VIN - lOV
r--- r----
--
-g
I
6.5
... V
I-
z
Ie
Ie
a
I-
I
z
~
/
V
~
.:::::
~
~ ~,.qf"a~
\1) _
5.0
ei
1---- 4.5
-75
-50
-~
i
!Z
---.-
~~
~
5.01--4--+---1---+-+
~
~
-25
25
50
76
JUNCTION TEMPERATURE _
6-182
I 5.5 r--t-TI--=:±:::::~~:::;:;;:~
"._-
100
'C
126
150
20
INPUT VOLTAGE -
V
10k
DEFINITION OF TERMS
, AlVlrS
AVERAGE INPUT OFFSET CURRENT to COEFF - The
change in input offset current divided by the change in
ambient temperature producing it.
OUTPUT SHORT-CIRCUIT CURRENT - The maximum
output current available from the amplifier with :the output
shorted to ground or to either supply.
AVERAGE INPUT OFFSET VOLTAGE to COEFF - The
change in input offset voltage divided by the change in
ambient temperature producing it.
OUTPUT VOL rAGE SWING - The peak output swing,
referred to zero, that can be obtained.
COMMON MODE INPUT RESISTANCE - The resistance
looking into both inputs tied together.
POWER CONSUMPTION -- The DC power required to
operate the amplifier with the output at zero and with no
load current.
COMMON MODE REJECTION RATIO (CMRR) - The
ratio of the change of input offset voltage to the input
common mode voltage change producing it.
POWER SUPPLY REJECTION RATIO - The ratio of the
change in input offset voltage to the change in supply
voltages producing it.
FULL POWER BANDWIDTH - The maximum frequency
at which the full sinewave output might be obtained.
RISE TIME - The time required for an output voltage
step to change from 10% to 90% of its final value.
INPUT BIAS CURRENT - The average of the two input
currents at zero output voltage. In some cases, the input
current for either input independently.
SLEW RATE - The maximum rate of change of output
voltage under large signal condition.
INPUT CAPACITANCE - The capacitance looking into
either input terminal with the other grounded~
INPUT CURRENT - The current into an input terminal.
INPUT NOISE VOLTAGE - The square root of the mean
square narrow-band noise voltage referred to the input.
SUPPLY CURRENT - The current required from the
power supply to operate the amplifier with no load and
the output at zero.
TEMPERATURE STABILITY OF VOLTAGE GAIN The maximum variation of the voltage gain over the specified temperature range.
*;'{IULATORS
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at
zero volts.
DROPOUT VOLTAGE - The input-output voltage differential at which the circuit ceases to regulate against further
reductions in input voltage.
INPUT OFFSET VOLTAGE - That voltage
be applied between the input terminals to
output voltage. The input offset voltage may
fined for the case where two equal resistances
in series with the input leads.
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - The range
of voltage difference between the supply voltage and the
regulated output voltage over which the regulator will
operate.
which must
obtain zero
also be deare inserted
INPUT RESISTANCE - The resistance looking into either
input terminal with the other grounded.
INPUT VOLTAGE RANGE - The range of voltages on
the input terminals for which the amplifier operates
within specifications. In some cases, the input offset
specifications apply over the input voltage range.
LARGE-SIGNAL VOLTAGE GAIN - The ratio of the
maximum output voltage swing to the change in input
voltage required to drive the output to this voltage.
OUTPUT RESISTANCE - The resistance seen looking
into the output terminal with the outp'ut at null. This
parameter is defined only under small signal conditions
at frequencies above a few hundred cycles to eliminate
the influence of drift and thermal feedback.
LINE REGULATOR - The percentage change in output
voltage for a specified change in input voltage.
LOAD REGULATOR - The percentage change in output
voltage for a specified change in load current.
MAXIMUM POWER DISSIPATION - The maximum total
device dissipation for which the regulator will operate
within specifications.
OUTPUT NOISE VOLTAGE - The rms output noise
voltage with constant load and no input ripple.
OUTPUT VOLTAGE RANGE - The range of output
voltage over which the regulator will operate.
QUIESCENT CURRENT -- That part of input current to
the regulator that is not delivered to the load.
6-183
DEFINITION OF TERMS
~:'
7
iULl',.-rORS (Cant'd.)
REFERENCE VOLTAGE - The output of the reference
amplifier measured with respect to the negative supply.
to an input level just barely in excess of that required to
bring the output from saturation to the logic threshold
voltage overdrive.
RIPPLE REJECTION - The ratio of the peak-to-peak
input ripple voltage to the peak-to-peak output ripple
voltage.
STROBE CURRENT - The maximum current drawn by
the strobe terminals when it is at the zero logic level.
SENSE VOLTAGE - The voltage between current sense
and current limit terminals necessary to cause current
limiting.
STROBE DELAY - The time delay measured from strobe
to output threshold with a signal present exceeding the
input threshold.
SHORT CIRCUIT CURRENT LIMIT - The output current of the regulator with the output shorted to the
negative supply.
STROBE RELEASE TIME - The time required for the
output to rise to the logic threshold voltage after the
strobe terminal has been driven from the zero to the one
logic level. Appropriate input conditions are assumed.
STANDBY CURRENT DRAIN - The supply current
drawn by the regulator with no output load and no reference voltage load.
i DRS!Sf N;-.:f I NTE R fAC E
COMMON MODE FIRING VOLTAGE - The CM input
voltage that exceeds the dynamic range of the inputs with
strobe enabled resulting in the output switching states.
COMMON MODE RECOVERY TIME - The time from
the turn off of the CM signal to the analog input threshold
of the earliest sense line pulse signal that can be processed
normally. Processed normally refers to bi-polar signals
greater than or less than the input threshold with a corresponding proper output.
EQUIVALENT INPUT COMMON MODE NOISE VOLTAGE - The change in input offset voltage due to common
mode input noise.
LOGIC INPUT HIGH VOLTAGE - The minimum voltage
allowed at a bit control gate to hold the bit off.
STROBED OUTPUT LEVEL - The DC output voltage,
independent of input voltage, with the voltage on the
strobe terminal equal to or less than a minimum specified
amount.
SWITCHING SPEED - The time required to turn on the
least significant bit.
THRESHOLD UNCERTAINTY - With all sense amps
sharing the same input threshold less the uncertainty as a
"0". This includes unit to unit, power supply and temperature variations.
THRESHOLD VOLTAGE - The typical referred to input
voltage which determines whether an input is a "1" or a
"0". A signal whose magnitude is greater than the threshold
level is sensed as a logic "1" and a signal whose magnitude
is less as a "0"
ZERO SCALE OUTPUT CURRENT - The output current
for all bits turned off.
I
LOGIC INPUT LOW VOLTAGE - The maximum voltage
allowed at abit control gate to hold the bit on.
OUTPUT SINK CURRENT - The maximum negative
current that can be delivered by the comparator.
PEAK OUTPUT CURRENT - The maximum current that
may flow into the output load without causing damage
to the comparator.
PROPAGATION DELAY - The interval between the
application of an input voltage step and its arrival at either
output, measured at 50% of the final value.
RESPONSE TIME - The interval between the application
of an input step function and the time when the output
crosses the logic threshold voltage. The input step drives
the comparator from some initial, saturated input voltage
6-184
:'"ll'"HJNiCATIONS CIRCUITS
ACC DETECTOR SENSITIVITY - The ratio of the incremental differential DC voltage change at the ACC Detector
Output Terminals to the incremental change in peak-topeak voltage at the ACC Detector I nput Terminal for a
specified burst input level, with the local oscillator locked.
APC DETECTOR SENSITIVITY - The ratio of the incremental differential DC voltage change at the APC Detector
Output Terminals to the incremental change in relative
phase at the APC Detector Input Terminal for a specified
burst input level.
AVERAGE TEMPERATURE COEFFICIENT OF OUTPUT
VOLTAGE - The percentage change in output voltage
for a specified change in ambient temperature.
BANDWIDTH - The frequency at which the differential
gain is 3dB below its low frequency value.
·1.0
o
>
·2.0
·3.0
\
-4.0
-4.0
-3.0
-2.0
-1.0
V 1N (VOLTS)
All 2.500 series devices are manufactured with the P-channel
enhancement mode silicon gate process. A typical data input
structure is shown in Figure 1.
vee
f
~
0-----4
\
\
3.0
·5.0
-5.0
INPUT INTERFACE
INPUT
4.0
FIGURE 2
In actual practice, tying the TTL V,ce to the MOS Vee
will ensure maximum noise margin since the TTL output
levels and MOS input thresholds will track.
54/7400 TTL
Q,
OUTPUT
2
Figure 3(a) and (b) show a typical 7400 Series gate circuit
and transfer characteristic.
·voo
.---~~-...--o
Vee
'VGG
FIGURE 1
The input transistor exhibits the transfer curve shown in
Figure 2. The device is fully OFF at -1.8 volts or less (VGS)
and fully ON at -3.5 volts or more. To simplify the interfacing of TTL and 2500 Series devices, the source voltage
for the input transistor is specified at +5.0 volts. In practice,
this point is tied to the +5.0 volt TTL Vee supply. The required MOS input levels are then specified as positive levels
referenced to the TTL ground.
IN,
IN 2
0--...---'
0--+-_-'
OUT
~~------+--~--oGNO
FIGURE 3(a)
7-5
SILICON GATE TECHNOLOGY
54/7400 TTL
Vee = 5V i 5%
7.0
8.0
5.0
~
~
4.0
g
...
~
I-3.0
I--.
"\
5
1\
2.0
1.0
o
0.4
0.8
• EXTERNAL 10K
PUll-UP RESISTOR
\
1.2
FIGURE 4
2.0
2.4
INPUT VOLTAGE
8000 TTL
FIGURE 3(b)
Figure 5 illustrates a typical 8800 series output structure.
The output structure shown in Figure.3(a) is normally specified
as follows:
@
VCC = +5V ±5%
VOL = +O.4V maximum
@
16 mA sink
VOH = +2.4V minimum
@
400 IlA source
MOS devices require only negligible D.C. input current (approximately lilA), so the current available from the TTL
output is of no interest for steady state conditions. VOL is
perfectly compatible with the MOS offering at least 400mV
of noise margin in the 0 state. VOH however, is not sufficient to guarantee a 1 level to the MOS input since the TTL
VOH allows a VCC - VOH separation of as much as 2.85V
VCC = 5.25V, VOH = +2.4V; 5.25V - 2.4V = 2.85V).
Assuming a common VCC' this results in a virtual VOH
of 2.15V, far too low for MOS. In practice, the TTL VOH
wi II track V CC' rather than the opposite case just noted.
Also VOH will be higher than +2.4 at lilA IOH. However,
the TTL circuit is tested and guaranteed as in the example.
The 7400 TTL output structure will typically provide a
VOH approximately 1.5V (two Vbe drops) below VCC·
When the MOS and TTL VCC are tied, a 300mV noise
margin (1.8\/ - 1.5V = 0.3V) is obtained. If VCC is not tied
common, the worst case typical noise'margin is a negative
200mV. In other words, a satisfactory 1 input level cannot
be assured, even under typical conditions.
TO ASSURE A SATISFACTORY 1 OUTPUT LEVEL
FROM SERIES 7400 IN DRIVING SERIES 2500 MOS, AN
EXTERNAL PULL-UP RESISTOR SHOULD BE CONNECTED FROM THE OUTPUT TO VCC AS SHOWN IN
FIGURE 4.
7-6
FIGURE 5
The 8800 series circuit typically offers an unloaded output
voltage separated from V CC by one V be . Therefore the output level driving MOS will always be approximately 0.75V higher than the preceeding example for 7400 series circuits
- resulting in at least 550mV 1 level noise margin under any
conditions. Noise margin at 0 level is 400 mV, the same as
in the case of 7400 TTL.
Signetics guarantees 8000 Series TTL (See figure 6) VOH at
3.6V @ 101lA. Under worst case conditions, this results in
a minimum guaranteed 0 level noise margin of 400mV for
tied V cc. I f the' MOS and TTL V CC are not tied (may vary
independently), worst case guaranteed noise margin is
·150mV. This configuration requires a pull-up resistor.
WHEN VCC'S ARE TIED COMMON, SERIES 8000 TTL
IN FIGURE 6 WI LL INTERFACE DI RECTL Y WITH
SERIES 2500 MOS, WITHOUT THE NEED FOR AN EXTERNAL PULL-UP RESISTOR.
SILICON GATE TECHNOLOGY
GATES
FLIP-FLOPS
8808
Single 8-lnput NAND Gate
8815
Dual 4-lnput NOR Gate
8816
Dual 4-lnput NAND Gate
8821
Dual Master-Slave J-K Binary
8840
Dual Expandable AND-OR-INVERT Gate
8822
Dual Master-Slave J-K Binary
8848
Expandable AND-OR-INVHn Gate
8824
Dual Master-Slave J-K Binary
8870
Triple 3-lnput NAND Gate
8825
DC Clocked J-K Binary
Dual J-K Binary
8875
Triple 3-lnput NOR Gate
8826
8880
Quad 2-lnput NAND Gate
8827
Dual J-K Binary
8885
Quad 2-lnput NOR Gate
8829
High Speed J-K Binary
*See Note Below
FIGURE 6
*For devices not Iisted,addan external pull-up resistor as in the 7400 example(Fig. 4).
DTLlUTI LOGIC ®
those noted for Series 800 circuits.
Logic forms utilizing an internal passive pull-up resistor
{such ·as DTL) will interface directly with 2500 Series MOS.
WHEN VCC'S ARE COMMON, SERIES 2500 MOS MAY
BE DIRECTLY DRIVEN BY SERIES 600 DTL AND
SERIES 300 UTILOGIC CIRCUITS WITHOUT THE NEED
FOR AN EXTERNAL PULL-UP RESISTOR.
Utilogic is guaranteed te provide output levels equivalent to
2500 SERIES MOS-TTL INPUT CONSIDERATIONS (TTL Level data and clock inputs)
WORST CASE
EXTERNAL
DRIVING DEVICE
PULL-UP
RESISTOR(S)
WORST CASE
GUAR.
GUAR.
1 LEVEL
o LEVEL
NOISE MARGIN
NOISE MARGIN
Common VCC
8000(1) Series TTL
not req.
400
400
8000(2) Series TTL
10K
1300
400
1300
400
7400 Series TTL
10K
600 Series DTL (3)
not req.
400
400
600 Series DTL (4)
not req.
400
400
300 Series Uti logic (3)
not req
1300
400
300 Series Utilogic (4)
not req.
400
400
400
I ndependent V CC
All. TTL
10K
800
600 Series DTL (3)
not req.
550
150 (5)
600 Series DTL (4)
not req.
550
150 (5)
300 Series Uti logic
10K (7)
550
150 (5)
NOTES:
(1)
From List in Table I
FIGURE 7
(2)
Not listed in Table I
(3)
(4)
Passive Pull-up (resistor), ±10% power supply
Active Pull-up, ±10% power supply
(5)
Use ±5% DTL or Utilogic power supply to maintain 400 mV noise margin
(6)
(7)
From driving output to V CC
Certain Series 300 devices utilize a passive pull-up and require no external pUlluup.
7-7
SILICON GATE TECHNOLOGY
BARE DRAIN:
OUTPUT INTERFACE
TTL/DTL INPUT STRUCTURES
Standard TTL circuits employ the input structure shown in
Figure 8.
.
The bare drain output is the simplest structure and requires
an external pull-down resistor. Bare drain is used where
several outputs are to be tied together in a WI R ED-O R
configuration as shown in Figure 11.
TYPICAL TTL INPUT STRUCTURE
Vee
(
4K
IN
WIRED-OR CONFIGURATION OF
TWO BARE DRAIN DEVICES
o-__-..Ti
_
eLAMPOR
SUBSTRATE
DIODE
*
GND
FIGURE 8
DTL circuits employ the structure shown in Figure 9.
TYPICAL DTL INPUT STRUCTURE
DTL/TTL
3.4K
- - - - - ______ 1
4K
FIGURE 9
2500 SERIES OUTPUT STRUCTURES
Four basic types of output structures are used in the 2500
series:
1. Bare drain
2. Internal resistor pull-down
FIGURE 11
3. Push-pull
4. Three-state
See Figure 10.
TYPICAL 2500 SERIES OUTPUT CIRCUITS
+Vee
The external resistor is chosen to sink the j .6mA required
by a TTL gate. I n Figure 11, a 3.3K resistor is tied to the
VDD supply. The output voltage will be +OAV or less depending on the actual 101 of the TTL input.
When the bare drain device is ON, it represents approximately 500 ohms. For the circuit of Figure 9, VOH is approximately +3. 7V - more than sufficient to drive a TTL or
DTL gate. Bare drain 2500 devices are listed in Figure 12.
BARE DRAIN SERIES 2500 DEVICES
OUT
,V
IAI BARE DRAIN
(BI RESISTOR PULL-DOWN
FIGURE 10
7-8
DD
(el PUSH-PULL
2502
2503
2504
2505
2512
2518
FIGURE 12
2519
2524
2525
SILICON GATE TECHNOLOGY
RESISTOR PULL-DOWN
The second type of output has a pull-down resistor on the
chip. The 2507 and 2517 are examples of this. The 2517
has a 20K ohm internal resistor for interfacing with MOS.
Resistor pull-down series 2500 devices are listed in Figure 13.
The 2507 hasa7.5Kohm resistor, and if used in the WI REDOR configuration with another 2507 output, will drive TTL
directly as shown in Figure 14.
The advantage of this circuit is that no additional power is
dissipated in either state. Both states have low impedance
to the power supplies. Push-Pull output series 2500 devices
are Iisted in Figure 15.
PUSH-PULL OUTPUT SERIES 2500 DEVICES
2527
2521
[
2522
2528
2529
----------'-FIGURE 15
RESISTOR PULL-DOWN SERIES 2500 DEVICES
2507
2517
THREE-STATE
7.5K
20K
A disadvantage of the push-pull circuit is that paralleling of
the outputs is not possible because two low impedance
devices would be ON simultaneously directly across the
power supplies. To avoid this condition, a three-state output is used. The third state is an open output configuration
where both devices are OFF and is accomplished by using
an OUTPUT ENABLE line tied to the gates of both output
devices as shown in Figure 16. Three-state series 2500 devices
are listed in Figure 17.
FIGURE 13
PARALLEL CONFIGURATION
FOR 2507's
+5
1- -
-
-
-
-
-
-
-
-
-
-
- - ...
1
I
1
1
1
[==}
1
1
Vee
1
1
7.5K 1
1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ I1
DATA IN
~
+3.85V
DTL/TTL
r=,--~~----:
~
+O.BV
OUTPUT ENABLE
I
:
:
~5K:
1
-VDD
I
1 _____ - - - - - - - - -
·5V
FIGURE 16
FIGURE 14
PUSH-PULL
The third type of output structure used in the 2500 Series
isthe push-pull circuit shown in Figure 10c. In the push-pull
configuration, the gates of the two output devices are driven
from complementary sig l1 als such that only one device is ON
at a time. When the upper device is ON, the output is tied to
Vee through approximately 500 ohms. When the lower
device in ON, the output is tied to VDD through 5000hms.
THREE-STATE SERIES 2500 DEVICES
L
2501
2509
2510
2511
2513
2514
2516
FIGURE 17
Figure 18 summarizes the output configurations used on the
2500 Series circuits.
7-9
SILICON GATE TECHNOLOGY
OUTPUT CONSIDERATIONS FOR 2500 LINE
PRODUCT
NUMBER
1103
2501
2502
2503
2504
2505/2524
2506
2507
2509
2510
2511
2512/2525
2513
2514
2516
2517
2518
2519
2521
2522
2527
2528
2529
DESCRIPTION
OUTPUT
STRUCTURE
1024 x 1 dynam ic RAM
256 x 1 Static RAM
256 x 4 Dynamic Shift Register
512 x 2 Dynamic Shift Register
1024 x 1 Dynamic Shift Register
512 x 1 Dynamic Shift Register
100 x 2 Dynamic Shift Register
100 x 2 Dynamic Shift Register
50 x 2 Static Shift Register
100 x 2 Static Shift Register
200 x 2 Static Shift Register
1024 x 1 Dynamic Shift Register
64 x 7 x 5 Character Generator
512 x 5 ROM
64 x 6 x 8 Character Generator
100 x 2 Dynamic Shift Register
32 x 6 Static Shift Register
40 x 6 Static Shift Register
128 x 2 Static Shift Register
132 x 2 Static Shift Register
256 x 2 Static Shift Register
250 x 2 Static Shift Register
240 x 2 Static Shift Register
Bare Drain
3-State
Bare Drain
Bare Drain
Bare Drain
Bare Drain
Bare Drain
7.5K Resistor
3-State
3-State.
3-State
Bare Drain
3-State
3-State
3-State
20K Resistor
Bare Drain
Bare Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
'NOTE: Values are given for the maximum value of pull-down resistor ,output to
TO DRIVE
ONE TTL/DTL
USE*
Sense Amp
Direct
3.0K
3.0K
3.0K
3.0K
3.0K
6.8K
Direct
Direct
Direct
3.0K
Direct
Direct
Direct
3.3K
6.8K
6.8K
Direct
Direct
Direct
Direct
Direct
voo.
FIGURE 18
"OR" TY ING OUTPUTS
The characteristics of the four types of output structures
differ when tied together. A basic feature of MOS is that the
design limitation on output "OR"ing is related to the output
voltage levels required and the RC time constant of the
resulting network.
vee
---1 Ql-1 ~-~
r--
BARE DRAIN
The number of bare drain devices which can be tied together
is limited by the output time constant and the VOH level
required.
9vee
I
1
.!.
rOUT
~
.. - ,
~I
RPOjCw
VOO
1.
":"
1
-;C0UT
1..
":"
Switching time for the pull-down condition is determined
by the load resistor RpD and load capacitance CL· The MOS
pull-up device is turned off and does not contribute to the
negative going time constant. See Figure 19.
FIGURE 19
CL is comprised of wIring capacitance (CW) and output
capacitance (COUT) from each of the paralleled outputs.
As the number of paralleled devices increases, the value of
RpD must be decreased to maintain speed.
When driving loads having significant input capacitance, CL
should be increased accordingly.
'-10
As RpD is decreased, VOH decreases since the impedance of
Ql when ON (approx. 500 ohms) will ratio with RpD to produceVOH· If RpD is reduced too far, the output voltage will
be insufficient to turn off the TTL gate being driven.
Figure 20 gives the recommended value of RpD as a function of fan-out for 2500 series bare drain devices.
SILICON GATE TECHNOLOGY
Fan-Out
A CLOCK DRIVER FOR 2500 SERIES MOS
CL
RPO·
VOH
1
!
1
2
3
4
5
3.3K
2.5K
2K
1.67K
1.43K
15pF
20pF
25pF
30pF
35pF
3.7V
3.3V
3.0V
2.7V
2.4V
I
FIGURE 20
• For t F= 50ns
In order to obtain optimum performance from MaS devices, they must be provided with clock signals ofthe proper.
amplitude, shape and timing. This section will present a
simple clock generator and driver scheme suitable for use
with 2500 Series MaS devices.
NOTE: The following devices employ on-chip clock generators and may be driven directly by TTL gates:
2509
Figure 20 assumes 10pF of wiring capacitance and 5pF per
output. It should be noted that when the MaS device' is OFF,
the TTL input current of 1.6mA is sunk to -5V. When set up
for a fanout of 5, the 1.6mA from the TTL gate will bring
the output to only -2.7V. In actuality the input clamp or
substrate diode of the TTL gate will turn on and clamp the
output to -1.0V. The diode will supply the additional current
(approximately 1.9mA).
INTERNAL PULL-DOWN
When 2500 Series devices with internal pull-down resistors
are paralleled, the equivalent resistance RpD is the parallel
combination of all the internal resistors. A chart of the
equivalent resistance, output time constant and VOH for the
2507 with a 7.5K internal pull-down resistor is shown in
Figure 21.
2510
2511
2518
2519
2521
2522
The clock driver must provide relatively large voltage swings
for the clock lines. In the case of 2500 Series MaS, the clock
signal must swing from +5V to -12V. And it must provide a
clean waveform having reasonable rise and fall times (under
40 ns.) and lack of positive overshoot.
IMPROPER CLOCK WAVEFORMS
Some common examples of improper clocking are shown in
Figures.23, 24, and 25.
.~
- --- --u--~='~~'~A~'~.
NOTE:
An ideal clock driving waveform.
FIGURE 22
Fan-Out
1
2
3
4
5
CL
RpO
tf
VOH
15
20
25
30
35
7.5K
3.75K
2.5K
1.87K
1.5K
110nS
75nS
63nS
56nS
53nS
4.4 V
3.8V
3.3V
2.9V
2.5V
+5.3
+5
====~ ~ ~ =8~ ~ ~ --------------~~
.12
POSITIVE OVERSHOOT
NOTE:
Shows an overshoot occurring on the positive going
transition of clock. This has the effect of forward
FIGURE 21
biasing the substrate diode and must be avoided to
prevent erratic behavior in the driven device.
FIGURE 23
PUSH-PULL OUTPUTS
Push-Pull outputs allow low rise and fall times but cannot
be paralleled because it would then be possible to have both
a push and a pull device on at the same time resulting in a
low impedance between the power supplies (and indeterminate output level).
+5
o
·12
NOTE:
Shows the clock never returns to 5V (0 reference) to
turn the input device OFF. This clock can sometimes
appear to be functional. Data may toggle through a
THREE STATE OUTPUTS
shift register, but will not be stored.
FIGURE 24
The three state output is designed to take advantage of pushpull drive capability plus the ability to OR the outputs.
+5
The third (or open) state is used when the chip is unselected.
The selected output is freQ to drive the load without being
affected by the other outputs tied to the bus.
Output rise and fall times for the WIRED OR configuration
of three-state devices is a function of the ON resistance of
the individual pull-up and pull-down devices together with
the load capacitance.
0---------------CROSS- COUPLED CLOCKS
·12
NOTE:
Shows cross-coupling between two clock drivers
usually caused by lack of clamping or non-active
(high-impedance) switching in the positive direction.
FIGURE 25
7-11
SILICON GATE TECHNOLOGY
The positive overshoots illustrated in Figure23 and Figure25
are the most common sources of clock driving trouble. When
the clock line goes positive relative to the circuit substrate
(Vee) by more than approximately 0.3V. the substrate diode
may become forward biased. When this occurs. device operation may become erratic. And because the forward characteristics of the substrate diode may be different for different
processing techniques, a clock driver may work properly
with one device but not with another.
The driver circuit recommended here (Figure 29) utilizes a
complementary output structure to obtain maximum noise
immunity and fast rise and fall time under heavy capacitive
load. It is capacitively coupled to the TTL clock generator.
Resistor R4 is required only when operating at a clock
frequency of lower than 750 KHz. This resistor shifts the
response of the driver input circuit toward the lower frequencies by lengthening the input time constant. One clock
driver is required for each clock phase.
+5V
A properly designed driver utilizing level clamping will prevent the overshoot problem.
THE DRIVER OUTPUT STRUCTURE
Figures 26. 27. and 28 show possible output driver structures together with their advantages and disadvantages.
~ioUT
RESISTOR PULL-UP, POOR NOISE IMMUNITY, AND
SLOW RISE TIME
+5
-12V
OUT
0,. 04 2N2906. Heat Sink Required
02. 03 2N2222, Heat Sink Required
C" C2 100pF
0,. 02 1N914
R1' R2. R3 33 Ohm
R4 2.2K Ohm (Required only
for operation _ below 750KHz)
FIGURE 29
-12
(POOR)
FIGURE 26
PUSH-PULL, SLOW RISE AND FALL TIME
+5
GENERATING MULTIPLE PHASES
The 2500 Series MOS devices which require high level clocks
also require more than one phase. The dynamic shift registers require two phases and the 2508 dynamic RAM requires
four phases.
TWO PHASE SYSTEM
~JVV\r--<> OUT
The clock generator in Figure 30 produces alternate pulsesthe width of which are one quarter of the input clock period
(assuming a square wave clock). See Figure '32.
TWO PHASE TTL CLOCK GENERATOR
Vee
-12
(ACCEPTABLE)
FIGURE 27
COMPLEMENTARY, EXCELLENT NOISE IMMUNITY,
FAST RISE AND FALL TIME
+5
FIGURE 30
-12
FIGURE 28
7-12
(BEST)
When required. the clock pulse widths can be varied by using
one-shot multivibrators such as the 8162 or 74121. Each
phase width can be varied independently (the limiting factor
being the clock period), see Figure 31 (a). or a single oneshot ahead of the clock generator will change both phases
simultaneously. See Figure 31(b).
SILICON GATE TECHNOLOGY
METHOD OF PROVIDING INDEPENDENTLY
VARIABLE CLOCK PHASES
TWO PHASE CLOCK
GENERATOR WAVEFORMS
+5
CLOCK
a
FIGURE 31(8)
1L..._ _......
+5
+5
METHOD OF PROVIDING
VARIABLE CLOCK PHASES
Q
U
~1
U
+5
+5
o
¢2
n
n
~--------~
¢1
+5
¢2
FIGURE 31 (b)
FIGURE 32
FOUR PHASE SYSTEM
The circuit shown in Figure 33(a) and (b) can be used to generate four phase clock signals for the 2508 1024 RAM.
DIVIDE-BY-12 SYNCHRONOUS COUNTER
(
()
~J
0
J
0
y,
r--- f--o
8H21
C
(A)
I
Y,
C
r---
.-
(81
'---- K
J2
J3
J3
8H21
8829
C
Kl
'----- K2
'"- K
~
J2
K3
Of--
~Jl
Of---<
~Jl
C
(el
'--
Kl
~
K2
' - - - - K3
8829
(0)
a
f---------4
CLOe KIN
(26 MHz)
.2.
FIGURE 33(8)
7-13
SILICON GATE TECHNOLOGY
FOUR PHASE SYSTEM
FOUR PHASE DECODER
A
8260
4 "---...,---..,.
FIGURE 33(b)
Figure 34 shows typical clock input capacitances for 2500
Series devices. The number of similar devices which can be
driven by one clock driver is indicated.
NO. OF UNITS
TYPICAL
DEVICE
WHICH CAN BE
CLOCK
DRIVEN (INCLUDES
CAPACITANCE
ALLOWANCE FOR
(pF)
WIRING CAPACITANCE)
2502
2503
2504
2505
2506
2507
2508
2512
2517
2524
2525
140
140
140
80
25
25
25
100
25
80
100
<2MHz (1)
8
8
8
12
40
40
40
11
40
12
11
FIGURE 34
7·14
'2-4MHz (2)
6
6
6
9
30
30
30
7
30
9
(1) Drive capacity 1200pF
7
(2) Drive capacity 750pF
!ii!)notiC!i
FULLY DECODED RANDOM ACCESS
1024-811 DYNAMIC MEMORY
1103
SILICON GATE 2500 SERIES
DESCRIPTION
SILICONE PACKAGING (Cont'd)
The Signetics 1103 is designed for main memory applications where high performance, low cost and large bit
storage are important design objectives. It is a 1024 word
by 1 bit random access memory element using enhancement
mode P·channel MOS devices integrated on a monolithic
array. It is fully decoded, permitting the use of an 18'pin
dual in-line package. The dynar:nic circuitry dissipates significant power only during precharge. Information ston~d
in the memory is nondestructively read. Refreshing of all
1024 bits is accomplished in 32 read cycles and is required
every two milliseconds. A separate cenable (chip enable)
lead allows easy selection of an individual package when
outputs are OR-tied. Use Signetics 8T25 Sense Amp, and
3207 Clock Driver.
material over the silicon gate-ox ide-substrate structure provides an ion barrier. In addition, Signetics proprietary
surface passivation and silicone packaging techniques result
in an MOS circuit with inherent high reliability and demonstrating superior moisture resistance, mechanical shock and
ionic contamination barriers.
PIN CONFIGURATION (Top View)
1.
2.
3.
4.
5.
6.
7.
8.
9.
FEATURES
•
LOW POWER DISSIPATION - DISSIPATES POWER
ON SELECTED CHIPS
ACCESS TIME - 300 nsec.
CYCLE TIME - 580 nsec.
REFRESIH PERIOD - 2 MILLISECONDS FOR 0-70c C
AMBIENT
OR-TIE CAPABILITY
SIMPLE MEMORY EXPANSION WITH CHIP ENABLE
FULLY DECODED - ON-CHIP ADDRESS DECODE
INPUTS PROTECTED - ALL INPUTS HAVE PROTECTION AGAINST STATIC CHARGE.
LOW COST PACKAGING -18 PIN SILICONE AND 18
PIN CERAMIC DUAL IN-LINE
PRIMAR~LY
•
•
•
•
•
•
•
•
APPLICATIONS
CORE MEMORY REPLACEMENT
BUFFER STORES
MAIN MEMORY
Address 3
Address 2
Address 0
Address 1
Precharge
Address 9
Address 6
Address 5
Address 7
18.
17.
16.
15.
14.
13.
12.
11.
10.
Read/write
VSSI
Cenable
Address 4
Data Out
Address 8
Data In
VDD
VBB
PART IDENTIFICATION TABLE
E
TYPE
PACKAGE
OP. TEMP. RANGE
1103XA
18-Pin DIP Silicone
0-70°C
11031K:
18-Pin DIP Ceramic
0-70°C
BLOCK DIAGRAM
PROCESS TECHNOLOGY
The use of Signetics' unique silicon gate low threshold
process allows the design and production of higher performance MOS circuits and provides higher functional
density on a chip than other MOS technologies.
Vae
Vss
Voo
PRECHARGE
SILICONE PACKAGING
CENABLE
READ!WRITE
Low cost silicone DIP packaging is implemented and reli-·
ability is assured by the use of Signetics unique silicon gate
MOS process technology. Unlike the standard metal gate
MOS process, the silicon material over the gate oxide passivates the MOS transistors, and the deposited dielectric
a-----..
a-----..
a-----..
a-----..
a-----..
a-----..
LOGIC 0" HIGH VOLTAGE
LOGIC 1 '" LOW VOLT AGE
7-15
SILICON GATE MOS. 1103
MAXIMUM GUARANTEED RATINGS(10)
Operating Ambient Temperature
Storage Temperature
All Input or Output Voltages
with Respect to the Most
Positive Supply Voltage, VBB
oOe to700e
o
-65°e to +150 e
Supply Voltages VDD and VSS
with Respect to VBB
Power Dissipation
-25V to O.3V
1.0W
-25V to O.3V
D.C. AND OPERATING CHARACTERISTICS
o
T A =ooe to +70 e, VSS(1) = 16V ± 5%, (VBB -VSS)(6) = 3V to 4V, VDD = OV unless otherwise specified (Note 9).
SYMBOL
TEST
!VIIN.
TYP.
MAX.
UNIT
CONDITIONS
= OV, T A = 25°C
= OV, TA = 25°C
III
Input Load Current (All input pins)
1
J.i.A
V IN
ILO
Output Leakage Current
1
J.i.A
VOUT
ISS
1001(2)
100
J.i.A
Supply Current During tpc
37
56
mA
All Addresses = OV
Precharge = OV
Cenable = VSS; T A
1002(2)
Supply Current During tov
38
59
mA
All Addresses = OV
Precharge = OV
Cenable = OV; TA = 25°C
1003(2)
Supply Current During tpov
5.5
11
mA
Precharge = VSS
Cenable = OV; TA
1004(2)
Supply Current During tcp
3
4
mA
Precharge = V SS
Cenable = VSS: T A
100(5)AV
Average Supply Current
17
25
mA
Cycle Time = 580 ns;
Precharge Width'" 190 ns;
TA = 2SOC
VIL1(7)
Input Low Voltage (All Address
& Data-in Lines)
VSS-17
VSS-14.2
V
TA
= O°C
VIL2(7)
Input Low Voltage (All Address
& Data-in Lines)
VSS-17
VSS-14.S
V
TA
= 70°C
VIL3(7,8)
Input Low Voltage (Precharge
Cenable & Read/Write Inputs)
VSS-17
VSS-14.7
V
TA
= O°C
VIL4(7,8)
Input Low Voltage (Precharge
Cenable & Read/Write Inputs)
VSS-17
VSS-1S.0
V
TA
= 70°C
= O°C
= 70°C
Vss Supply Current
VIH1(7)
Input High Voltage (All Inputs)
VSS-1
VSS+1
V
TA
VIH2(7)
Input High Voltage (All Inputs)
VSS-0.7
VSS+1
V
TA
IOH1
Output High Current
600
900
4000
J.i.A
IOH2
Output High Current
SOO
800
4000
J.i.A
TA
90
400
mV
TA
80
400
mV
TA
IOL
Output Low Current
VOH1
Output High Voltage
60
VOH2
Output High Voltage
SO
VOL
Output Low Voltage
= 25°C
= 25°C
= 25°C
TA =-25"C}
70°C
See Note 3
RLOAO
= 100.11(4)
= 25°C
= 70°C
See Note 3
NOTES:
1.
The VSS current drain is equal to (100 + IOH) or (100 + IOL)'
2.
See Supply Current vs. Temperature (p. 3) for guaranteed current at the temperature extremes. These values are taken from a single pulse
measurement.
3.
The output current when reading a low output is the leakage current of the 1103 plus external noise coupled into the output line from the
clocks. VOL equals IOL across the load resistor.
4.
This value of load resistance is used for measurement purposes. In applications the resistance may range from 100.11 to 1 kn.
5.
This parameter is periodically sampled and is not 100% tested.
6.
(VSS - VSS) supply should be applied at or before VSS'
7.
The maximum values for VIL and the minimum values for VIH are linearly related to temperature between O°C and 70°C. Thus any value
between O°C and 70°C.canpe calculated using a straignt-line relationship.
S. . The maximum values forVIL (for precharge, cenable & read/write) may be increased to VSS-14.2 @ O°C and VSS-14.5 @ 70°C (same values
as those specified for the address and data-in lines) with a 40 ns degradation (worst case) in tAC, tpc, tRC, twc, tRWC, tACC1 and tACC2'
9.
Manufacturer reserves the right to make design and process changes and improvements.
10.
Stresses above those listed under "Maximum Guaranteed Rating" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7-16
SILICON GATE MOS. 1103
CHARACTERISTIC CURVES
SUPPLY CURRENT VS TEMPERATURE
VSS· 1a.8V
Vss - Vss - 3V
.. "
I
51 t---I---t---I--'-''''''tGUARANTEED ~r---r--r---r-~r---I---,
.......
i"-....
~t---I---t---I-~-I-f---~-~
54 f--_-I-_ _f--_-I-_"+GUARANTEEO -
""
TYPICAL
I
" " TYPICAL
70
26
60
70
TloCI
"
,
VSS·,6.8V
VBB-vSS·av
,
" ' ... "
J
f----+---f----I--~GUARANTEED
-
-
TloCI
100 VS TIME
TloCI
IOO(mA)
T
TA"26"C
VSS·16.8V
Vas- Vss- 3V
t.IOO(SEE
NOTE 11
1\
f~
1003"1'
1004-4
\
0'---,--..,.-'-----"---.==0--____
I-·H·~·I:TpC TOV T~V
Tep
Tpw+TW
NOTES:
1.
III DO is due to charging of internal device node capacitance
at precharge.
2.
These values are taken from a single pulse measurement.
'·17
SI LICON GATE MOS • 1103
CHARACTERISTIC CURVES (Cant'd)
I
1.2
1-+--+~!M--""'+-r-1~~H~
1.1
I--+--+;._
J:
.9
1
~ 18
1---+-+-+
VsslVOLTSI
VsslVOLTSI
120
TOv(m)
AC CHARACTERISTICS TA = 25°C, VSS= 16 ± 5%, (VBB -VSS) = 3.0V to 4.0V, VDD = OV
READ, WRITE, AND READ/WRITE CYCLE·
SYMBOL
TEST
MIN.
MAX.
2
tREF
tAC(1)
Time Between Refresh
tCA
tpC(1)
Cenable to Address Hold Time
Precharge to Cenable Delay
tOVL
Precharge & Cenable Overlap, Low
25
tcp
Cenable to Precharge Delay
85
tOVH
Precharge & Cenable Overlap, High
Address to Cenable Set Up Time
TYP.
115
UNIT
COI\!DITIONS
ms
ns
20
ns
125
ns
75
ns
ns
140
ns
MAX.
UNIT
500
ns
120
ns
READ CYCLE
SYMBOL
TEST
WIN.
tRC(1)
Read Cycle
480
tpov
precharge to End of Cenable
165
tpo
End of Precharge to Output Delay
tACC1(1).
Address to Output Access
300
TYP.
CONDITIONS
ns
ns
t7= 20 ns
tACmin + tOVLmin
+ tPOmax + 2 t7
tACC2(1)
7-18
Precharge to Output Access
310
ns
tPCmin + tOVLmin
+ tPOmax + 2 t7
CLOAD = 100 pF
RLOAD = 100n
VREF = 40 mV
SILICON GATE MOS. 1103
AC CHARACTERISTICS(Cont'd)
WRITE OR READ/WRITE CYCLE
SYMBOL
MIN.
TEST
TYP.
MAX.
UNIT
twC(1)
Write Cycle
580
ns
tRWC(1}
Read/Write Cycle
580
ns
165
tpw
Precharge to Read/Write Delay
twp
Read/Write Pulse Width
50
tw
Read/Write Set Up Time
80
ns
tDW
Data Set Up Time
105
ns
Data Hold Time
tpo
End of Precharge to Output Delay
tp
Time to Next Precharge
Read/Write Hold Time
tcw
}
tr= 20 ns
ns
500
ns
10
tDH
CONDITIONS
ns
120
ns
10
ns
ns
0
CLOAD = 100 pF
RLOAD = 100n
VREF =40 mV
CAPACITANCE (note 2)
SYMBOL
(1)
(2)
MIN.
TEST
TYP.
UNIT
MAX.
CONDITIONS
CAD
Address Capacitance
5
.,
pF
VIN = VSS
CPR
Precharge Capacitance
15
18
pF
VIN = VSS
-
CCE
Cenable Capacitance
15
18
pF
VIN = VSS
CRW
Read/Write Capacitance
11
15
pF
CIN1
Data I nput Capacitance
4
5
pF
VIN = VSS
Cenable = OV
CIN2
Data I nput Capacitance
2
4
pF
VIN = VSS
Cenable = VSS
VIN = VSS
COUT
Data Output Capacitance
2
3
pF
VOUT = OV
f = 1 MHz
f- All Unused Pins are
at A.C. Ground
-
These times will degrade by 40 ns (worst case) if the maximum values for V I L (for precharge, cenable and read/write inputs) go to VSS 14.2V @ O°C and VSS-14.5V @ 70°C as defined on page 2.
This parameter is periodically sampled and is not 100";" tested. It is measured at worst case operating conditions. Capacitance measurements
for plastic packages only.
TIMING DIAGRAM
WRITE CYCLE OR READ/WRITE CYCLE
Tlmlnllillultratedforminknumcycft
o
I
.
~I
~\
60
100
160
I
I
I
200
I
3110
300
260
I
I
I
400
460
I
I
660
600
I
I
twCOR'RWC
-tc~_
..-toVH_
~
/
_tw
- ! p c -------..
-
V,H
N .
-l
H
H
VALUE OF
PREVIOUS STATE
w~
READ/WAITE
LOGIC 0
0
HIGH VOLTAGE (HI
LOGIC 1 = LOW VOLTAGE (L.)
Vee'" SUBSTRATE VOLTAGE
7·20
lijgDotiCIi
FULLY DECODED RANDOM ACCESS 1024-81T
DYNAMIC MEMORY (HIGH SPEED VERSION)
1103.1
SILICON GATE MOS
DESCRIPTION
SILICONE PACKAGING (Cont'd)
The Signetics 1103-1 is designed for main memory applications where high performance, low cost and large bit
storage are important design objectives. It is a 1024 word
by 1 bit random access memory element using enhancement
mode P-channel MOS devices integrated on a monolithic
array. It is fully decoded, permitting the use of an 18-pin
dual in-line package. The dynamic circuitry dissipates significant power only during precharge. Information stored
in the memory is nondestructively read. Refreshing of all
1024 bits is accomplished in 32 read cycles and is required
every two milliseconds. A separate cenable (chip enable)
lead allows easy selection of an individual package when
outputs are OR-tied.
Use Signetics 8T28 Sense Amp, and
3207 Clock Driver.
material over the silicon gate-oxide substrate structure provides an ion barrier. In addition, Signetics proprietary
surface passivation and silicone packaging techniques result
in an MOS circuit with inherent high reliability and demonstrating superior moisture resistance, mechanical shock and
ionic contamination barriers.
PIN CONFIGURATION (Top View)
18
17
16
16
FEATURES
14
•
13
LOW POWER DISSIPATION - DISSIPATES POWER
PRIMARILY ON SELECTED CHIPS
• ACCESS TIME - 150 nsec.
• CYCLE TIME - 340 nsec.
• REFRESH PERIOD - 1 MILLISECOND FOR 0-550 C
AMBIENT
• OR-TIE CAPABILITY
• SIMPLE MEMORY EXPANSION WITH CHIP ENABLE
• FULLY DECODED - ON-CHIP ADDRESS DECODE
• INPUTS PROTECTED - ALL INPUTS HAVE PROTECTION AGAINST STATIC CHARGE
• LOW COST PACKAGING - 18 PIN SILICONE AND 18
PIN CERAMIC DUAL IN-qNE
12
11
Read/write
1. Address 3
18.
2.
Address 2
17. Vss
3.
Address 0
4.
Address 1
16. Cenable
15. Address 4
Datii Out
5. Precharge
14.
6. Address 9
13. Address 8
7.
Address 6
12. Data In
8.
Address 5
11.
9.
Address 7
10.
VOO
VBB
10
PART IDENTIFICATION TABLE
TYPE
PACKAGE
OP. TEMP RANGE
1103-1XA
18-Pin DIP Silicone
0-55°C
1103-11K
18-Pin DIP Ceramic
0-55°C
APPLICATIONS
CORE MEMORY REPLACEMENT
BUFFER STORES
MAIN MEMORY
BLOCK DIAGRAM
PROCESS TECHNOLOGY
The use of Signetics' unique silicon gate low threshold
process allows the design and production of higher performance MOS circuits and provides higher functional
density on a chip than other MOS technologies.
vaB 0 - - - - - .
Vss~
VDD
DATA IN
-----0
C>---t--
PAECHARGE C > - - - t - CENABlE
.---...!...----,
' - - - - r - - - - - ' i5ATA OUT
a-----.-
READ/WRITE 0---------
SILICONE PACKAGING
Low cost silicone DIP packaging is implemented and reliability is assured by the use of Signetics unique silicon gate
MOS process technology. Unlike the standard metal gate
MOS process, the silicon material over the gate oxide pass ivates the MOS transistors, and the deposited dielectric
LOGIC 0 '" HIGH VOL rAGE
LOGIC 1 " LOW VOL T AGE
7-21
SILICON GATE MOS. 1103-1
MAXIMUM GUARANTEED RATINGS (8)
Operating Ambient Temperature
Storage Temperature
All Input or Output Voltages
with Respect to the Most
Positive Supply Voltage, VBB
O°C to 55°C
-65°C to +150°C
Supply Voltages VDD and VSS
with Respect to VBB
Power Dissipation
-25V to O.3V
1.0W
-25V to O.3V
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to -55°C, VSS(1) = 19V ± 5%, (VBB - VSS)(6) = 3V to 4V, VDD = OV unless otherwise specified (Note 7).
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
= OV, T A = 25° C
= OV, TA = 25°C
III
Input Load Current (All input pins)
10
JJ.A
V IN
ILO
Output Leakage Current
10
JJ.A
VOUT
ISS
1001(2)
Supply Current During tpc
Vss5upply Current
45
100
JJ.A
60
mA
= OV
= OV
All Addresses
Precharge
= VSS; T A = 25°C
= OV
Precharge = OV
Cenable = OV; T A = 25°C
Precharge = VSS
Cenable = OV; TA = 25°C
Precharge = VSS
Cenable = VSS; T A = 25°C
Precharge Width =150n5 @ 50%
Cycle Time = 340 ns; T A = 25°C
Cenable
1002(2)
Supply Current During tov
1003(2)
Supply Current During tpov
8.5
1004(2)
Supply Current During tcp
100(5)AV Average Supply Current
Inp.ut Low Voltage (All address
and data·in lines)
VSS-20
VIH1
Input High Voltage (All Inputs)
VSS-1
IOH1
Output High Current
1.15
0.9
VIL1
68.5
mA
11
mA
3
4
mA
20
23
mA
VSS-18
V
50
IOH2
Output High Current
IOL
Output Low Current
VOH1
Output High Voltage
115
VOH2
Output High Voltage
90
VOL
Output Low Voltage
VSS+1
All addresses
V
0
1.3
7.0
mA
1.15
7.0
mA
TA
-25 C)
TA = 55°C
See Note 3
R LOAO
130
700
mV
TA
115
700
mV
TA
= 100n(4)
= 25°C
= 55°C
See Note 3
NOTES:
1.
The VSS current drain is equal to (100 + IOH) or (100 + lOLl.
2.
See Supply Current vs. Temperatuse (P. 3) for guaranteed current at the temperature extremes. These values are taken from a single pulse
measurement.
3.
The output current when reading a low output is the leakage current of the 1103-1 plus external noise coupled into the output line from the
clocks. VOL equals I OL across the load resistor.
4.
This value of load resistance is used for measurement purposes. I n applications the resistance may range from 100n to 1 kn.
5.
This parameter is periodically sampled and is not 100% tested.
6.
(V BB -
7.
Manufacturer reserves the right to make design and process changes and improvements.
8.
Stresses above those listed under "Maximum Guaranteed Rating" may cause permanent damage to the device. This is a stress rating only and
VSS) supply should be applied at or before VSS'
functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7·22
SI'L1CON GATE. MOS 1103-1
AC CHARACTERISTICS T A = O°C to +55°C; VSS = 19 ± 5%, (VBB -VSS)
READ, WRITE, AND READ/WRITE CYCLE
SYMBOL
TEST
MIN.
TYP.
MAX.
1
= 3.0V to 4.0V,
CONDITIONS
UNIT
tREF
Time Between Refresh
tAC
Address to Cenable Set Up Time
30
ns
tCA
Cenable to Address Hold Time
10
ns
tpc
Precharge to Cenable Delay
60
tOVL
Precharge & Cenable Overlap, Low
tcp
Cenable to Precharge Delay
tOVH
Precharge & Cenable Overlap, High
= OV
VOO
ms
ns
5
30
40
ns
ns
85
ns
MAX.
UNIT
READ CYCLE
SYMBOL
TEST
MIN.
tRC(1 )
Read Cycle
300
tpov
Precharge to End of Cenable
115
tpO(1)
End of Precharge to Output Delay
tACC1(1)
Address to Output Access
TYP.
CONDITIONS
-
ns
500
ns
75
ns
ns
150
tr = 20 ns
tACmin + tOVLmin
CLOAD = 50 pF
+ tPOmax + 2 tr
t ACC 2(1 )
Precharge to Output Access
180
ns
i-RLOAD = 100n
VREF =80mV
tPCmin + tOVLmin
+ tPOmax + 2 tr
-
WRITE OR READ/WRITE CYCLE
SYMBOL
TEST
MIN.
TYP.
MAX.
twc
Write Cycle
340
ns
tRWC(1)
Read/Write Cycle
340
ns
115
tpw
Precharge to Read/Write Delay
twp
Read/Write Pulse Width
20
ns
tw
Read/Write Set Up Time
20
ns
tDW
Data Set Up Time
40
ns
tDH
Data Hold Time
10
tpO(1)
End of Precharge to Output Delay
500
CONDITIONS
UNIT
}
tr = 20 ns
ns
ns
75
CLOAD
ns
= 50 pF
RLOAD =100n
tp
Time to Next Precharge
tcw
Read/Write Hold Time
0
ns
15
ns
MAX.
UNIT
VREF
= 80
mV
CAPACITANCE (note 2)
SYMBOL
TEST
MIN.
TYP.
CONDITIONS
CAD
Address Capacitance
5
7
pF
VIN = VSS
CPR
Precharge Capacitance
15
18
pF
VIN = VSS
CCE
Cenable Capacitance
15
18
pF
VIN = VSS
CRW
Read/Write Capacitance
11
15
pF
VIN = VSS
CIN1
Data I nput Capacitance
4
5
pF
Cenable = OV
f = 1 MHz
- All Unused Pins are
at A.C. Ground
VIN = VSS
CIN2
Data I nput Capacitance
2
4
pF
Cenable = VSS
VIN = Vss
COUT
Data Output Capacitance
2
3
pF
VOUT = OV
-
(1)
ThesEI times will degrade by 35 ns if a V RE F point of 40 mV is chosen instead of the 80 mV point defined in this specification.
(2)
This parameter is periodically sampled and is not 100% tested. It is measured at worst case operating conditions. Capacitance measurements
for plastic packages only.
7-23
SILICON GATE MOS. 1103-1
TIMING DIAGRAM
WRITE CYCLE OR READ/WRITE CYCLE
Timing illustrated for minimum cycle
0
50
100
150
200
250
300
350
I
400
I
I
I
I
I
I
I
I
oil
VIH~
AOORESS
ADDRESS
VIL
450
I
twc OR tRWC
V
@
~
CHANGE
I\",G)
_
-
toVH_
_tAC_
/~
PRECHARGI:
-
VIL
VIH
tpc
- :Q ,-
_
VIL
~
I
•
tpw
oil
VIH
READ/WRITE
VIL
_
VIH
DATA IN
tw
I-toVL
CENABLE
I
-
580
I
•
ADDRESS
CAN CHANGE
tCA _
~I'_tcp _
7~
...--tew
..-
tp
twp - - - -
--..
V
-- X
_ _ tDH (Note 4)
tow (Note 3) _
)<~
DATA C!"N CHANGE
550
I
X
ADDRESS STABLE
VIH~
500
STABLE DATA TIME
DATA CAN CHANGE
VIL
_tpo_
VOH
VOL
- --
/
DATA OUT
...
VREF
RLOAD
CLOAD
=
50pF
.•
tACCl
tACC2
oil
------"
-
: ~:ri-'\."-
DATA OUT NOT VALID
-
"-,
I - - - DATA OUT VALID
READ CYCLE
VIH~
?@
CAN
ADDRESS
CHANGE
..
tRC
'"
X
ADDRESS STABLE
~(j)
- --
VIL
_tAC_
VIH~
PRECHARGE
VIL
VIH
CENABLE
-
_toVH_
teA
/
tpo_
~'x
-ltoVL -
VIH
.,
..
•
tpov
READ/WRITE
VIL
_tpo_
VOH
/
--
VOL
...
VREF= 80mV
~
RLOAD = lOOn CLOAD = 50pF
tACCl
tACC~
'"
•
.
--"-
"-
-
-
"DATA OUT VALID
NOTES:
CD
@
3
4
7·24
VOO + 2V}
VSS _ 2V
tr is defined as the transitions between these two points.
tow is referenced to point
tOH is referenced to point
CD
@
~"
tep-
VIL
DATA OUT
ADDRESS CAN CHANGE
of the rising edge of cenable or read/write whichever occurs first.
of the rising edge of cenable or read/write whichever occurs first.
SILICON GATE MOS. 1103-1
CIRCUIT SCHEMATIC
L"LOWVOLTI\GE
H ~HIGHVOLTAGE
'o-f~VOO
-cAli
AOo-f
Vss
Voo
AJ o---{).o---o G
c;;i"
,
CEo--lf
AS o---{).o-o A5
AS o---{).O--o As
,
A7o----{).O--o10
,
Aao----{).o--o As
,
A9o----{).o--o As
Po--l~VOO
Vss
Vss
ffo-j
0"
CEo-f
Vss
P-PRECHARGE
Ce"'CENABLE
WmREAD/WRITE
LOGIC 0" HIGH VDI..TAGE (H)
LOGIC 1 a LOW VOLTAGE ILl
VSB -SUBSTRATE VOLTAGE
7-25
2000
DUAL STATIC
SHIFT REGISTERS
Si!lDOliCS
(FOR REFERENCE ONLY, NOT RECOMMENDED
FOR NEW DESIGNS)
DESCRIPTION
METAL GATE MOS 2000 SERIES
PIN CONFIGURATION
The S2001 K, S2002K, S2003K, S2004K, and S2005K are
Dual Static Shift Registers manufactured with a "P",
channel enhancement mode process.
BOTTOM VIEW
The registers vary in length from dual 16 to dual 100. Two
power supplies and 2 external 28 volt clocks are required.
Static operation is assured with a third clock phase that is
generated on the chip. The pin configuration allows interchanging of register lengths without rewiring the socket.
Data is transferred into the register during 1/>1 and output
data appears on the negative-going edge of 1/>2' For static
operation 1/>1 must be a "0" and 1/>2 "1".
He
OND
He-NO INTERNAL CONNECTION
PARTS IDENTIFICATION TABLE
PART NO.
BIT LENGTH
PACKAGE
ABSOLUTE MAXIMUM RATINGS
S2001K
16
10 Pin TO-100
Vdd with respect to Gnd
Vgg with respect to Gnd
Clock and In with respect to Gnd
Operating Temperature
Storage Temperature
S2002K
25
10 Pin TO-100
S2003K
32
10 Pin TO-100
-16V to 0.3V
-30V to 0.3V
-30V to 0.3V
-55°C to +85°C
-55°C to +150°C
S2004K
50
S2005K
100
10 Pin
CIRCUIT SCHEMATIC
°2~
________
~
________
~~
______
~
________
~
"1~--------~--,-----~~------+-~
Voo>-~--~--~--~~--~~r-----~~~--~~~~
Voo~+-~~--~--~~~~~r-~--~~~--~~~~r---+--'
DATA OUT
"280
INf'UT CIRCUITRY
7·26
I
T
LAST BIT
TO-~OO
10 Pin TO·100
OUTPUT BUFFER
METAL GATE MOS. S2000 SERIES
ELECTRICAL CHARACTERISTICS ( Notes: 1,2,3,4 and 5 )
LIMITS
CHARACTER ISTICS
"1" Output Voltage
MIN
TYP
-11
-13
"0" Output Voltage
-0_3
MAX
-1
TEST CONDITIONS
UNITS
TEMP
NOTES
VDD
VGG
Vin
V,
V2
V
-13
-27
-10
-27
-27
5
V
-15
-29
-2
-29
-29
5
°c
OUTPUT
Output Drive Capability
2001
~002/3/4/5
{
-[
-8
-10
V
-13
-27
-10
-27
-27
RL
-4
-6
V
-13
-27
-10
-27
-27
RL
-10
-11
V
-13
-27
-10
-27
-27
RL
-6
-8
V
-13
-27
-10
-27
-27
RL
0
0
= 17kD. to Gnd
= 4 kD. to Gnd
= 17 kD.to Gnd
= 4 kD. to Gnd
Input Leakage Current
Data Inputs
0_5
JJ.A
+85
0
0
-20
1
50
JJ.A
+85
0
0
0
-28
0
2
50
JJ.A
+85
0
0
0
0
-28
2001
2.5
kD.
-13
-27
-2
-27
-27
Oto -lV
2002/3/4/5
1.5
kD.
-13
·27
-2
-27
-27
Oto -lV
3
5
pF
-14
-28
0
0
0
2001
8
10
pF
25
-14
-28
0
0
0
8
2002
8
12
pF
25
-14
-28
0
0
0
8
2003
8
13
pF
25
-14
-28
0
0
0
8
2004
12
18
pF
25
-14
-28
0
0
0
8
2005
16
33
pF
25
-14
-28
0
0
0
8
-29
Clock Inputs
Output Impedance
Input Capacitance
Data Inputs
25
8
Clock Inputs
Power Supply Current
IDD
2001
-3
-10
mA
-55
-15
-29
0
2002
-5
-20
mA
-55
-15
-29
0
-29
2003
-6
-24
mA
-55
-15
-29
0
-29
2004
-7
-17
mA
-55
-15
-29
0
-29 ...
2005
-14
-32
mA
-55
-15
-29
0
-29
2001/2/3
-0.8
-3.5
"
mA
-55
-15
-29
0
-29
2004/5
-0.5
-3.0
mA
-55
-15
-29
0
-29
IGG
Propagation Delay (tpd)
from 2
2001
300
475
ns
25
-14
-28
-28
-28
6, 7
2002/3/4/5
300
450
ns
25
-14
-28
-28
-28
6, 7
7-27
METAL GATE MOS. S2000 SERIES
FORCING FUNCTIONS
NOTES FOR ELECTRICAL CHARACTERISTICS:
1. Parameter valid over operating temperature range unless otherwise specified.
2.
"DOWN" Level
=
3.
Negative logic definition:
Level = "0".
4.
Manufacturer reserves the right to make design and process
changes and improvements.
5.
"1",
"UP"
Output voltage levels valid from D.C. to 1 MHz.
90% - - - - - -
6. See output timing diagram.
7.
Output load is 10 pF and 1 Mil
8. f = 1 MHz, Vac = 25 mV rms ' All pins not specifically referenced
are tied to guard terminal for capacitance tests. Output pins are
left open.
9.
CLOCK REQUIREMENTS
All voltage measurements are referenced to the ground terminal.
Terminals not specifically referenced are tied to ground.
10% - - - - -
- -
- - -
All typical values are at 25°C and nominal supply voltages.
OUTPUT TIMING DIAGRAM
VOL TAGE lEVELS
MIN
TVP
¢1
¢2
"0"
0
-1
¢1
¢2
"1"
-27
-28
MAX
UNITS
-2.0
Volts
-29
Volts
5
j.J.sec
10
j.J.sec
TIMING
tr & tf
<;2
90:J
' "t
~~{
OV
DATA OUT
.025
¢1 PW
0.4
¢2 PW
0.4
j.J.sec
too
0
j.J.sec
-2V
Note: ¢2 may not be at "0" logic level
for more than 10 j.J.s.
CLOCK DRIVER
INPUT REQUIREMENTS
+5V
r-----------------,
I
I
I
I
I
I
~LOCK o-....,--t;><>-h>----'lNv--,.--4--C'
2N3053 I
lOll. I
~""""_+-ogl
lW I
2N4036 I
I
'l68490
IL
_________________
I
I
~
-23V
r-----------------l
:
SAME AS ABOVE
rfll2
CHARACTERISTIC
MIN
MAX
Data in "0"
+0.3
-2.0
Data in "1"
-10
t"l" & t"o"
0
UNITS
Volts
L _________________ J
Note: At high repetition rates and/or high capacitance loads, the
transistors may require heat sinking, i.e., 1000 pF at 1 MHz.
7·28
Volts
j.J.sec
Note: Data In must be stabl~ between the 10% points of 91'
Si!)notics
(FOR REFERENCE ONLY, NOT RECOMMENDED
FOR NEW DESIGNS)
DESCRIPTION
;METAL ~ATE MOS 2000 SERIES
PIN CONFIGURATION
The N2010K Dual 100-Bit Static Shift Register is designed
for use at shift rates from 0 to 3 MHz. * The device employs
"P" channel enhancement mode MOS techniques. Power
supply requirements are -14 and -28 Vdc. Clocking is
provided by two external -28 volt clock phases. A delayed
second clock phase (<1>2S) is generated on the chip.
Data is transferred into the register during <1>1. Output data
appears on the negative going edge of <1>2. For static
operation, <1>1 must be a "0" and <1>2 a "1".
The N2010K is a direct pin replacement for the S2005K/
3003 1 MHz Static Shift Register.
BOTTOM VIEW
NC
ABSOLUTE MAXIMUM RATINGS:
VDD with respect to Gnd
VGG with respect to Gnd
Clock and Input with respect to Gnd
Operating Temperature
Storage Temperature
2010
DUAL 1~O-BIT STATIC
SHIFT REGISTER DC TO 3 MHZ
GND
-16V to 0.3V
-30 to 0.3V
-30V to 0.3V
O°C to +70°C
-55°C to +150°C
NC-NO INTERNAL CONNECTION
CIRCUIT SCHEMATIC
°2o-------------~----------~--------~._--------__,
~1o-------------~-1--------~--------~~,
vGGo-~----~----~~--~--~~_1------~~-+~--_.--~~--,
vooo-~--~~--~+-~--r_~~~~--_.--_,~_r~--_+--~~--_r----~__,
OATAOUT
~2S0
INPUT CIRCUITRY
NBIT
I
T
LAST BIT
OUTPUT BUFFER
7-29
METAL GATE MOS. 2010
ELECTRICAL CHARACTERISTICS (Notes: 1,2,3,4,9)
RECOMMENDED POWER SUPPLY VOLTAGES: VDD
= -14 +1
Vdc, VGG
TEST CONDITIONS
LIMITS
UNITS
CHARACTERISTICS
NOTES
TEMP
VDD
V
25
-13
V
25
-15
V
25
-13
-0.5
J.J.A
25
1
-50
J.J.A
2
-50
J.J.A
1.5
kr2
MIN
TYP
-8
-10
"1" Output Voltage
"0" Output Voltage
Output Drive Capability
-4
MAX
-6
OUTPUT
V in
V 1
-27
-7
-27
-27
5, 7
-29
-2
-29
-29
5, 7
-27
-7
-27
-27
RL = 4kr2 to Gnd
0
0
-15
0
0
25
0
0
0
-28
0
25
0
0
0
0
-28
25
-13
-27
-2
-27
-27
°c
-1.0
-0.3
= -28 ±lVdc
VGG
V2
Input Leakage Current
Data Inputs
Clock Inputs
Output Impedance
o to -lV
Input Capacitance
Data Inputs
3
5
pF
25
-14
-28
0
0
0
8
Clock Inputs
16
33
pF
25
-14
-28
0
0
0
8
-14
-20
mA
25
-15
-29
0
-29
-0.8
-3.0
mA
25
-15
-29
0
-29
200
250
ns
25
-14
-28
-28
-28
Power Supply Current
IDD
IGG
Propagation Delay (tdp) from 2
6, 7
NOTES:
0
1. Parameter valid at +25 C unless otherwise spec1fied.
2. All voltage measurements are r.ferenced to the ground terminal. Terminals not specifically
ref.renced are tied to ground.
"~OWN" Level'" "1 ", "UP" Level'" "0".
Manufacturer reserves the right to make design and process changes and improvementt.
Output voltage levals valid from DC to 3 MHz.
6. S. . output timing diagram,
7. Output load is 10pF and 1 M.o.
8. t .. 1 MHz, Vee" 25mV rml. All pins not specifically r.f.renced are tied to guard terminal
J. Negative logiC definition:
4.
5.
9.
for capacitance testl. Output plnl are left open.
All tYpical values are at 25°C and nominal supply voltages.
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM OPERATION FREQUENCY
VERSUS CLOCK AND SUPPLY VOLTAGE
6.0
POWER DISSIPATION
VERSUS OPERATING FREQUENCY
1000
-
::::~
!
-
6
~~ ~~
~:::=
:t,Yl"'"
- / N20IOK
~TATIC.: ~
,.. "+2SoC
=
/
I
I
IlUAR.. !ITI:I:D +Z,"C)
I
--
.-
16:
--t--
DUAl.. 1OO-81T MOS
REGIS!ERS
---
o
+20
+1.0
0
-10
-2.0
POWER SUPPlIES 8 CLOCK VOLTAGE (!\U.TS FROM NOIIINALl
7·30
SHt'j
1
o
1.0
2.0
3.0
MAXIMUM OPERATING FREQUENCY (MHZ)
4D
METAL GATE MOS. 2010
CLOCK REQUIREMENTS
TTL INTERFACE REQUIREMENTS
HV
'ra1p!lf
::::::~
-: _:t~i~:::
W%----
'1
'2
---
-----------
~%---------------
. . . . 'r
VOL TAGle LEVELS
ct>,
ct>2
"0"
ct>,
ct>2
"'"
MIN
PW
It
1168490·
TTl/DTl
'""O'ATA
INPUT
-----
MAX
UNITS
0
NOM
-,
-2.0
Volts
-27
-28
-29
Volts
5
~sec
10
~sec
NOTES:
1. Register ground (V s) is tied to the bipolar integrated
circuit Vcc power supply for proper biasing.
2. Vs =
TIMING
.010
tr & 'tf
+5VDC
VD =-9 VDC
VG =-23 VDC
0.'0
ct>1 PW
*3. Signetics Corp. N8490A
ct>2 PW
0.15
too
0
Clock Repetition Rate
~sec
~sec
0
3
MHz
OUTPUT TIMING DIAGRAM
Note: ct>2 may not be at "0" logi'c level
for more than 1 0 ~s.
INPUT REQUIREMENTS
DATA OUT.
CLOCK DRIVER
ARACTERISTIC
Note:
MIN
MAX
Data in "0"
+0.3
-2.0
Data in "1"
-7.0
t"1" & t"o"
0
UNITS
Volts
Volts
Ilsec
Data In must be stable between the 10% points of
It>,.
NOTES:
1. At high repetition rates and/or high capacitance loads,
the transistors may requ ire
heat sinking, i.e., 1000 pFat 3M Hz.
2. y, N8822B, SP322B etc.
3. y, N8880A, SP387A etc.
7·31
!ii!lDotiC!i
FULLY DECODED 1024 AND
2048 STATIC READ·ONLY MEMORIES
2400
METAL GATE MOS 2400 SERIES
DESCRIPTION
CUSTOM ENCODING
The Signetics 2400 Series devices are high speed, fully decoded, MOS static 1024 and 2048-bit read-only memories
offering 128X8, 256X8, 256X4, and 512X4 organizations.
You may describe the particular option you desire in a booklet which will be provided by Signetics. Ask your local
Signetics representative for a copy of "SIGNETICS 2400
SERIES STATIC READ-ONLY MEMORIES - MOS-ROM
PROGRAMMING"_ The booklet contains a blank truth table
and instructions for preparing punched data cards.
Two output structure options, plus both single line and
3-bit binary coded chip select options, provide for wide
versatil ity and economy of appl ication. The devices interface
ct:irectly with standard TTL/DTL or MOS logic circuits.
Process technology is P-Channel enhancement mode_
PIN CONFIGURATIONS (Top View)
FEATURES
•
•
•
•
•
•
128X8, 256X8, 256X4, 512X4 ORGANIZATIONS
STATIC OPERATION - NO CLOCKS
FULLY DECODED ADDRESS
500ns TYPICAL ACCESS' TIME
TTL/DTL COMPATIBILITY
OUTPUT OPTIONS:
BARE! DRAIN
20K OHM PULL-DOWN RESISTOR
• TWO CHIP SELECT OPTIONS:
SINGLE LINE
3-BIT BINARY CODED
• EBCDIC-ASCII CONVERSION
TABLE IS CATALOG STANDARD,
OTHER STANDARDS AVAILABLE
• +12, -12V POWER SUPPLIES,
• STANDARD PINNING IN 16 AND 24 PIN CERAMIC
DUAL IN-LINE PACKAGES
..
1.
2.
3.
4.
5.
6.
7.
8.
.0
20
APPLICATIONS:
CODE CONVERSION
LOOK-UP TABLES
MICRO-PROGRAMMING
RANDOM LOGIC SYNTHESIS
CHARACTER GENERATION
"
11
13.
Chip Select Options: Both the 2420 and 2430 group may be
specified with either single line chip select or a 3 line, 3-bit
binary coded chip select. The coded chip select allows oneof-etght chip selection without external logic components
for larger memory matrices. The 2410 group is pin limited
to single line chip select.
Package Options: The 256X4 organization is available in
either a 16-pin or 24-pin dual in-line package.
For a detailed listing of part numbers and options see the
PART IDENTIFICATION TABLE.
7·32
Vss
1.
2.
3_
4.
5.
6.
Addres"3
AddrelS 2
Address 1
Output 1
Output 2
Output 3
7.
8.
9.
10.
11.
12.
Ol·tput 4
e .Jtput 5
Output 6
Output 7
Output 8
VSS
16 •
VOO
15.
14.
13_
12_
11.
Addresl4
Address 5
Address 6
Address 7
VGG
10. Chip Enable
Address 8
9.
24.
VOO
23.
22.
21.
20.
19.
18.
Chip Enable 3·
Chip Enable 2·
Address 4
Address. 5
Address 6
Address 7
17. VGG
16.
15.
14.
13.
Mode Control
Chip Enable
Address 8
No Connection
14
SPECIAL FEATURES
Output Options: Two output structure options allow ease
of interfacing with TTL/DTL or other MOS circuits.
Address 3
AddrelS 2
Address 1
Output 1··
Output 2
Output 3
Output 4
n
·No connection for ,Ingle chip
enable optlonl.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Addrell3
Address 2
Address 1
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Output 8
VSS
24.
VOO
Chip Enable 3·
Chip Enable 2·
Address 4
Address 5
Address 6
Address 7
17. Address 8
16. VGG
23.
22.
21.
20.
19.
18.
15. Mode Control
14. Chip Enable
13. Address 9
• No connection for single chip
enable options.
METAL GATE MOS. 2400 SERIES
BLOCK DIAGRAMS
INPUTS
OUTPUTS
t--;:=>--o .,
A,
.......- - - - - 1 - -
A2
-
--
2410
A3
MEMORY
UI
:I
!!j
OPERATING MODE
1. Logic "1" level enables outputs.
At
CHIP ENABLE
.,
INPUTS
OUTPUTS
A,
2420
~----t--£==>--o~
OPERATING MODES
MEMORY
H--I--C>--OBe
~t---t--£==>--oB7
ceo
At 0--...,....--' L..-+'6--I
1. 128 x 8 ROM Connections
Mode Control - Logic "0"
A 8
- Logic "1"
2. 256 x 4 ROM Connection
Mode Control - Logic "1"
A8
- Logic "0" Enables the odd
(81,83,85,87) outputs.
- Logic "1" Enables the even
(8~ 84, 86, 88) outpuU
3. CEO' CE 1 , and CE 2 are AND'ed per
customer instructions.
CE,
<--_~-...,CE2
MOOS CONTROL
0------1_",
.,
INl'UTS
OUn'UTS
A, 0 - -
t----t--i:..J-o()
2430
~
A3~
OPERATING MODES
I
MEMORY
I
1. 256 x
Mode
A9
2. 512 x
Mode
A9
H~-t--LJ-o()Bs
I
I
Hr--t--LJ-o() Be
I
I
I
Hr--I--C=:l-o()
_-........
.......
117
-r---:>--oBe
~1---.......
ABo--..._----'
ceo
8 ROM Connection
Control - Logic "0"
- Logic "1"
4 RO'M Connection
Control - Logic "1"
- Logic "0" Enables the odd
(81,83 .. 87) Outputs
- Logic "1" Enables the even
(82, 84 .•• 88) Outputs
3. CEO' CE 1 , and CE 2 are AND'ed per
customer instructions.
eE,
L...-_....----v CE2
MODE CDNTROL o-----L~
7·33
METAL GATE MOS. 2400 SERIES
ABSOLUTE MAXIMUM RATINGS
-25°C to +70°C
-65°C to + 150° C
@70°C 1.14W
@70°C O.BOW
-30 to +0.3
Operating Ambient Temperature
Storage Temperature
Power Dissipation (2) ("Y" Package)
("1" Package)
VGG (3)
-30 to +0.3
VDD (3)
Input Voltage (3,4)
-30 to +0.3
DC CHARACTERISTICS
TA
=-25"C to +70°C; VSS = +12V
(17); VDD
TEST
SYMBOL
V IL
Input Logic "0"
V IH
ISS
VssPower Supply Current
IGG
VGGPower Supply Current
= OV;
MIN
V GG
= -12V ±10% unless otherwise noted
TYP
Input Leakage
RPD
Pull-down Resistor
UNIT
CONDITIONS
V
Input Logic "1"
IIH
MAX
10
(Notes: 10, 11, 12, 13, 14, 16).
4
14
V
= 25°C
20
mA
TA
1
lolA
Note 5, T A
1
I-/A
V IN
= 25°C
= OV
Note 6
2410,2025,30,35
12
20
k ohm
AC CHARACTERISTICS
= 25°C;
TA
VSS = +12V (17); VDD = OV; VGG = -12V ±10% unless otherwise noted. (Notes: 11,12,13,14,16).
SYM·BOL
TEST
Output Logic "0"
VOL
V OH
Output Logic "1",
Output Logic "0"
MOS to MOS
MIN
TYP
MAX
11
UNIT
1 Megohm to Ground, Note 8
+3
V
1 Megohm to Ground, Note 8
V
Note 7,9
+0.4
V
Note 7,9
Note 15
+2.5
VOL
V OH
Output Logic "1"
tA1
Address Time (bare drain)
500
750
ns
tAO
Address Time (bare drain)
400
500
ns
MOS to TTL
CONDITIONS
V
NOTES:
1.
Stresses above those listed under "MaXimum Guaranteed Ratings" may cause permanent damage to the device. This is a stress rating only.
Operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied,
2.
For operation at elevated temperatures, the device must be derated based on a max imum junction temperature of 150°C and a thermal resistance of
70 °C/W junction to ambient for the "Y" package, The "I" package is derated based on 1 00 °C/W junction to ambient.
3.
These voltages are referenced to network ground terminal (VSS )'
4.
All inputs are protected against damage by static charge,
5.
TheVGGsupply may be clocked to reduce device power without affecting access time,
6.
8.
Output to V OO '
6.8kfl tOV
plus 1 standard TTL gate input,
GG
This test is for devices using a 20kfl MOS pull·down resistor (2410,20, 25,30, 35, ),
9.
This test is for devices supplied with a bare drain out'put (2411,21, 26,31,36),
7.
10. Parameter valid over operating temperature range unless otherwise specified,
11.
All voltage measurements referenCed to ground.
12. Manufacturer reserves the right to make design changes and process improvements,
13. Typical values are at 25°C and nominal supply voltages.
14. Negative logic definition is employed for this device, i,e" more negative level is logic "1 ", most positive level is logic "0",
15.
For bare drain devices, TAl is primarily a function of the time constant of the load capacitance and external load resistor
(tAl
2!
4RL CL +50ns).
16. CAUTION: These devices will be permanently damaged if reversed in board or socket.
17. Vee tolerance Is t10%. Any variation in actual Vee will be tracked directly by VI L' V IH' and V OH which are stated
for a Vee of exactIV 12 voltl.
7·34
METAL GATE MOS. 2400 SERIES
AC TEST SETUP
+12V
+6V
+6V
+~rI
Ov.....J
L-
APPLICATIONS
TIMING DIAGRAM
TTL-MOS-TTL INTERFACING
+12V
"I
OV
{
IN
+12V
OV
R 1 may range from 680n to 33k. typically 3.3k is
satisfactory.
R2 S.8k for a standard TTL (10 IN = 1.6mA)
R3 = 2.2k
PART IDENTIFICATION TABLE
PART
ORGANIZATION
PACKAGE
OUTPUTS
CHIP SELECT
CONTROLS
N24101
256 x 4
16-pin Cer. DIP
20k ohm Pull-down
1
N24111
256 x 4
16-pin Cer. DIP
Bare Drain
1
N2420Y
128 x 8 or 256 x 4
24-pin Cer. DIP
20k ohm Pull-down
1
N2421Y
128 x 8 or 256 x 4
24-pin Cer. DIP
Bare Drain
1
N2425Y
128 x 8 or 256 x 4
24-pin Cer. DIP
20k ohm Pull-down
3
N2426Y
128 x 8 or 256 x 4
24-pin Cer. DIP
Bare Drain
3
256 x 8 (EBCDIC-ASCII)
24-pin Cer. DIP
20k ohm Pull-down
1
N2430Y
256 x 8 or 512 x 4
24-pin Cer. DIP
20k ohm Pull-down
1
N2431Y
256 x 8 or 512 x 4
24-pin Cer. DIP
Bare Drain
1
N2435Y
256 x 8 or 51 2 x 4
24-pin Cer. DIP
20k ohm Pull-down.
3
N2436Y
256 x 8 or 512 x 4
24-pin Cer. DIP
Bare Drain
3
. N2430Y/CMOOO
7-35
METAL GATE MOS. 2400 SERIES
CHARACTERISTIC CURVES
ACCESS TIME VERSUS
SUPPLY VOLTAGE
100 VERSUS TEMPERATURE AND
POWER SUPPLY VOLTAGE
24
2000
1800
22
1800
20
«
.§.
1400
1200
18
c
9
!«
1000
t-
16
800
800
14
400
12
200
TAO
10
100
·25
+25
+100
+75
+50
·20
·24
·22
100 VERSUS SUPPLY VOLTAGE
-7
-8
-9
-10
-11
-12
VOO(V)
NOTE: For typical
= OV.
curves, VSS
7·36
·26
VGG(V)
TEMPERATURE( °C)
-13. -14
-15
-16
-17
·28
·30
METAL GATE MOS. 2400 SERIES
NOTE' Blanks are logic 1 'so
EBCDIC
WORD#
I
CMOOOO TRUTH TABLE
ASCII Code
Bit Number
EBCDIC
WORD,#
0 0 0 0
1 0 0 0
o 1 0 0
1 1 0 0
0
0
0
0
0
0
0
0
65
66
67
68
69
70
71
0
0
0
0
0 1 1 0 0 0 0
1 1 1 1 1 1 1
72
I
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
o
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 1 0 0 0
0 0 0 1 1 0 0
1 0 0 1 1 0 0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 1 0 1 0 0 0
1 1 1 o 1 0 0
1 1 0 1 1 0 0
1 0 1 0 0 0 0
0 1 1 0 0 0 0
1 1 1 0 0 0 0
o
1 1 0 1 0 0
001 0 0 0 0
0 0 1 0 1 0 0
1 0 1 0 1 0 0
0 1 '0 1 1 0 0
0 o 0 0 o 1 0
EBCDIC
WORD #
1 234 5 6 7
1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ASCII Code
Bit Number
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
.0
0
0
1
0
o
1
0
0
1
1
1 1 1 o 1
0 1 1 1 1
0 0 1 0 1
1
1 0 1
1 1 1 1
1 1 0 o 1
o
0
0
1
0
1
o
0
1
0
0
0
0
0
0
0
1
0
0 o 1 0
0 o 1 0
1 0 1 0
1 0 1 0
1 1 1 0
1 0 1 1 0 1 0
1 1 1 1 0 1 0
0
1
1
0
1
o
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1 1 0
0 1 0
0 0 1
1 0
1 1 0
0 1 0
1
1
0
1
1
0
0
1
0
0
o
1 0 0 0 0 1 1
ASCII Code
Bit Number
EBCDIC
WORD #
1 2 3 4 5 6 7
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
0 1 0 0
1 1 0 0
0 0 1 0
1 o 1 0
o 1 1 0
1 1 1 0
0 0 0 1
1 0 0 1
0 1
o 1
o 1
o 1
0 1
0 1
0 1
o 1
1
1
1
1
1
1
1
1
1
1
0
0
o 1
1 1
0 0
1 0
o 1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1 1 1
1 0 1 1 1
1 0 1 1 1
1 o 1 1 1
1
1 1 1
0 1 1 1 1
1 1 1 1
o 1 1 1 1
0
1
0
1
o
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
o
o
o
1 0 0 0 0
1 0 0 0
o
o
o
ASCII Code
Bit Number
1 234 5 6 7
195
196
197
198
199
200
201
202
203
204
205
106
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
1
0
1
0
1
0
1
1
o
o
1
1
0
0
1
1
1
0
o 1
1 1
0 0
1 0
1
0
1
1
1
o
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0 1
1
1 1
1 1
1 1
1 1
0 o
0 0
0 0
0
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
o
o
o
o
o
1
1
1
1
1
1
1
o
o
1
1
1
1
1
1
1
1
1
1 1 0 o 1 0
0 0 1 o 1 0
1 0 1 o 1 0
o 1 1 o 1
1 1 1 o 1 0
0 0 o 1 1 0
1 0
1 1 0
1 o 1 1 0
1
1
1
1
1
1
1
1
o
o
1
0
o
0
0
o
o
o
0 0 0
1 0 0
o 1 0
1 1 0
0 o 1
1 o 1
o 1 1
1 1 1
0 0 0
1 0 0
o
1 1
0 1 1
0 1 1
o 1 1
o 1 1
o 1 1
0 1 1
0 1 1
1 1 1
1 1 1
0
0
0
0
0
0
0
0
0
0
1
1
7·37
METAL GATE MOS. 2400 SERIES
SCHEMATIC DIAGRAM
OUTPUT STRUCTURE
Vss
~tO""",
I
r
I
b
VGG
~ ~~I
• Optional
b
20K MOS pulldown resistor
N2410,20,25,30 and 35 only
Voo
EXERPT FROM SOFTWARE' PACKAGE (CARD FORMAT)
CARDS 2 THROUGH 129 (4
x
266 Qroanlzetioll onlvl
DATA
S'TA'R'TING AT COLUMN 1
IF "COOEO"PUNCHTHEBINARVCOOECHIP
S(LECTI,el011
rf"SINGLE"LEAVl
EACH CARD SPECIFIES THE OUTPUT OF TWO 4·B11
WORDS IN COLUMNS 1 THROUGH 8. THE oeCIMAL
EOUIVALENT OF THE BINARY CODED INPUT
PUNCHTHI:ROMORGANIZATIONOESIRED
ADDRESS IS PUNCHED IN COLUMNS 78. 79, AND 80
."SX2!>64X512ETC
eE).
~UAN:~
PUNCH TTl FORATTL OUTPUTUlARl
DL'TPUT FOR wonDS 0 2M
PUNCH OUTPUT FORWORDS256511
PUNCHTH[SASICOEVICE TVPE DESIRED
,~ N14101 N14;>!)V f rt
PUNCH DECIMAL EOUIVALENTQf BINARY
CODED INPUT ADDRESS OF THE WOROCOR
RESPONDING TO THE OUTPUTS PUNCHED IN
COMMENTS PUNCHED HERE WilL APPEAR
ASTHE TITLE ONTHE TRUTH TABLE
IHISSHOULDINClUDE CUSTOMER PART
IDENTIFICATION
COLUMN 78 HUNDREOS DIGIT
COLUMN 79 TENSQIGlT
COLUMN 80 UNtTS DIGtT
PUNCHMOSFQRANMOSQUTPUT
CE2~"dCEl IMpecU.<>ly
THE ABOVE SPECIFIES A "CODED" ROM WITH THE BINARY COD;D CHIP SELECT "101" ORGANIZED 8 X,258
WITH TTL OUTPUTS !BARE DRAIN!. THE 8ASIC DEVICE TVP~ IS A N2436Y ("Y" INDICATES A 24·PIN CERAMIC
DIP. N INDICATES TEMPERATURE RANGE: -26~C - +70"C.1
EXAMPLE
CARDS
2·129 AND CARDS 2·267
CARDS 2 THROUGH 2B714 X 512 Org,,,IZIItlon onlv!
EACH CARD SPECIFIES THE OUTPUT OF ONE a·BIT
WORD IN COLUMNS 1 TUROUGH 8. THE DECIMAL
EQUIVALENT OF THE BINARY CQDED INPUT ADDRESS
FOR THAT WORD IS PUNCHED IN COLUMNS 78, 79 AND 80
~~LUMNS ~U~:~ OUTPUTS Bl THROUGH BSIN
COLUMNS ONE THROUGH
7880
~IGHT
RESPECTIVELY
PUNCH DECIMAL EOUIVALENT OF 81NARY
CODED INPUT ADDRESS WHICH CORRES
PONDS TO THE OUTPUTS PUNCHED IN
COLUMN 78 HUNDREDS DIGIT
COLUMN 79 TENS DIGIT
COLUMN 8DUNtTS DIGtT
EACH CARD SPECIFIES THE OUTPUT OF TWO 4 BIT
WORDS IN COLUMNS 1 THROUGH 8 THE DECIMAL
EQUIVALENT OF THE BINARY CODED INPUT
ADDRESS IS PUNCHES IN COLUMNS 78. 79, AND 80
~:N:~
OUTPUT FOR WORDS 0 127
PUNCH OUTPUT FonWOROS 128255
[/°1010101
r/'D101010
1/'1100100
PUNCHOECIMALEDUIVALENTOFOINARY
CODED INPUT ADDRESS CORRESPONDING
TD THE OUTPUTS PUNCHED IN CDLUMNS 1 '"
COLUMN 18 HUNDR(!Os DIGIT
COLUMN 19 TIlNSOIGtT
COLUMN 80 UNITsOIGIT
1
•
•
•
OUTPUTS 81 THROUGH 88 ARE IN COLUMNS THROUGH 8 RESPECTIVEL Y
DECIMAL EQUIVAl.ENT OF BINARY CODED INPUT ADDRESS IS IN COl.UMNS 78, 79, AND SO.
FOR 8 X 128 AND 8 x 266 ORGANIZATIONS - OUTPUTS ARE 81 THROUGH 88 RESPECTIVEl.Y
•
FOR 4 X 512 ORGANIZATION:
WORD 000 OUTPUTS
WORD 266 OUTPUTS
WQRD 010 OUTPUTS
WORD 266 OUTPUTS
111111
II
01 IfI
'. 11~1~ 0 ~ ~ ~ 00
U ~ 0 ~:
..,L..111: 111111111111111!
7·38
~ ~ ~ ~~. ~ ~ ~ ~ ~~~~~ 0 ~~.~~ ~~~~!~.,~ 0. ~O ~ n~~~?!~.O~.~ A.?,~ ~?,~.~~ ~~, ~~~~~'~~I!
1!1:)llI11111,!11111111111111111j,111111111111111111IljI...J...
81
85
81
86
THROUGH
THROUGH
THROUGH
THROUGH
84
88
84
88
RESPECTIVEL Y
RESPECTIVEL Y
RESPECTIVELY
RESPECTIVEL Y
WORD 000 OUTPUTS 81 THROUGH 84 RESPECTIVEL V
WORD 128 OUTPUTS 86 THROUGH B6 RESPECTIVELY
WORD 010 OUTPUTS 81 THROUGH B4 RESPECTIVELY
WORD 136 OUTPUTS 85 THROUGH 88 RESPECTIVELY
SmDotiCS
FUllY DECODED 1024 AND
2048 STATIC READ·ONl Y MEMORIES
2441
2451
2461
2462
METAL GATE MOS
DESCRIPTION
PIN CONFIGURATIONS (Top View)
These Signetics devices are high speed, fully decoded, MOS
static 1024 and 2048-bit read-only memories offering
128X8, 126X4, and 512X4 organizations.
I PACKAGE
Both single line and 3-bit binary coded chip select options,
provide for wide versatility and economy of application.
The devices interface directly with standard TTUDTL logic
circuits. Process technology is P-Channel enhancement
mode.
2462
FEATURES
•
•
•
•
•
•
•
12SXS, 256XS, 256X4" 512X4 ORGANIZATIONS
STATIC OPERATION - NO CLOCKS
FULLY DECODED ADDRESS
ACCESS TIME 950n5 MAX.
TTL/DTL COMPATIBILITY
BARE DRAIN OUTPUT
TWO CHIP SELECT OPTIONS:
SINGLE LINE
3-BIT BINARY CODED
• EBCDIC-ASCII CONVI:RSION (CM4030)
TABLE IS CATALOG STANDARD,
OTHER STANDARDS AVAILABLE
• +5, -12V POWER SUPPLIES
• STANDARD PINNING IN 16 AND 24 PIN CERAMIC
DUAL IN-LINE PACKAGES
1.
2.
3.
4.
5.
6.
7.
8.
Address 3
Address 2
Address 1
Output 1
Output 2
Output 3
Output 4
Vss
16.
15.
14.
13.
12.
11.
10.
9.
Voo
Address
Address
Address
Address
1.
2.
3.
4.
5.
6.
7.
8.
4
5
6
7
VGG
Chip Enable
Address 8
Y
Address 3
Address 2
Address 1
Output 1
Output 2
Output 3
Output 4
Vss
16.
15.
14.
13.
12.
11.
10.
9.
Address
Address
Address
Address
Address
4
5
6
7
8
VGG. Voo
Chip Enable
Address 9
24.
23.
22.
21.
20.
19.
18.
17.
16.
15.
14.
13.
VOO
Chip Enable 3"
Chip Enable 2'
Address 4
Address 5
Address 6
Address 7
Address 8
VGG
Mode Control
Chip Enable
Address 9
PACKAGE
APPLICATIONS
CODE CONVE RSI ON
LOOK-UP TABLES
MICRO-PROGRAMMING
RANDOM LOGIC SYNTHESIS
CHARACTER GENERATION
SPECIAL FEATURES
Chip Seleet Options: Both the 2451 and 2461 may be
specified with either singlE! line chip select or a 3 line, 3-bit
binary coded chip select. The coded chip select allows one:of-eight chip selection without external logic components
for larger memory matrices. The 2441 and 2462 are pin
limited to single line chip select.
.
Package Options: The 2!:i6X4 organization is available in
either a 16-pin or 24-pin dual in-line package.
For a detailed listing of part numbers and options see the
PART IDENTIFICATION TABLE.
1.
2.
3.
4.
5.
6.
CUSTOM ENCODING
You may describe the particular option you desire in a
booklet which will be provided by Signetics. Ask your local
Signetics representative for a copy of "SIGNETICS 2400
SERIES STATIC READ-ONLY MEMORIES - MOS-ROM
PROGRAMMING". The booklet contains a blank truth table
and instructions for preparing punched data cards.
Address3
Address 2
Address 1
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Output 8
7.
8.
9.
10.
11.
12. VSS
24.
23.
22.
21.
20.
19.
18.
17.
16.
15.
14.
13.
VOO
Chip Enable 3'
Chip Enable 2"
Address 4
Address 5
Address 6
Address 7
VGG
Mode Control
Chip Enable
Address 8
No Connection
• No connection for single chip
enable options.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Address 3
Address 2
Address 1
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Output8
VSS
'No connection for single chip
enable options.
7·39
METAL GATE MOS. 2641,2451,2461,2462
BLOCK DIAGRAMS
OUTPUTS
t----c:::~--oB,
MEMORY
2441,2462
OPERATING MODE
,. Logic "'" level enables outputs.
AS
Ag"
"2462 ONLY
CHIP ENABLE
INPUTS
OUTPUTS
A,
-- ---
A2
-----
A3
>gj
- - ---
:;;0
-- ---
O::w
00::
wo
MEMORY
:;;«
--
---
-- ----
---
B,
B2
2451
B3
OPERATING MODES
B4
,. '28 x 8 R OM Connections
Mode Control- Logic "0"
B5
Ba
B7
BS
A7
CEo
CE,
AS
A8
- Logic " ' "
2. 256 x 4 ROM Connection
Mode Control- Logic "'"
A8
- Logic "0" Enables the odd
(6', 6~ 6~ 67)output~
- Logic " ' " Enables the even
(6~ 6~ 6~ 68)outpuU
3. CEO, CE" and CE2 are AND'ed per customer
instructions.
CE2
MODE CONTROL
INPUTS
OUTPUTS
A,
A2
>gj
O::w
00::
:;;0
wo
:;;«
-- - --- - --- - -MEMORY
-- - --- - --- - --- ---
AS
B2
B3
B4
B5
B6
B7
Ba
MODE CONTROL
7-40
B,
2461
OPERATING MODES
,. 256 x 8 ROM Connection
Mode Control- Logic "0"
A9
- Logic "'"
2. 5'2 x 4 ROM Connection
Mode Control- Logic "'"
A9
- Logic "0" Enables the odd
(6',63 .. 67) Outputs
- Logic "'" Enables the even
(62, 64 .. 68) Outputs
3. CEO, CE" and CE2 are AND'ed per customer
instructions.
METAL GATE MOS. 2441,2451,2461,2462
ABSOLUTE MAXIMUM RATINGS (1)
SCHEMATIC DIAGRAM
Operating Ambient Temperature
-250Ct~ +70o C
Storage Temperature
-65°C to +150 o C
Power Dissipation (2) ("Y" Package)
@70oC 1.14W
@70oC 0.80W
("1" Package)
VGG(3)
-20 to +0.3
VDD(3)
-15 to +0.3
Input Voltage (3,4)
-20 to +0.3
OUTPUT STRUCTURE
Vss
-1~
OUTPUT
DC CHARACTERISTICS
T A = -25°C to +70°C; VSS = +5V 15%; VDD = VGG = -12V ±5% unless otherwise noted·(Notes: 8, 9, 10, 11, 12, 14)
_._--_ ..
SYMBOL
VIL
TEST
MIN
Input logic "0"
MAX
TYP
VIH
Input logic "1"
ISS
VSS Pc)wer Supply Current
IGG
IIH
UNIT
CONDITIONS
--
V
3
0.8
14
V
0
20
mA
TA = 25 C
V GG Power Supply Current
1
/-LA
Note 5,
I nput Leakage
1
/-LA
VIN = -12V
TA
=
0
25 C
AC CHARACTERISTICS
T A = 25°C; VSS = +5V ±5%; VDD = VGG = -12V ±5% unless otherwise noted (Notes 9, 10, 11, 12, 14)
-
SYMBOL
VOL
TEST
MIN
Output Logic "0"
TYP
MAX
UNIT
CONDITIONS
V
Note
6
+0.4
V
Note
6
750
ns
Note 13
+2.4
MOS to TTL
VOH
Output Logic" 1"
tA1
Access Time
tAO
Access Time
CIN
Input Capacitance
950
ns
pF
5
Note7,f=1 MHz,VIN=O
NOTES:
1.
Stresses above. those listed under "Maximum Guaranteed Ratings" may cause permanent damage to the device. This is a stress ra!ing only.
Operation of the device at those or any other conditions above those Indicated In the operational sections of the specification is not im~lied.
2.
For operation at elevated temperatures, the device must be derated based on a maximum junction temperature of 150 0 C and a thermal resistance of 70 0 C/W junctic)n to ambient for the "Y" package. The "I" package Is derated based on 100 0 C/W junction to ambient.
3.
These voltages are referonced to network ground terminal (VSS)'
4.
All Inputs are protected against damage by static charge.
5.
The V GG supply may be clocked to reduce device power without affecting access time.
6.
6.8kn to VGG plus 1 standard TTL gate input.
7:
Capacitance measured on lot sample basis only.
8.
Parameter valid over op,erating temperature range unless otherwise specified.
9.
All voltage measurements referenced to ground.
10.
Manufac.turer reserves the right to make design changes and process Improvements.
11.
Typical values are at 25'J C and nominal supply voltages.
12.
Negative logic definition Is employed for this device. i.e., more negative level is logic "1", most positive level is logic "0".
13.
For bare drain devices, T A 1 is primarily a function of the time constant of the load capacitance and external load resistor (tA 1 ~ 4R L CL
+50 ns).
14.
CAUTION: These devices will be permanently damaged If reversed in board or socket.
AC TEST SETUP
TIMING DIAGRAM
+6V
o--r---o
VO
..L
DTL/TTLr ·1"5p··"F
I
10pF
~
-'12V
~
7·41
METAL GATE MOS. 2441, 2451, 2461, 2462
PART IDENTIFICATION TABLE
PACKAGE
OUTPUTS
N2441 I
PART
256 x 4
16-pin Cer. DIP
Bare Drain
N2451Y
128 x 8 or 256 x 4
24-pin Cer. DIP
Bare Drain
N2461Y/CM4030
256 x 8 (EBCDIC-ASCII)*
24-pin Cer. DIP
Bare Drain
N2461Y
256 x 8 or 512 x 4
24-pin Cer. DIP
Bare Drain
N24621
512 x 4
16-pin Cer. DIP
Bare Drain
ORGANIZATION
* Demonstrator
APPLICATIONS
MOS-TTlINTERFACING
+5
+5V
+5V
IN
-12V
=
R1
6.8k for a standard TTL (10 IN
= 1.6mA)
CHARACTERISTIC CURVES
TYPICAL POWER SUPPLY
CURRENT VS.
POWER SUPPl·' VOLTAGE
TYPICAL ACCESS TIME
VS. SUPPLY VOLTAGE
1600
LOiD - 1 tTL INPIUT
1400
25 1--+-+---I----+-+----+---:7/-250 C
K~
1200
"
...........
1000
"'"
800
~
~ i"...........
f'-.-
600
~ +125 O C
r;doc
r--...... 1""-...
+2r
400
15
16
17
18
19
20
Vss - VGG (V)
NOTE: For typical curves, VSS
7·42
= OV.
21
22
23
o~~--~~~~--~~--~~
15
16
17
18
19
20
Vss - VGG IV)
21
22
23
METAL GATE MOS. 2441,2451,2461,2462
NOTE: Blanks are logic 1'5.
EBCDIC
WORD#
CM 4030 TRUTH TABLE
ASCII CODE
BIT NUMBER
EBCDIC
WORD#
1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1 1 0 0 0 0
1 1 1 1 1 1 1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0 0 0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0 0
0 0 0 1 1 0 0
1 0 0 1 1 0 0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 1 0 1 0 0 0
1 1 1 0 1 0 0
1 1 0 1 1 0 0
1 0 1 0 0 0 0
0 1 1 0 0 0 0
1 1 1 0 0 0 0
o
1 1
o
1
001
o
0 0 0
0 0
1 0
1 0
1 0
o
0
1 0 0
1 0 0
0 1 0 1 1 0 0
0 0 0 0 0 1 0
ASCII CODE
BIT NUMBER
1 234 5 6 7
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
0
0
0
1
0
0
1
0
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1 0 1 1 0
1 1 1 1 0
ASCII CODE
BIT NUMBER
EDCDIC
WORD #
1 0
1 0
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
1
0
0
0
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
1
EBCDIC
WORD#
1 2 3 4 5 6 7
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
o 1
0 1
0 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1 0
o 1
0 1
1 1
1 1
0 0
0 0
1 o
0
1
1
1
1
1
1.
1
1
1
1
1
1
1
1
1
1
o
o
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1 0 0 0 0 0
0 1 0 0 0 0
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
ASCII CODE
BIT NUMBER
1 2
3 4 5 6 7
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
1
1
0
o
0
0
0
0
0
1
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
0
1
1
1
1
0
0
0
1 o 0 1
1 o 0 1
1 1 ·1 1
1 o 0 1
1 0 0 1
1 0 0 1
o 1 0 1
o 1 0 1
o 1 o 1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
o
o
0
0
0
0
0
1
1
1
1
1
1
1
1 0
1
1
1 1
1 1
0 0
0 0
1 0
1
1
o 1
0 1
0 1
1 1
1 1
1 1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
o 1 1
1 1 1
1 1 1
0
0
0
0
0
0
0
0
0
0
o
o
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
o
1
1
7-43
METAL GATE MOS. 2441,2451,2461,2462
EXERPT FROM SOFTWARE PACKAGE (CARD FORMAT)
CARDS 2 THROUOH 129 (4 X 258 Oroanlutiofl only)
~
~lNGATCOLUMNI
COOED 10' IXN"l
OR-'SINGLE
IF 'CODED" PUNCH THE 81NARY CQOr CHIP
SELECT1,. 1011 IF ·SINGtE"\.£AV[
PUNCH
T~E
ROM ORGANllATION OES1R£D
N2436V SlGNIfICl HAl THE FASTUT A.O.M:.
IIII
I
EACH CARD SPECIFIES THE OUTPUT OF TWO 4·811
WORDS IN COLUMNS 1 THAOUGH 8. THE DECIMAL
11111 II
IIII I
III
III
EQUIVALENT OF THE BINARY CODED INPUT
ea0 ~ ~ n~ ~ ~~ 0 0 ~~ noD ~~~ ~ '~, ~ ~ ~ ~ ~%!~~~~!! ~ ~~!~ ~~~~!~!~.~~ ~~~!!~!!!~~!!~\!,~!!!! ~~~.~\~~},~!
ADDRESS IS PUNCHED IN COLUMNS 7,8, 79, AND 80
11.11"'111'1.'11"1"1'11111'111111111'111111'111111111111111111111111111111111
1.1I)(156.)(512£1C
PUNCHMOS FOR AN MOS QUTPUl
PUNCHTll FOR ATTLOUTPUT 111ARL
PUNCH THE BASIC DEVICE TVPEOESIREO
.e N24101 N24]OY fT<..
;~~:~~~:EU~~~~~ ~!~~=~l~B~7EAR
lHISSHOUlDINCLU06 CUSTOMER PART
~
~OL'TPUTFORWOROS02SS
THE ABOVE SPECIFIES A "CODED" ROM WITH THE BINARY" CODED CHIP SELECT "101" ORGANIZED 8)( ~56
f'UNCHO[CIMAL EQU1VALENlOF BINARV
COoEO INPUT ADDRESS OF TH(WQAQCOA
RESPONDING TO THE OUTPUTS PUNCHED IN
WITH TTl OUTPUTS (BARE DRAINI. THE BASIC DEVICE TVP, IS A N2436V I"V" INDICATES A 24·PIN CERAMIC
DIP N INDICATES TEMPERATURE RANGE' -25 C - "70·'C.I
COLUMN 18 HUNDREDS DIGIT
COLUMN 19 TENS DIGIT
COLUMN 80 UNITSQIGtT
EXAMPLE
CARDS 2·129 AND CARDS 2 251
CARO:2 THROUGH 129 IB x t:lBO.;.n,ntionl
2 THROUGH 268 18 x 256 O.g.IIniutionl
EACH CARD SPECIFIES THE OUTPUT OF ONE 8 BIT
WORD IN COLUMNS 1 TUROUGH 8 THE DECIMAL
EOUIVALENT OF THE BINARY CODED INPUT ADDRESS
FOR THAT WORD IS PUNCHED IN COLUMNS 78. 79 AND 80
~~LUMNS ~ OUTPUTS 91 THROUGH 98 IN
COLUMNS ONE THAOUGH EIGHT RESPECTIVELV
CAROS:2 THROUGH 2571~ X !12 Oro-nlutton onlvl
EACH CARD SPECIFIES THE OUTPUT OF TWO 4·BIT
WORDS IN COLUMNS 1 THROUGH 8 THE DECIMAL
EQUIVALENT OF THE BINARY CODED INPUT
ADDRESS IS PUNCHES IN COLUMNS 78, 79. AND 80
OATA
;;u;:;c;; OUTPUT FOR WORDS 0 121
'/'01010'0
/'1'00100
PUNCH OUTPUT FOR WORDS 128255
PUNCHOECIMALEOUIVALENTOF61NARV
cOOEO INPUT ADORESS WHICH CORRtS
PONOSTOTHEOUTPUTSPUNCHEDIN
COLUMN 18 HUNDREOSDIGIT
COLUMN 19 T[NSOIGIT
COlUMN8CJUNITSOIGIT
~ ~~.,~.,~ ~ 0 ~ DDu~ ~ ~ ~~ 0 O!, ~ e~ u~~!~~ 0 ~~,:~~ ~!~~~.~,~!~ ~ ~~~ ~~ ~ ~~ O.,~\~~~O ~'~I~O ~ ~~~. 0 ~,~'~~'~,~'~~!
PUNCHOECIMAL EQUIVALENT OF BINARV
CODEDINI'UTADORESSCORAESPONOING
TOTHE OUTPUTS PUNCHED IN COLUMNS 14
COLUMN 18 HUNDAEDS DIGIT
COLUMN 19 TENS DIGIT
COLUMN 80 UNITS DIGIT
1111111'11""11'11"'11111111,1111111111111111111'111111,'1111"1'1111111111111 ......
• OUTPUTS 81 THROUGH Bo ARE IN COLUMNS 1 THROUGH 8 RESPECTIVELY
• DECIMAL EQUIVALENT OF BINARY CODED INPUT AODRI!SS IS IN COLUMNS 18, 19, AND 80
•
FOR 8)( 128 AND 8 X 2S6 ORGANIZATIONS - OUTPUTS ARE 81 THROUGH 88 RESPECTIVE LV
•
FOR 4 X 512 ORGANIZATION
WORD
WORD
WORD
WORD
VIC
YOUR
~OW;NY'S
111111
t
B4 RESPECTIVEl Y
88 RESPECTIVELY
B4 RESPECTIVEL Y
B8 AESPECTIVEL V
NA.;E,
II
il:'~ 0 ~ ~~ 0 0 01 ,0 [:~. nn; ~ ~ q ~ o~ ~ on ~~,~ ~ ~ 0 ~~ 0 ~.~~,~~!?~ 0 ~D ~ o~~ ~~~ ~.O~.;' R,~,~ ~~,~~G ~ ~?,~,~,~~.~~!
~ 1111: ~ 1'11,,'1, I I I ' . ,
7·44
000 OUTPUTS Bl THROUGH
256 OUTPUTS 85 THROUGH
010 OUTPUTS 81 THROUGH
286 OUTPUTS 85 THROUGH
:. '1I'' i 11111 11, 11111111111111111l1,1111111111111I111111J 1 _ ...
WORD 000 OUTPUTS 81
WOAD 128 OUTPUTS 85
WORD 010 OUTPUTS 81
WORO 138 OUTPUTS B6
THROUGH
THROUGH
THROUGH
THROUGH
84 RESPECTIVEL V
88 RESPECTIVELV
54 RESPECTIVELY
B8 AESPECTIVELV
SmDotiCS
FULLY DECODED, 256 X1STATIC
RANDOM ACCESS MEMORY
2501
SILICON GATE MOS 2500 SERIES
DESCRIPTION
BIPOLAR COMPATIBILITY
The Signetics 2500 Series 256 x 1 Random Access Memory
employs enhancement mode P-channel MOS devices integrated on a single monolithic chip. It is fully decoded, permitting the use of a 16-pin dual in-line package. Complete
static operation requires no clocking.
All inputs of the 2501 can be driven directly by standard
bipolar integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 2.0 mA,
sufficient to drive one standard TTL load.
FEATURES
• FULLY DECODED ADDRESS
• ACCESS TIME -1.0~s GUARANTEED
• POWER DISSIPATION -1.6mW/BIT MAXIMUM
DURING ACCESS
• STANDBY POWER DISSIPATION - 50~W/BIT
• DTL AND TTL COMPATIBLE
• CHIP SELECT AND OUTPUT WIRED-OR CAPABILITY
FOR EASY EXPANSION
• STANDARD 16-PIN DIP SILICONE PACKAGE
• SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
•
VCC = +5V, VDD = VD = -9V
APPLICATIONS
POWER DISSIPATION
The maximum power dissipation of 1.6mW/bit is required
only during Read or Write. For standby operation, 50~W/bit
is obtained by removing VD and reducing VDD to -2.0V.
Removal of VD alone will cut power dissipation by a factor
of 1.5.
SPECIAL FEATuRE
The outputs of the 2501 are effectively open circuited when
the device is not selected (logic 1 on chip select). This feature allows OR-Tying for memory expansion.
PART IDENTIFICATION TABLE
TYPE
25018
PACKAGE
16-pin Silicone DIP
OP. TEMP. RANGE
O°C. to+70°C.
25011
16-pin Ceramic DIP
O·C. to +70 C.
--
PIN CONFIGURATION (Top View)
SMALL BUFFER STORES
SMALL CORE MEMORY REPLACEMENT
BIPOLAR COMPATIBLE DATA STORAGE
B/I PACKAGE
SILICONE PACKAGING
Low cost silicone DIP packaging is implemented and reliability is assured by the use of Signetics unique siiicon gate
MOS process technology. Unlike the standard metal gate
MOS process the silicon material over the gate oxide passivates the MOS transistors, and the deposited dielectric
material over the silicon gate-ox ide-substrate structure provides an ion barrier. In addition, Signetics proprietary surface passivation and silicone packaging techniques result in
an MOS circuit with inherent high reliability and demonstrating superior moisture resistance, mechanical shock and
ionic contaminatioQ barriers.
11
16
14
13
12
11
1.
2.
3.
4.
5.
6.
7.
8.
Address 6
Address 8
Address 7
VD
Vcc
Address 5
Address 1
V DD
16.
15.
14.
13.
12.
11.
10.
9.
Chip Select
R/W
Data Out
Data Out
Data In
Address 4
Address 2
Address 3
10
PROCESS TECHNOLOGY
The use of Signetics' unique Silicon Gate Low Threshold
Process allows the design and production of higher performance MOS circuits and provides higher functional
density on a chip than other MOS technologies.
7-45
SILICON GATE MOS. 2501
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied.
2. For operating at elevated temperatures the device must be
o
derated based on a +150 C maximum junction temperature and
o
a thermal resistance of ,150 C/W junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless
MAXIMUM GUARANTEED RATINGS (1)
Operating Temperature
Storage Temperature
All Input or Output Voltages with
Respect to the Most Positive Supply
Voltage, VCC
Supply Voltages VOO and Vo with
Respect to V CC
Power Dissipation at T A = 70° C
O°C to +70°C
-65°C to +150°C
+O.3V to -20V
specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and improvements.
7. Typical values are at +25°C and nominal supply voltages.
8. V CC tolerance is ±5%. Any variation in actu~1 V CC will be
tracked directly by V • V IH and V OH which are stated for
IL
a V CC of exactly 5 volts.
-18V
640mW
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This Is a stress rating
NOTE: Special devices are available for operation at VDD
= -7V,
VD
= -10V.
Contact your Signetics Representative fQr.-detalis.
DC CHARACTERISTICS'
(T A = O°C to 70°C, VCC = +5V (8), VOO = Vo = -9V ±5%, unless otherwise specified. See notes below)
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
III
Input Load Current
(All Input Pins)
<1.0
500
nA
VIN = O.OV; TA = +25°C
ILO
Output Leakage Current
<1.0
1000
nA
VOUT = O.OV, Chip Select
Input = +3.3V, T A = +25°C
100
Power Supply Current, VOO
13.0
18
mA
TA=+25°C, VOO=VO=
·-9V
10
Power Supply Current, Vo
8.5
12
mA
IOL = O.OmA TA
VOO = Vo =-9V
VIL
Input "Low" Voltage
-12
VCC-4.5
V
VIH
Input "High" Voltage
VCC-2.0
VCC+0.3
V
lOll
Output Sink Current
3.0
6
mA
VOUT = +O.45V, TA = +25°C
IOL2
Output Sink Current
2.0
5
mA
VOUT = +O.45V, T A = +70°C
IOL3
Output Sink Current
mA
VOUT = -0.7 V
IOH1
Output Source Current
-3.0
4
mA
VOUT = O.OV, T A = +25°C
IOH2
Output Source Current
-2.0
3
mA
VOUT=O.OV, TA=+70oC
VOL
Output "Low" Voltage
V
IOL =3.0mA
VOH
Output "High" Voltage
V
IOH =-100~A
CIN
I nput Capacitance
(All Input Pins)
7
10
pF
VIN =+5.0V
f= 1 MHz
COUT
Output Capacitance
7
10
pF
VOUT=+5.0V
f= 1 MHz
--
7-46
6
-0.7
+3.5
13
+0.45
+4.5
= +25°C
SILICON GATE MOS. 2501
SWITCHING CHARACTERISTICS
o
Guaranteed Limits T A = Oo·C to +70 C, VCC = +5V (8) , VOO= Vo = -9V ± 5% except as noted.
READ CYCLE
SYMBOL
LIMITS (tlsec) MAX
TEST
Access Time
ta
WRITE CYCLE
1.0J,lSec
TEST
SYMBOL
LIMITS (tlsec) MIN.
two
Address to Write Pulse Delay
0.3
twp
Write Pulse Width
0.4
tw
Write Time
0.3
too
Data-Write Pulse Overlap
0.1
TEST SETUP FOR SPEED MEASUREMENT
BLOCK DIAGRAM
• "AGE
IYNCHIIONOOa
PRIEIIT COUNTE"
A,7
",'0
A,.
a."
~,.
allo----..J
NOTES:
1. Each clock time is split into a Read fOllowed by a Write. Read
and Write times can be varied by adjustment of the "delay" and·
"width" controls of the pulse generator.
2. Data generator produces a 256-bit block of data. 32 bits repeated
8 times. "PCM" mode used so data can be changed in 32 bits of
the 2501 from one cycle to the next.
3. ~~IJnf5u~~ to the 2501 are standard TTL outputs with Vce =
4.
Ac:cess time is measured between A 1 (least significant address
input) and points 1 and 2.
CONDITIONS OF TEST
Input pulse amplitudes: 0 to +5V, Input pulse rise and fall times:
< 10 nsec. Speed measurements referenced to
1.5V levels.
Output load is 1 TTL gate; measurements made at output of TTL gat'; (tpd";;; 10 nsec)
READ CYCLE (For Measurement Purpose Only)
A.-
WRITE CYCLE (For Measurement Purpose Only)
,
At)\(- - - - - - - - - - .
a~<._
.
RlWj~
oUTPUTS
~-
-
'.
-...;....-
,r
~--------------
RIW
DATA
--1-----
.N----------7·47
SILICON GATE MOS. 2501
TYPICAL CHARACTERISTICS
ACCESS TIME VERSUS
TEMPERATURE
ACCESS TIME VERSUS
LOAD CAPACITANCE
1500
1.000
--
100
10lI0
i
~
~
;:
~
(1)
~
----
~
~
~
~-
---
~
600
200
o
o
110
o
200
110
100
o
10
20
LOAD CAPACITANCE 'pFI
30
110
110
70
TEMPERATURE '"CI
TYPICAL ACCESS TIME AND POWER DISSIPATION
VERSUS SINGLE POWER ~UPPLY VOLTAGE
POWER SUPPLY CURRENT VERSUS
. POWER SUPPLY VOLTAGE
20r-----~------~----~------~
~
~
~
600 1 - - - - - - + - - - + - - - - - 1 < - - - - - - 1 300
~
i5
!
400
1----+---
200
200 L...-____--IC:_ _ _...L...-_ _- - "_ _ _.... 100
15
16
Vcc-Vo (VI
Vee - PUWfH SUPPl Y VOL T AGE IV I
OUTPUT CURRENT VERSUS
TEMPERATURE
'z"
:0
--
V~D
=:VU)-9
VOUT ~04!JV
r--
~
z
a:
a:
:::>
u
r--
--- -r--
:::>
:::>
o
(1) NOTE: For all typical curves. Vee
7·48
= 5V,
VOO
=
Vo
= -9V,
TA
= 25°e
(unless otherwise noted).
SI LICON GATE MOS. 2501
WRITE
TYPICAL CHARACTERISTICS (Cont'd)
OUTPUT CURRENT VERSUS
SUPPLY VOLTAGE
24
21
TYPICAL 0
VOO"VO
Vcc" +6V
T A "26"C
18
/
15
/
12
V
A "Write" command is a logic "1" (~+3.3V) level to the
R/W control. This should be presented to the chip no sooner
than 300 nsec after the application of an address code. Th is
time delay is necessary for proper address decoding. This
"Write" command has to be present for at least 400 nsec to
insure that the information is written into the memory. The
"Write" command should be off (i.e., memory should be in
"Read" mode) by the time the address code is changed. The
input data should be present for at least the last 300 nsec,of
the "Write" command.
IOL......
V~
-8
./
CHIP SELECT
/
The memory array is inhibited with the application of a logic
"1" (~+3.3V) to the Chip Select control. This will render
both R/W and Data Input leads ineffective and will stop information transfer through the output buffer. The address
decoder, however, will not be inhibited. This feature allows
an effective increase in memory speed. (See below) The output leads are open while the memory array is inhibited. This
allows OR-Tying of many memory arrays.
~~
"" ""'r-..
"
-9
-12
IOH
-16
RANDOM ACCESS MEMORY
~
-18
~
"
-21
-24
-7
-8
-9
-10
-11
-12
-13
SUPPLY VOLTAGE (Voo" V O' (VOLTS'
APPLICATION INFORMATION
OPERATION
The 2501 is a 256 x 1 Random Access Memory element. It
is fully decoded and provides control for ReadlWrite and
Chip Select modes. The operation of this element is described below.
ADDRESSING
An a-bit address code will select anyone of 256 bits for
either Read orWrite operation. All address input logic levels
are compatible with standard bipolar TTL or DTL logic
levels.
READ
A logic "0" level ('VOV) applied to the RIW control will
result in a Read operation. This can be presented to the RIW
control simultaneously or before application of an address
code. In this mode the information from the memory will
be available on the outputs less than 1Msec later than the application of an address code. Note that there is no need to rewrite the data into the memory after a read operation since
the read is non-destructive.
Arbitrary size memories can be built by tying appropriate
numbers of 2501's together. Figure 1 shows a block diagram of a memory system containing 256 N words by M
bits. For example, if the memory size were 4096 words by
12 bits, N = 16 and M = 12. Thus the number of 2501's
required is M x N = 192. The address inputs A1 through
Aa are common to all the rows. Inputs C1 through Cn
provide the column select and are wired to the Chip Select
inputs of the 2501 's. For the example of the 4096 word
memory, a 12-bit address must be specified. The first a
bits would drive inputs A1 through Aa directly. The remaining 4 bits would have to be decoded externally into
the 16 lines required for the 16 columns. A block diagram
of the 4096 x 12 memory is shown in Figure 2. Any
number of 2501's can be OR-tied together, however, access
time is affected by capacitive loading (approximately 1
nsec/pF). Each 2501 output represents 7 pF (typical) of
loading, but the amount of stray capacitance contributed
by the printed circuit board wiring can vary greatly and
must be determined for each application. Figure 3 shows
two different bit line organizations where the capacitive
load that must be driven by the 2501 is reduced by employing logic gates to perform the OR-ing function. The organization of Figure 3b results in the minimum load capacitance but requires more gates per bit line than other
organizations.
SEQUENTIAL MEMORY
On applications such as program memory or table lookup,
where memory operations are highly sequential, but nonsynchronous, the memory may be organized for a faster
7·49
SILICON GATE MOS. 2501
SEQUENTIAL MEMORY (Cant'd),
LOW POWER OPERATION
average memory cycle than in the true random access case.
This involves using the fact that access may be made
through the chip select input in 0.2 J.lsec (typically) where
a typ(cal access time if one of the address inputs (A 1-AS)
changes; is O.S J.lsec. For the case of the 4096 word memory
organized in this fashion information can be read out at an
average access time of 0.25 J.lsec since access is made through
the Chip Select input 15/16 of the time.
Another feature of this memo~y element is its capability
of operating at very low standby power levels. The only
time the element has to dissipate full power (-1.6mW/bitl
is when it is exercised by either "Write" or "Read" operation. In the standby mode, when the chip will only store
information, but does not need to be accessed, the peripheral power supply (VOl is completely shut off. This will
immediately cut the total power drain by a factor of 1.5.
RMo-----~_1~----------~~r_----~--__,
r---------~+_.---------+_;_~--__ol,
L---------+-+-4---------+-;-~----O~
INI
o-T""""f-+-+-....-+----------......;r-------------'
~--------r_+-.---------+-+_~--__o12
M· # IITS
- "............... ,
2111N·#WORDS
-/-4---Q
i2
I
==~Im
- 210'
.......-------It--.................- -
a;;;
-
INlIIo-...L-----_-----------~........- - - - -
FIGURE 1. ORGANIZATION OF 2501's INTO LARGER'MEMORY
I,
B,
Bz
i2
112
RM
B,2
FIGURE 2. ORGANIZATION OF 4096 WORD BY 12-BIT MEMORY
7·50
liT LINE
OUTPUTS
SILICON' GATE MOS. 2501
.....-----------2601'.---------------,
a. Combination of wire-ORlng and 10gic-ORing of 2501's
r------------2601'.--------------,
b. Logic-ORing of 2501's
FIGURE 3. BIT LINE ORGANIZATIONS TO MINIMIZE CAPACITIVE LOAD-4096 WORDS
PACKAGE MAXIMUM POWER DISSIPATION
1000
.........
. 800
i
!
I!
"
~
~
800
"
400
~
~
i
200
10
20
30
40
AMBIENT TEMPERATURE
60
60
70
rei
7·51
~
::D
n
~
r
c: 0n
=4' 2
en
",.:».1."_'"
;-------------,..----_:---
n
::r:
m
3:
G')
»
-I
m
»
s:
-I
n
I
0
en
•
I\)
U1
0
~
s:
(I)
3
o
-<
s::>~========+.;::+::=====
,& :
..,,,
0:-.::4"
~no ~l:;,,~,+---+-----oLl
."~.,,a
£':
:
a"
FULLY DECODED 256 xl STATIC
RANDOM ACCESS MEMORY
!ii!lDotiC!i
25LOl
SILICON GATE MOS 2500 SERIES
DESCRIPTION
The Signetics 25L01 256 x 1 Random Access Memory
employs enhancement mode P-channel MOS devices integrated on a single monolithic chip. It is fully decoded, permitting the use of a 16-pin dual in~line package. Complete
static operation requires no clocking. The 25L01 is optimized
with +5 and -12V supplies.
FEATURES
Removal of VD alone will cut power dissipation by a factor
of almost 3.
TRI-STATE OUTPUT
The outputs of the 25L01 are effectively open circuited
when the device is not selected (logic 1 on chip select).
This feature allows OR-tieing for memory expansion.
PART IDENTIFICATION TABLE
•
FULLY DECODED ADDRESS
•
ACCESS TIME -1.0ps GUARANTEED
TYPE
•
POWER DISSIPATION -1.7 MW BIT MAXIMUM
DURING ACCESS
STANDBY POWER DISSIPATION - 100 pW/BIT
•
•
DTL AND TTL COMPATIBLE
•
CHIPSELECT AND OUTPUT WI RED-OR CAPABILITY
FOR EASY EXPANSION
•
STANDARD 16-PIN DIP SILICONE OR CERAMIC'
PACKAGE
•
SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
•
VCC = +5V, VDD = VD = -12V
PACKAGE
OP. TEMP. RANGE
25L01B
16-pin Silicone DIP
O°C to +70°C
25L011
16-pin Ceramic DIP
O°C to +70°C
PIN CONFIGURATION : fop View)
B/I PACKAGE
16
15
14
APPLICATIONS
13
SMALL BUFFER STORES
SMALL CORE MEMORY REPLACEMENT
BIPOLAR COMPATIBLE DATA STORAGE
12
11
1.
2.
3.
4.
5.
6.
7.
8.
Address 6
Address 8
Address 7
VD
VCC
Address 5
Address 1
Voo
16.
15.
14.
13.
12.
11.
10.
9.
Chip Select
R/W
Data Out
Data Out
Data In
Address 4
Address 2
Address 3
10
SI LICONE PACKAGING
Low cost silicone DIP packaging is implemented and reliability is assured by the use of Signetics unique silicon gate
MOS process technology. Unlike the standard metal gate
MOS process the silicon material over the gate oxide passivates the MOS transistors, and the deposited dielectric
material over the silicon gate-oxide-substrate structure provides an ion barrier. In addition, Signetics proprietary surface passivation and silicone packaging techniques result in
an MOS circuit with inherent high reliability and demonstrating superior moisture resistance, mechanical shock and
ionic contamination barriers.
BLOCK DIAGRAM
BIPOLAR COMPATIBILITY
All inputs of the 25LOl can be driven directly by standard
bipolar integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 2.0 mA,
sufficient to drive one standard TTL load.
POWER DISSIPATION
DATA, ..
OUT
"iW15
0---------1
The maximum power dissipation of 1.7 mW/bit is required
only during Read or Write. For standby operation 100 pW/
bit is obtained by removing VD and reducing VDD to -8.0V.
7-53
SI LICON GATE MOS. 25L01
MAXIMUM GUARANTEED RATINGS (1)
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device of these or any other
condition above those indicated in the operation sections of this
specification is not implied.
O°C to +70°C
Operating Temperature
2.
For operating at elevated temperatures the device must be
0
derated based on a +150 C maximum junction temperature and
a thermal resistance of 150° C/W junction to ambient (" S" pkg.)
0
("I" pkg., 100 C/W).
.
3.
All inputs protected against static charge.
4.
Parameter valid over operating temperature range unless otherwise specified.
-65°C to +150°C
Storage Temperature
All Input or Output Voltages with
Respect to the Most Positive Supply
Voltage, VCC
+0.3V to -20V
Supply Voltages VOO and Vo with
Respect to V CC
Power Oissipation at T A = 25°C "8" pkg.
"I" pkg.
-18V
640mW
800mW
5.
All voltage measurements are referenced to ground.
6.
Manufacturer reserves the right to make design and process
changes and improvements.
7. Typical
values
are
at
+25° C and nominal supply voltages.
DC CHARACTERISTICS (TA=O°Cto 70°C, VCC =+5V ± 5%, VOO=VO=-12V±5%unlessotherwise specified. See
notes above).
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
III
I nput Load Current
(All Input Pins)
<1.0
500
nA
VIN = O.OV; T A = +25°C
ILO
Output Leakage Current
<1.0
1000
nA
VOUT = O.OV, Chip Select
Input = +3.3V, T A = +25°C
100
Power Supply Current, VOO
5
9
mA
T A = +25°C
10
Power Supply Current, Vo
11
16
mA
IOL = 0.0 mA
T A = +25°C
V IL
Input "Low" Voltage
-12
VCC-4.5
V
VIH
Input "High" Voltage
VCC-2.0
VCC+0.3
V
IOL1
Output Sink Current
3.0
6
mA
VOUT = +0.45V, T A = +25°C
IOL2
Output Sink Current
2.0
5
mA
VOUT = +0.45V, T A = +70°C
IOL3
Output Sink Current
mA
VOUT = -0.7 V
IOH.1
Output Source Current
-3.0
4
mA
VOUT = O.OV, TA =+25°C
IOH2
Output Source Current
-2.0
3
mA
VOUT = O.OV, T A = +70°C
VOL
Output "Low" Voltage
V
IOL =3.0mA
VOH
Output "High" Voltage
V
IOH =-100pA
CIN
I nput Capacitance
(All Input Pins)
7
10
pF
VIN =+5.0V
f = 1 MHz
COUT
Output Capacitance
7
10
pF
VOUT = +5.0 V
f= 1 MHz
7·54
6
-0.7
+3.5
13
+0.45
+4.5
SI LICON GATE MOS. 25L01
o
SWITCHING CHARACTERISTICS Guaranteed Limits T A = 0 to +70 e, Vee= +5V ±5%, VDD = VD = -12V ±5%
READ CYCLE
SYMBOL
WRITE CYCLE
LIMITS (Msec) MAX
TEST
SYMBOL
TEST
LIMITS (Msec) MIN.
--
two
Address to Write Pulse Delay
0.3
twp
Write Pulse Width
0.4
tw
Write Time
too
Data·Write Pulse Overlap
~
1 Msec
Access Time
ta
~----~-
-----------------0.3
...--..
0.1
---~----
..
-----
TEST SETUP FOR SPEED MEASUREMENT
I STAGE
NL.SE GENERATOR
SYNCHRONOUS
'RESlT COUNTER
NOTES:
1.
Each clock time is split into a Read followed by a Write. Read and Write times can be varied by adjustment of the "delay" and "width"
controls of the pulse generator.
2.
Data generator produces a 256-bit block of data, 32 bits repeated 8 times. "PCM" mode used so data can be changed in 32 bits of the 25L01
from one cycle to the next.
3.
All inputs to the 25L01 are standard TTL outputs with VCC
4.
Access time is measured between A 1 (least significant address input) and points 1 and 2.
CON DI TI ONS 0 F TEST
= +5V
±5%.
<
Input pulse amplitudes: 0 to +5V, Input pulse rise and fall times:
10 nsec. Speed measurements referenced to 1.5V levels.
Output load is 1 TTL gate; measurements made at output of TTL gate (tpd ~ 10 nsec).
READ CYCLE (For Measurement Purpose Only)
Al-A8~/- -
-
-
-
-
-
-
-
WRITIE CYCLE (For Measurement Purpose Only)
--
/
~~~_~~_n
,---------------
cs
_ _ _ _ _ _ _ __ _
R/w)_ _
· '. ,rrOUTPUTS
-
-
-
---
R/W
---11-----
DATA I N - - - - - - - - - - -
APPLICATION INFORMATION: Reference 2501 specifications.
7·55
SILICON GATE MOS. 25L01
TYPICAL CHARACTERISTIC CURVES
ACCESS TIME VERSUS
SUPPLY VOLTAGE
ACCESS TIME VERSUS
TEMPERATURE
1400
i
1300
25LOl
TA = 25"C
Vcc = +5V
OUTPUT CURRENT VERSUS
SUPPLY VOLTAGE
25
I
700 t - - - t - - t - - + - - - t - V C C = t5V
VOO = Vo = -12V
1200
15
1100
-r---
\
1000
_\
900
\
800
- - ---f---
-f-~--
r'\.
600
..--
~-+----+---~~--+--~~
f---//
".........
--
' -r--
500
-
400
10
8
11
12
13
500
15
10
15
-~--.
20
20
30
40
50
60
25
70
8
ACCESS TIME VERSUS
LOAD CAPACITANCE
14
I
12
r- TA = 25"C
25LJl
Vcc = t5V
= -12V
700t---+-~-~-+-_4--+-_f___1
---
~
----
/
10
1
0/
/V
V
600 1--+-*""'--+---,--
3.5 I---+--+--+--+--+-----="l'-~_
f---- ------
---~~--
10
20
30
40
50
-
60
--
V
-500 ' - -......._-L._-'-_-'----J_---'-_-'-~
200
50
150
100
70
LOAD CAPACITANCE IpFI
TEMPERATURE I CI
15
V
I--+--+--+--+-"""".!:--+------l
...................
4.0
14
POWER SUPPLY CURRENT
VE RSUS SUPPL Y VOL. T AGE
-
""~-----
13
Voo =Vo I-VI
5.5 r - - - r - - - r - - - r - - , - - , - - , - - ,
25LOI
- VCC = ·t5V
VOO = Vo
12
11
10
TEMPERATURE I CI
OUTPUT CURRENT VERSUS
TEMPERATURE
5.0~
IOH
V
10
= Vo I-VI
Voo
~
"...,..,. ~
-5
~
~
14
...-..--r-rDL
10
6001--~-+--+--+_-~~~~~~
700
4.5
25LOI
VCC = +5V TA = 25"C
20
/
/V
,/
<: "
. . .V
/"
V
V
V
2
8
10
11
12
13
14
15
16
Voo = Vo I-VI
ACCESS TI ME VE RSUS
SUPPLY VOLTAGES
TYPICAL OPERATING AREA
14
GUARANTEED OPERATING AREA
12
~
o
>
10
, 8
10
12
Voo I-VI
7·56
14
16
!ii!lDotiC!i
1024-81T CAPACITY MULTIPLEXED
DYNAMIC SHIFT REGISTERS
2502
2503
2504
SILICON GATE MOS 2500 SERIES
DESCRIPTION
BIPOLAR COMPATIBILITY
These Signetics 2500 Series 1024-bit multiplexed dynamic
shift registers consist of enhancement mode P-channel MaS
devices integrated on a single monolithic chip. Due to onchip multiplexing, the data rate is twice the clock rate.
The data inputs of these registers can be driven directly by
standard bipolar integrated (TTL, DTL, etc.) or by MaS
circuits. The bare drain output stage provides driving capability for both MaS and bipolar integrated circuits (one
standard TTL load).
FEATURES
PIN CONFIGURATIONS (Top View)
•
•
10 MHz TYPICAL DATA RATE
THREE CONFIGURATIONS-QUAD 256, DUAL 512,
SINGLE 1024
11
•
LOW POWER DISSIPATION-40 J,.LW/bit at 1 MHz
DATA RATE
14
16
13
•
LOW CLOCK CAPACITANCE-140 pF
•
TTL, DTLCOMPATIBLE
12
•
STANDARD PACKAGES - 8 LEAD TO-99, 8-PIN
AND 16-PIN DUAL IN-LINE PACKAGE
SIGNETICS P-MOS SILICON GATE PROCESS
AND SILICONE PACKAGING TECHNOLOGIES
10
•
11
1.
2.
3.
4.
5.
OUT 1
NC
IN 1
1
VCC
6. OUT2
7. NC
8. IN 2
18
18
16.
15.
14.
13.
12.
11.
10.
9.
IN 4
NC
OUT4
NC
Voo
2
IN 3
OUT3
8
APPLICATIONS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST BUFFER MEMORIES
CRT REFRESH MEMORIES
DELAY LINE MEMORY REPLACEMENT
PROCESS TECHNOLOGY
Use of low threshold silicon gate technology allows high
speed (10 MHz typical) I while reducing power dissipation
and clock input capacitance dramatically as compared to
conventional technologies.
The use of low voltage circuitry minimizes power dissipation and facilitates interfacing with bipolar integrated
circuits.
SI LICONE PACKAGING
Low cost silicone DIP packaging is implemented and reliability is assured by the use of Signetics unique silicon gate
MaS process technology. Unlike the standard metal gate
MaS process, the silicon material over ttw gate oxide passiYates the MOS transistors, and the deposited dielectric material over the silicon gate-ox ide-substrate structure provides
an ion barrier. In addition, Signetics proprietary surface
passivation and silicone packaging techniques result in an
MaS circuit with inherent high reliability and demonstrating superior moisture resistance, mechanical shock and ionic
contamination barriers.
2
7
2603V
3
8
,4
&
1. OUT 2
2. IN2
3.4>2
4. Voo
1. OUT 1 5. OUT 2
8. VCC
2. IN 1
3. 4>1
6. IN 2
7. 4>2
4. VCC
8. Voo
1. NC
2. 'IN
5. OUT
7. 4>1
6. IN1
5. OUT1
B
2
7
, 2504V
3
6
4
6
1. OUT
2. 2
3. NC
8. VCC
7. NC
6. 1
4.
5. IN
Voo
6. NC
3. 4>1
7. 4>2
4. VCC
8. Voo
PART IDENTIFICATION TABLE
TYPE
25028
25021
2503TA
2503V
2504TA
2504V
FUNCTION
Quad 256-bit
Quad 256-bit
Dual 512-bit
Dual 512-bit
Single 1024-bit
Single 1024-bit
PACKAGE
16-Pin Silicone DIP
16-Pin Ceramic DIP
TO-99
8-Pin DIP
TO-99
8-Pin DIP
7-57
SILICON GATE MOS. 2502. 2503. 2504
MAXIMUM SIGNETICS GUARANTEED RATINGS(1)
Operating Ambient Temperature(2)
Storage Temperature
Power Dissipation(2) at T A = 70°C
T A ,and V Package
B Package
Data and Clock Input Voltages
and Supply Voltages with
respect to V CC(3)
O°C to +70°C
-65°C to + 150°C
POWER DISSIPATION VERSUS DATA RATE
535mW
640mW
TVPlCAL.
T.-mOc
.1-85,.
~·85",
+0.3V to -20V
/
V.·~l1V
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent d~mage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of th is specification is not iinplied.
2. For operating at elevated temperatures the device must be
o
derated based' on a +150 C maximum junction temperature and
a thermal resistance of 150°C/W {TA and V package)or 125" C/W
~
Z
I.
o
~
~
o
a:
/
~.
'(8 package).
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless
specified.
5, All voltage measurements are referenced to ground,
6. Manufacturer reserving the right to make design and process
changes and improvements.
7. Typical values at +25°C and nominal supply voltages.
8. V CC tolerance is ±5%. Any variation in actual V CC will be
tracked directly by V I L' V I Hand V OH which are stated for
a V CC of exactly 5 volts.
/
V
/
/
/
DATA RATE I"'a)
9. When cascadIng use 140 ns mInImum to allow
data set.up tIme for drIver regIster.
DC CHARACTERISTICS
T A = O°C to +70°C; VDD = -5V ±5%; VCC = +5V(8) unless otherwise noted. (See Notes 4,5,6,7).
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
VIN = VCC to VDD, T A = 25°C
III
Input Load Current
10
500
nA
ILO
Output Leakage Current
10
1000
nA
ILC
Clock Leakage Current
1000
nA
10
V¢l = V¢2 = -10V
VOUT = O.OV, T A = 25°C
VILC = -10V
T A = 25°C
Outputs at logic "0",4 MHz data
rate,¢l = ¢2 = 85ns
100
Power Supply Current
15
25
mA
TA = 25°C
7·58
1.05
V
3.2
5.3
V
Clock Input "High" Voltage
4.0
5.3
V
Clock Input "Low" Voltage
-10
-12
V
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
VIHC
VILC
continuou~
operation, V I LC = -12V
SILICON GATE MOS. 2502,2503,2504
AC CHARACTERISTICS
TA=25°e, VOO=-5V±5%; Vee=+5V (8)
SYMBOL
VILe= -11V,(Seenotes4,5,6,7)
TEST
Frequency
Frequency
d
t r , tf
MIN
tw
85
10
10
50
CONDITIONS
UNIT
MHz
MHz
ns
ns
ns
ns
1000
10
See note 9
ns
Data Out
C
MAX
4
8
J).QO}
Data in Overlap
tDO
t a+
CIN
COUT
TYP
0.0005
Clock Rep Rate
Data Rep Rate
Clock Pulse Width (9)
Clock Pulse Delay
Clock Pulse Transition
Data Write Time (Setup)
90
ns
I nput Capacitance
2.5
5
pF
@ 1 MHz 25. mV p-p
Output Capacitance
2.5
5
pF
@ 1 MHz 25 mV p-p
Clock Capacitance
130
150
pF
@ 1 MHz 25\ mV p-p
VOL
Output "Low" Voltage
V OH1
Output "High" Voltage
Driving MOS
V OH2
Output "High" Voltage
Driving TTL
-0.3
V
R L =3k, depends on R L and TTL Gate
3.6
4.0
V
RL = 5.6k
[3.0
3.5
V
RL = 3k
MULTIPLEXED 4-BIT MOS SHIFT REGISTER
1 81T 4
: BIT 1 : BIT 2! 81T 3
!
:
:
:
I
I
I
r+-----i
~:
I
:
'"
I
I
0-;-1"
I
2:
3
:'0': '0':
!
!
:
:
~
I
I
t-Lr+--LrT~
DATA IN
:
~
~:
r
~
: : : : _-+'_
:
o.:-'"'--!!--+-_+_+-_+l,_-i!_-I:_+!
!
'"
I
I
1 '"
~
I
I
I
I
I
I
:
I
:
:
:
:
I
I
:
I
1
Figure 1
Figure 1 is a simplified illustration of the timing of a 4-bit multiplexed register showing input output relationships with
respect to the clock. If data enters the register at 1 time, it exits at 1 time, (beginning on 1>1 's negative going edge and
ending on the succeeding 1>2's negative going edge).
CONDITIONS OF TEST
APPLICATIONS INFORMATION
Input rise and fall times: 10nsee. Output load is 1 TTL gate.
TIMING DIAGRAM,
DTL/TTL/MOS INTERFACES'
81T N
""'[1---I
90%_1 ___
I
II
.~;~ :: 1
"
II
: ::
--
-:w--.: :t-I
-
_
----------10V
lJr1[tf--:~-i:-t' .5V
II
I
--
.:
: """ ---
ItP2~WIDATAd
I
:
-- _____
10V,
~~H ~r:-:-_ --"-':--- -- ~ - --- ~ -- --. 5V
DAT~ IN
'J--:
,
---------------f;--iN-aiT;
IN BIT 2
DATA OUT
-----------11'
• tw and too same for 2
•• N=256 for 2502, N = 512 for
2503, N = 1024 for 2504
-
-
t:::r
I
-:'T ~ t: --ov
-.m~-X- ----~t----·5V
I
:
~
,
'-ouriiT,-J
OUTBIT2- 0 .3V
NOTE: When interfacing MOS to MOS output resistors should be 4.7K min
7-59
SILICON GATE MOS. 2502, 2503, 2504
POWER DISSIPATION/BIT
VERSUS SUPPLY VOLTAGE
POWER DISSIPATION/BIT
VERSUS CLOCK AMPLITUDE
1.0
0.'
~
I
.. .......
.......
~
---'
...
i
~~
I
13
I.--""
V
V
0.2
12
10
0.'
a
... 1-- ......
12
10
to
"
22
20
C~OCK .AWLITUDE (VOL TI -:-'
IVcc- Vool (VOLTSI
MAXIMUM ALLOWABLE POWER DISSIPATION
VERSUS AMBIENT TEMPERATURE
POWER DISSIPATION/BIT
VERSUS TEMPERATURE
800 I----+-----+--~i:.!'
6OO1---~--~----4-----+----+-~~----~
0.'
r--
----
400~--~---4----4----+----+----+--~
i-200
1--~--~----4-----+----+----+--~
OL-__ __.....
o
10
20
~
10
20
10
~
__
L.--
/'
V
/
____ __ __
40
50
60
~
~
~
~
70
MINIMUM OPERATING DATA RATE
VERSUS TEMPERATURE
"
12
__
TEMPERATURE (·CI
CLOCK AMPLITUDE VIP
VERSUS MAXIMUM DATA RATE
i
~
30
TEMPERATURE I"CI
~
V-
~
~
~
~~
./
V
V
V
/"
v
~~~
0.1
13
11
CLOCK AMPLITUDE (VOLTS p-pl
"
o
10
20
30
10
10
TEWERATURE (·CI
NOTE:
Conditions forTypical Curves; V CC ~ +5V,V OO = -5V, IP1PW andIP2Pw=85ns, VIP =·11 V, T A=25 °c, fOATA =1 OMHz unless otherwise noted.
7·60
SI'LlCON GATE MOS. 2502, 2503, 2504
APPLICATIONS (Cont'd)
WRITE/RECIRCULATE LOGIC .
• BIT. 2· INPUT DIGtTAL
MULTIPLEX'"
Vee
..
..
....."
ftECIIITlft
------ ...... -.
DATA
'N2
QUAD 2
'NPUT
_ClATE
,r-o'iLiTTL
~
DATA
,,
,
OUT3
,,
!
i
OUfO
L:.2102
_________VOD.....
_____
I
~J
I
WIIITII
RECIfICULATE
_________
!
!
a.!~
ALLIII..ITOftllk ....
CIRCUIT SCHEMATIC
NOTES:
1. N = 1024 on 2504
2. N - 512 on 2603 schematic for second register same as above.
3. N = 256 on 2602 schematic for second, third and fourth registers same as above.
7·81
512 AND 1024-81T RECIRCULATING
DYNAMIC SHIFT REGISTERS
Si!lDotiCS
2505
2512
SILICON GATE MOS 2500 SERIES
DESCRIPTION
PIN CONFIGURATION (Top View)
These Signetics 2500 Series 512 and 1024 bit recirculating
dynamic shift registers consist of enhancement mode
P-channel MOS devices integrated on a single monolithic
chip.
Internal recirculation logic plus write and read
controls, together with two chip select controls are included
on the chip.
K
PACKAGE
1. Select 1
6.1/>2 Input Clock
2. Write.
7. Output
3. Input
8. Read
9. Select 2
4.1/>1 Output Clock
10. V
5. VCC
DD
FEATURES
•
HIGH FREQUENCY
CLOCK RATE
OPERATlON-3 MHz TYPICAL
BLOCK DIAGRAM
• SINGLE 512, SINGLE 1024
•
TTL, DTL COMPATIBLE
•
•
2-CHIP SELECT CONTROLS FOR XY MATRIX
SELECTION
WRITE AND READ CONTROLS INCLUDED
•
LOW POWER DISSIPATlON-150/-lW/bit at 1 MHz
•
LOW CLOCK CAPACITANCE-80pF for 512, 160pF
for 1024 Bits
• +5, ·5V POWER SUPPLIES
•
STANDARD PACKAGE-10 LEAD TO·100
•
SIGNETICS P·MOS
TECHNOLOGY
SILICON
GATE
PROCESS
APPLICA TlONS
FAST ACCESS SWAPPING MEMORY SYS I t:M~
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST BUFFER MEMORIES
CRT REFRESH MEMORIES
DELAY LINE MEMORY REPLACEMENT
DRUM MEMORY REPLACEMENT
PROCESS TECHNOLOGY
Use of low threshold silicon gate technology allows high
speed (3MHz typical) while reducing power dissipation and
clock input capacitance dramatically as compared to other
technologies. The use of low voltage circuitry minimizes
power dissipation and facilitates interfacing with bipolar
integrated circuits.
NOTES:
N ~ 512 or 1024 '0' = OV, '1' = +5V.
When S1 or S2 is '0' Data Recirculates
When S 1 and S2 are '1' see truth table
TRUTH TABLE
WRITE
READ
FUNCTION
0
0
1
1
0
1
0
1
Recirculate, Output is '0'
Recirculate, Output is Data
Write Mode, Output is '0'
Read/Write, Output i~ Data
PART IDENTIFICATION TABLE
PART NO.
BIT LENGTH
PACKAGE
2505K
2512K
512
1024
10 pin TO - 100
10 pin TO - 100
MAXIMUM GUARANTEED RATINGS (1)
BIPOLAR COMPATIBILITY
The signal inputs of these registers can be driven directly by
standard bipolar integrated (TTL, DTL, etc.) or by MOS
circuits. The bare drain output stage provides driving
capability for both MOS and bipolar integrated circuits
(one standard TT L load).
7·62
Operating Ambient Temperature (2)
Storage Temperature
Power Dissipation (2)
Data and Clock Input Voltages
and Supply Voltages with
respect to Vec
oOe to +lO°C
-65°C to + 150°C
535mW@TA>lOoe
+ 0.3V to -20V
SILICON GATE MOS. 2505,2512
NOTES:
1. Stresses above thosa listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. Th is Is a stress rating.
only and functional operation of the device at these or at any
other condition above those indicated In the operational sections
of this specification is not implied.
2. For operating at elevated temperatures the device must be
o
derated based on a +160 C omaxi~um j~nction te":,perature and
a thermal resistance of 160 C/W Junction to ambient.
.5. Parameters are valid over operating temperature range unless
otherwise specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserves the right to make design and process
changes and improvements.
8,' Typical values are at +25°C and nominal supply voltages.
'9. V CC tolerance is ±6%. Any variation in actual V CC will be
tracked directly by V I L' V I H and V OH which are stated for
a CC of exactly 5 volts.
3. All inputs are protected against static charge.
10. VOL is a function of the Input characteristics of the driven
TTL/DTL gate 101 and VCLAMP and the value of the pulldown resistor (R L)'
y
4. See "Minimum Operating Frequency" graph for low limits on
data rep. rate.
0
0
DC CHARACTERISTICS TA =0 C to +70 C;VCC= +5V (9) ; Voo = -5V ±5% unless otherwise noted.
TEST
SYMBOL.
MIN
III
Input Load Current
I
Output Leakage Current
I
LO
LC
100
TYP
10
MAX
500
nA
= 25°C
10
1000
nA
VILC =12V; T A = 25°C
Power Supply Current: 2505
15
25
mA
Continuous Operation;
cJ>'pW "'i150nS~ 1MHz-
25
35
mA
VILC =-l~V ; T A = 25~C
Voo = -5.5V
·5.0
1.05
V
V
Input "High" Voltage
3.2
5.3
V
Clock Input "Low" Voltage
·12.0
·10.0
V
Clock Input "High" Voltage
4.0
5.3
V
V IHC
A
VcJ>l = ".9.2 =-1.2V, _ ~oo = -5V;
V OUT --5.5V, T A - 25 C
1000
Input "Low" Voltage
ILC
IN
=--5.5V;T
10
V IL
V
V
Clock Leakage Current
2512
IH
CONDITIONS
UNIT
nA
TIMING DIAGRAM
4-BIT RECIRCULATING SHIFT REGISTER
NOTE 1:
OUTI'UT
CLOCK.,
-10
INPUT
CLOCK
-10
+5
+5
~2
DATA IN
may be either "1" or "0",
I
+5~~~NA:A
IN'
"0"
I
NOTE 2:
I
Data recirculates if one or more
of the following control lines are
"0"; Sl, S2 and W
Read may
'be either "1" or "0"
~:~AI ri~'A
I
IN 4
"0"
I
I
D... TA OUT
DATA
+5V ____________________________________~~~OU~T~2--~~~~~~;~
WRITE
+5~--.J
READ
(WRITE cycle)
The positive and negative going
edge of the" W ", "Sl", "S2"
controls are coincident with the
negative going edge of the input
clock (~). The "Read" control
0
I
NOTE 3:
LL
I
o____________________________________~
+5V
NOTE 3,
READ CYCLE
LL
I
(RECIRCULATE cycle)
(READ cycle)
The positive going edge of the
"Read", "S1", "S2" controls are
coincident with the negative edge
of the output clock (111)' The
negative going edge of R, S 1, 52
is coincident with the negative
going edge of either clock pulse
succeeding the last desired data
output bit.
W may be either
"1" or "0"
Figure 1
Figure 1 is a simplified illustration of the timing of a 4-blt recirculating shift register showing the 3 basic modes of. operation.
7·83
SILICON GATE MOS. 2505, 2512
CONDITIONS OF TEST
Input rise and fall times: 10 nsec Output load is 1 TTL gate
TIMING DIAGRAM
.
-10
"---;--~H-~~---4~------~~~~--.F~,ft~--------'
.,OUTPUT CLOCK
-10
I
::
!!......1ott
-111'
"
:
:: I
DATA,N"---i"""
o
!!
,
"
-
I:
LOCKIIEI'IIATE~,
....
!I !
--- --
:
:
....
t,.
1 I"
,\._, J
I
::...t,.+~
-I
+1
I
I
---.---~----------------~~ ---~1r
y--DATAOUT
:
'
,'L.,
o
I
:
IS •
i
-----auTliT;-----J
ow +-1 :- --:t-- ow I
..
MIiTE"
o
,, 'Nllf1
,
::.A.
!
I
:
I
"'.;-1 :-
:
~~
t :
...-
"'+-1-I !:
SELECT 1 '" , - - - - - , .
SELECT 20--1
~.,.J
"'+-1:-
IlEAD
I
. --------------~,J
NOTE:
1. N=512 for 2505, N=1024 for 2512
_
2. Note that the Readlnput is AND'ed with
'if) 1;
!
:
~
t- ...-
:: \'-.__
~.
_______________
~ ~"'-
\~------------
therefore this function Is not valid until 1>1 occurs.
AC CHARACTERISTICS TA=+25°C VCC=+5V (9); VDD=-5V±5%; VILC=·llV
SYMBOL
TEST
MIN
.0005
(Note 4)
Frequency
Clock Data Rep Rate
tqJpw
Clock Pulse Width
180
tq,cJ
Clock Pulse Delay
10
tr;tf
Clock Purse Transition
tow
Data Write (Setup) Time
tDH
ta+;tatR_;tCS_
tw _
Data to Clock Hold Time
tR-;tCS+
tw +
Cin
TYP
3
MAX
UNIT
2.5
MHz
nsec
1
p.sec
nsec
150
10
nsec
100
nsec
Clock to "Read" or
"Chip Select" or ''Write''
Timing
0
nsec
Clock to "Read" or
"Chip Select" or "Write"
Timing
. Input Capacitance
0
nsec
Cout
eq,
Clock Capacitance
2505
2512
5
pF
5
pF
50
100
pF
pF
1 MHz; V =VCC;V AC= 25m V Pop
-1.0
V
R L = 3.0K; 1 TTL Load
(I L = 1.6mA) Note 10
RL =3.0K; 1 TTL Load
(I L = l00,..A)
VOL
Output "Low" Voltage
VOHI
Output "High" Voltage
Driving 1 TTL Load
2.4
3.5
V
VOH2
Output "High" Voltage
Driving MOS
3.6
4.0
V
7·64
W= R = VCC
nsec
Clock to Data Out Delay
Output Capacitance
CONDITIONS
1 MHz'S VI=VCC; VAC=:25rnjVp_p
1 MHz; VO=VCC; VAC= 25mVp_p
RL
=5.6K; CL = 10 pF
SILICON GATE MOS. 2505,2512
CHARACTERISTICS CURVES
POWER DISSIPATION/BIT
VERSUS CLOCK RATE
POWER DISSIPATION/BIT
VERSUS SUPPLY VOLTAGE
800
l000~----~----~----~-----r-----'
l00~----+-----+----'~~---r----~
i
800
.3
;;
10 ~----+----,"I-r----+------r----~
~
~
j:;
:
~
i
400
~
t:::= ~
V
lOU
VV
o
·4
-i
·5
100
-7
·6
SUPPLY VOLTAGE IVCC-VOOI IVOLTSI
CLOCK RATE IMH,I
MAXIMUM CLOCK RATE
VERSUS CLOCK AMPLITUDE
POWER DISSIPATION/BIT
VERSUS TEMPERATURE
IlOO
400
~~
V
/
V
/
lOU
""
---
~ ....
15
13
18
16
0
10
MAXIMUM PACKAGE POWER DISSIPATION
-
10.000
~ .....
..........
10
J~ /
V
u-';::P'
:-..........
1000
............... t--.
700
10
30
MINIMUM OPERATING
CLOCK FREQUENCY
VERSUS TEMPERATURE
800
-
TEMl'ERATURE fe)
CLOCK AMPLI TUDE IV 011 IVOL TSI
900
r--
100
2
1000
'"""'---
........
600
t'-....
500
100
~
~
/
~
~,~
0
300
'/
200
/
V
~
/
V
./
100
I
20
30
40
TEMPERATURE I CI
50
10
30
50
10
70
TEMPERATURE I CI
NOTE:
Conditions for Typical Curves = V CC=+5V, V DD=-5V, Clock Duty Cycle=35°C, f CLK =2.5MHz, V ¢p_p=16V, ¢PW =180ns, T A =25°C
unless otherwise .noted
7-65
SILICON GATE MOS. 2505,2512
APPLICATIONS OAT A
TTL/DTL/MOS INTERFACES
TTLJDTL
TTLIDTL
n---1-----___~J IN
-+---1
OUTj.!7----<_-+----"IIN
IRECIRCULATING
SHIFT REGISTERI
OUTI-!7_ _
(USED AS AN
N BIT SHIFT
REGISTER I
IR
2505
2512
2W
2W
6.IK
U
JK
'5V
U
10V
'6V
-10V
·5V
MATRIX CHIP SELECT LOGIC
X DECOOER
1210 .-.a ,
0
EAD
.--1
I-
....
READS,
W
W
Ii
Sz
Sz
Sz
READ 5,
READ I,
I-
....
1
52
Sz
Sz
READ 5,
I-
....
W
....
READ 5,
W
I
.....
L...
T
w
w
Sz
Ii
12
I
3. All "', 's common
7-66
IIEAD 5,
w
w
2. All inputs common for each plana
I-
I-
REAO 5,
w
1
4. All
I
-L B~N.~
1
_ _ _ _ ~IT~ _ _ _ _
L _
1
~T~S~OE
. ~;~ ~
LFV"~
.'AO '" o----t
."D
H"
v"
NOTE:
'Joe
V.
__ I
Yoe: ,.Nt
VOO:PlN10
Vee
V.
~,
I'tN4
~:
,.NI
N .. 512 for 2505
N - 1024 for 2512
7-87
!ii!lDotiC!i
2506
2507
2517
DUAL 1~O-BIT DYNAMIC
SHIFT REGISTER
SILICON GATE MOS 2500 SERIES
DESCRIPTION
BIPOLAR COMPATIBILITY
These Signetics 2500 Series dual 100-Bit dynamic shift
registers consist of enhancement mode P-channel MOS
devices integrated on a single monolithic chip. They use two
clock phases.
The dual 100 bit device can be driven directly by standard
bipolar integrated circuits (TTL, DTL, etc.) or by MaS
circuits. The design of the output stage provides driving
capability for MOS or bipolar IC's.
FEATURES
It is available in bare drain configuration or with internal
pull down resistor values of 7.5k or 20k to provide easier
interfacing with other MOS circuitry.
•
•
•
•
•
•
•
•
HIGH FREQUENCY OPERATION
4 MHz TYPICAL CLOCK RATE
TTL, DTL COMPATIBLE
LOW POWER DISSIPATION - 400 fJW/BIT AT 1 MHz
LOW CLOCK CAPACITANCE 40pF MAXIMUM
LOW OUTPUT IMPEDANCE - 300 OHMS TYPICAL
BARE DRAIN AND MOS RESISTOR VERSIONS
AVAILABLE
STANDARD PACKAGES - 8 LEAD TO-5 AND 8
LEAD SI LlCONE DIP
SIGNETICS P~MOS SILICON GATE AND SILICONE
PACKAGING TECHNOLOGIES
APPLICATIONS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST BUFFER MEMORIES
PIN CONFIGURATIONS (TOP VIEW)
T PACKAGE
V PACKAGE
'0'
VCC
Output Clock (.1)
Output 2
Input 2
8.
Voo
7
•
4
II
1. Output Clock
1. Input 1
2. Output 1
3. Input Clock (.2)
4.
5.
6.
7.
2
3
(t/> 1 )
2. Output 2
3. Input 2
4. Voo
5. Input 1
6. Output 1
7. Input Clock (<1>2)
8. VCC
PROCESS TECHNOLOGY
Use of the low threshold silicon gate technology allows high
speed (3 MHz guaranteed), while reducing power dissipation
by a factor of 2 and reducing clock input capacitance
dramatically as compared to conventional MOS technologies.
BLOCK D·IAGRAM
IN 1
-f:>o-I
100 BITS
IN 2
--{::>oi
100 BITS
f-1>of-1>o-
OUT 1
OUT 2
SILICONE PACKAGING
Low cost silicone DIP packaging is implemented and reliability is assured by the use of Signetics unique silicon gate
MOS process technology. Unlike the standard metal gate
MOS process the silicon material over the gate oxide passivates the MOS transistors, and the deposited dielectric
material over the silicon gate-ox ide-substrate structure provides an ion barrier. In addition, Signetics proprietary surface passivation and silicone packaging techniques result in
an MaS circuit with inherent high reliability, demonstrating
· superior moisture resistance, mechanical shock and ionic
contamination barriers. For further information reference
Signetics - "Silicone Package Qualification Report".
7-68
PART IDENTIFICATION TABLE
PART NO.
2506T
2506 V
2507T
2507 V
2517 T
2517 V
OUTPUT
Bare
Bare
7.5k
7.5k
20k
20k
Drain
Drain
Pull Down
Pull Down
Pull Down
Pull Down
PACKAGE
8 Pin TO-5
BPin DIP
8 Pin TO-5
8 Pin DIP
8 Pin TO-5
8 Pin DIP
SILICON GATE MOS -2506,2507,2517
MAXIMUM GUARANTEED RATINGS (1)
O°C + 709 C
Operating Ambient
-65°C
+ 150°C
Storage Temperature
Power Dissipation (Note 2) @ T A=70°C
535mW
TPackage
455mW
V Package
Clock Input Voltages with respe.ct to VCC(3) +0.3 to -20V
Supply and Data Input Voltages with
+0.3 to -12V
respect to Vcd 3 )
NOTES:
1. Stresses above tho.. listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at the.. or at any
other condition above those indicated In the operational sections
of this specification Is not Implied.
2. For operating at elevated temperatures the device must be
o
d~rated based on a +150 C :naxlmum junction temp~rature and
a thermal resistance of 150 CIW (T package) or 175 CIW (V
package).
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless
otherwise specified.
5. Ali voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and Improvement,.
7. Typical values are at +2SoC and nominal supply voltages.
S. V CC tolerance Is ±5%. Any variation In actual VCC will be
tracked directly by V IL . V IH and V OH which are stated for
a VCC of exactly 5 volts.
9. VOL (for this bare drain device) is a function only of the driven
gate characteristics together with the external pull-down resistor.
(R pD )'
10. Sea Figure 2 for definitions.
11. Logic Convention: Data Lines - Positive; Clocks - Negative.
DC CHARACTERISTICS
T A = O°C to +70°C; V DD
= -5V ±5%; VCC = +5 (8); unless otherwise noted(Notes:
4,5,6,7).
CONDITIONS
TYP.
MAX.
UNIT
III
Input Load Current
(Input 1)
10
500
nA
+5V ON OUT 1,161,
VCC'
IN 2, OUT 2.IN 1 = -5.5V.
VOO =-4.5V. TA = 25°C
III
Input Load Current
(Input 2)
10
500
nA
+5V ON OUT 2.161.1$2. VCC.
IN 1. OUT 1.IN 2 =-5.5V.
VOO =-4.5V. TA = 25()C
I LO
Output Leakago Current
(OUT 1) (Notes 9 & 10)
10
1000
nA
+5V ON IN 1. VCC. OUT 2.
IN 2. VSo, OUT 1 = -5.5V
161 =-1 V.TA=25°C(25060nly)
I LO
Output Leakage Current
(OUT 2) (Notes 9 & 10)
10
1000
nA
+5V ON IN 1. OUT 1. VCC.
IN 2. Voo. OUT 2 = -5.5V.
16=-10v. TA ~ 25°C (2506 Only)
I LC
Clock Leakage Current
(161 )
10
1000
nA
VI$1 = -12V. VOO = -4.5V
All other pins +5V.
TA = 25°C
I LC
Clock Leakage Current
10
1000
nA
Vt$2 = -12V. VOO =-4.5V
All other pins +5V
TA = 25°C
V IL
Input "Low" Voltage
(Note 11)
-5
1.05
V
VIH
Input "High" Voltage
(Note 11)
3.2
5.3
V
C IN
Input Capacitance
(Inputs 1 & 2)
2.5
5
pF
VIN = VCC.1 MHz.
25 mV p-p
C~
Clock Input Capacitance
(161.162)
25
40
pF
VI6= VCC.1 MHz.
25mVp-p
V IHC
Clock Input "High" Voltage
4
5.3
V
VILC
Clock Input "Low" Voltage
-12
-10
V
SYMBOL
TEST
MIN.
(t$2)
e:z,
e:z.
e:z.
7-69
SILICON GATE MOS. 2506,2507,2517
CONDITIONS OF TEST
Data amplitude +1.05 to +3.2 Input rise and fall times: 10 nsec. Output load is 1 TTL gate.
TIMING DIAGRAM
INPUT
I
I,
1~2':i:~
~I
OUTPUT
PHASE
I
---11r
I
I.
:loolU
I
I
DATA
OUT
FREQ.
ltv
I,
lC.1-
H:~'~I
--I
-t-- - -
--h
_IW~~I_
DATA
IN
+6V
---10%
I
~2
PHASE
+6V
l1V
~
+6
I
L I ..
L:
I
AC CHARACTERISTICS
TA = 25°C; V DD = -5V ±5%; VCC = +5V (8) ; VILC = -llV
SYMBOL
Frequency
TEST
Clock Rep Rate
MIN
TYP
MAX
UNIT
0006
4
3
MHz
CONDITIONS
¢ IPW
Clock Pulse Width ¢ 1
150
nsec
@3MHz.
¢2PW
Clock Pulse Width ¢ 2
100
nsec
@3MHz.
¢d
Clock Pulse Delay
10
nsec
@3MHz
t r , tf
Clock Pulse Transition
10
Data Write Time (Set-Up)
75
Data I n Overlap
10
tw
~DO
t a+
1000
t r¢2
90
Clock to Data Out
nsec
V ¢ = VCC - 16V, DATA OUT =+2.5V
150
Output "High" Voltage
VOHl
RINT = 7.5k nom., CL = 10pF, 2507
3.4
driving MOS (Note 11)
4.0
V
3.5
V
Only, RINT = 20k nom. 2517 only
Output "High" Voltage
VOH2
driving TTL (Note 11)
3.0
Outputs @ logic "0" or "1'; 3MHz,
7-70
12
(VDD)
RL = 3.3k, VDD = -5V
2506 only
Power Supply Current
IDD
= tr¢ 1 = 10nS
26
rnA
¢ 1 = 150ns, ¢ 2 = lOOns
SILICON GATE MOS. 2506,2507,2517
CHARACTERISTIC CURVES
TY~CALCLOCKFREQUENCY
POWER DISSIPATION PER
BIT VERSUS FREQUENCY
VERSUS CLOCK AMPLITUDE
1000
320
100
32
10
3.2
V
/
V
/
V
/
V
/
V
/
L
25°C
V
/V
V
V
V
V
V
V
10'C
2
13
.01
.10
.032
1.0
.32
14
16
CLOCK AMPLITUDE IV)
CLOCK FREQUENCV IMHz)
MINIMUM OPERATING
CLOCK RATE
POWER DISSIPATION BIT
VERSUS TEMPERATURE
800
10K
i
~
!
i
800
i'"
~
~
ft
~
1~
lK
700
;
~
liDO
!
19
18
11
16
3.2
100
~ ~~
V
~
-----
.----
o _____
----
~
~
-----
~
10
400
.1
o
TEMPERATURE lOCI
NOTE:
10
20
30
60
eo
70
TEMPERATURE 1°C)
Contltions for Typical Curves: V CC=+5V, V DD =-5V. VI LC=-11 V, f/lPW1 =150n5, tPpW2=100ns, f=3MHz, T A=+25°C unless otherwise noted.
APPLICATIONS DATA
DTL/TTL/MOS INTERFACES
100-BIT DELAY
200-BIT DELAY
+6V
r-----------------~----------------._--_o+&V
* *3.3K for 2506
6.8K for 2507
-6V
3.3K for 2517
• For 2506 only.
7-71
SILICON GATE MOS. 2506,2507,2517
CIRCUIT SCHEMATIC
VDD
IN1jf
i----------------------------------------------------- -----------------:~==~~---:
IN 2
I
I
I
I
I
I
i~
---t-j
SCHEMATIC FOR SECOND 100 BITS SAME AS ABOVE.
I
I
:L
I
VCC
100 BITS
__________________________________________________________________
• For 2507 and 2517 Options Only.
7·72,
!:
--H
I
VCC ...J:
.1: ______
OUT 2
Smnotics
2509
2510
2511
TRI-STATE OUTPUT DUAL 50-100-200
BIT STATIC SHIFT REGISTERS
SILICON GATE MOS 2000 SERIES
DESCRIPTION
BIPOLAR COMPATIBILITY
These Signetics 2500 Series Dual 50, 100, and 200 bit recirculating static shift registers consist of enhancement mode
P-channel silicon gate MOS devices integrated on a single
monolithic chip. Internal recirculation logic plus TTL/DTL
level clock signals plus TRI-STATE outputs are provided for
maximum interfacing capability.
The clock and signal inputs of these registers can be driven
directly by standard bipolar integrated (TTL, DTL, etc.)
or by MOS circuits. The TRI-STATE output stage provides
driving capability for both MOS and bipolar integrated
circuits (one standard TTL load).
FEATURES
PIN CONFIGURATIONS (Top View)
A PACKAGE
•
TRI-STATE MOS OUTPUTS - PROVIDE POWERFUL
BUSSING CAPABILITY
• TTL/DTL COMPATIBLE CLOCKS - PROVIDE
EXTREMELY LOW CLOCK CAPACITANCE
• RECIRCULATION PATH ON CHIP
• THREE BIT LENGTHS AVAILABLE
• HIGH FREQUENCY OPERATION
• 2MHz GUARANTEED CLOCK RATE
• TTL, DTL COMPATIBLE SIGNALS
• STANDARD PACKAGES - 10 LEAD TO-100, 14 PIN
DIP
• SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
14
13
12
11
10
1.
Recirculate
14. VCC
2.
INl
3.
OUT 1
13. IN2
12. OUT 2
4.
NC
11. NC
5.
6.
7.
NC
10. VGG
9. Output Enable
8.
CLOCK CAPACITANCE
VOL
V OH
OUTPUT "LOW" VOLTAGE
6
7
pF
@
V
Note 9
V
RL
1MHz; V
V AC
0.4
3.6
OUTPUT "HIGH" VOLTAGE
= 25mV
= 7.5Kn
+6V
+5V
+5V
= 25mV
7.5KO
TTL INTERFACE
·12V
Vc~~
RECIRCULATE
CLOCK
.,....
11
12
. . - - - 13
r - - - 14
rcr
15
18
0,
O2 2518/2519 03
-
VGG
°4 t-°5108
OUTPUT
~
'.
:':.::
·17V
7·98
ALL 7,5KO
MOS INTERFACE
= VCC;
pop
= VCC;
pop
to VGG
SILICON GATE MOS. 2518,2619
APPLICATIONS OATA
32 or 40 POSITION CRT DISPLAY MEMORY SYSTEM
2518B·
OATA
INPUTS
OR
2519B·
8BIT
ASCII
LINE MEMORY
32X8
or
4OX8
MAIN MEMORY
1024X8
-These registers include internal redfoolatl. Two 82668 multiplexers are used for system recirculate.
MULTIPLEXING LINE MEMORY REGISTERS AT 4MHz DATA RATE
DATA OUT
~
CLOCK
,--+5
~
CLOCK
(:4MHz)
O.4V
NOTE:
The above schem.atic connects two 2518B or 2519B Hex Shift
Registers into a multiplexing scheme In order to accomplish a
64 or 80 character/line display at4MHz data rate •.
7-99
SILICON GATE-MOS. 2518,2519
CHARACTERISTIC CURVES
MAXIMUM SHIFT FREQUENCY
VERSUS VGG
IGGVERSUS TEMPERATURE
20
5.0
I
18 t--- VGG· -12V
Vee = +5.0V
16
-
t---
4.0
_2519
-
14
"""12
1-0
r--
2518
-
3.0
-I---
~
~
.§.
10
~
1;1
~E
2.0
1.0
o
o
20
10
30
40
50
70
60
0.0
·12
·11
·13
TEMPERATURE (De)
I GG VERSUS VGG
ISOURCE VERSUS V OUT
-12.0
·10.0
-8.0
~
~
rI
I
I
Vee
<>r-I
(1
CLOCK GEN.
per chip)
l __________________________
---1
OUTPUT
STAGE
..1
~ ~IJ
!ii!lDotiC!i
DUAL 128·132 BIT STATIC
SHIFT REGISTERS
SILICON GATE MOS 2500 SERIES
PIN"CONFIGURATION (Top View)
DESCRIPTION
These Signetics 2500 Series Dual 128 and 132 bit recirculating static shift registers consist of enhancement mode
P-channel silicon gate MOS devices integrated on a single
monolithic chip.
FEATURES
•
•
•
•
•
•
•
•
2521
2522
PUSH-PULL OUTPUTS
TTL/DTL COMPATIBLE CLOCK
PROVIDES
EXTREMEL Y LOW CLOCK CAPACITANCE
RECIRCULATION PATH ON CHIP
TWO BIT LENGTHS AVAILABLE
HIGH FREQUENCY OPERATION - 2MHz TYPICAL
CLOCK RATE
TTL, DTL COMPATIBLE SIGNALS
STANDARD PACKAGE - 8 LEAD SILICONE DIP
SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
V PACKAGE
10
8
2
7
3
8
4
&
1. Recirculate
2. IN 1
3. 0UT 1
4. VGG
TRUTH TABLE
INPUT
FUNCTION
0
0
0
Recirculate
1
Recirculate
1
0
"0" is Written
1
"1" is Written
RECIRCULATE
1
APPLICATIONS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST STATIC BUFFER MEMORIES
CRT REFRESH MEMORIES - LINE STORAGE
LINE PRINTERS
" CASSETTE RECORDERS
8. VCC
7. IN2
6. OUT2
5. 1 Output clock
3. Read
6. Input
4. VOO
5. Write
BLOCK DIAGRAM
APPLICATIONS
FAST ACCESS SWAPPING MEMORY SYSTEMS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST BUFFER MEMORIES
CRT REFRESH MEMORIES
DELAY LINE MEMORY REPLACEMENT
DRUM MEMORY REPLACEMENT
PROCESS TECHNOLOGY
Use of low threshold silicon gate technology allows high
speed (5MHz typical) while reducing power dissipation and
clock input capacitance dramatically as compared to other
technologies. The use of low voltage circuitry minimizes
power dissipation and facilitates interfacing with bipolar
integrated circuits.
BIPOLAR COMPATIBILITY
The signal inputs of these registers can be driven directly by
standard bipolar integrated (TTL, DTL, etc.) or by MOS
circuits. The bare drain output stage provides driving
capability for both MOS and bipolar integrated circuits
(one standard TTL load).
7-108
INPUT
NOTE
N = 512 or 1024 '0'
= OV,
'"
= +5V.
TRUTH TABLE
WRITE
READ
FUNCTION
a
a
0
1
0
1
Recirculate, Output is '0'
Recirculate, Output is Data
Write Mode, Output is 'a'
Read Mode Output is Data
1
1
PART IDENTIFICATION TABLE
PART NO.
BIT LENGTH
PACKAGE
2524V
512
8 pin DIP
2525V
1024
8 pin DIP
SI LICON GATE MOS. 2524, 2525
MAXIMUM GUARANTEED RATINGS (1)
2. For operating at elevated temperaturef the device must be
derated based on a + 150°C maximum junction temperature and
o
a thermal resistance of 150 C/W junction to ambient.
Operating Ambient Temperature (2)
Storage Temperature
Power Dissipation (2)
Data and Clock Input Voltages
and Supply Voltages with
respect to V CC
3. All inputs are protected against static charge.
4. See "Minimum Operating Frequency" graph for low limits
;on data .rep. rate.
•
O°C to +70°C
-65°C to + 150°C
535mW@TA>70°C
5. All voltage measurements are referenced to ground.
6'. Manufacturer reserving the right to make design and process
changes and improvements.
7. Typical values are at +25°C and nominal supply voltages.
+ 0.3V to -20V
8. Parameters are valid over' operating temperature range unless
otherwise specified.
9. Vce tolerance is ±. 5%. Any variation is actual VCC will be
tracked directly by VIL, VIH and VOH which are stated
for a V CC of exactly 5 volts.
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied.
10. VOL is a function of the input characteristics of the driven
TTLlDTL gate 101 and VCLAMP and the value of the pulldown resistor (R L l.
DC CHARACTERISTICS TA = o°c to +70°C; VCC = +5V(9); VDD
== 5V ±5% unless otherwise noted.
---
SYMBOL
TEST
MIN
TYPICAL
MAX
UNIT
-.
CONDITION
III
I nput Load Current
10
500
nA
VIN =-5.5V;TA = 25°C
ILO
Output Leakage Current
10
1000
nA
V¢1 = V¢2 = -12V; VDD =-5
VOUT =-5.5V; TA = 25°C
ILC
Clock Leakage Current
10
1000
nA
Power Supply Current: 2524
100
15
2525
35
mA
VIL
Input "Low" Voltage
-5.0
1.05
V
VIH
Input "High" Voltage
3.2
5.3
V
; TA = 25°C
Continuous Operation;
mA
35
25
VILC = -12V
------,--
¢pW
=
150nS; 1MHz
VI LC = -12V; T A = 25°C
VDD = -5.5V
--- -------
-~---.--
VILC
Clock Input "Low" Voltage
-12.0
-10.0
V
VIHC
Clock Input "High" Voltage
4.0
5.3
V
..
--
.--
----
TIMING DIAGRAM
NOTE 1: (WRITE cycle)
OUTPUT
+6
CLOCK~l
-10
INPUT
CLOCK 162
.6
-10
OATAIN
NOTE 2: (RECIRCULATE cycle)
+~~L:?:;":2e.TA_...l?.:;,:!..~A,...~
+6V
DATA OUT
The positive and negative going
edge of the "Write" control is
coincident with the negative going
edge of the input clock (<1>2)' The
"Read" control may be either "1"
or "0"
liN 1
"0"
"0"
IN 4
IL---------I---D-A-T-A--D-A-TA------I-
0' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~~~2~~O~~3~
I
I
WRITE
READ
+6~~r---------iL
OUT 1
I
I
______________________
o_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
+ISV
NOTE 1:
WRITE CYCLE
OUT4
NOTE 2:
RECIRCULATE CYCLE
I
L..L
NOTE 3:
READ CYCLE
NOTE:
This is a simplified illustration of the timing of a 4 bit recirculating shift register
showing the 3 basic modes of operation.
I
Data recirculates if the "Write"
control line is "0". "Read" may
be either "1" or "0".
NOTE 3:
(READ cycle)
The positive going edge of the
"Read" control is coincident with
"!be negative edge of the output
clock (<1>1). The negative going edge
of "Read" is coincident with the
negative going edge of either clock
pulse succeeding the last desired
data output bit. "Write" may be
either "1" or "0"
7-109
SI LICON GATE MOS. 2524, 2525
CONDITIONS OF TEST
I nput rise and fall times: 10 sec Output load is 1 TTL gate
TIMING DIAGRAM
~
-10
~---;--tr~~--~------~~~--~Wl~~-----;
~10UTPlJT CLOCK
tow
-10
:
: :
.
!
DATA IN
'NaIT 1
I
- :- -
I
-1
1
~
I
iI
II
-:1
i - - - -- - - -- -- - - - - - 'H- T- - :\4-.
ss i
i
-+-:1 tw
:
I
-
I
tR-
NOTE:
N = 512 for 2524
C
I
-----O'UTBTT"'i-----..1
:
1
1.
I
--!.i
I
:
READ
i
:,
d
: :"- ..
I
-
90%
!!
CLOCKREPRATE~
I
\-",!oJ
I
o
~
! __ ~~_
I
O~- 'w
WRln
::
I
o
I
I ~tDH
~ ___ ~,I
DATA
I
-f.--t..; I
:
--1:-- --:
~---------------------------~\~
t-- 'R-
\~---------------------
N= 1024 for 2525
2. Note that the Read Input isAN O'ed with (ji1; therefore this function is not valid until
tPl occurs.
AC CHARACTERISTICS T A = +25°C VCC = +5V(9); VDD = -5V ±5%;VILC = -llV
SYMBOL
TEST
MIN
.0005
(Note 4)
135
Frequency
Clock Data Rep Rate
t¢pw
t¢d
t6 t f
Clock Pulse Width
Clock Pulse Delay
10
Clock Pulse Transition
10
tDW
Data Write (Setup) Time
70
tDH
Data to Clock Hold Time
20
ta+
tR-;·
tw_
Clock to Data Out Delay
Clock to "Read" or
"Write" Timing
TYP
5
MAX
3
UNIT
CONDITtONS
MHz
W= R = VCC
ns
85
ns
1000
ns
ns
ns
100
ns
0
ns
0
ns
tR-;
tW+
Clock to "Read" or
Cin
Input Capacitance
5
pF
lMHz; VI=VCC;V AC=25m V p .p
Cout
Output Capacitance
5
pF
lMHz; VO=VCC;VAC=25m V p.p
C¢
Clock Capacitance
80
160
pF
"Write" Timing
2524
2525
VOL
Output "Low" Voltage
VOHI
Output "High" Voltage
Driving 1 TTL Load
VOH2
Output "High" Voltage
Driving MOS
7-110
pF
lMHz; V=VCC; VAC=25m V p.p
-1.0
V
RL =3.0K; 1 TTL Load (I L =
1,6mA) Note 10
2.4
3.5
V
RL=3.0K;1 TTL, Load (I L=100t,tA)
3.6
4.0
V
RL = 5.6K; CL = 10pF
51 LICON GATE MOS. 2524, 2525
CHARACTERISTIC CURVES
POWER DISSIPATION/BIT
VERSUS SUPPLY VOLTAGE
POWER DISSIPATION/BIT
VERSUS CLOCK RATE
lOOO..-----,-----r---,.---r---,
100
~
Ii
100
I
15
-
!
200
~
~
..
:
/
/
~
/
~
v::
~26
-.
-7
IIUPPL Y VOLTAGE (
CLOCK RATE (MHoI
Vool (VOLTal
POWER DISSIPATION/BIT
VERSUS TEMPERATURE
MAXIMUM CLOCK RATE
VERSUS CLOCK AMPLITUDE
600
:/
/
/
~
./'
I-
iii
~
-"-
::
~
Q
~
300
~
---_. __ ..-
200
i
""
~
~ 1-0..
r--
~
r---_
100
Z
11
II
17
14
o0
10
20
CLOCK AWLITUO£ (Y4I (y0L1'11
MAXIMUM PACKAGE POWER
DISSIPATION VERSUSTEMPERATUR E
1000
900
i
~r-...
800
700
i:i
600
~
.........
'-.......
...........
I'-..
a:
500
~
400
~
100
V
~ .....
~
~
~~
10
300
~
~::;
70
~r""
~
200
eo
~p ~
2
::;
50
(OCI
MINIMUM OPERATING CLOCK
FREQUENCY VERSUS TEMPERATURE
1000
............ ,
5
~
40
10,000
E
~
30
TEMPERATURE
'V
~
V
V"
./
V
./
1011
0. I
10
20
30
40
50
60
CP,PW1 =cf>?W2
= 80ris; TA = +25
Q
= +5V,
20
30
•
•
•
711
TEMPE""TURE rCI
TEMPERATURE I CI
NOTE:
Conditions for tvplcal curves: VCC
10
VOO
= -5V, clock
duty cvcle = 35%, fCLK = 3MHz, V¢p-p = 16V,
C unless otherwise noted.
7·111
SI L ICON GATE MOS. 2524, 2525
APPLICATIONS DATA
TTL/DTL/MOS INTERFACES
+!iV
8880
2524
2524
2525
2525
TTL/DTL
DUT~"""'----1f---IIN
(RECIRCULATING
SHIFT REGISTER)
OUT~.......--t---l
(USED AS AN
N BIT SHIFT
REGISTER)
W
Lr-r------------__4
w
5.6K
3K
+5V
+5V
li
li
-10V
-10V
-5V
CIRCUIT SCHEMATIC
I
I
I
I
I
. __ .~' __ ..J _____
I- - - '- t~ ~ ~~~
•
:~: ::~J
HTE
~
NOTE
N = 512 for 2524
N = 1024 for 2525
7·112
I IIT3 I
_____ .1 ~..~ ____
~.
I
~'T~ _ _ _ _
L _
~~~AGE
~~~~ ~~ -
I
L"· mo~
"0
READ
o---i
~
~
!i~nl!tiC!i
ADVANCE SPECIFICATION
DESCRIPTION
HIGH SPEED 64 x 9 x 9
STATIC CHARACTER GENERATOR
SILICON GATE MOS 2500 SERIES
PIN CONFIGURATION (Top View)
The 2526 is a high speed 5,184-bit Static Read-Only
Memory available in a 64x9x9 organization. This device has
TTL compatible inputs and outputs and requires +5V and
-12V power supplies. A READ input controls the entry of
data from the ROM into output latches. Three-state outputs
allow OR tying for implementing larger memories. OUTPUT
ENABLE controls the nine output devices without affecting
address circuitry.
N PACKAGE
1. Output 6
FEATURES
•
•
•
•
•
•
•
•
•
64x9x9 ORGANIZATION
625n6 TYPICAL ACCESS TIME
STATIC OPERATION
OUTPUT LATCHES
TTL/DTL COMPATIBLE INPUTS
TTL/DTL COMPATIBLE THREE-STATE OUTPUTS
VCC = +5V, VGG = -12V
24-PIN SI LlCONE DIP
SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
2526
24. VCC
23. Output 5
2. Output 7
3. Output 8
22. Output 4
4. Output 9
20
5. VDD (GND)
6. Address 4
21. Output 3
20. Output 2
19
7. Address 3
19. Output 1
18. Read
8. Address 2
17. Address 10
9. Address 1
17
16. Address 9
16
14. Address 7
10. Output Enable
15. Address 8
11. Address 5
13. Address 6
12. VGG
APPLICATIONS
VERTICALOR RAS'TERSCAN DISPLAYS (7x9MATRIX)
PRINTER CHARACTER GENERATOR
PANEL DISPLAYS AND BILLBOARDS
MI CRO-PROGRAMMI NG
CODE CONVERSION
BLOCK DIAGRAM
BIPOLAR COMPATIBILITY
All inputs of the 2526 can be driven directly by standard
bipolar integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA
sufficient to drive one standard TTL load.
STANDARD TRUTH TABLES
The 2526N/CM3940 is a 7x9 matrix, ASCII character set
(raster scan)*utilizing the two unused left-most columns for
BCDIC-ASCII and BAUDOT-ASCII code converters. Use
this device for evaluation or for suitable application. Other
standards will be announced as they become available.
-for vertical scan specify CM3400
CUSTOM TRUTH TABLES
See page 7-197.
PART IDENTIFICATION
PART
OP. TEMP. RANGE
2526N
0-70 C
24-Pin Silicone DIP
0-70°C
= +5V
24-Pin Ceramic DIP
o
25261
NOTE: "0"
= OV,
PACKAGE
"1"
7-113
SI LICON GATE MOS. 2526
MAXIMUM GUARANTEED RATINGS (1)
Operating Ambient Temperature
Storage Temperature
Package Power Dissipation 2 @ 70°C
Input3 and Supply Voltages
with respect to V CC
o°C to 70°C
_65° C to +150° C
730mW
+0.3 to -20V
DC CHARACTERISTICS
T A=Oo to +70°C, VCC= +5V; VGG= -12V ±5%; unless otherwise noted. (See notes 4,5,6,7)
SYMBOL
TEST
MIN
Input Load Current
III
TYP
MAX
UNIT
10
500
nA
CONDITIONS
VIN = -5.5V
TA = 25°C
Output Leakage Current
ILO
10
nA
1000
VOUT= OV
TA = 25°C
VCE = VCC
ICC
VCC Power Supply Current
30
45
mA
(8)
IGG
VGG Power Supply Current
30
45
mA
(8)
VIL
I nput Logic "0"
-5
1.05
V
VIH
Input Logic "1"
3.2
5.3
V
AC CHARACTERISTICS
0
TA=iO°C to +70 C;VGG=-12V ±5% unless otherwise noted.
SYMBOL
TEST
MIN
TYP
VOH
Output Logic "zero"
VOH
Output Logic "one"
3.0
tRPW11
Read Pulse Width
250
200
tRPW10
Read Pulse Width
500
400
MAX
UNIT
0.8
V
One TTL Load
V
One TTL Load
CONDITIONS
ns
ns
tAD
Address Delay Time (12)
tAG
Address- Read Pulse Gap (12)
50
ns
tAl
Address to Output Delay
625
700
ns
(9)
tA2
End of Read Pulse to Output Delay
200
250
CIN
Address Input Capacitance
10
pF
tOE
Output Enable to Output Delay
250
ns
r=
100
50
ns
(9)
lMHz.
VAC = 25mV POp
VIN = VCC
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operet[on of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied.
2. For operating at elevat:d temperatures the device must be
derated based on a +150 C maximum Junction temperature .and
0
a thermal resistance of 110 C/W Junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless
specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and improvements.
7-114
7. Typical values are at +26° C and nominal supply voltages.
8. Outputs Open, tRPw
9. tA
0
= OoC to +70
=
250ns, t RPW
=
500ns.
C
10. During t RPW1 data is clocked into the output latches and the
address decoders are precharged in preparation for the next
cycle.
11. During t R PW1 addresses are decoded and sent to the memory
matrix; and the stored memory data is moved to the data inputs
of the output RS latches. This data is clocked into the output
latches at the end (rising edge) of the READ pulse. After t A2 ,
data appears at the output terminals.
12. Addresses must be stable within 50ns after the READ line falls
and must remain stable until at least 50ns before the READ
line goes high.
SI LICON GATE MOS. 2526
TIMING DIAGRAM
lr"~-I
;I
tF!Pw
'\
1..
'AG
..-.
tA2
ADDRESSES
MAY
CHANGE
ADDRESSES
MUST BE
STABLE
ADDRESSES
MAY
CHANGE
I·
OUTPUTS
\
f
11
ADDRESSES
-I
·1
I
tAl
'1
X
X
Note: All times measured from 50% points, for all input waveforms tr
= tf<10nsec.
7·115
SILICON GATE MOS. 2526
CHARACTER FONTS
eM 3400
ASC I I SET, VERTICAL SCAN 7X9 WITH CODE CONVERSIONI1)
i
':!. :~! ' 1~!' :u: ' !~'
I; I~ i, :10:;: 0; 0
.~ • • • • II • •
O
. . • •'. .M..:.A.. :: L
E
AOO,"O.....C
'.A._A"OI
::
. .....
DECIMAL ADDRESS "8"
~~M:L-t AO RES .. ~'<~
.'" . . -t..=, 'MA~._. _ ".~." .•.• .:. .
t. . E.:o
.•
C
.:.•. . .
i~_
'.~ :C ALAO~-:
I
....
'..
..
.' . . '.M. AL.AOOR,.
.-. .R•.S.S
. .O_E.:::
. '. .,.'.MALADDRESS
. "_'." I]0.'.E.
C
. :•. . AOO._.R'SS
.
.:. •-..
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. •. :.':•.M. ALAO
O
. OR-•. SS. "4,"
•
O'::.C
'. •SS,,:.:.:"." O
•.....•................
C
. . :.• .':•. M
:.• AL.AOO.RE. ..S.'.S "6"- 0
. :.:........ •.'•. :.M•:. : , g
DECIMAL ADDRESS "9"
OECIMAL ADDRESS "10"
DECIMAL ADDRESS """
_~
=;> ~ - _ -
OECIMAL ADDRESS "12"
DECIMAL ADDRESS "'3"
"7"
_. - ; ' ;
DECIMAL ADDRESS "'4"
DECIMAL ADDRESS "15'
••••••••
"a'·:} .:.:. • ••...
:. •.
:. •.
:. •.
DECIMAL ADORESS "'6"
-
~J.'
...
~
..'•. :.
DECIMAL ADDRESS "'7"
-'
_.
.: -----:--
_I.:.:.
._
.i.• .•·.:.:
.•·..•..•...
•
_
·1,
,
DECIMAL ADDRESS "24"
oeCIMAL ADDRESS "'8"
_ .. _
<1
.. ', ..'
DECIMAL ADDRESS "25"
DECIMAL ADDRESS "'9"
. .~:. . . - ' .
:'.~.:~.
__
--
-
/, •.:•. • . •'. •
:: .. :. . :
::\"'::.
:". ::::::,::
.•.:.:. ';
DECIMAL ADDRESS ":26"
OECIMAL ADDRESS "20"
. . . . . ____ .-:. -
"
.
....
_ __
..'
'~
DECIMAL ADDRESS "27"
OECIMAL ADDRess "21"
_.. _
---- .
"-= -
:::':
--
. ::
. .
DECIMAL ADDRESS "29"
:!://: -- _
-
DECIMAL AODRess "23"
::L!?) - - __
"::. ::':,:
. _......
•.••.•.•••.••• : .',
DECIMAL ADDRESS "22"
--
1
..: . _ " "
. . i ' , .. _
. . • :.• .:.••..••.. ,
DECIMAL ADDRESS "29"
.,' .
DECIMAL ADDRESS "30"
J_
>:~.;
':.: ,. . . :. . . . .
. .......'
1_
DECIMAL ADDRESS "31"
lID II • • • • • •
DECIMAL ADDRESS "32"
DECIMAL ADDRESS "33" DECIMAL ADDRESS "34"
·.• .• ~.•··.'l.··.--.. t.· ~.-,
•
~.,.,
~
_..
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i:::."
::' :.':::
OECIMAL ADDnE:SS "4'"
•
~r.:.~·
~
i
-
--
/:
DECIMAL ADDRESS ":.te"
~
•
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DECIMAL ADDRESS "37"
DECIMAL ADDRESS "3a"
•
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:.- . -,.
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c..•.:••..
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DECIMAL ADDRESS "4:2"
•...
-
DECIMAL ADDRESS "43"
r;[lCt,
. . . •'.;::-:..._'
. . ...
•' ........................
~-::::::;:. __
DECIMAL ADDRESS "36"
.~:::;:~ -
'Cj.::~:; _""_
--
-
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-
A
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DECIMAL ADDRESS "44"
DECIMAL ADDRESS "45"
II'.'.:."
."
. :-_
;'
....•.......
i ... ,- •
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- L
:?___
_
,:::,
DECIMAL ADDRESS "39" ,
,~ :t~
DECIMAL ADDRESS "47"
~
:::::/::.
. _ __ ._
DECIMAL ADDRESS "46"
<:;
--_.-
~
--
.:.:::~::}:'
\{
__
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.
"",:':':
_
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I
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• • • • • •III.
DECIMAL ADDRESS "56"
D~CIMAL ADDRESS "67" DECIMAL ADDRESS "68" DECIMAL ADDRESS "69"
DECIMAL ADDRESS "60"
NOTES
1.
2.
BCOIC to ASC I I in leftmost column, Baudot to ASC I I in next column to right,
Undefined addresses result in all outputs going low (TTL "0").
3.
Blank squares in character font are high (TTL "1 ").
7·116
DECIMAL ADDRESS "6'"
DECIMAL ADDRESS "62"
DECIMAL ADDRESS "63"
SI LICON GATE MOS. 2526
CHARACTER FONTS (Cont/d)
eM 3940
ASC I I SET, RASTER SCAN 7X9 WITH CODE CONVERSION(1)
0111
0100
0101
o
I
1 1
1000
·
...
, .',:.:',~.'."::;:;:
.':."'. .
.
• • ::~,.:~".:"; •.•
'.'. .
•'.;::i;;.,. . •. :.• .'
II,.,.",.",
::;::'
-
;:'::
; :~:;
::::;: ::::::
: ;~;
.
i~i: ! {::l : ' i I:i~;;I ' · ' · " : " " " .
: ~:.•:'.:
:{: ::}.
:~:~:
"
. .'
. .--
:}::
11';,.·,,',·.·,·.;;·······
; ;~
:} .:/;
-
-
.'•.•.
!:"...'~".~. ~ ~ .•
~~"" . . -' 'l1i~-"'""-' ~ 'gf''"'-'
mm 1111 i i i KfiJ,
DECIMAL. ADDRESS "8"
DECIMAL ADORESS "9"
DECIMAL ADDRESS "10"
DECIMAL ADDRESS "11"
DECIMAL ADDRESS "12"
OECIMAL ADDRESS "'3"
1mI·
DECIMAL ADDRESS "'4"
DECIMAL ADDRESS "15"
••••••••
••••••••
.•. . . B
.::· .:.:_.i
.... .
••••••••
••••••••
••••••••
DECIMAL ADDRESS "'6"
DECIMAL ADDRESS "'7"
DECIMAL ADDRESS "'8"
DECIMAL ADDRESS "19"
DECIMAL ADDRESS "20"
DECIMAL ADDRESS "2'"
DeCIMAL ADDRESS "22"
DECIMAL ADDRESS "23"
DECIMAL ADDRESS "24"
DECIMAL ADDRESS "25"
DECIMAL ADDRESS "26"
DECIMAL AODRESS "27"
DECIMAL ADDRESS "28"
DECIMAL ADDRESS "29"
DECIMAL ADDRESS "30"
DECIMAL ADDRESS "31"
~,
-
;!i
.....
lIB:·
~H.!.m
~
II:;~~
DECIMAL ADDRESS "32"
DECIMAL ADDRESS "33" DECIMAL ADDRESS "34"
DECIMAL ADDRESS "35"
DECIMAL ADDRESS "36"
DECIMAL ADDRESS "37"
DeCIMAL ADDRESS "3S"
DECIMAL ADDRESS "39"
DECIMAL ADDRESS "40"
DECIMAL ADDRESS "41" DECIMAL ADDRESS "42"
DeCIMAL ADDRESS "43"
DECIMAL ADDRESS "44"
DECIMAL ADDRESS "45"
DECIMAL ADDRESS "46"
DECIMAL ADDRESS "47"
DECIMAL ADDRESS "4S"
DECIMAL ADDRESS "49"
DECIMAL ADDRESS "60"
DECIMAL ADDRESS "61"
DeCIMAL ADDRESS "62"
DECIMAL ADDRESS "63" DECIMAL ADDRESS "54"
DECIMAL ADDRESS "56"
oeCIMAL ADDRESS "56"
DECIMAL ADDRESS "67"
DECIMAL ADORES's "68" DECIMAL ADDRESS "69"
DECIMAL ADDRESS "60"
DECIMAL ADDRESS "6'"
DECIMAL ADDRESS "62" DECIMAL ADDRESS "63"
NOTES
BCDIC to ASC I I in leftmost column, Baudot to ASC I I in next column to right.
Undefined addresses result in all outputs going low (TTL "0").
Blank squares in character font are high (TTL ",").
,.
2.
3.
7-117
!ii,gnotiC!i
2527
2528
2529
DUAL 256·250·240 BIT
STATIC SHIFT REGISTERS
PRELIMINARY SPECIFICATION
SILICON GATE 2500 SERIES
DESCRIPTION
BIPOLAR COMPATIBI LlTY
The Signetics 2500 Series Dual 256, 250 and 240 bit recirculating static shift registers consist of enhancement mode
P-channel silicon gate MOS devices integrated on a single
monolithic chip.
The clock and signal inputs of these registers can be driven
directly by standard bipolar integrated (TTL, DTL, etc.) or
by MOS circuits. The outputs drive directly into TTLIPTL
without requiring external resistors.
FEATURES
PIN CONFIGURATION (Top View)
•
•
PUSH-PULL OUTPUTS
TTL/DTL COMPATIBLE CLOCK - PROVIDES EXTREMELY LOW CLOCK CAPACITANCE
• RECIRCULATION PATH O,N CHIP
• THREE BIT LENGTHS AVAILABLE
• HIGH FREQUENCY OPERATION - 3 MHz TYPICAL
CLOCK & DATA RATE
• TTL, DTL COMPATIBLE INPUTS AND OUTPUTS
• STANDARD PACKAGE - 8 LEAD SILICONE DIP
• SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
APPLICATIONS
lOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST STATIC BUFFER MEMORIES
CRT REFRESH MEMORIES - LINE STORAGE
DEt.AY LINES
CASSETTE RECORDERS
V PACKAGE
10'
2
7
8
3
6
4
5
1. Recirculate
2. IN1
3. OUT1
4. VGG
8. Vee
7. IN 2
6. OUT2
5. ct>IN
TRUTH TABLE
RECIRCULATE
INPUT
FUNCTION
0
0
1
1
0
1
0
1
Recirculate
Recircu late
"0" is Written
"1" is Written
BLOCK DIAGRAM
NOTE:
"0"
= OV; "1" = +5V
PART IDENTIFICATION TABLE
+Vcc
PART
NUMBER
2527V
2528V
2529V
BIT LENGTH
Dual 256
Dual 250
Dual 240
PACKAGE
8 Pin DIP
8 Pin DIP
8 Pin DIP
MAXIMUM GUARANTEED RATINGS (1)
Operating Ambient Temperature (2)
IN2'
I
N BIT REGISTER
I
IL_______________ _
Storage Temperature
Package Power Dissipation
at T A = 70°C
Data and Clock Input Voltages
and Supply Voltages with
respect to V CC
7-118
535mW
+0.3V to -20V
SILICON GATE MOS. 2527,2528,2529
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied.
2. For operating at elevated temperatures the device must be derated
basedona+1500e maximum junction temperature and a thermal
resistance of 150° e/w junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are val id over operating temperature range unless
specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and improvements.
7. Typical values are at +25°e and nominal supply voltages.
8. Vee tolerance is ±5%. Any variation in actual Vee will be
tracked directly by VIL, VIH, and VOH which are stated for a
Vee of exactly 5 volts.
DC CHARACTERISTICS TA = O°C to +70°C; VCC = +5V(8); VGG = -12V ±5% unless otherwise noted.
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
III
Input load Current
10
500
nA
VIN = 5.5V, T A = 25°C
IlC
Clock leakage Current
10
500
nA
VILC = OV, T A = 25°C
IGG
Power Supply Current
28
35
mA
VIL.
Input "Low" Voltage
1.05
V
VU-I
Input "High" Voltage
5.3
V
VILC
Clock Input "Low" Voltage
1.05
V
VII-IC
Clock Input "High" Voltage
5.3
V
-~--
-
Continuous Operation
F = 2.5 MHz, T A = 25°C
Outputs Open
----3.2
-~
~~
3.2
AC CHARACTERISTICS T A =0° to +70°C, VCC = +5V(8); VGG = -12V +5%, VIC = 0,4 to 4.0V
Clock Rep Rate
DC
2.5
1.5
MHz
t¢pw
Clock Pulse Width
0.2
0.1
100
fJ,S
t¢pw
Clock Pulse Width
0.2
DC
fJ,s
1
fJ,s
FREQUENCY
See Maximum Frequency Curve
tR tF
Clock Pulse Transition
tDS
Data Set-up Time
50
tDH
Data Hold Time
50
tA
Clock to Data Out Delay
tR's
Recirculate Set-up Time
50
tRH
Recirculate Hold Time
50
CIN
Input Capacitance
5
pF
@
C¢
Clock Capacitance
5
pF
@
VOL
Output "Low" Voltage
0.4
V
1 TTL load (IL = 1.6mA)
VOHI
Output "High" Voltage
Driving 1 TTL Load
3.0
3.5
V
1 TTL load (II = 100fJ,A)
VOH2
Output "High" Voltage
Drivi
MOS
3.5
4.0
V
ns
ns
330
450
ns
IOL = 1.6mA
ns
ns
1 MHz;VIN=VCC;
V AC = 25mV POp
1 MHz; V¢ = VCC;
V AC = 25mV POp
CONDITIONS OF TEST I nput rise and fall times: 10 nsec. Output load is 1 TTL gate.
7·119
SILICON GATE MOS. 2527,2528,2529
TIMING DIAGRAM
'Os
1 _ • I .... I
1 +,1
'OH
r r---------o-----jW~---------...,...
+6
OATAIN
I--+6
OATAOUT
:
_______
tA-I
\J.:
. 3 OV
-- --
--I-' _____ -1~o::.O.4;:,::V_ _ _ __
O
'lis
I.' I_ • 1
'AH
RECIRCULATE-_-_-_-_-_-~'"'\O~,..6O%-_-_-_-_-_-_-_-_-.
-_-_-_-
'R • 'F
< 10 NSEC FOR ALL INPUTS
APPLICATIONS INFORMATION
TTL/OTL/MOS INTERFACES
Note: When using 7400 series data, recirculate and clock' drivers,
connect 10k resistor from driver output to Vee. This insures an
adequate "1" level input for the MOS register. See page 13'01 MOS Handbook.
7·120
.SILICON GATE MOS. 2527,2528,2529
SCHEMATIC DIAGRAM
INPUT (1 OF 2)
1------- -
BASIC CE LL
-;2 T
OUTPUT STAGE (1 OF 2)
-;,- ---;;- - ; ; - - 1 - -4>;- ---4>3-;;----'
~
1
1
I
OUT
I
1
+-_ _ _ _~__r-_ _ _~~______~~~
VCC~T-r--~_~~~~r-_~_ _ _
RECo-+-r---~~--~
-
-
-
L--~------------+4~------~
--;~GENER~~pfcH-;;;-- -
-
I
I
- 1 - _.J - - - - - - - - - - - ~
I
I
4>3 I
~-_-I--"""'4>11
4>IN
o--+-If--I-I
I
~~----~I
VCI o-~+-+--+-~~--~~~-~~
I
I
i
I
I
4>21
I
1
I
I
_______________ J
~
CLOCKING WAVEFORMS
EXTERNALt
CLOCK
_IN
+5~~
o
4>1_::~~
INTERNALLY
GENERATED
CLOCKS
4>2_::~rr----I
+5
-12
14>3 15 USED FOR STATIC OPERATION)
~
~ ,OO~S MIN. - . J
7-121
SILICON GATE MOS. 2527, 2528, 2529
CHARACTERISTIC CURVES
POWER DISSIPATION VS SUPPLY VOLTAGE
SUPPLY CURRENT VS SUPPLY VOLTAGE
50
1000
900
O°C
, 25°C
700
/./' J
;'~
30
~~
h
500
./
~~
400
/.
300
k~
.-
TYPICAL
OPERATING
RANGE
V
11
1 .....
-
~ t;/
V
/
f = 3 MHz
VCC = +5V
¢IN • 180n.
¢IN = 150n,
LOAD = TTL Gate
-
10
o
12
13
14
15
16
10
5
VGG (-VI
VGG I-VI
TYPICAL DATA RATE VSSUPPLY VOLTAGE
10.0
9.0
8.0
7.0
6.0
5.0
¥
!§
4.0
i:;
iii
=>
~
3.0
-- --
2.0
--
~
~
~
TA = 25°C
Vce = +5V
VIC = + 0.4 to 4.0V
J
1.0
6.0
7-122
~
/
,./
f · 3 MHz
Vec· +5V
¢IN·180n,
¢IN = 150n,
LOAD = TTL Gate
I---
(Note greatly reduced power at lower VGG leveL)
10
/1-'..........
70°C
/ ...... /
I
I
100
/
///
20
~V
~~ I~
L---::: ~
70°C
V/'/
600
200
o°C
25°C
40
800
7.0
8.0
9.0
10.0
11.0
12.0
13.0
11
12
I
I
13
14
15
SILICON GATE MOS. 2527,2528,2529
APPLICATIONS INFORMATION
(Cont'd)
12 LINE, 32 OR 40 CHARACTER PER LINE CRT DISPLAY MEMORY SYSTEM
DOT RATE CLOCK
(2)
POSITIVE VIDEO
2518B
OR
2519B
DATA INPUTS
6 BIT ASCII
t-----I
2516NX
CHARACTER
GENERATOR
LINE MEMORY
32 X 601 40 X 6
BLANKING INHIBIT
3k
8266B
MAIN MEMORY 512 X 6
ROW COUNT CLOCK
(1) Duals connected in series.
(2) These registers include internal recirculate. Two 8266B multiplexers are used for system recirculate.
7-123
Smnotics
HIGH SPEED 512x8 STATIC READ·ONlY MEMORY
2530
SILICON GATE MOS 2500 SERIES
ADVANCE SPECIFICATION
PIN CONFIGURATION (Top View)
DESCRIPTION
The 2530 is a high speed 4,096-bit Static Read-Only
Memory available in a 512x8 organization. This device has
TTL compatible inputs and outputs and requires +5V and
-12V power supplies. A READ input controls the entry of
data from the ROM into ou'tput latches. Three-state outputs allow OR tying for implementing larger memories. Two
OUTPUT ·ENAB LES control the eight output devices without affecting address circuitry.
Nil PACKAGE
FEATURES
•
•
•
•
•
•
•
•
•
512x8 ORGANIZATION
625n5 TYPICAL ACCESS TIME
STATIC OPERATION
ADDRESS LATCHES
TTL/DTL COMPATI BLE INPUTS
TTL/DTL COMPATIBLE THREE STATE OUTPUTS
VCC = +5V, VGG = -12V
24-PIN SI LlCONE DIP
SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
APPLI CATI ONS
MI CRO-PROGRAMMI NG
CODE-CONVERSION
1.
Output 6
24.
2.
Output 7
23.
Vcc
Output 5
3.
Output 8
22.
Output 4
4.
Voo (Gnd)
21.
Output 3
5.
Address 1
20.
Output 2
6.
Address 2
19.
Output 1
7.
Address 3
18.
Read
8.
Output Enable 1
17.
NC
9.
Output Enable 2
16.
Address 9
10.
Address 4
15.
Address 8
11.
Address 5
14.
Address 7
12.
VGG
13.
Address 6
BLOCK DIAGRAM
BIPOLAR COMPATIBiliTY
OUTPUT
ENABLE 1
All inputs of the 2530 can be driven directly by standard
bipolar integrated circuits, (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA
sufficient to drive one standard TTL load.
STANDARD TRUTH TABLES
The 2530NX/CM3530 is an ASCII-EBCDIC and EBCDICASCII code converter. Use this device for evaluation or for
applications requiring this conversion. Other standards will
be announced as they become available.
PART IDENTIFICATION
PART
OP. TEMP. RANGE
PACKAGE
2530N
0-70°C
24-Pin Silicone DIP
25301
0-70°C
24-Pin Ceramic DIP
7·124
CUSTOM TRUTH TABLES
See page 7-196.
SILICON GATE MOS. 2530
MAXIMUM GUARANTEED RATINGS (1)
Package Power Dissipation 2 @ 70° C
Input 3 and Supply Voltages·
with respect to V CC
o°C to 70°C
_65° C to +150° C
Operating Ambient Temperature
Storage Temperature
730mW
+0.3 to -20V
DC CHARACTERISTICS
T A =0° to + 70°C, V CC= +5V; V GG= -12V ±5%; unless otherwise noted. (See notes 4,5,6,7)
SYMBOL
III
TEST
MIN
Input Load Current
TYP
MAX
UNIT
10
500
nA
CONDITIONS
VIN = -5.5V
TA = 25°C
ILO
Output Leakage Current
10
nA
1000
VOUT = OV
TA = 25°C
VCE = VCC
ICC
V CC Power Supply Current
30
45
mA
(8)
IGG
VGG Power Supply Current
30
45
mA
(8)
VIL
Input Logic "'0"
-5
1.05
V
VIH
Input Logic "1"
3.2
5.3
V
AC CHARACTERISTICS
TA = O°C to 70°C; VCC = 5V ± 5%, VGG = -12V ± 5% unless otherwise noted.
SYMBOL
TEST
MIN
TYP
CONDITIONS
MAX
UNIT
0.8
V
One TTL Load
V
One TTL Load
VOH
Output Logic "zero"
VOH
Output Logic "one"
3.0
tRPW 11
Read Pulse Width
250
200
tRPW10
Read Pulse Width
500
400
tAD
Address Delay Time (12)
50
ns
tAG
Address- Read Pulse Gap (12)
50
ns
tA1
Address to Output Delay
625
700
ns
(9)
tA2
End of Read Pulse to Output Delay
200
250
CIN
Address Input Capacitance
10
pF
tOE
Output Enable to Output Delay
250
ns
r=
100
ns
ns
(9)
1MH,.
VAC = 25mV POp
VIN = VCC
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied.
2.
For operating at elevated temperatures the device must be
0
derated based on a +150 C maximum junction temperature and
a thermal resistance of 110° C/W junction to ambient.
3.
All inputs are protected against static charge.
4.
Parameters are valid over operating temperature range unless
specified ..
5.
All voltage measurements are referenced to ground.
6.
Manufacturer reserves the right to make design and process
changes and improvements.
7.
Typical values are at +25°C and nominal supply voltages.
8.
Outputs Open, tRPw
=
250ns, t RPW
=
500ns.
9. t
=00CtO+700C
A
10. During t RPW1 data is clocked into the output latches and the
address decoders are precharged in preparation for the next
cycle.
11. During t RPW1 addresses are decoded and sent to the memory
matrix; and the stored memory data is moved to the data inputs
of the output· RS latches. This data is clocked into the output
latches at the end (rising edge) of the READ pulse. After t
,
A2
data appears at the output terminals.
12. Addresses must be stable within 50ns after the READ line falls
and must remain stable until at least 50ns before the READ
line goes high.
7·125
SILICON GATE MOS. 2530
TIMING DIAGRAM
I
-tRPW
I
ADDRESSES
~I-
- t RPW - - - -
H
-'" I
ADDRESSES
MUST BE
STABLE
-
OO~
\
I
'\
ADDRESSES
MAY
CHANGE
_I
_____ tA2 - - - - - - - - -
ADDRESSES
MAY
CHANGE
~-- - - - - - - - - t A1 - - - - - - - - - - _ _ [
X
_ - - - - - - J
V
Ii\I.--
_ _ _ _ _ _
Note: All times measured from 50% points, for all input waveforms tr = tf< 1 Onsae.
7·126
-,
!ii!ln~tiC!i
QUAD 80-BIT STATIC SHIFT REGISTER
2532
SILICON GATE MOS 2500 SERIES
DESCRIPTION
PIN CONFIGURATION (Top View)
The Signetics 2532 Static Shift Register consists of enhancement mode P-Channel silicon gate MOS devices integrated
on a single monolithic chip. Each of the four 80-bit registers
is provided with an independent input, push-pull output
and recirculation control. The single phase clock is common
to all four registers. All inputs and outputs including the
clock interface directly with TTL or DTL circuits without
external components.
B PACKAGE
16
15
14
Data is entered when the clock is at a logic "1 ". Data is
shifted when the clock goes low. When the Recirculate
control is at a logic "1", data recirculates and is continuously
available at the output, data input is inhibited. With the
Recirculate control is at,a logic "0", data is entered.
13
12
11
10
FEATURES
•
•
•
•
•
•
TOTAL TTL COMPATIBILITY
SINGLE CLOCK LINE
RECIRCULATE PATH ON CHIP
DC TO 2.5 MHz OPERATION GUARANTEED
LOW POWER (TYPICALLY 400 ,uW/BIT)
PIN-FOR-PIN REPLACEMENT FOR (DYNAMIC)
MK1007P AND TMS3409
• POWER SUPPLIES +5V AND -12V
1.
OUT 1
16.
2.
Recirculate 1
15.
3.
IN 1
14.
Recirculate 4
4.
OUT2
13.
OUT4
5.
Recirculate 2
12.
6.
IN 2
11.
7.
8.
OUT3
10.
9.
VOO (Ground)
Vee
IN 4
VGG
IN
IN 3
If>
Recirculate 3
TRUTH TABLE
RECIRCULATE
INPUT
FUNCTION
0
0
1
1
0
1
0
1
"0" is Written
"1" is Written
Recirculate
Recirculate
APP LI CATIONS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST STATIC BUFFER MEMORIES
CRT REFRESH MEMORIES - LINE STORAGE
DELAY LINES
DIGITAL FI LTERING
NOTE:
"0"
= OV,
"1"
= +5V
BLOCK DIAGRAM
SPECIAL FEATURES
The three clock phases used by the static register cells are
generated internally by an on-chip generator. This clock
generator is controlled by a single TTL/DTL logic level
input.
.pIN
0----------1
IN
OUT
REC
BIPOLAR COMPATIBILITY
All inputs of these registers, including the clock can be
driven directly by bipolar TTL/DTL integrated circuits without external components. Outputs are push-pull operating
between OV and +5V and provide a sink current of 1.6mA
for one TTL fanout.
PART IDENTIFICATION
E
PART NUMBER
2532B
BIT LENGTH
PAC K'AG E
Quad 80
16-Pin DIP
7-127
SI LICON GATE MOS. 2532
MAXIMUM GUARANTEED RATINGS (1)
Operating Ambient Temperature (2)
O°C to +70°C
Storage Temperature
Package Power Dissipation
at TA = 70°C
DC CHARACTERISTICS
Data and Clock Input Voltages
and Supply Voltages with
respect to V CC
-65°C to +150°C
+0.3V to -20V
640mW
TA
SYMBOL
= ooe to +70oe; Vee = +5V(8); VGG = -12V ±5% unless otherwise noted.
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
= 5.5V, T A = 25°C
III
Input Load Current
10
500
nA
VIN
ILC
Clock Leakage Current
10
500
nA
VILC
IGG
Power Supply Current
6
10
mA
ICC
Power Supply Current
12
20
mA
Continuous Operation
F = 2.5 MHz, TA = 25°C
Outputs Open
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
VILC
Clock Input "Low" Voltage
VIHC
Clock Input "High" Voltage
AC CHARACTERISTICS TA
3.2
3.2
1.05
V
5.3
V
1.05
V
5.3
V
= OV, TA = 25°C
= oOe to 70o e; Vee = +5V(8); VGG = -12V + 5%, Vie = 0.4 to 4.0V
(CONDITIONS OF TEST Input rise and fall times: 10 nsec. Output load is 1 TTL Gate.)
SYMBOL
Frequency
TEST
Clock Rep Rate
MIN
TYP
DC
3.0
MAX
UNIT
1.5
MHz
1:¢PW
Clock Pulse Width
0.18
100
/.ls
t¢pw
Clock Pulse Width
0.22
DC
/.ls
tR,tF
Clock Pulse Transition
5
/.lS
tDS
Data Set-up Time
tDH
Data Hold Time
tA
Clock to Data Out Delay
tRS
Recirculate Set-up Time
tRH
Recirculate Hold Time
CIN
Input Capacitance
120
ns
0
ns
400
ns
CONDITIONS
IOL = 1.6mA
ns
150
ns
0
5
pF
@
Crt>
Clock Capacitance
5
pF
@
1 MHz; Vrt> = VCC;
V AC
VOL
Output "Low" Voltage
VOHI
Output "High" Voltage
Driving 1 TTL Load
VOH2
Output "High" Voltage
Driving MOS
= VCC;
= 25mV POp
1 MHz; VIN
V AC
= 25mV POp
V
1 TTL load (I L = 1.6mA)
4.0
V
1 TTL load (II
4.0
V
0.4
= 100/.lA)
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied.
2. For operating at elevated temperatures the device must be derated
o
based on a +150 e maximum junction temperature and a thermal
resistance of 125°e/W junction to ambient.
3. All inputs are protected against static charge.
7-128
4. Parameters are valid over operating temperature range unless
specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and improvements.
7. Typical values are at +25°e and nominal supply voltages.
8. Vee tolerance is ±5%. Any variation in actual Vee will be
tracked directly by V I L. V I H. and V OH which are stated for a I
Vee of exactly 5 volts.
SILICON GATE MOS! •. 2532
TIMING DIAGRAM
f..t-- tcJ>Pw........ l...- ttPl'w----1
I
I
---....t
90% Ilr
50%
" -_ _.:.:10;,;:%;..t,,
I
I .... I ..... 1
tDs
~
tDH
I
I
r--
10%
tR-+-
I I
tF
+ ,1,..-------~50%
.../'\.....L-"\.. - - - - - - - ---+
+51r
50%~
DATA IN
0- -
-
-
;
I------tA
I
DATA OUT +5
0- -
-
-
-
tRS
RECIRCULATE
tR = tF
<
-
f- - - .- -
/ ..... / ..... 1
~.OV
oJ
O.4V
tRH
--------Ir-,I,..------------------~l50%_______ _
____50%~1
---'lL-}\":'"
10 NSEC FOR ALL INPUTS
CHARACTERISTIC CURVES
POWER SUPPLY CURRENT (ICC)
VERSUS TEMPERATURE
15
POWER SUPPLY CURRENT (ICC)
VERSUS TEMPERATURE
19r---~--~--~--~--~--~--~
I
f'lMHl
VCC=+5V
Voo-ov
VGG'-12V
14
2532
-
f-- ~~~ ~~z12v~~--l--·---
-
..-
..
-
Vee'" +5V
18 t--+---+--+---+-~-f----I-~-I
-
13
i"-....
12
1
r-- r---
u
---
u
t--
11
-r--
15~-+---+--+-~-+-----f----~--4
-- ..10
10
30
20
40
50
60
70
14L---~--~--~--~--~--~--~
40
60
70
20
30
TEMPERATURE (OC)
POWER SUPPLY CURRENT (ICC)
VERSUS POWER SUPPLY VOLTAGE (VGG)
POWER SUPPLY CURRENT (lGG)
VERSUS POWER SUPPLY VOLTAGE (VGG)
6.6 r----...,..-----r---""'!'""----r--~_-..,
2532
17
f·1MHz
TA""2S=>C
f '" lMHz
16
15
,,-I
~I(-t GENERATOR
DATA INPUTS
GBIT ASCII
2532
12)
-
BLANKING INHIBIT
3k
+-""1\,..,...........-0 +5V
ROW COUNT CLOCK
I
L
I
MAIN MEMORY
-2.02~8 _
-l
(1) These registers include internal recirculate. Two 82668 multiplexers are used for system recirculate.
7·130
1024·81T STATIC
SHIFT REGISTER
!ii!lDotiC!i
2533
PRELIMINARY SPECIFICATIONS
DESCRIPTION
PIN CONFIGURATION: (Top View)
The Signetics 2533 Static Shift Register consists of
enhancement mode P-channel silicon gate MOS devices
integrated on a single monolithic chip.
"V" PACKAGE
The 1024-bit register is equipped with two data inputs
together with a "Stream Select" control to facilitate
external recirculation.
Out
The single phase clock input, data input, data output, and
stream select control will interface directly with TTL/DTL
circuits without external components.
1
Stream
Select
3
Voo (GNO)
4
8
Vee
Data is entered when the clock is at a logic "1 ". Data is
shifted when the clock goes low.
FEATURES
TRUTH TABLE
•
•
•
•
•
TOTAL TTL COMPATIBILITY
SINGLE CLOCK LINE
DC TO 1.5MHz GUARANTEED
LOW POWER (TYPICALLY 250IlW!BIT)
POWER SUPPLIES +5V AND -12V
E
•
•
8-PIN DIP
STREAM SELECT FOR EASY RECIRCULATION
BLOCK DIAGRAM
STREAM SELECT
FUNCTION
o
IN 1
IN 2
.-~
NOTE:
"'0"' = OV, "'1"' = +5V
APPLICATIONS
LOW COST SEQUENTIAL ACCESS MEMORIES
LOW COST STATIC BUFFER MEMORIES
CRT REFRESH - LINE AND PAGE
DELAY LINES
DRUM MEMORY REPLACEMENT
"IN
O---------f
CLOCK
GENERATOR
SPECIAL FEATURES
The three clock phases used in the static register cells are
generated internally by an on-chip generator. This clock
generator is controlled by a single TTL/DTL 5V logic level
input.
Recirculation of data in the 2533 is accomplished by
simply jumpering the output back to In 2. The stream
select control then becomes a Data Entry/Recirculate
Control.
BIPOLAR COMPATIBILITY
All inputs of this register, including the clock, can be driven
directly bV bipolar TTL/DTL integrated circuits without
external components. Each input is equipped with an
internal pull-Up resistor to enhance the "1" level of the
TTL driver. The output is push-pull, operating between OV
and +5V, and provides a sink current of 1.6mA for one
TTL fanout.
PART IDENTIFICATION TABLE
PART NUMBER
BIT LENGTH
PACKAGE
2533 V
1024
8-Pin DIP
MAXIMUM GUAR~NTEED RATlNGS(l)
Operating Ambient Temperature(2)
Storage Temperatme
Power Dissipation (Note 2)
Data and Clock Input Voltages
and Supply Voltages with
Respect to V CC
O°C to +70°C
-65°C to +150°C
535mW @ T A >25°C
+O.3V to -20V
7·131
SI L ICON GATE MOS. 2533
DC CHARACTERISTICS
(T A = O°C to +70°C; Vec = +5V ±5%; VGG = -12V ±5% unless otherwise noted.)
SYMBOL
TEST
MIN.
TYP.
MAX.
UNITS
CONDITIONS
= 0, TA = 25°C
= GND, TA = 25°C
III
I nput Load Current
10
500
nA
VIN
ILC
Clock Leakage Current
10
500
nA
VILC
ICC
Power Supply Current
16
30
mA
IGG
Power Supply Current
5.0
7.5
mA
VIL
Input "Low" Voltage
0.8
V
VCC
VIH
Input "High" Voltage
V
VCC
VILC
Clock Input "Low" Voltage
VIHC
Clock Input "High" Voltage
F = 1.5MHz
0.8
V
= +5V
= +5V
VCC = +5V
5.3
V
VCC
3.2
3.2
} Continuous Operation
= +5V
NOTES:
1.
2.
Stresses above those listed under "Maximum Guaranteed
Rating" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or at any other condition above those indicated in the
operational sections of this specification is not implied.
3.
All inputs are protected
4.
Parameters are valid over operating temperature range unless
specified.
5.
All voltage measurements are referenced to ground.
For operating at e.levated temperatures .the device mu~t be
derated corresponding to a thermal resistance of 150 C/W
junction to ambient.
6.
Manufacturer reserves the right to make design and process
changes and improvements.
7.
Typical values are at +25°C and nominal supply voltages.
against~static
TIMING DIAGRAM
+5V
---+\._----- t,;pw------r
CLOCK IN
---1---.j.--"I-~
- tDH
+5V - - - - - - - - - - - ' " " " '
DATA IN
,----------+5v------------~
STREAM
SELECT
0---+5v
-"l-
a- - - - - - - - - - - - - - - -
~---------------
NOTE: Times measured at 50% points with input tr, tf .;; 10ns.
7-132
charge.
SILICON GATE MOS. 2533
AC CHARACTERISTICS vcc = +5V ±5%;VGG= -12V ±5%;
SYMBOL
TEST
TA = 0° to +70°C
MIN.
TYP.
2
MAX.
UNITS
CONDITIONS
Frequency
Clock & Data Rep Rate
tcpPW
Clock Pulse Width
DC
.350
t;ppw
t r , tf
Clock Pulse Width
250
tDS
Data Write Set-Up Time
50
tDH
Data to Clock Hold Time
50
tA
Clock to Data Out Delay
tSSH
Stream Select Hold Time
50
ns
tsss
Stream Select Set-Up Time
80
ns
CIN
I nput Capacitance
5
pF
COUT
Output Capacitance
5
pF
Ccp
Clock Capacitance
5
pF
VOL
Output "Low" Voltage
0.4
V
1 TTL load (I=1.6mA)
VOH
Output "High" Voltage
V
1 TTL load (I=-100J1A)
--
Clock Pulse Transition
A.C. TEST SETUP
MHz
us
no;
1
J1S
ns
ns
200
2.4
1.5
100
DC
400
ns
3.5
10L = 1.6mA
1 MHz, VIN = VCC
V AC = 25mV pop
@
1 MHz, VOUT = VCC
VAC = 25mV pop
@
1 MHz, V¢= VCC
VAC = 25mV POp
@
APPLICATIONS INFORMATION
2048-BIT STORAGE REGISTER
WITH RECIRCULATE
'5V
IN,
Dour
2533
S. SEL
S. SEL
CL~DIO-t_ _-+--+_ _--'
NOTES:
Measure T A between device input and point (a).
Gates are standard 8800 or 7400.
NOTE:
Gates are standard DTL or TTL.
7·133
SI LICON GATE MOS. 2533
CHARACTERISTIC CURVES
POWER SUPPLY CURRENT (Icc!
VERSUS
TEMPERATURE
POWER SUPPLY CURRENT (lGG)
VERSUS
TEMPERATURE
6.0
2533
f= 1 MHz
'- VGG = ~12V--l---~~I-~---e---VCC = +5V
18~--+---~---+----~--+---~--~
5.9
............
['-...
5.8
«
E
~-f----.--
'~
'~
~r---- -"+--~-'1-- ~-I--~-~.- -I--~",---l
'"
<>
5.7
f------I-----~-.-~f-~-
r----~----+----4---_r---+---~~-~
15~--+---~---+----~--+---~--~
f-----
-
~---
f-- --
-~
-
5.6 ~---+-----+----+---+----+---+--~
r---
---
~ ----4--~__t_--i
--
e· - ---
14L---~---L--~----~--~---L--~
10
20
30
40
50
60
70
10
20
30
TA ( CI
POWER SUPPLY CURRENT (ICc!
VERSUS
POWER SUPPLY VOLTAGE (VGG)
20
2533
J
I
f= 1MHz
19 I - TA = 25 C
18
.,.
V
11
u
u
~
1~
V
-"
15
~~
50
60
70
POWER SUPPLY CURRENT (IGG)
VERSUS
POWER SUPPLY VOLTAGE (VGG)
6.6
V
./
2533
6.2
V
./
~
.---------r-----r-----r------r----~--___,
6.4
r---+---i--
6.0
-.JCC
«
E
-.JCC
~~
40
TA ( CI
«
E
V
'"
5.8
.!?
5.6
-.JCC
14
V
..........
5.4 f----+----¥~-f-----+---_;_---f
5.2 r-----bo'~--T_---l-----I-----+----l
13
5.0
12
~11
~12
VGG (VI
7-134
13
L.....-__-L____....L____L-__---L._ _ _.....L..._-'
~11
~12
VGG (VI
--13
!ii!lnotiC!i
UNIVERSAL ASYNCHRONOUS
FIRST·IN, FIRST·OUT BUFFER REGISTER
SILICON GATE MOS2500 SERIES
PRELIMINARY SPECIFICATION
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The Signetics 2535 is a P-Channel MOS asynchronous
buffer memory consisting of 32 8~bit words. Both' input
and output can be either serial or parallel with a data rate
of DC to 1 MHz in either mode of operation.
I PACKAGE
The register is designed so that information entered at the
input will "fall through" to the lowest unoccupied location.
I nput and output may be accessed asynch~onously. Control
logic provides flag signals indicating presence of data and
availability status of empty storage locations.
The 2535 may be expanded in either the bit or word
direction. All inputs and outputs are directly DTL/TTL
compatible.
28
27
26
1. Input 2
25
24
4. Extenp
23
6. Serial Output
22. Input 7
21.lnputB
Output 2
21
20. Fullness Flag (8)
20
18. LOad Control/Clear
Output 3
19. Fullness Flag (161
Output 4
Output Enable
Output 5
13. OUtput 6
24.lnput5
23. Input 6
Control
7. Output 1
• ASYNCHRONOUS LOAD AND DUMP
• 32 WORD BY 8-BIT ELASTIC STORAGE
• DC TO 1 MHz OPERATION
• SERIAL OR PARALLEL OPERATION
• TTL COMPATIBLE
• 28-PIN DIP PACKAGE
• VCC = +5 V, VGG = -12 V
26. Overflow Indicator
25. Vee
5. Dump Control
8.
9.
10.
11.
12.
28. Input 3
27. Input 4
2. Input 1
3. VGG
FEATURES
2535
*
11.Serial Input Con,rol
10
16.Ground
15.oLtput 8
14, Output 7
·12
13
14
APPLICATIONS
INTERFN~E
BETWEEN INDEPENDENTLY
CLOCKED SYSTEMS
KEYBOARD TO LINE BUFFER MEMORY
DISC AND TAPE BUFFER MEMORIES
DATA CONCENTRATORS
DATA "SILO'S"
BIT RATE SMOOTHING
MODEMS
CPU/TERMINAL BUFFERING
~In
conjunction with pin 26.
'PART IDENTIFICATION
PACKAGE
OP. TEMP. RANGE
28-Pin Ceramic DIP
MAXIMUM GUARANTEED RATINGS(l)
Operating Ambient Temperature
Storage Temperature
BIPOLAR COMPATIBILITY
All inputs of the 2535 can be driven direotly from TTL
output levels. Outputs will sink and source sufficient
current for one TTL fan-out.
-65°C to +150°C
Package Power Dissipation(2) @ T A 70°C
I nput(3) and Supply Voltages
with respect to VCC
3.13 W
+0.3 to -20 V
7·135
SILICON GATE MOS. 2535
DC CHARACTERISTICS
TA = o°c to 70°C, VCC = 5 V (8), VDD = GND, VGG = -12 V ±5% unless otherwise noted. (Notes 4,5,6,7,8)
SYMBOL
TEST
III
I nput Leakage
ILO
Output Leakage (Tri-State Outputs)
VIH
Input High Level Voltage (all inputs)
VIL
Input Low Level Voltage (all inputs)
VOH
Output High Voltage (all outputs)
TYP.
MIN.
VCC -1.5
CONDITIONS
MAX.
UNIT
500
na
Vin = GND
500
na
Vout = Chip Enable = GND
VCC +0.3
V
VCC -3.8
VCC -2.0
V
IOH = 2.6 mA (source)
V
VOL
Output Low Voltage (all outputs)
CIN
I nput Capacitance (any input)
COUT
Output Capacitance (any output)
ICC
Power Supply Current
60
mA
Outputs open, Output Enable = 5 V
IGG
Power Supply Current
10
mA
Outputs open, Output Enable = 5 V
0.4
V
5
10
pF
f = 1 MHz, V,H = VCC, 25 mVp·p
5
10
pF
f = 1 MHz, V,H = VCC, 25 mVp-p
IOL = 1.6 mA (sink)
AC CHARACTERISTICS
TA.= o°c to 70°C, VCC == 5 V (~), VDD = GND, VGG = -12 V ±5% unless otherwise noted. (Notes 4,5,6,7,8)
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
tRC
Read-In Cycle Time
1
/-lS
tRP
-tRP
Read-In Pulse Width
200
ns
Read-In Pulse Width
400
tRD
Delay from Read-In Rising Edge Time
200
ns
tFD
Delay from Read-In Falling Edge Time
350
ns
1 TTL Load shunted by 20 pF
tRD
Delay from Read-I n R ising Edge Time
120
ns
MOS Loading Equivalent to 20 pF
tFD
Delay from Read-In Falling Edge Time
ns
MOS Loading Equivalent to 20 pF
tSR
Shift-Out Cycle Time
1
/-lS
tsp
Shift-Out Pulse Width
200
ns
tSD
Delay from Shift-Out Rising Edge
200
ns
tEX
Extend Time
500
ns
1 TTL Load shunted by 20 pF
tSD
130
ns
MOS Loading Equivalent to 20 pF
tEX
375
ns
ns
275
ns
0
tED
Data Out to Extend Delay
tFFD
Fullness-Flag Delay Time
800
ns
tOR
Delay from Output Enable Rising Edge
500
ns
tOF
Delay from Output Enable Falling Edge
500
ns
tFT
Fall-Thru Time
2
/-lS
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any
other condition above those indicated in the operational sections
of this specification is not implied.
2. For operating at elevated temperatures the device must be
o
derated based on a +150 e maximum junction temperature and
a thermal resistance of 48°C/W junction to ambient.
7-13.6
1 TTL Load shunted by 20 pF
1 TTL Load shunted by 20 ,:..;':
MOS Loading Equivalent to 20 pF
All Data Outputs & Ex with either TTL
or MOS loading but not mixed loading
1 TTL Load shunted by 20 pF
1 TTL Load with 20 pF shunt capacity
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless
specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process
changes and improvements.
7. Typical values are at +25°e and nominal supply voltages.
8. Vee tolerance is ±5%. Any variation in actual Vec will be
tracked directly by VI L. VIH and VOH which are stated for a
V CC of exactly 5 volts
SILICON GATE MOS. 2535
TIMING DIAGRAMS
READ-IN
FALL-THRU TIME
---~-tRC-··--~--~1
------.
lOR
1
1
I
1
INPu3(
~{{h%JX~_
- - I tRD
1-- t'O-_1
I~-
~TV
~\
OVERF.L_O_W_-I-111
INDICA_~R
I
!-tRP-_I_---tRP_ _ _---!'
SIC)
•
IF FULL
L
tFT
:---
TFT = time required for 1st Byte of data to appear on
on outputs from falling edge of Read-In command ..
- -
FULLNESS FLAGS
~
I
(SIC #8 OR
SHIFT-OUT
----tSR~
~~-
soc pcB)
: r
1~--tFFD--_1
-----I
r-------,.
FFBOR FF16
w~"'" !-,.~
¥'----_
==L~~!~-')~I ___-.----\
i i __ ~~~EMPTY
DATA OUT VALID - -
I
-_I tSD 1---
I NOT VALID I
I~- tEx _
1
7
OUTPUT ENABLE
OUTPUT ENABLE
DATA OUT VALID
-_ltEDI~·-
CIRCUIT DESCRIPTION
INTERNAL ORGANIZATION
- I tOR
1--- --I tOF
....Jt
.:.;OU:.; TP..:.;UT_ _ _ _
HIGH IMPEDANCE STATE ___I
1-
L
BLOCK DIAGRAM
The Block Diagram in Figure 1 shows how the data is
moved and controlled within the FIFO. The input register
accepts either parallel or serial data. I nput data is written
into the storage array in a location specified by the Write
Address Counter. At the s~me time, the Available Storage
Counter is incremented to Indicate the fullness condition of
the FIFO.
The current output byte is au't matically available at the
output register. Data may be extra ed from the register in
parallel or serial form. After the current byte of data is
used, the next output byte is read from the storage array at
the location specified by the Read Address Counter. At the
same time, the Available Storage Counter is decremented to
maintain the proper fullness indication.
Two bits of the Available Storage Counter are supplied to
the user as Fullness Flags. They indicate the buffer capacity
status so that the empty or full conditions can be
anticipated. FF8 indicates 1/4 full status, FF16 indicates
1/2 full status and when both flags are up the buffer is
3/4 full.
INPUT CONTROL
When parallel data is presented to the eight input lines, the
Load Command (LC) is pulsed positive to enter the data
into the buffer. The input data should remain valid for the
width of the LC, and the LC should occur only when the
Overflow Indicator (01) output is low. The 01 low signal
FIGURE 1.
indicates that the input is available for lo·ading. After a
delay following the leading edge of the LC, the 01 will
acknowledge the input by going high. If the 01 remains
high, then the buffer is full and no new data should be
entered. When the 01 goes low, the buffer is again available
for loading.
Serial data is entered into the input register on Input 1. The
Serial Input Clock (SIC) is used to shift the data into the
register. 01 acknowledges each SIC and the 8th SIC causes
the byte in the input register to be inserted into the storage
7-137
SI LICON GATE MOS • 2535
If LC is pulsed during a serial entry before the 8th SIC, the
byte actually entered into the buffer will be a logical OR of
the partially entered serial data and the data at the parallel
inputs. Bit positions in the input register that have not been
shifted into will contain logical zeros.
OUTPUT CONTROL
When a byte is available in the buffer, it falls through to the
output register and is available on the output pins
(assuming the Output Enable signal is on). The Extend
(EX) signal goes high to indicate that data is available at the
output. When the using system is ready for the next byte, it
should pulse the Dump Command (DC) line. EX will then
go low until the next byte is available. EX stays low if the
FIFO is empty.
Serial data is shifted from the output register on Output 8.
The Serial Output Clock (SOC) is used to shift the data out
of the register and EX responds to each clock pulse. The
8th SOC causes the output control logic to retrieve the next
output byte and insert it into the output register.
If DC is pulsed during serial extraction before the 8th SOC,
the next output byte is inserted into the output register and
the remaining partially shifted data is lost. As the output
register is shifted, it is filled with logical zeros.
BUFFER STORAGE
The first byte inserted into an empty buffer falls all the
way through directly to the 8-bit output register.
Succeeding input bytes are written into a random access
memory array with a capacity of 31 x 8. The array is
designed so that it may be addressed at different locations
simu Itaneously. In that way, data may be inserted and
removed at the same time. The Write Address Counter
controls the locations for storing input data and the Read
Address Counter controls the locations from which data is
extracted for the output. Both counters are implemented as
31-bit shift registers that move a single bit along their
length to directly select the desired word lines in the
storage array. This control approach eliminates binary
decoding networks and is possible because both the read
and write locations are always sequentially accessed.
The use of random access memory to implement the
required storage means that the stored data need not be
moved around internally. Only the counters that point to
the data are manipulated in response to loading and
dumping the FIFO. It also means that the fall-through time
is minimized since new data in an empty buffer does not
have to be shifted sequentially through the buffer before it
is available.
RESET
To clear the buffer to its empty state and thus reset all the
control counters, two control signals are used. The 01
signal, which is normally an output from the FIFO, should
be held in a low state by the external reset logic. LC is then
pulsed positive for at least 2 microseconds and returned
low. The hold on 01 is then released, concluding the reset
operation.
7-138
EXPANSION
Increased FIFO capacity can be obtained by using mu Itiple
2535's in serial/parallel organizations. Sixteen-bit words,
for example, may be buffered by operating two eight bit
streams in parallel. In applications where the timing is not
critically fast, the LC, SIC, DC, and SOC may be tied
together and operated in parallel, but only one each of the
01, EX, and FF signals should be used to control the
data flow.
Cascaded operation of more than one FIFO allows
expansion to any word depth that is a multiple of 32. The
2535 control signals may be inter-connected without
intervening logic to form a FIFO of the desired depth. See
Figure 2. Data will automatically fall through to the end of
the chain.
FIGURE 2. CASCADE OPERATION
L_C_ _
S_IC_ _
To control two cascaded devices using parallel data
interconnection between them, it is only necessary to
connect EX from the first device to LC of the second, and
01 from the second device to DC of the first. The inputs to
the first device and the outputs from the second device may
then be operated in the normal modes. When data is
entered into the two device combination it falls through to
the output of the first device and causes the first EX to go
high. The second device sees the EX as a LC, accepts the
data, and responds with an 01 signal which the first device
sees as a DC. In this way the combination acts like one
device with twice the capacity and twice the fall-through
time of a single 2535.
FIFO USAGE
Asynchronous FIFO data stream buffering can come in
handy in many situations. When a data sink, for example,
requires data at a constant rate, the FIFO can provide the
constant data stream while at the same time it can absorb
data at highly variable rates from the data source.
The reverse situation can also apply. Consider a CRT
terminal connected to a computer via a high speed data
line. The terminal uses a large recirculating serial memory
for data storage. A FIFO in the terminal can accept the
constant speed data from the communication line, while at
the same time it can wait for synchronization with the
circulating memory and then dump a burst of data at
high speed.
The circuitry required to implement a FIFO function using
SSI and MSI logic can be considerable indeed. In addition
to the cost of the logic replaced, the economic evaluation
of the FIFO should consider inventory, ordering, testing,
reliabil ity, board space, production, design, and debugging
problems associated with the old approach. In all of these
areas the 2535 can provide significant advantages.
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER (UAR-T)
!ii!lDotiC!i
PRELIMINARY SPECIFICATION
SILICON GATE MOS 2500 SERIES
DESCRIPTION
FEATURES
The Signetics 2536 Universal Asynchronous Receiver-Transmitter is a general purpose, programmable MOS/LSI subsystem integrated on a single monolithic chip. The device
can simultaneously convert asynchronous serial binary
chara~ters to a parallel format (receiver) and parallel binary
characters to serial, asynchronous output (transmitter)
with start, parity, and stop bits added or verified. Both
receiver and transmitter are double buffered and fully
compatible with bipolar logic. The UAR-T may be programmed as follows: the word length can be either 5, 6, 7,
or 8 bits; parity generation and checking may be inhibited;
the parity may be even or odd; and the number of stop bits
may be either one or two. The 2536 is pin compatible with
the TMS 6010, AY-5-1012, TR-1402A, S1757 & COM2502.
•
DATA
HANDLING
EQUIPMENT
(COMPUTER. DISPLAY
PERIPliI:RAL, ETC)
(8)
"-
•
•
•
ASYNCHRONOUS
...
U'AR/T
2636
(8)
"
~SERIAL DATA LINK
•
l---/
SERIAL
TRANSFER
PARALLEL
TRANSFER
PIN CONFIGURATION (Top View)
I PACKAGE
40
39
•
1.
Vce
2.
VGG
Ground
3.
4.
Received data enable
•
•
38
37
38
36
34
33
32
31
30
29
6.
7.
8.
'}
9.
10.
11.
12.
13.
14.
Received data bits
(AD
1
- ADS)
•
•
Parity error
Framing error
15.
Over-run
16.
17.
Status flag enable
1S.
19.
Receiver clock
Reset data available
Oats aveilable
20.
21.
22.
Transmitter buffer empty
23.
24.
25.
Receiver serial input
..
Transmitter ragister empty
Transmitter serial output
27.
. 2S.
"}
29.
28
25
17
24
23
22
21
30.
31.
32.
33.
34.
35.
36.
37.
3S.
39.
40.
•
•
•
DIRECTLY TTL/DTL COMPATIBLE - NO INTERFACING CIRCUITS REQUIRED
FULL DUPLEX OR HALF DUPLEX OPERATION TRANSMITS AND RECEIVES DATA SIMULTANEOUSLY OR ALTERNATELY (AT INDEPENDENT
INFORMATION RATES)
FULLY BUFFERED - ELIMINATES NEED FOR SYSTEM SYNCHRONIZATION: FACILITATES HIGH
SPEED OPERATION.
FULLY PROGRAMMABLE - EXTERNALLY SELECTABLE:
WORD LENGTH: 5,6,7,8 DATA BITS
INFORMATION RATE - UP TO 20K BAUD
EVEN/ODD PARITY
PARITY INHIBIT
SINGLE OR DOUBLE STOP BIT GENERATION
AUTOMATIC DATA STATUS GENERATION:
TRANSMISSION COMPLETE
TRANSMITTER BUFFER REGISTER EMPTY
RECEIVED DATA AVAILABLE
PARITY ERROR
FRAMING ERROR
OVERRUN ERROR
THREE-STATE OUTPUTS, RESETABLE - BUSSING
CAPABILITY:
DATA OUTPUTS
STATUS FLAGS
INTERNAL PULL-UPS ON ALL INPUTS
CLOCK BITS TO DATA BITS RATIO - 16
OPTIONS AVAILABLE- 32, (8,4,2)
HIGH SPEED OPERATION - FROM D.C. TO 320KHz
GUARANTEED
START BIT VERIFICATION-MINIMIZES ERROR
RATE
STATIC LOGIC - STABLE
STANDARD POWER SUPPLIES - +5V, -12V
DUAL .IN-LiNE PACKAGE - CERAMIC
External (master) reset
Oats load strobe
28
27
253 6
Transmitter data inputs
(DB
1
- DBS)
Control load strobe
No parity
Stop bit(s) select
Word length select 2
Word length select 1
Odd/even parity select
Transmitter clock pulse
APPLICATIONS
PERIPHERALS
TERMINALS
PRINTERS
MINI-COMPUTERS
MODEMS
CONCENTRATORS
MULTIPLEXERS
CONTROLLERS
CARD AND TAPE READERS
KEYBOARD ENCODERS
REMOTE DATA ACQUISITION
SYSTEMS
PART IDENTIFICATION
PACKAGE
OP. TEMP RANGE
40-Pin Ceramic DIP
0-70°C
7-139
SILICON GATE MOS. 2536
FUNCTIONAL BLOCK DIAGRAM
MAXIMUM GUARANTEED RATINGS (1)
Package Power Dissipation (2)
@T A
Operating Ambient Temperature
Storage Temperature
7·140
O°C to 70°C
-65°C to +150°C
=
70°C
3.0W(14)
Input (3)and Supply Voltages
with respect to Vee
+0.3 to -20V
SI LICON GATE MOS. 2536
DC CHARACTERISTICS
T A = O°C to 70°C, VCC = 5V (8), V DD = :"'12V ±5% unless otherwise noted. (Notes 4, 5, 6, 7, 8)
SYMBOL
TEST
MIN
VIH
Input "High" Voltage (9)
V IL
Input "Low" Voltage
TYP
MAX
3.2
UNIT.
5.3
V
1.05
V
CONDITIONS
VIH
Clock Input "High" Voltage (9)
5.3
V
VIL
Clock Input "Low" Voltage
1.05
V
IIH
Input "High" Current
10
ua
IlL
Input "Low" Current
1.6
IIH
IlL
Clock Input "High" Current
10
ua
Clock Input "Low" Current
1.6
ma
ICC
V CC Supply Current
20
ma
All Inputs
Logic "High"
V GGSupply Current
10
ma
All Inputs
Logic "High"
Power Dissipation
200
mW
All Inputs
Logic "High"
3.2
=
V IN =
V IN =
V IN =
V IN
ma
5.0V
OV
5.0V
OV
TIMING DIAGRAM AND VOLTAGE. WAVEFORMS
I'
os
DBS-DB,
t6S
----.~,\_
mY. r - - - -
----
-
.~"
"I
150%
cs _ _ _ _
f~~.~
\-
50%
SBS. NP. EPS,
WLS1, WLS2
.50%
-~---
TRANSMITTER DATA INPUT LOAD CYCLE
CONTROL REGISTER LOAD CYCLE
-l5(1%
D A -
1
RDE,SWE
\j'-_50%
______
J Ir-------6(1%
,.--_-+--_ _~II,-
RD 1 - RDa,OR
DA, TBE,PE, FE _ _ _ _ _
+-___
tR
=
tF
-'~
<
- -
50%
10 n sec for all inputt
OUTPUT DELAYS
7·141
SILICON GATE MOS. 2536
AC CHARACTERISTICS
_ 0
T A - 0 C to 70
0c , VCC -_ 5V (8) , V
SYMBOL
fC
BR
-12V ±5% unless otherwise noted. (Notes 4, 5, 6, 7, 8,10,11,13)
DD
TEST
Clock Frequency (12)
MIN
TYP
MAX
DC
480
320
KHz
30
20
kBaud
us
Baud Rate
UNIT
Clock Pulse Width
1.5
1.0
100
tPW1
ct>3
ct>2
Address
Address
Address
Address
Address
4
3
2
1
0
BIPOLAR COMPATIBILITY
All address lines, control lines and data input I ines are directly TTL compatible and defined in positive logic. The
three clocks require high level drivers. The data out line is
a non-inverted current source output requiring a sense amplifier or high impedance gate. (Signetics N575 Clock Driver
and 8T25 Sense Amplifier are recommended.)
GENERAL TIMING AND OPERATION
1. During period 1 internal nodes are precharged. The
rising edge of CL 1 (end of Period 1) clocks input
address and CS data into storage elements.
2. During period 2 the row and column decoders select
the desired bit.
3. During period 3 the information in the bit is exclusive
OR'd with the selected information contained in the
column inversion memory. The· result is sent to the
output. The output information is stable near the
end of period 3.
4. During period 4.thewriteenable circuitry is activated.
The internal data-in level is determined by ex;lusive
OR'ing the actual input with the selected information
contained in the column inversion memory.
5. If a write is desired during period 5, data is written into the selected bit. The information stored in all
other bits sharing the same addressed column is inverted and refreshed. The appropriate bit of the
column inversion memory is also inverted and refreshed.
If a refresh is desired during period 5, the information stored in all bits sharing the same addressed
column is inverted and refreshed. The appropriate
bit of the column inversion memory is also inverted
and refreshed.
SI LICON GATE [MOS. 2548
PART IDENTIFICATION
TYPE
25481
2548XC
PACKAGE
22-Pin Ceramic DIP
(0.4")
22-Pin Plastic DIP
NOTE: "0";, 0 V, "1"
= +5
BLOCK DIAGRAM
OP. TEMP. RANGE
0-70DC
0-70DC
V
MAXIMUM GUARANTEED RATINGS (1)
D
ODC to 70 C
Operating Ambient Temperature
D
D
Storage Temperature
-65 C to 150 C
All Input or Output Voltage with respect +0.3 V to -25 V
to the most positive supply VBB
Supply Voltages with respect to VBB
+0.3 V to -25 V
D
Package Power Dissipation at T A = 25 C
800mW
NOTES:
1. Stresses above those listed under "Maximum Guaranteed
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or at any other condition above those indicated in the
operational sections of this specification is not implied.
2.
The VBB supply should be applied at or before the VCC supply.
3.
tr and tf = 20ns' for all inputs. All timing measurements are
made at the 50% points.
4.
Only CL 1 and CL2 are required for a short read cycle. 60 ns
after CL2 the next cycle can start. No refresh occurs when using
short read cycles.
DC CHARACTERISTICS
D
TA = ODC to 70 C, VCC = 5 V, VBB = 8.5 V ±0.5 V, VOO = -15 ±1 V unless otherwise noted.(2)
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
CONDITlqNS
ILC
Clock Load Current
5.0
fJ.A
VClK = VOO
III
Input Load Current
1.0
fJ.A
VIN = VOO
I
CL1 = VOO
ILO
Output Leakage Current
1.0
VOUT = VOO, CL2 = VCC
fJ.A
CL3 =VCC
D
100
Average Power Supply Current
10.0
mA
TA = 25 C, Tcyc = ~6() ns
IBB
Average Power Supply Current
500.0
fJ.A
T A = 25 C, T cyc = p60 ns
VIL
Input Low Voltage
VOO -1.0
Vec -4.5
V
VIH
Input High Voltage
VCC -1.5
Vct
V
VILC
Clock Input Low Voltage
-16
-14,
V
VIHC
Clock Input High Voltage
VCC -1.5
VCC
IOH
Output High Source Current
IOL
Output Low Source Current
D
V
mA
R L = 1.1 K connec~ed to 0 V
25.0
fJ.A
R L = 1.1 K connec~ed to 0
CAOO
Address Input Capacitance
5.0
pF
CCS
CS Input Capacitance
5.0
pF
CRW
R!W Input Capacitance
5.0
pF
COl
01 Input Capacitance
6.0
pF
CCL1
Cll Input Capacitance
35.0
pF
CCl2
Cl2 Input Capacitance
16.0
pF
CCl3
Cl3 Input Capacitance
25.0
pF
COUT
OutltlJt Capacitance
5.0
pF
0.6
V
VIN =VCC,
-
= 1 ~Hz
VCll = VOO, V~d~ = VCC
VCL2 = VCl3 =V C, f = 1 MHz
7-149
SILICON GATE MOS. 2548
AC CHARACTERISTICS (3)
TA = O°C to 70°C, VCC = 5 V, VBB = 8.5 V ±0.5 V, VDD = -15 V ±1 V unless otherwise noted.(2)
SYMBOL
TEST
MIN.
TYP.
MAX.
UNIT
2.0
ms
CONDITIONS
General Memory Cycle Timing
TREF
Time Between Refresh
T1PW
CL 1 Pulse Width
75
ns
T12
CL 1 to CL2 Gap
75
ns
T2PW
CL2 Pulse Width
240
ns
T23
CL2 to CL3 Gap
50
ns
T3PW
CL3 Pulse Width
70
ns
T31
CL3 to CL 1 Gap
50
ns
TAS
Address & Chip Select Setup Time
40
ns
TAH
Address & Chip Select Hold Time
TOUT
CL2 to Output Access Time
60
ns
230
ns
ns
TCYC
Cycle Time
560
TSRC (4)
Short Read Cycle Time
450
ns
T21 (4)
CL2 to CL 1 Gap (for SRC only)
60
ns
RL
= 1.1
K, CL = 30pF
VREF = 500 tlA
Read/Refresh Cycle Timing
TACC1
CL 1 to Output Access
380
ns
T1PW + T12 + TOUT
TACC1
Address or Chip Select to Output
345
ns
TAS+T12+ T OUT
TRWS3
Read Setup Time
60
ns
TRWH3
Read Hold Time
20
ns
Read/Write Cycle Timing
TRWS2
Write Setup Time
0
ns
TDS1
Data High Setup Time
100
ns
TDSO
Data Low Setup Time
60
ns
TDH
Data Hold Time
20
ns
GENERAL NOTES:
A. Every time a column is accessed during a normal memory cycle (either a READ or a WRITE, but not a SHORT READ), all 64 bits in that column
are refreshed.
B. Refreshing continues to occur even if the device is not selected
(Cs = "1").
CS
C. When
= "1" the Data In and Read/Write inputs are disabled so that no data can be written into the device. When
device is left floating so that many device~outputs can easily be 0 R'ed together.
Cs = "1",
the output of the
D.AO through A4 are the column address lines. A5 through A10 are the row address lines.
E. For proper refreshing, all column addresses (32 of them) must be selected at least once during every 2 ms period.
F. Inputs AO through A 1 0 and Cs are essentially clocked into the device on the rising edge of CL 1. They are then held by internal latches for the
duration of each memeory cycle.
G. The RAM is non-inverting such that data written in as a "1" (DI = "1") is read out as a positive current greater than 600 J.l.A. Data written in as a
"0" is read out as a very small current less than 25 J.l.A.
7·150
SILICON GATE ~OS. 2548
TIMING DIAGRAM
READ/REFRESH CYCLE
READ/WRITE CYCLE
SHORT READ CYCLE
I~--------TCYC--------~~I~--------TCYG----------_I·+-----TSRC~
GLOCK 1
VCC
VDD
GLOCK 2
VCC
VDD
GLOCK 3
VDD
ADDRESS
VCC -1.5 ~~Ir-....,
&
cH1PSEUCT VCC-4.5 .-.~"'_.....
VCC -1.5
READ/WRITE
VCC -4.5
DATA IN
VCC -1.5
VCC -4.5
600llA
DATA OUT
NOTES:
1. Signal may change with no effect.
2. Data I n can go low but cannot go high during this time.
7-151
S!!Inntics
8192- BIT HIGH SPEED
STATIC READ·ONL Y MEMORY
PRELIMINARY SPECIFICATION
DESCRIPTION
2580
SILICON GATE MOS 2500 SERIES
PIN CONFIGURATION (Top View)
The 2580 is a high' speed 8,192 Static Read-Only Memory available in a 2048x4 organization. This device ha_s
TTL compatible inputs and outputs and requires +5V and
-12V power supplies. A READ input controls the entry of
data from the ROM into output latches. Three-state outputs
allow OR tying for implementing larger memories. The outputs are enabled by a programmable four bit select code
applied to four binary chip select terminals.
N,I PACKAGE
24
23
1.
FEATURES
•
•
2048x4 ORGANIZATION
625n5 TYPICAL ACCESS TIME
20
6.
A2
A3
A4
19
A5
A6
17
16.
15.
A7
16
14.
VGG(-12V)
A10
13.
A9
OUTPUT LATCHES
•
BUILT-IN 1 OF 16 CHIP ENABLE DECODER
10.
11.
•
TTL/DTL COMPATIBLE INPUTS
12.
•
TTL/DTL COMPATIBLE THREE-STATE OUTPUTS
7.
8.
9.
18
AS
= +5V, VGG = -12V, VDD = OV
•
24 PIN SILICONE DIP
SIGNETICS P-MOS SILICON GATE PROCESS
TECHNOLOGY
VDD (OV)
eS1
AO
A1
•
•
23.
22.
4.
5.
STATIC OPERATION, NO REFRESHING
VCC
24.
Vee (+5V)
GND
READ
•
•
22
21
2.
3.
10
15
11
14
12
13
21.
20.
19.
18.
17.
eS2
eS3
eS4
OUT 1
OUT2
OUT 3
OUT4
APPL ICATIONS
•
MICRO-PROGRAMMING
•
LOOK-UP TABLES
• CODE CONVERSION
•
RANDOM LOGIC SYNTHESIS
•
CHARACTER GENERATION
PART IDENTIFICATION
PART NUMBER
OP. TEMP. RANGE
PACKAGE
2580N
0-70°C
24-PIN DIP
25801
0-70°C
24-PIN DIP
BIPOLAR COMPATIBILITY
All inputs of the 2580 can be driven directly by standard
bipolar integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA
sufficient to drive one standard TTL load.
7-152
Note: "0"
= OV,
"1"
= +5V
SI L ICON GATE MOS. 2580
BLOCK DIAGRAM
2580
AO
A1
8192 BITS
64 X 128 MATRIX
A2
A3
A4
AS
A6
A7
AS
A9
A10
CS4
CS3
CS2
CS1
16
OUT 4
17
OUT 3
18
OUT 2
19
OUT 1
MAXIMUM GUARANTEED RATINGS (1)
Operating Ambient Temperature
Storage Temperature
oOe to 700e
-65°C to +1500 C
Package Power Dissipation 2 @ 70° e
Input3 and Supply Voltages
with respect to Vee
730mW
+0.3 to -20V
7·153
SILICON GATE MOS. 2580
bc CHARACTERISTICS
T A = O°C to +70°C; VCC = +5V ±5%, VDD
SYMBOL
= OV, VGG = -12V ±5% unless otherwise noted. (See notes 4,5,6, 7)
TYP
MAX
UNIT
III
Input Load Current
TEST
MIN
10
500
nA
ILO
Output Leakage Current
10
1000
nA
CONDITIONS
VIN = -5.5V
TA = 25°C
VOUT = OV
TA = 25°C
VCE = VCC
ICC
VCC Power Supply Current
23
35
mA
(8)
IGG
VGG Power Supply Current
23
35
mA
(8)
VIL
Input Logic "0"
1.05
V
VIH
Input Logic "1"
5.3
V
3.2
AC CHARACTERISTICS
TA = 25°C; VCC = 5V ±5%, VDD = OV, VGG= -12V ±5% unless otherwise noted.
SYMBOL
TEST
VOL
Output Logic "0"
MIN
TYP
VOH
Output Logic" 1"
3.5
tRPW 10
tRPW 9
Read Pulse Width
500
400
Read Pulse Width
500
400
tAD
Address Delay Time (11)
MAX
UNIT
CONDITIONS
0.8
V
One TTL Load
V
One TTL Load
ns
ns
50
tAH
Address Hold Time
tAl
Address to Output Delay
625
700
tA2
End of Read Pulse to Output
200
250
ns
0
ns
ns
Delay
CIN
Input Capacitance
10
pF
f= 1MHz, VAC=
25mV pop
VIN = VCC
NOTES:
1. Stresses above those listed under "Maximum Guaranteed Rating"
7.
Typical values are at +25° C and nominal supply voltages.
8.
Outputs open, tRPW
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
= 500ns,
tRPW
= 500ns.
conditions above those indicated in the operational sections of
this specification is not implied.
2.
9.
derated based on a +150°C maximum junction temperature and
a thermal resistance of 110° C/W junction to ambient.
During tFjpw data is clocked into the output latches and the
address decoders are precharged in preparation for the next
cycle.
For operating at elevated temperaturEls the device must be
10.
During tRPW addresses are decoded and sent to the memory
matrix; and the stored memory data is moved to the data inputs
3.
All inputs are protected against static charge.
4.
Parameters are valid over operating temperature range unless
of the output RS latches. This data is clocked into the output
specified.
latches at the end (falling edge) of the READ pulse. After tA2,
5.
All voltage measurements are referenced to ground.
6.
Manufactu rer reserves the right to make design and process
changes and improvements.
7-154
data appears at the output terminals.
11.
Addresses must be stable within 50ns after the READ I ine rises
and must remain stable until the 8EAD line falls.
SI LICON GATE MOS. 2580
TIMING DIAGRAM
':
"'~ J=~~=t-.ADDRESSES
AND CHIP
SELECT
-I
~
tAD
+ 5 V - - -......
i----...
-tAH
1
+6V - - - - - - - -_ _ _"
OUTPUTS
OV -
_______ _
.J
Note: All measurements made at 50% points.
Input tr tf 10ns.
= =
AC TEST SETUP
+5V
TTL
(8880)
ADDRESSES
I
VCC
An
TTL
(8880)
10pF
On
2580
OUTPUT
TTL
(8880)
READ
READ
CS n
V OD
J
GND
VGG
-=-
-12V
7-155
SILICON GATE MOS. 2580
CODING FORMAT
Coding data for the 2580 may be sent to Signetics via punched cards or via a written truth table. Cards are preferred since errors
are essentially eliminated.
On receipt of a card deck, Signetics will translate the card deck to a truth tab!e using the Signetics Computor Aided Design
(CAD) facility. The truth table will then be sent to the customer requesting engineer for final approval. On receipt of final approval, Signetics will cut the rubylith mask and proceed with manufacture.
CARD FORMAT
(IDENTIFICATION CARDS)
o UMN 89
C L,
COLUMN 10, 11, 12, 13,
CUSTOM NUMBER (ASSIGNED
CUSTOM DESIGN\ATION "/CM"BY SIGNETICS)
BASIC PART TYPE
~
.
~
COLUMN 21,22,23,24,
~C~~ ~~~,E~T CODE
COLUMN 26-80
~
_________ CUSTOMER IDENTIFICATION
- --tDDrD 1100 ActIE
1 III
"E1'!DIU~
II I 1 II
I I III
,./tt·13S217-1'
I 1
0001001000000000000000" 0 0 0 0 0 0 0 0 I 0 0 0 01001000000000000000000000000000'000000000000'
1 Z 3 4 5111 t1111 12IJUI51111111910ZIZZUZ4Z5IU,n"S31J1U:MJljIll1." .. 414Z4UU5414141USO5ISZU54SUl5rSlUII.IlU3141SII"tllI70711Z1314757G1l1I1U.1
11111111111111111111111111111111111111111111111111111111111111111111111111111111
122222222222211 ZZZZZZZZZZ11 11 ZZZZ22 Z212 2 2 Z2 2 2 212 ZZZZ2 2 211 2 2 2 2 Z2 Z2 2 ZZZ2 212 Z112112l .
PERSON RESPONSIBLE FOR REVIEWING SIGNETICS
COMPUTER GENERATED TRUTH TABLE
ATTN.
1 1
J.Q.
ENGIIiEER, MEMORY PROD.
I I I II II
I I I I I I
1
I
I III
II
III
MGR.
I I
I I
II 01111110000 I 0 0 0.000 I 000. DII 0 0 DII 0 0 0 DOD 0 I DID DOD DD0 0 0 0 0 D• D0 0 0 0 0 D0 0 0 0 0 0 0 0 0 leD .1. t
I I J .. I I ' • • • nlllJ .. " .. " .. IUU'IIHluululln.J1lUuuS."II ..... IUO.UU.. , .... SOsIUSUtSSKIlIiHICUIIUJNISlurIlHrlnrUJlUUu,,,,,.
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 212 22 2 2 222222
STREET ADDRESS
CITY
STATE ZIP
SUNNYVALE" CALI FORN I A 94086
I I
II
II II ..
I III
10 1100 II D• DI 0 I. 0 I. 0 0 0 0 e 0 0 Dill 0 DOlO DID. 0 0 0 0• 0 0 0 I 0 0 DOlO 0 0 •••••• 1 0 0 0 • 0 81 0 • 0 ••••••••
1 1, ... 1
r ••• IIIIUI."IIIlIIIU"'anM"lU1Ju•• "JllIJU'.31 ••••14IO.U'.u .. ., .. slsunUSllIlIU•• III1,UUUII, • • rtnruUHIJlU"".
111111111111111111111111111111111111111111111111111 II 1 I 1 1111 1 1 1 11 1 11111111111111
22122222222222222222222222222222222222222222222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22222222222
COMPANY NAME
'.~A~C~ME~M~E~M~OR~I~E~S-I~H~C~.------------------~----------------------------~
I II I I II I II
I I III
0000000100000 DID 0 0 eo 0 0 0 0 ot. 01 0 0 0 000 DDII 0 I 0 000 II 0 D. 00 0 0 ... 11 •••• 00000 ... II .......
1I
J""
I ,.11 1I1J1.IIMIII,IUIlInnl..uu,,,n.JIIUUIJl.n . . . . "Ilq.IfI ••'."'UIUU$UUU11111.IIIUHUU"' .. I"ln'''UUUI1,ptn.
1111111111111111111111111111111111 1 11111111111111111111111111111 1 111 1 1111111 1 1 1 1
2222222222222 21Z 2 ~ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22222222222222222222222222122222222222'
7·156
SILICON GATE MOS. 2580
CODING FORMAT (Cont'd)
DATA CARD FORMAT
Col 1·4
Decimal equivalent of first data word location.
Example: 0124
Note: leading zeros must be used for addresses from 0000 to 0999.
Col 5
Dash (.) to separate numbers
Col '6·9
Address of last data word on card
Col 10
Blank
Col 11·14
Col 15
First data word (04. 03 ' O2 , 0 1)
Blank
Col 16·19
Second data word
Etc. thru column 71
Col 72·80
Reserved for comments (These columns are ignored by the
computer)
Up to twelve (12) data words can be coded on one card. Less than
12 may be used as long as the first and last addresses are given in
columns 1·9.
EXAMPLE
000-0011 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
I
11110110001111011100110101100010110101001001010000011100110001010010000 I
1 2 3 4 5 6 7 8 9 1011.11131415161718191021111324252621282930313233343536 37 38 3140 414243444546474949505152 5H4I5 56 57 58 59 60 616263 6465 66 6168 6910 71 ,,~
1111111111111111111111111111111111111111111111111111111111 Jl11111111111
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2::
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
44444444444444444444444444444444444444444444444444444444444444444444444)
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5,5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
6 6 f; 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6, 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6,. } :
77777777777777777777777777777777777777777777777777777777777777777777777'
8 8 [I B8 B8 B8 8 8 8 B8 88 8 BB8 a BBB8 8 8 B8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 a 8 8 8 8.. / .•.•
9 9 ~I 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 '
1 1 3 4 5 6 7 8
j
1011 121314 IS 16 17 16 19 20212223 24Z5 26 27 28 29 30 31323334353637183940414243444546414849 SO 515253545556515859606162636465666168697011
't;Mf!mlI]
7·157
SI LICON GATE MOS • 2580
TRUTH TABLE WOR KSHEET
Note:
"1" = +5V
"0" = ov
(Copy this form when submitting written truth table)
7·158
S!!II Dolies
FULLY DECODED, 1024·81T
________
ST_AT_IC_RA_ND__O_M_AC_CE_SS_M_EM_OR--IY
ADVANCED SPECIFICATION
2602
2602.1
SILICON GATE MOS 2600 SERIES
DESCRIPTION
PIN CONFIGURATION
The Signetics 2602 is a medium speed, static random access
memory offering a 1024x 1 organization. Fabricated with
low threshold N-Channel silicon gate technology, the 2602
yields an access and read cycle time of less than 1 J1S for the
standard version and 500ns for the -1 version. Write cycle
time is 500ns.
B & I PACKAGES
The 2602 is fully static, requiring no clocks and is completely DTUTTL compatible including the single +5V
power supply requirement.
•
FEATURES
•
1024x1 STATIC OPERATION
•
100% TTL COMPATIBLE
•
LOW ACCESS AND CYCLE TIME: 2602
2602-1
•
LOW POWER DISSIPATION
0.2mW/BIT
•
STANDARD PACKAGE
16-PIN DIP
500n5
2602
• VCC = +5V
• SIGNETICS N-CHANNEL SILICON GATE TECHNOLOGY
• TRI·STATE OUTPUT
APPLICATIONS
PERIPHERAL MEMORIES
BUFFER MEMORIES
MINICOMPUTER MEMORY
1.
BLOCK DIAGRAM
Vee
AO
Address 6
2. Address 5
3.
4.
5.
6.
7.
8.
GND
Read/Write
Address 1
Address 2
Address 3
Address 4
Address 0
16.
15.
14.
13.
12.
11.
10.
9.
Address 7
Address 8
Address 9
Chip Select
Data Out
Data In
VCC
Ground
o-!
Al~
A2~
A3~
A402
DIN
o!..!
R/Wo1-
CisoE
PART IDENTIFICATION
DOUT0.!3
TYPE
A5
AS
A7
AS
A9
PACKAGE
OP. TEMP. RANGE
lJ1s
500ns
0-700 C
0-700 C
16-Pin Ceramic DIP lJ1s
16-Pin Ceramic DIP 500ns
0-700 C
0-700 C
2602B
16-Pin Plastic DIP
2602-1 B 16-Pin Plastic DIP
12602 I
2602-11
TA
7·159
SILICON GATE MOS. 2602/2602-1
MAXIMUM GUARANTEED RATINGS:
o
oOe to +70 e
Operating Ambient Temperature
o
Storage Temperature; All Input,
Output, and Supply Voltages with
respect to VSS
-65°e to +150 e
Package Power Dissipation "8" Pkg.
640mW
"I" Pkg.
800mW
-0.5 V to +12 V
DC AND OPERATING CHARACTERISTICS:
= oOe to +70o e,
TA
Vee
= +5V ±5%, Vss = OV unless otherwise noted.
UNITS
III
500
nA
VIN
ILO
Output Leakage
500
nA
VOUT
VIH
Input High Level Voltage (All Inputs)
2.2
5.25
V
VIL
Input Low Level Voltage (All Inputs)
-0.3
0.65
V
VOL
Output Low Voltage
0
0.4
V
IOL
VOH
Output High Voltage
2.4
VCC
V
IOH
Output Open
MIN
TEST
TYP
CONDITIONS
MAX
Input Leakage
SYMBOL
ICC
Supply Current
35
50
mA
CIN
I nput Capacitance (Any Input)
5
10
pF
COUT
Output Capacitance
5
10
pF
TYP
MAX
= 5.25V
= 5.25V
= 1.6 mA
= -1001LA
AC CHARACTERISTICS:
TA
= oOe to +70o e,
Vee
= +5V ±5%, VSS = OV unless otherwise noted.
SYMBOL
MIN
TEST
UNITS
CONDITIONS
READ CYCLE
tRC
tAC
Read Cycle
2602
1.0
2602-1
0.5
Address to Chip Select Delay 2602
Access Time
ILS
0.4
0.2
ILS
At Minimum
ILS
Read Cycle
2602
1.0
ILS
2602-1
0.5
ILS
2602-1
tA
ILS
WRITE CYCLE
tw
Write Cycle
1ILs
ILS
tAC
Address to Chip Select Delay
ILS
ILS
tWD
Address to Write Pulse Delay
0.05
0.4
twp
Write Pulse Width
0.5
tDW
Data Set-up Time
0.25
ILS
tDH
Data Hold Time
0.1
ILS
tcw
Chip Select Pulse Width
0.3
ns
tcs
Access Time Through Chip Select Input
0.2
IL-S
tCD
Chip Deselect Time
0.2
ILS
tR/WS
Read/~Set-Up Time
ILS
CHIP SELECT AND DESELECT
7-160
0.5
ILS
SI L ICON GATE MOS. 2602/2602-1
TIMING DIAGRAMS
READ CYCLE
WRITE CYCLE
_.--.~tRC ----~a
ADDRESS
__ J1 . . . ._________r
I
::..:J
_
.
I,'.'V;-----t
/11--1- - -
wp
..,....tR/WS,
DATA OUT
_--~tA---_IIo_1
DATA IN
CH~P
SELECT AND DESELECT
"",:y: ------------~~.--------------
~-T-------,~I
r:
DATA OUT
_ _ _ _ _ _-J
I-
L ___ ...J
NO.E: Timing measured from 50% points.
7·161
CUSTOM CODING INFORMATION
COMPANY _______________________________
2410
ADDRESS _______________________________
CITY_____________ STATE ________ ZI P_____
TEL. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
AUTHORIZED SIGNATURE ___________
A2
A.
A,
A5
At
BASIC PRODUCT TYPE _ _ _ _ _ _ _ _ _ _ _ __
DATE ________________~-----------------
B2
A,
B.
CE
VGG
CUSTOMER PRINT OR 1.0. NUMBER _________
PURCHASE ORDER NUMBER ______________
Vss
2410 Series- 1024 bit read-only
memory organized as 256 words
of 4 bits in a 16 pin dip.
2420
. BASIC INFORMATION
0 D
• DEVICE TYPE N24
• NUMBER OF CHIP SELECTS
• CHIP SELECT CODE
• OUTPUT DEVICE
D
D
0
CE3
1
0
0
CE2
3
0
CE1
MOS RESISTOR
TTL (Bare Drain)
• ORGANIZATION
o
0
8 X 128
• PACKAGE
0
D
0
8 X 256 0 4 X 512
4 X 256
16 PIN
D
24 PIN
• LOGIC "1" MORE NEGATIVE VOLTAGE
lOGIC "0" MORE POSITIVE VOLTAGE
• INSTRUCTIONS FOR COMPLETING TRUTH TABLE
(Required only if computer punch cards are not used)
FOR 8 X 256 USE COLUMN I ADDRESS- OUTPUTS
B1-B8
FOR 8 X 128 USE COLUMN I ADDRESS- OUTPUTS
B1-B8
FOR 4 X 256 USE COLUMN I ADDRESS WORDS
0-127, OUTPUTS B1-B4; COLUMN II ADDRESS
WORDS 128-255, OUTPUTS B5-B8
FOR 4 X 512 USE COLUMN I ADDRESS WORDS
0-255, OUTPUTS B1-84; COLUMN III ADDRESS
WORDS 256-511, OUTPUTS B5-B8
ORGANIZATION
The Signetics 2400 Series is a family of read-only memories.
The 2410, 2420, and 2430 Series are offered with the following organizations.
7-162
2420 Series- 1024 bit read-only
memory organized a 128 words
by 8 bits or 256 words by 4 bits
If the 256 words by 40rgimization
is specified outputs will appear on
pins 4, 6, 8, and 10.
2430
CE,
CE,
B,
A.
A5
B,
AS
B.
A,
B5
AS
B6
VGG
B,
Me
Be
CE
2430 Series- 2048 bit read-on~y
memory organized as 256 words by
8 bits or 512 words by 4 bits. If the
512 word by 4 organization is specified outputs will appear on pins 4,
6,8, and 10.
2400 SERIES CUSTOM CODING INFORMATION
ROM SEL.ECTION· CHART
TYPE
ORGANIZATION
PACKAGE
OUTPUTS
CHIP SELECT CONTROLS
N2410I
256 x 4
16-Pin Ceramic DIP
MOS Pull-up
1
N24111
256 x 4
16-Pin Ceramic DIP
Bare Drain
1
N2420Y
128 x 8. 256 x 4
24-Pin Ceramic DIP
MOS Pull-up
1
N2421Y
128 x 8. 256 x 4
24-Pin Ceramic DIP
Bare Drain
1
N2425Y
128 x 8. 256 x 4
24-Pin Ceramic DIP
MOS Pull-up
3 (binary coded) *
N2426Y
128 x 8. 256 x 4
24-Pin Ceramic DIP
Bare Drain
3 (binary coded) *
N2430Y
512 x 4. 256 x 8
24-Pin Ceramic DIP
MOS Pull-up
N2431Y
512x4.256x8
24-Pin Ceramic DIP
Bare Drain
N2435Y
512 x 4. 256 x 8
24-Pin Ceramic DIP
MOS Pull-up
3 (binary coded) *
N2436Y
512x4.256x8
24-Pin Ceramic DIP
Bare Drain
3 (binary coded) *
1
1
'Mask Programmable
CIRCUIT OPTION
The following circuit options are available for the user's
particular needs:
Input definition:
A 1 is the least significant input address
A8 is the most significant input address
OUTPUT BUFFER
For all series the user has the option of MOS or TTL
outputs. This must be specified by the user.
• MOS output- an output having an MOS resistor connected to VOD. This allows interfacing with other
•
MOS devices.
TTL output- an output having no MOS resistor connected to VDD. Commonly called a "bare drain"
output; this allows direct interfacing with TTL
circuits and external "wired AND" capability.
CHIP SELECT
•
•
•
•
"Single" ROM- one which has only one chip select. A
logical "0" on the chip select line places all outputs in
the "1" state (or open-circuited in the case of a"TTL"
output).
"Coded" ROM- one which has a three digit binary code
chip select. This allows paralleling up to eight devices
without external chip select logic thereby allowing the
user to save the cost of extra packages and PC board
space.
2410 Series may only be ordered as a "single" ROM
(one chip select).
2420 and 2430 Series may be ordered as "single" or
"coded" ROM's (one chip select or three chip selects).
DEFINITIONS
Logic definition:
All logic is assumed negative
"0" is the more positive voltage
"1" is the more negative voltage
INPUT FORMAT
Programming information for Signetics' 2400 Series should
be transmitted to Signetics in the form of computer
punched cards accompanied by information on the various
circuit options desired.
Upon receipt of each deck
and the circuit option desired for that deck a computer generated truth table will be made and a copy of this truth
table returned to the customer. This minimizes the possibility of error and allows the best possible delivery (normally 4 weeks after receipt of card deck).
Upon receipt of the computer generated truth table check
it carefully and if any errors are discovered notify Signetics
immediately.
The Signetics' 2400 Series Read-Only Memory can be programmed so that for any binary input A 1 through A8 the
outputs B 1 through B8 are uniquely determined. Each
deck of cards sent to Signetics must contain a card describing the options desired (card 1), the unique outputs for
each word in memory (cards 2 through 129 or 257, depending on organization), and cards specifying the address
to which the computer generated truth table should be
sent. Cards should be punched according to the format on
the following pages.
If it is not feasible to use computer punched cards, the user
should describe the circuit option desired and complete
the truth table. Upon receipt of pages Signetics will punch
the Gomputer cards and return a copy of the computer
generated truth table, (the user can real ize a substantial
savings associated with the coding charge by using computer cards).
7·163
2400 SERIES CUSTOM CODING INFORMATION
CARD 1
CARDS 2 THROUGH 257
(4 X 512 Organization only)
COLUMN
DATA
1-8
Starting at column 1- punch "coded" or
"single"
9-11 *
If "coded", punch the binary code chip
select (i.e., 101), if "single" leave blank
12
13-17
Leave blank
Each card specifies the output of two 4-bit
columns 1 through 8.
words in
The decimal equivalent of the bi-
nary coded input address is punched in columns 78. 79,
and 80.
Punch the ROM organization desired (i.e.,
COLUMN
DATA
8 X 256, 4 X 512), etc.
1-4
Punch output for words 0-255
Punch output for words 256-511
18
Leave blank
5-8
19-21
Punch MOS for an MOS output. Punch TTL
9-77
Leave blank
for a TTL output (bare drain)
78-8
Punch decimal equivalent of binary coded
22-27
Leave blank (For CM No.)
input address of the word corresponding to
28-33
Punch the basic device type desired (i.e.,
the outputs punched in Columns 1-4
34-80
Comments punched here will appear as the
Column 78- Hundreds Digit
title on the truth table. This should include
Column 79- Tens Digit
customer part identification
Column 80- Units Digit
N2410 I, N2420Y), etc.
*CE3, CE2 and CE 1 respectively
CARD 2 THROUGH 129 (8 X 128 Organization)
2 THROUGH 257 (8 X 256 Organization)
Each card specifies the output of one
8-bit
CARDS 2 THROUGH 129
(4 X 256 Organization only)
word in
columns 1 through 8. The decimal equivalent of the binary
Each card specifies the output of two 4-bit
coded input address for that word is punched in columns
columns 1 through 8. The decimal equivalent of the binary
words in
78, 79, and 80.
coded input address is punched in columns 78, 79, and 80.
COLUMN
DATA
COLUMN
DATA
1-8
Punch outputs 81 through 88 in columns
1-4
Punch output for words 0-127
Punch output for words 128-255
one through eight respectively
5-8
9-77
Leave blank
9-77
Leave blank
78-80
Punch decimal equivalent of binary coded
78-80
Punch decimal equivalent of binary coded
7-164
input address which corresponds to the
input address corresponding to the outputs
outputs punched in Columns 1-8
punched in Columns 1-4
Column 78- Hundreds Digit
Column 78-Hundreds Digit
Column 79- Tens Digit
Column 79- Tens Digit
Column 80- Units Digit
Column 80- Units Digit
2400 SERIES CUSTOM CODING INFORMATION
EXAMPLE CARDS:
ADDRESS CARDS
AT'I'N: THE PERSON'S NAME WHO WILL REVIEW THE TRUTH TABLE
I
I
II I
I I I
STATE
I I
C
I
I II
II
I II I
ZIP CODE
I II
I
STREET ADDRESS
I
II III I
C YOUR COMPANY'S NAME
I
I
I I
I
III I
I I
I I
00101000000001 0100000000000000000000000000000000000000OOoooooonOOOOOOOOOOOOOOOOO
, r3
• S , I I I "" '213141~ il °1 Illtl91I.I: ,'liIS 2521 ztH lOJI 123330DI1I II 394b II 424HUSfl.,.14hOI 1 nSHHS IUHtsHUII IZ;!~li;"6"U"O" 12 I! lOS Ii " " II.
111111111111111' 1111' I ""
I.,' 1 " " " " ' "
1"'" 1"""'"
I""""'" j-", 1111111
CARD 1
CODED 101 8X256 TTL
N2436Y SIGNETICS HAS THE FASTEST R.O.M.'.
II I II II
I III
II II I
I I I
I I I
I
I
I
I
88000000010001000011000000000001101000010010001010000011011000000001100008810001
I ! I ' \ S I I I II" ;/llte /111" /1/11021 II 111HH521 212111 3' J2333USKJI1I1UUI U.UUHUI.~usa51 SUJMSS5ISllIst . . . .UJlUS." .... "" "'UO"""I".
1111111 '11111' 1'1" '11' 111' 1" 111'" 11' 1" l' 11111' 1" 11111111' 1111111' 1111111111
The above specifies a "coded" ROM with the binary coded
chip select "101" organized 8 X 256 with TTL outputs
(bare drain). The basic device type is a N2436Y ("Y" in-
dicates a 24-pin ceramic DIP.
range: -25°C- +70°C).
N indicates temperature
CARDS 2·129 AND CARDS 2·257
?01111111
~01010101
~10101010
11100100
801.1011100000000000000000000000000000000000000000000000000000000000000000000111
1 I J • 5 , , I t i l " 1113141, II 1I111t2l11121ltU5~hl2lItll31323JIHSlI31 lilt •• ' .1.UUS4.. ,q(ISlSI5253.4Si5l5HHUOII lzeUUH,.,'Ullln IHUH"'" lilt.
111111111111111111111111' l' 1111111111111111111111111111111' 111111111111111111111
•
Outputs 8 1 through 88 are in columns 1 through 8
respectively
• Decimal equivalent of binary coded input address is in
columns 78, 79, and 80
• For 8 X 128 and 8 X 256 organizations- outputs are 81
through 88 respectively
• For 4 X 512 organization:
Data card
Data card
a
10
Word 000 outputs 81 through 84
respectively
Word 256 outputs 85 through 88
respectively
Word 010 outputs 81 through 84
•
respectively
Word 266 outputs 85 through 88
respectively
For 4 X 256 Organization:
Data card
a
Data card 10
Word 000
respectively
Word 128
respectively
Word 010
respectively
Word 138
respectively
outputs 81 through 84
outputs 85 through 88
outputs 81 through 84
outputs 85 through 88
7·165
2400 SERIES CUSTOM CODING INFORMATION
-
-
ADDRESS
INPUT GATE
DECIMAL
AODRESS
I
II
III
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
000
128
256
005
133
261
006
134
262
1 1
007
135
263
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
008
136
264
A8 A7 A6 A5 A4 A3 A2 A1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
'0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
7-166
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
a
a
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUTPUT DATA
1
001
129
257
002
130
258
003
131
259
004
132
260
009
137
265
010
138
266
011
139
140
267
013
141
269
014
142
270
1 1
015
143
271
a a a a
a a a 1
a (;) 1 a
a a 1 1
a 1 a a
a 1 a 1
a 1 1 a
a 1 1 1
1 a a a
1 a a 1
1 a 1 a
1 a 1 1
1 1 a a
1 1 a 1
1 1 1 a
016
144
272
017
145
273
018
146
274
275
1
1
1
1
1
1
1 1
1 1 1
a
a
a
a
a
1 1
a a a
a a 1
a 1 a
a 1 1
1 a a
012
268
019
147
020
021
148
276
149
277
022
150
278
023
151
279
024
152
280
025
026
153
154
281
027
155
028
156
157
283
284
029
282
285
030
031
158
286
159
287
032
160
288
033
161
289
034
162
163
290
291
164
292
035
036
B1
B2
B3
B4
B5
B6
B7
B8
USER'S
CHARACTER
2400 SERIES CUSTOM CODING INFORMATION
ADDRESS
INPUT GATE
!
DECIMAL
ADDRESS
I
II
III
0
0
1
0
0
1
0
1
037
165
293
0
0
1
0
0
1
1
0
038
166
294
0
0
1
0
0
1
1
1
039
167
295
0
0
1
0
1
0
0
0
040
168
296
0
0
1
0
1, 0
0
1
041
169
297
0
0, 1
0
1
1
0
042
170
298
A8 A7 A6 AS A4 A3 A2 A 1
OUTPUT DATA
81
82
83
84
85
86
87
88
USER'S
CHARACTER
---
---
0
-----
0
0
1
0
1
0
1
1
043
171
299
0
0
1
0
1
1
0
0
044
172
300
0
0
1
0
1
1
0
1
045
173
301
0
0
1
0
1
1
1
0
046
174
302
0
0
1
0
1
1
1
1
047
175
303
0
0
1
1
0
0
0
0
048
176
304
0
0
1
1
0
0
0
1
049
177
305
0
0
1
1
0
0
1
0
050
178
306
0
0
1
1
0
0
1
1
051
179
307
0
0
1
1
0
1
0
0
052
180
308
0
0
1
1
0
1
0
1
053
181
309
0
0
1
1
0
1
1
0
054
182
310
0
0
1
1
0
1
1
1
055
183
311
0
0
1
1
1
0
0
0
056
184
312
0
0
1
1
1
0
0
1
057
185
313
0
0
1
1
1
0
1
0
058
186
314
0
0
1
1
1
0
1
1
059
187
315
0 '0
1
1
1
1
0
0
060
188
316
0
0
1
1
1
1
0
1
061
189
317
0
0
1
1
1
1
1
0
062
190
318
0
0
1
1
1
1
1
1
063
191
319
0
1
0
0
0
0
0
0
064
192
320
0
1
0
0
0
0
0
1
065
193
321
0
1
0
0
0
0
1
0
066
194
322
0
1
0
0
0
0
1
1
067
195
323
0
1
0
0
0
1
0
0
068
196
324
0
1
0
0
0
1
0
1
069
197
325
0
1
0
0
0
1
1
0
070
198
326
0
1
0
0
0
1
1
1
071
199
327
0
1
0
0
1
0
0
0
072
200
328
0
1
0
0
1
0
0
1
073
201
329
---'--
~--
1--------
----
--
--
---
---
--
------
--- - ---------
I
--- -----------
---------- -----
--'"-
--
----
--
7-167
2400 SERIES CUSTOM CODING INFORMATION
DECIMAL
ADDRESS
ADDRESS
INPUT GATE
A8 A7 A6 A5 A4 A3 A2 A1
I
II
III
0
1
0
0
1
0
1
0
074
202
330
0
1
0
0
1
0
1
1
075
203
331
0
1
0
0
1
1
0
0
076
204
332
0
1
0
0
1
1
0
1
077
205
333
0
1
0
0
1
1
1
0
078
206
334
0
1
0
0
1
1
1
1
079
207
335
0
1
0
1
0
0
0
0
080
208
336
0
1
0
1
0
0
0
1
081
209
337
0
1
0
1
0
0
1
0
082
210
338
0
1
0
1
0
0
1
1
083
211
339
0
1
0
1
0
1
0
0
084
212
340
0
1
0
1
0
1
0
1
085
213
341
0
1
0
1
0
1
1
0
086
214
342
0
1
0
1
0
1
1
1
087
215
343
0
1
0
1
1
0
0
0
088
216
344
0
1
0
1
1
0
0
1
089
217
345
0
1
0
1
1
0
1
0
090
218
346
0
1
0
1
1
0
1
1
091
219
347
0
1
0
1
1
1
0
0
092
220
348
0
1
0
1
1
1
0
1
093
221
349
0
1
0
1
1
1
1
0
094
222
350
0
1
0
1
1
1
1
1
095
223
351
0
1
1
0
0
0
0
0
096
224
352
0
1
1
0
0
0
0
1
097
225
353
0
1
1
0
0
0
1
0
098
226
354
0
1
1
0
0
0
1
1
099
227
355
0
1
1
0
0
1
0
0
100
228
356
0
1
1
0
0
1
0
1
101
229
357
0
1
1
0
0
1
1
0
102
230
358
0
1
1
0
0
1
1
1
103
231
359
0
1
1
0
1
0
0
0
104
232
360
0
1
1
0
1
0
0
1
105
233
361
0
1
1
0
1
0
1
0
106
234
362
0
1
1
0
1
0
1
1
107
235
363
0
1
1
0
1
1
0
0
108
236
364
0
1
1
0
1
1
0
1
109
237
365
0
1
1
0
1
1
1
0
110
238
366
7·168
OUTPUT DATA
B1
B2
B3
B4
B5
B6
B7
B8
USER'S
CHAR·
ACTER
-
2400 SERIES CUSTOM CODING INFORMATION
DECIMAL
ADDRESS
ADDRESS
INPUT GATE
A8 A7 A6 A5 A4 A3 A2 A 1
I
II
III
0
1
1
0
1
1
1
1
111
239
367
0
1
1
1
0
0
0
0
112
240
368
0
1
1
1
0
0
0
1
113
241
369
OUTPUT DATA
81
82
83
84
85
86
87
88
USER'S
CHARACTER
--
0
1
1
1
0
0
1
0
114
242
370
0
1
1
1
0
0
1
1
115
243
371
--------
~~--
0
1
1
1
0
1
0
0
116
244
372
0
1
1
1
0
1
0
1
117
245
373
0
1
1
1
0
1
1
0
118
246
374
0
1
1
1
0
1
1
1
119
247
375
-
.. -
--
---
-----------
---
------
0
1
1
1
1
0
0
0
120
248
376
0
1
1
1
1
0
0
1
121
249
377
0
1
1
1
1
0
1
0
122
250
378
0
1
1
1
1
0
1
1
123
251
379
--
--
-- - ---------
-_._.----
-
-
------
.._--
--~--
---
0
1
1
1
1
1
0
0
124
252
380
0
1
1
1
1
1
0
1
125
253
381
0
1
1
1
1
1
1
0
126
254
382
0
1
1
1
1
1
1
1
127
255
383
1
0
0
0
0
0
0
0
128
384
1
0
0
0
0
0
0
1
129
385
1
0
0
0
0
0
1
0
130
386
1
0
0
0
0
0
1
1
131
387
1
0
0
0
0
1
0
0
132
388
1
0
0
0
0
1
0
1
133
389
1
0
0
0
0
1
1
0
134
390
1
0
0
0
0
1
1
1
135
391
1
0
0
0
1
0
0
0
136
392
1
137
393
394
-------
---- ----------
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
138
1
0
0
0
1
0
1
1
139
395
1
0
0
0
1
1
0
0
140
396
1
0
0
0
1
1
0
1
141
397
1
0
0
0
1
1
1
0
142
398
1
0
0
0
1
1
1
1
143
399
1
0
0
1
0
0
0
0
144
400
1
0
0
1
0
0
0
1
145
401
1
0
0
1
0
0
1
0
146
402
1
0
0
1
0
0
1
1
147
403
\
---
-----
---1-------
------------
--
7-169
I
2400 SERIES CUSTOM CODING INFORMATION
ADDRESS
'INPUT GATE
DECIMAL
.ADDRESS
A8 A7 A6 A5 A4 A3 A2 A1
I
II
III
1
0
0
1
0
1
0
0
148
404
1
0
0
1
0
1
0
1
149
405
1
0
0
1
0
1
1
0
150
406
1
0
0
1
0
1
1
1
151
407
1
0
0
1
1
0
0
0
152
408
1
0
0
1
1
0
0
1
153
409
1
0
0
1
1
0
1 -0
154
410
1
0
0
1
1
0
1
1
155
411
1
0
0
1
1
1
0
0
156
412
1
0
0
1
1
1
0
1
157
413
1
0
0
1
1
1
1
0
158
414
1
0
0
1
1
1
1
1
159
415
1
0
1
0
0
0
0
0
160
416
1
0
1
0
0
0
0
1
161
417
1
0
1
0
0
0
1
0
162
418
1
0
1
0
0
0
1
1
163
419
1
0
1
0
0
1
0
0
164
420
1
0
1
0
0
1
0
1
165
421
1
0
1
0
0
1
1
0
166
422
1
0
1
0
0
1
1
1
167
423
1
0
1
0
1
0
0
0
168
424
1
0
1
0
1
0
0
1
169
425
1
0
1
0
1
0
1
0
170
426
1
0
1
0
1
0
1
1
171
427
1
0
1
0
1
1
0
0
172
428
1
0
1
0
1
1
0
1
173
429
1
0
1
0
1
1
1
0
174
430
1
0
1
1
1
1
1
1
175
431
1
0
1
1
0
0
0
0
176
432
1
0
1
1
0
0
0
1
177
433
1
0
1
1
0
0
1
0
178
434
1
0
1
1 .0
0
1
1
179
435
1
0
1
1
0
1
0
0
180
436
1
0
1
1
0
1
0
1
181
437
1
0
1
1
0
1
1
0
182
438
1
0
1
.1
0
1
1
1
183
439
1
0
1
1
1
0
0
0
184
440
OUTPUT DATA
81
82
83
84
85
86
87
88
USER'S
CHARACTER
--
--
----- f - - - - - - -
--
--
--
--
2400 SERIES CUSTOM CODING INFORMATION
ADDRESS
INPUT GATE
DECIMAL
ADDRESS
A8 A7 A6 A5 A4 A3 A2 A1
I
II
USER'S
CHARACTER
OUTPUT DATA
III
1
0
1
1
1
0
0
1
185
441
1
0
1
1
1
0
1
0
186
442
81
82
83
84
85
87
86
88
----.
--l------- -
1
0
1
1
1
0
1
1
187
443
1
0
1
1
1
1
0
0
188
444
1
0
1
1
1
1
0
1
189
445
1
0
1
1
1
1
1
0
190
446
1
0
1
1
1
1
1
1
191
447
1
1
0
0
0
0
0
0
192
448
-~--
..
---
---
---
-
1
1
0
0
0
0
0
1
193
449
1
1
0
0
0
0
1
0
194
450
1
1
0
0
0
0
1
1
195
451
1
1
0
0
0
1
0
0
196
452
1
1
0
0
0
1
0
1
197
453
1
1
0
0
0
1
1
0
198
454
-f-
---
--
---
----
--~---
.----- ---
---_.
---
-
--
--
-
----
--- r
--
---t--
--
--~--.
-
---
----
--
--f--.
1
1
0
0
0
1
1
1
199
455
1
1
0
0
1
0
0
0
200
456
1
1
0
0
1
0
0
1
201
457
1
1 0
0
1
0
1
0
202
458
1
1
0
0
1
0
1
1
203
459
1
1
0
0
1
1
0
0
204
460
1
1
0
0
1
1
0
1
205
461
1
1
0
0' 1
1
1
0
206
462
1
1
0
0
1
1
1
1
207
463
1
1
0
1
0
0
0
0
208
464
1
1
0
1
0
0
0
1
209
465
1
1
0
1
0
0
1
0
210
466
1
1
0
1
0
0
1
1
211
467
1
1
0
1
0
1
0
0
212
468
1
1
0
1
0
1
0
1
213
469
1
1
0
1
0
1
1
0
214
470
1
1
0
1
0
1
1
1
215
471
1
1
0
1
1
0
0
0
216
472
1
1
0
1
1
0
0
1
217
473
1
1
0
1
1
0
1
0
218
474
1
1
0
1
1
0
1
1
219
475
1
1
0
1
1
1
0
0
220
476
1
1
0
1
1
1
0
1
221
477
-- r-- -----
-- -----
- - f-----
1---
-----
-
--- r------- 1------- ---
--
-- f------- - 1--
__
-
r
--
- - t--------- -
--
- f------
-----
--
------------
-
-_.- 1-------
-
-~-----
----"---
w _ _ • __
--
--
-
----
--- I---- ---------- --
----_._- 1-------
------------ - -
-- 1 - - - - - - -
-
---
-
---------
_.. -
-------- 1--------
--
---.-- t---------
-
---"--------"---
----
-
--------
-- 1---------- r- ---- -
-------------
-----~-
------"--
7-171
2400 SERIES CUSTOM CODING INFORMATION
DECIMAL
ADDRESS
ADDRESS
INPUT GATE
A8 A7 A6 AS A4 A3 A2 A 1
I
II
III
1 0 1 1 1
1 1 0 1 1 1
1 0
222
478
1
1
223
479
1
1
1 0 0 0
0 0
224
480
1
1
1
0 0 0
0 1
225
481
1 1
1
0 0 0
~
0
226
482
1 1
1
1 1
227
483
0 0
228
484
1
OUTPUT DATA
B1
B2
B3
B4
B5
B7
B6
B8
USER'S
CHARACTER
--~-----
1
0 0 0
1 1 0 0 1
1 1
0
1
229
485
1
1 0
230
486
1
1
231
487
1
1 0 0 1
1 1 0 0 1
1 1 0 0 1
1 1 0 _1 0
0 0
232
488
1
1
1
0
1
0
0
1
233
489
1
1
1
0
1
0
1 0
234
490
1
1
1
0
1
0
1 1
235
491
1
1
1
0
1
1
0 0
236
492
1
1
1 0
1 1
0
1
237
493
1
1
1
0 1 1
1
0
238
494
1
- - - - - - ------
--
----t-----
~-~--
--f-----f----------
t----- - - - - - - - -~
- - - - I----~
--- -~--
--
-----~---
---~-
--
--------
---------- t-------- - - - - - - --~
1
1 1
0
1 1
1 1
239
495
1
1 1
1
0 0
0 0
240
496
1
1
1
241
497
1
1 1
1 0 0
1 0
242
498
1
1
1
1 0 0
1
1
243
499
1
1
1
1 0
1
0 0
244
500
1
1
1
0
1
0
245
501
f----~--
1--------
---
---
--~--
--r---~-
--~--
--
f--
1 1 0 0
'--
--
1
0
r---
1
---- - - r-----~--
---
1 1
1 1 0
1
1 0
246
502
1
1
1
0
1
1
1
247
503
1
1
1 1
1 0
0
0
248
504
1
--
--
1
1
1
1
1
0
0
1
249
505
1
1
1
1
1
0
1 0
250
506
1
1
1
251
507
1 1
1 1 1 0
1 1 1 1
1
252
253
508
1 1
0 0
0 1
1
1
1 1
1 1
1
0
254
510
1
1
1 1
1 1
1
1
255
511
4'72
I---~ r-----~--
1 1 1
1
----
509
--
2513 STATIC CHARACTER GENERATOR. CUSTOM CODING INFORMATION
COMPANY ______________________________
CHARACTER FORMAT
ADDRESS
,_________ STATE _____ ZIP _ _
CITY.
TELEPHONE ____________________________
AUTHORIZED SIGNATURE ______________
DATE ________________________________
ROW ADDRESS
ROW ADDRESS
A3
A2 A1
CUSTOMER PRINT OR ID NO. _ _ _ _ _ _ _ ___
0
0
0
0
0
0
0
PURC'HASE ORDER NUMBER _______________
0
0
1
0
1
1
1
0
DEVICE TYPE _______ 2513,____________
0
1
0
~1~
0
0
0
,..:"'!
~
0
1
1
~1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
0
1
CUSTOM PATTERN NUMBER (TO BE ENTERED BY
SIGNETICS) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
0
...
1
1
0
(1)
0
0
0
1
1
1
1
0
1
"'1
1
0
EXAMPLE 'S'
INTRODUCTION
The Signetics 2513 is a high speed silicon gate MOS
2560-Bit read-only memory whose organization is specially
suited for 64 X 8 X 5 raster scan character generation.
FIGURE 1
CHARACTER ADDRESS
COLUMN ADDRESS
MAJOR FEATURES OF THE 2513
•
•
•
•
•
•
•
ACCESS TIME 450n5 TYPICALLY
STATIC OPERATION
TTL/DTL COMPATIBLE
TRI-STATE OUTPUTS (HIGH-LOW-DISCONNECTED)
FOR POWERFUL BUSSING CAPABILITY
+5, -5, -12V POWER SUPPLIES
24-PIN SIGNETICS SILICONE DIP
SIGNETICS SILICON GATE PROCESS TECHNOLOGY
FOR PERFORMANCE AND RELIABILITY
FIGURE 2
ORGANIZATION AS READ-ONLY MEMORY
For a straight 512 X 5 read-only memory, the five outputs
will display anyone of 512 5-bit stored words corresponding to a 9-bit address applied to A1 through Ag.
ORGANIZATION AS
CHARACTER GENERATOR
A six-bit binary address (A4 through Ag) selects 1-of-64
matrix characters arranged 5 dots horizontally and 8 dots
vertically. A three bit binary address code (A1 through A3)
selects 1 of 8 rows. Five outputs display a complete row of
the character matrix. See Figure 1. The devices may also be
used in pairs to provide 9 X 7 and 10 X 8 vertical scan
formats.
STANDARD PATTERN
A standard ASCII character font is available for the 2513.
This device (2513NX/CM2140) may be used for ASCII
character generation or for device evaluation.
7-173
2513 CUSTOM CODING INFORMATION
PIN CONFIGURATION (Top View)
CUSTOM DEVICES
For unique custom memory patterns, this form should be
used to transmit coding instructions. The nomenclature for
a custom device will consist of the basic product type
followed by a unique CM number assigned by Signetics. For
example, "2513NX/CM2141"
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
VGG
NC
NC
Out 1
Out 2
Out 3
Out 4
Out 5
NC
NC
Chip Enable
VOO
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
NC
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
NC
VCC
•
PROGRAMMING WITH PUNCHED CARDS
For maximum accuracy and minimum cost and turnaround time, the truth table should be transmitted to
Signetics in the form of punched cards according to
the format indicated on the following pages.
•
PROGRAMMING WITH WRITTEN TRUTH TABLE
When punched data cards cannot be suppl ied, the truth
table may be transmitted in written form using the
attached blank truth table.
VERIFICATION
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
1'1.
VGG
NC
NC
Out 1
Out 2
Out 3
Out 4
Out 5
NC
Chip Enable
V
OO2
12. VOO
7-174
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
NC
Address
Address
Address
Address
Address
Address
Address
Address
Address
NC
VCC
1
2
3
4
5
6
7
8
9
Upon receipt of either punched card or written truth table
information, Signetics will prepare a computer tabulation of
the instructions and return to the address indicated. If errors
are detected, they should be transmitted to Signetics as
quickly as possible.
LOGIC CONVENTION
Logic" 1"s or blackened squares in the truth table will result
in "high" output from the indicated output terminal (i.e.
3.2V m!nimum). Similarly, a "1" address input level
is interpreted as 3.2V minimum.
2513 CUSTOM CODING INFORMATION
IDENTIF~CATION
CARDS
LEAVE COLS. 22,23,24,25 BLANK
FOR ASSIGNMENT OF CM NO. BY SIGNETICS
INDICATES "COMMENT" CARD
. CUSTOMER PIN IDENTIFICATION
ACME MEMORIES P/N 135216-1
I
II I I II
I I III
I I
I
I
OOIUJlOIOOIOOOOOOIIOOOOOOOOOOOOOOOOOOOIOOIOOOOOOOOOOOOO0000000000000000000100001
Irl(~~"'~""U"~U"qqnnDUUftHnnn.~u»MH.n •• ~~uu~U~UUUW"""~~MUH"M~"""~""""Q"nnunnnnQ.
I 1111111111111111111111111111111111111111111111111 1'111111111 1111 111111111111111
22122222221212222222222222222222222222122222222122i222 222222t2222222222222222222
PERSON RESPONSIBLE FOR REVIEWING SIGNETICS
COMPUTER GENERATED TRUTH TABLE
ATTN. J.Q. ENGINEER, MEMORY PROD.
I I
I
I I
I II II
MGR.
I
II I I
I III III
I I
I I I
I I I
OOOIIOOOOOOOOOOOOGOOOIOOOOOOIOOOOOOOOOOOOOOOOOOOOOOOOO0000000000000000000080'0.'
IrJ4SI7'1~""""~U"qq~nDUUftnUnn •• unMH.n •• ~~uu~U.U~U~"H"M~HUH""~"""u""""nnn"unnnnQ.
11111111111111111111111111111111111111111111111111111111111111111111111111111111
.22222222222222222222222222222222222222222222222222222222222222222222222222~22222
STREET ADDRESS
8000 ELECTRONICS LANE
I II
II I I
I III
I I
I
00011100000100000100000000000000000000000000000000000000000000000000000000000 •••
IrI4sI71.q""U"~U"""nnDHUHnnnn~~u»MH.n •• ~~uu~U~U~UW"""M~MUWW.~"""H."."Q"nnunQnQ".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222222222222212222222222222222222222222222222}222222222222222222222222222222
CITY
STATE
ZIP
SUNNYVALE, CALIrORNIA 94086
I I II II
II
II
I
I III
00110011000100000000000000100000000000000000000000000000000000000000000000000000
IrI4SI71'~""""~""""nnDHUHnnnD.~U»MH.n •• ~~uu~U~UUUW"H»M~MUW".~a""""""QQnn~unnnnQ.
11111111111111111111111111111111111111111111111111111111111111111111111111111111
22122222222222222222222222222222222222222222222222222222222222222222222222222222
COMPANY NAME
. ACME MEMORIES INC.
I
II III
I I III
I
00000000000000100000000000000000000000000000000000000000000000000000000000000000
I 11451'1."""""~""""nnUHUHnnnD.~»»MH.n •• u~uu~U~U~UH"H~M~HUH""~a"U""u""nnnnun""nn.
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2 22 22 22222 222 212 222 22222222 22 222 22 2222 222222 2222 2222 2222 22222 222 222H 2 2222 22ZZ2Z
7-175
2513 CUSTOM CODING INFORMATION
DATA CARDS
CHARACTER NUMBER
(DATA CARD NUMBER)
OUTPUTS 05 THROUGH 01 RESPECTIVELY
0000 01110 10001 00001 00010 00100 00000 00100
11111010001001110011110011101011011011111011011000000000000000000000000000000100
lIJ4""'M"U""~K»K"n~UUUnKnHH.~»»~».U.H_~UU«U"U"U~~U»~»HUU"~~n~«n"u""n"nn~nn"nn.
1 111 11111111111111111111111111 11111 111 111 1 1 111 1 1 1 I I I I I I I I I I I I I 1 I I I I I I I I I I I I 1 I 1 I I
2 2 2 2 2 2 2 2 22 2 2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 i 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3. 3 3 3 3 3 3 3 3 3 3
44444444444444444444444444444444444444444444444444444444444444444444444444444441
5555555555555555555555555.5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 555
66666&666666666J666666666666666611111'&6&666665666666666666666666666666666666616
7 77 77 1 7 7 7 7 7 77 7 7 71 7 77 7 7 7 7 7 7 7 7 7 7 77 7 17 7 7 77 7 7 77 7 7 7 7 77 7 7 77 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1 7 7 7 1 7 7 7
ROW ADDRESS.
\
\
000
001
\
\
010
011
\
100
\
101
\
110
\
111
10000 01110 10001 10111 10101 10111 10000 01110
001l
11111010001001110001000001010001000001111010001000000000000000000000000000000110
lZ1451"IK"U""nK»K"H~nnUHHnHH~~»»M».» •• "~UU«U"U"U~~U»~»HUU"~~n~«n"N""~nnn~nn"n"M
111111111111111111111111111111111111111111111111111111111IIII I II 111 I 11 I II I II II II
22222222222222222222222222222222222222222222222222222222227722222222222222222222
33333333333333333333333333333333 3 3 3 3 33333333333333333333333333333333 3 3 3 3 3 3 333 333
44444444444444444444444444444444444444444444444444444 44444444444444444444"4 4 44 44 4
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5S 5 5 5 5
6666 ti 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 66 66 6 6 '6 &&, 1 ,& 6 6 6 6666666666666666666666666666666666 6 6 6 6
7 7 7 7 7 7 7 7 7 7 7 1·7 7 7 7 1 7 7 7 7 1 7 7 1 7 1 7 7 7 1 7 111111 7 7 7 7 7 7 7 7 7 7 7 7 7 1 7 7 7 7 7 7 7 7 7 11 7 1 7 7 111111 7 7 11 7 7 1
BASIC DEVICE TYPE
lEAVE COlS. 10,11,12,13 BLANK FOR ASSIGNMENT OF CM NO. BY SIGNETICS
I
00000110000000000000000000000000000000000000000000000000000000000000000000000000
lIJ451"'M"U""nK»K"H~nUUHHnHH.~»»MH.» ••• ~UU«U"U"U~~U»~»MUU"~~n~«n"u""~"nn~nn"n".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
It 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
33313331333333333333333333333333333333333333333333333333333333333333333333333333
4 4 4 4 4 4 4 414 4 4 4 4 4 4 4444444444444444444444444444444444444444444444444444 4 4 4 4 4 4 4 4 4 4 4 4
515 515 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 S5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
66666666666666666666666666666666&&&&&6666666666666666666666666666666666666666666
17177171771711711111111777711171177171171711117177 717 7171717 7 7 77 717 7 71117 7771717
NOTE:
"Character" number is in columns
of coding .
. 176
~8,
79, and 80. Note that each group of eight 5-bit words Is treatad as a character for convenience
2513 CUSTOM CODING INFORMATION
..1m
ADDRESS
AB ABA7 AlAS A4A3 A2A1
ia:
~§
OUTPUT DATA
05 04, 03 02
01
ADDRESS
..1m
ABABA7 A6ASA4A3A2A1
28
oce
{/Jei
ffi~
!u
ia:
0
0
0
0
0
0
0
0
0
000
0
0
0
1
0
0
0
0
0
032
0
0
0
0
0
0
0
0
1
001
0
0
0
1
0
0
0
0
1
033
0
0
0
0
0
0
0
1
0
002
0 0
0
1
0
0
o
1 0
034
o
0
0
0
0
0
0
1
1
003
0
0
0
1
0
0
0
1
1
035
0
0
0
0
0
0
1
0
0
004
0
0
0
1
0
0
1 0
0
036
0
0
0
0
0
0
1
o
1
005
0
0
0
1
0
0
1
o
1
037
0
0
0
0
0
0
1
1
0
006
0
o
0
1
0
0
1
1
0
038
0
0
0
0
0
0
1
1
1
007
0
0
0
1
0
0
1
1
1
039
o
0
0
0
0
1
0
0
0
008
0
0
0
1
0
1
0
0
0
040
0
Q
0
0
0
1
0
0
1
009
0
0
0
1
0
1
0
0
1
041
0
0
0
0
0
1
0
1
0
010
0
0
0
1
0
1
0
1
0
042
0
0
0
0
0
1
0
1
1
011
0
0
0
1
0
1
0
1
1
043
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
1 0
0
044
0
0
0
0
1
1
0
,
012
0
013
0
0
0
1
0
1
1
0
1
046
0
0
0
0
0
1
1
1
0
014
0
0
0
1
0
1
1
1
0
046
0
0
0
0
0
1
1
1
1
015
0
0
0
1
0
1
1
1
1
047
0
0
0
0
1
0
0
0
0
016
0
0
0
1
1
0
0
0
0
048
0
0
0
0
1
0
0
0
1
017
0
0
0
1
1
0
0
0
1
049
0
0
0
0
1
0
0
1
0
018
0
0
0
1
1
0
0
1
0
060
0
0
0
0
1
0
0
1
1
01~
0
0
0
1
1
0
0
1
1
051
0
0
0
0
1
0
1
0
0
020
0
0
0
1
1
0
1
0
0
052
0
0
0
0
1
0
1
0
1
021
0
0
0
1
1
0
1 0
1
063
0
0
0
0
1
0
1
1
0
022
0
0
0
1
1
1
1
0
054
0
0
0
1
0
1
1
1
023
0
0
0
1
,.
0
0
0
1
1
1
066
0
0
0
0
1
1
0
0
0
024
0
0
0
1
1
1
0
0
0
056
0
0
1
026
0
0
0
1
1
1
0
0
1
067
026
0 0
0
1
1
1
0
1
0
068
o
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
1
027
0
0
0
1
1
1
0
1
1
059
0
0
0
0
1
1
1
0
0
028
0
0
0
1
1
1
1
0
0
060
0
0
0
0
1
1
1
0
1
029
0
0
0
1
1
1
1
0
1
061
0
0
0
0
1
1
1
1
0
030
0
0
0
1
1
1
1
1 0
062
031
0
0
0
1
1
1
1
1
063
0
0
0
0
1
1
1
1
1
0
1
1
OUTPUT DATA
05
04 03 02 01,
a: a:
{/J.
!g
7-177
2513 CUSTOM CODING INFORMATION
-II
ADDRESS
ABABA7 ABA6A4A3A2A1
~:;!
~8
COO(
OUTPUT DATA
a: a:
woo(
05 04 03 02
01
!!l5
0
0
0
064
0
0
1
1
0
0
0
0
1
0
0
0
0
0
1
065
0
0
1
1
0
0
066
0
0
1
1
0
0
0
097
0
098
0
0
0
1
1
0
0
0
0
0
0
0
1
096
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
067
0
0
1
1
0
0
0
1
1
099
1
000
1
0
0
068
0
0
1
1
0
0
1
0
0
100
1
0
0
1
0
1
101
0
0
1
0
0
0
1
0
1
069
0
0
1
0
0
1
0
0
0
1
1
0
070
0
0
1
1
0
0
1
1
0
102
0
0
1
1
0
0
1
1
1
103
0
0
1
0
0
0
1
1
1
071
0
0
1
0
0
1
0
0
0
072
0
0
1
1
0
1
0
0
0
104
0
0
1
0
0
1
0
0
1
073
0
0
1
1
0
1
0
0
1
105
0
0
1
0
0
1
0
1
0
074
0
0
1
1
0
1
0
1
0
106
0
0
1
0
0
1
0
1
1
075
0
0
1
1
0
1
0
1
1
107
0
0
1
0
0
1
1
0
0
076
0
0
1
1
0
1
1
0
0
108
0
0
1
0
0
1
1
0
1
077
0
0
1
1
0
1
1
0
1
109
0
1
1
0
1
1
1
0
110
0
0
1
0
0
1
1
1
0
078
0
0
0
1
0
0
1
1
1
1
079
0
0
1
1
0
1
1,1
1
111
0
0
1
0
1
0
0
0
0
080
0
0
1
1
1
0
0
0
0
112
0
0
1
0
1
0
0
0
1
081
0
0
1
1
1
0
0
0
1
113
o
0
1
0
1
0
0
1
0
082
0
0
1
1
1
0
0
1
0
114
0
0
1
0
1
0
0
1
1
083
0
0
1
1
1
0
0
1
1
115
0
0
1
0
1
0
1
0
0
084
0
0
1
1
1
0
1
0
0
116
0
0
1
0
1
0
1
0
1
085
0
0
1
1
1
0
1
0
1
117
0
0
1
0
1
0
1
1
0
086
0
0
1
1
1
0
1
1
0
118
0
0
1
0
1
0
1
1
1
087
0
0
1
1
1
0
1
1
1
119
o
0
1
0
1
1
0
0
0
088
0
0
1
1
1
1
0
0
0
120
0
0
1
0
1
1
0
0
1
089
0
0
1
1
1
1
0
0
1
121
0
0
1
0
1
1
0
1
0
090
0
0
1
1
1
1
0
1
0
122
o
0
1
0
1
1
0
1
1
091
0
0
1
1
1
1
0
1
1
123
0
0
1
0
1
1
1
0
0
092
0
0
1
1
1
1
1
0
0
124
0
0
1
1
1
1
1
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7·178
OUTPUT DATA
:Ea:
~8 .05 I 04 1 03
ABABA7 A6A6A4A3A2A1 Coo(
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OUTPUT DATA
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ABA8A7 A6A6A4A3A2A'l
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1
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183
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1
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152
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184
0
1
0
0
1
1
0
0
1
153
0
1
0
1
1
1
0
0
1
185
0
154
0
1
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1
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1
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186
0
1
0
0
1
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1
0
1
0
0
1
1
0
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1
155
0
1
0
1
1
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187
0
1
0
0
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1
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156
0
1
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188
0
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157
0
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1
189
0
1
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0
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190
159
0
1
0
1
1
1
1
1
1
191
0
1
0
0
1
1
1
1
1
7·179
2513 CUSTOM CODING INFORMATION
..qg
~~
-0
ADDRESS
ABABA7 A8A5A4A3A2A1
~~
OUTPUT DATA
05
04 03
02
01
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ADDRESS
ABABA7 A8A5A4A3A2A1
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0
1
1
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192
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1
1
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0
0
1
193
0
1
1
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0
0
0
1
225
0
1
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194
0
1
1
1
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0
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1
0
226
0
1
1
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0
0
1
1
195
0
1
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0
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1
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1
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196
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0
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1
229
1
1
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0
1
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230
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198
0
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1
1
1
199
0
1
1
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0
1
1
1
231
0
1
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0
1
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0
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200
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1
1
1
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1
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0
0
232
0
1
1
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0
1
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1
201
0
1
1
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1
233
0
1
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0
0
1
0
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202
0
1
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1
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1
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234
0
1
1
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1
1
203
0
1
1
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0
1
0
1
1
235
0
1
1
0
0
1
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0
204
0
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1
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0
236
0
1
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1
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1
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1
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0
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206
0
1
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1
1
1
0
238
207
0
1
1
1
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1
1
1
1
239
0
1
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0
0
1
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1
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0
0
0
208
0
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240
0
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0
1
1
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1
241
0
1
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210
0
1
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1
0
242
0
1
1
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1
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0
1
1
211
0
1
1
1
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0
1
1
243
0
1
1
0
1
0
1
0
0
212
0
1
1
1
1
0
1
0
0
244
0
1
1
0
1
0
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1
213
0
1
1
1
1
0
1
0
1
245
0
1
1
0
1
0
1
1
0
214
0
1
1
1
1
0
1
1
0
246
0
1
1
0
1
0
1
1
1
215
0
1
1
1
1
0
1
1
1
247
0
1
1
0
1
1
0
0
0
216
0
1
1
1
1
1
0
0
0
248
0
1
1
1
1
1
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0
1
249
0
1
1
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1
1
0
0
1
217
0
1
1
0
1
1
0
1
0
218
0
1
1
1
1
1
0
1
0
260
0
1
1
0
1
1
0
1
1
219
0
1
1
1
1
1
0
1
1
261
0
1
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220
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1
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0
252
0
1
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0
1
221
0
1
1
1
1
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1
263
0
1
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1
1
1
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222
0
1
1
1
1
1
1
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0
254
0
1
1
0
1
1
1
1
1
223
0
1
1
1
1
1
1
1
1
266
7-180
OUTPUT DATA
05
04 03 02 o~
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2513 CUSTOM CODING INFORMATION
ADDRESS
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I!I
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NlNJA7 NJAlMA3A2A1
OUTPUT DATA
06 04 03 02
Q~
!~
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ADDRESS
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l!i
NlMA7 AlAlMA3A2A1
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1
0
0
0
0
0
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0
0
268
1
0
0
1
0
0
0
0
0
288
1
0
0
0
0
0
0
0
1
257
1
0
0
1
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0
0
0
1
289
1
0
0
0
0
0
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258
1
0
0
1
0
0
0
1
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290
1
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1
1
269
1
0
0
1
0
0
0
1
1
291
1
0
0
0
0
0
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0
260
1
0
0
1
0
0
1
0
0
292
1
0
0
0
0
0
1
0
1
261
1
0
0
1
0
0
1
0
1
293
1
0
0
0
0
0
1
1
0
262
1
0
0
1
0
0
1
1
0
294
1
0
0
0
0
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1
1
1
263
1
0
0
1
0
0
1
1
1
296
1
0
0
0
0
1
0
0
0
264
1
0
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1
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0
296
1
0
0
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0
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0
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265
1
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297
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266
1
0
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1
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298
1
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0
0
0
1
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1
267
1
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0
1
0
1
0
1
1
299
OUTP,UT DATA
06 04 03
02 .01
[no
a: a:
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1
0
0
0
0
1
1
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0
268
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0
300
1
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0
0
0
1
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1
269
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1
301
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270
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302
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271
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1
1
303
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272
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0
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304
1
0
0
0
1
0
0
0
1
273
1
0
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1
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305
1
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274
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0
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306
1
0
0
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1
276
1
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1
1
0
0
1
1
307
1
0
0
0
1
0
1
0
0
276
1
0
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308
1
0
0
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1
277
1
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1
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1
309
1
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278
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310
1
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1
0
1
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1
279
1
0
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1
311
1
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280
1
0
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1
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0
0
312
1
0
0
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281
1
0
0
1
1
1
0
0
1
313
1
0
0
0
1
1
0
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282
1
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314
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283
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315
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284
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316
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285
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317
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286
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318
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1
1
1
1
1
287
1
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0
1
1
1
1
1
1
319
7·181
.2513 CUSTOM CODING INFORMATION
~B
ADDRESS
OUTPUT DATA
Ia:
~~
a: a:
05 !Q4
03 02
01
!Ui
AB A8 A7 AS AS A4 A3 A2 A1
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0
0
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1
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322
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323
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324
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0
362
0
1
353
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354
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356
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326
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327
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359
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360
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362
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363
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332
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364
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333
1
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334
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370
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339
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371
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372
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373
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374
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0
346
1
0
1
1
1
1
0
1
0
378
1
0
1
0
1
1
0
1
1
347
1
0
1
1
1
1
0
1
1
379
1
0
1
0
1
1
1
0
0
348
1
0
1
1
1
1
1
0
0
380
1
0
1
0
1
1
1
0
1
349
1
0
1
1
1
1
1
0
1
381
1
0
1
0
1
1
1
1
0
350
1
0
1
1
1
1
1
1
0
382
1
0
1
0
1
1
1
1
1
351
1
0
1
1
1
1
1
1
1
383
7-182
OUTPUT DATA
~m:
IIIC
05!
04 03. 02 . 01'
!li
2513 CUSTOM CODING INFORMATION
~IJ
ADDRESS
ABABA7 A6A6A4A3A2A1
~w
OUTPUT DATA
Qe(
05 04 03 02 01
u!i
wQ
ADDRESS
ABABA7 A6A6A4A3A2A1
..IIJ
e(w
OUTPUT DATA
[no
Qe(
05 04 03 02 01
!o
:Ea:
~g
1
1
0
0
0
0
0
0
0
384
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
385
1
1
0
1
o
0
0
0
1
417
1
1
0
0
0
0
0
1
0
386
1
1
0
1
0
0
0
1
0
418
1
1
0
0
0
0
0
1
1
387
1
1
0
1
0
0
0
1
1
419
1
1
0
0
0
0
1
0
0
388
1
1
0
1
0
0
1
0
0
420
a:
a:
we(
416
1
1
0
0
0
0
1
0
1
389
1
1
0
1
0
0
1
0
1
421
1
1
0
0
0
0
1
1
0
390
1
1
0
1
0
0
1
1
0
422
1
1
0
0
0
0
1
1
1
391
1
1
0
1
0
0
1
1
1
423
1
1
0
0
0
1
0
0
0
392
1
1
0
1
0
1
0
0
0
424
1
1
0
0
0
1
0
0
1
393
1
1
0
1
0
1
0
0
1
425
1
1
0
0
0
1
0
1
0
394
1
1
0
1
0
1
0
1
0
426
1
1
0
0
0
1
0
1
1
395
1
1
0
1
0
1
0
1
1
427
1
1
0
0
0
1
1
0
0
396
1
1
0
1
0
1
1
0
0
428
1
1
0
0
0
1
1
0
1
397
1
1
0
1
0
1
1
0
1
429
1
1
0
0
0
1
1
1
0
398
1
1
0
1
0
1
1
1
0
430
1
1
0
0
0
1
1
1
1
399
1
1
0
1
0
1
1
1
1
431
1
1
0
0
1
0
0
0
0
400
1
1
0
1
1
0
0
0
0
432
1
1
0
0
1
0
0
0
1
401
1
1
0
1
1
0
0
0
1
433
1
1
0
0
1
0
0
1
0
402
1
1
0
1
1
0
0
1
0
434
1
1
0
()
1
0
0
1
1
403
1
1
0
1
1
0
0
1
1
4,35
1
1
0
0
1
0
1
0
0
404
1
1
0
1
1
0
1
0
0
4,36
1
1
0
0
1
0
1
0
1
405
1
'I
0
1
1
0
1
0
1
4137
-----
1
1
0
0
1
0
1
1
0
406
1
1
0
1
1
0
1
1
0
4138
1
1
0
0
1
0
1
1
1
407
1
'I
0
1
1
0
1
1
1
4139
1
1
0
0
1
1
0
0
0
408
1
'I
0
1
1
1
0
0
0
4140
1
1
0
0
1
1
0
0
1
409
1
'I
0
1
1
1
0
0
1
4141
1
1
0
0
1
1
0
1
0
410
1
1
0
1
1
1
0
1
0
4142
1
1
0
0
1
1
0
1
1
411
1
1
0
1
1
1
0
1
1
443
1
1
0
0
1
1
1
0
0
412
1
1
0
1
1
1
1
0
0
~144
1
1
0
0
1
1
1
0
1
413
1
1
0
1
1
1
1
0
1
~145
1
1
0
0
1
1
1
1
0
414
1
1
0
1
1
1
1
1
0
~146
1
1
0
0
1
1
1
1
1
415
1
1
0
1
1
1
1
1
1
~147
7-183
2513 CUSTOM CODING INFORMATION
...I1a
ADDRESS
~w
_a:
ABABA7 A6A5A4A3A2A1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
~8
001(
OUTPUT DATA
...I1a
ADDRESS
~a:
~w
wol(
05 04 03 02 01
!i5
(j~
ABABA7 A6A5A4A3A2A1
wO Q!?
001(
448
1
1
1
1
0
0
0
0
0
480
1
449
1
1
1
1
0
0
0
0
1
481
0
450
1
1
1
1
0
0
0
1
0
482
1
451
1
1
1
1
0
0
0
1
1
483
0
452
1
1
1
1
0
0
1
0
0
484
0
1
1
1
0
0
0
1
0
1
453
1
1
1
1
0
0
1
0
1
485
1
1
1
0
0
0
1
1
0
454
1
1
1
1
0
0
1
1
0
486
1
1
1
0
0
0
1
1
1
455
1
1
1
1
0
0
1
1
1
487
1
1
1
0
0
1
0
0
0
456
1
1
1
1
0
1
0
0
0
488
1
1
1
0
0
1
0
0
1
457
1
1
1
1
0
1
0
0
1
489
1
1
1
0
0
1
0
1
0
458
1
1
1
1
0
1
0
1
0
490
1
1
1
0
0
1
0
1
1
459
1
1
1
1
0
1
0
1
1
491
1
1
1
0
0
1
1
0
0
460
1
1
1
1
0
1
1
0
0
492
1
1
1
0
0
1
1
0
1
461
1
1
1
1
0
1
1
0
1
493
1
1
1
0
0
1
1
1
0
462
1
1
1
1
0
1
1
1
0
494
1
1
1
0
1
1
1
1
495
1
1
1
0
0
1
1
1
1
463
1
1
1
1
0
1
0
0
0
0
464
1
1
1
1
1
0
0
0
0
496
1
1
1
0
1
0
0
0
1
465
1
1
1
1
1
0
0
0
1
497
1
1
1
0
1
0
0
1
0
466
1
1
1
1
1
0
0
1
0
498
1
1
1
0
1
0
0
1
1
467
1
1
1
1
1
0
0
1
1
499
1
1
1
0
1
0
1
0
0
468
1
1
1
1
1
0
1
0
0
500
1
1
1
0
1
0
1
0
1
469
1
1
1
1
1
0
1
0
1
501
1
1
1
0
1
0
1
1
0
470
1
1
1
1
1
0
1
1
0
502
1
1
1
0
1
0
1
1
1
471
1
1
1
1
1
0
1
1
1
503
1
1
1
0
1
1
0
0
0
472
1
1
1
1
1
1
0
0
0
504
1
1
1
0
1
1
0
0
1
473
1
1
1
1
1
1
0
0
1
505
1
1
1
(,
1
1
0
1
0
474
1
1
1
1
1
1
0
1
0
506
1
1
1
0
1
1
0
1
1
475
1
1
1
1
1
1
0
1
1
507
1
1
1
0
1
1
1
0
0
476
1
1
1
1
1
1
1
0
0
508
1
1
1
0
1
1
1
0
1
477
1
1
1
1
1
1
1
0
1
509
1
1
1
0
1
1
1
1
0
478
1
1
1
1
1
1
1
1
0
510
1
1
1
0
1
1
1
1
1
479
1
1
1
1
1
1
1
1
1
511
7·184
OUTPUT DATA
04 03 02 01
en
il::a:
wol(
!i5
2516 CUSTOM CODING INFORMATION
COMPANV _______________________________
PIN CONFIGURATION
ADDRESS _______________________________
,_________ STATE _ _ _ _ ZIP_
CITY
TELEPHONE ______________________________
24
AUTHORIZED SIGNATURE ___________
23
22
DATE
CUSTOMER PRINT OR 10 NO. _________________
20
PURCHASE ORDER NUMBER _ _ _ _ _ _ _ _ __
I.
I'
CUSTOM PATTERN NUMBER (TO BE ENTERED BY
17
SIGNETICS) _ _ _ _ _ _ _'--_ _ _ _ _ __
l'
IS
14
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Chip Enable
NC
Output 8
Output 7
Output 6
Output 5
Output 4
Output 3
Output 2
Output 1
Ground
24.
23.
22.
21.
20.
19.
18.
17.
16.
15.
14.
13.
Voo
VCC
VGG
Address
Address
Address
Address
Address
Address
Address
Address
Address
NC
9
8
7
6
5
4
3
2
1
13
INTRODUCTION
The Signetics 2516 is a high speed silicon gate MOS readonly memories whose organization is specially suited for
64 X 6 X 8 vertical scan character generation.
CHARACTER FORMAT
ROW ADDRESS
MAJOR FEATURES OF THE 2516
•
•
•
•
•
•
64 X 6 X 8 CHARACTER MATRIX
COLUMN OUTPUT
ACCESS TIME 450n5 TYPICALLY
STATIC OPERATION
TTL/DTL COMPATIBLE
TRI-STATE OUTPUTS (HIGH-LOWDISCONNECTED) FOR POWERFUL BUSSING
CAPABILITY
• +5, -5, -12V POWER SUPPLIES
• 24-PIN SIGNETICS SILICONE DIP
• SIGNETICS SILICON GATE PROCESS TECHNOLOGY FOR PERFORMANCE AND RELIABILITY
A3 0
COLUMN
ADDRESS
A2 0
A,
0
,,
,,
, , ,
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
o..!.
0
1
0
0
0
1
0
0
1
1
1
0
EXAMPLE
"s"
FIGURE 1
CHARACTER ADDRESS
ORGANIZATION AS
CHARACTER GENERATOR
A six-bit binary address (A4 through Ag) selects 1-of-64
matrix characters arranged 6 dots horizontally and 8 dots
vertically. A three bit-binary address code (Al through A3)
selects 1 or 6 columns. Eight outputs display a complete
column of the character matrix. See Figure 1.
FIGURE 2
7·185
2516 CUSTOM CODING INFORMATION
•
STANDARD PATTERN
A standard ASCII Character Font is available for the 2516.
This device (2516NX/CM2150) may be used for ASCII
character generation or for device evaluation.
Programming with written truth table.
When punched data cards cannot be supplied, the
truth table may be transmitted in written form using
the attached blank truth table.
VERIFICATION
CUSTOM DEVICES
For unique custom memory patterns, this form should be
used to transmit coding instructions. The nomenclature for
custom device will consist of the basic product type followed
by a unique "CM" number assigned by Signetics. For example, "2516NX'CM2151"
• Programming with punched cards.
For maximum accuracy and minimum cost and turnaround time, the truth table should be transmitted to
Signetics in the form of punched cards according to
the format indicated on the following pages.
Upon receipt of either punched card or written truth table
information, Signetics will prepare a computer tabulation
of the instructions and return to the address indicated. If
errors are detected, they should be transmitted to Signetics
as quickly as possible.
LOGIC CONVENT10N
Logic" 1"s or blackened squares in the truth table will result
in "high" output from the indicated output terminal (i.e.
+3.6V minimum). Similarly, a "1" address input level is
interpreted as +3.2V minimum.
Undefined addresses result in "1" level outputs.
IDENTIFICATION CARDS
INDICATES "COMMENT" CARD
LEAVE COLS. 22, 23,24, _25, 26 BLANK
FOR ASSIGNMENT OF CM NO. BY SIGNETICS
CUSTOMER PIN IDENTIFICATION
I
I
ACME MEMORIES P/N
.. I I
II
I I III
I I
I
00100001001000000110000000000000000000100100000000000000000000000000000000000000
1 23.5'7"M"»~""n"n~MnUnUHHVHH.~n»Mn.U.H"~UU«U.u"u~~nn~~ H~"HH~n"«~"p""~nnn~nnnnn.
111111 i 111111111111111111111111111111111111.1111111 11111 111 I I 11 I I I I I I I I I 11 I 11,11 I I
22122222221212222222222222222222222222122222222122222222222222222222222222222222
7·186
2516 CUSTOM CODING INFORMATION
IDENTIFICATION .CARDS(Cont'd)
PERSON RESPONSIBLE FOR REVIEWING SIGNETICS
COMPUTER GENERATEDTRUTH TABLE
J. Q. ENG I NEER, MEMOR'( PROD.
I
I I
I I
I II II
I
MGR.
II ' I I
I I I I III III
I I
OOO.IOOOOOOOOOOOO~OOOIOOOOOOIOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOt
I 1345'7"M""""~K"K"~~nH"ftaUan.~~~~H.~.H~~UU«U"U~U~~"~~~H~H""""nUu"uu"~nnn~nn""".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
22222222222222222222222222222222222222222222222222222222222222222222222222222222
STREET ADDRESS
. 8000 ELECTRONICS LANE
I
I II
II I I
I
III
I I
00011100000100000100000000000000000000000000000000000000000000000000000000000000
11345""K""""~U"K"a~nn"HaUan~~»»~».~
••• ~uu«u~u~u~~u~~~H~~".""nuu.pu""n~n~nn""".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222222222222212222222222222222222222222222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Z2 2 2 2
CITY
STATE
ZIP
SUNNYVALE, CALIFORNIA 94086
I
II
I
I II II II
I III
00110011000100000000000000100000000000000000000000000000000000000000000000000000
11345'7"M""""~U"""a~nn"ft~UaH.~»»~».~.H.~UU«U~UUU~~U~~~HU~".""nuu"pu""nnn~nn"n".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2212222222222222222222222222222222222222222222222222 2 2 2 2 2 2 2222222222222222222222
COMPANY NAME
~
ACME MEMORIES INC.
I II I I II I II
I I III
I
00000000000000100000000000000000000000000000000000000000000000000000000000000000
I Il.5""M"""W~K"""a~nn"H~uan.~»»~».n.H.~UU«U.U~U~~U~~»HUH"."UnUu"p.""nnn~nn"n".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222222222212222222222222222222222222222222222222 2 2 2 2222222222222222222222222
7-187
2516 CUSTOM CODING INFORMATION
DATA CARDS
DECIMAL CHARACTER ADDRESS
(DATA CARD NUMBER 001 THRU 064)
OUTPUTS Os THROUGH 01 RESPECTIVELY
\
\
JOOOOOOO 00110010 01001001 Ol0010Ll 01001001 00100110
(THIS EXAMPLE ILLUSTRATES OUTPUT SEQUENCE)
111111110110011010101101100101101100101101100110110010 00000-000000000000000000101
I 2 3 4 5 6 7 8 5 101112131415 16 17 18 19 20 21 22232425262728293031 32 33 34 35 36 3738 39 40 41 42434445464748495051 52535455565758596061 6263646566676869707112 7374 75 76 7778 1980
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222222222222222222222222222222222222222222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22222222222212
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4444444444444444444444444444444444444444444444444444 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 44444
55555555555555555555555555555555555555555555555555555555555555555555555555555555
666666666666666666 6 6~ 6 6 6 6 6 666666666666666666666666666666666666666666666666666 S 6 0
11177777717711117711717177777777177777771777777777777777777777777777777777777777
COLUMN ADDR ESS (A3.A2,A 1)
\
\
000
001
\
010
\
011
\
100
\
101
00110010 01001001 0100tOOl 01001001 00100110
(THIS EXAMPLE ILLUSTRATES COLUMN ADDRESS SEQUENCE)
111111110110011010101101100101101100101101100110110010 oooororooooooOOOOoooooolol
I 2 3 4 5 6 7 8 5 10 111213141516171819202122232425262128293031323334353637 383940414243 44454647484950515253545556575859 6061626364656667686970 11727374757617781980
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2222222222222222222222222222222222222222222222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222222222212
33333333333333333333333333333333333333333333333333333333333333333333333333333333
4 4 4 4 4 4 4 4 4 4 4 4 4 4 44 4 4 4 44 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
5 5' 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
666666666666666666 6 6~ 6 6666666666666666666666666666666666666666666666666666 6 6 6 S 6 0
177 77 7 77 117 77 77 711 71 7 77 1 77 7 77 77 7 7717 7 77 1 7 7 77 77 1 7 7 77 77 77 7 7 7 7 7 77 11 7 7 7 77 7 7 77 7 7 7 7 7 7 7
BASIC DEVICE TYPE
LEAVE COLS. 10, 11, 12, 13 BLANK FOR ASSIGNMENT OF CM NO. BY SIGNETICS
\
.6H,NX/CM
1
I
(HEADER CARD)
I
o0 0 0 0II 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 2 3 4 5 6 7 8 I 101112131415 16 17 18 19 20 21 222324252621 28 29 30 31 31333435363738 39 ~C 41 42434445464148495051 52535455565758596061 62636465666768697011 72/314757611 781980
11111111111111111111111111111111111111111111111111111111111111111111111111111111
12222222222222222222222222222222222222222222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222
3333333133333333333333333333333333333333333333333333 3 3 3 3 333333333333333333333333
4444444414444444444444 4 4 4 4 4 4 4 4 44444444444444444444444444444444444444444444444444
515515555 5S S 5 SS 5 5 5 5 5 5 S S 5 5 5 5 5 5 5 5 5 5 55555555555555555555555555555555555555555555555
6 6 6I 6 6 6 6 6 6 6 6 6 6 6, 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 0
77777177177777711171177717177777777177777717777777777777777171777777777777777777
NOTE
"Character" number is in columns 78, 79, and 80.
7·188
2516 CUSTOM CODING INFORMATION
Character Number
Column Decimal
Address
Column
Binary
Address
001
Column Decimal
Address
Column
Binary
000 001 002 003 004 005
002
Character Number
Address
Character Number
Column Decimal
Address
Column
Binary
OOS 009 010 011 012 013
Address
003
Character Number
Column Decimal
Address
Column
Binary
016 017 018 019 020 021
Address
004
024 026 026 027 02S 029
A,
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Output
Output Codes
Output Codes
Output
0,
Output
01
Output Codes
Output
01
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
07
07
0,
Os
Os
Os
Os
Column
Column Decimal
Address
Binary
032 033 034 035 036 037
006
Character Number
~olumn
Column Decimal
Address
Binary
Address
005
Address
A,
0
1
0
1
0
1
A,
A2
0
0
1
1
0
0
A2
A3
0
0
0
0
1
1
A3
A4
0
0
0
0
0
0
A4
A5
0
0
0
0
0
0
A5
007
Character Number
Column Decimal
Address
Column
Binary
040 041 042 043 044 045
Address
Output Codes
01
02
Character Number
1
Character Number
Column Decimal
Address
Column
Binary
048 049 050 051 052 053
008
Address 056 057 05S 059 060 061
0
1
0
1
0
1
A1
0
1
0
1
0
1
A,
0
1
0
1
0
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
Output
Output Codes
Output
Output Codes
Output
Output Codes
Output
0,
01
01
0,
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
07
07
07
Os
Os
Os
Os
0
0
0
Output Codes
--1--
7·189
I
2516 CUSTOM CODING INFORMATION
Chara.ter Number
Column
Binary
Address
009
Column Decimal
Address
A,
0
1
0
1
A2
0
0
1
1
A3
0
0
0
0
A4
0
0
0
0
A5
0
0
0
0
A6
0
0
0
0
0
Column Decimal
Address'
Column
Binary
064 065 066 067 06S 069
Address
011
Character Number
Column Decimal
Address
Column
Binary
072 073 074 075 076 077
Address
0
1
A,
0
1
0
1
0
1
1
0
0
A2
0
0
1
1
0
0
1
1
A3
0
0
0
1
1
1
1
1
A4
0
0
0
0
0
0
0
A5
1
1
0
0
0
0
A6
0
A,
0
1
0
0
A2
0
0
1
1
A3
0
0
0
0
A4
1
0
0
A5
0
0
A6
0
0
0
012
Character Number
Column Decimal
Address
Column
Binary
OSO OS1 082 OS3 OS4 1OS5
1
1
0
010
Character Number
Address
088 OS9 090 091 092 093
1
A,
0
1
0
1
0
0
0
A2
0
0
1
1
0
0
0
1
1
A3
0
0
0
0
1
1
0
0
0
0
A4
1
1
1
1
1
1
1
1
1
1
A5
1
1
1
1
1
1
0
0
0
0
0
A6
0
0
0
0
0
1
0
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
A9
0
0
0
0
0
0
Output
Output Codes
Output Codes
Output
Output
0
Output Codes
Output
0,
0,
0,
02
02
0;2
02
~
03
03
03
0,
04
04
04
04
05
05
05
°5
05
05
05
05
07
cry
cry
°7
Os
Os
Os
Os
013
Character Number
Column
Binary
Address
~olumn
Column Decimal
Address
Column Decimal
Address
Binary
096 097 O9S 099 100 101
014
Character Number
Address
015
Character Number
Column
Column Decimal
Address
Binary
104 105 106 '07 108 109
Address
Output Codes
Column Decimal
Address
Column
Binary
112 113 114 115 116 117
016
Character Number
Address
120, 121 122 123 124 125
At
0
1
0
1
0
1
A,
0
1
0
1
0
,
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
A4
1
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
,
0
1
A5
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
1
1
1
1
1
A6
, ,
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
AS
0
0
0
0
0
O·
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
°
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Output
Output Codes
Output
Output Codes
Output
Output Codes
Output
0,
0,
0,
02
02
02
02
03
03
03
03
04
0,
04
04
04
05
05
05
05
05
05
05
05
07
°7
07
07
Os
Os
Os
Os
7·190
Output Codes
2516 CUSTOM CODING INFORMATION
Character Number
Column
Binary
Address
A,
A2
017
Character Number
Column Decimal
Address
Column Decimal
Address
Column
Binary
128 129 130 131 132 133
Address
018
0
0
1
0
1
A,
0
1
0
1
0
0
0
1
1
0
A2
0
0
1
1
0
0
Column Decimal
Address
Column
Binary
136 '37 138 139 140 141
1
019
Character Number
Address
Column Decimal
Address
Column
Binary
144 145 146 147 148 149
020
Character Number
Address
152 153 154 155 156 157
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
A4
1
1
1
1
1
1
A3
0
0
0
0
,
0
1
A3
0
0
0
A4
0
0
0
0
0
0
A4
1
1
1
A5
0
0
0
0
0
A5
0
0
0
0
°
0
A5
1
1
1
1
A5
1
1
1
1
1
1
A6
0
°
0
0
°
0
,
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A7
0
0
0
A7
0
0
0
°
0
A7
0
°
0
0
0
A7
0
0
0
0
0
0
1
1
A8
1
1
1
1
1
A8
,
0
1
,
0
AB
, , .,
0
1
1
1
1
1
A8
1
1
1
1
1
Ag
0
0
0
0
0
A9
0
0
0
0
0
0
A9
0
0
0
°
0
0
A9
0
0
0
0
0
Output
0
0
0
Output Codes
Output
Output Codes
1
Output
1
Output Codes
Output
0,
0,
0,
01
02
02
°2
02
03
03
03
03
°4
04
04
°4
°5
°5
05
05
°5
05
05
05
07
07
07
°7
Os
08
Os
Os
021
Character Number
Column
Column Decimal
Address
Binary
Address
Column Decimal
Address
Column
Binary
160 161 162 163 164 165
022
Character Number
Address
Column
Column Decimal
Address
Binary
168 169 170 171 172 173
023
Character Number
Address
0
024
Character Number
Column Decimal
Address
Binary
Address
1
Output Codes
Column
176 177 178 179 180 181
1
1
184 185 186 187 188 189
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1 .
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
A7
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
°
0
0
0
1
,
0
AB
1
1
1
1
A8
1
1
1
1
1
1
A8
1
1
1
1
1
1
A9
0
0
0
0
0
0
A9
0
0
0
0
0
0
Ag
0
0
0
°
0
0
A9
Output
Output Codes
Output
Output Codes
Output
Output Codes
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A,
0
0
0
0
0
0
A8
1
1
1
1
1
1
0
0
0
0
0
0
Output
0,
0,
0,
01
02
02
°2
02
03
03
03
D:3
°4
04
°4
°4
°5
05
05
05
°5
°5
05
05
07
07
07
07
Os
Os
Os
08
Output Codes
7·191
2616 CUSTOM CODING 'INFORMATION
Character Number
Column
Binary
Address
Character Number
025
Column Decimal
Address
Column
Binary
192 193 194 19S 196 197
A1
0
1
0
1
0
A2
0
0
1
1
0
A3
0
0
0
0
A4
0
0
0
0
Addres,
Character Number
026
Column Decimal
Address
Column
Binary
200 201 202 203 204 20S
Binary
Address
216
1217 218 1219 220
221
1
0
1
0
1
0
1
A,
0
1
0
1
0
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
1
0
1
0
1
0
0
A2
0
0
1
1
1
1
A3
0
0
0
0
0
0
A4
1
1
1
Column
208 209 210 211 212 213
028
Column Decimal
Address
A1
A,
1
Address
Character Number
027
Column Decimal
Address
AS
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
A5
1
1
1
1
1
1
A6
0
0
0
0
0
0
A6
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A7
1
1
1
1
1
1
A7
1
1
1
1
,
0
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Output
Output Codes
Output Codes
Output
Output
1
Output Codes
Output
01
0,
01
01
02
02
02
02
03
03
03
03
04
04
04
04
Os
05
05
05
Os
05
05
Os
07
0,
07
0,
Os
Os
Os
Os
Character Number
Column
Binary
Address
030
Character Number
029
Column Decimal
Address
Column Decimal
Address
Column
Binary
224 22S 226 227 22S 229
Address
Column Decimal
Address
Binary
232 233 234 235 236 237
Address
Character Number
031
Character Number
Column
240 241 242 243
Output Codes
Column
Binary
1244 245
Address
032
Column Decimal
Address
248 249 250 251 252 253
A1
0
1
0
1
0
1
A,
0
1
0
1
0
1
A1
0
1
0
1
0
1
A,
0
1
0
1
0
1
A2
0
0
1
1
0
A2
0
0
1
1
0
0
A2
0
0
1
"1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
,
0
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
AS
1
1
1
1
1
1
AS
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
,
1
AS
-
A7
1
1
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
0
0
0
Ag
0
0
0
Output
Output Codes
Output
Output Codes
Output
-
Output Codes
Output
01
01
0,
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
07
07
07
Os
Os
Os
Os
0,
7·192
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
Output Codes
2516 CUSTOM CODING INFORMATION
Character Number
Column Decimal
Address
Column
Binary
Address
Character Number
033
Column Decimal
Address
Column
Binary
256 257 258 259 260 261
Address
Character Number
034
Column
272 273 274 275 276 217
Address
Binary
Address
Character Number
Column Decimal
Address
Column
264 265 266 267 26S 269
036
036
Column Decimal
Address
Binary
280 281 282 1283 284 285
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
O.
0
A4
1
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
A6
0
.0.
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
·0
0
0
0
0
A7
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
A9
1
1
1
1
1
1
Output
Output Codes
Output
Output Codes
01
Output
01
1
Output Codes
Output
01
02
02
02
02
OJ
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
try
07
07
Os
Os
Os
Os
Character Numb!!r
Column
Column Decimal
Address
Binary
Address
038
Character Number
037
Binary
2SS 2S9 290 291 292 293
Address
Character Number
Column Decimal
Address
fcolumn
Column
Column Decimal
Address
Binary
296 297 29S 299 300 301
Address
Character Number
039
Binary
304 305 306 307 308 309
Address 312 313 314 31E 316 317
0
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
,()
0
0
0
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
A2
'1
1
040
Column Decimal
Address
Column
1
A1
Output Codes
01
0
1
A1
0
1
0
1
0
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A4
1
1
1
1
1
1
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
P
0
0
0
0
Ag
1
1
1
1
1
1
Ag
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Output
Output Codes
Output
1
Output Codes
1
Output
Output Codes
Output
01
01
01
01
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
-07
07
07
07
Os
Os
Os
Os
Output Codes
7·193
I
2516 CUSTOM CODING INFORMATION
Character Number
Column
Binary
Address
Character Number
041
Column Decimal
Address
Column
Binary
320 321 322 323 324 325
Address
042
Column Decimal
Address
Character Number
Binary
32S 329 330 331 332 333
Address
043
Column Decimal
Address
Column
Character Number
Column
Binary
336 337 :33S 339 340 341
Address
044
Column Decimal
Address
344 345 346 347 348 349
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
,
A,
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
0
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
Ag
1
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
A9
1
1
1
1
1
1
Output
1
Output Codes
Output
Output Codes
Output
Output Codes
Output
0,
0,
0,
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
07
OJ
Os
07
07
Os
Os
Character Number
Column
Column Decimal
Address
Binary
Address
Character Number
045
Column Decimal
Address
icolumn
Binary
352 353 354 355 356 357
Address
047
Character Number
046
Column Decimal
Address
Column
Binary
1360 361 362 363 364 365
Address
0
Output Codes
0,
05
Os
0
Character Number
Binary
36S 369 370 371 372 373
Address
048
Column Decimal
Address
Column
376 377 37S ;379 3S0 3S1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
AS
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
AS
0
0
0
0
0
0
Ag
1
1
1
A9
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Output
0
1
0
1
0
1
Output Codes
Output
1
0
Output Codes
Output
Output Codes
Output
0,
0,
0,
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
07
07
07
Os
Os
Os
Os
7·194
0,
02
Output Codes
1
2516 CUSTOM CODING INFORMATION
Character Number
Column Decimal
Address
Column
Binary
Address
Character Number
049
Column Decimal
Address
Column
Binary
384 385 386 387 388 389
Address
Character Number
050
Column Decimal
Column
Address
Binary
1400 401 402 403 404 405
Address
052
Column Decimal
Address
Column
Address
Binary
392 393 394 395 396 397
Character Number
051
408 409 410 411 412 413
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
0
0
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A6
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
0
0
0
0
AS
1
1
1
1
1
1
A8
1
1
1
...
1
1
AS
1
1
1
1
1
1
A8
1
1
1
1
1
1
Ag
1
1
1
1
1
1
A9
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
qutput
Output Codes
Output
Output Codes
Output
Output Codes
Output
01
01
01
0,
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
05
05
05
05
07
07
07
07
Os
Os
Os
Os
053
Character Number
Column
Column Decimal
Address
Sinary
Address
Binary
0
1
0
1
0
1
A1
0
1
0
1
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
A3
0
0
0
0
1
1
A3
0
0
0
0
A4
0
0
0
0
0
0
A4
1
1
1
1
A5
0
0
0
0
0
0
A5
0
0
0
Column
Address
432 433 434 435 436 437
Address
Column Decimal
Address
Binary
440 441 442 443 444 445
1
A,
0
1
0
1
0
1
A,
°
1
0
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
°
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
0
A5
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
A6
1
1
A6
1
1
0
0
0
0
0
0
A7
0
0
0
0
0
0
A7
0
0
°
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
Ag
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Ag
1
1
A6
1
1
1
1
1
1
A6
A7
0
0
0
0
0
0
A7
AS
1
1
1
1
1
1
A9
1
1
1
1
1
1
Output Codes
0
Column Decimal
Address
Binary
Address 424
425 426 427 42S 429
A1
Output
Column
Output
056
Character Number
055
Character Number
Column Decimal
Address
Column
416 417 418 419 420 421
054
Character Number
Output Codes
Output Codes
Output
1
1
1
Output Codes
1
Output
01
01
01
0,
02
°2
02
°2
03
03
03
03
°4
04
04
°4
05
05
05
05
05
05
05
05
°7
07
07
°7
Os
Os
Os
Os
1
1
1
0
0
0
1
1
1
1
1
1
1
1
Output Codes
7·195
2516 CUSTOM CODING INFORMATION
Character Number
Column Decimal
Address
Column
Binary
Address
Character Number
057
Column Decimal
Address
Column
Binary
44B 449 450 451 452 453
Address
Character Number
058
Column Decimal
Address
Column
Binary
456 467 46S 459 460 461
Address
Character Number
059
Binary
464 465 466 467 46S 469
Address
060
Column Decimal
Address
Column
472 473 474 475 476 477
A1
0
1
0
1
0
1
A1
0
1
0
1
0
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
A2
0
°
1
1
0
0
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
A3t"'
0
0
0
0
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
A4
0
°
0
0
0
A4
1
1
1
1
.1
1
A5
0
0
0
0
0
0
A5
0
A6
0
0
0
0
0
0
A6
0
A7
1
1
1
1
1
1
A7
1
AS
1
1
1
1
1
1
AS
1
Ag
1
1
1
1
1
1
Ag
1
1
Output
Output Codes
0
0
0
0
AS
1
1
1
1
1
A5
1
1
1
1
1
0
0
°
0
0
A6
0
°
°
0
0
0
A6
0
0
°
0
0
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
1
1
1
1
1
AS
1
1
1
1
1
1
AB
1
1
1
1
1
1
1
1
1
1
A9
1
1
1
1
1
1
A9
1
1
1
1
1
1
Output Codes
Output
0,
°
°
1
Output
0,
Output Codes
Output
0,
02
°2
02
02
03
03
03
04
°4
°4
°4
°5
°5
°5
°5
°5
05
05
°5
07
0,
0,
°7
Os
Os
Os
Os
061
Column
Address
Column
488 489 490 491 492 493
Address
Binary
480 481 482 483 484 485
Address
0
,
0
1
A1
0
1
0
1
0
1
1
0
0
A2
0
0
1
1
°
0
0
1
1
A3
0
0
0
0
0
°
0
0
A4
1
1
0
0
0
0
0
0
A5
0
1
1
1
1
1
1
A6
1
A7
1
1
1
1
A7
1
AS
1
1
1
1
"
1
1
1
AS
Ag
1
1
1
1
1
1
A9
A,
0
1
A2
0
0
A3
0
A4
0
A5
A6
Output
Output Codes
Output
063
Character Number
Column Decimal
Address
~olumn
Column Decimal
Address
Binary
062
Character Number
Character Number
Column Decimal
Address
Binary
Binary
496 497 498 499 500 501
064
Column Decimal
Address
Column
Address 504 505 506
607 608 609
1
A,
0
1
0
1
0
1
A,
0
1
0
1
0
1
°
0
A2
0
0
1
1
0
0
A2
0
0
1
1
0
0
0
1
1
A3
0
0
0
0
1
1
A3
0
0
0
0
1
1
1
1
1
1
A4
0
0
0
0
0
0
A4
1
1
1
1
1
1
0
0
0
0
0
A5
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
1
1
1
A6
1
1
1
1
1
1
A6
1
1
1
1
1
1
1
1
1
1
1
A7
1
1
1
1
1
1
A7
1
1
1
1
1
1
1
1
1
1
1
1
AS
1
1
1
1
1
1
AS
1
1
1
1
1
1
1
1
1
1
1
1
A9
1
1
1
1
1
1
Ag
1
1
1
1
1
1
Output Codes
Output
1
Output Codes
Output
0,
0,
0,
0,
02
°2
02
°2
03
03
03
03
04
04
°4
04
05
°5
°5
°5
05
°5
°5
05
°7
°7
°7
07
°B
Os
Os
°8
7·196
Output Codes
0,
03
Character Number
1
°
Output Codes
2526'/30 PROGRAMMING INFORMATION
2530 HIGH SPEED 512 X 8 STATIC READ ONLY MEMORY
PUNCHED CARD INPUT
Header Card
Card No.
Data Cards:
Information
Column
1
1-8
9-14
15-19
20
21
22
23
24-71
72
73-80
Card No.
"2530N/CM"
Blank
Column
1
Information
1-3
"CODED"
Blank
Logic state of Output Enable #2,
(CS2) - Most §.ignificant ~it.
Logic state of Output Enable #1.
Blank
Customer company name.
Blank
Date
Decimal address (blank, blank,
0.)
4
Blank
5-12
8-digit binary output
13-20
Blank
21-33
Decimal address, (blank,
bla'nk, 1.)
24
25-32
Blank
8-Digit binary output
33-40
Blank
(MSB-Ieft)
(MSB-Ieft)
41-43
De<:.[mal address, (Blank,
blank, 2.)
I.D./Comment Cards:
Card No.
Column
1
1
2
3-80
2
3
44
45-52
Information
I'C"
Blank
Person responsible for reviewing
Signetics truth table and Company Name.
61-63
Blank
8-digit binary output
(MSB-Ieft)
53-60
Blank
Decimal address, (Blank,
blank, 3.)
64
Blank
1
2
3-80
"c"
65-72
8-digit binary output
Blank
Customer Street Address
73-80
Blank
1
2
3-80
Blank
Customer City, State, Zip.
(MSB-Ieft)
"c"
2
128
Same format as data card #1.
.---
NOTE: MSB = 09
EXAMPLES:
Header Card
2530
CM3530 CODED 00 ASCII TO EBCDIC AND EBCDIC TO ASCII CODE CONV
I
I
I III
I III
I
111111 I I 111111'
I
I
I III I II I
I
I
02/02/72
II
DOOIOOOOOOOOIOOOOOOOIIOOOIOOOOIOOO~OOOOOOOOOOOOOOOOIOO01000000000000100010110100
I I 3 4 S a I •• 1I111l131'411111711 1IHII 1!IH4HIt,'1 Hlt JOlllllf)4J1I1II JI 31 4041 ItZ 4f414S 4641 41 U IO"II"SI II 14 SS·S"'51S1 IUD" 61 5H461""""'D Ii ii 71 14 Ii ,,1/ " " .
First Data Card'
o 00000000
1 00000001
2 00000010
3 00000011
08101111111100000000000011111110000000000000111111010000000000001111110000000000
I I 3 4 S 1 , •• 1111 IlII 14 1111171111 II II
n U 241 H H lIlt It JO 31 1231)4 IS II !7 JI 314141 41 4J U 4HS, 41414' \0 II l25lSHHUIIISUO" 521154 6111""" ID 71 12 11147S "
1/ " III!1
Last Data Card
508 00000000
509 00000000
510 00000000
511 00000000
0100111111110000000001001111111100000000001011111111.0000000000001111111100000000
I
i 34
I i i • • 11111(11 1411" 1711 1IHII
n\n 14!S 15 17 it 2')(1.11 lZ\n )4 nil II Jl3I4I414241U4HI41 II 4;\1 III/ ,IISlII \611\11""1 6liH'II5U'"'' 10 1111/1 1411" 1/ II IU~
. 7-197
2530/2526 PROGRAMMING INFORMATION
TRUTH TABLE INPUT:
A truth table may be submitted at a greater non-recurring cost to the customer. A format similar to the one shown below is satisfactory.
INPUT ADDRESS
DECIMAL ADDRESS
OUTPUT
08
A9
A8
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
001
1
1
1
1
1
1
1
1
1
510
1
1
1
1
1
1
1
1
1
511
07
06
05
04
03
O2
01
Plus Output Enable 1 and 2 coding.
2526 HIGH SPEED 64 X 9 X 9 CHARACTER GENERATOR
PUNCHED CARD INPUT
Comment/LD. Cards:
Card No.
1
Column
1
2
3-17
18-26
27-71
72
73-80
2
3
4
7·198
Information
"C"
Blank
"SIGNETICS 2526N/CM"
Blank
Customer I.D. (Company, Project, Part No., etc.)
Blank
Date
1
2
3-80
"C"
Blank
Person responsible for reviewing Signetics truth table.
1
2
3-80
"C"
Blank
Customer Street Address
1
2
3-80
"C"
Blank
Customer City, State, Zip.
Card No.
Column
5
1
2
3-80
Information
"C"
Blank
Name
Data Cards:
Card No.
1
Column
1-9
10
11-19
20
21-29
Information
Binary outputs of rows 9
through 1, (MSB at 9), first column, first character, (first
character is "000"). Logic "1"
is high output (3.2V, min.)
Blank
Binary outputs of second column, first character.
Blan.k
Third column
2526 PROGRAMMING INFORMATION
Data Cards (Continued)
Card No.
1
(Cont'd)
30
31-39
40
41-49
50
51-59
60
61-69
70·71
72
73
74-76
77
78-80
2
Information
Card No.
Column
Blank
Fourth column
Blank
Fifth column
Blank
Sixth column
Blank
Seventh column
Blank
Data card number of first
character, ("1").
Blank
Anything - customer option.
Blank
Decimal character number,
("000")
2
(Cont'd)
11-19
20-70
71
72
Eight column
Blank
128
Column
1-9
10
73
74-76
77
78-80
3
1-9
(Etc., as
Card 1)
4
(Etc., as
Card 2)
78-80
Note: MSB
EXAMPLES:
Information
Ninth column
Anything - customer option.
Blank
Data card number of first
character, ("2").
Blank
Customer option
Blank
Decimal character number
("000").
First column, second character,
rows 9 through 1 (MSB at 9).
Second character is "001".
Decimal character number,
("063").
= 09
1.0. Card
C.
CM3400 VERTICAL SCAN CHAR GEN WITH BCDIe AND BAUDOT TO ASCII CONVERSION
I
I III
II III II
I I 11111 I I II I
I III I
I I
II I II
I
I
I
I
I
I
I
I
I
OOOOOOOOOOOllOIOOIOOOOOIOOOOOOOOOOOOOlulOOOOOOOOOOOOOO10010100010000000100109000
I Z 3 4 S I 1 I I 1111 II 1114 IS 1II11111lO 211123 242H121 !l2UII 31 32 U J43S Ii 113UI411 41 4Z 434/11 1& 4141 IHO II 11SlS1SSlSSl SI5NIIII 1153 &161 51 61" n 10 11 lH31HS " II III1N
First Data Card - First Character
010100000 000000000 011111100 100000010 101100010 101010010 101001010
1
0
1010111110111111111010000001100111111010010011101001010110100101101010000000000.
I 2 3 4 5 I 1 I t II II 111111 IS 111111 It lI21 n 2321lSlI 21 !I n lOll llll J4l1.m. 3t It 1111 U II 45 4141.", II II 11IHI
I~ Ii
5111 IUO 1112 6H161 66 61 61 il 10 11 l1ll II 15 16 11111110
Second Data Card - First Character
2
01111100 000000000
o
IICOOOOIIOIIIIIIIIIOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO00000000000000000000000001
1 I J 4 5 • , I I 1111 II 1114 IS 11171111 lO 2122 U lHUI21 lIlt.31 lll3 J41S Ii II .114141 414I4/1S41414141' ~ II S1SlSISSlII1 IIIHII5II21HHHU"Ut ro 11-72 1314 1S1511 11 liN
First Data Card - Last Character
~10001101
I
011111111 000000010 000000001 110100001 000010001 000001001
1
63
000000001111111010111111110000101111 00111101110011111011000000000001
101110010010
I I J 4 5 I , I I 11 11 111114 15 111111 It 20 21 21 U lH5 lI21 lilt. II Ill3 J4 35 Ii 31 .314141 4Z 41 4/1S4141 4141 II 12SlSl ISlSS111S1 11111 I21HHHUlSUt7D II 72 1111 15 151111 liN
~
Second Data Card - Last Character
00000110 000000000
2
63
11111100101111111110000000000000000000000000000000000000000000000000000000000000
, I 2 I 4 5 I 1 I I II II 111111 i~ III; 111. ,lI21 n U 21lS 15 21 !I n lOll llli J4l1.31 .3141 11111)4/45 4111" I' II il 1113 SI II IHI I1II III 51 116HI6I" 6161 il 10 11 l11l 141116 111111111
7·199
2526 PROGRAMMING INFORMATION
TRUTH TABLE INPUT:
A truth table may be submitted at a greater non-recurring cost to the customer. A format similar to the one shown below is
satisfactory _
DECIMAL
ADDRESS
ADDRESS
A10 Ag
AS
A7
A6
A5
A4
A3
A2
Al
0
0
0
0
0
0
0
0
0
0
CHARACTER
OUTPUT DATA
Og Os 0 7 06 0 5 0 4 03 O2 0 1
000
0
0
0
0
0
0
0
0
0
1
001
0
0
0
0
0
0
0
0
1
0
002
0
0
0
0
0
0
0
0
1
1
003
0
0
0
0
0
0
0
1
0
0
004'
0
0
0
0
0
0
0
1
0
1
005
0
0
0
0
0
0
.0
1
1
0
006
0
0
0
0
0
0
0
1
1
1
007
0
0
0
0
0
0
1
0
0
0
OOS
0
0
0
0
0
0
1
0
0
0
009
0
0
0
0
0
0
1
0
0
1
010
FIRST
CHARACTER
1
--
Etc.
503
504
--
505
506
LAST
507
50S
CHARACTER
--
509
510
511
--
7·200
APPLICATIONS MEMO
!ii!lBOlie!i
MOS DEVICES
2526
READ-ONLY MEMORY
INTRODUCTION
OUTPUT CIRCUITS
The 2526 is a high speed 5,184-bit Static Read-Only
Memory. It may be organized as 64 x 9 x 9 for use as a
character generator in dot matrix displays, or as a 512 x 9
ROM for general purpose use. It features TTL compatible
inputs, three-state TTL compatible outputs, two standard
supply voltages (+5, -12), output data latches, and less than
700ns access time. The 2526 is fabricated using Signetics
P-MOS silicon gate process and is packaged in a 24-pin
silicone dual in-line package.
The outputs from the 2526 use a three-state push-pull configuration that allows wired-OR connection of several circuits for expanded capacity. The push-pull circuitry provides
low impedance outputs for both high and low output voltages. See Figure 2. For a low output voltage 02 is turned
ON and 01 is turned OFF with 03 and 04 kept OFF by a
high Output Enable voltage. For a high output voltage 01 is
turned ON and 02 is turned OFF while 03 and 04 are
OFF. When the Output Enable voltage goes low, however,
both 03 and 04 are turned ON, keeping 01 and 02 both
OFF for any condition the output latch assumes. In this
state the output of the 2526 is essentially floating,allowing
other circuits to dominate the output line.
INPUT CIRCUITS
The inputs to the 2526 use a configuration similar to that
used in most of the other 2500 series products. Interface
requirements with TTL circuitry are described in detail in
the Signetics MOS Handbook. In general, a standard TTL
gate driving only the 2526 does not require any interfacing
resistors. See Figure 1. If another TTL gate is driven in
addition to the 2526, a 10k ohm pull-up resistor will improve the input noise margins.
INPUT INTERFACE
+
TTL
-D
0
I~
Figure 3 shows one way to make use of this three-state
output. Two 2526 Character Generators are tied together at
their outputs and fed to the receiving logic c;rcuitry, e.g., a
parallel to serial converter. One 2526 can contain the dot
matrix information for upper case characters and the other
can contain the lower case information, thus providing a
full 128 character set. A I I inputs for the two generators are
tied in parallel except the Output Enables which serve as
A11 address inputs. One 2526 receives the A 11 signal and
the other receives A1T. In this way only one set of outputs
at a time will activate the output lines. If the system configuration requires periods where neither output is active,
that fact can be gated with A 11 to turn off both Output
Enable signals. To reduce power dissipation, the A 11 information can be gated with the READ signals to avoid turning
on the unused 2526.
OUTPUT CIRCUITRY
+5V
+
OUTPUT
ENABLE
+
TTL
TTL
~
D-
OUTPUT
DATA
FROM
LATCH
+5V
1L---_9~Q4
OUTPUT
GND
FIGURE 1
FIGURE 2
7-201
2526 APPLICATIONS MEMO
SCAN DECODING
CAPACITY EXPANSION
INPUT CODES
A4 0 0 o 0 0
A3 0 0 0 0 1
A2 0 0 1 1 0
A1 0 1 0 1 0
0 0 0 1
1 1 1 0
0 1 1 0
1 0 1 0
1 1 1 1 1 1 1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 0 0 1
!
I I I I I I I II
OUTPUT',
•• •••
••• •
•• •• ••• •••
FIGURE 3
EXCESS
CODES
LOGIC 0 < 0.8 VOL T5
LOGIC 1 > 3.2 VOL T5
9X9MATRIX
FIGURE 5
ADDRESS DECODING
The Signetics 2526 Character Generator is organized to
provide 64 character locations with each location described
by a 9 x 9 matrix of bits. The block diagram in Figure 4
shows the address assignments for the character and scan
functions. The six address inputs A5 through A 10 are decoded directly to provide a 1-of-64 character selection. The
four address inputs A 1 through A4 are decoded to provide
a 1-of-9 selection of scans within each character. Since four
address lines can generate 16 scan selections instead of only
9, there are seven excess codes. See Figure 5. The 1-of-9
scan decoder forces the excess input codes to generate all
logic "l's" at the output latches. The address decoding circuits are only activated during a READ operation in order
to save power when the memory is not being used.
TIMING
The timing diagram in Figure 6 shows how the READ signal
controls the operation of the memory. The address inputs
propagate through the decoders and the bit matrix when
READ goes low. The output data are strobed into the
latches when READ goes high. The state of the OUTPUT
ENABLE signal determines whether or not the latched data
are transferred to the outputs. With OUTPUT ENABLE
high, the worst case access time from stable addresses to
valid output data is 700ns. Notice that addresses must be
stable for only a short period of time so that address
changes may be made in parallel with the access operations.
Once the data are set into the latches, they remain stable
for a full READ cycle until the next cycle's data are
available.
BLOCK DIAGRAM
TIMING DIAGRAM
_-tA2-_
ADDRESSES
MAY
CHANGE
FIGURE 4
7-202
ADDRESSES
MAY
,--C;,...H;,...AN;,.;;G_E_ _
FIGURE 6
+-_
2526 APPLICATIONS MEMO
MEMORY ORGANIZATION
CHARACTER ORGANIZATION
The 2526 is intended primarily for use as a 7 x 9 dot matrix
character generator, and the address decoding scheme reflects this purpose. Address lines A 1 through A4 (see
Figure 5) generate the required nine scan selects plus seven
excess codes. Thus, an attempt to use the 2526 with all ten
address lines in a 1024 x 9 configuration would fail because
there are only 5,184 bits in the memory and the excess input address codes would not be able to generate relevant
output data. However, if address input A4 is tied to a logic
"0", the excess codes are eliminated. The remaining nine
address lines may then be used to address a 512 x 9 ROM.
The ninth scan in each character is ignored along with the
excess codes and a subset of 4,608 bits is used to provide
the 512 x 9 capacity.
When used as a 7 x 9 dot matrix character generator, the
9 x 9 dot configuration of each character allows the 2526 to
be used with either vertical or horizontal scanning techniques. Figure 5 shows a 7 x 9 configuration for the letter K
that is oriented for use with a horizontal scan. As each horizontal slice through the character is extracted from the
ROM, the two extra bits may be ignored and the seven remaining bits serially shifted to control the dot formation.
Other organizations are possible, of course, as long as the
total memory capacity is not exceeded. 576 x 9 is the real
capacity of the memory (576 x 9 = 5,184). The extra ~4 x 9
(576 x 9 - ~)12 x 9 = 64 x 9) can be accessed by careful use
of address A4. See Figure 7. The critical condition is stated
in the figure: when A4 is logical "1", AO, A2, and A 1 should
be logical "a's". When A4 is logical "0", any code is allowed
in the remaining nine bits. When some form of counter is
used to generate the address inputs, it will often be convenient to assign the most significant bit (MSB) to A4 and
the six least significant bits to A5 through A10. In this way,
the highest allowed bit configuration will correspond to a
binary count of 575 and the forced zero states of A3, A2,
and A1 will be easier to implement.
576 x 9 ROM ADDRESSING
IT'I ,'I r
MSB
I
LSB
,,1,01 .. 1,,1,·
INPUT ADDRESS BITS
Figure 8 shows the letter K oriented within the 9 x 9 matrix
for use with a vertical scan. Each vertical slice through the
character is extracted from the ROM and then serially
shifted to control the dot formation. Two complete scans
are not used for dots and may supply blank spaces between
characters or may be ignored. Alternatively, those extra
scan positions may be put to good use for translating character codes. When a code translation is desired, the column
address (A 1 through A4) is set to the appropriate translate
scan instead of one of the dot matrix scans, and the code to
be translated forms the row address (A5 through A 10). The
dot matrix contents of that character location are not related to the input code, but the output from the translate
scan provides the desired new code.
Assume that the dot matrix letter K in Figure 8 is placed In
the character array at an address corresponding to the
ASCII-6 code for K (001011). Then the dots for K can only
be retrieved by using the proper ASCII code as an address.
The same code pattern in EBCDIC, however, stands for the
period. To perform an EBCDIC to ASCII translation it is
only necessary to insert the ASCII code for the period
(101110) in the translate scan of the K character position.
This code can then be used directly for any purpose or it
can, in turn, be applied as an input to select the dot matrix
for the period.
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNI FICANT BIT
A4 A3 112 Al Al0 A9 A8 A7 A6 AS
WHEN M - 1. A3 AND A2 AND Al
SHOULD BE O.
FIGURE 7
INPUT ADDRESS
ASSIGNMENTS
The spare bits in the 9 x 9 matrix of each character are
most convenient to use for translations when the matrix is
arranged for vertical scans. In that way a single read operation can perform the translation. A 7 x 9 vertical matrix
leaves two spare scans for translations so that a two-way
translation between two codes is possible, or two source
codes can be translated into a single target code. The spare
bits in the horizontal scan case are only available two at a
time, so are more awkward to use for translations. In either
case, the spare bits can be used to expand the character dot
matrix from 7 x 9 to 9 x 9. Several special characters can be
constructed (e.g., arrows) and some augmented standard
characters (e.g., %) can be more legible.
7-203
2526 APPLICATIONS MEMO
VERTICAL SCAN MATRIX
•• ••
••.Ie •••
• ••
•• ••
I.
1
0
1
1
1
0
X
X
X
t
001011 IN EBCDIC STANDS FOR
PERIOD INSTEAD OF K. THE ASCII
CODE FOR PERIOD (1011101 MAY
BE OBTAINED FROM A TRANSLATE
SCAN.
FIGURE 8
7·204
INPUT ADDRESS 001 011
SELECTS THIS
CHARACTER BLOCK
APPLICATION AREAS
There are many places where a nine bit wide ROM can be
useful. A nine bit output from a function look-up table can
provide an extra degree of accuracy. A sine function table,
for example, could supply an added bit of resolution in the
result. For arithmetic tables with 8-bit operands, the ninth
output bit can be used as a sign bit or a carry bit for increased flexibility. Many byte-plus-parity systems are organized around 9-bit data paths and some of their memory
requirements can only be satisfied with a 9-bit ROM. 9-bit
or 18-bit minicomputers often need Read Only instruction
storage for bootstrap loaders and other non-volatile routines.
The added sophistication of new CRT terminal designs is
making 7 x 9 characters more and more popular. Increased
legibility, decreased errors and better lower case characters
are the immediate advantages. The 2526 provides an economical, easy-to-use approach for implementing 7 x 9
character graphics.
smAoties
APPLICATIONS MEMO
2602
MOS DEVICES
STATIC MEMORY
INTRODUCTION
The Signetics 2602 is a 1024-bit Random Access Read/
Write Memory. It is fabricated with Signetics N-Channel
Silicon Gate technology.
FEATURES
•
•
•
•
•
•
•
•
•
•
1024 x 1 ORGANIZATION
COMPLETELY STATIC OPERATION
+5 VOLT POWER SUPPLY ONLY
TTL COMPATIBLE INPUTS
THREE-STATE TTL OUTPUT
16-PIN DIP PACKAGE
200mW DISSIPATION
N-CHANNE L SI LICON GATE
NO CLOCKS, NO REFRESHING, NO SENSING
DOWN TO 500ns ACCESS/CYCLE TIME
GUARANTEED
In addition to the refresh hardware costs imposed by
dynamic memories, there is also a performance price to pay.
Each refresh cycle ties up the memory and makes it unavailable for normal data operations. There are several
interesting approaches to minimizing the performance impact of the refresh cycles, but each involves an even greater
investment in support logic. Both the hardware and performance penalties of dynamic memory refreshing are
eliminated by the 2602 since no refreshing of any kind is
required by the device.
In the 2602 the on-chip support circuits, as well as the
memory cells, are static. Thus no clocks are required for
any part of the memory operation. Memory clocks for
dynamic memories have proven to be very difficult to drive,
distribute, and time properly so that their complete elimination saves design and debug expenses, and reduces support logic and distribution circuitry costs.
SUPPORT CIRCUITRY
The dominant system design characteristic for the 2602 is
ease of use. This is a result of several unusual features, with
fully static operation as perhaps the most important. Since
the static memory cell does not depend on stored charge
for its data retention, it does not need periodic refreshing.
Thus, the memory does not require external circuitry to
generate and control refresh cycling and refresh addresses.
The on-chip support logic can also be simplified. See the
block diagram in Figure 1.
The output of the 2602 is a three-state, push-pull circuit
that can drive a TTL data bus. For increased capacity
several chips may be directly wire-ORed, taking advantage
of the three-state output. No sense amplifiers or chip buffers
are required. The problems associated with the distribution
of low level sense lines and with coupled sense noise are
eliminated. Figure 2 shows the output buffer circuit.
BLOCK DIAGRAM
With 5 pF of typical input capacitance on any signal input
and no pull-up resistors required to achieve a reliable highlevel input voltage, any simple TTL logic can be used to
drive arrays of the 2602 memory devices. With no high
voltage, high current, or low level interface signals, noise
and crosstalk problems are practically non-existent.
Vee
FIGURE 1
The net result of all these features is a dramatic decrease in
the external support electronics required to implement a
memory system. With greatly simplified driving, no clocks,
no refreshing, and no sensing, the 2602 has eliminated all
the major headaches associated with semiconductor memory
system design. The cost of support electronics is also
dramatically decreased. The result is that memory system
costs per bit relative to dynamic memories are very attractive
for 2602 memory systems of less than about 100K bits.
7-205
2602 APPLICATIONS MEMO
OUTPUT CIRCUITRY
CHIP SELECT
The Chip Select signal on the 2602 performs three interrelated functions. It controls the status of the three-state
output signal, it acts as the decimal address input for
memories of more than 1024 words, and it enables and
disables the write circuitry.
+5V
OUTPUT
ENABLE
For a 1 K word memory where the outputs share a data bus
with other logic subsystems, the Chip ~elect signals can be
tied together and used simply to connect or disconnect the
output data from the data bus. A 2K word version of such
a memory (see Figure 3) could then gate the bus connect
information with the 11th address bit to form two Chip
Select signals. The output data lines from the first 1 K words
are wire-ORed with the output data lines from the second
1 K words. The two Chip Select signals will then connect
the first 1 K or connect the second 1 K or disconnect both
from the output data bus. Notice that the Read/Write lines
need not be gated with the 11th address bit since an unselected chip automatically has the write circuit disabled.
+5V
OUTPUT
OATA
1'---_9~04
OUTPUT
GNO
FIGURE 2
POWER
The 2602 contributes in other ways to decreased memory
system costs. Only one standard supply voltage, +5V ±5%,
is required. Not only are multiple supply costs eliminated,
but power distribution and decoupling problems are minimized.
The low average power of less than 200mW typical and the
important absence of peak currents both contribute to ease
of use and lower costs. The power dissipated by the support
circuits in a dynamic memory system - even a small one can be a large percentage of the system power demands.
With the 2602 static memory, the support dissipation is
practically eliminated and the memory cell dissipation is
very low. Power and cooling costs are, therefore, much less
of a factor in the total memory system economics.
READ OPERATIONS
The Read Cycle for the 2602 is very easy to execute. See
the timing diagram in Figure 4. With the chip selected and
in the read state, simply input an address. The data will be
valid at the output after the access time has elapsed.
Because there are no clocks to define the Read Cycle, it is
measured as the time addresses are required to be stable.
This interval is from the latest arriving address to the
earliest departing address. For the same reason the access
time should be measured from the latest address input.
Care should be taken to make sure that the Read/Write line
is fully in the Read state before any cycle starts. Notice
that one of the memory cells is being addressed at all times;
CHIP SELECT GATING
10 AODRESS LINES
PLUS READ/WRITE
11TH
---...,
•••
_
::~{
•••
11TH
_D--------'C...;.HI.;..PS:.;:E.=,:LE:..:..CT.:...,.....
lK
ADDRESS
_ _ _ _01
DATA OUT
DATA BUSS
FIGURE 3
7-206
2602 APPLICATIONS MEMO
TIMING DIAGRAM
READ CYCLE
ADDRESS
UJ \-~~.
\
'----
--~l
I
I
CHIP
SELECT
R/W
--=i\--t
I
-/ i-
AC
-
-; :
Lu
L -_______________
I
;o100n.
-1i
DATA OUT
r-------"\
---tw-
---tRC--I
WRITE CYCLE
-
,---------.\
-
-
-
-
r-=
--------,
\
DATA IN
ADDRESS
~L_-_-_-_-__-_-_-_-_-_-_-_J"-tcw--~
-\tcslDATA OUT
~ tcDI-
-------.Ir-
_~lL ___ ~L
FIGURE 4
there is no quiescent state for the memory array. Thus, any
time the Chip Select and Read/Write lines are both low,
something will be written somewhere. The Read/Write line
should be considered normally high with a negative-going
write pulse allowed only under strict conditions.
The Chip Select signal may arrive as late as 200ns after the
start of a Read cycte (for the 2602-1) without impacting
the access time. This will often come in handy when there
are extra levels of address gating involved with generating
the Chip Select signal.
WRITE OPERATIONS
The write cycle is also measured by the required stable
address time. Since the Chip Select signal gates the write
circuitry, it must arrive earlier than in a read cycle so that
the write pulse can propagate properly into the cell array.
Notice that the stable addresses must overlap both the start
and finish of the write pulse. It is important that the desired
cell, and only the desired cell, be fully selected before the
write pulse arrives and that the write pulse is 'fully gone
before the addresses begin to change at the cell. The propagation path for the write pulse into the cell is shorter than
the address path through the decoders.
For a minimum write cycte the timing of the write pulse is
important. Notice in the timing diagram that tWD plus twp
is 400ns minimum, which leaves 100ns as the required
minimum Read level before the beginning of the next cycte.
A longer write cycle would allow more flexibility. in the
write pulse timing. The minimum write pulse width is the
most critical parameter and should be maintained even if
the write pulse window within the write cycle is adjusted
slight!y.
WAVEFORMS
The waveform picture in Figure 5 shows the 2602 in action.
The test pattern being run is a simple one designed to check
the general operation of every cell. The memory had previously had zeroes stored in all 1024 cells. Then a pattern of
Read-Write-Read is executed at every cell location. The
first Read at each cell is useo to check for the previously
written zero. The Write cycle then writes a one in the
addressed cell and the second Read confirms that a one was
in fact stored. The address then changes and the three
operations are repeated on the next sequential cell.
Notice that in situations like the one pictured in Figure 5
where multiple cyctes are executed at one address, there is no
obvious, well-defined start of each cycte. Simple external
time delays (not shown in the picture) serve to mark the
transitions from cycte to cycle. The first change in the Data
Out signal following the AO address change reflects the zero
being read at the newly addressed location. During the succeeding Write cycte, the Data Out line indicates the polarity
of the data being written in the cell. At the end of the
Write cycle, the same cell is read again and the Data Out
signal shows that a one was successfully stored. When the
addresses change again, this sequence is repeated.
7-207
2602 APPLICATIONS MEMO
MEMORY CELL
WAVEFORM
+5
t
32 CELLS
PER COLUMN
t
.....E...COLUMNS
BIT
LINE
BIT
LINE
~
WORO LiNE
1/-ls/DIV.
FIGURE 5
BIT SELECT
r
STORAGE CELL
Figure 6 is a schematic ofthe memory bit cell in the 2602. It
is a standard six device cell configuration, using two crosscoupled devices (01, 02) with active pull-ups (03,04).05
and 06 are used to connect the cell to the bit lines.
FIGURE 6
The cells are arranged in a two-dimensional array of 32 by
32 for a total of 1024 cells. Address lines 0 through 4 are
decoded to select 1-of-32 word lines. Each word line drives
32 cells, connecting them to 32 pairs of bit lines. Addresses
5 through 9 are decoded to select 1-of-32 bit line pairs.
Thus, the 10 address lines select one cell out of 1024 for
reading or writing. The bit lines are ORed together and the
selected pair drive the output data amplifier.
When writing, the bit lines are driven by the write amplifiers
to force the selected cell in one direction or the other.
Because the bit lines are being actively driven instead of
passively sensed, the write cycle can always be executed in
500ns or less even when the read cycle is longer.
MEMORY SYSTEMS
For those designers who have worked with dynamic memory
systems, the dominant theme with the 2602 is the things
that do not have to be done. With no clocks, no refreshing
and no sensing, the designer can center his work on optimizing the TTL/MaS interfaces and the system packaging.
7-208
Because of the lack of support circuitry around the 2602,
the propagation paths to and from the memory chip are
much shorter than is the case with dynamic memories. This
fact will help to compensate for the somewhat longer access
times of the 2602, although there are large numbers of
applications where the 2602 offers more than sufficient
speed. The lack of support circuits makes it easy to gain
performance from the static memory by interleaving. The
expensive dynamic support circuitry does not have to be
duplicated for a two-way interleave.
The lack of power surge currents, high voltage transitions,
low level sense currents, and multiple power supplies
simplifies memory system designs in several ways. One
significant result is that many systems will work very well
on two-sided printed circuit boards, with consequent savings
in design and production costs. With less board area devoted
to supporting the memory chips, the board bit density can
be increased.
SIGNETICS STANDARD ROM CODES
STANDARD ROM CODES
CODE CONVERTERS
PIN
TYPE
DESCRIPTION
CMOOOO
EBCDIC-ASCII
2430
CM2810
ASCII to Selectric
2430
CM3421
ASCII-Selectric, Selectric-ASCII
2431
CM3480
EBCDIC to Packed Hollerith
2431
CM3501
Quick Brown Fox Generator (MM522DF)
2420
CM3511
Quick Brown Fox Generator (MM522DZ)
2420
CM3530
ASCII-EBCDIC; EBCDIC-ASCII
2530
CHARACTER GENERATORS
PIN
TYPE
DESCRIPTION
CM2140
ASCII Alphanumeric, 7x5, Row Output
2513
CM2143
Katakana, 7x5, Row Output (Obsolete, See (CM4800)
2513
CM2170
ASCII with yen sign, 7x5, Row Output
CM3001/3010
Upper case ASCII, 10x7, Row Output
2513
(set of 2)
2516
CM3021
Lower case ASCII, 7x5, Row Output
2513
CM3030
Upper case ASCII, 7x5, Row Output
2513
CM3041
Lower case ASCII, 10x7, Row Output (split character)
2516
CM3410
Upper case ASCII, 9x7, Row Output
2526
CM3400
Upper case ASCII, 7x9, with EBCDIC-ASCII and BAUDOT-ASCII in spare left columns,
CM3940
Same as CM3400 but Row Output
Vert. Output
CM2150
ASCII Alphanumeric, 5x7, Column Output
CM3970
12x8 ASCII A thru_ 1st half
CM3980
12x8 ASCII null thru ? 2nd half
CM4800
Katakana 7x5
2526
2526
2516
(set of 2)- ~2516
2516
2513
NOTE: Customer shall ask for and approve a copy of our truth table for any of those ROMs. We do not guarantee the suitability of the contained
truth table for any particular application.
7·209
~tG IIUI~~
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
SECTIONS
PACKAGE INFO
RELIABILITY INFO
INDUSTRY
CROSS· REFERENCE
GUIDE
SECTIONS
(\ r ('\TI" 1\1 (\
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LID MATERIAL: CERAMIC. GLASS SEAL.
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~ SIGNETICS SYMBOL OR ANGLE CUT DENOTES LEAD NO. 1.
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ID MAXIMUM GLASS CLIMB, LID SKEW OR FRIT SQUEEZE OUT .DIO.
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ALL DIMENSIONS SHOWN IN PARENTHESES ARE METRIC EQUIVALENTS. (MILLIMETERS).
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LEAD SPACING SHALL BE MEASURED WITHIN TH.IS ZONE.
SIGNETICS SYMBOL OR ANGLE CUT DENOTES LEAD NO.1.
RECOMMENDEO MINIMUM OFFSET BEFORE LEAD BEND.
THERMAL RESISTANCE, (-) Ja = .150°C/mW, (-) Jc = .050·C/mW.
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THERMAL RESISTANCE: (-) Ja = .220°C/mW, (-, Jc = .0BSoC/mW.
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ALL DIMENSIONS SHOWN IN PARENTHESES ARE METRIC EQUIVALENTS. (MILLIMETERS)
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~ TOLERANCES NON CUMULATIVE.
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8-13
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3.
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TOLERANCES NON CUMULATIVE.
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RECOMMENDED MINIMUM OFFSET BEFORE LEAD BEND.
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9.
THERMAL RESISTANCE: (-J Ja = .200"C/mW, (-J Jc = .OS5'C/mW.
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7
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ALL DIMENSIONS SHOWN IN PARENTHESIS ARE METRIC EQUIVALENTS. (MILLIMETERS)
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8·15
8·16
SIGNETICS • SUPR DIP PROGRAM
INTRODUCTION
• Preseal Visual Inspection, MIL-STD-883, Method
2010, Condition B Criteria
Increasingly, users are demanding ultra high quality and
reliability commercial temperature range ICs for their use
in certain electronic systems. This trend toward a "Zero
Defects" philosophy has been prompted by the inability
of previously available "one or two percent" defective device lots to meet board rework cost requirements and
system reliability goals.
The need for nearly perfect, but low cost, devices is being
met by the industry with varying degrees of success. Several
IC manufactures have programs which partially meet these
requirements, and many users have implemented specifications designed to accomplish this goal.
Signetics has been supplying devices to these general requirements for some time, but only now, and for the first
time in the industry, has a fully evaluated and comprehensive program been instituted. We call it SUPR DIP.
100% Thermal Shock, MIL-STD-883, Method 1011,
Condition A Criteria
•
100% Production Electrical Testing
•
100% High Temperature Functional Testing for elimination of functional rejects and temperature sensitive
(intermittent) bonds
•
Outgoing Lot Quality Acceptance Testing including
0.15% AQL for functionality and 0.15% to 1.0% for
other electrical and mechanical criteria
BENEFITS
The above processing steps are efficiently performed in
volume, and users realize the following benefits at both
DESCRIPTION OF PROCESS STEPS
(see Page 7)
LOW INITIAL COST and LOW EVENTUAL COST:
SUPR DIP utilizes the best provisions of various user specifications and adds a few of our own. SUPR DIP i,s a COMPREHENSIVE program which results in the HIGHEST
QUALITY and RELIABILITY commercial
products AVAILABLE IN THE INDUSTRY. Other suppliers' user
specifications offer SOME of the advantages of our program, but only SUPR DIP gives ALL of the following
provisions:
•
•
Visual Die Sort Inspection, MIL-STD-883, Method
2010, Condition B Criteria
•
Eliminates need for 100% incoming electrical testing
and mechanical inspection
•
No need for additional preconditioning prior to
board assembly
•
Significantly reduces requirement for board rework
(page 8)
•
Reduction in system field failures
• Permits the following Signetics GUARANTEES:
GUARANTEES
TEST
CONDITIONS
AQL
Electrically
25°C
0.15%
Functional
100°C
0.15%
25°C
DC
AC
Mechanic;~1
1.0%
25°C
1.0%
Minor
NOTES
0.15%
1
.65%
At Temperatures
Major
CUMULATIVE
.25%
1.0%
2.5%
1.0%
2
NOTE 1; The functional test not only checks for opens and shorts but also performs an operating test where the device is driven from standard
outputs and drives Inputs under full load.
NOTE 2: MAJOR DEFECTS: those that make the circuit Inoperable such as miSSing pin, wrong symbol, no solder, shorted pins, holes in package.
MINOR DEFECTS: physical dlmenslons,llleglble type, solderability to MIL-S-202C-20BB.
8-17
SIGNETICS • SUPR DIP PROGRAM
WHAT FLOW AND GUARANTEES DO I GET
WITH SUPR?
masking errors and lots that exhibit potential high yield
losses. Critical random defects which constitute reliability
problems and which may not be detected at final test are
inspected to a 1.0% AOL. These include:
1. scratches
2. smears
3. glassivated bonding pads
NOTE 2:
O.C. Lot Acceptance of Preseal Parts
From the above study an analysis was completed on parts
prior to encapsulation. The same inspection at this point is
being performed in accordance with MI L-STD-883, 2010-B
to a 2.5% AOL, and with critical defects to a 0.65% AOL.
Critical defects include:
PROCESS FLOW
a.c. LOT ACCEPT
NOTE 1
1. scratches caused by assembly operators
2. contamination
3. smeared ball bonds on bonding pads decreasing the
aluminum
SUPR
DIE ATTACH
WIRE BOND
VISUAL
a.c. LOT ACCEPT
NOTE 2
SUPR
THERMAL SHOCK
NOTE 3
FINISH
PRODUCT ACCEPTANCE
SYMBOLIZE
HIGH TEMP FUNCTIONAL
TEST NOTE 4
PACK
OUTGOING aUALITY
CONTROL NOTE 5
.----..&...----....
NOTE 3: Preconditioning
Various types of preconditioning were examined including
thermal shock, temperature cycle, and high temperature
storage. Thermal shock (M I L-STD-883, 1011, A) was selected as the most effective method of removing potential
package problems that could not be detected by other processing screens. This processing weakens loose bonds so that
they may be tested out at temperature without degrading
the quality of good bonds. Other tests have either no effect
on quality and reliability or significantly degraded the good
parts during the preconditioning period.
Some users, attempting to incorporate tighter screening,
have instituted various preconditioning steps before testing
or board assembly. Many of these steps create problems
which would not occur if preconditioning was performed
prior to shipment. Examples of a few of these problems are
opens at high temperature due to extremes of thermal
shock or temperature cycles, symbolization coming off
after exposure to liquids used for shock testing, handling
loss and mechanical damage, solderability problems due to
contamination within ovens.
NOTE 4: High Functional Temperature Test
Analysis of user incoming quality and system failure reports
has yielded four significant results:
PROCESS NOTES AND DESCRIPTIONS
NOTE 1: O.C. Lot Acceptance of Die
From reports covering all reported 1971 failures an analysis
was compiled to determine the need for improved inspection
at die sort. The inspection derived from this study was to
lot accept to a 4.0% AOL to MIL-STD-883, 2010B. This is
statistically adequate to reject all lots with repetitive type
8-18
A.
Due to supplier processing and handling from final
test to shipment, parts may become mixed to a low
percent defective.
B.
Some decives, due to internal differential expansion
coefficients, become non-functional when operated
in a system in which the ambient is above room
temperature and the junctions receive continuous
power. This is normally due to weak bonds. These
parts create considerable system detection problems
since they test good at room temperature and may
also become system life test failures.
SIGNETICS • SUPR DIP PROGRAM
C.
Most customers building boards of 40 or more
units complexity perform 100% parts testing upon
receipt of a shipment. This is to obtain a low percentage board rework. This is normally performed
at room temperature using a large test system.
These testers have the potential for destroying or
degrading units due to faulty relay controls which
force excessive currents into devices. In an ordinary electronic system, parts are never subjected
to these conditions. In many cases, this type of inspection results in a greater percent lot defective
than was received and can result in additional
board rework. 100% testing normally only reduces
percent defective to a .28% AQL level. (see Page 8)
AQL LEVELS VS. BOARD REWORKS
1.
One sample is selected to check functionality, using a
tester which has no potential for degrading units. No
relay switching or current forcing modules should be
used.
2.
From this sample another sample is tested for AC and
DC conformance to specifications. Only devices
which have a marginal AC or high temp quality
history need be tested.
3.
In most cases skip lot testing can be instituted immediately.
In this manner a great savings can be realized in incoming
control and board rework costs.
A TYPICAL IC USER'S ASSEMBLY FLOW AND
SOME INDUSTRY AVERAGE COSTS
90
80
70
I---+---+---+~.-c+
"
a;
~
60
~50
I---+--~~-+--+-~r_~
Cl
~ 40
~
r
0.
o
20
10
20
40
60
80
100
120
DEVICES/BOARD
Costs added to parts because of quality problems
(based on current industry averages)
D.
Most integrated circuits will never be used in a
circuit that requires all worst case load and threshold conditions. If a part will function under load
at 100 degrees C ambient, it will consistently work
in a system.
Signetics has addressed to all these problems by
designing a test system that repetitively tests devices
functionally at a temperature in excess of 100
degrees C. This testing circuit is the same electrical
environment as in a computer.
NOTE 5:
Outgoing Quality Control
The task of this function is to ensure that parts have been
processed to the required flow and that the tightened
inspection criteria are being met. An additional sample will
be selected to assure electrical specification conformance.
Each shipment will be sealed by Quality Assurance personnel.
RECOMMENDED INCOMING TEST
Signetics recommends that parts from this program be
sampled at incoming inspection by using the following
technique:
Incoming inspection (sampling, 100% test, preconditioning) labor and material only. Outside labs were
kept separate since they tend to distort this number.
Present average cost for outside lab usage is $.08 per
part.
.02
Find and repair defective parts in boards and systems.
This includes location of defects, scrapped parts, replacement of bad parts, engineering support during
system burn-in. Labor and material only.
.03
Field service support. Labor, material, travel, revenue
lost dLle to equipment being down. Calculated only on
first year expenses. No customer ill will, lost accounts,
maintenance, organization overhead is included.
.01
Administration and overhead. Test equipment for
parts and systems (depreciation, only) support costs
of this equipment, inventory of parts and systems
necessary because of delays due to quality problem~.
No additional hidden costs such as added supervision,
field service overhead, quality and reliability overhead
is included.
.02
TOTAL (not including outside labs)
.08
SUPR DIP WAS ENGINEERED TO CUT THIS EXPENSE
BY ONE ORDER OF MAGNITUDE
8,19
SIGNETICS SURE 883 PROGRAM
FOR DIGITAL DEVICES.
BULLETIN 5001A
The Signetics SU R E· /883 Program consists of a combination of 100
percent and statistical sample tests designed to assure specified
performance, continuing uniformity, and long term reliability of
Signetics products. These tests are made regularly at no extra cost to
the user and are performed in addition to the 40 quality assurance
inspections and tests to which every circuit is subjected before final
seal. The tests, tabulated below for the specifier's convenience, are
performed in accordance with the following conditions, sequence,
and schedules on equipment calibrated to meet all requirements of
MI L-Q-9858A and MI L-C-45662A.
All of the applicable Electrical Parameters of Table IliA are performed at pretest on the Table II I C samples. This provides the
MI L-STD-883 electrical parameter and design verification Group A
tests. These tests are performed on representative circuit types from
every die process family type in manufacturing during this period.
Table I II B consists of the package oriented qualification environmental stress tests of MI L-STD-883, Groups Band C. Representative
samples from each package product family type are monitored and
qualified every 90 day period by these tests. A common device is
used as the die type for these package and assembly qualification
tests.
Every circuit of every lot is processed to the environmental screens
shown in Table I. These screens are performed in production and
include 100% final production electrical tests. Any unit failing
either the environmental screens or the final production electrical
tests is rejected and removed from the lot.
Table "IC consists of the die process oriented qualification electrical stress or operational tests at high temperature per MI L-STD-883,
Groups Band C. Representative devices from each die process
family are monitored and qualified every 90 day period by these
tests. The package type is randomly selected as applicable.
After completion of Table I tests, each manufacturing lot is sampled
and tested by Quality Assurance for conformance to the requirements of Table II. The unsampled portion of the lot is held pending
acceptance of the lot sample. Detailed electrical tbSt limits and
conditions applicable to each subgroup are shown in the Electrical
Characteristics table of the individual part type data sheets_
An additional screening series is available at extra cost. Details are
given in Table V, MI L-STD-883, method 5004, high reliability
screening.
Table I - 100% Production Screen Tests
CONDITIONS
TEST
Tables IliA, II 18, and II I C provide a complete process qualification
and verification program in accordance with the conditions of
MI L-STD-883, Group A, Band C tests. These tests are performed
once in every 90 day manufacturing period, on representative
devices from each standard production die process family and on
each production package family. The representative circuits and
packages selected are changed routinely, and the tests performed
monitor and qualify all structurally similar devices produced by the
same process and production during that period. A summary of
these test results is available on request at the time of order
placement.
Preseal Visual
High Power -
Thermal Shock
Liquid to Liquid, 5 Cycles 60 Seconds
at OoC, 60 Seconds at 100 C, transfer
time 5 Seconds. (See Note 1.)
Centrifuge
Y1 Axis; 30,000 g minimum,
1 minute. (See Note 1.)
Hermeticity
Gross leak test (Bubble Test).
(See Note 1.)
Low Power
e
Production Electrical
Tests
• Systematic' Uniformity and Reliability Evaluation
Table II - Signetics Acceptance Tests (See Notes 2 and 3)
SIGNETICS
SUBGROUP
TEST
CONDITIONS
AQL
MIL·STD·105
INSPECTION LEVEL
A-1
Visual and Mechanical Inspection
MI L-STD-883 Method 2009
1.0%
:IT
A-2
DC Parameters
T A = +25 C
0
1.0%
IT
A-3
DC Parameters
TA = +25 C
0
1.0%
II:
A-4
DC Parameters
TA=+125OC
1.0%
IT
A-5
DC Parameters
T A = -55°C
1.0%
II:
1.0%
]I
A-6
8·20
AC Parameters
0
T A = +25 C
TABLE IliA. MIL-STD-883 GROUP A
ELECTRICAL TESTS
MI L-STD-883
GROUP A
SUBGROUP
SIGNETICS
SUBGROUP
Al
A-2, A-3
A2
A-4
A3
A-5
A4
TEST DESCRIPTION
Static tests at 25°C
Static tests at maximum
rated operating temperature.
Static test. at minimum
rated operating temperature.
A-6
Dynamic tests at 25°C,
A5
C-2. when
applicable
A6
C·2. when
applicable
rated operating temperature.
A-4. A-5
and minimum rated
A7
A8
Dynamic tests at maximum
rated operating temperature.
Dynamic tests at minimum
Functional tests at 25°C.
Functibnal tests at ma)(imum
operating temperatures.
A9
A-6
Switching tests at 25°C.
Al0
C-2. when
applicable
Switching tests at maximum
Al.l
C-2, when
applicable
Switching tests at minimum
rated operating temperature,
rated operating temperature.
TABLE IIIB. MIL-STD-883 GROUPS BAND C ENVIRONMENTAL TESTS
MIL-STD-883
GROUPBllrC
SUBGROUP
TEST DESCRIPTION
MI L·STD-883
METHOD
LTPD
CONDITIONS
Physical DImensions
2008
Test Condition A
15
Marking Permanency
Visual and Mechanical
2008
2008
Test Condition 6. Para. 3,2,1
Test Condition 6
4 devices/no lailure
1 device/no faIlure
~________~~~60~n~dccS~t~re~ng~t~h__________~__~2~01~1____~~T~es~t~C~0~n~di~ti~on~D__~~~~~~~15~___________ _
~__~6~3__~~~So~ld~e~ra~b~il~it~y____________~__~2~00~3~__~~S~0~1d~er~T~e~m~p~e~ra~tu~r~e~26~0~o~C~±~I~Oo~IC~1-~15~________._
64
Lead Fatigue
Hermeticity
B.
Fine
b.
2004
1014
Gross
Test Condition 62
See Note 4
Test Condition A or B
15
Test Condition C
~--~~--~~~~~~~~--------~------~--~~~~~~~~--------1----------------
Cl
Pre-Test Electrical
Signetics Subgroup A-3
Parameters
Thermal Shock
1,011
Temperature Cycle
1010
Harmel1citv
1014
15 Cycles. Test Condition C,
+ 150°C to _65°C
10 Cycles. Test CondItion C.
150°C to -65°C
See Note 4
1004
Test Condition A or B
Test Condition C
Omit initial conditioning.
a.
b,
Fine
Gross
Moisture Resistance
15
End Point Electrical
Parameters
Signetics Subgroup A-3
ReIer to Table IV.
FAILURE CRITERIA
C2
Pre-Test Electrical
Parameters
Mechanical Shock
Signetics Subgroup A-3
2002
Test Condition B
2007
2001
Test Condition A
15
Vibration Variable
Frequency
Constant Acceleration
End Point Electrical
Parameters
FAILURE CRITERIA
Test Condition E
Signetics Subgroup A·3
Refer to Table IV.
r----rC~3----1--S~a~lt~AA.t~m=0~sp~h=e=re~--------~--~INOOM9~---r~T~e=st~C~o~n~di7,ti~on~A~_~O~m-'it~------4--------------initial conditioning.
C4
15
Pre-Test Electrical
Parameters
High Temperature
Storage
Signetics Subgroup A-3
1008
TA
= + 150°C.
t
= 1000 hours
~ =
15
End Point Electrical
Parameters
Signetics Subgroup A-3
ReIer to Table IV.
FAILURE CRITERIA
TABLE IIIC. MIL-STD-883 GROUPS BAND C HIGH TEMPERATURE
OPERATING LIFE TESTS
:~~~~':i~
TEST DESCRIPTION
MIL-8TD-883
CONDITIONS
L TPD
~~SU~B~G~R~O~U~P~~~~__~____________~__M_E_T_H_O_D__~~______________________~____________.__
Pre-Test ai.d Design
Verification Electrical
Table lilA 8S applicable.
data sheet groups A & C.
Parameters
C5
High Temperature
Operating Life
End Point Electrical
Parameters
FAILURE CRITERIA
1005
Test Condition D or E as applicable.
T A • + 125°C or +85 0 C. per Part
Data Sheet. t = 1000 hours.
----------~ =
10
Signetics Subgroup A-3
Refer to Table IV.
• Slgn.tics p'erforms a truth table test.
8-21
Signetics Failure Criteria
Table IV
TEST
" ' " Input Current
LIMITS
"0" Input Current
" ' " Output Voltage
Expansion Node Current
"0" Output Voltage
D&ta Sheet Lim its and:
Data Sheet Limits and:
Data Sheet Limits
Data Sheet Limits and:
Data Sheet Limits and
'OX Initial Value for DTL
±20% Initial Value
±20% Initial Value
±O., V
±20% Initial Value
5X Initial Value for TTL
Optional High Reliability Screening
Notes:
To maximize reliability in critical application, the Optional High
Reliability Screening of Table V provides for three levels of '00%
screening per M I L·STD·883, Method 5004 at extra cost. This series
eliminates the necessity for special specification, minimizes cost and
provides the shortest possible ·delivery time. This series is applied
after the normal Group A acceptance test. Circuits subjected to this
Preconditioning Series are clearly distinguishable from standard
products in the following ways:
,.
Individual serial number on each circuit (Class A only).
2.
The first letters of a part number are either RA, RB, or RC.
RA = Class A
RB = Class B
RC = Class C
i.e., RA8880J
3.
=
1.
Not applicable to solid molded packaged devices.
2.
All test equipment calibrated
MI L·Q·9858A and MI L·C·45662A.
3.
Detailed tests, conditions, and limits applicable to each subgroup
are given in the Signetics data sheet ELECTRICAL CHARAC·
TERISTICS table. See Table IliA for the corresponding Group A
tests of MI L·STD·883.
4.
The Hermeticity
packages.
5.
Class B and Class C may be subjectlld to thermal shock as an
alternate.
6.
The test sequence of fine and gross leak may be reversed when
fluorocarbons are utilized for gross leak.
7.
The individual MI L·STD·883 Test Methods are, in many cases
designed to "stand alone" as a sole screen or sole Group B
environmental sampling test. But since 5004 specifies a screening
series or flow, some of the measurements, etc., specified in an
individual Test Method are not intended to be applicable in the
screening series.
'00% screening of Table V, Class A.
Individual device variables parametric test data is supplied with
each shipment (Class A only).
Consult your local representative for price information. Device
types should be specified with the appropriate letter prefixes.
TABLE V -
tests
are
not
to
meet
employed
requirements
of
for solid molded
MIL-STD-883 METHOD 5004, HIGH RELIABILITY SCREENING
MIL·STD·883
TEST
CLASS A
CLASSB
CLARIFICATIONS
CLASSC
lSeeNoto7}
METHOD
Internal Visual (prese.1)
2010.1
Condo A
Cond, B
Condo B
Test Condition A, Paragraph 3.1.1.7, ., delete the
Stabilization Bake
1008 (24 hours)
Condo C
Condo C
Condo C
::~td~~~n go(~ :~o~ ~2a~O t~) .u~~;.t:~~ze~:~~
words "and paramete,".
I
metallization system, No electrical
me.,urements
at this point.
Thermal Shock
1011
Cond C
Not required.
Not required.
Condo C (150°C) max. for ,u/.1 ."etelliution
system. Condo 0
(200°C) max. for al/al met·
allization system. No electrical mea.urementl, no
external visual Inspection at thil point.
Temperatur. Cvcling
1010
Condo C
Condo C
Condo C
(150 0 C) max. for au/al metallization system.
Condo 0
(200°C) max. for allal metallization
sYltem. No electrical mea.urementl, no external
visual Inspection, no harmeticity teltl at this point.
No electrical me.surementl at this point.
Mechanical Shock
2002. Y 1 plane only
Centrifuge
2001
Hermlticlty
A. Fine Leak
B. Gross Leak
1014, Note 6
(Hermetic deVICes
only)
Not Aequlred
Not Required
Condo E
V2 then Y 1 plane
Condo E
Yl plane
Condo E
Y 1 plane
Condo A or B
Condo C
Condo A or B
Condo C
Condo A or B
Condo C
Critical Electrical Parameterl
Signetics Subgroup A 3
Read and Record
Not Required
Not Required
Burn In Test
1015, TA -' .q2SoC
240 hours Condo 0
or E (as applicable)
168 hours Cond .. D
or E (as applicable)
Not Required
Critical Electrical Parameters
Signetics Subgroup A 3
Read and Record
Not ReqUired
Not ReqUired
Table I V
Not Required
Not Required
Not Requl,'ed
Not Requited
Sign.tics
FAILURE CRITERIA
Reverse Bias Burn In
1015, TA
t
150°C
t - 72 houn
ReqUIred only when specified in the .pplicable
procurement document_ Slgnetics standard burn In
(above) includes reverM bias of unused junctions
r-.------------------~---------------r_-------------r_-----------~------------~-----------------------------
Flnsl Electrical Test
Porforrn go no go
measurements of
Slgn.tlcs Subgroup
A Parameters
Signetics Subgroups
A 2. A 4. A 5, A 6,
Functional tests,
truth lable when
applIcable
Signetlcs Subgroups
A 2,A 3.
FunctIOnal tests,
Iruth lable
when applICable
SlgnltlCS Subgroups
A 2. A 3 Functional
tests, truth table
when applicable
NOI ReqUired
Nol ReqUired
- - - - - - -- ---------- ----4-----------------------------1
RadiographIC Inspection
f-------------------External VISual
8-22
2012
~---------
2009
Ve-s
---
f--Ve.
SIGNETICS LINEAR SURE 883 PROGRAM
SIGNETICS QUALIFICATION AND SCREENING
PROGRAM IN ACCORDANCE WITH MIL-STD883, METHOD 5004 & 5005
The Signetics SU R E * /883 Program consists of a combination of 100 percent and statistical sample tests designed to
assure specified performance, continuing uniformity, and
long term reliability of Signetics products. These tests are
made regularly at no extra cost to the user and are performed in addition to the 40 quality assurance inspections
and tests to which every circuit is subjected before final
seal. The tests, tabulated below for the specifier's convenience, are performed in accordance with the following
conditions, sequence, and schedules on equipment calibrated to meet all requirements of M I L-Q-9858A and
MIL-C-45662A.
Every circuit of every lot is processed to the environmental
screens shown in Table I. These screens are performed in
production and include 100% final production electrical
test. Any unit failing either the environmental screens or
the final production electrical tests is rejected and removed
from the lot.
After completion of Table I tests, each manufacturing lot is
sampled and tested by Quality Assurance for conformance
to the requirements of Table II. The unsampled portion of
the lot is held pending acceptance of the lot sample. Detailed electrical test limits and conditions applicable to each
subgroup are shown in the Electrical Characteristics table of
the individual part type data sheets.
Tables IliA, IIIB, and IIIC provide a complete process
qualification and verification program in accordance with
the conditions of MI L-STD-883, Group A, Band C tests.
These tests are performed once in every 90 day manufacturing period, on representative devices from each standard
production die process family and on each production
package family. The representative circuits and packages
selected are changed routinely, and the tests performed
monitor and qualify all structurally similar devices produced
by the sam(~ process and production during that period. A
summary of these test results is available on request at the
time of order placement.
Table III B consists of the package oriented qualification
environmental stress tests of M I L-STD-883, Groups Band
C. Representative samples from each package product
family type are monitored and qualified every 90 day
period by these tests. A common device is used as the die
type for these packages and assembly qualification tests.
Table IIIC consists of the die process oriented qualification
electrical stress or operational tests at high temperature per
MI L-STD-883, Groups Band C. Representative devices
from each die process family are monitored and qualified
every 90 day period by these tests. The package type is
randomly selected as applicable.
An additional screening series is available at extra cost.
Details are given in Table V, MIL-STD-883, Method 5004,
HIGH RELIABILITY SCREENING.
TABLE I - SIGNETICS 100% PRODUCTION
SCREEN TESTS
TEST
CONDITIONS
r---------------~---------~-----------
~----
Preseal Visual
Thermal Shock
High Power-Low Power
Liquid to Liquid, 5 Cycles,
60 Seconds at O°C, 60 Seconds
at 100°C, transfer time 5
seconds. (Note 1)
Centrifuge
Y 1 Axis; 30,000 g minimum,
1 minute. (Note 1)
Hermeticity
Gross leak test (Bubble Test)
(Note 1)
Production
Electrical Tests
~--------------~---------~-------------------
All of the applicable Electrical Parameters of Table lilA are
performed at pretest on the Table IIIC samples. This provides the MI L-STD-883 electrical parameter design verification Group A tests. These tests are performed on representative circuit types from every die process family type in
manufacturing during this period.
NOTE:
1. Not applicable to solid molded packaged devices.
'Systematic Uniformity and Reliability Evaluation
8-23
SIGNETICS LINEAR SURE 883 PROGRAM
TABLE 11- SIGNETICS ACCEPTANCE TESTS
SIGNETICS
SUBGROUP
TEST
(Notes 2,3)
CONDITIONS
AQL
MIL-STD-105
INSPECTION
LEVEL
A-1
Visual and Mechanical
Inspection
MI L-STD-883
Method 2009
1.0%
II
A-2
DC Parameters
TA = +25°C
1.0%
II
II
A-7
DC End Point*
TA=+25°C
1.0%
A-4
DC Parameters
T A = +125°C
1.0%
II
A-5
DC Parameters
TA = -55°C
1.0%
II
A-6
AC Parameters
TA=+25°C
1.0%
II
·Applies to Data Sheets Published After 6/11/70
NOTES:
2. All test equipment calibrated to meet requ irements of M I L-Q-9858A and M I L-C-45662A.
3. Detailed tests, conditions, and limits applicable to each subgroup are given in the Signetics data sheet ELECTRICAL CHARACTERISTICS
table. See Table lilA for the Corresponding Group A tests of MIL-STD-883.
TABLE IliA - SIGNETICS MIL-STD-883 GROUP A ELECTRICAL TESTS
MI L-STD-883
GROUP A
SUBGROUP
TEST
DESCRIPTION
A1
A-2,A-7
A2
A-4
Static tests at maximum rated operating temperature
A3
A-5
Static tests at minimum rated operating temperature
A4
A-7
Dynamic tests at 25°C
A5
A4
Dynamic tests at maximum rated operating temperature
A6
A5
Dynamic tests at minimum rated operating temperature
Static tests at 25°C
A7
Functional tests at 25°C
A8
Functional tests at maximum and minimum rated operating temperature
A9
8-24
SIGNETICS
SUBGROUP
A-6
Switching tests at 25°C
A10
Switching tests at maximum rated operating temperature
A11
Switching tests at minimum rated operating temperature
SIGNETICS LINEAR SURE 883 PROGRAM
TABLE IIiB - SIGNETICS MIL-STD-883 GROUPS BAND C ENVIRONMENTAL TESTS
MIL-STD-883
GROUP B & C
SUBGROUP
TEST DESCRIPTION
MI L-STD-883
METHOD
CONDITIONS
LTPD
B1
Physical Dimensions
2008
Test Condition A
15
B2
Marking Permanency
2008
Test Condition B, Para. 3, 2, 1
Visual and Mechanical
2008
Test Condition B
4 devices/no
failures
1 device/no
failure
15
Bond Strength
2011
Test Condition D, Para. 3, 7
B3
Solderability
2003
Solder Temperature 260°C ±lO°C
15
B4
Lead Fatigue
Hermeticity
a. Fine
b. Gross
2004
1014
Test Condition B2
Note 4
Test Condition A or B
Test Condition C
15
Cl
Pre-Test Electrical Parameters
Thermal Shock
1011
Temperature Cycle
1010
Hermeticity
a. Fine
b. Gross
1014
Moisture Resistance
End Point Electrical Parameters
FAILURE CRITERIA
1004
C2
M
Pre-Test Electrical Parameters
Mechanical Shock
Vibration Variable Frequency
Constant Acceleration
End Point Electrical Parameters
FAILURE CRITERIA
C3
Salt Atmosphere
C4
Pre-Test Electrical Parameters
High Temperature Storage
End Point Electrical Parameters
FAILURE CRITERIA
2002
2007
2001
Table IV as applicable
15 Cycles. Test Condition C, +150°C
to -65°C
10 Cycles. Test Condition C, +150°C
to -65°C
Note 4
Test Condition A or B
Test Condition C
15
Omit vibration and initial conditioning
Table IV as applicable
Refer to Table IV
Table IV as applicable
Test Condition B
Test Condition A
15
Table IV as applicable
Refer to Table IV
1009
1008
Test Condition A. Omit initial
conditioning
Table IV as applicable
T A = +150°C, t = 1000 hours
Table IV as applicable
Refer to Table IV
15
15
NOTE:
4. The Hermeticity tests are not employed for solid molded packages.
TABLE IIIC - SIGNETICS MIL-STD-883 GROUPS B & C HIGH TEMPERATURE OPERATING LI FE TESTS
MI L-STD-883
GROUP B & C
SUBGROUP
TEST DESCRIPTION
MI L-STD-883
METHOD
Pre-Test and Design
Verification Electrical
Parameters
B5&C5
High Temperature Operating
Life
End Point Electrical Parameters
FAILURE CRITERIA
CONDITIONS
LTPD
Table lilA, as applicable,
data sheet groups A & C
1005
Test Condition B, T A = +125°C
or +85°C, per Part Data Sheet
t = 1008 hours
Table IV as applicable
Refer to Table IV
10
8-25
I
SIGNETICS LINEAR SURE 883 PROGRAM
TABLE IV - SIGNETICS FAILURE CRITERIA
FUNCTION
Operational Amplifier
Comparators
I
(Note 5)
DEL TA LIMITS
PARAMETER
I nput Offset Voltage
±1mV Data Sheet Limits
Open Loop Voltage Gain (Note 6)
±20%
I nput Offset Voltage
±1mV Data Sheet Limits
Open Loop Gain
Input Threshold Voltage
±1 mV Data Sheet Limits
Input Bias Current
±30%
Video Amplifiers
Voltage Gain
±20% Data Sheet Limits
Voltage Regulators
Quiescent Current
±15%
RF/IF Amplifiers
Voltage Gain
±15% Data Sheet Limits
Phase Lock Loop
Center Frequency of Oscillation
±10% Initial Value
Sense Amplifiers
NOTES:
5. For limits of specific devices, consult Signetics Product Marketing
6. For 5709 only
OPTIONAL HIGH RELIABILITY SCREENING
To maximize reliability in critical applications, the Optional
High Reliability Screening of Table V provides for three
levels of 100% screening of MIL-STD-883, Method 5004 at
extra cost. This series eliminates the necessity for special
specifications, minimizes cost and provides the shortest
possible delivery time. This series is applied after the normal
Group A acceptance test. Circuits subjected to this Pre·
conditioning Series are clearly distinguishible from standard
products in the following ways:
(1)
8·26
Individual serial number on each circuit (Class A
only)
(2)
(3)
The first letters of a part number are either RA, RB,
or RC
RA = Class A
RB = Class B
RC = Class C
i.e., RA5709G - 100% screening of Table V, Class A.
Individual device variables parametric test data is sup·
plied with each shipment (Class A only).
Consult your local representative for price information.
Device types should be specified with the appropriate letter
prefixes.
SIGNETICS LINEAR SURE 883 PROGRAM
TABLE V - SIGNETICS MIL-STD-883, METHOD 5004, HIGH RELIABILITY SCREENING
TEST
MI L-STD-883
METHOD
CLASS
A
CLASS
B
CLASS
C
CLARIFICATIONS
(Notes 7, 8, 9)
Internal Visual
(pre-seal)
2010.1
Condo A
Condo B
Condo B
Test Condo A, Para. 3.1.1.7
delete the words "and
parameter"
Stabilization Bake
·1008
(24 hrs.)
Cond.C
Cond.C
Cond.C
Condo C (150°C) max. for
au/al metallization system.
Condo D (200°C) max. for
al/al metallization system.
No electriGal measurements,
at this point.
Thermal Shock
1011
Condo A
Not. Req'd
Not Req'd
Condo C (150°C) max. for
au/al metallization system.
Condo D (200°C) max. for
al/al metallization system.
No electrical measurements,
no external visual inspection
at this point.
Temperature
Cycling
1010
Cond.C
Cond.C
Note 7
Cond.C
Note 7
(150° C) max. for au/al metallization Condo D (200°C)
max. for al/al metallization
system. No electrical measurement, no external visual
inspection, no hermeticity
tests at this point.
Mechanical Shock
200, Y1
plane only
Condo B
Not Req'd
Not Req'd
No electrical measurements
at this point.
Centrifu~le
2001
Condo E
Y2 then
Y1 plane
Condo E
Y1 plane
Condo E
Y1 plane
Hermeticity
a. Fine Leak
1014, Note 6
(Hermetic
devices only)
Condo A
or B
Cond.C
Condo A
or B
Cond.C
Cond.A
or B
Cond.C
b. Gross Leak
Critical Electrical
Parameters
Table IV as
applicable
Read &
Record
Not Req'd
Not Req'd
Burn-In Test
1015, TA = +125°C
240 hrs.
Condo B
168 hrs.
Condo B
Not Req'd
Critical Electrical
Parameters
Table IV as
applicable
Read &
Record
Not Req'd
Not Req'd
Table IV
Not Req'd
Not Req'd
Signetics F A I LU R E
CRITERIA
Reverse Bias
Burn-In
1005, TA = +150°C
t = 72° hours
Cond.A
or C
Not Req'd
Not Req'd
Final
Electrical
Test
Perform go-no-go
measurements of
Signetics sub Group
A Parameters
Signetics
Sub Groups
A-2,A-4
A-5, A-6
Signetics
Sub Groups
A-2,A-7
Signetics
Sub Groups
A-2, A-7
Radiographic
Inspection
2012
Yes
Req'd
Not Req'd
External Visual
2009
Yes
Yes
Yes
I
Not required unless specified
on Purchase Order
NOTES:
7. Class B and Class C may be subjected to thermal shock as an alternate.
8. The test sequence of fine and gross leak may be reversed when fluorocarbons are utilized for gross leak.
9. The individual M I L-STO-883 Test Methods are, in many cases designed to "stand alone" as a sole screen or sole Group B environmental
sampling test. But since 5004 specifies a screening series or flow, some of the measurements, etc., specified in an individual Test Method are not
intended to be applicable in the screening series.
8-27
SIGNETICS MOS 883 SURE PROGRAM
QUALIFICATION AND SCREENING
PROGRAM FOR MOS DEVICES
similar devices produced by the same process and production during that period.
The Signetics SURE* /883 Program consists of a combination of 100 percent and statistical sample tests designed
to assure specified performance, continuing uniformity,
and long term reliability of Signetics products. These
tests are made regularly at no extra cost to the user and are
performed in addition to the 40 quality assurance inspections and tests to which every circuit is subjected before
final seal. The tests, tabulated below the specifier's convenience, are performed in accordance with the following
conditions, sequence, and schedules on equipment calibrated to meet all requirements of M I L-Q-9858A and
MI L-C-45662A.
Every circuit of every lot is processed to the environmental
screens shown in Table I. These screens are performed in
production and include 100% final production electrical
te~ . Any unit failing either the environmental screens or
tl' : final production electrical tests is rejected and removed
from the lot.
After completion of Table I tests, each manufacturing lot
is sampled and tested by Quality Assurance for conformance to the requirements of Table II. The unsampled
portion of the lot is held pending acceptance of the lot
sample. Detailed test limits and conditions applicable to
test group are shown in the Electrical Characteristics table
of the individual part type data sheets.
Tables III, and IV provide a complete process qualification
and verification program. These tests are performed once in
every 90 day manufacturing period, on representative devices from each standard production die process family and
on each production package family. The representative
circuits and packages selected are changed routinely, and
the tests performed monitor and qualify all structurally
All of the applicable Electrical Parameters on the data
sheets are performed at pretest on the Table I V samples.
These tests are performed on representative circuit types
from every die process family type in manufacturing during
this period.
Table III consists of the Package oriented qual ification
environmental stress tests of MI L-STD-883, Groups Band C.
Representative samples from each package product family
type are monitored and qualified every 90 day period by
these tests. A common device is used as the die type for
these package and assembly qualification tests.
Table IV consists of the die process oriented qualification electrical stress or operational tests at high temperature. Representative devices from each die process are
monitored and qualified every 90 day period by these tests.
The package type is randomly selected as applicable.
TABLE I - 100% PRODUCTION SCREEN TESTS
TEST
CONDITIONS
Preseal Visual
High Power
Low Power
Liquid to Liquid
Thermal Shock
5 Cycles; 60 Seconds at O°C,
60 Seconds at 100°C, Transfer
Time 5 Seconds. Note 1.
Centrifuge
Y1 Axis; 30,000 G Minimum 1
Minute. Note 1.
Hermeticity
Gross Leak Test (Bubble Test)
Note 1.
Production
Electrical Tests
AC and DC, TA = 25°C
NOTE:
1. Not applicable to solid molded packaged devices.
TABLE II - SIGNETICS ACCEPTANCE TESTS (See Notes 2 and 3)
CONDITIONS
AQL
MIL-STD-105 INSPECTION LEVEL
Visual and Mechanical
Inspection
MI L-STD-883
Method 2009
1.0%
II
TEST GROUP
DC Parameters
TA=+25°C
1.0%
II
DC Parameters
TA = 70°C
1.0%
II
DC Parameters
TA =
O°C
1.0%
II
AC Parameters
TA = +25°C
1.0%
II
..
NOTES:
2.
3.
·Systematic Uniformity and Reliability Evaluation
All test equ ipment calibrated to meet requ irements of M I L-Q-9858A and M I L-C-45662A.
Detailed tests, conditions, and limits applicable to each test group are given in the Signetics data sheet ELECTRICAL
CHARACTERISTICS table.
8-28
SIGNETICS MOS 883 SURE PROGRAM
TABLE III - MIL-STD-833 GROUPS BAND C ENVIRONMENTAL TESTS
TEST DESCRIPTION
MI L-STD-833 METHOD
CONDITIONS
LTPD
Physical Dimensions
2008
Test Condition A
15
Marking Permanency
Visual and Mechanical
Bond Strength
2008
2008
2011
Test Condition B, Para. 3.2.1
Test Condition B
TestCondition 0, Para. 3.7
4 devices/no failures
1 device/no failures
15
Solderability
2003
Solder Temperature
260°C ±lOoC
15
Lead Fatigue
Hermeticity
a. Fine
b. Gross
2004
1014
Pre-Test Electrical
Parameters
Test Condition B2
Note 4
Test Condition A or B
Test Condition C
Table V as Applicable
15 Cycles. Test Condition C,
o
+150 C to -65°C
Thermal Shock
1011
Temperature Cycle
1010
Hermeticity
a. Fine
b. Gross
1014
10 Cycles. Test Condition C,
+150°C to -65°C
Note 4
Test Condition A or B
Test Condition C
1004
Omit Vibration and Initial
Conditioning
Moisture Resistance
End Point Electrical
Parameters
Table V as Applicable
FAIL.URE CRITERIA
Refer to Table V
Pre-Test Electrical
Parameters
2002
Test Condition B
Vibration Variable Frequency
2007
Test Condition A
Constant Acceleration
2001
End Point Electrical
Parameters
Table Vas Applicable
FAILURE CRITERIA
Refer to Table V
1009
Pre-Test Electical
Parameters
High Temperature Storage
15
Table Vas Applicable
Mechanical Shock
Salt Atmosphere
15
15
Test Condition A. Omit
Initial Conditioning.
I
Table V as Applicable
1008
TA
= +150°C,
t
= 1000 hours
End Point Electrical
Parameters
Table V as Applicable
FAILURE CRITERIA
Refer to Table V
15
NOTE:
4. The hermeticlty tests are not employed for solid moldad packages.
8-29
SIGNETICS MOS 883 SURE PROGRAM
TABLE IV - HIGH TEMPERATURE OPERATING LIFE TESTS
LTPD
CONDITIONS
TEST DESCRIPTION
Pre-Test Electrical Parameters
Refer to Table V
Operating Life
TA
= 70° C; t = 1000 hours
10
Shift Registers
Logic 1's Clocked Through Register
ROMs, RAMs
Addresses Being Counted Through in a Binary Fashion
TABLE V - SIGNETICS FAILURE CRITERIA
SHIFT REGISTERS
TEST
Delta Limit
INPUT LEAKAGE
5X or 100nA whichever
is greater
tACCESS
"1" LEVELS
"0" LEVELS
Data Sheet
Limits
20%
20%
CLOCK LEAKAGE
100
"1"LEVELS
5X or 100nA whichever
is greater
20%
100
20%
ROMs
TEST
Delta Limit
INPUT LEAKAGE
5X or 100nA whichever
is greater
20%
"0" LEVELS
20%
RAMs
TEST
INPUT LEAKAGE
Data Limit
5X or 100nA whichever
is greater
• For dynamic memories.
8-30
tACCESS
Data Sheet Limit
tREFESH*
Data Sheet
Limits
"1" LEVELS
20%
"0" LEVELS
20%
::i1l:i1'\lt:111.0)
AMD
n l ,",nv,",,", , .... , ........... " .... _ _ _ • __
SIGNETICS
PAGE
FAIRCHILD
SIGNETICS
PAGE
FAIRCHILD
SIGNETICS
PAGE
LM202
LM101H
6-169
9N02
S5402A/F
2-6
9H08
S54H08A/F
2-191
LM101A
LM101AH
6-164
9N02
N7402A/F
2-6
N74H08A/F
2-191
LM201
LM201H
6-169
9N03
S5403A/F
2-8
S54H10A/F
2-193
LH201D
LM201N
6-164
9N03
N7403A/F
2-8
N74H10A/F
2-193
LM301A
LM301AH
6-164
9N04
S5404A/F
2-10
LM301AD
LM301AV
6-164
9N04
N7404A/F
2-10
9N05
S5405A/F
2-12
N7405A/F
2-12
9N06
S5406A/F
2-14
N7406A/F
2-14
9N07
S5407A/F
2-16
N7407A/F
2-16
S5408A/F
2-18
N7408A/F
2-18
9N09
N7409A/F
2-20
9N10
S5410A/F
2-22
9N11
S5411A/F
2-24
N7411A/F
2-24
S5420A/F
2-28
N7420A/F
2-28
9N26
S5426A/F
2-32
9N30
S5430A/F
2-34
N7430A/F
2-34
S5440A/F
2-38
N7440A/F
2-38
9N50
S5450A/F
2-58
N7450A/F
2-58
9N51
S5451A/F
2-58
N7451A/F
2-58
9N53
S5453A/F
2-60
N7453A/F
2-60
S5454A/F
2-60
N7454A/F
2-60
9N60
S5460A/F
2-62
N7460A/F
2-62
9N70
S5470A/F
2-66
N7470A/F
2-66
7-57
9N72
S5472A/F
2-68
N7472A/F
2-68
7-57
9N73
S5473A/F
2-70
N7473A/F
2-70
S5474A/F
2-72
N7474A/F
2-72
9N76
S54768/F
N74768/F
2-77
2-77
9N86
S54868/F
2-88
N7486A/F
2-88
S54107A/F
2-110
N74107A/F
2-110
S54HOOA/F
9352
N74HOOA/F
2"183
2-183
S54H01A/F
2-185
9353
N74H01A/F
2-185
S54H04A/F
2-187
N74H04A/F
2-187
S54H05A/F
2-189
N74H05A/F
2-189
LM307
LM307H
6-175
AM1101A
25018
7-45
AM1402A
25028
7-57
AM1403A
2503TA
7-57
AM1404A
2504TA
7-57
AM1506
2506T
7-68
AM1507
2517T
7-68
ANALOG
SIGNETICS
PAGE
DEVICES
AD101AH
LM101AH
6-164
AD201H
LM201AH
6-164
AD301AH
LM301AH
6-164
AD710CH
j.LA71 OCT
6-99
AD710CN
j.LA710CA
6-99
AD710H
j.LA710T
6-99
AD711CH
j.LA711CK
6-101
AD711CN
j.LA711CA
6-101
AD711H
j.LA711K
6-101
AD741CH
j.LA741CT
6-115
AD741CN
j.LA741CA
6-115
AD741H
j.LA741T
6-115
CMI
SIGNETICS
PAGE
CM1101/
25018/P
7-45
11011
1101A1
CM1103
1103XA/
CM1402
25028/
1103-1XA
7-15
9N08
9N20
9N40
9N54
7-21
7-57
1402A
CM1403
2503TA/
1403A
CM1404
2504TA/
1404A
CM251:.!
2512K
7-62
CM4500
2525V
7-108
CM7601
N24101
7-32
CM7602
N2420Y
7-32
CM7603
N2430Y
7-32
9N74
9N107
FAIRCHILD
SIGNETICS
PAGE
6-97
*
II~UU;:)I
*j.LA71 0
j.LA71 0
6-99
*j.LA711
j.LA711
6-101
*j.LA741
j.LA741
6-115
*j.LA748
j.LA748
6-124
9NOO
S5400A/F
2-2
9NOO
N7400A/F
2-2
9N01
S5401A/F
2-4
9N01
N7401A/F
2-4
= Requires definition of Temp.
9HOO
9H01
9H04
9H05
9H10
9H11
9H20
S54H11A/F
2-195
N74H11A/F
2-195
S54H20A/F
2-197
N74H20A/F
2-197
9H22
S54H22A/F
2-201
N74H22A/F
2-201
9H30
S54H30A/F
2-203
N74H30A/F
2-203
S54H40A/F
2-205
N74H40A/F
2-205
S54H50A/F
2-206
N74H50A/F
2-206
S54H51A/F
2-207
N74H51A/F
2-207
9H40
9H50
9H51
9H61
9H62
9H71
9H72
9H73
9H74
9H76
9H101
9H102
9H106
9H108
9341
S54H61A/F
2-219
N74H61A/F
2-219
S54H62A/F
2-221
N74H62A/F
2-223
S54H71A/F
2-225
N74H71A
2-225
S54H72A/F
2-227
N74H72A/F
2-227
S54H73A/F
2-229
N74H73A/F
2-229
S54H74A/F
2-231
N74H74A/F
2-231
S54H768/F
2-233
N74H768/F
2-233
S54H101F
2-235
N74H101A/F
2-235
S54H102F
2-237
N74H102A/F
2-237
S54H1068/F
2-241
N74H1068/F
2-241
S54H108F
2.244
N74H108A/F
2-244
N741418
2-119
S54181F
2-281
N74181N
2-281
9342
S541828/F
2-164
N741828/F
2-164
9345
S5445F
2-48
N74458/F
2-48
S54180A/F
2-158
N74180N/F
2-158
S54428/F
2-42
N74428/F
2-42
9349
S54438/F
2-44
N74438/F
2-44
S54448/F
2-46
N74448/F
2-46
9357A
N74468/F
2-50
93578
N74478/F
2-50
9358
N74488/F
2-54
9354
Range and Pkg.
8-31
I
FAIRCHILD
SIGNETICS
PAGE
FAIRCHILD
SIGNETICS
PAGE
FAIRCHILD
SIGNETICS
PAGE
9360
S74192B/F
2-166
U5E7796393
p,5596K
6·147
U6A743059X
N7430A/F
2-34
N74192B/F
2-166
U5F7711312
p,A711K
6-101
USA 744059X
N7440A/F
2-38
554192B/F
2-166
U5E7711393
p,A711CK
6-101
U6A745059X
N7450A/F
2-58
N74192B/F
2-166
U5F7733312
",A733K
6-108
USA745159X
N7451A/F
2-58
9375
57475B/F
2-75
U5F7733393
/JA733CK
6-108
U6A745359X
N4753A/F
2-60
N7475B/F
2-75
U5R7723312
/JA723L
6-103
U6A745459X
N7454A/F
2-60
9380
S5480A/F
2-81
U5R7723393
/JA723CL
6-103
U6A746059X
N7460A/F
N7480A/F
2-81
U6A7733312
p,A733F
6-108
U6A747059X
N7470A/F
2-64
2-66
S5483B/F
2-85
U9T7741393
/JA741CV
6-115
U6A747259X
N7472A/F
N7483B/F
2-85
U9T7748393
p,A748CV
6-124
U6A747359X
N7473A/F
2.-68
2-70
55490A/F
2-94
U6A54oo51 X
55400A/F
2-2
U6A747459X
N7474A/F
2-72
N7490A/F
2-94
U6A540151X
S5401A/F
2-4
U6A748059X
N7480A/F
2-81
S5491A/F
2-96
U6A540251X
S5402A/F
2-6
U6A748259X
N7483A/F
2-85
N7491A/F
2-96
U6A540351X
S5403A/F
2-8
U6A748659X
N7486A/F
2-88
9392
55492A/F
2-98
U6A540551 X
S5405A/F
2-12
U6A 749059X
N7490A/F
2-94
N7492A/F
2-98
U6A540851 X
S5408A/F
2-18
U6A749159X
N7491A/F
2-96
9393
S5493A/F
2-100
U6A541051X
S5410A/F
2-22
U6A749259X
N7492A/F
2-98
N7493A/F
2-100
U6A541151X
S5411A/F
2-24
U6A749359X
N7493A/F
2-100
N7495A/F
9366
9383
9390
9391
55494F
2-102
U6A542051 X
S5420A/F
2-28
U6A749559X
N7494B/F
2-102
U6A543051X
S5430A/F
2-34
U6A74H0059X N74HOOA/F
2-183
55495A/F
2-104
U6A544051 X
S5440A/F
2-38
U6A74H0159X N74H01A/F
2-185
N7495A/F
2-104
U6A545051X
S5450A/F
2-58
U6A74H0459X N74H04A/F
2-187
55496B/F
2-106
U6A545151 X
S5451 A/F
2-58
U6A74H0559X N74H05A/F
2-189
N7496F/F
2-106
U6A545351 X
S5453A/F
2-60
U6A74Hl059X N74H10A/F
2-193
554198F
2-178
U6A545451X
S5454A/F
2-60
U6A74H2059X N74H20A/F
2-197
N74198N
2-178
U6A546051 X
S5460A/F
2-62
U6A74H3059X N74H30A/F
2-203
554121A/F
2-112
U6A547051X
S5470A/F
2-66
U6A74H4059X N74H40A/F
2-205
N74121A/F
2-112
U6A547251X
S5472A/F
2-68
U6A74H7359X N74H73A/F
2-229
9500
N74SOOA
2-247
U6A547351X
S5473A/F
2-70
U6A74H7659X N74H76B/E
2-233
9503
N74503A
2-247
U6A547451X
S5474A/F
2-72
U6A 7723393
p,A 723A/F
6-103
9504
N74504A
2-249
U6A548051X
55480A/F
2-81
U6A 7733393
p,A 733A/F
6-108
9505
N74505A
2-249
U6A548251X
S5483A/F
2-85
U6A 7741393
p,A 741 A/F
6-115
9520
N74520A
2-254
U6A548651 X
S5486A/F
2-88
U6A7748393
p,A748A/F
6-124
9522
N74522A
2-256
U6A549051X
S5490A/F
2-94
U6A960159X
N8T22A/F
3-159
9S40
N74S40A
2-258
U6A549151X
S5491A/F
2-96
U6B547551X
55475B/E
2-75
9564
N74564A
2-260
U6A549251X
S5492A/F
2-98
U6B547651X
55476B/E
2-77
9565
N74565A
2-260
U6A549351 X
S5493A/F
2-100
U6B548351X
S5483B/E
2-85
95140
N745140A
2-258
U6A549551 X
S5495A/F
2-104
U6B744159X
N7441B/E
2-40
U5B101A312
LM101AH
U6A54H0051X 554HOOA/F
2-183
U6B747559X
N7475B/E
2-75
U5B301A393
LM301A
6-164
6-164
U6A54H0151 X 554H01 A/F
2-185
U6B748359X
N7483B/E
2-85
9394
9395
9396
93198
9603
2-104
U5B770939X
p,A 7041 T
6-97
U6A54H0451 X S54H04A/F
2-187
U6B7414159X N74141B/E
2-119
U5B7710312
6-99
U6A54H0551X S54H05A/F
2-189
U6E7709393
p,A709CA/CF
6-97
U5B7710393
p,A710T
p,A710LT
6-99
U6A54H1051X S54Hl0A/F
2-193
U6E771 0393
p,A710CA/CF
6-99
U5B7101312
LM101H
6-164
U6A54H2051X S54H20A/F
2-197
U6E7711393
p,A711CA/CF
6-101
U5B7101333
LM201H
6-164
U6A54H3051 X 554H30A/F
2-203
U6E7723393
p,A723CA/CF
6-103
U5B7740312
5E536T
6-32
U6A54H4051 X S54H40A/F
2-205
U6E7733393
p,A733CA/CF
6-108
U5B7740393
NE536T
6-32
U6A54H7351X S54H73A/F
2-229
UG E7741393
p,A741 CA/CF
6-115
U5B7709393
p,A709CT
6-97
U6A54H7651 X S54H76B/E
2-233
U6E7748393
p,A748CA/CF
6-124
U5B7709312
p,A709T
6-97
U6A740059X
N74ooA/F
U6M7520393
N7520B
6-149
U5B7740312
p,A740T
6-113
U6A740159X
N7401A/F
2-2
2-4
U6M7521393
N7521B
6-149
U5B7740393
p,A740CT
p,A741T
6-113
U6A740259X
N7402A/F
2-6
U6M7522393
N7522B
6-149
U5B7741312
6-115
U6A740359X
N7403A/F
2-8
U6M7523393
N7523B
6-149
U5B7741393
p,A741CT
6-115
U6A740459X
N7404A/F
2-10
U6M7424393
N7524B
6-149
U5B7748312
p,A748T
6-124
U6A740559X
N7405A/F
2-12
U6M7525393
N7525B
6-149
U5B7748393
p.A748CT
6-124
U6A740859X
N7408A/F
2-18
U6T7741393
p,A 741 CV
6-115
U5B7710312
p,A710T
6-99
U6A741059X
N7410A/F
2-22
U6T7748393
p,A 748CV
6-124
U5B771 0392
p,A71 OCT
N7411A/F
2-24
U7B544251X
55442B/E
2-42
55596K
6-99
6-147
U6A741159X
U5E7796312
U6A742059X
N7420A/F
2-28
U7B544351 X
55443B/E
2-44
NOTE: Fairchild 54/74 Dual-in-line is available ONLY in Cerdip. Signetics Dual-in-line is
8-32
avail~le
in BOTH Silicone and Cerdip.
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
SIGNETICS
PAGE
FAIRCHILD
SIGNETICS
PAGE
INTEL
SIGNETICS
PAGE
MIL
U7B544451X
S5444B/E
2-46
1506
2506T/
7-68
MF1506
2506T/1506
7-68
U7B549451X
S5494B/E
2-102
MF1507
2517T/1507
7-68
U7B549651X
S5496B/E
2-106
U7B541925'IX
S54192B/E
2-166
U7B5419351 X
S54193B/E
2-170
MM
SIGNETICS
PAGE
U7B744259X
N7442B/E
2-42
MM3402
2502B/1402A
7-57
MM3403
2503TA/
7 -57
1506
1507
2517T/
P21Q2
2602B/
7-68
1507
7-158
26021B
U7B744395X
N7443B/E
2-44
3101
N8225B
4-15
U7B744459X
N7444B/E
2-46
3101A
N8225B
4-15
U7B744759X
N7447B/E
2-50
3016
N82S061
4-20
U7B745859X
N7448B/E
2-54
1307
N82S071
4-20
U7B749459X
N7494B/E
2-102
3301
N82S26F
4-30
U7B749659X
N7496B/E
2-106
3601
N82S26F
4-30
U7B7419259X
N74192B/E
2-166
U7B7419359X
N74193B/E
2-170
U7B9034A9B
N8224B/E
4-11
U7B930159X
N8252B/E
3-39
U7B931259X
N8230B/E
3-22
U7B931599X
N7441B/E
2-40
U7B932859X
N8277B/E
3-88
GI
SIGNETICS
PAGE
*INTEL uses Prefix P for Plastic,
C for Ceramic.
INTERSIL
SIGNETICS
PAGE
IM7051
2501B/
7-45
P1101A1
25361
7-139
RA91101/
2501B/
7-45
RA91101A-1
RA91103
P1101A1
1103XA/
7-15
4-15
4-30
1024A
N82S26F
4-30
1024B
N828S26F
4-30
8256
N8223B
4-8
MC201G
SE101K*
MC202F
SE102G*
MC202G
SE102K*
MC203F
SE105G*
2503TA/
7-57
1403A
IM7703CPA
2503V
7-57
IM7704CTA
2504TA/
7-57
SE150G*
7-57
MC205G
SE150K*
2506T/1506
7-68
MC206F
SE115G*
2517T/1507
7-68
MC206G
SE115K*
IM7712CTB
2512K
7-62
MC206G
SE115K*
IM7722CPA
2525V
7-108
MC207F
CS700G*
5501
N8225B
4-15
MC207G
CS700K*
5503
N82S071
4-20
MC208F
CS701G*
5523
N82S061
4-20
MC208G
CS701 K*
5533
N82S071
4-20
MC209F
SE124G*
5600
N8223B
4-8
MC209G
SE124K*
5603
N82S26F
4-30
MC210F
CS704G*
5610
N82S123B
4-27
MC210G
CS704K*
MC215F
CS705G*
PAGE
C1101A/
25011/
7-45
MF1101A/
2501 B/
7-45
1101A1
MF1101A/
P1101A
2501 B/
P1101A1
P1101A1
1101A1
MF1103/
1103-1K/
7-21
1103-11K
7-21
P1103
1103XA/
7-15
Mf1103-1
MF1103/
MF1103-1
P1101A1
25011/
1103XA/
1103-1XA
1103-1K/
1103-11K
MC252G
NE102K*
7-21
MC253F
NE105G*
7-21
MC253G
NE105K*
7-21
MC254F
NE110G*
MC254G
NE110K*
MC255F
NE150G*
MC255G
NE150K*
7-57
MF1402A
2502B/1402A
7-57
1403A
2503TA/
7-57
MF1403A
2503TA/
7-57
1403A
1404A
2505K/
MF1403A
2503V
7-57
MC256F
NE115G*
MF1404A
2504TA/
7-57
MC256G
NEl15K*
1404A
2504V
MC257F
NS700G*
MF1404A
7-57
MC257G
NS700K
7-62
1405A
CS709K*
NE101G*
7-15
7-21
1405A
MC217G
MC251F
NE101 K*
1103-1 XA
7-57
CS709G*
NE102G*
2502B/1402A
2504TA/
CS705K*
MC217F
MC252F
1402A
1403A
MC215G
MC251G
7-45
C1101A1
P11031
1404A
SE110G*
SE110K*
SIGNETICS
C1103
SE105K*
MC204F
MC204G
MIL
C11031
MC203G
MC205F
1404A
PAGE
7-45
5-23
7-57
SIGNETICS
C1101A1
PAGE
7-32
INTEL
C1101A1
SIGNETICS
2502B/
IM7707
N82S29F
MOTOROLA
N2430Y
IM7706
N8225B
7-62
IM7702
7-57
1024
2512K
IM7603
2503TA/
0064
MM3412
N1068B
DL91403A
PAGE
7-68
SE101G*
2504V
SIGNETICS
2517T/1507
MC201F
IM7704CPA
HARRIS
7-68
MM3407
MC1068P
7-57
7-57
2506T/1506
7-32
2502B/1402A
1404A
2504V
MM3406
7-32
DL91402A
2504TA/
MM3405
N24101
IM7703CTA
7-57
1404A
N2420Y
7-21
DL91404A
2504TA/
IM7602
1103-1XA
1403A
MM3404
IM7601
1402A
AY51012
1403A
7-57
I
* Data sheet available upon request from Signetics.
8-33
\)IUI~t: I I\';:) II~UU:S
I HY GHUSS REFERENCE GUIDE
MOTOROLA
SIGNETICS
PAGE
MOTOROLA
SIGNETICS
PAGE
MOTOROLA
SIGNETICS
PAGE
2-60
MC258F
NS701G
MC3020P
N74H50A
2-206
MC5454F
55454J
MC258G
N5701K
MC3023P
N74H51A
2-207
MC5454L
S5454F
2-60
MC1004P
N1004A
MC3024P
N74H40A
2-205
MC5454P
55454A
2-60
5·11
MC1005P
N1005A
5·11
MC303P
N74H60A
2-215
MC5460F
55460J
2-62
MC1006P
N1006A
5·11
MC3031P
N74H52A
2-209
MC5460L
S5460F
2-62
MC1010P
N1010A
5·11
MC3032P
N74H53A
2-211
MC5460P
55460A
2-62
MC1011P
N1011A
5·11
MC3033P
N74H54A
2-211
MC5470L
55470F
2-66
MC1012P
N1012A
5·11
MC3034P
N74H55A
2-213
MC5470P
55470A
2-66
MC1013P
N1013A
5·11
MC3055P
N74H72A
2-227
MC5472F
55472J
2-68
MC1014P
N1014A
5·11
MC3063P
N74H73A
2-229
MC5472L
55472F
2-68
MC1015P
N1015A
5·11
MC3065P
N74H76B
2-233
MC5472P
55472A
2-68
2·70
MC1016P
N1016A
5·11
MC5400F
55400J
2-2
MC5473F
55473J
MC1017P
N1017A
5·11
MC5400L
55400F
2·2
MC5473L
S5473F
2·70
MC1024P
N1024A
5·11
MC5400P
55400A
2-2
MC5473P
55473A
2·70
MC1025P
N1025A
5·11
MC5401F
55401J
2-4
MC5475L
55475E
2·75
MC1027P
N1027A
5·11
MC5401L
55401F
2-4
MC5475P
55475B
2·75
MC1033P
N1033A
5·11
MC5401P
55401A
2-4
MC5476L
55476E
MC1039P
N1039B
5·11
MC5402F
554020
2-6
MC5476P
55476B
2·772·77
MC1160G
52004K/
7·26
MC5402F
554020
2-6
MC5480L
55480F
2·81
MC5402L
55402F
2-6
MC5480P
55480A
2·81
MC5402P
55402A
2-6
MC5483L
55483E
2·85
MC5403L
55403F
2-8
MC5483P
55483B
2·85
TM53002LR
MC1161G
52005K/
7·26
TM3003LR/
7·29
MC5403P
55403A
2-8
MC5490F
554900
2·94
MC1456G
N5556T
6~42
MC5404F
554040
2-10
MC5490L
55490F
2·94
MC1458G
N5558T
6·145
MC5404L
55404F
2-10
MC5490P
55490A
2·94
MC1458L
N55581
6·145
MC5404P
55404A
2-10
MC5491AL
55491F
2·96
MC1458P
N5558V
6·145
MC5405L
55405F
2·12
MC5491AP
55491 A
2·96
MC1556G
55556T
6·147
MC5405P
55405A
2-12
MC5492L
55492F
2·98
2·98
N2010K/
MC1558G
55558T
6·145
MC5410F
55410J
2·22
MC5492P
55492A
MC1558L
555581
6·145
MC5410L
55410F
2-22
MC5493L
55493F
2·100
MC1596G
55596K
6·147
MC5410P
55410A
2-22
MC5493P
55493A
2·100
MC1709CP
/.LA 709CA
6·97
MC5420F
55420J
2-28
MC5495L
55495F
2·104
MC1709CG
/.LA 709CT
6·97
MC5420L
55420F
2-28
MC5495P
55495A
2·104
MC1709F
/.LA7090
6·97
MC5420P
55420A
2-28
MC7400F
N7400J
2·2
MC1709G
/.LA709T
6·97
MC5430F
55430J
2-34
MC7400L
N7400F
2·2
MC1710CP
/.LA 71 OCA
6·99
MC5430L
55430F
2-34
MC7400P
N7400A
2·2
2-4
MC1710CG
/.LA 71 OCT
6·99
MC5430P
55430A
2-34
MC7401F
N74010
MC1710F
/.LA71 00
6·99
MC5440F
554400
2-38
MC7401L
N7401F
2-4
MC1710G
/.LA710T
6·99
MC5440L
55440F
2-38
MC7401P
N7401A
2-4
MC1711CP
/lA711CA
6·101
MC5440P
55440A
2-38
MC7402F
N7402Q
2-6
MC17115G
/lA711CK
6·101
MC542L
55442E
2-42
MC7402L
N7402F
2-6
MC1711G
/lA711K
6·101
MC5442P
55442B
2-42
MC7402P
N7402A
2-6
MC1741CP
/lA741CA
6·115
MC5443L
55443E
2-44
MC7403L
N7403F
2-8
MC1741CG
/lA741CT
6·115
MC5443P
55443B
2-44
MC7403P
N7403A
2-8
MC1741G
/lA741T
6·115
MC5444L
55444E
2-46
MC7404F
N7404Q
2-10
MC3000P
N74HOOA
2·183
MC5444P
55444B
2-46
MC7404L
N7404F
2-10
MC3004P
N74H01A
2·185
MC5445L
55445E
2-48
MC7404P
N7404A
2-10
MC3005P
N74H10A
2·193
MC5445P
55445B
2-48
MC7405L
N7405F
2-12
MC3006P
N74H11A
2·195
MC5450F
55450J
2-58
MC7405P
N7405A
2-12
MC3008P
N74H04A
2·187
MC5450L
55450F
2-58
MC7410F
N7410J
2-22
MC3009P
N74H05A
2·189
MC5450P
55450A
2-58
MC7410L
N7410F
2-22
MC3010P
N74H20A
2·197
MC5451F
55451J
2-58
MC7410P
N7410A
2-22
MC3011P
N74H21A
2·199
MC5451L
S5451F
2-58
MC7420F
N7420J
2-28
MC3012P
N74H22A
2·201
MC5451P
55451 A
2-58
MC7420L
N7420F
2-28
MC3016P
N74H30A
2·203
MC5453F
S5453J
2-60
MC7420P
N7420A
2-28
MC3018P
N74H62A
2·223
MC5453L
S5453F
2-60
MC7430F
N7430J
2-34
MC3019P
N74H61A
2·219
MC5453P
55453A
2-60
MC7430L
N7430F
2-34
8·34
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
MOTOROLA
SIGNETICS
PAGE
MOTOROLA
SIGNETICS
PAGE
NATIONAL
SIGNETICS
PAGE
MC7430P
N7430A
2-34
MC7493L
N7493F
2-100
DM5400N
S5400A
2-2
MC7440F
N7440Q
2-38
MC7493P
N7493A
2-100
DM5401N
S5401A
2-4
MC7440L
N7440F
2-38
MC7495L
N7495F
2-104
DM5402N
S5402A
2-6
MC7440P
N7440A
2-38
MC7495P
N7495A
2-104
DM5403N
S5403A
2-8
MC7441AL
N7441E
2-40
MC7520P
SN7520N
6-149
DM5404N
S5404A
2-10
MC7441AP
N7441B
2-40
MC7521P
SN7521N
6-149
DM5405N
S5405A
2-12
MC7442L
N7442E
2-42
MC7522P
SN7522N
6-149
DM5408N
S5408A
2-18
MC7442P
N7442B
2-42
MC7523P
SN7523N
6-149
DM5409N
S5409A
2-20
MC7443L
N7443E
2-44
MC7524P
SI\J7524N
6-149
DM5410N
S5410A
2-22
MC7443P
N7443B
2-44
MC7525P
SN7525N
6-149
DM5411N
S5411A
2-24
MC7444L
N7444E
2-46
MC7241P
N8241 A
3-31
DM5420N
S5420A
2-28
MC7444P
N7444B
2-46
MC7242P
N8242A
3-31
DM5430N
S5430A
2-34
MC7445L
N7445E
2-48
MC7250P
N8250A
3-39
DM5440N
S5440A
2-38
2-58
MC7445P
N7445B
2-48
MC7251P
N8251B
3-39
DM5450N
S5450A
MC7446L
N7446E
2-50
MC7261P
N8261A
3-49
DM5451N
S5451 A
2-58
MC7446P
N7446B
2-50
MC8312P
N8230B
3-22
DM5453N
S5453A
2-60
MC7447L
N7447E
2-50
MC8328P
N8217B
3-88
DM5454N
S5454A
2-60
MC7447P
N7447B
2-50
MC8301
N8252B
3-39
DM5460N
S5460A
2-62
MC7448L
N7448E
2-54
MC8601
N8T22A
3-159
DM5472N
S5472A
2-68
MC7448P
N7448B
2-54
MC8241P
S8241A
3-31
DM5473N
S5473A
2-70
MC7450F
N7450J
2-58
MC8242P
S8242A
3-31
DM5474N
S5474A
2-72
MC7450L
N7450F
2-58
MC8250P
S8250A
3-39
DM5475N
S5475B
2-75
MC7450P
N7450A
2-58
MC8251P
S8251B
3-39
DM5476N
S5476B
2-76
MC7451F
N7451J
2-58
MC8261P
S8261 A
3-49
DM5486N
S5486A
2-88
MC7451L
N7451F
2-58
MC9312P
S8230B
3-22
DM5490N
S5490A
2-94
MC7451P
N7451A
2-58
MC9228P
MC9328P
3-88
DM5492N
S5492A
2-98
MC7453F
N7453J
2-60
MC9601P
8T22A
3-159
DM5493N
S5493A
2-100
MC7453L
N7453F
2-60
MC10101L
10101F
5-26
DM54107N
S54107A
2-110
MC7453P
N7453A
2-60
MC10102L
10102F
5-28
DM7400N
N7400A
2-2
MC7454F
N7454J
2-60
MC10105L
10105F
5-30
DM7401N
N7401A
2-4
MC7454L
N7454F
2-60
MC10106L
10106F
5-32
DM7402N
N7402A
2-6
MC7454P
N7454A
2-60
MC10107L
10107F
5-34
DM7403N
N7403A
2-8
MC7460F
N7460J
2-64
MC10109L
10109F
5-36
DM7404N
N7404A
2-10
MC7460L
N7460F
2-64
MC10110L
10110F
5-38
DM7405N
N7405A
2-12
MC7460P
N7460A
2-64
MC10111L
10111F
5-40
DM7408N
N7408A
2-18
MC7470L
N7470F
2-66
MC10115L
10115F
5-46
DM7409N
N7409A
2-20
MC7470P
N7470A
2-66
Mciol16L
10116F
5-48
DM7410N
N7410A
2-22
MC7472F
N7472J
2-68
MC10117L
10117F
5-50
DM4711N
N7411A
2-24
MC7472L
N7472F
2-68
MC10118L
10118F
5-52
DM7420N
N7420A
2-28
MC7472P
N7472A
2-68
MC10119L
10119F
5-54
DM7426N
N7426A
2-32
MC7473F
N7473J
2-70
MC10121L
10121F
5-56
DM7430N
N7430A
2-34
MC7473L
N7473F
2-70
MC10124L
10124F
5-58
DM7440N
N7440A
2-38
MC7473P
N7473A
2-70
MC10125L
10125F
5-59
DM7441AN
N7441B
2-40
MC7475L
N7475E
2-75
MC10130L
10130F
5-60
DM7442N
N7442B
2-42
MC7475P
N7475B
2-75
MC10131 L
10131F
5-63
DM7446N
N7443B
2-44
MC7476L
N7476E
2-77
MC10132L
10132F
5-67
DM7447N
N7447B
2-50
MC7476P
N7476B
2-77
MC10133L
10133F
5-69
DM7448N
N7448B
2-54
MC7480L
N7480F
2-81
MC10134L
10134F
5-71
DM7450N
N7450A
2-58
MC7480P
N7480A
2-81
MC10136L
10136F
5-73
DM7451N
N7451A
2-58
MC7483L
N7483E
2-85
MC10137L
10137F
5-73
DM7453N
N7453A
2-60
MC7483P
N7483B
2-85
MC10160L
10160F
5-75
DM7454N
N7454A
2-60
MC7490F
N7490Q
2-94
MC10161L
10161F
5-76
DM7460N
N7460A
2-64
MC7490L
N7490F
2-94
MC10162L
10162F
5-78
DM7472N
N7472A
2-68
MC7490P
N7490A
2-94
MC10164L
10164F
5-80
DM7473N
N7473A
2-70
MC7491A
N7491F
2-96
MC10173L
10173F
5-87
DM7475N
N7475B
2-75
MC7491AP
N7A91 A
MC10174L
10174F
5-89
DM7476N
N7476B
2-77
MC7492L
N7492F
2-96
2-98
DM7483N
N7483B
2-85
MC7492P
N7492A
2-98
DM7486N
N7486A
2-88
8·35
I
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
NATIONAL
SIGNETICS
PAGE
NATIONAL
SIGNETICS
PAGE
NATIONAL
SIGNETICS
PAGE
2517/1507
7-6S
DM7490N
N7490A
2-94
DM8601N
N8T22A
3-159
MM507
DM7492N
N7492A
2-98
DM8680N
NS280A
3-90
MM5210
N25101
7-73
DM7493N
N7493A
2-100
DM8681N
N82S1A
3-90
MM1101A!
2501B6
DM7495N
N7495A
2-104
DM8688N
NS288A
3-100
MM1101A-1
P1101A1
7-45
7-15
DM7496N
N7496B
2-'106
DM8840N
N7441B
2-40
MM1103
1103XA/
7-15
DM74107N
N74107A
DM8842N
N7442B
2-42
DM8S50N
N8T22A
3-159
DM88SON
DMS880N
6-161
11031XA
DM74153N
N74153B
2-110
"'2-128
DM74154N
N74154N
2-130
DM74HOON
N74HOOA
2-183
LH740ACH
#lA740CT
6-113
DM74H01N
N74H01A
2-185
LH740AH
#lA740T
6-113
DM74H04N
N74H04A
2-187
LM101AH
LM101AH
6-164
DM74H05N
N74H05A
2-189
LM101H
LM101H
6-169
DM74HOSN
N74H08A
2-191
LM101AF
LM101AF
6-164
MM5013H
2512K
7-62
DM74H10N
N74H10A
2-193
LM101AD
LM101AD
6-164
MM5013N
2525V
7-10S
DM74H11N
N74H11A
2-195
LM107H
LM107H
6-169
MM5220
N2420Y
7-32
DM74H20N
N74H20A
2-197
LM107F
LM107F
6-175
MM5230
N2430Y
7-32
DM74H21N
N74H21A
2-199
LM107D
LM107D
6-175
MM5221
N2451 1
7-39
DM74H22N
N74H22A
2-201
LM109H
S5109T
6-179
MM5231
N2461 1
7-39
DM74H30N
N74H30A
2-203
LM201AH
LM201AH
6-164
MM1402A
2502B/
7-57
1402A
MM1403A
2503TA/
7-57
1403A
MM1404A
2504TA!
7-57
1404A
DM74H40N
N74H40A
2-205
LM201D
LM201D
6-169
DM74H50N
N74H50A
2-206
LM201H
LM201H
6-169
RAYTHEON
SIGNETICS
PAGE
DM74H51N
N74H51A
2-207
LM201N
LM201N
6-169
RC101AT
LM301AH
6-164
DM74H53N
N74H53A
2-211
LM201AH
LM201AH
6-164
RC101T
LM201H
6-169
DM74H54N
N74H54A
2-211
LM201AF
LM201AF
6-164
RC107T
LM307H
6-175
DM74H55N
N74H55A
2-213
LM301AH
LM301AH
6-164
. RC709T
#lA709CT
6-97
DM74H60N
N74H60A
2-217
LM301AN
LM301AN
6-164
RC710T
#lA71 OCT
6-99
DM74H62N
N74H62A
2-223
LM307H
LM307H
6-175
RC711T
#lA711CK
6-101
DMSOOON
N7400A
2-2
LM307N
LM307N
6-175
RC733T
#lA733CK
6-10S
DMS001N
N7410A
LM309H
LM309H
6-179
RC741T
#lA741CT
6-115
DMS050N
N7450A
DMS051N
N7451 A
2-22
2-6
2-8
2-10
2-22
2-28
2-34
2-38
2-58
2-58
DMS053N
N7453A
2-60
LM711CN
#lA711CA
6-101
RC8250
8250
3-39
DMS054N
N7454A
2-60
LM711H
#lA711K
6-101
RC8251
8251
3-39
DMS060N
N7450A
2-58
LM723CH
#lA723CL
6-103
RC8252
8252
3-39
DMS086N
N7486A
LM723CN
#lA723CA
6-103
RCS260
8260
3-43
DMS200N
N8269A
LM723H
#lA723L
6-103
RCS261
8261
3-49
DMS213N
N74154N
LM741CH
#lA741CT
6-115
RC8263
8263
3-57
DmS2S0N
N8280A
LM741CN
#lA741CV
6-115
RC8264
8264
3-57
LM741H
#lA741T
6-115
RC8266
8266
3-63
LM748CH
#lA74SCT
6-124
RCS267
8267
3-63
DMS002N
N7402A
DMSOO3N
N7403A
DMSOO4N
N7404A
DMS010N
N7410A
DMS020N
N7420A
DMS030N
N7430A
DMS040N
N7440A
LM309K
LM309K
6-179
RC8200
8200
3-16
LM709CH
#lA709CA
6-97
RC8021
8201
3-16
LM709F
#lA709G
6-97
RC8202
S202
3-16
LM709H
#lA709T
6-97
RC8203
8203
3-16
LM710CN
#lA710CA
6-99
RC8233
8233
3-26
LM710CH
#lA71 OCT
6-99
RC8234
S234
3-26
LM710F
#lA710G
6-99
RC8241
8241
3-31
LM710H
#lA710T
6-99
RCS242
S242
3-31
LM711CH
#lA711CK
6-101
RC8243
8243
3-35
DMS2S1N
N8281 A
DM8288N
N8288A
2-88
3-71
2-130
3-90
3-90
. 3-100
DM82S3N
N7483B
2-85
LM748H
#lA748T
6-124
RC8270
8270
3-73
DMS500N
N7476B
LM1458H
N5558T
6-145
RC8271
8271
3-73
DM8501N
N7473A
LM1458N
N555aV
6-145
RCS273
8273
3-79
DM8510N
N7474A
LM155SH
S5558T
6-145
RC8274
8274
3-S0
DMS530N
N7490A
LM7520N
SN7520N
6-149
RC82S0
82S0
3-90
DM8532N
N7492A
LM7521N
Sn7521N
6-149
RC8281
82S1
3-90
DM8533N
N7493A
LM7522N
SN7522N
6-149
RCS290
8290
3-106
DM8550N
N7475B
2-77
2-70
2-72
2-94
2-98
2-100
2-75
2-166
2-170
2-104
LM7523N
SN7523N
6-149
RC8291
8291
3-106
LM7524N
SN7524N
6-149
RCST09
8T09
3-132
LM7525N
SN7525N
2506T/1506
6-149
RC8T10
8T10
3-136
7-68
RC8T13
8T13
3-140
DM8560N
N74192B
DM8563N
N74193B
DMS580N
N7495A
8·36
MM506
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
RAYTHEON
SIGNETICS
PAGE
T.I.
SIGNETICS
PAGE
T.I.
SIGNETICS
PAGE
RC8T14
8T14
3·143
SN52558L
S5558T
6·145
SN5440S
S5440J
2·38
RC8T23
8T23
3·l61
SN72709F
p.A7090
6·97
SN5442J
S5442E
2-42
RC8T24
8T24
3~165
SN52709L
J.LA709T
6·97
SN5442N
S5442B
2-42
RL709T
p.A709CT
6·97
SN52710F
p.A71 00
6·99
SN5443J
S5443E
2-44
RL711T
p.A711K
6·101
SN52710L
p.A710T
6·99
SN5443N
S5443B
2-44
RL733T
p.A733CK
6·108
SN52711L
p.A711K
6·101
SN5444J
S5444E
2-46
RL101T
LM201H
6·169
SN52741L
p.A741T
6·115
SN5444N
S5444B
2-46
RM7090
p.A7090
6·97
SN5400J
S5400F
2·2
SN5445N
S5445E
2-48
RM709T
p.A709T
6·97
SN5400N
S5400A
2·2
SN5450J
S5450F
2·58
RM711T
p.A711K
6·101
SN5400S
S5400J
2·2
SN5450N
S5450A
2·58
RM733T
p.A733K
6·108
SN5401J
S5401F
2-4
SN5451J
S5451F
2·58
RM741T
p.A741T
6·115
SN5401N
S5401A
2-4
SN5451N
S5451 A
2·58
RM101T
LM101H
6·169
SN5401S
S5401J
2-4
SN5453J
S5453F
2-60
SG710CN
p.A710CA
6·99
SN5402J
S5402F
2-6
SN5453N
S5453A
2-60
SG710CT
p.A71 OCT
6·99
SN5402N
S5402A
2-6
SN5453S
S5453R
2-60
SG710T
p.A710T
6·99
SN5402S
S5402J
2-6
SN5454J
S5454F
2-60
SN5403J
S5403F
2·8
SN5454N
S5454A
2-60
SN5403N
S5403A
2·8
SN5454S
S5454R
2-60
SILICON GEN'L
SIGNETICS
PAGE
SN5403S
S5403J
2·8
SN5460J
S5460F
2-62
SG101AT
LM101AH
6·164
SN5404J
S5404F
2·10
SN5460N
S5460A
2-62
SG101T
LM101H
6·169
SN5404N
S5404A
2·10
SN5460S
S5460R
2-62
SG107T
LM107H
6·175
SN5404S
S5404J
2·10
SN5470J
S5470F
2-66
SG201AT
LM201AH
6·164
SN5405J
S5405F
2·12
SN5470N
S5470A
2-66
SG201N
LM201D
6·169
SN5405N
S5405A
2·12
SN5470S
S5470R
2-66
SG201T
LM201H
6·169
SN5405S
S5405J
2'12
SN5472J
S5472
2-68
SG301AN
LM301AV
6·164
SN5406J
S5406F
2·14
SN5472N
S5472
2-68
SG301AT
SG301AH
6·164
SN5406N
S5406A
2·14
SN5473J
S5473F
2·70
SG307T
LM307H
6·175
SN5406S
S5406J
2·14
SN5473N
S5473A
2·70
SG709CN
J.LA709CA
6·97
SN5407J
S5407F
2·16
SN5473S
S5473R
2·70
SG709CT
p.A709CT
6·97
SN5407N
S5407A
2·16
SN5474J
S5474F
2·72
SG709T
p.A709T
6·97
SN5407S
S5407J
2·16
SN5474N
S5474A
2·72
SG710CN
p.A710CA
6·99
SN5408J
S5408F
2·18
SN5474S
S5474R
2·72
SG710CT
p.A71 OCT
6·99
SN5408N
S5408A
2·18
SN5475J
S5475E
2·75
SG710T
p.A710T
6·99
SN5408S
S5408J
2·18
SN5475N
S5475B
2·75
SG711CN
p.A711CA
6·101
SN5409J
S5409F
2·20
SN5476J
S5476E
2·77
SG711CT
p.A711CK
6·101
SN5409N
S5409A
2·20
SN5476N
S5476B
2·77
SG711T
p.A711K
6·101
SN5409S
S5409J
2·20
SN5477J
S5477
2·79
SG723CN
p.A723CA
6·103
SN5410J
S5410F
2·22
SN5477N
S5477
2·79
SG723CT
p.A723CL
6·103
SN5410N
S5410A
2·22
SN5480J
S5480F
2·81
SG723T
J.LA723L
6·103
SN5410S
S5410J
2·22
SN5480N
S5480A
2·81
SG733CN
p.A733CA
6·108
SN5416J
S5416F
2·14
SN5480S
S5480J
2·81
SG733CT
p.A733CK
6·108
SN5416N
S5416A
2·14
SN5483J
S5483E
2·85
SG733T
p.A733K
6·108
SN5416S
S5416J
2·14
SN5483N
S5483B
2·85
2·85
SG741CN
p.A741CA
6·115
SN5417J
S5417F
2·16
SN5483S
S5483R
SG741CT
p.A741CT
6·115
SN5417N
S5417A
2·16
SN5486J
S5486F
2·88
SG741T
p.A741T
6·115
SN5417S
S5417J
2·16
SN5486N
S5486A
2·88
SG748CT
p.A748CT
6·124
SN5420J
S5420F
2·28
SN5486S
S5486J
2·88
SG748T
p.A748T
6·124
SN5420N
S5420A
2·28
SN5488N
S8224B
4·11
SG1496N
S55961
6·147
SN5420S
S5420J
2·28
SN5488S
S8224R
4·11
SG1496T
N5596K
6·147
SN5426J
S5426F
2·32
SN5489N
S8225B
4·15
SG1596T
S5596K
6·147
SN5426N
S5426A
2·32
SN5489S
S8225R
4·15
SG7520N
SN7520N
6·149
SN5430J
S5430F
2·34
SN5490J
S5490F
2·94
SG7521N
SN7521N
6·149
SN5430N
S5430A
2·34
SN5490N
S5490A
2·94
SG7522N
SN7522N
6·149
SN5430S
S5430J
2·34
SN5490S
S5490J
2·94
SG7523N
SN7523N
6·149
SN5438J
S5438
2·36
SN5491AJ
S5491F
2·96
SG7524N
SN7524N
6·149
SN5438
S5438
2·36
SN5491AN
S5491 A
2·96
SG7525N
SN7525N
6·149
SN5440J
S5440F
2·38
SN5491AS
S5491 0
2·96
SN5440N
S5440A
2·38
SN5492J
S5492F
2·98
8-37
I
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
SIGNETICS
PAGE
T."
SIGNETICS
PAGE'
T."
SIGNETICS
PAGE
SN5492N
S5492A
2-98
SN54H01S
S54H01Q
2-185
SN54H71J
S54H71
2-225
SN5492S
S5492J
2-98
SN54H04J
S54H04F
2-187
SN54H71N
S54H71
2-225
SN5493J
S5493F
2-100
SN54H04N
S54H04A
2-187
SN54H72J
S54H72F
2-227
T.I.
SN5493N
S5493A
2-100
SN54H04S
S54H04Q
2-187
SN54H72N
S54H72A
2-227
SN5493S
S5493J
2-100
SN54H05J
S54H05F
2-189
SN54H72S
S54H72Q
2-227
SN5494J
S5494E
2-102
SN54H05N
S54H05A
2-189
SN54H73J
S54H73F
2-229
SN5494N
S54948
2-102
SN54H05S
S54H05Q
2-189
SN54H73N
S54H73A
2-229
SN5495J
S5495F
2-104
SN54H08J
S54H08F
2-191
SN54H73S
S54H7SQ
2-229
SN5495N
S5495A
2-104
SN54H08N
S54H08A
2-191
SN54H74J
S54H74F
2-231
SN5495S
S5495J
2-104
SN54H08S
S54H08Q
2-191
SN54H74N
S54H74A
2-231
S5496J
S5496E
2-106
SN54H10J
S54H10F
2-193
SN54H74S
S54H74Q
2-231
SN5496N
S54968
2-106
SN54H10N
S54H10A
2-193
SN54H76J
S54H76E
2-233
SN54101J
S54101F
2-22
SN54H10S
S54H10Q
2-193
SN54H76N
S54H768
2-233
SN54101N
S54101A
2-22
SN54H11J
S54H11 F
2-195
SN72558P
N5558V
6-145
SN54107N
S54107A
2-22
SN54H11N
S54H11A
2-195
SN72709L
J,LA709CT
6-97
SN54121J
S54121 F
2-112
SN54H11S
S54H11Q
2-195
SN72709N
J,LA709CA
6-97
SN54121N
S54121A
2-112
SN54H20J
S54H20F
2-197
SN72710L
J,LA71 OCT
6-99
SN54123J
S54123
2-116
SN54H20N
S54H20A
2-197
SN72710N
J,LA710CA
6-99
SN54123N
S54123
2-116
SN54H20S
S54H20Q
2-197
SN72711L
J,LA711CK
6-101
SN54145N
S541458
2-48
SN54H21J
S54H21 F
2-199
SN72722N
J,LA711CA
6-101
SN54150N
S54150N
2-121
SN54H21N
S54H21A
2-199
SN72741 L
J,LA741CT
6-115
SN54151N
S541518
2-123
SN54H21S
S54H21Q
2-199
SN72741 L
J,LA741T
6-115
SN54151S
S54151R
2-123
SN54H22J
S54H22F
2-201
SN72741N
J,LA741CA
6-115
SN54152N
S54152A
2-125
SN54H22N
S54H22A
2-201
SN72741P
J,LA741CV
6-115
SN54153N
S541538
2-128
SN54H22S
S54H22Q
2-201
SN7400J
N7400F
2-2
SN54154N
S54154N
2-130
SN54H30J
S54H30F
2-203
SN7400N
N7400A
2-2
SN54157N
S541578
2-136
SN54H30N
S54H30A
2-203
SN7400S
N7400J
2-2
SN54164J
S54164
2-144
SN54H30S
S54H30J
2-203
SN7401J
N7401F
2-4
SN54164N
S54164
2-144
SN54H40J
S54H40F
2-205
SN7401N
N7401A
2-4
SN54166N
S541668
2-149
SN54H40N
S54H40A
2-205
SN7401S
N7401J
2-4
SN54176J
S8280F
3-90
SN54H40S
S54H40Q
2-205
SN7402J
N7402F
2-6
SN54176N
S8280A
3-90
SN54H50J
S54H50F
2-206
SN7402N
N7402A
2-6
SN54176S
N8280Q
3-90
SN54H50N
S54H50A
2-206
SN7402S
N7402J
2-6
SN54177J
S8281F
3-91
SN54H50S
S54H50Q
2-206
SN7403J
N7403F
2-8
SN54177N
S8281 A
3-91
SN54H51J
S54H51F
2-207
SN7403N
N7403A
2-8
SN54177S
S8281Q
3-91
SN54H51N
S54H51 A
2-207
SN7403S
N7403J
2-8
SN54178J
S8270F
3-73
SN54H51S
S54H51Q
2-207
SN7404J
N7404F
2-10
SN54178N
S8270A
3-73
SN54H52J
S54H52F
2-209
SN7404N
N7404A
2-10
SN54179J
S8271E
3-73
SN54H52N
S54H52A
2-209
SN7404S
N7404J
2-10
SN54179N
S82718
3-73
SN54H52S
S54H52Q
2-209
SN7405J
N7405F
2-12
SN54180J
S54180F
2-158
SN54H53J
S54H53F
2-211
SN7405N
N7405A
2-12
SN54180N
S54180A
2-158
SN54H53N
S54H53A
2-211
SN7405S
N7405J
2-12
SN54181N
S54181N
2-160
SN54H53S
S54H53J
2-211
SN7406J
N7406F
2-14
SN54182N
S541828
2-164
SN54H54J
S54H54F
2-211
SN7406N
N7406A
2-14
SN54192J
S54192E
2-166
SN54H54N
S54H54A
2-211
SN7406S
N7406J
2-14
SN54192N
S541928
2-166
SN54H54S
S54H54J
2-211
SN7407J
N7407F
2-16
SN54193J
S54193E
2-170
SN54H55J
S54H55F
2-213
SN7407N
N7407A
2-16
SN54193N
S541938
2-170
SN54H55N
S54H55A
2-213
SN7407S
N7407J
2-16
SN54195N
S541958
2-176
SN54H55S
S54H55J
2-213
SN7408J
N7408F
2-18
SN54196N
S8290A
3-106
SN54H60J
S54H60F
2-215
SN7408N
N7408A
2-18
SN54197N
S8291A
3-106
SN.54H60N
S54H60A
2-215
SN7408S
N7408J
2-18
SN54198N
S541988
2-178
SN54H60S
S54H60J
2-215
SN7409J
N7409F
2-20
SN54199N
S541998
2-180
SN54H61J
S54H61F
2-219
SN7409N
N7409A
2-20
SN54HOOJ
S54HOOF
2-183
SN54H61N
S54H61 A
2-219
SN7409S
N7409J
2-20
SN54HOON
S54HOOA
2-183
SN54H61S
S54H61J
2-219
SN7410J
N7410F
2-22
SN54HOOS
S54HOOQ
2-183
SN54H62J
S54H62F
2-221
SN7410N
N4710A
2-22
SN54H01J
SN54H01N
S54H01F
S54H01A
2-185
2-185
SN54H62N
S54H62A
2-221
SN7410S
N7410J
2-22
SN54H62S
S54H62J
2-221
SN7416J
N4716F
2-14
13-38
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
T. I.
SIGNETICS
PAGE
T.!.
SIGNETICS
PAGE
T.1.
SN7416N
N7416A
2·14
SN7476J
N7476F
2·76
SN7416S
N7416J
2·14
SN7476N
N7476B
2·76
SN7417J
N7417F
2·16
SN7480J
N7480F
SN7417N
N7417A
2·16
SN7480N
SN7417S
N7417J
2·16
SN7420J
N7420F
SN7420N
SIGNETICS
PAGE
SN74176S
N8280Q
3·90
SN74177J
N8281F
3·90
2·81
SN74177N
N8281A
3·90
N7480A
2·81
SN74177S
N8281Q
3·90
SN7480S
N7480J
2·81
SN74178J
N8270F
3·73
2·28
SN7483J
N7483E
2·85
SN74178N
N8270A
3·73
N7420A
2·28
SN7483N
N7483B
2·85
SN74179J
N8271 E
3·73
SN7420S
N7420J
2·28
SN7483S
N7483R
2·85
SN74179N
N8271B
3·73
SN7426J
N4726F
2·32
SN7486J
N7486F
2·88
SN74180J
N74180F
2·158
SN7426N
N7426A
2·32
SN7486N
N7486A
2·88
SN74180N
N74180A
2·158
SN7430J
N7430F
2·34
SN7486S
N7486J
2·88
SN74181N
N74181 N
2·160
SN7437N
N7437A
2·36
SN7488N
N8224B
4·11
SN74182N
N74182B
2·164
SN7438N
N7438A
2·36
SN7488S
N8224R
4·11
SN74192J
N74192E
2·166
SN7430N
N7430A
2·34
SN7489N
N8225B
4·15
SN74192N
N74192B
2·166
SN7430S
N7430J
2·34
SN7489S
N8225R
4·15
SN74193J
N74193E
2·170
SN7440J
N7440F
2·38
SN7490J
N7490F
2·94
SN74193N
N74193B
2·170
SN7440N
N7440A
2·38
SN7490N
N7490A
2·94
SN74194N
N74194A
2·174
SN7440S
N7440J
2·38
SN7490S
N7490J
2·94
SN74H71N
N74H71A
2·225
SN7441AJ
N7441E
2-40
SN7491AJ
N7491F
2·96
SN74195N
N74195B
2·176
SN7441AN
N7441B
2-40
SN7491AN
N7491A
2·96
SN74196N
N8290A
3·106
SN7442J
N7442E
2·42
SN7491AS
N7491Q
2·96
SN74197N
N8291A
3·106
SN7442N
N7442B
2-42
SN7492J
N7492F
2·98
SN74198N
N74198N
2·178
SN7443J
N7443E
2-44
SN7492N
N7492A
2·98
SN74199N
N74199N
2·180
SN7443N
N7443B
2-44
SN7492S
N7492J
2·98
SN74HOOJ
N74HOOF
2·183
SN7444J
N7444E
2-46
SN7493J
N7493F
2·100
SN74HOON
N74HOOA
2·183
SN7444N
N7444B
2-46
SN7493N
N7493A
2·100
SN74HOOS
N74HOOQ
2·183
SN7445N
N7445B
2-48
SN7493S
N7493J
2·100
SN74H01J
N74H01F
2·185
SN7446N
N7446B
2·50
SN7494J
N7494E
2·102
SN74H01N
N74H01A
2·185
SN7447J
N7447E
2·50
SN7494N
N7494B
2·102
SN74H01S
N74H01Q
2·185
SN7447N
N7447B
2·50
SN7495J
N7495F
2·104
SN74H04J
N74H04F
2·187
SN7448J
N7448E
2·54
SN7495N
N7495A
2·104
SN74H04N
N74H04A
2·187
SN7448N
N7448B
2·54
SN7496J
N7496E
2·106
SN74H04S
N74H04Q
2·187
SN7450J
N7450F
2·58
SN7496N
N7496B
2·106
SN74H05J
N74H05F
2·189
SN7450N
N7450A
2·58
SN74100J
N74100F
2·108
SN74H05N
N74H05A
2·189
SN7451J
N7451F
2·58
SN74100N
N74100A
2·108
SN74H05S
N74H05Q
2·189
SN7451N
N7451A
2·58
SN74107N
N74107A
2·110
SN74H08J
N74H08F
2·191
SN7453J
N7453F
2-60
SN74121J
N74121F
2·112
SN74H08N
N74H08A
2·191
SN7453N
N7453A
2-60
SN74121N
N74121A
2·112
SN74H08S
N74H08Q
2·191
SN7453S
N7453R
2-60
SN74122J
N74122F
2·116
SN74H10J
N74H10F
2·193
SN7454J
N7454F
2-60
SN74122N
N74122A
2·116
SN74H10N
N74H10A
2·193
SN7454N
N7454A
2-60
SN74123J
N74123F
2·116
SN74H10S
N74H10Q
2·193
SN7454S
N7454R
2-60
SN74123N
N74123A
2·116
SN74H11J
N74H11F
2·195
SN7460J
N7460F
2-64
SN74141J
N47141E
2·119
SN74H11N
N74H11A
2·195
SN7460N
N7460A
2-64
SN74141N
N74141B
2·119
SN74H11S
N74H11Q
2·195
SN7460S
N7460R
2-64
SN74145N
N74145B
2-48
SN74H20J
N74H20F
2·197
SN7470J
N7470F
2-66
SN74150N
N74150N
2·121
SN74H20N
N74H20A
2·197
SN7470N
N7470A
2-66
SN74151N
N74151B
2·123
SN74H20S
N74H20Q
2·197
SN7470S
N7470R
2-66
SN74151S
N74151R
2·123
SN74H21J
N74H21 F
2·199
SN7472J
N7472F
2-68
SN74152N
N74152A
SN47H21N
N74H21A
2·199
SN7472N
N7472A
2-68
SN74153N
N74153B
2·128
SN74H21S
N74H21Q
2·199
SN7472S
N7472R
2-68
SN74154N
N74154N
2·130
SN74H22J
N74H22F
2·201
SN7473T
N7473F
2·70
SN74157N
N74157B
2·136
SN74H22N
N74H22A
2·201
SN7473N
N7473A
2·70
SN74164J
N74164F
2·144
SN74H228
N74H22Q
2·201
SN7474J
N7474F
2·72
SN74164N
N74164A
2·144
SN74H30J
N74H30F
2·230
SN7474N
N7474A
2·72
SN74165N
N74165B
2·147
SN74H30N
N74H30A
2·203
SN7474S
N7474R
2·72
SN74166N
N74166B
2·149
SN74H30S
N74H30J
2·203
SN7475J
N7475E
2·75
SN74176J
N8280F
3·90
SN74H40J
N74H40F
2·205
SN7475N
N7475B
2·75
SN74176N
N8280A
3·90
SN74H40N
N74H40A
2·205
8·39
SIGNETICS INDUSTRY CROSS REFERENCE GUIDE
T.I.
SIGNETICS
PAGE
T.I.
SIGNETICS
PAGE
SN74H40S
N74H40Q
2-205
SN74S65N
N74S65A
2-260
SN74H50J
N74H50F
2-206
SN74S140N
N74S140A
2-258
SN74H50N
N74H50A
2-206
SN74S151N
N74S151B
2-270
SN74H50S
N74H50Q
2-206
SN74S~53N
N74S153B
2-273
SN74H51J
N74H51F
2-207
SN74S157N
N74S157B
2-276
SN74H51N
N74H51A
2-207
SN74S158
N74S158B
2-276
SN74H51S
N74H51Q
2-207
SN74S174N
N74S174B
2-278
SN74H52J
N74H52F
2-209
SN74S175N
N74S175B
2-278
SN74H52N
N74H52A
2-209
SN74S181N
N74S181N
2-281
.SN74H52S
N74H52Q
2-209
SN74S194N
N74S194B
2-284
SN74H53J
N74H53F
2-211
SN7520N
N7520N
6-149
SN74H53N
N74H53A
2-211
SN7521N
N7521N
6-149
SN74H53S
N74H53J
2-211
SN7522N
N7522N
6-149
SN74H54J
N74H54F
2-211
SN7523N
N7523N
6-149
SN74H54N
N74H54A
2-211
SN7524N
N7524N
6-149
SN74H54S
N74H54J
2-211
SN7525N
N7525N
6-149
SN74H55J
N74H55F
2-213
TMS2600
N2430Y
7-196
SN74H55N
N74H55A
2-213
TMS2800JC, NC
N24101
7-32
SN74H55S
N74H55J
2-213
TMS1103JC
1103-IK/
SN74H60J
N74H60F
2-217
1103-11K
TMSll03NC
1103XA/
7-15
7-21
7-15
SN74H60N
N74H60A
2-217
SN74H60S
N74H60J
2·217
SN74H61J
N74H61F
2-219
TMS300LR
S2002K
SN74H61N
N74H61A
2-219
TMS3001LR
S2003K
7-26
SN74H61S
N74H61J
2-219
TMS3002LR
S2004K
7-26
SN74H62J
N74H62F
2-223
TMS3003LR
S2005K
7-26
SN74H62N
N74H62A
2-223
TMS3406LM
S2505T
7-62
SN74H62S
N74H62J
2-223
TMS3407LM
S2517T
7-68
SN74H72J
N7472F
2-68
TMS3409JC, NC
S2532B
7-127
SN74H72N
N74H72A
2-227
TMS3412NC
S2502B
7-57
SN74H72S
N74H72Q
2-227
TMS3413LC
S2503TA
7-57
SN74H73J
N74H73F
2-229
TMS3414LC
S2504TA
7-57
SN74H73N
N74H73A
2-229
SN75324
N75324
1103-1XA
7-21
7-26
SN74H73S
N74H73Q
2-229
SN75450N
N75450N
6-157
SN74H74J
N74H74F
2-231
SN75450AN
N75450AN
6-157
SN74H74N
N74H74A
2-231
SN75451N
N75451N
6-159
SN74H74S
N74H74Q
2-231
SN75451AN
N75451AN
6-159
SN74H76J
N74H76E
2-233
SN74H76N
N74H76B
2-233
SN74Hl01N
N74Hl01
2-235
SN74Hl02N
N74H102B
2-237
SN74Hl03N
N74Hl03B
2-239
SN74Hl06N
N74Hl06B
2-241
SN74Hl08N
N74Hl08B
2-244
SN74S00N
N74S00A
2-247
SN74S03N
N74S03A
2-247
SN74S04N
N74S04A
2-249
SN74S05N
N74S05A
2-249
SN74S10N
N74S10A
2-251
SN74S11N
N74S11A
2-253
SN74S112N
N74S112B
2-264
SN74S113N
N74S113B
2-266
2-266
SN745114N
N74S114B
SN74S15N
N74S15A
2-253
SN74S20N
N74S20A
2-254
SN74S22N
N74S22A
2-256
SN74S40N
N74S40A
2-258
SN74S65N
N74S64A
2-260
8-40
SIGNETICS~
811 EAST ARQUES AVENUE
SUNNYVALE, CALIF. 94086
TEL: (408) 739-7700
TWX: (910) 339-9283
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer : Adobe Acrobat 9.31 Paper Capture Plug-in
Modify Date : 2010:03:24 23:38:57-08:00
Create Date : 2010:03:24 23:38:57-08:00
Metadata Date : 2010:03:24 23:38:57-08:00
Format : application/pdf
Document ID : uuid:f0247036-58e9-4efb-8adb-93cf141901d9
Instance ID : uuid:0ea42d4e-378f-4262-a940-827c73b27718
Page Layout : SinglePage
Page Mode : UseOutlines
Page Count : 1123
EXIF Metadata provided by EXIF.tools
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