1973_Bipolar_Memory 1973 Bipolar Memory

User Manual: 1973_Bipolar_Memory

Open the PDF directly: View PDF PDF.
Page Count: 73

Download1973_Bipolar_Memory 1973 Bipolar Memory
Open PDF In BrowserView PDF
BIPOLAR
MEMORIES

TABLE OF CONTENTS

8204/8205

2048 (256X8 ROM) 4096 (512X8 ROM) Bit Bipolar ROM

2

8220

8-Bit Content Addressable Memory (4X2 CAM)

4

8223

256-Bit Bipolar Field-Programmable ROM (32X8 PROM)

9

8225

64-Bit Bipolar Scratch Pad Memory (16X4 RAM)

12

8228

4096-Bit Bipolar ROM (1024X4 ROM)

15

82S06/82S07

256-Bit Bipolar RAM (256X1 RAM)
(82S06 Tri-8tate) (82S07 Open Collector)

17

82S12/82S112

High Speed Multiport Memory (8X4 Multiport RAM)

19

82S 16/82S 17

256-Bit Bipolar RAM (256X1 RAM)
(82S16 Tri-8tate) (82S17 Open Collector)

21

82S21

64-Bit Bipolar High Speed Write-Read RAM (32X2 RAM)

23

82S23/82S 123

256-Bit Bipolar Programmable ROM (32X8 PROM)
(82S23 Open Collector) (82S123 Tri-8tate)

26

82S26/82S29

1024-Bit Bipolar Programmable ROM (256X4 PROM)

29

10139

ECl High Performance 256-PROM

33

10140/10148/10151

ECl64X1 RAMS -30 to +85°C Cerdip

37

10145

ECl 16X4 RAM

40

Customer Ordering Information

44

COPYRIGHT 1973
SIGNETICS CORPORATION

Signetics Corporation reserves the right to make changes in the products
contained in this book in order to improve design or performance and to
supply the best possible product.
Signetics Corporation assumes no responsibility for the use of any circuits
described herein and makes no representations that they are free from
patent infringement.

ABSOLUTE MAXIMUM RATINGS*
CHARACTERISTICS

SYMBOL

RATING

UNIT

-60 to +150

DC

TTL MEMORIES
Storage Temperature

TSTG

Output and Supply
Voltages

VOUT, VCC

-0.5 to +6.0

V

Input Voltages

VIN

-0.5 to +6.0

V

Output Currents

lOUT

100

mA

liN

-30 to +30

mA

VEE

-8

Vdc

VIN

o to VEE

Vdc

50
100

mAdc
mAdc

Input Currents

Eel MEMORIES
Power Supply Voltage
(VCC = 0)
Input Voltage (VCC

= 0)

Output Source Current
Continuous
Surge

10

Storage Temperature
Range

T stg

-54 to+175

DC

Operating Junction
Temperature

TJ

125

DC

Operating Temperature
Range

TA

-30 to +85

DC

Power Supply Regulation
Required

±10%

*These ratings do not imply that the device will function or meet
the specified parameters at the levels indicated. They do, however,
indicate those levels at which permanent damage and/or parameter
degradation could occur. Exposure to these levels over extended
periods of time could affect reliability and should, therefore, be
avoided.

1

2048 BIT BIPOLAR ROM (256x8 ROM)
4096 BIT BIPOLAR ROM (512x8 ROM)

Si!)DlltiCS

8204
8205

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION
Refer to back of Bipolar Memory section for ASCII
(ADDRESS) to EBCDIC (DATA) and EBCDIC (ADDRESS) to ASCII (DATA) and ORDERING BLANKS.

The 8205 and 8204 are high performance bipolar ROM's
incorporating the storage output or memory data register
into the chip. Data is addressed by applying address information to the address lines. After val id data appears at the
output of the memory array, (typically 35ns after the address is applied) and if the circuit is enabled, the strobe
pulse will enter data into the 8 bit output latch register. A
D-type latch (L) is used to enable the tri-state output
drivers. If the circuit enable signals are valid, the strobe
will set the latch. This turns on the output stage. The
latch will remain set and keep the output enabled until the
chip is disabled and the next strobe pulse occurs. If the
strobe line is held high, the ROM will function in a conventional mode. The output will be controlled solely by the
chip enable and the output latches will be bypassed.

FEATURES
• BUFFERED ADDRESS LINES
• ON THE CHIP DECODING
• ON THE CHIP STORAGE LATCHES
• TRI-STATE OUTPUT
• PROTECTED INPUTS

APPLICATIONS
MICROPROGRAMMING
HARDWIRE ALGORITHMS
CHARACTER GENERATION
CONTROL STORE

BLOCK DIAGRAM
8204 (256x8) AND 8205 (512x8) MEMORY ORGANIZATION
Address Pins

AOo-----I
ADDRESS LINES

8204 8205

512,,8 OR 256,,8
ROM

DECODE

An o---~

1181

STROBE

CE1

C>-----.--------t

8 BIT OUTPUT LATCH

1201
r"-I"'---"""

(21 )

(21 )

A1

(22)

(22)

A2

(23)

A3

(1 )

(23)
(1 )

A4

(2)

(2)

A5

(4)

(3)

A6

(5)

(4)

A7
A8

(6)

(5)

-

(6)

8 TRI-STATE DRIVERS

Q

CE2 ETCE~

*T0--1

I

CE2

I

_ST_RO_B_E_-+_ _ _ _J

I

----------~I-------_i

:_~ _________)K

:

I
1

0, ....08

:1

i
V
I

----------~~~~------~
I
NOTE: T Cycle Time = TA + TAOS + TSW + TCOS

Vcc

If the strobe is high, the device functions in a manner identical to
conventional bipolar ROM's. The timing diagram shows valid data
will

appear T A nanoseconds after the address has changed and

T CE nanoseconds after the output circuit is enabled. TO is the time
required to disable the output and switch it to an 'off' or high impedance state after it has been enabled.

In Read Mode II, data from any selected address will be held on the
output when strobe is lowered. Only when strobe is raised will new
location data be transferred and chip enable conditions be stored.
The new data will appear on the outputs if the chip enable
conditions enable the outputs.

3

G!!InlltiCG

8·BIT CONTENT ADDRESSABLE
MEMORY (4x2 CAM)

8220

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

both directions, i.e., in the word length and in the number
of words.

The 8220 CAM Element is a high speed monolithic array,
incorporating the necessary addressing logic and eight identical memory cells organized as four words, each being two
bits long. I n reference to data-in/data-stored, the 8220 can
be conditioned to perform the following functions: associate,
write-in only, and read-out only.

The CAM circuit structure is the familiar TTL type (DCL
Family) and fully compatible with TTL and DTL input/
output structures.

FEATURES

When addressed into the "ASSOCIATE" mode, this element
offers the novel capability of data association, where each
cell (M nj ) will respond with a "Match" or "Mismatch"
answer (Y n ) to each bit presented to the data inputs (lj),
depending on presence or absence of an alike bit stored
within the cell.

• WRITE ENABLE CONTROL LINES
• ASSOCIATE CONTROL LINES
• ADDRESS SELECT CONTROL LINES
• ASSOCIATES IN 20nsec TYP.
• 16 PIN PACKAGE (1/3 SIZE OF 24 PIN PACKAGE)
• OPEN COLLECTOR OUTPUTS
• DIODE PROTECTED INPUTS

Write-in can be simultaneously done to all bits, or one bit
at a time. Read-out of stored information is performed on
one word at a time. Cell-selection for read and write is performed by proper addressing of Y n and An lines.

APPLICATIONS
DATA-TO-MEMORY COMPARISON
PATTERN RECOGNITION
HIGH SPEED INFORMATION RETRIEVAL
CACHE MEMORY
AUTO CORRELATION
VI RTUAL MEMORY
LEARNING MEMORY

The element's output structures (Y nand Dj) are of the
"bare collector" variety and can be mutually connected,
thus allowing direct expansion when multiple packages are
employed. Expansion of the CAM may be implemented in

LOGIC DIAGRAM

Vee
GND
(
)

.-----------,

= (16)
=
(8)

= Denotes Pin
Numbers

V3
(15)

°00-----'

4

~--------~

I

Mnj

(3)

= WORD n, bit j

(1)

'------00,

SIGNETICS 8-BIT CAM. 8220

ELECTRICAL CHARACTERISTICS

oOe ~ TA ~ 75°C; 4.75V ~ Vce ~ 5.25V
LIMITS

CHARACTERISTICS
MIN.

TYP.

MAX.

UNITS

0.4

V

Wj

Aj

Ij

Yi

2.0V

0.8V

2.0V

30mA

2.0V

60mA

Yk

OJ

NOTES

"0" Output Voltage
Yn

8,9

0.6

V

2.0V

0.8V

0.4

V

2.0V

2.0V

0.8V

20m A

0.6

V

2.0V

2.0V

0.8V

40mA

Yn

125

p,A

OJ

100

p,A

Ij and Aj

40

p,A

Wj

80

p,A

-1.2
-2.4

mA
mAo

1181
590

mA/mW

OJ

8,9

"1;' Output Leakage Current
10

2.0V
OV

10

OV

"1" Input Current
4.5V

4.5V

O.4V

O.4V

4.5V

"0" Input Current
Ii, Yn and Aj

-0.1

Wj
Power Consumption

851
425

O.4V

VCC = 5.0 Volts

SWITCHING CHARACTERISTICS 0 ~ T A ~ 75°e, 4.75V ~ Vee ~ 5.25V
LIMITS
CHARACTERISTICS

NOTES
MIN.

TYP.

MAX.

UNITS

Delay Time
Associate (Aj to Yn)

20

35

ns

See Notes 8 & 11

Associate (lj to Yn)

45

65

ns

See Notes 8 & 11

Read-Out (Yn to OJ)

30

45

ns

See Notes 8 & 11

Write-In to Read-Out (Wj to OJ)

45

65

ns

See Notes 8 & 11

Write Pulse Width

35

Ij Set-Up Time (ISO)
Ij Hold Time (HOI

ns

See Notes 8 & 11

10

ns

See Notes 8 & 11

10

ns

See Notes 8 & 11

20

NOTES
1. All voltage and capacitance measurements are referenced to the ground terminal. Terminals not specifically referenced are left electrically
open.
2. All measurements are taken with ground pin tied to zero volts.
3. Positive current is defined as into the terminal referenced.
4. Positive NAND logic definition: "UP" Level = "1", "DOWN" Level = "0".
5. Precautionary measures should be taken to ensure current limiting in accordance with Absolute Maximum Ratings should the isolation diodes
become forward biased.
6. Measurements apply to each gate element independently.
7. Manufacturer reserves the right to make design and process changes and improvements.
8. Prior to this test write in a "0" in all or desired Memory cells as follows: Wj = Ij = OV, Aj = V CC.
9. Output sink current is supplied through a resistor to V CC.
10. Connect an external 1 K ohm + 1% resistor from VCC to the output terminal for this test.
11. See AC test Figures on the following pages.

5

SIGNETICS 8-BIT CAM. 8220
MODE OF OPERATION
FUNCTION
HOLD

Wo

W1 AO A1

10 11

1 1 1 1 x x

REMARKS
(Ref. Definitions & Glossary)

FUNCTION

NO OPERATION

HOLD

Question Answer
1 1 1 0

x x

\NO W1 AO A1

1 1 1 1 x x

Output
State
1 0

B V E S - Vi =1.V k=O
11=Mi1
NO -Vi=Vk=O

1 1 '0

1 x x

1 1 x x

NO OPERATION
Forced
'Vi V k
1 0

WRITE 11 into Mi1

1 1 1 x x

1

0

WRITE 10 into M iO

1 1 x x

1

0

WRITE 11 and 10
into Mi1 and M iO

1 1 1 1 x x

1

0

DO=

0

WRITE·IN

0 0
ASSOCIATE

REMARKS
(Ref. Definitions & Glossary)

10 11

B V E S - Vi=1. Vk=O
10=MiO
NO -Vi=Vk=O

1 - IF M' 0 =1
I
0- IF MiO=O

1 1 0 0

x x

11=Mi1 - YES - V i =1, V k=O
READ-OUT
and ?
'O=M iO f-NO -Vi=Vk=O

1 1 1 1 x x

.

1 1 1 1 x x

1

0

D =
1

0

0

1-IFM· 1=1
I

0- IF Mi1=0

DO=D1 = 1

AC TEST FIGURES AND WAVEFORMS
ASSOCIATE DELAY AND INPUT DELAY
INPUT

5.0V

5.0V

Vee

GND

5.

~

1
30

'F

INPUT DELAY

ASSOCIATE DELAY

INPUT

A

,.5V\

INPUT I

'.5V

I .I - -_ _---1
I~----I

OUTPUT Y I
I

~-+I~'r-~-~'r-----

:,.5V\V

I

I
I
I

- - 1 ton

6

OUTPUT

y:

Y;.5V

~

-----: ton :-- -:

~'--

toft

___

:-

NOTES:
1. When checking AO let A1 = "1" and
when checking A1 let AO = "1".

NOTES:
1. When checking 11, A, = "0" and AO = "1" and
when checking 10, AQ = "0" and
= "1"

2. Wo = W 1 . = "1".

2.WO=W1="1".

A1

SiGNEiiCS S-Bii CAM

ii

822Q

AC TEST FIGURES AND WAVEFORMS (Cont'd)
WRITE DELAY
INPUT

Vee

Vee

IHO~
ISU

~
I

1-

2200
DO
D1

}-5K

-=

1.5V
INPUT I---.J.
INPUTW

OUTPUT

r

I

OF

1-

Isu

PW:--

:

- : PW

I

1

1

1

\

1.5V:

I

I___ ,--IHO

Pv
I
1

1

:

I

OUTPUT D - - - 0 + - - - . . 1

NOTES:
1. Ao = A 1 = "1".
2. Let all non-selected Y's = "0".
3. W's pulse width is 40ns @50% points.

READ DELAY
INPUT

5.0 V

5.0V
INPUTY

'.SV~,,-___--,{SV

Vee

DO

--I

D1

5K

5151

I

}--

GND
-:"

r

OUTPUT D

OF

NOTES:
1. A tested bit must store a "0".
2. ~O = ~1 = "1".
3. AO = A 1 = "1".
4. All non-tested Y's = "0".

data (logical "1" = Match, logical "0" = Mismatch).

GENERAL NOTES FOR AC TESTING:
1. Use 5k Probes for all AC tests TEK 169 or equivalent.
2. The Pulse Generator signal should consist of the following
Frequency: 10 MHz ±5 MHz
Amplitude: OV to 3V
Rise & Fall Times: 5 ns ±2ns
3.
= bit number (i = 0, 1). j = word number (j
0, 1, 2, 3).

In the read and write modes these terminals act as input controls and word-select lines Y lines (Y 1) associated with words
desired to accept writing of data or read-out are to be kept
in the logical "1" state and the remaining Y lines (Y k) to be
forced to a logical "0" state. (Note that A = 1 forces all
Y n = 1).
Data Output
These are "bare collector" output lines indicating the state
of one or more selected cells. Cell-Selection is accomplished
as defined under "Y n" above.

INPUT/OUTPUT DEFINITIONS

Yn -

Data Inputs
Data entering these terminals are either compared with stored
information at the cell(s) in the "associate" mode or stored in
the cell(s) in the "write-in" mode.
Associate Controls
A logical "0" at this pin enables Data-Cell association to
result into a defined logical level at the Y n lines (e.g. Y n = "1"
= Match, Y n = "0" Mismatch). A logical "1" at this pin
forces all Y n to a "1".
Write Enable
A logical" "0" at this control pin opens the gates of the
selected word, allowing data-in to be stored. A logical "1"
locks the gates such that data-in can no longer disturb the
cell(s).
"Associate" Output and Address Selection Control
During "Associate" mode these "bare collector" lines provide
output results of match or mismatch between input and stored

GLOSSARY OF TERMS - SUBSCRIPTS
A.

B.

Word number = 0, 1,2 and 3
Bit number = 0 or 1
Input/Output number(s) associated with cell(s) upon
which a "Write-in", "Read-out" or other function is
being performed.
k
Input/Output number(s) other than "i" above.
M
Designation of Memory Cell (word) = eight identical
cells in each package.
Examples
1. Ij for bit "1" equals 11 •

n

= M 10 = word "1" bit "0".
3. Y i = 0, Y k = 1: for i = words 1 and 3; then k
and 2: Y 1 3 = 0 and YO 2 = 1 .

2. Mnj

"

= words

0

7

SIGNETICS 8-BIT CAM. 8220
APPLICATION: LEARNING MEMORY
This system is a CAM array with peripheral IC circuitry
designed to operate as a learning memory. It is organized
in two sections of equal capacity, the total memory size
(both sections) being 8 ten bit words. Either section can be
selected through the section SELECT line, and the memory
is easily expandable in the number of words and in word
length.
By activating the COMPARE line, a new word is loaded into
the buffer and is presented to the memory. Through the
novel feature of data association, which is unique with CAM
elements, the buffer's content is compared with the words
stored in memory. If the input word, with which the memory was presented, is already contained in storage, no need
for "learning" i.e. data acquisition, exists. This fact is indicated by a match from one of the Y n lines (Yi = 1) and thus

no write command is initiated.
Before a WRITE operation is initiated, a location select has
to be made such that the word to be written into the
memory will go to the proper place. For this reason, a tag
CAM is employed to keep track of memory locations, both
empty and full. When a word is written into memory, a "1"
is simultaneously written into the tag CAM. Thus, it is
possible to keep track of the filled memory locations.
By monitoring the Y n lines of the tag CAM, a convenient
way of decoding an available address exists. Here exclusive
OR circuitry is used which ensures that memory locations
are filled successively when the need for "learning" exists.
The quad latch is enabled before the write command is
available to the CAM array. Thus the Y lines of unavailable
memory locations are forced low (Yk = 0).

Vee

8

256-B11 BIPOLAR FIELD-PROGRAMMABLE
ROM (32x8 PROM)

I

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

APPLICATIONS

The 8223 is a TTL 256-Bit Read Only Memory organized as
32 words with 8 bits per word. The words are selected by
five binary address lines; full word decoding is incorporated
on the chip. A chip enable input is provided for additional
decoding flexibility, which causes all eight outputs to go to
the high state when the chip enable input is high.

PROTOTYPI NG
VOLUME PRODUCTION
MICROPROGRAMMI NG
HARDWIRED ALGORITHMS
CONTROL STORE

LOGIC DIAGRAM

This device is fully TTL or DTL compatible. The outputs
are uncommitted collectors, which permits wired AND operation with the outputs of other TTL or DTL devices. These
outputs are capable of sinking twelve standard DCL loads.
Propagation delay time is 50ns maximum. Power dissipation
is 310 milliwatts with 400 milliwatts maximum. The 8223
may be programmed to any desired pattern by the user. (See
fusing procedure.) This feature is ideal for prototype hardware and systems requiring propriety codes.
A Truth Table/Order Blank is included on page 4-43 for
ordering custom patterns.

= (16)
=
(8)

(

=;

)

Denotes

Pin Numbers

32 x 8 ARRAY

FEATURES
•
•
•
•
•
•
•

VCC
GND

BUFFERED ADDRESS LINES
ON THE CHIP DECODING
CHIP ENABLE CONTROL LINE
OPEN COLLECTOR OUTPUTS
DIODE PROTECTED INPUTS
NO SEPARATE FUSING PINS
BOARD LEVEL PROGRAMMABLE

Chip is Enabled when CE = "0"

ELECTRICAL CHARACTERISTICS S8223-55°C ~ TA ~ +125°C N8223 O°C ~ TA ~ 75°C; 4.75V ~ VCC ~ 5.25V
LIMITS
CHARACTERISTICS
MIN.

"1" Output Leakage Current

"0" Output Voltage (NB223-)

TYP.

"0"

"1"

CHIP

An

An

ENABLE

OUTPUTS NOTES

MAX.

UNITS

(NB223-)

100

J.LA

(SB223-)

250

J.LA

(SB223-)

0.4

V

O.BV

2.0V

O.BV

9.6mA

6,10

(NB223-)

0.5

V

O.BV

2.0V

O.BV

16mA

6,10

40

J.LA

2.0V

5.5V

13

2.7V

"1" I nput Current
An, Address
Chip Enable Input

"a"

BO

J.LA

-1.6

mA

4.5V
4.5V

Input Current
An, Chip Enable

Power Consumption

-0.1
62/310

77/400

mW/mA

O.4V

O.4V
4.5V

4.5V

14

9

SIGNETICS 256-BIT FIELD PROGRAMMABLE ROM. 8223
SWITCHING CHARACTERISTICS S8223 -55°C ~TA ~ 125°C, N8223 O~TA ~ 75°C, 4.75~ VCC~ 5.25V
LIMITS
CHARACTERISTICS

TEST CONDITIONS
MIN.

TYP.

MAX.

UNITS

35

50

ns

TA

65

ns

Full Temp

60

ns

Full Temp

50

ns

TA

S8223

60

ns

Full Temp

N8223

55

ns

Full Temp

Access Time (tON, tOFF)
Address
S8223
N8223
Chip Select

35

=

=

25°C Only

25°C Only

NOTES
1. All voltage measurements are referenced to the ground terminal. Terminals not specifically referenced are left electrically open.
2. All measurements are taken with ground pin tied to zero volts.
3. Positive current is defined as into the terminal referenced.
4. Positive logic definition: "UP" L.evel = "1", "DOWN" Level = "0".
5. Precautionary measures should be taken to ensure current limiting in accordance with Absolute Maximum Ratings should the isolation diodes
become forward biased.
6. Output sink current is supplied through a resistor to V CC.
7. One DC fan-out is defined as O.SmA.
S. One AC fan-out is defined as 50pF.
9. Manufacturer reserves the right to make design and process changes and improvements
10. By DC tests per the truth table, all inputs have guaranteed thresholds of O.SV for logical "0" and 2.0V for logical "1".
11. Th is test guarantees operation free of input latch-up over the specified operating power supply voltage range.
12. For detailed test conditions, see AC testing.
13. Connect an external 1 k resistor from VCC to the output terminal for this test.
14. VCC = 5.2SV.

AC TEST FIGURE AND WAVEFORMS

INPUT PULSE:
AMPLITUDE =3.0V

SCHEMATIC DIAGRAM

vee

(16)

Vee

tr = tf = 5ns
PW = 200ns (50% DUTY CYCLE)

INPUT OR
CHIP ENABLE
_I

'oFF

:
I
I
I
I

:---

_:

"ON

1
I

t---I

OUTPUT
OUTPUT
80 111

8,121
82131
B3 (4)

1

I
-I

INPUT

TON

1

t---_

Vee

84151
~~

TOFF ~

86 171'
87191

TEST LOAD
Vee

VCC = (16)
GND = (S)
Ground Pin 15 When Testing Address-Output Delays

10

(S) denotes pin number ( )

SIGNETICS 256-BIT FIELD-PROGRAMMABLE ROM. 8223
8223 PROGRAMMING PROCEDURE
The 8223 Standard part is shipped with all outputs at
logical "0". To write a logical "1" proceed as follows:
Simple Programming Procedure using "bench" Equipment
(See below)
1. Start with pin 8 grounded and Vee removed from pin
16.
2. Remove any load from the outputs.
3. Ground the ehip Enable.
4. Address the desired location by applying ground (i.e.,
O.4V maximum) for a " 0", and +5.0V (i.e., +2.8V
minimum) for a "1" at the address input lines.
5. Apply +12.5V ±0.5V to the output to be programmed
through a 390 ohm ±10% resistor. (Program one output
at a time.)
6. After a short delay apply +12.5V to Vee (pin 16) and
remove as quickly as possible (rise time of 50J.Lsec or
less). The Vee overshoot should be limited .to 1.0V
maximum. If necessary, a clamping circuit should be
used.
NOTE: Normal practice in test fixture layout should be
followed. Lead lengths, particularly to the
power supply, should be as short as possible. A
capacitor of 10 mi~rofarads minimum, connected from the +12.5V to ground, should be
located close to the unit being programmed.
7. Verify that the bit has programmed by applying 5 volts
to Vee and 5 volts through a lk resistor to the output.
8. Proceed to the next output and repeat, or change
address and repeat.
9. Continue until the entire bit pattern is programmed into
your custom 8223.

10. If during verification a bit had been found not to have
programmed, return to that bit and repeat the programming procedure once.
Fast Programming Procedure

1. Remove Vee (open or ground pin 16).
2. Remove any load from the output.
3. Ground eE (pin 15)
4. Address the word to be programmed by applying 5 volts
for a "1" and ground for a "0" to the address lines.
5. Apply +12.5V ±0.5V to the output to be programmed
through a 390 ohm ±10% resistor. (Program one output
at a time.)
6. After a minimum delay of 100psec, apply +12.5V to
Vee (pin 16) for 1.0mS. The Vee rise time must be
50psec or less. Limit the Vee overshoot to 1.0 volts
max.
7. Reduce Vee to ground «0.5V) and remove the load
from the output.
8. Repeat steps 5 and 6 for other outputs of the same
word, or repeat 4 through 6 for a different word until
the entire bit pattern is programmed.
After programming the 8223, the unit should be checked to
insure the code is correct.

BOARD LEVEL PROGRAMMING PROCEDURE
FOR THE 8223
The chip select controls which 8223 is being programmed
when several PROMS are collector OR'd. To program in
this manner, the only change required is to reduce the 390
200 ohm
.
N
where N IS the number of outputs
ohm resistor to
tied together (2 ~ N ~ 12).

MANUAL PROGRAMMER DIAGRAM

PROGRAM
VERIFY

5.0V
390 ohm

PROGRAM
VERIFY

NOTES
1. The 10J.LF capacitor across pin 16 to ground is required to eliminate noise from Vee.
2. During programming switch Sa must be in the verify position long enough for the 10J.LF capacitor to discharge to 5.0 volts.

11

Si!ln~liCS

64·B11 BIPOLAR SCRATCH PAD
MEMORY (16x4 RAM)

8225

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

BLOCK DIAGRAM

The 8225 is a TTL 64-bit Read-Write Random Access Memory organized as 16-words of 4 bits each. The 8225 is ideally suited for application in scratch pads and high-speed
buffer memories.
Words are selected through a 4-input binary decoder when
the chip enable input (CE) is at logic "0". Data is written
into the memory when Read Enable (RE) is at logic "0"
and read from the memory when R E is at logic "1".
The outputs of the 8225 are logical "1" during write operation, therefore, inputs and outputs can be commoned in
busses to reduce the number of I/O leads. Output collectors
are uncommitted.

FEATURES
•
•
•
•
•

CHIP ENABLE LINE FOR EXPANSION
OPEN COLLECTOR OUTPUTS FOR EXPANSION
ON THE CHIP DECODING
ALL OUTPUTS "1" DURING WRITING
DIODE PROTECTED INPUTS

VCC
GND

= (16)
=
(8\

(

= Denotes Pin Numbers

)

"ONE" LEVEL ON DATA INPUT APPEARS AS "ZERO"
LEVEL OUT.
Chip is enabled when CE = "0"

PIN CONFIGURATION

APPLICATIONS
SCRATCH PAD MEMORY
BUFFER MEMORY
PUSH DOWN STACKS (First in-first out)
CONTROL STORE

TRUTH TABLE
RE

-

CE
(Chip Enable)

0

0
1
X

x

0
1

MODE

OUTPUTS

Write
Read
Chip Disable

1'1 "
Information
1'1 "

= Either State

ELECTRICAL CHARACTERISTICS o°c ~ TA 75°C; 4.75V ~ VCC ~ 5.25V
LIMITS

INPUTS
CHIP
ENABLE

CHARACTERISTICS
MIN.

TYP.

"0" Output Voltage

.4

"1" Output Leakage Current
"0" I nput Current

MAX.

-.1

DATA
INPUTS
WRITE

UNITS

V

.8V

Pulse

100

J.LA

.8V

Pulse

-1.6

mA

.4V

.4V

80

J.LA

4.5V

40

J.LA

4.5V

1101
550

V
mAl
mW

-18mA
OV

OUTPUTS

NOTES

ADDRESS

.8V
.4V

16mA

6,8,0,

5.25V

8,9

.4V

11

4.5V

11

"1" Input Curnmt
Chip Enable
Write, Address, Data
Input Clamp Voltage
Power Consumption

12

-1.5
80
400

4.5V
-18mA
5V

4.5V
-18mA
OV

-18mA
OV

11
10,5

SIGNETICS 64-BIT SCRATCH PAD MEMORY. 8225
SWITCHING CHARACTERISTICS 0 ~ TA ~ 75°C, 4.75 ~ VCC ~ 5.25V
LIMITS
TEST CONDITIONS

CHARACTE R ISTICS
MAX.

UNITS

MIN.

TYP.

Minimum Write Pulse Width (WpW)

30

18

ns

Input Setup Time (lSU)

20

18

ns

Input Hold Time (lHO)

10

0

Address Setup Time (ASU)

10

Address Hold Time (AHO)

10

ns

Access Time (T A)
Access Time (T A)

35

Data Pulse Width (DpW)

ns
ns

60

ns

See Note 12

50

ns

T A = 25°C, See Note 12

ns

20

Write Recovery Time (TWR)

25

40

ns

Write Access Time (TWA)

25

50

ns

Chip Enable Recovery Time (TCR)

20

35

ns

Chip Enable Access Time (T CAl

20

35

ns

NOTES
1. All voltage measurements are referenced to the ground terminal. Terminals not specifically referenced are left electrically open.
2. All measurements are taken with ground pin tied to zero volts.
3. Positive current is defined as into the terminal referenced.
4. Positive logic definition: "UP" Level = "1", "DOWN" Level = "0".
5. VCC = 5.0V.
6. Output sink current is supplied through a resistor to V CC.
7. One DC fan-out is defined as 0.8mA.
8. By DC tests per the truth table, all inputs have guaranteed thresholds of 0.8V for logical "0" and 2.0V for logical"1".
9. For any given binary code on the Address inputs the Write input must be momentarily brought to a logical "0" level.
1 O. A II sense outputs in "0" state.
11. Test each input one at a time.
12. Address Pulse Width (ApW> is 40ns for this test.
13. Rise and fall times of inputs for AC tests are ~5ns. Pulse amplitudes are 2.5 volts and measurements are made at 1.5 volts.

FUNCTIONAL DIAGRAM
,..-..-------------,
Vcc

r--------CE

RE

I

ONE LEVEL IN ON DATA INPUT APPEARS
AS "ZERO" LEVEL OUT.

13

SIGNETICS 64-BIT SCRATCH PAD MEMORY. 8225
AC TEST FIGURES AND WAVEFORMS

NOTE:

* See Note 13.

14

NEGATIVE TRANSITION
DOES NOT GO BE LOW 2.6
VOLTS AND GENERALLY
IS NOT MEASURABLE.

4096 BIT BIPOLAR ROM I
(1024x4 ROM)

I:lnnntll!l:
";·I··~"·""

R??R
" .... u

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION
The 8228 is a 4096 Bit Bipolar Read Only Memory
organized as 1024 words by 4 bits per word. Available in a
16 pin dual in-line package, the 8228 can provide very
high bit packing density by replacing four standard 256X4
ROMS.

See page 4-35 for CD162 Pattern and USASCII Row
Character Generator.

FEATURES

The 8228 is fully TTL compatible and includes on-the-chip
decoding. Typical access time is 50ns with a power
consumption of only .125mW per bi~.

•
•
•
•
•

BUFFERED ADDRESS LINES
ON THE CHIP DECODING
TOTEM POLE OUTPUTS
DIODE PROTECTED INPUTS
16 PIN PACKAGE (1/3 SIZE OF 24 PIN PACKAGE)

The standard 8228 ROM pattern is the USASCII Row
Character Generator code; however, custom patterns are
also available. The standard pattern is specified as the
N82281 - CD162, while custom circuits are identified as
N82281 - CXXX. A truth table/order blank is included
on page 4-46 for orderi ng custom patterns.

MICROPROGRAMMING
HARDWIRED ALGORITHMS
CHARACTER RECOGNITION
CHARACTER GENERATION
CONTROL STORE

APPLICATIONS

BLOCK DIAGRAM

INPUT
SCHEMATIC

Vcc

PIN CONFIGURATION

OUTPUT
SCHEMATIC

Vee
WORD SELECT

OE~~ER

64X64BIT
STORAGE MATRIX

1-----1

61TSELECT
1-16

64-4 BIT

DECODER

MULTIPLEXER

Vee = (16)
GND =
(8)
(
)
= Denotes Pin Numbers

ELECTRICAL CHARACTERISTICS O°c ~ TA ~ 75°C; 4.75V ~ Vec ~ 5.25V
·

-

-~---

LIMITS
TEST CONDITIONS

CHARACTERISTICS
MIN.
"0" Output Voltage
"1" Output Voltage
"0" I nput Current
"1" Input Current
Input Threshold Voltage
"0" Level
"1" Level

TYP.

MAX.
0.5

2.7
-10
1

-400
25
.85

2.0

NOTES

..

UNITS
V
V
p,A
p,A

lout = 11.2 rnA
lout = -1.0 rnA
Yin = 0.45V
Yin = 5.5V

V
V

15

SIGNETICS 4096-BIT ROM. 8228
ELECTRICAL CHARACTERISTICS (Cont'd)
LIMITS
CHARACTE RISTICS

TEST CON 01 TI ONS
MIN.

Input Clamp Voltage
Power Consumption
Output Short Circuit Current

TYP.

MAX.

140

'170
-70

UNITS
V
mA
mA

-1.2

-20

NOTES

= -lamA
= "0"
VOUT = 0 Volts
lin

01 to 03

SWITCHING CHARACTERISTICS 0 ~ TA ~ 750 e, 4.75 ~ Vee ~ 5.25V
LIMITS
CHARACTE RISTICS
MIN.

I

TYP.

I

Access Time-Address to Output

50

I

I

MAX.

I

I

70

TEST CONDITIONS
UNITS
ns

NOTES

5

NOTES
1. Positive current is defined as into the terminal referenced.
2~ No more than one output should be grounded at the same time.
3. Manufacturer reserves the right to make design and process changes and improvements.
4. Applied voltages must not exceed 6.0V. I nput currents must not exceed ±30mA. Output currents must not exceed ±100mA. Storage
o
temperature must be between -60°C to +150 C.
5. Rise and fall time for this test must be less than 5ns. Input amplitudes are 2.8V and all measurements are made at 1.5V.

AC TEST FIGURE AND WAVEFORM
TEST LOAD

vee
(

5K

READ CYCLE

AOA~i;RES:9

F~--~I---------- - - - - - ----./ 1 .....
_ _ _ _-+1- - - - - - -

0,'°2'°3'°4
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

16

I
~/~--------

J/"'"

siqnl!tics
.....

( ol)~nc
l UL"UU

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

BLOCK DIAGRAM

The 82S06 and 82S07 are ideal devices for use in Control
Stores, small buffers, scratch pads, "cache" type buffer
stores, memory maps, etc. The typical read time (the
time between applying an address and obtaining valid output data) is 45ns. The typical write time (the time between applying one.address and storing data) is 30ns. The
circuit has 3 chip enable inputs which greatly simplifies the
circuit configuration when used in larg~ memories. The
82S06 and 82S07 also feature very low input loadings,
25 microamperes for a "1" state and -100 microamperes
for "0".

256 BIT BIPOLAR RANDOM ACCESS MEMORY
OUTPUT
SCHEMATIC

INPUT
SCHEMATIC
VCC

82S06 ONL Y

Al

"VCC

1

AO'
CE ,
1
CE ,
2
CE ,
3
D06
A

13

,

4

DIN

12

R/W

11

A7

.. A

GNDa

6

• A5

The memories are TTL compatible and operate from single
5 volt supply.
16 X 16 BIT STORAGE MATRIX

APPLICATIONS
BUFFER MEMORY
WRITABLE CONTROL STORE
MEMORY MAPPING
PUSH DOWN STACK

ADDRESS
LINES

FEATURES
•

256 X 1 ORGANIZATION

•

30 NANOSECOND ACCESS TIME TYPICAL

•

LOW 1.5 mw/BIT POWER DISSIPATION TYPICAL

•

LOW 100 tJA INPUT LOADING

V'CC
GND

•

TRI-STATE (82S06) OR OPEN COLLECTOR
(82S07) OUTPUT

(

•

ON CHIP DECODING

161

Denotes Pin Numbers

)

"ONE" LEVEL IN ON DATA INPUT APPEARS AS "ZERO"
LEVEL OUT.

ELECTRICAL CHARACTERISTICS (TA = 0 to 7SoC, 'VCC = 5.0V ±5) Note 1,2,3
LIMITS
CHARACTE RISTICS

TEST CONDITIONS
MIN.

TYP.

MAX.

"0" I nput Current

-10

-100

/-LA

Vin

"1" I nput Current

<1.0

25

/-LA

Vin

"0" Output Voltage

0.35

0.45

V

Output Leakage Current (82S07)

<1.0

40

/-LA

Output "off" Current (82S06)

<1.0

±100

/-LA

"1" Output Voltage (82S06)
"0" Input Threshold

2.6

"1" Input Threshold

2.0

Power Consumption
Input Clamp Voltage

80/400
-1.2

I nput Capacitance

V

115/604

mA/mW

-0.8

lout = 16mA
CE1, CE2, CE3 = "1", V out
CE1, CE2, CE3 = "1", 0.45
CEl = CE2

= CE3 = "0"

=

5.5V

~

V out

lout

~

5.5V

= -3.2mA

V

lin

= -18mA

pF

8.0
-20

= 0.45V
= 5.5V

V

2.0

5.0

Output Capacitance
Output Short Circuit Current
(82S06)

V
0.85

NOTES

UNITS

pF
-70

mA

V out

= OV
17

SIGNETICS 256-BIT ROM. 82806/07
SWITCHING CHARACTERISTICS 0 ~ TA ~ 75 0 e, 4.75 ~ Vee ~ 5.25V
LIMITS

CHARACTERISTICS

MI~.

Access Time-Address to Output

TYP.
45

Access Time-Address to Output
Address Set-Up Time (read)

25

t1

10

MAX.

UNITS

65

ns

SO

ns

SO

ns

NOTES

TEST CONDITIONS
T A =25

0

4,5

COnly

4,5

Propagation Delay
Chip Enable to Output Enable

t2

25

40

ns

t3

25

40

. ns

4,5

Propagation Delay
Chip Enable to Output Disable
Address to Write Enable

4,5

Set-Up Time

t4

25

5

ns

t5

10

0

ns

Chip Enable to Write Enable

4,5

Set-Up Time

4,5

Data Input to Write Enable
Set-Up Time

t6

10

0

ns

Write Enable Pulse Width

t7

30

15

ns

4,5

Address Hold Time

ts

10

0

ns

4,5

Chip Enable Hold Time

tg

10

0

ns

4,5

Data Input Hold Time

t10

10

0

ns

4,5

Write Enable Propagation Delay

t11

ns

4,5

30

40

NOTES
1. Positive current is defined as into the terminal referenced
2. Manufacturer reserves the right to make design and process changes and improvements.
3. Applied voltages must not exceed 6.0V. Input currents must not exceed ±30mA. Output currents must not exceed ±100mA. Storage
o
o
temperature must be between _60 e to +150 e.
4. Refer to Timing Diagram for definition of terms and test load.
5. Rise and fall times for this test must be less than 5ns. Input amplitudes are 2.8V and all measurements are made at 1.5 volts.

TIMING DIAGRAM

READ MODE PROPAGATION DELAY FROM CHIP ENABLE

~r---I------------------------

Ao A7
ADDRESS

TEST LOAD
VCC
()

~~L._I_l__~~~
____________________________

• -

I -

______

~

,
~I

\

eEl. CE2. eE3
CHIP ENABLE

I~

'"__ _ _ _ _ _ _J

.~ 270H

_________

I

1

; I , -____ ~--~
- 1 t2
~ 13 Jr'~

1':'-

DO

.-- -----1---- J I

OUTPUT

I

1'-----·

::x ---.; ----(:.::-':':i --; -- -y;=

WRITE MODE

AO A7
ADDRESS
tEl. CE2. eE3
CHIP ENABLE
DIN
DATA INPUT

R/W
READ/WRITE ENABLE

__ J

.

----:\.

~

____

15

I

I

I

I

II I '
~

t9

,--1----- -t-, ,.-----

t7

===LJ:=
1

------- --~ \.,----""!:~------_____t'_,_~-~
__ ~ ______ _

OUTPUT
(ADDRESS AND CHIP ENABLE STABLE)

18

--..1

~t6 i~~lt10Y.~-----_
I

DO

• '----

set up time for an address input to chip enable for valid data at outputs.
propagation delay from chip enable to valid data at output
propagation delay from chip disable to output turn off
set up time from address to write enable
set up time from chip enable to write enable
set up time from data input to write enable
write enable pu lse width
hold time for address from write enable
hold time for chip enable from write enable
hold time for data input from write enable
propagation delay from write enable to valid data at

o~tput

GinnntiCG
-i-'--- ----

.HIGH SPEED MULTIPORT MEM"OR~I
(8x4 MULTIPORT RAM)
DIGITAL 8000

SERI~S

TTL/MEMORY

DESCRIPTION

APPLICATIONS

The 82S12/112 is a Schottky TTL 32 bit multiport
memory organized in 8 words of 4 bits each. The device is
ideally suited for high speed accumulators and buffer
memories:

SCRATCH PAD MEMORY
BUFFER MEMORY
ACCUMULATOR REGISTER
GENERAL REGISTER

Stored data is addressed through 2 independent sets of
3-input decoders, and read out when the corresponding,
output enable line is low. Two separate word locations can,
therefore, be read at the same time by enabling both the A
and B output drivers. In addition, data can be read and
written at the same time by utilizing the "A" address to
specify the location of the word to be written, and the
"B" address to specify the word to be read.

82S12
82S112

PIN CONFIGURATION

The 82S12/112 can be used in larger memory arrays since it
includes all the control logic required to disable the chip
and the outputs are open-collector devices suitable for
"Wire-O Ring."

FEATURES
•

LOW CURRENT INPUT BUFFERS (-25J,LA TYPICAL)

•

SEp·ARATE INPUT DECODERS FOR EACH WORD

•

SEPARATE OUTPUT ENABLE LINES FOR. EACH
WORD

•

OPEN COLLECTOR (82S12) OR TRI-STATE (82S112)
OUTPUTS

•

2 WRITE ENABLE LINES

•

FAST ACCESS (20 ns TYPICAL)

• USEFUL 8 X 4 ORGANIZATION
• TTL COMPATIBLE
• NON INVERTING DATA LINES

BLOCK DIAGRAM

TRUTH TABLE
A

Fi/w R/W

ENABLE

AAO
'A"OECODER
ADDRESS LINES
;READfWRlTEl

141
(5)

AA1

{:
AA2

(6)

0
0
0
0
1
1
1
1
1
1

X
X
X
X

1
1
1
1
0
0

B

OUTPUTS

OUTPUT OUTPUT

1
1
0
0
1
1
0
0
1
1

MODE

ENABLE
Outputs
Disabled
Read
Read
Read
Read
Read
Read
Read
Write
Write

1
0
1
0
1
0
1
0
1
0

A

B

"1"
"1",
Data
Data
"1"
"1"
Data
Data
"1"
"1"

"1"
Data
"1"
Data
"1"
Data
"1"
Data
"1"
Data

"8"

-

1

0

0

1

Write

1

0

0

0

Write

Address
"1"

Data
Being
Written
Data
Data
"B"
Being
Written Address

19

SIGNETICS HIGH SPEED MULTIPORT MEMORY. 82812/112
OBJECTIVE ELECTRICAL SPECIFICATIONS aOe ~ T A
LIMITS

CHARACTERISTICS

MIN.

Input "0" Current
Input "1" Current
Input "0" Threshold Voltage
Input" 1" Threshold Voltage
Input Clamp Voltage
Output "0" Current
Output "0" Current
Output "1" Voltage(825112)
Output Off Current (82S12)
Output Off Current (82S112)
Power Consumption
Write Pulse Width
Tl
Address Set Up Time
Address Hold Time
Data Input Hold Time
Write Access Time
Data Input Set Up Time
Output Enable Time
Output Disable Time
Address Access Time

~ 75°e; -4.75 V ~ Vee ~ 5.25 V.

T1
T2
T3
T4
T5
T6
T7
T8
T9

TYP.

MAX.
-250
25
0.85

2.0
-1.2
16
9.6
2.6
-40
30
45

110/550
15
10
0
0
30
5
10
10
20

40
+40
160/840

20
.20
30

TEST CONDITIONS

UNITS
/-LA
/-LA
V
V
V
mA

Vin
Vin

lin = -18 mA
V out = 0.5 V
V out = 0.45 V
lout = -3.2 mA
V out .,;;; 5.5 V
0.45.,;;; V out ";;; 5.5 V
Outputs Enabled
T A = 25°C Only

Volts
/-LA
/-LA
mA/mW
ns
ns
ns
ns
ns
ns
ns
ns
ns

TIMING DIAGRAM

T1

WRITE PULSE WIDTH - Width of write pulse (when R/W="1" and R/W="O")

T2

ADDRESS SETUP TIME - Required delay between beginning of valid Address and beginning
of Write pulse.

T3

ADDRESS HOLD TIME Address.

T4

DATA INPUT HOLD TIME - Required delay between start of Write pulse and end of Valid
Data input.

VCC

Required delay between end of Write pulse and end of valid

T5

WRITE ACCESS TIME - Delay between beginning of Write pulse and Data Out at new value.

T6

DATA INPUT SET·UP TIME - Required delay between beginning ov Valid Data Input and
start of Write pulse.

T7

OUTPUT ENABLE TIME - Delay between beginning of Output Enable high and when Data
Output becomes valid.

270.11

300.11

OUTPUT DISABLE TIME - Delay between when Output Enable becomes low and Data
Output is in off state.
Tg

ADDRESS ACCESS TIME - Delay between beginning of Valid Address (with Output Enable
high, R/W high and R/W low) and when Data Output becomes valid.

NOTES
*"8" Address functions identically in read mode. No write mode through 8 address decoder.
* * R/W input is either the reverse of R/W or held high.
Outputs can be disabled during write cycle to penetrate a known output state during write.

20

= 0.45 V
= 5.5 V

A. C. LOAD

!iinn~tiC!i
~

256 BIT BIPOLAR RAM [256x1 RAMll82S
[82S16 TRI·ST ATE J [82S 17 OPEN COLLECTOR j 1

16

2
S
17
8

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

BLOCK DIAGRAM

The 82S 16 and 82S 17 are ideal devices for use in Control
Stores, small buffers, scratch pads, "cache" type buffer
stores, memory maps, etc. The typical read time (the
time between applying an address and obtaining valid output data) is 30ns. The typical write time (the time between applying one address and storing data) is 30ns. The
circuit has 3 chip enable inputs which greatly simplifies the
circuit configuration when used in large memories. The
82S16 and 82S17 also feature very low input loadings,
25 microamperes for a "1" state and -100 microamperes
for "0".

256 BIT BIPOLAR RANDOM ACCESS MEMORY
OUTPUT
SCHEMATIC

INPUT
SCHEMATIC
VCC

A1

82S\.60NLY

" VCC

AO'
CE 1 3

" A2
" A3

CE 2 '

" ?IN

CE 3 '

" R/W

0 06
A

4

,

" A7
" A6

GND'

A5

-=
The memories are TTL compatible and operate from single
5 volt supply.

16 X 16 BIT STORAGE MATRIX

APPLICATIONS

ADDRESS
LINES

BUFFER MEMORY
WRITABLE CONTROL STORE
MEMORY MAPPING
PUSH DOWN STACK

FEATURES
•

256 X 1 ORGANIZATION

• 30 NANOSECOND ACCESS TIME TYPICAL
•

LOW 1.5 mw/BIT POWER DISSIPATION TYPICAL

•

LOW 100 tJA INPUT LOADING

•

TRI-STATE (82S16) OR OPEN COLLECTOR
(82S17) OUTPUT

•

ON CHIP DECODING

VCC
GND
(

\61

)

Denotes Pin Numbers

"ONE" LEVEL IN ON DATA INPUT APPEARS AS "ZERO"
LEVEL OUT. Chip is enabled when CE1 = CE2 = CE3 = "0"

ELECTRICAL CHARACTERISTICS (O°C ~ TA ~ 75°C; 4.75V ~ VCC ~ 5.25V) Note 1,2,3
--

LIMITS
CHARACTE RISTICS

TEST CONDITIONS
MIN.

TYP.

MAX.

"0" I nput Current

-10

-100

p.A

Yin

"1" I nput Current

<1.0

25

p.A

Yin

"0" Output Voltage

= 0.45V
= 5.5V

.35

0.45

V

Output Leakage Current (82S17)

<1.0

40

p.A

eEl, CE2, CE3 = "1", V out

Output "off" Current (82S16)

<1.0

40

p.A

eEl, CE2, CE3 = "1", 0.45 ,;;;; V out ,;;;; 5.5V

"~,, Output Voltage (82S16)

V

"0" Input Threshold

2.6

"1" Input Threshold

2.0

Power Consumption
I nput Clamp Voltage

-1.2

-.8

eEl = CE2 = CE3 = "0" lout = -3.2mA

mA/mW
V

lin

= -18mA

pF

8
-20

= 5.5V

V

115/604

5

Output Capacitance
Output Short Circuit
(82S16)

lout = 16mA

V

80/400

I nput Capacitance

NOTES

UNITS

pF
-70

mA

- V out

= OV
21

SIGNETICS 256- BIT ROM. 82516/17
o ~ 75°e, 4.75 ~ Vee ~ 5.25V

SWITCHING CHARACTERISTICS

LIMITS

CHARACTERISTICS

MIN.

TYP.

MAX.

UNITS

30

50
60

ns

10

65

ns

t2

20

40

ns

t3

20

40

ns

Access Time-Address to Output
Access Time-Address to Output
Address Set-Up Time (read)

25

t1

TEST CONDITIONS
TA

= 25°C

Only

NOTES
4,5

4,5

Propagation Delay
Chip Enable to Output Enable

4,5

Propagation Delay
Chip Enable to Output Disable
Address to Write Enable

4,5

Set-Up Time

t4

20

5

ns

t5

10

0

ns

t6

0

ns

t7

10
30

15

ns

Address Hold Time

t8

0

0

ns

Chip Enable Hold Time

t9

0

0

ns

4,5

'Data Input Hold Time

tlO

0

0

ns

4,5

Write Enable Propagation Delay

t11

Chip Enable to Write Enable

4,5

Set-Up Time

4,5

Data Input to Write Enable
Set-Up Time
Write Enable Pulse Width

30
-20

Output Short Circuit Current (82S16)

40

ns

-70

rnA

4,5
4,5

4,5
V out

= OV

4,5

NOTES:
1. Positive cu rrent is defined as into the terminal referenced.
2. Manufacturer reserves the right to make design and process changes and improvements.
3. Applied voltages must not exceed 6.0V, I nput currents must not exceed 30mA, Output currents must not exceed 100mA, Storage
temperatu re must be between -60 C to + 150 C.
4. Refer to Timing Diagram for definition of terms and test load.
5. Rise and fall times for this test must be 5ns. Input amplitudes are 2.8V and all measurements are made at 1.5 voLts.

TIMING DIAGRAM

TEST LOAD

READ MODE PROPAGATION DELAY FROM CHIP ENABLE

Vee

AO A7
~r---I-----------------------ADDRESS ~~~._t_l__:~~
___________________________

'\

CE,. CE2. eE3
CHIP ENABLE

~

1.':"- ~I
.-- -----1---- I
--l

WRITE MODE
AO
A7
ADDRESS

CE1. CE2. CE3
CHIP ENABLE

-:'\.r
--;'\
• _J

t2

R/W
READ/WRITE ENABLE

J

l4

~.

-I

I!
1

;.:--

,,---

tg

.

____ ~t6 i-,t'oX~_____ _
__1_ _ _ _ -

t7~

------t'_l_~-_'I
-- --~ ,--+:+-------______ _
____

1

\. _ _

-1

30pF

270H

~~

.~ 300~1

I-=-~

-'~

F
_+_, ,.________

~--i1
1

ts

(ADDRESS AND CHIP ENABLE STABLE)

22

p~
1'-----·

1

I

DO
OUTPUT

t3

--------1-t-----1------ta
,

DIN
DATA INPUT

:~

j

_ _ _ _ _JI

;I,-----~--~

DO
OUTPUT

C)

set up time for an address input to chip enable for valid data at outputs •
propagation delay from chip enable to valid data at output
propagation delay from chip disable to output turn off
set up time from address to write enable
set up time from chip enable to write enable
set up time from data input to write enable
write enable pulse width
hold time for address from write enable
hold time for chip enable from write enable
hold time for data input from write enable
propagation delay from write enable to valid data at output

e:nnnt;l!-=

64-BIT BIPOLAR HIGH SPEED I R?~?l
WRITE -WHILE-READ RAM (32x2 RAM J v .. " ...

.. :., •• -.= .......

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

APPLICATIONS

The 82S21 is a TTL 64 bit Write-While-Read Random
Access Memory organized in 32 words of 2 bits each. The
82S21 is ideally suited for high speed buffers and as the
memory element in high speed accumulators.

SCRATCH PAD MEMORY
BUFFER MEMORY
ACCUMULATOR REGISTER
CONTROL STORE

LOGIC DIAGRAM
Words are selected through a 5 input decoder when the
Read-Write enable input, CE is at logic "1". Wo and W1
~e the write inputs for bit 0 and bit'~f the ~rd selected.
C is the write control input. When Wx and C are both at
logic "0" data on the 10 and 11 data lines are written into
the addressed word. The read function is enabled when
either Wx or Cis at logic "1".

An internal latch is on the chip to provide the Write-WhileRead capability. When the latch control line, I, is logic
"1" and data is bei ng read from the 82S21, the latch is
effectively bypassed. The data at the output will be that of
the addressed word. When L goes from a logic "1" to logic
"0" the outputs are latched and will remain latched
regard!!ss of the state of any other address or control line.
When L goes from "0" to "1" the outputs unlatch and the
outputs will be that of the present address word.

(5) CE

FEATURES
• BUFFERED ADDRESS LINES
• ON CHIP LATCHES
• ON CHIP DECODING
• BIT MASKING CONTROL LINES
• ENABLE CONTROL LINE
• OPEN COLLECTOR OUTPUTS WITH
40mA CAPABI L1TY'

(6)

L--------.-,f--r----,....-+-.----,

Vee
GND
(

)

(16)
(8)
= Denotes Pin Numbers
=

• PROTECTED INPUTS
• VERY HIGH SPEEDS (25ns TYP)

TRUTH TABLE
CE

-C

-Wo

-W,

-L

X

X

X

X

0

Output Hold

Data from last addressed word when CE = "1"

0

X

X

X

1

Read & Write Disabled

Disabled logic "1"

1

1

X

X

X

Read

Data stored in addressed word

1

0

1

1

X

Read

Data stored in addressed word

1

0

0

0

0

Write Data

Data from last word address when L went from
"1 " to "0"

1
1

0

0

0

1

Write Data

Data being written into memory

0

0

1

X

Write Data into Bit 0 Only

If L = 0: Data from last word address when L went from
"1 " to "0"

1

0

1

0

X

Write Data into Bit 1 Only

If L = 1: Data being written into the selected bit location
and stored in other addressed location

Outputs

Mode

23

SIGNETICS 64-BIT HIGH SPEED WRITE-WHILE-READ ROM. 82S21
ELECTRICAL CHARACTERISTICS oOe ~ TA ~ 75°e; 4.75V ~ vee ~ 5.25
LIMITS
CHARACTE RISTICS

MIN.

TYP.

MAX.

UNITS

"0" Output Voltage

.45

V

"1" Output Leakage Current

40

/.LA

"0" I nput Current (All Inputs)

-1.6

mA

"1" Input Current (All Inputs)

25

/.LA

Input "0" Threshold Voltage

0.S5

Input "1" Threshold Voltage

NOTES

= 40mA
V out = 5.5V
Vin = 0.45V
Vin = 5.5V
V out

V

2.0

V

Power Consumption

130/683

Input Clamp Voltage

TEST CONDITIONS

mAlmW

-1.2

lin

= -lSmA

SWITCHING CHARACTERISTICS 0 ~ TA ~ 75 0 e, 4.75 ~ Vee ~ 5.25V
LIMITS
CHARACTERISTICS

MIN.

Read Access Time Address to Output

tl

Address Set-Up Time

t2

15

Data Set-Up Time

t3

20

Address Hold Time

t4

0

'TVP.

MAX.

UNITS

25

50

ns

S

ns

15

ns

15

ns

ns

Control or Write Pulse Width

t5

Write Access Time

ts

20

25

ns

t7

25

50

ns

Address to Latch Set-Up Time
Latch Address to Address Hold Time

ts

Delatch Access Time

tg

Data Hold Time Earliest

20

10

tlO

ACWAVEFORM

ns

7
15

5

TEST CONDITIONS

0

25

ns
ns

TEST LOAD

' ------£
'
--X:
Read Access Time

Ai

1.5V

--- ,

/__- _ t _ _ _
./
1

OJ

_______

I

1.5V

_ _ _ __

Goon

Address Setup and Hold Time

,,-.----------""'
,
I
\

- - _I, ""--________
1.5V

1.5V

-.J

~t2-./1-.I-----~----.

tr='tf ";;5ns,

't.v

INPUTVOLTAGE=2.8Volts

FIGURE 2

24

C)

150n

FIGURE 1

c~w

Vee

H

i;v

t4

NOTES

SIGNETICS 64-BIT HIGH SPEED WRITE-WHILE-READ ROM. 82S21
AC WAVEFORMS

-,I
Ij

I'---- _ _ _ _ _ _ JI

.I---~ tl0

1.5VI--t3
c"w

t'5V

\
Fig. 3

Data Setup and Hold Time

-------£1
1.5V
1 l-f t
l__
1.5V

OJ

-

I

I
t9~1

7

l

Ij

___

Je
I

-------

1-'·5v---

--~5V

--L

1.!Jv

I--ta--I

'5~\-

A;

_ _ _ _ _ _ _ __

l--

Fig. 5

·1

t

6

I

OJ
_______

Fig. 4

lc ______ _

---"'"'\1

I

CorW

_

~

1.5V

1

Latch Times

---

_ _ _ __

Write Access Time

TYPICAL APPLICATION

DATA INPUT

TO "S"
REGISTER

BASIC 8 BIT FULLY BUFFERED ACCUMULATOR
Sy use of the control lines So and S1 data is loaded into the "A" register through inputs Ox or from the outputs of the 74181's (EX) to
the 82S33's and stored in the 82S21's organized as a 32 x 8 RAM register. Data is loaded directly into the "S" register. With this arrangement, the function A+S A (A plus S into A) can be performed in 70ns, typically, starting from data stored in the 82S21's.

25

sinnoliCS
l!I

256-BIT BIPOLAR PROGRAMMABLE ROM 132 x 8 PROM]
[82S23 OPEN COLLECTOR)[82S123 TRI-STATE)
DIGITAL 8000 SERIES TTL/MEMORY

OBJECTIVE SPECIFICATION

82S23
82S123

DESCRIPTION

FEATURES

The 82523 (open Collector Outputs) and the 825123
(Tristate Outputs) are Bipolar 256 Bit Read Only Memories organized as 32 words by 8 bits per word. They are
Field-Programmable, which means that custom patterns are
immediately available by following the simple fusing procedure given in this data sheet. A chip enable line is provided and the outputs are bare collector or Tristate to allow
for memory expansion capability.

•

PNP INPUTS

•

BUFFERED ADDRESS LINES

•

ON THE CHIP DECODING

•

A CHIP ENABLE LINE

•

OPEN COLLECTOR OR TRISTATE OUTPUTS

•

DIODE PROTECTED INPUTS

•

NO SEPARATE "FUSING" PINS

•

BOARD PROGRAMMABLE

The 82523 and 825123 are fully TTL compatible and include on-the-chip decoding. Typical access time is 35 n5.

APPLIC~TIONS

PROTOTYPING
VOLUME PRODUCTION

The standard 82523 and 825123 are supplied with all outputs at a logical "0." If a programmed unit is required the
Truth Table/Order Blank on page 4-43 of the TTL M51/
Memory Handbook may be used.

CONTROL STORE

LOGIC DIAGRAM

INPUT/OUTPUT SCHEMATIC DIAGRAMS

MICROPROGRAMMING
HARDWIRED ALGORITHMS

INPUT SCHEMATIC
Vee

32x8ARRAY

~

~

~

~

~

OUTPUT SCHEMATICS

~

~

~

GND

=
=

(N)

= Denotes Pin Numbers

Vee

(16)
(8)

eE

82S23
26

82S123

SIGNETICS 256-BIT PROGRAMMABLE ROM. 82S23/123
SWITCHING CHARACTERISTICS 0 ~ TA ~ 75°C, 4.75 ~ VCC = 5.25V
LIMITS
CHARACTERISTICS

TEST CONDITIONS
MIN.

TYP.

MAX.

NOTES

UNITS

"0" Output Voltage

0.5

"0" Output Voltage

0.45

"1" Output Leakage

40

J.LA

lout = 9.6mA
CE = "1" V out = 5.5V

100

J.LA

CE = "O"Vout = 5.5V

12

+40

J.LA

V out = 0.5V IV out = 5.5V

12

mA

V out = 2.4V, CE = "0"

82S23
82S123

-40

V
V

lout = 20mA
12

CE = "1'
"1" Output Current 82S123

-2.0

"0" Input Current

-250

J.LA

Vin = 0.45V

"1" I nput Current

50

J.LA

Vin = 5.5V

After Fusing

Input Threshold Voltage
"0" Level

V

.85

"1" Level

V

2.0

Propagation Delay
Address to Output

35

Enable to Output

15

Input Calmp Voltage

50

ns

60

ns

30
35

ns
ns
V

-1.2

TA = 25°C only
TA = 25°C only
lin = -18mA

Power Consumption
82S23

80/400

115/605

mA/mW

82S123

80/400

115/605

mA/mW

Output Short Circuit Current

20

90

mA

Vout=OV

NOTES
1. All voltage measurements are referenced to the ground terminal. Terminals not specifically referenced are left electrically open.
2. All measurements are taken with ground pin tied to zero volts.
3. Positive current is definec as into the terminal referenced.
4. Positive logic definition: "UP" Level = "1", "DOWN" Level = "0".
5. Precautionary measures should be taken to ensure current limiting in accordance with Absolute Maximum Ratings should the isolation diodes
become forward biased.
6. Output sink current is supplied through a resistor to V CC.
7. One DC fan-out is defined as 0.8mA.
8. One AC fan-out is defined as 50pF.
9. Manufacturer reserves the right to make design and process changes and improvements.
10. By DC tests per the truth table, all inputs have guaranteed thresholds of 0.8V for logical "0" and 2.0V for logical "1".
11. F or detailed conditions, see AC testing.
'12. Connect an external 1k resistor from VCC to the output terminal for this test.

OBJECTIVE FUSING PROCEDURE
The 82S23/82S123 standard part is shipped with all outputs at Logical "0". To write a Logical "1" proceed as follows:
1. GND Pin 8 and apply 5V to VCC, Pin 16.
2.
Remove any load from the outputs.
Ground the Chip Enable.
3.
4.
Address the desired location by applying ground for a "0" and 5.0 ±0.25V for a "1" at the address input lines.
5.
Raise VCC to 10.0V ±0.5V.
6.
Apply 65 ±3' mA to the output to be programmed to logic "1". (The voltage will be between 12 to 18V until fused, and
must be clamped at 20.0V max.)
7.
Release fusing current.
8.
Reduce Vee to 5.0V.
9. Proceed to the next output and repeat, or change address and repeat procedure.
10. Continue until the entire bit pattern is programmed into your custom 82S23/82S123.
NOTE:
After 1.0 SEC of programming, a 25% duty cycle on power must be imposed to avoid over heating.

27

SIGNETICS 256-BIT BIPOLAR PROGRAMMABLE ROM. 82S23/123
AC TEST FIGURE AND WAVEFORMS

___ :tfr-INPUT

5V

INPUT PULSE:

----

5V

AMPLITUDE

tr

= tf = 5ns

= 3.0V

PW = 200ns (50% DUTY CYCLE)
INPUT OR
tON_

_-...1..._'

270n

30pF

OUTPUT
OUTPUT
OUTPUT PULSE

,, ' -_ _J
I

':'

28

':'
- : TON
GROUND PIN 15 WHEN TESTING ADDRESS·OUTPUT DELAYS

:..-

I

~

,

TOFF : - -

l!:nnnt:1I1!

1.n?4
AMMARI
-_. RIT
-.. RIPnl
-.. -_.AR... .PRnr,R
.. --...........
.---Fin"
0 l. r""
l. 0
~

iII!I,II": LI . . iII

ROM [256x4 PROM)

82S29

DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION

APPLICATIONS

The 82S26 (open Collector Outputs) and the 82S29 (tri
State Outputs) are Bipolar 1024 Bit Read Only Memories
organized as 256 words by 4 bits per word. They are FieldProgrammable, which means that custom patterns are
immediately available by following the simple fusing procedure given in this data sheet. Two chip enable lines are
provided and the outputs are bussable to allow for memory
expansion capability.

PROTOTYPING
VOLUME PRODUCTION
MI CROPROG RAMMING
HARDWIRE ALGORITHMS

The 82S26 and 82S29 are fully TTL compatible and include
on-the-chip decoding. Typical access time is 35ns.
The standard 82S26 and 82S29 are supplied with all outputs at a logical "0". If a programmed unit is required the
Truth Table/Order Blank on page 4-44/45 can be used.

CONTROL STORE
FEATURES
•
•
•
•

BUFFERED ADDRESS LINES
ON THE CHIP DECODING
TWO CHIP ENABLE LINES
OPEN COLLECTOR OR TRI STATE
OUTPUTS

• DIODE PROTECTED INPUTS
•
•
•

NO SEPARATE "FUSING" PINS
UNPROGRAMMED OUTPUTS ARE
"0" LEVEL
BOARD LEVEL PROGRAMMABLE

LOGIC DIAGRAM
Vee

r -_ _-

----------------------1---t---1-------o(16)

__

.., 82S29 ONLY

I

I
I

I

BO

..,::=----.........0 (12)

-=
(6)~

t:

(7~y

t=:

(4~

t:

(3t~

~

(2~y

t=:

(1~y

(15)Y

h

~

PROGRAM
-MING

-=

~

GND(8)

( ) DENOTES PIN NUMBER

29

81GNETIC8 1024-BIT PROGRAMMABLE ROM. 82826/29

PROGRAMMING
82S26 AND 82S29 PROGRAMMING PROCEDURE
1. Connect pin 8 (Grnd) to ground.
2. Disable the device by bringing CE1 and/or CE2 to a
logical "1" (greater than 2.6 volts). If only one CE pin is
used for the control of programming the other CE pin
'.ihould be at logical "0" (0.4 volts or less).
3. Raise VCC (pin 16) to 12.5 ±0.5 volts. (A 10J,lF in
parallel with a 200pF high frequency capacitor should
be connected between pins 16 and 8, as near the device
as possible, to minimize noise on the VCC line.)
4. Address the word to be programmed, using standard
TTL logic levels. Apply 85 ±5mA into the output to be
programmed to a logical "1". The output must be
limited to 22 volts ±5% and only one output at a time
should be programmed.
5. Wait until the current generator has reached the 22 volt
clamp. (The current generator will be supplying about
50mA min.) Then drop both CE1 and CE2 to a logical
"0" for 2.0msec. (fall time ~50Jlsec).
6. Return CE 1 and/or CE2 to a logical "1" for 10
microseconds.
7. Repeat steps 5, 6, and 7 until the entire word has been
programmed. Change address and repeat steps 5, 6, and
7 until the entire device is programmed. At this point
VCC can be dropped to 5.0 volts and the chip enabled so
that the outputs can be tested to verify that all bits
programmed; if one or more bits have not programmed,
return to the proper address and repeat steps 3 to 6 once
for each unprogrammed bit.
NOTE: Do not apply the high VCC (12.5 volts) for
greater than 1.0 seconds continuously. At that point use
a 20% duty cycle.

are programmed, one at a time, by means of four doublepole, double-throw (DPDT) switches. This arrangement has
the advantage that the switches are normally in the verify
mode, indicating the state of the output (logic "0" when
not programmed). By switching to the programming position, the outputs may be altered to a logic "1" which will
tU,rn on the light emmiting diode (LED) indicator. Upon return to the verify position the LED indicator will stay lit
for a programmed bit position.
Once the switch is in the programming position, it may remain there as long as the operator wishes. The total programming cycle is set up to last only for 5ms and is controlled by one-shots as shown in the timing diagram, Fig. 2.
The programmer timing follows the recommendation of
the Signetics revised programming procedure and is easily
adaptible to automatic programming and duplicating equipment.

CIRCUIT DESCRIPTION
Activating one of the four programming switches triggers
one-shot No. 1 for 5 milliseconds. This activates gate
No. 1 of the peripheral driver (75451) and, by releasing
zener diode No.1, VCC is raised to 12.5V for 5 milliseconds
while the 82S26 or 82S29 chip is disabled. (It should be
mentioned that use of the 74121 eliminates contact bounce
problems since it is non-retriggerable.)
After a time delay of 1 millisecond generated by one-shot
No.2, one-shot No.3 is turned on. This turns off the output transistor of gate No.2 of the 75451, enabling the programming current source. The constant current generator
consists of LM309 No.3 that is clamped to 22Vby zener
diode No.2. The programming current is determined by
the 59 ohm resistor and maintained at a constant 85mA.
An additional time delay of 1 millisecond, established by
one-shot No.4, guarantees that even slow current sources
have rei;lched the required current before the chip is enabled
for 2ms to open the NiCr link. One-shot No.5 establishes
the chip enable (CE) signal and thus the programming time.

OPERATION OF THE 82826/82829
PROGRAMMER

Figure 2 shows that VCC for the memory is held at 12.5V
for an additional 1 millisecond before the output of oneshot No.1 allows the supply to return to 5V.

INTRODUCTION

The two time delays of 1 millisecond generated by oneshots No.2 and No.4 can be shortened to the microsecond
range for automatic programming equipment if fast switching and a fast current source, as the one discussed above,
are chosen. Should it be desired to make the programmer
self-contained, a power supply suggestion is also shown in
Figure 2.

Figure 1 shows the complete programmer schematic. The
memory to be programmed is inserted, and by means of
seven single-pole, double-throw (SPDT) switches, the binary
address is selected. Notice that these switches may easily be
replaced by thumbwheel switches. The memory outputs

30

SIGNETICS 1024-BIT PROGRAMMABLE ROM. 82S26/29

PROGRAMMER
82826-82829
Vee

60----r---'>III-....-I----Ovee

~TRONIX

J
LlTRONIX

FIGURE 1

POWER SUPPLY AND WAVEFORMS

FUNCTION
12VTO 14V

->-_--0

+30V-35V

74121

{
"'" {

'"''
12VTO 14V

)6--10---<> +15V-18V
2000!,F
20V

ONE
SHOT 1

1_5ms_1

FROM VCC CONTROL

n

+5V-12.5V

ONE
S H O T 2 - - - 1ms
ONE
SHOT 3
ONE
SHOT 4
ONE
SHOT5

DELAY

-~

----'n...-

FUSE CURRENT
GENERATOR

1ms

-11-

DELAY

FROM CE

FIGURE 2
31

SIGNETICS 1024-BIT PROGRAMMABLE ROM -82S26/29
ELECTRICAL CHARACTERISTICS oOe ~ TA ~ 75°e ; 4.75V ~ Vee ~ 5.25
LIMITS
CHARACTE R ISTICS

TEST CONDITIONS
TYP.

MAX.

UNITS

0.5

V

"1" Output Leakage (82S26)

40

J..LA

CE1 or CE2 = "1 ", V out = 5.5V

(82S29)

100

J..LA

CE1 = CE2 = "0", V out = 5.5V

(82S29)

+40

J..LA

CE1 or CE2 = "1", V out =.45 to 2.4V

mA

CE1 = CE2 = "0", V out = 2.4V

MIN.
"0" Output Voltage

-40

"1" Output Current (82S29)

-2.0

lout = 16mA

"0" Input Current

-250

J..LA

Vin = 0.45V

"1" Input Current

50

J..LA

Vin = 5.5V

Input Threshold Voltage
"0" Level

.85

V

"1" Level

2.0

V

Power Consumption (82S26)

105/525

130/685

mA/mW

(82S29)

115/575

145/760

mA/mW

Input Clamp Voltage
Output Short Circuit Current

1.2

V

-20

mA

-70

SWITCHING CHARACTERISTICS 0 ~ T A

lin = -18mA
V out = 0 Volts

~ 75°e, 4.75 ~ Vee ~ 5.25V
LIMITS

CHA RACTE R ISTICS

TEST CONDITIONS
TYP.

MIN.

MAX.

UNITS

Propagation Delay
Address to Output

Chip Enable to Output

60

ns

70

ns

25

ns

30

ns

T A = 25°C only

T A = 25°C only

NOTES
1. Positive current is defined as into the terminal referenced.
2. Manufacturer reserves the right to make design an(i" process changes and improvements.

AC TEST FIGURE AND WAVEFORM

INPUT PULSE:
AMPLITUDE = 3.0V

Vec

=

tr tf = 5ns
PW = 200ns (50% DUTY CYCLE)

vee

INPUT

Vce

Ao

p.OV
INPUT OR
CHIP SELECT

Al

°1

AJ
PULSE

270n

OJ

AS

°4

At;
A7
CEl

-~

r"'"

OUTPUT
OUTPUT

GND

-=Ground Pins 13 and 14 when testing address-Output delays

32

toff

I
I
I
I

°2

A.t

CE2

I

~

A2

GENERATOR

f--

I

~

ton

PW

-------I
I

--..,

ton

..~innntil!l:
;., ......... ...

ECl HIGH PERFORMANCEI1 n1 ')"
256.PROM I U I \J \J
DIGITAL 54/74 TTL SERIES

PRELIMINARY INFORMATION
DESCRIPTION

FEATURES

The 10139 is an ECl 256-Bit Read Only Memory organized
as 32 words with 8 bits per word. The words are selected by
five binary address lines; full word decoding is incorporated
on the chip. A chip enable input is provided for additional
decoding flexibility, which causes all eight outputs to go to
low state when the chip enable input is high. This-device is
fully compatible with all of Signetics series 10,000 products. Address to output access time is 15 ns typical. Power
dissipation is 580 milliwatts typical with separate internal
bond wires and metal systems for V CC 1 and V CC2. The
10139 may be programmed to any desired pattern by the
user. The 10139 is suitable for use in high performance
ECl systems. A Truth Table/Order Blank is attached.

•
•
•
•
•
•
•

TEMPERATURE RANGE
-30 to +85°C Operating Ambient
RECOMMENDED OPERATING VOLTAGE
VCC = GND, VEE = -5.2V ±5%

15 ns TYPICAL ACCESS TIME
16 PIN PACKAGE
EASY PROGRAMMING
FULLY DECODED
FULLY COMPATIBLE WITH ECL 10,000 SERIES
HIGH IMPEDANCE INPUTS 50K OHM PUlLDOWN
OPEN EMITTER OUTPUTS

APPLICATIONS
PROGRAMMABLE LOGIC
CONTROL STORES
MICROPROGRAMMING
VOLUME PRODUCTION
HARDWIRED ALGORITHMS

PACKAGE TYPE
F: 16 Pin CERDIP

BLOCK DIAGRAM
VCC~(1~6~)____________________________________~~--._----------------~

(15)
CEo--~

SIGNETICS ECl HIGH PERFORMANCE 256-PROM. 10139
PRELIMINARY ELECTRICAL CHARACTERISTICS (TA = +25°C, vcc = OV, RL = 50[2, VEE = -5.2V)
CHARACTER ISTIC

SYMBOL

MIN

TYP

MAX

UNIT

110

145

mAdc

265

MAdc
MAdc

Power Supply Drain Current

lEO

I nput Current
VIH = -0.B10V,
VIL = -1.B50V

lin H
lin L

30

Logic "1" (VIH = -0.B10V, VIL = -1.B50V)

VOH

-0.960

-0.B10

Vdc

Logic "0" (VIH = -0.B10V, VILA = 1.B50V)

VOL

-1.990

-1.650

Vdc

Logic "1" (VIHA = -1.105V, VILA= -1.475V)

VOHA

-0.9BO

Logic "0" (VIHA = -1.105V, VILA = 1.475V)

VOLA

Output Voltage

Threshold Voltage

PRELIMINARY ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC
CHARACTERISTIC

SYMBOL

Chip Enable Prop Delay

-1.630

Vdc

= OV, VEE = -5.2V, RL = 50[2)

MIN

TYP
10

MAX

UNIT

15

ns

Output Rise Time (20 to BO%)

4.2

ns

Output Fall Time (20 to 80%)

4.2

ns

Access Time Address to Output

34

Vdc

TAD

15

20

ns

SIGNETICS ECl HIGH PERFORMANCE 256-PROM. 10139
RECOMMENDED PROGRAMMING
PROCEDURE

STEP6
If verification is positive, proceed to the next bit to be
programmed.
AUTOMATIC (see Fig. 2)

The 10139 is shipped with all bits at logical "0" (low). To
write logical"1's", proceed as follows:

STEP 1
Connect VEE (Pin 8) to ground and VCC (Pin 16) to +5.2
volts. Apply the proper address data and raise VCC (Pin 16)
to 12 volts.

MANUAL (see Fig. 1)
STEP 1
Connect VEE (Pin 8) to ground and VCC (Pin 16) to +5.2
volts. Address the word to be programmed by applying
4.0 to 4.6 volts for a logic "1" and 0.0 to 1.0 volts fOr a
logic "0" to the appropriate address inputs.

STEP 2
After a minimum delay of 100 IlS and a maximum delay of
1.0 ms, apply a 2.5 mA current pulse to the first bit to be
programmed (0.5::::;;; PW::::;;; 1 ms).

STEP 2

STEP3

Raise VCC (Pin 16) to 12 volts.

Repeat Step 2 for each bit of the selected word specified as
a logic "1". (Program only one bit at a time; The delay
between output programming pulses should be equal to or
less than 1.0 ms.)

STEP3
After VCC has stabilized at 12 volts (including any ringing
which may be present on the V CC line) apply a current
pulse of 2.5 mA to the output pin corresponding to the bit
to be programmed to a logic "1".

STEP4
After all the desired bits of the selected word have been
programmed, change address data and repeat Steps 2 and 3.

STEP4

NOTE: If all the maximum times listed above are maintained, the

Return V CC to 5.2 volts.

entire memory will program in less than 1 second. Therefore, it

CAUTION: To prevent excessive chip temperature rise, VCC should

would be permissible for V CC to remain at 12 volts during the

not be allowed to remain at 12 volts for more than 1 second.

~ntire

STEP 5

STEP 5

Verify that the selected bit has program.med by connecting
a 460[2 resistor to ground and measuring the voltage at the
output pin. If a logic "1" is not detected at the output, the
procedure should be repeated once.

After stepping through a" address words, return VCC to
+5.2 and verify that each bit has programmed. If one or
more bits have not programmed, repeat the entire procedure once.

programming time.

PROGRAMMING SPECIFICATIONS
LIMITS
CHARACTERISTIC

SYMBOL

Power Supply Voltage
To Program
To Verify

VCCP
VCCV

Programming Supply Current

ICCp

Address Voltage
logical"1"
logical "0"

VIH
VIL

TYP.

MAX.

11.5
5.0

12.0
5.2

12.5
5.4

Volts
Volts

250

mA

4.6
1.0

Volts
Volts

1.0

Sec.

3.0

mA

1.0

ms

4.0
0.0

Max. Time at VCC = Vccp
Output Programming Current

lOp

2.0

Output Program Pulse Width

tp

0.5

OutpU! Pulse Rise Time
Programming Pulse Delay (1)
following VCC change
between output pulses

UNITS

MIN.

2.5

10
td
td 1

0.1
0.01

1.0
1.0

CONDITIONS

VCC = 12.0 Volts

Ils

ms
ms

NOTE:
(1) Maximum is specified t6 minimize the amount of time VCC is at 12 volts.

35

SIGI\IETICS ECl HIGH PERFORMANCE 256-PROM • 10139
MANUAL PROGRAMMING CIRCUIT

+20V
+12V +5.2V

PROGRAM

11

3K

VERIFY

(M~~T~Y~--i
~--~16---I

ADDRESS

~T-TEST
:

POINT

-=

I

I

4600

!

OUTPUTS

-=

I

I

I
CE
OPEN

8
7.5K
(ALL OUTPUTS)

AUTOMATIC PROGRAMMING CIRCUIT

ADDRESS

.-J

f

I

1

I

I

I

~.-J

I

1
I

1
1123

I
1
td _ _ 1

1

L
I

I
I

8:'23

L(~

1

I

8

1

I
12

y~

8

L(~

I

I

I

1......1 - - - - - - - - - - - . ; ; 1

1

I

I --I l_ t d1
1__
I

I

nl . -

I

--I I--tp

36

22

nnn n,nnn
n:nn
--..J LJ LJ
LLJ LJ LJ
LLJ LJ
1

OUTPUT

u

U

I

SECONDI-~--------~~~

f

!;innntie!:
-;-,--- ----

Eel 64x1 RAMSI1n14n
-30 to +85°C CERDIP
ADVANCED INFORMATION

DIGITAL 10,000 Eel SERIES
DESCRIPTION

1014 8
•

'WI'

••

Wi'

10151

LOGIC DIAGRAM

The 10140, 10148 and 10151 are 64 Bit ECl Random
Access Memories (RAM's) organized as 64 words with 1 bit
per word. The words are selected by six binary address
lines; full word decoding is incorporated on the chip. Two
chip enable input lines are provided for additional decoding
flexibility. The chip is disabled when either chip enables are
high, which causes the output of the 10140 and 10148 to
go low.

ADDRESS INPUTS

I

The 10151 has an internal latch on the chip to provide the
Write-While-Read capability. When the latch control line, l
is a "1" and data is being read from the 10151 the latch is
effectively bypassed. The data at the output will be that of
the addressed word. When I goes from a logic "1" to logic
"0" the outputs are latched and will remain latched
regardless of the state of any other address or control line.
When l goes from "0" to "1" the outputs unlatch and will
take the state of the addressed word. The 10151 and 10148
logic levels are fully compatible with the 10,000 series and
are specified for driving a 50n load. The 10140 is
compatible with series 10,000 ECl except the output is
specified for driving a 90n load.

COLUMN
SELECT
GATES

CE1

(4)

CE2

(5)

DATA
OUT

(15)

16x 4
ARRAY

DATA IS HELD
IN THE OUTPUT
LATCH (10151
ONLY) WHENI
IS AT POSITIVE
LOGIC "0".

CHIP ENABLE
BUFFER

OUTPUT
BUFFER
AND LATCH
*(10151 ONLY)

THE CHIP IS
ENABLED WHEN
CE AND CE2
AREAT
POSITIVE
LOGIC "0".

SENSE AMPLIFIER

(A) = DENOTES PIN NUMBER
(1) =VCC1
(16) =VCC2
(8) = VEE
(14)

LATCH CONTROL

L

FEATURES
•

10 ns TYPICAL ACCESS TIME

•

16 PIN PACKAGE

•

ON THE CHIP LATCH (AVAILABLE ON 10151)

•

ON THE CHIP DECODING

•

TWO CHIP ENABLE CONTROL LINES

•

HIGH IMPEDANCE INPUTS 50k OHM PULL-DOWN

•

OPEN EMITTER OUTPUTS

TRUTH TABLE (10151)

- -

-

CE RW L

MODE

0
0
0
0
1

0
0
1
1
0

0 Write Data
1 Write Data
0 Read
1 Read
0 Chip Disabled

1
1

0
1

1 Chip Disabled
0 Chip Disabled

1

1

1 Chip Disabled

APPLICATIONS
SCRATCH PAD MEMORY
BUFFER MEMORY
ACCUMULATOR REGISTER
CONTROL STORE

OUTPUTS

Data stored in addressed word
Data stored in addressed word
Data from last address when
CE = "0"
logical "1"
Data from last address when
CE = "0"
logical "1"

37

SIGNETICS ECl 64x1 RAMS. 10140, 10148, 10151
ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

Power Supply Voltage
(VCC = 0)

VEE

-8

Vdc

CHARACTE RISTIC

UNIT

Input Voltage (VCC = 0)

Yin

o to VIL min

Vdc

Output Source Current

10

40

Storage Temperature Range

Tstg

mAdc
°c

Operating Junction Temperature

TJ

110

Operating Temperature Range

TA

-30 to +85

-

±10%
±5%

Power Supply
Regulation Required
VCCl

-55 to +125

°c
°c

-

= VCC2 = Gnd

SWITCHING CHARACTERISTICS T A

= 25°C, RL = 50n for 10148 and 10151, RL = 90n for 10140

CHARACTER ISTIC

SYMBOL

MIN

TYP

MAX

UNIT

Chip Enable
Turn-On

tCE-D+

-

8

12

Turn-Off

tCE+D-

-

8

12

ns

Access Ti me for Add ress to Output
tA+D+

-

10

15

tA+D~

-

10

15

tA-D+

-

10

15

tA-D-

-

10

15

Write Pulse Width

tw(R/W)

10

ns

ns

Chip Enable Pulse Width

tw(CE)

13

ns

Set-Up Time for Data to Write

tset(D±R/W+)

10

ns

Set-Up Time for Data to Chip Enable

tset(D±CE+)

10

ns

Set-Up Time for Write to Chip Enable

tset(W-CE+)

10

ns

Set-Up Time for Chip Enable to Write

tset(CE-R/W+)

13

ns

Set-Up Time for Data to Latch (10151 only)

tset(D±I-)

ns

Set-Up Time for Latch Release to Data (10151 only)

tset(l+D±)

ns

Set-Up Time for Latch to Address (10151 only)

tset(I-A±)

ns

ELECTRICAL CHARACTERISTICS TA = 25°C, RL = 50n for 10148 and 10151, RL = 90n for 10140
CHARACTERISTIC
Power Supply Drain Current
(VEE = -5.2 V)
I nput Current
(VIH = -0.810 V, VEE = -5.2 V)
(VI L = -1.850 V, VEE = -5.2 V)
Output Voltage
Logic "1"
(VIH = -0.810 V, VI L = -1.850 V, VEE = -5.2 V)
Logic "0"
(VIH = -0.810 V, VIL = -1.850 V, VEE = -5.2 V)
Threshold Voltage
Logic "1"
(VIHA = -1.105 V, VILA = -1.475 V, VEE = -5.2 V)
Logic "0"
(VIHA = -1.105 V, VILA = -1.475 V, VEE = -5.2 V)

38

SYMBOL

MIN

TYP

MAX

UNIT
mAdc

lEO

-

80

-

-

265

0.5

-

-0.960

-

-0.810

-1.990

-

-1.650

-0.980

-

-

-

-

,uAdc
linH
linL

-

Vdc

VOH

Vdc

VOL

Vdc

VQHA

Vdc

VOLA
-1.630

SIGNETICS ECl 64x1 RAMS. 10140, 10148, 10151
'TII\IIII\I~

1"\1

A~D

• . . . . . . . ,. '-I ""1""\.'-1'

AI\IIC"

11""\.1"'~

WRITE TIMING DIAGRAMS-WRITE STROBE MODE

~
1

I

\

-r --------:- -'i
1

tset(D±R/W)
10min

-

•

I

I '------

;:'3ns~

-DIN--:11

__ +.i ,

1

1

1

C<:

i-I

13 mm

'\

:

tw(R/W)----.I_;;:.Ons~

"I_

1_;:'5ns

W

r

.1\.- __

I . - - - tset(CE-R/W+) _ _ _ _ ;:.3 ns---.l

10mm

\

-I

I

1

!--twr __1

_ _ _~l'--

DOUT

.

READ TIMING DIAGRAM

t-----=-----'t
----Jl

...1..1------\*:-

ci\:£<

D_o_uT_ _ _ _ _ _'_
..

~\.,~

~------------------It~ ----------

:u:-------:-y

----------+-I-...J· I\..- - - - - - - ~:::~~
I tA-D+
I
tA-D15 MAX

CHIP ENABLE STROBE MODE

~,

-CE

>OM"

1---

10151 LATCH TIMING DIAGRAM

'ou,

X----------¥
~t
1

___ J

1'

--I

I--- LSET(D±L-)

-I

. 1'-_- - j--LSET(L+D±)

L-

_____ J,~______
---I

I- tSET(L-A±)

--------..;...-Ir-----------

~

39

!ii!ln~tiC!i

10145

Eel 16X4 RAM
10145 F, I

-30°C to +85°C

DIGITAL 10,000 Eel SERIES
BLOCK DIAGRAM

DESCRIPTION
The 10145 is an ECl 64-bit read-write random access
memory organized as 16 words of 4 bits each. Words are
selected through fully decoded and buffered inputs when
the chip enable (CE) is low. Data is written into the selected word by bringing the READ/WRITE input low. Cutputs are low during write.
On-chip input pulldown resistors allow any unused inputs
to be left open. Open emitter outputs allow corresponding
bits of different devices to be tied together to form a
"Wire OR" logic connection.

Ao
A1
A2
A3

The 10145 utilizes separate internal metal systems and wire
bondsforVCC1 and VCC2. The exceptionally high speed of
the 10145 makes it particularly suited for register file and
and scratch pad appl ications.

CE

Vii

(10)
(9)

(7)
(6)

ADDRESS
BUFFERS
AND
DECODER

MEMORY
MATRIX
16X4

...,;.(3...:....)_ _~_ _

---1
DATA BUFFERS

(13)

FEATURES
•

8.5n5 ADDRESS ACCESS TIME (TYP)

•

INPUT PUlLDOWN RESISTORS

•

OPEN EMITTER OUTPUTS AND CHIP ENABLE INPUT FOR MEMORY EXPANSION

•

50 Ohm OUTPUT SPECIFICATION

•

SINGLE -5.2V POWER SUPPLY

•

FULLY DECODED INPUTS

•

FULLY
COMPATIBLE WITH SIGNETICS 10,000
SERIES FAMILY OF INTEGRATED CIRCUITS

(8) = VEE
(16) =Vcc
( ) = DENOTES PIN NUMBER

100 0 1 O2 03 00 01 02 0
.
31
11

I

I

DATA
INPUTS

DATA
OUTPUTS

APPLICATIONS
SCRATCH PAD MEMORIES
BUFFER MEMORIES
REGISTER FILES
CONTROL STORES

PACKAGE TYPES
F:
I:

16 Pin Cerdip
16 Pin Laminated Ceramic

ELECTRICAL CHARACTERISTICS VEE = -5.2V, VCC = OV, Rl = 50n TO -2.0V
CHARACTERISTIC
Supply Current

SYMBOL

CONDITIONS

4, 5, 11, 12)

40

UNITS

116

145

rnA

25°C

200

JiA

IINH

VIN

MAX.

25°C

220

JiA

IINH

VIN = VIH MAX.

25°C

455

JiA

IINL

VIN

I nput Current
(All Inputs)

MAX.

VIN= VIH MAX.

= VIH

Input Current
(Pin 13)

TYP.

IINH

Input Current
(Pin~

MIN.

25°C

IE

Input Current
(Pins 3,6, 7, 9, 10)

TEMP.

= VIL

MIN.

25°C

0.5

JiA

SIGNETICS ECl 16x4 RAM. 10145
ELECTRiCAL CHARACTERiSTiCS (Cont;d)
CHARACTERISTIC

Output Voltage

Output Voltage

Output Voltage
(Threshold)

SYMBOL

VOH

VIN = VIH MAX.,
VIL MIN.

VOL

VIN = VIH MAX.,
VIL MIN.

VOHA

Output Voltage
(Threshold)

CONDITIONS

VOLA

VIN = VIHA, VILA

VIN = VIHA, VILA

MAX.

UNITS

-1.06

-.89

Vdc

25°C

-.96

-.81

85°C

-.89

-.70

TEMP.

MIN.

-30°C

TYP.

-30°C

-1.89

-1.675

25°C

-1.85

-1.65

85°C

-1.825

-1.615

-30°C

-1.08

25°C

-.98

85°C

-.91

Vdc

Vdc

-30°C

-1.655

25°C

-1.63

85°C

-1.595

Vdc

SWITCHING CHARACTERISTICS VEE = -3.2V, VCC = 2V, RL = 50[2 TO GND
CHARACTERISTIC
Access Time - Chip Enable to Output
Address to Output

MIN.

SYMBOL

TYP.

MAX.

UNITS

tCE-Q+,tCE+Q-

5.0

ns

tA + Q+, tA- Q+

8.5

ns

tA+ Q-, tA- Q Write Strobe Mode
tSET(D± R/W+)

7.5

ns

Chip Enable Set-up

tSET(CE- R/W+)

11.0

ns

Address

Data Set-up

tSET(A± R/W-)

3.5

ns

Data Hold

tHOLD(D+ R/W+)

3.0

ns

Chip Enable Hold

tHOLD(CE,+ R;W+)

3.0

ns

tHOLD(A+ R/W+)

3.5

ns

tRNv+ Q+, tR/W+ Q-

7.5

ns

tW(R/W)

7.5

ns

Data Set-up

tSET(D± CE +)

7.5

ns

Read/Write Set-up

tSET( R/W- CE +)

Address Hold
Recovery Time
Write Pulse Width
Chip Enable Strobe Mode

Address Set-up
Data Hold

11.0

ns

tSET(A±CE -)

3.0

ns

tHOLD(D+CE+)

3.0

ns

Read/Write Hold

tHOLD(R/W + CE +)

3.0

ns

Address Hold

tHOLD(A+ CE+)

3.0

ns

tW(CE)

7.5

ns

Chip Enable Pulse Width
Rise Time (20%-80%)

t+

2.5

ns

Fall Time (20%-80%)

C

2.5

ns

TEST VOLTAGE VALUES
Vdc ± 1%
@Test
Tern perature

VIH max

VILmin

VIHAmin

VILA max

VEE

-30°C

-0.890

-1.890

-1.205

-1.500

-5.2

+25°C

-0.810

-1.850

-1.105

-1.475

-5.2

+85°C

-0.700

-1.825

-1.035

-1.440

-5.2

41

SIGNETICS ECl 16x4 RAM. 10145
TIMING DIAGRAMS
WRITE CYCLE
READ/WRITE STROBE MODE

ADDRESS

I~----- tset(D± R / W + ) - - - - -...~I~ -1tJold(A+ R/W+)

DATA IN

~---tset(CE - R/W+) - - - -...~I ......J - - - -....~~I- \'old(D+ R/W+)
1.....

CHIP ENABLE

\'old

(CE+R/W+)~

READIWRITE

'------

WRITE CYCLE
CHIP ENABLE STROBE MODE

ADDRESS

1-4------tset(D± CE+)-----~~~I·...........---i~~I-1tJold(A+ CE+)

DATA IN

READ/WRITE

CHIP ENABLE

1 4 - - - - - - - - t s e t ( R / W - CE+)-------~

42

SIGNETICS ECl 16x4 RAM. 10145
TiMiNG DiAGRAMS

(Com:dj

READ CYCLE

CHIP ENABLE

ADDRESS

I

)\

~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

_ _ _ _ _ _ _ _ _ _ _ __ J

°OUT

~{

--------~--~/\---------------------------t A +O+
4 - - tA+O_----.
tA-O+
tA-O-

WRITE/READ CYCLE

AD DRESS

\(

J\

.

..

..

\

-

R/W

..
CH IP ENABLE

DA TAOUT

\

.

)V1\

DA TAIN

t (A± R/W-)

tset (A± R/W+)

tw(R/W)

\

..

/
tset (CE - R/W+)

/

..

tR/W + 0+
tR/W + Q-

~

/

.V

43

CUSTOMER ORDERING INFORMATION
N8205
N8204
N8204

ASCII-TO-EBCDIC, EBCDIC-TO-ASCII
ASCII-TO-EBCDIC CODE CONVERTER
EBCDIC-TO-ASCII CODE CONVERTER

- CB 175
- CB504
- CB505

ASCII (ADDRESS) TO EBCDIC (DATA)

o
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
124

00000000
00110111
00010110
00001100
00010000
00111100
00011000
00011100
01000000
01011011
01001101
01101011
11110000
11110100
11111000
01001100
01111100
11000100
11001000
11010011
11010111
11100011
11100111
11100000
01111001
10000100
10001000
10010011
10010111
10100011
10100111
01101010

1
5
9
13
17
21
25
29
33
37
41
45
49
53
57
61
65
69
73
77
81
85
89
93
97
101
105
109
113
117
121
125

2 00000010
3 00000011 128 00100000 129
00000001
7 00101111 132 00100100 133
6 00101110
00101101
10 00100101
11 00001011 136 00101000 137
00000101
14 00001110
15 00001111 140 00101100 141
00001101
18 00010010
19 00010011 144 00110000 145
00010001
22 00110010
23 00100110 148 00110100 149
00111101
27 00100111 152 00111000 153
00011001
26 00111111
30 00011110
31 00011111 156 00000100 157
00011101
34 01111111
35 01111011 160 01000001 161
01001111
01101100
38 01010000
39 01111101 164 01000101 165
42 01011100
43 01001110 168 01001001 169
01011101
46 01001011
01100000
47 01100001 172 01010100 173
11110001
50 11110010
51 11110011 176 01011000 177
54 11110110
11110101
55 11110111 180 01100100 181
11111001
58 01111010
59 01011110 184 01101000 185
01111110
62 01101110
63 01101111 188 01110010 189
11000001
66 11000010
67 11000011 192 01110110 193
11000101
70 11000110
71 11000111 196 10001010 197
74 11010001
11001001
75 11010010 200 10001110 201
11010100
78 11010101
79 11010110 204 10011011 205
11011000 82 11011001
83 11100010 208 10011111 209
11100100 86 11100101
87 11100110 212 10101100 213
11101000
90 11101001
91 01001010 216 10110000 217
01011010 94 01011111
95 01101101 220 10110100 221
10000001
98 10000010
99 10000011 224 10111000 225
10000101 102 10000110 103 10000111 228 10111100 229
10001001 106 10010001 107 10010010 232 11001010 233
10010100 110 10010101 111 10010110 236 11001110 237
10011000 .114 10011001 115 10100010 240 11011100 241
10100100 118 10100101 119 10100110- 244 11101010 245
10101'000 122 10101001 123 11000000 248 11101110 249
11010000 126 10100001 127 00000111 252 11111100 253

EBCDIC (ADDRESS) TO ASCII (DATA)

256
260
264
268
272
276
280
284
288
292
296
300
304
308
312
316
320
324
328
332
336
340
344
348
352
356
360
364
368
372
376
380

44

00000000
10011100
10010111
00001100
00010000
10011101
00011000
00011100
10000000
10000100
10001000
10001100
10010000
10010100
10011000
00010100
00100000
10100011
10100111
00111100
00100110
10101100
10110000
00101010
00101101
10110100
10111000
00100101
10111010
10111110
11000010
01000000

257
261
265
269
273
277
281
285
289
293
297
301
305
309
313
317
321
325
329
333
337
341
345
349
353
357
361
365
369
373
377
381

CB175 FIRST HALF
CB504

8205
8204

00000001
00001001
10001101
00001101
00010001
10000101
00011001
00011101
10000001
00001010
10001001
00000101
10010001
10010101
10011001
00010101
10100000
10100100
10101000
00101000
10101001
10101101
10110001
00101001
00101111
10110101
10111001
01011111
10111011
10111111
01100000
00100111

258
262
266
270
274
278
282
286
290
294
298
302
306
310
314
318
322
326
330
334
338
342
346
350
354
358
362
366
370
374
378
382

00000010
10000110
10001110
00001110
00010010
00001000
10010010
'00011110
10000010
00010111
10001010
00000110
00010110
10010110
10011010
10011110
10100001
10100101
01011011
00101011
10101010
10101110
01011101
00111011
10110010
10110110
01111100
00111110
10111100
11000000
00111010
00111101

00000011
01111111
00001011
00001111
00010011
10000111
10001111
00011111
10000011
00011011
10001011
00000111
10010011
00000100
10011011
00011010
10100010
10100110
00101110
00100001
10101011
10101111
00100100
01011110
10110011
10110111
00101100
00111111
10111101
11000001
00100011
00100010

130
134
138
142
146
150
154
158
162
166
170
174
178
182
186
190
194
198
202
206
210
214
218
222
226
230
234
238
242
246
250
254

00100010
00000110
00101010
00001010
00011010
00110110
00111010
00111110
01000011
01000111
01010010
01010110
01100010
01100110
01110000
01110100
01111000
10001100
10010000
10011101
10101010
10101110
10110010
10110110
10111010
10111110
11001100
11011010
11011110
11101100
11111010
11111110

131
135
139
143
147
151
155
159
163
167
171
175
179
183
187
191
195
199
203
207
211
215
219
223
227
231
235
239
243
247
251
255

00100011
00010111
00101011
00011011
00110011
00001000
00111011
11100001
01000100
01001000
01010011
01010111
01100011
01100111
01110001
01110101
10000000
10001101
10011010
10011110
10101011
10101111
10110011
10110111
10111011
10111111
11001101
11011011
11011111
11101101
11111011
11111111

CB175 SECOND HALF
CB505

8205
8204
259
263
267
271
275
2-79
283
287
291
295
299
303
307
311
315
319
323
327
331
335
339
343
347
351
355
359
363
367
371
375
379
383

00100001
00010101
00101001
00001001
00110001
00110101
00111001
00010100
01000010
01000110
01010001
01010101
01011001
01100101
01101001
01110011
01110111
10001011
10001111
10011100
10100000
10101101
10110001
10110101
10111001
10111101
11001011
11001111
11011101
11101011
11101111
11111101

384
388
392
396
400
404
408
412
416
420
424
428
432
436
440
444
448
452
456
460
464
468
472
476
480
484
488
492
496
500
504
508

11000011
01100100
01101000
11000110
11001010
01101101
01110001
11001101
11010001
01110101
01111001
11010100
11011000
11011100
11100000
11100100
01111011
01000100
01001000
11101010
01111101
01001101
01010001
11110000
01011100
01010101
01011001
11110110
00110000
00110100
00111000
11111100

385
389
393
397
401
405
409
413
417
421
425
429
433
437
441
445
449
453
457
461
465
469
473
477
481
485
489
493
497
501
505
509

01100001
01100101
01101001
11000111
11001010
01-1011·10
01110010
11001110
01111110
01110110
01111010
11010101
11011001
11011101
11100001
11100101
01000001
01000101
01001001
11101011
01001010
01001110
01010010
11110001
10011111
01010110
01011010
11110111
00110001
00110101
00111001
11111101

386
390
394
398
402
406
410
414
418
422
426
430
434
438
442
446
450
454
458
462
466
470
474
478
482
486
490
494
498
502
506
510

01100010
01100110
11000100
11001000
01101011
01101111
11001011
11001111
01110011
01110111
11010010
11010110
11011010
11011110
11100010
11100110
01000010
01000110
11101000
11101100
01001011
01001111
11101110
11110010
01010011
01010111
11110100
11111000
00110010
00110110
11111010
11111110

387
391
395
399
403
407
411
415
419
423
427
431
435
439
443
447
451
455
459
463
467
471
475
479
483
487
491
495
499
503
507
511

01100011
01100111
11000101
11001001
01101100
01110000
11001100
11010000
01110100
01111000
11010011
11010111
11011011
11011111
11100011
11100111
01000011
01000111
11101001
11101101
01001100
01010000
11101111
11110011
01010100
01011000
11110101
11111001
00110011
00110111
11111011
11111111

N82281 - CB 162 PATTERN
USASC II ROW CHARACTER GENERATOR
AO
Al

A2r.---------~--------+_~--------~--------_+_+----o----~-r--------+-+---------~r-------~-+---------i
A3
A4

0
0

0
0

0
1

1
0

1

1
0

1
1

1
1

A5~----~----O----_r~----1----+_~---O----_r1_----1----+_+_----0----~-----1----~+_---O~--~_r----1----;
As

A-,

.
..
..
•
•
......
......
I
•I...... :••
........:

A8r-~----._--_+_+----._--_r1_--_.----+_+_--_.----~r_--._--~_+----._--_+_r--~----+_+_--_.--__1

o

Ag

000

000
001
010
011
100
101
110
111

00 1

000
001
010
011
100
101
110
111

o

1 0

000
001
010
011
100
101
110
111

01 1

000
001
010
011
100
101
110
111

1 00

000
001
010
011
100
101
110
111

1 0 1

000
001
010
011
100
101
110
111

1 1 0

000
001
010
011
100
101
110
111

111

000
001
010
011
100
101
110
111

o

1

•••••

o

1

•••••••••
•••••••
••• •••

o

1

1

:

I

I

I

I

.-;

,

• • • 1• • •

I.•••••

I

I

I ••••••
~.

1

1•••

• •
••• •••
I.••••

:

II
••
I ••.

I
I
I
I ••••••

I

~.

I

•

1• •

I

I

~

.. r .......

• •••
•• ~ •• ••
••
••
••
••
••
: :

i

••

i.~.

•
••

•.J

••••••1
r~

I

II ••

..

••••
:.~
• •

•.~.

••
•

I·'~·
'--i•••
•..1•...•

II

.-Ie•

1

o

1

o

1

~

.~.:
~.

I
••
••
• •••••

!

I
i I • •:
J III·•

i
I

~

I

o

••••••
•••
•••••••

......... .. ..
• •
:
•••••••
.
.....
:•
..
...
: : •••••
.....
....•... ...
•• ••
......
•••••••
:
......•
I ••• :

o

• •
I
•
••••••I
• •

L!J
.......
•
.. •...• • •

..

._. I

•••••

I·

~

:.:.••

·i· ••••••
•••••••

••••
I

••
••

••
•••••
••
••
•
••
I...... I•••••••
• ••••••••• ••
•

.......•• .-•
.....
···eL' .......
..•••• .......
•• .:..
•
•••••••
•• ••
...
..
I·····:
•••••
.
....
•
•
.....
... ....... •
••
•••
...
•••
•.......• ••••••
•••••••
••••
•
....

•

~.

I • I
·I ......
. I

•

.

I

~.

I"~I

~~

.1

~

I

45

PUNCHED CARD PROGRAM INPUT FOR 8204 & 8205
The customer may specify the content of the ROM either by filling out the
accompanying form or by using punched cards. He should note that:
1.

"Zero" levels on data out lines are defined as low.

2.

Address bit AO is the least significant address bit.
(See 8204 and 8205 data sheet)

Punched Card Data Input - Data to program the 8205 and the 8204 can be
supplied in punched card-format. The format for the data is shown in
Figure 1. Each data word is preceded by an address word which identifies its

position in memory. Figure 2 shows the deck format for the 8204 256 x 8 bit
ROM. For the 8204 the first card in the deck contains the part number and
it is immediately followed by up to 40 alphanumeric characters of customer
supplied information used to identify the part. The 64 customer data cards
follow immediately. Figure 3 shows the deck format for the 8205 512 x 8
ROM. For the 8205 the first card in the deck contains the part number and it
is immediately followed by up to 40 alphanumeric characters of customer
supplied information used to identify the part. 128 data cards follow immediately. The left-most digit in the data word corresponds to output 08 and the
right-most digit to output 0 1,

I I I I I I I I I I 2 2 2 2 2 2 2 2 2 2 3 33 33 3 3 3 3 3 4 44 44 44 44 45 55 5 5 5 5 5 5 5 6 6 6 6 6 6 6 66 6 7 7 7 7 7 7 7 77 7 8
I 2 34 56 78 90 I 2 34 5 6 78 90 I 2 3 4 5 6 78 90 I 2 34 5 6 78 90 I 2 3 4 56 7 8 90 I 2 3 4 5 6 7 8 90 I 2 3 4 5 6 7 8 90 I 2 3 4 5 6 78 90
2
3
4

e

-

II:
0
I~

0

1:;(

f-O ~T ~i) I-H

IS

~

~

~

0

r-O AT ~j) I - I -

c(

II::
0

f-O AT

IA~ f-f-

c(

t-O AT AU)I-r-

003
007

I 10 10 101
I I I 10 o I I

5

FIGURE 1. CARD DATA FORMAT

6
7

8
9

r....1 ...

CU S~ ~~ E~

10 ~~ IV

II

ppp

12

pp~

IP I I 01 I I
I I QI IP I I

P~I

pp5

P~ ~rr 10
~~ op pp pp

I I 10 00 Op

13

,

1002 I I 00 I I I I
OP6 PO I I I I pO

64 CA R05

14
15

252 00 I I 00 00

253 00 00 10 Op

254 01 10 I I I I

255

101 10 000

16

FIGURE 2. DECK FORMAT FOR 8204 ROM (256x8)

17
18
19

20
21

~2 05

POP

10 I I 01 I I

25

5P~

26

508

10 I I Op 01
10 10 10 10

22
23

CU 5T ~M ER

PA RT 10
I I 10 I I I I

K:>02

I I 10 01 I I

003

10 I I 10 I I

505 Op pO Op pp
509 I I 01 10 I I

506
510

I I 101 101
10 001 I I I

507
5 I I

128
101 10 000
101 I I I 10

POI

24

27
28

29

30

FIGURE 3. DECK FORMAT FOR 8205 ROM (512x8)
111111111111111111 I I I I I I I I I I I I I111111

CA ROS

PUNCHED CARD PROGRAM INPUT FOR 8228
Punched card data to program can be transmitted directly to Signetics. Data
information to program the ROM requires 128 80-column IBM pu nched cards
per 4096 bit device and 64 punched cards per 256 bit device.

own part identification. These first three cards are then followed by 128
data cards. Immediately following are two cards to terminate the computer
run. These should be punched by the customer.
Data Cards

Input Deck Format
For each 4096 bit ROM, the customer should prepare an input card deck as
shown in Figure 1. The first two cards should be punched as shown and
placed at the start of the deck. The third card should contain "8228" in the
first four columns. In the next 40 positions, the customer should fill in his

Figure 2 shows the layout used in the data cards. Each data card specifies
eight addresses and the four bits of data associated with these addresses.
Address (i) tells the computer what position to assign Data (i) to etc.
Immediately under this, a typical layout for the first two and the last data
cards is shown.

INPUT CARD
I I I I I I I I I I 2 2 2 2 2 2 2 2 2 2 3 3 3 3 33 3 3 33 44 44 44 44 44 5 5 5 5 5 5 5 5 5 5 6 6 6 6 66 6 6 6 6 7 7 77 7 7 7 7 77 8
I 2 34 56 78 90 I 2 34 5 6 78 90 I 2 3 4 5 6 78 90 I 2 34 5 6 78 9 0 I 2 3 4 5 6 7 8 90 I 2 3 4 5 6 7 8 90 I 2 3 4 5 6 7 8 90 I 2 3 4 5 6 78 90

/1
2

3

JOB

I I XEQ
82 28

51 GRIM
'j

T

4

128

5
6
7

1*

8

II

CU 5T OIM ER PA RT

10

OA TA CA R05

T
J

*J OB ENO

9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
~

.....

30

FIGURE 1. DECK LAYOUT FOR 8228 DATA INPUT

DATA CARDS
1 I I 1 I I 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 33 33 3 3 33 44 44 44 44 44 5 5 5 5 5 5 5 5 5 5 6 6 6 6 66 6 6 6 6 7 7 77 7 7 7 7 77 8
1 2 34 56 78 90 1 2 34 5 6 78 90 1 2 34 5 6 78 90 1 2 34 5 6 78 90 1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 78 90
1

.,

.,

3

~

4

c(

..

2

0

I~
...J
III

C

0

:!

..
0
0

...J
III

....

.Q

.Q
~

!
...J
III

0

U

I~

...J
III

~

0

I~

....

'U

U

I~

...J
III

0

I~

I~

...J
III

I~

!

...J
III

..
c
0

Q)

Q)

'U

!

...J
III

II:
0

I~

I

z

..
c

...J
III

0

'3

...J
III

II::
0
0
c(

~

...J
III

..-

~

0

~

C(

co
II::
0

~

co

I~

...J
III

c
~

I.e

,I;

I~

Ii

II::
0

I~

~
...J

III

I~

c(

0

I~
'ii5

5

EX AIM PLE

6
7

00 00

10 10

QO 01

10 00 00 02

01 I I 00 03

00 08

I I 01

00 09

10 10 00 10

I I 01

10 10 00 04

I I 00

I 1 01

00 07

10 01

I II I

10 00 00 13 00 00 00 14 01 I I

00 15

01 10

10 23

I II I

00 05

I II I

00 06

8
9

K>o I

I

10

!
I

II
12

I,

13
14

00 12
1+

10 16

I I 01

10 17

I II I

10 18 00 00

10 19

10 01

10 20 01 10

15
16
17
18
19

20

FIGURE 2. DATA DECK LAYOUT

21

22

23
24

25
26

27
28

29

30

I

10 21

10 10

10 22

01 01

(8204,8205)
2048/4096 BIT READ ONLY MEMORY TRUTH TABLE/ORDERING BLANK

CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:
Note: For 256 x 8 Use This Page Only

Word Os 07 °6 °5 °4 °3 °2 0,

Word °8 °7 °6 °5 °4 °3 °2

a

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Word °8 °7 °6 °5 °4 °3 °2 0,

OUTPUT
Word °8 °7 °6 °5 °4 °3 °2 0,

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152

192
19J
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216

OUTPUT

OUTPUT

OUTPUT

P,

-

U1

o

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191

217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255

I

(8204,8205)
2048/4096 BIT READ ONLY MEMORY TRUTH TABLE/ORDERING BLANK

CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:
Note: For 256 x 8 Use Previous Page Only
OUTPUT

Word

Con

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280

OUTPUT

OUTPUT

OUTPUT

°8 P7 °6 °5 °4 °3 °2 0, Word °8 °7 °6 °5 10 4 °3 °2 0, Word °8 °7 °6 °5 °4 °3 °2 0, Word °8 °7 °6 °5 °4 °3 °2 0,
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344

384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408

448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472

0'1

N

281
282
283
284
285
286
287
288
289
290
291

292
293
294
295
296
297
298
299
300

301
302
303
304

305
306
307
308
309

310
311
312
313
314
315
316
317
318
319

345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383

409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
~38
~39
~40

~41

f442
f443
f444
f445
~46

f447

473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511

(8223,8224) (82823, 82S123) (lU13~)

CB (XXX) 256 BIT READ ONLY MEMORIES TRUTH TABLE/ORDER BLANK
CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

OUTPUTS

INPUTS
WORD
A4

A3

A2

A1

Ao

ENABLE

0

0

0

0

0

0

0

1

0

0

0

0

1

0

2

0

0

0

1

0

0

3

0

0

0

1

1

0

4

0

0

1

0

0

0

5

0

0

1

0

1

0

6

0

0

1

1

0

0

7

0

0

1

1

1

0

8

0

1

0

0

0

0

9

0

1

0

0

1

0

10

0

1

0

1

0

0

11

0

1

0

1

1

0

12

0

1

1

0

0

0

13

0

1

1

0

1

0

14

0

1

1

1

0

0

15

0

1

1

1

1

0

16

1

0

0

0

0

0

17

1

0

0

0

1

0

18

1

0

0

1

0

0

19

1

0

0

1

1

0

20

1

0

1

0

0

0

21

1

0

1

0

1

0

22

1

0

1

1

0

0

23

1

0

1

1

1

0

24

1

1

0

0

0

0

25

1

1

0

0

1

0

26

1

1

0

1

0

0

27 -

1

1

0

1

1

0

28

1

1

1

0

0

0

29

1

1

1

0

1

0

30

1

1

1

1

0

0

31

1

1

1

1

1

0

ALL

X

X

X

X

X

1

B7

B6

85

84

83

82

81

BO

1

1

1

1

1

1

1

1

53

'O"~"OI

'O"~~~J

CB (XXXX) 1024 BIT READ ONLY MEMORY TRUTH TABLE/ORDER BLANK

CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

OUTPUT
Word

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

04

°3

°2

OUTPUT

°1

Word

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

°4

°3

°2

OUTPUT

°1

Word

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153

°4

°3

°2

OUTPUT

°1

Word

192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
2.07
208
209
210
211
212
213
214
215
216
217

°4

°3

°2

0,

c.n
c.n

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
1n7

108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191

218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255

(8228)
4096 BIT READ ONLY MEMORY TRUTH TABLE/ORDER BLANK
m -----------------------------------------------------------------------------------------------------------en
CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

OUTPUT
Word

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

°4

°3

°2

OUTPUT

°1

Word

70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

°4

°3

°2

OUTPUT

°1

Word

140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

°4

°3

°2

OUTPUT

°1

Word

210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238

°4

°3

°2

°1

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139

169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
105
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209

239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279

(8228)
4096 BIT READ ONLY MEMORIES TRUTH TABLE/ORDER BLANK

0'1

co

CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

Word

280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
'301
302
303
304
305
306
307
308

04

OUTPUT
0 3 O2

0,

Word

350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378

04

OUTPUT
0 3 O2

0,

Word

420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448

04

OUTPUT
0 3 O2

OUTPUT

0,

Word

490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518

04

03

°2

0,

309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349

379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419

449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489

519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559

(8228)
4096 BIT READ ONLY MEMORIES TRUTH TABLE/ORDER BLANK
o~-----------------------------------------------------------------------------------------------------------CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

Word

560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588

°4

OUTPUT
0 3 °2

0,

Word

630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658

°4

OUTPUT
°3 O 2

OUTPUT
0,

Word

700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728

°4

°3

°2

0,

Word

770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798

°4

OUTPUT
0 3 O2

0,

589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629

659
660
661
662
663
664
665
666
667
668
669'
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699

729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769

799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839

(8228)
4096 BIT READ ONLY M·EMORIES TRUTH TABLE/ORDER BLANK

~

N

--------------------------------------------------------------------------------------------------------CUSTOMER:

THIS PORTION TO BE COMPLETED BY SIGNETICS

P.O. NO.:

PART NO.:

YOUR PART NO.:

S.D. NO.:

DATE:

DATE RECEIVED:

OUTPUT
Word

840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868

°4

°3

°2

OUTPUT

0,

Word

910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938

°4

°3

°2

OUTPUT

0,

Word

980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008

°4

°3

°2

OUTPUT

0,

Word

°4

°3

°2

°1

869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909

939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
0963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979

1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023

SALES OFFICES
New England Regional Sales Office
Lexington, Massachusetts 02173
Miller Building, Suite 11
594 Ma rrett Road
Phone (617) 861-0840
TWX: (710) 326-6711
Wappingers Falls, New York
Imperial Plaza
Phone: (914) 297-4074
Newmarket, Ont., Canada
303 Towercrest Dr.
Phone: (416) 895-4256

REPRESENTATIVES
ARIZONA
Scottsdale 85254: Adrig Sales, Box 1607
Phone: (602) 947-4336 TWX: (910) 950-1293

CANADA
Toronto 17, Ontario: Corning Glass Works of Canada, Ltd.,
135 Vanderhoff Ave.
Phone: (416) 421-1500 TWX: (610) 491-2155
Montreal 265, Quebec: Corning Glass Works of Canada,
7065 Chester Ave.

Atlantic States Regional Sales Offices
Fort Lee, New Jersey 07024
2460 LeMoine Avenue
Phone (201) 947-9870
TWX: (710) 991-9794
Woodbury, Long Island, New York 11797
20 Crossway Park, Noorth
Phone (516) 364-9100
TWX: (510) 221-2158
Clearwater, Florida 33515
3267 San Mateo Blvd.
Phone (813) 726-3747
Medford, New Jersey 08055
Cedar Brook Building
Taunton Blvd.
Phone (609) 665-5071
TWX: (510) 683-6291
Rockville, Maryland 20852
11400 Rockville Pike, Suite 304
Phone (301) 881-5710
TWX: (710) 828-0532

COLORADO

Central Regional Sales Offices
Rolling Meadows, Illinois 60008
5105 Tollview Drive, Suite #209
Phone (312) 259-8300
TWX: (910) 687-0765
Birmingham, Michigan 48011
725 S. Adams Road
Phone (313) 642-3789
TWX: (810) 232-1673
Dallas, Texas 75230
12830 Hillcrest, Suite 111
Phone (214) 661-1296
TWX: (910) 860-5451
Indianapolis, Indiana 46205
4002 Meadows Drive, Suite J
Phone (317) 545-3232
TWX: (810) 341-3248
Minneapolis, Minnesota 55431
8200 Humboldt Ave., S.
Phone (612) 884-7451
TWX: (910) 576-2845

INDIANA

Northwest Regional Sales Office
Sunnyvale, California 94086
465 Mathilda, Suite 301
Phone (408) 736-7565

NEW MEXICO

Southwest Regional Sales Offices
Irvine, California 92664
2061 Business Center Drive, Suite 214
Phone (714) 833-8980
TWX: (910) 595-1506
Del Mar, California 92014
P. O. Box 788
Phone (714) 453-7570
Phoenix, Arizona 85022
12601 N. Cave Creek Rd., Suite 105
TWX: (910) 950-1299
Phone (602) 971-2517
Encino, California 91316
15910 Ventura Blvd., Suite 813
Phone: (213) 990-2610 TWX: (910) 495-1772

64

Denver 80237: Parker Webster Company, 8213 E. Kenyon Dr.
Phone: (303) 770-1972 TWX: (910) 935-0881

CONNECTICUT
Hamden 06518: Kanan Associates, P. O. Box 5204
Phone: (203) 288-9276 TWX: (710) 465-1540

FLORIDA
Altamonte Springs 32701: WMM Associates, Inc., 505 Tivoli Ct.
Phone: (305) 831-4645
Clearwater 33516: WMM Associates, Inc.,
Hulmac Building, Suite 115,
3118 Gulf to Bay Boulevard
Phone: (813) 726-8871, (813) 726-8872
Pompano Beach 33060: WMM Associates, Inc.,
1628 E. Atlantic Blvd.
Phone: (305) 943-3091

Indianapolis 46250: R. H. Newsom Associates, 6320 Woburn Dr.
Phone: (317) 849·4442

KANSAS
Overland Park 66201: B. C. Electronics, 7520 West 63rd
Phone: (913) 831-2922 TWX: (910) 743-6862

MASSACHUSETTS
Newton Highlands 02161: Kanan ASSOCiates, 88 Needham Street
Phone: (617) 969-7140 TWX: (710) 335-1686

MICHIGAN
Detroit 48224: Rathsburg Associates, 16621 East Warren Avenue
Phone: (313) 882-1717

MISSOURI
St. Louis 63132: B. C. Electronics, 1573 North Warson Road
Phone: (314) 426-3231 TWX: (910) 765-0940

Albuquerque 87110: Staley Company Inc., 2925 Charleston N.E.
Phone: (505) 294-2660

UPSTATE NEW YORK
Dewitt 13214: TriTech Electronics, Inc.,
P. O. Box C Phone: (315) 446-2881

NORTH CAROLINA
Winston-Salem 27101: Murphy-Cota, 1106 Burke Street
Phone: (919) 723-1002 TWX: (510) 931-3101

OHIO
Dayton 45405: Compar Corp., 1112 GreenTree Drive
Phone: (513) 435-1301
Fairview Park 44126: Norm Case Associates, P.O. Box 4791
Phone: (216) 333-4120 TWX: (810) 421-8396

TEXAS

COLORADO

Dallas 75229: McCoy Associates, 4339 Southcrest Road
Phone: (214) 352-9517
Richardson 75080: Semiconductor Sales Associates,
312 North Central Expressway, Suite 213
Phone: (214) 231-6181
Houston 77023: Semiconductor Sales Associates,
975 Corbindale, Suite 109
Phone: (713) 969-7700

Denver 80216: Hamilton/Avnet ElectroniCS; 5921 N. Broadway
Phone: (303) 534-1212 TELEX: 45872
Denver 80222: Cramer Electronics, 5465 E. Evans Place at Hudson
Phone: (303) 758-2100

WASHINGTON
Bellevue 98009: Western Technical Sales, P. O. Box 902
Phone: (206) 454-3906 (503) 224-5107 TWX: (910) 443-2309

CONNECTICUT
Hamden 06514: Arrow Electronics,
295 Treadwell Street
Phone: (203) 248-3801
Georgetown 06829: Hamilton/Avnet Electronics,
643 Danbury Road
Phone: (203) 762-0361
North Haven 06473: Cramer Electronics, 35 Dodge Avenue
Phone (203) 239-5641

FLORIDA

DISTRIBUTORS
ARIZONA
Phoenix 85034: Hamilton/Avnet Electronics, 2615 S_ 21st St.
Phone: (602) 275-7851 TELEX: 667-450
Phoenix 85034: Kierulff Electronics, 2633 East Buckeye Road
Phone: (602) 273-7331 TWX: (910) 951-1550

CALIFORNIA
Culver City 90230: Hamilton Electro Sales,
10912 W. Washington
Phone: (213) 870-7171
TELEX: 677-100, 674-381, 674-354
EI Monte 91731: G. S. Marshall, 9674 Telstar Avenue
Phone: (213) 686-1500 TWX: (910) 587-1565

Hollywood 33021: Hamilton/Avnet Electronics, 4020 No. 29th Ave.
Phone: (305) 925-5401 TELEX: 51-4328
Hollywood 33020: Schweber Electronics, 2830 North 28th Terrace
Phone: (305) 927-0511
Orlando 32805: Hammond Electronics, 911 West Central Blvd.
Phone: (305) 241-6601 TWX: (810) 850-4121

GEORGIA
Atlanta 30340: Schweber Electronics,
4126 Pleasantdale Road, Suite 14
Phone: (404) 449-9170
Norcross 30071: Hamilton/Avnet Electronics
6700 Interstate 85 Access Road, Suite 2B
Phone: (404) 448-0800 TELEX: 542-127

ILLINOIS
Elk Grove 60007: Schweber Electronics, 1380 Jarvis Avenue
Phone: (312) 593-2740
Elmhurst 60126: Semiconductor SpeCialists, Inc.,
195 Spangler Avenue, Elmhurst Industrial Park
Phone: (312) 279-1000 TWX: 254-0169
Schiller Park 60176: Hamilton/Avnet Electronics,
3901 No. 25th Avenue
Phone: (312) 678-6310 TELEX: 728-330

Los Angeles 90022: KT/Wesco Electronics, 5650 Jillson Street
Phone: (213) 685-95'25 TWX: (910) 580-1980
Mountain View 94041: Hamilton/Avnet Electronics,
340 East Middlefield Road
Phone: (415) 961-7000 TELEX: 348-201
Palo Alto 94303: Wesco Electronics, 3973 East Bayshore Road
Phone: (415) 968-3475 TWX: (910) 379-6488
San Diego 92123: Hamilton/Avnet Electronics,
8917 Complex Dr.
Phone: (714) 279-2421
San Diego 92123: Kierulff Electronics,
8797 Balboa Avenue
Phone: (714) 278-2112 TWX: (910) 335-1182
Sunnyvale 94063: Cramer Electronics,
720 Palomar
Phone: (408) 739-3011

Lenexa 66215: Hamilton/Avnet ElectroniCS,
37 Lenexa Industrial Center
Phone: (913) 888-8900

CANADA

MARYLAND

Downsview 463, Ontario: Cesco Electronics, Ltd.,
24 Martin Ross Avenlle
Phone: (416) 661-0220 TELEX: 02-29697
Downsview, Ontario: Cramer Electronics, 920 Alness Ave.,
Unit 9
Phone: (416) 661-9222
Montreal, Quebec: Cesco Electronics, Ltd., 4050 Jean Talon West
Phone: (514) 735-5511 TWX: (610) 421-3445
Montreal, Quebec: Hamilton/Avnet, 935 Montee De Liesse
Phone: (514) 735-6393
TWX: (610) 421-3731
Ottawa, Ontario: Hamilton/Avnet Electronics, 880 Lady Ellen Place
Phone: (613) 725-3071
Ottawa, Ontario: Cesco Electronics, Ltd., 1300 Carling Avenue
Phone: (613) 729-5118
Quebec: Cesco Electronics, Ltd., 128 St_ Vallier Street
Phone: (418) 524-3518

Hanover 21076: Hamilton/Avnet ElectroniCS, 7255 Standard DrIve,
Phone: (301) 796-5000 TELEX: 879-68
Rockville 20850: Pioneer Washington Electronics, Inc.,
1037 Taft Street Phone: (301) 424-3300
Rockville 20852: Schweber Electronics, 5640 Fisher Lane
Phone: (301) 881-2970

INDIANA
Indianapolis 46241: Semiconductor Specialists,
P.O. Box 41630, Weir Cook Airport
Phone: (317) 243-8271
TWX: (810) 341-3126

KANSAS

MASSACHUSETTS
Burlington 01803: Hamilton/Avnet Electronics
185 Cambridge Street
Phone: (617) 273-2120 TELEX: 9496·61
Needham Heights 02194: Kierulff/Schley, 14 Charles Street
Phone: (617) 449-3600 TWX: (710) 326-1179
Newton 02150: Cramer Electronics, 85 Wells Avenue
Phone: (617) 969-7700
Waltham 02154: Schweber Electronics, 213 Third Ave.,
Phone: (617) 890-8484

65

MICHIGAN

Cleveland 44122: Arrow Electronics, 23945 Mercantile Rd.
Phone: (216) 464-2000

Livonia 48150: Hamilton/Avnet Electronics,
12870 Farmington Road
Phone: (313) 522-4700
Detroit 48240: Semiconductor Specialists, Inc.,
25127 W. Six Mile Road
Phone: (313) 255-0300 1WX: (910) 254-0169

Cleveland 44105: Pioneer Standard Electronics,
4800 East 131st Street
Phone: (216) 587-3600 TWX: (810) 421-8238
Kettering 45429: Arrow Electronics, 3100 Plainfield Road
Phone: (513) 253-9176 1WX: (810) 459·1611

MINNESOTA

TEXAS

Minneapolis 55423: Semiconductor Specialists, Inc.,
8030 Cedar Avenue South
Phone: (612) 854-8844
Edina 55435: Hamilton/Avnet Electronics,
7683 Washington Ave., S.
Phone: (612) 941-3801

MISSOURI
Hazelwood 63042: Hamiiton/Avnet Electronics,392 Brookes Lane
Phone: (314) 731-1144 TELEX: 442348

NEW YORK
Buffalo 14202: Summit Distributors, Inc., 916 Main Street
Phone: (716) 884-3450 1WX: (710) 522-1692
Farmingdale, L. I., 11735: Arrow Electronics,
900 Broad Hollow Rd.
Phone: (516) 694-6800
TWX: (510) 224-2694
Rochester 14620: Schweber Electronics, 999 Buffalo Road
Phone: (716) 328-4180
Syracuse 13211: Hamilton/Avnet Electronics, 6500 Joy Road
Phone: (315) 437-2642
Westbury 11590: Schweber Electronics, Jericho Turnpike
Phone: (516) 334-7474 TWX: (510) 222-3660

Dallas 75240: Hamilton/Avnet ElectroniCS, 4445 Sigma Road
Phone: (214) 661-8661 TELEX: 732359
Dallas 75220: Cramer Electronics, 2970 Blystone Ave.
Phone: (214) 350-1355
Houston 77036: Component Specialties, 7315 Ashcroft, Suite 113
Phone: (713) 771-7237
Houston 77019: Hamilton/Avnet Electronics,
1216 West Clay Street
Phone: (713) 526·4661 TELEX: 762589

UTAH
Salt Lake City 84115: Alta Electronics, 2280 S. Main St.,
Phone: (801) 486-7227 TELEX: (910) 925·5282
Salt Lake City 84119: Hamilton/Avnet Electronics
647 West Billinis Road
Phone: (801) 262-8451

WASHINGTON
Bellevue 98005: Hamilton/Avnet Electronics,
13407 Northrup Way
Phone: (206) 746-8750 TELEX: 32249

Westbury 11590: Hamilton/ Avnet Electronics,
70 State Street
Phone: (516) 333-5800
TWX: (510) 227-6073

NEW MEXICO
Albuquerque 87108: Cramer Electronics, 137 Vermont, N.E.
Phone: (505) 265-5767

NORTH CAROLINA
Greensboro 27406: Hammond Electronics,
2923 Pacific Avenue
Phone: (919) '275-6391

NORTHERN NEW JERSEY
Cedar Grove 07009: Hamilton/Avnet Electronics,
218 Little Falls Road
Phone: (201) '239-0800 TELoEX: 138313
Saddlebrook 07662: Arrow Electronics, 285 Midland Avenue
Phone: (201) 797-5800
Moorestown 08057: Arrow/Angus Electronics,
Pleasant Valley Road
Phone: (609) 235-1900
TWX: (710) 897-0829

INTERNATIONAL SALES
EUROPEAN HEADQUARTERS
Signetics International Corp., Yeoman House, 63 Croydon Road,
Penge, London, S.E. 20, England
Phone: (01) 659-2111 TELEX: 946619

FRANCE
Signetics S.A.R.L., 34 Rue de Silly, F92100 Boulogne
Phone: 604-23-07 TELEX: 26801

WEST GERMANY
Signetics GmbH, Dantestr. 29, D 8 MOnchen 19
Phone: (0811) 151029/151020
Signetics GmbH, Ernsthaldenstrasse 17,
D 7 Stuttgart 80, West Germany
Phone: (0711) 73-50-61 TELEX: 7255798
Signetics GmbH, Eulenkrugstr. 81E, D 2 Hamburg 67
Phone: (0411) 60-35-242 TELEX: 2174490

SOUTHERN NEW JERSEY AND PENNSYLVANIA
Mt. Laurel. N. J. 08057: Hamilton/Avnet Electronics,
113 Gaither Dr., East Gate Industrial Park
Phone: (609) 234-2133 TELEX: 834737
Cherry Hill, N. J. 08034: Milgray-Delaware Valley,
1165 Marlkress Road
Phone: N.J. (609) 424-1300 Phila. (215) 228-2000
TWX: (710) 896-0405
Somerset, N.J. 08873: Schweber Electronics,
43 Belmont Drive
Phone: (201) 469-6008

OHIO
Beechwood 44122: Schweber Electronics,
23880 Commerce Park Road
Phone: (216) 464-2970

66

STOCKING DISTRIBUTORS
AUSTRALIA
Pye Industries, Ltd., Tecnico Electronics Division,
Premier St., Marrickville, Sydney, N.S.W. 2204
Phone: 55-0411 TELEX: AA-21490
Pye Industries, Ltd., Tecnico Electronics Division,
2 High St., Northcote, Melbourne, Vic. 3070
Phone: 489-93'22 TELEX AA-31240

BELGIUM
Klaasing Benelux S.A., Avenue de L'Universite 93, 1050 Bruxelles
Phone: (02) 49-85-32 TELEX: 25003

WEST GERMANY
EBV Elektronik GmbH. Augustenstrasse 79, D 8 Munchen 2
Phone: (0811) 52-43-40/48 TELEX: 524535
EBV Elektronik GmbH. Myliusstrasse 54 D 6 Frankfurt/Main 1
Phone: (0611) 72-04-16/18 TELEX: 413590
EBV Elektronik GmbH. Scheurenstrasse 1, D 4 Duesseldorf
Phone: (0211) 8-48-46/47 TELEX: 8587267
Mirotronic, 2 Hamburg 54, Ahornllee 5
Phone: (0411) 560-40-54
TELEX: 02 15427
EBV Elektronik GmbH, Abraham-Wolf Strasse 48,
D 7 Stuttgart-Sonnenberg
Phone: (0711) 765072/3
TELEX: 07255811
"Mutron" Muller & Co. KG, Postfach 164, Bornstrasse 22,
D 28 Bremen 1
Phone: (0421) 31-04-85 TELEX: 245-325
Omni-Ray GmbH, 67 Ludwigshafen, Moltkestrasse,
8 Postfach 211023
Phone: (0621) 51-30-55/56 TELEX: 0464557
Oistron GmbH, D 1 Berlin 31, Wilhelmsaue 39-41
Phone: (0311) 82-13-064
TELEX: 18-27-58

A. B. Kuno Kallman, Sibyllegarten 28, 11443, Stockholm, Sweden
Phone:08/671711-671595 TELEX: 17165

DENMARK
E. Friis-Mikkelsen A/S, Krogshojvej 51, DK-2880 Bagsvaerd
Phone: (01) 986333 TELEX: 2350

THE NETHERLANDS
Mulder-Hardenberg, Westerhoutpark I-A, P. O. Box 3059, Haarlem
Phone: (023) 3191 84 TELEX: 41431

JAPAN
Asahi Glass Co., Ltd., 1-2 Marunouchi, 2 Chome Chiyoda-ku, Tokyo
Phone: 211-0411
TELEX: 24616

AFRICA
Allied Electronic (PTY) Ltd., P. o. Box 6090,
Dunswart, Transvaal, South Africa
Phone: 52431
TELEX: 43-7823

REPRESENTATIVES
SWEDEN, NORWAY, FINLAND

AUSTRIA

A. B. Kuno Kallman, Jarnorget 7, S-41304 Gothenburg, Sweden
Phone: 17-01-20 TELEX: 21072

Ing. Ernst Steiner, Beckgasse 30, A-1130 Wien
Phone: (222) 82-10-605

A. B. Kuno Kallman, Sibyllegarten 28, 11443, Stockholm, Sweden
Phone: 08/671711-671595
TELEX: 17165

SWITZERLAND

AUSTRALIA

Omni Ray AG, Dufourstrasse 56,8008 Zurich
Phone: 01/478200 TELEX: 53239

FRANCE
S. A. Gallec Electronique, 22 Rue Raymond Losserand,
75-Paris 14e
Phone: 734-25-65/273-18-51
R.T.F., 73 Avenue Charles de Gaulle, 92-Neuilly
Phone: 722-70-40
TELEX: 65933
Elic 38, Ie Bureau Barisien S_A.R.L,
8-10 Avenue du Grand Sablon, 38 La Tronche
Phone: (76) 87-67-71 TELEX: 32-739

ITALY
Metroelettronica S.A.S., Via Ie Cirene 18, 1-20135 Milano
Phone: 546-26-41 TELEX: 33-168 Metronic

ISRAEL
Rapac Electronics Ltd., 15 Karl Herbst St.,
Tel-Baruch, Tel-Aviv Phone: 77 71 15,6,7

Pye Industries, Ltd., Tecnico Electronics Division,
Premier St., Marrickville, Sydney, N.S.W. 2204
Phone: 55-0411 TELEX: AA-21490
Pye Industries, Ltd., Tecnico Electronics Division,
2 High St., Northcote, Melbourne, Vic. 3070
Phone: 489-9322 TELEX AA-31240

ISRAEL
RAPAC Electronics ltd., 15 Carl Herbst Street, Tel Baruch, Tel Aviv
Phone: 777115.6.7
TELEX: TV 528

JAPAN
Asahi Glass·Co. ltd., 1-2, Marunouchi, 2 Chome, Chiyoda-ku, Tokyo
Phone: 211-0411
TELEX: 24616

SWITZERLAND
Omni Ray AG, Dufourstrasse 56, 8008 Zurich
Phone: 01/478200
TELEX: 53239

INDIA
TELEX: TV 528

ITALY
Metroelettronica S.A.S., Viale Cirene 18, 1-20135 Milano
Phone: 546-26-41
TELEX: 33-168 Metronic

Semiconductors Limited, Nagar Rd., Mile 4/5, Ramawadi,
Poona 14, Maharashtra
Phone: 25186
CABLE: Transducer

UNITED KINGDOM
Quarndon Electronics Ltd., Slack Lane, Derby, Derbyshire
Phone: Derby 32651
TELEX: 37163
S.O.S. (Components) Ltd., Hilsea Industrial Estate
Portsmouth, Hampshire
Phone: 6 53 11 TELEX: 86114
Semicomps Ltd., 5 Northfield Industrial Estate,
Beresford Ave., Wembley, Middlesex
Phone: (01) 903-3161 TELEX: 935243
A. M. Lock & Co. Ltd., Neville Street, Middleton Road,
Oldham, Lancashire
Phone: (061) 624-6832 TELEX: 669971

SCOTLAND
Semicomps Northern Ltd., 42 The Square, Kelso, Roxburghshire
Phone: Kelso 2366 TELEX: 72692

SWEDEN, NORWAY, FINLAND
A. B. Kuno Kallman, Jarnorget 7, S-413 04 Gothenburg, Sweden
Phone: 17-01-20 TELEX: 21072

67

Please add the name below to the next product information mailing on:

D

D
D

D

DIGITAL
LINEAR
MOS

D

D

D
D

What is the end product of your plant?

Which title most closeley represents your
professional position? (check only one)

D

A.
B.
C.
D.
E.

D
D
D
D
D F.

SIGNETICS INTEGRATED
CIRCUIT HANDBOOK
SIGNETICS INTEGRATED
CIRCUITS APPLICATIONS NOTES
SIGNETICS SCHOTTKY SYSTEMS DESIGN

General or Corporate Management
Engineering Management
Design Engineer
Research and Development Engineer
Purchasing
Other (please specify)

0
D

D
D
D

A.
B.
C.
D.
E.
G.

0

H.

D

Z.

D

Computer (main frame + mini)
Terminals
Peripherals
Test and Measurement Instruments
Communications Equipment
I ndustrial Control Systems and
Equipment
Aircraft, Missile, Space or
Undersea Equipment
Other (please specify)

Please Print

Name (first initial only)

Title (abbreviate)

Company

Division

Street

Mail Stop

City

State

Zip

III

r·-

=
....-r:In

FIRST CLASS
Permit No" 166
PAID
Sunnyvale
California

III

~m
m~

!.~

... m
8l>
men
~.,
Wl>

tp:n
~~

~c
Om
en

BUSINESS REPLY MAIL

No postage stamp necessary if mailed in the United States

-l>

<

~m

~z

~c

film

g.
wen
wc

tpz
rnz
~-<
w<

_rl>
fTl

l>O

(')~l>

Postage will be paid by

SIGNETICS CORPORATION
811 East Arques Avenue
Sunnyvale, Ca.

og-r

~§;=n

~"~ 0
::r

0

:n

:~z
¢
o_
;j~l>
.- 2
~ CO) •
:;" CO)

;S;(()
Co

~ ~

!=:eD
CJ)om

~~m

Attention: Marketing Communications Dept.
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer                        : Adobe Acrobat 9.31 Paper Capture Plug-in
Modify Date                     : 2010:03:26 12:40:20-08:00
Create Date                     : 2010:03:26 12:40:20-08:00
Metadata Date                   : 2010:03:26 12:40:20-08:00
Format                          : application/pdf
Document ID                     : uuid:f0ea314d-f455-4550-94b4-41d06767ab78
Instance ID                     : uuid:e6c4bb68-e2b1-4014-bb56-c3267dffbc14
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 73
EXIF Metadata provided by EXIF.tools

Navigation menu