1973_National_Digital_Integrated_Circuits 1973 National Digital Integrated Circuits
User Manual: 1973_National_Digital_Integrated_Circuits
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Introduction
Here IS the new Digital Data Handbook from National It gives complete specifications for devices useful
In building nearly all types of electronic systems, from small Instruments to computer designs
For Information regarding newer devices Introduced since the printing of this handbook, or for further
information on listed parts, please contact our local representative, distributor, or regional office
DIGITAL
I
I
I
LogiC
Shift
Registers
Hybnd
Clock
Dnvers
LogiC
Elements
HYBRIOS
OTl
TRI·STATE®
RAMs
I
I
TTl
MOS
Senes
-Hybrid
54L174L
Dnvers
I
Serres
930
Analog
Operational
SwItches
Ampllfters
LINEAR
I
I
Operational
I
Interface
I
Voltage
Consumer
Comparatorsl
Amphflen
CirCUits
Regulators
Circuits
Buffers
I
I
I
Hybrods
I
Sense
Amplifiers
Penpheral
Dnvers
Lme Drivers!
Receivers
T.V
Commu mcatlOn
Circuits
AudiO
Analog
SWitches
DnYers
Operational
Amplifiers
TRANSISTORS
I
LEO's
Transducers
~
Lamps
Displays
I
Power
TranSistors
NPN & PNP Small Signal
SIlicon TranSistors
I
Field Effect TranSistors
~
Amplifiers &
SWItches
Monolithic
Duals
Ordering Information
For available packages, consult the tables which precede each section. Then refer to the package drawings
(pages I through VI) In the back of the catalog.
The ordering information for National devices covered
E~ ~L~
In
thiS catalog IS as follows:
t
~PACKAGE
......- - - - - - - - DEVICE NUMBER
L...-_ _ _ _ _ _ _ _ _ _ _
DEVICE FAMILY
DEVICE FAMILY
PACKAGE
AH - Analog Hybrid
0- Glass/Metal Dual·ln·Llne Package
AM - Analog Monolithic
F - Flat Package (025" wide)
OM - Digital Monolithic
G - TO·8 (12 lead) Metal Can
LH - Linear Hybrid
H - TO·5 (multl·lead) Metal Can
LM - Linear Monolithic
J - Glass/Glass Dual·ln·Llne Package
MM - MaS MonolithiC
N - Molded Dual·ln·Llne Package
W - Flat Package (0.275" wide)
DEVICE NUMBER
4, 5, or 6 digit number.
Suffix Indicators:
A - Improved Electrical SpeCification
C - Reduced Temperature Range
For most of the products listed In thiS catalog the temperature range can be obtained from the first one or
two numbers following the family designation. For example:
DM54XX
All numbers beginning with 5 denote -55°C to +125°C temperature operation.
DM74XX
If the "74" IS indicated, the operating temperature IS O°C to +70°C.
DM7XXX
All other numbers beginning with 7 (beSides the "74" shown above) are NSC
propnetary products and a 7 here Indicates -55°C to +125°C.
DM8XXX
All numbers beginning with 8 denote O°C to +70°C temperature operation.
iii
Table of Contents
Introduction . . . . . . . . . . . . . . . . . .
Ordering Information ......... .
Edge I ndex by Product Family
Product Function GUide ...
iii
xiIi
xv
SERIES 54/74 - SECTION 1
Reference to Package Dimensions, Waveforms, Test Circuits, and Ordering Information . . ...... .
DM5400/DM7400 (SN5400/SN7400) Quad 2-lnput NAND Gate ............ . .
. . . . .. .
DM5401/DM7401 (SN5401/SN7401) Quad 2-lnput Gate (Open Collector)
.. ........ . .... .
DM5402/DM7402 (SN5402/SN7402) Quad 2-lnput NOR Gate.
. . .. .. .... . ....... .
DM5403/DM7403 (SN5403/SN7403) Quad 2-1 nput Gate (Open Collector)
...... ..
DM5404/DM7404 (SN5404/SN7404) Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . ..... . ... .
DM5405/DM7405 (SN5405/SN7405) Hex Inverter (Open Collector)
. . .... .
DM5406IDM7406 (SN5406/SN7406) Hex Inverter Buffer/Dnver . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5407/DM7407 (SN5407/SN7407) Hex BufferlDnver . . . . . . . . . . . . . . . . . ... .. ... .
DM5408/DM7408 (SN5408/SN7408) Quad 2-lnput AND Gate
. . . . . . .. .
DM5409/DM7409 (SN5409/SN7409) Quad 2-lnput AND Gate (Open Collector) .. ...... . ... .
DM5410/DM7410 (SN5410/SN7410) Triple 3-lnput NAND Gate . . . . . . . . . . . . . . . .
DM5411/DM7411~(SN5411/SN7411) 3-lnput Positive AND Gate....
. ........ .
DM5413/DM7413 (SN5413/SN7413) Dual Schmltt-Tngger ...... .... . . ... .. .
DM5416/DM7416 (SN5416/SN7416) Hex Inverter BufferlDnver . . . . . . . . . . . . . . . . . . . . . . . . .
DM5417/DM7417 (SN5417/SN7417) Hex Buffer/Dr.lver .. . . . . . . . . . . . . . . . . ...... . ..
DM5420/DM7420 (SN5420/SN7420) Dual 4-lnput NAND Gate. . . . . . . .
. ....... .
DM5426/DM7426 (SN5426/SN7426) Quad 2-lnput TTL-MOS Interface Gate ........ . ..... .
DM5430/DM7430 (SN5430/SN7430) 8-lnput Gate.
. . . . . .. . . . . .
. . . . . .. .
.. . ...... .
DM5432/DM7432 (SN5432/SN7432) Quad 2-lnput OR Gate. . . . . .
DM5437/DM7437 (SN5437/SN7437) Quad 2-lnput NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . .
....... .
DM5438/DM7438 (SN5438/SN7438) Quad 2-lnput NAND Buffer (Open Collector)
DM5440/DM7440 (SN5440/SN7440) Dual 4-lnput Buffer. .... ..... ......
. ........ .
DM5441A/DM7441A (SN5441A/SN7441 A) BCD to Decimal Decoder/Nlxle™ Dnver. . .. ..
DM5442/DM7442 (SN5442/SN7442) BCD to Decimal Decoder .. . ... .. . .... ... . ...
DM5445/DM7445 (SN5445/SN7445) BCD to Decimal Decoder/Dnver . . . . . . . . . . . . . . . . .
DM5450/DM7450 (SN5450/SN7450) Expandable Dual 2-Wlde 2-lnput AND-OR-INVERT Gate.. ..
DM5451/DM7451 (SN5451/SN7451) Dual 2-Wlde 2-lnput AND-OR-INVERT Gate .. . ... . .. .
DM5453/DM7453 (SN5453/SN7453) Expandable 4-Wlde 2-lnput AND-OR-INVERT Gate.. . .... .
DM5454/DM7454 (SN5454/SN7454) 4-Wlde 2-lnput AND-OR-INVERT Gate .....
. ........ .
DM5460/DM7460 (SN5460/SN7460) Dual 4-lnput Expander. . .. ... .
.. ..... .
DM5470/DM7470 (SN5470/SN7470) Edge-Tnggered JK Flip Flop. . . . .. .......... .. . ..
DM5472/DM7472 (SN5472/SN7472) JK Master/Slave Flip Flop
. .. ... .. ...
. ..... .
DM5473/DM7473 (SN5473/SN7473) Dual JK Master/Slave Flip Flop. . . . . . . . . . . . .. . ..... .
DM5474/DM7474 (SN5474/SN7474) Dual D Flip Flop ...... . .. .
.....
. ... . ....... .
DM5475/DM7475 (SN5475/SN7475) Quad Latch
Dll!i5476IDM7476 (SN5476/SN7476) Dual JK Master/Slave Flip Flop. . .. ..... ... ... . ..
DM5483/DM7483 (SN5483/SN7483) 4-Blt Binary Full Adder and Dual Single-Bit Binary Full Adder .
DM5485IDM7485 (SN5485/SN7485) 4-Blt Magnitude Comparator .......
..... . .. . . ..
DM541\6/DM7486 (SN5486/SN7486) Quad EXCLUSIVE-OR Gate.
.. .. . ... . ......... .
DM5488/DM7488 (SN5488/SN7488) 256-Blt Read Only Memory . . . . . . . . . . . . . . . . . . . . .. ..
DM5489/DM7489 (SN5489/SN7489) 64-Blt Random Access Read/Wnte Memory.. . .......... .
DM5490/DM7490 (SN5490/SN7490) Decade Counter
. . . . . . . . .. . ..
DM5491 A/DM7491 A (SN5491 A/SN7491 A) 8-Bit Shift Register. . . . . . . . . .. . .....
DM5492/DM7492 (SN5492/SN7492) D,v,de by 12 Counter . ...... . .
DM5493/DM7493 (SN5493/SN7493) 4-Blt Binary Counter .. .... .
DM5495/DM7495 (SN5495/SN7495) 4-Blt Rlght-Shlft/Left-Shlft Register ..
DM5496/DM7496 (SN5496/SN7496) 5-Blt Parallel-In/Parallel-Out Shift Regl~ter
DM54107/DM74107 (SN54107/SN74107) Dual JK Master/Slave Flip Flop . . . . . . .
l-i
1-1
1-3
1-5
1-3
1-7
1-3
1-9
1-11
1-13
1-13
1-1
1-15
1-17
1-9
1-11
1-1
1-19
1-21
1-23
1-25
1-25
1-27
1-29
1-31
1-33
1-35
1-35
1-35
1-35
1-35
1-38
1-40
1-42
1-44
1-46
1-42
1-48
10-1
1-51
1-53
1-57
1-59
10-2
1-59
1-59
1-63
1-66
1-42
v
SERIES 54/74 - SECTION 1 (CONTINUED)
DM54121/DM74121 (SN54121/SN74121) Monostable Multlvlbrator
DM54123/DM74123 (SN54123/SN741231 TTL!Monostable Multlvlbrator..... .
DM54125/DM74125 (SN54125/SN741251 (See DM7093/DM80931 .
DM54126/DM74126 (SN54126!SN741261 (See DM7094/DM80941 .
DM54141/DM74141 (SN54141/SN74141I BCD to DeCimal Decoder/Driver
DM54145/DM74145 (SN54145/SN741451 BCD to DeCimal Decoder/Driver.
DM54150/DM74150 (SN54150/SN741501 16-Llne to l-Llne Multiplexer.
DM54151 !DM74151 (SN54151 /SN74151I 8-Channel Digital Multiplexer. ..
DM54153/DM74153 (SN54153/SN741531 Dual 4:1 Multiplexer . . . . .
DM54154/DM74154 (SN54154/SN741541 4-Llne to 16-Llne Decoder/Demultiplexer
DM54155/DM74155 (SN54155/SN741551 Dual 2.4 Demultiplexer ..
DM54156/DM74156 (SN54156/SN741561 Dual 2 4 Demultiplexer . . . .
DM54157/DM74157 (SN54157/SN741571 (See DM9322/DM83221 . . . . .
DM54160/DM74160 (SN54160/SN741601 Synchronous 4-Blt Counter ...... .
DM54161/DM74161 (SN54161/SN74161I Synchronous 4·Blt Counter
DM54162/DM74162 (SN54162/SN741621 Synchronous 4-Blt Counter ... .. .
DM54163/DM74163 (SN54163/SN741631 Synchronous 4-Blt Counter
DM54164/DM74164 (SN54164/SN741641 (See DM7570/DM85701
DM54165/DM74165 (SN54165!SN741651 (See DM7590!DM85901.
DM54166/DM74166 (SN54166/SN741661 8-Blt Shift Register
DM54173/DM74173 (SN54173/SN741731 (See DM7551/DM8551I
DM54174/DM74174 (SN54174/SN741741 Hex D Flip Flop ....
DM54175/DM74175 (SN54175/SN741751 Quad D Flip Flop .. . ..
DM54176/DM74176 (SN54176/SN741761 (See DM7280/DM82801
....... .
........ .
DM54177/DM74177 (SN54177/SN741771 (See DM7281/DM8281)
DM54180/DM74180 (SN54180/SN741801 8-Blt Odd/Even Parity Generator/Checker. .
DM54181/DM74181 (SN54181/SN74181I ArithmetiC LogiC Unit . . . . . . . . : .
DM54182/DM74182 (SN54182/SN741821 Look-Ahead Carry Generator
DM54184/DM74184 (SN54184/SN741841 BCD-to-Blnary Converter ....... .
DM54185A/DM74185A (SN54185A/SN74185AI Blnary-to-BCD Converter
DM54187/DM74187 (SN54187/SN741871 1024-Blt Read Only Memory
DM54190/DM74190 (SN54190/SN741901 Up-Down Decade Counter .
DM54191/DM74191 (SN54191/SN74191) Up-Down Binary Counter
DM54192/DM74192 (SN54192/SN741921 (See DM7560/DM85601 . . . . . . . . . . . . . .
DM54193/DM74193 (SN54193/SN741931 (See DM7563/DM85631 ..
DM54195/DM74195 (SN54195/SN741951 (See DM9300/DM83001
DM54196/DM74196 (SN54196/SN741961 Presettable Decade Counter. ..
DM54197/DM74197 (SN54197/SN741971 Presettable Binary Counter
DM54198/DM74198 (SN54198/SN741981 8-Blt Shift Register . . .
DM54199/DM74199 (SN54199/SN741991 8-Blt Shift Register. . ..
DM74200 (SN742001 TRI-STATE® 256-Blt Random Access Memory
DM7090/DM8090 Quad Inverter/Dual 2-lnput NAND Buffer ...... .
DM7091/DM8091 Quad 2-lnput NAND Buffer. . .. .
DM7092/DM8092 Dual 5-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . .
DM7093/DM8093 TRI-STATE® Quad Buffer. . . . . .. . . . . . . . . . . . . .
DM7094/DM8094 TRI-STATE® Quad Buffer ....
DM7095/DM8095 TRI-STATE® Hex Buffer.
DM7096/DM8096 TRI-STATE® Hex Inverter
DM7097/DM8097 TRI-STATE® Hex Buffer...... .
DM7098/DM8098 TRI-STATE® Hex Inverter .. .
DM7121/DM8121 TRI·STATE® 8-Channel Digital Multiplexer
DM7123/DM8123 TRI-STATE® Quad 2-lnput Multiplexer
DM7130/DM8130 10-Blt Comparator ....
DM7131/DM8131 6-Blt Unified Bus Comparator . . . .
DM7136/DM8136 6-Blt Unified Bus Comparator . . .
DM7160/DM8160 6-Blt Comparator
DM7200/DM8200 4-Blt Comparator ..
DM7210/DM8210 8-Channel Digital SWitch.
DM7211/DM8211 8-Channel Digital SWitch . . . . . . . . . . . . . . . .
vi
1-68
10-2
1-113
1-113
10-3
1-33
1-70
1-73
1-75
1-77
1·80
1-80
6-12
10-3
10-3
10-3
10·3
1-167
1-180
1-82
1-152
10-4
10-4
1-143
1-143
1-84
1-86
1-92
1-94
1-94
1-96
1-99
1-101
1-161
1-164
6-4
10·4
10-4
1-103
1-105
1-146
1·107
1-109
1-111
1-113
1-113
1-116
1-116
1-116
1-116
1-118
1-120
1-122
1-124
1-124
1-122
1-126
1-128
1-128
SERIES 54/74 -
SECTION 1 (CONTINUED)
DM7214/DM8214 TRI-STATE® Dual 4:1 Multiplexer.
DM7219/DM8219 TRI-STATE® 16-Llne to l-Llne Multiplexer
DM7220/DM8220 Parity Generator/Checker .
DM7223/DM8223 l-Llne to 8-Llne Demultiplexer..
DM7230/DM8230 TRI-STATE® Demultiplexer ...... .
DM7280/DM8280 (S8280/N8280) Presettable Decade Counter .. .
DM7281/DM8281 (S8281/N8281) Presettable Binary Counter .. .
DM7288/DM8288 (S8288/N8288) Presettable D,v,de by 12 Counter
DM7512/DM8512 Dual Gated Master/Slave JK/D Flip Flop
DM7520/DM8520 Modulo-N Divider ...
DM7551/DM8551 TRI-STATE® Quad D Flip Flop
DM7552/DM8552 TRI-STATE® Decade Counter/Latch ..
DM7553/DM8553 TRI-STATE® 8-Blt Latch
............. .
DM7554/DM8554 TRI-STATE® Binary Counter/Latch .. .
DM7555/DM8555 TRI-STATE® Programmable Decade Counter ..
DM7556/DM8556 TRI-STATE® Programmable Binary Counter.
DM7560/DM8560 (SN54192/SN74192) Up/Down Decade Counter.
DM7563/DM8563 (SN54193/SN74193) Up/Down Binary Counter ..
DM7570/DM8570 (SN54164/SN74164) 8-Blt Serial-In Parallel-Out Shift Register
DM7573/DM8573 1024-Blt Field-Programmable Read Only Memory .. . . .
DM7574/DM8574 TRI-STATE® 1024-Blt Field-Programmable Read Only Memory
DM7575/DM857S Programmable Logic Array (PLA)
DM7576/DM8576 Programmable Logic Array (PLA)
DM8582 256-Blt Random Access Memory (Open Collector)
DM7590/DM8590 (SN54165/SN74165) 8-Blt Parallel-I n Serial-Out Shift Register.
DM7595/DM8595 4096-Blt Bipolar Read Only Memory
DM7596/DM8596 TRI-STATE® 4096-Blt Bipolar Read Only Memory.
DM7597/DM8597 TRI-STATE® 1024-Blt Read Only Memory ..... .
DM7598/DM8598 TRI-STATE® 256-Blt Read Only Memory .. .
DM7599/DM8599 TRI-STATE® 64-Blt Random Access Read/Write Memory.
DM7613/DM8613 Quad Gated D Flip Flop ...
DM7695/DM8695 4096-Blt Bipolar Read Only Memory . .
. . . .... .
DM7696/DM8696 TRI-STATE® 4096-Blt Bipolar Read Only Memory .... .
DM7800/DM8800 Dual Voltage Translator . .. .. . .. ..
DM7806/DM8806 High Speed MOS to TTL Level Converter
DM7810/DM8810 Quad 2-lnput TTL-MOS Interface Gate. ...
. ....... .
DM781 ,/DM8811 Quad 2-lnput TTL-MOS Interface Gate.. ..... .... . .
DM7812/DM8812 TTL-MOS Hex Inverter
....... .
DM7819/DM8819 Quad 2-lnput TTL-MOS AND Gate. . . .. ... .. ..... . ..
DM7820/DM8820 Dual Line Receiver ........ _ . .. . ...... .
DM7820A/DM8820A Dual Line Receiver . . . . . . . . . . . .
DM7822/DM8822 Dual Line Receiver.
DM7830/DM8830 Dual Differential Line Driver . .
DM7831/DM8831 TRI-STATE® Line Driver. . . . . . .. . . . . . . . . . . ... .
DM7832/DM8832 TRI-STATE® Line Driver ... . .... . ...... .
DM7833/DM8833 Quad TRI-STATE® Transceiver. .. . . . . . . . . . . . . .
DM7834/DM8834 Quad TRI-STATE® Transceiver . . . . . . . . . . . . . .
DM7835/DM8835 Quad TRI-STATE® Transceiver . . . . . . . . . . .
DM7836/DM8836 Quad NOR Unified Bus Receiver.
DM7837/DM8837 Hex Unified Bus Receiver. . . . . . . . . . . . . .. . ..
DM7838/DM8838 Quad Unified Bus Transceiver .. .
DM7839/DM8839 Quad TRI-STATE® Transceiver .. .
DM7875A/DM8875A TRI-STATE® 4-Blt Multiplier ... "
...... .
DM7875B/DM8875B TRI-STATE® 4-Bit Multiplier. ...
. ...... .
DM7880/DM8880 High Voltage 7-Segment Decoder/Driver (for Driving Sperry and
Panaplex IITM Displays) . . . . . . . . . . . . . . . . . . . ... ..... ..
DM8884A High Voltage Cathode Decoder/Driver (for Driving Sperry and Panaplex IITM Displays) ..
DM8885 MOS to High Voltage Cathode Buffer . . . . . . . . . . .
DM9602/DM8602 Dual TTL/Monostable Multlvlbrator
I
1-13.1
1-133
1-136
1-138
1-140
1-143
1-143
1-143
10-5
1-148
1-152
1-155
1-159
1-155
10-5
10-6
1-161
1-164
1-167
1-169
1-172
1-175
1-175
1-146
1-180
1-182
1-184
1-187
1-190
1-195
10-6
1-182
1-184
1-197
1-200
1-202
1-202
1-202
1-204
1-206
1-208
1-210
1-212
1-214
1-214
10-7
10-7
10-7
1-217
1-219
1-221
10-7
1-223
1-223
1-225
1-228
1-230
10-8
vii
SERI ES 54H/74H Reference to Package
DM54HOO/DM74HOO
DM54H01/DM74HOl
DM54H04/DM74H04
DM54H05/DM74H05
DM54H08/DM74H08
DM54Hl0/DM74Hl0
DM54Hll/DM74Hll
DM54H20/DM74H20
DM54H21/DM74H21
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
DM54H50/DM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
DM54H54/DM74H54
DM54H55/DM74H55
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73/DM74H73
DM54H74/DM74H74
DM54H76/DM74H76
DM54H78/DM74H78
SECTION 2
Dimensions, Waveforms, Test CirCUitS, and Ordering Information
(SN54HOO/SN74HOOI Quad 2·lnput NAND Gate . . . . . . . . . . . . . . . . . . . .
(SN54H01/SN74HOll Quad 2·lnput NAND Gate (Open Collectorl . . . . . . . . .
(SN54H04/SN74H041 Hex Inverter. . . . . . . . . . . . . . . . .. . ..........
(SN54H05/SN74H051 Hex Inverter (Open Collectorl . ..... . ..... '
(SN54H08/SN74H081 Quad 2·lnput AND Gate. .
. . . . . . .. .
(SN54Hl0/SN74Hl01 Triple 3·lnput NAND Gate
. .. .. . .... .
(SN54Hll/SN74Hll1 Triple 3·lnput AND Gate
.................
(SN54H20/SN74H201 Dual 4·lnput NAND Gate
. .. . . . . . . . . . . . . .
(SN54H21/SN74H211 Dual 4·lnput AND Gate. . . .. .......... ....
(SN54H22/SN74H221 Dual 4·lnput NAND Gate (Open Collectorl . . . . . . .
(SN54H30/SN74H301 8·lnput NAND Gate. .. . . . . . . . . . . . . . . . . . . .
(SN54H40/SN74H401 Dual 4·lnput NAND Buffer. . . . . . . .
. . . . . . . . ..
(SN54H50/SN74H501 Expandable Dual AND·OR·INVERT Gate .. . . .. ....
(SN54H51/SN74H511 Dual AND·OR·INVERT Gate . . . . . . . . . . . . . . . . . .
(SN54H52/SN74H521 Expandable AND·OR Gate .....
. . . . . . ..
(SN54H53/SN74H531 Expandable AND·OR·INVERT Gate...
.. . . . . . ..
(SN54H54/SN74H541 AND·OR·INVERT Gate . . . . . . . . . . . .
(SN54H55/SN74H551 Expandable AND·OR·INVERT Gate. . . . .
(SN54H60/SN74H601 Dual 4·lnput Expander. . .
(SN54H61/SN74H61I Triple 3·lnput Expander . . . . . . . . . . . . .. .
(SN54H62/SN74H621 3·2·2·3·lnput Expander.. ......
(SN54H71/SN74H711 JK Flip Flop with AND·OR Inputs ...
(SN54H72/SN74H721 JK Master/Slave Flip Flop. . .. . . . . . . . . . . . . . ..
(SN54H73/SN74H731 Dual JK Flip Flop with Separate Clocks. . . . . . . . . . . .
(SN54H74/SN74H741 Dual 0 Edge·Trlggered Flip Flop . . . . . . . . . . . . . . .
(SN54H76/SN74H761 Dual JK Master/Slave Flip Flop..
.... . . . .
(SN54H78/SN74H781 Dual JK Flip Flop with Preset and Clear Inputs
SERIES 54L!74L -
SECTION 3
Reference to Package Dimensions, Waveforms, Test CirCUitS, and Ordering Information
DM54LOO/DM74LOO (SN54LOO/SN74LOOI Quad 2·lnput NAND Gate. . . .
DM54L01/DM74LOl (SN54L01/SN74LOll Quad 2·lnput NAND Gate (Open Collectorl.. .
DM54L02/DM74L02 (SN54L02/SN74L021 Quad 2·lnput NOR Gate ..... . . . . . . . . . . .
DM54L03/DM74L03 (SN54L03/SN74L031 Quad 2·lnput NAND Gate (Open Collector I
DM54L04/DM74L04 (SN54L04/SN74L041 Hex Inverter. . . .. ........ .......
DM54Ll0/DM74Ll0 (SN54L10/SN74L101 Triple 3·lnput NAND Gate . . . . . . . . . . . . . . . . . . . .
DM54L20/DM74L20 (SN54L20/SN74L201 Dual 4·lnput NAND Gate. . . . . . .
DM54L30/DM74L30 (SN54L30/SN74L301 8·lnput NAND Gate. . .. ...
. . . . . . . ..
DM54L42A/DM74L42A (SN54L42A/SN74L42AI Low Power BCD to Decimal Decoder . ........
DM54L51/DM74L51 (SN54L51/SN74L511 Dual 2,Wlde AND·OR·INVERT Gate. ......
DM54L54/DM74L54 (SN54L54/SN74L541 4,Wlde 3·2·2·3·lnput AND·OR·INVERT Gate. . . . .
DM54L55/DM74L55 (SN54L55/SN74L551 2,Wlde 4·lnput AND·OR·INVERT Gate
DM54171/DM74171 (SN54171/SN741711 RS Flip Flop. . .. .
. . . . . . . . . . . . . . .. .
DM54L72/DM74L72 (SN54L72/SN74L721 JK Flip Flop. . . . . . . . . . . . . . . . . . . . . . . . ....
DM54173/DM74173 (SN54173/SN741731 Dual JK Flip Flop . . . . . . . . . . . . . . . . . .
DM54174/DM74174 (SN54174/SN741741 Dual 0 Flip Flop .. ..... .
DM54L78/DM74178 (SN54L78/SN741781 Dual JK Flip Flop
.. .. .. ..
DM54L85/DM74L85 (SN54L85/SN74L851 4·Blt Magnitude Comparator. . . . .. ...
DM54L86/DM74L86 (SN54L86/SN74L861 Quad EXCLUSIVE·OR Gate. . .
DM54L89A/DM74L89A (SN54L89A/DM74L89AI 64·Blt Random Access Memory ..
DM54L90/DM74L90 (SN54L90/SN74L901 Low Power Decade Counter. . . .
. . . .. .... .
DM54L91/DM74L91 (SN54L91/SN74L91I 8-Blt Shift Register. .. ..........
. . . . . . . . ..
DM54L93/DM74L93 (SN54L93/SN74L931 Ripple Binary Counter. . .
. ..........
DM54L95/DM74L95 (SN54L95/SN74L951 4·Blt Parallel·ln Parallel·Out Shift Register
. . . . . . ..
DM54L98/DM74L98 (SN54L98/SN74L981 4·B,t Data Selector/Storage Register
DM54L123/DM74L123 (SN54L 123/SN74L1231 Dual TTLIMonostable Multlvibrator
... . ...
viii
2·i
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2· 1
2·1
2·1
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
3·i
3·3
3·3
3·3
3·3
3·3
3·3
3·3
3·3
3·31
3·7
3·7
3·7
3·10
3·10
3·10
3·10
3·10
3·34
3·22
10·9
3·37
3·40
3·42
3·25
3·45
10· 10
SERIES 54L!74L - SECTION 3 (CONTINUED)
DM54L154A/DM74L154A (SN54L154A/SN74L154A) Low Power 4-Llne to 16-Llne
Decoder/Demultiplexer _. _ _ _.
. "
. ..
DM54L 165A/DM74L 165A (SN54L 165A/SN74L 165A) Low Power Parallel-In Serial-Out
8-Blt Shift Register
.. "
.. . ... ..
DM54L187 A/DM74L 187 A (SN54L187 A/SN74L187 A) 1024-Blt Read Only Memory
DM54L 192/DM74L 192 (SN54L192/SN74L 192) Up-Down Decade Counter. . ..
DM54L193/DM74L193 (SN54L193/SN74L193) Up-Down Binary Counter ...
DM70L95 TRI-STATE® Hex Buffer
. .. . ...
DM70L96 TRI-STATE® Hex Buffer
DM70L97 TRI-STATE® Hex Buffer
DM70L98 TRI-STATE® Hex Buffer
DM71 L22/DM81 L22 Quad 2-lnput Multiplexer
DM71 L23/DM81 L23 Quad 2-lnput Multiplexer.
DM75L11/DM85L11 TTL Dual Gated 0 Flip Flop
DM75L 12/DM85L 12 Dual JK, 0 Flip Flop ..
DM75L51/DM85L51 Low Power TRI-STATE@ Quad 0 Flip Flop
DM75L52/DM85L52 TRI-STATE® Decade Counter/Latch
DM75L54/DM85L54 TRI-STATE® Binary Counter/Latch
DM76L 13/DM86L 13 Quad Gated 0 Flip Flop . .
DM76L70/DM86L70 8-Blt Serial-In Parallel-Out Shift Register
DM76L75/DM86L75 Low Power Presettable Decade Counter ..
DM76L76/DM86L76 Low Power Presettable Binary Counter.
DM76L93/DM86L93 Ripple Binary Counter
DM76L97/DM86L97 TRI-STATE® 1024-Blt Read Only Memory
DM76L99/DM86L99 TRI-STATE® 64-Blt Random Access Memory
DM78L12/DM88L12 TTL-MaS Hex Inverter/Interface Gate
SERI ES 74S -
3-47
3-49
10-11
3-52
3-52
10-12
10-12
10-12
10-12
3-59
3-59
3-63
3-66
3-69
3-74
3-74
10-13
3-25
3-80
3-80
3-42
10-14
10-15
3-82
SECTION 4
Reference to Package Dimensions, Waveforms, Test CirCUitS, and Ordering Information
DM74S00 (SN74S00) Schottky Quad 2-lnput NAND Gate. .... . ..
DM74S03 (SN74S03) Schottky Quad 2-lnput NAND Gate (Open Collector)
DM74S04 (SN74S04) Schottky Hex Inverter
DM74S05 (SN74S05) Schottky Hex Inverter (Open Collector) .
DM74S10 (SN74S10) Schottky Triple 3-lnput NAND Gate ...
DM74S11 (SN74S11) Schottky Triple 3-lnput AND Gate.. . ....
DM74S15 (SN74S15) Schottky Triple 3-lnput AND Gate (Open Collector) . .
DM74S20 (SN74S20) Schottky Dual 4-lnput NAND Gate ...
DM74S22 (SN74S22) Schottky Dual 4-lnput NAND Gate (Open Collector) . .
DM74S40 (SN74S40) Schottky Dual 4-lnput NAND Buffer
DM74S64 (SN74S64) Schottky AND-OR-INVERT Gate
. . . . . . .. . .
DM74S65 (SN74S65) Schottky AND-OR-INVERT Gate (Open Collector) . .
DM74S74 (SN74S74) Schottky Dual 0 Flip Flop. . . .
DM74S86 (SN74S86) Schottky Quad EXCLUSIVE-OR Gate.. .. . ...
DM74S112 (SN74S112) Schottky Dual JK Flip Flop With Preset and Clear. . .. .
DM74S113 (SN74S113) Schottky Dual JK Flip Flop With Preset. . .
DM74S114 (SN74S114) Schottky Dual JK Flip Flop With Common Clock and Clear. . . .
DM74S135 (SN74S135) Schottky Quad EXCLUSIVE-ORINOR Gate. . .
DM74S140 (SN74S140) Schottky Dual 4-lnput NAND Line Driver. . . . .. ....
DM74S151/DM74S251 (SN74S151 /SN74S251) Schottky 8-lnput Multiplexer With True
and Complement Outputs. . . . . . .
. . . . . . .. . ... . .. ... .
DM74S153/DM74S253 (SN74S153/SN74S253) Schottky Dual 4-Llne to 1-Llne Data
Selector/Multiplexer
. .. ..... ....
DM74S157/DM74S257 (SN74S157/SN74S257) Schottky Quad 2-Llne to 1-Llne Data
Selector/Multiplexer. .. . .. ..... .... . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S158/DM74S258 (SN54S158/SN74S258) Schottky Quad 2-Llne to 1-Llne Data
Selector/Multiplexer (Inverting) . . . . .. . ..
4-j
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-5
4-1
4-1
4-1
4-5
4-1
4-7
4-7
4-7
4-7
jx
SERIES 930 -
SECTION 5
Reference to Package Dimensions, Waveforms, Test CirCUits, and Ordering Information
DM930 Dual 4-lnput Gate with Expander. .. . ...... ,. . . . . . . . . . . . . . . .
DM932 Dual 4-lnput Buffer with Expander. . . . . .. .
. . . . . . . . . . . ..
DM933 Dual 4-lnput Extender . . . . . . . . . . . .
DM935 Hex Inverter
DM936 Hex Inverter . . . . . . . . . . . . .. .... ..... ,., . . . . . . . . . . . . . .
DM937 Hex Inverter . . . . . . .. . ........ .
DM944 Dual 4-lnput Power Gate with Expander. . . .. . . . . . . . . . . . .
DM945 RS Flip Flop . . . . . . . . . . . . , ... ,.. . ....... .. . ....... ,.
..........
DM946 Quad 2-1 nput Gate. . . . . .. . . . .. .
. . . . . . . . . . . . ..
DM948 RS Flip Flop ..... . ..... . ..... .
. . . . . .. .,.... ..
DM949 Quad 2-lnput Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
............
DM957 Quad 2-lnput Buffer ..... ,
,. ,. . . . . . . . . . . . .. . . . . . . . . . . . .
DM958 Quad 2-1 nput Power Gate ...... , . , . .
. . . . . . .. . . . . . . . . . . ,.
DM961 Dual 4-lnput Gate with Expander .. ,.... . ........ .
DM962 Triple 3-lnput Gate
-DM963 Triple 3-1 nput Gate
DM1800 Dual 5-lnput Gate
DM1801 Dual 5-lnput Gate
. . . . . . . . . . . . ..
DM9093 Dual JK Flip Flop . .. . ... , ........ , . . . . . . . . . . . . . . . . . . . . . . ........
DM9094 Dual JK Flip Flop
. . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9097 Dual JK Flip Flop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9099 Dual JK Flip Flop
5-i
5-3
5-5
5-5
5·3
5·3
5-3
5-5
5·7
5-3
5~
5·3
5·5
5-5
5·3
5-3
5·3
5·3
5-3
5·7
5·7
5·7
5-7
SERI ES 9000 - SECTION 6
Reference to Package Dimensions, Waveforms, Test CirCUits, and Ordering Information . . . . . . . . . . ..
DM9002C Quad 2-1 nput NAN 0 Gate .. , ........ , . , . . .. . ....... , . . . . . . . . . . . . . . . . .
DM9003C Triple 3-lnput NAND Gate . . . . . , . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . .
DM9004C Dual 4·lnput NAND Gate .. , . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . .
DM9005C Dual AND-OR-INVERT Gate/Expander. . .. ........ . . . . . . . . . . . . . . . . . . . . . .
DM9006C Dual 4-1 nput Expander .. , . . . . . . . . . . . . . . . . . . . . . . . .. ....... . . . . . . . . . .
DM9008C 2·2·2·3-lnput AND-OR-INVERT Gate . . . . . . . . . . . . . . . . . . , .
. . .. ...
DM9009C Dual 4-1 nput NAN 0 Gate/Buffer .. , ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9012C Quad 2-lnput NAND Gate (Open Collector I ... , . . . . . . . . . . . . . . . . . . . . . . . , .....
DM9016C Hex Inverter. . . . . . . . . . .. ..
. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .
DM9300/DM8300 (SN54195/SN741951 4-Blt Shift Register ...... . . . . . . . . . . . . . . . . . . . . .
DM9301/DM8301 BCD to Decimal Decoder . . . . . . . . . . , . . . . . . .. . . . . . . . . . . . . . . . . . . . .
DM9309/DM8309 Dual 4-lnput Multiplexer . . . . . . . . . . . . . . . . . . . . . . .
...............
. . . . . . . .. .... ..
DM9312/DM8312 8-lnput Multiplexer . . . . . . . . . . ' . .. .......
DM9322/DM8322 Quad 2-lnput Multiplexer . . . . . . . . . . . . . . . .
, . . . . . . . . . , . . . . . ..
DM9601/DM8601 Retrlggerable Monostable Multlvlbrator . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . .
SERIES 10000 Reference
DM10101
DM10102
DM10105
DM10106
DM10107
DM10109
DM10110
DM10111
DM10112
DM10115
DM10116
DM10117
x
6·i
6-1
6·1
6-1
6·1
6-1
6·1
6-1
6·1
6·1
6-4
6-6
6-8
6·10
6-12
6·14
SECTION 7
to Package DimenSions, Waveforms, Test CirCUitS, and Ordering Information. . . . . . . . . ..
(MC101011 Quad OR/NOR Gate with Strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(MC101021 Quad Gate. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101051 Triple 2-3-2-0R/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ......
(MC101061 Triple 4-3-3·lnput NOR Gate. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101071 Triple EXCLUSIVE-OR/NOR Gate. . . . . . .. . ... ,..... . . . . . . . . . . .
(MC101091 Dual 4-5-lnput OR/NOR Gate . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . .
(MC101101 Dual 3-lnput/3-0utput OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101111 Dual 3-lnput/3-0utput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101121 Dual 3-lnput 1 ORf2 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101151 Quad Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC101161 Triple Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(MC10117CI Dual 2·Wlde OR-AND/OR-AND-INVERT Gate . . . . . . . . . . . . . . . . . . . . .
7-i
7-1
7·3
7-5
7-7
7-9
7-11
7-13
7-15
7-17
7·19
7·21
7-23
SERIES 10000 - SECTION 7 (CONTINUED)
DM10118
DM10119
DM10121
DM 10124
CMOS -
(MC10118)
(MC10119)
(MC10121)
(MC10124)
Dual 2-Wlde OR-AND Gate
4-Wlde 4-3-3-3-lnput OR/AND Gate.
OR-AND/OR-AND-INVERT Gate
Quad TTL to ECL Translator/Differential Line Driver
7-25
7-27
7-29
7-31
SECTION 8
Reference to Package Dimensions, Waveforms, Test CirCUitS, and Ordering Information
MM54COO/MM74COO Quad 2-lnput NAND Gate
MM54C02/MM74C02 Quad 2-lnput NOR Gate .
MM54C04/MM74C04 Hex Inverter .
MM54Cl0/MM74Cl0 Triple 3-lnput NAND Gate
MM54C20/MM74C20 Dual 4-lnput NAND Gate
MM54C42/MM74C42 BCD to Decimal Decoder .
DM54C73/MM74C73 Dual JK Flip Flop with Clear
MM54C74/MM74C74 Dual D Flip Flop
MM54C76/MM74C76 Dual JK Flip Flop with Clear and Preset
MM54C95/MM74C95 4-Blt Right-Shift Left-Shift Register
MM54Cl07/MM74Cl07 Dual JK Flip Flop with Clear.
MM54C151/MM74C151 8-Channel Digital Multiplexer
MM54C154/MM74C154 4-Llne to 16-Llne Decoder/Demultiplexer
MM54C157/MM74C157 Quad 2-lnput Multiplexer
MM54C160/MM74C160 Decade Counter with Asynchronous Clear.
MM54C161/MM74C161 Binary Counter with Asynchronous Clear ...
MM54C162/MM74C162 Decade Counter with Synchronous Clear_
MM54C163/MM74C163 Binary Counter with Synchronous Clear.
MM54C164/MM74C164 8-Blt Parallel-Out Sertal Shift Register ..
MM54C173/MM74C173
MM54C192/MM74C192
MM54C193/MM74C193
MM54C195/MM74C195
TRI-STATE® Quad D Flip Flop.
Synchronous 4·Blt Up!Down Decade Counter
Synchronous 4-Blt Up/Down Binary Counter
4·B,t Register. . .
INTERFACE CIRCUITS -
8-i
81
8-1
8-4
8-6
8-6
8-9
811
8-14
8·11
8-17
8-11
8-19
8-22
8-25
8-27
8-27
8-27
8-27
8-31
8-35
8-38
8-38
8-41
SECTION 9
Reference to Package DimenSions, Waveforms, Test CirCUitS, and Ordering Information
DH0006/DH0006C Current Driver
DH0008/DH0008C High Voltage, High Current Driver
DH0011/DHOOll C/DHOOll CN (SH2001/SH2002/SH2002P) High Voltage High Current Drivers
DH0016CN High Voltage High Current Driver
DH0017CN (SH2200P) High Voltage High Current Driver
DH0018CN High Voltage High Current Driver
DH0028C/DH0028CN Hammer Driver
DH0034/DH0034C High Speed Dual Level Translator
DH0035/DH0035C PIN Diode SWitch Driver
DH3467C Quad PNP Core Drivel
DH3725C Quad NPN Core Driver
LH2111/LH2211/LH2311 Dual Voltage Comparator
LM 106/LM206 Voltage Comparator/Buffer
LM306 Voltage Comparator/Buffer
LM 111/LM211 Voltage Comparator. _ ... _ ...
LM311 Voltage Comparator ...... _
9-i
9-1
9-4
9-7
910
910
9-10
9-13
9-15
9-18
9-20
9-22
9-24
9-26
9-28
9-30
9-35
LM 160 High Speed Differential Voltage Comparator
LM 161 High Speed Differential Voltage Comparator
10-16
1016
LM350 Dual Peripheral Driver.
LM710 Voltage Comparator
LM710C Voltage Comparator
LM711 Dual Comparator
9-40
9-42
9-44
9-46
Xl
INTERFACE CIRCUITS - SECTION 9 (CONTINUED)
LM711 C Dual Comparator
LM1488 Quad Line Driver.
LM1489/LM1489A Quad Line Receiver
LM1514/LM1414 Dual Differential Voltage Comparator
LM5520/LM7520 Dual Core Memory Sense Amplifier
LM5521/LM7521 Dual Core Memory Sense Amplifier
LM5522iLM7522 Dual Core Memory Sense Ampll f,er
LM5523/LM7523 Dual Core Memory Sense Amplifier
LM5524/LM7524 Dual Core Memory Sense Amplifier
LM5525/LM7525 Dual Core Memory Sense Amplifier
LM5528/LM7528 Dual Core Memory Sense Amplifier
LM5529/LM7529 Dual Core Memory Sense Amplifier
LM5534/LM7534 Dual Core Memory Sense Amplifier
LM5535/LM7535 Dual Core Memory Sense Amplifier
LM5538/LM7538 Dual Core Memory Sense Amplifier
LM5539/LM7539 Dual Core Memory Sense Amplifier
LM55325/LM75325 Memory DrIVer.
LM75324 Memory Driver with Decode Inputs
LM75450A Dual Peripheral Driver
LM75451 A Dual Peripheral Driver.
LM75452 Dual Peripheral Driver
LM75453 Dual Peripheral Driver
LM75454 Dual NOR Peripheral Line Driver
LM75461 Dual Peripheral Driver IHlgh Voltage)
LM75462 Dual Peripheral Driver IHlgh Voltage)
LM75463 Dual Peripheral Driver IHlgh Voltage)
LM75464 Dual Peripheral Driver IHlgh Voltage)
MH0007/MH0007C DC Coupled MOS Clock Driver
MH0009/MH0009C DC Coupled Two Phase MOS Clock Driver
MH0012/MH0012C High Speed MOS Clock Driver.
MH0013/MH0013C Two Phase MOS Clock DrIVer
MH0025/MH0025C Two Phase MOS Clock DrIVer
MH0026/MH0026C 5 MHz Two Phase MOS Clock Driver.
MH0027C Dual High Speed MOS Interface Driver
MH7803/MH8803 Oscillator/Clock Driver ... .
MH7807/MH8807 Oscillator/Clock Driver .. .
MH8804 Quad, Dual MOS Memory Driver
MH8805 Quad, Dual MOS Memory Driver
MH8808 Dual High Speed MOS Clock Driver
9-48
9-50
9-53
9-55
9-58
9-58
9-61
9·61
9-63
9·63
9-65
9-65
9-67
9-67
9-69
9-69
10-17
10-18
9-40
NEW PRODUCTS -
10-1
9-71
9-71
9-73
10-19
10-19
10-19
10-19
9-75
9-77
9-79
9-81
9-85
9-88
9-97
10-20
10-20
10-21
10-21
9-99
SECTION 10
AC TEST CIRCUITS AND WAVEFORMS
SECTION 11
PhYSical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Available Digital Applications Literature. . . .. . . . . . . . . . . . . . . .
xii
9-71
11-1
.....................
VII
Edge Index
by Product Family
D
g
g
9
Series 54/74
Series 54H/74H
Series 54L/74L
Series 74S
~
~
Series 930
Series 9000
0
Series 10,000
[;]
CMOS
m
m
Interface Circuits
New Products
(II
AC Test Circuits and Waveforms
Xli!
...
"'tJ
~s
0
c..
c:
Product Function Guide
C"l
r+
"T1
c:
:J
C"l
r+
GATES
DM5400/DM7400
DM5401/DM7401
DM5402/DM7402
DM5403/DM7403
DM5404/DM7404
DM5405/DM7405
DM5408/DM7408
DM5409/DM7409
DM5410/DM7410
DM5411/DM7411
DM5413/DM7413
DM5420/DM7420
DM5430/DM7430
DM5432/DM7432
DM5450/DM7450
DM5451/DM7451
DM5453/DM7453
DM5454/DM7454
DM5460/DM7460
DM5486/DM7486
DM7090/DM8090
DM7091/DM8091
DM7092/DM8092
DM54HOO/DM74HOO
DM54H01/DM74HOl
DM54H04/DM74H04
DM54H05/DM74H05
DM54H08/DM74H08
DM54Hl0/DM74HlO
DM54Hll/DM74Hl1
DM54H20/DM74H20
DM54H21/DM74H21
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
DM54H50/DM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
DM54H54/DM74H54
DM54H55/DM74H55
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM54LOO/DM74LOO
DM54L01/DM74LOl
DM54L02/DM74L02
DM54L03/DM74L03
DM54L04/DM74L04
DM54Ll0/DM74L10
DM54L20/DM74L20
DM54L30/DM74L30
DM54L42A/DM74L42A
DM54L51/DM74L51
DM54L54A/DM74L54A
DM54L55/DM74L55
DM54L86/DM74L86
DM74S00
DM74S03
DM74S04
DM74S05
DM74S10
DM74S11
DM74S15
DM74S20
DM74S22
DM74S64
DM74S65
DM74S86
DM74S135
DM930
DM933
DM935
DM936
DM937
DM946
DM949
DM961
DM962
DM963
DM1800
DM1801
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM10l01
DM10102
DM10105
DM10l06
DM10l07
DM10l09
DM10ll0
DM10lll
DM10112
DM10115
DM10116
DM10117
DM10118
DM10119
DM10121
0
:J
C')
c:
c..
(1)
BUFFERS/DRIVERS
DM5406/DM7406
DM5407/DM7407
DM5416/DM7416
DM5417/DM7417
DM5437/DM7437
DM5438/DM7438
DM5440/DM7440
DM54125/DM74125
DM54126/DM74126
DM7093/DM8093
DM7094/DM8094
DM7095/DM8095
DM7096/DM8096
DM7097/DM8097
DM7098/DM8098
DM7806/DM8806
DM54H40/DM74H40
DM70L95/DM80L95
DM70L96/DM80L96
DM70 L97/DM80L97
DM70L98/DM80L98
DM74S40
DM74S140
DM932
DM944
DM957
DM958
FLIP FLOPS
LATCHES
STORAGE REGISTERS
DM5470/DM7470
DM5472/DM7472
DM5473/DM7473
DM5474/DM7474
DM5475/DM7475
DM5476/DM7476
DM54107/DM74107
DM54173/DM74173
DM54174/DM74174
DM54175/DM74175
DM7511/DM8511
xv
Q)
;:s
::I
(!)
FLIP FLOPS
LATCHES
STORAGE REGISTERS
(con't)
c:
...
0
CJ
c:
DM7512/DM8512
DM7551/DM8551
DM7553/DM8553
DM7613/DM8613
::I
LL
...
CJ
::I
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73/DM74H73
DM54H74/DM74H74
DM54H76/DM74H76
DM54H78/DM74H78
;:s
0
...
D..
DM54L71/DM74L71
DM54L72/DM74L72
DM54L73/DM74L73
DM54L74/DM74L74
DM54L78/DM74L78
DM54L98/DM74L98
DM75L11/DM85L11
DM75 L 12/DM85 L 12
DM75 L51/DM85L51
DM76L 13/DM86L 13
DM74S74
DM74S112
DM74S113
DM74S114
DM54L90/DM74L90
DM54L93/DM74L93
DM54L1 92/DM74L 192
DM54L 193/DM74193
DM75L52/DM85L52
DM75L54/DM85L54
DM76L75/DM86L75
DM76L76/DM86L76
DM76L93/DM86L93
SHIFT REGISTERS
DM5491A/DM7491A
DM5495/DM7495
DM5496/DM7496
DM54164/DM74164
DM54165/DM74165
DM54166/DM74166
DM54195/DM74195
DM54198/DM74198
DM54199/DM74199
DM7570/DM8570
DM7590/DM8590
DM945
DM948
DM9093
DM9094
DM9097
DM9099
DM54L91/DM74L91
DM54L95/DM74L95
DM54L 165A/DM74L 165A
DM76L70/DM86L70
DM76L90/DM86L90
COUNTERS
MUL TIPLEXERS
DEMUL TIPLEXERS
DM5490/DM7490
DM5492/DM7492
DM5493/DM7493
DM54160/DM74160
DM54161/DM74161
DM54162/DM74162
DM54163/DM74163
DM54176/DM74176
DM54177/DM74177
DM54190/DM74190
DM54191/DM74191
DM54192/DM74192
DM54193/DM74193
DM54196/DM74196
DM54197/DM74197
DM7280/DM8280
DM7281/DM8281
DM7288/DM8288
DM7290/DM8290
DM7291/DM8291
xvi
DM7520/DM8520
DM7552/DM8552
DM7554/DM8554
DM7555/DM8555
DM7556/DM8556
DM7560/DM8560
DM7563/DM8563
DM9300/DM8300
DM54150/DM74150
DM54151/DM74151
DM54153/DM74153
DM54155/DM74155
DM54156/DM74156
DM54157/DM74157
DM7121/DM8121
DM7123/DM8123
DM7210/DM8210
DM7211/DM8211
DM7214/DM8214
DM7219/DM8219
DM7223/DM8223
DM7230/DM8230
DM7875A/DM8875A
DM7875B/DM8875B
DM71 L22/DM81 L22
DM71 L23/DM81 L23
DM74S151/DM74S251
DM74S153/DM74S253
DM74S157/DM74S257
DM74S158/DM74S258
DM9309/DM8309
DM9312/DM8312
DM9322/DM8322
DECODERS
DECODER/DRIVERS
DM5441 A/DM7441 A
DM5442/DM7442
DM5445/DM7445
DM5446A/DM7446A
DM5447A/DM7447A
DM5448/DM7448
DM54141/DM74141
DM54145/DM74145
DM54154/DM74154
DM8880
DM7884/DM8884
DM7885/DM8885
DM54L42A/DM74L42A
MEMORY PRODUCTS
DM5488/DM7488
DM5489/DM7489
DM54184/DM74184
DM54185A/DM74185A
DM54187/DM74187
DM74200
DM7573/DM8573
DM7574/DM8574
DM7575/DM8575
DM7576/DM8576
DM8582
DM7595/DM8595
DM7596/DM8596
DM7597/DM8597
DM7598/DM8598
DM7599/DM8599
DM54 L89A/DM7 4 L89A
DM54L187 A/DM74L 187 A
DM76 L97/DM86L97
DM76L99/DM86L99
COMPARATORS
DM5485/DM7485
DM7130/DM8130
DM7131/DM8131
DM7136/DM8136
DM7160/DM8160
DM7200/DM8200
DM54L85/DM74L85
..,
"tI
0
ARITHMETIC CIRCUITS
DM5483/DM7483
DM54181/DM74181
DM54182/DM74182
MUL TlPLI ERS
DM7875A/DM8875A
DM7875B/DM8875B
PARITY GENERATORS
DM54180/DM74180
DM7220/DM8220
ONE SHOT
DM541211DM74121
DM54123/DM74123
DM54L 123/DM74L 123
DM9601/DM8601
DM9602/DM8602
INTERFACE CIRCUITS
DM5426/DM7426
DM7800/DM8800
DM7810/DM8810
DM7811/DM8811
DM7812/DM8812
DM7819/DM8819
DM7833/DM8833
DM7834/DM8834
DM7835/DM8835
DM7836/DM8836
DM7837/DM8837
DM7838/DM8838
DM7839/DM8839
DM78L 12/DM88 L 12
DM10124
LM160
LM161
LM55325/LM75325
LM75324
LM75461
LM75462
LM75463
LM75464
MH7803/MH8803
MH7807/MH8807
MH8804
MH8805
c..
c:
CMOS
(')
r+
MM54COO/MM74COO
MM54C02/MM74C02
MM54C04/MM74C04
MM54C1 0/MM74C1 0
MM54C20/MM74C20
MM54C42/MM74C42
DM54C73/MM74C73
MM54C74/MM74C74
MM54C76/MM74C76
MM54C95/MM74C95
MM54C1 07 /MM74Cl 07
MM54C151/MM74C151
MM54C154/MM74C154
MM54C157/MM74C157
MM54C160/MM74C160
MM54C161/MM74C161
MM54C162/MM74C162
MM54C163/MM74C163
MM54C164/MM74C164
MM54C173/MM74C173
MM54C192/MM74C192
MM54C193/MM74C193
MM54C195/MM74C195
"T'I
c:
::;,
(')
=-.
0
::;,
G')
c:
c..
CD
xvii
C/)
...
CD
~s
Series 54/74
REFERENCE
The following table references all PhYSical DimenSion Drawings, Waveforms, and Test CirCUits for the devices
In this section. For Order Numbers, see below.* Refer to the alpha·numerlcal Index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are In the back of the catalog.
PACKAGES
DATA SHEETS
Molded DIP (N)
Devices
DM5400
DM7400
DM5401
DM7401
DM5402
DM7402
DM5403
DM7403
DM5404
DM7404
DM5405
DM7405
DM5406
DM7406
DM5407
DM7407
DM5408
DM7408
DM5409
DM7409
DM5410
DM7410
DM5411
DM7411
DM5413
DM7413
DM5416
DM7416
DM5417
DM7417
DM5420
DM7420
DM5426
DM7426
DM5430
DM7430
DM5432
DM7432
DM5437
DM7437
DM5438
DM7438
DM5440
DM7440
DM5441A
DM7441A
DM5442
DM7442
DM5445
DM7445
DM5450
DM7450
DM5451
DM7451
Cavity DIP (D)(J)
Pg.
Fig.
Pg.
Fig.
1·1
1·1
1·3
1·3
1·5
1·5
1·3
1·3
1·7
1·7
1·3
1·3
1·9
1·9
1·11
1·11
1·13
1·13
1·13
1·13
1·1
1·1
1·15
1·15
1·17
1·17
1·9
1·9
1·11
1·11
1·1
1·1
1·19
1·19
1·21
1·21
1·23
123
1·25
1·25
1·25
1·25
1·27
1·27
1·29
1·29
1·31
1·31
1·33
1-33
1·35
135
1·35
1·35
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
5
II
5
II
5
3
3
3
3
II
II
II
II
II
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
11
11
11
11
"
II
II
In
Type
Pg.
Type
Fig.
Pg.
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
'J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
18
18
18
18
V
V
V
V
V
W
W
W
W
W
19
V
W
19
V
W
19
19
18
V
V
V
W
W
W
18
V
W
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
*Order Numbers. use Device No. suffixed with package letter,
**Also available
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Pg.
Type
WAVEFORMS
Fig.
Pg.
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
3
3
1
1
3
3
42
42
2
2
3
3
1
1
4
4
I
1
1
3
3
1
1
1
1
1
1
5
5
9
9
1
1
1
1
TEST
CIRCUITS
Fig.
Pg.
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·19
11·19
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
11·5
1
1
2
2
1
1
2
2
1
1
2
2
4
4
4
4
1
1
2
2
1
1
1
1
1
1
4
4
4
1
1
2
2
1
1
1
1
6
6
2
2
6
6
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
111
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·5
11·5
11·6
11·6
11·5
11·5
11·5
11·5
1
1
2
2
1
1
1
1
11·1
11-1
11·4
11·1
11·1
11·1
11·1
11·1
4
e. DM7800W.
0 package. See page III.
l-i
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
DM5453
DM7453
DM5454
DM7454
DM5460
DM7460
DM5470
DM7470
DM5472
DM7472
DM5473
DM7473
DM5474
DM7474
DM5475
DM7475
DM5476
DM7476
DM5483
DM7483
DM5486
DM7486
DM5488
DM7488
DM5489
DM7489
DM5490
DM7490
DM5492
DM7492
DM5493
DM7493
DM5495
DM7495
DM5496
DM7496
DM54107
DM74107
DM54121
DM74121
DM54145
DM74145
DM54150
DM74150
DM54151
DM74151
DM54153
DM74153
DM54154
DM74154
DM54155
DM74155
DM54156
DM74156
DM54166
DM74166
DM54180
DM74180
DM54181
DM74181
DM54182
DM74182
DM54184
DM74184
...
Q)
(J)
D~54185A
DM74185A
DM54187
DM74187
DM54190
DM74190
Hi
Pg.
1·35
1·35
1·35
1·35
1·35
1·35
1·38
1·38
1·40
1-40
1-42
1·42
1·44
1·44
1·46
1·46
1·42
1·42
1·48
1·48
1·51
1·51
1·53
1·53
1·57
1·57
1·59
1·59
1·59
1·59
1·59
1·59
1·63
1·63
1·66
1·66
1·42
1·42
1·68
1·68
1·33
1·33
1·70
1·70
1·73
1·73
1·75
1·75
1·77
1·77
1·80
1·80
1·80
1·80
1·82
1·82
1·84
1·84
1·86
1·86
1·92
1·92
1·94
1·94
1·94
1·94
1·96
1·96
1·99
1·99
CavIty DIP (D)(J)
Flat Pack (F)(W)
Metal Can (G) (H)
FIg.
FIg.
Pg.
FIg.
3
3
3
3
3
3
3
3
3
3
5
5
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
5
3
3
5
5
II
II
II
II
II
5
3
3
3
3
3
3
3
3
II
II
II
II
II
II
II
II
II
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
11
11
12
12
12
12
11
11
11
11
11
11
11
11
12
12
12
12
11
11
12
12
13
13
12
12
12
12
13
13
12
12
12
12
12
12
11
11
13
13
12
12
12
12
12
12
12
12
12
12
3
3
3
3
5
5
5
5
5
3
3
II
II
II
5
II
7
III
5
II
5
II
7
III
5
II
5
II
5
II
3
II
7
III
5
II
II
II
5
II
5
II
5
II
5
II
Pg.
Type
FIg.
Pg.
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
19
V
W
19
V
W
19
V
W
18
V
W
19
19
V
V
W
W
18
V
W
18
V
W
18
V
W
18
V
W
19
V
W
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Type
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
FIg.
Pg.
Fig.
Pg.
1
1
1
1
11·5
11·5
11·5
11·5
1
1
1
1
11·1
11·1
11·1
11·1
6
6
6
6
7
7
8
8
6
6
11·5
11·5
11·5
11·5
11·6
11·6
11·6
11·6
11·5
11·5
1
1
1
1
1
1
1
1
1
1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
15
15
13
13
16
16
18
18
18
18
18
18
14
14
11·9
11·9
11·8
11·8
11·9
11·9
11·10
11·10
11·10
11·10
11·10
11·10
11·9
11·9
1
1
2
2
7
7
1
1
1
1
1
1
1
1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
6
6
11·5
11·5
11·1
11·1
11·1
11·1
11·1
11·1
18
V
W
19
19
17
V
V
V
W
W
F
9
9
11·6
11·6
1
1
1
1
2
2
19
19
19
19
17
17
19
19
19
19
19
19
19
18
V
V
V
V
V
V
V
V
V
V
V
V
V
V
W
W
W
W
9
9
3
3
19
19
9
9
9
9
11·6
11·6
11·5
11·5
11·10
11·10
11·6
11·6
11·6
11·6
1
1
1
1
1
1
1
1
2
2
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
9
9
20
20
11·6
11·6
11·10
11·10
11·5
11·5
11·8
11·8
11·8
11·8
11·8
118
12
12
1
1
2
2
2
2
7
7
11·4
11·4
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
F
F
W
W
W
W
W
W
W
W
3
19
V
V
V
V
W
W
W
W
19
19
V
V
W
W
19
19
19
3
13
13
13
13
13
13
DATA SHEETS
PACKAGES
Molded DIP IN)
Devices
DM54191
DM74191
DM54198
DM74198
DM54199
DM74199
DM74200
DM7090
DM8090
DM7091
DM8091
DM7092
DM8092
DM7093
DM8093
DM7094
DM8094
DM7095
DM8095
DM7096
DM8096
DM7097
DM8097
DM7098
DM8098
DM7121
DM8121
DM7123
DM8123
DM7130
DM8130
DM7131
DM8131
DM7136
DM8136
DM7160
DM8160
DM7200
DM8200
DM72lO
DM8210
DM7211
DM8211
DM7214
DM8214
DM7219
DM8219
DM7220
DM8220
DM7223
DM8223
DM7230
DM8230
DM7280
DM8280
DM7281
DM8281
DM7288
DM8288
DM7520
DM8520
DM7551
DM8551
DM7552
DM8552
DM7553
DM8553
DM7554
DM8554
DM7560
Pg.
1·101
1·101
1·103
1·103
1·105
1·105
1·146
1·107
1·107
1·109
1·109
1·111
1·111
1·113
1·113
1·113
1·113
1·116
1·116
1·116
1·116
1·116
1·116
1·116
1·116
1·118
1·118
1·120
1·120
1·122
1·122
1·124
1·124
1·124
1·124
1·122
1·122
1·126
1·126
1·128
1·128
1·128
1·128
1·131
1·131
1·133
1·133
1·136
1·136
1·138
1·138
1·140
1·140
1·143
1·143
1·143
1·143
1·143
1·143
1·148
1·148
1·152
1·152
1·155
1·155
1·159
1·159
1-155
1·155
1·161
FIg.
Pg.
5
II
7
III
7
5
5
5
3
3
3
3
III
II
II
II
II
II
3
II
3
II
5
II
5
II
5
II
5
II
5
II
5
II
7
5
5
III
II
II
5
II
5
3
3
II
II
II
3
II
5
II
5
II
7
3
3
III
5
II
5
II
II
11
II
II
3
II
3
II
3
II
5
II
5
II
5
II
5
II
5
II
CavIty DIP IDIIJ)
Flat Pack IF)IW)
Metal Can IGIIH)
FIg.
Pg.
Type
FIg
Pg.
FIg.
12
12
13
13
13
13
IV
IV
J
J
J
J
J
J
0
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
19
19
17
17
17
V
V
V
V
V
V
W
W
F
F
F
F
19
19
18
18
18
18
18
V
V
V
V
V
V
V
W
W
W
W
W
W
W
18
V
W
19
19
19
19
19
19
19
19
19
19
19
16
17
17
19
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
W
W
W
W
W
W
W
W
W
W
W
F
F
F
W
19
V
W
19
19
18
V
V
V
W
W
W
18
V
W
19
V
W
19
19
17
17
18
V
V
V
V
V
W
W
F
F
W
19
V
W
18
18
18
18
18
18
19
V
V
V
V
V
V
V
W
W
W
W
19
V
W
19
19
19
19
19
19
19
V
V
V
V
V
V
V
W
W
9
12
12
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
10
10
12
12
12
9
12
11
11
11
11
12
12
12
12
10
10
11
11
12
12
12
12
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
IV
IV
IV
IV
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
D
D
J
J
J
D
J
J
J
J
J
J
J
J
J
0
D
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
17
Type
W
W
W
W
W
W
W
W
Pg.
type
WAVE·
FORMS
FIg.
Pg.
1
1
1
1
1
1
10
10
10
10
21
21
21
21
21
21
21
21
12
12
12
12
11
11
11·5
11·5
11·5
11·5
11·5
11·5
11·7
11·7
11·7
11·7
11·11
11·11
11·11
11·11
11·11
11·11
11·11
11·11
11·8
11·8
11·8
11·8
11·8
11·8
11
11
11·8
11·8
22 11·12
22 11·12
23 11·12
23 11·12
23 11·12
23 11·12
12 11·8
12 11·8
12·A 11·8
12·A 11·8
9 11·6
9 11·6
5 11·5
5 11·5
12 11·8
12 11·8
18 11·10
18 11·10
18 11·10
18 11·10
18 11·10
18 11·10
24 11·12
24 11·12
25 11·12
25 11·12
26 11·13
26 11·13
27 11·14
27 11·14
26 11·13
26 11·13
28 11·15
TEST
CIRCUITS
Fig.
Pg.
1
1
6
6
1
1
3
3
3
3
3
3
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
3
3
3
3
3
3
3
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
15
15
1
1
1
1
3
3
1
1
1
1
1
1
1
1
3
3
11
11
13
13
11
11
1
n
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11-4
11-4
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·1
11·3
11·3
11-4
11-4
11·3
11·3
11·1
1-lii
PACKAGES
DATA SHEETS
Molded DIP INI
Devices
DM8560
DM7563
DM8563
DM7570
DM8570
DM7573
DM8573
DM7574
DM8574
DM7575
DM8575
DM7576
DM8576
DM8582
DM7590
DM8590
DM7595
DM8595
DM7596
DM8596
DM7597
DM8597
DM7598
DM8598
DM7599
DM8599
DM7695
DM8695
DM7696
DM8696
DM7800
DM8800
DM7806
DM8806
DM7810
DM8810
DM7811
DM8811
DM7812
DM8812
DM7819
DM8819
DM7820
DM8820
DM7820A
DM8820A
DM7822
DM8822
DM7830
DM8830
DM7831
DM8831
DM7832
DM8832
DM7836
DM8836
DM7837
DM8837
DM7838
DM8838
DM7875A
DM8875A
DM7875B
DM8875B
DM7880
DM8880
DM8884A
DM8885
...
Q)
(/)
)
l-iv
Cavity DIP IDIIJI
Flat Pack IFIIWI
Fig
Pg.
Fig.
Pg.
Fig.
Pg.
Type
1-161
1-164
1-164
1-167
1-167
1-169
1-169
1-172
1-172
1-175
1-175
1-175
1-175
1·146
1·180
1-180
1-182
1-182
1-184
1-184
1-187
1-187
1-190
1-190
1-195
1-195
1-182
1-182
1-184
1-184
1-197
1-197
1-200
1-200
1-202
1-202
1-202
1-202
1-202
1-202
1-204
1-204
1-206
1-206
1-208
1-208
1-210
1-210
1-212
1-212
1-214
1-214
1-214
1-214
1-217
1-217
1-219
1-219
1-221
1-221
1-223
1-223
1-223
1-223
1-225
1-225
1·228
1-230
5
II
II
3
II
IV
IV
IV
IV
IV
III
III
III
III
III
III
III
III
J
5
12
12
12
11
11
9
9
9
9
10
10
7
III
7
5
III
II
10
10
9
5
II
12
12
7
III
10
7
III
10
10
5
II
5
II
5
II
7
III
7
III
10
9
12
12
12
12
12
10
10
10
10
J
J
J
J
Pg
Type
Metal Can IGIIHI
Fig.
II
II
II
II
II
II
II
II
II
III
D
J
J
3
II
3
II
3
II
3
II
5
II
5
II
3
II
5
II
5
II
5
II
5
II
5
5
5
II
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
11
11
12
12
12
12
11
11
12
12
12
12
9
12
9
12
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
12
Pg.
Fig.
Pg.
11-15
11-15
11-15
11-15
11-15
11-16
11-16
1
1
1
5
5
7
7
11-1
11-1
11-1
11-1
11-1
11-1
11-1
V
W
18
V
W
19
V
W
33
30
30
11-16
11-15
11-15
2
1
1
11-1
11-1
11-1
32
32
32
32
17
17
11-16
11-16
11-16
11-16
11-9
11-9
3
3
3
3
3
3
11-1
11-1
11-1
11-1
11-1
11-1
34"
34
11-17
11-17
4
4
4
4
4
4
35
35
11-5
11-5
11-5
11-5
11-5
11-5
11-17
11-17
2
2
2
2
2
2
2
2
11-1
11-1
11-1
11-1
11-1
11-1
11·1
11-1
12
12
12
12
11-8
11-8
11-8
11-8
3
3
3
3
11-1
11-1
11-1
11-1
D
D
D
D
D
J
J
J
J
J
D
D
D
D
J
J
J
J
J
J
J
J
J
J
J"
J
J"
J
18
18
V
V
V
V
H
H
W
W
18
18
18
18
18
18
18
18
18
18
V
V
V
V
V
V
V
V
V
V
W
W
W
W
W
W
W
W
W
W
18
18
19
19
19
19
V
V
V
V
V
V
W
W
W
W
W
W
19
19
19
V
V
V
W
W
W
J"
J"
J
J"
J
J"
J"
J
J
J
J
J
J
III
D
IV
J
III
D
IV
IV
IV
J
J
J
IV
J
II
II
Fig.
19
D
D
D
D
D
D
D
D
IV
IV
III
III
III
III
III
IV
IV
IV
IV
IV
III
III
III
III
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
Type
TEST
CIRCUITS
28
28
28
29
29
31
31
21
21
3
3
3
3
3
3
3
3
3
Pg.
WAVEFORMS
cc
s:s:
Series 54/74
(J'I(J'I
-'="-'="
NO
00
DM5400/DM7400(SN5400/SN7400) quadruple 2-input NAND gate
DM5410/DM7410(SN5410/SN7410) triple 3-input NAND gate
DM5420/DM7420(SN5420/SN7420) dual4-input NAND gate
................
CC
S:S:
'-1'-1
general description
-'="-'="
NO
00
features
Employing TTL (Translstor-Translstor-Loglc) to
achieve high speed at moderate power dissipation,
these gates provide the basic functions used in the
Implementation of digital integrated circuit systems. Characteristics of the circuits include high
noise immunity, low output Impedance, good
capacitive drive capability, and minimal variation
In sWitching times with temperature. The gates
are compatible with and Interchangeable with
Senes 54/74 equivalent.
•
TYPical NOise Immunity
•
Guaranteed
•
•
Fan Out
Average Propagation Delay
•
Average Power DISsipation
NOISe
1V
Immunity
400 mV
10
13 ns
10 mW per gate
schematic and connection diagrams
, ___......___.....___ '00
u
(shown for DM5410/DM7410)
DM5400/DM7400
Dual-tn-Line Package
DM5400
DM5410/DM7410
Dual-In-Line Package
Dual-I n-Llne Package
DM5420
DM5410
Flat Package
DM5420/DM7420
Flat Package
Flat Package
0
N
o::t
I'
operating conditions
absolute maximum ratings
~
Q
........
0
N
o::t
Il)
Vee
Input Voltage
Storage Temperature Range
Fan·Out
Lead Temperature (Soldering, 10 sec)
7.0V
55V
_65°e to +150'e
10
3000 e
SUJ;>ply Voltage (Vee)
DM54XX
DM74XX
MIN
MAX
495
4.75
5.25
525
V
V
-55
0
+125
70
°e
°e
UNITS
Temperature (T A)
DM54XX
DM74XX
~
Q
...o::t
-'0
electrical characteristics
I'
~
(Note 1)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
Input Diode Clamp Voltage
Vcc~5.0V, TA ~25°C, liN ~-12mA
...o::t
Logical "1"
Input Voltage
Vee ~ Min
~
Logical "0"
Input Voltage
Vee ~ Min
Logical "1"
Output Voltage
Vee ~ Min V ,N ~ 0 8V, lOUT ~ -400 /LA
Logical "0"
Output Voltage
Vee ~ Min
V ,N
Logical "1"
I nput Current
Vee
~
Max
V ,N
~2.4V
Logical "1"
I nput Current
Vee
~
Max
V ,N
~
5.5V
1
mA
Logical "0"
Input Current
Vee
~
Max
V ,N
~
O.4V
-1.6
mA
Output Short
Circuit Current
(Note 2)
Vee
~
Max V ,N
~
OV, Va
Supply CurrentLogical "0"
(Note 3)
Vee
~
Max V ,N
~
5.0V
3
5.1
mA
Supply CurrentLogical "1"
(Note 3)
Vee
~
Max V ,N
~
OV
1
1.8
mA
Propagation Delay Time to
Logical "0", tpdO
Vcc
~
5.0V,
T A ~ 25°C,
C ~ 50 pF
8
15
ns
Propagation Delay Time to
Logical" 1", tpd 1
Vee~
5.0V,
TA ~ 25°C,
C ~ 50 pF
13
25
ns
Q
........
0
-1.5
V
V
2.0
It)
Q
0
0
o::t
I'
~
Q
........
0
0
o::t
It)
~
Q
0.8
~
V
2.4
0.4
2.0V, lOUT ~ 16 rnA
40
~
OV
DM74XX
DM54XX
-20
-18
-55
Note 1: Unless otherwise specified minImax limits apply across the _55°C to +12SoC temperature range for the DM54XX and
across the O~C to 70°C range for the DM74XX All tYPlcals are given for Vee = 5 OV and T A = 2SoC
Note 2: Not more than 1 output should be shorted at a time
Nota 3: Each gate.
1·2
V
V
/LA
mA
Series 54/74
DM5401/DM7401 (SN5401/SN7401)
quad 2-input gate (open collector)
DM5403/DM7403(SN5403/SN7403) quad 2-input gate (open collector)
DM5405/DM7405(SN5405/SN7405) hex inverter (open collector)
general description
These Senes 54/74 functions are
applications where the normal TTL
output configuration IS not wanted
tions include Implementation of
function
designed for
"totem-pole"
Such applicathe Wire-OR
ASide from the output, the circuitry IS Identical
to the standard quad tWO-input gate (DM5400/
DM7400) and hex Inverter (DM5404/DM7404).
schematic and connection diagrams
4K
o
16K
INPUT
OUTPUT
INPUTS ~;....!_....J
"
....-_o GND
'----~
' - - -....-oGND
DM5405/DM7405
DM5401/DM7401, DM5403/DM7403
DM5403/DM7403
Dual-In-Line Package
DM5401/DM7401
Dual-In-Llne Package
DM5401
DM5405/DM7405
Dual-tn-Line Package
DM5405
Flat Package
Flat Package
absolute maximum ratings
7V
Vee
Input Voltage
5.5V
Operating Temperature Range DM5401, DM5403, DM5405 _55°C to +125°e
oOe to 70°C
DM7401, DM7403, DM7405
Storage Temperature Range
-65°C to +150 o e
Lead Temperature (Soldering, 10 sec.)
300°C
M
o
q,....
electrical characteristics
:E
(Note 1)
c
........
M
PARAMETER
oq-
CONDITIONS
II)
Input Diode Clamp Voltage
:E
c
Logical "1" Input Voltage
DM5401,3,5
DM7401,3,5
Vee=45V
V ee -475V
Logical "0" Input Voltage
DM5401,3,5
DM7401,3,5
Vee=45V
V ee -475V
Logical "1" Output Current
DM5401,3,5
DM7401,3,5
Vee = 5.5V
Vee - 525V V ,N =
MIN
TYP
T A = 25°C
Vee = 50V,
liN = -12 mA
MAX
-1 5
20
V
V
08
V ,N
UNITS
a 8V, VOUT = 55V
= a OV, V OUT = 5 5V
V
250
Il A
40
Il A
Logical "0" Output Voltage
DM5401,3,5
DM7401,3,5
Vee=45V
Vee 475V, V ,N = 2 OV
Logical" 1" I nput Current
DM5401,3,5
DM7401,3,5
Vee = 5.5V
Vee 5.25V, V ,N = 2 4V
40
Il A
Logical "1" Input Current
DM5401,3,5
DM7401,3,5
Vee = 5.5V
Vee - 5.25V, V ,N = 5 5V
1
mA
Logical "0" I nput Current
DM5401,3,5
DM7401,3,5
Vee = 5.5V
Vee - 5.25V, V ,N =04V
-16
mA
Supply Current-Logical "0" DM5401,3,5
(Each Gate)
DM7401,3,5
Vee=55V
Vee - 5.25V, V ,N =50V
30
51
mA
Supply Current-Logical "1" DM5401,3,5
(Each Gate)
DM7401,3,5
Vee = 5.5V
Vee - 5.25V, V ,N = OV
1.0
1.8
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee = 5.0V, TA = 25°C
COUT = 15 pF, RL = 39051 (Note 2)
3
Propagation Delay Time to a
Logical "1", tpdl
Vee=5.0V, T A =25°C
COUT = 15 pF, RL = 3.9 k51 (Note 2)
18
04
V
lOUT = 16 mA
Note 1: MiniMax Units apply across the guaranteed temperature range unless otherwise speCified.
All typlcals are given for Vee = 5.0V and TA = 25 0 e,
Note 2: COUT Includes deVice output capacitance of approximately 8 5 pF and wIring capacitance
1-4
75
28
15
ns
45
ns
Series 54/74
OM5402/0M7402 (SN5402/SN7402) quad 2-input NOR gate
general description
The DM5402/DM7402 IS a quad 2-lnput NOR gate
utilizing TTL (Transistor-Transistor Logic) to
achieve high speed at nominal power dissipation. It
IS completely compatible with other Series 54/74
devices.
10
• Fan-out
• Allowable Power Supply Variation
DM5402
DM7402
features
• Input Clamping Diodes
• TYPical NOise Immunity
400mV
• Guaranteed Noise Immunity
1V
4.5V to 5 5V
4.75V to 5.25V
• Average Propagation Delay
12 ns (with 50 pF)
• Average Power Dissipation
14 mW per gate
o
schematic and connection diagrams
DM5402/DM7402 (each gate)
r - - -...- -...--~t--o v"
16K
4K
OK
I.
DM5402/DM7402
Dual-In-Line Package
DM5402
Flat Package
OND
GND
V"
TOP VIEW
TOP VIEW
1-5
absolute maximum ratings
7V
5.5V
Vee
Input Voltage
Operating Temperature Range
DM7402
DM5402
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
oOe to 70 0 e
-55°e to +125°e
-65°e to +150 oe
300 0 e
(Note 1)
PARAMETER
CONDITIONS
Input Diode Clamp Voltage
MIN TYP MAX UNITS
Vee = 5.0V TA = 25°C
liN = -12 mA
-1.0
V
Logical "I" Input Voltage
DM5402
DM7402
V_"e = 4.5V
Vee = 4.75V
Logical "0" Input Voltage
DM5402
DM7402
Vee = 4.5V
Vee = 4.75V
Logical "I" Output Voltage
DMS402
DM7402
Vee = 4.5V
Vee = 4.75V Y'N = 0.8V, lOUT = -400I.lA
Logical "0" Output Voltage
DMS402
DM7402
_
_
Vee = 4.5V
Vee - 4.75V Y'N - 2.0V, lOUT - 16 mA
Logical "I" Input Current
DMS402
DM7402
Vee = 5.5V
_
Vee = 5.25V Y,N - 2.4V
40
I.IA
Logieal "I" Input Current
DM5402
DM7402
Vee = 5,5V
_
Vee = 5.25V Y,N - 5.5V
1
mA
Logical "0" Input Current
DMS402
DM7402
Vee = 5.5V
_
Vee = 5.25V Y'N - 0.4V
Output Short Circuit Current (Note 2)
DMS402
DM7402
_
Vee = 5.5V
Vee - 5.25V V OUT - 0
Supply Current-Logical "0"
(each gate)
DMS402
DM7402
_
Vee = 5.5V
Vee = 5.25V Y'N - 6.0V
3.6
6.3
mA
Supply Current· Logical "I"
(each gate)
DM5402
DM7402
Vee = 5.5V V = OV
Vee = S.25V IN
2.0
3.6
mA
2.0
V
0.8
2.4
-20
-18
V
V
0.4
V
-1.0 -1.6
mA
-32 -55
mA
Propagation Delay to a
Logical "0", tOd~
Vee = 5.0V TA = 25°C
C = SO pF
N = 10
3
9
15
ns
Propagation Delay to a
Logical "1". tOd1
Vee = S.OV TA
C = SO pF
N = 10
S
13
22
ns
= 25°C
Note 1: Minimax "mils apply across the guaranteed temperature range of oOe to 70°C for the
DM7402 and -55°C to +125°C for the DM5402 unless otherwise specified All tYPlcals are given for
Vee = 5 OV and T A = 25°C
Note 2: Only one output at a time should be short CirCUited.
1·6
-1.5
Series 54/74
DM5404/DM7404(SN5404/SN7404} hex inverter
general description
The DM5404/DM7404 IS a hex inverter utilizing
TTL to achieve high speed at nominal power dissipation. It IS totally compatible with other Series
54/74 devices.
•
•
•
features
•
•
•
Input clamping diodes
TYPical NOise Immunity
1V
•
400mV
Guaranteed NOise Immunity
10
Fan-out
Allowable Power Supply Variation
DM5404
4.5V to 5.5V
DM7404
4.75V to 5.25V
Average Propagation
12 ns (with 50 pF)
Delay
10 mW per gate
Average Power Dissipation
schematic and connection diagrams
II
DM5404/DM7404
16K
130
DM5404
DM5404/DM7404
Dual-I n-Line Package
Flat Package
GND
14
13
12
11
10
GND
TOP VIEW
TOP VIEW
1-7
absolute maximum ratings
7V
5.5V
Vee
Input Voltage
Operating Temperature Range
DM7404
DM5404
Storage Temperature Range
Lead Temperature (soldering, 10 sec!
electrical characteristics
oOe to 70°C
-55°C to +125°C
_65°C to +150°C
300°C
(Note 1!
CONDITIONS
PARAMETER
Vee ~ 5.0V
liN ~ -12 mA
Input diode clamp voltage
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
Logical "1" Input Current
Logical "1" Input Current
DM5404
DM7404
Vee = 4 5V
Vee
= 4.75V
DM5404
DM7404
Vee
~
DM7404
Vee = 4.75V
DM5404
DM7404
Vee
DM5404
Vee = 5.5V
= 5.5V
Vee - 5.25V
= 5.25V
DM5404 Vee = 5.5V
DM7404
Vee - 5.25V
Output Short Circu It Current
(Note 2!
DM5404
DM7404
Vee = 5.5V
Vee - 5.25V
Supply Current· Logical "0"
(each gate!
DM5404
Vee
DM7404
Vee - 5.25V
Supply Current· Logical "1"
(each gate!
DM5404
DM7404
Vee = 5.5V
Propagation Delay to a
Logical "0" tpdO
= 5.25V
TA = 25°C
~
10
= 25°C
= 10
TA
N
V
2.0
0.8
V
Y,N
= 0.8V, lOUT = -400}1A
Y'N
~
Y'N
= 2AV
40
}1A
Y'N
= 5.5V
1
mA
Y,N
~
-1.6
mA
V OUT
2.0V, lOUT
2A
0.4
-1.0
OAV
~
a
V
= 16 mA
-20
-18
V
-30 -55
mA
Y'N
= 5.0V
3.0
5.1
mA
Y'N
=a
1.0
1.8
mA
Vee = 5.0V
C = 50 pF
5
16
22
ns
Vee = 5.0V
C = 50 pF
3
9
15
ns
Note 1. MiniMax limits apply across the guaranteed temperature range of OoC to 70°C for the
DM7404, and _55°C to +125°C for the OM5404, unless otherwise specified All tYPlcals are given for
Vee = 5 OV and T A = 25°C
Note 2. Only one output at a time should be short circuited
1·8
V
= 5.5V
Vee
N
MAX UNITS
-1.5
4.5V
= 4.75V
DM5404 Vee = 4.5V
DM7404 Vee = 4.75V
DM5404 Vee = 4.5V
Vee
Propagation Delay to a
Logical "1", tpd1
TYP
Vee
DM7404
Logical "0" Input Current
MIN
TA ~25°C
Series 54/74
OM5406/0M7406,OM5416/0M7416
(SN5406/SN7406,SN5416/SN7416)
hex inverter buffers/drivers
general description
features
These TTL hex inverter buffers/drivers are fully
compatible for use with TTL and OTL logic circuits. Each Inverter features high-voltage, opencollector outputs (OM5406/OM7406 30 volts
minimum breakdown and OM5416/OM7416 15
volts minimum breakdown). These inverters also
feature high sink current capability. (OM5406,
OM5416 30 mA and OM7406, OM7416 40 mAl.
•
•
•
•
Input clamp diodes
High voltage open-collector outputs
OM5406/OM7406
OM5416/OM7416
High sink current capability
OM5406,OM5416
OM 7406, OM7416
30V
15V
30 mA
40 mA
15 ns typical propagation delay time
01
schematic and connection diagrams
Dual-In-Line and Flat Package
14
13
12
11
10
OUTPUT
4K
JK
2'
INPUT O-~>--~
2.
L------4~-__4>----4--....- 0 GNO
NOt9
Component valU8S shown are numlnal
TOPVIEW
GNO
1-9
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
DM5406/DM7406
DM5416/DM7416
Storage Temperature Range
Lead Temperature, (Soldering, 10 Sec)
operating conditions
(Note 1)
Supply Voltage
DM5406,DM5416
DM7406,DM7416
7.0V
55V
30V
15V
-65°C to +150°C
300°C
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°c
°c
30
40
mA
mA
Temperature (T A)
DM5406,DM5416
DM7406,DM7416
Output Sink Current
DM5406,DM5416
DM7406,DM7416
CD
o
~
I'
electrical characteristics
~
(Note 2)
C
.........
CD
PARAMETER
o
~
LO
~
C
CONDITIONS
MIN
TYP
MAX
2
Logical "1" I nput Voltage
UNITS
V
08
Logical "0" Input Voltage
V
Output Breakdown Voltage
DM5406!DM7406
Vee == Max, IOFF == 250 MA,
30
V
15
V
VIN = 0.8V
DM5416!DM7416
Vee
=
Max, IOFF == 250 MA,
Y'N =08V
Logical "0" Output Voltage
Vee
=
07
04
Mm, }IOUT == Max,
2V,
lOUT = 16 mA
VIN =
Logical "1" Input Current
Logical "0" Input Current
Supply Current - Logical "'"
Logical "0"
Vee = Max, V IN
Vee:' Max, VIN
Vee = Max, V IN
==
2 4V
5 5V
40
1
/lA
mA
;=
0 4V
-16
mA
mA
mA
=
Vee = Max, VIN = OV
30
42
Vee
27
38
=
Max, VIN
=
5V
Input Clamp Voltage
Vee = 5 OV, liN = -12 mA,
T A = 25°C
Propagation Delay to a Logical "0", tpdO
Vee = 5 OV, T A = 25°C,
C L = 15 pF, RL = 110n
Propagation Delay to a Logical "1 ", tpd1
Vee = 50V, TA = 25°C,
C L = 15 pF, RL = 110n
-1 5
V
15
23
ns
10
15
ns
Note 1: Absolute Maximum Ratings" are those values beyond which the operation of ihe device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operatIOn
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature range for the DM5406,
IJ
DM5416 and across the O°C to 70°C range for the DM7406,DM7416. All tYPlcals are given for VCC = 5.0V and TA = 25°C
1·10
V
V
c
s:
Series 54/74
(J1
.j:::o
o
-..J
.......
C
s:-..J
.j:::o
DM5407 /DM7407,DM5417 /DM7417
(SN5407/SN7407,SN5417/SN7417) hex buffers/drivers
o
-..J
c
s:
features
general description
(J1
.j:::o
....
-..J
These TTL hex buffers/dnvers are fully compatible
for use with TTL and DTL logic circu ItS. Each
buffer features high·voltage, open-collector outputs
(DM5407/DM7407 30V minimum breakdown and
DM5417/DM7417 15V minimum breakdownl.
These buffers also feature high sink current capability (DM5407, DM5417 30 mA and DM7407,
DM7417 40 mAl.
.......
•
Input clamp diodes
•
High voltage open·collector outputs
DM5407/DM7407
DM5417/DM7417
•
High sink current capability
DM5407,DM5417
DM7407,DM7417
•
14 ns tYPical propagation delay time
•
145 mW typical power dissipation
C
s:-..J
30V
15V
.j:::o
....
-..J
30mA
40mA
schematic and connection diagrams
Dual-In-Line and Flat Package
. - - - -.....- -.....- - - - - 0
Vee
OUTPUT
4K
3K
INPurO----OGND
Dual-In-Llne and Flat Package
4B
4.
IB
IV
4V
JB
3'
3V
2B
2V
GND
14
,.
2A
TOPVIEW
t
POSITIVE lOGIC Y=AB
tP,olSSlgnmentsforthIlIClrtlllt5ilfethesamefDlailpackages
1-25
absolute maximum ratings
VCC
Input Voltage
Output Voltage
Operating Temperature Range
Storage Temperature Range
operating conditions
(Note 1)
MIN~
70V
55V
5.5V
O()C to +70°C
Supply Voltage
DM5437,DM5438
DM7437,DM7438
-65°C to +150° C
Lead Temperature (Soldering, 10 sec I
4.5
475
Temperature (TAl
DM5437, DM5438
DM7437, DM7438
300"C
MAX
5.5
5.25
V
V
"C
+125
70
-55
0
UNITS
°c
I"M
.;t
I"-
:!:
c
.......
I"M
.;t
electrical characteristics
(Note 2)
It)
:!:
c
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Logical "0" Input Voltage
08
Vee ° Min, Y'N °
a 8V,
Logical "11/ Output Current
---
DM5438
DM7438
Vee ° Min, Y'N °
a 8V, V OUT °
Logical "0" Output Voltage
Logical "1" Input Current
250 0
5 5V
V
/.lA
mA
-16
mA
a
mA
155
85
mA
mA
a
rnA
Y'N ° 5 5V
a 4V
Vee:::: Max
Vee ° Max, All Inputs at OV
Logical "0"
DM543738
---DM7437,38
Vee ° Max All Inputs at 5V
-20
a
-70
9
5
34
54
-1 5
V
15
a
ns
11
18
a
ns
Vee ° 5 OV
TA ° 25"C
13
22
a
ns
Vee o5OV
TA ° 25°C
14
22
a
ns
Vee::;; Min, T A:::: 25°C, liN == -12 mA
Logical "0" tpdO
DM5437
--DM7437
Vee o5OV
TAo 25"C
9
Propagation Delay to a
DM5438
Logical "0"
Dr~7438
--.--
Vee ° 5 OV
TA ° 25 Q C
Propagation Dela\{ to a
Logical" 1" tpd1
flM54J7
DM7437
Propagation Delay to a
Logical" 1" tpd1
---
DM5438
DM7438
tpdO
/.lA
04
DM5437,38
DM7437,38
Input Clamp Voltage
V
40 a
10
Supply Current - Logical "1"
(each devlcel
Propagation Delay to a
24
V
V ,N o 24V
Vee ° Max, Y'N °
DM5437
-DM7437
lOUT ° 4 2 mA
UNITS
Vee ° Min, V ,N ° 2 OV, lOUT ° 48 mA
Vee:::: Max,
Logical "0" Input Current
MAX
V
Vee"" Min
Logical "1" Output Voltage
(Note 31
TYP
20
DM5437
DM7437
Output Short CircUIt Current
MIN
Vcc=Mm
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The
table of "Electncal Charactenstlcs" provides conditions for actual deVice operation
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature range for the DM5437,
DM5438 and across the O°C to 70°C range for the DM7437, DM7438 All typlcals are given for VCC ° 5.0V and TAo 25°C
Note 3: Only one output at a time should be shorted
1·26
Series 54/74
DM5440/DM7440(SN5440/SN7440} dual 4-input buffer
general description
features
Employing TTL (Translstor-Translstor-Loglc) the
DM5440(DM7440 buffer IS used when the high
fan-out IS desirable. In addition to driving a large
number of TTL inputs, this buffer can be used to
drive lines between equlpments, to operate small
relays and lamps (50 mAl, and to act as a clock
driver for synchronous logic systems. it IS completely compatible With other Series 74 devices.
•
Typical Noise Immunity
•
Guaranteed Noise Immunity
•
Fan Out
•
Diode Clamps on inputs
1V
400 mV
30
schematic and connection diagrams
u
OUTPUT X
Schematic shows one half of dual unit
DM5440/DM7440
Dual·ln-Line Package
DM5440
Flat Package
1-27
absolute maximum ratings
Vee
Input Voltage
Storage Temperature Range
Fan-Out
Lead Temperature (Soldering, 10 sec)
operating conditions
7.0V
55V
-65'e to +150'e
30
300'e
electrical characteristics
PARAMETER
Supply Voltage (Vee)
DM5440
DM7440
MIN
MAX
UNITS
475
475
5.25
5.25
V
V
-55
0
+125
70
'e
'e
Temperature (T A)
DM5440
DM7440
(Note 1)
CONDITIONS
MIN.
TYP.
MAX.
-1.0
-1.5
UNITS
Input Diode Clamp Voltage
Vee = 5.0V, TA = 25°C, liN = -12 mA
Logical "1"
I nput Voltage
Vee=Min
Logical "0"
I nput Voltage
Vee = Min
Logical "1"
Output Voltage
Vee = Min, V ,N = 0.8V, lOUT = -12 mA
Logical "0"
Output Voltage
Vee = Min, V ,N = 2.0V, lOUT = 48 mA
Logical "1"
Input Current
Vee= Max, V ,N = 2.4V
Logical "1"
I nput Current
Vee= Max, V ,N = 5.5V
1.0
mA
Logical "0"
Input Current'
V ee =Max,V ,N =O.4V
-1.6
mA
Output Short
CircUit Current
(Note 2)
Vee=Max,V'N=OV
-55
-70.0
mA
Supply Current - Logical "0"
(Note 3)
Vee = Max, V IN = 5.0V, 25°C
8.6
11.4
mA
Supply Current - Logical "1"
(Note 3)
Vee = Max, V ,N = OV, 25°C
2.0
3.6
mA
Propagation Delay Time to
Logical "0", tpd 0
Vee = 5.0V, TA = 25°C, C = 50 pF
F.O. = 30
10
15
ns
Propagation Delay Time to
Logical" 1", tpd 1
Vee = 5.0V, TA = 25°C, C = 50 pF
F.O. = 30
8
25
ns
2.0
V
0.8
2.4
40
Note 1: Unless otherwise specified minImax limits apply across the _55 0 C to +125° C temperature range for the DM5440 and
across the O°C to 70 0 e range for the DM7440 All tYPlcals are given for Vee = 5.0V and TA = 25°C.
Note 2: Not more than 1 output should be shorted at a time.
Note 3: Each gate.
1·28
V
V
0.4
-24.0
V
V
MA
~s
Series 54/74
DM5441A/ DM7441A (SN5441A/SN7441A)
BCD to decimal decoder/nixie* driver
general description
The DM5441A/DM7441A IS monolithic blnarycoded-decimal to decimal decoder. The BCD
number to be decoded IS applied to the four
Input lines; and the unique output corresponding
to the deCimal equivalent of the Input number
falls to a logical 0 level. Outputs are deSigned to
drive gas-filled-readout (N Ixle *) tubes but are also
able to operate with other low current lamps
and relays.
An over-range feature provides that if binary numbers between 10 and 15 are applied to the input
the least significant bit of these numbers (0
through 5) will be decoded on the output.
Dual~ln-Lme
u
logic table
connection diagram
and Flat Package
GN.
0
C
INPUT
B
A
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
0
1
0
0
4
0
1
0
1
S
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
0
0
1
lOW OUTPUT
0
3
1
9
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
1
0
1
2
3
1
1
1
0
4
1
1
1
1
5
lOVER RANGE)
typical applications
Nixle* Readout
"
Over-Range Decoding
INDICATOR TUBE
OVER RANGE
INDICATOR
- '00
I,.PUT5 \ :
INPUTS
INPUTS ON
DM545g~~~7450
~+=+~: \II'fPUTS
i: o---+~~
OUTPUT
v
EXPANDER
GATE 1 Of
0---+--<1....
1-x ~=====--J---.-:~L-t
E~::~~:R II xX <>:===t+t:~
0
IOM5453/OM7453
ONLY
X
INPUTS
1: 0---+--<1....
DM5460/DM7460 (each gate)
,------<> '00
,,,",,rj~2J
NOTES 1 l:onneetp,n90rI210p,n12ofOM5450/0M7450orDM5453iDM7453
2 Conn"otpm14o,11 top>n 11 ofDM5450IDM7450.,DM5453/DM1453
~-I--O ~
i
INPUTS
absolute maximum ratings
Vee
Input Voltage
Storage Temperature Range
Fan·Out
Lead Temperature (Soldering, 10 .ecl
operating conditions
Supply Voltage (Veel
DM54XX
DM74XX
Temperature (T A)
DM54XX
DM74XX
7V
5.5V
-65°C to +150 o e
10
300°C
electrical characteristics
MIN
MAX
UNITS
4.75
475
5.25
5.25
V
V
-55
0
+125
70
°e
°e
(Notes 1,3) (DM5450/DM7450, DM5451/DM7451, DM5453/DM7453,
DM5454/DM7454)
PARAMETER
CONDITIONS
Input Diode Clamp Voltage
Vee ~ 5.0V, TA ~ 25°C
liN ~ -12 mA
Logical" 1" I nput Voltage
Vee ~ Min
Logical "0" Input Voltage
Vee
Logical "1" Output Voltage
Vee ~ Min, V IN ~ 0.8V
lOUT ~ -400 JJ.A
Logical "0" Output Voltage
Vee ~ Min, V IN
lOUT ~ 16 mA
Logical "1" Input Current
Vee
~
Logical "1" Input Current
Vee
Logical "0" I nput Current
~
MIN
TYP
MAX
-1.5
2.0
UNITS
V
V
Min
0.8
2.4
V
V
~
2.0V
Max, V IN
~
2.4V
40
~
Max, V IN
~
5.5V
1
mA
Vee
~
Max, V IN
~
0.4V
-1.6
mA
Output Short Circuit Current
(Note 2)
Vee
~
Max, V IN
~
OV
Supply Current - Logical "0"
(Each Gate)
Vee ~ Max, V IN ~ 5.0V
Supply Current - Logical" 1"
(Each Gate)
Vee
Propagation Delay Ti me to a
Logical "0", tpdO
Vee ~ 5.0V, T A ~ 25°C
C ~ 50 pF, N ~ 10
15
ns
Propagation Delay Ti me to a
Logical "1", tpd1
Vee ~ 5.0V, TA ~ 25°C
25
ns
Propagation Delay Time to
Logical "0" Level
(through DM5450/DM7450 or
DM5453/DM7453)
Vee ~ 5.0V, TA ~ 25°C
C ~ 50 pF, N ~ 10
20
n~
Propagation Delay Time to
Logical "1" Level
(through DM5450/DM7450 or
DM5453/DM7453)
Vee ~ 5.0V, T A ~ 25°C
C ~ 50 pF, N ~ 10
34
ns
~
Max, V IN
~
0.4
-18
OV
-55
V
jJ.A
mA
3.7
6.5
mA
2.0
3.6
mA
C~50pF,N~10
Note 1: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature range for the DM54XX and
across the oOe to 70°C range for the DM74XX. All typical. are given for Vee
Note 2: Not more than 1 output should be shorted at a time.
Note 3: Measurements made with expandable Inputs open
1-Cl6
= 5.0V and T A = 25°C.
o
electrical characteristics
s:
er
== Inputs
1G and 2G connected together
c
absolute maximum ratings
s:UI
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM54155,DM54156
DM74155,DM74156
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
electrical characteristics
~
.-
7V
55V
5.5V
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
UI
UI
.......
C
s:......
~
.-
UI
UI
(Note 2)
CONDITIONS
PARAMETER
Logical "1" Input Voltage
DM54155,DM54156
DM74155,DM74156
Vee ~ 4 5V
Vee - 4 75V
Logical "0" Input Voltage
DM54155,DM54156
DM74155,DM74156
Vee~45V
MIN
TYP
MAX
20
08
Vee - 4 75V
Logical "1" Output Voltage
DM54155
Vee~45V
DM74155 -Vee ~ 475iT
Logical "1" Output Current
DM54156
DM74156
Logical "0" Output Voltage
DM54155,DM54156
DM74155,DM74156
Vee
DM54155,DM54156
DM74155,DM74156
Vee ~ 5 5V
Vee - 525V
DM54155,DM54156
DM74155,DM74156
Vee~
Vee ~ 55V
Vee - 525V
~
4 5V
475V
V
~
.-
V
0)
V OUT
~
~
24
-80011A
55V
250
04
24V
40
I1A
55V
V ee - 525V
V ,N
~
5 5V
1
mA
DM54155,DM54156
DM74155.DM74156
Vee~ 55V
Vee - 525V
V ,N
~
04V
-16
mA
DM54155.DM54156
DM74155,DM74156
Vee ~ 55V
Vee - 525V
V OUT
V OUT
Supply Current
DM54155.DM54156
DM74155,DM74156
Vee ~ 525V
Input Clamp Voltage
DM54155,DM54156
DM74155,DM74156
Vee~ 55V
Vee - 525V
Output Short Circuit Current
(Note 3)
switching characteristics
~
OV
~OV
-10
-20
-18
Vee~55V
liN
= -12 rnA
~
.-
UI
V
~
16 mA
s:
......
I1A
V ,N
Logical "0" I nput Current
C
V
~
Logical "1" Input Current
UI
.......
lOUT
lOUT
Vee
C
s:
UI
UNITS
-32
-55
mA
25
40
mA
-10
-15
0)
III
V
Vee = 5V, T A = 25°C, N = 10
PARAMETER
FROM
INPUT
TO
OUTPUT
LEVELS
OF LOGIC
tpdl
A, B, 2C,
1G, or 2G
V
2
tpdO
A, B, 2C
1G,or2G
Y
2
tpd1
AorB
Y
3
tpdO
AorB
Y
tpd'
1C
tpdO
lC
TEST
CONDITIONS
DM54155/DM74155
MIN TYP MAX
14
21
19
18
3
Y
Y
DM54156/DM74156
MIN
TVP MAX
UNIT
17
26
30
19
30
ns
27
22
33
ns
17
26
18
27
ns
3
18
27
21
32
ns
3
17
26
18
27
ns
ns
CL~50pF,
RL
~
400Q
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
deVices should be operated at these limits The table of "Electrlcal Characterrstlcs" provides conditions
for actual deVice operation
Note 2: Unless otherwise specified min/max limits apply across the _55°C to +125°C temperature
range for the DM54155,DM54156 and acros' the O°C to 70°C range for the DM74155,DM74156.
All typical, are given for VCC ~ 5.0V and TA ~ 25°C.
Note 3: Only one output at a time should be shorted.
1-81
Series 54/74
DM54166/DM74166(SN54166/SN74166) a-bit shift register
general description
The DM54166/DM74166 IS a parallel-In serial-in,
serial-out eight-bit shift register containing a gated
Clock, and overriding Clear. The parallel-In or
serial-in modes are determined by the Shift/Load input. The truth table below indicates the operation.
During paralielloading shifting IS prohibit~d. Clocking is accomplished on the rising edge of the
clock pulse through a 2-input NOR gate, permitting one Input to be used as a clock-inhibit
function. Holding either of the Inputs high inhibits clocking. To prevent false clocking the clock
inhibit' input should be taken high only when the
clock input is high.
features
• Shift Frequency
35 MHz
•
360 mW
Power DIssipation
.Iogic diagram
CLEAA SEA1AL SHIFT A
DATA LOAD
H
connection diagram
Dual-In-Line and Flat Package
truth table
I.
IS
2
1
SERIAL
INPUT
"
3
4
A
11
0
10
9
SHIFT LOAD
.,
'--_~_~
PARALlEL INPUTS
'-82
"
13
,
ClOCK CLOCK
INHIBIT
I'
GND
FUNCTION
1
Serial In Senal Out
a
Parallel In Senal Out
CLOCl\ClOCK
INH16n
c
absolute maximum ratings (Note
1)
s:
CJ1
,J:Io
operating conditions
..&
MIN
Supply Voltage
7V
55V
55V
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
_65°C to +150°C
Supply Voltage (Veel
DM54166
DM74166
MAX
45
4.75
en
en
UNITS
.......
v
v
55
525
C
s:
Temperature (T A)
300"e
~55
DM54166
DM74166
0
--.I
,J:Io
"e
"e
+125
70
..&
en
en
electrical characteristics
(Note 2)
PARAMETER
CONDITIONS
Logical "1 " Input Voltage
Vee
Logical "0" Input Voltage
Vcc=Mln
LOglCdl "1" Output Voltage
Vee
V 1H
Logical "0" Output Voltage
Vee
V 1H
=
-
'"
-800MA
VIL ·08V
Min
lOUT""" 16 mA
V 1L =08V
IOI,.JT
Vcc=Max
VIN-=24V
Input CUrtellt at Max Input Voltage
Vee
V ,N
Logical "0" Input Current
Vcc=Max
INote 31
SuplJly
CUI
rent
=-
Max
55V
Clear to Output, tpdO
TA - 25°C
Propagation Delay to a Logical "0" from
5 OV
Vee
T A · 25"C
CL =50pF, RL
V ee --50V
T A =25°C
C l - 50 pF, RL
Clock to Output, tpdl
Maximum Clock Frequency
0-
Vee - 5 OV
Data Setup Time
Vee
Mode Control Setup Time
tSETUP
12 rnA
·1 5
mA
35
'"
400Sl
30
ns
400n
26
ns
25
35
MHz
50 pF
20
ns
50V
TA = 25'C, CL = 50 pF
20
ns
Vee "'50V
TA=25"C, Cl. = 50 pF
30
ns
Vee'" 5 OV
TA = 25°C, C L = 50 pF
0
ns
=
TA = 25°C, C L
mA
V
50 pF, RL ·40051
25"C
Minimum Clock and Clear Pulse Width
Hold Time at Any Input, t HOLD
liN =
CL
Vce-=50V
TA
mA
116
Vcc-=50V
Propagation Delay to a Logical "1" frOr:1
mA
104
Vec=-Mln
tpdO
pA
1
57
Max
Illput Clamp Voltage
V
40
6
·20
·18
Plopagatlon Delay to a Logical "0" from
Clock to Output,
~1
V
V
04
VIN =04V
UNITS
V
24
Vee -- Mdx
Vee
MAX
08
Min
2V
2V
TYP
2
Logical "1" Input Current
Olltput Short ClfCLllt CUrient.
MIN
Min
=
Note 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed
Except for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these
limits. The table of "Electncal Characteristics" provides conditions for actual device operation
Note 2: Unless otherWise specified minImax limits apply across the -55°C to +125°e temperature range for the DM54166
and across the oOe to +70o e range for the DM74166 All tYPlcals are given for Vee ~ 5.0V and TA = 25°C
Note 3: Only one output at a time should be shorted
1-83
Series 54/74
DM54180/DM74180(SN54180/SN74180)
8-bit odd/even parity generator/checker
general description
features
The DM54180/DM74180 can both generate and
check parity on eight bits of information Separate
Inputs are provided which perform a two-fold purpose. They can be used to gate the outputs to a
known state regardless of the conditions on the
data Inputs; and in addition they can be used for
convenient expansion of longer words.
•
TYPical propagation delay
30 ns
•
TYPical power dissipation
180mW
•
Ease of expansion
logic diagram
EVEN
OUTPUT
DATA
INPUTS
aDO
OUTPUT
IN~~~
0----------------....1
I~~~~ o-----------------~
connection diagram
truth table
Dual·ln-line and Flat Package
DATA
INPUTS
I"
13
11
11
10
,
9
NUMBER OF BtT "1"8
AT DATA INPUTS
Even Number
Odd Number
Even Numher
Odd Number
Even or Odd
Even or Odd
-
-
2
1
G
H
~
,
3
EVEN
INPUT
ODD
INPUT
DATA
INPUTS
TOPVIEW
5
6
EVEN
ODD
OUTPUT OUTPUT
I'
GND
INPUTS
EVEN
ODD
OUTPUTS
EVEN
ODD
0
s:
absolute maximum ratings
Supply Voltage
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 1)
7V
5'5V
c
_65 C to +150"C
300°C
U'I
...
operating conditions
Supply Voltage (VCC)
DM54180
DM74180
~
MIN
MAX
UNITS
45
475
55
525
V
V
-55
0
+125
70
"c
"c
00
0
.......
0
s:
Temperature (T A)
DM54180
DM74180
~
...
~
00
0
electrical characteristics
(Note 2)
PARAMETER
!,:>
CONDITIONS
Logical "1" Input Voltage
Vrc-:oMlfl
Logical "0" Input Voltage
Vee
Logical "1" Output Voltage
\fcc
Logical "0" Output Voltage
Vee - Min
Logical "1" Input Current
Vee
=0
lOUT
~
-800 flA
24
-c;;
V
V
04
lOUT - 16 mA
V ,N
V ,N
Vee
UNITS
V
08
V
24V
5 5V
40
10
flA
mA
V ,N - 24V
V ,N -55V
80
flA
mA
~
~
_.-._---
,-.-.-.~--
Logical "0" Input Current
MAX
Max
At Each
Data I nput' {A to HI
At Even or Odd Input
-,-----~--
TYP
20
!\Ii'n
~~ !\!llil
=
MIN
Max
10
V ,N - 0 4V
At Each
-1 6
-32
Data Inputs (A to H)
At Even or Odd Input
Output Short Circuit Current DM54180
(Note 3)
DM74180
Vee
='
Max
DM54180
DM74180
Vee
=
Max
Vee
=
Min
Supply Current
(Each DeVice)
Input Diode
V OUT
c
OV
-20
-18
--
-55
-55
mA
49
56
mA
--
366
366
-11N~-12mA
mA
-
-1 5
V
40
45
60
68
ns
ns
32
25
48
38
ns
n5
32
25
48
38
n5
ns
Odd
40
45
60
68
ns
n5
Even or Odd
Even or Odd
13
8
20
10
ns
n5
Clamp Voltage
TA - 25'C
Parameter
tpd1
tpdO
From Input
To Output
Data
Even
Odd Input Grounded
tpdl
tpdO
Data
Odd
tpdl
tpdO
Data
Even
tpdl
tpdO
Data
Even Input Grounded
tpdl Even or Odd
tpdO Even or Odd
Vee - 5 OV
TA - 25 c C
C L - 50 pF
Fa - 10
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual deVice operation
Note 2: Unless otherwise specified min/max limits apply across the _55°C to +125°C temperature range for the DM54180,
and across the 0° C to 70° C range for the OM74180 All tYPlcals are given for V CC = 5.0V and T A =. 25° C
Note 3: Only one output at a time should be shorted
1-85
...
...
,...
CIO
~
Series 54/74
::?!
o
...
...
........
CIO
~
DM541811DM74181 (SN541811SN74181) arithmetic logic unit
It)
::?!
o
general description
The DM54181/DM74181 (SN54181/SN74181) IS
a high-speed arithmetic logic unit (ALUl/functlon
generator that has a complexity of 75 equivalent
gates on a monolithic chip This CirCUit performs
16 binary arithmetic operations on two 4-blt words
as shown In the function table. These operations
are selected by the four function-select lines (S0,
5" 52, 53 1 and Include addition, subtraction,
decrement, and straight transfer When perform Ing
arithmetic manipulations, the Internal carnes must
be enabled by applYing a low-level voltage to the
mode control Input (MI. A full carry look-ahead
scheme IS made available In the device for fast,
simultaneou~ carry generation with a group carry
propagate (PI and carry generate (GI for the four
bits In the package.
High speed arithmetic operations can be performed for up to N-blt words when the DM54181/
DM74181
IS used In conjunction with the
DM54182/DM74182.
For example, the tYPical addition time for the
DM54181/DM74181 IS 24 ns for four bits. When
expanding to 16-bit addition with the DM541821
DM74182, only 13 ns further delay IS added so
that the total addition time IS 37 ns, or 2.3 ns per
bit. One DM54182/DM74182 IS needed for every
16 bits (four DM54181/DM74181 Clrcuitsi.
If high speed IS not of Importance, a ripple-carry
Input (Cnl and a ripple-carry output (C n+4 1 are
available. However, the ripple-carry delay has also
been minimized so that arithmetic manipulations
for small word lengths can be performed without
external circuitry. The tYPical delay for the ripple
carry IS 12 ns for four bits. With a tYPical additIOn
time of 24 ns for four bitS, addition of two 8-blt
words is accomplished tYPically In 36 ns when
emploYing the ripple carry.
The DM54181 and DM54182 are characterIZed for
operation over the full military temperature range
of -55°C to 125°C; the DM74181 and DM74182
are chdl"acterlzed for operation from O°C to 70 D C.
features
•
Full look-ahead for high-speed operations on
long words
•
Input clamping diodes minimize transmissionline effects
•
Darlington outputs reduce turn-off time
•
Arithmetic operating modes:
AdditIon
Subtraction
Shift operand A one position
Magnitude comparISon
Plus twelve other arithmetic operations
•
Logic function modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
plus ten other logical operatIons
•
24 ns tYPical add time for four bits
•
12 ns tYPIcal carry time for four bits
connection diagram and table
Dual-In-Line Package
OUTPUTS
INPUTS
Vi" /' ','
1~
n
'I' I" I' V ;cT"' j,'5 Ai'114 "13
In 121 120 '9 118 117
I I I I I I II II
Al
iiI
A2
ii2
A3
ii3
G
DM54181/DM74181
PIN DESIGNA1)ONS
16
C"..
P
A-8
..
DESIGNATION
PIN NOS
A3,A2,A 1.Ao
19,21,23,2
63 ,82 ;81 .8 0
18,20,221
Word B Inputs
53 ,52 ,5,,50
3,4,5,6
Function Select
Inputs
Co
7
Carry Input
M
8
Mode Control
FUNCTION
Word A Inputs
DESIGNATION
PIN NOS
FUNCTION
A~B
14
Comparator Output
ji
'5
Carry Propagate
Output
Cn +4
16
Carry Output
G
17
Carry Generate
Vee
24
Supply Voltage
GND
12
GROUND
Output
iio
I I I I I I II II
, J' .I' r I' J' I' I' J' J'" J"I"
AU
S3
52
51
SO
Cn
INPUTS
TOPVIEW
1-86
M
I'D
1'1
1'2
GND
Input
F3.F2,FT,Fo
13,11,10,9
Function Outpu,ts
c
absolute maximum ratings
s:U1
(Note 1)
....00
~
7V
55V
55V
Supply Voltage
Input Voltage
Output Voltage
Operatmg Temperature Range DM54181
DM74181
Storage Temperature Range
Lead Temperature (Soldering, 10 sec}
....
-55"C to 125"C
aOc to 70~C
"'-
-65'C to 150 'c
300"C
s:....
C
~
....
00
electrical characteristics
....
(Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
DM54181
DM74181
Logical "0" Input Voltage
ee_=-~"~~~~ _~Vee=
4 75V
Logical "1" Output Voltage
DM54181
DM~
Logical "0" Output Voltage
Logical "1" Input Current
(Mode Input)
Logical "1" I nput Current
(Any
A or 8 Input)
V 1H =2V,V 1L =08V
DM54181
DM74181
Vee = 4 5V
Vee ",-OW
V 1H =2V,V 1L =-08V
DM54181
---DM74181
Vee -= 55V
Vee -'=' 525V
DM54181
---DM74181
Vee
=
Logical "0" Input Current
(Mode Input)
Logical "0" Input Current
(Any
Ii.. or B Input)
Logical "0" Input Current
lOUT =
08
V
04
V
V
24
-800 /JA
IOUT= 16mA
Vcc=525V
40
~A
120
~A
160
~A
200
~A
1
mA
V 1N =24V
DM54181
Vee = 5 5V
- , - - - - _. . .
DM74181Vee = 525V
DM54181
DM74181
UNITS
V
55V
Logical "1" Input Current
Logical "1" Input Current
MAX
2
Vee = 4 5V
Vcc=475V
6~;:~+-
(Any Input)
TYP
-,-~--
Logical" 1" I nput Current
(Any S Input)
(Carry Input)
MIN
Vcc=45V
Vee _. 4 75V
Vee = 55V
~-=525V
Vee = 55V
Vee - 525V
V IN -=55V
DM54181
Vee = 5 5V
DM7418'- ~"-Vee = 5 25V
DM54181
Vee = 55V
OM 74fsl r-v;;-~;-s 25 V
~~"-Vee'" 5 25V
(Any S Input)
DM54181
DM74181
Logical "0" Input Current
(Carry Input)
55"6~;:~+-- ~e=
Vee 525V
Output Short Circuit Current
(Note 3)
DM541S1
DM74181-
-1
~1
6
mA
,,3
~4
8
mA
-39
~6
4
mA
8
~8
mA
-55
-57
mA
VIN = 04V
~4
=
Vee=55V
Vee = 525V
V OUT
-
OV
-20
18
~
Bs & Cn, Other Inputs HIGH)
~~;:~:~- r-~='?2"-Vee 525V
88
88
127
140
mA
mA
GND All As, Bs & en,
Other Inputs HI G H
DM54181
DM74181
vee = 5 ~~
Vee = 525V
92
92
135
150
mA
mA
Input Clamp Voltage
DM54181
DM74181
Vee'" 4 5V
Supply Current
~
(GND All
=
Propagation Delay to a Logical "0" from
Cn to Cn+4 , t prlO
Propagation Delay to a L09lcal "1 ' from
Cn to Cn ,4, tpd1
Propagation Delay to a Logical "0" from
Cn to Any F, tpdO
V
14
19
ns
Ddf Mode
9
18
ns
Dlff Mode
13
18
ns
Dlff Mode
11
19
ns
Dlff Mode
15
25
ns
Vee = 50V
TA=25'C
Ddf Mode
12
25
ns
Vee -= 50V
TA = 25 c C
Dlff Mode
17
25
ns
Vee = 50V
T A = 25"C
Dlff Mode
11
25
ns
Dlff Mode
14
34
os
~
Vee"" 50V
T A = 25°C
Ddf Mode (Note 4)
Vee = 50V
T A = 25'-'c
Vee -0:·5 OV
TA = 25"'C
475V
Propagation Delay to a Logical "1 ' from
Vee = 50V
C n to Any F, tpd1
TA
Propagation Delay to a Logical "0" from
Any A or
8
to G, tpdO
Propagation Delay to a Logical "1" from
Any A or
8
to G, tpd1
Propagation Delay to a Logical "0" from
Any A or B to P, tpdO
Propagation Delay to a Logical "1" from
Any A or
8
to P, tpdl
Propagation Delay to a Logical "0" from
Any A or
8
to F, tpdO
1
-1 5
IIN=-12mA
Vee
25"C
Vee = 5 OV
T A = 25"C
Vee
5 OV
T A = 25 C
1 87
c
....
CIO
....
'lit
electrical characteristics (cont.)
"C~
PARAMETER
........
CIO
'lit
....
....
It)
~
Propagation Delay to a Logical "1" from
Vee"" 5V
Any A or B to F,
T A = 25°C
tpdl
MIN
Dlff Mode
TYP
MAX
UNITS
14
48
ns
14
34
Propagation Delay to a Logical "0" from
Any Po.. or B to Any f, tpdO
Vee = 5V
T A " 25°C
Logic Mode M
(Note 5)
Propagation Delay to a Logical" 1" from
Vee"" 5V
T A " 25°C
Logic Mode M "" 4 5V
16
48
Vee'" 5V
T A'" 25°C
Dlff Mode
26
48
Any
C
CONOITIONS
A to B to
Any f,
tpdl
Propagation Delay to a Logical "1" from
Any A to B to A::.B,
tpdO
Propagation Delay to a Logical "0" from
Any A or B to A::.B, tpdl
Vee:::: 5V
=
4 5V
os
Dlff Mode
25
50
Vee'" 5V
T A " 25c C
Sum Mode
(Note 6)
14
19
Vee'" 5V
T A " 25 c C
Sum Mode
en to Any F, tPdO
Vee = 5V
T A = 2S"C
Sum Mode
13
18
Propagation Delay to a Logical "1 ' from
en to Any F, tpdl
Vee'" 5V
T A" 25°C
Sum Mode
12
19
ns
Propagation Delay to a Logical "0" from
Vee:::: 5V
T A " 25°C
Sum Mode
16
19
ns
Sum Mode
13
19
ns
Sum Mode
17
25
ns
Sum Mode
12
19
ns
Sum Mode
15
32
ns
Sum Mode
14
42
ns
T A == 25°C
Propagation Delay to a Logical "0" from
en to Cn + 4 ,
tpdO
Propagation Delay to a Logical" 1" from
en to C n +- 4 ,
tpdl
Propagation Delay to a Logical "0" from
Any
A or B to G,
tpdO
Propagation Delay to a Logical" 1" from
Any
A or B to G,
Vee'" 5V
T A :::: 25°C
tpd1
Propagation Delay to a Logical "0" from
tpdO
Vee'" 5V
TA '" 25°C
Propagation Delay to a Logical "1" from
Any A or B to P, tpdl
TA = 25°C
Propagation Delay to a Logical "0" from
Any A to B to Any F, tpdO
Vee'" 5V
T A " 25°C
Propagation Delay to a Logical "1 'from
Any A or B to Any F, tpdl
TA = 25°C
Any A or B to P,
Vee'" 5V
Vee
=
5V
18
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherwise specified minimax limits apply across the -55"'C to +125°C temperature range for the DM54181
and across the O°C to 70 0 e range for the DM74181 All tYPlca[s are given for Vee = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted
Note 4: Dlff Mode S1 = S2 = 4 5V, So = S3 = M = OV
Note 5: LogiC Mode S1 = S2 = M = 4 5V, So = S3 = OV
Note 6: Sum Mode So = S3 = 4 5V, S1 = S2 = M = OV.
truth table
TABLE OF ARITHMETIC OPERATIONS
FUNCTION
OUTPUT FUNCTION
SELECT
lOW LEVELS ACTIVE
S3 82 81 80
L
L
L
L
H
HIGH LEVELS ACTIVE
F=Ammus 1
F = AS minus 1
F=A
F = A+S
L
L
L
L
L
H
F = AB minus 1
F = A+S
L
L
H
F = minus 1 12's complement)
F= minus 1 12's complement)
L
H
L
L
F
F = A plus AS
L
H
L
H
F '" AS plus [A+Bl
L
H
H
l
F" A minus B minus 1
F = A+B
L H H H
=
A plus [A+BI
F = A plus [A+BJ
L
F = [A+Bl plus AS
F = A minus B minus 1
F '" AS mmus 1
F = A plus AS
H
L
H
L
L
H
l
H
L
H
L
H
H
H
H
L
L
H
H
L
H
F
H
H
H
l
F=ASplusA
F '" [A+Sl plus A
H
H
H
H
F"'A
F '" A minus 1
F'" A plus B
F = AS plus [A+Sl
F'" A plus B
F '" A+S
F = A plus At
F'" AB minus 1
=
AB plus A
F
=
F'" A plus At
F
=
With mode control 1M) and Cnlow
tEach bit IS shifted to the next more significant pOSitIOn
1-88
[A+Bl plus AB
[A+Bl plus A
mode of operation
The DM54181/DM74181 has been designed to not
only Incorporate all of the designer's requ irements
for arithmetic operations, but also to provide 16
possible functions of two Boolean variables without the use of external circuitry_ These logic functions are selected by use of the four function-select
Inputs (So, S1, S2' S3) with the mode control
Input (M) at a high level to disable the Internal
carry_ The 16 logic functions are detailed In the
function table and Include exclUSive-OR, NAND,
AND, NOR, and OR functions.
Active-low data'
No Input carry, C n = 0
(H IGH logic level)
No output carry, Cn + 4 = 0
(HIGH logic level)
Subtraction IS accomplished by 1's complement
addition where the 1's complement of the subtrahend is generated Internally. The resultant output IS A-B-1 which requires an end-around or
forced carry to prov Ide A-B.
The DM541811DM74181 can also be utilized as a
comparator. The A = B output IS Internally decoded from the function outputs (Fa, 1"1, F 2, 1"3)
so that when two words of equal magnitude are
applied at the A and B inputs, It will assume a highlevel state to indicate equality (A = B)_ The device
should be In the subtract mode when performing
thiS comparison. The A= B output IS open-collector
so that it can be Wire-AND connected to give a
comparISon for more than four bits. The carry
output (C n +4 ) can also be used to supply relative
magnitude information. Again, the ALU should
be placed In the subtract mode by plaCing the
control lines at LHHL.
The DM54181/DM74181 IS designed with a Darlington output configuration (54H174H type) to
reduce the high-logic-level output Impedance and
thereby Improve the turn-off propagation delay
time All outputs are rated at a normalized fanout of ten at the low logic level and increased to a
fan-out of 20 at the high logic level. The Increased
high-logic-level fan-out allows the system designer
more freedom In tYing unused Inputs to driven
Inputs
The DM54181/DM74181 will accommodate actlvehigh or active-low data If the input carry and output carry are reinterpreted.
Active-high data: Cn +4 = 1 (HIGH logic level)
A~B
C n +4 = 0 (LOW logic level)
AB
C n +4 = 0 (HIGH logic level)
A:O;:B
truth table (cont,)
TABLE OF LOGIC FUNCTIONS
FUNCTION
OUTPUT FUNCTION
SELECT
53
'2
L
L
L
L
F=A
L
L
L
H
F '"
L
L
H
L
F = A+8
L
H
H
F = Logical 1
F'" LogIcal 0
H
L
L
F = A+B
F
.1 so
NEGATIVE LOGIC
POSITIVE LOGIC
F=A
As
F = A+B
F
=
=
AS
As
L
H
L
H
F=B
F '" B
L
H
H
L
F = AIIl8
F
L
H
H
H
F = A+B
F = AS
L
L
L
F
=AS
=
L
L
H
F
H
L
H
L
F=B
H
L
H
H
F
=
=
Ae8
F '" A+B
F = A@B
Aw8
F=B
F = AS
A+B
H
H
L
L
F'" Logtcal 0
F = LogIcal 1
H
H
L
H
F =AS
F = A+B
H
H
H
L
F '" AS
F = A+B
H
H
H
H
F=A
F=A
WIth mode control (M)
HIGH
For pOSitive logiC loglca) 1 =
logical 0 =
For negative logiC logical 1 =
logical 0 =
C n Irrelevant
HIGH VOltage
lOW Voltage
LOW Voltage
HIGH Voltage
1-89
...
...o::t
CX)
switching parameter measurement information
.....
:E
c
...o::t
;:::
DIFFMODE TEST TABLE
FUNCTION INPUTS' S1 = S2 = 4 5V. SO = S3 = M = OV
CX)
OTHER INPUT
It)
:E
INPUT
UNDER
TEST
PARAMETER
c
tPLH
A
tPHL
tPLH
8
tPHL
tPLH
tPHL
tPLH
tPHL
tpHL
lPlH
tPLH
tPHL
tPLH
tPHL
tpHL
tPLH
tpHL
OTHER DATA INPUTS
APPLY
GND
APPLY
45V
APPLY
GND
None
8
Remaining
Remaining
None
A
A
S, en
Remaining
Remaining
A
S, en
Remaining
A. and B, en
A
None
B
None
B
A
None
None
A
8
None
None
8
None
A
None
A
tplH
SAME BIT
APPLY
45V
None
B
B
A
Non~
Cn
None
None
Remaining
Remaining
A and S,
en
Remaining
A and S, en
Remaining
Ii. and B,
en
Remaining
A
S, en
Remaining
Remaining
A
S, en
All
A and Ei
None
OUTPUT
UNDER
TEST
F
Any
Any F
P
p
G
G
A=B
A=B
Cn +4
SUM MODE TEST TABLE
FUNCTION INPUTS SO:: $3 = 4 5V, 51 '" 52 = M = OV
OTHER INPUT
INPUT
SAME BIT
PARAMETER
UNDER
TEST
APPLY
45V
APPLY
GND
tPLH
A
jj
None
8
A
None
tPHL
tpLH
tPHL
APPLY
4.SV
Remaining
Any
F
Cn
Any
F
None
Remaining
A and B, C n
p
Remaining
Aand e,Cn
p
Remaining
A, C n
G
A
jj
A
None
None
tPLH
tpHL
A
None
8
Remaining
Remaining
None
tPLH
tpHL
8
None
A
tPLH
tpHL
Cn
None
None
LO~IC
PARAMETER
INPUT
UNDER
TEST
tPLH
tPHL
tPLH
tpHL
A
B
8
8
Remaining
A, Cn
G
All
All
Any F
A
8
or Cn+4
MODE TEST TABLE
S1 "" S2"' M = 4 5V, SO = S3 = OV
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
APPLY
APPLY
APPLY
APPLY
4 SV
GND
45V
GND
None
8
None
A and B,
None
OUTPUT
UNDER
TEST
Cn
Aand B
tPLH
tPHL
jj
APPLY
GND
Remaining
A and B
tPLH
tPHL
FUNCTION INPUTS
1-90
OTHER DATA INPUTS
A
None
Remaining
Cn
Remaining
A and B, en
OUTPUT
UNDER
TEST
Any
F
Any F
c
s:
logic diagram
U"I
~
-'
00
-'
.......
c
s:.....
~
-'
III
(4)
00
0------...,
-'
S)
S20-_ _ _ _- ,
(5)
S,o-___-,
(6)
So
0-----,
iiarV
(l1)
..
'
(16)
PI/IX
(151
"
(13)
B, 01-'OI+-~;>-t-1-tTM
A,OI::-:"~1--+H-t--"1
)-.....I--~,,:O,1 "
B,
o-+-..cf>+-+-i-++-'t
(22)
A,o----++t-if-+-1
(23)
r+-+---:",1O::O, fl
."
111
191
'.
A.
'"
181
'-
Vcc ",PINZ4
GNIl-P1Nt2
m
1-91
Series 54/74
DM54182/DM74182 (SN54182/SN74182)
look-ahead carry generator
general description
The DM54182/DM74182 (SN54182/SN74182) IS
a high-speed, look-ahead carry generator capable of
a'nticlpatlng a carry across four binary adders or
group of adders. It IS cascadable to perform full
look-ahead across n-bit adders, with only 13 ns
delay for each level of look-ahead. Carry, generatecarry, and propagate-carry functions are provided
as enumerated In the Pin designation table.
propagate (P) and carry generate (G) are In negated
form; therefore, the carry (Input, outputs, generate, and propagate) functions of the look-ahead Circuit are Implemented,ln the compatible forms. Reinterpretations of carry functions at the DM54181 /
DM74181 are also applicable and compatible with
the look-ahead package, Logic equations are:
Go + POC n
G 1 + P1 GO+ P 1 POCn
G2 + P2 G 1 + P2 P1 GO + P2 P1 PoCn
Cn +z
G G3 + P3 G2 + P3 P2 G1 + P3 P2 P1GO
P = P3 P2 P1PO
C n +x
High speed arithmetic operations can be performed
for up to N-bit words when the DM54181/
DM74181 is used in conjunction with the
DM54182/DM74182.
For example, the typical addition time for the
DM54181/DM74181 IS 24 ns' for four bits. When
expanding to 16-blt addition with the DM54182/
DM74182, only 13 ns further delay is added so
that the total addition time IS 37 ns, or 2.3 ns
per bit. One DM54182/DM74182 is needed for
every 16 bits (four DM54181/DM74181 circuits).
Cn +y
Carry inputs and outputs of the DM54181/
DM74181 are In their true form and the c~rry
Inputs of the DM54182/DM74182 are dlodeclamped to minimize transmission-line effects, and
Darlington outputs are employed to Improve turnoff times and reduce propagation delay times.
Typically, the average carry time IS 13 ns, and
power dissipation IS tYPically 180 mW or 11 mW
per gate.
logic diagram
connection diagram and table
Dual~ln-Line
Package
OUTPUTS
INPUTS
co••
" O-=--+-I-~-I-H+."
" o-:--+-I-I--I-H......-L../
DM54182/DM74182
"
OUTPUTS
INPUTS
TOP VIEW
DM54182/DM74182
PIN DESIGNATIONS
~UNCTION
DESIGNATION
GO,0,.02,03
--+-+.,,
PO'p"P2.P3
"0-:... .
4,2 15,6
Active LOW
Carry Propagate Inpuls
Carry Input
C,
12,11 9
Vee·PINtS
GND-PIN8
C, ••
FUNCTION
Carry Generate Outpul
ActoveLOW
Carry Ganera1e Inputs
"O"----......-+-L../
1-92
DESIGNATION PIN NOS
3,1,14,5
CarryOutpulS
Ca"yPropagateQutput
V"
Supply
Voll~ge
0
absolute maximum ratings
3:
(Note 1)
U1
~
7V
55V
55V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM54182
...a
CO
N
.......
_55°C to 125°C
O°C to 70°C
-6Soe to 150°C
300°C
DM74182
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
0
....3:
~
...a
electrical characteristics
CO
(Note 2)
PARAMETER
N
CONDITIONS
DM54182
MIN
DM74182
Vee'" 4 5V
V cc -475V
DM54182
V cc "'45V
DM74182
Vee
OM54182
DM74182
Vcc'=4SV
Vee 4,75V
10
DM54182
DM74182
Vee
Vee'" 4SV
475V
10= 16mA
Logical "1" Input Current
(en Input)
DM54182
Vee'" 55V
DM74182
V cc -525V
Logical "1" Input Current
DM54182
DM74iii2
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Ol,ltput Voltage
Logical "0" Output Voltage
frY 3
1nputl
TYP
MAX
V
20
08
475V
=
-800 /J.A
UNITS
V
V
24
04
V
V 1N "'24V
80
.A
~;:~'~~v
VIN '" 24V
120
.A
Vcc=55V
Vee = 525V
VIN '" 24V
160
.A
V cc "'55V
Vee - 525V
V 1N =24V
200
.A
Vee" 55V
V ce -525V
V IN .. 24V
360
.A
Logical "1" Input Current
(P2 Input)
DM54182
Logical "1" Input Current
(Po, l'" or G3 Input)
DM54182
Logical "1" Input Current
(Go or G 2 Input)
DM54182
Logical "1" Input Current
((31 Input)
g~~~f- 4~~':...
Vee'" 5 25V
V IN
2 4V
400
.A
Logical "1" Input Current
(Any Input)
DM54182
DM74182
Vce'" 55V
VIN '" 5 5V
1
mA
Logical "0" Input Current
(C n Input)
DM 54 Hl2
Vee=55V
Vee - 52q,V
-32
mA
Logical "0" Input Current
(1'3 Input)
DM54182
DM74182
V ec "'S5V
-48
mA
Logical "0" Input Current
{P2 Input)
DM54182
Vee=55V
Vce - 525V
Loqlcal "0" Input Current
(po. 'P 1 or G3 Input)
DM54182
Logical "0" Input Current
(Go or (;2 Inputs)
DM54182
DM74182
OM74182
DM74182
DM74182
Vee
Vee
525V
'"
525V
-64
mA
Vcc=55V
Vee - 5 2SV
-8
mA
DM74182
Vee=S5V
V ee ",525V
-144
mA
-16
mA
-100
mA
DM741S2
g
VIN '" 0 4V
OM74182
Logical "0" Input Current
(31 Input)
DM54182
V ec ",S5V
DM74182
Vee - 525V
Output Short CirCUit CUrrent
(Note 3)
g~;:~-
Vee=55V
Vee: 525V
Supply Current - All
Outputs HIGH
DM54182
OM74182
Vee'" 55V
V ce "'525V
27
Supply Current All
Outputs LOW
OM74182
Vee= S 5V
V ec -525V
45
45
65
72
mA
DM54182
-40
mA
Propagation Delay to a Logical "0" from
Carry Input to Carry Output, tprlO
Vee'" SOV
T A ", 25°C
CL '" 50 pF, RL '" 40051
14
22
n,
PropBgatlon Delay to a logical "0" from
Carry Propagate Inputs (P 3 to Carry
Generate (G) & Carry Propagate (P)
Vee=50V
TA =: 25°C
CL '" 50 pF, RL = 4QOn
11
22
n,
Propagation Delay to a Logical" 1" from
Carry Input to Carry Outputs, tpd1
Vee'" 5 OV
T A'" 25°C
CL '" 50 pF, RL '" 400n
11
17
n,
Propagation Delay to a Logical" 1" from
Carry Propagate Inputs (P s ) to Carry
Generate (G) & (P) Propagate, tprll
Vee'" 50V
TA= 2SoC
CL
10
17
n,
Outputs, tpdQ
=:
50 pF, RL '" 400!2
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" proVides conditIOns for actual deVice operation
Note 2: Unless otherwise speCified minimax limits apply across the -55°C to +125°C temperature range for the DM54182
and across the
oOe
to +70o e range for the DM74182.'AII tYPlcals are gIven for
Vee = 5 OV
and TA
= 25°C
Note 3: Only one output at a time should be shorted.
1-93
~s
Series 54/74
DM541841 DM74184 (SN 54184/SN74184)
BC 0 -to-binary converter
OM 5418 5AI DM7418 5A(SN 54185A/S N7418 5A)
binary-to-BCD converter
general description
When the enable input IS taken to the logic "1"
level all outputs go high. In addition, the unused
states of the DM54184/DM74184 and the unused
outputs of the DM54185A/DM74185A are pro·
grammed to be logical "1 "'s.
Both of these converters are mask options of the
DM5488/DM7488 256·blt Read·Only Memones.
In normal operation the least significant bit by·
passes the converter smce m all cases the bmary
and BCD LSB's are the same. Thus each device
performs a 6·blt conversion.
connection diagram
Dual-In-Line and Flat Package
BINAflVSELECT
OUTPUT
ENABLE
r:
115
v s
1
1'"
Y1
Y3
,
In
112
0
C
B
" "
YO
VB
9
'+
Y1
I I5 I6 I
I
):
"
L iu
, I I I I
i14
)33 y~4
)/ Gl~
)6
)5
OUTPUTS
TOPVIEW
truth tables
DM54185A/DM74185A
Binary-to-BCD Converter
BINARY
WORDS
DM54184/DM74184
BCD-to-Binary Conv~rter
BCD
WORDS
BI NAR V SE LEer
E
o
OUTPUTS
INPUTS
(See Note A)
D
C
B
ENABLE
A
G
V5
Y4
V3
Y2
Y1
1
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
L
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
4-5
G7
L
8··9
L
L
L
L
L
10-11
12-13
14-15
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
L
24-25
24-27
28-29
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
H
H
L
L
H
L
H
L
H
L
30-31
12 33
34-35
36-37
38-39
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
H
L
H
L
H
ANY
X
X
X
X
X
H
H
H
H
H
H
16 17
18··19
20-21
22-23
H
=
L
high level, L
L
L
H
=
L
low level, X
=
L
L
Irrelevant
Note A' Input conditions other than those shown produce high at
outputs Yl through Y5
Note B Outputs Y6, Y7, and Y8 are not used for BCD-to-blnary
c.onverslon
1·94
D
C
B
A
G
Y8
Y7
Y6
V5
YO
Y3
Y2
Y1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
10-'1
12·13
14-15
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
L
L
H
L
16-17
18-19
20-21
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
22-23
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
L
H
L
L
L
H
L
L
H
24-25
26-27
28-29
30-31
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
H
H
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
H
L
H
H
L
L
L
H
L
L
32-33
34-35
36-37
38-39
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
Ii
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
L
H
L
40-41
42-43
44-45
46-47
H
H
H
H
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
48-49
50-51
52-53
54-55
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
L
L
H
L
56-57
58-59
60-61
62-63
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
L
L
L
H
L
L
H
ALL
X
X
X
X
X
H
H
H
H
H
H
H
H
H
4-5
6-7
8-9
2 3
OUTPUTS
ENABLE
E
0-'
2-3
(See Note B)
INPUTS
BINARY SELECT
L
L
L
L
L
L
H
L
L
absolute maximum ratingS(Note
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
1)
7V
5.5V
5.5V
_65°C to +150°C
300°C
electrical characteristics
operating conditions
Supply Voltage (Veel
DM54184. DM54185A
DM74184, DM74185A
MIN
MAX
UNITS
45
4.75
5.5
5.25
V
V
-55
0
+125
70
°c
°c
Temperature (T A)
DM54184, DM54185A
DM74184, DM74185A
(Note 2)
PARAMETER
CONDITIONS
MIN
Logical "1" Input Voltage
Vcc=Mm
Logical "0" I nput Voltage
Vee~Mm
Logical "1" Output Current
Vee = Max, Vo ~ 5.5V
Logical "0" Output Voltage
Vee = Min, 10 ~ 12 mA
Logical "1" Input Current
Vee
~
TYP
20
100
0.4
Max, V, =24V
~04V
Logical "0" Input Current
Vee = Max, V,
Supply Current
Vee=Max
Input Clamp Voltage
Vce = Min, I, = -12 rnA
Propagation Delay to a Logical "0" from
Vce = 5 OV
T A ~ 25'C
CL~15pF
Vce = 50V
T A = 25°C
CL
Propagation Delay to a Logical "0" from
Enable to Output, tpdO
Propagation Delay to a Logical "1" from
Address to Output, tpd1
Propagation Delay to a Logical "1" from
Enab!e to Output, tpd1
UNITS
V
0.8
Vee ~ Max, V, ~ 5 5V
Address to Output, tpdO
MAX
50
V
/lA
V
40
/lA
1
mA
-1.6
mA
80
mA
-1,5
32
50
ns
15 pF
34
50
ns
Vee ~ 5.0V
TA = 25°C
CL~15pF
28
50
ns
Vee = 5.0V
T A = 2SoC
C L =15pF
27
50
ns
~
o
V
Note 1. "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they afe not meant to Imply that the deVices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherWise specified min/max limits apply across the _55°C to +125°C temperature range for the DM54184,
DM54185A and across the oOe
25'C
to
70°C range for the DM74184, DM74185A All typical, are given for Vee = 5,OV and T A =
1·95
Series 54/74
DM54187 /DM74187 (SN54187 /SN74187)
1024·bit read only memory
general description
The DM54187/DM74187 is a custom-programmed
read-only memory organized as 256 four-bit words.
Selection of the proper word IS accomplished
through the eight select inputs. Two overriding
memory enable mputs are provided; and when one
is taken to the logical "1" state, It will cause all
four outputs to go to the logical "1" state.
• 20 ns tYPical delay from enable to output
•
Open collector outputs for expansion
applications
•
Microprogrammmg
•
Code conversions
features
•
Look·up tables
•
•
Use for any memory where content is fixed
36 ns tYPical delay from address to output
logic diagram
171
",
10'
MEMO"' { "
ENABLE
68
Illi
114)
connection diagram
Dual-In-Line Package
1·96
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operatmg Temperature Range
7V
5.5V
5.5V
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
DM54187
DM74187
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
(Note 2)
CONDITIONS
MAX
TVP
MAX
UNITS
Logical "1" Input Voltage
DM54187
DM74187
Vee = 4.5V
Vee - 4.75V
Logical "0" I nput Voltage
DM54187
DM74187
Vee = 4.5V
Vee - 4.75V
Logical "1" Output Current
DM54187 Vee = 5.5V
DM74187 Vee - 5.25V
Vo = 5.5V
Logical "0" Output Voltage
DM54187
DM74187
Vee = 4.5V
Vee - 4.75V
lo=16mA
Logical "1" Input Current
DM54187
DM74187
Vee = 5.5V
Vee = 5.25V
Y,N =2.4V
40
!1A
= 5.5V
1
mA
-1.0
mA
2.0
0.8
DM54187 Vee=55V
DM74187 Vee - 5.25V
Y'N
DM54187
DM74187
Vee = 5.5V
Vee - 5.25V
Y,N = 0.4V
Supply Current
(each device)
DM54187
DM74187
Vec = 5.5V
Vee - 5.25V
All Inputs at GND.
Input Clamp Voltage
DM54187
DM74187
Vee = 4.5V
Vee - 4.75V
liN = -12 mA
Logical "0" I nput Current
V
40
0.4
75
110
V
J.lA
V
mA
-1.5
V
Propagation Delay to a Logical "0" from Vee = 5.0V
TA = 25°C
Enable to Output, tpdQ
CL = 30 pF
20
30
ns
Propagation Delay to a Logical ''0'' from Vee = 5.0V
Address to Output, tpdQ
TA = 25°C
CL
= 30 pF
37
60
ns
Propagation Delay to a Logical "1" from Vee = 5.0V
Enable to Output, tpd 1
TA = 25°C
CL = 30 pF
20
30
ns
Propagation Delay to a Logical "1" from Vee = 5 OV
Address to Output, tpd 1
TA = 25°C
CL
= 30 pF
36
60
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device
cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply
that the devices should be operated at these limits The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified mm/max limits apply across the _55°C to +125°C temperature
range for the DM54187 and across the oOe to 70°C range for the DM74187. All typicals are given
for Vec = 5 OV and T A = 25°C.
La7
ordering instructions
Programming instructions for the DM54187 or
DM74187 are solicited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordenng data_ Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part_ This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program_ This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly_
Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the cond it ions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched: Cards should be
punched accord ing to the data card format shown.
10-13
14
15-18
19
20-23
24
25-28
29
30-33
34
35-38
39
supplementary ordering data
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.
40-43
44
45-48
49
50-51
data card format
1- 3
4
5- 7
8- 9
52
53-55
Column
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
Punch a "-" (Minus sign)
56
57-58
59
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H = h ighlevel output, L = low-level output, X =
output irrelevant_
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "Hi., "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L",or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs_
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs_
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Blank
Punch a right-justified Integer representing
the binary Input address (007-255) for
the last set of outputs described on the
card.
60-61
Punch "DM"
62-66
Punch the National Semiconductor part
number 54187 or 74187.
Blank
67-70
Blank
c
Series 54/74
s:
U1
...
~
CD
o
.......
c
OM54190/0M74190(SN54190/SN74190)
up/down decade counter
s:
..."
~
general description
CD
o
The DM54190/DM74190 is a four-bit up/down
decade counter capable of being preset to any
number from 0 through 9. A smgle Clock line is
provided and depending upon the logic level on the
down/up control, proper direction of counting IS
ach ieved. The flip flops are triggered on the
positive·golng transition of the clock providing
that the Enable Input IS low. A logical 1 at the
Enable input inhibits counting. Level changes at
the Enable Input should be made only when the
Clock input is high. Information can be asyn·
chronously entered by puttmg the desired logiC
levels on the Data inputs and then taking the Load
input low. This may be done independent of the
state of the clock.
Two outputs have been made available to perform
the cascading function: ripple clock and maxlmum/
minimum count. The latter output produces a
high-level output pulse with a duration approxi·
mately equal to one complete cycle of the clock
when the counter overflows or underflows. The
ripple clock output produces a low-level output
pulse equal in Width to the low·level portion of
the clock input when an overflow or underflow
condition exists. The counters can be easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter If parallel
clocking IS used, or to the clock input If parallel
enabling IS used. The maximum/minimum count
output can be used to accomplish look-ahead for
high-speed operation.
logic and connection diagrams
Dual·1 n·Llne and Flat Package
~~
CLOCK
DATA
RIPPLE MAXI
A
CLOCK CLOCK Mill
L
RIPf'LE
CLOCK
LOAD
DATA
C
9
" " " " " '"
')...--.J.--l-.......~--..!!!!.., ~~~U~N
~
~
. . , I'
, , ,
n~
DATA
B
llA
'---'
OUTPUTS
;
ENABLE DOWN'
L.,.....!!!.
a.
00
GND
'--.---'
INPUTS
ASYNCHRONOUSINPUfS
OUTPUTS
LOWI",PUTTOlDAOSETSQA
Os-8Oc
A
CANDOo"O
operating modes
DOWN/UP
ENABLE
LOAD
MODE
X
L
H
H
H
Parallel Load
X
X
H
L
L
L
H
H
Pl" (161- Vee PI" IHI
~
GND
=::
high level, L
=::
No Change
'Count Up
Count Dow~
low level, X == Irrelevant
absolute maximum ratingS(Note
operating conditions
1)
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature ISoldeflng, 10 seel
Supply Voltage IVeel
DM54190
DM74190
Temperature IT AI
DM54190
DM74190
7V
5.5V
5.5V
-65°e to +150o e
3000 e
electrical characteristics (Note
PARAMETER
CONDITIOIliS
Logical ':0" Input Voltage
Vee'" Min
Logical ''1'' Output Voltage
Vee'" Min
V IH '" 2V
lOUT'" -800 iJ.A
V IL ""D8V
Vec'" Min
lOUT'" 16 rnA
V IL "0 8V
Logical "1" Input Current at Any
V IH
'"
2V
5.5
5.25
+125
70
o
MIN
TVP
MAX
0.8
24
04
Vee'" Max
40
Vee'" Max
120
Logical "0" Input Current at Any
Input Except Enable
Vee'" Max
Logical "0" Input Current at Erlable
Vee'" Max
V IN "'04V
Output Short CirCUit Current
(Note 3)
Vee'" Max
V OUT
Supply Current (each device)
Vee'" Max
Input Clamp Voltage
Vee"" Min
Propagation Delay to a Logical "0" from
Vee'" SOV
T A "'2SoC
Load to Outputs,
tpdQ
Vce '" 50V
Data to Output,
TA
tpdQ
'"
'"
OV
-20
-18
25°C
66
-16
mA
-48
mA
-65
mA
105
mA
-15
24
50
26
50
Propagation Delay to a Logical "0" from
Clock to Ripple Clock, tpdQ
Vee"'50V
T A "" 25°C
16
24
Propagation Delay to a Logical "0" from
Clock to Outputs, tpdQ
Vee'" SOV
T A '" 25"C
22
36
Propagation Delay to a Logical "0" from
Clock to MaxiMin, tpdQ
Vee'" 50V
TA '" 25°C
21
52
Propagation Delay to a Logical "0" from
Down/Up to Ripple Clock, tpdQ
Vee'" 5 DV
TA '" 25"C
21
45
Propagation Delay to a Logical "0" from
Down/Up to Max/Min, tpdO
TA '" 25°C
16
33
Propagation Delay to a Logical "1" from
Load to Outputs, tpdl
Vee'" 5.0V
TA "" 25"C
22
33
Propagation Delay to a Logical "1" from
Data to Outputs, tpdl
Vee =SOV
TA '" 25"C
12
22
ProlJagatlon Delay to a Logical "1 ' from
Clock to Ripple Clock, tpd1
Vee=50V
T A ". 25°C
14
20
Propagation Delay to a Logical "1" from
Clock to Outputs, tpdl
Vee'" 5.0V
19
24
23
42
Propagation Delay to a Logical "1" from
Clock to MaxiMin, tpd1
V
mA
Vee'" Max
Propagation Delay to a Logical "0" from
V
V
Logical ''1'' Input Current at Enable
Input Except Enable
UNITS
v
Vee'" Min
Logical "1" Input CUrient at
Maximum Input Voltage
-55
UNITS
2)
Logical "1" Input Voltage
Logical "0' Output Voltage
45
4.75
MAX
Vec=50V
TA '" 25°C
Vee "'50V
TA '" 25°C
V
ns
ns
Propagation Delay to a Lgolcal "1 ' from
DowniUp to Ripple Clock, tpd1
r
22
45
Propagation Delay to a Logical "1" from
Down/Up to MaxiMin, tpd1
Vee=50V
TA=25"C
14
33
ns
Maxlm~Jm
Vee'" 5.0V
T A '" 25~C
20
25
MH,
20
Clock Frequency f MAX
Vec"'50V
A '"
25"C
Input Clock Frequency fCLOCK
o
Width of Input Pulse tW(CLOeK)
25
Width of Load Input Pulse tW(l.. OAD)
35
Data Setup Time, tSEtuP
20
Data Hold Time, tHOLD
Note 1 "AbsOlute MaXimum Ratings" afe those values beyond which the safety of the devIce cannot be !:Iuaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVIces should be operated at these limits The table
of "Electrlcal Charactenstl<:l;" prOVides conditions for actual deVIce operauon
Note 2 Unless otherwise specified min/max limitS apply across the _55°C tb +125"C temperature range for the DM54190
and across the O·C to 70"C range for the DM74190 All typlcals are gIVen for Vee" 5 OV and TA ~ 25°e
Note 3' Only one output at a time should be shorted
o
~s
~
Series 54/74
OM5419110M74191(SN541911SN74191)
up/down binary counter
general description
The DM54191/DM74191 IS an up/down bmary
counter capable of being preset to any number
from 0 through 15. A single Clock line is pro·
vided and depending upon the logic level on the
down/up control, proper direction of counting IS
achieved. The flip flops are triggered on the
positive-going transition of the clock providing
that the Enable input is low. A logical 1 at the
Enable mput tnhlblts counting. Level changes at
the Enable input should be made only when the
Clock input is high. I nformation can be asynchronously entered by putting the desired logic
levels on the Data inputs and then taktng the Load
input low. This may be done mdependent of the
state of the clock.
Two outputs have been made available to perform
the cascading function: ripple clock and maximum/
mtnimum count. The latter output produces a
high-level output pulse With a duration approximately equal to one complete cycle of the clock
when the counter overflows or underflows. The
ripple clock output produces a low-level output
pulse equal tn width to the low-level portion of
the clock tnput when an overflow or underflow
condition exists. The counters can be easily cascaded by feedtng the ripple clock output to the
enable input of the succeeding counter if parallel
clocking is used, or to the clock input If parallel
enabling IS used. The maximum/minimum count
output can be used to accomplish look-ahead for
high·speed operation.
logic and connection diagrams
Dual·1 n-Line and Flat Package
Ir.lPUTS
OUTPUTS
INPUTS
~~
DATA
RIPPlE
CLOCK
1,
A
,
CLOC~
RIPPLE MAX'
CLOCK
n
"
MIN
DATA
LOAD
C
" '"
"
,
r--t-t-.-...~--"""" ~~~:uM~N
~
,
UAfA
,
'.
,
,
'.
;
,
;
fN BLE DOWN
0,
'.
~
J:
OUTPUTS
ASYNCIlROIIJOUSINPU1S
lDWINPUTIOlDADSETSO A A
a.
sa..
C ANDU
o
0
operating modes
DOWN/UP
X
X
L
H
ENABLE
LOAD
MODE
X
H
L
L
L
H
H
H
Parallel Load
No Change
Count Up
Count Down
H '" high level, L = low level, X = Irrelevant
P," 1161
~
Vee P'n (81- GND
D
absolute maximum ratings (Note 1)
operating conditions
Supply Voltage
Input VOltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
Supply Voltage (Vee)
DM54191
DM74191
Temperature (T A)
DM54191
DM74191
MIN
7V
5.5V
5.5V
-65°e to +150o e
3000 e
4.5
4.75
-55
0
MAX
5.5
5.25
UNITS
V
V
°e
°e
+125
70
electrical characteristics (Note 2)
~ONDITIONS
PARAMETER
Logical "1" Input Voltage
Vee
LOglCdl "0" Input Voltage
Vee'" Min
Vee"" Min
LOgICdl "'" Output Voltage
V IH = 2V
Vee::: 2V
Logical "0" Output Voltage
Logical "1" Input Current dt
Ma>llmum Input Voltage
MIN
M,n
TYP
MAX
2
V
0.8
lOUT'" -BOO J.lA
V 1L =DaV
24
V
V 1H '" 2V
04
Vee::: Max
VIN =55V
1
rnA
"A
Input Except Enable
Vee"" Max
V1N=~4V
40
Logical "'" Input Current at Enable
Vee::: Max.
VIN=24V
120
Input Except Enable
Vee::: Max
VIN "" 0 4V
Logical "0" Input CUf,rent dt Enable
Vee::: Max
VIN :::
Output Short CI(cult Current
(Note 3)
Vee = Max
V OUl = OV
Supply Current (each device)
Vee'" Max
Input Clamp Voltage
Vee
Propagation Delay to d Logical "0" from
Vee =SOV
T A = 2Soc
C, • 50 pF, R L ' 400n
Vee "'50V
T A'" 2SoC
C L = 50 pF, R L
Vee =50V
T , ' 25°C
load to Outputs, tpdQ
Propagation Delay to a Logical
Data to OUtput, tpdQ
Propagation Delay to a Logical
"a" from
"a .. from
Clock to Ripple Clock, tpdQ
Propagation Delay to a Logical "0" from
= Mm
Clock to Outputs, tpdQ
Vcc=50V
TA • 25°C
Propagation Delay to a Logloal "0" from
Vee' 5 OV
Clock lO MaxlMm, tpdQ
TA '" 25°C
PropagatIon Delay to a Logical "0" from
Vcc=50V
Down/Up to Ripple Clock, tpdQ
TA '" 25°C
PropagatIon Delay to a Logical
"a" from
V
lOUT::: 16 mA
V 1L "'08V
Logical "1" Input Current at Any
Logical "0" Input Current at Any
UNITS
Vec=50V
a 4V
-48
-20
-18
"A
rnA
rnA
-65
rnA
105
rnA
-15
V
24
50
ns
400n
26
50
ns
CL • 50 pF. RL • 40012
16
24
ns
C L = 50 pF, RL = 400n
22
36
ns
CL '" 50 pF, RL '" 400n
21
52
ns
CL = 50 pF, RL '" 400n
21
45
ns
CL.
SO pF, RL. = 400n
16
33
ns
CL • 50 pF, RL • 400n
22
33
ns
liN'" -12 mA
:=
:=
Down/Up to MaxlMm, tpdQ
TA
Propagation Delay to a Logical "1" from
Vcc=50V
Load to Outputs, tpdl
I , ' 26°C
Propagation Delay to a Logical "1" from
Data to Outputs, tpdl
Vee.:!: SOV
T A '" 2Soc
CL. = 50 pF, AI.. '" 400n
12
22
ns
Propagation Delay to a Logical "1" from
Vee = SOV
T A = 25°C
CL
50 pF, AL =4000
14
20
ns
Clock to Ripple Clock, tprjl
'
25°C
-16
V
Vee '50V
:=
Propagation Delay to a Logical "'" from
Clock to Outputs, tpdl
TA
400n
19
24
ns
Propagation Delay to a Logical "'" from
Clock to Max/Mm. tpd1
Vee = SOV
T A :: 25°C
CL • 50 pF. RL • 400n
23
42
ns
Propagation Delay to a Logical "1" from
CL • 50 pF, RL • 400n
22
45
ns
50 pF, RL • 4QOn
14
33
ns
= 2SoC
Down/Up to A.lpple Clock, tpd1
Vee'" 6,QV
T A 2SoC
Propagation Delay to a LbQlcal"'" from
Vcc=6QV
Oown/U" to Maw/Min, tpd1
T A '" 25°C
Maxlmlouli Clock Frequency f MA )(
Vee'" 5,QV
T A ::: 2SoC
=
CL '" 50 pF, AL '"
CL •
CL. '" 50 pF, R L ;;;
400n
20
25
MHz
Input Clock Frequency fc:l.oc~
0
Width of Input Pulse tw~CL.OC"')
25
ns
Width of Load Input Pulse tW(LOAO)
35
ns
Oat8 Setup Time, lsETUP
20
ns
0
ns
Data Hold Time, tHOl.O
Not. 1 "AI:IIOlute Maltlmum Aatmgl" are those values beyond whIch the cafety of the deVice cannot be guaranteed Eltcept
j
for "Operating Tempereture Atlnge" they are not meant to Imply that the devIces should be operated at these hmlts The table
of "Electrical Cl'laracterlSlIcs" provIdes conditions for ad:ual davice operation
Not. 21 UnlHi othirw,.e speCified minimax IlmlU apply across the -56·C to +126"C temperature range for the DM54191
afld acr'oss the rfc to 7rfC range for the OM74191 All 'tYpical. are given for Vee'" 5 OV and TA" 25"C
NOte 31 Only one output at a time mould be shorted
20
MHz
c
Series 54/74
s:
U'I
...
0l=Io
CD
(X)
OM54198/0M74198(SN54198/SN74198) 8-bit shift register
.......
C
general description
...
s:......
0l=Io
CD
The DM54198/DM74198 is an eight-bit shift
register capable of being operated in four modes:
(1) Parallel-Load, (2) Shift-Right, (3) Shift-Left,
(4) Clock Inhibit (do nothing)_
With inputs So and S, at logic "1" levels the
data on the A through H inputs will be entered
on the next clock pulse_ Whether shifting left or
nght, clocking occurs on the rising edge of the
clock pulse_ During loading shifting is Inhiblted_
Cascading is accomplished by connecting the
Shift-Right and Shift-Left inputs to the outputs of
Q H of the preceeding register or Q A of the following
register respectively_ Clocking is inhibited when
both mode control inputs are low_ The mode
control inputs should be changed only when the
clock input is high_
features
• Shift Frequency
35MHz
• Power Dissipation
360mW
log ic and connection diagrams
Dual In-Line and Flat Package
SHIFT
LEFT
SERIAL INPUT
Vee
8, INPUT
I"
ZJ
2Z
H
21
Ilti
INPUT
zo
G
Do
INPUT
I' "
INPUT
OF
F
17
DE CLEAR
E
16
" "
13
truth table
INPUTS
P-
r-
I
So
2
, •
5
•
1
SHIFT INPUT ~ INPUT Os INPUT
RIGHT
ABC
SERIAL
INPUT
TOP VIEW
8
Dc
•
INPUT
D
MODE
S,
So
L
L
L
H
H
10
no
11 )'2
CLOCK GND
H
L
H
Inhibit Clock
Shift Right
Shift Left
Parallel Load
(X)
absolute maximum ratings (Note 1)
operating conditions
MIN
Supply Voltage
I nput Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
7V
55V
55V
-65°C to +150'C
300'C
electrical characteristics
Supply Voltage !VCC)
DM64198
DM74198
CONDITIONS
PARAMETER
Vee = Min
Logical "1" Output Voltage
Vee = Min
V ,H = 2V
lOUT = -800 JJ.A
V ,L =08V
V ,H
Vee = Min
= 2V
lou; = 16 mA
V'c =08V
Vee = Max
V ,N
= 2 4V
Vee = Max
Y,N
= 5 SV
Voltage
Logical "0" I nput Current
Output Short Circuit Current
(Note 3)
o
MAX
V
V
'c
'c
V
V
24
04
V
40
mA
mA
-16
Va
UNITS
V
08
Vee = Max
Vee = Max
TYP
2
Logical "0" Input Voltage
Input Current at Maximum Input
+125
70
-55
MIN
Vee = Min
LogIcal ."" Input Current
5,5
525
UNITS
(Note 2)
Logical "1" Input VOltage
Logical "0" Output Voltage
45
475
Temperature (T A)
DM64198
DM74198
MAX
-20
-18
= OV
72
-57
mA
104
116
mA
ns
Supply Current (each device)
Vee = Max
Input Clamp Voltage
Vee = Min
liN
= -12 mA
Propagation Delay to a Logical "0" from
Clear to Output, tpdO
Vee = 5 OV
TA = 2SoC
Cc
= 50 pF,
Rc
= 400n
35
Propagation Delay to a Logical "0" from
Clock to Output, tpdO
Vee = S,OV
T A = 25°C
Cc
= 50 pF,
RL = 400n
30
ns
Propagation Delay to a Logical "1" from
Clock to Output, tpdl
Vee = 50V
TA = 25°C
CL
= 50 pF,
Rc = 400n
26
ns
Maximum Clock Frequency
Vee = 50V
TA = 25'C
V
-15
25
35
MHz
20
ns
~ 50 pF
20
ns
= 5,OV
T A = 25°C, CL = 50 pF
30
ns
Vee = SOV
T A = 25'C, C c = 50 pF
a
ns
Minimum Clock and Clear Pulse Width
Vee = 5,OV
TA = 25°C, Cc = 50 pF
Data Setup Time
Vee = 5,OV
TA
Mode Control Setup Time tSETUP
Vee
Hold Time at Any Input, tHocD
= 25°C, C c
Note 1: "Absolute MaXimum Ratings" are those values beyond Which the safety of the deVice cannot be guaranteed.
Except for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these
limits. The table of "Electrlcal CharacteristIcs" provides conditions fOr actual deVice operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +12So C temperature range for the DM54198
and across the O'C to +70'C range for the DM7419B All tYPleals are given for VCC = 5,OV and TA = 25'C
Note 3: Only one output at a time should be shorted,
1
1(111
Series 54/74
OM54199/0M74199(SN54199/SN74'99) 8·bit shift register
general description
The DM54199/DM74199 IS an 8-bit shift regIster capable of being operated In three modes.
(1) Pa~allel-Load, (2) Shift-Right, (3) Inhibit Clock.
Parallel load is accomplished by applYing the eight
bits of data and taking the Shift/Load control
Input low when the clock input IS not inhibited.
Data appears as the output after the positive transItion of the next clock pulse. DUring loading
shifting is inhibited. Shifting is accomplished
synchronously when Shift/Load IS high and the
clock Input IS not inhibited. Serial data IS entered
at the J-K Inputs. In order to cascade deVices,
connect the Q H output of one stage to the J-K
Inputs (tied together) of the following stage. Both
Clock and Clock Inhibit are Identical in function
and may be used Interchangeably to serve as
clock or a clock inhibit· Inputs Holding althe·r high
inhibits clocking; but when one is held low, the
other will clock the register. Therefore the clock
inhibit input shoUld be changed from low to high
only while the clock Input is high.
features
• Shift Frequency
35MHz
360mW
• Power Dissipation
logic and connection diagrams
ClOCKCLOCKJ
INHIBIT
RSHIFTI
A
LOAD
Dual·ln·Line and Flat Package
SHIFTflNPUT
Vee LOAD H
I"
2J
22
OH
21
INPuT
INPUT
G
QG
F
OF
20
19
18
17
INPUT
E
16
QE
CLEAR CLOCK
"
14
13
truth table
J-K INPUTS
INPUTS
at tn
-
l-
2
I
Ii:
J
SERIAL
,
4
, ,
7
• , "
11 1'2
INPUT QA INPUT DB INPUT Dc INPUT no CLOCK GNO
ABC
0.
INHIBIT
INPUTS
TOPVIEW
OUTPUT
tn+1
J
K
QA
L
L
H
H
H
QAn
L
H
L
H
L
CiAn
H '" high level, L = low level
NOTE A tn '" bit time before clock pulse
NOTE B. tn+l
=
bit time after clock pulse
0')
0')
....
"It
.....
:E
C
.......
en
en
....
absolute maximum ratings (Note
operating conditions
1)
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
L.ead Temperature IS"lde"ng, 10 sec)
7V
-55V
55V
_65°C to +150°C
300°C
Supply Voltage IVCC)
DM54199
DM74199
Temperature IT A)
DM54199
DM74199
"It
45
475
-55
0
MAX
55
525
+125
70
UNITS
V
V
°c
°c
ID
:E
c
electrical characteristics (Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
Vee = Min
Logical "0" Input Voltage
Vee = Mil'
Logical "1" Output Voltage
Vee = Min
V ,H = 2V
V,L = O.BV
Logical "0" Output Voltag.
Vee = Min
V ,H = 2V
lOUT = 16 rnA
V'L =Q8V
Logical" 1" I nput Current
Vee = Max
V 'N = 2 4V
40
iJ.A
Vee = Max
V 'N = 5 5V
1
rnA
= Max
V 'N = OAV
Input Current at Maxlm .... m Input
Voltage
Logical "0" Input Current
Vee
Output Short CirCuit Current
INote3)
Vee = Max
Su pply Current l.aCh deVice)
Vee = Max
2
UNITS
Logical "1" Input Voltage
V
O.B
lou~ = -BOO iJ.A
V 'N
24
V
04
-16
V
rnA
-20
-18
= OV
V
72
-57
rnA
104
116
rnA
Input Clamp Voltage
Vee = Min
liN = -12 rnA
Propagation Delay to a Logical "0" from
CI ear to Output, tpdO
Vee = SOV
TA = 2S'C
CL = SO pF, RL = 400n
Propagation Delay to a Logical "0" from
Clock to Output, tpdO
Vee = S.OV
T A ~ 25'C
CL
Propagation Delay to a Logical "1 ,,' from
Clock to Output, tpdl
Vee = 50V
TA = 25°C
Maximum Clock Frequency
Vee = 5.0V
TA = 25'C
Minimum Clock and Clear Pulse Width
Vee=50V
T A = 2S'C, CL = SO pF
20
Data Setup Time
Vee=50V
T A = 25°C, CL = 50 pF
20
ns
Mo<;ie Control Setup Time tSETUP
Vee = 5.0V
i
Hold Time at Any Input, tHOLD
Vee
= S.OV
-1 S
V
35
ns
RL = 400n
30
ns
CL = 50 pF, RL = 40011
26
ns
= 50 pF,
25
35
MHz
ns
A
= 2S'C, CL = SO pF
30
ns
TA
= 2Soc, CL = 50 pF
0
ns
Note 1: "Absolute MaxlIl"Ium Ratings" are those values beyond which the safety of the deVice cannot be guaranteed.
Except for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these
liMits. The table of j'Electncal CharacteristiCs" provides conditions for actual deVice operation
Note 2: Unless otherWise specified minima" limits apply aCross the -S5'C to +12SoC temperature range for the DM54199
and across the a'c to +70'C range for the DM74199. All tYPical. are given for VCC = 5.0V and TA = 25°C
Note 3: Only one output at a time should be shorted.
o
3:
....,
Series 54/74
o
CD
o
........
o
3:
CO
o
o
DM7090/DM8090 quad inverter/dual 2-input NAND buffer
CD
general description
The DM7090/DM8090 optimizes the flexibility of
the 16-pin package by providing two 2-input
NAND gates and four Inverters In the same package. The electrical specifications are totally compatible with all Senes 54/74 devices.
schematic and connection diagrams
Dual*1 n-Line and Flat Package
...---"-"'--QVee
4K
16K
Vee
130n
INVE~;~~ 0 - -...-1"
NANOo--
OUTPUT
GNO
TOP VIEW
1_107
o0')
o
absolute maximum ratings
00
operating conditions
(Note 1)
~
c
........
o0')
o.....
70V
55V
5.5V
_65°e to +150 o e
3000 e
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
~
c
electrical characteristics
Temperature IT AI
DM7090
DM8090
CONDITIONS
Vee
MIN
MAX
UNITS
4.5
4"75
55
5.25
V
V
-55
0
+125
70
°e
°e
(Note 2)
PARAMETER
Logical "1" Input Voltage
Supply Voltage IVeel
DM7090
DM8090
=
MIN
TYP
08
Vee'" Min, V IN
:::
0 8V,
lOUT:::
-400,uA
UNITS
v
Logical "0" Input Voltage
Logical "1" Output Voltage
MAX
20
Min
v
v
24
Logical "1" Output Current
Logical "0" Output Voltage
Logical "1" Input Current
Logical "0" I nput Current
Output Short Circuit Current
(Note 31
Supply Current - Logical "1"
04
Vee::: Max, V 1N
-=
Vee"" Max, V IN
:::
Max, V 1N
=
Vee
=
v
40
pA
5 5V
1
rnA
04V
-16
rnA
24V
DM7090
DM8090
a
Vee::: Max, V OUT
:::
Vee::: Max, V IN
;:::
0
Vee = Max, V IN
:::
5 OV
-20
-18
-55
rnA
11
rnA
31
rnA
(each device)
Logical "0"
Input Clamp Voltage
Vee -= 50V,
Propagation Delay to a Logical "0"
from Inputs to Outputs, tpdO
Vec
T A o25"C
Propagation Delay to a Logical "1"
from Inputs to Outputs, tpd1
TA
=
liN;::: -12 mA, T A
:::
50V
Vee;::: 5 OV
"
-1 5
v
g
15
ns
13
25
ns
-10
25"C
25"C
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation
Note 2: Unless otherwise specified min/max limits apply across the _55°e to +125°C temperature range for the OM7090 and
across the O°C to 70°C range for the OM8090. All typlcals are given for Vee 5 OV and TA = 25°e
Note 3: Only one output at a time should be shorted
0::
1-108
c
Series 54/74
....s:
o
CD
....
........
C
s:
CO
o
DM7091/DM8091 quad 2-input NAN D buffer
general description
The electncal specifications are totally compatible
with all Senes 54/74 devices.
The DM7091/DM8091 provides four 2-input gates
each with a fan-out of 30, in the same package.
schematic and connection diagrams
,---,_--"",-0() v"
4K
INPUT
0-_---'7'"
INPUT
0--+-.
luau
600le
OUTPUT
Dual·ln-Line and Flat Package
GND
14
13
12
11
TOP VIEW
10
CD
....
~
en
o
co
absolute maximum ratings
~
operating conditions
c
........
~
en
o
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
"~
c
70V
55V
55V
_65°C to +150 o e
300 0 e
electrical characteristics
(Note
PARAMETER
Supply Voltage 1Veel
DM7091
DM8091
Temperature (T A)
DM7091
DM8091
Vee = Min
Logical "0" Input Voltage
Vee = Min
MAX
UNITS
45
475
55
525
V
-55
o
+125
70
TYP
MAX
MIN
2
UNITS
V
0.8
2A
V
Logical "1" Output Voltage
Vee = Min, Y'N = 0 8V, lOUT = -12 mA
Logical "0" Output Voltage
Vee = Min, Y'N = 2 OV. lOUT = 48 mA
Logical "1" Input Current
Vee = Max, Y'N = 2AV
Vee = Max, Y'N = 5.5V
40
1
Il A
mA
Logical "0" I nput Current
Vee = Max, Y'N = OAV
-1.6
mA
Output Short Crreult Current
(Note 3)
Vee = Max
Supply Current - Logical "1"
Logical "0"
Input Clamp Voltage
Propagation Delay to a Logical
-18
V
-70
mA
Vee = Max, Y,N = 0
15
mA
Vee = Max, Y'N = 50V
46
mA
V ee =5.0V,T A =25°C,I'N=-12mA
"a"
V
04
-10
-15
V
from Any Input to Output, tpdO
Vee = 5.0V
TA = 25°C
8
15
ns
Propagation Delay to a Logical "1"
from Any I nput to Output, tpd1
Vee = 5.0V
T A = 25°C
13
22
ns
Note 1 "Absolute M'axlmum Ratings" are tho~e values bey&nd which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual deVice 0118ratlon
Note 2 Unless otherWise specified min/max limits apply across the -55"e to +125"e temperature range for the DM7091 and
across the oOe to 70"e range for the DM8091 All typlcals are given for Vee'" 5 OV and T A'" 25°e
Note 3
1-110
V
11
CONDITIONS
Logical "1" Input Voltage
MIN
Only one output at a time should be shorted
c
3:
....,
o
Series 54/74
CD
N
.......
c
3:
CO
o
CD
N
DM7092/DM8092 dual 5-input NAND gate
general description
features
The DM7092/DM8092 IS a dual 5-input NAND
gate utilizing TTL (Transistor-Transistor Logic),
The device fills a gap In the standard 54/74 series
In that it replaces two single 8-input gates (with
tied inputs) or an assembly of smaller gates, Also
either of the two 5-input gates can be used as a
smaller gate,
•
Series 54/74 compatibility
•
No longer necessitates use of SN5430/SN7430
(eight-input-gate) for the five-Input function
•
Specifications identical to standard SN54XX/
SN74XX gate
logic and connection diagram
Dual-in-Line and Flat Package
T
14
1
13
I"
11
10
9
8
6
J~
~
2
3
S::
4
I'
rOPVIEW
1-111
N
en
o
CO
:E
Q
.......
N
en
o.....
:E
Q
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
7V
5.5V
5.5V
DM7092
DM8092
Storage Temperature Range
-55"C to +125°C
O°C to +70°C
_65°C to +150°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
300°C
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
UNITS
Logical "1" Input Voltage
Vee=45V
V ee -475V
Logical "0" Input Voltage
DM7092
DMB092
Vee = 4.5V
Vee 475V
LogIcal"," Output Voltage
DM7092
DMB092
Vee=45V
lOUT = -400I'A. Y'N = 0 BV
Vee = 4 75V
Logical "0" Output Voltage
DM7092
DMB092
Vee=45V
lOUT = 16 rnA. Y'N = 2 OV
V ee -475V
Logical "1" Input Current
DM7092
DMB092
Vee=55V
Y'N = 2 4V
Vee = 5 25V
40
I'A
DM7092
DM8092
Vee=55V
V,N =55V
Vee = 5 25V
1
rnA
Logical "0" I nput Current
DM7092
DMB092
Vee=55V
Y'N = 04V
Vee 525V
-16
rnA
Output Short CIrCUit Current
(Note 3)
DM7092
DMB092
Vee=55V
VOUT
Vee 525V
Supply Current - Logical "1"
(Each Device)
DM7092
DMB092
Vee=55V
Vee- 525V
Logical "0"
DM7092
DM8092
Vee = 5 5V
V ,N =50V
V ee -525V
20
V
OB
VIN
""
OV
24
V
04
-20
-18
= OV
V
-55
V
rnA
1
18
rnA
3
51
rnA
-15
V
Propagation Delay to a Logical "0",
tpdQ
Vee=50V, T A =25°e,e=50pF
8
15
ns
Propagation Delay to a Logical "1",
tpd1
Vee = 5 OV, T A = 25°e, e = 50 pF
13
25
ns
Vee = 5 OV.I'N = -12 rnA, TA = 25°e
Input Clamp Voltage
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electncal Charactenstlcs" prOVides conditions
for actual device operation.
Note 2: Unless otherwise speCified minImax limits apply across the -55°C to +125°C temperature
range for the DM7092 and across the O°C to 700 e range for the DM8092. All tYPleals are given for
Vce = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
1·112
MAX
DM7092
DMB092
c
3:
-.,J
o
Series 54/74
CD
W
........
c
3:
00
o
®
DM7093/DM8093 TRI-STATE quad buffer
DM7094/DM8094 TRI-STATE quad buffer
CD
W
general description
The DM7093/DM8093 and DM7094/DM8094 are
quad 2-input buffers which accept normal TTL or
DTL input levels and have outputs which provide
either normal low-impedance TTL output characteristics or a high Impedance state, One of the two
inputs to each buffer is used as a control line to
gate the output into the high impedance state, The
other input simply passes the non-inverted data
through the buffer, The DM7093/DM8093 and
DM7094/DM8094 differ only In the activating
logic state of the control input. The
DM7093/DM8093 provides the high impedance
state when a logical "1" IS applied to the control
Input; the DM7094/DM8094 operates Similarly
with a logical "0",
features
• Series 54/74 TTL and 930 DTL Compatible
• Same Pin Breakout as SN5400/SN7400 TTL
and 946 DTL
• Up to 128 Buffers can be Connected to a Common Bus- Line
3:
o
• High Capacitive Drive Capability
00
• I ndependent Control of each Buffer
This unique TRI-STATE concept allows outputs to
be tied together and then connected to a common
bus line, Normal TTL outputs cannot be connected due to the low-impedance logical "1" output current which one device would have to sink
from the other, If however on all but one of the
connected devices both the upper and lower output transistors are turned off, then the one remainIng device In the normal low impedance state will
have to supply to or sink from the other devices
only a small amount of leakage current, This is
exactly what occurs on the DM7093/DM8093 and
DM7094/DM8094,
Dual-In-Line and Flat Package
CONTROL
OUTPUT
*Invertedon DM1D9liElM80930nlv
truth tables
DM7093/DM8093
DM7094/DM8094
OUTPUT
DATA
CONTROL
OUTPUT
DATA
CONTROL
1
0
0
1
1
1
1
1
0
0
X
1
0
0
HI'Z
0
X
X:;:: Irrelevant
HI'Z
x=
~
c
• 12 ns Propagation Delay
logic and connection diagram
CONTROL
CD
........
-,Continued on following pages)
lice
c
3:
-.,J
o
Irrelevant
1-113
CD
~
0::1'
m
absolute maximum ratings
o
CIO
7V
55V
5.5V
Supply Voltage
~
C
Input Voltage
Output Voltage
Time that two bus-connected devices may be In
OPPosite low Impedance states simultaneously
(5% duty cycle)
........
0::1'
m
_65°C to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +12SoC
O°C to + 70°C
300°C
DM7093, DM7094
DM8093, DM8094
Lead Temperature (Soldering, 10 sec)
Indefinite
o
"~
C
M
0)
electrical characteristics
~
C
........
M
m
o
"~C
MIN
CONDITIONS
TVP
(NOTE 3)
Input Clamp Voltage
o
CIO
(Note 1)
PARAMETERS
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical" 1" Input Current
Logical "1" Input Current
DM7093/94
Vee "'4SV
DM8093/94
Vee "'47SV
DM7093/94
Vee =45V
DM8093/94
Vee "'47SV
DM7093/94
V cc =4SV
DM8093/94
Vcc"'47SV
DM7093/94
Vee "'55V
DMS093/94
Vee - 525V
DM7093/94
Vee = S SV
DM8093/94
V cc =S25V
T A ==2SoC,IIN=-12mA
MA
VIN=SSV
1
mA
V IN "'04V
-16
mA
Vce=55V
Logical "0" Input Current
(Data Input Only)
OM7093!94
Vec=55V
01\.18093/94
Vee'" 5 25V
DM7093/94
Vce=45V
10 = -2 0 mA
DM8093/94
V ee =475V
10=-52mA
DM7093/94
Vee'" 4 5
DM8093/94
Vee=475
DM7093/94
Vee = 5 5V
DM8093/94
Vce=525V
Supply Current
Supply Current
Output Disable Current
VCONTROL = 2 OV (DM7093!8093)
o BV (DM7094/8094)
-40
VIN "'04V
DM7093
Vce~55V
DMB093
Vce=525V
-1 6
VeoNTRoL = 0 8V (DM7093/B093)
2 OV (OM7094/B094)
24
V
10 = 16 rnA
04
V o = OV
-30
-45
-70
-28
-45
-70
1~
n
mA
Vee=55V
Vo = 2 4V
40
MA
Vce=525V
V o - 0 4V
-40
pA
Vce = OV
15
V
-15
V
"
Vee = OV
DM7093/8093
--DM7094/8094
DM7093/8093
--DM7094/8094
Vce=50V
12
23
TA = 2SoC
12
23
Vee=-50V
12
18
TA = 25°C
12
18
~
Vce=50V
5
10
DM7094(8094
T A =25°C
12
18
DM7093(8093
Vce=50V
14
24
T A = 25°C
18
29
--DM7094!8094
--DM7094/8094
Vcc=50V
14
21
T A = 2SoC
14
21
---DM7093/8093
Vee=50V
13
25
DM7094/8094
TA= 2SoC
13
25
Vee'" 5 OV and TA
='
25°C
NOTE 2, Only one output at a time should be shorted
NOTE 3_ MIN and MAX values refer to the absolute values
1-114
62
DM8093/94
NOTE l' Unless otherwise specified the min-max limits across the _55°e to +125()C temperature
range for the DM7093 & DM7094 and across the O"C to 700 e temperature range for the DM8093 &
DM8094 Ali typlcals are given for
mA
DM7093/94
DM7093(8093
1"
54
Vee=55V
10=-12mA
'0H
mA
Vee=525V
Ground Clamp
"H
V
DM8094
10 = 12mA
tpdO
MA
mA
DM7094
Vee Clamp
tpdl
V
40
Vcc=52SV
Output Short Current
(Note 2)
V
V 1N =24V
DMB093/94
Logical "0" Output Voltage
UNITS
V
08
Logical "0" I nput Current
(Control Input Only)
"1" Output Voltage
-15
20
DM7093/94
Logical
MAX
(NOTE 3)
"'
"'
"
n,"'
"
"
n,
"'
"
"
c
:s:....
general description (cont.)
o(D
A tYPical system connection IS shown In Figure 1
While true that In a TTL system open-collector gates
could be used to perform the logic function of
these TR I-STATE elements, neither waveform integrity nor optimum speed would be achieved. The
low output impedance of the DM7093/DM8093
and DM7094/DM8094 provides good capacitance
drive capability and rapid transition from the
logical "0" to logical "1" level thus assuring both
speed and waveform integrity.
It is possible to connect as many as 128 devices to
a common bus-line and still have adequate drive
capability to allow fan-out from the bus. The
example shown in Figure 2 indicates how this
guarantee can be made under worst-case conditions.
Another advantage of these buffers IS that in the
high impedance state their inputs do not present
the normal loading to the driving device. This is
significant when It is desirable to transmit in both
w
......
directions over a common line. Figure 3 illustrates
such a system. Assume one device in group A is
driving the bus-line; and the gates at B are receiving the signals. All outputs at C and D are gated
into the high-impedance state. Normally the fanout from the driving gate at A would be calculated
at 4-2 from Band 2 from D, plus additional slight
loading from those outputs in the high impedance
state. But since the logical "0" Input current on
D's inputs deliver only 40 flA when these devices
are gated into the high impedance state, the loading is significantly reduced. It's true that the logical "1" fan-out remains the same (40 flA times the
number of inputs and high-impedance-state outputs). However since the logical "1" fan-out capability of these tri-state devices is 130 while the
logical "0" fan-out capability is only 10, it is
obvious that the logical "0" fan-out is the limiting
item and that a significant Increase in the number
of inputs which can be tied to the bus-line can be
achieved by reducing the number of ~1.6 mA logical "0" loads.
c
:s:
CO
o(D
w
c
:s:....
o
(D
~
......
c
:s:
CO
o
(D
~
STANOARDTH
DR
DTLCIACUITS
120mA fOR DRIVING OTHER
TTL INPUTS
SElECTED AS
lOWIMHOANCE
DEVICE
GATED INTO
HI IMPEDANCE
STATE
CONTROL =
HIGH IMPEDANCE OUTPUT
GATED INTO
IlllMHOilNCE
STATE
I----j="l~~
I---F=t~~
CONTROL =
HIGH IMPEDANCE OUTPUT
FIGURE 2
FIGURE 1
FIGURE 3
1-115
1'00
0')0')
00
0000
Series 54/74
:!:!
cc
................
1'00
00
1'1'
DM7095/DM8095,DM7097/DM8097 TRI-STATE® hex buffers
DM7096/DM8096,DM7098/DM8098 TRI-STATE hex inverters
CC
general description
LOU)
Each of the devices descrl bed herein are used to
convert standard TTL or DTL outputs to TRISTATE outputs. The DM7095/DM8095 and the
DM7097/DM8097 do so with no logic inversion; the
DM7096/DM8096 and DM7098/DM8098 provide
the logical opposite of the input signal. The
DM7095/DM8095 and DM7096/DM8096 control
all SIX devices from common' Inputs; the
DM7097/DM8097 and DM7098/DM8098 control
0')0')
:!:!
0')0')
00
0000
:!:!
cc
................
LOU)
0')0')
00
1'1'
:!:!
CC
connection diagrams
four devices from one input and two from another
Input.
features
•
Maximum package utilization
•
Typical power dissipation
DM7095/DM8095, DM7097/DM8097 325 mW
DM7096/DM8096, DM7098/DM8098 295 mW
15 ns
TYPical propagation delay
•
(Oual·ln-Llne and Flat Packages)
OM7095iOM8095
Vcc
DIS,
DIS,
IN.
OUT.
IN,
OUT,
IN,
DUl,
INI
OUT,
IN,
OM7096iOM8096
IN,
OUT.
Vcc
01$,
IN"
OUT,
[JIS,
IN,
QUT,
IN~
1I0c
OIS,
IN"
OU1,
OUL,
IN,
II'<,
OUT,
our,
TOPVIEW
OM7097 iOM8097
OM7098iOM8098
Vcc
DIS,
IN.
OUl s
IN,
OUT.
IN,
DIS 4
IN,
OUT,
IN,
aUT,
IN,
OUT,
OUT.
DIS,
Ir.!.
OUT,
IN,
OU1;
IN,
OUT,
IN,
OUT,
IN,
OUT,
TOPVIEW
truth tables
OM7095iOM8095
OM7096iOM8096
DISABLE
DIS,
INPUT
015 2
INPUT
OUTPUT
0
0
0
1
1
0
0
1
0
1
0
1
X
X
X
0
1
H·,
H·,
H,
DISABLE
DlS1
INPUT
0
0
0
1
1
0
0
1
0
1
OM7097 iOM8097
DISABLE
1-116
DIS 4
INPUT
015 2
INPUT
0
0
X
1
0
0
1
X
0
1
X
X
015 2
INPUT
OUTPUT
0
1
X
X
X
1
0
H·,
H·,
H·,
OM7098iOM8098
OUTPUT
0
1
H.,
H·z .....
"Output 5-6 only
.. "Output '-4 only
X;o Irrelevant
DISABLE
015 4
INPUT
0
0
X
1
0
0
1
015 2
X
INPUT
0
1
X
X
OUTPUT
1
0
H-z"
H-z"'''
OUT,
00
absolute maximum rati ngs (Note
S:S:
operating conditions
1)
Supply Voltage
Input Voltage
Output Voltage
7V
5.5V
5.5V
_65 0 C to +150° C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)
Time that 2 bus-connected devices may be in opposite
Indefinite
low-Impedance states simultaneously . . .
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
""
00
CD CD
0)CJ1
Supply Voltage IV ccl
DM7095/617IS
DMS095/617IS
Temperature IT AI
DM7095/617!S
DMS095/617IS
-55
0
..............
00
S:S:
0000
00
'c
'c
+125
70
CD CD
.
0)CJ1
electrical characteristicsl(Note 2)
00
CONDITIONS
PARAMETER
Logical "1" Input Voltage
Vee"" Mm
Logical "0" Input Voltage
Vcc=Mm
TA ~ 25'C
10
10
~
~
-2.0 rnA
-52 mA
Logical "1" Output Current
Logical "0" Output Voltage
Vee = MIn
10
~
32 mA
Third State Input Current
Vee
V IN ~ 0 5V
DIS = 2 OV
Third State Output Current
Vee::: Max
Logical "1" Input Current
Logical "0" Input Current
OM 7095/6/7/S
DMS095/617IS
Output Short CirCUit Current
INote 31
Supply Current
(each deVice}
DM709517
DMS09517
DM7096/S
DMS096/S
Vee
MAX
20
OS
= Mm
Logical "1" Output Voltage
TYP
MIN
,
~
UNITS
S:S:
V
00
-40
flA
00"
Vo = 24V
Vo = 04V
40
-40
flA
flA
Vee::: Max
V'N " 24V
V'N = 5 5V
40
1
pA
mA
Vee::: Max
V ,N = 04V
DIS = 04V
-1 6
mA
Vee::: Max
Vo = OV
=;
Max
04
CD CD
-40
-SO
-115
65
85
59
77
mA
mA
Vee = Max
-I 5
V
I 5
V
-I 5
V
14
22
ns
10
16
ns
10
16
ns
\ 11
17
ns
Vee = 5 OV
T A ~ 25°C
6
11
ns
Vce=50V
T A ~ 25°C
16
27
ns
Delay from Disable Input to Logical 1/1"
Level (from High Impedance State), tH1
Vee=50V
T A ~ 25°C
21
35
ns
Delay from Disable I nput to Logical "a"
Level (from High Impedance State), tHO
Vee
24
37
ns
Vee
Vee = OV
Output Ground Clamp Voltage
Vec
Input to Output, tpd1
=
~
Mm
OV
DM709517
DMS09517
DM7096/S
DMS096/S
Vee = 5 OV
TA = 25 c C
DM709517
DMS09517
DM7096/8
DMS096/S
Vee = 5 OV
T A = 25'c
Delay from Disable Input to High
Impedance State (from Logical //1/1
Levell, t1H
Delay from Disable Input to High
Impedance State (from Logical "0//
Level), tOH
S:S:
0000
00
Input Clamp Voltage
Propagation Delay to a
Logical "1// from Data
00
V
24
V
Output Vee Clamp Voltage
Propagation Delay to a
Logical "0" from Data
Input to Output, tpdO
""
CD CD
00"
..............
V
liN = -12 mA
10=12mA
loc-12mA
i
\
~
5 OV
TA~25°C
Note 1 "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electncal Characteristics" prOVides conditions for actual deVice operation
Note 2. Unless otherWise specified min/max limits apply across the _55°e to +125°e temperature range for the
OM7095/6/7/8 and across the oOe to 70 G e range for the DM8095/6/7/8 All tYPlcals are given for Vee'" 5 OV and T A '"
25"C
Note 3. Only one output at a time should be shorted
1·117
...
...eo
N
Series 54/74
~
Q
...
...
,....
"-
DM71211DM8121 TRI-STATE ® eight channel digital multiplexer
N
general description
~
Q
The DM7121/DM8121 multiplexes digital signals
from eight Imes to one Ime. Two outputs provide
either true or complement Information. Three
select lines determine which of the eight Input
lines are routed to the output. A strobe Input is
provided which when taken to the logical "1"
state overrides all other Inputs and places the
outputs In a defined state.
This unique state turns off both upper and lower
output transistors thus presenting a high Impedance
state and allOWing numerous outputs to be connected to a common bus-line. Only one device at a
time may be In the normal output state when
connected In th IS manner. The logical "0" state on
the strobe Ime was selected as the level which
places the device In the normal output state, because the logical "0" state IS usually the unique
state which occurs on such devices as the SN5442/
SN7442 and SN54154/SN74154 decoders
features
•
•
•
•
•
•
Performs parallel-to-serial conversion
Pin compatible with SN54151/SN74151
Strobe over-ride
15 ns tYPical propagation delay
150 mW typical power dissipation
Outputs can be connected to a common bus-line
logic diagram
GUl1'UT
DISABLE
DATA
INPUTS
{
'
DATA
SELECT
•
(IIN"Rr~
c
connection diagram
Dual~1 n-Line
truth table
and Flat Package
OUTPUTS
C
B
A
STROBE
DO
01
x
00
,
0
o ,
0
,
0
0,
OATAtNPUTS
1·118
OUTPUTS
0
03
04
Os
06
07
x
x
X
x
x
x
x
x
x
x
x
x
x
o
,
00
o ,
02
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
HI Z
H,Z
o
absolute maximum ratings
!:
.........
(Note 1)
....
II.)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM7121
DM8121
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
electrical characteristics
7V
"'-
o
5.5\/
5.5V
!:
-55°C to +125°e
oOe to 70°C
-65°C to +150o e
300°C
....
....
00
II.)
INote 21
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" I nput Voltage
DM7121
DM8121
Vee=45V
Vee 475V
Logical "0" Input Voltage
DM7121
DM8121
Vee=45V
Vee - 4-75V
Logical" 1" Output Voltage
DM7121
Vee=45V
r,.;---DM8181 Vee = 4 75V
lOUT
lOUT
Logical "0 'Output Voltage
DM7121 ~c=4~
DM8121
V ee =475V
lOUT"" 16 rnA
Logical "1 ' Input Current
DM7121
--DM8121
VIN=24V
40
MA
VIN '" 5 5V
1
mA
-16
mA
r-.;~---
Vee=525V
DM7121
DM8121
Vcc=55V
DM7121
~ee=~
Logical "0" Input Current
DM8121
Output Short Circuit Current
DM7121
DM8121
INote 31
Vcc=55V
V ee -525V
Vec=525V
2
08
=
=
-2 mA
-5 2 mA
24
V ,N =04V
-20
-18
V ee -525V
Supply Current
DM7121
DM8121
Input Clamp Vcltage
DM7121
Vcc=45V
-,-,'--DM8121 Vee=475V
TA
Output Vee Clamp Voltage
DM7121
DM8121
10= ±12 mA, TA
=
5 5V
31
V ec -525V
Vee=55V
Vee - 5 25V
=
25°C, liN
=
V
-55
-55
mA
51
mA
-12 mA
-15
V
25°C
Vee + 1 5
V
-15
V
=
DM7121
Output Ground Clamp Voltage
DM8121
Vee = 5 5V
Vee - 5 25V
10 = -12 mA, TA = 25°C
DM7121
DM8121
Vee = 5 5V
V ee -525V
V o =24Vor04V
Third State Output Current
V
V
04
Vcc=55V
Vee
V
-40
40
MA
Propagation Delay Time to
Logical" 1" from A,B,C or 0
Vee = 5 OV, CL = 15 pF, RL = 40011
18
36
ns
Propagation Delay Time to
Logical "0" from A,B,C or 0
Vee = 5 OV, CL = 15 pF, RL = 40011
21
33
ns
Propagation Delay Time to
Logical "1" from Strobe
Vee = 5 OV, CL = 15 pF, RL = 40011
17
30
ns
Propagation Delay Time to
Vee = 50V, CL = 15 pF, RL =40011
18
27
ns
Logical "0" from Strobe
25°C
W Output
to Y Output
4
4
8
8
ns
Vee=50V
T A = 25"C
W Output
to Y Output
15
14
30
28
ns
Level
Veeo 5OV
T A = 25°C
W Output
to Y Output
15
15
30
30
ns
Delay from Strobe to Logical "0" Level
Veeo 5OV
TA=25"C
to W Output
Y Output
19
18
38
Delay from Strobe to High Impedance
State (from Logical "1" Level), tlH
Delay from Strobe to High Impedance
State (from Logical "0" Level), tOH
Delay from Strobe to Logical "1
II
(from High Impedance State), tHl
(from High Impedance State), tHO
Vee ° 5 OV
TA
""
36
ns
Note 1 "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electrical Charactemtlcs" provides conditions
for actual device operation
Note 2 Unless otherWise specified min /max limits apply across the -55 C to +125°C temperature
range for the OM7121 and across the DoC to 70°C range for the OM8121 All typlcals are given for
Vee'" 50V and TA '" 25°C
Q
Note3
Only one output at a time should be shorted
1-119
Series 54/74
DM7123/DM8123 TRI-STATE ®
quad 2-input multiplexer
general description
The DM7123/DM8123 consists of four 2-lnput
multiplexers with common input select logic and
common output disable circuitry. It allows two
groups of four bits each to be multiplexed to four
parallel outputs. When the Enable Input IS at the
logical "0" level the outputs are conventional TTL.
However, when a logical "1" is applied, the outputs
assume a high"mpedance state. Both upper and
lower output transistors are turned off and the
resulting condition allows many devices to be
connected to a common bus line without loading
down or being loaded down by other devices on
the line.
The DM7123/DM8123 is pin compatible and func·
tlonally compatible with the FSC 9322 and the
SN54157/SN74157 except for the TRI·STATE
capability.
features
•
Typically 10 ns from data to output
•
Power dissipation 200 mW typ
•
TRI-STATE outputs
•
Pin compatible with FSC 9322 and SN54157/
SI\174157
•
Diode clamped inputs
logic diagram
h,
100
11
10
z,
connection diagram
11C
13
z,
z,
truth table
Dual-In-Line and Flat Package
ENABLE
SELECT
1
X
0
1
1
0
0
0
0
0
TOP VIEW
1-120
INPUT
10
X
"
X
OUTPUT
HI-Z$tate
X
0
X
1
1
0
1
X
0
1
X
0
c
absolute maximum ratings
........3:
(Note 1)
N
W
7V
5.5V
5.5V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM7123
DM8123
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
~
3:
...
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
300°C
electrical characteristics
CO
N
W
(Note 2)
PARAMETER
CONDITIONS
Log.cal "I" Input Voltage
DM7123
DM8123
Vee = 4.5V
Vee - 4.75V
Log.cal "0" Input Voltage
DM7123
DM8123
Vee = 4.5V
Vee - 4.75V
Log.cal "I" Output Voltage
DM7123
DM8123
Vee = 4.5V
Vee=475V
lOUT = -20 mA, V. N = 2V
lOUT = -52 mA, V. N = 2V
Log.cal "0" Output Voltage
DM7123
DM8123
Vee = 4.5V
Vee - 4.75V
lOUT
Third State Output Current
DM7123
DM8123
Vee=55V
Vee - 525V
Logical "'" Input Current
DM7123
DM8123
Vee = 5.5V
V ee -525V
DM7123
DM8123
MIN
TYP
MAX
V
2.0
.8
V OLH ~ 2.4V
V. N (Enable) = 2V
V
V
2.4
= 16 mA, V. N = 8V
0.40~
UNITS
.4
40
IlA
V. N = 2 4V
40
IlA
Vee = 5.5V
V ee -525V
V. N = 5.5V
1
mA
DM7123
DM8123
Vee = 5.5V
Vee = 5.25V
V. N = O.4V
-16
mA
DM7123
DM8123
Vee=55V
Vee - 5 25V
V. N = 4.5V
-50
-70
mA
Supply Current
DM7123
DM8123
Vee=55V
Vee 525V
V. N (Enable) = 4 5V
Other Inputs OV
40
51
mA
Input Clamp Voltage
DM7123
DM8123
Vee = 5.0V
TA - 25 C
I. N = -12 mA
-10
-15
V
Log.cal "0" I nput Current
Output Short Circuit Current
(Note 3)
-40
V
-1.0
-30
Vee = 5 OV
TA = 25°C
5
11
18
ns
Propagat.on Delay to a Log.cal "0" from
Select to ZA, tpdO
Vee = 5 OV
TA = 25°C
8
17
24
ns
Propagation Delay to a Log.cal "I" from
Data to Output, tpd'
Vee = 5.0V
T A = 25°C
4
8
15
ns
Propagat.on Delay to a Log.cal "I" from
Select to ZA, tpd'
Vee= 50V
T A = 25°C
5
15
23
ns
Delay from D.sable to H.gh Impedance
State (from Log.cal "I" Level), t.H
Vee= 50V
T A = 25°C
4
7
11
ns
Delay from D.sable to H.gh Impedance
State (from Log.cal "0" Level), tOH
Vee=50V
TA = 25°C
9
19
27
ns
Delay from D.sable to Log.cal "I" Level
(from H.gh Impedance State), tH'
Vee = 5.0V
TA = 25°C
9
18
25
ns
Delay from D.sable to Log.cal "0" Level
(from H.gh Impedance State), tHO
Vee = 5.0V
TA = 25°C
10
23
30
ns
Propagation Delay to a Logical "0" from
Data to Output, tpdO
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVICes should be operated at these limits The table of "Electncal Characteristics" provides conditions
for actual deVice operation
Note 2: Unless otherwise specified mm/max limits apply across the _55°C to +12SoC temperature
range for the DM7123 and across the o"e to 70"e range for the DM8123 All typlcals are gIVen for
Vee::: S OV and TA ::: 2S"e
Note 3: Only one output at a time should be shorted
1·121
Series 54/74
DM7130/DM8130 10 -bit comparator
DM7160/DM8160 6-bit comparator
o
....
M
00
~
C
.......
o
M
....
I"
~
general decription
features
The DM7130/DM8130and DM7160/DM8160comparators determine equality or non-equality between two binary words. The DM7130/DM8130
compares two ten-bit words while the DM7160/
DM8160 compares two six-bit words. A strobe
over-ride is provided on both devices which when
taken to a logical "1" will force the output to a
logical "1".
•
Series 54/74 compatible
•
20 ns typical compare delay
•
TYPical power dissipation
DM7130/DM8130
DM7160/DM8160
•
Open collector outputs for expandabillty
C
logic and connection diagrams
Dual-In-Line and Flat Package
Dual-I n-Line and Flat Package
DM713DiDM813D
DM716DiDM816D
truth table
CONDITION
STROBE
S
Z
1
0
0
1
1
0
A=B.A*B
A=B
A*B
For DM7130/DM8130:
IA) = A9 - - - - - - Ao
IB) = B9 - - Bo
z = s + [Xo . X, . X2
•
X3 • X4
•
X3 . X4
•
Xs . X6 . X7 · Xs' Xg J
For DM7160/DM8160
IA) = As IB) = B5
- Ao
- - - Bo
z = s + [Xo . X, . X2
• X5
J
where
Xo
1·122
=
240mW
205 mW
Ao Bo + Ao Bo. X,
=
A, B, + A, B,
c
absolute maximum ratings
3:
...'"
o
(Note 1)
W
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM8130, DM8160
DM 7130, DM 7160
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
.....
c
7V
5.5V
5.5V
oOe to 70°C
_55°C to +125°e
-65°C to +150o e
300°C
3:
...
CO
W
o
c
...'"3:
C'l
electrical characteristics
(Note 2)
PARAMETER
c
CONOITIONS
MIN
TYP
MAX
OM7130.DM7160
DM8130.DMB160
Vee = 4 5V
Vee - 4 75V
Logical "0" Input Voltage
DM7130.DM7160
DM8130,DM8160
Vee=45V
Vee - 4 75V
Logical "1" Output Current
DM7130.DM7160
DM8130.DM8160
Vee=55V
V ee -52SV
V OUT
=:
Logical "0" Output Voltage
DM7130.DM7160
DM8130,DM8160
Vee = 4 5V
Vee - 4.75V
tOL =
16 rnA
Logical "1" Input Current
DM7130/DM7160
DM8130,DM8160
Vee = 5 5V
V ee -52SV
V'N=24V
40
JJ.A
DM7130,DM7160
DM8130,DM8160
Vee=55V
Vee S 25V
V IN =55V
1
mA
Logical "0" I nput Current
DM7130,DM7160
DM8130.DM8160
Vee = 5 SV
V ee -525V
Y,N = 04V
-16
mA
Supply Current
DM7130.DM7160
DM8130,DM8160
Vee = 5 5V
Vee 525V
48
70
mA
DM7130,DM7160
DMB130,DM8160
Vee = 5 5V
Vee- 525V
41
60
mA
DM7130,DM7160
DM8130.DM8160
Vee = 4 5V
Vee- 47SV
Propagation Delay to a loglcat "0" from Strobe
Vee= 50V
to Output, tpdO
T A = 25°C
Propagation Delay to a Logical "1" from Strobe
to Output,
tpdl
Propagation Delay to a Logical "0" from Data
to Output,
tpdO
Propagation Delay to a Logical "1" from Data
to Output, tpdl
3:
UNITS
Logical "1" Input Voltage
Input Clamp Voltage
I
o
.....
...
CO
V
2
C'l
OB
5 5V
100
02
liN = -12 mA, TA = 2Soe
See ac test
04
o
V
JJ.A
D
V
-1 5
V
ClfCUlt
20
30
ns
Vee = 5 OV
TA = 2Soe
See ac test circuit
9
18
ns
Vee = 50V
TA = 25°C
See ac test
Clfeu It
27
40
ns
Vee = 50V
T A =25°e
See ac test
ClfCUIt
15
25
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits The table of "Electrical Characteristics" provides conditions
for actual deVice operation
Note 2: Unless otherWise speCified min/max limits apply across the -55°C to +125°C temperature
range for the DM7130 and DM7160and across theO°Cto 7Qoe range for the DM8130and DM8160
All typleals are given for Vec = 5 OV and T A = 25°C.
1·123
CD
M
...
Series 54/74
CO
:E
c
.......
CD
M
.........
6-bit unified bus comparator
DM7131/DM8131. DM7136/DM8136
:E
c
...
...
general description
M
The DM7131/DM8131, DM7136/DM8136 compare two binary words of two-to-Slx-blts In
length and indicates matching bit-for-bit of the
two words. I nputs for one word are 54/7 4 seriescompatible TTL inputs, whereas those of the
second word are high impedance receivers driven
by a term inated data bus. These bus inputs include 1V typical hysteresis which provides 1.8V
noise immunity. The DM7131/DM8131 has active
pull up output and goes to the 10';" state upon
comparison. The DM7136/DM8136 has opencollector output which goes to high state upon
comparison and is expandable to n bits by collector-ORing. Both devices have an output latch
which is strobe controlled.
CO
:E
c
...
.......
.........
M
:E
c
The transfer of information to the output occurs
when the STROBE input goes from a logic "1"
to logic "0" state. Inputs may be changed while
the STROB E is at the logic "1" level without
affecting the state of output. These devices are
useful as address comparators In computer systems
utilizing unified data bus organization.
features
15 J.1A typ
•
Low bus input current
•
High bus input noise immunity
•
High fan out
1.8V typ
•
Input clamping diodes
•
Output compatible with TTL circuits
•
Output latch provision
logic and connection diagrams
T1
o--!>o--L,
Bl~
T2
o---t:>o--y
Dual-In-Line and Flat Package
82~
Tl
o---t:>o--y
B3~
14
o--!>o--L,
84~
T5
o---t:>o--y
B5~
TO
o---t:>o--y
Bfi~
R = HIGH IMPEDANCE
BUS RECEIVER
1-124
IBUS INPUT) 81
1
16 Vee
(TTL INPUT) T1
2
1566
•
1385
OUTPUT
(DM1131l
T2
OUTPUT
(DM713S)
B3 5
12 T5
11B4
STROBE
7
1014
OND 8
9 OUTPUT
TOPVIEW
c
s:-..J
operating conditions
absolute maximum ratings
.....
.....
W
;>
Supply Voltage
TTL and Strobe Input Voltage
Fan Out
Storage Temperature Range
7V
5.5V
10
_65°C to +150°C
Supply Voltage
DM7131.DM7136
DM8131,DM8136
TYP
MAX
UNITS
4.5
475
5
5
5.5
5.25
V
V
-55
0
+25
+25
PARAMETER
MIN
CONDITIONS
TYP
MAX
Vee = Min
Bus Input "1" Threshold Voltage
DM7131,DM7136
DM8131,DM8136
165
180
225
225
265
250
DM7131,DM7136
DM8131,DM8136
097
105
13
13
163
155
Vee
TA
=
°c
°c
V
Input "0" Voltage (Except Bus Inputs)
Input Clamp Diode Voltage----
.....
=
UNITS
20
Vee'" Min
V
08
-15
Max, liN = -12 mA
I'
V
V
V
V
V
+25 c C
TTL Input "1" Current
Vee'" Max, VIN = 2 4V
V IN = 5 5V
40
1
pA
mA
TTL Input "0" Current
Vee = Max, VIN = 0 4V
-16
mA
Strobe Input "1" Current
Vee'" Max, VIN = 2 4V
V 1N =55V
80
2
pA
mA
Strobe Input "0" Current
Vcc=Max, V 1N =04V
-24
mA
Maximum Bus Input Current
Vee = Max, VIN = 4V
50
50
pA
pA
15
1
Vee'" OV, VIN = 4V
Logic "0" Output Voltage
Vce=Mm,louT=16mA
Logic "1" Output Voltage
Vee=Mm, IOUT""-400}lA
04
DM7131
V
V
24
DM8131
Logic "1" Output Current
Vee = Max, V OUT '" 5V
DM7136
DM8136
Output Short CirCUit Current
Vee = Max, VOUT '" OV
OM7131
OM8131
Power Supply Current
Vee"" Max
50
TTL Input to Output, tpd1
V ce =5V,T A =25°C
20
TTL Input to Output, tpdO
Vee ='~V, T A = 25°C
20
Bus Input to Output, tpd1
Vee'" 5V, T A
25"C
30
-20
-18
250
pA
-55
-55
74
mA
mA
mA
Propagation Delays
".=
Bus I nput to Output, tpdO
V ee =5V,T A =25°C
30
Strobe Input to Output, tpdl
V ec =5V,T A =25°C
20
Strobe I nput to Output, tpdO
V ee =5V,T A =25°C
20
s:00
.....
(Operating Temperature Range - Unless Otherwise Specified)
Input "1" Voltage (Except Bus Inputs)
Bus Input "0" Threshold Voltage
+125
+70
.......
C
W
Temperature (T AJ
DM7131,DM7136
DM8131,DM8136
electrical cha racteristics
MIN
n,
n,
n,
n,
n,
n,
1·125
o
o
;
~S
Series 54/74
Q
.......
o
o
~
OM7200/0M8200 4-bit comparator
Q
general description
features
The DM7200/DM8200 is a monolithic TTL
(Transistor-Transistor Logic) circuit which is used
to compare the numerical values of two four-bit
binary numbers_ Outputs indicate (1) whether
number A is greater than number B. (2) whether
number B is greater than number A. or (3) whether
the two numbers are equal. A strobe input overrides all other Inputs and places the outputs in a
definite state. The design chosen provides maximum speed with minimum circuit complexity.
Nu merical comparisons of words longer than four
bits may be made by using additional DM7200!
DM8200's only.
•
Series 54/74 Compatible
•
TYPical Noise Immunity
•
Guaranteed Noise Immunity
:E
lV
400mV
•
TYPical Propagation Delay
20 ns
•
Typical Power Dissipation
175mW
applications
•
Digital stepping-motor control applications
•
Convergence applications
•
Summing junction for digital servo systems
logic and connection diagram (Dual-In-Llne and Flat Package)
A,lsth,mOlt Slgniliunt bll of A
'.Icc
A,
A]
Bo
B,
B,
A,
Ne
B,
GNO
logic table
Input
Number A4 A3 A,A,
A
A
A
A
1-126
>
<
~
""
Output
Number B4 B3 B,B,
Strobe
X
Y
B
0
1
0
1
B
0
0
B
0
1
1
B
1
0
0
o
i:
absolute maximum ratings
Supply Voltage
"""
N
7V
Input Voltage
Operating Temperature Range
<:)
<:)
DM7200
5.5V
_55°C to +125°C
......
DM8200
O°C to +70°C
_65°C to +150°C
s:00
300°C
N
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o
<:)
<:)
electrical characteristiCS(Note
PARAMETER
1)
CONDITIONS
Logical "1" Input Voltage
Logical "0" I nput Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
Logical "1" Input Current
Logical "0" I nput Current
Logical "1" Input Current
Output Short CirCUit
Current (Note 2)
Supply Current
DM7200
Vee=45V
DM8200
V ee =4.75V
DM7200
Vee = 4.5V
DM8200
Vee'" 4.75V
DM7200
Vee = 4.5V
DM8200
Vee'" 4.75V
DM7200
Vee "'·4.5V
DM8200
Vee = 4.75V
DM7200
Vee = 5.5V
DM8200
Vee=525V
DM7200
Vce=55V
DM8200
Vee = 5 25V
MIN
TYP
MAX
V
2.0
.8
IOUT"'-400/.LA
24
.4
lOUT'" 16 mA
80
/.LA
V IN
'"
0.4V
-3.2
mA
V IN
'"
5 5V
1
mA
Vee = 5.5V
Vee=525V
DM7200
Vee'" 5.5V
-20
-55
DM8200
V ee "'525V
-18
-55
Vee" 5.5V
V ee "'525V
Propagation Delay to a
Logical" 1" from Any Data
I nput to Output
t pd '
Vee = 5.0V
T A = 25°C
Propagation Delay to a
Logical "0" from Any Data
tpd 0
I nput to Output
T A = 25°C
Propagation Delay to a
Logical" 1" from Strobe
tpd
I nput to Output
1
T A'" 25°C
Propagation Delay to a
Logical "0" from Strobe
tpd
I nput to Output
0
T A'" 25°C
Vee = 5.0V
Vee'" 5.0V
Vee'" 5 OV
Time Prior to Removal of
Strobe that Data Inputs
Must Be Stabilized I tSET UP
Time After Activation of
Strobe that Data Inputs
Must be Held, tHOLD
V
V IN = 2.4V
DM8200
DM8200
V
V
DM7200
DM7200
UNITS
Vee'" 5.0V
mA
35
53
mA
24
40
ns
17
30
ns
15
27
ns
a
18
ns
0
10
ns
-10
0
ns
T A " 25Q C
Vee'" 5.0V
TA '" 25 Q C
Note 1; Unless otherwise specified, limits shown apply from _55°C to +1 25°C for the OM7200 and
aOc
to +70 oC for the DM8200 TYPical values apply to supply voltages of 5 OV
Note 2: Only one output should be shorted at a time
1-127
o
....
....
N
00
Series 54/74
~
o
.......
....
....
N
,....
~
o.
o....
N
00
~
o
.......
o
....
N
,....
~
o
DM7210/DM8210 8-channel digital switch
DM7211/0M8211 8-channel digital switch
general description
eight bits of parallel Information are applied to the
Inputs, and If the binary numbers 000 through 111
are sequenced on the select lines, the output will
provide a serial presentation of the Input bits.
The DM7210/DM8210 and DM7211/DM8211 are
digital bipolar .Integrated circuits emploYing TTL,
used to multiplex eight INPUT channels to a single
OUTPUT Depending upon the 3·blt binary num·
ber applied to the SELECT lines, the digital bit on
the unique I NPUT selected appears on the output
features
•
The DM7211/DM8211 prOVides a strobe Input
which when taken to a logical "1" level places
the output In the logical "1" state
The cirCUit can also be used to convert parallel
Input information to serial output information. If
TTL Circuitry
•
Input Clamping Diodes
•
1 Volt Typical Noise Immunity
•
400 m V Guaranteed Noise Immunity
•
Completely compatible with Senes 54/74 circuits
connection diagrams
Dual·ln·Line and Flat Package.
INPUT
INPUT
INPUT
1
6
5
INPUT
INPUT
1
INPUT
2
Vee
o
INPUT
STROBE* OUTPUT
INPUT
J
NC
GND
*A Loou;al1 on the strobe mput causes the output to go the Logical 1 state
A Logical 0 on the strobe mput allows information to be routed through the device.
Vee
L.
A
13
INPUT1
INPUTI
I"I
12
INPUTS
1,0
I
INPUT4
19
'--
OUTPUT
•
'--
-
SELECTION
INPUTS
OUTPUT
DATA INPUTS
I1II
I
2
3
INPUT 0
1·128
14
INPUT 1
15
INPUTZ
16
INPUT 3
r
GNO
c
3:
.....
absolute maximum ratings
N
...a
o
c
3:
7V
5.5V
10
-65°C to +150°C
_55°C to +125°C
DoC to +70°C
300°C
Supply Voltage
Input Voltage
Fanout
Storage Temperature Range
Operating Temperature Range
DM7210, DM7211
DM821O, DM8211
Lead Temperature (soldering, 10 sec)
.......
00
N
...a
o
c
electrical characteristics
3:
.....
(Note 1)
CONDITION
PARAMETER
MIN TYP MAX
UNITS
N
...a
...a
.......
C
DM7210,DM7211
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical" 1" Output Voltage
Logical "0" Output Voltage
Vee" 4 5V
DM8210,DM8211
Vce"475V
DM721O,DM7211
Vee" 4 5V
DM8210, DM8211
Vce "4 75V
DM7210,DM7211
V ee "45V
DM8210,DM8211
Vee"475V
DM7210,DM7211
Vee" 4 5V
DM8210,DM8211
Vee"475V
Logical" 1" I nput Current
DM7210,DM7211
Vee "55V
IAII Inputs)
DM8210,DM8211
V ee "525V
Logical "1" Input Current
IAII Inputs!
DM7210,DM7211
Vee"55V
DM821O,DM8211
V ee "525V
Logical "0" I nput Current
DM721O,DM7211
Vee" 5 5V
IAII Inputs!
DM8210,DM8211
V ce "525V
I nput Clamp Diode
IAII Inputs!
DM7210,DM7211
Vee" 5 5V
DM821O,DM8211
Vee" 525V
DM721 0, DM7211
Vee"55V
DM821O, DM8211
Vee" 5 25V
Output Short Circuit Current
Power Supply Current
IAII Inputs GND)
DM721O,DM7211
Vee" 55V
DM8210,DM8211
V ee -525V
Propagation Delay to a Logical "0"
From Data Input to Output, tpdO
Propagation Delay to a Logical "0"
From Strobe I nput to Output
Propagation Delay to a Logical" 1"
From Data I nput to Output,
tpd 1
Propagation Delay to a Logical" 1"
From Strobe Input to Output
Data Selection Settling Time From
0-+ 1 TranSitIOn on A, B, C It s l)
Data SelectIOn Settling Time From
1---»0 Transition on A, B, C (tsO)
20
V
08
lou T " -400 IlA
24
00
N
....
....
V
V
04
lOUT" 16 mA
V ,N "24V
40
V ,N "55V
1
V
Il A
mA
V ,N "04V
-1 0 -16
mA
liN" -12 mA, TA "25°C
-1 0 -1.5
V
V OUT "0
3:
-20
-55
mA
-18
20
33
mA
Vee" 5 OV, T A " 25°C
10
21
30
ns
Vee" 5 OV, T A " 25°C
10
19
27
ns
Vee" 5 OV, T A " 25°C
10
23
32
ns
Vee" 5 OV, T A "25°C
10
21
30
ns
Vee" 5 OV, T A " 25°C
15
31
43
ns
Vee" 5 OV, T A "25°C
15
31
42
ns
Note 1 Unless otherWise speCified the min-max limits apply across the _55°C to +125°C temperature
range for the DM7210 and DM7211 and across the O°C to 70 0 temperature range for the OM8210
and DM8211 Typlcals are given for Vee = 5 OV and 25°C
e
1-129
u
....
....
N
;
logic table
C
.......
....
....
N
SELECTION INPUTS
r-.
~
C
STROBE
DATA INPUTS
3
4
5
6
7
x
x
x
x
x
x
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
0
1
X
X
x
0
x
x
x
x
x
0
1
X
X
X
X
X
1
X
X
0
X
X
X
X
X
X
0
1
X
X
x
0
x
x
x
0
1
X
X
X
1
X
X
0
X
X
0
1
X
X
x
0
x
C
B
A
IDM 7211/DM8211
ONLY)
0
1
2
o
....
0
0
0
0
0
0
0
0
0
x
1
X
co
0
0
0
0
1
1
0
0
X
X
0
c
0
0
1
1
0
0
0
0
x
x
X
o
....
0
0
1
1
1
1
0
0
X
X
X
X
1
1
0
0
0
0
0
0
x
x
x
x
x
x
X
1
1
0
0
1
1
0
0
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
X
1
X
1
1
1
1
1
1
1
0
0
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
1
1
X
X
X
1
X
X
X
X
X
X
X
X
1
N
~
.......
N
r-.
~
C
x
OUTPUT
0
1
1
-
1
0
x = "Don't Care" Condition
typical application
ONE OF SIXTEEN CHANNEL
DIGITAL DATA MULTIPLEXER
15 14 13 12 11 10
CLOCK
9
8
7
6 5
OM7533/0M8533
OR
DM7563/0M8563
4
DM7210/
OM8210
OUTPUT
OUTPUT
I
I
I
I
I
I
I
L ____________ J
1·130
3
OUTPUT
2
1 0
Series 54/74
®
DM7214/DM8214 TRI-STATE dual 4:1 multiplexer
general description
The DM7214/DM8214 IS a TRI-STATE dual fourItne to one-line multiplexer. The device acts as a
double-pole four·throw sWitch. One data Itne IS
selected from each of two four-Itne Inputs. Two
SELECT lines determine which of the four tnputs
IS chosen, however the same input of both four-Itne
selections Will be selected. TRI-STATE logic allows
for the added feature that the outputs of the device can be tied to outputs of similar devices and
connected to a common bus-line. Nomtnal TTL
outputs cannot be connected due to the lowImpedance logical "1" output current which one
device would have to sink from the other. If,
however, on all but one of the connected deVices
both the upper and lower output tranSistors are
turned off, then the one rematning deVice In the
normal lOW-Impedance state Will have to supply to
or Sink from the other deVices only a small amount
of leakage current. This IS exactly what occurs on
the DM7214/DM8214 The STROBE Input IS used
to place the output
state
In
this unique high-impedance
features
•
Ptn-for-pln compatible with SN54153/SN74153
•
Organized for party-line systems
•
Up to 128 deVices can be connected to a
common bus-line
•
Propagation delay 20 ns tYPical
•
Power dissipation 170 mW tYPical
•
Input diode clamps
•
Series 54174 compatible
D
The DM7214 is characterized for operation over
the full military temperature range of _55°C to
+125°C, the DM8214 is characterIZed for operation from O°C to 70°C.
logic and connection diagrams
Dual-in-Line and Flat Package
STROBE
A
DATA INPUTS
OUTPUT
Vct;2GADDRESS~2Y
OUTPUT
"
TOP VIEW
Analogous to DP4T Switch
OUTPUT
---0
"
~-"r-c>-
--0
I
I
---0
I
~
---0
truth table
DATA INPUTS
ADDRESS INPUTS
CO
Cl
C2
STROBE
OUTPUT
C3
X
x-
DON T CARE
11')1
...
~
N
absolute maximum ratings
QO
:E
c
(Note 1)
7V
Vee
Input Voltage
Output Voltage
Time that two bus-connected devices may
be In opposite low Impedance states
simultaneously
(5% Duty Cycle)
Storage Temperature Range
Operating Temperature Range DM7214
DM8214
Lead Temperature (Soldering, 10 see)
........
...
,....
~
N
:E
c
electrical characteristics
55V
5.5V
Indefinitely
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
(Note 2)
PARAMETER
CONDITIONS
Input blade Clamp Voltage
MIN
Logical "1" Input Voltage
DM7214
DM8214
Vec = 4.5V
Vcc ~ 4 75V
Logical "0" Input Voltage
DM7214
DM8214
Vcc = 4.5V
Vcc - 4.75V
Logical "1" Output Voltage
DM7214
DM8214
Vce=45V
Vce- 4.75V
lOUT ~ -2.0 mA
lOUT - -5 2 mA
Logical "0" Output Voltage
DM7214
DM8214
Vcc=4.5V
Vcc - 4.75V
lOUT = 16 mA
Logical "1" Input Current
DM7214
DM8214
Vee= 5.5V
V ec - 525V
24
004
40
V
IlA
1.0
mA
-1.6
mA
DM7214
DM8214
Vce = 5.5V
Vee - 5.25V
V OUT = OV
Output Disable Current
DM7214
DM8214
Vce= 5 5V
Vce - 5.25V
V OUT = a 4V to 2 4V
V OUT - Oo4V to 204V
DM7214
DM8214
Vee = 5.5V
Vee - 5.25V
All inputs at GND
-55
-57
mA
40
-40
IlA
34
34
56
65
mA
50pF
15
12
23
18
ns
Vee" 50V, T A " 25°C, CL = 50 pF
20
20
34
34
ns
Vee= 50V, TA = 25°C, CL
-20
-18
"
tpdO
Delay from Logical "1" to H,-Z
Oytput State, t1 H
Vee ~ 5.0V, T A" 25°C
5
10
ns
Delay from Logical "0" to H,-Z
Output State, tOH
Vee" 5.0V, T A = 25°C
15
23
ns
Delay from H,-Z to Logical "1"
Output State, tH1
Vee" 5.0V, T A = 25°C, C L ~ 50 pF
12
18
ns
Delay from H,-Z to Logical "0"
Output State, tHO
Vee" 5.0V, T A" 25°C, CL
14
21
ns
"
50 pF
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electncal Characteristics" prOVides conditions
for actual deVice operation
Note 2: Unless otherWise specified minImax limits apply across the -55°C to +12Soe temperature
range for the DM7214 and across the oOe to 700 e range for the DM8214 All tYPlcals are gIven
for Vce = 5 OV and T A ~ 25°C
Note 3: Only one output at a tIme should be shorted
1_11?
V
V
3.2
V,N = 204V
Short-Circuit Output Current
INote 3}
PropagatIOn Delay from Address
to Output, tpd1
V
V ,N = 5.5V
V ,N =04V
tpdo
-1.5
V
0.2
Vee = 5.5V
V ec -525V
Propagation Delay from Data to
Output, tpd1
UNITS
0.8
DM7214
DM8214
Supply Current
MAX
2.0
Logical "0" I nput Current
IH,-Z Output State}
TYP
Vcc = 5 OV, liN = -12 mA
TA = 25°C
o
s:.....
Series 54/74
N
...A
CD
......
o
s:00
DM7219/DM8219 TRI-STATE®
16-line to one-line multiplexer
N
...A
CD
general description
features
The DM7219/DM8219 mUltiplexes sixteen digital
lines to one output. A four·blt code determines
the particular one-of·slxteen Inputs which IS routed
to the output. The data is inverted from Input to
output. A strobe over· ride places the output In the
high-Impedance state.
•
Typical propagation delay
10 ns
• TYPical power dissipation
225 mW
•
Series 54/74 compatible
logic and connection diagrams
OUTPUT
W
~
D~ ilW
rh
rh
II
rh
II
l~ ~ ~ i l l
II
m
II
II
m1m
Ilr
~
ll,
III
l
~
Or
,
II
c
0
C
B
B
STRDB E
1ENA8l EI
~E_O_________
E'____E_'____E'_____
E' ____E~'____E'~y~_E_"____E'____E_"____E_,,____
E,_,___E_,,____E,_,__~EI5J
~A__~v_~~
~
~
INPUTS
SELECT
(BINARY)
Dual-In-line and Flat Package
DATA
SElECT
DATA INPUTS
V"
r,
---....:::::..;.=-=---~, ~
1"
" "
21
18
19
20
17
~E'
E.
E"
En
E"
E"
Eo.
E,
E,
E,
E,
E,
E,
E.
15
16
2
3
, , ,
1
:+
W
8
,
10
' -_ _ _ _~_---_'STROBE
DATA INPUTS
13
A
Eoe
E,
1
"
t
" 112
S~t;~T
OUTPUT
t
GND
TOP VIEW
1_1'l'2
en
"""
N
co
absolute maximum ratings (Note 1)
operating conditions
...,...
Supply Voltage
Input Voltage
Storage Temperatu,e Aange
Lead Temperature (Soldenng, 10 secl
Supply Voltage (Veel
DM7219
DM8219
Temperature (TAl
DM7219
DM8219
:t
Q
.....
MIN
en
N
7V
5.5V
-65'e to +160'e
300'e
:t
0
electrical characteristics
CONDITIONS
~
Logical "I" Input Voltage
Vee
Logical "0" Input Voltage
Vee = Min
Logical "'" Output Voltage
i5'M82f9
MIN
Min
Vee = Min
V 'N (1) = 20V
V ,NIO ) ~ O.BV
lOUT" -2.0 mA
lOUT" -6 2 mA
Third State Output Current
Vee" Max, V OUT = 2.4V
V OUT ~ D.4V
Logical "I" Input Current
Vee = Max, Y'N = 2 4V
Y'N = 5 6V
Output Short Circuit Current
V
V
-55
0
+125
70
'e
'e
TYP
i5M82i9
24
" 4.5V
Supply Current
Vee" Max, V ,N
Input Diode Clamp Voltage
Vee" Mm, liN = -12 mA
T A " 25'C
Propagation Delay to a Logical "0"
from Data Select Inputs to Output,
tpdO
Vee = 5.0V
T A = 25'C
Propagation Delay to a Logical "'"
from Data Select Inputs to Output,
Vee = S.OV
T A " 25'C
04
V
±40
I'A
40
'.0
I'A
mA
-'6
mA
-100
-100
mA
mA
68
mA
-15
CL = 50 pF
RL " 40011
V
V
-30
-28
Vee" Max, V OUT ~ OV
UNITS
V
Vee = Max, V ,N " O.4V
DM7219
MAX
0.8
Vee = Min, V ,NllI " 2V, V ,NIO)" 0.8V
lOUT = +16 mA
"a" Input Current
55
5.25
20
Logical "0" Output Voltage
Logical
4.5
4.75
(Note 2)
PARAMETER
DM7219
UNITS
MAX
V
22
33
ns
2'
35
ns
'4
ns
20
ns
'0
ns
2'
30
ns
'5
23
ns
'7
27
ns
tpd1
Propagation Delay to a Logical "0"
from Data Inputs to Output, tpdO
Vee" 50V
TA = 25'C
Propagation Delay to a Logical "1"
Vee" 50V
TA ~ 25'C
from Data Inputs to Output, tpd1
Delay from Strobe to High Imped·
ance State (from Logical "," Levell,
t1H
Vee" 50V
T A " 2S'C
Delay from Strobe to High Imped·
ance State (from Logical "0" Level),
tOH
Vee" 5.0V
T A " 2S'C
Delay from Strobe to Logical ","
Level (from High Impedance State I.
tH1
Delay from Strobe to Logical "0"
Level (from High Impedance Statel.
tHO
Vee~
TA
SOV
8.5
'3
50
_." ....
= 2S'C
Vec=50V
TA = 2S'C
Note 1: "Absolute MaXimum Ratings" ar'e those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are nOt meant to Imply that the deVices should be operated at these limits The table
of "electrlcal Characteristics" provides conditiOns for actual device oper'8tlon.
Note 2. Unless other'Wlse specified min/max limits apply across the -65°C to +125°C temperature range for the DM7219 and
acrOSI! the O°C to 70°C fange for the OM8219, All typlcals are given for Vee = 5.0V and TA "" 25°C
Not. 3:
1.1~4
Only one output at a time should be shOr'ted,
o
s::
.....
truth table
...
N
CD
.....
INPUTS
0
C
•
A
X
X
X
0
0
0
0
0
0
0
E,
..
E,.
W
X
X
H!-Z
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
X
0
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
X
1
X
X
X
X
X
x
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
1
0
E"
E"
E,.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STROBE
E,
E,
E,
E3
X
1
X
X
X
X
X
X
0
0
0
X
X
X
X
X
0
0
0
1
X
X
X
X
X
0
0
1
0
X
0
X
X
X
0
0
1
0
X
1
X
X
X
0
0
1
0
0
X
X
0
X
X
0
0
1
0
0
X
X
1
X
X
0
0
1
1
0
X
X
X
0
X
X
X
X
X
X
X
0
0
1
1
0
X
X
X
1
X
X
X
X
X
X
X
0
1
0
0
0
X
X
X
X
0
X
X
X
X
X
0
1
0
0
0
X
X
X
X
1
X
X
X
X
X
0
1
0
1
0
X
X
X
X
X
0
X
X
X
0
1
0
1
0
X
X
X
X
X
1
X
X
X
0
1
1
0
0
X
X
X
X
X
X
0
X
0
1
1
0
0
X
X
X
X
X
X
1
X
0
E,
OUTPUT
E,
E,
E,
E"
En
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
0
0
0
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
1
0
0
0
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
1
0
0
1
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
1
1
0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
1
1
0
1
0
0
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
0
1
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
1
1
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
0
1
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
0
1
1
1
0
0
X
X
X
X
X
X
X
X
X
0
X
1
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
0
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
X
X
X
X
o
s::
CO
...
N
CD
o
N
N
Series 54/74
CO
:E
c
........
o
N
N
DM7220/DM8220 parity generator and checker
"
:E
general description
c
The DM7220/DM8220 is a monolithic integrated
circuit which can be used to both generate a parity
bit and check for parity, Nine inputs and a single
output are provided, When it is desired to generate
a parity bit, eight of the nine inputs are connected
to the eight data transmission Iines, Depending
upon whether odd parity or even parity is desired
a logical 1 or a logical 0 is applied to the ninth
input, For a parity check, the output of the parity
generator (sending end) is connected to the ninth
input of the parity checker (receiver end), The
,resulting output of the parity checker will remain
in one particular logic state unless a bit is "lost"
during transmission,
The device is fully compatible with other
Series 54/74 circuits,
schematic and connection diagrams
Dual-In-Llne and Flat Package
OUTPUT
X=AG>e@C@O@E@F@GC±>H@P
typical application
If the controllme IS a logical "0" the panty generator
Will generate odd parity, The panty checker Will acknowledge the presence of an odd number of "l'''s
(odd panty) With a logIcal "0" on Its output
If the controllme IS a logical "1" the panty generator
will generate even panty The panty checker Will acknowledge the presence of an even number of "1 '''5
(even panty) With a logical "1" on Its output
1_1~~
o
3:
.....
absolute maximum ratings
N
N
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range DM7220
DM8220
Lead Temperature (Soldering, 10 sec.)
electrical characteristics
PARAMETER
o
......
7V
5.5V
10
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
o
3:
CO
N
N
o
(Note 1)
CONDITIONS
Logical" 1" I nput Voltage
DM7220
DM8220
Vee = 4.5V
Vee = 4.75V
Logical "0" I nput Voltage
DM7220
DM8220
Vee = 4.5V
Vee - 4.75V
Logical "1" Output Voltage
DM7220
DM8220
Vee = 4.5V
Vee - 4.75V
IOUT;'-4OO IlA
Logical "0" Output Voltage
DM7220
DM8220
Vee = 4.5V
Vee - 4.75V
lOUT = 16 mA
Logical "1" Input Current
DM7220
DM8220
Vee = 5.5V
'vee = 5.25V
VIN = 2.4V
Input Diode Clamp Voltage
DM7220
DM8220
Vee = 5.5V
Vee = 5.25V
Logical "1" Input Current
DM7220
DM8220
Vee = 5.5V
Vee = 5.25V
V IN = 5.5V
Logical "0" Input Current
DM7220
DM8220
Vee = 5.5V
Vee - 5.25V
VIN = O.4V
Output Short Circuit Current
DM7220
DM8220
Vee = 5.5V
Vee = 5.25V
V OUT = OV
Power Supply Current
DM7220
DM8220
Vee = 5.5V
Vee - 5.25V
MIN
TYP
MAX
V
2.0
0.8
V
V
2.4
0.4
-1.1
liN = -12 mA
TA = 25°C
UNITS
V
40
IlA
. -1.5
V
1.0
mA
-1.6
mA
55
mA
26
35
mA
-1.0
20
18
Propagation Delay to Logical "1 ", tpd1
Inputs A, B, C, D, E, F, G, H
Vee = 5.0V
Co = 50 pF
TA = 25°C
F.O. = 10
15
36
58
ns
Propagation Delay to Logical "0", tpdO
Inputs A, B, C, D, E, F, G, H
Vee= 5.0V
Co = 50 pF
TA = 25°C
F.O. = 10
11
32
52
ns
Propagation Delay to Logical "1 ", tpd1
Input P
Vee = 5.0V
Co = 50 pF
TA = 25°C
F.O. = 10
8
21
35
ns
Propagation Delay to Logical "0", tpdO
Input P
Vee = 5.0V
Co = 50 pF
TA = 25°C
F.O. = 10
7
14
25
ns
Note 1: Unless otherwise speCified the min-max limits apply across the -55°C to +125°C temperature
range for the DM7220 and across the OOC to 70°C temperature range for the DM8220. Ali typ,cals are
g,ven for Vee = 5.0V and T A = 25°C.
1·137
M
N
;
~S
Series 54/74
c
.......
M
N
N
":E
DM7223/DM8223 1-line to 8-line demultiplexer
C
general description
The DM7223/DMB223 1-line to B-line demultiplexer utilizes Series 54/74 compatible circuitry to
demultiplex a data train to one of eight outputs.
These eight outputs are capable of driving 10
standard TTL loads each. Three address lines
determine which output receives the data train.
When the data Input is a logical "0" only the
addressed output will be a logical "0". When the
data input is a logical "1", all outputs, and therefore the addressed output, will be logical "1 's".
connection diagram
logic table
Dual-in-Line Package
ADDRESS
DATA
0
0
0
0
0
0
0
0
1
ADDRESS
INPUTS
C
B
A
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
x = Don't Care
OUTPUTS
*0(1 not make &onnectlon to PlMS 100111
TOPVIEW
typical application
Digital Data Demultiplexer (1 Line to 64 Lines)
AD[lRESSINPUTS
2°
1-13B
2'
22
OUTPUTS
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
o
absolute maximum ratings
Supply Voltage
Input Voltage
Fan Out
Operating Temperature Range
DM7223
DM8223
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
3i:
(Note 1)
'-I
N
N
W
7V
5.5V
10
.......
_55°C to +125°e
oOe to 70°C
_65°C to +150 oe
300°C
00
N
N
W
o
3i:
(Note 2)
CONDITIONS
MIN
TYP
MAX
UNITS
Logocal "1" Input Voltage
DM7223
DM8223
Vee=45V
Vee - 4.75V
Logocal "0" Input Voltage
DM7223
DM8223
Vee = 4.5V
Vee - 4.75V
Logical "1" Output Voltage
DM7223
DM8223
Vee = 4.5V
Vee - 4 75V
lOUT = -400 I1A
Logocal "0" Output Voltage
DM7223
DM8223
Vee=45V
Vee - 4.75V
lOUT = 16 mA
Logocal "1" Input Current
DM7223
DM8223
Vee = 5.5V
Vee - 5.25V
VON = 2.4V
40
I1A
DM7223
DM8223
Vee = 5.5V
Vee = 5.25V
VON = 5 5V
1
mA
Logical "0" I nput Current
DM7223
DM8223
Vee=55V
Vee = 5.25V
VON =04V
-16
mA
Output Short Corcuot Current
(Note 3)
DM7223
DM8223
Vee = 5 5V
Vee - 5.25V
V OUT = OV
Supply.Current
DM7223
DM8223
Vee = 5.5V
Vee 525V
Input Clamp Voltage
DM7223
DM8223
Vee= 5 5V
Vee - 5.25V
20
V
0.8
2.4
V
04
-10
-20
-18
ION = -12 mA
V
V
-32
-55
mA
28
41
mA
-10
-15
V
Propagation Delay to a Logical "0"
Vee = 5.0V
T A = 25°C
COUT = 50 pF, F.O. = 10
12
24
35
n,
Propagatoon Delay to a Logical "1"
Vee = 5.0V
T A = 25°C
COUT = 50 pF, F.O = 10
12
26
35
n,
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electncal Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherWise specified mm/max limits apply across the _55°C to +125°C temperature
range for the DM7223 and across the DOC to 700
e
ranqe for the DM8223 All tYPlcals are given for
VCC = 50V and TA = 25°C.
Note 3: Only one output at a time should be shorted
,.,39
o
M
N
CO
Series 54/74
~
o
.......
®
o
DM7230/DM8230 TRI-STATE demultiplexer
M
N
"""
~
o
general description
features
The DM7230(DM8230 demultiplexer is another
•
•
•
•
Senes 54/74 compatible
20 ns propagation delay
Data complement capability
Very
low output Impedance-high drive
capability
• Separate Input disable controls
• High-Impedance output state which allows many
outputs to be connected to a common bus-I me.
device m National's TRI-STATE logic family.
Digital signals applied to two mput Imes can be
routed to two-of-four output lines depending upon
the logic on the Address Inputs. Outputs can be
directly connected to other similar outputs for use
in bus-organized systems.
logic and connection diagrams
Dual-In-Line and Flat Package
.
c~~:~~ o·.......::..----c>----j-I
UISA6L~ O
..----l1H>c>---~
logic table
DATA
CDMP
A
A
B
o
0
DATA
'x
COMP
B
1
~
X
~
o
0
x
X
lOX
X
0
1
1
1
0
1
X
X
lOX
lOX
X
X
0
0
1
1
1
I
1
I
I
1
1
1
1
0
ADDRESS A
21
2°
0
ADDRESSB
21
2°
x x
DIS
DIS
OUT
ABO
0
,
OUT
1
OUT
2
OUT
3
0
,-.7.JL-+,-+,",,-+--i;i-+--+;-.. -:-:r::t:t-:-:--::.+".: ~~::'[:.~o-t:~c:I!--5.; ..::t=:l'-i,~-+c:::r'';:.:1-'-Ts·-:-I
' :::
X
lOX
XII
X
X
)(
0
0
1
1
1
1
1
0
1
XII
XII
X
X
X
X
0
0
1
,
1
1
1
1
I
1
1
1
XII
X
X
0
1
1
1
1
0
o
1,140
O~X~~'~~
:t··t:o =--t,t:-~'x =--i, i-::+~o~·t~-:rt:r+t,~:Ct+·=i--::-:-t:::-+:,:~',t
'. ~ ~·:~:'Y···~i,::.t.:~,x~t::.~x,
x
x
0
0
1
0
0
I
1
1
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
1
I
1
1
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
X
X
1
1
1
1
0
0
X
X
0
0
1
1
1
1
1
1
1
I
X
X
0
1
I
0
I
0
1
1
X
X
X
X
X
X
1
1
I
0
0
0
1
I
1
0
0
0
1
1
I
1
I
1
0
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
0
1
1
1
1
1
1
I
1
1
0
0
0
0
0
I
1
1
I
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
X
X
X
Xl'
HI Z
HI Z
HI Z
HI Z
DATA
B
DATA
A
tOMPLE-COM'tEMENTB MENTA
c
absolute maximum ratings
3:
.....
Supply Voltage
Storage Temperature Range
Operating Temperature Range
DM7230
DMB230
Lead Temperature (Soldenng, 10 sec)
7V
55V
55V
Input Voltage
Output Voltage
Time that two bus-connected
devices may be In OPPosite
N
W
o
-5S0C to +12SoC
oOe to +70°C
.........
c
300°C
low Impedance states simultaneously
(5% duty cycle)
3:
CO
electrical characteristics
N
(Note 11
W
MIN
CONDITIONS
PARAMETER
OM 7230
Logical' 1" Input Voltage
Vcc=45V
Vee 4 f!:l\
Vee
Logical '0" Input Voltage
OM.L30
=
Vee
08
Logical "0" Output Voltage
"'~~ii-~;;;;"~~;;---+---i7~~"'~~o"",:;";;;,;~,,.v
lOUT
~~: - ~ ~~v
V IN -
=
24
16 rnA
DM7230
DM8230
1" Input Current
~~~ - ~5~v
02
04
V
-20
-10
-32
-16
mA
mA
80
40
"A
"A
VIN - 24V
All other Inputs
Logical "1" Input Current
DM7230
DM8230
~~~~~;~V
Outj..>ut Disable Current
DM7230
DM8230
Vee 55V Vo=24V
Vee - 5 25V Va = 04V
DM7230
DM8230
V,e 5 5V
- OOV
Vee . 525V Vo
DM7230
DM8230
Vee - 5 5V
Vee 525V Y'N
(Note 21
Supply Current
VIN
-30
-28
=
=
Output Diode Clamp Voltage
Vee 5 OV, TA
lOUT -12 mA
IOUT-+12mA
C
-
48
50V
Input DIOde Clamp Voltage
mA
40
-40
"A
"A
-70
mA
75
mA
-1 5
V
-1 5
V
V
25 C
Vee +1 5
50V, TA - 25 C
Vee
'"1"
10
55V
Vee 50V,T A = 25C
liN - -12mA
Propagal!on Delay to logical
V
35
Disable Inputs
Output Short Curren!
V
a 4V
Disable Inputs
All other Inputs
Logic,!'
UNITS
V
4 hV
;:;~,:;~;;~~~;;;.~_ _--t__-c~,,~~~o,-:;-5:;'7~+:-~, :~~~: =~ ;;A
Logical "0" Inpu! Current
MAX
20
45V
Logical '1" Output Voltage
DM7230
DM8Z30
TYP
C l =50pF
from Data or Complement Input, todl
13
20
Nonmvertmg
Inverting
from Data or Complement Input, tpdQ
Propagation Delay to logical "1'" from
Address Input, Ipdl (Note 3)
Propagation Delay to logical "0" from
NOlllnvertlngor Inverting
18
26
ns
Vee - 50V. TA - 25'C
C l = 50pF
20
36
c,
20
30
c,
13
25
IlS
16
25
lIS
Vee
50V. TA
50pF
=
25"C
Vee - 50V. TA
=
25'C
~
=
CL~50pF
Disable Input. tpd1 (Note 4)
Propagation Delay to Logical '"0" from
Vee
=
5OY, TA ~ 25"C
CL~50pF
Disable Input, tpdQ (Note 4)
"
Delay from Ol5able Input to High
Impedance State (Note 5). t'H
to"
Delay from Disable Input to Low
Vee = 50V, TA
Impedance State (Note 5). t HI
'"
CL~50pF
CL
Address Input, tpdQ (Note 3)
Propagation Delay to Logical "1"' from
'"
25 C
Vee - 50V, TA
PropagatIOn Delay to logical "'0"'
24
36
=
25 c C
CL~50pF
teo
C,
7
14
15
27
c,
15
18
23
27
c,
c,
Note 1: MinImax values apply across the -55°C to +125°e temperature range for the DM7230 and across the oOe to 700 e
range for the DM8230 unless otherWise speCified TYPlcals are given for TA co 25°C and Vee = 5 OV
Note 2: Only one output at a time should be short circuited,
Note 3: The only cond,tions under which a tpdO from the Address Inputs can be observed IS when an output goes from being
nonselected to being selected and the information being routed to that output IS a logical "0 " If the information had been a
logical "1," no change would have occurred and no measurement could have been made Similarly, the only tIme a tpd1 from
the Address mputs can be observed, IS when an output goes from being selected to being nonselected and the information that
had been routed to that output was a logical "0" If the information had been a logical "1," no change would have occurred
and no measurement could have been made
Note 4: Information
In
Note 3 concerning tpdO and tpdl from the address Inputs are applicable here also
Note 5: All delays involVIng tranSitIons to or from the High Impedance state are measured With respect to the Disable Inputs
For example, With A mformatlon at a logical "0" and Disable B at a logical "1" the selected output WIJI go from a logical "0"
to the High Impedance state some time, tOH, after D,sable A has gone from a logical "0" to a logical "1 "
1-141
o
r;
o
(W)
mode of operation
N
00
:E
......
COMPLEMENT AND DATA INPUTS
Q
When Complement A IS a logical "1 ", Data A will
appear Inverted at the output. When Complement A IS a logical "0", Data A will appear nonInverted at the ou tpu t.
o
(W)
N
.....
:E
Q
This function is accomplished on the chip through
the use of a two-input exclusive-OR gate with
Complement A and Data A as the two Inputs.
Therefore, the A information that IS routed to the
outputs is actually (Complement A <±! Data A).
That this is the case may be verified by examining
the logic diagram.
The two inputs of this exclusive-OR gate have
identical characterIStics, allowing the functions of
these two inputs to be reversed. Also the propagation delay from either Input to the output will be
the same. This IS also true for the Complement B
and Data B Inputs.
ADDRESS INPUTS
The Address A Inputs select to which of the four
outputs A information will be routed. The same IS
true for the Address B inputs and B Information.
If A and B information are both routed to the
same output simultaneously, that output will be a
logical "0" if either the A or B Information IS a
logical "0". All outputs which are not selected for
either A or B information will be In the logical "1"
state.
DISABLE INPUTS
The Disable Inputs are similar to higher order
Address inputs in that when Disable A is a logical
",.', A Information is not routed to any output.
All four outputs are nonselected for A information. The same is true for Disable Band B information The Disable inputs have the additional feature that when both Disable A and Disable B are a
logical "1" all outputs go to the High Impedance
state. When multiple outputs are connected to a
bus line, only one deVice at a time can be In the
normal low Impedance state. All others should be
gated Into the high Impedance state (Figure 1).
The selected device therefore has the normal TTL
low Impedance output providing good capacitive
drive capabl hty and waveform Integrity especially
during the transition from the logical "0" to logical "1" state. The other outputs-in the high Impedance state-take only a small amount of leakage current from the low Impedance outputs.
Since the logical "1" output current of the selected deVice is 13 times that of a conventional
Senes 54/74 deVice (5.2 mA vs 400 MA), the output is easily able to supply that leakage current to
as many as 127 other DM7230/DM8230's and still
have available drive for the bus-line. (Figure 2)
BUS LINES
12D"A FOR DRIVING OTHER lPTTL INPUTS
~
o
SELECTED AS
DRIVING ---.
DEVICE
SELECTED AS
DRIVING
DEVICE
M
8
2
3
o
GATED INTO
THIRD STATE
GATED INTO
THIRD STATE ---+-
lOp.A It 45 OUTPUTS = 9 rnA
LEAKAGE CURRENT
GATED INTO
THIRD STATE
20,uA LEAKAGE CURRENT
Figure 1
1-142
Figure 2
00
Series 54/74
3:3:
""
COCO
NN
"'0
..................
00
3:3:
DM7280/DM8280(S8280/N8280) presettable decade counter
DM7281/DM8281 (S8281/N8281) presettable binary counter
DM7288/DM8288 (S8288/N8288) presettable -:-12 counter
COco
NN
COco
''''0
o
general description
The counters In this series are four-bit monolithic
subsystems containing a dlvide-by-two counter
with one clock Input and a second counter with a
second clock Input. The two clock Inputs and the
other logic functions provided will Implement a
wide variety of counter and storage register func·
tlons.
•
Two clock Inputs for additional flexibility
•
Strobed parallel-entry capability
•
Reset Inputs common to all stages
•
TYPical toggle rates to 45 MHz
•
TYPical power dissipation of 130 mW
3:
"Nco
CO
.........
o
3:
co
features
•
Direct-coupled stages
N
•
•
Available In cavity or molded 01 P
CO
CO
Senes 54/74 compatible
connection diagrams
(Dual-In-Lmeand Flat Packages)
DM7280/DM8280
DM7281/DM8281
DM7288/DM8288
1-143
·CO
°co
CON
NCO
absolute maximum ratings
Supply Voltage
I nput Voltage
Operating Temperature Range
DM7280, DM7281, DM7288
DM8280, DM8281, DM8288
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
CO~
~C
C .......
....... CO
°co
CON
N"
"~
~C
C
....
electrical characteristics
N
CO
MIN
~
C
.......
"1" Output Voltage l31 141
TYP
N
"C~
MAX
(Notes 1, 2)
UNITS
V
V
V
26
28
26
"0" Output Voltage l31 15)
....
CO
_55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
LIMITS
CHARACTERISTICS
CO
7V
5.5V
TEMP
Vee
O°C
+25°C
475V
50V
475V
+75°C
DoC
DATA
STROBE
DATA
INPUTS
RESET
o 8V
20V
20V
20V
20V
20V
20V
Output A
Output A
Output A
-200 }1A
-200 I1A
-200 I1A
o 8V
o 8V
o 8V
Output A
64 rnA
64mA
64mA
o8V
o 8V
o8V
o 8V
CLOCK
1
CLOCK
2
OUTPUTS
04
04
04
V
V
V
-16
-12
-30
-28
-32
-16
-32
-16
mA
mA
mA
mA
mA
mA
mA
mA
+25°C
25
25
75
50
75
75
pA
pA
pA
pA
pA
pA
+75°C
+75°C
+75°C
+75°C
+75°C
+75°C
50V
50V
50V
50V
50V
50V
25
25
n,
n,
+25 C
+25 Q C
50V
50V
64 rnA
25
25
n,
n,
+25°C
+25"C
50V
5 OV
64 mA
35
n,
+25°C
50V
64 mA
+25°C
+75"'C
475V
50V
4 75V
o 8V
o8V
o 8V
Output A
Output A
o8V
"0" Input Current
Data Strobe
Data Inputs
Reset (DM8280, DM8281)
Reset (DM8288)
Clock 1 'OMB28D, DMB281)
Clock 1 (DM8288)
Clock 2 (DM8280)
Clock 2 (DMB281, DM8288)
-01
-01
-01
-01
-01
-01
-01
-01
+25 C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Q
525V
525V
o 4V
o 4V
o 4V
o 4V
525V
525V
525V
525V
525V
525V
04V
o 4V
o 4V
o 4V
"1" Input Current
Data Strobe
Data Input
Reset (DMB28a, DMB281)
Reset (DM8288)
Clock 1
Clock 2
45V
45V
45V
45V
45V
45V
Clock Mode TON Delay
Bit A
Bit B, C, D
c
Clock Mode T OFF Delay
Bit A
Bit B, C, D
Data/Strobe TON Delay
Bit A, B, C, D
Data/Strobe T OFF Delay
45
Bit A, B, C, 0
Toggle Rate
20
45
35
Clock Mode SWitching Test(61
Output Fall Time
Power Consumption
130
n,
+25°C
50V
64 mA
MH,
MH,
+25°C
+25°C
50V
50V
64 mA
64 mA
00
"
+25°C
50V
50
nA
+25°C
475V
194
mW
+25°C
525V
V
V
V
+25°C
+25°C
+25°C
50V
50V
50V
lOrnA
mA
+25°C
50V
OV
pF
+25°C
50V
Pulse
Pulse
OV
OV
100 pF
OV
Input Voltage Rating
55
55
55
Data Strobe
Data Inputs
Reset
10mA
lOrnA
Output Short Circuit
-10
Current
-60
Input Capacitance
30
Strobe Memory Holding
Time with "1" to "0"
Clock or Output
Transition
With no "1" to "0"
Clock or Output
TranSition
17
35
ns
+25°C
50V
o 8V
20V
20V
Output A
17
35
"
+25°C
50V
20V
20V
20V
Output A
o 8V
20V
20V
Output A
20V
Output A
Strobe Pulse Width
25
ns
+25°C
50V
Reset Pulse Width
30
n,
+25°C
50V
Note 1:
that are
Note 2:
Note 3:
Note 4:
Note 5:
Note6:
1·144
OV
20V
o 8V
All voltage and capacitance measurements are referenced to the ground terminal. Terminals
not specifically referenced are left electrically open.
Positive current flow IS defined as the current Into the referenced terminal.
Measurements of each output and the associated data Input apply Independently.
Output source current IS supplied through a resistor to ground.
Output Sink current IS supplied through a resistor to Vec.
The unit Will tolerate any fall time on the clock due to the DC deSign.
00
S:S:
general description (cont.)
'oJ 'oJ
NN
0000
The DM7280/DM8280 counter operates as a divldeby-two and divide-by-flve counter with no external
connections. When the A output IS connected to
the Clock 2 input, It counts In the familiar BCD
mode. The bl-quinary mode is obtained by connecting the D output to the Clock 1 input while
applying the clock to the Clock 2 Input. This
produces a square-wave output at fila on the A
output that IS particularly useful tn frequency
synthesizers.
The DM7281/DM8281 is a 2,2,4,8 counter when
operated with two clock inputs and no external
connections. It IS a 2,4,8,16 counter when the A
output IS connected to the Clock 2 input. Thus,
It may be used as a divide-by-two, -eight, or
-sixteen counter.
The DM7288/DM8288 consists of divlde-by-two
and divlde-by-slx counters. For dlvide-by-twelve
operation, output A IS connected to the Clock 2
input.
,~
Counttng IS performed on the negative-going edge
of the clock pulse In all three types. The dlvldeby-two stages may be toggled at up to 45 MHz,
typical, approximately tWice the maximum frequency of the Clock 2 input.
00
S:s:
0000
N
N
0000
.... 0
All three have parallel Inputs which may be used
to set the corresponding outputs to desired states.
The parallel Input logic levels are transferred to the
outputs when the strobe line IS placed at the logical "0" level. A "0" on the reset line will place
all four outputs tn the "0" state.
o
s:
'oJ
N
00
00
........
o
The register-storage function can be obtained by
using the strobed parallel-entry capability. Data to
be stored is entered by the method indicated above
and retatned on the outputs holding both clock
inputs at logical "1" (V cel The register may be
reloaded with a new parallel entry and strobe
operation or cleared by the reset line.
s:
00
N
00
00
1-14'i
N
co
Ln
Series 54/74
co
~
C
o
~
o::t
DM74200(SN74200) TRI-STATE®
256-bit random access memory
C
DM8582 256-bit random
access memory (open collector)
I'
~
general description
The DM74200 and the DM8582 are 256 x 1 read!
write random access. TTL memories which can be
used in applications ranging from scratch· pad to
main memories. Eight address inputs select the
proper bit·location and a Wnte·Enable input deter·
mines whether the read mode or write mode is
chosen. Three ch ip-enable inputs determ ine whether
the output is in the conventional logical "1" or
logical "0" state or whether it is gated into the
off· state (DM8582) or the high·impedance state
DM74200. The off·state and high·impedance states
are usefu I when connection is made to a common
bus·line.
features
•
•
•
•
40 ns typical address access time, DM74200
50 ns typical address access time, DM8582
20 ns typical chip select access time
<2 mW!bit typical power dissipation
connection diagram
Dual·ln*Line Package
DATA
IN
"
14
WE
13
11
12
10
-
CE,
CE,
CE,
DATA
OUT
J:
TOP VIEW
truth table
CE
WE
OPERATION
Write
Read
H
H
1·146
OUTPUT
IDM8582)
Logical" 1"
(Open Collector)
OUTPUT
IDM74200)
High Z
D {Complement
o (Complement
of Stored Datal
of Stored Data)
Do Nothing
Logical "1"
High Z
Do Nothing
Logical" 1"
High Z
c
absolute maximum ratings
:s:
......
(Note 1)
.J:o,
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM74200, DM8582
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
N
o
o
7V
5.5V
5.5V
O°Cto+70°C
_65°C to +150°C
300°C
c
:s:
00
U1
00
N
electrical
ch~racteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
DM74200
DM8582
Vee = 4.75V
Logical "0" Input Voltage
DM74200
DM8582
Vee = 4 75V
Logical "1" Output Voltage
DM74200
Vee = 4 75V
, IsouAeE = 10 mA
Logical "1" Output Current
DM8582
Vee = 5.25V
,V ouT =55V
50
IJ.A
Logical "0" Output Voltage
DM74200
DM8582
Vee = 475V
, ISINK = 24 mA
04
V
Third State Output Current
DM74200
Vee= 5.25V
,V ouT =04Vor24V
Logical "1" Input Current
DM74200
DM8582
Vee = 5.25V
Y,N = 2.4V
'V'N = 5 5V
25
10
IJ.A
mA
Logical "0" I nput Current
DM74200
DM8582
Vee = 525V
,V ,N =04V
-10
mA
DM74200
Vee = 5.25V
,VOUT=OV
Supply Current
DM74200
DM8582
Vee=50V
Input Clamp Voltage
DM74200
DM8582
Vee = 4 75V , liN = -12 mA
Output Vee Clamp Voltage
DM74200
Output Ground Clamp Voltage
Address Access Time,
Output Short
C,fCUlt
Current
(Note 3)
tAA
20
V
08
2.4
V
V
-40
+40
-40
99
96
IJ.A
-80
mA
130
125
mA
mA
-15
V
lOUT = 12 mA
Vee + 1.5
V
DM74200
lOUT = 12 mA
-15
V
DM8582
DM74200
Vee = 5.0V
50
40
ns
ns
20
ns
Chip Select Recovery Time, t RCS
TA = 25°C
20
ns
Write Enable Pulsewldth, twp
RL
= 300n
25
ns
Sense Recovery Time, tSR
C L = 30 pF
40
ns
Chip Select Access Time, t ACS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electrlcal Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the OG
e
e
to 70 G
range for the
DM74200 and DM8582 All typlcals are given for VCC = 5 OV and TA = 25°C
1·147
o
N
It)
Series 54/74
CO
~
Q
........
o
N
It)
r-
~
Q
DM7520/DM8520 modulo-n divider
general description
without external components to divide by any
number from 2 to 15. Cascading of these dividers will provide division by any number
from 2 to very large numbers_
The DM7520/DM8520 combines TTL technology
and MSI (Medium Scale I ntegration) design to provide a circuit equal in complexity to more than 50
gates.
2. SHIFT REGISTER
Although extremely versatile In a number of digital applications, its primary usage will be realized
in two areas.
Since the basic organization of the logic is that
of a serial shift register, the device may be used
where four-bit parallel-in-serial out shifting is
required.
1. MODULO-N DIVIDER
A single DM7520/DM8520 can be programmed
logic diagram
PRESET
-C><>------.--+------~------_+-.._-------__,
SERIAL
INPUT ---,,---,..../
SERIAL
OUTPUT
INPUT-i~-t-----~-I__t--~::::~:;j-_t------4-t__r------J
P,
OUTPUT
0000
DETECT
table for division by n
connection diagram
Dual~ln·Line
SERIAL
INPUT
and Flat Package
161- PRESET
P,
SETTING
P3
P2
P4
7BY
EXTERNAL
lSI- EX OR
INPUT
SERIAL
PARALLEL
INPUT
14
I- ~~~:UT
13~OUTPUT
'00
"
12
I-
GND
0000
DETECT
SERIAL
OUWUT
1-148
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
c
3:
-.J
U'I
absolute maximum ratings
N
o
7V
Supply Voltage
Input Voltage
Operating Temperature Range
3:
DMS520
O°C to +70°C
U'I
-65°C to +150°C
o
electrical characteristics
Logical "0" Output Voltage
CONDITIONS
DM7520
Vee
~
4.5V
DMS520
Vee
~
4.75V
DM7520
Vee
~
4.5V
DMS520
V ee
~
4.75V
DM7520
Vee~45V
DMS520
Vee
~
DM7520
Vee
~
4.5V
DMS520
Vee
~
4.75V
4.75V
DM7520
Vee
~
5.5V
Logical "0" Input Current
(All Inputs except pin 9)
DMS520
Vee
~
5.25V
Logical "0" I nput Current
DM7520
Vcc
~
5.5V
DM8520
Vcc
~
5.25V
DM7520
Vee
~
5.5V
DM8520
Vee
~
5.25V
(Pin 9)
Logical "1" Input Current
N
(Note 1)
PARAMETER
Logical "1" Output Voltage
00
300°C
Lead Temperature (Soldering, 10 sec.)
Logical "0" Input Voltage
c
DM7520
5.5V
_55°C to +125°C
Storage Temperature Range
Logical "1" Input Voltage
.......
MIN
TYP
MAX
V
2.0
O.S
lOUT
~
-400 j.l.A
lOUT
~
16 mA
UNITS
V
V
2.4
0.4
V
V ,N
~
O.4V
-1.6
mA
V,N
~
O.4V
-3.2
j.l.A
V'N~2.4V
40
j.l.A
V ,N
~
2.4V
SO
j.l.A
V ,N
~
5.5V
1
mA
55
mA
DM7520
Vee
~
5.5V
DM8520
Vee
~
5.25V
DM7520
Vee
~
5.5V
DM8520
Vee
~
5.25V
DM7520
Vee
~
5.5V
DM8520
Vee
~
5.25V
Power Supply Current
Vee
~
5.0V
TA~25°C
50
mA
Counting Frequency
Vee
~
5.0V
T A ~ 25°C
20
MHz
Logical" 1" I nput Current
(pin 9)
Logical "1" Input Current
(All inputs except pin 9)
Output Short CirCUit Current
(Note 3)
-20
V OUT
~
OV (Note 2)
-18
Note 1: Unless otherw1se specIfied, limits shown apply across the -550C to +125 0 C temperature
range for the DM7520 and the ODC to +70 o C temperature range for the DM8520 Typical values
apply to supply voltages of 5.0V
Note 2:
Only one output should be shorted at a time.
Note 3:
Serial and exclusIve OR outputs.
1·149
o
N
It)
CO
:ii!
Q
"-
o
N
It)
"""
:ii!
Q
theory of operation
The basic operation of the DM7520/DM8520 is
derived from the fact that wh en several outputs of
a shift register are EXCLUSIVE OR'ed and the
result fed back to the register's input, a unique
progression of stable states results on the outputs
of the flip-flops. Depending upon which outputs
are EXCLUSIVE OR'ed the number of different
states can be varied_ Even if optimum gating is
provided the most states which can be obtained is
2n-1, where n IS equal to the number of flip-flops
In the register. The all-zero state is precluded; and,
therefore, the maximum number of states is
always one less than the theoretical maximum
number. Since the DM7520/DM8520 contains
four flip-flops, its maximum number of states is
15. Because the 1111 state occurs only once durIng a 15-state sequence, this state is detected; and
its output becomes the output of the divider.
EXTERNAL EX-OR input, a 1 will be forced Into
the register at the next clock pulse, thus clearing
the unallowed state.
A PRESET input is provided which when taken to
a logical "1" level overrides all other inputs and
sets the register to the 1111 state.
To divide by numbers greater than 15, it is necessary to cascade DM7520/DM8520's. Both the
OUTPUT and the 0000 DETECT output are capable of being connected directly to other like outputs thus providing the "WI RED-OR" configuration. These outputs should be connected to the
similar outputs on other dividers for proper operation. All SERIAL/PARALLEL inputs should be
connected to the common OUTPUT.
To obtain frequency division by numbers other
than the maximum, it is necessary to cause the
register to "jump" immediately from ItS initial
1111 to the state which It would normally reach in
16-m (m = desired frequency division) pulses. For
example, to divide by eleven it would be necessary
to jump to the fifth state and then simply allow
the register to normally progress forward to ItS
original state. The output of the divider is also
used as a control pulse. Since the 1111 state is
detected and since the "jump-state" information is
of interest only at the time that this state is
reached, the OUTPUT is used to gate the parallel
inputs, through the SERIAL/PARALLEL input,
so that it recognIZes this "jump-state" information
only at this time. Subsequently as the states
change, the parallel input Information is locked
from the divider.
Other connections are shown. (Figure 1 indicates
connections for 2 dividers or a maximum frequency division ~f 255. For division by higher
numbers, a more complete discussion of the interconnection techniques will be given in the final
data sheet.)
To divide by numbers between 16 and 255, the
table in Figure 2 will apply.
Thus to summarIZe, the following connections
should be made for operation of a single DM7520/
DM8520.
Ex·Or Output to Serial Input
0000 Detect to External Ex·Or Input
Output to Serial/Parallel Input
Preset to Ground
Ex-Or Control to Ground
Should the divider ever be accidently set in the
forbidden 0000 state, an output is provided to detect this state. If this output is in turn fed into the
LOGICAL 1
-~
I. .
~p
EX OR'
OUTPU;
'"
EX OR
CONTRO l
5(
I;
0000
DETECT
\6
~
SERIAL
OUTPUT
INPUT
OM752010M8520
I OUTPUT
.-:- I
PR,ESET
INPUT
FREQUENCY
Exo~l_
-....,,,
I
SERIAl/PARAllEl
r
EX OR
CONTROL .J1
['Y
EXTERNAL
EX-OR
.,
I)
OM1520/0M85Z0
OUTPUT
INPUT
r---.~
'~'I PRESET
1
FIGURE 1. Connection for 2 Divider or Maximum Frequency Division of 255
1-150
-"I"
0000
DETECT
SERIAL
INPUT
5
j'
-=
OUTPUT /.c;
r:J
INP~
r
'""
~
lEXTERNAL
S-- EX OR
~
SERIAL/PARALLEL
c
., .,, .,,
DIVIDER 1
SETTING
I
p.J P,
, , , ,,,
, , , ,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
, ,
, ,
,, ,,
,
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
,
,,
,
,
0
0
1
1
0
0
0
0
,,
,
0
,
,
0
1
0
0
0
0
, ,
,, ,
, ,
0
0
1
0
0
1
0
0
0
1
1
0
0
,
0
0
, ,
,
0
,
,, ,,
,
,
, ,
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
,, ,
, ,
, ,
,
0
0
0
1
0
0
,
,, ,
,
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
.,, .,, .-,
,
,,
,,,
,
1
0
0
0
0
0
0
0
0
0
C
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
,
,,,
,
0
0
1
0
0
0
0
1
.0
0
0
.()
70
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
0
1
0
I
1
0
0
0
0
0
0
0
,,,
,
,
,
0
1
0
0
0
0
0
0
0
,
,
,
1
0
1
0
0
0
0
0
,
,
, , , , ,
, , ,, ,
,
,,
,, ,
, ,
, , ,
,, , , , ,
, , ,, , ,
, ,, ,,
, ,
,
,
, ,
,
, ,
,
,
,, ,,, , , ,
, ,
, , , ,, ,,,
,, , ,, , ,
, , , ,, ,, ,,
, , , , , ,
,
,
,
, ,, ,, , ,
, , , ,
,, ,, , , ,, ,,,
, , ,, , , ,
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
'"
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
.,, ., .,,
DIVIDER 1
DIVIDER 2
,,
,,
1
0
0
0
0
0
0
1
0
0
BY
255
254
253
252
25'
250
249
248
247
246
0
0
1
0
,
,,
,
,
1
1
1
0
1
,
,,
,
,
0
0
1
1
1
0
,
,,
,
,
235
234
233
232
231
230
229
228
227
226
1
0
1
1
0
a
1
'95
'94
193
'92
191
'90
'89
'88
'87
'86
'85
'84
'83
'82
'8'
'80
179
178
177
176
175
17.
173
'72
171
170
'69
'68
'67
'66
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
205
204
203
202
20'
200
199
'98
197
196
.,, .,, .-
1
0
0
0
0
, ,
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
I
I
,
,,
BY
0
I
I
0
1
1
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
1
0
,
,
, ,,,
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
, ,
,
'65
'64
'63
'62
'6'
160
159
'58
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
~+----~~--~--~-t+ -ill-
,,
,
,
,,
0
0
0
0
0
1
0
,
,
,,
,
,
,
,
,
0
0
0
1
0
1
1
0
1
0
0
1
,
0
0
0
0
1
,
,
,
0
0
1
,,
,
,,
,
,
,
,,
,,
,,
,,,
,
,
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
,,
,
,
, ,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
1
1
0
0
,, ,
0
0
1
0
0
0
,,
, ,
0
I
0
1
1
0
0
1
0
0
1
0
,,
,
,,
,
,
1
0
1
1
0
1
0
0
1
1
0
0
0
0
,,
,
,
,
0
0
0
0
0
0
0
0
0
1
0
1
0
0
,
0
1
1
,
,
,
,,
0
1
1
1
0
1
0
,
0
1
0
0
0
0
,
1
0
,
0
,
0
,
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
0
1
0
1
, , ,,
, ,, ,,
,
0
0
, ,
, , , ,
, ,
,, ,, ,, ,
,, ,,, ,,, ,,,
,, , , ,,
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
, ,
,
, ,
, ,, , ,
,
,, , , ,
, ,
, ,
,, , ,,
,, , ,, ,
,, , , ,,
, , ,
, ,, ,
, ,
, ,,
,, ,
, ,
, , , ,,
, , , ,
, , ,
,
,
, ,
,, ,, , ,
,, ,,, ,,, ,,
, , ,
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
107
'06
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
'35
134
133
'32
'3'
'30
'29
'28
'27
'26
125
124
'23
122
'2'
120
119
118
'17
116
1
1
0
0
0
1
140
139
138
137
'36
115
114
113
112
11'
110
109
0
0
0
SETTING
.,, .,, .,, .- I ., .,, .,, ••,
, , , ,
, ,
DIVIDER 1
DIVIDER 2
, , ,, ,, , , ,,
,,, ,, , , , ,, ,
,
,
0
2'5
2'4
2'3
212
211
210
209
208
207
206
I
·_1 .,
0
245
244
243
242
241
240
239
236
237
236
225
224
223
222
22'
220
2'9
2'8
217
2'6
SETTING
'08
'05
'04
103
'02
10'
100
99
98
97
96
95
94
93
92
9'
90
89
DIVIDER 2
0
0
0
, ,, ,, ,, ,, ,
, , , , ,
, , ,,
, ,
,
, , ,
, ..d-, , ,
, ,
,
,
0
0
0
0
0
0
0
0'
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
,,
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
O
0
0
0
0
1
1
0
1
1
0
0
0
0
0
,, ,
,, , ,
, , ,,
,, , ,,
, ,, ,
, , ,
, , ,
, ,, ,,
,
, ,
, , ,
, ,
,,, ,,, ,,,
0
0
0
0
0
,, ,
, , ,
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
,, ,
, ,
,
,
,
,
,
, ,
0
0
1
0
0
0
0
0
0
0
0
0
-BY
0
1
0
0
0
0
,
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
,
0
0
1
,,,
,
0
0
0
0
0
1
0
,
0
0
0
0
,
0
0
0
0
,
,,, ,,,
,, ,
,
, ,, ,
, , ,
, ,
,
, ,
,
,
, , , ,
, ,
,, ,, , , ,
, ,
,, ,, , , ,,
,, , , ,, ,
,, ,, ,, , ,
, , ,, , ,
, , , , ,,
, , , ,
,, , , , ,
, , ,
, ,
,,, ,, , ,
, , , ,
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
,,
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
U'I
N
s:00
72
71
70
69
U'I
N
68
67
o
66
6~
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
4'
40
39
38
37
36
35
34
33
32
3'
30
29
28
27
26
25
24
23
22
2'
20
'9
'8
17
'6
,.
'5
13
'2
11
10
9
0
8
7
6
0
0
0
o
......
c
75
74
73
0
0
s:.....
5
4
3
2
88
87
86
85
84
83
82
81
80
79
78
77
76
FIGURE 2. DM7520/DM8520 Shift Register DiVider Input Coding Table (2 Package Combinations)
1-151
.it)
it)
Series 54/74
CO
:E
c
.......
.it)
it)
,...
®
DM7551/DM8551 TRI-STATE quad D flip flop
:E
c
general description
The DM7551/DM8551 IsaTRI-STATE logic device
which prOVides four D-type flip flops In one package which operate synchronously from a common
dock.
features
•
Series 54/74 compatible
•
23 ns typical propagation delay
•
250 mW typical power dissipation
•
Outputs directly connectable for bus-line operation
•
A" do-nothing" state accomplished without gating the clock
•
Simple disable encoding
A unique three-state output allows the device to
be used In bus-organIZed systems. The outputs can
be directly wired to outputs of other DM7551/
DM8551 's without encountering the problems normally met with "collector- ORlng" TTL CirCUitS.
This IS accomplished by gating the normally low
Impedance logical "1" or logical "0" output into
a high Impedance state.
(Continued)
logic and connection diagrams
Dual-In-Line and Flat Package
DATA INPUT
DISABleS
1
DATA
INPUT
INPUT
INPUT
INPUT
INPUT
ABC
0
OUTPUT OUTPUT OUTPUT
OUTPUT
INPUT
DISABlE DISABLE
OUTPUT {
DISABLES
OUTPUT
OUTPUT
DISABLE OISABLE
CUTPure
a
A
C
0
truth table (Both Output Disables Low)
to
DATA INPUT DISABLE
DATA
INPUT
OUTPUT
Logical "1" on 1 or both Inputs
X
Qn
Logical "0" on both Inputs
1
1
Logical "0" on both Inputs
0
0
x=
1-152
Don't Care
tn+l
c
s:
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
7V
55V
55V
_65°C to +150D C
_55°C to +125D C
O°C to +70D C
300°C
Output Voltage
Storage Temperature Range
Operating Temperature Range
DM7551
DM8551
Lead Temperature (Soldering, 10 sec)
-..I
(J'I
(J'I
...
........
C
s:
CO
(J'I
(J'I
...
Time that two bus·connected devices may
be In Opposite low Impedance states
simultaneously
Indefinitely
electrical characteristics
(Note 2)
PARAMETERS
CONDITIONS
MIN
Input Voltage
DM7551
DM8551
Vee=45V
Vee 475V
Logical "0" Input Voltage
DM7551
DM8551
Vcc=45V
Vee 475V
Logical "1" Output Voltage
DM7551
DM8551
Vcc=45V
Vee - 4 75V
-2 0 ~
lOUT - -52 mA
Logical "0" Output Voltage
DM7551
DM8551
Vee=45V
V ee -475V
lOUT
Logical "0" Input Current
DM7551
DM8551
V cc "'55V
Vee 525V
VIN =040V
Logical "1 ' Input Current
DM7551
DM8551
Vee = 525V
Vee - 525V
VIN=24V
VIN = 5 5V
Output Current
In High Impedance State
DM7551
DM8551
Vee=55V
Vee - 525V
Vo = 24V
Vo-04V
Supply Current
DM7551
DM8551
Vee=55V
V cc =525V
Output Short Current
INote 3)
DM7551
DM8551
Vee= 55V
Vee~525V
Logical
"1"
TVP
MAX
V
20
080
lOUT =
=
24
-1 0
"
0 OV
040
V
-16
rnA
40
1
rnA
I'A
40
-40
50
V OUT
V
V
33
02
16 mA
UNITS
-30
72
rnA
-70
rnA
MaXimum Clock Frequency
Vee = 5 OV
C L = 50 pF
TA "25°C
25
30
Propagation Delay from Clock
Vee = 5 OV
CL = 50 pF
TA
25D C
11
20
28
ns
to Logical "0", tpdO
Propagation Delay from Clock
to Logical "1", tpdl
Vee" 50V
C L = 50 pF
TA=25D C
11
16
25
ns
I nput Data Setup Time, ts
OA T A
Vee = 5 OV
T A'" 25D c
3
10
ns
Input Data Hold Time, tH
DATA
Vee=50V
TA = 25°C
4
10
ns
TA
25°C
7
14
ns
Input Disable Setup Time, ts
DIS
Vee
=
5 OV
Input Disable Hold Time, tH
DIS
Vee
=
Delay from "Output Disable" to High
=
=
MHz
5 OV
T A =25 c C
-7
Vee = 50V
TA = 25D C
5
30
Vee = 5 OV
TA
=
2SoC
11
30
Vee = 5 OV
TA
-=
2SDC
16
30
Vee = 5 OV
T A = 25°C
21
30
ns
Vee = 5 OV
TA = 25°C
18
27
ns
ns
Impedance State (from Logical "1"
Level), t1 H
Delay from "Output Disable" to High
ns
Impedance State (from Logical "0"
Level), tOH
Delay from "Output Disable" to
Logical "1" Level (from High
I mpedance State), tH 1
Delay from "Output Disable" to
Logical "0" Level {from High
Impedance Statel, tHO
Propagation Delay from Clear
to Output, tpd R
Note 1; Absolute maximum ratings are those values beyond vvhlch the safety of the deVice cannot
be guaranteed Except for "Operating Temperature Range", they are not meant to Imply operating
conditions
Note 2: Unless otherwise specified the min-max limits across the -55.)C to +125°C temperature
range for the DM7551 and across the O°C to 70 0 temperature range for the DM8551 All tYPlcals are
given for Vee;:: 5 OV and T A = 25°e
e
Note 3: Only
1 output at a time should be shorted
1-153
...
I.C)
I.C)
co
~
Q
...
......
I.C)
I.C)
......
BUS LINES
12D rnA FOR DRIVING OTHER TTl INPUTS
~
SELECTED AS
DRIVING DEVICE - - - -
SElECHDAS
DRIVING
DEVICE
~
Q
40 ~A x 127 OUTPUTS ~ 5GB rnA
GATED INTO
TtllRDSTATE
GATED INTO
LEAKAGE CURRENT
GATED INTO
THIRO STATE - - - - -
THIRD STATE
40IJA LEAKAGE CURRENT
FIGURE 1
FIGURE 3
FIGURE 2
general description (cont.)
The high Impedance state occurs on all outputs of
ali deVices except the four outputs of the one de·
vice selected (Figure 11. The result IS that the
selected deVice has a normal TTL low Impedance
output· providing good capacitive drive capability
and waveform Integrity especially during the tran·
sltlOn from a logical "0" to a logical "1". The
other outputs are all in the "thlrd·state" and take
only a small amount of leakage current from the
driving outputs. Since the logical "1" output cur·
rent of the selected deVice IS 13 times that of a
normal Series 54/74 output (5.2 mA vs 400 flAI,
the output IS easily able to supply that leakage
current to as many as 127 connected deVices and
stili retain enough drive for a full Series 54/74
fan·out of 3 at the end of the bus line (Figure 21.
A two'lnput NOR gate faCilitates selection of the
driVing device through the use of only two octal
decoders for as many as 64 DM7551/DM8551's
(Figure 31.
A problem Inherent In conventional D·type flip
flops is that It IS Impossible to code the data Input
in such a way as to cause the flip flop to remain In
ItS present state when clocked. Because fleXibility
1·154
IS not as great as With a J·K flip flop (and ItS J~O,
K~O statel, to keep a D·type flip flop In ItS present
state It IS usually necessary to gate the clock,
which Increases the danger of false·clocklng. The
DM7551/DM8551 contains a gated input disable
which does not disrupt clocking, but rather re·
circulates information from the Q output to the 0
Input In thiS manner the flip flop does not change
state and the possibility of false·clocklng IS
eliminated
The follOWing logiC levels control the deVice.
•
Clocking occurs on the positive· gOing transition.
•
Clearing IS enabled by taking the Input to a
Logical "1" level
•
Outputs are placed In the "thlrd·state" If either
of the two Output Disable Inputs IS taken to a
Logical" 1" level.
•
The flip flops Will remain In their prevIous state
when clocked so long as either of the two Data
Input Disable Inputs IS taken to a Logical "1"
level.
The DM7551/DM8551 IS completely compatible
With other Series 54/74 deVices.
o
s:
Series 54/74
illS
.....
U'I
U'I
N
........
OM7552/0M8552 TRI-STATE® decade counter/latch
OM7554/0M8554 TRI-STATE
o
s:
binary counter/latch
CO
U'I
U'I
N
general description
The DM7552/DM8552 and DM7554/DM8554 are
TTL TRI-STATE Synchronous Decode and Binary
counter/latch circuits respectively_ The circuits
consist of a counter made up of four edge-triggered
JK flip-flops.
features
•
•
330 mW tYPical power dissipation
TRI-STATE outputs directly connectable for
bus-line operation
•
TR I-STATE outputs information may be latched
30 ns typical propagation delay
Count mode and Terminal Count output are
operable when the outputs are in the high
impedance state or latch mode
•
Blanking capability with the DM7552/DM8552
•
Positive true logic
The circuits logically combine the function of
counters for frequency division, latches to hold
the counter's information, and output buffer gates
wh ich allow active TT L outputs as well as the high
impedance (3rd) state for output multiplexing of
data.
Series 54/74 compatible
•
•
•
connection diagram
Dual,ln-line and Flat Package
TRANSFER
Vee
ENABLE
L"
"
3
2
1
'--<---'
OUTPUT
DISABLES
rRESET CLEAR
CP
flIC
CEP
" " '"
T3
.
;
6
'---=--C
)
HRM
COUNT
eET
9
J
GND
OUTPUTS
TOP
VI~W
typical application
Multi-Stage Synchronous Counter with Visual Display
OISPLAY
UNIT
DISPLAY
UNIT
DISPLAY
UNIT
COUNT
ENABLE
I:'~'~:~ANT
STAGES
cpo-~t-~~~~--~.,--~~~~--.,----~----~.,------------
STROBEo--....---;;1S;;-TS;:;T-;;AG~E---....---;2;;;ND:-;ST;:;'-;::GE;------4I'---,3;;RD;-;S:;;TA;;:6;-E---4-----;";:;'",ST;';'''GE;---
Counter stages can be cascaded as shown above to prOVide multiple stage BCD or binary synchronous countmg by uSing the
DM7552/DM8552 or the DM7554/DM8554 respectively. With a Terminal Count (TCI fan out of
SIX
the above scheme allows
seven stages to operate at the maximum frequency equivalent to a two stage counter.
The characters displayed can be held with a low level on the strobe line while the counters can continue counting. The
display can be updated by applYing a positive pulse to the strobe line.
1-155
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
N
It)
It)
operating conditions
(Note 1)
70V
55V
5.5V
-65°C to +150°C
300°C
Supply Voltage IVCCI
DM7552/54
DM8552/54
Temperature (T A)
DM7552/54
DM8552/54
MIN
MAX
UNITS
4 5
4 75
55
525
V
V
-55
+125
70
0
electrical characteristics
co
:E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
c
Logical "1" Input Voltage
N
Logical "0" Input Voltage
It)
It)
LogIcal "1" Output Voltage TC Output
lOUT = -04 mA
24
33
V
Logical "1" Output Voltage (Other Outputs I
lOUT = -2 mA IDM7552/54)
lOUT = -5 2 mA(DMB552/54)
24
3.3
V
.........
......
:E
c
20
V
OB
Logical "0" Output Voltage
lOUT = 16 mA
Third State Output Current
V OUT = OAV to 2AV
Logical "1" Input Current
Y,N = 2AV
02
04
V
V
±40
IJA
"CET"
Y'N = 5 5V
80
2
IJA
mA
"Other Inputs"
Y'N = 2AV
V ,N =55V
40
1
IJA
mA
Logical "0" I nput Current "CET"
"Other Inputs"
Output Short CirCUit Current (Note 3)
TC Output
Other Outputs
V ,N =04V
-20
-32
mA
V ,N =04V
-1.0
-1.6
mA
VOUT=OV
V OUT = OV
Supply Current (each device) Icc (max)
-20
-30
-55
-70
66
106
mA
mA
mA
Input Clamp Voltage
I'N=-12mA
Output Vee Clamp Voltage
Vee = OV lOUT = 12 mA
Output Ground Clamp Voltage
Vee = OV louT=-12mA
Propagation Delay to a Logical "0" from
Clock to Any Output, tpdO
Vee = 5.0V
T A = 25°C
23
45
ns
Propagation Delay to a LO]lcal "1" from
Vee = 5 OV
T A = 25°C
34
70
ns
Vee = 5.0V
T A = 25°C
26
50
ns
Clock to Any Output, tpd1
Propagation Delay from TE to
Output, tpd (TEl
-1.5
V
15
V
-15
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherwise specified minimax limits' apply across the -55°C to +125°C temperature range for the DM75521
DM7554 and across the O°C to 70°C range for the DM8552/DM8554. All tYPlcals are gIven for VCC ~ 5.0V and TA = 25°C
Note 3: Only one output at a time should be shorted
1-156
c
s:
electrical characteristics (cont.)
'-J
c.n
c.n
MIN
CONDITIONS
TYP
MAX
UNITS
27
8
ns
17
40
ns
Vcc = 50
T A = 25°C
21
45
ns
Delay from Output Disable to Logical
"0" Level (from High Impedance Statel. tHO
Vcc = 5.0
T A = 25°C
25
50
ns
Maximum Clock Frequency
Vcc = 5.0
T A = 25°C
PARAMETER
Delay from Output Disable to High
Impedance State (from Logical "1" Levell, t'H
Vcc = 5.0
T A = 25°C
Delay from Output Disable to High
Impedance State (from Logical "0" Levell. tOH
Vcc = 5.0
TA = 25°C
Delay from Output Disable to Logical
"1" Level (from High Impedance Statel, tHl
15
23
,
N
C
s:CO
c.n
c.n
N
c
s:'-J
c.n
c.n
MHz
,
.I=Jo
C
s:
mode of operation
CO
When the Transfer Enable (TE) IS at a logical "1"
level the data transfer paths between the counter
outputs and the output buffer gates are rna Intalned.
When the Transfer Enable (TEl is at a logical "0"
level, the data transfer paths are inhibited, and the
state of the output buffer gates are locked In by
the latches. The counter and Terminal Count (TC)
output remain operable dUring th IS time.
c.n
c.n
CET IS high. The Terminal Count logic equations
are:
OM7552!OM8552 TC
OM7554!DM8554 TC
= CET
= CET
. A . B .C . 0
The follOWing logic levels control
II
the device:
•
The counter changes state on the positive-going
transition of the clock_
Asynchronous Clear (Cl) resets the counter to
0000.
•
Clearing or Presetting IS enabled by taking the
respective input to a logical "1" level.
Asynchronous Preset (PRE) resets the counter
to 1111.
•
To enable the count mode both CET and CEP
Inputs must be at a logical "1" level.
•
To latch the outputs the Transfer Enable (TEl
Input must be taken to the logical "0" level.
•
To place the TRI-STATE outputs into the
"Third-State" either of the Output Disable (00)
Inputs must be taken to the logical "1" level.
The 1111 state may be used in the DM7552!
DM8552 for blanking out leading zeroes In visual
displays. The next clock pulse will advance the
DM7552!DM8552 to 0001 which denotes the first
count of the blanked zero. The next clock pulse
will advance the OM7554!OM8554 to 0000.
.I=Jo
. A . B. C . D
The clock Input must be high dUring the high to
low transition of CEP and/or CET for correct
logic operation. The CEP and CET Inputs may be
used In a high speed look ahead technique (see
application) .
The Terminal Count (TC) output IS active high
when the counters are at terminal count and the
logic tables
FUNCTION TABLE
002
1
X
X
0
0
0
0
1
0
0
0
0
CEP
CET
X
X
X
X
X
X
X
X
X
X
1
1
CLEAR
• Function of the count sequence
DM7554/DM8554
BINARY COUNT SEQUENCE
OUTPUTS
OUTPUTS
INPUTS
001
DM7552/DM8552
DECADE COUNT SEOUENCE
PRESET
TE
1
X
X
X
0
X
0
1
1
X
0
0
X
X
X
X
1
1
A
B
C
0
"High Impedance State"
H'~r;'('T~tc
1
1
1
LATCH
COUNT
1
TC
OUTPUTS
COUNT
A
B
C
a
TC
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
2
0
3
1
4
0
5
6
7
8
9
1
0
1
0
1
1
1
0
0
1
-'If Preset
Applied
Next
Count
1
1
1
1
1
0
0
0
0
0
COUNT
0
B
C
0
TC
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
2
0
3
4
0
1
5
1
6
7
0
8
0
9
10
11
12
13
14
15
• "The 1111 state may be used ,n ~QnJu"cl'on wIth
certain decoderldnvers t e DM5446, OM5447
A
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
and OM5448 tor blankIng leadmg zeroes
1-157
logic diagrams
DM7552/DM8552
.
,
OUTPUT
DISABlU
~
J
,
co
~
C
........
N
OUTPUT
~
S
,
OUTPUT
"
~
~ ~
N
It)
It)
TERMINAL
,
OUTPUT
nUTPUT
~
S
,
TRANSfER
ENABLE
COUNT
nUTPUT
,
, ,
LATCH
S
It)
It)
.....
~
~
C
+
-0'
r---""
~'
+"
-+-
" r-'[=LJ'
-
,
"
;::0,
irl---' '
"
,
'----; ~,
~
,
+
=;=U'
"
;::u'
" I--
"
~Sf!-
~¥I-
L..-..!!!'S~
~ESf!-
I
"
,-- .
COUNT ENABLE
TRICKLE
COU"TENABL
PARAllEL
,
:(I'DM7554/DM8554
.
,
OUTPUT
OUTPUT
OUTPUT
DISABLES
IjESET
1·158
,
OUTPUT
TERMINAL
OUTPUT
COUNT
"
OUTPUT
c
!:
Series 54/74
"""
U'I
U'I
W
.......
c
!:
OCI
c.n
c.n
DM7553/DM8553 TRI-STATE® eight bit latch
w
general description
The DM7553/DM8553 provides eight latcheswhose
Inputs and outputs are accessed on the same leads.
The fact that the outputs utilize TRI·STATE Circuitry allows this to be done. While in the high·
impedance state, the outputs and inputs are dlsabl·
ed and no information can be entered. When the
outputs are active the gating associated with each
latch prevents Information from being entered. The
outputs are disabled while information IS entered.
In this manner eight bits of storage can be accom·
plished with parallel inputs and outputs in a 16·pin
package.
features
• Series 54/74 compatible
• Typical power dissipation
• TYPical propagation delay
330mW
25 ns
logic and connection diagrams
Vcc::=18
GNU .. S
,---------;-,
DATAINPUT/OUTPUTl
I
I
I
I
DATAINPUT/OUTPUT20-:"+.......,.."""\
II
Oual·ln·LIn" and Flat Pickage
vr
"
READ
WRITE
WRiTE
"
13
"
DATA IN'UTS/OUTPUTS
11
12
,
10
1
fiiiO
,
mm
1
,
,
•
CLEAR
,
•
DATA INPUTSIOUTPUT$
.N.I'
TOPVI~W
truth table
CLEAR
ENABLE
READ
WRITe
1
0
0
x
x
x
1
X
1/0 STATE
Output
X
1
1
X
0
0
x
0
Write
0
0
0
1
Re~d
=
a
HI'z
CLEAR
1·159
absolute maximum ratings
Supply Voltage
I nput Voltage
Output Voltage
operating conditions
(Note 1)
7V
5.5V or 0.5V above Vee
Storage Temperature Range
Lead Temperature ISolderlng, 10 sec)
-65'Cto+150'e
300'e
,
Supply Voltage (Vee)
DM7553
DM8553
Temperature IT A)
DM7553
DM8553
MIN
MAX
UNITS
4.5
475
55
5.25
V
V
-55
0
+125
70
'c
'C
electrical ch aracteristics (Note 2)
PARAMETER
CONDITIONS
Vee
= Min
Logical "0" I nput Voltage
Vee
= Min
Logical "I" Output Voltage,
Output Enabled
Vee
= Min,
lOUT
= -5 2 mA (8553)
Logical "0" Output Voltage,
Output Enabled
Vee
= Min,
lOUT
= 16 mA
Logical "1" Input Current, Input Enabled
Vee
= Max,
Logical "I" Input Voltage
TYP
MAX
2.0
-2.0 mA 17553)
UNITS
V
0.8
V
V
2.4
0.4
V
1.0
mA
V ,N
= 5.5V
V ,N
= 2.4V
40
I'A
V ,N
= O.4V
-1.6
mA
Logical "0" Input Current, Input Enabled
Vee
= Max,
TRI·STATE 110 Current with Inputs &
Outputs Disabled
V,IO
= 2.4V
Vee
= Max, 7553
Output Short CirCUit Current
(Note 3)
MIN
or 04V
-28
-30
8553
Supply Current
66
Input/Output Vee Clamp Voltage
Vee
= OV,
= +12 mA
Input/Output Ground Clamp Voltage,
Outputs Disabled
Vee
= 5V,
Delay from Output to High Impedance
State (from Logical "I" Level), t'H
Vee
= 5.0V, T A = 25'C
Delay from Output to High Impedance
State (from Logical "0" Level), tOH
Vee
Delay from Output to Logical "1" Level
(from High Impedance State), tH1
Delay from Output to Logical "0" Level
(from High Impedance State), tHO
±40
I'A
-70
mA
93
mA
15
V
-1.5
V
7
12
ns
= 5 OV, T A = 25'C
20
30
ns
Vee
= 5.0V, T A = 25'C
22
33
ns
Vee
= 5.0V, T A = 25'e
25
38
ns
21
32
ns
lOUT
lOUT
= -12
mA
TRI-STATE OUTPUT CHARACTERISTICS
Delay from Clear Input to Output =
Logical "0", tpdA
10
15
ns
Data
=1
14
20
ns
Data
=a
26
36
ns
Data
=1
-26
-15
ns
Data
=a
-14
-8
ns
28
40
ns
Min Clear Pulse Width Required, t,pw
Data Setup Time,
ts
Data Hold Time, th
Min Wnte Pulse Width Required, !wpw
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherwise specified mm/max limits apply across the _55°C to +12SoC temperature range for the DM7553
and across the O'C to 70'e range for the DM8553. All tYPlcals are given for Vee = 5.0V and T A = 25°C
Note 3: Only one output at a time should be shorted.
1-160
o
Series 54/74
3:
"""
en
U'I
o
........
o
3:
(1)
U'I
DM7560/DM8560(SN54192/SN74192) up/down decade counter
en
o
general description
The DM7560/DM8560 IS a TTL, Series 54174 compatible, up-down decade counter which IS capable
of being preset to any number from 0 through 9,
A load Input controls the asynchronous entry of
these numbers, and sets all outputs to appropriate
state,
Counting IS performed through two clock Imes-
one controlling the count in the up direction, and
the other in the down direction, Two outputs, Borrow and Carry, are connected to the clock inputs
of subsequent counters to provide for counting to
numbers greater than 9, The counter is synchronous by itself, and "semi-synchronous" Itwo gate
delays between stages) when cascaded,
logic diagram
II
1-161
o
CD
,
It)
absolute maximum ratings
CIO
:!
Q
........
Vee
I nput Voltage
Operating Temperature Range
o
CD
It)
......
70V
55V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
10
300°C
DM7560
DM8560
Storage Temperature Range
Fanout
Lead Temperature (Soldering, 10 sec)
:!
Q
electrical characteristics
(Note 1)
PARAMETER
Logical "1" Input Voltage
CONDITIONS
DM7560
DM8560
Vee
Vee
-
C
C
4 5V
475V
Logical" 1" Output Voltage
DM7560
DM8560
Vee
Vee
DM7560
DM8560
Vee
Vee
Logical" 1" I nput Current
(All Inputs)
DM7560
DM8560
Vee c55V
Vee 525V
V ,N =24V
Logical" 1" I nput Current
(All Inputs)
DM7560
DM8560
Vee
Vee
V ,N
Logical "0" I nput Current
DM7560
DM8560
Vee 55V
V ee c 525V
V ,N c 04V
Output Short Circuit Current
(Note 2)
DM7560
DM8560
Vee c55V
Vee 525V
V OUT ., 0
Supply Current
DM7560
DM8560
Vee c55V
V ee -525V
0
C
C
C
MAX
08
45V
475V
lOUT
C
-400 J.1A
45V
4,75V
lOUT
C
16 mA
UNITS
V
V ee c 45V
Vee - 475V
DM7560
DM8560
V
V
24
04
V
40
J.1A
1
mA
-1,6
mA
C
C
C
5,5V
5,25V
C
C
5 5V
C
Propagdtlon Delay to d
Logical "1", tpdl
Vee = 50V
T A c 25°C
From Clock to Output
Propagation Delay to a
Logical "0", tpdO
Vee = 5 OV
T A 25°C
From Clock to Output
MaXimum Clock Frequency
Vee 5,OV
T A o 25°C
C
-20
-18
From Clock to Carry/Borrow
From Clock to Carry/Borrow
Note 2: Only 1 output may be shorted at a tIme
-55
mA
50
89
mA
27
22
38
30
ns
ns
37
18
47
30
ns
ns
C
20
Note 1: SpecIfIcations apply across _55°C to +125°C temperature range for the DM7560 and OoC to
700 e for the DM8560 unless otherWise specified. TYPlcals are given for Vee"" 5V and T A = 25°C only.
1·162
TYP
20
Logical "0" Input Voltage
Logical "0" Output Voltage
MIN
30
MHz
o
3:
.....
logic waveforms
U1
en
o
IExampleshownfor (1) ctearlng, (2l asynchronously settlOQtD eight count,
__________________________
.......
~~----------------------------
3:
(J) counting "up"to two, and (4) counting "down" to eight I
-1l~
CLEAR
o
I
LOAD
I
CO
I
U1
I
en
A'"~L....!.I__+-____
o
BIN~L-!.._-!.._ _ __
CIN~L-+_-!____
OIN--.-J
LJLJLJL.J
CLOCK UP
I
I
I
CLOCK DOWN
I
I
r
I
I
I
I
I
I
I
r
LJLJLJL.J
I
I
I
I
I
I
I
I
AOUT
I
BOUT
I
r----i
----,
L--...!._ _ _ _~~_~~,
~~~~-~--_
COUT
~L_-!_ _ _ _+-..!-+_....!..__:'-__..!-_...!......l..-+_---"f-___
Dour
--,
li----..!......!.......,i
u
i
I
~i-~--~--~-~-7'~i
L---J
LJr' --------~:------
CARRY
I
BORROW
NOTES
----------------------~LJ
LOAD AND CLEAR INPUTS SHOULD NEVER BE ENABlED TOGETHER
A, D, C AND 0 INPUTS ARE FREE TO CHANGE AFTER LOAD INPUT IS DISABLED
WHEN COUNTING "UP", THE "DOWN" CLOCK MUST BE IN THE LOGICAL 1 STATE, AND CONVERSELY
cascading counters
f------lCLDCK UP
f------l~~~CNK
connection diagram
Dual-In-Llne and Flat Package
Vee
BIN
AIN CLEAR BORROW CARRY LOAD
BOUT
AOUT
CLOCK CLOCK
DOWN
UP
COUT
CIN
Dour
DIN
GROUND
TOP VIEW
l-lR:1
Series 54/74
DM7563/DM8563(SN54193/SN74193) up/down binary counter
general description
The DM7563/DM8563 is a TTL, Series 54174 compatible, up-down binary counter which is capable
of being preset to any number from a through 15.
A load input controls the asynchronous entry of
these numbers, and sets all outputs to appropriate
state.
Counting is performed through two clock lines-
logic diagram
1-1R4
one controlling the count in the up direction, and
the other in the down direction. Two outputs, Borrow and Carry, are connected to the clock inputs
of subsequent counters to provide for counting to
numbers greater than 15. The counter is synchronous by itself, and "semi-synchronous" (two
gate delays between stages) when cascaded_
c
s:
.....
absolute maximum ratings
C1I
Vee
Input Voltage
Operating Temperature Range
en
w
........
70V
55V
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
DM7563
DM8563
Storage Temperature Range
Fanout
Lead Temperature (Soldering, 10 sec)
C
s:00
10
C1I
en
300°C
electrical characteristics
w
(Note 1)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
DM7563
DM8563
Vee"45V
Vee 475V
Logical "0" I nput Voltage
DM7563
DM8563
Vee = 4 5V
Vee = 4 75V
Logical" 1" Output Voltage
DM7563
DM8563
V ee =45V
V ee -475V
lOUT = -4001JA
Logical "0" Output Voltage
DM7563
DM8563
Vee=45V
Vee 475V
lOUT = 16 mA
Logical" 1" I nput Current
(All Inputs)
DM7563
DM8563
Vee = 55V
Vce=525V
V ,N =24V
40
IJA
Logical" 1" I nput Current
(All Inputs)
DM7563
DM8563
Vee= 55V
Vee = 525V
V ,N =55V
1
mA
Logical "0" I nput Current
DM7563
DM8563
Vee=55V
Vee - 525V
V ,N =04V
-1.6
mA
Output Short CirCUit Current
(Note 2)
DM7563
DM8563
Vee=55V
Vee - 525V
V OUT = 0
Supply Current
DM7563
DM8563
Vee=55V
Vee - 525V
Logical "1" Input Voltage
2.0
V
0
Propagation Delay to a
Logical" 1", tpd 1
Vee = 50V
TA = 25°C
Propagation Delay to a
Logical "0", tpdQ
Vee=50V
T A = 25°C
MaXimum Clock Frequency
Vee = 50V
TA = 25°C
08
24
-20
-18
From Clock to Output
From Clock to Output
From Clock to Carry/Borrow
Note 2. Only 1 output may be shorted at a time
Vee"" 5V
and T A = 25°C only
V
-55
mA
50
89
mA
27
22
38
30
ns
ns
37
18
47
ns
30
ns
30
Note 1: SpecificatIOns apply across _55°C to +125°C temperature range for the OM7563 and QOC to
70c e for the DM8563 unless otherWise spec~fted Typlcals are given for
V
04
From Clock to Carry/Borrow
V
MHz
logic waveforms
[Example shown fOI (1) clearing.
I
masynchronouslV setting to fourteen count,
(3} counting "up" to two, and (4) countmg "down" 10 fourteen I
...Jl
CLEAR
------------------------------------------------
~r------------------------------------------------
LOAD
I
A,.
11..+:__+ ____
BIN .--J
C1N.--J
~
CLOCK UP
I
I
j
I
I
CLOCK DOWN
t
I
I
I
I
I
I
I
LIUULJ
I
I
I
I
Aour
I
BOUT
I
I
-U
Dour
CARRY
BORROW
NOTES.
I
I
I
I
~
I
I
r-----l
~,--~--~
I
Cour
I
I
I
~,--~,~,~
I~----~~~I'
L-.J
.
I
I
I
I
I
j
:
-U
I
I
r--~----I
--------------~~LJ~'-----------------~~-----------
----------
-----------------------------------;LJ~I
1. LOAD AND CLEAR INPUTS SHOULD NEVER BE ENABLED TOGETHER
2 A, e, C, and 0 INPUTS ARE FREE TO CHANGE AFTER LOAD INPUT IS
DISABLED
WHEN COUNTING "UP", THE ''~OWN'' CLOCK MUST BE IN THE LOGICAL 1 STATE, AND CONVERSELY
cascading counters
L..--_________
1------1 CLOCK UP
1-____--Ig~~CNK
~
~
connection diagram
Dual-In-Llne and Flat Package
Vee
BIN
1·166
Alf.j CLEAR BORROW CARRY LOAD
BOUT
AOUT
CLOCK CLOCK
DOWN
UP
TOP VIEW
COUT
tiN
Dour
OIN
GROUND
________
o
s:.....
Series 54/74
U'I
.....
o
.......
o
s:
00
DM7570/DM8570 (SN54164/SN74164)
8 - bit serial-in parallel-out shift register
U'I
~
general description
The DM7570/DM8570 utilizes Senes 54/74 compatible TTL circuitry to provide an eIght-bit
senal-In parallel-out shift register designed to operate at frequencies of
MHz_ Other features include gated senallnputs for strobe capability and a
clear Input WhiCh, when taken to a logical 0, asynchronously sets all flIp flops to the logical 0 state
Because the flIp flops are R-S Instead of J-K, Input
informatIon may be changed ImmedIately pnor to
the tnggenng edge of the clock waveform. LogIcal 1 levels on SA and SB enter logIcal 1 's Into the
shift regIster Clocking occurs on the posItIve-going
edge of the clock pulse.
26
logic and connection diagrams
01
112
113
04
0'
05
07
01
0'
Dual-In-Line and Flat Package
SA
sa
02
0'
o.
GND
TOP VIEW
1-167
o
......
absolute maximum ratings
It)
00
~
c
Supply Voltage
Input Voltage
Fanout
Storage Temperature Range
Operating Temperature Range
......
o......
It)
7V
5,5V
5
_65° C to +150° C
-55°C to +125°C
DoC to +70°C
300°C
DM7570
DM8570
Lead Temperature (Soldering, 10 sec,)
......
~
c
electrical characteristics
(Note 1)
PARAMETER
LogIcal "1" Input Voltage
Logical "0" Input Voltage
Logical
"1" Output Voltage
Logical "0" Output Voltage
Logical "1" Input Current (Except Clear Input)
Logical
"1"
Input Current {Clear Input)
Logical "1" Input Current
Logical "0" Input Current (Except Clear Input)
Logical "0" Input Current (Clear Input)
Output Short Circuit Current (Note 2)
Power Supply Current
CONDITIONS
DM7570
Vee'" 4 5V
DM8570
Vcc=475V
DM7570
Vee = 4 SV
DM8570
Vee - 4 75V
DM7570
V cc ",,45V
DM8570
Vee - 4 75V
DM7570
Vcc=45V
DM8570
V cc -475V
DM7570
Vcc=55V
DM8570
V cc -S25V
DM7570
Vcc=55V
DM8570
Vee - 525V
DM7570
Vee'" 5 5V
DM8570
V cc -525V
DM7570
Vcc=55V
DM8570
V ee -525V
DM7570
Vcc=55V
DM8570
Vee
DM7570
Vcc=55V
DM8570
Vee - 525V
DM7570
Vee=55V
DM8570
Vee ""S25V
525V
MIN
TYP
MAX
20
V
08
lOUT = -200 J.l.A
UNITS
24
V
V
04
lOUT = 8 mA
V
VIN=24V
40
~A
VIN =24V
80
~A
VIN =55V
1
mA
V 1N =04V
-16
mA
V 1N =04V
-32
mA
-275
mA
VOUT = OV
-10
-9
36
= 5 OV, 2SoC, 50% Duty Cycle
54
mA
14
20
Vee = 5 OV, TA = 25°C, C = 50 pF
10
28
40
ns
= 50 pF
10
28
40
ns
34
50
ns
MaXimum Clock Frequency
Vee
Propagatton Delay to a Logical "0" from Clock
to Output, tpdO
Propagatton Delay to a Logical "1" from Clock
to Output, tpd1
Vee == 5 OV, TA = 25°C, C
Propagation Delay to a Logical "0" from Clear
to Output
Vee = 5 OV, T A= 25°C, C = 50 pF
mHz
Minimum Clock Pulse Width
Vee'" 5 OV, TA == 25°C, C "" 50 pF
25
45
ns
Minimum Clear Pulse Width
Vee = 5 OV, T A = 25°C, C = 50 pF
30
45
ns
Minimum Time that SA Sa Data Must be Set-up
Prior to Clock Pulse, t,.,t .... P
Vee == 5 OV, TA == 25°C, C == 50 pF,
Clock Pulse Width = 50 ns
15
30
ns
Vee:: 5 OV, T A == 25° C, C = 50 pF,
Clock Pulse Width = 50 liS
-15
0
ns
Mimmum Time that SA
After Clock Pulse, t hold
Note 1
Unless otherwise specified, limits shown apply from _55°C to +125°C for the DM7570 and
the DM8570 Typical values apply to supply voltages of 5 OV and 25°C
Only one output should be Shorted at a time
aOe to +70°C for
Note 2
1-168
Sa Data Must be Held
c
Series 54/74
DM7573/DM8573 1024-bit field-programmable read only memory
general description
features
• Can be programmed In 1 sec (50% logical 1'so
50% logical O's)
• Pin compatible wfth SN54187/SN74187
• Can be programmed after being connected In a
system
• Outputs can be fully tested before programming
400mW
• Typical power dissipation
60 ns
• Propagation delay
logic and connection diagrams
BINARY
SELECT
m
(6)
Ao
(5)
JMEI""~"'~==r.:::r--t+-----T1-----,-f----,
MEMORY
ENABLE LMEZ<>l141
Pin
11BI~vcc
c
3:
UI
An additional feature of the DM7573/DM8573 IS
that its outputs can be tested in the logical "0"
state without permanently programming the memory. In order to place all outputs in the logical "0"
Az
"UI
"W
......
CO
state, a 9V level is applied to the most significant
address input, Pin 15. This feature will allow a
much more complete tGst to be made before a part
is shipped, thus minimizing customer returns.
The DM7573/DM8573 is a field-programmable
read-only memory organized as 256 four-bit
words_ Selection of the proper word is accomplished through the eight select Inputs. Two overriding memory enable inputs are provided; when
either or both of the enable inputs are taken to a
high state, all the outputs will be turned off. A
logical "1" has been built into each bit location. A
logical "0" can be programmed into any bit by
selecting the proper word, disabling the chip, and
applying a programming pulse to the proper
output.
A,
3:
PIn (8) ~ GND
Dual~ln-Line
Package
GND
TOP VIEW
1-169
"
W
absolute maximum ratingS(Note
1)
operating conditions
MIN
Supply Voltage
7.0V
Input Voltage
5.5V 112V on Pins 13, 141
Output Voltage
5.5V 125V for programmlngl
Storage Temperature ~ange
-65°C to +150o e
Lead Temperature (Soldenng, 10 sec)
300°C
Supply Voltage IVeel
DM7573
DM8573
Temperature IT AI
DM7573
PARAMETER
45
4.75
-55
DM8573
electrical characteristics(Note
MAX
5.5
Volts
5.25
Volts
+125
70
0
UNITS
°e
°e
2)
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Current
Vee = Max, Vo = 4.0V
Logical "0" Output Voltage
Vee = Min, 10 = 16 mA
Logical" 1" I nput Current
Vee = Max, V ,N = 2AV
Vee = Max, V ,N = 5.5V
40
1
/lA
mA
Logical "0" I nput Current
Vee = Max, V ,N = OAV
-1
mA
Supply Current
Vee = Max
110
mA
Input Clamp Voltage
Vee = Min, liN = -12 rnA
Propagation Delay to a Loglca!
"0" from Address to Output,
Vee = 5 OV
T A = 25°C
60
ns
Vee = 5.0V
28
ns
60
ns
28
ns
V
2.0
0.8
50
0.4
82
-1.5
V
/lA
V
V
tpdO
Propagation Delay to a Logical
"0" from Enable to Output,
TA = 25°C
tpdO
Propagation Delay to a Logical
"1" from Address to Output,
Vee = 5.0V
T A = 2.5°C
tpd1
Propagation Delay to a Logical
"1" from Enable to Output,
Vee = 5.0V
TA = 25°C
tpd1
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55° to +125°C temperature range for the DM7573 and
across the O°C to 70°C range for the DM8573. All typicals are given for Vee ~ 5.0V and T A = 25°C.
1·170
I
programming procedure
should be limited to 25V; the current should
be limited to 70 mAo Apply the pulse as
shown in the diagram. A reduction in cur·
rent of approximately 15 mA indicates the
bit is programmed.
The DM7573/DM8573 IS manufactured such that
the outputs are high for all addresses. To program
a logic zero (low output level), the following pro·
cedure should be followed:
1. Apply aVec voltage of 5.0V and select the
word to be programmed uSing address inputs
A7 - Ao.
4. To verify that the bit has been programmed,
apply a logic zero to both of the enable
Inputs and check for a low level on the pro·
grammed output.
2. Apply a high level (logic 1) to either or both
of the ENABLE Inputs (PinS 13 and 14).
5. Advance to the next output and/or word,
programming only one bit at a time.
3. Apply a programming pulse to the output
where a low level is desired. The voltage
Vcc=50V
_ tow::: 1 ms
,'----..Ji-------T
ADDRESS
{"
:
INPUTS.
"
---DUTY CYCLE <;50%---------l
l,.,SSI,';;;fiJ,lS
OPENOR{ME,
LOGIC 1
ME2
Programmmg Connections
Programming Pulse
board programming
The DM7573/DM8573 possesses added flexibility
in that It can be programmed after it has already
been connected In a system. Whether soldered to a
printed circuit board or socketed, if the procedure
described below is followed the units may be pro·
grammed even though their outputs are connected.
logical "1 ". Because the decoder outputs are
active-low, the ENABLE input of the device to be
programmed is operated at 6V. The other
ENABLE inputs reach 9V, normally a prohibited
level, but in this case the circuit was designed to
use the 9V to prevent the outputs from being
programmed.
As shown In the diagram the decoder used to
select the appropriate package must be operated at
voltage levels which are 6 volts higher than normal.
The outputs of the decoder therefore range between about 6V for a logical "0" and 9V for a
Although all common outputs receive the programming pulse, only the memory whose ENABLE input IS at the 6V level IS programmed.
Vee
r ____
15!L.. _ _ _ ...,
Vee PIN
OM751J1
OM8513
I ENABLE
I
I
'9V
I
~~A._I
DM7573!
OMB,)]
I Erl/ABLE
I
I
I
I
I
I
. . 1",----
DM7573!
OMB573
[ENABLE
I
I
L.----1----...J
1-171
Series 54/74
DM7574/DM8574 TRI-STATE®1024-bit
field-programmable read only memory
general description
ory. In order to place all outputs in the logical "0"
state, a 9V level is applied to the most significant
address input, Pin 15. This feature will allow a
much more complete test to be made before a part
is shipped, thus minimizing customer returns.
The DM7574/DM8574 is a fleld·programmable
read·only memory organized as 256 four·bit
words. Selection of the proper word IS accomplished through the eight select Inputs. Two overriding memory enable Inputs are provided; when
either or both of the enable inputs are taken to a
high state, all the outputs go to the high Impedance
state. A logical "1" has been bUilt Into each bit
location. A logical "0" can be programmed Into any
bit by selecting the proper word, disabling the
ChiP, and applYing a programming pulse to the
proper output.
features
•
•
Pin compatible with SN54187/SN74187
Can be programmed after being connected In a
system
• Outputs can be fully tested before programming
400mW
• Typical power diSSipation
60 ns
• Propagation delay
An additional feature of the DM7574/DM8574 IS
that its outputs can be tested in the logical "0"
state without permanently programming the memo
logic and connection diagrams
BINARY
SELECT
A,
(6)
AD
(5)
rMElo,'~'31==::::::r::)---r+----tt----r1----l
MEMORY
ENABlEtME2 <>114)
I'I~
(16) ~VCl:: Pm(B)"SND
OUTPUTS
Dual-In-Line Package
GND
TOPV'EW
1-172
absolute
maximum
ratings(Note 1)
operating
conditions
MIN
70V
55V (12Von PinS 13, 14)
55V (25V for programming)
Storage Temperature Range
_65°C to +150"e
Lead Temperature (Soldenng, 10 sec)
300°C
Supply Voltage
Input Voltage
Output Voltage
Su~ply
MAX
UNITS
Voltage (Vee)
DM7574
45
55
Volts
DM8574
475
525
Volts
Temperature (T A)
DM7574
-55
+125
"e
DM8574
0
70
°e
MAX
UNITS
electrical characteristiCS(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
V
Logical "0" Output Voltage
Vee = Mm, 10 = 16 mA
Logical "1" Input Current
Vee = Max, V ,N = 24V
Vee = Max, V ,N = 5 5V
40
1
MA
rnA
Logical "0" I nput Current
Vee = Max, Y'N = 04V
-1
mA
Supply Current
Vee=Max
110
mA
Input Clamp Voltage
Vee
Propagation Delay to a Logical
Vee = 50V
TA = 25°C
60
ns
Vee = 5 OV
TA = 25°C
28
ns
Vee = 5.0V
T A =25°C
60
ns
Vee = 5 OV
T A = 25°C
28
ns
"0" from Address to Output,
= Max I = -2.0 mA (DM7574)
ee
,0
-52 mA (DM8574)
~
V
20
0.8
2.4
V
V
04
82
-1.5
Mm, liN = -12 mA
V
V
tpdO
Propagation Delay to a Logical
"0" from Enable to Output,
tpdO
Propagation Delay to a Logical
"1" from Address to Output,
tpd1
Propagation Delay to a Logical
"1" from Enable to Output,
tpd1
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrlcal Characteristics" provides conditIOns for actual device operation
Note 2: Unless otherwise specified min/max limits apply across the _55 0 to +125°C temperature range for the DM7574and
across the O°C to 70 0 e range for the DM8574. All tYPlcals are given for Vee = 5 OV and T A = 25"'e
1-173
programming procedure
The DM7574/DM8574 IS manufactured such that
the outputs are high for all addresses. To program
a logic zero (low output level), the following procedure should be followed:
should be limited to 25V; the current should
be limited to 70 mAo Apply the pulse as
shown In the diagram. A reduction in cur·
rent of approximately 15 mA indicates the
bit IS programmed.
1. Apply aVec voltage of 5.0V and select the
word to be programmed using address Inputs
A7 - Ao·
2. Apply a high level (logic 1) to either or both
of the ENABLE Inputs (PinS 13 and 14).
4. To verify that the bit has been programmed,
apply a logic zero to both of the enable
inputs and check for a low level on the pro·
grammed output.
3. Apply a programming pulse to the output
where a low level IS desired. The voltage
5. Advance to the next output and/or word,
programming only one bit at a time.
Vee
~
5 DV
A,
ADDRESS {
INPUTS
:
•
DM7514/
DMB574
A,
OR {ME,
OPEN
LOGIC 1 ME2
f - - - - DUTY CYCLE <.50%,-----1
l,us:::;;t,=:;;:5,us
GND
Programming Pulse
Programming Connections
board programming
The DM7574/DM8574 possesses added flexibility
in that it can be programmed after it has already
been connected in a system. Whether soldered to a
printed circuit board or socketed, if the procedure
described below is followed the units may be programmed even though their outputs are connected.
logical "1 ". Because the decoder outputs are
active-low, the ENABLE Input of the device to be
programmed is operated at 6V. The other
ENABLE inputs reach 9V, normally a prohibited
level, but in this case the circuit was designed to
use the 9V to prevent the outputs from being
programmed.
As shown in the diagram the decoder used to
select the appropriate package must be operated at
voltage levels which are 6 volts higher than normal.
The outputs of the decoder therefore range between about 6V for a logical "0" and 9V for a
Although all common outputs receive the programming pulse, only the memory whose EN·
ABLE input is at the 6V level is programmed.
'00
, ____ .l:5L
II
I
Vcc P1N
SELECTED
OUTPUT-6V
'"
~"
DM1514f
DM1514
-"DM1514/
OM8614
IENABL
-"
'm'
I
I
I
I
I
I
I _..F\....
t---t-----Jt,il---~R--_....J
HIA8LE \~ME20(14)
=::~
OPTION 2
connection diagram
Dual-In-line Package
Oth'fDptlon,onm.mDry.nabl'iat~
ME,~
ME2 o-d.-.,.I-
OPTION 3
truth table
TABLE of Programmable Memory Enable OptIOns
OPTION
MEl
ME2
OUTPUTS
1
0
0
X
1
Normal
HIGH Impedance
HIGH Impedance
1
X
0
Normal
0
Normal
HIGH Impedance
HIGH Impedance
1
X
2
1
0
X
3
1
X
0
1
X
HIGH Impedance
HIGH Impedance
X'" don t care
TOPVIEW
1-187
I'
en
It)
absolute maximum ratings
00
(Note 1)
:E
C
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM7597
DM8597
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
.......
I'
en
It)
I'
:E
C
7V
5.5V
5.5V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
electrical characteristics (Note
2)
PARAMETER
CONOITIONS
~
.
TYP
MAX
UNITS
Logical "1" Input Voltage
Vee
Vee
Logical "0" Input Voltage
DM7597
DM8597
Vee ~ 4 5V
V ee -475V
Logical "1" Output Voltage
DM7597
DM8597
Vee
Vee
Logical "0" Output Voltage
DM7597
DM8597
Vee~45V
Third State Output Current
DM7597
DM8597
Vee ~ 5 5V
V ee -525V
Logical" 1" Input Current
DM7597
DM8597
Vee
Vee
~
5 5V
525V
VIN
DM7597
DM8597
Vee
Vee
~
5 5V
525V
Y'N ~ 55V
10
rnA
DM7597
DM8597
Vee~55V
V'N~04V
-10
rnA
~
4 5V
475V
MIN
DM7597
DM8597
4 5V
475V
475V
Vee
20
V
08
10
-2 rnA
=
10~-52rnA
10
V
16 rnA
~
Va
24
~
04
2 4V
Vo~04V
~
V
2.4V
V
40
-40
IlA
IlA
40
IlA
Logical "0" Input Current
Output Short Circuit Current
(Note 31
DM7597
DM8597
DM7597
DM8597
Supply Current
Input Clamp Voltage
DM7597
DM8597
525V
Vee
Vee~55V
VLe ·525V
Vee~55V
525V
Vee
Vee~45V
V ee -475V
Propagation Delay to a Logical "0" from
Vee~50V
Address to Output,
TA = 25°C
tpdO
Propagation Delay to a Logical "1" from
Vee
Address to Output,
TA
tpdl
=
~
5 OV
25°C
Delay from Enable to High Impedance
Vee~50V
State (from Logical "1" Levell,
TA ~ 25°e
tlH
Delay from Enable to High Impedance
Vec~50V
State (from Logical "0" Levell, tOH
TA ~ 25"e
Delay from Enable to Logical "1" Level
(from High Impedance State), tH1
Vee ~ 5.0V
TA =' 25°C
Delay from Enable to Logical "0" Level
Vee~50V
(from High Impedance State), tHO
TA ~ 25'e
Vo
~
OOV
All Inputs at GND
-20
75
110
rnA
V
39
60
ns
31
60
ns
30
ns
10
ns
30
ns
30
ns
Note 2: Unless otherWise speCified min/max limits apply across the _55°C to +125°C temperature
range for the DM7597 and across the O°C to 70°C range for the DM8597. All tYPlcals are given for
Vee ~ 5.0V and T A ~ 25'e
1-188
rnA
-1 5
liN"" -12 mA
Note 1: " Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits The table of "Electrical Characteristics" prOVides conditions
for actual deVice operation
Note 3: Only one output at a time should be shorted.
-70
ordering instructions
Programming Instructions for the DM7597 or
DM8597 are solicited In the form of a sequenced
deck of 32 standard 80-column data cards providing the Information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-auto·
mated design (CAD) program. This single run also
generates mask and test program data, therefore,
verification of the truth table should be completed
promptly.
Each card in the data deck prepared by the pur·
chaser Identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.
10·13
14
15-18
19
20·23
24
25-28
29
30-33
34
35-38
39
40·43
supplementary ordering data
44
Submit the following information with the data
cards:
45-48
49
a) Customer's name and address
b) Customer's purchase order number
50-51
c) Customer's drawing number.
52
53-55
data card format
56
Column
1· 3
4
5- 7
8· 9
57-58
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H ~ hlghlevel output, L ~ low·level output, X ~
output irrelevant.
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H", "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L",or"X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-Justified Integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation repre·
senting the current month.
Blank
Punch the last two digits of the current
year.
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
60-61
Punch "DM"
Punch a "-" (MinUS sign)
62·65
Punch 7597 or 8597
Punch a right-justified integer representing
the binary Input address (007·255) for
the last set of outputs described on the
card.
66· 70
Blank
71
Punch 1, 2, or 3 for memory enable
option deSired (assumed 1 if not punched)
59
u
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Blank
1.1RQ
co
en
La
co
:E
~s
Series 54/74
c
.......
co
en
La
"'"
:E
c
®
DM7598/DM8598 TRI-STATE
256-bit read only memory
general description
The DM7598/DM8598 is a customer programmed
256-blt read-only memory organized as 32 8-blt
words. A five-bit input code selects the appropriate
word which then appears on the eight outputs. An
enable input overrides the select Inputs and blanks
all outputs.
Although the DM7598/DM8598 can have its outputs tied together for word-expansion, the outputs
are not open-collector, but rather the famillartotempole output with the capability of being placed
in a "third-state". This unique three state concept
allows outputs to be tied together and then connected to a common bus line. Normal TTL outputs
cannot be connected due to the low-Impedance
logical "1" output current which one device would
have to sink from the other. If however, on all but
one of the connected devices both the upper and
lower output transistors are turned off, then the
one remaining device in the normal low Impedance
state will have to supply to or sink from the other
devices only a small amount of leakage current.
ThiS IS exactly what occurs on the DM75981
DM8598.
A typical system connection demonstrating expansion to greater numbers of words IS shown in Figure 1. While It IS true that In a TTL system opencollector gates could be used to perform the logic
function of these three-state elements, neither
waveform Integrity nor optimum speed would be
achieved. The low output impedance of the
DM7598/DM8598 provides good capacitance drive
capability and rapid transition from the logical
"0" to logical" 1" level thus assuring both speed
and waveform Integrity.
It IS possible to connect as many as 128 DM8598s
to a common bus line and stili have adequate drive
capability to allow fan out from the bus. The
example shown in Figure 2 Indicates how thiS
guarantee can be made under worst-case conditions_
Figure 3 indicates how multiple packages can be
used to Increase word length.
features
•
•
•
•
•
Pin compatible with SN5488/SN7488
Organized as 32 8-bit words
Full Internal decoding
30 ns typical access time
350 mW typical power dissipation
•
•
I nput clamp diodes
DeSigned for bus-organized systems
• Strobe override
logic and connection diagrams
....
110lV
....
~
81NARY
SELECT
I"v
Dual-In-Llne Package
I-f;::
, ~2V
" 1
V
{13)V
I"
V
1141
4>
{lSI
"
V
PROGRAMMING
'"
SHOWlll
1-Hl0
o
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
3:
...,
(Note 1)
OperatIng Temperature Range DM7598
7V
55V
55V
-55'C to +125'C
DM8598
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-65'C to +150'C
300'C
CO
.........
o
3:
O°C to +70°C
electrical characteristics
CO
UI
CD
(Note 2)
PARAMETER
CO
MIN
CONDITIONS
LogIcal "1" Input Voltage
DM7598
DM8598
Vee=45V
Vee = 4 75V
LogIcal "0" Input Voltage
DM7598
DM8598
Vee = 4 5V
Vee - 4 75V
LogIcal "1" Output Voltage
UI
CD
DM759~_ ~_=45V
TYP
MAX
V
20
08
~=-2~
10 = -5 2 rnA
UNITS
V
V
24
DM8598
Vee = 4 75V
Logical "0" Output Voltage
DM7598
DM8598
Vee = 4 5V
ThIrd State Output Current
DM7598
DM8598
Vee=55V
V ee - 525V
Vo = 24V
Vo = 04V
±40
±40
IJ.A
IJ.A
Address Inputs
DM7598
DM8598
Vee = 55V
V ee - 525V
V ,N = 24V
40
IJ.A
Enable Input
~1\'I75_~ -+.<:S_~~
VIN
24V
80
IJ.A
Any Input
DM7598 ~",e=55V
DMS!598 Vee = 525V
V ,N = 5 5V
1
rnA
Address Inputs
DM7598
DM8598
V ,N =04V
-1 6
rnA
Enable Input
DM7598 _yee=55V
DM8598
Vee = 525V
VIN
= 0 4V
-32
rnA
DM7598
Vee = 55V
---DM8598 Vee~5V
Vo = OV
Supply Current
DM7598 ~",e = 55V
DM8598 Vee=525V
Inputs Gfounded
Input Clamp Voltage
DM7598
DM8598
Vee = 4 5V
Vee - 4 75V
liN = -12 rnA
Output Vee Clamp Voltage
DM7598
DM8598
Vee= 5 5V
Vee - 525V
10
Output Ground Clamp Voltage
DM7598
DM8598
Vee = 5 5V
Vee - 525V
V cc -475V
04
lo=+12mA
V
LogIcal "1" Input Current
DM8598
Vee = 5 25V
=
II
Logical "0" Input Current
Output Short CirCUit Current
(Note 3)
Vee= 55V
V ee -525V
-20
70
-70
rnA
99
rnA
-15
V
rnA
Vee
+1 5
V
10 = -12 rnA
-15
V
= +12
Propagation Delay to a Logical "0" from
Address to Output, tpdO
Vee= 50V
TA = 25'C
29
50
ns
Propagation Delay to a Logical "1" from
Address to Output, tpdl
Vec=50V
TA = 25'C
33
50
n,
Delay from Enable to High Impedance
State (from Logical "1" Level),t1H
Vee=50V
TA = 25'C
C L = 5 pF
13
20
n'
Delay from Enable to High Impedance
State (from Logical "0" Level). tOH
V ee =50V
TA = 25'C
CL = 5 pF
24
36
ns
Delay from Enable to Logical "1" Level
(from High Impedance State), tHl
Vee=50V
TA = 25'C
CL = 50 pF
16
25
ns
Delay from Enable to Logical "0" Level
(from High Impedance State), tHO
TA
Vee=50V
= 25°C
C L = 50 pF
26
40
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits The table of "Electrical Characteristics" prOVides conditions
for actual deVice operation
Note 2: Unless otherWise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM7598 and across the O°C to 70°C range for the DM8598 All tYPlcals are given for
VCC = 50V and TA = 25°C
Note 3: Only one output at a time should be shorted.
1-191
co
en
It)
typical applications
co
::!
o
.........
co
OUTPUTS
OFO THEA
MEM ORIES
LINE
en
'"'1
It)
"
::!
1I I
Y,
o
r
ME
Y2
YJ
v.,
V.
Yo
Y,
v,
Va
r--<
OM1598/DM8598
,
B
C
0
J'"
III
V2
V3
Yo
y~
V.
Y,
VB
DM7598/0M8598
ME
,
E
B
C
0
E
11
}m
INARY
SELE CT INPUTS
OFO THER
MEM DRIES
TO ENABLE INPUTS Of OTHER MEMORIES
0
! t. t ! ,
, , ,
6
5
B
9
16
12
11
DM541541DM74154
,
J
ABC
0
E
B
C
I
I
0
G,
III1
H
I
J
F
BINARY SELECT REGISTER
FIGURE 1. ExpanSIon to Larger Word Capacity
GATED INTO
LQWIMPEDANCE
lOGICAl'1
STATE
GATED INTO
HIGH IMPEDANCE
STATE
GATED INTO
HIGH IMPEDANcE
STAH
OTHER OM75981DMaS98
OUTPUTS
FIGURE 2.
IlM759BiDM8598
ABC
0
E
BINA.RYSHfCT
REGISHR
FIGURE 3.
1-192
G,
!!!
13
1415
c
s::
.....
DM7598AA TRUTH TABLE
C1I
CD
CO
A special pattern has been generated for the DM7598/DM8598 The AA pattern provides a sine table The 5-blt
Input code linearly diVides 90° Into 32 equal segments Each 8-blt output IS therefore the sine of the angle
applied
.......
C
s::CO
C1I
CD
EXAMPLE Input 11010 means 26/32 of 90°, or about 73° The corresponding output 11110100 Indicates
(1/2 + 114 + 1/8 + 1/16 + 1/641 or about 95, which IS close to the sine of 73° Rounding-off has not been
employed, since without rounding-off It
The truth table
IS
IS
INPUTS
WORD
CO
possible to extend the accuracy with additional ROMs
shown
OUTPUTS
BINARY SELECT
ENABLE
E
D
C
B
A
ME
YB
Y7
Y6
Y5
Y4
Y3
Y2
Yl
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
2
0
0
0
1
0
0
0
0
0
1
1
0
0
1
3
0
0
0
1
1
0
0
0
1
0
0
1
a
1
4
0
0
1
0
0
0
0
0
1
1
0
0
0
1
5
0
0
1
0
1
0
0
0
1
1
1
1
1
0
6
0
0
1
1
0
d
0
1
0
0
1
0
1
0
7
0
0
1
1
1
0
0
1
0
1
0
1
1
0
8
0
1
0
0
0
0
0
1
1
0
0
0
0
1
9
0
1
0
0
1
0
0
1
1
0
1
1
0
1
10
0
1
0
1
0
0
0
1
1
1
1
0
0
0
11
0
1
0
1
1
0
1
0
0
0
0
0
1
1
12
0
1
1
0
0
0
1
0
0
0
1
1
1
0
13
0
1
1
0
1
0
1
0
0
1
1
0
0
0
14
0
1
1
1
0
0
1
0
1
0
0
0
1
0
15
0
1
1
1
1
0
1
0
1
0
1
0
1
1
16
1
0
0
0
0
0
1
0
1
1
0
1
0
1
17
1
0
0
0
1
0
1
0
1
1
1
1
0
1
18
1
0
0
1
0
0
1
1
0
0
0
1
0
1
19
1
0
0
1
1
0
1
1
0
0
1
1
0
1
20
1
0
1
0
0
0
1
1
0
1
0
1
0
0
21
1
0
1
0
1
0
1
1
0
1
1
0
1
1
22
1
0
1
1
0
0
1
1
1
0
0
0
0
1
23
1
0
1
1:
1
0
1
1
1
0
0
1
1
1
24
1
1
0
0
0
0
1
1
1
0
1
1
0
0
25
1
1
0
0
1
0
1
1
1
1
0
0
0
1
26
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
27
1
1
0
1
1
0
1
1
1
1
1
0
0
28
1
1
1
0
0
0
1
1
1
1
1
0
1
1
29
1
1
1
0
1
0
1
1
1
1
1
1
0
1
30
1
1
1
1
0
0
1
1
1
1
1
1
1:
0
31
1
1
1
1
1
0
1
1
1
1
1
1
1
1
All
X
X
X
X
X
1
H,-Z
H,-Z
H,-Z
HI'Z
HI-Z
HI-Z
HI-Z
HI-Z
x = Don't Care
1-193
TRUTH TABLE IORDER BLANK
The output levels are not shown on the truth table since the customer specifies the output condition he deSIres
at each of the eight outputs for each of the 32 words (256 bits) The customer does this by filling out the
Truth Table on this data sheet, and sending It In with his purchase order.
INPUTS
WORD
0
OUTPUTS
E·,b,BLE
BINARY SELECT
E
D
C
B
A
ME
0
0
0
0
0
0
1
0
0
a
a
1
a
2
1
a
0
0
1
1
0
1
0
a
0
5
0
1
0
1
0
6
a
a
a
a
a
a
0
4
a
a
a
1
1
0
0
a
3
7
0
0
1
1
1
8
a
1
0
0
0
0
9
0
1
a
0
1
0
10
0
1
0
1
0
1
a
1
0
1
0
11
12
0
1
1
0
0
13
0
1
1
0
14
0
1
1
1
0
1
0
15
0
1
1
1
1
0
16
1
0
0
1
0
1
0
18
1
0
0
19
1
0
0
0
0
1
0
17
0
0
0
1
1
20
1
0
1
0
0
0
0
0
21
1
1
22
1
0
0
23
1
a
1
24
1
1
0
0
1
1
0
25
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
a
0
0
0
0
1
0
1
0
0
1
1
1
30
1
1
1
Y4
Y3
Y2
Yl
HI·Z
HI·Z
HI·Z
HI·Z
HI-Z
HI-Z
H,-Z
HI-Z
0
0
0
1
1
Y5
0
1
29
Y6
0
26
28
Y7
0
27
0
1
1
YB
31
1
1
1
1
1
0
All
X
X
X
X
X
1
x = Don't Care
Notice ThiS 'heet must be co""pleted and signed by an authorIZed representative of the customer's company before an
order can be entered
To be used by National only
AuthorIZed Representative
Date
_ _ _ _ _ _ _ _ Part Number
________ 5
a
Number
Company
_ _ _ _ _ _ _ _ Date Received
DeSIred Part
1-194
o
DM7598
o
DM8598
II1S
Series 54/74
DM7599/DM8599 TRI-STATE®
64-bit random access read/write memory
general description
The DM7599/DM8599 is a fully decoded 64-bit
RAM organized as 16 4-bit words. The memory
IS addressed by applying a binary number to the
four Address inputs. After addressing, information
may be either written Into or read from the
memory. To write, both the Memory Enable and
the Write Enable inputs must be in the logical "0"
state. Information applied to the four Write Inputs
will then be written into the addressed location.
To read information from the memory the Memory Enable input must be in the logical "0" state
and the Write Enable Input in the logical" 1" state.
I nformatlon will be read as the complement of
what was written Into the memory. When the
Memory Enable input IS in the logical" 1" state,
the outputs will go to the high-impedance state.
This allows up to 128 memories to be connected
to a common bus-line without the use of pull-up
resistors. All memories except one are gated Into
the high-Impedance while the one selected memory exhibits the normally totem-pole low impedance output characteristics of TTL.
features
•
Series 54/74 compatible
•
Same pin-out as SN5489/SN7489
•
Organized as 16 4-bit words
•
Expandable to 2048 4-bit words without additional resistors (DM8599 only)
•
Typical access from chip enable
•
Typical access time
•
Typical power diSSipation
20 ns
28 ns
400mW
block diagram
DATA
INPUTS
connection diagram
truth table
Dual-In-Line Package
MEMORY
WRITE
ENABLE
ENABLE
0
0
0
1
Write
HI-Z State
Read
Complement of Data
Stored In Memory
1
X
Hold
HI"Z State
OPERATION
OUTPUTS
1_1QJ::.
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Operating Temperature Range
7V
55V
55V
Time that two bus-connected devices may be In
opposite low Impedance states simultaneously
electrical characteristics
CONDITIONS
MIN
Logical "1" Input Voltage
DM7599
DM8599
Vee "4SV
Vee" 4 75V
Logical "0" Input Voltage
DM7599
DM8599
Vee'" 4 5V
Vee 475V
Logical "1" Output Voltage
DM7599
DM8599
V ec ==45V
Vee 475V
10 '" -2mA
10 "'-5 2 mA
Logical "0" Output Voltage
DM7599
DM8599
Vee =45V
V ee - 4 7SV
10
Third State Output Current
DM7599
DM8599
Vee=55V
Vee 525V
Logical "1" Input Current
DM7599
DM8599
Vee=55V
V ee -525V
DM7599
DM8599
Vee "55V
Vee S 25V
DM7599
DM8599
Vee = 5 SV
V ee -525V
DM7599
DM8599
Vec=55V
Vee 525V
Supply Current
DM7599
DM8599
Vec"'55V
Vee" 525V
All Inputs at GND
Input Clamp Voltage
DM7599
DM8599
Vee = 4 5V
Vee 475V
liN = -12 mA
Output Short Circuit Current
(Note 3)
Propagation Delay to a Logical "0" from
Address to Output,
tpdQ
Propagation Delay to a Logical "1" from
Address to Output, t p d1
Delay from Memory Enable to High
Impedance State (from Logical "1"
Level), t1H
TVP
MAX
08
=
V
04
12 mA
Vo = 0 4V
±40
Vo = 2 4V
±40
rnA
Y'N =
a 4V
-16
-30
80
rnA
120
rnA
-15
28
45
27
45
12
20
Vee= SOV
2SoC
Vee",SOV
TA == 2SoC
21
30
Delay from Memory Enable to
Logical "1" Level (from High
Impedance State), tH1
Vce=50V
TA = 2SoC
14
20
Delay from Memory Enable to
Logical "0" Level (from High
Impedance State), tHO
Vce=SOV
T A '" 25°C
19
30
40
23
Setup Time, Data
0
-15
Hold Time, Data
0
-14
Setup Time Address
0
-17
Hold Time, Address
5
-7
Sense Recovery Time
42
Note" "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electrical CharacterIStics" prOVides conditions
for actual device operation
Note 2 Unless otherwJSe speCified min/max limits apply across the -55°C to +125°e temperature
range for the OM7599 and across the oOe to 700e range for the DM8599 All typlcals are given
for Vee
50V and TA
25°e
Note 3 Only one output at a time should be shorted
=
rnA
-70
Delay from Memory Enable to High
Impedance State (from Logical "0"
Level), toH
=
V
40
Vee=SOV
T A = 2SoC
=
v
v
24
24
Vee"" 50V
T A = 25°C
TA
UNITS
v
20
Write Enable Pulsewldth, twp
1·196
300'C
(Note 2)
PARAMETER
Logical "0" Input Current
_55°C to +125°C
cOe to +70°C
DM7599
DM8599
Lead Temperature (Soldering, 10 sec)
Indefinite
V
ns
ns
ns
60
c
~s
s:....
Series 54/74
00
o
o
.......
c
s:
00
DM7800/DM8800 dual voltage translator
00
general description
features
The DM7800/DM8800 are dual voltage translators
designed for interfacing between conventional TTL
or DTL voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices The design allows the user a wide latitude
In his selection of power supply voltages, thus providing custom control of the output sWing. The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required.
•
o
o
31 volt (max) output swing
•
1 mW power dissipation in normal state
•
Standard 5V power supply
•
Temperature range:
DM7800
DM8800
•
_55°C to +125°C
O°C to +70°C
Compatible with all MOS devices
schematic and connection diagrams
A1
R2
20K
45K
D
Metal Can Package
....._ _~H_OUnUT){
OUTPUT X
L...-_ _ _
~_v,
typical applications
Bipolar to MOS Interfacing
4·Channel Analog Switch
1 1
r'" - - - ' --,1
t5V
+10V
r------I
I
MM451
ANALOGINPUT2
I
I
I
DTl
I
"
Tn
I
I
INPUT
LEVelS
I
SWITCH
4'_-"-W-....
3---
A/tIALOGINPUT4
r
II
.J
,J"
I
I
,n
r ---~Ll-
ANAlOGINPuTt·1
I
OR
MOSSHIFT
~
AfGI$TER
TTL
I
DM1&OO
INPUT~~
1--- T
tEVEtS~~
L
J
':'"
-IOV
I
I
I
ANAtOGOUTPUT
L _____
I
-l
*Amll"I"!luIIWlth,nthe,angf
01 +8 ,0115 ,o--$.oU,
1-197
o
o
00
CO
absolute maximum ratings
:IE
Q
.......
Vee Supply Voltage
7.0V
V 2 Supply Voltage
-30V
V 3 Supply Voltage
+30V
V 3 ,V 2 Voltage Differential
40V
I nput Voltage
5.5V
-65°C to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
DM7800
O°C to 70°C
DM8800
Lead Temperature (Soldering, 10 sec)
300°C
o
o
CO
....
:IE
Q
electrical characteristics
(Note 1)
PARAMETER
CONDITIONS
=4.5V
=4.75V
MIN
TVP
(Note 4)
MAX
UNITS
Logical" 1" I nput Voltage
DM7800
DM8800
Vee
Vee
Logical "0" I nput Voltage
DM7800
DM8800
Vee =4.5V
Vee - 4.75V
Logical "1" Input Current
DM7800
DM8800
Vee = 5.5V
Vee = 5.25V
V ,N = 2.4V
5
IlA
Logical" 1" I nput Current
DM7800
DM8800
Vee= 5.5V
Vee - 5.25V
V ,N
= 5.5V
1
mA
Logical "0" I nput Current
DM7800
DM8800
Vee = 5.5V
Vee - 5.25V
V ,N = O.4V
-0.4
mA
Output Leakage Current (Note 2)
DM7800
DM8800
Vee = 5.5V
Vee - 5.25V
V ,N
10
IlA
20.0
kn
V 2 + 2.0
V
Output Collector Resistor
2.0
V
0.8
=0.8V (Note 5)
TA = 25°C
Logical "0" Output Voltage
DM7800 Vee = 4.5V
DM8800 Vee = 4.75V
V ,N = 2.0V (Note 5)
Power Suppl y Cu.rent
Logical "0" (Note 3)
(Each Gate)
DM7800 Vee = 5.5V
DM8800 Vee = 5.25V
V ,N
Power Supply Current
Logical "1" (Note 3)
(Each Gate)
DM7800
DMBBOO
V ,N = OV
Vee = 5.5V
Vee = 5.25V
--0.2
11.5
= 4.5V
16.0
V
0.85
1.6
mA
0.22
0.41
mA
Transition Time to Logical "0" Output
TA = 25°C
C = 15 pF (Note 6)
25
70
125
ns
Transition Time to Logical" 1" Output
TA = 25°C
C = 15 pF (Note 7)
25
62
125
ns
Noto 1: Minimax limits apply across the guaranteed temperature range of -55°C to +125°e for the DM7800 and oOe to +70o e
for the DM8800 unless otherwISe speCified.
Note 2: Current measured IS drawn from V3 supply
Note 3: Current measured is drawn from Vee supply.
Noto 4: All tYPical values are measured at TA = 25°C with Vee = 5.0V, V2 = -22V, V3 = +8V.
Noto 5: SpeCification applies for all allowable values of V2 and V3.
,
Note 6: Measured from 1.5V on mput to 50% level on output.
Note 7: Measured from 1.5V on Input to logic "0" voltage, plus 1V.
1-198
c
s:
~
CO
o
o
theory of operation
.......
C
The two input diodes perform the AND function
on TTL or DTL input voltage levels. When at least
one input voltage IS a logical "0", current from Vee
(nominally 5.0V) passes through R 1 and out the
Input(s) which is at the low voltage. Other than
small leakage currents, this current drawn from Vee
through the 20 kQ resistor is the on Iy source of
power dissipation in the logical "1" output state.
When both Inputs are at logical" 1" levels, current
passes through R1 and diverts to transistor 0 1 , turnIng it on and thus pulling current through R 2 . Current is then supplied to the PNP transistor, O 2 The
voltage losses caused by current through 0 1 , D3 ,
and O 2 necessitate that node P reach a voltage sufficient to overcome these losses before current begins to flow. To achieve this voltage at node P, the
Inputs must be raised to a voltage level which is one
diode potential lower than node P. Since these levels
are exactly the same as those experienced with conventional TTL and DTL, the Interfacing with these
types of CirCUits is achieved.
Transistor O 2 provides" constant current switching" to the output due to the common base connection of O 2 , When at least one input is at the
logical "0" level, no current is delivered to O 2 : so
that its collector supplies essentially zero current
to the output stage. But when both Inputs are raISed
to a logical "1" level current is supplied to O 2 ,
Since .thIS current IS relatively constant, the collector of O 2 acts as a constant current source for the
output stage. Logic inverSion IS performed since
logical" 1" Input voltages cause current to be supplied to O 2 and to 0 3 And when 0 3 turns on the
output voltage drops to the logical "0" level
CO
o
o
The reason for the PNP current source, O 2 , is so
that the output stage can be driven from a high
Impedance. ThIS allows voltage V 2 to be adjusted
In accordance with the application. Negative voltages to -25V can be applied to V 2 Since the output will neither source nor sink large amounts of
current, the output voltage range is almost exclusively dependent upon the values selected for V 2
and V3 .
Maximum leakage current through the output transistor 0 3 is specified at 10 JlA under worst-case
voltage between V 2 and V 3. This will result In a
logical "1" output voltage which is 0.2V below V 3 .
likewISe the clamping action of diodes D 4 , D s, and
D6 , prevents the logical "0" output voltage from
falling lower than 2V above V 2, thus establIShing
the output voltage swing at typically 2 volts lessthan the voltage separation between V 2 and V 3.
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. The
range of operation for power supply V 2 is shown
on the X axis. It must be between -25V and -8V.
The allowable range for power supply V 3 is governed by supply V 2. With a value chosen for V 2, V 3
may be selected as any value along a vertical line
passing through the V 2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.
s:CO
~
V';:
OPERATING
5
5
15
10
RE~":N
~:o
V'17-: -5
-
-15
- -20
-
~25
1-199
II
CD
o
CO
CO
Series 54/74
:E
Q
.......
CD
o
CO
"'"
:E
DM7806/DM8806 high speed MOS to TTL level converter
Q
general description
features
The DM7806/DM8806 IS a high speed MOS to
TTL level converter. This circuit acts as an Inter·
face level converter between MOS & TTL logic
devices. It consists of two 1'lnput converters with
common strobe input to Inhibit "0" entry when
strobe is high. It allows parallel entry when strobe
is low and the internal latch IS preset by the com·
mon preset input. TRI·STATE@ output logic IS
Implemented In this circuit to facilitate high speed
time sharing of decoder·drivers, fast random·access
(or sequential) memory arrays, etc.
•
Very low output Impedance - high drive cap·
ability
•
High Impedance output state wh Ich allows
many outputs to be connected to a common
bus line
•
Average power dissipation 110 mW per con·
verter
logic and connection diagrams
Dual·1 n·line and Flat Packago
IN,
(CURRENT INPUT)
OUTPUT A
14 Vee
13 OUTPUTB
I.,
(CURRENT INPUT)
12
OISABL~D
OUTPUT B
11
NC
10 GNO
TOP VIEW
PRESET
truth table
IN AOR B
ST
P
0
1
1
1
1
1
1
X
1
0
1
X
1·200
0
0
X
0
0
0
0
0
1
QA OR Q B
1
1
0
1
H,·Z
9
INPUT B
8
GND
c
absolute maximum ratings
~
operating conditions
(Note 1)
"o
CD
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Supply Voltage (Vee)
OM780S
OM880S
7V
55V
5.5V
-S5°e to 1500 e
300 0 e
Temperature (T A)
OM780S
OM8806
MIN
MAX
UNITS
45
475
55
525
V
V
C
-55
0
+125
70
°e
°c
CD
CD
0)
.......
~
o
0)
electrical characteristics
(Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Current Pin 6, 9
Vee"" Min
Logical "0" Input Current Pin 6, 9
Vee
= Min
Logical "1" Input Voltage
Vee
= Min
Logical "0" Input Voltage
Vee
= Min
MIN
TYP
MAX
500
UNITS
J-IA
200
J-IA
V
20
8
V
04
V
V
Logical "1" Output Voltage
Vee = Min, lOUT
=
Logical "0" Output Voltage
Vee::: Mm, lOUT
= 16 mA
Third State Output Current
Vee = Max, Vo = 2 4V
Vcc=Max,Vo=04V
40
-40
J-IA
IlA
Logical" 1" I nput Current
Vee = Max, VIN
Vee = Max, VIN
= 2 4V
= 55V
40
1
IlA
rnA
logical "0" Input Current
-16
rnA
40
rnA
-15 mA
Vee
= Max, VIN = 0 4V
Supply Current
Vee
= Max, V IN(OISABLE) = 2V. Other
Input ClafTlP Voltage
Vee
= Min,
Output ShOft Circuit Current
Vee == Max, Vo
'iN
24
Inputs
= OV
= -12 rnA
= OV
(Note 3)
-15
DM7806
DM8806
-20
-18
-70
-70
V
rnA
rnA
(See Figure 1)
17
25
ns
Vee = 5 OV
TA = 25°C
(See Figure 1)
22
32
ns
Delay from Disable Input to High Impedance
State (from Logical ',1" Levell, t1H
Vee=50V
TA = 25°C
(See Figure 2)
7
11
ns
Delay from Disable Input to High Impedance
State (from Logical "0" Level), tOH
Vee=50V (See Figure 3)
17
25
ns
TA
Delay from Disable Input to Logical "1"
level (from High Impedance State), tH1
(See Figure 2)
9
14
'JS
TA
Delay from Disable I nput to logical "0"
level (from High Impedance State), tHO
Vec=50V
TA = 25°C
(See Figure 3)
135
16
ns
Vee=50V
Propagation Delay to a Logical "0" from
STROBE to Output, tds
TA "" 25°C
Propagation Delay to a Logical" 1" from
Preset to Output, tdp
= 25°C
Vee=50V
= 25°C
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVice should be operated at these limits The table
of "Electrtcal Characteristics" proVides conditions for actual deVice operation
Note 2: Unless otherwise specified mm/max limits apply across the _55°C to +125°C temperature range for the DM7806
and across the 0° e to 70° e range for the OM880S All tYPlcals are given for Vee = 5 OV. T A = 25° e.
Note 3' Only one output at a time should be shorted
1-701
NN
""" ....
coco
coco
:E:E
Cc
.......
;:::N
co ....
COCO
I""-
:E:JE
~c
o
....
.
CO;:::
COCO
:E CO
c:E
c
......
....
....
CO
I""-
:E
Series 54/74
DM7810/DM8810 quad 2-input TTL·MOS interface gate
DM7811/DM8811 quad 2-input TTL-MOS interface gate
DM7812/DM8812 TTL-MOS hex inverter
general description
These Series 54/74 compatible gates are high out:
put voltage versions of the DM5401/DM7401
(SN5401/SN7401), DM5403/DM7403
(SN 5403/SN 7403), and D M 5405/DM7405
(SN5405/SN7405). Their open-collector outputs
may be "pulled-up" to +14 volts In the logical "1"
state thus providing guaranteed Interface between
TTL and MOS logic levels.
c
In addition the devices may be used in applications
where I t IS desl rable to drive low current relays or
lamps that require up to 14 volts.
schematic and connection diagrams
r-........-.............Ov~
4K
" " " " " " " " , - " " " " " " - - 0 v"
18K
OUTPUT
INPUT
INPUTS
OUTPUT
0-;4-......
"
.........-_--0 ...
' - - -....-0 •••
DM7810/DM8810, DM7811/DM8811
DM7812/DM8812
Dual-I n-Llne Package
Dual-ln-.Line and Flat Package
•••
TOP VIEW
TOP VIEW
DM7811/DM8811
DM7810/DM8810
v,
14
Dual-tn-Line and Flat Package
13
12
11
10
TOPVIEW
DM7812/DM8812
1-702
•••
.N•
cc
absolute maximum ratings
operating conditions
7V
55V
14V
-65'e to +150'e
300'e
Vee
Input Voltage
Output Voltage
Storage Temperature Range
Lead TEmperature (Soldenng, 10 sec)
S:S:
-..J-..J
Supply Voltage (Vee)
DM78XX
DM88XX
MIN
MAX
UNITS
475
475
525
525
V
V
-55
0
+125
70
'e
'e
Temperature (T A)
DM78XX
DM88XX
........
.... 0
(Xl (Xl
.................
Cc
S:s:
........
.... 0
(Xl (Xl
(Xl (Xl
c
electrical characteristics
s:-..J
....
N
(Xl
(Note 1)
........
PARAMETER
CONOITIONS
MIN
TYP
MAX
-15
UNITS
(Xl
(Xl
V
Input Diode Clamp Voltage
Vee = 50V, T A = 25°C
liN = -12 mA
Logical "1" Input Voltage
Vee
=
Logical "0" Input Voltage
Vee
= Min
Logical "1" Output Current
Vee = Min
V OUT = lOV
Logical "1" Output Breakdown
Voltage
Vee = Min, V ,N = OV
lOUT = 1 mA
Logical "0" Output Voltage
Vee = Min, V IN = 2.0V
IOUT=16mA
Logical "1" Input Current
Vee = Max, V IN = 2.4V
40
Logical "1" Input Current
Vee = Max, V IN = 5 5V
1
mA
Logical "0" Input Current
Vee = Max, V ,N = O.4V
-16
mA
Supply Current - Logical "0"
(Each Gate)
Supply Current - Logical "1 "
(Each Gate)
Propagation Delay Time to a
Logical "0", tpdQ
Vee = Max, V ,N = 5 OV
3.0
5.1
mA
Vee = Max, V ,N = OV
1.0
1.8
mA
Vee = 50V, TA = 25°C
COUT = 15 pF, RL = lk
4
12
18
ns
Propagation Delay Time to a
Logical "1", tpdt
Vee = 5.0V, T A = 25°C
C OUT = 15 pF, RL = lk
18
29
45
ns
N
20
Min
V
08
V ,N =08V
V IN = O.OV
250
40
V
flA
flA
14
V
04
V
flA
Note 1: Unless otherWise specified minImax limits apply across the _55 D C to +125 D C temperature range for the DM78XX and
across the oDe to 70 0e range for the OM88XX All tYPlcals are given for Vee;::; 5 OV and T A = 25 DC
typical applications
+10V
3K
+12V
75K
I.
GROUND
L....jC>--....--jINPUT
DM8810, DM8811, DM8812
C
s:
....
l
CLOCK
1
I.
L....jC>--....--ItINPUT
-!.
":"
+10V--,
OMS810, OM881t DM8S12
ruse MOS shift register
(Example MM506)
+Vl
-V2
I
NSC MaS ROM
(ExampIEMM521)
Note Normnlvoltagesapplred
to MOSshlftreglstershave
been shifted by+l0Volts
L--6V
forthlsapphcatlOll
1·203
...
en
00
00
Series 54/74
~
c
.......
...
en
00
"'~"
c
DM7819/DM8819 quad 2-input TTL-MOS AN 0 gate
general description
The DM7819 IS the high output voltage version of
the SN5409. Its open-collector outputs may be
"pulled-up" to +14 volts in the logical "1" state
thus providing guaranteed interface between TTL
and MOS logic levels.
schematic and connection diagrams
16K
4K
lK
DuaHn-Line and Flat Package
TOP VIEW
1-204
c
absolute maximum ratings
(Note 1)
operating conditions
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
70V
55V
55V
_65°C to +125°e
300°C
electrical characteristics
Supply Voltage (Veel
DM7819
DM8819
DM7819
DM8819
CONDITIONS
Vcc=Mm
Logical "1" Output Current
Vee 0 Min, V ,N 0 2 OV, V auT 0 lOV
Vee 0 Min, V ,N 04 5V, V auT 0 14V
Logical "0" Output Voltage
Vee = Min, VIN =
= Max,
a 8V,
Vee
Logical "0" I nput Current
Vee = Max,
Supply Current - Logical 1/1"
Vee = Max, V ,N " 5V
Vcc=Max, V ,N = OV
DM7819
DM8819
V
V
-55
0
+125
70
°e
°e
MIN
TYP
MAX
lOUT = 16 mA
V ,N
~
04V
110
200
V
400
10
}1A
mA
....
CD
04
V
400
10
}1A
mA
-1.6
mA
21 0
330
mA
mA
-1.5
V.
tpdO
Vee 0 5 OV
T A ~ 25°C
160
240
ns
Vee 0 5 OV
TAO 25°C
160
320
ns
C
00
UNITS
08
CD
........
s:
00
V
Vee 0 5 OV, TA 0 25°C, 'iN 0 -12 mA
DM7819
DM8819
PropagatlOn Delay to a Logical "1"
55
525
V ,N o24V
V ,N 0 5 5V
Logical" 1" I nput Current
Propagation Delay to a Logical "0"
UNITS
45
475
20
Logical "0" Input Voltage
Input Clamp Voltage
MAX
Temperature (T A)
Vcc=MIn
Logical "0"
....
00
(Note 2)
PARAMETER
Logical "1" I nput Voltage
s:.....
tpd1
Note 1 "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electncal Charactenstlcs" provides conditions for actual device operatlo~
0
Note 2 Unless otherWise specified min/max limits apply across the -55 C to +125 C temperature range for the DM7819
and across the oOe to 70 0e range for tile DM8819 All tYPlcals are given for Vee
5 OV and T A == 25°C
=0
1-205
o
N
00
00
Series 54/74
~
C
......
o
N
00
....
DM7820/DM8820 dual line receiver
C
general description
~
The DM7820, specified from -55°C to 125°C, and
the DM8820, specified from oOe to 70°C, are
digital Iine receivers with two completely independent units fabricated on a single silicon chip_
Intended for use with digital systems connected
by twisted pair lines, they have a differential input
designed to reject large common mode signals while
responding to small differential signals_ The output
is directly compatible with RTL, DTL or TTL
integrated circuits_
• Each channel can be strobed independently
• High input resistance
• Fanout of two with either DTL or TTL
integrated ci rcu its
The response time can be controlled with an external capacitor to eliminate noise spikes, and the
output state is determined for open inputs_ Termination resistors for the twisted pair line are
also included in the circuit. Both the DM7820 and
the DM8820 are specified, worst case, over their
full operating temperature range, for ±10-percent
supply voltage variations and over the entire input
voltage range,
features
• Operation from a single +5V logic supply
• Input voltage range of ±15V
schematic and connection diagrams
RESl'ONSETIME
CONTROl
,.
AIO
'"
~
AU
"
OJ
-~
INPUT
no'"
A9
AI
no
A16
JK
~ ,..,"
A9
"
NON INVERTING
AU
"
"
A6
"
,-
~"
Dual~ln~Line
AI,
.
Q9>-
and Flat Package
'OK
.... Ql0
~(.,
~-4"':::""INPUT
TERr,.,INATION
A15
,20
AI,
'"
STROBE
..,.....
ST~OB£
OUTPUT
_'::""f---.J
lEflMINATlON
""
AJ
m
AI
INVE'HlNG
INPUT
"
A6
"
A16
15.
A2
'"
typical application
c,t
0002j.lF
Line Driver and Receivert
TWISTED PAIR LINE
OUTPUT
tVee Is4 5V to5.5V
for both the DM1820
Ind DM1B30
tElIact value depends
on hne length
·0 ptlonll to control
response time
1-206
STROBE
c
3:
.....
absolute maximum ratings
00
N
Supply Voltage
±20V
Differential Input Voltage
±20V
Strobe Voltage
C
3:
8.0V
Output Sink Current
00
00
25 mA
Power Dissipation (Note 1)
N
600mW
Operating Temperature Range
DM7820
DM8820
Storage Temperature Range
Lead Temperature (Soldenng, 60 sec)
0
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
PARAMETER
0
.......
8.0V
Input Voltage
(Notes 2 & 3)
CONDITIONS
MIN
Input Threshold Voltage
V IN = 0
- 15V :S VIN:S 15V
High Output Level
lOUT :S 0.2 mA
Low Output Level
I sink :S 3.5 mA
-0.5
-1.0
TYP
0
0
MAX
UNITS
0.5
1.0
V
V
2.5
5.5
V
0
0.4
V
Inverting Input Resistance
3.6
5.0
kn
Non·inverting Input Resistance
1.8
2.5
kn
Line Termination Resistance
TA = 25°C
Response Ti me
Cdelay = 0
Cdelay = 100 pF
Strobe Current
120
170
1.0
1.4
-5.0
mA
I1A
3.2
5.8
8.3
6.0
10.2
15.0
mA
mA
mA
5.0
-1.0
-7.0
7.0
-1.6
-9.8
mA
mA
mA
4.2
-0.5
-4.2
3.0
0
-3.0
mA
mA
mA
V strobe =O.4V
V 1N = 15V
V'N = 0
V 1N =-15V
Non·inverting Input Current
V 1N = 15V
V 1N = 0
V 1N =-15V
Inverting Input Current
Note 1
V 1N = 15V
V 1N = 0
V 1N =-15V
For operating at oeJevated temperatures, the device must be derated
~ased
n
ns
ns
40
150
Vstrobe = 5.5V
Power Supply Current
250
U
on a
thermal resistance of 100 C/W and a maximum Junction temperature of 160 C for the
DM7820 or 105°C for the DMB820
.s
Note 2. These specifICations apply for 4 5V S; Vee S; 5 5V, -15V:S; V CM
15V and
_55°C S; T A S;; 125°C for the DM7820 or O°C.s TA S; 70 ce for th~ OM8820 unless
otherWise specified tYPICal values given are for Vee = 50V, TA = 25 C and V CM = 0
unless stated differently
Note 3. The speclflcatlofls and curves given are for one Side only Therefore, the total
package dissipation and supply currents will be double the values given when both
receivers are operated under Identical conditions
1-207
«
o
N
Series 541741
co
co
:E
c
........
«o
DM7820A/DM8820A dual line receiver
N
co
.....
general description
:E
The DM7820A and the DM8820A are Improved
performance digital line receivers with two completely Independent units fabricated on a single
silicon chip_ Intended for use with digital systems
connected by tWisted pair lines, they have a differential Input designed to reject large common mode
signals while responding to small differential signals The output IS directly compatible with RTL,
DTL or TTL integrated CirCUltS_
c
Operation from a single +5V logic supply
•
I n put voltage range of ± 15V
•
Strobe low forces output to "1" state
•
High input resistance
Fanout of ten with either DTL or TTL integrated CirCUitS
•
Outputs can be wire OR'ed, 3 (maxi
•
Series 54/74 compatible
The response time can be controlled with an external capacitor to reject input noise spikes. The
output state IS a logic "1" for both Inputs open.
Termination reSistors for the tWisted pair line are
also Included In the circuit. Both the DM7820A
and the DM8820A are specified, worst case, over
their full operating temperature range (_55°e
to 125°e and oOe to 700 e respectivelyl, over the
entire Input voltage range, for ±10% supply voltage vanatlons.
features
•
•
schematic and connection diagrams
Rt:S~ONSE
TIME
cONTROL
, - - -....- ....---t-.....- - -....--1r---'c.
~
'"
;0'
'"
~:
""
"."
.
,,>--'
V
"
..... r -
Dual-I n-Lme and Flat Packages
0.10
eo
"'
no
"
"
-1r.,rPUT
'"
STROBE
""
TERMINATlON_
,.,"
INVERTING
,-,
INPUT
""
""
""
'"
''"
,.,"
typical applications
Single Ended (EIA-RS232C) Receiver with Hysteresis
Differential Line Dnver and Receiver
IOUTPUT- 1 fOR
OPENINPUl)
*Optlonal to control response tIme
1-208
c
3:
.....
absolute maximum ratings
00
Supply Voltage
N
8.0V
0
Commo~·Mode Voltage
±20V
Differential I nput Voltage
±20V
»
......
8.0V
C
Strobe Voltage
Output Sink Current
3:
50mA
Power Dissipation (Note 1)
600mW
00
00
Operating Temperature Range
DM7820A
-55°C to 125°C
DM8820A
O°C to 70°C
»
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
(Notes 2,3
VCM
& 4)
GONDITIONS
OUTPUT
+0 5
V
+10
<; a 4V
V auT <; a 4V
-0.08
-05
V
V
-0.08
-1.0
+16mA
<; V eM <; +15V
Non-Inverting Input Resistance
-15V
<; V eM <; +15V
36
18
TA
Line Termination Resistance
"
25°C
120
+15V
5
25
170
250
V
kn
kn
n
+30
+42
mA
a
-0 5
mA
-3 a
-42
mA
+15V
+5 a
+7 a
mA
OV
··10
-7 a
-16
mA
-98
mA
+6 a
+10 2
mA
mA
OV
-15V
Non-Invertmg Input Current
UNITS
+0 06
V auT
V auT
<; V eM <; +15V
MAX
+0 06
V aUT
-400 IlA
+16 mA
-15V
TYP
2" 2 5V
2" 2 5V
-4001lA
-15V
MIN
OTHER
<; V eM <; +3V
-15V <; V eM <; +15V
-3V <; V eM <; +3V
-3V
I nvertmg I nput Resistance
Inverting Input Current
0
_65°C to 150°C
Storage Temperature Range
Differential Threshold Voltage
N
-15V
Logic "0"
Logic "0"
V DlFF ==-lV
V D1FF =-05V
+39
+65
Logic "0"
V 01FF = -lV
>92
+140
Logical "1" Output Voltage
-4001lA
V o1FF =+lV
25
40
55
V
Logical "0" Output Voltage
+16mA
VOIFF=-lV
a
022
0.4
V
Loglcal"l" Strobe Input Voltage
+16mA
VauT
<; 0 4V. V DIFF
"
-3V
Logical "0" Strobe Input Voltage
-4001lA
V OUT
2: 2 5V, V 01FF =
-3V
09
V
Power Supply Current
+15V
OV
-15V
Logical "1" Strobe Input Current
VSTROBE =
5 5V, V 01FF
Logical "0" Strobe Input Current
VSTROBE;=
OV, V01FF
Output Short CirCUIt Current
Propagation Delays (see waveforms)
Differential Input to "0" Output
OV
Vee
='
5 5V,
:;
5.0
IlA
-10
001
-14
mA
-28 -45
-67
mA
+3V
OV
V
21
= -3V
VSTROBE =
Differential Input to "1" Output
Vee" 5V. T A
Vee" 5V, T A
"
25' e
25°C
30
24
Strobe Input to "0" Output
Vee" 5V,T A
"
25°C
Strobe Input to "1" Output
Vec" 5V, T A" 25°C
"
mA
45
ns
40
ns
16
25
ns
18
30
ns
Note 1: For operatmg at elevated temperatures, the deVice must be derated based on a thermal
re~lsJance of 1000 0C/W and a maximum junction temperature of 160°C for the DM7820A, or
150 C/W and 115 C maximum Junction temperature for the DM8820A
Note 2: These specificatiOns apply for 4 5V :::: Vcc :::: 55V, -15V :::: VCM :::: 15V and -55°C::::
T A :::: 125°C for the DM7820A or DoC:::: T A :::: 70°C for the DM8820A unless otherwISe speCified.
Typical values given are for Vce = 5 OV, T A = 25°C and VCM = OV unless stated differently
Note 3: The speCifications and curves given are for one side only Therefore, the total package
diSSipation and supply currents WIll be double the values given when both receivers are operated
under Identical conditions.
Note 4: Min and max limits apply to absolute values.
1·209
N
N
00
00
Series 54/74
:E
c
......
N
N
00
DM7822/DM8822 dual line receiver
.....
:E
general description
c
The DM7822/DM8822 is a dual Inverting line
receiver which meets the requirements of EIA
specification RS232 Revision B The device contains both receivers on a single monolithic silicon
chip The receivers share common power supply
and grou nd connections, otherwise their operation
is fully Independent.
Inputs which allow the receiver to be placed in the
high state independent of the Information being
received at the input.
The output of the DM7822/DM8822 IS completely
compatible with five volt DTL and TTL logic
families.
In addition to meeting the requirements of RS232,
the DM7822/DM8822 also has Independent strobe
connection diagram
Dual-In-Line Package
vee
INPUT
INPUT
*
*
**
**
STRbBE
*
OUTPUT
STROBE
*
OUTPUT
GNO
TOP VIEW
*MakenoconneC'bontothesepms.
* * For operation requlrmg ''Mark Hold" With the mput open connect
410n resistOrs from each of these pms to ground
typical connection
TWISTED PAIR LINE
RI"
4For Ma,k Hold Rl " 410n, otherWise connect pm 3 to ground
1·210
o
...,s:
absolute maximum ratings
Supply Voltage
I nput Voltage
Strobe Voltage
Output Sink Current
Power DISSipation INote 1)
Operating Temperature Range
80V
±30V
8 OV
25 mA
600 mW
-55°C to +125°C
O°C to 70°C
-65°C to +150°C
300°C
DM7822
DM8822
Storage Temperature Range
Lead Temperature ISolderlng, 10 sec)
electrical characteristics
Negative I nput Threshold
Voltage
4.8 IS)
Positive I nput Threshold
Voltage INote 3)
o
s:
CO
CO
N
N
MIN
CONDITIONS
V OUT
::> 2 5V
V OUT S;
Input ResIStance
.......
INote 2)
PARAGRAPH IN
RS-232
PARAMETER
CO
N
N
4.5 and 4.S 14)
30
3.57
20
V
50
70
kll
5
833
-357
mA
mA
mA
05
V
a
-8.33
-5
V ,N = OV
.03
Logical "1" Output Voltage
louT S; -0.2 mA
Logical "0" Output Voltage
lOUT = 3 5 mA
Strobe Current
VSTROBE = OV
VSTROBE = 5.5V
Power Supply Current
(Both Receivers)
-25V S; V IN S; 25V
Response Time, t, or t2
T A = 25°C
Vcc=50V
Input Ramp Rate S; 10 ns
UNITS
V
a 4V
V ,N = 25V
V ,N = OV
V ,N = -25V
Open CirCUit Input Voltage
MAX
-20
45and4S15)
I nput Current
TYP
25
V
04
10
-501lA
14
-10 mA
mA
a
mA
24
65
V
125
ns
Note 1. For operating at elevated temperatures, the devIce must be derated In accordance with
the "MaXimum Power DISSipation" curve
Note 2. MiniMax limits apply across the guaranteed temperature range of -55°C to +125°C for
the DM7822 and O°C to lOoe for the DM8822 unless otherWise specified LikeWise the limits
apply across the guaranteed Vee range of 45V to 55V for the DM7822 and 475V to 525V
for
TA
the
=
DM8822
unless
otherWise
specified
TYPlca!
values
are given for
Vee
=
5 OV and
25°C
Note 3. Since the EIA RS-232 specificatIOn requ1res the threshold to be between -3V and
the Immunity limits shown here guarantee 1 volt additional nOise Immunity
+3V,
1-211
o
('t')
00
00
Series 54/74
:!
c
........
o
DM7830/DM8830 dual differential line driver
('t')
00
I'
general description
:!
c
The DM7830/DM8830 is a dual differential line
driver that also performs the dual four-input NAND
or dual four-input AND function.
normally associated with single-wire transmissions.
features
TTL (Transistor-Transistor-Logicl multiple emitter
inputs allow this line driver to interface with standard TTL or DTL systems. The differential outputs
are balanced and are designed to drive long lengths
of coaxial cable, strip line, or twisted pair transmission lines with characteristic impedances of
50£1 to 500£1. The differential feature of the
output eliminates troublesome ground-loop errors
•
Single 5 volt power supply
•
Diode protected outputs for termination of
positive and negative voltage transients
•
Diode protected inputs to prevent line ringing
•
High Speed
•
Short Circuit Protection
sch~matic*and connection diagrams
...----..........- ..........-,,,
Dual-in-line and Flat Package
NAND
OUTPUT
...---.............- ..........-""
'"
OUTPUT
"'2 per package
typical application
C1 t
Digital Data Transmission
o01 ~F
LIRe Dnver and RecelYer f
OUTPUT
thad value depends
on transmiSSion rate
1-212
tVee IS 4 5V to 5.5V
for both the DM1820
and DM7830
·Optlorul to control
response time
STROBE
C
absolute maximum ratings
3:
......
vee
7.0V
Input Voltage
Operating Temperature
5.5V
_55°C to +125°C
DM7830
0
.......
C
O°C to 70°C
_65°C to +150°C
DM8830
I
00
W
Storage Temperature
3:
00
00
W
300°C
Lead Temperature (soldering, 60 sec)
Output Short Circuit Duration (125°C)
1 second
0
electrical characteristics
(Note 1)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
MIN
TYP
MAX
2.0
UNITS
V
Logical "0" I nput Voltage
0.8
V
V ,N
~
0.8V lOUT ~ -0.8 mA
2.4
Logical "1"Output Voltage
V ,N
~
0.8V lOUT ~ 40 mA
1.8
Logical "0" Output Voltage
V ,N
~
2.0V lOUT ~ +32 mA
0.2
0.4
V
Logical "0" Output Voltage
V ,N
~
2.0V lOUT ~ +40 mA
0.22
0.5
V
Logical "1" Input Current
V ,N
~
+2.4V
Logical "1" Input Current
V ,N
~
5.5V
2
mA
Logical "0" I nput Current
V ,N
~
O.4V
4.8
mA
Output Short Circuit Current
Vee ~ 5.0V
100
Note 2
120
mA
11
18
mA
ns
Logical "1" Output Voltage
V ,N
Supply Current
~
tpd1
tpdO
Propagation Delay NAN D Gate tpd 1
tpdO
Differential Delay t1
}
Note 2
40
fJA
5.0V
TA~25°C
Vee
CL
~
8
12
5.0V
11
18
ns
15 pF
8
12
ns
5
8
ns
12
16
ns
12
16
ns
~
See Figure 1
} Load, 100D. and 5000 pF
Differential Delay t2
V
3.3
120
(Each Dnver)
Propagation Delay AN D Gate
V
See Figure 2
Note 1: Specifications apply for OM7830 -55°C S. T A'S. +125 0c, Vee = +5V ±10%, DM8830 oOc
.$ 70o e, Vee =: +5V ±5% unless otherWise stated TYPical values given are for T A = 25°C,
Vee=50V.
~ TA
Note 2: Applies for T A
=
+125 0 C only
1·213
N
M
00
00
Series 54/74
:E
o
.......
N
M
DM78311DM8831,DM7832/DM8832 TRI-STATE
Ie
:E
general description
...
Through simple logic control, the DM7831/
DM8831, DM7832/DM8832 can be used as either
a quad single-ended line driver or a dual differential
line drIVer. They are specifically designed for
party line (bus-organized) systems_ The DM7832/
DM8832 does not have the Vee clamp diodes
found on the DM7831/DM8831 .
o
M
00
00
:E
...o
.......
mode of operation
To operate as a quad Single-ended line driver apply
logical "O"s to the Output Disable pins (to keep
the outputs In the normal low impedance mode)
and apply logical "O"'s to both Differential/
Single-ended Mode Control inputs. All four
channels will then operate Independently and no
signal inverSion will occur between inputs and
The DM7831 & DM7832 are specified for operation over the -55°C to +125°C military temperature range_ The DM8831 & DM8832 are specified
for operation over the O°C to + 70 c C temperature
range.
:E
o
line drivers
• High impedance output state which allows
many outputs to be connected to a common
bus line
M
Ie
®
outpu~s.
To operate as a dual differential line driver apply
logical "O"s to the Output Disable pins and apply
at least one logical "1" to the Differential/Singleended Mode Control inputs. The inputs to the A
channels should be connected together and the
Inputs to the 8 channels should be connected toIn this mode the signals applied to the resulting
inputs will pass non-inverted on the A2 and 8 2 outputs and Inverted on the A, and 8 , outputs.
features
• Series 54174 compatible
• 17 ns propagation delay
• Very
low output impedance-high drive
capability
• 40 mA Sink and source currents
• Gating control to allow either single-ended or
differential operation
When operating in a bus-organized system with
outputs tied di rectly to outputs of other
(Continued)
connection and logic diagram
Dual-In-Line and Flat Package
A
OUTPUT
ENABLE
B OUTPUT
ENABLE
OUTPUT
INPUT
OUTPut
INPUT
DIFfERENTIAL!
SINGtEENDEO
A~
A2
A,
A,
MODE CONTROt
OUTPUT
INPUT
8,
8,
OUTPUT INPUT DIFFERENTIAL! GND
8,
8,
SINGLEEHDEO
TOPVIEW
truth -table
(Shown for A Channels Only)
"A·· OUTPUT DISABLE
DIFFERENTIAL!
SINGLE·ENDED
MODE CONTROL
X
X
X - Don t Care
1-214
Logical
.. ,
Logical
··0··
OUTPUT A,
m
Logical "(' or
X
X
INPUT A,
Logical "0"
INPUT A2
Logical
..
Input Al
Logical
··0··
OpPosite of
Logical
Input A,
Logical ··0··
High
X
X
,
.. ,
Same as
Impedance
state
X
OUTPUT A2
m
Same as
m
Same as
Input A2
Input A2
High
Impedance
state
c
I
3C
.........w~
absolute maximum ratings
Supply Voltage
7V
55V
55V
-65'C to +150'C
-5SoC to +125°C
O'C to +70'C
300'C
Input Voltage
Output Voltage
Storage Temperature Range
DM7831, DM7832
DM8831, DM8832
Lead Temperature (Soldering, 10 sec)
Time that 2 bus-connected devices may be In
Operating Temperature Range
OPPosite low Impedance states simultaneously
c
3C
CO
CO
...
W
c
~
3C
~
electrical characteristics
W
N
(Note 1)
......
PARAMETER
Logical "1" Input Voltage
Logical
"a"
I nput Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
CONDITIONS
DM7831,DM7832 Vee" 4 5V
DM8831,DM8832 Vee 475V
MIN
TYP
08
Vee "45V
10" -40 mA
10'" -2 rnA
Vee" 475V
10 -40 mA
10" -5 2 mA
18
24
18
24
029
029
10 "32mA
Input Current
DM7831,DM7832 Vee" 5 5V Y'N " 5 5V
DM8831,DM8832 Vee -525V Y'N - 24V
Logical "0" Input Current
DM7831,DM7832 Vee" 5 5V
Y,N "0 4V
DM8831,DM8832 Vee -525V
Output Disable Current
DM7831,DM7832 Vee "55V
V o --24Vor04V
DM8831,DM8832 Vee "525V
Logical
"1"
DM7831,DM7832 Vee "55V
Output Short CirCUIt Current
OM8831,DM8832 Vee 525V
Supply Current
DM7831,DM7832 Vee"55V
DM8831,DM8832 Vee 525V
-40
-100
65
Vee" 50V, TA " 25'C
liN" -12 mA
Input Diode Clamp Voltage
Output Diode Clamp Voltage
-1 0
-40
INote 2)
3C
DM7831,DM7832 In T "-12 mA,V ee " 5 OV, T " 25'C
OM8831,DM8832 lOUT - +12 mA,Vc,e - 5 av, TA - 2SoC
CO
CO
W
V
N
V
V
V
V
23
27
25
29
10 "40mA
10" 32 mA
10 -40mA
DM7831,DM7832
DM8831,DM8832
c
UNITS
V
20
DM7831,DM7832 Vee "45V
DM8831,DM8832 Vee - 4 75V
DM7831,DM7832
DM8831,DM8832
MAX
050
40
050
40
V
V
V
V
1
40
mA
pA
-16
mA
40
pA
120
INote 2)
mA
90
mA
-15
V
-15
Vcc +l 5
V
V
Propagation Delay to a Logical "0"
from Inputs A l . A 2 , 8,. 8 2 Dlfferentlal Smgle-el1ded Mode Control to
T A " 25'C
13
25
ns
Vee "50V, TA"25'C
13
25
ns
Vee =50V.
TA = 25°C
6
12
ns
Vee "50V,
TA " 25'C
14
22
ns
Vee "~,OV,
TA " 25'C
14
22
ns
Vee" 50V,
T A " 25'C
18
27
ns
Vee "50V,
Outputs, tpdO
Propdgatlon Delay to a Logical "1"
from Inputs A,. A 2 , 8,. 8 2 Dlfferentlal Single-ended Mode Control to
Outputs, t pd ,
Delay from Disable Inputs to High
Impedance State (from Logical "1"
Level), t, H
Delay from Disable Inputs to High
I mpedance State (from Logical "0"
Levell. tOH
Propagation Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State I. tH 1
Propagation Delay from Disable Inputs
to Logical "0" Level (from High
I mpedance State). tH a
Nota 1: Unless otherwise specified minImax limits apply across the _55°C to +12SoC temperature
range for the DM7831, DM7832 and across the O'C to 70'C temperature range for the DM8831,
DM8832. All tYPlcals are given for V CC " 5 OV and T A : 25' C
Note 2. Applies for TA = 12SoC only Only one output should be shorted at a time
1-215
N
M
CIO
CIO
~
C
.........
N
M
CIO
,....
~
C
mode of operation (cont.)
DM7831 /DM8831 's, DM7832/DM8832's (F Igure
1), all devices except one must be placed In the
"high Impedance" state. This IS accomplished by
ensuring that a logical "1" IS applied to at least
one of the Output Disable pinS of each deVice
which IS to be In the "high Impedance" state A
NOR gate was purposely chosen for thiS function
since It IS possible with only two DM5442/
DM7442, BCD·to·declmal decoders, to decode as
many as 100 DM7831/DM8831's, DM7832/
DM8832's (F Igure 2).
The unique deVice whose Disable Inputs receive
two logical "0" levels assumes the normal low
Impedance output state, providing good capacitive
drive capability and waveform integrity especially
dUring the transition from the logical "0" to
logical "1" state. The other outputs-in the high
Impedance state-take only a small amount of
leakage current from the low Impedance outputs
Since the logical "1" output current from the
selected deVice IS 100 times that of a conventional
Series 54174 deVice (40 rnA vs 400 !1A), the
output IS easily able to supply that leakage current
for several hundred other DM7831 /DM8831 's,
DM7832/DM8832's and stili have available drive
for the bus line (Figure 3).
BUS LINES
SElECTED AS
DRIVING
DEVICE
~
DD
T~~:~~i~~~ ----
MM
::
n
I-Hrl-'
D D
GATED INTO
THIRD STATE -----..
MM
8 8
8 8
nHt-t-+..
Figure 1
Figure 2
FOR DRIVING OTHER TTL INPUTS
DD
SElECTED AS
DRIVING DEVICE
OUTPUTS
MM
8 8
8 8
40 mA
J J
1 2
GATED INTO
HI IMPEDANCE
STATE
~~I---.
8
8
J
1
8
8
J
2
40 iJA
LEAKAGE
CURRENT
PER CONN
GATED INTO
HI IMPEDANCE
STATE
~~I---.
8 8
8 8
J J
1 2
Figure 3
1·216
c
s::.....
Series 54/74
00
w
en
........
C
s::
00
CO
DM7836/DM8836 quad NOR unified bus receiver
general description
w
en
features
The DM7836/DM8836 are quad 2-input receivers
designed for use in bus organized data transmission
systems interconnected by terminated 120n impedance lines_ The external termination is intended to be 180n resistor from the bus to the +5V
logic supply together with a 390n resistor from
the bus to ground_ The design employs a built-in
input hysteresis providing substantial nOise Immunity_ Low input current allows up to 27 driver/
receiver pairs to utilize a common bus. This receiver has been specifically configured to replace
the SP380 gate pln-for-pin to provide the distinct
advantages of the DM7837 receiver design in existing systems.
•
Plug-in replacement for SP380 gate
•
Low input current < With normal Vce or
Vee; OV (15!LA typ)
•
Built-in input hysteresIs (lV typ)
•
High nOise immunity (2V typ)
•
Temperature-insensitive Input thresholds track
bus logic levels
•
DTL!TTL compatible output
•
Matched, optimized noise immunity for "1"
and "0" levels
•
High speed (18 ns typ)
typical application
+5V
'5V
1.0n
tBO!!
120n UnifIed Data Bus
--, r- --,
39052
J9D!!
1
1
1
1I
I I
11
I 11/,'
1
_.J ~7.!!.' -...I
connection diagram
Dual-I n-Line Package
OUTl
OUT4
IN4A
IN 48
IN 3A
IN 18
Vee
OUT 2
OUT 1
IN 1A
IN 18
IN2A
IN 28
14
GND
TOP VIEW
1-217
absolute maximum ratings
(Note 1)
7.0V
5.5V
600mW
Supply Voltage
Input Voltage
Power Dissipation
Operating temperature range:
DM7836
DM8836
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
The following apply for V L
:S Vee :S V H, T L :S T A :S T H, unless otherwISe specified (Note 2)
PARAMETER
INPUT
MIN
TYP
MAX
UNIT
OUTPUT
COMMENTS
V TH
V TH
16 mA
16 mA
Output < 0 4V
Output < 0 4V
1.65
180
225
2.25
2.65
250
V
V
V TH
V TH
-40011A
-40011 A
Output> 2 4V
Output> 2 4V
097
1.05
130
130
1.63
1.55
V
V
High Level Input Threshold
OM7836
DM8836
Low Level Input Threshold
DM7836
DM8836
Maximum I nput Current
4V
Vee::; V H
15
50
I1A
Maximum Input Current
4V
Vee
= OV
1
50
I1A
Logic "1" Output Voltage
o 5V
24
-40011 A
025
Logic "0" Output Voltage
4V
16 mA
Output Short Circuit Current
o 5V
OV
Power Supply Current
4V
Per Package
Input Clamp Diode Voltage
-12 mA
TA
The following apply for Vee"" 5V, T A
=
V
Vee
=
-18
VH
0.4
V
- 55
mA
mA
25
40
= 25"C
-1
-1 5
V
Note 3
Note 4
20
18
30
30
ns
ns
2SoC unless otherwise specified
Propagation Delays
I npu! to Logic "1" Output
J nput to Logic "0" Output
I
I
I
Note 1: Voltage values are with respect to network ground terminal. Positive current
IS
defined as current Into the reference pin.
Note 2: For DM7836· V L = 4.5V, VH = 5.5V, T L = _55°C, T H = +125°C.
For DM8836. V L = 4.75V, VH = 5.25V, TL = O°C, TH = +70°C.
Note 3: Fan-out of 10 load, C LOAD = 15 pF total, measured from V1N = 1.3V to VO UT
= 1.5V, V1N
= OV to 3V pulse.
Note 4: Fan-out of 10 load, C LOAD = 15 pF total, measured from V 1N = 2.3V to V OUT = 1.5V, V ,N = OV to 3V pulse.
1·218
~s
Series 54/74
DM7837/DM8837 hex unified bus receiver
general description
features
The DM7837/DM8837 are high speed receivers designed for use In bus organized data transmission
systems Interconnected by terminated 120Q Impedance lines. The external termination IS Intended to be 180Q resistor from the bus to the +5V
logic supply together with a 390Q resistor from
the bus to ground. The receiver design employs a
built-In input hysteresIs providing substantial noise
Immunity. Low Input current allows up to 27 driver/receiver parrs to utilize a common bus. Disable
Inputs provide time discrimination. Disable Inputs
and receiver outputs are DTLlTTL compatible.
•
Low receiver Input current for normal Vee or
Vee~OV(15I1Atyp)
• S'x separate receivers per package
•
Built-In receiver Input hysteresIs (lV typ)
•
High receiver nOise Immunity (2V typ)
•
Temperature Insensitive receiver Input thresholds track bus logic levels
•
DTLlTTL compatible disable and output
•
Molded or cavity dual-In-Ilne or flat package
•
High speed
01
typical application
.5V
'5V
18011
laOn
--, r- --,
39011
I I
I
I
I
I
I I
I I
I
_...1
39011
'::"
_...I
connection diagram
Dual-In-Llne and Flat Package
Vee
IN lOUT 1
IN 2
OUT 2
IN 3
OUT J
DISABLE A
TOPVIEW
1-219
.....
~
00
00
absolute maximum ratings
(Note 1)
:E
o
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature Range
DM7837
DM8837
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
"
.....
~
00
.....
:E
o
7V
5.5V
600mW
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
electrical characteristics
The followinll apply for V L
:s Vee :s V
RECEIVER
INPUT
PARAMETER
H,
TL
:s T :s T
A
DISABLE
INPUT
H,
unless otherwise specified (Note 2)
TYP
MAX
High Level Receiver Threshold
DM7837
V TH
o 8V
OUTPUT
l6mA
Output<04V
COMMENTS
MIN
165
225
265
UNIT
V
High Level Receiver Threshold
DM8837
V TH
08V
16mA
Output<04V
180
225
250
V
Low Level Receiver Threshold
DM7837
V TH
08V
-400 mA
Output> 2 4V
097
130
163
V
Low Level Receiver Threshold DM8837
V TH
08V
-400 mA
Output> 24V
105
130
155
V
MaXimum Receiver Input Current
4V
Vee:::: V H
150
500
~A
MaXimum Receiver Input Current
4V
Vee = OV
10
500
~A
Disable
05V
Y'N
l6mA
Output < 0 4V
logiC "0" Input Voltage Disable
05V
Y'N
-400~A
Output> 2 4V
LogiC "1" Output Voltage
o 5V
08V
-400~A
LogiC "0" Output Voltage
4V
08V
l6mA
LogiC "1" Input Voltage
20
V
08
V
04
V
24
V
025
LogiC "l"'nput Current Disable
24V
800
~A
LogiC "1" Input Current: Disable
55V
2,0
mA
4V
04V
Output Short Circuit Current
LogiC "O"'nput Current
05V
OV
Power SupplV Current
4V
OV
Per Package
Input Clamp Diode
-12mA
-12mA
T A = 25°C
Disable
OV
Vee:::: V H
-32
mA
-550
mA
450
60,0
mA
-10
-15
V
-180
The follOWing apply for Vee:::: 5V. TA = 2SoC unless otherWise specified
Propagation Delays
Receiver Input to LogiC "1" Output
OV
Note 3
20
30
n.
Receiver Input to LogiC "0" Output
OV
Note 4
18
30
n.
Disable Input to LogiC "1" Output
OV
Note 5
9
16
n.
Disable Input to LogiC "0" Output
OV
Note 5
4
10
ns
Note 1: Voltage values are With respect to network ground terminal. Positive current is defined as current into the referenced pin.
Note 2: For DM7837: V L = 4.5V, VH = 5.5V, T L = _55°C, T H = +125°C
For DM8837: VL = 4.75V, VH = 5.25V, TL = O°C, TH = +70°C
Note 3: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 1.3V to V OUT
Note 4: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 2.3V to VOUT
Note 5: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 1.5V to VOUT
1-220
= 1.5V, VIN = OV to 3V pulse.
= 1.5V, VIN = OV to 3V pulse.
= 1.5V, VIN = OV to 3V pulse.
c
3:
Series 54/74
~
00
W
00
"-
c
OM7838/0M8838, quad unified bus transceiver
general description
3:
00
features
00
Co\)
The DM7838/DM8838 are quad high speed drlvers/
receivers designed for use in bus organized data
transmission systems Interconnected by termi,
nated 120n impedance Imes, The external termination is intended to be a 180n reSIStor from the
bus to the +5V logic supply together with a 390n
resistor from the bus to ground, The bus can be
terminated at one or both ends, Low bus pin current allows up to 27 driver/receiver pairs to utilize
a common bus, The bus loading is unchanged
when V cc ~ OV, The receivers Incorporate hystereSIS to greatly enhance bus nOise immunity, One
two-input NOR gate IS Included to disable all
drivers In a package simultaneously
00
• 4 totally separate driver/receiver pairs per
package
•
•
•
1 V typical receiver Input' hysteresIs
Receiver hysteresIs Independent of receiver
output load
Guaranteed minimum bus noise immunity of
1,3V, 2V typ,
• Temperature,insensltlve' receiver thresholds
track bus logic levels
•
20MA tYPical bus terminal current with normal
Vee or with V cc'~ OV
• Open collector driver output allows wire-OR
connection
• High speed
• Series 74 TTL compatible driver and disable
inputs and receiver outputs
II
typical application
.,v
.5V
180U
lao!!
1201'1 Unofied Data Bus
rijl'r:i:.:;,
390!J
'::'
-, r-
I
I I
I
I I
I
II
I I
1116
I!M!!.'!... __ J L_
I I
I I
I I
I
Q
-,
I
I
I
I
_...I
_...J
390lJ
':'
connection diagram
Dual In-Line and Flat Package
Vee
BUS 1
IN 1
OU11
BUS 2
IN 2
BUS3
IN3
OU13
BUS4
IN4
OUT4
OUT 2 DISABlE A
DISABLEB
GND
TDPVIEW
1-221
00
('I).
absolute ma.ximum ratings
00
00
Supply Voltage
Input and Output Voltage
::E
o
Operatmg Temperature Range
DM7838
DM8838
Storage Temperature Range
7V
55V
600rnW
Power DISSipation
"
_55°C to +12SoC
O°C to +70°(;
-6SoC to +150°C
Lead Temperature (Soldering, 10 sec)
00
300"C
('I)
electrical characteristics
00
"::E
DM7838/DM8838
o
The followmg apply for V L ~ V cc ~ V H' T L ~ T A ~ T H unless otherWise specified (Note 2).
DRIVER
INPUT
Logic "1" Input
Disable
Y'N
2V
4V
Logic "0" Input
Disable
Y'N
2V
50 rnA
Bus
< 0 7V
Logic ''1'' Input
Voltage, Driver
0.8V
V ,N
50mA
Bus
< a 7V
Logic "0" Input
Voltage
Driver
08V
Y'N
4V
.
o 8V
V TH
l6mA
Receiver output
<04V
165
High Level Receiver
DM8838
o BV
V TH
l6mA
Receiver output
<04V
Low Level Receiver
Threshold·. DM7838
08\/
V TH
-400 MA
Low Level Receiver
Threshold DM8838
o 8V
V TH
-400MA
Voltage
Voltage
Hlgn Level Receiver
Threshold DM7B38
BUS
PIN
RECEIVER
OUTPUT
DISABLE
INPUT
PARAMETER
5 5V
MIN
Bus < 100 MA
20
TYP
MAX
UNIT
V
08
V
V
20
OB
V
225
265
V
180
225
250
V
Receiver output
>24V
097
1 30
1 63
V
Receiver output
>24V
1 05
130
1 55
V
Bus < 100MA
Threshold
Logic "1" Input
Current' Disable
COMMENTS
55V
1
rnA
and Driver
,.,f
Logic "1" Input
2 4V
24V
40
MA
04V
04V
-16
rnA
Maximum Bus
Current
o 8V
o 8V
4V
Vee::: V H
20
100
MA
Maximum Bus
08V
o 8V
4V
Vee::: OV
2
100
MA
Low Level Bus
Voltage
o 8V
2V
Logic "1" Output
Voltage
Receiver
08V
o 8V
o 5V
Logic "0" Output
Voltage' Receiver
o BV
o 8V
4V
16 rnA
Output Short CirCUit
€urrent. Receiver
0.8V
0.8V
o 5V
OV
Current.
Disable
and Driver
Logic "0" Input
Current
Disable
and Drlvgr
Current
Supply Current
OV
Input Diode Clamp
Voltage
-12 rnA
SOmA
04
-400MA
2V
~12
mA
-12 mA
07
24
V
025
Vee::: V H
V
-18
0.4
V
-55
rnA
rnA
Per Package
50
70
TA = 25°C
-1
-1 5
V
n,
The following apply for Vee::: 5V, T A ::: 25°C unless otherwise speCified
Propagation Delays
Disable to Bus "1"
Note 3
19
30
Disable to Bus "0"
Note 3
15
23
ns
Driver Input to Bus "1"
Note 3
17
25
n,
Driver I nput to Bus "0"
Note 3
9
15
ns
Bus to Logic "1"
Receiver Output
Note 4
20
30
n,
Bus to Logic "0"
Receiver Output
Note 5
18
30
n,
Note 1 Voltage values are with respect to network ground term mal Positive <:urrent IS defmed as current mto the referenced
pm
Note 2:
For pM7838
For DMB838
n
VL =0 4 5V, VH =0 5 5V, TL '" _55°C, TH '" 125°C
VL "'4 75V, V .... "'- 525, TL '" OOC, TH '" 70°C
Note 3' 91
from bus pm to Vee and 200Q from bus pin to ground, C LOAD '" 15 pF total Measured from VIN '" 1 5V to
VSUS '" 1 5V, VIN '" OV to 3V pulse
Note 4
Note 5
1·222
Fan-out of 10 load, C LOAD '" 15 pF total Measured from VIN = 1 3V to VOUT '" 1 5V, YIN = OV to 3V pulse
Fan-out of 10 load, CL.OAD '" 15 pF total Measured from YIN'" 2 3V to V OUT '" 1 5V, VIN '" OV to 3V pulse
Series 54/74
cc
:s::s:
...,...,
...,...,
COCO
U'IU'1
all>
..............
CC
:s::s:
DM7875A/DM8875A and DM7875B/DM8875B
COCO
COCO
TRI-STATE® 4-bit multipliers
...,...,
U'IU'1
all>
general description
The DM7875A/DM8875A & DM7875B/DM8875B
are two Integrated circuits which together will
multiply two four-bit bmary numbers. Smce the
largest number that can be obtained by mu Itlplymg
two four-bit numbers IS 225 (15 x 15), the eight
output pms (four from each package) are sufficient
to produce this number. Both multiplier and multiplicand are connected to the eight mput pms of
each package
Since only one multiplier-pair at a time is allowed
to be m the conventional low -Impedance state,
the advantages of TTL outputs can be combmed
with a bus structured system.
The DM7875A/DM8875A provides the most significant four bits and the DM7875BIDM8875B the
least significant four bits.
features
A gated two-input strobe control IS provided. When
either of the two inputs IS taken to the logical" 1"
state, the outputs will all be placed in the high
Impedance state. In this state both the upper and
lower output transistors are turned off, provldmg
a high output impedance. This allows multiple
devices to be connected to a common bus Ime, and
•
36 ns tYPical propagation delay
•
375 mW tYPical power~dlsslpatlon
(each package)
•
Series 54174 compatible
•
Outputs directly connectable to a common
bus Ime
1-223
aI
U')
.....
absolute maximum ratings
00
00
:E
(Note
11
7V
Supply Voltage
5.5V
I nput Va Itage
5.5V
Output Voltage
Operating Temperature Range DM7875A, DM7875B _55°C to +125°C
DM8875A, DM8875B
O°C to +70°C
-65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
300°C
c
........
aI
U')
.....
00
.....
:E
c
electrical characteristics
«
(Note 2)
U')
.....
PARAMETER
00
00
CONDITIONS
Logical "1" I nput Voltage
DM7875A, DM7875B
DM8875A, DM8B75B
Vee" 4 5V
Vee - 4 75V
c
Logical "0" I nput Voltage
DM 7875A/DM 7875B
DM8875A, DM8875B
Vee" 4 5V
Vee 475V-
«
Logical "1" Output Voltage
DM7875A, DM7875B Vee" 4 5V, 10" -2 0 mA
DM8875A, DM8875B Vee - 4 75V, 10 - -5 2 mA
Logical "0" Output Voltage
DM7875A, DM7875B Vee"45V
DM8875A, DM8875B V ee - 475V
Third State Output Current
DM 7875A, DM 7875B Vee" 55V
DM8875A, DM8875B Vee 525V
Logical "1" Input Current
DM7875A, DM7875B V ee "55V
DM8875A, DM8875B V ee -525V
:E
........
U')
.....
00
.....
:E
c
DM7875A, DM7875B
DM8875A, DM8875B
04
10" 16mA
V 1N =24V
Vo" 0 OV
Supply Current (each device)
DM7875A, DM7875B
DM8875A, DM8875B
Vee" 5 5V
Vee - 525V
All Inputs at GND
Input Clamp Voltage
DM7875A, DM7875B
DM8875A, DM8875B
Vee ~ 4 5
Vee - 4.25
IIN=-12mA
Output Vee Clamp Voltage
DM7875A, DM7875B
DM8875A, DM8875B
Vee" 55V
Vee - 525V
lo=12mA
DM8875A, DM8875B
Propagation Delay to a Logical "0" from X, Y Inputs
Vee
= 5 5V
IlA
IlA
40
-1 2
VIN = 04V
-20
75
-70
mA
110
mA
-15
V cc +15
10 = -12 mA
Vee - 525V
mA
V
V
-1 5
V
Vee ~ 5 OV
T A = 25°C
39
60
ns
to Outputs, tpdl
Vee" 5 OV
TA = 25°C
31
60
ns
Delay from Strobe to High Impedance State (from
Vee
Logical "1" Level),
T A" 25°C
to Outputs,
tpdO
Propagation Delay to a Logical "1" from X, Y Inputs
t1 H
Delay from Strobe to High Impedance ~.tate (from
Logical "0" Leven,
tOH
Delay from Strobe to Logical "1" Level (from High
Impedance State), tHl
Delay from Strobe to Logical "0" Level (from High
Impedance State), tHO
= 5 OV
30
ns
Vee" 5 OV
T A = 25°C
10
ns
V ee "50V
TA " 25°C
30
ns
Vee ~ 5 OV
T A " 25"C
30
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed
Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electrical Characteristics" provIdes conditions
for actual device operation
Note 2: Unless otherwise specified min/max limits apply across the _55°C to +125° C temperature
range for the DM7875A, DM7875B and aeross the oOe to 70 c e range for the DM8875A, DM8875B
All tYPleals are 91ven for Vee" 5 OV and TA ~ 25°C
Note 3: Only one output at a time should be shorted
1·224
V
mA
Vee o55V
Vee 525V
Output Ground Clamp Voltage DM7B75A,DM7875B
40
-40
Vo " 2 4V
Va" 0 4V
525V
Vee~55V
V
V
Vee~55V
Vee
UNITS
V
24
DM7875A, DM7875B
DM8875A, DM8875B
{Note 31
MAX
08
Vee - 525V
Output Short Circuit Current
TYP
20
DM7875A, DM7875B
DM8875A, DM8875B
Logical "0" Input Current
MIN
c
s:
.....
Series 54/74
00
00
o
c
........
s:
DM7880/DM8880 high voltage 7-segment decoder/driver
(for driving Sperry and Panaplex IITM displays)
00
00
00
o
general description
The DM7880/DM8880 is custom designed to decode four lines of BCD and drive a gas-filled
seven-segment display tu be.
dance with the programming curve. The CirCUit
design provides a one-to-one correlation between
program input current and b-segment output
current.
Each output constitutes a sWltchable, adjustable
current sink which provides constant current
to the tube segment, even with high tube anode
supply tolerance or fluctuation. These current
Sinks have a voltage compliance from 3V to
at least 80V; tYPically the output current vanes
1% for output voltage changes of 3 to 50V. Each
The Blanking I nput provides unconditional blankIng of any output display, while the Ripple BlankIng pins allow Simple leadlng- or trailing-zero
blanking.
features
current Sink IS ratioed to the b-output current
as reqUired for even illumination of all segments.
Output currents may be varied over the 0.2 to 1.5
mA range for dnvlng va'rious tube types or
mUltiplex operation. The output current IS adjusted by connecting an external program resistor
(Rp) from Vee to the Program input In accor-
•
Current sink outputs
•
Adjustable output current - 0.2 to 1.5 mA
•
High output breakdown voltage - 110V typ
•
SUitable for multiplex operation
•
Blanking and Ripple Blanking proVIsions
•
Low fan-in and low power
logic and connection diagrams
,-----------------'
I
I
I
+
Dual-In-line Package
a OUTPUT
I
---------OUTPUTS
",1~t---!- b OUTPUT
A INPUT
r-+--ir c OUTPUT
B INPUT
" , 1 : - t - - - ; - d OUTPUT
C INPUT
'C--+--ir e OUTPUT
o INPUT
RIPPLE
BLANKING
INPUT
+----1
",i:--i---+- !OUTPUT
r---/--+ 9 OUTPUT
BLANKING
INPUTI
RIPPLE
BLANKING
OUTPUT
~BIJRBO ~
INPUTS
+--+--1
CURRENT
GND
INPUTS
fOP VIEW
PROGRAMMING
INPUT
1-225
o
ClO
ClO
ClO
absolute maximum ratings
operating conditions
~
C
Vee
Input Voltage IExcept 811
Input Voltage 1811
Segment Output Voltage
7V
6V
Vee
80V
Power DISSipation (Note 1)
600mW
Transient Segment Output Current (Note 2)
50 mA
-65"e to 150°C
Storage Temperature Range
300"e
Lead Temperature (Soldering, 10 sec)
Supply Voltage IVeel
DM7880
DM8880
.......
o
ClO
ClO
"~
C
electrical characteristics
Temperature (T A)
DM7880
DM8880
MIN
MAX
UNITS
4.5
475
5.5
5.25
V
-55
0
+125
+70
V
(Note 3)
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
Logic "1" Input Voltage
Vee == Mm
Logic "0" I nput Voltage
Vee == Min
Logic "1" Output Voltage (RBO)
Vee = Min,
lOUT = -200 f.lA
Logic "0" Output Voltage IRBO)
Vee = Mm, lOUT = 8 mA
0.13
Logic "1" Input Current (Except BII
Vee = Max, V ,N = 2 4V
Vee=Max, V ,N =55V
2
4
15
400
Logic "0" Input Current (Except BII
Vee = Max, V ,N = 04V
-300
-600
Logic "0" Input Current (BI)
Vee= Max, V ,N =04V
-12
-20
mA
Power Supply Current
Vee = Max, R p = 2 2k
All Inputs = OV
27
43
mA
Input Diode Clamp Voltage
Vee = Max, T A = 25°C
liN = -12 mA
-09
-15
Segrnent Outputs
Outputs a, f, g ON Current Ratio
20
V
0.8
24
37
V
V
0.4
V
p.A
f.lA
f.lA
V
All Outputs = 50V
Output b Curro = Ref
0.84
0.93
1.02
Output c ON Current Ratio
All Outputs = 50V,
Output b Curr = Ref.
1.12
1.25
1.38
Output d ON Current RatiO
All Outputs = 50V
Output b Curr = Ref.
0.90
100
1.10
Output e ON Current Ratro
All Outputs = 50V
Output b Curr = Ref.
0.99
1 10
1.21
Output b ON Current
Vee = 5V, V OUT b = 50V
T A = 25"C, Rp = 18 1k
Vee = 5V, V OUT b = 50V
T A = 25°C, Rp = 703k
018
020
0.22
mA
045
050
0.55
mA
Vee = 5V, V OUT b = 50V
T A = 25°C, Rp = 340k
0.90
100
1 10
mA
Vee = 5V, V OUT b = 50V
T A = 25°C, Rp = 2 20k
135
1.50
165
mA
Output Saturation Voltage
Vee = Min, Rp = 1k±5%
lOUT b = 2 mA (Note 41
Output Leakage Current
V OUT = 75V, BI = OV
Output Breakdown Voltage
lOUT = 250 f.lA, BI = OV
0.8
25
.003
80
3
110
V
f.lA
V
Propagation Delays
BCD I nput to Segment Output
BI to Segment Output
RBI to Segment Output
RBI to RBO
Note 1
MaXimum Junction temperature for DM7880
Vee
Vee
Vee
Vee
IS
=
=
=
=
5V,
5V,
5V,
5V,
TA =
TA =
TA =
TA =
0.4
0.4
0.7
04
25°C
25°C
25°C
25°C
150°C whereas that for DM8B80
temperatures the deVice must be derated based on a thermal resistance of 85°C/W
8 JA
IS
10
10
10
10
130°C For operating at elevated
for DM788Q and 150°C/W
8 JA
for
DMB880
Note 2
In all applications tranSient segment output current must be limited to SO mA This may be accomplished In DC
applications by connecting a 2 2k resistor from the anode-supply filter capacitor to the display anode, or by current limiting
the anode driver In multiplex applications
Note 3 Min/max limits apply across the guaranteed operating temperature range of -SSoC to 12SoC for DM7880 and aGc
to 70 Ge for DM8880, unless otherWise specified Typlcal~ are for Vce - 5V, T A ~ 25°e Positive current IS defined as current
Into the referenced pin
Note 4
1-226
For saturatIOn mode the segment output currents are externally limited and ratloed
f.ls
f.ls
f.ls
f.ls
c
s:
typical performance characteristics
100
.,E
30
i
,
>-
0
106
'">"
'"
u
"'"
"
1 O'
"-
J
096
'"
~
01
10
1/
092
I .l.
1 rnA
t.:I
f-
TYPICAL OPERATING POINTS
~
Rp =0 TEMP COEFf
50A
-50
C
s:00
0
02mA~loUT::;:15mA
50
Ii
100
OUTPUT OFF
30
1 1 1
60
90
120
OUTPUT VOLTAGE (VI
TAnl
Rp(kn)
.......
\ I I I
~
Vee" 5V
VOUT = 50V
090
100
30
~
/
098
:0 09.
,
>-
\ /
1 00
I I I
I I I
IOUT~:7
Vee = 5V
TA '" 25°C
/
\
102
N
03
-..",
ON CURRENT RATIOS
0
0
">-
"
~
0
I'
10
/
ON CURRENTS
i=
TA =25°C
Output Characteristic
108
0
Vee =5V
VOUT = 50V
>-
"
On Currents vs Temperature
Output Current Programming
00
00
0
typical application
IlIO-200VDCI
o"'r
~:9
<;>
Q
R=22K
!NOTt21
9
)"""'
~~S~~~YTUBE
.
SP-730DA
<;> Q Q.
,
'oc
5\1'10%
",
,I "I 01 ·1
OM5475
QUAD LATCH
cl
AI 81
D+-g~~~JT
DM>490
DECADE
COUNT
INPUT
truth table
DECIMAL
OR
FUNCTION
RBI
D
C
B
A
0
0
0
0
0
0
0
X
0
0
0
0
0
X
0
0
0
0
0
3
x
0
0
0
0
0
4
X
0
0
0
0
X
0
0
X
0
x
0
0
6
8
X
BI/RBO
0
0
0
0
9
X
0
10
X
0
0
0
0
0
14
X
15
X
BI
X
X
X
X
X
0
RBI
0
0
0
0
0
0
0
0
0
I
5
5-,
0
1-1
0
0
0
0
0
0
0
0
0
0
0
=1
_I
LI
0
0
0
0
X
,?
0
0
0
13
0
0
0
0
1
1
0
0
0
0
X
0
0
0
0
X
0
II
LI
0
0
0
0
11
0
0
0
12
0
0
0
0
DISPLAY
d
b
0
,
c:J
0
0
0
_I
0
0
0
II
0
Ll
0
0
0
0
0
0
0
0
0
0
0
0
{;-/b
"/ Ie
SEGMENT
IDENTIFICATION
I-I
I-
1-
L
~
0
LI
0
0
E
0
0
1
C
1-227
00
00
0
UT
c
3:
00
00
00
absolute maximum ratings
Vee
Input Voltage (Note 1)
Segment Output Voltage
Power DISSipation (Note 2)
TranSient Segment Output Current (Note 3)
Operating Temperature Range
Storage Temperature Range
electrical characteristics
7V
(DoC
PARAMETER
<;: T A <;:
e-
70 0
Logic "1" Input Voltage
Vee = 4 75V
Logic "0" Input Voltage
Vee = 4 75V
Logic "1" Input Current
Vee = 5 25V, V ,N = 24V
POSItive Input Clamp Voltage
Vee=4 75, liN = 1 mA
LogIc "0" I nput Current
Vec= 5 25V, V ,N = 04V
Vee= 5 25V,
»
Unless otherwise noted), Vee
CONDITIONS
Power Supply Current
~
Vee
80V
600mW
50 mA
DoC to +70°C
-65°C to +150°C
MIN
MAX
~ 5V ± 5%
UNITS
V
20
10
pA
-250
pA
40
mA
50
Rp= 2 Sk,
V
15
V
All Inputs = 5V
Negative Input Clamp Voltage
All Outputs ~ 50V
Output b Current = Ref
Output b ON Current
Vee = 5V, V OUT b = 50V,
T A = 25°C, Rp = 18 1k
Rp= 7 03k
Rp =340k
Rp = 2 SDk
Output Leakage Current
V OUT
Output Breakdown Voltage
lOUT = 250 fJA
Propagation Delay.
Any I nput to Segment Output
Note 1
-1 5
Vee = 5V, liN = -12 mA, TA = 25°C
Segment Outputs
All Outputs ON Current RatiO
Vee
=
=
V
09
11
018
045
090
108
022
055
1 10
132
rnA
rnA
mA
mA
5
fJA
75V
V
80
5V, T A "' 25° C
10
fJs
This limit can be higher for a current limiting voltage source
Note 2 The maximum Junction temperature IS 140°C For operation at elevated temperatures, the deVice must be derated
based on a thermal resistance of 140°c/we JA
Note 3' In all applications tranSient segment output current must be limited to 50 mA This may be accomplished In DC applications by connecting a 22k resistor from the anode-supply filter capacitor to the display anode, or by current limiting
the anode driver In multiplex applications
truth table
FUNCTION
,
0
,
,
,
,
,
,
,
""
"n
;
"
"
"OPT
"Cornm.
Deo
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
typical application
COMMA
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
o
o
o
o
o
o
o
o
0
0
0
0
U
1
0
1
0
0
0
0
0
1
0
I
0
I
1
1
0
0
1
1
I
0
0
1
0
0
0
I
0
0
0
1
0
0
0
0
1
0
1
1
1
I
0
0
0
0
1
0
1
0
1
I)
I)
1
I)
I)
1
1
1
1
0
1
0
0
1
0
I)
{)
I
0
1
0
0
0
1
f~
,
,
,
,
,
,
,
,
,
0
, ,
,
, ,, , , ,
,
,
,
,
, , , , , ,
, , ,
, , , ,
, ,
, , , , , , ,
, , , , , , , , ,,
, , , '1' , , , ,
0
0
0
's
0
r:J
0
0
0
C}
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
l
0
J
,
2
3
'-I
5
1:::.1
0
°,
,
,
p Comm.
"Decimal pomt and comma can be dISplayed w.lh or Wllhout any numeral
typical performance characteristics
(see DM7880 data sheet)
1·229
Ln
00
00
00
Series 54/74
:!!
c
DM8885 MOS to high voltage cathode buffer
general discription
The DM8885 Interfaces MOS calculator or counterlatch-decoder-drlver circuits directly to sevensegment high-voltage gas-filled displays The SIX
Inputs A, B, D, E, F, G are decoded to drive the
seven segments of the tube.
multiplex operation. The output current IS adjusted
by connecting a program resistor (Rp) from Vee to
the program Input.
Each output constitutes a switchable, adjustable
current source which prOVides constant current to
the tube segment, even with high tube anode supply
tolerance or fluctuation These current sources have
a voltage compliance from 3V to at least 80V. Each
current source IS ratloed to the b-output current
as required for even illumination of all segments.
Output cu rrents may be varied over the 0.2 to
1.5 mA range for driVing various tube types or
• Current source outputs
• Adjustable output currents 0.2 to 1.5 mA
connection diagram
features
• High output breakdown voltage 80V min
• SUitable for multiplex operation
• Low fan-In and low power
• Blanking via program input
• Also drives overrange, polarity, decimal pOint
cathodes
truth tables
Dual-In-Line Package
PROG
A
B
D
E
F
G
DISPLAY
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
'-'
0
1 (OFF)
,?
1
a(ON)
a
1
0
0
1
1
1
1
1
1
1
0
1
1
0
GND
1
1
1
1
1
0
0
1
1
0
1
1
1
0
0
0
a
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
0
a
1
a
a
1
1
1
1
1
0
0
0
0
0
0
a
a
/
:::J
_I
5
J;
-I
I
1
EI
'3
1
b
q
1
1
ILl
Fi
I I
a
U
1
E/
a
TOP VIEW
typical applications
'5V
'5V
---i
v" 0-"'-;--0
____ .J
-12V
Open-Drain MOS Output
1-230
OUTPUT*
-<-POSItive LogiC
'-I
a
1
1
INPUT'
I I
Push-Pull MOS Output
c
s:
absolute maximum ratings
00
00
00
electrical characteristics
(Note 3)
PARAMETER
,
C11
7V
6V
80V
600mW
50mA
O°C to +70°C
-65°C to +150°C
300°C
Vee
Input Voltage
Segment Output Voltage
Power Dissipation (Note 1)
Transient Segment Output Current (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
CONDITIONS
MIN
TYP
MAX
UNITS
Logic "1" Input Voltage
V cc =47SV
Logic "0" Input Voltage
Vcc=475V
Logic "1" Input Current
Vee
==
5 25V, VIN '" 2 4V
2
15
~A
Vee
==
5 25V, VIN -; 5 5V
4
400
~A
Logic "0" Input CUrrent
Vee
==
5 25V, VIN
-300
-600
~A
Power Supply Current
Vee"" 5 25V, All Inputs '"
22
31
mA
Input Diode Clamp Voltage
Vcc=5V,tIN""-12mA,TA=2SoC
-09
-15
V
20
08
==
0 4V
av,
Rp "" 2 2k
V
III
V
Segment Outputs
084
093
102
1 12
125
138
Outputs a, f, 9 On Current Ratio
All Outputs = SOY, Output b Curr == Ref
Output c On Current Ratio
All Outputs" SOY, Output b CUfr == Ref
Output d On Current RatiO
All Outputs" SOY, Output b Curr
==
Ref
090
100
110
Output e On Current
All Outputs
==
Ref
099
110
121
RatiO
Output b On Current
==
50V, Output b Curr
mA
Vee'" 5V, VOUT b '" 50V, T A'" 25°C, Rp '" 18 1k
018
020
022
Vee'" 5V, VOUT b= 50V, TA "" 25"C, Rp =703k
045
050
055
mA
Vee=5V, VouTb= 50V, TA '" 25°C, Rp= 340k
090
100
110
mA
Vee'" 5V, VOUT b'" 50V, T A'" 25"C, Rp
135
mA
==
220k
Output Saturation Voltage
Vee'" 4 75V, IOUTb '" 2 mA, Rp '" lk ± 5% (Note 4)
Output Leakage Current
VouT"'75V,VIN=08V,
Output Breakdown Voltage
IOUT::= 250 }.lA, V IN
~p:o:lk
VOUT= 75V, VpROG '" 0 4V
=
0 8V
80
150
165
08
25
0003
3
~A
0003
3
"A
110
V
V
Propagation Delays
I nput to Segment Output
Vee'" 5V, TA '" 25°C
04
10
~;
Note 1: MaXimum Junction temperature IS 130°C. For operating at elevated temperatures, the deVice must be derated based
on a thermal resistance of 150° C/W e JA.
Note 2: In all applications transient segment output current must be limited to 50 mAo ThiS may be accomplished m DC applications by connecting a 2 2k resistor from the anode-supply filter capacitor to the display anode, or by current Ilmltmg the
anode driver In multiplex applications,
Note 3: Min/max limits apply across the guaranteed operating temperature range of O°C to +70°C, unless otherWise speCified
Typlcals are for Vee = 5V, TA = 25°e POSitIVe current IS defmed as current Into the referenced pm
Note 4: For saturation mode the segment output currents are externally limited and ratloed
typical performance cha racteristics
(see DM7880 data sheet)
1·231
Series 54H/74H
illS
REFERENCE
The following table references all Physical DimenSion Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below.' Refer to the alpha-numerical index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
Pg.
DM54HOO
DM74HOO
DM54H01
DM74H01
DM54H04
DM74H04
DM54H05
DM74H05
DM54H08
DM74H08
DM54H10
DM74H10
DM54H11
DM74H11
DM54H20
DM74H20
DM54H21
DM74H21
DM54H22
DM74H22
DM54H30
DM74H30
DM54H40
DM74H40
DM54H50
DM74H50
DM54H51
DM74H51
DM54H52
DM74H52
DM54H53
DM74H53
DM54H54
DM74H54
DM54H55
DIVI74H55
DM54H60
DIVI74H60
DM54H61
DM74H61
DM54H62
DM74H62
DM54H71
DM74H71
DM54H72
DM74H72
DM54H73
DM74H73
DM54H74
DM74H74
DM54H76
DM74H76
DM54H78
DM74H78
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-6
Fig.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
3
3
Cavity DIP (D)(J)
Pg.
Fig.
Pg.
Type
II
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
11
11
11
11
12
12
11
11
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Fig.
Pg.
Type
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9,
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-9
TEST
CIRCUITS
Fig.
Pg.
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
'Order Numbers: use DeVice No. suffixed with package letter, i.e. DM54HOOJ.
2-i
en
.
CD
Series 54H/74H
CD
VI
Series DM54H/DM74H
general description
The Series 54H/74H extends the breadth of the
Series 54/74 Family by adding a product IIr,e
which IS approximately tWice as fast as the basic
series. The products are completely miscible
connection diagrams
DM54HOO/DM74HOO
quad 2-lnput NAND gate
DM54H05/DM74H05
hex Inverter
within a system, and it IS generally considered
good engineering to optimize a design by utilizing
the Series 54H/74H only where needed for higher
speed.
Dual-in-Line Package Only (Con't on Page 2-6)
DM54H01/DM74HOl
DM54H04/DM74H04
hex Inverter
quad 2-lnput NAND gate
(open collector!
DM54H08/DM74H08
quad 2-lnput AND gate
DM54Hl0/DM74Hl0
triple 3-lnput NAND gate
(open collector!
7
GND
DM54Hll/DM74Hll
triple 3-mput AND gate
DM54H20/DM74H20
dual 4-lnput NAND gate
DM54H21/DM74H21
dual 4-lnput AND gate
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
dual 4-lnput NAND gate
8-Input NAN 0 gate
dual 4-mput NAN 0 buffer
(open collectod
21
operating conditions
absolute maximum ratings
Supply Voltage
Input Voltage
7V
5.5V
Supply Voltage
DM54HXX
DM74HXX
Operating Temperature Range
Series 54H
Series 74H
Storage Temperature Range
Lead Temperature (Soldering, 10 seel
-55°e to +125°e
O"e to +70o e
-55°e to +150o e
3000 e
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
125
70
°e
°e
Temperature
DM54HXX
DM74HXX
..
!II
.~
G)
CI)
electrical cha racteristics
PARAMETER
MIN
CONDITIONS
Input Diode Clamp Voltage
Vee = 5 OV. TA = 25"C, liN = -12 mA
Logical "1" Input Voltage
Vee = Mm
Logical
"a"
Input Voltage
TVP
MAX
-15
UNITS
V
V
20
08
Vee = Min
V
Logical "1" Output Voltage
All Devices, Except DM54H40/DM74H40
and Open Collector C Ireu Its
DM54H401DM74H40
Vee
= MIn,I" = -5001'A, V ,N = 2 OVor 08V
24
V
Vee
= Min,
24
V
Vee
=
Vee
0
10 = -1 5 mA, V IN
= 2 OV or 0 8V
Logical "0" Output Voltage
All Devices, Except DM54H40/DM74H40
DM54H40/DM74H40
Logical "1" Output Current
All Open Collector C,rcults
Except DM54H60,DM54H62
DM74H60,DM74H62
DM54H611DM74H61
04
04
Min, 10 20 mA, \lIN = 2 OV or 0 8V
Min, 10 - 60 mA, V ,N - 2 OVor 08V
Vee - Min. V OUT
@ -55"C
@O"C
= 5 5V. V ,N - 2 OV or 0 8V
V
V
250
320
570
50
I'A
I'A
I'A
I'A
-40
-100
mA
-40
-125
mA
VouT=22V
Output Short Circuit Current (Note 1)
All CirCUits Except DM54H40/DM74H40
Vee = Max, V OUT
= OV
and Open Collector Circuits
DM54H40/DM 74H40
Supply Current
Vee
MdX
DM54HOO/DM74HOO
Logical "0"
Logical' 1"
DM54H01/DM74HOl
Logical "0"
Logical "1"
26
10
40
168
mA
mA
26
68
40
10
mA
mA
40
16
58
26
mA
mA
40
16
58
26
mA
mA
42
28
64
40
mA
mA
195
75
30
'26
mA
mA
13
5.0
20
84
mA
mA
20
12
32
20
mA
rnA
13
34
20
50
rnA
rnA
DM54H04/DM74H04
Logical "0"
Logical" 1"
DM54H05/DM74H05
Logical "0"
Logical "'"
DM54H08/DM74H08
Logical "0"
Logical "1"
DM54H101DM74Hl0
Logical "0"
Logical "'"
DM54H201DM74H20
Logical "0"
Logical "1"
DM54H21/DM74H21
Logical "0"
Logical "I"
DM54H22/DM74H22
Logical "0"
Logical "1"
Note 1: Not more than one output shorted at a time. duration of short-CircUit test not to exceed 1 second, and all tYPical
values are at Vee = 5V, TA = 25"e
C/)
CD
...
electrical characteristics (con't)
CD
en
MIN
CONDITIONS
PARAMETER
TYP
MAX
UNITS
65
25
,0
42
rnA
rnA
25
104
40
,6
rnA
rnA
,52
82
24
,28
rnA
rnA
'52
20
24
3,
rnA
rnA
94
7,
,4
rnA
rnA
DM54H30/DM74H30
Logical "0"
Logical "1"
DM 54H40/DM 74H40
Logical "0"
Logical "1"
DM54H50/DM74H50
DM54H511DM74H5'
Logical "0"
Logical "1"
DM54H52/DM74H52
Logical "0"
Logical "1"
DM54H53/DM74H53
DM54H54/DM74H54
Logical "0"
Logical "1"
DM54H55/DM74H55
Logical "0"
Logical "1"
,
"
75
45
,2
64
rnA
rnA
,9
30
35
45
rnA
rlA
"50
,6
70
rnA
rnA
38
60
70
90
rnA
rnA
OM 54H601 DM 74H60
On Level Current
Off Level Current
DM54H6'/DM74H6'
On Level Current
Off Level Current
DM54H62IDM74H62
On Level Current
Off Level Current
DM54H7'/DM74H7'
,9
30
rnA
DM54H72/DM74H72
,6
25
rnA
DM54H73/DM74H73
32
50
rnA
DM54H74/DM74H74
30
50
rnA
DM54H76/DM74H76
32
50
rnA
DM54H78/DM74H78
32
50
rnA
MAX
UNITS
62
59
10
10
ns
ns
75
10
12
15
ns
ns
65
60
10
10
ns
ns
75
10
,2
15
ns
ns
88
76
,2
12
ns
ns
switching characteristics
PARAMETER
TA
= 25°C, Vee = 5V, N = 10, C = 25 pF,
CONDITIONS
MIN
RL
= 28O"
TYP
DM54HOO/DM74HOO
tpdO
tpd'
DM54H01/DM74H01
tpdo
tpd1
DM54H04/DM74H04
tpdO
tpd1
DM54H05/DM74H05
tpdO
tpd'
DM54H08lDM74H08
tpdO
tpd1
2-3
switching characteristics (con't)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
63
59
10
10
ns
ns
8.8
76
12
12
ns
ns
70
60
10
10
ns
ns
88
76
12
12
ns
ns
75
10
12
15
ns
ns
89
68
12
10
ns
ns
65
85
12
12
ns
ns
62
68
11
11
ns
ns
62
68
11
11
ns
ns
92
106
15
15
ns
ns
62
70
11
11
ns
ns
62
70
11
11
ns
ns
65
70
11
11
ns
ns
DM54H10IDM74H10
tpdO
tpdl
DM54H11/DM74H11
VI
tpdO
Q)
...
tpdl
DM54H20/DM74H20
Q)
C/)
tpdO
tpdl
DM54H21/DM74H21
tpdO
tpdl
DM54H22/DM74H22
tpdO
tpdl
DM54H30/DM74H30
tpdO
tpdl
DM54H40/DM74H40
tpdO
tpdl
DM54H50/DM74H50
tpdO
tpdl
DM54H51/DM74H51
tpdO
tpdl
DM54H52/DM74H52
tpdO
tpdl
DM 54H53/DM 74H53
tpdO
tpdl
DM54H54/DM74H54
tpdO
tpdl
DM54H55/DM74H55
tpdO
tpdl
DM54H60/DM74H60
(Thru Expandable Gates)
tpdO
tpdl
74
114
ns
ns
98
148
ns
ns
74
11.4
ns
ns
DM54H61/DM74H61
(Thru Expandable Gates)
tpdO
tpdl
DM54H62/DM74H62
(Thru Expandable Gates)
tpdO
tpdl
DM54H71/DM74H71
tpdO(CLOCK)
tpdl (CLOCK)
tpdO(PR ESET)
tpd 1 (P RESET)
2-4
22
14
12
60
27
21
24
13
ns
ns
ns
ns
en
...
CD
switching characteristics (con't)
CD
(/)
PARAMETER
MIN
CONDITIONS
25
MaxImum Clock Frequency
TYP
MAX
UNITS
ns
30
DM54H721DM74H72
DM54H731DM74H73
DM54H761DM74H76
DM54H78/DM74H78
22
14
12
60
tpdO(CLOCKI
tpdHCLOCK)
tpdO(CLEAA,PRESETI
tpd1 (CLEAA,PRESET)
25
MaxImum Clock Frequency
27
21
24
13
ns
ns
ns
ns
ns
30
DM54H74/DM74H74
13
tpdO(CLOCKl
85
t pd 1(CLOCK)
tpdO(CLEAR,PAESETl
tpdl (CLEAR,PAESET)
35
MaxImum Clock Frequency
43
20
15
30
20
ns
ns
ns
ns
ns
loading table
DEVICES
DM54HOO/DM74HQO
OM54HQ1/DM74HOl
DM54H04/DM74H04
DM54HOS/OM74H05
DM54H08/DM74H08
DM54Hl0/DM74H 10
DM54Hl1!DM74Hl1
DM54H2OJDM74H20
DM54H21/DM74H21
DM54H22/0M74H22
DM54H30/0M74H30
DM54H40/0M74H40
DM54H50/DM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
WEIGHTED
LOADS
1
1
1
1
1
1
1
1
1
1
1
2
DM54H611DM74H61
1
1
1
1
1
1
1
1
DM54H62/DM74H62
DM54H71/DM74H71
1
DM54H54/DM74H54
DM54H55/DM74H55
DM54H60/DM74H60
1
All Inputs Except
Preset and Clock
Preset
Clock
DM54H72/DM74H72
Ali Inputs Except
Preset and C lear
Preset, Clear
1
3
2
1
2
DM54H73iDM74H73
J, K, and Clock
Clear
1
2
DM54H74/DM74H74
D
1
Preset and Clock
2
Clear
3
DM54H761DM74H76
J, K, and Clock
Preset and Clear
1
2
DM54H78/DM74H78
J and K
Preset and Clock
Clear
1 Load
1
2
4
= 50 I1A @24V Logical "1" Input Current
= 2 rnA @O 4V Logical "0" Input Current
(All Inputs are guaranteed 1 rnA @ 5 5V for Logical
"1" breakdown test)
2-5
connection diagrams (con't)
en
Q)
...
Q)
DM54H50/DM74H50
DM54H51/DM74H51
(/)
expandable dual 2-wlde
2-lnput AND-OR-INVERT gate
dual 2-wlde 2-H1PUt
AND-OR-INVERT gate
DM54H52/DM74H52
expandable 2-2-2-3-,nput
AND-OR gate
GNO
DM54H53/DM74H53
expandable 2-2-2-3-lnput
AND-OR-INVERT gate
DM54H60/DM74H60
dual 4-lnput expander
DM54H54/DM74H54
4-wlde 2-lnput
AND-OR-INVERT gate
DM54H61/DM74H61
triple 3-lnput expander
DM54H55/DM74H55
expandable 2-wlde 4-lnput
AND-OR-INVERT gate
DM54H62/DM74H62
3-2-2-3-mput expander
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73/DM74H73
J-K flip flop With AND-OR Inputs
J-K master-slave flip flop
dual J-K flip flop with
separate clocks
DM54H74/DM74H74
DM54H76/DM74H76
DM54H78/DM74H78
dual 0 edge-tnggered flip flop
dual J-K master-slave flip flop
dual J-K flip flop With preset
and clear Inputs
2-6
en
CD
.,
ac test circuits
CD
til
Ifcco5V
o INPUT
SH NOTE B
<,
~25pF
-¥EENOTEC
NOTE A Clock Input pulse has the folhlwlng charactenstlcs
tW1ClOCK) = 20 ns, PRR = 1 MHz
NOTE B 0 Input (pulse A) has the following characterIStics
ISETUP = 10 os, !w = 60 ns, PAA IS 50% of clock PRR 0 mput
(pulse 8~ has the following chara~tenst'cs tHOLD
60 ns, PRR IS 50% of clock PRR
NOTE C CL Includes probe and 119 ~3pacltance
~
0 01, !w "
Switching Characteristics, Clock and Synchronous Inputs
(High Level Datal
c,
SHNOTEC
J25~F
DINPUT
SEENOHB
NOTE A Clock Illput pulse has the following Eharacteflstlcs
20 os, PRR = 1 MHz
NOTE B 0 Input (pulse AJ has the following characteristics
'SETUP ~ 15 "S,!w = 60 os, PRR '" 1 MHz and PRR IS 50% of
!w =
nSf oj---l-~==:jr------t==-_j-oTEST
OUTPUT
theclotkPRR Dmput(pul~eB)lIasthefoIlOWlllgcllaractenstlcs
IHOLO '" 0 ns, tw
60 ns, and PRR IS 50% 01 dock PRR
NOTE C Cl Intludes plObe and I'g capacitance
OUTPUT
;0
Switching Characteristics, Clock and Synchronous Inputs
(Low-Level Datal
,----;;:-I
280"
I
SEENOHC
C,
~15Pf
I
I
I
I
I
I
I
I
c,
2~PF1'
SEE NOTE C
I
I
IL-
~
I
I
I
~J\~~~J
.,r.,PAESH
--....., INPUT
NOTE A Clear or Preset Inputs 31e dommate fegardless of clock
orJKlnputs
NOTE B Clear or Preset Input pulse charactemtlcs V,NII' = lV,
VINI01 = OV, t1 ~ 10 ~ 1 ns tpIClEAA) ~ tp(PAESETI = 16 ns,
PRR'" 1 MHz
NOTE C CL mclud~Jlycapacltance
''''
OUTPUT
Flip Flop Preset/Clear Propagation Delay Times
IJ cc
SEE NOTEC
J25 PF
C,
PRESET
INPUT
=
51J
25 PFJ
C,
SEE NOTE C
CLEAR
INPUT
NOTE A Clnr and Preset Inpllt dominate clod or 0 inputs
NOTE B Clear or Preset mpulse cllaractemtlcs tW(CLEAAI =
tWIPRESETI = 25 ns, PRR = I MHz
NOTE C CL inCludes probe and Jig capaCitance
Asynchronous Inputs Switching Characteristics
Vcc- 5V
ac test circuits (con't)
-,
~
GATE
PULSE
BEING
GEtiERATOA
TESTED
I
I
SEE NOTE A
1'"
CI)
...
CI)
en
L- _ _ _
NOTE A V'NW" 3V, V'NUlI- ov, to" I, "7 RS, duty
NOTE B Cl.lncludesJlgcapacltance
NOTE C C. mcludesllgcapacltance
~v~le
- 50%. PRR " 1 MHz, ZOUT
~
I
NOTE A The pulse generat~r has the follllWlng
characteristics V,nlll = lV, VmIO) " DV. I, = to = 7
AS,PRR=1 MHl.dutycvcle~ 50%,andZout 'I to • 7 ns, IptCLOCkl = ZO ns, and PRR = 1 MHz
NOTE B All J and K Inpu15 Ire at 2 4V
NOTE C Wh&l1 testing fCLOCk Ihe clock IOput characttl'l5tlCSlte V1NIDI ~ 3V, VINCOI = OV, 1, = to = 3 nt,
"'(cLOCkl = 10 lIS, PRR = 40 MHz All J and K inputs aleal2 4V
NOTE 0 CL IlICIudes probe and Jlgcapacltancl
t,
Flip Flop Propagation Delay Times
II cc '511
truth tables
tn
tn+1
J
K
0
0
1
1
0
1
0
1
a
a
0
1
ON
all J-K flip flops
NOTE A VtNI1I = 3V, V1NIDI = OV, 10 = tl = 1 AS, duty cycle = 50%, PRR = 1 MHz
NOTES CLHlcluliesprobelndllgcaplCltlInc:e
NOTEC Ci H1cludesllgcaplcttan;e
DM54H50, DM54H53, DM54H55
2-8
~I
Vee = 511
r--;;;----l
IL-
_
L!!.!!..r~_--=
DM54H52/DM74H52 Loadong For Gates
DM54H52/DM74H52
I
I
tn
tn+1
0
0
ala
1
0
0
,I
1
DM74H74 only
en
...
~
switching time waveforms
3V
CLOCK
INPUT
OV
<7 ns
3V
o INPUT
(PULSE A)
(SEE NOTE BI
10%
OV
,,7m
~
o INPUT
3v
90%
(PULSE 8)
(SEE NOTE BJ
- OV
Ve"
Q OUTPUT
15V
Vee
Ve "
0: OUTPUT
15V
NOTE A Clock Input pulse has the follolll/lIlg charactemllCS 1,,[CLOCKi 20 ns, PRR
NOTE B 0 Input (pulse
~ 10 os, tw =
clock PRR 0 Input (pulse
= 0 <1$
=
dock PRR
NOTE C Cl Includes probe and Jig capacitance
1 MHz
'w
Switching Characteristics, Clock and Synchronous Inputs
(High Level Datal
~-~-----3V
CLOCK
INPUT
~~~--------------------OV
~~~-------------3V
INPUT
(PULSE A)
(SEE NOTE 8)
-; 7 ns
Jc~--------------~~-i-------3V
o INPUT
(PULSE)
(SEE NOTE HI
1'--""'------- OV
n OUTPUT
' - - - - - - - - - - - - - - - - - - - - - - - - - V"
nOUTPUT
r-----------------------
yO"
- - - - - - - - - - - - - V"
NOTE A Clock IIlput pulse has the follOWing chalactemtlCS lw = 20 nil, PRR = 1 MHz
NOTE 8 0 Input (pulse A) has the follOWIng characterlstlcs 'SETUP ~ 15 ns, lw ~ 60 ns, PRR = 1 MHz
and PRR IS 50% of the clod PRR 0 Input (pulse B! has the follOWing characteristics tHOLO ~ II ns,
t..,. ~ 611 ns, and PRR IS 50% of clock PRR
NOTE C CL Indudes probe and Jig capacitance
SWltchmg Characteristics, Clock and Synchronous Inputs
(Low Level Data)
switching time waveforms (con't)
CLEAR
INPUT
en
PRESET
G)
INPUT
...
G)
(fJ
Q OUTPUT
0: OUTPUT
NOTE A Clear OJ Preset inPuts are dllmlllate re~ar~tess of cloc~ or JK Inputs
NOTE B Clear 01 Preset IO!lUI pulse charactemtlcs VINlt ) ~ 3V, VINIOI = 0\1,
I, ~
to
~
7 ns, IplCLEARI "
~ 16 ns, PRR = 1 MHz
NOTE C CL meludes 119 CaDaWaI1C~
lplPAEsEn
Flip Flop Preset/Clear Propagation Delay Times
3V
CLEAR
INPUT
OV
3V
PRESET
INPUT
v"
Q OUTPUT
1 5V
v"
QOUTPUT
-=;v=
'~(
I 5\1
Vo ,
15V
Vo<
NOTE A Clear and Pr~t mput dominate cloek or 0 inputs
NOTE B tlnf or Preset !"pulse characteristICS t..(CLEA.II)
NOTE C Cl mcludesprobendllgcapacllance
"t..\PREst:T) =
25 os, PRR " 1 MHz
Asynchronous Inputs SWitching Characteristics
Ir-:=-----:::::::-~--+----
VINIII
INPUT
OUTPUT
VO UnDI
NOTE A V1NIU" 3V, VINIOI" 0\1, to" I, = 1 os, duty cycle = 50%, PRR = 1 MHz, ZOUT'" 5011
NOTE B Cl Includes 1111 caplcltanee
NOTE C C. Includes 1111 capacItance
DM54H52/DM74H52
2-10
CJ)
...
CD
switching time waveforms (can't)
CD
!II
C
s:
V IN11 )
INPUT
0'1
~
V"'1lOl
:J:
VOUTI11
"C
INVERTING
s:.....
OUTPUTS
VOUTIOi
~
V OUT1 ,)
:J:
NON INVERTING
OUTPUTS
VOUTIOI
NOTE A V 1N (1! ~ JV, VINIO) OV, I, = to 7 m, PRR
NOTE B CL Includes probe and 119 capacitance, RL =
NOTE C CL 25 pF on all devices
NOTE 0 C.
=
=
1 MHz, duty cyd~ = 50%, lOUT"" 50%
on all giltes except OM54H4D where RL
Z80~1
=
9311
I 3 pF typical for expanders
DM54H52/DM74H52 Propagation Delays
ir-::::,----..",,::-.J-+-----
VINlll
CLOCK
INPUT PULSE
!'-'''''----V1r,lIOI
,-_____+ _____
VINlll
'------+-----VIN10I
------------i---x--QOR
V OUTlll
oOUTPUT
VOUTIOJ
VOUTI11
Q OUTPUT
------------I-'---~
VOlJTIOJ
NOTE A Wilen testing tp~o and tpdl (all types). the dock Input pulse charactetlsttcs are VINlll '" JV,
VINIOI '" nv, 11 = to ~ 7 liS, '",CLOCK) = 20 liS, alld PRR = 1 MHz
NOTE B All J and K 1I1putsare at 2 4V
NOTE C When testing fCLOCK the clock Input charactenstlcs are VINIOi" lV, VIN10I "OV, t, ~ to 3 ns,
tplCLQCKi " 10 ns, PRR" liD MHz All J and K mputs are at 2 IIV
NOTE 0 CL Includes probe and Ilg capacitance
Flip Flop Propagation Delay Times
V-::=----:::"""'J~+-----
VINlll
INPUT
1"-=----VINIOI
OUTPUT
---+--'+----VQUTIOI
NOTE A VINlll" 3V, VINIOi "OV, to 11 = 7 ns, duty cycle
NOTE B CL Includes probe and Ilgcapacltance
NOTE C ex mdudes 119 capacitance
50%, PRR
1 MHz
DM54H50, DM54H53, DM54H55
2-11
CJ)
CD
Series 54L/74L
~s
REFERENCE
The following table references all Physical Dimension Drawings for the devices In this section For Order
Numbers, see below. * Refer to the alpha-numerical Index at the front of this catalog for complete device
title and function Packages (pages I thru VI) are In the back of the catalog
DATA SHEETS
PACKAGES
Molded DIP IN}
Devices
DM54LOO
DM74LOO
DM54LOl
DM74LOl
DM54L02
DM74L02
DM54L03
DM74L03
DM54L04
DM74L04
DM54L10
DM74Ll0
DM54L20
DM74L20
DM54L30
DM74L30
DM54L42A
DM7.4L42A
DM54L51
DM74L51
DM54L54
DM74L54
DM54L55
DM74L55
DM54L71
DM74L71
DM54L72
DM74L72
DM54L73
DM74L73
DM54L74
DM74L74
DM54L78
DM74L78
DM54L85
DM74L85
DM54L86
DM74L86
DM54L90
DM74L90
DM54L91
DM74L91
DM54L93
DM74L93
DM54L95
DM74L95
DM54L98
DM74L98
DM54L154A
DM74L 154A
DM54L 165A
DM74L165A
DM54L192
DM74L192
Pg
Fig
3-3
33
33
3·3
33
33
33
33
33
3·3
33
33
33
33
33
33
331
331
3-7
37
37
37
3-7
3-7
3·10
3·10
310
3·10
3-10
3·10
3-10
310
310
3-10
3·34
3-34
3-22
3·22
3·37
3·37
3-40
3·40
3-42
3-42
3-25
3·25
3·45
3-45
3-47
3-47
3-49
3-49
3·52
3-52
3
3
3
3
3
3
3
:3
3
3
3
3
3
3
Fig.
Pg
Type
Fig.
Pg.
Type
II
II
11
11
IV
IV
J
J
15
15
15
15
15
15
IV
IV
IV
IV
IV
IV
F
15
15
15
15
15
15
15
15
lei
lG
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
15
15
15
15
15
15
15
15
15
15
16
16
17
17
16
16
16
16
IV
IV
IV
IV
1\'
II
II
II
II
II
II
II
II
II
II
3
3
3
3
3
3
II
3
3
3
3
5
5
3
3
3
3
3
3
3
3
3
3
5
5
7
7
5
5
5
5
II
II
II
II
II
II
II
II
II
II
II
II
5
3
3
3
3
3
3
Flat Pack IF}(W}
Pg.
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
!)
Cavity DIP ID}IJ}
II
II
II
II
II
II
III
III
II
II
II
II
11
11
11
11
11
11
11
11
11
11
11
11
Q
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
9
11
11
11
11
11
11
11
11
11
11
12
12
10
10
12
12
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
1\
1\
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
.J
J
J
.J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
D
D
J
J
J
J
*Order Numbers. use DeVice No suffixed with package letter,
1.8
IV
IV
IV
V
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
V
V
V
V
V
V
V
Metal Can IG}(H}
Fig
Pg
Type
WAVE·
FORMS
Fig
Pg
TEST
CIRCUITS
Fig
Pg
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
DM54LOOF
3-i
...
Q)
t/)
PACKAGES
DATA SHEETS
Molded DIP (N)
Devices
OM54L193
OM74L193
OM71 L22
OM81 L22
OM71 L23
OM81 L23
OM75L 11
OM85L11
DM75L 12
DM85L12
DM75L51
DM85L51
DM75L52
DM85L52
DM75L54
DM85L54
DM76L70
DM86L70
DM76L75
DM86L75
DM76L76
DM86L76
DM76L93
DM86L93
DM78L12
DM88L12
Pg
3-52
3-52
3-59
3-59
3-59
3-59
3-63
3-63
3-66
3-66
3-69
3-69
3-74
3-74
3-74
3-74
3-25
3-25
3-80
3-80
3-80
3-80
3-42
3-42
3-82
3-82
Cavity DIP (O)(J)
FIg
Pg
FIg
Pg
Type
FIg
Pg
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3
3
5
5
5
5
3
3
3
3
II
I
12
12
12
12
12
12
9
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
0
D
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
15
16
16
16
16
15
15
15
15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
F
F
F
V
IV
IV
V
V
V
V
IV
IV
IV
IV
F
F
F
F
F
9
II
II
II
II
II
II
II
II
II
12
12
12
12
12
12
12
12
11
11
12
12
12
12
11
11
11
11
.
3-ii
Flat Pack (F)(W)
J
Type
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Metal Can (G)(H)
FIg
Pg
Type
WAVE·
FORMS
F,g.
Pg.
TEST
CIRCUITS
FIg
Pg.
,...
o
$1
Series 54L/74L
"'CJ
o
.
$1
CD
LOW POWER TRANSISTOR-TRANSISTOR LOGIC
general description
The Series 54L!74L family IS designed for applicatIOns requiring very low power dissipation.
Typically a system can be built with a factor-of·
ten power saving over the conventional TTL
Integrated circuits, such as Series 54/74. Gates
typically draw 0.2 mA from a 5 volt supply thus
dissipating 1 mW. Flip flops pull about 1.0 mA
and therefore dissipate about 5 mW. Speed however is not proportionately sacrificed. Flip flops
can typically be clocked at 11 MHz. Gate delays
are tYPically 25 ns.
The Series IS manufactured with TTL circuitry and
employs low impedance Darlington outputs which
maintain output voltage waveform integrity when
capacltlvely loaded. The Darlington outputs also
allow greater guaranteed logical "1" fan out (20)
in case It IS desirable to connect unused Inputs to
used Inputs.
National's Low Power Series is also guaranteed to
drive two standard TTL Unit loads from ODC to
70D C.
features
• Low power diSSipation-typically 1 mW/gate,
5 mW/fllp flop.
• Relatively high speed
TYPical gate propagation delay time of 25 ns.
Typical flip flop toggle frequency at 11 MHz.
TYPical MSI shift register toggle frequency at
12to 14 MHz.
• High
TA
=
dc nOise margin-typically
25 D C.
1 volt at
• Low Impedance Darlington outputs provide low
ac noise susceptibility.
• Fan Out
10 Series 54L loads In logical "0" state
20 Series 54L loads In logical" 1" state
2 Series 74 loads (74L only)
1 Series 54 load and 2 Series 54 L loads
1 Series 54H load.
• TTL and DTL compatible.
DeVice types speCified in the data sheet include:
NAND, NOR GATES
DM54LOO/DM74LOO (SN54LOO/SN74LOO)
Quad 2·lnput NAND Gate
DM54L01/DM74L01 (SN54L01/SN74L01)
Quad 2·lnput NAND Gate, Open Collector
DM54L02/DM74L02 (SN54L02/SN74L02) Quad
2-lnput NOR Gate
DM54L03/DM74L03 (SN54L03/SN74L03) Quad
2·lnput NAND Gate, Open Collector
DM54L04/DM74L04 (SN54L04/SN74L04)
Hex Inverter
DM54L 10/DM74L 10 (SN54L 10/SN74L 10)
Triple '3-lnput NAND Gate
DM54L20/DM74L20 (SN54L20/SN74L20)
Dual 4-lnput NAND Gate
DM54L30/DM74L30 (SN54L30/SN74L30)
Eight-Input NAND Gate
AND-OR-INVERT GATES
DM54L51/DM74L51 (SN54L51/SN74L51)
Dual 2,wlde AND·qR·INVERT Gate
DM54L54/DM74L54 (SN54L54/SN74L54)
Four-Wide 3-2-2-3-lnput AND·OR-INVERT
Gate
DM54L55/DM74L55 (SN54L55/SN74L55)
Two-wide 4-lnput AND-OR-INVERT Gate
table of contents
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-1
Absolute MaXimum Ratings . . . . . . . . . .
3-2
....
.....................
Guaranteed Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
NAND, NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-3
AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·7
Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . ..
....................
3-10
.....................
3-22
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-25
EXCLUSIVE-OR Gates. . . . . . . . . . . . . . . . . ..
3·1
...I
~
....
gen'eral description (cont.)
.......
...I
~
FLIP FLOPS
1/1
DM54L71/DM74L71 (SN54L71/SN74L711
R-S Flip Flop
an
Q)
...
Q)
DM54L78/DM74L78 (SN54L78/SN74L78)
Dual J-K Flip Flop
Operation IS the same as the DM54L 73/DM74L 73
except that common CLEAR and CLOCK Inputs
feed both flip flops ThiS frees two pins which are
used for separate PRESET Inputs.
These R-S flip-flops use master-slave construction
so the slave IS stable when the clock IS held either
high or low Clock disable at data Inputs results In
hold times of a ns, and also clock-controlled data
entry
en
..........i
...
EXCLUSIVE-OR GATES
DM54L86/DM74L86 (SN54L86/SN74L86)
Quad EXCLUSIVE-OR Gate
Q)
~
DM54L72/DM74L72 (SN54L72/SN74L72)
J-K Flip Flop
o
D..
The DM54L86IDM74L86 (SN54L86/SN74L86)
quad EXCLUSIVE-OR circuit performs as a halfadder: the output IS a logical "1" only when the
Inputs are at different logical states.
These J-K flip-flops use master-slave construction
so the slave IS stable when the clock IS held either
high or low Clock disable at data Inputs results In
hold times of a ns, and also clock-controlled data
entry
~
o
...I
SHIFT REGISTERS
DM54L95/DM74L95 (SN54L95/SN74L95)
Four-bit Parallel-In Parallel-out Shift Register
Parallel or serial operation IS selected by the
MODE Input, which also enables one of the two
clock Inputs Parallel information must be
clocked-In allOWing shift-left operation by connecting each output to the left-adjacent parallel
input.
DM54L73/DM74L73 (SN54L73/SN74L73)
Dual J-K Flip Flop
Operation IS the same as the DM54L72/DM74L72
except that only single J and K Inputs are
available.
DM76L70/DM86L70 Eight-Bit Serial-In ParallelOut Shift Register
DM54L74/DM74L74 (SN54L74/SN74L74)
Dual D Flip Flop
The DM76L70/DM86L70 utilizes Series 54L!74L
compatible TTL circuitry to provide an eight-bit
serial-in parallel-out shift register. Other features
Include gated serial Inputs for strobe capability
and a clear Input WhiCh, when taken to a logical
"0", asynchronously sets all flip flops to the
logical "0" state.
These monolithic, low-power, dual, edge-triggered
flip flops utilIZe TTL circuitry to perform D-type
flip flop logic Each flip flop has Individual clear
and preset Inputs, and complementary Q and Q
outputs
Information at D-input IS transferred to the Q
output on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level of
the clock pulse and IS not directly related to the
transition time of the positive-gOing pulse. When
the clock Input IS at either the high or low level,
the D-Input signal has no effect on the state of the
output.
Because the flip flops are R-S Instead of J-K, Input
information may be changed Immediately prior to
the triggering edge of the clock waveform Logical
"1" levels on SA and SB enter logical "1'5" Into
the shift register Clocking occurs on the posltivegOing edge of the 'clock pulse.
absolute maximum ratings
Power Supply Voltage
Input Voltage
Fan Out Logic "1"
Logic "0"
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
8 OV
55V
20
10
-65°C to 150°C
300°C
guaranteed operating conditions
3-2
Power Supply Voltage
DM54LXX, DM7XLXX
DM74LXX, DM8XLXX
4 5V to 5 5V
4.75V to 5.25V
Operating Temperature
DM54LXX, DM7XLXX
DM74LXX, DM8XLXX
-55°C to 125°C
O°C to 70°C
NAND, NOR GATES
DM54LOO/DM74LOO, DM54LOl /DM74L01, DM54L02/
DM74L02, DM54L03/DM74L03, DM54L04/DM74L04,
DM54L 10/DM74L 10, DM54L20/DM74L20,DM54L30/
DM74L30
schematic diagrams
-I
-I
r-
en
(1)
500
'OK
..,
40K
(1)
en
'OK
DM54L01/DM74L01
DM54L03/DM74L03
DM54LOO/DM74LOO, DM54L 10/DM74L 10
DM54L20/DM74L20,DM54L30/DM74L30
soon
'OK
40K
o
500
40K
12K
DM54L04/DM74L04
DM54L02/DM74L02
dual-in-line package connection diagrams
DM54LOO/DM74LOO
DM54L03/DM74L03
DM54L02/DM74L02
DM54L04/DM74L04
3-3
SUMMARY
dual-in-line package connection diagrams (cont.)
114
....
113
"
11110
19 10
lI-
~
,
DM54L 10/DM74L 10
2
DM54L20/DM74L20
,
.
,
~
.
DM54L30/DM74L30
NAND. NOR GATES
flat package connection diagrams
13
12
'N'
11
DM54LOO/DM74LOO
DM54L01/DM74L01
"r-+'~J_+'~2_~~-f"~-f-;
DM54L 10/DM74L 10
I4
r T'"-T'"--=-f-f-,
DM54L02/DM74L02
DM54L04/DM74L04
Ne
GND
3-4
GND
GND
"
DM54L20/DM74L20
Ne
GND
DM\j4L30/DM74L30
I'
r-
o
~
NAND, NOR GATES
."
dc electrical characteristics
o
~
...
Cl)
SYMBOL
PARAMETER
V1N1l)
Logical "1" Input Voltage
VINIO)
Logical "0" Input Voltage
CONOITIONS
TEST
FIGURE
Vee = MIN
1
Vee '" MIN
2
TYP
(NOTE 11
MIN
2
MAX
13
UNITS
-I
-I
V
07
13
V
r-
V
en
LogIcal "1" Output
Voltage (Except
DM54L01/DM74L01,
DM54L03/DM74L03)
Vee
:= MIN, lOUT = -200 pA.
V," = 0 7V, Other Inputs'" 2V
2
Output Current
VIN =03V,V cc =MIN,
V OUT = 5 5V
6A
50
"A
OM54L01/DM54L03
VIN =06V,V cc =MIN,
V OUT = 5 5V
6A
200
"A
DM74LQ1/DM74L03
V IN = 0 7V, Vee = MIN,
V OUT =55V
6A
200
"A
VOUT(Q)
Logical "0" Output Voltage
Vee := MIN, lOUT = 2 mA,
VIN (Allinputsl = 2V
1
V OUTW )
LogIcal "0" Output Voltage
(Series 74L Only)
Vee = MIN, lOUT = 3 2 mAo
VIN (All tnp:Jts) = 2V
1
Logical "1" Input Current
Vee = MAX, V IN = 24V,
Other Inputs = OV
4
Vee
4
VOUTlll
DM54L01/0M74L03
'aUTO}
IIN(l)
iIN(Q)
Logical "0" Input Current
los
Logical" 1" Output
Short CirCUit Current
(Except
Vee'" MAX, V IN
V OUT = OV
Logical" 1 " State
Icc{O)
=
~
5 5V
a 3V,
OV,
Vee = MAX,
V 1N (All Inputs) = OV,
lOUT = 0
Power Supply Current
(Per Gate) (Except
DM54L02/0M74L02)
(Note 2)
Logical "0" State
Power Supply Current
(Per Gate) (Except
DM54L02IDM74L021
(Note 3)
Note 1: All tYPical, at T A ~ 25°C
Note 2. For the DM54L02/DM74L02, 'CCllI
Note 3: For the DM54L02/DM74L02, ' CCIO )
MAX, VIN
Vee = MAX, V IN -=
Other Inputs = 4 5V
DM54L01IDM74L01,
DM54L03IDM74L03)
ICCIII
:=
Vcc '" MAX,
V IN (All Inputs) = 5V,
24
28
015
03
V
04
V
...
Cl)
10
"A
100
"A
-120
-180
"A
-8
-15
mA
6
120
200
"A
6
330
510
"A
<1
3
5
-3
lOUT'" 0
~
~
400l'A Max
600l'A Max
ac electrica I characteristics
SYMBOL
PARAMETER
CONDITIONS
TEST
FIGURE
TYP
MAX
UNITS
30
60
os
60
100
"
7
25
60
"
MIN
tpdQ
Propagation Delay to a
Logical' 0' (ExcePt
DM54LOl IDM74LOl
DM54L03/DM74L03)
tp01
Propagation Delay to a
Logical "J" (Except
DMS4L01/DM74LOl
DM54L03IDM74L03)
Vee = SV, C L
TA - 25'C
tpdQ
Propagation Delay to a
Logical "0"
DM54L01/DM74LOl
DM54L03iDM74L03
Vee -'5V,R L =4k,
C, - 15pF,TA~25°C
171
25
60
"
tpd 1
Propagation Delay to a
Logical "1"
OM54L01/OM74LOl
DM54L03/0M74L03
Vee -5V,R L =4k,
C, 15pF, T A " 2S"C
171
40
90
os
Vee = 5V, C L -" 50 pF,
T A = 2Soc
7
OMS4L30/DM74L30
~
50 pF,
3-5
-I
o::t
t::
NAND, NOR GATES
-I
o::t
It)
DM54l03/DM14l03 open collector application data
CII
Q)
...
Q)
CJ)
The DM54L03/DM74L03 IS an open-collector LP
TTL gate, that when supplied with a proper load
resistor R L, can be paralleled with other similar
LP TTL gates to perform the wire-AND function,
and simultaneously, will drive from one to six
loads When only one gate IS wire-AND connected,
thiS gate can be used to drive eight LP TTL gates.
To meet these conditions, an appropriate load resistor value must be determined for the desired circuit
configuration. A maximum resistor value must be
determined so that sufficient load currents Ito LP
TTL Gate Loadsl and Off Currents ITo wire-AN D
connectlonsl will be available dUring a logical "1"
level at output. Also, a minimum resistor value
must be determined which will ensure that currents
from the loads will not cause the output voltage to
rISe above the logical "0" level.
...
Q)
~
o
Il..
~
o
-I
(11
Where;
V R L ~ Voltage Drop Ivoltsl
I R L ~ Current (ampsl
The following equations will be useful In determining the value of RL IMaxl and RL (Mini:
121
RL IMlnl ~ I
N
M
To meet both conditions (logical "0" and logical
"1''1, the value of RL IS determined by:
~
~
Vee - Vout(OI
101 _ M I (01
out
(31
In
number of gates wire-AND connected
number of LP TTL loads
DM54l03/DM14l03 open collector application data
curves For Instance, for N ~ 2 and M
mum loads connected IS SIX
The maximum loads connected (MI under any
wire-OR configuration INI,s shown respectively by
the intersection of the RL (Mini and RL (Maxi
Vee' 50V
hN((lI· '80llA
VOUTlll -24V
IINIII
VOUTIO)=OJV
IOUTIII ~ 200 f.lA
~
"
12
10
=
~
5 the maxI-
ISINK :2mA
10"A
lP TTL lOADS
.1 l 1
1 1 l"- I'---
LI'TTllOAOS
RL lMAX)N = 1
RL(MAX~-Z .......
t::...
RL (MAX)N= 3,
V
I P1""" Ir'-
RL (MAX) N· 4
1 1 1
3
Rl (MIN)
4
5
6
7
B
M = NUMBER OF LP TTL LOADS
lou,i')
Logical "0"
C1fC~lt
CondItIOn
dc test circuits
OPEN
v,. 0----1
3-6
v..
Note All ,"puts are tested simultaneously
Note Each Input IS tested separately
Figure 1
Figure 2
0----1
Note
Each '"put IS tested separately
Figure 3
r-
NAND, NOR GATES
dc test circuits (cont.)
UV
V,"
o
~
'
0----1
OPEN
OPEN
V,"
~
."
Vee
o
~
~
...
CD
You.
-t
-t
r-
Note
Each mput
separately
IS
tested
Note
Each gate IS tested
separately
Notes
1
Logical "0" and logical "'"
conditions are tested
2
All gates are tested simultaneously
figure 5
Figure 4
en
Figure 6a
...
CD
Figure 6
ac test circuits and waveforms
OK
IN9,I
OK
r
IN916
"'' 1' '
lNg,S
':"
DM54l00/DM74l00, DM54l04/DM74l04
DM54l10IDM74l10, DM54l20/DM74l20
DM54l30/DM74l30
DM54l01/DM74l01
DM54l03/DM74l03
INSIS
r
1NU16
o
""'r""
1N91&
':"
DM54l02/DM74l02
'V
Note
\'----
TA
VT
125°C
70°C
25°C
o°c
_55°C
09V
llV
13V
10V
16V
Cllncludes probe and Jig capacitance
Figure 7
AND-OR-INVERT GATES
schematic diagram
DM54L51/DM74L51, DM54L54/
DM74L54, DM54L55/DM74L55
r - -...--4>-------~'-OV,'
.00
ZDK
40K
DM54l51/DM74l51, DM54l54/DM74l54, DM54l55/DM74l55
(DM54l55/DM74l55 Shown)
3-7
...J
AND-OR-INVERT GATES
'o:t
.....
.......
...J
'o:t
dual-in-line package connection diagrams
It)
II)
CI)
...J
lI-
..
CI)
~
o
Il.
DM54L51/DM74L51
~
DM54L54/DM74L54
DM54L55/DM74L55
o
...J
flat package connection diagrams
GNO
Nt
DM54L51/DM74L51
DM54L55/DM74L55
DM54L54/DM74L54
dc electrical characteristics
SYMBOL
PARAMETER
V ,N ",
LoglC~1
1
Input Voltage
Inpu! Voltage
V'NCOI
LogIcal '0
V OUTLlI
Logical
VOUT'CI
LogIcal' 0 Output Voltage
VOUTLOI
Logical 0 Output Voltage
($eroes 74L Only I
I'N<1I
LogIcal
1
Input Current
I'N'OI
Log,cal' 0
Input Current
LogIcal
1o,
ICCIlI
ICCIOI
1 Output Voltage
1 OU1PUl
CONDITIONS (Note l'
'"
TEST
TV'
FIGURE
(Note2}
'"
Vee - MIN lOUT --200J.lA V ,N '07V
24
lEach Inpu! Tested Separately)
~
'"
'"
'"
UNITS
- MIN
20V,
28
015
03
MIN,I OUT
W
• MAX, V 'N - 2 4V, Other InpUl, - OV
,A
,A
- MAX V ,N = 55V,Other Inpu!s
Vee' MAX V 'N
=
0 3V. Other Inputs
~
Vee - MAX, V ,N IAlllnpu\sl" av.
Short CirCuit Current
VOUT = OV
Log.cal I 'State
Power Supply Current
IPerGatel
Vee' MAX,
V,,,, (Allinputsl
Logical "0 State
Power Supply Current
IPerGatel
Vcc - MAX,
V,,,, (Allinputsl
lOUT = 0
12
DM54L51!OM74L51
o
OV, DM54L54IDM74L54
OM54L5510M74L55
lOUT' 0
-180
,A
240
480
240
400
800
,A
,A
,A
390
600
390
650
990
650
,A
,A
,A
45V
OM54L51IDM74LSI
5V. OM54LS4!OM74L54
OM54L55!DM74LS5
"
"
"
-3
-8
Note 1: Each Input "AND" section tested separately
Note 2: All typlcals at T A" 25°C
ac electrica I characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
TEST
FIGURE
MAX
Pro!,agatlon Delav 10 a
logical 1
Propagation Oelay 10 a
logical '0
3-8
30
60
UNITS
r-
o
ANO-OR-INVERT GATES
~
."
o
dc test circuits
~
...
CD
45V
-I
-I
r-
v,"
en
...
CD
Note
Note
Each AND section IS tested separately
Each set of Inputs IS tested separately
Note Each mput
Figure 9
Figure 8
IS
tested separately
Figure 10
~
v'" 0---=---1--.
OPEN
Note
Each Input
IS
tested separately
Note
Figure 11
Each gate
IS
Note
tested separately
All gates are tested sImultaneously
Figure 12
Figure 13
ac test circuits and waveforms (cont.)
+24V
'5V
4K
r
Note
lN91~
1N910rJO·'
lN916
T.
VT
12SOC
70°C
25'C
O'C
-55'C
09V
IIV
13V
14V
16V
CL Includes probe and 119 capacitance
Figure 14
3-9
FLIP FLOPS
DM54L71 /DM74L71, DM54L72/DM74L72, DM54L73/
DM74L73, DM54L74/DM74L74, DM54l78/DM74L78
schematic diagrams
r---------~--.-_.~----~~----~--------~~--__o'"
...
II)
~
Q
D.
~
Q
...J
SI(K1)"
Note
Dotted connections refer to
OM54l72/0M74L72 only
DM54L71/DM74L71, DM54L72/DM74L72
-.--o v"
, - - - -....--6~;TpUT
L _ _ _ _ _ _ -.J
aOUTPUT
Notes
v,
1-=
C1
30"
ISu NOle:')
TA
VT
12S"C
70°C
2S"C
O"C
-SS"C
o9V
11V
13V
14V
16V
v,
1 Clear or preset mputs dominate regardless of the state of clock or logic mputs
2 Clear or preset mput pulse characteristics tp(clead = Ip(preset)
and PRR = 500 kHz
.c 100 ns,
3
See applicable CirCUit type for actual synchronous and asynchronous mput configuration
4
5
CL mcludes probe and 119 capacitance
Load IS applied to both outputs
Figure 37
3-21
FLIP FLOPS
ac test circuits and waveforms (cont.)
Vcc '5V
o-...... - - - -....--------~~---_,
CLOCK
Rl ·4Ki2
IS •• Note 2)
VI
PULSE
Q)
...
Q)
en
TEST
TA
VT
'25°C,
70°C
25°C
O°C
_55°C
09V
"V
, 3V
, 4V
, 6V
TEST
OUTPUT
...
r--
15n'----1
Q)
~
o
CLOCK INPUT
c..
~
J
15 ••
o INPUTIPUlSE
(See Hote21
:
10%
--1
I
A)
10% I
90%
I
VT
~ _~"%,,------_OV
-+-90%
90%
10%
I
~-
~
INPUT (PULSE C]
_~
r-------
s~------
Q OUTPUT
I
OV
15",--..,
o INPUT (~UlSE
0)
(See Not. 2)
~15n.
y
---+-------- - - - - - - - - - t,.dl-
I
I
I
Yj"
i
I.
(I
(S •• Hot. 2)
'
~_
1:,=11%:----"
90%
I
-,'='----ov
2~
!
VO "
Vo ,
o
V "
fiOUTPUT
'------Vo,
Notes
1 Clock Input pulse has the following characterlstu:,s tp(clockl ;;:: 200 ns and PRR " 500 kHl When testing 'clock, use 50% duty cycle
D Input (pulse A and C) have the following characteristics tsetup'" 30 ns, tp '" 100 ns and PRR IS 50% of the clock PRR
2
o Input (pulse Bf
has the follOWing characteristics thold" 15 ns, tp '" 80 ns dnd PAR IS 50% of the clock PRR
o Input (pulse Df has the follOWing characteristics thold" 10 ns, tp '" 80 ns and PRR IS 50% of the clock PAR
3
CL Include~ probe and Jig capacitance
Figure 38
EXCLUSIVE-OR GATES
(DM54L86/DM74L86)
schematic diagram
Note
DM54L86iDM74L86 '
3-22
-]V
--j_ J.~l~ns_ _ _ _ -]V
. ~ -~"""''''_____-'' ':::.%L: __-oV
(Sa. Nato 21
15ns
+---- - - - - -
liT
:,~.~
o INPUT (PULSE 8)
r-
1___________ JV
90%jli
; . - - - 1.lelo,,1
.j ' .. ,up
Q OUTPUT
~I~n.
I I
---1 f--I
I
o
...J
I
SchematiC diagram shows only one of
the four exclUSive OR,gates
I"""
o
DM54L86/DM74L86
:e
EXCLUSIVE-OR GATES
"tJ
o
dual-in-line package
connection diagram
:e
flat package connection
diagram
...
CD
-I
-I
I"""
en
CD
...
4V
. ..-+_+-----L_+--+--,
4A
GND
3B
"
CD
en
U1
~
I"""
.......
......
~
I"""
18
DM54L86/DM74L86
"
2A
DM54L86/DM74L86
OIl
dc electrical characteristics
SYMBOL
PARAMETER
TEST
FIGURE
CONDITIONS (Note 1)
TYP
MIN
(Note 2)
MAX
UNITS
V'N(1)
I nput Voltage ReqUired
to Ensure Log,cal "1" at
Any Input Terminal
39
Vee = MIN
V'NIO)
Input Voltage ReqUired
to Ensure Logical "0" at
Any Input Terminal
39
Vee = MIN
VOUT(1)
Logical "1" Output Voltage
39
Vee = MIN, V ,N(1 ) = 2V,
V INIO) = 0 7V, I LOAD = -200 /1A
VOUTIO)
Logical "0" Output Voltage
40
Vee = MIN, V'N(1) = 2V,
V ,NIO) = 0 7V, lOUT = 2mA
015
03
V
VOUTIOI
Logical "0" Output Voltage
(Senes 74L Only)
Vee = MIN, ISINK = 3 2 mA
V ,N (All Inputs) = 2V
02
04
V
I'N(1)
Logical "1" Level Input
Current (Each Input)
41
Vee = MAX, V,N = 2.4V
Vee = MAX, V,N = 55V
<2
I'NIOI
Logical "0" Level Input
Current (Each Input)
42
Vee = MAX, V ,N = 0 3V
-022
los
Short CirCUit Output
Current
43
Vee = MAX, V,N(1 ) = 4 5V,
V ,NIO ) = 0
leelo)
Supply Current (Per Gate)
44
Vee = MAX
167
mA
43
Vee = MAX, V,N(1 ) = 4 5V,
V ,NIO) = 0
110
mA
leel1l
Supply Current (Per Gate)
2
13
13
24
-3
V
07
28
-9
V
V
20
200
-036
-15
/1 A
/1A
mA
mA
Note 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable Circuit type
3·23
EXCLUSIVE-OR GATES
switching characteristics
PARAMETER
TEST
FIGURE
tpdO
Propagation Delay Time to
Logical "0" Level IOther
Input Low)
45
CL =50pF,R L =4kl1
tpd 1
Propagation Delay Time to
Logical "1" Level IOther
Input Low)
45
CL
= 50 pF, R L
tpdO
Propagation Delay Time to
Logical "0" Level IOther
Input High)
45
CL
= 50 pF,
tpdl
Propagation Delay Time to
Logical" 1" Level IOther
Input High)
45
SYMBOL
~
Q)
~
o
a..
~
o
TYP
(Note 1)
MAX
UNITS
21
60
ns
= 4 kn
37
60
ns
=4
kl1
35
60
ns
CL = 50 pF, R L = 4 kn
25
60
ns
CONDITIONS
RL
MIN
Note 1: SWitching parameter limits, sWitching parameter tYPlcals, and electrical parameter typlcals are given for
~
at TA
=
Vee
co:
5V
2S'C only.
dc test circuits
~
V"'''~OPEN
Note
Each
Input IS
tested separately
Note
Figure 39
Note
Each mput
IS
Note
Logical "0" and logical "'" Input
conditions are tested
Notes
1 Each gate IS tested separately
2 When testing 'CellI. the output
Figure 42
Note
IS
CL Includes probe and J'9 capacitance
I+I
--1 1--15",
L - L - - - - 3v
I
~
I
INPUT
OUTPUT
"liN POSITION AI
10%
90%
gn%
VT
VT
~T1J.1S--1
~
tpdO
f--
l~
I
I
I
I
I
I
-1'oo"'UI-
I/V,
{SlIN
POS~T~~:UB~----J
-~
I
I
10%
vTVO"'"
- - Va ",101
i
~VO"""
I
-i
V,
t"dO!-
Figure 45
3-24
OV
1---
tpd1
I
I
I
Logical "0" and logical "1 'Input
Figure 44
ac test circuits and waveforms
15"'--j
I
I
tested separately
conditions are tested
open
Figure 43
Note
IS
Figure 41
Figure 40
tested separately
Each Input
V""fIOI
TA
V.
125"C
70·C
25·C
O·C
-55·C
09V
llV
13V
14V
16V
r-
o
DM54L95/DM74L95, DM76L70/DM86L70
SHIFT REGISTERS
~
( DM54L95/DM74L95l
connection diagram
dual-in-line package
flat package connection
diagram
,
GOO
INPUT
ClOCK2
,
ClOCK]
IN'UT
SERIAL
8
INPUT
INPUT
C
INPUT
Vee
o
SERIAL
INPUT
INPUT
DM54L95/DM74L95
8
INPUT
C
INPUT
logic diagram
TRUTH TABLE
Mode Ser"
Vee
0
INPUT
DM54L95/DM74L95
lnpAn
lopen
lopCn lopOn An+l
DM54L95/DM74L95
8 0 +1 Cn +l
On+1
An
Bn
Cn
An
Bn
Cn
-I
-I
r-
..,
SHIFT REGISTERS
electrical ch a racte r isti cs
SYMBOL
...
Q)
(/)
...
PARAMETER
MIN
2
Logical "1" Input Voltage
Vee = MIN
46,48
Logical "0" Input Voltage
Vcc = MIN
47,49
VOUTll)
Logical "1" Output Voltage
Vee = MIN
VOUT{O}
Logical "0" Output Voltage
VOUT(O)
Logical "0" Output Voltage
IIN(Q)
Il..
TEST
FIGURE
V1N(0)
Logical "0" Input Current
~
CONDITIONS
V 1N1n
Q)
o
(DM54L95/DM74L951
(Except Model
Logical "0" Input Current
IIN(o)
~
(Mode Only)
Logical "1" Input Current
o
IINIl)
...J
(Except Mode)
Logical "1" Input Current
IINtl)
(Mode Only)
UNITS
a
V
0.7
Vee = MIN
IOUT= +2 mA
47,49
0.13
0.3
V
Vec = MIN
lOUT = 3 2 mA
47,49
02
0.4
V
Vee = MAX
V ,N =03V
50
-0 1
-0.18
mA
Vce = MAX
V ,N =03V
50
-0 2
-0 36
mA
Vee = MAX
Vce = MAX
Short-Circuit Output Current
Vee = MAX
Supply Current
Vee = MAX
switching characteristics
V ,N =24V
Y'N = 55V
V ,N =2.4V
Y'N = 55V
V OUT = OV
24
3.1
46,48
lee
PARAMETER
MAX
I OUT = -200 J1A
los
SYMBOL
TYP
51
10
100
J1A
pA
51
20
200
pA
pA
-15
mA
52
-3
53
-9
48
80
mA
TYP
MAX
UNITS
(DM54L95/DM74L95) (Note 1)
CONDITIONS
TEST
FIGURE
f MAX
Maximum Shift Frequency
Vee = 50V
C L = 50 pF
54
tpW(CLOCK)
Clock Pulse Width
Vee = 50V
C L =50pF
54
tpd In
Propagation Delay to a
Logical "1" A, B, C, or D
Vee = 5 OV
C L = 50 pF
t pdW)
Propagation Delay to a
Logical "0" A, B, C, or D
MIN
14
MHz
90
44
ns
54
15
42
90
ns
Vee = 5 OV
C L = 50 pF
54
15
48
90
ns
t,
Mode Control Logleal "0" Setup
Time With Respect to CPl
Vee = 5 OV
C L = 50 pF
55
120
55
ns
t2
Mode Control Logical "1" Setup
Time With Respect to CP2
Vee = 5 OV
C L = 50 pF
56
100
45
ns
t3
Mode Control Logical "0" Setup
Time With Respect to CP2
Vee = 5 OV
(Note 2)
C L = 50 pF
56
0
-43
ns
t4
Mode Control Logleal "1" Setup
Time With Respeet to CPl
Vee = 5 OV
(Note 21
C L = 50 pF
55
0
-50
ns
t5
Logical "1" Setup Time at
Senal, A, B, C, or D Inputs
Vee = 5 OV
C L =50pF
54
50
20
ns
t6
Logleal "0" Setup Time at
Serial, A, B, C, or D Inputs
Vee = 5 OV
C L = 50 pF
54
50
13
ns
t7
Logical "1" Hold Time at
Senal, A, B, C, or D Inputs
Vee = 5 OV
(Note 2)
CL = 50 pF
54
0
-14
ns
t8
Logical "0" Hold Time at
Senal, A, B, C, or D Inputs
Vee = 50V
(Note 2)
C L = 50 pF
54
0
-20
ns
60
Note 1: SWitching parameter limits, sWitching parameter tYPlcals, and electncal parameter typlcals are given for Vee = 5V at
TA = 25=C only
Note 2: Negative hold time values Indicate that data can be released prior to the time the clock reaches Its 1.3V level
3·26
r-
o
SHIFT REGISTERS
~
de test ei reuits (DM54L95/DM74L95)
"U
o
CONTROL
OPEN
~
.
V'nlllo----;MMOilioiE'-"l
MODE
V,ol1l
A
CD
CONTROL A
OPEN
SERIAL
SERIAL
INPUT
INPUT
-t
-t
!"'"
0
OPEN
CLOCK I
en
.
CLOCK 2
CLOCK
CD
.".
(i'
CLOCK
CLOC~::
OV
~
r-
TESTVou,lo)
Note
tested separately
IS
U'I
~>9D",~·[
TE5TVO "I(11
Note Each output
(II
Each output
IS
........
tested separately
-.oJ
~
Figure 47
Figure 46
r-
V"
'Iood
VmIOlo-.---;Moii,-"I-___.-_
MODE
V,nIOI
CONTROL
A
SERIAL
INPUT
V,nllj
OP"{
OPEN {
}OP" V
o ,,'"
1
CLOCK 1
CLOCK 2
CLOCK
OPEN
.".
1
CLOCK 2
.".
CLoCK~--3V
Vr
Vr
I
I
Figure 49
TEST TABLE
V"
~
V'"
INPUT
SEE
TEST
TABLE
CLOCK 1
CLOCI<2
.".
Note
OIl
TE5TV o.,111
Figure 48
MODE
CONTROL A
SERIAL
r
DV
1----:?90ns--l
45V
I
OPEN
0----; CLOCK
l~'
.".
Each Input IS tested separately
TEST
APPLY 4 5V
MODE CONTROL
CLOCK 2
APPLYGND
NONE
SERIAL INPUT
NONE
MODE CONTROL
A INPUT
MODE CONTROL
NONE
B INPUT
MODE CONTROL
NONE
C INPUT
MODE CONTROL
NONE
D INPUT
MODE CONTROL
NONE
CLOCK 1
NONE
MODE CONTROL
CLOCK 2
MODE CONTROL
NONE
Figure 50
TEST TABLE
V"
TEST
APPLY 4 5V
MODE
45V
CONTROL A
SERIAL
v,"
~
INPUT
SEE
TEST
TABLE
CLOCK 1
CLOCK 2
.".
";'
Note
l""
Each Input
IS
tested separately
APPLY GND
CLOCK 2
MODE CONTROL
NONE
SERIAL INPUT
MODE CONTROL
NONE
A INPUT
NONE
MODE CONTROL
B INPUT
NONE
MODE CONTROL
C INPUT
NONE
MODE CONTROL
D INPUT
NONE
MODE CONTROL
CLOCK 1
MODE CONTROL
NONE
CLOCK 2
NONE
MODE CONTROL
Figure 51
3-27
SHIFT REGISTERS
dc test circuits (cont.)
v,.
(DM54L95/DM74L95)
o-....--;~M;O~EO!E"
",:1
tONTR,DL A
OPEN
V,nlH
o----;.!'!C8i.P.:T~E~R~0l.A.1
SERIAL
INPUT
OPEN
SERIAL
INPUT
]-
OPEN
CLOCK
...
0----;
CLOCKo-,,--;!!:!!~....J
CLOCK~-_"3V
Q)
~
Vr
o
CLOCK
VT
1
1
OV
I----- ~gO ns-------+l
D.
Note Each output
~
IS
tested separately
TEST los
Figure 53
FIgure 52
o
...I
ac test circuits and waveforms (DM54L95/DM74L95)
INPUTS
r----------,
I
I
L
lN910
RL
4K'N916
1NII6
_ _ _L~c~r~
r- -
-
L... _ _
1111116
___
I
I
I
I
I
J
- -1
..!:n:.::~I~ ___ ...J
-L;;;;C~I'M-
-
r - - - -lDADciii'C'iirj"j"'" - - - - ,
L- _ _ ....:Sa==L!!C:::!'~ __ ..J
r---U;OCiRcuiT4-- ---,
L- _ _ ~:.:!L~"~ _ _ _ ...J
Notes
1 The pulse generators have the following characteristics ., '" 10 ns to 12 ns, to '" 10 ns to 12 n5, and Zout "" son
For pulse generator A tp ,150 ns and PRR '" 500 kHz For pulse generator B tp 10 ns and PAR:: t MHz
When testing f max • vary PRR
2
Voltage yalues are with respect to network ground terminal
3 CL Includes probe and Jig capacitance
TA
125°C
70°C
25°C
qOc
_55°C
,,
A,B,C,ORD
DUTPUTS
! !:'---,"-"'!,
t--
~lpdO~ ~d1
Figure 54
'-----VIOI'"
CLOCK 1
~llV
~
'JV~---------V'N'"
~
'--------VI~ ..
: ,..,f""""\,,":
1'.---''''''
~ '--
CLOCII.2~
I
MOD~ CO/llT1!.~~
I
I
I
J±----T\
V'~'OI
~ I
!
~VI~'"
IIV ~ ';V
! '-----J____
_
---:',1I~L
I
1-',-1 1---_-1
I __
-----VINIDJ
Vour""
NOTE AIN.UTtilV ... ·OV
Figure 55
3-28
VT
O.9V
llV
13V
14V
16V
(DM76L70/DM86L70)
dual-in-line package
connection diagram
r
SHIFT REGISTERS
o
~
flat package connection
diagram
"o~
.
CD
en
.
CD
DM76L 70lDM86L 70
DM76L 70lDM86 L70
logic diagrams
0'
01
o.
05
DM76L 70lDM86 L70
electrical characteristics(DM76L70/DM86L70)
SYMBOL
PARAMETER
(Note 1)
CONDITIONS
MIN
V 'NI1I
Logical "1" Input Voltage
Vce ~ MIN
V,NIO)
Logical "0" Input Voltage
Vee
VOUTI1I
Logical "1" Output Voltage
Vee ~ MIN, louT ~ -200 J1A
V OUTIO )
Logical "0" Output Voltage
Vee
V OUTIO)
Logical "0" Output Voltage
(Series 74L Only)
Vee ~ MIN, lOUT ~ 3.2 rnA
I'NI1I
Logical "1" Input Current
(Except Clear Input)
Vee
~
MAX, V ,N
~
24V
I'NI1I
Logical "1" Input Current (Clear Input)
Vee
~
MAX, V ,N
~
I'NI1I
Logical "1" Input Current
(Except Clear Input)
Vee
~
MAX, V ,N
I'NI1I
Logical" 1" I nput Current (Clear Input)
Vee
~
I'Nll)
Logical "0" Input Current
(Except Clear Input)
Vee
I'NIO)
Logical "0" Input Current (Clear Input)
los
Output Short CirCUit Current (Note 2)
Icc
Power Supply Current
~
~
2.0
MAX
~
2.4
UNITS
1.3
V
1.3
MAX
MIN, lOUT
TYP
V
0.7
V
2.8
2 rnA
<1
V
0.4
V
10
J1A
2.4V
20
J1A
~
5.5V
100
J1A
MAX, V ,N
~
5.5V
200
J1A
~
MAX, V ,N
~
0.3V
-120
-180
J1A
Vee
~
MAX, V ,N
~
0.3V
-240
-360
J1A
Vee
~
MAX, V OUT
-9
-15
rnA
Vee
~
MAX
6
9
rnA
~
OV
<2
0.3
-3
Note 1: SWitching parameter limits, sWltchmg parameter tYPlcals, and electncal parameter tYPlcals are given for
Vee
'= 5V
at T A :; 25°C only
Note 2: Only one output should be shorted at a time.
3·29
~
S
SHIFT REGISTERS
switching characteristics
-it
SYMBOL
It)
II)
.!!!
"-
CD
~
o
a.
~
o
...I
PARAMETER
CONDITIONS
MIN
TYP
6
12
UNITS
Minimum Clock Frequency
V cc = 5 OV, 50% Duty Cycle
tpdO
Propagation Delay to a Logical "0"
From Clock to Output
Vcc = 50V, C L = 50pF
70
120
ns
tpd 1
Propagation Delay to a Logical "1"
From Clock to Output
Vce = 5.0V, C L = 50 pF
40
90
ns
tpdO
Propagation Delay to a Logical "0"
F rom Clear to Ou tput
Vec = 5.0V, C L = 50 pF
90
160
ns
MHz
tpwleLOCK) Minimum Clock Pulse Width
V cc = 5 OV, C L = 50 pF
40
25
ns
tpwICLEAR) Minimum Clear Pulse Width
Vcc = 5.0V, C L = 50 pF
40
25
ns
tSET-UP
M,nimum Time That SA • 58 Data Must
Vcc =50V,C L =50pF
be Set·up Prior to Clock Pulse, ts.t up
t HOLD
M,nimum Time That SA • 58 Data Must
Vcc =50V,C L =50pF
be Held After Clock Pulse, t hold
tCR
Clear Recovery Time'
35
-10
Vce = 5.0V, T A = 25°C,
C L = 50 pF
80
*Tlme required after removal of clear signal for clocking to occur.
switching waveforms
CLEAR
(NOTE 3)
(DM76L70/DM86L70)
LEAR3lOV
VT
~
_PULSE ....
VT
WIDTH
- 2 4V, YOUTlOl <; D4V,
t, Ind l! < Iii /IIi, Ind PRR ~ 1 MHz Input B, C, end 0 Ifans'tlons DeCU! S1multantOMsly with or
IInOtta Input A tranlll'Ont
Note2 CLIllClud8$probelnd J'g~8pIIC,t8nce
NOle3 AlIdiadeurelN3D84 orlqu,nlant
3-32
Nata 4 Th'lwl'Ieiolm represent lIIeO output when A 10 goasiJom ''0'' to "I"
('II wllhB=C=D=''U''
Noll! 5 Thll W ..... OIlll "'P'-'''' tho 0 GUlpul when A gOIl from
('II
"1"to"II"w,tbB"C~O·''U''
V OUTlO,
dc test circuits
TEST
PER
TRUTH
TABLE
TEST
PER
TRUTH
TABtE
Holt Eithoutput,stestedsejlliitely
Note E.choutpotlsteS!HS8IIat,lIlv
TEST
PER
TRUTH
TABlE
O----lt
SEE
v"
OPEN
NOTE
Note
Elchmputistested~rltllly
Nott E,choulput"tested ... p.,atelv
SEE
NOTE
Not~l
When testlng I'NIOI ndllnputlstestedSl!p •••tely
Note2
Wbentestlnglcc'lImputs.r.,roun~edlndoutpuulleopen
DPEN
3-33
Series 54L/74L
DM54L85/DM74L85 (SN54L85/SN74L85)
4-bit magnitude comparator
general description
The DM54L85/DM74L85 low power TTL 4-blt
magnitude comparator IS compatible with most
TTL and DTL families. This comparator compares
two 4-bit words and determines their relative
magnitude with the result being indicated by a
high level at the A>B, AB,
AB and
Ao--+-cj CP
INPUT A
-,
-
!IV
I
Cl
~50'F ~JO'F
I
-::-
L _________ J
r- - L __
~o ~u-;;
- -
-1
~M~L~C~UI.:..!.. _ _
J
c
absolute maximum ratings
3:
(Note 1)
U1
MIN
Supply Voltage
80V
Input Voltage
55V
Output Voltage
55V
Supply Voltage (Veel
DM54L91
DM74L91
Lead Temperature (Soldering, 10 sec)
DM54L91
DM74L91
300 0 e
electrical characteristics
45
475
r-
....
CD
.......
V
V
55
525
-55
0
c
3:
°e
°e
+125
70
.....
0l:Io
r-
(Note 2)
PARAMETER
....
CD
MIN
CONDITIONS
TYP
Logical "1" Input Voltage
13
Logical "0" Input Voltage
13
Logical "1" Output Voltage
Vee = Mm, lOUT'" -200 IlA
Logical "0" Output Voltage
Vee = Mm, lOUT = 2 rnA
(OM54L91)
Vee - Mm, lOUT - 32 rnA (DM74L91)
Logical "1 . Input Current
Vee = Max, Other Inputs = OV, V IN
24
co
2 4V
Logical "0" Input Current
Vee = Max, Other Inputs
Output Short CirCUit Current
(Note 3)
Vee = Nlax, VOUT -= OV
Supply Current
Vee
=
4 SV, V IN '" 0 3V
-3
V
V
07
28
V
V
V
03
04
<1
10
<10
100
"A
-110
-180
"A
-8
-15
mA
35
Max, VIN = 5V
UNITS
MAX
015
02
V IN = 5 SV
=
0l:Io
UNITS
Temperature (T A)
_65°e to 1500 e
Storage Temperature Range
MAX
"A
mA
66
Icc (Max)
f MAX (maximum Input clock frequency)
MH,
Vee=~>OV
TA = 2SoC
Vce=50V
= 25°C
65
130
Propagation Delay to a Logical "1" from
Vee'" 5 OV
40
80
Clock to Output,
T A =25c C
Propagation Delay to a Logical "0" from
Clock to Output,
tpdO
tpdl
TA
Minimum Width of Logical "0" level
Vee=SOV
Clock Pulse,
TA = 2SoC
tpO(clock)
Minimum Width of Logical "1" Level
Vee=50V
Clock Pulse, t p 1{clockl
TA = 25°C
Input Setup Time, t setup
Vee = 5 OV
120
60
120
60
120
T A = 25°C
Input Hold Time, t hold
Vee=50V
TA = 25°C
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operatmg Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electncal Characteristics" prOVides conditIOns for actual deVice operation
Note 2: Unless otherWise specified minImax limits apply across the _55°e to +125°e temperature range for the DM54L91,
and across the O°C to 70 0 e range for the DM74L91. All tYPlcals are given for Vee == 5.0V and TA:::; 25°C.
Note 3: Only one output at a time should be shorted
switching time waveforms
'''''""'
,J",,~O%
ClOCI(PUlSE
INPUT
3V
''''1@lJ%lJv
10% !IV
--"""'=1---CtOCKPULSE
INPUT
INPUTA
L _______ ~ __ ____1"L _________
Sl ____________ s--L
OUTPUTO _ _ _ _ _ _
-----it,
-~:voom'
\JV
OUTPUTOORQ
'"""'"". :r
:::~II -
''''~.'-:l
ClOCKfUlSE
INPUT
~:~::::
to
!","pIOI
INPUT
AORB
13V
V" '11
V,3V
'-..J+-_ _ _ _ _ V,.. IOI
~_,
--jl-,-"'_O"_,"'_ _ _ v.. ",
lJV
1\13V
--VOUTIOJ
t.....plH
'-----V'NIOI
TYPICAL INPUT/OUTPUT WAVEfORMS
Note 1 The generator has the follOWing chara£terlstrcs VINIOI < 0 3V, VINlll > 2 4V, 11
IpdlCLOCKI =500 n~, tpdOlCLOCKI =500 liS, PAA" I MHz, and ZOUT" 5011
Note2 CL mcludesprobeandJ'gcapac,tallCe
No~e 3 Each output I~ te~ted separately
=
to
=
15 ns,
Note4 Voltage values are w,th respect 10 network ground termmal
Note5 All diodes are lN3064 orequrvalent
Note6 f MAX use 50% duty cycle
3-41
Series 54L/74L
DM54L93/DM74L93(SN54L93/SN74L93) and
DM76L93/DM86L93 ripple binary counters
general description
The DM54L93/DM74L93 and DM76L93/DM86L93
ripple binary counters enable a systems designer to
have some flexibility in his design. The DM76L93/
DM86L93 has the same pin out as the standard
SN5493/SN7493, but the same power specifications
as the SN54L93/SN74L93 low-power counter.
Both counters can be used to dlvide-by-2, 8, or 16.
Two reset inputs are provided to allow for initializIng the counters. Resetting occurs asynchronously when both reset Inputs are high. Darlington
outputs provide for a fanout capability of two
standard TTL unit loads over the commercial
temperature range and 10 54L174L loads In the
low state. In addition these devices can fan out to
20 54L/74L loads In the high state.
features
•
Series 54L/74L compatible
•
15 MHz tYPical clock frequency
•
18 mW tYPical power dissipation
logic and connection diagrams
OUTPUTS
,....-........,
OUTPUTS
~
c
TOP VIEW
Dual-tn-line Package
Dual-In-Llne Package
DM54L93/DM74L93
INPUT
A
OUTPUTS
...,......"
OUTPUTS
~INPUTB
Flat Package
DM54 L93/DM74 L93
3-42
DM76L93/DM86L93
INPUT
A
Flat Package
DM76L93/DM86L93
absolute maximum ratings (Note 1)
+8.0V
Supply Voltage
+5.5V
Input Voltage
+5.5V
Output Voltage
Operating Temperature Range DM54L93,DM76L93 -55°C to +125°e
oOe to +70 o e
DM74L93,DM86L93
_65°C to +150 o e
Storage Temperature Range
300 D e
Lead Temperature (Soldering, 10 sec)
electrica I characteristics(Note 2)
PARAMETER
Logical "1" I nput Voltage
Logical "0" Input Voltage
CONDITIONS
DM54L93. DM76L93
DM74L93, DM86L93
Vee - 4 5V
Vee - 4 75V
DM54L93. DM76L93
DM74L93, DM86L93
Vcc=45V
Vee - 4 75V
MAX
lOUT ==
Logical "0" Output Voltage
IOUT= 2mA
lOUT = 3 2 mA
Logical "1" Input Current
DM54L93. DM76L93
DM74L93. DM86L93
Vee'" 55V
V IN
Vee - 525V
24V Reset Inputs
VIN = 55V Reset Inputs
DM54L93. DM76L93
DM74L93. DM86L93
Vee
Vee
V IN ", 24V AIN & BIN
VIN == 5 5V AIN & BIN
DM54L93. DM76L93
DM74L93. DM86L93
Vcc=55V
Vee 525V
VIN == 03V, R01 &
DM54L93. DM76L93
DM74L93. DM86L93
Vee'" 55V
Vee - 525V
VIN
Output Short Circuit Current
(Note 3)
DM54L93. DM76L93
DM74L93. DM86L93
Vee = 5 5V
Vee - 525V
VOUT
Icc max
DM54L93. DM76L93
DM74L93. DM86L93
Vee'" 55V
Vee 525V
06
07
24
-200,uA
28
=
=
03
04
10
100
pA
pA
20
pA
pA
200
R02
-018
rnA
03V, AIN & BIN
-036
rnA
=
OV
-3
-9
-15
550
ns
V cc "'50V
T A = 25°C
CL = 50pF, RL = 4 kQ
210
400
ns
MaXimum Clock Frequency
Vcc=50V
TA = 25°C
CL = 50 pF. RL
Minimum Clock Pulse Width
Vce= 50V
TA = 25"C
CL = 50pF, RL = 4 kQ
=
4 krl
6
s:co
0')
r-
CD
to)
rnA
400
tpdl
C
rnA
230
",
-.....
V
V
4 kS1
D ouT ,
CD
V
015
020
CL = 50 pF, R L
Propagation Delay to a Logical "1" from AIN to
r-
V
V
Vcc=50V
TA=25"C
tpdO
s:
......
to)
Vcc=45V
Vee 475V
D ouT ,
c
UNITS
V
12
13
DM54L93. DM76L93
DM74L93. DM86L93
Propagation Delay to a Logical "0" from AIN to
13
& BIN
Reset Inputs
Vee'" 4 5V
Vee 475V
Logical "0" Input Current
20
AIN
DM54L93. DM76L93
DM74L93. DM86L93
5 5V
525V
TYP
0')
Logical "'" Ou tput Voltage
=
MIN
MHz
15
100
60
ns
Note1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual deVice operation
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the DM54L93,
DM76L93 and across the o"e to 70"e range for the DM74L93,DM86L93. All tYPlcals are given for Vee = 50V and
TA = 25"e
Note 3: Only one output at a time should be shorted
ac test circuit
switching time waveforms
·"·~1€:::
r
'00,""
13V
PULSE
GENERII.TOR
OUTPUTD-----.."",------i
ISEENOHll
13V
VOUT«)l
Not,\ Thepul .. yln&rltOthaoth.follllW"'!lehar,etertsttC, VQ 'N-3V,Io=t,<15n"
t,,=OS~$.PRR=IMHz,ZouT~50Q
r.lol.2 Alidtodes ... 1Nl95110.eq",Yllont
,"ote3C L trn:lud"pfOb •• ooJlyc.pac",nc.
Note4Iod~~
,"0105 VoItagevolu"",wllilr-
0,
I---< 0--0'OUTPUTOB
T
i\,
~
~
OAT A
INPUT C
~
1
~ 8J
T
n.ot----+---1-<11'
U.
COUNT
.
+++++++++++-----~-L...I ~
IN~;:~o-----i=:t=~=F*~F**:t==I-)..---....---4--,
C:Jn
r-'
l
>-+-__+<1'
D, _
r-oDUTPU'D,
li,
H++::::::~--~L-J ~
IN~~;~o-----i=:t=~=F*~F**:t==I-')..---....--~-...,
CLEAR
~
l
>-+---+<11'
LOAD
DD ~r-o OUTPUT 00
li.
~~~-~~------~------~-l----I)o ~
3-55
dc test circuits
V,"~TEST
V'"~~WH
PER
TRUTH
TABLE
TABLE
V"
V"
N
-'
....
...J
CJ)
Each output IS tested sepBllItely
-,.;;;LO;;;AO;;...,..----'
Each output IS tested S1!p.rately
'It
I'
:::E
Q
......
N
....
...J
CJ)
'It
Ln
45V
v"
:::E
Q
v"
UP
DOWN
BORROW
CARRY
0.
SEE
NOTES
Q,
Dc
CLEAR
}~,
UP
-
DOWN
V,
SEE
NOTES
l"'
De
0,
Do
CLEAR
LOAD
0,
LOAD
-=
Note 1 EachmputlStestedseparate/y
NoteZ Apply V, to Input uncler test and ground IIthermpulsexcept
when tesbng data mputl, apply 45V to clear and load mputs
Note 1 Eachlnputlstestedseparately
Note 2 Apply V,lo mput under test and ground other mputs
v"
t'
45V
UP
DOWN
BORROW
CARRY
QA
0,
0,
0,
Each output
IS
tested saparately m the high level state
'os
-=
1~'
-=
ICC
*" Arrows indicate actual direction of current flow Current IOta a terminal IS a positive value.
3-56
switching time waveforms
1 Clearoulputstozero
2 L03d {preset to BCD seven
3 Count Ul' to eight, nine, carry, zero, one and two
4 I:Durrt down to one, zero,borrow, nme, elgllt, and seven
ClEAR-.Jl:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
:, u
,
1
L===============:
: _______________ _
,'..J::
~----------------~I
C..J"
1
1
i
I
I~
,----------------'
o
~----------------
3:
~----------------
--i--'-+-'-----------------
COU~!---+---'---'-'--LflJUl.SUr-;----------
C1I
oou,,-_;"-'--'"-'---'-',- - - - - - - - ' - - . . . ,
r.....
~
DOWN
CD
W
........
1
o
3:
......
~
r.....
CARRY
CD
W
ILLUSTRATED
DM54L 192/DM74L 192
lUustmtedbelowIsthefoliuwmQsequence
1 Clearuulputstozero
2 load (preset) \u 8CO thirteen
3 Count up to fOlJrteen, fifteen, carry, zem, one, and two
4 Count down to Dlle, zero,borrOW,flfteen, lourteen, and thirteen
CLEAR - . J l L - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
,
u
~===============:
LOAD
!a-.J. -:---'--iL == === ==========:
'..J
~---------------
--'--:--'-"
am
c
----------------
,1"""'-'-..:....;:-----------------
~
~----------------
COU~!--;..-'--.;-::---'LflJUl.SUr-;----------1
1
cg~~~---'---'-'---'-,- - - - - - - - ' - . . . ,
,
0,OUTPUTS
,
'~-~---...,
a,:lU
"
I,
CARRY
SEQUENCE
ILLlJSTRATED
'----7"--:-----"
,
U
--,""""",--7-,-',---'-,--------',--+---+-,-----,U
II
I,
1
,
1 0 1
1 13 1
~~
,
'
,
I
14
l~OUNT~P
r-----
1
_21
~
1_
1
~
:OUNT~~WN
,
14
~I
~
DM54L 193/DM74L 193
3-57
switching characteristics
OUTPUTS
I no fie Q. fiA "CARRY SORROW'
r--loADCiiiciiiT2--'
_(~M~t!-.0~ E!!I~T.!l._J
r- - -loADciRcwT3 - - ,
_(~M!..A!.!0!.DE.!..R£!!!T.Jl_.J
Note 1 The pulse ~enerators have the follOWing charactenstlcs lOUT'" 50n, fur the data pulse generator,
PRR ~ 500 kHz, duty cycle ~ 50%, for the load pulse generator, PRR = 1 MHz, duty cycle = 50%
Note 2 CllOcludes probe and Jig ca~acltallCe
All dludesa.e lN3064,
orellu'nl~nt
Test Circuit 1
OUTPUTS
~
r---------l
3oh:
A
<=4K
I
=
I
O'~W~~~
0.1--
o.
o.
=
I
I
I
I
I
I
L __ ::!:"!.CI~~ 1___ J
--loADciRcUi'i'r--'
L.._(~Ml.A~O!!!~S!:!!.T.!l._.J
- - ToAiiciiicmTj""--'
L_(~M.LA~IJ.!!I.s!!£!;!,!T..ll_J
--wAociRcUiTr---'"
L
_1~M!.!t!-.0!E. S!.!!S!!!.T.lL_J
Note 1 The pulse generator has the follOWing characteristics PAR = 1 MHz, lOUT'" 50n, duty cycle =
50%
Nota2 CL mGiudes plObe and Jig capacitance
Note3 All diodes are lN3064
Note4 Count up and £ountdown pulses mown are fOI the SN54193!SN74193 blnarv countm Count
cycle fOI SN54192 d~cade counter IS 1 through 10
Note 5 Waveforms for outputs QA" Qs, and Clc are omitted to Simplify the drawmg
Test Circuit 2
';15ns-J
i__
-----:
1_
, ''"------------~~'
OATA~I
'To%
90,%,$.L,Tt,-,,,---------
10%
INPUT
, lJV
jV;'irj.."
,
:'-'-P~
r--t,.,", ___:
-~
'" ¥:."'",--------1
,
10%
1--,,15n,
--j
OUTPU~
t------t--" 15",
/
Voltage Waveforms 1
15n<---JI--..Jk-15",
"
~NOp~~
IS •• Nnt,41
OUTPUT
IS..
~~t'51
,
~:_",J~~
\--.I 9~~%8
COUNT""\
.
" ~,
.. r.:
\.Jr~'LJ
llV~l~;---
.r.::::"\"
~llV
~t'Hll___
I
I
CVOH
\llV:
:
BORROW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--i
__'_
4=.l!..V_ vo,
-H "'"I--
PHl
1
VO H
13V~VOL
OUTPUT
Voltage Waveforms 2
3-58
3V
~p:k-~OV
:
c
~
Series 54L/74L ....,.........
~s
DM71L22/DM81L22. DM71L23/DM81L23 quad 2-input multiplexers
N
N
........
general description
C
~
Each buffered output can fanout to two standard
TTL Unit loads over the commercial temperature
range, and 10 54L!74L unit loads In the low state
over the Mil temperature range In addition these
devices can fanout to 20 54L!74L unit loads with
the output In the high state ("1"1.
The OM71 L2210M81 L22 and OM71 L23/0M81 L23
are quad 2-lnput multiplexers which select one of
two word Inputs, and outputs the data when
enabled_ The enable Input can be used to synchronize data transfer and forces the output to the "0"
state (OM71 L22/0M81 L221 or high Impedance
state (OM71L23/0M81L231 when enable ~ "1"_
The advantage of the OM71 L23/0M81 L23 IS that It
makes "wlre-oCing" of the outputs pOSSible.
....
,...
00
N
N
C
~
......
....
,...
N
W
........
connection diagram
C
~
Dual-I n-Llne and Flat Packages
ENB
Vee
I.
15
Dc
"
lc
COUT
13
OD
11
11
10
10
~
1
00
....
,...
00UT
0
N
W
~
,
3
4
5
6
7
I'
truth tables and logic diagrams
ENABLE
E
7
••
•
¢
SElECT
INPUT
S
X
1
1
,•
INPUTS
OUTPUT
tPx lx
X X
X
X
1
Z,
•
1
¢
¢
1
•
x
,
X
1
DM71 L22/DM81 L22
ENABLE
E
1
Q
•
••
SELECT
INPUT
S
X
INPUTS
1x
Z,
X
X
X
X
HI Z
1
X
•
•• • x
1
1
OUTPUT
¢;x
7
•
•
7
1
DM71 L23/DM81L23
3-59
(W)
....
N
absolute maximum ratings
po
co
~
Supply Voltage
I nput Voltage
Output Voltage
Operating Temperature Range
OM71 Ln, OM71 L23
OMSI L22, OMSI L23
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
Q
........
(W)
N
....
po
,....
~
Q
N
N
po
-55'C to +125'C
O'C to +70'C
-65'C to +150'C
+300'C
~
Q
........
N
N
....
Vee
=
Min
Logical "0" Input Voltage
Vee
=
Min
Logical "1" Output Voltage
10H
~
Q
OM71 L22, OM71 L23
OMSI L22, OMSI L23
Logical "0" Output Voltage
Mil lOUT
=
MIN
20
MAX
UNITS
45
475
55
525
V
V
-55
0
+125
70
'c
'c
TVP
24
lOUT =
3 2 rnA
UNITS
V
07
V
V
28
015
020
2 rnA, Vee = Min
MAX
13
13
= -200iJA, Vee = Min
Comm
,....
MIN
Temperature (T A)
CONDITIONS
Logical "1" Input Voltage
po
Supply Voltage (VCC)
OM71 Ln, OM71 L23
OMSI Ln, OMSI L23
(Note 2)
PARAMETER
co
operating conditions
+80V
+55V
+55V
electrical characteristics
....
(Note 1)
030
040
V
V
Third State Output Current
OM71L23/DM81L23 Only, Vee = Max
+20
pA
Logical" 1" I nput Current
V 1N = 2 4V, Vee = Max
10
iJA
V ,N = 5 5V, Vee = Max
100
Logical "0" Input Current
V ,N = 0 3V, Vee = Max
Output Short Circuit Current
V OUT =
av. Vee = Max
-40
-018
-3
-9
pA
rnA
-15
rnA
(Note 31
MAX
OM71 L22/0M81 L22
See DC Test Ckts, Vee = Max
4
rnA
Icc MAX
OM71 L23/0M81 L23
See DC Test Ckts, Vee = Max
53
rnA
Icc
Input Clamp Voltage
Output Vee Clamp Voltage
Output Ground Clamp Voltage
Vee = 50V, TA = 25'C, RL = 4 kn, CL = 50 pF
20
40
80
ns
Vee = 5 OV, TA = 25'C, RL = 4 kn, CL = 50 pF
25
50
100
ns
Vee = 5 OV, TA = 25'C, RL = 4 kn. CL = 50 pF
20
40
80
ns
Vce= 50V, TA = 25'C, RL = 4 kn, CL = 50 pF
35
70
140
ns
Delay from Enable to Output from
Logical "1" to High Impedance State
Vee = 50V, TA = 25'C, RL = 4 kn, CL = 50 pF
OM71 L23/0M81 L23 Only
15
30
60
ns
Delay from Enable to Output from
Vee = 5 OV, TA = 25'C, RL = 4 kn. CL = 50 pF
OM71 L23/0M81 L23 Only
35
75
150
ns
"a .. to High Impedance State
Delay from Enable to Output from
High Impedance State to Logical "1"
Vee = 50V. TA = 25'C, RL = 4 kn, CL = 50 pF
OM71 L23/0M81 L23 Only
15
30
60
ns
Delay from Enable to Output from
High Impedance State to Logical "0"
Vee = 5 OV, TA = 25'C, RL = 4 kn, CL = 50 pF
OM71 L23/0M81 L23 Only
20
35
70
ns
Propagation Delay to a logical "1" from
OM71 L22/0M81 L22 Only
30
60
120
ns
OM71 L22/0M81 L22 Only
30
60
120
ns
Propagation Delay to a Logical "0" from
4J or 1 to ZOUT. tpdQ
Propagation Delay to a Logical "0" from
Select to ZOUT, tpdQ
Propagation Delay to a Logical "1" from
q, or 1 to ZOUT.
tpdl
Propagation Delay to a Logical "1" from
Select to ZOUT.
Logical
tpdl
Enable to ZOUT, tpd1
Propagation Delay to a Logical "0" from
Enable to ZOUT. tpdQ
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operatmg Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrlcal Characteristics" provides conditions for actual device operation
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to + 12SoC temperature range for the DM71L22,
OM71 L23 and across the O'C to 70'C range for the OM81 Ln, OMSI L23 All tYPleals are given for V CC = 50V and
TA = 25'C
Note 3: Only one output at a time should be shorted
3-60
c
s:.....
DM71L22, DM71L23 dc test circuits
....
r-
N
N
........
C
s:00
....
'o"~
TEST
PER
o--r--.....,~
TEST
PER
TRUTH
TRUTH
rN
N
IOL
TABLE
TABlE
vo,
1J
I
-
hchoutputtestedsepilrilt~ly
C
s:.....
hch output tested separately
....rN
W
........
C
45V
V"
s:00
V"
....
V"
r-
1'"
-'"
0
Z.
1
Z,
SEE NOTE
Z,
}...
A
Z.
8
Z,
0
1
0
1
Zo
0
Zo
1
-=
NOTE Fm IIH on 0/1, take enable mput to 4 5V and 110 to 0 yolts
For IlL (Ill Dll,ground enableilnd takeseleet Input to [lV/45V
Testl jH & IlL on select & enable Inputssepilrately wltb no speellil condilionson other inputs
-=
N
W
C
Z,
0
Zo
1·"
-=
Each oulput tested separately
'CC
'os
DM71L22 ac test setup
r--
-----.,
I
to
I
I
Z,
50 PF-r
L
...+-----i14
Z,
I
_________
-=- .JI
~JDPF
r
- - - - - - - - - - ,.J
L ___
~AM~S~ _ _ _
r---------.,
L ___
~M~S~ _ _ _
..J
rL _
- _
- _
- _
-;M-;;;:S;:- - - ..,
_ _ _ _ _ .J
3-61
('I)
......
N
DM71L23 ac test setup
00
:E
c
o
......
r-
You,
-------.,
I
('I)
......
I
:E
I
N
I
r-.
I
C
N
N
C,
......
MEASURE
TO
!iOpF
50pF
00
Closed
:E
c
5,'
5"
50pF
Open
50pF
Open
......
N
N
......
DM71L22 ac switching characteristics
r-.
1[""
- I""
:E
C
9~l~
,7""
v, .. (OIHPlITS)
~
""
\
llV/
1\
J
13V
~
-
\U
V
J
h
I\. t-J
\
lI.lV
Vh
1"- r-V-
f\. t-J
V, .. (lII11PUTS)
-
- ...
'.' I-
IpdOE' Prop delay trom logIC 1" to logo: "0" due to
- '-
I-
enlble,"~ul
r-
t"';1E
r
,-
I-
' .... ,S
r-
1.,.,,;P,"P del.y hom logl< '010109" 'I duel.enabl.,n,,"!
tpd(J!;·P'.p delay from loJogI( 'I 1010g'o O' duetostl .. ".,",
I.. ,s·"op del.y hom l"9lC '0 101o,,", " du,tost' ..
"n,"'
DM71L23 ac switching characteristics
~
V, .. (0 INPUTS)
~
'.'
I--~
I--
,~
V
V;lV
IL
'"
13V
lJV
lOUT
J
V
\v
-\
I
..."
-
nr-'·
V,""
\-
\
hr'\"
.J
11,.. (1 INPUTS)
l".oos-P,OP delayhomlo9,e 1 lulo!ll' 0 du.t.select,n,"!
Pr.p dellv(homlog,c'O I to H'/I1a!'due to en.ble,np.n
t"o.<,"
!p, .. ,"'OIl dOI.vllromlugoc 1 ) •• H"""edu.to,n,ble,npul
\P,m"'.'
t,,~oo-
3-62
del.ylrumll""""o,I"!" 1 du.to en,bllmp"t
Prop delay hom II"
'0' log", 0 duo to "n,bl. ,nput
,til.
- ..... 1---
....,
i--
-
to, .. ,
I--
o
5V Chdnge
o 5V Change
o
s:.....
Series 54L/74L
U1
......r-
.........
o
s:
co
U1
......
DM75L111DM85L11 TTL dual gated 0 flip flop
general description
features
The DM75L 11/DM85L 11 IS a low power TTL
dual gated D flip flop utilIZing two gate Inputs
Both gate mputs must be low to enable data transfer to the Q and Q outputs If either gate mput IS
high the data on the Q and Q outputs IS constant
•
r-
Positive edge triggered, buffered clock
•
18 mW tYPical power dissipation
•
70 ns tYPical propagation delay
•
Pm compatible with STD TTL DM7511/
DM8511
logic and connection diagrams
Dual-in-Line and Flat Package
Vee
CLOCK
L
CLA
G2
,.
15
Q
Gl
1]
12
11
CLEAR
g
10
f-
G1
CP
G1
elK
1
CLOCK
1
G2
3
4
5
6
a-
Gl
7
CLEAR
I'
GND
TOP VIEW
truth table
D
G,
G2
CLR
Q n+ 1
0
0
0
0
0
0
1
1
0
X
X
X
1
X
0
0
0
0
G"
G"
0
G"
Gn
1
X
X
X
,
1
°n+1
l'
* Asynchronous Transition
X = Irrelevant (Don't Care)
3-63
......
-I
It)
absolute maximum ratings
co
~
C
........
(Note 1)
operating conditions
MAX
MIN
......
Supply Voltage
Input Voltage
-I
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
It)
,....
~
+80 VDe
+55 VDe
+55 VDe
-65'C to +150°C
300'C
Supply Voltage (Veel
DM75L11
DM85L 11
PARAMETER
Logical "1" Input Voltage
Vee=MIn
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
Vee = Min, lOUT = -200VA
Logical "0" Output Voltage
DM75L 11
DM85L 11
Vee = Min, lOUT = 2 0 mA
Vee = Min, lOUT = 3 2 mA
Logical "1" Input Current
All Inputs
DM75L 11
DM85L11
Vee = Min, Y'N = 2 4V
Vee = Min, Y'N = Vee
Logical "0" Input Current
All Inputs
Vee = Max, V ,N = 0 3V
Output Short CircUIt Current
(Note 3)
Vee = Max, V OUT = OV
Supply Current (Per Package I
Vee = Max
Propagation Delay to a Logical "0"
from t pH L Clock to Output, tpdO
Vee = 5 OV, T A = 25°C
Figure 1 Waveforms A
Propagation Delay to a Logical" 1"
Vee =50V, TA = 25°C
from t pLH Clock to Output, tpd1
Figure 1 Waveforms A
Propagation Delay to a Logical "0"
Vee =50V, TA = 25°C
from t pHL Clear to Output,
Figure 2 Waveforms B
PropagatIOn Delay to a Logical "1"
from
tpLH
Clear to Output,
tpd1
Minimum Clear Pulse Width,
Figure 1 Waveforms A
tW(CLEAR)
Minimum Clock Pulse Width, tW(eLOeKI
Minimum Set-Up Time for Data
Input,
tS(DATA)
MInimum Hold Time
for Data Input
tH(oATA)
Minimum Set-Up Time
G, or G2 Input
tS(GI
for
Minimum Hold Time tH(GI for
G, or G2 Input
DM75L 11
DM85L 11
MIN
TYP
20
13
V
V
-55
0
"125
70
"e
'e
MAX
24
030
040
V
V
10
100
VA
VA
-100
-180
VA
-9
-15
mA
35
6
V
V
28
015
020
-3
UNITS
V
07
13
Vee = 5 OV, T A = 25°C
Figure 2 Waveforms B
Vee = 5 OV, TA = 25°C
Maximum Clock Frequency
55
525
(Note 2)
CONDITIONS
tpdo
45
475
Temperature (T A)
c
electrical characteristics
UNITS
49
mA
75
125
ns
55
95
ns
75
125
ns
55
95
ns
MHz
9
Vee = 5 OV, T A = 25° C
Figure 2 Waveforms B
30
100
ns
Vee = 5 OV, T A = 25°C
Figure 1 Waveforms A
30
100
ns
Vee = 5 OV, T A = 25°C
Figure 3 Waveforms e
40
80
ns
Vee = 5 OV, T A = 25" C
Figure 3 Waveforms C
30
60
ns
Vee = 5 OV, T A = 25° C
Figure 4 Waveforms 0
40
80
ns
Vee = 5_0V, TA = 25°C
Figure 4 Waveforms 0
30
60
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditIOns for actual device operation.
Note 2: Unless otherWise specified minimax limits apply across the -55°C to +125°C temperature range for the OM75L 11 and
across the oOe to 700 e range for the DM85L 11 All tYPlcals are given for Vee = 5.0V and T A = 25°e
Note 3: Only one output at a time should be shorted
Note 4: SWitching parameters guaranteed to change less than 50% over the full operating temperature range
3-64
0
3:
.....
switching time waveforms
C1I
r-
All times measllred from 1 3V level
~
~
PULSE GEN A
t,=t l =15ns
'v
'v
PULSE GEN 8
1,=tl =15ns
'v
'v
o.UTI'UT
VO"
.......
0
'V
PULSE GEN
~ tt - 15 os
'V
t,
VO"
V"
0. OUTPUT
Q
3:
00
C1I
r-
~
~
v"
Ii OUTPUT
VO"
V"
VO"
v"
Ii OUTPUT
la)
PUlSEGENA1-,
,,15",
Ib)
-;t-::t, - - - - -
~~~.
t,- I,
ov
n
1SIIs
OV
__
o DUTPUl
3V
P~,:S;,~~~:'
PULSE GENB
1,101
----=x ______ ~::
t, =
If = 15 liS
QOUTPUT
r
1
----1 ,(
I
l---t,IGI------f--t~(GI___!
:~
:~
------y~~_-_--_-_-_-~::
Id)
(e)
ac test circuits
o
G1
G2
FIGURE 2. Use Waveforms B
FIGURE 1. Use Waveforms A
G1
FIGURE 4. Use Waveforms 0
FIGURE 3. Use Waveforms C
-G
=
OUTPUT -
--1I4-......I-l~,
....
ALL DIODES
lNJ064 OR EOUIVfl.LENT
FIGURE 5.
3·65
Series 54 L/74 L
DM75L12/DM85L12 dual JK. 0 flip flop
general description
o
The DM75L 12/DM85L 12 IS a dual JK, D flip flop
with a common clock and common clear A
mode control Input on each flip flop determines
the type of flip flop operation (Mode = "1"
enables the JK mode, and mode = "0" enables the
D mode.) The clear Input IS an asynchronous
Input which overrrdes all other Inputs
and 0 outputs are both provided on each
flip flop. TYPical propagation delays from clock
to outputs are approximately equal to three low
power TTL gate delays.
logic and connection diagrams
CLEAR
r---------- -----,
I
I
I
MODE 2
0,
/"
I
I
15
n,
K,
14
13
12
4
5
CLEAR
Q,
11
"
9
CP
I
I
I
2
1
I
0',
3
MODE 1
K,
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..I
TOPVIEW
~ONlY
~~CLOCK
LOGIC FOR ONE OF THE TWO FLIP FLOPS IS SHOWN
AND CLEAR ARE COMMON HI 80TH FLIP FLOPS
truth table
J
K
M
CLEAR
On+1
0
0
0
1
On
1
an
D
O·
1
1
1
x
x
0
0
0
0
0
0
X
X
X
1
1
0
1
1
1
* Asynchronous Transition
3·66
0
6
-
Q,
J
Q,
I'
"'0
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 1)
+80 VDe
+5.5 VDe
+5.5 VDe
_65°e to +150o e
3000 e
3:
.....
operating conditions
Supply Voltage (Veel
DM75L 12
DM85L 12
UI
MIN
MAX
UNITS
45
4.75
55
525
V
V
-55
0
+125
70
°c
r....
N
.......
c
3:
Temperature (T A)
DM?5L12
DM85L 12
°e
00
UI
r....
N
electrical characteristics
Vee ~ 5.0V, T A ~ 25°C,
RL
(Note 2)
~ 4krt, C L ~ 50 pF
CONDITIONS
PARAMETER
Vee = Max
Logical "0" Input Voltage
Vee
Logical' 1" Output Voltage
lOUT
Logical "0" Output Voltage
Md lOUT = 2 mA,
Vcc=Mln
Com lOUT = 3 2 mA,
ClfCUlt
-200IlA, Vee
=
VIN = 24V
0, J, K, M, Inputs, CP, CLEAR
VIN
Vee = Max
5 5V
24
Min
Current
M,
Supply Current - Icc Max
-3
VOUT =DV, Vee = Max
M2
=
Vee
=
=
CP
=
"0", All Other Inputs = "1"
MA
MA
-180
MA
-15
mA
mA
I,
60
120
ns
HI
35
70
ns
57
114
tpd1
Propagation Delay to a Logical
"0" from Clear to Output, tpdO
I"
6
MaXImum Clock Frequency
t HOLD Minimum
V
V
10
100
45
"
tpdO
Propagation Delay to a Logical
tS ETUP Minimum
03
04
Max
Propagation Delay to a Logical
''1'' from Clock to Output,
'-9
V
V
28
015
020
UNITS
V
07
Vee = Max
(Note 3)
"0" from Clock to Output,
MAX
13
V 1N =03V, All Inputs
Logical "0" Input Current
Output Short
=
TYP
13
Max
=
=
MIN
2
Logical "1" Input Voltage
Logical "1 ' Input Current
WAVEFORM
REF tt.
JK
t3, t4
Mode
t 7 ,110
Data
t 12, t13
JK
Mode
Data
t 5 , t6
t 8 , t9
t 14 , t 1 5
ns
MH,
10
77
81
45
140
150
90
ns
ns
ns
77
81
45
140
150
90
ns
ns
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVIce cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limIts. The
table of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherWise specified min/max limits apply across the _55°C to -r125°C temperature range for the DM75L 12
and across the oOe to 70°C range for the DM85L 12. All tYPlcals are given for Vee = 5.0V and TA = 25°e.
Note 3: Only one output at a time should be shorted
3-67
ae test circuit
+5V
+5V
4.
ALL DIODES lN916
Cl " INCLUDES PROBE AND JIG CAPACITANCE
switching time waveforms
3-68
c
3:
.....
Series 54L/74L
C11
r-
C11
....
......
c
3:
CO
C11
r-
DM75L51/DM85L51 low power TRI-STATE® quad-D flip flop
general description
features
The DM75L511DM85L51 IS a TRI-STATE ® logic
device which provides four D-type flip flops In one
package which operate synchronously from a common ciock
•
Series 54L174L compatible
•
50 ns tYPical propagation delay
•
30 mW tYPical power diSSipation
•
Outputs directly connectable for bus-line operation
•
A "do-nothing" state accomplished without
gating the clock
•
Simple disable encoding
A unique three-state output allows the device to
be used In bus-organized systems_ The outputs can
be directly wired to outputs of other DM75L51/
DM85L51s without encountering the problems
normally met with "collector-OR Ing" LP TTL Circuits. ThiS IS accomplished by gating the normally
low Impedance logical "1" or logical "0" output
into a high Impedance state
....C11
The DM75L51/DM85L51 IS completely compatible
with other Series 54L174L devices
logic and connection diagrams
Dualwln·Line and Flat Package
INPUT
INPUT
DlSA8LE
~~
VeL
ClEAR
J
A
"
" " "
"
'" "
d
, ,
,
. .,r
;
~
OUTPUT
truth table
(Both Output Disables Low)
'.
DATA INPUT DISABLES
Logical
1 0111 or both Inputs
Logical
Oonb01h,,'ptJI<
0
0
Log,cdl"O'onbotll",puts
3-69
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM75L51
DM85L51
(Note 1)
80V
55V
55V
-55'e to 125'e
oOe to 70'e
electrical characteristics
CONDITIONS
Logical "1" Input Voltage
DM75L51
Vee 04 5V
t-;-;-~--DM85L51- Vee 04 75V
Logical "0" Input Voltage
DM75L51
V ee o 45V
DM85L51- ~o475V
Logical "1" Output Voltage
DM75L51
Vee 04 5V
t-,---DM85L51- Vee 04 75V
Logical "0" Output Voltage
DM75L51
V ee o 45V
DM85L51- ~eo 4 75V
Third State Output Current
DM75L51
DM85L51
Logical "1" Input Current
DM75L51
Vee' 55V
DM85L51- ~'525V
Logical "0" I nput Current
DM75L51
DM85L51
(Note 3)
Supply Current" (each deVice)
Icc
(max)
Vee o 55V
Vee 525V
Vee' 55V
Vee' 525V
~i-
DM75L51
Vee' 55V
DM85L51- r--.----Vee' 525V
MIN
2
2
TYP
lOUT 0 -1 mA
lOUT
= -1 rnA
24
24
V ouT o 24V
V OUT ~ 0.3V
V ,N ' 24V
Y'N ' 55V
V IN 'O.3V
V OUT
:;:
OV
-3
-3
UNITS
V
V
07
07
27
27
015
02
2 rnA
lOUT 0 3 2 mA
lOUT:;:
MAX
13
13
13
13
DM75L51
Vee 05 5V
",----DM85L5'- Vee' 5.25V
Propagation Delay to a Logical "0" from
-65'e to 150°C
300'e
(Note 2)
PARAMETER
Output Short C'feu It Current
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
V
V
V
V
03
04
V
V
20
-40
IlA
IlA
<1
<10
10
100
IlA
IlA
-120
-120
·-180
-180
IlA
IlA
-8
-8
-15
-15
mA
mA
9
mA
55
Clock to Output, tpdO
TA
Vee' 50V
'25'e
77
120
ns
Propagation Delay to a Logical" 1" from
Vee' 5 OV
T A' 25'e
39
70
ns
Vee' 50V
T A' 25'e
72
110
ns
Vee' 50V
T A ' 25'e
18
50
ns
Vee' 50V
T A ' 25'C
32
75
ns
V ec '50V
25°C
28
55
ns
Vee' 50V
25'e
35
60
ns
Clock to Output, tpdl
Propagation Delay from Clear to
Output,
tpdR
Delay from Output DISable to High
Impedance State (from Logical "1"
Level),t 1H
Delay from Output Disable to High
Impedance State (from Logical "0"
Levell. tOH
Delay from Output Disable to
Logical "1" Level (from High
Impedance State), tH1
Delay from Output Disable to
Logical "0" Level (from High
Impedance State), tHO
MaXimum Clock Frequency
Input Data Setup Time, tSDATA
TA '
TA '
Vee' 50V
25'e
Vee' 50V
T A ' 25'e
T A'
6
15
+57
MHz
+10
ns
Input Data Hold Time, tHDATA
Vee' 50V
T A' 25°C
Input Disable Setup Time, tSOIS
Vee' 50V
T A' 25'e
33
45
ns
Vee = 50V
25'e
19
40
ns
Input Disable Hold Time, tH DIS
T A'
10
+2
ns
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" provides conditIOns for actual deVIce operation.
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature range for the DM75L51 and
across the aOc to 700e range for the DM85L51 All typlcals are given for Vee = 5,OV and T A = 25°e.
Note 3: Only one output at a time should be shorted
3-70
c
s:.....
UI
r-
UI
...a
-....
C
s:00
UI
ImAFORDRIVINGOTHERLPT1LINPUTS
r-
BUS LINES
UI
~
SELECTED AS
DRIVING_
DEVICE
...a
SELECTED AS
DRIVING
DEVICE
ZO"A.450UTPUTS- 9mA
LEAKAGE CURRENT
GATED INTO
THIROSTATE
GATED INTO
THIRD STATE - - .
GATED INTO
THIRD STATE
21"ALEAKAGECURRENT
FIGURE 1
FIGURE 2
FIGURE 3
mode of operation
The high Impedance state occurs on all outputs of
all devices except the four outputs of the one device selected (Figure '). The result is that the
selected device has a normal LPTTL low Impedance output prOViding good capacitive drive capability and waveform integrity especially dUring the
transition from a logical "0" to a logical "1". The
other outputs are all In the "third-state" and take
only a small amount of leakage current from the
dnvlng outputs. Since the logical "'" output current of the selected device IS 5 times that of a
normal Senes 54L/74L output ('.0 mA vs 200JlA),
the output is easily able to supply that leakage
current to as many as 45 connected devices and
stili retain enough drive for a full Series 54L/74L
fanout of 10 at the end of the bus line (Figure 2).
A tWO-input NOR gate facilitates selection of the
driVing device through the use of only two lout of
5 decoders for as many as 64 DM75L51/DM85L51s
(Figure 3)
A problem inherent in conventional D-type flip
flops IS that It is impossible to code the data input
In such a way as to cause the flip flop to remain in
o
Its present state when clocked. Because flexibility
IS not as great as with a J-K flip flop (and Its J=O,
K=O state), to keep a D-type flip flop in ItS present
state it IS usually necessary to gate the clock,
which Increases the danger of false-clocking. The
DM75L5,/DM85L5' contains a gated input disable
which does not disrupt clocking, but rather recirculates information from the Q output to the 0
Input. In th IS manner the flip flop does not change
state and the possibility of false-clocking IS eliminated.
The follOWing logic levels control the device:
• Clocking occurs on the positive-going transition.
• Clearing IS enabled by taking the Input to a
logical "'" level.
• Outputs are placed in the "third-state" If either
of the two Output Disable Inputs IS taken to a
logical "'" level.
• The flip flops will remain In their prevIous state
when clocked so long as either of the two Data
Input Disable inputs IS taken to a logical "'"
level.
3-7'
...
It)
..J
switching time waveforms
It)
co
:IE
, - - -______-;, ______________ 3v
Q
...
CLOCK
......
INPUT
CLOCK
13V
(SEE NOTE 2)
It)
INPUT
1.....- - - - - - - - - - -
..J
It)
....
ov
r-+-______, __________________ 3V
:IE
r---------------
INPUT
(PULSE I)
(SEE NOTE l)
Q
13V
3V
13V
I.....- - - - - - - O V
------Jt---------------- OV
""'
I--- '.., V.H
V
v.,
V.H
a OUTPUT
V..,
~J'
QOUTPUT
13V
QOllTPUT
v.,
V.H
0.0U1PUl
13V
13V
v.,
v.,
1---'.. _______
''''
,-----I--------- 3V
CLOCK
INPUT
13V
(SEE NOTEZ)
....._____ .V
,---r----------,-----t----------
3V
DATA
13V
INPUT
1~--_1---------------·V
r-1---,------------3V
13V
INPUT ________________....J
DISABLE
1.....- - - - - - - - ISDIS
ov
t!-lOIS
r-----------------------V~
-J/__
OUTPUT ____________________________________
J
,_3V_______________________
.,
V
r-------,------------------3V
CLEAR~
(SEE NOTE 4)
_'_3V_______________
oV
DUTPUl
''''f.--
V. H
~
'----------_______________ V.,
3-72
Notal
AlimputpulllllshlY1lt,"t,= 15HI
Note 2 Clo~k Input fplcllldoJ > 200 os Ind PRR = 500 kHz When testmg Ie....... U58 50% duty ~vcle
Note3 Pulplandpulse2 tp=10Dns.PRRIS50%ofthe~IOI:kPRR
NOlll4 IpI_I=>I00ns,PRR=500kHz
tpl....'1
NoteS tplDATAI
~
4 t,.ldo<*1 and PRR
~
125 kHz
NoteS tpIDISI=tplclockllndPRR=250kHz
o
3l:
......
switching time waveforms (con't)
UI
tOH
r-
...
UI
.......
o
3l:
CO
UI
I--'~'"nk::::l'-
VOLTAGE
OUTPUT
...r-
~'·h
lOGI~~~U~l _ _ _ _ _ _ _...
-;:--j---~--
UI
I
ACTUAl--------L----T-LOGICAL 0
VOLTAGE
"f
'" - - - - '"'~
\
OUTPUT
ac test circuits
~ OM15L51f~
TABLE!
DM85l51
~
HI
' - - - L-----r---'
.,!,
INPUT CONDITIONS
ACTEST
OUTPUT
OUTPUT
DISABLE 1
DISABLE 2
tpdO
GND
GND
See Note ,
to'd'
GND
GND
See Note I
CLOCK
DATA INPUT
DATA INPUT
DISABLE
DISABLE
rNPUTD
INPUTC
INPUTS
GND
GND
See Note 2
See Note 2
See Note 2
GND
GND
See Note 2
See Note 2
See Note 2
Voo
Voo
Voo
Voo
Voo
,~"
""
""
'"'
'"'
See Note 3
See Note 3
See Note 2
GND
See Note 3
See Note 3
GND
GND
See Note3
See Note 3
GND
tSDATA
CLEAR
GND
GND
See Note 2
GND
Voo
Voo
Voo
GND
GND
GND
GND
GND
Voo
Voo
Voo
Voo
GND
GND
Voo
See Note 2
GND
GND
GND
GND
GND
GND
See Note 1
GND
GND
See Note 2
See Note 2
GND
See Note 2
tso,s
GND
GND
See Note 1
See Note 3
See Note 3
See Note 2
t H01S
GND
GND
See Note 1
See Note 3
See Note 3
See Note 2
fclocl<
GND
GNO
See Note 7
tHDATA
INPUT A
Voo
GND
See Note 2
See Note 2
See Note 2
GND
SOffl Note 2
See Note 2
See Note 2
GND
See Note 2
See Note 2
See Note 2
GND
ac load circuit
'"
!
/
SWITCH 5,
SWITCH 52
C,
!pdO
Closed
Closed
50pF
Ipdl
Closed
Closed
50pF
TEST
SWITCH'
tpdR
""
OIlTPUTCL~
""
(SEENOTE4)J
'""
'"'
OIODES
ISEE NOTE 5)
'"'
tSCATA
,SWITC",
Note 1
Note 2
Note 3
Note4
Note5
Note6
Note7
Pulsegen PRR"500kHz,'tpJdo>o:k,:?:200ns.t,=t,= 15ns
See Ie SWitching time WB'Ieforms
Tie these inputs together. see It switching time waveforms
IncludesJlgandprobecapactllnce
Alldlodllare 1N3064orequlValent
Jlgcapacttance
Use 50% duty cycle
Closed
5pF
Open
Closed
50pF
Open
SOpF
Closed
Closed
50pF
Closed
50pF
tHOIS
!clock
5pF
Closed
IHOATA
'SOlS
50pF
1See Note 6)
50pF
Closet!
Closed
}
Closed
50pF
50pF
3-73
~
Ln
...J
Series 54L/74L
Ln
co
:!:
c
........
~
DM75L52/DM85L52 TRI-STATE® decade counter/latch
DM75L54/DM85L54 TRI-STATE
binary counter/latch
Ln
...J
Ln
.....
:!:
general description
c
features
The DM75L521DM85L52 and DM75L541DM85L54
are LPTTL TRI-STATE synchronous decade and
binary counter/latch circuits respectively. The cirCUit consists of a counter made up of four edgetriggered J-K flip-flops.
N
Ln
...J
Ln
co
•
:!:
c
........
Ln
...J
Ln
.....
:!:
c
38 mW typical power dissipation
•
Tf'll-STATE outputs directly connectable for
bl-ls-line operation
•
TRI-STATE outputs information may be latched
•
50 ns typical propagation delay
II Count mode and terminal count output are
~perable when the outputs are in the high
Impedance state or latch mode.
The circuits logically combine the function of
counters for frequency division, latches to hold
the counter's information, and output buffer gates
which allow active LPTTL outputs as well as the
high impedance (3rd) state for output multiplexing
of data.
N
Series 54L/74L compatible
•
•
B I a n kin 9 capability with the D M 7 5 L 52/
DM85L52
•
Positive true logic
logic and connection diagram
Packa~
DuaHn-Lme and Flat
V,c
Tf
L"
CP
"
PRESET CLEAR
"
Nt
CEP
,
" " "
~
1
,
t:ET
, , ,
;
"
,
I'
--"'--OUTPUTOUTPUTOUTPUTOUTPUT TERM
GND
D~~::~:S
C0 8
A
COUNT
typical application
Multi-Stage Synchronous Counter with Visual Display
DISPLAY
DISPLAY
DISPLAY
DISPLAY
UNIT
UNIT
UNIT
UNIT
Vee
COUNT
ENABLE
1"-,,
SIGNIFICANT
STAGES
CP
STROBE
3-74
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
(Note 1)
80V
55V
55V
-65"C to 150°C
300°C
3:
operating conditions
Supply Voltage (V CCI
DM75L52115L54
DM85L52/85L54
Temperature (TAl
DM75L52,DM75L54
DM85L52,DM85L54
'-I
CJI
MIN
MAX
UNITS
4.5
4.75
55
5.25
V
V
-55
+125
70
o
r-
CJI
N
"c
3:
CO
CJI
r-
electrical characteristics
CJI
N
(Note 2)
C
PARAMETER
CONDITIONS
MIN
TYP
24
13
Logical "0" Input Voltage
13
Logical" 1" Output Voltage
lOUT
24
27
Logical "1" Output Voltage - Terminal Count
lOUT" -2001lA
24
28
Logical "1" Input Voltage
Logical "0" Output Voltage
Third State Output Current
Logical "1" Input Current
"CET"
"Other Inputs"
= -1
mA
DM75L52/DM75L54, lOUT" 2 mA
015
DM85L52/DM85L54, lOUT = 3 2 rnA
02
MAX
3:
UNITS
'-I
CJI
r-
07
CJI
~
"c
:s:CO
03
04
VOUT " 24V
20
CJI
VouT "03V
-40
CJI
V ,N "24V
<2
20
V ,N "55V
<20
200
Y'N = 24V
<1
10
Y'N = 55V
<10
100
r-
~
Logical "0" Input Current
"CET"
V ,N =03V
-240
-360
"Other Inputs"
Y'N
= 0 3V
-120
-180
IlA
-8
-15
rnA
Output Short Circuit Current (Note 3)
Supply Current - (Each Devlcel
V OUT = OV
-3
76
Icc (Maxi
150
ns
Vee=50V, TA = 25°C
115
220
ns
Vee = 50V, TA = 25°C
90
160
ns
Vee = 5 OV, T A = 25°C
8
15
ns
57
105
ns
75
150
ns
90
150
ns
tpdO
Propagation Delay to a Logical "'" from
Clock to any Output,
tpd1
Propagation Delay from
TE to Output,
DI
mA
75
Propagation Delay to a Logical "0" from
Ctack to any Output,
130
IlA
tpd (TE)
Delay from Output Disable to High Impedance
State (from Logical "1" Level), tlH
Delay'from Output Disable to High Impedance
State (from Logical "0" Level). tOH
Delay from Output Disable to Logical "1"
Level (from High Impedance State), tHl
Delay from Output DI"able to Logical "0"
Level (from High Impedance State), tHO
Vee = 50V, TA = 25°C
Max Imum Clock Frequency
Vee= 50V, TA = 25°C
6
11
MHz
Nota 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherWise specified minImax limits apply across the -5SoC to +125°C temperature range for the DM75L52,
DM75L54 and across the O°C to 70°C range for the DM85L52,DM85L54 All tYPleals are given for VCC = 50V
TA = 25°C
and
Note 3: Only one output at a time should be shorted
3·75
'lit
It)
...I
mode of operation
It)
CIO
:E
Q
.......
'lit
It)
...I
It)
"'"
:E
Q
N
When the Transfer Enable (TE) IS at a logical "1"
level the data transfer paths between the counter
outputs and the output buffer gates are maintained .
When the Transfer Enable IS at a logical "0" level,
the data transfer paths are inhibited, and the state
of the output buffer gates are locked in by the
latches. The counter and Terminal Count (TC)
output remain operable dUring this time.
• Clearing or presetting is enabled by taking the
respective Input to a logical "1" level.
Asynchronous Clear (CL) resets the counter to
0000.
• To place the TRI-STATE outputs into the
"third-state" either of the Output Disable (OD)
Inputs must be taken to the logical "1" level.
• To enable the count mode both CET and CEP
inputs must be at a logical "1" level.
• To latch the outputs the Transfer Enable (TE)
input must be taken to the logical "0" level.
It)
...I
Asynchronous Preset (PRE) sets the counter to
1111. The 1111 state may be used In the
DM75L52/DM85L52 for blanking out leading
zeroes In visual displays. The next clock pulse
will advance the DM75L52/DM85L52 to 0001
which denotes the first count of the blanked
zero. The next clock pulse will advance the
DM75L54/DM85L54 to 0000.
It)
CIO
:E
Q
.......
N
It)
...I
It)
:E
"'"
The clock Input must be high dUring the high to
low transitIOn of CEP and/or CET for correct
logiC operation. The CEP and CET Inputs may be
used in a high speed look ahead technique (see
application) .
Cou nter stages can be cascaded as shown above
to prOVide multiple stage BCD or Binary synchronous counting by using the DM75L52/DM85L52 or
the DM75L54/DM85L54 respectively. With a Terminal Count (TC) fan out of ten the above scheme
allows eleven stages to operate at the maximum
frequency equ ivalent to a two stage counter.
The Terminal Count (TC) output IS active high
when the counters are at terminal count and the
CET is high. The Terminal Count logiC equations
are:
Q
DM75L52/DM85L52
TC = CET'A'B'C'D
DM75L54/DM85L54
TC = CET'A'8,C'D
The characters displayed can be held with a low
level on the strobe line while the counters can
continue counting. The display can be updated by
applying a positive pulse to the strobe line.
The following logiC levels control the device:
• The counters changes state on the positlvegOing transition of the clock.
logic tables
FUNCTION TABLE
OUTPUTS
INPUTS
001
002
eEP
eET
CLEAR
PRESET
TE
1
x
x
x
1
0
0
0
0
X
X
x
X
0
0
0
0
X
X
X
X
X
X
X
1
x
x
x
x
x
1
1
1
0
,
x
x
0
0
A
B
e
Te
0
"High Impedance State"
,
'H~ro'r~'i s~" ..
0
1
LATCH
COUNT
1
1
1
0
1
'Functlon of the count sequence
DM75L52/DM85L52
DECADE COUNT SEQUENCE
OUTPUTS
e
0
OUTPUTS
COUNT
A
B
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
2
3
4
5
6
7
B
9
Te
**tfPreset
Applied
Next
Count
**The 1111 state may be used In conjunction with
certam decoder/drivers Ie, DM5446. DM5447
and DM5448 for blanking leadmg zeroes
3-76
DM75L54/DM85L54
BINARY COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
A
B
e
0
Te
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
c
s:
"r-CJ1
logic diagrams
DM75L52/DM85L52
,
OUTPUT
,
OUTPUT
"
r¢
J
OUTPUT
DISABLE
,
OUTPUT
r¢
"
o
r¢
~ ~
,
"
"
TRANSFER
ENABLE
CJ1
N
.......
C
s:
CO
~
,
TERMlIIIAl
COijtlT
OUTPUT
OUTPUT
CJ1
,
LATCH
,
"
r-
CJ1
N
,
C
s:
"rCJ1
CJ1
~
r-i>
.......
C
r---!--:-D'
----<"
a
:::u'
,
-+,-
r---!---
r--
--r--.; ,
a
"
- ~,
,
~'
"
'--
I
-+,-
>-- ~'
a
s:
-
CO
CJ1
r-
"
,
~,
~sp-
L......B4\u-
a
~'
~~
CJ1
~
a
~~
GOUNTENABLE
TRICKlf 0 -
rrDM75L54/DM85L54
,
OUTPUT
I
I
OUTPUT
OUTPUT
DISABlES
"
,
OUTPUT
CUTPIJT
o
I
COUNT
ENABLE~
COUNT
ENABLE
v
,o--{;;:
3-77
'lit
It)
...J
ac test circuit
It)
co
~
C
.......
~
I
AC
•
~
'lit
SEE
TABLE 1
It)
...J
OM15L52,
DM15L54
LOAD
~
'---
It)
r-.
~
C
FIGURE 1
N
It)
...J
It)
co
INPUT CONDITIONS
~
OD1
TEST
C
.......
N
It)
...J
It)
r-.
~
C
002
CET
CEP
CLEAR
PRESET
TRANSFER
ENABLE
CP
tpdO
GND
GND
Vee
Vee
GND
GND
See Note 1
tpd1
GND
GND
Vee
Vee
GND
GND
See Note 1
Vee
tpd(TEI
GND
GND
Vee
Vee
GND
GND
See Note 1
See Note 2
Vee
t'H
See Note 4
See Note 4
GND
GND
GND
Vee
GND
Vee
tOH
See Note 4
See Note 4
GND
GND
Vee
GND
GND
Vee
t H,
See Note 4
See Note 4
GND
GND
GND
Vee
GND
Vee
tHO
See Note 4
See Note 4
GND
GND
Vee
GND
GND
Vee
fCLOCK
GND
GND
Vee
Vee
GND
GND
See Note 9
Vee
TABLE 1
ac load circuit
TEST
SWITCH 81 SWITCH S2
CL
4001)
INPUTS
-
DM75L52,
OM15l54
r
T
...
....
c,
~:SEE
NDTES
)
"
tpdO
~,
r
DIODES
(SEE NOTE 6)
--
Closed
50 pF
tpd1
Closed
Closed
50 pF
tpd(TEI
Closed
Closed
50 pF
t'H
Closed
Closed
50 pF (See Note 8l
tOH
Closed
Closed
50 pF (See Note 8)
tH,
Open
Closed
50 pF
tHO
Closed
Open
50 pF
fclock
Closed
Closed
50 pF
FIGURE 2
Note 1 Pul5l! 9tll PRR.:;; 1 MHz, t,.< 15nl, lj< 5 ns, tpldod~Tcl,tJ>dlITCI.
Note8 Jlgcapacltance
Notll9 '_uSII50%dutycyde
3·78
Closed
0
s:
switching time waveforms
~
U1
Q
.{""""\
CP
~
~
\
r-
JV
U1
13V
N
OV
........
JV
s:
co
0
r---tplclockl
I \
PRESET
1
13V
\
U1
r-
OV
n--
CLEAR
J
L
U1
N
JV
0
13V
s:
OV
~
U1
JV
\
CE
r-
U1
-i=Io
13V
\
ov
........
0
s:
co
JV
13V
TE
U1
r-
OUTPUTS
OR
TC
-
OUTPUT
'pd1
tOR,
~
L~
r---- t----
U1
-i=Io
v"
13V
v"
tpdO
tOR
lV
lJV -IE
TE
ov
--~t---
,lV---t--t-
OUTPUTS
J
-
DI
-j~--IJV
OV
13V
V"---t--I'--V oc
;+Elr--
t1H
tOH
INPUTt
OV
13V
OV
"~
ACTUAL
LOGICAL'T'
OUT:U~~
VOLTAGE
ACTUAL
LOGICAL "0"
VOLTAGE
-j
JV
13V
"h
----r
OUTPUT,
5V
tHO
tH1
·"E"
INPUT
13V
OV.
OUTPUT
J
OUTPUT
J
JV
13V
13V
13V
3-79
c.o
r-.
...I
Series 54L/74L
c.o
co
~
C
.......
r-.
DM76l75/DM86l75 low power presettable decade counter
DM76L76/DM86L76 low power presettable binary counter
c.o
general description
~
C
The DM76L75IDM86L75and DM76L76/DM86L76
are synchronous up decade and binary counters
respectively. They have synchronous parallel load
capability, overriding asynchronous master reset,
terminal count and carry look·ahead logic for high
speed multl·decade operation.
c.o
...I
r-.
Operation can best be understood by realizing that
in order for counting to occur both C EP and C ET
must be at logical "1" levels. In addition the Tc
output is a logical "1" only when a counter is at
its maximum count (9 for the DM76L 75/DM86L1 ;
and 15 for the DM76L76/DM86L76) and when
the CET Input IS at a logical "1" level. Therefore
If counters are connected as shown, a more slgnlfl'
cant counter stage cannot be clocked until all
previous counters are at their maximum count.
The reason for the feedforward connection from
the least significant counter to all C EP Inputs IS
that no counter needs to wait for a ripple from the
previous counter when the least significant counter
changes from a maximum count to zero.
The counters are synchronous, with the counter
outputs changing state after the logical "0" to
logical "1" transition of the clock. When the
parallel enable input IS low, the parallel inputs
determine the next state of the counter synchronously With the clock.
Mode selection is accomplished as shown In the
table below. However the transition of CEP or
CET from logical "1" to logical "0" or of PE from
logical "0" to logical "1" may only be done With
CP In the logical" 1" state.
features
A logical "0" level on M R will reset all outputs
to logical "0".
The purpose of the CEP and CET Inputs and the T c
output is to prOVide for a fast propagation delay
when cascading several decades (shown below).
•
32 IT!W tYPical power
•
13 MHz tYPical count frequency
•
Series 54L/74L compatible
•
Pin compatible With 93L 10, 93L 16
logic and connection diagrams
i"
'I'
l c:?l-
I
:l
, ,
I
I
~'"
~\
i'
F,£t~
t::?r"O
IL __
-'-~
"
~
Dotted Ime IJortoons
------
p',
~'"'
Dr:',:
~',.'
- - ----
----- --
-
I
~
I
.p~h&able
"
0,
"co"
to DM75L 75/IlM86L 75 only
Dual-In-Line and Flat Package
3·80
r=-l-
~lr;-
I
,
Nut~
I
L
0,
J'..
0,
c
absolute maximum ratings
s:.....
(Note 1)
Supply Voltage
I nput Voltage
Output Voltage
Operating Temperature Range
DM76L75,DM76L76
DM86L75, DM86L76
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
Vee =: 4 5V
V cc -475V
Logical "0" Input Voltage
DM76L75/76
DM86L75/76
V cc =45V
Vee 475V
Logical "1" Output Voltage
DM76L75/76
DM86L75/76
Vee =: 4 5V
Vee - 4 75V
.......
.....
MIN
C
s:.....
V
V
07
0)
r-
.....
V
31
2.4
lOUT'" -200.uA
0)
Vcc=55V
Vee 525V
VIN '" 24V
CET
DM76L75/76
DM86L75/76
Vee == 5 5V
V cc -525V
V 1N =24V
DM76L75/76
DM86L75176
Vcc=55V
Vee 525V
VIN = 03V
V 1N =04V
DM76L75/76
DM86L75/76
Vcc=55V
Vcc- 525V
VIN ==
DM76L75/76
DM86L75/76
Vee'" 5 5V
Vee 525V
DM76L75/76
DM86L75/76
Vee'" 5 5V
V cc -525V
Supply Current
UNITS
MAX
13
13
DM76L75/76
DM86L75/76
(Note 3)
TVP
20
Logical "1" Input Current
All Inputs Except GET
Output Short Circuit Current
0)
r-
Vee'" 4 5V
Vee 475V
CET
C
s:00
C1I
DM76175176
DM86L75/76
All Inputs Except CET
.....
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
CONDITIONS
DM76L75/76
DM86L75/76
Logical "0" Input Current
r-
C1I
(Note 2)
logical ''1'' Input Voltage
Logical "0" Output Voltage
0)
8V
5.5V
5.5V
02
02
lOUT == 2 0 mA
lOUT
VIN
==
VIN '"
32mA
-3
C
s:
00
10
100
MA
MA
20
200
MA
MA
0)
-100
-180
MA
0)
-200
-360
MA
-9
-15
mA
9
mA
5 5V
a 3V
V
V
03
04
5 5V
V 1N =04V
.......
65
r-
.....
Propagation Delays
UI
Clock to Any Q Output
65
45
110
75
ns
ns
tpd1
85
70
140
115
ns
ns
tpdO
tpdl
35
35
60
60
ns
ns
"dO
tpd1
Clock to Tc Output
tpdO
GET to T c Output
t,ICE)
t, ICE)
Setup Time CE
Release Time CE
40
50
65
80
ns
ns
t,
t,
Setup Time P Inputs
Release Time P Inputs
15
15
30
30
ns
ns
ts(PE}
t,Il'E')
Setup Time Parallel Entry
Release Time Parallel Entry
40
40
65
65
ns
ns
Count Frequency
6
13
MHz
Clock Pulse Width
60
25
ns
Reset Pulse Width
80
30
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual deVice operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM76L75 and DM76L76 and across the O°C to 70°C range for the DM86L75 and
DM86L 76. All tYPlcals are given for Vee = 5 OV and T A = 25°C.
mode selection
PE
CE
MODE
1
1
1
Count
No Change
Preset
o
o
X
cascading counters
~
CCC~'C'PC"'
'0
~
e"
~
'0
e"
~
"
e"
~
COIJNT·_...._ _ _ _...._ _ _ _...._ _ _ _...._ _
3·81
...
N
...I
Series 54L/74L
CIO
CIO
:E
Q
DM88L12 TTL-MOS hex inverter/interface gate
general description
The DM88L 12 IS a low power TTL to MOS hex
Inverter element. The outputs may be "pulled up"
to +14V In the logical "I" state, thus providing
guaranteed Interface between TTL and MOS logiC
levels. The gate may also be operated With Vee
levels up to +14V Without resistive pull·ups at the
outputs and still providing a guaranteed logical "1"
level of \Icc - 2.2V With an output current of
-200 !lA.
schematic and cOhnection diagrams
Dual~ln-Line
40'
10K
and Flat Package
500
GND
TQPVIEW
"'
Note Shown Isschemal'c for each mve.le.
typical applications
TTL Interface to MOS ROM
TTL Interface to MOS ROM
Without Resistive Pull-Up
With Resistive Pull-Up
•
NATIONAL MOS ROM
{EXAMPLIMM521l
ac test circuits
switching time waveforms
p--30V
Vc,"140V
INPUTJ
J"'"''
3-82
fORVCC "14V
FORVcc ·50V
Figure 1
Figure 2
,..
i\---
::
ounUT~:1
,
.
,
1--- 50%---,
::
todO
-!
::
!~-:
:__
'0"'
~:;fO~;~ns
c
absolute maximum ratings
3:
operating conditions
(Note 1)
00
00
MAX
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
15V
55V
15V
--£5' C to +150' C
300'C
electrical characteristics
Supply Voltage
DM78L12
DM88L12
CONDITIONS
MIN
125
70
'c
'c
=
MAX
1.3
13
13
13
Vee= 140V
Vee
-55
0
TYP
20
20
Vee= 140V
Vee = Mm
Logical "0" I nput Voltage
5.5
5.25
Min
UNITS
V
V
07
07
Vee = 140V V ,N =07V
Vee = Min
Y'N = 0 7V
lOUT = -200)lA
lOUT = +200 JJ.A
Logical "0" Output Voltage
Vee = 140V Y'N = 2.0V
Vee = Mm
Y'N = 20V
IOUT= 12 mA
lOUT = 3 2 rnA
Logical"'" I nput Current
Vee= 140V Y'N = 24V
V 1N = 24V
Vee = Max
<1
<1
20
10
)lA
)lA
Vee = 140V Y'N = 5 5V
Vee = Max
Y'N = 5 5V
<1
<1
100
100
)lA
)lA
Vee = 140V Y'N = 04V
V ,N =04V
Vee = Max
-320
-100
-500
-180
)lA
)lA
-25
-8
-50
-15
rnA
rnA
Output Short Circuit Current INote 3)
Supply Current - LogIcal" 1"
(Each Inverter)
Logical "0"
.
Propagation Delay to a Logical "0"
Vee= 140V
Vee
=
Max
VOUT=
V OUT
OV
= OV
118
145
120
150
V
V
Logical"'" Output Voltage
Logical "0" Input Current
05
02
-10
-3
V
V
10
04
V
V
Vee= 140V Y'N = OV
Vee = Max
Y'N = OV
032
011
050
016
rnA
rnA
Vee= 140V Y'N = 525V
Vee = Max
Y'N = 5.25V
10
03
15
05
rnA
rnA
V ee =50V
TA= 2SoC
See Figure 2
27
45
ns
Propagation Delay to a Logical "0"
from Input to Output, tpdO
Vee= 140V
See Figure 1
TA=25'C
11
20
ns
Propagation Delay to a Logical "1"
from Input to Output, tpdl (Note 41
Vee= 50V
TA = 25'C
See Figure 2
79
100
ns
Propagation Delay to a Logical "1"
from Input to Output, !Pdt
Vee" 140V
See Figure 1
TA = 2SOC
34
55
ns
from Input to Output,
tpdO
N
(Note 2)
PARAMETER
Loglca' "1" Input Voltage
4.5
475
V
V
Temperature
DM78L12
DM88L12
r....
UNITS
Nota 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electrical Characteristics" prOVides conditions
for actual deVice operation
Note 2: Unless otherWise specified minImax hmlts apply across the -5SoC to +12SoC temperature
range for the DM78L12 and across the O°C to +70°C range for the DM88L12. All tYPlcals are
given for V CC = 5.0V and T A ~ 25' C, or for V CC ~ 14.0V and T A = 25' C.
Note 3: Only one output at a time should be shorted.
Note 4: t pd1 for VCC = S.OV IS dependent upon the resistance and capacitance used.
3-83
en
...
CD
Series 74S
REFERENCE
The following table references all PhYSical DimenSion Drawings for the devices In thIS section. For Order
Numbers, see below * Refer to the alpha·numerlcal Index at the front of thIS catalog for complete device
title and function. Packages (pages I thru VI) are In the back of the catalog.
DATA SHEETS
Devices
DM74S00
DM74S03
DM74S04
DM74S05
DM74S10
DM74S11
DM74S15
DM74S20
DM74S22
DM74S40
DM74S64
DM74S65
DM74S74
DM74S86
DM74S112
DM74S113
DM74S114
DM74S135
DM74S140
DM74S151
DM74S251
DM74S153
DM74S253
DM74S157
DM74S257
DM74S158
DM74S258
*Order Numbers
PACKAGES
Pg.
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4·1
4-1
4-1
4-1
4·5
4·1
4-1
4-1
4·5
4·1
4·7
4·7
4·7
4-7
4-7
4·7
4-7
4-7
Molded DIP (N)
Fig.
Pg.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
5
3
5
5
5
5
5
5
5
5
II
II
Cavity DIP (D)(J)
Fig.
Pg.
Type
Flat 'ack (F)(W)
Fig.
Pg.
Type
Metal Can (G)(H)
Fig.
Pg.
Type
WAVEFORMS
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
use Device No suffixed with package letter, I.e. DM74S00N
4-i
CJ)
...
CD
Series 74S
CD
en
series DM74S schottky-clamped transistor-transistor logic
general description
The gates, inverters, buffers and flip flops in the
DM74S series are ultra-high speed versions of the
similarly numbered devices in National's standard
senes 54/74 family. They can be used In combina·
tion with series 54/74 circuits whenever the absolute
minimum propagation delays are required.
•
Higher source and sink currents than standard
TTL
•
Fanout of 10 series DM74S loads or 12 standard
series 54/74 loads
•
Compatible with all senes 54/74 families
features
•
Pin identical to lower speed deVices
• Typical gate delay of 3 ns
•
19 mW typical power dissipation
connection diagrams (Dual-In-Line Package, Top Views)
DM74S00
DM74S03
DM74S05
DM74S04
tpd=lnstyp
tpd"5nstyp
tpd=3nstyp
tpd"5nstyp
Po" 19mWtvp/Gate
Po "17 mWtyp/Gate
Po" 19 mW tvp/Gate
Po" 17 mWtyp!Gate
DM74S11
DM74S15
DM74S20
DM74S10
tpd=3nstyp
tl>
MAX
TY>
75
t pLH
Propagation Delay Time,
Low tu High Level Output
tpHl.-
Propagation Delay Time,
High to Low Level Output
Data
tpLH
Propagation Delay Time,
Low to H'gh Level Output
Select
t pHL
Propagation Delay T,me,
High to Low Level Output
Select
95
15
tpLI<
Propagation Delay Time
Low to High Level Output
Strobe
85
125
tpHL
Propagatloll Dela', Time,
High to low Level Output
Strobe
75
12
',"
Output Ellable Time to
H'l}h Level
Output Control
Data
45
=
15 pF
=
280H
UNITS
75
65
95
MAX
45
15
85
65
15
11
'"
Output Enable Time to
Low Level
Output Control
.~,
Output Disable Time
From High Level
Output Control
Output DISable Time
From Low Level
Output Control
'"
MIN
~
50 pF,
=
280n
11
13
195
14
21
55
CL = 5 pF,
RL ~ 280n,
(Note 1)
85
14
DM7 4S 158/DM7 4S258
SYMBOL
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
tpLH
Propagation Delay Time
Low to High Level Output
Data
A,ly
tpHL
Propagation Delay Time,
High to Low Level Output
Data
AllY
t pLH
Propagation Delay T,me
Low 10 High Level Output
Select
Any
tpHl.-
Propagation Delay Time,
High to Low Level Output
Select
Any
TEST
CONDITIONS
=
15 pF
=
280£1
DM74S158
MIN
TY>
DM74S258
MAX
MIN
TY>
12
12
MAX
UNITS
12
75
12
Note 1 See load Circuits and waveforms on page 4 of thiS data sheet
4·9
ac switching characteristics (con't)
DM74S158/DM74S258
PARAMETER
SYMBOL
II)
DM74S158
FROM
TO
TEST
(INPUT)
(OUTPUTI
CONDITIONS
MIN
Q)
...
tpLH
Propagation Delav TIn'le,
Strobe
Aoy
Strobe
Aoy
Aoy
Low-to High-level Output
Q)
en
CL
:.
15 pF,
TVP
DM74S258
MIN
MAX
65
12
7
12
MAX
TVP
UNITS
"'
RL "'280n,
tpHI..
Propagation Delay Time,
t,"
Output Enable Time to
High Level
Output Control
t"
Output Enable Time to
Output Control
Aoy
t",
Output Disable Time
Output Control
Aoy
Output Control
Aoy
(Note 1)
"'
High to Low Level Output
13
CL = 50 pF,
oo
21
oo
RL = 280n
(Note 1)
"
Low Level
oo
85
55
CL = 5pF
From High Level
Output Disable Time
From Low Level
t"
195
AI.." 280U,
9
(Note 1)
"'
"
Note 1 See load Circuits and waveforms on page 4 of this data sheet
ac load circuits
voltage waveforms
Propagation Delay Times
B,-state Totem-pole Outputs
TRI-5TATE Outputs
IN'UT~
3V
r,sv
,.) i".
Tm
POINT
TEST
POINT
'"
··'-'n
IR'
"
Cl
""'' 1
OUTOFPHASE
OUTPUT
FROM OUTPUT
UNDUTEST
UNDEflTEST
'5~''"
'"
IN PHASE
OUTPUT
"
r-'~.:.."j
~IPLH
'"
'0'
~
IGV
VOH
ISV
---'oc
(Ngte2)
(Noll 2)
lkl!
-=-
"1
" ... " -=-
Enable and Disable Times, TRI-5TATE Outputs
'--
OUTPUT
CONTROL
f'
(~~~i~,~~~ ~
WAVEfORM I
(Iottl!
WAVEfORM 2
(lIote3)
~"
~'"~m'''
:':~q-->li
Zl
SIClOSEO~1511
SIANO
nCLOIEO
.45\1
r..2
SlClOSEO
'0'
511
110"
SIANO
S2ClOSfO
asv
~~15\1
15\1
• all
logic diagrams
DM74S151
STROBE
OUTPUT
CONTROL
"" '"
" '"
"' '"
"'
"
~~a
~
os
"
"
4-10
vF
114)
r
(5)
OliTPUTW
(INVERTING)
~. ,
,
v
~
r!
"' '"
"'
"
"
DATA
SELECT
(BINARYI
(S)
16)
(151
"
~
~,
(4)
"' '"
DATA
INPUTS
I-"
112)
B (lOIr-....
C
(91 r-....
~~UlPUTV
mONINVERTING)
~
1131
)11)
DATA
SELECT
(BINARVI
Ff--h-
115)
In
""
" '"
~
111
DATA
INPUTS
DM74S251
In
['
B
C
1\4)
~
nJl
(UI
(111
110L.f-.,.
(91----""
v
r;::-:- ,
~. ,
r----->,
DIJTPIJTV
(NDNINVERTlIIG)
OUTPlITW
(tNVERTINGI
logic diagrams (con't)
CD
1/1
DM74S253
DM74S153
"",1::"0"'-'01---FfFL--J
'" o.!!'-------+H-F=L..__
SELECT
{
'" o.!!'-------;:==+~I=L....I
'I
'21
:
SELECT
{
:
OUTPUTlY
OUTPUT
CONTROL
DM74S257
DM74S157
OUTPUT
CONTROL
DM74S158
DM74S258
4-11
truth tables
DM74S151/DM74S251
OUTPUTS
INfUTS
II)
G)
...
SELECT
G)
t/)
DATA
STROBE
DM74S251
DM74S151
C
B
A
OUTPUT
CONTROL
DO
01
02
03
0'
05
06
07
Y
W
Y
W
x
x
X
H
X
X
X
X
X
X
X
X
L
H
Z
Z
H
L
L
L
L
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
H
X
X
X
X
X
X
X
H
L
H
L
H
L
L
H
L
X
L
X
X
X
X
X
X
L
H
L
L
L
H
L
X
H
X
X
X
X
X
X
H
L
H
L
L
H
L
L
L
X
X
L
H
X
X
X
X
X
L
H
L
H
L
H
X
X
X
X
X
X
X
H
L
H
L
L
L
H
H
X
X
X
X
X
X
X
X
L
H
H
L
H
X
X
X
L
X
L
H
X
H
L
L
X
H
H
L
H
L
L
L
X
X
X
X
L
X
X
X
L
H
L
H
H
L
L
L
X
X
X
X
H
X
X
X
H
L
H
L
H
L
H
L
X
X
X
X
X
L
X
X
L
H
L
X
X
X
X
X
H
X
H
H
L
H
L
X
e
H
H
L
L
H
X
X
L
H
L
H
H
L
H
L
X
L
H
L
H
H
H
L
L
H
L
H
H
L
L
X
X
X
X
X
X
H
H
L
L
X
X
X
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
DM74S153/DM74S253
STROBE
SelECT
INPUTS
OUTPUTS
DATA
INPUTS
OUTPUT
CONTROL
DM74S153
DM14S253
B
A
G
CO
C1
C2
C3
y
y
x
X
H
X
X
X
X
L
Z
L
L
L
X
X
X
L
L
L
L
L
H
X
X
X
H
H
L
H
L
X
X
X
L
H
L
X
L
H
X
X
L
H
L
H
H
H
L
L
L
X
X
L
H
X
X
L
H
L
H
H
L
H
X
X
L
X
X
X
L
H
H
L
X
X
X
H
L
H
H
L
L
DM74S157/DM74S257,DM74S158/DM74S258
STROBE
SELECT
INPUT
A
B
DM74S157
DM74S158
DM74S257
DM74S258
X
H
X
L
H
Z
Z
L
L
X
L
X
L
H
L
H
L
L
H
X
H
L
H
L
H
L
X
L
L
H
L
H
H
L
X
H
H
L
H
L
H' hIgh level l,
4-12
OUTPUT Y
DATA
OUTPUT
CONTROL
~
low level X
~
Irrelevant, Z" h'gl1lmpedance (off)
L
en
...
CD
Series 930
CD
UI
CD
W
REFERENCE
o
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below. * Refer to the alpha-numerical Index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
Devices
Pg.
PACKAGES
Molded DIP (N)
Fig.
DM930
DM932
DM933
DM935
DM936
DM937
DM944
DM945
DM94 6
DM948
DM949
DM957
DM958
DM961
DM962
DM963
DM1800
DM1801
DM9093
DM9094
DM9097
DM9099
5·3
5·5
5-5
5-3
5-3
5-3
5-5
5-7
5-3
5-7
5-3
5-5
5-5
5-3
5-3
5-3
5-3
5-3
5-7
5-7
5-7
5-7
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pg.
Cavity DIP (D)(J)
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Fig.
Fig.
Pg.
Type
Pg.
Type
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
5-4
5·6
5-6
5-4
5-4
5-4
5-6
5-9
5-4
5-9
5-4
5-6
56
5-4
5-4
5-4
5-4
5-4
5-9
5-9
5-9
5-9
TEST
CIRCUITS
Fig.
Pg.
5·4
5·6
5-6
5-4
5-4
5-4
5-6
5-9
5-4
5-9
5-4
5-6
5-6
5-4
5-4
5-4
5-4
5-4
5-9
5-9
5-9
5-9
*Order Numbers: use Device No. suffixed with package letter, i.e. DM930N.
5-i
C
-I
r-
Series 930
en
.
CD
CD
CII
CD
DTL series 930 integrated circuits
W
o
general description
The National Semiconductor family of DTl
(Dlode-Translstor-logic) is a complete line of compatible monolithic Integrated circuits designed to
operate at medium speed with medium power dissipation and high fan-out. The DTl family is available in 14-pin, silicone, dual-In-Ilne packages for
operation over the O°C to 75°C temperature range.
The DTl line is composed of a variety of NAN D
gates that allow complete design flexibility. The
gates are available with either 6K pull-Up resistors
for low power dissipation, or 2K pull-Up resistors
for Increased speed. The gate outputs can be wired
together to achieve the wired-OR function.
The NAND gates are complemented with the
DM932 and DM957 buffers which provide higher
fan-out, the DM944 and DM958 power gates
which have an open collector, and the DM933
extender which allows Increased fan-in for both
buffers and the DM930 and DM961 gates.
The binaries In this family are of the direct coupled master-slave type with direct clear and direct
set lines. The dual flip flops include ones with
either common or separate clocks.
The DM930 series is directly compatible with the
TTL devices manufactured by National and can be
used in conjunction with them In those portions
of a system where speed IS not the main consideration.
table of contents
Absolute Maximum Ratings •...•.••..•..••.•..••••.•.•••..•••.••.•.•.•..•••....•.••.•..••..••.•.. 5-2
Connection/Logic Diagrams .••..••••.......•.•••..••..•....•••.••...•.•..•••.••••••.•.••••••.••.. 5-2
NAND Gates .•...••••.•..•...•..•.••.•..•. , . • . •• .•. ..•. ... .. .•• .••••••.•••••. •. .•.• • ••.••. ••••• 5·3
DM930, DM961 - dual four input gates with expanders
DM935, DM936, DM937 - hex Inverters
DM946, DM949 - quad two Input gates
DM962, DM963 - triple three Input gates
DM1800, DM1801- dual five Input gates
Buffers/E xtender • • . • . . . • . • • • . . • . • . . • . . . . . . • • . . . . • . • • . . • • . . . . • . . • . • • . • • . • . • • • . • • • • . • • • . • . . • . . • • .. 5-5
DM932 - dual four input buffer with expander
DM933 - dual four Input extender
DM944 - dual four input power gate with expander
DM957 - quad two Input buffer
DM958 - quad two Input power gate
Binaries ..•••••••..........•..•.............••...•••.....•..•..•••••••••.••..•.••.•......••.•.•. 5-7
DM945, DM948 - RS flip flops
•
DM9093, DM9094, DM9097, DM9099 - dual JK flip flops
5·1
o(V)
en
absolute maximum ratings
Power Supply Voltage
Continuous
Pu Ised < 1 sec.
Input Forward Current
Input Reverse Current
Output Current
Gates and B maries
Buffers
Storage Temperature
Operating Temperature
8.0V
l2.0V
10mA
1.0 mA
30mA
100mA
-65°C to 150°C
DoC to 75°C
connection/logic diagrams
:::::[::;~~3L_J:l--+13--+--..1
1I---j.-_ _ _.J
DM930/DM961
DM932/DM944
DM1800/DM1801
13_--j._ _"
;>00----+-- 10
13-+-----1 ':><>--1-- 12
11-+--1
DM935/DM936/DM937
=t=:::c):>---+-IO
DM946/DM949
10--,--1..-:=
11--'--'--'=
}-__-+_11
13-+----'
"'--~-
DM962/DM963
DM933
DM957/DM958
10-+---_...,
10-+----"
10-+++----.
11-+---1
13_+_-Q
l1-++-H
12-+--1
12-+--H
13-+~""'-~
DM945/DM948
5-2
11
»--+--12
,,--+___-1
1I--+__
1312::::j~:D--t-
DM9093/DM9094
DM9097/DM9099
NAND gates
The DM930, DM936, DM946 and DM962 are a
variety of NAND gates with a 6K pull-up resistor.
The DM961, DM937, DM949 and DM963 are the
2K pull-up versions of the respective gates. The
DM935 IS a hex inverter similar to the DM936
with the exception that it has no Input diodes.
The DM1800 and DM1801 dual 5-input NAND
gates are new DTL gates completely compatible
with DM930 series gates.
schematic diagrams*
14 {Ved
14 (Vcd
1 191
6181
o-........-.f
214.6. B. 10. 121
113.5.9.11.1310-. . . . . . . .--1
21101
31111
NOTE
4 1121
51131
llGNOI
llGNOI
DM930/DM961
DM935/DM936/DM937
14 (Ved
14 (Vccl
316.B.111
H..--f
114.9.1210-.....
1216.BI
113.910-........--1
214.1010-.....~'
215.10.131
50K
1315.111
llGNOI
llGNOI
DM946/DM949
DM962/DM963
14 (Vee!
1191
21101
31111
4 (12)
51131
llGNOI
DM1800/DM1801
-lfOnl y one
Circuit
element
IS
shown. Pm connections are given
In
parentheses for other Circuit elements
5-3
o
M
en
electrical characteristics
en
.!
...
Pin 14 (Vee)
=
5 0 volts, Pin 7
=
GND, unspecified pins open unless otherwise stated
CD
CONDITIONS
tn
SYMBOL
PART
PARAMETER
...I
INPUT
UNDER TEST
~
Q
V
oc
Output Low Voltage
V
o"
Output High Voltage
LIMITS
o'c
OUTPUTS
INPUTS
OTHER
All gates
V,"
V,"
All gates'
V"
Ve
MIN
Ie
All except
Ve
GND
I,
Input Forward Current
All except
935
V,
Ve
935"
V,
-
-
-
-
-
-140
-
-140
75°C
MAX
MIN
5
26
-
25
-
5
-
935
I"
Input Current
ICEX
Output Leakage Current
6k gates
2k gates
Output Short Clfeu It
Current
2k gates
GND
GND
"D
Power Supply Current
per gate
6k gates
Ve
I MAX
Max. Supply Current
per gate 1Vee " 8V)
All
t pd _
Turn-On Delay
I,c
t pd +
Turn On Delay
6k gates
--
GND
GND
GND
GND
2k gates
GND
-
-
6k gates
2k gates
R=400H,C=50pF
R" 400n, C '" 50 pF
-
6k gates
2k gates
R " 3 9kn, C '" 30 pF
R '" 3 9kSl, C '" 30 pF
-
-
1D
-
-133
mA
--
-125
-061
-
-185
-
4
59
-
-
4
-
10
10
30
30
--
25
15
80
60
-
-130
-390
(6k)
(6k)
(2k)
(2k)
TEMP.
V'H
VOLTS
V,L
VOLTS
VR
VOLTS
VF
VOLTS
VCEX
VOLTS
IOL
rnA
IOH
rnA
IOL
rnA
IOH
rnA
OoC
+25°C
+7SoC
2.0
1.9
1.8
1.2
1.1
0.95
4.0
4.0
4.0
045
0.45
050
5.0
12.0
12.0
11.4
-0.12
-0.12
-0.12
110
11.0
10.4
-0.5
-0.5
-0.5
-
~
~r
PULSE IN
PW >100n~
mA
mA
-
mA
-
"'
n. ~~~
0-
KY~
v,,~~
-
~
5-4
-:1-
V'~~
15V
r.::..
;~c~
':'
..
~Ii
VOUT
VOUT
7
r--
"A
"A
mA
mA
--
switching time test circuit and waveforms
R/
"A
-140
100
100
test conditions
Vee" 5V
V
mA
*Use an F0600 diode or eqUivalent on Input under test
-
V
-133
130
-
-
-
-
-
050
-140
-
-
UNITS
MAX
-
045
-
26
'0"
Input Reverse Current
MIN
045
'oc
except 935
2SoC
MAX
13V
'I
~,
15V
GNO
"'
"'
"'
C
-I
r-
buffers and extender
CJ)
(II
:::!.
of two four input diode nodes and can be used to
extend the fan-in of the DM930, DM961, DM932,
and DM944.
The DM932, DM944, DM957, and DM958 are
power gates which are capable of sll1king high
currents.
(II
C/I
CO
W
o
The DM933 is an extender element which consists
schematic diagrams*
{Veel \4
(Vcd14
1K
1 8~K
1 a5K
1 (9)
1(5,8,12)
15'
2{1D)
150
2(6,9,13)
6(8)
3(11)
3(4,10,11)
4(12)
2K
5(13)
63'
53'
IGNO) 7
(GND)7
DM957
DM932
§':
'~
:--r~-J
n
7 (GND)
DM933
(Vee) 14
Vee
81'
8"
1 (9)
1(5,a,12)
llIO)
2(6.9J3)
6(8)
3(11)
3(4,10,11)
2K
4(12)
5(0)
63'
53"
(GND) 7
DM958
DM944
*Only one
Circuit
element
IS
shown Pm connections are given
(GND)7
In
parentheses for other
CIrcuit
elements.
5-5
oCW)
en
..
electrical characteristics
III
.~
Pin 14 (Vee) = 5.0 volts, Pin 7
= GND,
unspecified pms open unless otherwise stated .
Q)
en
.......
CONDITIONS
PARAMETER
SYMBOL
PART
LIMITS
e
INPUT UNDER TEST
OTHER
MIN.
VOL
Output Low Voltage
932,944
957,958
V ,H
V ,H
10L
V OH
Output High Voltage
932,957
V ,L
VR
10H
IR
Input Reverse Current
932,944
957,958
VR
GND
'R
Input Reverse Current
933
VR
GND
IF
Input Forward Current
932,944
957,958
VF
VR
GND
V FD
Input Forward Voltage
933
IFD
Ise
Output Short Glr. Cur
932,957
GND
~
ICEX
Output Leakage Current
932,957
GND
~
944,958
GND
IpD
932
Power Drain Current
~
957
~
944
~
958
I MAX
Max. Supply Current
per gate (Vee =: 8V)
t pd _
Turn-On Delay
t pd+
Turn-Off Delay
26
~
GND
~
~
~
075
GND
-16
GND
VeE x
~
V CEX
~
~
~
~
~
~
~
~
~
~
~
932,944
957,958
~
~
~
~
GND
~
= 150n, C = 500 pF
932
957
R
944
958
R = 150n, C = 100 pF
932
957
R = 510n, C = 500 pF
944
958
R = 51On, C = 20 pF
25°C
O°C
OUTPUTS
INPUTS
MAX.
0.45
MIN.
~
5
~
-140
090
~
068
~
~
~
5
~
082
060
-14
300
pA
mA
075
~
mA
~
600
~
~
mA
~
225
~
~
mA
~
4.5
~
~
4
~
~
mA
~
mA
~
~
~
~
~
15
40
~
~
ns
~
~
~
10
35
~
~
ns
~
25
80
~
~
ns
~
15
50
~
~
ns
~
~
~
~
V,l
VOLTS
VR
VOLTS
VF
VOLTS
rnA
OoC
+25°C
+75°C
20
1.9
1.8
1.2
1.1
0.95
4.0
4.0
4.0
045
0.45
0.50
-2mA
-2mA
~
~
'FD
-2mA
VCEX
VOLTS
-
5.0
957
932
958
944
957
932
'Ol
rnA
IOl
rnA
IOH
rnA
36
36
34
40
40
36
-2.0
-2.5
-30
switching time test circuit and waveforms
Vee = 5V
~Y-ALL
OTHERS OPEN)
.
...~ :'"
~
~, D1
PULSE IN
PW>100ns
n
0-
~~
;:C2 ?
.,!. .,!.
1'::\
:;,t;,~
'=!:-
NOTE When testmg 958 (If 944 short dIOde 01, remove diodes
02,03,04 and 05 and add capacitor C2 ~ 20 pf as shown
5-6
~
""i
VOUT
pA
~
~
V,H
VOLTS
ri:\
pA
~
TEMP.
l'
V
mA
~
test conditions
v..
V
pA
10
.
ZOK
V
-133
200
~
~
~
~
~
100
MAX.
10
~
100
~
~
25
~
UNITS
050
~
5
~
~
25
MIN.
-1 40
~
-16
~
MAX.
0.45
~
2.6
~
5
75°C
.'.~
15.
DS
VOUT
y'
~..
tpd_
15.
GND
C
-I
r-
binaries
en
.
CD
The DM945 and DM948 are R-S flip flops which
can be externally cross coupled to perform In the
JK mode. They are of the master slave type with
output buffers to provide isolation from the out·
put load These flip flops feature both asynchro·
nous set and clear lines. The DM945 has a 6K
pull·up resistor and the DM948 has a 2K pull·
up resistor.
;'
of the DM945 and DM948 variety respectively.
Both flip flops have separate clocks and no asyn·
chronous clear lines.
en
CD
W
o
The DM9097 and DM9099 are dual JK flip flops
of the DM948 and DM945 variety respectively.
Both flip flops have common clocks and both
asynchronous set and clear lines.
The DM9093 and DM9094 are dual JK flip flops
schematic diagrams
Vee (141
Cp GNO'
Cp GND
121 (7)
121 (1)
DM945
DM948
truth tables
SYNCHRONOUS TRUTH TABLE
S,
S2
C,
Pin 3
PonO
Pin 12
X
X
0
X
0
X
0
0
0
X
1
1
X
X
1
1
1
X
0
1
1
1
0
X
1
a-
Low State (more negative)
1 -
High State (more positive)
Indetermmate State
U -
C2
Pin 11
0
0
X
0
J-K TRUTH TABLE
ASYNCHRONOUS TRUTH TABLE
t,,+ ,
t.
X
0
1
1
X
0
,
X -
a
P,"6
an
On
On
Qn
0
0
1
SD
Pin 10
CD
Q
0
Pin 5
P.. 6
Pm9
1
0
1
0
1
1
0
0
NC
NC
1
0
1
0
1
1
t,,+1
t.
S,
Pin 3
C,
Pm 12
0
1
0
1
0
0
1
1
Q
Pin 6
ON
1
0
ON
(Connect 5, to Q, C2 to QJ Asynchronous ,"puts,
direct set (Sol and direct clear (Col. override the
1
synchronous inPUts, they are Independent of all
U
other mputs
State of the
Input does not
affect the state
of the CirCUit
5·7
oCW)
en
schematic diagrams
.
III
CD
CD
en
.oJ
l-
e
D.....
.. U.dotttdllMtnpliceoftnlnslrtor
.. Restrtorw..uels2Kohms
DM9093/DM9094 (DM9093 shown)
c,r---------jt::::=========.-___
~
13
D.....
.. U. doned bnl Including nastar Ind tnllllltor In pIKa If direct Cp Input
•• RlHIItor ..lue IS IK ohms
DM9097/DM9099 (DM9097 shown)
truth table
J-K TRUTH TABLE
tn
tn
+1
S,
c,
a
Pin 3
PIn 12
Pin 6
0
1
0
1
0
0
1
1
aN
1
0
aN
Direct set (So J and direct clear (Co), override the
synchronous Inputs, they are mdependent of all
other Inputs
5-8
....r-c
switching time test circuits and waveforms
C/)
...
CD
Vcc '5V
CD
en
CD
W
o
DM945iDM948
/3,11]
(2,12)
---,
14
--r-Q Vcc -5V
~
I
":"
.1
~I
:1
;)Jl-"-"__...JI __ -- ~~'-'"--
1
I
I
I
I
1
FIXED
LOAD
---"
VARIABLE
I
LOAD
GNO
15.
GNO
Cl and C2 mcludeplObeand)lgcapacllY
All dllldesale F06000r equ.valentat +25 C
DM9093iDM9094
lone~half
circuit shown)
PW>50Dm
511%OC
V, ..
25VMIN
,-
~D
,,"
---t~'---_--.J
-If'v
FIXED
LOAD
-'-----GNO
GNO
VOUT
VARIABLE
LOAD
NOTE To;t,.lUpfo,on.h.lld.aIJK,how"
DM9097 iDM9099
5~9
.0
('I)
en
DM945/DM948
(I)
CD
'i:
electrical characteristics
en
Pin 14 (Vee)
CD
~
~
5 0 volts, Pin 7
GND
...I
I-
CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNITS
PART
Q
C,
5,
5,
Q
Co
So
C,
o'c
C,
MIN
V oc
Output Low Voltage
Both
CPo
GNO
1oc
Vo ,
Output High Voltage
(Data Inputs)
945
CP,
V,"
V"
1o,
948
CP,
V"
V"
Vo ,
Output High Voltage
(Set Reset Inputs)
Both
CP,
GND
GND
V"
Input Reverse Current
"0
MAX
MIN
045
COMMENTS
7SoC
MAX
MAX
MIN
X"Momentary
050
045
God
26
V"
26
26
25
26
26
26
Both
GNO
Input Reverse Current
(Set Reset Inputsl
Both
CP,
GND
GND
V,
I"
Input Reverse Current
(Clock Input)
Both
V,
GNO
GNO
GNO
V"
'0 ,
2S
V"
1o,
I,
26
X=Momentary
God
50
50
100
"A
50
50
100
"A
30
40
-095
-095
_090
'"'
mA
-28
-28
-267
mA
-28
-28
-266
mA
-28
-28
-267
mA
-138
-40
"A
mA
mA
V,
(Data Inputs)
ICD
Input Forward Current
(Data Inputs)
Both
I,
Input Forward Current
{Set Reset Inputsl
Both
I,e
2SOC
Input Forward Current
(Clock Input)
V,
V,
Vee
30
V,
GNO
V,
945
V,
V"
948
V,
V"
ICE ){
Output Leakage Current
Both
I,e
ShortCffcult Current
945
948
CP,
CP,
"0
Power Dram Current
945
948
Vee
Vee
GND
GND
VCEX
GND
GNO
GNO
GNO
GND
GND
-141
-059
-177
_42
100
-059 -141
_177 _42
-055
_160
17
mA
mA
18
23
mA
mA
14
GND
GND
GND
GND
GND
GNO
GND
GNO
GNO
GND
GNO
GNO
I MAX
Max Supply Current
(Vee = BV)
945
948
tpd_
Turn-On Delay
945
948
R=330n, C=50pF
R = ,non, C = 50 pF
15
15
55
55
I",.
Turn-Off Delay
945
948
R = 2 Okn, C = 30 pF
R '" 2 Okn, C=30pF
25
25
IDa
75
V AC
volts
test conditions
TEMP.
00 C
+25° C
+750 C
V,H
VOLTS
V,L
VOLTS
VF
VOLTS
VA
VOLTS
2.0
1.9
1.8
1.2
1.1
0.95
0.45
0.45
0.50
4.0
4.0
4.0
I
I
I
>25V
I
I
I
I
,y
I
I
PRESET
REMOVED
TEST
CP,
5-10
945(6K)
948(2K)
945(6K)
948(2K)
945(6K)
948(2K)
VCPTH
V CPTH
VOLTS
VOLTS
IOL
rnA
IOL
rnA
IOH
rnA
IOH
rnA
1 15
0.95
0.65
1.30
1.15
0.85
16.8
16.8
16.0
15.4
15.4
14.6
-0.12
-0.12
-0.12
-0.5
-0.5
-0.5
I
>25V
I
I
I
I
I
I
I
I
I
VCPTH
I
I
,y
I
I
I
PRESET
REMOVEO
TEST
cp.
I
= 40
VCEX
VOLTS
5.0
C
-I
r-
DM9093/DM9094/DM9097/DM9099
tJ)
...
;.
CD
electrical characteristics
Pm 14 (Veel
en
= 5 0 volts. Pm 7 = GND
CD
LIMITS
SYMBOL
PARAMETER
PART
o'c
CONDITIONS
MIN
va'
Output low Voltage
All
IOL on output under test
VOH
Output HI!/! Voltage
All
101-1 on output under test
I,e
Output Short CircUit
Current
- 7SOC
+25°C
MIN
MAX
MIN
MAX
045
UNITS
050
045
26
V
25
26
2k
GND output under test
-177
-42
-177
-42
-160
-40
mA
6'
GND output under test •
-059
-141
-059
-141
-055
-138
mA
1'0
Input Forward Current
(Data Input)
All
V F on Input under test
VA onothermputs
-095
-095
-090
mA
I'e
I nput Forward Current
9097
9099
VF on Input under test
-56
-56
-534
mA
I,e
Input Forward Current
(Clock Input)
9093
9094
VF on mput under test
VA on others
-28
-28
-267
mA
Input Forward Current
All
VF on mpu1undel'"test
VA another Inputs
_2.
_28
-267
mA
All
VA on Input under test
GND on other Inputs
50
'0
100
pA
VR on Input under test
GND on other Inputs
10
10
20
pA
20
20
30
pA
9094
VR on Input under test
GND on other Inputs
9087.
9099
V R on IOput under test
GND on other Inputs
40
40
60
I,
(Clock and Direct Clear
InputsJ
(Direct Set Inputs)
I,
Input Reverse Current
(Altexceptclock Inputs
and Direct clear Input
on 9097, 9099)
I,
Input Reverse Current
Direct (Clear Input)
9097&
I,
Input Reverse Current
(Clock Inpunl
9093&
1'0
Power Drain Current
9099
9093
9094
9099
9097
I MAX
Max Supply Current
(Vee'" BV)
9093
9099
9094
V R on other mputs
34
36
mA
45
mA
34
28
GND all mputs
pA
mA
mA
mA
mA
28
Inputs Open
InpuuOpen
Inputs Open
Inputs Open
9097
tpd_
Turn-On Delay
All
R-330Q,C-50pF
15
55
t ...
Turn-Off Delay
6k
R-2k,C .. 30pF
R=2k,C=30pF
25
25
100
75
2k
test conditions
TEMP.
(6kl
IOL
mA
mA
mA
mA
00 C
+25°C
+75°C
16.8
16.8
16.0
15.4
15.4
14.6
-0.12
-0.12
-0.12
-0.5
-0.5
-0.5
(2kl
IOL
(6kl
IOH
(2k1
IOH
VR
VOLTS
VIH
VOLTS
VIL
VOLTS
0.45
0.45
0.50
40
4.0
4.0
2.0
1.9
1.8
0.95
1
I
I
>Z5V
I
I
.v
VF
VOLTS
1
I
1
I
PRESET
REMOVED
TEST
er.
I
>25V
IV
9094-7
2K
VCPTH
115
0.95
065
130
115
085
1.2
1.1
1
1
1
I
I
Vc,nl
9093·9
6K
VCPTH
1
1
1
1
1
I
I
I
1
I
rEST
'RESET
REMOVED
W
0
MAX
CP,
5·11
en
CD
:.
Series 9000
illS
CD
Ul
U)
o
o
o
REFERENCE
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below.' Refer to the alpha·numerical index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
Pg.
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM8300
DM9300
DM8301
DM9301
DM8309
DM9309
DM8312
DM9312
DM8322
DM9322
DM8601
DM9601
6·1
6·1
6·1
6·1
6~ 1
6~ 1
6~ 1
6~ 1
6~ 1
64
64
6~6
6~6
6~8
68
6~ 10
6~ 10
6~12
6~
12
6~ 14
6~14
Cavity DIP (D)(J)
Fig.
Pg.
Fig.
Pg.
Type
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
5
5
3
3
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
11
11
IV
j
IV
j
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
j
II
II
II
Flat Pack (F)(W)
Fig.
Pg.
19
19
19
19
19
19
19
19
19
19
18
18
V
V
V
V
V
V
V
V
V
V
V
V
Type
Metal Can (G)(H)
Fig.
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
36
36
5
5
39
39
40
40
37
37
38
38
11 ~ 17
11 ~ 17
11·5
11 ~5
11 ~ 18
11 ~ 18
11 ~ 18
11 ~ 18
11 ~ 17
11 ~ 17
11 ~ 17
11 ~ 17
9
9
1
1
1
1
1
1
14
14
8
8
11 ~2
11 ~2
11 ~ 1
11-1
11 ~ 1
11 ~ 1
11 ~ 1
11 ~ 1
114
114
11 ~2
j
j
j
j
j
j
j
j
J
J
J
J
J
J
J
J
J
J
W
W
W
W
W
W
W
W
W
W
W
W
11~2
'Order Numbers: use Device Number suffixed with package letter, I.e., DM9002CN.
6-i
Series 9000
~
(/I
CD
o
o
DM9002C
DM9003C
DM9004C
DM9005C
o
quad 2-input NAND gate
triple 3-input NAND gate
dual 4-input NAND gate
dual AND-OR-INVERT gate/expander
DM9006C dual 4-input expander
DM9008C 2-2-2-3-input AND-OR- INVERT gate
DM9009C dual 4-input NAND gate/buffer
DM9012C quad 2-input NAND gate(open collector)
DM9016C hex inverter
general description
the DM9000 Series devices. The "c" designation
is used in place of the earlier "-59X" suffix.
The above' gate fu nctions are commercial temperature range (O°C to +75°C) plug-in equivalents for
connection d iag rams
DM9002C
(Dual-In-Llne and Flat Packages)
DM9003C
DM9004C
DM9006C
DM9008C
~
~
GND
DM9005C
GND
DM9009C
DM9012C
DM9016C
6-1
o
o
o
en
absolute maximum ratings
III
Q)
...
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Q)
(f)
7V
5.5V
O°C to + 75°C
-65°C to +150°C
300°C
electrical characteristics
DM90002C, DM9003C, DM9004C, DM9012C, DM9016C
PARAMETER
(Note 1)
CONDITIONS
MIN
Logical "1" Input Voltage
Vee~475V
Logical "0" Input Voltage
Vee~475V
Logical "1" Output Voltage
Vee
~
4 75V, lOUT
=
-12 rnA, V ,N
Vee
Vee
~
4 75V, lOUT
5 25V, lOUT
~
~
+141 rnA. V ,N ~ 1 6V
+16 rnA, V ,N ~ 525V
Vee
~
4 75V, V OUT
Logical "1" Input Current
Vee
~
5 25V. V ,N
~
4.5V
Logical "0" Input Current
Vee
Vee
~
5 25V. V ,N
4 75V, V ,N
~
45V
45V
Supply Current - Logical "0" Output
(each gate;
Vee~50V
MAX
16
V
85
~
85V
UNITS
24
V
V
Except DM9012C
Logical "0" Output Voltage
Logical "1" Output Current
~
~
5 5V, V ,N
~
45
45
250
.85V
V
V
/lA
(DM9012CI
~
~
Supply Current - Logical "1" Output
(each gate)
Propagation Delay Time to a Logical "1 "
Except DM9012C
DM9012C
Propagation Delay Time to a Logical "0"
Except DM9012C
DM9012C
60
/lA
-I 6
-1 41
rnA
rnA
61
rnA
17
rnA
30
13
~4kn
30
45
ns
Vee ~ 5 OV, CL ~ 15 pF. T A ~ 25'C
30
15
ns
30
15
ns
MIN
MAX
Vee~50V,CL ~
~
Vee
5 OV, C L
~
15pF. RL
15 pF. RL
~
4oon.
ns
T A = 25°C
DM9005C, DM9006C, DM9008C (Note 1)
PARAMETER
CONDITIONS
16
UNITS
Logical "1" Input Voltage
Vee~475V
Loglcal"Q" Input Voltage
Vee~475V
Logical "1" Output Voltage
Vee = 4 75V, lOUT"" -1 2 mA,
V ,N ~ 85V
Logical "0" Output Voltage
Vee = 4 75V, lOUT'" 14 1 mA,
V ,N 1 6V
45
V
Vee'" 4 75V, lOUT == 16 rnA,
45
V
V
85
24
V
V
0
V'N~525V
Logical "1" Input Current
Except DM9005C Non·
Vee
~
4 75V. V ,N
~
4 5V
90
/lA
Vee
~
4 75V. V ,N
" 45V
60
/lA
-212
-24
-141
-16
rnA
rnA
rnA
rnA
77
13.6
17.7
rnA
rnA
rnA
Extendable Gate
DM9005C Non-Extendable Gate
Logical "0" Input Current
Ex~ept DM9005C Non·
Extendable Gate
DM9005C Non-Extendable Gate
Vee ~ 4 75V, V ,N ~
Vee ~ 5 25V. V ,N ~
V ee ==475V,V IN '"
Vee ~ 5 25V, V ,N =
45V
45V
45V
45V
Supply Current - Logical "0" Output
DM9005C Non-Extendable Gate
DM9005C Extendable Gate
DM900BC
Vee~50V
Vee
Vee
~
~
5 OV
5 OV
Note 1: All deVices are guaranteed across the Que to +75°e temperature range except where specified differently_
6·2
CJ)
CD
...
electrical characteristics (con't)
CD
en
CD
0
0
0
DM9005C, DM9006C, DM9008C (con't)
CONDITIONS
PARAMETER
Supply Current - Logical "1" Output
DM9005C Non-Extendable Gate
MIN
Vee" 5 OV
Vee" 5 OV
Vee"50V
DM9005C Extendable Gate
DM9008C
MAX
UNITS
34
51
102
mA
mA
mA
6Supply Current
Additional Supply
Current when one DM9006C
Extender IS connected to a
OM g005e Gate
Additional
the Logical "0" State
In the Logical "1" State
205
mA
254
mA
In
Vee" 5 OV
Propagation Delay Time to a Logical "1"
V ee "SOV,C L "15pF,
T A " 2S"C
OM g005e Non-Extendable Gate Only
DM9005C Extendable Gate, and
30
30
DM9008C
DM9006C INote 2)
-20
Propagation Delay Time to a Logical "0"
Vee" 5 OV, C L
T A" 25"C
"
12
15
ns
ns
40
ns
15 pF,
DM9Q05C Non-Extendable Gate Only
DM9005C Extendable Gate, and DM9008C
30
30
I
DM9008C
DM 9006C (Note 2)
14
12
ns
ns
-20
40
MIN
MAX
ns
DM9009C (Note 1)
CONDITIONS
PARAMETER
Logical "1" Input Voltage
Vee" 4 75V
Logical "0" Input Voltage
Vee" 4 75V
Logical "1" Output Voltage
Vee
=
V ,N
"
Loglcai "0" Output Voltage
16
V
8S
4 75V, lOUT
-=-
-36 mA,
=
42 3 mA,
24
V
V
85V
Vee == 4 75V, lOUT
V'N=16V
Vee == 5 25V, lOUT == 48 mA,
V IN =525V
~
UNITS
Loglca! "1" Input Current
Vee
Loglca! "0" Input Current
Vee" S 25V, V ,N
45
V
45
V
120
5 2SV, Y'N " 4 SV
Vee == 4 75V, VIN '" 45V
Supply Current - Loglca! "0" Output
Vee=50V, VIN =45V
146
mA
Supply Current - Logical "1" Output
Vee:::; 5 OV, VIN
34
mA
Propagation Delay to a Loglcal"1"
Vee" 5 OV, C L
"
15 pF, TA ~ 25°C
30
17
ns
Propagation Delay to a Logical "0"
Vee" 5 OV, C L
"
15 pF, TA " 25°C
20
13
ns
45V
GND
g
IlA
-32
-282
"
mA
mA
Note 1: All deVices are guaranteed across the O°C to +75°C temperature range except where specified differently
Note 2: The DM9006C IS tested by measuring ItS propagation delay through the DM9005C The delay readings shall not exceed
the DM9005C reading by the speCified amount
6-3
o
o(W)
Series 9000
00
:E
c
.......
DM9300/DM8300(SN54195/SN74195) 4-bit shift register
o(W)
en
general description
o
The DM9300/DM8300 IS a 4-blt multi-function
shift register designed to wOrk at tYPical speeds of
:E
c
25 MHz_
It features a common asynchronous Reset Input
which resets the register Independent of any other
Input In addition, the J and K Inputs to the first
flip flop enable greater flexibility In the operation
of the register (See truth table)
shifted nght When the fiE Input IS In the logical
"0" state, the Information on the parallel Inputs
will be entered Into the flip flops on the subsequent clock pulse A logical "1" level on the PE
control will allow shifting to the nght
The outputs change state on the positive-going
transition of the clock Input
The PE (Parallel Enable) control allows information to be entered from the parallel Inputs or be
This register IS completely compatible with Senes
54/74 and CCSL devices Input diode clamps are
provided for additional system reliability
connection diagram
truth table
Dual-I n-Line and Flat Package
J
K
0
0
0
1
1
0
Clo
at tn+1
a
00 at tn
1
(no change)
00 at tn
1
dOE ~
(toggle)
1
logIcal "I", MR = logIcal "1")
typical application
Eight Bit Left/Right Shift RegISter
This register shifts left or fight on each shift clock, depending upon the condition of the LS/RS select
Input If this Input IS high, fight shift occurs and If low, left shift occurs
lS/RSSELECT
AS DATA IN
L~:
LSDATAOUT
CLOCK
PE
III
P,
P,
P,
P,
MR
'"
n,
II
II,
I
J
n,
oM930OIDM8300
n,
P,
MR
n,
-JCP
K
III
PE
P,
P,
LS DATA IN
P,
n,
DM931JIIIDM8JOO
n,
II
n,
n,
I
MASTER RESET
equivalent circuits
,------.--,,,
QU1PUT CllRRENT VERSUS OUTPUT VOlTAGE
10" 0, 0, O, AND !hl
6-4
RSDATADUT
o
s:CD
absolute maximum ratings
vcc
electrical characteristics
W
o
o
........
-.5V to 7V
-.5V to 5.5V
5.5V
-55°C to +125°C
oDe to 75°C
-65°C to +150°C
300 DC
Voltage Range
Input Voltage Range
Output Voltage (Logical "1" state)
Operating Temperature Range DM9300
DM8300
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
= _55°C 10 +125°C,
(T A
o
s:
CO
W
o
o
Vee'" 5 OV ±10%)
LIMITS
SYMBOL
_SSOC
CHARACTERISTICS
V OH
Output High Voltage
VOL
Output Low Voltage
V ,H
Input High Voltage
V ,L
Input Low Voltage
MIN
24
MAX
Vee=45V.
10H
= -0 36 rnA
Volts
Vee = 55V.
Vee=45V.
10L
= 9 6 rnA
= 7 44 rnA
Volts
Guaranteed Input high
threshold for allmputs
08
Volts
Guaranteed Input low
threshold for all Inputs
-110 -16
-097 -124
-1 6
-1 24
rnA
rnA
Vee=55V V =04V
Vee = 4 5V
F
15
60
pA
Vee =55V. V R =45V
24
27
02
04
17
04
14
08
09
-16
-124
Input Leakage Current
K. MR. po. p, . P, & P3
UNITS CONDITIONS & COMMENTS
MIN MAX
Volts
24
20
J,
IR
TY?
0.4
Input Load Current
K, MR, po. P1, P2 & P3
IF
+12S oC
+2So C
MIN MAX
60
10L
J.
electrical characteristics
(T A
::=
O°C to +75°C. Vee = 5 OV ±5%)
LIMITS
SYMBOL
DoC
CHARACTERISTICS
+25°C
MIN MAX
V OH
Output High Voltage
VOL
Output Low Voltage
VH
Input High Voltage
MIN
TY?
24
24
02
045
18
UNITS CONDITIONS & COMMENTS
MIN MAX
24
30
045
19
+75°C
MAX
045
10H
= -0 36 rnA
10L
= 9.6 rnA
= 8 5 rnA
Vee
Vee
Volts
16
= 4.75V,
= 5 25V.
Vee = 4.75V.
Volts
Volts
10L
Guaranteed Input high
threshold for all mputs
VL
Input Low Voltage
085
085
085
Volts
Guaranteed I nput low
threshold for allmputs
Input Load Current
IF
J.
IR
K. MR.
po. P P, & P3
"
-16
-141
Input leakage Current
J,
K, MR,
-16
-141
-16
-141
rnA
rnA
15
60
60
pA
CHARACTERISTIC
(TA
MIN
= 25"CI
TY?
MAX
tpd+
Turn Off Delay
12
22
tpd_
Turn On Delay
19
38
26
f"
Shift Right
Frequency
30
CP pw
Clock Pulse Width
17
I,
Set-up Time
30
Ie
I,{PEI
Release Time
-
'e(PEI
-
tpd_~~1
trec(MR)
MRpw
= 525V
= 475V. V F =045V
Vee = 525V. V R = 4 5V
Vee
Vee
Po, P 1 , P 2 & P3
switching characteristics
SYMBOL
-1.0
-09
Set up Time for PE
Release Time for PE
Reset Time for MR
-
45
Vee = 5 OV. CL = 15 pF
(See Figs 1 & 2al
MHz
Vee = 50V. CL = 15pF
(See FIgs 1 & 2el
ns
Vee = 50V
CL = 15 pF
ns
(See Figs 2a & 2bl
ns
0
20
17
CONDITIONS & COMMENTS
ns
ns
ns
11
13
10
UNITS
10
ns
28
ns
Recovery Time for MR
13
ns
Min Reset Pulse Width
15
ns
SET UP TIME ts IS defined as the minimum time required for the logiC level to be present at the logiC
Input prior to the clock transition from low to high In order for the flip flop(s) to respond
RELEASE TIME tr IS defined as the maximum time allowed for the logiC level to be present at the
logiC Input prior to the clock tranSition from low to high In order for the flip flopls) not to respond
RECOVERY TIME FOR MR treclMR} IS defined as the minimum time required between the end of
the reset pulse and the clock tranSitIOn from low to high In order for the flip flop(s) to respond to the
clock
6-5
...o
CO)
Series 9000
00
~
o
...
.........
oCO)
0)
~
DM9301/DM8301 BCD-to-decimal decoder
general description
features
The DM9301/DM8301 utilizes Series 54/74 compatible circuitry to decode a four-bit BCD number
to one-of-ten decimal outputs. These ten decimal
outputs are capable of driving 10 standard TTL
loads each.
•
125 mW tYPical power dissipation
•
20 ns tYPical propagation delay
•
Clamp diodes on Inputs
The decoding logic IS designed such that when
binary numbers between 10 and 15 are applied to
the Inputs, no outputs are enabled.
logic and connection diagrams
Dual-In-Llne and Flat Package
logic table
OUTPUTS
INPUTS
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
6-6
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c
absolute maximum ratings
~
CD
(Note 1)
W
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range DM9301
7V
55V
CONDITION
Logical "1" Input Voltage
DM9301
DM8301
Vee = 4 5V
V ee -475V
Logical "0" I nput Voltage
DM9301
DM8301
Vee = 45V
Vee - 4 75V
Logical "1" Output Voltage
DM9301
DM8301
Vee = 4 5V
V ee - 475V
lOUT = -600 /lA
Logical "0" Output Voltage
DM9301
DM8301
Vee = 4 5V
V ee - 4 75V
lOUT = 16 mA
Input Current
DM9301
DM8301
Vee = 5 5V
Vee - 525V
V ,N = 4 5
Logical "1" Input Current
DM9301
DM8301
Vee = 5 5V
Vee - 525V
V ,N = 55V
Logical "0" I nput Current
DM9301
Vee = 55V
----;-;-"-'--DM83-6T Vee = 5 25V
V ,N = 04V
I nput Clamp D lode (All I nputsl
DM9301
DM8301
Vee = 5 5V
Vee - 525V
I'N=-12mA
DM9301
DM8301
Vee = 5 5V
V ee -525V
V OUT = OV
DM9301
DM8301
Vee=55V
Vee - 525V
:'1"
Output Short Circuit Current
(Note 31
Power Supply Current
~
CO
W
o....
(Note 2)
PARAMETER
Logical
C
10
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
DM8301
Lead Temperature (soldering, 10 sec)
electrical characteristics
o
....
......
MIN
TYP
MAX
20
V
08
24
V
V
04
-20
-18
UNITS
V
40
/lA
1
mA
-10
-16
mA
-10
-15
V
-32
-55
mA
25
41
mA
Propagation Delay Time to a Logical "0"
Vee= 50V, T A = 25°C,
COUT = 50pF, F 0 = 10
8
19
30
ns
Propagation Delay Time to a Logical "1"
Vee = 50V, T A = 25°C,
COUT = 50pF, F 0 = 10
8
20
30
ns
D
Note l' "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operatlng Temperature Range" they are not meant to Imply that the
devices should be operated at these limits The table of "Electrical Characteristics" provides conditions
for actual device operation
Note 2' MinImax limits apply across the guaranteed operating temperature range -5SoC to +12SoC for
DM9301 and
aOc
to 70°C for the DM8301 unless otherwise specified All typlcals are given for
Vce = 50V and TA = 25°e
Note 3: Only one output may be shorted at a time
6-7
en
o
('t)
co
Series 9000
~
c
.......
en
o
('t)
en
DM9309/DM8309 dual 4-input multiplexer
c
general description
features
The DM9309/DM8309 IS a dual four-Input digital
multiplexer. It consists of two multiplexing CirCUitS with common input select data logic. Each
CirCUit contains four Inputs and fully buffered
complementary outputs.
•
~
Series 54174 T2L and DTL compatible
•
Input clamping diode
•
Fully buffered complementary outputs
•
Fan-out of 10
logic and connection diagrams
Dual-I n-Llne and Flat Package
I~
I"
12
4
115
15
"
13
11
11
.--
z,
rr
":"
13
s,
1
f-
1
Vee
S,
truth table
SELECT INPUTS
L
=
OUTPUTS
So
S,
lOA
I'A
"A
13A
ZA
ZA
L
L
L
X
X
L
H
L
L
H
X
X
H
L
L
X
X
X
X
H
X
X
X
X
L
H
X
L
X
X
H
H
L
ZB
ZB
L
H
H
L
L
H
H
L
X
X
L
H
X
L
H
X
H
H
H
H
X
X
So
S,
lOB
"B
"B
13B
L
L
L
L
L
H
X
X
X
X
H
L
X
X
X
X
L
X
H
X
X
X
X
X
X
H
L
X
X
L
L
H
H
H
L
H
L
L
H
L
H
H
H
X
H
H
X
Low Voltage Level
H -= High Voltage Level
X = Irrelevant
6-8
INPUTS
H
X
X
X
X
X
L
9
10
X
X
H
L
L
H
X
H
L
L
H
H
L
L
H
H
L
L
H
3
4
5
6
,
I'
C
absolute maximum ratings
s:
CD
operating conditions
(Note 11
w
0
Supply Voltage
Input Voltage
\
Output Voltage
Storage Temperature Range
Lead Temperature (Solqerl ng, 10 sec)
7V
55V
55V
_65 c C to +150"C
300 c C
Supply Voltage (Vccl
DM9309
DM8309
MIN
MAX
UNITS
45
475
55
525
V
V
-55
+125
70
°c
CD
.........
C
s:00
Temperature (T A)
DM9309
DM8309
0
C
c
W
0
CD
electrical ch a racteristics
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Logical "1" Input Voltage
Vee =- Min
Logical "0" Input Voltage
Vee
Logical "1" Output Voltage
_
V 1N (11 = 2V
_
Vee - Min, V'N(01 ~ 8V IOH - -800pA
Logical "0" Output Voltage
Vee
==
Min,
Logical" 1" Input Current
Vee
=
Max, VIN
=
2 4V
40
!1A
Vee
~
Max, V ,N
~
5 5V
1
mA
Logical "0" I nput Current
Vee
=
Max, VIN
==
4V
-16
mA
Output Short
(Note 31
Vee"" Max
ClfCUlt
Current
-'C.
2
Min
08
V 'N (lI
~
V1N(O) --;
V
2V
8V IOL == 16 mA
Supply Current
Vcc=-Max
Input Clamp Voltage
Vee =- Min, I'N~-12mA
Propagation Delay to a Logical "0"
24
V
04
-30
-27
27
V
-85
mA
44
mA
-1 5
V
Vee ~ 5 OV, T A ~ 25"C
24
35
ns
V ee ~ 5 OV, T A ~ 25"C
10
15
ns
Propagation Delay to a Logical "1"
from Data to Z, tpdl
V cc ~ 5 OV, T A ~ 25"C
20
28
ns
Propagation Delay to a Logical "1"
from Data to Z, tpdl
Vee~ 50V, TA ~ 25°C
15
22
ns
5 OV, T A ~ 25 c C
30
25
45
37
ns
ns
V cc ~ 5 OV, TAo 25 c C
17
21
25
31
ns
ns
from Data to Z,
tpdO
Propagation Delay to a Logical "0"
from Data to
Z,
tpdO
~
Data Select to Z
tpdl
tpdO
Vee
c
-
Data Select to Z
tpdl
tpdO
Note 1. ·'Absolute Maximum Ratings" are those values beyonu which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherWise specified min/max limits apply across the _55 C to +125°C temperature range for the DM9309
and across the oOe to 700 e range for the DM8309 All tYPlcals are given for Vee := 5 OV and T A == 25 D e
Note 3: Only one output at a time should be shorted
G
6-9
N
po
CW)
Series 9000
00
::E
Q
........
N
DM9312/DM8312 8-input multiplexer
po
CW)
en
::E
Q
general description
features
The DM9312/DM8312 IS an eight-input digital
multiplexer which provides in one package the
ability to select one bit of data from up to eight
sources. When the enable input is taken to a
logical "0", It Will enable the multiplexer to fu nction_
•
Senes 54/74 T2L and DTL compatible
•
•
Input clamping diodes
Selects one-of-elght data sources
•
•
Fan-out of 10
Fully buffered complementary outputs
logic and connection diagrams
Dual·ln-Lme and Flat Package
s,
I..
14
"
"
r-
r-
,
,
1
I,
I,
.
, ,
I,
TOP VIEW
truth table
E
S, 5,
So
10
I,
I,
I,
I.
Is I.
17
Z
Z
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
~
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H = High Voltage Level
L '" Low Voltage Level
6-10
x = Irrelevant
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
,
10
11
12
I,
,
I,
I'
GND
C
absolute maximum ratings (Note 1)
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
s:
operating conditions
Supply Voltage (VCCI
DM9312
DM8312
7V
55V
55V
-65"C to +150"C
300"C
MIN
MAX
UNITS
45
475
5.5
525
V
V
.......
-55
0
+125
70
,·C
s:
Temperature (T A)
DM9312
DM8312
CD
W
~
N
C
"c
00
W
~
N
electrica I characteristics
(Note 2)
PARAMETER
MIN
CONDITIONS
TYP
MAX
Vee =- Min
Logical "0" I nput Voltage
Vcc=Mtn
Logical "1" Output Voltage
V 'N (ll = 2V
Vee = Min, V'N(OI = 8V IOH
08
cc
-800 /1A
UNITS
V
2
Logical "1" Input Voltage
V
V
24
VouT=55V
250
I1A
Logical "1" Output Current
Vee'" Max,
Logical "0" Output Voltage
Vee::::;; Mm, V 1N (1) ~ 2V
V1N(o) = 8V, IOL = 16 rnA
Logical "1" Input Current
Vee = Max, V ,N = 24V
40
/1 A
Vee = Max, V ,N = 5 5V
1
rnA
-16
rnA
Vee
Logical I/O" Input Current
Output Short Circuit Current
VIN = OV
= Max, V IN
:::
4V
-30
Vee;:; Max
(Note 31
-27
Supply Current
Vee
=
Input Clamp Voltage
Vee
= Mm, liN:::: -12 mA
Propagation Delay to a Logical "0"
from Data to Z,
"a"
Propagation Delay to a Logical "1"
from Data to Z, tpdl
Propagation Delay to a Logical "1"
Z,
33
Max
V
-85
mA
44
rnA
-15
V
Vee = 50V, TA = 25"C
23
34
ns
25"C
9
14
ns
Vee= 5 OV, TA = 25 c C
19
28
ns
Vee = 5 OV, T A = 25"C
15
23
ns
Vee = 5 OV, T A = 25 Q C
29
25
43
37
ns
ns
Vee = 5 OV, TA = 25°C
20
18
30
27
ns
ns
Vce= 50V, TA = 25°C
28
25
42
37
ns
ns
Vee = 5 OV, T A = 25°C
17
18
25
27
ns
ns
tpdO
Propagation Delay to a LogICal
from Data to Z, t prlO
from Data to
04
tpdl
Vee = 50V, TA
C
Data Select to Z
tpdl
tpdO
Data Select to
a
Z
tpdl
tpdO
Enable to Z
tpdl
tpdO
Enable to Z
tpdl
tpdO
Note 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limIts The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2. Unless otherWise specified minimax limits apply across the _55°C to +125°C temperature range for the DM9312
and across the O°C to 70 e range for the DM8312 All typlcals are given for Vee'" 5 OV and T A'" 25°C
0
Note 3. Only one output at a time should be shorted
6-11
N
N
M
Series 9000
00
:E
Q
.......
N
N
M
DM9322/DM8322 quad 2-input multiplexer
en
:E
Q
general description
features
The DM9322/DM8322 consists of four 2-input
multiplexers with common input select logic and
common output disable circuitry. It allows two
groups of four bits each to be multiplexed to four
parallel outputs. When the Enable Input is at the
logical "0" level the outputs reflect information
on the selected Inputs. However, when a logical
"1" is applied, the outputs assume the logical "0"
level.
•
Typically IOns from data to output
•
Power dissipation 150 mW typ
•
Pin compatible with FSC9322 and SN54157/
SN74157
•
Diode clamped inputs
•
Available In either cavity or molded dual-inline package
The DM9322/DM8322 is pin compatible and functIOnally compatible with the FSC9322 and the
SN54157/SN74157. Features of the deVice are:
logic and connection diagram
Dual-In-Llne and Flat Package
Vee
Ze
10D
lOB
110
ZD
z.
GNU
TUPVIEW
truth table
6-12
ENABLE
SELECT
E
S
10
I,
ZX
1
X
0
0
0
0
1
X
X
X
0
X
0
0
0
1
1
x
0
1
X
1
1
0
0
INPUT
OUTPUT
o
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM9322
DM8322
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
s:
(Note 1)
(D
W
N
N
7V
5.5V
5.5V
_55°C to 125°C
oOe to 70°C
_55°C to 150°C
300°C
......
o
s:
CO
W
N
N
electrical characteristics
(Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
Input Voltage
DM9322
DM8322
Vee = 4 5V
Vee = 4 75V
Logical "0" Input Voltage
DM9322
DM8322
Vee=45V
V ee -475V
Logical "1" Output Voltage
DM9322
DM8322
Vee = 4.5V
Vee - 4 75V
IOUT=-12mAV'N=2V
Logical "0" Output Voltage
DM9322
DM8322
Vee = 4 5V
V ee -475V
IOUT= 124mA V 'N=08V
lOUT = 14 1 mA
04
045
V
DM9322
DM8322
Vee=55V
V ee -525V
lOUT""
16 mA
lOUT = 16 mA
04
045
V
DM9322
DM8322
Vee=55V
Vee- 525V
V'N = 45V
60
/lA
DM9322
DM8322
Vee=55V
Vee - 5 25V
V'N = 5 5V
1
mA
DM9322
DM8322
Vee=55V
Vee- 525V
V'N = 04V
Logical
"1"
Logical" 1" I nput Current
Logical "0" Input Current
Output Short Circuit Current
INote 3}
DM9322
DM8322
Vee=45V
Vee - 4 75V
DM9322
DM8322
Vee = 5.5V
Vee - 5.25V
20
V
08
24
V
V'N = 08V
-1
-35
V
-16
mA
-1 24
-141
mA
mA
-46
-80
mA
mA
Supply Current ~ (each deVice)
DM9322
DM8322
Vee = 5V
All Inputs = 45V
30
43
Input Clamp Voltage
DM9322
DM8322
Vee = 5V
TA = 25°C
I'N=-12mA
-10
-15
V
Vee = 5 OV
T A = 25°C
6
11
16
ns
Vee = 5 OV
T A =25"C
8
17
27
ns
Vee = 5 OV
TA = 25°C
4
8
15
ns
\Icc"" 5 OV
TA = 25°C
5
15
25
ns
Enable to Output,tpdo
Vee = 5V
TA = 25°C
7
16
23
ns
Enable to Output,
Vee = 5V
T;>. = 25"C
6
14.
20
ns
Propagation Delay to a Logical
"0" from Data to Output,
tpdO
Propagation Delay to a Logical
"0" from Select to ZA,
tpdO
Propagation Delay to a Logical
"1" from Data to Output,
tpdl
Propagation Delay to a Logical
"1" from Select to ZA,
tpdl
tpd1
a
Note 1· "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits The table of "Electrical Characteristics" prOVides conditions
for actual deVice operattOn
Note 2: Unless otherWise speCified minimax limits apply across the _55°C to +125°C temperature
range for the DM9322 and across the oDe to 70°C range for the DM8322 All tYPlcals are given for
V CC = 50V and T A = 25° C
Note 3: Only one output at a time should be shorted
6-13
....o
CD
Series 9000
CIO
:E
c
.......
....
o
DM9601/DM8601 retriggerable monostable multivibrator
CD
0)
:E
c
general description
features
The DM9601/DM8601 IS both pln-for-pln and
spec-for-spec Interchangeable with the 9601 oneshot. Pulse widths range from 50 ns upward
depending upon the values of the external R&C
used. The retriggerable feature allows for output
pulse widths to be extended beyond the normal
range attainable with just a resistor and capacitor.
• Input Clamping Diodes
• Complementary DC Level Sensitive Inputs
• FleXibility of Operation-Optional Retrlgger·
lng/Lockout Capability
• DTUTTL Compatible Logic Levels
• High Speed OperatIOn-Input Repetition
Rate> 1,0 MHz
• Output Pulse Width Range 50 ns to 00
• Leading or Trailing Edge Triggering
• Complementary Outputs
schematic and connection diagrams
(141
L
Dual-In-Llne and Flat Package
I
ex
R
I
t'';'~---II---,
v"
A,
"
"
TOPVIEW
6-14
Nt
c
s:
DM9601
absolute maximum ratings
(D
0)
Supply Voltage to Ground
Input Voltage
Voltage Applied to Outputs
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
o- '
-0.5V to +8.0V
-0.5V to +5.5V
-0.5V to +Vcc
-65°e to +150 o e
-55°e to +125°e
300De
........
C
s:
CO
0)
o-'
electrical characteristics
TABLE I
limits
Svmbol
_55 c C
Parameter
Mon
VOH
Output High Voltage
Max.
+25°C
Mon
Typ.
24
24
+125°C
Max
33
Mon
Umts
Conditions
(Note l'
Max
24
V
Vee = 4 5V
IOH '" -0 72 rnA
(Note 2)
Vue
04
Output Low Voltage
02
04
04
V
Vee =45V
i oL =10mA
(Note 2)
V'H
Input High Voltage
V"
Input Low Voltage
20
17
14
085
090
085
V
Vee
=
4 5V
V
Vee
=
5 5V
(Note 3)
Ie
-16
Input Load Current
-1 1
-1 6
-1 6
mA
Vee
5 5V
=
V F =04V
IR
Input Leakage Current
15
60
60
"A
Vee'" 5 5V
V R = 4 5V
Isc
-10
Short Circuit Current
-40
Vee =50V
V OUT
leo
QUiescent Power
t pd <
Negative Trigger Input
Supply Dram
25
25
to True Output
25
25
40
Negative Trigger Input
to Complement Output
25
40
OV (Note 2)
mA
Vee =55V
ns
Vee =50V
Rx
t pd _
'"
ns
=
ex -'"
5 0 KIl
0
CL =15pF
tpwlmonJ
Minimum True Output
lHpw
Pulse Width VariatIOn
Pulse Width
45
308
342
65
ns
376
"s
Vee =50V
Rx
Cstr"y
Rx
Maximum Allowable
WIring Capacitance
(Pin 13)
External Timing Resistor
50
50
25
50
50
25
50
50
pF
25
kr!
=
10 KIl. C x
=
1.000 pF
Pm 13 to GND
Note 1: Unless otherwise specified, RX 10 Kn between Pin 13 and Vee on all tests
Note 2: Ground Pin 11 for VOL test on Pin 6, VOH test on Pin 8 and ISC test on Pin 8.
=;
Open Pin 11 for VOL test on Pin 8, VOH test on Pm 6 and ISC test on Pm 6
Note 3: Pulse test to determine VIH and VIL (Min PW
=;
40 ns)
6-15
....
o
OM8601
absolute maximum ratings
CD
CO
::?!
Supply Voltage to Ground
Input Voltage
Voltage Applied to Outputs
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
c
"'....
o
CD
en
::?!
-0.5V to +8.0V
-0.5V to +5.5V
-0.5V to +V cc
-65°C to +150°C
oDe to +75°C
300°C
c
electrical characteristics
TABLE II
Limits
Symbol
aCc
Parameter
Mm.
VOH
Output High Voltage
+2S"C
Max.
24
Mm.
24
Typ.
+75°C
Max.
34
Units
Conditions
(Note l'
Max.
Mm.
24
V
Vee =475V
IOH
:=
-096 mA
(Note 2)
VOL
045
Output low Voltage
02
045
045
V
Vee'" 4 75V
IOL '" 128 rnA
(Note 2)
V'H
Input High Voltage
V"
Input Low Voltage
Ie
Input Load Current
19
18
16
085
085
085
V
Vee =475V
V
Vee =525V
(Note 3)
-16
-10
-1 6
-16
mA
Vee
=
525V
V,=045V
IR
15
Input Leakage Current
60
60
~A
Vee =525V
V R = 4 5V
Ise
Short CirCUit Current
1'0
QUiescent Power
-10
-40
mA
Vcc=50V
V OUT = OV (Note 2)
25
Supply Drain
tpd t
25
Negative Trigger Input
to True Output
25
25
40
mA
ns
Vee'" 5 25V
GNDPlnsl &2
Vee "'SOV
A x =50KIl
tpd ~
Negative Trigger Input
to Complement Output
25
40
ns
ex
=0
c L = 15 pF
lpwlmm)
Minimum True Output
j t pw
Pulse Width Variation
estray
Maximum Allowable
WIring Capacitance
Rx
External Tlmmg Resistor
45
Pulse Width
308
342
65
ns
3.76
~s
Vee =50V
Ax = 10 KIl. C x = 1.000 pF
(P,n 13)
50
50
50
50
50
50
50
50
pF
50
kll
Note 1: Unless otherWise specified, RX = 10 Kr2 between Pin 13 and Vee on all tests
Note 2: Ground Pin 11 for VOL test on Pin 6, VOH test on Pm 8 and Ise test on Pin 8
Open Pin 11 for VOL test on Pm 8, VOH test on Pin 6 and Ise test on Pin 6
Note 3: Pulse test to determine VIH and VI L (Min PW = 40 ns)
6-16
Pin 13 to GND
c
s:
CD
en
o....
operating rules
.......
C
tance and noise pickup. If remote trimming IS
required, Rx may be split up such that at least
Rx 1M IN) must be as close as possible to the
circuit and the remote portion of the trimming
resistor R
RXIMAX)-Rx
1. An external resistor R x and an external capacitor C x are required for operation. The value of
Rx can vary between the limits shown on
tables I and II. The value of C X IS optional and
may be adjusted to achieve the required output
pulse width.
2. Output pulse width tpw may be calculated as
follows:
tpw
~ 0.32 RxCx [1 + ~':1 (for Cx 2' 10
Rx in KSl, C x
In
3
s:CO
en
o
....
<
4. Set-up time(t11 for Input trigger pulse >40 ns.
(See Figure 11
Release time(t 2 1 for Input trigger pulse >40 ns.
(See Figure 21
5 Retrlgger pulse width (see Figure 31 IS calculated
as follows'
pFI
pF and tpw In ns
For ex < 10 3 pF, see curve.
3. Rx and C x must be kept as close as possible to
the CirCUit in order to minimize stray capacl-
'.C):-'"
Figure 2
Figure 1
INPUT
0. OUTPUT
~
:
L
Figure 3
6-17
C/)
CD
Series 10,000
CD
1/1
~
o
o
o
o
REFERENCE
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below! Refer to the alpha·numerlcal Index at the front of thiS
catalog for complete device title and function. Packages (pages I thru VI) are In the back of the catalog.
PACKAGES
DATA SHEETS
Devices
Pg
DM10l0l
DM10102
DM10105
DM10106
DM10l07
DM10l09
DM10l10
DM10lll
DM10112
DM10115
DM10116
DM10117
DM10118
DM10119
DM10121
DM10124
7·1
7·3
7·5
Molded DIP (N)
Fig.
n
7·9
7·11
7·13
7·15
7·17
7·19
721
7·23
7·25
7·27
7·29
731
Pg.
Cavity DIP (D)(J)
Fig.
Pg
Type
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Fig.
Pg
Type
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
Fig
Pg.
Fig.
Pg.
41
41
41
41
41
41
1118
11·18
11·18
1118
11·18
11·18
10
10
10
10
10
10
11·2
11·2
11·2
11·2
112
11·2
*Order Numbers use DeVice No suffixed with package letter, I.e. OM10101J.
7-i
o
...o~
Series 10,000
...o
...
DM10101(MC10101) quad OR/NOR gate with strobe
general description
The DM 101 01 quad gate IS a low power, high
speed, standard ECl logic device. High Z input
pulldowns allow high DC and AC fanout and
eliminate the need to tie unused Inputs to an
external supply. The open emitter outputs allow
maximum flexibility In the selection of termination techniques and minimize the power requirements when driving transmission lines. Wire"OR"ing of outputs IS available with the open
emitter outputs.
applications
The DM10101 is useful In control, bUSSing and
communications In high speed central processors,
high speed peripherals, digital communications
systems, minicomputers and instrumentation. This
deVice is commonly used for control and bUSSing
data by using the wire OR capability of the baSIC
ECl gate and/or the common enable input. The
complementary outputs on all gates makes this
part useful as a quad line driver for twisted pair
lines thus redUCing package count.
features
3.5 ns
•
Slow rise and fall times
•
High speed
2.0 ns
•
low power
25 mW/gate
•
High fanout
•
50£1 line driving capability
50 mA/output
•
High Z input pulldowns
•
Open emitter follower outputs
•
Wire OR capability
•
Complementary output for added versatility
•
Standard end power pins for conventional layout
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
Dual~1 n~Line
Package
TOP VIEW
8
V"
7-1
....
o....
o....
:E
absolute maximum ratings
Q
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
_30° C to +85° C
-55°C to +125°C
300°C
electrical characteristics
@TEST
VOL
VtHA
VILA
MIN
MIN
MAX
-089
-1 89
-1 205
_1 50
-52
+25°C
-081
-185
-1 105
V
-070
-1825
-1035
-'475
-144
-52
+85"C
-52
v
_30°C
CHARACTERISTIC
SYMBOL
TEST
Power Supply Drain Current
Input Current
logic "1" Output Voltage
logic "0" Output Voltage
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
DM10101
PIN
UNDER
_30°C
MIN
I,
8
-
-
l.nH
13
-
-
l'flH
12
-
I,nl
12,13
V OH
Yo,
VOHA
VOLA
MIN
-
TYP
LISTED BELOW
+8SoC
UNITS
MAX
MIN
MAX
20
26
-
-
-
265
VILA
MIN
MIN
MAX
-
-
8
1,16
-
8
1,16
-
8
1, 16
-
8
1,16
-
8
1,16
-
8
1,16
mAde
-
.uAde
13
_.
-
550
-
-
pAdc
12
-
-
-
-
}.JAde
-
-096
-
-081
-070
Vde
12
-
-081
-089
-070
Vde
13
-081
-089
-070
Vdc
-081
-089
-070
Vde
-165
-1825 -1615
Vde
-
-165
-1825 -1615
Vde
-
-165
-1825 -1615
Vdo
12
-165
9
-106
-089
-096
15
-106
-089
-096
15
-106
-089
-096
9
-189
-1675
-185
9
-189
-1675
-185
15
-189
-1675
-185
15
-1 89
-1675
9
-1 08
9
-108
15
-108
-
-098
15
-108
-
-098
9
-
-1655
9
15
-
15
-
-1655
-
-
-185
-089
-
-
12
13
-
8
1, 16
-
-
8
1, 16
-
-
8
1,16
-
-
8
1, 16
-
Vde
13
-
-091
Vdo
-
-
12
-098
-
-091
Vde
-
-
13
Vde
-
-
-
Vde
-
-
-091
-
-
-091
-
-
-163
-
-1595
Vdo
-
-1655
-
-
-163
-
-1595
Vde
-
-1655
-
-163
-
-1595
Vde
_.
-
12
-1 595
Vde
-
-
13
-163
RlseTlme
(20 to 80%)
Fall Time
(20 to 80%
15
t 12 _ 15 +
15
-
10
20
29
-
10
20
29
10
20
29
-
10
20
29
11
20
33
-
11
20
33
-
11
20
33
-
-
11
20
33
-
-
112+9+
9
-
t 1Z _ 9
9
-
-
t 15 +
15
-
-
0,.
9
115 -
15
0,-
9
-
-
-
-
-
-
e,
-
e,
-
e;
-
e;
-
"e,
-
8
1, 16
8
1,16
1,16
12
8
13
8
1, 16
-
12
8
1,16
-
13
Pulse
Ie
112+15-
1, 16
-
-1825 -1615
-
8
GND
13
-
-
VEE
12
SWitching Times
1500hm load)
Propagation Delay
-
12,13
-098
-
(Vee)
V 1HA
MAX
05
-089
V
VOL
-
-106
UNITS
VOH
-
9
VEE
TEST VOL TAGE APPLIED TO PINS
TEST LIMITS
+2SoC
MAX
TEST VOL rAGE VALUES
VOH
MAX
TEMP
Pulse
0",
8
1, 16
8
1,16
8
1, 16
-32V
+20V
12
15
8
1,16
-
12
15
8
1,16
12
9
8
1,16
12
9
8
1,16
-
12
15
8
1,16
1, 16
-
12
9
8
e,
-
-
12
15
8
1,16
e;
-
-
8
1,16
12
9
Note: Each DM10,OOO series Circuit has been designed to meet the DC specifications shown In the test table, after thermal
eqUilibrium has been established. The Circuit IS In a test socket or mounted on a printed circuit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm resistor to -2 a volts. Test procedures are shown for only one gate. The other gates are tested In the same manner
7-2
c
....
s:
Series 10,000
o
o
N
DM10102(MC10102) quad gate
general description
The DM10l02 quad gate IS a low power, "high
speed, standard ECl logic device. High Z Input
pulldowns allow high DC and AC fanout and
eliminate the need to tie unused Inputs to an
external supply. The open emitter outputs allow
maximum flexibility in the selection of termination techniques and minimize the power requirements when driving transmission lines. Wtre Ortng
of outputs is available with the open emitter
outputs.
applications
The DM10l02 is very useful In control, bussing,
and communications in high speed central processors, high speed pertpherals, digital communications systems, minicomputers and Instrumentation
This device IS commonly used for control and
bussing data by uSing the wire OR capability of
the basIc ECl gate. The additional non-Inverting
output on one gate adds to the fleXibility of thiS
part.
features
35 ns
•
Slow rise and fall times
•
High speed
2.0 ns
•
low power
25 mW/gate
•
High fanout
50 mA/output
•
50Q line drtvlng capability
•
High Z Input pu IIdowns
•
Open emitter follower outputs
•
Wire OR capability
•
Complementary output for added versatility
•
Standard end power pinS for conventional layout
•
Separate Vee pins maintain high speed and
minimIZe crosstalk and nOise generation
schematic and logic diagrams
VCC2
16
Vee1
Dual-In-Line Package
16
15
+---+--013
TOPVIEW
11
12
7-3
N
o.~
absolute maximum ratings
:E
C
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
oto VEE
50mA
_30° C to +85° C
-55°C to +125°C
300°C
electrica I characteristics
@
TEST h;:::-,v.T:-,E'lSrT~Vf':0=:LT,-,AfGo.;EfV:,:A:=L,U=:ES'---1
TEMP
~~HX
~II~
~~~
~~~
Vee
UNITS
_30°C
,-089
-189
-1205
-150
-52
V
+25°C
+85"C
-081
-070
-185
-1825
-1105
-1035
-1475
-144
-52
-52
V
V
TEST VOLTAGE APPLIED TO PINS
LISTED BELOW
DM10102 TEST LIMITS
PIN
CHARACTERI~TlC
UNITS
(Vee!
r-:-V'-'H-'--:V"-Il--:--:V-'H-'-A-'-:V"-Il-A-'---; GND
MAX
Power Supply Drain Current
20
Input Current
12
12
Logic ''1'' Output Voltage
15
15
Logic "0" Output Voltage
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
26
mAde
265
.uAde
05
RlseTlme
(20 to 80%)
Fall Time
(20 to 80%
MIN
MAX
Vee
1,16
12
1,16
12
,uAde
1,16
-106
-089
-096
-0 81
-0 89
-070
Vde
12
-1 06
~089
-096
-081
-089
-070
Vde
13
-106
-089
-096
-081
-089
-070
Vdc
12
1,16
-070
Vdc
13
1,16
1,16
1,16
1,16
-106
-089
-096
-08t
-089
-189
-1675
-185
-165
-1825 -1615
Vde
12
13
-189
-1675
-185
-165
-1825 -1615
Vde
15
-189
-1675
-185
-165
-1825 -1615
Vde
12
15
-189
-1675
-185
-165
13
1,16
1,16
-1825 -1615
Vde
-098
-091
Vdc
12
-108
-098
-091
Vdc
13
15
-'08
-098
-091
Vdc
12
1,16
15
-108
-098
-091
Vdc
13
1,16
V OHA
-108
1,16
1,16
1,16
-1655
-163
-1595
Vde
12
1,16
-1655
-163
-'595
Vde
13
1,16
15
-1655
-, 63
-1595
Vde
12
15
-1655
-163
-, 595
Vde
13
VOLA
SWltchmg Times
(50·ohm load)
Propagation Delay
MIN
1,16
1,16
Pulse
Pulse
In
0",
-32V
t 12 +15_
15
10
20
29
12
15
1,16
t12-15+
15
10
20
29
12
15
1,16
t12+9+
10
20
29
12
1'2_9_
10
20
29
12
11
20
33
12
11
20
33
12
11
20
33
12
11
20
33
12
t,5+
15
t"
15
1,16
1,16
15
1,16
1,16
15
Note: Each DM10,000 series CirCUit has been designed to meet the DC specifications shown In the test table, after thermal
eqUIlibrium has been established The circuit IS In a ~est socket or mounted on a printed cirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested In the same manner.
7·4
+20V
1,16
1,16
c
...os:
...
o
Series 10,000
U'1
DM10105(MC10105) triple 2-3-2 OR/NOR gate
features
general description
The DM10105 triple gate IS a low power, high
speed, ECl logic device with the standard ECl
high Z Inputs and open emitter outputs. This
offers the system deSigner maximum flexibility
in layout and design. The open emitter output
allows a maximum number of gates to be wire
ORed. This device is useful in high speed digital
commUnications systems, central processors, penpheral controllers, minicomputers, instrumentation, and testing systems. The DM 101 05 IS a
general purpose gate which generates both true
and complement of a control signal and can be
used to drive twisted pair lines.
•
Slow rise and fall times
•
High speed
•
low power
•
High fanout
3.5 ns
tpd
= 2.0 ns
50 mA/output
•
Open emitter follower outputs for Wire OR
•
Complementary outputs simultaneous functions
•
Standard end power pins conventional layout
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
16
"
13
Dual-In-Line Package
TOPVIEW
v"
10
11
7-5
In
...
...
o
o
:!:
absolute maximum ratings
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
c
o to VEE
50mA
-30 C to +85°C
-55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
(Volts)
@TEST
TEMP
V,H
MAX
VIL
MIN
V,HA
MIN
V,LA
MAX
VEE
_30°C
-0890
-1890
-1205
-1500
-52
+25°C
-0,810
-1850
-1 105
-1475
-52
-1035
-1440
-52
+85"C
-0700
DM10105 TEST LIMITS
PIN
CHARACTERISTIC
Power Supply Dram Current
Input Current
SYMBOL
UNDER
TEST
PINS LISTED VELOW
+2SOC
_30°C
MAX
Logic '0" Output Voltage
MIN
I,
TVP
15
Voc
Logic "1 'Threshold Voltage
V OHA
Logic "0' Threshold Voltage
VOI.- A
(2010 80%1
Fall Time
(2010 80%1
MAX
21
V,H
MAX
VIL
MIN
V,HA
MIN
V,LA
MAX
VEE
GNo
mAde
1,16
pAdc
1,16
pAdc
1,16
-0890
-0960
-0810
-0890
-0700
Vdo
1,16
-1060
-0890
-0960
-0810
-0890
-0700
Vdo
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vdo
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vdo
1,16
Vdo
1,16
Vdo
1,16
-1080
- 910
-0980
-0980
- 910
-1655
-1630
-1595
Vdo
-1655
-1630
-1595
Vdo
1,16
1,16
Pulse
10
Pulse
0",
-32V
+20V
14~3
20
1,16
14_3+
20
1,16
14+2+
20
1,16
t"
20
1,16
t"
20
1,16
t"
20
1,16
t,
20
1,16
t,
20
1,16
Note: Each DM10,OOO senes circuit has been deSigned to meet the DC specifications shown In the test table, after thermal
eqUilibrium has been established. The Circuit IS 10 a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 Imear fpm IS maintained. Outputs are term mated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates ~re tested In the same manner.
7-6
(Vee)
-1060
SWitching Times
150 ohm load I
Rise Time
MIN
05
-1080
Propagation DeidY
MAX
265
l,nH
V OH
+8S"C
UNITS
MIN
l,nL
logic ',"Output Voltage
-1825
TeST VOLTAGE APPLIED TO
c
~
....
Series 10,000
o....
o
en
DM10106(MC10106) triple 4-3-3-input NOR gate
general description
The DM10l06 triple gate IS a low power, high
speed, ECl logic device with the standard ECl
high Z inputs and open emitter outputs. This offers
the system designer maximum flexibility In layout
and design. The open em itter output allows a
maximum number of gates to be wire ORed. This
deVice is useful In high speed digital communications systems, central processors, peripheral controllers, minicomputers, instrumentation, and testing systems. Busing data with wire OR IS a useful function of the DM10l06 and It is also useful
as a general purpose gate.
features
•
Slow rise and fall times
•
High speed
•
low power
•
High fanout
3.5 ns
tpd
z
2.0 ns
50 mA/output
•
Open emitter follower outputs for wire OR
•
Standard end power pins conventional layout
•
Separate Vcc pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
Dual·1 n-line Package
"
TOPVIEW
7-7
absolute maximum ratings
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
o to VEE
50mA
-30 C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
DM10106
PIN
CHARACTERISTIC
SYMBOL
-30°C
UNDER
TEST
MIN
l,nH
4
-
-
-
I'''L
4
-
-
05
VO "
Vo ,
3
-1060
-0890
-0960
3
-1890
-1675
-1850
Loglc"t 'Threshold Voltage
V OHA
3
-1080
-
-0980
Logic "0 'Threshold Voltage
VOLA
3
-
-1655
-
Logic "1 'Output Voltage
LogIc "0' Output Voltage
RIse Time (20 to 80%)
TYP
MAX
VEE
-1890
-1205
-1500
-52
+25"C
-0810
-1850
-1 105
-1475
-52
+85"C
-0700
-1825
-1035
-1440
-52
TEST VOLTAGE APPLIED TO
PINS LISTED BelOW
+85"C
MAX
15
21
-
265
Fall Time (20 to 80%)
14+3_
3
-
-
-
14 _3<
3
-
-
-
20
20
3
-
-
-
20
20
t,.
t,
3
VILA
MIN
-0890
MIN
MAX
V,"
V"
VIHA
VILA
MAX
MIN
MIN
MAX
mAde
-
-
,uAde
-
,uAde
-
-
-0810
-0890
-0700
Vde
-1650
-1825
-1615
Vde
-
-0910
-
Vde
-1630
--
-1595
Vde
4
4
-
-
-
-
-
4
-
4
-
-
SWltchmgTlmes
(50 ohm load)
Propagation Delay
VIHA
-30"e
TEST LIMITS
+26"C
MAX
8
Input Current
V"
MIN
UNITS
MIN
I,
Power Supply Dram Current
(Volts)
v,"
MAX
-
-
-
-
""
""
""
""
-
-
-
(Vee)
GND
8
1,16
-
8
1,16
-
4
4
VEE
-
Pulse
Pulse
'"
0"
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-32V
+20V
3
8
1,16
4
3
8
1,16
4
3
8
1,16
4
3
8
1,16
4
Note: Each DM10,OOO senes circuit has been designed to meet the DC specificatIOns shown In the test table, after thermal
eqUlllbnum has been established. The Circuit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested In the same manner.
7-8
c
...
3:
o
o
...
Series 10,000
"-J
DM10107(MC10107) triple EXCLUSIVE-OR/NOR gate
general description
features
The DM10l07 triple gate IS a low power, high
speed, ECl logic device with the standard ECl
high Z Inputs and open emitter outputs. This
offers the system designer maximum flexibility In
layout and design. The open em itter output allows
a maximum number of gates to be wired ORed ThiS
device is useful in high speed digital communications systems, central processors, peripheral controllers, minicomputers, instrumentation, and testIng systems. The DM10l07 provides the Exclusive
OR and the complement function simultaneously.
This device can selectively invert control Signals,
and can be used to bUild special purpose adders or
counters.
•
Slow rise and fall times
•
High speed
•
low power
•
High fanout
•
Open emitter follower outputs for wire OR
•
Standard end power pins conventional layout
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
3.5 ns
tpd
=
2.0 ns
50 mA/output
schematic and logic diagrams
Dual-In-Line Package
TOP VIEW
7-9
o"'...."
S2
absolute maximum ratings
:E
C
-8V
Supply Voltage
I nput Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30 C to +85°C
_55°C to + 125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
(Volts)
TEMP
CHARACTER ISTle
SYMBOL
I,
Input Current
UNDER
TEST
Logic "0" Threshold Voltage
-1500
-52
+2SOC
-0810
-1850
-1105
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
355
pAdc
5,7,15
265
pAdc
SWitching Times (50n Load)
Rise Time
-1205
I-M-IN--.:;30r-°C=-M-AX--1r-M-IN...;+.;25:..0C=-M-A-X+-M-'N"';+-'i85r°=-~-A-x-l UNITS
VIH MAX
VIL MIN
V1HA MIN
VEE
1,16
1,16
~Adc
1,16
-0890
-0960
-0810
-0890
-0700
Vdc
4,5
-1 060
-0890
-0960
-0810
-0890
-0700
Vdc
1,16
-1060
-0890
-0960
-0810
-0890
-0700
Vdc
1,16
-1060
-0890
-0960
-0810
-0890
-0700
Vdc
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vdc
1,16
-1890
-1675
-1850
-1650
-1825
"·1615
Vdc
-1890
-1675
-1850
-1650
-1825
-1615
Vdc
-1890
-1675
-1850
-1650
-1825
-1615
Vdc
4,5
1,16
1,16
4,5
1,16
4,5
1,16
1,16
-1080
-0980
-0910
Vdo
-1080
-09S0
-0910
Vdo
-1080
--09S0
-0910
Vdo
1,16
-1080
-0980
-0910
Vdo
1,16
TYP
-1655
-1630
-1595
Vdc
-1655
-1630
-1595
Vdc
-1655
-1630
-1595
Vdc
-1655
-1630
-1595
Vdc
MAX
UNITS
MAX
TYP
MAX
TYP
4,5
4,5
1,16
1,16
1,16
1,16
4,5
1,16
4,5
Pulse In
Pulse Out
-32V
+20V
Inputs
20
5,7,15
Input
Corresponding
4,9 or 14
20
5,7,15
4,9,or
OR/NOR
1,16
to either
20
5,7,15
14
Outputs
1,16
Output
20
5,7,15
Inputs
28
4,9,14
Input
Corresponding
5,7 or 15
2B
4,9,14
5,7, or
OR/NOR
1,16
to either
28
4,9,14
15
Outputs
1,16
Ouput
2B
4,9,14
25
4,9,14
Any Input
Corresponding
t'
Fall Time
(20 to 80%)
1,16
1,16
1,16
1,16
(20 to 80%)
1,16
OR/NOR
25
4,9,14
Any Input
Outputs
IIlndlvtdually test each Input applYing V IH or V 1L to mput under test
II*Any Output
Note: Each DM10,OOO series CirCUit has been designed to meet the DC speCifications shown In the test table, after thermal
eqUilibrium has been established. The CirCUit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained, Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate The other gates are tested In the same manner
7-10
GND
1,16
All Inputs
-1060
VOLA
c-
-1890
4,9,14
VOHA
Propagation Delay
VEE
-0890
mAdc
Logic "0" Output Voltage
Threshold Voltage
VILA MAX
_30°C
28
Logic "1" Output Voltage
"1"
VIHA MIN
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
05
Logic
VIL MIN
DM10107 TEST LIMITS
PIN
Power Supply Drain Current
VIH MAX
1,16
c
s:
....
o
....
o
Series 10,000
CD
DM10l09 (MC10l09) dual 4-5-input OR/NOR gate
general description
features
Open emitter outputs, high Z inputs, high speed,
and low power are the outstanding characteristics
of the DM10109 dual gate. The high Z Inputs and
open emitter outputs allow a maximum fanout
with minimum power requirements. Slow rise and
fall times, characteristic of ECl 10,000 series
gates, allow conventional interconnect techniques.
The open emitter outputs allow a maximum num·
ber of outputs to be wire ORed and stili drive a
heavy fanout. I n addition, unused outputs may be
left open and do not waste power. This device is
designed for use In high speed central processor,
peripheral controllers, minicomputers, digital com·
municatlons systems, and instrumentation and test·
ing systems.
•
Slow rise and fall times
•
High speed
•
low power
•
High fanout
•
Multiple open emitter follower outputs
•
MUltiple wire OR capability
•
Complementary outputs
•
Standard end power pins
•
Separate Vee pins maintain high speed and
minimize crosstalk and nOise generation
The DM 101 09 IS a general purpose gate that can
be used In control. The complementary outputs
are also useful In driving twisted pair lines when
it is necessary to send control signals or data a long
distance.
3.5 ns
tpd
= 2.0 ns
50 mA/output
schematic and connection diagrams
Dual-I n·L me Package
8
V"
7·11
0')
...
o
~
absolute maximum ratings
::E
C
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
_30° C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOL TAGE VALUES
@TEST
DM10109
PIN
CHARACTERISTIC
Power Supply Dram Current
Input Current
SYMBOL
UNDER
TEST
_30 o e
MIN
MAX
I,
High Output Voltage
Low Output Voltage
High Threshold Voltage
i,,,H
YO"
Yo,
V OHA
VOLA
+85°C
MAX
(20 to 80%)
Fall Time
(20to 80%)
MIN
MAX
-1890
-1205
-1500
-52
+2SoC
-0810
-1850
-1105
-1475
-52
+BSOC
-0700
-1825
-1035
-1440
-52
VIHA
MIN
VILA
VEE
UNITS
MAX
V,"
V"
V 1HA
VILA
MAX
MIN
MIN
MAX
VEE
1,16
265
pAdc
1,16
/JAde
1,16
1,16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,16
-1890
-1675
-1850
-1650
-1825
-1615
-1080
-0980
-0980
Vd,
1,16
-0910
Vd,
1,16
-0910
Vd,
1,16
1,16
-1655
-1630
-1595
Vd,
-1655
-1630
-1595
Vd,
1,16
'0
Pulse
Oct
-32V
+20V
, 0
20
29
1,16
, 0
20
29
1,16
t4+3
, 0
20
29
1,16
14.3,
, 0
20
29
1,16
20
33
1,16
20
33
1,16
20
33
1,16
20
33
1,16
t4+2+
t,.
t,.
t,_
t,_
"
"
"
"
Note: Each DM10,OOO series Circuit has'been designed to meet the DC specifications shown In the test table, after thermal
eqUlllbnum has been established. The circuit IS In a test socket or mounted on a printed CircUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner.
7-12
GNO
mAde
Pulse
t"
Rise Time
MIN
-0890
14
SWltchmg Times
(50 ohm load)
Propagation Delay
MAX
_30 o e
V"
TEST VOLTAGE APPLIED TO
PINS LISTED BelOW
05
-1080
Low Threshold Voltage
TYP
'0
l,nL
v,"
TEST LIMITS
+25°C
MIN
(Volts)
TEMP
Series 10,000
DM10110(MC10110) dual 3-input/3-output OR gate
general description
features
The DM 1011 0 is designed to drIVe up to three
transmission lines simultaneously. The multiple
outputs of this device also allow the w!re·"OR"ing
of several levels of gating for minimization of gate
and package count.
•
Slow rise and fall times
•
High speed
•
Low power
•
•
50 mA/output
High fanout
Multiple open emitter follower outputs
The ability to control three parallel lines from a
single pOint makes the DM10110 particularly use·
ful in clock distribution applications where min·
Imum clock skew IS desired.
•
Multiple wire OR capability
•
Standard end power pinS
•
Separate Vee pins maintain high speed and
minimize crosstalk and nOise generation
3.5 ns
tpd ~
2.0 ns
schematic and connection diagrams
VCC'l
16
Vee1
..........- - 0 1
Dual-In-Line Package
11
DIll
TOPVIEW
0-+------,
100-+----,
~+-+--O"
.....-'--"13
12
v"
7-13
......
o
...
o
:E
absolute maximum ratings
Q
-8V
Supply Voltage
I nput Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30°C to +85°C
-55°C to +125°C
300°C
TEST VOLTAGE VALUES,
electrical characteristics
o TEST
(Volts)
TEMP
PIN
CHARACTERISTIC
SYMBOL
UNDER
TEST
-lOoe
MAX
TY.
LogIc "1" Output Voltage
LogiC "0" Output Voltage
logIC "1" Threshold Voltage
logIC "0" Threshold Voltage
MAX
MIN
VOH
Yo,
VOHA
VILA
MIN
MAX
VEE
-JOoc
-0890
-1890
-1205
-1500
-52
+2SoC
-0810
-1850
-1105
-1475
-52
+85°C
-0700
-1825
-1035
-1440
-52
5,6,7
43.
5,6,7
PINS LISTED BELOW
UNITS
V'H
MAX
MAX
38
"
VIHA
TEST VOLTAGE APPLIED TO
+8S"C
+25°C
MIN
Power Supply Dram Current
I. H
I.,
V'L
MIN
DM10110 TEST LIMITS
MIN
Input Current
V'H
MAX
05
RIse TIme
(20 to 80%)
Fall TIme
(20 to 80%)
V'HA
MIN
VILA
MAX
V••
tVccl
GND
mAde
1.15,16
j.lAdc
1,15,16
.uAdc
1,15,16
1,15,16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
-1060
-0890
-01160
-0810
-0890
-0700
Vd,
1, IS, 16
1.15.16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,15.16
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,15,18
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,15,16
-lOBO
-0980
-0910
Vd,
1,15,16
-1080
-0980
-0910
Vd,
1,15,16
-1080
-0980
-0910
Vd,
1,15,16
VOLA
-1655
-1630
-1595
Vd,
1,15,16
-1655
-'630
-1595
Vd,
1,15,16
-1655
-1630
-1595
Vd,
1,15,16
SWItchIng TImes
(50 ohm load)
PropagatIon Delay
V'L
MIN
Pulse
'n
Pulse
Out
-32V
+20V
t5_2'
14
24
35
1,15,16
t"
14
24
35
1,15,16
tS'3_
t4
24
3S
1,15,16
t53_
14
2.
35
1,15,16
t5"_
14
24
35
1,15,16
t6_'_
14
24
35
1,15,16
t,.
11
22
35
1,16,16
t,.
11
22
3.
1,15.16
"'.
11
22
3.
1,15,16
t,_
11
22
3.
l,lS,16
t,_
11
22
35
l,1S,16
t._
11
22
35
1, IS, 16
-lndlvrdu,lIy IItSI nch InPUI applYing V'H or VIL 10 pm ul'lder tltSt
Note: Each DM10,OOO senes CIrCUIt has been deSIgned to meet the DC specifIcations shown In the test table, after thermal
eqUIlibrium has been established. The CirCUIt IS In a test socket or mounted on ,8 printed Circuit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50 ohm resistor to -20 volts Test procedures are shown for only one gate. The other gate IS tested In the same manner.
M
7-14
c
s:
....
Series 10,000
........o
....
DM10111 (MC10111) dual 3-input/3-output NOR gate
general description
features
The DM10111 IS designed to drive up to three
transmission lines simultaneously. The multiple
outputs of thiS device also allow the wlre-"OR "ing
of several levels of gating for minimization of
gate and package count.
The ability to control three parallel lines from a
Single pOint makes the DM10111 particularly useful in clock distribution applications where minimum clock skew is desired.
3.5 ns
•
Slow rISe and fall times
•
High speed
•
Low power
•
•
50 mA/output
High fanout
Multiple open emitter follower outputs
tpd
= 2.0
ns
•
Multiple wire OR capability
•
Standard end power pins
•
Separate Vee pins maintain high speed and
minimize crosstalk and nOise generation
schematic and logic diagrams
VCC2
16
Dual-tn-Line Package
r-......- Q I 5
TOP VIEW
·....-++-<>14
13
12
7-15
absolute maximum ratings
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30°C to +85°C
_55°C to +125°C
300°C
electrical characteristics
reST VOLTAGE VALUES
@TEST
TEMP
DM10111
PIN
CHARACTERISTIC
SYMBOL
UNDER
TEST
-3a"e
MAX
rvp
-
-
38
-
-
435
05
-
I,
8
-
Input Current
l,nH
5,6,7
-
l'nL
5,6,7
-
logiC "'" Output Voltage
YO"
2
-1060
-0890
-0960
3
-1060
-0890
-0960
4
-1060
-0890
-0960
Power Supply Drain Current
logiC "0" Output Voltage
Vo c
LogiC "1" Threshold Voltage
LogiC "0" Threshold Voltage
VOHA
VOLA
MIN
MAX
V"
-30' C
-0890
-1890
-1 205
-1500
-52
- 2SoC
-0810
-1850
-1 105
-1475
-52
+85"C
-0700
-1825
-1 035
-1440
-52
-
MAX
MIN
MAX
-
-
.uAdc
-0810
-0890
-0700
Vdo
-0810
-0890
-0700
-0810
-0890
-
mAde
V"
VIHA
VILA
MIN
MIN
MAX
v"
-
-
-
-
8
I, 15, 16
-
-
8
1,15, 16
-
-
8
1,15,16
5
-
-
8
1,15, 16
Vdo
6
-
8
1,15, 16
-0700
Vdo
-
7
-
-
8
1,15,16
-
8
1, 15, 16
8
1.15,16
8
1, 15, 16
-1890
-1675
-1850
-1650
-1 825
-1615
Vdo
5
-
-1890
-1675
-1850
-1650
-1 825
-1615
Vdo
6
4
-1890
-1675
-1850
-1 650
-1825
-1615
Vdo
-
-0980
-
-0910
Vdo
-
-0 980
-
-0910
Vdo
-0980
-1080
-1080
4
-1080
-
2
-
-1655
-
-0910
-1630
-
-
t5+2_
-
-
7
8
1,15, 16
-
5
-
8
1, 15, 16
-1595
Vdo
-
-
6
-
8
1, 15, 16
-1595
Vdo
-
7
-
8
1,15, 16
-
-
14
24
35
14
2'
35
-
14
24
35
-
14
2'
35
Rise Time
-
14
2'
35
-
14
24
35
(20 to 80%)
Fait Time
(20 to 80%)
t52+
2
-
15<3·
3
-
t53+
3
-
15+4
164+
,
1"
2
4
-
-
22
35
3
--
11
t"
11
22
35
-
t"
t,
4
-
-
II
22
35
-
2
-
-
11
22
35
-
t,
3
-
t 1
22
35
-
-
t,
4
-
11
22
35
-
-
'Ind,v,dually lest each ,nput appiY"'9 V,nH
Note: Each
-
Or
Vonllo pon
under
1,15, 16
1, 15, 16
-
-1 655
-
8
8
Vdo
4
2
5
Vdc
SWitching Times
(50 ohm load)
Propagation Delay
6
-
-
-1630
-
-
-1595
-1 655
-1630
7
-
3
-
GNo
-
/.lAde
2
2
(Vee)
V,H
MAX
3
3
VILA
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
UNITS
+8S"C
MIN
V rHA
V,l
MIN
TEST LIMITS
+25"C
MIN
(Volts)
V,H
MAX
"
"
"
"
"
"
"
"
"
"
"c;
Pulse
Ie
Pulse
-
5
2
-
5
5
-
5
-
-
-
-
-
-
-
-
-
-
-32V
+2 OV
8
1,15, 16
2
8
1,15,16
3
8
1, 15, 16
3
8
1, 15, 16
5
4
8
1.15, 16
5
4
8
1,15,16
5
2
8
1,15, 16
5
3
8
1 15, 16
5
4
8
1, 15, 16
5
2
8
1, 15, 16
5
3
8
1, 15, 16
5
4
8
1,15, 16
0"
tl<$1
DM10,OOO series CIrcuit has been deSigned to meet the DC specifications shown In the test table, after thermal
eqUilibrium has been established. The circuit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than
500
linear fpm IS maintained
Outputs are terminated through a 50-ohm resIstor to
cedures are shown for only one gate The other gate IS tested In the same manner
7-16
-2.0
volts, Test pro-
o
s:
....
o....
....
N
Series 10,000
DM10112(MC10112) dual 3-input 1 OR/2 NOR gate
general description
features
The DM10112 IS a dual 3 Input 1 OR/2 NOR
gate. The DM 10112 IS useful for driving multiple transmission lines. The open emitter outputs allow the use of wire OR In data bus applications.
•
Slow rISe and fall times
•
High speed
•
Low power
•
•
50 mA/output
High fanout
Multiple open emitter follower outputs
The ability to drive multiple transmission lines
from a single gate make the DM 10112 particularly useful in clock distribution applications where
minimum clock skew IS desired. The DM10112 IS
also useful for memory chip select decoding.
3.5 ns
tpd ~
2.0 ns
•
Multiple wire OR capability
•
•
Standard end power pinS
Separate Vee pins maintain high speed and
minimize crosstalk and nOise generation
schematic and connection diagrams
Dual-In-Llne Package
l16
1,
13
14
---<
I"
11
"
6
7
.~
9
r---1
I'
Vee!
2
~
3
I'
,
I'
TOP VIEW
7-17
N
....o..:E
absolute maximum ratings
c
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
-8V
o to VEE
50mA
-30°C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
(Volts)
@TEST
TEMP
DM10112
PIN
CHARACTERISTIC
SYMBOL
_30 o e
UNDER
rEST
MIN
-
-
-
-
-
-
I,
8
Input Current
l,nH
5,6,7
l,nL
5,6,7
-
05
LogiC "1" Output Voltage
VOH
2
-1060
-0890
-0960
3
-1060
-0890
-0960
4
-1060
-0890
-0960
2
-1890
-1675
3
-1890
4
Power Supplv Dram Current
LogiC "0" Output Voltage
logiC "1" Threshold Voltage
logiC "0" Threshold Voltage
Va'
VOHA
VOLA
MIN
MAX
_30°C
-0890
-1890
-1 205
-1500
-52
+2SOC
-0810
-1850
-1105
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
PINS LISTED BELOW
+8SoC
UNITS
TYP
MAX
MIN
MAX
-
38
-
-
mAde
V"
VIHA
VILA
MIN
MIN
MAX
-
-
-
-
-
-
-
-
J.?l
13
12
11
10
8
V"
Dual-In-Llne Package
2 ~ (4 + 5) • (6 + 7 + 9)
3 = (4+ 5). (6+ 7 + 9)
TOPVIEW
7·23
absolute maximum ratings
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
-8V
o to VEE
50mA
-30°C to +85°C
-55°C to +125°C
300°C
electrical characteristics
rEST VOLTAGE VALUES
(Volts)
@rEsr
TEMP
V,H
V,L
MAX
MIN
MIN
MAX
VEE
-0890
-1890
-1205
-1500
-52
+2SoC
-OS10
-1850
-1105
-1475
-52
+8Soc
-0700
-1825
-1035
-1440
-52
_30°C
DM10117
SYMBOL
Power Supply Drain Current
Input Current
Logic "1" Output Voltage
Logtc "0" Output Voltage
Logic "'" Threshold Voltage
Logic "0" Threshold Voltage
TVP
-
-
20
26
-
9
-
2
-1060
-0780
-0960
3
-1060
-0780
-0960
2
-2000
-1675
3
-2000
2
4
Voe
VOHA
VOLA
+8SoC
MIN
l,nH
V OH
+2SoC
MAX
8
•
TEST VOLTAGE APPLIED TO
TEST LIMITS
MIN
I,
l,nL
-J,fc
UNDER
TEST
MIN
MAX
265
-
-
MAX
UNITS
V,H
V,L
V 1HA
VILA
MA~
MIN
MIN
MAX
VEE
-
-
-
-
8
1.16
-
-
-
8
1,16
-
-
mAde
.uAdc
4
-
-
-
355
-
-
-
05
-
•-
-
-
,/.lAde
05
,uAdc
-
-0700
-0890
-0590
Vdc
4, •
-0700
-0890
-0590
Vdc
-1650
-1920
-1615
Vdc
-
4,9
-1990
-
-
-
-1675
-1990
-
-1650
-1920
-1615
Vdc
4,.
-1080
-
-0980
-
--0910
-
Vdc
-lOBO
-
--0980
-
-0910
-
-
3
-
Vdc
2
-
-1655
-
-
-
-1595
Vdc
-1595
Vdc
-
4
3
-
-1655
-1630
-1630
,uAdc
-
4
•4, •
SWitching Times
(60n Load)
Propagation Delay
t4+2+
t 4_2_
.."
t4_3+
Rise Time
(20 to 80%)
Fall Time
(20to 80%)
I,.
t"
I,
1,-
3
-
3
-
2
-
-
3
-
-
-
2
2
2
3
V,LA
PINS LISTED BELOW
PIN
CHARACTERISTIC
VIHA
-
-
23
-
-
23
-
22
-
-
23
23
22
22
22
-
-
-
-
"'
"'
"'
"'
"'
"'
"'
"'
•
•
•
••
•
•
•
-
GND
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-
8
1.16
8
1,16
-
4, •
8
1,16
-
4, •
•
1.16
8
1,16
-32V
+20V
-
4,9
4, •
-
Pulse
Pulse
I,
Out
4
2
8
1,16
4
2
8
1,16
4
3
8
1,16
-
4
3
8
1,16
4
2
8
4
3
8
1,16
4
2
8
1,16
-
4
3
8
1,16
-
Note: Each DM10,OOO series CirCUit has been designed to meet the DC specifications shown 10 the test table, after thermal
eqUilibrium has been established. The Circuit IS 10 a test socket or mounted on a printed Circuit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner
7-24
{Veel
1,16
Series 10,000
DM10118(MC10118) dual 2-wide OR-AND gate
general description
The DM 10118 IS a basIc logic building block providing the OR-AND function, useful in data control and digital multiplexing applications.
•
50Q line driving capability
•
High Z input pulldowns - for lower power
dissipation
features
•
Open emitter follower outputs
•
Internal collector dot for maximum logic utility
and speed
•
•
Slow rise and fall times
4.0 ns
High speed
tpd ~ 2.5 ns for two levels of logic
•
Wire OR capability - for bus oriented systems
•
Low power
100 mW/package
•
•
High fanout
50 mA/output
Standard end power pinS - standard
requirements
layout
schematic and connection diagrams
Vee1
VCC2
16
115
()-<
~ .......
KK
)-
~
--M"
r - r--
~
12
13
r
~ ~~
14
'--
o-~
K
r-r:
C
rK
10
~
>-
~~
11
Dual-In-Line Package
TOP VIEW
7-25
...
...
::E
00
o
absolute maximum ratings
Q
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
o to VEE
50mA
-30°C to +85°C
_55° C to + 125°C
300°C
TEST VOLTAGE VALUES
electrical characteristics
jVolts)
@TEST
TEMP
V,"
MAX
MIN
MIN
MAX
VEE
-30"C
-0890
-1890
-1205
-1500
-52
+2S"C
-0810
-1850
-1150
-1475
-52
+85°C
-0700
-1825
-1035
-1440
-52
DM10118 TEST LIMITS
PIN
CHARACTERISTIC
Power Supply Drain Current
Input Current
SYMBOL
-30'C
UNDER
+25"C
MIN
MAX
MIN
TVP
MAX
I,
8
-
-
20
26
l,nH
6
-
-
-
265
7
7
-
-
05
9
l,nL
6
265
05
05
9
-
Logic "1" Output Voltage
VOH
2
-1060
-0890
-0960
Logic "0" Output Voltage
Vo ,
2
-2000
-1675
-1990
logic "'" Threshold Voltage
V OHA
2
-1080
-
-0980
logic "0" Threshold Voltage
VOLA
2
-
-1655
-
-
355
V'L
VIHA
VILA
MIN
MIN
MAX
VEE
-
-
-
8
1,16
pAdc
6
-
-
8
1,16
/JAde
7
-
-
8
1,16
-
8
1,16
-
3,9
8
1,16
Pulse
Pulse
In
0",
-32V
'2OY
1,16
-
-
p.Adc
9
-
-
J.lAdc
6
pAdc
-
-
pAdc
-OB10
-0890
-0700
Vd,
3,9
-
-1650
-1920
-1615
Vd,
-
3,9
-
-0910
Vd,
-1630
-
-
-
-1595
Vd,
7
9
SWItchmgTlmes
(50-ohm load)
Propagation Delay
t6+2_
2
I"
2
Rise Time (20 to 80%)
1,
2
FaJi Time (20 to 80%)
t
2
-
--
-
1•
23
3.
14
23
3.
15
25
40
15
25
40
-
3,9
GNO
8
1,16
8
1,16
8
1,16
8
1.16
8
1,16
8
1,16
-
n,
3
-
6
2
8
-
n,
3
6
2
8
-
n,
3
6
2
8
1,16
-
n,
3
-
6
2
8
1, 16
Note: Each DM10,OOO sertes Circuit has been deSigned to meet the DC specifications shown In the test table, after thermal
equIlibrium has been established. The CircUit IS In a test socket or mounted on a printed Circuit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner
7-26
(Vccl
V,"
MAX
mAde'
MAX
-
VILA
UNITS
MIN
-
-
VIHA
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
+85°C
TEST
V'L
1,16
c
...os::
...
, Series 10,000
CD
DM10119(MC10119) 4-wide 4-3-3-3-input ORlAND gate
general description
The DM10119 IS a 4-Wlde 4-3-3-3 Input OR/
AND gate with one Input from two gates common
to pin 10. Input pulldown resistors eliminate the
need to tie unused inputs to an external supply.
features
•
Slow rise and fall times
•
High speed
tpd ~ 2.5 ns for two levels of logic
•
Low power
100 mW/package
4.0 ns
•
50 mA/output
High fanout
• 50n line driving capability
•
High Z Input pUlidowns - for lower power
dissipation
•
Open em itter follower outputs
•
Internal collector dot for maximum logic utility
and speed
•
Wire OR capability - for bus oriented systems
•
Standard end power pinS - standard layout
requirements
schematic and logic diagrams
Dual·ln~Line
Package
TOPVIEW
7-27
......
en
o
...::?!
absolute maximum ratings
Q
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
o to VEE
50 mA
-30°C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOL TAGE VALUES
@TEST
TEMP
DM10119
CHARACTER ISTle
Power Supply
Dr~1n
Current
Input Current
SYMBOL
PIN
UNDER
TEST
-
-
20
-
-
-
05
9
-
05
-
10
-
-
05
-
-
9
10
l,nL
LogiC "1" Output Voltage
LogiC "0" Output Voltage
Logic' '" Threshold Voltage
LogiC '0" Threshold Voltage
7
Vo <
2
-1060
-0890
-0960
Vee
2
-2000
-1675
-1990
VOHA
2
~1
VOLA
2
080
-
+8SoC
Q
TYP
7
VII.. A
MIN
MIN
MAX
VEE
-30"C
-OS90
-1 890
-1 205
-1 500
-5,2
+ 2SOC
-0810
-1850
-1 105
-1 475
-52
+85°C
-0700
-1 825
-1035
-1440
-52
TEST VOL TAGS APPLIED TO
+25 C
MIN
l,nH
V1HP,
MAX
PINS LISTED BELOW
_30°C
MAX
8
V"
TEST LIMITS
MIN
I,
(Volts)
v,"
-1655
~O
980
-
-
-
MAX
UNITS
V,"
V"
VIHA
MAX
MIN
MIN
-
-
-
MIN
MAX
26
-
-
mAde
265
-
-
/JAde
7
265
-
9
-
10
-
-
!JAde
9
-
/-lAde
10
-
/JAde
-
JJ,Adc
-
-
-
pAdc
-
-0810
-0890
-0700
Vd,
3,10,15
-
-1 650
-1 920
-1615
Vd,
-0910
-
Vd,
-1,630
-
-1595
Vd,
-
3,10,15
-
355
-
-
7
t4+2+
2
-
t"
2
-
Rise Time (20 to 80%)
t,
2
-
Fall Time (20 to 80%)
t
2
-
-
-
14
23
34
14
23
34
15
25
40
15
25
40
-
-
-
VEE
8
1,16
8
1, 16
8
1, 16
8
1, 16
-
8
1,16
-
8
I, 16
8
1, 16
8
1,16
8
1, 16
3,10,15
8
1, 16
-
-
-
3,10,15
8
1, 16
Pulse
Pulse
'0
0"
-32V
+20V
0'
10, 13
-
4
2
8
1,16
0,"
10, 13
4
2
8
1,16
4
2
8
1,16
"
10,13
-
1
2
8
1,16
10,13
Note: Each DM10,OOO senes CIrCUIt has been deSigned to meet the DC specifications shown In the test table, after thermal
equilibrium has been established. The Circuit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm reSIstor to -2.0 volts Test procedures are shown for only one gate. The other Inputs are tested In the same manner.
7·28
(Vee)
GND
-
-
SWitching Times
(50 ohm load)
Propagation Delay
VILA
MAX
o
~
.-
Series 10,000
o.-
N
.-
DM10121(MC10121) OR·AND/OR·AND·INVERT gate
general description
The OM10121 is a basic logic building block
providing the simultaneous OR-ANO/OR-ANOINVERT function, useful in data control and digital mUltiplexing applications.
•
50n line driving capability
•
High Z input pulldowns - for lower power
dissipation
Open emitter follower outputs
I nternal collector dot and em Itter dot - for
maximum logic utility and speed
•
•
features
•
•
Slow rise and fall times
4.0 ns
High speed tpd ~ 2.5 ns for two levels of logic
•
Wire OR capability - for buss oriented systems
•
Complementary outputs -
•
•
Low power
High fanout
'" Standard end power pins requ irements
100 mW/pkg
50 mA/output
added versatility
standard iayout
schematic and connection diagrams
I
K
r-.t
-I-'
.
~
"
J
........ -.J
~;r
~
f
2: }-9
rl-'
0f"""1
rl-'
"
10
r< K~>
16
~
"
r-
~ K~ ~ )=ri
~~
I- l
f
r-o
"
"
>
8
TOPVIEW
7-29
absolute maximum ratings
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
o to VEE
50 mA
-30°C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
(Volts)
@TEST
TEMP
DM10121
PIN
CHARACTERISTIC
Power Supply Dram Current
Inpw Current
SYMBOL
UNDER
TEST
_30°C
MIN
MAX
MIN
I,
MAX
20
26
10
10
LogiC "l"Qutput Voltage
LogiC "0" Output Voltage
LogiC "1" Threshold Voltage
LogiC "0" Threshold Voltage
V OH
V oe
VOHA
VOLA
MIN
MAX
_30°C
-0890
-1890
-1205
-1500
-52
+2SoC
-0810
-1850
-1105
-1475
-52
+8S"C
-0700
-1825
-1035
-1440
-52
AlseTlme
(20 to 80%)
Fall Time
(20 to 80%)
VEE
PINS LISTED BElOW
MIN
UNITS
MAX
V,H
V"
VIHA
VILA
MAX
MIN
MIN
MAX
VEE
-
mAde
GND
1,16
/.lAde
1,16
265
pAdc
1,16
355
!lAde
05
/JAde
05
.uAdc
05
pAdc
1,16
10
1,16
1,16
10
1,16
-1060
-0780
-0960
-0700
-0890
-0590
Vde
-1060
-0780
-0960
-0700
-0890
-0590
Vde
4, la, 13
1,16
-2000
-1675
-1990
-1650
-1920
-1615
Vde
4, la, 13
1,16
-2000
-1675
-1990
-1650
-1920
-1615
Vde
1. 16
1,16
-1080
-0 980
-0910
Vde
-1080
-0980
-0910
Vde
4,10,13
1,16
4, la, 13
1,16
-1655
-1630
-1595
Vde
-1655
-1630
-1595
Vdo
1. 16
1,16
Pulse
Pulse
I,
0"
-32V
+20V
t':l+3
23
10,13
1,16
14_3+
23
10, 13
1,16
t4 +2+
23
10,13
1,16
t 4 _ 2_
23
10, 13
1,16
I"
25
10,13
1,16
t"
25
10,13
1,16
t,
25
10,13
1,16
I, ~
25
10,13
1,16
Note: Each DM10,OOO senes CIrcuit has been deSigned to meet the DC specificatIons shown to the test table, after thermal
equilibrium has been established. The Circuit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm reSistor to -2.0 volts Test procedures are shown for only one gate. The other inputs are tested In the same manner.
7·30
(Vee)
265
SWltchmg Times
(50·ol1m load)
Propagation Delay
VILA
TEST VOLTAGE APPLIED TO
+85°C
TVP
I"'H
l,nL
V"
MIN
TEST LIMITS
+25°C
V 1HA
V,H
MAX
Series 10,000
DM10124(MC10124) quad TTL to ECl
translator/differential line driver
general description
The DM10124 IS a quad TTL to ECL translator
which may also be used as a quad TTL to ECL
differential line driver. The input levels are com·
patlble with the series 7400, senes 74HOO and
Schottky series 74500.
• Complementary outputs with ECL 10,000 levels
• High output capacity, drives 8 50n lines
• TTL compatible inputs, input strobe
• Four translators per package
The output logic levels are ECL 10,000 compatible
over the recommended operati ng temperature
range. Complementary emitter follower outputs
provide for Inverting, non·inverting or differential
line driving applications. A common TTL strobe
Input is provided which when held at a TTL logic
"0" forces all true (non·lnvertlng) outputs to an
ECL logic logical "0" LOW and all compliments
(inverting) outputs to an ECL logical "1" HIGH.
applications
The DM10124 may be used as either an inverting
or non·inverting TTL to ECL translator. One dif·
ferential line driving application includes very high
speed data transmission in a TTL system by con·
verting the data to ECL levels and driving through
terminated twisted line pairs. The DM10125 is the
logical complement to the DM10124 and can be
used to translate the differential ECL levels back to
standard TTL ones. The advantages of ECL trans·
mission line characteristics (i.e. controlled edge
speeds, terminations, very high speed data rates)
may then be utilized in a TTL system.
features
• High speed
• Power dissi pation
tpd "" 3.5 ns typical
250 mW/pkg typical
connection diagram
Dual-In-Line Package
116
15
114
113
l
III'
L-
112
10'
Is
r-I
H
H
r---,
....., ,......, ,......,
H
h
'--
'---
----,
1
I
3
14
5'
6'
17'
1
8
TDPVIEW
• '" TTL lEVelS
Vee'" PIN 9 '" +5,DV
VEE =PINH=-S2V
GND . PIN 16 = OV
7·31
or:I'e
...o
...:E
N
absolute maximum ratings
Supply Voltage:
VEE
Vee
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
c
-8V
+7V
+55V
50 mA
-30°C to +85°C
-65°C to +150°C
300°C
electrical ch aracteristics
CHARACTERISTIC
SYMBOL
PIN
UNDER
TEST
I"
Icc
LogiC "1" Input Current
I'H
I'H
2: 7,10, 11
I,L
5,7,10,11
6
LogiC "1" Input Voltage
I'L
V 1HA
LogiC "0" Input Voltage
VILA
Input Clamp Voltage
LogiC "1" Output Voltage
MIN
MAX
TYP
6
MIN
MAX
1,2,14,15
-106
-089
UNITS
38
25
rnA
rnA
Inputs & Outputs
OPEN
4
16
"A
"A
VIN =V 1H =+27V
-16
60
rnA
rnA
V
08
V
V
Measured at IT '" -12 rnA
V
5051 to -2 OV
All Inputs = V 1H
-089
-070
LogiC "1" Output Voltage
V OH
3,4,12, 13
-106
-089
-096
-081
-089
-070
V
LogiC "0" Output Voltage
VOL
1,2,14, 15
-189
-1675
-185
-165
-1825
-1615
V
LogiC "0" Output Voltage
VOL
3,4,12,13
-189
-1675
-185
-165
-1825
-1615
V
LogiC "1" Threshold Voltage
V OHA
1,2,14,15
-108
VIN '" V 1L '" +0 4V
Threshold InputsUse for Test
-15
-081
-096
CONDITIONS
MAX
+20
5,6,10,11
V OH
+8SoC
+2S o C
MIN
8
9
Power Supply Dram Current
LogiC "0" Input Current
DM10124 TEST LIMITS
_30°C
-091
-098
V
'"
2.7
son to -2 OV
Pm 6= V 1L '" Q4V
501l to -2.0V
Pin 6 '" V 1L '" +0 4V
501l to -2 OV
All Inputs'" VIN = +2 7
son to -2 OV
Inputs at V1HA = +2 0
VOHA
3,4,12,13
V
50n to -2.0V
Input at V,L.A = +0 8
LogiC "0" Threshold Voltage
VOL.A
1, 2, 14, 15
-1655
-163
1595
V
50n to -2 OV
Inputs at VIL.A '" +08
LogiC "0" Threshold Voltage
VOLA
3,4,12.13
-1 655
-163
-1595
V
501l to -2 OV
Inputs at V 1HA = +2 0
SWltchmg Times 50n Load
tpd++
5,6,7,10,11
10
35
50
ns
Propagation Delay (3V p.p
t pd --
5,6,7,10,11
10
35
50
ns
t pd +-
5,6,7,10,11
10
35
50
ns
t pd -+
5,6,7,10,11
10
35
50
ns
LogiC "1" Threshold Voltage
Input at tr = tf = 2 ns,
20% - 80%)
-108
-091
-098
RlseT,me 20% - 80%
t,
Outputs
11
20
33
ns
Fall Time 20% - 80%
t,
Outputs
11
20
33
ns
Note 1:
Each Input tn Sequence,
Undrrven Inputs to
Vce (NOMf "" +5V
"Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits
table of "Electrical Characteristics" provides conditions for actual device operation.
7·32
The
o
illS
CMOS
REFERENCE
The following table references all Physical DimenSion DraWings, Waveforms, and Test Circuits for the deVices
In this section. For Order Numbers, see below.' Refer to the alpha·numerlcal Index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are In the back of the catalog.
DATA SHEETS
Devices
MM54COO
MM74COO
MM54C02
MM74C02
MM54C04
MM74C04
MM54Cl0
MM74Cl0
MM54C20
MM74C20
MM54C42
MM74C42
MM54C73
MM74C73
MM54C74
MM74C74
MM54C76
MM74C76
MM54C95
MM74C95
MM54Cl07
MM74Cl07
MM54C151
MM74C151
MM54C154
MM74C154
MM54C157
MM74C157
MM54Cl60
MM74C160
MM54C161
MM74C161
MM54C162
MM74C162
MM54C163
MM74C163
MM54C164
MM74C164
MM54C173
MM74C173
MM54C192
MM74C192
MM54C193
MM74C193
MM54C195
MM74C195
Pg.
8·1
8·1
8·1
8·1
8·4
8·4
8·6
8·6
8·6
8·6
8·9
8·9
8·11
8·11
8·14
8·14
8·11
8·11
8·17
8·17
8·11
8·11
8·19
8·19
8·22
8·22
8·25
8·25
8·27
8·27
8·27
8·27
8·27
8·27
8·27
8·27
8·31
8·31
8·35
8·35
8·38
8·38
8·38
8·38
8·41
8·41
PACKAGES
Molded DIP IN)
Fig.
Pg.
3
II
3
II
3
II
3
II
3
II
5
II
3
II
3
II
5
II
3
II
3
II
5
II
7
III
5
II
5
II
5
II
5
II
5
II
3
II
5
II
5
II
5
II
5
II
Cavity DIP IDIIJ)
Fig.
Pg.
Type
8
1II
D
8
1II
D
8
III
D
8
1II
D
8
III
D
9
III
D
8
III
D
8
1II
D
9
1lI
D
8
1II
D
8
1II
D
9
III
D
10
1II
D
9
III
D
9
III
D
9
1II
D
9
III
D
9
1Il
D
8
1Il
D
9
III
D
9
III
D
9
III
D
9
III
D
Flat Pack IFIIW)
Metal Can IGIIH)
Fig.
Fig.
Pg.
Type
*Order Numbers' use DeVice No. suffixed With package letter, I.e. MM54COOD .
.-:
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
8·3
8·3
8·3
8·3
8·4
8·4
8·8
8·8
8·8
8·8
8·3
8·3
8·3
8·3
8·4
8·4
8·8
8·8
8·8
8·8
8·13
8·13
8·16
8·16
8·13
8·13
8·13
8·13
8·16
8·16
8·13
8·13
8·13
8·13
B·21
8·21
8·24
8·24
8·13
8·13
8·21
8·21
B·30
B·30
8·30
8·30
8·30
8·30
8·30
8·30
8·33
8·33
8·36
8·36
8·42
8·42
8·33
8·33
3!:
oen
CMOS
MM54COO/MM74COO quad two-input NAN 0 gate
MM54C02/MM74C02 quad two-input NOR gate
general description
EmploYing complementary MOS (CMOSI tran·
slstors to achieve low power and high noise mar·
gin, these gates provide the basic functions used
in the implementation of digital Integrated cir·
cuit systems. The Nand P channel enhancement
mode transistors provide a symmetrical circuit
with output swings essentially equal to the supply
voltage. This results In high noise immunity over
a wide supply voltage range. No DC power
other than that caused by leakage current IS
consumed during static conditions. All Inputs
are protected aga inst static discharge damage.
features
•
Wide supply voltage range
•
Guaranteed noise margin
•
High nOise immunity
•
Low power
•
Low power T2L
compatible
0.3 Vcctyp
10 nW typ
drive 2 L T2L loads
applications
•
Automotive
•
Instrumentation
•
Alarm systems
•
R emote metering
•
Data terminals
•
Medical electronics
3V to 15V
•
I ndustrial controls
1V
•
Computers
schematic and connection diagrams
MM54COO/MM74COO
X=
Ai
GNO
TOPVIEW
MM54C02!MM74C02
,-""-----,,,,--0 Vee
Vee
GNO
TOP VIEW
8·1
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature MM54COO,MM54C02
MM7 4COO,MM7 4C02
Storage Temperature
Package DIssipation
Lead Temperature (Soldering, 10 sec)
Operating Vcc Range
-0.3V to +Vcc + 0.3V
-55°C to +125°C
ODC to +70°C
_65°C to +150 DC
500 mW
300°C
+3V to +15V
electrical characteristics
MinIMax limits apply across the guaranteed temperature range unless otherWise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS to CMOS
Logical "1" Input Voltage
VIN
(1)
Vee'" 5.DV
Vee'" 100V
Logical "0" Input Voltage
VIN
{OJ
Vee; =: 5 OV
Vee'" 10GV
3,5
80
V
V
15
20
V
V
Logical "1" Output Voltage V OUT (1)
Vce=50V, V IN =15,1 0 "'-10,uA
Vec=100V,VIN=70,10=-10,uA
LogICal "0" Output Voltage V OUT (0)
Vee -= 50V, VIN '" 3 5,1 0 '" 10,uA
Vee=lDOV,VIN"'BO,10=10fJA
05
10
Logical "1' Input Current liN (ll
Vee'" 15V, VIN '" l5V
1
pA
45
90
V
V
V
V
Logical "0" Input ClIrrent liN (OJ
Vee'" 15V, VIN '" OV
Output Short
(Note 2)
Curtent los (1)
V ee ""55V, VIN"'O,Vo=D
Vee = 11 OV, V IN '" 0, Vo '"
a
1
75
6
30
rnA
rnA
Output Short CirCUit Current los (OJ
(Note 2)
Vee=55V, VIN=Vo"'Vee
Vee'" 11 OV, VIN = Vo '" Vee
15
10
10
40
rnA
rnA
C,I·CUlt
-1
pA
Supply Current Icc
Vee= l5V
Propagation Delay Time to a
Vee 50V, C L =50pF,T A "'25°C
Vee'" 100V,C L =50pF, TA = 25 n C
50
25
90
60
ns
ns
Vee'" 5 OV, C L
Vee'" 10 OV, CL
50
30
90
60
ns
ns
logical "0"
tpdO
Propagation Delay Time to a
Logical "1" tprll
1
'"
'"
50 pF, T A '" 25"C
50 pF, T A'" 25"C
LOW POWER TTL to CMOS
Logical "1 ' Input Voltage Y'N (1)
54C Vee'" 4 5V
74C Vee = 475V
Loglql "0" Input Voltage Y'N {OJ
54C Vee'" 4 5V
74C Vee'" 4 75V
Loglcal"1 'Output Voltage V OUT (1)
54C Vee'" 4 5V, 10 = -10!J.A
74C Vee'" 4 75V, 10'" -lOfJA
Logical "0 'Output Voltage V OUT (0)
54C Vee'" 4 5V, 10 '" 10,uA
74CV ec =475V, 10= 10,uA
Propagation Delay Time to a
Vee'" 5 OV, CL
Logical "0"
'"
V
Vee - 1 5
08
15 pF,T A
'"
44
V
V
08
V
125
25°C
tpdlO)
Propagation Delay Time to a
Logical "1" t pd (l)
125
CMOS to Low Power TTL (tenth power)
Logical "1" Input Voltage VIN (1)
54C Vee = 4 5V
74C Vee'" 4 75V
Logical "0" Input Voltage VIN (0)
54C Vee = 4 5V
74C Vee'" 4 75V
LOglCill "1" Output Voltage V OUT (1)
54CVec"'45V,VIN"'08,lo=-100,uA
74CVee "'475V, VIN =08,l o ""-100pA
40
40
10
10
24
V
V
24
Logical "0" Output Voltage V OUT (0)
54CVec=45V,VIN=40,10=360,uA
74CVee=475V,VIN=40,lo=360f.j.A
Propagation Time to a
Logical "0" tpdiO)
Vec" 5 OV, CL
T A = 25°e
50 pF, RL '" 20k,
60
ns
Propagation Time to a
LogiCal "1" t pdl 1)
Vee'" 5 OV, C L '" 50 pF, R L '" 20k,
T A '" 25°C
45
ns
=
Note 1: These deVices should not be connected under power on conditions
Note 2: Only one output at a time may be shorted.
8·2
V
04
04
V
V
switching time waveforms and ac test circuits
CMOS to CMOS
V1N
V"~
50%
50%
F
DV
~"(
50%
50%
V OUT
OV
TTL to CMOS
'": dr
'"_%_\
VOUT OV _ _ _ _
)~
t
VOUT
T
50%
15PF
*15 PF
CMOS to low power T2L
v,,::
50%/
_., "--;::-:jr
~
--l
ir=-'~'
15V
'f15V
OV _ _ _ _
_ '-_ _ _....J'
applications
Guaranteed nOIse margin as a
function of Vee
15V
135
74C Compatib,lity
125
'"w
;
u
~
405
3.05
VIN
(0)
25
15
145
045
4.50V
10V
15V
Vee
8·3
CMOS
M M 54C04/ MM74C04 hex inverter
general description
The MM54C04/MM74C04 hex Inverter is constructed from complementary MOS (CMOS) enhancement tranSIStors to achieve lower power
and high nOise margin.
•
Wide supply voltage range
•
Guaranteed nOise margm
•
High nOise Immunity
•
Low power
drIVe 2 LPTTL
loads
applications
•
features
•
Tenth power TTL compatible
3V to 15V
1V
0.45 Vee typ
10 nW typ
Automotive
•
Instrumentation
•
Alarm systems
•
Remote meterl ng
•
Data termmals
•
Medical electronics
•
Industrial controls
•
Computers
connection diagram
Dual-In-Line Package
74C Compat,b,lity
switching time waveforms
CMO~toCMOS
TTL to CMOS
'. ~-:?r
v"
v"
OV
'...,
v"
V OUT
50% \
V OUT
OV·
)15~V
'. .,
t
50%
t,=t,=20ns
Guaranteed Noise Margin as a
Function of
15V
Vee
r:-:=======,,-,
13'
"'
40'
30'
LVi"§(~O'~~~~~~~ 2'
145 ~
04,
45DV
8-4
15
IOV
15V
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C04
MM74C04
Storage Temperature
Package Dissipation
Lead Temperature (Soldering, 10 sec)
Operating Vcc Range
-0.3V to Vee +0.3V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
500 nW
300°C
+3V to +15V
electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage V IN (1)
Logical "0" Input Voltage
VIN(O)
logical "1" Output Voltage V OUT (1)
Logical "0" Output Voltage
VOUT(O)
8
Vee = 5V
Vee = 10V
Vee = 5V
Vee = 10V
10 = -1OMA
10 = -lOj.lA
Vee = 5V
Vee = 10V
10 = +10MA
10 = +10MA
IIN(1)
Vee = 15V
Y'N = 15V
Logical "0" Input Current IIN(O)
Vee = 15V
VIN
Supply Current Icc
Vee = 15V
Logical "1" Input Current
V
V
35
Vee = 5V
Vee = 10V
=
15
2.0
V
V
05
10
V
V
V
V
4.5
9.0
1
MA
5
IlA
MA
-1
OV
01
pF
5
Input Capacitance
Any Input
Propagation Oelay Time to a
Logical "1," tpd1
Vee = 5V
Vee = 10V
CL = 50 pF. T A = 25"C
CL = 50pF. TA =25"C
40
25
90
60
os
ns
Propagation Delay Time to a
Logical "0," tpdO
Vee = 5V
Vee = 10V
C L = 50 pF, T A '" 25°C
CL = 50 pF. T A = 25" C
40
25
90
60
ns
ns
Logical "1" Input Voltage V IN (1)
54C
74C
Vee = 4 5V
Vee = 4 75V
Logical "0" Input Voltage V1N{O)
54C
74C
Vee = 4 5V
Vee=475V
Logical "1" Output Voltage V OUT (1)
54C
74C
Vee = 4 5V, 10 = -lOIlA
Vee = 4 75V, 10 = -lOIlA
Logical "0" Output Voltage
54C
74C
Vee
Vee
Vee = 5V
CL = 15 pF. T A
25'C
125
ns
Vee = 5V
CL = 15 pF, T A = 25" C
125
ns
Logical "1" Input Voltage V 1N {1l
54C
74C
Vee =45V
Vee = 4 75V
Logical "0" Input Voltage
54C
74C
Vee = 4 5V
Vee = 4 75V
LOW POWER TO CMOS
VOUT{Q}
PropagatlOn Delay Time to a
Logical "1," tpdl
Propagation Delay Time to a
Logical "0,"
V
Vee - 1 5
0.8
V
4.4
V
04
= 4 5V, 10 = +101lA
= 4 75V, 10 = +101lA
tpdO
CMOS TO LOW POWER
VIN(O)
Logical "1" Output Voltage
VOUT(l)
54C
74C
Vee = 4 5V, 10 = -1001lA
Vee = 4 75V. 10 = -1001lA
Logical "0" Output Voltage
VOUT(O)
54C
74C
Vee = 4 5V, 10 = 360llA
Vee = 4 75V. 10 = 360MA
V
40
10
V
V
24
04
V
Note 1: This deVice should not be connected to Circuits With the power on because high tranSient voltage may cause
permanent damage.
8-5
CMOS
MM54C10/MM74C10 triple three-input NAND gate
MM54C20/MM74C20 dual four-input NAND gate
general description
Employing complementary MOS (CMOS) transistors to achieve low power and high nOise margin, these gates provide the basIc functions used
in the implementation of digital Integra ted cirCUit systems. The Nand P channel enhancement
mode transistors provide a symmetrical CirCUit
with output sWings essentially equal to the supply
voltage. ThiS results In high nOise Immunity over
a Wide supply voltage range No DC power
other than that caused by leakage current IS
consumed dUring static conditions All inputs
are protected against static discharge damage.
Wide supply voltage range
•
Guaranteed nOise margin
High noise immunity
Low power
•
Low power T2L
compatible
0.45 Vee typ
10 nW typ
drive 2 LPT2 L loads
applications
•
•
features
•
•
•
Automotive
•
Instrumentation
•
Alarm systems
•
Remote metering
•
Data term Inals
•
Med Ical electronics
3V to 15V
•
I ndustrlal controls
1V
•
Computers
schematic and connection diagrams
MM54Cl0/MM74Cl0
Dual-In-Lme Package
y-~+-::t-o x· ABC
MM54C20/MM74C20
Dual-In-Line Package
8-6
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature MM54Cl0, MM54C20
MM74Cl0, MM74C20
Storage Temperature
Package D 1551 patlan
Lead Temperature (Soldering, 10 sec)
Operating Vee Range
-0.3V to +Vcc + 0.3V
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
500mW
300°C
+3V to +15V
electrical characteristics
MiniMax limits apply across the guaranteed temperature range unless otherwise specified.
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
CMOS to CMOS
Logical "1" Input Voltage
VIN
(1)
Vcc=50V
Vee = 10 OV
Logical "0" Input Voltage
VIN
(O)
Vcc=50V
Vee = 10 OV
35
80
V
V
15
20
Logical "1" Output Voltage V OUT (1)
Vcc=50V, VIN = 1 5,1 0 -; -10pA
Vee= lOOV, V 1N =2, lo=-lOJ.1A
Logical "0" Output Voltage V OUT (0)
Vcc=50V,
45
90
V
V
05
10
V 1N =35,l o = lOpA
Vcc=1ODV,VIN=80,lo=10.uA
1
Logical "1" Input Current liN (1)
Vee'" 15V, VIN
Logical "0" Input Current liN (0)
Vee'" 15V, VIN = OV
Supply Current Icc
Vee = 15V
001
Input Capacitance
Any Input
7
Propagation Delay Time to a
Logical "0" tpdO
54Cl0/74C1O
=
54C20/74C20
Propagation Delay Time to a
Logical "1" tpd1
54Cl0/74Cl0
54C20/74C20
V
V
15V
-1
Vcc=50V, C L =50pF,T A =25cC
V
V
"A
"A
2
"A
pF
50 pF, T A'" 2SDC
50
25
90
60
ns
n,
Vee" 5 OV, C L " SO pF, T A = 25 D C
Vee'" 10 OV, C L = 50 pF, T A " 25 D C
70
30
110
75
ns
ns
Vee" 5 OV, C L
60
35
100
60
ns
70
40
115
80
ns
Vee -; 10
av, C L
'"
SO pF, T A'" 2SoC
'"
Vee'" 10 OV,C L = 50 pF, TA '" 25°C
V ee "50V,C L ""50pF, T A =25°C
Vee = 10 OV, C L
"
50 pF, T A = 25°C
ns
ns
lOW POWER TTL to CMOS
Logical "1" Input Voltage V IN (1)
54C Vee" 4 5V
74C Vee" 4 75V
Logical "0" Input Voltage VIN (0)
S4C Vee = 4 SV
74C Vee" 4 75V
Logical "1" Output Voltage V OUT (1)
54C Vee" 4 5V, 10'" -10pA
74C Vee = 4 75V, 10 '" -10,uA
Logical "0" Output Voltage V OUT (0)
54C Vee'" 4 5V, 10 "'" lOpA
74C Vee = 4 75V, 10 '" 10,uA
Propagation Delay Time to a
Logical "0" tpd(Q)
Vee'" 5 OV, C L = 1S pF, T A" 2SoC
125
"'
Propagation Delay Time to a
Logical "1" tpdW
Vee = S OV, C L == 15 pF, T A" 25°C
125
ns
V
Vee - 15
08
44
V
V
08
V
CMOS to Low Power TTL (tenth power)
40
40
V
V
Logical" 1" I nput Voltage V IN (1)
54C Vee == 4 5V
74C Vee = 4 75V
Logical "0" Input Voltage V IN (0)
54C Vee" 4 5V
74C Vee == 4 75V
Logical "1" Output Voltage V OUT (1)
54Cl0 Vee = 4 5V, V IN = 1 0, 10 = -100pA
74Cl0 Vee == 4 75V, VIN == 1 0, 10 = -100pA
24
24
V
V
54C20 Vee'" 4 5V, VIN = 0 8,1 0 '" -100pA
74C20 Vee'" 4 7SV, V IN == 08,1 0 = -100,uA
24
24
V
V
10
10
04
04
V
V
V
V
logical "0" Output Voltage V OUT (0)
54C Vee = 4 5V, V IN == 4 0,1 0 == 360,uA
74C Vee == 4 75V, V IN = 4 0, 10 = 360,uA
PropagatlOn TIme to a
Logical "0" tpd(O)
Vee"" 50V,C L " 50pF, RL" 20k,
T A = 2SoC
60
ns
PropagatIon TIme to a
Logical "1" tpd(t)
Vee = 5 OV, C L = SO pF, R L = 20k,
T A = 2S"C
45
n,
Note 1: These deVices should not be connected under power on conditions.
8-7
switching time waveforms and ac test circuits
CMOS to CMOS
":~-.j"
Voo ,
~%
j50
t
50% \
ov-~--
'eO'
50%
~-'----~
Test Circuit
TTL to CMOS
": dr
V
50%\
oo ,
ov
}~ .
F
'
Test Circuit
CMOS to low power T2L
v,"
5V-
-5::~ 50%
'•. :: -----;:-::'j JOV -
15V\
j};:1;:-::-'''''
}j15V
Test Circuit
applications
Guaranteed noise margin as a
function of
Vee
15V
135
74C CompatIbIlity
125
~
;
u
~
405
305
25
15
145
045
450V
10V
Vee
8-8
15V
CMOS
MM54C42/MM74C42 BCD to decimal decoder
general description
The MM54C42/MM74C42 one of ten decoder IS
a monolithic complementary MOS (CMOS) integrated circUit constructed with Nand P-channel
enhancement tranSIStors. This decoder produces a
logical "0" at the output corresponding to a four
bit binary Input from zero to nine, and a logical
"1" at the other outputs. For binary Inputs from
ten to fifteen all outputs are logical "1."
Supply voltage range
•
Tenth power TTL
compatible
•
applications
•
Automotive
•
Data terminals
Instrumentation
Medical electronics
3V to 15V
•
Alarm systems
drive 2 LPTTL loads
•
Industrial electronics
0.45 Vee (typ.)
10 MHz (typ.)
with 10V Vee
•
High noise immunity
50 nW (typ.)
Low power
Medium speed operation
•
features
•
•
•
•
Remote metering
•
Computers
schematic diagram
'"
'"' * '" " "
mM''''T''"'"''
connection diagram
Dual~ln"Lme
I"
"
"
"
truth table
Package
"
"
'"
,
INPUTS
DeB A
o 0 0 0
o 0 0 1
o
t
1
,
,
,
,
. . 'I'
o
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
o
o
0
0
1
1
1
1
1 0
1 1
0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
o 0
0 1
1 0
1 1
o
OUTPUTS
o
o
1
1
10
11
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
2 3 4 5 6 7 8 9
1 1 1 1 1 1 1 1
1 1 1 11 1 1 1
o 1 1 1 1 1 1 1
1 01 1 1 1 1 1
1 1 o 1 1 1 1 1
1 1 1 0 1 1 I I
1 1 1 10 I 1 I
1 1 I 1 101 I
1 1 1 1 I 1 01
1 1 I 1 I 1 10
1 I 1 1 I I I 1
1 I 1 1 1 1 1 I
1 1 1 1 1 1 1 I
1 1 I 1 1 1 I I
1 1 I 1 I I I I
1 1 I 1 I I I I
8-9
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature MM54C42
MM74C42
Storage Temperature
Package Dissipation
Operating Vee Range
Lead Temperture (Soldering, 10 sec)
-0.3V to Vee +0.3V
_55°C to +125°C
O°C to + 70°C
_65°C to +150°C
500 mW
3V to 15V
300°C
electrical cha racteristics MiniMax limits apply acrOss temperature range unless otherWISe specified
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage
VI N (1)
Logical "0" Input Voltage
V,NIOI
Logical "1" Output Voltage
VOUT(11
Vee = 5.av
Vee= 100V
Logical "1" I nput Current
V
V
8
15
2
Vee = 50V
Vee= 10.0V
Vee=50V,IO=-10~A
Vee = 100V.10 = "10~A
Logical "0" Output Voltage VOUTIOI
35
4.5
9.0
V
V
Vee = 5 OV, 10 = +10~A
Vee= 100V, lo=+10~A
0.5
IIN!l)
Vee= 150V, V'N= 15V
I'NIOI
Vee = 15.0V, V ,N = OV
IcC
Vee = 15.0V
005
Input Capacitance
Any Input
5
Prop~gatlOn Delay Time to a
Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10 OV, CL = 50 Pp. T A = 25°C
Logical
"a"
Input Current
Supply Current
Logical "0" or Logical "1"
V
V
1
V
V
1
IJA
-1
IJA
200
90
30
IJA
pF
300
140
ns
ns
CMOS TO TENTH POWER
INTERFACE
Logical "1" Input Voltage
V IN(1)
54C. Vee = 4.5V
74C, Vee = 4.75V
Logical "0" Input Voltage
VINIO)
54C, Vee = 4 5V
74C, Vee = 4.75V
Logical "1" Output Voltage
VOUT(t)
54C, Vee= 4 oV.lo = -100~A
74C, Vee = 4.75V.lo = -100IJA
Logical "0" Output Voltage
VOUTIOI
54C, Vee = 4 5V. 10 = 360 j.1A
74C. Vee" 4 75V, 10 = 360IJA
Propagation Delay Time to a
Logical "0" or Logical "1"
Vee = 5.0V, C L = 50 pF, TA = 25°C
V
Vee- 1.5
0.8
V
V
24
0.4
250
400
V
ns
Note 1: This deVice should not be connected to circuits with the power on because high tranSient voltages may cause
permanent damage.
8·10
CMOS
MM54C73/MM74C73 dual J-K flip flop with clear
MM54C76/MM74C76 dual J-K flip flop
with clear and preset
MM54C107lMM74C107 dual J-K flip flop with clear
general description
These dual JK flip flops are monolithic Complementary MOS (CMOS! Integrated CirCUits constructed with Nand P channel enhancement
transistors. Each flip flop has independent J, K,
clock and clear Inputs and Q and Q outputs The
MM54C76/MM74C76 flip flops also Include preset
Inputs and are supplied In 16 Pin packages. These
flip flops are edge sensitive to the clock Input and
change state on the negative gOing transition of
the clock pulses. Clear or preset IS Independent of
the clock and IS accomplished by a low level on
the respective Input.
features
•
Supply voltage range
•
Tenth power TTL
compatible
3V to 15V
drive 2 LPTTL loads
0.45 Vee (typ!
•
High nOise immunity
•
•
Low power
Medium speed operation
50 nW (typ!
10 MHz (typ!
with 10V supply
applications
•
Automotive
•
Data terminals
•
Instrumentation
•
Medical electronics
•
Alarm systems
•
Industrial electronics
•
Remote metering
•
Computers
logic and connection diagrams
mm
Transmission Gate
R
Cl
T
MM54C73/MM74C73 and MM54Cl07/MM74Cl07
'co
INPUTfROTECTION+TOINTERNAl
fOR ALI INPUTS
CIRCUITRV
Cl
Cl
ClOCK~
MM54C76/MM74C76
" -'-'t-----,
CLOCKS 5
Q.
, '.
,-",,,
AI01l"
0
.~d .. ,
.. n 11 10 logl< 0
Not.
AlolI'C 0 on Qto,log,c
1
MM54C76/MM74C76
8-11
fI')
,....
(.)
~
;
,....
~
absolute maximum ratings
(.)
~
,....
Voltage at any pin (Note 11
Operating Temperature MM54CXX
MM74CXX
Storage Temperature
Package DISSipation
Lead Temperature (Soldering, 10 secl
Operating Vee Range
:E :E
.......
:!
,....
,.... .......
(W)
...
(.)
0
~
(.)
It)
-o.3V to Vee +0.3V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
500 mW
300°C
+3V to 15V
~
:E It)
:E :E
:E
electrical characteristics'
CD
,....
PARAMETERS
(.)
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
~
,....
:E
:E
.......
CD
,....
(.)
~
It)
:E
:E
Logical "1" Input Voltage V 1N (1)
Vee = 5 OV
Vee = 10.0V
Logical "0" Input Voltage V1N{O)
Vee = 5.0V
Vee = 10.0V
Logical "1" Output Voltage V OUi (l)
Vee = 5.0V
Vee = 10 OV
Logical "0" Output Voltage VOUTIOI
Vee = 5 OV
Vee = 100V
Logical "1" Input Current
IINIl)
Vee=150V
Logical "0" Input Current
IIN(O)
Vee=150V
35
8
V
V
1.5
2.0
45
90
V
V
0.5
1.0
V
V
1.0
J.lA
-10
J.lA
Supply Current Icc
Vee = 150V
0.050
Input Capacitance
Any Input
5
Propagation Delay Time to a Logical "0"
V
V
10
J.lA
pF
Vee = 50V,C L = 50pF, TA = 25"C
Vee = 100V,C L =50pF, TA =25'C
180
80
300
130
ns
ns
PropagatIOn Delay Time to a Logical "0"
From Preset or Clear
Vee = 5 OV, C L = 50 pF, TA = 25'C
Vee = 100V,C L = 50 pF, TA = 25'C
200
80
300
130
ns
ns
Propagation Delay Time to a Logical "1"
From Preset or Clear
Vee = 5.0V, C L = 50 pF, T A = 25'C
Vee = 10V, C L = 50 pF; T A = 25'C
200
80
300
130
ns
ns
TI me Prior to Clock Pulse That Data Must
Vee = 50V,C L = 50pF, TA =25'C
Vee = 10V, C L = 50 p~, TA = 25'C
90
40
130
60
ns
ns
0
or Logical" 1"
QorO
tpdO
be Present,
tpd1
From Clock to
tS ETUP
Time After Clock Pulse That J and K
Must be Held
Vee = 5 OV, C L = 50 pF, TA = 25'C
Vee = 100V,C L =50pF, TA =25'C
-40
-20
a
ns
ns
Minimum Clock Pulse Width
Vee = 5 OV, C L = 50 pF, TA = 25'C
Vee = 10.0V, C L = 50 pF, TA = 25'C
90
40
130
60
ns
ns
MInimum Preset and Clear Pulse Width
Vee = 5.0V, C L = 50 pF, T A = 25'C
Vee = 100V,C L = 50pF, TA = 25'C
90
40
130
60
ns
ns
Maximum Toggle Frequency
Vee = 5.0V, C L = 50 pF, TA = 25'C
Vee = 10 OV, C L = 50 pF, TA = 25'C
Clock Pulse RISe and Fall Time
Vee = 5.0V, C L = 50 pF, TA = 2S'C
Vee = 10 OV, C L = 50 pF, TA = 25°C
tWL:::: tWH
2.5
5
.
5
10
MHz
MHz
15
5
J.ls
J.ls
LOW POWER TTL TO CMOS INTERFACE
Logical "1" Input Voltage V ,NI1 )
Logical "0" Input Votlage V 'N1O )
54C, Vee
74C, Vee
= 4 5V
= 4.75V
74C, Vee
54C, Vee = 4.5V, 10 = -100J.lA
74C, Vee = 4.75V, 10 = -100J.lA
Loglcal"Q" Output Voltage
54C, Vee
74C, Vee
Propagation Delay Time to a Logical "0"
tpdO or LogIcal "1" From Clock
V
Vee
08
= 4.75V
Logical "1" Output Voltage V OUTI1 )
VOUT(O)
V ee ·15
54C, Vee = 4 5V
2.4
V
= 4.5V, 10 = 360J.lA
= 4 75V, 10 = 360j1A
= 5 OV, CL = 50 pF, T A = 25'C
V
04
250
V
ns
Note 1; These devices should not be connected to circuits with the power on because high transient voltage may cause
permanent damage.
8-12
ac test circuit
truth table
tn
Vee Vee
tn
0;;:
tn+1
tn+1
J
K
a
a
a
a
On
1
a
1
1
0
1
1
On
bit time before clock pulse
=
bit time after clock pulse
3:
3:
typical applications
en
74C CompatIbility
~
Ripple Binary Counters
(")
Vee
C~~~~i~--------------..~--------------~----------------,
-"
o
.....
.......
3:
3:
.....
~
....
(")
Guaranteed Noise Margin as a
Function of
o.....
CLOCK----------------------------------------~
Vee
15V
135
125
Shift Registers
DATA
INPUT
405
a
305
25
15
145
045
K CLK
K CLK
jj
K CLK
jj
jj
CLOCK
450V
10V
15V
Vee
switching time waveforms
CMOS TO CMOS
TTL TO CMOS
t,
Vee
4.0V
90%
50%
CLOCK
OV
OV
Vee
40V
J or K
[;JI
tSETUP
tHOLD
J or K
OV
OV
Vee
Vee
50%
OorO
OV
OV
Vee
Vee
50%
OorD
OV
r--tpdO-
15V
OV
t," tl'''
20 ns
8-13
CMOS
MM54C74/MM74C74 dual 0 flip flop
general description
The MM54C74/MM74C74 dual D flip flop IS a
monolithic complementary MOS (CMOS) Inte·
grated CirCUit constructed with Nand P·channel
enhancement transistors. Each flip flop has Inde·
pendent data, preset, clear and clock Inputs and
Q and Q outputs. The logic level present at the
data input is transferred to the output during the
positive going transition of the clock pulse. Preset
or clear is Independent of the clock and accom·
pi ished by a low level at the preset or clear input.
features
•
•
Supply voltage range
Tenth power TTL compatible
3V to 15V
drive 2LPT 2 L
loads
•
•
•
High noise immunity
Low power
Medium speed operation
0.45 Vee (typ)
50 nW (typ)
10 MHz (typ)
with 10V supply
applications
•
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Industrial electronics
Remote metering
Computers
logic and connection diagrams
/>RfSET _ _ _ _ _ _~~---.J
ff
Ct
CLOCK~
T
~~AllPCHANNElSlJBSTRAUS
II--
CONN£CTEDTOVcc
-.J~
ALLNCHANNELSUBSTflATES
II--
'"
' 'UT,"OTEcr,,,+
'OR ' " '''"''
CONNECTED TO GND
Dual-I n-Line Package
NOTE Alo9'C "O"onclea,setsQtolog,c '0"
A logIc "0"
8·14
00
presel sets 0 to log'c 'I"
-::-
TO "TERNAl
"'W,,
absolute maximum ratings
Voltage at any Pin (Note 1)
Operating temperature MM54C74
MM74C74
Storage temperature
-0.3V to Vee + 0.3V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
500mW
300°C
+3V to +15V
Package diSSipation
Lead temperature (Soldering, 10 secl
Operating Vee range
electrical characteristics
Mm/Max limits afJply across temperature range unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage V 'N ll)
Vee=50V
Vee= 10.0V
"a" Input Voltage V'NIO)
Vee = 5.0V
Vee = 10.0V
Logical
Logical "1" Output Voltage VOUTll)
Vee = 5.0V
Vee = 10.0V
"a" Output Voltage VOUTIO)
Vee = 5.0V
Vee= 100V
Logical
Logical "1" Input Current I'Nll)
Vee = 15.0V
"a" Input Current I'NIO)
Vee= 150V
Logical
Supply Current Icc
Vee = 15.0V
V
V
35
80
15
20
45
9.0
V
V
V
V
0.5
10
V
V
10
/1A
-1.0
/1A
001
/1A
pF
I nput Capacitance
Any Input
Propagation Delay Time to a Logical
"a" tpdO or L<:glcal "1" tpdl from
clock to Q or Q
Vee = 5 OV, CL = 50 pF, T A = 25° C
Vee = 10.0V, CL = 50 pF, TA = 25°C
180
70
50
ns
ns
Propagation Delay Time to a Logical
"a" from Preset or Clear
Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C
200
90
ns
ns
Propagation Delay Time to a Logical
"1" from Preset or Clear
Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, TA = 25°C
200
90
ns
ns
Time Pnor to Clock Pulse That Data
Must be Present t SETUP
Vee= 50V, CL = 50pF, TA = 25°C
Vee= 100V, CL = 50 pF, TA = 25°C
30
15
ns
Time After Clock Pulse That Data
Must be Held
Vee = 5. OV, CL = 50 pF, T A = 25° C
Vee = 10 OV, CL = 50 pF, TA = 25°C
a
a
ns
ns
Minimum Clock Pulse Width
(tWL = tWHI
Vee = 50V, CL = 50 pF, TA = 25°C
Vee = 10 OV, CL = 50 pF, TA = 25°C
70
30
ns
ns
Minimum Preset and Clear Pulse
Width
Vee = 5.0V, C L = 50 pF, T A = 25°C
Vce = 10.0V, CL = 50 pF, T A = 25°C
90
40
ns
ns
MaXimum Clock RISe and Fall
Time
Vee = 5.0V, C L = 50 pF
Vee= 100V,C L = 50 pF
5.0
20
/1S
/1S
0.8
V
LOW POWER TTL/CMOS INTERFACE
Logical "1" Input Voltage V 'N ll)
54C, Vee = 4.5V
74C, V ce = 4.75V
"a" Input Voltage V ,NIO)
54C, Vee = 4 75V
:74C, Vee = 4.75V
Logical
Logical '.,.' Output Voltage VOUTll)
Logical
"a" Output Voltage VOUTIO)
Propagation Delay Time to a Logical
"a" tpdO or Logical "1" from elock
54C, Vce = 4.5V,ID = -100/1A
74C, Vee = 4.75V,I D = -100/1A
V ec -l.5
V
2.4
04
54C, Vee = 4.50V, I D = 360 /1A
74C, Vee = 4.75V, ID = 360 /1A
Vee = 5.0V, C L = 50 pF, TA = 25°C
250
V
V
Note 1: These deVices should not be connected under power on conditions
8-15
~
.....
CJ.
switching time waveforms
~
.....
:E
:E
......
CMOS to CMOS
Vee
~
.....
TTL to CMOS
4.0V----H,.....------
90%
50%
CLOCK
ov---....:lrl
OV
CJ
~
it)
:E
:E
Vee
0.4V -Hr::::::;--+-=~
OV
ov-HF"-+"";''''''''["
DATA
DATA
vee----------~----------.,_---
Vee
50%
OorO
ov--___~-----J
OV
Vee -------~~------.....
Vee
511%
QDrO
oV----------------
OV
1,=1,,,, 20 ns
ac test circuit
.
"~~ ,,
INPUT
CLOCK
typical applications
Ripple Counter (Divide by 2n)
CLOCK
Q
CLOCK
Q
CLOCK
Shift Register
Q
DATA
Q
DATA
Q
DATA
Guaranteed Noise Margin as a'
74C Compatibility
Function of VCC
15V
1"7========-0
13.5
12.5
Vee
w
~
~
;
405
<0 305
~
u
25
1.5
145
045
450V
10V
. Vee
8-16
15V
Q
CMOS
MM54C95/MM74C954-bit right-shift left-shift register
general description
features
This 4-bit shift register is a monolithic complementary MOS (CMOS) integrated circuit composed of
four D nip flops. This register will perform rightshift or, left-shift operations dependent upon the
logical input level to the mode control. A number
of these registers may be connected in series to
form an N-bit right shift or left shift register.
•
•
Medium speed operation
Vee
High noise Immunity
~
10 MHz typ
lOV, CL ~ 50 pF
045 Vee typ
100 nW typ
Drive 2 LTTL
loads
3V to 15V
• Low power
• Tenth power TTL
compatible
• Wide supply voltage range
• Synchronous parallel load
• Parallel Inputs and outputs from each flip flop
• Negative edge triggered clocking
When a logical "0" level is applied to the mode
control input, the output of each flip flop is
coupled to the D input of the succeeding flip flop.
Right-shift operation IS performed by clocking at
the clock 1 Input, and serial data entered at
the serial input, clock 2 and parallel inputs A
through D are inhibited. With a logical "1" level
applied to the mode control, outputs to succeeding
stages are decoupled and parallel loading is possible,
or with external interconnection, shift-left opera·
tion can be accomplished by connecting the
output of each flip flop to the parallel input of
the previous fl ip flop and serial data is entered at
input D.
applications
•
•
Data terminals
Instrumentation
•
•
•
•
•
Automotive
Medical electrOnics
Alarm systems
Remote metering
Industrial electronics
•
Computers
block and connection diagrams
CLOCKl
ASIIIFT
_ r--
MC
MODECONTROl~MC
MOOECONTAOt'OFORRIGHTSHIFT
MODECONTROl-' FORLEfTSHIFTOAPARALLEL LOAD
ol!--GND
Dual-I n·Line Package
INPUT
,
OUTPUT
,
OUTPUT
,
SERIAL
INPUT
INPUT
INPUT
\I
C
OUTPUT
C
Vee
OUTPUT
0
CLOCf(2
t-SHlfT
INPUT
MODE
CLOCK 1
0
CONTROL
RSHIFT
8·17
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C95
MM74C95
Storage Temperature
-0 3V to Vee +03V
-55°C to +125°C
aOc to +70°C
--65°C to +150°C
500mw
Package DISSipation
Operating Vee Range
Ll:'ad Temperature (Soldering, 10 sec)
+3V to +15V
300·C
electrical characteristics
Max/min limits apply across temperature range unless otherwise specified.
PARAMETER
CONDITIONS
I
MIN
I
TVP
MAX
UNITS
CMOS TO CMOS
35
8
Logical "1" Input Voltage VIN (11
Vec= SOV
Vec" 100V
Logical "0" Input Voltage VIN(OI
Vee = SOV
Vee'" lOOV
Logical "1" Output Voltage VOUTI!I
Vee'" SOV
Vee = lOOV
Logical "0" Output Voltage VOUTIOI
Vee'" SOV
Vee = 100V
Loglc.al "1 'Input Current IINUI
Vee'" lS0V
Logical "0" Input Current IIN(O)
Vee
Supply Current Icc
Vce = lS0V
Input Capacitance
Any Input
PropagatIon Delay Time to a Logical "0" tpdO
or Logical "1" tpdl from Clock to Q or Q
Vee = SOV,C L =SOpF, TA. =2SoC
Vee = 100V,CL = 50 pf, TA. = 2SoC
200
80
Time Prior to Clock Pulse Thdt Data Must be
Preset tSETUP
Vee'" 50V,C L =50pF,TA."'2Sc C
Vee = 100V,C L = 50 pF, TA. = 2SoC
15
10
Time After Clock Pulse That Data Must be
Held
Vce = 50V,C L =-50pF, TA =2SoC
Vee = 100V,CL =50pF, TA = 2SoC
Minimum Clock Pulse Width (tWL = tWH)
V ee - 50V,CL =-SOpF,TA "'25°C
Vee" 100V,CL = SOpF, TA = 2SoC
100
50
Mlntmum ModI' Control Pulse Width
Vee - 50V, CL = 50pf, TA '" 2SQC
Vee = 100V,CL = 5OpF, TA " 25°C
100
40
Maximum Clock Rise and Fall Time
Vee" 5 OV, CL "SOpF, TA = 2SoC
Vce = 100V,CL = 50pF, TA. ~25°C
Maximum Input Clock Frequency
Vee" SOV,C L 5OpF,T A =25°C
Vee = lOOV, CL = 50pf, TA = 2SoC
=
l&OV
V
15
2
45
-1
050
10
10
LOW POWER TTLICMOS INTERFACE
Logical "1" Input Voltage V INII)
54C, vee = 4 5V
74C, Vee = 4 7SV
Logical "0" Input Vorlage VINIOI
S4C, Vee = 4 5V
74C, Vee = 4 75V
Logical "1" Output Voltage VOUTO )
54C, Vee = 4 5V, 10 '" -lOOp,A
74C, Vee = 4 75V, 10 = -lOQp,A
Logical "0" Output Voltage V ouno)
54C, Vee "'45V, 10 = 360,uA
74C, Vee. = 4 7SV, 10 = 360,uA
Propagation Delay Time to a Logical "0" tpdO
or Logical "1" tpd1 from Clock to or Q
Vee = SOY, CL = 50 pF, TA = 25°C
a
Note 1: These deVices should not be connected under "Power On" conditions
8·18
V ee -1 S
24
175
50
400
160
CMOS
MM54C151/MM74C151 8 channel digital multiplexer
general description
The MM54C151/MM74C151 multiplexer is a
monolithic complementary MOS (CMOS) Integrated circuit constructed with Nand P-channel
enhancement transistors.
This data selector/multiplexer contains on·chlp
binary decoding. Two outputs provide true (out·
put Y) and complement (output W) data. A logical
"1" on the stroke input forces W to a logical "0"
and Y to a logical "1 ".
All Inputs are protected against electrostatic
effects.
features
• Supply voltage range
3V to 15V
• Tenth power TTL
compatible
•
High nOise Immunity
•
Low power
drive 2 LPTTL loads
0.45 Vee typ
50 nW typ
applications
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering
•
Computers
logic and connection diagrams
o,o----f-:::l=±::::::t-,_
o,o---i=J::j=::j:::::::j-,
Input Protection For All Inputs
0.
DATA
INPUTS
0,
0.
0.
Dual-I n-line Package
8-19
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C151
MM74C151
Storage Temperature
Package DISSipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec)
-0.3V to Vee +0.3V
_55°C to +125°C
O°C to +70°C
-65°C to +150°C
500 mW
3V to 15V
300°C
electrical characteristics
MiniMax limits apply across temperature range across otherwise specified
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage
V,Nlll
Vee = 50V
Vee = 10.0V
Logical "0" Input Voltage
V,NIOI
Vee = 5.0V
Vee= 100V
Logical "1" Output Voltage VOUTlll
Vee = 5.0V, '0 = -10pA
Vee = 10 OV. 10 = - 10pA
Logical "0" Output Voltage VOUTIOI
Vee = 5.0V, '0 = +10pA
Vee = 10.0V, 10 = +10pA
Logical 1/1" Input Current
I'NI1I
Vee = 15 OV, V ,N = 15V
Logical "0" Input Current
I'NIOI
Vee = 15 OV, V,N = OV
Supply Current
lee
Vee= 15.0V
V
V
3.5
8
15
2
45
9
V
V
V
V
05
1
V
V
1
pA
30
pA
pA
-1
005
pF
Input Capacitance
Any Input
Propagation Delay Time to a
Logical "0" or Logical "1" from
Vee= 50V,CL= 50pF, TA = 25°C
Vee= 100V, CL = 50pF, TA = 25°C
170
80
270
130
ns
ns
Propagation Delay Time to a
Logical "0" or Logical "1" from
Data to W
Vee = 5.0V, CL = 50 pF, T A = 25°C
Vee = 10.0V, CL = 50 pF, TA = 25°C
200
90
300
140
ns
ns
Propagation Delay Time to a
Logical "0" or Logical "1" from
Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee= 100V, CL = 50pF, TA = 25°e
240
110
360
170
ns
ns
5
Data to Y
Strobe or Data Select to Y
CMOS TO TENTH POWER
INTERFACE
Logical "1" Input Voltage
V,NI1I
54C, Vee = 4' 5V
74e, Vee ~ 4.75V
Logical "0" Input Voltage
V,NIOI
54C, Vee = 4 5V
74C, Vee = 4.75V
Logical "1" Output Voltage VOUTl1I
54C, Vee = 4.~V, 10 = -100pA
74C, Vee = 4.75V, 10=-100IlA
Logical "0" Output Voltage VOUTIOI
54C, Vee ~ 4 5V, 10 = 360 pA
74C, Vcc ~ 4.75V, '0 = 360pA
Propagation Delay Time to a
Logical "0" tpdO or a Logical "1"
tpdl from Data Input, to Y
Vee = 5.0V, CL = 50 pF, T A = 25°c
Note 1: This deVice should not be connected under power on conditions.
8-20
V
Vee - 1.5
0.8
24
V
V
04
200
320
V
ns
s::
s::UI
switching time waveforms
~
............
(')
OUTPUT (WI
VOC~
!lO%
UI
TTL to CMOS (t p dl & tpdOI
CMOS to CMOS (tpdl & tpdOI
OUTPUT (WI
50%
vocT:t15V
s::
s::
"(')
1 5V
~
...
DV
DV
f.p.t1
t"do
tpd'
tpdO
...
V'"
v"
OUTPUT(Yj
UI
OUTPUT(Y)
DV--~~~~----~-----+-J
4Ov---h,.=.......--------:,:::..:""<
DATA INPUT
DATASELEtT
STROM
DATA INPUT
15V
DATA SELECT
STROBE
'v
DV
tr.1t=2Dns
ac test circuit
V"
OUTPUT(W}
·~l
~CL=50PF
OUTPUT
(V)
GND
'1'CL=50 PF
"::"
truth table
OUTPUTS
INPUTS
DO
0,
02
03
04
05
06
07
Y
x
,
x
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
0
1
0
0
0
0
1
X
X
X
X
X
X
X
1
0
0
0
1
0
X
0
X
X
X
X
X
X
0
1
0
0
1
0
X
1
X
X
X
X
X
X
1
0
0
1
0
0
0
x
x
x
x
x
0
1
0
0
x
x
x
0
X
1
X
X
X
X
X
,
0
I
1
0
X
X
X
0
X
X
X
X
0
1
0
1
1
0
X
X
X
1
X
X
X
X
1
0
1
0
0
0
x
x
0
x
x
x
0
1
0
0
0
x
x
x
x
1
x
X
1
X
X
X
1
0
1
0
1
0
X
X
X
X
X
0
X
X
0
1
1
0
1
0
X
X
X
X
X
1
X
X
1
0
1
1
0
0
x
x
0
x
0
1
0
0
x
x
x
x
x
1
x
x
x
1
x
X
1
X
1
0
1
1
1
0
X
X
X
X
X
X
X
0
0
1
1
1
1
0
X
X
X
X
X
X
X
1
1
0
C
B
A
x
x
0
STROBE
W
,
1
0
8·21
CMOS
MM54C154/MM74C154 4-line to 16-line
decoder/demultiplexer
general description
The MM54C154/MM74C154 one of sixteen decoder IS a monolithic complementary MOS (CMOS)
Integrated circuit constructed with Nand P-channel
enhancement transistors. The device IS provided
with two strobe Inputs, both of wh Ich must be
In the logical "0" state for normal operation. If
either strobe Input IS In the logical "1" state, all
16 outputs will go to the logical "1" state.
• Tenth power TTL
compatible
drive 2 LPTTL
loads·
1V guaranteed
•
High noise margin
•
High nOise Immunity
•
Low power
045 Vcctyp
100JlW typ
applications
To use the product as a demultiplexer, one of the
strobe inputs serves as a data input terminal,
while the other strobe input must be maintained
in the logical "0" state. The information will then
be transmitted to the selected output as determined by the 4-line input address.
features
•
Supply voltage range
3V to 15V
•
Automotive
•
Data terminals
•
Instrumentation
•
Medical electronics
•
Alarm systems
•
Industrial electronics
•
Remote metering
• Computers
logic and connection diagrams
V"
INPUT PROTECTI ••
"RALLINPUTS
~AA~
!"--~
T. INTERNAL
CIRCUITRY
Dual-I n-Lone Package
OU1l'UTS
INPUTS
I.
11
12
13
14
OUTPUTS
"
8-22
TOP VIEW
absolute maximum ratings
-0.3V to Vcc +0.3V
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C154
MM74C154
Storage Temperature Range
Package Dissipation
Operating Range, Vcc
Lead Temperature (Soldering, 10 sec)
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
500mW
+3V to +15V
300°C
electrical characteristics
(Minimax limits apply across temperature range unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
CMOS TO CMOS
Logical "1" I.,put Voltage (V1Nu)1
Vee == 5V
Vee == lOV
Logical "0" Input Voltage
Vee = 5V
Vee = lOV
(VIN(O))
35
8
15
2
Logical "1" Output Voltage (V oUT (1}1
Vee" 5V, 10 " -10/lA
Vee" 10V. 10 "-10JIA
LogIcal "0" Output Voltage
Vee = 5V, 10 = +10,uA
Vee == lOV,I o == +101J. A
Logical "1" Input Current
(VOUT(O))
V
V
45
9
V
V
V
V
05
1
1
V
V
Vee = l5V, VIN
==
l5V
Logical "0" Input Current II'N{Q)1
Vcc=15V,
-='
OV
Supply Current (Icc)
Vee
Input CapacItance
Any Input
Propagation Delay to a logical "0" From
Any Input to Any Output (tPdO)
Vee - 5V, CL = 50 pF, TA = 2S"C
275
400
ns
(lIN(1))
Propclgatlon Delay to a Logical "0" From
=
VIN
-1
JIA
JIA
l5V
JIA
pF
5
Vee - 5V, CL
=-
50 pF. TA == 2S"C
275
400
ns
Propagation Delay to a L(JQlcaJ "1" From
Any Input to Any Output (t pd1 )
Vee
5V, CL
'"
50 pF, TA
Propagation Delay to a Logical "'" From
Gl or G2 to Any Output (tpd1)
Vee'" 5V, CL
'"
50 pF,
Gl or G2 to Any Output (tpdol
==
=;
25°C
265
400
ns
TA '"
25°C
265
400
ns
LOW POWER TTL/CMOS INTERFACE
Logical "1" Input Voltage (V IN (1))
54C
74C
Vee'" 4 5
Vee =475
Logical "0" Inpllt Voltage (V INIO ))
54C
74C
Vee:: 4 5
Vee ==475
Logical "1" Output Voltage (V OUTO ))
54C
74C
Vee" 4 5V, 10" -1ooJIA
Vee" 4 75V. 10 "-100/lA
Logical "0" Output Voltage (VO UT1QJ )
54C
74C
Vee 04 5V. 10 " 360JIA
Vee" 4 75V. 10 " 360JIA
V
Vee - 1 5
08
V
V
24
04
[;J
V
Note 1: This device should not be connected to cirCUits with the power on because high transient voltages may cause
permanent damage.
8·23
switching time waveforms
A.B.CORO~VCC
I
--j
ANY OUTPUT
I",
t=
t
-- I
----I
r-
I,,,,,
~
50%
_ _ _ _ _- '
G10AG2~O%
_
50%
OV
tpdO
Vee
Vee _ _ _ _ _,
50%
50%
ANY OUTPUT
~OV
1--- --
Vee
OV
tpdl
Vee
50%
OV
OV
t, "1 1 = 20 ns
Guaranteed Noise Margin as a
Function of Vee
15V
13.5
125
~
;
4.05
"
305
~
V 1N (0)
25
15
145
0.45
10V
450V
15V
Vee
truth table
INPUTS
Gl G2
x
8-24
OUTPUTS
0
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H.
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
==
"Don't Care" Condition
H
CMOS
MM54C157/MM74C157 quad 2-input multiplexer
general description
These multiplexers are monolithic complementary
MOS (CMOS) integrated circuits constructed with
Nand P channel enhancement transistors. They
consist of four 2-input multiplexers with a common select and enable inputs. When the enable
input is at logical "0" the four outputs assume
the values as selected from the inputs. When the
enable input is at logical "1" the outputs assume
logical "0." Select decoding is done mternally
resulting in a single select input only.
•
•
Supply voltage range
High nOise Immunity
drive 2 LPTTL
loads
applications
•
•
•
•
•
•
•
•
features
•
•
50 nW (typ)
Low power
Tenth power TTL compatible
3V to 15V
0.45 Vee typ
Automotive
Data termmals
Instrumentation
Medical electronics
Alarm systems
Industnal electronics
Remote metenng
Computers
schematic and connection diagrams
Dual-In-Line Package
SELECT
It
truth table
'«
Guaranteed Noise Margin as a
Function of
INPUTPROT£CTlON+rOINTERNAi
FOA ALL INPUTS
CIRCUITRY
15V
ENABLE
SELECT
A
B
OUTPUT Y
1
X
X
X
0
0
0
0
x
0
0
0
1
X
1
0
1
X
0
0
0
1
X
1
1
Vee
r::-=======:;--, 13.
12'
40'
30.
~~~15
145~
15
04'
450V
10V
10V
74Li Compatibility
I
8-25
absolute maximum ratings
Voltage at Any Pin (Note 1)
MM54C157
Operating Temperature
-0.3V to Vee to 0.3V
_55°C to 125°C
MM74C157
O°C to 70°C
_65°C to 150°C
Storage Temperature
Package Dissipation
Lead Temperature (Soldering. 10 sec)
500 nW
300°C
+3V to 15V
Operating Vee Range
electrical characteristics
MinIMax limits apply across temperature range unless otherwise specified
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage V 1N (1)
Vee = 5 OV
Vec = 100V
Logical "0" Input Voltage
Vee = 5 OV
Vee = 100V
VIN(O)
Logical "1" Output Voltage V OU T(1)
Vee=50V
Vee = 100V
Logical "0" Output Voltage VOUTIO)
Vee =50V
Vee = 100V
Logical "1" Input Current
IIN(l)
Vce = 150V
Logical "0" Input Current IINIO)
Vee = 150V
35
8
V
V
1.5
2.0
V
V
45
90
0.5
10
1.0
Supply Current Icc
Vee = lS0V
0.050
Input Capacitance
Any Input
5
Propagation Delay from Data to Output
(tpdo or tpdl )
Vee = 50V CL = 50 pF.
Vee = 100V CL ='50 pF,
=25' C
TA
= 25'C
Propagation Delay from Select to
Output (tPdO or tpdl )
Vee=SOV CL = SO pF, T A
Vee = 10 OV CL = SO pF, T A
Propagation Delay from Enable to
Vee = SOV CL = SO pF. T A
Vee = 10 OV CL = SO pF, T A
= 2S'C
= 2S'C
= 2S' C
=2S'C
Output (tpdo)
V
V
p.A
p.A
-10
TA
V
V
10
p.A
pF
150
70
250
110
ns
ns
180
80
300
130
ns
ns
180
80
300
130
ns
ns
CMOS TO TENTH POWER INTERFACE
Logical "'" Input Voltage V IN(1)
54C
74C
Vee =4 SV
Vee = 4 7SV
Logical "0" Input Voltage V'NIO)
54C
74C
Vee=4SV
Vee =47SV
Logical "1" Output Voltage V OUT(1 )
54C
74C
Vee = 4 SV, 10 = -100p.A
Vee =4 7SV, 10 = -100p.A
Logical "0" Output Voltage VOUTIO)
S4C
74C
Vee = 4.SV. 10 = 360 p.A
Vee = 4 7SV, 10 = 360 p.A
Propagation Delay from Select to
Output (tPdO or t pd1 )
Vee
= S OV
CL ~ SO pF,
TA
V
Vee - 1 S
08
= 2S'C
V
2.4
04
2S0
Note 1: ThiS device should not be connected to circuits with the power on because high tranSient voltage may cause
permanent damage.
8·26
V
V
ns
CMOS
MM54C160/MM74C160 decade counter
with asynchronous clear
MM54C161/MM74C161 binary counter
with asynchronous clear
MM54C162/MM74C162 decade counter
with synchronous clear
MM54C163/MM74C163 binary counter
with synchronous clear
general description
These (synchronous presettable upl counters are
monolithic complementary MOS (CMOSI integrated circuits constructed with Nand P channel
enhancement mode transistors. They feature an
Internal carry lookahead for fast counting schemes
and for cascading packages Without additional
gating.
Counting IS enabled when both count enable inputs are high. Input T is fed forward to also enable
the carry out. The carry output IS a positive pulse
with a duration approximately equal to the positive portion of QA and can be used to enable successive cascaded stages. Logic transitions at the en·
able P or T Inputs can occur when the clock is high
or low.
features
A low level at the load input disables counting and
causes the outputs to agree with the data input
after the next positive clock edge. The clear function for the C162 and C163 is synchronous and a
low level at the clear input sets all four outputs
low after the next positive clock edge. The clear
function for the C160 and C16l is asynchronous
and a low level at the clear input sets all four
outputs low regardless of the state of the clock.
•
High nOise margin
•
HIgh nOise Immunity
•
1V guaranteed
045 Vee typ
drIVes 2 LPTTL loads
Tenth power TTL
compatible
• Wide supply voltage range
3V to l5V
• Internal look·ahead for fast counting scemes
• Carry output for N-blt cascading
• Load control line
• Synchronously programmable
connection diagram
(For Logic Diagrams See Page 31
Dual-I n-Line Package
".
Ir--....-+~+--+--
connection diagram
truth table
Dual-In-Line Pack...-
Senal Inputs A and 8
INPUTS
OUTPUT
tn
to"
A
B
1
1
1
0
QA
1
1
0
0
0
0
0
0
8-31
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C164
MM74C164
Storage Temperature
Package DIssipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec)
--o.3V to Vee +O.3V
-55°C to +125°C
O°C to +70°C
--65°C to +150°C
500mW
3V to 15V
300°C
,
electrical characteristics
Min/max limits apply across temperature range' unless otherwise specified.
PARAMETER
CONDITIONS
MIN
Tvpl MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage V IN(l}
Vee = 50V
Vee = 10.0V
Logical "0" Input Voltage V INto )
Vee = SOV
Vee = 10.0V
Logical "1" Output Voltage V OUT (l)
Vee = SOV
Vee=100V
10 = -1OjlA
10 =-1OjlA
Logl,cal "0" Output Voltage
Vee = SOV
Vee = 10.0V
10=-10jlA
10 =-10jlA
Loglcal"1" Input CUrrent "Nil)
Vee = lS0V
Y'N = lSV
Logical "0" Input Current 'INtO)
,Vee = lS0V
VOUTtO)
35
8
V
V
15
2
Y'N = OV
4S
90
V
V
V
V
1
S
V
V
1
jlA
-1
jlA
OS
jlA
Supply Current Icc
Vee = lS0V
Input Capacitance
Any Input
Propagation Delay Time to a Logical "0" or
Logical "1" From Clock to Q
Vee "" SOV, CL = SO pF, TA = 2SoC
Vee = 100V, CL = SO pF, TA = 2SoC
230
90
310
120
ps
ns
Propagation Delay Time to a Logical "1" From
Clear to Q
Vee = S OV, CL = SO pF, T A = 2SoC
Vee = 10.0V, CL = SO pF, T A = 2SoC
280
110
380
lS0
ns
ns
Time Prior to Clock Pulse That Data Must be
Vee = 50V, CL = SO pF, TA = 2SoC
Vee = 10 OV, CL = SO'pF, TA '= 2SoC
110
30
Time After Clock Pulse That Data Must be
Held
Vee = S.OV, CL = 50 pF, T A = 2SoC
Vee =100V,C L =SOpF, TA'= 2SoC
0
0
ns
ns
MInimum Clock Pulse Width (tWI.. = tWH)
Vee = 50V, CL = SO pF, T" = 2SoC
Vee = 100V, CL = SO pF, TA = 2SoC
120
50
n,
ns
Minimum Clear P.ulse Width
Vee = SOY, CL = SO pF, TA = 2SoC
Vee = 10 OV, CL = SO pF, T A = 2SoC
lS0
55
n,
MaXimum Clock. Rise and Fall Time
Vee = 50V,C L =50pF,T A =2SoC
Vee = 10 OV, CL = SO pF, TA = 2SoC
1
130
ms
jlS
Present
tSETUP
SO
pF
S
,
ns
ns
ns
CMOS TO TENTH POWER INTERFACE
54C
74C
Vee =45V
Vee = 4 75V
54C
74C
Vee=4SV
V ee =47SV
Logical "1" Output Voltage VOlJT (1)
54C
74C
Vee = 4 5V, 10 = -100jlA
Vee = 4 7SV, 10 = -100 jlA
Logical "0" Output Voltage VOUT(O)
54C
74C
Vee = 4 SV. 10 = 360jlA
Vee = 4 7SV, 10 = 360jlA
Loglca'''l'' Input Voltage V 1N (1)
Logical "0" Input Vol~age V INIO )
';
V
8
V
!
Propagation Delay Time to a Logical "0" or
Logical "1" From Clock To Q
Note 1: These devices should not be connected under power on conditions.
8·32
V ee -15
24
V
4
320
V
ns
ac test circuit
INPUTS {
CLOCK
switching time waveforms
u
ClEAR-U
SERIAL [
INPUTS
A
.--1'-----.....
ClOCK
0.
0,
0,
OUTPUTS
________________________
____________________________
==.'.____________________--'
o,==~,~
~
o>==~,
0,
~
0" - - ,
~I----------------------------~
CLEAR
I
CLEAR
CMOS
'0 CMOS
TTL to CMOS
v,,----+-r.::;:;-----CLOCK
OV--_.11
OV----"'=I
DATA
DATA
ov ----+------
V,,----+-i----..
r----50"~
v" _ _ _ _._-----..
r-tpdO.--~
1.,.,0 - - -\ .
OIJ~------------- ----~
t, '
'f
<
20
OV
n~
8-33
typical applications
Guaranteed NOise Margin as a Function of
Vee
135
74C Compatibility
125
25
15
450V
10V
Vee
8-34
15V
illS
CMOS
MM54C173/MM74C173 TRI-STATE® quad 0 flip flop
general description
The MM54C173/MM74C173 TRI-STATE quad D
flip flop IS a monolithic complementary MOS
ICMOS) Integrated CirCUit constructed with N
and P-channel enhancement transistors The four
D type flip flops operate synchronously from a
common clock. The TRI-STATE output allows the
deVice to be used In bus organized systems. The
outputs are placed In the TRI·STATE mode when
either of the two output disable Pins are In the
logiC "1" level. The Input disable allows the flip
flop to rema In In their present states Without
dISrupting the clock. If either of the two Input
dISables are taken to a logiC "1" level, the Q
outputs are fed back to the Inputs and In thiS
manner the flip flops do not change state
Clearing IS enabled by taking the Input to a logiC
"1" level. Clocking occurs on the pOSItive going
transition.
features
•
Supply voltage range
3V to 15V
•
Drive 2 LPTTL
loads
Tenth power TTL
compatible
045 Vee typ
•
High nOise Immunity
•
Low power
•
Medium speed operation
•
High Impedance TRI·STATE
•
Input dISabled Without gating the clock
applications
•
Automotive
•
Data terminals
•
Instrumentation
•
Medical electronics
•
Alarm systems
•
Industrial electronics
•
Remote metering
•
Computers
logic and connection diagrams
DATA INPUT (
DISABlE
Dual·1 n·Line Package
INPUT
INPUT
INPUT
ABC
Vee
OUIPU1
OUTPUT
OISMLE DISABlE
OUTPUT OUWUT
A
~,
INPUT
0
OUTPUT
OUTPUT
C
0
DATA
INPUT
CP
OUTPUll
DISABLE
8·35
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C173
MM74C173
Storage Temperature
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec)
-{).3 to Vee +O.3V
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
500mW
+3V to +15V
300°C
electrical characteristics
Minimax limits apply across temperature range unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage V,N111
Vee = 5.0V
Vee = 10.0V
Logical "0" Input Voltage V ,NIO )
Vee = 5.0V
Vee = 10.0V
Logical "1" Output Voltage V OUT (1)
Vee = 5.0V
Vee = 1O.0V
"a" Output Voltage VaUTIO)
Vee = 5.0V
Vee = 10.0V
Logical
High Impedance State
V
V
V
V
9
.5
1
1
V
V
p.A
p.A
_
Va = 15V
Vee - 15V, Vo = OV
001
.001
p.A
I1A
Supply Current lee
Vee = 15V
Input Capacitance
Any Input
Propagation Delay Time to a Logical "0" (tpdo)
Vee = 5.0V, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
220
80
400
200
ri.
ns
DATA
Vee = 5.0V, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
40
15
80
30
ns
ns
Input Data Hold Time, tH DATA
Vee = 5.0V, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
a
a
Input Disable Setup Time, t5 DISS
Vee = 5.0V, CL = 50 pF, T A = 25'C
Vee = 10.0V, CL = 50 pF, T A = 25'C
100
35
Input Disable Hold Time, tH DISS
V ee '= 5.0V, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
a
a
or Logical "1" (t pd1
1 From Clock to Output
Input Data Setup Time, t5
001
10
5
p.A
pF
ns
ns
200
70
ns
ns
ns
ns
170
70
340
140
Vee = 5 OV, CL = SO pF, TA = 2S'C
Vee = 1O.0V, CL = 50 pF, TA = 2S'C
170
70
340
140
n,
ns
Vee = 5.0V, C L = SO pF, T A = 2S'C
Vee = 10.0V, CL = 50 pF, T A = 25'C
170
70
340
140
ns
ns
Propagation Delay From Clear to Output tpdR
Vee = S.OV, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, T A = 25'C
240
90
490
180
ns
MaXimum Clock Frequency
Vee = S.OV, CL = SO pF, TA = 2S'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
5
10
Minimum Clear Pulse Width
Vee = 5 OV, CL = SO pF, TA ~ 25'C
Vee = 10.aV, CL = 50 pE, TA = 2S'C
150
70
MaXimum Clock Rise and Fall Time
Vee = 5 OV, CL = 50 pF
Vee = 10.0V, CL = 50 pF
Delay From Output Disable to High Impedance
State (From Logical "1" or Logical
"a" Levell,
t iH • tOH
Delay From Output Disable to Logical "1"
Level, tHI (From High Impedance Statel
Delay From Output Disable to Logical "0"
Level, tHO (From High Impedance Statel
Vee = 5.0V, CL = 50 pF, TA = 25'C
Vee = 10.0V, CL = 50 pF, TA = 25'C
Note 1: These deVices should not be connected under "Power On" conditions.
8-36
4.5
-1
logical "0" Input Current IIN(O)
In
1.5
2
Vee = 15.0V
logical "1" Input Current 'IN(l)
Output Current
V
V
3.5
8
10
5
35
7
ns
ns
MHz
ns
p.s
p.s
electrical characteristics (con't)
"
CONDITIONS
PARAMETER
MIN
TYP
',:
MAX
UNITS
'LOW POWER TTL/CMOS INTERFACE
= 4 5V
Logical "I" Input Voltage V ,N (1)
54C, V'Ce
74C, >{Jce
Logical "0" Input Voltage V'NIO)
54C. Vee = 4 5V
74C, Vee = 4 7SV
Logical "I" Output Voltage V OUTllI
54C, Vee
74C, Vee
= 4 5V, 10 =-1QO!,A
= 4 75V, 10 =-100!,A
Logical "0" Output V?ltage VOUTIO)
54C, Vee
74C,.v ce
=
Propagation Delay Time to a Logical "0",
or Logical "I"
t"Ol
=
' V'
Vcc";1.5
475V
.8
V
"
4 5V, 10
=
V
·24
360!,A
4
= 4 75V, 10 = 360!,A
tpdO
500
From Clock
Ii
ns
truth table
Truth Table (Both Output Disables Low)
In
tn+1
DATA INPUT DISABLE
DATA
INPUT
OUTPUT
X
an
LogiC "1" on One or Both Inputs
LogiC "0" on Both Inputs
LogiC "0" on Both Inputs
1
1
'b
0
"
-:r
switching time waveforms
90.
CLEAR
DUTPUT
DISABLE
50%
10%
I
I
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
/1--1 Lt'-_____. .r
50%.¥\.5D%
:
,
1''---'---
--
I
5 0 % - 1 \ , 50%
~
150ISS
tSOISS·__
HO'SS
DATA
--
INPUT
I
i
50%
I
Is DATA
_
50% .r---\,90%
CLOCK
--t-----J.I.
",''''''
50%
tH'01SS
A,., l
J ~5D%
--t
I
~_~'"D'"
-l
r--'"DAOA
r--
c
50%
50r. I
511%
.
tf~~-tpd'~
...
50_%_ _ _ _ _ _ _ _
Is DATA
I
~
DATA
OUTPUT
I
r--
--J15~
----jtpdOk--
\~.
8·37
-CMOS
MM54C192/MM74C192 synchronQus
4-bit up/down decade counter
MM54C193/MM74C193 synchronous
4-bit up/dQw~ binary counter
general des.cription
counters also have carry and bbrrow outputs so
that they can be cascaded uSing no external
circuitry.
These up/down counters are monolithic complementary MOS (CMOS) Integrated CircUits. The
MM54C192 and MM74C192 are BCD counters.
While the MM54C193 and MM74C193 are binary
counters.
features
Countmg up and countmg down IS performed by
two count Inputs, one being held high while the
other IS clocked. The outputs change on the POSItive gOing transition of th IS clock.
These counters feature preset Inputs that are set
when load IS a logical "0" and a clear which forces
all outputs to "0" when It IS at logical "1." The
•
High nOise margin
1 V guaranteed
•
Tenth power
TTL compatible
drive 2 LPTTL
loads
3V to 15V
•
Wide supply range
•
Carry and borrow outputs for N-bit cascading
•
Asynchronous clear
•
High nOise Immunity
0.45 Vcc typ
connection diagram
Dual-In-Line Package
INPUTS
OUTPUTS
INPUTS
~~
OAATA
I"
CLEAR
"
"
2
J
BORROW CARRY
LOAD
12
II
\3
DATA
C
10
9
-
I
DATA
B
INPUT
DB
QA
__________
OUTPUTS
\
5
4
COUNT
DOWN
7
6
COUNT
Qc
UP
I
00
'---'
OUTPUTS
T'
GNO
INPUTS
TOPVIEW
cascading packages
Guaranteed Noise Margin as
LOAO---.---------.--------
A Function of
15V
Vee
...,...-======-;
1J5
125
U,
CLOCK
TO NEXT
STAGE
DOWN
406
30'
CLOCK
145
D.45
OUTPUTS
OUTPUTS
CLEAR--....- - - - - - - -...._ _ _ _ _ _ __
8-38
~~~~~~~~~
'------'----
4.50V
IOV
15V
25
15
absolute maximum ratings
Voltage at Any Pin (Note 1 )
Operating Temperature Range
MM54C192, MM54C193
MM74C192, MM74C193
Storage Temperature Range
Package DIssipation
Operating Vee Range
Lead Temperature (Soldenng, 10 sec)
-O,3V to Vee + O,3V
-55°C to +125°C
-70°C to +70°C
-65°C to +150°C
500mW
+3V to +15V
300°C
electrical characteristics
(Mm/max limits apply across temperature range unless otherwise speCified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO MOS
Logical "1" Input Voltage (V 1N (1»)
Logical "0" Input Voltage (V1N(0)1
Logical "1" Output Voltage (Vo UT (11)
Logical "0" Output Voltage (V OUTW)}
Vee = 5V
Vee
=
35
8
lOV
Vee = 5V
Vee = lOV
15
2
10 = -10pA
Vee = 10V, 10 = -10pA
Vee"" 5V,
=
5V,
Vee
=
lOV, 10
Vee = 15V, V'N = 15V
Logical "0" Input Current (lINW1)
Vee = 15V,
Supply Current (Icc)
Vee=15V
Input Capacitance
Any Input
Propagation Delay Time to Q From
Vee
tpdl )
45
9
VIN '"
OV
V
V
V
V
10 = +10j.lA
= +10.uA
Vee
Logical "1" Input Current (1IN(1»)
Count Up or Down (t pdO or
V
V
05
1
V
V
10
pA
-10
pA
50
pA
pF
5
C L = 50 pF, TA ~ 25°C
Vee = 10V, C L = 50 pF, TA =25"C
250
100
400
160
ns
ns
=
5V,
Propagation Delay Time to Borrow
From Count Down (t pdO 01 tPCl1 )
Vcc=5V,
CL = 50 pF, T A =25°C
Vee = 10V, C L =50pF, TA =25°C
120
50
200
80
ns
ns
Propagation Delay Time to Carry
Vee=5V, CL = 50 pF, TA = 25°C
Vee = lOY, CL = 50 pF, T A ::= 25°C
120
50
200
80
ns
ns
C L =50pF, TA = 25°C
CL = 50 pF, T A " 25 c C
100
30
160
50
ns
ns
CL =50pF, TA = 25"C
=: 50 pF
TA o 25°C
300
120
480
190
ns
ns
Vee
= 5V, CL = 50 pF, T A " 25 c C
Vee = 10V, CL = 50 pF, T A = 25°C
100
40
160
65
ns
ns
Vee
= 5V, CL = 50 pF, TA = 25°C
Vee = 10V, C L =50pF, TA = 25'C
300
120
480
190
ns
ns
Minimum Count Pulse Width
Vee" 5V, CL = 50 pF, TA = 25'C
Vee = lOY, CL = 50 pF, TA = 25'C
120
35
200
80
ns
ns
MaXimum Count Frequency
Vee °5V, CL = 50 pF, TA = 25°C
Vee = lOY, CL = 50 pF, TA =25°C
Count Rise and Fall Time
Vee = 5V, CL = 50 pF, TA = 25°C
Vee = lOY, CL = 50 pF, TA = 25°C
From Count Up (tpdo or t pd1 )
Time Prior to Load That Data
Vee
Must be Present (tSETUP)
Vee
= 5V.
= 10V.
Vee
= 5V,
Minimum Clear Pulse Width
Minimum Load Pulse Width
Propagation Delay Time to Q From
Load (tpdo or tpd1 )
Vee = 10V,
eL
25
6
MHz
MHz
4
10
15
5
ps
ps
CMOS TO TENTH POWER INTERFACE
Logical" 1" Input Voltage (V'N''')
54C Vee = 4 5V
74C Vee = 4 75V
Logical "0" Input Voltage (V'N(O»)
54C Vee=45V
74C Vee=475V
logical "1" Output Voltage (V OUT {1})
54C Vee=45V, 10 = -lOOpA
74C Vee = 4 75V, 10 = -lOOpA
logical "0" Output Voltage (VOUTIOI)
54C V ce =45V, 10 = 360!,A
74C Vee = 4 75V, 10 = 360pA
V
V
V ec -15
VeC 15
08
08
V
V
V
V
24
24
04
04
V
V
Note 1: This deVice should not be connected to circuits With the power on because high transient voltage may cause
permanent damage.
8-39
schematic diagrams
MM54C192 Synchronous 4-Bit Up/Down Decade Counter
VccU
r
n
GNO
MM54C193 Synchronous 4·Blt Up/Down Binary Counter
8·40
CMOS
MM54C195/MM74C195 4-bit register
general
~escription
The MM54C195/MM74C195 CMOS 4-bit r!glsters
feature parallel Inputs, parallel outputs, JK serial
inputs, shift/load control input, and a direct
overriding Clear. The following two modes of
operation are possible:
Parallel Load
Shift i.n direction Q A towards Q D
Parallel loading is accomplished by applying the
four bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flops and appears at the outputs after the
positive transition of the clock input. During
parallel loading, serial data flow is inhibited.
Serial shifting is accomplished synchronously when
the shift/load control Input is high. Serial data
for this mode IS entered at the JK inputs. These
Inputs allow the first stage to perform as a JK.
D or T-type flip flop as shown In the truth table.
features
• Medium speed operation
10 MHz (typ) With
10V supply and 50 pF load
• High nOise immunity
0.45 Vee (typ)
• Low power
• Tenth power TTL compatible
100 nW (typ)
drive 2 LPTTL
loads
• Supply voltage range
3V to 15V
• Synchronous parallel load
• Parallel inputs and outputs from each flip-flop
•
•
•
•
•
Direct overriding clear
J and K inputs to first stage
Complementary outputs from last stage
Positive edge triggered clocking
Diode clamped Inputs to protect against static
charge
applications
• Automotive
• Data terminals
• Instru mentation
• Medical electronics
• Alarm systems
• Remote metering
• Industrial electronics
• Computers
schematic and connection diagrams
SHIFTltDAD~
PlN8TOOND
PIN 16TO Vee
... ,
Dual-In-Lrne Package
8-41
absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C195
MM74C195
Storage Temperature
Package Dissipation
Lead Temperature (Soldering, 10 sec)
Operating Vee Range
-O.3V to Vee +O.3V
-55°C to +125°C
O°C to +70°C
_65°C to 150°C
500mW
300°C
+3V to +15V
e lectrica I cha racteristics
MaxiMin limits apply across temperature range unless otherwISe specified.
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
CMOS TO CMOS
logical "0 'OutfJut Voltage
V
V
15
2a
Vee "'SOV
Logical "0" Input Voltage V 1NI01
Logical "1" Output Voltage V OUl
30
80
Vee -'" 5 OV
Vee" lODV
Logical "1" Input Voltage V IN11 )
Vee
=
lODV
45
90
Vee = 5 OV
Vee c-: 10 OV
(1)
V
V
05
10
Vee =50V
VOUTWI
Vee = lOQV
Logical "1" Input Currpnt
IINI1)
Vee. =·150V
Logical "0" InlJut Current
IINIO)
Vee '" 15 OV
10
10
V
V
~A
MA
Supply Current Icc
Vee = 15 OV
0050
Input Capacitance
Any Input
50
Propagation Delay Time to a Logical
"0" tpdO or Lo~cal "1" tpdl from
V
V
20
MA
pF
Vcc=50V
Vee =-100V
C L " 50 pF, T A ." 25°C
25°C
C L -= 50 pF, T A
200
75
300
130
n,
n,
Propagation Delay Time to a Logical
"0" Flom Clear
Vee = 50V
Vec=lOOV
C L - 50 pF, TAo 25°C
CL 50 pF, T A " 25°C
100
50
300
130
n,
ns
Time Prior to Clock Pulse That Data
Must be Present tSETUP
Vee=-50V
Vee = 100V
C L =- 50 pF, T A "" 25°C
C L =- 50 pF, T A "25°C
60
15
100
50
ns
n,
Time Prior to Clock Pulse That
Shift/Load Must be Present tSETUP
Vee =50V
Vee -e 10 OV
CL ~- 50 pF, TA - 25°C
C L =- 50 pF, TA o 25()C
110
60
150
90
ns
ns
Time After Clock Pulse That Data
Must be Held
Vee
Vee
=
5 OV
10 OV
CL
CL
50pF, TA " 25"C
50 pF, T A =- 25"C
"-10
-5
a
a
Vee
Vee
-=
5 OV
100V
CL
CL
-
50 pF, T A
50 pF, T A
=
25°C
25°C
100
50
200
100
ns
n,
50 pF, T A
50 pF, TA
=
25()C
25°C
90
40
130
60
ns
ns
Clock to 0 or
Q
Minimum Clock Pulse Width
(tWL
tWH)
=
"0
-,
'"
=
"0
Minimum Clear Pulse Width
Vee = 5 OV
Vee =- 50V
CL
CL
-=
MaXimum Clock Rise and Fall Time
Vee = 5 OV
Vee = 100V
CL
CL
=
MaXimum Input Clock Frequency
Vee
Vee
C L =50pF, T A '" 25°C
C L =50pF, T A - 25°C
00,
=
5 OV
100V
=-
=-
50 pF
50 pF
50
20
25
5
ns
'"
~s
~,
MHz
MHz
5
100
LOW POWER TTL/CMOS INTERFACE
Logical "1" Input Voltage VI'\Hll
54C
74C
Vee=45V
Vee=-475V
Logical "0" Input Voltage V,NIOI
54C
74C
Vee=-45V
Vee = 4 75V
Logical "1" Output Voltage VOUTll)
54C
74C
Vee =45V, 10 =--lOOj.1A
Vee = 4 75V, 10 = -lODIlA
Logical "0" Output Voltage VOUTIO)
54C
74C
Vec
Vee
Propagation Delay Time to a Logical
"0" tpdO or LO~lcal "1" tpdl From
Clock to Q or Q
Vee =50V
CL
"
==
08
50pF, TA "25°C
V
V
24
4 5V, ID" 360MA
4 75V, 10 == 360 j.1A
Note 1: These deVices should not be connected under power on conditions.
8·42
V
Vee-1 5
04
250
V
ns
s:
s:U'1
switching time waveforms
~
(")
~
TTL to CMOS
CMOS to CMOS
CD
U'1
........
s:
s:
4V
~
OV
~
(")
40V
Vee
~
CD
U'1
DATA
OV
OV
Vee
40V
DATA
OV
OV
Vee
Oora.
ov
Vee
norO
ov
t, '" t f
'"
20 ns
tr eo tf"
20 ns
truth table
INPUTS AT tn
OUTPUTS AT tn+1
J
K
QA
QB
QC
QD
QD
L
H
QAn
QAn
QBn
Q Cn
Q cn
L
L
L
QAn
QBn
Q Cn
Q Cn
H
H
H
QAn
QBn
Q Cn
Q Cn
QAn
QAn
QBn
Q Cn
H
-
L
-
-
-
Q Cn
Note: H = HIGH LEVEL, L = LOW LEVEL
tn = bit time before clock pulse
tn+1
=
btt time after clock pulse
QAn = State of QA at tn
Guaranteed nOise Margin as
a Function of
Vee
15V
13'
12'
40'
'"
LV~'~'~IOI~~~~~~~~
145 [;;
2'
15
045 L -_ _--"----_ _- '
450V
lOV
15V
8-43
illS
:I
r+
CD
...
....
Interface Circuits
I»
(')
CD
REFERENCE
n
The following table references all Physical DimenSion Drawings for the devices in this section. For Order
Numbers. s~e below.' Refer to the alpha·numerical Index at the front of this catalog for complete deVice
title and function. Packages (pages I thru VI) are In the back of the catalog.
(')
DATA SHEETS
Devices
Pg.
DHOO06
DHOO06C
DHOO08
DHOO08C
DHOOll
DHOOllC
DHOOllCN
DHOO16CN
DHOO17CN
DHOO18CN
DH0028C
DHOO28CN
DH0034
DHOO34C
DHOO35
DH0035C
DH3467C
DH3725C
LH2111
LH2211
LH2311
LM106
LM206
LM306
LMll1
LM211
LM311
LM350
LM710
LM710C
LM711
LM711C
LM1414
LM1514
LM1488
LM1489.A
LM5520
LM7520
LM5521
LM7521
LM5522
LM7522
LM5523
LM7523
LM5524
LM7524
LM5525
LM7525
LM5528
LM7528
LM5529
LM7529
LM5534
LM7534
9·1
9·1
9·4
9·4
9·7
9·1
9·7
9·10
9·10
9·10
9·13
9·13
9·15
9·15
9·18
9·18
9·20
9·22
9·24
9-24
9-24
9-26
9·26
9·28
9-30
9·30
9-35
9-40
9-42
9·44
9-46
9-48
9-55
9-55
9·50
9-53
9-58
9-58
9-58
9-58
9-61
9-61
9·61
9-61
9-63
9-63
9·63
9-63
9·65
9-65
9·65
9-65
9·67
9·67
PACKAGES
Molded DIP (N)
Fig.
Pg.
2
II
2
II
2
2
2
2
2
2
2
II
II
II
II
II
II
II
Cavity DIP (D)(J)
Flat Pack (F )(W)
Fig.
Fig.
11
11
3
3
Pg.
IV
IV
Type
Pg.
Type
J
J
Metal Can (G)(H)
Fig.
Pg.
Type
21
21
21
21
21
21
21
V
V
V
V
V
V
V
H
H
H
H
H
H
H
21
21
21
21
24
24
V
V
V
V
VI
VI
H
H
H
H
G
G
20
20
20
20
20
20
V
V
V
V
V
V
H
H
H
H
H
H
20
23
22
23
V
VI
V
VI
H
H
H
H
WAVE·
FORMS
Fig.
Pg.
...
C
r+
III
TEST
CIRCUITS
Fig.
Pg.
II
II
9
9
9
3
3
1
3
II
II
II
II
3
3
II
II
5
II
5
II
5
II
5
II
5
II
5
II
5
II
5
II
5
II
8
8
8
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
III
III
III
III
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
D
D
D
D
D
D
16
16
16
15
V
V
V
IV
F
F
F
F
14
14
14
IV
IV
IV
F
F
F
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
'Order Numbers: use DeVice No. suffixed with package letter. i.e. DHOOO6H.
9-i
...
1/1
.u
::::s
fJ
Q)
fJ
.
....ca
...
Q)
I:
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
LM5535
LM7535
LM5538
LM7538
LM5539
LM7539
LM75450A
LM75451A
LM75452
LM75453
LM75454
MHOO07
MHOO07C
MHOO09
MHOO09C
MHOO12
MHOO12C
MHOO13
MHOO13C
MH0025
MH0025C
MH0026
MH0026C
MH0027C
MH8808
9-ii
Pg9·67
9-67
9-69
9-69
9-69
9-69
9-40
9-71
9-71
9-71
9-73
9-75
9-75
9-77
9-77
9-79
9-79
9-81
9-81
9-85
9-85
9-88
9-88
9-97
9-99
F,g_
Pg-
5
II
5
II
5
3
1
1
1
1
II
II
II
II
II
II
1
\I
1
1
5
II
\I
\I
Cavity DIP (D)(J)
Flat Pack (F) (W)
Metal Can (G)(H)
FIg
F,g_
F,g_
Pg.
Type
22
22
24
24
24
24
24
24
20
20
24
20
V
V
V
V
VI
VI
VI
VI
VI
V
VI
V
H
H
12
12
12
12
12
12
Pg
IV
IV
IV
IV
IV
IV
Type
Pg-
Type
J
J
J
J
J
J
G
G
G
G
G
G
H
H
G
H
WAVEFORMS
FIg.
Pg.
TEST
CIRCUITS
FIg.
Pg.
c
::z:::
o
o
o
en
......
c
::z:::
o
o
o
en
Interface Circuits
DH0006/DH0006C*current driver
general description
n
there IS less likelihood of false turn·on due to an
inadvertent short In the drive line.
The DH0006/DH0006C IS an Integrated high
voltage, high current driver designed to accept
standard DTL or TTL logic levels and drive
a load of up to 400 mA at 28 volts. AND Inputs
are provided along with an Expander connection,
should additional gating be required The addition
of an external capacitor provides control of
the rISe and fall times of the output in order to
features
• Operation from a Single +10V to +45V Power
Supply.
decrease cold lamp surges or to mmlml7e electro-
magnetic Interference If long lines are driven
• Low Standby Power Dissipation of only 35 mW
for 28V Power Supply
Since one side of the load is normally grounded,
• 1.5A, 50 ms, Pulse Current Capability.
'Prevlously called NH0006/NH0006C
schematic and connection diagrams
Metal Can Package
OUTPUT
RESPONSE
TIME
CONTROL
........- -....~---........- ........-+-ov"
NC
"-"'-0
TOP VIEW
OUTPUT
Dual·1 n-Line Package
INPUT
10
INPUT
EXPANDER
+-_-,
OUTPUT
INPUT _ _
INPUT
C } RESPONSE
TIME
INPUT
B
INPUT
CONTROL
' A . - -. . .---4....------oGROIJNO
GROUND
INPUT
_--'+---' L-_ _r __
INPUT
typical applications
lamp Dnver with Expanded Inputs
Relay Dnver
V"
+28V
OUTPUT
OTl/TTl {
lOGIC
INPUTS
311
LAMPS
- - - L -_ _A
OTLITTl
EXPANDER INPUT
RELAY
COIL
LOGIC
INPUTS
, - ~USH TO
lTEST
9-1
(.)
U)
o
o
o
absolute maximum ratings
Peak Power Supply Voltage (for 0.1 sec)
Continuous Supply Voltage
Input Voltage
Input Extender Current
Peak Output Current (50 ms On/1 sec Off)
Operating Temperature
DH0006
DH0006C. DH0006CN
Storage Temperature
:J:
C
.......
U)
o
o
o
:J:
C
electrical characteristics
PARAMETER
60V
45V
5.5V
5.0mA
1.5A
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
(Note 1)
CONDITIONS
MIN
Logical "1" Input Voltage
Vee = 45V to 10V
Logical "0" Input Voltage
Vee = 45V to 10V
Logical "1" Output Voltage
Vee = 28V. V ,N = 2.0V. lOUT = 400 mA
Logical "0" Output Voltage
TYP
(Note 2)
MAX
2.0
V
0.8
26.5
Logical "1" Output Voltage
Vee = 10V. V ,N = 2.0V. lOUT = 150 mA
Logical "0" Input Current
Vee = 45V. V ,N = .4V
Logical ''1'' Input Current
Vee = 45V. V ,N = 2.4V
27.0
8.8
0.5
Vee = 45V. V ,N = 5.5V
"Off" Power Supply Current
Vee = 45V. V ,N = 0.8V
.01
-1.0
mA
5.0
}1A
100
1.6
V
V
92
-0.8
V
V
.001
Vee =45V. V rN =0.8V"R L = 1K
UNITS
}1A
2.0
mA
8
mA
"On" Power Supply Current
Vee = 45V. V ,N = 2 OV. lOUT = 0 mA
Rise Time
Vee = 28V. RL = 82Q
0.10
}1S
Fall Time
Vee = 28V. RL = 82Q
0.8
}1S
Ton
Vee = 28V. RL = 82Q
0.26
}1S
Toff
Vee = 28V. RL = 82Q
2.2
}1S
Note 1: Unless otherWise specified, limits shown apply from -55°C to 125°C for DH0006 and OoC to
70°C for DH0006C.
Note 2: TYPical values are for 25°C ambient
Note 3. Power ratings for the TO-5 based on a maximum Junction temperature of +175°C and a ¢JA
of 210°ClW
Note 4: Power rating for the DH0006CN Molded DIP based on a maximum Junction temperature of
+150 o C and a thermal resistance of 175°C/W when mounted
In
a standard DIP socket
Note 5: Power rating for the DH0006CN Molded DIP based on a maximum Junction temperature of
+150 o C and a thermal resistance of 150°C/W when mounted on a 1/16 Inch thick, epoxy-glass board
with ten 0 03 Inch Wide 2 ounce copper conductors
switching time waveforms
--,.t:::......::J"-
90%--t+----'H-~
(I
PULSE
INPUT
!iO%,---tt----ti---
to%
9-2
C
::I:
0
0
0
typical performance
Maximum Continuous Output
Current For TO-S
Maximum Continuous Output
vs Temperature
Current For Molded DIP
50
~
40
w
w
'"~
>
~
40
~>
'"~
~
30
Q
Q
~
30
Q
20
~
;:
~
~
~
~
20
::I:
22
~
~
en
.......
C
Input Threshold Voltage
~
~
0
0
0
20
18
en
n
16
14
1.2
GUARANTEED LOGICAL
"0" INPUT VOLTAGE MAX
10
08
06
200
400
600
800
MAXIMUM CONTINUOUS OUTPUT CURRENT (rnA)
200
Logical "0" I nput Current
j
25
"....
.!
~
+25°C
i<
_55°C,~
~ ~ I...;:: +12S"'C
.....:==::::: ~
800
~
600
5 400
...
~ 200
~ =---
_55°~~
15
P
~
~
1.0
~
05
~ P"
~
15 100 125
In r;;
I--
'l
I :'Y"
+25°~~
,/
k:;: ~
50
"ON" Supply Current Dram
/.
B'OOD
F
0
AM81ENT TEMPERATURE (OC)
"OFF" Supply Current Drain
~ 1200
~
-50 -25
800
20
1400
....
600
MAXIMUM CONTINUOUS OUTPUT CURRENT (rnA)
1600
....
400
V
~
?' ....c .....
+125"C-
+125°C
L:~ ' /
+2S C
Q
leV"
~
~
~~
o
10
30
20
50
40
10
Turn On And Rise Time
-
....
200
;::
3.0
~
'"
I
20
,;-
;::
RISE TIME
100
Vee =2aV
RL "6aU
CL " 10 pF
VIN =l.GV PULSE
tf::;;lDns
Vee =28V
RL ""6an
CL = 10pF
VIN = 3 OV PULSE
tr '::;;10ns-
!
~
10
I
o
o
-75 -50 -25
0
25
50
15 100 125
-15 -50 -25
TEMPERATURE (OC)
....
~
a:
B
....
~
~
5
1.2
.8
.,w
.6
;;:
.4
"
.2
>
l}'W
1.0
Q
:5
I
T~' j25°~/ ,
o
~
If.
-
20 ' - -
5
10
1ms"ON"
100 ms "OFF"
30
~
Te=25"C
....
~
'\ U
Tr-ri
Q
30
12
llr-I~I'r\,~'~-b~~~~-;
10~1~1+-~~~~~~~~~
091-:~"":""'Y
08
1-""F7'r:....F-t-
01~~~~~~~~~~
200
15 100 125
40
SUPPLY VOLTAGE, Vee, (V)
50
400
800
600
1000
OUTPUT CURRENT. 1106• (mA)
Turn On Control
".,J "'
~
20
~
-
1•• 11"'
~
"PULSE CONDITION
20
16r-~~,--r-r~~~r-~
40
20
10
-
Vee = 2aV
Rl "'68n
TA =25°C
~
\
C, -
o.F
o
50
50
13
I
l. l ~=
I
25
40
15
14
--b~~
~~~
~
i.l.~
~
1_
~
0
30
Output Saturation Voltage
~
Turn Off Control
4.0
1.4
I
20
SUPPLY VOLTAGE (V)
TEMPERATURE ('C)
Available Output Current
2.0
1.8
16
10
50
Turn Off and Fall Time
4.0
300 I-- TutoL1JE
5
40
SUPPLY VOLTAGE (V)
400
~
30
20
SUPPLY VOLTAGE (V)
..........
"
Cl
~
= rOPF
F" 300
100
TIME
(~,)
5
e
~
\C, . . . .
50
C, ·300.F
30
Q
Y
C,'O
20
10
.£. :,......
CF '" 680pF
~I
Vee'" 28V
R, ·6an
T.· 25"C
Kj80.F
pF
150
200
250
Cl
20
40
60
"
10pF
8.0
10
TIME (",)
9-3
(.)
co
o
o
o
Interface Circuits
J:
C
.........
CO
DH0008/DH 0008C*
high voltage, high current driver
J:
C
general description
o
o
o
The DHOOOS/DHOOOSC IS an Integrated high voltage, high current driver, deSigned to accept standard DTL or TTL Input levels and provide a pulsed
load of up to 3A from a continuous supply voltage
up to 45V. AND Inputs are provided with an EXPANDER connection, should additional gating be
required.
circuit also requires only one power supply for
circu It fu nctlonal operation.
The DHOOOS is available In a lO-pln TO-5 package;
the DHOOOSC IS also available In a lO-pln TO-5, In
addition to a 10-lead molded dual-In-Ilne package.
features
Since one side of the load is normally grounded,
there IS less likelihood of false turn-on due to an
Inadvertent short In the drive line.
• Operation from a Single + 1OV to +45V Power
Supply.
•
The high pulse current capability makes the
DHOOOS/DHOOOSC ideal for driVing nonlinear
resistive loads such as Incandescent lamps. The
*Prevlously called NHOOOS/NHOOOSC
Low Standby Power DISSipation of only 35 mW
for 2SV Power Supply.
• 3.0A, 50 ms, Pulse Current Capability.
schematic and connection diagrams
Metal Can Package
RISE AND
FAll
RESPONSE CONTROL
TIME
.----.....--+--4~-....- ....>-2, Y'N = 5.0V
0.2
Fall Time
Vee = 2SV, RL = 39>2, Y'N = 5.0V
3.0
fls
TON
Vee=2BV,RL=39>2,V'N=50V
004
flS
TOFF
Vee = 2SV, RL = 39>2, Y'N = 5.0V
7.0
flS
Note 1· Unless otherWise specified limits shown apply from _55°C to 125°C for
70°C for DH0008C.
o H0008 and OoC
20
mA
fls
to
Note 2: TYPical values are 25°C ambient
Note 3: Power rattngs for the TO-5 based on a maximum Junction temperature of +175°C and a1> JA
of 210oC/w
Note 4: Power ratings for the DH0008CN Molded DIP based on a maximum Junction temperature of
150°C and a thermal resistance of 150°C/w when mounted In a standard 01 P socket
Note 5: Power ratings for the DH0008CN Molded DIP based on a maximum Junction temperature of
150°C and a thermal resistance of 115°C/w when mounted on a 1/16 Inch thick, epoxy-glass board
with ten 003 Inch Wide 2 ounce copper conductors_
switching time waveforms
-.. ,t::...:J" I+-
90%--++----'H-A PULSE \
(I INPUT I,
50%--hf----\t---
9·5
(,)
ex)
o
o
o
typical performance
::r:
o
......
Maximum Continuous Output
Maximum Continuous Output
Current for Molded DIP
Current for TO-5 Package
Available Output Current
50
ex)
o
o
o
5:
....
~
::r:
o
I"
40
w
;'"
....
lO
Q
>
l!:
§:
>
~
400
200
20
20
11/
1.2
:5
;;:
OB
>
'"
0.4
I If
Tc--55 °C
;
~
1.6
c
14
~
1.2f-+--t-t---t--f-+""t...::'1
a:
%
~!:
"
!:
P
~
;:l
I-+--t-+--+-I-+"-t--i
0.6 1--'--'-_'--'---'---'_-'---'
-50 -25 0 25 50 15 100 125
1 .B .9 10
....
il:
~
1.0
O.B
j
....~
Q
I-
OUTPUT CURRENT (AI
~
1200
1000
+25°C
BOO
..
600
400
200
~
-55'~~
15
P
....
~
c:c:
S
~~
1.0
~ po
~
~
05
~
!/
10
V...
+125°C
~
10.0
~
>=
B.O
V1N = 3.0V PULSE
I
",
20 ~~
10
I I I I
f---tlr--lt--P-..t-
"
11K
100
TIME 1",1
9·6
150
200
250
o
2
.....J-t-T
, '\ fALL TIME I
-25
+25
4
6
RL =39H
CL =10pF
TA
600
]
=
25 C
+125
500
~
400
;:::::
300
R, • 3911
I
I
i-'
TURN ON TIME V
I
200
RISE TIME"
Q
B 10 12 14 16 lB
TIME 1",1
+15
CL =10pF
V1N '" 3.0V PULSE
t, <; 10 ns
100
I
RF =51 H2
I I
liME
Vee = 28V
700
r- f -
I-
f-.~~
~~ .",,~ _Vee =28V
f-1 ~.v,"';;-
-
iff
TEMPERATURE rCI
I
r-
30 f---j---+--+
50
-75
50
Ti RN
./
/'
'/
Turn ON and Rise Time
T, = aprOXlmatjly 10 nS
30
10
40
TUrn OFF Control
r-
50
j'"
tf~10ns
6.0
SUPPL Y VOLTAGE IVI
Turn ON Control
40
CL =10pF
o
SUPPL Y VOLTAGE (VI
30
20
Vee = 28V
RL = 3951
14.0
12.0
+25°C
30
+125°C
~ ::0-'"
Turn OFF and Fall Tunes
4.0
20
...o=~ ~ reo:
r<
t:: ~
160
2.0
10
~
SUPPL Y VOLTAGE IVI
~'"
P
-55'CI~
o
OFF Supply Current Drain
2.0
~
50
1400
AMBIENTTEMPERATURE I'CI
ON Supply Current Drain
40
Logical "0" Input Current
2.0 I-+"-+-+--+-I-+-+~
1B
lO
1600
w
'"
20
SUPPL Y VOL TAGE. Vee. (VI
I"put Threshold Voltage
vs Temperature
t----tr+.."....---+
PULSE CONOI.T~
1 MS"ON"
100 MS "Ofr"
I I
I I
10
~
20
If
Te' 25°CI
16
.,w
2.2
.5 .6
I I
2B T ~1~oC
ell
2.4
MAXIMUM CONTINUOUS OUTPUT CURRENT (mAl
Output Saturation Voltage
3 .4
IJ
l.2
BOO
600
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
1 .2
40
l.6
-50 -25
0
+25 +50 +75 +100 +125
TEMPERATURE rCI
C
::t
o
o
Interface Circuits
......
.....
C
::t
o
......o
n
.....
c
DHOOll*(SH2001)
DHOOllC*(SH2002)
DH 00llCN*(SH2002P)
::t
o
o
...
n
high voltage high current drivers
z
general description
Applications Include driving lamps, relays, cores,
and other devices requiring several hundred milliamp currents at voltages up to 40V. Logic flexibility is provided through a 4-input NAND gate, a
NOR input and an input which bypasses the gating
and connects the base of the output transistor.
The DHOOll high voltage, high current driver
family consists of hybrid integrated circuits which
provide a wide range of variations in temperature
range, package, and output current drive capability. A summary of the variations is listed below.
*Prevlously called NHOOll, NHOOll C, NHOOll CN
logic diagram
Vee
10
ordering information
NSC DESIGNATION
SH DESIGNATION
PACKAGE
TEMPERATURE AANGE
~55°C to
+ 12SoC
OUTPUT CURRENT
CAPABILITY
DHQ011H
SH2001
TO 100
DHOO11CH
SH2002
TO 100
aOc to +70°C
150 rnA
OHOO11CN
SH2002 P
Epoxy "8" D1P
aOc to +70°C
150mA
250 rnA
9-7
z
(J
..-
absolute maximum ratings
o
o
:c
8V
VCC
Collector Voltage (Output)
40V
I nput Reverse Current
1.0mA
Power Dissipation
800mW
_55°C to +125°C
Operating Temperature Range DH0011
DoC to +70°C
DH0011C/DH0011CN
_65°C to 150°C
Storage Temperature
o
.......
(,)
..-
o
o
:c
o
.......
..-
electrical characteristics
o
o
:c
o
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
1
V IH
V IH
V IH
V IH
GND
2
V IL
GND
3
V IL
GND
TEST NO.
4
V IL
5
V IL
PIN 6
PIN 7
PIN 8
GND
IOL1
GND
IOL1
PIN 9
PIN 10
SENSE
V CCL
Va
VOL
V CCL
V CCL
Va
VOL
IOL2
V6
V OL2
GND
IOL2
V CCL
V6
V OL2
GND
IOL2
V CCL
V6
V OL2
V CCL
V6
V OL2
V CCL
V6
V OL2
6
V IL
GND
IOL2
7
GND
GND
IOL2
V IL
V IH
MIN
8
VR
GND
GND
GND
GND
V CCH
I,
IR
9
GND
VR
GND
GND
GND
V CCH
12
IR
10
GND
GND
VR
GND
GND
V CCH
13
IR
11
GND
GND
GND
VR
GND
V CCH
14
IR
V CCH
19
IR
13
VF
VR
VR
VR
GND
V CCH
I,
-IF
14
VR
VR
VF
VR
VR
VF
VR
VR
GND
V CCH
12
-IF
15
GND
V CCH
13
-IF
16
VR
VR
VR
VF
GND
V CCH
14
-IF
GND
GND
V CCH
19
V CCL
V6
V CCL
18
lox
V PD
1'0
IpDH
1'0
12
GND
17
18
19
GND
20
21
GND
VR
VF
GND
GND
GND
GND
GND
GND
Vox
-IF
V OH
GND
V MAX
22*
GND
V PD
tON
23*
GND
V PD
tOFF
I MAX
*See Test Circuits and Waveforms on Page 4
forcing functions
PARAMETER
(Note 1) DH0011
-55°C
+25°C
+125°C
UNITS
V CCL
4.5
4.5
4.5
V
V CCH
5.5
5.5
5.5
V
V PD
5.0
V
V MAX
8.0
V
V IL
1.4
1.1
0.8
V
V IH
2.1
1.9
1.7
V
VR
4.0
4.0
4.0
V
VF
0.0
0.0
0.0
V
lOLl
250
250
250
IOL2
8.0
8.0
7.5
Vox
40.0
40.0
40.0
Note 1: Temperature Range _55°C to +125°C
9·8
MAX
mA
mA
V
C
:::t
forcing functions
O°C
PARAMETER
+25°C
+70°C
UNITS
V CCL
5.00
5.0
5.0
V
V CCH
5.00
5.0
5.0
V
V PD
V MAX
5.0
V
8.0
V
V ,L
1.20
1.1
V ,H
2.00
1.9
1.8
V
VR
4.00
4.0
4.0
V
VF
.95
0.45
0.45
0.5
8.0
8.0
7.5
mA
40.00
40.0
40.0
V
(")
"C
:::t
o
o
+125°C
MAX
UNITS
( ")
Z
(Note 1) DHOOll
PARAMETER
MIN
_55°C
MAX
+25°C
MIN
MAX
MIN
V OL1
0.45
0.4
0.45
V
V OL2
0.45
0.4
0.45
V
5.0
JlA
mA
V OH
V
1.80
2.00
2.20
2.0
IR
-IF
1.60
1.6
1.5
200
5.0
30.6
JlA
mA
29.6
mA
lox
IpDH
I MAX
tON
160
ns
tOFF
220
ns
(Note 2) DHOOllC, DHOOllCN
O°C
+25°C
MAX
MIN
V OL1
V OL2
MIN
+70°C
MAX
MIN
0.45
0.5
V
0.45
0.45
0.5
V
10.0
JlA
mA
1.95
1.85
V
5.0
IR
-IF
UNITS
MAX
0.45
2.05
V OH
o
o
V
IOL2
PARAMETER
C
:::t
mA
Vox
test limits
"-
V
150
150
150
IOL1
test limits
o
o
(Note 2) DHOOllC, DHOOllCN
1.4
1.40
1.35
5.0
lox
IpDH
I MAX
200
30.6
JlA
mA
34.0
mA
Note 1: Temperature Range -55°C to +125O C
Note 2: Temperature Range OoC to +70 O C
switching time test circuit
c
PIN 10
PULSE
GEN
fRED
=
~
50V
.,
Vee = 5V
C~".F·.'.'NG
~
100 kHz
DUTY CYCLE
=
50%
PIN 5, PIN 1 GNO
±
Typical Switchmg Times
OUTPUT
-=-
CAP
200
!
~
switching time waveforms
'50
~
w"
100
w·
50
INPUT
~
"
"
."
"
1..-,"..
"
\"~""~ "
T'
-so°c
25°C
125°C
TEMPERATURE (OC)
9·9
z
(.)
...
00
Interface Ci rcuits
o
o
::I:
C
Z
...o,...
(.)
DH0016CN*
D H 0017CN*(SH2200P)
DH0018CN*
o
::I:
C
Z
(.)
...
high voltage high current drivers
CD
o
o
::I:
C
general description
withstanding voltages up to 100V. Logic flexi·
bility is provided through a 4·input NAND gate, a
NOR input and an input which bypasses the gating
and connects to the base of the output transistor.
This high-voltage, high-current driver family consists of hybrid integrated circuits which provide a
wide range of output currents and output voltages.
Applications include driving lamps, relays, cores,
and other devices requiring up to 500 mA and
'Previously called NH0016CN, NH0017CN, NH0018CN
logic diagram
Vee
10
ordering information
NSC DESIGNATION SH DESIGNATION
PACKAGE
OUTPUT CHARACTERISTICS
Maximum Standoff
Voltage
9·10
Current
DHOO16CN
N/A
Epoxy "8" DIP
70V
250mA
DHOO17CN
SH2200P
Epoxy "8" DIP
50V
500mA
DHOO18CN
N/A
Epoxy "8" DIP
100V
500mA
o
:::l:
o
o
absolute maximum ratings
~
8V
8V
70V
DHOO16CN
50V
DHOO17CN
100V
DHOO18CN
1.0A
DHOO16CN
Output Surge Current
2.0A
DH0017CN & DHOO18CN
Power Dissipation
455mW
O°C to +70°C
Operating Temperature Range
_65°C to +150°C
Storage Temperature
0)
Vee
I nput Voltage
Collector Voltage
n
2
o
:::l:
o
o
.....
n
~
2
o
electrical characteristics
:::l:
TEST
PIN 1
NO.
2
V IH
3
V IL
4
PIN 2
PIN 3
PIN 4
V IH
V IH
V IH
V IL
5
V IL
6
7
V IL
\IlL
8
V IL
9
V IL
PIN 5 PIN 6
PIN 7
PIN 8
GND
GND
lOLl
GND
GND
lOLl
GND
GND
GND
GND
PIN 9
PIN 10
SENSE
MAX
o
o
CD
LIMITS
MIN
Vee
Vs
VaLl
V IL
Vee
Vs
VaLl
lOLl
V IL
Vee
Vs
VaLl
GND
lOLl
V IL
Vee
Vs
VaLl
GND
lOLl
V IL
Vee
Vs
VaLl
GND
IOL2
Vee
V6
V OL2
GND
IOL2
Vee
V6
GND
IOL2
Vee
V6
V OL2
V OL2
10
V IL
Gt-JD
IOL2
11
GND
GND
IOL2
V IH
Vee
V6
V OL2
Vee
V6
V OL2
IR
12
VR
GND
GND
GND
GND
Vee
11
13
GND
VR
GND
GND
GND
Vee
12
IR
14
GND
GND
VR
GND
GND
Vee
13
IR
15
GND
GND
GND
VR
GND
16
GND
VR
Vee
14
IR
Vee
19
IR
17
VF
VR
VR
VR
GND
Vee
11
-IF
18
VR
VF
VR
VR
GND
Vee
12
-IF
19
VR
VR
VF
VR
GND
Vee
13
-IF
20
VR
VR
VR
VF
GND
Vee
14
-IF
GND
GND
Vee
19
Vee
V6
Vee
V PO
Is
110
110
21
22
23
GND
GND
GND
24
25
VF
GND
IOL3
GND
Vox
GND
GND
GND
GND
V MAX
~
o
2
-IF
V OH1
lox
Ipo
I MAx
forcing functions
SYMBOL
Vee
Vpo
V MAX
V IL
V IH
VR
VF
Vox (DHOO16CN)
Vox (DHOO17CN)
Vox (DHOO18CN)
lOLl (DH0017CN, DHOO18CN)
lOLl (DHOO16CN)
IOL2
IOL3
O°C
+25u C
5.0
5.0
50
80
0.85
1.8
4.5
0.45
70
50
100
500
250
16
8.0
0.85
1.9
45
0.45
500
250
16
+70°C
50
0.85
1.6
4.5
045
70
50
100
500
250
16
UNITS
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
9·11
z
co
(J
...
test limits
o
o
O°C
SYMBOL
:I:
C
Z
VOLT
..."
V OHI
V OL2
(J
IR
o
o
-IF
:I:
C
lox
Z
I MAX
+70°C
0.6
0.45
1.65
60
1.6
200
+25°C
0.6
0.45
185
60
1.6
5.0
12.2
10
0.6
0.45
1.95
1.6
Ipo
UNITS
V
V
V
/JA
mA
/JA
mA
mA
(J
CO
...
o
o
:I:
C
Typical Switching Times
Typical Output Voltages vs Temperature
Ie = 250 mA
Typical Switching Times
DHOO16CN
Ie = 500 rnA
DH0017CN, DHOOl8CN
~ 04
."
~
w
~
>
OJ
z
02
;::
DHool1CN, DHoolBCN Ie: SOD mA
....
= -
:li
'"....
~
I- -
!
600
!l!;::
SOD
z
i
400
.
DHoo16CN Ie : 250 mA-
f-
.--
i.--"
.... .,
]:
~
01
3D
w
."
~
20
;;;
~ 300
5
~
-
tO~F
~
a
200
100
10
~~
tON
i.--" i'"
....-
"
ION
0
0
25
50
15
0
TEMPERATURE ( CI
25
50
15
0
TEMPERATURE ( CI
50V
Rt
PIN10"Ycc "5V
PULSE
GEN.
±.
OUTPUT
",f·WlRI'G
CAP
FREQ "100 kHz
DUTYCYCLE:SIt%
.,..
PIN 5, PIN 1 GND
RI "200n(DHODI6CN)
RI = loon (DHOOl1CN,
DHDDI8CN)
switching time waveforms
INPUT
IV
,-,
';
I
\
,"v
\
zv
1-- ..,,-
'v
\
25
50
TEMPERATURE rCI
switching time test circuit
9-12
-
tOFF
zv
/-'0"-
.V
our
1&
o
::z:
o
o
Interface Circuits
N
00
n
"'-
o
::z:
o
o
DH0028C/DH0028CN*hammer driver
N
00
general description
features
The DH0028C/D H0028CN IS a hIgh current
hammer driver desIgned for utilizatIon In a wide
variety of printer applIcations. The devIce is
capable of drlvmg 6 amp pulsed loads at duty
cycles up to 10% (1 ms ON/10 ms OFF). The
Input IS DTUTTL compatIble and requires only a
single voltage supply In the range of 10V to 45V.
• Low standby power 45 mW at Vee
35 mW at Vee = 28V.
• AND Input
flexibIlIty.
n
wIth
expander
affords
z
= 36V,
logic
• Fast turn·on, typically 200 ns.
'Prevlously called NH0028C/NH0028CN
connection diagrams
Molded DualMln-Line Package
Metal Can Package
OUTPUT
r---i- 10
Vee
1
INPUT
2
INPUT
3
EXPANDER
4
1
GROUND
5-~;;;;;;~
6
INPUT
NC
INPUT
,
OUTPUT
NC
INTERNAL
CONNECTION
TOPVIEW
typical application
COLUMN ONE
INPUT
COLUMN TWO
INPUT
..._7 +JIV
r------t----~I----
.~41IlF
r-+----t------H.----+-----7~~i::LCLE
r--NHOOZlCN-j
I
I
L_-T-_.J
INHIBIT
>-------4I1---------i-...--------+--:~
zn
zn
JW
JW
HAMMER =1
IOV
HAMMER =2
lOY
*Use one decouphng capacitor per SlK hammer dovel'S for Improved AC nOlS8 Immumty
**Zener IS used to control the dynamiCs ofthe hammer
9·13
z
(.)
co
absolute maximum ratings
(\oj
o
o
Continuous Supply Voltage
Instantaneous Peak Supply Voltage
(Pin 1 to Ground for 0.1 sec)
Input Voltage
Expander Input Current
Peak Otuput Current (1 ms ON/10 ms OFF)
Continuous Output Current DH0028C at 25°C
DH0028CN at 25°C
Operating Temperature
Storage Temperature
Lead Soldering Temperature (10 sec)
J:
C
........
(.)
CO
(\oj
o
o
J:
C
electrical characteristics (Note
PARAMETER
45V
60V
5.5V
5.0mA
6.5A
750 mA
1000 mA
O°C to 70°C
-65°C to +175°C
300°C
1)
MIN
CONOITIONS
' TVP
MAX
UNITS
(Note 1)
Logical "1" Input Voltage
Vee'" lQVto45V
LogICal "0" Input Voltage
Vee" lOV to 45V
v
20
Logical "0" Input Current
Vee'" 45V, V IN
04V
08
Logical ., 1 . Input Current
Vee'" 45V, VIN '" 2 4V
Vee = 45V, V IN ::: 55V
05
Logical ",,, Output Voltage
"
08
v
10
mA
50
1000
Vee" 45V, V IN " 2 av,
a
435
v
335
34 a
v
43
lOUT'" 1 6A
Vee'" 36V, V IN ::: 2 av,
lOUT'" 5A
(Note 2)
020
100
v
Logical "0" Output Voltage
Vee'" 45V, RL
OFF Power Supply Current
Vcc = 45V, VIN - DaV
16
Rise Time {1O% to 90%)
Vee" 45V, RL
02
"'
Vee" 45V, RL = 39~l
V IN ::: 5 OV peak, PRF '" 1 kHz
30
"'
Vee::: 45V, R L
04
"'
:::
=
1k, V IN ::: 0 BV
39U
VIN = 5 OV peak, PRF '"
Fall Time {90% to 10%)
VIN '"
kHz
39U
5 OV peak, PRF ::: 1 kHz
70
Vee::: 45V, R L ::: 39H
VIN "- 5 OV peak, PRF ::: 1 kHz
TOFF
Note 1
:::
t
These specifications apply for ambient temperatures from OoC to 70 0 e unless otherWise
specified All tYPical values are for 25°C ambient
Note 2' Measurement made at 1 ms ON and 10 ms OFF
Note 3' Power ratings for the DH0028C are based on a maximum Junction temperature of 175 Q C and
a thermal reSIStance of 21 OoC/W
Note 4. Power ratings for the DH0028CN are based on a maximum Junction temperature of 175°C
and a thermal resistance of 1500 C/W
typical
perform~nce
characteristics
Waveforms for TYPlcClI
Drum Printer Hammer
40n=:E:ES=w=D
301-+
Vec = 3SV
o
20r-
TON=lms
>
lOr-
~~F:2~}~ms++::-t~H
°
o
-10
:
:
J
I-I-'HAJME .-+-I''"'1"""'''r:!-l
I-l-fET~~~~"-I---t-l
IA ,
Vl , ,
002040S08
TIME (ms)
9·14
20
mA
C
:::t
o
o
Interface Circuits
w
~
.......
C
:::t
o
o
DH0034/DH0034C high speed dual level translator
w
~
(")
general description
features
The DH0034/DH0034C is a high speed level translator suitable for Interfacing to MaS or junction
F ET analog switches. It may also be used as a
universal logic level shifter capable of accepting
TTL/DTL input levels and shifting to CML, MaS,
or SL T levels.
• Fast switching, tpdO: typically 15 ns; tpdl:
typically 35 ns
• Large output voltage range: 25V
• Input is TTL/DTL compatible
• Low output leakage: typically 0.1 iLA
• High output currents: up to ±100 mA
schematic and connection diagrams
Metal Can Package
Dual-in-Line Package
GND
I
14
Vee
A,
2
\3
B,
3
12
.,
Ne 4
11
Ne
V-
ID
OUTPUll
,TQPVIEW
If,C,rcliltShown
Ne
GND
5
,
,
•
,
A,
V-
OUTPUTl
Ne
V-
GNO
TOP VIEW
typical applications
5 MHz Analog Switch
TTL to IBM (SLT) Logic Levels
SOY
ANALOG
OUT
,. . _____ L____ ,
SOY
I
I
I
INPUT 1
I
I
I
I ___________ oJI
L
":"
-15
".
+11V
INPUT 2
""
9-15
(,)
'd'
(\')
absolute maximum ratings
o
o
J:
vcc Supply Voltage
Q
......
'd'
(\')
o
o
7.0V
Negative Supply Voltage
-30V
Positive Supply Voltage
Differential Supply Voltage
+25V
25V
Maximum Output Current
100mA
Input Voltage
J:
Operating Temperature Range:
Q
DHOO34
+5.5V
-55°C to +125°C
O°C to +85°C
DHOO34C
Storage Temperature Range
_65°C to +150°C
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
(See Notes 1 & 2)
CONDITIONS
MIN
DHOO34
TVP
MAX
Logical "I"
Input Voltage
Vee = 4.5V
Vee = 475V
Logical "0"
Input Voltage
Vee = 5.5V
Vee = 4.75V
Logical "I"
Input Current
Vee = 5.5V, Y'N = 2.4V
Vee = 5.25V, Y'N = 2.4V
Logical "I"
Input Current
Vec = 5.5V, Y'N = 5.5V
Vee = 5.25V, Y,N = 5.5V
10
Logical "0"
Input Current
Vee = 5 5V, Y,N = O.4V
Vee = 5.25V, Y'N = a 4V
1.6
Power Su ppl y
(Note 3)
Vee = 5.5V, Y'N = 4 5V
Vee = 5.25V, Y,N = 4.5V
30
37
LogiC "I"
(Note 3)
Vee = 5.5V, Y,N = OV
Vee = 5 25V, Y,N = OV
Logical "0"
Output Voltage
Vec = 4.5V, lOUT = 100 rnA
Vee = 4.5V. lOUT = 50 rnA
V- + .50 V- + .75
V- +.3 V- + .50
Output Leakage
Vee = 5.5V, Y'N = 0.8V
V+ - V- = 25V
Current
Logic "0"
Power Su ppl y
Current
Current
Transition Time to
Logical "0"
Transition Time to
Logical "I"
MIN
DHOO34C
TVP
2.0
UNITS
V
2.0
V
0.8
0.8
40
I1A
40
rnA
10
rnA
1.6
01
38
rnA
30
38
37
48
V- + .50
V- + .3
V- + .80
V- + .65
48
5
rnA
0.1
V
V
5
I1A
Vee = 5.0V, V3= OV,TA = 25°C
V- = -25V, RL = 510rl
15
25
15
35
ns
Vee = 5 OV, T A = 25° C
V- = -25V, RL = 510rl
35
60
35
65
ns
Note 1: These specifications apply over the temperature range _55°C to +125°C for the DHOO34
and O°C to +85°C for the DH0034C with a 510 ohrn resistor connected between output and ground,
and V- connected to -25V, unless otherwise specified.
Note 2: All typical values are for T A = 25°C.
Note 3: Current measured
9-16
MAX
IS
total drawn fro~ Vee supply.
c
::x:
o
o
w
~
.......
theory of operation
When both inputs of the DH0034 are raised to
logic "1 ", the input AND gate is turned "on"
allowing 01's emitter to become forward biased.
01 provides a level shift and constant output cur·
rent. The collector current is essentially the same
Vee - VB.
as the emitter which is given by
R1
Approximately 7.0 mA flows out of 01's col·
lector.
c
::x:
o
o
About 2 mA of 0 I's collector current is drawn off
by pull down resistor, R2. The balance, 5 mA, is
available as base drive to 02 and to charge its
associated Miller capacitance. The output is pulled
to within a VSAT of V-. When either (or both)
input to the DH0034 is lowered to logic "0," the
AND gate output drops ,to 0.2V turning 01 off.
Deprived of base drive 02 rapidly turns off causing
the output to rise to the V3 supply Voltage. Since
02's emitter operates between O.6V and 0.2V, the
speed of the DH0034 is greatly enhanced.
w
~
(")
applications information
1. Parallel ing the Outputs
The outputs of the DH0034 may be paralleled to
increase output drive capability or to accomplish
the "wire OR". In order to prevent current hogging by one output transistor or the other, resistors of 2 ohms/l00 mA value should be Inserted
between the emitters of the output transistors and
the minus supply.
2. Recommended Output Voltage Swing
The graph shows boundary conditions which
govern proper operation of the DH0034. The
range of operation for the negative supply is
shown on the X aXIs and must be between -3V
and -25V. The allowable range for the positive
supply is governed by the valu~ chosen for V-. V+
may be selected by drawing a vertical line through
the selected value for V- and terminated by the
boundaries of the operating region. For example, a
value of V- equal to -6V would dictate values of
15
~
10
15
"'
-10
;::
~
-15
w
~>
,..
~
....
v- < ~3V
v+ - v- ::;25V
I
I.....!'
V
/'
~ OPERATING REGION l- I--
-10
-15
/'
./
V
V
-14
-18
-11
-6
NEGATIVE SUPPl V VOL TAGE I-VI
V+ between -5V and +19V. In general, it is desirable to maintain at least 5V difference between
the supplies.
9-17
(J
It)
Interface Circuits
(W)
o
o
J:
Q
........
It)
('t)
o
o
DH0035/DH0035C PIN diode switch driver
J:
Q
general description
The DH0035/DH0035C is a high speed digital
driver designed to drive PIN diodes in RF modulators and sWitches. The device is used In conjunction
with an Input buffer such as the DM7830/DM8830
or DM5440/DM7440.
features
•
Large output voltage sWing - 30V
•
•
Peak output current in excess of 1 Amp
Inputs TTLlDTL compatible
•
Short propogation delay - 10 ns
•
High repetition rate - 5 MHz
The DH0035/DH0035C IS capable of driving a
variety of PIN diode types including parallel,
serial, anode grounded and cathode grounded. For
additional Information, see AN-49 PIN Diode
Drivers.
The DH0035 IS guaranteed over the temperature
range -55°C to +125°C whereas the DH0035C is
guaranteed from O°C to 85°C.
schematic and connection diagrams
Metal Can Package
INPUT B
'""
/' \
""
TOP VIEW
typical applications
Grounded Cathode Design
sov
1
r--- '!----,
I
I
I
IQ
I
I
I
I
I
I r ---.
I,
II O;:~E
x>--;I---....-----T-11
I
I
I I SWlTCH
I
IL_--1
20 F
I
I
I
'--'-1;.;;.".....----.,
1/2DM8BJO
1"'1"'
41
J
~
~--1---~
[lfl0035
-1--~"
-
! o',~
Note Cathode groondd PIN dIode Rp " 621, lImIts diode forward curren! to 100 mA. TypIcal sw'tchlllg 10f
HP33604A RF tU"1 on 25 IlS, turn of! 5 lis ~2 " 250 pF, Rp ~ Oll, Cl " 0 IF
9-18
OUTPUT
o
%
o
absolute maximum ratings
o
CAl
V- Supply Voltage Differential (Pin 5 to Pin 1 or 2)
40V
V I Supply Voltage Differential (Pin 1 or 2 to Pin 8 or 9)
30V
Input Current (Pin 3 or 7)
±75 mA
Peak Output Current
±1 0 Amps
Power DISSipatIOn (Note 3)
1 5W
Storage Temperature Range
-65°C to +150°C
Operating Temperature Range DH0035
_55°C to +125°C
aOc to +85°C
DH0035C
Lead Temperature (Soldering, 10 sec)
300°C
U1
.......
o
%
o
o
CAl
electrical cha racteristics
U1
(Notes 1,2)
PARAMETER
n
CONDITIONS
Input logic "1" Threshold
V OUT
~
-8V, RL
~
100S)
Input Logic "0" Threshold
V OUT
~
+8V, RL
~
100rl
Positive Output SWing
lOUT
~
100 rnA
Negative Output SWing
lOUT
~
100 rnA
Positive Short Circuit Current
V ,N ~ OV, RL ~ Orl
(Pulse Test, Duty Cycle
LIMITS
TYP
MIN
MAX
v
15
70
04
V
-70
V
V
+80
-80
S
UNITS
400
800
rnA
800
-1000
rnA
3%1
Negative Short Circuit Current
V ,N ~ 1 5V, liN ~ 50 rnA, RL ~ Orl
(Pulse Test, Duty Cycle S 3%1
Turn-On Delay
V ,N
~
1 5V, V OUT
~
-3V
10
15
Turn-Off Delay
V ,N
~
1 5V, V OUT
~
+3V
15
30
ns
On Supply Current
V ,N
~
1 5V
45
60
rnA
ns
Note 1: Unless otherWise specified, these specifications apply for V+:::; 10.0V, V- = -10.0V, pin 5
grounded, over the temperature range -55°C to +125°C for the DH0035, and O°C to 85°C for the
DH0035C_
Note 2: All tYPical values are for T A = 25°C
Note 3: Derate linearly at 10 mW;oC for ambient temperatures above 25°C
typical applications (cont,)
Grounded Anode Design
If'"
~
10V
~----~'~
i
--L
1-
111
I
71
200pF
r-----~----~~I~
lOGIC
0-------;.---4-,
INPUT
v--:--t_'/
I
I
:><:>--7''----__-._--''+,-1
I
20pF
II
I
'"
DIODE
I SWITCH
I
t..t-_T~D~fJc.. __.".-l
-:'
,2
RM
.
ch
120pF
56ll
":"
V-=-100V
Note Anode Grounded PIN dIOde. RM - 56U limits diode IOIWard cunent to 100 rnA TVJllcal swltchmg lor
HP33622A, RF IUrROn 5 liS, turn 0114
!IS
Cl
=
470 pF, C2
=
01 "f, RM - On..
.
Alternate Current Limiting
V'
TO
~>--!_""'WH~-Pl'
OIOOE
9-19
Interface Circuits
DH3467C quad PNP core driver
general description
typical characteristics
The DH3467C consists of four 2N3467 type PNP
transistors mounted in a 14-pln molded dual-in-Ilne
package. The device IS primarily Intended for core
memory application requiring operating currents
In the ampere range, high stand-off voltage, and
fast turn-on and turn-off times.
Turn·ON Time
Turn·OFF Time
Collector Current
Collector-Base Breakdown Voltage
connection diagram
18 ns
45 ns
1A
120V typo
Collector Saturation Voltage
atle=lA
Collector Saturation Voltage
at Ie = 0.5A
o 55V
0.31V
Dual-In-Line Package
NC
TOP VIEW
-30V
-30V
590
59.11
SCOPE
-'~l-f-
200n
SCOPE
200n
2<1,<50011$
12<5n5
1N916
-'DBVU
ta<1j.!S
DUTY CYCLE = 2%
-=
PW"200ns
RISE TIME <;; 2 ns
DUTY CYCLE = 2%
+3V
FIGURE 2. Turn-Off Equivalent Test Circuit
FIGURE 1. Turn-on Equivalent Test Circuit
Vcc=-30V
DUTY CYCLE" 2%
69n
1 Ov
_10vUl
--: f-
1Bon
c·,
~
C
TlME--
10 1J5
co,,"
FIGURE 3. QT Test Circuit
9-20
C-:,'-__...J
v - o - ' - - - -.....
INV INPUT
JTL
OUTPUT
STROBE
10 GND (EMITTER)
NON INV INPUT
BAL/STROBE
BALANCE
o-'---...J
Offset BalanCing
v'
Strobmg
1'"""--.-"
INPUTS·
c,
·lnCfe".Slyplcalc~mmQn
mode
slewlrom 7 OV/j1!i to 18V!/.5
Increastng Input Stage Current*
USing Clamp Diodes to Improve Responses
DriVing Ground-Referred Load
fROM DIA NETWORK
R5
"
ANALOG
INPUT
TO TTL lOGIC
Cl'
Tn
STROBE
'Valuesshown ire for a
Du30V 109'c swmR.nd
al5Vlhreshoid
'TYPICil,npulcUffent,s
tMaybeaddedtocontrQ!
Sfleedandreducesusceptlb,lrty
to nOIse splkei
50 pA w,th'nputsS!fobed off
Comparator and Solenoid Driver
9-24
Strobing off Both Input*
and Output Stages
TTL Interface WIth High level logiC
r-
::I:
.........
......
N
absolut,e maximum ratings
r-
Total Supply Voltage (v+ - V-I
Output to Negative Supply Voltage (V OUT - V-I
Ground to Negative Supply Voltage (GND - V-I
Differential Input Voltage
Input Voltage (Note 1)
Power Dissipation (Note 2)
Output Short Circuit Duration
Operating Temperature Range LH2111
LH2211
LH2311
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics -
::I:
36V
50V
30V
±30V
±15V
500mW
10 sec
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
-65°C to 150°C
300°C
N
N
......
......
r-
::I:
N
W
......
each side (Note 3)
LIMITS
PARAMETER
UNITS
CONDITIONS
LH2111
LH2211
LH2311
Input Offset Voltage (Note 4)
T A ~ 25"C, Rs ~ 50k
I nput Offset Current (Note 4)
T A ~ 25"C
10
10
50
nA Max
Input Bias Current
T A ~ 25"C
100
100
250
nA Max
Voltage Gain
T A'" 25°C
200
200
200
V/mV Typ
Response Time (Note 5)
TA ~ 25"C
200
200
200
ns Typ
Saturation Voltage
Y'N ~ -5 mY, lOUT = 50 mA
TA = 25"C
Strobe On Current
TA ~ 25°C
Output Leakage Current
Y'N Z 5 mY, V OUT ~ 35V
T A = 25"C
Input Offset Voltage (Note 4)
Rs ~ 50k
30
15
30
10
30
15
30
10
75
mV Max
15
V Max
3.0
mATyp
50
nA Max
10
mV Max
20
20
70
nA Max
Input Bias Current
150
150
300
nA Max
Input Voltage Range
±14
±14
±14
V Typ
Input Offset Current (Note 4)
V+Z45V, V-~O
Satu ration Voltage
4.0
40
0.4
0.4
0.4
V Max
V'N~-5mV, ISINK~8mA
PosItive Supply Current
TA ~ 25"C
60
60
75
mAMax
Negative Supply Current
TA ~ 25°C
50
5.0
5.0
mAMax
Note 1: This rating applies for ±15V supplies The positive Input voltage limit
input voltage limit
IS
IS 30V above the negative supply. The negative
equal to the negative supply voltage or 30V below the pOSitive supply, whichever IS less.
Note 2: The maximum junction temperature IS 150°C. For operating at elevated temperatures, devices in the flat package, the
derating IS based QO a thermal resistance of 185°C/W when mounted on a 1/16-lOch-thlck epoxy glass board with O.03-inchWIde, 2 ounce copper conductor. The thermal resistance of the dual-In-Ime package IS 100°C/W, junctIon to ambient.
Note 3: These specifications apply for V S ~ ± 15V and _55 0 C ~ T A ~ 125" C for the LH 2111, _25" C ~ T A ~ 85" C for the
LH221l, and oOe
TA
700e for the LH2311, unless otherWise stated. The offset voltage, offset current and bias current
specifications apply for any supply voltage from a Single 5V supply up to ± 15V supplies. For the LH23l1, V IN = ± 1 0 mV.
s.
s.
Note 4: The offset voltages and offset currents given are the maximum values required to drive the output wlthm a volt of
either supply with a 1 rnA load. Thus, these parameters define an error band and take IOto account the worst case effects of
voltage gain and input Impedance.
Note 5: The response time specifIed
IS
for a 100 mV Input step with 5 mV overdrive
9-25
CD
o
N
:E
....I
Interface Circuits
ISIS
........
LM106/LM206 voltage comparator/buffer
general description
CD
o
....
:E
....I
The LM 106 and LM206 are high-speed voltage
comparators designed to accurately detect lowlevel analog signals and drive a digital load. They
are equivalent to an LM710, combined with a two
input NAN D gate and an output buffer. The
circuits can drive RTL, DTL or TTL integrated
circuits directly. Furthermore, their output.s can
switch voltages up to 24V at currents as high as
100 mAo Other features include:
• Improved accuracy: 2 mV maximum worst case
offset.
• Fan-out of 10 with DTL or TTL
• 40 ns maximum response time
The devices have short-circuit protection which
limits the inrush current when it is used to drive
incandescent lamps, in addition to preventing
damage from accidental shorts to the positive
supply. The speed is equivalent to that of an
LM 71 O. However, they are even faster where buffers and additional logiC circuitry can be eliminated
by the increased flexibility of the LM 106 and
LM206. They can also be operated from any negative supply voltage between -3V and -12V with
little effect on performance.
The LM106 IS specified for operation over the
-55°C to +125°C military temperature range. The
LM206 is specified for operation over the _25°C
to +85°C temperature range.
• Added logic or strobe capabi IIty
• Useful as a relay or lamp driver
• Plug-In replacement for the LM710.
schematic and connection diagrams **
,
Metal Can
TOP VIEW
V·
STRQIIE
vR6
'50
Not.' Ptn4connlCttdtoceM
"'"
Flat Package
NC
NC
GROUND
NO
INPUT
NC
t--+_-,-10UTPUT
"
50'
INPUT
v'
NC
NC
v-
OUTPUT
STROBE
STROBE
Note Pm 6 connected to bottom of
y-'
* *Pm cllnneclmntshown are lor TO 5 packlfl!
p~ck~ge
TOPVIEW
typical applications * *
Level Detector and Lamp Driver
Fast Response Peak Detector
v~" 12V
y'
Relay Driver
"'
"
"
-'---1r--1'I--'"
FIJ6661i
OUTPUT
Adjustable Threshold Line Receiver
OUTPUT
fO <10
9-26
absolute maximum ratings
PosItIve Supply Voltage
NegatIve Supply Voltage
Output Voltage
Output to Negative Supply Voltage
Differential Input Voltage
Input Voltage
15V
-15V
24V
30V
±5V
±7V
electrical characteristics
Input Offset Current
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
MAX
0.5
20
mV
Note 3
07
3.0
IJ.A
CONOITIONS
MIN
UNITS
TVP
Note 3
Input Bias Current
Response Time
LM106
LM206
600mW
10 sec
_55°C to 125°C
_25°C to 85°C
_65°C to 150°C
300°C
(Note 2)
PARAMETER
Input Off5et Voltage
Power DISSipation (Note 1)
Output Short Circuit Duration
Operating Temperature Range
Note 4, RL = 3901] to +5V,
10
20
IJ.A
28
40
ns
CL =15pF
Saturation
Volta~e
Output Leakage Current
V IN ~ -5 mY, lOUT
= 100 rnA
V'N~ 5 mV, 8V:5 VOUT :5 24V
10
15
V
002
10
IJ.A
30
mV
electrical characteristics
The follOWIng specii,cat,ons apply for TL
I nput Offset Voltage
~ T A ~ T H (Note 5)
Note 3
Average Temperature CoeffiCient
of Input Offset Voltage
Input Offset Current
30
Note 3, T L ~ T A ~ 25°C
18
025
25'C~TA~TH
Average Temperature CoeffiCient
of Input Offset Current
25°C ~ TA ~T H
50
15
Input Voltage Range
IJ.A
IJ.A
T L ~ TA ~ 25°C
45
IJ.A
25°C<;' TA~TH
20
IlA
-7V
'C. V- 'C. -12V
i50
V
i50
V
V ,N :5 -5 mV, lOUT = 50 mA
10
V
= 16 mA
04
V
Satu ration Voltage
V'N 'S -5 mV, lOUT
POSitive Output Level
V'N
2: 5 mV, lOUT = -400 IJ.A
V'N
2: 5 mV, 8V:5
Output Leakage Current
IJ.vtc
nAtC
nAtC
Differential Input Voltage Range
Saturation Voltage
70
30
25
75
T L ~TA~ 25°C
Input BIas Current
10
25
VOUT'S 24V
55
V
10
IJ.A
T L ~ TA ~ 25°C
25°C< TA ~ T H
Strobe Current
VSlrObe =
100
a 4V
Strobe ON Voltage
-1 7
09
-32
14
IJ.A
mA
V
Strobe OF F Voltage
ISlnk ~ 16 rnA
14
POSitive Supply Current
V'N = -5mV
55
10
mA
-15
-36
mA
Negative Supply Current
22
V
m
Note 1. The maximum Junction temperature of the LM106 's 1S0"C, while that of the LM206
IS 110"C For operating at elevated temperatures, devices ,n the TO-5 package must be derated
based on a thermal resistance of 1S0"C/W, Junction to ambient, or 45"C/W, Junction to case
For the flat package, the derating IS based on a thermal resistance of 185" C/W when mounted
on a 1/16-lnch-thlck epoxy glass board with ten, 003-Inch-wlde, 2-ounce copper conductors
Note 2. These specifications apply for -3V > V- > -12V, V+ = 12V and T A = 2S"C unless other
wise specified All currents Into device PinS are considered positive
Note 3: The offset voltages and offset currents given are the maximum values required to dnve the
output down to OSV or up to 50V Thus, these parameters actually define an error band and take
Into account the worst-case effects of voltage gain, specified supply voltage vanatlons, and common
mode voltage variations
Note 4 The response time specified (see deflnltlonsl IS for a 100 mV Input step With 5 mV overdrive
Not. 5: All currents Into device pms are conSidered positive
9-27
Interface Circuits
LM306 voltage comparator/buffer
general description
The LM306 IS a high-speed voltage comparator
designed to accurately detect low-level analog signals and drive a digital load. It IS equivalent to an
LM710e, combined with a two input NAND gate
and an output buffer. The circuit can drive RTL,
DTL or TTL integrated circuits directly. Furthermorp, the output can sWitch voltages up to 24V at
currents as high as 100 mAo Other features
include.
• Improved accuracy. 5 mV (max) offset, 25,000
gain
• Fan-out of 10 with DTL or TTL
• Added logic or strobe capability
• Useful as a relay or lamp driver
• Plug-In replacement for the LM710e.
The device has short-circuit protection which
limits the inrush current when it IS used to drive
incandescent lamps, In addition to preventing
damage from accidental sports. The speed IS
equivalent to that of an' LlV1710e. However, It IS
even faster where buffers and additional logic
circuitry can be eliminated by the Increased flexibility of the LM306. It can also be operated from
any negative supply voltage between -3V and
-12V with little effect on performance. The LM306
IS identical to the LM106,except that It is specified
over a oOe to 70°C temperature range.
schematic and connec'tion diagrams
STROBE
r---~-------1r---t---t---1r---t----'~
"'"
TOPVIEW
....----+---t---i----1r---{."
v'
"
'50
D3
.3V
....---t---~7 OUTPUT
vNon Ptn4tonnectedtoRil
"
10'
!:l---...,........w..,-......~-------<.....--.....--....--....;. GROUND
typical applications
V*" =12V
Fast Response Peak Detector
RI
Leval Detector and Lamp Driver
" ....
DI
"
"
Adjustable Threshold Line Receiver
Relay Driver
OUTPUT
FOSIO
INPUTS
·Optlollllfo .... on"'tlmec.IItl'.1
9-28
r-
3:
w
o
c:n
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Output Voltage
Output to Negative Supply Voltage
Differential Input Voltage
Input Voltage
Power DIssipation (Note 11
Output Short CirCUit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 60 seci
15V
-15V
24V
30V
±5V
±7V
600mW
10 sec
DoC to 70°C
-65°C to +150°C
300°C
electrical characteristics
(Note 21
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I nput Offset Voltage
Note 3
1.6
5.0
mV
I nput Offset Current
Note 3
1.S
50
jlA
I nput Bias Current
16
Voltage Gain
25
40
Response Time
Note 4
Saturation Voltage
V ,N
Output Leakage Current
V ,N '2: 7 mV, SV
V/mV
ns
40
<::: -7 mV, I"nk = 100 mA
<::: V OUT <::: 24V
jlA
O.S
2.0
V
0.02
2.0
/lA
6.5
mV
electrical characteristics
The following specifications apply for DoC
I nput Offset Voltage
<::: T A <::: 70°C
Note 3
Average Temperature Coefficient
of Input Offset Voltage
5
I nput Offset Current
Note3,T A =0°C
Average Temperature Coefficient
of I nput Offset Current
25°C:::; T A:::; 70°C
DoC:::; T A::; 25°C
2.4
Input B las Current
I nput Voltage Range
-7V'2: V-"2.- 12V
7.5
nAtC
24
100
nAtC
25
40
/lA
V
V
V ,N :::; -SmV, I"nk = 50 mA
Saturation Voltage
V'N~ -SmV, l"nkS 16 mA
V ,N "2. SmV, lOUT = 400 /lA
Output Leakage Current
V ,N "2. SmV, SV S V OUT
Strobe Current
V strobe = O.4V
1.0
2.5
<::: 24V
Strobe ON Voltage
i.7
I"nk'::; 16 mA
1.4
Positive Supply Current
V ,N =-S mV
5.5
Negative Supply Current
V
5.5
V
3.3
1.4
Strobe OFF Voltage
1.5
V
0.4
100
0.9
/lA
50
±5.0
Positive Output Level
/lvtc
15
±5.0
Differential I nput Voltage Range
Saturation Voltage
20
/lA
mA
V
2.5
10
3.6
V
0
mA
mA
Note 1: For operating at elevated temperatures, the device must be derated based
on a 85°C maXimum Junction temperature and a thermal resistance of 45°C!W
Junction to case or 1500 C/W Junction to ambient
Note 2. These specifications apply for -3V
V-12V, V+ = 12V and
T A"" 25°C unless otherwise specified.
Note 3: The offset voltages and offset currents given are the maximum values
2':
2':
required to drive the output down to O.5V or up to 5 av. Thus, these parameters
actualJy define an error band and take Into account the worst-case effects of
voltage gain and Input Impedance
Note 4: The response time specified (see definitions) IS for a 100 mV Input step
with 5 mV overdrive.
9-29
...
N
~
Interface Circuits
......
...I
......
~
...I
LMll1/LM211 voltage comparator
general description
The LM111 and LM211 are voltage comparators
that have input currents nearly a thousand times
lower than devices like the LM 106 or LM710.
They are also designed to operate over a wider
range of supply voltages: from standard ± 15V op
amp supplies down to the single 5V supply used
for IC logic. Their output is compatible with RTL,
DTL and TTL as well as MOS circuits. Further,
they can drive lamp,s or relays, switching voltages
up to 50V at currents as high as 50 mAo
features
• Operates from single 5V supply
• Input current: 150 nA max. over temperature
• Offset current: 20 nA max. over temperature
• Differential input voltage range: ±30V
• Power consumption: 135 mW at ±15V
Both the inputs and the outputs of the LM 111 or
the LM211 can be isolated from system ground,
and the output can drive loads referred to ground,
the positive supply or the negative supply. Offset
balancing and strobe capability are provided and
outputs can be wire OR' ed. Although slower than
the LM106 and LM710 (200 ns response time vs
40 ns) the devices are also much less prone to
spurious oscillations. The LM 111 has the same pin
configuration as the LM106 and LM710.
The LM211 is identical to tne LM 111, except that
its performance is specified over a _25°C to 85°C
temperature range instead of -55°C to 125°C.
schematic diagram and auxiliary circuits
. .
IALANCEISTR08E
""
BALANCE
RJ
A4
300
300
'"
Offset Balancing
m
STROSE
,
OUTPUT
Strobing
.
v'
.
'"
,
GROUND
·,"" .... '·vP'ellcommDnmod.
" ... 1,0., 7 OVI", 10 18'0'1",
Increasing Input Stage Current*
connection diagrams *
Metal Can
Flat Package
"
Dual-I n-Line Package
"
BALANCEI
STROBE
11
V·
Non Pm5connectldtobol10mofp .. k.ge
Non
"'n4CGMoctldtoco..
TO' VIEW
BALANCEI
STROlE
+Pm connections shown on schematiC diagram
and tYPical applicatIOns are for TO·5 package.
9-30
NOTE Pm 6 connecled10 bonom01 po.t...
r-
....3:....
....
absolute maximum ratings
........
Total Supply Voltage (V 84 )
Output to Negative Supply Voltage (V 74 )
Ground to Negative Supply Voltage (V 14)
Differential Input Voltage
Input Voltage (Note 1)
Power DIssipation (Note 2)
Output Short CirCUit Duration
Operating Temperature Range LM 111
LM211
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
electrical characteristics
PARAMETER
Input Offset Voltage (Note 4)
r-
36V
50V
30V
±30V
±15V
500mW
10 sec
_55°C to 125°C
_25° C to 85° C
_65°C to 150°C
300°C
3:
........N
(Note 3)
CONDITIONS
TA = 25°C, Rs ::;50k
MIN
TYP
MAX
07
3.0
40
10
UNITS
mV
nA
Input Offset Current (Note 4)
T A = 25°c
Input Bias Current
T A = 25°C
60
Voltage Gain
T A = 25°C
200
V/mV
200
ns
Response Time (Note 5)
TA =25°C
Saturation Voltage
V ,N ::; -5 mV, lOUT = 50 mA
T A =25°C
0.75
Strobe On Current
T A =25°C
3.0
Output Leakage Current
V ,N :::>5mV,
TA = 25°C
Input Offset Voltage (Note 4)
Rs ::; 50k
0.2
V
mA
10
4.0
Input Offset Current (Note 4)
nA
mV
20
nA
150
nA
V
±14
Input Voltage Range
Output Leakage Current
1.5
nA
V OUT = 35V
Input Bias Current
Saturation Voltage
100
V+ :::> 4.5V, V- = 0
V ,N ::; -6 mV, I SINK ::; 8 mA
023
0.4
V
V ,N :::>5mV, V OUT = 35V
01
0.5
flA
Positive Supply Current
TA = 25°C
5.1
6.0
mA
Negative Supply Current
TA
25°C
4.1
5.0
mA
=
Note 1. This rating applies for ±15V supplies The positive Input voltage limit IS 30V above the
negative supply The negative Input voltage limit IS equal to the negative supply voltage or 30V below
the positive supply, whichever IS less
Note 2. The maximum JunctIOn temperature of the LM111 IS 150°C, while that of the LM211 IS
11 aOc For operating at elevated temperatures, deVices In the TO-5 package must be derated based on
a thermal resistance of 150o C/W, Junction to ambient, or 45°C/W, Junction to case For the flat
package, the derating IS based on a thermal resistance of l85°C/W when mounted on a 1/16-lnch-thlck
epoxy glass board with ten, 0 03-lnch-wlde, 2-ounce copper conductors The thermal resistance of the
dual-In-Ilne package IS lDDoC/W, JunctIon to ambient
Note 3. These speCifications apply for Vs = ±15V and -55°C STA::; 125°C, unless otherwise stated
WIth the LM2ll, however, all temperature speCIfIcations are limited to _25°C ~TA ~85°C The offset voltage, offset current and bIas current speCifications apply for any supply voltage from a single 5V
supply up to ±15V supplies
Note 4: The offset voltages and offset currents given are the maximum values required to drive the
output wlthm a volt of either supply With almA load. Thus, these parameters define an error band
and take Into account the worst case effects of voltage gam and Input Impedance
Note 5: The response time speCified (see definItions) IS for a 100 mV Input step With 5 mV overdrive
9-31
....
....
<"II
:E
typical applications
....
......
....
....
....
:E
....
"
lOOOpf 1
"."'
"
no
5ml~~~~v_-1>---+----'\IIfV--""""1r.,
"
"
2NS019
2N3972
"
IN/51
"'
330~
"'
lNI~l
"'
IN4!i1
'--__
"'
"
10K'
111457
....-+------....-
~--------
saUARE
WAV£
OUlPl/T
"."'
'AdlU,I!.,.vmmo,.,.. Is.qu".
w ... tlmt ""on v,~ . S mV
'"..
IM,nlmum'....-+4-+----I--OUTPUT
He
IfilPUT
PreCISion Squarer
Crystal Oscillator
9·33
......
N
typical applications (con't)
:E
....I
......:E
.......
....I
..
,"
T"
"
'"
15 "f'
01'
'"
I',.
Negative Peak Dectector
'O.".01l.go",."0010,.,,.,
'O.tomllnlnnr",n, •• lt.!IO 5V."no"n
Crowbar Over-Voltage Protector
Driving Ground-Referred Load
POSitive Peak Detector
USing Clamp Diodes to Improve Response
'"~ucl' .. k,ekb.ck of
""v·nd~,ol .."ICI,om ..."
"Ab$O.1H
vol" .. ".n... M' on V" hne
Relay Driver with Strobe
,-....--....--...... ,'
"
"....
"
lOOk
..."
"
21113135
"
o1 ~f
""
"
"
""
"
""
,,,.
"
"
02Z"F
'""
Switching Power Amplifier
9-34
:K
'""
"'"
SWitching Power Amplifier
. ".""
,.'"
,...
s:w
....
....
Interface Circuits
LM311 voltage comparator
general description
The LM311 is a voltage comparator that has input
currents more than a hundred times lower than devices like the LM306 or LM710e. It is also designed to operate over a wider range of supply
voltages: from standard ±15V op amp supplies
down to the single 5V supply used for Ie logic. Its
output IS compatible with RTL, DTL and TTL as
well as MOS circuits. Further, it can drive lamps or
relays, switching voltages up to 40V at currents as
high as 50 mAo
• Maximum offset current: 50 nA
• Differential input voltage range: ±30V
• Power consumption: 135 mW at±15V
Both the input and the output of the LM311 can
be isolated from system ground, and the output
can drive loads referred to ground, the positive
supply or the negative supply. Offset balancing
and strobe capability are provided and outputs can
be wire OR' ed. Although slower than the LM306
and LM710e (200 ns response time vs 40 ns) the
device is also much less prone to SpUriOUS oscilla·
tions. The LM311 has the same pin configuration
as the LM306 and LM710e .
features
• Operates from single 5V supply
• Maximum Input current: 250 nA
schematic diagram and auxiliary circuits
,
,
IALAIriCEISfROBE
""
BALANCE
R3
fl4
'"
300
fit
11K
"
R2
IlK
"
600
Offset Balancing
He
STROBE
,
OUTPUT
Strobing
.
,-
connection diagrams *
Metal Can
.
'"
,
GROUND
Dual-In-Line Package
"Inc"'''''¥P.ulcommunmudo
slewlr~m 1 OV/""t. laV/",
Increasing Input Stage Current*
Dual-I n-Line Package
Flat Package
"
"':::::8:::""'
INPUT]
V-4
6
BALANCEI
STROBE
5 BALANCE
BALANCEI
STROBE
*Pin connections shown on schematic diagram
and typical applications are for TO·5 package.
9·35
........
M
~
absolute maximum ratings
Total Supply Voltage (V B4 1
Output to Negative Supply Voltage (V 74 1
Ground to Negative Supply Voltage (V 141
Differential Input Voltage
Input Voltage (Note 11
Power Dissipation (Note 21
Output Short CirCUit Duration
Operatmg Temperature Range
Storage Temperatu re Range
Lead Temperature (soldering, 10 seci
electrical characteristics
PARAMETER
36V
40V
30V
±30V
±15V
500mW
10 sec
O°C to 70°C
-65°C to 150°C
300°C
(Note 31
MIN
CONDITIONS
TYP
Input Offset Voltage (Note 41
T A = 25°C, Rs ::; 50K
2.0
Input Offset Current (Note 41
T A = 25°C
6.0
MAX
7.5
50
250
UNITS
mV
nA
Input Bias Current
T A = 25°C
100
Voltage Gam
T A = 25°C
200
V/mV
200
ns
Response Time (Note 51
T A = 25°C
Saturation Voltage
V ,N ::; -10 mV,
T A =25°C
Strobe On Current
TA = 25°C
Output Leakage Current
V ,N -::> 10 mV,
TA =25°C
Input Offset Voltage (Note 41
Rs ::; 50K
nA
lOUT = 50 mA
0.75
1.5
3.0
V
mA
V OUT = 35V
0.2
Input Offset Current (Note 41
Input Bias Current
50
nA
10
mV
70
nA
300
nA
±14
Input Voltage Range
V
Saturation Voltage
V+ -::> 4.5V, V- = a
V ,N ::; -10 mV, ISINK
023
0.4
V
Positive Supply Current
T A = 25"C
5.1
75
mA
Negative Supply Current
T A = 25C
4.1
50
mA
::;
8 mA
Note l' This rating applies for ±15V supplies The positive Input voltage limit IS 30V above the
negative supply The negative Input voltage limit IS equal to the negative supply voltage or 30V below
the positive supply, whichever IS less
Note 2. The maximum Junction temperature of the LM311 IS 85°C For operating at elevated
temperatures, devices In the TO-5 package must be derated based on a thermal resistance of 150 o C/W,
Junction to ambient, or 45°C/W, Junction to case For the flat package, the derating IS based on a
thermal resistance of 185°C/W when mounted on a 1/16-lnch-thlck epoxy glass board with ten,
0.03-mch-wlde, 2-ounce copper conductors The thermal resistance of the dual-In-Ilne package IS
1 OOoC/W, Junction to ambient
Note 3: These specifications apply for Vs = ±15V and OoC :-......- ______
'"
"'
WAV,
OUTPUT
"
lNJ9n
2tl5019
eo
"
llOK
""
"
'"
"
"'
0'
lN151
eo
,e,
lN45J
lN4~1
'"'"
·AIIIU'11D1·vmm'1I1e,l'qu."
..... 11m... ~."
11'hmmum
v,~ ~
5 mV
''""
"?"'('"" 20 pF
M."mum h'qu,ncy 50 kit'
"""
10 Hz to 10 kHz Voltage Controlled Oscillator
Rl
\/'05\1
20K
R5
11(
SQUARE
WAVE
OUTPUT"
Low Voltage Adjustable Reference Supply
Zero
Cro~mg
Detector driving MOS logic
100 kHz Free Running Multlvibrator
r - - - -.....--~IP_v·.:v
....---.....-,.
,--
"'
'"
""
""
"' ....._ ....._~~TPUT
lN4001
~,""""""I4-
"'
2N3140
Zero Crossing Detector Driving MOS SWitch
Detector for Magnetic Transducer
Comparator and Solenoid Driver
9-37
....
....
('I)
:E
typical applications (con't)
....
v'
W
fREQUENcY RANGE
INPUT ~ ..., ,. 50 kH.
lIU1PUT ,0.H"o'OO,H,
Frequency Doubler
, - - + - - 9 - V ' &11
"'"
""'
"'
""
,"
'A2 .. " Ih.
"mo.""," I•• ~
:;,',::~~'::; ~~',~~;~~,'Odt
d." .. ~nl''''.v.. bv ,n ",d"
'","yb •• ddedI. <.ntr.1
olm.llno'"d •
... Hd.ndnd.' ... ..,.pllb'h1v
'"n"'........ 01
TTL Interface with High Level Logic
PreCISion Photodlode Comparator
,J~+--:;---H
'"
ourpUT
'"
STROBl:
Ki
;OK
Cl
001
f
lyp.ul"'put'"".n'"
50 pA
"",i> '"puB \Hob.rl oH
Strobmg off Both Input·
Digital TransmIssion Isolator
and Output Stages
\/'
"
'"
511
.
'"""
"
"
lOOK
""
II'
5\1
..
"
He
INPUT
TAd,onl ... tol.mpl ... ,
PreCISion Squarer
9-38
Crystal Oscillator
.-
3:
w
......
typical applications (con't)
"
IN4~1
"
'"
",'
'",
Negative Peak Dectector
"
MCR2918
1
·Ov... Dltatelf._lconlroi
TDtIlI.m'"'n.. '''' ... ..,ltIgt 5Vls"'own
Crowbar Over-Voltage Protector
Positive Peak Detector
"
·lnpool'ol·"W .. ' ...... dwlMn
uSI .... nl .. oulpP!
v'
Driving Ground-Referred Load
USing Clamp Diodes to Improve Response
o\~K"b, ,n~": T A :<>: 70°C, V cc = 5V ±5%, for LM350 and LM75450A unless otherwise specified.
TTL GATES
PARAMETER
LOGIC
INPUT
COMMENTS
LOGIC
OUTPUT
SUPPLY
VOLTAGE
MIN
2
a 4V
V,"
l6mA
475V
Logic Output;;::': 2 4V
V,"
-400 rnA
475V
Logical "1" Output Voltage
08V
-400 rnA
475V
Logical "0" Output Voltage
2V
l6mA
475V
Logical
"1" Input Voltage
Logic Output ~
Logical "0" Input Voltage
A Input
LogICal "," I nput Current
TVP
MAX
UNIT
V
08
24
V
V
04
V
24V
525V
40
S Input
24V
525V
80
~A
A Input
55V
525V
1
mA
~A
S Input
55V
525V
2
mA
A Input
04V
525V
-16
mA
S Input
04V
525V
-32
Output Short Circuit Current
Note 4
OV
Supply Current
Output Low
LM350
Per Package
5V
525V
8
14
mA
Per Package
5V
525V
6
11
mA
Per Package
OV
525V
4
7
mA
Per Package
OV
525V
2
4
mA
T A '" 25°C, Vsus '" OV
-12mA
-15
V
MAX
UNIT
logical "0" Input Current
LM75450A
Output High
LM350
LM75450A
Input Diode Clamp Voltage
OV
525V
-18
-55
5V
mA
mA
TRANSISTORS
COMMENTS
PARAMETER
BASE
EMITTER
OV
BVcso
RSE ~
BVCEA
soon
OV
BV EBO
COLLECTOR
MIN
100~A
35
TVP
100~A
30
V
5
V
V
OV
lOOJ.!A
V. E
lOmA
30mA
OV
OV
lOOmA
300mA
085
105
1
12
V
V
VCE(sat)
lOmA
30mA
OV
OV
100mA
300mA
025
05
04
07
V
V
I,
I.
I.
I,
OV
OV
OV
OV
lOOmA
300mA
lOOmA
300mA
h,.
VeE = 3V, TA ==
VeE = 3V, TA =
VeE: == 3V. TA ==
VeE = 3V, TA =
O°C,
O°C,
25°C,
25°C,
Note 5
Note 5
Note 5
Note 5
20
25
25
30
The following apply for Vcc = 5V, T A = 25°C
TTL GATES (Note 6)
I
PARAMETER
I
tpdl
tpdO
I
TVP
I
MAX
TRANSISTORS
I
I I I
lOns
5 ns
22 ns
15 ns
GATES AND TRANSISTORS (Note 7)
PARAMETER
TVP
MAX
PARAMETER
TVP
td
6 ns
15 ns
tpdl
14 ns
t.
12 ns
20 ns
,,",0
18 ns
t,
6 ns
15 ns
t,
5ns
t,
8 ns
15 ns
t,
10 ns
Note 1: All voltage values are With respect to ground termmal. POSitive current IS defined to be
current mto referenced pm.
Note 2: With base-emitter reSistance ~ soon.
Note 3: The maXimum Junction temperature IS 150u C. For operatmg at elevated temperatures the
package mUlt be derated based on a thermal resistance of 150°C/W 0JA.
Note 4: Only one output should be shorted at a tIme.
Note 5: These parameters are to be measured With less than 2% duty cycle.
Note 6: Delays measured With fanout of 10,15 pF total load capacitance, measured from 1.5V Input
to 1.5V output.
Note 7: Delays m.asured With 50n load to 10V, 15 pF total load capacitance, measured from 1.5V
input to 50% of output.
9·41
...
o
,.....
:E
....I
Interface Circuits
LM710 voltage comparator
general description
The LM710 is a high-speed voltage comparator
intended for use as an accurate, low-level digital
level sensor or as a replacement for operational
amplifiers in comparator applications where speed
is of prime importance. The circuit has a differential input and a single-ended output, with saturated
output levels compatible with practically all types
of integrated logic.
saturating comparator appl ications. In fact, the low
stray and wiring capacitances that can be realized
with monolithic construction make the device dlf·
ficult to duplicate with discrete components operating at equivalent power levels.
The LM710 is useful as a pulse height discriminator, a voltage comparator in high-speed AID converters or a go, no-go detector in automatic test
equipment. It also has applications in digital systems as an adjustable-threshold line receiver or an
interface between logic types. In addition, the low
cost of the unit suggests it for applications replacing relatively simple discrete component circuitry.
The device is built on a single silicon chip which
insures low offset and thermal drift. The use of
a minimum number of stages along with minoritycarrier lifetime control (gold doping) makes the
circuit much faster than operational amplifiers in
schematic* and connection diagrams
Metal Can Package
INPUTS
T
R4
R5
28K
J9K
-+------11::
"''"0
"sa
typical applications*
Line Receiver With
Schmidt Trigger
Increased Output
Sink Current
"'
'"
OUTPUT
Level Detector With
Pulse Width Modulator
Lamp Driver
A3
>~'M,......-C~~2222
*Pm connections shown are for metal can.
9·42
absolute maximum ratings
l4.0V
-7.0V
10mA
±5.0V
±7.0V
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Power DISSipation
300mW
200mW
-55°C to +125°C
-65°C to +150°C
300°C
TO-99 (Note 1)
Flat Package (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
electrical characteristics
(Note 3)
PARAMETER
Input Offset Voltage
CONDITIONS
'"
TA
::=
25°C. VOUT
Input Bias Current
TA
::=
25°C
Voltage Gam
TA = 25°C
Output Resistance
TA= 2SoC
==
MAX
UNITS
20
mV
OV
Input Offset Current
TA
TYP
06
T A = 25°C, Rs S200n
V CM
Output Sink Current
MIN
::
075
1 4V
13
1250
30
20
1700
n
200
20
25°C
pA
pA
mA
2.5
V OUT == 0
Response Time
ns
40
TA '" 25°C
(Note 4)
RsS200n. V CM
-55°CS;T A 'S 12SOC
CoeffiCient of Input
30
= OV
Input Offset Voltage
Average Temperature
mV
pvtc
10
RsS50n
30
TA =125°C
025
30
pA
TA
_55°C
18
70
pA
25'CSTAS125'C
50
Offset Voltage
Input Offset Current
Average Temperature
==
25
nAtC
-55° CST A S25°C
15
75
nAtC.
Input Bias Current
TA
::=
27
45
pA
Input Voltage Range
V-
= -7
Rs
-s: 200n
CoeffiCient of Input
Offset Current
Common Mode Rejection Ratio
-5SoC
OV
80
100
dB
V
±50V
Differential Input
Voltage Range
Voltage Gam
PosItIve Output Level
V
±50
1000
V IN ?5mV.
Os lOUT S -5 mA
NegatIve Output Level
V IN s-5mV
Output Sink Current
TA "" 125°C. VIN :::;-5 mV
40
V
0
V
25
32
-10
-05
05
, 7
mA
' 0
23
mA
VOUT "" 0
T A = -55°C, V IN S -5 mV
V OUT
Positive Supply Current
=
a
V IN ~-5 mV
Negative Supply Current
Power Consumption
V IN ~-5 mV
52
90
mA
4.6
70
mA
90
150
mW
lOUT = 0
Note 1: Rating applies for case temperatures to +125"C, derate linearly at 56 mWtC for ambient
temperatures above +10S"C
Note 2: Derate linearly at 4 4 mW(C for ambient temperatures above +100°C
Note 3: These specifications apply for V+ = 12 OV. V- '" -6.0V, -55°C::;' T A ::; +125°C unless
otherWise specifIed The Input offset voltage and Input offset current (see definitions) are specified
for a logIc threshold voltage of 1 8V at -55"C, 1 4V at +25"C, and 1 OV at +125"C
Not. 4: The response time specifIed (see definitions) IS for a 100 mV Input step with 5 mV overdrtve
9-43
(.)
...
o
.....
Interface Circuits
::?1
..J
LM710C voltage comparator
general description
The LM710e is a high-speed voltage comparator
Intended for use as an accurate, low -level digital
level sensor or as a replacement for operational
amplifiers In comparator applications where speed
is of prime Importance. The circuit has a differential input and a slngle·ended output, with saturated
output levels compatible with practically all types
of integrated logic.
with monolithic construction make the device difficult to duplicate with discrete components operating at equivalent power levels.
The LM710e is useful as a pulse height discriminator, a voltage comparator in high-speed A/D converters or a go, no-go detector in automatic test
equipment. It also has applications in digital systems as an adjustable-threshold line receiver or an
interface between logic types. I n addition, the low
cost of the unit suggests it for applications replacing
relatively simple discrete component circuitry.
The device is bUilt on a single silicon chip which
insures low offset and thermal drift. The use of a
minimum number of stages along with minority·
carner lifetime control (gold doping) makes the
circuit much faster than operational amplifiers in
saturating comparator applications. In fact, the low
stray and wiring capacitances that can be realized
The LM710e is the commercial/Industrial version
of the LM710. It IS Identical to the LM710 except that operation IS specified over a oOe to 70°C
temperature range.
schematic and connection diagrams
Metal Can Package
Dual-In-Line Package
I~PUTS
+
Nt
I
GROUND
2
13
NC
1+) INPUT
3
12
NC
HINPUT
4
11
'V ee ISUPPl Yl
Nt
,
10
NC
-Vee ISUPPlY)
6
9
OUTPUT
Nt
,
8
Nt
14
NC
LM710C
typical applications
Schmidt Trigger
Line Receiver With
I ncreased Output
Sink Current
Pulse Width Modulator
Level Detector With
Lamp Driver
JUUL
9-44
r-
3:
....,
...0
absolute maximum ratings
(")
Positive Supply Voltage
Negative Supply Voltage
Differential Input Voltage
Input Voltage
Power Dissipation (Note 11
Output Short Circuit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 10 secl
14.0V
-7.0V
±5.0V
±7.0V
300mW
10 sec
OOC to 70°C
_65°C to +150°C
300°C
electrical characteristics
(Note 21
PARAMETER
Input Offset Voltage
CONDITIONS
MIN
T A'" 25°C, Rs <200n
V OUT
Input Offset Current
T A =25"C,V OUT
TA
Voltage Gam
T A =25°C
Output Resistance
T/I.:; 25 Q C
Output Sink Current
T A'" 25"C, AV 1N 25 mV
'"
14V
=-
50
mV
50
MA
18
16
25°C
V OUT
MAX
16
UNITS
4V
'" ,
Input Bias Current
'"
TYP.
1000
25
200
17
MA
1500
n
25
mA
0
Response Time
40
ns
(Note 3)
Input Offset Voltage
RsS200n
Average Temperature
0° C,S TA:::;70°C
CoeffiCient of Input
65
5.0
RsS50n
20
mV
MVtC
Offset Voltage
Input Offset Current
Average Temperature
CoeffiCient of Input
75
MA
25°C<;TA<;70°C
15
50
nAtC
O°C::;TAS25°C
24
100
nAtC
Offset Current
Common Mode Rejection Ratio
Rs ::: 200n
Input Bias Current
TA :;
Input Voltage Range
V-'-70V
Voltage Gain
40
MA
±50
V
±50
V
800
V IN
?
5 mV,
0::; lOUT
Negative Output Level
V IN S:-10mV
V IN ::;-10 mV, V OUT "" 0
V IN
25
32
40
V
-10
-05
0
V
52
9
mA
46
70
rnA
5-5 rnA
Output Sink Current
Positive Supply Current
98
25
Differential Input
Voltage Range
Positive Output Level
70
aOc
:S -10 mV
Negative Supply Current
Power Consumption
05
mA
150
m
mW
Note 1 Ratings apply for ambient temperatures to 70°C
Note 2 These specifications apply for V+ '" 12,OV, V- = 6,QV, O°C:s TA 'S 70°C and for
a logic threshold voltage of 1 5V at O"C, 1 4V at 25"C and 1 2V at 7JJ"C unless otherwise
speCified
Note 3 The response time specified (see definitions) IS for a 100 mV mput step With
5 mV overdnve.
9·45
...........
:i!!
...I
Interface Circuits
LM711 dual comparator
general description
The LM711 contains two voltage comparators
with separate differential inputs, a common output and provision for strobing each side independently. Similar to the LM710, the device features
low offset and thermal drift, a large Input voltage
range, low power consumption, fast recovery from
large overloads and compatibility with most integrated logic circuits.
With the addition of an external resistor network,
the LM711 can be used as a sense amplifier for
core memories The input thresholding, combined
with the high gain of the comparator, eliminates
many of the inaccuracies encountered with con-
ventlonal sense amplifier designs. Further, it has
the speed and accuracy needed for reliably detectIng the outputs of cores as small as 20 mils.
The LM711 is also useful in other applications
where a dual comparator with OR'ed outputs IS
requ ired, such as a double-ended I im it detector. By
using common circuitry for both halves, the device
can provide high speed with lower power dissipation than two single comparators. The LM 711 is
available In either a~ 10-lead low profile TO-5
header or a 1/4" by 1/4" metal flat package.
schematic and connection diagrams
Metal Can Package
STROBE
r-~t---------.---+---~---4---.--------~~--~---v·
INPUTS
typical applications
Sense Amplifier With Supply Strobing
for Reduced Power Consumption*
Double-Ended Limit Detector
With Lamp Driver
"
620
01
lN755
'"
LM111
;~~~~I:E_""",_"
""
UPPER
LIMIT
It.
RI
J2K
VOLTAGE
R2
12K
AS
100
LOWER
LIMIT
VOLTAGE
FADM
SENSE
LINES
OUTPUT
Rfi
100
'St1ndbvd'qlpal'nn'$
about40mW
9-46
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Internal Power Dissipation (N ote 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec!
+140V
-7.0V
25 mA
±5.0V
±70V
o to +6.0V
300mW
_55°C to 125°C
_65°C to 150°C
300°C
electrical characteristics
(Note 2)
(These specifications apply for TA = 25°C, V+ = 12V, V- = -6V)
PARAMETER
Input Offset Voltage
CONDITIONS
MIN.
Rs:S 200,12, V CM = 0
TYP.
10
10
Rs:S 2COn
Input Offset Current
05
Input Bias Current
25
Voltage Gain
750
Response Time (Note 2)
40
12
V- = -7.0V
10.0
Il A
75
Il A
ns
ns
V
±50
Output Resistance
V
,12
200
Positive Output Level
V ,N
Loaded Positive 0 utput Level
V'N
2: 10 mV
2: 10 mV,
4_5
10 =-5 mA
25
3.5
-0.5
Negative Output Level
V,N ::;-10 mV
-1.0
Strobed Output Level
VSTROBE :S 0.3V
-10
Output Sink Current
V,N ::; -10 mV, VOUT
Strobe Current
VSTROBE = 0
V ,N ::;-10 mV
Positive Supply Current
mV
mV
±50
Differential Input
Voltage Range
2: 0
UNIT
3.5
5.0
1500
Strobe Release Time
Input Voltage Range
MAX.
05
Power Consumption
V
V
0
V
0
V
08
12
Negative Supply Current
5.0
mA
2.5
mA
86
mA
39
mA
130
200
mW
The followmg specifications appry for _55° C :S T A :S 125° C:
Input Offset Voltage (Note 3)
Rs :S200n, V CM = 0
Rs::; 200,12
4.5
6.0
Input Offset Current (Note 3)
20
Input Bias Current
150
Average Temperature
Coefficient of Input
Offset Voltage
Voltage Gain
5.0
mV
mV
Il A
Il A
IlV/oC
500
Note 1: Rating applies for case temperatures to +12So C; derate linearly at 5.6
temperatures above 105°C.
mwtC
for ambient
Note 2: The Input offset voltage and Input offset current (see definitions) are speCified for a logiC
threshold voltage of 1 8V at -5SoC, l.4V at +2SoC, and 1.0V at +12SoC.
Note 3: The response time speCIfied IS for a 100 mV Input step with 5 mV overdrive (see definitions).
9-47
Interface Circuits
LM711C dual comparator
general description
ventional sense amplifier designs. Further, it has
the speed and accuracy needed for reliably detect·
ing the outputs of cores as small as 20 mils.
The LM711C contains two voltage comparators
with separate differential inputs, a common out·
put and provision for strobing each side indepen·
dently. Similar to the LM710C, the device features
low offset and thermal drift, a large input voltage
range, low power consumption, fast recovery from
large overloads and compatibility with most integrated logic circuits.
The LM711C IS also useful in other applications
where a dual comparator with OR'ed outputs is
required, such as a double·ended limit detector. By
uSing common circuitry for both halves, the device
can provide high speed with lower power dissipa'
tion than two single comparators. The LM711 C is
the commercial/industrial version of the LM711.
It is identical to the LM711, except that operation
is specified over a O°C to 70°C temperature range.
With the addition of an external resistor network,
the LM711 C can be used as a sense amplifier for
core memories. The input thresholding, combined
with the high ·gain of the comparator, eliminates
many of the inaccuracies encountered with con·
Metal Can Package
schematic and connection diagrams
STROlE
v,
STROlE
r-~~--------~---+--~~--~--~----------e---~--v'
Dual-In-Line Package
INPUTS
.>-----1-
L..--------4....--------4....- _____ v·
typical applications
.---9---9--.,,,
lOY
..
BUS
R1
12K
um.
STROBE
LIMIT
VOLTAGE
.n.
"
12K
INPUT
"'
'00
"..
SENSE
LiNts
9·48
LOWER
LIMIT
VOLTAGE
OUTPUT
"::'
R6
'00
13
STROIE"A"
1
12
GROUND
-Vcl;(SQ"LY) •
11
+VccISUPPLY)
(+II.'UT"'~
t
11
OUTPUT
I-)IWPUT"B"
I
•
STRO.E .....
Double-Ended Limit Detector
With Lamp Driver
D1
lN755
~='i'~e_~,....-
2
I+)IIII'UY"""
SILICONE MOLDED
Sense Amplifier With Supply Strobing
for Reduced Power Consumption'
LM111
"
HINI'UT"""
....
!:
:::i
...
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
I nternal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(")
+14.0V
·7.0V
25 mA
±5.0V
±7.0V
o to +6.0V
300mW
O°C to 70°C
·65°C to 150°C
300°C
electrical characteristics
(These specifications apply for T A
;
(Note 1)
25°C, V+ = 12V, V-
PARAMETER
=-6V)
CONDITIONS
MIN.
Rs S200~2, VCM = 0
Rs S 200n
Input Offset Voltage
Input Offset Current
TYP.
1.0
1.0
0.5
Input Blas Current
Voltage Gam
700
Response Time (Note 2)
25
1500
MAX.
5.0
7.5
15
IJA
100
IJA
40
12
Strobe Release Time
I nput Voltage Range
V-=-7.0V
ns
ns
±50
Differential Input
Voltage Range
V
V
±50
Output Resistance
200
2: 10 mV
Positive Output Level
VIN
Loaded Positive Output Level
2.5
4.5
3.5
Negative Output Level
VIN ? 10 mV, 10 =-5 mA
VIN $-10 mV
-1.0
-0.5
Strobed Output Level
Output Smk Current
VSTROBE SO 3V
VIN $-10 mV, VOUT2:0
-10
0.5
0.8
Strobe Current
VSTROBE =0
VIN $-10mV
Positive Supply Current
Negative Supply Current
n
5.0
0
0
1.2
2.5
V
mA
mA
mA
3.9
130
V
V
V
mA
8.6
Power Consumption
UNIT
mV
mV
230
mW
6.0
10
25
150
mV
mV
The following specifications apply for OoC ::; TA ::; 70°C:
Input Offset Voltage (Note 3)
Rs S 200n, V CM
Rs S200n
=0
Input Offset Current (Note 3)
Input Bias Current
Average Temperature
Coefficient of input
Offset Voltage
5.0
Voltage Gain
500
Note 1: RatIngs apply for ambient temperatures to 70°C
<
<
Note 2: Thesa specIfications apply for V+ "" 12 OV, V- ... 6 OV, OoC
TA
70°C and for a logic
threshold voltage of 1 5V at aOc, 1.4V at 2SoC and 1 2V at 7CoC unl"$ otherWise speCified
Note 3: The response time specified
IS
for a 100 mV input step With 5 mV overdrive (see
de~lnl'tIQns).
IJA
IJA
IJvtc
Interface Circuits
LM1488 quad line driver
general description
features
The LM 1488 is a quad line driver which converts
standard DTL/TTL input logic levels through one
stage of inversion to output levels which meet EIA
Standard No. RS-232C and CCITT Recommendation V. 24.
•
•
•
•
•
±10 mA typ
Current limited output
Power-off source impedance
300£1 min
Simple slew rate control with external capacitor
Flexible operating supply range
Inputs are DTL/TTL compatible
schematic and connection diagrams
r-------_1~--------_1~--~-----ov·
Rl
R2
D1
INPUT
Dual-In-Line Package
DO
v'
INPUT
R8
r----1I---+-'V'IIV--O
OUTPUT
D7
DB
GND
TOPVIEW
R7
~--~------~I-----~~-~----_ov-
1/4 CIRCUIT
9-50
absolute maximum ratings
(Note 1)
Supply Voltage
V+
VInput Voltage (V ,N )
Output Voltage
Power Derating (Note 2)
(Package Limitation, J Package)
Derating above T A = +25°C (1/0 JA)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-15V::; V ,N
1000 mW
6.7 mWtC
O°C to +75°C
_65°C to +175°C
300°C
electrica I characteristics
PARAMETER
LogiC "0"
Input Current
LogiC "1"
Input Current
High Leyel
Ou tput Voltage
RL = 30kD.
Y'N = 0 SV
Y'N = 19V
High Level Output
V OUT = OV
Short-Circuit Current
Y'N = O.SV
Low Level Output
V OUT = OV
V ,N = 19V
V+ = V- = OV
V OUT
""
±2V
V ,N =19V
Positive Supply
Current
Y'N = O.SV
V ,N =1.9V
Negative Supply
Current
(Output Openl
Power Dissipation
Propagation Delay
MAX
-10
-1.3
rnA
10.0
J.lA
.005
Y'N = O.SV
r+=90V
V- = -9.0V
V+ = 13.2V
V- = -13 2V
{ V+ = 9.0V
V- = -9.0V
V+ = 13.2V
V- = -13 2V
I
I
I
Iv:
UNITS
TYP
Y'N = +5 OV
Output Voltage
(Output Openl
MIN
Y'N = OV
RL =30kD.
Output ReSistance
(Note 3)
CONDITIONS
Low Level
Short-CIrcuIt Current
+15V
-15V
::; 7.0V
±15V
6.0
70
V
9.0
105
V
-6.0
-6.S
V
-9.0
-105
V
-60
-100
-120
mA
60
100
12.0
mA
D.
300
V' = 9.0V, V- = -9 OV
V' = 12V, V- = -12V
V+ = 15V, V- = -15V
150
190
25.0
200
25.0
34.0
mA
mA
mA
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
45
5.5
8.0
6.0
7.0
12.0
rnA
mA
mA
V+ = 9 OV, V- = -9 OV
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
-13.0
-lS 0
-25.0
-170
-230
-340
mA
mA
mA
-1.0
-10
-2.5
mA
mA
mA
= 9 OV, V~ = -9 OV
V = 12V, V = -12V
V+ = 15V, V- = -15V
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
-.001
-.001
-.01
252
441
333
576
mW
mW
RL = 3.0 kD.
CL = 15 pF, TA = 25°C
230
300
ns
R L =3.0kn
C L = 15 pF, T A = 25°C
70
175
ns
Rise Time (t r)
RL = 3.0 kD.
CL = 15 pF, TA = 25°C
75
100
ns
Fall Time (t,1
RL = 3.0 kD.
CL = 15pF, TA = 25°C
40
75
ns
to "1" (tpd,1
Propagation Delay
to "0" (tpdol
Note 1: Voltage values shown are with respect to network ground terminal. Positive current
IS
D
defined as curren~ Into the
referenced pin.
Note 2: The maXlmum junction temperature of the LM1488 IS 150°C. For operating at eievated temperatures the cavity
Dual~ln-line Package (J) must be derated based on a thermal resistance of 85°C/W, junction to amb,ent.
Note 3: These specifications apply for V+ = +9.0V ± 1%, Vtypicals are for V+ = 9.0V, V- = -9.0V, and T A = 25°C.
:=
-9.0V ± 1%, TA:= O°C to +7SoC unless otherwise noted. All
9-51
co
co
...:E
~
applications
...I
By connecting a capacitor to each driver output
the slew rate can be controlled utilizing the output
current Iimitlng characteristics of the LM 1488.
For a set slew rate the appropriate capaclto; value
may be calculated using the follOWing relationship
C = Isc (l1T/LW)
where C is the required capacitor, Isc is the short
circuit current value, and l1V/l1T !S the slew rate.
RS232C specifies that the output slew rate must
not exceed 30V per microsecond. USing the worst
case output short circuit current of 12 mA in the
abov~ equation, calculations result in a required
capacitor of 400 pF connected to each output.
typical applications
RS232C Data Transmission
T~LlDTL
--...,.-,
1/4 LM14118
T2l/011
__ .r-,
-_..
--..
t>----L._~
t::l---
--""1...-'"
r 2L!DTl
---:(-l:
==----'V';IIr-...----TlL/on
1/4lM14B91
1/4 LM1488
lM1489A
r 2 L/OlL
--~-,
p---t--..,...--t---l2<>--= =:t. _ }>- - 1/4 LM14B91
rll/OTL
--2
<0
>2
4V
4V
4V
4V
Logic
Logic
Logic
Logic
Output
Output
Output
Output
<0 4V
>2 4V
<04V
>2 4V
±525V
LM7520/LM7521 : The following apply for OOe:::;TA :::;70 o e
11(8)
Differential Input
Threshold Voltage
361331
(V TH ) (Note 4)
Differential & Reference
Input Bias Current
15
15
40
40
441471
mV
mV
mV
mV
30
75
"A
191221
:tV TH
15mV
15mV
40mV
40mV
'5V
'5V
+5V
'5V
'5V
'5V
+5V
'5V
OV
OV
+525V
+525V
+525V
±525V
+525V
±525V
±VTH
±VTH
±VTH
+16 mAlO)
-400/JA(Q)
+16 mAlO)
-400 "Alai
±5V
±5V
±5V
±5V
LM5520/LM5521: The following apply for -55°C:::; T A:::; 125°c
LM7520/LM7521: The following apply for oOe:::; T A :::; 70°C
Differential Input Offset
Current
Logic" 1" I nput Voltage
(Strobes)
(Gate a)
(Gate a)
05
Logic "0" Input Current
-1
5
02
5
02
24
24
24
025
025
025
-3
Q Output Short
t525V
V
V
V
40 mV
40 mV
40 mV
20 mV
20 mV
20mV
'2V
OV
OV
.,.475V
+2V
OV
08
08
08
V
V
V
40 mV
40 mV
40mV
20 mV
20 mV
20 mV
+0 BV
OV
OV
+475V
+0 BV
OV
-1.6
mA
40mV
20 mV
to 4V
t04V
to 4V
±525V
Each Input
40
1
40
1
"A
mA
20 mV
20mV
20 mV
20 mV
+24V
+525V
... 525V
+525V
t525V
t525V
t24V
+525V
+24V
+525V
±525V
±525V
±525V
±525V
Each Input
Each Input
"A
mA
OV
OV
40mV
40mV
V
V
V
40mV
40mV
40mV
20mV
20mV
20mV
+20V
OV
+-475V
t525V
+0 BV
OV
V
V
V
40mV
OV
OV
20mV
20 mV
20 mV
+08V
OV
OV
+475V
.2V
OV
-5
mA
OV
20 mV
OV
OV
39
39
39
LogiC "0" Output Voltage
(Strobe)
(Gate QJ
(Gate 0)
Circuit Current
+525V
2
2
Logic" 1" Input Current
(Strobe & Gate OJ
(Gate a)
Q Output Short
OV
2
Logic "0" Input Voltage
(Strobes)
(Gate a)
(Gate 0,)
Logic "1" Output Voltage
(Strobe)
(Gate 0)
(Gate aJ
OV
"A
-4
040
040
040
'2V
-400 "AIOI
+16 mAlO)
+16 mAlO)
±5V
±5V
±5V
Logic Output >2 4V
Logic Output <0 4V
Logic Output <0 4V
+0 8V
+16 mAlO)
-400 !'Alai
-400,uA(O)
±5V
±5V
±5V
Logic Output <0 4V
Logic Output >2 4V
Logic Output >2 4V
-400,UA(OJ
+08V
'2V
-400 "AIOI
-400 "Alai
±475V
±475V
±475V
+16 mAlO)
+16 mAlO)
+16 mAlO)
±475V
±475V
±475V
OVIOI
±525V
OVlal
±525V
-28
-35
mA
OV
20 mV
OV
OV
ov
V+ Supply Current
21
35
mA
OV
20 mV
OV
OV
OV
±525V
V- Supply Curreqt
-13
-18
mA
OV
20 mV
OV
OV
OV
±525V
-21
Circuit Current
e
Note 1 For OoC ::; T A S; 700 operation, electrical characterIStiCS for LM5520 and LM5521 are
guaranteed the same as LM7520 and LM7521, (espectlvely
Note 2' Limits
Note 3
In
parentheses '")ertaln to LM5521, other limits pertain to LM5520
a or 0 In parentheses Indicate Q or Q logiC output, respectively
Note 4: Limits
In
parentheses pertain to LM7S21, other limits pertain to LM7520
Note 5
POSitive current IS defined as current Into the referenced pin
Note 6
Pm 1 to have ~100 pF capacitor connected to ground
9-58
r-
s:
U1
U1
N
o
........
r-
LM5520/LM7520 and
electrical characteristics
s:.....
LM 5521/LM7521
U1
N
LM5520/LM5521 and LM7520/LM7521: The following apply for T A = 25°C, V+ = 5V, V- = -5V
o
TEST CONDITIONS
PARAMETER
AC Gommon Mode
Input Firing Voltage
MIN
TYP
MAX
±25
UNIT
V
DIFF
INPUT
REF
INPUT
STROBE
AND
GATE
INPUTS
PULSE
20 mV
+5V
C/)
a
lOGIC
OUTPUT
AC TEST
CIRCUIT
Logical" 1" Q Output
Differential Input to
logical "0"
Q
Output
Differential Input to
LogICal "'"
6 Output
Differential Input to
Logical "0"
6. Output
Strobe Input to
Logical "1" Q Output
ns
20 mV
1
28
ns
20 mV
1
36
ns
20mV
1
20
40
28
55
ns
20 mV
1
10
30
ns
20mV
1
Strobe I nput to
Logical "0" Q Output
20
ns
20 mV
1
Strobe Input to
Logical "1" Q Output
33
ns
20 mV
1
Strobe Input to
Logical "0"
6 Output
Gate Q Input to
Logical "1" Q Output
Gate Q Input to
Logical "0" Q Output
Gate Q Input to
Logical "1" 0 Output
Gate 0 Input to
Logical "0"
Q Output
16
55
ns
20 mV
1
12
20
ns
20 mV
2
6
0;
20 mV
2
17
ns
20mV
2
ns
20 mV
2
ns
20 mV
2
ns
20mV
2
19
Gate Q Input to
Logical "1" Q Output
12
Gate 6. Input to
Logical "0"
Output
6
6
Dlff Input Overload
Recovery Time
Common Mode Input
Overload Recovery
30
20
10
ns
5
ns
200
ns
Time
Min Cyde Time
CD
en
SCOPE
Propagation Delays
Differential Input to
...
CD
9-59
I/)
CD
';:
LM5520/LM7520 and LM55211LM7521
CD
(J)
o
N
In
schematic diagram
"::?!
.......
.......
v'o-----------~-----.--------__,
o
N
In
In
",,,,,,,.{'
::?!
.......
INPUT
GAT~ o----l---+~==+~==~=~=t_------_,
DlFFEAENTlAl{
INPut A
STROBE A
0---1----++----++-'
OUTPUT
<>----11--------+-'
GAT~ <>----ir--------+---+--i+--'
a
STROBE B
L----6-~~---~-4-----4
connection diagram
Duat-tn-Line Package
v+
C(~T
STROBE
GATE
A
Q
~
DIFFERENTIAL
INPUT A
9-60
OUTPUT OUTPUT STROBE
11
il
-
+
~
REFERENCE
INPUT
B
GATE
fi
'---....,.-..-'
DIFFERENTIAL
INPute
GND
IF
__6-06ND
r-
s:
LM5522/LM7522 and LM5523/LM7523
electrical characteristics
U1
U1
LM5522/LM5523: The followtng apply for -55°C ~ T A ~ 125°C (Note 11
N
o
........
TEST CONDITIONS (EACH AMPLIFIER)
PARAMETER
MIN
10(8)
Differentia! Input
Threshold Voltage
(V iH I (Note 2)
35(33)
TvP
15
15
40
40
Differential & Aeiefence
30
Input Bias Current
GATE
INPUT
LOGIC
OU1PUT
SUPPLY
VOLT
.. sv
+5V
+5V
+5V
'5V
.5V
'5V
'5V
-400/JA
+16 rnA
-400/JA
+16 rnA
±5V
±5V
±5V
±5V
+525V
+525V
MAX
20(22)
45(47)
100
mV
mV
mV
mV
±VTH
±VTH
±VTH
±VTH
j.J.A
OV
15 mV
15 mV
40 mV
40 mV
OV
r-
s:
...,
COMMENTS
Logic
Logic
Logic
logic
Output
Output
Output
Output
U1
>2 4V
<0 4V
>2 4V
2
<0
>2
<0
!II
4V
4V
4V
4V
LM5522/LM5523: The following apply for -55°C::::: TA ~ 125°C
LM7522/LM7523: The follOWing apply for O°C ~ T A
Dlff Input Offset Current
05
pA
Logic "1" Input Voltage
(Strobes)
(Gate)
Logic "0" Input Voltage
(Strobes)
(Gate)
08
08
-1
OV
:::::
70°C
OV
40 mV
40mV
20 mV
20rnV
+2V
OV
+475V
+2V
+16 mA
-400 pA
±5V
±5V
Logic Output <0 4V
Logic Output >2 4V
40mV
40mV
20mV
20mV
+08V
OV
+475V
tOBY
-40011A
+16rnA
±5V
±5V
Logic Output >2 4V
Logic Output <0 4V
Each Input
-16
rnA
40mV
20mV
+04V
+04V
:l:525V
(Strobes)
40
(Gate)
40
pA
mA
pA
rnA
OV
OV
40 mV
40 mV
20
20
20
20
+24V
+525V
+525V
+525V
+525V
+525V
+24V
+525V
±525V
±525V
±525V
±S 25V
V
40mV
20mV
+08V
+2V
V
40 mV
40 mV
20 mV
20 mV
+2V
OV
+4.75V
+0 8V
mA
40 mV
Logic "0" Input Current
Logic "1" Input Current
Logic "1" Output Voltage
24
Logl,c "0" Output Voltage
(Strobes)
(Gate l
Output Short Circuit
Current
025
025
-2 1
Output Leakage Current
39
-28
001
040
040
-35
mV
mV
mV
mV
20 mV
OV
+525V
250
pA
OV
20 mV
OV
.2V
-400 pA
±475V
+16 rnA
+16 rnA
:t4 75V
±475V
Tie PinS 10 and 12
Tie PinS 10 and 12
OV
±525V
TiePins 10 and 12
+S25V
±'475V
V+ Supply Current
23
36
mA
OV
20 mV
OV
OV
:1:525V
V- Supply Current
-13
-18
rnA
OV
20 mV
OV
OV
:l:525V
LM5522/LM5523 and LM7522/LM7523. The following apply for T A
AC Common Mode Input
±25
Firing Voltage
Propagation Delays
Dlfferentlal!nput to
logical "1" Output
PULSE
21
Strobe Input to
Logical "1" Output
22
Strobe Input to
Logical "0" Output
12
+5V
.5V
SCOPE
20mV
26
DI.fferentlallnput to
logical "0" Output
20 mV
= 25°C, V+ = 5V, V- = -5V
45
AC Test Clfcult
20m"
20mV
40
Gate Input to
Logical "1" Output
20mV
AC Test Circuit
20 mV
Gate Input to
Logical "0" Output
15
Differential Input Over
load Recovery Time
10
25
20mV
ACTest CIrcuit
c~mmon
Mode Input
Overload Recovery
Time
Min Cycle Time
200
Note 1: For O°C ~ T A ::; 70°C operation, electrical characteristiCs for LM5522 and LM5523 are
guaranteed the same as LM7S22 and LM7523, respectively
Note 2
LImits In parentheses pertain to LM5523, other limits pertain to LM5522
Note 3. Limits
Note 4
In
parentheses pertaIn to LM7523, other limIts pertain to LM7522
POSitive current
IS
defined as current Into the referenced pm
Note 5· Pm 1 to have ~ 100 pF capacitor connected to ground
9-61
III
G)
';:
LM5522/LM7522 and LM5523/LM7523
G)
fA
o
N
an
:E
r-
schematic diagram
....t
Y'~---------1~---'--------~
"
o
N
an
an
:E
....t
1"T£o---+---I+...:==t~==~::~+---,
H,
OUTPUT
STROIE.o---+-_ _ _ _ _ _
-+~
Y-
'-_-_-o6N02
connection diagram
Dual-In-Line Package
v+
STROlE
A
GATE
'-----..--J
DIFFERENTIAL
INPUT A
9-62
'NO 2 OUTPUT
~
REFERENCE
INPUT
STROlE
RL
'-----..--J
DIFFERElTlAL
INPUT.
GND 1
r-
s:
U1
U1
N
o
.......
r-
s:......
LM5524/LM7524 and LM5525/LM7525
electrical characteristics
LM5524/LM5525:
The following apply for
-55°C ~ T A ~ 125°C
(Note
U1
1)
N
o
en
TEST CONDITIONS lEACH AMPLIFIERI
MIN
PARAMETER
10lBI
Differential Input
Threshold Voltage
~VTH j
TVP
351331
(Note 2)
Differential & Reference
30
Input Bias Current
LM7524/LM7525:
11181
361331
Differential & Reference
Input Bias Current
REF
INPUT
mV
±VTH
+5V
+16 rnA
201221
mV
±VTH
15mV
15mV
+5V
mV
mV
±VTH
40mV
40mV
+5V
+5V
-400IJA
+16mA
451471
"A
OV
100
441471
mV
±VTH
30
75
"A
OV
05
Logic "0" Input Voltage
-1
Logic ''1'' Input
Current
5
002
Logic "1" Output Voltage
24
Output Short Circuit
Current
-21
-2 B
-400 }J.A
SUPPLV
VOLT.
±5V
±5V
±5V
±5V
±VTH
±VTH
±VTH
15mV
15mV
40mV
40mV
OV
+16mA
+5V
+5V
+5V
-400 }J.A
+16 rnA
+5V
-400 "A
±5V
±5V
±5V
±5V
OV
OV
Logic Output >2 4V
Logic Output <0 4V
OB
V
40mV
20 mV
+0 BV
-16
mA
40 mV
20mV
+04V
±525V
40
1
"A
mA
OV
OV
20 mV
20mV
+24V
+525V
±525V
±525V
V
40 mV
20mV
+20V
V
40 mV
20 mV
+0 BV
-35
mA
40mV
20 mV
+525V
-400 J.1A
+16 mA
-400J.1A
UI
±475V
+16mA
±475V
OV
±S 25V
29
40
mA
OV
20 mV
OV
1525V
-1B
mA
OV
20 mV
OV
±525V
The follOWIng apply for T A =
V
±25
<0 4V
>2 4V
<0 4V
>2 4V
±5V
+2V
-13
AC Common-Mode Input
FlrlOg Voltage
Output
Output
Output
Output
±5V
20mV
LM7524/LM7525:
Logic
Logic
Logic
Logic
...CD
CD
±525V
+525V
40 mV
V- Supply Current
and
<0 4V
>2 4V
<0 4V
>2 4V
±525V
+525V
V+ Supply Current
LM5524/LM5525
Output
Output
Output
Output
±S 25V
+525V
V
040
COMMENTS
Logic
Logic
Logic
Logic
-55°C ~ T A ~ 125°C
aOe ~ T A ~ 7aoe
"A
39
025
Logic "0" Output Voltage
INPUT
~ 7aoe
191221
2
Logic "0" Input Current
TA
OV
mV
mV
mV
The following apply for
Logic "1 ' Input Voltage
aOe ~
±VTH
15
15
40
40
The following apply for
Dlff Input Offset Current
LOGIC
OUTPUT
DIFF.
INPUT
The following apply for
Differential Input
Threshold Voltage
(V TH ) (Note 3)
LM5524/LM5525:
LM7524/LM7525:
15
15
40
40
STROBE
UNIT
MAX
PULSE
20 mV
+5V
25°C, V+
=
5V, V-
=
-5V
SCOPE
PropagatIOn Delays
Differential Input to
logical" 1" Output
20
Differential Input to
Logical "0" Output
2B
Strobe Input to
Logical "1" Output
10
Strobe I nput to
Logical "0" Output
Differential Input Over
load Recovery Time
Common-Mode Input
Overload Recovery
Time
MIO Cycle Time
ns
20 mV
AC Test Circuit
ns
20 mV
AC Test Circuit
ns
20 mV
AC Test Circuit
20
ns
20 mV
AC Test Circuit
10
ns
5
ns
200
ns
40
30
e
Note 1 For O°C ~ T A ~ 700
operation, electncal characteristics for LM5524 and LM5525 are
guaranteed the same as LM7524 and LM7525 respectIVely
Note 2 Limits In parentheses pertalO to LM5525, other limits pertalO to LM5524
Note 3. Limits 10 parentheses pertain to LM7525, other limits pertain to LM7524
Note 4
Positive current IS defmed as current IOta the referenced pm
Note 5: Pin 1 to have
2:: 100 pF capacitor connected to ground
.
9-63
LM5524/LM7524 and LM5525/LM7525
schematic diagram
v·o------------.----~--------__,
OUTPUT A
OUTPUT B
STROBE B ()---+---------+_~
ONO 2
connection diagram
Dual-I n-Lme Package
v+
CEXT
STROBE
A
OUTPUT
A
~
DIFFERENTIAL
INPUT A
9-64
GNO 2
OUTPUT
8
+
~
REFERENCE
INPUT
STROBE
8
NO
CONN
~
DIFfERENTIAL
INPUTB
GNO 1
v-
r-
3:
lM5528/lM7528 and lM5529/lM7529
C1I
C1I
N
electrical characteristics
LM5528/LM552g·
-55°C ~
The following apply for
~ 125°C
TA
(Note
11
o
TEST CONDITIONS lEACH AMPLIFIER)
PARAMETER
MIN
10(8)
Olfferentlal Input
Threshold Voltage
{V TH } (Note 2)
35(33)
Differential & Reference
30
Input Bias Current
LM7528/LM7529:
TYP
15
15
40
40
MAX
UNIT
20(22)
45(47)
100
The following apply for
DIFF.
INPUT
INPUT
±VTH
15mV
±VTH
15 mV
40 mV
mV
mV
mV
mV
±VTH
±VTH
"A
OV
REF
40 mY
OV
oOe ~ T A
STROBE
INPUT
+5V
+5V
+5V
+5V
LOGIC
OUTPUT
+16 mA
-400 tlA
+16 mA
-400 j.1A
+525V
SUPPLY
VOLT
±5V
±5V
±5V
±5V
........
r-
COMMENTS
Logic
Logic
Logic
Logic
Output
Output
Output
Output
<0
>2
<0
>2
3:
.....
4V
4V
4V
4V
C1I
N
o
en
±S 25V
CD
~ 70°C
~
CD
11(8)
Differential Input
Threshold Voltage
(V TH ) (Note 3)
36(33)
Differential & Reference
Input Bias Current
LM5528/LM5529 :
LM7528/LM7529.
15
15
40
40
44(47)
mV
mV
mV
mV
30
75
"A
OV
-55°C ~
The follOWing apply for
oOe ~ T A
LogiC "1" Input Voltage
05
-1
LogiC "0" Input Current
LogiC "1" Input
Current
5
002
LogiC "1" Output Voltage
24
LogiC "0" Output Voltage
Output Short Circuit
V+ Supply Current
Supply Current
and
AC Common Mode Input
Firing Voltage
15 mV
40 mY
40mV
OV
+5V
+5V
+5V
+5V
+16mA
-400 J.lA
+16mA
-400 pA
±5V
±5V
±5V
±5V
OV
OV
~400
08
V
40mV
20 mV
+0 BV
-16
mA
40mV
20 ,'!IV
+04V
!525V
40
1
"A
mA
OV
OV
20 mV
20 mV
+24V
+525V
±525V
±525V
V
40 mV
20 mV
+20V
V
40mV
20 mV
+0 BV
+16 mA
+525V
OV
J1A
±5V
LogiC Output >2 4\1
+16 mA
±5V
LogiC Output <0 4V
~400
J1A
±475V
±475V
-28
-35
mA
40 mV
20 mV
29
40
mA
OV
20 mV
OV
±525V
-13
-18
mA
OV
20 mV
OV
±525V
The following apply for T A
V
en
4V
4V
4V
4V
±525V
+525V
+2V
:r25
<0
>2
<0
>2
~ 125°C
~ 70°C
20 mV
LM7528/LM7529:
Output
Output
Output
Output
TA
40 mV
040
Logic
Logic
Logic
Logic
±S 25V
+525V
V
39
025
-21
Current
"A
2
LogiC "0" Input Voltage
LM5528/LM5529
±VTH
±VTH
±VTH
±VTH
The follOWing apply for
Dlff Input Offset Current
V~
19(22)
15mV
PULSE
20 mV
+5V
±525V
= 25°C, V+ = 5V, V- = -5V
SCOPE
Propagation Delays
Differential Input to
Logical "1" Output
20
Differential Input to
Logical "0" Output
28
Strobe Input to
Logical "1" Output
10
Strobe Input to
Logical "0" Output
Differential Input Overload Recoverv Time
Common·Mode Input
Overload Recovery
Time
Min Cycle Time
40
"'
20mV
AC Test CirCUit
"'
20 mV
AC Test CirCUit
"'
20 mV
AC Test Circuit
20
"'
20mV
AC Test CIrCUit
10
"'
5
"'
200
"'
30
Note 1 For OoC ::; T A ::; 70°C operation, electrical characterIStics for LM5528 and LM5529 are
guaranteed the same as LM7528 and LM7529 respectively
Note 2
Limits
In
parentheses pertain to LM5529, other limits pertain to LM5528
Note 3. Limits In parentheses pertain to LM7529, other limits pertain to LM7528
Note 4: POSitive current IS defined as current rnto the referenced pin
Note 5_ Prn 1 to have ~ 100 pF capacitor connected to ground
Note 6: Each test pornt to have::; 15 pF capaCitive load to ground
9·65
I/)
~
';:
~
LM5528/LM7528 and LM5529/LM7529
tn
o
N
It)
......
schematic diagram
:!:
".....I
v·~
__________. -____. -________,
o
N
It)
It)
:!:
.....I
TEsr:OINT
.....- ....-,
o---l---~-l--===t:~--
OUTPUT A
OUTPUT 8
STROBE 8
fEST POINT B
0---+---------+_-'
0---+---------.
' - - - - _ - H > - -....----....
--OUTPUT
r------~.--OUTPUT
9·75
u
....o
o
o
absolute maximum ratings
SV
-40V
+2SV
30V
5.5V
SOOmW
1500mA
-65"C to +150"C
-55"C to +125"C
O"C to +S5"C
300"C
vee Supply Voltage
V- Supply Voltage
V+ Supply Voltage
(V+ - V-I Voltage Differential
Input Voltage
Power Dissipation (T A; 25°C)
Peak Output Current
Storage Temperature Range
Operating Temperature Range MH0007
MH0007C
Lead Temperature (Soldering, 10 sec)
::J:
::E
e
o
o
::J:
::E
;:::
electrical characteristics
(Note 1)
PARAMETER
TYP
(Note 2)
MIN
CONDITIONS
UNITS
Logical "1" Input Voltage
Vee; 4.5V
Logical "0" Input Voltage
Vee; 4.5V
Logical "1" Input Current
Vee; 5.5V, V ,N ; 5.5V
Logical "0" Input Current
Vee; 5.5V, V ,N ; O.4V
Logical "1" Output Voltage
Vee; 5.5V, lOUT; 30 mA, V ,N ; O.SV
Vee; 5.5V, lOUT; 1 mA, V ,N ; O.SV
Logical "0" Output Voltage
Vee; 4.5V, lOUT; 30 mA, V ,N ; 2.2V
Transition Time to
Logical "0" Output
CL
;
200 pF (Note 3)
50
ns
Transition Time to
Logical "1" Output
CL
;
200 pF (Note 3)
75
ns
V
2.2
O.S
100
1.0
Allowable Values for V- and V+
y'
VOLTS
y~OLTS
-40
/
Y
"
2D
lD
:i1i
0.6
0
;
04
c;
f
-lD
1
10
CA~E
I"
AMtENT
I
02
REGION
-zo
-30
-40
""-
r-..... .....
1
0
0
25
50
75
-
"
100
TEMPERATURE I"C)
mA
V
V- + 2.0
12
~
~ 08
;::
V
(.1A
V
MaXimum Power Dissipation
..
1.5
V t -4.0
V+ - 2 0
Note 1: Min/max limits apply across the guaranteed range of -55"C to +125"C for the MHOO07, and
from O"C to +85"C for the MH0007C, for all allowable values of V- and V+
Note 2: All tYPical values measured at T A = 25'C with V CC =5 0 volts, V- = -25 volts, V+ = 0 volts.
Note 3: Transition time measured from time VIN = 50% value until VOUT Iolas reached 80% of
fmal value
9-76
MAX
125
150
V
3:
%
o
o
o
Interface Circuits
CD
......
!:
:::r:
o
o
o
CD
n
MH0009/MH0009C de coupled two phase MOS clock driver
general description
~.atures
The MH0009/MH0009C is high speed, DC coupled,
dual MOS clock driver designed to operate In
conjunction with high speed line drivers such as
the DM8830, DM7440, or DM7093. The tranSition
from TTUDTL to MOS logic level IS accomplished
by PNP input tranSistors which also assure accl.lrate
control of the output pulse width.
•
DC logically controlled operation
•
Output SWings - to 30V
•
Ol.ltput Currents - In excess of ±500 nA
•
High rep rate -
•
Low standby power
In
excess of 2 MHz
schematic and connection diagrams
2 41, INPUT A
12·Load TO·8 Pockage
., INPUTS
4---,..-+--f
~ 5------~~~
."N.UTI Q
__•
----+-.--t:
V";o+5.0V
412 BIAS ,
\,
,rfI-lINPUTA
v~
v+ .. 1ZV
.j
typical appliclJltion
.,
-----,
v."..-_·,
I
I
I
V·,.+iOV
_-..
.......
FIGURE 1
9·77
(.)
en
o
absolute maximum ratings
::t,
v- Supply Voltage.
oo
Differential (Pm 5 to Pm 3) or
(Pm 5 to Pin 7)
V+Supply Voltage: Differential (Pm 11 to Pm 5)
Input Current: (Pm 2, 4, 6 or 8)
Peak Output Current
Power DIssipation (Note 2 and Figure 2)
Storage Temperature
Operating Temperature: MH0009
MH0009C
Lead Temperature (Soldering, 10 Sec.)
:E
G7
o
o
o
i
electrical characteristics
PARAMETER
-40V
30V
±75 mA
±500 mA
1.5W
_65°C to +150°C
_55°C to +125°C
O°C to 85°C
300°C
(Note 1)
MIN
CONDITIONS
TYP
MAX
UNITS
C'N = .0022,uF
CL = 001,uF
10
35
ns
C'N = 0022,uF
C L = 001,uF
40
50
ns
C'N = 0022,uF
CL = 001,uF
400
440
ns
C'N = 0022,uF
CL = 001,uF
80
120
ns
C'N = 600 pF
C L = 200 pF
10
ns
C'N = 600 pF
C L = 200 pF
15
ns
Pulse Width (50% to 50%)
C'N = 600 pF
CL = 200 pF
tloll
C'N = 600 pF
CL = 200 pF
toN
Pulse Width (50% to 50%)
340
40
70
40
Note 1: Characteristics apply for CirCUit of Figure 1 With V- = -20 volts, V+ = 0 volts, VCC = 50
volts Minimum and maximum limits apply from -5SoC to +12SoC for the MH0009 and from aOc to
-+a5'C for the MH0009C. TYPical values are for T A = 25'C
Note 2: Transient power IS given by P = fel (V+ - V-I 2 watts, where f = repetition rate, CL = load
capadtance, and (V+ - V-I = output sWing
Note 3: For tYPical performance data see the MHOOI3/MHOOI3C data sheet
150~4.-4--+-~~--+--4
! 1.25 1--1"-":"k--+--I-+-4---l
~ 10~+-4"~~~~--+-~
10151-+-4--+"~k-+-4---l
~ 0.5
ffi
o25
"
f-~--l--+--+--I-+--l
o~~-L-J
__L-~-L~
o 25 50 15 100 125 150
TEMPERATURE I CI
FIGURE 2. Maximum Power Dissipation
9·78
120
ns
ns
s::I:
o
o
Interface Circuits
...a
N
.......
s::I:
o
o...a
MH0012/MH0012C high speed MOS clock driver
N
n
general description
features
The MH0012/MH0012C is a high performance
clock driver that IS designed to be driven by the
OM 7830/0M8830 or other line drivers or buffers
with high output current capability. It will provide a fixed width pulse suitable for driving MOS
shift registers and other clocked MOS devices.
• High output voltage sWlngs~ 12 to 30 volts
• High output current drive capabllity~ 1000 mA
peak
• High repetition
100 pF
rate~10
MHz at 18 volts into
• Low standby power~less than 30 mW
schematic and connection diagrams
12-lead TO-8 Package
".
R9
COMP
&
11 !OUTPUT
R1
.....14-+-t-o"
25.
INPUT 2 3 -'V'h-....- '
R2
1K
COMP
4
typical application
TOPVIEW
(ac test CIrcuit)
timing diagram
9-79
(,)
...o
N
absolute maximum ratings
o
v- Supply Voltage
J:
Differential {Pin 1 or 2 to
Pm 5)
Differential (Pin 8 or 9
V r Supply Voltage
:E
........
to Pin 1 or 21
...
30V
:+75 rnA
f.l0DDmA
Input Current (PIn 3 or 7)
Peak Output Current
N
o
o
dc electrical characteristics
J:
PARAMETER
:E
Maximum Output Load-See Figure 2
Power DISSipation-See Figure 1
Stordge Temperature
Operating Temperature MHOO12
MHOO12C
Lead Temperdlure (Soldering, 10 sec)
-40V
15W
-65"C to +150"C
-55"C to +12S"C
O"C to +85"C
300"C
(Note 1)
CONDITIONS
MIN
Logic "1" Input Voltage
(PinS 7 and 3)
V+-V-""20V,V OUT vt -
1,5V
04
TYP
MAX
UNITS
10
20
V
06
V
, 10
V
V- + 20
V
VIN = 20V
Logic "0" Output Voltage
V' - V- = 20V, lOUT'" - lmA,
V 1N =04V
IDe (V- Supply)
V' - V- ::: 20V, V IN = 2 OV
vt
_
15
V' - 07
V
mA
34
60
TYP
MAX
10
15
5
10
ns
35
50
ns
35
45
ns
ac electrical characteristics
CONDITIONS (Note 3)
PARAMETER
MIN
Turn·On Delay (tON)
V' -V-" 20V, Vee'" 5 OV
CL '" 200 pF, f ~ 10 MHz
TA = 25"C
Rise Time (t,)
Turn·Off Delay (tOF F )
Fall Time {ttl
UNITS
ns
Note 1: Characteristics apply for CirCUit of Figure 1 Min and max limits apply from -5SoC to +125°C
for the MHOO12 and from O°C to +85°C for the MH()()12C TYPical values are for T A = 25°C
Note 2: Due to the very fast rISe and fall times, and the high currents Involved, extremely short connections and good by passmg techniques are reqUired
Note 3: All conditions apply for each parameter
Maximum Output Load
vs Voltage Swing vs Rise Times
Power Dissipation
RIse and Fall Times vs
Load Capacitance
40
1.5
~
"
'"
~
5
~ 35
I
~ 30
L (V+ _ V-)
I"
1.0
C =~
30
~
'"~
"'\"
\
\
\~.
~,~
>
20
N
>,
-
;£
10
~r$'
"~ 25
~o
~~ ~ ~. I'o~.r
"'$ :~
~.r
r-,... 'I'-....
...........
;;!
r-.. ....
~
~
~
'~"
;::
~
"'
20
-V+ -
v-= 20V
_TA"25"C
15
.... -t-
10
5
II-
0
0
25
50
75
100
125
0
150 175
400
800
1200
1600
MAXIMUM OUTPUT LOAD IpFI
AMBIENT TEMPERATURE lOCI
Figure 1.
200
400
600
800
1000
LOAD CAPACITANCE. CL IpFI
Figure 2.
applications information
Power DISSipation Considerations
Where
The power diSSipated by the MH0012 may be
diVided Into three areas of operation = ON, OFF
and SWitching The OFF power IS approximately
30 mW and is diSSipated by R2 when Pm 3 IS In
the logiC "1" state The OFF power IS neglibleand
Will be Ignored In the subsequent diSCUSSion The
ON power IS diSSipated pnmanly by 0 3 and Rg
and IS given by'
PON
9-80
== ["rIl IN
IV+ - V-I'
+ - - - 1 DC
R.
(1)
DC = Duty Cycle
'=
ON TIme
ON Time & OFF Time
The transient power Incurred dunng sWitching IS
given by
PAC'" (V+ - v-)2 CLf
VIN-VBE3
liN IS given by - - R - , - - and equatIon (1)
becomes
PON'"
[IV,,-VBE3IIV-1
IV'-V-I']
Rl
+ ~- DC (2)
The total power IS gIven by
PT == PAC + PON
PT
For V IN == 2 5V, V SE3 =0 7V, V+ =OV, V- = -20V,
and DC = 20%, PON == 200 mW
131
For V+ = OV, V- = -20V, C L ::: 200 pF, and
f '= 50 MHz, PAC == 400 mW
s
PM AX
For the above example, PT '" 600 mW
141
~
:I:
o
Interface Circuits
o
....
w
......
~
:I:
MH0013/MH0013C two phase MOS clock driver
general description
features
...oow
The MH0013/MH0013C IS a general purpose clock
driver that IS deSIgned to be driven by DTL or
TTL line drivers or buffers with high output current capability It will provide fixed width clock
pulses for both high threshold and low threshold
MOS deVices. Two external Input coupling capacitors set the pulse width maximum, below which
the output pulse width will closely follow the
Input pulse width or logiC control of output pulse
width may be obtained by uSIng larger value Input
• High Output Voltage SWings-up to 30V
C')
• High Output Current Drive Capability-up to
500 mA
• High Repetition
Rate~up
to 50 MHz
• Pin Compatible with the MH0009/MH0009C
• "Zero" QUiescent Power
capacitors and no Input resistors.
schematic and connection diagrams
12·Lead TO·8 Package
01
.---f.-I!)--12 OUTPUT A
INPUT A,
INPUT A2 4
----+-.....- f
D1
V'
5-----i--~-_+
11 V'
OJ
-!
INPUT8 1 6 - - - - - + -....
INPUTB 2
' - - - f . - _ 1 I 1 OUTPUT B
TOPVIEW
D4
typical applications
+Vcc
C,"
~~PL~~
OUTPUT
1
I
I
I
Ur-----
PUL"--U
INPUT
PULSE
U
OUTPUT:
PULSE
u-:
9-81
(.)
M
....
absolute maximum ratings
o
o
(V+ - V-) Voltage Differential
30V
±75mA
Input Current (Pin 2,4, 6 or 8)
Peak Output Current
±600mA
Power Dissipation (Figure 7)
1.5W
_65°C to +150°C
Storage Temperature
_55°C to +125°C
Operating Temperature MH0013
MH0013C
O°C to +85°C
30aoC
Lead Temperature (Soldering, 1a sec 1/16" from Case)
::J:
::iE
"M
....
o
o
::J:
::iE
electrical characteristics
PARAMETER
(Note 1 and Figure 8)
MIN
CONDITIONS
Logical "0" Output Voltage
logical "1" Output Voltage
IOUT"'SOmA
Power Supply Leakage Current
IV"· V"I" 30V
NegatIVe Input Voltage Clamp
IIN"--10mA
lOUT'" liN
UNITS
MAX
TYP
vI- _ 1 0
IOUT"'-50mA IIN=10mA
louT"'-lOmA IIN=10mA
IIN""lOmA
V
07
v+ - a 5
V- + 1 5
V- + 2 a
v
v
v
100
!JA
v+ -
10
=OmA
v- - 1 2
tdON
v- - 0 8
V
20
35
"
35
50
30
60
"n,
40
50
80
n,
40
70
120
340
420
490
CIN "'00022.uF
t{j OFF (Note 2)
RIN
t1all (Note 2)
",Q,Q
CL "'OOOlj.lF
tlall (Note3)
Pulse Width (50% to 50%) (Note 3)
CIN '" 500 pF
RIN '"
Pulse Width (50% to 50%) (Note 3)
CL
"
"
"
"
"
15
On
20
'" 200 pF
110
Positive Output Voltage Swmg
v+ - 0 7V
V
Negative Output Voltage Swmg
V- + 0 7V
V
Note 1: MinIMax limits apply over guaranteed operating temperature range of _55°C to +125°C for
MH0013 and O°C to +85"C for MH0013C. With V' = -20V and V+ = OV unless otherwISe specified.
TYPical values are for 25°C
Note 2: Parameter values apply for clock pulse width determined by Input pulse width
Note 3: Parameter values apply for Input pulse width greater than output clock pulse width
TABLE I. Typical Drive Capability of One Half MHa013 at laoC Ambient
1V3-V21
VOLTS
FREaUENCY
MH,
PULSE WIDTH
n.
TYPICAL RIN
TYPICAL CIN
_F
28
20
16
"
40
100
0
750
50
200
350
7
10
1600
100
400
700
19
28
20
16
20
200
10
28
20
16
28
20
16
OUTPUT DRIVE
CAPABI LITY IN pF I
RISE TIME
LIMIT nsl
5
14
10
200
0
2300
400
1000
1700
19
34
45
05
500
10
4000
2800
5500
9300
130
183
248
Note 1: Output load IS the maximum load that can be dnven at 70°C Without exceeding the package
rating under the given conditions.
Note 2: The rise time given is the minimum that can be used without exceeding the peak tranSient
output current for the full rated output load.
circuit operation
Input current forced into the base of 01 through
the coupling capacitor C 'N causes 01 to be driven
into saturation, sWinging the output to
drive through R2, turning 02 on. This supplies
current to the load and the output swings positive
to V+ - V SE '
V- + V CE (SAT) + VDIDDE'
It may be noted that 01 always sWitches off
before 02 begins to supply current; hence, high
Internal transient currents from V+ to V- cannot
occur.
When the input current has decayed, or has been
switched, such that 01 turns off, 02 receives base
9·82
3:
::s:::
o
o
""'"
w
.......
3C
typical performance characteristics
FIGURE 1. Output Load vs Voltage
Swing
FIGURE 2. Transient Power vs Rep.
Rate vs CL
FIGURE 3. Transient Power vs Rep.
Rate vs CL
700
700
t r =10ns
30
~
>-,
20
~
~
\\ ,\
.\ \\'\.
\\ ~
g
'"3!
~
""
" ""
10
~
in
~ ~ r--..
20 ns 30 ns 40 ns 50 ns 60 ns
1000
g
~
600
g
600
500
'"3!
500
~
400
""~
300
~
'""""
200
100
2000
10 20
3000
30 40
FIGURE 4. Average Internal Power vs
Output SWing vs Duty Cycle
30
~
I;;,
20
~
10
V
i
30%
100
5,0 60 7:0
10
V . /~
V ~~
l~ I%; V
"
\50%
:;'"
i
.s 3000
w
u
500
""~" 2000
~
400
R1N "'10n
5
25 45
65
85 105 125
AMBIENT TEMPERATURE 1°C)
V
--//
RIN '" 47n
V V
~
II.. '/': ~ V
~
-55 -35 -15
400
AVERAGE POWER 'mW)
:::on ~
R'N' 20n,--j
""~ 1000
300
300
RIN
Z
~
~
=>
~
200
70
DM8830 DRIVER
Vee::: 5V
~
100
50 6,0
FIGURE 5. Typical Clock Pulse Variations FIGURE 6. RIN VSCIN vs Pulse Width
vs Ambient Temperature
w
M
~
'ITP
20 30 4,0
REPETITION RATE IMHz)
g
40%
n
300
200
600
20%
10%
o
o
....
w
400
REPETITION RATE (MHz)
MAXIMUM OUTPUT LOAD (pF)
::s:::
V
./
...
f-ji.g1n
~ :;:;.--
200
100
400
300
PU LSE WIDTH (ns)
FIGURE 7. Package Power Derating
1.5
~
1.0
'"
""
I"
I
,5
25
50
75
I'\.
100
125
150 175
AMBIENT TEMPERATURE rC)
ac test circuit
timing diagram
A
Inpu!puI5l!w,dl~
> clock pulse
WIdth
~"
V
,"
OV
VOUT
F"-=;-t------ V2 ~-16V
v,~
ft
0 tG 5V pulse, f- SOD kHz, DC - 5[1%, t,.~d It
< 10 n.
Figure 8
9·83
(.)
M
....
o
pulse width
o
::J:
:E
.......
Maximum output pulse width IS a function of the
mput driver characterIStiCS and the coupling
capacitance and resistance. Aft~r bemg turned on,
the Input current must fall from Its mitial value
I, N peak to below the input threshold current
I, N min "" VB E fR 1 for the clock driver to turn
off. For example, referring to the test circuit of
Figure 8, the output pulse width, 50% to 50%, IS
given by
....
M
o
o
::J:
:E
+ ROC 'N In liN peak", 400 ns.
liN mm
For operation with the mput pulse shorter than
the above maximum pulse width, the output pulse
width will be directly determined by the input
pulse width.
PWOUT ~ PW'N + td OFF + td ON +
1
"2
(t'all
+ t"",)
Typical maximum pulse width for various C, Nand
R'N values are given In Figure 6.
fan-out calculation
The drive capability of the MH0013 is a function
of system requirements, I.e., speed, ambient tem·
perature, voltage sWing, drive circuitry, and stray
wiring capacity.
The following equations cover the necessary calcu·
lations to enable the fan·out to be calculated for
any system condition. Some tYPical fan·outs for
conditions are given m Table 1.
TranSient Current
The maximum peak output current of the MH0013
IS given as 600 mAo Average transient current reo
qUlred from the driver can be calculated from'
I ~ C L (V+ - V-)
TR
(1)
ThiS can give a maximum limit to the Iqad.
Figure 1 shows maximum voltage sWing and
capacitive load for various rISe times.
1. TranSient Output Power
fhe average transient power IP AC) diSSipated IS
equal to the energy needed to charge and discharge
the output capacitive load ICc) multiplied by the
frequency of operation IF).
PAC ~ C L X IV+ - V-)2 X F
(2)
Figures 2 and 3 show transient power for two d,f·
ferent values of (V+ - V-) versus output load and
frequency.
2. Internal Power
"0" State
Negligible 1<3 mW)
"I" State
(3)
9·84
Figure 4 gives varIOus values of internal power
versus ouptut voltage and duty cycle .
3 Input Power
The average Input power IS a function of the Input
current and duty cycle Due to Input voltage
clamping, thiS power contribution IS small and can
therefore be neglected. At maximum duty cycle of
50%, at 25" C, the average Input power IS less than
10 mW per phase for R,NC 'N controlled pulse
Widths For pulse Widths much shorter than
R,NC ,N , and maximum duty cycle of 50%, Input
power could be as high as 30 mW, since liN peak IS
maliltained for the full duration of the pulse
Width
4 Package Power DISSipatIOn
Totdl Average Power
c
TranSient Output Power +
Internal Power
Input
Power
TYPIcal Example Calculation for One Half
MHOOl3C
How many MM506 shift regIsters can be driven by
an MH0013C driver at 1 MHz uSing a clock pulse
Width of 400 ns, rISe tIme 30-50 ns and 16 volts
amplitude over the temperature range 0-70°C?
Power Dissipation
From the graph of power dISSIpation versus tem·
perature, F,gure 7, It can be seen that an
MH0013C at 70°C can dISSIpate lW WIthout a heat
Sink, therefore, each half can dISSipate 500 mW.
TranSIent Peak Current Limitation
From F,gure 1 (equation 1), It can be seen that
at 16V and 30 ns, the maximum load that can be
driven IS limited to 1140 pF.
Average I nternal Power
Figure 4 (equation 3) gives an average power of
102 mW at 16V 40% duty cycle.
Input power will be a maximum of 8 mW
Transient Output Power
For one half of the MH0013C
500 mW = 102 mW + 8 mW
+ transient output power
390 mW = transient output power
USing Figure 2 (equation 2) at 16V, 1 MHz and
390 mW, each half of the MH0013C can drIVe a
1520 pF load. ThiS IS, however, In excess of the
load derived from the transient current limitation
(Figure 1, equation 1), and so a maximum load
of 1140 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load IS 80 pF. Therefore the number
1140
of deVices driven IS 80 or 14 registers.
For nonsymmetrlcal clock Widths, drive capability
IS Improved
s::I:
o
o
Interface Ci rcuits
MH0025/MH0025C two phase MOS clock driver
N
U1
........
general description
features
:I:
The MH0025/MH0025C IS monolithic, low cost,
two phase MOS clock driver that IS designed to be
driven by TTLlDTL line drivers or buffers such as
the DM932, DM8830, or DM7440 Two input
coupling capacitors are used to perform the level
shift from TTLlDTL to MOS logic levels. Optimum
performance In turn-off delay and fall time are
obtained when the output pulse IS logically controlled by the Input However, output pulse widths
may be set by selection of the Input capacitors
eliminating the need for tight Input pulse control
•
s:
o
o
8-lead TO-5 or 8-lead dual-In-Ilne package
N
U1
• High Output Voltage SWings-up to 30V
• High Output Current Drive Capability-up to
15A
•
(")
Rep Rate 1 0 MHz Into> 1000 pF
• Driven by DM932, DM8830, DM7440(SN74401
• "Zero" Qu lescent Power
connection diagrams
Dual-I n-Line Package
Metal Can Package
v'
NC
8 N C.
1
7 OUTPUT A
INPUT A 2
V-
v-
6
3
INPUT B 4
Note Pm 4 eonnected to case
TOP VIEW
v'
5 OUTPUT B
TOP VIEW
typical application
ac test circuit
timing diagram
Inputw~veform
PRR '05MHz
V OlJT 1
Vp p ~ 5 OV
A Input pulse width
clock pulse
~
5V
V
I~'
width
OV
tr~tf<10ns
Pulsew,dth
A 1 Ups
V' = OV
B 200ns
BlnputPlilsewldth~90%
sets cloc~ pulse
width
Clock pliise
uutput
10%
----~5V
' -_ _ _ _ _ _ OV
t~ ON
10%
1-1-',..'"_'>_ _ _ _
V3 " oV
10%
V OUT 2
Vour
""01,sa selected high speed NPN switchmgtransistor
~-'---"""'-1-+----------- V2=-16V
9-85
(.)
It)
N
absolute maximum ratings
o
o
::r:
:E
.......
(v+ - V-)'Voltage Differential
I nput Current
Peak Output Current
Power Dissipation
Storage Temperature
Operating Temperature MH0025
MH0025C
Lead Temperature (Soldering, 10 sec)
It)
N
o
o
::r:
:E
30V
100 mA
L5A
See Curves
-65°C to +150°C
-55°C to +125°C
O°C to +85°C
300°C
electrical characteristics
PARAMETER
(Note 1) See test circuit.
CONDITIONS
TYP
MIN
T dON
CIN ~ .001 !iF
T rtse
T doFF (Note 2)
>-
T lall (Note 2)
RIN ~
~
CL
on
.001 !iF
T lall (Note 3)
P.W. (50% to 50%) (Note 3)
VIN ~ OV, lOUT ~ -1 mA
UNITS
15
30
ns
25
50
ns
30
60
ns
60
90
120
ns
100
150
250
ns
500
ns
V+ - 0.7V
v
'"
Positive Output Voltage SWing
MAX
V+ - 1.0
v
Negative Output Voltage SWing liN ~ 10 mA, lOUT ~ 1 mA
Note 1. MiniMax limits apply aCfOSS the guaranteed operating temperature range of _55°C to +12SoC
for MH0025 and O°C to 85°C for MH0025C. TYPical values are for +25°C
Note 2. Parameter values apply for clock pulse Width determined by Input pulse Width.
Note 3. Parameter values apply for Input pulse Width greater than output clock pulse Width
typical performance
Package Power Derating
Transient Power vs Rep. Rate
DC Power (POC) vs Duty Cycle
160
_.- MH0025H &MH0025CH STILL AIR
14 _
12
0,6
0.4
"l3
::
ill
i5
'"
1O
f--+---+-+---i'r'~!--+-+---i
02~~-+-+++'~-r~
25
50
60
~
40
0
20
u
75 100 125 150
10
TEMPERATURE I'CI
15
=(V+
~
~...
2800
2400
2000
~ 1600
~ 1200
C>
800
c(
::
400
0
\
\1\
\.
I\.
~/
V
,
MHoom: v
.,
"
.......
.' i'o. ....... '"
lOV TA
l~
IP'
10
20
40
50
r-
--
OUTPUT PULSE wrOTH VS C'N FOR lONG
INPUT PUts£S
f--
rr-
100
Hq....
-++-H-+--iIH-+-t-I
200
600
1~00
tiN
~
S
v+ _V-
60
IV' - V-I' (OCI
Poe'" - - 1 ' - -
- v-)2f CL
r-...
::~:;~Nvv_ ~ v: ~~l~VT:~ ~oro~ c~
(f) Ok) (V+ _ V-)2
30
I'- .....
(P MAX ) (1 k) - (V+ - V-)2 (DC)
9·86
./
211VT.25C
FREQUENCY (MH,I
-::;
/ / /v. -)'1k-
C
0,2 04 0.6 0,8 1 0 1 2 1 4 1 6 1.8 2,0
Cl
X
DUTY CYCLE (%1
1100
MHOOl5CNV
19
/
/
Output P.W. Controlled by CIN
,11'1,
3200
<.lv\116V
I/j~
0
20
Maximum Load Capacitance
~
/
PULSE REPETITION RATE (MHz)
PAC
DC
r/
80
OL-L-~~-wLL-L~~
0
/
;:: 100
fI"k\
f---t--t---1"'-:''I<-+--1-+---i
-25
/
oS 120
1.0 ~----i'.C-+-+-+--+--+--I
08
X
V' - v-· 20V/
140
MH0025CN SOLDERED INTO PC
BOARD WITH 8 Co CON~UCTORS
2 OZ. 03 IN WIDE
1400 1800
(pFl
2200
70 85
s:
:I:
o
o
applications information
N
Circuit Operation
Input current forced Into the base of 0 1 through the
cou pll ng capacitor C 'N causes 0 , to be driven Into
saturation, sWinging the output to V- + VcE(satl +
VOlode'
When the Input current has decayed, or has been
sWitched, such that 0 , turns off, O2 receives base
drive through R2 , turning O2 on. This supplies
current to the load and the output sWings positive
to V+ - V SE '
It may be noted that 0 , must sWitch off before
O2 begins to supply current, hence high Internal
transients currents form V- to V+ cannot occur.
~;
J '
U'I
culatlons to enable the fan·out to be calculated
for any system condition
.......
Transient Current
:I:
s:
o
o
The maximum peak output current of the MH0025
IS given as 1.5A. Average transient current required
from the driver can be calculated from
C L (V+ - V-I
I~---
N
U'I
(")
(11
t,
Typical rise times into 1000 pF load is 25 ns
For V+ - V- ~ 20V, I ~ O.SA.
Transient Output Power
The average transient power (P,cl dissipated, IS
equal to the energy needed to charge and discharge
the output capacitive load (CLI multiplied by the
frequency of operation (fl.
...-------.-or
1
t)'
....
"'T' c,~
+-~
I
II\IPUT
J", ~
-<> OUTPUT
,:;+---...--I
L-__
~
__
~
PAC ~ C L X (V+ - V-1 2
X
f
(21
For V+ - V-~ 20V, f ~ 1.0 MHz, C L ~ 1000 pF,
PAC ~ 400 mW.
I nternal Power
______
~,
FIGURE 1. MH0025 Schematic (One·Half Circuit)
Fan-Out Calculation
The drive capability of the MH0025 IS a function
of system requirements, I.e. speed, ambient tem·
perature, voltage SWing, drive CIrCU Itry, and stray
wirl ng capacity.
The following equations cover the necessary cal·
"0" State
Negligible «3 mWI
"1" State
(V+ _ V-12
~
~-R-2---
~
SO mW for V+ - V- ~ 20V, DC ~ 20%
x Duty Cycle
(3)
Package Power Dissipation
Total average power
Internal power
~
transient output power +
example calculation
How many MM506 shift registers can be droven by
an MH0025CN driver at 1 MHz uSing a clock pulse
width of 200 ns, rise time 30-50 ns and 16V am·
plltude over the temperature range 0-70°C?
Power D ISSI patlon:
At 70°C the MH0025CN can diSSipate 630 mW
when soldered Into printed CirCUit board
TranSient Peak Current Limitation:
From equation (11, It can be seen that at 16V and
30 ns, the maximum load that can be driven IS
limited to 2S00 pF.
Average Internal Power:
Equation (31. gives an average power of 50 mW at
16V and a 20% duty cycle.
For one half of the MH0025C, 630 mW 72 can be
diSSipated.
315 mW
~
50 mW + tranSient output power
265 mW
~
transient output power
USing equation (2) at 16V, 1 MHz and 250 mW,
each half of the MH0025CN can drive a 975 pF
load. ThiS IS, less than the load Imposed by the
transient current limitation of equation (1) and
so a maximum load of 975 pF would prevail
From the data sheet for the MM506, the average
clock pulse load is SO pF. Therefore the number
975
of deVices driven IS 80 or 12 registers.
9-S7
u
CD
N
Interface Ci rcuits
o
o
::t
~
.......
CD
N
MH0026/MH0026C 5 MHz two phase MOS clock driver
o
o
general description
::t
~
The MH0026/MH0026C is a low cost monolithic
high speed two phase MOS clock driver and interface circuit. Unique circuit deSign along with
advanced processing provide both very high speed
operation and the ability to drive large capacitive
loads. The deVice accepts standard TTLlDTL outputs and converts them to MOS logiC levels. I t may
be driven from standard 54/74 series gates and
flip-flops or from drivers such as the DM8830 or
DM7440. The MH0026 IS Intended for applications
In which the output pulse width IS logically controlled' I.e., the output pulse width is equal to the
Input pulse width.
•
•
The MH0026 IS Intended to fulfill a wide variety of
MOS interface requirements. As a MOS clock driver
for long silicon gate shift registers, a single deVice
can drive over 10k bits at 5 MHz. S'x devices provide Input address and precharge drive for a 8k by
16 bit MM 1103 RAM memory system. Information
on the correct usage of the MH0026 In these as well
as other systems IS Included In the applicatIOn section starting on page 5. A thorough understanding
of its usage will Insure optimum performance of the
deVice.
features
•
•
•
•
•
Low power consumption In MOS "0" stat82 mW
Drives to O.4V of GND for RAM address drive
Fast rISe and fall tlmes-20 ns with 1000 pF load
High output sWlng-20V
High output current drive-±1.5 amps
TTLlDTL compatible Inputs
High rep rate-5 to 10 MHz depending on load
The deVice IS available In 8-lead TO·5, one watt
copper lead frame 8-pln mlnl·DIP, and one and a
half watt TO-S packages.
schematic diagram
connection diagrams
11/2 of CirCUit Shown)
S-Lead TO-5
V'
EXTERNAL
C"
DO
<>1 ~NPUT
MHOO26H/MHOO26CH
8-Lead Dual-I n-Llne Package
OUTPUT
"B'·
INPUTA
z
J OUTPUrA
v- 3
6
INPUT B 4
v'
5 OUTPUT
TOPVIJ:W
MHOO26CN
D5
12· Lead TO-S
v-
"
MH0026G/MH0026CG
9-88
~
3:
o
o
::J:
absolute maximum ratings
v+ -V- Differential Voltage
I nput Current
Input Voltage (V ,N - V-I
Peak Output Current
Power DIssipation
Operating Temperature Range
22V
100mA
5.5V
1.5A
See curves
-55°C to +125°C
O°C to 85°C
-65°C to +150°C
300°C
MH0026
MH0026C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
N
0')
.......
3:
o
o
::J:
N
0')
(')
dc electrical characteristics
(Notes 1 & 2)
LIMITS
CONDITIONS
PARAMETER
LogiC "1" Input Voltage
Y OUT = V- + 1.0Y
LogiC "1" Input Current
Y'N - V- = 2.5Y, V OUT = V- + 1.0V
10
= y+ - 1.0Y
Y'N - Y- = OY, Y OUT = y+ - 1.0V
Logic "0" Output Yoltage
y+ = +5.0Y, V- = -12.0V
y+ -1.0
Y'N - Y- = OAV
Logic" 1" Output Yoltage
V+ = +5.0Y, YY'N = -9.5Y
Logic "1" Output Yoltage
Y'N - Y- = 2.5V
"ON" Supply Current
y+ - Y- = 20Y, Y'N - Y-
"OF F" Supply Current
y+ - Y-
Y- + 0.5
Y'N - Y-
= 2.5V
= O.OV
V
Turn-Off Delay (tOFF)
5.0
= 17Y, CL = 250 pF
= 17Y, CL = 500 pF
-11.0
Y
Y- + 1.0
Y
30
40
mA
10
100
JlA
12
ns
15
ns
(Notes 1 & 2, AC test circuit, T A
5.0
= 25°C)
7.5
12
ns
12
CL = 1000 pF
Falltlme (tf) - Note 3
Y
JlA
Y
V+ - 0.7
-11.5
Turn·On Delay (tON)
V+ - Y-
4.3
mA
= -12.0Y
ac electrical characteristics
y+ - Y-
0.4
-10
-0.005
4.0
Y'N =-11.6
Logic "0" Output Yoltage
Rise time (t,) - Note 3
15
0.6
Y OUT
LogiC "0" Input Current
UNITS
V
1.5
2.5
LogiC "0" Input Yoltage
= 20Y,
MAX
TYP
MIN
= 17V, CL = 250 pF
V- = 17V, CL = 500 pF
15
18
ns
20
35
ns
V+ - Y-
10
V+ -
12
16
ns
17
25
ns
CL
= 1000 pF
Note 1: These specifications apply for V+ - v-
=
10V to 20V, CL
=
ns
1000 pF, over the temperature range -55°C to +125° C
for the MH0026 and O°C to +85°C for the MH0026C, unless otherWise specified.
Note 2: All typical values for the TA = 25 C
Q
Note 3: Rise and fall time are given for MOS logiC levels,
fall. See waveforms on the following pages.
1
e , rise time
IS
transistion from logiC "0" to logiC "1" which is voltage
ac test circuit
switching time
waveforms
v+ ~ ov
;tl>-h:y
...:ih"~ T·:.)'It-
1.~:J
INPUT
Q----+-J1
II
I
MHIlD26
I
L~p~
V-~-21l0V
...
INPUT~
/
OUTPUT-
aUTeur
t"
-
9-89
(.)
CD
N
typical performance characteristics
o
o
::t
:E
.......
12
N
10
TO·5 & DIP Power Ratings
o
::t
:E
400
MH0026G AND MH0026CG IN
MH0026CN SOLDERED TO PC
CD
o
--
!
z
0
>=
DB
f
~
0
06
a:
04
~
2
~OARD WlTH 'CU CONDUCTORS
_202, OliN WIDE
~
!
INSTILLAIRWlTHClIP
z
~ONHEATSINK
.........
0
::>=
i'-.. ....
17 ....
MH002&H& MHOOZ6CH
IN STILL AIR
02
_
MHOO28H'ANDMH'OO28CH
25
50
15
ill
15
~
1.0
is
a:
~
100
-
20
Cl =2000 P
BOO
100
a:
BOO
2
....
500
~
~ 400
300
a:
....
200
I
100
"
25
II.
I'!;...
...
"....
V
8.0
CL
100
40
125
10
~
65
>
I--"
15
1:l
40
50
/
V.
,
..,,-
l>'
/. V V
(V~ _ V-)2
~" PDc=~(DC)
10
150
20
30
40
50
60
10
BO
DUTY CYCLE (%1
Input Current vs Input Voltage
14
=0
~
V+ -V- = 20V
f-"
"....
oS
~
12
TA =25'C
v+" 20V
v-= ov
10
1/
~
V
5
V
~
V
V+ -V- = 17V
_.-J
f-"
6.0
30
Bo
I
oS
~
~
Cl 200p,t...
20
r> ~
120
DUTY CYCLE = 20%
f:::1MHz
I I
10
r--.....
15
/'
200
16
85
1000 pF
....rr
50
1/
v· - V·= 20V_ ./
v· - v: = 1JV '-, V
v>-v =12~)(
AMB1ENTTEMPERATURE (OCI
VI
·1 1
V-
........
240
TA =25°C
Cl .:" 0
~
2 160
STlY AIR
150
Cl - 500pF
I I
J
!O
oS
Supply Current vs Temperature
I I
/
I
il!
"
CL
2BO
1/
MH0026G AND
MHOj26CG liN
05
AV+.V-=17V
I
...... ,
...........
Transient Power (P ACI vs
Frequency
900
320
TYPE 215-1 9 OR EQUIV I
a:
2
125
360
I- ~~I!~ :I~~~~T:E~~='~~OY
-
25
AMBIENT TEMPERATURE ("CI
!O
oS
DC Power (PDCI vs
Duty Cycle
TO·8 Pack_ Power Rating
30
-15 -50 -25
0
25
50
05
15 100 125
10
20
15
25
INPUT VOLTAGE (VI
FREQUENCY (MHd
TEMPERATURE ('C)
Rise Time YS Load Capacitance
Fall Time vs Load Capacitance
Optimum Input Capacitance vs
26
Output Pulse Width
25
800
V+ -V·=2DV
v+ - V-",'15V to 20V
]
20
]:
~
....
v+
-V-"ZOV
..-:;;;
20
~~;;.
V+ -V-" 17V
15
w
....%e>
!
....~
15
./
~
!
g;
....
11
I-~+ -~. =2~V
CIN
I- RD= 5011
l
tON
10
"
,/
l/ ~
tOFF
./
/"
-15 -50 -25
0
25
20
!w
~
II
o
200
50
400
600
BOO
~
~
200
~
100
1000
200
15
10
I I
:!
~....
~
~
:;:
CL -0
-15 -50 -25
BOO 1000 1200
l-
V
20
I
I
15 100 125
600
Fall Time vs Temperature
25
V+-V-=2DV
C~F
l ~:;;-
r-- I-
400
INPUT CAPACITANCE, C'N (pFI
CL " 1000 pF
I
I
I
............
TEMPERATURE I"C)
9·90
V
~
w
I
0
TA =25°C
300
Rise Time vs Temperature
25
I
=Cl '" 1000 pF
.,
Cl = 1000 pF
LOAO CAPACITANCE (pF)
Turn-On & Turn-Off Time
vs Temperature
!
400
TA = 25"C
LOAO CAPACITANCE (pFI
14
500
~
~....
Ro::: 50n
Ro " SOn
TA = 25°C
600
i
~
V
10
~
,. "
100
Vi= 20V
V'
~
-
C'IO~"'""
15
I---"
Cl~~
10
J
V
I--'
CL = 0
I
o
0
25
50
15
TEMPERATURE rCI
100 125
I
-15 -50 -25
0
25
50
15 100 125
TEMPERATURE I"CI
s::::I:
typical applications (cont.)
o
o
N
0)
AC Coupled MOS Clock Driver
........
.,v
s::::I:
o
o
G,'
MH0026CN
N
1
0)
TWO PHASE
CLOCK TO
(")
SHIFT REGISTERS
1000pF
~
54/74SER1E$
GATES AND FLOPS
-12V
"See apphcalmnssectlOn on page 5fol detailed mformatumon mput!o IItPII'tdeslllncllterlOr
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)
t17V
100pF
100pF
MHOO26CN
1
TO ADDRESS
LINES ON
MM1103TVPE
MEMORY SYSTEM
1/2DM740D
Precharge Driver for MOS RAM Memories
..
CONTROl.
r+-+---+----~~
MEMORI
SHEeT
9-91
(..)
cc
N
o
o
typical applications
::c
DC Coujlled MOS Clock Driver
,:::E
+50V
CC
N
o
o
::c
"
:::E
,10UlPOT
lNPU1_'"1"........"
<>-+--
-12 V
Logicelly Controll
...._ _...!£.I
INPUT '"
TOADamONAL
} SHIFT flEGI~TERS
If,
...-----....----0-",
f'----1
~
•
b
CLtlCK1NPUT-2fo
MESHOTDUTPuT-ADJPULSeWIOTH
PHASE ONE outPut
PHASEi'WD OUTPUT
9-92
s:
J:
o
application information
o
1.0 I ntraduction
The MH0026 IS capable of delivering 30 watts
peak power (1.5 amps at 20V needed to rapidly
charge large capacitative loads) while Its package IS
limited to the watt range. This section descnbes
the operation of the circuit and how to obtain
optimum system performance. If additional design
information is required, please contact your local
National field application engineer.
N
a simplified diagram, 0] (Figure 3) provides 0.7V
dead zone so that 0, IS turned ON for a nsing
input pulse and O 2 OFF pnor to 0] turning ON a
few nanoseconds later. O2 prevents zenenng of the
emltter·base junction of O 2 and provides an initial
discharge path for the load via 0, Dunng a falling
input, the stored charge In 0, is used beneficially
to keep 0, ON thus preventing 0, from conduct·
ing until 0] IS OFF. 0] stored charge is quickly
discharged by means of common·base transistor
en
........
s:
J:
o
o
N
en
(")
04.
2.0 Theory of Operation
Conventional MOS clock dnvers like the MH0013
and similar devices have relied on the CirCUit
configuration In Figure 1. The AC coupling of an
input pulse allows the device to work over a wide
range of supplies while the output pulse width
may be controlled by the time constant - R] XC] .
The complete CirCUit of the MH0026 (see sche·
matlc on page 1) basically makes Darllngtons out
of each of the transistors in Figure 3.
, - - -....-ov·
.....- ...-ov·
EXTERNAL
C1
IN
+-14"'-0
EXTERNAL
C1
IN
OUT
OUT
<>-1 f-<'
FIGURE 1. Conventional MOS Clock Drive
O2 provides 0.7V of dead·zone thus preventing OJ
and O 2 from conducting at the same time. In
order to drive large capacitive loads, 0] and O 2
are large geometry devices but Cob· now limits
useful output rise time. A high voltage TTL output
stage (Figure 2) could be used; however, during
switching until the stored charge is removed from
0], both output devices conduct at the same time.
This is familiar in TTL with supply line glitches in
the order of 60 to 100 mAo A clock driver built
this way would Introduce 1.5 amp spikes into the
supply lines.
ExTERNAL
C1
IN
<>-1 f-<'
OUT
<>-1 f-o
D1
FIGURE 3.
Simplified MH0026
When the output of the TTL Input element (not
shown) goes to the logic "1" state, current IS
supplied through C 'N to the base of 0] and O 2
turning them ON, and 0 3 and 0 4 OF F when the
input voltages reaches 0.7V. Initial discharge of
the load as well as E·B protection for 0 3 and 0 4
are provided by 0] and O2 . When the input
voltage reaches about 1.5V, 0 6 and 0 7 begin to
conduct and the load IS rapidly discharged by 0 7 .
As the Input goes low, the input side of C, N goes
negative with respect to V- causing 0 8 and 0 9 to
conduct momentarily to assure rapid turn·off of
O2 and 0 7 respectively. When 0] and O 2 turn
OFF, Darlington connected 0 3 and 0 4 rapidly
charge the load toward V+ volts R6 assures that
the output will reach to within one VB E of the
V+ supply
The real secret of the device's performance IS
proper selection of transistor geometries and resis·
tor values so that 0 4 and 0 7 do not conduct at
the same time while minimizing delay from Input
to output.
3.0 Power Dissipation Considerations
FIGURE 2.
Alternate MOS Clock Drive
.Unlque cirCUit design and advanced semiconductor
processing overcome these clasic problems allow·
ing the high volume manufacture of a device, the
MH0026, that delivers 1.5A peak output currents
with 20ns rISe and fall times into 1000pF loads. In
There are four considerations In determining
power dissipatIOns.
1 Average DC power
2. Average AC power
3. Package and heat Sin k selection
4. Remember-2 dnvers per package
9·93
u
CD
N
application information (cont.)
o
o
The total average power dissipated by the MH0026
is the sum of the DC power and AC transient
power. The total must be less than given package
power ratings.
J:
:!!
.......
CD
N
Thus for RAM address line applications, package
type and heat sink technique will limit drive
capability rather than AC power.
3.2 AC Transient Power (per driver)
o
o
AC Transient power IS given by:
J:
Since the device dissipates only 2mW with output
voltage high (MOS logic "0"), the dominating
factor in average DC power is duty cycle or the
percent of time in output voltage low state (MOS
logic "1"). Percent of total power contributed by
Poc is usually neglible in shift register applications
where duty cycle is less than 25%. Poc dominates
in RAM address line driver applications where
duty cycle can exceed 50%.
:!!
POC ~ (V+ - V-I X (is(LDW)) X
(
ON time
)
OFF time-ON time
or Poc = (Output Low Power) X (Duty Cycle)
Example 1: (V+
@
= +5V,
(V+ - V-I
V-
=
-12V)
a) Duty cycle = 25%, therefore
Poc = 17V X 40mA X 17/20 X 25%
Poc = 145mW worst·case, each side
Poc = 109mW typically
b) Duty cycle = 5%
Poc = 21mW
c) See graph on page 3
The above illustrates that for shift register applica·
tions, the minimum clock width allowable for the
given type of shift register should be used in order
to drive the largest number of registers per clock
driver.
Example 2: (V+
= +17V, V- = GND):
a) Duty cycle = 50%
Poc = 290mW worst·case
Poc = 21BmW typically
b) Duty cycle = 100%
Poc = 5BOmW
9-94
strays and wiring)
Example 3: (V+
= +5V,
V-
= -12V)
C L (nF) X 10- 9
DC Power is given by:
IS(LOW) = Is
C L = Load capacitance (including all
PAC = 17 X 17 X f(MHz) X 10 6 X
3.1 DC Power (per driver)
where:
where: f = frequency of operation
PAC = 290mW per MHz per 1000pF
Thus at 5MHz, a 1000pF load will cause any driver
to dissipate one and one half watts. For long shift
registers, a driver with the highest package power
rating will drive the largest number of bits for the
lowest cost per bit.
3.3 Package Selection
Power ratings are based on a maximum junction
rating of 175°C. The following guidelines are
suggested for package selection. Graphs on page 3
illustrate derating for various operating tempera·
tures.
3.31 TO-5 ("H") Package: Rated at 600mW still
air (derate at 4.0mWtC above 25°C) and 900mW
with clip on heat sink (derate at 6.0mWtC above
25°C). This popular hermetic package is recom·
mended for small systems. Low cost (about 10<,1)
clip-on-heat Sink increases driving capability by
50%.
3.32 B·Pin ("N") Molded Mlni·DIP: Rated at
600mW still air (derate at 4.0mWtC above 25°C)
and 1.0 watt soldered to PC board (derate at
6.6mW/oC). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly
where automatic insertion is used. (Please note for
prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down.)
3.33 TO-B ("G") Package: Rated at 1.5 watts
stili air (derate at 10mWtC above 25°C) and 2.3
watts with cil p on heat Sink (Wakefield type
215-1.9 or equivalent-derate at 15mWtC).
Selected for its power handling capability and
moderate cost, this hermetic package will drive •
very large systems at the lowest cost per bit.
s:
:I:
o
application information (cont.)
o
3.4 Summary-Package Power Considerations
In
pFI
10-3
= --;;-
pF I
=
Table I illustrates MH0026 drive capability under
various system conditions.
0)
by:
o
o
t +t
(PW)OUT= (PW),N+¥= PW ,N +25ns
S X 10- 3 X
Two external Input coupling capacitors are reqUired to perform the level translation between
TTLlDTL and MOS logiC levels. Selection of the
capacitor Size is determined by the desired output
pulse width. Minimum delay and optimum performance IS attained when the voltage at the input
of the MH0026 discharges to just above the
deVices threshold (about 1.5V). If the input is
allowed to discharge below the threshold, to F F
and tl will be degraded. The graph on page 3
shows optimum values for C'N vs desired output
pulse Width. The value for G'N may be roughly
predicted by:
Pm "X ImWI X SOO - V S 2 X Dc X 103
V S ' X SOO X f(MHzI
Where: n = number of drivers per pkg. (lfor
the MH0026)
Pmax{mw)(T A , pkg) = Package power
rating In mililwatts for given package,
heat sink, and max, ambient temperature (See graphs)
Req
:I:
The MH0026 is intended for applications in which
the input pulse width sets the output pulse width;
i.e., the output pulse width is logically controlled
by the input pulse. The output pulse width is given
X
(V"" - V I' X R,q X f(MHzI
In
s:
Time in output low + Time in output high state
4.0 Pulse Width Control
Pm"xlmW) (T A,pkgl X R,q - (V+ - V-I' X lOci X 103
C L (max
0)
.......
Time in output low state
The maximum capacitative load that the MH0026
can drive is thus determined by package type, heat
sink technique, ambient temperature, AC power
(which is proportional to frequency and capacitive
load) and DC power (which is principally determined by duty cycle). Combining equations previously given, the follOWing formula is valid for
any clock driver with negligible input power and
negligible power In output high state:
C L (max
N
Dc = Duty Cycle =
= equivalent Internal resistance
= (V+ - V-)/I S { Low) = 500 ohms (worst
case over temperature for the MH0026 or
660 ohms typically)
Req
For an output pulse width of 500ns, the optimum
value for C, N is:
Vs = (V+ - V-I = total supply voltage across
device
C, N = (2 X 10- 3 )(500 X 10-9
)
==
1000pF
TABLE 1. Worst Case Maximum Drive Capability for MH0026*
TO-8WITH
HEAT SINK
PACKAGE TYPE
TO-8
FREE AIR
MINI· DIP
SOLDERED DOWN
TO·S AND MINI·DIP
FREE AIR
Max.
Max
Operating
Ambient
~
60°C
8SoC
60°C
8S'C
60'C
8S'C
60a C
85°C
-+
Frequency j
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.Sk
SOOkHz
10%
6.Sk
5.1k
4.1k
3.2k
27k
2k
1.5k
1MHz
20%
2.9k
22k
1.8k
1.4k
1 1k
5.8k
1.1k
840
600
430
2MHz
25%
850
650
S50
400
280
190
SMHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
-
*Note
l.4k
1.1k
Values In pF and assume both Sides In use as non-overlaplng 2 phase driver, each Side operating
at same frequency and duty cycle With (V+ - V~)
17V For loads greater than 1200 pF,
rise and fall times Will be limited by output current, see Section 5
a
9-95
N
n
u
CD
N
application information (CO nt.)
::I:
5.0 Rise & Fall Time Considerations(Note 3)
o
o
:E
.........
The MH0026's peak output current is limited to
1.5A. The peak current limitation restricts the
maximum load capacitance which the device is
capable of driving and is given by:
CD
N
o
o
::I:
I = CL
:E
The rise time,
predicted by:
t"
dv
at ,;;;
1.5A
7.0 Clock Line Cross Talk
for various loads may be
t, = (6V)(250 X 10- '2 + C L )
Where: 6V = The change In voltage across C L
=
V+ - VC L = The load capacitance
For V+ - V- = 20V, C L = 1000pF, t, is:
t,
=
(20V) (250 X 10- '
= 25ns
2
+ 10- 12 )
For small values of CL , equation above predicts
optimistic values for t,. The graph on page 3
shows tYPical nse times for various load capaci'
tances.
The output fall time (see Graph) may be predicted
by:
tf
2.2R(C s +~)
=
hFE
practice, determination of a value for L IS rather
difficult. However,R, is readily determined emper·
Ically, and values tYPically range between 10 and
51 ohms. R, does reduce rise and fall times as
given by:
+1
At the system level,voltage spikes from CPl may be
transmitted to CP2 (and vlce·vers,,) during the
transition of CPl to MOS logiC "1 ". The spike IS
due to mutual capacitance between clock lines and
IS, In general, aggravated by long clock lines when
numerous registers are being driven. TranSistors
0 3 and 0 4 on the CP2 Side of the MH0026 are
essentially "OFF" when CP2 is In the MOS logic
"0" state since only micro-amperes are drawn
from the device. When the spike is coupled to CP2,
the output has to drop at least 2 VB E before 0 3
and 0 4 come on and pull the output back to V+.
A simple method for eliminating or minimizing
this effect is to add bleed resistors between the
MH0026 outputs and ground causing a current of
a few milliamps to flow In 0 4 , When a spike is
coupled to the clock line 0 4 is already "ON" with
a finite hie' The spike is qUickly clamped by 0 4 ,
Values for R depend on layout and the number of
registers being driven and vary typically between
2k and 10k ohms.
6.0 Clock Overshoot
8.0 Power Supply Decoupling
The output waveform of the M H0026 can over·
shoot. The overshoot is due to finite inductance of
the clock lines. It occurs on the negative gOing
edge when 0 7 saturates, and on the positive edge
when 0 3 turns OFF as the output goes through
V+ - V be . The problem can be eliminated by
placing a small series resistor In the ouput of the
MH0026. The critical valve for R,= 2yLlCQ where
L is the self·inductance of the clock line. In
9·96
Power supply decoupling is a Widespread and
accepted practice. Decoupling of V+ to V- supply
lines With at least 0.111F non inductive capacitors
as close as pOSSible to each MH0026 is strongly
recommended. This decoupling is necessary
because otherwise 1.5 ampere currents flow during
logiC transition in order to rapidly charge clock
lines.
s:
:::t
o
o
Interface Circuits
N
.....
n
MH0027C dual high speed MOS interface driver
general description
The MH0027C is a dual high current active pull-up
designed to operate with a high current sink such
as the DH0034 or lM7541 A and thus provides fully
TTL compatlbte DC coupled Inputs The partitioning of current sinks and sources Into separate
packages provides higher overall power drive capability while minimizing system cost. The device is
intended for use as a drover for MOS RAM memories
such as the MMll03. The MH0027C IS capable of
sourcing over 1 ampere peak current with a rosetime of 25 ns Into 600 pF loads_
•
Peak output current In excess of 1 ampere
•
Fully compatible with DH0034 dual level shifter
and lM75450 series peropheral drivers.
•
Wide operating supply range -
•
Output voltage clamp
•
low power dissipation logiC "1" state
features
The MH0027C operates over an ambient temperature range of O°C to +85°C and is supploed in a
miniature 8-pln molded dual-in-Ilne package_
•
Fast rose times -
25 ns Into 600 pF load
5V to 25V
1 mW tYPical In
schematic and connection diagrams
v·
v"
,
.,
1k
.,
.. "
INPUT A
1k
'....:!.
J os
o.
,
~
7
J
OJ
'::.
07
•
~1l2
4
OUTPUT A
~
J
INPUT B
~QI
I
6
J
08
J
OUTPUT B
0'
v3
Dual-In-Line Package
tl .U.
INPUT A .....
vel...ll Li)
v- 2
1
7
ri>-l
INPUTB...J.U
..-
OUTPUT A
f!-v·
L~OUTPUT8
TOP VIEW
9-97
(J
.....
('II
o
o
absolute maximum ratings
J:
Continuous Supply Voltage
Peak Supply Voltage (10 ms)
Input Voltage
Output Voltage
Peak Output Current (each side)
Power DiSSipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
:E
electrical characteristics
PARAMETER
25V
30V
25V
Vee
1.2A
1.0W
O°Cto 85°C
-65°C to +150°C
300°C
(T A
= +25°C, v+ = 24V, Vel = 21V, unless otherwise specified)
LIMITS
CONDITIONS
MIN
= OV
Low Level Input Current (I,l)
V ,N
High Level Output Voltage (V OH )
Turn·On Time (t dON )
= 4 mA
IOl = 100 mA
Cl = 600 pF
Turn·Off Time (tdOFF)
Cl
Rise Time (t,)
Cl
Fall Time (t,)
Cl
IOH
Low Level Output Voltage (V o l)
UNITS
TYP
MAX
18
25
32
2075
210
21.25
V
07
1.0
V
= 600 pF
= 600 pF
= 600 pF
mA
5
15
ns
5
15
ns
20
45
ns
15
35
ns
Note 1- Rating applies for deVice soldered to a printed circuit board with 8 copper conductors
03 Inches wide For ambient temperatures above 25' C, derate linearly at 6 7 mW/"C
MOS Interface Circu its
For specifications on other National MaS clock
drivers and interface Circuits, see the following
data sheets:
Dual Voltage Translator - DM7800/DM8800
Dual High Speed Translator - DH0034/DH0034C
Quad 2·lnput NAND TTL/MaS InterfaceDM8810,DM8811
Quad 2·lnput AND TTL/MaS Interface - DM8810
Hex Inverter TTL/MaS Interface - DM8812
Dual Peripherlal Drivers - LM350,LM351/
LM75450A,LM75451A
Analog Comparator to MaS - LM 111 series
Dual Analog Comparator to MaS - LH2111 series
MaS Clock Drivers
Single Phase, TTL Input DC Coupled - MH0007
Two Phase DC Coupled - MH0009
Single Phase, High Speed DC Coupled - MH0012
Two Phase AC Coupled - MH0013
Two Phase Low Cost - MH0025
Two Phase High Speed AC Coupled - MH0026
typical applications
TT l to Negative Level Interface
(DC Coupled MOS Clock)
TTL to MMll03 High Speed Memory Interface
lM15451A
'Iiu~
TT~
:A-: 2
INPUTS 'Be--!-
nUAl
PERIPHERIAL
DRIVER
..3_ _~---'I'
r
f!-o ~, 'TOMM11DJ4~bVI6b'lm.mo,v.,,,y
I t""••
r-o"
,ndh"
,.Z5n.typ mto600pF
ml'O--;~, l:;""J',
R...
I.~d
INPUTS !Be--!
mjA~
INPUTS
DHOO]4CD
•
9·98
...l!......k
1
f"_ _~---'l4
(So-!!L-_....rh...,.
T'
NolO M,n,m".nrayb.ord •• p.ClllIn".,on'" •• nn«bOn,botw .. nLM15451A.ndMH0021eN
OpIlDn.I .. I ..... lpullup' .."'o.. IRx·lk)maVb.oddllllto'mp.... " .. t'm.by.b.uI.
,"'100012
;
Note Ax 11k) npll ... lt.~ ••:r........ t.m.
MH0021C
r-0 I
01
OUlp"IOW,ng--llVto4V, delay bm,-20n.
r--o¢,J R,...
ndf.rtt,m.-2!in,fo'Cl=600 PF
s::::t
Interface Circuits
00
00
o
00
MH8808 dual high speed MOS clock driver
general description
features
The MH8808 IS a high speed dual MOS clock
driver Intended to drive the two phases of a
memory array of 500 pF per phase at rates up to
4 MHz. The design includes output current limit·
Ing for controlled rISe and fall times, and thermal
shutdown which protects the chip against exces·
sive power dissipation or accidental output shorts
Two DTLITTL compatible status outputs monitor
clock outputs and provide a corresponding TTL
logic level for status Indication. Both direct and
Internally damped outputs are available for each
phase to suit the particular application. It IS ideally
suited for driVing MM5262 2k RAMs.
•
High Speed 18 ns typ delay and 20 ns typ rise
and fall tl mes with 500 pF load
•
Current limited outputs ±450 mA typ
•
Direct and damped outputs available
•
Thermal shutdown protection
•
TTL compatible status outputs
•
1W dissipation capability at 25°C T A
•
16 pin cavity dual·in·llne package
•
Output high level clamped to +5V
connection diagram
Dual-I n-Line Package
DAMPED
Vss
16
'~O
OUT
15
DAMPED
OUT
OUT
14
12
11
OUT
Nt
10
NOT CONNECT TO THIS PIN
TOP VIEW
9-99
00
o
00
00
absolute maximum ratings
J:
:?!
~
+N
Vss - Voo
26V
Total Power DISSipation (Note 1)
lW
O°C to +70°C
Operating Temperature Range
electrical characteristics
The following apply for Vss
=
+7V, Vss
=
+5V, V OD
PARAMETER
':=
-15V, TA = 25°C unless otherWise stated
CONDITIONS
I nput Current
VIN = -9V INote 2)
Output Low Voltage
lOUT = +1 mA, VIN -= -lOY
INote 2)
Output High Voltage
lOUT = -1 mA, VIN = -14V
Status "1" Voltage
lOUT
Status "0" Voltage
lOUT
Output Leakage Current
V BB = +8 5V, Vss = 5V
Voo = -17 5V, V OUT = +8 5V
= -250MA, VIN = -14V
MIN
10
-14
45
=
53
mA
V
V
05
100
open
4
Damping Resistor
UNITS
V
3
= 20 rnA, VIN = -10V
INote 2)
VIN
MAX
V
MA
12
IBB
VIN = -11 5V
Vss = +6 5V, V OD = -17 5V
V BB = +8 5V INote 2)
32
mA
Iss
VIN=-115V
Vss = +6 5V, Voo = -17 5V
V BB = +85V INote 2)
23
mA
V IN =-115V
Vss = +6 5V, V OD = -17 5V
V BB = +8 5V INote 2)
-55
mA
100
Output Rise Time
C L =500pF
26
ns
Output Fall Time
C L = 500 pF
26
ns
Delay to Negative-Going Output
C L =500pF
7
22
ns
Delay to Positive-Going Output
C L = 500 pF
10
25
ns
Note 1
Maximum Junction temperature
IS
110°C For operation above 25"C derate at 85"C/W ()JA for stili air
Note 2 Test only one Input high (more positive) at a time
9-100
c
~s
s:
<11
New Products
-'="
CO
<11
.......
C
s:.....
DM5485/DM7485 (SN5485/SN7485)
4-bit magnitude comparator
-'="
CO
<11
general description
features
The DM5485/DM7485 performs magnitude companson of straight binary and BCD (8421) codes.
Three fully decoded decisions on two 4-blt words
(A & B) are made and brought to three outputs.
•
Greater than, less than and equal to in one
package
•
Easily expandable through high speed cascading
inputs
This device IS fully expandable by use of cascading
Inputs. When expanded the total comparison time
is a function of word length and IS two gate delays
("" 12 ns) for each four bit section added to the
basIc device delay.
275mW
• TYPical power
truth table
COMPARING
INPUTS
CASCADING
INPUTS
OUTPUTS
A3, B3
A2, B2
A1, B1
AO, BO
A>B
AB
A 83
A3< 83
A3 = 83
A3 = 83
A3 = 83
A3 = B3
A3= B3
A3= B3
A3 = B3
A3 = B3
A3= 83
x
x
X
X
x
x
X
X
X
X
X
X
X
X
X
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
A2
A2
A2
A2
A2
A2
A2
A2
A2
>
<
=
=
=
=
=
=
=
82
B2
82
82
B2
B2
B2
B2
B2
NOTE' H '" high level, L "" low level, X
X
X
A1
A1
A1
A1
A1
A1
A1
>B1
80
AO< 80
AO= BO
AO = BO
AO= 80
X
X
H
L
L
X
X
X
X
X
X
X
X
X
X
L
H
L
X
L
L
H
L
L
L
L
H
= Irrelevant
connection diagram
I
1
I I I I
12 iJ 14 15 1& b G~~
10·1
DM5491A/DM7491A(SN54911SN7491) 8-bit shift register
general description
features
The DM5491A/DM7491A IS a serial-In, serial-out,
8-blt shift register utilizing TTL technology. It IS
composed of eight RS master/slave flip flops, Input
gating, and a clock driver. The register is capable of
storing and transferring data at clock rates up to
18 MHz while maintaining a typical noise-immunity
level of 1.0V. Power dissipation is typically 175
mW; a full fan out of 10 IS available from the outputs.
•
•
•
•
•
High speed
18 MHz typo
Gated data Input
Both true and complement outputs of last bit
Input loading of 1 on each Input
Typical power
175 mW
connection diagram
Data and input control are gated through inputs
A and B to the first bit of the shift register. Drive
for the common clock line is provided by an
internal clock buffer. Each of the Inputs (A, B,
and CP) appear as only one TTL input load.
The clock pulse inverter/driver causes these circuits
to shift Information to the output on the positive
edge of an Input clock pulse, thus enabling the
shift-register to be fully compatible with other
edge-triggered synchronous functions.
DM54123/DM74123(SN54123/SN74123)
TTL/monostable multivibrator
general description
features
The DM54123/DM74123 is a dual retriggerable,
resettable monostable multivibrator providing an
output pulse whose duration and accuracy is a
function of external timing components. Its inputs
and outputs are standard TTL and compatible with
all 5400 and 7400 products.
•
•
•
•
•
There are two inputs per function, one active LOW
and one active HIGH. This permits triggering on
either the leading (positive going) or trailing (negative going) edge. Triggering is Independent of Input
transition time or pulse width. An input cycle
time shorter than the output R*C cycle time will
retrigger the DM54123 and result in a continuous
output.
Retriggerlng may be inhibited by tying the Q output to the active LOW trigger input or the Q
output to the active HIGH Input. .
The true output may be forced LOW during any
phase of input or output timing by connecting a
logic LOW level to the reset input.
10-2
Retriggerable
0% to 100% duty cycle
TTL compatible inputs and outputs
Triggers on leading or trailing edge
Complementary outputs
Compensated for temperature and power supply
variations
21 ns (typ.)
• High speed trigger to Q
connection diagram
OM54141/0M74141 (SN54141/SN74141)
BCD to decimal decoder/driver
general description
features
The DM54141/DM74141 is a second-generation
BCD-to-declmal decoder designed specifically to
drive cold cathode indicator tubes. This decoder
demonstrates an Improved capability to minimize
switching transients in order to maintain a stable
display.
•
Full decoding is provided for all possible input
states. For binary inputs 10 through 15, all the outputs are off. Therefore the DM54141/DM74141,
combined with a minimum of external circuitry,
can use these Invalid codes in blanking leadlngand/or trailing-edge zeros In a display as shown in
the typical application data. The ten high-performance NPN output transistors have a maximum
reverse current of 50!,A at 55V.
•
•
•
•
Drives cold cathode numeric Indicator tubes
directly
Low leakage current at 55V (50pA max.)
Low power dissipation of 55 mW (typ.)
Fully decoded inputs ensure all outputs off for
Inval id codes
Input clamp diodes for minimizing transmission
line effects
connection diagram
Low-forward-impedance diodes are also provided
for each input to clamp negative-voltage transitions
In order to minimize transmission-line effects.
Power dissipation IS tYPically 55 mW, which is
about one-half the power requirement of earlier
designs.
...
OM 54160/0M74160 (SN54160/SN74160).
OM54161 /OM74161 (SN54161 /SN74161).
OM 5416 2/ 0 M7416 2 (SN 5416 2/SN74162).
OM54163 /OM74163 (SN54163/SN74163).
synchronous 4-bit counter
general description
These synchronous, presettable counters feature
an internal carry-look-ahead for applications in
totally synchronous high speed counting schemes.
The DM54160/DM74160and DM54162/DM74162
are BCD decade counters and the DM54161/
DM74161 and DM54163/DM74163 are 4-bit binary
counters. All counting flip flops are triggered
simultaneously from a common clock buffer,
counting on the rISing (positive going) edge of
the clock Input waveform.
All counters are synchronously presettablii to
either state. With a Low logic level on the Load
input, the next rising edge of the clock will transfer
Into the counting register data present on the
Inputs A, B, C, and D.
The Clear functions for the DM54160/DM74160
and DM54161/DM74161 are asynchronous and a
Low logic level on the Clear Inputs will set all
outputs Low regardless of the state of the clock or
any other input (i.e., clear overrides all other
functions).
The Internal carry-look-ahead provides for cascading up to 10 counters in totally synchronous
applications without additional gating.
featurus
•
•
•
•
•
•
•
Internal look-ahead for fast counting
Terminal count output for ripple cascading
Synchronous counting
Synchronous loading
Typical count frequencies over 32 MHz
DM54160/DM74160 equal to FSC 9310
DM54161/DM74161 equal to FSC 9316
connection diagram
The Clear function for the DM54162/DM74162
and DM54163/DM74163 are totally synchronous. A
Low logic level on the Clear input will set the
outputs Low after the next clock pulse. This
synchronous clear allows simplified count sequences
as the maximum count can be decoded with one
extra NAND gate. This gate then synchronously
sets the counter to 0000 (all Low).
10-3
DM54174/DM74174(SN54174/SN74174) hex 0 flip flop
DM54175/DM74175(SN54175/SN74175) quad 0 flip flop
general description
features
Both devices contain positive edge-triggered Dtype flip flops_ Q outputs only appear on the
DM54174/DM74174 whereas both Q and Q outputs are available on the DM541751DM74175.
Overriding Clear inputs are used to set the Q outputs to the logic "0" state.
connection diagrams
•
Buffered clock and direct clear Inputs
•
Individual data Input to each flip flop
truth table
INPUTS
OUTPUTS
0'
CLEAR
CLOCK
0
°
L
X
X
L
H
t
t
H
H
L
H
L
L
H
H
L
X
00
00
H
*Avatlable on the DM54175/DM74175
x = Don't care
DM54174/DM74174
DM54175/DM74175
t = Transition from low to high
DM54196/DM74196(SN54196/SN74196 )
presettable decade counter
DM54197 IDM74197(SN 54197/SN74197)
presettable binary counter
general description
These high-speed counters consist of four M/S flip
flops which are internally connected to provide
either a divide-by-two and a divlde-by-five counter
(DM54196/DM74196); or a divide-by-two and a
divide-by-eight counter (DM54197 /DM74197). The
outputs may be preset to any state by placing a
low on the count/load input and entering the
desired data at the data inputs, independent of the
state of the clocks.
• Input clamping diodes simplify system design
• Output Q A will drive clock-2 input plus ten
series 54/74 loads
connection diagram
features
•
•
•
•
Performs BCB, bi-quinary, or binary counting
Fully programmable
Fully independent clear Input
Guaranteed to count at Input frequencies from
o t'o 50 MHz
DM54197/DM74197
(See Note 1)
truth tables
COUNT
(5-2) (See Note 2)
(BCD) (See Note 1)
COUNT
°B
aA
°A
00
Dc
L
L
H
L
H
L
L
L
H
H
L
L
0
L
L
L
L
L
L
H
1
L
L
L
H
2
L
L
H
L
2
L
L
H
L
3
L
L
L
H
H
3
L
L
H
H
H
L
4
L
H
L
L
L
H
L
L
H
5
H
L
L
L
L
L
H
H
L
L
L
H
H
H
6
7
H
H
H
L
H
L
H
L
L
L
8
H
L
H
H
H
L
L
H
9
H
H
L
L
Note 1. Output QA connected to CLOCK-2 Input
Note 2- Output QO connected to CLOCK-1 Input
L
L
L
L
8
9
L
1
3
L
7
L
4
L
5
6
L
2
0
1
4
10-4
COUNT
°B °A
Dc
0
°B
OUTPUT
OUTPUT
aD Dc
OUTPUT
00
BI-QUINARY
DM54196/DM74196 DECADE
L
H
L
L
5
L
H
L
H
6
L
H
H
L
H
7
L
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
c
3:
.....
...
DM7512/DM8512 dual gated master/slave JK/D flip flop
general description
features
The DM7512(DM8512 IS a dual flip flop which
can operate in either a J, K mode or in aD-type
mode. Both flip flops operate from a common
clock and a common asynchronous clear but have
separate mode inputs so that one can operate as a
J, K flip flop while the other is operating as a Dtype flip flop. (See truth table.)
•
•
•
•
......
CO
...
U'I
N
c
3:
.....
truth table
M-k~j------'
~
c
3:
Positlve-edge-triggered
High speed, 40 MHz typical operation
DM75L 12(DM85L 12 pm compatible
Target power dissipation
270 mW max.
logic and connection diagrams
L.. _ _ _ _ _ _ _ _
U'I
N
U'I
U'I
U'I
J
K
M
CLR
QN+1
0
0
1
0
1
0
1
0
ON
1
0
1
1
0
0
CO
1
1
1
0
ON
X
X
0
0
D
X
X
X
1
0*
U'I
U'I
U'I
......
c
3:
_ _ _ _ _ .J
* Asynchronous transltlOn
X = Don't care
DM7555/DM8555 TRI-STATE@programmable decade counter
connection diagram
general description
The DM7555(DM8555 is a TRI-STATE four-bit
decade counter which has both conventional and
TRI-STATE outputs. When the TRI-STATE outputs are in the high-impedance mode, they can be
used to load mformation into the subsequent stage.
This is particularly useful in applications involving
program counters. Fully synchronous operation
results when these devices are cascaded.
features
•
•
•
375mW
27 ns
50 MHz
Typical power dissipation
Target propagation delay
Target clock frequency
logic diagram
00 12
-LJ
~:-:
.
.
::n,.. .
r=f=D1r" "
--D-r
11oe
4- ~
r-
et""
1IOC
I
-~~.
~:'
.
.
~'
~: .
~
,
--D-r
~""'
,
,
,
---.;;-
~
,
~ '--';-
'--';-
--=I-
)0-'
~
."
Vcc' 16
.
.
".
;
,
" ."
COllNl
10-5
DM7556/DM8556 TRI-STATE@programmable binary counter
general description
connection diagram
The DM7556/DM8556 is a TRI-STATE four-bit
binary counter which has both conventional and
TRI-STATE outputs. When the TRI-STATE outputs are In the high-impedance mode they can be
used to load information into the subsequent stage.
This IS particularly useful in applications involving
program counters. Fully synchronous operation
results when these devices are cascaded.
CD
It)
It)
--4+----....,t-----r-t---i
MEMORY
ENABLE LME2O(4)
PIh(l6)"V cc Pln(8)"OND
OUTPUTS
:::~
OPTION 2
=:~~
OPTIONJ
L
'I
connection diagram
truth table
OPTION
ME,
ME2
1
0
0
Normal
1
X
Logical 1
X
1
Logical 1
1
1
Normal
2
3
x
10-14
=
Don't care
OUTPUTS
0
X
Logical 1
X
0
Logical 1
1
0
Normal
X
1
Logical 1
0
X
Logical 1
DM76L99/DM86L99 TRI-STATE®64-bit random access memory
general description
The DM76L99/DM86L99 is a fully decoded 64-bit
RAM orgamzed as 16 4-bit words. The memory
IS addressed by applying a binary number to the
four Address inputs. After addressing, information
may be either written into or read from the
memory. To write, both the Memory Enable and
the Write Enable inputs must be in the logical "0"
state. Information applied to the four Write inputs
will then be written into the addressed location.
To read information from the memory the Memory Enable input must be in the logical "0" state
and the Write Enable input in the logical "1" state.
Information will be read as the complement of
what was written into the memory. When the
Memory Enable Input is In the logical "1" state,
the outputs will go to the high-impedance state.
This allows up to 75 memories to be connected
to a common bus-line without the use of pull-up
resistors. All memories except one are gated into
the high-impedance while the one selected memory exhibits the normally totem-pole low impedance output characteristics of TTL.
features
•
•
•
•
Series 54L74L compatible
Same pin-out as SN5489/SN7489, 3101, 5501
Organized as 16 4-bit words
Expandable to 1200 4-bit words without additional resistors
50 ns
• Typical access from chip enable
80 ns
• Typical access time
55mW
• Typical power dissipation
logic diagram
~~:
A,
ADDRESS
INPUTS
~A'
II,
~~A'
II,
~~:
DI
D'
D'
DATA
INPUTS
DC
lOt
ME
connection diagram
truth table
MEMORY
ENABLE
WRITE
ENABLE
OPERATION
a
a
a
Wrlte
Logical "1" State
1
Read
Complement of Data
1
X
Hold
OUTPUTS
Stored
In
Memory
LogIcal "1" State
10-15
...
...
CD
:e
LM160 high speed differential voltage comparator
o
general description
...I
...:e
CD
The LM 160 high speed comparator is designed to
be used In D to A and disc file pre amp applIcations where spiied is critical. It is designed with a
high impedance differential input stage and provides complementary saturated logic output levels,
with minimum skew between outputs. The device
operates off of ±4.5V to ±6.0V supplies and has
outputs wh Ich are compatible with standard DT L/
TTL levels. This product is pin and function compatible with the pA760. TO·5, dual· in-line and
...I
flat package versions of this product will be
available.
features
15 ns
•
Response time
•
Bias current max.
10pA
•
Offset voltage
2 mV
•
Voltage gain
3000
connection diagrams
Metal Can Package
Dual-In-Line Package
v'
vTOP VIEW
LM161 high speed differential voltage comparator
general description
The LM161 high speed comparator IS designed for
D to A and disc file pre amp applications where
speed is cntical. It features a high impedance
differential Input stage and provides complementary saturated logic output levels with minimum
skew between outputs. Each output is Individually
strobed and is compatible with standard DTL/TTL
levels. The preamplifier section IS capable of operating from ±4.5V to ±15V supplies, and is independent of supply symmetry. ThiS comparator IS
pin and function compatible with the NE529.
TO-5, dual'In-line and flat package versions of the
product will be available.
features
•
Op amp supply compatible
•
Common mode range
•
Individual output strobing
•
Maximum bias current
•
Response time
15 ns
•
Offset voltage
2 mV
•
Voltage gain
3000
connection diagrams
Metal Can Package
v·
OUT B
TOP VIEW
10-16
Dual-In-Line Package
±7V
10pA
r~
LM55325/LM75325 memory driver
U1
U1
general description
N
U1
W
.......
The LM55325 and LM75325 are monolithic memory drivers which feature high current outputs as
well as internal decoding of logic inputs. These cirCUits are designed for use with magnetic memories.
outside the package thereby allOWing the circuit to
operate at higher source currents for a given junction temperature. If this method of source current
setting is not desired, then nodes Rand R'NT can
be shorted externally. This activates an internal
resistor connected from VCC2 to node R. This
method provides adequate base drive for source
current up to 375 mA with V CC2 = 15V or
600 mA with VCC2 = 24V.
The circuit contains two 600 mA sink-switch pairs
and two 600 mA source-switch pairs. Inputs A and
B determine source selection while the source
strobe (S 11 allows the selected source turn on. In
the same manner, Inputs e and D determine sink
selection while the sink strobe (S21 allows the
selected sink turn on.
The LM55325 operates over the full military
temperature range of -55°C to 125°C, while the
LM75325 operates from oOe to 70°C.
Sink-output collectors feature an internal pull-up
resistor In parallel with a clamping diode connected to VCC2 ' ThiS protects the outputs from
voltage surges associated with sWltchl ng Inductive
loads.
features
• 600 mA output capabil ity
• 24 volt output capability
• Dual Sink and dual source outputs
• Fast switching times
• Source base drive externally adjustable
• Input clamping diodes
• DTL/TTL compatible
The source stage features node R which allows
extreme fleXibility in source current selection by
controlling the amount of base drive to each
source transistor. This method of setting the base
drive brings the power associated with the resistor
connection diagram
truth table
ADDRESS'INPUTS
SOURCE
A
B
STROBE INPUTS
SINK
C
D
H
X
X
H
L
X
X
L
X
X
X
X
X
H
H
H
L
SOURCE SINK
S1
S2
OUTPUTS
SOURCE
W
X
ON OFF
SINK
v
Z
L
H
OFF OFF
X
L
H
OFF ON
H
H
L
OFF OFF
ON
OFF
L
H
L
OFF OFF
OFF
ON
X
X
H
H
OFF OFF
OFF OFF
H
H
X
X
OFF OFF
OFF OFF
OFF OFF
H "" high level, L == low level, X::: Irrelevant
Note Not more than one output
IS
to be on at anyone time
10-17
r-
~
.....
U1
W
N
U1
LM75324 memory driver with decode inputs
general description
features
• 400 mA output capability
The LM75324 is a monolithic memory driver
which features two 400 mA (source/sink) switch
pairs along with decoding capability from four
address lines. Inputs Band e function as mode
selection lines (source or sink) while lines A and D
are used for switch'pair selection (output pair
Y/Z or W/X).
•
•
•
•
High voltage outputs
Dual sink/source outputs
Internal decoding and timing circuitry
Fast switching times
• oOe to 700e operation
• DTl/TTL compatible
connection diagrams
truth table
INPUTS
ADDRESS TIMING
AB C
i
OUTPUTS
SINK SOURCES SINK
Y
Z
D
E F G
W
0 0 1 1
1 1 1
ON
OFF OFF
0 1 0 1
1 1 1
OFF
ON OFF
OFF
1 1 0 0
1 1 1
OFF OFF ON
OFF
1 0 1 0 1 1 1
X X X X 0 X X
X
OFF
OFF OFF
ON
OFF OFF OFF
OFF
OFF
X X X X X 0 X
OFF
OFF OFF
OFF
X X X X X X 0
OFF
OFF OFF
OFF
Note 1: X - Logical 1 or logical 0
Note 2: ['-Jot more than one output IS to be allowed to be
ON at one time When all timIng Inputs are at a
logical 1, two of the address Inputs must be at a
logical 0
10·18
LM75461, LM75462, LM75463, LM75464
dual peripheral drivers (high voltage)
general description
These circuits are high voltage versions of the
LM75451A, LM75452, LM75453, and LM75454
series. Pin configurations for the corresponding
parts in the two series are identical. Each circuit
contains two independent high voltage transistors
each capable of sinking 300 mA at the same time.
features
•
•
High breakdown
Outputs withstand high voltage with Vee
for power strobing applications
•
Both outputs can sink 300 mA simultaneously
•
Two separate drivers per package
III
oOe
to 70 0e operation
•
Identical pin configurations as the lower voltage
LM75450 series equivalents
•
8-pin mtni-dual-in-line package
•
Inputs have clamp diodes and are DTUTTL
compatible
= OV
connection diagrams
Vc<;
82
A2
X2
vee
82
A2
X2
Al
81
Xl
GNO
Al
81
Xl
GNO
TOP VIEW
TOP VIEW
LM75462
LM75461
vee
82
A2
81
Xl
X2
Vc<;
2A
28
2Y
lA
TOP VIEW
TOP VIEW
LM75463
LM75464
10-19
"oCO
MH7803/MH8803,
MH7807/MH8807 oscillator/clock drivers
00
::t
:E
.......
"o00
"::t
general description
The MH7803(MH8803 and MH7807(MH8807 are
complete self-contained two-phase oscillators and
clock driver subsystems for MOS micro-computer,
calculator and shift register systems.
:E
M
o
00
00
features
::t
• No external timing components
• Two non-overlapping outputs
• Both frequency and pulse width are voltage
control/ed
:E
.......
M
o
•
Frequency adjustable from 100 kHz to 500 kHz
(MH7803(MH8803) and from 400 kHz to
2 MHz (MH7807(MH8807)
•
Pulse width adjustable from 300 ns to 2!1s
•
Low power for battery operation
•
TTL outputs for verification and synchronization
•
Both direct and damped MOS outputs
00
"::t
logic diagram
:E
--0 v'
--CV-
FREQUENCY CONTROL
PULSE WIDTH CONTROL
--0
INHIBIT
--CTEST
0----------'
" " " , - - 0 Vee
IOn
TTL OUTPUTS
DAMPED MOS OUTPUTS
10n
....¢1
..._-OGNO
¢2
DIRECT MOS OUTPUTS
connection diagrams
14 v~
INHIBIT INPUT
INHIBIT
PW CONTROL
v'
"
"
TEST
v-
10-20
FREQ CONTROL
TOP VIEW
fQPVll'.W
MH7803/MH8803
MH7807/MH8B07
MH8804. MH8805 quad. dual MOS memory drivers
features
general description
The quad MH8804 and the dual MH8805 are
bipolar to MOS drivers specifically designed to
drive input address lines for MOS memory arrays
using MM1103 type RAMs. The MH8804 is pin
compatible with the 13207 and the MH8805 with
the SN 75361.
~
::I:
±500 mA
•
Current mode output drive
•
Rise and fall times
20 ns
•
•
Delay times
High output voltage
15 ns
•
Low output vo Itage
•
Input levels
00
00
o
Vss - 1.0V
0.3V
TTL!DTL
c.n
connection diagrams
16
v"
"
0,
v"
0,
14
0,
0,
13
E,
12
E,
E,
0,
E,
11
0,
0,
10
0,
GNO
0,
0,
v"
TOP VIEW
TOP VIEW
MH8804
MH8805
10-21
»
(')
AC Test Circuits
-I
CD
...
en
(')
...
5V
5V
T
~T
4DOll
OUTPUT
n
c
'5V
50pF
'
;:+'
en
COUT
+24V
Test Circuit 1
Test Circuit 2
5,
52
CL
tpdl
Closed
Closed
50 pF
tpdO
Closed
Closed
50 pF
tOH
Closed
Closed
5 pF'
t, H
Closed
Closed
5pF'
tHO
Closed
Open
50 pF
tH 1
Open
Closed
50 pF
.. Approximate value of Jig capacitance only
Test Circuit 3
Vcc=5V
50V
800.11
RL = 11011
>--....- - - 0
INPUT
CL
DM7510f
DM8570
I-<>--....-~-....-I~-~I--I~...,
OUTPUT
15pF
Test Circuit 4
Test Circuit 5
50V
5V
30Q.l!
5V
OUTPUT
130
INPUTo--==L_?-"t"i'...................i-• ..,
SDDIl
OJ
DIODES· F0100
Test Circuit 6
Test Circuit 7
11-1
II)
:!::
..
o
::I
.. 5V
(,)
50Ko±1%
...
II)
G)
t-
iO--...--tO)
VOUT
iO--...--tO)
Your
O
«
Test Circuit 8
Vcc=+5V
v"
'K
50
PULSE GENERATOR OUTPUT
1 SWitcHING TIME ltptl+ & tpdJ TESTS
RISE TIME < 15 ns
FALL TIME < 15 ns
AMPLITUDE"" 4\1
fREQ, '" 2 MHz ±5% AT 50% DUTY CYCLE
"1
2. SHIFT RIGHT FREQUENCY TEST
RISE TIME < 15 N5
FALL TIME < 15 NS
AMPLITUDE"" 4\1
FREQ,"
CL INCLUDES
PROBE ANO JIG
CAPACITANCE
16 MHz WITH PULSE WIDTH
ADJUSTMENT SO THAT VI~ HAS
DUTY CYCLE OF APPROX. 50%
VOUT "OUT
"OUT
VOUT
"OUT
Test Circuit 9
VIN
Veel = VCC2
VOUT
TO CHANNEL "A"
+20 Vde
OR
VOUT
NOR
TO
CHANNEL
"8"
INPUT
PULSE
GENERAtOR
INPUTPULSE
t+"I-"'2D±O.2ns
(20 to BD%}
VEE =-J.2Vdc
ALL INPUT AND OUTPUT CABLES TO THE SCOPE ARE EQUAL LENGTHS OF 5IJ.OHM COAXIAL CABLE
WIRE LENGTH SHOULD BE < 1/4 INCH FROM TP 1N TO INPUT PIN AND TPOUT TO OUTPUT PIN.
Test Circuit 10
"·2
»
(")
-t
~
SEE
OM75521
TABLE 1
OM7554
CD
~
III
~
(")
r+
AC
LOAD
L......-
....
(")
C
r+
III
Figure 1 (Test Circuit)
INPUT CONDITIONS
TEST
tpd(TEl
CLEAR
PRESET
CP
TRANSFER
ENABLE
Vee
GND
GND
See Note 1
Vee
Vee
GND
GND
See Note 1
Vee
GND
Vee
GND
GND
See Note 1
See Note 2
ODI
OD2
GND
GND
GND
GND
GND
CE
t'H
See Note 3
See Note 3
GND
GND
Vee
GND
tOH
See Note 3
See Note 3
GND
Vee
GND
GND
tH1
See Note 3
See Note 3
GND
GND
Vee
GND
tHO
See Note 3
See Note 3
GND
Vee
GND
GND
GND
GND
Vee
GND
GND
See Note 8
Table 1
400n
INPUTS
-
NOTE 1 PULSE GEN PAR
~
MHz, t,:S 15
OS,
tl
~
5 ns, tp (CLOCK)
2:;200ns
-
~
DM155Z/
DM7554
NOTE 2 See At SWITCHING TIME WAVEFORMS
"
"
1s'~EDES
NOTE 5)
NOTE J TIE THESE INPUTS TOGETHER, SEE SWITCHING TIME
WAVEFORMS
NOTE 4 INCLUDES JIG CAPACITANCE
NOTE 5 ALL DIODES ARE F01Da OR EOUIVALENT
NOTE 6 OPEN SWITCH 8;; FOR tpdO(TCl. tpd1 (Tel. tpdo(CETl, AND
tpd1(CET)
NOTE 7 JIG CAPACITANCE
NOTE 8 f CLOCK USE 50% DUTY CYCLE
Figure 2 (Load Circuit)
SWITCH S,
SWITCH S2
tpdO
Closed
Closed
50 pF
TEST
CL
tpdl
Closed
Closed
50 pF
tpd(TE)
Closed
Closed
50 pF
t'H
Closed
Closed
tOH
Closed
Closed
tH1
Open
Closed
tHO
Closed
Open
50 pF
fclock
Closed
Closed
50 pF
5 pF ISee Note 7)
5 pF ISee Note 7)
50 pF
ID
Table 2
Test Circuit 11
11-3
II)
.t::
::l
...
(,)
u
r -
v"
....
II)
s,
s,
s,
s,
B,
U
«
A,
B,
A,
B,
A,
- - - - ....,
OATA
I
I
Q)
l-
-vc7""
I
I
Rl =4DOn
I
c,"
",f
I~
L __
CONTROL
I
,
I
_ _ ..J
~D~CU.!!.!
VI
1K
F,
DM54t81/DM74181
r- F,
B"
i\,
-V~ -
I
I
-
-
-
I
I
I
R," 4000
A"' 1-"----...
M
Co
T
'::'
L
__
-,
C
'"""
LOAD DIAGRAM
:
!;2!D~C~
__
---1
t s, t h ,
NOTE 1. USE LOAD CIRCUIT 2 FOR A '" B OUTPUT ONLY LOAD CIRCUIT 1 SHOULD BE
USED TO TEST THE REST OF THE OUTPUTS
NOTE 2 FOR INPUT PULSE, F" 1 MHz, ZOUT "" SOu 50% DUTY CYCtE, VIN PP = 3V
~ $10 ns
NOTE 3 CL lNCLUDES PROBE AND JIG CAPACITANCE
NOTE 4 ALL DIODES ARE INJD64
t,. =
Test Circuit 12
tpdR
S,
S2
Cl
Closed
Closed
50 pF
50 pF
t wpw , t rpw
Closed
Closed
tOH
Closed
Closed
"H
Closed
Closed
tHO
Closed
Open
50 pF
IH1
Open
Closed
50 pF
5 pF'
5 pF'
.. ApprOXimate value of Jig capacitance only
Test Circuit 13
Vee =5V
Test Circuit 14
OUTPUT
VI
OM7219!
DM8219
1 KO
ALL DIODES ARE FDIOO
Test Circuit 15
11-4
~
<
CD
!II
Switching Time Waveforms
....
o..,
3
1/1
l r'lO",
INPUT~
F-Sns (NOTE I)
CP WIDTH
(NOTE I)
VOUT
~-,5V\
PRESET 01 CLEAR
VOUT
(2 lOGIC lEVelS)
r
F
,PULSEWIDTH:? 25n1
,I
(3 lOGIC LEVELSI
Ir
NOTE 1 J AND K INFORMATION Will REGISTER PROPERLY EVEN THOUGH THE INFORMATION IS REMOVED 5 NS
BEFORE THE CLOCK PULSE VOLTAGE FALLS HOWEVER WHEN THIS OCCURS IT MUST BE ASSURED THAT THE
LOGICAL "1" CLOCK PULSE LEVEL AND THE DESIRED J AND K INFORMATION OCCUR SIMUL TANEOUSL V FOR AT
LEAST20NS
Waveform 5
Waveform 6
11-5
1lI
II)
...E
o
~
Q)
"""lO""V
>
ca
~
o
~
50%
DUTY CYCLE
OV
CLOCK
[
~
"-'
15V
_ _ _.:.,'
O%
ln~
I
IwAVEFORM USED
ItpdO
T~ MEASURE
U
(U) AND tpdl (U)
10%
: LJ'!
~
l..-,."
'.'" --:
__ ,
j'G
---L!:'''-T1L-
9D%
"
I,
14- ---..l
,I
I WAVEFORM USED TO MEASURE
~d 0 (U)
1
:\15V---:J
15V
CLOCK
o ___ .n
----'l--D ' - -
tpdl""""'"
AND tpd 1 (il)
~tpdO
I'
(.1
UORU--------~---------J
QORfi--------~------------~
15V
CLOCK
NOTE
NO MAXIMUM RISE AND fALL TIMES ARE IMPOSED UPON
THE CLOCK VOLTAGE HOWEVER VERY SLOW TRANSITIONS WHICH
ALLOW AN INPUT TO REMAIN IN THRESHOLD REGION CAN CAUSE
NOISE PROBLEMS
(bl
Waveform 7
Waveform 8
INPUT OV
OUTPUT
OUTPUT
'",.
'''''
FREQUENCY = 1 MHz
DUTY CYCLE" 50%
t, = ~ = 10n5
Waveform 9
11·6
~
<
CD
I»
tpd1 & 'pdO
1
-., "
'OH
....
3V
1
...
0
1
I
I
3
1
I
15V
1/1
1
1
DATA
.::;,15V
CONTROL
1
ov (DM7D93!OMBD93)
INPUT
1
'V
OUTPUT
1
LOGICAL "0" LEVEL
3V
--..j
CONrADt
tOH : . . -
I
i
I
(OM7094!DM8094)
15V
'v
{al
(bl
'H1
'HO
3V
3V
OUTPUT
~
CONTROL
5V-VDl
,-:::":::M7:.::"~3:.::/D:::M8:::09:;;",-_
CONTROL
\.....:::"::;.M7:::":::3/:::'::::"8::::"::::":...-,v
'v
LOGICAL "1 • LEVEl
I
1
LOGICAL ''0'' LEVEL
'v
',.r:~--------- 3v
I
I
I
OUTPUT
1
r+:~'-CD-NT~R-'L-----3V
CONTROL
(DM7094fDM8094)
I
(OM7U94/DMB994)
I
15V
I
I
1
'v-------'
'V----.....I
I
I
I
I
I
I
I
1
I
~tHt~
{dl
(el
LOGICAL "l"LEVEL
OU~]05V
:",--,,5V
,.,1_ _ _ _ _ _ _ _ _
3V
CONTROL
INPUT CHARACTERISTICS
FREQUENCY t MHz
PULSE WIDTH 100 liS
t,.=t,<10ns
AMPLiTUDE = JV
I
OV (0 709J/DM8093)
1
ro-
3V-"'CO"'N"'TR"'0l"'-""\
(DM7094/DM8D94)
ill
'---------'v
(el
Waveform 10
11-7
1/1
E
...
....o
--I
Q)
>
cu
~
I,
_______
j--
~I "
1~----~3V~-----1
~
90%
115V
_ _ _.-:.::'0::;'. I _
INPUT
1
------j
r
1____~3V~___
90%~
15V
I
I 10%
1
r-""
------j
OUTPUT-----J!..
r----""
, \ ' -_ ____
INPUT CHARACTERISTICS
AMPLITUDE = JV
FREQUENCV" 1 MHz
t,=t!=10ns
Waveform 11
tpdl & tpdO
"p:~
(,'V
OV---.!t
~1t;,dO~
STROBE-X-i'~'_'V_ _ _ _ _ __
\'V
: \..-,----
OUTPUTS
~tpdl~
I
1
I
1 5V
~tpdl""""'"
:
I
1
tHO
----4-~
'I'
~
OUTPUT
--
1 SV
r-I -----""
15V
5 OV
STROBE~15V
~ ~. :.i05;':V
OUTPUTS
'""
-JtpdOf----.-
OUTPUT~
15V
f= 1 MHz
t,"'tfS;10ns{10%to!JO%)
DUTY CYCLE = 50%
Waveform 12
MEMORY~
15V
15V
ENABLE
ADORESS
---+-------------,.
INPUTS _
_
_
r--
----------+ _____
_ _ - . J K.:,-'_'_V_ _ _ _ _ _ _ _ _ _ _ _
l,5V
15V
OUTPUTS
15V
INPUT PULSES
',"'IOns
'Ij=lDns
f'" 1 MH~
Waveform 13
11-8
_ _ _ __
ACTUAL ....
..-::L
VOLTAGE---!-J',
~ 15V
~
<
CD
III
30V
15V
ODV
3DV
16V
ODV
30V
16V
DOV
.3....
0
en
t, = It = 10 os (10%10 90%1 ON CLOCK AND INPUT DATA WAVEFORMS
NOTE 1 INPUT DATA IS APPLIED TD SERIAL INPUT WHEN MODE CONTROL
EQUALS A LOGICAL ZERO INPUT DATA IS APPLIED TO INPUT A, B, C, OR 0,
WHEN MODE CONTROL EQUALS A LOGICAL ONE
Waveform 14
~=-----~~t------'V
OV
t,=t, "'10 rn
PW"',OOns
FREQUENCV = 1 MHz.
Vcc= +5 OV
VO"'(A)~r-I..,
I
YoUT(BI
15Y
15V
Waveform 15
R.ad Cycl.
Writ. Cycle
ME~
~ ~~
~l~ r-
*OUTPUT
ADDRESS
----------.J
ADDRESS
A
ADDRESS
ADDRESS
•
C
t~--
*DUTPUT SHOWN fOR STORED DATA IN
ADDRESS A = 1, IN ADDRESS B = 0
tl
•
t---
(bl
(01
Waveform 16
Writ. Cycle
~:~~~~...'_5_V_____________
OUTPUTS
I~
----4---,.
Ir-
ME
--------.50V
ENABLE~I!iY
OUTPUTS
I~ ~'0;.f5V;" "
J
_ _ ___
",15V
15V
WE--+--"
05V
AC~g:~~~; -----t-""""---.L
t""ld
OUTPUT_- ------ --
MEMORY
---
.ov _ _+.J
-----~+'~---+--"'T:
-
I ,,;01-----.16V
15V
I"
r-
~--.
III
I"
(01
(bl
(cl
Waveform 17
11-9
I/)
.
E
....o
G1 OR G2
CIl
TO OUTPUT
>
CO
VOUT
3:
(a)
f
V'N _ _ _""""
15V
A, B, C, OR 0
TO OUTPUT
~
15V
--I '\...-,'·I-----'-I",.r-15V
VOUT
f
\,._'_5V_ _ __
(b)
Waveform 18
+ __..J
1.5V
OUTPUT-_ _ _ _ _ _ _
'~oj
OUTPUT------------~
t,=tf"'10ns
f= 1 MHz
Waveform 19
FREQUENCY'" 1 MHz
t,= tf:s:.
10ns
::;; 10 ns
I~--------~,~+_--------------JV
~~-----------ov
,,----~----\--------VOH
15V
OUTPUT WAVEFORM 1
Cnt", Cn+ y• Cr>+z, - - - - - - "
GorP
(a)
OUTPUT WAVEFORM 2
OH
V ------"\
15V\
',dO
F=t:
''''
I\----~---
15V
Yo,
NOTE 1. C,· 50 pF INCLUDING PROBE AND JIG CAPACITANCE FOR OM541B2, OM74182.
NOTE 2 ALL DIODES ARE INJ064
(b)
Waveform 20
11·10
~
Dl
<
".,~"'"
r------- 3V
CO
~
STR~"",~
(STROBE INPUT - LOGICAL 0)
. _ .} '
DATA INPUTS"
..."
~
15V
,
tpdO
EITHER OUTPUT
tpdl ~ EITHER QUTPUT
OUTPUT
"""'''~
15V
~
--4:
~15V
. / 15V
PROVIO~ LOGICAL "1" ON OUTPUT UNDER TEST}
EITHER OUTPUT
DATA INPUTS" - - - OUTPUT - - - - - - - - - - - - -
£
- Lt.l
~ J-
(OATA INPUTS- TO
STROBE INPUT
STROBE INPUT
(DATA INPUTS- TO PROVIDE LOGICAL "l"ON OUTPUT UNDER TEST)
I5V
"THE DATA INPUT WAVEFORMS SHOWN MAY NOT NEefSSARll Y REPRESENT THE ACTUAL DIRECTION OF THE TRANSI·
TlON FOR A PARTICULAR DATA INPUT PIN THE TRANSITIONS
SHOWN INDICATE ALSO WHAT AN OUTPUT WOULD 00 IF IT
EITHER OUTPUT
tpdl
I5V
WEREN'T fOR THE STROBE INPUT IN ALL CASES THE WORST
CASE INPUT·TO OUTPUT PATH IS SPECIFIED REGARDLESS OF
THE TRANSITIONS SHOWN
(b)
(a)
Waveform 22
2 SETTliNG TIMES FROM CHANGE OF A, 8, or C TO CORRECT DATA OUTPUT
1 PROPAGATION DELAYS FROM DATA INPUTS TO OUTPUT
SElECT INPUT
(NOTE 1)
OATA INPUTS CONNECTED IN ANY lOGIC CONFIGURATION
NOTE 1 WHEN THE SElECT INPUTS ARE TAKEN TO OPPOSITE lOGICAL lEVElS SIMULTANEOUSLY, THE
ONe (ONES) MAKING THE lOGICAL "1" TO LOGICAL "0" TRANSITION PROVIDE THE WORST-CASE PATH
NOTE 2 TRANSITION TIMES SPECIFIED ARE INDEPENDENT OF THE DIRECTION OF THE OUTPUT WAVEFORM
SET INPUTS A, B, C SUCH THAT TESTED INPUT IS ROUTED TO THE OUTPUT
(a)
(b)
Waveform 23
CLEAR
1.5V
INPUT
DISABLE
INPUT
,
--.Jr;\.~.,
. \.,
-jt"'I~1
DATA
OUTPUT
CLOCK
OUTPUT
Waveform 24
11-12
~t--
___ 3\..1.51._'IV_ _ _ _ _ __
Waveform 25
~
1\1
<
CD
-oft
...o
,v
--i==~-----i~~-------=========:== ,w
CP
J~
,v
-+_____r-__ _
15V
' - - - -_ _ OV
- --L--+--==J"---L
CLEAR:.._-+_____t-______
!II
INPUT~~v
OV
PRESET _ _
3
,V
~15V
3V
15V
OUTPUT
ov
(b)
C,=====c==-------4~(=================___
-L-+--===
TE=r--+---OuTPuTS----l~r_----~~r_----Jr----,L=_
OR
TC _ _""_I
3V
15V
tHO
ov
j --
,v
v""
15V
~
...
15V
OU1PU1------- \
15V
------
Vo<
OUTPUT
,v
INPUT----.
(a)
15V
(e)
__--___________ 'V
t
ov_'NPUT,,"~
LOGICAL
"'"
ACTUAL
VOLTAGE
15V
------------;;OU~T;PU~T~~=l5F:V=~
_, ,V
(d)
(e)
-------------'V
tOH
OV
"3 -------r
I~ :~.
OUTPUTP.
LOGI~~~~~ _ _ _ _ _ _ _ _
m
VOLTAGE
(f)
Waveform 26
11-13
1/1
E
...
Q
'+-
(\)
Clear Pulse Width and Delay
>
cu
Data Setup and Hold
MINIMUM WRITE
~
PULSE WIDTH
WRITE - - - - - .
15V
15V
ClEAR _ _ _....I1
OUTPUT - -_ _
15V
15V
DATA. _ _ _ _ _ _ _J
+-_.....,
(OR)
""\1
'ATA _ _ _ _ _ _ _
15V
15V
3V-----.,.
r------
tOH
3V
OUTPUT
~
5V-Vo 1
_---""15V
I
OUTPUT
LOGICAL "0" LEVEL
I
-~
10H
~
LOGICAL "0" lEVEL
(d)
(e)
3V----.,.
LOGICAL "1" lEVEL
OU~]05V
i"'---
,15V
,..,.1_ _ _ _ _ _ lV
,--....:':;;":;;>'::':.',;;IN;:.'U:.;T_ _ OV
LOGICAL ''1'' LEVEl
I
I
I
I
I
I
I
OV
DISABLE INPUT
I
I
I
I
tlH
I
r---
I
OV _ _-"O;;.UT;;.'U;.;T_-?
tHl
(e)
INPUT CHARACTERISTICS
FRED 1 MHz
PULSE WIDTH 100 flS
1,=tl
<
lOlls
AMPLITUDE = JV
Waveform 27
11·14
(f)
:.--
y"'-
~
II)
<
CD
....
o
3
10%
CLOCK
~
III
CARRY. BORROW
15V
OUTPUT---+-,
OUTPUT
----1--"\
1__ lpdO
Waveform 28
30V
NOTE 1. CLOCK MAY BE AT EITHER A LOGICAL "I • DR A LOGICAL "O"WHILE CLEARmG
NOTE 2. NEGATIVE HOLD TIME VALUES INDICATE SA • Sa INfORMATION MAY BE RELEA'SED
PRIOR TO THE TIME THE CLOCK PULSE REACHES ITS I 5V LEVEL
NOTE 3 CLEAR AND CLOCK WAVEFORMS 1,." tl" 10 ns 110%-90%,90%-10% TRANSITION},
f" 1 MHt
Waveform 29
D.~.
(\:I
ADDRESS
INPUTS
3:
------- ---
r-
-- -
I5V
----'
r---'.,,-
~
I5V
I5V
OUTPUTS
1\ 15V
I5V
r--'""~
-'",'-
INPUT PULSE CONDITIONS
t,
It < 10ns
~
f" 1 MHz
Waveform 31
MEMORY~'5V
ENABLE
',-,_ _ _ _ _ _ _ _ _ _ _ _ __
ADDRESS
INPUTS____1
~5V_ '0<'
OUTPUT
15V
-
-
-
-
-:j""
_
rr
INPUT PULSES
t,"10111
t!=IOlls
f = 1 MH~
1_
5V _ _ _ _
~
""'r-~
tal
MEMORY
ENABLE~15V
OUTPUTS
'"'
1=-'50V
OUTPUTS
-
""
~~V
....!_ _ _ _ _ ""5V
t5V
,ov---i-oJ
'"'
I5V
f--
.......
05V
AC~~t;~~~---f- -~
I ''1------'''' 1 5V
'" r{el
(bl
Waveform 32
Read Mode
Write Mode
CHIP~\
CHIP
SElECT
SElECT
DATA
OUT
ADDRESS
OA~~
WRITE
ENABLE
/
......._ _ _ _ _ _ _ _- '
~'-
______
...JXI..______
____
I5V
DATA
DUT _ _ _ _ _ _......t
tal
PULSE AMPLITUDE'" 3 ov
RISE TIME AND FALL TIME::;
IlS
Waveform 33
11-16
~)C
~
<
III
CD
~
...o
3
en
INPUT
OUll'UT-_ _
--1_....
~
1_ IOV
_ _ _ _I-_,_..,J_~
1=' MHz
t,=t,=IOns
PW='OOm
Waveform 34
Waveform 35
"""STOlA
PlNZ,15=GNO PIN3=Vcc
VON
OATA __
SEAIALOR
PARALLEL
CP
YOUTZ
(a)
OUTPUT
tpd,ETO l ...
All OTHER INPUTS HIGH
I5V
(a)
Vw---------------
v~,--------------------,
I5V
15V
(b)
tpd,IOA TO lA
~r------~"
S~:~~-=\-----------------'6V
r::
-J '--r"-~- voo,-------'-'VJ~'-------------V"
:::j I..,
(e)
Jr----\. . ______Jr
OUTPUT _ _ _
Waveform 37
(b)
-ri
VIN 15
IPIN120~Orl)~
VOUT FREQUENCY -"Z X YIN FREQUENCV
(e)
40M
r-
~
. . -1 t
v,.
~'5Y
---1~".--1~VOU'
~YOU'
Waveform 36
. .--1 ~
m
NOTE CAPACITANCE INCLUDES JIG AND PROBE
Waveform 38
11·17
1/1
E
...
....o
PIN 13
Q)
>
ca
DATA
INPUT
SELECT
DATA INPUT
3:
PIN 2
V 1NW1
VOUTI1I
FREQUENCV ~ 1 MHz
DUTY CYCLE ~ 50%
I
Z OUTPUT
If'" t, ~ 10 ns
----1[ I L
tp(IO
AMPLITUDE
------11""°1-
-
-I'''",~
ZOUTPUT
PIN 4
PIN2
VoO""
~
;-
-15V
PIN I
'"" !-;r---"",
15V
Z OUTPUT
VOUTIDI
SELECT DATA INPUT TO OUTPUT VOL lAGE
WAVEFORMS E IS LOGICAL 0,1 0 IS LOGICAL l ' & V,
PINS 3, 5, 11
~
Voo ""
15V
=
=
VOUTIOI
DATA INPUT TO OUTPUT VOLTAGE WAVEFORMS
PINS 5,6, 7, 9, 10, 11 = Vee
OV
GND
PINS4, 6, 7, 9,10,12
E&SoARELOGICAl"O"&V,45V
=
VGc
PINS 3, 13
=
GND
(al
(bl
Waveform 39
SELECT
DATA INPUT
ENA8LE
INPUT
Z OUTPUT
Z OUTPUT
VOUTWI
Z OUTPUT
Z OUTPUT
VOUTIIJI
ENABLE TO OUTPUT VOLTAGE WAVEFORMS
So IS LOGICAL "0" 10 IS LOGICAL "'" & V, '" 4 5V
SELECT DATA INPUT TO·OUTPUT VOLTAGE
WAVEFORMS E IS LOGICAL "11",11J IS LOGICAL T' & V1 ~ OV
(al
(bl
DATA
INPUT
FREQUENCY ~ 1 MHz
DUTY CYCLE ~ 50%
ZOUTPUT
t."tj=10ns
AMPLITUDE = 3V
Z OUTPUT
DATA INPUT·TO OUTPUT VOL rAGE WAVEFORMS
E & So ARE LOGICAL "0" & V, = 4 5V
(el
Waveform 40
11-18
=
3V
~
I»
<
CD
~
o...
3
1/1
v"
VOUT
OR
Waveform 41
Waveform 42
m
11·19
"tI
:r
Physical Dimensions
.c
~;---~t---'=L
MAX
j
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INCHES TO MILLIMETERS CONVERSION TABLE
INCHES
MM
INCHES
001
.0254
.010
254
.100
2.54
002
0508
020
.508
.200
5.08
.003
.0762
.030
.762
300
7.62
004
1016
.040
1.016
400
10.16
MM
MM
005
.1270
.050
1.270
500
1270
.006
.1524
060
1.524
600
15.24
007
1778
.070
1.778
700
17.78
.008
2032
.080
2.032
.800
20.32
.009
2286
090
2.286
900
22.86
All package dimensions are In Inches.
VI
INCHES
l>
<
II)
Available Digital
Applications Literatu re
II)
C"
CD
o
...
CO
II)
l>
'0
'0
The following is a listing of Digital applications literature.
This literature, plus Information on National's other product
lines, IS available through our sales offices, representatives,
distributors, or our headquarters In Santa Clara.
(')
II)
...
o
::l
(I)
r-
...
...
.,CD
application notes
II)
AN-12
AN-17
...
C
Applications of the DM7200/DM8200 Digital Comparator
CD
Programmable D,v,der Applications
AN-22
Integrated Circuits for Digital Data Transmissions
AN-35
High-Speed TTL Adders
AN-36
TTL MSI Applications
AN-37
TTL MSI Multiplexers and Demultiplexers
AN-43
TRI-STATE® Logic
AN-45
CharacterIStiCS and Applications of TRI-STATE® IC's
AN-47
TRI-STATE® Logic
AN-49
Pin Diode Drivers
In
In
Modular Systems
High-Speed Memories of Microprogrammed Computers
AN-60
A Method of Implementing Stacks with EXisting Minicomputer Memory
AN-61
The Application of ROMs
AN-68
USing TRI-STATE® Logic for "Rubber-Band" Memories
AN-73
TRI-STATE® Logic Applied
Added Performance
AN-84
Driving 7-Segment Gas Discharge Display Tubes With National Semiconductor CirCUits
In
a Computer System Can Reduce System Cost and Provide
VII
Notes
Notes
Notes
Notes
Notes
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"'?
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