1974_ITT_Semiconductor_Product_Catalog 1974 ITT Semiconductor Product Catalog
User Manual: 1974_ITT_Semiconductor_Product_Catalog
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CONTENTS
Section
.,
Hi REL and JAN Semiconductors
Index
TTL Integrated Circuits
, DTL Integrated Circuits
High Noise Immunity Logic (Hi-Nil) IC
Inte~face Integrated Circuits
Linelir Industrial Integrated Circuits
Consumer Integrated Circuits
Silicon Transistors
Germanium Diodes
Silicon Diodes
Rectifiers
Zener Diodes
Tuner Diodes
Thyristor Diodes
Capacitors
Package Dimensions
Information fumis.hed by lIT is believed to be acclIra.te and reliable. Ho:-vever, no responsiblity is assumed
by lIT for its use; nor for any infringements of patents or other right' of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent right of lIT.
Circled(E)with device number indicates copyright material reproduced
by permission of Fairchild Camera and Instrument Corporation.
30M474
Printed in U.S.A.
_ITT "
______
H_IG_H_R_E_L_IA_B_IL_IT_Y_P_R_O_C_ES_S_I_N_G
SEMICONDUCTORS
5004 of Military Standard 883 - Test Methods
and Procedures for Integrated Circuits. The
various screening class levels are outlined in
the following section:
HIGH RELIABILITY
PROCESSING
ITT Semiconductors maintains a broad capability for high reliability microcircuit screening.
A
Since its release, ITT has been a leader in
qualifications to MIL-M-38510, the military
specification creating "JAN IC's".
84 -
Mil STO
Class 8
avionics
product
testing.
82 -
Same as 84 without 100% post burnin temperature testing.
ITT's approach to these requirements differs
from several "acronym" programs. We ofte'r a
full and complete "NO EXCEPTION"approach
to each of the normally used military
specifications.
Certain applications require various class
levels of environmental screening and electrical
test. The ITT approach to High Reliability
provides a solid easily understood processing
sequence. Each class level is geared exactly to
the screening procedures outlined in Method
-
Mil STO 883 Method 5004 Class A Processing - Generally used in ultra
hiah reliability applications.
883 Notice ·4, Method 5004
Processing - Used in many
systems requiring burned-in
and 100% OC temperature
C -
Mil STO 883 Method 5004 Class C Processing. Used in many ground-based
systems. Includes complete environmental screening.
Note: These screening procedures are available
in all ceramic and metal packages.
METHODS ARE MIL STD 883
SCREEN
[Spec Paragraph1
CLASS "A"
[Methods)
CLASS"B"
[Methods)
CLASS "B4"
[Methods)
.CLASS"C"
[Methods)
3.1.1 Precap Visual
(100% inspection per specified
method)
2010 A
1008
2010 B
1008
2010 B
1008
2010 B
1008
3.1.2 Stabilization Bake - 24 hrs.
@ 150 C
1008
1008
1008
1008
3.1.3 Thermal Shock - 0 C to 100 C .,.
15 cycles, 5 min, at extreme, 10
sec. transfer time. Liquid to liquid
1011
None
None
None
1010 (may be
replaced with
thermal shock)
1010 (may be
replaced with
thermal shock)
1010(may be
replaced with
thermal shock)
2002, "F" 1 Shock
or 5 pulses atB
(.5 msec. @1500 g)
None
None
None
3.1.6 Centrifuge
2001, E 30,000 9
in Yi, then Yi
plane
2001, E
30,000 9 in Y1
2001,E
30,000 9 in Y1
2001, E 30,000 9
in Y1 plane
3.1.7 Hermeticity
Fine Leak
Gross Leak
Method 1014
Radioflo
Bubble Test
Radioflo
Bubble Test
Radioflo
Bubble Test
Radioflo
Bubble Test
Per Electrical
Spec.
Per Electrical
Spec.
Per Electrical
Spec.
None
3.1.4 Temp-Cycle'- minus 65 C to
1010 (may be
150 C 10 cycles, 10 min. at
replaced with
extreme. 5 min. max. transfer time thermal shock)
3.1.5 Mechanical Shock
3.1.8 Critical Elect. Para.
(Go-No-Go or Oatalog)
1-1
HIGH RELIABILITY PROCESSING
METHODS ARE MIL STD 883
SCREEN
[Spec Paragraph)
CLASS "A"
[Methods)
CLASS"B"
[Methods)
CfLASS"B4"
[Methods)
CLASS"C"
[Methods)
1015125 C
for 240 hours
1015125 C
for 168 hours
1015125 C
for 168 hours
None
3.1.10 Critical Elect. Para.
(Go-No-Go or Datalog)
Per Elect. Spec.
None
None
None
3.1.11 HTRB
72 hrs@ 150 C
None
None
None
Per Spec.
Per Spec.
Per Spec.
Per Spec.
Per Spec'.
None
Per Spec.
Per Spec.
Per Spec.
Per Spec.
Per Spec.
Per Spec.
Per Spec.
None
None
Per Spec.
Method 2012
None
None
None
3.1.14 Qualification and Quality
Conformance Procedures
5005
5005
5005
5005
3.1.15 External Visual
2009
2009
2009
2009
3.1.9
Burn-In
3.1.12 Final Elect. Test
(a) D.C. @ 25 C
(b) D.C. @ Hi/Low Temp.
(c) A.C. Para. @ 25 C
(d) Functional Tests
3.1.13 Radiographic Insp.
Optional Additions.
Class A
- Scanning Electron
Microscope Wafer
Inspection
All Classes
- Read and Record Data (DC at
Temperature) With Delta
Calculations as Required
All Classes
- Switching Measurements at
Temperature Extremes with
Data
All Classes
Through QPL 38510-11 dated 16 July, 1973,
ITT qualificatic;m status is as follows:
1) Full.Qualified Part I
5400
5405
5401
5410
5402
5420
5430
5403
5404
5440
------'TOTAL
Packages
A -1/4 x 114 Flatpack
C-14pinDip
- Lot Conformance Testing
(Life Tests) and Generic
Reliability Data.
Lead Finishes
, --A Package - A - Solder Dipped
B - Tin Plated '
'
C - Gold
C Package - B - Tin Plated
C - Gold
Classes A & B - Elevated Temperature,
Burn-in.
2) Interim Qualification Part II
MIL 38510- JAN MICROCIRCUITS
ITT also offers a broad line of fully qualified
MIL-38510 microcircuits. At this writing, 20
devices are fully qualified and qualification
plans are in process for an additional 21 types.
The rigorous life qualification test are
conducted in full compliance to Method 5005 of
MIL 883 and are available on all ceramic and
. metal can integrated circuits.
5472
545Q
5451
5473
5453
5474
5454
5486
5470
54H30
20'-----
54H10* .
5482
5407
54H72
5417
54H73
54HOO*
5483
54H30'
54H04*
5406
5442
5416
54121
54H20'
--------TOTAL 15--------These qualifications are rigorously controlled by the Defense Electronics Supply Center, Dayton, Ohio .
• Flat Pack Only I
1-2
HIGH RELIABILITY PROCESSING
.=
tJIiO!ilJ#l~b
ORDERING INFORMATION
A cross reference guide for ordering of JAN
microcircuits is shown below:
Jan No. Part No. • Jan No. Part No.
00101
00102
00103
00104
00105
00106
00107
00108
00109
00201
00202
00203
00204
00205
00206
00207
00301
00302
,00303
00401
00402
00403
00404
00501
00502
00503
00504
00601
00602
00701
00801
00802
00803
00804
00901
00902
00903
00904
01001
01002
01003
01004
01005
00106
01007
01008
01009
01101
01201
01202
01203
01301
5430
5420
5410
5400
5404
5412
5401
5405
5403
5472
5473
54107
5476
5474
5470
5479
5440
5437
5438
5402
5423
5425
5427
5450
5451
5453
5454
5482
5483
5486
5406
5416
5407
5417
5495
5496
54164
54165
5442
5443
5444
5445
54145
5446
5447
5448
5449
54181
54121
54122
43123
5492
01302'
01303
01304
01305
01306
01401
01402
01403
01404
01405
02001
02002
02003
02004
02005
02006
02101
02102
02103
02104
02105
02201
02202
02203
02301
02302
02303
02304
02305
02306
02307
02401
02601
02701
02801
02802
02901
02902
02903
02904
02905
05301
05302
10101
10102
10103
10104
10201
10301
10302
10303
10202
5493
54160
54163
54162
54161
54150
9312
54153
9309
9322
54L30
54L20
54L10
54LOO
54L04
54L03
54L71
54L72
54L73
54L78
54L74
54H72
54H73
54H74
54H30
54H20
54H10
54HOO
54H04
54H01
54H22
54H40
54L86
54L02
54L95
54L164
54L42
54L43
54L44
54L46
54L47
'4007A
4019A
741
747
LM101A
LM108A
723
710
711
LM106
MCM5304
Part No. Jan No.
Part No. Jan No.
54L47 02905
710 10301
711 10302
5448 01008
5449. 01009
723 10201
741 10101
5450 00501
5451 00502
747 10102
4007A 05301
5453 00503
5454 ' 00504
4019A 05302
5470
00206
5400 00104
54L71 02101
54HOO 02304
5472· 00201
54LOO 02004
54H72 02201
5401 00107
54L72 02102
54H01 02306
5473 00202
5402 00401
54H73 02202
54L02 02701
54L73 02103
5403 00109
5474 00205
54L03 02006
54H74 02203
5404 00105
54L74 02105
54H04 02305
5476 00204
. 54L04 02005
54L78 02104
5405 ,00108
5479 00207
5406 00801
5482 00601
5407 00803
5483 00602
5410 00103
5486 00701
54H10 02303
54L86
54L10 02003
02601
5492 01301
5412 00106
5416 00802
5493 01302
5417 00804
5495 00901
54L95 02801
5420 00102
54H20 02302
5496 00902
9309· 01404
54L20 02002
9312 01402
54H22 02307,
5423' 00402
9322 01405
54107 00203
5425 00403
54121 01201
5427 00404
54122 01202
5430 00101
54H30 02301
54123 01203
54145 01005
54L30 02001
5437 00302
54150 01401
5438 00303
54153 01403
5440 00301
54160 01303
54H40 02401
54161 01306
5442 01001
54162 01305
54L42 02901
54163 01304
5443 01002
54164 00903
54L43 02902
54Ll64 02802
5444 01003
54165 00904
54L44 02903
54181 01101
5445 01004 LM101A 10103
5446 01006
LM106 10303
54L46 02904 LM108A 10104
5447 01007 MCM5304 20102
HIGH RELIABILITY PROCESSING
SUFFIX DEFINITioNS
ALL MIL-M38510 DEVICES MUST HAVE A THREE
LETTER SUFFIX AFTER THEIR NUMBER
EXAMPLE: 38510/0010lBCB IS 5430 GATE,
... '-;..... ,. \
,,,',""
.",-','
/""
",'"
'"
/
, '"
CLASS
B
I
\
\
'"
\
/
II
14 PIN
I DIP
/
I
•
I
r 1st LmER
\ DEVICE CLASS
\
\\
\
I ,
\A-883A
8-8838
C-883C
\
/'"
",,,,,",,
/
\
",'"
TIN PLATED'KOVAR
LEADS
,
\
\
".
2nd LETTER _ PACKAGE OUTLINES' \
"
3rd LEmR
WD FINISH
A- W' x W' Flatpack 14 Pin
, B- W' x Va" Flatpack
'C -14 Pin DIP
D- %" x 31a" Flatpack 14 Pin
E-16 Pin DIP
F- %"
X
3/8 " Flatpack 16 Pin
G- 8 Pin T0-99
H- %" x %" Flatpack 10 Lead
1-10 Pin TO·99
J - 24 Pin Flatback
1-24 Pin DIP
The JAN number is a complete processing
and electrical description of the part odered.
All full Jan parts are completely assembled,
fabricated and tested in the United States.
Exception" to the standard military screening
'documents, the need for exact selection of par~
ticular processing Is relieved. In addition, test
plans for exact conformance to customer drawings are generated if required and as a standard
practice, submitted to the customer for final
approval.
SOURCE CONTROL DRAWINGS
DELIVERY
lIT maintains a completely staffed specification review group for analysis of customer
controlled specifications.
The West Palm Beach factory of lIT Semiconductors is dedicated to manfacture of Highreliability circuits. A complement in excess of
100,000 burn-in sockets is maintained. In addition, if a c(:>ntractual or specification limitation
does not exist our offshore facilities are completely equipped for all Class C assembly and
screening techniques. All class B final work
is done in the U.S.
In many cases, the customer may find one of
'the standard lIT H~-Rel processing sequences
exactly equivalent to his needs and his only
requirement is to specify the. final electrical
specification.
Since
lIT . performs with "NO
I
.
1-4
PRODUCT INDEX
HIRELand
JAN SEMICONDUCTORS
. Type No.
Page
Type No.
Page
ITT-7445 ............. -;67/70
ITT74160 ........ : .. 196/201
ITT7446A ............ . 71/80
ITT74161 ......... .. 196/201
ITT7447A
............
.
71/80
ITT74162 .; ...... : .. 1~6/201
Type No.
Page
ITT7448 .............. 71/80
ITT74163 ......... .. 196/201
High-Reliability
ITT7450 ....... , ..... . 81/83
ITT74164 ........ ... 202/204
Processing - ............ . 1/4
ITT7451 ............. . 81/83
ITT74165 ........... 205/207
ITT7453 ............. . 84/86
ITT74174 .......... . 208/210·
ITT7454 ............ .. 84/86
ITT74175 .. ~ ....... . 208/210
INDEX
ITT7460 : ........... .. 87/89
ITT74180 ........ ... 211/213
----SECTION 2 - - - ITT7470 ... : .......... . 90/92
ITT74181 ........... 214/220
ITT7472 ............. . 93/95
ITT74182 ........... 222/224
TTL INTEGRATED CIRCUITS
ITT7473 ............. . 96/98
ITT74190 ......... :.225/231
ITT74191 ........... 225/231
---SECTION 3 - - - ITT7474 ..... ; ... ; .. . 99/101
ITT7575 ............. . 102/5
ITT74192 .......... . 232/237
Typ~ No.
Page
ITT7476 ........... . 106/108· )TT74193 ........... 232/237
TTL Numerical Index ..... 1,2
ITT7480 ....... ..... 109/112
ITT74194 ........... 238/241
TTL Functional Index ..... 3,4
ITT7482 .......... .. 113/115
ITT74195 ........ ... 242/245
General Information
ITT7483 ........... . 116/119
54/74 Series TTL
IT17486 ............ 120,121
ITT54/74HOO ....... ;246,247
Family ...... 5114 and 14A/D
1TT.7490 ........... . 122/125
ITT74H01 ......... , .248,249
ITT54/7400 ............ 15,16
ITT7491 A ...... : ... . 126/128
ITT74H04 ..........• 250,251
ITT7401 ............... 17,18
ITT7492 ........... . 129/131
ITT74H05 ........... 252,253
ITT7402 ...•... , ....... 19,20
ITT7493 ........ : ... 132/134
ITT74H10 ........... 254,255
ITT7403 ............... 21 ,22
ITT7494 ......... ... 135/137
ITT74H11 ........... 256,257
ITT7404 ..... , ......... 23,24
ITT7495A ........... 139,140ITT74H20 .......... ;258,259
ITT7405 ............... 25,26
I.IT7496 ........... . 1411143 -ITT74H21 .: ......... 260,261
ITT74104 .. : ............. 144
ITT7406 ............ .. 27/29
ITT74H30 ........... 262,263
ITT7407 .............. 30,31
ITT74105 ............... 144
ITT74H40 ......•.... 264,265
ITT7408 ............. . 32/34
ITT74107 ........... .. 96/98
ITT74H50 .......... . 266/268
ITT7409 ............. . 32/34
ITT741 09 ................ 144
ITT74H51 ...... ; .... 266/268
ITT7410 ... ~ ........... 35,36
ITT74118 ............ 145,1~6
ITT74H53.;; ...... .·.269/271
ITT7411 ............... 37,38
ITT74121 ........•. . 147/152
ITT74H54 ......... : .269/27.1
ITT7412 ............... 39,40 - ITT74122 ......... .. 153/157
ITT74H60 ........... 272,273
ITT7413 ............... 41,42
ITT74123 _.......... . 153/157
ITT74H72 .. ~ ....... . 274/276
ITT74124 .......... . 158/164_ ITT74H73 -........ _. . 277/279
ITT7416 ............ .. 27/29
ITT7417 ............... 30,31
ITT74130 ......... .. 165/166
ITT74H74 ........... 280/282
ITT74131............. 165,166
ITT7420 ............... 43,44
ITT74H76 .......... . 283/285
ITT7421 ............... 45,46
ITT74135 .......... . 167/169
ITT7525 ............... 47,48
ITT74137 .......... . 167/169
ITT7426 ....... ;.; ..... 49,50 -ITT74138 ............ 170,171
ITT7428 •............ . 51/53
ITT74139 ............. 170,171
DTL INTEGRATED CIRCUITS
ITT7430 ............... 54,~5
iTT74141 ........•. . 172/174
---SECTION 4 - - ITT7432 .... ; ..... : .... 56,57
ITT74145 ........... .. 67/70
ITT7433 ............. . 51/53
ITT74150 ........... 175/180
ITT930,961 .............. 1/3
ITT7437 ............. . 58/60
ITT74151 : .... ; ...... 175,180
ITT932,944 .............. 4/7 .
ITT7438 ............. . 58/60
ITT74153 ........... 181/184
................ .4/8
ITT933
ITT7440-............. ; .61,62
ITT74154 ........... 185/187
ITT935/938 ............ 9/13
IT17442 ............. . 63/66
ITT74155 ....... -.... 188/192
ITT941 ;951 . : .......... 14/16
ITT7443 .......... : ... 63/66
ITT74156 .....••.•.. 188/192
ITT945,948 ....•....... 17/19
ITT7444 ............. . 63/66 - ITT74157 .......... . 193/195
---SECTION 1 - - -
PRODUCT INDEX
DTL INTEGRATED CIRCUITS
(continued)
Type No.
Page
ITT946,949 ........... . 20/22
ITT962,963 ........... . 23/25
ITT1800 ............... 26,27
ITT1806,1807 ......... . 28/30
ITT1808,1809 ......... . 31/33
ITT1810,1811 ......... . 34/36
ITT9093/94,9097,9099 . . 37/41
DTL Gate Propagation
Testing .................. 42
SENSE AMPLIFIERS
- - - SECTION 6 - - Type No.
Page
ITT7520 ........ .. 1/8,25/47
ITT7521 .............. .. 6/8
ITT7522,7523 ...•.....• . 9/11
ITT7524,7525 ......... . 12/14
ITT7528,7529 ......... . 15/17
ITT5534,5535' ... :"..... . 18/21
ITT75234,75235 .... : .. . 22/24
ITT3671 ............. . 48/62
ITT9614 ............. . 63/68
ITT9615 ............. . 69/74
INDUSTRIAL LINEAR
---SECTION
HIGH NOISE IMMUNITY
LOGIC [HINIL] IC
---SECTION 5 - - ITT301,301 H ............. 1,2
ITT302,302H ............. 3,4
ITT303,303H ............. 5,6
ITT311 ,311 H ............ .7/9
ITT312,312H ......... . 10/12
ITT321 ,321 H ..•........ 13,14
ITT322,322H ........... 15,16""
ITT323,323H ........... 17,18
ITT324,324H ........... 19,20
ITT325,325H .......•... 21,22
ITT326,326H ........... 23,24
ITT331 ,331 H ............. 25
ITT332,332H ........... 26,27
IlT333,333H ........... 28,29
ITT334,334H ........... 30,31
ITT335,335H ........... 32,33
ITT342,342H .. , ........ 34,35
ITT343,343H ........•. 36/38
ITT361 ,361 H ......... . 39/41
ITT362,362H ......... . 42/44
ITT370,370H ........... 45,46
ITT371 ,371 H .......... 47/49
ITT372,372H ......... . 50/53
ITT380,381
380H,381 H ........... . 54/56
7---
ITT709,709A .......... .. 1/8
ITT710 ............... . 9/16
ITT711 .............. . 17/22
ITT712 .............. . 23/31
ITT720 .............. . 32/37
ITT723 ............... 38/46
ITT726 ............... 47/50
ITT741 ............. .. 51/57
CONSUMER LINEAR
(continued)
Type No.
Page
ITT3065 ............. . 39/42
TDA1330 ............. 43/45
TDA1352 ............. 46/49
ITT3701 ............. . 50/53
SAJ110 ............... 54/60
SAH190 ............. . 61/68
TBA470 ................. 69
TBA800 .............. 70/73
TCA250 .............. 74/76
TCA270 ............... 77 ,78
TCA350 : .............. 79,80
TCA430-N ; .............. 81
ZTK6.8 to
ZTK33 (TAA550) ...... . 82/86
ZTK33DPD ......•..... 87,88
UAA110 ............ .. 89/92
SAJ220 .............. . 93/94
TAA780 ............... 95,96
TBA840 .............. 97/99
TCA840 ............ .. 97/99
TAA775G .......... . 100/103
SAK115 ............. 104,105
SAY115 ............. 106,107
ITT7103 ..... ~.: ....... 18,19
SILICON TRANSISTORS
CONSUMER LINEAR
---SECTION 9 - - -
---SECTION 8 - - -
Small Signals Chips
And Wafers ............. 1,2
ITT491 ................ . 1/4
ITT492 ............... .. 1/4
ITT500 ................... 5
ITT501 .................. 6,7
ITT502 .................. 8,9
ITT503 ...... , ......... 10,11
ITT505 ................ 12,13
ITT508 ................ 14,15
ITT509 ................ 16,17
ITT7103 .........•.........
ITT7105 ............... 20,21
TBA940 .............. 22/25
TBA950 .............. 26/29
TBA120S ............ . 30/34
ITT3064 ............. . 35/38
MPSA05 .................. 3
MPSA10 •................. 4
MPSA20 .....•....•....... 5
MPSK20 ....•.....•....... 5
MPSK21 .......•.......... 5
MPSK22 ...........•...... 5
MPSA55 ........•......... 6
MPSA70 ..............•... 7
MPS706,MPS706A ......... 8
MPS834 ...................9
MPS2369 ................ 10
MPS2711 ................ 11
MPS2712 ................ 11
MPS2713 ................ 12
MPS2714 ................ 12
PRODUCT INDEX
SILICON TRANSISTORS
(continued)
Type No.
Page
M PS2923 12925 .......... 13
M PS2926/2931 ........... 14
MPS3392/3395 ........... 15
MPS3638,3638A ....... 16,17
MPS3693 ................ 18
MPS3702 ................ 19
MPS3703 ................ 19
MPS3704 ................ 20
MPS3705 ................ 20
MPS3706 ................ 20
M PS3707/3711 ........... 21
MPS5172 ................ 22
MPS6530/6532 ........... 23
MPS6533/6535 ........... 24
MPS6565 ................ 25
MPS6566 ................ 25
MPS6591 ................ 26
2N696 ..................• 27
2N706 ................ 28,29
2N706A ............... 28,29
2N706B ............... 28,29
2N708 ................... 30
2N744 ................... 31
2N834 ................... 32
2N2195 .................. 33
2N2195A ................ 33
2N2195B ................ 33
2N929 ................ 34,35
2N930 ................ 34,35
2N2217 ............... 36,37
2N2218 ............... 36,37
2N2219 ............... 36,37
2N2219A .............. 38,39
2N2221 ............... 40,41
2N222 ................ 40,41
2N2221 A .............. 42,43
2N222A ............... 44,45
2N2368 .............. .46/50
2N2369 .............. . 46/50
2N2369A ............ . 51/56
2N2480 ............... 57,58
2N2480A ............. 57/58
2N2483 ..... ; ........ . 59/64
2N2484 .............. . 59/64
2N2904A .............. 65,66
2N2905A .............. 65,66
2N2906A .............. 65,66
2N2907 A .............. 65,66
Type No.
Page
2N3011 ............... 67,68
2N3053 .................. 69
2N3502 ............... 70/72
2N3503 .............. . 70/72
2N3504 .............. . 70/72
2N3505 .............. . 70/72
2N3724 .............. . 73/78
2N3725 .............. . 73/78
2N4013 ............... 73/78
2N4014 ............ ... 73/78
2N3903 .............. . 79/81
2N3904 .............. . 79/81
2N3905 .............. . 82/84
2N3906 ............... 82/84
2N3962 .............. . 85/87
2N3963 .............. . 85/87
2N3964 .............. . 85/87
2N3965 .............. . 85/87
2N4123 .................. 88
2N4124 .................. 88
2N4125 .................. 89
2N4126 .................. 89
2N4248 ............. : .90/92
2N4249 .............. . 90/92
2N4250 .............. . 90/92
2N4400 ............... 93,94
2N4401 ............... 93,94
2N4402 ............... 95,96
2N4403 ............... 95,96
2N4418 ............... 97,98
2N4419 ............... 97,98
2N4420 .............. 99,100
2N4421 .............. 99,100
2N4422 .............. 99,100
2N5086 ................. 101
2N5087 ................. 101
2N5221 ................. 102
2N5209 ................. 103
2N5210 ................. 103
2N5219 ................. 104
2N5220 ................. 105
2N5087 ................. 106
2N5223 ................. 107
2N5224 ................. 108
2N5225 ................. 109
2N5226 ................. 110
2N5227 ................. 111
2N5228 ................. 112
2N5368/5371 ............ 113
2N5372/5375 ............ 114
Type No.
Page
2N5376 ................. 115
2N5377 ................. 115
2N5378 ............. 116,117
2N5379 ............. 116,117
2N5447 ................. 118
2N5448 ................. 118
2N5449 ................. 119
2N5450 ................. 119
2N5451 ................. 119
GOLD BOND
GERMANIUM DIODES
---SECTION 1 0 - - -
Gold Bond Germanium
Diodes ................ . 1/8
SILICON DIODES
- - - SECTION 11.,----
Switching Diodes .......... 1
Si !icon Planar Diodes ... . 2/6
1 N148 .................... 7
JAN1 N148 ................ 8
1 N149 .................... 9
ITT600 .................. 10
1TT601 .................. 11
ITT2001 ............... 12,13
ITT2002 ............... 12,13
ITT2003 ............... 12,13
ITT3001 ............... 14,15
ITT3002 ............... 14,15
ITT3003 ............... 14,15
1 N5194 .................. 16
1N5195 .................. 16
1 N5196 .................. 16
1 N5605 .................. 17
1N5606 .................. 17
1 N5607 .................. 17
1 N5608 .................. 17
1N5609 .................. 17
PRODUCT INDEX
THYRISTOR DIODES
RECTIFIERS
---SECTION 1 2 - - -
-
.......-SECTION 1 5 - - -
Type No.
Page
Selenium Contact Protector
Rectifiers .............. . 1/6·
Selenium Transient Voltage
Suppressors .......... . 7/12
1 N645/649 ............... 13
1 N4000 Series ........ . 14/17
EM500 Series .. ; ..... . 14/17
1 N4001/4007 ............. 18
1 N4383-5 ............ . 19/21
1 N4585-6 ......•..... . 19/21
RG1122-3 ............ . 19/21
EM500G Series .... : ...... 22
1 N3611 Series .... : ....... 22
1 N4245 Series ............ 22
1 N5400/5408 ...... , ... 23,24
Entertainment Type
Selenium Rectifiers ... . 25/30
Type No.
Page
1 N3831 13846 ............ 1,2
Type E 4E20-4E200 ....... 3,4
Type E 4E20M-4E200M ... 5,6
Four-Layer Diode,
Application Notes ..... . 7114
CAPACITORS
---SECTION 16 _ __
Type TAG .............. 115
Type TAP ............. . 6110
Type TAM ............ . 11114
PACKAGE DIMENSIONS
-SECTION 1 7 - - Package Dimensions ..... 1 17
ZENER DIODES
---SECTION 13 ...· - 1 N746/759 .............. 1,2
1 N957/973 .............. 3,4
1 N4729/4752 ........... . 5/7
1 N5226 15257 .......... . 8/10
TUNER DIODES
---SECTION 1 4 - - ITT109 .................. 1,2
ITT141 .................. 3,6
ITT142 .................. 3,6
ITT21 0 .................. 7,8
ITT243 ................... 9
ITT244 ·................... 9
V-Series Variable Between
5pF and 60pF ......... 10,11
U-Series Variable Between
2pF and 18pF......... : 12,13
INTEGRATED CIRCUITS DICE AND WAFERS
All ITT integrated circuits are available both in wafer and in chip
form. Since the completed individual encapsulated product is·
capable of being more extensively and thoroughly tested than the
wafer, these specifications are limited to the capability of the chip
and the attendant testing equipment.
USE
DTL and Linear circuits are normally supplied with plain
backing. Gold backing can be furnished upon special
request. All other circuits are supplied with gold backing.
Recommended die attach temperature Is 420·C for either
type of backing. A 98% gold, 2% silicon preform is
recommended for die attach with all plain-backed chips.
One mil aluminum wire, ultrasonically bonded to the pads,
is recommended for connecting the chip to the circuit.
PACKAGING FOR SHIPMENT
I. C. WAFER PACKAGE
Wafers will be shipped in the plastic package shown.
Chips will be packaged in carriers as indicated.
IDENTIFICATION
All integrated circuit dice will be identified by the
appropriate three or four-digit code, together with the
individual suffix number indicating the temperature range.
For example, a 930 limited-temperature range chip would
be a "930-5." A 930 full-temperature range chip would be a
"930-1."
CHIP PACKAGE
MIL AND HI-REL SEMICONDUCTORS
MIL38510. Many diodes and transistors are available
as JAN, JAN/TX, or MI L types.
Virtually all ITT Semiconductors are available with
hi-rei processing. IC's, for example, can be processed
for any portions of, or all of, MIL-STO-883 and
Whenever you need hi-rei semiconductors, check
ITT. Your local representative can give up-to-date
information on availability, price, etc.
3-0
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... JI[~~ __________________TT__L_N_U~M_E_R_IC_A_L__IN_D_E_X
SEMICONDUCTORS
Type
Description
,Type
Quad 2 ilp NAND
Quad 2 ilp NAND (open collector
5.5V rating)
ITT 7402
Quad 2 il P NOR
Quad 2 ilp NAND (open collector
ITT 7403
5.5V rating)
. ITT 7404
Hex inverter
ITT 7405
Hex inverter (open collector 5.5V
rating)
ITT 7406
Hex inverter bufferldriver (open
collector 30 V rating)
ITT 7407
Hex blifferl driver (open-collector
30 V rating)
ITT 7408
Quad 2 ilp AND
ITT 7409 ' Quad 2 ilp AND (open-collector)
ITT 7410
Triple 3 ilp NAND
ITT 7411
Triple 3 ilp AND
ITT 7412
Triple 3 ilp NAND (open-collector
5V rating)
ITT 7413
Dual 4 ilp Schmitt Trigger
ITT 7416
Hex inverter bufferl driver (opencollector 15V rating)
ITT 7417
Hex bufferl driver (open-collector
15V rating)
ITT 7420
Dual 4 il P NAND
ITT 7421
Dual 4 il P AND
ITT 7425
Dual 4 ilp NOR.(with strobe)
ITT 7426
Quad 2 il P high voltage interface
NAND(open collector)
ITT 7428
Quad 2 ilp NOR buffer
ITT 7430
8 ilp NAND
ITT 7432
Quad 2 i/p OR
ITT 7433
Quad 2 ilp NOR buffer (open collector 5.5V rating)
ITT 7437
Quad 2 ilp NAND buffer
ITT 7438
Quad 2 ilp NAND buffer (open
collector 5.5V rating)
ITT 7440
Dual 4 il P NAND buffer
ITT 7442
B. C. D. to decimal decoder
ITT 7443
Excess 3 to decimal decoder
ITT 7444
Excess 3 gray to decimal decoder
ITT 7445
B.C.D. to decimal decoder (open
collector 30V rating)
ITT 7446A
BCD to seven segment Decoderl
driver ("open collector 30V rating)
ITT 7447A
BCD to seven segment Decoderl
driver (open collector 15V rating)
ITT 7448
BCD to seven segment decoderl
Driver (2k pull up)
ITT 7450
Expandable dual 2 wide, 2 ilp
A.O.1.
ITT 7451
Dual 2 wide, 2 ilp A.O.1.
Expandable 4 wide, 2 ilp A.O.I.
ITT 7453
ITT 7400
ITT 7401
3-1
ITT 7454
ITT 7460
ITT 7470
ITT 7472
ITT 7473
ITT 7474
ITT 7475
ITT 7476
ITT 7480
ITT 7482
ITT 7483
ITT 7486
'ITT 7490
ITT 7491 A
ITT 7492
ITT 7493
ITT 7494
ITT 7495A
ITT 7496
ITT 74104
ITT 74105
ITT 74107
ITT 74109
ITT 74118
ITT 74121
ITT 74122
ITT 74123.
ITT 74124
ITT 74130
ITT 74131
ITT 74135
ITT 74137
ITT 74138
ITT 74139
ITT 74141
ITT 74145
ITT 74150
ITT 74151
ITT 74153
ITT 74154
Description
4 wide, 2 i/p.A.O.1.
Quad 2 il P expander
Edge-triggered J-K flip-flop
J-K master-slave flip-flop
Dual ·J-K master-slave flip-flop
Dual D-type edge-triggered flipflop
Quad bistable latch
Dual J-K master-slave flip-flop
with preset and clear
Gated full adder
2-bit full adder
4-bit full adder
Quad 2 il P exclusive-OR
Decade counter
8-bit shift register
Divide by 12 counter
4-bit binary counter
.
5-bit shift register
4-bit shift register (reversible)
4-bit shift register
Gated J-K master-slave flip-flop
Gated J-K master-slave flip-flop
Dual J-K master-slave flip-flop
Dual J-K positive-edge-triggered
flip-flop with preset and clear
Hex set-reset latch
Monostable· multivibrator
Retriggerablo monostable multi vibrator with; clear
Dual retriggerable monostable
multivibrator with clear
Universal pulse generator
Quad 2 ilp AND buffer (open collector 30V rating)
Quad 2 lip AND buffer (open collector 15V rating)
Quad 2 i/p positive NAND schmitt
trigger
Hex inverter Schmitt Trigger
Quad 2 il P OR buffer (open collector 30V rating)
Quad 2 ilp OR buffer (open collector 15V rating)
B.C.D. to decimal decoderldriver
B.C.D. to decimal decoder (opencollector 15V rating)
16-bit data selectorl multiplexer
8-bit data selectorl multiplexer
Dual 4-llne-to-1-llne datasehictorl
multiplexer
4-1 ine-to-16-line decoder Idem u It iplexer
TIL NUMERICAL INDEX
Type
ITT 74155
ITT 74156
ITT 74157
ITT 74160
ITT 74161
ITT 74162
ITT 74163
ITT 74164
ITT 74165
ITT 74174
ITT 74175
ITT 74180
ITT 74181
ITT 74182
ITT 74190
ITT 74191
ITT 74192
ITT 74193
ITT 74194
ITT 74195
ITT 74HOO
ITT 74H01
ITT 74H04
ITT 74H05
ITT 74H10
ITT 74H11
ITT 74H20
ITT 74H21
ITT 74H30
ITT 74H40
ITT 74H50
ITT 74H51
ITT 74H53
ITT 74H54
ITT 74H60
ITT 74H72
ITT 74H73
Description
Dual 2 to 4 line decoder/demultiplexer
Dual 2 to 4 iine decoder/demultlplexer (ole 5-5V rating)
Quad 2-line-to-1-line data selectorI multiplexer
Synchronous 4-bit counter
Synchronous binary up counter
Fully syncnronous counter
Fully synchronous counter
8-bit parallel-out serial shift
register
Parallel-load 8-bit shift register
Hex D-type flip-flop
Quad D-type flip-flop
8-bitparity generatorl checker
Arithmetic logic unit I function
generator
Look-ahead carry generator
Synchronous upl down counter
with downlup mode control
Synchronous upldown counter
with downlup mode control
. Synchronous BCD-upl down
counter
Synchronous binary 4-blt upl
down counter
4-bit bidirectional universal shift
register
4-bit parallel-access shift register
Quad 2 ilp NAND
Quad 2 ilp NAND (open-collector
output)
Hex inverter
Hex inverter with open-collector
output
Triple 3 ilp NAND
Triple 3 ilp AND
Dual 4 il P NAND
Dual 4 il P AND
8-input NAND
Dual 4 i/p NAND
Dual 2-wide 2 ilp and-or-invert
gate (one gate expandable)
Dual 2-wide 2 il P and-or-invert
gate
Expandable 4-wide and-or-invert
g~e
4-wide and-or-invert gate
Dual 4 ilp expander
and-gated J-K master-slave flipflops with preset and clear
Dual J-K flip-flops with clear
-
Type
Description
ITT 74H74
Dual d-type positive-edgetriggered flip-flop with preset and
clear
Dual J-K flip-flops with preset and
clear
ITT 74H76
ITT
ITT
ITT
ITT
ITT
ITT
9000
9001
9002
9003
9004
9005
ITT 9006
ITT 9007
ITT 9008
ITT
ITT
ITT
ITT
ITT
ITT
ITT
ITT
.ITT
9009
9016
9020
9022
9300
9301
9304
9308
9309
9311
ITT 9312
ITT 9316
ITT 9322
ITT 9328
ITT 9601
ITT 9602
in
3-2
J-K Flip-flop
J-K Flip-flop
Quad 2 il P NAND gate
Triple 3 ilpNAND gate
.
Dual.4 il p NAND gate
AND-OR-invert gate, dual 2-wide,
2 il p, expandable'
Dual 4 il p extender
Single 8 ilp NAND gate
And-or-invert gate, expandable
4 wide, 2 ilp
Dual 4 i I p Buffer
Hex inverter
Dual J-K Flip flop
Dual J-K Flip flop
4-Blt Shift Register
One-of-Ten Decoder
Dual Full Adder
Dual 4-Bit Latch
Dual 5-lnput Multiplexer
One-of-16 Decoder
8-lnput Multiplexer
HexiClecimal Counter
Quad. 2-lnput Multiplexer
Dual 8-Bit Shift Register
Retriggerable One Shot
Dual Retriggerable One Shot
TTL FUNCTIONAL INDEX
Positive-NAND Gates And Inverters With
Totem-Pole Outputs
Function
Type
Hex Inverters ........................ 74H04
7404
9016
Quad 2 i/p NAND ..... : ............. .74HOO
7400
9002
Triple3 i/p NAND .................... 74H10
7410
9003
Dual 4 i/p NAND ..................... 74H20
7420
9004
8i/pNAND ......................... 74H30
7430
9007
Positive-NAND Gates And Inverters With
Open-Collector 9utputs
Hex Inverters ........................ 74H05
.
7405
9017
Quad2i/pNAND .................... 74H01
7401
7403
9012
Triple3 i/p NAND ..................... 7412
Positive-NOR Gates With Totem-Pole Outputs
Buffer And Interface Gates With
Open-Collector Outputs
Function
Type
Hex Buffersl Drivers ................... 7407
7417
Hex Inverter Buffersl Drivers ............ 7406
7416
Quad 2 il P NAND ...................... 7426
7438
Quad 2 i/p NOR ....................... 8433
Quad 2 i/p AND ...................... 74130
74131
Quad 2 i/p OR ....................... 74138
74139
Positive-OR Gates With Totem-Pole Outputs
Quad 2 il P OR ........................ 7432
AND-OR Invert Gates With Totem-Pole
Outputs
4-Wide 2-2-3-2-input .................. 74H54
4-Wide 2 il P ................ : ......... 7454
Dual 2-Wide 2 i I p .................... 74H51
7451
Expandable Gates
4-Wide AND-OR invert ................ 74H53
7453
9008
Dual2-Wide AND-OR invert ............ 74H50
7450
9005
Quad 2 il P NOR ....................... 7402
Dual 4 il p NOR with strobe ............. 7425
Positive-AND Gates With Totem-Pole Outputs
Quad2i/pAND ....................... 7408
Triple3i/pAND ..................... 74H11
Dual4i/pAND ...................... 74H21
Positive-AND Gates With Open-Collector
Outputs
Quad2.i/pAND ....................... 7409
Schmitt-Trigger Positive-NAND Gates And
Inverters With Totem-Pole Outputs
Hex Schmitt Trigger Inverters .......... 74137
Quad 2 il P NAND Schmitt Triggers ...... 74135
Dual 4 i/p NAND Schmitt Triggers ....... 7413
Buffers! Clock Drivers With
Totem-Pole Outputs
Quad 2 il P NOR ....................... 7428
Quad 2 il P NAND ...................... 7437
Dual 4 i/p NAND ................... , .74H40
7440
9009
Expanders
Dual4i/p ............................ 7460
74H60
9006
Flip-Flops
Dual J-K edge-triggered ............... 74109
9024
Single J-K edge-triggered ............... 7470
Dual pulse-triggered .................. 74H73
7473
74107
74H76
7476
9020
9022
Single pulse-triggered ................ 74H72
7472
Gated J-K Master Slave ................ 74104
74105
9000
9001
D-Ty~e Flip-Flops
Dual .......................... 7474,74H74
3- 3
TTL FUNCTIONAL INDEX
Monostable Multivibrators With
Schmitt-Trigger Inputs
Function
Type
Single .............................. 74121
Retriggerable Monostable Multivibrators
Single .............................. 74122
9601
Dual ................................ 74123
9602
S-R Latches
Hex S-R ............................. 74118
Adders
Sir4gle 1-bit gated full .................. 7480
Single 2-bit full ........................ 7482
4-bit arithmetic logic units/
function generators ................... 74181
Look-ahead carry generators .......... : 74182
Dual1-bit fu II ......................... 9304
Parity Generators! Checkers
8-bit odd/everi ....................... 74180
Other Arithmetic Operators
Quad 2 i/ P exclusive-or gates with
totem-pole outputs .................... 7486
Shift Registers
4-bit parallel-in parallel-out
(bidirectional) ........................ 74194
5-bit parallel-in, parallel-out. ............ 7496
4-bit parallel-in, parallel-out. ........... 74195
9300
7495A
Serial-in, parallel-out, 8-bit ............ 74164
8-bit parallel-in, serial-out ............. 74165
4-bit parallel-in, serial-out .............. 7494
8-bit serial-in~ serial-out ............... 7491 A
Dual 8 Bit serial in - serial out ........... 9328
Pulse Generators
Function
Type
Universal pulse generator .............. 74124
Latches
DG (clocked) latches ................... 7475
Dual 4-Bit ............................ 9308
Decoders! Demultiplexers
4-line-to-16-line ...................... 74154
9311
Dual 2-line-to-4-line ................... 74155
74156
4-lineto10-line ....................... 7442
7443
7444
9301
Open-Collector Display
Decoders! Drivers
BCD-to-decimal ....................... 7445
74145
74141
BCD-to-seven-segment .... '........... 7446A
7447A
7448
Data Selectors! Multiplexers
Dual 4-bit ............................ 9309
74153
8-bit ........................... ~ ..... 9312
74151
Quad 2-bit ............................ 9322
74157
16-bit ............................... 74150
Asynchronous Counters
Decade .............................. 7490
Divide by 12 .......................... 7492
4-bit Binary ........................... 7493
Other Registers
Hex D-type registers .......... ; .... -... 74174
Quad D-type registers ................. 74175
Synchronous Counters-Positive-Edge
Triggered
Decade ............................. 74162
74160
Decade up/down ..................... 74192
74190
4-bit binary .......................... 74163
74161
74193
74191
9316
3-4
GENERAL INFORMATION ITT54/74 SERIES TTL FAMilY
This series offers a wide range of digital integrated
circuit devices from simple NAN D gates to large
complex functions. They form a TTL family
(Transistor-Transistor Logic) guaranteed to operate
over the following ambient temperature ranges.
Military range. 54 series
Industrial range. 74 series
For ease of reading. the data only refers to the
ITT7400 series family but it is equally applicable
to the ITT5400 series. Where there are exceptions
these are clearly indicated on the individual data
sheets concerned.
-15°Cto 125°C
O°C to 75°C
LOGIC DEFINITION
All devices operate over a frequency range between
D.C. and typically 20 M Hz. and are fully compatible
with all 5417 4 series TTL and 930 series DTL.
Clamping diodes are provided at the inputs to
enhance the inherent high noise immunity when
driving transmission lines. Most outputs are of
totem pole configuration to give good drive capability. i.e. high fan-out, especially into large
capacitive loads. Other outputs include an opencircuit collector connection.
Positive logic is used throughout the data sheets.
This is defined as follows.
Logical '0'
<0.8V
Logical '1'
>2.0V
Low voltage; typically 0.2 V but
High voltage; typically 3.3 V but
Current flowing into a device terminal is defined as
positive.
D.C. CHARACTERISTICS COMMON TO ALL
DEVICES (except where otherwise stated)
FEATURES
High speed-typical propagation delay (gate) of
9 ns.
Guaranteed noise margin-greater than 400
mY.
Low power dissipation-l0 mW per gate at
50% duty cycle.
Worst case fan-out of 10.
Low output impedance.
Logic levels guaranteed over range of supply
voltage and operating temperature.
Wide range of functions-many SSI and MSI
functions.
Compatible with other DTL. TTL logic series.
INTRODUCTION TO TTL
The TTL circuit configurations are designed so that
the uniform logic and noise margin levels apply to
all the standard devices in the families. Thus many
parameters and their limits are common. In addition
the operating conditions are identified for each family. Once these standard operating conditions are
understood it becomes possible for the designer to
use the family by simply referring to the logic and
connection diagrams on each data sheet. All i:om~
mon information is included in the remainder of this
section.
D.C. tests are carried out under the specified conditions. All inputs and outputs are tested for all possible logic states. Worst state load currents and
voltages are applied and the test limits are applicable over the full temperature range.
Min.
Max.
Unit
Supply voltage. VCC:
74 series
4.75
5.25
V
54 series
4.5
5.5
V
Operating temperature:
74 series
75
0
°c
-55
54 series
125 °c
D.C. noise margin typically greater than 1 V.
ABSOLUTE MAXIMUM RATINGS
(above which the useful life of the device may be
impaired)
Continuous supply voltage VCC (Note 1) ............. 7 V
Input voltage .......................................................... 5.5 V
Voltage between inputs ....................................... 5.5 V
Continuous input current ............................... -1 0 mA
Standard output voltage ....................... -0.5 to 5.5 V
Storage temperature! ..................... -65°C to 150°C
Note 1
This rating is reduced to 5.5 V if unused inputs are
connected directly to V CC.
3-5
GIENERAl INFORMATION ITT54/74 SERIES TTL FAMILY
STAN DARD CHARACTER ISTICS (limits'apply over the full range of operating temperature and fo'r standard totem Dole outout exceot where otherwise stated).
PARAMETER
LIMIT (Note 8)
CONDITIONS
Min.
V IH
Typ.
Max. Unit
2.0
Min.
VOL 204 V (Note 1)
0.8
V
Min.
VOL <0.4 V or VOH > 2.4 V (Note 2)
0.22 004
V
Min.
IOL = 16 mAo VIH = 2 VorVIL = 0.8V
(Note 3)
3.3
V IL
VOL (standard output)
VOL (buffer output) VOH
2.4
VCC
V
V
Min.
VI L = 0.8 V or VOH = 2.0 V (Note 4)
250
uA
Min.
V,L = 0.8 V. V,H = 2 V. VOUT = max.
alp voltage rating
1.6
mA
Max.
VF = 0.4 V (Note 5)
IR
40
uA
Max.
VR = 204 V. input loading-l unit
load (Note 6)
IR
1.0
mA
Max.
VR = 5.5 V irrespective of input loading"
I CEX open collector only
-IF
1.0
-ISC
54 series
20
55
mA
Max.
V OUT = 0 V (Note 7)
74 series
18
55
mA
Max.
V, H = 2.0 V or VI L =0.8 V; apply according
to logic function
Where characteristics for devices differ from the above table these are shown in the data sheets.
Note 1
Condition at outputs dependent on the truth table
of the device. For example. for gates and buffers.
VOL <004 V applies. and for flip-flops. shift registers. counters. decoders. etc. either VOL <004 V
or V OH >204 V applies at each output. Output conditions do not apply for 7486. 7460. 7445. 74145.
and 7441A. This parameter does not apply for
7413 and 74121 because of the Schmitt trigger
inputs.
Note 2
Conditions at outputs dependent on the the truth
,table of 'the device. for example. for gates and inverters V OH >204 V. Output conditions do not apply for devices with open collector output. This
parameter does not apply for 7413. 74121.
Note 3
Conditions VI H and VI L depend on device truth table. Limits for 7441 A. 7445 and 74145 are shown
on the appropriate data sheets.
Note 4
This parameter for totem pole output devices only.
VI L and VI H apply according to the truth table.
IOH = -400 uA for devices with Fan-out=; 0;
IOH=-800 uA for devices with Fan-out=20;
IOH = -1.2 mA for devices with Fan-oLit=30. etc.
Note 5
Limits apply for an input loading of 1 unit load; for
other input loadings mUltiply limits by number of
unit loads. For flip-flops. see appropriate data for
test conditions.
N~e6
i
For other inputs at 0 V for 7472. 7473. 7476.
74107. For 7470 all other inputs at 0 V except J
and K which are at 4.5 V. For 7474 consult data
sheet. Limits to be mUltiplied by the input loading
of the device.
Note 7
Maximum limit = 57 mA for devices with internal
feedback connections. (e.g. flip-flops and some
complex devices). For 7400 series simple NAN D
gates not more than two outputs may be shorted
at any time. For all other devices and for all 5400
series not more than one output" to be shorted at
any time. Open collector devices; no parameter for
ISC'
3-6
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
Note 8
Typical limits are at ambient temperature.
TA =25°C and VCC= 5 V.
ORDERING CODE FOR TTL CIRCUITS
Operating Temperature Range
5400 series -55to +125°C
7400 series 0 to +70°C
A.C. TESTS
Testing of propagation delays is carried out using
the typical switching load circuits shown below.
These load circuits are designed to simulate full fanout loading. An oscilloscope with high impedance
probes and having a bandwidth of at least 100 MHz
is suitable for these measurements.
Package (add)
B for Flat Pack
J for Ceramic Dual In-Line
N for Plastic Dual In-Line
Example:
ITT7400J
is O°C to +70°C Range in
Ceramic Dual In-Line Package
I
TYPICAL SWITCHING TEST LOAD CIRCUITS
For totem pole outputs:
Vee
DEVICE DIp
~O-~~~~-4--~~__~~~---'
OUTPUT
Notes
1. Diodes are type 1N4148.
2. The values of CL and RL are quoted in the data
sheets. Value of CL includes probe and jig
capitance.
'3. The characteristics of the pulse generator used
at the input of the device are stated in the data
sheets. Typical characteristics are: VOUT = 3.5
V; Rise time. tr. = Fall time. !to = less than 15
ns; Zo = 50 0: Pulse Repetition Frequency.
P.R.F. = 11 MHz: Pulse width for gate. tp = 500
ns.
For open collector outputs:
Waveforms
,
OUTPUT
I
I
,
I
I
k-
t .....
-a--i- -- t
I
I
---50%
-t' \ '- - - - - ~
OUTPUT
100/.
I,.
~I
• I \I
tpd_
.... I.~.d+
-"tft--1tr~
::....t 14-., ..-
I
1-5 V
3-7
-90%
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
1. HIGH lOGIC STATE '1' (ON STATE)
The NAN D gate has two stable operating states. These are illustrated in Figs. 1A and 1 B.
+5Y
\II
RG
'II«
IG
""' Ie
>
MULTIPLE·
EMITTER
TRANSISTOR
130
r.::
'-!.;
tHY
Q
LOAD
'G+le+'IIR
fL
~
J
n-t==
I
VTl
10 GATES
Fig.1A. Typical 'ON' conditions
with all inputs Logic '1' .
~
......
--
J
1K
IA
I
'_(T1
+0·2 V ~ ~-.
vn
R8
II'.
j~ ~~
rr+-r-oJ. L_
I
'L
"'-0·7 V
II'.
D
~
~
+5V
IV VTJ
'!:
I,.
+HV t C
+sv
;>
D1~r
)
\
+HV
HK
?'
+2·1 V
\
INPUTS
RL
+0·9 V
(MET)
+J.3V ~t+J.3v ~ 8
Re
""
"'ll
= 16 mAmax
r---~----------~--------------~~------+SV
Ie
Re
UK
Ie
MET' +0·9 V
VT1
, I'
lOAD OF
\
+0·) V
IG+3 I",
+0·2V
+HV
+HV
II
A
B
I",
C
I",
0
'1",
R6
1K
+HV
-
Fig. 1B. Typical 'OFF' conditions
with one input Logic '0'.
3-8
BV
10 GATES
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
The d.c. operation of this circuit is more readily
understood if the multiemittertransistor (M ET) connecting the inputs is considered equivalent to a
diode AND gate in series with an offset diode connected to the base of transistor VT1. This is shown
in Fig. 2, the emitter-base junctions of the MET
forming the input diodes and the collector base
junction forming the offset diode.
Fig. 2. Simplified analogy of TTL gate.
+5V
Rc
Rg
Rl
r.::I
~
VT3
VT1
r.;
A
~
~
VT2
RO
C
o
The opposite state shown in Fig. 1 B is achieved
if the voltage of any number of inputs is reduced
below a threshold level of about +1.5 volts. Fig.
1 B shows the conditions when input A is at +0.2
volts (a typical output voltage of a previous gate).
No base current flows into, VT1 since the collector
of the MET is attoo' Iowa potential. with respect
to its base.
Therefore, no current will flow through VT1 and
VT2 other than leakage current (which can be
neglected in this analysis). The transistor VT3 will
conduct to provide sufficient output current to
maintain following gates connected to the output
terminal at 3.3 V positive in logic 1. The fan-out
is high (10) under worst case conditions because
of the low output impedance of VT3.
3: CHANGEOVER BeTWEEN STATES
Q
{
a
2. LOW OR OFF STATE
=
When all the inputs are positive a logic '1' current
flows from the positive supply through Rg into the
base of VT1 which heavily conducts and turns VT2
'ON' into the saturated state. Since both
and
VT2 are saturated, there is insufficient voltage
across the base emitter terminals of VT3 to render
it conducting. The output voltage is'about +0.2 V,
(i.e. saturation voltage of VT2). The collector current of VT2 will consist of the total 'sinking' current
from the gates connected to the output terminal.
When the base current drive to VT2 is high, VT2
can remain saturated even with a large collector
current. with adverse circuit tolerances and temperature variations. This permits a fan-out of up to
10. With a multiemitter transistor, more current
flows from a positive held input than with a COh,ventional D.T: L. gate (the leakage current of the, re~
vn
The, transistor action of the MET considerably imprbves the' switchi,ng speed when compared with
a bTL gate: In switching from the ON to the OFF
state the MET saturates and rapidly removes the
charge stored in VT1 turning it off. Then VT2 begins
to turn off and VT3 turns on as the collector potential of VT1 rises. VT3 assists VT2 to turn off and
pulls the output terminal rapidly positive, charging
any load capacitance. The diode D1 helps to prevent VT2 and
from conducting simultaneously
and RL limits the current through VT3 to a safe
value during the switch over if the output terminal
is accidentally shorted.
vn
Fig. '3. Propagation delay waveforms.
,--_ _ _...... v tH
~'_. +HV
1
-::.71--- ----'1'-- -- -- -
1t."~UT _ _
V~lTAGE
I
I
... ",",
I
OUTPuT
VOLTAGE
I
I
1
r- IO , , ' ,
~I
I
VOH
--1- ----1-- . . .;,. __ _
-l
1
I
I
+1-5 V
1--1
,
V1L
I
vo,''I
,L
I
I'
' -1,1, ,
'l·tPd··:r
"
I
I
I
I
I.
I
1
1_'PeI. . .
verse biassed input diode) since the MET is biassed' ' " Switching from the, OFF to the ON state is more
in the inverted mode and the functions' of emitter
rapid than ON to OFF since none of the transistors
VT2 arid MET are saturated in the OFF conand collector are reversed. However, the MET is dedition. The switch to the ON condition is particularly
signed to have a very low inverse gain and IR is
kept to a minimum. IR will equal the emitter base
fast owing to additional drive by transistor VT1 in
leakage current plus the product of inverse current
turning on VT2. Fig. 3 shows the typical switching
gain and IG.
times from this gate.
vn,
,3-,: 9
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
NOISE IMMUNITY
The noise immunity of the TTL gate is typically
greater than 1 volt and is guaranteed 0.4 V minimum under worst case conditions for temperature
and loading tolerances. The noise immunity is derived from the difference between extreme limits of
input voltage and the voltage required to ensure the
change of a logic state. This is illustrated by the
transfer characteristic shown in Fig. 4.
+3-6 V t - - - - ,
Lowest loglt '1'
level of available
output (and Input)
voltage
Fig. 4. Typical transfer characteristic
showing noise margins .
'"
m
."
n
:ii
m
""
m 0
§
~
Z
Highest logic '0'
output
(and available input)_ VoL
volt.ge
VOL
For input voltaces ~t
above this level the NM
devlto will remain
Vil
in the 'ON' state
t
For input voltages
below this level the
V1H device will remain
in the 'OFF' state
BASIC RULES FOR THE USE OF TTL
DEVICES
1. Spare inputs should be connected to used inputs if the fan-out permits. Otherwise connected
to the Vee power line via a resistor of value 1
K ohm or greater. This is particularly important
for the 'preset' and 'clear' asynchronous inputs.
2. Gates from the same package may be paralleled
where necessary for better driving capability.
3. Interconnection lengths of 12 inches or less
(capacitance of about 50 pF) are unlikely to give
ringing problems; lengths up to 24 inches are
possible with good ground arrangements. Greater length will probably require line driving precautions (see separate Application Note)
Note: NM-Noise margin
4. Wired-OR' can be performed at the output terminals of open-collector networks however a
speed penalty is incurred by the introduction of
a resistive pull-up.
5. In calculating system speeds, due allowance
should be made for the maximum set-up and
minimum clock pulse width times on flip-flops,
as well as the propagation delays of the elements used.
6. If relays are driven from TIL circuitry, care must
be taken to ensure that the load connection
wires to the relay contacts do not introduce
noise into the logic system. This can be done
by allowing these wires only to enter the logic
system enclosure at a point close to the relay
contacts, or in extreme cases by also shielding
the relay.
3-10
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
7. Similarly extemal inputs should be brought on
to the printed circuit con~ections at right angles
to the other wiring, the printed circuit itself being laid out to ensure least coupling between
inputsand other ·connections.
8. If system speed is high, allowance should be
made when calculating power supply requirements for the' increased network supply currents
due to current spiking and line driving .. An allowance at 10 MHz of 15% for spiking and up
to 0.5 mA per each gate node for the line driving
wi" be adequate for this.
9. Decouple' every'1 0 gates or their equivalent in
MSI functions with 0.01 uF to 0.1 uF capacitors
of R. F. rating.
In conclusion, a careful perusal of the data sheet
together with the points mentioned above, will help
in achieving a trouble free logic design at the first
attempt.
When driving ITT930 series DTL from 74/5400 series TTL the full fan-out of the TTL is available
. DRIVING TTl L.OGIC FROM DTl DEVICES
Driving ITT7400 series TTL from ITT930 series DTL
necessitates a reduction of the full fan-out from 8
to 3 for standa(d'igates and from 25 to 20 for
buffers. Increas~d' f~n-out can be achieved with
standard DTL gates by using an additional pull-up
resistor.
SYMBOLS AND THEIR DEFINITIONS
ICCL
High state output current.
Supply current.
Input current at V T +
Input current at VTDynamic power dissipation.
Load resistor in switching test circuit.
Ambient temperature.
Input hold time ..
Logical '1' hold time.
Logical '0' hold time.
, Clock pulse width.
Preset,or clear pulse width.
Output pulse width.
Propagation delay to logical '1' on output.
Propagation delay to logical '0' on output.
State of output (or input) before the
active edge of the clock pulse.
State of output (or input) after the active edge of the clock pulse.
Minimum width trigger pulse.
t-min
Logical '1' input set up time.
t sp
Logical '0' input set up time.
t sp Supply voltage.
VCC
Hysteresis voltage.
VH
Input high voltage to ensure VOL (or
VIH
V OH )"
,
Input low voltage to ensure V OH (or
V IL
VOL)"
Output low voltage.
VOL
Output high voltage.
VOH
Output brl,lakdown voltage of open
VOH(M).
collector device.
Voltage at an input.
VIN
Voltage at an output.
VOUT
Positive edge threshold voltage.
VT
Negative edge threshold voltage.
VTWIRED-OR The commoning of open collector outputs with a pull-up resistor to perform
the AN D, function.
ICC
IIN+
IINPdyn
RL
TA
th
th+
thtcp
tp
tpo
tpd+
+
DRIVING DTllOGIC FROM TTL DEVICES
Fan-out
'i OH
+
Load capacitor iri switching test circuit
(includes probe and jig capacitance):
Number of unit loads an output car)
drive.
Maximum clOck frequency.
Supply current for highest dissipation
logic state.
Supply current for lowest dissipation
logic:; state.
Input forward current.
Input reverse. current.
Output short circuit current.
Output leakage current.
Low state output current.
"Output'level dependent on device logic as found
from truth table.
3-11
APPLICATION DATA FOR OPEN COLLECTOR DEVICES
Combined Fan-Out and Wire-OR Capabilities
where: V R L is the voltage drop in
volts. and IRL is the current in amperes.
The open-collector TTL gate. when supplied with
a proper load resistor (R). may be paralleled with
other similar TTL gates to perform the wire-OR
function. and simultaneously. w.ill drive from one to
nine TTL loads. When no other open-collector gates
are paralleled. this gate may be used to drive ten
TTL loads. For any of these conditions an appropriate load resistor value must be determined for
the desired circuit configuration. A maximu m
resistor value must be determined which will
ensure that sufficient load current (to TTL loads)
and lout current (through paralleled outputs) will
be available during a logical 1 level at the output.
A minimum resistor value must be determined
which will ensure that current through this resistor
and sink current from the TTL loads will not cause
the output voltage to rise above the logical 0 level
even if one of the paralleled outputs is sinking all
the current.
Logical 1 (off level) Circuit Calculations (see
figure A)
The allowable voltage drop across the load resistor
(V RL ) is the difference between Vee applied and
the Vout( 1) level required at the load:
V RL
= Vee -Vout (1) required
The total current through the load resistor (I R L) is
the sum of the load currents (lin( 1)) and off-level
reverse currents (lout( 1 )) through each of the wireD R connected outputs:
IRL
= n olout(l) + N° lin(1) to TTL loads
Therefore. calculations for the maximum value of
RL would be:
R
in both conditions (logical 0 and logical 1) the value
of RL is determined by:
- Vee -V out (1) required
L(max) - n olout(l) + N olin(l)
where: n = number of gates wire-OR
connec!ed. and
number of TTL loads.
N
=
TTL LOADS
Calculation:
RL(max)
~
Vee - V out (1) required
Tl o lout(1) + N o lin(1)
5-2.4
= ~ = 2321 n
0.001 + 0.00012
0.00112
N =3
N° lin(1) = 3 o40I'A
'7
Tl
0
=4
lout(1) = 4
0
250 /JA
Calculation
R
- Vee -V out (l) required
+ N 0 Iload
L(max) - no I
out( 1)
FIGURE A -
R
_
5 - 2.4
L(max) - 0.001 + 0.00012
LOGICAL 1 CIRCUIT CONDITIONS
3-12
2.6
=2321Q
0.00112
APPLICATION DATA FOR OPEN COLLECTOR DEVICES
Logical 0 (on levell Circuit Calculations (see
figure BI
The current through the resistor must be limited to
the maximum sink-current capability of one output
transistor. Note that if several output transistors are
wire-OR connected. the current through RL may be
shared by those paralleled transistors. However. unless it can be absolutely guaranteed that more than
one transistor will be on during logical 0 periods.
the current must be limited to 16mA. the maximum
current which will ensure a logical 0 maximum of
0.4 volts.
Also. fan-out must be considered. Part of the 16mA
will be supplied from the inputs which are being
driven. This reduces the amount of current which
can be allowed through RL.
Therefore. the equation used to determine the minimum value of RL would be:
Vee - Vout(O) required
ISINK capability - ISINK from TTL loads
TTL LOADS
C.I,ul.lion,
RL(minl
=
_ __~Yc~c~__Y;~~t~lo~l_req~u_ire_d____
I'i,* 'op.bilily -
I'i,* from TTL lo.ds
I
S-
R
-
Llminl -
0.4
0.016 _ 0.0048
4.6
=-=
0.0112
4100
~
N=3
N • lin(O)
=3
• 1.6 rnA
t Current into OFF outputs i. negligible at logical O.
MAXIMUM I sink CAPABILITY
OF ONE ON OUTPUT = 16 mA
Calculation:
Vee - V~ut(O) required
RL(min) = ISINK capability - ISINK from TTL loads
5 - 0.4
RL(min)
0.016 - 0.0048
4.6
=
41000
0.0112
FIGURE B - LOGICAL 0 CIRCUIT CONDITIONS
3-13
.1
APPLICATION DATA FOR OPEN COLLECTOR DEVICES
Driving TTL Loads and Combining Outputs
Table 1 provides minimum and maximum resistor
values. calculated from equations shown above, for
driving one to ten TTL loads and wire-OR connect- ..
ing two to seven parallel outputs, Each value shown
'for wire-OR output one is determined by the fan~
out plus the leakage of a single output transistor.
Extension beyond seven wire~O R connections is
permitted with fan-outs of seven or. less if a valid
minimum and maximum RL is possible, When
fanning-out to ten, TTL loads the calculation for the
minimum value of RL indicates. that an .infinite .resistance should be used (V RL - 0 = 2.0V
Low voltage; typically Oi2 V but
i
High voltage; typically 3~3 V but
!
I
Current flowing into a device terminal is defined as
positive.
I
mY.
,
Low power dissipation-23 mW per gate at
500"{' duty cycle.
Worst case fan-out of 1 O.
Low output impedance.
Logic levels guaranteed over range of supply
voltage and operating temperature
Compatible with other DTL, TTL logic series.
D.C. CHARACTERISTICS COMMON TO ALL
DEVICES (except where otherwise stated)
D.C. tests are carried out under the specified conditions. All inputs and outputs are tested for all possible logic states. Worst state load currents and
voltages are applied and the test limits are applicable over the full temperature range.
I
INDEX FOR STANDARD 7400H SERIES
Min.
For the military range, replace 74H in the type
number by 54H.
Prefix the type number by ITT and end with J which
indicates the ceramic dual-in-line package.
For example: ITT5400 is a Quad 2-input NAND gate
device in 54 series logic with a ceramic dual-in-line
package.
Max.
Unit
~,upp,ly voltage, V CC:
'74H series
4.75
5.25
V
I
54H series
4.5
5.5
V
Operating temperature:
74H series
751°C
54H series
-'55
125°C
D.C. noise margin typically greater than 1
I
\
o
V.
I
I
I
3-14a
GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
ABSOLUTE MAXIMUM RATINGS
(above which the useful life of the device may be
impaired)
Continuous input current ............................... -1 0 mA
Standard output voltage ....................... -0.5 to 5.5 V
Storage temperature! ..................... -65°C to 150°C
Continuous supply voltage VCC (Note 1) ............. 7 V
Input voltage .......................................................... 5.5 V
Voltage betweel:' inputs ....................................... 5.5 V
Note 1
This rating is reduced to 5.5 V if unused inputs are
connected directly to VCC.
STANDARD CHARACTERISTICS (limits apply over the full range of operating temperature and for standard totem pole output except where otherwise stated).
LIMIT (Note 8)
PARAMETER
CONDITIONS
Min. Typ.
VIH
Max. Unit
2.0
2.4
VOH
Min.
VOL <0.4 VorVOH> 2.4 V (Note 1)
0.8
V
Min.
VOL <0.4VorVOH> 2.4 V (Note 2)
0.22 0.4
V
Min.
IOl = 20 mAo VIH = 2 VorVll = 0.8 V
(Note 3)
3.3
V
Min.
VIL = 0.8VorVOH = 2.0 V (Note 4)
Vll
VOL (standard output)
VCC
V
ICEX open collector only
250
uA
Min.
Vll = 0.8 V. VIH = 2 V. VOUT = max.
o/p voltage rating
-IF
2.0
mA
Max.
VF = 0.4 V (Note 5)
IR
50
uA
Max.
VR = 2.4 V. input loading-1 unit
loacl (Note 6)
IR
1.0
mA
Max.
VR = 5.5 V irrespective of input loading
100
mA
Max.
VO UT = 0 V (Note 7)
-ISC
54 series
40
Where characteristics for devices differ from the above table these are shown in the data sheets.
Note 1
Condition at outputs dependent on the truth table
of the device. For example. for gates and buffers.
VO l :S0.4V applies. and for flip-flops. either VOL
:S0.4V orVOH ~2.4V applies at each output. Output conditions do not apply for 74H60.
Note 4
This parameter for totem pole output devices only;
V ll and VIH apply according to the truth table. IOH
= -500 uA for devices with Fan-o.ut =10; IOH
= -1.0mA for 54H/74H74; IOH = -1.5mAfor
54H174H40.
. .
Note 2
Conditions at outputs dependent on the truth table
of the device. for example; for gates and inverters
VO H >2.4V. Output conditions do not apply for
devices with open collector output. This parameter
does not apply for 7413. 74121.
Note 5
limits apply for an input loading of 1· unit load; for
other input loadings multiply limits by number of
unit loads. For flip-flops. see appropriate data for
test conditions.
Note 3
Conditions VIH and Vil depend on device truth
table.
Note 6
All other inputs at OV for 74H72. 74H73.74H76.
For 74H74 consult data sheet. limits to be multiplied by the input loading of the device.
3-14b
GENERAL INFORMATION ITT54H/74H SERIES TTL FAMILY
Note 7
For all devices not more than one output to be
shorted at any time. Open collector devices; no
parameter for -I SC.
Diodes are type 1 N4148 or equiv.
The values of CL and RL are quoted in the data
sheets. Value of CL includes probe and jig
capitance.
Note 8
Typic,!I limits are at ambient temperature. TA
25°C and VCC = 5V.
The characteristics of the pulse generator used at
the input of the device are stated in the data sheets.
Typical characteristics are: VO UT = 3V; Rise time.
tr. = Fall time. tf. = less than 7 ns; Zo = 50; Pulse
Repetition Frequency. P.R.F. = 1 MHz; Pulse width
for gate. tp = 500 ns.
A.C. TESTS
Testing of propagation delays is carried out using
the typical switching load circuits shown below.
These load circuits are designed to simulate full fanout loading. An oscilloscope with high impedance
probes and having a bandwidth of at least 100 MHz
is suitable for these measurements.
Waveforms
BV / . - - - - - - - \ I N P U T
I
.
I
TYPICAL SWITCHING TEST LOAD CIRCUITS
I I
.
I
I
I
k- ' • .-.j
I
"5V~\-----~PUT
I
I I
For totem pole outputs:
'~
\.-
-.j
~+
I
-,90,),.
;..-~--___ _
50%
+ -- t
I I
10%
II
-tt"r-1'0f4-
DEVICEO'P
'~O-~-'~"~~~~~IM~IM----~
CIRCUIT DIAGRAM ITT74HOO GATE
r-----~~---------1~VCC
OUTPUT
I
,
1\
I,
For open collector outputs:
OEYICE'~/P,
RL Yee
~
,
I
-.
470!l.
4kfi
GND
CL
OUTPUT
COMPONENT VAWES ARE NOMINAL
The d.c. operation of this circuit is more readfly
understood if the multiemitter transistor (M ET) connecting the inputs is considered equivalent to a
diode AND gate in series with an offset diode connected to the base of transistor VTl. This is shown
in Fig. 2. the emitter-base junctions of the MET
forming the input diodes and the collector base
junction forming' the offs~t diode.
GENERAL INFORMATION ITT54H/74H SERIES TTL FAMILY
of the METis at too Iowa potential, with respect
to its base.
Fig. 2. Simplified analogy of TTL gate.
+5V
J
~Rc
R,
Therefore, no current will flow through VT1 and
VT2 other than leakage current (which can be
neglected in this analysis). The transistor VT3 will
conduct to provide sufficient output current to
maintain following gates connected to the output
terminal at 3.3 V positive in logic 1. The fan-out
is high (10) under worst case conditions because
of the low output impedance of VT3.
{RL
~
\.!:!
vn
VT1
r.:
\.!:!
•
Q
ra.
\.!:!
VTZ
R.
3, CHANGEOVER BETWEEN STATES
c
The transistor action of the MET considerably improves the switching speed when compared with
a DTL gate. In switching from the ON to the OFF
state the MET saturates and rapidly removes the
charge stored in VT1 turning it off. Then VT2 begins
to turn off and VT3 turns on as the collector potential of VT1 rises. VT3 assists VT2 to turn off and
pulls the output terminal rapidly positive, charging
any load capacitance. The diode D1 helps to prevent VT2 and VT1 from conducting simultaneously
and RL limits the current through VT3 to a safe
value during the switch over if the output terminal
is accidentally shorted.
T
D
When all the inputs are positive a logic '1' current
flows from the positive supply through Rg into the
base of VT1 which heavily conducts and turns VT2
'ON' into the saturated state. Since both VT1 and
VT2 are' saturated, there is insufficient voltage
across the base emitter terminals of VT3 to render
it conducting. The output voltage is about +0.2 V,
(i.e. saturation voltage of VT2). The collector current of VT2 will consist of the total 'sinking' current
from the gates connected to the output terminal.
When the base current drive to VT2 is high, VT2
can remain saturated even with a large collector
current. with adverse circuit tolerances and temperature variations. This permits a fan-out of up to
10. With a multiemitter transistor, more current
flows from a positive held input than with a conventional D.T. L. gate (the leakage current of the reverse biassed input diode) since the MET is biassed
in the inverted mode and the functions of emitter
and collector are reversed. However, the MET is designed to have a very low inverse gain and IR is
kept to a minimum. IR will equal the emitter base
leakage current plus the product of inverse current
gain and I G.
2, LOW OR OFF STATE
The opposite state shown in Fig. 1 B is achieved
if the voltage of any number of inputs is reduced
below a threshold level of about + 1.5 volts. Fig.
1 B shows the conditions when input A is at +0.2
volts (a typical output voltage of a previous gate).
No base current flows into VT 1 since the collector
Fig. 3. Propagation delay waveforms.
r------V'H
vo~~:~~ =i-------\-----t~~
I
"Bns;
I
I
OUTPUT
VOLTAGE
-I
,-TI
1
1
I
I
I
I
1
,-10 ns...,
~II,r--VOH
_~_
----1--'- __ _
VO l -
, i
v"
--l
I
1
I:
',d-.
f--
I
I
I
I
I
I
I
I
I
I
+HV
I
I
'pd+
I
I
Switching from the OFF to the ON state is more
rapid than ON to OFF since none of the transistors
VT1, VT2 and MET are saturated ,in the OFF con, dition. The switch to the ON condition is particularly
fast owing to additional drive by transistor VT1 in
turning on VT2. Fig. 3 shows the typical switching
times from this gate.
3-14d
__
ITT
ITT 5400 , ITT7400
QUADRUPLE 2-INPUT
__________________________
.a=-__
POSITIVE NAND GATES=
==================-==-="==""
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE
GATES
DUAL-IN- LINE PACI(AGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@4r
IB0
@)4B
Iz0
@4A
vccG
@GND
2r0
@3B
2A0
®3A
2B0
0
POSITIVE
NA~j[))
LOGIC:
3r
Z;As
POSITIVE LOGIC:
r;AS
schemati<: (each gate)
HO
1.6 kO
130 0
OUTPUT .2
L - - - 6 - - - _ 4 . -_ _L--o GND
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Min
Nom Max
5400 Circuits ........................................................................ .
7400 Circuits ........................................................................ .
4.5
4.75
5
5
Normalized Fan-Out From Each Output. N ............................................................. .
Operating Free-Air Temperature Range, TA: 5400 Circuits ............................... .
7400 Circuits .............................. .
-55
0
25
25
Supply Voltage V CC:
3-15
5.5
5.25
10
125
70
Unit
V
V
°c
°C
ITT5400, ITT7400
QUADRUPLE 2-INPUT POSITIVE NAND GATES
E LE CTR I CAL C H ARACTE R ISTI CS over recommended operating free-a ir temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Vin(l )
Logica I 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at either input
terminal to ensure logical 1
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vout (1)
Logica I 1 outp ut voltage
Vout(O)
Logical 0 output voltage
lin(O)
lin(l )
lOS
2
2.4
V
3.3
V
Logical 0 level input current
(each input)
-1.6
mA
Logical 1 level input current
(each input)
40
uA
lee(O)
Logical 0 level supply current
lee(1)
Logical 1 level supply current
0.22
V
0.4
Short-circuit output current 3
= Min Ii = -12 mA
Vee = MIN, Vin = 0.8 V,
Iload = -400 uA
Vee = MIN, Vin = 2V,
I sink = 16 mA
Vee = MAX, Vin = 0.4 V
Vcc
1
mA
Vee
Vee
-20
-55
mA
Vee
-18
-55
12
4
22
8
SWITCHING CHARACTERISTICS. Vec = 5V, TA = 25°C, N
Parameter
Test Conditions 2
Min
Typ
= MAX, Vin = 2.4 V
= MAX, Vin = 5.5 V
= MAX
ITT5400
ITT7400
mA
Vee
mA
Vee
= MAX, Vin = 5 V
= MAX, V in = 0
= 10
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
7
15
ns
CL = 15pF,R L
= 400n
tpd 1
Propagation delay time to
logical 1 level
11
22
ns
CL = 15 pF, R L
= 400.Q
, All typical values are at Vee = 5 V, TA = 25°e.
For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
2
3-16
__
ITT
.
ITT5401. ITT7401
QUADRUPLE 2-INPUT POSITIVE NAND GATES
_______________{_W_IT_H__
O_P_EN_-_C_O_L_LE_C_T_O_R_O_U_T_P_U_T)
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
lAG)
@4i!
IB0
@)4B
1i!G)
@)4A
VCCG
@GND
2i!0
@3B
2A0
®3A
2B(£)
G)3i!
POSITIVE
LOGIC:
i!=AB
POSITIVE
LOGIC:
i! = AB
schematic (each gate)
INPUTS
NOTE: Component values shown are nominal.
recommended operating conditions
Min
Supply Voltage V CC: 5401 Circuits .........................................................................
7401 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ..............................................................
Operating Free-Air Temperature Range. TA: 5401 Circuits ............................... .
7401 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-17
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT5401, ITT7401
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Vin (1)
Logical 1 input voltage required
at both input terminals to ensure
logical 0 (on) level at output
Min
Typ'
Max
. Test Conditions 2
Unit
V
2
Logical 0 input voltage required
at input terminal to ensure
logica I 1 (off) level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
10ut(1)
Output reverse current
250
uA
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
lin(O)
Logical 0 level input current
(each input)
-1.6
mA
= Min Ii = -12 mA
Vee = MIN. V in = O.BV.
V out(1) = 5.5V
Vee = MIN. V in = 2V.
Isink = 16 mA
Vee = MAX. V in = 0.4V
lin(l)
Logical 1 level input current
(each input)
40
uA
Vee
1
mA
Vee
. Vin(O)
lee(O)
Logical 0 level supply current
12
22
mA
lee(1)
Logica I 1 level supply current
4
8
mA
SWITCHING CHARACTERISTICS. Vee
Parameter
tpdO
tpdl
Propagation delay time to logical
Vee
= MAX. Vin = 2.4V
= MAX. Vin = 5.5V
Vee = MAX. Vin = 5V
Vee = MAX. V in = 0
== 5V. TA = 25°e
Min
Typ
Max
Test Conditions
Unit
8
15
ns
eL
= 15 pF. RL = 400 n
35
45
ns
eL
= 15 pF. RL = 4 kn
o level
Propagation delay time to logical
1 level
, All typical values are at Vee = 5V. TA =; 25°C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
2
3-18
ITT
----ITT5402. ITT7402
QUADRUPLE 2-INPUT POSITIVE NOR GATES
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NOR GATES
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@4i!
IB0
@)4B
4B
1i!0
@4A
4A
VCC0
4l
@GND
I
POSITIVE LOGIC:
i!' A+i'i
2i!CV
@3B
2A0
®3A
2B0
®3i!
POSITIVE LOGIC:
i!.m
schematic (each gate)
A
8o;--~---+----~
OUTPUT
y
'--_---<11_-------<11_--0 GNO
NOTE: Component values are nominal.
Recommended Operating Conditions
Min
Supply Voltage V CC: 5402 Circuits .........................................................................
7402 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ..............................................................
Operating Free-Air Temperature Range. TA: 5402 Circuits ............................... .
7402 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-19
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT5402, .ITT7402
QUADRUPLE 2-INPUT POSITIVE NOR GATES
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
lunless otherwise noted)
Parameter
Min
Typ'
Max
Vinl 1 )
Logical 1 input voltage
required at either input
terminal to ensure logical
o level at output
VinlO)
Logical 0 input voltage
required at both input
terminals to ensure logical 1
level at output
0.8
V
V1
Input elamp Voltage
-1.5
V
Vout l 1 )
Logical 1 output voltage
VoutlO)
Logical 0 output voltage
linlO)
linl1 )
lOS
2
Unit
2.4
Test Conditions 2
V
3.3
0.22
V
= Min Ii = -12 mA
Vee = MIN. V in = 0.8 V.
Iload = -400 uA
Vee = MIN. Vin = 2V.
Isink = 16 mA
Vee = MAX. Vin = 0.4 V
Vcc
0.4
V
Logical 0 level input current
leach input)
-1.6
mA
Logical 1 level input current
leach input)
40
uA
1
mA
Vee = MAX. Vin = 2.4 V
Vee - MAX. V in - 5.5 V
-20
-55
mA
Vee = MAX
-18
-55
Vee
Short-circuit output current 3
leelO)
Logical 0 level supply current
14
27
mA
lee(1)
Logical 1 level supply current
8
16
mA
SWITCHING CHARACTERISTICS. Vee
Parameter
I ITT5402
I ITT7402
= MAX. V in = 5 V
Vee = MAX. Vin = 0
= 5V. TA = 25°e. N = 10
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL
= 15pF.R L =4000
tpd1
Propagation delay time to
logical 1 level
12
22
ns
eL
= 15 pF. RL = 400n
=
=
All typical values are at VCC
5 V. TA
25°C.
• For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
1
3-20
ITT5403, ITT7403
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
ITT
----SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NAND
GATES (WITH OPEN-COLLECTOR OUTPUT)
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
schematic (each gate)
r----_+--.()
Vee
1.HO
OUTPUT
INPUTS
~---+-~~
~
GNO
NOTE: Component values shown are nominal.
POSITIVE
LOGIC
Z=As
Recommended Operating Conditions
Min
Supply Voltage V CC: 5403 Circuits .........................................................................
7403 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ..............................................................
Operating Free-Air Temperature Range. TA : 5403 Circuits ............................... .
7403 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-21
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT5403, ITT7403
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless othelWise noted)
Parameter
Typ1
Min
Max
2
Unit
Test Conditions 2
V in (ll
Logical 1 input voltage
required at input terminal to
ensure logical 0 (on) level at
output
V
Vin(O)
Logical 0 input voltage
required at input terminal to
ensure logical 1 (off) level at
output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vee = Min Ii = -12 mA
lout(1)
Output reverse current
250
llA
Vee = MIN. Vin = 0.8 V.
Vout (1) =.5.5 V
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
Vee = MIN. Vin = 2 V.
Isink = 16 mA
lin(O)
Logical 0 level input current
(each input)
-1.6
mA
Vee = MAX. Vin = 0.4 V
lin(1)
Logical 1 level input current
(each input)
40
).IA
Vee = MAX. Vin = 2.4 V
1
mA
Vee = MAX. Vin = 5.5 V
lee(O)
Logical 0 level supply current
12
22
mA
Vee = MAX. Vin = 5 V
lee(1)
Logical 1 level supply current
4
8
mA
Vee = MAX. Vin = 0
, All typical values are at Vee = 5 V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Z
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°C. N = 10
Parameter
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL = 15pF.R L =400S"l
tpd1
Propagation delay time to
logical 1 level
35
45
ns
eL = 15pF.R L =4kS"l
3-22
=
ITT'.
= = = = = = = = = = = = = = I T T =HEX
'=5=40=4,
ITT7404
INVERTERS
===
SEMICONDUCTORS
HEXINVERTE~S
FLAT PACKAGE
PIN' CONFIGURATION
(TOP VIEW)
DUAL-IN-LiNE PACI(AGE
PIN CONFIGURATION
(TOP VIEW)
IA(D
@Ii!
2i!0
@6A
2AG)
@6i!
@GND
Vcc8
3A0
@5i!
3i!0
0
5A
0
4 i!
4AG)
POSITIVE
LOGIC:
i! = A
POSITIVE
i!
LOGIC:
=A
schematic (each inverter)
INPUT
A
L-------4---~-GND
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Supply Voltage V CC:
Min
5404 Circuits .. ................... .........................
7404 Circuits .......
.......................... .................
Normalized Fan-Out From Each Output, N
Operating Free-Air Temperature Range. TA:
Nom Max
4.5
4.75
5
5
-55
0
25
25
...................
5404 Circuits ......... ......................
7404 Circuits .... ...................
3-23
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT5404,ITT7404
HEX INVERTERS
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
V in (1)
Logical 1 input voltage
required at input terminal to
ensure logical 0 level at
output
V
Vin(O)
Logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
V out (l )
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
'in(O)
'in(l)
2
2.4
Test Conditions 2
Unit
3.3
0.22
V
0.4
V
Logical 0 level input current
-1.6
mA
Logical 1 level input current
40
uA
1
mA
-20
-55
mA
-18
-55
= Min Ii = -12 mA
Vee = MIN. V in = 0.8 V.
Iload = -400 uA
Vee = MIN. V in = 2V.
Isink = 16 mA
Vee = MAX. Vin = 0.4 V
Vcc
----
'as
lee(O)
lee(1)
Short-circuit output current 3
Logical 0 level supply current
Logical 1 level supply current
SWITCHING CHARACTERISTICS. Vec
Parameter
1
2
3
= MAX. V in = 2.4 V
Vee = MAX. V in = 5.5 V
Vee = MAX I ITT5404
Vee
r ITT7404
18
33
mA
6
12
mA
= MAX. V in = 5 V
Vec = MAX. Vin = 0
Vee
= 5V. TA = 25°C. N = 10
Min
Typ
Max
Test Conditions
Unit
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL
= 15 pF. RL = 4000
tpdl
Propagation delay time to
logical 1 level
12
22
ns
CL
= 15 pF. RL = 4000
All typical values are at Vee = 5 V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3 - 24
ITT
----ITT5405, ITT7405
HEX INVERTERS (WITH OPEN-COLLECTOR OUTPUT)
SEMICONDUCTORS
HEX INVERTERS (WITH OPEN-COLLECTOR
OUTPUT)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@Ir
220
@SA
2A0
@S2
vccG)
@GND
@5r
3A0
0
0
32®
4A0
POSITIVE
LOGIC:
2
=A
POSITIVE
LOGIC
5A
4r
i! = A
schematic (each inverter)
4 kO
1.6 kQ
OUTPUT Y
INPUT
A
~------~--~~GND
NOTE: Component values are nominal.
Recommended Operating Conditions
Min
Supply Voltage V CC: 5405 Circuits ........................................................................ .
7405 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ............................................................. .
Operating Free-Air Temperature Range, TA: 5405 Circuits ............................... .
7405 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-25
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
I TT540 5, ITT7405
HEX INVERTERS (WITH OPEN-COLLECTOR OUTPUT)
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V in (l)
Logical 1 input voltage
required at input terminal to
ensure logical 0 (on) level at
output
Vin(O)
Logical 0 input voltage
required at input terminal to
ensure logical 1 (off) level at
output
Min
Typ'
Max
2
Unit
Test Conditions 2
V
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vee = Min Ii = -12 mA
10ut(1 )
Output reverse current
250
uA
Vee = MIN, Vin = 0.8 V,
V out (l) = 5.5 V
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
Vee = MIN, Vin = 2 V,
Isink = 16 mA
lin(O)
Logical 0 level input current
-1.6
mA
Vee = MAX, Vin = 0.4 V
lin(l )
Logical 1 level input current
40
uA
Vee = MAX, Vin = 2.4 V
1
mA
Vee = MAX, Vin = 5.5 V
,-
lee(O)
Logical 0 level supply current
18
33
mA
Vee = MAX, Vin = 5 V,
TA =25°e
lee(1)
Logical 1 level supply current
6
12
mA
Vee = MAX, Vin = 0
TA = 25°C
SWITCHING CHARACTERISTICS, Vee = 5V, TA = 25°C
Parameter
1
2
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL=15pF,R L =400SJ
tpd1
Propagation delay time to
logical 1 level
40
55
ns
eL = 15pF,R L =4kSJ
These typical values are at Vee = 5 V, TA = 25°e.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
3-26
ITT5406, ITT5416, ITT7406, ITT7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
""""
ITT- - - - SEMICONDUCTORS
HEX INVERTER BUFFERS/DRIVERS WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
FOR INTERFACING WITH HIGH-LEVEL CIRCUITS
OR FOR DRIVII\IG HIGH-CURRENT LOADS
DUAL-IN- LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IAQ)
@VCC
I;!@
@)SA
2A0
@SZ
2;!0
@5A
3A0
@5Z
3Z0
®4A
GND(2)
G)4Z
POSITIVE
LOGIC:
"
Converts TTL voltage levels to MOS
levels
lit
High sink-current capability
•
Input clamping diodes simplify system
design
"
Typical propagation delay time: 15 ns
"
Open-collector driver for indicator lamps
and relays
CII
Inputs fully compatible with most TTL
and DTL circuits
"
Typical power dissipation; 105 mW
POSITIVE
LOGIC
;!=A
schematic (each inverter)
.---..---_----0 vee
INPUT
A
2 kH
L----~-_+--~--+-~GND
Note: Component values shown are nominal.
3- 27
ITT5406, ITT5416, ITT7406, ITT7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
description
These monolithic TTL hex inverter buffers/drivers
feature. high-voltage open-collector outputs for
interfacing with high-level circuits (such as MOS or
Hi NIL). or for driving high-current loads (such as
lamps or relays). and are also characterized for use
as inverter buffers for driving TTL inputs. For increased fan-out. several inverters in a single
package may be paralleled. The ITT5406 and
ITT7406 have minimum breakdown voltages of 30
volts and the ITT541 6 and ITT7 416 have minimu m
breakdown voltages of 15 volts. The maximum sink
current is 30 milliamperes for the ITT5406 and
ITT5416. and 40 milliamperes for the ITT7406 and
ITT7416.
for operation over the full military temperature
range of -55°C to 125°C; the ITT7406 and
ITT7416 are characterized for operation from 0° C
to 70°C.
These circuits are completely compatible with most
TTL or DTL families. Inputs are diode-clamped to
minimize transmission-line effects which simplifies
design. Typical power dissipation is 150 milliwatts
and average propagation delay time is 15 nanoseconds. The ITT5406 and ITT5416 are characterized,
absolute maximum ratings over operating
free-air temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ........................... 7 V
Input voltage (see Note 1) ................................... 5.5 V
Output Voltage (see Notes 1 and 2):
ITT5406. ITT7406 Circuits ................................ 30 V
ITT541 6. ITT7 416 Circuits ................................ 1 5 V
Operating free-air temperature range:
ITT5406. ITT5416 Circuits ......... -55°C to 125°C
ITT7406. ITT7416 Circuits .................. O°C to 70°C
Storage temperature range ........... -'65°C to 150°C
Notes: 1. Voltage values are with respect to network
ground terminal.
2. This is the maximum voltage which should be
applied to any output when it is in the off
state.
recommended operating conditions
Supply voltage Vee
Output voltage. Vo H
I
J
ITT5406. ITT5416
Min
Nom
Max
ITT7406.ITT7416
Min
Nom Max
4.5
4.75
5
ITT5406.ITT7406
ITT541 6. ITT7416
Low-level output current. IOL
Operating free-air temperature range. TA
-55
3- 28
25
5.5
Unit
5.25
V
30
15
30
15
V
30
40
mA
70
°e
125
0
5
25
ITT5406, ITT5416, ITT7406, ITT7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
Min
Typ'
Max
2
Unit
Test Conditions 2
V
V IL
Low-level input voltage
0.8
V
VI
Input Clamp Voltage
-1.5
V
IOH
High-level output current
250
uA
VOL
Low-level output voltage
0.7
V
0.4
= MIN Ii = -12 rnA
Vee = MIN. VI = 0.8 V.
V OH = MAX
Vee = MIN. VI = 2 V.
IOL = MAX
Vee
Vee=MIN'VI=2V.
IOL = 16mA
= 2.4 V
High-level input current (each
input)
40
uA
Vee = MAX. VI
1
rnA
Vee = MAX. VI = 5.5 V
IlL
Low-level input current (each
input)
-1.6
mA
Vee = MAX. VI
leCH
Supply current. high-level output
30
42
mA
VCC = MAX. VI
ICCL
Supply current. low-level output
27
38
mA
Vce =
IIH
= 0.4 V
=0
MAX. VI = 5V
, All typicalvalues are atV cc = 5 V. TA = 25°C.
2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e
Parameter
Min
Typ
Max
Unit
Test Conditions
= 15 pF. RL = 110.0.
tpLH
Propagation delay time.
low-to-high-Ieveloutput
10
15
ns
CL
tpHL
Propagation delay time.
. high-to-Iow-Ievel output
15
23
ns
CL = 15 pF. RL
3-29
= 110.0.
_
I
ITT5407, ITT541. 7, ITT7407, ITT7417
HEX BUFFERS/DRIVERS
W_IT_H_O_P_E.N_-_C_O_l_lE_C_T_O_R_H_I_G_H_-V_O_L_TA_G_E_O_U_T_PU_T_S
mm
..L..L. ___
SEMICONDUCTORS
HEX BUFFERS/DRIVERS. WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
•
Converts TTL voltage levels to MOS
levels
•
High sink-current capability
•
Input clamping diodes simplify system
design
•
Typical propagation delay time: 14 ns
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
VCC
Ii!
6A
2A
6i!
5A
e Open-collector driver for indicator lamps
and relays
•
Inputs fully compatible with most TTL
and OTL circuits
•
Typical power dissipation: 145 mW
5i!
POSITIVE
i! = A
LOGIC:
absolute maximum ratings over operating
free-airtempeniture range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Output Voltage (see Notes 1 and 2):
ITT5407. ITT7407 Circuits ................................. 30V
ITT5417.ITT7417 Circuits ................................. 15V
Operating free-air temperature range:
ITT5407.ITT5417 Circuits .:....... -55°C to 125°C
ITT7407.ITT7417 Circuits .................. ooC to. 70°C
Storage temperatu.re range ........... -65°C to 150°C
Notes:
schematic (each buffer/driver)
.-----~---.----------ovcc
4kU
3kU
OUTPUT
i!
2kn
INPUT
A
1. Voltage values are with respect to network
ground terminal.
2. This is the maximum voltage which should
be applied to any output when it is in the
off state.
2 kU
L -__
~
____
~
__
~
______
~-oGNO
Note: Component values shown are n!lminal.
3-30
ITT5407, ITT5417, ITT7407, 11T7417
HEX BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
description
These monolithic TTL hex buffers/drivers feature
high-voltage open-collector outputs for interf acing
with high-level circuits (such as MOS or Hi NIL).
or for driving high-current loads (such as lamps or
relays). and are also characterized for use as buffers
for driving TTL inputs. For increased fan-out.
several buffers in a single package may be paralleled. The ITT5407 and ITT7407 have minimum
breakdown voltages of 30 volts and the ITT5417
and ITT7417 have minimum breakdown· voltages
of 15 volts. The maximum sink current is 30
milliamperes for the ITT5407 and ITT5417. and 40
milliamperes for the ITT7407 and ITT7 417.
These circuits are completely compatible with most
TTL or DTL families. Inputs are diode-clamped to
minimize transmission-line effects which simplifies
design. Typical power dissipation is 145 milliwatts
and average propagation delay time is 14 nanoseconds. The ITT5407 and ITT541.7 are characte rized
for operation over the full military temperature
range of -55°C to 125°C; the ITT7407 and ITT7417 are characterized for operation from O°C to
70°C.
recommended operating conditions
Min Nom Max
Supply voltage Vee
.4.5
Output voltage. V OH
5
IITT5407. ITT7407
IITT5417.ITT7417
5.5
Min Nom Max
4.75
5
30
15
Low-level output current. IOL
30
-55
Operating free-air temperature range. TA
_.
25
125
0
25
Unit
5.25
V
30
15
V
40
rnA
70
°e
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
Mill
Typ'
Max
2
Unit
Test Conditions 2
V
V IL
Low-level input voltage
0.8
V
VI
Input Clamp Voltage
-1.5
V
Vce
10H
High-level output current
250
uA
Vee ~ MIN. VI
MAX
V OH
VOL
Low-level output voltage
0.7
V
0.4
High-level input current (each
input)
40
1
mA
IlL
Low-level input current (each input)
-1.6
mA
leCH
Supply current. high-level output
29
41
mA
leeL
Supply current. low-level output
21
30
mA
IIH
uA
= MIN Ii = -12 rnA
= 2V.
=
Vee = MIN. VI = O.BV
10L = MAX
Vee = MIN. VI = O.BV
IPL = 16 rnA
Vee = MAX. VI = 2.4V
Vee = MAX. VI = 5.5V
Vee = MAX. VI = 0.4V
Vee = MAX. VI = 5V
Vee = MAX. VI = (]II
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e
Parameter
Min
Typ
Max
Test COl\ditions
Unit
tpLH
Propagation delay time.
low-to-high-Ieveloutput
6
10
ns
eL
= 15pF.R L = 1100
tpHL
Propagation delay time.
high-to-Iow-Ieveloutput
20
30
ns
eL
= 15pF.R L = 1100
, All typi!'al values are atV ec = 5V. TA = 25°C.
.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
2
3-31
-
ITT5408, ITT5409, ITT7408, ITT7409
-
ITT- - - - QUADRU PLE 2-IN PUT POSITIVE AND GATES
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE AND GATES
schematics (each gate)
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
ITT5408/ITT7408
VCC
48
4A
A
42:
28
38
ITT5409/ITT7409
POSITIVE
2kU
LOGIC:
Z = A8
The ITT5408 and ITT5409 are characterized for operation over the full military temperature range of
-55°C to 125°C; the ITT7408 and ITT7409 are
characterized for operation from O°C to 70°C.
1.6kU
z
1 kU
Component values shown are nominal.
description
These Series 54174 TTL gates provide the system
designer with direct implementation of the positiile
AND or negative OR functions.
The ITT5408/1TT7408, with totem-pole outputs,
drives 10 normalized Series 54174 loads at the low
output level and 20 loads at the high output level.
The ITT5409/1TI7409, with open-collector output,
provides additional logic flexibility, as the outputs
may be wire-AN D connected to extend the AN D
function. The ITI5409/1TT7409 will sink sufficient
current to drive 10 normalized Series 54174 loads
at the low output level.
Choice ofTotem-Pole Outputs (lTI5408/ITT7408)
or Open~Co!lector Outputs (lTI5409/ITT7409)
absolute maximu m ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
I nput voltage (see Note 1) .................................... 5.5V
Interemittervoltage (see Note 2) ........................ 5.5V
Output voltage (see Notes 1 and 3)
(lTT5409/ITI7409) ............................................. 5.5V
Operating free-air temperature range;
ITI5408/1TT5409 ........................ - 55°C to 125°C
ITT7408/1TT7409 ................................. ooC to 70°C
Storage temperature range ........... -65°C to 150°C
Notes:
3 - 32
1. Voltage values, except interemitter voltage,
are with respect to network ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor.
3. This is the maximum voltage which should
be applied to any output when it is in the
off state.
ITT5408, ITT5409, ITT7408, ITT7409
QUADRUPLE 2-INPUT POSITIVE AND GATES
recommended operating conditions
Supply voltage Vee
Min
Nom
Max
lII!in
Nom
Max
Unit
4.5
5
5.5
4.75
5
5.25
V
Normalized fan-out from each output, N
10
-55
Operating free-air temperature range. TA
25
125
10
0
25
70
°e
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT540S.ITT740S
V IH
Typl
Min
Parameter
High-level input voltage
Max
2
Unit
Test Conditions 2
V
V IL
Low-level input voltage
O.S
V
V1
Input elamp Voltage
-1.5
V
Vee = MIN. Ii = -12 mA
VOH
High-level output voltage
V
Vee = MIN. V IH = 2V.
10H = -BOO uA
VOL
Low-level output voltage
0.4
V
Vee = MIN. VII:' = O.BV.
IOL = 16 mA
IIH
High-level input current (each
input)
40
uA
Vee = MAX. VI = 2.4V
1
mA
Vee = MAX. VI = 5.5V
IlL
Low-level input current (each
input)
-1.6
mA
Vee = MAX. VI = O.4V
lOS
Short-circuit output current
-20
-55
mA
Vee = MAX ITT540B
-lB
-55
2.4
3
ITT740B
leeH
Supply current. high-level output
11
21
mA
Vee = MAX. VI = 5V
leeL
Supply current. low-level output
20
33
mA
Vee = MAX. VI = OV
SWITCHING CHARACTERISTICS.
Vee =5v. TA = 25°e. N = 10
ITT540S. ITT740S
Parameter
Min
Typ
Max
Unit
Test Conditions
tpLH
Propagation delay time.
low-to-high-Ieveloutput
17.5
27
III
eL = 15pF.R L = 40011.
tpHL
Propagation delay time.
high-to-Iow-Ievel,?utput
12
19
III
eL = 15 pF. RL = 40011.
3-33
ITT5408,ITT5409, ITT7408, ITT7409
QUADRU PLE 2-IN PUT POSITIVE AND GATES
ElECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT5409, ITT7409
Parameter
V IH
High-level input voltage
Min
Typ'
Max
2
Unit
Test Conditions 2
V
V il
low-level input voltage
0.8
V
V1
Input clamp voltage
-1.5
V
Vee =MIN,l i = -12 mA
IOH
High-level output current
250
uA
Vee = MIN. V IH = 2V.
VOH = 5.5V
VOL
low-level output voltage
0.4
V
Vee = MIN, V il = 0.8V.
IOL = 16mA
IIH
High-level input current (each
input)
40
uA
Vee = MAX, VI = 2.4V
1
mA
Vee = MAX. VI = 5.5V
III
low-level input current (each
input)
-1.6
mA
Vee = MAX, VI = 0.4V
ICCH
Supply current. high-level output
11
21
mA
Vee = MAX, VI = 5V
ICCl
Supply current. low-level output
20
33
mA
Vee = MAX, VI = OV
SWITCH!NG CHARACTERISTICS, Vee
= 5V, TA = 25°e, N = 10
ITT5409, ITT7409
Parameter
Min
Typ
Max
Unit
Test Conditions
tplH
Propagation delay time,
low-to-high-Ieveloutput
21
32
ns
eL = 15 pF, RL = 400n
tpHl
Propagation delay time.
high-to-Iow-Ieveloutput
16
24
ns
el = 15 pF, RL = 400n
, All typical values at V CC = 5V, TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
, Not more than one output should be shorted at a time.
2
3 - 34
_I
mm
ITT5410, ITT7410
.L.L ______T_R_IP_L_E_3_-_1N_P_U_T_P_O_S_IT_I_V_E_N_A_N_D_G_A_T_E,""",S
SEMICONDUCTORS
TRIPLE 3-INPUT POSITIVE NAND GATES
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL- IN- LINE PACKAGE
PIN CONFIGURATION
(lOP VIEW)
IA(D
@IC
0
Ir0
@3r
@3C
18
vccG
@GND
2i!0
2AG
0
@)38
®3A
0
2C
28
POSITIVE
LOGIC:
Z =ABC
POSITIVE
LOGIC
schematic (each gate)
OUTPUT ;!
~~------~~--~~GND
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Min
Supply Voltage V CC: 5410 Circuits .........................................................................
741 0 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ..............................................................
Operating Free-Air Temperature Range. TA : 5410 Circuits ............................... .
7410 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-35
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT541 0, ITT741 0
TRIPLE 3-INPUT POSITIVE NAND GATES
E LE CTR ICA L CHARACTE R ISTI CS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
Vin (l)
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at,output
Vin(O)
Logical'O input voltage
required atany input
terminal to ensure logical 1
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vcc = Min Ii = -12 mA
V out (l )
Logical 1 output voltage
V
Vee = MIN. Vin= 0.8 V.
Iload = -400 uA
Vout(O)
Logical 0 output voitage
0.4
V
Vee = MIN. Vin = 2V.
Isink = 16 mA
lin(O)
Logical 0 level input current
(each input)
-1.6
mA
Vee = MAX. Vin = 0.4 V
lin(1)
Logical 1 level input current
(each input)
40
uA
1
mA
Vee = MAX. V in = 2.4 V
Vee = MAX. Vin = 5.5 V
-20
-55
rnA
Vee = 5.5V
-18
-55
lOS
Short-circuit output current 3
2
2.4
V
3.3
0.22
ITT541 0
ITT741 0
lee(O)
Logical 0 level supply current
9
16.5
mA
Vee = MAX. Vin = 5 V
lee(1)
Logical 1 level supply current
3
6
mA
Vee = MAX. Vin = 0
SWITCHING CHARACTERISTics. Vee = 5V. TA = 25°C. N == 10
Parameter
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
7
15
ns
eL = 15pF.R L =400Q
tpdl
Propagation delay time to
logical 1 level
11
22
ns
eL =.15pF.R L =400Q
1
2
3
All typical values are at V cc = 5 V. TA = 25° C.
.
..
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3-36
ITT
-----
ITT5411,ITT7411
TRIPLE 3-INPUT POSITIVE AND GATES
SEMICONDUCTORS
TRIPLE 3-INPUT POSITIVE AND GATES
description
These Series 54174 TTL gates provide the system
designer with direct implementation of the positive
AND or negative OR functions.
DUAL- IN - LINE PACKAGE
PIN CONFIGURATI.oN
(TOP VIEW)
The ITT5411 IITT7411. with totem-pole outputs.
drives 10 normalized Series 54174 loads at the low
output level and 20 loads at the high output level.
absolute m aximu m ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) ........................ 5.5V
Operating free-air temperature range:
ITT5411/1TT5411 ........................ -55°Cto 125°C
ITT7411 IITT7411 ................................. O°Cto 70°C
Storage temperature range ........... - 65°C to 150°C
Notes:
1. Voltage values. except interemitter voltage.
are with respect to network ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor.
schematic
POSITIVE
LOGIC:
l = ABC
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@IC
IB0
@)3r
IrG)
@3C
@GND
VCcG
210
@3B
2A0
®3A
2B0
.®2C
i!
POSITIVE'
3 - 37
LOGIC
l=ABC
ITT5411.ITT7411
TRIPLE 3-INPUT POSITIVE AND GATES
recommended operating conditions
Min
4.5
Supply voltage VCC
ITT5411
Nom
Max
5
Normalized fan· out from each output. N
5.5
Min
4.75
ITT7411
Nom
5
10
-55
Operating free-air temperature range. TA
25
125
Max
Unit!
5.25
V
10
0
25
70
°c
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
VIH
High-level input voltage
V il
low-level input voltage
0.8
V
V,
Input Clamp Voltage
-1.5
V
VCC = MIN. Ii = -12 mA
VOH
High-level output voltage
..
V
VCC = MIN. VIH = 2V.
10H = -800uA
VOL
low-Ievei output voltage
V
VCC = MIN. VII: = 0.8V.
10l = 16mA
40
uA
VCC = MAX. VI = 2.4V
1
mA
VCC = MAX. VI = 5·.5V
-1.6
mA
VCC = MAX. V, = 0.4V
-20
-55
mA
VCC = MAX ITT5411
-18
-55
V
2.4
0.4
0
IIH
2
I
High-level input current (each
input)
I
III
low-level input current (each
input)
I
lOS
Short-circuit output1current 3
0
ITT7411
leCH
Supply current. hig h-Ievel output
11
21
mA
VCC = MAX. VI = 5V
leCl
Supply current. low-level output
20
33
mA
VCC = MAX. VI = OV
SWITCHING CHARACTERISTICS, Vee = 5V. TA = 25°e. N = 10
Parameter
Min
Typ
Max
Unit
Test Conditions
tplH
Propagation delay time.
low-to-high'level output
17.5
27
ns
Cl = 15 pF. Rl = 4oon.
tpHl
Propagation delay'time.
high-to-low-lev61 output
12
19
ns
Cl = 15 pF. Rl = 400n
3-38
ITT
a::::I:D
ITT5412,ITT1412
TRIPLE 3-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
=====~~~
SEMICONDUCTORS
TRIPLE 3-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
DUAL-IN-LiNE PACI~AGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
schematic (each gate)
1.6 kO
.....
OUTFUT i!
INPUTS {
A
C
L6-<1>-----+---o GND
NOTE: Component values shown are nominal.
POSITIVE LOGIC:
recommended operating conditions
Min
~=A8C
Nom Max
5412 Circuits .........................................................................
7412 Circuits .........................................................................
4.5
4.75
5
5
Normalized Fan-Out From Each Output, N ............................................................. .
Operating Free-Air Temperature Range, T A: 5412 Circuits ............................... .
7412 Circuits ............................... .
-55
0
25
25
Supply Voltage VCC:
3-39
5.5
5.25
10
125
70
Unit
V
V
°C
°c
ITT5412, ITT7412
TRIPLE 3-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
2
Unit
Test Conditions 2
Vin (1)
Logical 1 input voltage required
at both input terminals to ensure
logical 0 (on) level at output
V
Vin(O)
Logical 0 input voltage required
at either input terminal to ensure
logical 1 (off) level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
lout( 1)
Output reverse current
250
J.1A
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
linlO)
Logical 0 level input current
(each input)
-1.6
mA
= Min Ii = -12 mA
Vce = MIN. Vin(O) = 0.8V.
V out (1) = 5.5V
Vee = MIN. Vin = 2V.
Isink = 16 rnA
VCC = MAX. Vin = O.4V
linl1 )
Logical 1 level input current
(each input)
40
J.1A
Vce
1
mA
Vce
leelO)
Logical 0 level supply current
g
16.5
mA
leC(1 )
Logical 1 level supply current
3
6
mA
VCC
= MAX. Vin = 2.4V
= MAX. V in = 5.5V
Vce = MAX. Vin = 5V
Vce = MAX. V in = 0
, All typical values are at Vec = 5V. TA = 25° C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
2
SWITCHING CHARACTER ISTICS, Vee
Parameter
tpdO
Propagation delay time to logical
= 5V. TA = 25°e
Min
Typ
Max
Unit
Test Conditions
8
15
ns
CL
= 15pF. RL = 400 n
35
45
ns
CL
= 15 pF. RL = 4 kn
o level
tpd1
Propagation delay time to logical
1 level
3-40
ITT5413,ITT7413
- ITT - - - - DUAL NAND SCHMITT TRIGGERS
SEMICONDUCTORS
DUAL NAND SCHMITT TRIGGERS
• Operation from Very Slow Edges
DUAL-IN-L1NE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
• Temperature-Compensated Threshold
• Temperature- Compensated Hysteresis.
Typically O.SV
• High Noise Immunity
IA
VCC
2D
The ITT5413 and ITT7413 dual Schmitt triggers
consist of two identical Schmitt-trigger circuits in
monolithic integrated circuit form. Logically. each
circuit functions as a four-input NAN D gate. but because of the Schmitt action. the gate has different
input threshold levels for positive- and negativegoing signals. The hysteresis. or backlash. which is
the difference between the two threshold levels. is
typically 800 mV.
An important design feature is the built-in temperature compensation which ensures very high
stability of the threshold levels and the hysteresis
over a very wide temperature range. Typically. the
hysteresis changes by 3% over the temperature
range of - 55°C to 125°C and the upper threshold
changes by 1 % over the same range. The
ITT5413/ITT7413 can be triggered from the slowest of input ramps and still give clean. jitter-free
output signals. It can also be triggered from straight
d-c levels.
2C
NC
2B
POSITIVE LOGIC: 'to ABeD
NC- NO INTERNAL CONNECTION
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE
THE SAME FOR ALL PACKAGES.
absolute maximum ratings over operating
free-air temperature range (unless otherwise noted).
These circuits are fully compatible with most other
TTL. DTL. or M SI circuits. The ITT5413 is cha racterized for operation over the full military temperature range of -55°C to 125°C; the ITT7413
is characterized for operation from O°C to 70°C.
Supply voltage V CC (see Note) .............. , ................7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) ........................ 5.5V
Operating free-air temperature range:
ITT5413 Circuits ........................... -55°C to 125°C
ITT7413 Circuits ........................... -65°C to 150°C
Notes: 1. Voltage values. except interemitter voltage.
are with respect to network ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor.
ITT5413
ITT7413
MIN NOM MAX MIN NOM MAX
recommended operating conditions
Supply voltage V CC
Fan-out from each output. N
4.5
I
5
-55
Operating free-air temperature range. TA
Maximum input rise and fall times
5.5
0
125
No restriction
3-41
4.75
5
20
10
High logic level
Low logic level
5.25
UNIT
V
20
10
0
25
70
No restriction
°C
ITT5413,ITT7413
DUAL NAND SCHMITT TRIGGERS
ELECTRICAL CHARACTERISTICS over recommended operat.ing free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit·
Test Conditions 2
VT +
Positive-going threshold voltage
1.5
1.7
2
V
Vee = 5V
VT -
Negative-going threshold
voltage
0.6
0.9
1.1
V
Vee = 5V
VT +
-V T -
Hysteresis
0.4
0:8
V
Vee - 5V
VI
I nput clamp voltage
V
Vee = MIN.I I = -12mA
VOH
High-level output voltage
V
Vee = MIN. VI = 0.6V
IOH =. -800 uA
VOL
Low-level output voltage
0.22
V
Vee = MIN. VI = 2V.
IOL = 16 mA
IT+
Input current at positive-going
threshold
-0.65
mA
Vee = 5V. VI = VT +
IT -
Input current at negative-going
threshold
-0.85
mA
Vee = 5V. VI = V T -
II
Input current at maximum input
voltage
1
mA
Vee = MAX. VI = 5.5V
IIH
High-level input current
40
IlL
Low-level input current
lOS
Short-circuit output current
leeH
Supply current. high-level output
leeL
Supply current. low- level output
-1.5
2.4
3.3
-1
3
0.4
).lA
Vee = MAX. VI = 2.4V
-1.6
mA
Vee = MAX. VI = 0.4V
-55
mA
Vee = MAX
14
23
mA
Vee = MAX. VI = 0
20
32
mA
Vee = MAX. VI = 4.5V
-18
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N =.10
Parameter
Min
Typ
Max
Unit
Test Conditions
tpLH
Propagation delay time.
low-to-high-Ieveloutput
18
27
ns
eL = 15pF.R L =400Q
tpHL
Propagation delay time.
high-to-Iow-Ieveloutput
15
22
ns
eL = 15pF.R L =400Q
, All typical values are at Vee = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
2
3-42
ITT
----ITT5420, ITT7420
DUAL 4-INPUT POSITIVE NAND GATES
SEMICONDUCTORS
i
DUAL 4-INPUT POSITIVE NAND GATES
OUAL-IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@IO
Il0
@IC
VCC
NCG)
'--~-+-®
vccG
IB
2C
@GNO
Nc0
@2l
2A0
L..----1_® 20
0
2B0
POSITIVE
20
LOGIC:
r=
2C
ABci5'
schematic (each gate)
POSITIVE LOGIC: -t = ABCO
~---------~~------1--4Vcc
4kU
1.6kll
1300
OUTPUT
Z
GND
Component values shown are nominal.
NC-No internal connection.
Recommended Operating Ccmdition.s
Min
Supply Voltage VCC: 5420 Circuits ...................................'..................................... .
7420 Circuits ...................................:..................................... .
Normalized Fan-Out From Each Output. N ........................:..................................... .
Operating Free-Air Temperature Range. TA: 5420 Circ~its ............................... .
7420 Circuits ............................... .
4.5
4.75
5
5
-55
0
25
25
3-43
I
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITT5420, ITT7420
DUAL 4-INPUT POSITIVE NAND GATES
ELECTR ICAL CHARACTER ISTICS over recommended operating free-air temperature range
(unless othelWise noted)
Parameter
Min
Typ'
Max
Vin(l)
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
08
V
V1
Inputelamp Voltage
-1,5
V
Vout (l)
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
'in(O)
'in(l)
lOS
2
Unit
Test Conditions 2
V
0.4
V
Logical 0 level input current
(each input)
-1.6
mA
= Min 'i = -12 mA
Vee = MIN. Vin = 0.8 V.
"oad = -400 uA
Vee = MIN. Vin = 2 V.
'sink = 16 mA
Vee = 1'v1AX. Vin = 0.4 V
Logical 1 level input current
(each input)
40
JlA
Vee
1
mA
-20
-55
mA
-18
-55
2.4
3.3
V
0.22
Short-circuit output current 3
Logical 0 level supply current
6
11
mA
'ee(1)
Logical 1 level supply current
2
4
mA
Parameter
= 5V. TA = 25
Min
Typ
Q
e. N
= MAX. Vin = 2.4 V
Vee = MAX. V in = 5.5 V
Vee = MAX 'ITT5420
ITT7420
'ee(O)
SWITCHING CHARACTERISTICS. Vee
Vcc
= MAX. Vin = 5 V
Vee = MAX. Vin = 0
Vee
= 10
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL
= 15 pF. RL = 400Q
tpd1
Propagation delay time to
logical 1 level
12
22
ns
eL
= 15 pF. RL = 400Q
1
2
3
=
=
All typical values are at Vee
5 V. TA
25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3-44
ITT
----ITT5421,ITT7421
DUAL 4-INPUT POSITIVE AND GATES
SEMICONDUCTORS
DUAL·4-INPUT POSITIVE AND GATES
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN-LiNE PACKAGE
PIN CON FIGURATION
(TOP
VIEW)
BID
VCC
IB
20
NC
2C
@) IC
'--...J--t-@ IB
rilc
10
2B
I~
2A
itccG
Nc0
@2i!
2A®
'----1-0 20
@GNO
2B0
POSITIVE
LOGIC:
. i!" ABCD
POSITIVE
0
LOGIC:
2C
i! =ABCD
Circuit schematic
vee
This Series 54174 TTL gate provides the system designer with direct implementation of the positive
AND or negative OR functions .
.The ITI5421 IITI7 421 with totem-pole outputs,
drives 10 normalized Series 54174 loads at the low
output level and 20 loads at the high output level.
The ITI 5421 is characterized for operation over the
full military temperature r;~nge of -55°C to 125°C;
the ITT7421 is characterized for operation from
OOCto 70°C.
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) .................. ,..... 5.5V
Operating free-air temperature range:
ITI5421 .......................................... -55°C to .125°C
ITI7421 ................................................... OoC to 70°C
Storage temperature range ........... - 65°C to 150°C
COMPONENT VALUES SHOWN ARE NOMINAL
Notes:
3-45
1. Voltage values. except interemitter voltage.
are with respect to network ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor.
ITI5421, ITT7421
DUAL 4-INPUT POSITIVE AND GATES
recommended operating conditions
Min
Nom
Max
Min
Nom
Max
Unit
4.5
5
5.5
4.75
5
5.25
V
-55
25
125
Supply voltage vee
Normalized fan-out from each output. N
10
Operating wee-air temperature range. TA
ELECTRICAl,. CHARACTERISTICS over recommended
(unless otherwise noted)
op~rating
10
0
25
70
De
free-air temperature range
ITT542l. ITT7421
Parameter
VIH
Min
High-level input voltage
Typ'
Max
2
Test Conditions 2
Unit
V
V IL
Low-level input voltage
0.8
V
Vl
Input elamp Voltage
-1.5
V
V OH
High-level output voltage
VOL
Low-level output voltage
0.4
V
= Min Ii = -12.mA
Vee = MIN. V IH = 2V.
IOH = -800 uA.
Vee = MIN. V IL = O.SV.
IIH
High-level input current (each
input)
40
uA
Vee
1
mA
Low-level input current (each
input)
-1.6
mA
= MAX. VI = 2.4V
Vee = MAX. VI = 5.5V
Vee = MAX. VI = 0.4V
-20
-55
rnA
Vee
-18
-55
2.4
V
Vee
IOL':' l6mA
IlL
lOS
,
Short-circuit outpUt current"
= MAX
1TT5421
n:T742l
leeH
Supply current. high-level output
11
21
mA
leeL
Supply current. low-level output
20
33
mA
= MAX. VI = 5V
Vee = MAX. VI = 0
25°e; N
= 10
Unit
Test Conditions
SWITCHING CHARACTERISTICS.
Vee = 5V. TA
=
Vee
ITT542l. 1TT7421
Parameter
Min
Typ
Max
= 15 pF. RL = 400 g
tpLH
Propagation delay time.
low-to-high-Ievel output
17.5
27
ns
eL
tpHL
Propagation delay time.
hig h-to-Iow-Ievel output
12
19
ns
eL = 15pF.R L
= 400g
.
, All typical values at Vee = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
" Not more than one output should be shorted at a time.
2
3-46
=-
ITm
In-5425, ITT1ij·25
-IL~=====-===D=U==A=L=4=-I=N=P=U=T=N=O=R=G==A=TE=S=W==IT=H==S=~R==.O~!
SEMICONDUCTORS
DUAL 4-INPUT NOR GATES
W~TH
schematic (each gate)
STROBE
DUAL -IN-LINE PACKAGE
AND FLAT PACI(AGE
PIN CONFIGURATION
(TOP VIEW)l
vcco----..-.---.......---,
---"r
A ___
IA
VCC
IB
2D
STROBE
IG
INPUTS
2C
OUTPUT
c ___-+"r
i!!
D ____-+''f
IC
STROBE
ID
28
It
2A
2G
GND
G _ _ _-+-_jq.,
POSITIVE LOGIC: t = G(A+B+C+D)
800H
-+_--'
G N O o - - -_ _ _ _
1
Pin assignments for these circuits are the same for
all packages.
Notes: A, Component values shown are nominal.
V -VCCbus
absolute maximum ratings over operating freeair temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) ....................... 5.5V
Operating free-air temperature range:
ITT5425 .......................................... -55°Cto 125°C
ITT7425 ................................................... aoc to 7aoC
Storage temperature range ........... - 65°C to 15aoC
logic and functional block diagram (each gate)
Notes:
Ao----i
1.. Voltage val.ues. except interemitter voltage.
are with respect to network ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor.
TRUTH TABLE
Bo--+--i
Output
Inputs
OUTPUT
if
Co--+--i
Do--+---1
Go---4---1
H
A
B
C
0
G
V
H
X
X
X
L
X
X
H
X
X
L
X
X
X
H
X
X
X
X
H
H
H
H
L
L
X
X
X
L
L
L
L
L
H
H
H
= hi!Jh level, L = low level. X = irrelevant.
3-47
ITT5425, ITT7425
DUAL 4-INPUT NOR GATES WITH STROBE
recommended operating conditions
Supply voltage VCC
Normalized fan-out from each output. N
ITT5423,ITT5425
Min
Nom
Max
ITT7423, ITT7 425
Min
Nom Max
4.5
4.75
5
5.5
5
High logic level
20
20
Low logic level
10
10
-55
Operating free-air temperature range, T A
25
125
0
Unit
5.25
25
70
V
°c
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
V ,H
High-level input voltage
V ,l
low-level input voltage
0.8
V
V,
I nput clamp voltage
-1.5
V
Vec = MIN. " = -12mA
VOH
High-level output voltage
V
VCC = MIN. V ,l = 0.8V.
'OH = -800uA
Val
low-level output voltage
V
VCC =MIN. V ,H = 2V.
2
2.4
V
3.3
0.22
0.4
'Ol = 16mA
Input current at maximum input
voltage
"
"H
',L
1
mA
v.CC = MAX. V, = 5.5V
uA
VCC = MAX. V, = 2.4V
mA
VCC = MAX. V, = 0.4V
-55
mA
VCC = MAX
High-level input
current
data inputs
40
strobe inputs
160
low-level input
data inputs
-1.6
strobe inputs
-6.4
current
-20
'OS
Short-circuit output currents
'CCH
Supply current. high-level output
8
16
mA
VCC = MAX.
All inputs at OV
'CCl
Supply current. low-level output
10
19
mA
VCC = MAX.
All inputs at 5V
3
.' All typical values are at V CC = 5V. TA = 25°C.
2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
3-48
ITT5426, ITT7426
QUADRUPLE 2-INPUT HIGH-VOLTAGE
INTERFACE NAND GATES
ITT
----SEMICONDUCTORS
QUADRUPLE 2-INPUT HIGH-VOLTAGE
INTERFACE NAND GATES
These open-collector NAND gates feature high output voltage ratings for interfacing with lowthreshold-voltage M OS logic circuits or other 12volt systems. Although the output is rated to withstand 15 volts, the V CC terminal is connected to the
standard 5-volt source. The output transistor will
sink 16 milliamperes while maintaining a low-level
output voltage of 0.4 volt maximum thus providing
a high-fan-out driver with the nominal power dissipation of standard Series 54174 gates.
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
vec
IA
49
4A
4l
The ITT5426 is characterized for operation over the
full military temperature range of -55°C to
125°C; the ITT7426 is characterized for operation
from O°C to 70°C.
39
schematic (each gate)
POSITIVE
4kn
1.6 kn
INPUTS
LOGIC
l=AB
absolute maximum ratings over operating
free-air temperature range (unless otherwise noted)
..,----0 OUTPUT"
an
~~-----+--4---~GND
Note: Component values shown are nominal.
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .......... ,......................... 5.5V
Output voltage (see Notes 1 and 2): ................... 15V
Operating free-air temperature range:
ITT5426 Circuits ........................... -55°C to 125°C
ITT7426 Circuits .................................... O°C to 70° C
Storage temperature range ........... -65°C to 150°C
Notes:
1. Voltage values are with respect to network
ground terminal.
2. This is the maximum voltage which should
be applied to any output when it is in the
off state.
recommended operating conditions
Supply voltage
ITT5426
Min Nom Max
ITT7426
Min Nom Max
4.5
4.75
5
5.5
5
5.25
Unit
V
Output voltage, V OH
15
15
V
Low-level output current. 10L
16
16
mA
70
°C
-55
Operating free-air temperature range, T A
3-49
25
125
a
25
ITT5426, ITT7426
QUADRUPLE 2-INPUT HIGH-VOLTAGE
INTERFACE NAND GATES
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Min
Parameter
V IH
High-level input voltage
Typ'
Max
2
Unit
Test Conditions 2
V
..
V IL
Low-level input voltage
0.8
V
-1.5
V
VCC
V
VCC = MIN. V IL
IOH = 1 mA
= MIN Ii = -12mA
= O.BY.
VI
I nput Clamp Voltage
VOH
High-level output voltage
10H
High-level output current
50
uA
VCC = MIN. V IL
V OH
12V
= O.BY.
VOL
Low-level output voltage
0.4
V
VCC = MIN. V IH
IOL = 16mA
= 2V.
IIH
High-level input current (each
input)
40
uA
VCC
1
mA
VCC
IlL
Low-level input current (each
input)
-1.6
mA
= MAX. VI = 2.4V
= MAX. VI = 5.5V
VCC = MAX. VI = 0.4V
ICCH
Supply current. high-level output
4
8
mA
VCC
ICCL
Supply current. low-level output
12
22
mA
15
=
= MAX. VI = 0
VCC = MAX. VI = 5V
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e
Parameter
Min
Typ
Max
Unit
Test Conditions
tpLH
Propagation delay time.
low-to-high-Ieveloutput
16
24
ns
CL
= 15 pF. RL = 1kfl
tpHL
Propagation delay time.
high-to-Iow:leveloutput
11
17
ns
CL
= 15pF.R L = 1kn
, All typical values are at V CC = 5V. TA = 25°C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
2
3-50
ITT
-----
ITT5428, ITT7428, ITT5433, ITT7433
QUADRUPLE 2-INPUT POSITIVE NOR BUFFERS
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NOR
BUFFERS
Choice of Totem Pole Outputs (tTT5428/ITT7428)
or Open Col\ector Outputs (tTT5433/ITT7433)
OUAL-IN-L1NE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage Vee (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Output voltage of
ITT5433. ITT7433 (Note 2) ............................... 5.5V
Operating free-air temperature range:
ITT5428. ITT5433 ........................ -55°C to 125°C
ITT7428. ITT7433 ................................. O°C to 70°C
Storage temperature range ........... -65°C to 150°C
Vce
4~
48
4A
3~
Notes:
POSITIVE LOGIC:
r
1. Voltage values, except interemitter voltage,
are with respect to network ground term ina!.
2. This is the maximum voltage which should
be applied to any output when it is in the
off state.
= A+8
schematics (each gate)
ITT5433/ITT7433
ITT5428/ITT7428
vee
A o--+--.r
A o---I---.r
B
B
3-51
ITT5428, ITT7428, ITT5433, ITT7433
QUADRtJPLE 2-INPUT POSITIVE NOR BUFFERS
recommended operating conditions
Min
ITT5428
Nom
Max
4.5
Supply voltage V CC
5
Normalized fan-out from each output. N
5.5
Min
4.75
ITT7428
Nom Max
5
30
-55
Operating free-air temperature range. TA
25
125
Unit
5.25
V
30
0
25
70
°c
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT5428.ITT7428
Parameter
V IH
High-level input voltage
V IL
Min
Typ'
Max
2
Unit
Test Conditions 2
V
Low-level input voltage
O.S
V
V1
Input Clamp Voltage
-1.5 .
V
Vcc = Min. Ii = -12mA
VOH
High-level output voltage
V
VCC= MIN. VCC = 0.8V
2.4
IOH = -2.4mA
VOL
Low-level output voltage
0.4
V
VCC = MIN. VIH = 2.0V
IOL = 4SmA
High-level input current (each
input)
40
uA
VCC = MAX. VI = 2.4V
1
mA
Vce= MAX,VI = 55V
IlL
LOW-level input current (each
input)
-1.6
mA
VCC = MAX. V I
lOS
Short-circuit output current 3
-lS0
mA
VCC = MAX
ICCH
Supply current. high-level output
21
mA
VCC = MAX. VI = OV
ICCL
Supply current. low-level output
57
mA
VCC = MAX. VI = 5V
IIH
SWITCHING CHARACTERISTICS. Vee
-70
= 0.4V
= 5V. TA = 25°e. N = 10
ITT5408. ITT740S
Parameter
Min
Typ
Max
Unit
Test Conditions
ltpLH
Propagation delay time.
low-to-high-Ievel output
9
ns
CL = 50pFRL = 133,Jl-
tpHL
Propagation delay time.
high-to-Iow-Ievel output
12
ns
CL = 50pFRL = 133-"-
3-52
ITT&428, ITT7428,ITT&433, 11T7433
QUADRUPLE 2-INPUT POSITIVE NOR BUFFERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT5409, ITT7409
Parameter
Min
Typl
Max
Unit
Test Conditions 2
V 1H
High-level input voltage
V 1L
Low-level input voltage
0.8
V
IOH
High-level output current
250
uA
VOL
Low-level output voltage
0.4
V
IIH
High-level input current (each,
input)
40
uA
= MIN. V1L = 0.8V
= 5.5V
VCC = MIN. VIH = 2.0V
IOL = 48mA
VCC = MAX, VI = 2.4V
1
rnA
VCC = MAX. VI = 5.5V
IlL
Low-level input current (each
input)
-1.5
mA
VCC = MAX. VI = 0.4V '
ICCH
Supply current. high-level output
21
mA
VCC = MAX. VI = OV
ICCL
Supply current. low-level output
57
mA
VCC= MAX. VI = 5V
"
SWITCHING CHARACTERISTICS, Vee
2
V
VCC
VOH
= 5V. TA = 25°e. N = 10
ITT5409,ITT7409
Parameter
I
2
3
Min
Typ
Max
Unit
Test Conditions
tpLH
Propagation delay time.
low-to-high-Ievel output
15
ns _
CL = 50pFRL = 133..1\..
tpHL
Propagation delay time.
high-to-Iow-Ievel output
18
ns
CL = 50pFRL = 133-,A.
All typical values are atVCC = 5\1. TA = 25°C.
,
,,
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
' ,
'
Not more than one output should be shorted at a time.
ITT
----ITT5430, ITT7430
8-INPUT POSITIVE NAND GATES
SEMICONDUCTORS
a-INPUT POSITIVE NAND GATES
OUAL- .IN-LiNE PACKAGE
PI N CONFIGURATION
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
(TOP VIEW)
NCeD
A
VCC
B
NC
A0
B0
H
G
E
VCC
Z
@NC
@z
G
@GNO
c0
NC
00
z
POSITIVE LOGIC:
@NC
= ABCOEFGH
' - - -.... @H
'----11-0
POSITIVE LOGIC:
G
Z = ABCOEFGH
schematic
4 kQ
1.6 kQ
I kQ
GNO
AS
0
GH
'----.r------'
INPUTS
NOTES: 1. (omponenl values shown are nominal
2. HC - No internal (onRedio"
Recommended Operating Conditions
Min
Supply Voltage V CC:
4.5
4.75
5
5
- 55
0
25
25
5430 Circuits ............... .
7430 Circuits .................. .
Normalized Fan-Out From Each Output. N ..
............................................... .
Operating Free-Air Temperature Range. TA: 5430 Circuits................................
7430 Circuits....................
3-54
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
ITIS430, ITI7430
8-INPUT POSITIVE NAND GATES
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
Vin(1)
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vcc = Min Ii = -12 mA
Vout (1 )
Logical 1 output voltage
V
Vee = MIN. Yin = 0.8 V.
Iload = -400 uA
Vout(O)
Logical 0 output voltage
0.4
V
Vee = MIN. Yin = 2V.
I sink = 16 mA
lin(O)
Logical 0 level input current
(each input)
-1.6
mA
Vee = MAX. Yin = 0.4 V
lin(1 )
Logical 1 level input current
(each input)
40
uA
1
mA
Vee = MAX. Yin = 2.4 V
Vee = MAX. Yin = 5.5 V
-20
-55
mA
Vee = MAX
-18
-55
lOS
2
2.4
V
3.3
0.22
Short-circuit output current 3
ITT5430
ITT7430
lee(O)
Logical 0 level supply current
3
6
mA
Vee = MAX. Yin = 5 V
lee(1)
Logical 1 level supply current
1
2
mA
Vee = MAX. Yin = 0
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°C. N = 10
Parameter
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL= 15pF.R L =400Q
tpd1
Propagation delay time to
logical 1 level
13
22
ns
eL = 15 pF. RL = 400 Q
1
2
3
=
=
All typical values are at Vee
5 V. TA
25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3-55
ITT
----ITT5432, ITT7432
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE-OR GATES
schematic (each gate)
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)T
Vee
VCC
4B
OUTPUT
INPUTS
~
4A
I~
~--------~--~----4---~GND
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1) .......................... 7 V
Input voltage .......................................................... 5.5 V
Operating free-air temperature range:
ITT5432 Circuits ........................... -55°C to 125°C
ITT7432 Circuits .................................... O°C to 70°C
Storage temperature range ........... -65°C to 150°C
Note:
POSITIVE LOGIC:
~:
A+B
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE
1. Voltage values are with respect to network
ground terminal.
THE SAME FOR ALL PACKAGES.
recommended operating conditions
ITT5432
Supply voltage, Vee
Normalized fan-outfrom each output N
ITT7432
Min
Nom
Max
Min
Nom
Max
Unit
4.5
5
5.5
4.75
5
5.25
V
High logic level
20
20
Low logic level
10
10
-55
Operatin g free-air temperature, T A
3-56
25
125
0
25
70
DC
ITT5432, ITT7432
QUADRUPLE 2-INPUT POSITIVE-OR GATES
ELECTRICAL CHARACTERISTICS over reoommended operating free-air temperature range
(unless otherwise noted)
Parameter·
Min
Typ'
Max
V IH
High-level input voltage
V il
low-level input voltage
0.8
V
-1.5
V
VI
Input clamp voltage
V OH
High-level output voltage
Val
low-level output voltage
II
2
2.4
V
3.3
0.22
V
0.4
V
Input current at maximu m input
voltage
1
rnA
IIH
High-level input current
40
uA
III
low-level input current
-1.6
rnA
lOS
Short-circuit output current 3
-20
-55
rnA
-18
-55
= MAX. II = -12mA
VCC = MIN. V IH = 2V.
10H = -800uA
VCC = MIN, V il = 0.8V,
10l = 16mA
VCC = MAX, VI = 5.5V
VCC
= MAX, VI = 2AV
VCC = MAX, VI = OAV
VCC = MAX ITT5432
Vce
ITT7432
ICCH
Supply current. high-level output
15
22
mA
ICCl
Supply current. low-level output
23
38
rnA
=
Test Conditions 2
Unit
= MAX, See Note 2
VCC = MAX, See Note 3
VCC
=
, All typical values are at V CC
5V, TA
25°C.
Forconditionsshown as MIN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
2
Notes:
2. ICCH is measured with one input of each gate at 4.5V, the remaining inputs grounded, and outputs open.
3. ICCl is measured with both inputs of all gates grounded, and outputs open.
SWITCHING CHARACTERISTICS. Vee = 5V, TA = 25°e, N = 10
Parameter
Min
Typ
Max
Test Conditions
Unit
tpHl
Propagation delay time,
high-to-Iow-Ieveloutput
14
22
ns
Cl
= 15 pF, Rl =
tplH
Propagation delay time,
low-to-high-Ieveloutput
10
15
ns
Cl
= 15 pF, Rl = 40o-n-
3-57
40o-n-
•
I
ITT
-----ITT5437, ITT5438, ITT7437, ITT7438
QUADRUPLE 2-INPUT POSITIVE NAND BUFFERS
Package: Dual In-Line and Flat Pack
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NAND
BUFFERS
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
IA
Supply voltage V CC (see Note 1) ........................... 7 V
Input voltage (see Note 1) ................................... 5.5 V
Inte~emitter voltage (see Note 2) ....................... 5.5 V
Output voltage (see Notes 1 and 3):
ITT5438, ITT7438 Circuits ........................... 5.5 V
Operating free-air temperature range:
ITT5437, ITT5438 Circuits ..... -55°C to 125°C
ITT7437, ITT7438 Circuits .............. ooC to 70°C
Storage temperature range ........... -65°C to 150°C
Notes:
VCC
46
4A
4r
26
36
1. Voltage values, except interemitter voltage,
are witl:! respect to network ground terminal.
2. This is the voltage between two emitters of
a mUltiple-emitter transistor.
3. This is the maximum voltage which should
be applied to any output when it is in the
POSITIVE LOGIC:
r= A 6
!PIN ASSIGNMENTS FOR THESE CIRCUITS ARE
THE SAME. FOR ALL PACKAGES.
off state.
schematics (each buffer)
""----",,,---"""'_--0 vee
4 kU
600!!
" " - - - - " , , , - - - - - - 0 vee
100U
60Dsz
INPUTS
INPUTS { :
{:o--+-..
.,------0 OU~UT
OUTPUT
0---+-"
r
~~----4-~~---OGND
40011
ITT5438. ITT7438 (OPEN-COLLECTOR
~~----+--~-~--oGND
OUTPUT)
ITT5437. ITT7437 (TOTEM-POLE OUTPUT)
3-58
ITT5437, ITT5438, ITT7437, ITT7438
QUADRUPLE 2-INPUT POSITIVE NAND BUFFERS
recommended operating conditions
ITT5437, ITT5438
Typ
Min
Max
ITT7437, ITT7438
Typ
Min
Max
4.5
4.75
Supply voltage Vee
5
Normalized fan-out from each output. N
5.5
5
30
-55
Operating free-air temperature range. TA
25
125
Unit
5.25
V
30
0
25
70
°e
-
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT5437,ITT7437
Parameter
Min
Typ'
Max
V IH
High-level input voltage
V il
low-level input voltage
0.8
V
VI
Input clamp voltage
-1.5
V
V OH
High-level output voltage
VOL
low-level output voltage
II
2
Test Conditions 2
Unit
V
0.4
V
Input current at maximum input
voltage
1
mA
= MIN. II = -12mA
Vee = MIN. V il = 0.8V.
10H = -1.2mA
Vee = MIN. V IH = 2V.
10l = 48mA
Vee = MAX. VI = 5.5V
IIH
High-level input current
40
uA
Vee
III
low-level input current
-1.6
mA
= MAX. VI = 2.4V
Vee = MAX. VI = O.4V
lOS
Short-circuit output current 3
-70
mA
Vee
Vee
V.
2.4
0.22
-20
leeH
Supply current. high-level output
9
15.5
mA
leel
Supply current.low-Ievel output
34
54
mA
3-59
Vee
= MAX. VI = 0
= MAX. All ilputs at OV
Vee = MAX. All inputs at 5V
ITT5437, ITT5438, ITT7437, ITT7438
QUADRUPLE2-INPUT POSITIVE NAND BUFFERS
ELECTRICAL CHARACTER ISTICS over recommended operating free-air temperature range
IlInless otherwise noted)
ITT5438.ITT7438
Parameter
V IH
Min
High-level input voltage
Typ'·
Max
2
V
V IL
Low-level input voltage
0.8
V
VI
I nput clamp voltage
-1.5
V
IOH
High-level output current
250
uA
VOL
Low-level output voltage
0.4
V
IIH
IlL
,
0.22
= MIN. II = -12mA
Vec = MIN. V IL = 0.8V.
V OH = 5.5V
Vee
Vce - MIN. V IH - 2V.
IOL 48mA
Input current at maximum input
voltage
1
mA
=
Vce = MAX. VI = 5.5V
High-level input current
40
uA
VCC
Low-level input current
-1.6
mA
Vec
,
I
Test Conditions 2
Unit
-,-,
CCH
Supply current, high-level output
5
8.5
mA
ICCL
Supply current. lOW-level output
34
54
mA
= MAX. VI = 2.4V
= MAX. VI = 0.4V
Vec = MAX. All inputs at OV
VCC = MAX. All inputs at 5V
, All typical values are at V CC = 5V. TA = 25°C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time. and duration of the short-circuit test should not exceed one
second.
2
SWITCHING CHARACTERISTICS,V ee
Parameter
= 5V.TA = 25°e. N = 30
ITT5437.ITT7437
Typ
Min
Max
ITT5439. ITT7438
Typ
Max
Min
Test Conditions
Unit
tplH
Propagation delay
time.
low-to-high-Ievel
output
13
22
14
22
ns
Cl
= 45pF. Rl = 133-"-
tpHl
Propagation delay
time.
high-to-Iow-Ievel
output
8
15
11
18
ns
Cl
= 45pF. Rl = 133.()..
3-60
__
ITm
ITT5440, ITT7440
. ______________D~UA--L-4--I-N-PU-T--P-O-S-IT-IV-E-N-A-N-D--B-U-FFE_R...
S
SEMICONDUCTORS
DUAL 4-INPUT POSITIVE NAND BUFFERS
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW).
DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
@ID
Vce
20
@IC
2C
'-->-_-@ IB
@GND
@2i!
'-----1-
® 20
0
POSITIVE LOGIC:
2C
i!=ABCD
POSITIVE
LOGIC
i! = ABCD
schematic (each gate)
Component velues shown ere nomlnel.
NC-No Internal Connection
Recommended Operating Conditions
Min
Supply Voltage VCC: 5440 Circuits ........................................................................ .
7440 Circuits .........................................................................
Normalized Fan-Out From Each Output. N ............................................................. .
Operating Free-Air Temperature Range. TA: 5440 Circuits ............................... .
7440 Circuits ............................... .
3-61
Nom Max
4.5
4.75
5
5
-55
0
25
25
5.5 .
5.25
30
125
70
Unit
V
V
°c
°c
ITT5440, ITT7440
DUAL 4-INPUT POSITIVE NAND BUFFERS
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
V
2
Vin (l )
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vout (l)
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
lin(O)
lin( 1)
lOS
2.4
V
3.3
0.4
V
Logical 0 level input current
(each input)
-1.6
rnA
Logical 1 level input current
(each input)
40
uA
1
-20
-18
Short-circuit output current 3
0.28
rnA
= MAX, V in = 2.4 V
= MAX, Vin = 5.5 V
-70
rnA
Vee
= MAX
-70
rnA
Logical 0 level supply current
17
27
rnA
lee(1)
Logical 1 level supply current
4
8
rnA
Parameter
= Min Ii = -12 rnA
Vee = MIN, Vin = 0.8 V,
Iload = -1.2 uA
Vee = MIN, V in = 2V,
Isink = 48 rnA
Vee = MAX, Vin = 0.4 V
Vcc
Vee
Vee
lee(O)
SWITCHING CHARACTERISTICS. Vee
Test Conditions 2
I
r
ITT5440
.ITT7440
= MAX. Vin = 5 V
Vee = MAX. Vin = 0
Vee
= 5V, TA = 25°C. N = 30
Min
Typ
Max
Test Conditions
Unit
tpdO
Propagation delay time to
logical 0 level
8
15
ns
eL
= 15pF,R L = 133 Q
tpdl
Propagation delay time to
logical 1 level
13
22
ns
eL
= 15pF.R L = 133Q
1
2
3
All typical values are at Vee = 5 V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3-62
ITT5442, ITT5443, ITT5444,
ITT7442, ITT7443, ITT7444
4-UNE-TO-10-UNE DECODERS (1-0F-10)
ITT
----SEMICONDUCTORS
4-LINE-TO-10-LINE DECODERS (1-0F-10)
• BCD-to- Decimal
• Excess-3-to-Decimal
•
Excess-3-Gray-to-Decimal
Also for applications as
• 4-Line-to-16-Line Decoders
•
3-Line to B-Line Decoders
DUAL- IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP'VIEW)t
These monolithic decimal decoders consist of eight
inverters and ten four-input NAND gates. The i!1verters are connected in pairs to make BCD input
data available for decoding by the NAN D gates. Full
decoding of valid input logic ensures that all outputs remain off for all invalid input conditions.
In5442/1TT7442 BCD-to-decimal. ITT5443/1TT7443 excess-3-to-decimal. and ITT5444/1TT7444 excess-3-gray-to-decimal decoders
feature fa miliar transistor-transistor-Iogic (TTL) circuits with inputs and outputs which are compatible
for use with other TTL and DTL circuits. D-c noise
margins are typically one volt and power dissipation
is typically 140 milliwatts. Full fan-out of 10 is
available at all outputs.
The
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply Voltage. V CC (See Note 1) .......................... 7V
Input Voltage. Vin (See' Note 1) ........................... 5.5V
Operating Free-Air Temperature Range:
ITT5442. ITT5443.
ITT5444 Circuits ........................... - 55°C to 125°C
ITT7442.1TT7443.
ITT7444 Circuits .................................... OoC to 70°C
Storage Temperature Range ......... - 65°C to 150°C
POSITIVE
LOGIC
SEE
FUNCTION
TABLE
tplN ASSIGNMENTS FOR THESE CIRCUITS
ARE
THE
SAME FOR
ALL PACKAGES
recommended operating conditions
Min
Nom
Max
Unit
Supply Voltage VCC (See Note 1): ITT5442. ITT5443. ITT5444 Circuits.....................
ITT7442.ITT7443. ITT7444 Circuits.....................
Normalized Fan-Out from each Output (N) .........................................................................
4.5
4.75
5
5
5.5
5.25
v
Note: 1. Voltage values are with respect to network ground terminal.
3-63
10
V
ITT5442, ITT5443, ITT5444,
ITT7442, ITT7443, ITT7444
4-LlNE-TO-1 O-LiNE DECODERS (1-0F-1 0)
TRUTH TABLES
ITT5442/ITT7442
BCD
INPUT
ITT5443/ITT7443
EXCESS 3
INPUT
ITT5444/ITT7444
EXCESS 3 GRAY
INPUT
ALL TYPES.
DECIMAL
OUTPUT
..
D
C
B
A
D
C
B
A
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
0
0
1
1
0
1 0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
0
0
1
.0
1
0
1
1
1
1
1~ 1
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1 ·1
1
1
1
1
1
1
1
1
1
0
,1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
TYPICAL OF
ALL OUTPUTS
EQUIVALENT OF
EACH INPUT
VCC----1I---
INPUT
3-64
ITT5442, ITT5443, ITT5444,
ITT7442, ITT7443, ITT7444
4-UNE-TO-10-LlNE DECODERS (1-0F-10)
ELECTRICAL CHARACTERISTICS Over Recommended Operating Temperature Range
(unless otherwise noted)
MIN
PARAMETER
Vin(1 )
Vin(O)
Input voltage required to
ensure logical 1 at any
input terminal
TYP:j:
MAX UNIT
2
V
Input voltage required to
ensure logical 0 at any
input terminal
0.8
V
-
Vout(O) Logical 0 output voltage
lin(1 )
Logical 0 level input current
(each input)
los
Short-circuit output current§
Icc
Supply current
V1
Vin(1)= 2V,
Vcc=MIN,
Vin(O)= 0.8V, Iload = - 400uA
V
Vcc= MIN,
Vin(O)= 0.8V,
40
uA
Vcc = MAX,
Yin = 2.4V
1
mA
Vcc= MAX,
Vin = 5.5V
1.6
mA
Vcc= MAX
Vin = 0.4V
mA
Vcc = MAX
5442, 5443, 5444
7442, 7443, 7444
mA
Vcc= MAX,
5442, 5443, 54'!.!
7442, 7443, 7444
Vcc= Min
!i=-12mA
0.4
Logical 1 level input current
(each input)
lin(O)
V
2.4 .
Vout(1) Logical 1 output voltage
TEST CON DITIONSt
-
20
-
55
-
18
-
55
28
28
Input Clamp Voltage
41
56
-
1.5
V
SWITCHING CHARACTERISTICS, (Vcc= 5V, TA= 25°C, N = 10)
PARAMETER
MIN
tpdO
Propagation delay time to
logical 0 level through
two logic levels
10
tpdO
Propagation delay time to
logical 0 level through
three logic levels
tpd1
tpd1
Propagation delay time to
logical 1 level through
two logic levels
10
Propagation delay time to
logical 1 level through
three logic levels
TYP
MAX
UNIT
TEST CONDITIONS
22
30
ns
CL=15pF, RL=400n
23
35
ns
CL= 15pF, RL= 400 n
17
25
ns
CL=15pF, RL=400n
26
35
ns
CL=15pF, RL=400n
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended
operating conditions for the applicable device type.
:j: All typical values are at Vcc=5V, TA=25°C.
§ Not more than one output should be shorted at a time.
3-65
t:
:::l
!l
III
Z
m
I
cr
-I
...
Co
OUTMO
OUTPVJO
OUTMI
Ol1JMI
INI'UT A
OUTM'
OUTM2
OUTM'
Ol1JM3
OUTM3
OUTP\.n4
OUTM4
I
r-
o·
:::l
0n
OVTP\JT 0
.J::>.
iii·
ce
i»
3
til
o
o
I
I
r-
INMI
~.~
~
~~
o
o
m
--b-I
w
I
CUlM'
INMC
OlllM5
OUTPUT'
INPUTC
IHMC
Ol
Ol
OUTM6
OUTM.
OUTM7
OUTM7
OUTM'
OUTMi
OUT"'"
OUT"'"
OUTPUT 9
OVJl'UT9
OUT"'"
0UT""7
INPUT D
IHMO
5442/7442 BCD-TO-DECIMAL
5443/7443 EXCESS-3·TO·DECIMAL
5444/7444 EXCESS-3-G RA Y-TO·DECIMAL
tt
:::tJ ~~
en
OUTM.
""(11
Z
m
o
OUTM'
INPUT!
:t::t
.tt.
:t::t
...,en
o-n
I
- ITT- - - - ITT5445, ITT54145, ITT7445, ITT74145
BCD-TO-DECIMAL DECODER/DRIVERS
SEMICONDUCTORS
BCD-TO-DECIMAl
DECODER/DRIVERS
DUAL-IN-liNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
TTL MSI LAMP. LOGIC. OR MOS DRIVERS
• Full Decoding of Input Logic
·80 mA Sink-Current Capability
These monolithic BCD-to-decimal decoder/drivers
consist of eight inverters and ten four-input NAND
gates. The inverters are connected in pairs to make
BCD input data available for decoding by the NAND
gates. Full decoding of valid BCD input logic
ensures that all outputs remain off for all invalid
binary input conditions. These decoders feature TTL
inputs and high-performance. n-p-n output transistors designed for use as indicator/relay drivers or
as open-collector logic-circuit drivers.
Each of the high-breakdown output transistors
(lTT5445. ITT7445 = 30 volts and ITT54145.
ITT74145 = 15 volts) will sink up to 80 milliamperes of current. Each input is one normalized Series 54n4 load. Inputs and outputs are entirely
compatible for use with TTL or DTL logic circuits.
and the outputs are compatible for interfacing with
most MOS integrated circuits. Power dissipation is
typically 215 milliwatts.
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply Voltage VCC (See Note 1) .......................... 7 V
Input Voltage. V in {See Note 1 ) .......................... 5.5 V
Maximum Current into each Output
(See Note 2) ......................................................... 1 rnA
Operating Free-Air Temperature Range:
lTT5445.ITT54145 Circuits ....... -55°C to 125°C
lTT7445.ITT74145 Circuits ................ O°C to 70°C
Storage Temperature Range ......... -65°C to 150°C
POSITIVE LOGIC: SEE FUNCTION TABLE
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE
THE SAME FOR ALL PACKAGES.
TRUTH TABLE
INPUTS
1 2 3 4
5 6 7 8
9
0 0 0 0
0
1 1 1 1
1 1 1 1
1
0 0 0
1 0
1
1 1
0 0
1 0
1 1 0
1 1
1 1 1 0
1 1 1 1. 1
1 1 1 1
1
1
1 1 1 1
1
1 1 1 1
1
0
1 0 0
1 1 1 1 0
0
1 0
1 1 1 1 1 0
0
1 1 0
1 1 1 1 1
1 0
0
1 1 1
1 1 1 1 1
1 1 0
1
1
1 0 0 0
1 1 1 1 1
1 1 1 0
1
1 0 0
1
1 1 1 1 1
1 1 1 1 0
1 0
1 0
1 1 1 1 1
1 1 1 1
1
1 0
1 1 1 1 1 1 1
1 1 1 1
1
1
1 1 0 0
1 1 1
1 1
1
1
1 1 1 1 1
1 1 1 1
1
1 1 1 1 1 1
1 1 1 1
1
1 1 1 1 1
1 1 1 1
1
1 1 1 1 1 1 1 1 1
1 1 1 1
1
1 0
1 1 1 0
3-67
1 1 1
0 0
1
lIIot8s: 1. These voltage values are with respect to
network ground terminal.
2. This rating applies when the output is off.
OUTPUTS
0 C B A 0
ITT5445, ITT54145, ITT7445, ITT74145
BCD-TO-OECIMAL DECODER/DRIVERS
recommended operating conditions
MIN
Supply Voltage Vcc (See Note 1): ITT5445, ITT54145 Circuits .................. .
ITT7445, ITT74145 Circuits .................. .
Voltage on any Output (See Note 2): ITT5445, ITT7445 Circuits ... ,............ .
!TT!'i4145, ITT7 4145 Circuits .......... ..
4.5
4.75
NOM MAX
5
5
5.5
5.25
30
15
UNIT
V
V
V
V
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V in (1) .
Input voltage required to
ensure logical 1 at any input
terminal
Vin(O)
Input voltage required to
ensure logical 0 at any input
terminal
Von
On-state output voltage
Min
Typl
Max
2
Unit
Test Conditions 2
V
0.5
0.8
V
0.9
V
VCC - MIN,
Isink = 80 mA
0.4
V
VCC - MIN,
Isink = 20 mA
VCC
Off-state output voltage
(lTT5445 or ITT7445)
30
V
VCC - MAX,
loff = 250uA
Voff
Off-state output voltage
(lTT54145 or ITT74145)
15
V
VCC = MAX,
loff = 250 uA
lin(1)
Logical 1 level input current
(each input)
40
uA
VCC = MAX, V in = 2.4 V
1
mA
VCC -,. MAX, V in -5.5 V
lin(O)
Logical 0 level input current
(each input)
-1.6
mA
VCC = MAX, V in = 0.4 V
ICC
Supply current
43
62
mA
VCC = MAX
43
70
mA
,
ITT5445,
ITT54145
ITT7445,
ITT74145
SWITCHING CHARACTERISTICS. VCC =5V, TA = 25°C
Parameter
Min
Typl
Max
Unit
Test Conditions 2
tpd1
Propagation delay time to
logical 1 level
50
ns
CL = 15pF,R L
= 100n
tpdO
Propagation delay time to
logical 0 level
50
ns
CL = 15pF,R L
= 100n
1
2
=
All typical values are at V cc
5V. TA :0 25° C.
For conditions 'shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3-68
ITT5445, ITT54145, ITT7445, ITT74145
BCD-TO-DECIMAL DECODER/DRIVERS
functional block diagram
DECODER/DRIVER GATES
~
,
INPUT A
INPUT INVERTERS
1\
o-[)o
A
B
,
c
OUTPUT 0
,...... 0
A
A
ii
c
OUTPUT 1
t- O
{>A
A
B
L
OUTPUT 2
t- O
INPUT B
A
0-[>0
B
B
L
OUTPUT 3
t- O
A
~>.
ii
c
OUTPUT 4
t- O
A
INPUT C
ii
0-[>0
C
L
~
OUTPUT 5
t- O
[>oc
A
B
C
OUTPUT 6
t- O
A
INPUT D
B
0-[>0
0
C
l)oD
B
C
OUTPUT 7
B
A
'-
OUTPUT 8
D
A
B
C
'--- D
3-69
OUTPUT 9
ITT5445, ITT54145, ITT7445, ITT74145
BCD-TO-DECIMAL DECODER/DRIVERS
schematic
vcc.-------e---------e-------------~.-------~~--ovcc
4kQ
3 kQ
3 kQ
4kQ
INTERNAL
A, 8, C, OR 0
INPUT "'--- ...
INTERNAL
A, ii, C, OR i5
1.5 kQ
GND.---~~----~----------------~---oGND
. EACH PAIR OF INPUT INVERTERS
Vcc4----.--------------------~
HQ
320Q
INTERNAL
CONNECTION
TO INPUT
INVERTERS
(SEE LOGIC
DIAGRAMI
OUTPUT
1 kQ
2kQ
2 kQ
GND 4-----.......-----------~~----....I
EACH DECODER/DRIVER GATE
Note: 1. Component values shown are nominal.
3-70
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447 A, ITT7448
ITT
-,
----BCD-TO-SEVEN-SEGMENT DECODER/DRIVERS
SEMICONDUCTORS
Package: Dual In-Line and Flat Pack
BCD-TO-SEVEN-SEGMENT
DECODER/DRIVERS
•
•
•
•
•
•
•
•
•
ITT5446A. ITT5447A. ITT7446A. ITT7447A
featuring
Direct Drive For Indicators
Open Collector Outputs
Lamp Test Provision '
Leading/Trailing Zero Suppression
Ceramic Or Plastic Dual In Line Packages
ITT5448.ITT7448
featuring
Passive Pull Up Outputs
Lamp Test Provision
Leading/Trailing Zero Suppression
Ceramic Or Plastic Dual In Line Packages
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEWJ t
INPUTS
{
B I
C
LAMP
TEST
RB
OUTPUT
RB
INPUT
OUTPUTS
JO 6
INPUTS~
ALL CIRCUIT TYPES FEATURE:
• TTL-DTL Compatibility
• Full Decoding of all 16 Input Combinations
• Lamp Intensity Modulation Capability
POSITIVE LOGIC: SEE TRUTH TABLES
tPIN ASSIGNMENTS FOR THESE CIRCUITS ARE THE SAME
FOR ALL PACKAGES.
These monolithic. TTL. B CD-to-seven-segment
decoder/drivers consist of NAN D gates. input
buffers. and seven AND-DR-INVERT gates. Two
configurations offer active-low. high-sink-current
outputs (ITT5446A and ITT5447A) for driving indicators directly; active-high. passive-pull-up outputs. (ITT5448) for current-sourcing applications to
drive logic circuits or discrete. active components.
Seven NAND gates and one driver are connected
in pairs to make BCD data and its complement
available to the seven decoding AND-OR-INVERT
gates. and the remaini':lg 'NAND gate and three input buffers provide' lamp test. blanking in-,
put/ripple-blanking output, and ripple-blanking input for the ITT5446A. ITT544 7A and ITT5448.
The circuits accept 4-bit binary-coded-decimal
(BCD) and. depending on the state of the auxiliary
inputs. decodes this data to drive a seven-segment
display indicator (ITT5446A and ITT5447A) or other components (ITT5448). The relative positivelogic output levels. as well as conditions required
at the auxiliary inputs. are shown in the truth tables.
Output configurations of the ITT5446A and ITT5447 A are, designed to withstand the relatively
high voltages required for seven segment indicators. The ITT5446A outputs will withstand 30
volts. and the ITT5447A will withstand 15 volts.
with a maximum reverse current of 250 micro-
amperes. Indicator segments requiring up to 40
milliamperes of current may be driven directly from
the ITT5446A or ITT5447 A high-performance output transistors. Segment identification with resultant displays are shown in Figure A. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.
The ITT5446A. ITT5447A. and ITT5448 circuits incorporate automatic leading and/or trailing edge
zero-blanking control (RBI and RBO), Lamp test
(LT) of these types may be performed at any time
when the BI/RBO node is a logical 1. All types contain an overriding blanking input (BI) which can be
used to control the lamp intensity or to inhibit the
outputs. All inputs except the BI/RBO nodes are
one normalized Series 54/74 load. Inputs and outputs are entirely compatible for use with TTL or
DTL logic outputs, Power dissipation is typically
320 milliwatts (ITT5446A, ITI5447 A. and ITT5448).
The ITT5446A. ITT5447A. and ITT5448 are char,acterized for operation over the full military temperature range of -55°C to 125°C. The ITT7446A. ITT7447A. and ITT7448. (electrically identical to the corresponding Series 54 types) are for
operation over the temperature range of O°C to
70°C.
3-71
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447A, ITT7448
BCD-TO-SEVEN-SEGMENT DECOD ER/DR IVERS
TRUTH TABLE ITT5446A, ITT5447A, ITT7446A, 1TT7447A
/.-----Inputs - - - - - - - - - "
Decimal
or
Function
/r---------Outputs - - - - - - "
LT
RBI
0
'c
B
A
BI/RBO
a
b
c
• d
e
f
g
Note
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
X
0
0
0
1
1
1
0
0
1
1
1
1
1
2
1
X
0
0
1
0
1
0
0
1
0
0
1
0
3
1
X
0
'0
t
1
1
0
0
0
0
1
1
0
4
1
X
0
1
0
0
1
1
0
0
1
1
0
0
5
1
X
--
0
1
0
1
1
0
1
0
0
1
0
0
6
1
X
0
1
1
0
1
1
1
0
0
0
0
0
7
1
X
0
1
1
1
1
0
0
0
1
1
1
1
8
1
X
1
0
0
0
1
0
0
0
0
0
0
0
9
1
X
]
0
0
1
1
0
0
0
1
1
0
0
10
1
.X
1
0
1
0
1
1
1
1
0
0
1
0
11
1
X
1
0
1
1
1
1
1
0
0
1
1
0
12
1
X
1
1
0
0
1
1
0
1
1
1
0
0
13
1
X
1
1
0
1
1
0
1
1
0
1
0
0
14
1
X
. 1
1
1
0
1
1
1
1
0
0
0
0
15
1
X
1
1
1
1
1
1
1
1
1
1
1
1
BI
X
X
X
X
X
X
0
1
1
1
1
1
1
1
2
RBI
1
0
0
0
0
0
0
1
1
1
1
1
1
1
3
LT
0
X
X
X
X
X
1
0
0
0
0
0
0
0
4
Notes:
1. BI/RBO is wire-AND logic serving as blanking input (BI} and/or ripple-blanking output (RBO). The blanking input
(BI) must be open or held at a logical 1 when output functions 0 through 15 are desired, and the ripple-blanking'
input (RBI) must be open or at a logical 1 if blanking of a decimal 0 'is not desired. X = input may be high
or low.
2. When a logical 0 is applied directly to the blanl0UTPUT
L-----~--J-t---~--~--~-----------lAMP TEST
Component values shown are nominal
3--76
__________________~--------~~GND
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447 A, ITT7448
BCD-TO-SEVEN-SEGMENT DECODER/DRIVERS
functional block diagram ITT5448. ITT7448
OUTPUT
INPUT
A
OUTPUT
b
INPUT
B
INPUT
C
OUTPUT
INPUT
o
OUTPUT
d
QUTPUT
BLANKING
INPUT OR
RIPPLE-BLANKING.
OUTPUT.
OUTPUT
f
LAMP-TEST 0-+.,-----'
INPUT
OIJTPUT
9
RIPPLE-BLANKING 0 - + - - - , - - - - '
INPUT
.
3-77
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447 A ITT7448
BCD-TO-SEVEN-SEGMENT DECODER/DRIVERS
functional block diagrams
ITT5446A. ITT5447A. ITT7446A. ITT7447A
OUTPUT
OUTPUT
b
INPUT
C
OUTPUT
INPUT
D
OUTPUT
d
OUTPUT
BLANKING
INPUT OR
RIPPLE-BLANKING
OUTPUT
OUTPUT
f
lAMP-TEST
INPUT
o-+--....l
RIPPLE-BLANKING 0-+------"
IMPUT
3-78
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447 A, ITT7448
BCD-TO-SEVEN-SEGMENT DECODER/DRIVERS
Electrical Characteristics Over Recommended Operating Free-air Temperature Range
(unless otherwise noted)
Parameter
V IH
High-level input
voltage
VIL
Low-level input
voltage
Input clamp voltage,
any input except
BI/RBO
VI
Min
Max
Typ*
Unit
Test Conditionst
V
2
0..8
V
1.5
V
1DmA
Vee - MIN, 1,-
250.
!J.A
0..4
V
Any input
except
BI/RBO
1
rnA
= MIN, VIII - 2V,
= o..8V,
= -2o.o.llA
Vee = MIN, VIII - 2V,
VII. = D.8V, 1 = 8mA
Vee = MAX, VIII - 2V,
VIL = o..8V,
VO(off) =MAX
Vee - MAX, Vm - 2V,
VII. = o..8V,
lo(on) = 4o.mA
Vee = MAX, VI = 5.5V
High-level input
current
Any input
except
BI/RBO
40.
!J.A
Vee
= MAX, V, = 2.4V
Low-level input
current
Any input
except
BI/RBO
BI/RBO
-1.6
Vee
= MAX, VI = q.4V
= MAX
VOIl
High-level output
voltage
BI/RBO
VOl.
Low-level output
voltage
BI/RBO
10(0ff)
Off-state output
current
a thru g
VO(on)
On-state output
voltage
a thru g
It
Input current at
maximum input
voltage
1m
In.
los
Short-circuit output
current
Icc
Supply current
2.4
3.7
V
0..3
0..4
V
Vee
VIL
lOll
01•
0..3
rnA
-4
-4
rnA
Vee
85
10.3
rnA
Vee
MAX,I5446A,5447A
See Note 2,V446A,7447A
BI/RBO
64
61
tFor conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions for the applicable
type.
=
=
=
tAli typical values are at Vee
5V, TA
25°C.
NOTE 2: Icc is measured with all outputs open
and all inputs at 4.5V.
Switching Characteristics, Vee = 5V, TA = 25°C
Parameter
to ff
Turn-off time from A input
ton
Turn-on time from A input
torr
Turn-off time from RBI input
tOil
Turn-on time from RBI input
Test Conditions
Min
Typ
Max
10.0.
C•.
= pF,
RL
= 12Dfl.
10.0.
10.0.
10.0.
3-79
Unit
ns
ns
ITT5446A, ITT5447 A, ITT5448
ITT7446A, ITT7447 A, ITT7448
BCD-TO-SEVEN-SEGM ENT DECOD ER/DRIVERS
Electrical Characteristics Over Recommended Operating Free-air Temperature Range
(unless otherwise noted)
Parameter
Min
Max
Typ*
VIH
High-level input
voltage
VII~
Low-level input
voltage
V,
Input clamp voltage,
any input except
BI/RBO
VOH
High-level output
voltage
a thru Q
BIIRBO
2.4
2.4
10
Output cu rrent
a thru g
-1.3
VOL
Low-level output
voltage
Unit
Test Conditions'f
2
V
0.8
-1.5
4.2
3.7
-2
.27
= -1OmA
V
Vee
= MIN,
V
Vee
= MIN, V = 2V,
= 0.8V, 1011 = MAX
VII~
mA
V
0.4
.V
I,
IlI
Vee - MIN, Vo - 0.85V,
Input conditions as for
Von
Vee
Vn .
= MIN, V = 2V,
= 0.8V, 1 = MAX
IH
01•
"
Input current at
maximum input
voltage
Any input
except
BI/RBO
1
mA
Vee - MAX, V, - 5.5V
III!
High-level input
current
Any input
except
BI/RBO
40
p.A
Vee - MAX, VI - 2AV
III~
Low-level input
current
Any input
except
BI/RBO
Short-circuit output BI/RBO
current
-1.6
4
mA
Vee
-4
mA
Vee - MAX
los
Icc
=
Supply current
=
=
= 5V, TA = 25°C
Parameter
Min
Typ
Max
Propagation delay time,
high-to-Iow-Ievel output
from A input
100
t PLII
Propagation delay time,
low-to-high-Ievel output
from A input
100
tpln~
Propagation delay time,
high-to-Iow-Ievel output
from RBI input
100
tPLH
Propagation delay time,
low-to-high-Ievel output
from RBI input
100
t PIIl•
I
5448
Vee
MAX,
53 76
mA
See Note 2
53 90
I 7448
~AII typical values are at Vee
5V, TA
25°C.
NOTE 2: Icc is measured with all outputs open
and all inputs at 4.5V.
tFor conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions for the applicable
type.
Switching Characteristics, Vee
= MAX, V, = OAV
Unit
Test Conditions
ns
CI.
= 15 pF,
5448: RI.
7448: R..
3-80
ns
= 1kn
= 677 n
ITT5450, ITT5451, ITT7450, ITT7451
EXPANDABLE DUAL 2-WIDE 2-INPUT
AND-DR-INVERT GATES
ITT
----SEMICONDUCTORS
EXPANDABLE DUAL 2-WIDE 2-INPUT
AND-OR-INVERT GATES
DUAL- IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
SEE
NOTE4
reD
@IO
x(~
@IC
lAG)
®IZ
@GNO
VCcG
@2Z
2A0
®20
2B0
02C
POSITIVE LOGIC:
POSITIVE LOGIC:
iii! =(AB1+{C01+lXl
X = OUTPUT OF
IB0
Z =(ABI+(CO)+(X)
X = OUTPUT OF ITT5460/ITT7460
ITT5460/ITT7460
schematic (each gate)
r-----,.---.---.-~ vee
4kA
1.6kA 4kA
130.n.
Notes:
OUTPUT
C
I kll
GATE I
OF
5450 7450 ONLY
1. Component values shown are nominal.
2. Both expander inputs are used simultaneously for expanding.
3. If expander is not used leave X and X pins
open.
4. Make no external connection to X I!nd X pins
of the ITI5451 and ITI7451.
5. A total of four expander 'gates can be connected to the expander inputs.
L---t-+-_--..J
CLOCK~+-+-~-..J
TO OTHER
FLIP·FLOP
NOTE: Component values shown are nomlrw!.
3-101
','"
mm
I
_".1-.1- ___________
ITT5475, ITT7475
4_-_B_IT_B_I_S_TA_B_LE_L_A_T_C_H_E_S
, SEMICONDUCTORS
4-BIT BISTABLE LATCHES
"
These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units,
Information present at a data (0) input is transferred to the Q output when the clock is high. and
the Q output will follow. the data input as long as
the clock remains·high. When the clock goes low.
the information (that was present at the data input
at the time the transition occurred) is retained at
the Q output until the clock is permitted to go high.
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
10
10
20
20
The iTI5475/ITI7475 features complementary Q
and Q outputs from a.4-bit latch. and is a"vailable
in the 16-pin packages.
CLOCK
These circuits are completely compatible with all
popular TIL. or OTL families. Typical power dissipation is 40 milliwatts per latch. The Series 54
circuits are characterized for operation over the full
military temperature range of - 55°C to 125°C and
Series 74 circuits are characterized for operation
from ooe to 70°C.
.30
3-4
GNO
VCC
POSITIVE
LOGIC: SEE TRUTH TABLE
logic
TRUTH TABLE
(Each Latch)
tn
0
+
tn 1
Q
1
1
0
0
Notes: 1. tn = bit time before clock negative-going
transition.
2. tn 1 = bit time after clock negative-going
transition.
'
absolute maximum ratings (over operating
temperature range unless otherwise noted)
Supply Voltage. Vee (See Note 3) ......................... 7 V
Input Voltage, Vin (See Notes 3 and 4) ............. 5.5 V
Operating Free-Air Temperature Range:
ITT5475 ......... ;; ............................... -55°C to 125°C
ITT7475 ..................................................·.00eto 70°C
Storage Temperature Range ......... -65°C to 150°C
Notes: 3" These voltage values are with respect to
. network ground terminal.
4. Input signals must be zero or positive with
respect to network ground terminal .
+
.
recommended operating conditions
MIN
Supply Voltage Vee (See Note 3.): ITT5475 .............................................:........ .
, ITT7475 ..................................................... ..
Normalized Fan-Out From Outputs .. ~ ................................................................. ..
4.5
4.75
Note: 3. These voltages are with respect to network ground terminal.
3-102
NOM MAX UNIT
5
5
5.5
5.25
10
V
V
ITT5475, ITT7475
4-BIT BISTABLE LATCHES
ELE CTR ICAL CH ARACTE R ISTI CS over recommended operating free-air temperature range
(unless otherwise noted)
. Parameter
Min
Vin (1)
Input voltage required to ensure
logical 1 level at any input
terminal
Vin(D)
Input voltage required to ensure
logical 0. level at any input
terminal
Vout (l )
Logical 1 output voltage
Vout(D)
Logical 0. output voltage
lin(D)
Typ'
Max
2
Test Conditions 2
Unit
V
0..8
V
V
Vee = MIN.
Iload = -40.0. uA
0..4
V
Vee = MIN.
Isink = 16 rnA
Logical 0. level input current at
D
-3.2
rnA
Vee = MAX. Vin = D.4V
lin(D)
Logical 0. level input current at
clock
-6.4
rnA
Vee = MAX. Yin = D.4V
lin(l )
Logical 1 level input current at
D
80.
uA
Vee = MAX. Yin = 2.4V
1
rnA
Vee = MAX. Yin = 5.5V
Logical 1 level input current at
clock
160.
uA
Vee = MAX. Yin = 2.4V
1
rnA
Vec=MAX. Yin = 5.5V
lin(1)
IDS
lee
Short-circuit output current
Supply current
2.4
3
-20.
-57
mA
Vee = MAX.
ITT5475
-18
-57
rnA
Vout =0.
ITT7475
32
46
rnA
Vee
32
53
rnA
== MAX.
ITT5475
ITT7475
All typical values are at Vee = 5V. TA = 25° e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
. for the applicable device type.
3 Not more than one output should be shorted at a time.
1
2
3-103
ITT5475, ITT7475
• 4-BIT BISTABLE LATCHES
SWITCHING CHARACTERISTICS. Vee
Parameter
= 5V. TA = 25°e. N = 10
Min
Typ
Max
Unit
Test Conditions
tsetup1
Minimum logical 1 level
input setup time at D input
7
20
ns
CL = 15pF.R L =4000
tsetupO
Minimum logical 0 level
input setup time at D input
14
20
ns
CL = 15 pF. RL = 4000
thold1
Maximum logical 1 level
input hold time required at D
input
0
15'
ns
CL = 15pF. RL = 4000
tholdO
Maximum logical 0 level
input hold time required at D
input
0
6'
ns
CL = 15 pF. RL = 4000
tpd1(D-O)
Propagation delay time to
logical 1 level from D input
to 0 output
16
30
ns
CL = 15 pF. RL = 4000
tpdO(D-O)
Propagation delay time to
. logical 0 level from D input
to 0 output
14
25
ns
CL = 15 pF. RL = 4000
tpd1(D-O)
Propagation delay time to
logical 1 level from D input
to·O output
24
40
ns
CL = 15 pF. RL = 4000
~dO(D-Ol .
Propagation delay time to
logical 0 level from D input
to 0 output
7
15
ns
CL
=;
15 pF. RL = 4000
;~
tpd l(C-O)
Propagation delay time to
logical 1 level from clock
input to 0 output
16
30
ns
CL = 15 pF. RL = 4000
tpdO(C-O)
Propagation delay time to
logical 0 level from clock
input to 0 output
7
15
ns
CL = 15pF. RL = 4000
tpd1(C-O)
Propagation delay time to
logical 1 level from clock
input to 0 output
16
30
ns
CL = 15pF. RL = 4000
tpdO(C-O)
Propagation delay time to
logical 0 level from clock
input to 0 output
7
15
ns
CL = 15pF. RL = 4000
I
, These typical times indicate that period occurring prior to the fall of clock pulse (to) below 1.5V when data at the
D input will still be recognized and stored.
3-104
ITT5475, ITT7475
4-BIT BISTABLE LATCHES
functional block diagram (each latch)
»-;.-0 Q
Q
(ITT547 5/ITT74 75)
CLOCK
DATA
schematic (each latch)
Q
GND
To Other Latch
DATA
CLOCK
Note: Component values shown are nominal.
3-105
ITT5476, ITT7476
DUALJ-K MASTER-SLAVE FLIP-FLOPS
WITH PRESET AND CLEAR
ITT
----SEMICONDUCTORS
I
DUAL J-K MASTER-SLAVE FLIP-FLOPS
WITH PRESET AND CLEAR
DUAL-iN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEw)t
The ITT7476 J-K flip-flop is based on the masterslave principle. Inputs to the master section are
controlled by the clock pulse. The clock pulse also
regulates the state of the coupling transistors which
connect the master and slave sections. The sequence of operation is as follows:
1. Isolate slave from master
2. Enter information from J and K inputs to master
3. Disable J and K inputs
4. Transfer information from master to slave.
logic
TRUTH TABLE
(Each Flip-Flop)
t n +1
tn
J
K
a
0
0
an
0
1
0
1
0
1
1
1
5n
POSITIVE
LOGIC:
LOW INPUT TO PRESET SETS Q TO LOGICAL I
LOW INPUT· TO CLEAR SETS Q TO LOGICAL 0
CLEAR. AND PRESET ARE INDEPENDENT OF CLOCK
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE SAME
FOR ALL PACKAGES.
H.IGH~
2
.
3
. . . . . ..
N(ltes:
1. tn = Bit time before clock pulse.
2. t n + 1 .'" Bit time after clock pulse.
1
4
LOW
CLOCK WAVEFORM
recommended operating conditions
Min
Supply Voltage Vec:
4.5
4.75
-55
0
tTI5476 Circuits ..........................................................................
ITI7476 Circuits .......... ,...............................................................
Operating Free-Air Temperature Range, TA : ITT5476 Circuits ,................................
ITI7476 Circuits .................................
Normalized Fan-Out From Each Output, N ..................................................................... .
Width of Clock Pulse, tp(clock) ..........................................................................................
Width of Preset Pulse, tp(preset) .......................................................................................
20
25
~~~~h;:t~:;~;~,I::~:~~cl.~.a.~~ ........................................................:: . ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ~tp~c~OCk)
Input Hold Time, thold ........................................................................................................
3-106
0
Nom Max
5
5
25
25
5.5
5.25
125
70
10
Unit
V
V
DC
DC
ns
ns
ns
ns
ITT5476, ITT7476
DUALJ-K MASTER-SLAVE FLIP-FLOPS
WITH PRESETAND CLEAR
ELECTRICAL CHARACTERISTICS. TA
Parameter
=
ooe to 70 e (unless otherwise noted)
0
Min
Typ'
Test Conditions
Unit
Max
2
V
2
V in(1 )
Input voltage required to ensure
logical 1 at any input term inal
Vin(O)
I nput voltage required to ensure
logical 0 at any input terminal
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vee = MIN. Ii = -12mA
Voutll)
Logical 1 output voltage
V
Vee = MIN. Iload = -400uA
VoutlO)
Logical 0 output voltage
0.4
V
Vee = MIN. Isink = 16mA
linlO)
Logical 0 level input current at
J or K
-1.6
mA
Vee = MAX. V in = O.4V
linlO)
Logical 0 level input current at
clear. preset. or clock
-3.2
mA
Vee = MAX. V in = 0.4V
linll )
Logical 1 level input current at
JorK
40
uA
Vee
1
mA
Vee = MAX. V in = 5.5V
Logical 1 level input current at
clear. preset. or clock
80
uA
Vee = MAX. V in = 2.4V
1
mA
-57
mA
Vr:r: - MAX. V in - 5.5V
ITT5476
Vee = MAX.
lin(1)
lOS
Short-circuit output current
3.5
2.4
0.22
3
-20
18
ICC
20
Supply current leach flip-flop)
SWITCHING CHARACTERISTICS. Vee = 5V. TA
Parameter
f max
tpdl
Maximum clock frequency
= 25°e. N =
Min
Typ
15
20
Propagation delay time to Ipgical
I
I ITT7476
V·In = 0.
57
40
mA
2.4V
MAX. V in
Vee - MAX
10
Max
Unit
Test Conditions
MHz
eL = 15 pF. RL = 400.0.
16
25
ns
eL = 15 pF. RL = 400.0.
25
40
ns
eL - 15 pF. RL - 400.0.
o level from clear or preset.to
output
tpdO
Propagation delay time to logical
1 level from clear or preset to
output
tpdl
Propagation delay time to logical
1 level from clock to output
10
16
25
ns
eL - 15 pF. RL - 40011.
tpdO
Propagation delay time to logical
o level from clock to output
10
25
40
ns
eL = 15 pF. RL = 400.0.
, All typ i ca I values are at Vee
5V. TA - 25 0 e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating c·onditions
2
for the applicable device type.
3
Not more than one output should be shorted at a time.
3-107
ITT5476, ITT7476
DUAL J-K MASTER-SLAVE FLIP-FLOPS
WITH PRESET AND CLEAR
130
n
TO OTHER
FLIP·FLOP
.,...--+.......-oQ
Qo-.......--4....
1 kn
CLEARo-t::±========~~t===!Jl====E~==========±::±~~PRESET
J
K
2kn
2kn
TO OTHER
FLlp·FLOP
~--~----+-------+-~----~--~----~--~_~~ GND
CLOCK
Note: Component values shown are nominal.
schematic (each flip· flop)
3-108
ITT
-
TYPES ITT5480, ITT7480
GATED FULL ADDERS
SEMICONDUCTORS -~---
GATED FULL ADDERS
DUAL-IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(Top VIEW)
AceD
B2
BI®
BI
B20
@A*
@A2
@AI
Ae
veeG)
@GND
A*
B*0
Vee
AI
enG)
POSITIVE LOGIC: SEE FUNCTION TABLE
POSITIVE LOGIC: SEE FUNCTION TABLE
These single-bit. high-speed. binary full adders with
gated complementary inputs. complementary sum
(rand!) outputs and inverted carry output are designed for medium- and high-speed. multiple-bit.
parallel-add/serial-carry applications. These circuits
(see schematic) utilize diode-transistor logic (DTL)
for the gated inputs. and high-speed. high-fan-out
transistor-transistor logic (TTL) for the sum and
carry outputs and are entirely compatible with both
DTL and TTL logic families. The implementation of
a
single-inversion.
high-speed.
Darlingtonconnected serial-carry circuit minimizes the necessity for extensive "look-ahead" and carry-cascading
circuits.
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 4) ........................... 7V
Input voltage (see Note 5) .................................... 5.5V
Operating free-air temperature range:
ITT5480 .......................................... -55°C to 125°C
ITT7480 ...................................................... 0o to 70°C
Storage temperature range ........... -65°C to 150°C
Notes:
@1
BC®
A2
logic
FUNCTION TABLE
(See Notes 1 2 and 3)
Inputs
Outputs
.r
B
A
Cn +l
'f
L
L
H
H
H
L
L
L
H
H
L
L
H
H
L
H
L
H
H
L
L
H
H
L
Cn
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
H
L
L
L
H
H
H = high level. L = low level
Notes:
4. Voltage values are with respect to network
ground terminal.
5. Input signals must be zero or. positive with
respect to network ground terminal.
3-109
+
+
1. A = AC
A' A 1 • A2.
8 = Be + S' + 81 • B2.
2. When A' is used as an input. A 1 or A2 must
be low. When 8' is used as an input. 81
or 82 must be low.
3. When A1 and A2 or 81 and 82 are used
as inputs. A' or 8'. respectively. must be
open or used to perform dot-AN D logic.
TYPES lTI5480, ITT7480
GATED FULL ADDERS .
RECOMMENDED OPERATING CONDITIONS
ITT5480
MIN
Supply voltage. V CC
NOM
4.5
NOM
5.5
4.75
5
5
MAX
5.25
-400
Cn+l
-200
-200
A* or B*
-120
-120
16
16
~ Qr
Low-level output current.IOL
MIN
-400
~
High·level output current. IOH
or
1TT7480
MAX
~
l:
Cn+l
A* or B*
Operating free-air t~mperature. T A
-55
8
8
4.8
4.8
125
0
70
UNIT
V
IlA
mA
°c
ELECTRICAL CHARACTERISTICS. over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level
output voltage·
VOL
Low-level
output voltage
E orE
Min
ITT5480
Typ 1
Max
Min
ITT7480
Typ 1
Max
0.8
2.4
3.5
0.8
2.4
Test Conditions 2
V
2
2
Unit
3.5
V
V
VCC= MAX. IOH = -400uA
Cn +l
VIH = 2V
IOH = -200uA
A" orB"
V1L =O.8V
IOH - -.120uA
E or E
0.22
0.22
0.4
0.4
V
Vce = MAX.
IOL= 16mA
Cn +l
VIH = 2V.
IOL - 8rnA
A" orB"
VIL =0.8V
IOL = 4.8rnA .
II
Input current at maximum input
voltage
1
1
'rnA
Vee = MAX. VI = 5.5V
IIH
High-level
15
15
uA
Vee = MAX. VI = 2.4V
rnA
Vee = MAX. VI = 0.4V
rnA
Vce = MAX
rnA
Vee = MAX. See Note 6
input current
A 1·A2 ·B 1·B 2 ·
AC·orBe
-1..1
A" orB"
IlL
" Low-level
input current
t
• Digital Computer Systems
• Data-Handling Systems
• Control Systems
This full adder performs the addition of two 4-bit
binary numbers. The sum (~\ outputs are provided
for each bit and the resultant carry (C 4 ) is obtained
from the fourth bit. Designed for mediumto-high-speed. mUltiple-bit, parallel-add/serial-carry
applications, the circuit utilizes high-speed, highfan-out transistor-transistor logic (TTL) but is compatible with both DTL and TTL families. The implementation of a single-inversion, high-speed,
Darlington-connected serial-carry circuit within
each bit minimizes the necessity for extensive
"look-ahead" and carry-cascading circuits. The
power dissipation level has been maintained considerably below that attainable with equivalent
standard integrated circuits connected to perform
four-bit full-adder functions.
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply Voltage V CC (See Note 1) ........................... 7V
Input Voltage, Vin (See Notes 1 and 2) .............. 5.5V
Operating Free-Air Temperature Range:
ITT5483 Circuits .......................... -55°C to 125°C
ITT7483 Circuits ................................... 0° C to 70° C
Storage Temperature Range ......... -65°C to 150°C
, Pin assignments for these circuits are the same
for all packages.'
logic
TRUTH TABLE
INPUT
%%
IA AIXIX"- %f- IXIX, IXX
,
,
,
co=o
1. These voltage values are with respect to
network ground terminal.
2. Input signals must be zero or positive with
"3
A_
o
0
0
0
,
3-116
0
0
0
0
0
0
0
,
0
0
0
0
,
0
0
0
0
0
, ,
, , ,
,
,
, ,
0
0
0
0
0
0
0
3. Input conditions at A l' A 2 . B l' B2 , and Co
are used to determine outputs ~1 and I:2'
and the value of the internal carry C2 . The
values at C2 . A 3 , B3 . A 4 , and B4 . are then
used to determine outputs I: 3 . I: 4 . and C4 .
0
0
0
0
,
,
,
, ,
,., ,
0
0
0
0
0
~-
!:4
0
0
-2
c_
::3
, ,
,
,
,
0
0
Note:
WHEN
C2 =1
Cz=O
-2
A3
0
respect to network ground terminal.
C o =1
WHEN
.
0
Notes:
OUTPUT
,
,
,
,
,
,
,
,
0
0
,
, ,
, ,
,
, ,
0
0
0
,
0
0
0
, ,
0
0
0
,
0
0
0
, ,
, ,.
0
0
,
0
0
,
,
, ,
, ,
0
,
0
0
0
0
0
0
0
,
,
,
,
, ,
,
,
,
,
, ,
, ,
, ,
, , ,
0
0
c_
0
0
0
0
0
0
0
0
0
0
ITT5483, ITT7483
4-BIT BINARY FULL ADDERS
recommended operating conditions
Supply Voltage V CC: (See Note 1) ITT5483 Circuits ................................................
ITT7483 Circuits ................................................
Normalized Fan-Out From Outputs:
Min
Nom Max
4.5
4.75
5.5
5.25
5
5
C4 ····················································........................................... ;........................................ .
5
2: 1 .2: 2 ,2: 3 or 2:4 ................................... ,.............................................................................
10
Unit
v
V
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Typ
Min
1
Max
V
V in (1)
Input voltage required to ensure
logical 1 at any input termi~al
Vin(O)
Input voltage required to ensure
logical 0 at any input terminal
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vout (l )
Logical 1 output voltage
Vout(OI
Test Conditions 2
Unit
2
V
2.4
VCC = MIN, Ii = -12mA
Vee ~ MIN,
VIH
c
VIL=04V
IOH = -200 ~A
vee = MIN,
IOL '16mA
0.4
V
Logical 0 level input current at
A 1.A3 , B 1, B3 ,orCO
-6.4
mA
VCC = MAX, V in = 0.4V
Logical 1 level input current at
A 2 • A 4 • B2 • or 8 4
-1.61
mA
Vee = MAX, V in = 0.4V
Logical 1 level input current at
A 1, A 3 , B 1 , B3 , or Co
160
uA
Vec =.MAX, V in = 2.4V
1
rnA
Vec = MAX, V in =5.5V
Logical 1 level input current at
A 2, A 4 , 8 2 , or 8 4
40
uA
Vec = MAX, V in = 2.4V
Logical 0 output voltage
VIH = 2 V,
VIL"·0.4V
lin(O)
linlO)
lin(l )
lin(1 )
lOS
lOS
ICC
1
2
3
IOH = -400 "A
2V,
IOL=8mA
1
mA
Vce = MAX, V in = 5.5V
Short-circuit output current at
E1, E2 , E3 , or E4 ,3
-20
-55
mA
Vec - MAX
-18
-55
mA
ITT5483
1--ITT7483
Short-circuit output current at
C4 3
-20
-70
mA
MAX
-18
~70
mA
ITT5483
ITT7483
78
110
mA
Vec = MAX
78
128
mA
ITT5483
ITT7483
Supply Current
VCC
All typical values are at V CC = 5V, TA = 25°e.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
3-117
I TT5483 , ITT7483
4-BIT BINA RY FULL ADDERS
SWITCHING CHARACTERISTICS. Vee
Parameter
tpd1
1
From
(Input)
Co
To
(Output)
= 5 V. TA = 25°e (unless otherwise noted N = 10)
Min
Typ
Max
Unit
34
ns
CL = 15 pF. RL = 400
40
ns
CL - 15 pF. RL = 400
38
ns
CL = 15 pF. RL = 400
42
ns
CL = 15 pF. RL = 400
50
ns
CL = 15 pF. RL = 400
60
ns
CL = 15 pF. RL = 400
55
ns
CL = 15 pF. RL = 400
55
ns
CL = 15 pF. RL = 400
35
48
ns
CL = 15 pF. RL = 780
22
32
ns
C L = 15 pF. RL = 780
rl
rl
40
ns
CL = 15pF. RL = 400
rl
35
ns
CL = 15 pF. RL =400
rl
40
ns
CL = 15 pF. RL = 400
35
ns
C L = 15 pF. RL = 400
rl
rl
1
tpdO
tpd1
Co
2
tpdO
tpd1
Co
3
tpdO
tpd1
Co
4
tpdO
tpd1
Co
C4
tpdO
tpd1
A2 or 8 2
2
tpdO
tpd1
A4 or 8 4
4
tpdO
1
Test Conditions
tpd1 is propagation delay time to logical 1 level. tpdO is propagation delay time to logical 0 level.
3-118
rl
rl
rl
rl
rl
rl
rl
rl
ITT5483. ITT7483
4-BIT BINA RY FULL ADDERS
schematic
Note: Component values shown are nominal.
Resistor values are in ohms.
3-119
ITT
----ITT5486, ITT7486
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SEMICONDUCTORS
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
QUADRUPLE 2-INPUT
EXCLUSIVE-OR GATES
PIN CONFIGURATION
(TOP VIEW)
• Input-Clamping Diodes Simplify System
Design
• Fully Compatible with TTL. DTL. and Other
MSI Circuits
• Typical Propagation Delay Times: 12 ns
description
Each of these monolithic. quadruple 2-input
exclusive-OR gates utilize TTL circuitry to perform
the function Y = AS + AB. When the input states
are complementary. the output goes to a logical 1.
POSITIVE LOGIC:
These circuits are fully compatible for use with other TTL or DTL circuits. Input clamping diodes are
provided to minimize transmission line effects and
thereby simplify system design. Input buffers are
used to lower the fan-in requirement to only one
normalized series 54174 load. A full fan-out to 10
normalized series 54174 loads is available from
each of the outputs in the logical state. A fan-out
of 20 is provided in the logical 1 state to facilitate
connection of unused inputs to used inputs.
Propagation delay is 12 nanoseconds and power
dissipation is 37.5 milliwatts typically for each
exclusive-O R function.
l . A 4& B
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ........................... 7V
Input voltage ........................................................... 5.5V
Operating free-air temperature range:
ITT5486 .......................................... - 55°C to 125° C
ITT7486 ................................................... ooC to 70°C
Storage temperature range ........... -65°C to 150°C
a
Note: 1. These voltage values are with respect to network
ground terminal.
The ITT5486 is characterized for operation over the
full military temperature range of -55°C to 125°C
and the ITT7486 is characterized for operation from
O°C to 70°C.
recommended operating conditions
ITT5486
Supply voltage,
Vee
Min
Nom
4.5
5
ITT7486
Max
Min
Nom
Max
Unit
5.5
4.75
5
5.25
V
High-level output current. IOH
-800
-800
uA
Low-level output current. IOL
16
16
rnA
Operating free-air temperature. TA -55
125
70
°c
3-120
a
ITT5486, ITT7486
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
ELECTRICAL CHARACTERISTICS. over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
ITT5486
Typ'
Max
ITT7486
Typ'
Max
Min
Unit
Test Conditions 2
V IH
High-level input
voltage
V IL
Low-level input
voltage
0.8
0.8
V
-1.5
-1.5
V
Vee = MIN, II = -8 mA
V
Vee = MIN, V IH = 2V,
V IL = 0.8V, 10H = -800 uA
0.4
V
Vee = MIN, V IH = 2V,
V IL = 0.8V, 10L = 16 mA
2
2
V
VI
I nput clamp voltage
V OH
High-level output
voltage
VOL
Low-level output
voltage
II
Input current at
maximum input
voltage
1
1
mA
Vee = MAX. VI = 5.5V
IIH
High-level input
current
40
40
uA
Vee = MAX, VI = 2.4V
IlL
Low-level input
current
-1.6
-1.6
mA
Vee = MAX. VI = O.4V
lOS
Short-circuit output
current 3
-55
mA
Vee = MAX
ICC
Supply current
50
mA
Vee = MAX, See Note 2
2.4
2.4
3.4
0.2
-20
0.4
0.2
-55
30
3.4
-18
43
30
, All typical values are at Vee = 5V. TA = 25°C.
Fo rconditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions
forthe applicable type.
3 Not more than one output should be shorted at a time.
2
Note:
2. ICC is measured with the inputs grounded and the outputs open.
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e
Parameter'
From
(Input)
tpLH
tpHL
Min
Typ
Max
Unit
Aor B
15
23
ns
Other input low
e L = 15 pF. RL = 400Jl
AorB
11
17
ns
Other mput low
e L = 15pF.
Test Conditions
RL = 400n
tpLH
Aor 8
18
30
ns
Other input high
tpHL
Aor B
13
22
ns
e L = 15 pF, RL = 400Sl.
Other input high
e L = 15 pF. RL = 400Sl.
-
, tPLH = propagation delay time, low-to-hig h-Ievel output.
tpHL - propagation delay time. hlgh-to-Iow-Ievel output
3-121
ITT5490, ITT7490
__ JI[~~ __________________________D_EC_A_D_E__C_O_U_N_T_ER_S
SEMICONDUCTORS
DECADE COUNTERS
DUAL-IN -LINE PACKAGE
MSI TTL HIGH-SPEED DECADE COUNTERS
for applications in
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
• Digital Computer Systems
• Data-Handling Systems
• Control Systems
description and typical count configurations
These high-speed, monolithic decade counters consist of four dual-rank, master-slave flip-flops internally interconnected to provide a divide-by-two
counter and a divide-by-five counter. Gated direct
reset lines are provided to inhibit count inputs and
return all outputs to zero or to a binary coded
decimal (BCD) count of 9. As the output from flipflop A is not internally connected to the succeeding
stages, the count may be separated in three independent count modes:
1. When used as a binary coded decimal decade
counter, the BO input must be externally connected to the A output. The A input receives
the incoming count. and a count sequence is
obtained in accordance with the BCD count
sequence truth table shown above. In additi.On
to a conventional zero reset. inputs are provided to reset a BCD count for nine's complement
decimal applications.
2. If a symmetrical divide-by-ten count is desired
for frequency synthesizers' or other applications requiring division of a binary count by
a power of ten, the 0 output must beex~
ternally connected to the A input. The input
count is then applied at the BO input and a
divide-by-ten square wave is obtained at output A.
3. For operation as a divide-by-two counter and
a divide-by-five counter, no external intereon"
nections are required. Flip-flop A is used as a
binary element for the divide-by-two function.
The BO input is used to obtain binary divideby-five operation at the B, C, and 0 outputs.
o
A
INPUT
INPUT
Rom
NC
RO(21
NC
VCC
ILG~;::t.;:tL;..:JGND
R9Ul
R9(21
POSITIVE LOGIC:
SEE TRUTH TABLE
In this mode, the two counters operate independently: however, all four flip-flops are reset
simultaneously.
These circuits are completely compatible with Series 54174 TTL and OTL logic families. Average
power dissipation is 160 mW.
absolute maximum ratings (over operating
temperature range unless otherwise. noted)
Supply Voltage V CC (See Note 3) ........................... 7V
InputVoltage V in (See Notes 3 and 4) ............... 5.5V
Operating Free-Air Temperature Range:
ITT5490 Circuits ........................... -55°Cto 125°C
ITT7490 Circuits .................................... ooC to 70°C
Storage Temperature Range ......... -65°C to 150°C
Notes: 3. These voltage values are with respect to
network ground term inaf.
4. Input signals must be zero or positive with
respect to network ground terminal.
ITT5490, ITT7490
DECADE COUNTERS
logic
TRUTH TABLES
RESET COUNT
(See Note 2)
BCD COUNT SEQUENCE
(See Note 1)
~OUNT
OUTPUT
0 C B A
RESET INPUTS
OUTPUT
RO(1)
RO(2)
R9(1)
R9(2)
0
C
B
A
0
0
0
0
0
1
1
0
X
0
0
0
0
1
0
0
0
1
1
1
X
0
0
0
0
0
2
0
0
1
0
X
X
1
1
1
0
0
1
3
0
0
1
i
X
0
X
0
COUNT
4
0
1
0
0
0
X
'0
X
COUNT
5
0
1
0
1
0
X
X
0
COUNT
6
0
1
1
0
-X
-0
0
X
COUNT
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
NC-No Internal Connection
Notes:
1. Output A connected to input'BOfor BCD count.
2. X indicates that either a logic 1 or a
logic 0 may be present,
MIN
recommended operating conditions
. Supply\loltagevcc (See Note 3) ITT5490 Circuits -.......................::: ............... .
ITT7490 Circuits .........................................
Normalized Fan-Out From Each Output (See Note 5) ...................................... .
Width of Input Count Pulse. tp(in) ........................................................................
Width of Reset Pulse. tp(reset) .......................:.......................................................
4.5
4.75
NOM MAX
5
5
50
50
~
V
V
ns
ns
____________ ____
Note: 5. Fan-outfrom output A to inputBD and to 10 additional Series 54174 loads is permitted.
3-123
UNIT
5.5
5.25
10
~
ITT5490, ITT7490
DECADE COUNTERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
Vin (1)
Input voltage required to ensure
logical 1 at any input terminal
Vin(O)
Input voltage required to ensure
logical 0 atany input terminal
0.8
V
VI
Input Clamp Voltage
-1.5
V
Vout (1)
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
0.4
V
lin(l )
Logical 1 level input current at
40
J.1A
RO( 1)' RO(2)i R9 ( 1)' or R9 (2)
1
Logical 1 level input current at
input A
80
uA
1
rnA
Logical 1 level input current at
input BO
160
J.1A
1
rnA
Logical 0 level input current at
-1.6
rnA
= Min Ii = -12 rnA
= MIN.
= -400 uA
Vee = MIN.
I sink = 16 rnA
Vee == MAX. Vin = 2.4V
Vee = MAX. V in = 5.5V
Vee = MAX. Vin = 2.4V
Vee = MAX. V in = 5.5V
Vee ~ MAX. V in = 2.4V
Vee = MAX. V in = 5.5V
Vee = MAX. V in = O.4V
lin(l )
lin(l )
lin(O)
2
V
2.4
V
rnA
Vee
Vee
Iload
RO( 1)' RO(2)' R9 ( 1)' or R9 (2)
lin(O)
Logical 0 level input current at
input A
-3.2
rnA
Vee
= MAX. Vin = 0.4V
lin(O)
Logical 0 level input current at
input BO
-6.4
rnA
Vee
= MAX. Vin = O.4V
lOS
Short-circuit output current
-20
-57
rnA
Vce
= MAX,
-18
-57
rnA
Ice
Supply current
3
32
46
rnA
32
53
rnA
IlT5490
IlT7490
Vee
= MAX
IlT5490
IlT7490
, All typical values are atV ee = 5V. TA = 25°e
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the particular circuit type.
3 Not more than one output should be shorted at a time.
2
3-124
ITT5490, ITT7490
DECADE COUNTERS
SWITCHING CHARACTERISTICS. VCC
Parameter
f max
Maximum frequency of input
count pulses
tpd1
Propagation delay time to logical
I level from input count pulse to
= 5V. TA = 25°C. N = 10
Min
Typl
10
18
Max
Unit
Test Conditions 2
MHz
CL = 15 pF .. RL = 400 Q
I
60
100
ns
CL = 15 pF. RL = 400 Q
60
100
ns
CL = 15pF.R L =400Q
output C
Propagation delay time to logical
input count pulse to
output C
tpdO
o level from
"k
~
Ill'
.
2.
•
I
schematic
IESET 9 {
IN'UTS (2)'
I
3.......
Component values shown are nominal.
Resistor values are in ohms.
3-125
ITT
------ITT5491A, ITT7491A
8-BIT SHIFT REGISTERS
SEMICONDUCTORS
Package: Dual In-Line and Flat Pack
8-BIT SHIFT REGISTERS
MSI TTL SHIFT REGISTERS
for applications in
• Digital Computer Systems
• Data-Handling Systems
DUAL-IN C LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
• Control Systems
These monolithic serial-in. serial-out. a-bit shift registers utilize transistor-transistor logic (TTL) circuits
a nd are composed of eight R-S master-slave flipflops. input gating. and a clock driver. Single-rail
data and input control are gated through inputs A
and B and an internal inverter to form the complementary inputs to the first bit of the shift register.
Drive for the internal common clock line is provided
by an inverting clock driver. This clock pulse inverter/driver causes these circuits to shift information one bit on the positive edge of an input clock
pulse.
Series 54 devices are characterized for operation
over the full military temperature range of - 55°C
to 125°C; Series 74 devices are characterized for
operation from 0° C to 70° C.
absolute maximum ratings over operating
free-air temperature range (unless otherwise noted)
Supply voltage. V CC (see Note 1) ........................... 7V
Input voltage (see Note 2) .................................... 5.5V
Operating free-air temperature range:
ITT5491A ....................................... -55°Cto 125°C
ITT7491A ................................................ ooC to 70°C
Storage temperature range ........... -65°C to 150°C
Notes:
1. These voltage values are with respect to
network ground terminal.
2. Input signals must be zero or positive with
respect to network ground terminal.
3-126
FLAT PACKAGE
PIN CONFIGURATION
TOP VIEW
NC
NC
NC
Vee
NC
POSITIVE LOGIC: SEE FUNCTION TABLE
NC - NO INTERNAL CONNECTION
ITT5491A, ITT7491A
8-BIT SHIFT REGISTERS
Schematics of inputs and outputs
FUNCTION TABLE
TYPICAL OF BOTH OUTPUTS
EQUIVALENT OF ALL INPUTS
Inputs
Outputs
AT tn
AT t n + 8
A
B
Q
H
H
H
L
L
X
H
X
L
L
L
=
Vee
Vee--_---
QH
INPUT
OUTPUT
H
=
=
H
high.l
low. X
irrelevant
tn = Reference bit time. clock low
t n +8 = Bit time after 8 low-to-high
clock transitions·.
recommended operating conditions
Min
ITT5491A
Nom
Milx
Min
ITT7491A
Nom Max
Unit
5,25
V
High level output current. IOH
-400
-400
uA
Low level output cu rrent. 10 L
16
16
mA
Supply voltage.
Vee
4.5
5
5.5
4.75
5
Width of clock input pulse. tw
25
25
ns
Setup time. tsetup (see Figure 1)
25
25
ns
0
0
ns
Hold time. t hold (see Figure 1)
-55
Operating free-air temperature. TA
3-127
I
125
0
70
°e
ITT5491 A, ITT7491 A
8-BIT SHIFT REGISTERS
ELECTAICAL CHARACTERISTICS. over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input
voltage
V IL
Low-level input
voltage
V1
Input Clamp Voltage
V OH
High-level output
voltage
Min
ITT5491A
Nom
Max
2
204
ITT7491A
'Nom
Max
Min
2
Unit
V
0.8
0.8
V
-1.5
-1.5
V
204
3.5
Test Conditions 2
Vee = MIN. Ii = -12mA
V
Vee = MIN. V IH =2V.
V IL = 0.8V. 10H = -400uA
0.4
V
Vee = MIN. V IH = 2V.
V IL = 0.8V.I OL = 16mA
3.5
\
VOL
Low-level output
voltage
II
Input current at
maximum input
voltage
1
1
mA
Vee
= MAX. VI = 5.5V
IIH
High-level input
current
40
40
uA
Vee
= MAX. VI = 2.4V
IlL
Low-level input
current
-1.6
-1.6
mA
Vee = MAX. VI = OAV
lOS
Short-circuit output
current 3
-57
mA
Vee
= MAX
ICC
Supply current
58
mA
Vee
= MAX. See,Note 4
0.2
35
SWITCHING CHARACTERISTICS. Vee
t max
Maximum clock frequency
0.2
-57
-20
Parameter
004
-18
50
35
= 5V. TA = 25°e. N = 10
Min
Typ
Max
Unit
10
18
MHz
eL
eL = 15pF.R L =400n
eL
tpLH
Propagation delay time.
low-to-high-Ievel output
24
40
ns
tpHL
Propagation delay time.
high-to-Iow-Ievel output
27
40
ns
Test Conditions
= 15 pF. RL = 400 n
= 15 pF. RL = 400n
, Aillypical values are atV ee = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
3 Not more than one output should be shorted at a time.
• ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.,
2
, 3-128
ITT
-----
ITT5492, ITT7492
DIVIDE-8Y-TWELVE COUNTERS
SEMICONDUCTORS
DIVIDE-BY-TWELVE COUNTERS
MSI TTL HIGH-SPEED COUNTERS
for applications in
eDigital Computer Systems
e Data- Handling Systems
-Control Systems
DUAL - IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
logic
TRUTH TABLE
(See Notes 1.2. and 3)
COUNT
OUTPUT
0
C B
A
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1 0
0
5
0,
1 0
1
6
1
0
0
0
7
1 0
0
1
8
1 0
1
0
9
1
0
1
1
10
1 1
0
0
11
1
1 0
1
POSITIVE LOGIC: SEE TRUTH TABLE
Notes:
NC-No Internal Connection
1.
When used as a divide-by-twelve counter,
output A must be externally connected to
input BC. The input count pulses are applied to input A. Simultaneous divisions
of 2. 6, and 12 are performed at the A.
C, and 0 outputs as shown in the truth
table above.
2.
When used as a divide-by-six counter, the
input count pulses are applied to input
BC. Simultaneously, frequency divisions
of 3 and 6 are available at the C and 0
outputs. Independent use of flip-flop A is
available if the reset' function coincides
with reset of the divide-'by-six counter.
1. Output A connected to input B.
2. To reset all outputs to logical 0 both. RO( 1)
and RO(2) inputs must be at logical 1.
3. Either (or both) reset inputs RO( 1) and RO(2)
must be at a logical 0 to count.
These high-speed, monolithic ¢bit binary counters
consist of four master slave flip-flops which are internally interconnected to provide a divide-by-two
counter and a divide-by-six counter. A gated direct
reset line is provided which inhibits the count inputs and simultaneously returns the four flip-flop
outputs to a logical O. As the output from flip-flop
A is not internally connected to the succeeding flipflops, the counter may be operated in two independent modes:
These circuits are completely compatible with Series 54174 TTL and DTL logic families. Average
power dissipation is 155 mW.
3-129
ITT5492, ITT7492
DIVIDE-BY-TWELVE COUNTERS
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply Voltage VCC (See Note 4) ............... " .......... 7V
Input Voltage Vin (See Notes 4 and 5) ., ............. 5.5V
Operating Free-Air Temperatu re Range:
ITT5492 Circuits ........................... ~55°C to 125"C
ITT7492 Circuits .................................... ooC to 10°C
Storage Temperature Range ......... -65°C to 150°C
Notes:
4. These voltage values a re with respect to
network ground terminal.
5. Input signals must be zero or positive with
respect to network ground terminal.
recommended operating conditions
Min
Supply Voltage V CC (See Note 4): JTT5492 Circuits ... ;................................. ..
ITT7492 Circuits ...................................... .
Normalized Fan- Out from Each Output (See Note 6) ..................................... ..
Width of Input Count Pulse, tp(in) .......................................................................
Width of Reset Pulse. tp(reset) ........ ;....................................................................
4.5
4.75
Note:
Nom Max
5
5
5.5
5.25
10
Unit
V
V
ns
ns
50
50
6. Fan-out from output A to input BC and to 10 additional Series 54174 loads is permitted.
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Test Conditions 2
Unit
V in (l )
Input voltage required to ensure
logical 1 at any input terminal
2
V
Vin(O)
Input voltage required to ensure·
logical 0 at any input terminal
O.S
V
Vl
Input Clamp Voltage
~1.5
V
Vce
= Min Ii = -12 mA
V out (l )
Logical 1 output voltage
V
VCC
== MIN,
V
= . . . 400 uA
YCj::= ~,IN, Isink '= . 16 ITlA
2.4
lioad
Vout(O)
Logical 0 output voltage
lin(l )
Logical 1 level input current at
RO( 1) or RO(2) inputs
lin(1)
lin(1)
.•. • O. ~
.co,.
4b
'"
....
1
..
8b
Logical 1 level input current at
input A
Logical 1 level input current at
input BC
..•..
'
1M
..
;;,.
uA
Yec:M~X, Yin ==2.4V
mA
•.Vet"" ~AX'Vil) =5.5V
..
.
uA
. VCO.",MA>t Vin ,=2.4v
rnA
Y<::G ",MAX. ViI) = 5.5'1
u,A
.Vec,:,,¥~: Vin = 2.4V
rnA
.V
ee ,,= MAX. Vin == 5.5V
lin(O)
Logical 0 level input current at
RO(1 iorRO(2) inputs
.... '.6
rnA·
Vee == MAX. Vir'! == O.4V
lin(O)
Logical 0 level inpu!current at
input A
~3.2
ITlA
Vce'= MAX, Vin == 0.4V
3-130
ITT5492, ITT7492
DIVIDE-BY-TWELVE COUNTERS
ELECTR ICAl CHARACTE RISTICS over recommended operating free-air temperature range
(unless otherwise noted) (continued)
Parameter
Min
lin(O)
Logical 0 level input current at
input BC
lOS
Short-circuit output current
ICC
3
Typ'
Max
Unit
Test Conditions 2
-604
mA
VCC = MAX, V in = OAV
-20
-57
mA
VCC = M~,
-18
-57
mA
V out = 0
ITT7492
Supply current
ITT5492
31
44
mA
VCC = MAX
ITT5492
31
51
mA
V in = 4.5V
ITT7492
SWITCHING CHARACTERISTICS. Vee = 5V, TA = 25°e, N = 10
Parameter
Min
Typ
10
18
f max
Maximum frequency of input
count pulses
tpdl
Propagation delay time to logical
1 level from input count pulse to
output 0
60
Propagation delay time to logical
60
tpdO
o level from input count pulse to
Max
Unit
Test Conditions
MHz
CL = 15pF, RL = 400n
100
ns
CL = 15pF,R L =40011.
100
ns
CL = 15pF, RL
= 400n
output 0
1
2
3
All typical values are atV cc = 5V, TA = 25°C.
For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions
forthe particular circuit type.
Not more than one output should be shorted at a time.
Schematic
13.
1k
4k
3-131
_.ITT ______________
ITT_5_4_9_3,_I_TT_74_9_3
4-BIT BINARY
COUNTERS
SEMICONDUCTORS
4-BIT BINARY COUNTERS
MSI TTL HIGH-SPEED RIPPLE-THROUGH COUNTERS
for applications in
• Digital Computer Systems
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
• Data-Handling Systems
• Control Systems
These high-speed. monolithic 4-bit binary counters
consist of four master-slave flip-flops which are internally interconnected to provide a divide-by-two
counter and a divide-by-eight counter. A gated direct reset line is provided which inhibits the count
inputs and simultaneously returns the four flip-flop
outputs to a logical O. As the output from flip-flop
A is not internally connected to the succeeding flipflops the counter may be operated in two independent modes:
1. When used as a 4-bit ripple-through
counter. output A must be externally connected to input B. The input count pulses
are applied to input A. Simultanedus
divisions of 2. 4. 8. and 16 are performed
at the A. B. C. and D outputs as shown in
the truth table above.
2. When used as a 3-bit ripple-through
counter. the input count pulses are applied
to input B. Simultaneous frequency
divisions of 2. 4. and 8 are available at the
B. C. and D outputs. Independent use of
flip-flop A is available if the reset function
coincides with reset of the 3 -bit ripplethrough counter.
These circuits are completely compatible with Series 54/74 lIT and DTL logic families. Average
power dissipation is 40 mW per flip-flop (160 mW
total).
INPUT
B
RoUl
RO(2)
vcc
NC
POSITIVE LOGIC: SEE TRUTH TABLE
NC-No Internal Connection
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply Voltage VCC (See Note.4) ........................... 7V
Input Voltage. V in (See Notes 4 and 5) .............. 5.5V
Operating Free-Air Temperature Range:
ITT5493 Circuits ............................ -55°C to 125°C
ITT7493 Circuits ..................................... O°C to 70°C
Storage Temperature Range ......... -65°C to 150°C
Notes: 4. These voltage values are with respect to
network ground terminal.
5. Input signals must be zero or positive with
respectto network ground terminal.
recommended operating conditions
Min
Supply Voltage VCC (See Note 4): ITT5493 Circuits ......................... :... :.................... .
ITT7493 Circuits ...................................................
Normalized Fan-Out From Each Output (See Note 6) ....................................................
Width of Input Count Pulse. tp(in) ......................................................................................
Width of Reset Pulse. tp(reset) ..........................................................................................
Note 6.
4.5
4.75
Nom Max
5
5
50
50
Fan-out from output A to input B and to 10 additional Series 5417 4 loads is permitted.
3-132
5.5
5.25
10
Unit
V
V
ns
ns
ITT5493, ITT7493
4-BIT BINARY COUNTERS
TRUTH TABLE
(See Notes 1. 2. and 3)
OUTPUT
COUNT
0
C
B
A
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
I
Notes:
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
1
•
I
I
Qutput A connected to input B
2. To reset all outputs to logical 0 both RO(l)
and RO(2) inputs must be at logical 1.
3. Either (or both) reset inputs ROO) and RO(2)
must be a logical 0 to count.
GND
AOUTPUT
B INPUT
B OUTPUT
COUTPUT
DOUlPUT
130
1•
••
Vee
A INPUT
til
RESET 11 {
INPUTS
(2)
Component values shown are nominal.
3-133
ITT5493, ITT7493
4-BIT BINARY COUNTERS
ELECTR ICAl CHARACTER ISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ1,
Max
Unit
Test Conditions 2
V in (1)
Inputvoltage required to ensure
logical 1 at any input term inal
Vin(O)
Input voltage required to ensure
logical 0 at any input terminal
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vee = MIN. Ii = -12mA
Vout (1)
Logical 1 output voltage
V
Vee = MIN. Iload =-400uA
Vout(OI
Logical 0 output voltage
0.4
V
Vee = MIN.l sink = 16mA
lin(1)
Logical .1 level input current at
ROn) or RO(2) inputs
40
uA
Vee = MAX. V in = 204V
1
mA
Vee = MAX. V in = 5.5V
Logical 1 level input current at
A or B inputs
80
uA
Vee = MAX. V in = 204V
1
mA
Vee = MAX. V in = 5.5V
'in(O)
LogicalO level input current at
RO(1 ) or. Rom inputs
-1.6
mA
Vee = MAX. V in = 0.4V
lin(OI
Logical 0 level input current at
A or B inputs
-3.2
mA
Vee = MAX. V in = Oo4V
lOS
Short-circuit output cUHent 3
-20
-57
mA
-18
-57
mA
Vee = MAX.
V out = 0
ITT5493
ITT7493
32
46
mA
32
53
mA
Vee = MAX.
V in = 4.5V
ITT5493
ITT7493
lili( 1 )
SWITCHING CHARACTERISTICS. Vee
Parameter
f max
Maximum frequency of input
count pulses
tpd1
,
....
V
204
Supply current
ICC
tpdO
2
= 5V. TA = 25°e. N = 10
Min
T.yp
10
18
Max
Unit
Test Conditions
MHz
eL = 15pF.R L =400n
Propagation delay time to logical
:·1 level froin input count pulse to
output 0
75
135
ns.
eL = 15pF.R L =400.0
Propagation delay time to logical
o levelfrcim input count pulse to
output 0
75
135
ns
eL = 15 pF. RL = 400n
'.
1 All tYpicalvaluesare at Vee = 5V. TA == 25°C.
ForconditioriS shoyvn as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable circuit type.
3 Not mOre than one output should be shorted at a time.
2
3-134
ITT
-
ITT5494, ITT7494
4-BIT SHIFT REGISTERS
SEMICONDUCTORS -~---
4-BIT SHIFT REGISTERS
TTL MSI PARALLEL-IN SERIAL-OUT REGISTERS
for application as
eDual-Source. Parallel-To-Serial Converter
-Serial-In Serial-Out Register
This monolithic shift register. utilizing transistortransistor logic (TTL) circuits in the familiar Series
74 configuration. is composed of four R-S masterslave flip-flops. four AND-OR-INVERT gates. and
four inverter-drivers. Internal interconnections of
these functions provide a versatile register which
performs right-shift operations as a serial-in. serialout register or as a dual-source. parallel-to-serial
converter. A number of these registers may be connected in series to form an n-bit register.
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
CTOP VIEW)
r
iA
IB
PRESETS
l
lC
All flip-flops are simultaneously set· to the logical
a state by applying a logical 1 voltage to the clear
input. This condition may be applied independent
of the state of the clock input. but not independent
of state of the preset input. Preset input is independent of the clock and clear states.
10
vcc
This register is completely compatible for use with·
TTL and DTL logic circuits and when used with oth·
er TTL circuits. noise margins are typically one volt.·
Typical average power dissipation is 175 milliwatts.
and propagation delay times from clock to output
are typically 25 nanoseconds.
GNO
PR
20
SEA.
IN
The flip-flops are simultaneously set to the logical
1 state from either of two preset input sources. Preset inputs 1 A through 1D are activated during the
time that a positive pulse is applied to preset 1 if
preset 2 is at a logical a level. When the logic levels
at preset 1 and preset 2 are reversed. preset inputs
2A through 2D are active.
Transfer of information to the outputs occurs when
the clock input goes from a logical a to a logical
1. Since the flip-flops are R-S master-slave circuits.
the proper information must appear at the R-S inputs of each flip-flop prior to the rising edge of the
clock input waveform. The serial input provides this
information for the first flip-flop. The outputs of the
subsequent flip-flops provide information for the. remaining R-S inputs. The clear input. preset 1. and
preset 2 must be at a logical a when clocRing occurs.
:3
POSITiVE LOGIC: HIGH INPUT TO CLEAR SETS QA,
QB, Qc AND Qo TO LOGICAL O.
IplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE
SAME FOR ALL PACKAGES.
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply VoltageVcc (See Note 1) ... ,....................... 7V
Input Voltage V in (See Notes 1 and 2) ............... 5.5V
Operating Free-Air Temperature Range:
ITT5494 Circuits ............................ - 55°C to 125°C
ITT7494 Circuits ..................................... aoc to 7aoC
Storage Temperature Range ......... - 65°C to 15aoC
Notes:
3-135
1. The voltage values are with respect to
network ground terminal.
2. Input signals must be zero or positive with
respect to network ground terminal.
ITT5494, ITT7494
4-81T SHIFTREGISTERS
schematic
Note: Component values shown are nominal.
recommended operating conditions
Min
Typ
Max
Unit
Supply Voltage VCC (See Note 1): ITT5494 Circuits
ITT7494 Circuits ...................................................... .
4.5
4.75
5
5
5.5
5.25
V
V
Normalized Fan-Out From Output ......................................................................................
10
Width of Clock Pulse, tp(clock) ..............................................................................................
Width of Clear Pulse, tp(clear) .................................. ............................................................
35
30
Width of Preset Pulse, tp(preset) ...........................................................................................
Serial Input Setup Time: tsetup(l) ............... .........................................................................
tsetup(O) ................................................................................
Serial Input Hold Time, t hold ......................................................................................
30
35
25
0
ns
ns
ns
ns
ns
Note: 1. These voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
2
Unit
V in (1)
Input voltage required to ensure
logical 1 at any input terminal
Vin(O)
Input voltage required to ensure
logical 0 at any input terminal
0.8
V
y,
Input Clamp Voltage
-1.5
V
Test Conditions 2
V
3-136
VCC
= MIN, Ii = -12mA
ITI5494, ITT7494
4-BIT SHIFT REGISTERS
ELECTRICAL CHARACTERISTICS(over recommended operating free-air temperature range
unless otherwise noted)(continued)
'Parameter
Min
Typ'
V out(1)
Logical 1 output voltage
2.4
3.5
Vout(O)
Logical 0 output voltage
lin(l)
Logical 1 level input current at
any input except preset 1 and
preset 2
Logical 1 level input current at
preset 1 and preset 2
lin(l)
0.22
Max
Unit
Test Conditions
V
Vee = MIN. Iload = -400uA
V
Vee = MIN, Isink = 16mA
40
uA
Vee = MAX, Vin = 204V
1
mA
Vee = MAX, Vin = 5.5V
160
uA
Vee = MAX, Vin = 2.4V
1
mA
Vee = MAX, Vin = 5.5V
004
lin(O)
Logical 0 level input current at
any input except preset 1 and
preset 2
-1.6
mA
Vee = MAX, Vin = O.4V
lin(O)
Logical 0 level input current at
preset 1 and preset 2
-6.4
mA
Vee = MAX, Vin = Oo4V
lOS
Short-circuit input current 3
-20
-57
mA
Vee = MAX,
ITI5494
-18
-57
mA
Vout = 0
ITI7494
35
50
mA
Vee = MAX
ITI5494
35
58
mA
lee
Supply current
SWITCHING CHARACTERISTICS. Vee
Parameter
= 5V, TA = 25°e, N = 10
Min
Typ
f max '
Maximum clock frequency
tpdl
Propagation delay time to logical
1 level from clock to output
25
Propagation delay time to logical
25
tpdO
tpdl
tpdO
ITI7494
Max
Unit
Test Conditions
MHz
eL = 15pF, RL =400n
40
ns
eL = 15 pF, RL = 400fi
40
ns
eL = 15 pF, RL = 400fi
Propagation delay time to logical
1 level from preset to output
35
ns
eL= 15pF,R L =400n
Propagation delay time to logical
40
ns
eL = 15pF, RL = 400U
o level from clock to output
10
o level from clear to output
, All typical values are at Vee = 5 V, TA = 25°C.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
for the particular circuit type.
3 Not more than one output should be shorted at a time.
2
3-137
tIJ
I
ITT- - - - _.
ITT5495A, ITT7495A
.
4-BIT RIGHT-SHIFT LEFT-SHIFTREGISTERS
SEMICONDUCTORS
4-BIT RIGHT-SHIFT LEFT-SHIFT
REGISTERS
This monolithic shift register. utilizing transistortransistor-logic (TTL) circuits in the familiar Series
54174 configuration. is composed of four R-S
master-slave flip-flops. four AND-OR-INVERT
gates. one AN D-O R gate. and six inverters-drivers.
Internal interconnections of these functions provide
a versatile register which will perform right-shift or
left-shift operations dependent upon the logical input level to the mode control. A number of these
registers may be connected in series to form an
n-bit right-shift or left-shift reg ister. This register
can also be used as a parallel-in. parallel-out storage register with gate (mode) control.
DUAL-IN - LINE pACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
SERIAL
INPUT
When a logical 0 level is applied to the mode control input. the number-1 AND gates are enabled
and the number-2 AND gates are inhibited. In this
mode the output of each flip-flop is coupled to the
R-S inputs of the succeeding flip-flop and right-shift
operation is performed by clocking at the clock 1
input. In this mode. serial data is entered at the
serial input. Clock 2 and parallel inputs A through
Dare inhibited by the number-2 AND gates.
When a logical 1 level is applied to the mode control input. the number-1 AND gates are inhibited
(decoupling the outputs from the succeeding R-S
inputs to prevent right-shift) and the number-2
AN D gates are enabled to allow entry of data
through parallel inputs A through D and clock 2.
This mode permits parallel loading of the register.
or with external interconnection. shift-left operation. In this mode. shift-left can be accomplished
by connecting the output of each flip-flop to the
parallel input of the previous flip-flop (QD to input
C. and etc.). and serial data is entered at input D.
Clocking for the. shift register is accomplished
through the AND-OR gate E which permits separate clock sources. to be used for the shift-right and
shift-left modes. If both modes can be clocked from
the same source. the clock input may be applied
commonly to clock 1 and clock 2. Information must
be present at the R-S inputs of the master-slave
flip-flops prior to clocking. Transfer of information
to the output pins occurs when the clock input goes
from a logical 1 to a logical o.
VCC
MODE
CONTROL
CLOCK I
R-SHIFT
GNO
CLOCK 2
L-SHIFT
POSITIVE LOGIC:
MODE CONTROL =0 FOR RIGHT SHIFT
MODE CONTROL = I FOR LEFT SHIFT -OR PARAlleL LOAD
This shift register is completely compatible with Series 54/74 TTL and DTL logic families. Average
power dissipation is typically 195 milliwatts. The
ITT5495A and ITT7495A are unilaterally interchangeable with and replace ITT5495 and ITT7495. respectively. but offer diode-clamped inputs.
improved speed. and reduced power dissipation.
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply Voltage V CC (See Note 1) ........................... 7V
Input Voltage Vin {See Notes 1 and 2) ............... 5.5V
Operating Free Air Temperature Range:
ITT5495A Circuits ........................ - 55°C to 125°C
ITT7495A Circuits ................................. ooC to 70°C
Storage Temperature Range ......... -65°C to 150°C
3-138
ITT5495A, ITT7495A
4-81T RIGHT-SHIFT !-EFT~SHIFT REGISTERS
schematic
OUTPUTQB
OUTPUTQA
OUTPUTQC
OUTPUTQO
I
I
I
I
I
•
I
Notes:
1. Register values are in ohms.
2. Component values shown are nominal.
recommended operating conditions
Min
Nom
Max
Unit
Supply VoltageV cc (See Note 1): ITT5495A Circuits .......................;.......................,.... .
ITT7495A Circuits ................................................... ..
Normalized Fan-Out From Each Output: High logic level ............................................... ..
Low logic level ..................................................
Width of Clock Pulse tp(clock) (See Figure 9): ITT5495A Circuits .................. :............ ..
ITT7495A Circuits .................................
Setup Time Required at Serial: A. B. C. or 0 inputs t setup
4.5
4.75
5
5
5.5
5.25
20
10
V
V
20
15
10
10
ns
ns
10
ns
0
ns
15
ns
15
ns
.5
ns
5.
ns
Hold Time Required at Serial. A. B. C. or 0 inputsthold
Logical 0 Level Setup Time Required at Mode Control
(With Respect to Clock 1 input) .............................................................
Logical 1 Level Setup Time Required at Mod\! Control
(With Respect to Clock 2 input) ......................................................:.... ..
Logical 0 Level Setup Time Required at Mode Control
(With Respect to Clock 2 input) .......................................................,.... .
Logical 1 Level Setup Time Required at Mode Control
(With Respect to Clock 1 input) .........................................;:................ ..
Notes:
1. Voltage values are with respect to network ground terminal.·
2. Input voltages must be zero or positive with, respect to network ground terminal.
3-139
ITT5495A. ITT7495A
4-811 RIGHT-SHIFT !-EFT-SHIFT REGISTERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Test Conditions 2
Vin (l)
Input voltage required to ensure
logical 1 at any input terminal
Vin(O)
I nput voltage required to ensure
logical 0 at any input terminal
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vee = Min Ii = -12mA
V out(l)
Logical' 1 output voltage
V
Vee = MIN. Iload =-800uA
Vout(O)
Logical 0 output voltage
0.4
V
Vee = MIN. Isink = 16mA
lin(O)
Logical 0 level input current at
any input except mode control
-1.6
mA
Vee = MAX. Vin = 0.4V
lin(O)
Logical 0 level input current at
mode control
' -3.2
mA
Vee = MAX. Vin = 0.4V
lin(l )
Logical 1 level input current at:
any input except mode control
40
ua
Vee = MAX,Vin = 2.4V
1
mA
Vee = MAX. Vin = 5.5V
Logical 1 level input ,current at
mode control
80
uA
Vee = MAX. Vin = 2.4V
1
mA
Vee = MAX. Vin = 5.5V
lin(1)
2
Unit
V
2.4
~ ~;.
lOS
Short-circ4(t output current 3
-18
-57
mA
Vee = MAX
ICC
Supply current
39
63
mA
Vee = MAX
SWITCHING CHARACTERISTICS. Vee
Parameter
= 5V.TA = 25°e. N = 10
Min
Typ
25
36
f max
Maximum shift frequency
tpdl
Propagation delay time to logical
1 level from clock 1 or clock 2
to outputs
18
Propagation delay time to logical
21
tpdO
Max
Unit
Test Conditions
MHz
eL = 15 pF. RL = 4000
27
ns
eL=15pF.R L =400n
32
ns
eL = 15 pF. RL = 4000
o level frol1l'Clock 1 or clock 2
to outputs,,:,
, All typical va lues are at Vee = 5V. TA = 25° e.
,
,:
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
,
for the particular circuit t y p e . '
3 Not more than one output should be shorted at a time.
2
3-140
-
·ITT
SEMICONDUCTORS
ITT5496, ITT7496
5-BIT SHIFT REGISTERS
-----
5-BIT SHIFT REGISTERS
TTL MSI MULTIFUNCTION SHIFT REGISTERS
·DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)-
for application as
• N-Bit Serial-To-Parallel Converter
• N-Bit Parallel-To-Serial Converter
• N-Bit ,~torage. Register
CLOCK
A
PRESETS B
Lc
All flip-flops are simultaneously set to the logical
o state by applying a logical 0 voltage to the clear
input. This condition may be applied independent
of the state of the clock input.
The flip-flops may be independently set to the
logical 1 state by applying a logical 1 to both the
preset input of the specific flip-flop and the common preset input. The Rreset-enable input is provided to allow flexibility of either setting each flip-flop
independently or setting two or more flip-flops simultaneously. Preset is also independent of the
state of the clock input or clear input.
Transfer of information to the output pins occurs
when the clock input goes from a logical 0 to a
logical 1. Since the flip-flops are R-S master-slave
circuits. the proper information must appear at the
R-S inputs of each flip-flop prior to the rising edge
of the clock input voltage waveform. The serial input provides this information to the first flip-flop.
while the outputs of the subsequent flip-flops provide'information for the remaining R-S inputs. The
clear input must be at a logical 1 and the preset
input must be at a logical 0 when clocking occurs.
CLEAR
r
This shift register consists of five R-S master-slave
flip-flops c.onnected to perform parallel-to-serial or
serial-to-parallel conversion of binary dilta. Since
both inputs and outputs to all flip-flops are accessible. parallel-in/parallel-out or serial-inlserial-out operation may be performed.
vcc
GNO
('0
01
PRESETS
ENABLE
lE
OUTPUTS
EJ
PRESET
POSITIVE LOGIC:
lii"
LOW INPUT AT CLEAR SETS
ALL OUTPUTS TO LOGICAL O.
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply Voltage VCC (See Note 1) ........................... 7V
Input Voltage Vin (See Notes 1 and 2) ............... 5.5V
Operating Free-Air Temperature Range:
ITT5496 Circuits ........................... -55°C to 125°C
ITT7496 Circuits .................................... ooC to 70°C
. Storage Temperature Range .. ,...... -65°C to 150°C
This shift register is completely compatible with Series 54/74 TTL and DTL logic families. Typically.
average power dissipation is 240 milliwatts. and
prOpagation i:lel~y time is 25 nanoseconds.
3-141
Notes: 1. These. voltage values are with respect to
network ground terminal.
2. Input signals must be zero!or positive with respect to network ground terminal.
ITT5496, ITT7496
5-BIT SHIFT REGISTERS
schematic
OUTPUT A
OU:rPUTC
OUTPUTB
OUTPUTE
OUTPUTD
.:.:,
GND
I
I
SERIA~
INPUT
PRESET' PRESET A
ENABLE
CLOCK
n
PRESET E
PRESET 0
PRESET B
(;omponant valulIS are nominal.
.recommended· operating conditions
MIN
S\lpply Voltage VCC (See Note 1): ITT5496 Circuits .................................. .
ITT7496 Circuits .................................. .
Normalized Fan Out from Output ..................................................................... ..
Width of Clock Pulse. tp(clock) ...................................................,...................... .
Width of Clear Pulse. t(clear) ...............................................................................
Width of Preset Pulse. tp(preset) ........................................................................
Serial Input Setup Time. tsetup ..........................................................................
Serial Input Hold Time. thold ..............................................................................
4.5
4.75
TYP MAX UNIT
5
5
5.5
5.25
10
35
30
30
30
0
V
V
ns
ns
ns
ns
ns
NOTE1: This voltage.value is with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Vin (1 )
Logical 1 input voltage
Min
Typ'
Max
2
Test Conditions 2
V
Vin(O)
Logical 0 input voltage
0.8
V1
Input Clamp Voltage
-:--1.5
Vout (1 )
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
2.4
Unit
3.5
V
VCC = Min Ii = -12 mA
V
VCC = MIN
V
VCC = MIN.
Iload = -400 uA
0.22
0.4
Isink = 16 mA
3~142
ITf5496,ITf7496
5-81T SHIFT REGISTERS
•
j
. '.:'
ELECTRICA!. ~HARACTERISTICS over rllcommended operating free-air temperature range
(unless QthEln.vis~ nQtlld) (~C)ntifl~e~)
....."
,;
Pa~mlt~~r
"
:"-'.:..;
'l in (1)
. '.- ":'
:.."
","
.;
;<",
Max
Typ'
l\IIin
... :: .....
Logical 1 leilel input current
at !!'1V inpu~ ~1Ic.;~p~ ,
"'~'
;
Test Conditions z
Unit
','
preset-l1na~le
~9giC~lrl~;;~ii"p.iit 9Yr?~~1 '
40
uA
Vee
i
mA
Vee
200
uA
Vee
i
mA
= MAX. Vin = 2.4V
= MAX. Vin = 5.5V
lin(O)
Logical 0 Ii!velinput"current
at any input exci;lpt
preset-enable
-1.6
mA
= MAX. Vin = 2.4V
Vee = MAX. Vin = 5.5V
Vee = MAX. Vin = 0.4V
linlO)
Logical 0 level input current
at preset-enable
-8
mA
Vee
lOS
Short-circuit output current 3
-20
-57
mA
-18
-57
mA
= MAX.
=0
Vee = MAX
lin(l)
at pre~t-enable
lee
"
Supply current
48
68
mA
48
79
mA'
= MAX. Vin =
0.4V
Vee
ITT5496
V out
ITT7496
ITT5496
ITT7496
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter
1
2
3
Min
Typ
Max
Unit
Test Conditions
= 15pF. RL = 4000
, eL = 15pF. RL = 400.n
f max
Maximum clock frequency
tpdl
Propagation delay time to
logical 1 level from clock to
output
25
40
ns
tpdO
Propagation delay time to
logical 0 level from clock to
output
25
40
ns
eL
= 15pF. RL = 4000
tpdl
Propagation delay time to
logical 1 level from preset or
preset-enable to output
25
35
ns
eL
= 15pF. RL = 4000;
tpdO
Propagation delay time to
logical 0 level froin clear to
output
55
ns
eL
= 15pF. RL = 4000
MHz
10
eL
,H;
For conditions ~hown as MIN or MAX. use the appropriate value specified'under recommended ope,r,ating conditions
for the particular circuit type.
.
All typical values are at Vee = 5V. TA = 25°e,
Not more than one output should be shorted 1.2
-50
-25
25
50
75
100
125
~
t:-...
;::
~
.0
~
Vee· ~ v
~
20
Rr
10
Ie
·80 pF
-Internal
'10
~X
r---T74121--.
o
-75
-60
+-
!--CL • '00
80
t-CL
·50.
.F
F
100
-25
0
25
50
~
TA-Fr,eoA.l, TemPirMurl- C
30
I-
RT • Internal
o
-50 -25
0
26
60
76
TA-F,..Alr TemperltUre-°C
VI
10ms
1m.
/"
~
1Jtf'
./
V'
~
.0.\ ~~
c.,;.
100~s
.../V
~
./
../V-
.oll\ ~~
I-;C~
I
.../
V
~
-"
.Jf"
".. V
(j$l9~
~
.\
.;,-
,."
lp I
V'
~
r;P9~
C~
lOOn
•
V
.../
V-
./
.\
~
.;'
~.
\0 9/
V
Vee - 5 V
TA =25°e
54121
10 ns
4
1
10
20
AT-Timing Resistor Value-kn
Unless otherwise noted data is applicable for ITI54121 and ITT74121.
3~151
40
74121~
Vee· 6 V
OUTPUT PUL.SE WIOTH
,."
~ I--
~.80pF
10
TIMING RESISTOR VALUE
"# \
--
r-
>--
20
-16
126
~
40
V
l"-
S 50 i-CL ·'6.F
c
ol!
80
70
~
l -t - V
CL -15pF
1;
-75
!
i...0
CL.~
;::
~
]
60
9 50
~
'0
~
FREE-AIR TEMPERATURE
70
>
~
>
Y1
FREE·AIR TEMPERATURE
70
100
100
125
ITT54121,ITT74121
MONOSTABLE MULTIVIBRATORS
TYPICAL CHARACTERISTICS 1
OUTPUT PULSE WIOTH
VI
EXTERNAL CAPACITANCE
L
V
lG.~
lGpF
l000pF
G.Gl~F
G.l
~F
Cr-Timing Capacitance
1
Unless otherwise noted data is applicable for ITI54121 and ITT74121
3-152
lG~F
ITT54122, ITT54123, ITT74122, ITT74123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
ITT
----SEMICONDUCTORS
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
• Retriggerable for Very Long Output Pulses.
Up to 100% Duty Cycle
PIN CONFIGURATION OF
DIP AND FLAT PACKAGE
• Overriding Clear Terminates Output Pulse
ITT541221IT T74122
• Diode-Clamped Inputs
• D-C Triggered from High- or Low-Level
Gated Logic Inputs
VCC
:: 1
• Compatible for Use with TTL or DTL
• Typical Average Propagation Delay to
Output Q ... 21 ns
ITT54123/1TT74123
Outputs
A1
A2
B1
B2
a
a
L
x
X
x
X
L
X
H
X
X
H
X
X
X
L
X
L
L
L
L
H
H
H
H
H
X
X
X
IB
,
transition from high to low level,. ~
pulse, U = one low-level pulse, X.
20
.n
=
=
Cext
10
'"
'"
VCC
I Rex"
It••,
L
L
X
H
H
U
.fL
H
L
X
t
H
L
Jl
1..r
H
X
H
t
H
L
H
X
L
H
H
U
Jl
H
L
t
H
X
lJ'
H
X
L
.Jl
t
H
.j.
J'L
U
H
H
H
H
.j.
U
11.
H
H
H
H
H
H
H
l.f
SL
t
L
X
H
H
V
X
L
H
J'L
1..r
H
Notes: A. H = high level (steady state), L = low level
(steady state). I = transition from low to high level, t =
X
NC
GND
IA
Clear
Cext
CLEAR
TRUTH TABLE-ITT54122, ITT74122
X
NC
B2
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage VCC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage, ITT54122, ITT74122
Circuits only (see Note 2) .................................... 5.5V
Operating free-air temperature range:
ITT54122, ITT54123 Circuits .... - 55°C to 125°C
ITT74122, ITT74123 Circuits ............. O°C to 70°C
Storage temperature range ........... -65°C to 150°C
Inputs
RIIII
C.x'
DATA
{
INPUTS BI
2Cex'
2 CLEAR
2 Reltt
Cut
GND
POSITIVE LOGIC: LOW INPUT TO CLEAR RESETS
TO LOW LEVEL AND INHIBITS DATA INPUTS
Q
NOTES:
one high-level
Irrelevant (any
input. including· transitions).
3-153
NC = No internal connection .
To use the internal timing resistor of ITT54122/1TT74122 (10 k!l nominal), connect
Rint to VCC'
An external timing capacitor may be connected between Cext and RexlCext (positive).
ITT54122, ITT54123, ITT74122, ITT74123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
TRUTH TABLE -ITT54123/1TT74123
Inputs
These monolithic TTL retriggerable monostable
multivibrators feature doc triggering from gated
low-level-active (A) and high-level-active (B) inputs,
and also provide overriding direct clear inputs.
Complementary outputs are provided. A full fan-out
to 10 normalized Series 54174 loads is available
from each of the outputs at the low logic level, and
in the high-level state, a fan-out of 20 is available.
The retrigger capability simplifies the generation of
output pulses of extremely long duration. By triggering the input before the output pulse is
terminated, the output pulse may be extended. The
overriding clear capability permits any output pulse
to be terminated at a predetermined time independently of the timing components Rand C.
Outputs
Clear
A
B
Q
Q
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
~
SL
_ft
lJ
lJ
t
L
H
H
J1.
V
,
=
=
Notes:·H
high level (steady state). L
low level
(steady state).' = transition from low to high
level, ~ = transition from high to low level.
I
one high-level pulse, U
one lOW-level
pulse, X = irrelevant (any input, including
transitions).
=
=
Figure A below illustrates triggering the one-shot with the high:level-active (B) inputs.
RETRIGGER PULSE
(See Notel
BINPUT
Jl~P'-----'-_--;--1
1"'·----
tw
+ tPLH
_
-I
I
.L _________ __ J. . .____
OUTPUT o J
,:...- - - - - - tw - - - - - - - . ; , OUTPUT WITHOUT RETRIGGER
OUTPUT PULSE CONTROL USING RETRIGGER PULSE
BINPUT
CLEAR
~
_______________________________________
LJ
~
OUTPUT WITHOUT CLEAR
OUTPUTo~~----------~I-_ _-__--__--__-__-__-,_:____________________________
OUTPUT PULSE CONTROL USING CLEAR INPUT
FIGURE A-TYPICAL INPUT/OUTPUT PULSES
NOTE:
Retrigger pulse must not start before 0,22 C ext (in picofarads) nanoseconds after previous trigger pulse.
3 - 154
ITT54122, ITT54123, ITT74122, ITT74123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORSWITH CLEAR
RT is in kQ (either internal or external timing
resistor)
Cext is in pF
tw is in ns
These monostables are designed to provide the system designer with complete flexibility in controlling
the pulse width, either to lengthen the pulse by
retriggering; or to shorten by clearing. ITT.54122/1IT74122 has an internal timing resistor
which allows the circuit to be operated with only
an external capacitor, if so desired. Applications requiring more precise pulse widths and not requiring
the clear feature can best be satisfied with ITT-
For pulse widths when Cext < 1000 pF, see Figure
8.
These circuits are fully compatible with most TTL
or DTL families. Inputs are diode-clamped to minimize reflection~ due to transmission-line effects,
which simplifies design. Typical power dissipation
per one shot is 115 milliwatts; typical average propagation delay time to the Q output is 21 nanoseconds. ThelTT54122 and IIT54123 are characterized for operation over the full military temperature
range of 55°C to 125°C; the IIT74122 and IIT74123 are characterized for operation from ooe to
JO°C.
54121/1IT74121.
The output pulse is primarily a function of the external capacitor and resistor. For Cext > 1000 pF,
the output pulse width (tw) is defined as:
•tw =
~ 4- Rr
0.7)
0.32 RTCext 1
where
recommended operating conditions
54122,54123
MIN
NOM
MAX
4.5
5
5.5
20
10
40t
40t
40t
5
25
SupplV voltage, VCC
Normalized fan-out from each output, N
I
I
High logic level
Low logic level
Input data setup time, tsetup (see Note 31
Input data hold time, thold (see Note 41
Width of clear pulse, tw(clearl
Extarnal timing resistance
External capacitance
Wiring capacitance at Rext/Cext terminal
Operating free-air temperature, T A
tThese conditions are recommended for use ~t V CC
NOTES:
74122,74123
NOM
MAX .
5
5.25
20
10
40t
40t
40t
5
50
MIN
4.75
No restriction
-55
::I
5 V. T A
::I
V
ns
ns
ns
kl1
No restriction
50
125
25
UNIT
0
25
50
pF
70
°c
25° C.
.
1. Voltage values, except intereminer volta'ge, are with respect" to network ground terminal.
2. This Is the voltage between: two emitters of s·multlple·emitter transistor. For the 54122/74122 circuit, this rating applies to
each A input with respect to the other and to each B input with respect to the other.
3. Setup time for a 'dynamic Input is the interval immediately preceding the transition which constitutes the dynamic input, during
which interval a steady-state logic level must be maintained at the input to ensure recognition of the transition.
4. Hold time for a dynamic input is the interval immediately following the transition which constitutes the dynamic input, duri'ng
which Interval a steady-state logic Jevel must be maintained at the input to ensure continued recognition of the transition.
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
V IL
Low-level input voltage
VI
I nput clamp voltage
V OH
High-level output voltage
Min
Typ'
Max
2
Unit
Test Conditions 2
V
2.4
3-155
O.S
V
. -1.5
V
Vee = MIN,II = -12mA
V
Vee = MIN, IOH = -SOOuA,
See Note 5
ITT54122, ITT54123, ITT74122, ITT74123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
ELeCTRICAL CHARACTERISTICS (continued)
VOL
Low-level output voltage
II
Input current at maximum input
voltage
IIH
High -level input
current
IlL
Low-level input
current
0.22
1
'3
1
mA
VCe
= MAX. VI = 5.5V
uA
VCC
= MAX. VI = 2.4V
mA
VCC
= MAX. VI = 0.4V
-40
mA
VCC
28
mA
VCC
= MAX, See Note 5
ITT54122,
= MAX.
40
80
data inputs
-1.6
clear input
-3.2
ICC
Supply current (quiescent or
triggered)
-10
23
ITT74122
46
'2
Vcc
MIN. 10L
See Note 5
data inputs
Short-circuit output current 3
= 16mA.
V
clear input
lOS
=
0.4
See Notes 6 and 7 ITT54123,
ITT74123
66
All typical values are atV cc = 5V, TA = 25°C.
For conditions shown as M IN or MAX, use the value specified under recommended operating conditions for the applicable
device type.
Not more than one output should be shorted at a time.
Notes:
5. Ground Cext.:0 rTjeasure VOH at Q, VOL at IT, or lOS at Q, Cext is open to measure V OH at 5, VOL at
Q, or lOS at Q.
6. Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs. B inputs grounded.
all outputs open.C ext
0.02uE. and Rext
25kn. Rint of ITT54122. ITT7 4122 is open.
7. ICC is measured in the triggered state with 2.4V applied to all clear and B inputs. A inputs grounded, all
outputs open. Cext
0.02uF. and REXT
2Sk!1. Rint of ITT54122.ITT74122 is open.
=
=
=
=
SWITCHING CHARACTERISTICS. Vce = 5V; TA = 25°e. N = 10
Parameter
Min
Typ
Max
Test Conditions
Unit
=
=
= Sk!} ..
= 4000
=
=
= Skn.
= 400 n.
tpLH
Propagation delay time.
low-to-high-Ievel Q output. from
either A input
22
33
ns
Cext
O. Rext
CL
1SpF. RL
tpLH
Propagation delay time.
low-to-high-Ievel Q output. from
either B input
19
28
ns
Cext
O. Rext
CL
15pF. RL
tpHL
Propagation delay time.
high-to-Iow-Ievel Q output. from
either A input
30
40
tpHL
Propagation delay time,
high-to-Iow-Ievel Q output. from
either B input
27
tpHL
Propagatton delay time.
high-to-Iow-Ievel Q output. from
clear input
18
3-156
ns
Cext - O. Rext - 5kQ
CL
1SpF. RL
400 Q
36
ns
Cext
O. Rext
CL
1SpF. RL
27
ns
Cext
O. Rext
CL
1SpF. RL
=
=
=
=
= SkQ
= 400 Q
=
=
= SkQ
= 400 Q
ITT54122, ITT54123, ITT74122, ITT74123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
SWITCHING CHARACTERISTICS, VCC
Parameter
= 5V. TA = 25°C. N = 10
Min
Typ
(continued)
Max
Unit
Test Conditions
=
=
=
=
=
= 5k{1
= 400 n
tpLH
Propagation delay time.
low-to-high-Ievel Q output. from
clear input
30
40
rs
Cext O. Rext == 5k{!
CL
15pF. RL
400
tw(min)
Minimum width of Q output
pulse
45
65
ns
Cext
O. Rext
CL
15pF. RL
tw
Width of Q output pulse
3.42
3.78
ns
Cext = 1OOOpF. Rext = 10k
CL
15pF. RL
400
3.00
=
=
n
TYPICAL APPLICATION DATA.' .
OUTPUT PULSE WIDTH
vs
EXTERNAL TIMING CAPACITANCE
10000
7000
n
VCC
VCC - 5 V
FIGURE C
TA=25°C
4000
,/
2000
~
I
-5
1000
700
~
51
400
'0
:;
11-
:;
e
~
0
I
J
200
100
70
~
-
~
.<:J
\
~~> ,>o't-Q.
~~. ').o't-Q.
-
~~",,~o~
0
/1/
/'
Tcext
~
w(
,:>'t-~
40
To Rext/Cext
terminal
terminal
TIMING COMPONENT CONNECTIONS WHEN Cext <; 1000 pF
20
10
To Cext
2
4
10
20
40
100 200 400
Vec
1000
Cext-External Timing Capacitance-pF
FIGURE D
FIGURE B
t
Rext ~ 0.6 Rext max.
(See recommended operating
These values of resistance exceed the maximums recommended for use over the full temperature range of
the ITT54122 and ITT54123.
conditions for R ext max.)
Any silicon switching diode
such as 1N3064, etc.
To Cext
To Rext/Cext
terminal
terminal
TIMING COMPONENT CONNECTIONS WHEN
Cext > 1000 pF AND CLEAR IS USED
To prevent reverse voltage across Cext ' it is recommended that the method shown in Figure 0 be
employed when using electrolytic capacitors and in
applications utilizing the clear function. In all applications using the diode. the pulse width is:
tw
where
3 -157
= 0.28 RextCext
n
Rext is in k
Cext is in pF
tw is in ns
~ +-1
0.7)
Rext
~
ITT74124
ITT _________
U_N_'V_E
..R
...S_A_L_PU_LS_E_G_EN_ER_A_T_O_R
SEMICONDUCTORS
DUAL- IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
UNIVERSAL PULSE
GENERATOR
~
• Delayed Pulse Generator.
<>
INTR} TIMING
EXT C CIRCUIT
EXT R
2
INT R
Controllable high stability oscillator.
NEGATIVE
TRIGGER
EXT C
POSITIVE
TRIGGER
Q20UTPUT
Q,OUTPUT
02 OUTPUT
.. Applications include clock generator, Timing
pulse generation, Synchronized oscillator,
and pulses frequency divider.
o Outputs available from the two incorporated
Cascade Monostables.
<>
VCC
TIMING { : : :
CIR9UIT
EXT R
INHIBIT OSC.
INPUT
GND
No jitter self start.
PIN CONFIGURATION (top view)
., Complete output waveforms.
" Positive Schmitt Trigger input.
" Delays and pulse widths from 35 ns to 40
second.
-
FEEDBACK CONNECTION
~O--"""'-=j
POSITIVE
TRIGGER
LOGIC DIAGRAM
6
1
\
~3
EXTERNAL e, R
EXTERNAL e
9
10
II
12
13
\ . .... EXTERNAL etR
EXTERNAlC
TRUTH TABLE
Inputs
Mode
Outputs
During Time Period:
T2
INH
OSC
POS NEG
TRIG TRIG
OSCILLATOR
MODE
1
1
0
X
X
1
DELAYED
PULSE
MODE
0
t
0
J"1..
0
1
t
J"1..
..n...
..n...
l.J
0
0
1
STABLE
STATE MODE
ALL OTHER
LEVELS
Tl
01
02
02
JI.. JI.. -UJI.. ..n... ""Lr
"1J""
Notes:
t =
Transition from 0 to 1.
Tra nsition from 1 to O.
X = Indicates that O. 1 or any transition may be present.
+=
...n..=
1 level pulse of width = timing period T 1 or T2·
1-f= 0 level pulse of width = timing period T2.
Timing period T 1 set by timing,circuit 1.
Timing period T 2 set by timing circuit 2.
3-158
ITT74124
UNIVERSAL PULSE GENERATOR
ElECTRICAL CHARACTERISTICS AND
RECOMMENDED OPERATING CONDITIONS
Propagation delay, trigger input to 0, ............. .43 ns
Inhibit Oscillator input to 0, ............................ 26 ns
0, to 02 ...................... :....................................... 15 ns
Power dissipation (50% duty cycle) ............. 1 50 mW
Input loading factor ................................... 1 Unit load
Maximum fan out.. .................................. 10 unit loads
External timing resistor, RT ....................... 1.4 kDmin
(54124 25K max.) 50 kDmax.
External timing capacitor, GT ....................... 0 pF min.
50 uF max.
Recommended maximum
output frequency ........................................... 10M Hz
Recommended input pulse width:
Inhibit Oscillator input ............................ ,.... 15 ns min.
Trigger input ................................................. 50 ns min.
Trigger input setup time ....................................... 10 ns
Maximum mark space ratio:
RT = Max. Value ............................................. 100: 1
RT = Min. Value ................................................... 5: 1
Output pulse width ................................... 0.695 GTRT
Timing Stability:
Typical Timing period change
with supply voltage .............................. 0.2% per Volt
Typical Timing period change
over 0° to 75°G Temperature range ............ 0.15%
The ITT 74124 Universal Pulse Generator has
been designed specifically for clock and delayed
pulse generation applications. This versatile device
incorporates two cascaded monostable circuits to
provide the delayed pulse facility and a gated feedback path allows its operation as a controllable high
stability oscillator. The external timing components
which control the delay and pulse width periods in
the delayed pulse generator mode are used to determine the oscillator mark - space ratios (duty cycle). The true output. 0, from the first monostable
and true and complements outputs, 02 and 02
from the second monostable are provided. These
outputs are of standard totem pole configuration
and provide a maximu m fan-out of 10 T.T.l. loads.
Delayed Pulse Generator Mode
When operating in the delayed pulse mode the
feedback loop is inhibited by maintaining the inhibit
oscillator input at '0'. The device can then be triggered from the positive edge trigger input with the
negative edge input held at '0', or from the negative
edge trigger input with the positive edge trigger in-
put held at '1'. The positive trigger input incorporates a Schmitt trigger circuit for slow edges or level detection. Once triggered further transistions on
the inputs have no effect on the 01 output pulse
until after the first monostable timing period is
completed. The second. monostable is triggered
from the first monostable output pulse by. its trailing
edge and is not effected by any further transistions
from the first monostable until its timing period is
over. The output of the second monostable is therefore a single pulse having .a width determined by
the time-constant of the second monostable and
which is delayed from the initiating input trigger
edge by the time constant of the first monostable.
Oscillator (Astable Multivibrator) Mode
The feedback path is operative when the inhibit oscillator input is taken to logical ',', and for operation
in the oscillator mode the positive trigger input
and/or the negative trigger input must be maintained at '1'. The feedback path enables the trailing
edge from the second monostable to retrigger the
first monostable to maintain the oscillations. As
soo.n as the inhibit oscillator input is taken to logical
'0', the device reverts to its delayed pulse mode and
the oscillations stop when the second monostable
timing period is over. In this way only whole cycles
are produced. It is a feature of the design that a
locked-up state, preventing the circuit from oscillating, cannot occur. The first monostable is immediately triggered on application of '1' to the inhibit oscillator input with the correct trigger input
levels, and will not lock-up when the supplies are
switched on with the correct input signals applied.
By virtue of the inhibit oscilliltorinput it is possible
to gate the oscillator on and off to produce bursts
of pulses. It is also possible to synchronize the oscillator by applying appropriate waveforms at the
inputs. This facility allows for its use as a pulse frequency divider.
The time period for the first monostable, which determines the pulse width from the 01 output and
the delay before the pulse from the 02 and 02 outputs begins, is set by the timing circuit on pins 1,
2, and 3. The time period for the second
monostable determines the pulse width obtained
from the 02 and 02 outputs is set by the timing
components connected to pins 11, 12, and 13. The
timing components may be connected as follows:
3 -159
ITT74124
UNIVERSAL PULSE GENERATOR
a. External timing capacitor. CT, may be connected between pin 1 (11) positive and pin 2 (12).
With no external capacitance an output pulse
width of typically 25 ns is obtained with RT
= 1.5K,Q,+10Kil
b. To use the internal timing resistor (normally
7.2K.Q) connect pin 3 (13) to VCC (pin 14).
The pulse width or time delay is approximately
given byt
5 X 103 CT'
c. To obtain variable resistor between pin 3 (13)
and V CC (pin 14). Add the value ofthe internal
resistor. 7.2K,Q to the external resistance
used, to obtain the RT value.
d. For accurate timing connect an external resistor
between pin 2 (12) and VCC (pin 14). Leave
pin 3 (13) open circuit.
Relationship for timing period, t = 0.695
CTR T where CT and RT are the timing components values used.
Note: Timing periods of the order of one second
are obtained when using the maximum recommended RT and CT component values.
=
1/ Delayed Pulse Mode
a) Timing Period T1
»
Timing Period T2 (inhibit
22
bl Timing Period T1
I!p
~LJ
Qj
~I
«
=negative trigger" '0'1.
LIl
l2
n
a
IL-
U
n
U-
Timing Period T2.
It--u
n
n
2Z
U
~
__
~rl~
________________
~l
02
02
a
2/ Oscillating Mode
a) Timing Period T1
INHIBI~
=Timing Period T2 (positive trigger = '0').
l~'"l:-l--'--'
~--~~:r-~
_--..J1LJLJLj"-Ul
l~:l:-l__~I-UU---U-U---
--LnJ~~
bl Timing Period Tt«
Timing Period T2.
--1------
----'L ..- - I L_ _.__----'
_____---.r-
~
LJ
Waveforms illustrating the function of the circuit in the delayed pulse and oscillating modes.
3-160
ITT74124
UNIVERSAL PULSE GENERATOR
ELECTRICAL CHARACTERISTICS. over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Typ
Min
,
Max
Unit
VT +
Positive edge threshold
Voltage at trigger input (positive)
VT
Negative edge threshold
Voltage at trigger input (positive)
0.8
V IH
High-level input
voltage
2
V il
low-level input
voltage
0.8
V
VI
I nput clamp voltage
-1.5
V
V OH
High-level output
voltage
1.75
2
1.4
Test Conditions
=
V
1000 pf
5V eT
10KD.
RT
V
5V eT
1000 pf
RT
10 KD.
=
=
=
V
2.4
3.4
V
= MIN, II = -12mA
Vee = MIN,
Vee
10H
= -400uA
= MIN,
= 16 rnA
0.4
V
Vee
10l
Input current at
maximum input
voltage
1
mA
Vee
= MAX, VI = 5:5V
IIH
High-level input
current
40
uA
Vee
= MAX, VI = 2.4V
III
low-level input
current
-1.6
rnA
Vee
= MAX, VI = O.4V
lOS
Short-circuit output
current 3
-55
mA
Vee
= MAX
ICC
Supply current. Input high
30
60
mA
Max) eT
= 1000 pf
ICC
Supply current, Inputs low
30
60
mA
Max) RT
= 10 KD.
VOL
low-level output
voltage
II
M KS mark space ratio (duty
cycle)
0.2
-18
90.1
100.1
RT = max, value minimum
space width = 100 ns with 5')(
degradation in pulse w.idth set
at equal mark space ratio.
, All typical values are at Vee = 5V, T A = 25°C.
Forconditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions
for the applicable type.
3 Not more than one output should be shorted at a time.
2
3- 161
ITT 74124
UNIVERSAL PULSE GENERATOR
SWITCHING CHARACTERISTICS. Vee
Parameter
Tpd +
From
From
From
From
From
From
Tpd -
From Q2 to Q2
From Q 1 to Q2
tpo
Output pulse width
CT = Opf, RT = 1.5n~10Kn
CT = 100 pf, RT = 10Kn
CT = 1 uf, RT ~ 10Kn
1
Tmin ,
= 5V, TA = 25°e
Min
Inhibit Oscillator to Q1
Neg Trigger to Q 1
Pos Trigger to Q 1
Q 1 to Q2
Q 2 to Q2
Q2 to Q 1
Minimum width pulse into:
Trigger Inputs
I nhibit Oscillator
T set-up
600
6
Typ
Max
Unit
26
45
40
15
15
18
50
85
75
30
30
35
ns
ns
ns
ns
ns
ns
Use Test
Use Test
Use Test
Use Test
Use Test
Use Test
8
20
15
45
ns
ns
Use Test Circuit Or 100 pf
Use Test Circuit CT 100 pf
25
700
7
35
800
8
ns
ns
ms
Use Test Circuit
Use Test Circuit
Use Test Circuit
30
10
50
15
10
ns
ns
ns
Use Test Circuit
Use Test Circuit
Use Test Circuit
Test Conditions
Circuit
Circuit
Circuit
Circuit
Circuit
Circuit
CT
CT
CT
CT
CT
CT
100
100
100
100
100
100
pf
pf
pf
pf
pf
pf
T min = The hold time which is the interval immediately following the trigger transition, during which
interval the.input must be maintained at the steady state level shown in the Truth Table to ensure correct
operation. Applied to the inhibit oscillator input. tmin' is the minimum input pulse '!"idth required to ensure
the generation of one period of oscillator, with the other inputs at the logic levels given in the truth
table.
Test Circuit
cc
'_~_
V _____ ,
I
:
02 OUTPUT :
''tL'4OQC
•
:
IN4!"IB :
~11..,,:;pF
-;;-
f"'------'--+L--'_ :.. ~O!~C~C~T~ ___
Qi
:; pos
OUTPUT
-1
r----------- -,
0,1'-'_ _ _9,---,:- - 01 OUTPUT
TABLE
8 'IIIHI9.
csc.
I
J
~
I
~oA;-c7Ra:,;:r;- -
___
-
~S~E~'2.... _ _ -l
LOAD CIRCUIT 3
L ___
!..:A~E~!..!I____
1
J
T pd Voltage Waveform
Note:
3-162
1. T pd + Q 2 output to Q 1 output progagation
delay when in the oscillatory mode, apply input logic levels as shown in the Truth Table.
ITT74124
UNIVERSAL PULSE GENERATOR
I ""., I
. "
A-~Z".7r.::iJr>.~
,1I,,"
O.7VP...___
I
II_
S.!lV
II..._ _ _ _ _ _ _ _ _ _ _--".;..
t MI.
I·
I
•I I...., . ,I
-~~
Voltage Waveforms for
set-up and pulse width tests .
ActI"IY\t,or V, ...._
.kr,.-~V---'.~-"~ - - -- - - -- --- --- - - -- ~V-
...:Q:.:.,.::
..c.;Q::JC'-_ _ _
I...
.1
~.!5V
I•
l'
~"_""'rl/,
~1.5V
,.!I~'--------V-OI-r-------VOI...;.;;.
_~..:2~_ _ _ _-.. 100--1,. - - I
~.5V
'See note.3
Note:
2. The Pu Ise generator characteristics are:
Amplitude = 3.5V ....................... PRF = 1 MH
tr = 10 ns ......................................... Zo = 50
t f = 4 ns ................................. ~ = 10 to 50 ns
n
Note:
3. Use the waveforms given for triggering from
the positive trigger input. Apply the inverse
of both waveforms for triggering from the
negative trigger transition (active input =
negative trigger input). Ground the inhibt oscillator input for testing the delayed pulse
mode of 0 peration.
A positive pulse should be applied to the inhibit oscillator input to test for t min in the
oscillato ry mode of operation.
"ott
1.5Vf-___ 'toL
APPLICATION NOTES
The universal pulse generator has been specifically
designed for clock and delayed pulse generation.
However. full use can be made if .its two modes
of operation to perform functions previously requiring many logic devices in a wide variety of logic
circuits. for example in timing pulse generation
where several monostables and gates are employed. The following application notes show a
selection of these applications to illustrate some
useful features of the device.
INTENSITY MODULATOR
Modulation of the intensity of seven segment indicators driven from decoder/drivers can be easily
achieved using the universal pulse generator. Using
variable timing components the duty cycle of the
modulating waveform from the pulse generator can
be altered to adjust the indicator brightness. The
indicators can be run at full intensity by taking the
inhibit oscillator input of the pulse generator to
zero. Appropriate input waveforms can be applied
to the pulse generator to gate the indicators from
full or reduced intensity.
tTT74~
"-
~ = R£CUCEDIHTENSITY
hM.Tl\Ilt3"AT~
AS
S.!lV
__________________ 2..v_
~l
OR LOGICAl. '0' =FULL INTENSITY
DtCOC£PlDRlYERS
IptTENSfTYMOOULA~R: Typical Arrangement For The Intensity Modulation of Seven - Segment Il)dicators
3-.163
· ITT74124
UNIVERSAL PULSE GENERATOR
LONG TIMING PERIODS
GENERAL PURPOSE APPLICATIONS
It is possible to use large timing capacitors up to
1.000)1 to produce timing periods up to about 40
seconds. However. the recommended maximum
timing capacitor of 50Jlf has been set to permit precise operation and good stability from the universal
pulse generator (timing periods to 1 second).
Several problems occur when using very large capacitors. The relative high leakage current of electrolytics makes accurate timing difficult and the
normal operation of the pulse generator cannot be
guaranteed with very long timing periods. However.
for some general purpose application;; large timing
cc!pacitors may be used up to 1.000pf. A settling
down period after switch-on of the supply is recommended. The maximum mark-space ratio will
also depend upon the timing peri'od length.
ACCURATE LONG TIMING PERIOD
An arrangement which takes advantage of the high
stability of the pulse generator when using lower
capacitance values is shown below.
used to preset the counter to a state depending on
the preset data input. The long delay can therefore
be varied using the preset data inputs. The carry
output also resets the input latch so inhibiting
further output pulses from the pulse generator.
Very long delays can be obtained by cascading the
counters using the same basic carry output arrangement from the last counter. In calculating
delays the ripple delay from cascaded counters'
must be taken into account.
By incorporating an additional latch in the circuit
the same basic arrangement can be used to produce short delay and long pulse outputs.
FREQUENCY SYNCHRONISM
By applying appropriate waveforms to the pulse
generator inputs as determined from the device operation modes the output frequency can be synchronized to an input frequency (usually a multiple
of the output frequency desired). The range of synchronism is dependent on the ratio of the input and
output frequencies. the ratio of the two timing periods the input mark-space ratio and any restric-
TIll'''' ClIlCUITS
PllESEJ" DATA
~
''IIlln"
SIGNAL
AP1'l..It!D
ACCORDINGTD
DELAY REQUI
1J
Typ,cal' Arrangement for Long Timing Periods Short Pulse Obtained After Long Delay.
The universal pulse generator is used in its oscillator mode with the output pulses counted by the
programmable counter. A start signal initiates the
train of pulses which causes the counter to advance
to its highest state. The next input clock pulse appears at the carry output with the same pulse width
and this is the desired output pulse of duratiori
equal to the second timing period of the universal
pulse generator. The delay time period depends
primarily on the period of the output from the pulse
generator anp trie initial preset state of the
programmable counter.
In the arrangement shown the counter output is
tions such as minimum input pulse widths.
Equal mark-space output waveforms can be obtained using an additional flip-flop toggled from the
pulse generator output.
EXAMPLE Pulse Frequency Divider.
Basically the universal pulse generator should be
arranged to give the desired output frequency and
short positive pulses applied to the inhibit oscillator
input at a frequency slightly slower than some mul- '
tiple of the natural frequency of the device. Output
waveforms of a frequency division of the input
pulse frequency can be obtained i.e. + 10. +
1 .5. + 2/3 etc.
3-164
__ I
mm
_L_L
ITT54130. ITT74130. ITT54131. ITT74131
QUAD 2-INPUT AND BUFFERS
________________W
__IT_H_O_P_E_N_C_O_L_L_EC_T_O_R_O
__
UT_P_U_T
SEMICONDUCTORS
QUAD 2-INPUT AND BUFFERS
WITH OPEN COLLECTOR OUTPUT
•
•
•
DUAL-IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
High Current and High Voltage Drivers
Inputs Are Compatible With All Other 74
Series Devices
.
Large Wire-AND Capability
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) .................................... 5.5V
Output voltage (see Notes 1 and 2):
ITI54130. ITI7 4130 ........................................... 30V
ITT54131.ITI74131 ........................................... 15V
'Operating' free-air temperature range:
ITI54130.ITI54131 ................... -55°C to 125°C
ITI74130.ITI74131 ............................ ooC to 70°C
Storage temperature range ........... - 65°C to 150°C
Notes:
1. Voltage values are with respect to network
ground terminal.
2. This is the maximum voltage which should
be applied to any output when it is in the
off state.
POSITIVE
LOGIC:
i!= A . B
Circuit Schematic,
r---~------'--oVcc
A
0--.--'
B
IK
One gate only shown
recommended operating conditions
ITT54130.ITT54131 ITT74130.ITT74131
Min Nom
Max
Min Nom Max
4.5
Supply voltage Vee
Output voltage. V OH
5
5.5
4.75
5
Unit
5.25
V
ITT54130. ITT74130
30
30
V
ITT54131.ITT74131
15
15
V
100
100
rnA
70
ae
Low-level output current. IOL
-55
Operating free-air temperature range. TA
3-165
25
125
0
25
ITT54130, ITT74130, ITT54131, ITT74131
QUAD 2-INPUT AND BUFFERS
WITHUPEN COLLECTOR OUTPUT
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
V IH
High-Iellel input voltage
V IL
Low-level input·voltage
0.8
V
V1
Input Clamp Voltage
-1.5
V
VCC = MIN. Ii = -12mA
High-level output current.
250
uA
Vec = MIN. VI = 2V.
V OH = MAX
Low-level output voltage
0.4
V
VCC = MIN. VI = 0.8V.
IOH
VOL
9
2
V
IOL = 100mA
H ig'h-Ievel input current (each
input)
40
uA
Vec = MAX. VI = 2.4V
1
mA
VCC = MAX. VI = 5.5V
IlL
Low-level input current (each
input)
'-'-1.6
mA
VCC = MAX. V I = O.4V
ICCH
Supply current. high-level output
12
24
mA
VCC = MAX. VI = 5V
ICCL
Supply current. low-level output
47
75
mA
VCC = MAX. VI = 0
IIH
SWITCHING CHARACTERISTICS, Vee
Parameter
= 5V. TA = 25°e. N = 10
Min
Typ
Max
Unit
Test Conditions
tpLH
Propagation delay time.
low-to-high-Ieveloutput
18
ns
CL= 15 pF. RL = 500
tpHL
Propagation delay time.
high-to-Iow-Ievel output
35
ns
CL = 15 pF. RL = 50n
, All typical .-alues are at V CC = 5V. T A = 25°C.
For conditions shown as MIN or JYlAX. use the appropriate value specified under recommended operating conditions
forthe applicable device type
.
2
3.,--166
O&:D
ITT
_
ITT54135, ITT54137,ITT74135,
QUAD 2-INPUT
NAND SCHMITT
HEX INVERTER SCHMITT
_
_
ITT74137
POSITIVE,
TRIGGER,
TRIGGER
__
SEMICONDUCTORS
QUAD 2-INPUT
POSITIVE NAN D
SCHMITT TRIGGER,
ITT54/74135
DUAL-IN- LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)!
1
HEX INVERTER
SCHMITT TRIGGER
High Input Impedance - Input Directly
Compatible With 74L
G Applications Include Pulse Shaping, Clock
Generation, and Interfacing to T.T.l. From
74L, T.T.L .. D.T.l., M.O.S., H.l.l. and High
Voltage Transducers
-'---t--.......---<> V C C
A o..--i'IIr--.
INPUT
t:
BO+-..-Ie-......
OUTPUT
'--+--~---~---'l----------O
Circuit Diagram
ITT54174137
A 01--llt-...
INPUT
3-169
G NO
ITT74137
POSITIVE,
TRIGGER,
TRIGGER
ITT
-SEMICONDUCTORS
ITT54138, ITT74138, ITT54139, ITT74139
QUAD 2-INPUT OR BUFFER
WITH OPEN COLLECTOR OUTPUT
-~~~-
QUAD 2-INPUT OR BUFFER
WITH OPEN COLLECTOR OUTPUT
•
•
•
DUAL-IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
High Current and High Voltage Drivers
Inputs Are Compatible With All Other 74
Series Devices
Large Wire-AND Capability
VCC
18
3A
38
4A
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage Vee (see Note 1) ........................... 7 V
Input voltage (see Note 1) ................................... 5.5 V
Output voltage (see Notes 1 and 2):
ITT54138. ITT74138 .......................................... 30 V
ITT54139, ITT74139 .......................................... 15 V
Operating free-air temperature range:
ITT54138, ITT54139 ................... -55°C to 125°C
ITT74138, ITT74139 ............................ O°C to 70 0 e
Storage temperature range ........... -65°C to 1500 e
Notes: 1. Voltage values, are with respect to network
ground terminal.
2. This is the maximum voltage which should
be applied to any output when it is in the
off state.
POSITIVE
A 0--.,--'
B
One gate only shown
Supply voltage Vee
54138. 54139
Min Nom Max
741 38. 741 39
Min Nom Max
4.5
4.75
5
5.5
5
Unit
5.25
V
ITT54138, ITT74138
30
30
V
ITT54139, ITT74139
15
15
V
100
mA
70
°c
Low-level output current, IOL
Operating free-air temperature range, TA
i! = A+8
Circuit Schematic
recommended operating conditions
Output voltage, VOH
LOGIC:
100
-55
3-170
25
125
0
25
ITT54138, ITT74138, ITT54139, ITT74139
QUAD 2-INPUT OR BUFFER
WITH OPEN COLLECTOR OUTPUT
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
Min
Typ'
Max
2
Unit
Test Conditions 2
V
V IL
Low-level input voltage
O.S
V
VI
Input Clamp Voltage
-1.5
V
VCC= MIN,II"" -12m~
IOH
High-level output current
250
uA
VCC = MIN, VI = 2V,
V OH =MAX
VOL
Low-level output voltage
0.4
V
VCC = MIN, VI = O.SV
IOL = MAX
IIH
High-level input current (each
input)
40
'uA
VCC = MAX, VI = 2.4V
1
mA
VCC~ MAX, VI = 5.5V
IlL
Low-level input current (each
input)
-1.6
mA
VCC = MAX, VI = a.4V
ICCH
Supply current. high-level output
30
42
mA
VCC'7 MAX, VI = 0
ICCL
Supply current, low-level output
27
38
mA
VCC = MAK VI = 5V
SWITCHING CHARACTERISTICS. Vee = 5V, TA = 25°e
Parameter
Min
TVP
Max
Unit
Test Conditions
tpLH
Propagation delay time,
low-to-high-Ieveloutput
16
ns
CL = 15pF, RL = 50n
tpHL
Propagation delay time,
high-to-Iow-Ievel output
35
ns
CL = 15pF, RL = 50n
':',
, All typical values are at V CC = 5 V, TA = 25°C.
2 For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
"
3 -171
ITT
----ITT74141
BCD-TO-DECI MAL D ECOD ER/D RIVER
SEMICONDUCTORS
BCD-TO-DECIMAL DECODER/DRIVER
• Drives gas-filled cold-cathode indicator tubes
directly
• Fully decoded inputs ensure all outputs are
off for invalid codes
.Input clamping diodes minimize transmission-
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
line effects
• Power dissipation typically 55 mW
logic
TRUTH TABLE
Input
0
C
B
A
Output
On'
L
L
L
L
0
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
.4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
L
L
L
8
H
L
L
H
9
H
L
H
L
NONE
H
L
H
H
NONE
H
H
L
L
NONE
H
H
L
H
NONE
H
H
H
L
NONE
H
H
H
H
NONE
INPUTS~
VCC
=
=
H high level. L low level
, All other outputs are off
INPUTS{:
2
OUTPUT
POSITIVE LOGIC: SEE TRUTH TABLE
IplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE
SAME FOR ALL PACKAGES.
The ITT74141 is a second-generation BCOto-decimal decoder designed specifically to drive
cold-cathode indicator tubes. This decoder demonstrates an improved capability to minimize switching transients in order to maintain a stable display.
Full decoding is provided for all possible input
states. For binary inputs 10 through 15. all the.outputs are off. Therefore the ITT74141. combined
with a minimum of external circuitry. can use these
invalid codes in blanking leading- and/or trailingedge zeros in a display. The ten high-performance.
n-p-n output transistors have a maximum reverse
current of 50 microamperes at 55 volts.
3-172
ITr74141
BCD-TO-DECIMAL DECODER/DRIVER
Low-forward-impedance diodes are also provided
for each input to clamp negative-voltage transitions
in order to minimize transmission-line effects. Power dissipation is typically 55 milliwatts. The ITT74141 is characterized for operation over the temperature range of OOC to 70°C.
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
SUpply voltage V CC ................................................... 7V
Input voltage (see Note 1) .................................... 5.5V
Current into any output (off-state) ..................... 2 mA
Operating free-air temperature r~nge .. O°C to 70°C
Storage temperature range ........... - 65°C to 150°C
Min
recommended operating conditions
Supply voltage Vee (see Note 1) .......................................................................................
Output voltage (see Notes 1 and 2) ...................................................................................
Operating free-air temperature range ...............................................................................
Notes:
Nom Max
4.75
5
0
25
5.25
65
70
Unit
v
V
.. °e
1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the off state.
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
.
Parameter
Min
Typ'
Max
VIH
High-level input voltage
V IL
Low-level input voltage
0.8
V
VO(on)
On-state output voltage
2.5
V
VO(off)
Off-state output voltage for input
c9unts 0 thru 9
10(0ft)
Off-state reverse current
10(0ft)
IIH
2
Test Conditions 2
Unit
V
V
= MIN. 10 = 7mA
Vee = MAX. 10 = 0.5mA
50
uA
Vee
Off-state reverse current for
input counts'l 0 thru 1 5
5
uA
High-level input current at A
40
uA
1
mA
60
Vee
= MAX. Va = 55V
Vee = MAX. Va = 30V
High-level input current at B. e.
orO
80
uA
1
mA
IlL
Low-level input current into A
-1.6
mA
IlL
Low-level input current into B. e.
or 0
-3.2
mA
= MAX. VI = 2.4V
Vee = MAX. VI = 5.5V
Vee = MAX. VI = 2.4V
Vee = MAX. VI = 5.5V
Vee = MAX. VI = 0.4V
Vee = MAX. VI = 0.4V
lee
Supply current
25
mA
Vee
IIH
16
Vee
= MAX
, This typical value is at Vee = 5V. TA = 2 soe.
.
2 For conditions shown as MIN or MAX. use the appropriate value specified underrecommended operating conditions.
3-173
ITT74141
BCD-TO-DECIMAL DECODER/DRIVER
functional block. diagram
A
(3)
{>-
1"\
n==rrL>
( 16)
.-
~
( 15)
V
1\
B
(8)
r,t-
(6)
1
2
~
d
~ f-
f
(9)
Y
( 13)
r,l'
~
~
f
c
o
f" (14)
V
(7)
--'
n
( 11 )
3
4
5
6
"
~
(10)
V
-~
(1)
7
8
"t'
D
(4)
rr.
1 J'"
Y
3-174
(2)
9
=
ITT
ITT54150, ITT54151, ITI74150, ITT74151
DATA SELECTORS/MULTIPLEXERS
-~--===~""""""""
SEMICONDUCTORS
[DATA
SElECTORS/MUlT~PlEXERS
features
ITT54151/ITT74151
o selects one-of-sixteen (or one-of-eight) data
sources
o serves as a five-variable~function generator
(ITT54150.ITT74150)
o performs parallel-to-serial conversion
o permits multiplexing from N lines to 1 line
o input-clamping diodes simplify system design
o typical propagation delay times:
through 4 select levels - 28 ns
through 3 select levels - 20 ns
data input to output -10 n s
o high fan-out. low impedance. totem-pole
outputs
o fully compatible with TTL. DTL and other
MSI circuits
Each
of
these
monolithic.
data
selectors/multiplexers contain inverter/drivers to supply
fully complementary. on-chip. binary decoding data
selection to the AND-OR-INVERT gate. The ITT54151 /ITT7 4151 features complementary outputs
whereas the ITT54150/ITT74150 has inverted outputs only. The circuits are provided with a strobeinput which. when taken to a logical O. enables the
function of these multiplexers.
DUAL-IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)'
VCC
DATAJ:
INPUTS1~
5} INPUT
DATA
6
oow~,{
7
)
DATA
STROBE
:
GND
SELECT
r =s-+---.---+----'
I
A
OUTPUT
o
I
I
I ~~~~C~~ ~:T~~
I
I
I
jj
' - - . -.....- 0 GND
L ______ _ _ _ _ _ _ _ _ J
OUTPUT
1
OUTPUT
15
TO OUTPUT
GATES 0·15
Note:
Component values shown are nominal.
3-187
ITT
----------ITT54155, ITT54156, ITT74155, ITT74156
DUAL 2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS
SEMICONDUCTORS
DUAL 2-LINE-TO-4-lINE
DECODERS/DEMULTIPLEXERS
~------------------------~
• Applications:
Dual 2-to-4-Line Decoder
Dual 1-to-4-Line Demultiplexer
3-to-8-Line Decoder
1 -to-8-Line Demultiplexer
• Individual Strobes Simplify Cascading for
Decoding or Demultiplexing Larger Words
• Input Clamping Diodes Simplify System Design
• Choice ~f Outputs:
Totem Pole (ITT54155. ITT74155)
Open-Collector (ITT54156. ITT74156)
• Typical Average Propagation Delay
Times:
16 ns through 2 levels of logic
21 ns through 3 levels of logic
• Typical Power Dissipation ... 125 mW
These monolithic transistor-transistor-Iogic (TTL)
circuits feature dual 1-line-to-4-line demultiplexers
with individual strobes and common binary-address
inputs in a single 16-pin package. When both sections are enabled by the strobes. the common
binary-address inputs sequentially select and route
associated input data to the appropriate output of
each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1 C is inverted at its outputs and data applied at 2C is not inverted through
its outputs. The inverter following the 1C data input
permits use as, 3-to-8-line decoder or 1-to-8-line
demultiplexer without external gating. See typical
applications data and ,the truth tables for more details.
The ITT54155/1TT74155 circuits. with totem-pole
outputs. are rated to fan-out to 10 normalized Series 54174 loads in the low-level output state. and
to 20 loads in the high-level output state. The ITT54156/1TT74156 circuits. with open-collector outputs. are rated to sink 16 milliamperes at a lowlevel output voltage of less than 0.4 volt. Inputclamping diodes are provided on all of these circuits
to minimize transmission-line effects and simplify
system design. Typical power dissipation is 125
milliwatts. Typical average propagation delay times
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
,
DATA
Ie
Vcc
STRDBE
IG
DATA
2C
SELECT
INPUT
STROBE
r
SELECT
INPUT
A
2G
B
ll3
1l!2
l
OUTPUTS
2i!
l
3
li!1
2'1.2
IlO
2'1.~UJTPUTS
GND
2'1.0
POSITIVE LOGIC: SEE TRUTH TABLE
t Pin assignments for these circuits are the same for all
are 16 nanoseconds through 2 levels of logic and
21 nanoseconds through 3 levels of logic for the
ITT541 55/1TT741 55.
The ITT541 55 and ITT54156 are cha racterized for
operation over the full military temperature range
of - 55°C to 125°C; the ITT74155 and ITT74156
are characterized for operation from DoC to 70°C.
a6solute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage V CC (see Note 1) ............................ 7V
Input voltage (see Note 1) ............ .'....................... ·5.5V
Operating free-air temperature range:
ITT54155.ITT54156 ................... -55°C to 125°C
ITT74155.ITT74156 ............................ O°C to 70°C
Storage temperature range ........... -65°C:to 150°C
Note
3-188
1. Voltage values are with respect to network
ground terminal.
ITT54155, ITT54156,
DUAL2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS
truth tables (H • high level. L • low level. X • irrelevant)
2·LlNE·TO·4·LlNE DECODER OR 1·LINE·TO·4·LlNE DEMULTIPLEXER
I
Outputs
Inputs
Outputs
Inputs
Strobe
Data
Strobe
Data
B
A
1G
1C
110
1Z,1
H2
1Z3
B
A
2G
2C
2Z0
2Z,1
2Z,2
2Z3
X
L
L
X
L
H
X
H
H
H
L
H
X
L
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
X
L
L
L
L
L
H
H
H
H
X
L
L
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
X
L
H
H
X
X
H
H
H
Select
H
Select
L
L
H
H
H
H
H
L
L
L
L
X
H
L
H
H
H
H
L
3·LINE·TO·8·LlNE DECODER TO 1·LlNE·TO·8·LlNE DEMULTIPLEXER
Outputs
Inputs
Strobe
or Data
(0)
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
c'
B
A
G2
2Z0
2Z1
2Z2
2Z3
HO
1 Z1
112
1Z3
X
L
L
L
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
Select
L
H
H
H
H
, C = inputs 1C and 2C connected together
G = inputs 1G and 2G connected together
2
recommended operating conditions
Min
4.5
Supply voltage VCC
Normalized fan·out from each output. N
I
I
ITT54155
Nom
Max
5
High logic level
5
Min
4.5
25
125
ITT54156
Nom
Max
5
5,5
-55
Operating free-air temperature range. TA
3-189
25
125
Unit
V
10
0
Min
4.75
25
0
70
ITT74156
Nom Max
5
16
Low·level outPUt current. 10 L
5.25
20
10
-55
Supply voltage VCC
4.75
ITT74155
Nom Max
20
Low logic level
Operating free·air temperature range. TA
5,5
Min
25
°c
Unit
5.25
V
16
mA
70
°c
ITT54155, ITT54156, ITT74155, ITT74156
DUAL 2-UNE-TO-4-UNE DECODERS/DEMULTIPLEXERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT54155.ITT74155
Parameter
VIH
High-level input voltage
V IL
Low-level input voltage
V OH
High-level output voltage
VOL
Low-level output voltage
IIH
Min
Typ'
Max
Unit
Test Conditions'
V
2
0.8
V
V
Vee = MIN. V IH = 2V.
10H = -800uA
0.4
V
Vee = MIN. VIL = 0.8V.
10L = 16mA
High-level input current (each
input)
40
uA
Vee = MAX. VI = 2.4V
1
mA
Vee = MAX. VI = 5.5V
IlL
Low-level input current (each
input)
-1.6
mA
Vee = MAX. VI = 0.4V
lOS
Short-circuit output current 3
-20
-55
mA
Vee = MAX ITT54155
-18
-57
lee
2.4
.,
Supply current
25
25
35
40
ITT74155
mA
Vee= MAX ITT54155
ITT74155
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
ITT54156. ITT74156
Parameter
V IH
High-level input voltage
Min
Typ'
Max
Unit
Test Conditions'
V
2
VIL
Low-level input voltage
0.8
V
10H
High-Ieveloutputcurrent
250
uA
Vee = MIN. VI = 2V.
V OH = 5.5V
VOL
Low-level output voltage
0.4
V
Vee = MIN. VIL = 0.8V.
IOL=16mA
40
uA
Vee = MAX. VI = 2.4V
1
mA
Vee = MAX. VI = 5.5V
-1.6
mA
Vee = MAX. VI = 0.4V
25
35
mA
Vee = MAX ITT54156
25
40
IIH
High-level input current (each
.input)
IlL
Low-level input current (each
input)
lee
Supply current
ITI74156
, All typical values are at Vee = 5V. TA == 25°e.
• For conditions shown as MIN or MAX. use 'the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted ata time.
3-190
ITT54155, ITT54156, ITT74155, ITT74156
DUAL 2~LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS
SWITCHING CHARACTERISTICS. Vce
= 5V. TA = 25°C. N = 10
ITT54155.ITT74155
From
(Input)
To
(Output)
Levels
of Logic
tpLH
A.B.2C.
lG.or2G
Z
tpHL
A.B.2C.
lG.or2.G
tpLH
Parameter
Typ
Max
2
13
Z
2
AorB
Z
tpHL
AorB
tpLH
tpHL
1
Min
ITT54155.ITT74155
Min
Test
Conditions
Typ
Max
Unit
20
15
.23
ns
CL = 15pF•
RL = 4000
18
27
20
30
ns
CL = 15pF.
RL = 4000
3
21
32
23
34
ns
CL = 15pF.
RL = 4000
Z
3
21
32
23
34
ns
CL = 15 pF.
RL = 4000
lC
Z.
3
16
24
18
27
ns
CL = 15pF.
RL = 4000
lC
Z
3
20
30
22
33
ns
CL = 15pF.
RL = 4000
, tpLH = propagation delay time. low-to-high-Ievel output
tpHL = propagation delay time. high-to-Iow-Ievel output
schematic
4
kn
FROM {
FROM {
INPUT
GATES
INPUT
GATES
!..
--
1.6
kn
OUTPUT
OUTPUT GATE FOR 54156.74156
(ONE OF EIGHT SHOWN)
OUTPUT GATE FOR 54155. 74155
(ONE OF EIGHT SHOWN)
3-191
-r
ITT54155, ITT54156, ITT74155, ITT74156
DUAL 2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS
schematic
STROBE
lG
VCC~--~-----'----r-~~~~~--,
4
4
2
kn
kn
kn
DATA
1C
TO OUTPUT GATES
1Z0.1Z1.1Z2.1Z3
1
kn
TO OUTPUT GATES
~--~~--1-~~--~-----'
4
2
kn
kn
4
2
kn
kn
1Z0.1Z1. 2Z0. 2Z1
TO OUTPUT GATES
SELECT ~~
1 Z2. 1 Z3. 2Z2. 2Z3
B
TO OUTPUT GATES
4
kn
.----4~--~~~--~-----.
4
2
kn
kn
kn
TO OUTPUT GATES
SELECT ~---r
1Z1. 1Z3. 2Z1. 2Z3
A
4
4
kn
DATA
2C
1 ZOo 1Z2. 2Z0. 2Z2
2
kn
~~
TO OUTPUT GATES
2Z0. 2Z1. 2Z2. 2Z3
STROBE
2G
0---+--__- - - - - - '
1
kn
GND o--~--~--------------~~-J
Component values shown are nominal.
W
V CC bus
3-192
ITT54157, ITT74157
ITT
-----
Quadruple 2-Line-To-1-Line
Data Selectors I Multiplexers
SEMICONDUCTORS
Quadruple 2-Line-To-1Line Data Selectors/
Multiplexers
PIN CONFIGURATION
(TOP VIEW)
•
•
•
•
•
•
•
Buffered Inputs and Outputs
Three Speed/Power Ranges Available
Typical Average Propagation Time 9 ns
Typical Power Dissip~tion 150 mW
Expand Any Data In!lut Point
Multiplex Dual-Data Buses
Generate Four Functions of Two Variables
(One Variable is Common)
• Source Programmable Counters
This monolithic, data selector/multiplexer
contains inverters and drivers to supply full
on-chip data selection to the four output
gates. A separate strobe input is provided. A
4-bit word is selected from one of two sources
and is routed to the four outputs.
FUNCTION TABLE
INPUT
POSITIVE LOGIC:
LOW LOGIC LEVEL AT S SELECTS A INPUTS
HIGH LOGIC LEVEL AT S SEL ECTS
B INPUTS.
OUTPUT
STROBE
SELECT
A
B
i:
H
L
L
L
L
X
X
L
L
L
H
X
X
X
H
H
X
X
L
H
L
L
H
L
H
Absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) .................................................... 7v
Input voltage .................................................................... 5.5V
Operating free-air temperature range: 54157
- 55° C to 125° C
74157~ .. ,., .. ,., ... , .. ,., .. , ............ O°C to 70°C
Storage temperature range: ............................................ - 65° C to 150° C
NOTE 1: Voltage values are with respect to network ground terminal.
3-193
ITT54157, ITT74157
Quadruple 2-Line-To-1-Line
Data Selectors I Multiplexers
Recommended operating conditions
74157
54157
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
4.5
5
5.5
4.75
5
5.25
V
Supply voltage, VCC
-
High-level output current, 10H
Low-level output current, 10L
BOO
.:..-. BOO
uA
16
mA
70
°c
16
Operating free-air temperature TA
-
125
55
0
Electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
MIN
PARAMETER
VIH
High-level input voltage
VIL
Low-level input yoltage
2
Input clamp voltage
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum
input voltage
IIH
High-level input current
ilL
Low-level input current
lOS
Short-circuit output
current §
.
t
Supply current
2.4
1.5
3.4
0.4
0.2
TEST CONDITIONSt
-
V
VCC= MIN,
Ij=-12mA
V
VCC= MIN,
VIH = 2V,
V
VIL=O.BV,
10H = -:- BOOuA
VCC= MIN,
VIH = 2V,
VIL=O.BV,
10L= 16mA
VCC= MAX,
VI = 5.5V
40
uA
VCC= MAX,
VI= 2.4V
1.6
mA
VCC= MAX,
VI = O.4V
55
mA
VCC= MAX
48
mA
VCC= MAX;
-
20'
V
mA
1
-
UNIT
V
O.B
-
VI
VOH
ICC
MAX
TYPt
30
See Note 2
ITT74157 MIN IS - 18.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for
the appl icable device type.
=1= All typical values are at VCC=5V, TA=25'C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with 4.5V applied to all inputs and all outputs open.
Switching characteristics, VCC = 5V, TA= 25°C
PARAMETER
FROM (INPUT)
tPLH
Data
TEST CONDITIONS
tPHL
tPLH
Strobe
tPHL
CL=15pF,
RL= 400 ,
tPLH
tPHL
Select
tPLH = propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time, high-to-Iow-Ievel output
3-194
MIN
TYP MAX
UNIT
9
14
9
14
ns
13
20
ns
ns
14
21
ns
15
23
ns
1B
27
ns
ITT54157, ITT74157
Quadruple 2-Line-To-1-Line
Data Selectorsl Multiplexers
Block Diagram
lA
lB
2A
2B
3A
3B
4A
(2)
(3)
(5)
(6)
(11 )
(10)
(14)
4B
(1 )
SELECT S
STROBE G (15)
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
-
.....- - V C C
100
n
Vcc--~~-4kU
INPUT
~--OUTPUT
3-195
I
ITT54160 THRU ITT54163
ITT74160 THRU ITT74163
mm ________________S.Y_N_CH_R_O_N_O.U_S__4_-B_IT__CO__U_NT_E_R_S
-___L_L
SEMICONDUCTORS
SYNCHRONOUS 4-BIT COUNTERS
ITT54160. ITT54161. ITT74160. ITT74161 •..• SYNCHRONOUS COUNTERS WITH DIRECT
CLEAR
ITT54162. ITT54163. ITT74162. ITT74163 ... FULLY SYNCHRONOUS COUNTERS
•
Internal Look-Ahead for Fast
Schemes
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
• Typical Maximum Input Clock
cy ... 32 MHz
Counting
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW) t
Frequen-
r:
These synchronous, presettable counters feature an
internal carry look-ahead for application in highspeed counting schemes. The ITT54160, ITT54162, ITT74160, and ITT74162 are decade
counterS and the ITT54161, ITT54163, ITT74161.
and ITT74163 are 4-bit binary counters. Synchro-nous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable inputs and internal gating. This
mode of operation eliminates the output counting
spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock
input triggers the four J-K master-slave flip-flops
on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the
outputs may be preset to either state. As presetting
is synchronous, placing a low level on the load input
disables the counter and causes the outputs to
agree with the data inputs after the next clock
pulse. The clear function for the ITT54160, ITT54161, ITT74160, and ITT74161 is asynchronous
and a low level at the clear input sets all four of
the flip-flop outputs low regardless of the state of
the clock. The clear function for the ITT54162, ITT54163, ITT74162, and ITT74163 is synchronous
and a low level at the clear input sets all four of
the flip-flop outputs low after the next clock pulse.
DATA
INPut
ENABLE
P
POSITIVE LOGIC: SEE DESCRIPTION
t plN ASSIGNMENTS FOR THESE CIRCUITS ARE THE SAME
FOR ALL PACKAGES.
This synchronous clear allows the count length to
be modified easily as decoding the maximum count
desired can be accomplished with one external
NAND gate. The gate output is connected to the
clear input to synchronously set the counter to
0000 (LLLL).
The carry look ahead circuitry provides for
cascading counters for n-bit synchronous applications w.ithout additional gating. Instrumental in
accomplishing this function are two count-enableinputs and l!- carry output. Both count-enable inputs
(P and T) must be high to count, and input T is
3-196
ITT54160 THRUITT54163, ITT74160 THRU ITT74163
SYNCHRONOUS 4-BIT COUNTERS
fed forward to enable the carry output. The carry
output thus enabled will produce a positive output
pulse with a duration approximately equal to the
positive portion of the Q A output. This positive
overflow carry pulse can be used to enable successive cascaded stages. High-to-Iow-Ievel transitions at the enable P or T inputs should occur only
when the clock input is high.
All inputs are diode-clamped to minimize
transmission-line effects. thereby simplifying system design. A full fan-out to ten normalized Series
54174 loads is available from each of the outputs
in the low-level state. A fan-out to 20 normalized
Series 54174 loads is provided in the high-level
state to facilitate connection of unused inputs to
used inputs. Input clock frequency is typically 32
megahertz and power dissipation is typically 325
milliwatts.
Series 54 circuits are characterized for operation
over the full military temperature range of-55°C
to 125° C; Series 74 circuits are characterized for
operation from O°C to 70°C.
ITT54160, ITT54162, ITT74160, ITT74162 SYNCHRONOUS DECADE COUNTERS
typical clear, preset, count. and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero.
2. Preset to BCD seven.
U
CLEAR
(54160, '14160)
3. Count to eight. nine. zero. one. two, and three.
4. Inhibt.
(ASYNCHRONOUS)
1
- - - ,L.....!.J
1,1r--------------------------------(SYNCI,RQNQUS)
1
CLEAR
(54162,74162)
u
LOAD
L=
L=
[=
DATA
INPUTS
1-------~----~I
__
CLOCK
154160,74160)
CLOCK
(54162.741621
ENABLE P
E:B
A;;::B
Active- Low Data
(Figure II)
L
H
L
H
L
L
H
H
AB
A;;::B
A~B
These circuits have been designed to not only in·
corporate all of the designer's requirements for
arithmetic operations. but also to provide 16 .possible functions of two Boolean variables without
the use of external circuitry. These logic functions
are selected by use of the four function-select inputs (SO. S1. S2. S3) with the mode control input
(M) at a high level to disable the internal carry. The
16 logic functions are detailed in the function table
and include exclusive-OR. NAND. AND. NOR. and
OR functions.
3- 215
ITT54181.ITT74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
The ITT54181/1TT74181 is designed with a Darlington output configuration (54H/74H type) to reduce the high-logic-level output impedance and
thereby improve the turn-off propagation delay
time. All outputs are rated at a normalized fan-out
of ten at the low logic level and increased to a fanout of 20 at the high logic level. The increased highlogic-level fan-out allows the system designer more
freedom in tying unused inputs to driven inputs.
The ITT54181 is characterized for operation over
the full military temperature range of -55°C to
125° C; the ITT74181 is characterized for operation
from O°C to 70°C.
121
1231 (22)
(1)
(21H20)
ALU Signal Designations
The ITT54181 and ITT74181 can be used with
either the signal designations as shown in Figures
lor II.
The logic functions and arithmetic operations obtained with signal designations as in Figure'l are
given in Table I; those obtained with the signal designations of Figure II are given in Table II.
(1911181
121
12311221
(H
(1IH1a)
(211(20)
FIGURE II
(FOR TABLE II)
FIGURE I
(FOR TABLE I)
en
(7)
171
Co
54f14181
114l
181
'"
(91
nOl
nll
(131
1111115)
!l61
I
191
I
Illi
no)
(1711151
lit)
I
(131
171
I
nOI
54fl4182
171
110)
Ill)
1121
1121
191
1111
191
TABLE I
Active-High Data
M = L. Arithmetic Operations
M=H
Selection
S1 S2 S1 So
L L
L L
L L
L L
L H
LH
LH
L H
H L
H L
H L
H L
H H
H H
H H
H H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
C = 0
_n
Cn
1
H
Logic
Functions
L F=A
H F=A+B
L F = AB
H F=O
L F = AB
HF=B
LF=A@B
H F = AS
L F=A+B
H F=AEt>B
L F=B
H F = AB
L F=1
_
H F=A+B
L F=A+B
H F=A
= =
F= A
F= A+ B
F= A+ B
F = MINUS 1 (2's COMPL)
F= A PLUSAB
F = (A + B) PLUS AS
F = A MINUS B MINUS 1
F = AB MINUS 1
F = A PLUSAS
F = A PLUS S
F = (A +
PLUS AS
F=ASMINUS1
F=APLUSA'
F = (A + B) PLUS A
F = (A + "B"i PLUS A
F = A MINUS 1
Bi
• Each bit is shifted to the next more significant position.
3 - 216
F = A PLUS 1
F = (A - S) PLUS 1
F = (A + S) PLUS 1
F = ZERO
F = A PLUS ABPLUS 1
F = (A + S) PLUS AS PLUS 1
F=AMINUSB
F= AS
F = A PLUS AS PLUS 1
F = A PLUS S PLUS 1
F = (A + B) PLUS AB PLUS 1
F = AS
F = A PLUS A PLUS 1
F = (A + B) PLUS A PLUS 1
F = (A + B) PLUS A PLUS 1
F= A
ITT54181,ITT74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
TABLE II
Active-Low Data
M = L; Arithmetic Operations
M=H
Selection
S3 S2 Sl
So
L L
L L
L L
L L
L H
L H
LH
L H
H L
L
L
H
H
L
L
H
H
L
H L
L
H L
H L
H H
H H
H
H
L
L
H H
H
H HH·
c;,
= 1
Cn =l=H
Logic
Functior-
L F=~
HF = AB
L F =A + B
H F=l
L F=A+B
H F=B
LF=A@B
H F=A+B
L F = AB
H F=A@ B
L F=B
H F=A+B
L F = 0_
H F = AB
L '~= AB
H
A
F= A
F= AB
F= AB
F = ZERO
F = A PLUS (A + B) PLUS 1
F = AB PLUS (A + B) PLUS 1
F= MINUS B
F = (A + 'B) PLUS 1
F = A PLUS (A + B) PLUS 1
F = A.fLUS B PLUS 1
F = AB PLUS (A + B) PLUS 1
F = (A + B) PLUS 1
F = A PLUS A PLUS 1
F= ABPLUSAPLUS 1
F = ABPLUS A PLUS 1
F= APLUS 1
F=AMINUS1
F = AB MINUS 1
F = ABMINUS 1
F = MINUS 1 (2's COMPL)
F = A PLUS (A + s'l
F = AB PLUS (A +
F = A MINUS B MINUS 1
F=A+'B
F = A PLUS (A + B)
F = Al'LUS B
F = AB PLUS (A + B)
F= A+ B
F = A PLUSA*
F = AB PLUSA
F = ABPLUSA
Bi
IT-
F= A
,
"'.,
* Each bit is,shlfted to the next more significant position.
absolute maximum ratings over operating
temperature range (unless otherwise noted)
Supply voltage. VCC (see Note 1) ........................... 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) ........................ 5.5V
Operating free-air temperature range:
ITT54181 ....................................... -55°Cto 125°C
ITT74181 ................................................ 0°Cto 70°C
Storage temperature range ........... -65°C to 150°C
Notes: 1. Voltage values are with respect to network
ground terminal.
.
2. This is the voltage between two emitters of
a multiple emitter transistor. For this circuit.
this rating applies to each A input conjunction
with inputs S2 or 53. and to each B input
in conjunction with inputs SO or S3.
recommended operating conditions
ITT54181
ITT74181
Min Nom Max Min Nom Max
Supply voltage V CC
Normalized fan-out from each
output. N
Operating temperature, TA
4.5
I
I
High logic level
Low logic level
5
5.5
4.75
20
10
-55
3-217
125
5
5.25
Unit
V
20
10
0
70
°c
ITT54181, ITT.74181
ARJTHMETIC LOGIC UNITS/FUNCTION GENERATORS
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
VIH
Typ
Min
Parameter
High-level input voltage
1
Test Conditions
2
V
2
Low-level input voltage
VOH
High-level output voltage any
output except A
B
IOH
High-level output current.
A
B output only
250
uA
VOL
Low-level output voltage
0.4
V
IIH
High-level input current (mode
input)
40
uA
= MIN. V IH = 2V.
= 0.8V.
10H = -800uA
Vee = MIN. V IH = 2V.
V IL = 0.8V. V OH = 5.5V
Vee = MIN. V IH = 2V.
V IL = 0.8V. IOL = 16 mA
Vee = MAX. VI = 2.4V
IIH
High-level input current (any A
or B input)
120
uA
Vee
= MAX. VI = 2.4V
IIH
High-level input current (any S
input)
160
uA
Vee
= MAX. VI = 2.4V
IIH
High-level input current (carry
input)
200
. uA
Vee
= MAX. VI = 2.4V
IIH
High-level input current (any
input)
1
mA
Vee = MAX. VI
IlL
Low-level input current (mode
input)
-1.6
mA
Vee
= MAX. VI = O.4V
IlL
Low-level input current (any A or
B input)
-4.8 . .
mA
Vee
= MAX. VI = O.4V
IlL
Low-level input current (any S
input)
-6.4
mA
Vee
= MAX. VI = O.4V
IlL
Low-level input current (carry
input)
-8
mA
Vee
= MAX. VI = O.4V
lOS
Short-circuit output current
-20
-55
mA
Vee
= MAX
-18
-57
ITT54181
ITT74181
mA
Vee
= MAX
ITT54181
ITT74181
mA
Vee
= MAX
ITT54181
ITT74181
lee
0.8
=
=
Supply current
Supply current
3
V
V
2.4
88
127
88
140
94
135
94
150
Vce
V IL
= 5.5V
typical values are at Vee = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the. applicable device type.
Not more than one output should be shorted at a time.
1 All
3
Unit
V IL
lee
2
Max
3 - 218
ITT54181,ITT74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SWITCHING CHARACTERISTICS. VCC = 5V. TA = 25°C. N = 10 (C L = 15 pF. RL = 400fi)
tpLH
To
(Output)
From
(Input)
Parameter'
Cn
Cn
Typ
Max
Unit
Cn+4
12
13
18
19
ns
Any F
13
19
ns
12
18
M = OV
(5UM or DIFF model)
ns
M = OV. 50 = 53 = 4.SV
51 = 52 = OV
(5UMmodel)
ns
M = OV. 50 = 53 = OV.
51 = 52 = 4.5V
(DIFFmodel)
ns
M = OV. 50 = 53= 4.SV.
51 = 52 = OV
(5UMmodel)
ns
M = OV. 50 = 53 = OV.
51 = 52 = 4.5V
(DIFF model)
ns
M = OV. 50 = 53 = 4.SV.
51 = 52 = CN
(5UMmodel)
ns
M = OV. 50 = 53 = OV.
51 = 52 = 4.5V
(DIFF model)
ns
M = 4.5V (logic model)
ns
M = OV. 50 = 53 = OV.
51 = 52 = 4.5V
(DIFF model)
Min
tpHL
tpLH
tpHL
tpLH
AnyAor 8
G
tpHL
tpLH
AnyAor 8
G
tpHL
tpLH
AnyAor B
P
tpHL
tpLH
AnyAor B
P
tpHL
tpLH
AnyAor B
Any F
tpHL
tpLH
AnyAor B
Any F,
tpHL
tpLH
AnyAor B
Any F
tpHL
tpLH
Any A or B
A=B
tpHL
1
13
19
13
19
17
25
17
25
13
19
17
25
17
25
17
25
28
42
21
32
32
48
23
34
32
48
23
34
35
50
32
48
tpLH = propagation delay time. low,to-high-Ievel output
tpH L = propagation delay time. high-to-Iow-Ievel output
3-219
Test Conditions
--
ITT54181, ITT74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
functional block diagram
S3
S2
SI
I
so
B3
0-.
~
A3
B2
0-<
k>
W>-
~
Gor y
~
~
I
Cn+4
P or
=
x
F3
))
,JU
~
,
I
J
A2
F2
,JU
Bl
()-<
.-4)
~
T
~
A- B
I
Al
1)
BO
C)--<
>-{:;
~
I
~D
:::J))
en
AO
M
3-220
?U
F
Fo
_
I
ITT54182, ITT74182
mm
-L.L _ _ _ __
LOOK-AHEAD CARRY GENERATOR
SEMICONDUCTORS
MSI LOOK-AHEAD CARRY GENERATOR
The ITT54182. ITI74182 is a high-speed. lookahead carry generator capable of anticipating a
carry across four binary adders or group of adders.
It is cascadable to perform full look-ahead across
n-bit adders. with only 13 nanosecond delay for
each level of look-ahead. Carry. generate-carry. and
propagate-carry functions are provided as enumerated in the pin designation table above.
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
The ITT54182 or ITT74182. when used in conjunction with the ITT54181 or ITT74181 arithmetic
logic unit (ALU) provides full high-speed carry lookahead capability for up to n-bit words. Each ITT54182/1TT74182 generates the look-ahead (anticipated carry) across a group o'f four ALUs and. in
addition. other carry look-ahead circuits may be
employed to anticipate carry across sections of four
look-ahead packages up to n-bits.
Carry
inputs
and
outputs
of
the
ITT54181/1TT74181 are, in their true form. and the
carry propagate (P) and carry generate (G) are in
negated form; therefore. the carry (input. outputs.
generate. and propagate) functions of the lookahead circuit are implemented in the compatible
forms. Reinterpretations of carry functions at the
ITT54181/1TT74181 are also applicable and compatible with the look-ahead package. Logic equations are:
LOGIC: SEE DESCRIPTION
tplN ASSIGNMENTS FOR THESE CIRCUITS
ARE THE SAME FOR
ALL PACKAGES.
absolute maximum ratings over operating freeair temperature range (unless otherwise noted)
Cn + x = GO + POC n
Cn + y =G 1 +P1GO+P1POCn
Cn + z = G2 + P2 G 1 + P2 P 1 GO + P2 P1 POCn
G = G 3 + P3 G2 + P3 P2 G 1+ P3 P2 P1GO
P = P3 P2 P1 Po
Inputs of the ITT54182/1TT74182 are diodeclamped to minimize transmission-line effects. and
Darlington outputs are employed to improve turnoff times and reduce propagation delay times. Typically. the average carry time is 13 nanoseconds.
and power dissipation is typically 180 milliwatts or
11 milliwatts per gate. The ITT54182 is characterized for operation over the full military temperature
range of -55°C to 125°C; the ITT74182 is characterized for operation from 0° C to 70° C.
Supply voltage V CC (see Note 1) ................ ;........... 7V
Input voltage (see Note 1) .................................... 5.5V
Interemitter voltage (see Note 2) ........................ 5.5V
Operating free-air temperature range:
ITT54182 ....................................... - 55°C to 125°C
ITT74182 ................................................ O°Cto 70°C
Storage temperature range ........... -65°C to 150°C
Notes: 1. Voltage values are with respect to network
ground terminal.
2. This is the voltage between two emitters of
a multiple-emitter transistor. For this circuit.
this rating applies to each G input in conjunction with any other G input or in conjunction
with any P input.
3- 221
ITT54182, ITT74182
LOOK-AHEAD CARRY GENERATOR
PIN DESIGNATIONS
DESIGNATION
PIN NOS.
FUNCTION
GO. Gl. G2. G3
3. 1. 14.5
ACTIVE-LOW
CARRY GENERATE INPUTS
PO. Pl.P2.P3
4.2.15.6
ACTIVE-LOW
CARRY PROPAGATE INPUTS
Cn
13
CARRY INPUT
Cn + x. Cn + y.
Cn +z
12. 11. 9
CARRY OUTPUTS
G
10
ACTIVE-LOW
CARRY GENERATE OUTPUT
P
7
ACTIVE-LOW
CARRY PROPAGATE OUTPUT
VCC
16
SUPPLYVOLTAGE
GND
S
GROUND
recommended operating conditions
ITT54182
ITT74182
MIN NOM MAX MIN NOM MAX UNIT
Supply voltage
Vee
Normalized fan-out from each
output, N
4.5
5
I High logic level
I Low logic level
5.5
4.75
5
20
10
-55
Operating free-air temperature range. T A
25
125
5.25
V
20
10
0
25
70
°c
EI..ECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
Min
Typ
1
Max
2
Unit
Test Conditions 2.
V
V IL
Low-level input voltage
VR
Input Clamp Voltage
VOH
High-level output voltage
VOL
Low-level output voltage
0.4
V
IIH
High-level input current (C n
input)
SO
IIH
High-level input current (P3
input)
IIH
High-level input current (P2
input)
O.S
V
V
uA
= MIN.I i = -12mA
VCC = MIN. V IH = 2V.
V IL = O.SV.IOH = -SOOuA
VCC = MIN. V IH = 2V.
V IL = O.SV. IOL = 16 mA
VCC = MAX. VI = 2.4V
120
uA
Vee
= MAX. VI = 2.4V
160
uA
Vee
= MAX. VI = 2.4V
-1.5
2.4
V
3 - 222
VCC
ITT54182, ITT74182
LOOK-AH EAD CARRY GEN ERATOR
E lE CTR ICAl CH A RACTE R ISTI CS over recommended operating free-air temperature range
(unless otherwise noted) (continued)
Min
Parameter
Max
TVp'
Unit
Test Conditions 2
IIH
High-level input current (PO. Pl.
or G3 input)
200
uA
Vee = MAX. VI = 2.4V
IIH
High-level input current (GO or
G2 input)
360
uA
Vee = MAX. VI = 2.4V
IIH
High-level input current (G 1
input)
400
uA.......
Vee = MAX. VI =.2.4V
IIH
High-level input current (anv
input)
1
rnA
Vee = MAX. VI = 5.5V
IlL
Low-level input current (en
input)
-3.2
rnA
Vee = MAX. VI = 0.4V
IlL
Low-level input current (P3
input)
-4.8
rnA
Vee = MAX. VI = 0.4V
IlL
Low-level input current (P2
input)
-6.4
rnA
Vee = MAX. VI = 0.4V
IlL
Low-level input current (PO. Pl.
or G3 input)
-8
rnA,
Vee = MAX. VI = 0.4V
IlL
Low-level input current (GO or
G2 input)
-14.4
rnA
Vee = MAX. VI = 0.4V
IlL
Low-level input current (G 1
input)
-16
rnA
Vee = MAX. VI = 0.4V
lOS
Short-circuit output current
leeH
Supply current. all outputs high
3
-40
-100
27
rnA
Vee = MAX
rnA
Vee = MAX
ITT54182
ITT74182
rnA
Vce = MAX
ITT54182
ITT74182
27
ICCL
Supply current. all outputs low
SWITCHING CHARACTERISTICS. Vee
Parameter
45
65
45
72
= 5V. TA = 25°e. N = 10
Min
TVp'
Max
Unit
Test Conditions 2
tpLH
Propagation delay time.
low-to-high-Ieveloutput
11
17
ns
eL = 15pF.R L =400Q
tpHL
Propagation delay time.
high-to-Iow-Ieveloutput
15
22
ns
CL = 15 pF. RL = 400Q
,
, All typical values are at Vce = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not niore than one output should be shorted at a time and duration ofthe short-circuit test should not exceed 1 second.
2
3-223
IIT54182, IIT74182
LOOK-AHEAD CARRY GENERATOR
functional block diagram
~--oG
P30----+-r-r~~~+_~
G30----+~~--4-~+_~
P20----+-r~--~~+_~
G2o----+-r----4-~+-~
P10----+......-----!--I---+-I
G1o----r------+-.--;~
POo---......------~----~
GOO-----------~----~
3 - 224
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH
DOWN/UP MODE CONTROL
ITT
----SEMICONDUCTORS
SYNCHRONOUS UP/DOWN COUNTERS
WITH DOWN/UP MODE CONTROL
• Counts 8-4-2-1 BCD or Binary
Down/Up Count Control Line
• Single
• Count Enable Control Input
• Ripple Clock Output for Cascading
Asynchronously Presettable with Load
• Control
•
•
•
•
•
DUAL -IN - LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)T
INPUT{
DATA
B
I
OUTPUTS {
Parallel Outputs
QA
Cascadable for n-Bit Applications
a4
fNABL
INPUTS
DOWNf
UP
Typical Average Propagation Delay (Clock
to Q Output) ... 20 ns
Typical Power Dissipatian ... 325 mW
·13 CLOCK
RIPPLE}.
OUTPUTS
12
~~~f
OUTPUTS{
Typical Maximum Clock Frequency...25 Mhz
."
ASYNCHRONOUS INPUTS: LOW INPUT TO LOAD SETS
QA 'A,QB 'B,QC'C, AND QD'D
The ITT54190. ITT54191. ITT74190. and ITT74191 are synchronous. reversible up/down
counters having a complexity of 58 equivalent
gates. The ITT54191 and ITT74191 are 4-bit
binary counters and the ITT54190 and ITT74190
are BCD counters. Synchronous operation is
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with
each other when so instructed by the steering logic.
This mode of operation will eliminate the, putput
counting spikes which are normally associated with
asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are
triggered on a low-to-high-Ievel transition of the
clock input if the enable input is low.. A high at the
enable input inhibits counting. Level changes at the
enable input should be made only when the clock
input is high. The direction of the count is determined by the state of the down/up input. When
low. the counter counts up and when high. it counts
down.
fPIN ASSIGNMENTS FOR THESE CIRCUITS ARE THE
SAME FOR ALL PACKAGES.
These counters are fully programmable; that is. the
outputs may be preset to any state by placing a
low on the load input and entering the desired data
at the data inputs. The output will change to agree
with the data inputs independently of the state of
the clock input. This feature allows the counters to
be used as modulo-N dividers by simply modifying
the count length with the preset inputs.
Input buffers have been
requirement to only one
load at all inputs except
when the output of the
what limited.
3-225
used to lower the fan-in
normalized Series 54174
enable. This is important
driving circuitry is some-
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP
MODE CONTROL
Two outputs have been made available to perform
the cascading function: ripple clock and maximum/minimum count. The .Iatter output produces
a high-level output pulse with a duration approximately equal to one complete cycle of the clock
when the counter overflows or underflows. The ripple clock output produces a low-level output pulse
equal in width to the low-level portion of the clock
input when an overflow or underflow condition exists. T.he counters can be easily cascaded by feeding
the ripple clock output to the enable input of the
succeeding counter if parallel clocking is used, or
to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to
accomplish look-ahead for high-speed operation.
Power dissipation is typically 325 milliwatts for
either the decade or binary version. Maximum input
clock frequency is typically 25 megahertz and is
guaranteed to be at least 20 megahertz.
The ITT54190 and ITT54191 are characterized for
operation over the full military temperature range
of - 55°C to 125°C; the ITT74190 and ITT74191
are characterized for operation from O°C t070°C.
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
ITT54190, ITT74190 DECADE COUNTERS
Supply voltage, VCC (see Note 1) ........................... 7V
Input voltage (see Note 1) .................................... 5.5V
Operating free-air temperature range:
ITT54190, ITT54191 .................. - 55°C to 125°C
ITT74190, ITT74191 ........................... ooC to 70°C
Storage temperature range ........... - 65°C to 150°C
Note
1: Voltage values are with respect to
network ground terminal.
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to BCD seven.
2. Count up.tO eight, nine (maximum). zero, one,
and two.
3. Inhibit.
4. Count down to one, zero (minimum). nine,
eight, and seven.
r-
_---;..--"'-11
CLOCK
DOWNJUP ~L""'--+!...-_ _ _ _ _ _ _.-J
ENABLEIL+---'-!...-_ _ _ _ _---l
aB----ri
---~
ac -
---["'11
---~
-- --,
aD ____
. I~;------------~----~~----------~I
-!...-------!...---!-----.-J
L
II
I
L..J.J
MAX MIN
f - '- - - - - ,
L-____
===J ::, ,
I,
RIPPLE CLOCK
I
:~I------~
----I
___ ..J
:
U
I I
I I
7
I I
8
I II-----
~
9
U
0
COUNT UP
1
2
-I--
INHIBIT
LOAD
3-226
I
2
--I I---
-·"s .
COUNT DOWN - - - -
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP
MODE CONTROL
recommended operating conditions
(,
ITT54190, ITT54191 ITT74190, ITT74191
Min
Nom
4.5
Supply voltage, Vee
Normalized fan-out from each output, N
Max
Min
5.5
4.75
5
Nom
Max
Unit
5
5.25
V
20
20
High logic level
10
Low. logic level
0
Input clock frequency, fclock
10
20
20
0
MHr
Width of clock input pulse. tw(clock)
25
25
ns
Width of load input pulse, tw(load)
35
35
ns
Data setup time, t5etup (See Figures 1 and 2)
20
20
ns
0
0
ns
Data hold time. t hold
-55
Operating free-air temperature. TA
25
125
0
25
70
ITT54191. ITT74191 BINARY COUNTERS
typical load. count. and. inhibit sequences
Illustrated below is the following sequ.ence:
1: Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen (maximum). zero,
one, and two.
,, ,,
LOA0-U
A
-.ll-~-L:
I
,
3. Inhibit.
4. Count down to one, zero (minimum). fifteen,
fou rteen, and thirteen.
=
'1,r
__
, ,
II
DATA
INPUTS
I
1
,
I
__
cJ17L-_
0-n-:'L-_
,
CLOCK
--'I .
DOWN/UP IL._---'--'-_ _ _ _ _ _ _ _
-,IL-+---;"7'
" _ _ _ _ _ _ _-!
"
ENABLE
os: =W.1:1--_-,
L
L-_ _...J
__--I
-I
00 -
"
"
""
,'
",I
MAx/M'N=-=~LI--.!:..;.:_-IIlL___-..!.___-"----..!._-lIlL_____
,,
--I
,'
--113 ::
IPPLE CLOCK -
U
1 I
14
15
U
I:
2
2: 2
I II---COUNTUP----ti-·
IN·HIBIT--I
~
LOAD
3 -227
I
1
15
14
13
l--COUNTDOWN---
°c
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP1DOWN COUNTERS WITH
DOWN/UP MODE CONTROL
E LECTR I CAL C H ARACTE RISTI CS. over recommended operating free-air temperatu re range
(unless othelWise noted)
Parameter
1
2
3
ITT54190.ITT54191
Typ 1
Max
Min
ITT74190. ITT74191
Typl
Min
Max
Unit
2
2
V
Vee =MIN
Test Conditions 2
V IH
High-level input
voltage
V IL
Low-level input
voltage
0.8
0.8
V
Vee = MIN
VI
Input clamp voltage
-1.5
-1.5
V
Vee = MIN. II
V OH
High-level output
voltage
VOL
Low-level output
voltage
0.4
0.4
V
II
High-level input
current at maximum
input voltage
1
1
mA
= -12mA
Vee = MIN. V IH = 2V.
V IL = 0.8V. 10H = -800uA
Vee = MIN. V IH = 2V.
V IL '= 0.8V. 10L = 16mA
Vee = MAX. VI = 5.5V
IIH
High-level input
current at any input
except enable
40
40
uA
Vee
= MAX. VI = 2.4V
IIH
High-level input
current at enable
input
120
120
uA
Vee
= MAX. VI = 2.4V
IlL
Low;level input
current at any input
e>«:ept enable
-1.6
-1.6
mA
Vee
= MAX. VI = 0.4V
IlL
Low-level input
current at enable
input
-4.8
-4.8
mA
Vee
= MAX. V I = 0.4V
lOS
Short-circuit output
current 3
-65
mA
Vee
= MAX
ICC
Su pply current
105
mA
Vee
= MAX. See Note 2
2.4
2.4
-65
-20
65
=
105
V
-18
65
=
All typicalvalues are atV ee
5V. TA
25°e.
.
For conditions shown as MAX or MIN. use appropriate value specified under recommended operating conditions for
the applicable device type.
Not more than one output should be shorted at a time.
Note
2: ICC is measured with all inputs grounded and all outputs open.
3- 228
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP
MODE CONTROL
SWITCHING CHARACTERISTICS, Vee
Parameter'
From
(Input)
To
(Output)
t max
tpLH
Load
tpHL
tpLH
Min
Typ
20
25
Ok 0B' DC,
22
33
33
50
Data A. B. C.
D
0A' 0B' DC,
14
22
°D
35
50
Clock
Ripple Clock
13
20
16
24
tpHL
tpLH
Clock
tpHL
tpLH
Clock
Ok 0B' 0C-
16
24
°D
24
36
Max/Min
28
42
37
52
30
45
30
45
21
33
22
33
tpHL
tpLH
Down/Up
Ripple Clock
tpHL
tpLH
Max
°D
tpHL
tpLH
= 5V. TA = 25°e. N = 10
Down/Up
Max/Min
tpHL
, t max = maximum clock frequency
tpLH = propagation delay time. low-to-high-Ievel output
tpHL = propagation delay time. high-to-Iow-Ievel output
3- 229
Unit
Test Conditions
MHz
CL = 15pF.R L =400rl
ns
CL = 15 pF. RL = 400rl
ns
CL = 15 pF. RL = 400rl
ns
CL = 15 pF. RL = 400rl
ns
CL = 15pF. RL = 400rl
ns
CL = 15 pF. RL = 400rl
ns
CL = 15 pF. RL = 400rl
ns
CL = 15pF.R L =400rl
ITT54190, ITI54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH
DOWN/UP MODE CONTROL
ITT54191, ITT74191 BINARY COUNTERS
functional block diagram
CLOCK
-
DOWNI
UP
DATA
INPUT A
ENABLE
I
r--f
MAX
I MIN
OUTPUT
I
;V+
n
p
RIPPLE
CLOCK
I~
f
-
A
I"-
..........
-
PRESET
QA
J
OUTPUT QA
I--C CLOCK
f- f-
-
QA I -
t-- K
CLEAR
'(
--/
DATA
INPUT B
I~
-
n
r- r--
~~
~
'--
-~
[)ATA
INPUT C
I
n
J
PRESET
QB
OUTPUT QB
CLOCK
r-- K CLEA~B -
y
-"
~~
" Dc
PRESET
r- - J
OUTPUT
Dc
I--C CLOCK
~
-
K CLEAi?c
~
?
DATA
INPUT 0
I
j
----;
-
-J
PRESET
QD
OUTPUT QD
--C CLOCK
-K
aD
CLEAR
I'
1
LOAD
3-230
r-
ITT54190, ITT54191, ITT74190, ITT74191
SYNCHRONOUS UP/DOWN COUNTERS WITH
DOWN/UP MODE CONTROL
ITT54190. ITT74190 DECADE COUNTERS
functional block diagram
-
CLOCK
/
DOWN
UP
DATA
INPUT A
ENABLE
G
DATA
INPUT B
I
I
~.
~ 1-1-
-
,...-
'"
1
flU
I- -
..........
l...-
f--
I>
-
OUTPUTQA
-
KCLEA~A ly
II.
-
,...- f--
---
~
1
l...-
I--
n
"
-DATA
INPUT 0
PRESET
J
0A
1
....1---1
OUTPUT
~ CLOCK
-V
I
MAX I MIN
)..
1
DATA
INPUT C
RIPPLE
CLOCK
J
PRESET
0B
CLOCK
KCLEA'pB
r- - J
~
n-
PRESET
Dc
KCLEA~Iy
I--
J
1
r-
PRESET
00
L.( CLOCK
3-231
OUTPUT Dc
CLOCK
-
l...-
' - 1---1
",LOAD
l-
'(
j\.
-
OUTPUTOB
'----- K
n
CLEA~O
'1'
OUTPUT 00
I
mm
..I....L
ITT54/74192,ITT54/74193
SYNCHRONOUS 4-81T UP-DOWN COUNTER
-o/SEMICONOUCTORS - - - - - - - - - - - - - - - - - - - -
SYNCHRONOUS 4-B'T UP-DOWN
CO U NTE R (dual clock with' clea'r)
DUAL -IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
• Cascading Circuitry Provided Internally
• Guaranteed fanout of 10 TTL loads over
the full temperature range and supply
voltage ranges.
• High capacitive drive capability.
• Individual Preset to Each Flip' Flop.
• Typical power dissipation of 325 mW
},~"
• The input/output characteristi'cis provide
easy interfacing with DTL930, TTL9000,
TIL7400 and MSI families .
•• Input clamp diodes limit high speed line
termination effects
",.'
}
OUTPUTS
}
INPUTS
• Fully Independent Clear Input
II
• Typical Maximum Input Count
Frequency.•...32 MHz
'-----I
.)
LOGIC LOW INPUT TO LOAO SETS
OA=A , 0 8=8,
The M SI ITT5417 4192 is a synchronous \J,p(down
decade counter with separate up/down clockS'. parallel load (asynchronous) facility. two terminal
count outputs for multi-decade operation. and a"~
asynchronous overriding master reset
The MSI ITT54174193 is a synchronous up/down
4-bit binary counter with separate up/down clocks.
parallel load (asynchronous) facility. terminal count
outputs for multi-decadeTPperations. and an asynchronous overriding master reset.
Counting is synchronous. with the outputs changing state after the low to high transition of either
the count-up clock (CPU) or count-down clock
(CPO). The direction of counting is determined by
which clock input is pulsed while the other clock
input is high. (incorrect counting will occur if both
the count-up clock and count-down clock inputs
are pulsed simultaneously.) The counter will respond to a clock pulse on either input by changing
to the next appropriate state of a binary sequence.
atc . a 0=0
The counter hasra parallel load (asynchronous) facility which pernjlits the counter to be reset. Whenever the data e'~able (Pl;) input is low. the information present on the parallel data inputs (P A- PB •
PC. PO) will be loaded into the counter and appear
on the outputs independent of the conditions of the
clock inputs. When the data enable input goes low.
this information is stored in the counter and when
the counter is clocked it changes to the next appropriate state in the counts sequence. The data
inputs are inhibited when the data enable is high
and have no t;lffect on the counter.
The terminal count-up (T!=:U) and terminal countdown (TC O) outputs (Carry and Borrow respectively) allow multistage binary counter operations
without additional logic. The counters are cascaded
by feeding the terminal count-up output to the
count-up clock input and the terminal'count-down
output to the count-down input of the following
counter.
3-232
,
ITr54/74192, ITT54/74193
,
/
.,\
1
SYNCHRONOUS 4-81T UP-DOWN COUNTER
absolute maximum ratings (above which the
useful life may be impaired)
.
Storage Temperature ................ -65° e to + 150 °e
Temperature (Ambient)
Under Bias ................................. -55°eto +125°e
Vee Pin Potential to Ground Pin -0.5V to +7 Volts
Voltage Applied to. Outputs
for high output state ................ -Q;5V to Vee value
Input Voltage (D.C.) .................... -O.5V to + 5.5 Volts
. ,i:_
recommended operating conditions
ITT54192. rTT54193
.,
Supply voltage Vee
ITT74192.ITT74193
Min
Nom
Max
Min
'Nom
Max
Unit
4.5
5
5.5
4.75
5
5.25
V
Normalized fan-out from each output. N
10
25
10
0
Width of any input pulse. tw
20
20
ns
Data setup time. tsetup (see Figure 7 and Note 2)
20
20
ns
Data hold time. t hold (see Note 3)
,,'
Operating free-air temperature range. TA
Notes:
0
0
25
MHz
Input count frequency. f count
ns
0
-55
25
125
0
25
70
°C
2. Setup time is the interval immediately preceding the positive-going edge of the load pulse during whic~
interval the data to be recognized must be maintained atthe input to ensure its recognition.
~.
3. Hold time is the interval immediately following the positive-going edge of the load pulse during which
interval the data to be recognized must be maintained.at the input to ensure its recognition.
"
'.[
schematics of inputs dnd outputs
- - . . - - - - vce
130fl
vee----~~----
4,Kfl
INPUT
. - - - - OUTPUT
3-233
ITT54/74192, ITT54/74193
SYNCHRONOUS 4-BIT UP-DOWN COUNTER
w
ELECTRICAL CHARACTERISTICS. over recommended operating free-air temperature range
(unless otherwise noted)
Symbol
VIH
Characteristics
High-level input
voltage
ITT54192. ITT54193 ITT74192.ITT74193
Min
Typ'
Max
Min
Typ'
Max
Unit
2
Low-level input
voltage
V OH
High-level output
voltage
VOL
Low-level output
voltage
0.4
IIH
High-level input
current
IlL
Low-level input
current
-1.6
lOS
Short-circuit output
current 3
65cc
V
2
V IL
0.8
0.8
2.4
Supply current
V
V
VCC = MIN. V IH =2V
V IL = 0.8V.I OH = 400 uA
0.4
V
VCC = MIN. VOH = 2V.
V IL = 0.8V.I OL =' 16 mA
40
40
uA
1
1
mA
VCC =MAX. VI = .2.4V
5.5V
MAX. VI
VCC
-1.6
mA
VCC = MAX. VI = 0.4V .'
-65
mA
VCC = MAX
102
mA
VCC = MAX
2.4
-20
-65
65
Conaitlons 2
-18
89
, All typical values are at VCC = 5V.TA = 25°C
2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
.
for the applicable device type.
3 Not more than one output should be shorted at a time.
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
From
Input
Parameter'
To
Output
f max
Min
Typ
25
32
tsetup
Max
Units
Conditions
MHz'
CL = 15pF.R L =400n
14
20
ns
CL = 15 pF. RL = 400
n
tpLH
tpHL
Count-up
Carry
17
16
26
24
ns
CL = 15. pF. RL = 400
n
tpLH
tpHL
Count'down
Borrow
16
16
24
24
ns
CL = 15 pF.H L = 400
n
tpLH
tpHL
Either Count
Q
25
31
38
47
ns
CL = 15 pF.R L = 400
n
tpLH
tpLH
Load
Q
27
29
40
40
ns
CL = 15 pF. RL = 400.n
tpHL
Clear
Q
22
35
ns
CL = 15 pF. RL = 400
'fmax = maximum clock frequency
tpLH = propagation delaytime.low-to-high-Ievel output
tpH L = propagation delay time. high-to-Iow-Ievel output
3- 234
n
ITT54/74192, ITT54/74193
SYNCHRONOUS 4-BITUP-DOWN COUNTER
ITT54114192 DECADE COUNTERS
TYPICAL CLEAR. LOAD. AND COUNT SEQUENCES
1. Clear outputs to zero.
3. Count up to eight. nine, carry, zero, one, and two.
2. Load (preset) to BCD seven.
4. Count down to one, zero, borrow, nine, eight. and seven.
~~--------------------------
,.{
COUNT
U,
u
1
:- - - - - -- -- - --.J,.;.--,..-.0.,,~---------------.J
~~-7'-i'
.
.J
I
c================
c================
===== === ====== ==
1 ,
_-:---'---i-'..Ji-
--~~~,-'Lfl1lLILJlJ~---------------
~~~T
1 •
r-- •
SEOUENCE
ILLUSTRATED
, ,
0
COUNT UP
~
Ir-'
U
0
'
,
•
'I
COUNT D O W r . I - (
ITT54174193 BINARY COUNTERS
TYPICAL CLEAR. LOAD. AND COUNT SEQUENCES
1. Clear outputs to zero.
3. Count up to fourteen, fifteen carry, zero, one, and two.
2. Load (preset) to BCD thirteen.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
--fl'-,--r-----'--------------------:-.-----------------------------_-_-_-_-_"I
I
U
I I
~~================
:: :c================
~c================
I
I
I
I
~~================
LJL.fl...f1..JL
I
COUNT
U,
~'b~NNT
I
I
I
I.'
I
I
I
I
I
I
I
I
1
I
~
=,..:..,.i-'.,...;-:---;'..J
oc=~
OUTPUTS { : :
0,
=:l.U--i--:----i.-___-;.---,..__----'r-----i--...:'--;.'--;-:-;,--;-----,Ur-----;.-.;---------;-,,
,
, I
U
I
SEOU£NCE
IllUSTRATED
Notes:
r-- '"
1 "
0
CDUNlUP
A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must
1'
~ r--
"I
0
"
"
COUNT DOWN----'
be high. When counting down, count-up input must be high.
3 - 235
ITT54/74192,ITT54/74193
SYNCHRONOUS 4-BIT UP-DOWN COUNTER
ITT54/74192 DECADE COUNTERS
FUNCTIONAL BLOCK DIAGRAM
~
0
/'
BORROW
OUTPUT
CARRY
OUTPUT
~
DATA
INPUT A
~
r-l--/
DOWN
COUNT
0--
D
"~
UP
COUNT
DATA
INPUT B
°A
CiA r-
b
--r\.
~
~
0D'Q
R
ipR~ET
r-LJ
0...-.-.-
OUTPUTQA
T
Os
OUTPUT Os
T
Os -
D .-3f
DATA
INPUT C
tlf
I-
DATA
INPUT D
V"
~0
~Dc
OUTPUTQC
T
Oe -
W-
-1\.
r-LJ
CLEAR
t-i
~tiET
Do
.......--..
T
001LOAD
-3-236
Lr\ L3V
OUTPUTQO
ITT54/74192, ITT54/74193
SYNCHRONOUS 4-81T UP-DOWN COUNTER
ITT54/74193 BINARY COUNTERS
FUNCTIONAL BLOCK DIAGRAM
'-
BORROW
OUTPUT
"
OUTPUT
J
CARRY
j
DATA
INPUT A
r-L.I"
Je.
DOWN
COUNT
QA
OUTPUT QA
T
UP
COUNT
OA
D
DATA
..r-'\
INPUT B
DATA
INPUT C
,
,
DATA
INPUT D
CLEAR
~Os
f1-'
.~
oJ">
OUTPUT 0B
T
Oa
U ~
--r-"\
~Oc
rl-/
.~
fifyR
OUTPUTQC
T
Dc
U
:9~r
D
---
I--t
~~
00
T
00
s:J'Y
LOAD
3-237
OUTPUT Q D
ITT
ITT54194, ITT74194
.... SEMICONDUCTORS -
----
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT
REGISTERS
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Left Shift
Right Shift
Do Nothing
•
Positive Edge-Triggered Clocking
C
Direct Overriding Clear
DUAL-IN-LiNE P!lCKAGE
PIN CONFIGURATION
(TOP VIEW)t
SHIFT
s~~~[ 2
INPUT
These bidirectional shift registers are designed to
incorporate virtually all of the featur.es a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel in-.
puts, parallel outputs, right-shift and left-shift serial
inputs, operating-mode-control inputs, and a direct
overriding clear-line. The register has four distinct
modes of operation, namely:
PARALLEL{:
INPUTS
C
o
SHIFT
LEFT
SERIAL
INPUT
GNO
MODE CONTROL
POSITIVE LOGIC: SEE DESCRIPTION
Parallel (Broadside) Load
S1
SO
H
H
L
H
t
Shift Right (In the direction
QA toward QO)
Shift Left (In the direction
Q O toward QA)
H
L
Inhibit Clock (00 nothing)
L
L
In the parallel load mode, data is loaded into the
associated flip-flop and appears at the outputs after
the positive transition of the clock input. Ouring
loading, serial data flow is inhibited. Shift right is
accomplished synchronously with the rising edge
of the clock pulse when SO is high and S1 is low.
Serial data for this mode is entered at the shift-right
data input. When SO is low and S 1 is high, data
shifts left synchronously and new data is entered
at the shift-left serial input. Clocking of the flip-flops
is inhibited when both'mode-control inputs are low.
The mode controls should be changed only while
the clock input is high.
Pin assignments for these circuits are the same for all
packages.
These four-bit shift registers are compatible with
most other TTL and OTL logic families. All inputs
are buffered to lower.the drive requirements to one
normalized Series 54174 load, and input clamping
diodes minimize switching transie.nts to simplify
system design. Maximum input clock frequency is
typically 36 megahertz and power dissipation is
tYpically 195 mW.
The ITT54194 is characterized for operation over
the full military temperature range of -55°C to
125-°C; the ITT74194 is characterized for operation
from aoc to 70°C.
3 -,238
ITT54194,ITT74194
.4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
;
absolute maximum ratings over operating
free-air temperature range (unless otherwise noted)
Operating free-air temperature range
ITT54194 ........................................ -55°C to 125°C
ITT74194 ................................................. 0° C to 70°C
Storage temperature range ........... -65°C to 150° C
Supply voltage. vee (See Note 1) .......................... 7V
Input voltage (see Note 1) .................................... 5.5V
Note:
1. Voltage values are with respect to network
ground terminal.
recommended operating conditions
-
ITT54194
Nom
Max
Min
Supply voltage. Vee
Normalized fan-out from each output. N
4.5
5.5
4.75
ITT74194
Nom Max
5
20
20
low logic level
10
10
0
25
Unit
5.25
High logic level
Input clock freq uency. fclock
V
25
0
MHz
20'
20
ns
Mode control
30
30
ns
Serial and
parallel data
20
20
ns
Clear
in active- state
25
25
ns
Width of clock or clear pulse. tw
S etup time. tsetup (See Figure 1 )
5
Min
Hold time at any input. t hold
0
Operating free-air temperature. TA
0
-55
125
ns
70
0
°e
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
Min
Typ'
Max
Test Conditions
Unit
2
V
2
V il
low-level input voltage
V1
Input clamp voltage
V OH
High-level output voltage
Val
low-level output voltage
0.4
V
Ii
Input current at maximum input
voltage
1
mA
= MIN. Ii = -12mA
= 2V.
= -BOO u.A
Vee = MIN. VIH = 2V.
V IL = O.BV. IOl = 16mA
Vee = MAX. VI = 5.5V
IIH
High-level input current-
40
uA
Vee
O.B
-1.5
2.4
3-239
V
V
Vee
V
Vee = MIN. VIH
V IL = O.BV. IOH
= MAX. VI = 2.4V
ITT54194, ITT74194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
ElECTR ICAl CHARACTE RISTI CS over recommended operating free-air temperature range
(unless otherwise noted) (continued)
Parameter
IlL
Low-level input current
lOS
Short-circuit output current"
ICC
Note:
1
2
3
Typ
Min
1
Max
Test Conditions 2
Unit
-1.6
rnA
-20
-57
mA
= MAX. VI = 0.4V
ITT54194
VCC = MAX
-18
-57
mA
VCC
Supply current
39
63
VCC
= MAX. See Note 2
2. With all outputs open. inputs A through D grounded. and 4.5V applied to SO. 51. clear. and the serial inputs.
ICC is tested with a momentary ground. then 4.5V. applied to clock.
All typical values are at VCC = 5V. TA = 25°C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter
f max
Maximum input clock frequency
tpHL
Propagation delay time
high-to-Iow-Ievel output from
clear
tpLH
Propagation delay time
low-to-high-Ievel output from
clock
tpHL
Propagation delay time
high-to-Iow-Ievel output from
clock
Min
Typ
25
36
Max
Unit
Test Conditions
MHz
CL
= 15 pF. RL = 400
= 15 pF. RL = 400
~
30
ns
7
14
22
ns
CL
= 15 pF. RL = 400
~
7
17
28
ns
CL
= 15 pF. RL = 400
~
typical clear. load. right-shift. left-shift. inhibit. and clear sequences
CLOCJ(J1..fl...fLSlSU~~
MODE
CONTROL
INPUTS
{so ::J
51
1
CLEAR
SERIAL{R
I~:~:S l
PARALLEl.{:
DATA
INPUTS
OUTPUTS
c
;
::1 : ;
I!
:
t-J!
i
1
I!
-t7
--+rn
I
1
1
I
I :
I
:
I
I
:
I
!
:
:
1:
JI
:
:~
: 11
!
00
--::
--.,
l
'j
i
I
I : ,
I
~
I
!
~
{: =:tti=8,
DC
~
19
CL
:
::~ !
i
-- i i
~SHIFTRIGHT---..j
~SHIFTLEFT-+-INHIBIT----l
3-240
ITT54194, ITT74194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
functional block diagram
PARALLEL OUTPUTS
r-__________________
__________________
~A~
lOA
CLEAR
CLOCK
o---"---j
Sl
MODE {
CONTROL
SO
3-241
OB
ac
~
ao\
ITT
----ITT54195, ITT74195
4-81T PARALLEL-ACCESS SHI FT REG ISTERS
SEMICONDUCTORS
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
• Synchronous Parallel Load
• Positive Edge-Triggered Clocking
Vee
CLEAR
• Parallel Inputs and Outputs from
Each Flip-Flop
SERIAL{J
INPUTS R
• Direct Overriding Clear
• J and K Inputs to First Stage
• Complementary Outputs from Last Stage
OUTPUTS
PARALLEL{:
INPUTS
e
o
SHIFT/
LOAD
These 4-bit registers feature parallel inputs. parallel
outputs. J-K serial inputs. shift/load control input.
and a direct overriding clear. The registers have two
modes of operation:
POSITIVE LOGIC: SEE DESCRIPTION
, Pin assignments for these circuits are the
same for all packages.
TRUTH TABLE
Parallel (Broadside) Load
Inputs a.!. tn
J
K
Shift (In direction QA toward QD)
Parallel loading is accomplished by applying the
four bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flop and appears at the outputs after the
positive transition of the clock input. During
loading. serial data flow is inhibited.
Shifting is accomplished synchronously when the
shift/load control input is high. Serial data for this
mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K. 0-. or T-type
flip-flop as shown in the truth table.
These shift registers are fully compatible with most
other TTL and DTL families. All inputs are buffered
to lower the drive requirements to one normalized
Series 54174 load. including the clock input. Maximum input clock frequency is typically 39
megahertz and power dissipation is typically 195
milliwatts. The ITT54195 is characterized for operation over the full -military temperature range of
-55°C to 125°C; the ITI74195 is characterized
for operation from O°C to 70° C.
QA
L
H
QAn
L
L
L
H
H
H
H
L
QAn
Outputs at t n +1
QB
QC
QD
QD
QCn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
QAn
QAn
QAn
QAn
QBn
QBn
QBn
QBn
H = high level. L = low level
Notes: A. tn = bit time before clock pulse
B. t n+ 1 = bit time after clock pulse
C. QAn = state of QA at tn
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage. V CC (see Note 1) ........................... 7V
Input voltage (see Note 1) .................................... 5.5V
Operating free-air temperature range:
ITI54195 Circuits ......................... - 55°C to 125°C
ITT74195 Circuits .................................. O°C to 70°C
Storage temperature range ........... -65°Cto 150°C
Note:
3-242
1. Voltage values are with respect to network
ground terminal.
ITT54195, ITT74195
4-BIT PARALLEL-ACCESS SHI FT REGISTERS
recommended operating conditions
Min
4.5
Supply voltage. VCC
Normalized fan-out from each output. N
ITT54195
Max
Nom
5
5.5
Min
4.75
ITT74195
Nom Max
5
5.25
High logic level
20
20
Low logic level
10
10
0
V
Input clock frequency. fclock
0
Width of clock input pulse. tw(clock)
16
16
ns
Width of clear input pulse. tw(clear)
12
12
ns
Shift/load
25
25
Serial and
parallel data
15
15
Clear
inactive-state
25
25
Setup time. tsetup (see Figure 1)
30
Unit
0
Serial and parallel data hold time.
MH2
ns
10
10
Shift/load release time. trelease
30
0
ns
ns
thold
-55
Operating free-air temperature. TA
3-243
125
0
70
°c
ITT54195, ITT74195
4-81T PARALLEL-ACCESS SHI FT REG ISTERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
High-level input voltage
V IL
Low-level input voltage
VI
Inpllt clamp voltage
V OH
H igh'level output voltage
Min
Typ'
Max
Unit
Test Conditions
2
V
2
0.8
V
-1.5
V
Vee = MIN. II = -12mA
V
Vee = MIN. V IH = 2V.
V
Vee = MIN. V IH = 2V.
2.4
V IL = 0.8V. 10H = -800uA
VOL
OA
Low-level output voltage
V IL =0.8V.I OL = 16mA
II
Input current at maximum input
voltage
1
mA
Vee = MAX. VI = 5.5V
IIH
High-level input current
40
uA
Vee = MAX. VI = 2.4V
IlL
Low-level input current
lOS
Short-circuit output current
lee
Note:
3
-1.6
mA
Vee = MAX. VI ~ OAV
-20
-57
mA
Vee = MAX
-18
-57
Supply current
39
63
IITT54195
llTT74195
mA
Vee = MAX. See Note 2
2. With all outputs open. shift/load grounded, and 4.5V applied to the J, K, and data inputs, lee is measured
by applying a momentary ground, followed by 4.5V, to clear, and then applying a momentary ground, followed
by 4.5V, to clock.
, All typical values are at Vee = 5V, TA = 25°e.
For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at & time.
2
SWITCHING CHARACTERISTICS. Vee = 5V, TA = 25°e, N
Parameter
f max
Maximum input clock frequency
tpHL
Propagation delay time,
high-to-Iow-Ievel output from
clear
tpLH
Propagation delay time,
low-to-high-Ievel output from
clock
tpHL
Propagation delay time,
high-to-Iow-Ievel output from
clock
Min
30
.
Typ
= 10
Max
39
Unit
Test Conditions
MHz
eL = 15pF, RL = 400.n.
19
30
ns
eL = 15pF, RL = 40011
6
14
22
ns
eL = 15pF, RL = 40011
7
17
26
ns
eL = 15pF, RL = 400.n.
3-244
ITT54195, ITT74195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
functional block diagram
PARALLEL OUTPUTS
/\
laA
ac
as
aA
ac
as
CLOCK
R
SHIFT/\J
Kj
CLEAR
CLEAR
\A
CJ~~OL --v-SERIAL
.....--!---lR
R
R
OA
CLEAR
B
OJ
C
00
CLEAR
CLEAR
~------------------------~v~------------------------~
PARALLEL INPUTS
INPUT
typical clear. shift. and load sequences
CLOCK
SERIAL {
J
,,
--+---''l'''-----------r'--+--------:=+:==~!i'""I__+'~=========:::;_:'
--;:~=========
Ll.--i
,
,
INPUTS
R T/LOAD:
SHIF
PARALLEL
B
,
L
,
--+-----+---------~~'--+---------L ,
INPUTS
QA
OUTPUTS
--+----+:---------~~'--+---------I
DATA
as
---~~
----;
______
~~,',._ _~-----~,r---,
:::"+;___-+:_--,r---l
:: :::J
---,
I
:
1-----------
I
~'----~
I
I'
SERIALSHIFT _ _ _ _ _..,
CLEAR
LOAD
3--245
,
t---SERIALSHIFT_
CLOCK
ITT
-----
ITT54HOO, ITT74HOO
QUADRUPLE 2-INPUT POSITIVE NAND GATES
SEMICONDUCTORS
QUADRUPLE 2-INPUT
POSITIVE NAND GATES
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA(0
@U
IB@
@4B
Ilev
@)4A
@GND
VCCG
@3B
2l!0
0
0
2A®
2B0
POSITIVE
LOGIC
ii!
3A
3 ii!
POSITIVE LOGIC: i! =)!;B
= AB
schematic (each gatel
.----_'""""""----_--0 Vee
2.8 kO
760 0
580
OUTPUT
ii!
A I
GND
~
INPUTS
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Min
Supply Voltage Vec: 54HOO Circuits ......................................................................
74HOO Circuits ......................................................................
Normalized Fan-Out From Each Output, N ........................................ ;..................... .
Operating Free-Air Temperature Range, TA : 54HOO Circuits ............................ .
74HOO Circuits ............................ .
4.5
4.75.
5
5
-55
0
25
25
3-246
Nom Max
5.5
5.25
10
125
70
Unit
V
V
DC
DC
ITT54H 00, ITT74HOO
QUADRUPLE 2-INPUT POSITIVE NAND GATES
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Unit
Test Conditions 2
Vin (1 )
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
O.S
V
V1
Input Clamp Voltage
-1.5
V
VIN Ii = -S mA
V out (1 )
Logical 1 output voltage
V
Vee = MIN. V in = O.S V.
Iload = -500 uA
Vout(O)
Logical 0 output voltage
0.4
V
Vee = MIN. V in = 2 V.
Isink = 20mA
lin(O)
Logical 0 level input current
(each input)
-2
mA
Vee = MAX. V in = 0.4 V
lin(1 )
Logical 1 level input current
(each input)
50
uA
Vee = MAX. V in = 2.4 V
1
mA
Vee - MAX. V in - 5.5 V
-100
mA
Vee = MAX
"
2
V
2.4
lOS
Short-circuit output current 3
lee(O)
Logical 0 level supply current
-40
26
40
mA
Vee = MAX. V in = 4.5 V
lee(1)
Logical 1 level supply current
10
16.S
mA
Vee = MAX. Vin = 0
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°C. N = 10
Parameter
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to
logical 0 level
6.2
10
ns
eL=25pF.R L =2S0Q
tpd1
Propagation delay time to
logical 1 level
5.9
10
ns
eL = 25 pF. RL = 2S0 Q
1
2
3
All typical values are at VCC = 5 V. TA = 25°C.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3-247
I
CIRCUIT TYPES ITT54H01, ITT74H01
ITT
....
-----
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
SEMICONDUCTORS
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
DUAL - IN - LINE PACKAGE
PIN ~DNFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
lAG
@4i!
IBG)
@4B
Ilev
@4A
@GND
VCCG
210
@3B
0
0
2A0
2B0
POSITIVE
LOGIC
3A
3l
POSITIVE
l = AB
LOGIC:
i!=AB
\"
schematic (each gate)
NOTE: Component values shown are nominal.
recommended operating conditions
Min
Nom
Max
Supply Voltage V CC:
4.5
4.75
5
5
-55
25
25
5.5
5.25
10
125
70
54H01 Circuits ........................................................................................ ..
7 4HO 1 Circuits ......................................................................................... .
Normalized Fan-Out From Each Output, N .................................................................................. ..
Operating Free-Air Temperature Range: 54H01Circuits ........................................................ .
74H01 Circuits ........................................................ .
3-248
0
Unit
1<
V
V
°c
°c
CIRCUIT TYPES ITT54H01, ITT74H01
QUADRUPLE 2-INPUT POSITIVE NAND GATES
(WITH OPEN-COLLECTOR OUTPUT)
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Test Conditions 2
Unit
V
V in (l)
Logical 1 input voltage required
at both input terminals to ensure
logical 0 (on) level at output
2
·Vin(O)
Logical 0 input voltage requ·ired
at either input terminal to ensure
logical 1 (off) level at output
O.S
V
V1
Input Clamp Voltage
-1.5
V
10ut(1 )
Output reverse current
250
uA
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
lin(O)
Logical 0 level input current
(each input)
-2
mA
= Min. Ii = -S mA
Vee = MIN. Vin = O.SV.
Vout (l) = 5.5V
Vee = MIN. Vin = 2V.
Isink = 20 mA
Vee = MAX. Vin = 0.4V
lin(l )
Logical 1 level input current
(each input)
50
uA
Vee
1
mA
Vee
lee(O)
Logical 0 level supply current
26
40
mA
lee(1)
Logical 1 level supply current
6.S
10
mA
= MAX. Vin = 2.4V
Vee = MAX. V in = 5.5V
Vee = MAX. V in = 4.5V
Vee = MAX. Vin = 0
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter
tpdO
tpd1
Propagation delay time to logical
Min
Typ
Max
Unit
Test Conditions
7.5
12
ns
eL
= 25 pF. RL = 2S011
10
15
ns
eL
= 25 pF. RL = 2S011
o level
Propagation delay time to logical
1 level
, All typical values are at Vee = 5V. TA = 25°C.
2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3-249
ITT
----CIRCUIT TYPES ITT54H04, ITT74H04
HEX INVERTERS
SEMICONDUCTORS
HEX INVERTERS
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN -LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
lAG)
@Ii!
SA
2i!G)
@)SA
Si!
2A0
@)Si!
VCC
@GND
VCCG
POSITIVE
LOGIC:
3A0
@Sii!
3i!®
' - -____ ®SA
4AG)
G)4i!
i! = A
POSITIVE
LOGIC:i!
=A
schematic (each inverter)
,...---+-----.....--<> Vee
2.8 kn 760 n
58n
INPUT
A
Component values shown are normal.
Recommended Operating Conditions
Min
Supply Voltage V CC: 54H04 Circuits ......................................................................
74H04 Circuits ................................ ;.................................... .
Normalized Fan-Out From Each Output, N ..............................................................
Operating Free-Air Temperature Range, TA: 54H04 Circuits ............................ .
74H04 Circuits ............................ .
4.5
4.75
5
5
-55
0
25
25
3-250
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°c
CIRCUIT TYPES ITT54H04, ITT74H04
HEX INVERTERS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
Test Conditions 2
Unit
V in (1)
Logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
Vin(O)
Logical 0 input voltage
required at input terminal to
ensure logical 1 level at
output
0.8
V
V1 .
Input Clamp Voltage
-1.5
V
Vout(1)
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
0.4
V
lin(O)
Logical 0 level input current
-2
rnA
lin(1 )
Logical 1 level input current
50
uA
= Min Ii = -8 rnA
Vee = MIN. Vin = 0.8 V.
Iload = -500 uA
Vee = MIN. Vin = 2 V.
Isink = 20 rnA
Vee = MAX. Vin = 0.4 V
Vr.r. = MAX. Vin = 2.4 V
1
rnA
Vee - MAX. Vin - 5.5 V
-100
rnA
Vee
lOS
Short-circuit output current 3
2
V
2.4
V
-40
lee(O)
Logical 0 level supply current
10
58
rnA
lee(1)
Logical 1 level supply current
16
26
rnA
SWITCHING CHARACTERISTICS. Vee
Parameter
Vcc
= MAX
Vee = MAX. Vin = 4.5 V
Vee = MAX. Vin = 0
= 5V. TA = 25°C. N = 10
Min
Typ
Max
Test Conditions
Unit
tpdO
Propagation delay time to
logical 0 level
6.5
10
ns
eL
= 25 pF. RL = 280 Q
tpd1
Propagation delay time to
logical 1 level
6
10
ns
eL
= 25 pF. RL = 280 Q
1
2
3
All typical values are at Vee = 5 V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one outPl.t should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3-251
_
I
ITT54H05,ITT74H05
mm _
HEX INVERTERS
(WITH
OPEN-COLLECTOR
OUTPUT)
.L.L
_
_
_
_
SEMICONDUCTORS
HEX INVERTERS (WITH OPEN-COLLECTOR
OUTPUT)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
DUAL-IN -LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA(0
@Ii!
2i!G)
@SA
2A@
@Si!
VCC
vcc@
@GND
3A0
@Si!
3i!@
0
4AG)
G)4i!
POSITIVE
SA
LOGIC:
i!
SA
=A
POSITIVE
LOGIC:
schematic (each inverter)
. - - -_ _- - - - 0
2.8 kn
INPUT
A
NOTE:
Vee
760n
L.....4~-_+__oGND
Component values shown are normal.
recommended operating conditions
Min
Supply Voltage VCC: 54H05 Circuits ......................................................................
74H05 Circuits ......................................................................
Normalized Fan-Out From Each Output. N ..............................................................
Operating Free-Air Temperature Range. TA: 54H05 Circuits ............................ .
74H05 Circuits ............................ .
4.5
4.75
-55
0
3-252
Nom Max
5
5
25
25
5.5
5.25
125
70
10
Unit
V
V
°c
°c
ITT54H05, ITT74H05
HEX INVERTERS (WITH OPEN-COLLECTOR OUTPUT)
ELECTR ICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typl
Max
Test Conditions 2
Unit
Vin (1 )
Logical 1 input voltage
required at input terminal to
ensure logical 0 (on) level at
output
Vin(O)
Logical 0 input voltage
required at input terminal to
ensure logical 1 (off) level at
output
0.8
V
V1
I nput Clamp Voltage
-1.5
V
lout(1 )
Output reverse current
250
uA
Vout(O)
Logical 0 output voltage (on
level)
0.4
V
Vee = MIN. Yin
I sink
20 mA
lin(O)
Logical 0 level input current
-2
mA
Vee
lin(1 )
Logical 1 level input current
50
uA
Vee
1
mA
Vec
2
V
= Min Ii = -'8 rnA
Vee = MIN. Yin = 0.8 V.
Vee
Vout (1)
lec(O)
Logical 0 level supply current
40
58
mA
lee(1)
Logical 1 level supply current
16
26
mA
SWITCHING CHARACTERISTICS. Vee = 5V. TA
Parameter
1
2
Min
=
= 5.5 V
= 2 V.
= MAX. Yin = 0.4 V
= MAX. V in = 2.4 V
= MAX. Vin = 5.5 V
Vee = MAX. Vin = 4.5 V
Vee = MAX. Yin = 0
= 25°C
Typ
Max
Test Conditions
Unit
tpdO
Propagation delay time to
logical 0 level
7.5
12
ns
CL
= 25 pF. R L = 280 Q
tpd1
Propagation delay time to
logical 1 level
10
15
ns'
CL
= 25 pF. RL = 280 Q
All typical values are at Vee = 5 V. TA = 25°e.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3-253
ITT
----CIRCUIT TYPES ITT54H10, ITT74H10
TRIPLE 3-INPUT POSITIVE NAND GATES
SEMICONDUCTORS
TRIPLE 3-INPUT POSITIVE NAND GATES
DUAL-I N - LI NE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0
@IC
IBG)
@)3t
ItG)
@3C
vccG
0
IC
It
@GND
210
2A
VCC
3B
@3B
--'--_TTT·~ ..
2B0
POSITIVE
-L-0
3A
®2C
LOGIC
POSITIVE
LOGIC:
t =ABC
schematic (each gate)
,----_---_._-0 vee
2,8 kG
470 Q
~
4 kCl
GND
INPUTS
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Min
Supply Voltage VCC: 54H 10 Circuits ......................................................................
74H 1 0 Circuits ......................................................................
Normalized Fan-Out From Each Output, N ..............................................................
Operating Free-Air Temperature Range, TA: 54H10 Circuits ............................ .
7 4H 10 Circuits ............................ .
4.5
4.75
5
5
-55
0
25
25
3-254
Nom Max
5.5
5.25
10
125
70
Unit
V
V
°c
°C
CIRCUIT TYPES ITT54H10, ITT74H10
TRIPLE 3-INPUT POSITIVE NAND GATES
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
2
Unit
Test Conditions 2
V in (l )
logical 1 input voltage
required at all input
terminals to ensure logical 0
level at output
V
Vin(O)
logical 0 input voltage
required at any input
terminal to ensure logical 1
level at output
O.S
V
V1
Input elamp Voltage
-1.5
V
Min Ii = -S mA
Vout( 1)
logical 1 output voltage
V
Vout(O)
Logical 0 output voltage
0.4.
V
lin(O)
Logical 0 level input current
(each input)
-2
mA
= MIN. Vin = O.S V.
= -500 uA
Vee = MIN. Vin = 2V.
Isink = 20 mA
Vee = MAX. Vin = 0.4 V
lin(1)
Logical 1 level input current
(each input)
50
uA
Vee
1
mA
Vee
-100
mA
2.4
Vee
Iload
lOS
Short-circuit output current 3
lee(O)
Logical 0 level supply current
19.5
30
mA
lee(l)
Logical 1 level supply current
7.5
12.4
mA
= MAX. Vin = 2.4 V
= MAX. Vin = 5.5 V
Vee = MAX
Vee = MAX. Vin = 4.5 V
Vee = MAX. Vin = 0
Unit
Test Conditions
-40
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter
Min
Typ
Max
= 25 pF. RL =
tpdO
Propagation delay time to
logical 0 level
6.3
10
ns
eL
tpdl
Propa'gation delay time to
logical 1 level
5.9
10
ns
eL=25pF.R L =2S0Q
1
2
3
2S0 Q
All typical values are atV cc = 5 V. TA = 25°C.
For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3- 255
ITT54H11,ITT74H11
- ITT- - - - TRIPLE 3-INPUT POSITIVE AND GATES
SEMICONDUCTORS
TRIPLE 3-INPUT POSITIVE AND GATES
DUAL- IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA0)
@IC
IB0
@3r
IC
IrG)
@)3C
Ii!:
@GND
3C
VCC
vccG
3B
@3B
POSITIVE
LOGIC
3A
0
3A
0
2C
POSITIVE
i!:=ABC
LOGIC:
r
= ABC
schematic (each gate)
2.8kO
I kG
7600
580
INPUTS
NOTE: Component values shown are nominal.
Recommended Operating Conditions
Min
Nom Max
54H 11 Circuits ..................................................................... .
74H11 Circuits ..................................................................... .
4.5
4.75
5
5
Normalized Fan-Out From Each Output, N ............................................................. .
Operating Free-Air Temperature Range. TA: 54H 11 Circuits ............................ .
74H 11 Circuits ............................ .
-55
0
25
Supply Voltage V CC:
3-256
25
5.5
5.25
10
125
70
Unit
V
V
°C
°0
ITT54H 11, ITT74H 1'1
TRIPLE 3-INPUT POSITIVE AND GATES
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ 1
Max
2
Test Conditions 2
Unit
Vin (1)
logical 1 input voltage
required at all input
terminals to ensure logical 1
level at output
V
Vin(O)
logical 0 input voltage
required at any input
terminal to ensure logical 0
level at output
0.8
V
V1
Input Clamp Voltage
-1.5
V
Vout (1 )
logical 1 output voltage
Vout(O)
Logical 0 output voltage
0.4
V
lin(O)
Logical 0 level input current
(each input)
-2
mA
= Min Ii = -8 mA
Vee = MIN. Yin = 2 V.
Iload = -500 uA
Vee = MIN. Yin = 0.8 V.
Isink = 20 mA
Vee = MAX. Yin = 0.4 V
lin(1 )
Logical 1 level input current
(each input)
50
uA
Vee
1
mA
-100
mA
2.4
V
Vcc
lOS
Short-circuit output current 3
lee(O)
Logical 0 level supply current
30
48
mA
lee(1)
Logical 1 level supply current
18
30
mA
= MAX. Yin = 2.4 V
Vee = MAX. Yin = 5.5 V
Vee = MAX. Yin = 4.5 V
Vee = MAX. Yin = 0
Vee = MAX. Yin = 4.5 V
Unit
Test Conditions
SWITCHING CHARACTERISTICS, Vee
Parameter
-40
= 5V. TA = 25°C. N = 10
Min
Typ
Max
= 25 pF. RL =
tpdO
Propagation delay time to
logical 0 level
8.8
12
ns
eL
tpd1
Propagation delay time to
logical 1 level
7.6
12
ns
eL = 25 pF. RL
1
2
3
=
=
280 Q
= 280 Q
All typical values are at Vee
5 V. TA
25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3-257
_
I
CIRCUIT TYPES ITT54H20, ITT74H20
mm
.L.L _ _ _ _ _....---DUAL4-INPUTPOSITIVE NAND GATES
SEMICONDUCTORS
DUAL 4-INPUT POSITIVE NAND GATES
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FL AT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IA(0
@ID
I;!G)
@)IC
NCG)
®IS
@GND
VCCG
NC0
@2;!
2A®
®2D
2B(2)
0
POSITIVE
LOGIC:
~=
2C
POSITIVE
ABCD
LOGIC:
i! = ABCD
schematic (each gate)
r------ov,c
INPUTS
...
LL---o~=:::::======j-
Notes:
1. Component values shown are nominal.
2. Both expander inputs are used simultaneously for expanding.
3. If expander is not used leave X and X pins
open.
4. Expander inputs X and X are functional on
the ITT54H53 and ITT74H53 circuits only.
3-269
-oGNO
Make no external connection to X and X pins
ofthe ITT54H54 and ITT74H74.
5. A total of four ITT54H60/lTT74H60 expander gates may be connected to the ex- •
pander inputs.
ITT54H53, ITT54H54, ITT74H53, ITT74H54
EXPAN DABLE 2-2-2-3-INPUT AN D-OR-INVERT GATES
recommended operating conditions
Min
Supply Voltage Vee:
Nom Max
Unit
ITT54H53. ITT54H54 .............................................................,.. .
ITT74H53.ITT74H54 .................................................................
Normalized Fan-Out From Each Output. N ......................................................................
4.5
4.75
5
5
5.5
5.25
10
V
V
Operating Free-Air Temperature Range. TA
-55
0
25
25
125
70
°e
°e
ITT54H53.ITT54H54 ....................... .
ITT74H53.ITT74H54 ....................... .
ElECTR ICAl CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Vin (1 )
Min
Logical 1 input voltage required
at all input terminals otone AN D
section to
output
~nsure
Typ'
Max
Test Conditions
Unit
2
V
2
logical 0 at
Vin(O)
Logical 0 input voltage required
at one input terminal of each
AN D section to ensure logical 1
at output
O.S
V
V1
Insure elamp Voltage
-1.5
V
Vout (1 )
Logical 1 output voltage
Vout(O)
Logical 0 output voltage
0.4
V
lin(O)
Logical 0 level input current
(each input)
-2
mA
= MIN. Ii = -SmA
Vee = MIN. Vin = O.SV.
Iload = -500uA
Vee = MIN. Vin = 2V.
Isink = 20mA
Vee = MAX. V in = 0.4V
lin(1)
Logical 1 level input current
(each input)
50
uA
Vee
1
mA
Vee
-100
mA
2.4
V
lOS
Short-circuit output current
lee(O)
Logical 0 level supply current
9.4
14
mA
lee(1 )
Logical f level supply current
7.1
11
mA
3
-40
Vee
= MAX. V in = 2.4V
= MAX. V in = 5.5V
Vee = MAX
Vee = MAX. V in = 4.5V
Vee = MAX. V in = 0
, Duration of short-circuit test should not exceed 1 second
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type. Expander pins are open.
3 All typical values are at Vee = 5V. TA = 25° e.
2
3-270
ITT54H53, ITT54H54, ITT74H53, ITT74H54
EXPANDABLE 2-2-2-3-INPUT AND-OR-INVERT GATES
ELECTRICAL CHARACTERISTICS (ITT54H53 circuits only) using expander inputs.
Vee
4.5V. TA
-55°e
=
=
Parameter
Min
Max
Typ'
Test Conditions 2
Unit
linX
Expander-node input current
-5.B5
mA
Vx= 1.4V
VBE(Q)
Base-emitter voltage of output
transistor Q
1.1
V
Isink = 20mA. 11 = 700uA.
R1 = 0
Vout (1 )
Logical 1 output voltage
V
Iload = -500uA.1 1 =
320uA.
12 = -320uA
Vout(O)
Logical 0 output voltage
V
Isink = 20mA.1 1 = 470uA.
R1 = 6Bn
2.4
0.4
ELECTRICAL CHARACTERISTICS (ITT74H53 circuits only) using expander inputs.
Vee = 4.75V. TA = ooe
Parameter
Min
Typ
Max
Unit
Test Conditions
linX
Expander-node input current
-6.3
mA
Vx = 1.4V
VBE(Q)
Base-emitter voltage of output
transistor Q
1
V
Isink =·20mA.1 1 = 1.1mA.
R1 = 0
Vout (1)
Logical 1 output voltage
V
Iload = -500uA. 11 =
570uA.
12 = -570uA
Vout(O)
Logical 0 output voltage
V
Isink = 20mA • .I 1 = 600uA.
Rt = 63..n.
2.4
0.4
SWITCHING CHARACTERISTICS. Vee
Parameter
= 5V. TA = 25°e. N = 10. expander pins are open
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagatio'l delay time to logical
o level
6.2
11
ns
CL = 25 pF. RL = 2BOn
tpd1
Propagation delay time to logical
1 level
7
11
ns
CL = 25 pF. RL = 2BOn
SWITCHI NG CHARACTER ISTICS. (ITT54H 53/1TT7 4H53 circuits only)
Vee
5V.T A
25°e.N
10.eX
15pF
=
=
=
=
Parameter
Min
Typ
Max
Unit
Test Conditions
tpdO
Propagation delay time to logical
o level
7.4
ns
CL = 25 pF. RL = 2Bon
tpd ,.
Propagation delay time to logical
1 level
11.4
ns
CL = 25 pF. RL = 2BOn
ITT54H60
DUAL4-INPUT EXPANDER
(FOR USEWITH ITT54H50.ITT54H53. CIRCUITS)
_.ITT- - - - SEMICONDUCTORS
DUAL 4-INPUTEXPANDER
DUAL-IN-L1NE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
IXCV
@2X
1110
@2X
lAG)
@2D
@GND
VCCG
POSITIVE LOGIC:
IB0
@2C
IC0
®2B
IDG)
0
2A
POSITIVE LOGIC:
X=ABCD
X=ABCD
WHEN CONNECTED TO X AND
IT17450 OR 7453
WHEN CONNECTED TO X AND X PINS OF
ITT54H50,ITT54H53, or ITT54H55 CIRCUIT.
CPINS OF
schematic (each expander)
2.8 kn
OUTPUT X
(See Note 2)
OUTPUT X
(See Note
n
,AByC 0,
L - - - - - c GND
INPUTS
Notes:
recommended operating conditions
Supply Voltage V CC ............................. 4.5Vto 5.5V
Maximum numberof expanders that may be
fanned-in to one ITT54H50. ITT54H 53 circuit ... 4
3-272
1. Connect to X input of ITT54H 50. ITT54H53
circuit.
2. Connect to X input of ITT54H50.ITT54H53
circuit.
3. Component values shown are nominal.
ITT54H60
DUAL 4-INPUT EXPANDER
(FOR USE WITH ITT54H50. ITT54H53. CIRCUITS)
ELECTRICAL CHARACTERISTICS (unless otherwise noted TA
Parameter
Vin (l)
Logical 1 input voltage required
at all input terminals to ensure
output is in the on state
Vin(O)
Logical 0 input voltage required
at any input terminal to ensure
output is in the off state
Min
Typ
loff
Off-state output current
Ion
On-state output current
lin(O)
Logical 0 level input current
(each input)
Logical 1 level input current
(each input)
lin(l )
Unit
0.8
V
0.4
V
2V.
4.5V. V in
Vee
V 1 = lV.lon = 5.85mA.
T A =-55°e
0.4
V
Vee = 5.5V. V in = 2V.
V 1 = 0.6V.l on = 7.85mA.
TA = 125°C
320
uA
Vce - 4.5V. V in - 0.8V
V 1 = 4.5V.R = 575n
TA = -55°C
uA
Vee - 4.5V. V in - 2V.
V, = lV. TA = -55°C
mA
Vee - 5.5V. V in - 0.4V
50
uA
Vee - 5.5V. V in - 2.4V
1
mA
Vee = 5.5V. V' n = 5.5V
Vee - 5.5V. V in = 4.5V.
V 1 = 0.85V
Vee - 5.5V, V in -:- O.
-470
-2
lee(on)
On-state supply current
1.9
3.5
mA
lee(ott)
Off-state supply current
3
4.5
mA
1
Test Conditions
V
2
On-state output voltage
Von
= -55°e to 125°e)
Max
All typical values are at Vee = 5V. T A = 25° e.
V 1 = 0.85V
OUTPUT CAPACITANCE. Vee and GND terminals open, TA = 25°e
Parameter
ex
I
Effective capacitance of output
transistor 01
Min
Typ
1.3
3-273
Max
Unit
pF
Test Conditions
f = 1 MHz
__
ITT
ITT54H72, ITT74H72
.__________________J_-K__
M_A_s_T_E=R~-S_L_.A_V_E_F_L_IP_-_F~LO~P-mS
SEMICONDUCTORS
J-K MASTER-SLAVE FLIP-FLOPS
These J- K flip-flops are based on the master-slave
principle. The AND gate inputs for entry into the
master section are controlled by the clock pulse.
The clock pulse also regulates the circuitry which
connects the master and slave sections. The sequence of operation is as follows:
DUAL- IN- LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
1. Isolate salve from master
2. Enter information from AND gate inputs to
master
3. Disable AN D gate inputs
4. Transfer information from master to slave.
Logical state of J and K inputs must not be allowed
to change when the clock pulse is in a high state.
HIGH
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
I
I
I
,
LOW
MINIMUM
: . - -tsetup
I
I
----+1
KI(0
@K3
CLOCKeD
@K2
CLOCK WAVEFORM
PRESET
0 ....+H-t--'
@Q
logic
vcc8
@GNC
TRUTH TABLE
CLEAR(D"'-Hh
t n +1
tn
Notes:
J
K
Q
0
0
Qn
NeG)
JIG)
0
1
0
POSITIVE LOGIC:
1
0
1
1
1
Qn
1.
2.
3.
4.
@Q
'----..... G)J3
0
J2
LOW INPUT TO PRESET SETS Q TO LOGICAL I
LOW INPUT TO CLEAR SETS Q TO LOGICALO
PRESET OR CLEAR ARE INDEPENDENT
OF CLOCK
J = J 1 • J2 • J3
K = K 1 • K2 • K3
tn = Bit time before clock pulse.
tn + 1 = Bit time after clock pulse.
3-274
ITT54H72, ITT74H72
J-K MASTER-SLAVE FLIP-FLOPS
recommended operating conditions
Min
Short Voltage V CC:
ITT54H72 ..............•.........................................................................
ITT74H72 ........................................................................................
Operating Free-Air Temperature Range. TA: ITT54H72.............................................
ITT74H72.............................................
Normalized Fan-Out From Each Output. N ......................................................................
Nom Max
4.5
4.75
- 55
0
5
5
25
25
Width of Clock Pulse. tp(clock) (See Figure 77) ..............................................................
12
Width of Preset Pulse. tp(preset) (See Figure 78) ...........................................................
16
Width of Clear Pulse. tp(clear) (See Figure 78) ...............................................................
16
Input Setup Time. tsetup (See Above) .............................................................................. ;::tp(clock)
0
Input Hold Time. t hold .........................................................................................................
5.5
5.25
125
70
10
Unit
V
V
°C
°C
ns
ns
ns
schematic
r---------~~----~----------~.-----~--~------~------ovcc
58 Cl
760 Cl
2.8 kCl
2.8 kCl
760 Cl
58 Cl
Qo--.........
PRESET
KI
0---+-....-------'
Jl
o-----4~
J2
J3
GND
Component val.,., \how" 011 neminG!.
CLOCK
3-275
ITT54H72, ITT74H72
J-K MASTER-SLAVE FLIP-FLOPS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
Typ'
Max
2
Unit
Test Conditions 2
V in (1)
Input voltage required to ensure
logical 1 at any input terminal
V
Vin(O)
Input voltage required to ensure
logical 0 at any input terminal
Vout (l )
Logical 1 output voltage
V
Vee = MIN. Iload = -500uA
Vout(O)
Logical 0 output voltage
0.4
V
Vee = MIN. I sink = 20mA.
V1
Input elamp Voltage
-1.5
V
Vee = MIN. 11 = -SmA
lin(O)
Logical 0 level input current at
J 1. J2. J3. K 1. K2. K3. or clock
-2
mA
Vee = MAX. V in = 0.4V
lin(O)
Logical 0 level input current at
preset or clear
-4
mA
Vee = MAX. V in = O.4V
lin(l)
Logical 1 level input current at
J 1. J2. J3. K 1. K2. or K3
50
uA
Vee = MAX. V in = 2.4V
1
mA
Vee = MAX. V in = 5.5V
Logical 1 level input current at
clock
50
uA
Vee = MAX V in = 2.4V
1
mA
Vee = MAX. V in = 5.5V
Logical 1 level input current at
preset or clear
100
uA
Vce = MAX. V in = 2.4V
1
rnA
Vee = MAX. V in = 5.5V
-100
mA
Vee = MAX. V in = 0
25
mA
Vee = MAX
O.S
2.4
lin(l)
lin(l)
lOS
Short-circuit current 3
lee
Supply current
SWITCHING CHARACTERISTICS, Vee
Parameter
-40
16
= 5V. TA = 25°e. N = 10
Min
Typ
25
30
Max
Unit
Test Conditions
MHz
eL = 25 pF. RL = 2S0n
13
ns
eL = 25 pF. RL = 2S0n
12
24
ns
eL = 25 pF. RL = 2S0n
fclock
Maximum clock frequency
tpdl
Propagation delay time to logical
1 level from clear or preset to
output
6
Propagation delay time to logical
tpdO
V
o level from clear or preset to
output
tpdl
tpdO
Propagation delay time to logical
1 level 1i'om clock to output
6
14
21
ns
CL = 25 pF. RL = 2S0n
Propagation delay time to logical
10
22
27
ns
CL = 25 pF. RL = 2S0n
o level from clock to output
, All typical values are at Vee = 5V. TA = 25°e.
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions
2
3
for the applicable device type
Not more than one output should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3-276
_
ITT
CIRCUIT TYPES ITT54H73, ITT74H73
. . _ _ _ _ _ _ _D_U_A_L_J_-_K_M_A_S_T_E_R_-S_L_A_V_E_F_L_IP_-_FL_O_P_S
SEMICONDUCTORS
DUAL J-K MASTERSLAVE FLIP-FLOPS
DUAL -I N - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
I
. CLOCK
These J-K flip-flops are based on the master-slave
principle. The AN D gate inputs for entry into the
master section are controlled by the clock pulse.
The clock pulse also regulates the circuitry which
connects the master and slave sections.
The sequence of operation is as follows:
1. Isolate slave from master
2. Enter information from AND gate inputs to
master
3. Disable AND gate inputs
4. Transfer information from master to slave.
Logical state of J and K inputs must not be allowed
to change when the clock pulse is in a high state.
I
10
CLEAR
10
IK
GND
CL8cK
20
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
Logic
@IJ
CL6cK0
TRUTH TABLE
tn +1
J
0
0
1
1
NOTES 1.
2.
K
®IQ
®IO
CLJAR0
tn
U
On
0
1
0
1
0
1
On
tn = Bit time before clock pulse.
tn + 1
Bit time after clock pulse.
@GND
VCCG
@2K
CL&:K0
=
CLlAR@
2J0
HIGH
POSITIVE LOGIC:
LOW INPUT TO CLEAR SETS 0 TO LOGICAL 0
CLEAR IS INDEPENDENT OF CLOCK
I
I
LOW
I
I
MINIMUM
I
:4--- t setup -----..1
CLOCK WAVEFORM
recommended operating conditions
MIN
Supply Voltage V CC ITT54H 73 Circuits .~: ...........................................(...........
4.5
ITT74H73 Circuits .. ~...................................................... 4.75
Operating Free-Air Temperature Range, TA : ITT54H 73............................. -55
ITT74H73.............................
0
Normalized Fan-Out from Each Output, N .......................................................
'Width of Clock Pulse, tp(clock)...........................................................................
12
Width of Clear Pulse, tp(clear) ...............................................................,...........
1.~
Input Setup Time, tsetup .................................................................................... tp(clock)
Input Hold Time, thold ..........................................................................................
3-277
0
TYP MAX UNIT
5
5
25
25
5.5
5.25
125
70
10
V
V
°C
°C
ns
ns
CIRCUIT TYPESITT54H73, ITT74H73
DUAL J-K MASTER'-SLAVE FLIP-FLOPS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Vin(1)
Input voltage required to
ensure logical 1 at any input
terminal
,Vin(O)
Input voltage required to
ensure logical 0 at any input
'terminal
V1
Input elamp Voltage
Vout (1)
Logical 1 output voltage
Min
Typ'
Max
2
Unit
Test Conditions 2
V
O.S
V
-1.5
V
2.4
V
= Min Ii = -S mA
Vee = MIN.lload =
Vee
-500uA
Vout(O)
Logical 0 output voltage
0.4
V
Vee
mA
= MIN.l sink = 20
lin(O)
Logical 0 level input current
atJ. K. or clock
-2
mA
Vee
= MAX. Vin = 0.4 V
lin(O)
Logical 0 level input current
at clear
-4
mA
Vee
= MAX. Vin = 0.4 V
lin(1 )
Logical 1 level input current
atJ or K
50
].lA
1
mA
Logical 1 level input current
at clock
50
].lA
1
mA
Logical 1 level input current
at clear
100
].lA
1
mA
= MAX. Vin = 2.4 V
Vee = MAX. Vin = 5.5 V
Vee = MAX. Vin = 2.4 V
Vee = MAX. Vin = 5.5 V
Vee = MAX. Vin = 2.4 V
Vee = MAX. Vin = 5.5 V
Vee = MAX. V in = 0
Vee = MAX
lin(1 )
lin(1)
lOS
Short-circuit output current 3
Ice
Supply current
1
2
3
-40
32
-100'
mA
50
mA
Vee
All typical values are at Vee = 5 V. TA = 25°C.
For conditions shown as MIN'or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
'
Not more than one output'should be shorted at a time. and duration of short-circuit should not exceed 1 second.
3-278
CIRCUIT TYPES ITT54H73, ITT74H73
DUAL J-K MASTER-SLAVE FLIP-FLOPS
SWITCHING CHARACTERISTICS. VCC = 5V. TA = 25°C. N = 10
Parameter
Min
'Typ
25
30
Max
Unit
Test Conditions
n
25pF. RL = 280 n
MHz
CL = 25pF. RL = 280
13
ns
CL =
12
24
ns
CL = 25pF. RL = 280
n
6
14
21
ns
CL = 25pF. RL = 280
n
10
22
27
ns
CL = 25pF. RL = 280
n
fclock
Maximum clock frequency
tpd1
Propagation delay time to
logical 1 level from clear to
output
6
tpdO
Propagation delay time to
logical 0 level from clear to
output
tpd1
Propagation delay time to
logical 1 level from clock to
output
tpdO
Propagation delay time to
logical 0 level from clock to
output
schematic (each flip·flop)
1---.,....-......- - - -........:....--<,-.....- -.....--1~ Vee
58
Q
760 Q
2,8 kQ
2,8 kQ
760 Q
58
Q
TO OTHER
FLlP·FLOP
Qo--~-+
H---OO
TO OTHER
CLOCK
Component values shown are nominal
3-279
FLlP·FLOP
ITT
----CIRCUIT TYPES ITT54H74, ITT74H74
DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SEMICONDUCTORS
DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
•
Maximum Clock Frequency: 35 Megahertz
•
Positive-Edge Triggering
•
High-Fan Out, Low-Impedance, Totem-Pole
Outputs
•
Input Clamping Diodes Simplify System
Design
I CLEAR
2 CLEAR
2D
ICLOCK
• Typical Power Dissipation: 75 Milliwatts per
Flip-Flop
These monolithic, high-speed, dual. edge-triggered
flip-flops utilize TTL circuitry to perform Ootype flipflop logic. Each flip-flop has individual clear and
preset inputs. and also complementary Q and IT
outputs.
Information at input 0 is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level of the clock
pulse and is not di rectly related to the transition
time of the positive-going pulse. When the clock
jnput is at either the high or low level. the O-input
signal has no effect.
logic
TRUTH TABLE
(Each Flip-Flop)
t n +1
I PRESET
2CLOCK
IQ
2 PRESET
GND
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
I CLOCK
CD
lOG)
a
L
L
H
H
H
L
@
I PRESET
®IQ
I CLEAR
0
®
Vcc
0
2 CLEAR
0
@ GND
@ 2Q
2D0
INPUT OUTPUT OUTPUT
D
Q
2 CLOCK
CD
0
IQ
2Q
0 2 PRESET
ASYNCHRONOUS INPUTS:
H = high level. L = low level
Notes:
VCC
ID
• Fully Compatible with most TTL and DTL
Circuits
tn
DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
LOW INPUT TO PRESET" SETS Q TO HIGH LEVEL
LOW INPUT TO CLEAR SETS Q TO LOW LEVEL
PRESET AND CLEAR ARE INDEPENDENT OF CLOCK
A. tn = bit time before clock pulse.
B. t n+ 1 = bit time after clock pulse.
3-280
CIRCUIT TYPES ITT54H74, ITT74H74
DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
These circuits are fully compatible for use with
most TTL or DTL circuits. Input clamping diodes
are provided to minimize transmission line effects
and thereby simplify systems design. A full fan-out
to 10 normalized Series 54H17 4H loads is available
from each of the outputs in the low-level condition.
In the high-level state. a fan-out of 20 is available
to facilitate tying unused inputs to used inputs.
Maximum clock frequency is 35 megahertz. with
a typical power dissipation of 75 milliwatts per flipflop.
The ITT54H74 is characterized for operation over
the full military temperature range of -55°C to
125°C; the ITT74H74 is characterized for operation from OOCto 70°C.
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V IH
2
V
Low-level input voltage
O.S
V
-1.5
V
V OH
High-level output voltage
VOL
Low-level output voltage
2.4
3.5
0.22
V
004
V
50
uA
1
mA
100
uA
1
mA
High-level input current into
clear
150
uA
1
mA
IlL
Low-level input current into
preset or D
-2
IlL
Low-level input current into
clear or clock
lOS
Short-circuit output current
lee
Supply current
High-level input current into D
High-level input current into
preset or clock
3
Test Conditions 2
Unit
Input elamp Voltage
IIH
3
Max
1
VL
IIH
2
High-level input voltage
Typ
V IL
IIH
1
Min
-40
= MIN. Ii = -S mA
Vee = MIN.I OH = -1 mA
Vee = MIN.I OL = 20 mA
Vee = MAX. VI = 2AV
Vee = MAX. VI = 5.5V
Vee = MAX. VI = 2.4V
Vee
Vee
mA
= MAX. VI
Vee = MAX. VI
Vee = MAX. VI
Vee = MAX. VI
= 5.5V
= 2.4V
= 5.5V
= O.4V
-4
mA
Vee
= MAX. VI = O.4V
= MAX
= MAX
-100
mA
Vee
30
42
mA
Vee
30
50
ITT54H7 4
ITT74H7 4
All typical values are at Vee = 5V. TA = 25°e.
.
For conditions shown as MIN or MAX.use the appropriate value specified under recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time. and duration of short-circuit test should not exceed 1 second.
3-281
CIRCUIT TYPES ITT54H74, ITT74H74
DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SWITCHING CHARACTERISTICS, VCC
Parameter
= 5V. TA = 25°C. N =
Min
Typ
35
43
1
10
Max
Unit
Test Conditions
2
f max
Maximum clock frequency
MHz
CL
tpLH
Propagation delay time.
low-to-high-Ievel output. from
clear or preset inputs
20
ns
CL
= 25 pF. RL = 280n
= 25 pF. RL = 280n
tpHL
Propagation delay time.
high-to-Iow-Ievel output. from
clear or preset inputs
30
ns
CL
= 25 pF. RL = 280fl
tpLH
Propagation delay time.
low-to-high-Ievel output. from
clock input
4
8.5
15
ns
CL
= 25 pF. RL = 280n
tpHL
Propagation delay time.
high-to-Iow-Ievel output. from
clock input
7
13
20
ns
CL
= 25 pF. RL = 280fl
schematic (each flip-flop)
r---._--------------~----~--------._~--Q
PRESETo-.----.-----+---4--------~
TO OTHER
FLIP-FLOP
~_---o
CLEAR
vee
Q OUTPUT
o-~H-------'
CLOCK o-_~~--.J
.-~--o Q OUTPUT
TO OTHER
FLIP-FLOP
Do-....-I-----'
'-~~~----~----~~--------~~~GND
Note:
Component values shown are nominal.
3-282
ITT
-----
ITT54H76, ITT74H76
DUALJ-K MASTER-SLAVE FLIP-FLOPS
SEMICONDUCTORS
DUAL J-K MASTER-SLAVE FLIP-FLOPS
These dual J-K flip-flops are based on the masterslave principle. Inputs to the master section are
controlled by the clock pulse. The clock pulse also
regulates the circuitry which connects the master
and slave sections. The sequence of operation is
as follows:
DUAL -I N-LiNE PACKAGE AND FLAT PACKAGE
PIN CONFIGURATION (TOP VIEW)t
IK
I
PRESET
10
I
CLEAR
1. Isolate slave from master
2. Enter information from J and K inputs to
master
3. Disable J and K inputs
4. Transfer information from master to slave.
GND
VCC
2K
2
20
. CLOCK
2
PRESET
Logical state of J and K inputs must not be allowed
to change when the clock pulse is in a high state.
2
CLEAR
POSITIVE LOGIC:
CLOCK WAVEFORM
LOW INPUT TO PRESET SETS 0 TO LOGICAL I
LOW INPUT TO CLEAR SETS 0 TO LOGICAL 0
CLEAR ANO PRESET ARE INDENPENDENT OF ClOCK
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE
SAME FOR ALL PACKAGES.
lOW
tn
logic
J
K
'n+l
a
0
0
an
TRUTH TABLE
0
1
0
1
0
1
1
1
an
Notes:
1. tn
2
= Bit time before clock
In+l "" Bit time after clock pulse
recommended operating conditions
Min
Supply voltage
Vee
ITT54H76
Nom
Max
4.5
5
Normalized fan-out from each output N
Min
5.5
ITT74H76
Nom Max
4.75
5
10
5.25
Unit
V
10
Width of clock pulse. tp(clock)
12
12
ns
Width of preset pulse. tp(preset)
16
16
ns
~tp(clock)
. Width of clear pulse. t p (c1ear)
~tp(clock)
Input setup time. tsetup
0
Input hold time, t hold
-55
Operating free-air temperature range. T A
3-283
1
25
125
0
0
25
70
°e
ITT54H76, ITT74H76
DUALJ-K MASTER-SLAVE FLIP-FLOPS
ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
Min
TVp'
Max
Test Conditions 2
Unit
-_.
Vin (l)
I nput voltage required to ensure
logical 1 afanvinputterminal
Vin(O)
Input voltage required to ensure
logical 0 at any input terminal
Vout (l )
Logica I 1 output voltage
Vout(O)
Logical 0 output voltage
Logical 0 level input current at
lin(O)
2
V
0.8
V
V
Vee= MIN.l load =-500uA
0.4
V
Vee
-2
mA
Vee = MAX. Vin = 0.4V
-4
mA
Vee = MAX. Vin = O.4V
50
uA
Vee = MAX. V in = 2.4V
1
mA
Vee = MAX. V in = 5.5V
100
uA
Vee = MAX. Vin = 2.4V
1
mA
Vee = MAX. V in = 5.5V
-100
mA
Vee = MAX. Vin = 0
50
mA
Vee = MAX. V in = 4.5V
2.4
='
MIN.l sink = 20mA
J. K. or clock
lin(O)
lin(l )
Logical 0 level input current at
clear or preset
Logical 1 level input current at
..
J. K. or clock
lin(l )
Logical 1 level input current at
clear or preset
lOS
Short:circuit output current 3
ICC
Supply current
-40
32
., All typical values are at Vee = 5V. TA = 25° e.
2
3
For conditions shown as MIN or MAX. use the appropriate value specified ~nder recommended operating conditions
for the applicable device type.
Not more than one output should be shorted at a time.
SWITCHING CHARACTERISTICS.
Vce = 5V. TA = 25°e. N = 10
Parameter.
Min
TVp
25
30
tclock
Maximum clock frequency
tpdl
Propagation delavtime to logical
1 level from clear or preset to
output
6
tpdO
Propagation delav time to logical
o level from clear or preset to
output
tpdl
Propagation delav time to logical
1 level from clock to output
Propagation delav time to logical
tpdO
o level from clock to output
Max
Unit
Test Conditions
MHz
eL = 25 pF. RL = 280 n
13
ns
eL = 25 pF. RL = 280 n
12
24
ns
eL = 25 pF. RL = 280 n
6
14
21
ns
eL = 25pF. RL = 280n
10
22
27
ns
eL = 25 pF. RL = 280 n
3-284
ITT54H76, ITT74H76
DUALJ-K MASTER-SLAVE FLIP-FLOPS
schematic (each flip-flop)
.---------~----~----------_e----_1~~------.__e--_o~c
7600
580
Q
PRE SET
2.8 kO
<.8 kO
0--""'''
TO OTHER
FLIP - FLOP
.....---OOQ
0----+--.....-----------'
L---+-+-------iH-_o CLEAR
2.8
2.8
kO
kO
K
580
o-_ _.J
CLOCK
~
TO OTHER
FLIP - FLOP
Component yalues show ..
lUI
nominal.
3-285
Series ITT9000-1, ITT9000-5
_][~~ _____________________
H_IG_H__
S_PE_E_D__TT__L
Package: 14 and 16 lead DIP and Flat Pack
SEMICONDUCTORS
HIGH SPEED SATURATED
TRANSISTOR-TRANSISTOR
LOGIC CIRCUITS
• Single power supply requirements: 5 volts
optimum, 4.5 to 5.5 volts range
o High speed: typical gate propagation delay
time of 7 ns
• High DC noise margin: typically one volt
• 'Added input diodes and low output impedance provides minimum AC noise susceptibility
o Fan Out: 10TTL loads
• Power dissipation: 11mw per NAND gate at
a 50% duty cycle
• Compatible with ITT DTL family and other
DTL and TTL circuits
o NAND gate pin configurations are compati-
ble with DTL
The ITT9000 Series of TTL circuits is designed
to be used in any digital system where good
noise immunity, high spped, medium power
and high fan-out performance is required. The
line is characterized by a broad number of
functions available in a variety of packages.
The basic elements of the family are active low
level output AND gates commonly known as
NAND gates.
Typical high level noise immunity of every
device in the family is 1.9 V and typical low
lev-el noise immunity is 0.9 V. Worst case
immunity is 400 mV over the entire temperature
range. Power dissipation is typically 11 mW per
gate function at a 50% duty cycle, and the
average propagation delay is 7 nanoseconds
per gate function. A single 5 V 10 per cent
power supply is used with the circuits.
The gates were designed to provide low output
impedance in both high and low states which
results in good capacitive drive capability and
good immunity to crosstalk. The output
impedance in the low state is about 10 ohms
and in the high state, about 20 ohms. To further
enhance noise immunity, all' inputs of all
devices incorporate diode clamps which
considerably reduces the ringing which can
result from long lines and impedance mismatches. The binary elements are of a JK, DC
master slace design and will toggle at 40 MHz,
except for the 9000 element. The 9000 has
capacitors purposely incorporated in the
design to increase its set-up time and provide it
with considerable immunity to long clock
skew. Due to the longer set-up time the 9000
toggle frequency is 20 MHz. A common JK
input is incorporated on all binary elements to
provide data entry inhibit! enable. The input to
the clock on each element is buffered to reduce
the clock input loading.
The Vee and ground terminals of all devices
are located on diagonal corners of the package
which allows two degrees of freedom in routing
of power and ground leads on the PC boards.
Special care has been taken in establishing
pin-outs for the flip-flop so as to minimize
cross-overs when laying out common dynamic
functions with these elements. Simple loading
rules are incorporated so that the fan-in and
fan-out capability of each device will be quickly
establ ished.
The ITT9000 series TTL is compatible with DTL
and MSI devices as well as the more complex
functions which will be available in the future.
ABSOLUTE MAXIMUM RATINGS (above which
the useful life. may be impaired)
-65"C to 150°C
Storage Temperature
Temperature (Ambient) Under Bias
(ITT9000-1)
-55°C to + 125°C
Temperature (Ambient) Under Bias
ITT9000-5)
O°C to + 75°C
Vee Pin Potential to Ground
(See Note 1)
-0.5V to + B.OV
Input Voltage (D.C.)
(See Note 2)
-0.5V to + 5.5V
Input Current (See Note 2) -30mA to + 5.0 mA
Output Voltage, Output
Normally High
0 V to + Vee value
Current Into Output Terminal,
Output Low(except9009)
50mA
Current Into Output Terminal,
Output Low 9009
100mA
NOTE 1
The maximum vee value of 8.0 volts is not the primary factor
in determining the maximum vee which may be applied to a
number of interconnected devices. The voltage at a high
output is approximately 2 VBE's below the vee voltage, so
the primary limit on the vee is that the voltage at any input
may not go above 5.5 V unless the current is limited, so this
effectively limits the system vee to approximately 7.0 volts.
3-286
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
NOTE 2
Because of the input clamp diodes, excess current can be
drawn out of the inputs if the D.C. input voltage Is more
negative than -0.5 V. The diode is designed to clamp off
large negative A.C. swings associated with fast fall times
and long lines. This maximum rating is intended only to limit
the steady state input voltage and current.
LOADING RULES
In this data sheet the following notation has
been chosen to indicate the input loading and
output drive for all logic elements.
INPUTS
OUTPUTS
X/V
A/B
2.
Tie the input to Vcc through a resistor.
This resistor should be chosen to keep the
input current within absolute maximum ratings for any possible extrenr ' of the Vcc
supply. More than one input may be terminated through one resistor.
3. Tie inputs to a separate supply between 4.5
and 2.4 V, if one should be available.
4. 'Tie he inputs to the output of an unused
gate. The unused gate must provide a
constant high level output.
LOG Ie ELEMENT
Where A= high logic level input load factor
B = low logic level input load factor
X= high logic level output drive factor
Y = low logic level output drive factor
When checking for loading violations it is only
necessary to insure that the sum of the high
logic level input load factors at any node does
not exceed the high logic level output drive
factor at that node. The same is true for the low
level load and drive factors. These rules apply
only within the TTL ITT9000 series.
NAND GATES-9002, 9003, 9004 AND 9007
HEX INVERTER-9016
The 9002, 9003, 9004 and 9007 are active low
level output AND gates commonly known as
NAND gates. The 9016 is a hex inverter with
input and output characteristics identical to the
9002, 9003, 9004 and 9007. The variety of gate
combinations provides the system designer the
utmost in logic flexibility and reduces package
count.
Figure 1 -
LOGIC SYMBOL AND PIN
CONFIGURATIONS
9002
9016
Multiplying the factor with the appropriate
current per unit load gives the input loading or
output drive in terms of current. For the TTL
circuits of this data sheet, current per unit is
-1.6 mA maximum at the low logic level and is
60uA maximum at the high logic level.
9
10
"
In the case where unused inputs of an AND
gate are shorted to a driven input, the high
logic level input load factor for the inputs will
be the number of inputs shorted together times
the high logic input load factor for one input.
The low logic level input load factor for the
inputs will be the same as that for a single
input.
10
12
13
"
9004
9003
1
2
13
3
4
5
UNUSED INPUTS
Proper termination of unused inputs will result
in maximum operating speed. Substantial
degradation of turn-on delay may occur if
unused inputs are left open.
12
9
10
11
10
12
13
9007
The following are acceptable ways to terminate
unused inputs:
1. Tie the input to a used input on the same
gate. The TTL 9000 series has made special
provision for this method by offering extra
high level drive factor on all inputs.
12
13
4
10
11
VCC=PIN 14, GND=PIN 7
3-287
12
13
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
Figure 3 -
Figure 2-BASiC GATE CIRCUiT
",
INPUT ....
Nominal Resistor Values
R.=Rs=4.0kO
Rz'= 1.5 kG
Rl= 1500
R.=800
R6= 1.25kO
",
1/1~
1/1--1/1--1/1---
"""""""1r----J rt.
: : 01
---1-----':
L......Nv-+--<>
**
___ 1-___ .. __ J
'
I
I
--t.-
'.~.'
LOADING FACTORS
OUTPUT
20/1010r-5
20/11 lor-1
~---I:::Q5
",
-Number of inputs depends on the gate.
ELECTRICAL CHARACTERISTICS 9002, 9003, 9004, 9007 AND 9016 (TA = -55°C 10 125°C, Vee = 5.0 V ± 10%)
VOH
Output High Voltage
-55°C
MIN. MAX. MIN.
2.4
2.4
VOL
Output Low Voltage
0.4
V.H
Input High Voltage
VIL
Input Low Voltage
I,
Input Load Current
SYMBOL CHARACTERISTIC
"
I,D
tpd+
I,d.-
LIMITS
25°C
TYP.
2.7
0.21
-
125°C UNITS
MAX. MIN. MAX.
2.4
Volts
0.4
1.7
2.0
1.4
0.8
Volts
0.9
0.8
-1.6
-1.24
-1.6
-1.24
-1.6
-1.24
-1.1
-0.87
10
60
60
5.5
3.5
5.5
5.5
1.6
1.07
1.6
1.6
,Input LeaKage current
Ve!E Current, Irate On
each gate
Vee Current, Gate Off
(each gate)
Switching Speed
Switching Speed
0.4' Volts
'10
12
3.0
3.0
Volts
rnA
/LA
CONDITIONS
Vee= 4.5 V 10H= -1.32 rnA
Inputs at VIL i~ee below)
Vee-5.5 V IOl-17.6 rnA
V'H=5.5 V
Vee=4.5 V h=13.6 rnA
Inputs at V,H (see belowi·
Guaranteed input high
threshold lor all inputs
Guaranteed inpul low
threshold lor all inouts
Vee=5.5 V I V,=0.4 V
Vee =4.5 V 5.5 V on other
inputs
Vee-5.5 V V.-4.5 V
GND on other Inputs
Inputs high
rnA
Vee=5.0 V
ns
ns
Vee=5.0 V, See Ipd lest circuit
C,=15 pF
ELECTRICAL CHARACTERISTICS 9002, 9003, 9004, 9007 AND 9016 (TA = OoC to 75°C, Vee = 5.0 V
SYMBOL CHARACTERISTIC
LIMITS
25°C
DoC
Output High Voltage
MIN. MAX. MIN.
2.4
2.4
VOL
Output Low Voltage
0.45
V,H
Input High Voltage
VOH
1.9
0.45
1.6
-1.0
-0.91
1.6
-1.41
1.6
,..1.41
10
60
,60
6.1
3.6
6.1
6.1
1.7
1.07
1.7
1.7
Input Low Voltage
0.85
1.6
-1.41
I.
Input Leakage Current
1,0
Vee Current, Gate On
(each gate)
Vee Current, Gate Off
(each gate)
SWllchlng speed
Switching Speed
3.0
3.0
13
15
3-288
.._.
Volts
Volts
0.85
Input Load Current
tpd+
0.45
0.85
I,
1",_
2.9
0.21
75°C
UNITS
MAX. MIN; MAX.
Volts
2.4
1.8
V,l
----
TYP.
Volts
rnA
/LA
rnA
ns
ns
Inputs at gnd
± 5%)
CONDITIONS
Vee = 4.75V 10H= -1.2 rnA
Inputs at VIL (see below)
Vee-5.25 V IOl-.16.0 rnA
V'H=5.25 V
Vee = 4.75 V h=14.1 rnA
Inputs at V,H (see below)
Guaranteed Input high
threshold for all Inputs
Guaranteed Input l o w ' - threshold lor all inputs
Vee 5.25 V V,-0.45 V
Vee =4.75 VI 5.25 V on other
inputs
Vee-5.25 V V.-4.5 V
GND on other inpuls
Inputs high
Inputs at gnd
Vee=5.0 V
Vee -= 5.0 V, See Ipd test circuit
C,=15 pF
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
TYPICAL INPUT AND OUTPUT CHARACTERISTICS 9002, 9003, 9004, 9007 and 9016
OUTPUT VOLTAGE VERSUS
INPUT VOLTAGE
4.0
f:: ~
r- -
20
~
~"'"
..,
i
f- 1- 125'C
15'C
e
rr
-2.0
~25'C
..
...z,
e
O'C
-55'C
"'
~
.7 55 'C
.O'C
B
~n:g
~
125'C
~
,
J
o
1.0
2.0
V1N-INPUT VOLTAGE -VOLTS
3.0
·4.0
...
-6.0
o
~
0
O'C
-5~
~
-40
~
-55'C
25'C
O'C
-60
-1.0
B.O
W
125'C_
...=>
2.0
4.0
6.0
V,N -INPUT VOLTAGE - VOLTS
~25'C
1 5 ' C - r--
/
,
-10
-2.0
~
125'C
-20
~-60
-8.0
L
I
VCc'5.0 V
INPUTS AT GNO.
IJII
./J;~
VCe' 5.0V
Vcc'5.0V
F.q. -11
~
o
. OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (OUTPUt HIGH)
INPUT CURRENT VERSUS
INPUT VOLTAGE
2.'0
I
1.0
3.0
5.0
VOUT-OUTPUT VOLTAGE -VOLTS
1.0
OUTPUT CURRENT VERSUS
OUTp·iJf VOLTAGE (OUTPUT 'LOW)
100
.,
VCC '5.0V
INPUTS HIGH
e
80
;
60
G
...=>
...=>
,
...=>
~
,
/
F
40
20
/
75'C
V
I.
0
.2
,~
I
I
00
25'C
--
POWER DISSIPATION, LOGIC LEVELS AND NOISE IMMUNITY
- -
WORST CASE LOGIC LEVELS
VERSUS AMBIENT TEMPERATURE
O'C
3.0
-55'C
........
~ii~H"ATI''i'cc'i5':ii'F =TrH;V~ I--
2.5
-
2.0
1.5
0.5
1.0
1.5
VOUT -OUTPUT VOLTAGE -VOLTS
_
f--VOH AT VCc'4.5V _
J
2.0
1.0
POWER DISSIPATION VERSUS
SUPPLY VOLTAGE
IOH'l.2mA
~
-
I
--
V1L
,...... ---:
VOL I
0.5
o C-~t'J
-55
r--
- I--
-
"e,
a
25
~ 20
~
"
~
f--t---+-t--+---+-=J;;--i"""'-!
151-=:::,.p4''--t--t--+-t--t--i
10
t:~IT.;!~~~~==-r-TI
-
j.5V'IVCC'15.5V
25
TA -AMBIENT TEMPERATURE -'C
125
vce-SUPPLY VOLTAGE·VOLTS
WORST CASE LOW LEVEL
NOISE IMMUNITY VERSUS
AMBIENT TEMPERATURE
WORST CASE HIGH LEVEL
NOISE IMMUNITY VERSUS
AMBIENT TEMPERATURE
2.4
2.0
1.6
1.2
I
I
I
I
i
~
-- -
1~F.O.~2.2
.11j.~\jL
....-
--l--~
I v; 5.0 'lj..- 1--.
1.2
f-"
.-+--r •.15' - f-r
0.8
,
1-',
~
0.4
-+- .-
~
~
I-
,-
-55
~
1.0
~ 0.8
"~
-
t;:! 0.6
~. 0.4
3
I
fL,
----I
f.O.' 5
f--
--
F.O.,1l
oz
I
o
4.5V ~ Vee!: 5.5V
I
'"
-
--
t:---
r-
O. 2
o
25
TA -AMBIENT TEMPERATURE -'C
3-289
125
-55
. 25
TEMPERATURE ('Cl
125
Series ITT9000·1, ITT9000·5
HIGH SPEED TIL
Vee
Ipd TEST CIRCUIT
SWITCHING WAVEFORM
2.0 kll
PULSE
INPUT
·Includes all probe and jig capacilance
36
SWITCHING
CHARACTERISTICS
WORST CASE TURN ON DElAY
VERSUS
AMBIENT TEMPERATURE °
~
~
VCC·5.0V..:..
l~
30
24
~
f"" 1.0 MHz
,
Amp"" 4.0 V
Widlh -"" 200 ns
If
1,:::;;10 ns
18
=
,
5
0
"" ~
I'--.
...........
"'4-1"47
~
12
JI.
520
r--
~,~t;
i!l
...
'i
10
I I
"See tpd test circuit
-55
-'
f--
~
5.0
I
25
TA-AMBIENT TEMPERATURE-'C
NAND BUFFER - 9009
The 9009 is a power gate capable of sinking and
sourcing large currents for high fanout
applications. Logically it is the same as the
9004.
125
Figure 4
o
,
~;"i
~ 15
z·
§
C('ls
~
V
MIN. AT C '15.F
o
Figure 6
-
I I I
6.0
r- VCC' 5.0V
~ 25
N4.f'_1
l~'
i!l
z
o
30
WORST CASE TURN OFF DElAY
VERSUS
AMBIENT TEMPERATURE o
-55
--
V
~~~ ~+- r-I
MiN. AT 15pF
=t-t-
25 I
TA -AMBIENT TEMPERATURE-'C
LOADING FACTORS
2/2 - - - . . - - -......
}-:
~~~
2/2
_
60/30 for - 5 .
66/33 for - 1
CIRCUIT DIAGRAM (One Gate)
vcc
Figure 5
LOGIC DIAGRAM
AND PIN CONFIGURATION
Nominal Resislor Values
R, = 2.0 kll R4 = 50 Il
R, = 560 Il Rs=4.0 kll
liJ = 150 Il R. = 500 Il
R,
R2
R3
R4
1--+-...,
2--+-L:1
4--+-r-::::l
INPUT
°4
R5
OUTPUT
9--+-...,
10--+--.
°5
6
5--+--'
12--+-r:l
13--+--'
8
RS
Vee = PIN 14
3-290
GND = PIN 7
125
Series ITT9000-1, ITT9OO0-5
HIGH SPEED TTL
ELECTRICAL CHARACTERISTICS 9009
-
.-
LIMITS
SYMBOL
CHARACTERISTIC
VOH
Output High Voltage
VOL
Output Low Voltage
V,H
Input High Voltage
V,L
Input Low Voltage
IF
Input Load Current
I,
-55°C
MIN.
MAX.
2A
MIN~
2A
0.4
2.0
25°C
TYP.
t,,,,
to"~
2A
2.7
0.21
Volts
Valls
0.9
0.8
Volts
3.2
3.2
-2.48
1.7
1.4
Valls
3.2
-2.48
2.15
-1.74
20
120
120
12.9
8.6
12.9
12.9
3.2
3.2
Vee Current, Gate On
(each gate)
Vee Current, Gate Off
(each gate)
Switching Speed
Switching Speed
3.2
-2A8
2.15
UNITS
OA
0.4
0.8
Input Leakage Current.
-Ipo
125°C
MAX. MIN.
MAX.
4.0
13.0
15
10
rnA
fJ.A
CONDITIONS
Vee =4.5 V 10H = - 3.96 rnA
Inpuls at V" (see below)
Vee = 5.5 VIoL - 52.8 rnA
V'H=5.5 V
Vee -4.5V IOL-40.8rnA
Inpuls at V,H (see below)
Guaranteed input high
threshold for all inputs
Guaranteed input low
threshold for all inputs
Vee- 5.5 V I VF-O.4 V
5.5 V on other
Vee=4.5 V
inputs
Vee -5.5 V
V,-4.5V
GND on other inputs
Inputs high
rnA
Vee=5.0 V
ns
ns
Vee - 5.0 V, See tpd test circuit
CL =15 pF
Inputs grounded
---_... -
DOC
SYMBOL CHARACTERISTIC
MIN.
MAX. MIN.
2.4
2.4
LIMITS
VOl-i
Output High Voltage
VOl
Oulput Low Voltage
V,H
Input High Voltage
V,L
Input Low Voltage
IF
Input Load Current
I,
Input Leakage Curren!'
I,D
Vee Current. Gate On
14.6
(each gate)
____
-----;;;----;Vee Current, Gate 6i1
3.4
2.15
(each gate)
Switching Speed
3.0
Switching Speed
2.0
2.4
2.9
0.45
Volts
0.45
0.85
0.85 '
-2.0
-1.82
-3.2
-2.82
20
120
;
Volts
Volts
1.6
1.8
-3.2
-2.82
0.85
Volts
-3.2
2.82
rnA
120
/J-A
~:_6_~-_~4.6 _ rnA
3.4 ,
3A i
tpd I
~=
SWITCHING CHARACTERISTICS
17
13
I ns
ns
tpd TEST CIRCUIT
2.0 kn
VOUT
f"" 1.0 MHz
Amp"" 4.0V
Width:::::: 200 ns
t f = tr~lO ns
INCLUDES ALL PROBE ANO JIG CAPACITANCE
3 - 291
Vee=4.75 V 10H= -3.6 rnA
Inputs at V,L (see below)
Vee=5.25 V lot =48.0 rnA
V'H=5.25 V
Vee=4.75 V IOL=42.3 rnA
Inputs at V,H (see below)
Guaranteed input high
threshold for all inputs
Guaranteed input low
threshold for all inputs
Vee-5.25 VI VF-0.45 V
Vee = 4.7.5 V 15.25 V on
other Inputs
Vee-S.25 V V,-4.5 V
GND on other inputs
Inputs high
Inputs at gnd
Vee=S.O V
Vee - 5.0 V, See tpd test
circuit CL=15 pF
SWITCHING WAVEFORM
vee
-=- *
CONDITIONS
MAX. MIN.
0.21
0.45
1.9
75°C
UNITS
MAX.
25°C
TYP.
Series ITT9000-1, ITT9000-5
HIGH SPEED TIL
TYPICAL INPUT AND OUTPUT CHARACTERISTICS 9009
INPUT CURRENT VERSUS
INPUT VOLTAGE
OUTPUT VOLTAGE VERSUS
INPUT VOLTAGE
4.0
2.0
;;;; ;:::..
ti=
Vcc' S'ov
F.O.·33
..
~
~
B:
2S'C~
.I
~ -2.0
20
I
I
L
~~'C
-SS'C
3.0
~
i'l
-4.0
-40
-6.0
~
?
-8.0
o
- -BO
o
2.0
4.0
6.0
V,N-,NPUT VOLTAGE-VOLTS
12S'C
~
-100
-1.0
8.0
"
f
'f'
I(ffIt
I. '(I'
.,/
25'C_ 75'C
125'C- -
,-
-60
5
-10
-2.0
-5g:g:::
~ -20
;!;
1.0
2.0
V,N -INPUT VOLTAGE -VOLTS
I
E
0-
~T
I
VCC'5.0V
INPUTS AT GNO.
.,
M
~
z
---
1.0
t--
'"~
-sS'C
O'C
... 25'C
7S'C
12S'C
,
r-
e
11
I
I-YCc'S,OV
12S'c,
o
7S'C
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
O'C
25'C
-55'C
0
1.0 2.0 3.0 4.0 5.0 6.0
VOUT -OUTPUT VOLTAGE -VOLTS
7.0
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
200
POWER DISSIPATION, LOGIC LEVELS AND NOISE IMMUNITY
WORST CASE LOGIC LEVELS
VERSUS
AMBIENT TEMPERATURE
POWER DISSIPATION VERSUS
SUPPLY VOLTAGE
100
I
I
I
j '\A~~'
-5S·C:S: TA! 12S·C
80
"~
E 60 I-- I-z
0
~
is
'"~
40
I 1 .J.
G~
I--~
~
~o
G~~
I
---
I--
I
3.0
I-- 2.5
GAT y OF
o
4.5
---
r-- ~ 2.0
~
~
'o3
>
1.5
1.6
1.2
0.8
0.4
o
---
-55
I-
--
C-
Jcc,~I~~
~~
~cc'~'~ I----
1--1: ,•.1~~
~cc :\
~cc"'~~
IOH'-3.96mA
§,
--- --
~ I--
-
-55
F.Of3 4.5v " c r
1
j
40
,
I
T-
r-
-55'C
17
1/
II'
o
0.5
1.0
1.5
VOUT -OUTPUT VOLTAGE - VOLTS
2.0
5.5r- -
25
TA-AMBIENT TEMPERATURE-'C
125
9009-1
WORST CASE TURN OFF DELAY
VERSUS
AMBIENT TEMPERATURE~
1.2
4.5V~
'"~
1.0
~
0,8
'"'"
~
0.6
~>-
VCC S5.5V
~
:::::P"~
r--
r-- _~.o.,~~
_r-
r--
cr--
fO.'
..p-
~
o
VCC ' 5.0V_t-+-t--l-t--+-l
T I
g 0.2
125
80
A
fI
1
25 c _
VOL
~ 0.4
~
~
I
o
-:-
r- -
~
f--~
25
TA - AMBIENT TEMPERATURE -'c
=>
-
~f-
~ 120
0-
b
160
ffi
WORST CASE LOW LEVEL
NOISE IMMUNITY VERSUS
AMBIENT TEMPERATURE
I----
~cc;.;:::-
,
VIL
WORST CASE HIGH LEVEL
NOISE IMMUNITY VERSUS
AMBIENT TEMPERATURE
2.0
1
tOH'I-3.9imA
~ I--
1.0
o
5.0
5.5
VCC-COLLECTOR SUPPLY VOLTAGE - VOLTS
l ' HIGH LEVEL FAN OUT' 66
VOH AT VCC'4.5V
0.5
I-TYi""
2.4
vr r
I--
AT~ orLMlx.
20
VOH(
5
125)?f- 75'C
VCC'5.0V
INPUTS .HIGH
-55
--
25
TA-AMBIENT TEMPERATURE-'C
125
~5~5~-L-I~~2L5~-L-~-L~125
TA -AMBIENT TEMPERATURE -'C
'SEE TEST CIRCUIT
3-292
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
9009-1
9009-5
WORST CASE TURN ON DELAY
VERSUS AMBIENT TEMPERATURE
i-+:h,1
:/..~iC\.'~ P
36
VCC ·5.0V
501--.--+--+-+-1-+-+--+--1
~
0
30
z
z
I
,.
"-"
.........
"'
1
........
g
24
!;
z
"'
...
18
"!
20
.........
30
I
,
o
I
"'A~. Ai C\" \5~ f-
-
125
I
o
I-
-
75
1.5/1.5
1.511.5
10
t><:
8
11
12
:~:~~6
-.-i-
III
I VCC ·5.0V rI
MAX. AT CL'I50pF
lB
.......
MAX. AT CL'15pF
'
12
I
6.0
o
MI~.
o
I
I
AT CL'15pF
25
50
75
9006
9008
~
5
NON·EXTENDABLE GATE
1.511.5
1.511.5
22/11 10.·1
20/10 lot· 5
Vee
Gnd
13
1.511.5
22/11 for· 1
20/10 .... 5
• EMIT.
• COll.
EXTENDABLE GATE
111
LL
LOGIC DIAGRAMS AND LOADING FACTORS
The numbers by each input and output give the
input loading and output drive capability. For
complete expanation see Page 2 and 3.
9005
13
I
I
I
TA-AMBIENT TEMPERATURE-'C
9005,9008, EXTENDER -
The TTL 9005 and 9008 are ANO-OR-INVERT
gates which may be OR extended with the use
of the 9006. For noise immunity and operating
level curves, refer to the gate section.
1.5/1.5
r-
I I
25
50
TA-AMBIENT TEMPERATURE-'C
24
I
I
I
~
~
z
~
~
EXTENDABLE AND-OR-INVERT GATES -
1.5/1.5
:3
'i'
MIN. ATCL'15pF
r-
c
12
6.0
F:J:=t=t~~M~I~t·~ATt~C~L'~I~~PF~t--~
25
TrAMBIENT TEMPERATURE-'C
f::::
II
I I
I .I
-
,£
~
15_PF-+--1
10 1-+--+-:-----f'=-t_M_AXt-.A_T"1"'C:,.L'-t
~~
l-
36
If
:.- ~
30
,
40
WORST CASE TURN ON DELAY
VERSUS AMBIENT TEMPERATURE"
WORST CASE TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE'
1.511.5
22/11 10'· I
)0--"--- 20/10 ... ·5
1.511.5
1.511.5
",---,-,11_ EMIT.
",-_1",2_. COlL.
*
1.5/1.5
1.5/1.5
1.5/1.5
= Pin 14
= Pin 7
Vee
Gnd
'Four Extenders (9006) may be
tied to these terminals
= Pin 14
= Pin 7
'Four Extenders (9006) may be
tied to these terminals
9006
13
~1.
~
12
COlL.
1.511.5
1.5/1.5
2
1.511.5
3
1.511.5 - - " " " - - -
11
EMIT.
4
1.511.5~
1.5/1.5
1.511.5
1.511.5
6
8
9
COll
10
EMIT.
.
Vee = Pin 14
Gnd = Pin 7
3- 293
Series ITT9000-1, 1119000-5
HIGH SPEED TTL
CIRCUIT DIAGRAMS
9005
.13 o---+-~...J
9006
'--"""'~+--O8
90--,-~"(
Vee
R = 2.6 k!l Typical
~--------~
10 0---+---.--'
EXTENDABLE GATE
Two in a package
Vee = Pin 14
Gnd = Pin 7
40---.---'
5 O:--+---.-...J
NON· EXTENDABLE GATE
Vee = Pin 14
Gnd = Pin 7
Typical Resistor Values
RI =
R2 =
R. =
Rs =
R3 = 2.6 kO
800 0
R" = 150 0
RI2 =.800
R.= R. = R,o = R" = 4.0 kO
R7=665!l
R, = 1.5 k!l
R,. =:' 1.25 k!l
9008
Typical Resistor Values
2
3
RI = R2 = R. = Rs = 2.6 k!l
R3 = 800 0
R6 = 150 0
R7=80!l
R.=4.0 k!l
R, = 6650
9
10
4~~--'
50-+--.--'
Vee = Pin 14
Gnd = Pin 7
6o-t-l--.p...J
3-294·
Series ITT9000-1, ITT9000-5
HIGH SPEED TIL
ELECTRICAL CHARACTERISTICS 9005, 9006 AND 9008 (TA = - 55°C to 125°C, Vee = 5.0 V
±- 10% I
--
LIMITS
SYMBOL CHARACTERISTIC
VOH
Output High Voltage
-VOL
Output Low Voltage
VIH
t
mpUt Mlgn vOltage
Input Low Voltage
VIC
-55°C
25°C
125°C
"'IN. MAX:'-. l'!'!!N. TYP. M~!,- M.!N. MAX.
2.4
2.4
2.7
UNITS CONDITIONS & COMMENTS
10H= -1.32 rnA
Vee =4.5 V
VIL=value Indicated below
on this table
---- 0.2 0.4
0.4
0.4 Volts Vee-S.S ,';-IoL=17.S mA--V'H=S.SV
Vee-4.5 V IOL-13.SmA
V'H= (see below)
Ir.~---- :--1.4
tpd _
3.0
3.0
12
14
ns
Vee-S.O V, CL-1S pF
9005 Nonexlendable gale only,
tpd+
3.0
3.0
15
12
ns
Vee=5.0 V, CL=15 pF, CN =5.0 pF
9005 Exlendable gale and 900B,
-.2.0
-2.0
4.0
4.0
ns
9006 only
The 9006 is lesled by measuring lis
propagalion time Ihrough Ihe 9005.
CONDITIONS & COMMENTS
See Fig. 7
I,d_
See Fig. 8
dip",
dl,d.
The I,d readings shall nol exceed
Ihe 9005 readings by Ihe specified
amount. See Fig. 9.
Symbols are deiined in Ihe lesl circuit.
9005, 9006, 9008
TYPICAL INPUT-OUTPUT CHARACTERISTICS
(EXTENDABLE GATES")
2.0
Vee-S.O v
F.o.-n
~~
\~
,
r- r-
;-2.0
r-- r--
B-4.0
-
':~~'
75-C af..!o·c
0
T
Vee s 5.0 V
I-
;I
5S·C
O'C
25-C
75-C
125·C
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)
INPUT CURRENT VERSUS
INPUT VOLTAGE
OUTPUT VOLTAGE VERSUS
INPUT VOLTAGE
~
O'c
-5S-C
-5S-C
0
~
7-6.0
o
25.c~_1f
-8.0
-Ft
0'-
0
1.0
2.0
VIN-INPUT VOLTAGE-VOLTS
'0
-10
-2.0
,-/I
,/
f{fff: "'c -
-
'~l;.g - -
o ~~:~::))
z
0
I
vcc cs.ov
INPUTS AT GND.I
0
o
2.0
4.0
6.0
VIN -INPUT VOLTAGE -VOLTS
3- 297
ao
-8
-1.0
~,.c
1.0
'.0
Your - OUTPUT VOLTAGE-VOLTS
7D
•
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
9005-1. 9006-1 AND 9008-1
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
.00
k
Vcc' S'ov
IN~UTS
'WORST CASE TURN OFF DELAY
OF NON EXTENDABLE GATE
.. VERSUS AMBIENT TEMPERATURE .
OPEN
160
WORST CASE TURN ON DELAY
OF NONEXTENDABLE GATE
..VERSUS AMBIENT TEMPERATURE
Yee' S,OY
SEE FlU
-40
TS'C
:
2~
~ 32
Vcc' 5.0V
SEE FIG. 7
\
I
I
120
;
~
80
L
~
I
°0
0.4
0.8
1.6
1.2
I
I
I
I---'
~.~1~
~
,,~~. ~1 c,:\~ P'"
-55'C
.0
f - ....
111
O'C
~
1II•• ~1
o
2.0
-S5
Your - ounUT VOLTAGE - VOLTS
Ct·'s"
TA- AMBIENT TEMPERA1\IfE
2.
~I
16
I-
- ~ ~Tc;,.~o" I-
~ i ' _.
J.. r' -
.:::
.1. AT c;",,,,
~AlAx.
"N. AT cL,rSpF
o
-55
125
25
!
-Ie
--
25
lA-AMBIENT TEIlPEATURE-'C
WORST CASE TURN ON DELAY
OF EXTENDABLE GATE VERSUS
.s
AMBIENT TEMPERATURE
~ ~.
. 1 .... L...l
--r
Vee' 5.OV
_\.
'.
r·
SEE FIG.•
'0 h~--+-t--t-i-H
I
..
~ 32
,I
I
r
'l\r ; .. -1--+_.+_+_
I
I!It-t~·+; ~ .. L
r-
"., AT CL I
• 24
I
J5~"
I. I.
SC
h-+-+-++-+
~M~-+-t~~+-~~
·tt '_ ..
r--i"".2.
. "'J
X-ATCL'I5,,!-'
1-
40
~ 321--+-+--+-+--:1.
~.,.
j
~~~-+~-+-+-t-4
1
F=:tl:~~~~"CTCl~I~5"±=~~--~
~5's
25
125
rA- AMBIENT
TA- AMarNT TEMPERATIJIE - "e
J·K FLlP·FLOPS -
9000, 9001, DUAL J·K FLIP·FLOPS -
The TTL 9000 series has four flip-flops to
satisfy the storage requirements of a logic
system. All are master-slave JK designs and
have the same high speed and high noise
immunity as the rest of the 9000 series. As with
the gates, all inputs have diode clamps to
further engance the noise immunity.
TEMPERATURE -'e
9020, 9022
D;;lta is accepted by the master while the clock
is in the low state. Refer to the truth table for
definition of "ONE" and "ZERO" data. Transfer
from the master to the slave occurs on the low
to high transition of the clock. When the clock
is high, the J and K inputs are inhibited.
The JK type flip-flop was chosen for all flip-flop
elements in this family because of its inherent
logic power. The input function required to
produce a given sequency of states for a JK
flip-flop will, in general, contain more "don't
care" conditions than the corresponding
function for an RDdlip-dlop. These additional
"don'.t care" conditons will, in most cases,
reduce the amount of gating elements required
to implement the input function.
A jOint (JK) input is provided for all flip-flops in
this family. This common input removes the
'necessity of gating the clock signal with an
external gate in many applicaitons. This not
only reduces package count, but also reduces
the possibility of clock skew problems, since
with internal gating provided, all flip-flops may
be driven from a common clock line. Several
TTL drivers may be used in parallel to drive this
common clock line, if the load exceeds the
F.O. capability of the 9009 buffer.
The master-slave design offers the advantage
of a DC threshold on the clock input initiating
the transition of the outputs, so that careful
control cif clock pulse rise and fall times is not
required.
The asynchronous Inputs provide ability to
control. the state of the flip-flop independent of
static conditions of the clock and synchronous
inputs. Both asynchronous set and clear are
provided on all flip-flops except the 9020,
3-298
Series 1119000-1, 1119000-5
HIGH SPEED TTL
which because of a logic trade-off has only
clear inputs. The set or clear pin being low
absolutely guarantees that one input will be
high, but if opposing data is present at the
synchronous inputs and the flip-flop if clocked,
the low output may momentarily spike high
synchronous with a positive transition of the
clock. If the low output of the flip-flop is
connected to other flip-flop inputs clocked
from the same line, the spike will be masked by
the clock. If the clock is suspended during the
time when the asynchronous inputs are
activated, no spike will occur..When the spikes
can cause problems, a simple solution is to
common the joint JK inputs with the
synchronous set or reset signal.
I
LOGIC DIAGRAMS AND LOADING FACTORS
9000
'1,
,"
'1,
41,
6
'2
'1,
212
'1,
'1,
'1,
'1,
'1,
20/10
I
9020
'4
20'10
20'10
20/ 10
20/10
2'2
8 20/10
"I,
'0
"
"
9022
9001
4/4
'1,
'1,
'1,
'1,
2/2
'1,
'1,
'1,
6
'2
lJ,
20/10
, '0
20/ 10
212
3
20/10
'1'
'0
"
Vee = 14
GND~7
Vee'16
GND' 8
FUNCTIONAL LOGIC DIAGRAMS
9020/9022
9000/9001
So 9022 ONLY
Y
JK~--~======~'~------------~~~~~~
SLAVE
SYNCHRONOUS OPERATION
TRUTH TABLES
BEFORE CLOCK
OUTPUTS
INPUTS
ASYNCHRONOUS OPERATION
OUTPUTS
AFTER
CLOCK
ONE
ZERO
J
K
ONE
ZERO
L
L
H
H
H
H
L
L
L'
H'
X
X
X
X
L'
H'
L
H
H
L
H
L
L
H
3--: 299
INPUTS
OUTPUTS
So
CD
L
L
H
L
H
L
H
H
ONE
,
l'
ZERO
H
H
H
L
L
H
Synchronous
Inputs Control
•
i
Series ITT9000-1, ITT9000-5
HIGH SPEED TIL
SYNCHRONOUS OPERATION
The H* symbol in the J and K input column is
defined as meaning that the input has been
high at some time while the clock was low.
The truth table defines the next state of the
flip-flop after a low-to-hlgh transition of the
clock pulse. The next state is a function of the
present state and the J and K inputs as shown
in the table.
The X symbol indicates that the condition of
that input has no effect on the next state of the
flip-flop.
The J and K inputs in the table refer to the basic
flip-flop J and K inputs as indicated on the
logic diagrams. These internal inputs are for
every flip-flop the result of a logic operation on
the external J and K inputs. This operation is
represented symbolically by AND gates in the
logic diagram for each flip-flop. Logic diagrams
are in accordance with MIL Standard 806B.
The Hand L symbols refer to steady state high
and low voltage levels, respectively.
UNUSED INPUTS
The 9001, 9020 and 9022 all have active level
low synchronous inputs. When not in use they
must be grounded. All other unused inputs
including asynchronous should be tied high for
maximum operating speed. Use one of the
methods recommended on Page 3.
The L* symbol in the J and K input column is
defined as meaning that that input does not go
high at any time while the clock is low.
.
ELECTRICAL CHARACTERISTICS 9000, 9001, 9020 AND 9022
(TA=-55 Ct0125 C,Vcc=5.0V
10%)
LIMITS
SYMBOL CHARACTERISTIC
-55°C
MIN.
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
V ,H
Input High Voltage
2.0
V"
Input Low Voltage
I,
Input Leakage
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
SD, CD (all flip-flops)
Input CUrrent
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T.inputs 9020,9022
JK inputs 9020, 9022
SD, CD (all flip-flops)
Input Current
All J, K inputs
T inputs 9000, 9001
. JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
SD, CD (all flip-flops)
Vee Current
9000
9001
9020,9022
each flip-flop
I,
I,
IpD
125°C
25°C
MAX. MIN.
2.4
0.4
TYP.
2.7
0.21
MAX. MIN.
UNITS
2.4
0.4
1.7
0.4
1.4
0.8
0.9
Volts
Volts
Volts
Vee=4.5 V,l oH = -1.2 rnA
Vee-4.5 V. h -12.4 rnA
Vee = 5.5 V, 10L = 16.0 rnA
Guaranteed input high
thres~old for all inputs
Guaranteed input low
threshold for all inputs
0.8
Volts.
p.A
V,=4.5V
Vee=5.5 V
Gnd. on other inputs.
rnA
Vee = 5.5 V
rnA
Vee=4.5 V
rnA
SD at gnd
SD at gnd
COl, CO2 at gnd
5.0
60
60
10
120
120
20
14
240
160
240
160
-1.60
-1.1
-1.60
-1.60
-3.~0
-2.2
-3.20
-3.20
-6.40
-4.32
-4.4
-2.97
-6.40
-4.32
-6.40
-4.32
-1.24
-0.87
-1.24
-1.24
-2.48
-1.74
-2.48
-2.48
-4.96
-3.35
-3.48
-2.35
-4.96
-3.75
-4.96
-3.35
24
28
27
13
14
14
24
28
27
24
28
27
3-300
CONDITIONS
& COMMENTS
MAX.
V,=0.4 V
5.5 V Gnd on
other inputs
Vee=5.0 V
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
ELECTRICAL CHARACTERISTICS 9000, 9001, 9020 AND 9022
(TA = DOC to 75"C, Vcc = 5.DV 5%)
LIMITS
O·C
SYMBOL CHARACTERISTIC
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
V,H
Input High Voltage
1.9
VII
Input Low Voltage
2S·C
TYP.
MAX. MIN.
MIN.
3.0
0.21
2.4
0.45
75°C
MAX. MIN.
2.4
0.45
0.45
1.8
1.6
& COMMENTS
Vee = 4.75 V, 10H= -1.2 rnA
Vee = 4.75 V, ioc-T4TrnA
Vee = 5.25 V, ioc=16 rnA
Guaranteed input high
threshold for all inputs
Guaranteed input low
threshold for all inputs
VCC-S.25 V, V.-4.5 V
Gnd. on other inputs.
Volts
Volts
Volts
0.85
0.85
60
60
10
120
120
20
14
240
160
240
160
-1.60
-1.0
-1.60
-1.60
0.85
CONDITIONS
UNITS
MAX.
Volts
p.A
I.
Input Leakage
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
So, Co (all flip-flops)
I,
Input Current
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
So, Co (all flip-flops)
-1,-- Input Current
All J, K inputs
T inputs 9000, 9001
J
J K inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
So, Co (all flip-flops)
Ipo
Vee Current
9000
9001
9020,9022
each flip-flop
5.0
-3.20
-2.0
-3.20
-3.20
-6.40
-4.32
-4.0
-2.7
-6.40
-4.32
-6.40
-4.32
-1.41
-0.94
,1.41
-1.41
-2.B2
-1.8B
-2.82
-2.B2
-5.64
-3.7B
-3.76
-2.54
-5.64
-3.7B
-5.64
-3.7B
28
33
30
2B
33
30
rnA
Vee -5.25 V
rnA
Vec-4.75 V
rnA
2B
33
30
V,-0.45 V
5.25 V on
other
inputs
Vee-S.O V
So at gnd
So at gnd
COl, CO2 at gnd
TYPICAL INPUT-OUTPUT CHARACTERISTICS 9000,9001,9020 AND 9022
OUTPUT VOLTAGE VERSUS
INPUT VOLTAGE
ASYNCHRONOUS INPUTS
CLOCK OUTPUT VOLTAGE
VERSUS INPUT VOLTAGE
4.0
4.0
g
2.0
Vcc' 5.0 V
VCC'5.oV
'"
S
INPUT CURRENT VERSUS
INPUT VOLTAGE 9004
.n
S
g
3.0
I
I
W
W
~
-55'C
)---O'C
25'C f-- ,.- f-75'C
125'C f- ' - f--
~
~ 2.0
~
o
~ 1.0
""E,
3.0
~ -2.0
~
i-"55'C
O'C
S
g
2.0
~
o
o
1.0
2.0
VIN -INPUT VOLTAGE -VOLTS
3.0
~ ---O'C
"WC
25'C
....=>
~75'C
125'C
ill.... 1.0
IT
lIT
71/(1
a~ -4.0
~25'C
....
0.
7-6.0
-~
~
~
Vcc' 5.0V
125'C
75:;"
0-
-6.0
1.0
2.0
VIN -INPUT VOLTAGE -VOLTS
3- 301
3.0
-1 0
-2.0
2.0
4.0
6.0
VIN -INPUT VOLTAGE - VOLTS
6.0
Series 11T9000-1, 1119000-5
HIGH SPEED TIL
INPUT CURRENT VERSUS
INPUT .vOLTAGE
JK INPUT 9000, 9001
INPUT CURRENT VERSUS
INPUT VOLTAGE 9009
.,
2.0
«
VCe'S.OV
oI-- 12S'C
7S'C
E
~ -2.0
~
~
r
2.0
!!I/l. I-O'C
""EI
L:'?S'C
2S'C
t-
~
~
I
'"
-B.O
-2.0
t-«
f
E
-2.0
~
7 -6.0
-10
L..!!! ~-ss'c
-6.0
B.C
-2.0
-'"
VCC'S.OV
t-i- 2S'C
t - I;;:~
~
E
~
-2.0
G '-4.0
.1
1, so
~55'C
O'C
~ 60
~
~
>=>
.5'
20
1
-10
-2.0
1
4.0
2.0
6.0
VIN -INPUT VOLTAGE - VOLTS
75°C
25'C
O'C
40
,
/
II
'L
o
-.l
o
2.0
4.0
6.0
V,N -INPUT VOLTAGE-VOLTS
I?l -
/
ffi
t-- -55°C
~I -6.0
t - V2~:~
z
t - ~~~:g
-2.0
v- S5 'C
II
1 1
V
>-
V
"I
-B.O I--
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
VCC' S.OV
INPUTS OPEN
>-
-B.O
B.O
100
11
lJI
1
I
12S'C
2S 'C
I- v
kO'C
-I 0
o
2.0
4.0
6.0
V,N -INPUT VOLTAGE - VOLTS
INPUT CURRENT VERSUS INPUT
VOLTAGE ASYNCHRONOUS
INPUTS - ALL FLIP-FLOPS
2.0
I
~5S'C
~ I" i'.2~:g
"I -6.0 I-- v!S'C
-B.O
10
o
2.0
4.0
6.0
VIN -INPUT VOLTAGE - VOLTS
~
r- ~~~:~
1
,J
IE
a -4.0
-sS'C
V.0'C
1/2S'C
I
VCC' 5.0V
7S'C
12S'C,
Itc
-2.0
a'" -4.0 t-r~
B -4.0
'"
r-
2. 0
12~'C'
VCe'S.OV
I
12S·C
U
1
INPUT CURRENT VERSUS
INPUT VOLTAGE
JK INPUT 9020, 9022
/
!/
B.O
-sS'C
A
0.5
1.0
1.5
VOUT - OUTPUT VOLTAGE - VOLTS
2.0
SWITCHING CHARACTERISTICS (T,=25°C, Vcc=5.0V, CL=C,=15 pF of all flip-flops unless otherwise noted)
CHARACTERISTICS
Clock-to-Output
So or Co-to-Otuput
Clock-to-Output
t,d
So or Co-to-Output
t1C t.up
J, K or JK
L9000 Only
Data Entry
J or K Data Entry
treleal
I I
28
~
V
MIN.lpd+ (T HIGHI
'4.0
/
0\0/
12
./
M~Pd_ (T LOW!
36
I I I
I
10
16
/'
I I I
44
~
-;;
./
~I
'Pd+CT LOW!
52
~o/
~,
I :
/
/"
I I I
I I I
12
9001·9020·9022
SET·UP/RELEASE TIME AND
NEGATIVE CLOCK PULSE WIDTH
VERSUS AMBIENT TEMPERATURE
VCCI ·5.y
~d_
20
25
'TA-AMBIENT TEIIPERATURE"C
22
~I
.
C THIGH
36
28
./
MIN,lpd-
4.0
-55
44
/
I-
20
V
IIA;!pd-
-
28
6,0
20
52
52
INCREASE IN ASYNCHRONOUS
OR CLOCK INPUT
DUE TO OUTPUT CAPACITANCE
I II
25
TA-AMBIENT TEMPERATURE"C
125
C1
>3.0 V
1.5 V
=i
Figure 12
VJK
<0.4 V
WAVEFORMS
"'-------II
>3.0 V ---'--t-~----""'"
1.5 V
<0.4 V _ _- J
>3.0 V
1.5 V
·'<0.4 V
----t--'
3-303
9020/9022
Flg.ll
Vee = 5.0 V
R= 2.0 kll
= CL = 15 pF
C,
including
probe and jig
capacitance
VCPH---+-4
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
SWITCHING TEST NOTES
will remain at a static logic level (no switching will occur).
tpd + and tpd1. VJ K should be kept at the high logic level
when performing tpd tests.
trelease
2. Drive the clock pulse input with a suitable
pulse source. tpd +and tpd - delays are as
defined in the waveforms.
1. trelease is defined as the maximum time
allowed for a HIGH to be present at a synchronous logic input at any time during the
low state of the clock and not be recognized.
~
2. The test for trelease is performed by adjusting the timing relationship between Vc P
and VJ K to the trelease maximum value. The
outputs of devices that pass will remain at
static logic levels. In order to check both J
and K sides of the flip-flop it is necessary to
perform the test with the flip-flop in each of
its two possible states, i.e., set and clear.
This can be accomplished by making use of
the appropriate direct inputs to establish the
state before a test. The outputs of devices
that do not pass the trelease test will exhibit
pulses instead of static levels.
1. tset-up is defined as the minimum time required for a HIGH to be present at a synchronous logic input atany time during the low
state of the clock in order for the flip-flop to
respond to the data.
2. The test for tset-u p is performed by adjusting the timing relationship between the Vcp
and VJK inputs to the tset-up minimum
value. A device that passes the test will have
theoutput waveform shown. The output of a
device that does not pass the tset-u p test
9000 SCHEMATIC DIAGRAM
9001 SCHEMATIC DIAGRAM
For resistor values,see page 16
For resistor values,see page 16
Vee
Rg
Vee = Pin 14
Gnd = Pin 7
Vee = Pin 14
Gnd = Pin"
-=-
3-304
RU
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
RECOMMENDED INPUT PULSE SOURCES
DTL9932 gates with adjustable capacitors
connected from extender inputs to ground
make suitable delay elements.
9020 SCHEMATIC DIAGRAM
16
vee
'''-+thp-015
11
4
Vee = Pin 16
Gnd=Pin 8
RI, R4,
Rs. Rs,
RIO,
RI., R I1, RII , R22, Rn, R24, Rl6 , RZ9=4.0 ko
R" R" R., R,=2.0 kn
Rqr R16, RUI R31 = 6.0 kO
NOMINAL COMPONENT VALUES [ALL FLIP-FLOPS]
RII, R,,=1.5kn
RIl , R,,=150n
RIl , R,,=80n
RIS,
R2z, RZ5 , Rz7 , RlO = 1.25 kn
R,,=1.0kll
C" C,=10 pF
Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
9022 SCHEMATIC DIAGRAM
VCC
Vcc=Pln 14
Gnd=Pin 7
APPLICATIONS
DIVIDE BY TEN COUNTER
SYNCHRONOUS BCD COUNTER
r+====+===::;===l=t----
IN....------.----h===:::::;-]
1/5
1/10
VCC
01
02
04
08
Two TTL 9020 Dual Flip-Flops require no additional gating
to produce a fully synchronous 8421 code BCD Counter.
Two TTL 9020 Dual Flip-FlOps require no additional
gating elements to produce divide by ten circuit with a
square 'wave divide by ten output and a divide by five.
output.
BINARY COUNTER WITH ASYNCHRONOUS PARALLEL LOAD AND CLEAR
PARALLEL INPUT ONES TRANSFER ENABLE ----...,-!-----.,.-\------'t4-----,
COUNT ENABLE
COUNT INPUT
--.---+-----1---+-.---+---.
-+'O'----+-f-J
MASTER CLEAR - - - -......---,f::--.2;~--'-+.Q2----.......~"'Q4--'~---.J
-
PARALLEL OUTPUT -
3-306
Binary counter using synchronous 2
bit stages with trickle down between
stages illustrates method of utilizing
dual JK flip-flops having common
clocks in counter applications.
ITT 9024
DUAL JK (OR D) FLIP-FLOP
-
ITT --------=""""""'"
SEMICONDUCTORS
Packages: 16 lead DIP and Flat Packages
LOGIC SYMBOL
DUAL JK [OR 0]
FLIP-FLOP
l---:I
11 - - - - " ,
• Dual Rank Type Circuit
14
• Separate Clocks
• Separate Asynchronous Set and Clear Inputs
12
13
• Low Power Dissipation
15
J So
Cp
Q
10
Q
9
K CD
• Compatible with ITT DTL and Other TTL
Families
• Input Diode Clamping
ABSOLUTE MAXIMUM RATINGS
• 25 M Hz Operation
Characteristics
The ITT9024 consists of two high-speed,
completely independent transition clocked JK
flip-flops. The clocking operation is independent of rise and fall times of the clock
waveform. The JK design allows operation as a
D flip-flop by simply connecting the J and K
pins together.
Units
Storage Temperature
................... -65 to + 150
C
Temperature (Ambient Under
C
Bias ............... -55to +125
Vee Pin Potential to Ground
Pin (See Note 1) ....... -0.5 to + 8 Volts
Voltage applied to output
when output is high .. O V to + Vee value
Input Voltage (DC)
(See Note 2) ........ -0.5 to + 5.5 Volts
Input Current (DC)
(See Note 2) ........... -30 to + 5 mA
Current into output when
output is low ................ + 30 mA
Notes 1 and 2 following page
LOGIC DIAGRAM
SDo-------.----______~
10--.--0 Q
cpo--------~---~
Jo---o'ij
.----.'---.1
CDo-~~--------------~
3-307
ITT 9024
DUAL JK (OR D) FLIP-FLOP
"ELECTRICAL CHARACTERISTICS (TA = _55°C to 125°C, Vee = 5 V
10%) (Note 3)
LIMITS
SYMBOL
CHARACTERISTIC
_55°C
MIN.
MAX.
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
IR
21R
4 IR
IF
-e IF
3 IF
IF
21F
3 IF
Ipo
J, K Leakage Current
Clock Input, So
CD
J, K Input Current
Clock Input, So
Co(Note 4)
J, K Input Current
Clock Input, So
CD (Note 4)
Current Drain
Ise
Output Current
MIN.
2.4
0.4
04
UNITS
25°C
TYP.
MAX.
2.7
0.2
0.25
0.4
0.4
Volts
Volts
Volts
Volts
0.8
Volts
1.4
0.8
0.9
5.0
10
20
-1.1
-2.2
-3.3
-0.91
-1.82
-2.73
9.0
-1.6
-3.2
-4.8
-1.24
-2.48
-3.72
0.4
0.4
2.4
1.7
CONDITIONS AND
COMMENTS
125·C
MIN. MAX.
60
120
240
-1.6
-3.2
-4.8
-1.24
-2.48
-3.72
60
120
240
-1.6
-3.2
-4.8
-1.24
-2.48
-3.72
14
/lA
Vee =5.25 V, VF = 0.4 V
4.5 V 011 other inputs
mA
Vee=5.5V
mA
Per Flip Flop in Worst
Logic State
mA
Logic 1 Output Short Circuli
5%) (Note 3)
LIMITS
SYMBOL
CHARACTERISTIC
VOH
VOL
Output High Voltage
Output Low Voltage
O°C
MIN. MAX.
2.4
0.45
VIH
Input High Voltage
1.9
VIL
Input Low Voltage
IR
21A
4 IR
J, K Leakage Current
Clock Input, So
CD
IF
2 IF
3 IF
J, K Input Current
Clock Input, So
CD (note 4)
IF
2 IF
3 IF
Ipo
J, K Input Current
Clock Input, So
CO(Note 4)
Current Drain
Ise
Output Current·
MIN.
2.4
1.8
25°C
TYPE
3.0
0.21
MAX.
0.45
0.85
0.85
Vee =5.5 V, VR =4.5 V
Gnd. on other Inputs
mA
-65
"ELECTRICAL CHARACTERISTICS (TA = O·C to 75°C, Vee = 5 V
Vee = 4.5 V, 10H = -1.2 mA
Vee - 4.5 V, 10 L -12.4 mA
Vee = 5.5 V, 10L = 16 mA
Guaranteed Input high
threshold for all inputs.
(To Sink 10L)
Guaranteed input low
threshold for all Inputs.
(For Vo H Output)
75°C
MIN. MAX.
2.4
0.45
UNITS
1.6
Volls
0.85
Volts
Volts
CONDITIONS AND
COMMENTS
Vee = 4.75 V, 10H = -1.2 mA
Vee = 4.75 V, IOH = 14.1 mA
Vee=5.25 V, 10H =16 mA
Guaranteed Input high
threshold for all inputs.
(To Sink 10 L)
Volts
Guaranteed input low
threshold tor all inputs.
(For Va H Output)
.uA
Vee = 5.25 V, VA = 4.5 V
Gnd. on other Inputs
5.0
10
20
60
120
240
-1.6
-3.2
-4.8
-1.0
-2.0
-3.0
-.16
-3.2
-4.8
-1.6
-3.2
-4.8
mA
Vee =5.25 V
-1.41
-2.82
-4.23
-0.94
-1.88
-2.82
9.0
-1.41
-2.82
-4.23
-1.41
-2.82
-4.23
mA
Vee = 4.75 V.
mA
Per Flip Flop in Worst
Logic State
LogiC ,1, Output Short Circuit
14
-65
(1) The maximum VCC value of 8.0 volls is not the primary
factor in det'3rmining the maximum VCC which may be
applied to a number of interconnected devices. The voltage at a high output is approximately 1 VBE below the
VCC voltage, so the primary limit on the VCC is that the
voltage at any input may not go above 5.5 V unless the
current is limited, so this effectively limits the system
VCC to approximately 7,0 volts.
(2) Because of the input clamp diodes, excess current can
be drawn out of the inputs if the D,C. input voltage is
mA
VF =0.4 V
4.5 V on other
inputs
negative than -0.5 V. The diode is designed to cramp off
large negative A.C. swings associated with fast fall times
and long lines. This maximum rating is intended only to
limit the steady state input voltage and current.
(3) POSitive current is into device and negative current is out
of device.
(4) Denotes maximum current under normal operation.
These currents may increase up to 4 IF if J, K=Logie 1
and SD = Logic O.
3-308
ITT 9024
DUAL JK (OR D) FLIP-FLOP
TRUTH TABLES
SYNCHRONOUS ENTRY
J-K MODE OPERATION
INPUTS AT to
J
K
L
L
H
H
H
L
H
L
ASYNCHRONOUS ENTRY INDEPENDENT
OF CLOCK & SYNCHRONOUS INPUTS
SYNCHRONOUS ENTRY
D MODE OPERATION
OUTPUTS AT to+1
INPUTS AT t,
Q
Q
No Change
H
L
L
H
INPUTS
OUTPUTS AT to+1
Q
Q
SD
CD
L
H
L
H
H
L
5(11)
1(15)
L
L
H
H
L
H
L
H
L = Low Logic Level, H = High logic Level
Toggles
OUTPUTS
D
Q
Q
6(10)
7(9)
H
H
H
L
L
H
No Change
LOADING RULES
INPUT
LOADING
J and K
1 U.L.
Cp and SD
CD' (Note 4)
2 U.L.
3 U.L.
OUTPUTS
FAN OUT
High State Low State
20
20
Q
Q
1 U.L. = 1 TTL Unit Load as defined by the entries
'R
10
10
and IF tables.
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
EQUIVALENT INPUT CIRCUIT
OUTPUT LOW
EQUIVALENT CIRCUIT
OUTPUT HtGH
EQUIVALENT CIRCUIT
r-..-----t--Q
Vee
65(1
:--JT
'~r
OUT
1--"'-'-0 OUT
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)
INPUT CURRENT VERSUS
INPUT VOLTAGE
1.0
0
"Ii
;".0
115'C,\
I
----j 71'~
f'1 \'
1--'
JINPUT
f--.smCITEO-
::·4.0
~
,,-I '
INPUT NOT SmCTEO
·55~C
O°C:'-
r-t--
25~C
4I-
'!::M6.0
-_.
·s.a
'-.
!
-- r---t ---t- ,-e--e--
-10
·2.0
I
0
1.0
4.0
6.0
VIN • I NPUT VOlTAGE· VOLTS
8:0
i~
z
-lD
~
I §'-40
f--
5
Jl
·w
10
i -l
L
8C
I
o_ _ _ _----'
VOUT - OUTPUT VOLTAGE - VOLTS
3-309
~'c- -I::-
joc
V
30
~ 10
IJl
i
fr
/
//
E
E
~
I:
<
<
- c- I---
I
-
10
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
vee· s.ov
~75"C
1--115"C::::
-
t
·55~C
~
-
r-
I,
I
011
0
0.>
1.0
I.>
VOUI - OUTPUT VOLTAGE - VOLTS
1.0
ITT 9024
DUAL JK (OR D) FLIP-FLOP
SWITCHING CHARACTERISTICS (TA = 25°C, Vee = 5.0 V, CL = 15 pF)
$YMBOL
LIMITS
25°C
CHARACTERISTIC
TYP.
MIN.
tpd+
fpd_
J,K,D
J,K,D
25
20
2.0
15
10
25
25
trela.",
t,et.vp
t",.
t",_
SDtOQ
SDtOQ
Toggle Frequency
UNITS
COMMENTS
ns
ns
ns
ns
ns
ns
MHz
Each Flip-Flop
MAX.
SWITCHING TEST CIRCUIT
INPUT PULSE o--...~
50n
J
So
~--_;Cp
Qt----.-u
Qlo-~-+-D
r K CD
Cl Includes probe and jig capacitance
WAVEFORMS
Cp.::::i
\--f--~5V
--I tpd+ ~
OUTPUT
Q OR Ii
---I
---I
___..I.
tpd-I--
'\
•
3-310
1.5V
=
ITT
ITT9300
==mc::::::I:E"""""'' ' ' ' ' ' ' ' ' ' ' _ _ _ _ _''''''''''''....
M'' ' 'S' ' ' ""'4....
-B_i=t_S""'h.....if....
t _R....e..
Q..
is_te_r
Package: Dual In-Line and Flat Pack
SEMICONDUCTORS
LOGIC SYMBOL
MS~
4 Srr SHIFT
m
REGISTER
The ITT9300 Four Bit Shift Register is a high
speed mUlti-functional sequential logic block
which is useful in a wide variety of register and
counter applications. As a register it may be
used in serial-serial, shift left, shift right,
serial-parallel, parallel-serial, and parallelparallel data transfers. The circuit uses TTL
for high speed and high fanout capability, and
is compatible with DTL, and TTL digital integrated circuits.
15 MHz Shift frequency
o
Synchronous parallel entry
o
J,
Cot
Asynchronous common reset
o
Typical power dissipation of 300 mW
o
The input I output characteristics provide
easy interfacing with DTL930, TTL9000,
TTL7400 and MSI families
o
first stage
All ceramic HERMETIC 16 pin Dual InInput diode clamping
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
Characteristics
Storage Temperature
............. -65 DCto +150
Temperature (Ambient)
Under Bias ... -55 D C to + 125
Vee Pin Potential to
Ground Pin ..... -0.5V to + 7
Voltage Applied to Outputs
for high output state
............ -O.5V to + Ve e
Input Voltage (D.C.)
.............. -0.5V to + 5.5
FUNCTIONAL DESCRIPTION
1. A JK input is provided to the first flip flop in
the register. This type of input is the same
as the more common J K input except that
the low voltage level activates the K input.
This provides the greater power of the J K
type input for more general applications and
at the same time the simple D type input
that is most appropriate for a shift register
can be easily obtained by simply tying the
two inputs together.
Line package
o
=
Figure 1
The logic symbol of Figure 1 provides an
indication of the functional characteristics of
the ITT9300 four bit shift register. Several
special logical features of the ITT9300 design
which provide a high degree of general
usefulness are described below:
o
if inputs to
Vee = PIN 16
GND
PIN 8
2. There is no restriction on the activity of the
J or K inputs for logical operation - except
for the set up and release time requirements.
Units
DC
DC
Volts
value
Volts
3. Parallel inputs for all four stages are provided. These will determine the next condition of the shift register synchronous with
the clock input, whenever the Parallel Enable input is low. With the Parallel Enable
input low the element appears as four common clocked D flip flops. When the Parallel
Enable is high, or not connected, the shift
register performs a one bit shift for each
clock input. In both cases the next state of
the .flip flop occurs after the low to high
transition of the clock input.
3-311
ITT9300
MSI 4-Bit Shift Register
TABLE I - TRUTH TABLE
FOR SERIAL ENTRY
4. An internal clock buffer provides both
reduced clock input loading, and the ability
to gate the clock with only a single NAND
gate.
+
(PE = HIGH. MR = HIGH, (n
1) indicales
slale after next clock)
ii
5. The active high output is provided for all
four stages and an active low output is provided for the last stage.
6. A master asynchronous clear input allows
the setting to zero of all stages, independent
of the condition of any other inputs.
IPE= HIGH, MR= HIGH, (n + 1) indicates
state after next clock)
Qo al In+ I
H
Qo al I,(no change)
H
L
Qo al 10 (Ioggles)
H
H
H
TABLE II - LOADING RULES
[1 U.L. = 1 TTL Gate Input Load)
INPUTS
LOADING
J, K: MR, Po, P" P2 & P,
1 U.L.
I5E
2.3 U.L.
Cp
4 U.L.
OUTPUTS
ELECTRICAL CHARACTERISTICS [ITT9300-1XJ
(TA = -55°C to
SYMBOL
CHARACTERISTICS
VOH
Output High Voltage
Output Low Voltage
V,"
Input High Voltage
V"
Input Low Voltage
LIMITS
+25°C
-55°C
MIN.
MAX.
MIN.
2.2
2.4
0.4
2.0
Input Load Current"
J, K, MR, Po, p" p, & p,
I.
0',
6U.L.
+ 125°C, Vee = 5.0 V ±1 0%-)
Vo,
I,
FANOUT
Qo' Q" Q2' Q, &
TYP.
MAX.
2.7
0.2
+125°C
MAX.
MIN.
UNITS
CONDITIONS & COMMENTS
2.4
Volls
rnA
rnA
Vee=4.5 V, 10H= -0.36 rnA
Vee - 5.5 V. 10, = 9.6 rnA
Vee=4.5 V, 10,=7.44 iliA
Guaranteed input high
threshold for all inputs
Guaranteed Input low
threshold for all inputs
Vee=5.5 V
Vee =4.5 V, V,=O,4 V
~A
Vee - 5.5 V, V. -4.5 V·
0.4
1.7
0.4
Volts
1.4
0.8
0.9
0.8
-1.6
-1.24
-1.10 -1.6
-0.97 -1.24
-1.6
-1.24
60
60
Inl1ut Leakage Current'
FMf, Po, p" P, & p,
15
Volts
J, R,
Volts
ELECTRICAL CHARACTERISTICS [ITT 9300-5X)
(TA = DoC to
SYMBOL
+ 75°C, Vee = 5.0 V±5%)
CHARACTERISTICS
MIN.
VOH
Output High Voltage
Vm
Output Low Voltage
V'H
Input High Voltage
V"
InP4t Low Voltage
"
I,
'For CP and
DOC
MAX.
2.4
Input Load Current'
TYP.
MAX.
2,4
3.0
0.2
0.45
0.45
1.9
J, K, MR, Po, p" P, & p,
LIMITS
+25°C
MIN.
2.4
0.45
1.6
1.8
0.85
0.85
-1.6
-1.41
-1.0 -1.6
-0.9 -1,41
60
15
-1.6
-1,41
use load factors in Table"
3- 312
UNITS
Volts
Volts
Volts
0.85
Inp-ut Leakage Current'
J, K, ~, Po, p" P, & p,
PE Input currents,
+75°C
MAX.
MIN.
60
Volts
rnA
rnA
~A
CONDITIONS
Vee=4.75 V, 10H= -0.36 rnA
Vee-5.25V, Im-9.6 rnA
Vee - 4.75 V, 10, - 8.5 rnA
Guaranteed input high
threshold for all inputs
Guaranteed input low
threshold for all inputs
Vee=5.25 V
Vee=4.75 V, VF=0.45 V
Vee - 5.25 V, V. 4.5V
ITT9300
MSI 4-Bit Shift Register
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUTS
YCC
EQUI'/ALENT CIRCUIT
INPUT CURRENT VS INPUT VOLTAGE
PE
CP
0
Vec' 5.0\1
TA' ZloC
.
Vec' 5.0V
TA'
zsoc
-l.0
-0.4
,/
v-
v
• ,Z.O
~
....-V
v
8-3.0
J
.......-
i
-2.0
-1.0
~
1.0
2.0
-5.0
-6.0
-1.0
l.O
v
~~-•. o
-5.0
I
J
/
v-l.a
'~-4.0
-1.6
I
I
~
. ·2. 0
!
~
Vec' 5.0\1
1,,' 2'S"C
·1. 0
VIN -INPUT VOLTAGE:- VOLTS
1.0
2.0
I
".0-1.0 J
l.O
1.0
2.0
VIN - INPUT VOLTAG{' VOllS
VIN - INPUT VOLTAGE -VOlTS
OUTPUTS
OUTPUT CURRENT VERSUS OUTPUT VOLTAGE
LOW STATE
HIGH STATE
V
Vec' 5.0\1
Vec' 5.0Y
1,,'
('Soc
'A' ;5"C
-5.0
/
/
II
/
/
10
o
V
II
o
0,2
0..
0.6
0.1
1.0
l.i?
1.0
YOUT - OUTPUT VOLTAGE - VOLTS
2.0
).0
YOUT - OUTPUT VOLTAG(' VOLIS
3-313
•• 0
5.0
l.O
ITT9300
MSI A-Bit Sh ift Reg ister
SWITCHING CHARACTERISTICS (TA= 25°C)
SYMBOL
tpdt
tpd _
f"
CP,w
t,
t.
t.(PE)
t.(PE)
t,,_(MR)
t.,,(MR)
MR,w
CHARACTERISTIC
Turn Off Delay
Turn On Delay
Shift Right
Frequency
Clock Pulse Width
Set-up Time
Release Time
Set-up Time for PE
Release Time for PI:
Reset Time for MR
Recovery Time for MR
Min Reset Pulse Width
MIN.
MAX.
35
45
TYP.
20
25
25
15
35
35
MHz
15
17
16
26
25
35
20
15
45
CONDITIONS & COMMENTS
Vee =5.0 V, .CL-15 pF
(See Fig. 4' & 6a)
Vee-5.0V, CL-15 pF
(See Fig, 4 & 6c)
UNITS
ns
ns-
ns
ns
ns
ns
ns
ns
ns
ns
0
10
Vee=5,0 V
CL=15pF
(See Figs, 6a & 6b)
SET-UP TIME: ts is defined as the minimum time required forthe logic level to be present at the logic input prior to the clock
transition from low to high In order for the fllp-flop(s) to respond.
RELEASE TIME: tr is defined as the maximum time allowed for the logic evel to be present at the logic Input prior to the clock
transition from low to high In order for the flip-flop(s) not to respond.
RECOVERY TIME FOR MR: trec (MR) is defined as the minimum time required between the end of the reset pulse and the
clock transition from low to high in order for the fllp-flop(s) to respond to the clock.
Figure 2
Figure 3
PROPAGATION DELAY CLOCK TO Q. OR 0'.
OUTPUT VS TEMPERATURE
PROPAGATION DELAY CLOCK TO Q. OR Q.
OUTPUT VS TEMPERATURE
"~~~~-.-r-r-r'-'-'
SH FI9'. Slnd61
~(~S~~
IL
"
S1
~ ~ f-H-f-+-+-+..J,p:J' '--'-t-
.",,~p -r----r-
1
L
~
"
-~s
--
l'(P'C~
-)S -15
'5 ~ e 6S
TEMP£RATl/R[ °c
~
r- -
~ "
'"
~
r-
__ ,---t---t--t-HH
f-H-f-+-+-+-+--+----¥---+4
\--
--. -
-Vt-
~~\"'t-'- r-r-- --' - -j-t-
"f--N-I~-tq++++---I
11 L-:_,L,--c:'_":---"_,,:--"-,-L,,-,,"------,,L,--c:'~:-:-:'I"':-:-:'I",-J
BS 105 125
T[MP{RATURE
·c
Vcc=+5V
YI•
"
Pul.. GenmkH' Outpul
I. Switchin, Tim. (1J>d+ & tpd-) Tlltt
Ris. Tim. < 15 ns
flU Time < 15ns
Amplitud. =:: 4 V
Frtq. - 2 MHz
±
5%
.t 50%
2. Shift Ri,hl Fr.qllincy Test
Rise Tim. < 15 ns
F.IITime
< 15ns
Amplitude
=:: 4V
C. i"~I,","
proM 1M II.
~Iplcill_
duty cycl.
VOUT
VOUT
VOUT
VOUT·
VOUT
Frtq,-lSMHzwilhpul .. "idlh
Idjuslmlntso thltVIN hIS
dllty cycJI of IpproJ. 50%.
Figure 4 -
SWITCHING TIME & SHIFT RIGHT FREQUENCY TEST CIRCUIT
3-314
ITT9300
MSI 4-Bit Shift Register
Figure 6b
Figure 6a
'--___---_-_-_-~F==1511
OuT"u~--d----t~------15V
'~rrliiii) .. - r - - - - - - - Mii
--1---------\::1---------1511
'pd . ..I...
'pd, _ ...
MlfP.
_
-
OOT~_T_ _~~~_ _ _ _ _~;_
_1,edMlil_
Figure 6c
VOUT
Figure 6 -
Frequency:::
liz
X VIN
Frequency
SWITCHING TIME & SHIFT RIGHT FREQUENCY WAVEFORMS
APPLICATIONS - The ITT9300 has been designed to be useful in a wide variety of
applications. The multifunctional capability of
the ITT9300 is illustrated by the applications
shown below.
Figure 7 - EIGHT BIT LEFT/RIGHT
SHIFT REGISTER
This register shifts Left or Right on each shift
clock, depending upon the condition of the
LSI RS SELECT input. If this input is high,
Right Shift occurs and if low, Left Shift occurs.
Figure 8 - SEVEN BIT PARALLEL to
SERIAL CONVERTER
~ 1PARALlUD"TAINPUTS~
'"
REQU(ST
This parallel to serial converter uses a marker
bit, to count the data bits shifted out, so that a
parallel load enable is generated to load the
next parallel word for conversion at the correct
time.
3-315
ITT9300
MSI 4-Bit Shift Register
SELECTOR SWITCH SHOWN IN N=IS POSITION
INPUT
MASTER _________
RESET
Figure 9 -
Po PI P2
9300 SR
Qo QI Q2
-------4
10-+---- OUTPUT
fin + N
N input pulses, where the number N is
determined by the setting of the slide selector
switch as shown or by logic inputs to the
parallel data lines from an external source.
M5D
This counter produces an output pulse for every
2
3
4
5
6
-::f"]
LSD
SELECTOR
SWITCH
8
9
Po Pl P2
9300 SR
P3
Qo
Q3 Q3
7
tl
t
~
L:
1
2
), I
J PE
I-<
hi>~"
K MR
ift>oINPUT
'I'
I
Q3 Q3
~
DIVIDE BY N COUNTER FOR
N = 2 to 15
~
P3
3
4
5
SELECTOR
SWITCH
7
8
Po Pl P2
9300 SR
Qo Ql Q2
P3
6
9
~
),
Ql
Q2
J PE
p-
IP-~:';"
Q3 Q3
to
9007
'\
OUT PUT
fin'TN
COUNT SEQUENCE
~
9
8
7
6
5
4
0
o0 1
o0 0
o0 0
1
1
0
1 000
1 1 0 0
o1 1 0
10 1 1
I I 0 I
I I I 0
o1 1 I
Figure 10 - TWO DECADE
PROGRAMMABLE DIVIDER
This circuit divides by any number "N" from 1
to 100. The selected N is one greater than is
shown on the slide switches. As an example
the switched are showing 56, therefore the
circuit will divide by 57 with this setting.
3-316
ITT9301
__ :J[~~ ____________________M_S_I_O_n_e_-_O_f-_T_e_n_D_e_C_O~de~r
SEMICONDUCTORS
Package: 16-Lead DIP
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
Mst ONE-OF-TEN
DECODER
Characteristics
The ITT9301 is a mUltipurpose decoder
designed to accept four inputs and provide 10
mutually exclusive output. The circuit uses TTL
for high speed and high fan out capability, and
is compatible with DTL, and TIL digital
integrated circuits.
o
Multi-function capability
•
Mutually exclusive outputs
Units
Storage Temperature
............. -65 DCto+150
Temperature (Ambient)
Un'derBias ... -55 DCto +125
Vee Pin Potential to
Ground Pin .: ... -O.5V to + 7
Voltage Applied to Outputs for
high voltage state
., .......... -O.5V to + Vee
Input Voltage (D.C.)
.............. -O.5V to + 5.5
o Guaranteed fanout of 10 TTL loads over
the full temperature range and supply
voltage ranges
DC
DC
Volts
villue
Volts
L'OGIC SYMBOL
15
14
2
o High capacitive drive capability
•
Demultiplexing capability
o Typical power dissipation of 145 mW
e The input/output characteristics provide
easy interfacing with DTL930, TIL9000,
TIL7400 and MSI families
o All ceramic HERMETIC 16-pin
Line package
e Input clamp diodes limit
line termination effects
TABLE I Ao Al A2 A3
L L
H "L
L H
H H
L L
H L
L H
H H
L L
H L
L H
H H
L L
H L
L H
H H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Dual -In-
Figure 1
TRUTH TABLE
1
234 5 6 789
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
GND =PIN 8
high speed
o
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
13121110934567
Vcc' PIN 111
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
FUNCTIONAL DeSCRIPTION
The ITT9301 Decoder accepts four active high
BCD inputs and provides ten mutually
exclusive active low outputs. The active
low outputs facilitate memory addressing
when inverting drivers are used between de":
coder and memory elements.
The logic design of the ITT9301 ensures that all
outputs are high when binary codes greater
than nine are applied to the inputs.
The most significant A3 input produces a
useful inhibit function when the ITT9301 is
used as a 1 out of B decoder. This is illustrated
in the 1 out of 32 decoder shown in Figure 9.
The Truth Table and Loading Rules for the
ITT9301 are shown in Table I and Table II.
3-317
ITT9301
MSI One-Of-Ten Decoder
ELECTRICAL CHARACTERISTICS [ITT9301-1X] (TA = -55°C to +125°C, Vee = 5.0V ± 10%)
SYMBOL
CHARACTERISTICS
LIMITS
+25·C
-SS·C
MAX.
MIN.
MIN.
TYP.
MAX.
Output High Voltage
Output Low Voltage
2.4
2.4
2.7
0.2
0.4
V,H
Input High Voltage
2.0
V"
Input Low Voltage
VOH
Vot
0.4
I,
Input Load Current
I,
Input Leakage Current
Turn Oil Delay Input to Output
Turn On Delay Input to Output
1,.+
Ipd_
1.7
+ 12S·C
MIN.
MAX.
UNITS
CONDITIONS
2.4
Volta
Volts
Vee = 4.5 V, IOH= -O.S rnA
Vcc=4.5V, ioo. a 12.4 rnA
Voc =5.5V, ioo. a 1S.0 rnA
Guaranteed Input high
threshold for all Inputs
Guaranteed Input low
threshold for all I~uts
Vcc-5.5VJ
Voc-4.5 V.l V,=0.4 V
0.4
1.4
Volts
O.S
.09
O.S
-1.S
-1.24
1.10 -1.6
-0.97 -1.24
-1.S
-1.24
15
23
20
60
35
30
60
Volts
rnA
rnA
,.A
ns
ns
Vcc=5.5 V, V.=4.& V
Vcc=5.0V
CL=15 pF
See Fig. 8
ELECTRICAL CHARACTERISTICS (TA = O°C to 75°C, Vee = 5 V ± 5%)
SYMBOL
O·C
MIN.
MAX.
CHARACTERISTICS
VOH
Vot
Output High Voltage
Output Low Voltage
2.4
VIH
Input High Voltage
1.9
VOL
Input Low Voltage
I,
MIN.
TYP.
2.4
3.0
0.45
0.2
-1.6
-1.41
Input Load Current
I,
Input Leakage Current
Turn Off Delay Input to Output
Turn On Delay
MAX.
+ 75·C
MAX.
MIN.
2.4
0.45
1.8
0.45
1.6
0.85
t...+
tpd_
LIMITS
+25·C
-1.0
0.85
'0.85
-1.6
-1.6
-1.41
-0.9 -1.41
15
60
23
35
20
30
60
UNITS
CONDITIONS
Volts
Vcc-4,75 V, IOH- -0.6 rnA
Volts
Vcc-4.75V, 1oL-14.1 rnA
Vcc=5.25 V 1oL=16.0 rnA
Volts
Guaranteed Input high
threshold for all I~uts
Volts
Guaranteed Input low
threshold for all Inputs
rnA
Vcc -5.25VJ
Vcc = 4.75 v.l V,=0.45 V
rnA
p.A
Vcc=5.25 V, V,=4.5V
ns
ns
Vcc -5.0V
CL 15pF
See Fig. 8
TABLE II - LOADING RULES
[1 U. L. = TTL Gate Inputload]
INPUTS
LOADING
OUTPUTS
FANOUT
Ao, A1 , A2 & A3
1 U.L.
0,1,2,3,4,5,6,7,8, & 9
10 U.L.
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
.. ',,·zrc
OUTPUT CURRENT YERSUS
L.
i
-'.
Figure 3
OUTPUT LOW
I
.....
1
/
-
....
r------...---
i
l!
j
~
_
1.0
~'B. ••0 I-I-I-I-HHHI-+Seefig. 7
I-I-I-I-HHHI-+~~ ;:;v
fA - AMBIENT TEMf£RATURE ,·c
flo - AMBIENT llMPERAruRE ,·c
Fig. 7
Fig. 8
TYPICAL ADD TURN ON
DELAY TIME
TYPICAL ADD TURN OFF
DELAY TIME
~
Ml:lz }
V
~~~LL~~D~: ~~on~
2.0 kll
INCLUDES PROBE AND JIG
t.IPACITANCE
VCC
I-I-I-I-HI-HHHH-l
" "H-+-+++1-+-+-H--.J
V
!
2.0
~RSUS TEM~MTURE
G
!l
~
i:
~~~~ee~e~m
Gr-r-r-r-r-,r-r-,r-,r-,r-,-.,
OJ
I-f-HH-+-+-+-+~~
=:!
:~SLES~I=~D}r's:!50 ns
:a4.O I-f-HH-+-+-+--1-SeeFi9.l
~~~~ee~e~m
~aus TEM~MTURE
2
V
§I'0l-t--+++++++++-! fREQUENCY
,.....
.-
.....-
H~~-~~~~~~-r+1--.J
; UHHHHHHHHH-l-l
.Jt•.o HHHHHHHI-+· See fig. 1
HHHHHHHI-+~~~;::V
-55 -3S -15 5.0 25
'e~l6S
15 10 125
'A - AMBlENTnMp£RATURf _oc
F1gi9
Seefig.]
Vee '5.011
)·••0
Cl ' 15 11
-5S
-n
-IS S.D &
45
65
15 105 125
TA - AMBIENT TEMPERATURE _·c
Fig. 10
3-324 .
7.0
"OUT" OUJPUJ VOUAe[" vallS
Fig. 11 -
SWITCHING TIME TEST CIRCUIT
AND WAVEFORMS
..•
ITT9304
MSI Dual Full' Adder
APPLICATIONS - The ITT9304 dual adder has
been designed to be useful in a wide variety of
applications such as addition, parity generation and checking, code conversion, majority
gating and other applications for which this
combination of logic gates may be useful. The
multifunction capabilities of the ITT9304 dual
adder can be seen from reference to the
applications shown.
~ ~
Ie
sse
9304BFA 2A
-OR-
Figure 12 - FUNCTIONAL BLOCK
REPRESENTATION
The principal of duality allows 2 ways of
representing each adder. The circuit is the
same in both cases but the logic diagrams
differ. The dual diagrams facilitate logic design
and allow a greater understanding of the
capabilities of the device.
PROPAGATION DELAY AND
PACKAGE COUNT AGAINST
WORD LENGTH FOR
RIPPLE CARRY ADDITION
400
V
V V
JOO
c
~
ii
~
200
./
15
~
~
.f-------------,
FRDM
STAGE
x- 1
c.
'------------------------t------ Cb
TO STAGE
x+1
'-----cc
Figure 15 -
ADDITION OF SIX VARIABLES
The above design shows how the ITT9304 can
be used in carry save arithmetic. Six input
variable are reduced to two where they can be
added in a parallel adder. Delay between inputs
and outputs is typically 50 ns, allowing
extremely high speed computation. Additional
variables may be added or the concept can be
extended to multiplication, division, and
various other arithmetic operations.
Sx
Cx
TO PARALLEL ADDER
GNO.
G2
GNO.-.,.-h--h
Figure 16 -
BYTE PARITY GENERATION
OR CHECKING
The ITT9304 can be used for parity checking or
generating. The above design uses 2 ITT9304's
to generate parity for an 8 bit byte or check
parity over 9 bits. The delay from input to odd
parity is typically 35 ns. Additional adder
blocks can be used to generate or check parity
over larger word lengths. The concept can also
be used for hamming and cyclic code
generation and checking.
82
Figure 17 - 4 BIT PARALLEL GRAY TO
BINARY CONVERSION
A 4 bit parallel binary to gray conversion is
shown. The adders can also be used for other
cyclic code manipulations.
3-326
ITT9308
ITT- - - - MSI Dual Four-Bit Latch
""",,"'
SEMICONDUCTORS
u~SI
DUAL FOU R-BIT
LOGIC DIAGRAM
lATCH
23 4 6 8 10
~
Active Level Low Enable Gate Inputs
Overriding Master Reset
25 ns Through Delay
The Input/Output Characteristics Provide
Direct Interfacing With ITT DTL and TTL
E DO
0, 02 03
9308 4 BIT LATCH I
MR 110 0, 02 03
Input Clamp Diodes Limit High Speed Termination Effects.
9
157911
The MSllTT9308 is a Dual 4-Bit Latch designed
for general purpose storage applications in
high speed digital systems. The ITT9308 uses
TTL technology. All inputs .incorporate diode
clamps to ground to reduce negative line
transients. All outputs have active pull-up circuitry to provide high capacitive drive and low
impedance outputs in both logic states to provide good A.C. noise immunity.
14 15 16 18 20 22
DO 0,
02 03
9308 4 BIT LATCH 2
MR 110 0,
02 Q3
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
Conditions
Storage Temperature
................ -65 to + 150
Temperature (Ambient) Under
Bias ............ -55 to + 155
Vee Pin Potential to Ground
Pin .............. -0.5 to + 7
Input Voltage (D.C.)
)see Note 1) ..... -0.5 to + 5.5
Input Current (D.C.)
(SeeNote1) ... '" .-30to +5
Voltage Applied to Outputs
(Output High) .. -0.5 to + Vee
Output Current (D.C.)
(Output Low) ............ + 30
13 17 19 21 23
Units
Vee
Gnd
C
= Pin 24
= Pin 12
C
Volts
Volts
mA
value
mA
NOTE 1: Either Input Voltage limit or Input Current limit is
sufficient to protect the inputs.
Description of Latch Operation - Data can be
entered into the latch when both of the enable
inputs are low. As long as this logic condition
exists, the output of the latch will follow the
input. If either of the enable inputs goes high,
the data present in the latch at that time is held
in the latch and is no longer affected by the
data input.
The master reset overrides all other input
conditions and forces the outputs of all the
latches low when a low signal is applied to the
master reset input.
3-327
1119308
MSI Dual Four-Bit Latch
ELECTRICAL CHARACTERISTICS (TA = -55°C to
+ 125°C,
Vee = 5.0 V± 10%, See Note 1)
SYMBOL
CHARACTERISTICS
-55·C
MIN. MAX.
LIMITS
+25·C
MIN. TYP. MAX.
+125·C
MIN. MAX.
UNITS
CONDITIONS
VOH
Output High Voltage
2.4
2.4
2.4
Volts
VOL
Output Low Voltage
V,H
Input High Voltage
V"
Input Low Voltage
Vee=4.5 V. 10H= -0.6 rnA
Inputs at threshold voltages
(V" or V,") (See Note 2)
Vee 5.5 V, IOL 14.4 rnA
Vee =4.5 V. 10L = 11.2 rnA
Inputs at threshold voltages
(V" or V, H) (See Note 2)
Guaranteed input high
threshold for all inputs
Guaranteed input,low
threshold for all inputs
I,
Input Load CUrrent
Eo, E, and MR Inputs
Input Load Current 0 Inputs
1.5 I,
I,
1.51.
I"
2.S
0.21
0.4
2.0
0.4
O.S'
0.9
O.S
-1.6
-1.1
-1.6
-1.6
-2.7
-1.9
-2.7
-2.7
10
60
60
15
90
90
65
90
90
klput Leakage Current
Eo, E, and MR Inputs
Input Leakage Current
Inputs
o
Power Supply Current
90
=OPC to
+ 75°C,
Vee
SYMBOL
CHARACTERISTICS
O·C
MIN. MAX.
LIMITS
+25·C
MIN. TYP. MAX.
VOH
Output High Voltage
2.4
2.4
VOL
Output Low Voltage
V,H
Input High Voltage
V"
Input Low Voltage
I,
Input Load Current
Eo, E, and MR Inputs
Input Load Current '
Inputs
I.
1.51.
I"
0.21
0.45
1.9
3.1
rnA
VI=O.OV
(See Note 3)
p.A
Vee - 5.5 V, V. -4.5 V
rnA
Vee -5.0 V
Input Leakage Current
, Eo, E, and MR Inputs
Input Leakage Current
Inputs
Power Supply Current
2.4
Volts
rnA
Vee=4.75 V, 10"= -0.6 rnA
Inputs at threshold voltages
(V" or V,H) (See Note 2)
Vee-5.25 V,louT-14.4 rnA
Vee =4.75 V, louT=12:7 rnA
Inputs at threshold voltages
(V" or V, H) (See Note 2)
Guaranteed input high
threshold for allinputs
Guaranteed input low
threshold for all inputs
V,=0.45 V
Vee =5.25 V
p.A
V,=O.OV
(See Note 3)
Vee=5.25 V, V.=4.5 V
rnA
Vee-5.0 V
0.45
0.85
Volts
Volts
0.S5
-1.0
-1.6
-1.6
-'2.7
-l.S
-2.6
-2.7
10
60
60
15
90
90
65
117
117
117
See Note 1)
CONDITIONS
-1.6
o
all outputs low
Inputs disabled
UNITS
Volts
!.
o
I V,=O.4 V
Vee =5.5 V
+75·C
MIN. MAX.
1.6
0.S5
Volts
=5.0 V ± 5%,
0.45
1.S
Volts
Volts
1.4
1.7
ELECTRICAL CHARACTERISTICS (TA
1.51,
0.4
all outputs low
inputs disabled
NOTES:
1. Units are pulse tested.
2. Output Voltages are guaranteed for either the input enabled or input diabled case.
3. This current is measured at VIN =0.0 V.\o insure that no current is being absorbed by the device Internally. The maximum
value given guarantees that the maximum instantaneous current that can flow out of the input at VIN =0.4 V is 2.4 rnA.
3-328
ITT9308
MSI Dual Four-Bit Latch
A.C. CHARACTERISTICS
9308 SWITCHING WAVEFORMS
TIME
STORING A ONE
E1=GND
~--13-1
____
1.5V-/
__ I
14
12
"I,
Min. time that data
must be present before
enable to not increase h
t,
Delay from enable to
output turning off
Min. enable pulse
width to store a ONE
Min. time thai data
must remain constant
after removal of enable
Min. lime that data
must be present before
enable to not increase tb
Delay from enable
10 oulput turning on
I,
1.5V
I.
I-;::
t,
-JJfL5V
__Q
__________
I.
I,
STORING A ZERO
E1=GND
LIMIT (See Note 4)
MIN. TYP. MAX. UNITS
DEFINITION
I,
Min. enable pulse
width to slore a ZERO
Min. lime that data
must remain constant
after removal of enable
X
minus
4
-
ns
-
22
X
ns
X
15
-
ns
X
5
-
ns
X
0
-
ns
-
15
X
ns
X
15
X
2
ns
-
ns
NOTE 4: Limits indicated by X will be shown on final data sheets.
1.5V
PIN
LOADING
INPUTS
DO, Of, 02. 0 3
MR, EO,El
1.5
1.0
OUTPUTS
°0. 0 \. 02' 03
9.0
Q
LOADING RULES
All delays are measured wilh VCC=5.0V applied 10 Pin 24 and Pin 12 grounded. Theacllve inpul is driven by a 9002 TTuL gale
with the output loaded with 15 pF. All outputs are loaded with 15 pF.
APPLICATIONS
A_....r-,
B--""-./
C
STROBE
DATA
_~_
O--"L_/
AND-OR ENABLE SHOWING ACTIVE LEVEL
LOW ENABLE GATE UTILITY
9308 4 BIT LATCH 1
3-329
ITT9308
MSI Dual Four-Bit Latch
CLOCK
~7
~r,9016
SLAVE REGISTER
~nTI
Iii
,
Ao
AI
A2 A3
EOoOI
9301 1/10 OECOOER
~8
01·23456789
lilili
yy
Dz
D3
S INGLE MASTER/MULTIPLE SLAVE FLIP-FLOP
4 BITLJm:H1
MR °0 °1
02 03
y
I I I I /I
I I. I I I
I
~
EOo
01
02 ~
93OS·4 BIT LATCH 2
1 I
I 1
I
I
II i
1
I
I
MROO 01
REllISTER
7
02 03
v
M
E
DO 01
02 03
9308 4 SIT LATCH 1
REllISTER
1
MR
00
QI
0 2 03
. 'r' 1 1 1 1
ET9:l<0 UP DECADE COUNTER TC
CLOCK
ITT9308 AS A HOLDING REGISTER
IN COUNTING & DISPLAY APPLICATION
3-330
00
01
02
03
_ InI1r11===~===-=--==c::L~
MSI__
Dual
Four-Input
Multiplexer
__
-===
_________
'T_T_9_30_9
SEMICONDUCTORS
MS~
Package: Dual In-Line and Flat Pack
DUAL FOUR .. INPUT MUlT~PlIEXlER
Multifunction Capability
25 ns Through Delay
III On-Chip Select Logic Decoding
III Fully Buffered Complementary Outputs
• The Input/Output Characteristics Provide
Easy Interfacing with DTL930, TTL9000, TTL
7400 and MSI Families
o Input Clamp Diodes Limit High Speed Termination Effects
GI
III
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
The ITT9309 is a monolithic, high speed, dual
four-input digital multiplexer circuit, constructed with a planar epitaxial process. It
consists of two multiplexing circuits with
common input select logic, each circuit
contains four inputs and fully buffered
complementary outputs. In addition to operating as a multiplexer, the ITT9309 can generate
any two functions of three variables. Active
pullups in the outputs ensure high drive and
high speed performance. Because of its high
speed performance and on-chip select decoding, the ITT9309 may be cascaded to multiple
levels so that any number of lines can be
multiplexed onto a single output buss. The
circuit uses TTL for high speed, high fanout
operation and is compatible with all DTL, and
TTL digital integrated circuits.
Characteristics
Units
Storage Temperature
.............. -65°Cto+150 °c
Temperature (Ambient)
UnderBias .... -55°Cto+125 °c
VCC Pin Potential to
Ground Pin ...... -0.5 V to + 7 Volts
Voltage applied to Output when
output is high .... OV to + Vccvalue
Input Voltage (DC)
(See Note 1) .... -0.5 V to+ 5.5 Volts
Input Current (DC)
(See Note 1) .... -30 mA to + 5 mA
Current into Output when
output is low ............ + 30 mA
NOTE 1: Either Input Voltage limit or Input Current limit is
sufficient to protect the inputs.
LOGIC DIAGRAM
LOGIC SYMBOL
12
\I
10
9
4
5
6
I
13
14
9309
Dual four input multiplexer
Logic diagram
15
Vee ~ PIN 16
GND ~ PIN 8
Figure 2
Figure 1
3-331
ITT9309
MSI Dual Four-Input Multiplexer
TYPICAL INPUT AND OUTPUT
CHARACTERISTICS
OUTPUT
EQUIVALENT
CIRCUIT
INPUT
EQUIVALENT
CIRCUIT
(Output High)
OUTPUT
EQUIVALENT
CIRCUIT
(Output Low)
z,O
Vee'5,0~I
f- I~
, -z.o
r
-
125'e
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT HIGH)
INPUT CURRENT VERSUS
INPUT VOLTAGE
20
125'e r-l II
15C
rl"oO"e
~ F.~h!
100
f
Vee· 5.0V
~
<
o'~
e
~
/
~t-25'e
rp...
15'e'- r--
V
~
125'e
15(
~~.6.0
~
-8.0
-5SoC
-10
-2.0
2.0
4.0
VIN - INPUT VOLTAGE - VOLTS
Figure 3
6.0
8,0
·80
-1.0
..,
r
~
~
~
o'e
r'-25 e
'I
l.O
5,0
Figure 4
FUNCTIONAL DESCRIPTION
The ITT9309 dual four input multiplexer is a
member of the ITT family of compatible
Medium Scale Integrated (MSI) digital building
blocks. It provides this family with the ability to
select two bits of either data or control from up
to four sources, in one package.
The ITT9309 dual four input multiplexer is the
logical implementation of a two-pole fourposition switch, with the position of the switch
being set by the logic levels supplied to the two
select inputs, Both assertion and negation
1.0
-we
~
20
1.0
e
I
5 CI
o
VOUT - ouTPUT VOLTAG£ - VOLTS
cr--
/
125'e
~-4.0
~II~~ r-~
Vee ·5.0V
..II1II
_5'5'0
I
o
1
II
0
0.5
1.0
0.5
2.0
VOUT' - OUTPUT VOLTAGE - VOLTS
Figure 5
outputs are provided for both multiplexers. The
logic equations for the outputs are shown
below:
A common use of the ITT9309 would be the
moving of ,data from a group of registers to a
common output buss. The particular register
from which the data came would be determined
by the state of the select inputs, A less obvious
use is as a function generator. The ITT9309 can
generate any two functions of three variables.
This is useful for implementing random gating
functions.
3-332
ITT9309
MSI Dual Four-Input Multiplexer
TRUTH TABLE
LOADING RULES
.(1 U.L. = 1 TTL gate input load)
OUTPUTS
INPUTS
SELECT INPUTS
S,
S,
I,.
I,.
I,.
I,.
Z.
Z.
l
l
H
H
l
l
H
H
l
l
l
l
H
H
H
H
l
H
X
X
X
X
X
X
X
X
l
H
X
X
X
X
X
X
X
X
l
H
X
X
X
X
X
X
X
X
l
H
l
H
l
H
l
H
l
H
H
l
H
l
H
l
H
l
S,
S,
I'b
I'b
I'b
~3b
X
X
X
X
X
X
l
H
Zb
lb
l
H
l
H
l
H
H
l
H
l
H
l
L
H
H
l
l
H
H
l
l
H
H
l
l
l
l
H
H
l
H
X
X
X
X
X
X
l
H
X
X
X
X
X
X
l
H
H
X
X
X
X
X
X
H
LOADING
INPUTS
1 U.L.
12a, 11a•
lOb' lib' 12b• Ilb•
lOa' Ila'
SO' S,
FANOUT AT LOGIC LEVEL
HIGH
LOW
OUTPUTS
20 U.L.
l,. lb
Za' Zb
18 U.L.
10 U.L.
9 U.L.
l
L=low voltage level
H=high voltage level
X=elther high or low logic level
ELECTRICAL CHARACTERISTICS· [ITT9309-1X] (TA = _55°C to + 125°C, Vc c
SYMBOL
CHARACTERISTICS
VOH
Output High Voltage
Voc
Output Low Voltage
V'H
Input High Voltage
V"
Input Low Voltage
'"
\, (all inputs) Input Load Current
LIMITS
UNITS
-55°C
+25 O C
+125 OC
MAX. MIN. TYP. MAX. MIN.
MAX.
MIN.
2.4
2.4
0.4
2.0
2.7
0.21
0.4
1.7
1.4
0.8
0.9
0.8
-1.6
-1.24
-1.1 -1.6
-.85 -1.24
-1.6
-1.24
I. (all inputs Input Leakage Current
15
40
Volts
Guaranteed input high threshold
for all inputs
Volts
Guaranteed input low threshold
for all inputs
V,=O.4 V
Vee =5.5 V
Input selected
Vee =4.5 V
V.=4.5 V
Vec=5.5 V
Input not selected
mA
mA
60
~A
40
mA
30
24
40
32
t,d_(S, to Z.) SWitching Speed
24
32
Vee Current
'Pulse tested
3-333
CONDITIONS
Volts
60
t,d_(S, to Z.) SWitching Speed
IPDH
0.4
10%)
Vee=4.5 V 10H= -1.2 mA (Pins 1 & 15)
Vee=4.5 V 10H= -1.08 mA (Pins 2 & 14)
Inputs at threshold voltages (V" or V'H)
as per truth table
Vee=5.5 V 10,=16.0 mA (Pins 1 & 15)
10,=14.4 mA (Pins 2 & 14)
Vee=4.5 V 10,=12.4 mA (Pins 1 & 15)
10,=11.2 mA (Pins 2 & 14)
Inputs at threshold voltages (V" or V'H)
as per truth table
Volts
2.4
=5.0 V
ns
ns
Vee = 5.0 V
All inputs high
Vee = 5.0 V, C, = 15 pF. See Figure 8
ITT9309
MSI Dual Four-Input Multiplexer
ELECTRICAL CHARACTERISTICS· [ITT9309-5Xl (TA
SYMBOL
DOC
CHARACTERISTICS
MIN.
VOH
Vm
Output High Voltage
!
MAX. MIN.
2.4
2.4
=aOc to
+ 75°C, Vee
=5.0 V
LIMITS
UNITS
+25°C
+75°C
TYP. MAX. MIN.
MAX.
3.0
2.4
Volts
5%)
CONDITIONS
Vcc~4.75
V lo"~ -1.2 rnA (Pins 1 & 15)
4.75 V lo"~ -1.08 rnA (Pins 2 & 14)
Inputs al threshold voltages (V" or V,")
as per truth table
Vcc~
Output Low Voltage
0.45
0.21
0.45
0.45
Volts
Vcc~
5.25 V 1m ~ 16.0 rnA (Pins 1 & 15)
10' ~ 14.4 rnA (Pins 2 & 14)
Im~14.1 rnA (Pins 1 & 15)
1m ~ 12.7 rnA (Pins 2 & 14)
Inputs at threshold voltages (V" or V,")
as per truth table
Vcc~4.75V
V,"
Input High Voltage
V: l
Input Low Voltage
1.9
I. (all inputs) Input Load Current
1.8
1.6
Volts
Guaranteed input high threshold
for all inputs
Volts
Guaranteed input low threshold
for all inputs
-1.6
-1.41
rnA
rnA
Vcc~5.25 V
Vcc~4.75V
0.85
0.85
0.85
-1.6
-1.41
-1.0 -1.6
- .91 -1.41
'" (all inputs) Input Leakage CUrrent
V,~0.45V
Input selected
15
60
60
pA
Vcc-5.25 V
V,-4.5 V
Input not selected
30
24
43
43
rnA
Vcc~5.0V
t,o,(S,to Z.) SWitching Speed
36
ns
t,o (S,to Z.) Switching Speed
24
36
ns
IPDH
43
Vee CUrrent
Vcc~5.0
V,
All inputs high
C,~
15 pF, See Figure 8
• Pu Ise tested
A.C. CHARACTERISTICS
SWITCHING WAVEFORMS
All inputs are outputs of TTL MIC9000 series gates loaded with
15 pF. All outputs are loaded with the same capacitance
(referred to as CLl and only with capacitan'ce.
tpd ; S. to Z.
tpd; S. to
CONDITIONS
Pins 3, 12 = GND.
Pin 11
v 5
= Vee
Pin 11
tpd; 1'0 to
Z.
CONDITIONS
Pins 3, 13 = GND.
= Vee
15Vr---\..15V
IIID~
IPIIII)1
Z.
CONDITIONS
Pins 3, 12 = GND.
~
-.-ilpd·'----
--llpd--
VOUT·l
IPINI51
__
Figure 6
Figure 7
3-334
Figure 8
IT19309
MSI Dual Four-Input Multiplexer
SWITCHING CHARACTERISTICS
TURN OFF DELAV TIME VERSUS
AMBIENT TEMPERATURE
..
(s, to z.)
Vee •
cl
~.O
II
'I~~
V
.... -..!r'
V
o
2>
I>
AMBI[HIIEMP£RATU~E
fA'
,
--
12>
,'V
12>
o.1>
Figure 12
0
TURN ON DELAY TIME VERSUS
AMBIENT TEMPERATURE
(s, to l.)
""ec' 5,01l
Cl'ISpf
"
/
-
./
--
'"
MM
125
'c
Figure 11
Vee '5,OV
0
21
12>
TEMPERATUR£ •
/
•
.........
AMBI[t~~
Cl'Ur'
.....
TA -AM!I[HTT[MP(RATUIIE'"C
2>
fA •
2
........
='jJ.5.0
.1>
(s, to l.)
•
"cc·,·ov
--
M,"
0
TURN OFF DELAY TIME VERSUS
AMBIENT TEMPERATURE
cl'uP:
1;::"10
s
'"
0-
Figure 10
TURN ON DELAY TIME VERSUS
AMBIENT TEMPERATURE
(I"tot)
"'
r-....
/'
V
0
fA' AM8IEPH T[MFtRATURE ~"c
Figure 9
lO
V
,
.->"
2>
,·c
tol.)
Vee • ~.O II
CL'ISIi
~ t--
---
/'
~ -..!!!
"
""CC·)·OIl
'L'UpE
V
"'"
(I~
(s, to z.)
/'
'-
TURN OFF DELAY TIME VERSUS
AMBIENT TEMPERATURE
TURN ON DELAY TIME VERSUS
TEMPERATURE
,/
--
21
fA' AMBIENTTEMPERATURt:
APPLICATIONS
III
CUT
Figure 15
3-335
--
-f-.
M,"
0
0
.1>
OJ'
~
./
,/
........
I-
2>
fA' AMBIEHllEMP{RATUII£ ·'C
Figure 14
Figure 13
ItT I
,.....
V
121
o'c
.....
I"
12>
ITT9309
MSI Dual Four-Input Multiplexer
Figure 15 - MULTIPLEXING TWO BITS
FROM SIXTEEN SOURCES
This diagram shows the interconnection of five
ITT9309 dual four bit multiplexers to provide
switching of two bits of data from one of
sixteen words onto a tow bit data buss. The
selection of which word will be transferred to
the buss is made by the address supplied to the
So, S1, S2, and S3 inputs. As an example: if
twelve bit words are to be transferred to a
twelve bit buss, the above diagram would be
repeated six times. Notice that the negative
outputs are used at both levels resulting in the
assertion output (negation of the negation) at a
higher speed due to the fact that the through
delay is less on the negation output.
If the word selecting address is held in four TTL
flip flops (two dual packages) enough load
capability is available to select between
sixteen, sixteen bit words.
OPERATION CODE LIST
~
---;1>--+-+--+--+----+-1--____ ..,..,.. "',. .
S,
S,
INSTRUCTION
o
0
0
1
1
SHIFT LEFT
AOD
SHIFT RIGHT
COMPLEMENT
1
UIII
o
1
H~···l··.
Figure 16- GENERAL PURPOSE
ACCUMULATOR
A fast, general purpose accumulator for
computer applications is capable of: 1) shift
left; 2) add; 3) shift right and 4) complement
operations. Only three packages are required to
construct two stages of the general purpose
accumulator shown above.
The D input capability of the ITT9022 is utilized
here to allow each flip flop of the accumulator
to accept the data as presented by the ITT9309
multiplexer.
L~"O"
Under the operation code instructions the
multiplexer provides an input to the ITT9022·
from: 1) adjacent stage to the right for a shift
left operation; 2) adjacent stage to the left for a
shift right operation; 3) output of adders for
add operation and 4) Q outputs of ITT9022 for
the com.plement operation. The operation code
at the right of Figure 18 shows the instruction
codes to perform the various operations. The
accumulator should be capable of 20-25MHz
operation.
3-336
ITT9309
MSI Dual Four-Input Multiplexer
OUTPUT
R(SYIICHRONIl(R
Figure 17 - 16·BIT PATTERN GENERATOR
This application illustrates the use of ITT9309
and ITT9020 in the design of one channel of a
16 bit pattern generator. Each channel requires
1/2 ITT9020, 1/2 ITT9002 and 2-1/2 ITT9309.
Each channel consists of a switch serializerl
pattern generator and resynchronizer sections
with a modulo 16"binary counter common to all
channels.
CDUNT
VALUE t----------~
The two least significant bits and two most
significant bits of the counter control the first
and second stages of multiplexing .respectively. In this manner four bits are multiplexed
on each of the four lines from the first stage to
the second stage. Every four clock times a new
input line containing four multiplexed bits is
selected by the second stage of the serializer
thus serializing the 16 input bits from the
switches.
The resynchronizer flip flop is used to eliminate
decoding spikes.
3-337
TIME
'Tn~
"*
ITT9309
MSI Dual Four-Input Multiplexer
MUlTIVIBRATOAS
'1
'6
's
'.
'3
"
r
.ro.
=
'1'5
.fl~
~·I·
:;'i""
.d
------,
I
I
I
I
I
I
L __
Figure 18 - NON-LINEAR COUNTER
The rate of the non-linear counter depends on
the multivibrator clock frequency selected
under control of the three most significant bits
of the counter. This makes the count rate a
function of both the count value of counter and
frequency of clock multivibrator selected.
-'D~
" 'I
9601
.(lRlliGl.ABU ON( SHOTS
I
I
__ -.J
Clock multiplexing is accomplished by an
ITT9309 dual 4-input multiplexer and one
ITT9002 quad gate. Eight line segments
representing clock rates of the multivibrators
may be adjusted in slope to approximate a
non-linear function.
3-338
-- ITT
SEMICONDUCTORS
ITT9311
Msi One-at-Sixteen Decoder
---~~
Package:' Dual In-Line and Flat Pack
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
MSI ONE-OF-SIXTEEN
DECODER
Units
Characteristics
Storage Temperature
................ -65 to + 150°C
Temperature (Ambient)
Under Bias ...... -55 to + 125°C
Vc c Pin Potential to
Ground Pin ....... -0.5 to + 7 Volts
Voltage Applied to Outputs for
high output state
............. -0.5Vto+Vcc value
Input Voltage (D.C.) -0.5 to + 5.5 Volts
• Multi-function capability
• Mutually exclusive outputs
• Guaranteed fanout of 10 TTL loads over the
full temperature range and supply voltage
range
• High capacitive drive capability
• Demultiplexing capability
• Typical power dissipation of 175 mW
• The input/ output characteristics provide easy
interfacing with DTL, 930 and TTL54/7400 and
9300 families
• All ceramic "Hermetic" 24-pin dual in-line
package
LOGIC SYMBOL
• Input clamp diodes limit high speed line
termination effects
93111 16 DECDDER
• Two input enable gate
o
The ITT9311 is a mUlti-purpose decoder
designed to accept four inputs and provide 16
mutually exclusive outputs. The circuit uses
TTL for high speed and high fan-out capability,
and is compatible with all members of the 930
DTL, 5417400 and 9300 families.
1 2 3 4 5
6 1 B 9 10 11 12 13 14 15
1 2 3 4 5 6 1 B 9 10 11 13 14 15 16 11
Vee
Gnd
= Pin 2~
= Pin 12
TRUTH TABLE
H = High Voltage Level
L= Low Voltage Level
X = Level Does Not Affect
Output
Eo
EI
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ao Al A2 A3
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
L
H
H
L
L
H
H"
L
L
H
H
L
L
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
3-339
7
8
9 10 11 12 13 14 15
H
H
H
H
H
H
H
H
H
L H
H L
H H
H H
H H
H H
H H
H H
H H
H H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
0
1
2
3
4
5
6
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H'
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
ITT9311
Msi One-Of-Sixteen Decoder
I
FUNCTIONAL DESCRIPTION - The 9311 decoder accepts four active high BCD inputs and
provides 16 mutually exclusive active low
outputs, as shown by Figure 1. The active low
outputs facilitate memory addressing when
inverting drivers are used between decoder and
memory elements such as the 9033.
The most significant A3 input produces a
useful inhibit function when the 9311 is used as
a 1 out of 8 decoder.
TYPICAL INPUT' AND OUTPUT CHARACTERISTICS
•
!
prr--+VCC'UV
o
'~-o.s
i
•~'l.S -+ V
OI!
l/
i "r---I- ~
--r-
,
S
---t------t--t-t----j-
:~
i
I i
_',,,
,
I
'1.0
0
1.0
2.0
VI~·I~PUTVOLlAG(·VOlIS
l.O
-r-~'
lL __. __L
r--- - i--r••
t- -I--
+--t-.--+.
r---r---r--- -, ~t-- t- --I- ,---+---ir-----t>''--I-t--t-t---t--i
k-"
-w -;p
'1.0
4.~
o
",0
1/
"'cC' UV
pT.,'"-"r-+-J--IL-t---t-t-t---t--i
-IOH-+-tf-t-/+-H-t-+-1
." H--t-;ft-H-t---t-H-J
V
·ro H-J---t-t-t-t--t-t-t-J
." lL
OJ
'OOS
I.
"~1.0
0
1.0
U
',0
1.0
U
YOUI • OUTPUT VOlTAG[ • VOlTS
Vee
EQUIVALENT
CIRCUIT
~QUIVALENT
1
outputs)
E
CIRCUIT
OUTPUT LOW
TTL INPUT LOAD AND
DRIVE FACTORS
INPUTS
LOADING
All Inputs
1 U.L.
OUTPUTS
DRIVE FACTOR
All Outputs
10 U. L.
=TTL Gate Input Load)
(1 U.L.
1.0
vou, 'OUTPUTVOLlACf' VOlTS
--.J
Vee
Inpuls
10
--"-r-
(
o
t- ---t-- ---
'l,l
-I--
,30
'
t-
~
VCC' USV
1,,'15'C
-t-/:>t--t-t-+-J
t--j;7 -r-
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE OUTPUT HIGH
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE OUTPUT LOW
INPYT CURRENT VeRSUS INPUT VOLTAGE
OUTPUT HIGH
INPUT LOAD AND DRIVE FACTORS
3-340
GRADE
INPUTS
LOADING
59
All Inputs
12/11
51
All Inputs
12/10
GRADE
OUTPUTS
DRIVE FACTOR
59
All Outputs
120/94
51
All Outputs
120178
ITT9311
Msi One-Of-Sixteen Decoder
ELECTRICAL CHARACTERISTICS (TA = DoC to
SYMBOL
VOH
Yo,
Output High Voltage
VOH
Input High Voltage
V"
Input Low Voltage
IF
Input Load Current
I.
Input Leakage Current
Vee Current
Turn Off Delay A Input to Output
Turn On Delay A Input 10 Output
tpd +
tpd_
Ipd+
tpd _
MAX.
2.4
Output Low Voltage
Vee = 5.0 V ±5%) See Note 1
LIMITS
.+2S oC
OOC
CHARACTERISTICS
MIN.
I"
+ 75°C,
MIN.
TYP.
MAX.
2.4
3.0
0.2
0.45
0.45
1,9
+7S oC
UNITS
MIN.
MAX.
2.4
1.B
0.45
1.S
0.B5
0.B5
0.B5
-1.0
-1.6
0.9 -1.41
15
SO
35
SO
23
40
20
35
17
31
17
2S
-1.S
1.41
10
7.0
10
7.0
Turn Off Delay E Input to Output
Turn On Delay E Input to Outpul
Volts
Vee = 4.75 V,loH= -0.6 rnA
Volts
Vee=4.75 V, 10'= 14.1 rnA
Vee=5.25V,lo,,!,16.0rnA
Guaranteed ",put high
threshold for all Inputs
Volts
-1.S
-1.41
60
CONDITIONS
Volts
Guaranteed Input low
threshold for all inputs
rnA
rnA
p.A
mA
Vee=5.25 V I VF=0.45 V
Vee-4.75 V I
,
Vee-5.25 V, V.-4.5 V
Vee-5.0 V
ns
ns
ns
ns
"'.
Vee=5.0 V
C,=15 pF
See test circuit
NOTE 1: Units are pulse tested.
ELECTRICAL CHARACTERISTICS (TA
,
SYMBOL
CHARACTERISTICS
= - 55°C to + 125°0, Vee =5.0 V ±1 0%)
-55°C
MIN.
MAX..
LIMITS
+2SoC
MIN.
TYP.
2.4
2.7
See Note 1
+12SoC
UNITS
MIN.
MAX.
MAX.
2.4
Output High Voltage
Output Low Voltage
2.4
V",
V,
Input High Voltage
2.0
V,
Input Low Voltege
0.8
0.9
0.8
I,
Input Load Current
-1.6
-1.24
-1.10 :"'1.S
-0.97 -1.24
SO
15
55
35
23
35
30
20
26
17
16
21
-1.S·
-1.24
60
V.....
I,
I.,
l~_
l"\;!_
t~_
l"\;_
0.4
Input Leakage Current
V" Current
Tum Off Delay A Input to Output
Tum On Delay A Inpul to Output
Turn Off Delay E Input to Output
Turn On Delay E Input to Output
0.4
0.2
0.4
1.4
1.7
Volts
Volts
Volts
Volts
mA
rnA
p.A
rnA
ns
ns
ns
ns
NOTE 1: Units are pulse tested.
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
PULSE GEN CHARACTERISTICS
Freq. = 1 MHz
Pulse Width = 100 ns
1.=I,':15ns
Amplitude = 4 V
'- 4 --- ,.,,• !lout
"I neludes all probe and Jig capaci¥ince
'.'
3-341
~-l
r"'" --::J 1'--"'("f
--\IR--
CONDITIONS
Vec=4.5 V,loH= -0.6 rnA
Vee-4.5 V, 10..= 12.4 rnA
Vec=5.5V,lo,=1B.OrnA
Guaranteed Inpul high
threshold for all Inputs
Guaranteed Inpul low
threshold for allinpuis
Vee-5.5 V I
VF=0.4V
Vee 4.5 V I
Vee 5.5 V, V. 4.5V
Vee -5.0 V
Vce=5.0 V
C,=15 pF
See lest circuit
ITT9311
Msi One-Of-Sixteen Decoder
ENABLE
OUTPUT SELECTION
GND
BCD CODE
MICI9f1 1/16 DECODER
DECODE ANY BcnCODE
Decode any BCD code using a 9311 element.
Any 4 bit BCD code may be decoded by
selecting outputs, examples are shown in the
table.
CLOCK
DECIMAL
DIGIT
8421
5421
EXCESS
3
GRAY
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
8
9
10
11
12
3
4
5
6
7
8
9
10
11
12
0
1
3
2
6
7
5
4
12
13
PROPAGATION DELAY ENABLE INPUT
TO OUTPUT VERSUS TEMPERATURE
ADDRESS
..
"~~~~:~1~_4.--~+-~-+~~
~~~~-4--~+-~-+~~
161-+--+--t--1---I--+--+---i1--i
5IX MIN ,59X MIN
E:t::t:j~·"·~···E···~
. ·i··~····3·"E···~····f::r:l
25
75
125
8.0
?S
TA - AMBIENT TEMPERA7URE -'C
PROPAGATION DELAY DATA INPUT
TO OUTPUT VERSUS TEMPERATURE
70
CLOCK DEMUL TIPLEXING
The 9311 can be used as a clock demultiplexer.
The binary address designates to which
register or counter the clock is sent. Up to 5
register counter stages can be driven by one
decoder ouput allowing word lengths of 20 bits
to be controlled. Any sequential ·circuit in the
9300 MSI family· can be used in this
configuration.
3-342
'IlII'I--
2O~+--+--4-11--+-~-+~~
10 t;;;;J,;;;;..J.......L--I~"""'SI'""X~MI~N.!!:?!::.i.'....:'!
.. :::
....=1
...
-55
25
75
TA - AMBIENITEMPERAIURE -'C
SWITCHING PERFORMANCE
125
ITT9312
Msi Eight-Input Multiplexer
SEMICONDUCTORS
Package: Dual In-Line and Flat Pack
EIGHT",~NPUT
MUl T~Pl[EXIER
MSI
LOGIC SYMBOL
11 ~~~~~~~~---,
12
10 11 12 13 14 15 ~ I)
51
9312 0 I1IPUT MULTlPUX£R
13·
L5~2____~~~~____-d
o Multifunction Capability
o 25 ns Through Delay
lJ On-Chip Select Logic Decoding
o Fully Buffered Complementary Outputs
oThe Input/Output Characteristics Provide
Easy Interfacing with DTL930, TTL9000,
TTL7400 and MSI Families
o Input Clamp Diodes Limit High Speed Termination Effects
14
Vee
GND
15
==PIN
16
PIN8
Figure 1
LOADING RULES
The ITT9312 is a monolithic, high speed, eight
input digital multiplexer circuit. It provides in
one package the ability to select one bit of data
from up to eight sources. The ITT9312 can be
used as a universal function generator to
generate any logic function of four variables.
Both assertion and negation output are
provided. TTL circuitry with active pullups on
the outputs provides high speed, high fanout
operation and is compatible with all DTL and
TTL digital integrated circuits.
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
Characteristics
Units
Storage Temperature
.............. -65 0 Cto+150 °c
Temperature (Ambient)
Under Bias .... -55°C to + 125°C
Vc C Pin Potential to
Ground Pin ...... -0.5 V to + 7 Volts
Voltage Applied to Output when
output is high .... 0Vto +Vcc value
Input Voltage (DC)
(See Note1) ... -0.5Vto+5.5 Volts
Input Current (DC)
(See Note1) .... -30mAto +5 mA
Current into Output when
output is low ............ + 30 mA
OUTPUTS
FAN-OUT
High State
I
Low State
18
20
I
9
10
Z
Z
=
1 U.l. 1 nL Unit load
1 U.l. Is doflnod by tho entrlu
IR and IF In the tablo on page 3.
Figure 2
TRUTH TABLE
E
82 81
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X X X X X
L L L L X
L L L H X
L L H X L
L L H X H
L H L X X
L H L X X
L H H X X
L H H X X
H L L X X
H L L X X
H L H X X
H L H X X
H H L X X
H H L X X
H H H X X
H H H X X
NOTE 1: Either Input Voltage limit or Input Current limit is
sufficient to protect the inputs.
3-343
80
10
11
12
X
X'
X
X
X
L X
H X
X L
X H
X X
X X
X X
X X
X X
X X
X X
X X
X
X
X
X
X
15
16
17
Z
Z
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
L X X
H X X
X L X
X H X
X X L
X X H
X X X
X X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
13
14
L
H
H = High voltage level
L= Lw voltage level
X = Level does not affect output
Figure 3
ITT9312
MSI Eight-Input Multiplexer
The ITT9312 provides the ability, in one
package, to select from eight sources of data or
control information. By proper manipulation of
the inputs, the ITT9312 can provide any logic
fuhction of four variables and its negation.
Thus any number of random logic. elements
used to generate unusual truth tables can be
replaced by one ITT9312.
FUNCTIONAL DESCRIPTION - The ITT9312 is
a logical implementation of a single pole - 8
position switch with the switch position
controlled by the state of three select inputs,
80, 81, 82. Both assertion and negation
outputs are provided. The enable input (E) is
active low. When it is not activated the
negation output is high and the assertion
output is low regardless of all other outputs.
OUTPUT LOW
EQUIVALENT CIRCUIT
OUTPUT HIGH
EQUIVALENT CIRCUIT
EQUIVALENT INPUT CIRCUIT
Vee
."
100
'--~~OOUT
..•
INPUT CURRENT VERSUS
INPUT ¥GLTAIE
INM NOT SEllCT£D
•
.-•
IEijliIIIiIi
rl.l~
..
,,-
"'·c, \
",'
l'O'c
""C1ID
I
~:\25'c
~;~
•
2.0
".0
6.0
...
•• 0
I
-1.0
,
I[fffj
;:::~- I-
S.D·
Figure 4
Figure 5
Vo+<
Output High Voltage
VOL
Output Low Voltage
2.4
2.4
0.4
TYP.
••I
7.'
J·c- f-- -
~
"-
3-344
I.'
...
to +125°C, Vee =5.0 V ±10%)
2.4
0.4
I.'
'.1
Vour - OUTPUT VOLTAGE - VOLTS
Figure 6
+12SoC
UNITS
MAX. MIN.
MAX.
2.7
0.21
I
,,'C I-~
~ I
I.'
LIMITS
+2S oC
~,,·c_ ~.~
-55"C
I
T.
VOUT - OUTPUT VOLTAGE - VOlTS
-SSoC
MAX. MIN.
MIN.
'V-
/
//
:".-
Y,N -INPUl VOLTAGE - VOLts
CHARACTERISTICS
f..-"'·C:::
~
;.".c
'c
I.'
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
"
.".~
ELECTRICAL CHARACTERISTICS· (MIC9312-1X) (T..,= -55°C
SYMBOL
.. -
/
I
IF-
of.
-2.D
1•.• v I I
Inputsllgnd.
~·c
'II'C
Vee
,,'C
•
·W
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT KlGH)
.04
CONDITIONS
Volts
Vcc-4.S V 10H= -1.2 mA (Pin lS)
Vee=4.SV 10+<= -1.08 mA (Pin 14)
Inputs at threshold voltages (VOL or V,H)
as per truth table
Volts
Vee-S.S V 1oc=16.0 mA (Pin lS)
IOL=14.4 mA (Pin 14)
Vcc=4.S V IOL=12.4 mA (Pin lS)
101.=11.2 mA (Pin 14)
Inputs at threshold voltages (VOL or V,H)
as per truth table
1119312
MSI Eight-Input Multiplexer
ELECTRICAL CHARACTERISTICS· (MIC9312.1X) (TA = - 55°C to
CHARACTERISTICS
SYMBOL
-55°C
MIN.
MAX. MIN.
LIMITS
+25 O C
TYP.
+ 125°C,
Vee = 5.0 V ±10%) (continued)
CONDITIONS
UNITS
+125°C
MAX. MIN.
MAX.
Volts
1.4
15
60
60
"A
27
40
40
rnA
Guaranteed Input hlgn t reshold
for alt Inputs
Guaranteed input low threshold
for all inputs
V, 0.4 V
Vcc=5.5 V
Input Selected
Vcc=4.5 V
V.-4.5V
Vee-5.5 V
Input not selected
Vee 5.0V
Switching Speed
23
34
Switching Speed
25
36
ns
ns
Vee - 5.0 V, See Page 4
C, 15 pF
V'H
Input High Voltage
V"
Input Low Voltage
1.7
2.0
I, (all inputs) Input Load Current
0.9
0.8
-1.6
-1.24
1.6
1.1
-0.85 -1.24
,1.6
-1.24
rnA
rnA
I. (all inputs) Input Leakage Current
IPDH
Vee Current
t,d> (S, to Z)
t,,_ (S, to Z)
Volts
0.8
40
• Pu Ise tested
ELECTRICAL CHARACTERISTICS' (MIC9312·SX) (T A =O°C to
CHARACTERISTICS
SYMBOL
VOH
Output High Voltage
Voc
Output Low Voltage
V'H
Input High Voltage
V"
Input Low Voltage
OOC
MIN.
MAX. MIN.
2.4
2.4
I, (all inputs) Input Load Current
Vee Current
1""
Switching Speed
Switching Speed
(S, to Z)
t,,_ (S, to Z)
+7S o C
UNITS
MAX.
MAX. MIN.
3.0
2.4
0.45
1.8
0.85
1.6
-1.41
1.0
1.6
-0.91 -1.41
60
15
43
27
23
25
43
34
36
CONDITIONS
Vee=4.75 V 10H= -1.2 rnA (Pin 15)
Vee=4.75V IOH=-1.08rnA(Pin14)
Inputs at threshold voltages (V" or V'H)
as per truth table
Vec=5.25 V Im= 16.0 rnA (Pin 15)
loc=14.4 rnA (Pin 14)
Vcc=4.75V loc=14.1 rnA (Pin 15)
1m=12.7 rnA (Pin 14)
Inputs at threshold voltages (V" or V,")
as per truth table
Guaranteed input high threshold
for all inputs
Guaranteed input low threshold
for all inputs
..
V,=0,45 V
Vcc-5.25 V
Input Selected
Vce =4.75 V
Volts
0.45
Volts
0.85
Volts
1.6
0.85
I. (all inputs) Input Leakage Current
IPDH
TYP.
0.21
0.45
1.9
LIMITS
+2S o C
+ 75°C, Vee = 5.0 V ±5%)
Volts
1.6
~1,41
rnA
rnA
60
"A
Vee-5.25 V
V.-4.5V
Input not selected
43
rnA
ns
Vee-5.0 V
Vee - 5.0 V, See Page 4
C,-15 pF
ns
'Pulse tested
A.C. CHARACTERISTICS
All measurements are made with Vee = 5.0 V
applied to pin 16 and with pin 8 grounded. The
active input is driven by an ITT9002 TTL gate
with the output loaded with 15 pF. Both
outputs of the ITT9312 are loaded with 15 pF.
TURN ON DELAY VERSUS
AMBIENT TEMPERATURE;
TURN OFF DELAY VERSUS
AMBIENT TEMPERATURE;
1.5V IIIPUT IPlIIII]
f ---=\;
=:j f= --l
tpd.
OUTPUT (PII151
1.5V--+
0tfMt Conditions: Plitl 1. 8, 10. 12. 13 = Gnd
Pin 2 Vee throulh 1.0 kG
=
Pin 16 = Vee
So to Z
So to Z
t,d: S, to Z
r-
-1.5Y
t,d_
~
~~~
;ss:vrt-
!~ ~~~~~~~~~.~
.~~~~~-~4-~~~~
,.-
~ ~~~t--~~4r4r4-,,~,~~~
•
t--
M~~~~~~-4-4-4
-'BUlK
'<:~~~*=1
,
~~pv
."
.-
-
'.
tA'~I{f(lTtMP[RA1URl
Figure 7
3-345
;·c
lA "AM81lNT ttMPlRATUI!f.·"C
Figure 8
ITT9312
MSI Eight-Input Multiplexer
\,d:
I. to
Z
1.5V--!\-1.5V
::::::J 'pd--I ''''1=
1.5V -=-t~==:.i-P;
Other Conditions: Pins I, 8. 10, 12, 13 =Gnd
Pin 2 =Vee throu,h 1.0 kO
Pin 16 =Vee
1."-+---=\-1.5V
=1 'pd- r-- -1 .... 1:::
INPUT [PIN II
~
1.5V--\
Oth,r Condllions: PIn, 8. 10. 11. 12. 13
Pin 16 Vee
=
=Gnd
So to l
So to Z
I. toT
I. toT
TURN ON DELAY VERSUS
AMBIENT TEMPERATURE;
TURN OFF DELAY VERSUS
AMBIENT TEMPERATURE;
TURN ON DElAY VERSUS
AMBIENT TEMPERATURE;
TURN OFF DELAY VERSUS
AMBIENT TEMPERATURE;
r-
INPUT IPlIII1I
~~~-r-r~~~ro
~~S ;::vrl-+-+-+-+-t--I
"CC"5.0V
CL '15pF
,
0
,"~-+-+~~+-+-~
~ .~-+-+~~+-+-~
1/
~
./
i--'" >---
__
~·~~-T-r-+-+-T-r~
"-
',,,,-
jo ~ t:::r:ttM~~
I-'
0
jl. 10
~1"-++=t::!=1=+::j::t~
0
fA -AMBI[NTTEMPEIUTUR! ··C
'A,AMBI[WT(MJ'ERATURE ··C
'A,MGIENTTlMPERATURE"C
'A,AMBIENTTEMPERAlURE"C
Figure 9
Figure 10
Figure 11
Figure 12
TURN OFF DELAY VERSUS
AMBIENT TEMtERATURE;
E to Z
TURN 01'1 DELAY VERSUS
AMBIENT TEMPERATURE;
::::::....Jf----\=! 'pd'
-l ',,- r-
'=
llFUTIPtNIOI _ _
-_-_-::..J-f
OUTPUTI'" "I _ _ _
=
\=-
==
Pin 16
Vee
,
~ ~~-+-+~~+-+-~
~~~~-+~-r~+-t--I
~~~-+-+-r~+-t--I
~
~~~-+-+~~+-+/~~
~~~~~~~~~~-+~~
,/
.0
~f~ ~~ovrl-+~~+-+-1
,
~
OHIor CondlUons: Plnl8, 11. 12. 13 Gnd
Pin 1 Vee through 2.0
Etol
j.1O~~
'.,
~'~~-+~-r~+-t--I
:0 ~~~~~~~~~~
ji ~~;;;t+~:j::+=H
N
10
0.,'-,...l-.L..c......,L....J--'--'--'-.....J
',\'AMSIENTTEMFtRA1URE-
'c
Figure 13
r,,·"MIII[NTUMI'[R"TUR[.·C
Figure 14
APPLICATIONS
A Multi-Port Memory Module
The four bit by eight word multi-port memory
module shown in the diagram below uses only
thirteen MSI packages; four ITT9308 24 pin
dual four bit latches, eight ITT9312 eight input
multiplexers, and one ITT9301 one-out-of-ten
decoder.
The module as shown is capable of simultaneously reading from two independently
specified locations and writing into a third
independently selected location. The necessary
enables are provided so that a number of these
modules may be connected together to produce
a larger memory. As an example a sixteen bit by
sixty-four word memory would require thirtytwo of the modules shown below.
By connecting this type of memory to a
function generator unit, a processor could be
constructed that would execute three address
instructions at a very high speed on the data
contained in this type of memory. In order to
utilize the speed of the memory the instructions would also have to be contained in fast
semiconductor memory.
3-346
ITT9312
MSI Eight-Input Multiplexer
won.
."IT[
DATA
AODMSS
NOOUI..E
ENAOI..
III ,--J-
WRITE
5 TROD[
ADDRESS
MODULE
In
'i!
;! ..
WORD
STORAGE
~
aib-..,-::-:~
.. ~.t--
_r;-;;;
- :~ ..
- ~~
- ~I-
.r&<6'~
.
~.. ~-
-
. & ..~
I.
: i do-
_r::-.'
~.
.r~ ..
-
r-
or
I.
r=-r -
• B q},77""~
.. ~ .. t--
~
~r;u;;
~
'---
I.
.. . ~
~
"S8
."
~
I~ ~ ...
0
0 0 outputs of tho latch, etc.
~S
• ' B DI:>-
...-:-"
BIT 2
being the 0 0 outputs of the
latches, MI and MI Inputs
being the 01 outputs of the
latch, M1 and M z inputs being
-- :~ ..
- ~~
-- _
- ;~
,6S.rt-.
~
• B.b--
_... 5 -IO-H-t+--
'All Multip lexer connections
ar. sImI! ar to Mo and M3
with Inpu Is to Mo and Mo
~
,."........",
~!
."
"
.
~~t=
• D ;):>--
:~ ..
~-
-
"~F
i.-
T_
~
• D • P-
,.,..........,,'
~ I - I>-t+t+-- ." ,
.!";
tb=
I.
......
~!
'"
~-
.!";
b;n.
1 •
:~ ..
__
A
WORD
.;.L
0-7
~~.r
L-
NOCULE ENAlI..E
~
~;
l31li''''''
S' , . ,
ADDRESS.
ENA~f:
~
.. " 'J 's
11-2 1 t
A
r::w,
E
I
~
:~~!
~!
;~
or •
."
-
Tt!:!-
• DDI:>-
Fi gure 15
APPLICATIONS
3 Bit Comparator
Three bits of data to be compared are supplied
to the address and select inputs of the ITT9301
and ITT9312 respectively. If Ao, A1 , A2, and Bo,
81, 82 compare, the mutually exlucisve active
low output of the ITT9301 1/10 decoder and the
selected input of the ITT9312 multiplexer will
be coincidental and COMPARE OUT will be
high. The COMPARE ENABLE must be low to
permit compare operation.
3 BIT COMPARATOR
INTERCONNECTION DIAGRAM
FOR 9 BITS
CO"'''4RE
TO
~EXT
COMPAIIE
E~
1Or.~~~~.-;-;-~
~
r- ;~~ ~s;v -+--+--+--+-+-+--1
"I-t--T-+-+-+-++-t--j
• ..
~
;"P¥t . !!~~L~f
7
I
TURN OFF DElAY TIME VERSUS
AMBIENT TEMPERATURE (f to lJ
TURN ON DElAY TIME VERSUS
.,ArM-::B_IENTo=T...,EM--,PE_RA..,.J_U"T"RE_(,S_to,Z.;'>
;::
a
I- ~cc'
s.ov-+-+-+-+-+-+-I
CI"5~ I
50
CL'UrI
~
..u:. ~'i:"'/
~ r-st;l;-
.~
~ZD~TYP.
~
•
k.
......
l,...;
"'"'
"P.
TA'AMlllNT llMPlAATUR['·C
'A: AMlIOO ltMPlRATUII[ ,. C
, I=i•..k.,k
"1".....·:- - f a
...
n
, "
'"
TURN ON DElAY TIME VERSUS
AMBI.ENT TEMPERATURE ([to ZJ
TURN OFF DElAY TIME VERSUS
AMBIENT TEMPERATURE (I" to l,>
TURN ON DElAY TIME VERSUS
AMBIENT TEMPERATURE (I,. to lJ
:;.. 10 51
a
f-:CC'S,'!'I
1ADf ""N. ......~(;.iiADi.Mi;.:.. .
•
'oICC· 5•0 'ol
'UFI
I
.1-- I-- f-
...
+-+--+--+-+-+-1
Cl'UrI
~",,:j.Lf-P'
."'~'+""';:-"""'7r--
, f- f- f,
VCc·J.DV
i"
i "f-+-+-+-+-+-++-+-~
cl
1YP
~~ b
59G1tAOlMIN-
" 51GRADlMlN
'= j:::;:::
'A • AMlI£NTTlMPf.ATUIE·"C
3-355
.....
'"
S
IH~~-+~~4-+-+-I
~ f-I-+-... ~~~.~,p.-t:;p
11
I ft.
SIGlADEiW:
i
:i'" f-~I-" ".....
,...
'-",=1,-
".........
I-
f-I-fn
",.
ITT9322
Quad Two-Input Multiplexer
"'T.""12
APPLICATIONS
Dual 10 Input Multiplexer
II '. '"
II
MULTfUllI1
....TINII. I OUTPUT
SHIFT LEFT, SHIFT RIGHT,
PARALLEL LOAD REGISTER
OPERATION CODE LIST
A
B
Operation
L
L
Perallel Load
H
L
Shift Left
L
H
Shift Right
H'
H
Shift Right
....'1mI1i 2 OU'M
DATUUI SII,n u"
This register will shift left, shift right, and load
4 bits of parallel data according to the
operation code applied to A andB.
l1li111 ••
lu.'.....fam
....·---'---+l+r---......- - -__H-tt--~
APPLICATIONS
Register Selection
The 9322 can be used to select parallel data
from two multiple bit sources. Illustrated above
is a counting and display system where the
9322 selects the content of one of the counters
for display.
==----+l+I-T---------t+t+r----~ ""U•••IIUIII
. . . - - - _ , I 0 I l ......111&111
3-356
_
ITT9328
MSI Dual 8-Bit Shift Register
I'~:\T~'
"
c:::::!I="'"""=======_____=-=""""=========
,
,,}
,",
SEMICONDUCTORS
MS~
DUAL
Package: Dual In-Line and Flat Pack
8c>B~T SH~FT
REGISTER
(',) 20 MHz Shift Frequency
II.)
•
•
..
.,
o
Two Input Multiplexer Provided at Data Input
of Each Register
Gated Clock Input Circuitry
Both True and Complementary Outputs Provided from Last Bit of Each Register
Asynchronous Master Reset Common to
Both Registers
Typical Power Dissipation of 300 mW
Compatible with TTL and DTL families
LOGIC DIAGRAM
13.11 12
14
15
a Input Diode Clamping
The ITT 9328 is a high speed serial storage
element providing sixteen bits of storage in the
form of two eight bit registers that will shift at
greater than 20 MHz rates. The multi-functional
capability of this device is provided by several
features: 1) Additional gating is provided at the
input to both shift registers so that the input is
easily multiplexed between two sources. 2) The
clock of each register may be provided
separately or together. 3) Both the true and
complementary outputs are provided from each
eight bit register, and both registers may be
master cleared from a common input.
ABSOLUTE MAXIMUM RATINGS
(abOve which useful life may be impaired)
Characteristics
Storage Temperature
................ -65 C to + 150°C
Temperature (Ambient) Under
Bias ............ -55 Cto +125 °C
Vee Pin Potential to Ground
Pin ............... -0.5Vto +7 V
Voltage Applied to Outputs for
high output state.-0.5V to + Vee value
Input Voltage (D.C.) -0.5V to + 5.5 V
Vee = Pin 16
Gnd = Pin 8
FUNCTIONAL DESCRIPTION - The two 8 bit
shift registers have a common clock input
(pin 9) and separate clock inputs (pins 10 & 7).
The clocking of each register is controlled by
the OR function of the separate and the
common clock input. Each register is composed of eight clocked RD master-slave
flip-flops and a number of gates. The clock OR
gate drives the eight clock inputs of the
flip-flop in parallel. When the'two clock inputs
(the separate and the common) to the OR gate
are Idw, the slave latches are steady, but data
can enter the master latches via the Rand S
input. During the fir,st low to high transition of
,either, or both simultaneously, of the two
clock inputs, the data inputs (R and'S) are
inhibited so that a later change in input data
will not affect the master; then the now trapped
information in the master is transferred to the
slave. When the transfer is complete, both the
3-357
ITT9328
MSI Dual 8-Bit Shift Register
master and the slave are steady as long. as
either or both clock inputs remain high. During
the high to low transition of the last remaining
high clock input, the transfer path from master
to slave is inhibited first, leaving the slave
steady in its present state; second the data
inputs (R and S) are enabled so that new data
can enter the master. Either of the clock inputs
can be used as clock inhibit inputs by applying
a logic high signal. Each a. bit shift register has
a two input multiplexer in front of the serial
data input. The two data inputs Do and 01 are
controlled by the data select input Os following
the Boolean expression:
Serial data in: SD
=Os Do + Os 01
An asynchronous m'aster reset is provided
which, when activated by a low logic level, will
clear all sixteen stages independently of any
other input signal.
'
LOADING RULES
(1 U.L. TTL input gate load)
=
INPUT
MR,DODI
SeparateCP (pins 9 & 10)
Os
Common CP (pin 9)
FAN IN
1 Unit Load
1.5 Unit Loads
2 Unit Loads
.3 Unit Loads
OUTPUT
FAN OUT
6 Unit Loads
07,07
ELECTRICAL CHARACTERISTICS ITA = -55 0 C to + 1250 C, Vcc= 5.0V:!: 10%1
I
LIMITS
_&6 oC
+25oC
+ 1Z6oC
MIN. MAx:. MIN. TYP. MAX. MIN. MAX. UNITS
. 2.4
Volts
2.4
2.7
2.4
SYMBOL
CHARACTERISTICS
VOH
Output High Voltage
VOL
Output Low Voltage
VH
I nput High Voltage
VL
Input Low Voltage
0.8
IF
Input Load Current (MR,Do'D II
-1.5
1.51F
I nput Load Current
0.4
0.2
0.4
1.7
2.0
0.4
1.4
TEST CONDITIONS
VCC=4.5V,IOH=-0.36mA
Volts
VCC=5.5V ,IOL=9.5mA
Volts
VCC=4.5V,IOL =7.44mA
Guaranteed input high
Volts
Guaranteed input low
threshold for all inputs
0.9
0.8
threshold for all inputs
-2.4
-1.0 -1.5
-1.5 -2.4
-1.5 mA
-2.4 mA
(separate CP pins 7 & 10
Vcc=5.5V
21F
I nput Load Current (Dsl
-3.2
-2.0 -3.2
-3.2 mA
31F
Input Load Current (common CP pin 91
-4.8
-3.0 -4.8
-4.8 mA
VF=0.4V
Ip
Input Leakage Current (MR.Do·Dll
SO
10
60
SO
J.!.A
1.51p
Input Leakage Current
90
15
90
90
P.A
21'p'
Input Leakage Current (Dsl
120
20
120
120
P.A
VR=4.5V
31p
I nput Leakage Current (common CP pin 91
1801
30
180
180
Ipo
Power Dissipation
365
300
365
365
P.A
mW
Vcc=5.0V
(separate CP pins 7 & 101
Vcc=5.5V
SWITCHING WAVEFORMS
1.5 V
_ 1_- tpd-lii)1
ii)-_-_-_-_~\
.
.
-
I-::
1.5 V
tpd'lii)1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. - - - - - - - - - - - / -
NOTE: 07 is connected to D1. Other clock is grounded.
Figure 1
3-358
-~
1.5V
1119328
MSI Dual 8-Bit Shift Register
ELECTRICAL CHARACTERISTICS ITA = oOc to + 75°C. Vee = 5.0V± 5%1
LIMITS
DoC
SYMBOL
CHARACTERISTICS
+7SoC
+ 25°C
MIN. MAX. MIN. TYP. MAX. MIN. MAX. UNITS
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
2.4
0.45
3.0
0.2
Volts
2.4
0.45
0.45
Volts
TEST· CONDITIONS
VCc=4.75V.loH=-0.36mA
VCC=5.25V. IOL =9.6mA
Vcc=4.15V. IOL =8.5mA
V'H
Input High Voltage
V'L
Input Low Voltage
0.85
0.85
0.85
Volts
IF
Input Load Current IMR.Do·DI I
-1.6
-1.0 -1.6
-1.6
mA
1.51F
Input Load Current
-2.4
-1.5 -2.4
-2.4
mA
1.9
1.6
1.8
Volts
Guaranteed input high
threshold for all inputs
Guaranteed input low
threshold for all inputs
Iseparate CP pins 7 & 10)
Vcc=5.25V
21F
Input Load Current IDsl
-3.2
-2.0 -3.2
-3.2
mA
31F
Input Load Current
-4.8
-3.0 -4.8
-4.8
mA
IR
Input Leakage Current IMR.Oo·O,1
60
10
60
60
fJA
1.51R
Input Leakage Current
90
15
90
90
fJA
VF=O.4V
Icommon CP Din 91
Vcc=5.25V
Iseparate CP pins 7 & 101
21R
Input Leakage Current (Os)
120
20
120
120' fJA
31R
Input Leakage Clirrent
180
30
180
180 . jlA
Ipo
Power Dissip8ti!l"
365
300
365
365
VR=4.5V
Icommon CP pin 91
mW
Vcc=5.0V
SWITCHING.CHARACTERISTICS ITA= 250CI
SYMBOL
CHARACTERISTICS
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
Vcc=5.0V. CL =15 pF
Fig.l
tpd-107& 07
Turn·Off Oelay Iclock to output)
13
ns
t pd-107&Q7)
Turn-On Delav {clock to output I
Turn-On Delay (Master reset to output)
22
ns
35
ns
Vcc=5.0V. CL =15pF
Fig. 2 & 3
Min. Clock Pulse Width
14
ns
Vcc=5.0V. CI=15 pF
Fig. 1
tpd IMRI
CP pw
MRpwICPH)
MRpwlCPLI
Min. Master Reset pulse width with clock high
15
ns
V cc 5.0V. CL =15 pF
Fig. 2
Min. Master Reset pulse width with clock low
28
ns
V cc =5.0V. CV 15pF
Fig.3
CP
_I 1- Milp.ICP"1
IlIR-----=--=--,U-- ---- ------ ----------=v-- --l I--=-::.F\-- - - --- --- - -- - --- - ------ ---- ~
..
1.5 V
tpd-IMRI
01
NOTE: OS, 01, ~O, are high. Other clock input is grounded.
Figure 2
3-359
1.5 V
ITT9328
MSI Dual 8-Bit Shift Register
CP
___I
~
MRpwlCPlI
.. -V-.--------=----------------=----------------,V----I r°7 --=F'""\-- ------- -------------~--- -
1.5 V
tpd-I"I
1.5 V
NOTE: OS,01, DO are high. Other Clock input is grounded.
Figure 3
APPLICATION:
DATA INPUTS
r~-----------A~--~-------C\
CLOCK
RESET
-------+---,----l-------+-----,-----t- - --
__
c:)
WRITE LI"E
----+---+------I--O-----+---- 40 ns
h, b = Release lime> 40 ns
Inpul to Pin 1 (2)
Pins 2, (1), 3 & 4 = 1
2. If a fixed value of Rx is used, the following
values are recommended: Rx = 30 kO for 0
to + 750C oporation; Rx = 10 kO for -55 to
+ 125°C operation.
COUT
_llpd'-~
r
Input 10 Pin 3 (4)
Pin 4 (3) = 1. Pins 1 or 2 = 0
(For Cx greater
Where Rx is in kO, Cx is in pF, T is in ns
For ex < 103 pF, see Figure 14
4. If electrolytic type capacitors are to be used,
the following two arrangements are recommended:
R < 0.6 Rx (Max)
~
0,: any silicon
R
type diode, such
as F0700
This circuit also amplifies Cx allowing
ex
01
for longer output pulse width.
R < Rx (0.7) (hr.Q,)
PIN 11 PIN 13
Rx (min) < Rx < Rx (max)
R
RX
H
8. The retrigger pulse width is calculated as
shown below:
:1
Q,: Any NPN silicon device with
sufficient hFE at low currents,
such as 2N2511
+
0:
tw = Ipw
C
-I x
comes within .32 RXCX ( ; ) ns after the initial trigger pulse.
x
1
LOGIC DIAGRAM
5. To obtain variable pulse width, by remote
trimming, the following circuit is recommended:
PIN 13
PIN 11
TO DEVICE
Vee = PIN 14
GND = PIN 7
_
R< Rx IMAXI -RX
eX
Rx
11
'§j)
2--()
3
.
4
>Rx IMINI
~---"'·---b
.l.. tL AS CLOSE AS POSSIBLE
T
o--J
+ ~~ ) + tpd+
Ipd+ = 0.32 RxCx (1
NOTE: Retriggerlng will not occur if the retrigger pulse
Where R is in kO, Cx is in pF, T is in ns
RX
+
The retrigger pulse width is equal to the pulse width Ipw pius
a delay time. For puise widths greater Ihan 500 ns, tw can be
approximated as tpw.
QI
Both circuits prevent reverse voltage across
Cx. The pulse width T for the circuits is
defined as follows:
T=0.36 RCx [1
L
1
.
Vee
13
8
9601
O/S
C>--6
0---------
Vec
3-362
ITT9601
Retriggerable Monostable Multivibrator TTL
ELECTRICAL CHARACTERISTICS (TA = -55°0 to 125°C, Ve e
SYMBOL
CHARACTERISTIC
-55°C
MIN. MAX.
VOH
Outpul High Voltage
VOL
Output Low Voltage
2.4
V,H
V,l
I,
Input High Voltage
Input Low Voltage
Input Load Current
I,
Ise
Inout Leakaae Current
Short Circuit Current
I,
t pd +
Quiescent Power SUooly Drain
Negative Trigger Input
to True Output
t",-
LIMITS
+2SoC
MIN.
TYP.
2.4
3.3
0.4
2.0
UNITS
+12S oC
MIN. MAX.
MAX.
2.4
0.2
0.4
1.1
0.90
1.!l
1.4
Volts
0.85 Volts
1.6 mA
60
p.A
mA
25
40
25
25
mA
ns
Negative Trigger Input
to Complement Output
25
40
ns
t",,",",
Minimum True Output
Pulse Width
45
65
ns
.ltp•
Pulse Width Variation
3.42
3.76
eSTRAY
R,
3.06
Maximum Allowable
Wiring Cap. (Pin 13)
Timing Resistor
TABLE II -
25
50
5.0
25
f--
VOH
Output High Voltage
Vee
Output Low Voltage
MAX.
2.4
2.4
0.45
0.2
! 1.6
Inout Leakaae Current
Short Circuit Current
Ir·d
Quiescent Power Supply Drain
t pd '
Negative Trigger Input
to True Output
25
40
t"
Negative Trigger Input
to Complement Output
25
40
Minimum True Output
Pulse Width
45
65
3.42
3.76
_.- ._.. .ltp •
CS1RIIY
R,
.85
-1.6
1.0
15
"-10
25
3.08
r--pujse Width Variation
5.0
50
0.85
1.6
!
0.85
1.6
60
-40
60
25
25
5.0
50
VC--J
1...
PIN I
.
b
R
TO OEVICE
'
R
Rx MAX - X
VCC 0 - - - - - - - - -
7. Under any operating condition, Cx and Rx
(min) must be kept as close to the circuit as
possible to minimize stray capacitance and
reduce noise pickup.
8. Input Trigger Pulse Rules. See Triggering
Truth Tables, page 5.
=
tl, t3
Min. Positive Input
Pulse Width >40 ns
t2, t4 = Min. Negative Input
Pulse Width >40 ns
1-
12 --1
1-11--1
INPUT 2.5V~---L2.5V ~
1.5V
OV
'
OV
-I
Ipd+
I-- Ipd+
QOUTPUT
1- ':-I
~V ~
Input to Pin 4 (121
Pin 5 (11) = High. Pin 3 (13)
=
High
- 13__
--l4-INPUT 2.5V ~. cu 2.5V ~
. -.J _ .. ~
OV '---..J
r-
21141
.---- tpd+
Cx
\--0 PIN
Q,
R RX (0.7) (hFE Q1) or <:2.5 MH whichever
RX (min)
Ry RX (max)
is the lesser
Q1: NPN silicon transistor with hFE requirements of
above equations, such as 2N5961 or 2N5962
t :::::::0.3 RCX
'IN914
Vee ~ PIN
t---'~
'---""W-+-l~r:"
0_,
Input to Pin 5 (111
Pin 4 (12) = Low
Pin 3 (13) = High
PIN 2(141
Cx
+ !-:-"PIN1(15)
R ';0.6 Ax IMAXI
C. Use to obtain extended pulse widths:
t :::::::0.3 RCX
Q~
11151
3-368
~V
_ _ _oJ
ITT9602
Dual Retriggerable Resettable Monostable Multivibrator
9. The retriggerable pulse width is calculated
as shown below:
tw
= tpw
+ tpd+
= 0.31
I. PUT
OUTPIIT
timing cycle can be terminated or any new
cycle inhibited until the low reset input is
removed. Trigger inputs will not produce
spikes in the output when the reset is held
low.
1
RxCx (1 + Rx ) + tpd+'
:
L
I~tw~'
~
LI_ _ _ _ _ _ _- I
RESET
The retrigger pulse width is equal to the
pulse width tpw plus a delay time. For pulse
widths greater than 500 ns, tw can be
approximated as tpw. Retriggering will not
occur if the retrigger pulse comes within
~ 0.3 Cx ns after the initial trigger pulse.
(i.e. during the discharge cycle).
---lI
I
Symbol
VOH
+125°C
Min. Max
2.4
2.4
2.4
VOL
VIH
VIL
IlL
Units
Limits
+25°C
Min •.TVp. Max.
2.0
IIH
Ise
IpO
tpd+
0.4
1.7
0.90
-1.1 -1.6
-1.24
-0.97-1.24
0.85
-1.6
-1.24
60
ConditiollS
(Note n
Volts
Vee = 4.5 V, IOH =-0.96 rnA (Note 2)
Volts
Vee = 4.5 V, IOL = 9.62 rnA (Note 2)
Vee = 5.5 V, IOL = 12.8 rnA
Volts
Volts
rnA
Guaranteed input high
Guaranteed input low
Vee = 5.5 V, VIN = 0.4 V
rnA
Vee = 4.5 V, VIN =0.4 V
Vee = 5.5 V, VIN = 4.5 V
Vee = 5.5 V, VOUT =1.0 V (Note 2)
Vee = 5.0 V
Vee =5.0 V, RX =5.0kil
ex = 0, eL = 15 pF
Il A
rnA
rnA
39
25
35
ns
29
43
ns
Vee = 5.0 V RX = 5.0 kil
ex = 0, eL = 15 pF
72
78
90
100
ns
ns
Vee = 5.0 V RX =5.0kil
ex = o. eL = 15 pF
3.08 3.42
3.76
50
25
Ils
Vee = 5.0 V, RX =10 kil. ex = 1000 pF
Pins 2and 14 to Ground
45
tpw(rnin)
50
25
QOUTPUT
60
-25
45
10
tpw
0.4
1.5
0.85
-1.6
tpd-
eSTRAY·
5.0
RX
3.3
0.2
r-LJ
=-55°C to 125°C, Vee =5 V ±10%)
-55°C
Min. Max.
0.4
I
r I11....;.Q_
OUTPUT
L-.J
_ _ _ _ _ __
11. Vee and Ground wiring should conform to
good high frequency standards so that
switching transients on Vee and Ground
leads do not cause interaction between
one-shots.
10. Reset Operatio'n - An overriding active
low level reset is provided on each oneshot. By applying a low to the reset, any
ELECTRICAL CHARACTERISTICS (TA
PULSE
WIDTH
-I-
5.0
45
5.0,
50
pF
25
kil
3-369
ITT9602
Dual Retriggerable Resettable Monostable Multivibrator
ELECTRICAL CHARACTERISTICS
Symbol
_OoC
Min. Max.
Limits
+25°C
Min. Typ. Max.
+75 OC
Min. Max
2.4
2.4
2.4
VOH
0.2
0.45
VOL
VIH
3.4
1.9
\ilL
0.85
IlL
-1.6
,
0.45
1.8
0.85
-1.0 -1.6
-1.41
10
IIH
Volts
VCC = 4.75 V, IOH =-0.96 rnA (Note 21
Volts
VCC = 4.75 V, IOL = 11.3 rnA (Note 21
VCC = 5.25 V, IOL = 12.8 rnA
Volts
Guaranteed input high
0.85
Volts
Guaranteed input low
-1.6
rnA
0.45
1.65
-1.41
-1.41 rnA
60
60
-35
ISC
52
IpO
tpd+
39
50
25
40
Conditions
(Note 11
Units
52
VCC = 5.25 V, VIN = 0.45 V
I VCC
= 4.75 V, VIN = 0.45 V
IlA
VCC = 5.25 V, VIN = 4.5 V
rnA
VCC = 5.25 V, VOUT = 1.0 V (Note 21
rnA
V CC = 5.0 V, Ground, Pins 1 and 2
ns
VCC = _5.0 V, RX = 5.0 kil
CX=O,CL=15pF
tpd-
29
48
ns
VCC= 5.0 V RX = 5.0 kil
Cx = 0, CL = 15 pF
tpw(rnin)
72
100
ns
Vee =5.0 V RX = 5.0 kil
110
ns
Cx = 0, CL = 15 pF
Us
VCC'= 5.0 V, RX =10 kil, Cx = 1000 pF
50
pF
Pins 2 and 14 to Ground
50
kil
78
tpw
3.08 3.42 3.76
50
CSTRAY
5.0
RX
50
50
5.0
50
5.0
1. Unless otherwise noted, 10k.Q:resistor placed between Pin 2 (14) and vee, for all tests. (RX)
2. Ground Pin 1 (15) for VOL on Pin 7 (9), or VOH on Pin 6 (10), or for Ise on Pin 6 (10); also, apply momentary ground to Pin
4 (12). Open Pin 1 (15) for VOL on Pin 6 (10), or for VOH on Pin 7 (9), or for Ise on Pin 7 (9).
TYPICAL ELECTRICAL CHARACTERISTICS
INPUT LOAD CURRENT
VERSUS INPUT VOLTAGE
INPUT LEAKAGE CURRENT
VERSUS INPUT VOLTAGE
0.5
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE (LOW STATE)
80
Vcc • 5.0 v
Jl25).t. rA
I
-0.5
T, •
·1.5
80
T, • 25 C
~55 C
~
..,:::; i==:====
~~
,yV
T,' ·55 C
. ,to
40
1
10
fA' 125 C
TA ' 125 C
'J.5
.1.5
I
'0.5
0
0.5
INPUT VOLTAGE· VOlTS.
1.5
1.5
7'".,,( .
'0
fA' 25 C
'1.5
1.1
1-~~fpU~·Ol~W"
VCC ·5.0V
o
0
r..
~
re- V
4.0
I NPLn VOLTAG( • VOLTS
3-370
0.0
TIA .
·~s c_ f---'
R
-
'f( '~I
V k-'""
,......
0
2.0
o
6.0
4.0
'25
-75
0
75
25
0
·75
125
MINIMUM TIME DELAY,
RESET TO OUTPUT VERSUS
AMBIENT TEMPERATURE
NORMALIZED OUTPUT PULSE
WIDTH VERSUS SUPPLY VOLTAGE
VCC • 5.0V -~--+--+----i-+---i
Cl '15 pf
RX' 10.0
Cx • lolpf
/
vec ·\.OV
Rx -IOtO
10
13 - 6
'" "'
9' ........
-.-~
-
ex'
~ 1.05
~
./
131+.196 0 .113
.19·8","3
0
·25
0
25
75
125
-- --
-........
5.5 V
Vee' S' OV
70
-7\
-2\
I
VCC·4.~V
25
--
-7\
TA ' AM81[NT1(MP(RATUR[· C
125
V
i
~IO
t--
V
I
V
-
./V
125
2
10
20
50
t.O
lO
RX - EXTERNAL TIMING RESISTOR -
n
MmlMUM OUTPUT PULSE
WIDTH VERSUS
AMBIENT TEMPERATURE
1«1
TA ' 25'e
Rx '!OkO
Cx 'IOJpf
Vee'
125
"c
/
'"
c
1.10
I~
15
Vcc • 5.0V
t-cx '103:>1
r-
NORMALIZED OUTPUT
PULSE WIDTH VERSUS
SUPPLY VOLTAGE
Rx • IOkO
50
103 pf
25
0
25
75
TA AMBIENT TEMPERATURE - ·c
7\
POWER DISSIPATION VERSUS
AMBIENT TEMPERATURE'
PINI • PIN2 ' 0
25
/
TA - AMBIENT TEMPERATURE"C
IlO
0
-
!9.1.
10
.0;0
'25
-
PULSE WIDTH VERSUS
TIMING RESISTOR'
t-+--+-t-+--+-+---+--+
0
..-
18
-+---+--+-+--+----i ;:
lO
;'
PL'ts.::
loA - AA'.BIENT TEMPERATURE -
l. I
40
-25
lA - AMBIENT TEMPERATURE - ~c
OUTPUT VOLTAGE - VOLTS
~
r- ~~~ f-""" V
POSITIvE
1
II
-25
-2.0
Vee' 5,0'.1
e l '1\ pf
Rx "IOlO
ex '103:>1
g30
~
TRIGGER UEilSUS
AMBIENT TEI'.1PERATURE
(NEGATIVE EDGE TRIGGER INPUT)
Vce' 5.0V
Cl "15 pf
Rx • IOtO
Cx 'Iolpf
VCIC '
v
OUTPUT "HI Gif'
5.0
•
p.mm.mr.1 PULSE wlDm YO
MINIMUM PULSE WIDTH TO
TRIGGER VERSUS
AMBIENT TEMPERATURE
(POSITIVE EDGE TRIGGER INPUT)
Vee· S' Ov
IJ0 - Rx'SkC'
./
I.U;
,/'
V-
4.S
Cl '15:>1
--
I
/
COMPl[t.iENTARY OUTPUT /
80
0
O.lO
•• 0
Cx • 0
1111
V
I--""
-;-
II0
./
1.111
120
S.D
~
s.s
VCe" SUPPLY VOLTAGE -VOLTS
3-371
• 6.0
10
-7\
-2!I
0
2S
U j.....-TRUjOUTT75
TA - AMBIENT TEMPERATURE'
-
I~
e
ITT9602·
Dual Retriggerable Resettable Monostable Multivibrator
OUTPUT PULSE WIDTH VERSUS TIMING
RESISTANCE AND CAPACITANCE FOR
CX<103 pF
NEGATIVE TRIGGER DELAY
TIME VERSUS
AMBIENT TEMPERATURE
/v
40
k-- I-TRUE OUTPU
lpel
o rVcc
RX
r
0
'75
V
--
I~ COMPLEMEN
OUTPUT
For Cx
-
~
M
c
• SkQ
103
...
I
:I:
I-
1
0
0
+.....!...j
Rx
~
q..+~",<::>... ,
• 5.OV
·25
RxCx (1
-'
Cx • 0
CL '15p[
'I
~ 103 pF, tpw = 0.31
25
15
.
~
125
TA -AMBIENT TEIoFERATURE -'C
'en
-'
a..
::l
a..
::l
0
~
..... ~ ~
~
~
./
----
I-
10 2
80
60
"..".,
~
/
V ~I;
~
<::>...v~/ ~
~ 't ....
q..+ ...
v
~II
~
,<::> - '
....
-
::l
I-
.JIll' ~
~ q..+
V
1....
~~7
",... ~
-.
~+
~
~
40
20
10
1
2
4
6 810
Cx - TIMING CAPACITANCE - pF
LOADING RULES
TTuL INPUT LOAD AND DRIVE FACTORS
TRIGGERING TRUTH TABLES
LOAD
5(11 )
INPUTS
3,4,5,11,12,13
HIGH
LOW
1 U.L
1 U.L.
PIN NO'S.
4(12)
3(13)
Operation
H->L
L
H
Trigger
H
L-.H
H
Trigger
X
X
L
Reset
DRIVE FACTOR
OUTPUTS
6,7,9,10
HIGH
LOW
16U.L
8U.L.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
H-L = HIGH to LOW Voltage Level transition
L-H = LOW to HIGH Voltage Level transition
1 U.L. = 1 TTL Gate Input Load
3-372
ITT9602
Dual Retriggerable Resettable Monostable Multivibrator
SWITCHING CIRCUITS AND WAVEFORMS
iNPUT PULSE
1--.-40II::j
u.
IW~I
f"'100kHz
Amp",3.0V
Width", 40 ns
tr = tf ::; 10 ns
~::_l1r--:~-----,.-l~
'\ F
Vee" Pin 16
GNO" Pin 8
APPLICATIONS
vee
Vee
eXt
eXt
RX'
exi
t5
.
tN~
RX2
Vee
ouTPUT
OUT
9602
9602
0/51
!!GOO
9602
Ol51
eX2
..
.0
-
Rx.
vee
")(2
O-S2
0-S2
5
'3
IN~
OUTPUT~
1-"-1
--'rL
12l=!-'1~
OuT _ _ _ _
'2..,-1
The first one-shot determines the time t1 before
the initiation of the output pulse. The second
one-shot determines t2 the output pulse width.
PULSE GENERATOR
The output frequency produced with the above
configuration is determined by CX1 and RX1 I
while the pulse width is determined by CX2 and
RX2. 0/5 1 forms an astable multivibrator with
an output pulse width of approximately 25 ns,
while 01 S _2 extends the pulse width to the
required value.
3-373
ITT
.....
----DTLDUAL FOUR-INPUT GATE
FAST DTL DUAL FOUR-INPUT GATE
ITT930
ITT961
Package:. Dual In~Line and Flat Pack
SEMICONDUCTORS
DTl DUAL
FOUR-INPUT ·GATE
fAST DTl DUAL
fOUR-I·NPUT GATE
The ITT930 and ITT961 elements are
four-input NAND/NOR gates.
dual
In addition to performing the positive NAND and
negative NOR logic functions. the gates can be
cross-coupled to form a flip-flop or the outputs can
be tied together to perform the "wired OR"
function. Both gate inputs may be extended using
ITT933 elements to allow increased fan-in.
The ITT930 im;orporates a 6K output pull-up
resistor which allows for a fan-out of up to 8 DTL
loads.
The ITT961 incorporates a 2 K output pull-up
resistor which typically results in a 30% faster rise
time with capacitive loads at a fan-out of up to 7
DTL loads.
CIRCUIT SCHEMATIC
A o-II vee
7
'F=':;'-I>I-o c 112
C2 11
4-17
NOTES:
Pins 1. B. 13 not used
945. R, = 6K
948. R, = 2K
ITT945, ITT948
CLOCKED FLIP-FLOPS
SYNCHRONOUS ENTRY
3
4
11
0
0
cp
cp
0
cp
cp
0
cp
1
1
1
tn + 1
5
10
6
0
6
1
1
0
0
1
0
1
0
NC
1
0
1
NC
0
1
1
12
POSITIVE LOGIC SYMBOLS
ASYNCHRONOUS ENTRY
Inputs
Outputs
Output
Inputs
tn
cp
NC
cp
0
NC
cp
NC
0
0
cp
0
0
NC
cp
1
1
0
1
0
1
0
cp
1
1
0
0
1
1
= immaterial. either 1 or 0 has no effect on outputs:
ELECTRICAL CHARACTERISTICS ITT945-1.ITT948-1(TA = -55°Cto +125°C. VCC = 5.0V±10%)
-66°C
Min.
Max
Symbol
Characteristic
VO H
Output High Voltage
945
948
VOL
2.6
2.5
Output low Voltage
945
948
Min.
Limits
+26°C
Typ. Max.
2.5
2.5
+126°C
Min.
Max. Units Conditions and Comments
Volts
2.5
2.5
0.4
0.4
0.4
0.4
0.4
0.4
Volts
= 4.5V.IOH = -180 pA
= 4.5V.IOH = -540 jJA
VCC = 4.5V. 10l = 12.0 mA
VCC = 5.5V. 10L = 15.0 mA
VCC = 4.5V.IOl = 13.0 mA
VCC
VCC
(at -55°C)
=
VIH
Input High Voltage
VIL
Input Low Voltage
IA
2.1
1.9
1.4
=
13.6 rnA
VCC
5.5V.IOl
Volts Guaranteed input high threshold
for aII inputs
1.7
1.1
0.8
Volts
Input Leakage. all J.K
S,C,SO.CO. inputs
2.0
5.0
jJA
VCC
5.5V. VA
4.0V
Gnd on other inputs
I ACP
Input Leakage. CP inputs
10
20
jJA
VCC 4.0V. VA
4.0V
Gnd on other inputs
IF
Input Current. all
J.K.S.C inputs
Input Current. 945
CP inputs
948
-.98
-.98
-.92
rnA
VCC
5.5V. VF 0.4V
4.0V on other inputs
-2.93
-2.35
-2.93
-2.35
-2.57
-2.03
-0.76
-0.62 -0.76
-0.72 rnA
VCC 4.5V. VF 0.4V
4.0V on other inputs
-2.26
-1.83
2.93
-2.26
-2.26
-1.83
2.93
-2.26
IF
Input Current. all
J.K.S.C inputs
Input Current. 945
CP inputs
948
I FSI
Input Current. CO.
So inputs
IpO
VCC Current
945
948
t pd +
Turn Off Delay
tpd-
Turn On Delay
945
948
945
948
35
30
30
30
-2.02
-1.59
-2.57 rnA
-2.20
Guaranteed input low threshold
for all inputs
=
=
=
=
=
=
=
=
=
VCC
5.5V.!vF = 0.4V
VCC = 4.5V:14.0V on other inputs
= 5.0V. all inputs <;len
14.0
16.2
rnA
VCC
75
65
75
75
ns
VCC - 5.0V
AL = 2.0K. CL
30pf
AL = 330 n. CL = 50p!
4-18
=
ns
ITT945, ITT948
CLOCKED FLIP-FLOPS
ELECTRICAL CHARACTERISTICS ITT945-5.ITT948-5 (TA
Symbol
Characteristic
-55°C
Min. Max.
V OH
Output High Voltage 945
948
2.6
4.3
VOL
Output Low Voltage
945
948
= aoe to +75°e. Vee = 5.av ±5%)
Limits
+25°C
Min. Typ. Max.
+125°C
Min.
Max. 'Units Conditions anti Comments
2.6
4.3
2.5
4.2
0.45
0.45
Volts
0.45
0.45
Volts
0.5
0.5
V IH
Input High Voltage
VIL
Input Low Voltage
1.4
1.1
IR
Input L:eakage. all
J·K S. C. SO. Co inputs
5.0
I RCP
Input Leakage.
CP inputs
IF
VCC = 5.0V.IOH = -120)JA
VCC = 5.0V.lOH = -120)JA
VCC
VCC
VCC
VCC
=
=
=
5.0V.IOL 5.0V.IOL =
5.0V.IOL =
5.0V.IOL =
16.8 rnA
16.0 rnA
15.4 mA
14.6 rnA
Volts
Guaranteed input high threshold
for all inputs
0.8
Volts
Guaranteed input low threshold
lor aII inputs
5.0
10.(
M
VCC = 5.0V. VR = 4.0V
Gnd on other inputs
10.0
10.0
20.(
JlA
VCC = 4.0V. VR = 4.0V
GNO on other inputs
Input Current. all
J.K.S.C inputs
Input Current. CP Inputs
945
948
-0.95
-0.95
-2.8
-2.24.
-2.8
-2.24
-2.66
IFSI
Input Current. CO. So input
-2.8
-2.8
-2.66 mA
IpO
VCC Current
Icex
Output Leakage Current
ISC
Output Short Circuit Current
945
0.59
948
1.77
IMAX
2.1
1.9
1.7
-0.90 mA
I
-21~
15.0
17.5
945
948
100.0
1.41
4.2
0.59
1.77
1.41
4.2
VCC = 5.0V. VF = 0.4V
4.0V on other inputs
0.55
1.6
mA
VCC = 5.0V.lnputs Open
)JA
VCC = Veex = 5.0V
1.38 rnA
4.0
VCC = 5.0V
VOUT = GNO
VCC = 8.0 . All inputs GNO
Maximum VCC Current
945
948
17.0
17.5
rnA
tpd+
Turn Off Delay
945
948
35
30
75
65
ns
VCC'= 5.0V
RL = 2.0K. CL = 30pf
tpd-
Turn On Delay
945
948
30
30
75
ns
RL = 330 n. CL = 50p!
75
tpd TEST CIRCUIT
+3V
r--I
' - - - - - +0.4V
I
~.::TL @VIN........,!f--~
PULSE
WIDTH
>IOOns
I
I
I
L __
c a
K
-t- __
I;:,r
I
---+I.SV
VOUT
---'---~~===-
I
...J
Your
4-19
--JdS:
GND
GND
mm
QUAD TWO-INPUT GATE ITT946
SEMICONDUCTORS
Package: Dual I.n-Llne and Flat Pack
.....I
-L-L _____..,.;.._FA_S_T_Q_U_A....D_TW_O_-IIIIIIIN_P_U_T G_A_T_E......ITT
.....9_4_9
IIIIII
QUAD TWO-INPUT
GATE
FAST QUAD
TWO-INPUT GATE
Pinout: Dual In·Line and Flat Pack
The ITT946 and ITT949 elements are quad
two-input NAND/NOR lIates.
In addition to performing the positive NAND and
negative NO R logic functions.· the gates can be
cross-coupled to form a flip-flop or ~he outputs can
be tied together to perform the "wired OR"
function.
CIRCUIT SCHEMATIC
(ONE GATE ONLY)
These quad two-input gates can also be wired to
perform the "exclusive OR" function. while two
elements can be wired together to form a full adder.
The ITT946 incorporates a 6K output pull-up
resistor which allows for a fan-out of up to 8 DTL
loads.
The ITT949 incorporates a 2 K output pull-up
resistor which allows for typically 30% faster rise
time with capacitive loads at a fan-out of up to 7
DTLloads.
TYPICAL
RESISTOR
VALUES
ABSOLUTE MAXIMUM RATINGS 1
Characteristics
Units
Supply Voltage (VCe). -55°C to +125°C.
Continuous ....................................... -.5 to +8 Volts
Supply Voltage (VCe). Pulsed.<1 sec ..... + 12 Volts
Output Current. Into Outputs ........................... 30 mA
Input Forward Current ................................... -1 0 mA
Input Reverse Current .......................................... 1 mA
Operating Temperature ................... -55 to + 125°C
Storage Temperature ...................... -65 to + 150°C
Operating Junction Temperature 2 ............... + 175°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering. 60 sec.) ....................... 300 o F
Vcc·
R1 =2.0 K
R2=1.75K
R3=5.0 i<
R4=6.0 K (946)
R4=2.0K (949)
NOTES:
1. Above· which useful life may be impaired.
2. Allow 300·C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50·C/Watt
OJ - C for TO-5; 180· C/Watt OJ - C for 114"
X 1/4" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachmel'1t and thermal paths .thru leads, as
well as number of soldered leads.
4 -20
ITT946 QUAD TWO-INPUT GATE
ITT949 FAST QUAD TWO-INPUT GATE
= -55°eto +125 oe. Vee = 5.0V ±10%)
ELECTRICAL CHARACTERISTICS ITT946-1 (T A
-66°C
Min. Max.
Symbol
Characteristic
VO H
Output High Voltage 2.5
Limits
+26°C
Typ.
Max.
Min.
2.6
+126°C
Min. Max. Units Conditions and Comments
3.5
2.5
Volts
Vec = 4.5V. 10H = -O.lS rnA
Inputs at VI L (See Selow)
VOL
Output Low Voltage
0.4
0.25
0.4
0.4 Volts
Vce = 4.5V.I OL = 12 rnA
Vee = 5.5V.IOL = 1.5 rnA
Inputs at VIH (See Selow)
V IH
Input High Voltage
VIL
Input Low Voltage
IF
Input Load Current
2.1
1.9
1.4
1. I
-1.5
-1.2
-1.16
IR
1.7
O.S
Volts
Guaranteed Input High Threshold
For All Inputs
Volts
Guaranteed Input Low Threshold
For All Inputs
-1.5
-1.4 rnA
-0.93 -1.16
-1.0S rnA
Input Leakage Current
2.0
5.0
p.A. Vee = 5.5V. VR= 4.0V
I
Ground on other inputs
IpD
Vec Current "'Gate On"'
(per gate) Vee Current "'Gate Olr"
lpd+
Turn Off Delay
tpd-
Turn On Delay
S.5~:1
Vee =
VF = 0.4V
Vee = 4.5V. 4.0V on other inputs
2.41
1.15
3.25
1.47
rnA
rnA
45
20
BO
30
ns
ns
25
10
Inputs Open Vce = 5.0V
Inputs Grounded
Vce = 5V. RL = 3.9K. CL - 30pf
Vee = 5V. RL = 400
CL= 50p
ELECTRICAL CHARACTERISTICS ITT946-5 (T A = ooe to +75°e. Vee = 5.0V ±5%)
Symbol
Characteristics
Min.
VOH
Output High Voltage
2.6
VOL
Output Low Voltage
Max.
LIMITS
+26°C
MinTyp. Max.
2.6
0.45
+76°C
Min.
Max.Units Conditions and Comments
2.5
IVa Its Vce = 5.0V.IOH = -12 rnA
0.45
Volts
Vce = 5.0V.IOL = 12 rnA
Vee = 5.0V. 10L = 11.4 rnA
IVa Its
Guaranteed Input High
Threshold For All Inputs
0.50
VIH
Input High Voltage
VIL
Input Low Voltage
1.2
1.1
0.95 1V0its 'Guaranteed Input Low
Threshold For All Inputs
IF
Input Load Current
1.4
1.4
rnA
1.33 rnA
VF = 0.4sv.lvec = 5.0V
V F = 0.5V. 4.0V On Other Inputs
IR
Input Leakage Current
5.0
5.0
10.0
Vee = 5.0V. VR = 4.0V
Gnd On Other Inputs
Ise
Output Shan Circuit
2.0
0.61
1.9
1.30
0.61
1.B
1.30
0.535
Il A
1.25 rnA
Current
ICEX
VOUT = Gnd
Output Leakage Current
Power Drain Current
IpD
(Per Gate)
I MAX
Max Vec Current
(Per Gate)
tpd+
tpd-
Turn Off Delay
Turn On Delay
'Vee = 5.0V
25
10
100
JlA
Vec = VCEX = 5.0V
4.0
rnA
Vee = S.OV Inputs Open
4.0
rnA
VCC = B.OV Inputs Gnd
SO
30
ns
ns
Vec = SV. RL = 3.9K. CL = 30pl
Vee = 5V. RL = 400
CL= SOp
4-21
QUAD TWO-INPUT GATE ITT946
FAST QUAD TWO-INPUT GATE ITT949
ELECTRICAL CHARACTERISTICS ITT949-1 (TA = -55°eto +125°e. Vee = 5.0V ±10%)
-S5 0 C
Min. Max.
Symbol
Characteristic
vOH
Output High Voltagel 2.5
Min.
Limits
+25 0 C
Typ.
Max.
2.6
3.5
+125°C
Min. Max. Units Conditions and Comments
2.5
Volts
VCC = 4.5V. 10H = -0.54 mA
Inputs at VIL'(See Below)
VOL
0.4
Output Low Voltage
0.27
0.4
0.4 Volts
VCC = 4.5V. 10L = 10.8 rnA
VCC = 5.5V.IOL = 13.5 rnA
Inputs at V,H (See Below)
V,H
Input High Voltage
V,L
Input Low Voltage
IF
Input Load Current
1.9
2.1
1.1
1.4
-1.2
-1.5
-1.16
IR
1.7
-1.5
qlf'
tpd+
tpd-
Turn Off Delay
Turn On Delay
Output High Voltage
VOL
Output Low Voltage
A
5.0
Inputs Open VCC = 5.0V
Inputs Grounded
35
20
50
30
ns
ns
VCC = 5v~'RL;'; 3.9K. CL = 30pf
VCC = 5V. AL = 400
CL = 50pf
= OOeto +75°e. Vee = 5.0V ±5%)
~olts
VCC = 5.0V.IOH = -12 rnA
~olts
VCC = 5.0V.IOL = 10.5 rnA
VCC = 5.0V.IOL = 10.2 mA
~olts
Guaranteed Input High
Threshold For Allloput:;.
0.95 ~olts
Guaranteed Input Low
. Ttlrelllloid .For All Inputs
4.2
0.5
0.5
0.55
V,H
Input High Voltage
VIL
Input Low Voltage
1.2
1.1
'F
Input Load Current
1.4
1.4
IR
Input Leakage Current
ISC
Output Short Circuit
1.8
1.9
..
rnA
1.33
5.0
5.0
1.85
10.0 JIA
Max VCC Current
IMAX
(Per Gate)
Turn Off O~lav
Tum On Dalay
VCC= 5.0V. VR = 4.OV
Gnd On Other Inputs
rnA
VCC = 5.0V
100
pA
VCC = VCEX.= 5.0V
5.9
rnA
VCC = 5.0V Inputs Open
2.86
rnA
VCC = B.OV Inputs Gnd
VOUT = Gnd
Output Leakage Current
Power Drain Current
IpD
(Per Gate)
Ipd+
Ipd-
VF = 0.45Vlvcc = 5.0V
VF = 0.5\1 4.0V on other inputs
3.68
Current
'CEX
VCC.= 5.5V. VR= 4.0V
Ground on other inputs
rnA
rnA
4.3
2;0
VCC = 5.5V. V F = 0.4V
VCC = 4.5V. 4.0Von other inputs
5.45
1.47
10
10
4.3
Guaranteed Input Low Threshold
For All Inputs
4.05
1.15
ELECTRICAL CHARACTERISTICS ITT949-5 (TA
VOH
0.8 Volts
-1.08 rnA
2.0
VCC Current "Gate On"
'pD
(per gate) VCC Current "Gate
Guaranteed Input High Threshold
For All Inputs
-1.4 rnA
-0.93 -1.16
Input Leakage currer
Volts
25
10
50
30
4-22
I
I
ns
ns
Vce - sv. Ri. = 3.9K. CL - 30Pf
VCC = 5V. Rt= 400
CL= 50pf
-
ITT
---------
TRIPLETHREE-INPUTGATE ITT962
FAST TRIPLE TH REE-INPUT GATE ITT963
Package: Dual In-Line and Flat Pack
SEMICONDUCTORS
TRIPLE THREE-INPUT
GATE
FAST TRIPLE
THREE-INPUT GATE
Pinout: Dual In-Line and Flat Pack
The ITT962 and ITT963 elements are triple
three-input NAND/NOR gates.
In addition to performing the positive NAND and
negative NOR logic functions. the gates can be
cross-coupled to form a flip-flop or the outputs can
be tied together to perform the "wired OR"
function.
CIRCUIT SCHEMATIC
(ONE GATE ONLY)
r------,-----..-o vee
These triple three!input gates can also be wired
together to perform the "exclusive 0 R" function.
The ITT962 incorporates a 6K output, pull-up
resistor which allows for a fan-out of up to 8 DTL
loads.
E
The ITT963 incorporates a 2K output pull-up
resistor which typically results in a 30% faster rise
time with capacitive loads at a fan-out of up to 7
DTL loads.
A
B
c
'----<1>--0 GND
ABSOLUTE MAXIMUM RATINGS
Characteristics
TYPICAL
RESISTOR
VALUES
1
Units
Supply Voltage (VCe!. -55°C to + 125°C.
Continuous .................................... -.5 to +8.0 Volts
Supply Voltage (VCe!. Pulsed.<1.0 sec .. + 12 Volts
Output Current. Into Outputs ............................ 30 mA
Input Forward Current ................................... -1 0 mA
Input Reverse Current ................ :......................... 1 mA
Operating Temperature ................... -55 to + 125°C
Storage Temperature ...................... -65 to + 150°C
Operating Junction Temperature 2 ............... + 175°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering. 60 sec.) ....................... 300° F
R1 =2.0K
R2 =1.75 K
R3 =5.0 K
(962)
R4=6.0 K
(963)
R4 =2.0 K
NOTES:
1. Ab<:lve which useful life maybe impaired.
2. Allow 300°C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50° C/Watt
OJ- c for TO-5; 180°C/Watt OJ- C for 1/4"
x1/4" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
4-23
ITT962
ITT963
TRIPLE THREE-INPUT GATE
FAST TRIPLE THREE-INPUT GATE
ELECTRICAL CHARACTERISTICS ITT962-~ (TA =.-55°eto +125°e. Vee = 5.0V ±10%)
-55°C
Min. Max.
Symbol
Characteristic
VOH
Output High Voltage
V OL
Output Low Volt"ge
V IH
Input High Voltage
VIL
Input Low Voltage
1.4
F
Input Load Current
-1.5
-1.16
IR
2.5
Min.
2.6
0.4
2.1
pd+
3.5
0.25
+125°C
Min.
Max.
Units Conditions and Comments
2.5
Volts
Vce= 4.5V.IOH = -O.lBmA
Inputs at VI L (See Below)
Volls
VCC = 4.5V.IO L = 12 rnA
VCC = 5.5V. 10L = 15 rnA
Inputs at VI H (See Below!
Volts
Guaranteed Input High Threshold
For All Inputs
O.B
Volts
Guaranteed Input Low Threshold
For All Inputs
-1.4
-LOB
rnA
rnA
5.0
pA
Vec = 5.5V. VR= 4.0V
Ground on other inputs
0.4
0.4
~
1.9
.7
1.1
-1.2 -1.5
-0.93 -1.16
2.0
Input Leakage Current
IpD
VCC Current "Gate On"
(per gate) VCC Current "Gate Off'
pd-
limits
+25°C
Typ.
Max.
Turn Off Delay
Turn On Delay
25
10
Vec = 5.5V:1 VF = 0.4V
Vce = 4.5V. 4.0V on other inputs
2.41
1.15
3.25
1.47
rnA
rnA
Inputs Open VCC = 5.0V
Inputs Grounded
45
20
BO
30
ns
ns
VCC = 5V. RL = 3.9K. CL = 30pf
VCC = SV. RL = 400
.CL = SOp
ELECTRICAL CHARACTERISTICS ITT962-6 (TA = O°C to +75°C. VCC = 5.0V ±5%)
Characteristics
OOC
Min. Max.
Min.
V OH
Output High Voltage
2.6
2.6
VOL
Output Low Voltage
Symbol
LIMITS
+25 0 C
TVp.
Max.
+76 0 C
Min.
Max_
Units Conditions & Comments
2.5
0.45
0.45
Volts
VCC = 5.0V.IOH = -0.12 rnA
Volts
VCC = 5.0V.IOL = 12 rnA
VCC = 5.0V.IOl = 11.4 rnA
Volts
Guaranteed Input High
Threshold For All Inputs
Volts
Guaranteed Input Low
Threshold For All Inputs
0.50
V IH
Input High Voltage
V IL
Input Low Voltage
2.0
1.B
1.9
1.2
0.95
1.1
..
IF
IA
ISC
1.4
Input Load Current
Input Leakage Current
Output Short CircDit
1.4
5.0
0.61
1.30
5.0
0.61
1.30
0.535
1.33
rnA
rnA
VF = 0.45V -j:!CC = 5.0V
V F = 0.5V. 4.0V On Oth~r Inputs
10.0
pA
VCCC= 5.0V. VA = 4.0V
Gnd On Other Inputs
1.25
rnA
VCC= 5.0V
VOUT = Gnd
Current
ICEX
Output Leakage Current
Power Drain Current
IpC
(Per Gate}
Max VCC Current
IMAX
(Per Gate)
tpd+
tpd-
Turn Off Delay
Turn On Delay
25
10
45
20
100
pA
VCC = VCEX = 5.0V
4.0
rnA
VCC = 5.0Vlnputs Open
4.0
rnA
Vce = B.OV Inputs Gnd
BO
30
ns
ns
VCC = 5V. AL = 3.9K. CL = 30pf
VCC ~ 5V. RL = 400 .CL = 50p
4-24
TRIPLE TH REE-INPUT GATE ITT962
FAST TRIPLE TH REE-INPUT GATE ITT963
ELECTRICAL .CHARACTERISTICS ITT963·1 (TA = -55°C to + 125°C. VCC = 5.0V ± 10%)
Symbol
Characteristic
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
IF
Input Load Current
IR
Input Leakage Current
-56°C
Min. Max.
2.5
Min.
2.6
0.4
2.1
tpd+
0.4
1.9
0.4
1.1
-1.5
-1.16
-1.2 -1.5
-0.93 -1.16
2.0
Turn Off Delay
Turn On Delay
10
10
Units Conditions and Comments
Volts
1.7
1.4
1
+126°C
Min.
Max.
2.5
3.5
0.27
VCC Current "Gate On"
IpD
Iper gate) VCC Current "Gate Off'
tpd-
Limits
+26°C
Typ.
Max.
Volts
VCC = 4.5V.IOH = -0.54 mA
Inputs at VI L (See Below)
VCC=4.5V.I OL = 10.BmA
. VCC = 5.5V.IOL = 13.5 mA
Inputs at VIH (See Below)
Volts
Guaranteed Input High Threshold
For All Inputs
0.8
Volts
Guaranteed Input Low Threshold
For All Inputs
-1.4
-1.08
rnA
rnA
VCC =
VF = OAV
VCC = 4.5V. 4.0V on other inputs
5.0
pA
VCC = 5.5V. VR= 4.0V
Ground on other inputs
5.5~:1
4.05
1.15
5.45
1.47
rnA
rnA
Inputs Open VCC= 5.0V
Inputs Grounded
35
20
50
30
ns
ns
Vee = 5V. Rl = 3.9K. el = 3
Vee = 5V. Rl = 400 .el = 50,
ELECTRICAL CHARACTERISTICS ITT963·5 (TA = OOCto +75°C. VCC = 5.OV ±5%)
Symbol
Characteristics
OoC
Min.
Max.
VOH
Output High Voltage
4.3
VOL
Output Low Voltage
Min.
4.3
LIMITS
+26 0 C
Typ.
Max.
+750 C
Min.
Max.
0.5
Units Conditions and Comments
Volts
VCC = 5.0V.IOH = -0.12 rnA
Volts
VCC = 5.0V.IOl = 10.5 rnA
VCC = 5.0V.IOL = 10.2 rnA
Volts
Guaranteed Input High
Threshold For All Inputs
0.95
Volts
Guaranteed Input Low
Threshold For All Inputs
1.33
rnA
rnA
VF = OA5V.lvcc = 5.0V
VF = 0.5V ·14.0V on other inputs
10.0
jJA
VCC= 5.0V. V R = 4.0V
Gnd On Other Inputs
rnA
VCC = 5.0V
VOUT = Gnd
100
jJA
VCC = VCEX = 5.0V
5.9
rnA
VCC = 5.0V Inputs Open
2.86
rnA
VCC = B.OV Inputs Gnd
50
30
ns
ns
Vec = 5V. RL = 39K. eL = 30pl
Vec = 5V. RL = 400
.eL = 50p
4.2
0.5
iO.55
VIH
Input High Voltage
V IL
Input Low Voltage
1.2
1.1
IF
Input Load Current
1.4
1.4
IR
ISC
Input Leakage Current
Output Short Circuit
2.0
1.9
1.8
5.0
5.0
1.85
3.68
Current
ICEX
Output leakage Current
IpO
Power Drain Current
(Per Gate)
I MAX
Max VCC Current
(Per Gate)
tpd+
tpd-
Turn Off Delay
Turn On Delay
10
10
35
20
4-25
.
ITT1800
_ITT _________~DIlliT~L-D-U~A~L~F~I""'!""!"VE_IN_P~U~T~G~A~T-.-E
SEMICONDUCTORS
Package: Dual In-Line and Flat Pack
DTL DUAL FIVE
INPUT GATE
The ITT1800 is a dual five input NAND/NOR gate.
The device is similar to the ITT930 in all respects,
except for the replacement of the expander node
with a standard input diode.
Pinout: Dual In-Line and Flat Pack
ABSOLUTE MAXIMUM RATINGS'
Characteristics
Units
Supply Voltage (VCC). -55°C to
+ 125°C. Continuous ............................... -5 to +8 Volts
Supply Voltage (VCe). Pulsed.< 1 ..................... + i 2 Volts
Output Current. Into Outputs ..................................... 30 mA
CIRCUIT SCHEMATIC
Input Forward Current ............................................. -10 mA
A 0-+::1-'''"-1:.
Input Reverse Current .................................................... 1 mA
..;r""I>!---<>
A--riCl-'
H
I
Operating Temperature ............................ -55 to +125 °c
B
C
Storage Temperature ............................... -65 to + 150°C
o
,K
Operating Junction Temperature 2 ........................ + 175°C
E
L
J
Input Voltage Applied to Input.. .......... -1.5 to +5.5 Volts
Lead Temperature (soldering •. 60 sec....................... 300 ° F
TYPICAL
RESISTOR
VALUES
NOTES:
1. Above which useful life may be impaired.
2. Allow 300·e/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50·e/Watt
OJ-C for TO-5; lBO·e/Watt OJ-C for 1/4"
x 1/4" flat pack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
4-26
R,=2.0K
R2= 1.75 K
R3 =5.0 K
R4=6.0 K
ITT1800
DTL DUAL FIVE INPUT Gate
ELECTRICAL CHARACTERISTICS ITT1800-1 (TA = -55°eto +125°e, Vee =5.0V ±10%)
Symbol
V OH
Min.
Characteristic
.
Output High Voltage
I
i
Max.
2.5
Limits
+25°C
Min. Typ. Max.
Min.
Max. Units
Volts
2.5
2.6
Conditions and Comments
VCC = 4.5V. 10H = -0.18 mA
Inputs at VI L (See Belowl
VOL
0.4
Output Low Voltage
0.4
0.4
Volts
VCC = 4.5V. 10L = 12 mA
VCC = 5.5V.IOL = 15 mA
Inputs at V IH (See Belowl
V IH
Input High Voltage
V IL
Input Low Voltage
IF
Input Load Current
IR
2.1
1.9
1.4
1.7
O.B
1.1
Volts
Guaranteed Input High Threshold
For All Inputs
Volts
Guaranteed Input Low Threshold
For All Inputs
-1.5
-1.5
-1.4 mA
-1.16
-1.16
-1.0B mA
Input Leakage Current
2.0
5.0
,
p.A
VCC = 5.5V. VR= 4.0V
Ground on other inputs
rnA
Inputs Open
VCC = 5.0V
Inputs Grounded
1
VCC Current "Gate On"
IpD
(per gate) VCC Current "Gate Off"
3.25
1.47
VCC = 5.5V:1 VF = O.4V
VCC = 4.5V. 4.0V on other inputs
mA
tpd+
Turn Off Delay
25
80
ns
tpd-
Turn On Delay
10
30
ns
VCC = 5V. RL = 3.9K. CL = 30pf
VCC = 5V. RL = 400
.eL = SOpf
ELECTRICAL CHARACTERISTICS ITT1800-5 (TA = OOeto +75°e, Vee = 5.0V ±5%)
Symbol
Characteristics
V OH
Output High Voltage
VOL
Output Low Voltage
Min.
Max.
Min. Typ. Max.
Max. Units
2.5
2.6
2.6
Min.
0.45
0.45
Volts
VCC= 5.0V.IOH = -12rnA
Volts
VCC = 5.0V.IOL = 12 rnA
Vce = 5.0V.IOL = 11.4 rnA
Volts
Guaranteed Input High
Threshold For All Inputs
0.50
V IH
Input High Voltage
V IL
Input Low Voltage
1.8
1.9
2.0
0.95
1.1
1.2
Conditions and Comments
Volts
Guaranteed Input Low
Threshold For All Inputs
IF
Input Load Current
IR
Input Leakage Current
ISC:;
Output Short Circuit
5.0
0.61
1.30
1.33
mA
mA
VF = 0.45VjVCC = 5.0V
V F = 0.5V. 4.0V On Other Inputs
10.0
fJ.. A
VCC = 5.0V. V R = 4.0V
Gnd On Other Inputs
1.25
mA
VCC = 5.0V
1.4
1.4
5.0
0.61
1.30
0.535
Current
VO UT = Gnd
100
fJ.A
VCC = VCEX = 5.0V
Power Drain Current
IpC
(Per Gatel
4.0
rnA
Vce = 5.0V Inputs Open
Max VCC Current
IMAX
(Per Gatel
4.0
rnA
VCC = B.OV Inputs Gnd
80
30
ns
ns
ICEX
tpd+
tpd-
Output Leakage Current
Turn Off Delay
Turn On Delay
25
10
4-27
VCC = 5V. RL = 3.9K. CL = 30pf
VCC = 5V. R L = 400'fl.CL = 50p
ITT
----.
DTL QUAD TWO-INPUT AND GATE
FAST DTL QUAD TWO-INPUT AND GATE
ITI1806
ITI1807
Package: Dual In-Line and Flat Pack
SEMICONDUCTORS
Dll QUAD TWOINPUT AND GATE
FAST OTL QUAD
TWO-INPUT AND GATE
The ITT1806 and 1807 perform the logical AND
function. Thus the device can be used to
expand the inputs of other DTL NAND, OR, or
NOR gates, or flip flops, greatly simplifying
logic design. As with all ITT DTL gates, the
outputs can be tied together to perform the
wire-AND function.
Pinout: Dual In-Line and Flat Pack
the ITT1806 incorporates a 6K output pull-up
resistor which .allows for a fan-out of up to 8
DTL loads.
The ITT1807 incorporates a 2K output pull-up
resistor which typically results in a 30% faster
rise time witli capacitive loads at a fan-out of
up to 7DTL loads.
SCHEMATIC DIAGRAM -.EACH GATE
Vee
1.75K
ABSOLUTE MAXIMUM RATINGS'
Characteristics
Units
c
2K
Supply Voltage (VCe), -55°C to +125°C,
Continuous ................................... -.5 to +8.0 Volts
Supply Voltage (VCC), Pulsed,< 1 sec .... + 12 Volts
Output Current. Into Outputs ........................... 30 mA
Input Forward Current ................................... -1 0 mA
Input Reverse Current .......................................... 1 mA
Operating Temperature ................... -55 to + 125°C
Storage Temperature ...................... -65 to + 150°C
Operating Junction Temperature 2 ............... + 175°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering, 60 sec.) ....................... 300° F
A
B
5K
GND
NOTES:
1. Above which useful life may be impaired.
2. Allow 300·C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50·C/Watt
OJ-C for TO-5; 180·C/Watt OJ-C for 1/4"
x 114" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
4-28
RI
=6K
R
=2K FOR
FOR IB06
1807
DTL QUAD TWO-INPUT AND GATE
FAST DTL QUAD TWO-INPUT AND GATE
=-55
ELECTRICAL CHARACTERISTICS ITT1807-1 (TA
Sym~1
Characteristic
V OH
Output High Voltage
VOL
Output Low Voltage
V IH
Input High Voltage
VIL
Input Low Voltage
IF
Input Load Current
-55°C
Min. Max.
2.5
Limits
+:!5°C
Min. Typ.
Max.
2.6
3.5
C to + 125 C, Vee
=5.0V
ITT1806
ITT1807
+ 10%)
+125°C
Min. Max. Units Conditions and Comments
2.5
VoltS! Vce = 4.5V. 10H = -0.54 rnA
Inputs at ViH (~ee Below)
0.4
0.27
2.1
1.4
1.1
-1.5
-1.2
-1.4 rnA
-1.08 rnA
2.0
ELECTRICAL CHARACTERISTICS ITT1807-5
Characteristics
VO H
Output High Voltage
VOL
Output Low Voltage
5.0
Inputs Open
Vee = 5.0V
Inputs Grounded
65
65
ns
ns
Vee = 5V. RL
Vec = 5V. Rl
ITA = aOCto +75°C. VCC
4.2
VIL
Input Low Voltage
1.2
1.1
IF
Input Load Current
1.4
1.4
1.9
ISC
Output Short Circuit
Vee = 5.0V.IOL = 10.5 mA
VCC = 5.0V.IOL = 10.2 mA
One Input at VIL
Volts
Guaranteed Input High
Threshold For All Inputs
0.95 Volts
Guaranteed Input Low
Threshold For Alllnptits
rnA
10.0 .uA
VF = 0.45V. Vec = 5.0V
V F = 0.5V
VCC= 5.0V. VR = 4.0V
Gnd On Other Inputs
1.853.66
rnA
VCC = 5.0V
VO UT = Gnd
Current
Output Leakage Current
Conditions & Comments
Volts
1.8
5.0
= 5.0V ±5%)
Vee = 5.0V.IOH = -0.12 mA
Inputs at VIH
1.33
5.0
= 3 9K Cl = 3Op!
= 400 n.CL = 50p!
liolts
0.5
Input High Voltage
Input leakage Current
I
Vee = 5.5V: V F = O.4V
Vee = 4.5V. 4.0V on other inputs
rnA
mA
V IH
IR
Guaranteed Input Low Threshold
For All Inputs
5.15
7.25
0.55
2.0
Guaranteed Input High Threshold
For All Inputs
Vee = 5.5V. VR= 4.0V
Ground on other inputs
4.3
0.5
Vee = 4.5V. 10L = 10.8 rnA
Vee= 5.5V.IOL = 13.5mA
One Input at VIL (See Below)
JlA
+75°C
+25°C
Min. Max. Min. Typ. Max. Min. Max. Units
4.3
Volts
-1.5
Turn Off Delay
Tum On 'Delay
Symbol
0.8
-0.93 -1.16
Vee Current "Gatea',,"
IpD
Per gate Vee Current "Gate On"
~ct+
Volts
IVaIts
1.7
Input Leakage Current
tpd-
0.4
1.9
-1.16
IR
04
100
p.A
VCC :, VCEX = 5.0V
Power Drain Current
IpD
Per gate
7.75
rnA
Vce = 5.0V Inputs GND
I MAX
Max Vce Current
Per gate
9.75
rnA
Vce = 8.0V Inputs Open
65
65
ns
ns
Vee = 5V. RL = 3.SK. el = 30pl
VCC = 5V. Rl = 400 n.Cl = 50p!
ICEX
Ipd+
Ipd-
Turn 011 Delay
Turn On Delay
10
10
4-29
ITT1806
ITT1807
DTL QUAD TWO-INPUT AND GATE
FAST DTL QUAD TWO-INPUT GATE
-55°C
Min. Max. Min.
Symbol
Characteristic
VOH
Output High Voltage
VOL
Output low Voltage
V IH
Input High Voltage
VIL
Input Low Voltage
1.4
IF
Input load Current
-1.5
-1.11
IR
Input Leakage CUHent
Typ.
+125°C
Max. Min. Max. Units
Conditions and Comments
~olts VCC = 4.5V. 10H = -0.18 rnA
.2.5
2.6
2.5
Inputs at VIH (See Below)
0.4
2.1
0.4
1.7
1.9
1.1
-1.5
-0.93 -1.11
tpd+
VOL
Output low Voltage
Guaranteed Input Low Threshold
For All Inputs
-1.4 rnA
-1.08 rnA
5.0
BO
25
10
65
ooe
Output High Voltage
O.B f./olts
4.B8
ELECTRICAL CHARACTERISTICS ITT1806-5 (TA
VO H
Guaranteed Input High Threshold
For All Inputs
5.15
Turn Off Delay
Turn On Delay
2.6
+25°C
2.6
0.45
VCC = 4.5V. 10l = 12 rnA
VCC = 5.5V.IOl = 15 rnA
Orie Inputs at Vil (See Below)
f./olts
2 ..0
,
IpO
Ve e Current "Gate Off"
Per gate Vee Current "Gate On"
tpd-
0.4 flails
5.5~:1
VCC =
VF = 0.4V
VCC = 4.5V. 4 ..oV on other inputs
p..A
Vce = 5.5V. VR= 4.0V
Ground on other inputs
rnA
rnA
Inputs Open
VCC = 5..oV
Inputs Grounded
ns
ns
VCC = 5.0V. Rl := 3.9K. Cl = 30pf
VCC = 5.0V. RL = 400n. Cl = 5 Opf
= aOeto +75°e. Vee = 5.0V ±5%)
+750C
2.5
0.45
Volts
flcc = 5 OV.IOH = -012 rnA
Inputs at VIH
Volts
flce =
0.50
50V.IOl = 12 rnA
~cc = 50V.IOl = 114 rnA
One input at VIL
V1H
Input High Voltage
Vll
Input low Voltage
1.2
IF
Input Load Curre.,t
IR
Input leakage Current
ISC'
Output Short Circuit
2.0
0.61·
VailS
Guaranteed Input High
p-hreshold For All Inputs
1.1
0.95 Volts
Guaranteed Input Low
!Threshold For All Inputs
1.4
1.4
rnA
1.33 rnA
VF = O.45V'lvcc = 5.0V
V F = 0.5V. 4.0V On Other Inputs
5.0
5.0
10.0
VCC= 5.0V. V R = 40V
Gnd On Other Inputs
1.9
1.30
0.61
1.B
1.30
0.535
Il A
1.25 rnA
Current
I CEX
VOUT = Gnd
Output Leakage Current
Power Drain Current
IpD
Per gate
Max Vce Current
IMAX
Per gate
'Pd+
tpd_
Turn Olf Delay
Turn On Delay
VCC = 50V
25
10
100
Il A
VCC = VCEX = 5.0V
5.75
rnA
Vee
=5.0V Inputs Gnd
8,5
rnA
Vee
=B.OV Inputs Open
80
ns
ns
VCC = 5V. RL = 39K CL = 30pf
VCC=5V.Rl=400Q.CL= SOpf
65
4-30
_I·oaI..oaI..
m.. m _____
_
FAST D_T_L_Q_U_A_D_TW_O_-I_N_PU_T_O_R_G_A_T_E_ITI_1_BO_B
DTL QUAD TWO-INPUT OR GATE ITI1B09
Package: Dual In-Line and Flat Pack
SEMICONDUCTORS
DTl QUAD TWO~NPUT
OR GATE
FAST DTl QUAD
TWO-INPUT OR GATE
The ITT 1808 and 1809 elements are quad two
input positive ORI negative AND gates. In
addition to performing the OR function with full
fanout available, outputs can be connected
together to perform the wire-AND function,
thereby reducing system complexity.
Pinout: Dual In-Line and Flat Pack
The ITT1808 incorporate a 6K output pull-up
resistor which allows for a fan-bur of up to 8
DTL loads.
The ITT1809 incorporates a 2K output pull-up
resistor which typically results in a 30% faster
rise time with capacitive loads at a fan-out of
up to 7 DTL loads.
CIRCUIT SCHEMATIC
Vee
2.25K
1.75K
ABSOLUTE MAXIMUM RATINGS
1
Units
Cliaracteristics
2K
Supply Voltage (VCe), -55°C to +125°C,
Continuous ................................... -.5 to +8.0 Volts
Supply Voltage (V ccL Pulsed,.< 1 sec .... + 12 Volts
Output Current. Into Outputs ........................... 30 rnA
Input Forward Current ................................... -1 0 rnA
Input Reverse Current ....................... ,.................. 1 rnA
Operating Temperature ................... -55 to + 125°C
Storage Temperature ...................... -65 to + 150°C
Operating Junction Temperature 2 ............... + 175°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering, 60 sec.) ....................... 300° F
A
B
NOTES:
1.75K
1. Above which useful life may be impaired.
2. Allow 300°C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50°C/Watt
OJ-C for TO-5; 180°C/Watt OJ-C for 1/4"
x 1/4" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
R, = 6K FOR '808
R,= 2K FOR '809
Vee
4-31
ITT 1808
ITT 1809
DTL QUAD TWO-INPUT OR GATE
FAST DTL QUAD TWO-INPUT OR GATE
ELECTRICAL\CHARACTERISTICS ITT1S0S~1 (TA
=-55
C to + 125 C, Vee
=5.0V+ 10%)
Limits
-650C
+260 C
+125°C
Min. Max. Min.
Typ. Max. Min. Max. Units Conditions and Comments
Symbol
Characteristic
vOH
'Output High Voltage
2.5
~olts VCC =;: 4.5V.IOH = -0.18 rnA
2.5
2.6
Onellnput at VIH (~ee Below)
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
In,put Low Voltage
1.4
IF
Input Load Current
-1.5
-1.1
IR
Input Leakage Current
2.0
IpD
vcc Current "Gate .Off
1.9
2.1
Vce = 4.5V.IOL = 12 rnA
VCC = 5.5V.IOL = 15 rnA
Inputs at VII. (See 8elowl
~olts Guaranteed Input High Threshold
1.7
For All Inputs
1.1
0.8
-1.5
-0.93 -1-11
Per gate VQc Current U~ate On"
tpd+
tpd_
0.4 ~olts
0.4
0.4
Volts
-1.4 mA
-1.08 mA
Vce = 5.5V:1 VF = 0.4V
VCC = 4.5V. 4.0V on other inputs
/l.A
Vee = 5.5V. VR= 4.OV
Ground on other inputs
7.61
6.25
mA
mA
Inputs Open
Vee = 5.OV
Inputs Grounded
90
ns
ns
Vee = 5V. RL := 3.9K. CL = 30pf.
Vee = 5V. RL = 4000. CL = 50p
Turn Off Delay
rum On Delay
5.0
Guaranteed Input Low Threshold
For All Inputs
65
ELECTRICAL CHARACTERISTICS ITT1S0S-5 (TA = OOCto +15°C. VCC = 5.0V ±5%)
DOC
fiS"C ' +7SoC
Symbol
Characteristics
V OH
Output High Voltage
vOL
Output low Voltage
VIH
Inpul High Voltage
VIL
Input low Voltage
1.2
IF
Input load Current
IR
Input leakage Current
Ise
Output Short Circuit
Current
I CEX
Max.
Output leakage Current
2.6
Min. Typ. Max.
Min.
Max.' Units Conditions & Comments
2.5
2.6
Volts
0.45
0.45
Volts
2.0
-
I MAX
Max Vec Current
Per gate
Turn Off Delav
Turn On Delay
061·
Yee = 5.0V.IOH = -0,12 mA
One Input at VIH
Vee = 5.0V. 10l = 12 mA
5.0V.IOL = 11.4 mA
Inputs at VIL
Vec =
0.50
Power Drain Current
IpO
Per gate
tpd+
tpd-
Min.
Volts
Guaranteed Input High
hreshold For All Inputs
1.1
0.95 Volts
Guaranteed Input L~w
hreshold For All Inputs
1.4
1.4
rnA
1.33 mA
VF = 0.45Vlvcc
5.0V
VF. = 0.5V.
4.0V On, Other Input
5.0 .
5.0
10.0 jlA
VCC= S.OV. V R = 4.0V
Gnd On Other Inputs
1.25 mA
Vec
SOV
VO UT = Gnd
1.9
1.30
0.61
1.8
1.30
0535
=
=
= VCEX =
100
jlA
VCC
7.25
mA
Vec
14.25
mA
VCC = 8.0V"lnputs Gnd
90
65
4-32
ns
ns
50V
=S.OV Inputs Open
=
VCC
SV. Rl = 3,9K. Cl' = 30pf
vec = SV. RL = 400{} .cL = 501'
DTL QUAD TWO-INPUT OR GATE
FAST DTL QUAD TWO-INPUT OR GATE
ITT1808
ITI1809
ELECTRICAL CHARACTERISTICS ITT1809·1 (TA = -55 C to + 125 C, Vcc = 5.0V + 10%)
Symbol
VOH
Characteristic
Min. Max.
Output High Voltage
2.5
Min. Typ.
2.6
Max.
3.5
Min. Max. Units
1 2 .5
Volts
Vee = 4.5V. 10H = -0.54 mA
One IInput at ViH (See Below)
Volts
Vee = 4.5V. 10L = 10.8 mA
Vee = 5.5V. 10L = 13.5 mA
Inputs at VIL (See Below)
Volts
Guaranteed Input High Threshold
For All Inputs
Volts
Guaranteed Input l.ow Threshold
For All Inputs
I
VOL
04
Output Low Voltage
0.27
04
0.4
j
VIH
Input High Voltage
VIL
Input Low Voltage
IF
Input Load Current
1,9
2.1
1,4
0,8
1.1
-1.5
-1.2
-1.5
-1.4 mA
-1.08 mA
-0.93 -1.16
-:-1.16
IR
1.7
Input Leakage Current
2.0
Ve e Current "Gate Off"
IpD
Per gate Vee Current "Gate On"
tpd+
tpd-
p.A
Vee = 5.5V. VR= 4.0V
Ground on other inputs
7.61
mA
Inputs Open
Vee = 5.0V
Inputs Grounded
Turn Off Delay
Turn On Delay
75
65
Symbol
Characteristics
vOH
Output High Voltage
VOL
Output Low Voltage
(T A
43
4.3
0.5
V IL
Input low Voltage
1.2
1.1
IF
Input Load Current
1.4
1.4
VCC = 5.0v. 10H = -0.12 rnA
VCC= 5.0V.IOL = 10,5mA
VCC = 5.0V. 10L = 102 rnA
2,0
1.9
Volts
:Guaranteed Input High
Threshold For All Inputs
0.95 Volts
Guaranteed Input Low
Threshold For All Inputs
1.8
rnA
5.0
5.0
10,0 p,A
1.853.68
mA
lOa
pA
Current
I CEX
Output Leakage Current
IpD
Per gate
Power Drain Current
IMAX
Max VCC Current
;Per gate
tpd+
tpd-
Turn Off Delay
Turn On Delay
= 3.9K. CL = 30pf
= 400 CL = 50pf
Volts
1.33
Output Short Corcuit
Vce c SV. RL
Vce = 5V. RL
Volts
4.2
0.5
Input High Voltage
ISC
ns
OOC
+25°C
+75°C
Min. Max. Min. Typ. Max. Min. Max. Units Conditions 8< Comments
V IH
Input Leakage Current
ns
= ooe to +75°e, Vee = 5.0V ±5%)
055
IR
5.5V~IVF
Vee =
= 0.4V
Vee = 4.5V: 4.0Von other inputs
5.0
8.38 mA
ELECTRICAL CHARACTERISTICS ITT1809·5
Conditions and Comments
-
9.38
rnA
14.25
rnA
75
65
ns
ns
4-33
VF = 045vlvcc = 50V
VF = 0 5V. 4.0Von other inputs
VCC= S.OV. V R = 4.0V
Gnd On Other Inputs'
VCC = S OV
V OUT = Gnd
= VCEX = 5 OV
VCC = 5.0V Inputs Open
VCC
--'
VCC = 8 OV Inputs Gnd
VCC = 5V. RL = 39K. CL = 30p!
VCc= 5V. RL = 400 n.Cl = Sap!
ITT
----DTL QUAD TWO-INPUT NOR GATE
FAST DTL QUAD TWO-INPUT NOR GATE
SEMICONDUCTORS
ITT1810
ITT1811
Package: Dual In-Line and Flat Pack
DTL QUAD TWOINPUT NOR GATE
FAST DTl QUAD
TWO-INPUT NOR GATE
The ITT181 0 and ITT1811 elements are quad
four-input positive NOR gates. In addition to
performing the positive NOR and negative
NAN D logic functions, the gates can be crosscoupled to form a flip-flop or the outputs can
be tied together to perform the "wired OR"
function.
Pinout: Dual In-Line .and Flat Pack
The ITT1810 incorporates a 6K output pull-up
resistor which allows for a fan-out of up to 8
DTL loads.
The ITT1811 incorporates a 2K output pull-up
resistor which typically results in a 30% faster
rise time with capacitive loads at a fan-out of
up to 7 DTL loads.
CIRCUIT SCHEMATIC -EACH GATE
r - - - - - - - - - ; s I - - O Vce
1.75K
ABSOLUTE MAXIMUM RATINGS
Characteristics
1
Units
Supply Voltage (V CC ). -55°C to + 125°C.
Continuous ................................... -.5 to +8.0 Volts
Supply Voltage (V CC ). Pulsed.<1 sec .... +12 Volts
Output Current. Into Outputs ........................... 30 rnA
Input Forward Current ................................... -1 0 mA
Input Reverse Current .......................................... 1 mA
Operating Temperature ................... -55 to + 125°C
Storage Temperature ...................... -65 to + 150°C
Operating Junction Temperature 2 ............... + 175°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering. 60 sec.) ....................... 300° F
2K
A
B
5K
2K
GNO
NOTES:
1. Above which useful life may be impaired.
2. Allow 300°C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50°C/Watt
OJ-C for TO-5; 180°C/Watt OJ-C for 1/4"
x 1/4" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
1.75K
Vee
R1 =6K for 1810
R1 =2K for1811
4-34
ITT1810
ITT1811
DTL QUAD TWO-INPUT NOR GATE
FAST DTL QUAD TWO-INPUT NOR GATE
ELECTRICAL CHARACTERISTICS ITT1810-1
Symbol
Characteristic
VO H
Output High Voltage
VOL
Output Low Voltage
V IH
Input High Voltage
V IL
Input Low Voltage
IF
Input Load Current
Limits
-550C
+25°C
Min. Max. Min.. Typ.
2.5
(T A = - 55" C to
+125°C
Max. Min. Max. Units
2.6
12.5
0.4
2.1
04
1.9
-1.5
-1.5
-1.H
-0.93 -1.1E
Input Leakage Current
2.0
IpD
VCC Current "Gate On"
'Per gate VCC Current "Gate OIl'
tpd+
Tlirn Olf Delay
Turn On Delay
25
10
Characteristics
VO H
Output High Voltage
VOL
Output low Voltage
Min.
OOC
Max.
2.6
0.8
5.0
Conditions and Comments
!vcc
= 4.5V.IOH = -0.18 rnA
Inputs atV IL ISee Below)
VCC = 4.5V.IO L = 12 rnA
VCC = 5.5V.IOL = 15 rnA
Inputs atV IH (See Below)
Volts
Guaranteed Input High Threshold
For All Inputs
:Volts
Guaranteed Input Low Threshold
For All Inputs
I
VCC = 5.5V: VF = 0.4V
VCC = 4.5V. 4.0V on other inputs
5.0
2.94
rnA
rnA
Inputs Open
VCC = 5.0V
Inputs Grounded
90
ns
ns
VCC = 5V. RL = 3.9K. CL = 30pl
VCC = 5V. Rl = 400
.Cl = 50p!
(T A = DoC to +75°C. Vee = 5.0V ±5%)
Max. Units Conditions & Comments
Volts
VCC = 5.0V. 10H = -0.12 rnA
Volts
VCC = 5.0V. 10l
VCC
5.0V.IOl
Volts
Guaranteed Input High
hreshold For All Inputs
0.95 Volts
Guaranteed Input Low
Threshold For All Inputs
2.5
0.45
0.50
V IH
Input High Voltage
V il
Input low Voltage
1.2
1.1
IF
Input load Current
1.4
1.4
IR
ISC
Input leakage Current
Output Short Circuit
5.0
5.0
061·
1.8
1.9
-
1.30
0.61
± 10%)
VCC = 55V. VR= 4.0V
Ground <)n other inputs
2.6
2.0
C. VCC = 5.0V
Ji..A
+25°C
+75°C
Min. Typ. Max.
Min.
0.45
Q
Volts
-1.4 rnA
-1.08 rnA
30
ELECTRICAL CHARACTERISTICS ITT1810-5
Symbol
0.4
1.1
IR
tpd-
faits
1.7
1.4
+ 125
1.30
0.535
=
= 12 mA
= 11.4 mA
=
1.33
mA
rnA
VF
0.45V.\VCC - 5.0V
V F = 0.5V. 4.0V On Other Inputs
10.0
jlA
VCC= 5.0V. V R = 4.0V
Gnd On Other Inputs
1.25
rnA
VCC = 5.0V
V OUT = Gnd
Current
ICEX
Output leakage Current
100
itA
VCC = VCEX = 5.0V
IpD
Power Drain Current
5.5
rnA
VCC = 5.0V Inputs Open
5.62
rnA
VCC = 8.0V Inputs Gnd
90
30
ns
ns
Per gate
I MAX
Max VCC Current
Per gate
tpd+
tpd-
Turn Off Delay
Turn On Delay
25
10
4-35
VCC
VCC
= 5V. RL =
= 5V. Rl =
3.9K. Cl = 30pl
400 n.Cl = 50p
DTL QUAD TWO-I N PUT NOR GATE
FAST DTL QUAD TWO-INPUT NOR GATE
(TA = -55°C to
ELECTRICAL CHARACTERISTICS ITT1811-1
+ 125°C. VCC =
ITT1810
ITT1811
5.0V ±10%)
LIMITS
Symbol
Characteristic
V OH
Output High Voltage
Min. Max.
Min. Tvp.
2.6
2.5
Max.
Min. Max. Units Conditions and Comments
2.5
3.5
Volts
VCC = 4.5V.IOH = -0.54 rnA
Inputs at VI L (See Below)
VOL
Output Low Voltage
V IH
Input High Voltage
Vll
Input low Voltage
IF
Input load Current
0.4
0.27
04
1.9
2.1
1.1
-1.5
-1.2
-1.5
-0.93 -1.16
VCC Current "Gate On"
IpO
Per gate VCC Current "Gate Off'
'Pd-
Turn Off Delay
Tum 0'; Delay
Symbol
Characteristics
Output High Voltage
VOL
Output Low Voltage
Volts
Guaranteed Input High Threshold
For All Inputs
O.B
Volts
Guaranteed Input Low Threshold
For All Inputs
-1.4
rnA
.5.0
VCC = 5.5V. VR= 4.0V
Ground on other inputs
6.9
2.94
rnA
rnA
Inputs Open
VCC = 5.0V
Inputs Grounded
'75
ns
ns
vee = 5V. RL = 3.9K. eL = 30pf
vee = 5V. RL = 400 .CL = SOpf
(TA = O°Cto +75°C. Vce= 5.0V ±5%)
Min. Max. Min. TVp. Max. Min. Max. Units Conditions & Comments
4.3
4.3
0.5
Vec = 5.0V.IOH
Volts
Vec
5.0V. 10L
Vee ~ 5.0V.IOL
Volts
Guaranteed Input High
Threshold For All Inputs
0.95 Volts
Guaranteed Input Low
, Threshold For All Inputs
0.55
Input High Voltage
V IL
Input Low Voltage
1.2
1.1
IF
Input Load Current .
104
1.4
2.0
1.9
1.8
rnA
1.33
Input Leakage Current
Ise
Output Short Circuit
5.0
5.0
= -0.12 rnA
= 10.5 rnA
= 10.2 rnA
Volts
4.2
0.5
V IH
IR
IV
VCC = 5.5V:
F ;= OAV
VCC = 4.5V. 4.0Von other inputs
/lA
30
ELECTRICAL CHARACTERISTICS ITT1811-5
vOH
VCC = 4.5V.I OL = 10.8 rnA
VCC = 5.5V.IOL = 13.5 rnA
Inputs at VI H (See Below)
-1.08 rnA
2.0
Input leakage Current
tpd+
Volts
1.7
1.4
-1.16
IR
0.4
10.0 .I.!.A
=
= OA5V\ VCC = 5 OV
= 05V
Vce= 50V. V R = 4.0V
VF
VF
Gnd On Other Inputs'
100
fJ.A
=
=
Vce = VCEX
. 7..65
rnA
VCC = 5.0V Inputs Open
5.62
rnA
75
30
ns
ns
1.853.68
rnA
Current
I CEX
Output Leakage Current
IpD
Per gate
Power Drain Current
I MAX
Max VCC Current
Per gate
tpd+
tpd-
Turn Off Delay
Turn On Delay
10
10
4-36
VCC
50V
VOUT
Gnd
= S.OV
i Vce = 8 OV Inputs Gnd
Vec = 5V. RL = 3.9K. CL = 30pf
vec = 5V. f1L = 400 .CL = SOpf
ITT
-
ITT9093, ITT9094, ITT9097, ITT9099
DUAL DTL MASTER-SLAVE J-K FLIP-FLOPS
SEMICONDUCTORS -----------~
Package: Dual In-L.ine and Flat Pack
DUAL DTL MASTER-SLAVE J-K FLIP-FLOPS
ITTSOS3/9094
(DUAL ITT945/948 SEPARATE So: SEPARATE Cp )
The ITISOS3 and ITTSOS4 are single chip dual
flip-flops with circuitry similar to the ITIS45 and
ITIS48 respectively. They feature internal J-K
connections. separate clock pins. and separate SO
pins. They are useful in ripple-carry counters and
many other J-K flip-flop applications.
The ITISOS7 and ITTSOSS are single chip dual
flip-flops with circuitry similar to the ITIS48 and
ITIS45 respectively. They feature internal J-K
connections. a ·common clock pin. a common CD
pin. and separate SO pins. They are useful in shift
registers. shift counters. and synchronous counters.
The ITTSOS3 and ITISOSS are usable with clock
frequencies up to 5 MHz and feature a DC level
sensitive clock input for stable operation regardless
of clock waveshape.
GND
The ITTSOS4 and ITISOS7 are usable with clock
frequencies up to 8 MHz.
7
ITT9097/9099
(DUAL ITT948/945 COMMON Cp : COMMON Co)
These circuits are fully compatible with the ITIS30
series OTL family and the ITISOOO series TTL
family.
The ITISOSS series of flip-flops feature J-K
feedback connections directly from the output
stage of the device. This configuration increases the
inherent noise immunity of the circuit. but prevents
the circuit from being used in a wired - 0 R mode.
Wired - OR capability is obtained with the
ITISOSSX series of devices. which are functionally
equivalent to the ITTSOSS series. but have J-K
feedback connections from the buffer stage of the
slave flip-flop.
ABSOLUTE MAXIMUM RATINGS 1
Characteristics
Pinout: Dual In-Line and Flat Pack
Units
Supply Voltage (VCC). -55°C to +125°C.
Continuous ..................................... -0.5 to +8 Volts
Supply Voltage (V CCI. Pulsed. < 1 sec ..... + 12 Volts
Output Current. Into Outputs ........................... 30 mA
Input Forward Current ................................... -10 mA
Input Reverse Current .......................................... 1 mA
Operating Temperature ................... -55to +125°C
Storage Temperature ...................... -65 to + 125°C
Input Voltage Applied to Input. -1.5 to +5.5 Volts
Lead Temp. (soldering. 60 sec.) ................•..... 300°C
NOTES:
1. Above which useful life may be impaired.
2. Allow 300·C/Watt OJ-A for 1/4" x 1/4"
flatpack and dual in-line. Allow 50·C/Watt
OJ-C for TO-5; 180·C/Watt OJ...,.c for 1/4"
x 1/4" flatpack and dual in-line. Heat removal
in 1/4" x 1/4" flatpack is highly dependent
upon contact surfaces or air flow and on lead
attachment and thermal paths thru leads, as
well as number of soldered leads.
4-37
ITT9093, ITT9094, ITT9097, ITT9099
DUALDTL MASTER-SLAVE J-K FLIP-FLOPS
NOTES:
1.
Positive logic: 0= L. 1 = H is shown.
2.
With synchronous entry. output changes occur as
clock level changes from High to Low. For operation
4.
in accordance with the table. J and K inputs should
normally be changed while the clock is low. and
the 9093-9094 may be used as a dual flip-flop having CD terminals available. and the 9097-9099 may
be used as a dual flip-flop having separate CD terAll rules for
minals and a common So terminal.
maintained while the clock is high.
3.
Asynchronous entry overrides synchronous entry. re-
ITT945 apply to ITI9093 and 9099. All rules for
ITT948 apply to ITI9094 and 9097.
gardless of clock level. If So and CD are both low.
then both go high simultaneously. final condition
cannot be predicted. For proper operation. the So
5.
ASYNCHRONOUS ENTRY
TRUTH TABLES
Refer to the ITT945/948 for typical operating characteristics.
or CD terminals must be held in the low state for
at least 50 nanoseconds.
Inputs
From circuit symmetry. the So and CD pin designations may be interchanged by interchanging the
J and K. and also the Q and Q pin designations. Thus.
SYNCHRONOUS ENTRY
Outputs
Inputs
Output
So
CD
a
a
J
K
On+1
0
0
0
1
an
0
0
0
0
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
an
No Change
1
+5.0 V
O.lMF
I
TPD TEST CIRCUIT
r----r .-__...---,
R
IN9162K
4-38
ITT9093, ITT9094, ITT9097, ITT9099
DUAL DTL MASTER-SLAVE J-K FLIP-FLOPS
CIRCUIT SCHEMATICS
FOR COMPONENT VALUES. REFER TO ITT945/948
ITT9093/9094 (1/2 OF
ITT9097/9099
ITT9093'X/9094X
9093 SHOWN)
ITT9097X/9099X
(1/2 OF 9097 SHOWN)
(1/2 OF'9094X SHOWN)
(1/2 OF 9099X SHOWN)
Vee
Vee
Vec
t-------+=-=----~To
!-colio)
Other
'--r------;,.- Flip-Flop
Vcc
Vcc
t--------t-='-'.:..------.;;.-To Other
Colio)
4-39
'-----r-~
Flip-Flop
ITT9093, ITT9094, ITT9097, ITT9099
DUAL DTL MASTER. SLAVE J-K FLIP-FLOPS
ELECTRICAL CHARACTERISTICS ITT9093·1. 9094-1. 9097·1. 9099·lITA = -55'C.o +125'C. VCC = 5.0II±10%)
Umits
-S5'C
Symbol
Characteristic
VOL
Output High Voltage
VOL
9093.9099 .
9094.9097
Min.
Mllx
2.5
2.5
Output Low Voltage
+25'C
Min.
Typ.
+125'C
Max.
2.5
2.5
Min.
Max.
2.5
2.5
Units Conditions and'Comments
Volts VCC = 4.5V.IOH = -180pA
VCC = 4.SV.IOH = -540 pA
0.4
0.4
0.4
0.4
0.4
0.4
VCC =
VCC =
VCC=
VCC =
Volts
Guaranteed Input High Threshold
9093.9099
9094.9097
VIH
Input High Voltage
VIL
Input low Voltage
IR
2.1
1.9
1.7
4.5V. 10L =
5.5V.IOL =
4.5V.IOL =
5.5V;lOL =
Volts
12.0 mA
15.0mA
13.0mA
13.6 rnA
For Alllnpu.s
1.4
1.1
0.8
Volts
Input Leakage. All J.K
S.C.SO.CO; Inpu ••
lexcep' Co of 9097. 9099)
2.0
5.0
pA
Input Leakage of Co
4.0
10
Guaranteed Input low Threshold
For Alllnpu's
VCC = 5.5V. VR = 4.011
GNO On O.her InpulS
9097.9099
IRCP
Inpu' Leakage. CP Inputs
9093.9094.
9097.9099
IF
Input Current. All
J.K.S.C Inputs
Input Current.
So or Co
10
20
20
40
-.98
-.98
-.92
-2.2
-2.2
-1.93
-2.93
-2.35
-4.68
-5.86
-2.93
-2.35
-4.68
-5.86
-2.57
-2.03
-4.04
-5.14
-0.76
-0.76
-0.72
-1.7
-1.7
-1.5
VCC = 4.0V. VR = 4.011
mA
VCC= 5.5V
VF = 0.4V
4.0V On Other InpulS
mA
VCC=4.5V
9093.9094
Input Current. CP InPl:Its
9093
9094
9097
9099
IF
Input Current. All
J.K..S.C Inputs
Input Current. So
OrCO Inputs
9093.9094
VF~0.4V
4.0V On O.her InpulS
Input Current. CP Inputs
9093
9094
9097
9099
'FSI
Input Current. CO. So Inputs
9097.9099
IpO
-2.26
-1.83
-3.66
-4.52
-2.26
-1.83
-3.66
-4.52
-2.02
-1.59
-3.18
-4.04
-2.26
-2.93 -2.57
-2.20
-2.93
-2.26
VccCurrent
mA
VCC = 5.5V. VF = 0.4V
VCC= 4.5V
4.0V On O.her Inpu's
mA
VCC = 5.0V. AlllnpulS Open
Momentary Ground On
9093
9094·
9097
9099
'pd+
tpd-
Tum Off Delay· Clock
9094.9U97
9093.9099
16.6
19.8
19.8
16.6
So
28.0
32.4
32.4
28.0
35
35
65
75
ns
VCC~
30
30
75
75
ns
RL = 330
5.0V
RL = 2K. CL = 30pf
Turn On Delay
9093.9094.
9097.9099
4-40
. CL = 50pf
ITT9093, ITT9094, ITT9097, ITT9099
DUAL DTL MASTER-SLAVE J-K FLIP-FLOPS
ELECTRICAL CHARACTERISTICS ITT9093·5. 9094·5. 9097·5.9099·5 ITA = Doe to 75°C. Vee
= 5.0V ±5%1
limits
Symbol
Characteristic
VOH
Output High Voltage
Min.
2.6
4.3
9093.9099
9094.9097
VOL
Max,
Output low Voltage
9093.9099
9099.9097
Min.
+25°C
Typ.
Max.
2.6
4.3
0.45
0.45
+75°C
Min.
Max.
3.1
4.3
0.45
0.45
Units Conditions and Comments
Vee = 5.0V
10H = -110)JA
Volts
0.45
0.45
Vee = 5.0V
10L = 15.8rnA
10L = 15.1 rnA
10L = 14.4 rnA
10L = 13.7 rnA
Volts
V IH
Input High Voltage
V IL
Input low Voltage
1.4
1.1
0.8
Volts
IR
Input Leakage. All
J·K S, C.
Inputs
5.0
5.0
10.0
)JA
Vec = 5.0V. VR
10.0
10.0
20.0
20.0
VCC = 4.0V. VR = 4.0V
2.1
1.7
1.9
Volts
Guaranteed Input High Threshold
For All Inputs
Guaranteed Input low Threshold
For All Inputs
So.
(except Co '.)f
9097.90991
Input Leakage Of Co
9097.9099
I RCP
IF
Input leakage. CP
Inputs 9093. 9094
9097.9099
20.0
40.0
30.0
60.0
)JA
40.0
Input Current. All
0.95
0.95
0.90
rnA
2.10
2.10
2.00
2.BO
2.24
4.4B
5.60
2.80
2.24
4.48
5.60
2.66
2.13
4.26
5.32
rnA
5.60
2.BO
5.60
2.80
5.32
2.66
rnA
1.41
rnA
GND On Other Inputs
VCC
= 5.0V. VF = 0.45V
4.0V On Other Inputs
J.K.S.C Inputs
Input Current
= 4.0V
So
Or Co 19093. 90941
I FCP
Input Current. CP Inputs
9093
9094
9097
9099
I FSI
Input Current
9097. 9099 Inputs CD
9097.9099 Inputs So
ISC
leex
Output Leakage
IpO
Vee Current
0.59
1.77
1.41
4.2
0.59
0.59
Vec = 5.0V. VOUT = GNO
-1.0V On Opposite J Or K
30
35
VCC = Veex
A
= 5.0V
Vee = 5.0V.lnputs Open
rnA
Clock Pulse On
Maximum Vee Current
So
VCC = B.O .Allinputs GNO
9093
9094
9097
42
4B
909~
3B
rnA
35
,
Turn Off Delay
9094.9097
9093.9099
'pd-
1.41
105
9093.9099
9094.9097
tpd+
Vce = 5.0V. VF = 0.45V
4.0V On Other Inputs
Output Short Circuit Current
9093.9099
9094.9097
IMAX
VCC = 5.0V. VF = 0.45V
4.0V On Other Inputs
35
35
65
75
30
30
75
75
ns
Vce = 50V
RL = 2.0K. CL = 30pf
Turn On Delay
9093.9094
9097.9099
I
4-41
RL = 330
CL = 50p!
_ITT ___
D_T_L_G_A_T_E_P_R_O_P_A_G_A_TI_O_N_D_E_L_A_Y_T_E_S_T_IN_G
SEMICONDUCTORS
DT L
TEST
CIRCUIT
TEST CIRCUIT
WAVEFORMS
PULSE IN
O~
pw=IOOns
NOTES:
a) All Diodes 1 N914 or equivalent
b) C1 and CI include Probe and Jig
Capacitances
c) 1 N914 Diodes are added to Pins 5 and 9
when testing
d) 6Ku Pull-up resistors are added to Pins 6
and 8 when testing ITT938
e) Pins 4 and 10 are open or grounded as
required by device logic
4-42
_I
ITT301, ITT301 H
DUAL EXPANDABLE
mm
-IL-IL _____________F_IV_E_-I_N_P_uT~N=A=N=D=B=U=F=F=E~R
SEMICONDUCTORS
DUAL EXPANDABLE FIVE-INPUT NAND BUFFER
Pin Configuration
The ITT301 is an active pull-up element featuring high current capability in both the high
and low state. It is an .excellent choice for
driving long transmission lines, as a system
clock driver, or for driving any load with high
capacitance.
INPUTS
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature
Range ................ --65°C to 1r150°C
Operating Temperature Range
301 H-1, 301-1 ........ --55°C to 1r125°C
301 H-5 .............. --':'30°C to 1r 75°C
301-5 .................. --30°C to 1r85°C
Lead Temperature, 1/16 inch from
case, 60 seconds maximum ........ 300°C
Supply Voltage
Continuous .................... 1r16.5V
Pulsed 0.1 Second .................. 18V
Input Voltage (exclusive of expanders)
301
-1, 301
-5 ........ --0.5V to 16.5V
301 H-1, 301 H-5 ........ --0.5V to 18V
Input Voltage-Expanders ........ OV to 6.0V
Voltage applied to output ...... -0.5V to Vee
Sink Current, Continuous Buffers .... 80mA
Output short circuit duration to
ground ..................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at: 1r125° ...................... 500mw
at 1r85° ........................ 900mw
5-1
GND
L -_ _ _-j
8
9
X2
0= ABCDE
SCHEMATIC (EACH GATE)
82K
620
'-----"-----oG'D
ITT301, ITT301 H
DUAL EXPANDABLE FIVE""INPUT NAND BUFFER
ELECTRICAL CHARACTERISTICS ITT301-1, ITT301-5 over recommended operating free air
temperature range
Parameter
Vm
Min
Input High Threshold Voltage
V,L
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
1m
Max
Units
6.5
V
5.0
V
10.0
V
Test Conditions
Vee=11.0V, V'L=5.0V
lolt =300ua
1.5
1.8
V
V
V,,=11.0V, V1H=6.5V
IOL=42mA
IOL=63mA
Input High Level Current
10
ua
V,,=13.0V, VR =13.0V
2.1
rnA
Vee=13.0V, VF=1.5V
48
rnA
Vee=13.0V
rnA
Vee = 12V, V'L=5.0V
Vou=7.0V
hL
Input Low Level Current
Icc
Power Supply Current
lou
Output Source Current
15.0
tpd+ Propagation Delay, Positive
Going Output
400
NS
CL=300pf, RL =330n
tpd- Propagation Delay, Negative
Going Output
240
NS
CL=300pf, RL=330n
ELECTRICAL CHARACTERISTICS ITT301H-1, ITT301H-5 over recommended operating free air
temperature range
Min
Parameter
Vm
Input High Threshold Voltage
V,L
Input Low Threshold Voltage
Von
Output High Voltage
VOL
Output Low Voltage
Max
6.5
Units
V
5.0
V
13.0
V
1.8
2.0
Test Conditions
Vee-14.0V, V'L-5.0V
lou =-250ua
V
V
Vee=14.0V, V,u=6.5V
10i.=52rnA
IOL=65
1m
Input High Level Current
10
ua
Vee=16.0V, VR =16.0V
hL
Input Low Level Current
-2.6
rnA
Vee=16.0V, VF=1.8V .
Icc
Power Supply Current
68
40
rnA
rnA
Vee =16.0V
10H
Output Source Current
301H-5
301H-1
15.0
rnA
Vee =15.0V, VIL=5.0V
VOH=9.5V
tpd+ Propagation Delay, Positive
Going Output
400
NS
CL=300pf, RL=330n
tpd- Propagation Delay, Negative
Going Output
240
NS
CL=300pf, RL =330n
5-2
ITT302, ITT302H
ITT
----QUAD 2-INPUT (2 EXPANDABLE)
NAND BUFFER
SEMICONDUCTORS
QUAD 2-INPUT (2 EXPANDABLE) NAND BUFFER
Pin Configuration
The ITT302 open collector quad buffer finds
application as a lamp or relay driver in addition
to its use as a high-sink-current logic element.
the open collector allows easy interfacing with
other logic systems and can be wired-OR for
increased design flexibility.
16
Vee
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -6So to +1S0°C
Operating Temperature Range
302H-1, 302-1 ........ -SSoC to +12SoC
302H-S ................ -30°C to + 7SoC
302-S ................. -30°C to +8SoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ...................... +16.SV
Pulsed 0.1 second ................. 18V
Input Voltage (exclusive of expanders)
302-1, 302-S .............. - O.S to 16.SV
302H-1, 302H-S ............. -O.SV to 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied to output ...... -O.S to 16.SV
Sink Current, Continuous Buffers ...... 80mA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So ...................... SOOmw
at +8So ....................... , 900mw
~I
GND
8
0=
Ali
Schematic (Each Gate)
302
.----+-------Qvcc
82K
1 2K
xo--_ _ _ _- ' V
0
A
L - -......-OGND
5-3
ITT302, ITT302H
QUAD 2-INPUT (2 EXPANDABLE) NAND BUFFER
ELECTRICAL CHARACTERISTICS ITT302-1, 302-5 Over Recommended Operating Free Air
Temperature Range
Parameter
Min
Vm
Input High Threshold Voltage
VIL
Input Low Threshold Voltage
VOL
Output Low Voltage
Max
6.5
Units
Test Conditions
V
V
5.0
1.5
0.4
V
V
V,,=11.0V, VIH=6.5V
IOL=62mA
IOL=16mA
Input High Level Current
10
ua
V,,=13.0V, Vn =13.0V
Ill.
Input Low Level Current
-2.1
rnA
V,,=13.0V, VF=1.5V
Icc
Power Supply Current
40
rnA
V,,=13.0V
IcEx
Output Leakage Current
25
p.A
Vcc=13.0V, VIL=5.0V
VCEx=13.0V
LVcE
Collector Latching Voltage
V
Vcc =13.0V, VIL=5.0V
ICE=4.0mA
1m
13.0
tpd+ Propagation Delay, Positive
Going Output
600
NS
CL=50pf, RL=2kn
tpd- Propagation Delay, Negative
Going Output
200
NS
CL =50pf, RL=2kn
ELECTRICAL CHARACTERISTICS ITT302H-1, 302H-5 Over Recommended Operating
Free Air Temperature Range
Parameter
Min
VIH
Input High Threshold Voltage
Vll •
Input Low Threshold Voltage
VOl.
Output Low Voltage
Max
6.5
Units
Test Conditions
V
V
5.0
1.8
0.4
V
V
Vc ,=14.0V, VllI=6.5V
IOL=64mA
10I.=16mA
1m
Input High Level Current
10
ua
Vec=16.0V, Vn =16.0V
lIT.
Input Low Level Current
-2.6
rnA
V,,=16.0V, VF=1.8V
Icc
Power Supply Current
40
60
rnA
rnA
Vcc =16.0V
25
p.A
Vcc=16.0V. VIL=5.0V
VCEx=16.0V
V
Vcc=16.0V, VIL=5.0V
ICE=4.0mA
302H:1
302H-5
IcEx
Output Leakage Current
LVcE
Collector Latching Voltage
16.5
tpd+ Propagation Delay, Positive
Going Output
600
. NS
CL =50pf, RL=2kn
tpd- Propagation Delay, Negative
Going Output
200
NS
CL =50pf, RL=2kn
5-4
ITT303. ITT303H
. T___________
-L
... 1 m
Q_U_A_D_2_-_IN_P_U_T
(2 EXPANDABLE) NAND
BUFFERS
SEMICONOUCTORS
QUAD 2-INPUT
NAND BUFFERS
(2 EXPANDABLE)
Pin Configuration
16 Vee
The ITT303 is a high sink current buffer with
passive pull-up resistors on the chip. It is useful in the collector-OR configuration, as a system buffer, or as a lamp driver. For use as
a high-fan out gate, a supplemental external
pull-up resistor should be used.
ABSOLUTE MAXIMUM RATINGS
GND
Characteristics
Units
Storage Temperature Range .. -65° to +150°C
Operating Temperature Range
303H-1, 303-1 ......... -55°C to +125°C
303H-5 ................ -30°C to + 75°C
303-5 .................. -30°C to +85°C
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ............... " .... , +16.5V
Pulsed 0.1 Second ................. 18V
Input Voltage (exclusive of expanders)
303-1, 303-5 .............. - 0.5V to 16.5V
303H-1, 303H-5 ............. -0.5V to 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied to output ...... -0.5V to Vee
Sink Current, Continuous Buffers ...... 80mA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +125° ...................... 500mw
at +85° ........................ 900mw
5-5
8
0=
AS
Schematic (Each Gate)
303
r---_---~~_oVee
xo---
8.2K
SO--*--+--i4-+L
1.2K
9.1K
.--..---vO
A
'-----OGND
ITT303, ITT303H
QUAD 2-INPUT
(2 EXPANDABLE) NAND BUFFERS
ELECTRICAL CHARACTERISTICS 303-1, 303-5 Over Recommended Operating Free Air
Temperature Range
Parameter
V lH
Input High Threshold Voltage
V,L
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
1m
Input High Level Current
hL
Input Low Level Current
Icc
Power Supply Current
Min
Max
Units
6.S
V
Test Conditions
S.O
V
10.0
V
Vee=11.0V, V'L-S,OV
10H =-SOua
V
Vee=11.0V, V1H=6.SV
IOL=60.SmA
1.S
10
ua
Vee =13.0V, VR =13.0V
-2.1
mA
Vee -13.0V, VF-1.SV
49
mA
Vee = 13.0V
tpd+ Propagation Delay, Positive
Going Output .
600
NS
CL=SOpf, RL=2kf!
tpd- Propagation Delay, Negative
Going Output
200
NS
CL=SOpf, RL=2kf!
ELECTRICAL CHARACTERISTICS 303H-1, 303H-5 Over Recommended Operating Free Air
Temperature Range
Parameter
VIH
Min
Input High Threshold Voltage
Max
Units
6.S
V
S.O
Test Conditions
V
V,L
Input Low Threshold Voltage
VOH
Output High Voltage
13.0
V
Vee -14.0V, V,L-S.OV
10lI =-SOua
VOL
Output Low Voltage
1.8
V
Vee=14.0V, V'H=6.SV
IOL=60mA
IIH
Input High Level Current
10
ua
Vee = 16.0V. VD=16.0V
Input Low Level Current
-2.6
mA
Vee=16.0V, VF=1.8V
hL
Power Supply Current 303H-1
303H-5
tpd+ Propagation Delay, Positive
Going Output
40
70
Icc
tpd- Propagation Delay, Negative
Going Output
5-6
mA
mA
Vee = 16.0V
600
NS
CL=SOpf, RL=2kf!
200
NS
CL=SOpf, RL=2kf!
_
I
ITT311, ITT311 H
mm
SLAVE
FLIP-FLOP
-1--1- _ _MASTER
_
_
_
SEMICONDUCTORS
MASTER SLAVE FLIP-FLOP
Pin Configuration
The ITT311 is a universal HiNiL flip-flop. It has
sepa rate clocks which allow two-phase (dual
inhibit) operation, direct set and reset inputs,
six data inputs, and is level sensitive. It can be
operated as a J-K flip-flop by external wiring
and features active outputs.
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -6So to +1S0°C
Operating Temperature Range
311H-1, 311-1 ......... -SSOCto +12SoC
311H-S .................. 30°Cto +7SoC
311-S .................. -30°C to +8SoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ..................... , + 16.SV
Pulsed 0.1 Second ................. '18V
Input Voltage (exclusive of expanders)
311-1, 311-S .............. -O.SVto 16.SV
311H-1, 311H-S ............. -O.SVto 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied' to output ...... -O.SV to Vee
Sink Current, Continuous Buffers ...... 80mA
All Other Devices ................. 2SmA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So ...................... SOOmw
at +8So ........................ 900mw
GND
8
J-K Operation
*R Operation
I
A
B
B
L
L
Q
L
L
Q
L
H
L
L
H
L
H
L
H
H
L
H
Q
H
H
X
.
Q
H
H
Undetermined
Typical Output
Schematic Typical Input
Vcc 0----1>-----,
IN 0--W_.........1--4~
R
9.IK
6K
VCCo----J
R= S.2K on A,
B,S,R, T2
-=
R=4.IK on TI
5-7
I
A
510n
Q
ITT311, ITT311 H
MASTER SLAVE FLIP-FLOP
Single-Phase Timing
Circuit Diagram
Set-Reset Mode
DATA ENTERED
IN MASTER
MASTER
INHIBITED
~HARS:::OLD1~
L
________
O.4V
~~~~;HOLDT
,-------1 -
SLAVE
INHIBITED
DATA ENTERED
IN SLAVE
Two-Phase Timing
J-K Mode
/
'T' SET INTO MASTER
II
TI~
/
MASTER INHla'TED
~
I
T2----:71
SLAVE INHIBITED/
L-J
~
"I" TRANSFERRED TO SLAVE
ELECTRICAL CHARACTERISTICS 311-1, 311-5 Over Recommended Operating Free Air
Temperature Range
Parameter
VIH
Input High Threshold Voltage
VIL
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
IIH
Input High Level Current
Max
Units
6.5
7.0
V
V
Icc
Power Supply Current
IOH
Output Source Current
Test Conditions
A, B, T Inputs
S, R Inputs
5.0
V
10.0
V
V,,--11,OV, V'L-5.0V
lOll = -50ua
1.5
V
V,,=11.0V, VlIl=6.5V
lOT. = 12,6mA
10
20
ua
ua
V,,=13.0V, V R =13.0V
A, B, R, S, T, Inputs
T, Input
-2.1
-4.2
mA
mA
V,,=13.0V, VF=1.5V
A, B, R, S, T, Inputs
T, Input
18
mA
V,,=13.0V
mA
V,,=12V, V'L=5.0V
VoH =7.0V, VIH=6.5V
Input Low Level Current
hL
,
Min
-5.0
tpd+ Propagation Delay, Positive
Going Output
tpd- Propagation Delay, Negative
. Going Output
.
5-8
820
400
NS
NS
CL =50pf, RL=2kQ
T-' Q+
R- Q+
610
250
NS
NS
CL=50pf, RL=2kQ
T- QR- Q-
ITT311, ITT311 H
MASTER SLAVE FLIP-FLOP
ELECTRICAL CHARACTERISTICS 311H-1, 311H-5 Over Recommended Operating Free Air
Temperature Range
Parameter
Vm
Input High Threshold Voltage
V1L
Input Low Threshold Voltage
VOll
Output High Voltage
VOL
Output Low Voltage
1m
Input High Level Current
hL
Units
6.S
7.0
V
V
A, B, T Inputs
S, R, Inputs
S.O
4.8
V
V
A, B, R, S, T, Inputs
T, Inputs
13.0
V
V,,=14.0V, V1L=S.OV
lou = -SOua
1.8
V
V,,=14.0V, V'll=6.5V
IOL=1S.6mA
10
20
ua
ua
V,,=16.0V, VR =16.0V
A, B, R, S, T, Inputs
T, Input
-2.6
-S.2
mA
mA
V,,=16.0V, VF=1.8V
A, B, S, R, T, Inputs
T, Input
2S
mA
V,,=16.0V
mA
V,,::::1S.0V, VIL=S.OV
VoH =9.SV, VIH=6.SV
Input Low Level Current
Icc
Power Supply Current
lOll
Output Source Current
tpd+ Propagation Delay, Positive
Going Output
tpd-
Max
Min
Propagation Delay, Negative
GOing Output
-S.O
Test Conditions
820
400
NS
NS
C,,=SOpf, RL=2kn
T- Q+
R- Q+
610
2S0
NS
NS
CL=SOpf, RL=2kn
T- QR- Q-
5-9
_
ITT
ITT312,ITT312H
._________________D_U_A_L__J-_K_F_L_Ip_-~F_LO_P
SEMICONDUCTORS
DUAL J-K FLIP-FLOP
PIN CONFIGURATION
Two completely separated J-K flip-flops are
incorporated on one 312 chip. Each flip-flop
has its own separate clock, set, and reset inputs. The device clock is negative edge sensitive, requiring a clock fall time of 3 volts per
microsecond or faster. Active-high outputs are
provided.
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -6So to + 1S0°C
Operating Temperature Range
321H-1, 321-1 ........ -SSoC to +12SoC
H-S .................... -30° to +7SoC
-S .................... , -30°Cte +8SoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ...................... +1,6.SV
Pulsed <0.1 Second ................ 18V
Input Voltage (exclusive of expanders)
321-1, 321-S ............. -O.SV to 16.SV
321H-1, 321-HS ............ -O.SV to 18V
Input Voltage - Expanders ....... ; OV to 6.0V
Voltage applied to output., .... ~O.SVto Vee
Sink Current, Continuous Buffers ...... 80mA
All Other Devices ................. 2SmA
Output short circuit duration
to ground ,.................. Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So ...................... SOOmw
at +8So ., ... ,.,., .............. 900mw
GND
9
B
Truth Table
S-R Mode
S
R
H
H
H
L
L
H
L
L
Q
X
L
H
H
J-K Mode
K
L
L
L
H
L
H
H
H
J
X= Indeterminate state
ELECTRICAL CHARACTERISTICS 312-1, 312-5 Over Recommended Operating Free Air
Temperature Range
Parameter
VIH
Min
Input High Threshold Voltage
V,L
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
!:2
Max
Units
6.S
V
Test Conditions
S.O
V
10.0
V
V,,=11.0V, VlI.=S.OV
IOf! = -SOua
V
Vcc=11.0V, VtH=6.SV
IOL=10.S mA
1.S
5_10
Q
1
Q
L
H
Q
ITT312, ITT312H
DUAL J-K FLIP-FLOP
ELECTRICAL CHARACTERISTICS 312-1, 312-5 Over Recommended Operating Free Air
Temperature Range
Parameter
1m
Ill.
Min
Max
Units
10
20
ua
ua
-2.1
-4.2
mA
mA
30
mA
Vcc=13.0V
mA
Vcc=12V, V,L=S.OV
VoH =7.0V, VJH=6.SV
Input High Level Current
Vcc =13.0V, VF=1.SV
Input Low Level Current
Icc
Power Supply Current
10H
Output Source Current
Test Conditions
Vcc=13.0V, V R =13.0V
J, K, T Inputs
S, R Inputs
-S.O
tpd+ Propagation Delay, Positive
Going Output
tpd- Propagation Delay, Negative
Going Output
J, K, T Inputs
S, R Inputs
300
600
NS
NS
CL=SOpf, RL=2kn
T- Q+
R- Q+
230
320
NS
NS
CL=SOpf, RL=2kn
T- QR- Q-
ELECTRICAL CHARACTERISTICS 312H-1, 312H·5 Over Recommended Operating Free Air
Temperature Range
Parameter
VJH
Min
Input High Threshold Voltage
V,L
Input Low Threshold Voltage
VOH
Output High Voltage
Max
Units
6.S
V
S.O
V
13.0
V
Test Conditions
Vcc=14.0V, V' L=S.OV
1011 =-SOua
VOL
Output Low Voltage
1,11
Input High Level Current
hL
1.8
V
10
20
ua
ua
Vcc=16.0V, VR =16.0V
Power Supply Current
1011
Output Source Current
tpd+ Propagation Delay, Positive
Going Output
tpd- Propagation Delay, Negative
Going Output
J, K, T Inputs
S, R Inputs
-2.6
-S.2
mA
mA
Vcc=16.0V, VF=1.8V
J, K, T Inputs
S, R Inputs
40
mA
Vcc=16.0V
mA
Vcc =1S.0V, V,L=S.OV
VolI =9.SV, VJH=6.SV
Input Low Level Current
Icc
Vcc=14.0V, V1H=6.SV
IOL=13.0mA
-S.O
300
600
NS
NS
C,.=SOpf, RL=2kn
T- Q+
R- Q+
230
320
NS
NS
CL=SOpf, RL=2kn
T- QR- Q-
5-11
ITT312, ITT312H
DUAL J-K FLIP-FLOP
SCHEMATIC (EACH FLiP-FI,.OPI
r---~----------------------------~--os
Ro---~--~-------------r------------~
vcco---t----Hr------,--...,-...,----+-------,..------+-----~-- B. Inputs are provided so that 343's can be cascaded, enabling
the system designer to compare n - bit numbers. A strobe is also provided to disable the
unit.
r
l
INPUTS
l
r
INPUTS
j
OUTPUC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -6So to +1S0°C
Operating Temperature Range
343H-1, 343-1 ......... -SSoC to +12SoC
343H-S ................ -30°C to + 7SoC
343-S .................. -30°C to +8SoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ...................... +16.SV
Pulsed 0.1 Second ................. 18V
Input Voltage (exclusive of expanders)
343-1, 343-S .............. - O.SV to 16.SV
343H-1, .343H-S ............. - O.SV to 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied to output ...... -O.SV to Vee
Sink Current, Continuous Buffers ; ..... SOmA
All Other Devices ................. 2SmA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So ...................... SOOmw
at +8So ........................ 900mw
5-36
GND
Logic Diagram
ITT343, ITT343H
FOUR-BIT COMPARATOR
Truth Table
Typical Input
Outputs
Inputs
EIN
G,N Strobe EouT
A>B
A=B
AB
A=B
AB
A=B
AB
A=B
A L_LO_W
......_T_O_H_IG_H_IN_T_ER_F_A_C_E
-L-L ____
. SEMICONDUCTORS
DUAL LOW TO
HIGH INTERFACE
Pin Configuration
The ITT362 converts low level signals from TTL
or RTL to high level signals for H,NIL processing. Both inverting and non-inverting inputs are
available for interfacing with RTL or TTL. Only
one input should be used at a time, with the
other three being tied to Vcc or ground to remove them from the circuit.
16 Vee
15
TTU1NVI
TTUNII
RlLliNVI
RlLlNIJ
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -6So to +1S0°C
Operating Temperature Range
362H-1, 362-1 ..... ; .. -SSoC to +12SoC
362H-S ................ -30°C to + 7SoC
362-S .................. -30°C to +SSoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ..................... ' +16.SV
Pulsed 0.1 Second ................. 1SV
Input Voltage
TTL Inputs ................ -O.SV to S.OV
RTL Inputs ................ -O.SV to S.OV
Voltage applied to output ...... -O.SV to Vee
Sink Current, Continuous Buffers ...... SOmA
. All Other Devices ................. 2SmA
Output short circuit duration
to ground .......... ;........ Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So ...................... SOOmw
at +SSo ........................ 900mw
Ni,
TTL
GNO
11
'i;L
10
~~.
8
Schematic
'ccc>-~---r-------t--...,
5-42
ITT362, ITT362H
DUAL LOW TO HIGH INTERFACE
ELECTRICAL CHARACTERISTICS 362-1, 362-5 Over Recommended Operating Free Air
Temperature Range
Parameter
Min
Max
Units
Test Conditions
VIIi
Input High Threshold Voltage
VII.
Input Low Threshold Voltage
0.7
0.8
V
V
VOH
Output High Voltage
TTL Inputs
8.5
V
Vcc=11.0V
IUH =-50ua
One Input at Threshold
VOL
Output Low Voltage
TTL Inputs
1.5
V
Vcc=11.0V
IOL=10.5 mA
One Input at Threshold
1m
Input High Level Current
10
ua
Vcc=13.0V, VR=4.0V
-1.6
mA
Vcc=13.0V, VF=OAV
.10
mA
Vee=13.0V
tpd+ Propagation Delay, Positive
Going Output
400
NS
CL=50pf, RL=2kn
tpd- Propagation Delay, Negative
Going Output
335
NS
CL=50pf, RL=2kn
Icc
Power Supply Current
~
362-5
ELECTRICAL CHARACTERISTICS 362H-1, 362H-S Over Recommended Operating Free Air
Temperature Range
Parameter
Min
Max
Units
Test Conditions
Vm
Input High Threshold Voltage
TTL Inputs
V1L
Input Low Threshold Voltage
TTL Inputs
0.7
0.8
V
V
VOH
Output High Voltage
11.5
V
Voc=14.0V
10H =-50ua
One Input at Threshold
VOL
Output Low Voltage
1.8
V
Vee=11.0V
IOL=10.5 rnA
One Input at Threshold
1m
Input High Level Current
TTL Inputs
10
ua
Vee = 16.0V, VR=4.0V
hL
Input Low Level Current
TTL Inputs
-1.6
rnA
Vee=16.0V, VF=OAV
Icc
Power Supply Current
13.0
rnA
Vee = 16.0V
tpd+ Propagation Delay, Positive
Going Output
400
NS
CL=50pf, RL=2kn
tpd- Propagation Delay, Negative
Going Output
335
NS
CL=50pf, RL=2kn
V
5-43
~
362H- 5
ITT362, ITT362H
DUAL LOW TO HIGH INTERFACE
RTL INPUT SPECIFICATIONS FOR 362, 362H
Max
Units
Vm
Parameter
Input High Threshold Voltage
1.01
0.95
0.85
0.70
0.675
V
V
V
V
V
V1L
Input Low Threshold Voltage
0.71
0.6
0.5
0.38
0.32
1m
Input High Level Current
Min
0.495
0.460
0.440
0.470
0.470
Test Conditions
362-1,362H-1@-55°
362-5, 362H-5@-30°
362-1, 362H-1, 362-5,
362H-5@+25°C
362-5,362H-5@+70/+75°
362-1, 362H-1@125°
362-1, 362H-1@-55°
362-5, 362H-5@-30°
362-1, 362H-1, 362-5,
362H-5@+25°C
362-5, 362H-5@+70/85°
362-1, 362H-1@125°
rnA
rnA
rnA
rnA
rnA
362-1,362H-1@-55°
362-5, 362H-5@-30°
362-1, 362H-1, 362-5,
362H-5@+25°C
362-5, 362H-5@+70/85°
362-1, 362H-1@125°
Inputs at Vm,
Vcc-13V for
362-1, 362-5,
Vcc-16V for
362H-1, 362H-5
!xL
Input Low Level Current
10
5-44
uA
Inputs at V1L
Vcc=13V for 362-1,362-5
Vcc=16V for 362H-1, 362H-J
ITT
.....
----ITT370, ITT370H
QUAD D FLIP-FLOP
SEMICONDUCTORS
QUAD D FLIP-FLOP
Pin Configuration
Four D-type flip-flops utilizing a common clock
line make up the 370. Each flip-flop has complimentary passive pull up outputs with a single
D input. This circuit is ideal as a quad latch
for temporary storage of 4-bit binary numbers.
Data is transferred from D inputs to outputs
when the clock line is low. With the clock line
high, output data is held and D inputs are
ignored.
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -65° to +150°C
Operating Temperature Range
370H-1, 370-1 ......... -55°C to +125°C
370H-5 ................ -30°C to +75°C
370-5 ................. -30°C to +85°C
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ..................... , +16.5V
Pulsed 0.1 Second ................. 18V
Input Voltage (exclusive of expanders)
370-1, 370-5 ............. - 0.5V to 16.5V
370H-1, 370H-5 ............ -0.5V to 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied to output ...... -0.5V to Vee
Sink Current, Continuous Buffers ..... , 80mA
All Other Devices ................. 25mA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +125° ...................... 500mw
at +85° ........................ 900mw
TRUTH TABLE
C
D
Qn+
1
1
1
0
1
0
Qn
Qn
1
0
0
1
0
Schematic
5-45
ITT370, ITT370H
QUAD D FLIP-FLOP
ELECTRICAL CHARACTERISTICS 370-1, 370-5 Over Recommended Operating Free Air
Temperature Range
Parameter
Min
VlH
Input High Threshold Voltage
V1L
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
IlH
Input High Level Current
hL
Test Conditions
Max
Units
6.5
V
5.0
V
10.0
V
Vec-11.0V, V'L-5.0V
lOR = -40ua, VlH=6.5V
1.5
V
Vec=11.0V, Vm=6.5V
IOL=8.4mA
10
20
ua
ua
Vee = 13.0V, VR =13.0V
C Input
D Inputs
-2.1
-4.2
rnA
rnA
Vec =13.0V, VF=1.5V
C Input
D Inputs
Input Low Level Current
38
rnA
Vee =13.0V
tpd+ Propagation Delay, Positive
Going Output
500
NS
CL=50pf, RL-2kO
tpd- Propagation Delay, Negative
Going Output
500
NS
CL-50pf, RL-2ko
Icc
Power Supply Current
ELECTRICAL CHARACTERISTICS 370H-1, 370H-5 Over Recommended Operating Free Air
Temperature Range
Parameter
VlH
Min
Input High Threshold Voltage
V1L
Input Low Threshold Voltage
VOR
Output High Voltage
VOL
Output Low Voltage
IlH
Input High Level Current
Max
Units
6.5
V
Test Conditions
5.0
V
13.0
V
Vec=14.0V, V'L=5.0V
IOH·=.40ua, VlH=6.5V
1.8
V
Vec=14.0V, Vm=6.5V
IOL=10.4mA
10
20
ua
ua
Vee=16.0V, VR =16.0V
C Input
D Inputs
-2.6
-5.2
rnA
rnA
Vee=16.0V, VF=1.8V
C Input
D Inputs
40
48
rnA
rnA
Vee-16.0V
tpd+ Propagation Delay, Positive
Going Output C- Q+
500
NS
CL=SOpf, RL=2ko
tpd- Propagation Delay, Negative
Going Output C- Q+
500
NS
CL=SOpf, RL=2kO
hL
I·cc
Input Low Level Current
Power Supply Current
370H-1
370H-S
5-46
ITT
----ITT371, ITT371 H
DECADE COUNTER
SEMICONDUCTORS
DECADE COUNTER
Pin Configuration
The ITT371 HLL MS1 counter generates BCD
on its outputs. It has direct set inputs for each
of its four internal f1ip·flops and a common
reset. Two clock inputs are provided, facilitat·
ing the input ENABLE function. A ninth count
output is provided as a carry output for cascad·
ing 371's so a decimal number of any size
may be generated. The passive outputs are
ideal inputs to the 380 Series BCD decoders.
The 371 is level sensitive, counting as the clock
goes low. Holding either clock low will inhibit
the count sequence. Direct set or reset is accomplished by switching the desired input high.
All unused direct set and reset inputs must be
grounded.
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. -65· to +150·C
Operating Temperature Range
371H·1,371-1 ......... -55·C to +125·C
371H-5 ................ -30·C to +75·C
371-5 .............•... -30·C to +85·C
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum .......• 300·C
Supply Voltage
Continuous ............ " . " .•... +16.5V
Pulsed 0.1 Second ................. 18V
Input Voltage (exclusive of expanders)
371-1, 371-5 .............. -D.5V to 16.5V
371H-1, 371H-5 ............ -0.5V to 18V
Input Voltage - E~panders ........ OV to 6.0V
Voltage applied to output ...... -0.5V to Vee
Sink Current, Continuous Buffers ...... 80mA
All Other Devices ...............•. 25mA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +125· ...................... 500mw
at +85· ....................•.. 900mw
Logic Diagram
----r'
CP1o-........
r---OS1
Jl---'~-o
.-----iI--OS2
R
r---i,--OS4
...-r-.,:--'f"""' r-"""'::""f---004
i~co
o
5-47
ITT371, ITT371 H
DECADE COUNTER
TRUTH TABLE
CP1 0r
0, O.
CP, 0,
O. 0,0.
TYPICAL INPUT
TYPICAL OUTPUT
0
0
0
0
0
0
Vee
Vee
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
ROUT
RIN
0
0
1
0
0
0
1
1
0
0
0
0
_ _ _- - v OUTPUT
0
0
1
1
0
0
0
1
1
0
1
O.
1
0
0
0
0
Q
1
0
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
Input
Output
ROUT
1
0
0
1
0
0
1
1
0
0
1
0
5 Kn Typ.
CP1 CP 2
01 02 9.1 Kn Typ.
1
0
1
0
0
1
5 Kn Typ.
Reset
03
O. 9.1 Kn Typ.
0
1
0
1
1
1
20
Kn
Typ.
CO
All Sets
1
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
1
1
1
0
ELECTRICAL CHARACTERISTICS 371·1, 371·5 Over Recommended Operating Free Air
Temperature Range
+
Parameter
Vm
Input High Threshold Voltage
V1L
Input Low Threshold Voltage
VOH
Output High Voltage
Min
Max
Units
6.S
V
S.O
Test Conditions
V
V•• =11.0V, V1L=S.OV
Vm=6.SV
10.0
V
C Output
IOH=-20p.A
10.0
V
Q Outputs
IHo=-SOuA
VOL
Output Low Voltage
V.c =11.0V, Vm=6.SV
V1L=S.OV
1.S
V
C Output
IOL=4.2mA
1.S
V
Q Outputs
IOL=1Q.SmA
1m
hL
Input High Level Current
V•• =13.0V, VR =13.0V
20
ua
10
CP Inputs
ua
R Input
S
ua
S Inputs
-4.2
-2.1
-1.0S
mA
mA
mA
Input Low Level Current
S-48
V. c =13.0V
CP Inputs
R Input
S Inputs
ITT371, ITT371 H
DECADE COUNTER
ELECTRICAL CHARACTERISTICS 371-1, 371-5 Over Recommended Operating Free Air
Temperature Range
Parameter
Min
Max
Units
Test Conditions
Icc
Power Supply Current
41
tpd+ Propagation Delay, Positive
Going Output
mA
CL=50pf, RL=2kfl
tpd- Propagation Delay, Negative
Going Output
800
NS
C- Q+
600
NS
S+ Q+
CL=50pf, RL=2kfl
300
NS
C- Q-
200
NS
R+ Q-
ELECTRICAL CHARACTERISTICS 371H-1, 371H-5 Over Recommended Operating Free Air
T emperature Range
Parameter
Min
Units
Test Conditions
Max
VIH
Input High Threshold Voltage
V1L
Input Low Threshold Voltage
VOH
Output High Voltage
VOL
IrH
IrL
Icc
6.5
5.0
V
V
13.0
V
13.0
V
Output Low Voltage
V" = 14.0V, V1L = 5.0V
Vm=6.5V
C Output
IOH=-20p.A
Q Outputs
IOH=-50ua
Vcc=14.0V, VIL=5.0V
Vm=6.5V
C Output
IOL=5.2mA
1.8
V
1.8
V
20
ua
CP Inputs
10
ua
R Input
5
ua
S Inputs
-5.2
mA
CP Inputs
-2.6
mA
R Input
-1.3
mA
S Inputs
40
mA
Vcc =16.0V
53
mA
800
NS
C- Q+
600
NS
Input High Level Current
Q Outputs
IOL=13.0mA
Vcc=16.0V, VR -16.0V
Input Low Level Current
Power Supply Current
tpd+ Propagation Delay, Positive
Going Output
l
I
371 H-1
371 H-5
CL=50pf, RL=2kfl
tpd- Propagation Delay, Negative
Going Output
5-49
300
NS
S+ Q+
CL=50pf, R1.=2kfl
C- Q-
200
NS
R+ Q-
_I
ITT372, ITT372H
mm
.L.L ___D_IV_ID_E_B_Y_1_6_(_H_EX_A_D_E_C_IM_A_U..._C_O_U_N_T_E_R
SEMICONDUCTORS
DIVIDE BY 16 (HEXADECIMAL)
COUNTER
Pin Configuration
The ITT372 is identic\,!1 to the ITT371 except
its outputs are coded in the standard 4-bit
binary (1-2-4-8) code.
R
16
1
Vcc
r - - - - - - - - I 15 CP2
Operation of the 372 is identical to that of the
371. Internal construction produces divide-bysixteen operation.
14
01
S1
02
52
04
54
58
08
co
08
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Storage Temperature Range .. ~6So to +1S0°C
Operating Temperature Range
372H-1,372-1 .......... -SSoC to +12SoC
372H-S ................ -30°C to +7SoC
372-S ................ -30°C to +8SoC
Lead Temperature, 1/16 inch from
case, 60 seconds Maximum ........ 300°C
Supply Voltage
Continuous ...................... + 16.SV
Pulsed 0.1 Second ................. 18V
Input Voltage (exclusive of expanders)
372-1, 372-S ............ - O.SV to 16.SV
372H-1, 372H-S ............ - O.SV to 18V
Input Voltage - Expanders ........ OV to 6.0V
Voltage applied to output ...... -O.SV to Vee
Sink Current, Continuous Buffers ...... BOmA
All Other Devices ................. 2SmA
Output short circuit duration
to ground ................... Continuous
(Not more than 1 output shorted simultaneously)
Maximum package power dissipation (free air)
at +12So...................... SOOmw
at +8So ....................... 900mw
GND
7 H---iH---4-~
L-~===j-l
8
Logic Diagram
CP10--_-----i
9
co
. - - - - { ) 51
,1---'''---001
.-----1f--052
t---+-'--"" J------r-~~-{)02
CP20--#---=I
.--f--054
.--I---{) 58
A -Hl---r--..
B
C
--f+-'--'/
A--I--I-...-......
5-50
J1-,,+--o08
ITT372, ITT372H
DIVIDE BY 16 (HEXADECIMAL) COUNTER
Truth Table
Typical Input
Vee
INPUT
CP1 CP2
RESET
ALL SETS
RIN
5 Kn TYP.
5 KU TYP.
20 Kn TYP.
Typical Output
vee
~""'-----!------'
INPUTS
~A' ~OUTPUT2W
2A2
'
supply this reference voltage; however, methods given here will be limited to the discussion
of fundamental design considerations. These
sense amplifiers are recommended for use in
systems requiring threshold voltage levels of
±15 to ±40mV.
A simple method of generating the reference
voltage is the use of a resistor voltage divider
from either the positive (Vcc+) or negative
(Vcc-) voltage supplies. See Figure G. This
type of voltage divider may be used to supply
an individual reference amplifier or to supply
a numbr of paralleled reference amplifiers. The
bias current required at the reference amplifier
input is low (normally 30,..A) therefore, voltage dividers of this type may normally be
operated with very low current requirements.
In noisy environments, the use of a filter capacitor across the inputs is recommended. By
locating the capacitor as close to the device
terminals. as possible, noise and stray signals
will be presented common-mode to the reference amplifier and thus be rejected.
STReBe 52
RI
Figure F
ITT7528/ITT7529 Logic Diagram
Vee+ 0
Ill>:
R2
Logic:
W = AS for ITT7528 and ITT7529
ITT75234, ITT75235, ITT75238, ITT75239
Circuits
~
__
REFERENCE
-
AMPLIFIER
Figure G
These dual sense amplifier circuits are the
same as ITT7524, ITT7525, ITT7528, and
ITT7529, respectively, except that an additional stage has been added to th'e output gate
to provide an inverted output. Compared to
using a separate gate for inversion, not only
is. package count reduced, but less propagation delay is added.
Reference Voltage Considerations
These sense amplifiers feature a variablethreshold voltage level with simultaneous adjustment of both sense channels or both sense
amplifiers by a single reference voltage. The
operating threshold voltage level of the input
amplifiers is established by and is approximately equal to the applied reference input
voltage, Vref' Several methods may be used to
Input Line Layout Considerations
Input sensitivity and device speed require
adequate precautions in the routing of signal
input and reference lines to prevent noise pickup. Bypassing of supply and reference inputs
at the device with low-inductance disc ceramic
capacitors, and use of a good ground plane
to separate strobe and output lines from sense
and reference input lines, is recommended.
6-4
ITT7520
SENSE AMPLIFIERS
Sense-input Termination Resistor
Considerations
Logic Input Current Requirements
Termination resistors are intentionally omitted
from the sense-input terminals so the desigller
may select resistor values which will be compatible with the particular application. Matched
termination resistors, (RT, Figure H), normally
in the range of 25 n to 200 n each, are required not only to terminate the sense line in
a desired impedance but also to provide a
doc path for the sense-input bias currents.
Careful matching of the resistor pairs should
be observed or effective common-mode rejection will be reduced.
Logic input current requirements are specified
at worst-case power-supply conditions over the
operating free-air temperature range ofO°C
to 70°C. The logic input currents are identical.
to and compatible with TTL digital integrated
circuits. Each logic input of •. the multipleemitter input transistors reqolres no more
than a 1.6-mA flow out of the inputata
low logic level. Each input .emitterrequires
current into the input when it is at a highlogic level. This current is 40 vA maximum.
current into the input terminals are specified .
as positive values. Ar~ows on tlie doc test circuits indicate the actual direction 01.' current
flow.
Absolute Maximum Ratings (over free-air
temperature range unless otherwise noted)
Supply voltages (see Note 1): .
.
'.
Vcc+ ........ ; ••...••.•.•.........•.• 7V
Vcc - ..................•....•.... ; .• -7V
Differential input voltage, VrD or Vr~£ ...... ±5V
Voltage from any input to ground
(see Note 2) ........................ 5.5V
Operating free-air temperature
'.'
range, TA ...........•..•.•. C·C to 70·C
Storage temperature range, T.te.-,55·C to 150·C
Figure H
Recommended Operating Conditions
Output Drive Capability
The output circuits of these sense amplifiers
feature the ability to sink or supply load current. This capability permits direct use with
both TTL- and DTL-type loads. The open-collector output of the ITT1522/1TT7523 circuit
may be connected to similar outputs to perform
the wire-AND function. Load currents (out
of the output terminal) are specified as negative values. Arrows on the doc test circuit indicate the actual direction of current flow.
Min ~om' Max Unit
Vcc+ (see Note 1).... 4.75
5
5.25
V
Vcc - (see Note 1) .... -4.75 -5 -5~25, V
Vref ••••••.•••••••••
15 ,
40mV'
NOTES:
1. These voltage values are ,with' respect to
network ground terminal.
2. Strobe and gate input voltages must be,
zero or positive with respect to'network.ground
terminal.
6-5
ITT7520, ITT7521
_I
mm.. ____D_U_A_L
-_C_H_A_N_N_E_L_S_E_N_S_E_A_M_P_Ll_F_IE_RS
.L.L
WITH
COMPLIMENTARY OUTPUTS
SEMICONOUCTORS
DUAL-CHANNEL SENSE AMPLIFIERS
WITH COMPLEMENTARY OUTPUTS
TRUTH TABLE
Inputs
A
B
G.
X
X
L
H
X
X
H
L
X
X
L
L
X
X
X
X
L
X
X
Gz
X
S
S8
X
X
X
X
X
X
H
L
L
X
L
H
H
H
L
L
L
L
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
L
X
L
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(Top VIEW)
Outputs
y
Z
§.Z
§.Z
Gz
AI
H
H
H
H
H
A2
fBi
INPUTS
Definition of Logic Levels
H
Input
A or S*
Vm
;;::'
Any G or S VI;;::' VIH min V,
GATE
6
la2
GATE
X
L
VT max VID
STROBF
2
INPUTS {
~ VT min Irrelevant
~
VI!. max Irrelevant
POSiTIVE LOGIC:
y. Gy+A'S A +B'Sa
f · Gi!+Y
z· GZ+Gy(A+~AH!i+~BI
regardless of which terminal of each pair is
positive with respect to the other.
* A and S are differential voltages (V ID ) between A 1 and A2 or S1 and 82, respectively.
For these circuits, VII) is considered positive
Schematic
INPUTS{AI
A2
OUTPUT Z
STROBE S A ~-+--+t---j-+-,
INPUTS {Bl
B2
~
~--~-!..
Gz
STROBESB~-+_ _ _--j-+-,
Vcc_
OUTPUT
y
6-6
ITT7520, ITT7521
DUAL-CHANNEL SENSE AMPLIFIERS
WITH COMPLIMENTARY OUTPUTS
= 5 V, Vcc -
ELECTRICAL CHARACTERISTICS (unless otherwise noted Vcc+
TA = DoC to 70°C)
Parameter
VT
Test.
Fig.
Differential Input threshold
voltage
1
Min
Typ** Max Unit
15 (20}19
mV V,.,.,
15
mV
35)36
40 (45j44
mV V".,
40
mV
33
VlCr
Common-mode Input firing
voltage
lIn
Differential-Input bias current
Differential-Input offset
current
47
30
VIH
High-level Input voltage
(strobe and gate inputs)
3
VIr.
Low-level input voltage
(strobe and gate inputs)
3
VOH
High-Level output voltage
2.4
0.25
4
-1
Low-level input current
(strobe and gate inputs)
4
los(y)
Short-circuit output
current into Y
5
los(z)
Short-circuit output
current into Z
5
Icc+
Supply current from Vcc+
0.4
V Vcc+ - 4.75 V,
Vee - =. -4.75 V,
10L = 16 mA
40
p.A Vcc+ = 5.25 V,
Vce - = -5.25 V
VIH = 2.4 V
1
mA Vec+ - 5.25 V,
Vcc - = -5.25 V
VIH = 5.25V
-1.6
mA Vcc+ - 5.25V,
Vcc - = -5.25 V
0.4 V
V1L
-3
-5
mA Vec+ = 5.25 V,
Vce - = -5.25 V
-2.1
-3.5
=
28
35
-14
.-'
-18
0
Supply current from Vcc -
Icc -
mA
Vec+ = 5.25 V,
Vce -5.25 V
=
mA Vec+
Vec TA
¥
5 V, Vcc - -
-5 V, TA -
Numbers in parenthesis apply to 5520 or 5521 as indicated.
6-7
=
=
=
mA Vec+
5.25 V,
vce - -5.25 V
TA
25 C
6
•• All typical values are at Vcc+ -
I 5521
ITT7521 / 5521
V Vce+ - 4.75 V,
Vcc - == -4.75 V,
10H = -400 ItA
4
High-level input current
(strobe and gate inputs) .
hL
ITT7521
V
0.8
3
IIH
ITT7520 (5520)
V
2
Low-level output voltage
=40 mV
p.A Vee+ = 5.25 V,
Vee - = -5.25 V,
Vm = 0
3
Vor.
ITT7520 (5520) ¥
p.A Vee+ = 5.25 V,
Vee - = -5.25 V, ( 5520/21)
Vm = 0
75
(100)
3
2
=15mV
V V,." = 40 mV
Common-mode Input pulse:
t,= 15 ns,
t, ~ 15 ns
tw = 50 ns
±2.5
2
ho
Test Conditions
1/10111
8
22
-5V,
25"C
= 5.25 V,
= -5.25 V
= 25 C
ITT7520, ITT7521
DUAL-CHANNEL SENSE AMPLIFIERS
WITH COMPLIMENTARY OUTPUTS
SWITCHING CHARACTERISTICS, Vcc+
= 5 V, Vcc - = -5V,
Propagation Delay Times
Symbol
From Input
tPLH(OY)
A1-A2 or
To Output
B1-B2
Y
tPHL(OY)
A1-A2 or
tPLH(OZ)
B1-B2
Z
tPHL(oz)
tPLH(SY)
Strobe A or B
Y
tPHL(SY)
tPLH(SZ)
Strobe A or B
Z
tPHL(SZ)
tPLH(GY,
y)
Gate Gy
Y
tPHL(GY, Y)
tPLH(GY, z)
Gate Gy
Z
tPHL(GY, z)
tPLH(GZ, z)
Gate Gz
Z
tPHL(GZ, z)
Test
Fig.
25
32
32
32
Max Unit
40
ns
30
ns
35
55
15
39
33
ns
ns
15
25
ns
ns
30
15
10
=
Min
5 V, Vcc Typ
CL
= 15 pF, RL = 288 {)
CL
= 15 pF, RL = 288 {}
CL
= 15 pF, RL = 288 {)
CL
= 15 pF,RL = 288 {)
CL
= 15 pF, RL = 288 {)
CL
= 15 pF, RL = 288 {)
CL
= 15 pF, RL = 288 {)
ns
15
34
ns
55
20
Test Conditions
ns
35
10
33
= 25°C
ns
30
32
ns
20
20
TYPICAL RECOVERY AND CYCLE TIMES, Vcc+
Parameter
Min Typ
100 pF, TA
ns
ns
20
ns
= -5 V, C
ext ;;:;;:
100 pF, fA
= 25°C
Max Unit Test Conditions
torD
Differential-input overload
recovery time (see Note 5)
20
ns. Differential Input Pulse:
VlD
2 V, Ir
It = 20 ns
torC
Common-made-input overload
recovery (see Note 6)
20
ns Common-Made-Input Pulse:
VIC
± 2 V; tr .It
20 ns
tcyc(mln)
Minimum cycle· time
200
NOTES:
5. Differential-input overload recovery lime
is the time necessary for the device to recover·
from the specified common-made-input overload signal prior to the strobe-enable signal.
=
=
=
= =
ns
6. Common-made-input overload recovery time
is the time necessary for the device to recover
from the specified common-made-input overload signal prior to the strobe-enable signal.
6-.8
-
ITT7522, ITT7523
DUAL-CHANNEL SENSE AMPLIFIERS
ITT- - - - SEMICONDUCTORS
DUAL-CHANNEL SENSE AMPLIFIERS
DUAL -IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
TRUTH TABLE
A
L
L
X
X
X
H
X
B
L
X
L
X
X
X
H
Inputs
G
H
H
H
H
L
X
X
5,[
5Ji
X
X
X
L
X
L
X
X
H
L
L
X
H
X
Output
Y
H
H
H
H
L
L
L
Cext
vcc+
rAI
STROBE
SA
LA2
GATE
-V,ef
GND
INPUTS
G
2
OUTPUT
+v,ef
Definition of Logic Levels
r
lB2
RL
BI
INPUTS
X
L
Vm ;;?: VT max Vm :::;; VT min Irrelevant
Any G or S V,;;?: VIH min V,:::;; V,L max Irrelevant
Input
A or 8*
Z
STROBE
SB
H
GND
Vcc-
I
POSITiVE LOGIC:
* A and 8 are differential voltages (V m ) )between A 1 and A2 or 81 and 82, respectively.
For these circuits, VIIJ is considered positive
Schematic
regardless of which terminal of each pair is
positive with respect to the other.
Vcc+
,
v,,, {
-
{
A1
INPUTS
RL
A2
OUTPUT Y
STROBE A
{
GNO 2
61
INPUTS
B2
STROBE B
Vcc_
6-9
ITT7522, ITT7523
DUAL-CHANNEL SENSE AMPLIFIERS
ELECTRICAL CHARACTERISTICS
(unless otherwise noted Vcc+ = 5 V, Vcc - = -5 V, TA = QOC to 70°C)
Test
Min Typ**Max Unit Test Conditions
Parameter
Fig.
~0)11 15 (20)19 mV Vref=15 m'll ITT7522 (5522i*
VT
Differential input threshold
voltage (see Note 3, page 17)
8
7
(35)36
ITT7,523/5523
15
22 mV
40(45)44 I mV Vref =40mV ITT7522 (55 22 )
40
33
VICF
Common-mode input firing
voltage (see Note 4, page.17)
±2.5
lIB
Differential-input bias current
30
47
ITT7523 / 5523
mV
=
VIR
V Vrel = 40 mY, VI (S)
Common-mode input pulse:
tr ~ 15 ns,
tf ~ 15 ns,
tw
50 ns
=
2
lro
Differential-input offset current
75
~OO)
/LA Vcc+ = 5.25 V,
Vce -5.25 V, (5522/23)
VID
0
p.A
3
2
=
=
Vce+ = 5.25 V,
Vee - = -5.25 V,
V =0
ID
VIR
High-level input voltage
(strobe and gate inputs)
8
V1L
Low-level input voltage
(strobe and gate inputs)
8
VOH
High-level output voltage
V
2
0.8
2.4
=
=
V VeN
4.75 V,
Vee -4.75 V,
10H = - 400 /LA
4
8
VOL
0.25
Low-level output voltage
0.4
B
IIR
High-level input current
(strobe and gate inputs)
9
IlL
10H
Low-level input current
(strobe and gate inputs)
High-level output current
Short-current output current
11
-2.1
. • Numbers in parenthesis apply to 5522 or 5523 as indicated.
6-10
=
=
=
Vec+ = 5.25 V,
Vcc - = -5.25 V,
VIR = 2.4 V
Vee+ = 5.25 V,
Vee - = -5.25 V,
VIR = 5.25 V
Vec+ = 5.25 V,
Vcc - = -5.25 V,
VIL = 0.4 V
Vce+ = 4.75 V,
Vee- = -4.75 V,
Vo = 5.25 V
Vee+ = 5.25 V,
Vcc- = -5.25 V
V Vcc+
4.75 V,
Vcc -4.75 V,
10L
16 mA
40
/LA
1
mA
-1 -1.6
mA
250
/LA
9
10
los
V
-3.5' mA
ITT7522, ITT7523
DUAL-CHANNEL SENSE AMPLIFIERS
ELECTRICAL CHARACTERISTICS (continued)
5 V, Vcc -5 V, TA
O°C to 70°C)
(unless otherwise noted Vcc+
Test
Fig.
Parameter
Min Typ** Max Unit Test Conditions
=
=
Icc+
Supply current from Vcc+
Icc-
Supply current from Vcc -
=-
27
36
mA
-15 -18
mA
6
6
•• All typical values are at Vcc+
= 5 V, Vcc - =
-5 V, TA
= -5 V, C
SWITCHING CHARACTERISTICS,Vcc+ = 5 V, VccPropagation Delay Times
Symbol
From Imput
tPLH(n)
A1-A2 or 81-82'
Y
Strobe A or 8
Y
; To Output
tpHL(n)
tPLH(S)
tPHL(S)
tPLH(G)
Gate
Test
Fig.
ext ;;;:
100 pF, TA
= 25°C
Min Typ Max Unit Test Conditions
ns Q = 15 pF, RL - 2880
20
35
30
45
35
20
40
15
TYPICAL RECOVERY AND CYCLE TIMES, Vcc+ =
5 V, Vcc-
25
CL = 15 pF,
RL =2880
CL = 15 pF,
RL = 2880
ns
ns
10
36
ns
ns
20
y.
tPHL(G)
= 25°C
=
=
=
Vcc+ = 5.25 V,
Vcc- = -5.25 V,
TA = 25°C
Vcc+
5.25 V,
Vcc -5.25 V.
TA
25°C
ns
= -5 V, C
ext ;;;:
100 pF, TA
=
25°C
- --
Parameter
torn
Typ
Min
Differential-input overload
recovery time (see Note 5)
torc
Common-mode-input overload
recovery (see Note 6)
teye(min)
Minimum cycle time
NOTES:
5. Differential-input overload recovery time
is the time necessary for the device to recover
from the specified common-mode-input overload signal prior to the strobe-enable signal.
Max Unit
20
ns
20
ns
200
ns
Test Conditions
Differential Input Pulse:
VlD = 2 V, tr
tE = 20 ns
=
Common-Mode Input Pulse:
VIC = ±2V, tr = tf = 20 ns
6. Common-mode-input overload recovery time
is the time necessary for the device to recover
from the specified common-mode-input overload signal prior to the strobe-enable signal.
6-11
_I
mm
ITT7524, ITT7525
DUAL SENSE AMPLIFIERS
~~
SEMICONDUCTORS ------------....;...;......;.;.;,;.;..;.;.;...;.;.;.;.;.
DUAL -IN-LINE 'PACKAGE
PIN CONFIGURATION '
(TOP VIEW)
DUAL SENSE
AMPLIFIERS
TRUTH TABLE
INPUTS
A
S
H
H
L
X
OUTPUT
W
H
X
L
L
L
Definition of Logic Levels
Input
A*
S
H
VT
VID ;;;:: VT max
VI;;;:: VIR min VI :::;; Vrr.
:::;;
'---~ II
X
L
VID
min
max
Irrelevant
NC
Irrelevant
GND
I
* A is a differential voltage (VIo) between A1
and A2. For these circuits, VIo is considered
positive regardless of which terminal is positive
with respect to the other.
'
POSITIVE LOGIC:
W =AS
NC - NO INTERNAL CONNECTION
Schematic
V~+~--------~----~------~
J----+---------+--o Cex!
,
{1A1
INPUTS
1A2
o---t-----H-------t--W
OUTPUT 1W
STROBE 2S ~--t--------=+=p
VCC_
OUTPUT 2W
STROBE 1S
'2A1
INPUTS
~fOBE
{
2A2
'----+-~_o
6-12
GNO 2
ITT7524, ITT7525
DUAL SENSE AM PLiFIERS
ELECTRICAL CHARACTERISTICS (unless otherwise noted Vee
O"C to 70'C)
T,
t
= 5 V,
-5 V,
V('('-
Test
Fig.
Parameter
V"
Differential-input threshold
voltage (see Note 3, page 17)
Min
12
*
15(20)19
15
8
(35)35
33
VIC'jo'
Common-mode input firing
voltage (see Note 4, page 17)
Max Unit Test Conditions
Typ*
(101)11
22
= 15 mV
mV V,·,.r
ITT7524( 5524 )*
ITT7525/ 5525
mV
40 (45)44
mV VI'!.f = 40",V
ITT7524{ 5524 )
40
mV
ITT7525/ 5525
47
±2.5
V V",.r
= 40 mY,
=V
VI(S)
IH
Common-Mode Input Pulse:
t,. ~ 15ns,
t, ~ 15 ns,
tw
50 ns
=
lIB
110
Differenti ai-input bias
current
2
.Differential-input offset
current
2
30
-3
High-level input voltage
(strobe inputs)
13
VIL
Lov-Ievel input voltage
(strobe inputs)
13
VOH
High-level output voltage
VIII
75
(100)
",A
2
V
0.8
2.4
4
Low-level output voltage
V
0.25
0.4
V
40
p.A
1
mA
13
IIH
=
=
=
Vcc+ = 4.75 V,
Vcc - = -4.75 V.
10L = 16 mA
Vcc+ = 5.25 V,
Vcc - = -5.25 V.
VIII = 2.4 V
Vcc+ = 5.25 V,
Vcc- = -5.25 V.
V = 5.25 V
Vcc+ = 5.25 V,
Vcc - = -5.25 V.
VIL = 0.4 V
V Vcc+
4.75 V.
Vcc-4.75 V,
10H
-400 p.A
13.
VOL
=
=
=
Vcc+ = 5.25 V.
Vcc - = -5.25 V.
Vm = 0
p.A Vcc+
5.25V.
-5.25 V. (5524/25)
Vcc Vm
0
High-level input current
(strobe inputs)
·14
IH
IrL
Low-level input current
(strobe inputs)
los
Short-circuit output current
Icc+
Supply current from Vcc+
-1
-1.6
mA
-3.5
mA Vcc+ - 5.25 V.
Vcc -5.25 V
40
5.25 V,
mA Vcc+
Vcc -5.25 V,
TA
25'C
mA Vcc+
5.25 V,
Vcc -5.25 V,
TA = 25'C
14
15
-2.1
25
6
Icc -
Supply current from Vcc -
-15
-
6
~* All typical values are at Vcc+
= 5 V,
Vcc -
= - 5 V.
TA
= 25'C.
"Numbers in parenthesis apply to 5524 or 5525 as indicated
6-13
18
=
=
=
=
=
=
ITT7524, ITT7525
DUAL SENSE AMPLIFIERS
SWITCHING CHARACTERISTICS, Vcc+
Propagation Delay Times
Symbol
From Input
tl'LH(n)
A1-A2
To Output
W
hHL(n)
tpLH(S)
Strobe
= 5 V,
Vcc -
Test
Fig.
Min
= -5 V,
15
30
5 V, Vcc Typ
CL
= 15
pF,
-
288
n
RL -
288
n
RL
ns
CL - 15 pF,
ns
20
Min
ns
ns
20
37
Parameter
40
25
37
TYPICAL RECOVERY AND CYCLE TIMES, Vcc+
= 25°C
Typ Max Unit Test Conditons
W
tpHL(s)
Coxt ;?! 100 pF, TA
= -5V,
Cext ;?! 100 pF, TA
= 25°C
Max Unit Test Conditions
Differential-input overload
recovery time
(see Note 5)
20
ns
Differential Input Pulse:
VII)
2 V,
te
tf
20 ns
t orc
Common-mode-input
overload recovery time
(see Note 6)
20
ns
Common-Mode Input Pulse:
VIC
±2V, te
tf
20 ns
tcyc(min)
Minimum cycle time
200
ns
tOI'D
NOTES:
5. Differential-input overload recovery time
is the time necessary for the device to recover
from the specified common-mode-input overload signal prior to the strobe-enable signal.
=
=
= =
= =
6. Common-mode-input overload recovery time
is the time necessary for the device to recover
from the specified common-mode-input overload signal prior to the strobe-enable signal.
6-14
ITT7528, ITT7529
_I
rI1m _____D_U_A_L_S_E_N_S_E
_A_M_P_L_IF_I_ER_S_W_I_T_H
.1-.1PREAM PLiFIER TEST POINTS
SEMICONDUCTORS
DUAL SENSE AMPLIFIERS
WITH PREAMPLIFIER TEST POINTS·
TRUTH TABLE
INPUTS
A
S
H
H
L
X
L
X
DUAL-IN-LiNE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
OUTPUT
W
H
L
L
Definition of logic Levels
Input
A*
S
L
H
X
VID ~ VT max VID ~ VT min Irrelevant
VI ~ VlH min VI ~ V1L max Irrelevant
+V,ef
* A is a differential voltage (ViD) between A1
and A2. For these circuits, VlD is. considered
positive regardless of which terminal is positive
with respect to the other.
II
POSITIVE LOGIC:
W=AS
Schematic
vcc+o-----~--~--__,
TEST POINT IP
INPUTS
,
{
.
o--'--f==--H---==:=:F1T
'A'
lA2
STROBE IS
<>---t---t-+--++--'
OUTPUT 1W
TEST POINT- 2P o---+--H----f,
INPUTS {
2AI
2A2
STROBE 2S
~::t===~:S::/:b::!fi
6-15
OUTPUT 2W
~~ROBE
ITT7528, ITT7529
DUAL SENSE AMPLIFIERS WITH
PREAMPLIFIER TEST POINTS
ELECTRICAL CHARACTERISTICS (unless otherwise noted Vcc+ =5V, Vcc - = -5V,
TA=O°C to 70°c)
Parameter
VT
Test
Fig.
Differential-input
threshold voltage (see
Note 3, page 17)
Min
10)11
20
8
,(35)36
33
VrcF
Common--mode input
firing voltage (see Note 4,
page 17)
1m
DifferentiaHnput bias
current
2
ho
Differential-input offset'
current
2
VIR
High-level input voltage
(strobe inputs)
21
V1L
Low-level input voltage
(strobe inputs)
21
VOH
High-level output voltage
21
VOL
Low-level output voltage
IIH
High-level input current
(strobe inputs)
hL
Low-level input current
(strobe inputs)
los
Short-circuit output current
Ice+
Supply current from Vee+
lee-
Supply current from Vee -
Typ** Max Unit Test Conditions
15 (20)19
40 (45)44
75
(100)
0.8
-1
V
0.4
V Vcc+ =4.75V, Vcc - = -4.75V,
IOL=16mA
40
p.A Vce+ =5.2SV, Vee - = -S.2SV,
VIH =2.4V
1
mA Vee+ =5.25V, Vee - = -5.25V,
VIR=5.2SV
-1.6
mA Vec+ =5.2SV, Vee - = -5.25V,
VrL =O.4V
0.25
"
-3.5
mA Vee+ =5.25V, Vee - = -5.25V,
25
40
mA Vce+ -5.25V, Vee - - -5.25V,
TA=25°C
-15
-18
rnA Vce+ =5.25V, Vee - = -5.25V,
I TA=2SoC
-2.1
** All typical values are at Vee+ = 'S V, Vee - =
p.A Vcc+ = 5.25V, (S528/29)
Vcc - = -5.25V, VID=O
V Vcc+=4.7SV, Vcc-=-4.75V,
10H= -400p.A
4
2.4
6
ITT7529/5529
V
2
6
Vrer =40mV
p.A Vcc+ =5.25V,
Vcc - =,-5.25V, VID=O
3
22
23
mV ITT7528( 5528 )
V Vref =40mV, VI(S) = VIR
Common-Mode Input Pulse:
tr::::;;15ns, t r ::::;;15ns, t w =50ns
30
22
ITT7529/ 5529
47
40
±2.5
21
ITT7528 ( 5528 )* Vrer=15mV
22
15
-5 V, TA
• Numbers in parenthesis apply to .5528 or 5529 as indicated.
6 -16
= 25°C
ITT7528, ITT7529
DUAL SENSE AMPLIFIERS WITH
PREAMPLIFIER TEST PONTS
SWITCHING CHARACTERISTICS, Vcc+
= 5 V, Vcc- = ~5 V, TA = 25 C
e
Propagation Delay Times
Symbol
From Input
tPLH(D)
A1-A2
To Output
W
tPHL(D)
tPLH(S)
Strobe
W
tPHL(S)
Test
Fig.
Min
25
39
40
20
15
39
20
ns
30'
RL - 2880
ns
CL = 15 pF,
RL
= 2880
ns
Min
,Typ
Max Unit Test Conditions
torD
Differential-input overload
recovery time
(see Note 5)
20
ns
torc
Common-mode-input overload
recovery time (see Note 6)
20
ns
t.y.(mln)
CL - 15 pF,
ns
= -5 V, Vcc - = -5 V, TA = 25°C
TYPICAL RECOVERY AND CYCLE TIMES, Vcc Parameter
Typ Max Unit Test Conditions
Differential Input Pulse:
VID
2 V,
tr
20 ns
=
Common-Mode Input Pulse:
±2V, tr
tr
20 ns
V~c
Minimum cycle time
200
=
=
= =
ns
NOTES:
3. The differential-input threshold voltage (VT )
is defined as the d-c differential-input voltage
(VID) required to force the output of the sense
amplifier to the logic gate threshold voltage
level.
4. Common-mode input firing voltage is the
minimum common-mode voltage that will exceed the dynamic range of the 'input at the
specified conditions and cause the logic output
to switch. The specifed common-mode input
signal is applied with a strobe-enable present.
5. Differential-input overload recovery time
is the time necessary for the device to recover
from the specified common-mode-input overlo~d signal prior to the strobe-enable signal.
6. Common"mode~inputoverloadrecovery time
is the time necessary for the device to recover
from the speCified common-mode-input overload signal prior to the strobe-enable signal.
6-17..
. . IT·T _.___
IT_T_55_3_4_/I_TT_7_5,;",,;.3_4_a_nd_IT_T_5_53_5....'_IT_T_75_3_5
SEMICONDUCTORS
schematic diagram'
DUAL-IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
v+
'CEXT
~IFFERENTlAL{
STROBE
A
OUTPUT
A
INPUT A
REFERENCE{INPUT
+
120U1rUT
STROBE
B
DIFFERENTIAL {
INPUT B
OUTPUT A
NO CONN.
v-
OUTPUT B
STROBE,S
GNDI
connection .diagram
<>--t---:-:---==F-l
V'
GND2
Voltage Waveforms
~~
I .
l '.
---I
t-_,.0.----+1I .
-.;.V
DIFFERENTIAL
AC test circuit
INPUT
'DillY
2DIIIV
''''tV
rOmV
IV
':
lDOM
DIFfERENTIAL
INPUT
':,
.~..
----'v
uv ,
~
......L...----.
STROlE
'NPUT
I.SY
5T,ROlfIN'UT
,......-....-oV··.V
OUTPUT.
'~-
no!!
'p~~""'::'=HI""'" '>-_....jLJ't:I.;;"';.;;",...--()~~~~~T
,
Ih'INClUDING
L_ 'Ji"~:
~
""'T
":"
I
--r
n
-="
I
,,,
,,
J
1"G'.D.AD"
.
~"'~ I
• --I 1--"'"
....
~
..
1.5V
i->=
I----I
.
lDOM
1--, •
,-I
~~
~1.5.V
. 1.5Y
I
I
---I
.V
.... r.:::1--,
0
~'.SV
1. Pulse generators have the following characteristics
Zout=5000 tr=tr=:15(.5) ns, PRR=1 MHz
2. Propagation delays
A=Diffelreritial input to logical "0" output
. B=Differential input to logical "1" output
C=Strobe input to logical "0" output
D=Strobe input to logical "1" output
y-. -sv
6-18
ITT5534/1TT7534 and ITT5535/1TT7535
ELECTRICAL CHARACTERISTICS
ITT5534/ITT5535: The following apply for -55°C~TA~125°C. V+=5V±5%. V-=-5V±5%
-5V±5% (Note 1)
Test Conditions (Each Amplifier)
Parameter
Differential
Input
Threshold
Voltage
(VTH) (Note 2)
Min
10(8)
Typ
Differential &
Reference
Input Bias
Current
Unit DiU.
Input
Ref. Strobe
Input Input
Logic
Output
Supply
Volt
Comments
+5.25V ±5V±5% Logic
Output
<2S0p.A
mV ±VTH 15mV +5V
+20mA ±5V±5% Logic
Output
.
=
=
=
Vcc+ = 4.75 V,
Vcc - = -4.75 V,
10L = 16 rnA
Vcc+ = 5.25 V,
Vcc - = -5.25 V,
V = 2.4 V
Vcc+ = 5.25 V,
Vcc - = -5.25 V,
VIH = 5.25 V
Vcc - = -5.25 V,
Vcc+ = 5.25 V,
V1L = 0.4 V
V Vcc+
4.75 V,
Vcc -4.75 V,
lOR
-400/lA
25
VOL
/lA Vcc+ = 5.25 V,
Vcc- = -5.25 V,(55234/35
Vm = 0
All typical values are at Vcc+ = 5 V, Vcc - = - 5 V, TA ;::: 25°C.
* Numbers in parenthesis apply to 55234 or 55235 as indicated.
6-23
=
=
=
ITT75234, ITT75235
DUAL SENSE AMPLIFIERS
SWITCHING CHARACTERISTICS, Vcc+
= 5V, Vcc Test
Symbol
tPLH(n)
From Input
To Output
A1-A2
W
Typ Max Unit
Min
Fig.
40
tpHL(n)
tPLH(s)
25
STROBE
W
25
ns
40
ns
25
40
tPHL(s)
TYPICAL RECOVERY AND CYCLE TIMES, Vcc+
Parameter
= 5V,
15
30
ns
Vcc -
= 5V,
TA
Typ
Min
ns
Test Conditions
CL
=
CL --
15pF,
RL
= 288 fl
15pF,
RL
= 288 fl
= 25°C
Max Unit Test Conditions
tORD
Differential-input overload
recovery time (see Note 5)
20
ns Differentiai Input Pulse:
2 V,
VID
tr
tf
20 ns
tORC
Common-made-input overload
recovery time (see Note 6)
20
ns Common-Mode Input Pulse
VIC
±2 V,
tcyc(min)
Minimum cycle time
200
=
= =
=
ns tr - tf - 20 ns
NOTES:
5. Differential-input overload recovery time
is the time necessary for the device to recover
from the specified common-made-input overload signal prior to the strobe-enable signal.
6. Common-made-input overload recovery time
is the time necessary for the device to recover
from the specified common-made-input overload signal prior to the strobe-enable signal.
6-24
-
ITT7520
SENSE AMPLIFIERS
ITT- - - - SEMICONDUCTORS
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
d·c test circuits·
VIO
~
SEE
______r-~OH
TEST
TABLE
ANO
/ff., {
v ....
~
~"
}
NOTE
________-<
~llOH
11
':'" -=
~
I
~
TEST TABLE
CIRCUIT
TYPE
ITT7520
ITT7521
INPUTS
Yr.r
OUTPUTY
Yrn
Yo
A1·A2 or 81·82 15 mV
::;;;11 mV ::;;;0.4 V
A1·A2 or 81·82 15 mV
~19
A1·A2 or 81·82 40 mV
::;;;36 mV ::;;;0.4 V
A1·A2 or 81·82 40 mV
~44
mV
~2.4V
IOH
OUTPUTZ
IOL
16 mA
-400 }LA
A1·A2 or 81·82 15 mV
A1·A2 or 81·82 15 mV
~22
A1·A2 or 81-82 40 mV
::;;;33 mV
::;;;0.4 V
A1-A2 or 81-82 40 mV
~47
16 mA
~2.4V
16 mA
16 mA
-400 }LA
~2.4V
16 mA
400 }LA
::;;;0.4 V
16 mA
-400 }LA
~2.4V
~2.4
V
16 mA
-400 }LA
::;;;0.4 V
NOTE A: Each pair of differential inputs is tested separately with the other pair grounded.
FIGURE 1-YT
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-25
IOL
-400 }LA
::;;;0.4 V
mV ~2.4V -400 }LA
mV
IOH
~2.4V
::;;;0.4 V
mV ~2.4V -400 }LA
::;;; 8 mV ::;;;0.4 V
Yo
16 mA
1117520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits* (continued)
TEST
POINTS
vcc~
STROBES
(SEE TABLE
6,.;x;
:r
cc +
~-~1~~T~---- ______'1-,
SEE
NOTES
~ AandB
4
ALL CIRCUIT TYPES
.
L __________
______
.J
~--
NOTES:
A. Each preamplifier is tested separately. Inputs
not under test are grounded.
B. 1.0 = hw and/or hw, 1.0 = 1.(1) - !tw, are
the currents into the two inputs of the pair
under test.
Pin Connections (Other Than Those Shown Above)
100 pF to GND
Circuit Types
ITT7520, ITT7521
0-
..
ITT7522, ITT7523
ITT7524, ITT7525 .
ITT7528, ITT7529
ITT75234, ITT75235
Apply Vcc+
Cext
GyoGZ,SA'SB
CD
CD
C
CD
C
CD
@@)®@
Cext
ext
ext
Apply GND
@@
G, 8A' SB
@@@
@@
@@
@
GND 2
®
®@
1W,2W
@@
1W,2W
@)@@)@
18, 28
GND.2
®®
®
6-26
AL, Y
1P, 2P,
18, 28
* Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
Other
V, Z
GND 2
18,28
Leave Open
1W,2W
@@
ITT7520
SENSE AM PLiFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits· (continued)
FIGURE 3-Vm, V1L, VOH,
Vlo . . .
mv~~::.
VOL
P-I.....--I-(1ii)3 OPEN
AI
TABLE Ll.!!!..r.'UJ... ,
~
V..,-20rnVo----I--{!
TEST TABLE
Test
1m at STROBE SA
1m at STROBE SB
Input
A1
GND
GND
Input
B1
Strobe
SA
GND
Vm
GND
V1L
Gate
Gy
Gate
Gz
V1L
V1L
V1L
Vm
V1L
V1L
Strobe
SB
1m at GATE Gy
VID
VID
Vm
Vm
VIH
V1L
1m at GATE Gz
GND
GND
VIL
V1L
VIH
VIH
Ill, at STROBE SA
VID
GND
V1L
V1L
V1L
V1L
VIL
lIT, at STROBE SB
GND
VID
VIL
V1L
V1L
I", at GATE Gy
GND
GND
V1L
V1L
V1L
V1L
I", at GATE Gz
GND
GND
V1L
V1L
V1L
V1L
FIGURE 4-lm ,
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-27
IxL
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits" (continuecJ)
,I
v..,.20mv....--""',""
~,,"'CL/"
l'OSIZI
'
• L2-----~~~'!!:~~-----J
~IOOPF
llos,vl
~
FIGURE 5-108
NOTE A:
When testing 108(Y), Pin 10 is open; when testing 108(Z), Pin 10 is grounded.
t:
TEST
POINTS
c•
YC01, ~ ~
'cc-i,-~ --:--t---'1) \.,J
':[ +ICC+
- - ---- 1
I
2 I
,
I
' I
I
I
I
,
!,
I
V..,.20~V
L _____ ~~::~~'~~~------J
Pin Connections (Other Than Those Shown Above)
Circuit Types
100 pF to GND
Apply GND
Leave Open
ITT7520, ITT7521
Cext
Gy , Gz' SA' SB
Y, Z
@@)@)@
ITT7522, ITT7523
Cext
G, SA' SB' GND 2
0)
@®@@
®®
R Y
@@
ITT7524, ITT7525
Cext
1S, 2S,·GND 2
@B@
@@
ITT7528, ITT7529
0
1W,2W
Cext
1S,2S
1P, 2P, 1W, 2W
0)
@@
@)@)@)@
1~~G.v2
15 11 13
1W'_Gi'
L
G4)
12
CD
ITT75234, ITT75235
...
.
Figure 6-lcc+, Icc.:.
.. Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-28
L,
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits· (continued)
v.,o------0~
TEST TABLE
Output
Circuit Type
Inputs
Vo
IOH
ITT7522
A1-A2 or 81-82
15 mV
::::;11mV
~2.4V
-400 p.A
A1-A2 or 81-82
15 mV
~19
::::;0.4
A1-A2 or 81-82
40 mV
::::;36 mV
~2.4V
A1-A2 or 81-82
40 mV
~44
mV
::::;0.4 V
A1-A2 or 81-82
15 mV
::::; 8 mV
~2.4V
A1-A2 or 81-82
15 mV
~2emV
::::;0.4 V
A1-A2 or 81-82
40 mV
::::;33 mV
~2.4V
A1-A2 or 81-82
40 mV
~47
::::;0.4 V
ITT7523
Vr.,
Vm
mV
mV
NOTE A:
Each pair of differential inputs is tested separately with the other pair grounded.
FIGURE 7-VT
Vm - 2OmVo---+-{!)>t-P-.....
FIGURE B-VIH' V1L, V oH, VOL
* Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-29
V
IOL
16 mA
-400 p.A
16 mA
-400 p.A
16 mA
-490 p.A
16 mA
IT17520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits* (continued)
"H
VIH~SEE ~=~==~l--l
TEST
Vll~ TABLE
'll
TEST TABLE
A,
Input
B,
Strobe
SA
Strobe
So
Gate
G
IIH at STROBE SA
GND
GND
VIH
'!IL
VIH
hn at STROBE So
Input
Test
GND
GND
VIL
VIH
VIH
1111 at GATE
VlD
V lD
V1JI
V1JI
V1JI
hL at STROBE SA
VlD
GND
VIL
V'L
V1JI
hL at STROBE S8
GND
V,o
VIL
GND
GND
VIL
V'L
V1L
V1JI
hL at GATE
FIGURE 9-hn, IlL
Vo
I
I
I
I
,
:'
I
vr•• ' 20mv---r--...:"",
,
4 L~ __. ___ ..!~2~&,:!!:~::: ____ J
*TOOPF
~ ~
FIGURE 10-loH
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-30
y
VIL
ITT7520
SENSE AM PLiFIERS
PARAMETER MEASUREMENT INFORMATION
doc Test Circuits·
V,.,·20mV
FIGURE 11-los
TEST TABLE
Output
Circuit Type
ITT7524
ITT7525
Inputs
Vre,
V ID
Vo
A1-A2
15 mV
::::;;11mV
::::;;0.4 V
A1-A2
15 mV
;::19 mV
;::2.4 V
A1-A2
40 mV
::::;;36 mV
::::;;0.4 V
A1-A2
40 mV
;::44 mV
;::2.4 V
A1-A2
15 mV
::::;; 8 mV
::::;;0.4 V
A1-A2
15 mV
;::22 mV
;::2.4 V
A1-A2
40 mV
::::;;33 mV
::::;;0.4 V
A1-A2
40 mV
;::47 mV
;::2.4 V
NOTE A:
Each pair of differential inputs is tested separately with its corresponding output.
FIGURE 12-VT
* Arrows indicate actual direction of current
flow. Current into a-terminal is a positive-value.
6-31
10H
IOL
16 mV
-400 }J-A
16 mV
-400 !LA
16 mV
-400 !LA
16 mV
-400 !LA
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits*
lW
T~~~H
}
'_ _~'-~OH
~l
{
TABLE
Vrlf" 20 mV
-"
Il10H
0-----+-<
1L1
FIGURE 13-VIH' V1L, VOH, VOL
t-------,
VIHd'IH SEE
TEST
Vll ...... T A B L E i - - - - - - .
',l
Vlo-COmV
~
SEE
>-~-l_r-----~14
OPEN
lA23
TEST 2A1
TABLE
2A
Vr.f· 20 m V o - - - - _ I _ {
TEST TABLE
Test
Input 1A1
Input 2A1
STROBE1S
GND
GND
V1L
VIL
VIH
hL at STROBE 1S
VID
GND
GND
GND
VIH
IIH at STROBE 2S
V1L
V1L
hL at STROBE 2S
GND
VID
VIL
V1L
IIH at STROBE 1S
FIGURE 14-IIH, IlL
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-32
STROBE 2S
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits' (continued)
FIGURE 15-105
* Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
v"
~
'A'
SEE
TEST
TABLE
3
'lA1
ANO
I
I
I
I
I
6
NOTE A
I
SEE
2W
I
2A'l
I
I
I.J
::
v"'~~
:'.~-,
•
~
," } {=rtTI
~"
2
lA2
L
q; _J
~ __ .:'.:': ':2"-'~,=,':'
l
1
lOOPF
]n
TEST TABLE
Output
Circuit Type
Inputs
Vrer
ITT7528
A1-A2
15 mV
:(11 mV
A1-A2
15 mV
~19mV
~2.4V
A1-A2
40 mV
:(36 mV
:(0.4 V
A1-A2
40 mV
~44mV
~2.4V
ITT7529
VID
Vo
A1-A2
15 mV
:(8 mV
:(0.4 V
A1-A2
15 mV
~22mV
~2.4V
A1-A2
40 mV
:(33 mV
:(0.4 V
A1-A2
40 mV
~47mV
~2.4V
NOTE A:
Each pair of inputs is tested separately with
its corresponding output.
FIGURE
16-V~.
6-33
10H
:(0.4 V
10L
16 mA
-400 jJ.A
16 mA
-400 jJ.A
16 mA
-400 jJ.A
16 mA
-400 jJ.A
ITT7520
SENSE AM PLiFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits· (continued)
v 10 --40 m
V~SEE
TRUTH
TABLE
-40mV
l - GND
I
I
Vref • 20mV~----t-{
'L
I
f --
I
I
_75':8/.!.5~c.!!'c~r!~ _-l
1
~'OOPF
FIGURE 17-VIH' V1L, VOH, VOL
• Arrows indicate actual direction of current
flow. Current into a ·terminal is a positive-value.
v,.,. 20 mV o-----'-+--<
TEST TABLE
Test
Input 1A1
Input 2A1
Strobe 1S
GND
GND
VIL
VIL
VIII
hL at STROBE 1S
VID
GND
GND
GND
VIH
IIII at STROBE 2S
V1L
V1L
IlL at STROBE 2S
GND
VID
VIL
VIL
IIII at STROBE 1S
FIGURE 18-IIH, /rL
6.,...,.34
Strobe 2S
---.-
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits· (continued)
V,e!.20 m Vo-----IH")-+f:'o..
FIGURE 19-108
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
TEST TABLE
Circuit
Type
Inputs
Vr•c
Vm
ITT75234
A1-A2
15 mV
~11
~19
ITT75235
Ou~ut
Vo
10H
mV
~2.4V
-400 p.A
A1-A2
15 mV
mV
~O.4V
A1-A2
40mV
~36mV
~2.4V
A1-A2
40mV
~44mV
~O.4V
A1-A2
15 mV
~
~2.4V
A1-A2
15 mV
~22mV
~O.4V
A1-A2
40 mV
~33
mV
~2.4V
A1-A2
40 mV
~47mV
~O.4V
8mV
NOTE A:
Each pair of differential inputs is tested separately with its correspondng output.
Figure 20-VT
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-35
10L
16 mA
-400 p.A
16 mA
-400 p.A
16 mA
-400 p.A
16 mA
ITT7520
SENSE AMPLIFIER$
PARAMETER MEASUREMENT INFORMATION
doc test circuits* (continued)
1
IW
SEE
T~~t}
IA2
TRUTH
VIO ~ 40 mV
TABLE
2A
H" COmV
l ~GND
V re," 20mV
{
-----..,...-l'+OH
10L
~
TABLE
A
I
0-----+-<
I
Hlr
I
I
I
I
I
· "-----',,",-""'f"'fc-J
':' "'::" ':' -=-
Figure 21-VIH, V1L, VoH, VOL
V'H~"H TEST t - - - - - - - - ,
1-----...,
SEE
VIL ..... TABLE
'll
'W
~~-l~~----~t4~EN
>_-l~~----__:<12
I
Vr .,·20mVC>-----t-{
OPEN
2W
I
I
·"-------~ll-J
I
I
I
oJ.
':"
-=-
TEST TABLE
Test
is
Input 1A1
Input 2A1
Strobe 1S
Strobe 2S
VIH
V1L
V1L
VIR
V1L
V1L
V1L
V1L
IIR at STROBE 2S
GND
GND
hL at STROBE 1S
VID
GND
GND
GND
hL at STROBE 2S
GND
VID
IIR at STROBE
Figure 22-IIH, IrL
• Arrows indicate actual direction of current
flow. Current into a terminal is a positive-value.
6-36
ITT7520
SENSE AMPLIFIERS
r
ee •
PARAMETER MEASUREMENT INFORMATION
d·c test circuits· (continued)
-----~,'.w
,, "
'2W
1
,,
I
V r.,.
---- 1
20 mVo---+--{!
""'",.-".,.~
Figure 23 -los
"
,
~j
J
~os
PARAMETER MEASUREMENT INFORMATION
Switching Characteristics vcc_~
ro
8
A,r-
~
Gz
---------- ---
28811
28811
) -_ _ _-+-o0U~UT
CL ' '5 pF-::I:"
(Set Note 8)
60n
50n
"='
SOn &On
GATEGy
INPUT
TEST CIRCUIT
VOLTAGE WAVEFORMS
-------
~
GATEG y
INPUT
NOTES:
A. The pulse generator has the following
characteristics: Zout = 500, tr = t, = 15 ± 5ns,
tw
100 ns, and PRR
1 MHz.
=
=
I
I
'\:.JL'
. l.r-
----.J1.t--~ ~
tpHl.IGY, VI
I
--l
I
I
OUTPUT
y
I
I
I
I
1.5V
.:
~
B. CL includes probe and jig capacitance.
OUTPUT
~ tPLHIGY,YI
I
'.
- - - - - 3.• V
1.6 v
1.SV
I
.
ov
~=""---"";"VOH
1.5V
: - - - - - - - - - - vOL
'PLHIGY,ZI
Z_ _ _ _ _ _ _ _..J
....f IPHLIGY,ZI .....
v
. ". \ : - -
----V
OH
VOL
Figure 24-ITT7520/ITT7521 Propagation Delay
Times From Gate Gy
6-37
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
Switching Characteristics (continued)
VCC_j
r-T -- ---
288~!
288!!
'r---.....-o
OUTPUT
Cl • 15 pF-:I:'
(See NoteD) ';'"
Vref = 20 mVo-l-+-+-+--<
SOIl
SOU
SOl!
SOu
TEST CIRCUIT
GATE G Z
INPUT
/"
_ _ _ _- - I
tpHL(GZ. Z)
OUTPUT
Z
-
-
-
I
--I
-
-
-
3.5 V
OV
t-
~~~_V
________
r-
tpLH(GZ. Z)
J~r~-v--_--_-----_--_--_--_-_-~~~
VOLTAGE WAVEFORMS
NOTES:
A. The pulse generator has the following
characteristics: Zout = 500, tr = tf = 15 ± 5ns,
tw
-
= 100 ns, and PRR = 1 MHz.
B. CL includes probe and jig capacitance.
Figure 25-ITT7520/ITT7521 Propagation Delay
Times From Gate Gz
z
11T7520
SENSE AM PLiFIERS
PARAMETER MEASUREMENT INFORMATION
Switching Characteristics (continued)
DIFFERENTIAL
INPUT
288u
V ..f '" 2OmVO-_ _f--{
TEST CIRCUIT
~omv
DIFFERENTIAL
INPUT PULSE
Ie-
STRO~E
15
. V
INPUT PULSE
I.
L
.HLIOI
OUTPUT
I:! k:..,
I
I
_
I 20mV
~1 --I'------;,rf'--J
I
'..2
--L...--.I
t.- -I
I..
II
4.-.- -
tw2
1-1
1.5 V
£Of_ _ _ _oJ
'~HLISI
~.5V
-.I
If
"\1.5 V
0V
t
~1 -I
I
I- tPLHISI
.,
'~'\:~:J1.5V
-
VOLTAGE WAVEFORMS
NOTES:
A. The pulse generators have the following
characteristics: Zout = 500, tr = tr = 15 ± 5ns,
twl = 100ns, tW2 = 300 ns, PRR = 1 MHz.
8. The strobe input pulse is applied to Strobe
SA when testing inputs A1-A2 and to Strobe SB
when testing inputs 81-82.
C. CL includes probe jig capacitance.
Figure 26 -ITT7522/ITT7523 Propagation Delay
Times From Differential· a.nd Strobe Inputs
6-39
ov
~-:----·':'-3.5V
IfI.--.I
.
1.5 V
tpLHIOI
~
-
.'
V
OH
---vOL
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
Switching Characteristics (continued)
vcc-r
A1
r-~---------
28811
OUTPUT
V
vref = 20 mV
o--+--1--t-+--{,
50!l
501:
Sal:
50~~
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES:
A. The pulse generator has the following charson, tr tf
15 ± 5 ns,
acteristics: Zo
t p•
100 ns, t p'
300 ns,
t p' = 0.8 p..s, PRR = l' MHz.
=
=
=
= =
B. CL includes probe and jig capacitance.
Figure 27-ITT7522/1TT7523 Propagation Delay
Times From Gate Input
6 - 40
ITT7520
SENSE AM PLIFIERS
PARAMETER MEASUREMENT INFORMATION
SWitching Characteristics (continued)
DIFFERENTIAL
INPUT
V'e! ~ 20 rnV
o---t-(0--+-f.'
TEST CIRCUIT
i
..J{~,
1'. .
DIFFERENTIAL
INPUT _PU_LS_E_ _
r-Ji
20_m_v_ _-I1
20 mV
~'w,~
~
I
I
I
I·
STROBE~NPUT
1 5V 1
I
15. V
PULSE
.
I.---f
I
'w2
,_
-t----l
--I
r-
----.......
'w2
.. r:::-":l.SV
-
1-/- - - - '
'--
-.J
I
' •• ,
V- -
.:..... -
-
-..J
r--~.-
!.- -.j
'PLHISI----'
mv
- - :Ov
-
------I
Ii ,'v i\.1~
'PHLIDI
Asv
'PLHIDI-<1"-OUTPUT
~:V -
20 mV
.
-
-
-
NOTES:
A. The pulse generators have the following
characteristics:
Zout
50 0, tr
tr
15 ± 5 ns,
twl
100ns, tw,
300 ns, PRR
1 MHz.
= =
=
=
8. The strobe input pulse is applied to Strobe
1S when inputs 1A1-1A2 are being tested and
to Strobe 2S when input 2A 1-2A2 are being
tested.
C. C. L includes probe and jig capacitance.
Figure 28-ITT7524/ITT7525 Propagation Delay Times
6- 41
v
- - V DH
'------
VOLTAGE WAVEFORMS
=
=
0
'PHLISI
T1.5V \5V
'-.---17--/-----'
- - 3.5 V
VOL
ITT7520
SENSE AMPLIFIERS
PARAMETER MEASUREMENT INFORMATION
SWitching Characteristics (continued)
DIFFERENTIAL
INPUT
l
lW
I Cl
OUTPUT
13
15 pF
'T"
hse.:- NOle CI -=
I
?----4'"t-,-\-___----1..;{'1Z'f-_ _
-'>----~:::{::~------~'W~'.~~OO~T
I CL · , . , · " ,
ICS-NotlCI-:b-
I
;>--T---rIP-------+.::-@12)-----~-o OtJ:!UT
1M
I
V ...f· 20 mY ()---~f--(
I
I
~--1-fJ
I"
11
.". -=
TEST CIRCUIT
DIFFERENTIAL
~~
-J"
INPUT_PU_LS
__
E ___
20 mV
1\,-20_m_v_ _-il
i
r--J'i
I-'w,--..I
I---
I
I
STAOBE~NPUT
I. I
PULSE
.
,.5V.
I
I--iI
I.
'w2
--I
I-'PLHIO)
I
"
l
~
OUTPUT
1.5V
~-.--------3.5V
lC·
1-1----' I.-. 'w' .....j ' - - - - - - .-.J r-----l r5V
1.5 V
+---I
'PHLIO)--,!.-
20mV
tpHLIS)~
1.5 V
i\',5V
I
OV
tpLHIS)
\:.j,r-----VOH
I
1.5 V
1.5V
- - - - - - - - VOL.
VOLTAGE WAVEFORMS
NOTES
A. The pulse generators have the following
characteristics:
Zout
son, tr tf 15 ± 5ns, tWi 100ns,
t w , = 300 ns, and PRR = 1 MHz.
=
= =
B. The strobe input pulse is applied to Strobe
1S when inputs 1A1-1A2 are being tested and
to Strobe 2S when input 2A1-2A2 are being
tested.
C. CL includes probe and jig capacitance.
Figure30-ITT75234/ITT75235 Propagation Delay Times
6-43
ITT7520
SENSE AMPLIFIERS
TYPICAL CHARACTERISTICS
THRESHOLD VOLTAGE
THRESHOLD VOLTAGE
vs
vs
RFERENCE VOLTAGE
SUPPLY VOLTAGE
50
>
E
.
VCCt-SV
VCC_ • -5 V
••
/
TA -O'Clo7frC
~JS
V
!!
(; 30
...>(;
~
~
I
....
2.
V
V re ,
>
~
V
20
"
/
V
10
20mV
~
g'
22
'0 21
V
2'
~
TA -2SC
23
r---
>
:220
V
o
~
19
~
18
f-
~11
>
>
- ----
16
00
5
10
15
10
25
30
35
40
045
4,75
50
Figure 32
Figure 31
NORMALIZED THRESHOLD VOLTAGE
vs
PULSE REPETITION RATE
FREE-AIR TEMPERATURE
'0
~
vCC+-sv
Vcc_· -5V
V,..-20mV
1.11
T A • 2S-e
1.4
~
J
m
V IISI • V 1H
O.B
0.5
~ -2
0 .•
0.2
>
Vcc_~-5V
~
v
~
I
f-
tf..1'V tCF
Vcc." 5 v
I
1.2
Z
1 I I,
J
"c
~
i
ig
"'"
~
>
COMMON-MODE FIRING VOLTAGE
vs
~ t,'
o
~
,Ir" 15ns,',.; 15ns, '",," SOns
E
o
I
U.
I
0-' 0
o
0,01
0,'
,
10
:>
100
rt'- 20mV
("IIIIIII'III"',I<1'-/II{III//'Il/""
-1
0-3
1
0.001
)0
50
.
~
,
'"'
3'
!D
30
~
25
~
0
60
"cc-" -5V
V ID .. 0
!
1.0
~
0.9
VCCt ·5\1
Vcc.--!lV
::J
0.8
V'O·O
!'
07
'-'
I
......... to....
o 0.6 t--...
~
0.5
:
0 .•
~
OJ
o
---
b-.,.
~ 02
001
I
o
70
vs
•
0
50
FREE-AIR TEMPERATURE
I
!D
40
FREE-AIR TEMPERATURE
1:
o
:lO
vs
"cc."SV
••
I
DIFFERENTIAL-INPUT OFFSET CURRENT
DIFFERENTIAL-INPUT BIAS CURRENT
T-
'Z.n
I
f I
Figure 34
Figure 33
c
I
-V leF
TA-Freeo Air Temperalure-oC
PRR-Puls. Rt'petition Rote-MHz
0
5.5
'5.25
Vee 1" and VCC--Supply Voltages·- V
Vret- ReferenC'e Voltage-mv'
10
70
JO
40
so
60
"
70
TA- Free Air Temperoture-OC
Figure 35
. 10
10
·30
40
Figure 36
6-44
50
TA - Free Air Temperature
M
-q.c
ITT7520
SENSE AMPLIFIERS
TYPICAL CHARACTERISTICS
I-IIGH-LEVEL INPUT CURRENT
LOW-LEVEL INPUT CURRENT
vs
vs
INPUT VOLTAGE
INPI.lT VOLTAGE
-2
'0
'"tv
~
E
VCC_· -5V
TA ·2S"C
8
,..
.
..,
3
'"
2
-'
TA .2S·C
_1.5
..,"
c3 '
1ii
Vcc_--sv
~t
'l; 6
a.
c
vcc.-sv
'"
vcc.-sv
1 _. f'..
V
3
~
i:
o
-'
•:::!
[)'
•
=
I
DO
•
,
.........
-=;;
1/
r--....
"\
-05
o
o
3
..•
D.'
V,-lnputVDltDge-V
V,- Input Voltoge-V
Figure 38
Figure 37
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL-INPUT VOLTAGE
DIFFERENTIAL-INPUT VOLTAGE
SN7522,SN7523; Z OUTPUT OF
7521
1520,
>
..
I
!!'"
~
7524.
-
Vr·f·'~mv
>
&,
3
.3I '
~
!!3~~~~
V,e,-3SmV
Vcc-- -sv
o
IOH --400 .. A
~
-;
"}
VCC.-SV
~
IOL -0
TA -2S-C
VCC_-- SV
LOH • -400 ~A
1
I
10
15
~
W
~
~
D~~~~==~~~~~
o
~
5
10
~
;
o
..>
r-.....
4
l"""- I"--.
3
I
vcc.-sv
Vcc-· -sv
.: 0.4
T A • 25~C
1i
.,....
2
I •
o
'"
0.2
Vcc_· -5V
;.
.3
0.1
TA ·2S"C
~
o
>
'1 1 I I I
o
-200
-400
-800
-BOO
.
0.3
~
Vee .. ·5V
>
o
D
o
a
:;:
40
0.6
~
r-.... !'oo.
;;
~
35
LOW-LEVEL OUTPUT CURRENT
.......
~
30
vs
HIGH-LEVEL OUTPUT CURRENT
""
.
25
LOW-LEVEL OUTPUT VOLTAGE
vs
!!
20
Figure 40
HIGH-LEVEL OUTPUT VOLTAGE
co
IS
VID-Diff.,.nliollnpul VDltoge- mV
Figure 39
.•
+-f-+---:f-+--'
+----~_t_~~-t--
'OL· 0
TA .2S·C
V, D Dilferentlallnput Vollagl-m V
>·6
r---
1
V,.,.25mV ~t--
'0
>
5
r-
V,.,·,SmV
I I
vcc.-sv
o
7528,
7529: ---:7520,
7521;
_
I
V",-3SmV
o
.1
I--vr.f·2smv
"
~
7525,
v OUTPUT Of
-1000
IOH -High-Level Oulput eurr.nl-~A
DO
~
..-
2.,.
k-'
tnt
. '.'.1Ir
IOL- Low Lavel Output eurrent-mA
Figure 41
Figure 42
6-45
ITT7520
SENSE AMPLIFIERS
TYPICAL APPLICATIONS
Small Memory Systems
This application demonstrates an improved
method of sensing data from relatively small
memory systems. Two individual core planes,
usually consisting of 4096 cores each, can be
interfaced by each of the dual-channel ITT7524
or ITT7525 sense amplifiers, see Figure K.
Standard TTL or DTL integrated circuits, driven
directly from the compatible sense-amplifier
outputs, may be selected to serve as the memory data register (MDR).
STROBE .It.
SENSE LINE 1
PLANE 1
4096 CORES
(Typical)
MEMORY DATA
REGISTER
r:- - - - - - 752417525
r-----,
I
I
t---'.-----T""I
_---4 __ y---r-----i
I
BIT 1
I
I
I
I
1---- -J
I
I
SENSE LINE 2
PLANE 2
4096 CORES
I
I
I
BIT 2
(Typical)
I
I
L __ _
I
~----~
-
SENSE LINE 3
7524/ 7525- - ,
I
I
I
PLANE 3
4096 CORES
I
~---II---""1
(Typical)
I
I
I
~~-J
I
I
BIT 3
I
I
:
L-----i
I
I
SENSE LINE 4
I
PLANE 4
I
4096 CORES
(Typical)
)--'--'1----1
'---~J
I
L ____1_ _ _ _ .,...._.J
I
I
I
I
BIT 4
I
I
I
L ____ J
\~------------------------------~vr------------------------------~'
To additional planes and 7524's or 7525'$
as necessary for complete memory word
Figure K-Sensing Small Memory Systems
6-46
ITT7520
SENSE AMPLIFIERS
Large Memory Systems
This application demonstrates an improved
method of sensing data from large memory
systems. The signal-to-noise ratio can be increased by sectioning the large core planes as
illustrated in Figure L. Two segments, usually
consisting of 409.6 cores each, can be interfaced by each of the dual-input channels of
ITT7420/ITT7421 or ITT74221lTT7423 sense
amplifiers. The cascaded output gates of ITT-
circuits may be connected to
serve as the memory data register (MDR). A
number of ITT7522/ITT7523 sense amplifiers
may be wire-AND connected to expand the input function of the MDR to interface all the
segments of the plane. Complementary outputs,
clear, and preset functions are provided for the
MDR. Rules for combined fan-out and wireAND capabilities must be observed.
7520/lTT7521
SEGMENTED CORE PLANE (reprot:lntl onG bit in momory word)
STROBE J""L
SENSE LINE 1A
r: - - - - - - - -
~2;;;r 7521-:;;;-
SEGMENT A
4096 CORES
(Typical)
--l
Output Connoctsd as
Memory Dati Register
(MDR)
SENSE LINE 1B
Y}MDR
SEGMENT B
4096 CORES
(Typical)
IO--r-....- O z
OUTPUTS
I
L __ _
MDR CLEAR (GATE Gz)
SENSE LINE 1C
r;; -
SEGMENT C
-
-
-
-
-
7522
;;;-1523.;;;j - - "I
as sense· input expander
4096 CORES
for 7520 or 7521
(Typical)
RT
RT
I
I
~NSE LI:E 10 I
I
I
I
I
I
I
SEGMENT 0
4096 CORES
I
(Typical)
I
I
- _______ -.J
-U-
MDR PRESET (GATE)
~--------------------------~vr-----------------------------'
To additional 7522's or 1523', to
provide necessary numbor of sensa inputs
Figure L-Sensing Large Memory Systems
6-47
WIRE·AND
CONNECTION
m
IT
_
JL ______
ITT3671
HI_G_H_-S_P_E_E_D_D_U_A_L__
SE_N_S_E_A_M
__
P_Ll_FI_E_R
SEMICONDUCTORS
HIGH-SPEED DUAL SENSE AMPLIFIER
High-speed dual sense amplifier with built-in
data register and data buffer for application in
coincident-current core memories.
Functional Diagram
The ITT3671 is a dual sense amolifier with a
built-in data register and data buffer. It is designed for use in high speed core memory
systems. It detects bi-polar differential-input
signals from the memory and provides the complete interface between the memory and logic
section.
DL
3
The ITT3671 sense amplifier is completely dc
coupled, and utilizes a "matched-amplifier"
technique. The reference amplifier circuit is
inherently stable and requires no external or
internal frequency compensation.
Features
Customer Benefits
• ±2 mv threshold sensitivity
• System performance
• Threshold voltage independent of temperature and supply voltage variations
• No external frequency compensation
required
• Reference amplifier inherently stable
• Package count, space, cost reduction, increased reliability
• Built-in data register with provisions for external data inputs
• Drive 450 pf load in 15 ns
• Built-in data buffer
• Reduced system power
• Low power consumption
• Reference amplifier less sensitive to noise
• Internal reference voltage attenuator
• Ease of design
PIN OUT DIAGRAM
• Two independent channels
• TTL compatible logic inputs and outputs
TVP·OIO
SENSE INPUT A I
I
SENSE INPUT B I
2
:oi9L
r
DECOUPLING NODE
SENSE
BUFFER OUTPUT I
I
SENSE
vccGROUND
19
DATA IN I
18
DATA IN 2
REGISTER INPUT 2
9
REGISTER OUTPUT 2
10
OATA LOAD
II
BUFFER
INPUT
VREF
TVP 045 .055
STROBE
I
CHANNEL SELECT.J
CHANNEL
SELECT 2
DET- OUT I REG. IN. I
REGISTER OUTPUT I
15
BUFFER OUTPUT 2
DETECTOR OUTPUT 2
RESET'
6-48
•
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
Definition of logic levels
TRUTH TABLE
Dill.
Logic Inputs
Output
Inpul
S
CSI
DI
DL
G
R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
L
ML
ML
X
X
X
H
H
H
H
X
H
X
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
X
H
L
L
L
X
H
H
H
H
L
H
H
X
X
L
L
H
H
L
H
L
H
L
H
L
H
L
H
Reg, In
L
L
H
X
X
H
ML
ML
X
X
ML
ML
X
X
ML
ML
X
X
ML
ML
X
X
ML
ML
X
X
ML
ML
X
X
ML
ML
X
X
X
X
H
H
H
H
0
ML
ML
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
X
H
H
H
L
H
H
H
H
H
H
Input
H
L
X
A
Vm VT max
Vm VT min
Irrelevant
S
VI VIH min
VI VIL max
Irrelevant
'Connect to detector output unless
otherwise noted.
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
H
H
ML=Momentary low followed by a high
Absolute Maximum Ratings
Supply Voltages (See Note 1)
Vcc+ ................................. 7V
Vcc - ................................ 7V
Differential Input Voltage, Vm or V REF • • • • ±5V
Voltage any Input to Ground .......... 5.5V
Storage Temperature Range - 55°C to 150°C
Operating Temperature Range
3671-1, 3673-1 Tc ........ -55°C to 125°C
3671-5, 3673-5 TA ............ O°C to 70°C
Recommended Operating Conditions
Min
Nom
Max Unit
Vcc+ (See Note 1) .... 4.75
5
5.25
-4.75 -5 -5.25
Vcc - (See Note 1)
VREF (See Note 1) .. ±1.5 ±2.1 ±4.5
Block Diagram -
ITT3671
CH
SEL I
DETOUTI
REG IN I
BUFFER OUT I
REG OUT I
IN AI
BUFFER INPUT
IN BI
RESET
VREF
STROBE
IN A2
DATA LOAD
IN 82
REG OUT 2
BUFFER OUT 2
CH
SEL2
OET DATA
OUT2 IN 2
REG
IH2
6-49
v
V
V
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
ELECTRICAL CHARACTERISTICS Over Specified Free-Air Temperature' Range
Vcc+ =SV, Vcc - = -SV, VnEF = -2.1V (Unless Otherwise Noted)
Symb.
Parameter
VT
Differential - Input
Threshold Voltage
Min
Typ
Max
S
9
3
11
Test
Fig.
Unit Test Conditions
TA =2SoC
Vcc+ =SV,
Vee - = -SV
3671-S
4
10
1
13
4.S
9.S
Vee+ =SV ±S%
2
12
Vee - = 5V ±S% 3673-1
4
10
Vee+
1
3673-S
mV
Temp.
Oper.
1
lIB
-2.1V
VREF =
3671-1
3673-1
Differential - input
bias current
Vee - =
13
20
=SV
2
-SV
p.A Vee+. =SV,
Vee -
VID
= -SV,
=
OV
Ito
Differential - input
offfset cu rrent
VIH
High-level input voltage
(strobe and logic inputs)
V1L
Low-level input voltage
(strobe and logic inputs)
VOH
High-level output voltage
(register output)
2.4
4
V Vec+ = 4.7SV,
Vee - = -4.7SV,
IOH = -120 p..A
VOH
High-level output voltage
(detector' output)
2.4
S
V Vee+ - 4.7SV,
Vee -4.7SV,
IOH
High-level output voltage
(buffer output)
2S0
4
p..A Vee+ = 4.7SV,
Vec - = -4.7SV,
VOH = S.2SV
VOL
Low-level output voltage
(register output)
.4
4
V Vee+ = 4.7SV,
Vee - = -4.7SV,
IOL
4.8ma
VOL
Low-level output voltage
(detector output)
.4
S
V Vee+ :::: 4.7SV,
Vee -4.7SV
VOL
Low-level output voltage
(buffer output)
.S
4
V
O.S
2
2
.8
p..A Vee+ = SV,
Vee - = -SV,
VID = OV
4,~
V
4,S
V
=
=
=
Vee+ = 4.7SV,
Vee -4.7SV,
IOL
'6-50
=
= 2SmA
Range
3671-1
3671-S
3673-S
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
ELECTRICAL CHARACTERISTICS Over Specified Free-Air Temperature Range
Vcc+ =5V, Vcc- = -5V, VREF
Symb.
= -2.1V (Unless Otherwise Noted)
Min Typ
Parameter
6
Unit Test Conditions
Strobe, reset,
buffer input
-3.2
input
current
Register 2
channel select
-3.0
-1.6
rnA Vcc - = -5.25V,
rnA
data load
data in
-a.4
2.0
rnA V,L = 0.4V
rnA
High-level input current
(strobe and logic inputs)
IR
High-level
input
current
1
6
Data in
channel select
40
-750
Register
Strobe, reset
buffer input
Data load
80
160
Short-circuit output current -20
register output
los
Test
Fig.
Low-level
-IF
IRn
Max
rnA Vee .. = 5.2SV
rnA Vcc+ = S.25V
Vcc - = -5.25V,
V,M = 5.25V
p.A Vcc+ = 5.25V
/LA
p.A Vcc - = -S.2SV,
p.A VIR = 2.4V
-a0
3
rnA Vcc+ = 5V,
Vcc - = -5.25V,
Vo =.OV -20
IREF
Reference input current
.5
2
rnA Vcc+
Vcc VREF
TA =
Icc-
Supply current from Vcc -
18
2
rnA Vcc+ = 5.25V,
Vcc - = -5.25V,
TA = 25°C
Icc+
Supply current from Vcc+
55
2
rnA Vcc+ = 5.25V
Vcc - = -5.25V,
TA = 25°C
NOTE 1:
These voltage values are with respect to
network ground terminal.
6-51
= 5.25V,
= ~5.25V,
= -2.17,
25°C
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
SWITCHING CHARACTERISTICS, VCN = 5V, Vcc- = -5V, Vr .!
Symbol
Delay Times
From
Input
To
Output
A" A, or
Test
Fig.
Typ
Min
= -2.1V,
Max Unit Test Conditions
ns
RQ=820n
Rx=520n
CQ=50pf
Cx=450pf
15
ns
RQ=820n
CQ=50pf
17
ns
RQ=820n
Rx=520n
CQ=50pf
Cx =450pf
15
ns
RQ=820n
CQ=50pf
12
ns
RQ=820n
Rx =520n
CQ=50pf
Cx=450pf
9
100
ns
RQ=820n
Rx =520n
CQ=50pf
Cx=450pf
X
9
15
ns
RQ=820n
Rx =520n
CQ=50pf
Cx =450pf
X
7
42
ns
RQ=820n
Rx=520n
CQ=50pf
Cx=450pf
0
tPLH (A, 0)
B" B,
tPLH (S, 0)
Strobe
0
8
tPLH (01, 0)
Data in
0
9
tPLH (OL, 0)
Data load
0
8
tPHL (R, 0)
Reset
0
9
tPLH (R, X)
Reset
X
ttPHL (G, X)
Buffer In
ttPHL (A, X)
A" A, or
28
7
B" B,
Transition Times
TA = 25°C
Symbol
Output
Test
Fig.
tTLH(O)
hm(O)
0
0
9
hLH(X)
X
150
Rx = 520n
tTHL(X)
X
12
Cx = 450pf
One response to
differential overload
tORO
Zero response to
differential overload
Max Unit Test Conditions
RQ = 820n
CQ = 50pf
Parameter
tOR'
Typ
Min
TYP.
VCMF Common mode
firing voltage
1.5
6-52
Unit
Test Conditions
V
f = 0.1 to 20 MHz
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
SWITCH ING CHARACTERISTICS,
Vcc+ =SV, Vcc - =SV, VREF = -2.1V
IpLH(A.Q)
IpLH (01.0)
IpLH (S.O)
40
40
30
-
..... 1---
.
40
"
-;;30
20
10
10
- 20
30
E
;:
20
-60
40
20
60
.....
20
- :..-
I-I-.
10
-60
100
I---
-20
20
60
100
-60
-20
20
60
100
TC (OC)
TC(OC)
IpHL(R.Q)
IpHL (OL.O)
PULSE THRESHOLD DATA
40
~30~~~~-r~4-+-~
~30
I
;: 20
10
-
-
;::
10
tt:a~~ttjj
-60
-20
20
60
100
TC (OC)
70
60
50
UJ
:l!
;:: 40
'"
./
30
-60
-20
20
6-53
60
-20
20
60
TC (OC)
IpHL (A.X)
~
-60
100
100
ITT3671
[1IGH-SPEED DUAL SENSE AMPLIFIER
GND
*
SEE
TEST
TABLE
Vcc+
......-+----1-..:.:. * *
965
n
}.-.-
~----+---4~-+~-~~----:-~---~~---- ~TEST
*
GND
Fig. 1-VT
Apply at
InpulA
Test
••• Match impedance of B. and B, to A. and A,.
•• Apply a momentary low then a high.
• Apply Vcc+ to side under test. GND to
. other.
Vt
Vt
Vt
Vt
min.
min .
max ..
max.
+Vt
'-Vt
+Vt
-Vt
-5.25V
Icc'-f
VCC _
min .
min.
max.
max.
5.25V
GND
CSI
GND
WI/RI
!ICC+
vcc+
QI
XI
G
t---..J-=--GND
.....-+---+..:..;R_ GND
GND
Fig. 2 -
PB , 110 = Icc+. Icc -. IREF
6-54
Measure
Output Q
O.4V
O.4V
2.4V
2.4V
max.
max.
min.
min.
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
-5.25V GND
GND
5.25V
QI
105_
GND
G
5V--~~-------+------~
- 2,1V ---':=-+---1
R
GND--~~-------'
GND
GND
5V
105=jl
Note:
GND
Only one output may be shorted at a time.
-
-=-
GND
Fig.3-IOS
TEST PER
TRUTH TABLE
I
Vee-I
CSI
TEST
PER
TRUTH
TABLE
011
p.--'
AI
BI
WIIRI
I
'<-
DL
VREF
lVCC+
~
-{>
XI
G
R
A2
fD
0-
J
CS2
W2
~GND
R2 DI2
I
TEST PER
TRUTH TABLE
6-55
I~
QI
3
B2
VOX
~
X2
Q2
VOL
VOH
l11J
ITT3671
HIGH-SPEED, DUAL SENSE AMPLIFIER
-TEST
4.75V
-4.75V
CSI
4.75V
011
WI/RI
QI
XI
TEST
PER
TRUTH
TABLE
4.75V
G
OL
4.75V
vREF
-2.1V
R
S
A2
B2
R2 012
4.75V
TEST
Diff.
.Test
VOH
VOH
VOH
VOL
VOH
VOH
VOH
VOL
at Wi
at Wi
at Wi
at Wi
at W2
at W2
at W2
at W2
Input
S
CSI
CS2
GND
40mV
40mV
40mV
GND
40mV
40mV
40mV
VIH
VIL
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIL
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
Fig. S-VOH, VOL, V IH, VIL
6-56
GNO
4.75V
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
-5.25V
Vee-
40MV
GND
5.25V
eSI
WIIRI
AI
BI
DL
-2.IV
vREF
S
40MV
GND
Test
A2
B2
Strobe Channel
S
CSl
Select
CS2
Data
01 1
Input
01 2
Data
Load
OL
Reset
R
Buffer Register
Input
tnput
6
R2
IR at S
VIH
VIL
VIL
X
X
X
X
X
W2
IR at CSl
VIL
VIH
X
X
X
X
X
X
W2
IR at CS2
VIL
X
VIH
X
X
X
X
X
W2
IR at 011
X
X
X
VIH
X
VIL
X
X
W2
IR at 012
X
X
X
X
VIH
VIL
X
X
W2
IR at OL
X
X
X
VIL
VIL
VIH
X
X
W2
IR at R
X
X
X
VIH
VIH
VIH
VIH
X
W2
IR at G
VIL
X
X
X
X
VIL
VIL
VIH
W2
- IF at S
VIL
VIH
VIH
X
X
X
X
X
W2
- IF at CS1
VIH
VIL
VIL
X
X
X
X
X
W2
-IF at CS2
VIH
VIL
VIL
X
X
X
X
X
W2
- IF at 011
X
X
X
VIL
VIL
VIH
X
X
W2
- IF at 012
X
X
X
VIL
VIL
VIH
X
X
W2
- IF at OL
X
X
X
VIH
VIH
VIL
X
X
W2
-IF at R
VIH
VIH
VIH
X
X
VIL
VIL
X
W2
- IF at G
X
X
X
VIL
VIL
VIH
X
VIL
W2
- IF at R2
X
X
X
X
VIL
VIH
X
X
VIH
- IF at R2
X
X
X
X
X
VIL
VIL
X
VIL
Figure 6. - IF, IR
6-57
ITT3671
HIG H-SPEED DUAL SENSE AM PLiFIER
5V
-5V
Vcc-
RO
CSI
011
WI/RI
To
oI or 02 -.--+4--+
QI
50
Q
OL
_
...-_ _-t-G
CQ
5V
-2.1 V _V,!!RE:::F+-_-I
S
J
5V
A2
CS2
TO
*
XlorX2
RX
CXI
• Connect same as Channel 1 when testing
Channel 2. CS2 is at GND when Channel 1
is tested.
3.5V
1.5V
-- ------- ------ ------ OV
RESET
(PULSE I)
i
t--200NS--l
90
1112MV
%
-275NS-
Figure 7
I -1
~~S
20NS
1
90%71
~ i'
\
--
40MV
90 %
----- ------
OV
3.5V
OV
VOH
iJI.5V
1--I
I
/
4
t=O
6-58
STROBE
(PULSE 3)
tPLH(AQ)
----- ------ VOL
I
I
I
I
DIFFERENTIAL
INPUT
(PULSE 2)
1_-
----- ------ VO H
\-1.5V
!.. tPHL(AX)
i
REGISTER
OUTPUT a
VOL
BUFFER
OUTPUT X
TR=TF= 15NS
ALL PULSES
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
-5V
VCC-
CSI
5V
*
WIIRI
5V
5V
011
AI
40MV}
BI
DIFF.
OL
-2.1V VREF
S
A2
40MV}
DIFF.
B2
*
5V
'GND channel select of unused side.
jl.sv
I 12005
I"
I
I
I
JI
I
I
tpLH(SQ) .:
-- ------ ' - - - - - -
STROBE
(PULSE I)
\I.SV
o
.1
I
I
I
,.hHL(DL.R)
1 I
I
1-,
I
g
3.SV
VOH
:I I \I.st
I
REGISTER
OUTPUT
1
VOL
Figure 8
I
I 1
~~~ l.I
I
I
I
i
I
I
n~
I
I.S
----- ------
.S
3.SV
OV
~
os
TR=TA=ISos
ALL PULSES
6-59
DATA
LOAD
(PULSE 2)
1113671
HIGH-SPEED DUAL SENSE AMPLIFIER
5V
-5V
VCC -
GNO
5V
CSI
011
WI/RI
RQ
GNO
5V--~~--------+-------
__
- 2.1 V-'.!!"'+--I
GNO--~---------'
GNO
3.5V
~--
------
-----
-----
RESET
(PULSE I)
OV
--. I---r;- tpHLlR,a)
ri
I
_~,. fTLH(Q)
IE
90%
I'
1.5V
, 10%
VOH
%
RESISTER
OUTPUT
10%
I'
~' hHL(Q)
VOL
I
I tpLH (01,0)
, --=.
Q
3.5V
U5V
U----
~I
--*
10%
,
~
,
I
~
DATA INPUT
PULSE 2
- - - - - -1-----
~tf---
9~:lo%
VOH
BUFFER
OUTPUT
X
VOL
I
I
I
_ : , tpHL(G,X)
I'
:L
T
OV
1,·
5V
Figure 9
6-60
3.5V
-----
BUFFER
INPUT
PULSE 3
OV
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
-
The data register outputs, shown .in figure 13,
feature the ability to sink or supply load current and are rated at 3 series 74 loads.
APPLICATION INFORMATION
Reference Voltage Considerations
The open-collector outputs of the data buffer,
shown in figure 12,may be connected to similar outputs to perform the wire-AND function.
These outputs are speCially designed to drive
high capacitive loads.
The threshold level of both channels is determined by applying an external voltage to the
VREF terminal (Pin 21). The ratio of the external threshold reference voltage to the internal threshold reference voltage is 300 to 1.
An internal reference of 7 mV may be established by applying ±2.1V to the VREF input.
The internal threshold reference voltage may
be varied for individual system applications by
adjusting the external reference voltage (see
figure 10).
v
4
./
3
V
V
Input Line Layout Considerations
./
Input sensitivity and device speed require adequate precautions in the routing of signal input
and reference lines to prevent noise pickup.
Bypassing of supply and reference inputs at
the device with low-inductance disc ceramic
capacitors, and the use of good ground planes
to separate logic inputs and outputs from sense
and reference input lines are recommended.
V
"
V
I
o
5
6
7
8
9
10
II
12
13
14
15
16
Fig. 10-lnternal Reference Voltage in nV
Sense-Input Termination Consideration
Termination resistors are intentionally omitted
from the sense-input terminals so the designer
may select resistor values which will be compatible with the particular application. Matched
termination resistors, (R T , Figure 11), normally
in the range of 25 ohms to 200 ohms each, are
required not only to terminate the sense line
in a desired impedance, but also to provide a
dc path for the input bias current. Careful
matching of the resistor pairs should be observed or the effective common-mode rejection will be reduced.
Figure 12
Figure 11
Equivalent Output Circuit
Detector Output
Buffer Output
Output Drive Capability
The detector outputs, shown in figure 12, are
intended to drive the internal data register. Detector output 1 is internally connected to input
of data register 1 and available at pin 1,]. Detector output 2 is not connected internally to
the input of data register 1 but is available at
pint 14. The input of data register 2 is available at pin 9. For dual operation pin 9 is
connected to pin 14; for dual channel operation pin 14 is connected to pin 17, this ANDs
the two sense channels and provide an extra
data register for other system applications.
Fig. 13-Register Output
6-61
ITT3671
HIGH-SPEED DUAL SENSE AMPLIFIER
Logic Input Current Requirements
+vcc
Logic input current requirements are specified
at worse case power supply conditions over
the operating temperature range. The logic
currents are compatible with Series 74 TTL integrated Circuits. Input circuits are shown in
figures 14 thru 17; current requirements are
specified in the dc characteristics table.
3.2k
5k
~--l--+I--t>---o
012
OL
=
3.2 k
5k
Fig. 16-Equivalent Circuit Data Input &
Data Load
Fig. 14-Equivalent Input Circuit Strobe and
Channel Select
r-----------~+vcc
Decoupling Node
An 0.01 uf capacitor may be placed between
pin 23 and ground to enhance the stability of
the input amplifiers.
=
G
Fig. 17-Equivalent Buffer Input Circuit
CYCLE 2
CYCLE I
READ I
WRITE
READ 0
WRITE
RESET
Fig. 15
Equivalent Buffer Input Buffer
I'
10 CT SIGNAL
I
STROBE
I CHANNEL
r~
SELECT
I
Fig. 18-Typical System
Timing Diagram
/"
I
DATA REGISTER OUTPUT
o
.6
.2
.8
TIME
6-62
1.0
IN
1.2
nS
1.4
1.6
1.8
2.0
I
-
rIlrll
..L.L
ITT9614
DUAL DIFFERENTIAL LINE DRIVER
SEMICONDUCTORS
-------------Pa-c-k-ag-e-:-O-u-a-I-In---u-ne-an-d-F-Ia-t-P-ac-k
DUAL DIFFERENTIAL
LINE DRIVER
Logic Diagram
• Single 5 Volt Supply
• TTL Compatible Inputs
~15
9~
• Output Short Circuit Protection
• Input Clamp Diodes
• Output Clamp Diodes for Termination of Line
Transients
14
10
~~13
11
---i>--12
vee = Pin 16
Gnd = Pin 8
o Complimentary Outputs for 'NAND', 'AND'
Operation
Fig. 1',
• Uncommitted Collector Outputs for Wired-OR
Application
• Military Temperature Range
ABSOLUTE MAXIMUM RATINGS (above which
the useful life may be impaired)
The ITT9614 is a TTL compatible Dual Differential Line Driver. It is designed to drive. transmission lines either differentially or singleended, back-matched or terminated. The outputs are similar to TTL, with the active pull-up
and the pull-down split and brought out to adjacent pins. This allows multiplex operation
(Wired-OR) at the driving site in either the
single-ended mode via the uncommitted collector, or in the differential mode by use of
the active pull-ups on one side and the uncommitted collectors on the other (See Fig. 3).
The active pull-up is short circuit protected and
offers a low output impedance to allow backmatching. The two pairs of outputs are complementary providing "NAND" and "AND" functions of the inputs, adding greater flexibility.
The input and output levels are TTL compatible
with clamp diodes provided at both, input and
output, to handle line transients.
Storage Temperature ..... -65°C to +150°C
Temperature (Ambient) Under
Bias ................... -55° to +125°C
Vee1 Pin Potential to Ground
Pin ................... -0.5Vto +7.0 V
Input Voltage Referred to Ground
(Attenuator Inputs) ................ ±20 V
Voltage Applied to Outputs for
High Output State without
Active Pull-up ........... 0.5 V to + 13.2 V
Voltage Applied to Strobe .. --0.5 V to +5.5 V
Lead Temperature (Soldering,
60 seconds) ...................... 300°C
Internal Power Dissipation (Note 1)
Ceramic DIP .................... 730 mW
Flatpak •........................ 570 mW
NOTE
1. Rating applies to ambient temperatures up
to 70 u C. Above 70°C derate linearly at 8.3
mWrC for the Ceramic DIP and 7.1 mW/oC
for the Flatpak Package.
6-63
1119614
DUAL DIFFERENTIAL LINE DRIVER
ELECTRICAL CHARACTERISTICS 9614-5
(0" C to +75° C, Vee =5.0V ±5"1o)
Limits
Symbol
Characteristic
VOL
Output
Low
Voltage
VOR
Output
High
Voltage
Output
Ise
"Short
Circuit"
Current
'eEx
Output
Leakage
Current
IF
Input
Forward
Current
la
Input
Reverse
Current
VIL
Guaranteed
Input
Low
Voltage
VIR
Guaranteed
Input
High
Voltage
DoC
.Min. Max.
Min.
200
450
2.4
2.4
+25°C
Typ. Max•
-40
450
3.2
450
mV IOL =40mA
Vee =4.75V
mA VOUT =O.OV
Vee =5.25V
100
200
-1.10-1.60
-1.60
60
100
35
Conditions &
Units Comments
V lOR =-10mA
Vee =4.75V
2.4
-90 -120
10
-1.60
+75°C
Min. Max.
!LA VeEx =5.25V
Vee =5.25V
mA VF =0.45V
Vee =5.25V
p.A Va =4.5V
Vee =5.25V
'.
0.85
1.9
1.3
1.8
0.85
0.85
1.6
1.5
-0.8 -1.5
V Vee :;::5.25V
V Vee =4.75V
V IOLe =-40mA
Vee =5.25V
. VOLe
Clamped
Low
Output
Voltage
Icc
Supply
Current
33
48.7
mA Inputs =OV
Vee =5.25V
Imax
Supply
Current
46
70
mA Inputs =0 V
VMAX =7.0V
tPLR
Turn-Off
Time
14
30
ns CL. =30pF
Vee =5.0V
tPHL
Turn-On
Time
18
30
ns See Fig. 4
VM =1.5V
VIC
Input
Clamp
Voltage
-1.0 -1.5
6-64
V Vee =4.75V
Ire =-12mA
,
ITT9614
DUAL DIFFERENTIAL LINE DRIVER
ELECTRICAL CHARACTERISTICS 9614-1 ..
(-55° C to +125° C, Vee =5.0V ±10%)
Limits
Symbol
Characteristic
-55°C
Min. Max.
Min.
+25°C
Typ. Max.
+125°C
Min. Max.
400
400
Conditions &
Units Comments
VOL
Output
Low
Voltage
VOH
Output
High
Voltage
Ise
Output
"Short
Circuit"
Current
leEx
Output
Leakage
Current
IF
Input
Forward
Current
IR
Input
Reverse
Current
VIL
Guaranteed
Input
Low
Voltage
VIR
Guaranteed
Input
High
Voltage
VOLe
Clamped
Output
Low
Voltage
lee
Supply
Current
34
48.7
rnA Inputs =:0 V
Vee =5.SV
Im• x
Supply
Current
46
65.7
rnA Inputs =0 V
VMAX =7.0V
tPLH
Turn-Off
Time
14
20
ns CL =30pF
Vee =S.OV
tPHL
Turn-On
Time
18
20
ns See Fig. 4
VM =1.5V
VIe
Input
Clamp
Voltage
400
200
mV 10L =40mA
Vee =4.SV
).
2.4
2.4
-40
0.8
2.0
1.7
rnA VOUT =O.OV
Vee =S.SV
-90 -120
10
-1.60
V 10H =-10mA
Vee =4.SV
2.4
3.2
p.A VeEx =12.0V
Vee =S.5V
100
200
'-1.10 -1.60
-1.60
rnA VF =O.4V
Vee =5.SV
35
60
100
p.A VR =4.5V
Vee =5.SV
1.3
0.9
0.8
V Vee =5.5V
1.5
1.4
-0.8 -1.5
-1.0 -1.5
6-65
V Vee =4.5V
V 10Le =-40mA
Vee =S.5V
V Vee =4.5V
he =-12mA
11T9614
DUAL DIFFERENTIAL LINE DRIVER
Switching Circuit and Waveforms
tLj~l_UT
r
V,N
1
510
5 ....
fL
J'~:_
INPUT PULSE
Frequency = 500 kHz
Amplitude = 3.0 ±0.1 V
Pulse Width = 110 ± 10 ns.
t, = t f :5 5.0 ns
---+""\.1
VOUT (A)
VOUT Ie)
Fig. 2
TYPICAL ELECTRICAL CHARACTERISTICS
OUTPUT LOW CURRENT
VERSUS
OUTPUT LOW VOLTAGE
100
V/
TA a2S·C
.~
80
VCc·S." .~
,
a...
~
~
40
~¢
",'
=r
~
Ycc=s.OV
~ 60
VCc· 4 •5V
I-so
I
<5
~ 20
I
-80
o 1/
a
0.1
0.2
0.3
0.4
0.5
VOL -OUTPUT VOLJAGE-vOLTS
0.6
0.7
--
~V
.,
3.0
~
o
=:- 2.5
i - ro-
~
~ 2,0
>
I
~
1.5
~ 1.0
/ / /
V If
§
f
'"" '"
I
VoH- NO LOAD
Vee -s.ov
o :,'
"
~
LOGIC LEVELS VERSUS
AMBIENT TEMPERATURE
3.5
I II
r.·25·C
~
...z
?
OUtPUT HIGH CURRENT
VERSUS
OUTPUT HIGH VOLTAGE
§
V
> 0.5
Val Cll tOl .40f.A,,'
I I I
1.0
2.0
3.0
VOH -OuTPUT VOLTAGE- VOLTS
6-66
4.0
-60
-20
a
20
60
100
T.6. - AMBIENT T~MP£aATURE ··c
140
ITT9614
DUAL DIFFERENTIAL LINE DRIVER
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
VERSUS
SUPPLY VOLTAGE
60
NO LOAD
TA "25°C
/;
50
.,
1/
~'?
.
l.e'
a
2.0
1/
"
~
4.0
6.0
8.0
20
-60
10
a
-20
20
60
-----
4.0
TA"2S-C -
,-
TA"SSoC _
-
~
~ 10 ~
-60
g
20
Vee· S.OV
VCC a4 .5V _
~ 2.0
t
?
60
vcc'51-
~
r
a
a
100
140
TA - AMBIENT TEMPERATURE·-C
o
1.0
a
0,5
1.0
V IN
1.5
2.0
2.5
3.0
-INPUT VOLTAGE- VOLTS
3.5
a
0.5
10
1.5
2.0
2.5
3.0
V IN -INPUT VOLTAGE - VOLTS
Applications
Differential Mode Expansion
.5 V
loon
5
6--=-1
7
lOon
15
9
10
"
10
5
~
...., ~---20
5.0
4.0
~ 3.0
V
;;;
2.0
TRANSFER CHARACTERISTICS \
VERSUS
SUPPLY VOLTAGE
5.0
tpHL
I
1,0
f - FREQuENCY - MHz
lA a 2S0C
g
~
i-
0.5
0.2.
TA 2 12.S-C
5
20
0.1
"CC 2 5.0V
tJ)
a
v
a
140
100
TRANSFER CHARACTERISTICS
VERSUS
TEMPERATURE
5.0
30
~
40
TA -AMBIENT TEMPERATURE·-C
-SUPPLY VOLTAGE- VOLTS
Vcc: 5 .OV
I,
g;
iil
u
u
U
-CL 230pF
~
!
/
~
,!i 25
PROPAGATION DELAY TIME
VERSUS
TEMPERATURE
40
~
/
60
JJ
Vee
I
80
E
20
10
a
30
~
Vce eS .CV
CL 230 pF
!Z
!
"'~
.#
I#'
u
u
~~CT"p5U~; OPE~
!Z
O.';:;~
~
100
3'
E
&~~~
(:JQ;-
SUPPLY CURRENT VERSUS
OPERATING FREQUENCY
SUPPLY CURRENT VERSUS
TEMPERATURE
40
14
Expand by tieing "NAND" outputs together and by
tieing active pull· Up" "AND" outputs togetheL
The drivers can be inhibited by taking one input to
ground.
12
13
Fig. 3
6-67
3.5
ITT9614
DUAL DIFFERENTIAL LINE DRIVER
Typical Reflection Diagram
200
160
VCC =5.0V
TA = 25°C
./
I
/..
/
120
«
T
80
f-
~ 40
~
~
LOW STATE OUTPUT DEVICE
CHARACTERISTICS
/'
II
a:
a:
B
0
/
-40
~~
j
:::J
o
...... -120
V
V
(
HIGH STATE OUTPUT DEVICE_
-- CHARACTERISTICS
o
1--- 80
~
V
:::J
.L
1
-160
200
-5
......
/
/
-4
-3
-2
-1
1
0
VO UT
-
2
3
4
5
6
7
8
9
10
OUTPUT VOLTAGE - VOLTS
Fig. 4
CIRCUIT SCHEMATIC
Vee =Pin 16
GND=Pin B
~ I'
15
9
10
II
l4-~--~->--------~-----4---4--.w..~--4---H.
8.36 K
1(15)
.
150n.
9
12
15
7
1
3
l~o~.l1
5
_
2.5K
;H--it~--il---+-----+---t--''--t::::.
m
2
6
14
4
Vcc=Pin 16
GND::Pm B
SGND
2615 ONLY
6-72
ITT9615
DUAL DIFFERENTIAL LINE RECEIVER
SWITCHING TIME TEST CIRCUIT
_--~·r-+3.0V
WAVEFORMS
VCC
· · --f
=l
=:';, r .-:....'C
o.ov
-----3.0V
+3.0V
.,
o.ov
-lc---~
("USE VIN OR VIN. GROUND OTHER INPUT.)
-----,1
Fig. 4
Photograph of a 9615 switching
differential data in the presence
of high common mode noise.
Fig. 5
VERTICAlo2.0V/DiV. HORIZONTAlo50ns/DIV.
STANDARD USAGE
DRIVER SYSTEM
RECEIVER SYSTEM
LINE
TTL LOGIC
uA9615
Fig. 6
FREQUENCY
RESPONS~
FREQUENCY RESPONSE
VERSUS CAPACITANCE
CONTROL
100'111
'"
RESPONSE
CONTROL PIN
"
-=
loo.§Efrnl§~E3!I§.
,all
Fig. 7
6-73
,01
0,1
CR - CAPACITANCE -IlF
1.0
10
-3"'
1.5V
ITT9615
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL ELECTRICAL CHARACTERISTICS
OUTPUT LOW VOLTAGE
VERSUS
OUTPUT LOW CURRENT
..
s.
T,,"25"C
OUTPUT HIGH VOLTAGE
VERSUS
OUTPUT HIGH CURRENT
•
r- v~cJ .1.",
:rYeP:;;' !-
,I'-.
k::;:
rr- r-
vcc"'~~rl
Vcc.s.,,-
-1
~r--r-
/
,
s.,
VIN
J
.'
•
~
i" •
'7
;
~2.D
VIN~n!!.
Jc.Jv
rA"-we
-,....
0
0.1
D.2
D.l
,..
"cc···sv
1
!;;: VOIFF-Z. OY
1
I
\
0,0\1
'."_Y..I.."Ib..•b:.•b~o;".,b.b.~.b,,bd,,_
"eM - COMMON MOot VOlTACf: -VOLtS
POWER SUPPLY CURRENT
VERSUS
_
POWER SUPPLY VOLTAGE
!'OWER SUPPLY CURRENT
VERSUS
AM81ENT TEMPERATUIIE
I
I .T,,'25'C
•
2.0
],0
M
5.0
~
,.,
I.'
6.0
Vee-POWER SUPPLYVOt.TACE-VOL1S
7.0
l.O
..•
,
...,
...,-as
INPUT CURRENT VERSUS
INPUT VOLTAGE
1/
Vcc· S' W
UNTtSTEDINPUT'OV
TA~ Z5~C
/
/
1/
/
-20
15
I)
-s
D
,
D
15
20
Z5
VIN -INPUTVOLTAGE-VOl15
SWITCHING TIME
VERSUS
AMBIENT TEMPERATURE
Vcc -S.w
II
V1N "'VtD+3V
"..
RL -l.na
\"7 y
vec''''v
~,"'V_
1.0
~
...c::;
'.
"
"'
,/
\.V:
·'i,ulS·tcc
~V
I
, ./
00 120
TA'~ C
/
,.INPUts "Vee
'INPUts"OV
~
60
_1 JCC'5~OV
,
•
,
V'N.-STROBE INPUTVOI,.TACE-VOLlS
70
~
VIN -STROBEINPUTVOl,TAGE-\lOt.1S
VCC ·5.,J
Vee
4.,
0.4
"ee· S•ov
>§ 1.0
I.'
20
Vcc'uv
-0.20.1
~ I.'
2•
•
•
...
Vcc
V
g
s
I~~~F:I~~.~V
0
STROBE INPUT-OUTPUT
TRANSFER CHARACTERISTIC
VERSUS Vee
\!!u
\
~
INPUT·OUTPUT- TRANSFER
-CIiARACT~RISYlC _ _
VEIISUS TEMPERATURE
-0.4 -0,)
s.'
~
VOL
TA·AMBI£NTTEMPERATURE.·C
, I
• I
..,
TA 25'C
T,,'-5"C
1.0
IOH -OUTPUT HICH CURRENT-mA
OUTPUT VOLTAGE VERSUS
COMMON MODE VOLTAGE
, ::t: ~
1.5
::.,§
~
STROBE INPUT·OUTPUT
TRANSFER CHARACTERISTIC
VERSUS AMBIENT TEMPERATURE
~·U ..:ih
~
0
vcc·,·ov
~
5
YIN -INPUTVOLTAG( -VOL""
TA "l25'e
!I
!v
1~~~;5:~.7:
~ 2.0
YIN - INPUTVOLTAG[-VOLTS
S••
rp. .
VOH
•
• I
o T .I'25 C
, 1"• 1,.I,,·C f ,
f-- Vee' s.lsv
,
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1cC ·4r
-.V
,
I
..,..., I ".1
'.1
~ 2.5
0.' i--~
..• ec ". ov
2kE..,
TA '25"t
I
Vee ·S.OV
..
'.
INPUT·OUTPUT TRANSFER
CHARACTERISTIC
VERSUS Vee
,'::b
, ,
H-t-
I-- I--
l.' I............
/"'CC· 4•5\1
"
IOL" OUTPUT LOW CURRfNT • mA
OUTPUT VOLTAGE VERSUS
AMBIENT TEMPERATURE
I.'
TA"ZS"e
'IN'UT.v~1
-ltUTj'OV r-
•
-110-«1 -20
0
20
CI
60
80
'",AMBIENT1I:MPERATURE
6-74
lA'
1..... -
100 120 ICI
_·c
....... ....... "..
1-
•-to
-CJ
Rl '191m
V
CL'~
20
0
20
II
oil
10
I)
OJ 120 ICI
fA -AMBIENT TlMPERATLIRf:_·C
_I
mm. ______________
IT_T_7_5_3_24
MEMORY DRIVER WITH DECODE INPUTS
~~
SEMICONDUCTORS
DUAL-IN-L1NE PACKAGE (TOP VIEW)
G~ramic
MEMORY DRIVER
WITH DECODE INPUTS
OUTPUT
13 y
II
PERFORMANCE
•
•
•
•
•
(SOURCE)
SOURCE
COLLECTORS
OUTPUT
X
(SOURCE)
OUTPUT
w
fast switching times
400-mA output capability
internal decoding and timing circuitry
dual sink/source outputs
output short-circuit protection
(SINK)
AOORESS
INPUT D
GND 1 and GND 2 are to be used in parallel
NC-No internal connection
DUAL-IN-LINE PACKAGE (TOP VIEW)
Plastic'
EASE OF DESIGN
•
•
•
•
•
•
r
TTL or DTL compatibility
eliminates transformer coupling
reduces drive-line lengths
increases reliability
minimizes external components
choice of flat or dual-in-Iine packages
CfTPUT
A
A~~~~~
I
Lc
r
E 4
TIMING
INPUTS F
LG
Description
The ITT75324 is a monolithic memory driver
with decode inputs designed for use with magnetic memories;',The device contains two 400milliampere (source/sink) switch pairs, with
decoding capability from four address lines.
Two address inputs (8 and C) are used for
mode selection, i.e., source of sink. The other
two address inputs (A and D) are used for
switch-pair selection, i.e., output switch-pair
Y/Z or W/X respectively.
OUTPUT
12 (SOURCE)
II
SOURCE
COLLECTORS
OUTPUT
10 X
(SOURCE)
OUTPUT
9 W
(SINK)
ADDRESS
INPUT D
FLAT PACKAGE (TOP VIEW)
r 0@
A
ADDRESS B
INPUTS
@OUTPUT
14 Z
(SINK)
@VCC
Lc0
®OUTPUT
12 y
(SOURCE)
rEG)
@SOURCE
II COLLECTORS
The sink circuit is composed of an inverting
switch with a transistor-transistor-Iogic (TTL)
input. The source circuit is an emitter-follower
driven from. a TTL input stage.
INPrG0
The ITI75324 is characterized for operation
from O·C to 70·C.
ADDRESS(£)
INPUT
6-75
(SINK)
B 2
T1MINGF0
®x
10
o
9
0
OUTPUT
(SOURCE I
OUTPUT.
W
(SINK)
GND
ITT75324
MEMORY DRIVER WITH DECODE INPUTS
Standard positive logic applies with the following definitions used for specifying digital-level
signals:
TRUTH TABLE
Inputs
A
0
0
1
1
x
x
x
B
0
1
1
0
x
x
x
C
1
0
0
1
x
x
x
Outputs
Timing
Address
D
1
1
0
0
x
x
x
E
1
1
1
1
0
x
x
Sink Sources Sink
F G
W
1 1
1 1
1 1
1 1
x x
0 x
x 0
On
Off
Off
Off
Off
Off
Off
LOW VOLTAGE = LOGICAL 0
HIGH VOLTAGE = LOGICAL 1
X
Y Z
Off Off Off
On Off Off
Off On Off
Off Off On
Off Off Off
Off Off Off
Off Off Off
Absolute Maximum Ratings Over Operating
Case Temperature Range (unless otherwise
noted)
NOTES:
1. X = Logical 1 or logical O.
2. Not more than one output is to be allowed to
be ON at one time: When all timing inputs are
at a logical 1, two of the address inputs must
be at logical O.
Supply voltage Vee (See Note 1) ........ 17V
Input voltage (See Note 2) .............. 5.5V
Operating case temperature range O'C to 70·C
Continuous total power dissipation
at (or below) 70'C case
temperature ..................... 800mV
Storage temperature range .. -65'C to 150'C
NOTES:
1. Voltage values are with respect to network
ground terminal.
2. Input signals must be zero or positive with
respect to network ground terminal.
ELECTRICAL CHARACTERISTICS (unless otherwise noted, Vee
VlnW
Vln(O)
hn(1)
hnw
hnCo)
hn(o)
Vc•• t )
Vc ••t)
I.ff
lee
lee
Icc
Parameter
Input voltage required to
ensure logical 1 at any input
Input voltage required to
ensure logical 0 at any input
Logical 1 level address input
current
Logical 1 level timing input
current
Logical 0 level address input
current
Logical 0 level timing input
current
Sink saturation voltage
Source saturation voltage
. Output reverse current
(off state)
Supply current, all sources and
sinks off
Supply current, either sink
selected
Supply current, either source
selected
Min
3.5
Typ*
=
Max
14V, Tc
= O'C to 70'C)
Unit Test Conditions
V
0.8
V
200
p..A
Vln - 5V
100
p..A
Vln - 5V
-6
mA
Vln -
OV
-12
mA
Vln -
OV
0.75
0.75
0.85
0.85
V
V
125
200
p.A
1.lnk = 420 mA, RL - 53n
I••urce = -420 mA,
R,. =47.5n
Vln - OV
12.5
15
mA
Vln
30
40
mA
25
35
mA
"These typical values are at Tc = 25'C.
6-76
-
OV
ITT75324
MEMORY DRIVER WITH DECODE INPUTS
Switching Characteristics, Vee
tpd(t)
tpd(O)
tpd(t)
tlld(O)
t.
= 14 V, Te = 25°C
Parameter
Propagation delay time to
logical 1 level, source output
Propagation delay time to
logical 0 level, source output
Propagation delay time to
logical 1 level, sink output
Propagation delay time to
logical 0 level, sink output
Sink storage time
Min
Typ
Max
Unit
Test Conditions
90
50
ns
ns
RI.; ....
53n,
RL , = 500n,
CL = 20 pF
110
ns
40
ns
70
ns
=
RI.
CL
= 53n,
= 20pF
Thermal Information
The ITT75324 is designed to be used at a case
temperature not to exceed 70°C. Under this
condition, infrared microradiometer and X-ray
studies indicate that a safe junction temperature
is maintained under specified worst-case conditions.
ITT75324 circuits should be mounted so that
minimum thermal resistance is achieved. A
thermal compound should be used between
bottom of the flat
package and a heat sink.
This, in conjunction with unrestricted forced
air flow across the heat sink and package, has
been found to adequately satisfy thermal requirements. No thermal compound is required
with the dual-in-line package. Air flow should
be across the short dimension of either
package.
r---~~----------~--~----------~----~VCC
Schematic:
../'----~O--o OUTOUT W
(SI~K)
~
TlMING{
INPUTS
G'
OUHUTX
· ......----+-I_ISOl ~CE)
ADDRESS.{
INPUTS
..-._____._*'"-----++--o SOUqCE
~ro;S;LECT
COLLECTORS
(SOURCf/SINK)
~ C o--I---~-l-4
SWITCH.pAIR
SELECT
L--.
.......---+-_ OUT?UT V
(SOURCE)
00-+--1-1
..,-----+- OUT"UT
Z
(SIIIoK)
~--------------~--_--~~--~----~GND
ITT75324
MEMORY DRIVER WITH DECODE INPUTS
PARAMETER MEASUREMENT INFORMATION
D-C Test Circuits*
>-------<>0 .,4V
TEST TABLE FOR lin(u)
Test
Apply. 3.SV
B,
B,
A,
A,
A,
A,
A,
C.
C.
0,
0,
B,
B,
B,
E.
E.
E,
E,
C,
C,
C,
Ground
tn(u)
°
°
F, and G
F, and G
F, and G
F, and G
0, F, and G
0, E, and G
0, E, and F
A
A and
A and
Band C
B and C
E
F
G
°
B
C
E
F
G
NOTES:
1. Check Vin(I) and Vin(o) per Truth Table.
2. Measure hn(u) per Test Table.
3. When measuring lin(1), all other inputs are at
ground. Each input is tested separately.
oSV
,..---- ----------- ----.,A,-,..
: TIMING INPUTS
IE
Vee
y--
='C,,-c_ _....
o.,ev
_ _ _ _---<>c+14V
·F'-2KO
±S.O
±10
V
70
90
db
=
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Input Offset Current
Input Bias Current
Input Resistance
40
Vs
Rs:::;;10KO
25
150
p.VIV
20
100
200
500
nA
nA
0.5
1.5
p.A
TA
Kn
TA
100
7-3
= ±15V
Rs:::;;10KO
TA = +125°C
= -55°C
= -55°C
ITT709, ITT709-A
HIGH PERFORMANCE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS ITT709-5
(Vs
= ±15V, TA = 25°C unless otherwise specified)
Parameter
Min.
Max.
Typ.
Units
Input Offset Voltage
2.0
7.5
Input Offset Current
100
500
nA
0.3
1.5
p.A
Input Bias Current
mV
Conditions
Rs :::;;1 OK,
±9V:::;;Vs:::;;±15V
50
250
KO
150
0
15,000
45,000
Output Voltage Swing
±12
±10
±14
±13
Input Voltage Range
±a.o
±10
V
90
db
Rs:::;;10K
Rs:::;;10K
Input Resistance
Output Resistance
Large-Signal Voltage Gain
Common Mode Rejection Ratio'
65
RL;;:::2K,
Vont
±10V
=
V
V
Supply Voltage Rejection Ratio
25
200
p,VIV
Power Consumption
ao
200
mW
Transient Response
Risetime
0.3
1.0
p,s
10
30
%
Input Offset Voltage
10
mV
Input Offset Current
750
nA
2.0
p,A
Overshoot
RL;;:::10K
RL;;:::2K
=
=
=
=
=
=
V!n
20mV,
RL
2KO,
C,
5000pF,
R,
1.5KO
C,
200pF,
R,
500
CL:::;;100pF
The following specifications apply for 0°C:::;;TA:::;;+70°C
Input Bias Current
Large-Signal Voltage Gain
Input Resistance
12,000
Rs:::;;10K,
±9V:::;;Vs±15V
RL;;:::2K,
Vont
±10V
=
35
kO
PROTECTION CIRCUITS
OUTPUT SHORT·CIRCUIT PROTECTION
"
~
-'
'"
D,
200~
'09
) +
INPUT BREAKDOWN PROTECTION
LATCH·UP PROTECTION
SUPPLY
OVERVOL TAGE
PROTECTION
"
>-~-EOU7
Pin numbers only apply to metal can package.
ITT709
I
ITT709-A
HIGH PERFORMANCE OPERATIONAL AMPLIFIER
DEFINITION OF TERMS:
LARGE-SIGNAL VOLTAGE GAIN-The ratio of
the maximum output voltage swing with load
to the change in input voltage required to drive
the output from zero to this voltage.
INPUT OFFSET VOLTAGE-That voltage which
must be applied between the input terminals
to obtain zero output voltage. The input offset
voltage may also be defined for the case where
two equal resistances are inserted In series
with the input leads.
OUTPUT VOLTAGE SWING-The peak output
swing, referred to zero, that can be obtained
without clipping.
OUTPUT RESISTANCE-The resistance seen
looking into the output terminal with the output
at null. This parameter is defined only under
s'mall signal conditions at 'frequencies above a
few hundred cycles to eliminate the influence
of drift and thermal feedback.
POWER CONSUMPTION-The DC power required to operate the amplifier with the output
at zero and with no load current.
SUPPLY VOLTAGE REJECTION RATIO-The
ratio of the change in input offset voltage to
the change in supply voltage producing it.
INPUT OFFSET CURRENT-The difference in
the currents into the two input teriminals with
the output at zero volts.
INPUT RESISTANCE-The resistance looking
into either input terminal with the other
grounded.
INPUT BIAS CURRENT-The average of the
two input currents.
INPUT VOLTAGE RANGE-A range of voltage
which, if exceeded on either input terminal,
could cause the amplifier to cease functioning
properly.
TRANSIENT RESPONSE-Te closed-loop step
function response of the amplifier under smallsignal conditions.
INPUT COMMON MODE REJECTION RATIOThe ratio of the input voltage range to the maximum change in input offset voltage over this
range.
PEAK OUTPUT CURRENT - The maximum
current that may flow in the output load without
causing damage to the unit.
GUARANTEED ELECTRICAL CHARACTERISTICS ITT 709-A
OUTPUT SWING
VOL.TAG£ GAIN
70k RL2: 2 kQ I
I _~
~~.s TA < tl251lC
~ 60k
v-
~40k
~30k
./
10k
k--
.....
i20k
r
~i~\C~"
~
t9
13,
12
11
10
-55°C
e>
j20
.....
~ 15
... .....
~IO
'"
o.
.....
.
14
I-
en
j - t- t-
!5
~,0
l!i
.
9
UJ
~
I
90
-
z
I~o
f-
-
Q 10
,~~i;;.-
10
9
M~~~~~~ t"-
13
14
10
II
12
SUPPLY VOLTAGE - ! VOLTS
.,
~~
z'"
I-'"
8~ 6
i4
I
11
12
13
SUPPLY VOlTAGE-iV
-55·C' TA' +12SoC
~8
!
"C-rl
I
i-
l..i-
if-
~,O
,/
J i'\C~" I-""
i- f-""
10
~
I-'"
1
,/
~30
I
-b~'''' ~.J/I"
,
./
IX
.
I
I
r--
i--'"
INPUT C _ MOOE'yOLTAGE RANGE
POWER CONSUMPTION
TA - 25"'C
MINIMU
RL"'OK
~
1~
SUPPLY VOLTAGE - ! V
11
'TA~+125·C
~2~
,
L
'\l~
~~i-'~
~~Ok
..
...en
MI 1M II
~
.....
i-i--
i2
14
09
15
7-5
12
13
14
10
II
SUPPLY VOLTAGE-!VOLTS
ITT709 , ITT709-A
HIGH PERFORMANCE OPERATIONAL AMPLIFIER
GUARANTEED ELECTRICAL CHARACTERISTICS ITT709-1,
VOLTAGE GAIN
RL !ZK
-5S·C ioTA 1+12S-C
~ 60K MIC709-t
V
~50K
.;!
~ 25
MAXIMUM
~20 f-
B 15
co:
"'~ 10
030K
9
.
~20K
~
MINIMUM
10K
c'
g
12
·13
14
10
SUPPLY VOLTAGE - t VOLTS
"
MINIMU,M
RL- 2K
0
g,o
.'~8
. ~~
1",6
0'"
uj!
--
I-
MIIM M
I-
g4
5·
.."'"
0
..... _r-
J,INIMUM
RL-IOK
>-r-
~
>
-
>-
--
--
I-
V
S40K
~
z
Y
!' '''' -~
a:
"'0
..
I
.~
MAXIMUM
100
~
5010
.....
--
TY ICAL
g
10
12
13
14
SUPPLY VOLTAGE - tVOLTS
"
GUARANTEED ELECTRICAL CHARACTERISTICS ITT709-S
J
VOLTAGE GAIN
RL' 2K
O"TA _+70MIC709-5
z
:c
'"~IOK
~
g
.....
..... ~ I-""
IL
~5K
_......
..... ~"MUM
it
~20
I-
~
~
IL
II
>-
..... >-
15
C
...c"
10
-
r- ~,'N'MUM
RL-IOK
"'
0
9
25
I-
12
13
14
SUPPLY VOLTAGE- tVOLTS
-
~
i--
MiNIMU.M
RL~2K
,. 10
~
0
on
Z
on
INPUT COUIION MODE VOLTAGE RANGE
OUTPUT VOLTAGE SWING
.,
~8
. ai
iw
6
0"
uC
MI IMUM
>-
:.--r-
:.-- f-
~4
g
5
0
.,
'~'O
"'
12
10'
II
12
13
14
SUPPLY VOLTAGE- tVOLTS
9
09
13
14
II
12
10
SUPPLY VOLTAGE -! VOLTS
FREQUENCY COMPENSATION CURVES ITT709-A. ITT709 -1 .ITT709-5
FREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS
1111 11111 11111 I
ID
~.
z
cOO
'"~
~ 40
!l
~
III
VS·:!.ISV
TA~25·C
RL~IOKn
CI'"IOOpF, RI'"1.5Kn.C2=3pF
III
'J11
III
!III
III
III
CI= 5000pF,RI=15Kn,C2'" ZOOpF
0
9
u_ 20
FREQUENCY-Hz
III
CI'"500pF,R.'"I.SO,CZ'"20pF
20
0
I:!
TA'"25·C
CI'"IOpF, Rl c O,C2 -3pF
III
OUTPUT VOLTAGE SWING AS A FUNCTION OF
FREQUENCY FOR VARIOUS COMPENSATION NETWORKS
VS·~15V
III
1111
III
III
1111 I 1111 I 1111 I 1111
100
IK
10K
lOOK
FREQUENCYaHz
7-6
1M
10M
ITT709, ITT709-A
HIGH PERFORMANCE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES In709·A
130
Z.·..
.....
TA- -55-C
5
~
~0
nil'
-1.0
-60
INPUT BIAS CURRENT AS
A FUNtnON OF AMBIENT TEMPERATURE
-20
1! 400
1.00
i
lOO
~
95
a
i-"""I"'"
~
20
100
60
'II II.
~
-f19V
140
INPUT OFFSET CURRENT AS
A FUNCTION OF AMBIENT TEMPERATURE
-
~ 6.8
::J
~O.6
>
1= 0.4
i02
0
"
12
13
14
0
-60
I
!Ii
1.0
a
~70
::>
§
'~"
110
-
'60
i§
V V
I
140
.0.1
i
...,
-2.0
2.0
TEMPERATURE-"C
60
100
140
POWER CONSUMPTION AS A
FUNcnON OF AM81ENT TEMPERATURE
3.0
tl
~
20
-20
9 -5
.
NO
iTA· +125·C
>I
OUTPUT VOLTAGE SWING
AS A FUNCTION OF LOAD RESISTANCE
VOLTAGE GAIN AS A
FUllCTION OF AMIIENT TEMl'EMl'URE
VOLTAGE TRANSFER CHARACTERISTIC
VS·:t15V
1.0 RL',.oK
I!- 'TA'
1.5
0.1
20
TIME-""
7-7
I
Ie
100
CLOSED-LOOP GAIN
W\
ITT709, ITT709-A
HIGH PERFORMANCE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
VOLTAGE TRANSFER CHARACTERISTIC
f
Vs =± 15V
10 RL-IOK
If'"" TA " 25°C
TA" +125°C
TA=-55°C I"5
..
...,
~
0
,
>
'"
.~
0
I-
-'
>
..
-51-- -TA'O";;:
:>
'rt
~TA'+70·
;;TA, +25·
VS·:t 15V
:> -10
I
0
...z
:>
0
.
..
c: 0.8
z
~
!!
/'
iii
0.4
;0
E
,
20
I-
18
....,.
'".
0
I-
._'--
-20
+60
.+20
...
~
0,
''"" Q4
9
j:9V~'i .$~l~V
-....
1
1
-
~
-
I~t=
,'I-~
''I-~'''~I
1
,;.r 1SL"t-d:- r-
c~WRATE
OSF:D.(po~
Pe.."
I;-
""'Dr'(_
0.5
2
I
'20
60
TEMPERATURE-'\:
-20
5
100
T -Z5"C
FREQUENCY COMPENSATION CIRCUIT
.1
-
o.~
9
,
SL.EWI
cees'O-
~SE
Rtt.~E
~
,0.
10
~
08
\.po' e""
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FREQuENCY CHARACTERlsnCS AS A
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I.~
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I
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FREQUENCY CHARACTERISTlCS AS A
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INPUT OFFSET CURRENT VS AMBIENT TEMPERATURE
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l -I -
ITT709-S
INPUT BIAS CURRENT VS AMBIENT TEMPERATURE
0
0
I-
ITT709-1,
15
20
ITT710
HIGH SPEED DIFFERENTIAL
COMPARATOR
- ITT- - - - SEMICONDUCTORS
HIGH SPEED DIFFERENTIAL COMPARATOR
CONNECTION DIAGRAMS
(TOP VIEW)
• Low Offset Voltage
• Low Offset Current
8 LEAD METAL CAN
• High Voltage Gain
V·
• Fast Response Time
The ITT710 is a differential voltage comparator
which offers high accuracy and fast response
times. The entire circuit is contained on one
silicon chip and is manufactured using the
ITT Planar Epitaxial process. The output of
the ITT10 is compatible with all integrated logic
forms. The ITT710 can also be used as a variable threshold Schmidt trigger, a pulse height
discriminator, a memory sense amplil'ier, a high
noise immunity line receiver, or in high speed
A-D conversion and multivibrator functions.
NON INVERTlNG
INPUT
V-
NOTE: PIN 4 CONNECTEO TO cASE.
14 LEAD DIP
NC
NC
GND
NC
NON INVERTING
INPUT
ABSOLUTE MAXIMUM RATINGS
Characteristics
2
INvERTING
INPUT
Units
NC
Positive Supply Voltage ............ +14.0 V
Negative Supply Voltage ............ -7.0 V
Peak Output Current ................. 10mA
Differential Input Voltage .... . . . . . . .. ±5.0 V
Input Voltage .. . . . . . . . . . . . . . . . . . . .. ±7.0 V
Internal Power Dissipation .......... 300mW
(ITT710-1 Note 1, ITT710-5 Note 2)
Operating Temperature Range
ITT71 0-1 .............. -55° to +125°C
ITT710-5 .................... 0° to 70°C
Storage Temperature Range -65° to + 150°C
Lead Temperature (Soldering, 60 sec.) .. 300°C
V·
OUTPUT
NC'
NC
FLATPAK
GND
NON
NC
c:::=:r----1
INVE ;~~~~ c::.=:r----Il/
INVE~~~~~
NC
v+
'--"<;===
OUTPUT
NOTES:
(1) Rating applies for case temperatures to
+125°C; derate linearly at 5.6mW;oC for ambient temperatures above +105°C.
(4) The input offset voltage and input offset
current (see definitions) are specified for a
logic threshold voltage of 1.SV at -55°C, 1.4V
at +25°C and 1.0V at +125°C.
(2) Ratings apply for ambient temperatures to
+ 70°C.
(5) The input offset voltage and input offset
current (see definitions) are specified for a
logic threshold voltage of 1.5V at O°C, 1.4V at
+25°C and 1.2V at +70°C.
(3) The response time specified (see definitions) is for a 100-mV input step with 5-mV
overdrive.
7-9
ITT710
HIGH SPEED DIFFERENTIAL COMPARATOR
ELECTRICAL CHARACTERISTICS for ITT710-1 (TA=+25°C, V=12.0V, V=-6.0V unless otherwise
specified)
PARAMETER (see definitions)
Min.
Typ.
Input Offset Voltage
Input Offset Current
1250
Output Resistance
Output Sink Current
mV Rs::::;;2000
0.6
2.0
3.0
uA
13
20
uA
1700
200
2.0
0
2.5
Response Time (Note 3)
The following
Units CONDITIONS (Note 4)
0.75
Input Bias Current
Voltage Gain
Max.
mA IlVln;;::5mV, Vout=O
ns
40
specifications apply for -55°C ::::;;TA ::::;; +125°C
Input Offset Voltage
3.0
Average Temperature Coefficient of
Input Offset Voltage
Input Offset Current
Average Temperature Coefficient of
Input Offset Current
3.5
10
2.7
10
0.25
1.8
3.0
7.0
5.0
15
25
75
27
45
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
±5.0
80
Differential Input Voltage Range
±5.0
Voltage Gain
1000
mV Rs::::;;2000
uvrc Rs = 500,
TA=25°C to TA= +125°C
uvrc Rs = 500,
TA=25°C to TA= -55°C
uA TA= +125°C
uA TA = -55°C
nArC TA=25°C to TA= +125°C
nArC TA = 25°C to TA = -55°C
uA TA -
-55°C
V V= -7.0V
100
dB Rs::::;;2000
V
~
Positive Output Level
2.5
Negative Output Level
Output Sink Current
3.2
4.0
-1.0 -0.5
0
0.5
1.7
1.0
2.3
Vin;;::5mV,
V O::::;;lout::::;;5.0mA
V IlV IN ;;::5mV
mA TA = +125°C,
IlVin~5mV, Vout=O
mA TA = -55°C,
IlVln;;::5mV, Vout=O
Positive Supply Current
5.2
9.0
Negative Supply Current
4.6
7.0
mA
Power Consumption
90
150
mW
7-10
mA Vout::::;;O
ITT710
HIGH SPEED DIFFERENTIAL COMPARATOR
ELECTRICAL CHARACTERISTICS FOR ITT710-5 (TA=25°C, V=12.0V, V=-6.0V unless otherwise
specified)
Parameter (see definitions)
Min.
Units Conditions (Note 5)
Typ.
Max.
Input Offset Voltage
1.6
5.0
mV Rs::::;200fl
Input Offset Current
1.8
5.0
uA
Input Bias Current
16
25
uA
Voltage Gain
1000
Output Resistance
1500
200
Output Sink Current
1.6
Response Time (Note 3)
fl
2.5
rnA t.v;n?::-5mV, Vout=O
ns
40
The following specifications apply for 0° C::::;TA::::; + 70°C:
Input Offset Voltage
mV Rs::::;200fl
6.5
Average Temperature Coefficient of
Input Offset Voltage
5.0
Input Offset Current
20
uV;oC
7.5
uA
nAloC TA=25°C teo TA=+70°C
nAloC TA=25°C to TA=O°C
Average Temperature Coefficient of
Input Offset Current
15
24
50
100
Input Bias Current
25
40
uA TA=O°C
±5.0
Input Voltage Range
Common Mode Rejection Ratio
70
Differential Input Voltage Range
±5.0
Voltage Gain
Rs=50fl
TA=O°C to TA= + 70°C
V V
98
=-7.0V
dB Rs::::;200fl
V
800
Positive Output Level
2.5
Negative Output Level
Output Sink Current
3.2
4.0
-1.0 -0.5
0
0.5
V llV;n?::-5mV,O::::;lout::::;5.0mA
V llV;n?::-5mV
rnA llV IN ?::-5mV, Vout=O
Positive Supply Current
5.2
9.0
rnA Vout::::;O
Negative Supply Current
4.6
7.0
rnA
90
150
mW
Power Consumption
R4
RS
28kll
3.9kU
Schematic Diagram
"
500.0.-
NON
INVE~J~0~
o-----+------t:" 0,
0,
6.2V
OUTPUT
Q'r--~----------~
'B
10011
7-11
'7
6811
ITT71 0
HIGH SPEED DIFFERENTIAL COMPARATOR
NE~ATIVE OUTPUT LEVEL" The DC output
voltage in the negative direction with the input
voltage equal to or greater than a minimum
specified amount.
DEFINITION OF TERMS:
LOGIC THRESHOLD VOLTAGE The approximate voltage at the output of the comparator at which the loading logic circuitry
changes its digital state.
OUTPUT SINK CURRENT The maximum
negative current that can be delivered by the
comparator.
INPUT OFFSET VOLTAGE" - The voltage between the input terminals when the output is
at the logic threshold voltage. The input offset
voltage may also be defined for the case where
two equal resistances are inserted in series
with the input leads.
PEAK OUTPUT CURRENT The maximum
current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE" - The resistance seen
looking into the output terminal with the DC
output level at the logic threshold voltage.
INPUT OFFSET CURRENT" - The difference
in the currents into the two input terminals
with the output at the logic threshold voltage.
INPUT BIAS CURRENT" two input currents.
STROBED OUTPUT LEVEL" - The DC output
voltage, independent of input voltage on the
strobe terminal equal to or less than a minimum
.
.
specified amount.
The average of the
INPUT VOLTAGE RANGE" - The range of
'Voltage on the input terminals for which the
comparator will operate within specifications.
STROBE CURRENT - The maximum current
drawn by the strobe terminal when it is at the
zero logic level.
.
DIFFERENTIAL INPUT VOLTAGE RANGE" The range of voltage between the input terminals for which operation within specifications
is assured.
POWER CONSUMPTION - The DC power into
the amplifier· with no output load. The DC power
will vary with signal level, but is specified as a
maximum for the entire range of input-signal
conditions.
,
VOLTAGE GAIN" - The ratio of the change
in output voltage to the change in voltage
between the input terminals producing it with
the DC output level in the vicinity of the logic
threshold voltage.
RESPONSE TIME" - The interval between the
application of an input step function and the
time when the output crosses the logic threshold voltage. The input step drives the comparator from some initial,· saturated input
voltage to an input level just barely in excess
of that required to bring the output from saturation to the logic threshold voltage. This excess
is referred to as the voltage overdrive.
STROBE RELEASE TIME" The time required for the output to rise to the logic
threshold voltage after the strobe terminal has
been driven from the zero to the one logic
level. Appropriate input conditions are assumed.
POSITIVE OUTPUT LEVEL· - The DC output
voltage in the positive direction with the input
voltage equal to or greater than a minimum
specified amount.
"These definitions apply for either side with
the other disabled with the strobe.
7-12
~TT710
HIGH SPEED DIFFERENTIAL COMPARATOR
TYPICAL CHARACTERISTICS ITT 710-1
VOLTAGE TRANSFER CHARACTERISTIC
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ITT71 0
HIGH SPEED DIFFERENTIAL COMPARATOR
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VOLTAGE GAIN AS A FUNCTION
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
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TYPICAL CHARACTERISTICS MIC 710-5
VOLTAGE TRANSFER CHARACTERISTIC
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ItMflRATUIl( ..
~
-~-
10
""
i
20
s
POWER CONSUMPTION AS A
FUNCTION OF AMBIENT TEMPERATURE
l!
10
l.'
~
10
r--...
INPUT OFFSET CURRENT AS A
FUNCTION OF AMBIENT TEMPERATURE
~
•• "
I
.. •
~:: ~:v-
!!
~
......
,
...
1O
10
3
...........
V V
.,
y>/
.; .
II1II
z
llOO
"
~
r-.
l. .
INPUT BIAS CURRENT AS A
FUNCTION OF AMBIENT TEMPERATURE
~
~
.. ..
,..
, ' '".,
y" ....QV
e
I
I
i
unless otherwise
VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGES
v· .. uv
!l
I
Ii,
I
-J.O
I
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
I".
I""
3z"'"
-s.ov
(TA= -i-2S'C. V=12.0V. V=
specified)
I
I
I
I
,.CAnvE OuTPuT uvH
10
10
I .,I
I
1O
lO
tlMKRATURE • ·C
OJ
10
ITT710
HIGH SPEED DIFFERENTIAL COMPARATOR
TYPICAL CHARACTERISTICS ITT 710-1 , ITT710-S
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
••J.'
...
I.'
•
-1.0
I
lGr.1'r'
IOmy
50
•
!
rill ,.4-'Q~Y
11 y
~-i
I
1
i
!
!
1
,
v··
I
i
~12V
i
TA '
I
,
!
I
I
I
I
• " ., '" '"
TIM{ •
n~
100
V· • .
...
~~
l-
....
...
I..
I
~0DF:
2,'1-=.t'
I.'
°i •
S;j
I"
I
I.'
• I--'
iI-
...
J.'
~v
fA' 25"C
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
I -' -
.1
I
,
!
I
•
I
~
IOmv
• ".V
1\
-1.0
..
110
III
11M('
7-16
ns
160
V~·O?IV
~-
I
I
20
I
I
I
.
I
v.'. ,"vi
j
•
I
'-l
I
,
100
"•
I
1I I
~ I.'.vl
i'
I-
2':>"c!
!
v.. ',"v
1.0
~~'"
I
v-' ./!:ovt-
!
,
;g
!
,
!
I
i?
!=:~g
V,
'/II! ~·j,omY
100
COMMON MODE PULSE RESPONSE
(TA=25'C.V =12.0V.V =-s.ov
unless otherwise specified)
I
V"
·b.OY
I III \TC
60
lINt-n,
1"1
120
-
ITT711
DUAL COMPARATOR
ITT- - - - SEMICONDUCTORS
CONNECTION DIAGRAMS
(TOP VIEW)
DUAL COMPARATOR
10 LEAD METAL CAN
• High Accuracy"
• Fast Response Time
• Large Input Voltage Range
• Low Power Consumption
STROBE I
STROBE 2
INVERTING
INPUT 1
INVERTING
INPUT 2
,Now, Pin S connect8d to case.
The ITT711 is a dual differential voltage comparator. It was primarily designed for corememory sense amplifiers which require high
accuracy, fast response times, large input
voltage range, and low power consumption.
The output voltage is compatible with most
integrated logic forms. When used as a sense
amplifier, the threshold voltage can be. adjusted over a wide range, almost independent
of the integrated circuit characteristics. Each
comparator channel is provided with independent strobing, Pulse stretching on the output
is easily accomplished. Double-ended detection for automatic GO/NO-GO test equipment
and pulse height detection (window discriminator) are additional applications of the dual
comparator. The entire circuit is contained on
a silicon chip and is manufactured using ITT
Planar Epitaxial process.
14 LEAD DIP
N.C.
INVERTING
!-"-""'-..Ll..j..J
INPUT 1
NON·INVERTING
INPUT 1
....__---v..----,
NON'INV~NRpT~~~ Lf-"--!l~O--L'4-J
INV~NRpT~~~
STROBE 1
GROUND
OUTPUT
.p--6~/,,"---4"" STROBE 2
1...'
N.C.
10 LEAD FLATPAK
INVERTING
INPUT 1
'--_.r---f "r---"'-C=::J
NON.INVERTING ____ .J;
INPUT 1
v-·r----i
NON.INVERTING ( .. ____
n_
STROBE 1
GROUND
~
4
INPUT2 _~--<~
INVERTING
INPUT 2
OUTPUT
STROBE 2
NOTES:
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Positive Supply Voltage ., ..... ,.,.. + 14.0V
Negative Supply Voltage , .. ,.,."",. -7.0V
Peak Output Current ., .... ,., .. '.... 50mA
Differential Input Voltage ............ ±5.0 V
Input Voltage .................... ±7.0 V
Strobe Voltage ................ 0 to +6.0 V
Internal Power Dissipation .......... 300 mW
(ITT711-1 Note 1, ITT711-5 Note 2)
Operating Temperature Range
ITT711-1 .......... , ..... -55° to +125°C
ITT711-5 .................. 0° to +50°C
Storage Temperature Range -65° to + 150°C
Lead Temperature (Soldering, 60 sec.) .. 300°C
1. Rating applies for case temperatures to
+125°C; derate linearly at 5.6mW/"C for ambient temperatures above +95°C.
2. Rating applies for ambient temperatures to
+70°C.
3. The response time specified (see definitions)
is for a 100-mV input step with 5-mV overdrive.
4. The input offset voltage (see definitions) is
specified for a logic threshold voltage of 1.8V
at -55°C, 1AV at +25°C and 1.0V at
+125°C ...
5. The input offset voltage is specified for a
logic threshold voltage of 1.5V at DoC, 1AV at
+25°C and 1.2V at +70°C.
7-17
ITT711
DUAL COMPARATOR
ELECTRICAL CHARACTERISTICS FOR ITT711·1 (TA=25°C, V+=12.0V, V-=-6.0V unless
otherwise specified)
PARAMETER (see definitions)
Min. Typ.
Input Offset Voltage
Max.
Units
1.0
3.5
mV
1.0
5.0
mV
Input Offset Current
0.5
10.0
uA
Input Bias Current
25
75
uA
Voltage Gain
750
40
ns
Strobe Release Time
12
ns
±5.0
Differential Input Voltage Range
±5.0
V
200
Positive Output Level
4.5
2.5
Negative Output Level
-1.0
Strobed Output Level
-1.0
Output Sink Current
0.5
Vout = +1.4V
V- -- --7.0V
V
Output Resistance
Loaded Positive Output Level
Vout = +1.4V,
Rs :::;;2000,
VCM = 0
Vout = + 1.4V,
Rs :::;;2000,
1500
Response Time (Note 3)
Input Voltage Range
Conditions
5.0
3.5
-0.5
0
0
0.8
Strobe Current
1.2
Positive Supply Current
8.6
Negative Supply Current
3.9
Power Consumption
130
2.5
°
V
Vin;;;::10mV,
V
Vin ;;;::10mV, 10 = 5mA
V
Vin ;;;:1OmV,
V
Vstrobe:::;;0.3V
mA
Vin ;;;:10mV,
Vout;;;:O
mA
Vstrobe -
mA
Vout:::;;O
100mV
mA
200
mW
The following specifications apply for -55"C:::;;T :::;;125°C:
..
Input Offset Voltage (Note 4)
Input Offset Current (Note 4)
Input Bias Current
mV
6.0
mV
20
uA
150
Temperature Coefficient of
5.0
Input Offset Voltage
Voltage Gain
4.5
500
7-18
uA
uV;oC
Rs :::;;2000,
VCM = 0
Rs:::;;2000,
ITT711
DUAL COMPARATOR
Schematic Diagram
STROBE 2
STROBE 1
~--~----------~r---+---~---+--~r-----------~----~--oV+
R15
4.3kO
910 {}
R7
5.05kO
R9
RIO
1200
1200
RS
2400
V'
ELECTRICAL CHARACTERISTICS FOR ITT711-5 (TA =25°C, V+=12.0V, V-= -6.0V unless
otherwise specified)
Typ.
Max.
Input Offset Voltage
1.0
5.0
1.0
7.5
Input Offset Current
0.5
15
25
100
Parameter
Min.
Input Bias Current
Voltage Gain
700
Response Time (Note 3)
Strobe Release Time
Units Conditions
mV Vout = + 1.4V,R,:::;;200n,
VCM=O
mV Vout = + 1.4V,R,:::;;200n,
uA Vout=+1.4V
uA
1500
40
ns
12
ns
Input Voltage Range
±5.0
V ~- --
Differential Input Voltage Range
±5.0
V
Output Resistance
-7.0V
n
200
Positive Output Level
Loaded Positive Output Level
4.5
3.5
5.0
2.5
V Vin~10mV
V Vin~10mV, IQ-5mA
Negative Output Level
-1.0
-0.5
0
V Vin~10mV
Strobed Output Level
-1.0
0
V V,'robe:::;;0.3V
Output Sink Current
0.5
0.8
7-19
mA Vin~10mV, Vou,~O
ITT711
DUAL COMPARATOR
ELECTRICAL CHARACTERISTICS FOR ITT711-5 (TA=25°C, V+=12.0V, V-= -6.0V unless
otherwise specified) (continued)
Parameter
Strobe Current
Min.
Typ.
1.2
Max.
2.5
Units Conditions
mA V.trobe-100mV
Positive Supply Current
8.6
mA Vout:::;;;O
Negative Supply Current
3.9
mA
Power Consumption
130
230
mW
The following specifications apply for O°C:::;;;T :::;;;+70°C:
Input Offset Voltage (Note 5)
6.0
10
mV Rs:::;;;200fl, VCM=O
mV Rs:::;;;200fl
Input Offset Current (Note 5)
25
uA
Input Bias Current
150
Temperature Coefficient of Input
Offset Voltage
Voltage Gain
5.0
500
DEFINITION OF TERMS:
LOGIC THRESHOLD VOLTAGE The approximate voltage at the output of the comparator at which the loading logic circuitry
changes its digital state.
INPUT OFFSET VOLTAGE" - The voltage between the input terminals when the output is
at the logic threshold voltage. 1he input offset
voltage may also be defined for the case where
two equal resistances are inserted in series
with the input leads.
INPUT OFFSET CURRENT" - The difference
in the currents into the two input terminals
with the output at the logic threshold voltage.
INPUT BIAS CURRENT" two input currents.
uA
uV/"C
The average of the
INPUT VOLTAGE RANGE" - The range of
'Voltage on the input terminals for which the
comparator will operate within specifications.
DIFFERENTIAL INPUT VOLTAGE RANGE" The range of. voltage between the input terminals for which operation within specifications
is assured.
VOLTAGE GAIN" - The ratio of the change
in output voltage to the change in voltage
between the input terminals producing it with
the DC output level in the vicinity of the logic
threshold voltage.
RESPONSE TIME" - The interval between the
application of an input step function and the
time when the output crosses the logic threshold voltage. The input step drives the comparatorfrom some initial, saturated input
voltage to an input level just barely in excess
of that required to bring the output from saturation to the logic threshold voltage. This excess
is referred to as the voltage overdrive.
STROBE RELEASE TIME" The time required for the output to rise to the logic
threshold voltage after the strobe terminal has
been driven from. the zero to the one logic
level. Appropriate input conditions. are assumed.
POSITIVE OUTPUT LEVEL" - The DC output
voltage in the positive direction with the input
voltage equal to or greater than a minimum
specified amount.
NEGATIVE OUTPUT LEVEL" - The DC output
voltage in the negative direction with the input
voltage equal to or greater than a minimum
specified amount.
7-20
!TT711
DUAL COMPARATOR
OUTPUT SINK CURRENT The maximum
negative current that can be delivered by the
comparator.
PEAK OUTPUT CURRENT The maximum
current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE' - The resistance seen
looking into the output terminal with the DC
output level at the logic threshold voltage.
STROBED OUTPUT LEVEL' - The DC output
voltage, independent of input voltage on the
strobe terminal equal to or less than a minimum
specified amount.
STROBE CURRENT - The maximum current
drawn by the strobe terminal when it is at the
zero logic level.
POWER CONSUMPTION - The DC power into
the amplifier with no output load. The DC power
will vary with signal level, but is specified as a
maximum for the entire range of input-signal
conditions.
'These definitions apply for either side with
the other disabled with the strobe.
VOL TAGE TRANSFER CHARACTERISTIC
>
TYPICAL PERFORMANCE CURVES ITT711-1
ii,'---.,-i-,.O+------f/JiH,
gu
,Ill
f----------c--cift
1/,,.'---j-- __ l--.--
g
ill
5
§
1.0
I'
I'
'1(5'C
*2S'C
:'/V
1
-1.0
-s.o
-
- ,-- :-'--Sj'C
-),0
-La
-1.0
INPt.T~OlUCE
3.0
s.o
- I'lV
VOLTAGE TRANSFER CHARACTERISTIC
TYPICAL PERFORMANCE CURVES ITT711-5
r--T-+--jff+.-+--,-1-+-I c.b
,.o--,-:-.,;'-c.0-"--:;'-;--'--,':;1.0-'---+',.0:-"---1
I \Pul VCLTAct .
7-21
m~
111711
DUAL COMPARATOR
TYPICAL PERFORMANCE CURVES
VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGES
"'"
TA
.~oc
1400
2;
'.0
'~~~tl~~=t~,t"~'~I"~
'LO~
H-++H+-H-+-+
Y"'6.0V
TA' 25'C
loo,H-++H+-H-++H-H
",H-++H·+-H-++H-H
20
III
TlI.'f -
~I
100
TEMPERATL.«E·C
POWER CONSUMPTION AS A FUNCTION
OF AMBIENT TEMPERATURE
"f-I\-\I--+-+-+-+-f-+ ::: :!~~v
100
~
~I'«i--t--t--t-r-r ~~: :~:v
3OOJ~t-~t-""~t-t-t-H
g
"\
~ ~~~\-+-+-+-~~-+-+~
t--t--I-
1 I
7
·•
I I I I I
! I I I I
liS
g
VC~,
.
1100
'I2Y
V-' -6,DV
~
'12V
V"
-r-r-r-
lO
I-
iii
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
TA '25"
~
v-' -6.0V
I I I I I
of-
~
1.0
v"
II
1.0
TlIII·nl
T,,'25'C
~~
).0
VOlTACE • V
I I I I I
'.0
1.0
·
g
COMMON MODE PULSE RESPONSE
~
STROBE RELEASE TIME FOR VARIOUS
INPUT OVERDRIVES
2.0
f-ltVJI--Hf\"Pkt--!c-r
~
liO~+$m~
-to,I-+-+-+-+-+-+-+-+-+--1
120
TIME - nl
7-22
I~
v.I•• "~
y-. -6.0V
I
~
II'" 1..... 1-
1'-r:::"
3
I"
~
I"·00
." ."
'00
J[Ml'DIATUH •
'100
'c
_
I
ITT712
HIGH-GAIN
DC AMPLIFIER
.L.L _
_WIDEBAND
__
_
mm
SEMICONDUCTORS
HIGH-GAIN
Absolute Maximum Ratings
Characteristics
WIDEBAND
DC AMPLIFIER
• Low Offset Voltage
o High Voltage Gain
• Low Offset Voltage Drift
The ITT712 is a general purpose amplifier for
use as an operational amplifier in high speed
analog computers, a precision instrumentation
amplifier or in other applications requiring a
feedback amplifier capable of operating within
the frequency ranges of DC to as high as
30M Hz. The ITT712 amplifier achieves low
DC offset and low thermal drift, wideband
operation and low power consumption as a
result of ITT Planar epitaxial manufacturing
process.
Units
Voltage between V+ and Vterminals ...................... ±21 Volts
Internal Power Dissipation (TO-S) .... 300mW
(ITT712-1 note 1,
ITT712-S note 2)
Differential Input Voltage ......... ±S.O Volts
Input Voltage .......... + 1.S to -6.0 Volts
Peak Output Voltage ................. SOmA
Storage Temperature Range .. -6S to +1S0°C
Operating Temperature Range
ITT 712-1 ................ -SS to +12SoC
ITT712-S .................... 0 to +70°C
Lead Temperature
(Soldering, 60 sec.) ................ 300°C
NOTES:
1. Rating applies for case temperatures to
+12SoC; derate linearly at S.6rhWrC for ambient temperatures above +9SoC.
2. Rating applies for ambient temperatures to
+70°C.
ELECTRICAL CHARACTERISTICS for ITT712-1
Parameter
(See definitions)
Min. I Typ I Max. Min. I Typ I Max
v+ =12.0V. v- =6.0V· V+ =6.0V. v- =-3.0V
Units
Conditions
Input Offset Voltage
O.S
2.0
0.7
3.0
mV Rs:::;;2kfl
Input Offset Cu rrent
180
SOO
120
SOO
nA
2.0
S.O
1.2
3.S
uA
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
16
40
-4.0
22
67
+O.S -1.S
80
100
2S00
3600
kfl
+O.S
V
dB Rs:::;;2kfl, 1:::;;1 kHz
80
100
600
900
1S00
RL ;?100kfl, Vout-±S.OV
RL ;?100kfl, Vout = ±2.SV
6000
Output Resistance
200
SOO
300
700
Supply Current
S.O
6.7
2.1
3.3
mA Vout=O
Power Consumption
90
120
10
30
mW Vout-O
7-23
fl
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
ELECTRICAL CHARACTERISTICS for ITT712-1 (continued)
Parameter
Min.
(See definitions)
V+=12.0V, V-=6.0V
TyP.
Max.
Min.
Typ,
Max
Units Conditions
V+=6.0V, V-=-3.0V
C1=0.01 uF, R1=20fl
Transient Response
RL~100kfl,
(Unity-Gain)
Rise Time
25
120
ns
Overshoot
10
50
%
CL~100pF
C,=50pF,
Transient Response
(x100 gain)
Vin =10mW
RL~1 OOkfl
Vin=1 mV
Risetime
10
30
ns
Overshoot
20
40
%
The following specifications apply for -55°C~TA~+125°C:
4.0
3.0
Input Offset Voltage
mV
Rs~2kfl
2.5
10
3.5
15
uvrc R.-50fl
TA=25°C to TA= +125°C
2.0
10
3.0
15
uvrc TA=25°C to TA= -55°C
Input Offset Cu rrent
80
400
500
1500
50
280
500
1500
Average
Temperature
Coefficient of Input
Offset Current
1.0
5.0
0.7
4.0
nArC TA=25°C to TA- +125°C
3.0
16
2.0
13
nArC TA=25°C to TA= -55°C
Input Bias Current
4.3
10
2.6
7.5
Average
Temperature
Coefficient of Input
Rs -50fl
Offset Voltage
Input Resistance
6.0
Common Mode
Rejection Ratio
70
8.0
95
nA TA-+125°C
nA TA=-55°C
vA
TA=55°C
kfl
70
dB
95
R.~2kfl, f~1
kHz
V+=12V, V-=-6Vto
Supply Voltage
Rejection Ratio
75
200
75
200
uV/V V+=6V, V-=-3V
Rs~2kfl
RL~1 OOKfl,
RL~100kfl,
Large Signal
Voltage Gain
2000
Output Voltage
Swing
±5.0 ±5.3
±3.5 ±4.0
Supply Current
4.4
5.0
6.7
7.5
1.7
2.1
3.3
3.9
rnA TA=+125°C, Vout=O
rnA TA=-'-55°C, Vout=O
Power Consumption
80
90
120
135
15
19
30
35
mW TA=+125°C, Vout=O
mW TA=-55°C, Vout=O
7000
500
1750
±2.5 ±2.7
±1.5 ±2.0
7-24
V
V
Vout= ±5.0V
Vout =±2.5V
RL~100kfl
RL~10kfl
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
ELECTRICAL CHARACTERISTICS for ITT712·5
Parameter
(see definitions)
The following specifications apply for TA==25°C
Input Offset Voltage
1.5
Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
10
6.0
mV Rs~2KO
0.3
2.0
fl.A
1.5
5.0
fl.A
KG
5.0
1.7
0.5
2.0
2.5
7.5
32
16
rt- 0.5
-4.0
70
92
2000
3400
55
1-1.5
70
+0.5
V
dB Rs~2KO, f~1 KHz
92
RL;;:'100 KO
Vout ==±5.0 V
6000
800
1500
600
300
800
500
RL;;:'100 KG
Vout== ±2.5 V
G
Output Resistance
200
Supply Current
5.0
6.7
2:1
3.3
mA Vout==O
90
120
19
30
mW Vout==O
Power Consumption
---
~
----~--
C,-0.01 fl.F,
R,==200
RL~100 KO
V'n==10 mV
Transient Response
(unity gain)
Risetime
25
120
ns
Overshoot
10
50
%
CL~100
pF
C3 ==50 pF
RL;;:'100 KO
Vin==1 mV
Transient Response
(X100 gain)
Risetime
10
30
ns
Overshoot
20
40
%
The following specifications apply for 0°CTA+70°C
Input Offset Voltage
Average
Temperature
Coefficient of Input
Offset Voltage
6.5
5.0
Input Offset Current
Average Temperature
Coefficient of Input
Offset Cu rrent
7.5
20
25
fl.vrc
2.5
}LA
3.0
5.5
8.0
18
2.5
4.0
6.0
10
20
7-25
mV Rs~2 KG
7.5
Rs==50G
TA==+70°C to TA==O°C
nArC TA-25°C to TA-+70°C
nAloC
TA==25°.C to TA==O°C
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
ELECTRICAL CHARACTERISTICS for ITT712-5 (continued)
Parameter
(see definitions)
Conditions
The following specifications apply for TA=25°C
Input Offset Voltage
1.5
5.0
1.7
6.0
mV Rs~2K!1
Input Offset Current
0.5
2.0
0.3
2.0
/LA
Input Bias Current
2.5
7.5
1.5
5.0
/LA
K!1
Input Resistance
Input Voltage Range
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
10
32
-4.0
16
55
~0.5
+0.5 -1.5
70
92
2000
3400
70
V
dB Rs~2K!1, f~1 KHz
92
RL;;:::100 K!l
Vout =±5.0 V
6000
500
800
1500
RL;;:::100 K!1
Vout=±2.5 V
!l
Output Resistance
200
600
300
800
Supply Current
5.0
6.7
2.1
3.3
rnA Vout=O
Power Consumption
90
120
19
30
mW Vout=O
Cr=0.01 /LF,
R,=20!1
RL~100 K!l
V1n =10 mV
Transient Response
(unity gain)
Risetime
25
120
ns
Overshoot
10
50
%
CL~100
pF
C,=50 pF
RL;;:::100 Kn
V1n =1 mV
Transient Response
(X100 gain)
Risetime
10
30
ns
Overshoot
20
40
%
The following specifications apply for O°C TA+ 70°C
Input Offset Voltage
Average
Temperature
Coefficient of Input
Offset Voltage
5.0
Input Offset Current
Average Temperature
Coefficient of Input
Offset Cu rrent
7.5
6.5
20
7.5
25
/LV/oC Rs=50!1
TA=+70°C to TA=O°C
2.5
3.0
5.5
8.0
18
/LA
nAloC TA=25°C to TA=+70°C
nAloC
TA=25°C to TA=O°C
2.5
4.0
6.0
10
20
mV Rs~2 K!1
7-26
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
ELECTRICAL CHARACTERISTICS for ITT712-5 (continued)
Parameter
(see definitions)
v- =6.0V
Typ. Max.
v- =-3.0V
Typ. Max
V+:, 12.0V,
V+ =6.0V,
Min.
Min.
4.0
Input Bias Current
2.7
12
8
Units
Conditions
p..A TA-O°C
Input Resistance
6.0
18
9.0
27
Kn
Common Mode
Rejection Ratio
65
86
65
86
dB Rs:::;;2Kn,f:::;;1 KHz
90
Supply Voltage
Rejection Ratio
Large Signal
Voltage Gain
1500
90
300
300
V+-12V,V --6y' to
p..V/v V+=6V,V-=-3V
Rs:::;;2 Kn
RL?:100 Kn
Vout =±5.0V
RL?:100Kn
Vout=±2.5V
7000
1750
400
±2.5 ±2.7
±1.5 ±2.0
V RL?:100 Kn
V RL?:10 Kn
Output Voltage
Swing
±5.0 ±5.3
±3.5 ±4.0
Supply Gurrent
5.0
7.0
2.1
3.9
rnA Vout-O
Power Consumption
90
125
19
35
mW
TYPICAL PERFORMANCE CURVES ITT712-1, 712-5
VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGES
....
"I. 2;OC
<000
j3000
I
•.,.,
~ 1.. H-t-+-t-+--t-H--t-+-t-l
..
-<
.,...
..
OUTPUT VOLTAGE SWING AS A FUNCTION OF
FREO,UENCY WITH LEAD·UG COMPENSATION
,.
~
~
~
-3
-
.
..
•
.
100'
-tV
e
..
I
I ..
~
I
!20
\
!I
•
'\
,.
..
,
FRt:GWICY - H,
100.
-,
-20
'00'
OP(JHOOP~r
~ 100
l!;
~
50
"
..-,
•
I III I
r
T,,'.WC
e,
C1"looopf'. RpZOOA
ILLl
,.
fREClt.l(MCY -Hz
7-27
..
-.
1111 I
11111
OP£N:LDOP
NI
-I
y.,
+12V
v-. -6Y
Ta' +8"C
C, oO.l,.f
R,oO
II 1111
x:~ I~L.,"~;
• ! III I II!
Xl CLOSED-LOOP
..
JllIJ 11lL
'00 " ,
·20
50.
~12
11..'g""•• 1.OOI'
!20
!I
,
..
~
,
l LIl J
C .0.01"'. R • 20.11.
.
V···,ZV
IIII I I r-...:
.,.-.
.,
SUPPLY VOLTAGES-Y
FREQUENCY RESPONSE WITH
CONSERVATIVE COMPENSATION NETWORK
Y-'·6V
C1"IOO"', R,.ZUl
J..-
:;;
-6
FREO,UENCY RESPONSE FOR VARIOUS
CLOSEIJ.LOOP GAINS (UG COMPENSATION)
fA' +ZS-C
......
~
&\:150
SUPPLY VOLTAGES-V
Y· .... ,2Y
y~.
-4
,,'.~oc
a
o.~,...,...1....J'-'-~
••,-i--'-'-.:::1O-'--'-'-.-:i12
'12
5UPf!t.Y VOLTAG(S-V
:
1 10
~
a
~zoo
a uH-t-t-I*-r-H--t-+-t-l
'000
12
".
2··H++-+++-H++-+--1
a
,/
=;
, .• H-t-+-t-+--t-H-""'1',,-'-F"'-j"-l
~
m2.ol-++-+-++-l-H+-+-+:...I
i-""'
~2000
INPUT OFFSET CURRENT AS A
FUNCTION OF SUPPLY VOLTAGES
INPUT BIAS CURRENT AS A
FUNCTION OF SUPPLY VOLTAGES
'00'
FR£QU[N(;Y - HI
..
,. ,
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
TYPICAL PERFORMANCE CURVES ITT712-1, 712-5 (continued)
FREQUENCY RESPONSE FOR VARIOUS CLOSED·
LOOP GAINS (LEAD·LAG COMPENSATION)
'I.' +12'1
10 ~.LOOP, Cz'O
f-V-"OV
r-.
I II
00
11
TA' +25'C
C3' SOpf
RI 'lo~n
........
I
.40
'"
C2rlOOOpF, RZ'ZOO.a
~20 III
III
·20
100'
IOU
~
,..
.
.~~
II
11
0
100
~
,.
110
.,.
~
""~
~ .. I-+HI--h~"-:.~.+-+-H.H-+I-tH
i
~~
i 10~.....j.....j....>-l---l--I-.j...j..J-~
•
Mft"\
N.u
N4J
10'
100'
'REQUENCY - HI
~'~~tt=l
f-++I+-.J--H~:::~~Y
TA'25'C
,.
1~1-~-WL-~'0~~20~~"~1~00'
CLOSEO-LOOl" VOLTAGE GAIN
'1""2'1
/
5 _~-.-6V
_TA'2~~
"$:
2
~
1
~
90%
/
0.6
',Or;:..
0.2
1/
RISET,,,[
0
,
,
1
I
it~ 0.4
/
0.1
oV~R$k ~
ii! 0.8
/
.'/
~~'~~'0~.LUL~~,~~-U~'Od~
1.2
1.0
•~O.5
,ol-+t++-H+H--jl,-!+H---!\,+-++H
TRANSIENT RESPOIISE
1.4
10
~ 100 H-o!:I!-+*lH-4d4+--H-Hl-l
~ "I-++++--?:+++H~\.
~20
~~
\...
SLEW RATE AS A FUNCTION OF CLOSED·LOOP
VOLTAGE GAIN ILAG COMPENSATION)
TIZS'C
~ 1-++lfl'Ok
Y· •• 12V_
y-. -IV
l800
~ '~~-4-4-+t~/-+-+-I--I
~ of--4-4-+-l-+-+-+-I--I
!"f-~-4-+fl+n-+-+-I--I--I
RL"OOkA
.,-, -,
1.0
f-HHH-+~
II-+':'!"';':''::.".;,.'-1
V
~ 0 f-H-4-+II+-+-+-+-I--I
1/
§.,
-2.0 ~f-';;IRLo;..':';'0'::0'~.L...f.I!i1-+'--+-
I
-,
-3.0
-10
1100
kf-i-4-4-+-+-+- ~::::~_
1000 f-p....l"-..~-4-+-+-+-+-+-I
~~-4-+~~-I-~4-+-+-I
I"
10
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
,
'000
2200
·00
i
.,.
T
00
'0
TEMPERATUR[-"C
100
140
INPUT OFFSET CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
I
v·,
, 1'\
f-
.12V
V-'-6V
1'<-
,
~1-~I--V."12V -1--1-1-1--1
,oof-~I--~~~··~·~V-I-+-.J-+-I
I"
r- r-;
TEMPERATURE·'C
3000
r
,1\
1 f-
~OO~~'20~~'O~~'O~~l~OO~,~-I
=
i
INPUT VOLTAGE -rtiV
IHPUTVOlTAG[-,.V
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
~:: ::~
-2
-6
"
~ 3400
&oj
LH-+-+-+-cH-+++-I
R • 10ke
1t'10kA
-4
!
0
·60
t---
v· •• 6V
v-· -3V'
"0
r-t'0
00
TEMPERATURE-'C
7-28
100
140
O'L-L-L-~~~~~~-I
-60
-20
20
60
TEMPERATURE-'C
100
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
TYPICAL PERFORMANCE CURVES ITT712-1 (continued)
SUPPLY VOLTAGE REJECTlOtJ RATIO
AS A FUNCTION OF AMBIENT TEMPERATURE
~
lOa
COMMON MODE REJECTION RATIO AS A
FUNCTION OF AMBIENT TEMPERATURE
IU~
RlslkQ
r-r-r-r-r-r-r-r-~f-1
f/
I
~
,w
,
I
I I
\
400
0
~
,
~
-f";;
300
200
"
v."..
+6'1
..,.-.
-~v
r-
~ 100 t-
." "
'60
\40
100
W
'
I
I I
~~
Mld7112j'
it
.
~
2
B
100
160
v
-6V
i/
--.j, ~ /1
-
;54-;,.a'.
-
~
~
A
v·, .IZV
V-I -6V
TA I .Z~·C
0
100
'00
"
"e
TEMPERATURE -
I
.0
20
TEMPERATURE -'C
-
~
i
I
I
r N-+
g4
V-, -611
·'e
lZ
~
is
+,1
0
"
~ 10
1'1+'·,2'1
:
I
I
OUTPUT VOLTAGE SWING
AS A FUNCTiON OF LOAD RESISTANCE
t
I
"-
I
' I
·20
'W
OUTPUT RESISTANCE AS A
FUNCTION OF AMBIENT TEMPERATURE
!
:
I
I
TEt.APERATURE-'C
200
TEMPERATURE
S'"
I
~~6'::-O~-:'2'::-O~-;2';;-O~-;,,';;--L;;,oo'::--':,\4::JO
TENPERATURE ·'c
~'OO
2
I T
i I I
I
r---+-----+-.r-r-
V· • • 610'
r-
i,
i
I
,
I
I
3
~
r r-r-r-r-r-r-r-r-r-H
INPUT RESISTANCI? AS A
FUNCTION OF AMBIENT TEMPERATURE
I
I
~ 4
a
~
I
1--+-'
V.... ,ZV,·
V~, - 6V
-
%
~
II L J
I I
i
~ 5
f/
;: 10
•
'''52.kll.
2 9Of-+-+-+-+-+-+-+-+-H
S
11 80 r-t-t-t-t-h;;-f-=-t----t--1
~
POWER SUPPLY CURRENT AS A
FUNCTION OF AMBIENT TEMPERATURE
lOOk
LOAD RESISTANCE - 11
TYPICAL PERFORMANCE CURVES ITT712-5 (continued)
VOLTAGE TRANSFER
CHARACTERISTIC
u
v••
11 V
TA •
VOLTAGE TRANSFER
CHARACTERISTIC
VOLTAGE GAIN AS A FUNCTiON
OF AMBIENT TEMPERATURE
,..,.
ltv
O"'t
<. f-"t-'-"i'-·"++-I'N'~III-:"'-.!-I
~::~,~V-
~ lA'we
~ "'f-+-I-HHi4i-i> b·, ~
g
II
~
~
'I-H-4-+-++-i'-4-~
g
g ""r-r-r-Hhfi,+++++--!
§
~
.... 1-'1-'•...;10.,;;0+1>1-+++++-1
_Rl'tCD:O
....-ut=t:;~t'!J~::j;=1~:j~
-1.0
-),G
1.0
),(1
S.Q
1.0
r-r-r-HH!-I1_TA . 25'C rIL
~
2
'1.'
r-r-r-Hf.li'+++++-I
"'
I
R 'IOOIII'l
.l.' --r;- ,
-10
-l.O
2.0
'HPUr VOlTAGI:: - mV
-6.0
l.
..........
.......
1.5
'"
"' • 10
l .• " ,
I'-..
..........
100
ro
~
()
nMf'f.RATUR{"C
~
6.0
10
~
"
r-....
..,
...
.
-
"-
'o"06.0V
V·'·l.OV
..........
./1
1-
10
ro
~
()
TtMPlRATURE· ·C
7-29
...
0
10
ro
~
"
~
10
~
()
TtMPlRATUR£'
I
I
'1+. ~v
- rv-'''Uv
- t-....L
l.'
r-...
r-....
"'"
~
-2.0
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
::: ~):O~-
..,
,."
'r-r-r-H~r-!-4-4-1-1
INPUT VOlTA(j( - mV
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
""'=----
~
10
'c
INPUT OFFSET CURRENT AS A
FUNCTION OF AMBIENT TEM~ERATURE
.""
..
.
.'
v", !12V
I"-
..........
"'t-
.•
L~'oV
i""--
10
'1··4.0 ....
V·· ·).0'1
ro
r--
t- t-
r- r-
-r-- I--.
)o«l5(l~
T(MPlRAlUR£ -
'c
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
TYPICAL PERFORMANCE CURVES ITT712-5 (continued)
SUPPLY VOLTAGE REJECTION RATIO AS A
FUNCTION OF AMBIENT TEMPERATURE
POWER SUPPLY CURRENT AS A
FUNCTION OF AMBIENT TEMPERATURE
COMMON MODE REJECTION RATIO AS A.
FUNCTION OF AMBIENT TEMPERATURE
•.•
1
w~~~
!
I .~~-+--+--t---l
m~+--+--~+--+~~
1.0 O!--:!IO~:!:-"--;~!:--:!~~:!:-~-!~~"
·'~~IO~m~~~~~~~*~~~~ro
l(MPERAltJRt: ··c
n'~~IO--m~~M~~~~~±-~~~ro
ItMf'UATUIIE '"C
INPUT RESISTANCE AS A
FUNCTION OF AMBIENT TEMPERATURE
ltMFtRATUU
tI
ltD
.;;
i!
"
.
10
-
,
10
I-
V'·IfV
V"j-6.0V
m
lO
INPUT VOLTAGE RANGE
AS AFUNCTION OF SUPPLY VOLTAGES
.
~
~
o
1-.
.. -,
~
i'~
"
....
.'" ..
'10
'12
S&PPLl'VOLTMU-V
,
M
~
ItMPERATUR(
otc
~
.pi!' V
.."",
~
~
'" ~
.. ..-,
•-,
~
"
SUPPLY CURRENT
AS AFUNCTION OF SUPPLY VOLTAGES
H++H-++HT..... C
I
i
~
"
-!5st'C SlT.:I+12S·C
':'10
Ii
Vt'IlY
Y"lOV
I
10
OUTPUT VOLTAGE SWING
AS AFUNCTION OF SUPPLY VOLTAGES
~
~
~l""
l-
,,
Ii;; •
.
-,
-,
~
lOll-- I--
II
!
~-.
~
i!'"'
Ii
ro·
~
"C
>
-sa-c.T, •• IZSlf:
i"" r-
t-- -
U~IT'
I
a
---
TlMPERA1\IM:
> 0
I
\It.!.ov - fY"'"OV
I
«II
a - v·.Lv
~.'[
··c
OUTPUT RESISTANCE AS A
FUNCTION OF AMBIENT TEMPERATURE
""
~D
~
,.'~:t;~~~
ie Ur-- :::I2~V+--+-t-t
__+-~~--+--r~
~
r-. r-..
I "1--+-+-+--+-+-1--'='1
.~
I
I
V
~
.,,-,
SUI'P.',Y VOLTAGES-V
~~,~~~.7.J-LJ~.±IO-L~~~
•
."-,
-3
-4
-5
SUPPlY VOLTAGES-V
-Ii
2kC
5kC
Vout
.
LAG
I
COMPENSATION .".
CI
R,
LEAD-LAG
COMPENSATION
XIOO AMPLIFIER (LEAD COMPENSATION)
Frequency Compensation
Circuits .
UNITY-GAIN AMPLIFIER
Transient Response
Test Circuits
7-30
(LAG COMPENSATION)
ITT712
HIGH-GAIN WIDEBAND DC AMPLIFIER
V'
"
.. 0
"..n
INVERTING
INPUT
2
6
~~~PENSATION
"
..0
GROUHD_+--J..-j---i
::t----.-I-t::Q,
vNOTE: PIN 4 CONNECTED TO CASE
utO
'"
RIO
2400
FLAT PACK (Top View)
L-_--J.._ _
'2400
1_1 _ _ _ _
~
,-
NO CONNECTION
NO
GROUND
INVERTING
'>----pocr-UT
INPUT
NON.INI/ERTING
Schematic Diagram
COW~ECTION
INPUT VOLTAGE RANGE-A range of voltage
which, if exceeded on either input terminal,
could cause the amplifier to cease functioning
properly.
7 l..AG
COMPENSATlO' j
4
INPUT
6
v-
LEAD
CO',04i-f:NSATION
DUAL IN-LINE
NO CONNECTION
NO CONNECTION
NO CONNECTION
V+ SUPPLY
NO CONNECTION
>---I:::J OUTPUT
NON-INVERTING
INPUT
v-
LAG
COMPENSATION
5
9
SUPPLY
NO CONNEcnON
LEAD
COMPENSATION
NO CONNECTION
Connection Diagrams
DEFINITION OF TERMS:
INPUT OFFSET VOLTAGE-That voltage which
must be applied between the input terminals
to obtain zero output voltage. The input offset
voltage may also be defined for the case where
two equal resistances are inserted in series
with the input leads.
INPUT OFFSET CURRENT-The difference in
the currents into the two input teriminals with
the output at zero volts.
INPUT RESISTANCE-The resistance looking
into either input terminal with the other
grounded.
INPUT BIAS CURRENT-The average of the
two input currents.
INPUT COMMON MODE REJECTION RATIOThe ratio of the input voltage range to the maximum change in input offset voltage over this
range.
LARGE-SIGNAL VOLTAGE GAIN-The ratio of
the maximum output voltage swing with load
to the change in input voltage required to drive
the output from zero to this voltage.
OUTPUT VOLTAGE SWING-The peak output
- swing, referred to zero, that can be obtained
without clipping.
OUTPUT RESISTANCE-The resistance seen
looking into the output terminal with the output
at nUll. This parameter is defined only under
small signal conditions at frequencies above a
few hundred cycles to eliminate the influence
of drift and thermal feedback.
POWER CONSUMPTION-The DC power required to operate the amplifier with the output
at zero and with no load current.
SUPPLY VOLTAGE REJECTION RATIO-The
ratio of the change in input offset voltage to
the change in supply voltage producing it.
TRANSIENT RESPONSE-Te closed-loop step
function response of the amplifier under smallsignal conditions.
PEAK OUTPUT CURRENT The maximum
current that may flow in the output load without
causing damage to the unit.
7-31
ITT720
DUAL HIGH SPEED
DIFFERENTIAL COMPARATOR
ITT
----SEMICONDUCTORS
DUAL HIGH SPEED
DIFFERENTIAL
COMPARATOR
CONNECTION DIAGRAfJI
• Better Temperature Tracking
• Low Offset Voltage
• Low Offset Current
• High Voltage Gain
• Fast Response Time
The ITT720 differential voltage dual comparator,
offering high accuracy and fast response consists of two separate ITT710 high speed differential comparators. The entire circuit is
contained on one silicon chip and is manufactured using the ITT Planar Epitaxial process.
The output of the ITT720 is compatible with
all integrated logic forms. The ITT720 can also
be used as a variable threshold Schmidt trigger,
a pulse height discriminator, a memory sense
amplifier, a high noise immunity line receiver,
or in high speed A-D conversion and multivibrator functions.
D2
5.2Y
OUTPUT
ABSOLUTE MAXIMUM RATINGS
Characteristics
Units
Positive Supply Voltage .............. + 14.0V
Negative Supply Voltage ........... -7.0V
Peak Output Current ............... 10 mA
Differential Input Voltage ............ ±5.0V
Input Voltage ...................... ±7.0V
Internal Power Dissipation ........... 300 mV
(ITT720-1 Note 1, ITT720-5 Note 2) .. 200 mW
Operating Temperature Range
ITT720-1 ......... -55°. to + 125°C
ITT720-5 ............... 0° to + 70°C
Storage Temperature Range .. -65° to +150°C
Lead Temperature (Soldering, 60 sec.) .. 300°C
NOTES:
(1) Rating applies for case temperatures to
+125°C; derate linearly at 5.6mWrC for ambient temperatures above +105°C.
CROUND
R5
1.71r.0
1f.z CIRCUITSCHEMATIC DIAGRAM
' - - - - - 4 - -..... y.
(2) Ratings apply for ambient temperatures to
+70°C.
(3) The response time specified (see definitions) is for a 100-mV input step with 5-mV
overdrive.
(4) The input offset voltage and input offset
current (see definitions) are specified for a
logic threshold voltage of 1.8V at -55°C, 1.4V
at +25°C and 1.0V at +125°C.
(5) The input offset voltage and input offset
current (see definitions) are specified for a
logic threshold voltage of 1.5V at O°C, 1.4V at
+25°C and 1.2V at +70°C.
7-32
ITT720
DUAL HIGH SPEED
DIFFERENTIAL COM PARA TOR
ELECTRICAL CHARACTERISTICS FOR ITT720·1
otherwise specified)
PARAMETER (see definitions)
Min.
Max.
0.6
2.0
mV Rs:(200n
0.75
3.0
uA
13
20
uA
Input Bias Current
Voltage Gain
1250
1700
0
200
Output Resistance
2.0
Output Sink Current
rnA AVl n ;;::5mV, Vout=O
2.5
ns
40
Response Time (Note 3)
The following
Units CONDITIONS (Note 4)
Typ.
Input Offset Voltage
Input Offset Current
(T=+25°C, V=12.0V, V=-6.0V unless
specifications apply for -55°C :(TA :( +125°C
Input Offset Voltage
3.0
Average Temperature Coefficient of
Input Offset Voltage
Input Offset Current
Average Temperature Coefficient of
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
3.5
10
2.7
10
0.25
1.8
3.0
7.0
5.0
15
25
75
27
45
80
±5.0
Voltage Gain
1000
Negative Output Level
Output Sink Current
nAloC TA=25°C to TA= +125°C
nArC TA = 25°C to TA = -55°C
uA TA = -55°C
dB Rs:(2000
100
V
Positive Output Level
2.5
uA TA= +125°C
uA TA = -55°C
V V= -7.0V
±5.0
Differential Input Voltage Range
mV Rs:(2000
uvrc Rs = 50n,
TA=25°C to TA= +125°C
uvrc Rs = 500,
TA=25°C to TA= -55°C
3.2
4.0
-1.0 -0.5
0
0.5
1.7
1.0
2.3
Vin ;;::5mV,
V O:(lout:(5.0mA
V
~VlN;;::5mV
rnA TA = +125°C,
AVin ;;::5mV, Vout=O
rnA TA = -55°C,
AVin ;;::5mV, Vout=O
Positive Supply Current
5.2
9.0
rnA Vout:(O
Negative Supply Current
4.6
7.0
rnA
90
150
"mW
Power Consumption
7-33
ITT720
DUA~ HIGH SPEED
DIFFERENTIAL COMPARATOR
ELECTRICAL CHARACTERISTICS .FOR .ITT720-5
otherwise specified)
Parameter (see definitions)
(TA=25°C. V=12.0V. V=-6.0V unless
Max.
Min. Typ.
Units
Input Offset Voltage
1.6
5.0
mV
Input Offset Current
1.8
5.0
uA
16
25
uA
Input Bias Current
Voltage -Gain
1000
Output Resistance
Output Sink Current
1.6
200
n
2.5
mA
40
ns
Input Offset Voltage
5.0
Input Offset Current
Average Temperature Coefficient of
Input Offset Current
Input Bias Current
70
Differential Input Voltage Range
±5.0
mV
20
uV/"C
7.5
15
24
50
100
uA
nA/oC
nA/"C
25
40
uA
V
98
Vout=O
dB
Rs~200n
Rs=50n.
TA=O°C to TA=+70°C
TA=25°C to TA=+70°C
TA=25°C to TA=O°C
TA=O°C
V
=-7.0V
Rs~200n
V
800
Positive Output Level
2.5
3.2
Negative Output Level
-1.0
-0.5
Output Sink Current
6.5
±5.0
Common Mode Rejection Ratio
Voltage Gain
~Vln~5mV.
0°C~TA~+70°C:
Average Temperature Coefficient of
Input Voltage Range
Rs~200n
1500
Response Time (Note 3)
The following specifications apply for
Conditions (Note 5)
4.0
0
0.5
V
~ Vin~5mV. O~lout~5.mA
V
~Vln~5mV
mA
~Vin~5mV.
mA
Vout~O
Positive Supply Current
5.2
Negative Supply Current
4.6
7.0
mA
Power Consumption
90
150
mW
9.0
Vout=O
DEFINITION OF TERMS:
LOGIC THRESHOLD VOLTAGE The approximate voltage at the output of the comparator at which the loading logic circuitry
changes its digital state.
INPUT OFFSET VOLTAGE" - The voltage between the input terminals when the output is
. at the logic threshold voltage. The input offset
voltage may also be defined for the case where
two equal resistances are inserted in series
with the input leads.
INPUT OFFSET CURRENT" - The difference
in the currents into the two input terminals
with the output at the logic threshold voltage.
INPUT BIAS CURRENT" two input currents.
The average of the
INPUT VOLTAGE RANGE" - The range of
'Voltage on the input terminals for which the
comparator will operate within specifications.
7-34
ITT720
DUAL HIGH SPEED
DIFFERENTIAL COMPARATOR
voltage equal to or greater than a minimum
specified amount.
DIFFERENTIAL INPUT VOLTAGE RANGE' The range of voltage between the input terminals for which operation within specifications
is assured.
NEGATIVE OUTPUT LEVEL' - The DC output
voltage in the negative direction with the input
voltage equal to or greater than a minimum
specified amount.
VOLTAGE GAIN' - The ratio of the change
in output voltage to the change in voltage
between the input terminals producing it with
the DC output level in the vicinity of the logic
threshold voltage.
OUTPUT SINK CURRENT The maximum
negative current that can be delivered by the
comparator.
RESPONSE TIME' - The interval between the
application of an input step function and the
time when the output crosses the logic threshold voltage. The input step drives the comparator from some initial, saturated input
voltage to an input level just barely in excess
of that required to bring the output from saturation to the logic threshold voltage. This excess
is referred to as the voltage overdrive.
PEAK OUTPUT CURRENT The maximum
current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE' - The resistance seen
looking into the output terminal with the DC
output level at the logic threshold voltage.
STROBED OUTPUT LEVEL * - The DC output
voltage, independent of input voltage on the
strobe terminal equal to or less than a minimum
specified amount.
STROBE RELEASE TIME' The time required for the output to rise to the logic
threshold v,ojtage after the strobe terminal has
been driven from the zero to the one logic
level. Appropriate input conditions are assumed.
STROBE CURRENT - The maximum current
drawn by the strobe terminal when it is at the
zero logic level.
POSITIVE OUTPUT LEVEL' - The DC output
voltage in the positive direction with the input
POWER CONSUMPTION - The DC power into
the amplifier with no output load. The DC power
will vary with signal level, but is specified as a
maximum for the entire range of input-signal
conditions.
'These definitions apply for either side with
the other disabled with the strobe.
TYPICAL CHARACTERISTICS ITT720-1
wise specified)
VOLTAGE TRANSFER CHARACTERISTIC
r--
(T = +25°, V=12.DV. V= -6.DV unless other-
VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE
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ITT720
DUAL HIGH SPEED
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TYPICAL CHARACTERISTICS ITT720·1 (T
wise specified) (continued)
INPUT BIAS CURRENT AS A
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OUTPUT VOLTAGE LEVELS AS A
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ITT720
DUAL HIGH SPEED
DIFFERENTIAL COMPARATOR
TYPICAL CHARACTERISTICS ITT720-S (TA=25°C, V =12.0V
-6.0V unless other-
wise specified)
VOLTAGE TRANSFER CHARACTERISTIC
~
fA' ~'c
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fA'
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INPUT BIAS CURRENT AS A
FUNCTION OF AMBIENT TEMPERATURE
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ITT
----ITT723
PRECISION VOLTAGE REGULATOR
SEMICONDUCTORS
PRECISION VOLTAGE REGULATOR
Connection Diagrams
Top Views
PRECISION VOLTAGE REGULATOR ITT723
• Positive or Negative Supply Operation
• Series, Shunt, Switching or Floating
Operation
CURRENT
LIMIT
• .01 0;. Line and Load Regulation
• Output Voltage Adjustable From 2 to 37 Volts
INVERTING
INPUT
• Output Current to 150 mA Without External
Pass Transistor
3
NON·INVERTING
INPUT
The ITT723 is a monolithic voltage· regulator
constructed on a single silicon chip using the
epitaxial process. The device consists of a
temperature compensated reference amplifier,
error amplifier, power series pass tansistor and
current limit circuitry. Additional NPN or PNP
pass elements may be used when output currents exceeding 150 mA are required. Provisions are made for adjustable current limiting·
and remote shutdown. In addition to the above,
the device features low standby current drain,
low temperature qrift and high ripple rejection.
The ITT723 is intended for use with positive
or negative supplies as a series, shunt, switcfJing or. floating regulator. Applications include
laboratory power supplies, isolation regulators
for low level data amplifiers, logic card regulators, small instrument power supplies, airborne systems and other power supplies for
digital· and linear circuits.
v
Note: On metal can, pin 5
is connected to case.
14 LEAD DIP
(TOP VIEW)
NC
FREQUENCY
COMPENSATION
NC
CURRENT LIMIT
v'
Vc
CURRENT SENSE
INVERTING INPUT
VOUT
NON·INVERTING INPUT
Vz
VREF
NC
V
ABSOLUTE MAXIMUM RATINGS
Characteristics
ITT723-1
Pulse Voltage from V+ to V- (50 msec) .....
Voltage from V+ to V-
50
Continuous Voltage from V+ to V-
40
0
••••••••••••••••
0
ITT723-5
V
40
0
••••••••
V
V
150
Maximum Output Current ...................
Units
mA
Input-Output Voltage Differential .............
40
40
V
Current from Vz ........•.....•....••• ; .•••
25
.25
mA
Current from VREF • • • • • • • • • • • • • • • • • • • • • • • • • •
15
15
mA
Internal Power Dissipation-Metal Can (Note 1)
800
800
mW
Internal Power DissiQation-DIP (Note 1) .....
900
'-900
mW
7-38
ITT 723
PRECISION VOLTAGE REGULATOR
Characteristics (continued)
ITT723-5
ITT723-1
o to
Operating Temperature Range ............... -55 to +125
Units
+70
°C
Storage Temperature Range ................
-65 to +150
-65 to +150
°C
Lead Temperatu re (Soldering, 60 sec.) .......
300
300
°C
Note: On metal can, pin 5 is connected to case.
ELECTRICAL CHARACTERISTICS FOR ITT723-1 (Note 2)
Parameter (see definitions)
Min. Typ.
Max.
Units
Conditions
Line Regulation
.01
.02
0.1
0.2
0.3
%VOUT
%VOUT
%VOUT
VIN=12V to VIN =15V
VIN =12V to VIN =40V
-55°C:=::;TA:=::;+125°C,
VIN =12V to VIN =15V
Load Regulation
.03
0.15
0.6
%VOUT
%VOUT
IL=1 mA to k=50 mA
-55°C:=::;TA:=::; + 125°C,
IL=1mA to k=50 mA
Ripple Rejection
74
86
.002
Average Temperature Coefficient of
Output Voltage
Short Circuit Current Limit
Reference Voltage
Output Noise Voltage
dB
dB
.015
65
6.95
7.15
20
mA
7.35
2.5
Long Term Stability
2.3
V
p.Vrms
p.Vrms
0.1
Standby Current Drain
%;oC
-55°C:=::;TA:=::;+ 125°C,
Rs c =10n, VOUT=O
BW-100Hz to 10 kHz,
CREF=O
BW=100Hz to 10 kHz,
CREF=5.uF
%/1000hrs
3.5
mA
Input Voltage Range
9.5
40
V
Output Voltage Range
2.0
37
V
Input-Output Voltage Differential
3.0
38
V
Definition of Terms
f=50 Hz t010 kHz, CREF= o
f=50 Hz to 10 kHz, CREF = o
CREF=5.uF
IL=O, VIN =30V
LINE REGULATION - The percentage change
in output voltage for a specified change in
input voltage.
AVERAGE TEMPERATURE COEFFICIENT OF
OUTPUT VOLTAGE - The percentage change
in output voltage for a specified change in
ambient temperature.
LOAD REGULATION - The percentage change
in output voltage for a specified change in load
current.
SHORT CIRCUIT CURRENT LIMIT - The output current of the regulator with the output
shorted to the negative supply.
RIPPLE REJECTION - The ratio of the peak to
peak input ripple voltage to the peak to peak
output ripple voltage.
REFERENCE VOLTAGE - The output of the
reference amplifier measured with respect to
the negative supply.
7-39
ITT723
PRECISION VOLTAGE REGULATOR
Equivalent Circuit
EQUIVALENT CIRCUIT
OUTPUT NOISE VOLTAGE - The rms output
noise voltage with constant load and no input
ripple.
fREOUENCY
COMPENSATION
Vc
STANDBY CURRENT DRAIN The supply
current drawn by the regulator with no output
load and no reference voltage load.
INPUT VOLTAGE RANGE The range of
supply voltage over which the regulator will
operate.
Vz
V-
OUTPUT VOLTAGE RANGE - The range of
output voltage over which the regulator will
operate.
CURRENT
LIMITER
2. Unless otherwise specified, TA=25°C, VIN =
V+=Vc=12V, V-=O, Vout =5V, h
=1mA, Rsc=O,
INPUT-OUTPUT VOLTAGE DIFFERENTIAL The range of voltage difference between the
supply voltage and the regulated output voltage
over which the regulator will operatae.
Cl=100pF, CREF=O and divider impedance as
seen by error Amplifier~1OKO connected as
shown in Fig. 1.
SENSE VOLTAGE The voltage between
current sense and current limit terminals necessary to cause current limiting.
3. LJ is 40 turns of #20 enameled copper wire
wound on Ferroxcube P36/22-3B7 pot core or
equivalent with 0.009" air gap.
TRANSIENT RESPONSE The closed-loop
step function response of the regulator under
small-signal conditions.
4. Figures in parentheses may be used if R/R,
divider is placed on opposite of error amp.
5. Replace R1 R, in figures with divider shown
in figure 13.
NOTES:
1. Derate metal can package at 6.8 mWrC
and dual-in-Iine package at 9 mWrC for operation at ambient temperatures above 25°C.
6. V+ must be connected to a +3V or greater
supply.
ELECTRICAL CHARACTERISTICS FOR ITT723-5 (Note 2)
PARAMETER (see definitions) .
Line Regulation
Min.
Typ.
Max.
Units
.01
0.1
0.1
0.5
0.3
%VOUT
%VOUT
%VOUT
0.2
0.6
%VOUT
%VOUT
Conditions
VIN =12V to VIN =15V
VIN =12V to VIN =40V
0°C~TA~70°C,
VIN =12V to VIN =15V
Load Regulation
.03
IL =1 mA to IL =50 mA
0°C~TA~70°C,
k=1 mA to IL =50 mA
Ripple Rejection
Average Temperature Coefficient of
Output Voltage
Short Circuit Current Limit
74
86
.003
65
7-40
dB
dB
.015
%/oC
mA
f=50 Hz to 10 kHz, CREF =
f=50 Hz to 10 kHz,
CREF=5}LF
0°C~TA~70°C
Rsc =100, VOUT=O
o
ITT723
PRECISION VOLTAGE REGULATOR
ELECTRICAL CHARACTERISTICS FOR ITT723-S (Note 2)
PARAMETER (see definitions)
Min.
Typ.
Max.
Units
Reference Voltage
Output Noise Voltage
6.80
7.15
20
7.50
V
p.Vrms
2.5
Long Term Stability
p.Vrms
Standby Current Drain
2.3
BW-100Hz to 10 kHz,
CREF=O
BW=100 Hz to 10 kHz,
CREF=5/LF
%/1000hrs
0.1
4.0
mA
9.5
40
V
Output Voltage Range
2.0
37
V
Input-Output Differential
3.0
38
V
Input Voltage Range
Conditions
k=O, VlN =30V
TYPICAL PERFORMANCE CURVES ITT723-1,ITT723-S
LINE REGUlATION AS A FUNCTION OF
INPUT·OUTPUT VOLTAGE DIFFERENTIAL
LINE TRANSIENT RESPONSE
+0.3
•.• HfT/+"":;.:PL"""Vi"'OlT.::;"',-+-+-++--f'"
4.' f-fH-t-++-++++-i2~O ~
~
1.' f-H-+-+-+-I'--+-+-+-I
(I
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HH-+-+-+-+-I-tJ.y- .)v
H-t++++-I-+-H
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~~~TI~;~V++++-I-+-H'u!:
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f-H-+-+-+-+--I-+-+-I
-0,1 VOUT'''V
RSC·Q
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TA'~'C
.
•••oltsc'O
•
".1
Il'ImA
f
V1N '+l1V
-1.0
Vou,'+SV
HH-t-+++-+ Itsc·(I
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+0.2
~
-1 ••
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LOAD REGUlATION AS A FUNCTION OF
INPUT·OUTPUT VOLTAGE DIFFERENTIAL
""ttl "
-o.3.~Wll~·I_,•..,.~-,II_·"""'~::-:-'-~,,""""-+',,-L.-,i
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OUTPUT IMPEDANCE AS A
FUNCTION OF FREQUENCY
LOAD TRANSIENT RESPONSE
HT+-f!l:="DP.CU:::;·~r'N1!.f-+-HH'LO
I.D
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-,.. "'
•
..
'A' Z5~C
+++-I-+-+-H
.
-30
»
r--"1'~V'~U1;"~5V~~mEiE!I~'
VIN "!2V
RIC"
_ ._
:t:~2!AC HtItfI~-tt/;1tIIt -
','HHi-t+-l'-t-+++-I
.r-- ~ OUT~ VOLTAct:
-10
-1.0
STANDBY CURRENT DRAIN AS
A FUNCTION OF INPUT VOLTAGE
I.'
]
"'~nmn
,, ,,
...
..•
..
,,
'A,tte
t- _'A . . '1
I.'
FRtQUENCY-HI
7-41
~~t-
'r' oJ,C
,, ,,
~
I.'
••
..
Vout'YW
'l'G
-
LO
"
lO
INpUtvonAc.t-y
1--
.,
"!
111723
PRECISION VOLTAGE REGULATOR
TYPICAL PERFORMANCE CURVES ITT723-1
MAXIMUM LOAD CURRENT AS A FUNCTION
OF'INPUT.CJ\ITPUT VOLTAGE 'DIFFERENTIAl.
,.,
1
INohQtsjnkl
120
O~
~
-~.,
~
.,
0
"
20
10
.,
"
!If
-0.2
"OUl''''', VIN ' '12Y
20
~-o.2
,\
-
. ,.
"
'.0
-
,.~
a
0.6
lO
YOUT'YIrEF
~O ••
'A''"·C
V
0
10
"
"
0
80
0
100
"
0
OUTPUT CURRENT- lilA
'" ,-:/S'C
~
i
v
'.0
0,'
~
1./
~
~
'00
J.O
; 2.0
~
II
25
'.0
1i
~~
.
.,
20
Il'O
i
OUTPUTCUIiRENT-mA
15
AS A STANDBY CURRENT DRAIN
FUNCTION OF INPUT VOLTAGE
..,
~ ~- - f -f-
!-
10
OUTPUTCUIfR(NT -rnA
;0,1
\ '\
H-t-++-H
-0.75 0
CURRENT LIMITING CHARACTERISTICS
~
0
'00
10
1.0
~
VOUT"511.II,N'oIlV.
Rsc'lon
.
.,
RSC'O
OUTPUlCURRENT-mA
"OUT' 5V, "IN' il2v
RSC'IOn
-
....
i'--b,.
'/~o
......
0
O ..... ~
~
I.......
-0.1
...,
LOAD REGULATION CHARACTERlmCS
WITH CURRENT LIMITING
!-o.1
l - I-
I'-, ~·C
tVIN""M'-"
"..
·,i,..,JC
~
".8
-~J
,
0
~:-
~
K" ,>,
'O'''H-+++-HH-+++-+-1
I I
...... ......
~§-o.rJj
!
\
~
I
'<0.05.
'JMAIC'15O"C
II TH 'I5O'CIW
'STANDly'Mld
100
LOAD REGULATION CHARACTERISTICS
WITH CURRENT LIMITING
LOAD REGULATION CHARACTERISTICS
WITHOUT CU'RRENT LIMITING
I
I
~
"
.
.50
IHP\JTIIOLT"C£'""V
TYPICAL PERFORMANCE CURVES IT1723-5
LOAD REGULATION' CHARACTERISTICS
WITHOUt CURRENT LIM ITING
MAXIMUM LOAD CURRENT AS A FUNCTION
OF INPUT-OUTPUT VOLTAGE DIFFERENTIAL
I
I I
.
r 'rr,
r--.:--
}
~·,;:r-
'UW(,'15O"C
... .,.
IIITAlCAN PACKACl
INOI(ATSINKI
i
f--t--t--f--t--t--t--t--t--H
_~
1i
\
i
,\
'\
II
.,
-~
',,'25·C
,..- "'",c-...ctI
10
0
OllfPUTCURRENT-mA
0.'
l/~
I-
-
'I.'~
7'"
(/~
NTI~SC
• JOt)
IJ
I I
I
...
~
I
-rl""E
D,'
0.3
...
~
I
I
D.'
D,'
,.,
bJ..... I
-§f~<,1
I
D
,50
r--
-
I'..
,'100
JUfoI(;HOttTEMPlRATUR[··C
."
.,
1--
"
"
.,
.'"
50
\
',,'75'C
0
~I
.;.Nr--.,
" "
-
1V1H'IIOUT/-Y
0,1
t-t-t-t-I--'H-t-HII--i"":'-""""c-1
'0.1
t-t-t-t-t-H-t-HHHH
50
H-+++-+-H-+-+ ~~:. '.::~
H-+++4-H-+-+'!' "0
>~ Ot...,jcl++4-TA·25·C-~t
~
~•• rtc
"b-.
~.'" -0.1 f-+-H-+-+T rtfc
F:::
•
1,,'10'C
o"l-t--t--l-'-'i-hf-I-f.JH,.l-:.i.o·cH
"
.LOAD REGUj.ATION CHARACTERISTICS
WITH CURRENT LIMITING
_L . L
H-1H-1--1~~-t-t-t
~
~
.;.
f-
0.2 V,,,' +1ZV+++t+Hl-++--j
IIOUT ' -511
-.50
\ i\
II
oil I I
1.0
o Its( 'Ion
D
lNO tfAT51NKI
\
., f-'
I
CURRENT LIMITING CHARACTERISTICS
0••
.,
:WN:,,~60m!.
IT
120
IIIIN'VOUl'-V
CURRENT LIMITING CHARACTERISTICS AS
A FUNCTION OF JUNCTION TEMPERATURE
TJMAX 'I75'C
RTH'III"CIW -
:\
0'1
0.'
,.,
,.
RTH '15O"CIWPSTANDIY -lIOfIIW'
\
~ Ii•
~
; -0.1
,.,
MAXIMUM LOAD CURRENT AS A FUNCTION
OF INPUT·OUTPUT VOLTAGE DIFFERENTIAL
D
+++1f-HHt--+--+--I
"
"
OUTPUTCURR[NT-mA
7-42
'"
'00
:0.2 0Ll--L...L.":"--L...L..L-,,!:-JLl.....L::l,,
OUTPUTCURRlNT-mA
ITT723
PRECISION VOLTAGE REGULATOR
TABLE 1- RESISTOR VALUES (kO) FOR STANDARD OUTPUT VOLTAGES
Positive
Output
Voltage
Applicable
Figures
(Note 4)
R,
R,
R,
p,
R,
+3.0
1,5,6,9,
12 (4)
1,5,6,9,
12 (4)
1,5,6,9,
12 (4)
1,5,6,9,
12 (4)
2,4, (5, 6,
12,9)
2,4, (5,6,
9,12)
2,4, (5, 6,
9,12)
2,4, (5,6,
9,12)
7
7
4.12
3.01
1.8
0.5
1.2
+100
+250
+3.6
+5.0
+6.0
+9.0
+12
+15
+28
+45
+75
Fixed Output
Output Adjustabte
±10% (Note 5)
±S%
Apptlcable
Negative
Output Voltage
Figures
5% Output
Adjustable ±10%
Fixed Output
::!:S%
R,
R,
R,
p,
R,
7
3.57
102
2.2
10
91
7
3.57
255
2.2
10
240
-6 (note 6)
3, (10)
3.57
2.43
1.2
0.5
.75
2.7
-9
3,10
3.48
5.36
1.2
0.5
2.0
2.7
-12
3,10
3.57
8.45
1.2
0.5
3.3
3.57
3.65
1.5
0.5
1.5
2.15
4.99
.75
0.5
2.2
1.15
6.04
0.5
0.5
1.87
7.15
.75
1.0
4.87
7.15
2.0
1.0
3.0
-15
3,10
3.65
11.5
1.2
0.5
4.3
7.87
7.15
3.3
1.0
3.0
-28
3,10
3.57
24.3
1.2
0.5
10
21.0
7.15
5.6
1.0
2.0
-45
8
3.57
41.2
2.2
10
33
3.57
3.57
97.6
249
2.2
2.2
10
10
91
240
3.57
3.57
48.7
78.7
10
10
2.2
2.2
39
68
-100
-250
8
8
TABLE 11- FORMULAE FOR tNTERMEDIATE OUTPUT VOLTAGES
Outputs from +2 to +7 volts
[Figures I, 5, 6,9, 12, (4)J
ILiMIT
R,
VOUl = [VRE< X R,
+ R,
J
VOUl
=
[VREF X
R,
+ R, J
R,
VREF
= [-2-
X R2 R,
- RI
VREF
R +R
Voul =[-2- X - ' - - '
R,
=
VSENSE
J " R, = R.
R"
Foldback Current Limiting
Outputs from -6 to -250 volts
[Figures 3, 8, 10J
Outputs from +7 to +37 volts
[Figures 2, 4, (5, 6, 9, 12)J
VOUl
Current limiting
Outputs from +4 to +250 volts
[Figure 7J
J;
IKNEE
RJ=R.
= [ VOUl R,
RIC R4
ISHORT CKT
=
+
[VSENSE
VSENSE (R, + R.)
RIC R4
X
R)
RIC
]
R4
Figure 2
Figure 1
BASIC HIGH VOLTAGE REGULATOR
(V"'
7 to 37 Volts)
BASIC LOW VOLTAGE REGULATOR
(V"'
2 to 7 Volts)
=
=
v'
+ R4
J
Vc
csl-----+
PERFORMANCE
Regulated Output Voltage
TYPICAL PERFORMANCE
5V
Regulated Output Voltage
15 V
Line Regulation (.1.VIN = 3 V) 1.5 mV
load Regulation (..l!L=50 mAl 4.5 mV
Line Regulation (.1.VIN = 3 V) 0.5 mV
Load Regulation <.lh=50 rnA) 1.5 mV
Nott: RJ
= ~~:ll
Note: R) =
fat minimum temper.ture drift.
R~~
for minimum temperature drift.
Rl may be eliminated for minimum component count.
7-43
ITT723
PRECISION VOLTAGE REGULATOR
Figure 3
Figure
NEGATIVE VOLTAGE REGULATOR
3~'
NEGATIVE VOLTAGE REGULATOR
Vm
VOUT
T,
2N500'
Vz
1i3
114
CL
cs
31111
NJ .
.13
31111
R,
V-
L - _....._~_ _ _ _ _ _~_~~;~TED
TYP'CAL PERFORMANCE
Regulated Output VQlt.ge
TYP'CAL PERFORMANCE
-15 V
Line Regulation ColVIN
=
LOld Regulation (.lIt
100 rnA) 2 mY
=~
3 V)
Regulated Output VoltaBe
-15 Y
Line Regulation (.lVIN· = 3 V)
1 mV
Load Relul.tlon (.lll = 100 mAl 2 mY
1 mY
Note 3
Figure 4
Figure S
POSITIVE VOLTAGE REGULATOR
(External NPN· Pass Transistor)
POSITIVE VOLTAGE REGULATOR
(External PNP Past Transistor)
T,
2N500'
TYPICAL PERFORMANCE
TYP'CAL PERFORMANCE
Regulated Output VoUage
Regulated Output Voltl'le
+5 Y
line Regulation (.lVlrJ"-= 3 V) 0.5 mY
+15 V
Line Regulation (.1VIN = 3 V) 1.5 mV
LOld Regulation (.lll = 1 A)
15 mY
LOld Regulation (.lIL = 1 A)
5 mY
Figure 6
Figure SA'
POSITIVE VOLTAGE REGULATOR
(External·PNP Pass TranSistor)
FOLDBACK CURRENT LIMITING
v,.
V·
y.
Yc
Vc
RSC 3011
VOUT
VREF
123
R,
123
REGULATED
OUTPUT
.R3
2.711.U
CL
RSC
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
Regulated Output Vollage
+5 V
line Regulation (.lVltJ = 3 V) 0.5 mV
Load Regulation (.lIL = 1 A)
5 mV
• Figure numbers followed by "A" Indicate low temperature range
Regulated Output Volt.ge
+5 V
line Regul.tion elVIN = 3 V) 0.5 mY
load Regulillion (.lIt -= 10 mAl 1 mY
CUrrent Limit Knee
20 inA
ITT723
PRECISION VOLTAGE REGULATOR
Figure 7
Figure 7A'
POSITIVE FLOATING REGULATOR
POSITIVE FLOATING REGULATOR
0, 36V
Dr 36V
INI3~
INI~
RS 111
L-4---_ _ _+--____-j_-.._~~~~~TEo
~-----+-----~--t-----<- ~~~~~ TED
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
Regulated Output Voltage
+50 V
Regulated Output Voltage
+50 V
Line Regulation (olV!N = 20 V) 15 mV
Load Regulation (.lIL = 50 rnA) 20 mV
Line Regulation (.lVIN = 20 V) 15 mV
Load Regulation (.lIL = 50 rnA) 20 mY
Figure 8
NEGATIVE FLOATING REGULATOR
'IN
'---+-+-__..j....,_--l_ _ _ _ _ _+_~'__
T,PICAl PERFORMANCE
Regulated Output Voltage
-100 V
TYPICAL PERFORMANCE
Regulated Output Voltage
-100 V
(~VIN
= 20 V)
Load Regulation(.lIL=100 rnA)
Line Regulation
~~~~MTEo
30 mV
Line Regulation (.lVItJ "'" 20 V)
load Regul.ation (j,!:.=100 rnA!
20 mV
Figure 9
Figure 10
POSITIVE SWITCHING REGULATOR
NEGAT.IVE SWITCHING REGULATOR
~'O m\
20 mV
VIN
II ~'2mH
01
1"2011
123
1-..j....,VV\~+_ _+_~~~~~TEo
CS
RJ lM1
RI
CoMP
Note 3
TYPICAL PERFORMANCE
Regulated Output Voltage
+5 V
line Regulation (. WIN = 30 V) 10 mV
Note 3
Load Regulation (.lll = 2 A)
80 mY
* Figure numbers followed by "A" indicate low temperature range
7-45
R,
lM~1
~'I~~mH
r
,
N.I
REGULATED
OUTPUT
C2 10M
TVPICAl PERFORMANCE
Regulated Output VoUlge
-15 V
line Regulation (j,VIN = 20 Y)
8 mV
Load Regulation (j,h = 2 A)
6 mY
ITT723
PRECISION VOLTAGE REGULATOR
Figure lOA'
Figure 11
NEGATIVE SWITCHING REGULATOR
REMOTE SHUTDOWN REGULATOR WITH
CURRENT LIMITING
v,.
v,.
Ve
V'
0,
,.207,
m
R,
Rse
REGUlATID
YDUT
VRn
OUTPUT
Cl
es
,,,
N.1.
Ie2
TYPICAL PERFORMANCE
Relul.ted Oulput Voll.,.
-15 V
Line Rliul.lion (.1YIN = 20 Y) 8 mY
LOld Helul.lion (lll = 2 A)
6 mY
Note 3
Note 7
...-~~~
lDO,f
ceSL
LOGIC INPUT
21W
TYPICAL PERFORMANCE
Rllul.ted Output Voltl,1
+5 V
Note: CUrrent limit transistor may be
if current
used for shutdown
Line Reeulation (,lVIN = 3 V) 0.5 mY
limiline is not required.
LOld Regulation (.llt=50 rnA) 1.5 mY
Figure 12
Figure 12
SHUNT REGULATOR
SHUNT REGULATOR
VIN
V'N
.~
lDOO
REGULATED
OUTPUT
RWlLRnD
OUTPUT
V'
VI£F
VOUI
R,
Vll--'W~I::.
13 'DOO
723
Cl
v- COMP
~
es
es
N.l.t-------'
•.1.1-____---"
R2
C 5nF
.~'
TYPICAL PERFORMANCE
Relul.t.d Output VOU'II
+5 V
line Relul.tion (.l.VrN = 10 V) 0.5 mY
Load Helul.tion (.lIt = 100 rnA) 1.5 mY
v- co.,
~
C
~'
Sir
TYPICAL PERFORMANCE
Heaul.tld Output Volt.,.
+5 V
lin. Rllul.tion (dV'N _ 10 V) 0.5 mY
LOid H.,ul.lion (6Il-100 mA) 1.5 mY
Note 3
V·
SCHEMATIC DIAGRAM
Figure 13
Ve
OUTPUT VOLTAGE
ADJUST
0,
62V
R,
"
--.0
+------0 COMPENSATION
R2
A-'---- ~~::~NT
Fla,ure numbers fnllowed by "A" Indicate low. temperature range
Va£(
7-46
NON·IHVERTING
INPUT
V-
INVERTING
INPUT
ITT726
TEMPERATURE-CONTROLLED
DIFFERENTIAL PAIR
ITT
-----SEMICONDUCTORS
Connection Diagram
TEMPERAlURE·
E2
CONTROLLED
DIFFER-e-NT-IAl PAIR
o Excellent Transistor Matching
o Close Thermal Coupling
o Fast Thermal Response
ABSOLUTE MAXIMUM RATINGS
e Tight Temperature Control
Units
Characteristics
ITT726 is a monolithic transistor pair in a high
thermal-resistance package, held at a constant
temperature by active temperature regulator
circuitry. The transistor pair displays the excellent matching, close thermal coupling and fast
thermal response inherent in monolithic construction. The high gain and low standby dissipation of the regulator circuit permits tight
temperature control over a wide range of ambient temperatures. It is intended for' use as
an input stage in very-low drift dc amplifiers,
replacing complex chopper-stabilized amplifiers; it is also useful as the nonlinear element
in logarithmic amplifiers and multipliers where
the highly predictible exponential relation between emitter-base voltage and collector curlent matching, close thermal coupling and fast
a single silicon chip using the ITT Planar process.
Operating Temperature
Range ................ -55°C to +125 0C
Storage Temperature
Range .................. -650 to +150 0 C
Lead Temperature
(Soldering 60 seconds) .............. 300°C
Supply Voltage ...................... ±18 V
Maximum Ratings For Each Transistor
Characteristics
Units
Maximum collector-to-substrate voltage .. 40 V
BVcBo .....................•........ 40 V
LVcEo [Note 1] ...................... 30 V
BVEBo ................................ 5 V
Collector Current .................... , 5 rnA
NOTE:
1. Measured at 1 rnA collector. current.
ELECTRICAL CHARACTERISTICS FOR ITT726-1
(-55°C:;;;;TA:;;;;+125°C, Vs=±15V, Radj=62kO unless otherwise specified)
Parameter
Input Offset Voltage
Min.
Conditions
Typ.
Max.
Units
1.0
2.5
mV
10Jl.A:;;;;1 c:;;;;100p.A
VcE =5V, Rs:;;;;500
nA
Ic=10!'A, VcE =5V
Input Offset Current
10
50
Input Offset Current
50
200
Average Input Bias Current
SO
1S0
Average Input Bias Current
250
500
nA
Ic=100p.A, VCE=SV
Offset Voltage Change
0.3
6.0
mV
Ic-10!,A, SV:;;;;VcE:;;;;2SV,
Rs:;;;;100kO
7-47
Ic=100p.A, VcE =5V
nA
nA .' Ic-10!'A, VcE -5V
ITT726
TEM PERA TU RE-CONTROLLED
DIFFERENTIAL PAIR
ELECTRICAL CHARACTERISTICS FOR ITT726-1
(-55°C~TA~+125°C, Vs==15V, R,dj=62kll unless otherwise specified) (continued)
Min.
Parameter
Offset Voltage Change
Typ.
Max.
Units
Conditions
0.3
6.0
mV
Ic=100.uA,
5V~VCE~25V,
Rs~10kfl
1.0
0.2
Input Offset Voltage Drift
.uvrc
10.uA~1c~100MA,
Rs~50fl,
VcE =5V
+25°C~TA~+ 125°C
1.0
0.2
Input Offset Voltage Drift
.u vrc
10.uA~lc~100MA,
Rs~50fl,
VcE =5V,
-55°C~TA~+25°C
Input Offset Current Drift
10
pAloC
Ic= 1OMA, VcE =5V
Input Offset Current Drift
30
pArc
Supply Voltage Rejection Ratio
25
.uV/v
10.uA~1c~100MA, Rs~50n
Low-Frequency Noise
4.0
.uVpp
Ic-10.uA, VcE =5"O, Rs~50 n,
BW=.001Hz to 0.1Hz
Broadband Noise
10
.uVpp
Ic=10.uA, VcE =5V, Rs~50 fl,
BW=0.1Hz to 10kHz
Long-Term Drift
5.0
.uV/week
10.uA~1c~100MA, VcE =5 V,
Ic=100.uA, VcE =5V
Rs~50n,
1.5
High-Frequency Current Gain
Output Capacitance
3.5
TA=25°C
f-20MHz,
Ic=100.uA, VcE =5V
Emitter Transition Capacitance
3.0
1.0
Collector Saturation Voltage
0.5
1.0
pF
IE-O, Vcn --5V
pF
IE=100.uA
V
IB=100.uA,lc=1mA
r-----~------~v.
8
TEMP AOJ
6
21 kn
I ko
01
6.2V
R3
4.8kn
10 U
L-____________~------~-----------------+__oV5
Schematic Diagram-1-5
7-48
ITT726
TEMPERATURE-CONTROLLED
DIFFERENTIAL PAIR
SUPPLY CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
'CURRENT GAIN AS A FUNCTION
OF COLLECTOR CURRENT
'"
I. .
I--I-++If-+-+-H+~C~ ~1~~rN
800
~~J~!~:~.I~'C -
Vs •
TYPICAL
.. I-t-ttl--+++++c:.oI-d+H-l CHARACTERISTICS I
FOR ITT726-1
~
r-
li
,.,/
IZ
i
~
,
"-
"-
i"'-
•
•...
~~~~~~I~~~~lmA~~I~omA
."
COlUCTOR CuRJlf.NT
ELECTRICAL CHARACTERISTICS FOR ITT726-5
unless otherwise specified)
Parameter
!l~V
R~J -6ZkQ
16
1"-.
"
OJ
nMfUATUR[··C
III
1«
(0°C:(TA:(+85°C, Vs =±15V, Ra dJ=75kfl
Typ.
Max.
Units
Input Offset Voltage
1.0
3.0
mV
10,uA:(1c:(1 OOp.A
VcE =5V, Rs:(50fl
Input Offset Current
10
100
nA
Ic=10p.A, VcE =5V
Input Offset Current
50
400
nA
Ic-100p.A, VcE -5V
Ic-10p.A, VcE -5V
Min.
Conditions
Average Input Bias Current
50
300
nA
Average Input Bias Current
250
1000
nA
Ic-100p.A, VCE-5V
Offset Voltage Change
0.3
6.0
mV
Ic=10,uA,5V:(VcE:(25V,
Rs :(100kfl
Offset Voltage Change
0.3
6.0
mV
Ic=100p.A, 5V:(VCE :(25V,
Rs :(10kfl
Input Offset Voltage Drift
0.2
2.0
p'vrc
Ic=100p.A, VcE =5V
Rs:(50fl,
Input Offset Current Drift
10
pArC
Ic=10p.A, VcE =5V
Input Offset Current Drift
30
pArC
Ic=100p.A, VcE =5V
Supply Voltage Rejection Ratio
25
p.VIV
Ic=100p.A, Rs:(50fl
Low-Frequency Noise
4.0
,uVpp
Ic-10p.A, VcE -5V
Rs :(50fl,
Broadband Noise
10
p.Vpp
Ic=10p.A, VcE =5V
Rs :(50fl,
BW=0.1Hz to 10kHz
Long-Term Drift
5.0
p.V/week
BW=0.001Hz to 0.1Hz
High-Frequency Current Gain
Output Capacitance
1.5
f-20MHz,
Ic=100p.A, VcE =5V
3.5
pF
3.0
Emitter Transition Capacitance
1.0
Collector Saturation Voltage
0.5
7-49
Ic=100p.A, VcE =5V
Rs :(50fl, TA=25°C
pF
1.0
V
IE=O, VcB =5V
IE-100p.A
IB=100p.A, Ic=1mA
ITT726
TEMPERATURE-CONTROLLED
DIFFERENTIAL PAIR
+15V
01
IN 7 5 7 A
+15V
Rad;
·62ku
SOn 2 6
SOil
Eou!
Rg
CI
5nF
'----_---.--ISV
SOkll
*FOR -1,75 kO FOR-5
Typical X1000 Circuit
SUPPLY CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
CURRENT GAIN AS A FUNCTION
OF COLLECIOR CURRENT
10
v~ .!
IS V
Rad , °mQ
-<
E
8.0"
z
~
~
=>
6.0
"-
u
i',.
>
~
~
=>
zoo/
I~
f"...
4.0
l"-.
1.0
a
a
0'---'-.L..L.L--l.-....J...J.....I...L-,L-L-l..JL.L.,.-I
lOCI>'
l.OmA
IOmA
10
40
""-
6(1
TEMP!RAruRE ° °c
COllICTOR CURRENT
Typical Characteristics For ITT726·5
7-50
I---
"
III
loa
ITT741
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
ITT
----SEMICONDUCTORS
HIGH PERFORMANCE OPERATIONAL
AMPLIFIER
CONNECTION DIAGRAMS
(TOP VIEW)
• No Frequency Compensation Required
• Short-Circuit Protection
8 LEAD METAL CAN
• Offset Voltage Null Capability
• Large Common-Mode and Differential
Voltage Ranges
• Low Power Consumption
• No Latch Up
IIOfI:""' _ _ 'ef"r.HI
The ITT741 is a high performance monolot~ic
operational amplifier constructed on a single
silicon chip, using the ITT Planar epitaxial process. It is intended for a wide range of analog
applications. High common mode voltage range
and absence of "latch-up" tendencies make the
ITT741 ideal for use as a voltage follower. The
high gain and wide range of operating voltages
provide superior performance in integrator,
summing amplifier, and general feedback applications. The ITT741 is short-circuit protected,
has th~ same pin configuration as the popular
ITT709' operational amplifier, but requires no
external components for frequency compensation. The internal 6dB/octave roll-off insures
stability in closed loop applications.
14 LEAD DIP
Nt
Nt
Nt
Nt
OfFSET
Nt
NULL
INVERTING
INPUT
V·
NON-INVERTING
INPUT
ouTPUT
OFfSET
NULL
Nt
Nt
FLATPACK
Schematic Diagram
N
r.
NC
NC
OffSt T NULL
I"lV UJPUT
V.
INVERTING INPUT
NON INVE.RTlNG
INPUT
OUTPUT
OffSET
NUll
MINIDIP
QFfS[l NUll
INVERT INPUT
NOr-.
INvl~T
INPUT
v·
·'Ve e
OF FSE r
NULL
7-51
i3
2.
3
6
4
,
NC
OUTPUT
OFfSET
NULL
ITT741
HIGH PERFORMANCE
OPERA TIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
ITT74J-1
Characteristics
ITT741-5
I
±18
Supply Voltage ...........................
±22
Internal Power Dissipation. . . . . . . . . . . . . . . . . .
500 (Note 1)
500
±30
±30
Differential Input Voltage ...................
Input Voltage (Note 2) .................•...
±15
±15
-65 to +150
Storage Temperature Range. . . . . . . . . . . . . . . .
-65 to +150
Operating Temperature Range ............. ;
-55 to +125
o to +70
Lead Temperature (Soldering, 60 sec) .......
300
300
Output Short-Circuit Duration .............. Indefinite (Note 3) Indefinite (Note )
NOTES:
1. Rating applies for case temperatures to
125 0 C; derate linearly at 6.5 mW.'°C for am·
bient temperatures above + 75°C.
3. Short circuit may be to ground or either supply. Rating applies to + 125 0 C case temperature and . 75 0 C ambient temperature.
2. For supply voltages less than .- 15V, the absolute maximum input voltage is equal to the
supply voltage.
4. Short circuit may be to ground .or either
supply.
Units
V
mW
V
V
°C
°C
°C
ELECTRICAL CHARACTERISTICS FOR ITT741-1 (Vs=±15V, TA=25°C unless otherwise specified)
Parameter
Min.
Typ. Max.
Input Offset Voltage
1.0
Input Offset Current
Input Bias Current
Input Resistance
Large-Signal Voltage Gain
5.0
mV
30
200
nA
200
500
nA
0.3
1.0
Conditions
Units
Rs
10kn
Mn
50,000
200,000
Output Voltage Swing
±12
±10
±14
±13
Input Voltage Range
±12
±13
V
70
90
dB
Rs~10kn
Rs~10kn
Common Mode Rejection Ratio
RL;;::2kn, Vout=±10V
RL>-:10kn
RL;;:: 2kfl
V
V
Supply Voltage Rejection Ratio
30
150
JLVN
Power Consumption·
50
85
mW
V1n =20mV, RL=2kn,
Transient Response (unity gain)
CL~100pF
Risetime
0.3
1.0
Overshoot
5.0
10
Slew Rate (unity gain) (Pulsed)
JLs
%
VIJLs
0.5
The following specifications apply for -55°C~TA~+125°C:
Input Offset Voltage
6.0
Input Offset Current
500
nA
1.5
JLA
Input Bias Current
Large-Signal Voltage Gain
Output Voltage Swing
mV
RL;;::2kn, Vout -±10V
25,000
±10
7-52
Rs~10kO
V
RL;;::2kO
ITT741
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS FOR ITT741-5 (Vs=±15V, TA =25°C unless otherwise specified)
Min.
Parameter
Typ. Max.
6.0
mV
30
200
nA
200
500
2.0
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Units
0.3
1.0
Conditions
Rs::;;;10kn
nA
Mn
RL ;;::2kn, Vout =±10V
20,000
100,000
Output Voltage Swing
±12
±10
±14
±13
Input Voltage Range
±12
±13
V
70
90
dB
Rs::;;;1Okn
Rs::;;;10kn
Large-Signal Voltage Gain
Common Mode Rejection Ratio
V
V
Supply Voltage Rejection Ratio
30
150
p,V/V
Power Consumption
50
85
mV
RL ;;::10kn
RL ;;::2kn
Vin =20mV, RL =2kn,
CL ::;;;100pF
Transient Response (unity gain)
Overshoot
0.3
Risetime
5.0
%
0.5
V/f1.s
Slew Rate (unity gain)
The
followin~
specifications apply for
O°C::;;;h~
f1.s
+70°C:
Input Offset Voltage
7.5
mV
Input Offset Current
300
nA
800
nA
Input Bias Current
Large-Signal Voltage Gain
RL ;;::2kn
Rs::;;;1Okn
15,000
±10
Output Voltage Swing
Transient Response
Test Circuit
RL ;;::2kn, V out =±10V
V
RL ;;::2kn
Voltage Offset
Null Circuit
v out
6
V in
RL
t
v-
-=7-53
111741
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
,
IJ . ,
lSV
II
400
.I
\0.0
i,i
i
L.
-{-- j
..
--~
i
-
'.
-t-
v • ~ 151,1
I
I
i
f-,.
Y,
O.~
o.l
1
-00
-10
10
00
TtMP[~AIUR£
100
140
Vs ' ! 15V
110
,
100
80
/0
,
!
!
j
:
\.
i
1
i
10
",741
,
i
:
-10 : \.
I
,
"I~
10
!
I
i
",741
i
I
0.1
-00
I
1
I
I
!
10
70
~ 2~~~~~~+-+-+-+-~
B
i
I
00
140
100
-10
10
,
,
/0
~ --....
I
50
I
40
100
140
FREQUENCY CHARACTERISTICS
AS A FUNCTION OF
AMBIENT TEMPERATURE
I
I'-.....
r--.
f--t- .J-I
!
00
TtMPERATUR[ - C
I
I
:
I
-
T
lO -J741
1
IIID
140
-00
-10
10
TtMP[RA7UR[ - C
100
00
140
TtMPERAIURE - C
TtMPERAIURE - C
OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE
40
I
RL ';!21ul
!
i
,
24
:
16
./'
o
~
i
I
I
10
SUPPlY VClTAGE ~! V
7-54
i
1/
A
.I'
10
o
~
/1
I
i
!
I
I
Y
;
I
,!
/1
"A,741
I~
i
I
i
!
~
1.....-
1
I
I
i
,
i
i
/!
r
-5S'C!T"s+125'C
14
i
:
, ./
12
.I'V
V
i
10
16
'./
./
)2
28
INPUT COMMON MODE
VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE
;
1
-5)"'C\1"... +125·C
).
SUPPLY VOLTAGE-tV
.2
,
·t
-10
Vs ",.± 151,1
i
i
/0
i
.
POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE
II
1
11
Vi
H
TtMPERAIURE - C
;
I
i
- C
I
1
40
~/O
i
,
/1
r-.-t--
INPUT OFFSET CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
140
i
i
I
I
1
i .......
.,
. <1
Y
,
LO
i
~
'1
-+ ..
~.O
l.O
._+,
,...
OUTPUT SHORT-CIRCUIT CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
INPUT RESISTANCE
AS A FUNCTION OF
AMBIENT TEMPERATURE
INPUT BIAS CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
500
ITT741·1
!
ID
!
~A741
IS
SUPP!.YVQ.TACI:·tV
10
ITT741
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
200
.
INPUT RESISTANCE
AS A FUNCTION OF
AMBIENT TEMPERATURE
10
VS' tlSV
ITT741·5
INPUT OFFSET CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
Vs ·:!: 15\1
Ys"'±15V
7.0
160
5.0
c
4.0
""-
'"t--,
/'
--r--. r-.
&lA741
b
/'
2.0
/'
V
G
~A7~1
10211304)
TEMPERATURE ··C
&lA741
o
506070
010211304)
TEMPERATURE _·C
FREQUENCY CHARACTERISTICS
AS A FUNCTION OF
AMBIENT TEMPERATURE
1.10
30
AV
Vs" il5V
28
z
o
I
8
i'----
-52
t---.
r----..
r-- r--
Q
~:-,..
i'---- I'-....
--:::: -:;;::;.'/'
'-.....
...........
0.95
211
&lA741
&lA741
41
Ia;
OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE
l6
.,..-
I
i
I
24
20
8
/1
I
I
V
~
INPUT COMMON MODE
VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE
I. o"C~TAH70"C
,
!
I.
i:!l
z
;:;
i:!l
:!'
g
~
i
12
1/
A
10
8
/V
•
i • /!k"
/"
1JA741
o
02468101214161820
SUPPLY VOLTAGE ttVI
/i
>
~I
~
'/
12
15
V
V
I
I'
/
80
10
'\:2kll
28
,/
j
~
I
OOC STA'So1'7o"C
l2
I
V
~,
1021130<0506070
40
TA • 25 C
85
'"
llMP£.RAT!.JRt - nC
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE
/'
SUW RATE
0.90
![Mf'(RAlURE ··C
V
V
&lA741
I!
0102113041506(70010211304)506070
100
~
~~
'",-
I'---
r--
i
,,*~
I.a;
24
50607tI
TEMPERATURE· ·C
OUTPUT SHORT·CIRCUIT CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE
Ys " t15V
"' ......... -.......
I---
10
U
0102113043506070
60
"
VV
l.O
.............
I"'-
L
5
SUPPly Va.TAGE: .. !. V
7-55
/!
i
i
I
I
I
!
!
!
:
I
I
I
I
I
10
~A741
15
SUPPlY VQ.rAGI: - t V
211
ITT741
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES IT1741·1, ITT741·5
POWER CONSUMPTION
AS A FUNCTION OF
SUPPLY VOLTAGE
TA "151:
/
I)
/
/
o
/'
V
/
/
OPEN LOOP PHASE RESPONSE
AS A FUNCTION OF
FREQUENCY
Vs -115V
VS"i15V
t---..
",,741
TA "25 C
\
"-
",,741
15
fRtQUENCY - Hz
SUP!'\.Y Va.TAGE - tV
\
IA· + 25'C
'"'""-
I'
,,/
5
OPEtt LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY
"-
'"
-135
~
",,141
i
fREQUENCY" Hz
INPUT OFFSET CURRENT
AS A FUNCTION OF
SUPPLY VOLTAGE
INPUT RESISTANCE AND
INPUT CAPACITANCE AS A
FUNCTION OF FREQUENCY
10M
TA"15·C
I
!
i
VS"' 15V
16 TA "15·C
I
i
-H-
V
I
i/
;
I It
I~
/
1M
41
---
36
I
II
,I
i"
i!
I
I
I
I
i !
I I'
I;
\
\1
Vs -!.lSV
TA" 2n
RL;~~
!I
:i
j'
Jl'
! [I
Ii;
i
'ii
I;
I
i
!
i
I
ill
i
i
I
fk
",,141
il
11.5
LO
1.0
LOAD RESISTANCE -
'Ii
11.1
OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY
I
t
11.1
!1~41
10k
fRtQUENCV - Hz
OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE
/
III
j
10k
100
15
10
SUP!'\.YVa.TAGE-tV
8
11.1
10
"
, IN '-'i,+I
5
10
,
Ii-..
i,
i
",,141
o
r--.~
,I ,
RIN
I
--
Ii
,5.0
o
100
10
II
It
10k
FREQUENCY - Hz
7-56
i ;,
I,i
",,741
i't--l.' ,
1M
ITT741
HIGH PERFORMANCE
OPERATIONAL AM PLiFIER
TYPICAL PERFORMANCE CURVES
ITT741-1,
INPUT NOISE VOLTAGE
AS A FUNCTION OF
FREQUENCY
ITT741-5 (continued)
INPUT NOISE CURRENT
AS A FUNCTION OF
FREQUENCY
~
~~10-/4 I-+i-irl-+r+"------'
ITT492N
• Hex High Gain Darlington Circuits
Pin Configuration (top view)
The ITT491 and ITT492 were designed to be
used together with MOS IC's and with
common cathode LED's in serially addressed
multi-digit displays. This time multiplexed
system using a segment address and digit
scan method of LED drive minimizes the
number of drivers required.
c
ITT491 Quad Segment Driver
IN 0---"""..-..1.
E
TO OTHERS
DRIVERS
SCHEMATIC
(Each Driver)
ITT491
TRUTH TABLE
ITT492
TRUTH TABLE
ITT492 Hex Digit Driver
Input
Output
E
Output
C
Input
Output
L
H
L
H
H
L
L
H
H
L
SCHEMATIC
(Each Driver)
8-1
OUT
TO OTHER
'----+~ DRIVERS
ITT491, ITT492
MOS TO LED SEGMENT AND DIGIT DRIVERS
ABSOLUTE MAXIMUM RATINGS
(over free air temperature range unless otherwise noted).
PARAMETER
ITT491
ITT492
UNITS
10
10
V
VSs
Vss
/Collector Voltage (2)
10
10
Collector to Emitter Voltage
10
Collector to Input Voltage
10
Supply Voltage Vss (1)
Input Voltage
V
V
10
V
Emitter Voltage
5
V
Emitter to Input Voltage
5
V
VD D to Input Voltage (3)
5
5
V
Continuous Collector Current
50
250
mA
Continuous VD DCurrent
600
mA
BOO
BOO
mW
Oto70
o to 70
C
-65 to 150
-65 to 150
C
260
260
C
Continuous Total Power Dissipation
Operating Free-Air Temperature Range
Storage Temperature Range
Lead Temperature 1/16 Inch from Case
for 10 Seconds
NOTES:
(1) Vss terminal voltage is with respect to any other
(3) With the exception of the inputs, the Vdd term 1nal must always be the most negative device
voltage for proper operation.
device terminal.
(2) Voltage. values are with respect to Vss terminal
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
(unless otherwise noted VS§.=10V;TA = 0 C to 70 C).
ITT491
PARAMETER
TYP.
MAX.
UNIT
0.9
1.2
V'
VIN = B.5V through 1 K
IOL =50mA, VE = 5V,
TA =25 C
0.9
1.5
V
\lIN = B.5\{ through 1 K
IOL = 50mA, VE =5V
100
jJA
Ve H = 1OV, VE = 0 .
liN = 40uA
100
jJA
Ve H = 1OV, VE = 0
VIN = 0.7V
3.3
mA
VIN = 10Vj IOL = 2QmA
VIN = 0, VE = 5V
IE R Reversed biased
emitter current
100
IJA
Ie =0
Iss supply current
1.0
mA
Ve EL Low-Level
collector-to-emitter
voltage
MIN.
Ie H High-Level
collector current
II Input current at
maximum input voltage
2.0
8-2
TEST CONDITIONS
ITT491, ITT492
MOS TO LED SEGMENT AND DIGIT DRIVERS
ITT492
PARAMETER
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
0.9
1.2
V
VIN = 6.5V through 1 K
IOL = 250mA, TA = 25 C
0.9
1.5
V
VIN = 6.5V through 1 K
IOL = 250mA
200
JJA
VOH =10V, liN =40uA
200
IJA
VOH =10V, VIN =0.5V
3.3
mA
VIN = 10V, 10 L = 20mA
1.0
mA
Vo L Low-Level
output voltage
IOH High-Level
output current
II Input current at
maximum input voltage
2.0
Iss supply current
NOTE: All typical values are at TA =25 C.
SWITCHING CHARACTERISTICS: Vss = 7.5V, TA = 25 C
DEVICE
TYP.
MIN.
ITT491
ITT492
MAX.
UNIT
CONDITIONS
TEST
20
ns
TPHL
RL :::200, VIN H = 4.5V
100
ns
TPLH
CL=15pF, VE =0
40
ns
TPHL
RL=39, VINH =7.5V
600
ns
TPLH
CL=15pF
7.5V
~:~;---~~50%
C
-O-~
:
Waveforms
TPHL~
I
I+-
~
VIN
:+-0.9 MA
VOL=1.25V
200
/JA
0.9
mA
Slope typically 4 kn
VIH = 3.0V
uA
Slope typically 11 kn
VIL =O.4V
IOH = 200 UA
8-5
VIL <0.4 V
VOH = 15V
-
ITT- - - - ITT501
QUAD SEGMENT DRIVER
Package 14 pin Dual-in-Line
SEMICONDUCTORS
QUAD SEGMENT
DRIVER
• MOS to LED segment driver
• 50
rnA source or sink capability
• Suitable for desk top and pocket calculator
• Operation down to 5V
• High gain Darlington Outputs
PIN CONFIGURATION (Top View)
The ITT 501 is a monolithic, integrated circuit
which provides the interface between MOS
integrated circuits and Light Emitting Diode
(LED) displays. The ITT 501 is designed to be
used in serially addressed multi-digit displays.
This time-multiplexed system, using a segment
address and digit scan method of LED drive,
minimizes the number of drivers required. This
circuit is designed to be used with current
source resistors in .series with the LED
segments. This aids in matching segment
intensity and reduces the total power dissipation. A resistor value of 200 ohms provides a
good current source for each segment when the
ITT 501 together with the ITT 500 (Digit Driver)
is used at 15 volts with 2 volt/25mA LED
displays. The Vee terminal must be connected
to the most positive supply.
SCHEMATIC
YIN
4.0K
6.81<
Yoo
6.8K
YOUT
(Each Drive, 4 per package)
ABSOLUTE MAXIMUM RATINGS
(Measurement with respect to GND)
Characteristics
Unit
18 V
Supply Voltage Vee
Input Voltage (VIN#Ve e )Vin
18 V
18 V
Isolation Voltage Vss.
Continuous Total Power800mW
Dissipation
Storage Temperature
Range
-55 9 C to + 125°C
Operating Temperature
OOCto + 50°C
Range
8-6
ITT501
QUAD SEGMENT DRIVER
D.C. SPECIFICATIONS - ITT 501 At 25 C unless otherwise specified. All voltages are with
respect to Gnd. All currents into the device are +.
PARAMETER
V
cc
IOL
15v
IOH
15v
IIH
15v
MIN
MAX
NOTES
TEST
CONDITIONS
ma
liN = 0.35 ma
Vo = 2.7v
VR = 4.6v
100
!la
VIL .7v
Vo = 2.7v
VR = 18v
2.0
ma
-50
0.35
UNITS
Typical4kn
Slope
VIH = 8.5v
Vo=2.7v
IlL
15v
25
lJa
8-7
Typical 17 .6Kn· VIL = 0.7v
Slope
Vo=2.7v
VR = Open
ITT
--------11T502
HEX DIGIT DRIVER
PACKAGE 16 Pin Dual-in-Line
SEMICONDUCTORS
HEX DIGIT DRIVER
• MOS to LED digit driver
• 200 rnA sink capability at 0.4 volts
• Suitable for pocket calculators
• "Chip enable" for extended battery life
• High gain Darlington Outputs
ITT 502 is a monolithic integrated circuit which
provides the interface between MOS integrated
circuits and Light Emitting Diode (LED) Digit
Displays. The ITT 502 is designed to be used in
serially addressed multi-digit displays. This
time-multiplexed system, using a segment
address and digit scan method of LED drive,
minimizes the number of drivers required. This
circuit, together with the ITT 503 (segment
driver), was designed to operate with two
different power supplies.
Pin Configuration (Top View)
SCHEMATIC
The first being a battery (Vee) where the
vOltage may range from 3.5 to 9 volts and
supplies the majority of the load currents
(display currents). The second (Vss) supply,
being a D.C. to D.C. converter or regulator
which maintains the voltage between 7 and 9
volts. In order to maximize the voltage from the
battery across the load, the ITT 502 output was
designed to provide 200 mA with only O.4V
Vo L. The "Chip Enable" circuit allows turning
the load (display) "off" independently of the
input signals.
Characteristics
Vss (Vss VIN orVeE)
. Vee
Continuous total power
dissipation
Storage temperature range
Operating temperature
(Each driver, 6 per package)
Units
9 V
9 V
800mW
-55 C to 125 C
o C to 50 C
8-8
ITT502
HEX DIGIT DRIVER
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted TA =25 C, measurements with respect to GND)
PARAMETER
V S5
V cc
MIN
IOl
6.5
3.2
200
iOH
8,8
8.8
IOH
8.8
8.8
IIH
8.8
8.8
MAX
UNITS
NOTES
TEST
CONDITIONS
rnA
VIH = 6.5
VeE =Ov
VOL = O.4v
400
IJA
VIN ~0.9
VCE=OV
VOH =8.8V
400
IJA
VIH = 8.8v
VCE) 6.5v
VOH = 8.8v
rnA
2.0
Slope typically
4Kfl
VIH = 8.8v
VCE=OV
VOUT = Open
III
8.8
Open
lJA
15
Slope typically
11 Kfl
Vil = 0.5v
veE =Ov
VOUT = Open
ICEl
8.8
150
8.8
IJA
Slope typically
12Kfl
vC'E =0.95v
VIN = Ov
VOUT = Open
ICEH
8.8
8.8
0.40
1.50
rnA
Slope typically
8Kfl
VC"E =6.5
VIN =Ov
VOUT = Open
8-9
- ITT- - - - ITT503
QUAD SEGMENT DRIVER
PACKAGE 16 Pin Dual-in-line
SEMICONDUCTORS
QUAD SEGMENT
DRIVER
• MOS to LED. segment driver
• Constant current source, programmable.
• Suitable for pocket calculators
• "Chip enable" for extended battery life
• High gain Darlington Outputs
The ITT 503 is a monolithic integrated circuit
which provides the interface between MOS
integrated circuits and Light Emitting Diode
(LE.P) displays. The ITT 503 is designed to be
used in serially addressed multi-digit displays.
This time-multiplexed system, using a segment
address and digit scan method of LED drive,
minimizes the number of drivers required. This
circuit, together~with the ITT 502 was designed
to operated with:two different power supplies.
The first being a battery, (Vee) where the
voltage may vary from 3.5 to 9 volts and
supplies the majority of the load currents
(display currents). The second, (Vss) supply,
being a D.C. to D.C. converter or regulator
which maintains the voltage between 7 and 9
volts. By connecting a resistor in series with
the VOUT terminal and the LED anode (i.e.
resistor across VOUT and VREF) an adequate
current source is generated. The voltage across
the resistor is equivalent to a diode forward
voltage drop (+ 0.6V), thus in order to control
20 mA, a resistor value of 300 is required. The
"chip enable" circuit allows turning the load
(display) "off" independently of the input
signals.
Pin Configuration (Top View)
SCHEMATIC
Vas
5K
VOUT
ABSOLUTE MAXIMUM RATINGS
(Measurements with respect to GND)
Characteristics
Unit
Vss (Vss VIN orVeE)
9V
Vee
9V
Continuous total power
dissipation
800 mW
Storage temperature range -55°C to + 1250C
Operating temperature range O°C to + 50°C
Vee
(Each Driver, 4 per package)
ITT503
QUAD SEGMENT DRIVER
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted TA = 25 C, measurement with respect to GND)
PARAMETER V 55
V cc
MIN
-20
IOl
6.5
3.2
IOH
8.8
8.8
liN H
7.0
IINl
MAX
UNITS
TEST
CONDITIONS
mA
VIN = 6.5v
VeE·= 1.0v
VOUT = 2.2v
-0.3
mA
VIN = 8.8V
VeE = 6.5v
VOUT = O.Ov
Open
1.5
mA
VIN = 5.0v
VeE = O.Ov
VOUT=O.OV
VREF=Open
7.0
Open
100
uA
VIN =1.5v
VeE = O.Ov
VREF=O.OV
leEl
8.8
Open
uA
VCE=0.5v
VIN = O.Ov
ICEH
8.8
Open
mA
VCE =6.5 v
VIN = O.Ov
VOUT = Open
20
1.5
NOTE: IINH - Slope typically 10KO
8-11
_'Imm
-L-L _________'T_Ts_os
GAS DISCHARGE SEGMENT DISPLAY DRIVER
SEMICONDUCTORS
GAS DISCHARGE SEGMENT
DISPLAY DRIVER
Pin Configuration
(Top View)
• Segment Drivers
• 18 Pin Ceramic Package
• Programmable Current
• .2 to 2.0 mA (Note 2)
-gO Volt Operation
The ITI505 is a monolithic integrated circuit
designed to provide the interface to gas
discharge type display drivers.
The ITT505 incorporates eight segment
drivers with equal segment currents. All
eight segment currents are programmed by a
single resistor at Pin ,1. The segment current
may be varied from .2 to 2.0 mAo
Your
The device also incorporates diode clamps
on all eight inputs to permit rapid recharging
of input capacitor in applications where
input signal is capacitively coupled.
.T.q.7. _~9.~.~ ...
CIRCUITS
Absolute Maximum Ratings
Vout ................. 90 VDC (See Note 1)
Yin ........................ -1.0 to 35 VDC
lout ............................... 3.0mA
Power dissipation .................. 800mW
Operating Temperature ........... 0 to 70·C
Storage Temperature ......... -55· to 125·C
Circuit Schematic
NOTE: Current limiting resistor should, be Incorporated for
testing,
NOTE: Inputs to unloaded stages should be grounded,
8-12
"
,
ITTSOS
GAS DISCHARGE SEGMENT DISPLAY DRIVER
Test Circuit
+50V
Typical Application
+90V
to anode drivers
t
:RL"27K
:
75K
IMIl
____
~UI
+
__________ _
t
RSios
IMO
r----f------)To 7 other drivers
AB-
-;. 90Y
cD-
ITT
E- 505
F-
~
GH-
ITT 505
-
Electrical Characteristics (T A = 25°C, all voltages with respect to Pin 10)
Parameter
lout
Min
Typ.
.2
Max
Units
2.0
mA
= .2 to 2.0mA
V
V
Yin
Yin
= BV, lout == .2mA
= BV, lout = 2.0mA
V
lin
lin
= .5mA
= -1.0mA
10
%
lout
10
uA
3.5
VBias
2.5
5.0
2.B
6.0
3.25
7.0
B.O
11.0
15.0
1
lout Matching
Output Leakage
=
Yin
3.5
3V~ VBias ~5V
lout
Yin
Yin
Conditions
8-13
= .2mA to 2.0mA
=
=
=
Vout
90V
Yin
gnd
RL
1 MO
_
I
ITT508
OCTAL DIGIT DRIVER
mm _ _ _ __
.1...1..
SEMICONDUCTORS
OCTAL DIGIT DRIVER
•
•
•
•
Drivers per package
MOS to LED interface
40ma sink capability at .45 volts Vol
Input current 500uA max. for 40mA sink
OUT 0
The ITT50B is a monolithic integrated circuit
which is designed to provide the interface
between MOS integrated circuits and Light
Emitting Diodes.
OUTF
OUTG
OUTH
The ITT50B is ideally suited for use in serially
addressed multidigit displays. This time
multiplexed system using a segment address
and digit scan method of LED drive,
minimizes the drivers required.
Pin Configuration
The ITT50B when used with the ITT509
requires only two IC packages to drive eight
digits, seven segments and one decimal.
+V
The ITT50B contains eight independent
drivers, each capable of sinking 40mA with a
Vol of .45 volts. The maximum input current of
400uA is all that is required to sink 40mA.
IK
38K
IN o----'l./VV""'I"'t
15K
4K
Maximum Ratings )TA at 25°C)
V+ ............................................. 10Volts
Vin .................................................... Vt
10ut ...............................................BOmA
Schematic Diagram
8-14
OUT
ITT508
OCTAL DIGIT DRIVER
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted TA = 25°C, all measurements with respect to GND)
(V + = 10 volts, V- = GND unless otherwise noted)
Parameter
Condition
Units
Limits
Min.
Max.
Output Leakage
lin::: 25uA
-
300
uA
Input Current
lout
40mA
Vin
V+"
lout::; 300uA
=
=
-
500
uA
25
uA
-
.45
-
10.0
mA
-
5.0
mA
5.0
usee
5.0
usee
Input Current
= 40mA
= V+·
= 10volts
= 5 volts
Output Voltage
lout
Vin
Is
V+
Is
V+
ton
to 90% lout
toft
to 10% lout
Volts
•
I
'5V}J.A
Video input signal ...... 3(1 to 6)V
Input current duing line flyback
pulse ................. 0.2 to 2mA
Switch over current ......... >2 mA
Time difference of output signal
Pin 2 and line flyback pulse
at pin 10 .................. <20}J.S
Current consumption
(see Fig. 6) ................. 40mA
Ambient temperature
range ................ 0 to +60°C
Design and Operation of the TBA940
The sync separator separates the synchronizing
pulses from the composite video signal. The
noise suppression circuit which does not need
any external components comprises an inte-·
grating and differentiating network which cleans
the synchronizing signal from distortion and
noise.
The frame sync pulse is obtained by multiple
integration and limiting of the synchronizing
signal, and is available at terminal 7. The RC
network normally required between the sync
separator and frame oscillator is no longer
needed.
The line oscillator frequency is set by a 10nF
capacitor (Polystyrene, pin 13) which is charged
and discharged periodically by two internal
current sources. The external resistor at pin
14 defines the charging current and consequently, in conjunction with the oscillator capacitor the line frequency.
8-23
CHARACTERISTICS At Tamb -25°C,
fo=15625Hz*) in the test circuit Fig. 1
V,
t,
RoutT
t,
Rou "
V2res
.10
Amplitude of frame pulse ... . .. >8V
Frame pulse duration ...... >150}J.s
Output resistance (high-state)
at terminal 7 .... ; .. 10(7.5 to 13)kn
Output pulse duration ...... 4 to 8p.s
Output resistance (high-state) at
terminal 2. See fig. 3 ........ =5.6a
Output voltage at 1,=20mA .. <0.55V
Oscillator frequency at C"I1=10nf
and R"I1=10.5K .... 15625±1562Hz
Frequency pull-in range 400 to 800Hz
Frequency hold-in range 400 to 800Hz
Slope of phase comparator control
loop ........ ,........... 2kHz/}J.s
Gain of phase control ........... 20
Adjustable phase shift between
leading edge of video signal and
line flyback pulse ...... see Fig. 3
Phase shift at td=6}J.S and
Pin 11 open ...... 1.6(0.5 to 2.7)}J.S
* By modifying the resistor of the oscillator at
pin 14 the TBA940 can also be used for other
line frequencies.
The phase comparator compares the sawtooth
voltage of the oscillator (see Fig. 3) with the
line sync pulses. Simultaneously an AFC voltage is generated influencing the oscillator frequency. A frequency range limiter restricts the'
frequency hold-in range to ±800Hz. The oscillator sawtooth voltage, which is in a fixed
ratio to the line sync pulses, is compared with
the flyback pulse in the phase control circuit,
in this way compensating all drift of delay
times in driver and line output stages. The correct phase position and hence the horizontal
position of the picture can be adjusted by a
10ka potentiometer connected to pin 11. Within the adjustable range the output pulse duration (pin 2) is constant. Any larger displacements of the picture, e.g. due to non-symetrical
picture tube, should not be corrected by the
phase potentiometer. In any case the flyback
pulse must overlap the sync pulse on both
edges. (See Fig. 3).
TBA940
HORIZONTAL DEFLECTION PROCESSOR
FOR THYRISTOR (SCR) OUTPUT STAGES
The switching stage has an auxiliary function.
When the two signals supplied by the. sync
separator and the phase control circuit respectively are in synchronism a saturated transistor is paralleled to the integrated 2kO resistor at terminal 9 and ground. Thus the time
constant of the filter network at terminal 4 increases and consequently reduces the pull-in
range of the phase comparator circuit for the
synchronized state to approximately 50Hz.
This arrangement ensures distortion-free operation.
stage. If the supply voltage goes off (e.g. by
switching off the A.C. voltage) a built-in protection circuft takes care to provide defined
line frequency pulses down to V,,=4V and
shuts off when Va gets below 4V preventing
pulses of undefined duration and frequency.
Vice ver.sa if the supply voltage rises, defined
pulses in duration and frequency will appear
at the output terminal when Va reaches 4.5V.
In the range between Va=4.5V and full supply
voltage the shape and frequency of the output
pulse are nearly constant.
For video recording operation this automatic
switchover can be blocked by a positive current fed into terminal 8, e.g. via a resistor
connected to pin 3. It can also be useful to
connect a resistor of about 6800 or 1ko between pin 9 and ground. The capacitor at terminal 4 may be lowered, e.g. toO.1p.F. These
alterations do not significantly influence the
normal operation of the IC and thus do not
need to be switched out, when changing from
VTR to TV or vice versa.
Fig. 3 - Phase relations of the TBA940. The
line flyback pulse overlaps the video signal
sync pulse on both edges.
i---'d--Flyback
The short circuit proof output stage delivers
at terminal 2 output pulses of duration and
polarity suitable for driving the output driver
pull.
./
I
~
(Video)
BAS Signa I
v£
10
Output
put..
V,
I
.. " -
r-
20ms . ,
Rv
3
---------,
I
I
BC327
I
I
I
BAS
Input signal ~(Video)
~ 1
B1120
.0.11'
o
Phase'
8-24
,
\
\
\
'\
-,
-,
-,
:~mepuises
f:'
...
~
Fig 4: Operating circuit
TBA940
"
-A
10
7
I
I
TBA940
HORIZONTAL DEFLECTION PROCESSOR
FOR THYRISTOR (SCR) OUTPUT STAGES
Vertical Output
~~50~s~ame
R5
+24 V
Fig6
Ik
*
I
I
6.ak
BC327
TBA 940
...J47n
J
0-/
6
VIDEO
I
r~1q9~I~
L
1;10
Jl
O.lu
100
-
Flyback
Pulses
O.47u
o
Frequency Phase
Fig 5: Another possibility for the line frequency adjustment
* Input circuit should be optimised for particular design of TV receiver.
n
TBA 9'0
500
Fig. 6 -
/
Graph for determining series resistance Rs.
R '00
v
Rv=3~On!
•
1300
270n)
200
-I
22rinf-/
l----15~6'i
180n
100 f---
L
-moW
120n
J.
/
82n
68n
10
20
-VB
8-25
7
330n~V
30V
_I
TBA950
mm
HORIZONTAL DEFLECTION
JLJL ________P_R_O_C_E_S_80_R__F-O-R-T-V--RE-C-E-IV-E-R-S
SEMICONDUCTORS
HORIZONTAL DEFLECTION PROCESSOR
FOR TV RECEIVERS
Fig. 2"An in Plastic Dual In-Line
TO-116 package
Monolithic integrated circuits for pulse separation and line synchronization in television receivers with transistor and tube output stages.,
Each circuit comprises the sync-separator with
noise suppression, the frame pulse integrator,
the phase comparator, a switching stage for
automatic change-over for noise immunity, the
line oscillator with frequency range limiter, a
phase control circuit, the output stage and a
supply voltage stabilizer. The circuit delivers a
prepared frame sync pulse for triggering tlile
frame oscillator. The phase comparator may
be switched over for video recording operation.
Due to large scale integration very few external
components are needed. Fig. 1 shows the block
diagram.
The TBA950 is available in two groups with
different output pulse widths.
Fig. 1 -
Block diagram and Test Circuit
I
I
9V
4.7 M
0.33 P
I
"'
f-+-o--+4
..---------o
r+9:: - - -IIM
~L
r------:----
~
-l62
Upon request there is also available a
qu'ad in-line version TBA 950 "S".
H
n . n Flam. PUll,'
0.J
I
Dimensions in mm
. 50~
3
+2'~
390
TBA 950-. - - - - - - - - . ,
I
:SLJ
,----+-:71
Sync separator
with noll'
luppr.llion
2
Output
'>.8k
Oscillator
10
with
frequency
range limiter
4,7 k
BAS
Input Ilgnal
(Video)
13
Line fl,back
pul••, 10. V
14
Phase
8-26
TBA950
HORIZONTAL DEFLECTION
PROCESSOR FOR TV RECEIVERS
MAXIMUM RATINGS
I,
I,
v,
I,
v,
18
V
ll
1,0
Tamb
Supply current (see Fig. 6) .... 50mA
Input Current ................ 2mA'
Input voltage ..........'...... '-6V
Output current .............. 22mA
Output voltage ............... 20V
Switch-over current for
video recording operation ..... 5mA
Phase adjustment voltage .... 0 to V3
Flyback peak pulse current .... 5mA
Ambient temperature ......... 60°C
RECOMMENDED OPERATING CONDITIONS
for operating circuit Fig. 4 and 5
v.
pp
1,0
Tamb
CHARACTERISTICS at Tomb == 25°C, to==
15,625H.* in the test circuit of Fig. 3
Amplitude of frame pulse ..... >8V
Frame pulse duration ..... >150,u.s
Output resistance at
Pin 7 (High state) .. 10(7.5 to 13)Kn
Duration of output pulse
t,
TBA950-1 .............. 22 to 26,u.s
t,
TBA950-2 .............. 25 to 28,u.s
Rout 2
Output resistance at Pin 2
(High state) see Fig. 3 .... =5.6Kn,
V2 res
Output voltage at L = 20mA. <0.55V
fo
Oscillator frequency
at C"/1 == 10nF and
R,,/,
10.5Kn .... 15,625±1562Hz
Frequency pull-in range .. 400 to 800Hz
± Mp
± MH
Frequency hold-in
range ............. 400 to 800Hz
dfo/dtd Slope of phase comparator
control loop ........... 2KHz/,u.S
dtd/dtp Gain of phase control .......... 20
tp
Adjustable phase shift
betwen leading edge of video
signal and line flyback
pulse ................. See Fig. 3
6,u.s,
tp
Phase shift at td
Pin 11 open ........ 1.6(0.5 to 2.7),u.S
* By modifying the resistor of the oscillator at
pin 14 the TBA950 can also be used for other
line frequencies.
=
Input current during sync
pulse ...................... >5p.A
Video input signal ....... 3(1 to 6)V
Input current during line'
flyback pulse ........... 0.2 to 2mA
Switch over current ......... >2mA
Time between leading edge
of the outpuf signal and the
middle of the flyback-pulse
at pin 10 .................. <20,u.s
Current consumption
(see Fig. 6) ................ 40mA
Ambient temperature
range ................ 0 to +60°C
=
Flyback
pulse
I'--td - -
V,o
I
I
I
/
I'
....
VE
Fig. 3-Phase relations of the TBA950. The
clipped line flyback pulse must overlap' the
video signal. Sync. I?ulse.
Output
pulae
V2
10
8-27
\
\
\
.
~
/
(Video)
BAS Signa I
,
A
-t
_t
t}
.
JL
",.
_t
TBA950
HORIZONTAL DEFLECTION
PROCESSOR FOR TV RECEIVERS
r- 1
:V~ram.
Fig. 4-Block diagram and test circuit for the
characteristics. Component tolerances ±1 %
20ms
pull..
Rv
7
+Va
3
-------.
I
I
I
I
68k
2
I
IL
BAS
Input ligna I
(Video)
I
TBA 950
sf
J.-
1
0.1/J
Line
Flyback
pulses
o
/-20ms--/
9 V : : r t : : J L Frame pulse.
7
-,
3
-----~
I
I
I2
TBA 950
II 10
1-
Input Ilgnal 8
BAS
(Video)
![
1
0.111
Line
flybock
pulsas
Fig. 5 Another possibility for line frequency adjustment
*Input circuit should be optimized for particular design of TV receiver.
8-28
o
TBA950
HORIZONTAL DEFLECTION
PROCESSOR FOR TV RECEIVERS
Design and Operation of the TBA950
The sync separator separates the synchronizing pulses from the composite video signal.
The noise suppression circuit which does not
need any external components comprises an
integ rating and differentiating network which
cleans the synchronizing signal from distortion
and noise.
The frame sync pulse is obtained by multiple
integration and limiting of the synchronizing
signal, and is available at terminal 7. The RC
network normally required between the sync
separator and frame oscillator· is no longer
needed.
The line oscillator frequency is set by a 10nF
capacitor (Polystyrene, Pin 13) which is
charged and discharged periodically by two
internal current sources. The external resistor
at Pin 14 defines the charging current and
consequently in conjuction with the oscillator
capacitor, the line frequency.
The phase comparator compares the sawtooth
voltage of the oscillator (see Fig. 3) with the
line sync pulses. Simultaneously an AFC voltage is generated influencing the oscillator frequency. A frequency range limiter restricts the
frequency hold-in range to ±aOOHz. The oscillator sawtooth voltage, which is in a fixed
ratio to the line sync pulses, is compared with
the flyback pulse in the phase control circuit,
in this way compensating all drift of delay
times in driver and line output stages. The
correct phase position and hence the horizontal
position of the picture can be adjusted by a
10kll potentiometer connected to pin 11. Within the adjustable range the output pulse duration (Pin 2) is constant. Any larger displacements of the picture, e.g. due to non-symetrical
picture tube, should not be corrected by the
phase potentiometer. In any case the fly back
pulse must overlap the syn9 pulse on both
edges (see Fig. 4).
nized state to approximately 50Hz. This arragement ensures distortion-free operation.
For
video recording operation this automatic
switchover can be blocked by a positive current fed into terminal a, e.g. via a resistor connected to Pin 3. It can also be useful to connect a resistor of about 6an .or 1 KII between
Pin 9 and ground. The capacitor at terminal 4
may be lowered, e.g. to O.1,uF. These alterations do not significantly influence the normal
operation of the IC and thus do not need to
be switched out when changing from VTR to
TV or vice versa.
The short circuit proof output stage delivers
at terminal 2 output pulses of duration and
polarity suitable for driving the output driver
stage. If the supply voltage goes off (e.g. by
switching off the A.C. voltage) a built-in protection circuit takes care to provide defined
line frequency pulses down to V, = 4V and
shuts off when V, gets below 4V preventing
pulses of undefined duration and frequency.
Vice versa if the supply voltage rises, defined
pulses in duration and frequency will appear
at the output terminal when V, reaches 4.5V.
In the range between V, = 4.5V and full supply voltage, the shape and frequency of the
output pulses are nearly constant.
II
TBA 950
500
/
R 400
Rv'3~0Ilt
L
-;
·33OIIf-/
TIOII/- ~
2');11/--/
200
18011
ri
15~h V
12011
10Of--
The switching stage has an auxiliary function.
When the two signals supplied by the sync
separator and the phase control circuit respectively are in synchronism a saturated transistor
is paralleled to the integrated 2kn resistor at
terminal 9 and ground. Thus the time constant
of the filter network at terminal 4 increases
and consequently reduces the pull-in range of
the phase comparator circuit for the. synchro-
~miLi
8211
6811
10
.
30V
Fig. 6-Graph for determining series
resistance Ps.
8-29
TBA120S
INTEGRATED FM/IF
AMPLIFIER AND DEMODULATOR
ITT
----SEMICONDUCTORS
INTEGRATED FM/IFAMPLIFIER
AND DEMODULATOR
.
FJg.2"A" in Plastic Dual In-Line
TO-116 package
The monolithic integrated FM /IF amplifier TBA
120 S is designed specifically for use in the
sound I F part of television receivers and the
FM /IF part of radio receivers. It comprises a
broadband symmetrical amplifier and a coincidence circuit for the demodulation. For the
volume control, a potentiometer may be connected between pin 5 and ground. Since the
potentiometer carries DC only the leads to and
from the potentiometer will not be affected by
hum; remote operation thus presents no diffiCUlty. The gain is 68 dB and AM rejection ratio
55 dB. The TBA 120 S has excellent limiting
properties, and needs only very few externar
components. The frequency characteristic of
the demodulator curve shows excellent stability.The permitted supply voltage range is 6 ...
18 v.
.
Pin. 3 is the collector and pin 4 the base of an
additional transistor suitable for use as an AF
preamplifier or as a switching transistor for
treble cut by means of an RC combination. An
internal 12 V Zener diode connected to terminal
12 may be used for stabilizing the supply
voltage for the TBA 120 S or ·for other stages.
Max. Zener current 15 mAo
I
I
_ - Z62 .-J
Dimensions in mm
Upon request there is also available a
quae! in-line version TBA 120 S "B"
.0lOmf
r---~,
r----~--~~--~
~I-----..,
Fig. 1: Application as 5.5 MHz sound IF amplifier
In connection with the integrated output
resistor R8/11
2.6 kQ the 22 nF capacitor
between pins 8 and 11 determines the time
constant of the de-emphasis.
=
o
8-30
o
TBA120S
INTEGRATED FM/IF
AMPLIFIER AND DEMODULATOR
All voltages are referred to pin 1.
Maximum Ratings
Supply voltage
Vll
18
V
Voltage at pin 5
Vs
4
V
Current into pin 3
13
14
5
mA
2
mA
R13/l4
1
kQ
Operating current of the Z-diode
permanent
112
15
mA
1 min max.
h2
20
mA
Ptot
Ptot
400
mW
500
Ambient operating temp. range
Tomb
-15 ... +70
mW
DC
Storage temperature range
1s
-40 ... +125
DC
Supply voltage range
Vll
6 ... 18
V
Current consumption
pin 5 open
III
14 (10" . 18)
mA
pin 5 grounded
III
16 (12".20)
mA
Frequency range
fin
0 ... 12
MHz
IF voltage gain
Gv
68
dB
250
mV
Current into pin 4
Resistor parallel
to pins 13 and 14
Power dissipation
permanent
1 min max.
Characteristics
forVll=12V, tin=5.5MHz, Tamb=25 DC
IF output voltage
in case of limitation
V6pp,
V10pp
AF output voltage
for t1tin = ± 50 kHz, Vin = 10 mV,
fAF = 1 kHz, Q = 45, k = 4 %
Va
1.1
V
for t1fin = ± 25 kHz, Vin = 10 mV,
fAF = 1 kHz, Q = 20, k = 1 %
Va
0.55
V
Input voltage for start of limitation
for t1fin = ± 50 kHz, fAF = 1 kHz, Q = 45
Vin
30 « 60)
f.J-V
Input impedance
Zin
40 kQ 114.5 pF
(>15 kQ II
6 pF)
Ra/ll
2.6
Output resistance
8-31
<
kQ
TBA120S
INTEGRATED FM/IF
AMPLIFIER AND DEMODULATOR
Volume control range
VB (P = 5 kQ)
70
Va (P = 0)
DC level of output signal
at Vin = 0
VB=
7.3
V
AM rejection ratio
for .Min = ± 50 kHz, Vin = 500 /-tV,
fAF = 1 kHz, m = 30 %
a'
55 (> 45)
dB
Resistance of potentiometer
for -1 dB output voltage decrease
P
3.7 « 4.7)
kQ
Voltage at pin 5
for -1 dB output voltage decrease
Vs
2.4 « 2.6)
V
Resistance of potentiometer
for -70 dB output voltage decrease
P
1.4 (> 1)
kQ
Voltage at pin 5
for -70 dB output voltage decrease
Vs
1.3
V
dB
Characteristics of Integrated Components
at pins 4, 3, and 12
Operating voltage of Z-diode
at 1Z12 = 5 mA
VZ/2
12
V
(11.2 ... 13.2)
Dynamic differential resistance
rz;
30
Q
Collector emitter breakdown voltage
at 13 = 500 flA
V31l10
> 13
V
DC current gain
at 13 = 1 mA
hFE
>30
Thermal resistance
die to ambient air
RthA
< 120
°C/W
The integrated circuit TBA 120 S is delivered in 4 groups. Depending on
the group a decrease of 30 dB requires a resistor from pin 5 to ground
as indicated in the table below. The No. of the group is printed on the IC.
Group
p
I
I
II
1.9 ... 2.2
I
I
"I
2.1 ... 2.5
I
I
IV
2.4 ... 2.9
8-32
I
I
V
2.8 ... 3.3
TBA120S
INTEGRATED FM/IF
AMPLIFIER AND DEMODULATOR
120
dB
100
+15V
TBA'20S
!
90
+~
AF
.' .
I
.!f.tSQkHz
1:
m.)O'"
'.v"
so
30
/
20
l - t-:'"
O~
,
V
.
-
V
I
O·
.
r---
V
V
"
10
kHz
V",,2V
./
V
dl.t25kHz
For good far-off selectivity the ceramic filter
should be combined with an LC filter.
Frequency
Filter
Resistor R
10.7 MHz
S.SMHz
4.5 MHz
SFC 10.7 MA
SFC 5.5MA
SFC 4.5MA
300 ... 390 Q
560 ... 680 Q
1000 ... 1200 Q,
Fig.4: Internal circuitry
14
I
2
610137
8-33
I
J1--1!
I
-v.
•
0
Fig. 3: AM rejection ratio versus input voltage
Fig. 2': Operating circuit using
a ceramic filter (Murata)
I
m.SO"l.
'",(""kHz
VI/·12V
•'m'
TBA120S
INTEGRATED FM/IF
AMPLIFIER AND DEMODULATOR
Fig. 5:
Fig. 6:
Output level versus
voltage at pin 5
Output levl:ll versus resistance
from pin 5 to ground
dB
o
ft:
12Y
-10 Vi .10mV
f; :s.sMHz
ILff ,:!sOkHz
-20
-30
-GO
-50
-60
~
L
I
o
r
V,/:12Y
-10 Vi :10mY
f; : 5.5MHz
Lff :!sOkHz
-20
/
II
, -'
I
-60
I
-70
I
-80
-90
-90
o
4
3
_RS
-100
Skrl
2
V
o
IS
0.5
2
2.SY
, -Vs
Fig. 7:
AF output voltage
versus supply voltage
2
I
-50
-80
-100
I
II
-GO
II
I
/
-30
/
I
-70
I
TBA 120 5
dB
TBA 120 S
Flg."S:
Distortion factor
versus output level
.,.
TBA 120 S
TBA 120 5
S
VI/=12V
RG =6011
Lff, =! 50kHz
Pin 5 open
V6rms
!
k
4
1\
2
1\
"-
k=3.7%(C=~n'J
k=l7·Io(C=IS nF
/
1
/
I
/
/
1/
/V
~
/
\
X'=18%(C:lnFl22km
~:~.8·/f=lrFl2fkQ
\ rt l 'l.(C:680 pF/L8krl
~ %:1'1.(C:680pF/l8kQ)
10
_VII
0_100
20V
8-34
-so
-GO
-GO
-20
OdB
ITT
-----
ITT3064
TV AUTOMATIC FINE-TUNING CIRCUIT
SEMICONDUCTORS
TV AUTOMATIC FINE-TUNING CIRCUIT
• HIGH SENSITIVITY
• 25kHz MAX. FREQUENCY DEVIATION
ABSOLUTE MAXIMUM RATINGS (Note 1)
• INTERNAL VOLTAGE REGULATOR
Supply Voltage .................... Note 2
Internal Power Dissipation (Note 3). .. 700 mW
Detector Differential Voltage (V,-a) ..... ±10V
Detector Input Voltage Range
(V" V,) ...................... +5V, -6V
I.F. Amp Output (V,) .............. +20V, OV
Bias Voltage (V,) ................. +2V, OV
Storage Temperature Range -65°C to +150°C
Operating Temperature Range -40°C to +85°C
Lead Temperature (soldering,
60 seconds) .............•........ 300°C
• INTERNAL AGC
GENERAL DESCRIPTION-The ITT3064 is a TV
automatic fine-tuning linear integrated circuit
constructed on a single chip. It combines all
of the automatic fine-tuning circuitry, except
transformers, in one integrated circuit. Systems
with low level I.F. amplifiers can now achieve
tuning accuracies of ±25 kHz due to the
ITT3064's high sensitivity. Internal voltage regulation improves overall performance and reduces system cost.
BLOCK DIAGRAM
10kn·3W
,----......,.,.......-_
"'140V
CORRECTION
VOL TAGE
TO VHF AND
UHF TUNERS
5
I
I
I
:,~~~__II__+_---~t__----l
I
IF AMP
~
6
lkl!
I
I
I
_ _________ J
L _______
8(14)
NOTES:
The number without parenthesis is the pin
number for the metal package. The number in
parenthesis is the pin number for the plastic
package.
Metal Package, Pin 9- no connection
Plastic Package, Pins 6, 7, 10, ii, 13
connection
no
1. All voltages reference,d to V
noted.
except as
2. V terminal may be connected to any positive voltage source through a suitable dropping
resistor, provided the dissipation rating is
not exceeded.
3. Derate linearly at 5.6 mW;oC for ambient
temperatures above +25°C.
8-35
ITT3064
TV AUTOMATIC FINE-TUNING CIRCUIT
ELECTRICAL CHARACTERISTICS
(Vcc=-t-30 V, Rs=1.5 kO, TA =25°C unless
otherwise specified)
PARAMETER
Power Consumption
Min.
130
Supply Current - 1
Regulated Supply Voltage - V
Quiescent Operating Voltage -12
Quiescent
Operating Voltages - V., Vo
Output Offset Voltage - (V. -V5)
Input Admittance - Yl1
Reverse Transfer Admittance - Y.2
Forward Transfer Admittance - Y2•
Output Admittance - Y22
Correction Control Voltage V. (Test Circuit 1)
4.0
10.9
1.0
5.0
-1.0
Max.
150
150
150
9.5
12.8
4.0
Units
mW
mW
mW
mA
8.0
6.9
1.0
0
0.41+j1.0
0+j3.4
24.5-j29
0.04+jO.9
V
V
Typ.
140
135
145
6.5
11.8
2.0
85
25
80
35
80
35
CONDITIONS
TA = +25°C
TA = -25°C
TA = +85°C
V = +10.5 V
V
mA
mmho
J.l mho
mmho
mmho
%V+
%V+
%V+
%V+
%V+
%V+
Correction Control Voltage Vo (Test Circuit 1)
f
f
f
f
=
=
=
=
45.75
45.75
45.75
45.75
MHz
MHz
MHz
MHz
V IN = 18 mV RMS
fo = 45.750 MHz
~f as listed (MHz)
-0.030
+0.030
-0.900
+0.900
-1.500
+1.500
V IN = 18 mV RMS
25
85
35
80
35
80
8'-36
%V+
%V+
%V+
%V+
%V+
%V+
fo = 45.750 MHz
At as listed (MHz)
-0.030
+0.030
-0.900
+0.900
-1.500·
+1.500
ITT3064
TV AUTOMATIC FINE-TUNING CIRCUIT
TYPICAL PERFORMANCE CURVES
Narrow- Band Dynamic Control
Voltage Characteristics
I
15
12.l
...........
...... CO~~ECTION CONTROl
10
"\
~
/
l.O
/
~
2.5
o
--
/
15
'A' Z5C
VI \ • lSnv
Vy
/
u
Wide-Band Dynamic Control
Voltage Characteristics
CO~I~ECTl1 COJ~OL
12.l
:::-
REF. A
r- ~Tr-r
10
t:l
<
i5' 01 VIO
~
~
I
7.5
~ S.O
~
2.5
Ii
INPUT FREQUENCY DEVIATION -
o
-2.0
O.OlD
I
/
" " 25'
REF. ofBVIO
-O.OlD -0.020 -0.010 45.150 0.010 0.020
'A' 2l'C
VIN 'limV
REF·illO'Yo
REF. ill."
\
"'-- I----' "-- V
-1.5 -1.0 -0.5 45.150 0.5
I\..
0; VIO
.l
V0
/
1\
l2
1.5
1.0
2.0
INPUT FREQUENCY DEVIATION - MHz
~,Hz
See Test Circuit 1
Test Circuit 1
Correction Voltages
RJ
R6
3kU OOOllJF 10
Rl
15kU
REF. AU-~"""'Mr----o,O:<>--'W''''''''-'''''''Mr---'30V
REF C
REF. 0
~~I!
R3
J
COIL FORM BASE TERMINAL DIAGRAM
r----r-----,
9k!1
REF. B
+---t---t--:*""+-~*7 T
30
1--J.
°r~
60 0 /
2
CONTROL VOLTAGE OUTPUT
NOTE:
1---
Parts placement is critical. Use P.C. board
layout on last page for best results.
connections shown for metal can only
L, is aligned for symmetrical bandwidth on
either side of 45.750 MHz.
L, tertiary winding wound on L, coil form
La is aligned· for zero differential output between terminal·s 4 and 5 at fa
45.750 MHz
=
8-37
TYP.
0
ITT3064
TV AUTOMA TIC FINE-TUNING CIRCUIT
COIL DATA FOR DISCRIMINATOR WINDINGS
L, - Discriminator Primary: 3 1/6 turns; #20,
Enamel-covered wire-close-wound, at bottom
of coil form. Inductance of L,
0.165 fLH;
Qo
120 at fo
45.75 MHz.
Start winding at Terminal #6, finish at Terminal #1. See Notes below.
=
Start winding at Terminal #2; finish at Terminal # 5, connect center tap to Terminal # 7.
See Notes below.
=
=
NOTES:
1. Coil Forms; Cylindrical; 0.30" Dia. max.
L, - Tertiary Windings: 2 1/6 turns; #20 Enamel-covered wire-close wound over bottom
end of L,. Start winding at Terminal #3; finish
at Terminal #4. See notes below.
2. Tuning Core: 0.250" Dia. x 0.37" Length.
:Material: Carbinal J or equivalent.
3. Coil Form Base: See drawing below.
L - Discriminator Secondary: 3 1/2 turns;
center-tapped, space wound at bottom of coil
form. Inductance of L"
0.180fLH; Qo
150
at fo
45.75 MHz.
=
=
4. End of coil nearest terminal board to be designated the winding start end.
=
ITT3064 Equivalent Circuit
IoF. AMP
OUTPUT
,
DETECTOA INPUT
BIAS
2
•
CORRECTION
VOLTAGE
OUTPUT
CORRECT10N
4
5
VOLTAGE
OUTPUT
"s
1000
"6
2 kn
IF AMP ..,---y-____
INPUT
",
Skll
".
9OO!l
V·~.-r--~--~--+---~--~+---~-+--~-------4---------+--+-----~
A9
1.5 kn
8-38
J
DETECTOR
INPUT
ITT
----ITT3065
TV IFM SOUND SYSTEM
SEMICONDUCTORS
TVIFM SOUND SYSTEM
CONNECTION DIAGRAM
(TOP VIEW)
&\ DC Volume Control Eliminates Need For
Shielded Cables
• Excellent AM Rejection
4.5 MHz
• Differential Peak Detector Requires Only One
Single-Tuned Coil
IF INPUT
TONE CONTROL
GND
AUDIO OUTPUT
GND
NC
QUAD DETECTOR
Vt
DC VOLUME
CONTROL
DEEMPHASIS
• Internal Zener Diode Regulated Supply
• Low Harmonic Distortion
QUAD DETECTOR
DETECTOR
OUTPUT
Connection Diagram (Top View)
ABSOLUTE MAXIMUM RATINGS
Unit
Characteristic
AUDIO INPUT
IF INPUT BIAS
SOdB Typical at
Supply Voltage ..................... Note 1
Internal Power Dissipation (Note 2) .... 670mW
Power Supply Current ............... 50 mA
Operating Temperature
Range ................... -40°C to +85°C
Storage Temperature
Range ........... " ..... -65°C to +150 oe
Lead Temperature Range
(Soldering, 60 seconds) .............. 30Qoe
The ITT3065 Monolithic TV/FM Sound System
consists of a Multistage Limiting IF Amplifier,
DC Gain (Volume) control, FM Detector,. and
an Audio Driver constructed in a single silicon
chip using the planar epitaxial process; Excellent sensitivity, high AM rejection and an internally regulated power supply coupled with low
external component requirement makes the
ITT3065 suitable for a wide varity of applications including TV Sound Channels, Line Operated and Automobile FM Radios and Mobile
Communications Equipment.
BLOCK DIAGRAM
DE-EMPHASIS
7
IF INPUT~2+-_...f""
AUDIO
OUTPUT
IF
INPUT BIASe>!-f--v
9 ----10 ---4r--14
GROUND
QUAD
DETECiOR
QUAD
DETECTOR
8-39
GROUND
Aurno
INPUT
13
TONE
CONTROL
ITT~65
TV IFM SOUND SYSTEM
TYPICAL PERFORMANCE CURVES
.. FREQUENCY RESPONSE OF
IF AMPLIFIER SECTION
70
AUDIO GAIN REDUCTION
VERSUS DC VOLUME
, CONTROL RESISTANCE
FREQUENCY RESPONSE OF
AUDIO AMPLIFIER SECTION
1111
IS
r-
J....-
1\
~
\
V
~
TA·25·C
·IIII.V
'''llOmj
IlrSTC:RCt: J
0.1
\
5'-:~:~~
10
0.1
/
1\
-V,~
o
I
O.S
1.0
1.0
S.O
10
0
0.01
1111
0.1
fREQUENCY - MHz
NOTES
TA'I5'C
I.· JOmA
7
I
fI1!QU!OCY ·MH,
10
o
so
T
V
I
10
1111
I1!SrSTAOC['1IOM DC CONTIIOlTO GNU • Kn
V+ terminal may be connected to any positive voltage through a suitable dropping resistor.
provided the dissipation rating is not exceeded.
2 . . Rating applies to ambient temperature ·up to 70'>C. ·Above 70"C ambient derate linearly
8.3 mW/"C for the Ceramic 01 p.
ELECTRICAL CHARACTERISTICS (TA
= 25°C, I
= 30 rnA uoless otherwise specified)
PARAMETER
Conditions
STATIC CHARACTERISTICS
Zener Regulating
Voltage (V.)
Supply Current (I.)
Internal Power
Dissipation
Voltage at IF Input
Vias (VI)
Voltage at DC Volume
Control (Vo)
Voltage at De Emphasis (V,)
Voltage at Quad Detector (V.)
Voltage at Audio Output (V12)
DYNAMIC CHARACTERISTICS
IF AMpLIFIER
Input Limiting Voltage at
-3dS point
AM Rejection
IF Transconductance
,.
Magnitude
Phase Angle
Feedback Capacitance
Input Impedance Components
10.5
10
343
4.0
11.5
16
370
12.5
24
400
rnA
mW
2.0
Volts
4.8
Volts
6.1
3.7
5.1
Volts
Volts
Volts
5.8
,
1
1
Volts
=
VSUPplY
9.0 V
I - 33mA
(fo :- 4.5 MHz, FM±25 KHz
at400 Hz, VIN
100p.V)
=
40
200
50
500
46
~0.02
8-40
400
p.V
dB
AM - 30% at 4.5 MHz
f - 4.5 MHz
mmho
degrees
pF f - 1.0 MHz, Pin 2 to Pin 9
f
4.5 MHz, Pin 1 to Pin 2
=
SGI
ITT3065
TV IFM SOUND SYSTEM
30 mA unless otherwise specified)
ELECTRICAL CHARACTERISTICS (Ti\
Test
Circuit
PARAMETER
Min.
Typ.
Parallel Input Resistance
Parallel Input Capacitance
Output Impedance Components
17
4.0
Parallel Output Resistance
Parallel Output Capacitance
DETECTOR
3.25
75
Recovered AF Voltage
Total Harmonic Distortion
Output Resistance
De emphasis Output
Detector Output
ATTENUATOR
Max. Attenuation
Max. Play-through Voltage'
AUDIO AMPLIFIER
Voltage Gain
Total Harmonic Distortion
Undistorted Output Voltage
Input Resistance
Output Resistance
Max.
Units
Conditions
kU
pF
f - 4.5 MHz,
Pin 9 to Ground
kn
pF
(fo - 4.5 MHz,
FM
±25kHz
at 400 Hz, VIN
=
0.5
1
1
0.75
0.9
2.0
%
kn
n
7.5
300
1
1
60
2
2
2
17.5
80
0.075 1.0
20
1.5
2.0
2.5
70
270
= 100 mV)
Vrms
= co
dB
mV
Rx
Rx --
dB
0.1 Vrms, f
400 Hz
Vi
400Hz
Vo
2 Vrms, f
400Hz
THO
5% f
f -- 400Hz
f
400Hz
%
Vrms
kn
n
co
=
=
=
=
=
=
=
'Play-through voltage is the unwanted signal, measured at the detector output, when the volume control is set for minimum output.
Input limiting voltage, AM rejection, recovered
audio, total harmonic distortion, maximum attenuation, maximum "play-through" test circuit.
AUDIO VOLTAGE GAIN
(UNDISTORTED OUTPUT)
Vee
30d,
RS
O.05r-
I'F:}
A
S,
DISTORTION
ANALYZER
( HEWLETrPACKARD·
TYPE 3:10
OR
EQUIVALENTI
:;
~)
UNlvERTER
(BOONTON
TYPE 207H
OR EQUIVALENT!
A"'-f'"
GEI'f
(BOONTON
TYPE. 202H
OR
0.47
II'F
aUlvALENTI
DISTORTION
ANALYZER
(HEWLETTPACKARD
TYPE 330
OR
EQUIVALENT!
PINS., 1.12,13.14 NO CONNECTION
*L I
= 16~H
PINS 7. 8,11.13 NO CONNECTION
NOMINAL.
Q(UNLOADED) = 50
TEST CIRCUIT 2
TEST CIRCUIT 1
8-41
ITT3065
TV IFM SOUNDSYSTEM
IF AMPLIFIER SECTION
AUDIO AMPLIFIER SECTION
EIN = 100llVrms
EIN = 100 mV
TEST CIRCUIT 3
TEST CIRCUIT 4
TYPICAL APPLICATION
TV SOUND SYSTEM
8-42
ITT
-----
TDA1330
LOW-LEVEL VIDEO DETECTOR
SEMICONDUCTORS
LOW-LEVEL VIDEO DETECTOR
The TDA1330 is a monolithic integrated circuit
designed for use in both colour and monochrome television receivers. It is designed to
replace the third IF stage, the detector, the
video buffer and the AFC buffer. An important
feature is the extremely linear video characteristics and wide band width.
'~
J:.~5~ ~
..-7,62--...
8
Absolute Maximum Ratings
Vs
Is
VI
Ptot
Tamb
Ts
Supply voltage ...........•.... 24V
Supply current ...........•.. 26mA
Input voltage (rms) ...........• 1.0V
Total power dissipation
(see note) with
Tamb = 25°C ............ 625 mW
Operating temperature
range ................ 0 to 75°C
Storage temperature
range ............ -65 to 150°C
7
6
5
1Cn
~.
.1
2
3
4
FIG. 1
TDA1330 in the mini Dual-in-Iine plastic package similar to TO-116 •.
NOTE
Derate above Ta mb=25°C at 5.0mW/"C
ELECTRICAL CHARACTERISTICS
With Vs =20V, Q=30, f c =45MHz, Tamb=25°C
in the test circuit shown in FIG. 3 (unless
otherwise stated)
Vs
Is
Vo
Vo
VI
Vo
Supply voltage range .... 20 (12-24)V
Supply current ...... 15 (20 max)mA
Quiescent Ol~tput voltage 7.7 (6.8-8.3)V
Maximum signal output voltage .. OV
Input signal voltage for
3.0V pk-pk, Video output
(90 % modulation) rms 36 (25-65)mV
Maximum output voltage swing
pk-pk ..................•.. 7.7V
Carrier rejection at
output ............ 60 (40 min)db
RI
CI
Ro
Rs
Cs
8-43
Carrier output voltage (at
3.0V pk-pk output) rms
fout=fc ••••••••••••••••••• 1.0mV
fout=2fc ••••••••••••••••• 3.0mV
3db Band width of IF carrier .• 80MHz
3dB Band width of
video output . . . . . . . . . . .. 12.3MHz
Input resistance .... 3.5 (2.4-4.0)KO
Input capacitance ...•......• 3.0pF
Output resistance ............ 180{)
Internal resistance .;........ 4.4KO
Internal capacitance ......... 1.0pF
Carrier buffer output at carrier
frequency (pk-pk) .. ~ ...... 350mV
Carrier buffer level .....••.... 6.5V
TDA1330
LOW~LEVEL VIDEO
DETECTOR
. TUNED CIRCUIT
I CARRIE
·....----+-0 ~~~~~;
>----l--t---,
::PUT C7
4
8.
2.5k
u.
+-4_-~_-----~-~~~--_6----~~~~4_--~~~~_oGND
FIG. 2 Internal Circuitry
V
8.0
t"-....
AUXILIARY OUTPUT
20V[~J
TDA· 1330
10V
----
'"e
6.0
4.0
0-
:::>
D-
'"
o-
"" r-....
-........
r----.... .......
--
r-----. r--..
:::>
3
2
0
4
CARRIER
OUTPUT
~
PRIMARY OUTPUT
2.0
o
3.3k
6.8k
1
f'45MHz
(unmodulat.~)
_
Vs' 20Vdc
~
~
g
I
~ ......
~
r---. :---....
15Vdc
I::::::
t::---
I~
I""-
~
I::'---. i"""" ~
.......
I
o
40
20
60
b
100
mV
80
Vi INPUT VOLTAGE (rms)
FIGURE 3- TEST CIRCUIT
FIGURE
V 8.0
./
'"...
e.
6.0
~
V
g
4.0
V
0-
:::>
D-
o-
:::>
0
g
~
2.0
./ ~
V
./
/
V
4 - OUTPUT VOLTAGE
V
VI '0
V
Vs' 20V
900/0 MOD
fM'lkHz
fe' 45 MHz
Q'30
l/
--""
~VI=40mV
~
"'"
V
~
L
L
lL
/'
o
8.0
10
12
14
16
18
20
22
24
10
5-
30
40
50
60
70
80
V INPUT CARRIER LEVEL (rma)
Vs SUPPLY VOLTAGE
FIGURE
20
OUTPUT VOLTAGE
. FIGURE
8-44
6- DETECTOR LINEARITY
90 100
mV
TDA1330
LOW-LEVEL VIDEO DETECTOR
V
dB
+6.0
~4.0
z
+4.0
-
+2.0
o
-2.0
'">~
~
0.1-
,/
........
-4.0
-6.0
-8.0
i
'-
\.
r\
4.0
6.0
f-
~ ~2.0
Vi ' 40mV
I--- Q'30
0
Il.
::!E
~
90% MOD
--
<11.0
5~
8.0
10
12
14
~I-
~
5
16
MHz
OUTPUT AMPLITUDE
1M ' I kHz
I- :I:
\
2.0
r- Vs '20Vdc
'" is
§
--
r--I-
~ ~
\
-10
o
g3.0
U>
_
IC' 45 MHz
Vi' 40mV
70% MOD
VS' 20 Vdc
Q';IO I
oJ
~
:;9
%DISTORTION
-'
0
25
30
35
I M MODULATING FREQUENCY
40
IC
45
50
55
60
65
MHz
'CARRIER FREQUENCY
FIGURE 8 - CARRIE R FREQUENCY PERFORMANCE
FIGURE 7- VIDEO FREQUENCY RES PONCE
Vs
r---~~------~----~ 12V
AGC
TO TUNER
----C3
Vs
IBV
IBV[~l
~O.IPF
3.9k
220
10V
3.3k
6
22
12pF
FLYBACK WINDING
AUXILIARY
~-+-----I---O VIDEO
OUTPUT
5
7
68pF
TDA 1352
"J
- - __
3.9k
4
PRIMARY VIDEO
AND
SOUND OUTPUT
TDA 1330
B
-B.OV PULSE
FIG. 9 Typical Application of TDA1330
General Information
Linear detection is simplified with the TDA1330
as it can be carried out at lower power signal
levels than previously possible. It offers considerable advantages to the designer some of
which are listed below:
1. As FIG. 4 shows, the linearity of output voltage is excellent. It can also be seen that as
the slopes are parallel the -video amplitude will
not change with supply voltage variations.
2. The output level is a linear function of
supply voltage and corrections for this can be
achieved by regulation of the supply or referring to the video amplifier supply.
3. A video output with positive-going sync is
provided but it should be used with care due to
its higher output impedance. When it is not
used the output should be connected to the
supply.
4. A carrier buffer output is provided giving
350mV, sufficient to drive a ratio detector with
one additional stage.
8-45
I mm _____
_-IL-IL
TDA1352
T_V_V_ID_E_O_IF_A_M_P_L_IF_IE_R_W_IT_H_G_A_T_E_D_A_G
__
C
SEMICONDUCTORS
TV VIDEO IFAMPLIFIER
WITH GATED AGe
1
.075
The TDA:1"3"52 is a monolithic integrated circuit
designed for use in either colour or monochrome TV receivers. It consists of an IF amplifier with gated wide-range AGC and is designed to replace the 1st and 2nd IF stages. A
single supply of 12V is required for the device
and a feature is the power gain of 52dB (typical) at 45MHz. Exhibiting extremely low reverse-transfer admittance, the device has nearly
constant input and output admittance over the
entire AGC range. A control signal for delayed
AGC of the tuner is available from an output.
Normally the TDA1352 is delivered in a dualin-line plastic package TO-116 (FIG. 1). Upon
special request it is also available in the quadin-line plastic package (FIG. 2).
.043
0.60
~_J__ J
-l0.,57h
MAX
0.75
FIG. 1
TDA1352A in dual-in-line plastic TO-116 package.
ABSOLUTE MAXIMUM RATINGS
Vs
Vos
Vi
V age
Vgv
Pto ,
Tamb
Ts
Supply Voltage ............... 18V
Output supply voltage ......... 18V
Input voltage (pk-pk) .:........ 10V
AGC input voltage ............ 6V
Gating voltage .......... +10, -20V
Total power dissipation ...... 625mW
(see note 1)
Operating temperature ..... 0 to 75°C
Storage temperature ... - 55 to 150°C
r
.- 0
._.
:l
::r
~
1
1
If
0.75
J:
.J:.
~D
ELECTRICAL CHARACTERISTICS
1 o
TO.
0.0
1_
t
.075
Vs=12V Tamb =25°C unless otherwise stated
Typ.
AGC Range ......................... 75dB
Power Gain
f=35 or 45MHz ............ 52 (46 min)dB
f=58MHz ........ : ................ 50dB
Voltage range for RF-AGC (pk-pk)
Maximum .......................... 7.0V
Minimum .......................... 0.2V
FIG. 2
TDA1352B in quad-in-line plastic package.
8-46
TDA1352
TV VIDEO AMPLIFIER WITH GATEDAGC
T2 is further amplified and the RF-AGC voltage
varies (positive-going) due to the change in
DC levels. Input impedance is independent of
AGC action as the input amplifiers operate at
constant emitter currents. Single-ended or differential inputs may be applied. The IF input
may be transformer driver, but no DC path to
ground is allowed on either terminal.
ELECTRICAL CHARACTERISTICS (continued)
Maximum differential output
voltage swing (pk-pk)
OdS AGC ....................... 16.8V
-30dS AGC ..................... 8.4V
IF gain change over RF-AGC range .... , 10dS
Output current ..................... 5.7mA
Supply current ...................... 27mA
Power dissipation ................... 325mW
Increased voltage on the bases of T4 and T5
causing AGC action as the transistors conduct
more heavily thereby shunting the original current from the interstage amplifiers (T6 and T7).
Output admittance is nearly constant as the
output amplifiers are constant current fed
(maintaining a constant quiescent bias).
General Information
For correct operation of the AGC section of
the TDA1352, a gating pulse, a reference level,
and a composite video signal must be supplied.
A voltage is maintained across the external
capacitor C2 (see FIG. 3) by the gating section, which is dependent on the video level and
DC reference setting. This voltage results from
the charge passed by D1 and the charges
drained by T1 during the gating pulse; the
magnitude of the charge passed is dependent
on the relative amplitude of the video signal
to reference level. The voltage passes through
the IF-AGC amplifier and is applied to the
RF-AGC amplifier where it is compared to the
fixed RF-AGC delay voltage by the differential
amplifier formed by T2 and T3. The output of
The supply must have a low' AC impedance to
prevent low-frequency instability in the RF-AGC
loop.
A balance between AGC stability and recovery
speed has to be achieved in choosing values
for C1, C2 and C3 (typical values 0.1 fLF, 0.25,u.F
and 10fLF respectively). For receiver alignment
a fixed IF-AGC operating point can be set by
connecting a 22Ko resistor across pins 9 and
11 (minimum gain), and pin 14 biased by means
of a 10KO variable resistor to ground.
DESIGN PARAMETERS
Typical values at Vs
= 12V, Tamb
= 25°C
f=35MHz
Single-ended input admittance ..............
0.55
2.25
Input admittance change with AGC .........
50
(0 to 60dS) ............................
0
Differential output admittance ...............
20
430
Output admittance change with AGC ........
3.0
(0 to 60dS) ............................
80
Reverse transfer admittance ................ < <1.0
Forward transfer admittance
magnitude ............................. .
260
Angle (OdS AGC) ...................... .
-73
Angle (-30dS AGC) .................. ..
-52
Single-ended input capacitance ............ .
9.5
Differential output capacitance ............. .
2.0
_Notes 1. Derate above Tamb = 25 ° C at 5mW;o C
8-47
f=45MHz
f=58MHz
Units
0.70
2.80
60
1.1
3.75
m mhos
fL mhos
o
40
570
4.0
100
«1.0
«1.0
fL mhos
240
-100
210
-135
m mhos
degrees
-72
10
2.0
75
780
fL mhos
fL mhos
-96
10.5
2.5
pf
pf
TDA1352
TV VIDEO IF AMPLIFIER WITH GATED AGe
'Ase S'RlRAGE CAfIIIC.J (IF .te PU'ERI
r1--,---'~~~--r--~~---~"~c~i~---~~--'----r~r-'-r----------------'--T7~1r---r'---~~
OUTPUT
SUPPLY'f'Ol.TAG'E
'1"
o
r----:---if--O
L_
T.Sk
I
.
"'FOUTPU'T
t_~
:
I ,
RE~~C:{'O
DCINPtITS
~,
.,0---_\--+----'
FIG. 3 Internal Circuit
L
I--V
L
v "l\.
'\
t'--,.t
f'
"'-..
-........
Scol8' I MH Z!cm
FIG. 5 Response Curve (45 & 58 MK2)
'G.;:.C...,.,,,,,~_..-J
80V
Video
Pola.-ity
Pin6
VoltoQe
::'1L
N·aoll....
TUNER AGe OUTPUT
FIG. 4
Test Circuit
Pin 10
Vo1t01jl1
Goln9
S,nc.
Adj.
..
Adj.I.O 'QVdc
NOlll4.5 Y
FIG. 6
toO ••OVdc:
No.2.0y
0 ____
Politi"
,",
Sync.
Pin 5
RI In}
. OJl
0-·______
~.91t
AGC Operation'
.-----r--------t----~V.
ozv
:~NCER· ....----f----\-----,
-co
TO
J
•..
AF AGe
VS
O'V[:I\:]
I8v
~o.lP.F
.. 0
lOY
• .oK
AGe INPUT
-
---
AUXIUAIIY
.....-+--f-.. OUTPUT
VIDEO
PR'MUY VIDEO
ANO
'.7
SOUND OUTPUT
•
carrier
s....
FL't'BAClC WINDING
··8.0Y PULSE
8-48
OUTPUT
FIG. 7
Typical Application
·TDA1352
TV VIDEO AMPLIFIER WITH GA TED AGe
FIGURE 8 -SINGLE ENDED INPUT ADMITTANCE
5.0
FIGURE 9 - DIFFERENTIAL OUTPtlT ADMITTANCE
1.0
II
/
4.0
(SINGl.E~NDED OUTPUT
V
ADIlITTANCE EXHIBITS
TWICE THESE VALUES)
0.8
/
.I
bll
3.0
2.0
1.0
,/
~
L.
911
....... V
o
20
10
30
40
70
50
!--
o
100
MHz
FREQUENCY
-
.,., V
0.2
~
~
/
0.4
/
I-"'"
~2~
0.6
/
10
-
922
20
30
40
V
I--
70
50
100
MHz
FREQUENCY
FIG. 11
22
"0
5
t-..t:HI-1tt-t-tt-t-tt----1_+-i--I 5.0
'"
~
iL
r--t1HHH-1Hf--l--H---r-+--f-~ 3.0
~
2.0
IFGAIN REDUCTION
1.0
I
I
~
I
55
6.0
6.5
7.0
7.5
10
v
/
./
./
V
I}
L
f=35I1Hz .. 4511Hz
"/
o
30
20
10
40
dB
AGC GAIN REOUCTION
FIG. 13
II
~
400
>
o
"
~da GAIN
IIAX~ "
-20
-60
1\
200
-80
o
50
10
FREQUENCY
20
60
7.0
'"
~
6.0
~ 5.0
-100
~
-120
1\
"
"
-160
I
5.0
-180
'"
1.0
-200
100
MHz
!;;
Q
I\,
4.0
IS
-140
100
8.0
-40
REDUCTION
1'\"
2D
/
L ....... ..........
L L
12
FIG.~2
1.0
-'
14
6.0
8.0 8.5
AGC INPUT VOLTAGE
f=5811~
16
8.0
o
5.0
20
18
r--r~~~~t-t-t+--r--r--1_~4.o
t--HI-II-I-Hr-~'V--t--t-t-TUNER AGe DELAY
1/
III
r-"~~J"-'1-'-'-'''8D
I-~..-'r-+-r""r.,.l--~+-I--i 7.0
> > > > TUNER
~. ~ ~
AGC
- t - 6.0
..........
VOl
:::I
..........
V..
= 12V
2.0
0
o
10
20
30
40
GAIN REDUCTION
8-49
14V
50
60
70
dB
60
ITT3701
_ITT ______
2_W_A_T_T_T_V_S_O....
U_N....,D=S""""Y""""S"""'T.....
EM
....
SEMICONDUCTORS
2 WATT TV
SOUND SYSTEM
• Monolithic 2 watt sound channel
Fig. 1- 14-Lead Plastic Dual-In-Line
• Minimum external components
.310
• 24 volt operation
.290
.Short circuit protection
• Low thermal resistance power package
LEADS TO BE TIN PLATED
; .200
020 MI",
The ITT3701 is a monolithic integrated circuit
which uses a minimum of external components
to provide the complete sound function of a TV
receiver. Current designs require either two
integrated circuits or one integrated circuit and
a discrete power transistor to perform the
functions incorporated in the ITT3701. The
functional block diagram and the required
external components are shown in Fig.:3.
. 15:TYp.Ll,
MAX .
I.......
Jl~~.='
I'
'I
.375
NOM.
11
14
The integrated circuit includes: a high gain
limiter - IF amplifier, a quadrature type FM
detector, a DC operated volume contrpl, and an
internally compensated 2 watt audio amplifier.
8
The ITT3701 is supplied in a modified 14 lead
dual in line package with an integral heat sink
bracket. (See figure 2.) The device will operate
satisfactorily at an ambient temperature of 60°
C with worst case program material when the
device leads and heat sink bracket are soldered
into a suitably designed printed circuit board.
For more severe operating conditions, tapped
holes are provided to permit easy addition of
extra radiators.
Fig. 2- 14-Lead Plastic Package
With Heat Sink Bracket
"i--
:'
V9
_.J l . - -,'
\
.4It.01
·~_~u
Maximum Ratings:
I"
I,
-
-~ - I
The ITT3701 will also be supplied without the
healtl sink bracket for those applications
requiring a different heat sink configuration.
Figure 1 shows the 3701 without the bracket
and illustrates the tinned mounting surface
available for heat sink attachment. (Note 3).
Supply Voltage
Supply Current
Output Current
:,:: 1
.'~
28 volts
50 ma
750ma
8-50
1113701
2 WATT TV SOUND SYSTEM
ELECTRICAL CHARACTERISTICS:
POWER DISSIPATION:
Test Conditions: Circuit Fig. 6
Supply Voltage = 24 volts
Input at Pin 13= 100mv rms, = 4.5 MHz,
Modulation ± 25 KHz at frequency of 400Hz.
With heat sink bracketa) Case temperature (Tc)
85°C (note 1) ................... 4 watts
b) Ambient temperature (Ta)
25 ° C (note 2) ................... 2 watts
derate at 16.7mw'oC for Ta= 25°C
I.F. Section
Quiescent current (Ill)
(Vll 11.0v) .............. 15ma typical
Zener voltage
(l l l }=25ma) ............ 12 volts typical
Limitting sensitivity
(-3dS) {Fig. 4} ......... 100 P.v maximum
Recovered audio (v.) ........ 700mv±3dS
Total harmonic distortion
(±25kHz deviation) ....... 1.5 % maximum
A.M. rejection (A.M. modulation
30% 500 pV:::;;V,3:::;;100mv) . .40dS minimum
Volume control attenuation
(V3=0) ................. 60dS minimum
Volume control characteristic:
Log (V3) (FIG. 5)
vout
=
Without heat sink bracketa) Case temperature (Tc)
85° C (note 1) .. , ................ 4 watts
b) Ambient temperature (Ta)
25°C ........................ 1.25 watts
derate at 10mw'oC for Ta= 25°C
Storage Temperature
Range ................. -40 to + 150° C
Operating Temperature
Range .................. -40to +85°C
Note 1: .Measured at the center of the heat sink bracket
directly above the device or at the center of the
mounting surface.
cr
Note 2: Operating with no extra external radiator and with
heat sink bracket in free air (not soldered Into PC
board).
Audio Section:
Test conditions,: Circuit Fig. 7
Audio input frequency = 400Hz
Quiescent current (Ig)
(Vg = + 24v, v = OJ: .......... 15ma typical
Power output (Total harmonic
distortion = 5%) ... " .... 2 watt minimum
Total harmonic distortion
(Pout = 1 watt) ........... 0.5% maximum
Voltage gain (Note 41 .....•... 30dS ± 1.5dS
Hum rejection ............. 30ds minimum
input resistance ............ 40K minimum
Note 3: Extreme care must be used when affixing heat sink
to the' mounting surface of the 3701. The preferred
method is by the use of a thermally conductive
epoxy cement. An alternative method is by use of a
low temperature solder preform. When using this
method do not permit the temperature of the device
mounting surface to exceed 150· C.
Note 4: To give nominal.overdrive capability of 12 dB at
100% modulation.
'.P~t)i
FRO"
SOUND
DETECTOR
_
Fig. 3
Typical Applications
L=ISp.H
Qo=Z8
8-51
•
ITT3701
2 WAn TV SOUND SYSTEM
Fig. 4
RELATIVE OUTPUT AND 5tNIN RATIO
IIII
o
-10
-20
II I
RELATIVE OUTPUT
)1
(
dB -.30
! '
-40
'
OVERALL NOISE
(VOLUME CONTROL FOR VOUT= I~)
-50
-60
,
/
........
...........
IIIII
DETECTOR NOISE
100
10
10K
1000
SIGNAL INPUT (jJv)
Fig. 5
o
-10
VOLUME CONTROL
VOLUME CONTROL
25 Kn LINEAR
-Te= 25·C
---- Te '" 70·C
L/
~
~
//
V'"
-20
",
/
-30
/
dB
-40
,/
-50
-60
./'
-70
..........'
o
...... /
'7
//
V
20
40
60
% ROTATION (C.W.J
8:-52
80
100
ITT3701
2 WATT TV SOUND SYSTEM
FIG. 6
I. F. Test Circuit
.IIL!
HP3406A
I
-=FIG. 7
Audio Test Circuit
.1
+IO°1z5VW
ILl
-=-=-
8-53
_
I
ITT SAJ110
STAGE
FREQUENCY
DIVIDER
-L-L _SEVEN
_
_
_
_
mm
SEMICONDUCTORS
~~0.75-----+l·1
SEVEN STAGE
FREQUENCY DIVIDER
~-:-~H~~l!
Monolithic integrated circuit in bipolar technique, designed primarily for use in electronic
organs. The device incorporates seven flipflops with externally accessible inputs and outputs.
1234567
Each flip-flop changes state on application of a
positive-going input pulse. The individual flipflops can be interconnected to form a divider
chain. Two flip-flop pairs are already internally
series-connected as shown in Fig. 2.
-
~
An emitter-follower is interposed between each
flip-flop and the associated output terminal to
ensure that the output voltage is largely independent of load. Because no internal emitter
resistors are provided, the emitter-follower delivers undirectional output currents.
When used in electronic organs the frequency
divider SAJ110 may be driven by sine-wave as
well as square-wave signals. The shape of the
square-wave output signal can be modified by
connection of RC filters.
If, by means of an appropriate circuit, all inputs and outputs are brought to a potential
below 1.5 volts for a short time, all outputs
remain in the low state.
Fig. 2: Block Diagram
L.--
14
All voltages are referred to terminal 1.
Normally, the SAJ110 is delivered in the dualin-line plastic package TO-116 (Fig. 1a, add
suffix "A" to type No.). Upon special request
it is also available in the quad-in-line package
(Fig. 1b, add suffix "B" to type No.).
12
0.60----+-1
fO
SAJ110-B
Fig. 1
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
V,
Supply voltage .............. 11 V
Input voltage see Fig. 4
10
Output current per stage .... 5 rnA *
Vext
External voltage at output
terminals .................... ±5V
Tamb
Ambient temperature
range .............. -10 to +60°C
Ts
Storage temperature
range ............ -30 to +125°C
CHARACTERISTICS PER DIVIDER STAGE
9 V, RL
2.2 kn, Tomb
25°C
atV,
Characteristic
Unit
Supply current (low state
at output) ................ <3 rnA
Vi
Input voltage high state
(see Fig. 4) .............. 6 to 9 V
Vi
Input voltage low state ....... <1 V
Vo
Output voltage low state .... <0.1 V
Vo
Output voltage high state ... >7.0 V
tr
Rise time of output voltage .. <0.2 us
tf
Fall time of output voltage .. <0.2 us
ri
Input resistance (see Fig. !5) 6 to 9 kn
=
The figures in brackets correspond to the pin
numbers.
SAJ110-A
8-54
=
=
ITT SAJ110
SEVEN STAGE FREQUENCY DIVIDER
CHARACTERISTICS PER DIVIDER STAGE
at V,=g V, RL=2.2 kn, Tamb =25°C
ro
ro
Output resistance low state ..
Output resistance high state "
v
5AJ1I0
v
SAJ
" Taj:25-C
Rl ,2,2kC'l
ToM'IlI:0 25
10
10
,/'
V~
200 n
Fig. 4 - Max.
admissible arid' min.
required value of
input pulses (high
state) versus supply
voltage.
Fig. 3 - Output
voltage versus
supply voltage.
"
> 1 Mn
Recommended Operating Conditions
V,
Supply voltage ................ 9 V
Max input frequency ........ 50 kHz
f imax
Load resistance ........ 2 to 20 kn
/" ./"
/"
mall.adm~
I;Y
V
>'"
Fig. 5 - Input
characteristic
no
"'"2.0
'.'
~
SAJ 110
1,1,6
4
I'·'
10
11V
9
10
o
\IV
I
:f' , .
I
t
0.'
0.'
--1\
,
.............
I
'.0
/
0.2
9
.,,"V.trIlO'(W-H"C
1~
,)
""'-
..
.
....
c...",,25ec
0.'
--v,
Fig. 6 - Output
characteristic
II
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.
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lOY
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1_.-.
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•
••
ITT SAJ110 IN FREQUENCY DIVIDER CIRCUITS
Introduction
Integrated digital frequency dividers have for
long been widely used in professional digital
equipment but have so far found little application in the entertainment sector of the electronic
industry. This, no doubt, is due to the fact that
the devices presently available do not quite
meet the specific requirements of the consumer
market, and that they were, until recently,
rather expensive. Advances in integration techniques have now made it possible to produce
inexpensive linear, as well as digital integrated
circuits which should be of special interest to
the electronic consumer industry. These devices offer many advantages when compared
with circuits employing dicrete components
and are in many instances already cheaper.
It is certain that the availability of these new
integrated circuits will lead to rapid new developments in all branches of the electronic
industry.
The new monolithic integrated frequency divider circuit SAJ110, developed by ITT Semiconductors, incorporates seven divider stages
which can be used either individually or interconnected to form a divider chain. Because
the SAJ110 requires no additional components
and can be used in place of conventional discrete-component flipflop dividers, its use as a
frequency divider in electronic organs is particularly advantageous.
The Integrated Circuit SAJ110
Integration of a conventional flipflop circuit
would offer virtually no advantage over a discrete component circuit - only a circuit which
does not incorporate capacitors or other
charge-storing elements is suitable for integration. Because the master slave flipflop (a frequency divider often used in digital equipment)
'is far too complex for consumer applications,
8-55
ITT SAJ110
FREQUENCY DIVIDER CIRCUITS
development of a new circuit was necessary.
This circuit had to function in a similar manner to a conventional flipflop but had to be
designed so that no additional charge-storing
elements were required. The result is a device
which combines seven single divider stages
on a single chip.
r----
- - - - - S A J 110-- - - -
-
-
--,
:rEhB rEhEh rB 8
~ =--1 =--i
(2)
8 :
-1-=-1-= 1- F~ 1-F~1-1-=-=-H f
(14)
(13)
(3)
(12)
0,
02
'3
03
{4}
(10):,(51
04 '5
05 '6
(II)
(9)
16)
06 '7
07:8)(1)(7)
"*
v·
Fig. 7 - SAJ110 Block diagram - The figures
in brackets are the same as the pin numbers
of package.
Performance Requirement Summary for the
Integrated Frequency Divider SAJ110
The integrated frequency divider had to meet
the following customer requirements:
Supply voltage .................... 7 - 11 V
Input (trigger
waveforms) ........ Sinusoid or square wave
Output voltage ......... Not less than 6V high enough to permit reliable
triggering of another divider
stage under all operating conditions.
Permissible load range ........ 2k to 100kn
Ambient operating
temperature range .............. 0° to 60°C
Number of stages to be accommodated
in one package ......................... 7
Packaging
14-pin DIP or OIL plastic package
In order to make maximum use of the 14 connections available on a TO-116 package the
pins are connected as shown in Fig. 1, being
arranged so that access to two divider pairs
and three single divider stages is possible. The
circuits can thus be used either singly or interconnected in various combinations.
Output stag.
1"0
D 0
I,
Functional Description of an SAJ110
Divider Stage
Each stage used in the SAJ110 comprises
basically a trigger network, two transistors
connected as a flipflop, and an output stage
(Fig. B). The input is first applied to a trigger
network which always steers the input pulse
to that transistor which is cut off at the time.
Fig. 8 shows the input and output waveforms
produced by one such stage. Each positive
edge of the input waveform causes the flipflop
to change state so that frequency division by
two results. The flipflop output is fed to a
transistor connected as an emitter follower output stage, this being provided to .isolate the
flipflop from an external load and to supply
output pulses of constant amplitude. The output pin is connected to the emitter of this
transistor.
Flip-flop
Trigger
I
I
I
I
I
1
I
I
-'I'
t:I I: :i---I-
.1
_t
Fig. 8 - Block diagram of one divider stage
with input and output waveforms
For reason of economy and reliability, it was
also considered desirable that the number of
integrated elements and the total resistance
of all the resistors used in the IC should be
kept to a minimum.
8-56
ITT SAJ110
FREQUENCY DIVIDER CIRCUITS
However, if the SAJ110 is used, simple RC
networks can be connected across the outputs
to generate sawtooth waveforms which contain even harmonics. An additional advantage
of the SAJ110 is its small size, making it particularly suitable for use in portable instruments.
The curves shown in Figs. 3 to 6 illustrate the
performance of the divider in more detail.
The input parameters of a frequency divider
stage at various supply voltages can be deduced from Figs. 3 and 4. The input pulse
amplitude should be not less than 6V, but
should, on the other hand, not exceed the
supply voltage. The curves in Fig. 3· give the
maximum permissible input pulse amplitude
range as a function of supply voltage. The
input corresponding to "low" level should be
less than 1\'/. Fig. 4 may be used to determine
the static input resistance, which varies between 6 and 9kO.
In the curve shown in Fig. 5 the output voltage
is plotted as a function of supply voltage. As
can be seen, the output voltage is 1 to 1.5V
lower than the supply voltage and varies somewhat with the ioad. Assuming the same loading conditions the output voltages of all individual stages are within ±5"1o - this applies
to stages on the same IC as well as to stages
on different IC's.
Fig. 6 shows the loading characteristic of a
divider stage which gives a "high" output.
Note that as the output current of the stage
is increased (by reducing the load resistor,
for example), point "8" on the curve
moves towards "c" (lout
35 mA and
V"ut
1.7V) at which point the stage flips into
the "low" state and remains there. This bistable output effect is discussed further on in
connection with the resetting of dividers used
in counting circuits.
=
=
Applications for the SAJ110
Use in Electronic Organs
The heart of modern eiectronic organs is
usually a set of LC master oscillators tuned
to the frequencies of the highest octave. The
frequencies of the lower octaves are then derived from these master oscillators by frequency division. In most conventional organs
this frequency division is accomplished by the
use of bistable multivibrators (flip-flops). These
have the disadvantage of producing a square
wave output, which contains practically no
even harmonics and offers only limited scope
for modifying the character of the notes
produced.
Fig. 9 shows the usual frequency generating
circuits employed in electronic organs. Twelve
master oscillators produce the frequencies of
the highest octave while all the frequencies
for the lower octaves are generated by frequency division. The arrangement shown in
Fig. 9 requires up to twelve SAJ110 circuits
for one organ. If the organ has less than seven
octaves. then there are several spare divider
stages which may ·be utilized in the divider
chains associated with other frequencies so
that in this case less than 12 integrated circuits are required:
Depression of one of the organ keys, T, causes
several outputs to be switched to a common
line, S, via high value resistors, R, and this
signal, which is a· combination of several frequencies, is then further processed. The spectrum of this signal is considerably richer in
harmonics than that of an ordinary square
wave.
It is an advantage to give a signal to the following filters the mean value of which does
little change when the organ keys are pressed.
In order to obtain this, the ground of resistor
R/10 (Fig. 9) should be connected to a positive potential. Another possibility is to ensure
that the divider outputs supply proper AC
signals. Fig.10 shows such ari alternative circuit. Use of a suitable bias causes the full
alternating divider output component to be developed across the load RL •
The circuit shown in Fig. 11 fully exploits
the high output voltage and low output resistance of the frequency divider SAJ110. In this
circuit RC networks are connected, via protection diodes, to the outputs of individual
divider stages so that waveforms which are
not very different from that of an ideal sawtooth are presented across· the load RL • The
protective resistor As connected in series with
each capacitor CL is included to limit the
capacitor surge toa value which the output
stage can safely handle.
8-57
I
I
ITT SAJ110
FREQUENCY DIVIDER CIRCUITS
.
:
0
In Fig. 12 the frequency spectrum of the waveform VRL is compared with that of two sawtooth waveforms, and it can be seen that the
spectrum attained with the circuit arrangement
of Fig. 10 approaches that of an ideal sawtooth.
Note that the sub-harmonic component is extremely small - much smaller than is necessary for this application.
., ,
.
, ,
,, ,, ,,,
,
-'0
1-
,
:
20
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-30
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-5 0
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i, ,I ,
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,, ,
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'0
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14
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16
-,-to
I
18
c ___ ~
Fig. 12 -Frequency spectrum associated with
various waveforms
Use of the SAJ110 in Counting Circuits
Fig. 9-Block diagram of the tone generating
circuits in electronic organs
r -- SAJ
I~I
110---~--
Output
IL ____ . ____
VOU!
_
Vf~'
f.;,
The output of a divider stage can change state
only while its input is positive going.
__ I
The frequency divider SAJ110, unlike a master
slave flipflop, does not possess a buffer stage
between input and output, nor a special reset
input.
0 ...0,5 V
Fig. 10-Conversion of divider undirectional output into alternating output
a)
Use of the SAJ110 in a counting circuit raises
the problem of how to reset the flipflops. With
the SAJ11 0 it is possible to reset a single stage
as well as several stages connected in a
counting chain. However, when designing a
suitable reset circuit the following features of
the device must be taken into account:
Rs
It is, however, possible to use th,e inputs and
outputs for reset purpose. Because the reset
capability of an SAJ110 stage depends on its
input state, it is necessary to use both the
input and the output terminals for reset purpose.
C,
Output Characteristic
Fig. 11-Modification of the divider frequency
spectrum using RC networks
Referring to the output characteristic of a
single stage (Fig. 6) it can be seen that a
"high" output can only be flipped to "'low"
if the output is pulled down to 1.5V or less by
some external means, and this can only be
accomplished while the input voltage Vln is
"low", The output characteristic in Fig. 6 is
divided into the sections A-B and B-C, section
8-58
ITT SAJ110
FREQUENCY DIVIDER CIRCUITS
A-B being the normal operating range. As mentioned previously, in order to initiate a reset
it is necessary to force the output through the
range B-C to point "C", and this should be
effected in the shortest time possible (tr
0.1 msec) to avoid overheating the device (the
output transistor dissipates considerable power
during this period).
<
If the divider input potential is higher than OV,
then the trigger point C is shifted to the left
on the curve, which means that the output
potential would then have to be pulled down
to a level below 1.5V. If the input and output
of a divider stage or if several inputs and outputs of a divider chain are to be pulled down
to a low potential together, then this potential
should be less than 1.5V to ensure that the
circuits reset reliably under any condition (refer
to Fig. 13).
Reset Circuit.
Fig. 13 outlines a reset circuit suitable for a
seven stage counting chain. All the output
points as well as the input point I are connected, via isolating diodes, to the collector
of a switching transistor type 2N2218, or alternatively to a RESET switch. It is important that
the transistor collector voltage drops to a saturation ,level of less than 0.6V for the duration
of the reset pulse, and that the transistor is
capable of passing up to 400 mA of collector
current under the most unfavorable conditions
(Le. when all outputs are in "high" condition
prior to the application of a reset pulse). The
pulse source must therefore be capable of
supplying at lease approximately 15mA to the
base of the 2N2218 so that the requirement
VI1 =V01 = ... Vo.>1.5V is fulfilled. The reset
pulse duration is, however, not very critical
provided it is not less than approximately
1/Lsec.
As mentioned previously, the output state of
all the stages depends on the input state of
the first stage immediately ,after the occur~
rence of the reset pulse. There are two possible conditions:
outputs which were in the "high" state immediately before application of the reset pulse
change to "low" and maintain this state after
the reset pulse has been removed. The next
input pulse to h then causes all the outputs to
be triggered to "high", this corresponding to
a "PRESET" condition of the counter. Only the
second input pulse is counted. These conditions are summarized in the truth table in
Fig. 14 and it can be seen that the counter
counts (n-1).
Fig. 15, on the other hand, illustrates a condition in which all the outputs are in the "PRESET" state immediately after the occurren'ce
of the reset pulse so that the next pulse is
correctly counted as No.1. The explanation
for this is as follows: Although in this case the
reset pulse initially pulls all the outputs, as
well as the input h, to "low", the input h is
immediately returned to "high" at the end of
the pulse (t = t,), because the positive edge
at the end of the pulse is equivalent to the
application of a logic "H" to the input. This
positive edge triggers first output 0, and then,
in turn, all the other outputs to "high" - this
corresponding to the "PRESET" state of the
counter.
Conclusion
The SAJ110 is an inexpensive seven-stage frequency divider which, in comparison with
equivalent discrete-component circuits, offers
many advantages,. the most important ones
being: small size and low wiring and assembly
cost. The device, because of its electrical characteristics, is particularly suitable for use in
electronic organs where its performance is
superior to that of discrete component flipflops.
Being insensitive to the waveform of the input
signal, the SAJ110 will accept a square wave
as well as other types of waveforms (e.g.
sinusoids; moreover, the low output impedance
ensures that the output remains virtually constant irrespective of load, the lowest permissible load being approximately 2kfl. At maximum loading the output amplitude is only 1.5V
less than supply voltage.
The generation of output waveforms which are
very similar to, and possess virtually the same
frequency spectrum as, that of an ideal sawtooth, is possible simply by connection of RC
networks across the outputs.
VI1 = "low" (Fig. 14)
VI1 = "high" (Fig. 15)
In Fig. 14 I, was "low" at the instant when the
reset was applied; under this condition all the
8-59
•
ITT SAJ110
FREQUENCY DIVIDER CIRCUITS
r-- ---- -."- --- -.--- -- -SAJIIO -- -
f- - - - - - - - - . ------ ---.- ---- ---- r,:~o',
_. - - - - - - - - - - - - ----,
"
l mo • .=O.4tA
Fig. 13-Reset circuit for a seven stage counter
'"L--L..Jn L..Jn L..Jn
=
.., r::1 r.1 r.-r r.;'1
r;'1
H
L..Jn L..Jn ...... ______ .Jlw2w3w4W5w6w7L_L
TRUTH TABLE
"
o~~------~-~
~~-"----~-~
°r----L-i_____ J
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ci
H
h-----J
1-
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06
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:: _____
P.
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I, °1 02 03 04~
° L
1 H
2 L
3 H
4 L
'5 H
6 L
7 H
L
H
H
L
L
H
H
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
Os 07
L L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
_ _ _ _Re_..
_I_P_U''''_:-:1t:::'p>'~.
Fig. 14-Reset action at VI1
,
.
"'ow"
H
'1:lJL.J1..JUU1.JU-___ ~-L
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. r--1
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L-
or.-
H
-L
"
TRUTH TABLE
11 °1 ~ °3°4 °50s°7
°
1
2
3
4
5
6
7
Os-------lJ---·--------_~
°I_
-:f
I'
L-
Rese' pu, ••
H
-L
tp"PS
Fig. 15-Reset action at VI1
8-60
"high"
H
L
H
L
H
L
.H
L
H
H
L
L
H
H
L
L
H H
H H
H H
H H
L H
L H
L'H
L H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-I
SAH190
MaS TONE GENERATOR
mm
~~----
SEMICONDUCTORS
MOS TONE
GENERATOR
The SAH190 is a monolithic, MOC integrated,
special LSI circuit. Only three SAH190 circuits
are required to generate the twelve notes of the
highest octave in electronic organs. A twophase clock generator, which is in practice the
master oscillator of the organ, is required for
driving the SAH190. This generator delivers a
frequency considerably higher than that of the
highest octave. The SAH190 generates four
tones, the frequency spacing of which corresponds to an interval of three semitones by
dividing the clock frequency. By externally
switching the connection Option 1 these four
notes can be lowered as desired by a semitone
or by a whole tone so that the twelve master
oscillators required hitherto can be replaced by
three SAH190 units. By switching the connection Option 11, the output frequencies of the
SAH190 can be modified by one octave. One
can therefore choose whether the tones generated are to lie in the third octave or the
fourth octave above middle C, for instance.
The outputs A to D of the SAH190 are specifically designed for directly driving the integrated frequency divider SAJ110, see Fig. 3.
In addition, a further load with a resistance of
greater then 10kn can be conne·cted. The.output signal has a square wave form with a
pulse duty factor of 0.5. The greatest deviation of the twelve tones from the equal temperament scale is ±0.03 0/00.
MAXIMUM RATINGS
V,
Clock voltages ....... -30 to +0.3V
V3
Drain voltage ........ -30 to +0.3V
14 , I,
Output currents ............ - SmA
10, I,
........................... -SmA
Ts
Storage temperature
range ............ -20 to +80°C
6
7
max.9,4~
max.D,S ~
Fig. 1-SAH190 in a TO-96 metal case =TO-S
with 10 terminals. Weight approx. 1 g.
Dimensions in mm
Terminals
1. Ground, 0, Substrate, case
2. Option II
3.
4.
5.
6.
7.
8.
9.
10.
I
Output A
Output B
Output C
Output D
Clock pulse t2
Clock pulse t1
Option I
I
RECOMMENDED OPERATING CONDITIONS
V3
V" V,
ft
Drain voltage ... -17 (-15 to -19) V
Clock voltages .. -20 (-18 to -22) V
Clock .frequency ....... 1 to 1.5MHz
CHARACTERISTICS
In
Output resistance ........... ==:o:-r
6-2.54:15,24
~_ l
MAXIMUM RATINGS:
Ic
IB
VCEO
P'o'
Tamb
Collector current
25mA
(terminal 14 or 1)
Emitter current
(each emitter) ............... -5mA
Base current (terminal 7 or 8) .. 25mA
Collector emitter voltage....... 22V
Total power dissipation
at Tamb = 60°C ........... 250mW
Ambient temperature
range ............... -10 to +60°C
1,9
min.
2.8 1
Fig. 1b-TBA470 "B" in quad in-line (Quil)
,plastic package
14
CHARACTERISTICS AT Tamb
transistor)
B
VCE,a'
ICEO
=
25°C (each
DC current gain
at VCE
2V, Ic
1mA ...... >40
Collector saturation voltage
at Ic ::::: 1mA, IB
9.,1mA .... 100 KHZ
rin
Input resistance ............ 50 Kfl
rout
Output resistance ........... 200 fl
±Vout p-pOutput Voltage Swing
at RL =1Kfl ............ 5.5(>4.5)V
I"
Current consumption
(no load) ................... 5 mA
Gv
MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
V..
-V,
Vw ,
Supply Voltage ................ 9V
(Symmetrical) .................. 9V
(Asymmetrical) ................ 18V
8-74
V"
-V,
Supply Voltage
Vln
Common Mode input
Voltage ................... V, to V,.
Differential input Voltage..... ± 5V
Output Current ............. 10 mA
10 mA
Ambient Temperature
Range ................ 0 to +60°C
Vn
IA
-IA
Tamb
11V
11V
TCA250
DUAL FILTER AMPLIFIER
APPLICATIONS INFORMATION
Circuit example 1: Second order tunable RC
lowpass with symmetrical voltage supply.
A single-ended voltage supply is also possible;
as is shown in the following example.
Using one half of the integrated filter amplifier
TCA250 RC lowpass and hlghpass filters of
the 2nd or 3rd orders, as well as selective RC
filters can be devised. The lowpass 2nd order
shown in Fig. 2 uses very few passive components, is stable and has an adjustable frequency limit f o•
Adjustments of the cut-off frequency is possible over a relatively large range by varying R2
by the factor, a. When using this circuit as a
sine-wave filter in electronic musical instruments, tuning is not necessary if the passive
components have tolerances of + 2%.
Fig. 2 Tunable Low Pass Filter
2nd order with frequency compensation
for Av= 1
Table 1:
Component values for a Tschebyscheff-filter
with amplification constant within + 1.5 dB in
the transmission band (fig. 2)
fa in the band
16Hz - 250Hz
250Hz - 16Hz
C1
nF
6.8
C2
nF
100
1
15
R1
K
1000Hz 7.318,
R2
k
·1 OOOHz 8.466
1000Hz 55.04
1000Hz 51.02
~
It;
-ro-
10
With the circuit values of table 1 the characteristic a= 1, in fig. 3 is obtained.
Fig. 3 - Frequency Response of Low Pass
Filter of Fig. 2, a: Variation of R2
.~
d B·
I----
o
--....
3dB
~
1'\
-10
f\
1\
-2 0
a,1o,31
.......
'\
~
'"
~
\
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w=omega
1"-
-" "-
0,2
0,3
0,4
0,5
0,7
2
W
wo(av= 1)
8-75
r'-
r-.,
1"'-
[\
'",,-
~
-4 0
a,O,065
a,1I,3I4
""K. K.,1"'-
-30
0,1
r--.
4
~
10
TCA250
DUAL FILTER AMPLIFIER
Circuit example 2:
Fourth order RC lowpass with single-ended
voltage supply
C.
~
By arranging two 2nd order lowpass filters in
series a 4th order filter is obtained. Other circuit values are necessary, however, (see fig. 4
and table 2). The frequency characteristic given
by the values of table 2 is shown infig. 5. When
using single-ended supply voltages the noninverting inputs of the amplifier are connected
to a voltage divider and decoupled.
R
I
Fig. 4 -
Low Pass 4th Order with Frequency
Compensation for AV 1
=
+5
dB
o
..... .,.,
1\
-10
\
\
\
-20
-30
\
0.3
0.4
(\5
(\7
I
W
\
2
4
5
10
-wo
Fig. 5 -
Frequency Response of Low Pass Filter of Fig: 4
Table 2:
Component values for the Tschebyscheff-filter
shown in fig. 4, having amplification constant
within +1.5 dB in the transmission band
Voin
the band
16Hz - 250Hz
250Hz - 16kHz
C1
nF
22
2.2
C2
nF
220
22
C3
nF
2.2
C4
nF
680
0.22 68
R1
k
1000Hz5.6
-y;;
1000Hz 56
-y;-
8-76
R2
k
1000Hz 4.94
R3/k
1000Hz 4.01
/0
to
1000Hz 49.4
1000Hz 40.1
to
to
lC.A.210
=
I~r~jr ==_===_"I=~=Y=N=C=H=R=O=N=O=U=S=D=E=M=O=D=U=LA=T=C?~
='"
SEMICONDUCTORS
SYNCHl~O~OlUJS
DEMO[))lUJlATOR
The TCA270 is a monolithic integrated circuit
designed for use in colour and monochrome
television receivers. It consists of a synchronous demodulator, video amplifier with buffer
output stages, noise inverters, AGC detector
with output stages for npn tuner and IF amplifiers, and AFC demodulator with buffer output
stage. Opposite polarity video signals are available from emitter followers.
Normally the TCA270 is delivered in dual-inline plastic packages (similar to TO-116) (see
Fig. 1). Upon special request it is also available
in the quad-in-line plastic package (see Fig. 2).
Electrical Characteristics
Vs
Is
Vo
Vo
Vi
Ri
' -_ _ _ _ _ _
u~~~_.~
__
·~.
__
. _==I
Fig. 1-TCA270A in dual-in-line plastic TO-116
pac\cage.
Typ.
Supply voltage
range ........... 12.0(10.1-13.8)V
Supply current range .. 47(33-59)mA
Quiescent output voltage
both outputs) .............. +6V
Output voltage at start of AGC
(pin 9) ................... +3V
Unbalanced RMS input voltage
for AGC .......... 70 (50-100)mV
Input resistance (both inputs) .. 3Kn
3dB band width of video
output ................... 5MHz
Differential gain
(see note 1) .......... 1Omax %
Differential phase
(see note 1) .......... 1Omax deg.
Intermodulation products
(blue colour bar)
1.6MHz ................. -60dB
2.8MHz ................. -67dB
Carrier frequency rejection
at outputs ........... -40min dB
Twice carrier frequency rejection at outputs .... -40min dB
Fig. 2-TCA270B in quad-in-line plastic package.
Absolute Maximum Ratings
Vs
P tot
TalUb
Ts
8-77
Supply voltage .............. l8V
Total power dissipation ........ 1W
Operating temperature
range ............... -25 to 55°
Storage temperature
range .... , ....... -25 to 125°C
TCA270
SYNCHRONOUS DEMODULATOR
R; ....................... 1.BKn
AFC
Output control voltage swing
(pk-pk) ........................ 10minV
Change of frequency for complete
output voltage swing ........ 400maxKHz.
Change of frequency to maintain
peak output voltage .......... ±1 min MHz.
Noise Inverters (see note 2)
Negative going noise pulses in pin 9
inversion threshold ... ; ........... ±2.55V
Positive going noise pulses in pin 9
inversion threshold ................ ±6.6V
NOTES
1. CC1 R system of modulation, peak white=
10 % carrier
Cu rrent ratio of unsatu rated
outputs 14/15 for
I,=1mA .................. 6min
2. Noise pulses are inverted to a point near
black level
AGC
V..,(pin 4)
V.. (pin 5)
VUlt
10
Saturation voltage of tuner
control at .10ma ........ +O.3V
Saturation voltage of IF
control at 10mA .. O.7min, 1.2max V
Breakdown voltage at
1mA (pin 4 & 5) ........ 14min V
Control current
(pin 4 & 5) .......... 10min mA
Signal expansion for complete
AGC ................ O.5max dB
AGC gating (optional) by
negative line fly back pulse
V; .............. 2min, Vsmax V
0
Fig. 4-Typical Application
vcc
7. 5
TUNER
RFSTAGE
5.0
12V
............
2.5
I.F. CONTROL STAGE
1.2K.n
k
2e
0
Z5
V
'\-c
l'----
U
50
75
-
PO
1.5
Fig. 5-Transfer Characteristic
80jlF
I
330.n.
1
33011
VI5
12.5
0-
10
'\..r
7. 5
OPTIONAL
r - - - o O LINE GATING
NC
5.0
2345678
TCA270
2. 5
/
/
J
15
14
13
12 .......
II -,.;-.-1-l- ___________6V
..........16r--r-.....-'"tc-=-_
40
'------.,s' -~ - ,0-:6
-,
----r-
TUNING
VOLTAGE
45
~
-
~
_IT
. T __
TCA350
A_N_A_L_O_G_S_H_IF_T_R_E_G_IS_T_E_R_{...
D_E_LA_Y_L_IN.....
E)
SEMICONDUCTORS
ANALOG SHIFT
REGISTER
(DELAY LINE)
Features
• 185 stage "Bucket-Brigade"
• Delay line for audio frequencies
• Symmetrical clock inputs up to 500 KHz
• Variable delay
to=~
2fc1ock
The TCA350 is a monolithic integrated circuit
using MOS technology for the delay of analog
signals up to 250 KHz. It uses the "bucketbrigade" principle and consists of 185 seriesconnected MOS transistors together with 185
integrated capacitors.
max.O,S·
Maximum Ratings
Voo
VE
Vu , V"
IA
Ts
Fig. 1-TCA350 in metal package JEDEC TO-77
(=TO-5 with 6 leads)
Drain voltage ...... -30 to +0.3V
Input voltage ........ -30 to +0.3V
Clock voltages ...... -30 to +0.3V
Output current ............. -5mA
Storage temperature
range .......... -40 to +100°C
-24Y
Recommended Operating Conditions
Voo
Vr: V"
fclock
t,ft
tz/T
VE
R,XR,
R,+R,
VE pk-pk
TA
I 6
Drain voltage .............. -24V
Clock voltages .... -19(-18 to 20)V
Clock frequency ...... 5 to 500KHz
Duty cycle of clock .......... 0.25
(T= 1ffclock) • • • • • • . • • • • • • • • • 0.25
Input bias voltage . -8(-7.5 to -8.5)V
Biasing
resistance at input ....... <20KO
Input signal amplitude ........ <6V
Ambient temperature
range ............ -20 to +60°C
I
L
4-+--J.-+--_~-+--!-Ot' 1·laYI
I
L -_ _i - -_ _ _.....-I- Vs ;12 v
"h
The monolithic integrated circuit TCA430-N
contains four RC oscillators in one package
and is designed for use in electronic organs.
Three TCA430-N integrated circuits provide
the twelve master oscillators of the highest
octave. The symmetrical square wave output
signals of the oscillators are suitable for
driving the integrated frequency divider SAJ
110, with which the lower octaves are obtained.
Since the TCA430 is thermally neutral, the
frequency stability of the oscillators is solely
dependent on the temperature coefficients of
the frequency determining RC elements. A
vibrato effect can be generated for all the
oscillators via the vibrato input Pin 4. The
TCA430-N replaces the TCA430, differing in
pin configuration only. Pins 5 and 8 have been
exchanged.
R"
CJ~·
H~
R"
AU
Ri
A3
CA430-N
d1 hR2'
~: pm· m
t- ~~ r--o Vibrato
Ru
112
A2
I
16
r-..
Ru
II--
c:,~
ql~
AI
0
Fig. i-Operating circuit of the TCA 430-N
r-
r
MAXIMUM RATINGS
(All voltages referred to Pin 1)
VB
A4
I -11"
R'
JL
II
el--
9
<0
Supply voltage ................ 15V
1" I" IG, I, Output current ............ 7.5mA
V'pp
Tamb
Ts
Vibrato voltage, peak-to-peak,
(pin 4 must be driven via
a capacitor) ................. 6V
Ambient temperature
range .......... -10 to +60°C
Storage temperature
range ............ -30 to 125°C
Figure 2
RECOMMENDED OPERATING CONDITIONS
Supply voltage ..........
12(>9)V
RL, to RIA Load resistors .......... 3.3(>2)kfl
R, to R, Frequency-determining resistors (Metal film resistors
with a temp. coefficient
::(50 X 10 "jOC) ....... 5 to 50 kfl
C, to C, Frequency-determining
capacitors (MKC polycarbonate foil capacitors) ...... ::(1 F
fo
Oscillator frequency .. 20 to 30,000Hz
v
8-81
Output voltage at high state
Pulse duty factor of the
square wave output
voltage ....................
0.5V
Oscillator frequency
865
Hz
R/kfl . C / ",F
Input resistance of the
vibrato circuit ................. 4kn
Slope of the vibrato circuit
For a vibrato of ± one semitone, a peak-to-peak voltage
of 1.7V is required at pin 4.
CHARACTERISTICS
at VB =12V, RL1 to RL,=3.3 kfl, Tamb =25°C
Current consumption ........ 22mA
Output voltage at low state .. .. ~J\
4
'\..
-10 ~
= 2Sif'c/W
f' 1\ \
6
o
RlhU
f'<
~
5"10-~;"...
.1 Vz
12
10
ZTK 6,8
40
1 1\
14
mV
ZTK 33
ZTKS.8 to ZTK33 (TAA550)
MONOLITHIC TEMPERATURE
COMPENSATED ZENER DIODES
mY
mY
ZTK 18
90
90
J
5x10- sl't
~
~
~~ ~ ~--;~
-30
"'"
-60
-90
-120
-150
o
20
40
'"
60
~
"'
~
-60
80
t::::'
"'" "
-'/z=15mA
-lOXlO-S'OC~
-150
-180
100°C
o
20
.\0
100
"
" "-
~
.......-::
100
"'"
-150
'-10xl0- s/0c
-200
-250
-300
L~ F----:~I.:_
-100
20
40
60
'"
-200
I---+---l---+---+~~
-250
I---+-'---+----+----!-,-~
-300
I----+----+----+---+---!
L-_-"---_--L._......L_---L_ _
o
80
20
.\0
60
80
100 DC
---"Tamb
----<.... Tamb
Change of Zener voltage versus ambient
temperature
1---+---1-~rt----+---1
-150 1---+---1---+----"1.--+---1
-350
o
I---+-'---+---I-----!-,~:.......j
.1 Vi 50
.\Iz =15nlA'"
-100
-350
-
k=5mA'
100 DC
mV
ZTK 33
150 ,...--.----,----,---,----,
sx~
~
80
Change of Zener voltage versus ambient
temperature
ZTK 27
mV
150
60
- -.... Tamb
- -.... Tamb
Change of Zener voltage versus ambient
temperature
._--
-/z=5mA-
'"
-120
"
/.
'\
-90
'\
-10xl0-Sf'C ~
,;y
/l
5XlO-s
.....
~
'"
~ "-
-30
-180
ZTK 22
120
120
Change of Zener voltage versus ambient
temperature
8-86
ZTK33DPD
MONOLITHIC TEMPERATURE
COMPENSATED ZENER DIODE
ITT
----SEMICONDUCTORS
MONOLITHIC TEMPERATURE
COMPENSATED ZENER DIODE
Monolithic linear integrated circuit producing
an extremely constant temperature-compensated voltage, particularly suitable for stabilizing the tuning voltage in Television and Radio
tuners employing capacitance diodes. This
device is available in a low-cost diode package.
CHARACTERISTICS
(At Tamb =25°C, Iz=5mA)
Reference voltage ...... 30 to 36V
Vz
Inherent Dynamic
rZI
Resistance ............ 13«25)0
o::.Vz
Temp. Coefficient of
Reference Voltage
at Iz=5mA+0.5mA with
Range Tamb 20°C to
60°C ... -2(-10.to +5)X10 5;oC
tth
Thermal Time Constant
(turn-on) .............. 20 sec."
Rthj -a
Thermal Resistance
Junction to air ..... <0.3°C/mW'
CATHODE BAND
NOTES:
I. ALL DIMENSIONS ARE IN INCHES AND ARE
REFERENCE UNLESS TOLERANCED.
2. LEAD DIAMETER NOT CONTROLLED WITHIN
.050· OF THE BODY.
Package-Jedec 00-35 Double
Type
'This value applies when the connection leads
Bmm from the package and are maintained
at ambient temperature.
"At the end of the thermal time constant
(turn-on) 90 % of the reference voltage tNzmax
spread fades away.
~Vzm.x=Vz( 0::.)
- Vz(O)
with Vz(O)=Vz at instant of switch-on.
and Vz( 0::.) =Vz when thermal stability (balance)
is reached.
8-87
Plug
Diode
MAXIMUM RATINGS
Iz
Operating Current at
Tamb =45°C .............. 10mA'
Tj
Junction Temperature ....... 150°C
T.
Storage Temperature
Range .......... -20 to +150°C
ZTK33DPD
MONOLITHIC TEMPERATURE
. COMPENSATED ZENER DIODE
-::::
ZTI<330PO
! ~~~ ~
51~
f---'" ,---8
ZTI<330PO
Q
1000
=
.....-: ;::: :;..:
/Z s 7,5mA
-
~
1~
~~
lfi~ ~2mm
IV/; ~a-25mm
TA-25°C
\
5
I"
"-
Ihrr/
r--. r-...
10
-
Ib
o
~
Ii
10
_time
10-
ZTI<330PO
\
6
8
10mA
ZTI<330PO
Iz-5mA
100
--
tJ.Vz 50
t
f\
5
,
mV
150
\
t
2
Inherent Dynamic resistance versus operating
current.
1\
Iz
o
-Iz
Curves showing relationships of /iV. after
switch-on for different lead lengths between the
package and solder point maintained at ambient temperature.
rnA
o
20se"
0
I-"
I-50
.\
-100
\
.............
-ISO
\
-200
\
-250
\
-300
\
100
_TA
-350
200"C
Permissible operating current versus ambient
temperature
(see note*)
o
20
40
60
80
100 DC
-TA
Change of reference voltage versus ambient
temperature
8-88
UAA110
_ITT _____
C_A_M_E_R_A_,_N_T_EG_R_A_T_E_D_C_,R_C_U_,T
SEMICONDUCTORS
CAMERA INTEGRATED
CIRCUIT
A monolithic integrated cricuit for the control
and monitoring of all functions of an electronic (single-shot) camera. Fig. 2 shows the circuit diagram of such a camera using the UAA110. In order to avoid over-exposure while
taking brightly-lit scenes and camera movement in dim light, a mea,surement phase precedes the automatic setting of the exposure
time. In this phase, the light intensity is measured as the shutter release is depressed half
way. The indicator-lamps Lu (over-exposure indicator) and Ls (tripod-indicator) show respectively whether the aperture must be reduced or
whether a tripod (or a larger aperture) should
be used. For this purpose two voltage comparators are used which are driven during the
measurement-phase from the photo-resistor RF •
In addition, the state of the battery can be
checked by blocking, (with the finger, for example) the light to the photoresistor. If the
lamp Ls does not light, the batter is exhausted.
If the shutter-release is fully depressed, the
photoresistor is connected to the integrated
capacitor at input of the threshold amplifier. At
the same time, the shutter is opened and held
open with a latch during the exposure. The exposure time is determined by the charging of
the capacitor CF through the photoresistor
whose resistance is dependent of the illumination. When the voltage on the capacitor
reaches the threshold voltage of the amplifier
(determined by the voltage divider Ry , Rx) the
electromagnet M is activated and the shutter
latch is released, permitting the shutter to be
closed by means of a spring.
I
I
--7,62----1
Fig. 1-Package
QS5it--+----,t-i:.....
O.4t--+--+---t
RECOMMENDED OPERATING CONDITIONS
(see the circuit of fig. 3)
V"
Riso !
TA
+
CM
~4---6-+--------4-~O
Supply voltage .......... 3,5 to 6V
Potential divider ratio .... 0,55 to 0,8
Photoresistor ........ 100 to 2x10Tn
Insulation resistance ...... >250MO
Ambient temperature
range ........... -18 to +50°C
Fig.
8-89
2~Block
diagram of camera
UAA110
CAMERA INTEGRATED CIRCUIT
All voltages are referred to Pins 4 + 7.
MEASUREMENT CONDITIONS FOR THE
CHARACTERISTICS
(see measurement circuit, fig. 4)
Definitions
Operating voltage limit
(lowest voltage) VeA: maximum supply voltage
at which the voltage V,>2,5 V for a specified value of X
RA
VI'
Potential divider ratio ..... X RA + Rp =-v;
Equivalent resistance
.
Potential divider ratio ...... V
Rx
Rx + Ry
-
Delay time ........ t v =R F XCFX1n 1,043
Insulation resistance
V"
V.
1
V
_ Rc x Rs
Ri,ol - Rc + Rs
Rs = insulation resistance of the printed circuit board and Rc = insulation resistance of
the capacitor CF
V"V"V,
V"V"V,
p"p,
P3
V
ll
RM
CHARACTERISTICS MEASURED UNDER THE
ABOVE MENTIONED CONDITIONS
I,
MAXIMUM RATINGS
Ts
Supply voltage
6,5V
Output pulse currents at an
operating frequency 1Hz
Lamp current, pulse
duration <50ms .......... 120mA
Electromagnetic coil current,
pulse duration <5ms ...... 350mA
Lamp current, continuous .... 40mA
Reverse current while switching
an inductive load ........ -20mA
Storage temperature
70°C
range ........... -30 to
+
Supply voltage (± 1 %) ........ 5V
Ambient temperature .... 23 to 25°C
Output voltages in "L" state .. <1,4V
Output voltages in "H" state .. >4,5V
Threshold potentiometer ........ 1 kO
Reference potentiometer ...... 10kO
Reference voltage (± 0.1 %) .. 3,375V
Equivalent resistance of the
lamps .... '" .............. 1330
Equivalent resistance to the
electro-magnet ............ 13,30
Current consumption at
V" =2,5V, V, = 0 .......... <6mA
at Vo = 1V, V, = 5V ........ <6mA
Output leakage current
at V"
6V, V4 = 0 ........ <0,1mA
Input curent at Vo = 2V ...... <8nA
Input switching current
=
at Vo = V" ........ . . . . . . .. <25nA
Input current at
V" = 4,35V, V. = 0 ........ <2fLA
Saturation voltage
V 1sat
at V" = 5V, V, = 0 ......... <1,2V
V2sat
at V" = 0, V4 = 0 .......... <1,2V
V ssat
at Vo = 5V, V4 = 5V ........ <1,3V
Vl2S
"Tripod"-threshold volt. range
at V, = 5V ............ 1,9 to 2,11V
Over-exposure threshold volt.
range at V4 = 0 .... 4.14 to 4.35V
V"
Exposure-time threshold volt.
range at V4 = 5V .. 2,97 to 3,335V
Relative exposure-time error
±Ilt./tv at V4 =V,=3,5 to 6V ........ <15%
+Ilt./tv at RF 10MO, TA=24°C ...... <30%
-Ilt./tv at RF 10MO,
TA=-18 to +50°C ........ <25%
+Iltv/tv at RF =20MO, TA=24°C ... <100%
-Iltv/tv ........................... <30 %
V'A
Offset voltage limit of battery
at X=0,3,
Vo
3, 5V, TA=24°C .... 3.1 to 3.5V
IlV'A/IlTA Temperature coefficient of offset
voltage ............... -10 mVioC
112
=
Fig. 3-Measurement circuit for UAA110
8-90
UAA110
CAMERA INTEGRATED CIRCUIT
~L2
P, ~V,2
/.
V2
q"
v,'-- ..-.--.-1 '-/ 14
-
V,
/o
~P,
\5
1
~R"
v
.sv
110
5
J
I
4.5 V
V9 =5 V
Ru =133n
TA =24°C
~
1
4.14
I-
I-UAAll0 t-----"
F7
l-
1
v/l
';',:::
~3
l001i 6V
1'"
B
V,
0
2
Fig. 4 -
tt3SV
Measurement circuit for UAA110 '"
l~
f- VI sal <1.2 V
V
5
110
V9=5 V
V = 0.675
RM =13,3 II
TA =24 °C
I
4.5V\
o
I
o
2
2.97 V-1
3
----1>
4
SV
VI2
Fig. 6 - Transfer characteristic of the overexposure indicator
110
V
5
v
I.
9 =SV
RL2 =133n
.L4.SV
I
~2.1IV
TA =24 °C
2
t{3.335 V
L~UV
-f-V8sat <1,3 V
~
2
o
o
2
3
4
1.9 V1
5V
k-
1.4"7'
V2sal<12V
Fig. 5 Transfer characteristic of the exposure-time forming circuit
o
o
2
3
4
SV
----1> Vl2
Fig. 7 - Transfer characteristic of the tripod
indicator
8-91
UAA110
CAMERA INTEGRATED CIRCUIT
v
110
110
2
5
x =0.3
RL2 =133 Q
TA =24°C
t •
v
'f
II
V
V11V~
2
o
V
V
V
V
o
4
3
- - - I.....
1\ \
1\ \ \\
2.5 V
f'-3.5 V
.......
~
2
\
Mot~
-
~OM'" ~ ~
~O~M ~ ~
\
1
5V
o
l"
200
- b:'
-
i"-
400
Vg
600
- - - I.....
Fig. 8 - Transfer characteristic of the operating (triggering, firing voltage)
UAA 110
sr---,
...,
I
I
Rs: Re:
I
1
I
7 ___ .J
=
Reo Rs' Re
Rc' Rs
800
1000MQ
RG
Fig. 9 - Influence of the shunt resistance on
the exposure time
't--"-~,
I
Es ist RG
RF =100MQ
+ Rs . Re + Rc' Re
Fig. 10 - Equivalent circuit for the shunt resistance RG
8-92
-
SAJ220 FAMILY
QUARTZ WATCH &
CLOCK INTEGRATED CIRCUITS
ITT- - - - SEMICONDUCTORS
t~'~lq
QUARTZ WATCH &
CLOCK INTEGRATED
3 x \27
CIRCUITS
=3,81
~
This family of monolithic integrated circuits has
been specially designed for use as frequency
dividers in Quartz Crystal controlled wrist
watches and clocks. The devices consist of an
oscillator, frequency divider chain, pulse
shaper and output stage. An external resistor is
used for current consumption programming.
The output stages have been designed to suit
the majority· of available movements. 'These
devices are available in several different circuit variations. Please contact factory for special requirements.
.fi-
qs
Fig. 1 -
Dimensions inmm
15°
.0.15
I
MAXIMUM RATINGS
VB
TA
Ts
0" IS·
,0--7.62_
Supply Voltage ................ 3V
Operating Temperature
Range ............. -10 to +60°C
Storage Temperature
Range .. : ......... -30 to +125°C
8
765
231,
TYPE
220C
2200
220H
220M
220P
220S
Note 1
Note 1
Note 1
Note 2
Note 2
Characteristics
Note 1
16
16
15
16
Current Consumption
(IB)
8/LA
8/LA
8/LA
8/LA
Output Frequency
(fo)
0.5Hz
O.5Hz
1Hz
O.5Hz
Output Pulse Form
Output Pulse time
(To)
Output Saturation
Voltage V
Push-Pull
16mS
Push-Pull
8mS
Unipolar
BmS
1
Bi-directional
12mS
16
15
20/LA
20/LA
O.5Hz
1Hz
2 Phase
Unipolar
Unipolar
32mS
32mS
(RL=2.2Kn) (RL=2.2Kn) (RL=1.2Kn) (RL=2.2Kn) (RL=1Kn)
O.25V
O.25V
O.W
0.25V
O.25V
8-93
1
:.1.
1
I
Fig. 2 Dimensions
inmm
Stages
. ,.
.....
[J
(RL=200n)
1.2V
SAJ220 FAMILY
QUARTZ WATCH &
CLOCK INTEGRATED CIRCUITS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Va
1-2V
1-2V
Note 3
1-2V
1-2V
1-2V
1-2V
Progr;l.mming
Resistor Rp
2.5Mn
2Mn
2.4Mn
2.2Mn
470Kn
470Kn
Quartz Series
Resonance
Frequency fQ
32768Hz
32768Hz
32768Hz
32768Hz
32768Hz
32768Hz
Quartz Series
Resistance Rs
<30Kn
<30Kn
<30Kn
<30Kn
<30Kn
<30Kn
Trimmer
Capacitance CT
10-50pf
10-50pf
10-50pf
10-50pf
8-56pf
10-50pf
Output Load
Resistance RL
>2Kn
>2Kn
>1.2Kn
>2Kn
>1Kn
>200n
Package
Fig. 1
Fig. 1
Fig. 1
Fig. 1
Fig. 2
Fig. 2
Application
Watch
Fig. 3
Watch
Fig. 3
Watch
Fig. 4
Watch
Fig. 5
Clock
Fig. 6
Clock
Fig. 7
2. Vn=1.5V,
Rp=470Kn,
T.=25'C, fQ =32,768KHz
,3. Reset with switching Pin 1 to negative. Fig. 4.
NOTES:
,1. VII =1.35V,
Rp:=2.4Mn,
TA=25'C,fQ =32,766KHz
O.lJlF
Rp
4
SAJ220C
SAJ220D
Rp
Fig. 5
Fig. 3
+Vs
0.1",
+
I.Sk
SAJ220S
Rp
Rp
o
Fig. 4
470k
Fig .. 6
O.IJlF
~;===~~r--------r~+v.
$AJ220H
I
RESET
Rp
2.2M
Fig. 7
8-94
G
v.
-- I
TAA780
1.1V STABILIZING CIRCUIT
mm
~~-----
SEMICONDUCTORS
91
,8 9
1 .1 V STABILIZING
C~RCUIT
....
I.
It>
~.
0,5
0,2 thick
Monolithic integrated circuit, e.g. for the voltage-stabilized drive of clocks and for the
stabilization of the operating point in transistor circuits. The circuit comprises the operating transistor T1 (see fig. 2) and a control
circuit for the stabilization of the output voltag e VaN to 1.1 V.
--.j
5 14-
1.~+1i
.' ·4
",~.
r
--'3
Fig. 1a - TAA780 "A" Plastic package with
vertical leads. Dimensions' in mm.
Normally the TAA780 is delivered with vertical
leads (Fig. 1a, add suffix "A" to the type No.).
Upon special request, it is also available with
horizontal leads (Fig. 1 b, add suffix "6" to thE'
type No.).
All characteristics and maximum ratings indicated below refer to the test circuit (Fig. 2)
shown on page 30. The figure 0 in the index
of some characteristics means that in this
case all other terminals are open.
The following definitions apply:
Lf V214'
Lf
V314
SV3/'= Lf V314' V214
and aV314:=
V314'
V314
Lf Tamb
Fig. 1b - TAA780 "8" Plastic package with
horizontal leads. Dimensions in mm.
MAXIMUM RATINGS
V3 /1!O
V'/l/O
I,
11
Tamb
T,
Collector base voltage .......... 3V
Collector emitter voltage at
R,/,,=5k (ext. connected) ........ 2V
Emitter base voltage ............ 2V
Substrate base voltage ......... 2V
Collector current ............ 15mA
Stabilizing current ............ 1 mA
Ambient temperature
range ............. -20 to +40°C
Storage temperature
range ............. -20 to +125°C
I
I
I
I
I
L_
'd
I
I
I
I
T1 :
Operating transistor
T2:
Regulation transistor
Blocking diode
R1, R2: Voltage divider
. ___ J
4
Fig. 2 - Circuit diagram and test circuit for
characteristics and maximum ratings
8-95
TAA780
1.tV STABILIZING CIRCUIT
mV
100
CHARACTERISTICS at Tamb =25°C
DC current gain of transistor T,
at V'I,,=1.5V, 1,=0.3mA,
1,=0 .................. 250(>120)
Collector saturation voltage at
V'",at
transistor T1 at 1,=3.5mA,
1,=35fLA, 14=0 .......... 0.1«0.12)
Vl/osat
Sase saturation voltage of
transistor T1 at 1,=3.5mA,
1,=35fLA, 14=0 ................ 0.7V
R1 +R2 Total resistance of voltage
divider ................ 15(>10)kn
V 3/,
Stabil ized voltage
at V'I,=1.5V, 1,=250 fL A,
1,,=3.5mA ............... 1.1±0.06
Voltage stabilization coefficient
SV3/4
at V'/4=1.3 to 1.7V, 1,= 250fLA,
b=3.5mA .............. 1.1 ±0.06V
Temperature coefficient of
the stabilized voltage
at V'/4 = 1.5V, 1,= 250 fLA,
b=3.5mA ...... -2.8 X 10- 3 1i"C
Small signal current gain of
hr.
transistor T1 at V'I,,=1.5V,
1,=0.3mA, 1,=0 ............... 250
TAA 780
Sf} 3
mV
10
80
/
J
V
L
o
V
-'-
-20
-40
V
I
-60
'2/4 = 1,5 V
13 =3,5mA ~
-80
= 25°C
'---
I
-100
10
20
50
100
200
.. 1/
500
1000 llA
Variation of output voltage V 3/4 versus current
I, referred to 1,= 250fLA, V3/4 =1.1V
TAA 780
mV
TAA 780
140
120
I
1\
0
4V3/4
I
12t4 = 1,5 V
\
1/ =250 llA 13=3,5mA _
I\.
!
\
->C
f\
\
40
-20
~
20
-30
~
o
-40
1/ = 250 ~A
13=3,5 mA -
-20
~=25°C
-40
_
J 1 1
-50
1,1
1,2
1,3
1,4
1,5
1,6
1,7
-60
-20
1,8 V
.. '2..z
Variation of output voltage V"I" versus input
voltage V'I" referred to V'i4 = 1.5V, V"I' = 1.1 V
\
~
-10
o
10·
20
--""'''.1A
30
40°C
Variation of output voltage V 3/, versus ambient
temperature referred to Tam b=25°C, V"/4=1.1V
8-96
TBA840, TCA840
TT
I
----WRIST-WATCH
BALANCE WHEEL DRIVERS
SEMICONDUCTORS
~
-
~
~
N
0.5
The TBA840 and TCA840 are monolithic integrated circuits for driving wrist watches with
single coil balance systems. Besides the driving-coils, the TBA840 and- TCA840 require only
one external capacitor and allow for extremely
space-saving circuitry inside an electronic wrist
watch. Self-starting is guaranteed for oscillation systems with sufficient induced voltage.
The mechanical oscillation amplitude is stabilized against external influences. The amplitude variation within the specified temperature
range is of a few rotation degrees only. The
circuitry may be operated from conventional
mercury oxide or silver oxide batteries. The
internal current consumption is small. The
TCA840A (geen) is recommended for use with
miniature watches with lightweight balance systems whereas the TCA840B (red) is for use
with tuning-fork or heavier systems. The TBA840 has a somewhat larger package and may
also be used in above applications.
MAXIMUM RATINGS
VB
I, & Ia
TA
TCA840
TBA840
WRIST-WATCH
BALANCE WHEEL
DRIVERS
:
~
1.4
N
0.3
Plastic micro package
Dimensions in mm
Packages: Fig. 1
MEASURING CONDITIONS FOR CHARACTERISTICS
The characteristics are measured in the test
circuit of Fig. 4. The actual signal conditions
within a watch were simulated using a function generator with signals as shown in Fig. 5.
VB
RL
VGS
C
Supply voltage ............... 1.5V
Load resistance ............. 2.5KO
Signal voltage (fig. 5) ........ O.9V
Frequency of drive pulse ...... 6Hz
Capacitor ....•....•..•.....• 1J-tF
CHARACTERISTICS at TA
uring conditions.
Itot
RECOMMENDED OPERATING CONDITIONS
VB
Nominal Supply Voltage .. 1.35 or 1.5V
fn
Frequency of driving
pulses .............. 2.5 to 12Hz
C
Capacitor .............. 0.5 to 4J-tF
Duty cycle (fig. 3) ...... 0.03 to 0.1
Coil resistance ........ 1.5 to 3.5KO
N
2
3
fn
Supply voltage ................ 3V
Currents I, TBA840, I,TCA840 .. 1rnA
Ambient temperature
range ........... -10 to +60°C
i f'
0.4 -
= 25°C. See meas-
Current consumption total .... 8.5f.lA
Ratio of driving current for
the oscillator to total current
consumption .................. 0.9
Drive pulse duration ....... 7.8 mS
Drive pulse duty cycle ........ 0.05
Saturation voltage V" TCA840,
V" TBA840 .................. 0.3V
Output series resistance ...... 1Kn
(See fig. 2)
Ipk = VB-V s Peak Value of operating current
I" TCA840, 1" TBA840 .......... .
RL+R,
Vs,=Vs,
Switching thresholds .......... 0.5V
8-97
TBA840, TCA840
WRIST-WATCH BALANCE WHEEL DRIVERS
Circuit Design Information
c
The optimum position for an output pulse is
when the switch-on threshold VSI and the
switchcoff threshold Vs, are equal. This is dependent upon the capacitor, C, chosen, the
mechanical clockwork, induced coH voltage
Vin s, driving frequency, fd, duty cycle tilT and
the coU resistance RL •
r
RI
With two-magnet systems, the output drive
pulse must appear only once per total oscUlation because the polarity of the induced volttage changes with each change in oscillation
direction. Care must be taken when designing
the external components with this system.
TIJ------;--------r---~
L _________________
The switching threshold is changed together
with the induced coil voltage. For optimum
pulse conditions, i.e. VSI
V S2, the switching
threshold is only dependent on the maximum
induced voltage.
o
~
c
=
3
,
r- --TBA 840------ -----,
I
I
I
I
The self-starting properties of the system are
dependent on the operation of the oscillator
and coil. The start-up time is limited by the
movement of the balance wheel, magnets,
value of the induced voltage and the coil resistance.
I
I
R,
T3
R,
RS
I
I
I
R2
I
I
I
I
I
I
.f?]
T1}------+-------+--~
I
IL ____________
o
~
____ JI
Circuit Diagram
Fig. 2--lnternal circuit diagrams TBA840,
TCA840
.
o~--~----------~~------~-
_I
Fig. 4--Test Circuits
Fig. 3--0perating waveforms for Veoil and leoll
with a 3-magnet balance system. (Vc & Ie)
8-98
TBA840, TCA840
WRIST-WATCH BALANCE WHEEL DRIVERS
-t
-t
Fig. S-Signal induced Waveforms
Hz
V
20
1
r
I
//
1\
/
V
o
OS
~
I
/
/
/
0.5
/
/C=0.2SIlF/
o
r
/ /
I
10
V
I
/
/,
/
/
I
Y1.~
/
I
o
2V
/
o
2V
--~
..
Fig. 6-Calculation of capacitor Value, C. See
measurement conditions.
8-99
Vins
Fig. 7-Switching thresholds versus induced
voltage.
_
I
TAA775G
POWER OSCILLATOR
mm
..L..L _ _ _ __
SEMICONDUCTORS
POWER OSCILLATOR
Monolithic integrated circuit in bipolar technique. Particularly suited as electronic pulse
generator for direction blinker and emergency
blinker in cars with 12 V DC supply. Also
suited for other applications, e. g. for interval
wind-screen wipers.
Dual In-Line
Plastic Package
The TAA775G is an oscillator, the frequency of
which is determined by an external RC network
and which supplies rectangular output pulses.
The output terminal 10 is connected to the collector of the output transistor operating in
common emitter configuration. An integrateddiode between the collector of the output
transistor and the supply voltage terminal 1
allows for operation with inductive loads.
;~
IS! _ _
~
1---7.62 --..j
As can be seen from the terminal diagram
Fig. 1, the TAA775G has two oscillator input
terminals 5 and 6, for the connection of the
frequency-determining RC network. By applying a suitable control voltage to the control
input (terminal 7) the following operating modes
are possible (see Fig. 5):
a) Operation at nominal frequency fo
b) Operation at increased frequency f'o
c) Oscillator not oscillating
When a control voltage for operating mode a)
or b) is applied, oscillation starts in the onstate. Since the control voltage is effective
only during the off-state, blocking of the oscillator in the on-state is possible only at the
end of the normal on-state.
Static Characteristics @ V,=12V:V.=V.=OV,
Tam b=25°C (see Fig. 3)
I,
Average current consumption ... SmA
-I.R
Leakage current of the oscillator
input at V.=OV .......... <1 p.A
Maximum Ratings (All voltages are referred to
terminals 3 and S.)
Required oscillator input current for turning on the
oscillator output ......... >10p.A
Terminals 3 and S grounded
V,
Supply Voltage ............... 15V
V,
Control voltage .....•..•...... I k.n~L_--A---J
-
.r..3ande
Fig. 10: TAA775G as pulse generator with
adjustable on-time
For the circuit in Fig. 10 these equations are
valid:
ton
tOff
= 0.6XCX(R1 + R,)
= CXR1 msec
msec
Fig. 8: TAA775G as pulse generator with adjustable frequency and constant on/off ratio.
Charging and discharging of the time-determining capacitor through the same resistor.
5 .____ ~
..--...-----.....-o--l
----I
I
1
1
1
R in kfl
C in MF
+12V
+12V
TAA775G
TAA775G
7
•
: 10
1
1
1
Raand Re >'1 kOeacho--tL.
~
I
---l.----I.
Fig. 11: TAA775G as pulse generator with
adjustable off-time
:1..3and8
Fig. 9: TAA775G as pulse generator with adjustable frequency and constant on/off ratio.
Charging and discharging of the time-determining capacitor is effected through separate
resistors.
For the circuit in Fig. 11 these equations are
valid:
ton
torr
For the circuit in Fig. 9 these equations are
valid:
ton
torr
= 0.7XCXR. msec
= CXRa msec
R in kn
C in MF
8-103
= 0.7XCXRl msec
= 0.75XCX(R1 + R,) msec
R in kfl
C in MF
SAK115
_ITT ___
T_A_c_H_o_M_E_T_E_R_'N_T_E_G_R_A_TE_D_c_'R_c_u_,
T
SEMICONDUCTORS
TACHOMETER
INTEGRATED CIRCUIT
Dual In-Line
Plastic Package
The SAK115 is a monolithic integrated circuit
designed for use as a pulse shaper in tachometer/rev-counter applications. By choosing
suitable external components, the SAK115 can
be used with 2 to 8 cylinder engines. It is designed for a nominal 12V supply. The basis of
the SAK115 is a monostable multivibrator
which converts the input signal (derived, for
example, from the contact breaker) into square
pulses of constant voltage and duration. Using
an 8 mA moving-coil instrument, it is possible
to design a simple freq'uency meter. The circuit
features good noise immunity as it can only be
triggered by input pulses exceeding 8 volts. An
internal diode parallel to input te~minals 1 and
3 prevents triggering from negative pulses. The
circuit is so designed that with the use of a
suitable instrument, the readings will be practically independent of temperature. The push'pull output allows use of instruments with meter
coils of high inductance even at high frequencies. Fig. 2 shows the circuit of a tachometer/rev-counter with a full scale deflection at
6000 rpm (2 input pulses with each crankshaft
revolution).
'
I
0.25
~~o I.-
I
/4--7.62 .---l
11...15'1
7.5V
Maximum Ratings
VB, V'/3
Supply voltage ............... 9V
I.
Currents .................. -20mA
I,
average value .............. 2mA
I,
at pulse duration<0.5ms .. , 20mA
I.
at pulse duration<0.5ms ... 75mA
I,.
at pulse duration<0.5ms .. -75mA
Tamb
_
~
1~
Ambient temperature
range ........... -40 to +85°C
Fig. 2: Circuit diagram or a rev-counter for a
four-cylinder 'our-stroke engine. Full-scale deflection at 6,000 RPM. Nominal voltage of car
battery 12 V.
tofT
Recommended Operating Data
Pulse duty factor of
output voltage ............ <0.85
V1/3
Supply voltage ........... 7.5 to 8V
Timing resistor ........... 3 to 20ko
fi
Frequency of input pulses .. <10kHz
Input pulse width ........ >1.0f.tsec
8-104
SAK115
TACHOMETER INTEGRATED CIRCUIT
-
,....------_-"IV'.,-..._---<) VB
1 Vis
Itot
vi
o -Fi-1==i--"':;
-it;1I
I
1-- t
I
I
t-- T--l
I
I
o -F=t--t===--_.:.:o
~------~----------------~----<)O
Fig. 3: Measuring circuit. The duration of the input pulses must always be shorter
than the duration of the output pulses.
Measuring Conditions for Characteristics
-I-
Supply voltage(±1 %)
........ ' BV
Timing resistor (±0.1%) ...... 10k[l
Timing capacitor (±0.1 %) ... 0.47[LF
Load resistance (±0.5%) ....... 440
R
A.vo
- V
(See measuring circuit Fig. 3)
L
Load inductance (±5%) ...... BOmH
R,
Series resistance at
input (±1 %) .............. 10k[l
ccVo
Change of output voltage
for a supply voltage change of
supply volt. of ±V7/3=0.3V .. <2%
Temperature coefficient
of output voltage. <2 X 10-:1 t/"C
Vm·•s
Residual output voltage ..... <30mV
At input frequencies in the range of
fi = 25 to 250Hz:
Dependence of output voltage
on the frequency
Voltage amplitude
of input pulses (±2 %) ...... 10V
ti
Duration of
input pulses (±5%) ........ 0.5ms
f.
Frequency of
input pulses (±0.1 %) ...... 250Hz
Definitions:
Vo = Actual value of output voltage
(average value)
Characteristics at Tamb =25°C
Volin = nominal value of output voltage
(See preceeding measuring conditions.)
Itot
Supply current at Vi=O .. 12 to 22mA
Input voltage drop ...... 6.5 to BV
Duration of output
pulses ............. 2.7 to 3.1ms
Vos
Voltage amplitude of
output pulses ......... 5 to 5.BV
Vo
Output voltage
average value ......... 3.3 to 4.5V
Vomax = final value of output voltage at
fi=fi mox=250 Hz (full scale deflection)
The period of the input pulse must be smaller
than the period of the output pulse.
8-105
-I
SAY115
SPEEDOMETER INTEGRATED CIRCUIT
mm
~~-----
SEMICONDUCTORS
SPEEDOMETER INTEGRATED CIRCUIT
The SAY115 is a monolithic integrated circuit
designed for use in electronic speedometers
and odometers in automobiles and other vehicles. As shown in Fig. 1, it consists of a
Schmitt Trigger, a monostable multivibrator, a
current source for supplying a moving-coil instrument, an analog output, a binary 5 or 6
stage frequency divider with a power output
stage for direct drive of a two-coil stepping
motor. This is used for mileage or distance
indication. The analog output allows a warning
signal to be set off when the speed falls below
or exceeds pre-set limits.
SAY115X-5 stage (7 32)
:.. - ----- max. 19.55 ________ ...:
.
.'
'mtljf
~.E
.
.,--
'I
-l~
.
-i-
: __ I2?S: ~627.01J,1.31' ~: -~:
~·5.'o8+'· :',62 '·''';'''5',08'' .~
,
f
Dimensions in mm
~
~=rirr--";--R-';;'- L
SAY115Y-6 stage (7 64)
Dual In-line Plastic Package
Maximum Ratings
Vom
VOila
V,
1" I.
I,
Tamb
Ts
Supply voltage, continuous ...... 16V
Supply voltage, pulsed <5 ms ... 20V
Input voltage ........ -0.5 to +20V
Output current at the motor
terminals ................... 300mA
Output current for moving
coil instrument ............ -30mA
Ambient temperature
range .............. -40 to +85°C
Storage temperature
range ............. -40 to +125°C
RECOMMENDED OPERATION DATA
VO/13
fi
R'ill
R7/g
tp
Supply voltage ........... 11 to 16V
Input frequency ........... <10kHz
Timing resistor for
monostable ............ 15 to 100kl1
Potentiometer for cu rrent
source .................... >10011
Duty Cycle of monostable ...... <0.9
Tperiod
Cs
Rs
Filtering network ............. 330
>25uF
33n.
Fig. 1Diagram of a Speedometer
Circuit with full deflection
at F,=300 Hz
.... Stepping
Motor
Speed
Worning
8-106
SAY115
SPEEDOMETER INTEGRATED CIRCUIT
CHARACTERISTICS TA
VII.
VIH
1,
1,
=
25° C
Supply voltage ........... 11 to 16V
Quiescent Current
(without stepping motor) ..... 16mA
Input trigger thresholds
"low" ..................... 2.5V
"high" .................... 3.5V
Input Current
at V, VIH • • • • • • • • • • • • • • • • • • • =0
NOTE-The monostable will trigger on the
trailing edge of the input signal if V'Lis exceeded.
V'/13
V'113
10
t p6
V,O
V,O
Reference voltage ............ 6.5V
Current source voltage
range ..................... 0 to 5V
Instrument current,
peak value ................... 2.3V
R,/s
Output pulse period
(Pin 6) .......... 0.67 X R'/ll X Cll",
Analog output voltage D.C.
f = 0 ..................... 6.5V
f = f max , t p
-T = 0.9 ......... 2.1V
period
R"ut 10
fi/fo
V"at,
V,sat
Output resistance of
analog output ............... 10K{J
Divider ratio of binary divider
Note (1) ................ 32 or 64
Saturation voltage of motor
outputs at l,=b=200mA ....... 1.2V
NOTE (1)-Ordering Instructions:
Order SAY115X for -:- 32 (5 stage).
Order SAY115,Y for -:- 64 (6 stage).
Application Information
The speedometer SAY115 is usually driven from
the gearbox (transmission) of an automobile
vi, for example, a reed-relay contact, a proximity switch or an inductive sensor. The monostable is triggered by the trailing edge (negative
going) of the input signal and is therefore not
susceptible to contact bounce of a reed relay.
This assumes that the input signal meets trigger threshold limits shown in the data. The
pulse width of the monostable is set by RC
components R'/ll and Cll /12 and can be adapted to a wide input frequency range.
The current source output at Pin 6 is proportional to the input frequency and can be adjusted by a resistor or potentiometer, R,/s. The resistors R'/8 or R'/ll can be chosen for calibration of
the speedometer system. Due to the current
source, temperature variation of the resistance of
the moving-coil instruments do not affect the
reading. The current source is essentially thermally neutral. Thus, temperature effects are limited to the external components R'/ll, Rus and
Cll /12. Therefore, virtually all temperature drift
effects on the reading are eliminated when
the supply voltage is turned on.
One side .of the instrument is connected to
ground thus simplifying mechanical construction.
If required, a filter capacitor can be connected
to the analog output in order to generate a
d.c. voltage as a linear function of speed.
Thus by using a simple comparator, K, a warning signal can be set off when the speed
exceeds or falls below a pre-set value. For
convenience, a stabilized reference voltage is
available at pin 2 of 6.5 volts. A potentiometer
may be used and the temperature dependence
of the comparator switching point is therefore,
a function of the comparator, potentiometer,
and the RC components (R'/Il and Cll",).
The binary divider divides the input frequency
by 2' or 2" and drives an output stage consisting of two NPN Darlingtons. Both outputs
change alternately to "high" and "low" during
half periods of the output signal. Both outputs
have a freewheeling diode with a common
cathode output at Pin 4.
In order to protect the circuit from high voltage
spikes generated in an automobile electrical
system an external filter network Rs, Cs should
be used as shown. The stepping motor current
does not flow through the filter resistor, Rs,
thus allowing sure starting of the stepping
motor even under low battery voltages. The
cooling pins of the package are the ground
connection pins of the SAY115 and should be
soldered to the PC board to allow good thermal
conduction.
8-107
_
I
mm
-L..L _ _ _ __
SMALL' SIGNAL CHIPS AND WAFERS
SEMICONDUCTORS
INTRODUCTION
CROSS REFERENCE CHART
ITT has a wide selection of planar transistor chips
and wafers available for those who require devices
in this form. Since the large number of JEDEC
specifications are derived from a few chip types,
many differing applications can be satisfied with
a relatively small quantity of basic chip families.
The list of JEDEC specifications, together with
the respective chip specification, will provide a
means of ordering the proper chip required in
an application. This chart is not exhaustive, and
is provided as a guide. Specific requirements may
necessitate a different chip specification from
available JEDEC "2N" numbers. In such cases,
the accompanying list of chip parameters will
provide the necessary information.
SPECIFICATIONS
The accompanying DC parameters identifying
each family are tested on each chip in the wafer.
These are the probe speCifications. As shipped
from our factory, THE PROBE PARAMETERS ARE
GUARANTEED TO AN AQL = 2.5%.
The design parameters such as V CE(SAT)" ton, toff,
COb, etc. are not probed. These characteristics
can best be tested after the chip is suitably
mounted; and, therefore, have little significance
in chip form.
The chips will have a high yield to the specified
limits. The actual yield will vary with the mechanical techniques used to assemble the device,
and the type of package used.
ORDERING
All chips and wafers should be ordered according
to the alpha-numeric coding system referred to
in the speCification chart. The four-digit geometry
family, together with the voltage letter and DC
gain number (from the accompanying geometry
parameter chart) will completely determine the
specification which ITT will provide. A third letter
specifies in which form, chip or wafer, the product
is to be shipped.
E.G.:
Q Family
Q 1 .§-
In all cases, the lowest useable voltage and the
lowest useable hFE should be chosen in specifying chip parameters. This will provide the highest
possible yield and the most economical design.
§!.l\Q ~
C = Chi
Voltage Gain W = Wafer
IDENTIFICATION
USE
The entire wafer is manufactured with approximately 3000 A ° of gold for die attach to a suitable
substrate or base. Recommended die attach temperature for all families is 450°C, maximum. 9,000
to 12,000 angstroms of aluminum are deposited
on the chip for metalization purposes. ITT recommends aluminum wire for connection to the aluminum base and emitter bonding pads. Ultrasonic
techniques may be used for the, wire-bond operation.
All small-signal transistor dice will be identified
by the appropriate four-digit family number together with the particular classification code for
voltage and current gain.
By way of example:
PACKAGING FOR SHIPMENT
The 2N2222 is a "0018" chip. The voltage class
is "M," the current gain is "A." Therefore, when
ordering a 2N2222 in chip or wafer form, the
correct part would be a "0018MA" chip. This
method applies to dice and to a wafer which has
been tested 100%.
Chips will be shipped in appropriate containers,
with the devices packaged to protect them from
damage in shipment. Wafers will be shipped in a
similar manner. Unless otherwise specified, wafers
will not be scribed prior to shipment.
If a wafer is needed which does not require all
the chips to be tested, then the alpha-numeric
suffix will apply. For a 2N2222 device, in wafer
form, sample probe-tested only, the proper part
number will be a "0018S1."
9-1
SMALL SIGNAL CHIPS AND WAFERS
TRANSISTOR WAFER INSPECTION CRITERIA
3. Aluminum color - the aluminum may not
be dark brown or black.
MECHANICAL INSPECTION
Measure overall thickness of one (1) wafer if run
contains five (5) or less wafers. Measure two (2)
wafers if run size is greater than six (6) wafers.
Reject the run if any of the measured wafers are
not per limits specified in Table I.
4. Aluminum reduction - aluminum fingers
must be continuous along 75% of the oxide
cutout length nearest the bond pad on
metal over oxide devices. Aluminum fingers may not be reduced more than 50%
of the oxide cutout width on metal over
oxide devices, nor more than 25% in width
at an oxide step-down point. Bond pads
must not be reduced more than 25% of
their intended area. EQR rings may not be
discontinuous at more than one place.
Q.C. will 100% measure overall thickness of each
wafer in a rejected run.
VISUAL INSPECTION
Inspect ten (10) randomly selected devices on
each wafer with no more than three (3) die in any
one quadrent using 100X magnification.
5. Oxide holes-silicon may not be exposed
within .0002 in. of any junction.
6. Mask misalignment - the outline of one
oxide mask definition may not cross over
the outline of another mask definition.
Aluminum mask outlines must cover more
than 50% of the intended oxide cutouts.
TABLE I
UNAIDED EYE INSPECTION
1. Backside gold - the backside gold must
cover 90% of the wafer surface. The gold
must exhibit a gold, orange, or yellow cast.
The gold must show no evidence of peeling or blistering.
Microscope Inspection (ll1DX) -
TijANSISTDR DIE INSPECTION CRITERIA
Inspect per Table II using 100X to combined 2.5%
AQL.
TABLE II
Combined 1:0% AQL
1. Aluminum bridging-the base metal, emitter metal, and EQR ring metal may not be
connected or bridged by unetched or
smeared aluminum.
1. Broken die - broken corners, edges, or
shell chips may not extend closer thai1
.001" to a junction or bond pad.
2. Cracks-cracks which are not terminated
at each end at the periphery of the die
may not extend toward a junction or bond
pad.
2. Aluminum adherance-the aluminum may
show no evidence of peeling, blistering,
or flaking.
9-2
ITT
----MPS-A05
NPN SI LICON AUDIO TRANSISTORS
SEMICONDUCTORS
Package: To-92
NPN SILICON AUDIO TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage ........
60
Collector-Base Voltage .............
60
Vdc
Vdc
Emitter-Base Voltage ..............
4.0
Vdc
Collector Current - Co'ntinuous
500
MAde
T A = 25 0 C .....................
500
mW
Derate above 25 0 C ............
4.54
Total Device Dissipation
@
Total Device Dissipation
@ TC
= 25 0 C
.....................
800
Derate above 25 0 C ... ..... ....
7.27
mW
Operating and Storage Junction
Temperature Range ............ -55 to +135
Thermal Resistance, Junction
to Case .............................. .
0.137
°C/mW
0.220
°C/mW
Thermal Resistance, Junction
to Ambient ......................... .
•
ELECTRICAL CHARACTERISTICS ITA = 25 0 C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
BV CEO
60
-
-
Vdc
BV EBO
4.0
-
-
ICBO
-
-
100
-
-
hFE
VCE(sat)
VBE(sat)
VBE(on)
fT
Cob
Cib
50
125
50
150
-
90
-
0.08
Conditions
IC
= 1.0 mAde, IB = 0
Vdc
IE
nAdc
V CB
= 100uAdc, IC = 0
= 60 Vdc, IE 0
IC - 10 mAde, V CE- 1.0 Vdc
IC
= 100 mAde, VCE = 1.0 Vdc
= 350 mAde, V CE = 1.0 Vdc
IC
= 100 mAde, IB -
IC
0.25
Vdc
0.75
IC - 100 mAde, IB
10 mAde
10 mAde
-
0.7
1.2
Vdc
50
200
-
MHz
-
6.0
-
pF
= 100 mAde, V CE = 1.0 Vdc
IC = 100 mAde, V CE - 1.0 Vdc,
f = 100 MHz
V CB = 10 Vdc, IE = 0, f = 100 kHz
15
-
pF
V BE - 0.5 Vdc, IC - 0, f - 100 kHz
9-3
IC
MPS-Al0
ITT
-----.
GENERAL PURPOSE NPN
SILICON AMPLIFIER TRANSISTORS
.
SEMICONDUCTORS
Package: To-92
NPN SILICON GENERAL PURPOSE
AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage ............................ 40 Vdc
Emitter-Base Voltage ................................... 4.0 Vdc
Collector Current - Continuous ............... 100 mAde
Total Device Dissipation
@
T A = 250 C ........ 300 mW
Derate above 25 0 C .......................... 2.73 mW/oC
Operating and Storage Junction
Temperature Range ..................... -55 to +135
0c
Thermal Resistance, Junction
to Ambient ................................... 0.367 0C/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise. noted)
Symbol
Min
Max
Unit
BV CEO
40
-
Vdc
BV EBO
4.0
-
Vdc
IE - 100 uAdc, IC = 0
ICBO
-
100
nAdc
V CB =30Vdc,I E -0
400
-
IC - 5.0 mAde, V CE - 10 Vdc
-
MHz
IC - 5.0 mAde, V CE = 10 Vdc, f - 20 MHz
4.0
pF
V CB = 10 Vdc, IE - 0, f - 100 kHz
hFE
40
fT
50
Cob
-
-
Conditions
IC = 1.0 mAde, IB = 0
Figure 1-Simplified AC Equivalent Circuit (Common Emitter!
BASE
COLLECTOR
'b
(hfe+l)re
9-4
__ I
mm
MPS-A20, MPS-K20, MPS-K21, MPS-K22
_L_L
___________N_P_N__SI_L_IC_O_N__A_M_P_L_IF_I_E_R_T_R_A_N_S_IS_T_O_R...S
SEMICONDUCTORS
Package: TO-92
NPN SILICON AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage _............................ 40 Vdc
Emitter-Base Voltage ................................... 4.0 Vdc
Collector Current - Continuous ................. 1 00 mAdc
Total Device Dissipation @ T A = 25 0 e ........ 300 mW
Derate above 25 0 C ......................... 2.73 mW/oe
Operating and Storage Junction
Temperature Range ..................... -55 to +135 0e
Thermal Resistance, Junction
to Ambient ................................... 0.367 oe/mW
ELECTRICAL CHARACTERISTICS (T A
= 25 0 e
unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO
40
-
Vdc
Ie = 1.0 mAde, I B = 0
BV EBO
4.0
Vdc
leBO
-
100
nAdc
40
400
-
IE 100uAdc,I C 0
V CB - 30 Vdc, IE 0
IC 5.0 mAde, V CE 10 Vdc
-
0.25
hFE
Conditions
VCE(sat)
fT
Vdc
IC - 10 mAde, IB - 1.0 mAde
125
-
MHz
Cob
-
4.0
pF
Ie 5.0 mAde, V CE 10 Vdc, f 100 MHz
V CB " 10 Vdc, IE - 0, f - 100 kHz
Figure 1-Simplified AC Equivalent Circuit (Common Emitter)
BASE
'b
(hIe
+ Ilre
9-5
ITT
-
MPS-A55
PNP SILICON AMPLIFIER TRANSISTOR
SEMICONDUCTORS ------~
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage .......
60
Collector-Base Voltage ............
60
Vdc
Vdc
Emitter-Base Voltage ...............
4.0
Vdc
Collector Current - Continuous
500
mAdc
Total Device Dissipation
@T A = 25 0 C ......................
500
mW
Derate above 25 0 C .............
4.54
mW/oC
Total Device Dissipation
@TC =25 0 C ......................
800
mW
...........
7.27
mW/oC
Derate above 25 0 C
Operating and Storage Junction
°c
Temperature Range ............... -55 to +135
Thermal Resistance, Junction
to Case ..................................
0.137
°C/mW
0.220
°C/mW
Thermal Resistance, Junction
to Ambient ...........................
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
BV CEO
60
BV EBO '
4.u
Typ
-,
ICBO
hFE
VCE(sat)-
Max
Unit
-
Vde
IC = 1.0 mAde, I B = 0
Vde
l.OU
nAde
IE = 100uAde,I C = 0
VCS = 60 Vde,I E 0
50
150
50
125
-
-
80
-
-
0.09
VBE(sat)
0.71i
VSE(on)
tT
0.13
cU
10u
-
6.5
Conditions
IC = 10 mAde, V CE - 1.0 Vde
IC = 100 mAde, V CE '= 1.0 Vde
IC = 350 mAde, V CE ='1.0 Vde
0.25
1.2
Vde
IC = 100 mAde, IS - 10 mAde
Vde
IC - 100 mAde, IS = 10 mAde
Vde
IC = 100 mAde, V CE - 1.0 Vde
MHz
IC -100 mAde, VCE - 1.0 Vde,
pF
V CB = 10 Vde, IE = O,f
100 kHz
pF
VSE = 0.5 Vde, IC
0, f
100 kHz
f=100MHz
Cob
C ib
-
20
9-6 '
MPS-A70
GENERAL PURPOSE
PNP SI LICON AMPLIFIER TRANSISTORS
ITT
----......---SEMICONDUCTORS
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Collector-Emitter Voltage ............................ 40 Vdc
Emitter-Base Voltage .................................... 4.0 Vdc
Collector Current - Continuous ................. 100 mAde
Total Device Dissipation
Derate above
250 C
@
T A = 250 C......... 300 mW
......................... 2.73 mW/oC
Operating and Storage Junction
Temperature Range .................... -55 to +135
0c
Thermal Resistance, Junction
to Ambient ............... ~ ................... 0.367 oC/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO
40
-
Vdc
BV EBO
4.0
-
Vdc
ICBO
-
100
nAdc
40
400
-
-
0.25
hFE
Vdc
VCE(sat)
fT
125
-
MHz
Cob
-
4.0
pF
Conditions
= 1.0 mAde, I B =0
IE = 100 uAdc, IC =0
V CB - 30 Vdc, IE =0
Ie =5.0 mAde, V CE = 10 Vdc
IC = 10 mAde, 18 = 1.0 mAde
Ie =5.0 mAde, VeE = 10 Vdc, f - 100 MHz
V CB - 10 Vdc, IE =0, f = 100 kHz
IC
Figure 1-Simplified AC Equivalent Circuit (Common Emitter)
COLLECTOR
(hfe
+ l}re
9-7
ITT
-
MPS706, MPS706A
HtGH-SPEED NPN SI LICON
LOW-LEVEL SWITCHING TRANSISTORS
.
SEMICONDUCTORS
.---~~
Package: To-92
NPN SILICON HIGH-SPEED
LOW-LEVEL SWITCHING
TRANSISTORS
A
P ...IU VOlt.
~70 V
a '11_
MPS706
I MPS706A
Figure 1 - Switch!ng Time Test Circuit
20
Vdc
Vdc
25
Emitter-Base Voltage
3.0
~o O"'m_
Z.OI!
O---'l.IVV-'lN'v--tI
-
Unit
Collector-E mitter Voltage
(R BE = 10 Ohms)
Collector-Base Voltage
-
-2.0'11
ABSOLUTE MAXIMUM RATINGS
Characteristic
-
I"t.rnol ResI.tonCt
I
5.0
Vde
Total Device Dissipation
= 25 0 C
310
mW
Derate above 25 u C
2.81
mW/oC
@T A
PulMVOIt,
Intung! Rtsl"onct
50 Ohm,
350
Operating and Storage Junction
Temperature Range
I
oC
-55 to +135
Figure 2 - Storage Time Test Circuit
I
ELECTRICAL CHARACTERISTICS (T
A
= 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
BV CER
15
Vdc
20
-
Vdeq
IC - 10 mAde, RBE - 10 Ohms
I CBO
-
0.5
uAde
lEBO
-
10
uAde
V CB -15Vde,I E -0
V EB - 3.0 Vde, IC - 0
hFE"
20
-
-
Conditions
IC
= 10 mAde, IB = 0
IC - 10 mAde, V CE
= 1.0 Vde
MPS706
20
60
-
0.6
Vde
IC
-
0.9
Vde
IC - 10 mAde, IB - 1.0 mAde
0.7
0.9
200
-
MHz
IC
Cob
-
6.0
pF
V CB - 10 Vde, IE
rb
t
on**
-
50
Ohms
IE - 10 mAde, V CE - 15 Vde~ f - 300 MHz
-
40
ns
Turn-On Time See Figure 1
75
ns
Turn-Off Time See Figure 1
-
60
ns
Charge Storage Time Constant "* See Figure 2
-
25
V CE (sat)"
V BE (sat) "
MPS706A
= 10 mAde, IB = 1.0 mAde
MPS706
fT
toff" *
T S **
MPS706A
= 10 mAde, V CE = 15 Vde, f = 100 MHz
=0, f
- 100 kHz
MPS706
MPS706A
'Pulse Test: Pulse Width === 12 ns, Duty CYCle£ 2.0%.
"Measured with Tektronix Type R Plug-In (50-Ohm Internal Impedance) and circuits shown.
9-8
ITT
-
MPS834
HIGH-SPEED NPN SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS '---~~
Package: To-92
NPN SILICON HIGH-SPEED
SWITCHING TRANSISTORS
50
ABSOLUTE MAXIMUM RATINGS
Characteristic
5.0
II;
Figure 1 - Turn-On and Turn·Off
Unit
Time Measurement Circuit
Collector·Emitter Voltage ............................. 30 Vdc
Coliector·Base Voltage ................................. 40 Vdc
+'0 Vdc
Emitter·Base Voltage ................................... 5.0 Vdc
Collector Current .................................... 200 mAdc
Total Device Dissipation @ T A = 25°C ........ 310 mW
Derate above 25°C ......................... 2.81 mW/oC
Totql Device Dissipation @ T C = 25°C ........ 500 mW
Derate above 250C ......................... 4.55 mW/oC
Operating and Storage Junctjon
Temperature Range .................... ·55 to
+ 1350C
Figure 2 - Charge Storage Time
Constant Measurement Circuit
ELECTRICAL CHARACTERISTICS (T A = 25 0 e unless otherwise noted)
Symbol
Min
Max
Unit
BV CBO
40
-
Vdc
BV EBO
5.0
Vdc
IE
ICES
-
10
uAde
V CE - ;j0 Vde, V BE
-
0.5
uAde
V CB - 20 Vde, IE
IC
IU mACc, VCE
0.25
Vde
IC
IU mACc, IB
IC bO mAdc, IB b.U mAde
IC - 10 mAde, IB - 1.0 mAdc
ICBO
h FE *
25
V CE(sat)*
V BElsat)*
Conditions
IC = 10uAdc, IE = 0
-
0.4
-
0.9
Vdc
luuAac,I C
U
0
0
1.0 Vdc
1.U mAde
-
MHz
IC - 10 mAde, V CE - 20 Vdc, f - 100 MHz
Cob
-
4.0
pF.
V CB - 10 Vde, IE - 0, f - 100 kHz
ton
-
16
ns
Turn·On Time IC - 10 mAdc, IBl - ;j.O mAde,
toff
-
30
ns
Turn·Off Time Ie - 10 mAde, IBl
t
-
25
ns
Storage Time IC
fT
350
I B2 = 1.0 mAdc See Figure 1
3.0 mAdc,
I B2 = 1.0 mAde See Figure 1
s
See Figure 2
·Pulse Test: Pulse Width ~ 12 ns, Duty Cycle.~ 2.0%.
9-9
10 mAde, IBl
IB2 = 10 mAde
I
_
mm
MPS2369
.L.L __H_IG_H_-_S_PE_E_D_N_PN_S_IL_IC_O_N_S_W_IT_C_H_I_N_G_T_R_A_N_S_IS_T_O_R
SEMICONDUCTORS
Package: To-92
+'006~l"
NPN HIGH-SPEED
SWITCHING
TRANSISTORS
_1.5V
3.0V
,,
270
~
Ji
-1
_1_
'ies· >4.0pf
I
<1.0".
--'
pULSE WIDTH (l1)=300n,
DUTY CYCLE
=2.0%
Figure 1 - ton Circuit
-1"\-
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Collector-Emitter Voltage ........................... 15 Vde
Collector-Emitter Voltage ........................... 40 Vde
Collector-Base Voltage ................................ 40 Vde
tlO':Tb
I
3.0V
-4.15-V--
,,
270
_1_
,T, •
,CS >4.001
I
3-3'
_<1.0ns
--'
=
PULSE WIDTH ell) 300n,
DUTY CYCLE
= 2.0%
Emitter-Base Voltage ................................... 4.5 Vde
Figure 2 - toff Circuit
Collector Current-Peak ........................... 500 mAde
Total Device Dissipation
@T A = 25 0C .......................................... 310 mW
Derate above 250 C ._ ........................ 2.81 mW/oC
Operating and Storage Junction
"':hcj'-I~-- >'OV~9"",80v-l
-4Qv
3.QpF
,
__J
Temperature Range .................... -55 to +135 0c
PULSE WIDTH (t,) =300"s
DUTY CYCLE
=20 %
-Tatallhunt capacitance at test jill Qnd connectors
Thermal Resistance, Junction
to Ambient ................................... 0.355 0C/mW
Figure 3 -: Storage Test Circuit
ELECTRICAL CHARACTERISTICS (T A = 25 0C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
BV CES
15
Vde
IC = 10 mAde,l B = 0
40
Vde
IC -10uAde,V BE =0
BV CBO
40
Vde
BV EBO
4.5
-
IC = 10uAde,I E = 0
I E =10uAde,I C =0
ICBO
hFE*
VCElsat)
VBE(sat)*
Cob
hfe
-
0.4
-
30
40
120
20
-
20
-
0.70
0.25
0.85
Conditions
Vde
uAde
V CB = 20 Vde, IE -.0
V CB - 20 Vde, IE = 0, T A = 1250C
-
IC = 10 mAde, V CE = 1.0 Vde
IC - 10 mAde, V CE - 1.0 Vde, T A - 55 0 C
IC - 100 mAde, V CE - 2.0 Vde
Vde
Ie = 10 mAde, IB = 1.0 mAde
Vde
IC = 10 mAde, lR - 1.0 mAde
pF
V CB = 5.0Vde,I E = 0, f= 140kHz
-
4.0
5.0
-
-
IC = 10 mAde, VCE = 10 Vde, f = 100 MHz
12
ns
V CC = 3.0 Vde, V BE (off) = 1.5 Vde,
18
ns
V CC = 3.0 Vde, IC = 10 mAde, IB1 = 3.0 mAde,
13
ns
ton
IC = 10 mAde, IB1 = ~.O mAde Figure 1
toff
-
182 = 1.5 mAde Figure 2
t
s
IB1 = IB2 = IC = 10 mAde Figure 3
·Pulse Test: Pulse Width = 300 us, Duty Cycle = 2.0%.
9-10
MPS2711, MPS2712
ITT
----LOW-POWER NPN
51 LICON SMALL-SIGNAL TRANSISTOR
Package: To-92
SEMICONDUCTORS
NPN SILICON LOW-POWER
SMALL-SIGNAL TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage ............................. 18 Vdc
Collector-Base Voltage ................................. 18 Vdc
Emitter-Base Voltage ................................... 5.0 Vdc
Collector Current ..................................... 100 mAdc
Total Device Dissipation @T A = 25 0 C ........ ~10 mW
Total Device Dissipation @T C = 600C ........ 210 mW
Operating Junction Temperature ................. 135 0C
Storage Temperature Range ............. -55 to +135 0C
Thermal Resistance, Junction
to Ambient ....................................... 0:357 0C/W
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Svmbol
Min
Max
Unit
ICBO
-
0.5
uAdc
-
1.5
lEBO
-
0.5
uAdc
V EB
hFE
30
90
-
VCE
75
225
-
4.0
pF
V CB
30
120
-
V CE - 10 Vdc, IC = 2 mAdc, f - 1 kHz
80
200
Conditions
V CB =18Vdc,I E =0
V CB = 18 Vdc, IE - 0, T A -100 o C
= 5 Vdc, IC =; 0
= 4.5 Vdc, IC = 2 mAdc
MPS2711
Cob
hfe
MPS2712
= 10 V, IE = 0 f = 1 MHz
MPS2711
MPS2712
9-11
MPS2713, MPS2714
GENERAL PURPOSE LOW-LEVEL NPN SILICON SWITCHING TRANSISTOR
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Base Voltage ..... _..... __ . __ .. _.... _..... __ .. 18 Vdc
Collector-Emitter Voltage __________ . _________________ . 18 Vdc
Emitter-Base Voltage ______________ . ___________________ . 5_0 Vdc
Collector Current ______________ . _________ . __________ . 200 mAdc
Total Device Dissipation @ T A = 600 C _______ . 210 mW
Total Device Dissipation @T
A= 250 C ________ 310 mW
Derate above 250 C _________ . _____________ . 2.81 mW/oC
Thermal Resistance, Junction
to Ambient _________________ . _______ ._. ______ . 0.357 0C/mW
Junction Operating Temperature _________ ._. _____ 135 DC
Storage Temperature Range ____ . _______ . -55 to +135 DC
ELECTRICAL CHARACTERISTICS (TA = 25 0C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
ICBO
-
-
0.5
uAdc
lEBO
-
-
0_5
hFE
30
60
90
IC
75
150
225
MPS2714
VCE/sat)
-
0.16
0.3
Vdc
VBE/sat)
hfe
0.6
;:su
0.75
1.3
Vdc
-
15
Conditions
V CB
V CB
uAdc
= 18 Vdc, IE = 0
18 Vdc, IE - 0, T A - 1000 C
=0
= 2 mAdc, V CE - 4.5 Vdc
V EB - 5 Vdc, IC
MPS2713
80
fT
-
-
Cob
2.5
300
-
= 3 mAdc
~;:s
mAdc
IC 2 mAdc, V CE - 4.5 Vdc,f
MPS2713
.1:lU
250
IC - 50 mAdc,l B
IC '50 mAdc, IB
1 kHz
MPS2714
= 10 mAdc, V CE
MHz
IC
pF
V CB
ohms
IC 0.5 mAdc, V CE . 1 Vdc, f 1 kHz
Delay Time IC - 10 mA, IB1 3mA,
10 Vdc, IE
- 10 Vdc, f - 100 MHz
0, f - 100 kHz
hie
3000
td
7_0
ns
\
6.0
ns
Rise Time· V CC
10V
ts
tf
I'"
ns
Storage Time IC
10 mA, IB1
l:1.U
ns
Fall Time
9-12
I B2 - 1 mA, V CC
3mA,
= 10 V
MPS2923 THRU MPS2925
GENERAL PURPOSE NPN SI LICON AMPLIFIER TRANSISTORS
Package: T 0-92
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Base Voltage ................................. 25 Vdc
Collector-Emitter Voltage ........................... 25 Vdc
Emitter-Base Voltage .................................. 5.0 Vdc
Collector dc Current ................................. 100 mAdc
Total Device Dissipation ............................. 200 mW
@ 250 C Ambient Temperature
Derating Factor above 250 C ........... 2.67 mW/oC
Total Device Dissipation ............................. 120 mW
@ 55 0 C Ambient Temperature
Derating Factor above 25 0 C ........... 2.67 mW/oC
Junction Temperature-Operating ................. 100 0C
Storage Temperature Range ............. -30 to +125 0C
ELECTRICAL CHARACTERISTICS (Tc = 250 C unless otherwise noted)
Symbol
ICBO
lEBO
hfe
Cob
Min
Max
Unit
-
0.5
uA
Conditions
15
uA
V CB =25V,I E =0
V CB - 25 V,I E - 0, T A - 1000C
0.5
uA
V EB - 5 V
-
V CE -10V,I C -2mA
90
180
MPS2923
150
300
MPS2924
235
470
-
12
MPS2925
pF
V CB - 10 V, IE = 0, f - MHz
9-13
•
MPS2926, MPS3721
Package: To-92
GENERAL PURPOSE NPN SI LICON TRANSISTOR
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage .............................. 18 Vdc
Collector-Base Voltage .................................. 18 Vdc
Emitter-Base Voltage ................................... 5.0 Vdc
Collector Current ..................................... 100 mAdc
Total Device Dissipation
@
25 0 C Ambient Temperature .............. 310 mW
Total Device Dissipation
@
600 C Ambient Temperature .............. 210 mW
Thermal Resistance, JU[lction
to Ambient ................................... 0.357 0C/mW
Junction Temperature, Operating ................. 135 0c
Storage Temperature Range ............. -55 to +135
0c
ELECTRICAL CHARACTERISTICS (T A = 25 0 Cunless otherwise noted)
Symbol
Min
Typ
Max
Unit
ICBO
-
-
0.5
uA
15
lEBO
fT
Cob
hfe
-
300
-
35
60
V CB - 18 Vdc, IE
0, TA
1000 C
0.5
uA
V EB
-
MHz
3.5
pF
IC - 4 mA, ".CE- 5 V MPS 2926
V CB - 10 V, IE - 0, f - 1 MHz
VCE 10 V, IC 2mA,f 1 kHz
MPS2926
470
-
Conditions
V CB =18Vdc,I E =0
'660
5 Vdc, IC - 0
MPS3721
9-14
ITT
----MPS3392 thru MPS3395
NPN SILICON SMALL-SIGNAL AUDIO TRANSISTOR
SEMICONDUCTORS
Package: To-92
NPN SILICON SMALL-SIGNAL
AUDIO TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage ._.._._._._.._.._._. .. _. .. _.. 25 Vdc
Collector-Base Voltage .................... _. ............ 25 Vdc
Emitter-Base Voltage ................................. _. 5.0 Vdc
Collector Current ................................... _. 100 mAdc
@ T A = 25 0 C ........ 310 mW
Total Device Dissipation
Total Device Dissipation @ T C = 60 0C ........ 210 mW
Operating Junction Temperature .................. 135 0C
Storage Temperature Range .............. -55 to +135 0C
Thermal Resistance, Junction
to Ambient ............................... _. .. 0.357 0C/mW
•
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Min
BV CEO
I CBO
25
-
Vdc
IC = 1 mAdc, I B = 0
-
0.1
uAdc
V CB - 18 Vdc, IE - 0
0.1
uAdc
V EB
150
300
-
V CE - 4.5 Vdc, IC - 2 mAdc
90
180
MPS3393
MPS3394
lEBO
hFE
Max
I
Symbol
Unit
Conditions
5 Vdc, IC
0
MPS3392
Cob
hfe
55
110
150
500
-
3.5
pF
V CB =10V,I E =0,f=1MHz
150
500
-
V CE - 4.5 V, IC - 2 mA, f - 1 kHz
90
400
55
300
MPS3394
150
800
MPS3395
MPS3395
MPS3392
MPS3393
9-15
MPS3638,MPS3638A
PNP SILICON TRANSISTOR
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Figure 1
Collector-Emitter Voltage ............................. 25 Vde
Collector-Emitter Voltage .............................. 25 Vde
"cc=.-rov
Collector-Base Voltage................................... 25 Vde
Emitter-Base Voltage .................................. 4.0 Vde
30.!l
IS
Collector Current ..................................... 500 mAde
"'out
Total Device Dissipation @T A = 250 C ........ 310 mW
To Sgmplmg Scope
Rise Time < I ns
lin ~IOOK
Derate above 25 0 C ......................... 2.S1 mW/oC
Operating and Storage Junction
Temperature Range .................... -55 to +135
0c
Thermal Resistance, Junction
to Ambient ................................... 0.357 oC/mW
ELECTRICAL CHARACTERISTICS (TA = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
BV CES
25
-
Vde
I C = 10 mAde, I B = 0
25
-
Vde
BV CBO
25
-
Vde
IC -100 uAde, V BE - 0
IC - 100uAde, IE - 0
BV EBO
4.0
ICES
-
0.035
IB
-
0.035
h FE *
SO
-
20
-
100
-
-
Vde
IE - 100uAde, IC = 0
uAde
VCE - 15 Vde, V BE = 0
VCE 15 Vde, V BE 0, T A - 65 0 C
uAde
VCE - 15 Vde, V BE - 0
I C -1 mAde,V CE =10Vde
2.0
V CE(sat)*
VBE (sat) *
fT
Conditions
-
MPS363SA
10 mAde, V CE - 10 V de MPS3638
IC
MPS363SA
30
-
IC = 50 mAde, V CE = 1 Vde
100
-
MPS363SA
·20
-
IC = 300 mAde, V CE = 2 Vde MPS3638
20
-
MPS3638A
-
0.25
-
1.0
-
1.1
O.SO
2.0
100
-
Vde
MPS3638
IC - 50 mAde, IB - 2.5 mAde
IC - 300 mAde, I B - 30 mAde
Vdeq
IC - 50 mAde, I B - 2.5 mAde
IC - 300 mAde, IB - 30 mAde
MHz
V CE - 3 Vde, IC - 50 mAde, f
MHz
MPS3638
Cob
150
-
-
20
-
10
MPS363SA
pF
V CB - 10 Vde, IE - 0, f - 140 kHz
MPS3638
MPS363SA
9-16
MPS3638, MPS3638A
ELECTRICAL CHARACTERISTICS T A = 25°C unless otherwise specified
SYMBOL
Cib
MIN
-
MAX
65
UNIT
CONDITIONS
pF
VCE
= 0.5 Vde, Ie = 0, f = 140 kHz
MPS3638
hfe
-
25
25
180
MPS3638A
-
Ie
= 10 mAde, VeE = 10 Vde, F = 1.0 kHz
MPS3638
hoe
hie
100
-
-
1.2
1500
-
2000
-
26
MPS3638A
= 1.0 kHz
mmhos
Ie - 10 mAde, VeE - 10 Vde, f
Ohms
Ie -10 mAde, VeE -10 Vde, f - 1.0 kHz
MPS3638
h re
MPS3638A
X10-4
Ie -10 mAde, VCE -10Vde, f - 1.0 kHz
MPS3638
td
\
\
tf
ton
toff
-
15
20
MPS3638A
ns
Delay Time Vee - 10 Vde, Ie - 300 mAde,
70
ns
Rise Time
140
ns
Storage Time Vee
IB1 - 30 mAde, VBE(off) - 3.1 Vde
10 Vde, Ie 300 mAde,
-
70
ns
Fall Time
75
ns
Turn-On Time Ie - 300 mAde, IB1 - 30 mAde
-
170
ns
Turn-Off Time Ie
IB2
*Pulse Test: Pulse Width - 300 us; Duty Cycle - 1%.
9-17
IB1 - 30 mAde, IB2
= 30 mAde
300 mAde, I B 1
30 mAde
30 mAde,
_
I
MPS3693
GENERAL PURPOSE NPN,
mm
.L.L _______
SI_L_IC_O_N_R_FA_M_PL_I_F_IE_R_T_R_A_N_S_IS_T_O_R_S
Package: To-92
SEMICONDUCTORS
NPN SILICON GENERAL PURPOSE
RF AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Unit
Collector-Emitter Voltage ........................... 45 Vdc
Collector-Base Voltage ................................ 45 Vdc
Emitter-Base Voltage .................................... 4.0 Vdc
Total Device Dissipation
@
T A = 250 C ........• 310 mW
Derate above 25 0 C ......................... 2.81 mW/oC
Operating and Storage Junction
Temperature Range ................... -55 to +135 0c
Thermal Resistance, Junction
to Ambient ........•.•........................ 0.357 oC/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
BV CEOJsus) *
BV CBO
45
-
-
Vdc
I C =10mAdc,I B =0
Conditions
45
-
-
Vdc
BV EBO
4.0
Vdc
IC = 100UAdc,I E = 0
IE = 10uAdc,I C -0
ICBO
-
-
50
nAdc
V CB = 35 Vdc, IE = 0
5.0
uAdc
V CB - 35 Vdc, IE - 0, T A = 65°C
hFE
40
-
160
-
IC - 10 mAde,
fT
200
-
-
MHz
v CE
= 10 Vctc
IC = 10 mAde, VCE = 15 Vdc,
f=100MHz
Cob
r' C
b c
-
-
3.5
pF
-
55
ps
V CB - 10 Vdc, IE = 0, f = 100 kHz
IE - 10 mAde, V CB - 15 Vdc,
f = 31.8 MHz
NF
-
4.0
-
dB
IC = 3.0 mAde, V CE = 10 Vdc,
RS = 300 ohms, f = 1.0 MHz
·Pulse Test: Pulse Width ~ 300 us; Duty Cycle ~ 1.0%.
9-18
MPS3702, MPS3703
LOW-POWER PNP SILICON TRANSISTORS
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristics
MPS3702
MPS3703 Unit
Collector-Emitter Voltage ...... 25
30
Vdc
Collector-Base Voltage ........... 40
50
Vdc
5.0
200
Emitter-Base Voltage .............
Collector Current - Continuous
Vdc
mAdc
Total Device Dissipation
@, 25°C Case Temperature ............ 8
W
Operating and Storage Junction
Temperature Range ........... -55 to +135
0C
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
25
-
Vdc
Conditions
30
Vdc
IC = 100uAdc, IE = 0
IC = 10 mAde, IB = 0
MPS3702
BV CBO
40
50
-
BV EBO
5.0
-
Vdc
ICBO
100
nAdc
IE = 100uAdc,I C = 0
V CB -20Vdc,I E =0
lEBO
100
nAdc
V BE = 3 Vdc, IC - u
-
IC - 50 mAde, V CE = 5 Vdc
Vdc
IC - 50 mAde, IB = 5 mAdc
MPS3702
MPS3702
MPS3703
MI'S31U:.!
60
300
30
150
VCElsat)*
-
0.25
VBElon)*
fT
0.6
1.0
Vdc
IC
100
-
MHz
IC = 50 mAdc, VCE - 5 Vdc, f - 20 MHz
Cob
-
12
pF
V CB = 10Vdc,f-1 MHz
h FE *
MPS3703
'Pulse Test: Pulse Width = 300 us: Duty Cycle = 2%.
9-19
= 50 mAde, VCE
= 5 Vdc
I
•
mm
I
_ . -L-L ______
MPS3704, MPS3705, MPS3706
L_O_W_-P_O_W_E_R_N_PN
.....
S_IL_IC_O_N_T_R_A_N_S_IS_T_O_R_S
SEMICONDUCTORS
Package: To-92
NPN SILICON LOW-POWER TRANSISTORS
Cha racter istics
Collector-Emitter Voltage ...
30
20
Vdc
Collector-Base Voltage ...... .
50
40
Vdc
Emitter-Base Voltage ......... .
5.0
Vdc
Collector Current - Continuous
600
mAde
Total Device Dissipation
@T A = 25 0 C .................
310
mW
Derate above 25 0 C .........
2.81
mW/oC
Operating and Storage Junction
Temperature Range ........
°c
-55 to +135
Thermal Resistanct, Junction
to Ambient .....................
0.357
oC/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
30
-
Vdc
30
-
BV CBO
20
-
50
-
50
-
Conditions
I C = 10 mAde, IE = 0
MPS3706
Vdc
IC = 100uAdc, IE
=0
MPS3706
40
-
5.0
-
Vdc
IE = 100 uAdc, IC = 0
ICBO
-
100
nAdc
lEBO
-
100
nAdc
V CB -20Vdc,I E =0
V BE = 3 Vdc, IC = 0
hFE *
100
300
-
IC = 50 mAde, V CE = 2 Vdc
50
150
30
600
-
0.6
-
0.8
-
1.0
0.5
1.0
VBE(on)*
fT
100
Cob
-
12
MPS3704
MPS3705
BV EBO
VCE(sat)*
MPS3704
MPS370b
MPS3704
MPS3705
MPS3706
Vdc
IC = 100 mAde, IB = 5mAdc
MPS3704
MPS3705
MPS3706
Vdc
IC - 100 mAde, V CE - 2 Vdc
MHz
IC 50 mAoc, VCE 2 Vdc, f 20MHz
V CB - 10 Vdc, IE - 0, f - 1 MHz
pF
*Pulse Test: Pulse Width = 300 us; Duty Cycle = 2%.
9-20
MPS3707 thru MPS3711
GENERAL PURPOSE NPN
SILICON AMPLIFIER TRANSISTOR
ITT- - - - -
-
Package: To-92
SEMICONDUCTORS
NPN SILICON GENERAL PURPOSE
AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Unit
Characteristics
Collector-Emitter Voltage ............................ 30 Vdc
Collector-Base Voltage ................................. , 30 Vdc
Emitter-Base Voltage ................................... 6.0 Vdc
Collector Current ....................................... 30 mAde
= 25 0 C .......
= 60 0 C : ......
310 mW
Operating Junction Temperature ................
135 0 C
Total Device Dissipation
@
TA
Total Device Dissipation
@
TC
210 mW
Storage Temperature Range ............. -55 to +135 °C
Thermal Resistance, Junction
to Ambient ...................................... 0.357 °C/W
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO
30
-
Vde
IC
100
nAdc
ICBO
Conditions
= 1 mAde,
IB
=0
lEBO
-
100
nAde
V CB -20Vde,I E -0
V EB - 6 Vdc, IC - 0
hFE
100
400
-
IC- 100uAde, VCE - 5 Vde
MPS3707
45
660
IC - 1 mAde, V CE - 5 Vde
MPS3708
45
165
90
330
MPS3710
180
660
MPS3711
MPS3709
VCE(sat)
V BE
-
1.0
Vde
IC
0.5
1.0
Vdc
IC - 1 mAde, VCE - 5 Vde
hFE
100
550
-
= 10 mAde,
IB
= 0.5
mAde
Ie -100uAdc, VCE - 5 Vde, f -1 kHz
MPS3707
45
800
IC
= 1 mAde, V CE = 5 Vde, f = 1 kHz
MPS3708
NF
45
250
MPS3709
90
450
MPS3710
180
800
~
5.0
MPS3711
dB
= 5 V,
= 5 kD,
= 100uA,
VCE
IC
RG
Noise Bandwidth
MPS3707
= 15.7 kHz
Note 1
Note 1 Average Noise Figure is measured in an amplifier with low frequency response down 3 dB at 10 Hz.
9-21
MPS5172
GENERAL PURPOSE NPN
SILICON AMPLIFIER TRANSISTOR
ITT
----SEMICONDUCTORS
Package: To-92
NPN SILICON GENERAL PURPOSE
AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Unit
Characteristics
COllector-Emitter Voltage ............................ 25 Vdc
Collector-Sase Voltage ................................ 25 Vdc
Emitter-Sase Voltage ................................... 5.0 Vdc
Collector Current - Continuous ................ 100 mAde
Total Device Dissipation
@
T A = 25 0 C ........ 210 mW
Derate above 25 0 C .......................... 1.91 mW/oC
Operating and Storage Junction
Temperature Range ................... -55 to +135
0c
Thermal Resistance, Junction
to Ambient.. ................................... 0.524 oC/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
BV CEO
25
-
-
Vde
I C -l0mAdc,I S =0
ICES
-
-
100
nAde
-
-
100
nAde
VCE - 25 Vde, V SE - 0
V CS =25Vdc,I E =0
-
-
10
uAdc
VCS - 25 Vde, IE - 0, TA - 1000 C
IESO
-
-
100
nAde
V SE = 5.0 Vde, IC = 0
hFE
100
-
500
-
IC - 10 mAde, V CE - 10 Vde
VCE(sat)
-
-
0.25
Vdc
IC
Vdc
IC = 10 mAde, IS = 1.0,mAde
IC - 10 mAde, V CE - 10 Vdc
ICBO
= 1'0 mAde, IS.-
1.0 mAde
V~ElsatL
-
VSE(on)
0.5
-
1.2
Vdc
fT
Ceb
hfe
-
120
-
MHz
IC - 2.0 mAde, V CE - 5.0 Vde
1.6
-
10
pF
VCS - 0, IE -0, f - 1.0 MHz
100
-
750
-
IC = 10 mAde, VCE = 10Vde, f = 1.0 kHz
0.75
-
Conditions
9-22
MPS6530 thru MPS6532
NPN SILICON AMPLIFIER TRANSISTORS
Package: To-92
ABSOLUTE MAXIMUM RATINGS (T A = 25 0 C unless otherwise noted)
Characteristic
Collector Current .................
Unit
600
600 mAdc
Total Device Dissipation
Collector-Base Voltage
MPS6530, MPS5631 ........ 60
Vdc
MPS6532 .......................... 50
MPS6530, MPS6531 ......... 40
MPS6532 ......................... 30
Emitter-Base Voltage ...... 5.0
@T A =60 0 C ................... 210
210
@T A = 25 0 C ................... 310
310
mW
Thermal Resistance, Junction
to Ambient ...................... 0.357 0.357 °C/mW
Junction Temperature ........... 135
4.0
135
°c
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Conditions
BV CBO
60
-
-
Vde
IC = 10uAde, IE = 0
50
-
-
40
-
-
MPS6530,
MPS6531
BV'CEO
MPS6532
Vdc
! IC I
10 mAdc, I B- 0
MPS6530,
MPS6531
30
-
-
BV EBO
5.0
-
-
ICBO
-
-
0.05
-
0.1
-
2.0
MPS6532
Vde
IB -10uAde, IC - 0
uAdc V CB -40Vde,I E -0
MPS6530,
MPS6531
-
,
MPS6532
V CB = 30 Vde, IE = 0,
TA = 60 0 C
hFE
-
-
5.0
30
75
-
60
120
-
40
85
120
-
MPS6530,
MPS6531
V CB - 30 Vde, IE - 0,
TA = 60 0 C
MPS6532
IC = 10 mAde, V CE V CE =1Vde
MPS6530
MPS6531
IC = 100 mAde,
MPS6530
VCE = 1 Vde
90
150
270
30
-
-
25
60
-
MPS6531
MPS6532
IC = 500 mAde,
MPS6530
VCE = 10 Vde
VCE(sat)
50
80
-
-
0.2
0.5
0.13
VBE(sat)
-
0.13
0.82
MPS6531
Vde
IC - 100 mAdc,
MPS6530,
IB = 10 mAdc
MPS6532
0.3
MPS6531
Vde
1.0
IC = 100 mAde,
IB = 10 mAde
Cob
fT
MPS6530,
MPS6531
-
0.85
1.2
-
3.5
5.0
pF
V CB = 10Vde, IE = 0, f = 100 kHz
390
-
MHz
IC - 50 mAde, V CE - 10 Vde
MPS6532
9-23
I
I
•
MPS6533 thru MPS6535
PNP SILICON AMPLIFIER TRANSISTORS
Package: To·92
ABSOLUTE MAXIMUM RATINGS (T A ; 250 C unless otherwise noted)
Emitter·Base Voltage ...........
Unit
Characteristic
Collector Current .................
Coliector·Base Voltage
MPS6533, MPS6534 ........
40
MPS6535 •........................
39
4.0
Vdc
600
mAdc
210
mW
Total Device Dissipation
Vdc
@T A ; 60 0 C
................... 210
@T A = 25 0 C ...................
Coliector·Emitter Voltage
MPS6533, MPS6534 .: ... : .. 1
MPS6535· .......... ·.......... ·· .. 1
5.0
600
310
310
Thermal Resistance, Ju nction
1 40
to Ambient ....................... 0.357 0.357 °C/mW
135 135
°c
1 30
Junction Temperatu re ...........
ELECTRICAL CHARACTERISTICS (TA = 25 0 C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
BV CBO
40
-
-
Vdc
30
-
-
40
-
-
30
-
-
4.0
-
-
Conditions
' C =10UAdc,I E =0
MPS6533,
MPS6534
BV CEO
MPS6535
Vdc
' C -10mAdc,I B -0
MPS6533,
MPS6534
BVEBO
ICBO
MPS6535
= 10 uAdc,I C = 0
Vdc
'B
uAdc
V CB -30Vdc,I E -0 MPS6533,
-
0.05
-
0.1
V CB
-
2.0
V CB = 30 Vdc, 'E - 0, MPS6533,
MPS6534
-
= 20
Vdc, IE
-
V CB - 20 Vdc, 'E - 0, MPS6535
5.0
TA
hFE
VCE(sat).
-
-
60
110
-
VCE
40
85
120
= 100 mAdc,
VCE = 1 Vdc
'90
140
270
30
-
-
25
55
-
50
70
-
-
0.2
0.5
'C - 10 mAdc,
-
0.13
0.84
MPS6534
MPS6.533
MPS6534
MPS6535
= 500 mAdc,
VCE = 10 Vdc
MPS6533
'C
MPS6534
Vdc
'C - 100 mAdc;
MPS6533,
= 10 mAdc
MPS6535
'C - 100 mAdc,
MPS6533,
= 10 mAdc
MPS6534
MPS6534
0.3
Vdc
1.0
'B
Cob
fT
MPS6533
= 1 Vdc
'C
'B
VBE(sat)
= 60 0 C
70
30
MPS6535
MPS6534
T A - 60 0 C
-
=0
MPS6535
-
0.87
1.2
-
4.8
6.0
pF
V CB
-
260
-
MHz
'C - 50 mAdc, V CE'- 10 Vdc
9-24
= 10 Vdc,
'E
= 0, f = 100 kHz
MPS6565, MPS6566
GENERAL PURPOSE NPN SILICON AMPLIFIER TRANSISTORS
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Unit
Characteristics
Collector-Emitter Voltage .......
uu •••••• u
••••••••
45 Vdc
Collector-Base Voltage ................................. 60 Vdc
Emitter-Base Voltage ................................... 4.0 Vdc
Collector Current - Con~inuous ................ 200 mAdc
Total Device Dissipation @T A = 250 C ........ 310 mW
Derate above 25 0 C .......................... 2.81 mW/oC
Operating and Storage Junction
Temperature Range .................... -55 to +135 °c
Thermal Resistance, Junction
to Ambient ............
u
•••••••••••••••••••••
0.357 °C/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Conditions
Symbol
Min
Typ
Max
Unit
BV CEO
45
-
-
Vdc
IC = 1 mAde, I B = 0
BV CBO
BV EBO
60
-
-
Vdc
IC = 100uAdc,I E = 0
4.0
-
-
Vdc
IE - 100 uAdc, IC - 0
ICBO
-
-
100
nAdc
V CB =30Vdc,I E -0
hFE
40
-
160
-
IC -10 mAde, VCE - 10 Vdc
MPS6565
VCE(sat)
100
-
400
-
0.1
0.4
Vdc
-
3.5
pF
v CB -
MPS6566
IC -10 mAdc, IB - 1 mAdc
-100 kHz
10 VdC, IE -.0, f
Cob
Cib
-
3.7
-
pF
V BE - 0.5 Vdc, IC - 0, f - 100 kHz
hfe
2.0
-
-
-
IC - 10 mAde, V CE - 10 Vdc, f - 100 MHz
-
60
-
umhos
IC = 10 mAdc, VCE - 10 Vdc, f -1 kHz
500
-
I C -l0mAdc, VCE -10Vdc,f-l kHz
-
2.5
-
4.0
-
ohms
X 10-4
dB
IC - 100 uAdc, V CE - 5 Vdc,
hoe
h· e
hre
NF
IC - 10 mAde, V CE - 10 Vdc, f - 1 kHz
RS = 1000 ohms, f = 10 Hz to 15.7 kHz
9-25
MPS6591®
Package: To-92
NPNSI LICON AMPLI FIER TRANSISTOR
High Voltage _________ BV CEO = 80 V (Min) MPS6590
Low Noise _______ .. _........ NF = 3.0 dB (Typ) Wideband
ABSOLUTE MAXIMUM RATINGS (Note 1)
Characteristics
Unit
Storage Temperature ........................ -55 to +150 °C
Operating Junction Temperature ...... ·55 to +150 °C
Total Dissipation (Notes 2 and 3)
at 25 0 C Case Temperature ........................ 1.0 W
at 25 0 C Ambient Temperature ................ 625 W
at 70 0 C Ambient Temperature ............... .400 W
Collector to Base Voltage ................................ 60 V
Collector to Emitter Voltage (Note 4) ............. 50 V
Emitter to Base Voltage ................................. 4.0 V
DC Collector Current .................................. 250 mA
ELECTRICAL CHARACTERISTICS (25 0 C Free Air Temperature unless otherwise noted)
Symbol
Min
BV CEO
50
Typ
Volts
IC = 1.0 mA, IB = 0
BV CBO
60
Volts
IC - 100uA, IE = 0
BV EBO
4.0
Volts
IE - 100uA, IC - 0
nA
V CB -50V,I E -0
100
nA
V CB
0.6
Volt
30V,I E -0
I C =10mA,V CE -10V
I C =10mA,I B -1.0mA
12
pF
V CB = 10 V, IE - 0, f - 100 kHz
50
pF
V BE = 0.5 V, IC - 0, f - 100 kHz
Max
ICBO
ICBO
hFE
40
VCE(satl
Ccb
Ceb
h.
Ie
h
re
h fe
hoe
NF
Test Conditions
Unit
1.4
kO
Ie - 10 mA, VeE - 5.0 V, f - 1.0 kHz
0.8
X 10-4
Ie -10 mA, VeE - 5.0 V, f= 1.0 kHz
75
umhos
Ie -10mA, VeE - 5.0V, f-1.0 kHz
3.0
dB
2.0
Ie - 10 mA, VeE - 10W, f = 30 MHz
Ie = 100uA, VeE - 5.0V,
f = 10 Hz to 15.7 kHz, Rs =4kO
NOTES:
(1) These ratings are limiting values above which the
serviceability of any individual semiconductor
device may be impaired.
(2) These are steady state limits. The factory should
be consulted on applications involving pulsed or
low duty cycle operations.
9-26
(3) These ratings give a maximum junction temperature of 150 0 C and junction to case thermal
resistance of 125 0 C/Watt (derating factor of 8.0
mW/oC); junction to ambient thermal reSistance
of 200 0 C/Watt (derating factor of 5.0 mW/0C).
(4) Rating refers to a high current point where
cOllector to emitter voltage is lowest.
(5) Pulse conditions: length = 300 us; duty cycle
= 1%.
ITT
----2N696
SILICON GENERAL PURPOSE TRANSISTORS
SEMICONDUCTORS
GENERAL
PURPOSE
NPN SILICON
PLANAR EPITAXIAL
TRANSISTOR
For Improved Performance See ITT 2N2217,
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage....................
60
Collector-to-Emitter Voltage ................
35
Emitter-to-Base Voltage.......................
5
Operating Junction Temperature.........
175
Storage Temperature ........................... -65 to +200
PD@ Tc = 25·C....................................
2.0
PD@ TA = 25.C....................................
0.6
Volts
Volts
Volts
oC
oC
Watts
Watt
ELECTRICAL .CHARACTERISTICS (25.C free air unless otherwise noted)
Svmbol
BVCBO
LVCER
BVEBO
hFE
Max.
Min.
60
40
5
Unit
Vdc
Vdc
. Vdc
I C= 150mA, V CE= 10V pulsed
60
20
VCE (sat)
VBE (sat)
1.5
1.3
Vdc
Vdc
ICBO
ICBO
1.0
100
A
A
35
pF
Cob
hIe
NOTES: Pulse width
2
300 sec, duty cycle
2%.
Conditions
Ic= 100 A
I c= 30mA, R BE= 10 pulsed
IE= 100 A
I c= 150mA, I B= 15mA pulsed
Ic= 150mA,I B= 15mA pulsed
V CB= 30V
VCB = 30V, TA = +150·C
VCB= 10V
I c= 50mA, V CE= 10V, f = 20MHz
I
I
_I .LT _______
rIl
2N706,2N706A,2N706B
S_I_Ll_C_O_N_S_W_IT_C_H_I_N_G_T_R_A_N_S_I_S_TO_R
SEMICONDUCTORS
HIGH-SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED SWITCHING
TRANSISTOR
For Improved Performance See ITT 2N2368.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage..........................
25
Collector-to-Emitter Voltage ......................
15
Emitter-to-Base Voltage.............................
3
Operating Junction Temperature...............
200
Storage Temperature ................................ -65 to +200
Po@ Tc = 25 u C.........................................
1.0
Po@ TA = 25 oC.........................................
0.3
Volts
Volts
Volts
oC
oC
Watt
Watt
ELECTRICAL CHARACTERISTICS (25C. free air unless otherwise noted)
Symbol
Max.
Min.
BVcBO
VCER
BVEBO
25
20
3
hFE
20
Conditions
Unit
Vdc
Vdc
Vdc
I c= 1.011A
I c= 30mA, R BE= 10Qpulsed
I E= 1011A
Ic= 10mA, VCE= 1.0V
VCE (sat)
VBE (sat)
0.6
0.9
Vdc
Vdc
I c= 10mA, I B= 1.0mA
I C.= 10mA, I B= 1.0mA
ICBo
ICBO
50
30
nA
llA
VCB= 15V
VCB = 15V, TA = +150·C
Cob
6.0
pF
VCB= 10V
11
ns
ns
I C=. 4.5mA
Ic= IB1= I B2= 10mA, VCC= 10V, R L= 1K
hfe
2
tpd
ts
5
Ic= 10mA, VCE= 15V,f = 100MHz
60
"
NOTE; Pulse width
300 sec. duty cycle
2%.)
9-28
2N706.2N706A.2N706B
SILICON SWITCHING TRANSISTOR
ELECTRICAL CHARACTERISTICS (25 o C free air unless otherwise noted)
Symbol
Min.
BVCBO
LVCER
BVEBO
25
20
5
hFE
20
VCE (sat)
VBE (sat)
0.7
ICBO
ICBO
Cob
hie
Max.
Unit
Vdc
Vdc
Vdc
Conditions
I c= 10~A
I c= 10mA, R BE= 10rlpulsed
I E= 10]lA
I c= 10mA, V CE= 1V
0.6
0.9
Vdc
Vdc
I c= 10mA, I B= 1mA
Ic= 10mA,IB= 1mA
0.5
30
]lA
~A
V CB= 15V
VCB = 15V, TA = 150 0 C
5
pF
VCB= 5V
2
I c= 10mA, V CE= 10V, f = 100MHz
ts
25
ns
I c.= I B1 = I B2= 10mA, V cc= 10V, R L= 1 K
ton
40
ns
I B1 = 3mA, I B2= 1 mA, V CC= 3V, R L= 270
toll
75
ns
I B1 = 3m A, I B2.= 1mA, V cc= 3V, R L= 270
I
I
ELECTRICAL CHARACTERiSTICS (25 o C free air unless otherwise noted)
Symbol
Min.
Max.
Conditions
Unit
BVCBO
LVCER
LVCEO
BVEBO
25
20
15
5
hFE
20
60
VCE (sat)
VBE (sat)
0.7
0.4
0.9
Vdc
Vdc
I c= 10mA, I B= 1mA
I c= 10mA, I B= 1mA
ICBO
ICBO
ICER
0.5
30
10
]lA
]lA
]lA
VCB= 15V
VCB = 15V, TA = 150 0 C
VCE = 20V, RBE = 100K
Cob
5
pF
VCB- 5V
hie
Vdc
'Vdc
Vdc
Vdc
I c= 10 A
I c= 10mA, R BE= 10 pulsed
I c= 10mA pulsed
I E= 10~A
Ic= 10mA, VCE-IV
I c= 10mA, V CE= 10V, f = 100MHz
2.0
rbl
50
ohms
I c= 10mA, V eE= 15V, f = 300M Hz
Ts
25
ns
Ic= IB1= IB2= 10mA, Vce= 10V, R L= 1
ton
40
ns
I B1 = 3m A, I B2= 1mA, Vce= 3V, R L= 270
75
ns
I B1 = 3m A, I B2= 1mA, V ce= 3V, R L= 270
toll
NOTE: Pulse width
300
sec. duty cycle 2%.
9-29
•
ITT
----2N708
SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS
HIGH-SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED SWITCHING
TRANSISTOR
For Improved Performance See ITT 2N2369A.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage ...................................... .
Collector-to-Emitter Voltage .................................. .
Emitter-to-Base Voltage ......................................... .
Operating Junction Temperature .......................... ..
Storage Tem perature ............................................. .
PD@Tc = 25~C ...................................................... .
PD@ TA = 25 o C ....................................................... .
40
15
5
200
-65 to +200
1.2
.36
Volts
Volts
Volts
oC
vC
Watts
Watt
ELECTRICAL CHARACTERISTICS (25 o C free air unless otherwise noted)
Symbol
Min.
BVcBO
LVCER
LVCEO
BVEBO
40
20
15
5
hFE
hFE
hFE
30
15
15
VeE (sat)
VCE (sat)
VBE (sat)
VBE (sat)
.72
ICBO
ICBO
lEBO
ICEX
Cob
"hfe
Max.
Unit
Vdc
Vdc
Vdc
Vdc
120
Conditions
Ic= WA
I e= 3mA pulsed, R BE= 10&1
I C= 30mA pulsed
I E= 10)lA
Ic= 10mA, VCE= 1V
Ic= 0.5mA, VCE= 1V, T A= -55 o C
I c= 10mA, V CE= 1V
.40
.40
.80
.90
Vdc
Vdc
Vdc
Vdc
I c=
I c=
Ic=
I c=
25
15
0.1
10
nA
)lA
)lA
)lA
V CB=
VCB =
V EB=
V CE=
6
pF
VCB= 10V
3
10mA, I B= 1.0mA
7mA, I B= .7mA, T A= +125 0 C
10mA, I B= 1.0mA
10mA, I B= 1.0mA, T A= -55 o C
20V
20V, TA = +150 o C
4V
20V,V EB= .25V, T A= 125 0 C
I c= 10mA, V CE= 10V, f = 100MHz
rb
50
ohms
I c= 10mA, V CE= 10V, f = 300MHz
Ts
ton
toff
25
40
75
ns
ns
ns
Ic= IB1= IB2= 10mA
I C= 10mA, I B1 = 3mA, V EB= 2V
I c= 10mA, I B1 = 3mA, I B2= 1mA
NOTE: Pulse width :='300f,lsec. duty cycle :='2%.
9-30
ITT
----2N744
SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS
HIGH SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED SWITCHING
TRANSISTOR
For Improved Performance See ITT 2N2369
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage ....................................... 20
Collector-to-Emitter Voltage ................................... 12
Emitter-to-Base Voltage .......................................... 5
Operating Junction Temperature ........................... 200
Storage Temperature ................................ -65 to +200
'Volts
Volts
Volts
oC
oC
Watt
Watt
~~ ~ i~: ~~~g::::::::::::::::::::::::::::::::::::::::::::::::::::::: 6:~
I
'1
ELECTRICAL CHARACTERISTICS (25 o C Iree air unless otherwise noted)
Symbol
Min.
BVcBO
LVCEO
BVEBO
20
12
5
hFE
hFE
hFE
hFE
20
40
20
20
VCE (sat)
VCE (sat)
0.35
1
VBE (sat)
VBE (sat)
VBE (sat)
0.65
VBE (sat)
Max.
Unit
Vdc
Vdc
Vdc
1.6
Ic=1IlA
I c = 1OmA pulsed
Ic= 1OIlA.
Ic=
Ic =
Ic=
I c=
120
0.85
1.5
1.1
Conditions
1.0mA. VCE= 0.25V
1OmA. VCE = 0.35V
100niA. VCE= 1.0Vpulsed
10mA. V CE= 0.35V. T A= -55 o C
Vdc
Vdc
Ic= 10mA.1 B= 1mA. T A= 170 0 C
I c= 100mA.1 B= 10mA. T A= 170 0 C pulsed
Vdc
Vdc
Vdc
Ic= 10mA.IB= 1mA
I C= 100mA. I B= 1OmA pulsed
I C= 10mA, I B= 1 mA, T A= -55 o C
Vdc
I c= 100mA, I B= 10mA, T A= -55 o C pulsed
ICBO
ICEO
1
30
IlA
Il A
V CB= 20V
V CE= 10V, V BE= 0.35V, T A= 100 0 C
ICES
ICES
1
100
].1 A
].1A
VCE= 20V
VCE= 20V, T A= 170 0 C
5
pF
VCB= 5V
18
12
16
45
24
ns
ns
ns
ns
ns
Ic= IB1= IB2= 10mA
I C= 100mA, I B1 = 40mA, I B2= 20mA
Ic=10mA, I B1= 3mA, I B2= 1.5mA
I C= 100mA, I B1= 40 mA, I B2= 20mA
I C= 10mA, I B1= 3m A, I B2= 1.5mA
Cob
hie
2.8
T5
ton
ton
toll
toll
I c= 10mA, V CE= 10V, 1= 100MHz
NOTE: Pulse.width:5300}lsec, duty cycle ~2%.
9-31
I
I
•
I
I
ITT
----2N834
SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS
HIGH-SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED
SWITCHING TRANSISTOR
For Improved Performance See ITT 2N2369.
2N834 ABSOLUTE MAXIMUM RATINGS
UNITS
CHARACTERISTICS
Collector-to-Base Voltage..................................... 40
Collector-to-Emitter Voltage ................................. 25
Emitter-to-Base Voltage........................................
5
Operating Junction Temperature .......................... 175
Storage Temperature .............................. -65 to +200
Po@ Tc = 25 o C ..................................................... 1.0
Po@ TA = 25 c C ..................................................... 0.3
Volts
Volts
Volts
oC
cC
Watt
Watt
2N834 ELECTRICAL CHARACTERISTICS (25.C free air unless otherwise noted)
Symbol
Min.
BVCBO
BVCES
BVEBO
40
30
5
hFE
25
Max.
Unit
Vdc
Vdc
Vdc
Ic= 100 A
Ic= 10 A
I E= 100 A
I c= 10mA, I B= 1.0mA
I c= 50mA, I B= 5.0mA pulsed
le= 10mA,IB= 1.0mA
Ic= 10mA, VCE= 1.0V
VeE (sat)
VeE (sat)
VBE (sat)
0.25
0.4
0.9
Vdc
Vdc
Vdc
leBo
leBo
0.5
30
A
A
4
pF
25
35
75
ns
ns
ns
Cob
hte
3.5
s
ton
tott
NOTE: Pulse width
300 sec, duty cycle
Conditions
2%.
9-32
VeB= 20V
VeB= 20V, T A= 150 0 C
VeB= 10V
Ie = 10mA. VeE = 15V. f = 100MHz
I c- 10mA, I B1- I B2- 10mA
I c= 10mA, I B1 = 3mA, I B2= 1mA
I c= 10mA, I B1 = 3mA, I B2= 1mA
2N2195, 2N2195A, 2N2195B®
HIGH-SPEED NPN SILICON
HIGH-CURRENT SWITCHING TRANSISTORS
ITT
---------......
SEMICONDUCTORS
Package TO-5
ABSOLUTE MAXIMUM RATINGS (Note 1)
Characteristics
Unit
Collector-Base Voltage ........................................ 45 Volts
Collector-Emitter Voltage (Note 4) .................... 25 Volts
Emitter-Base Voltage .......................................... 5.0 Volts
Collector Current ................................................... 1.0 Amp
Total Dissipation @:
TC = 25°C (Notes 2 and 3) ........................ 2.8 Watts
TC = 100° C (Notes 2 and 3) ...................... 1.6 Watts
TA = 25°C (Notes 2 and 3) .......................... 0.6 Watt
Storage Temperature ....................... -65°C to +300°C
Operating Junction Temperature ...... -65 to +200 °C
Lead Temperature
(Soldering. No Time Limit) ............... 300°C Maximum
ELECTRICAL CHARACTERISTICS (T A
Symbol
Min
Max
NOTES:
(1)
These ratings are limiting values above which the' serviceability of any individual semiconductor device may be
impaired.
(2)
These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle
operations.
(3)
These ratings give a maximum junction temperature of
20DoC and junction-ta-case thermal resistance of
62.5°C/watt Iderating factor of 16 mW/oCI: junction-toambient thermal resistance of 292°C/watt (derating factor of 3.42 mW/oCI.
(4)
Rating refers to a high-current point where collector-toemitter voltage is lowest.
151
Pulse Conditions: length :$ 300 psec. duty cycle :$ 2%.
= 25°C unless otherwise noted)
Unit
Conditions
hFE
20
IC
= 150 mAo VCE = 10 Volts
hFE
10
IC
= 150 mAo VCE = 1.0 Volt
VCE(sat)
0.35
Volt
IC
= 150 mA.IB = 15 mA (2N2195)
VCE(sat)
0.25
Volt
IC
= 150mA.IB = 15mA(2N2195A
VCE(sat)
0.18
Volt
IC
= 150 mA.IB = 15 mA(2N2195B)
VBE(sat)
1.3
Volts
IC
= 150 mAo I B = 15 mA
IC
= 50 mAo VCE = 10 Volts
hfe
2.5
Cob
20
pF
IE
= O. VCB = 10 Volts
ICBO
100
nA
IE
= O. VCB = 30 Volts
50
J.l.A
IE
= O. VCB = 30 Volts
100
nA
IC
= O. VEB = 3.0 Volts
= 100J.l.A.IE = 0
ICB O(150°C)
lEBO
BVCBO
45
Volts
IC
VCEO(sust)
25
Volts
IC = 25 mA (pulsed). IS
(Notes 4 and 5)
BVEBO
5.0
Volts
IE
9-33
= 100 J.l.A. Ie = 0
0
mm
_.I
2N929, 2N930
-L-L ___S_IL_I_C_O_N_G_EN_ER_A_L_P_U_R_P_O_S_E_T_R_A_N_S_I_ST_O_R
SEMICONDUCTORS
LOW LEVEL
LOW NOISE
NPN SILICON PLANAR
TRANSISTORS
• High Gain; 100 mln.@ Ic = 10 A
The ITT .2N929 and 2N930 are NPN silicon. planar
transistors designed for application in low noise.
low level amplifiers in the audio through high
frequency range.
• Low Noise; 3dB max.@ Ic = 10 A
• High VCEO; 45 Vdc min.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
Units
Collector-to-Base Voltage....................................... 45
Collector-to-Emitter Voltage (open base)............... 45
Emitter-to-Base Voltage.......................................... 5.0
Collector Current (continuous)................................ 30
Junction Temperature (operating) ............. -65 to +175
(storage) ................ -65 to +200
Total Power Dissipation @ Tc = 25~C .................... 0.6
(derate 4.0 mW/oC above 25 o C)
Total Power Dissipation @ T A = 25 0 C .................... 0.3
(derate 2.0 mW/eC above 25 0 CL
Volts
Volts
Volts
mA
oC
"C
Watts
ELECTRICAL CHARACTERISTICS @
Symbol
LVcEO
BVEBo
Min.
25~C
unless otherwise noted
Max.
Unit
Vdc
Vdc
45
5.0
Conditions
Ic= 10mA
IE=10nA
Ic= 10 A, VCE= 5.0V
2N929
2N930
hFE
40
100
Watts
120
300
I c= 500 A, V CE= 5.0V
2N929
2N930
60
150
Ic= 10mA, VCE= 5.0V
2N929
2N930
350
600
Ic= 10 A, VCE= 5.0V, T A= -55-C
2N929
2N930
10
20
9-34
2N929, 2N930
SILICON GENERAL PURPOSE TRANSISTOR
ELECTRICAL CHARACTERISTICS @ 25 0 C unless otherwise noted (continued)
Symbol
VCE (sat)
VBE (sat)
Max.
Unit
0.6
1.0
1.0
Vdc
Vdc
Ic=
mA, I B= 0.5mA
Ic = 10mA, IB = 0.5mA
1
1
Conditions
Min.
ICBo
ICEO
lEBO
ICES
ICES
10
2
10
10
10
nA
nA
nA
nA
A
V CB= 45V
VCE= 5V
V EB= 5V
VCE=45V
VCE= 45V, T A= 170 oC
Cob
8
pF
VCB= 5V
Ic= 1.OmA, VCE= 5V, f = 1KHz
2N929
2N930
hie
hib
hob
hrb
60
150
350
600
1.0
1.0
25
32
1.0
600
Ic.= 500 A, V CE= 5V, f = 30mHz
ohms
mho
X10_6
Ic= 1.OmA, VCB= 5V, f = 1mHz
Ic= 1.OmA, VCB= 5V, f = 1mHz
A, VCB= 5V
Ic=
dB
dB
Ic= 10 A, VCE= 5V, RG= 10K
BW. = 200Hz, f = 1 KHz
2N929
2N930
NF
4
3
Notes: 1. Pulse width 300 sec; duty cycle 2%.
2. Lowest emitter to collector voltage.
9-35
•
I
m _ _ _ _ __
_ 1 T.L
2N2217, 2N2218, 2N2219
SILICON GENERAL PURPOSE TRANSISTORS
SEMICONDUCTORS
GENERAL PURPOSE NPN SILICON
PLANAR EPITAXIAL TRANSISTORS
• Low VCE (sat),
It
0.4V@ Ic
High Frequency, fT
= 150mA
= 250 MHz @ I c = 20mA
• Wide Useful Current Range, 0.1 to 500mA
The ITT 2N2217-19 are NPN silicon planar epitaxial general purpose transistors for applications at
current ranges from 0.1 to 500mA. Low saturation
voltage and fast switching times make the
2N2217-19 ideal for core driving. The flat grain
over a wide current range gives good linearity in
amplifier circuits. High break~own voltage allows
large signal swing in switching and amplifier circuits.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage.......................................
60
Collector-to-Emitter Voltage (open base)...............
30
Emitter-to-Base Volta·ge..........................................
5.0
Collector Current (continuous)................................ 800
Junction Temperature (operating) ................ -65 to +175
(storage) ................... -65 to +300
Total Power Dissipation @ Tc = 250C ....................
3.0
(derate 20mW/~C above 25~C)
Total power Dissipation @ T A = 25oC.....................
0.8
(derate 5.33 mW/~C above 25 o C)
Volts
Volts
Volts
mA
oC
~C
Watts
Watts
ELECTRICAL CHARACTERISTICS @ 25 c C unless otherwise noted
Max.
Min.
Symbol
Conditions
Ic= 150mA, VCE= 10V
2N2217
2N2218
2N2219
hFE (1)
20
40
100
Unit
60
120
300
10
20
50
Ic= 150mA, VCE= IV
2N2217
2N2218
2N2219
20
30
Ic= 500mA, VCE= 10V
2N2218
2N2219
hFE
9-36
2N2217, 2N2218, 2N2219
SILICON GENERAL PURPOSE TRANSISTORS
ELECTRICAL CHARACTERISTICS @ 25 0 C unless otherwise noted (continued)
Min.
Symbol
Conditions
Unit
Max.
17
35
75
Ic= 10mA, VCE= 10V
2N2217
2N2218
2N2219
12
25
50
I c= 1mA, V CE= 10V
2N2217
2N2218
2N2219
20
35
Ic= 0.1mA, VCE= 10V
2N2218
2N2219
VCE (sat)
(1)
0.4
1.6
Vdc
Vdc
Ic= 150mA, I B= 15mA
I c= 500mA, I B= 50mA
VBE (sat)
(1)
1.3
2.6
Vdc
Vdc
I C= 150mA, I B= 15mA
I c= 500mA, I B= 50mA
ICBO
10
10
nA
A
VCB=50V,IE=0
VCB = 50V, IE = 0, T = 150-C
lEBO
10
nA
V EB= 3V, I c= 0
MHz
I C= 20m A, V CE= 20V
8
pi
VCB= 10V, I E= 0
Ohms
I C= 20mA, V CE= 20V, I = 300MHz
IT
250
Cob
60
Re(hie) (2)
BVCBO
VCEO (sust)
BVEBO
Vdc
Ic=10 A,IE=O
30
Vdc
Ic=10mA,IB=0
5
Vdc
IE= 10 A, Ic= 0
60
(1)
NOTES: 1.' Pulse Measurement: width 300 sec. duty cycle 2%.
2. Real part of Common-Emitter high frequency input impedance.
9-37
I
•
ITT
SEMICONDUCTORS
2N2219A
SILICON SWITCHING TRANSISTOR
---~-
HIGH-SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED SWITCHING
TRANSISTOR
UNITS
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
Collector-to-Base Voltage ....................................... 75
Collector-to-Emitter Voltage ................................. ~ ..
Emitter-to-Base Voltage.......................................... 6
Operating Junction Temperature ............................175
Storage Temperature ............................... -65 to +200
Po@ Tc = 25~C ............................................., ....: ... ,3.0
Po @ T A = 25"C .......................................................0.8
Volts
Volts
Volts
"C
wC
Watts
Watts
·40
ELECTRICAL CHARACTERISTICS (25 o C free air unless otherwise noted)
Symbol
BVCBO
LVEBO
BVEBO
hFE
hFE
hFE
hFE
hFE
hFE
hFE
VCE(sat)
VCE(sat)
VBE(sat)
VBE (sat)
ICBo
ICBO
Min.
Max.
75
40
6
35
50
75
100
40
50
35
0.6
Unit
Conditions
Vdc
Vdc
Vde
Ic= 10\.lA
I C= 10mA pulsed
IE= 10\.lA
I c=
.1 C=
Ic=
I C=
I C=
Ic=
I c=
100lJA, V CE = 10V
1 rnA, V CE= 10V
10mA, VeE= 10V
150mA, V CE= 10V pulsed
500mA, V CE= 1OV pulsed
150mA, VCE= 1Vpulsed
10mA, V CE= 10V, T A= -55"C
Vde
Vde
Vde
Vdc
I C=
Ic=
I c=
1C=
150mA, I B=
SOOmA,1 B=
1S0mA,I B=
500mA, I B=
nA
A
VCB= 60V
VCB = 60V, TA = 1S00 0
300
0.3
1.0
1.2
2.0
10
10
9-38
15mA pulsed
50mA pulsed
15mA pulsed
SOmA pulsed
2N2219A
SILICON SWITCHING TRANSISTOR
ELECTRICAL CHARACTERISTICS continued
Parameter
Min.
Conditions
Max.
Unit
ICEX
IEBX
lEBO
10
20
10
nA
nA
nA
V CE= 60V. V EB= 3V
VEB= 3V. VCB= 60V
VEB= 3V
Cob
Cib
B
25
pF
pF
VCB= 10V
VEB=0.5V
hIe
hIe
hIe
50
75
3
300
375
hie
hie
2
0.25
B
1.25
hre
hre
hoe
hoe
B
4
5
25
Re(hie)
rb'Cc
Kohms
Kohms
c= 1mA, VCE= 10V, f = 1KHz
c= 10mA, V CE= 10V, f= 1KHz
x10
x10
c= 1mA, V CE= 10V, f = 1KHz
c= 10mA, V CE= 10V, f = 1KHz
~4
~4
C= 1mA, VCE= 10V, f = 1KHz
C= 10mA, V CE= 10V, 11 KHz
35
200
mho
mho
60
150
omhs
ps
c= 20m A, V CE= 20V, f = 300M Hz
c= 20mA, V CE= 20V, f = 31.BMHz
db
c= 100 A, VCE= 10V, RG= 1K
N.F.
4
Ts
c= 1mA, V CE= 10V, f = 1KHz
C= 10mA. VCE= 10V, f= 1KHz
C= 20m A, V CE= 20, f = 100MHz
2.5
=
,f = 1KHz
ns
I c= 150mA, I B1= 15mA, V cc= 30V, VEB= 0.5V
td
10
ns
I C= 150mA, I B1 = 15mA, V CC= 30V, VEB= 0.5V
tr
25
ns
Ic= 150mA, I B1= 15mA, V cc= 30V, VEB= 0.5V
ts
tl
225
60
ns
ns
I c= 150mA, I B1= I B2= 15mA, V CC= 30V
I c= 150mA, I B1 = I B2= 15mA, V cc= 3DV
Note: Pulse width
30 sec, duty cycle
2%,
9-39
ITT
-----
2N2221,2N2222
SILICON GENERAL PURPOSE TRANSISTORS
SEMICONDUCTORS
GENERAL PURPOSE HIGH-VOLTAGE
NPN SILICON PLANAR
EPITAXIAL TRANSISTORS
The ITT2N2221-22 are NPN silicon planar epitaxial general purpose transistors for applications at
current ranges from 0.1 to 500 mAo Low saturation
voltage and fast switching times make the
2N2221-22 ideal for core driving. The flat gain over
a wide current range gives good linearity in
amplifier circuits. High breakdown voltage allows
large signal swing in switching and amplifier circuits.
-Low VCE(sat). 0.4 V@ Ic = 150mA
_ High Frequency. IT = 250 MHz @ I C
= 20mA
- Wide Useful Current Range. 0.1 to 500mA
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
Units
Collector-to-Base Voltage....................................... 60
Collector-to-Emitter Voltage (open base)............... 30
Emitter-to-Base Voltage.......................................... 5.0
Collector Current (continuous)................................ BOO
Junction Temperature (operating) .............. -65 to + 175
(storage) ................. -65 to +300
Total Power Dissipation @ Tc = 25 0 C .................... 1.B
(derate 12mW/oC above 25 o C)
Total Power Dissipation @ t A = 25 0 C .................... 0.5
(derate 3.33 mW/oC above 25 o C)
Volts
Volts
Volts
mA
oC
oC
Watts
Watts
ELECTRICAL CHARACTERISTICS @ 25 0 C unless otherwise notea
Symbol
Min.
Max.
UnlL
hFE'
Condition.
I c= 150mA, V GE= 10V
40
100
120
300
2N2221
2N2222
I c= 150mA, V CE= IV
20
50
2N2221
2N2222
Ic= 500mA, VeE= 10V
2N2221
2N2222
20
30
9-40
2N2221, 2N2222
SILICON GENERAL PURPOSE TRANSISTORS
ELECTRICAL CHARACTERISTICS @ 25 0 C unless otherwise noted
Symbol
nFE
Min,
Max,
Unit
Conditions
Ic= 10mA, VCE= 10V
17
35
75
VeE (sat) ,
0.4
1.6
Vdc
Vdc
2N2221
2N2222
Ic- 1mA, VCE= 10V
2N2220
2N2221
2N2222
Ic- 0.1mA, VCE= 10V
2N2221
2N2222
I C= 150mA, I B= lbmA
I C= 500mA, I B= 50mA
VBE (sat) ,
1.3
2.6
Vdc
Vdc
Ic= 150mA,I B= 15mA
I c= 500mA, I B= 50mA
10
10
nA
A
VCB=. 50V, IE= 0
VCB= 50V,IE= 0, T = 150oC
10
nA
VEB=3V,lc=0
MHz
I C= 20mA, V CE= 20V
pI
VCB= 10V,I E= 0
12
25
50
20
35
ICBO
lEBO
IT
250
8
Cob
Ohms
I c= 20mA; V CE= 20V, f = 300 MH;
60
Vdc
Ic=10 A,IE=O
30
5
Vdc
vac
I c= 10mA, Is= 0
I E- 10 A. I C- 0
60
Re (h,'e) ,
BVCBO
VCEO (sust) ,
BVESO
NOTES: 1, Pulse Measurement: width 300 sec, duty cycle 2%.
2. Real part of Common~Emitter high frequency input impedanC?e.
9-41
ITT
-----
2N2221A ®
SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS
HIGH-SPEED NPN
SILICON PLANAR
EPITAXIAL SATURATED
SWITCHING TRANSISTOR
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to- Base Voltage ........
Collector-to-Emitter Voltage .......
Emitter-to- Base Voltage ..........
Operating Junction Temperature ...
Storage Temperature .............
Po@ Tc = 25°C ...............
Po @ TA = 25°C ...............
.
.
.
.
.
.
.
75
40
6
175
-65 to +200
1.8
0.5
ELECTRICAL CHARACTERISTICS
SYMBOL
BVc,o
LVcEO
BVE,o
hFE
hFE
hFE
hFE
hFE
hFE
hFE
VCE(sat)
VCE( sat)
V'E(sat)
V'E(sat)
Ic,o
Ic,o
MIN.
75
40
6
20
25
35
40
25
20
15
0.6
MAX.
°c
°c
Watts
Watt
(25°C free air unless otherwise noted)
UNIT
Vdc
Vdc
Vdc
120
0.3
1.0
1.2
2.0
10
10
Volts
Volts
Volts
Vdc
Vdc
Vdc
Vdc
nA
",A
9-42
CONDITIONS
Ic= 1O",A
Ic = 1 OmA pulsed
IE=10",A
Ic=100",A, VcE =10V
Ic=1 mA, VcE =10V
Ic= 1OmA, VCE = 1OV
Ic= 150mA, VCE = 1OV pulsed
Ic=500mA, VCE=1 OV pulsed
Ic=150mA, VCE=1V pulsed
Ic= 1OmA, VCE = 1OV, TA = -55°C
Ic=150mA, 1,=15mApulsed
Ic=500mA, 1,=50mA pulsed
Ic=150mA, 1,=15mA pulsed
Ic=500mA, 1,=50mA pulsed
Vc,=60V
Vc,=60V, TA=150°C
2N2221A®
ELECTRICAL CHARACTERISTICS
PARAMETER
MAX.
UNIT
10
20
10
8
25
150
300
nA
nA
nA
pF
pF
T,
3.5
1.0
5
2.5
15
100
60
150
2.5
K ohms
Kohms
x10- 4
x10- 4
JLmho
JLmho
ohms
ps
ns
td
10
ns
t,
25
ns
Icex
leu
leso
Cob
C;b
hI.
hI.
hI.
h;.
h;.
h,.
h,e
hoe
hoe
R.(Me)
rb'C C
t,
tl
MIN.
continued
30
50
2.5
1
0.2
3
10
225
60
ns
ns
NOTES: Pulse width :S 300 "sec, duty cycle::; 2%.
9-43
CONDITIONS
Vce=60V, Ves=3V
Ves=3V, Vcs=60V
Ves=3V
Vcs=10V
Ves=0.5V
1c=1mA, Vce =10V,f=1KHz
Ic=10mA, Vce =10V, f=1 KHz
Ic=20mA, Vce=20V, f=1 OOMHz
1c=1mA, Vce =10V, f=1 KHz
1c=10mA, Vce =10V, f=1 KHz
Ic= 1 mA, Vce= 1 OV, f= 1 KHz
1c=10mA, Vce=10V, f=1 KHz
Ic = 1 mA, Vce= 1 OV, f= 1 KHz
Ic=10mA, Vce =10V, f=1 KHz
Ic=20mA, Vce=20V, f=300MHz
1c=20mA, Vce=20V, f=31.8MHz
Ic=150mA, IS1=15mA, Vcc=30V,
Ves=0.5V
Ic=150mA, IS1=15mA, Vcc=30V,
Ves=0.5V
1c=150mA, 1s,=15mA, Vcc=30V,
Ves=0.5V
Ic=150mA, Is1=l s2 =15mA, Vcc=30V
1c=150mA, IS1=ls2=15mA, Vcc=30V
_I
.
mm
2N2222A
S_I...
LI_C_O_N_S_W_IT_C_H_IN_G_T_R_A_N_S_IS...
i_O_R
.L.;.L ______
SEMICONDUCTORS
HIGH-SPEED NPN SILICON
PLANAR EPITAXIAL
SATURATED SWITCHING
TRANSISTOR
ABSOLUTE MAXIMUM RATINGS
UNITS
CHARACTERISTICS
Collector-to-Base Voltage······ .. ·.................... ·75·
Collector-to-Emitter Voltage ···.··· .... ·.............. 40
Emitter-to-Base Voltage ...............................• 6
Operating Junction Temperature ................. 175
Storage Temperature ... c ••••••••••••••••• -65 to +300
Po@ Tc = 2S·C ············· .. ·.··· ......................... 1.8
Po@ TA = 2S"C· ... ··· ...................................... O.5
Volts
Volts
Volts
o.C
oC
Watts
Watt
ELECTRICAL CHARACTERISTICS (25 oC free air'unless otherwise noted)
Symbol
Min.
BVcBO
LVCEO
BVEBO
7S
40
6
hFE
hFE
hFE
hFE
hFE
hFE
hFE
VCE(sat)
VCE(sat)
VBE (sat)
VBE (sat)
ICBO
ICBO
35
50
75
100
40
50
35
0.6
Max.
Unit
Vdc
Vdc
Vdc
Conditions
Ic= 10 A
I c= 10mA pulsed
IE = 10 A
=
Ic=
I c=
I C=
I C=
Ic=
I c=
100 A, VCE = 10V
1mA, VCE= 10V
10mA, V CE= 10V
1S0mA, V CE= 10V pulsed
SOOmA, V CE= 10V pulsed
1S0mA, VCE= 1Vpulsed
10mA, V CE= 10V, T A= -55-C
150mA, I B=
SOOmA, I B=
150mA, I B=
500mA,I B=
1(;
120
0.3
1.0
1.2
2.0
Vdc
Vdc
Vdc
Vdc
I c=
I c=
I c=
I C=
10
10
nA
A
VCB= 60V
VCB = 60V, TA = 150-C
9-44
15mA pulsed
SOmA pulsed
15mA pulsed
50mA pulsed
2N2222A
SILICON SWITCHING TRANSISTOR
ELECTRICAL CHARACTERISTICS continued
Max.
Min.
Parameter
Conditions
Unit
ICEX
IEBX
lEBO
10
20
10
nA
nA
nA
VCE= 60V, VEB= 3V
V EB= 3V, V CB= 60V
VEB= 3V
Cob
Cib
S
25
pF
pF
V CB= 10V
V EB= 0.5V
hfe
hfe
hfe
50
75
2.5
hie
hie
2.0
0.25
Ic= 1mA, VCE= 10V,f = 1KHz
Ic= 10mA, VCE= 10V, f = 1KHz
I c= 20mA, V CE= 20V, f = 100MHz
300
375
Kohms
Kohms
Ic= 1mA, VCE= 10V,f = 1KHz
Ic= 10mA, VCE= 10V, f = 1KHz
4
X10-4
X10-4
I C= 1mA, V CE= 1OV, f = 1 KHz
I C= 10mA, V CE= 10V, f = 1KHz
35
200
mho
mho
I C= 1mA, V CE= 10V, f = 1KHz
Ic= 10mA, VCE= 10V, f = 1KHz
Re(hie)
60
ohms
rb'Cc
150
ps
2.5
ns
Ic = 150mA,IB1 = 15mA, Vcc = 30V, VEB= 0.5V
td
10
ns
Ic = 150mA,IB1 = 15mA, Vcc = 30V, VEB = 0.5V
tr
25
ns
Ic = 150mA,IB1 = 15mA, VCC= 30V, VEB= 0.5V
ts
225
60
ns
ns
I c= 150mA, I B1= I B2= 15mA, V cc= 30V
I c= 150mA,I B1= I B2= 15mA, V cc= 30V
8
1.25
8
hre
hre
hoe
hoe
5
25
s
tf
NOTES: Pulse width
300 sec.
duty cycle
I c= 20mA, V CE= 20V, f = 300MHz
!
2%.
9-45
Ic=20mA, VCE= 20V, f = 31.SMHz
I
I
ITT
----2N2368,2N2369
SILICON SWITCHING TRANSISTORS
SEMICONDUCTORS
HIGH SPEED NPN SILICON PLANAR
EPITAXIAL SATURATED
SWITCHING TRANSISTORS
•
•
•
•
•
High fT: 650 mHz, typo
High Gain: 40 min. @ Ic 10mA .
Low Cob: 4pf max. @ Vcs 5V
Low Ton 9 nlee typo
Low toff '" 13 nlee typo
=
ABSOLUTE MAXIMUM RATINGS
=
=
CHARACTERISTICS
UNITS
Collector-to-Base Voltage............................... 40
Collector-to-Emitter Voltage (shorted base).. 40
Collector-to-Emltter Voltage (open base)....... 15
Emitter-to-Base Voltage .................................. 4.5
Collector Current (10 sec. pulse) .................... 500
Junction Temperature (op. and stg.) ... -65 to +200
Total Power Disslpation@ Tc ~ 25C ....•........ 1.2
(derate 6.6 mW/oC above 25 o C)
@ Te ~ 100-C .......... 0.66
Total Power Dissipation @ T A ~ 25cC ............ 0.36
(derate 2.06 mW/oC above 25 u C)
The ITT 2N2368 and 2N2369 are NPN silicon
planar epitaxial saturated switching transistors for
applications at current ranges from 0.1 to 100 rnA.
High gain and narrow base region provide excellent radiation resistance. They can operate at
clock rates above 10MHz for commercial computer applications.
Volts
Volts
Volts
Volts
rnA
'C
Watts
Watts
Watts
ELECTRICAL CHARACTERISTICS @ 250C unless otherwise noted.
Symbol
Min.
Typ.
Unit
Max.
hFE 1
20
40
I c= 10mA, V CE= 1V
2N2368
2N2369
60
120
I c= 10mA, V CE= 1V, T = -55-C
2N2368
2N2369
I G= 100mA, V CE= 2V
2N2368
2N2369
10
20
10
20
VCE (sat)
0.2
0.25
Vdc
0.75
0.85
Vdc
ICBO
0.1
10
0.4
30
A
A
fr
650
Cot>
2.5
VBE (sat)
s'
(charge storage
time)
0.7
Conditions
4.0
10
13
9-46
I c= 10mA, I B= 1mA
I c= 10mA, I B= 1mA
VCB= 20V, I E= 0
V CB= 20V, I E= 0, T = 150-C
MHz
VCE= 10V,lc= 10mA
pf
VCB= 5V, I E= 0
nsec
nsec
Ic= I B1 10mA,10mA,
I B2 -10mA-10mA
2N2368
2N2369
2N2368, 2N2369
SILICON SWITCHING TRANSISTORS
ELECTRICAL CHARACTERISTICS @ 250C unless otherwise noted. (continued)
Min.
Symbol
ton
2
Conditions
Typ.
Max.
Unit
9.0
12
nsec
Ic 10mA,
I B1 3mA
toft 2
15
18
10
13
BVCBO
40
nsec
nsec
Ic 10mA,
I B1 3mA,
I B2 -1.5mA
2N2368
2N2369
Vdc
Ic= 10 A,IE= 0
BVCES
40
Vdc
I C= 10 A, I B= 0
VCEO (sust)
15
Vdc
Ic=10mA, I B= 0
BVEBO
4.5
Vdc
I E= 10 A, Ic= 0
NOTES: 1. Pulse measurement: width 300 sec, dutY.cycle 2%.
2. Pulse switching circuits for exact IC, IB1, and IB2.
TYPICAL CHARACTERISTICS'
~ 4
;0
losmo
E 3 r- - I
.041"1\0
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"0
~
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2
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-
./ /
V
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J
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13
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r- -----
REGION COLLECTOR
;/ f-t /: ~
r; ..---r-z.Jo
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'r'
V
u
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COLLECTOR VOLTAGE (V CE ) VOLTS
. .j,~~
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/ 1/
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V
/ /
V /
./
B
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I
SATURATION
T.J•• C_
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V
COLLECTOR VOLTAGE WeE) VOLTS
V
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16
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VOLTS
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8
VOLTAGE COLLECTOR CHARACTERISTICS
~,.....
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100
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CHARACTERISTICS
I-
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00
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COLLECTOR VOLTAGE (VeE)
HIGH
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::. 200
IS-O
4
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SATURATION REGION COLLECTOR
HIGH VOLTAGE COLLECTOR CHARACTERISTICS
~'l
~
~
5m'
IS"'O
\,
0
9-47
0
I
CHARACTERISTICS
--
T=25°C
I
4
2
3
COLLECTOR VOLTAG~ W e.E ) VOLTS
2N2368, 2N2369
SILICON SWITCHING TRANSISTORS
TYPICAL CHARACTERISTICS, continued
HIGH VOLTAGE COLLECTOR
,..-
\8mo
:.--
~
-
u
I-
~
3
~
c....---
lomo
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e'"
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III
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2
3
.
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VOLTAGE" tYeEI VOLTS
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2:'' :'//,1/
E
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-
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~200
-55°C
..........
..........
:.--
~ I--
.
I~
z
40
~
CHARACTERISTICS
SATURATION REGION BASE CHARACTERISTICS
IDO·C
./
.
l!:
I-
~
III
-
VCE: 5 V
0
-- -
COLLECTOR
COLLECTOR
PULSE DC CURRENT GAIN VS COLLECTOR CURRENT
~ 80
t-
V
le: O
COLLECTOR VOLTAGE I VCEI VOLTS
~
l /' -
/
V
,/"
/'
100
L
U
~
-u
= 200
./
•
4
v
~
/ I I
I
02mo
00
SATURATION REGION
T"-~5.C
'/
_I-""
06mo
8
CHttRACTERISTICS
_f-"
\6~
50 100
COLLECTOR CURRENT (Ie' ma
-
ie
"
~
Ie
100
8
'II
III III
ril, 'I I
II
-,omAII
!
,
Nil
0.4
0.8
1.2
T.~5"C
1.8
BASE VOLTAGE lYBEI VOLTS
f
COLLECTOR SATURATION VOLTAGE
VERSUS COLLECTOR CURRENT
Ie
=10
SATURATION REGION BASE CHARACTERISTICS
's-H-+-+-+-++--+-+-t-rt--f-++--H
COLLECTOR CURRENT (Ie) mA
BASE VOLTAGE (YSE ) VOLTS
2N2368, 2N2369
SILICON SWITCHING TRANSISTORS
TYPICAL CHARACTERISTICS. continued
BASE SATURATION VOLTAGE VERSUS COLLECTOR CURRENT
~
I
1.2
~
_55°C
w
25°C
V
;u 200t--I--I---t--+--t--I"-I-ItH-t---t--I--l
!
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0.6
1;
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w
~
0.5
5
I
OJ
10
COLLECTOR CURRENT (lei
+
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50
0.4
100
FALL TIME VERSUS TuRN ON
AND TURN OF'F BASE CURRENTS
.01-
C'i
~
"
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6.0 "sec
I
ao
40
2.0
~
~
~
~
l-
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Vee,· 3,OV
1~ ~~
t-20t-
~
a
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-10
II
/
I -
0
~
-5
V
>-
00
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V
V
..~~~
o·
r-
. ,ro9
V
10
15
20
>-
Ic·IOOm~_
l'
25
TURN O~ BASE CURRENT tl Si) rnA
~8.0 J-Jt-'--
-6.0 1 - -
~ -4,0
it
Vee· 3.OV
5
!
--
-
1/
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~
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~
0
0
?~
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_ .ItL
V
V
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q
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60
llf
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8.0
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a
,,",9
-6.0
.-1'
"
-4.0
~
--
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0
10
mA
VCC· 3.OV
~
TURN ON BASE CURRENT (I BI ) mA
9-49
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~
IC·30mA
VCC· 3 .OV
80
{lSI}
STORAGE TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS
0
,j/
40
60
IC·IOmA
~
/Vv
2.0
40
z
V
/
20
w
ro (:' 0(:''''';7
/
I-
rkt- r=
TURN ON BASE CURRENT
>-
0.9
~
ICOmA
80mAI
160rnA
le= 10 18
~
~g
SATURATiON REGION BASE CHARACTERISTICS
I
~
0
20
"",,---4.0
~P~ F~
6,0 nsec
60
TURN ON BASE CURRENT
I
e:::
-
r- -
80
' 81
mA
2N2368, 2N2369
SILICON SWITCHING TRANSISTORS
TYPICAL CHARACTERISTICS. continued
DELAY TIME VER~US BASEEMITTER OFF VOLTAGE AND
TuRN ON BASE cuRRENT
RISE TIME VERSUS TURN ON BASE
CURRENT AND COLLECTOR CURRENT
~
4
E
Vee-
:iii 10
~
z
~
~
0
u
w
~
1.0
z
0
z
~
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>
-
I,
-
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100
0
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ifIf
10
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5.0
>=
50
10
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"- 1\
1,/
I,
.~
~
~
2.0
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d
VCC· 3 .OV
1.0
1.0
20
20
5.0
10
50
20
ul:~ '"'I;
LOWER LIMITING
VOLTAGE VERSlIS
SOURCE RESISTANCE
CAPACITANCES VERSUS REvERSE
alAS vOLTAGE
L.VCES
I~'
/'j
1
16m.
12 ~VCC=3.0V'
)-
10
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it
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--
LVCEO- -
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0
50
100
0
150
0
0.5
AMBIENT TEMPERATURE (T A ) ·C
~
0
.; 5
I\ \
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~/
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.-!1'
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5
10
20
50
COLLECTOR CURRENT (Ie'
E
I/
'""
~
100
"'~
~
~
/
i?
8
0
-10
50
75
100
AMBIENT TEMPERATURE (TA)
9-50
125
'C
-5
0
II /
II
1/
0
~
I
J1
-20
a -I'
V
O.lV
I
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1.0
0
2
STORAGE TIME vERSUS TURN ON
AND TURN OFF BASE CURRENTS
.
10
l-
""
r;
"j
SOURCE RESISTANCE (RS}OHMS
VOLTS
VCB .. 20V
f-
10K
IK
10
ffi
IE
600mc
~
'"
~
$0
50
COLLECTOR cuTOFF CURRENT
VERSUS AMBIENT TEMPERATuRE
PRODUCT (f I
~oJ
~5
10
In
1.0
REVERSE BIAS VOLTAGE
CONTOURS OF CONSTANT GAIN
BANDWIDTH
100
COLLECTOR CURRENT (lc) mA
TURN ON BASE CURRENT U SI ) mA
EMITTER TRANSITiON ANO
2
20
i/,c",omA
II
20
SWITCHING TIMES
VERSUS AMBIENT TEMPERATURE
<
<
,.'"
In
-
/
0
50
.,0
II
cuRRENT (lei rnA
COLLECTOR
!
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~
0
0
7g~~:~~~,~
II
IL
,b
~
0
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r-l
~
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-
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H,t!
SWITCHING TIMES VERSUS
COLLECTOR CURRENT
0
5
/
I
V
_1.0\' V
",QI- f- .r/ V
I
V
o~
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b[Lf- 7
~.~ -
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v-
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15
20
25
TURN ON BASE CURRENT (lBI) mA
ITT
----2N2369A
SILICON SWITCHING TRANSISTOR
SEMICONDUCTORS
HIGH SPEED NPN SILICON
SATURATED SWITCHING TRANSISTOR
The ITT 2N2369A is a NPN silicon planar epitaxial
saturated switching transistor for applications at
current ranges from 0.1 to 100 mAo High gain and
narrow base region provide excellent radiation
resistance. The 2N2369A can operate at clock
rates above 10 MHz for commercial computer
applications.
• High IT: 675 MHz, typo
• High Gain: 40 mln.@ Ic = 10 mA
• Low Cob: 4 pI max. @ Vca = 5V
• Low ton: 9 nsec typ.;
• Low toll: 13 nsec typo
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage................................. 40
Collector-to-Emitter Voltage (shorted base) .... 40
Collector-to-Emitter Voltage (open base)......... 15
Emitter-to-Base Voltage .................................... 4.5
Collector Current (continuous) .......................... 200
Collector Current (10 sec pulse) ...................... 500
Junction Temperature (op. and stg.) .... -65 to +200
Total Power Dissipation @ Tc = 25 u C .............. 1.2
(derate 6.8 mW/oC above 25~C)
Volts
Volts
Volts
Volts
mA
mA
oC
Watts
@Tc= 100 0 C ............. 0.68
Watts
Total Power Dissipation @ T A = 25cC .............. 0.36
(derate 2.06 mW/oC above 25 o C)
Watts
ELECTRICAL CHARACTERISTICS @ T A = 25 0 C unless otherwise noted
Symbol
hFE1
VCE (sat)
Min.
Typ.
Max.
40
40
20
66
63
50
120
120
30
20
71
Unit
Conditions
I c= 10mA, V CE= 1V
I c= 10mA, V CE= 0.35V
I c= 10mA, V CE= 0.35V,
T = -55 o C
I c= 30mA, V CE= OAV
I c= 100mA. V CE= 1V
0.14
0.19
0.2
0.3
Vdc
Vdc
0.17
0.28
0.25
0.5
Vdc
Vdc
9-51
I c= 10mA, I B= 1mA
I c= 10mA, I B= 1mA,
T = 1250C
Ic= 30mA, I B= 3mA
I C= 100mA, I B= 10mA
2N2369A
SILICON SWITCHING TRANSISTOR
ELECTRICAL CHARACTERISTICS @ T A = 25 0 C unless otherwise noted (continued)
Symbol
Min.
Typ.
Max.
0.7
0.59
0.8
0.85
1.02
Vdc
Vdc
0.9
1.1
1.15
1.6
Vdc
Vdc
VBE (sat)
Conditione
Unit
Ic= 10mA,IB= 1mA
I c= 10mA, I c= 1mA,
T = -65 to +125.C
Ic=- 30mA, I B= 3mA
Ic= 100mA,I B= 10mA
ICES
0.05
0.4
A
VCE= 20V, V BE= 0
leBO
10
30
A
VCB= 20V,I E= 0,
T = 150°C
fT
500
MHz
675
Cob
2.3
4.0
V CE';' 10V,I c= 10mA
pf
VCB= 5V,I E= °
Ic= IBI 10mA,
I B~= -10mA
Ts
(charge storage
time)
6.0
13
nsec
ton
9.0
12
nsec
Ic 10mA
I Bl 3mA
toff
13
18
nsec
Ic 10mA
I Bl 3mA
I B2 -1.5mA
BVCBO
40
Vdc
Ic=10 A,IE-O
BVCES
40
Vdc
Ic= 10 A, VBE= 0
VCEO (sust) 1.2
15
Vdc
Ic=10mA,IB=0
BVEBO
4.5
Vdc
I E= 10 A, I c= 0
NOTES: 1. Pulse measurement: width 300 sec. duty cycle 2%.
2.Rating refers to a high-current point where collector-to-emitter voltage is lowest.
CHARGE STORAGE TIME MEASUREMENT CIRCUIT
'"
I
.
ooon
--',-+~JI '~I
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9-52
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o.
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- Ii
2N2369A
SILICON SWITCHING TRANSISTOR
TYPICAL COLLECTOR CHARACTERISTICS1
COLLECTOR CURRENT
VERSUS COLLECTOR VOLTAGE
#~
I/O-"~'" Y
..
E 4.0
3
""
"
--
0
1.0
8
V
~~
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---- V
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00
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8.0
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«
COLLECTOR VOLTAGE
'AmA
k5'e
2.2r:.A
2.0mA
E 80
i
.~
60
0
u
00
:;:::::. I--
~/
~~:::
0.1
0.2
COLLECTOR VOLTAGE
(VeEI VOLTS
.~ >---
jc: ~
~
~
e 4.0
C:::: ~
C ~
.06(1'1A
!:!
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y
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V-
u
0
u
--- ------
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l-
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- -----------
oTm •
o.~mAIS"O
0.3
0.4
(VCE) VOLTS
1.0
.03mA
V / / /I I1II
./i/ / TA"·55°C
-
00
//1
V, II
20'f---+---l
./
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4.0
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V I
f-- ./ I
- I----" / /
02mA
F--
«
./ / /I
'8- 0
8.0
COLLECTOR VOLTAGE
12
I.
0.4
COLLECTOR VOLTAGE
IVeEI VOLTS
NOTE: Single family characteristics on Transistor Curve Tracer
9-53
I.OmA
C.SmA
COLLECTOR CURRENT
VERSUS COLLECTOR VOLTAGE
«
t.4rn~
1.2mA
O.SmA
:;:::::::-'
~ 0//' .............- --
0
'8- 0
W
W /'
"U40
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~ 20
~....- ~
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&. ;/'/"""
2
/
/
I.
12
(VeE I VOLTS
COLLECTOR CURRENT
.../ / il I
"'==::-020",'
U
0.4
0.3
V E R SUS C 0 LL ECTOR VOLTAGE
./V [11111111
. / // lA-ZSoC
../ /. '/III
../ '/ /I
~
10"0
0.2
COLLECTOR VOLTAGE
COLLECTOR CURRENT
VERSUS COLLECTOR VOLTAGE
1060 ",.,,---
o:z.",p. I - -
~~~v I---f-
(VeEI VOLTS
COLLECTOR VOLTAGE
--
/'~ ~
~7
..--;% ~ ~ V
20
I.
12
// v::-~ l---::Vh l;:%:-~6~ f..-
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d
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V
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a:
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V
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V
u 2.0
B
j
......... ep-,,°i"
r
~3.0
/'
COLLECTOR CUiiRENT
VERSUS COLLECTOR VOLTAGE
TA:125°C
(VCE) VOLTS
I
2N2369A
SILICON SWITCHING TRANSISTOR
TYPICAL COLLECTOR CHARACTERISTICS, continued
PULSED DC CURRENT GAIN
VERSUS COLLECTOR CURRENT
vc~
w
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COLLECTOR CURRENT
w
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COLLECTOR CURRENT (Ie) rnA
COLLECTOR CURRENT (le) rnA
TYPICAL BASE CHARACTERISTICS1
COLLECTOR
COLLECTOR CURRENT
VERSUS BASE
..
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..
CURRENT
VERSUS BASE VOLTAGE
VOLTAGE
100
2N2369A
SILICON SWITCHING TRANSISTOR
TYPICAL ELECTRICAL CHARACTERISTICS
COLLECTOR CURRENT
Ie .IOmA, '813,0' mAIIB2~-1.5mA,./
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25
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I
•
2N2369A
SILICON SWITCHING TRANSISTOR
TYPICAL CHARACTERISTICS, continued
FALL TIME VERSUS TURN ON
AND TURN OfF BASE CURRENTS
FALL TIME VERSUS TURN ON
AND lURN OFF BASE CURRENTS
le· IOmA
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"
LVCEO- -
00
50
75
100
AMBIENT TEMPERATURE (TAl
9-56
125
"C
IK
--
10K
SOURCE RE~'STANCE (RS)OHMS
I-
2N2480,2N2480A
-- ITT- - - - NPN SILICON DUAL TRANSISTORS
Package:
SEMICONDUCTORS
TO- 92
ABSOLUTE MAXIMUM RATINGS (each side)
Characteristics
Unit
Collector-Emitter Voltage ................. ,.................. 40 Volts
Collector-Base Voltage (2N2480) ..................... 75 Volts
Collector-Base Voltage (2N2480A) .................. 80 Volts
Emitter-Base Voltage .......................................... 5.0 Volts
Collector Current .................................................... 500 mA
Operating Junction Temperature .......................... 200°C
Storage Temperature Range ................ -65 to +200°C
Total Dissipation @T A = 25°C (one side) ...... 0.5 Watt
Derate above 25°C ................................. 2.86 mW/oC
Total Dissipation @ TC = 25°C ....................... 1.6 Watts
Derate above 25°C .................................... 9.1 mW/oC
Total Dissipation @ TA = 25°C (both sides) ... 0.6 Watt
Derate above 25°C ................................. 3.43 mW/oC
Total Dissipation@T C = 25 0 C ....................... 3.0Watts
Derate above 25°C ..... : ........................... 17.2 mW/oC
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Symbol
Min
8VCEO"
40
Volts
Ic=20mA.IB=0"
BV CBO
75
80
Volts
Volts
(2N2480) IC = 100,uA. IE = 0
(2N2480A)
5.0
Volts
IE
Max
15
0.050
ICBO
Unit
Conditions
= 100,uA. IC = 0
=
=
0.020
,uA
,uA
,uA
30 Volts. IE
O. TA = 150°C
VCB
(2N2480) VCB = 60 Volts. IE
0
(2N2480A)
50
20
nA
nA
(2N2480) VBE
(2N2480A)
= 5.0 Volts. IC =
(2N2480) IC = 100 ,uA. VCE
(2N2480A)
20
35
=
0
= 5.0 Volts
30
350
(2N2480) IC = 1.0 mAo VeE = 5.0 Volts
50
200
(2N2480A)
9-57
2N2480, 2N2480A
ElECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Svmbol
Min
Max
Unit
Conditions
VCE(sat)
1.2
1.3
Volts
Volts
(2N2480) IC = 50mA.IB = 5.0 rnA
(2N2480A)
VBE(sat)
0.9
1.0
Volt
Volt
(2N2480) IC = 50mA.IB = 5.0mA
(2N2480A)
MHz
IC = 50 rnA. VCE = 10 Volts. f = .20 MHz
fT
50
Cob
20
18
pF
pF
(2N2480) VCB = 10 Volts. IE = 0
. (2N2480A)
f= 1.0MHz
Cib
85
pF
(2N2480A) VBE
0.5 Volt.IC
f == 1.0 MHz
=
= O.
= 1.0 rnA. VCE =
f = 1.0 kHz
hie
1000
5000
ohms
(2N2480A) IC
h ib
20
35
ohms
(2N2480A) IC = 1.0 rnA. VCB = 5.0 Volts.
f
1.0 kHz
5.0 Volts.
=
hfe
50
300
hoe
4.0
16
umhos
8.0
dB
NF
(2N2480A) IC
• Pulse Test: Pulse Width :S 300 J.Ls. Duty Cycle :S 2%.
= 1.0 rnA. VCE = 5.0 Volts.
f = 1.0 kHz
(2N2480A) IC = 1.0 rnA. VCE = 5.0 Volts.
f = 1.0 kHz
IC = 0.3 rnA. VCE = 10 Volts. RS = 510 ohms.
f = 1.0 kHz. BW = 1.0 Hz
2N2483. 2N2484
-
ITT- - - - SILICON GENERAL PURPOSE TRANSISTORS
SEMICONDUCTORS
LOW LEVEL LOW NOISE NPN SILICON
PLANAR TRANSISTORS
• High Gain; 100 Min. @ I c = 10].lA (2N2484)
The ITT 2N2483 and 2N2484 are NPN silicon
planar transistors designed for application in lownoise. low-level, high-gain amplifiers in the audio
through high frequency range.
• Low noise; 3dB Max.@ Ic = 10].lA
• High VCEO ;60 Vdc Min.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Collector-to-Base Voltage............................. 60
Collector-to-Emitter Voltage (open base)..... 60
Emitter-to-Base Voltage................................
6
Collector Current.... .............. ............. ............ 50
Junction Temperature (op. and stg·)··-65 to +200
Total Power Dissipation @ Tc = 25 cC .......... 1.2
(derate 6.9 mW/cC above 25 c C)
@ Tc = 100 cC ........ 0.68
Total Power Dissipation @ T A = 25 0 C .......... 0.36
(derate 2.1 mW/oC above 25 o C)
Volts
Volts
Volts
mA
cC
Watts
Watts
Watts
ELECTRICIAL CHARACTERISTICS @ 25 0 C unless otherwise noted.
Symbol
BVcBo
LVCEO "2
BVEBO
Min.
2N2483
Typ.
Max.
60
60
6.0
60
60
6.0
hFE
40
75
100
175
80
140
200
230
280
120
30
100
175
200
250
500
10
VCE (sat)
VBE(on)
Min.
2N2484
Typ.
Max.
Conditions
Unit
Vdc
Vdc
\ldc
I c= 10].lA
Ic= 10mA
Ic= 10].lA
I C=
I C=
I c=
I c=
Ic=
I c=
I c=
1].lA, V CE= 5V
1OllA, V CE= 5V
10011A, V CE= 5V
500].lA, V CE= 5V
1mA, VCE= 5V
10mA, V CE= 5V
1011A, V CE= 5V, T A= -55 o C
200
290
375
430
450
430
800
0.2
0.57
0.35
0.7
Vdc
Vdc
I C= 1mA, I B= 0.1 mA
I c= 100].lA, V CE= 5V
500
20
0.2
0.57
0.35
0.7
ICEO
lEBO
0.1
0.2
0.1
0.1
10
10
2.0
10
0.1
0.2
0.1
0.1
10
10
2.0
10
nA
A
nA
nA
VCB= 45V
VCB= 45V, T A= 150 0 C
VCE= 5V
V EB= 5V
Cob
3.5
6.0
3.5
6.0
pF
VCB= 5V, f = 1mHt
ICBO
0.5
0.5
9-59
•
I
2N2483, 2N2484
SILICON GENERAL PURPOSE TRANSISTORS
ELECTRICIAL CHARACTERISTICS @ 25uC unless otherwise noted. (continued)
Symbol
2N2483
Typ.
Max.
Min.
Cib
3.5
hIe
2.4
2.0
80
1.5
hie
hre
hib
25
6.0
4.0
2.3
280
450
7.5
300
27
13
800
32
1.9
NF
2N2484
Typ.
Max.
Min.
3.5
3.0
2.0
150
3.5
4.0
2.6
400
Conditions
Unit
pF
6.0
V EB= 0.5V, f = 1 mHz
I e= 5()J.lA, V eE= 5V,f = 5mHz
I e= 500]1A, VeE= 5V, f = 30mHz
le= 1mA, VeE= 5V,5 = 1KHz
15
425
27
900
24
800
32
Kohms le= 1mA, VeE= 5V, f = 1KHz
X10-6 I e = 1mA, V eE= 5V, f = 1 KHz
ohms I e=1mA, V eE= 5V, f = 1 KHz
4.0
1.8
3.0
dB
I e= 1()J.lA, V eE= 5V, R G= 10K£1
B.W. = 15.7KHz3dB@10Hz&10KHz
1.9
4.0
1.8
3.0·
dB
0.7
3.0
0.6
2.0
dB
4.0
15
4.0
I e= 1()J.lA, VeE= 5V, R G= 10K£1
f = 1 KHz, B.W. = 200Hz (Note 3)
I e= 1()J.lA, V eE= 5V, R G= 10K£1
f = 10KHz, B.W. = 2KHz (Note 3)
I e= 10]1A, V eE= 5V, R G= 10K£1
f = 100Hz, B.W. = 20Hz (Note 3)
25
10
dB
Notes: 1. Pulsed width 300 sec; duty cycle 2%.
2. Lowest emitter to collector voltage.
3. Narrow band noise.
TYPICAL CHARACTERISTICS
.
0-
~
a:
a:
13
a:
tL~"~1
V
~
a
/
~
2
-'
-"
I
f--tB =.005
'"a:a:
"
a:
/
:J
0
I-
V
rn
:.l
:3.
IL
0
~
9
l).
I
00
20
40
~d~.l
.
I /'
4"'·
./
oV-
VCE -COLLECTOR VOLTAGE-VOLTS
MINIMUM DC CURRENT GAIN AT
~55·C
/
V
40
V
30
20
V
10
9l.001
z
"'"
0-
50
I
O\orn~
20
"a:
I
I
0.01
0.1
Ie· COLLECTOR CURRENT-mA
VCE 55V
700 f= r KHz
.z
600
:J
500
i:!a:
"-'
.15
400
in
300
.
-'
-'
200
~
100
~
'"
0
I-
•
'r
2
-=-
-"
00
60
•
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9-60
1i
V
ls··o05 tn j).-
-
r-
\
. \
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U
3
1.:
Till
IIII
.
I
V
20
40
60
VCE -COL.LECTOR VOLTAGE-VOLTS
.4
2~
0.1
1.0
IC~COLLECTOR CURRENT-mA
°0.001
f--
;:
-15~~~
-
(iiO""
OUTPUT CAPACITANCE
VERSUS REVERSE BIA S VOLTAGE
IIII
IIII
,/
1/
/"
'""5-'
~r
40
6
:J
I
K
9'~~
/'
a:
a:
SMALL SIGNAL CURRENT GAIN
VERSUS COLLECTOR CURRENT
70
60
~
J
/
VCE - COLLECTOR VOLTAGE-\()LTS
vERSUS COLLECTOR CURRENT
VCE =5V
V
/
.020mA
a
I-
I
a
60
...-
V
.02~"'A
~
I- ~
o~o ~
6
2
.
/
V o~" V
a
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/
f.-t§,O"'.
I/-",
I-
./
V l
0
B
-'
E
0
6·/,o~or
/
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4
.
X
~';~A
~
2N2483
COLLECTOR CHARACTERISTICS
......
;3
~0-
2
~
I
- -
'-I'E"O
:J
I
I
CD
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00
12
16
.a
Vca-REVERSE BIAS VOLTAGE-''(lLTS
4
2N2483, 2N2484
SILICON GENERAL PURPOSE TRANSISTORS
TYPICAL CHARACTERISTICS
2N2483
COLLECTOR CHARACTERISTICS (continued)
AVERAGE NOISE FIGURE
VERSUS SOURCE RESISTANCE
CONTOURS OF CONSTANT
TRANSITION FREQUENCY
veE =5V
SPOT NOISE
VERSUS
FREQUENCY
..-~tt
.
tS !
I ill
VeE- 5V
8 1\
m
1
w
w
g
'"".
6
w
•
~
u:
'"
w
15
"'z
15
f
o '01...0-, ""-'"'-:,"","-'-ll-..I.-.L...I.~
0
~
0::'"
'"
"
_u
10-4
0
!2
_u
I
2
z
~
0::'"
IC:1mA. R,·SOOfi.
'C=lmA, R.·5Kn
z
"-
Ie -COLLECTOR CURRENT-rnA
FIGURE
r-
POWER 8ANDWIOTHOF 15.7 KHZ
1 1 ill
10- 3
Rs·SOURCE RESISTANCE-OHMS
10- 2
II
I
10- 1
I
10
f -FREQUENCY - me
2N2483
CONSTANT NOISE FIGURE CO.,.TOURS
veE = 5V
l''"
t .IOOHZ
l\ • !\\ \'
5.1\\
0
'":r'"
0
5
u
z
~
ir
w
oo
w
u
oo
£"
~
6
8
10 \.
IK-
~\ \
I.
500
NF (dB)
I
I
.
V
r-
\
10
Ie . COLLECTOI:;
l\
)
'K~\
z
~
in
]:!
I
~
BANDWIDTH 22KHZ
\.
lV
200
oo"
100
100
CURRENT- vA
oo
III
"
f,l
II
,;
"-
I
10
VCE =5V f:IMHZ
./
100
"''" ,. \1\
\
6
)
1\
0
w
u
1\ \\ \
z
2K
~
IKr-
w
u
500
oo
=>
at
L\~
2
1\ 1\:
;--
NF(dB)
I
200
100
001
I
'-
\
01
'10
Ie - COLLECTOR CURRENT - ma
9-61
3
~2
3
6
IKr- 8
I
500
•~
\
"-
200
100
I
'-rr---- t-:-
NF (dB)
10
~
100
IC -COLLECTOR CURRENT-II'"
8ANDWIDTH=200KHZ
\
:r
f,l
2K \
~
Ie-COLLECTOR CURRENT-lolA
~
z
w
u
NF(dB)
'"
5Kl\:
~
8['\.
"0
":r'?
w
u
3
IK-
~,
V>
2
2K
500
oo
V
BANDWIOT H - 200HZ
w
u
w
u
r-r-- r-
I
200
100
I
L\
~
2K
veE =SV f = 1KHZ
BANDWIQTH=2QHZ
/
2N2483, 2N2484
SILICON GENERAL PURPOSE TRANSISTORS
TYPICAL CHARACTERISTICS.
2N2483
NORMALIZED COMMON EMITTER TRANSFER CHARACTERISTICS
PULSED DC CURRENT GAIN
VERSUS COLLECTOR CURRENT
EMITTER TRANSITION CAPACITANCE
VERSUS REVERSE BIAS VOLTAGE
VERSUS
...
COLLECTOR
CURRENT
h;2
FVeE:5 V
~
r - - I : I KHz
c
u
4[\
10
z
3
~
2
in
z
"'~
1/
10 hoe
~
f'-t-
I
u
0
0
4
2
6
001
0.1
8
02
VES-REVERSE 81AS VOLTAGE-VOLTS
vERSUS
VERSUS COLLECTOR VOLTAGE .
h~e
"
r--- r---
Icl'i6m1
TA'25"C
1
i4
~
i2
k"V ..... ~
" h,,~ ,""",~I-'r-
'l~
0.9 hie and hfe
t'::t
111
1
OBI
I I
o
5
10
15
20
VCE -COLLECTOR VOLTAGE-VOLTS
hi~~
JUNCTION
VCE
~
05
I
2
5
10
Ie - COLLECTOR
5V
Ie = I.Oma t-
TEMPERATURE
h re and h~
i3
hf.
~~~
01
le· O
>-
~
/h re
hie and h re
'2
>-
~
~/ h"
i2
V
1.1
/
1.0
A
o.g
vff
0.8
0.7 f-:-h oe IL~
:/::
hf.
061-'""
hie
05
-100
-50
0
50
100
Tj - JUNCTION TEMPERATUAE-"C
2N2484
COLLECTOR CHARACTERISTICS
,
""
>-
i:j
~
"'
0
~
8
_u
(j
10m~y
~.o9mA
V
8~1/
.'"
~
o
6
./
lr~"'>_
2
V
.L L
~
O~l
0·"'~ L.
4
.
102'1'
/
1
L
/
/
/'
V-r-t'B~OlmA
00
""E
~
I-
ffi
"''"u=>
"'
~
I-
a:
=>
u
"'
~
8
~
~
8
lL
","
~1L'
/.../"'
~
8~.~ /
6
4
rz:: ~C ./' L
~~
V
I-O
10
20 30 40 50 60
VCE -COLLECTOR VOLTAGE-YOLTS
L
2
002
00
.L
.......
_u
u
V
10
1
20
-
1"
30' 40
50
60
VeE - COLLECTOR VOL rAGE-VOLTS
9-62
2N2483, 2N2484
SILICON GENERAL PURPOSE TRANSISTORS
TYPICAL CHARACTERISTICS
2N2484
COLLECTOR CHARACTERISTICS (continued)
SMALL SIGNAL CURRENT GAIN
VERSUS COLLECTOR CURRENT
MINIMUM DC CURRENT GAIN AT -5S"C
VERSUS COLLECTOR CURRENT
z
VCE =5V
z
;;
'"
I-
~
'a
~
500 f=lk.c
0
u
W
z
40
~ 400
30
.
20
in
200
~
100
.J
2S"C
300
z
'"
.::J
,/
10
'6.001
0.01
0.1
1.0
001
0.1
.
4
['j
z
3
u
1f
.
\..\~\
U
~OOI
0.01
0.1
I
IC" O
1
00
2
4
a
6
REVERSE BIAS VOLTAGE - VOLTS
TRANSITION FREQUENCY
CONTOURS OF CONSTANT
'"~
I-
IOI+-+Ht-HH-rt+\N'<'t:"'d'''1
w
'"~
r--- I-
~
'-
2
u
'E=O
I
"I
11r·~ql+lH-+
11-+1++I-++tIH
100::::
r----
'!'
1.0
I!
1 's,~~'f'f
1f!-+-HlH----I
~~t..s..-rrll I
200
2
OUTPUT CAPACITANCE
VERSUS REVERSE BIAS VOLTAGE
~~400
"
30ol-ttlIb:HFHH-t-:lj1H-tttt--1
a:- ...
'"
D
~
Ocr
I-
:ii
\
.#:.-
3
Ie - COLLECTOR CURRENT-mA
PULSEO OC CURRENT GAIN
VERSUS COLLECTOR CURRENT
:i
.
lI-
III
0.001
Ie-COLLECTOR CURRENT-mA
>=
in
z
~
"55'C~
I-trrt-
0-
~
4~
0
V
u
.
';>
'"z
I-
:>
~
'"i3
u
VCE ,.5V
;;
50
EMITTER TRANSITION CAPACITANCE
VERSUS REVERSE BIAS VOLTAGE
12S"C
00
I
Ie - COLLECTOR CURRENT-mA
a
'.
REVERSE
12
I-0.1
I
IC-~OLLECTOR CURRENT-mA
16
81AS VOLTAGE - VOLTS
2N2484
CONTOURS OF CONSTANT NARROW BAND NOISE FIGURE
VCE -5V
'"
:>
"';
5.
l\\I\
w
u
z
2.
:::
'"uw
I.
~
'5
5l
",'
4
.\ a
NF (d BI
)
\
/
, \ 10
~4
I
10
IC -COLLECTOR
,.'"
'"'i'
['j
z
12
200
100
3
\.1'6
500
VCP 5V
f 100HZ BANDWIDTH- 20HZ
r-i--"
100
CURRENT-~A
~
:::
'"w
"'":>
5l
f'lKHZ
51(\
VCE -5V
BANDWIDTH-200HZ
.":
.'\
2.
I.
'" '.
'\ 6
SOO
200
a!'
10°1
I
'\ 3
I-
NFlda)
I II
5.\:
['j
z
2. \.
~
I.
l'.,
500
~
.
:;;
'"tl
'5
5l
a
BANDWIDTH-2KHZ
~.
,.'"
"'i'
2
f-IOKZ
I
10
100
1~-COLlECTOR CURRENT- ... A
9-63
,/
3
4
6
'-
200
'"
2_
~e.
NFldB)
100
I
10
100
IC-COLLECTOR CURRENT- ... A
2N2483, 2N2484
SILICON GENERAL PURPOSE TRANSISTORS
TYPICAL CHARACTERISTICS
2N2484
CONTOURS OF CONSTANT NARROW BAND NOISE FIGURE (continued)
f· I MHZ
veE z5V
BANDWIDTH' 200 KHZ
J~ 1\
"'"
~z
J:
III \(
: ,I
,*~
2Kt-,
~
!
l\~\ \\!M.2
I
I
l'\ ,\'
IK
~
"'u'"
~"
I
rr
100
001
III!
,
I)
i;
NF (dB) ,"-:
200
l;
I
,,L-/'
:\
500
Y-
i
?'
10
01
Ie-COLLECTOR CURRENT-rnA
2N2484
NORMALIZED COMMON EMITTER TRANSFER CHARACTERISTICS
AVERAGE
SPOT
NOISE
f-- VCE
5
m
"''"
""0:
"'
'"g
"'
'"
g
'~~
2
I
10
VERSUS
=V~E.'5~
hoe
COLLECTOR
TA =25°C
h"
hie ANO hre
---
I~ ;;-t;
12
1.1
hf~
10
_,hi'~
0,1
0_00 .1
0.2
0.5
I
2
5
10
Ie-COLLECTOR CURRENT-mA
/$
...,=- ~C'\~
IK
2K
5K
10K 20K
50K
d.
0.80
)::::
~
hh" ~.P
\
:::;
I-
~
-
h~
/,Vy
/ /~
"
I-- V
/p
JUNCTION
~. f- f-
1.2
&~f f- f-
lO
07I--hl'~
15
20
VCE -COLLECTOR VOLTAGE-VOLTS
9-64
I
I
-/
D.
061---10
I
l'1ie~ h"
0,8 f-- hoe / ' , /
h,.
5
TEMPERATURE
14 VcC 50V
Ie =1 OmA
13
13 \
'=:::-
Tf
'lJ
vERSUS
VOLTAGE
1~"~m1
\h oe
=,,'KHZ
10
!?
,v
Rs-SOURCE' RESISTANCE -OHMS
f -FREQUENCY-me
VERSUS COLLECTOR CURRENT
5V
,c,'
I
0
10-1
E
k- ~OWER BANDWIDT~
OF 157KHZ
~~
~
10-2
FIGURE
4l\,\
Z
10-3
NOISE
VERSUS SOURCE RESISTANCE
FIGURE
05
-100
i
I
i
n,e hii
·50
0
50
100
Tj - JUNCTION TEMPERATURE-oC
ITT
----2N2904A, 2N2905A, 2N2906A., 2N2907A
SILICON GENERAL PURPOSE TRANSISTORS
SEMICONDUCTORS
The ITT 2N2904A-7 A are PNP silicon planar
epitaxial general purpose transistors for applications at current ranges from 0.1 to 500mA. Low
saturation voltage and fast switching times make
the 2N2904A, 5A ideal for core driving. The flat
gain over a wide current range gives good linearity
in amplifier circuits. High breakdown voltage
allows large signal swing in switching and
amplifier. circuits. Designed to complement the ITT
2N2217 thru 2N2222 NPN types.
GENERAL
PURPOSE
PNP SILICON
PLANAR EPITAXIAL-TRANSISTORS
• High Voltage: ·60V min.
• Low VeE (sat): 0.4V@ 150mA
• hFE; guaranteed from 100 A to 500mA
ABSOLUTE MAXIMUM RATINGS
2N2904A2N2904A
2N2905A
2N2907AUNITS
CHARACTERISTICS
Collector-to-Base Voltage ...................... .
Collector-to-Emitter Voltage (open base) ..
BVcoo
LVCEO"l
BV EOO
h,,'
VeE(sat) ,
-60
-60
Volts
Volts
Emitter-to-Base Voltage ......................... .
Collector Current (continuous) ............... .
Junction Temperature (storage) ............ .
Total Power Dissipation @ Tc = 250C ... .
Derating factor above 25oC ............. .
-5
-5
600
600
-65 to 200
3.0
1.8
17.3
10.3
Volts
mA
oC
Watts
mW/oC
Total Power Dissipation @ T A = 25 0C ... .
Derating factor above 25 oC ............. .
0.6
3.43
Watts
mW/oC
ELECTRICAL CHARACTERISTICS
SYMBOL
-60
-60
2N2904A
2N2906A
MIN.
MAX.
-60
-60
-5
40
40
40
40
40
75
100
100
100
50
120
-0.4
-1.6
@ 25°C unless otherwise noted.
2N2905A
2N2907A
MIN.
MAX.
-60
-60
-5
0.4
2.28
Vdc
Vdc
Vdc
9-65
Ie= -101'A
Ie= -10mA
IE= -101'A
Ie=
Ie=
Ie=
le=
Ie:
300
-0.4
-1.6
CONDITIONS
UNIT
Vdc
Vdc
-1001'A
-1mA
-10mA
-150mA
-500mA
Ie= -150mA
le= -500mA
VCE=
VCE=
VCE=
VCE=
VtE=
-10V
-10V
-10V
-10V
-10V
10= -15mA
1,= -50mA
2N2904A, 2N2905A, 2N2906A, 2N2907 A
SILICON GENERAL PURPOSE TRANSISTORS
ELECTRICAL CHARACTERISTICS
SYMBOL
2N2904A
2N2906A
MIN.
MAX.
V,e(sat) I
@ 25°C unless otherwise noted.
2N2905A
2N2907A
MIN.
MAX.
le= -150mA
le= -500mA
1,= -15mA
1,= -50mA
10
10
50
50
nA
!LA
nA
nA
Vc,=
Ve,=
VeE =
VeE =
-50V
-50V
-30V
-30V
TA=150'C
V'E=0.5V
V'E=0.5V
8
30
pF
pF
Ve,= -10V
'VE,= -2V
f=100KHz
f=100KHz
le= -50mA
f=100MHz
Ic- -150mA
Vee= -10V
VeE = -20V
-1.3
-2.6
I,
10
10
50
50
Cob
C'b
8
30
leEx
h"
2
2
10
td
CONDITIONS
Vdc
Vdc
-1.3
-2.6
Ic,o
UNIT
(continued)
10
ns
1,,- -15mA
-:u: ~
200
V
0
IK
'"
40
I,
I.
40
ns
80
ns
I
-
~
SCOPE
50
-
le= -150mA I" =1" =15mA
Vee= -10V
"5
IK
37
°=U=F~ sctE
-30V
I
30
If
Notes: 1. Pulsed width :0; 300
~sec;
duty cycle <: 2%.
2. Lowest emitter to collector voltage,
9-66
ns
~
50
_
Fa
~oo_
6'
2N3011®
ITT- - - - HIGH-SPEED NPN SILICON
SATURATED SWITCHING TRANSISTOR
Package: TO-1 8
SEMICONDUCTORS
The ITT 2N3011 is an NPN silicon planar eptiaxial transistor designed specifically for high-speed
saturated switching applications in the 50-100 mc range at current levels from 100 microamperes
to 100 milliamperes. It is suitable for most small-signal. RF. and digital type circuits.
ABSOLUTE MAXIMUM RATINGS (Note 1)
NOTES:
Characteristics
Unit
Collector-Base Voltage ........................................ 30 Volts
Collector-Emitter Voltage .................................... 30 Volts
Collector-Emitter Voltage (Note 4) .................... 12 Volts
Emitter-Base Voltage .......................................... 5.0 Volts
Total Device Dissipation @:
TC = 25°C (Notes 2 and 3) ........................ 1.2 Watts
TC = 1oooe (Notes 2 and 3) ..................... 0.68 Watt
TA = 25°C (Notes 2 and 3) ....................... 0.36 Watt
Storage Temperature ...................... -65°C to +200 °C
Operating Junction Temperature ....... 200°C Maximum
Lead Temperature
(Soldering. 60 sec Time Limit) ......... 300 0 e Maximum
(1)
These ratings are lim~ing values above which the servo
iceability of any individual semiconductor device may
be impaired.
(2)
These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle
(3)
These ratings give a maximum junction temperature of
200°C and iunction-to-case thermal resistance of
146°C/watt (derating factor of 6.85 mW/oC); iunctionto-ambient thermal resistance of 486°C/watt (derating
factor of 2.06 mW/oC).
operations.
(4)
Rating refers to a high-current point where collectorvoltage is lowest.
to-em~ter
(5)
Pulse Conditions: length = 300psec; duty cycle = 1%.
(6)
See switching circuits for exact values of IC' 181' and
182 ,
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Conditions
hFE
30
70
120
hFE
25
75
IC = 30 mAo VCE = 0.4 Volt (Note 5)
hFE
12
50
IC = 100 rnA. VCE = 1.0 Volt (Note 5)
IC = 10 rnA. VCE = 0.35 Volt (Note 5)
VeE(sat)
0.17
0.2
Volt
IC = 10 mA.IB = 1.0 mA
VeE(sat)
0.18
0.25
Volt
IC = 30 rnA. IB = 3.0 mA
VeE(sat)
0.15
0.3
Volt
Ic=10mA.18= 1.0mA
VCE(sat)
0.3
0.5
Volt
Ie = 100 rnA.IB = 10 mA
0.8
0.87
Volt
IC = 10 mA.IB = 1.0 mA
VBE(sat)
0.9
1.15
Volts
IC = 30 mA.IB = 3.0mA
VBE(sat)
1.1
1.6
Volts
IC = 100 mA.IB = 10 mA
VBE(sat)
hfe
Cob
0.72
4.0
6.5
2.3
IC = 20 rnA. VCE = 10 Volts
4.0
pf
9-67
IE = O. VCB = 5.0 Volts
2N3011
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Svmbol
Min
ICES
' CES (85°C)
Conditions
Typ
Max
Unit
0.05
0.4
p.A
VCE = 20 Volts. VSE = 0
1.0
10
p.A
VeE = 20 Volts. VBE = 0
SVCBO
30
Volts
'C=10p.A·IE=0
SVeES
30
Volts
IC = 10p.A. VEB = 0
VCEO(sust)
12
Volts
Ie = 10 rnA (pulsed).IB = 0
BV EBO
5.0
Volts
'E = 100p.A. Ie = 0
TS
13
nsec
Ie = 'B 1 ~ 10 rnA.
'B2 ~ -10 rnA (Note 6)
ton
15
nsec
Ie ~ 30 rnA. 'B 1 ~ 3.0 rnA (Note 6)
toft
20
nsec
IC ~ 30 mA.IB1 ~ 3.0 rnA.
'B2 ;::: -3.0 rnA (Note 6)
SCHEMATIC
CHARGE STORAGE TIME - CONSTANT TEST CIRCUIT
0=-U
~L
Yin
-10--
'A"
890A
I 0.0023
ViIIAIi. Tim, "'" InHC
To Sampling Oscilioleolll
Input Imp,dane... 504
Rise Ti... :! I"lte
9: 10V
-
VIII RII. Tlml I,SI thon I nsec
PW==:300 nsec
c
2%
t..-!." MEASUREMENT CIRCUIT
VBB
10011
:-FI-.. . .
Vln
Puis. Source
Rise nme < I nsec
Puis' Width> 200nsec
lin' SOil
0.1
o
0.0023 I
11 v·
-9
Out, C,el.
.6v
-. v--t'---::;:::::=:::;=
91A
-\?.
.'0 -
Pulse G.n,ralor
Soure. 'mp.daM.· 504
IKJl
Voul
"-
SODA
56A
01
SODA
2KD
-Wlo---C
100 11
To 51mpll ng Scope
Rise nme < Insec
Input l .. lOOK
.".
ToIf , Vee' 2V
VBB • 7V
Ton' Vee - 2V
VBB Grounded
Vln • -13V
Vin -7V
9-68
2N3053
ITT
----NPN SILICON SWITCHING AND
AMPLIFIER TRANSISTOR
Package: TO-5
SEMICONDUCTORS
NPN SILICON SWITCHING
AND AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Collector-Emitter Voltage .................................... 40 Volts
Collector-Base Voltage ........................................ 60 Volts
Emitter-Base Voltage ............................................. 5 Volts
Collector Current - Continuous .......................... 700 mA
TotalOevice Dissipation @ TC = 25°C ............. 5 Watts
Derate above 25°C ................................. 28.6 mW/oC
Operating Junction Temperature Range ............ 200 °c
Storage Temperature Range ............... -65 to +200 °c
ELECTRICAL CHARACTERISTICS (T A
Max
= 25°C unless otherwise noted)
Symbol
Min
Unit
Conditions
BVCEO
40
Volts
IC
= 100,uA.IE = 0
BV CER
50
Volts
IC
= 100 mAo RBE = 10 ohms
BV CBO
60
Volts
IC
= 100,uA.IE = 0
BV EBO
5
Volts
IE
= 100,uA. IC = 0
I CEX
0.25
,uA
VCE 7" 60 Volts. VEB(off)
IBL
0.25
,uA
VCE
hFE
25
hFE
50
250
= 1.5 Volts
= 60Volts.VEB(off) = 1.5 Volts
IC
= 150 mAo VCE = 2.5 Volts
IC
= 150 mAo VCE = 10 Volts'
VCE(sat)
1.4
Volts
IC
= 150mA.IB = 15mA
VBE(sat)
1.7
Volts
IC
= 150mA.IB = 15mA
VBE(on)
1.7
Volts
IC
= 150 mAo VCE = 2.5 Volts
MHz
IC
= 50 mAo VCE = 10 Volts. f = 20 MHz
fT
100
Cob
15
pF
VCB
= 10 Volts. IE = O. f = 140 kHz
Cib
80
pF
VBE
= 0.5 Volt. IC = O. f = 100 kHz
. Pulse Test: Pulse Width = 300,u
S.
Duty Cycle
= 2%
9-69
2N3502,2N3503,2N3504,2N3505®
Packages:
PNP SILICON HIGH CURRENT
SWITCHING TRANSISTORS
2N3502/03. TO-5
2N3504/05. TO-18
These ITT PN P silicon planar epitaxial transistors are designed for digital and analog applications at
current levels up to 500 milliamperes. Their high beta. high fT at high current. high LVCEO' and low
noise figure make them ideal for use as line drivers. memory applications and low-noise amplifiers.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Characteristics
Unit
Storage Temperature ....................... -65°C to +200°C
Operating Junction Temperature ....... 200°C Maximum
Total Device Dissipation @:
TC = 25°C (Notes 2 and 3)
(2N3502. 2N3503) ...................................... 3.0 Watts
(2N3504. 2N3505) ...................................... 1.3 Watts
. :rA = 25° C (Notes 2 and 3)
(2N3502. 2N3503) ........................................ 0.7 Watt
(2N3504. 2N3505) ........................................ 0.4 Watt
Collector-Base Voltage
(2N3503. 2N3505) ..............................:: ..... -60 Volts
(2N3502. 2N3504) ..................................... -45 Volts
Collector-Emitter Voltage (Note 4)
(2N3503. 2N3505) ..................................... -60 Volts
(2N3502. 2N35,04) ..................................... -45 Volts
Emitter~Base Voltage
(2N3503. 2N3505) .................................... -5.0 Volts
(2N3502. 2N3504) .................................... --5.0 Volts
Collector Current (Note 2)
(2N3502. 2N3503. 2N3504. 2N3505) ...... 600 mA
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Symbol
Min
Typ
120
Max
Conditions
Unit
IC
= 10~A. VCE = -10 Volts
IC
= l00~A. VCE = -10 Volts
200
IC
= 1.0mA,VCE = -10 Volts
140
270
IC = 10 mAo VCE
(Note S)
100
lS0
hFE
2N3S03.2N3S0S.
2N3S02.2N3S04
80
hFE
2N3S03.2N3S0S.
2N3S02.2N3S04
120
hFE
2N3S03.2N3S0S.
2N3502.2N3S04
13S
hFE
2N3S03.2N3S0S.
2N3S02.2N3S04
hFE
2N3S03.2N3S0S.
2N3S02.2N3S04
300
9-70
=
= -10 Volts
IC
lS0 mAo VCE
(NoteS)
= -10 Volts
2N3502,2N3503,2N3504,2N3505
ELECTRICAL CHARACTERISTICS (T A
Symbol
= 25°C unless otherwise noted)
Min
Typ
Max
Conditions
Unit
IC = 500 mAo VCE
(Note 5)
= -lOVolts
hFE
2N3503.2N3505.
2N3502.2N3504
50
70
hFE
2N3503.2N3505.
2N3502.2N3504
115
160
300
VBE(sat)
2N3503.2N3505.
2N3502.2N3504
-0.9
-1.0
Volt
IC = 50 mAo IB
see Note 1)
VBE(satl
2N3503.2N3505.
2N3502.2N3504
-1.0
-1.3
Volts
IC = 150 mAo IB
see Note 1)
VCE(sat)
2N3503.2N3505.
2N3502.2N3504
-0.08
-0.25
Volt
IC = 50 mAo IB
see Note 1)
VCE(sat)
2N3503.2N3505.
2N3502.2N3504
-0.18
-0.4
Volt
IC = 150 mA, IB
see Note 1)
= 15 mA (Pulsed.
hfe
2N3503.2N3505.
2N3502.2N3504
2.0
IC = 50 mAo VCE
(f = 100 me)
= -20 Volts
VCEO{sust)
2N3503. 2N3505.
2N3502.2N3504
-60
-45
ton
2N3503.2N3505.
2N3502.2N3504
20
toff
2N3503.2N3505.
2N3502.2N3504
40
h FE (-55°C)
2N3503.2N3505.
2N3502.2N3504
ICES
2N3503.2N3505
0.07
10
nA
VCE
= -50 Volts. VBE = 0
ICES
2N3502.2N3504
0.05
10
nA
VCE
= -30 Volts. VBE = 0
BVCBO
2N3503.2N3505
2N3502.2N3504
-60
-45
Volts
Volts
IC
= 10~A.IE = 0
BVEBO
2N3503.2N3505.
2N3502.2N3504
-5.0
Volts
IE
= 10 ~A. IC = 0
Cob
2N3503.2N3505.
2N3502.2N3504
4.5
8.0
pf
IE
= O. VCB = -10 Volts
CTE
2N3503.2N3505.
2N3502.2N3504
15
25
pf
IC
= O. VEB = -0.5 Volt
50
IC = 50 mAo VCE
2.50
= 2.5 mA (Pulsed.
= 15 mA (Pulsed.
= 2.5 mA (Pulsed.
Volts
Volts
IC = 10 mA(pulsed).IB
(Notes 4 and 5)
40
nsee
IC ~ 300 mA.IBl ~ 30 mA
(Note 6)
100
nsec
IC ~ 300 mA.IBl ~ 30 mAo
IB2 ~ -30 mA (Note 6)
100
9-71
= -1.0 Volt
IC
=0
= 50mA,VCE = -l.OVolt
2N3502,2N3503,2N3504,2N3505
ElECTRICAL CHARACTERISTICS (T A
Symbol
NF
= 25°C unless otherwise noted)
Min
Conditions
Typ
Max
Unit
1.0
4.0
dB
IC = 30p.A. VCE
(Note 7)
2N3503.2N3505.
2N3502.2N3504
= -5.0Volts
I CBO (+150)
2N3503.2N3505
10
P.A
VCB
= -50 Volts. IE = 0
ICBO(+150)
2N3502.2N3504
10
p.A
VCB
= -30 Volts. IE = 0
VCE(sat)
2N3503.2N3505.
2N3502.2N3504
-1.6
Volts
IC = 500 rnA. IB
see Note 5)
VBE(sat)
2N3503.2N3505.
2N3502.2N3504
-2.0
Volts
IC = 500 rnA. IB = 50 rnA
(Pulsed. see Note 5)
-0.5
SMALL SIGNAL CHARACTERISTICS (f
= 50 rnA (Pulsed.
= lkc)
Conditions
Typ
Max
Unit
hie
1050
2300
Ohms
IC
= 10mA.VCE = -10 Volts
hoe
110
800
umhos
IC
= 10 rnA. VCE = -10 Volts
h re
240
1500
xl0- 6
IC
= 10 rnA. VCE = -10 Volts
200
420
Symbol
hfe
Min
135
Ic = 10 rnA. VCE = -10 Volts
NOTES:
(1)
These ratings are limiting values above which the serviceability of any individual semiconductor may be impaired.
(2)
These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
(3)
These ratings give a maximum junction temperature of 20QoC and junction-to-case thermal resistance of 58.3°C/watt (derating
factor of 17.2 mW/oC) for the 2N3502 and 2N3503. and 146°C/watt (derating factor of 6.85 mW/oC) for the 2N3504
and 2N3505: junction-to-ambient thermal resistance of 250°C/watt (derating factor of 4.0 mW/oC) for the 2N3502 and
2N3503. and 438°C/watt (derating factor of 2.28 mW/oC) for the 2N3504 and 2N3505.
(4)
Rating refers to a high-current point where collector-ta-emitter voltage is lowest.
(5)
Pulse Conditions: length = 300 J.lsec: duty cycle = 1%.
(6)
See switching circuit for exact values of I C. I B 1. and I B2'
(7)
f= 1.0Kc: RS = lOKI?
SCHEMATIC
FIGURE 1 - TON AND TOFF TEST CIRCUIT
·30V
4.0V
0.47
Vour
f---o TO SAMPLING
330
68
OSCILLOSCOPE
tr -
./
~r
o~
w
a
0:
12
~Io."'~ V
~ l-
geo
~
o~
'1'40
J
/
OozrnA
U
:;;;
1/
\
I I
0
'8=0
10
0
010203040
20
40
30
VeE -COLLECTOR'EMITTER VOLTAGE-VOLTS
VCE - COLLECTOR-EMITTER VOLTAGE-VOLTS
VCE -COLLECTOR-EMITTER VOLTAGE' VOLTS
.....
i-'"
I
0
o_~,.O
/
Collector Current vs. Collector Voltage. High Base Current
l ".,>;0- :::::: ::::: ~ ~
.."~ 800 ~~550;AA '~~ :;...: ....25m~
...-
3~~,i ~V
'1/ :,....- f-""
>-
~
~
v.. / -
600
i3
lr..;I' V
0:
~ 400
~
-
-
15mA
loLA
I
5mA
f/
J'/'
0
'7
-'"
2~
200
01'
0
oa
04
I
I.
12
IB"'O
VCE -COLLECTOR-EMITTER VOL lAGE-VOLTS
~OLLECTOR
SATURATION
TA=25°C
/. V
f- ~},.-~
40rnA ~ % V
"~BOO f- ~~t-:j;Z
,..... i.- O",J>
~"'~
ffi
II.: :/' l.-
~
~ 600
~,oo
[;l
j
0
V 200
9
,
r
~ ........
,4V .....
~
V
1'1'
011'
0 0.'
~
~
-
I ~b1c, ~ ~ .-
":...E 800 f- _).35'!'A7·7;t/" ~
30mAm? ~ V
~
a
600
~mL =
0:
I I
I I
0
"
1,'/
~ 400
j
';>
JJ,
V
200
9
0"0
"
VOLTAGE
""
18"'0
OB
0.4
I."
1.2
COLLECTOR CURRENT
,-.
Z
1->0.4
2S·C
~
E;;;:
0
10
i3
g
VI
BO
;,.-
./
,/"
0
~
.'"
II
~
100
2J.b.\
If \
JJc~
I--tftt.....
~ 40
~~ ~~~·C
10
V
ll!0:
oooC,!)
IOO·C
[11
'"z" 120
I-
g~
~
-
VCE" 5.0V
@5 go .•
>-'
U'"
~!;l
~~
ij>;
'" §o.•
IQmp.,
PULSED DC CURRENT GAIN VS
_1~Jlbl'B
!:i
~
-:IA
\smA.
VeE-COLLECTOR-EMITTER VOLTAGE-VOLTS
VCE-COLLECTOR-EMITTER VOlJAGE-\IOL.TS
VS COLLECTOR CURRENT
.
...-
..-
11/ /'
0
IB-O
O.B
~
0:
2.0!TI~
II
J- i.-
01--10
10
100
11
Ie-COLLECTOR CURRENT-mA
Ie -COLLECTOR CURRENT-mA
9-75
2N3724, 2N3725, 2N4013, 2N4014
SILICON SWITCHING TRANSISTORS
COLLECTOR CHARACTERISTICS 2N3725 2N4014
Collector Current vs. Collector Voltage. low Base Current
«
E
.:.
16
~
a:
G
12
a:
~
~ 8.0
84
2
.0
~
o·
I
~.
V
~ / //
E
;..z
\4(f\P-
a
w
a:
~
V
r-- VI
~
mA "..... LL
=-o,oe
~
V
40
a:
~ 1.0
w
?'1-~0"'V
..""
14..""
_f-P'" loa ~""
0
\
o.04rn!;:
20
I-p
i--'
0-10'" if
"--'--'
O.02mA
0
12
60
r..:: 4.0
1-1---1"'0 °'1'1
I I fiB~O \
2
'8=0
0
BO
0
20
40
SO
BO
VeE -COLLECTOR-EMITTER VOLTAGE-VOLTS
VeE -COLLECTOR-EMITTER VOLTAGE- VOLTS
VCE - COLlECTOR-:MtTTER VOLTAGE-VOL T~
~~I
IS
~ ~
o 200
---
TA=25°C
:;..- ;...- -,~-.OJ ""
I
E
I 800
0:
15mA.
10mA
'/
400
~
~
0
1>
" 200
tmj-
II
iB~L
II"
)
0
1.6
J' _L
04
°
OB
16
12
VCE~COLLECTOR -EMITTER VOLTAGE -VOLTS
PULSED DC CURRENT GAIN
YS
COLLECTOR CURRENT
~
VCE=5.0Y
z
'<
II
'"z 120
I-
IJ
frl~
~1!
~
~02
Q
5
~~
8~
G
ICOOC
1.0
"
~~
¥
40
w
1!10
v
n
-sl.l
.++
~
II
,/
/'
"-
-~5·C
I I
BO
2~·b
,/
i:!
0:
'IJ
'f.~O.4
0
.....zom.
"
0
~
-v.. .- -'.Ii.~V
.F/ /'
600
VCE - COLLECTOR -EMIT TER VOLTAGE-vOL T5
leU !!
~ ~O.6
"
-
i:!
COLLECTOR SATURATION VOLTAGE
VS COLLECTOR CURRENT
'"~
-
z>-
40m.> ;...~~
/.,"./ ..... ~
O~
LO
100
Ie -COllECTOR CURRENT -mA
'"
10
100
II
Ie-COLLECTOR CURRENT-mA
9-76
\
\
'-
2N3724, 2N3725, 2N4013, 2N4014
SILICON SWITCHING TRANSISTORS
COLLECTOR CHARACTERISTICS 2N3724 2N3725 2N4013 2N4014
Collector Current vs. Base-Emitter Voltage
TA=25°C
.,
E
~
a'"
IOOmA
~/'40mA
GO~A
IL
800
1'~Om~ - -
GOO
,-- f-
.",
0
I
1 200
'/
o.
BASE SATURATION VOLTAGE
vs
AMBIENT
...
0
>-
"'!:i
~
z
~~
~
iii
....
I~
0.4
V
,/
~
!~
~
--
_55°C
"'
~~O.8
~
-~
100
10
Ie-COLLECTOR CURRENT-mA
CONTOURS OF CONSTANT BANDWIDTH
PRODUCT (fr)
~
c::
:::il
~~
35J!!t /
.
0
~
0.1
1.0
TTtt!l1
50
100
,///,
1.2
0.8
0.'
COLLECTOR CUTOFF CURRENT VS
REVERSE
...
BIAS
VOLTAGE
T~'25!C
-
>- 04
!
"./'
0.3
V
~
~
V
02
".-
'"
8::J
0.1
a
a
25
50
TA-AMBIENT
75
100
TEMPERATURE .oC
?
~
0.1
a
a
6
~ ",5
~ ~4
"'.
/
If
>~
2
I
'oil
1
/
/
L
20
30
V
'0
I
~
~oJ
J
L
./
0
V
/
~~oL
.,II V
..~"g
500
60
t-ol/i
~ ~3
'e-COLLECTOR CURRENT-rnA
40
CURRENT AND REVERSE BASEEMITTER VOL rAGE
VOLTAGE
'"~
V
20
VCB -COLLECTOR-BASE VOLTAGE, VOLTS
DELAY TIME VS TURN ON BASE
INPUT AND OUTPUT CAPACITANCE VS
REVERSE BIAS
1.6
lIeE-BASE- EMITTER VOLTAGE-VOLTS
~
~ r--b:!: W~~'/
'f
'/I '/
Ill,
a
a
1.6
1.0
r--- ts~50MHZ
..J
..J
12
V
400MHZ/
LO
~
./
Vce=40V
10
It:
~
~/,'I
..J
TEMPERATURE
4~uMHz
"'t:>-
lUll
II/ II
" zoo
.9
~
8
La
~
~18O~A- r-
~
f- f- lel• 2O'....
600
~ 400
1l
~
>
a
>-
r.J.-'40mA
GomAI
800
COLLECTOR CUTOFF CURRENT VS
-I~.I,J!B
z
0.8
III I
IOOmA
E
IIeE -BASE-EMITTER VOLTAGE- VOLTS
COLLECTOR CURRENT
!aU) 1.2
IVI 'I
00
..
~
/ '/1/
II III/
,/JIJ
a
IG
VSE -BASE-EMITTER VOLTAGE-VOLTS
1/
IL
.1> 200
I/lm ,2
08
00
le=20mA
::J
/1'/
a
a
a~ 600
8
/,
8
I'~O~A-l.
-)
ISOmA
IOOmA
r 800 r-- t- -HGO~A
>-
::'"fd 400
le: 2OmA
>~ 400
I
~
/ ,p~
0:
0:
,/
~
z
0:
.
~1
130
V
I
IC"SOOmA
VCC'3OV
E
f-/'
0
...."
.,
I
II
... 20
STORAGE TIME VS TURN ON AND
TURN OFF BASE CURRENTS
!:::
r
10
5
,..,
-- ~"""
..."
~"""
I,~
;::::0
I,
I.
le·SOOmA
"-
2 _IC"O 'BI"'O IB2
2
I
Vee =30V
I
-30
0
~O
100
TA·-AMBIENT. TEMPERATURE·-C
VCC"30V
I
.
Ic-COL~~TOR CURR~NT-mA
9-78
IS 1s IS 2 s50mA
2N3903, 2N3904
Package: TO-92
NPN SILICON GENERAL PURPOSE SWITCHING
AND AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Collector-Emitter Voltage .....................................40 Volts
Collector-Base Voltage ........................................ 60 Volts
Emitter-Base Voltage .......................................... 6.0 Volts
Collector-Current ..................................................:200 rnA
Total Device Dissipation@ TA = 25°C ........... 310 mW
Total Device Dissipation@TA = 60°C ........... 210 mW
Derate above 25°C ................. ;............... 2.81 mW/oC
Operating and Storage Junction
Temperature Range ........................... - 55 to + 13& °c
Thermal Resistance.
Junction to Ambient.. ......................... :.... 0.357· °C/mW
ELECTRICAL CHARACTERISTICS (TA = 25° C unless otherwise noted)
Symbol
Min
BVCBO
60
Volts
IC
= 10~A.IE = 0
BVCEO·
40
Volts
IC
= 1.0 rnA. IB = o·
BVEBO
6.0
Volts
IE
= 10~A.IC = 0
ICEX
Max
50
Unit
nA
Conditions
VCE
= 30 Volts. VEB(off) = 3.0 Volts
h FE •
20
IC
= 0.1
rnA. VCE
= 1.0 Volt (2N3903)
h FE •
40
IC
= 0.1
rnA. VCE
= 1.0 Volt·
hFE*
35
IC
= 1.0 rnA. vCE = 1.0 Volt (2N3903)
hFE •
70
IC
= 1.0 rnA. VCE ,;.
hFE •
50
150
IC
= 10 rnA. VCE = 1.0 Volt t2N3903)
hFE"
100
300
IC
= 10 rnA. VCE = 1.0 Volt (2N3904)
hFE"
30
IC
= 50 rnA. VeE = 1.0 Volt (2N3903)
hFE •
60
IC
= 50 rnA. VeE = 1.0 Volt (2N3904)
h FE •
15
IC
= 100 rnA. VeE = 1.0 Volt (2N3903)
hFE •
30.
IC
= 100 rnA. VeE = 1.0 Volt (2N3904)
9-79
(2N3904)
1.0 Volt (2N3904)
2N3903,2N3904
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Symbol
Min
Max
Conditions
Unit
VCE(sat)*
0.2
Volt
IC= 10mA.IB = 1.0mA*
VCE(sat)*
0.3
Volt
IC = 50 rnA. IB = 5.0 rnA
0.85
Volt
IC = 10 mA.IB = 1.0 mAo
0.95
Volt
IC = 50 mA.IB = 5.0 rnA
VBE(sat) *
0.65
VBE(sat) •
fT
250
MHz
IC = 10 rnA. VCE = 20 Volts
f = 100 MHz (2N3903)
fT
300
MHz
IC = 10 rnA. VCE = 20 Volts
f = 100 MHz (2N3904)
Cob
4.0
pF
VCB = 5.0 Volts. IE = O. f = 100 kHz
Cib
8.0
pF
VBE = 0.5 Volt.IC = O. f = 100 kHz
hie
0.5
8.0
k ohms
IC = 1.0 mAo VCE = 10 Volts.
f = 1.0 kHz (2N3903)
hie
1.0
10
kohms
IC= 1.0mA.VCE= 10 Volts.
f = 1.0 kHz (2N3904)
h re
0.1
5.0
X 10- 4
IC = 1.0 rnA. VCE = 10 Volts.
f = 1.0 kHz (2N3903)
h re
0.5
8.0
X 10- 4
IC = 1.0mA,VCE = 10 Volts.
f = 1.0 kHz (2N3904)
hfe
50
200
IC = 1.0 mAo VCE = 10 Volts.
f = 1.0 kHz (2N3903)
hfe
100
400
IC = 1.0 mAo VCE = 10 Volts.
f = 1.0 kHz (2N3904)
hoe
1.0
40
,umhos
td
35
ns
VCC = 3.0 Volts. VB E(off) = 0.5 Volt.
tr
35
ns
IC = 10 mA.IB1 = 1.0 mA
ts
175
ns
VCC = 3.0 Volts. IC = 10 mAo IB 1 =
IC = 1.0 mAo VCE = 10 Volts.
f = 1.0 kHz
IB2 = 1.0 mA (2N3903)
9-80
2N3903.2N3904
ELECTRICAL CHARACTERISTICS (T A = 25° e unless otherwise noted)
Symbol
Min
ts
Max
Unit
200
ns
Conditions
Vee
IS2
50
tf
ns
Vee
IS2
• Pulse Test: Pulse Width
= 3.0 Volts. Ie = 10 mA.IS1 =
= 1.0 mA
= 3.0 Volts. Ie = 10 mA.IS1 =
= 1.0 mA
= 300~s. Duty Cycle = 2%.
SCHEMATIC
FIGURE 1 - DELAY AND RISE TIME
EQUIVALENT TEST CIRCUIT
+3.0V
FIGURE 2 - STORAGE AND FALL TIME
EQUIVALENT TEST TIME
+3.0V
10.< t1 <500 us
DUTY CYCLE
=2%
L.j t1
~+10.9V
<~~gp ,""
'Total shunt capacitance of test jig and connectors
9-81
2N3905, 2N3906
PNP SILICON GENERAL PURPOSE SWITCHING
AND AMPLIFIER TRANSISTORS
Package' TO- 92
ABSOLUTE MAXIMUM RATINGS
Characteristics
Unit
Collector-Emitter Voltage .................................... 40 Volts
Collector-Base Voltage ........................................ 40 Volts
Emitter-Base Voltage .......................................... 5.0 Volts
Collector Current ................................................. 200 mA
Total Device Dissipation @ TA = 25°C ........... 310 mW
Total Device Dissipation@TA = 60°C ........... 210 mW
Derate above 25°C ................................. 2.81 mW/oC
Operating and Storage Junction
Temperature Range ........................... -55 to 135°C
Thermal Resistance. Junction to
Ambient ..................................................... 0.357 °C/mW
+
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Max
Unit
Conditions
Symbol
Min
BVCBO
40
Volts
IC = 10,uA.IE = 0
BVCEO*
40
Volts
IC = 1.0 mAo IB = 0
BV EBO
5.0
Volts
IE = 10,uA.IC = 0
I CEX
50
nA
VCE = 30 Volts. VBE(off) = 3.0 Volts
IBL
50
nA
V CE = 30 Volts. VB E(off) = 3.0 Volts
hFE*
30
60
(2N3905) IC = 0.1 mAo VCE = 1.0Volt
(2N3906)
hFE*
40
(2N3905) IC = 1.0 mAo VCE = 1.0Volt
(2N3906)
80
(2N3905) IC = 10 mAo VCE = 1.0Volt
(2N3906)
150
300
hFE*
50
100
hFE*
30
60
(2N3905) IC = 50 mAo VCE = 1.0 Volt
(2N3906)
15
(2N3905) IC = 100mA.VCE = 1.0Volt
(2N3906)
hFE*
30
VCE(sat) *
0.25
Volt
IC= 10mA.IB = 1.0mA
0.4
Volt
IC = 50 mA.IB = 5.0 mA
9-82
2N3905,2N3906
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Symbol
Min
Max
VB E(sat)'
0.65
0.85
0.95
fT
200
250
Unit
Conditions
Volt
Volt
IC = 50 rnA. IB = 5.0 rnA
MHz
MHz
(2N3905) IC = lOrnA. VCE = 20 Volts.
(2N3906)
f=100MHz
IC=10mAIB=1.0mA
Cob
4.5
pF
VCB = 5.0 Volts. IE = O. f = 100 kHz
Cib
10
pF
VBE = 0.5 VOIt.IC = O. f = 100 kHz
hie
0.5
2.0
8.0
12
k ohms
k ohms
(2N3905) IC = 1.0 rnA. VCE = 10 Volts.
(2N3906)
f = 1.0 kHz
h re
0.1
1.0
5.0
10
X 10- 4
X 10-4
(2N3905) IC = 1.0 rnA. VCE = 10 Volts.
(2N3906)
f = 1.0 kHz
hfe
50
100
200
400
hoe
1.0
3.0
40
60
tlmhos
tlmhos
(2N3905) IC = 1.0 rnA. VCE = 10 Volts.
(2N3906)
f = 1.0 kHz
5.0
dB
4.0
dB
(2N3905) IC = 100 tlA. V CE = 5.0 Volts.
(2N3906)
RS = 1.0 k ohm. f = 10Hz
to 15.7 kHz
td
35
ns
VCC
tr
35
ns
IC
ts
200
225
ns
ns
(2N3905) VCC = 3.0 VOlts.IC = 10 rnA.
(2N3906)
IBl = IB2 = 1.0mA
tf
60
75
ns
ns
(2N3905) VCC = 3.0 Volts. IC = lOrnA.
(2N3906)
IBl = IB2 = 1.0mA
NF
• Pulse Test: Pulse Width
(2N3905) Ie = 1.0 rnA. VCE = 10 Volts.
(2N3906)
f = 1.0 kHz
= 300 f..ls. Duty Cycle = 2.0%.
9-83
= 3.0 Volts. VBE(off) = 0.5 Volt.
= 10mA.IBl = 1.0mA
I
."
2N3905, 2N3906
SCHEMATIC
FIGURE 1 - DELAY AND RISE TIME EQUIVALENT TEST CIRCUIT
-3.0V
1r-''WII....-+-i
10.9V
~ tl~
10 < tl <500 us
DUTY CYCLE = 2%
°Total shunt capacitance of test jig and connectors
9-84
2N3962,2N3963,2N3964,2N396S®
PNP SILICON LOW-LEVEL.
LOW-NOISE TYPE TRANSISTORS
Package: TO-18
• LOW NOISE FIGURE .............................. NF = 2.0 dB (MAX) AT 1.0 kHz
NF ='4.0 dB (MAX) AT 100 Hz
• HIGH CURRENT GAIN ........................_....... hFE = 180 (MIN) AT 1.0~A
hFE =; 250 - 500 AT 10~A
hFE = 250 - 600 AT 1.0 mA
• HIGH BREAKDWON VOLTAGE ......... LV CEO = 45. 60 AND 80 VOLTS
• EXCELLENT BETA LINEARITY ......................... FROM 1.0tLAT050mA
ABSOLUTE MAXIMUM RATINGS (Note 1)
Characteristics
Unit
Collector-Base Voltage
(2N3962. 2N3965) ..................................... -60 Volts
(2N3963) ...................... : ................................ -80 Volts
(2N3964) ....................................................... -45 Volts
Collector-Emitter Voltage (Note 4)
(2N3962. 2N3965) ..................................... -60 Volts
(2N3963) ....................................................... -80 Volts
(2N3964) ....................................................... -45 Volts
Emitter-Base Voltage
(2N3962, 2N3963, 2N3964, 2N3965) -6.0 Volts
Total Device Dissipation @:
TC = 25°C ................... , ................................. 1.2 Watts
TA = 25°C .................................................... 0.36 Watt
Storage Temperature ...................... - 65°C to +200 °c
Operating Junction Temperature .......................... 200°C
Lead Temperature
(Soldering, 60 sec Time Limit) ........................... 300 °c
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
,
Symbol
Min
Typ
hFE
2N3962,2N3963
2N3964,2N3965
60
180
175
300
hFE
2N3962,2N3963
2N3964,2N3965
100
250
210
320
hFE
2N3962,2N3963
2N3964,2N3965
100
250
240
330
hFE
2N3962,2N3963
2N3964,2N3965
100
250
260
330
Max
300
500
450
600
9-85
Unit
Conditions
Ie
= 1.0 IlA VeE = -5.0 Volts
Ie
= IOIlA VeE = -5.0 Volts
Ie
= l00~A, VeE = -5.0 VollS
Ie
= 1.0 mA, VeE = -5.0 Volts
2N3962,2N3963,2N396~2N3965
ELECTRICAL CHARACTERISTICS (TA = 25 0 ( : unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Conditions
hFE
2N3962.2N3963
2N3964.2N3965
100
200
280
300
IC = 10 mAo VCE = -5.0 Volts (Note 5)
hFE
2N3962.2N3963
2N3964.2N3965
90
180
260
315
IC = 50 mAo VCE = -5.0 Volts INote 5)
hFEI-55°C)
2N3962.2N3963
2N3964.2N3965
40
100
90
160
IC = IOIlA. VCE = -5.0 Volts
hFEI-55°C)
2N3962.2N3963
2N3964.2N3965
45
90
150
190
IC = 50 mAo VCE = -5.0 Volis INote 5)
375
400
hFEI+ 1000 C) 2N3962.2N3963
2N3964.2N3965
600
800
IC = 1.0 mAo VCE = -5.0 Volts
8VC80
2N3962
2N3964
-60
-45
Volts
Volts
IC = IOIlA.IE = 0
8VC80
2N3963
2N3965
-80
Volts
Volts
IC=101lA.IE=0
2N3962
2N3964
-60
Volts
Volts
IC = 101lA.IB = 0
-45
BVCES
2N3963
2N3965
-80
-60
Volts
Volts
IC = IOIlA.IB = 0
VCEOlsust)
2N3962
2N3964
-60
-45
Volts
.Volts
·IC = 5.0 mA Ipulsed).18 = 0 INotes 4 and 5)
VCEOIsust)
2N3963
2N3965
-80
-80
Volts
Volts
IC = 5.0 mA Ipulsed/.IB = 0 INotes 4 and 5)
BVEBO
2N3962.2N3963
2N3964.2N3965
-6.0
Volts
IC = O. IE = 10llA
NF
2N3962.2N3963
2N3964.2N3965
1.0
0.7
3.0
2.0
dB
dB
IC = 20IlA. VCE = -5.0Volis
Rs = 10 kohms. 8W '= 15.7 kHz
NF
2N3962.2N3963
2N3964.2N3965
0.8
0.5
3.0
2.0
d8
dB
IC ~ 20IlA. VCE = -5.0Volts.
RS = 10 kohms. 8W = 1.5 kHz
NF
2N3962.2N3963
2N396~. 2N3965
0.8
0.5
3.0
2.0
d8
dB
IC = 201lA. VCE = -5.0 Volts.
RS = 10 kohms. BW = 150 Hz
NF
2N3962.2N3963
2N3964.2N3965
3.0
1.8
10
4.0
dB
dB
IC = 20IlA;VCE = -5.0 Volts.
RS = 10 k ohms. BW = 15 Hz
NF
2N3964.2N3965
3.5
8.0
d8
IC = 201lA. VCE = -5.0Volts.
RS = 10 kohms. BW = 2.0 Hz
ICES
2N3962
2N3965
0.5
10
nA
VCE = -50 Volts. VE8 = 0
BVCES
-60
9-86
2N3962,2N3963,2N3964,2N3965
ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Symbol
Min
2N3963
ICES
Typ
Max
Unit
0.5
10
nA
= -70 Volts. VEB = 0
VCE = -40 Volts. VEB = 0
VCE
= -50 Volts. VEB = 0
= -70 Volts. VEB = 0
Conditions
VCE
2N3964
0.5
10
nA
I CES(+150°C) 2N3962
2N3965
2.0
0.5
10
10
IlA
ICES(+1500C) 2N3963
2.0
10
IlA
VCE
ICES (+1500C) 2N3964
2.0
10
IlA
VCE
10
nA
= -40 Volts. VEB = 0
Ic = O. VEB = -4.0 Volts
ICES
IlA
lEBO
2N3962.2N3963
2N3964.2N3965
VCE(sat)
2N3962.2N3963
2N3964.2N3965
-0.1
-0.25
Volt
IC
= 10 mA.IB = 0.5 rnA
VCE(sat)
2N3962.2N3963
2N3964.2N3965
-0.16
-0.4
Volt
Ie
= 50 rnA. IB = 5.0 rnA (Note 5)
VBE(sat)
2N3962.2N3963
2N3964.2N3965
-0.72
-0.9
Volt
IC
= 10mA.IB = 0.5 rnA
VBE(sat)
2N3962.2N3963
2N3964.2N3965
-O.Bl
-0.95
Volt
IC
= 50 rnA: IB = 5.0 rnA (Note 5)
'"::.,
:,,~,
•
I
hie
2N3962.2N3963
2N3964.2N3965
2.5
6.0.
B.O
10
17
20
kohms
kohms
·IC
= 1.0 rnA. VCE = -5.0 Volts
hoe
2N3962.2N3963
2N3964.2N3965
5.0
5.0
19
25
40
50
Ilmho
/lmho
IC
= 1.0 rnA. VCE = -5.0Volts
h re
2N3962.2N3963
2N3964.2N3965
10
Xl0- 4
IC
= 1.0 rnA. VCE = -5.0 Volts
hIe
2N3962.2N3963
2N3964.2N3965
100
250
550
700
IC
= 1.0 rnA. VCE = -5.0Volts
hIe
2N3962.2N3963
2N3964.2N3965
2.0
2.5
8.0
8.0
IC
= 0.5 rnA. VCE = -5.0 Volts
Cobo
2N3962.2N3963
2N3964.2N3965
6.0
pF
IE
= O. VCB = -5.0Volts
Cibo
2N3962.2N3963
2N3964.2N3965
15
pF
IC
= O. VEB = -0.5 Volt
300
360
NOTES:
(1)
These ratings are limiting values above which the serviceability 01 any individual semiconductor device may be impaired.
(2)
These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
(3)
These ratings give a maximum junction temperature 01 200°C and junction-to-case thermal resistance 01 146°C/watt (derating
factor of S.85 mW/oC); junction-to-ambient thermal resistance of 48SoC/watt (derating factor of 2.0S mW/oC).
(4)
This rating refers to a high-current point where collector-to-emitter voltage is lowest.
(5)
Pulse Conditions: length
= 300IlS; duty cycle = 1%.
9-87
I
2N4123,2N4124
GENERAL PURPOSE NPN SILICON
SWITCHING AND AMPLIFIER TRANSISTORS
Total Device Dissipation
ABSOLUTE MAXIMUM RATINGS
Characteristic
2N4123
Collector-Emitter Voltage .......
30
Collector-Base Voltage ...........
40
2N4124 Unit
25
Vdc
@T A = 25 0 C .....................
Derate above 25 0 C .............
30
Vdc
Operating and Storage Junction
Emitter-Base Voltage ..............
5.0
Vdc
Collector Current....................
.. 200
mAdc
Total Device Dissipation
mW
mW/oC
Temperature Range ............ -55 to +135
to Ambient ........................ .
mW
210
310
2.81
°C
Thermal Resistance, Junction
--------------~-----------------
@T A = 60°C ..............: ...... .
Package: To-92
0.357
------------------------------
0C/mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
30
Vdc
25
-
40
-
Vdc
30
-
BV EBO
5.0
-
Vdc
IE = 10uAdc, IC =0
ICBO
-
50
nAdc
V CB - 20 Vdc; IE - 0 .
lEBO
-
50
hFE*
150
nAdc
-
V BE = 3 Vdc, IC - 0
50
120
360
25
-
60
-
VCE(sat) *
-
0.3
VBE(sat)*
[hfel
2.5
BV CBO
0.95
-
Conditions
I C =1mAdc,I E =0
2N4123
2N4124
2N4123
IC = 10uAdc, IE =0
2N4124
2N4123
IC = 2 mAdc, VCE = 1 Vdc
2N4124
2N4123
IC = 50 mAdc, V CE = 1 Vdc
2N4124
Vdc
IC = 50 mAdc, IB = 5 mAdc
Vdc
IC 50 mAdc, IB - 5mAdc
IC - 10 mAdc, V CE - 20 Vdc,
-
2N4123
f=100MHz
fT
3.0
-
250
-
2N4124
MHz
IC = 10 mAdc, V CE = 20 Vdc,
2N4123
f=100MHz
Cob
Cib
h fe
300
-
-
4.0
2N4124
pF
V CB =5Vdc, IE =O,f= 100kHz
-
8.0
pF
V BE
50
200
-
IC - 2 mAdc, V CE
120
480
-
6.0
f
NF
= 1 kHz
2N4124
dB
IC = 100uAdc, VCE = 5 Vdc,
RS
-
= 0.5 Vdc, IC - 0, f - 100 kHz
2N4123
= 1 Vdc,
Noise Bandwidth
5.0
2N4123
= 1 k ohm,
= 10 Hz to
15.7 kHz
2N4124
td
t
r
ts
tf
Typ.24
ns
Typ.13
ns
Typ.125
ns
Typ.11
ns
= 3 Vdc, V E B(off) = 0.5 Vdc,
Rise Time IC = 10 mAdc, IB1 = 1 mAdc
Storag.eTinie VCC - 3Vdc, IC = 10mAdc,
Fall Time
IB1 = IB2 = 1 mAdc
Delay Time V CC
*Pulse Test: Pulse Width = 300 us, Duty Cycle = 2%.
9-88
2N4125,2N4126.
GENERAL PURPOSE NPN SILICON
SWITCHING AND AMPLIFIER TRANSISTOR
Package: To-92
ABSOLUTE MAXIMUM RATINGS
Characteristic
Total Device Dissipation
2N4125
Collector-Emitter Voltage .......
30
Collector-Base Voltage .............
30
2N4126 Unit
25
25
4.0
Emitter-Base Voltage ...............
Vdc
@T A = 25 0 C .................... ..
Derate above 250 C ............ .
Vdc
Operating and Storage Junction
@T A
= 60 0 C ...................... .
210
mW
mW/oC
Temperature Range ............ -55 to +135
Vdc
Collector Current ....................
200
mAde
=T:-o-ta71=D-ev--=i-ce---=D-:-iss--=i-pa-t-:-io-n-----------
310
2.81
Thermal Resistance, Junction
to Ambient ........................ .
0.357
°C
0C/mW
mW
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
30
-
Vdc
IC = 1 mAde, IE = 0
2N4125
25
-
BV CBO
30
-
Vdc
IC = 10uAdc,IE =0
2N4125
25
-
BV EBO
4.0
-
Vdc
IE = 10 uAdc, IC = 0
ICBO
-
50
nAdc
V CB = 20 Vdc, IE - 0
lEBO
-
50
nAdc
V BE - 3Vdc,I C - 0
hFE*
50
150
-
IC - 2 mAde, VCE - 1 Vdc
2N4125
120
360
25
-
IC = 50 mAde, V CE '" 1 Vdc
2N4125
60
0.4
-
0.95
VCE(sat)*
-
V BE (sat) *
hfe
2.0
-
2.5
-
fT
200
-
Conditions
2N4126
,
2N4126
i
2N4126
2N4126
Vdc
IC = 50 mAdc,l B = 5 mAde
Vdc
IC - 50 mAdc,l B - 5 mAde
-
IC= 10 mAde, V CE - 20 Vde,
f=100MHz
MHz
IC = 10 mAde, V CE = 20 Vde,
2N4125
2N4126
2N4125
f=100MHz
Cob
Cib
hfe
NF
250
-
-
4.5
pF
V CB = 5 Vde, IE = 0, f = 100 kHz
-
10
pF
-
V BE = 0.5 Vdc,I C - 0, f - 100 kHz
2N4125
IC - 2 mAde, V CE - 1 Vde,
f = 1 kHz
dB
IC = 100 uAde, V CE = 5 Vde, RS = 1 ohm,
50
200
120
480
-
5.0
-
4.0
2N4126
2N4126
2N4125
Noise Bandwidth = 10Hz to 15.7 kHz
2N4126
Typ 25
ns
tr
Typ 18
ts
tf
Typ 140
Typ 15
td
*Pulse Test: Pulse
Wid~h
Delay Time
V CC = 3 Vde, V BE (off) - 0.5 Vde,
ns
Rise Time
IC - 10 mAde, IBl - 1 mAde
ns
Storage Time V CC = 3 Vde, IC - 10 mAde,
ns
Fall Time
= 300 usee, Duty Cycle = 2%.
9-89
IBl - IB2 - 1 mAde
I
®
2N4248,2N4249,2N4250
PNP SILICON LOW LEVEL LOW NOISE
AMPLIFIER TRANSISTORS
•
•
•
•
Package:TO-92
Low Noise Figure .................................................. 2.0 dB (max) at 1.0 kHz
High Current Gain ....................................................... 250-700 at 100.uA
High Breakdown .......................................... .40 and 60 Volts (min) LV CEO
Excellent Beta Linearity ............................................. From l.uA to 50 mA
ABSOLUTE MAXIMUM RATINGS (Note 1)
Characteristics
Unit
Storage Temperatures ......................... - 55°C to 125°C
Operating Junction Temperatures ........................ 125° C
Lead Temperature (Soldering.
10 seconds time limit) .......................................... 260°C
Total Device Dissipation (Notes 2 and 3)
@T C = 25°C .................................................. 0.5 Watt
@ TA = 25°C .................................................. 0.2 Watt
Collector-Base Voltage
(2N4248. 2N4250) ..................................... -40 Volts
(2N4249) ....................................................... -60 Volts
Collector-Emitter Voltage
(2N4248. 2N4250) ..................................... -40 Volts
(2N4249) ....................................................... -60 Volts
Emitter-Base Voltage
(2N4248. 2N4250) .................................... -5.0 Volts
(2N4249) ...................................................... -5.0 Volts
ELECTRICAL CHARACTERISTICS (T A
Symbol
NF
NF
NF
= 25°C unless otherwise noted)
Typ
Max
Unit
2N4248
2N4249
0.7
0.7
3.0
dB
dB
2N4250
0.5
2.0
dB
2N4248
1.0
2N4249
1.0
3.0
dB
2N4250
0.7
2.0
dB
2N4248
0.8
2N4249
2N4250
0.8
0.7
2N4248
2N4249
90
190
2N4250
300
Min
dB
dB
3.0
2.0
2N4248
2N4249
50
100
100
240
300
2N4250
250
350
700
9-90
dB
dB
Conditions
IC = 20/J.A. VCE
(Note 6)
= -5.0 Volts
IC = 20/J.A. VCE
(Note 7)
= -5.0 Volts
IC = 250/J.A. VCE
(Note 8)
= -5.0 Volts
IC
= 1O/J.A. VCE = -5.0 Volts
IC
= 1oo/J.A. VCE = -5.0 Volts
2N4248,2N4249,2N4250
ELECTRICAL CHARACTERISTICS (TA
Symbol
= 25°C unless otherwise noted)
Min
Typ
2N4248
2N4249
50
100
110
250
2N4250
250
350
2N4248
2N4249
50
100
120
280
2N4250
250
350
BVCBO
2N4248.2N4250
2N4249
-40
-60
Volts
Volts
IC
= 10jlA.IE = 0
BVCES
2N4248.2N4250
2N4249
-40
-60
Volts
Volts
IC
= 10jlA
VCEO(sust)
2N4248.2N4250
2N4249
-40
-60
Volts
Volts
IC = 5.0 mA (pulsed). IB
(Notes 4 and 5)
BV EBO
2N4248.2N4249.
2N4250
-5.0
Volts
IC
= O. IE = 10jlA
ICBO
2N4248.2N4249.
2N4250
10
nA
IE
= O. VCB = -40 Volts
ICBO (65°C)
2N4248.2N4249.
2N4250
3.0
jlA
IE
= O. VCB = 40 Volts
lEBO
2N4248.2N4249.
2N4250
20
nA
IC
= O. VBE = 3.0 Volts
VCE(satl
2N4248.2N4249.
2N4250
-0.25
Volt
IC
10 mAo IB
(Note 5)
= 0.5 mA
VBE(sat)
2N4248.2N4249.
2N4250
-0.9
Volt
IC = 10mA.IB
(Note 5)
= 0.5mA
hFE
hFE
Max
Conditions
IC
= 1.0 mAo VCE = -5.0 Volts
IC = 10 mAo VCE
(Note 5)
2N4248
2N4249
50
100
250
550
2N4250
250
350
800
hfe
2N4248.2N4249
2N4250
2.0
2.5
Cobo
2N4248.2N4249.
2N4250
6.0
Cibo
2N4248.2N4249.
2N4250
16
hfe
Unit
9-91
=
= -5.0 Volts
=0
IC
= 1.0 mAo VCE = -5.0 Volts
IC
= 0.5 mAo VCE = -5.0 Volts
pF
IE
= O. VCB = -5.0 Volts
pF
IC
= O. VBE = 0.5 Volt
2N4248,2N4249,2N4250
.SMALL SIGNAL CHARACTERISTICS (f = 1 kHz)
Symbol
Min
Typ
Max
Unit
Conditions
hie
2N4249
2N4250
2.5
6.0
8.0
10
17
20
kohms
kohms
Ie = 1.0 mAo VeE = 5.0 Volts
hoe
2N4249
2N4250
5.0
5.0
19
25
40
50
/Lmho
/Lmho
Ie = 1.0 mAo VeE = -5.0 Volts
h re
2N4249.2N4250
10
xl0- 4
Ie = 1.0 mAo VeE = -5.0 Volts
hfe
2N4249
2N4250
100
250
250
350
550
800
Ie = 1.0 mAo VeE = -5.0 Volts
NOTES:
(1)
These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
(2)
These are steady state limits. The factory should be consulted on applications involving pulsed or low-duty cycle operations.
(3)
These ratings give a maximum junction temperature of 125°C and junction-ta-case thermal resistance of 20QoC/watt (derating
factor of 5.0 mW/oC); junction-to·ambientthermal resistance of 500°C/watt (derating factor of 2.0 mW/oC).
(4)
This rating refers to a high-current point where collector to emitter voltage is lowest.
(5)
Pulse Conditions: length = 300 /Ls; duty cycle = 1 %.
(6)
RS = 10 kQ. Power Bandwidth of 150 Hz.
(7)
RS = 10 kQ . Power Bandwidth of 15.7 kHz with 3.0 dB points at 10Hz and 10kHz.
(8)
RS = 1.0 kQ. Power Bandwidth of 150 Hz.
9-92
2N4400, 2N4401
GENERAL PURPOSE NPN SI LICON
SWITCHING AND AMPLIFYING TRANSISTORS
Package: To-92
SWITCHING TIME EQUIVALENT TEST CI RCUITS
ABSOLUTE MAXIMUM RATINGS
(T A = 25 0 C unless otherwise noted)
30V
~
_
Characteristic
Unit
Collector-Emitter Voltage ........................... 40 Vde
Collector-Base Voltage ................................ 60 Vde
Emitter-Base Voltage .................................. 6.0 Vde
-+16 v
o
I
I
4-1,0
~
to 100llS
DUTY CYCLE 2%
I
-2V _I I14-
.
'
_.1_
::]"ll 'F, -~"""~r--t
_14V
\+- <
-+
I
• _..1_
~1~'
I C s' 'r'AC,TANCE
JIG,
ELECTRICAL CHARACTERISTICS (T A = 25 0 C unless otherwise noted)
Symbol
Min
Max
Unit
BV CEO *
BV CBO
40
-
Vde
Ie
Conditions
60
-
Vde
IC - 0.1 mAde, IE - 0
BV EBO
6.0
-
Vde
ICEX
0.1
uAde
= 0.1 mAde, IC = 0
VCE = 35 Vde, VEllioffl = 0.4 Vde
IBL
-
0.1
uAde
VCE - 35 Vde, VEBloff) - 0.4 Vde
hFE
20
-
-
IC - 0.1 mAde, V CE - 1Vde
VCE(sat)
40
50
-
50
150
100
300
20
-
40
-
-
0.4
0.75
fT
200
IC
= 10 mAde, V CE = 1 Vde
IC
= 150 mAde, V CE = 1 Vde*
2N4400
2N4400
2N4401
IC
= 500 mAde, V CE = 2 Vde*
Vde
IC
= 150 mAde, IB = 15 mAde
Vde
IC 500 mAde, I B - 50 mAde
IC - 150 mAde, IB = 15 mAde
2N4400
2N4401
0.95
~-
-
MHz
IC
500 mAde, ~ - 50 mAde
= 20 mAde, V CE -
2N4400
-
2N4400
2N4401
1.2
250
1 Vde
2N4401
2N4401
0.75
VBE(sat)
1 mAde, VCE
IC
-
2N4401
,
*Pulse Test: Pulse Width _ 300 us, Duty Cycle _ 2%.
9-93
•
I
IE
20
40
= 1 mAde, ~ = 0
10 Vde, f - 100 MHz
2N4400,2N4401
ELECTRICAL CHARACTERISTICS (T A = 25°C)
SYMBOL
MIN.
MAX.
UNITS
6.5
CONDITIONS
Ceb
Ceb
-
30
pF
pF
hie
0.5
7~5
kohms
IC = 1 mAde, VCE = 10 Vde, f = kHz
-
V CB = 5 Vde, IE = 0, f - 100 kHz, emitter guarded
Vse = 0.5 Vde, IC = 0, f = 1O-0-kRz,
Collector guarded
2N4400
2N4401
1.0
15
h re
0.1
8.0
x 104
IC = 1 mAde, V CE = 10 Vde, f = 1 kHz
hfe
20
250
-
IC = 1 mAde, V CE - 10 Vde, f = 1 kHz 2N4400
40
500
IC = 1 mAde, V CE = 10 Vde, f = 1 kHz
V CC - 30 Vde, V ES(off) = 2Vde,
IC - 150 mAde, IS1 = 15 mAde
r
ts
tf
30
-
15
ns
-
20
ns
1.0
hoe
td
t
"...
2N4401
umhoe
~:
-
225
ns
30
ns
V CC = 30 Vde, IC - 150 mAde,
I
IS1 = IS2 -15 mAde
9-94
2N4402, 2N4403·
GENERAL PURPOSE PNP SI LICON
SWITCHING AND AMPLIFYING TRANSISTOR
Turn-On Time
ABSOlUTE.MAXIMUM RATINGS
Collector-Emitter Voltage ........................... 40 Vdc
Collector-Base Voltage ............................... 40 Vdc
zoo .n
_<2n,
Unit
Characteristic
-30V
,
0-4-+----
lUI.
.. .1_
"":c,'
... 0
"1_'OOPr, "':.,,,, 4."n
lMfl
ELECTRICAL CHARACTERISTICS at 25 0 C free-air temperature
Symbol
2N5447
Min
Max
2N5448
Min
Max
Unit
V (BR)CBO
V(BR)CEO
-40
-25
-50
-30
V
V
IC = -100 uA, ~ = 0
IC- 10mA,IB~u,Seel\lote4
V(BR)EBO
'CBO
-5
V
nA
'E--l00uA,IC=0
VCB -20V,I E -0
VEB
3 V, 'C 0
VCE --5V,I C --50mA,SeeNote4
VCE
5V,I C - 50mA,SeeNote4
'EBO
hFE
V BE
-5
100
II
60
-06
-100
300
-1
100
30
-0.6
-100
150
-1
nA
V
Test Conditions
7V~C~E~-------+-_--·--~-__===-_-_0_.2_5__~__;5------0-.-2-5-4--V____~71¥B------5~m~A~,~'~CL----~5~0~m-A~,S~e-e~N~ot~e~4~
I
[hfel
5
VCE - -5 V, 'C = -50 mA, f - 20 MHz
rC'C~b--------+--------~+----------~1~2'-~P~F~-+-'VTC~B~='1~0'VT,7'~E~~~O-,'f~=~l'M~HLz------
NOTES:
I
~N~5
These parameters must be measured using pulse teDhniques. t = 300 us, duty cycle ~ 2%.
5. CCb is measured using thfee-terminal measurement technique§lwith the emitter guarded.
4.
9-118
2N5449,2N5450,2N5451
Package: To-92
NPNSILICON AMPLIFIER TRANSISTORS
ABSOLUTE MAXIMUM RATINGS at 25 0 C free-air temperature (unless otherwise noted)
2N5449
2N5450
Characteristic
Collector-Base Voltage
2N5451
Unit
50
40
V
30
20
V
5
5
NOTES:
1. These values apply when the baseemitter diode is open-circuited.
2. Derate linearly to 150°C free-air temperature at the rate of 2.88 mW/deg.
3·. Derate linearly to IS00C lead temperature at the rate of 4 rnW/deg. Lead
temperature is measured on the collector lead 1/16 inch from the case.
Collector-Emitter Voltage
(See Note 1)
Emitter-Base Voltage
Continuous Collector Current
V
800
mA
360
mW
500
mW
Continuous Device Dissipation at
(or below) 250 C Free-Air
Temperature (See Note 2)
SILICON 15-WATT QUASI-COMPLEMENTARY
POWER AMPLIFIER
Continuous Device Dissipation at
(or below) 25 0 C Lead
Temperature (See Note 3)
-65 to 150
Storage Temperature Range
Junction Temperature-Operating
°C
°C
260
?I1A
1N128
1N128A
1N46
1N49
1N50
1N54A
78
79
80
81
82
83
84
85
86
87
1N60
1N949
88
89
1N139
1N276JAN
90
91
(matched pair 1N541)
(matched pair)
5
5
10
50
10
50
10
50@55°C
50@55°C
50@55°C
Va
30
30
5
-40
-40
-35
50kO
(solder-in 1N119)
-35
50kO
-40
2kO
10
50
50@75°C
10-4
300
300
500
500
300
1N449
1N108
1N452
1N455
G788
1N636
1N266
1N417
1N34A
92
93
94
95
96
97
98
99
100
1N66
101
1N66A
1N119
1N480
1N120
1N418
1N34
102
103
104
105
106
107
1N278
108
GOLD BOND GERMANIUM DIODES
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
IF
PIV
mA
60
60
20
40
1
1
60
60
60
60
40
50
100
100
1
0.7
1
1
60
100
1
60
60
100
100
1
1
60
200
1
60
65
200
100
1
1
65
200
1
70* *2.5
i
-I
70*j*2.5
1
70" *2.5
1
70
4
1
70
5
1
70
70
5
5
1
1
70" * * 5
1
I
70* * •• 5
Reverse Recovery Time
IR
V
1
70
70
75
75
30
200
3
5
2
1
1
1
75
5
1
75
5
1
75
75
75
75
5
5
10
10
1
1
1
1
,.A
1500
100
100
500
6
10
15
150
20
250
25
25
125
15
150
20
10
100
10
100
25
125
50
500
100
500
50
833
10
800
10
20
50
25
125
50
250
250
50
410
30
500
50
850
50
800
100
800
100
800
@V
50
50
10@75°C
50
5
10
10
50
10
50
40
10
50@55°C
10
50
45
10
50
10
50
10@55°C
50@55°C
10@55°C
50@55°C
10@55°C
50@55°C
10
50
10
50
10
10
70@50°C
10@55°C
50@55°C
10@55°C
50@55°C
40
50
50
10
50
10
50
10
50
50
50
50
50
IFmA
30
30
VR
-:-40
-35
10-5
Rec. to nsec
4000*
50kO
500
Part
No.
Line
No.
1N287
1N276
109
110
1N96A
G820
1N909
1N774
111
112
113
114
1N775
115
1N498
1N777
116
117
1N774A
118
1N3465
1N773
119
120
1N773A
121
1N113
122
1N114
123
1N115
124
1N86
125
1N294
126
1N294A
1N192
127
128
1N111
129
1N112
130
1N298
1N772A
1N45
1N69A
131
132
133
134
1N69
135
1N126
136
1N116
1N90
1N117
1N95
137
138
139
140
GOLD
BOND GERMANIUM
DIODES
_.
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
IF
In
PIV mA
V
75
75
75
75
15
20
20
25
1
1
1
1
75
25
1
75
75
75
40
100
100
1
1
1
75
75
80
100
200
3.5
1
1
1
80
3.5
1
80
80
80
3.6
4
4
1
1
1
80
80
80
80
80
80
40
100
100
100
125
200
1
1
1
1
1
1
80
200
1
80
200
.1
80
80
80
80
200
200
200
200
1
1
1
1
80
85
85
85
85
85
85
85
; 85
, 85
90
400
2.5
2.5
4
4
5
20
20
40
40
2.5
1
1
1
1
1
1
1
1
1
1
1
I 90
2.5
1
+
fJ-A
50
100
800
20
60
50
850
100
30
30
500
200
50
10
100
10
100
300
5
10
250
50
25
40
50
180
10
150
10
150
10
150
25
25
100
100
75
25
100
200
150
833
150
50
50
300
350
11
60
11
60
@V
10
50
50
10
30
10
50
50
50
10
50
50
50
5
50
Reverse Recovery Time
Rec. to nsec
IFmA
Vn
5
-40
300
5
50
75
5
10
50@75°C
50
50
60
50
90
20
20@70°C
20
I
20@70°C
20
I
20@70°C
50
50
50
50
10@75°C
50
50
50
50
50
50
50
50
50
50
10
10@60°C
I 10
10@60°C
Part
No.
Line
No.
1N314
1N118
1N96
1N447
141
142
143
144
1N126A
145
1N118A
1N499
1N281
146
147
148
1N292
1N454
1N297
149
150
151
1N297A
152
1N57
1N67
. 1N198
153
154
155
1N100A
1N771
1N500
1N772
1N419
1N3666M USN
156
157
158
159
160
161
5
30
-40
-10
300
300
30
-10
300 1N3666M1 USN
162
30
-10
300
1N3666M2 USN
163,
30
5
-10
-40
300
300
1N771A
1N3666
1N270
1N270JAN
164
165
166
167
1N771B
1N88
1N65
1N52A
1N48
1N52
1N141
1N289
1N140
1N288
1N476
168
169
170
171
172
173 ,:
174
175
176
177 I:
178
1N477
179
10-6
500fJ-A
i
1
GOLD BOND GERMANIUM DIODES
:
;
:
,ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
IF
PIV
V
3.2
5
5
1
1
1
90
90
90
5
7
25
1
1
0.5
90
90
100
100
100
50
50
3
3.5
4
3,5
0,62
1
1
1
100
4
1
100
4
1
100
4
1 '
100
4-
1
100
4
1
100
100
100
100
100
4
4
5
5
5
1
1
1
1
0.5
100
100
100
100
7.5
10
10
14
1
1
1
1
100
20
20
100
100 100
100 ' 150
110
5
115
3
1
1
1
1
1
1
"
, 90
: 90
: 90
Reverse Recovery Time
Ix
mA
I
~
115
115
3
5
1
1
115
115
5
50
1
1
120
120
5
25
1
1
@V
p.A
-100"
7
25
125
250
120
5
20
120
4
625
8
5
50
6
500
6
500
10
50
10
75
50
250
50
600
7
800
10
250
25
50
100
10
75
5
100
40 '
150
700
11
35
410
4
400
70
45
100
100
30
....
IFmA
- .. --
60
10
10
50@55°C
50@55°C
60
5
65
60
5
100
5
5
50
3
100
3
100
10
50
10
10@75°C
50
50@75°C
50
100
10
100
10
50@75°C
10
50
50
10
10@75°C
50
50
8'0
100
125
10
75@60°C
50
3
50
10
45
100
100
30
"
Rec. to nsec
VR
----
Line
No.
"-,
-35
50ko
500
5
(sC?lder-Jn 1NJ.2m "
-40
0.5mA
'300
5
-40
300
30
Part
No.
O,5mA
1N265
1N479
1N191
180
181
182 , ,
- 1N490
1N632
1,N3769
183
184
185
1N631
G819
1N68
1N89
1N67A
186
187
188
189
190
1N38A
191
1N388
192
1N355
193
1N198A
194
1N1988
195
1N63A
1N58A
1N478
1N58
1N277JAN
196
197
198
199
200
1N38
1N99
1N97
1N933
201
202
203
204
1N100
1N98
1N501
1N567
1N62
1N617
205
206
207
208
209
210
','
2
5
-6
50k
-40
0.5mA···
300
'400
-- 1-.
1N44
1N47
-----
211
212
!
,
i
!
I
;
,i
,
;
I
i
;
1N618
1N634
213
214
1N290
1N448
215' I
216
'
--~
,
i
I
I
10-t
GOLD BOND GERMANIUM DIODES
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
PIV
mA
Reverse Recovery Time
la
IF
V
@V
p.A
120
120
40
50
1
1
120
120
120
120
125
125
100
100
100
125
2.5
3
1
1
1
1
1
1
125
3
1
125
3
1
125
125
125
125
4
5
15
25
1
1
1
1
125
130
130
40
3
5
1
1
1
150
150
165
170
190
.250
3
4
50
50
5
40
1
1
1
1
1
1
100
30
100
50
75
100
180
50
25
300
25
300
25
300
50
100
3
25
300
100
625
300
700
800
500
175
150
500
100
100
30
100
100
10@75°C
100
90
50
10
50
10
50
10
50
50
100
25
10
50
100
100
100
125
150
150
150
150
150
50
NOTES:
·Modified IBM Test Circuit
• *IR
···JAN Test Circuit
····@+55°C
IFmA
5
VR
-40
Rec. to nsec
0.5mA···
300
Part
No.
Line
No.
1N291
1N450
217
218
1N502
1N;;!77
1N453
1N633
1N75
1N70
219
220
221
222
223
224
1N70A
..
225
1N127
226
1N63
1N142
1N102
1N127A
227
228
229
230
1N143
1N68A
1N61
231
232
233
1N55
1N55A
1N635
1N451
1N558
1N98A
234
235
236
237
238
239
_ITT _ _ _ __
SEMICONDUCTORS
SWITCHING DIODES
TYPICAL CHARACTERISTICS
MAXIMUM VF @ 250C
V@IF
V@IF
V mA V mA
MAXIMUM
OPO 00·7 BV
@
TYPE EQUIV. 5 uA
I
V
V@ IF
mA
V
lN4148 lN914
75(11
1.0
10
4121
025.05 20 ..,.
lN4149 lN916 75111
1.0
1U
4(2)
025 .05 20
,
lN4150 lN3600
lN4151 lN3604 75
lN4152 lN3605 40
lN4153 lN3606 75
lN4154 lN4009 35
V @ IF
V mA
V @ IF
V mA
.54/.62 1.0 .66/.74 10 .76/.86 50 .82/.92 100 .87/1.0 200
1.0
50
.49/.55 0.1 .53/.59 .25 .59/.67 1.0 .62/.70 2.0 .70/.81 10 .74/.88 20
.49/.55 0.1 .53/.59 .25 .59/.67 1.0 .62/.70 2.0 .70/.81 10 .74/.88 20
30
1.0
lN4305 lN4063 75 .505/.575 .25 .55/.65 1.0 .61/.71 2.0 .70/.85 10
lN4444
lN4446
REVERSE
CAP.
@
V @ IF T•• ~~~
O.OV
ns
"2~o~ 5:0 VR PF
V mA
.44/.55 0.1 .56/.68 1.0 .69/.82 10 .85/1.0 100
20
1.0
7511l
lN914~
1.0
lN4448 lN914B 75111 .62/.72
lN4449 lN9168 75111 .63/.73
lN4450
20
5
1.0
100
5
1.0
30
40111 .421.54 0.1 .52/.64 1.0 .64/.76 10 .80/.92 100
1.0
200
1.0
300
T•• Stored
(5) Charge
ns PC
2
2.5
.05 .05 50
2
4
212)
.05 .05 30
2
2121
2121
.05 .05 50
0.1 0.1 25
2
4
2121
0.1 0.1 50
2
.05 .05 50
2
4121 .02 .05 20
4(21 025 .05 20
4!21 .025 .05 20
4
4121
025.!i5 20
2
4121
.05 .05 30
4
2(2)
Oper.
Volt.
Cont.
Diu.
@ 250C
(12)
MW
500
500
150
1005(41
500
150
50
4
150
30
500
4
150
50
500
4
25
25
500
4
150
7
200
50
500
4
150
75
500
2
150
75
500
2.5VI6l
150
75
500
2.5VI6I
150
75
500
200
30
500
200
30
500
200
30
500
400
lN4451
40
.40/.50 0.1 .511.61 1.0 .62/.72 10 75/.875 100
.05 .05 30
6
lN4452
40
30
lN4453
30
.42/.54 0.1 .51/.62 1.0 .60/.71 10 .71/.83 100 1.0 600 .90/1.2 lA 50", .05 .05 30
.43/.55 .01 .51/.63 0.1 .60/.71 1.0 .69/.80 10 80/921B} lao
.05 .05 20
10
0/50019
30
~OO
500
20
1.0
10
75
500
IN5194 IN483B
1.0
100
.02 00 70
80
250
2(2)
2 3.0VI101 4
.
IN4454 lN3064 75
SOIIl!
0.1 0.1 50
Rect.
Fwd.
I @ 250
mA
75
75
131 0.1 0.1 50
70
lN4447 lN916A 75111
TF.
ABSOLUTE
MAXIMUM RATINGS
Ave.
Ma<. Power
IN5195 IN485B
200m'
1.0
100
02500 180
200
250
IN5196 IN486B
2~(1'1
1.0(131
100
02500 225
250
250
IN5605 lN457
701111
1.0
20
.02 00 60
70
250
IN5606 IN458
15111111
1.0
7.0
02500 125
ISO
200
lN5607 IN459
2001111
3.0
02500 175
200
200
IN5608 IN658
120111)
1.0
1.0
lao
3001161
05 02 50
120
250
IN5609 IN660
1201\11
1.0
6.0
3001171
5.0 .~~ 100 2.71141
120
250
NOTES
1. BV=100V @ IR 100p.A
2. IF= 10mA Recover to 1mA
VR=6V
RL =100 Ohms
3. TRR=4ns @ IF=
IR=10 to 200mA irr=0.1 IF
TRR=6ns @ IF=
IR=200 to 400mA irr=0.1 IF
TRR =6ns @ IF=10mA,
IR=1mA irr=0.1mA
4. IF=200mA tr<::;;O.4ns, tp=100ns
VFR=1.0V, DU<::;;1 %
5. IF=10mA
IR=10mA
Recover to 1mA
6. 50mA peak square wave,
0.1 P.s pulse width,
5 to 100 KC rep. rate,
generator tr<::;;30ns
7. IF 500mA
VR=adjust for IR=500mA
Recover to 50mA
8. Pulse width=30p.s, duty cycle=3 %,
VF measured at 25±3p.s
9. Q @ IF=1mA MIL-STD-750
method 4061
10. IF=100mA peak square wave
0.1 P.s pulse width
RL =50 Ohms tr<::;;30 ns, 5 to 100KC
11. @ 100p.A
11-1
12. Rated Max, Junction
Temp.=200"C
13. Pulse width=a.5msec,
duty cycle<::;;2 %.
14. VR=10V, f=1MHz
15. T =100°C
16. IF=5mA, VR=40V
R1 =2K, C1 =10pf
Recover to aOkn
17. IF=30mA, VR=35V
Recover to 400 kn
_
I
mm
SILICON PLANAR
-L-L _ _ _
_DIODE
_
SEMICONDUCTORS
SILICON PLANAR DIODE
This section contains silicon diodes featuring:
• Fast Switching
• High Conductance
• Low Leakage
• Voltages up to 250 Volts
How To Use This Buying Guide
Standard general purpose diodes are listed in
numerical order below. Each diode has a line
number referenced to the specification tables
on pages 2, 3 and 4. Use this buying guide two
ways: select the diode by type number, or 10cate the type number from the specification
data.
ITT is the world's leading producer of diodes.
Call your ITT sales engineer or distributor for
quotation on all your diode needs.
Part No.
Line No.
Pari No.
Line No.
1N194
1N194A
1N195
1N196
1N251
1N379
1N380
1N381
1N382
1N383
1N384
1N38'5
1N386
1N387
1N388
1N389
1N390
1N391
1N392
1N393
1N456
1N456A
1N457
45
44
46
43
20
1
2
3
6
11
14
23
40
66
77
90
103
137
152
168
31
36
80
1N457A
1N460
1N460A
1N461
1N461A
1N462
1N462A
1N464
IN482
1N482A
1N482B
1N483
1N483A
1N619
1N625
1N626
1N627
1N643
1N643A
1N658
1N658A
1N659
1N662
84
138
139
28
35
93
96
169
38
39
58
94
97
18
, 19
67
141
172
173
161
162
68
126
11-2
Part No.
Line No.
1N662A
1N663
1N663A
1N690
1N691
1N692
1N696
1N697
1N778
1N789
1N790
1N791
1N792
1N793
1N794
1N795
1N796
1N797
1N798
1N799
1N806
1N808
1N810
1N811
1N812
1N813
1N814
1N815
1N818
1N837
1N837A
1N838
1N840
1N841
1N844
1N891
1N892
1N903
1N903A
1N904
1N904A
1N905
1N905A
1N906
1N906A
1N907
145
129
146
60
130
164
54
163
155
25
24
32
34
79
78
82
85
157
156
159
153
154
69
7
17
4
47
5
128
149
150
170
70
171
151
83
160
52
55
26
29
9
12
10
13
27
Part No.
1N907A
1N908
1N908A
1N914
1N914JAN
1N914A
1N914B
1N916
1N916A
1N916B
1N920
1N921
1N922
1N925
1N926
1N927
1N928
1N929
1N930
1N931
1N934
1N993
1N3062
1N3063
1N3064
1N3065
1N3066
1N3067
1N3068
1N3069
1N3123
1N3124
1N3206
1N3298
1N3600
1N3600USN
1N3604
1N3605
1N3606
1N3607
1N3654
1N3669
1N3731
IN3872
1N4009*
1N4148*
Line No.
30
53
56
107
142
114
124
109
115
118
61
132
1'65
48
49
91
158
15
111
167
81
8
112
102
105
99
106
21
22
92
50
51
127
136
72
73
119
42
101
121
144
98
147
140
16
108
SILICON PLANAR DIODE
Part No.
Line No.
Part No.
Line No.
1N4149*
1N4150*
1N4151*
1N4152*
1N4153*
1N4154*
1N4305*
1N4380
1N4444*
110
71
120
41
100
37
117
76
95
1N4446*
1N4447*
1N4448*
1N4449*
1N4450*
1N4451 *
1N4453*
1N4454*
8298
113
116
122
123
57
59
33
104
86
Part No.
Line No.
Part No.
Line No.
65
131
75
143
125
133
87
62
134
8505
8506
8507
8508
8509
WG140*
WG141 *
WG142*
88
63
135
89
64
166
148
74
8398
8400
8401
8402
8403
8500
8501
8502
8504
* Double plug diode package
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
VitM
IF
Reverse Recovery Time t r r
High Temp IR
I"
Cap. C
Test
mA
9
11
13.5
15
15
17
20
20
20
20
20
20
20
25
25
25
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
35
36
36
37
40
35
30
24
5
100
17
1
10
10
10
12
20
20
9
20
30
2
3
4
5
5
5
7
10
10
10
10
15
20
20
40
50
0.01
0.1
1
10
100
100
100
100
30
100
100
5.5
0.1
0.25
1
2
10
20
@
VF
1
1
1
1
1.5
1
1
1.2
1
1
1
1
1
1
1
1
1
1
1.5
1
1
1
1
1
1
1
1
1
1
1
1
1
.43/.55
.51/.63
.60/.71
.69/.80
.80/.92
1
1
1
1
1.1
1
1
.49/.55
.53/.59
.59/.67
.62/.70
.70/.81
.74/.88
}J.A @ VR
"C
}J.A
VR
5
5
5
10
10
5
10
8.2
10
12
5
5
15
10
100
100
100
125
125
100
125
0.5
0.5
0.5
0.5
0.5
0.5
1
1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
1
.08
1
0.1
0.1
0.1
0.1
5
1
0.1
0.1
0.5
0.1
0.1
0.025
5
0.05
8.2
10
12
5
5
15
10
6
20
20
18
20
20
22
20
25
10
10
20
10
20
20
27
20
20
30
30
25
30
30
25
20
20
10
10
10
10
10
10
20
20
18
20
20
22
100
100
100
100
100
100
100
10
16
30
10
100
100
10
30
30
10
10
30
10
10
5
30
50
25
10
10
20
10
20
20
27
20
20
30
30
25
30
30
25
20
20
150
125
100
100
100
150
150
100
100
100
100
100
150
100
100
150
100
150
5
0.5
0.025
0.1
0.25
0.025
0.1
0.05
20
25
25
25
30
30
33
30
30
30
5
100
30
15
10
50
20
25
25
25
30
30
33
30
100
150
150
150
150
150
150
150
iF-mA
V"
Rec.to
nsec Condition
5
5
-10
-10
0.5mA
0.5mA
250
250
JAN 256
JAN 256
5
10
10
10
-10
-6
-5
-5
0.5mA
3mA
250
4
4
4
JAN 256
RL=75n
RL=100n
RL=100n
10
10
-5
-5
1mA
1mA
4
4
RL=100n
RL=100fl
10
5
-6
-10
0.5mA
2
250
RL=100n
JAN 256
30
5
10
30
-35
-10
-6
30mA·
400kn
0.5mA
1mA
1mA
1000
150
2
50
5
5
10
10
-20
-20
-5
-5
200kn
200kn
250
500
4
4
RL=100n
RL=100n
10
10
-5
-5
1mA
1mA
4
4
RL=100n
RL=100n
5
-20
200Kn
500
5
10
10
-20
-6
-6
.
11-3
100kn
pi @ VR
35
30
28
6
6
64
25
2
6
0
1
2.5
20
1
2.5
15
6
6
6
6
6
6
4
2
0
0
1
4
6
12
0
0
0
6
1
2.5
10
1
2.5
6
6
0
6
6
30
0
IBM Y Mod
RL=100n
R,.=100n
500
5
0
10
2
6
0
1mA
1mA
2
R,.=100n
2
RL=100n
Part
No.
Line
No.
1N379
1N380
1N381
1N813
1N815
1N382
1N811
1N993
1N905
1N906
1N383
1N905A
1N906A
1N384
1N929
1N4009
1N812
1N619
1N625
1N251
1N3067
1N3068
1N385
1N790
1N789
1N904
1N907
1N461
1N904A
1N907A
1N456
1N791
1N4453·
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1N792
1N461A
1N456A
1N4154"
1N482
1N482A
1N386
1N4152"
34
35
36
37
38
39
40
41
SILICON PLANAR DIODE
ELECTRICAL CHARACTERISTICS, Continued
IF
VRM
Reverse Recovery Time t r r
High Temp In
I.
Cap. C
Tesl
mA
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
43
50
50
50
50
50
50
50
50
50
50
52
60
60
60
60
60
60
60
60
60
60
60
60
62
65
65
70
70
70
70
70
70
0.1
1
1
1.5
2
2
5
5
10
10
10
10
10
20
20
0.1
1
10
100
200
100
0.1
1
10
100
300
400
400
500
500
500
500
4.5
4
6
10
150
1
10
50
100
200
200
200
250
400
570
3.5
10
10
20
30
50
50
100
100
500
500
500
500
2.7
10
50
5
100
0.1
1
10
100
100
100
400
@
VF
0.55
2
1
2
2
1
1
1
1.5
1.5
1
1
1
1
1
.42/.54
.52/.64
.64/.76
.80/.92
1
1
.40/.50
.51/.61
.62/.72
.75/.88
1
1
1
1
1
1
0.9
1
1.5
1
1
1
.54/.62
.66/.74
.76/.86
.86/.92
.87/1.0
1
1
1
1
1.4
1
1
1
1
1
1
1
1
_.-- 1
1
1
1
1
1
1
1
1
1.1
.44/.55
.56/.68
.69/.82
.85/1.0
1
1
1.1
p.A @ V.
/LA
Vn
'c
IFmA
10
30
30
30
30
5
5
5
10
10
10
10
10
10
10
10
0.05
10
10
10
10
0.1
1
0.1
0.1
0.1
0.1
0.1
0.015
0.1
0.1
0.05
30
40
40
40
40
20
10
10
40
40
40
40
20
40
40
30
50
300
300
300
300
10
20
10
10
10
10
10
20
10
10
50
30
50
40
40
40
20
10
10
40
40
40
40
20
40
40
30
150
150
150
150
150
150
100
100
100
100
100
100
150
100
100
150
0.025
0.05
30
30
5
50
30
30
150
150
0.25
0.25
0.05
0.05
0.05
0.2
0.1
1
5
1
0.1
0.1
30
30
25
25
25
25
39
35
50
40
40
50
50
50
30
30
150
150
10
30
25
39
35
50
100
100
100
15
100
40
50
100
150
0.1
0.1
0.1
0.1
50
0.1
5
1
0.025
0.025
5
0.1
0.025
5
0.2
0.1
0.1
0.1
1
0.1
0.1
0.5
0.25
0.05
50
50
30
30
50
47
50
50
60
60
50
50
60
50
30
30
30
30
56
10
50
60
60
50
100
100
50
10
100
30
30
50
50
10
50
60
60
50
100
100
100
150
150
150
0.5
0.025
0.25
60
60
70
30
15
60
60
150
150
10
30
30
5
6
3
25
5
30
50
50
47
50
50
60
60
50
50
60
50
150
150
100
100
100
150
150
100
100
150
100
V.
-6
-35
-35
-35
-35
-10
-10
-10
-5
-5
-5
-5
-5
-5
-6
Rec.to
"sec Condition
1mA
2 R.. =100a
100
200
200
300
250 JAN 256
150 JAN 256
150 JAN 256
4 RL=100n
4 RL=100a
4 R•. =100n
4 R•. =100n
5
4 RL=100n
4 RL=100a
4 R,,=100n
0.5mA
20kn
20kn
1mA
1mA
10mA
1mA
1mA
1mA
500
500
500
500
500
500
-30
-30
-30
-30
-30
-30
10kl!
10kn
10ko
10ka
10kn
10ka
30
30
10
30
20 to
200
200 to
400
10
10
10
10
400
570
-35
-35
400kO
400kf!
-35
20 to
200"
200 to
400"
1""
400kn
800
300
15
30
50
200
RL=1ka
RL=1kn
RL=100n
RL=1000
RL=100n
RL=1kO
1000 IBM Y Mod
300 JAN 256
50
300 JAN 256
4 irr=O.1 IF
6
Part
pI @ Vn
2
0
0.8
2
1
2.5
4
1
2.5
4
-6
-30
-15
0.1mA
1.1mA
1mA
10kf!
1mA
5
5
-40
-20
200kn
200kn
250
500
30
5
-35
-40
400kO
200kO
80kn
1000
500
300
6
6
6
6
0
6
6
0
1N3605
1N196
1N194A
1N194
1N195
1N814
1N925
1N926
1N3123
1N3124
1N903
.1N908
1N696
1N903A
1N908A
1N4450"
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
6
0
1N482B
1N4451"
58
59
9
7
7
7
7
8
7.5
9
9
9
9
6
1N690
1N920
8502
8506
8509
8398
1N387
1N626
10 1N659
·1N810
1N840
0 1N4150"
60
61
62
63
64
65
66
67
68
69
70
71
0 1N3600
0 1N3600U8N
0 WG142"
9 8401
15 1N4380
6 1N388
1N794
1N793
0 1N457
1N934
1N795
1N891
1N457A
1N796
9 8298
9 8501
9 8505
9 8508
6 1N389
1N927
0 1N3069
0 1N462
1N483
0 1N4444"
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
1N462A
1N483A
1N3669
96
97
98
2.7
2.5
irr=0.1 mA
JAN 256
100kO
10ko
10ko
10kn
10kn
500
200
15
30
50
RL=1kn
RL=100n
RL=100n
RL=100n
RL=1000
RL=100n
RL=100n
RL=100n
2.5
2.5
4
7
3
6
8
-40
-50
-30
-30
-30
7
7
7
7
5.6
5
30
-10
30mA"
20kn
1mA
150
50
Jan 256
RL=100n
10
-6
1mA
2
RL=100n
2
300
-10
1 rnA
200
RL=100n
10
11-4
Line
No.
irr=O.1 IF
6
6
4
6
15
1.8
5
500
500
500
500
No.
6
8
10
SILICON PLANAR DIODE
ELECTRICAL CHARACTERISTICS, Continued
V.,
IF
mA
75
75
0.1
0.1
0.25
1
1
10
20
0.1
0.25
2
10
10
10
10
10
10
10
75
75
75
75
75
75
75
75
75
75
75
2U
75
20
20
75
75
20
20
75
20
75
75 0.25
1
2
10
75
30
75
50
50
75
75
50
75
5
100
75
5
30
75 100
75 200
80
10
80
10
80
30
SO 100
SO 400
SO 400
SO 500
SO 500
SO 500
SO 500
SO 500
90
1.5
90
5
90
.15
90 150
4
100
100
10
25
100
100
50
100 100
100 100
100 100
100 100
100 150
100 150
100 200
110
1.2
110
4
110 100
112
120
120
120
120
10
10
10
10
50
@
High Temp I.
I.
VF
0.53
.49/.55
.53/.59
.59/.67
.62/.70
.70/.71
.74/.88
0.55
0.58
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.50/.58
.55/.65
.61/.71
.70/.81
1
1
1
1
.62/.72
1.0
.63/.73
1.0
1
1
1
1
1.5
1
1
1
1
1
1
1
0.9
1
1
1
1
1.5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
p.A @ V.
p.A
V.
'c
Cap. C
Reverse Recovery Time I r r
IFmA
V.
Rec.lo
nsec
Test
Condition
PanpI @ V,
0.1
0.05
50
30
100
50
50
30
150
150
10
10
-6
-6
lmA
lmA
2
2
RL-l00n
R,.=10O!J
1.5
2
0
0
0.05
0.1
1
50
50
68
50
100
50
50
50
68
150
150
100
10
10
-6
-1
lmA
lmA
2
4
R,.=100n
R,.=100n
0.1
0.1
0.025
0.Q25
0.025
0.025
U.l
0.1
0.025
0.025
0.Q25
0.Q25
50
50
20
20
20
20
50
50
20
20
20
20
100
100
50
50
50
50
50
50
20
20
20
20
150
150
150
150
150
150
10
10
10
10
-6
-1
-6
-6
lmA
lmA
lmA
lmA
2
4
2
4
RL=100n
RL=100n
RL=100n
RL=100n
10
-6
lmA
4
RL=100n
2
2
5.2
2
2
1
4
4
2
2
0
0
6
0
0
0
0
0
0
0
100
50
50
50
50
50
20
20
20
20
150
150
150
150
10
10
10
10
10
10
-6
-6
-8
-6
-6
-6
lmA
lmA
lmA
lmA
lmA
lmA
2
4
4
4
4
2
RL=100n
RL=100n
RL=100n
R,.=100n
RL=100n
RL=100n
0_025
0.05
0.05
0.05
0.025
20
50
50
50
20
50
50
50
50
50
20
50
50
50
20
150
150
150
150
150
10
10
10
10
10
-6
-6
-6
-6
-6
lmA
lmA
lmA
lmA
lmA
0.025
20
50
20
150
10
-6
lmA
0.Q25
0.1
1
0.025
0.25
5
0.25
0.1
0.25
0.1
0.1
0.1
0_2
1
0.01
0.01
0.1
1
5
10
0_025
1
0.1
0.050
0.050
0_1
0.1
0.1
1
0.5
1
20
50
10
20
60
75
60
50
60
50
50
50
60
S2
10
10
75
75
75
SO
75
10
75
50
50
75
SO
SO
100
100
100
50
100
100
50
20
50
50
20
50
50
20
60
75
60
150
150
100
150
100
100
150
lmA
O.lmA
lOOk!]
lmA
50
60
150
10
200
5
10
20
5
500
400
500
500
500
500
500
0.5
5
1
0.1
5
100
100
100
10
100
45
50
0.2
0.2
60
82
10
10
150
100
100
100
30
50
0.5
25
100
15
50
75
20
20
75
50
75
50
100
150
71
150
100
100
150
15
15
15
50
50
50
75
SO
SO
100
100
100
100
100
100
100
125
125
30
30
30
10
30
100
100
100
10
100
125
100
100
100
100
-6
200mA"
-40
-6
-40
-40
-50
-30
-50
--30
-30
-30
-30
200kn
10kn
10kn
10kn
10kn
10kn
10kn
50mA
200
30
10
30
5
5
5
10
10
30
30
30
-20
-35
5mA
400kn
-35
-6.5
-40
-40
-6
-6
-35
-35
-35
400kn
lmA
100kn
200kn
lmA
lmA
400kn
400kn
400kn
5
30
-40
-35
5
5
5
5
5
-40
-40
-40
-10
-40
11-5
Line
No.
1N3065
lN4153'
99
100
1
4
4
2
2
2
lN3606
lN3063
lN390
lN4454'
lN3064
lN3066
lN914
lN4148'
lN916
lN4149'
lN930
0 lN3062
0 lN446'
0 lN914A
0 lN916A
0 lN447'
0 lN4305'
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
4 RL=100n
2 RL=1000
2 RL=1000
2 RL=1000
4 RL=100n
2
2
2
2
4
0
0
0
0
0
lN916B
lN3604
lN4151'
lN3607
lN4448'
118
119
120
121
122
4
RL=100n
2
0
lN4449'
4
6
500
4
500
500
SOO
15
300
15
30
50
50
RL=100n
RL=1000
4
2.5
3
4
RL=100n
JAN 256
RL=lkO
RL=10O!J
RL=lkO
RL=1000
RL=100n
RL=1000
R,.=50n
50
1000
5
100
4
300
300
3
3
500
300
500
RL=100n
IBMYMod
RL=100n
R,.=2kn
300
300
JAN 256
JAN 256
RL=500n
JAN 256
JAN 256
JAN 256
RL =100n
R,.=100n
JAN 256
JAN 256
JAN 256
7
7
7
7
4.S
3
4
5
2.S
2
2
4.5
400kn
200kO
200kf!
20kn
200kO
No.
300
250
500
150
500
0 lN914B
0 5403
10 lN662
0 lN3206
lNS1S
lN663
lN691
9 5400
lN921
9 5500
9 5504
9 5507
lN329S
6 lN391
10 lN460
10 lN460A
0 lN3872
lN627
1.5 lN914JAN
5402
lN3654
lN662A
lN663A
0 lN3731
0 WG141'
1 NS37
lN837A
lNS44
6 lN392
lNS06
lNSOS
lN77S
lN79S
lN797
lN92S
lN799
123
124
125
126
127
12S
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
14S
149
150
151
152
153
154
155
156
157
15S
159
SILICON PLANAR DIODE
ELECTRICAL CHARACTERISTICS, Continued
I.
VRl'ot
mA
120
120
120
120
120
120
125
125
135
150
150
150
175
175
50
100
100
250
400
500
150
20
0.9
3
150
150
10
40
@
V.
p.A @
1
0.1
1 0.05
1 0.025
1
1
1 0.25
1 0.25
1
1
0.1
1
1
1
0.5
1
0.1
1
0.1
1 0.025
1
1.0
Reverse Recovery Time t r r
High Temp I.
I.
v.
p.A
v.
'C
100
50
50
50
90
90
25
25
10
100
50
50
100
150
150
50
100
90
90
150
150
100
120
125
125
120
10
100
50
30.
15
15
15
15
120
120
125
120
100
100
100
150
100
100
100
100
Cap. C
Teal
Condition
v.
Ree.lo
5
5
100
500
500
10
-40
-'40
-10
-50
-50
-6
80kn
80kO
80kO
10m
10kll
10kll
1mA
300 JAN 256
300
300 JAN 256
5
800 RL=1kll
300 RL=1kO
4 RL=100n
30
30
5
-35
-35
-40
400kll
400kll
200kO
,500 JAN 256
300 JAN 256
300
l.mA
nsec
pi @ V.
25
4.2
3
NOTES:
• Double plug diode package
HIRmA
I
11-6
Part
No.
1N892
1N658
1N658A
0 1N697
1N692
1N922
WG140'
1N931
6 1N393
1N464
1N838
1N841
1N643
-10 1N643A
Line
No.
160
161
162
163
164
165
166
167
168
169
170
171
172
173
I
mm
1N4148
_-IL-IL ______________S_IL_IC_O_N__P_LA_N_A_R__D_IO_D_E
SEMICONDUCTORS
SILICON EPITAXIAL PLANAR DIODE
• 00-35 Construction
o Hermetically Sealed
• Passivated Surfaces
•. Inherently Reliable
ABSOLUTE MAXIMUM RATINGS
Characteristics
@
25° C:
Units
Storage Temperature
65 to 2 0 0 ° C
Range ........... Lead Temperature 1/16 + If
1/32" from case for
10 sec .................... 300
°c
Continuous Reverse Operating
Voltage .................... 75
Volts
Power Dissipation ............ 500
mW
MW 1° C
Derating Factor .............. 2.85
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
Characteristic
Min.
Typ.
Max.
Conditions
U.nit
Peak Inverse
Voltage
75
V
5p.8.
Peak Inverse
Voltage
100
V
100p.a.
10mA
Forward Voltage
1.0
V
Reverse Current
25
na
20V
150
50
p'a
20V
*
4
4
flsec
Reverse Current
Capacitance
Reverse Recovery
Time
*If=10mA
Vr=6V
pf
R,=100 ohms
11-7
OV
1mA
recover to 1. mA
ITT
-----
JAN 1N4148
SILICON SWITCHING DIODE
SEMICONDUCTORS
SILICON EPITAXIAL PLANAR
SWITCHING DIODE
• 00·35 Construction
• Hermetically Sealed
• Passivated Surfaces
• Inherently Reliable
ABSOLUTE MAXIMUM RATINGS
Characteristics @ 25°C
Units
Peak Inverse Voltage .............. 100Volts
Power Dissipation ................. 250 mV
Storage Temperature ...... -65 to +200°C
Avg. Rectified Fwd. Current .......... 75 mA
Surge Current, 1 second ............ 500mA
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
Max.
Unit
Vdc
Conditions
IR=100fJ.A
IR
25
5.0
50
100
VR-20V
VR=75V
VR=20V, T=150°C
VR=75V, T=150°C
VF
1.0
nA
fJ.A
fJ.A
fJ.A
Vdc
Symbol
PIV
Min.
100
Typ.
IF =10mA
VR-OV
VR=1.5V
C
4.0
2.8
pF
pF
Trr
5.0
nsec
IF -IR-10mA, C-3pF,
RL = 100n, Rec. to 1.0mA
Tcr
5.0
Vdc
50mA/20 nsec, Rep. Rate
Less than 100 KC
11-8
1N4149
SILICON SWITCHING DIODE
SILICON EPITAX~AL PLANAR
SWITCHING D~ODE
ABSOLUTE MAXIMUM RATINGS
Characteristics @ 2SoC
Units
Peak Inverse Voltage ............. 100Volts
Power Dissipation ................. 2SOmW
Storage Temperature ...... -6S to +200°C
Avg. Rec!. Fwd. Current ............. 7SmA
Surge Current, 1 sec. . ............. SOOmA
ELECTRICAL CHARACTERISTICS
Symbol
PIV
IR
Min.
@ 2SoC unless otherwise noted.
Typ.
Max.
100
S.O
.02S
SO
Unit
Conditions
Vdc
IR=100jJ.A
jJ.A
p.A
p.A
VF
1.0
Vdc
Tn
4.0
nsec
C
2.0
pF
T'r
2.S
Vdc
11-9
VR=7SV
VR=20V
VR=20V, T=1S0°C
IF =10mA
IF =10mA, VR=6V
VR=QV
SOmA Peak Square Wave,
0.1jJ.sec Pulse Width, SKC
Rep. Rate, Max. Vol!. Drop:
ITT600
-
ITT- - - - SILICON SWITCHING DIODE
SEMICONDUCTORS
SILICON EPITAXIAL PLANAR
SWITCHING DIODE
ABSOLUTE MAXIMUM RATINGS
Units
Characteristics @ 25°C
Peak Inverse Voltage .............. 75Volts
Avg. Rect. Current ................. 200mA
Recurrent Peak Fwd. Current ........ 900mA
Surge Current, 1 sec ................ 1Amp
Power Dissipation ................. 500mW
Operating Temperature .... -65 to + 150°C
Storage Temperature ....... -65 to +175°C
ELECTRICAL CHARACTERISTICS
Symbol
VF
@ 25°G unless otherwise noted.
Min.
.87
.82
.76
.66
.54
IR
PIV
Typ.
Max.
Unit
Conditions
1.0
.92
.86
.74
.62
Vdc
Vdc
Vdc
Vdc
Vdc
IF=200mA
IF=100mA
IF=50mA
IF =10mA
IF=1mA
100
100
nA
j1.A
Vdc
75
C
2.5
pF
Trr
4.0
nsec
6.0
nsec
11-10
VR=50V
VR =50V, T=150°C'
IR=5j1.A
VR=OV
1,,=IR=10 to 200mA
Rec. to 0.1 of IF
IF=I R=200 to 400mA
Rec. to 0.1 of IF
-
ITT601
SILICON SWITCHING DIODE
ITT- - - - SEMICONDUCTORS
SILICON EPITAXIAL PLANAR
SWITCHING DIODE
ABSOLUTE MAXIMUM RATINGS
Units
Characteristics @ 25°C
Peak Inverse Voltage .............. 75Volts
Avg. Rect. Current ................. 200mA
Recurrent Peak Fwd. Current ........ 900mA
Surge Current, 1 sec. . ............. ; 1Amp
Power Dissipation ................. 500mW
Operating Temperature., .. -65 to +150°C
Storage Temperature ....... -65 to +175°C
ELECTRICAL CHARACTERISTICS @ 25°C unless otherwise noted.
Symbol
Min.
VF
.80
.75
.62
IR
PIV
Typ.
Max.
Unit
Conditions
1.2
1.0
.90
.85
.70
Vdc
Vdc
Vdc
Vdc
Vdc
IF =500mA
IF =400mA
IF =200mA
IF =100mA
IF =10mA
100
100
nA
p.A
Vdc
50
C
3.0
pF
Trr
6.0
nsec
11-11
VR=30V
VR=30V, T=150°C
IR=5fLA
VR=OV
IF =IR-10mA, RL=100n
Rec. to 1.0mA
ITT
----ITT2001, ITT2002, ITT2003
SILICON SWITCHING DIODE
SEMICONDUCTORS
SILICON EPITAXIAL PLANAR
SWITCHING DIODE
For General Purpose High-Voltage Applications
MAXIMUM' RATINGS @ 25°C (NOTE 1)
ITT2002
ITT2003
200Volts
150ma
250ma
4()Qma
250Volts
150ma
250ma
400ma
1.0A
300mw
3.3mw;oC
-65°C to +175°C
1.0A
300mw
3.3mw;oC
-65°C to +175°C
-65°C to +200°C
-65°C to +200°C
ITT2001
Peak Inverse Voltage ............. 100Volts
Average Rectified Current ............ 150ma
Forward Current Steady State D.C. .., 250ma
Recurrent Peak Forward Current ..... 400ma
Peak Forward Surge Current Pulse
Width of 1.0 Second ............... 1.0A
Power Dissipation ................. 300niw
Power Derating ................. 3.3mw;oC
Operating Temperature .. , -65°C to +175°C
Storage Temperature,
Ambient .............. -65°C to +200°C
ELECTRICAL CHARACTERISTICS, ITT2001 (25°C unless otherwise noted)
Parameter
Min
Max
Units
Test Conditions
VF
Forward Voltage
1.0
Volts
IR1
Reverse Current
0.1
ua
VR=50V
100
ua
VR=50V
IR.
Reverse Current (150°C)
BV
Breakdown Voltage
Os
Store Charge (Note 2)
Co
Capacitance
100
Volts
IF=100ma
IR=100ua
500
pc
IF=10ma
5.0
pf
VR=OV, f=1MHz
NOTES:
1. The maximum ratings are limiting values
above which life or satisfactory performance
may be impaired.
2. This test is equivalent to Trr @ IF = IR =
30 rna, RL - 100 ohms, recovered to 3 rna to
be .Iess t,han 50 nsec.
11-12
ITT2001, ITT2002, ITT2003
SILICON SWITCHING DIODE
ELECTRICAL CHARACTERISTICS, ITT2002 (25°C unless otherwise noted)
Parameter
Min
Max
Units
Test Conditions
VF
Forward Voltage
1.0
Volts
IR.
Reverse Current
0.1
ua
VR=150V
ua
VR=150V
IF=100ma
IR,
Reverse Current (150°C)
BV
Breakdown Voltage
as
Storage Charge (Note 2)
500
pc
IF=10ma
Co
Capacitance
5.0
pf
VR=OV, f=1MHz
100
Volts
200
IR=100ua
ELECTRICAL CHARACTERISTICS, ITT2003 (25°C unless otherwise noted)
Parameter
Min
Max
Units
Test Conditions
VF
Forward Voltage
1.0
Volts
IR.
Reverse Current
0.1
ua
VR=150V
ua
VR=150V
IF=100ma
IR,
Reverse Current (150°C)
BV
Breakdown Voltage
as
Store Charge (Note 2)
500
pc
IF=10ma
Co
Capacitance
5.0
pf
VR=OV, f=1MHz
100
Volts
250
11-13
IR=100ua
_
I
ITT3001, ITT3002, ITT3003
HIGH VOLTAGE HIGH
TEMPERATURE DOUBLE PLUG DIODE
mm _ _ _ __
-L-L
SEMICONDUCTORS
HIGH VOLTAGE HIGH TEMPERATURE
DOUBLE PLUG DIODE
MAXIMUM RATINGS (25°C) Note 1
3001
3002
3003
Peak Inverse Voltage ............... 70Volts
150Volts
200Volts
Average Rectified Current ........... 100ma
100ma
100ma
Forward Current Steady State D.C. .... 200ma
200ma
200ma
Recurrent Peak Forward Current...... 300ma
300ma
300ma
Peak Forward Surge Current Pulse
Width of 1.0 Second ............... 1.0A
1.0A
1.0A
Power Dissipation .................. 250mw
250mw
250mw
Power Derating ................. 2.0mw/"C
2.0mw/"C
2.0mw/"C
-65°C to +175°C
-65°C to +175°C
--65°C to +175°C
Storage Temperature,
Ambient .............. -65°C to +200°C
-65°C to +200°C
-65°C to +200°C
Operating Temperature '"
ELECTRICAL CHARACTERISTICS ITT3001 (25° C unless otherwise noted)
Max
. Units
Forward Voltage
1.0
Volts
0.025
ua
5
ua
Parameter
VF
IR,
Reverse Current
IR.
Reverse Current (150°C)
BV
Breakdown Voltage
Co
Capacitance
Min
Volts
70
8
NOTES:
1. The maximum ratings are limited values
above which life or satisfactory performance
may be impaired.
2. All Diodes must have black body coat.
11-14
pf
Test Conditions
IF=100ma
VR=60V
VR=60V
IR=100ua
VR=OV, f=1MHz
ITT3001, ITT3002, ITT3003
HIGH VOLTAGE HIGH
TEMPERATURE DOUBLE PLUG DIODE
~LECTRICAL
CHARACTERISTICS ITT3002 (25°C unless otherwise noted)
. Parameter'
..
Min
Max
Units
Test Conditions
VF
Forward Voltage
1.0
Volts
IR,
Reverse Current
1.0
na
VR=125V
ua
VR=125V
IR,
Reverse Current (150°C)
BV
Breakdown Voltage
Co
Capacitance
3.0
150
Volts
6.0
pf
IF=200ma
IR=100ua
VR=OV, f=1MHz
..
ELECTRICAL CHARACTERISTICS ITT3003 (25°C unless otherwise noted)
,
Parameter
Min
Max
Units
Test Conditions
VF
Forward Voltage
1.0
Volts
IF=100ma
IR,
Reverse Current
.025
ua
VR=175V
IR,
Reverse Current (150°C)
5
ua
VR=175V
BV
Breakdown Voltage
Volts
IR=100ua
200
11-15
_
1N5194, 1 N5195, 1 N5196
GENERAL PURPOSE
HIGH-TEMPERATURE DIODE
m _ _ _ __
1 T.L
SEMICONDUCTORS
GENERAL PURPOSE
SILICON DIODE
This device is a Silicon Double Plug Diode for
general-purpose, high-temperature application
in computer, industrial and military applications.
ABSOLUTE MAXIMUM RATINGS
Cross-Reference to Electrical Equivalents
Storage temperature range,
T stg • • • • • • • • • • • • • • • • • • • • • • 55°C to +200°C
Lead or terminal temperature at a
distance not less than 1/16" from the
seated surface (or case) for 2
seconds ......................... +275°C
1N5194
00-7 Types
OPO Types
1N483B
1N485B
1N486B
1N5194
1N5195
1N5196
1N5195
1N5196
200V
250V
Reverse voltage, 25°C free air ......... 80V
Maximum steady state power dissipation
at 25°C, free air ................... 250mw
250mw
250mw
Derating factor ................. 1.43mw/"C
1.43mw/"C
1.43mw/"C
ELECTRICAL CHARACTERISTICS
1N5194
Min
Forward Voltage, Vf @ 1f=100ma ...
1N5195
Max
Min
Max
200V
Max
1.0V· •
1.0V
1.0V
Breakdown Voltage, Bvr Ir=100ua .. 80V
1N5196
Min
250V
....
25na
25na'
25na'
.......................
5ua
5ua'
5ua'
Reverse Current, Ir @ Vr=70V
Reverse Current, Ir @ Vr=70V
@ 150°C
•• Pulsed-width 8.5 msec max duty cycle 2 %
or less
11-16
'Vr=180V
'Vr=225V
ITT
.
SEMICONDUCTORS
1 N5605, 1 N5606, 1 N5607, 1 N5608, 1 N5609
GENERAL PURPOSE SILICON DIODES
-~---
S~l~CON
GENERAL PURPOSE
DIODES
Cross-Reference to Electrical Equivalents
This device is a Silicon Double Plug Diode for
general purpose use in computer, industrial
and military applications.
ABSOLUTE MAXIMUM RATINGS
Storage temperature range,
Tstg .................... -65°C to +200°C
Lead or terminal temperature
at a distance not less than
1/16" from the seated surface
(or case) for 15 seconds .......... +275°C
00-7 Types
OPO Types
1N457
1N458
1N459
1N658
1N660
1N5605
1N5606
1N5607
1N5608
1N5609
1N5606
1N5607
1N560B/9
70V
150V
200V
120V
Maximum steady state power
dissipation at 25°C, free air ......... 250mw
200mw
200mw
1N5605
Reverse voltage, 25°C free air
Derating factor
.........
....................
250mw
2mw;oC
ELECTRICAL CHARACTERISTICS
Forward Voltage, Vf @ If=20ma
1N5605
Min Max
IN5606*
Min Max
IN5607*
Min Max
1.0V
1.0V
1.0V
...
Breakdown Voltage, Bvr Ir=100ua .. 70V
150V
Reverse Current, Ir @ Vr=60V ....
25na
Reverse Current, Ir @ Vr=60V
@ 150°C .......................
5ua
200V
25na
5ua
*If=7 ma, Vr=125V
.ELECTRICAL CHARACTERISTICS-1 N560B
Min
Max
1.0V
Forward Voltage, Vf@lf=100ma..
Breakdown Voltage, Bvr
Ir-100ua ....................120V
Reverse Current, Ir@50V .......
50na
Reverse Current, Ir @ 50V
@ 150°C .......... ,........
25ua
*Reverse Recovery Time, Trr
If=5 ma, Vr=40V
R1 =2K, C1 =10pf
Recover to 80K ohms ....... .
30 nsec
25na
5ua
*If=3 mao Vr=175V
ELECTRICAL CHARACTERISTICS-1N5609
Min
Max
1.0V
Forward Voltage, Vf@lf-6ma....
Breakdown Voltage, Bvr
Ir=100ua ................... 120V
Reverse Current, Ir @ 100V .....
5ua
Reverse Current, Ir @ 100V
@ 100°C ..................
50ua
Capacitance, C
Vr=10V, f=1 mc ............
2.7pf
Reverse Recovery time, Trr
If=30ma, Vr=35V,
Recover to 400K ohms ...... .
300nsec
11-17
ITT - - - - ......
SELENIUM CONTACT PROTECTORS
SEMICONDUCTORS
SELENIUM CONTACT
PROTECTOR RECTIFIERS
II) AC or DC Applications
• Low Cost
II Easy to Install
DIMENSIONS
N02010~21
TINNED COPPER WIRE
• Small Size
o Rugged Construction
These ITT selenium cells have been specifically processed for contact
protector applications. Their long life, low leakage current and reliable
operation provide a low-cost solution to arcing problems in switched
inductive devi:;es.
These circui~ protectors prevent arcing by effectively suppressing the
voltage surges which normally occur during switching. This eliminates
the undesirable by-products of arcing, such as contact pitting and erosion,
undesirable electrical noise, false triggering of adjacent control circuits
or possible insulation breakdown.
ITT selenium cells may be used in a back-to-back arrangement on
devic~s breaking either AC or DC circuits. In AC applicattons, each arm
normally contains the same number of cells; for DC use, a different number of cells is generally specified for each arm.
PACKAGE STYLE 2
PACKAGE STYLE 3
TYPICAL APPLICATIONS
•
•
•
Magnetic Chucks
Relays
Electric Clutches
e Stepping Switches 0 Telephone Switching
Thermostats
€I) Electric Brakes
Equipment
e Electromagnets
0 Automobile·Clocks & Horns 0 Solenoid Valves
0 Solenoids
Ii) Small Motors
0 Computers
0 Telemetering Equipment
Ii)
1·,,'·"'00
Mti;~
..
~
~OH
ORDERING INFORMATION
102 S 2 EX 1
LNO. of cells in position "A"
"S" indicates DC suppressor
"A" indicates AC suppressor
"P" indicates paper tube
"H" indicates hermetic seal
~l<.
II
I LNo.of cells in position "8"
L FInish
No. of cells in position "A"
"S" indicates DC suppressor
"A" indicates AC suppressor
A oBLOCKING SECTION
B 0 SUPPRESSOR SECTION
FIG. A
FIG. B
-,.,
PACKAGE STYLE 4
Explanation of part number codes
BA4 P S 1
-~~;;~ -
r ~~~ :~=~ ~::::',~~ :~~ '~~t~'~~'J:s, .,,'
FIG. C
Special finishes
Package style 1 is supplied in a paper tube or in a hermetically sealed can which meets MIL
specifications far environmental exposure. Package styles 2. 3 and 4 are supplied With a com·
mercial protective ·finish. Ta order special finishes replace the "X" in the part number with
letters as follows:
"Y" for humidity and salt'spray protection
"W" for heavy duty industrial protection
"YF" for humidity, salt spray and fungus protection
12-1
SELENIUM CONTACT PROTECTORS
CHARACTERISTICS
DC APPLICATIONS -10 BREAKS/ SECOND MAX
DC
Voltage
Range
0-30
0-22
31-60
23-44
61-90
45-66
91-120
67-BB
121-150
B9-110
151-IBO
111-132
IBI-210
133-154
211-240
155-176
241-270
177-198
271·300
199-220
301-330
221-242
331-360
243-264
Coil Curren
For 300V
Max. DC Coil
Current
Max. Rise
mA
mA
In
Part No.
Package
Style
Dimensions
B
A
ITT
Part No.
Package
Style
Dimensions
A
B
500
1000
1750
4700
9000
14000
BAIPSO
15AIPSO
101S1EXO
102SIEXO
103SIEXO
104S1 EXO
I
1
2
2
2
2
25/64
1/2
11/16
I
1-1/4
1-17/32
5/B
5/B
3/B
3/B
11/32
ll/32
BAIHSO'
15AIHSO'
10lSIAXO
102SIAXO
103SIAXO
104SIAXO
1
1
4
4
4
4
1/2
9/16
11/16
I
1-1/4
1-17/32
29/32
29/32
9r16
9/16
5/B
11/16
500
1000
1750
4700
9000
14000
BA2PSO
15A2PSO
10lS2EXO
102S2EXO
103S2EXO
104S2EXO
1
1
2
2
2
2
25/64
1/2
11/16
I
1-1/4
1-17/32
5/B
5/B
1/2
1/2
1/2
1/2
BA2HSO'
15A2HSO'
10lS2AXO
102S2AXO
103S2AXO
104S2AXO
1
1
4
4
4
4
1/2
9/16
11/16
I
1-1/4
1-17/32
29/32
29/32
11/16
11/16
11/16
13/16
500
1000
1750
4700
9000
14000
BA3PSO
15A3PSO
10lS3EXO
102S3EXO
103S3EXO
104S3EXO
1
I
2
2
2
2
25/64
1/2
11/16
I
1-1/4
1-17132
5/B
5/B
9/16
5/B
SIB
5/B
BA3HSO'
15A3HSO'
10lS3AXO
102S3AXO
103S3AXO
104S3AXO
1
1
4
4
4
4
1/2
9/16
11/16
I
1-1/4
1-17/32
29/32
29132
11116
27/32
13/16
31/32
500
1000
1750
4700
9000
14000
BA4PSO
15A4PSO
101S4EXO
102S4EXO
103S4EXO
104S4EXO
I
1
2
2
2
2
25/64
112
11/16
I
1-1/4
1-17/32
3/4
314
SIB
11116
314
23132
BA4HSO'
10lS4AXO
102S4AXO
103S4AXO
104S4AXO
1
1
4
4
4
4
1/2
9/16
11/16
I
1-114
1-17/32
1-1/32
1-1/32
13116
7/B
15/16
1
BA5PSO
15A5PSO
10lS5EXO
102S5EXO
103S5EXO
104S5EXO
I
I
2
2
2
2
25164
112
11116
I
1-114
1-17/32
3/4
SIB
314
71B
1
1
BA5HSO'
15A5HSO'
10lS5AXO
102S5AXO
103S5AXO
104S5AXO
1
1
4
4
4
4
1/2
9/16
11/16
I
1-114
1-17132
1-1/32
1-1/32
1
1-1/16
13132
1-3/16
'BA6PSO
15A6PSO
101S6EXO
102S6EXO
103S6EXO
104S6EXO
1
I
2
2
2
2
25164
1/2
11/16
1
1-114
1-17/32
3/4
15/16
1
1
1
1-1/B
BA6HSO'
15A6HSO'
10lS6AXO
102S6AXO
103S6AXO
103S6AXO
1
1
4
4
4
4
1/2
9/16
11/16
1
1-1/4
1-17/32
1-1/32
1-1/32
1-1/16
l-I/B
1-1/4
1-5/16
BA7PSO
15A7PSO
10lS7EXO
102S7EXO
103S7EXO
104S7EXO
1
1
2
2
2
2
25164
1/2
11/16
1
1-1/4
1-17/32
15/16
13/16
I
1
1-1/2
l-l/B
BA7HSO'"
15A7HSO'
101S7AXO
102S7AXO
103S7AXO
104S7AXO
I
1
4
4
4
4
1/2
9/16
11/16
1
1-1/4
1-17132
1-7/32
1-7132
l-l/B
1-1/4
1-3/B
1-7/16
BABPSO
15ABPSO
10lSBEXO
102SBEXO
103SBEXO
104SBEXO
I
1
2
2
2
2
25/64
1/2
11/16
I
1-1/4
1-17/32
13/16
13116
1-I/B
1-5/32
1-1/4
1-1/4
BABHSO'
15ABHSO'
10lS8AXO
102SBAXO
103SBAXO
104SBAXO
1
I
4
4
4
4
1/2
9/16
11/16
1
1-1/4
1-17/32
1-7/32
1-7/32
1-3/16
1-5/16
1-7116
1-1/2
BA9PSO
15A9PSO
101S9EXO
102S9EXO
103S9EXO
104S9EXO
I
1
2
2
2
2
25164
112
11/16
I
1·1/4
1-17132.
15/16
15/16
I-liB
1-114
1-3/B
1-3/B
BA9HSO'
15A9HSO'
10lS9AXO
102S9AXO
103S9AXO
103S9AXO
I
1
4
4
4
4
1/2
9/16
11/16
I
1-1/4
1-17/32
1-7/32
1-7132
1-114
1-15/32
1-9/16
1-3/B
BAIOPSO
15AIOPSO
10lSIOEXO
102SIOEXO
103SIOEXO
104S10EXO
I
1
2
2
2
2
25/64
112
11/16
I
1-114
1-17/32
15/16
15116
1-1/4
1-31B
1-1/2
1-1/2
BAIOHSO'
lSA1OHSQ*
10lSIOAXO
102SIOAXO
103S10AXO
104S10AXO
1
I
·4
4
4
4
1/2
9116
11/16
I
1-114
1-17/32
1-7/32
1-7132
1-5116
1-1/2
I-SIB
1-11/16
1
1
25/64
1/2
l-I/B
l-I/B
BAllHSO'
IOISllAXO
102S11AXO
103S11AXO
104S11AXO
1
1
3
3
3
3
112
9/16
11116
1
1-114
1-17/32
1-13/32
1-13/32
I-SIB
1-13/16
2
2-1/16
BAI2HSO'"
16AI2HSO'
10lS12AXO
102S12AXO
103S12AXO
104S12AXO
1
1
3
3
4
3
112
9116
11/16
1
1-1/4
1-17/32
1-13/32
1-13/32
1-9/16
1-13/16
2
2-1/16
500
1000
1750
4700
9000
14000
500
1000
1750
4700
9000
14000
500
1000
1750
4700
9000
14000
500
1000
1750
4700
9000
14000
'"z
;::
~
~
i
x
0
0
'"~
x
<
:E
'"
e
~
~
"!:;'"
0
>
~
::'"
<
E
151·180
250
600
111·132 850
2250
4300
6600
ITT
Dimensions
A
8
Part
No.
Pack·
age Dimensions
Style A
B
DC
Volt·
age
Range
Coil
Max. Current
DC Coil For 300V
CUrrent Max. Rise
rnA
rnA
ITT
Pari
No.
'"
Pack·
age Dimensions
Style A
B
ITT
Pack-
Part
age
Style
Dimensions
No.
A
8
z 8A7PSI
250
xi= 15A7PSI
600
g~~~
133·154 850 to?UlCl)t- IOlS7EXI
2250 CJr:a::cz 102S7EXI
~~
103S7EXI
4300 o~'-wa::
104S7EXI
6600
I
I
2
2
2
2
25!64 IS 16
15'16
1.2
11.16 1·1'8
I
31. 32
1-14 1·1 '4
1·17 321·1:4
8A7HSI*
15A7HSI*
10lS7AXI
102S7AXI
103S7AXI
104S7AXI
I
I
4
4
4
4
1·732
I 2
9 '16
1·732
11.16 1·3':16
1·5'16
I
1·1 4 1·7 '16
1·17 321·9 16
250
600
850
2250
4300
6600
8A8PSI
15A8PSI
IDlS8EXI
102S8EXI
103S8EXI
104S8EXI
I
I
2
2
2
2
25164 15'16
15116
1,2
11/16 1·1:8
I
1-1'4
1·1'4 1·3/8
1·17.'321·1'4
8A8HSI*
15A8HSI*
IDlS8AXI
102S8AXI
ID3S8AXI
104S8AXI
I
I
4
4
4
4
1'2
9 '16
11'16
I
250
600
850
2250
4300
6.00
120
300
500
1350
2600
4000
8A9PSI
15A9PSI
10lS9EXI
102S9EXI
103S9EXI
104S9EXI
I
I
2
2
2
2
2564 IS/I.
15·16
12
1l'16 1·14
1·3 '8
I
1·1 4 1·1 '2
1-17.321·1 2
8A9HSI*
15A9HSI*
10lS9AXI
102S9AXI
103S9AXI
104S9AXI
I
I
4
4
4
4
'1 '2
1·7·'32
9 '16
1·7 '32
11,16 1·1516
I
1·1 '2
1·1 '4 1·58
1·17/321·3'-4
250
600
850
2250
4300
6600
100
250
450
1125
4150
3300
8AIDPSI
15AIDPSI
I 2564
t tl2
1·1 8
1-18
8AIOHSI*
15AIOHSI*
10lSIOAXI
102SIOAXI
103SIOAXI
104SIOAXI
I
I
3
3
3
3
1'2
1·13'32
9.16
1·13:32
11 '16 1·518
1·13.'16
I
1·'·14 1·7 '8
1·17 '322·1 '16
250
'600
221·242 850
2250
4300
6600
50
125
210
560
1100
1650
8AllPSI
15AlIPSI
I 2564
I 1;2
1·1'8
1·1 8
8AlIHSI'
15AlIHSI*
10lSlIAXI
102S11AXI
103SIlAXI
104SlIAXI
I
I
3
3
3
3
1·13 '32
I 2
1-13 32
9 16
11'16 1·58
1·7 '8
I
1·1 '4 2
1·17.'32 2·1 '16
250
600
243·264 850
2250
4300
6600
10
25
45
110
215
330
8AI2PSI
15AI2PSI
I 25/64
I 1'2
1·1'8
1·1/16
8AI2HSA*
15AI2HSI'
10lSI2AXI
102S12AXI
103S12AXI
104S12AXI
I
I
3
3
3
3
1-13 '32
1.'2
9116
1·13 32
IU6 ,1-5/8
1·7 '8
'1
1-1'4 2·1 16
1·17322·3 '16
25,.4 5'B
5,B
I 2
11 'I. IS '32
I
15:32
1·1 '4 17:32
1·17.3217,32
BAIHSI'
15AtHSI*
10lSIAXt
102SIAXI
103SIAXI
104SIAXI
29 '32
I 112
I 911. 29,32
4 11 I. 5 B
-4 I
2532
4 1·1:4 34
4 1·17 3213 I.
181·210
25 '.4 5 'B
1:2
5B
11;1. 9 'I.
I
9 'I.
2. 1·1/4 17 '32
2 1·17:3219.32
BA2HSI*
.15A2HSI*
10lS2AXI
102S2AXI
103S2AXI
104S2AXI
I
I
4
4
4
4
29 32
1.2
9 I.
29 32
11'1. 1·3·1.
2932
I
1-1 '4 3 '4
1·17/327·B
250
600
155·176 850
2250
4300
6600
I
I
2
2
2
2
25/.4 3 4
1:2
3.4
11/1. 17'32
9/16
I
1·1 4 23 '32
1·17;3223:32
8A3HSI'
15A3HSI*
10lS3AXI
102S3AXI
103S3AXI
104S3AXI
I
I
4
4
4
4
1'2
9.'1.
11/16
I
1-14
1·17 32
1·1'32
1·1 32
I
1·1.32
25.32
I
241·270
8MPSI
15A4PSI
10lS4EXI
102S4EXI
103S4EXI
104S4EXI
I
I
2
2
2
2
25/64
34
3/4
1/2
11/16 21/32
I
I
1·1/4 I
1·17/323/4
8MHSl*
I
15A4HSI* I
10lS4AXl 4
102S4AXI 4
103S4AXI 4
104S4AXI ' 4
1:2
1·1 32
9:16
1·1 32
11,16 I
I
I
1·1·4 1·lil6
1·17 321-1 8
271·300
8A5PSI
15A5PSI
10lS5EXI
102S5EXI
103S5EXI
104S5EXI
I
I
2
2
2
2
25;64 3/4
1:2
3/4
11/16 13/16
I
7/8
1·1/4 1·1/8
1·17/321·1/8
8A5HSI*
15A5HSI*
10lS5AXI
.102S5AXI
103S5AXI
104S5AXI
I
I
4
4
4
4
1'2
1·1 '32
1·1 32
9'16
11;16 1·1.016
1·1.:8
I
1·1 '4 1·1 4
1·17/321·3 8
301·330
8A6PSI
15A6PSI
10lS6EXI
102S6EXI
103S6EXI
104S6EXI
I
I
2
2
2
2
25'64
1:2
15;16
IU6
11/16 I
I
I
1·1/4 1·1i8
1·17/321-1/8
8A6HSl*
15A6HSI*
10lS6AXI
102S6AXI
103S6AXI
104S6AXI
I
I
4
4
4
4
1/2
1·7,32
1·7.32
9'16
11.16 1·1 '8
1·1.-4
I
1·1;4 1·3 8
1-171321·7.16
331·360
ITT
Part
No.
Pack-
~~~B
211·240
1)7·198
199·220
1·7 '32
1·7 32
1·1 '4
1·7 '16
1·1/4 1-9:16
1·17132 1·5 '8
AC APPLICATIONS
Coil
Coil
Max. Current
DC
Volt· DC Coil For 300V
age Current Max. Rise
Range
rnA
rnA
0·26
200
400
600
1600
3000
4700
DC
ITT
Part
No.
.:='" 8AIPAI
x ... 15AIPAI
8LJ.J~~ 10lAIEXI
M~CI)~
102AIEXI
o..... I-UJQ:;
~~
103AIEXI
104AIEXI
Cl:cc:cZ::
~~~B
Package Dimensions
Style A
8
age
Style
Volt·
Dimensions
A
B
age
Max. Curr!nt
DCCoil For 300V
Current Max. Rise
ITT
Part
Range
rnA
rnA
No.
Pack·
age Dimensions
Style A
8
ITT
Part
No.
Pack·
age Dimensions
Style A
B
1·7.32
1·7 32
1·3'16
29!J2
1·1.14 1·1/4
1·17/32 Hi2
I
I
2
2
2
2
25164 5/8
1/2
5/8
11/16 15/32
I
15/32
1·1/4 1/2
1·17/3217/32
8AIHAI'
15AIHAI'
10lAIAXI
102AIAXI
103AIAXI
104AIAXI
I
I
4
4
4
4
29/32
1/2
9/16 29;32
11/16 11.16
25,32
I
1·1/4 3/4
1·17/3213116
79·104
200
400
600
1600
3000
4700
IS
35
60
160
300
470
8A4PA4
15A4PA4
10lA4EX4
102A4EX4
103A4EX4
104A4EX4
I
I
2
2
2
2
25'64 15'16
15116
1'2
11'16 29'-32
31'32
I
1-1/4 1·5.32
1·17/321·532
8A4HA4*
15A4HA4*
10lA4AX4
102A4AX4
103A4AX4
104A4AX4
I
I
3
4
4
4
12
9 16
11/16'
I
105·130
200
400
600
1600
3000
4700
10
20
3D
80
150
250
8A5PA5
15A5PA5
10lASEX5
102A5EX5
103A5EX5
104A5EX5
I
I
2
2
2
2
25 '64 15;16
15 '16
1/2
11;16 I·L8
I
1·1l . 32
1-1/4 1·1'4
1·17,1321·13 32
8A5HA5'
15A5HA5*
10lA5AX5
102A5AX5
103A5AX5
104A5AX5
I
I
4
3
4
3
1.2
1·7132
9,16
1·7.132
11/16 1·1'8
1·518
I
1·1;4 I-7l16
1·17;321·718
27·52
200
400
600
1600
3000
4700
200
400
600
1600
3000
4700
8A2PA2
15A2PA2
10lA2EX2
102A2EX2
103A2EX2
104A2EX2
I
I
2
2
2
2
25/64 5/8
1/2
3/4
11/16 112
I
1l/16
H;4 llil6
1·17,3223/32
8A2HA2*
15A2HA2*
IDIA2AX2
102A2AX2
103A2AX2
104A2AX2
I
I
4
4
4
4
1/2
1·1/32
9/16
1·1 '32
11/16 23,32
I
1-1/32
1·1/4 7/8
1·17;321
53·78
200
400
600
1600
3000
4700
60
140
250
650
1200
2000
8A3PA3
15A3PA3
10lA3EX3
102A3EX3
103A3EX3
104A3EX3
I
I
2
2
2
2
25/64 3/4
3/4
1/2
1l/16 13/16
I
7/8
1·1/4 1·3/16
1·17/321
8A3HA3*
15A3HA3*
10lA3AX3
102A3AX3
103A3AX3
104A3AX3
I
I
4
3
4
4
1-1/32
1/2
9/16
1·1/32
1l/16 27/32
I
1·7/16
H/4 1-1/4
1·17/321·5/16
NOTE: Hermetically sealed tubular construction to meet MIL specifications for environmental exposure.
12-3
SELENIUM CONTACT PROTECTORS
CAUSE OF CONTACT ARCING
Consider the circuit shown in Figure 1. Close the circuit contacts SI
and the current flow as indicated
by the ammeter MI builds up to
400 mAo The flow of current has
set up a magnetic field through
the core. Electrical energy has
been stored in the magnetic field
by the current, analogous to the
mechanical energy stored in a
spring by compression.
Now open the contacts SI thus
breaking the steady flow of current. Just as the compressed
spring will start to release its
stored mechanical energy, the
magnetic field starts to collapse,
releasing its stored energy. While
the magnetic field is collapsing it
induces a voltage in the coil that
acts to maintain the current
through the coil in the same
direction as the original current
which built up the field. The mag-
IRON}
CORE
nitude of this induced voltage is
eq ua I to the prod uct of the co iI
current, and the coil and circuit
resistance; and it can attain very
high values since the circuit resistance approaches infinity with
the switch contacts open.
WIRE
COIL
CONTACTS
Theoretically, when the flow of
current is suddenly stopped by the
opening of Slo the voltage that
appears across the coil could go
up to infinity. Approximately 300
volts is required to produce arcing
across contacts in free air. Since
air is not a perfect insulator, the
instant that SI is opened and the
high induced voltage appears
across the contacts, an arc occurs.
In typical applications, air breakdown across the contacts will limit
the voltage rise to the regIon of
300 to 1,000 volts in an average
24-volt coil circuit. See Figure 2.
R=60 OHMS
FIG.1
FIG.2
HOW ITT SELENIUM CONTACT PROTECTORS WORK
Half-wave configuration for
DC applications
Consider the circuit of Figure 3,
showing contact protector cell A
connected across the coil terminals. While contacts SI are held
closed a current of 400 milliamperes flows through the coil, but
no part of the coil current flows
through the contact protector.
When SI is opened coil current
flows in the low-resistance direction of the contact protector, thus
dissipating the energy stored in
the coil through the resistance of
the coil and contact protector. As
the resistance of the contact pro-.
tector is very low, usually a fraction of the coil resistance, the
voltage across the contacts rises
only. slightly, to a few volts above
battery voltage.
II: 400MA
1I
FIG. J
Half-wave configuration, continued
In the circuit shown in Figure 4,
cell B has been added in such a
direction as to oppose the discharge current I". A semicond.uctor
cell has the unique characteristic
of exhibiting decreasing resist-
ance with increasing voltage in
the blocking direction.
At the instant switch SI is opened,
the induced voltage rises to approximately 150 volts, due to the
blocking action of cell B. This induced voltage is indicated in Figure 4 and appears as a reverse
voltage across cell B, i.e., the highresistance direction.
- - - - . II =400MA
-}IOO'
r4V.
20DV
'---'-~.+
~I
FIG.4
12-4
SELENIUM CONTACT PROTECTORS
Figure 5 shows the change in reo
verse resistance with application
of reverse voltage to a typical
sem iconductor contact - protector
cell. At the working voltage of 24
volts, the reverse resistance is approximately 1 megohm, When S,
is opened, the voltage across the
coil b.uilds up to approximately
-200 volts, At this voltage the reverse resistance of cell B will be
less than 500 ohms, Much of the
stored energy is dissipated in this
low-resistance region of the cell
c ha racteri stic.
As the energy is dissipated and
the current decreases, the induced
voltage also decreases, The remainder of the stored energy is
d i ssi pated ina h igher-resista nce
region than initially. For example,
as the Induced voltage decays to
-25 volts, the cell resistance rises
to approximately one megohm.
Thus the effect of the nonlinear
resistance of cell B is to provide,
at the instant of switching, a path
of relatively low resistance to prevent the induced voltage from rising to a value which will cause
arcing. As the stored energy is
dissipated the low resistance in-
Back-to-back configuration for
AC applications
The back-to-back configuration is
readily adapted to use in AC circuits by providing the same number of cells in each arm of the
device. The number of cells in
series per arm will depend on the
applied AC voltage. The requirement for the same number of cells
in each arm arises from the fact
that both arms alternately are required to block the input voltage.
This arrangement differs from the
DC back-to-back configuration in
which one arm has sufficient cells
to block the battery voltage and
the other has only one or two cells
to provide the surge suppression.
creases, due to the nature of the
cell characteristics, and provides
a damping effect on the discharge
current. The result is to reduce
the coil release time as compared
to the action of the half-wave-type
contact protector,
Figure 6. Oscillograph trace voltage across a set of contacts breaking the circuit of a 48-volt telephone relay, without contact protection. Sparking tlegins at 300
volts (see oscillations), continues
as contacts are separated and
rises to a voltage peak at 500 volts.
Voltage decay is exponential.
~
10·
J
10'
I
I
10·
10'
10'
-150
L
V
L
L
/
- ,0
-100
vOLTAGE
FIG.5
Figure 7. Oscillograph trace of
voltage across same set of contacts, protected by ITT half-wave
semiconductor contact protector.
Figure 8. Oscillograph trace of
voltage across same set of contacts, protected by ITT back-toback semiconductor contact protector.
FFRr=++=1
[E~
o
10 20
a
10 20
TIME MILLISECONDS
FIG.6
FIG.7
FIG.8
Factors relating to the opening
After the circuit opens, and asof inductive circuits
suming no arcing occurs, the time
It can be shown mathematically for the cu rrent to fa II to a percentthat the time required for the coil age of its initial value is given by
current to drop to zero, after the the following equation:
switch contacts have opened, is
inversely proportional to the sum
of the coil resistance and protec- t=~log~
RL+r EI
tor resistance. Also, the magnitude of the voltage induced in the When R = Coil resistance
r = Forward resistance of
coil at the instant of switching is
rectifier
directly proportional to the sum
L = Indudance of coil
of these resistances.
t = Time for current to
When the circuit energizing an indecrease to i
ductance is opened the polarity
i = Current at time t
of the voltage across the coil is
I = Steady-state current
reversed and is indicated by the
through the coil
equation E = - L9i
E = Supply voltage
dt
12-5
I
SELENIUM CONTACT PROTECTORS
The voltage induced across the
coil is expressed by the equation
di
Rl +r
V = -L-= (Rl+r) IE--L-t
dt
protected con'tacts, it is very appreciably shorter than the decay
time of a circuit using the halfwave configuration,
The current values listed in the
column "Coil Current for 300-V
Max, Rise" are representative
values, based on the observation
of typical relays and solenoids,
The maximum value of voltage V APPLICATION NOTES
The specific value of current that
occurs when t =
V max, =
will limit the voltage at the conI(R + r) = E+ Ir
Voltage Range
tacts to 300 volts is a function of
In an inductive circuit with un- The words "voltage range" are 'the coil design, the size of the coil,
protected switch contacts, the coil used because the maximum volt- the number of turns of Wire, etc"
current decays through a path that age rating increases in discrete and it is possi~le for a contact proincludes the widening air gap be- steps, according to the number of tector to furnish adequat,e spa,rk
tween the moving contacts, The blocking cells in series, Each pro- suppression when used with cOils
high resistance of this gap results tector has a maximum permissible carrying currents greater, than
in a very short current decay time, voltage rating which is the low- those listed; but the. maximum
However, the voltage induced in voltage end of the range for the current rating, should not ,be ~xthe coil at the instant of switch- next higher voltage group,
ceeded, For this rea~on, It IS WIS~
i ng must rea c h a va I ue h i g h ,
to observe the action and efflenough to force the current across Max, COil, Current - m~ ,
,ciency of the protector before
the air gap, This leads to the elec- The ma~lmum permissible cOil freezing a design, Samples and
trical breakdown of the air gap curr~nt ,IS based on ,th~ thermal engineering assistance are availwith attendant arcing, contact dissipation characterIStics of the able upon written request to the
damage and electrical noise,
contac~ protec~or when operated Engineering Department.
at maximum cOil voltage and repe'
In the half-wave configuration the tition rate,
In selecting a suitable Contact
Protector from the list in this data
resistance of the protector is low Coil Current for 300-V Max.
sheet, it should be noted:
when it is acting as a suppressor, Rise _ mA
since the coil current flows in the At the instant of switching, the Ratings are based upon operation
low-resistance forward direction
th
h th
t t
. in typical inductive circuits at
roug
e pro ec or IS
of the device, The forward resist- current
the same as the coil current, and temperatures of 50 e C or lower.
ance of the half-wave suppressor the induced voltage at the coil Current ratings given in the colwill usually be only a small frac- terminals will rise to the value umn headed "Coil Steady State
tion of the coil resistance and, for required to drive this current Current for 300 volt max. rise"
practical purposes, may be re- through the protector, This volt- represent the rating of the progarded as a short circuit around
'II dd t th
I
It
tector to limit the voltage rise
0
e supp y vo age
t he coil, The low value of protector age WI a
and appear across the contacts. across the contacts to approxiresistance prevents the induced Sparking at the contacts will be mately 300 volts. This rating may
voltage from rising more than a minimized if the sum of these two be exceeded if a rise in excess of
volt or two over the battery volt- voltages does not exceed 300 volts, 300 volts is permissible, but the
age, and increases the current de- and this requirement is met if the maximum peak current rating
cay time compared to the decay . d
d It'
t th
should not be exceeded, The voltt 'lme of a coil with unprotected In uce vo age IS no grea er an
the difference between 300 and age rating should not be exceeded
contacts.
the supply voltage. This condition under any circumstances,
In the back-to-back configuration is achieved by reducing, for a
the reverse resistance of the pro- given cell size, the permissible Fast Contact Action
tector is inversely proportional to coil current as the supply voltage
the induced voltage. This resist- increases. Thus, it will be ob- Rate of operation of contacts in
ance will be the smallest at the served that the coil current for the range 10 to 40 breaks per secinstant of switching and will in- 300-volt rise will be less than the ond. The back - to - back arrangecrease in value as the current de- maximum coil current for many of ment of the ITT Contact Protector
creases. This n'onlinear resistance the higher-voltage units, Con- provides adequate arc suppression
characteristic causes the induced versely, the coil current for 300- with a negl igible effect upon the
, voltage to rise to a value higher volt rise is so great that it exceeds release time of the relay, The prothan it would reach in a circuit the maximum coil current for the tectors are fated for applications
using the half-wave configuration, low-voltage units. These protec- where the rate of operation of the
but it prevents the induced volt- tors carry the note in the rating contacts is in the range of 10 to 40
age from attaining the contact- table "MA for 300-Volt Rise Ex- breaks per second. ITT should be
damaging values existing in a cir- ceeds Max. Current Rating"; this consulted for recommendations if
cuit with unprotected contacts, means that operation at the listed the rate of operation exceeds 40
Although the current decay time is maximum coil current will give a breaks per second.
increased somewhat compared to voltage rise of less than 300 volts
the decay time of a coil with un- - at the contacts.
a
12-6
.......
ITT
SEMICONDUCTORS
SELENIUM TRANSIENT VOLTAGE SUPPRESSORS
...............
--~~
DIMENSIONS
TRANSIENT VOLTAGE
SUPPRESSOR RECTIFIERS
PAPER TUBE TYPE
• AC Input or DC Applications
• Improve Equipment Reliability
• Reduce Equipment Cost
~~.UG(
~-@
ITT transient voltage suppressors eliminate one of the major causes of
failure of semiconductor rectifiers by instantaneously short-circuiting
transient voltages in excess of the ratings of the rectifiers. They permit
the circuit designer to use rectifiers with lower PIV ratings, thereby reducing equipment cost. These specially processed selenium cells have
very sharp "zener" breakdown characteristics when operated in the
reverse direction. Since the reverse characteristic is used instead of the
forward characteristic, aging has very little effect on the resistance and
suppressing voltage level of the protector. The small effects of aging and
temperature variations have been taken into consideration in the voltampere curves and tabulated characteristics.
In inductive circuits using mechanical switches, these suppressors can
be used to eliminate pitting of the switch contacts by absorbing the high
peak voltages generated when the switch is opened. ITT contact protector
selenium rectifiers can also be used in this application.
Transient voltage suppressors can be mounted by eyelets or studs in
stack types and by clips or pigtail leads in tubular types. Stack types are
supplied with a standard industrial finish or with a moisture resistant
finish for protection against salt spray and humidity.
2'~~""",,
'*""~
PHENOLIC TUBE TYPE
EYELET TYPE
STUD TYPE
RATINGS
CHARACTERISTICS
8A SERIES
25A SERIES 102 SERIES
UNITS
Steady State RMS Volts/Cell
Peak Volts/Cell
DC Volts/Cell
Stack RMS Volts
Stack DC Volts
Steady State Leakage Current
(max.)
Single Pulse Current
(4 milliseconds) (max.)
Recurrent Pulse Current
(1 millisecond @ 60 cps) (max.)
Ambient Temperature
Cell Operating Temperature (max.)
Construction
30
42.4
20
30-600
20-400
0.8
30
42.4
20
36-600
20-400
1.2
25
35
20
25-500
20-320
12
Volts
Volts
Volts
Volts
Volts
mA
0.75
2
8
Amps
0.25
0.75
3
Amps
-20 to +100 -20 to +100 -20 to +100 °C
°C
130
130
130
Tubular
Tubular
Stud Or Eyelet
12-7
.... '/)2
SELENIUM TRANSIENT VOLTAGE SUPPRESSORS
ELECTRICAL AND MECHANICAL CHARACTERISTICS
AC INPUT TYPES
PAPER TUBE TYPES
MAX.
RMS
INPUT
VOLTS
MAX.
PEAK
INPUT
VOLTS
MAX.
ZENER
VOLTS'
DIA.
(A)
LENGTH
(B)
ITT
PART NO.
42
S5
127
170
212
254
297
339
382
424'
467
509
551
594
636
679
721
764
806
848
104
20S
312
416
519
623
727
S31
934
1039
1143
1247
1350
1454
155S
1663
1766
1S70
1974
2078
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/S
3/8
3/S
3/8
3/S
3/8
3/8
318
318
27/32
27/32
27/32
27/32
27/32
3/32
3/32
3/32
3/32
3/32
21/64
21/64
21/64
21/64
21/64
37/64
37/64
37/64
37/64
37/64
SA1PGl
SA2PG2
SA3PG3
8A4PG4
8A5PG5
SA6PG6
SA7PG7
SASPGS
SA9PG9
8Al0PG10
SAllPGli
8A12PG12
8A13PG13
SA14PG14
8A15PG15
8A16PG16
8A17PG17
8A18PG18
8A19PG19
8A20PG20
30
60
90
120
150
ISO
210
240
270
300
330
360
390
420
450
480
510
540
570
600
MAX.
RMS
INPUT
VOLTS
DIMENSIONS
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MAX.
PEAK
INPUT
VOLTS
MAX.
ZENER
VOL1$'
DIA.
(A)
42
85
127
170
212
254
297
339
382
424
467
509
551
594
636
679
721
764
806
S4S
87
177
266
354
443
532
620
709
79S
886
975
1063
"52
1241
1329
1417
1507
1595
1684
1772
37/64
37/64
37/64
37/64
37/64
37/64
37/54
37/64
37/64
37/64
37/64
37/64
37/64
37/64
37/64
37/64
37/64
37164
37164
37164
30
60
90
120
150
180
210
240
270
300
330
360
390
420
450
480
510
540
570
600
DIMENSIONS
LENGTH
(B)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ITT
PART'NO.
25Al PGl
25A2PG2
25A3PG3
25A4PG4
25A5PG5
25A6PG6
25A7PG7
25A8PGS
25A9PG9
25Al0PG10
25A" PGll
25A12PG12
25A13PG13
25A14PG14
25Al 5PGl 5
25A16PG16
25A17PG17
25A1SPG1S
25A19PG19
25A20PG20
1/64
1/64
1/64
1/64
1/64
1/4
1/4
114
1/4
1/4
1/2
1/2
1/2
1/2
1/2
314
314
3{4'
314
314
PHENOLIC TUBE TYPES
MAX.
RMS
INPUT
VOLTS
30
60
90
120
150
180
210
240
270
300
330
360
390
420
450
480
SID
540
570
600
MAX.
PEAK
INPUT
VOLTS
42
85
127
170
212
254
297
339
3S2
424
467
509
551
594
636,
679
721
764
S06
84S
DIMENSIONS
MAX.
ZENER
VOLTS'
104
208
312
416
519
623
727
831
934
1039
1143
1247
1350
1454
155S
1662
1766
1870
1974
207S
OIA.
(A)
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
15/32
LENGTH
(8)
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
311!2
31/32
117/64
117/64
I 17/64
117/64
117/64
11/2
11/2
11/2
11/2
11/2
FERRULE
LENGTH
(C)
3/8
3/8
3/8
318
318
3/8
3/8
3/8
3/S
3/S
3/S
3/S
3/S
3/S
318
3/8
3/8
318
3/S
3/S
FERRULE
WIRE LEAO
MAX.
RMS
INPUT
VOLTS
8AIQBGI
8A2QBG2
8A3Q8G3
8A4QBG4
8A5Q8G5
8A6Q8G6
8A70BG7
BA8QBG8
SA9QBG9
SAIOQBGIO
SAllQBGll
SAI2QBGI2
8AI3QBGI3
8AI4QBGI4
8AI5QBGI5
8AI6QBGI6
SAI7QBG17
SAISQBGIS
8AI9QBGI9
SA20QBG20
8AIABGI
8A2ABGZ
8A3ABG3
8A4ABG4
8A5ABG5
8A6ABG6
8A7A8G7
8A8ABG8
8A9ABG9
SA10ABG10
SAllABGll
8AI2ABGI2
SAI3ABGI3
8AI4ABGI4
SAI5ABGI5
SAI6ABGI6
SA17ABG17
SAISABGIS
SAI9ABGI9
SA20ABG20
30
60
90
120
150
ISO
210
240
270
300
330
360
390
420
450
4BO
510
540
670
600
ITT PART NO.
EYELET TYPES
MAX.
PEAK
INPUT
VOLTS
42
S5
127
170
212
254
297
339
3S2
424
467
509
551
594
636
679
721
764
806
84S
DIMENSIONS
MAX.
ZENER
VOLTS'
104
20S
312
416
519
623
727
S31
934
1039
1143
1247
1350
1454
155S
1662
1766
1870
1974
2078
OIA.
(A)
LENGTH
(B)
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31132
I
I
I
I
I
I
I
I
I
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
31/32
1/32
1/32
1/32
1/32
1/32
1/32
1/32
1/32
1/32
11/32
I 29/64
FERRULE
LENGTH
FERRULE
WIRE LEAD
13132
13132
25AIQBGI
25A2QBG2
25A3QBG3
25A4QBG4
25A5QBG5
25A6QBG6
25A7QBG7
25ASQBGS
25A9QBG9
25AIOQBGIO
25AllQBGll
25A12QBGI2
25AI3QBGI3
25AI4QBGI4
25A15QBG15
25AI6QBGI6
25A17QBG17
25AISQBG18
25AI9QBGI9
25A20QBG20
25AIABGI
25A2ABG2
25A3ABG3
25A4ABG4
25A5ABG5
25MABG6
25A7ABG7
25A8ABGS
25A9ABG9
25AIOABGIO
25AllABGll
25AI2ABGI2
25AI3ABGI3
25AI4ABGI4
25AI5ABGI5
25AI6ABGI6
25AI7ABGI7
25A18ABGIS
25AI9ABGI9
25A20ABG20
13/32
13132
13/32
13132
13/32
13/32
13132
129164
I 29164
13/32
13/32
13/32
13/32
129/64
13132
I 29/64
111/16
1 11/16
111116
111/16
1 11/16
ITT PART NO.
(C)
13/32
13132
13132
13132
13/32
13/32
STUD TYPES
DIMENSIONS
MAX. RMS
INPUT
VOLTS
MAX. PEAK
INPUT'
VOLTS
MAX.
ZENER
VOLTS'
25
50
75
100
125
150
175
200
35
70
lOS
140
175
210
245
2S0
80
159
239
319
398
478
558
637
DIMENSIONS
LENGTH (B)'
ITT
PART NO.
47/64
13/16
57/64
31/32
3/64
1/8
13164
19/64
102Gl EXI
102G2EX2
102G3EX3
102G4EX4
102G5EX5
102G6EX6
102G7EX7
102G8EX8
I
I
I
I
MAX. RMS
INPUT
VOLTS
25
GO
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
600
NOTES: 1. At 4 millisecond pulse current=O.75 Amperes
2. At 4 millisecond pulse current=2 Amperes
3. At 4 millisecond pulse current=8 Amperes
12-8
MAX. PEAK MAX.
INPUT
ZENER
VOLTS
VOLTS'
35
70
105
140
175
210
245
2S0
315
350
385
420
455
490
525
560
595
630
665
700
840
80
159
239
319
398
47S
558
637
717
797
S76
956
1035
11 15
1195
1274
1354
,1434
1513
1593
1913
STUD
LENGTH
(A)
STACK
LENGTH
(B)
ITT
PART NO.
I 7/16
I 1/2
I 5/8
I 11 116
1 3/4
I 7/S
I 15116
2
2 1116
2 3116
2 114
2 5/16
2 31S
2 112
2 9116
2 518
2 314
2 13116
2 71S
215116
3 5116
15116
I
I 1/8
I 3116
I 1/4
I 318
I 7 II 6
I 1/2
I 9116
I " 116
I 314
I 13116
I 7/8
2
2 1/16
2 1 IS
2 1/4
2 5116
2 31S
2 7116
213116
102Gl BXl
102G2BX2
102G38X3
102G4BX4
102G5BX5
102G6BX6
102G7BX7
102G8BXS
102G9BX9
102Gl0BX10
I 02G" BX"
102G12BX12
102G13BX13
102G14BX14
102G15BX15
102G16BX16
102G17BX17
102G18BX1S
102G19BX19
102G20BX20
102G24BX24
TRANSIENT VOLTAGE SELENIUM
SUPPRESSORS
ELECTRICAL AND MECHANICAL CHARACTERISTICS - DC INPUT TYPES
PAPER TUBE TYPES
MAX.
RMS
INPUT
VOLTS
MAX.
PEAK
INPUT
VOLTS
MAX.
ZENER
VOLTS
DIA.
(A)
LENGTH
(6)
20
40
60
80
100
120
140
160
I BO
200
220
240
260
2BO
300
320
340
360
3BO
400
31
63
93
126
157
1 BB
220
251
282
314
345
377
409
440
472
502
534
566
597
62B
104
208
312
416
519
623
727
831
934
1039
1143
1247
1350
1454
155B
1662
1766
lB70
1974
207B
31B
318
31B
31B
318
318
31B
31B
31B
31B
31B
31B
31B
31B
31B
31B
31B
31B
31B
31B
27132
27132
27132
27132
27132
27132
27132
27132
27132
27132
3132
3132
3132
3132
3132
3132
3132
3132
3132
3132
ITT
PART NO.
MAX.
RMS
INPUT
VOLTS
MAX.
PEAK
INPUT
VOLTS
MAX.
ZENER
VOLTS'
8Al PGO
8A2PGO
8A3PGO
BA4PGO
8A5PGO
BA6PGO
BA7PGO
8A8PGO
BA9PGO
8Al0PGO
BAll PGO
BA12PGO
BA13PGO
BA14PGO
BA15PGO
BA16PGO
BA17PGO
BAI BPGO
BA19PGO
BA20PGO
20
40
60
BO
100
120
140
160
1BO
200
220
240
260
280
300
320
340
360
380
400
31
63
93
126
157
18B
220
251
2B2
314
345
377
409
440
472
502
534
566
597
62B
B7
177
266
354
443
532
620
709
79B
BB6
975
1063
1152
1241
1329
1417
1507
1595
1684
1772
DIMENSIONS
I
1
I
1
I
I
I
I
I
I
DIMENSIONS
DIA.
(A)
LENGTH
(6)
37/64
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
37164
ITT
PART NO.
I 1164
I 1164
1 1164
I 1164
I 1164
I 1164
I 1164
I 1164
I 1164
1 1164
1 114
1.114
1 114
1 114
I 114
I 114
I 114
1 114
I 114
1 114
25Al PGO
25A2PGO
25A3PGO
25A4PGO
25A5PGO
25A6PGO
25A7PGO
25A8PGO
25A9PGO
25Al0PGO
25Al1PGO
25A12PGO
25A13PGO
25A14PGO
25A15PGO
25A16PGO
25A17PGO
25A18PGO
25A19PGO
25A20PGO
PHENOLIC TUBE TYPES
MAX.
RMS
INPUT
VOLTS
MAX.
PEAK
INPUT
VOLTS
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
310
340
360
380
400
31
63
93
126
157
lB8
120
251
2B2
314
345
377
409
440
472
502
534
566
597
62B
DIMENSIONS
MAX.
ZENER
VOLTS'
104
208
312
416
519
623
727
831
934
1039
1143
1247
1350
1454
1558
1662
1766
1870
1974
207B
DIA.
(A)
LENGTH
(B)
15m
31132
31132
31132
31132
31132
31132
31132
31132
31132
31132
31/32
31131
31132
31132
31131
31132
31/32
31132
31132
31132
15132
15132
15132
15132
15132
15132
15132
15132
15m
15132
15132
15132
15132
15131
15132
15132
15/32
15132
15{32
FERRULE
LENGTH
(C)
318
318
318
318
318
31B
318
318
318
318
31B
318
318
318
318
31B
31B
318
31B
318
ITT PART NO.
FERRULE
8Al08GO
8A208GO
8A30BGO
8A40BGO
8A50BGO
8A60BGO
8A70BGO
8A80BGO
8A90BGO
8Al00BGO
8All OBGO
8AlZOBGO
BAI30BGO
8A140BGO
BA1508GO
BA160BGO
8A170BGO
8A1808GO
8A190BGO
BA200BGO
WIRE LEAD
8A1A8GO
8A2ABGO
8A3ABGO
8A4ABGO
8A5ABGO
8A6ABGO
8A7ABGO
8A8ABGO
8A9ABGO
8A 1OABGO
BA11ABGO
8412ABGO
8A13ABGO
8A14ABGO
8A15ABGO
8A16ABGO
8A17ABGO
8A18ABGO
8A19A8GO
BA20A8GO
EYELET TYPES
MAX.
RMS
INPUT
VOLTS
MAX.
PEAK
INPUT
VOLTS
20
40
GO
80
100
120
140
160
180
200
220
240
260
280
300
320
340
360
3BO
400
31
63
93
DIMENSIONS
MAX.
ZENER
VOLTS'
104
20B
312
416
519
623
126
157
lB8
210
251
282
314
345
377
409
440
472
502
534
566
597
62B
727
B31
934
1039
1143
1247
1350
1454
155B
1662
1766
lB70
1974
207B
OIA.
(A)
LENGTH
(B)
FERRULE
LENGTH
(C)
FERRULE
WIRE LEAD
31132
31132
31132
31132
31131
31132
31132
31132
31m
31132
31132
31m
31132
31132
31132
31132
31132
31132
31132
31/32
1 1132
1 1132
1 1m
1 1132
1 1132
1 1132
11132
1 1132
1 1132
1 1m
1 1/32
11132
11132
11132
11132
11132
11132
11132
1 1132
11132
13132
13132
13131
13132
13132
13132
13132
13132
13132
13132
13132
13m
13132
13132
13132
13132
13132
13132
13132
13{32
25Al0BGO
25A20BGO
25A30BGO
25A40BGO
15A508GO
25A60BGO
25A708GO
25ABOBGO
25A908GO
15Al00BGO
25Al10BGO
25A120BGO
25A130BGO
15A140BGO
15A150BGO
15A160BGO
15A170BGO
25Al BOBGO
25A190BGO
25A200BGO
25A1ABGO
25A2ABGO
25A3ABGO
25A4ABGO
25A5A8GO
25A6ABGO
25A7ABGO
25ABABGO
25A9A8GO
25Al0A8GO
15AllABGO
25A12ABGO
25A13A8GO
25A14ABGO
25A15ABGO
25A16ABGO
25A17ABGO
25A1BABGO
25A19ABGO
25A20ABGO
ITT PART NO.
STUD TYPES
DIMENSIONS
MAX. RMS
INPUT
VOLTS
MAX. PEAK
INPUT
VOLTS
MAX.
ZENER
VOLTS'
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
320
31
63
93
126
157
188
220
251
282
314
345
377
409
440
472
502
80
159
239
319
398
478
558
637
717
795
876
956
1035
1115
1195
1274
DIMENSIONS
LENGTH (6)
27132
718
29132
15116
1
1 1132
1 1116
1 118
I 5132
I 3116
I 114
I 9132
I 5{16
I 1 I 132
I 318
I 7{16
NOTES: 1. At 4 millisecond pulse current=O.75 Amperes
2. At 4 millisecond pulse current=2 Amperes
3. At 4 millisecond pulse current=B Amperes
MAX. RMS
INPUT
VOLTS
~X. PEAK
ITT
PART NO.
INPUT
VOLTS
MAX.
ZENER
VOLTS'
102Gl EXO
102G2EXO
102G3EXO
102G4EXO
102G5EXO
102G6EXO
102G7EXO
102G8EXO
102G9EXO
102Gl0EXO
102GllEXO
102G12EXO
102G13EXO
102G14EXO
102G15EXO
102G16EXO
20
40
60
BO
100
120
140
160
180
200
220
240
260
2BO
300
320
31
63
93
126
157
188
220
251
2B2
314
345
377
409
440
472
502
BO
159
239
3\9
398
47B
558
637
717
797
876
956
1035
1 I 15
1195
1274
12-9
STUD
LENGTH
(A)
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
2
5{16
318
31B
7116
112
51B
51B
11116
314
314
13/16
71B
15116
15116
15116
STACK
LENGTH
(6)
1
1
1
1
1
1
1
1
1
1
1
13116
27132
71B
29!32
15116
3132
118
3116
7132
1/4
9132
11132
31B
13132
15132
112
ITT
PART NO.
102G1BXO
·102G2BXO
102G3BXO
102G4BXO
102G5BXO
102G6BXO
102G7BXO
102GBBXO
102G9BXO
102Gl0BXO.
102G116XO
102G12BXO
10ZG13BXO
102G14BXO
102G15BXO
102G16BXO
SELENIUM TRANSIENT VOLTAGE SUPPRESSORS
HOW TO SELECT THE PROPER RECTIFIER
Determination of Current Rating
Although the peak value and duration of a transient current cannot
always be determined, certain
valid assumptions can be made to
determine the ITT suppressor rectifier current rating for the application.
For circuits in which a transformer
is the power source, usually the
greatest transient currents have
been observed when the circuit is
interrupted with no load on the
transformer. The transient current
is the magnetizing current of the
transformer. If the actual transient
current is not known, a valid assumption can be made by the use
of the magnetizing current versus
voltage on page 4. If the transient
results from opening a circuit containing an inductance, the transient current will be the current
through the inductance at the instant of interruption. To select the
proper ITT suppressor series, assume a single pulse width of 4
milliseconds and refer to the pulse
current versus time curve on page
4: The same curve can be used to
select the appropriate ITT series
when a single pulse width other
than 4 milliseconds is known or
assumed.
Voltage Rating
After the required current rating
has been established, determine
the maximum steady-state voltage
which will appear across the suppress?r rectifier and select the appropriate type number from the
tables on pages 2 and 3. Note that
both RMS and peak voltage ratings
are tabulated for AC types and DC
ratings for DC types. Use the RMS
value for. sinusoidal voltages'
otherwise, use the peak value of
the input voltage to select the
proper rectifier.
Zener Voltage
where the pUls'e wid'th is less than
4 milliseconds.
For other values of peak current,
however, the indicated Zener voltage will be as shown in the curves
on page 4. To obtain the expected
protection, rectifiers should be
used within their rated currents.
For optimum protection, the maximum Zener voltage should be below the PIV rating of tfie semiconductor devices being protected.
The maximum Zener voltages
shown in the characteristics
tables have been derived from the
curves on page 4 which represent
the conservative ratings placed on
suppressor rectifiers. These voltampere curves apply to a single
cell. To determine the Zener voltage for a particular rectifier,
multiply the peak voltage values
that are shown by the number of
cells per arm for AC rectifiers, or
by the total number of cells for
DC rectifiers. The final step is to
be sure that the silicon or
germanium rectifier or silicon
controlled rectifier to be protected
has a PIV rating higher than the
Zener voltage of the ITT protector
rectifier. The volt-ampere curves
~re also v~li~ for DC applications
I~ determining the proper rectifier for a given peak transient
voltage.
Similar protection is also provided
to transformers, capacitors resistor~, switches, relays, or' any
electrical component subject to
damage from transient over-voltage.
3. From the RATINGS table on
page 1, select a rectifier series
whicH will withstand 3.8SA peak
@ 4 millisecondplilse width.
The 102 series, either stud
mounting or eyelet mounting
may be used. Assume a stud
type is preferred for this application.
4. Select the appropriate ITT part
number from the stud mounting table on page 2 by finding a
type with a RMS input voltage
rating equal to or above 115V.
102GSBXS meets this requirement.
S. De~ermine the PIV rating reqUired for the rectifier to be
protected. Use the 102 series
curve on page 4 to determine
the voltage corresponding to
3.8SA. The maximum voltage is
73 volts per cell. The number
of cells in each rectifier is indicated by the first number
after the first letter in the part
number. In this case the
102GSBXS has five cells. The
maximum voltage is 73 X S =
36SV. The PIV rating required
for the protected rectifier is
36SV.
CODING SYSTEM FOR EYELET AND
STUD TYPE ITT SELENIUM VOLTAGE
SUPPRESSOR RECTIFIERS
102 G 5 E X 5
I
~lNumber
Indicates
Number
of ce.llS
0= Always
Indicates
DC Oevice
letter Indicates Finish
X= Industrial
y= Humidity Resistant
YF= Humidity and Fungus Resistant
letter Indicates Construction
A=Stud
B=Screw
E- Eyelet
Number Indicates Number of Cells
Indicates ITT Suppressor Rectifier
l~===GNumbers
Indicate Cell Size
and Voltage
Example
As.sume a single phase fullcwave
102- 1" SQ. 25 VAC 20 VDC
bridge rectifier application with
a transformer rated at 8.SKVA CODING SYSTEM FOR TUBULAR TYPE
~ISV. The rectifier to be protected In SELENIUM VOLTAGE SUPPRESSOR
IS across the transformer sec- RECTIFIERS
ondary.
8 A 5 P G 1
1. Assume a 4 millisecond pulse
~L
Indicates Number of Cells
L Number
Q=Always Indicates DC Device
width.
G I ndicates ITT Suppressor Rectifier
. letter Indicates Construction
2. From. the curve on page 4, deP= Paper Tube
H= Hermetically Sealed Can
terf!1l.ne the per cent of magnetizing current. Using the
~~: ~~~nn~:f/~~~:A'~r~r l:!~inaIS
Terminals
"maximum" plot line, 8.SKVA
Number Indicates Number of Cells
ZS.2% of full load current.
I
The Zener voltages shown in the
characteristics tables are the maxi~um instantaneous voltages that
will appear across the rectifier if
the 4 millisecond current rating
is not e~c.eeded. Any ITT suppres- Full load current VA z 8S00 Z 74A
s
en
~
Single-Phase Half-Wave Silicon Rectifier'
DC CONTACT
PROTECTOR
Single-Phase Full-Wave Center Tap Silicon Rectifier
~
~
n.
n.
n.
::>
~ 110---.....---.
.
en
en
o
o
~
~
DC CONTACT
PROTECTOR
+
RESISTIVE OR CAPACITIVE LOAD
Single-Phase Full-Wave Bridge Silicon Rectifier
RESISTIVE
OR
CAPACITIVE
LOAD
DC CONTACT
Three-Phase Full-Wave Bridge Silicon Rectifier
PROTECTOR
DC CONTACT
PROTECTOR
+
RESISTIVE OR
CAPACITIVE LOAD
INDUCTIVE LOADSingle-Phase Full-Wave Silicon Rectifier
Single-Phase Half-Wave Silicon-Controlled Rectifier
12-12
_I
1 N645 THRU 1 N649
DIFFUSED SILICON
mm
-L-L ______G_E_N_ER_A_L_-_PU_R_P_O_S_E_D_I_O_D_E_S
SEMICONDUCTORS
DIFFUSED SILICON GENERAL-PURPOSE DIODES
• Hermetically sealed
• Rugged construction
• 00-7 package
• High reliability
ABSOLUTE MAXIMUM RATINGS at 25 C Free-Air Temperature (unless otherwise noted)
IN64S 1N646 1N647 1N648 1N649
Characteristics
Symbol
D
225
Working Peak Reverse Voltage over
Operating Free-Air Temperature
Range
VRl\Itwlig)
400
300
500
Unit
V
600
10
Average Rectified Forward Current at
(or below) 25 D C Free-Air
Temperature Range
(See Note 1)
400
mA
10
Average Rectified Forward Current
at 150 D C Free-Air Temperature
(See Note 1)
150
mA
IFl'.I(surge)
Peak Surge Current, One Second,
at 25 D C to 150 D C Free-Air
Temperature (See Note 2)
P
Continuous Power Dissipation at (or
below) 25 D C Free-Air Temperature
(See Note 3)
3
Operating Free-Air Temperature
Range
TA(oprJ
A
600
mW
-65 to 150
°C
*IN645, IN647 and IN649 are available in JAN and JAN TX versions.
ELECTRICAL CHARACTERISTICS @ 25 D C Free Air Temperature (unless otherwise noted)
IN64S· 1N646
1N647 1N648 1N649
Min Max Min Max Min Max Min Max Min Max [unit
Symbol
Parameter
V(BR)
Reverse
Breakdown
Voltage
IR
Static
Reverse
Current
0.2
0.2
0.2
0.2
0.2
15
15
20
20
25
VF
Static
Foward
Voltage
1
1
1
1
1
CT
Total
Capacitance
360
275
6 typ
480
6 typ
NOTES:
1. These values may be applied continuously
under single-phase SO-Hz half-sine-wave operation with resistive load. Above 25°C see Thermal Characteristics Chart.
600
6 typ
720
6 typ
Conditions
V h,=100p.A,
T A =100 D C
6 typ
p.A VR=Rated VRM(wkg)
VR= Rated VRM(wkg)l
p.A T A =100 D C
V IF =400mA
pF VR=12V,
f=1 MHz
2. These values apply for a one-second squarewave pulse with the device at nonoperating
thermal equilibrium immediatelly prior to the
surge.
3. Derate linearly to 200 mW at 150°C free-air
temperature at the rate of 3.2 mW/deg.
12-13
ITT
----.
1 N4000 SERIES, EM500 SERIES
PLASTIC SILICON RECTIFIER
SEMICONDUCTORS
1-AMP PLASTIC SILICON RECTIFIERS
• Moisture resistant
• Voltages to 1000 volts
The ITT Plastic Silicon Rectifier is molded using a new plastic formulation' with the following
advantages over silicone and epoxy compounds:
ELECTRICAL CHARACTERISTICS @ 25°C Unless Otherwise Noted
Peak Reverse Voltage (PRV) ............ 50
100
200
400
600
800
1000
Average Rectified Current @ 25°C Ambient ..
Average Rectified Current @ 75°C Ambient .'.
Foward Voltage Drop @ 1 Amp ........... .
Reverse, Current @ Rated DC Voltage ..... ~ .
Full Cycle Average Reverse Current @ Rated
PRV @ 85°C Ambient @ Rated Average
Rectified Current ......................•...
100°C Ambient @ Rated Average Rectified
Current .......................... _. __ .... __ __
Half Cycle Surge Current, 60 Hz ........... .
Temperature Range (operating) ............ .
Temperature Range - Storage ............ .
*1N4000
Series
EM500
Series
1N4001 50
1N4002 100
1N4003 200
1N4004 400
1N4005 600
1N4006 800
1N40071000
1.0
1.0
1.1
10
(EM500)
(EM501)
(EM502)
(EM504)
(EM506)
(EM508)
(EM510)
1.0
0.5
1.1
1.0
Amps
Amps
Volts
Volts
200
200
Volts
50
30
-65 to +175
-65 to +200
50
50
-65 to +175
-65 to +200
Volts
Amps
• Electrical Equivalent
12-14
Units
Volts
o,C
°C
1N4000 SERIES, EM500 SERIES
PLASTIC SILICON RECTIFIER
ITT SILICON RECTIFIER CROSS-REFERENCE
Now you can replace older types of rectifiers
with dependable, inexpensive ITT Plastic
types. In most cases, the ITT types will have
higher output current and PRV ratings than the
types to be replaced. Case dimensions are not
always physically identical, in many cases the
ITT types are smaller.
Type
To Be
Replaced
iN253
iN254
iN255
iN256
iN3i6
iN3i6A
iN3i7
iN3i7A
iN3i8
iN3i8A
iN3i9
iN3i9A
iN320
iN320A
iN32iA
iN322A
iN323A
iN324A
iN325A
iN326A
iN327A
iN328A
iN329A
iN332
iN333
iN334
iN335
iN336
iN337
iN338
iN339
iN340
iN34i
iN342
iN343
iN344
iN345
iN346
iN347
iN348
iN349
ITT
Replacement
iN4002
iN4003
iN4004
iN4005
iN400i
iN400i
iN4002
iN4002
iN4003
iN4003
iN4004
iN4004
iN4005
iN4005
iN4007
iN4007
iN400i
iN4002
iN4003
iN4004
iN4005
1N4007
iN4007
iN4004
iN4004
iN4004
iN4004
iN4003
iN4003
iN4002
iN4002
iN4002
iN4004
iN4004
iN4004
iN4004
iN4003
iN4003
iN4002
iN4002
iN4002
Type
To Be
Replaced
iN359A
iN360A
iN36iA
iN362A
iN363A
iN364A
iN365A
iN440
iN440B
iN44i
iN44iB
iN442
iN442B
iN443
iN43B
iN444
iN44B
iN445
iN445B
iN530
1 N53i
iN532
iN533
iN534
iN535
iN536
iN537
iN538
iN539
iN540
iN547
iN550
iN55i
iN552
iN553
iN554
iN555
iN560
iN561
iN562
iN563
ITT
Replacement
,
iN4002
iN4002
iN4003
iN4004
iN4005
iN4007
iN4007
iN4002
iN4002
iN4003
iN4003
iN4004
iN4004
iN4004
iN4004
iN4005
iN4005
iN4005
iN4005
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
iN400i
iN4002
iN4003
iN4004
iN4004
iN4005
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
IN4006
iN4007
iN4006
iN4007
Type
To Be
Replaced
1N596
iN597
iN598
iN599
iN599A
iN600
iN600A
iN60i
iN60iA
iN602
iN602A
iN603
iN603A
iN604
iN604A
iN605
iN605A
iN606
iN606A
iN607
iN607A
iN608
iN608A
iN609
iN609A
iN6i0
iN6i0A
iN6ii
1 N6iiA
iN6i2
iN6i2A
iN6i3
iN6i3A
iN6i4
iN6i4A
iN645
iN645A
iN646
iN647
iN648
iN649
iN676
iN677
iN678
iN679
iN68i
iN682
iN683
iN684
iN685
iN686
12-15
Type
To Be
Replaced
ITT
Replacement
iN4005
iN4006
iN4007
iN400i
iN400i
iN4002
iN4002
iN4003
iN4003
iN4003
iN4003
iN4004
iN4004
1N4004
IN4004
iN4005
iN4005
iN4005
iN4005
iN400i
iN400i
iN4002
iN4002
iN4003
iN4003
1N4003
iN4003
iN4004
iN4004
iN4004
iN4004
iN4005
iN4005
iN4005
iN4005
iN4004
iN4004
iN4004
iN4004
iN4005
IN4005
iN4002
iN4002
iN4003
iN4003
iN4004
iN4004
iN4004
1N4004
iN4005
iN4005 __
I-
iN687
iN689
iN846
iN847
iN848
iN849
iN850
iNB5i
iN852
iN853
iN854
iN855
iN856
iN857
iN858
iN859
iN860
iN86i
iN862
iN863
iN864
iN865
iN866
iN867
iN868
iN869
iN870
iN87i
iN872
iN873
iN874
iN875
iN876
iN877
iN878
iN879
iN880
iN88i
iN882
iN883
iN884
iN885
iN886
iN887
iN888
iN889
1 Ni08i
1 Ni082
iNi083
iNi084
1 Ni095
ITT
Replacement
,
iN4005
iN4005
iN400i
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
iN4006
iN4006
iN4007
iN4007
iN4001
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
iN4006
iN4006
iN4007
iN4007
iN400i
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
iN4006
iN4006
iN4007
iN4007
1 N400i
iN4002
iN4003
iN4004
iN4004
iN4005
iN4005
1N4006
iN4006
iN4007
iN4007
iN4002
iN4003
iN4004
iN4004
iN4005
•
1 N4000 SERIES, EM500 SERIES
PLASTIC SILICON RECTIFIER
Type
To Be
Replaced
ITT
Replacement
Type
To Be
Replaced
ITT
Replacement
1N1096
1N1100
1N1101
1N1102
1N1103
1N1104
1N1·105
1N1122A
1N1169
1N1217
1N1217A
1N1218
1N1218A
1N1219
1N1219A
1N1220
1N1220A
1N1221
1N1221A
1N4005
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4004
1N4004
1N4001
1N4001
1N4002
1N4002
1N4003
1N4003
1N4003
1N4003
1N4004
1N4004
1N4004
1N4005
1N4005
1N4005
1N4006
1N4006
1N4006
1N4006
1N4002
1N4002
1N4003
1N4004
1N4004
1N4007
IN4005
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4002
1N4003
1N4003
1N4004
1N4004
1N4005
1N4005
1N4002
1N4003
1N4004
1N4004
1 N1692
1N1693
1N1694
1N1695
1N1696
1N1697
1N1701
1N1702
1N1703
1N1704
1N1705
1N1706
1N1707
1N1708
1N1709
1N1710
1N1711
1N1712
1N1730
1N1763
1N1764
1N1907
1N1908
1N1909
1N1911
1N1912
1N1913
1N1914
1N1915
1N1916
1N2069
1N2069A
1N2070
1N2070A
1N2071
1N2071A
1N2072
1N2073
1N2074
1N2075
1N2076
1N2077
1N2078
1N2079
1N2103
1N2104
1N2105
1N2106
1N2107
1N2108
1N2482
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4007
1N4004
1N4005
1N4001
1N4002
1N4003
1N4004
1N4005
1N4005
1N4006
1N4006
1N4007
1N4003
1N4003
-1N4004
1N4004
1N4005
1N4005
1N4001
1N4002
1N4003
1N4003
1N4004
1N4004
1N4004
1N4005
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4003
-fr-;J1222
1 N1223
1N1224
1N1224A
1N1225
1N1225A
1N1226
1N1226A
1N1251
1N1252
1 N125'3
1N1254
1N1255
1N1443
1N1486
JN1487
1N1488
1N1489
1N1490
1N1491
1N1492
1N1538
1N1539
1 N1540
1N1541
1N1542
1N1543
1N1544
1N1617
1N1618
1N1619
1N1620
Type
To Be
Replaced
12-16
1N2483
1N2484
1N2485
1N2486
1N2487
1N2488
1N2489
1N2609
1N2610
1N2611
1N2612
1N2613
1N2614
1 N2615
1N2616
1N2617
1N2858
1N2859
1N2860
1N2861
1N2862
1N2863
1N2864
1N2878
1N2879
1N2880
1 N2881
1N2882
1N2883
1N3189
1N3190
1N3191
1N3193
1N3194
1N3195
1N3196
1N3253
1N3254
1N3255
1N3256
1N3544
1N3545
1N3546
1N3547
1N3548
1N3549
1N3611
1N3612
1N3613
1N3614
1N3639
ITT
Replacement
1N4004
1N4005
1N4003
1N4004
1N4004
1N4005
1N40051N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4006
1N4007
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4006
1N4006
1N4007
1N4007
1N4007
1N4007
1N4003
1N4004
1N4005
1N4003
1N4004
1N4005
1N4006
1N4003
1N4004
1N4005
1N4006
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4003
1N4004
1N4005
1N4006
1N4003
Type
To Be
Replaced
1N3640
1N3641
1N3642
1N4245
1N4246
1N4247
1N4248
1N4249
1N4250
1N4251
1N4361
IN4364
1N4365
1N4366
1N4367
1N4368
1N4369
1N4383
1N4384
1N4385
2E4
3MS5
3MS10
3MS20
3MS30
3MS40
3MS50
5A2
5A4
5A5
5A6
5A8
5A10
5E4
5E5
5E6
5MA2
5MA4
5MA5
5MA6
5MA8
5MA10
5MS5
5MS10
5MS20
5MS30
5MS40
5MS50
1081
1082
1083
ITT
Replacement
1N4004
1N4005
1N4006
1N4003
1N4004
1N4005
1N4006
1N4007
1N4006
1N4007
1N4007
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4003
1N4004
1N4005
1N4004
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4003
1N4004
1N4005
1N4005
1N4006
1N4007
1N4004
1N4005
1N4006
1N4003
1N4004
1N4005
1N4005
1N4006
1N4007
1N4001
1N4002
1N4003
1N4004
1N4004
1N4005
1N4002
1N4003
1N4004
1 N4000- -SERIES,
EM500 SERIES
---.-
PLASTIC SILICON RECTIFIER
Type
To Be
Replaced
ITT
Replacement
Type
To Be
Replaced
ITT
Replacement
Type
To Be
Replaced
ITT
Replacement
Type
To Be
Replaced
ITT
Replacement
,
1084
10B5
1086
1088
10810
1002
1003
1004
1005
1006
1007
1008
10010
320A
3208
320C
3200
320F
320H
320M
320K
320P
320S
320Z
1N4005
1N4005
1N4005
1N4006
1N4007
1N4003
1N4004
1N4004
1N4005
1N4005
1N4006
1N4006
1N4007
1N4001
1N4002
1N4003
1N4003
1N4004
1N4004
1N4005
1N4005
1N4006
1N4006
1N4007
359B
3590
359F
359H
359K
359M
359P
359S
359Z
A10A
A108
A10C
A100
A10E
A10M
A10N
A10P
A13A2
A1382
A13C2
A1302
A13E2
A13F2
A13M2
1N4002
1N4003
1N4404
1N4004
1N4005
1N4005 •
1N4006
1N4006
1N4007
1N4002
1N4003
1N4004
1N4004
1N4005
1N4005
1N4006
1N4007
1N4002
1N4003
1N4004
1N4004
1N4005
1N4001
1N4005
12-17
1N4006
AH805
1N4006
AH810
AH815-- --'fN4006
1N4007
AH1005
1N4007
AH1010
1N4007
AH1015
1 N4001
AM3
1N4002
AM13
1N4003
AM23
1N4004
AM33
1N4004
AM43
1N4005
AM 53
1N4005
AM63
1N4006
G100K
1N4007
G100M
1N4004
PA3
1N4003
PA069
IN4004
PA070
IN4005
PA071
1 N4001
PA305
1N4002
PA310
1N4003
PA315
1N4003
PA320
1N4004
PA325
PA330
PA340
PA350
PA360
PA380
PT3
PT5
PT5B
PT505
PT510
PT515
PT520
PT525
PT530
PT540
PT550
PT560
S91
S91H
S92
S92H
S93
S93H
S94
IN4004
1N4004
1N4005
1N4005
1N4006
1N4004
1N4004
1N4005
1N4001
1N4002
1N4003
1N4003
1N4004
1N4004
1N4004
1N4005
IN4005
1N4002
1N4002
1N4003
1N4003
1N4004
1N4004
1N4004
ITT
-------1 N4001 THROUGH 1 N4007
GLASS RECTIFIERS
SEMICONDUCTORS
1 AMP, 50 TO 1 ,000 VOL T8
GLASS RECTIFIERS
MAXIMUM RATINGS AT 50°C AMBIENT
Max
• Hermetic seal
V. cycle
• Glassivatedepitaxial grown state of
the art chip
• Peak inverse voltage to 1000V
Peak
inverse
voltage
(volts)
Type
• Average forward current, 1 Amp
• Surge current, 30 Amp max,
• .Withstands iead pull, 18 Ibs. for 15 sec.
This series designed for power rectification in
military and industrial. These devices are ideal
for ·Appliance & Entertainment circuits, Test
Equipment, Control circuits, Computer and
Peripheral and many more. Ideal lead material
for welding.
@ 60 cps
rated load
in amps
30
1N4001
50
1.0
1.0
30
1N4002
100
200
1.0
30
1N4003
400
1.0
30
1N4004
1.0
600
30
1N4005
1N4006
800
1.0
30
1N4007
1,000
1.0
30
..
For additional ratings see figures 1, 2 and 3.
II>
W
UNITS
ABSOLUTE MAXIMUM RATINGS
Max peak forward voltage
drop @ 1A peak @ 25°C ............ 1.1V
Max peak reverse current
at rated PIV @ 25°C .............. 10p.A
Max average reverse current
at rated full load .................. 30p.A
Max peak reverse current
at rated PIV D.C. ................. 50p.A
Operating temperature
range ................. -65°C to +175°C
Storage temperature range .. -65°C to 200°C
surge
Average
forward
current
amps
._-". -
1.2
_ ...-
0:
w
0.
::;
«
z
I"
f-
0.8
~
0.6
u
~
ii:
0.4
~
0.2
zw
:>
Icc
1.0
I"
i'.
-1>..,1
'"
~
«
I"
Icc
o
25
. ,'J'65
105 -T2S"
85
145
"'"
- -'-6"5
TA IN DC
17
FIG. 1
FORWARD CHARACTERISTICS
1.6
'"
II>
0.
:> :;
«
Z w
«
0:
::;
W
0.
Z :>
0.8
Z 0:
0.6
~~
-::;;::«
~o:
0
u.
«
/
1.0
50
w
1.4
0:
f- 0:
II>
1.2
OfW Z
SURGE RATINGS CYCLES AT 60 Hz.
II
40
f-
zw
0:
0:
/
30
:>
u
I
0.4
0.2
0
0.1 0.2
... v
0.4 0.5 0.6
w
20
':>"
"«
10
0:
V
II>
"- "-
I'.
r--- I-
w
0.
U
0
0.8
1.0
1.2
1.4 1.5
2
3
4
6
10
20
30
50
VFMINSTANTANEOUS
FORWARD VOLTAGE DROP VOLTS
SURGE RATINGS CYCLES AT 60 H:l.
FIG.2
FIG.3
12-18
80 100
ITT
----1 N4383/5, 1 N4585/6, RG1122/3
i-AMP GLASS RECTIFIERS
SEMICOND.UCTORS
1-AMP SILICON
GLASS RECTIFIERS
The ITT1N4383-5, 1N4585-6, offer up to oneamp rectified current at 100°C in a small, hermetically sealed 00-29 glass package. All units
are passivated, 100 percent tested, and have
a 50-amp surge current rating to insure a stable, highly reliable rectifier. Rectifiers are supplied with solderable leads and may be delivered reel-packed for automatic insertion
equipment.
• VR Ratings 50 to 1000 Volts
• Surge Current Rating 50 Amperes
• Series JAN approved
ABSOLUTE MAXIMUM RATINGS·
Characteristics
Maximum
Maximum
Maximum
Maximum
current
recurrent peak reverse voltage ..
RMS voltage ................
DC blocking voltage ..........
average forward rectified
'/a" lead length .. 50°C Ambient
100°C Ambient
150°C Ambient
Maximum peak surge
1 Cycle
overload current
10 Cycles
100 Cycles
Maximum forward voltage drop
at 1 amp DC, 25°C .................
Maximum full cycle average reverse
current, @ rated average forward
current and 100°C ambient ..........
Maximum DC leakage at rated DC
blocking voltage and 25°C ambient ...
Typical recovery time at 2SoC ambient ...
Temperature Range, op & stg ...........
RGl122
lN4385 lN4585 lN4586'
Units
RGl123
lN4383
lN4384
50
35
50
100
70
100
200
140
200
400
280
400
600
420
600
800
560
800
1000
700
100
Volts
Volts
Volts
1.0
1.0
0.3
50
16
6
1.0
1.0
0.3
50
16
6
1.0
1.0
0.3
50
16
6
1.0
1.0
0.3
50
16
6
1.0
1.0
0.3
50
16
6
1.0
0.6
0.2
50
16
6
1.0
0.6
0.2
50
16
6
Amps
Amps
Amps
Amps
Amps
Amps
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Volts
275
250
275
250
225
200
200
"amps
10
10
10
10
10
10
10
10
10
10
10
10
ramps
",secs
°C
NOTE:
60 cps, inductive or resistive load, single phase
half wave.
12-19
10
10
-65 to +175
1N4383/5, 1 N4585/6, RG1122/3
1-AMP GLASS RECTIFIERS
TYPICAL CHARACTERISTICS
25°C unless otherwise noted
@
Maximum Average Forward Current Rating
(Resistive or Inductive Load, Single Phase,
60cps)
Maximum Average FWD Current Rating-%"
Lead Length (Capacitive Load, Single Phase,
60cps)
...
~
in
OJ
1.0
!I
~ 0.8
~~
100)'fd TO 50
~§
.,u
r'<:
..... ~
5
~
P.fd..t ~"
0.6
.....
~~.... 0.4
TYPES IN43IP. IN438 ,IN438
TYPES IN45~ IN4!l&
0
~ 0.2
;::
~
20
....
~~
40
60
80
100
120
140
AMBIENT TEMPERATURE ('C)
~
0.
"''"
0:
:0
..........
--
~ °0
160
TYPES IN438!' 1N438 ,IN431 5
TYPES IN458 IN451~
20
40
60
AMBIENT
80
100
-
in
0.
'"OJ
60
YPES IN438
TYPES 1N458
NORM. L MOU mNG
'"
0.
..........
~
.. ~
0.6
",:0
""-..
20
..........;
....... ",,:
""U
~~
r--....
10
0.4
c( ....
r----
VI
loojdd
ffi
u:
0.2
rei SOC ~f~ ~
~O"fd TO 101
..--'0.
0.
~
Q.
2
I
6
4
8 10
20
40
60
'"
SURGE DURATION CYCLES AT 60CPS
Maximum Average FWD Current Rating-l/."
Lead Length (Capacitive L.oad, Single Phase,
60cps)
OJ
1.0
08
0. II!
li!5 0.6
.......
"'u
~~ 0.4
....
~ 0.2
TO
100"
--
YPES
Yf'0
Vi
0:
3/4
~!5 0.6
~~
~3/8
112
",,,,
Non-Recurrent Surge Rating
(-65° to 17S0C)
.,
"'
:I!
L,~~~ ~-....
",0.
~
00
'"
IO.ufd TO 10 .fd
10)'fd TO 10C ~fd
"
LEA~
'"::.~ 1.0
'"z 0.8
;:
II
235710 235710
235710023
REVERSE JUNCTION POTENTIAL VOLTS
(APPLIED V-O.7 VOLTS)
5 7
1 N4383/5, 1 N4585/6, RG1122/3
1-AMP GLASS RECTIFIERS
TYPICAL CHARACTERISTICS, continued
FORWARD
VOLTAGE DROP
REVERSE
CURRENT
IA
"~ IOOMA
lOTH PERCENTILE - ,
...a:
a:
u
"
....,
"
i
IOMA
~
z
I
IMA
~
:!!
PULSE z 300,UStc
DUTY CYCLE< 2%
AMBIENT TEMP- 25°C
I
IOOjJA
10.uAO
90TH PERCENTILE
I
Q
it
r
I
0.25
0.50
0.75
100
125
RATED
INSTANTANEOUS FWD VOLTAGE DROP.VFIVOL.TS)
DC REVERSE LEAKAGE TEST
The circuit at right provides a simple and inexpensive means for checking the instantaneous leakage characteristics of the 1N4383
series and other low current rectifiers. The
pushbutton switch should not be omitted as it
minimizes junction heating when testing is
being done at high voltage, and prevents the
possibility of thermal runaway. Tests may be
conducted at high temperature by placing the
test rectifier(s) in an oven. Junction temperature rise above ambient due to internal heating
is generally low enough to be neglected.
12-21
VOLTAGE 1%)
REYERSE CURRENT TEST CIRCUIT
I
V
TI
'"
"z
aoo
•
pA MICROAMMETEII
-1000 VOI.T YOI.TNETER
-TRIAD R-107A
"4 -tOO K"
CI -IO",f-t Kv
C2 -Ij.I'-1 Kw
-IN4!S.,
-SKn-z. WATTI
0,
-100 Kl1.
02 -IN451!S
AS -10"EO.4
D -TUT RECTI"'"
ITT
_
EM500G SERIES,
1 N3611 SERIES, 1 N4245 SERIES
__________________G_L_A_ss__R_E_C~T_IF_IE_R_S
SEMICONDUCTORS
1 AMP, 50 THROUGH 1 ,000 VOLTS
GLASS RECTIFIERS
MAX RATINGS AT 100°C
• Hermetic seal
• Glassivated epitaxial grown state of the
art chip
• Peak inverse voltage to 1000V
• Average forward current ••• 1 Amp
• Surge current . • . 50 Amp max
• Withstands lead pull - 18 Ibs. for 15 sec.
Type
This series is designed 'for power rectification
in military and industrial applications at low
cost. These devices are ideal for telephone
switching applications, appliance & entertainment circuits, test equipment, control circuits,
computer and peripherals and many more.
Ideal lead material for welding.
.
Max ';'
Cycle
Surge
@60Hz
Peak Average
Inverse Forward
Voltage Current
EM050G,
50
1A
50A
EM501G,
100
1A
50A
EM502G, 1N3611,
1N4245
200
1A
50A
EM504G, 1N3612,
1N4246
400
1A
50A
EM506G, 1N361.3,
1N4247
600
1A
50A
EM508G, 1N3614,
1N4248
800
1A
50A
EM510G, 1N3957,
1N4249
1000
1A
50A
..
For additional ratings see Figures 1, 2, & 3
SURGE RATINGS CYCLES AT 60 Hz.
til
UNITS
w
a:
w
Max peak forward voltage
drop @ 1.0 Amp @ 25°C ............ 1.0V
Max peak reverse current
at rated PIV, 25°C ................ 5MA
Max peak reverse current
at rated PIV & 150°C ............. 300MA
Operating temperature
range ................ -65°C to +175°C
Storage temperature range .. -65°C to 200°C
::;
ABSOLUTE MAXIMUM RATING
"-
«
....
50
40
Z
w
a:
a:
30
\.
:J
u
w
20
CJ
"-
a:
:J
til
"w«
"-
10
I--- I-0
2
3
4
6
10
20
30
50
80 100
SURGE RATINGS CYCLES AT 60 Hz,
FIG.3
FORWARD CHARACTERISTICS
1.6
~
til
:i
«
1.2
z
« w
.... a:a:
z :J
1.0
:J
£ ....z
«
....
U
til
Z
0
a:
til
W
1.4
I
CCa:
:i'
lK
I')
J
0.8
f-
z
a:
0
0.1 0.2
o
w
f=
u
w
0.8
-5»
»
';>/<\,.:'"0<1'
l'(-5>o"'l.l'<$-
~o
0,6
I'" <$-",0",
~+J-~O
~~
J"'o
0.4
u.
,/
0.40,50.6
"-
U
/
0.2
1"-
:J
V
0.4
0,8
w
II
0.6
DERATING CURVE
'.2
1/
- «
:i;:
a:
1.0
1.2
1.41.5
V FM INSTANTANEOUS
FORWARD VOLTAGE DROP VOLTS
0.2
1""'-
a:
>
«
((
25
)) 65
85
105
T A IN °c
FIG.1
FIG.2
12-22
1 25
145
-
"-
165175
ITT
----1 N5400 THROUGH 1 N5408
SILICON RECTIFIERS
SEMICONDUCTORS
3 AMPS, 50 VOLTS TO 1000· VOLTS
SILICON RECTIFIERS
.. Diffused silicon construction
ABSOLUTE MAXIMUM RATINGS
• PIV to 1000 volts
Max peak forward voltage
drop @ 3A ...................... 1.0Volt
Max peak reverse current at rated
PIV @ 25°C ...................... 25p.A
Max peak reverse current at rated
PIV @ 50°C ..................... 250p.A
Operating temperature
range ............... , -65°C to +150°C
Storage temperature
range ................ -65°C to +150°C
• Surge current ••• 300 amps max.
• Average forward current· ••• 3A
(J
Molded epoxy construction
Rectifier is designed for
pliance and entertainment
plies and test equipment.
ged construction, 3 Amp
300 Amp surge.
motor controls, apindustry, power supDesign features rugforward current and
MAXIMUM RATINGS AT 50°C
Type
IN5400
IN5401
IN5402
IN5403
IN5404
IN5405
IN5406
IN5407
IN540B
PIV
50
100
200
300
400
500
600
800
1000
Average
Forward
Current
3A
3A
3A
3A
3A
3A
3A
3A
3A
For additional ratings see Figures 1, 2, 3, 4
12-23
Max 112
Cycle
Surge
I't
::;;;S.3ms
amp'sec
300A
300A
30DA
300A
300A
30DA
300A
300A
300A
190
190
190
190
190
190
190
190
190
UNITS
1N5400 THROUGH 1 N5408
SILICON RECTIFIERS
DERATING CURVE
w
>
wI
.~Q ,I
f".,.~"',.).'1-
50
1\
I-
~~<>
~"'01-
o
SURGE RATINGS
0
Il.
0.4
0.2
0.1 ' - - ---o 0.2 0.4
CJ
/
J
0.6
0.8
a:
V>
L.U
~
"-
100
0
0..
0
o
25
50
75
I
.06
U
c:
L.U
I
Z
"-
i,\
200
0
j
.08
I-
100
U
125
150
::J
0
I-
«
c:
w
i
I
i
.- f--f-
J
J
-.02
w
.. -
3
4
5 6 78910
300,.....:
r--,---.---,....,..--.--'--.--.---.
······1
•
L=Lead Length
To Heat Sink
200
~
I
/
i
~
-""
0.4
«
Cl.
100
7
REVERSE VOLTAGE (volts)
V>
V>
30
20
I,.
o
~
30
TYPICAL.
FO AWARD CHARACTERISTIC
POWER TEMPERATURE DERATING CURVE
z
o
i=
20
VOL TAGE (volts)
ZENER CHARACTERISTICS
0.6
-f-
-.04
I-
MAXIMUM ALLOWABLE
AMBIENT TEMPERATURES (oC)
~
~
~
I
J
::;
175
j
,
J
1I
.02
UJ
c:
"-
I
.04
UJ
0
1\
1\
rT
rT'
,
,
.1
.e:
;f
1\
11\
.~
£
II
0
0.2
10
1······1 0.6
j1zt
/
0.7
0.8
0.9
1.0
VF (volts)
i--t--="""'.t:---f---f-3000:-f---''
200
E
-- -13-6
~
Izm
-1'-- -- --
!:!
1.5
1 N4729 THROUGH 1 N4752
ZENER DIODES
IDENTIFICATION OF SYMBOLS
Iz
Zener Current
Zo
Zener impedance
lot
Zener test current
Vz
Nominal Zener voltage
Zzt
Zener impedance at test
current (lot)
10k
Zener current near breakdown knee
ZOk
Zener impedance near breakdown
knee (10k)
10m
Maximum DC Zener .current
(limited by power dissipation)
If
Forward current
Vf
Forward voltage
DYNAMIC IMPEDANCE
The Zener Impedance is derived from the 60H z
AC voltage which results when an AC current
having an RMS value equal to 10% of the DC
Zener current (lot or Izk) is superimposed on
Izt or Izk. Zener Impedance is measured at two
points to insure a sharp knee on the break
down curve and eliminates unstable units.
13-7
ITT
-----
1N5226 THROUGH 1N5257
ZEN ER DIODES
SEMICONDUCTORS
500mW, 3.3 VOLTS TO 33 VOLTS
SILICON GLASS ZENER DIODES
FEATURES
• Hermetically sealed
• Rugged construction
• Planar, nitride passivated
• Low dynamic impedance
• Weldable leads
ABSOLUTE MAXIMUM RATINGS
Max power dissipation @Tl.=75°C .... 500mW
Derating factor above 75°C ...... 4.0mW;oC
Max forward voltage @ 200 ma .... 1.1 volts
Operating and storage temperature
range .................. -65°C to 200°C
ITT's glass zeners are inherently reliable and
are ideally suited for use under stringent environmental conditions. The applications include: Computers, Instruments, Automotive, Industrial and Entertainment markets.
ELECTRICAL SPECIFICATIONS @ 25 C
Type
Number
MaxiMaximum
mum
OyRe- IR Test
namic
Reguverse ~oltage
lator
Test Imped- Current (VR)
(IR) (For A
Voltage Current ance
(Iz.,,)
25°C Suffix)
(Vz)
(Z~T)
v
made
ohms
v
p,
MaxiIR Test
Voltage
(VR)
(For B
Suffix)
v
Maximum
Regulator
Current
(b,)
ma
mum
Oynamic
Knee
Impedance
Zzk
ohms
Typical
Temperature
Coefficient
%/oC
0.95
0.95
0.95
0.95
1.9
1.0
1.0
1.0
1.0
2.0
138
126
115
106
97
1600
1700
1900
2000
1900
-.070
-.065
-.060
-.055
±.030
5
5
5
5
3
1.9
2.9
3.3
3.8
4.8
2.0
3.0
3.5
4.0
5.0
89
81
76
73
67
1600
1600
1600
1000
750
±.030
+.038
+.038
+.045
+.050
3
3
3
3
3
5.7
6.2
6.2
6.7
7.6
6.0
6.5
6.5
7.0
8.0
61
55
52
50
45
500
500
600
600
600
+.058
+.062
+.065
+.068
+.075
1N5226
1N5227
1N5228
1N5229
1N5230
3.3
3.6
3.9
4.3
4.7
20
20
20
20
20
28
24
23
22
19
25
15
10
5
5
1 N5231
1N5232
1N5233
1N5234
1N5235
5.1
5.6
6.0
6.2
6.8
20
20
20
20
20
17
11
7
7
5
1N5236
1N5237
1N5238
1N5239
1N5240
7.5
8.2
8.7
9.1
10
20
20
20
20
20
6
8
8
10
17
13-8
1 N5226 THROUGH 1 N5257
ZENER DIODES
ELECTRICAL SPECIFICATIONS @ 25 C
Type
Number
MaxiMaximum
mum
Re- III Test
Dyverse \voltage
namic
Regulator
Test Imped- Current (VII)
(11/) (For A
Voltage Current ance
25°C Suffix)
(V z)
(1zT)
(Z"T)
MaxiIII Test mum
Voltage Regulator
(VII)
(For B Current
Suffix)
(br)
ma
Maximum
Dynamic
Knee
Impedance
Zzk
ohms
Typical
Temperature
Coefficient
%;oC
v
made
ohms
I)'
v
v
1N5241
1 N5242
1N5243
1 N5244
1N5245
11
12
13
14
15
20
. 20
9.5
9.0
8.5
22
30
13
15
16
2
1
0.5
0.1
0.1
8.0
8.7
9.4
9.5
10.5
8.4
9.1
9.9
10
11
41
38
35
32
30
600
600
600
600
600
+.076
+077
+.079
+082
+.082
1N5246
1 N5247
1N5248
1N5249
1 N5250
16
17
18
19
20
7.8
7.4
7.0
6.6
6.2
17
19
21
23
25
0.1
0.1
0.1
0.1
0.1
11.4
12.4
13.3
13.3
14.3
12
13
14
14
15
28
27
25
24
23
600
600
600
600
600
+083
+084
+.085
+086
+.086
1 N5251
1N5252
1 N5253
1N5254
1 N5255
22
24
25
27
28
5.6
5.2
5.0
4.6
4.5
29
33
35
41
44
0.1
0.1
0.1
0.1
0.1
16.2
17.1
18.1
20
20
17
18
19
21
21
21
19.1
18.2
16.8
16.2
600
600
600
600
600
+087
+.088
+089
+.090
+091
1N5256
1N5257
30
33
4.2
3.8
49
58
0.1
0.1
22
24
23
25
15.1
13.8
600
700
+.091
+092
1ZK=6.25ma
Standard tolerance is ±20 %. Add suffix "A"
for ±10% tal., suffix "8" for ±5% tal.
Consult factory for other tolerances and nonstandard voltages.
13-9
1N5226 THROUGH 1N5257
ZENER DIODES
ZENER CHARACTERISTICS
TEMPERATURE RATING
~~
:g
z
o
~
1200
1000
""'I\.
800
600
~
400
a:
200
is
w
..
~
o
o
"E
--r-
200
7
<>
!u.
T YPICAL
-
FORWAR o CHARACTERISTIC
•
i\.
I
100
20
30
75 100125150175 200
10
[··'1
11,1.
I.k
MAXIMUM ALLOWABLE
AMBI ENT TEMPERATURES 10C)
.
0.6
0.7
~
0.8
0.9
1.0
VF (volts)
--- -- - .! -- --
0.5
,
REVERSE CHARACTERISTIC
POWER TEMPERATURE DERATING CURVE
e
~
REVERSE VOLTAGE (volts)
'\
25 50
{1
300 r-- .....
3.0 ~--'--"'---',...-r-'--"'-'"'T--j
1.0
a.
!
z
-- --
0
..
f:
0.1
"~ 0.05
l<
V-I CHARACTERISTICS
Q.
~
TERMS AND SYMBOLS
Switching Voltage-Closest point to peak
voltage in Region' II where slope of V-I
curve is -3301!. This definition is adopted
because of instrumentation requirements
I,
Switching Current-Current which flows
through the diode at Vs
I,
Holding Current-The closest point to the
minimum voltage in Region II where the
slope of the V-I Curve is -loon
Vh Holding Voltage-Voltage across the diode at Ih
Ip
Peak Current-Current which the diode can
pass when in Region III; duration limited
to 50 #s
Ron ON Resistance-Slope of V-I curve measured
at currents> Ih
I'k Leakage Current-Measured in Region I at
60%Vs
V,b Reverse Breaker Voltage
0.02
'" 0.01
0001
0.01
0.1
DUTY FACTOR
(, PULSE WIDTH REPETITION FREQUENCY)
V,
x
POWER DERATING CURVE
125
i
.§ 100
1\
\
z
0
~
75
iii
'"aa:
"'0
~
50
25
Q.
50
-
\
1\
'\
\
100
AMBIENT TEMPERATURE IOC)
15-2
ITT
----------
TYPE E 4E20 - 4E200
COMMERCIAL SERIES
DIODE THYRISTORS
SEMICONDUCTORS
Package: 00-7
4-LAYER DIODE THYRISTORS
• Firing Voltages 20 to 200 volts
• Switching current <125 p,A @ 25°C
• ON resistance <2Q @ 70mA
The ITT diode thyristor is a reliable negative resistance device
designed for use in switching circuits_ Typical applications include
ring counters, matrixes, pulse generators, relay drivers, multivibrators, pulse modulators, and timing circuits_
ELECTRICAL SPECIFICATIONS
TYPE
Switching
Voltage (Vs)
(Volts)
4E20-8
4E20-28
4E30-8
4E30-28
4E40-8
4E40-28
4E50-8
4E50-28
4E80-8
4E80-28
4E100-8
4E100-28
4E200 ·8
4E200-28
20±4
20±4
30±4
30±4
40±4
40±4
50±4
50±4
80±8V
80±8V
100±10
100±10
200±20V
200±20 V
Holding
Current (I,)
(rnA)
Reverse Breakdown
Voltage (Min.)
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
12
12
18
18
24
24
30
30
48
48
60
60
120
120
0.5-60
0.5-60
0.5-60
0.5-60
0.5-60
0.5·60
0.5-60_
12
18
24
30
Series A (Broad Spec)
4E20A
4E30A
4E40A
4E50A
4E80A
4E100A
4E200A
20±6
30±6
40±6
50±6
80",,8
100±10
200±20
MECHANICAL DATA
Case:
Hermetically sealed glass
Finish:
All external surfaces corrosion
resistant and leads readily
solderable
Leads:
Dumet, tin plated
Weight:
0.135 grams (approx.)
Mounting Position:
Any
Marking:
48
60
120
Cathode band
Type number
Manufacturer's Symbol
ABSOLUTE MAXIMUM RATINGS
UNITS
CHARACTERISTICS
Average Forward Current, 50·C ........................ .
Power Dissipation, 50·C .............................. .
Power-Temperature Derating .......................... .
150
150
1.5
Reverse Breakdown Voltage
from T A = -40 to +70·C ............................ .
Operating and Storage Temperature ..................... .
nominal Vs/2
-40 to +70
15-3
mA
mIJY
mWrC
min.
·C
TYPEE 4E20-4E200
ELECTRICAL CHARACTERISTICS
SYMBOL
MIN.
~ 25'C unless otherwise noted
TYP.
Is
(forward switching current)
MAX.
UNIT
125
250
/lA
/lA
-60 to +125'C
15
/lA
75% of nom. Vs
1.4
1.2
V
V
If = 70 mA~lJVs 80, 100, 200
If = 70 mA@Vs 20,30,40,50
2.0
II
If = 70 mA
I'k (OFF state)
(forward leakage current)
VON
(forward voltage drop)
roo
(dynamic forward impedance)
"-
CONDITIONS
.,,"
+200V
0.1
too
/lsec
t f""'.v
:zvoTn
'0,." TEST
+300V
5
toff
CI~CUIT
'"
~ 2V.rn..~
OVT
~onpulSE G(~~ 390 2~~lon
/lsec
VAR PULSEWIDT>t
~~~~~FA:~i:R~A:TT~~~~
Ion
'OFF TEST
CI~CUIT
j
~:~
.
., I
U
HOW THE 4-LAYER DIODE OPERATES
The voltage-current characteristic for the
4-layer diode shows three essential operating regions:
I-"off" or high resistance state
II-transition or negative resistance
state
1I1-"on" or low resistance state
This curve is shown on a very expanded
scale (non-linear). for illustration purposes only. Note that as the voltage
rises and reaches the switching voltage
(Vs), the device begins to switch "on."
The current at this point (Is) is typically
several microamperes. The device switches
because of an internal feedback mechanism allowing the diode to pass a steadily
increasing current as the voltage decreases
(negative resistance state, Region II).
When "on" (Region III), the 4-layer
diode passes a current which is limited
principally by the external circuit.
In the "on" state, the device has a
dynamic resistance of less than a few
ohms and a voltage drop of about one
volt. As long as sufficient current is passed
by the cirCUit, the device will remain in the
"on" condition. At the point on the curve
marked Ih, the clfcuit is passing just
enough current to keep the device in the
"on" condition. If the current drops below.
Ih the diode ·switches back .to the high
resistance or "off" condition.
Rate Effect
In its "off" condition the device will pass
a capacitive current in response to a
.sharply rising voltage wave. If the rise
rate of this voltage wave is large enough
(usually 10 .to 100 volts / /lS), switching
occurs below the DC switching voltage.
DERATING CURVES
+1
PULSE DERATING CURVE
~
m
NEGATIVE
RESISTANCE
REGION_ - } EXPANDED
I
IT SCALE
-V~~~~~-~-~
Vs
+v
Ela:
w
a.
'"
~
20
10
....
05
a:
a:
0.2
u
01
~
=>
V-I CHARACTERISTICS
50
"I.....
I~
50°C MAX
I
I,
"- V
0.01
01
"'" ~
5'" 0.05
a.
~ 002
:> 0.01
0.001
TERMS AND SYMBOLS
Switching Voltage-Closest point to peak
voltage in Region·1I where slope of V-I
curve is -330!!. This definition is adopted
because of instrumentation requirements
I,
Switching Current-Current which flows
through the diode at Vs
Ih
Holding Current-The closest point to the
minimum voltage in Region II where the
slope of the V-I curve is -100!!
Vh Holding Voltage-Voltage across the diode at Ih
Ip
Peak Current-Current which the diode can
pass when in Region III; duration limited
to 50 M
Roo ON Resistance-Slope of V-I curve measured
at currents> Ih
I'k Leakage Current-Measured in Region I at
75% Vs
V,b Reverse Breaker Voltage
DUTY FACTOR
(, PULSE WIDTH X REPETITION FREOUENCY)
V,
15-4
POWER DERATING CURVE
125
'i
.5
1\
100
z
;:: 75
0
it
:;j
0
50
\
-~
1\
~
a:
~
25
0
a.
50
100
AMBIENT TEMPERATURE (OC)
\
ITT
----TYPE E 4E20M - 4E200M
DIODE THYRISTORS
MILITARY SERIES
Package: 00-7
SEMICONDUCTORS
4-LAYER DIODE THYRISTORS
• Firing Voltages 20 to 200 volts
• Switching current <125 J1.A @ 25°C
• ON resistance <2Q @ 70mA
The ITT diode thyristor is a reliable negative resistance device
designed for use in switching circuits. Typical applications include
rin.g counters, matrices, pulse generators, relay drivers, multivibrators, pulse modulators, and timing circuits.
ELECTRICAL SPECIFICATIONS
Mil-Line Series for extended temperature ranges
Holding
Reverse Breakdown
Voltage (Min.)
Current (In)
-60 to 125"C (mA) 25"C
-60to 125"C
Switching Voltage (Vs)
TYPE
25"C
4E20M-S
4E20M-2S
4E30M-S
4E30M-2S
4E40M-S
4E40M-28
4E501¥11-8
4E50M-28
4E30M-8
4E30M-28
4E100M-8
4E100M-28
4E200M-8
4E200M-28
20±4
20±4
30±4
30±4
40±4
40±4
50±4
50±4
SO±g
80±8
100±10
100±1 0
200±20
200±20
14-25
14-25
23-36
23-36
32-46
32-46
41-57
41-57
68-92
618-92
SO-115
SO-115
160-230
160-230
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1 -15
14-45
1-15
14-45
1-15
14-45
10
10
15
15
20
20
25
25
40
40
50
50
100
100
MECHANICAL DATA
Case:
Hermetically sealed glass
Finish:
All external surfaces corrosion
resistant and leads readily
solderable
Leads:
Dumet, tin plated
Weight:
0.135 grams (approx.)
Mounting Position:
Any
Marking:
Cathode band
Type number
Manufacturer's Symbol
I
I
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
UNITS
Average Forward Current, 50"C ...... , ..................... .
Power Dissipation, 50"C. , ................................ .
Power- Temperature Derating ....... , ........ , .... , ........ .
150
150
1.5
Reverse Breakdown Voltage
from TA = -60 to +125°C ............................... ,
Operating and Storage Temperature ... , ............ , ... , .... .
nominal Vs/2
-60 to +125
15-5
mA
mW
mW/"C
. min.
"C
•
TYPE E4E20M· 4E200M
ELECTRICAL CHARACTERISTICS
SYMBOL
MIN.
TYP.
@ 25°C unless otherwise noted
MAX.
UNIT
125
250
",A
",A
-60 to +125°C
15
",A
75% of nom. Vs
(forward voltage drop)
1.4
1.2
V
V
if = 70 mA@Vs 80.100,200
Ii = 70 mA@Vs 20,30,40,50
ren
(dynamic forward impedance)
2.0
n
If = 70 mA
Is
(forward switching current)
i;k (OFF state)
(forward leakage current)
VON
CONDITIONS
.",.
+zoov
ton
0.1
t f"'"
OUT
",sec
CAO
__--'-"'20"'. V
tON TEST CIRCUIT ... ~
toll
5
",sec
DERATING CURVES
HOW THE 4-LAYER DIODE OPERATES
The voltage-current characteristic for the
4-layer diode shows three essential operating regions:
I-"off" or high resistance state
II-transition or negative resistance
state
III-"on" or low resistance state
This curve is shown on a very expanded
scale (non-linear) for illustration purposes only.' Note that as the voltage
rises and reaches the switching voltage
(Vs), the device begins to switch "on."
The current at this point (Is) is typically
several microamperes. The device switches
because of an internal feedback mechanism allowing the diode to pass a steadily
increasing current as the voltage decreases
(negative resistance state, Region II).
When "on" (Region III), the 4-layer
diode passes a current which is limited
principally by the external circuit.
In the "on" state, the device has a
dynamic resistance of less than a few
ohms and a voltage drop of about one
volt. As long as sufficient current is passed
by the circuit, the device will remain in the
"on" condition. At the point on the curve
marked Ih, the Circuit is passing just
enough current to keep the device in the
"on" ·condition. If the current drops below
Ih the diode switches back to the high
resistance or "off" condition.
Rate Effect
In its "off" condition the device will pass
a capacitive current in response to a
sharply rising voltage wave. If the rise
rate of this voltage wave is large enough
(usually 10 to 100 volts / ",S), switching
occurs below the DC switching voltage.
PULSE DERATING CURVE
+I
...........
m
NEGATIVE
RESISTANCE
REGION__ } EXPANDED
n SCALE
-V ..=-;'i;;::=....p==-~~ +V
Vs
iii
"'
,."'
II:
0-
~
I-
5.0
2.0
"'" "'
.........
1.0
105°CMAX
II:
II:
0.2
u
0.1
50°C MAX
./
A.
0.5
z
"'::>
~
"'
I'--.
V,
I,
Ih
Vh
Ip
Ron
';k
Vrb
TERMS AND SYMBdLS
Switching Voltage-Closest point to Pl
voltage in Region II where slope of \
curve is -330P.. This definition is adopt&
because of instrumentation requirements
Switching'Current-Current which flows
through the diode at Vs
Holding Current-The closest point to the
minimum voltage in Region II where the
slope of the V·I curve is -1000
HoldingVoltage-Voltage across the diode at Ih
Peak Current-Current which the diode can
pass when in Region III; duration limited
to 50 #s
ON Resistance-Slope of V-I curve measured
at currents> Ih
Leakage Current-Measured in Region I at
75% Vs
Reverse Breaker Voltage
."'
0-
x 0.02
,. 0.01
0.001
""
""
'"
.. 0.05
V·I CHARACTERISTICS
0.01
0.1
DUTY FACTOR
(= PULSE WIDTH X REPETITION FREQUENCY)
POWER DERATING CURVE
125
\
i
.§ 100
z
0
1=
~
75
iii
0 50
'"
\
\
1\
\
II:
"'0
~
25
0-
50
10.0
AMBIENT TEMPERATURE (OC)
15-6
\
ITT
__ .
FOUR-LAVER DIODE
_____________________
**_A_PP_L_IC_A_T_IO
__
N_N_O_T_E_S
SEMICONDUCTORS
TWENTY-FOUR CIRCUIT APPLICATIONS FOR ITT 4-LAYER DIODES
THEORY OF OPERATION
Figure 2B
The ITT Semiconductor Four-Layer Diode is a
two-terminal semiconductor switch, sometimes
referred to as a negative-resistance diode.
These PNPN silicon devices are useful in many
applications including pulse generators, oscillators, telephone switching, sweep generators,
and multivibrators.
IC2
The diode has two stable states; the ON or
low impedance state, and the OFF or high impedance state. To turn the device ON, voltage
across the terminals must exceed the switching
voltage (V,). The device can be turned OFF by
reducing the current through the device below
the holding current ((h).
----I
I
I
I
I
Vs
II
I/32
The diode will remain in this condition until
either the temperature or the anode voltage is
increased to a point where B1 B2 = 1. At this
point, the middle junction breaks down and
the circuit becomes regenerative. This occurs
because the collector of each transistor supplies current to the base of the complimentary
transistor in the equivalent circuit and their
Betas are current dependent. As sOOn as they
reach unity the device effectively "runs away"
or "fires" and the current through the circuit is
limited only by external impedance.
Figure 1 is the V-I characteristic of a typical
device. V, is the point at which the device
breaks down and switches to the ON state
where current is limited only by the external
circuit impedance.
Ih is the minimum current that must be passed
through the diode to keep it in the ON state.
If the current drops below this value the diode
will switch to the 0 FF state.
Vac
Figure 3
Figure 2A
ANODE
p
p
N
N
N
p
p
p
N
ICI
The PNPN diode can be thought of as a
complimentary pair of transistors, one a PNP
and the other an NPN as shown in Figure 2A.
Figure 2B shows the two transistors as they
would appear schematically. The collector of
T2 drives the bose of T1 giving rise to a positive
feedback loop with a gain of B1 B2. As long as
B1 B2 is less than 1 the equivalent circuit is
stable with the upper and lower PN junctions
biased forward' and the middle junction reversed biased. In this condition only a small
leakage current flows.
I
Vh
t
~
:m
Is
TI.
I L,
Figure 1
Ih
~I
t
N
CATHODE
**Application notes will be found in the last pages of this section.
15-7
APPLICATION NOTES FOUR-LAYER DIODE
CIRCUITS
Triggered Pulse Generators
These circuits are used mainly for generating
ar amplifying pulses and for triggering purposes. They are similar to Figure 3 except that
the switching voltage of the diode is greater
than the supply voltage. Four variations, with
their input and output pulses, are shown in
Figure 4. A pulse, large enough to break dawn
the diode, is capacitively coupled either positive to the anod e or negative to the cathod e.
The conventional diode is used to present a
high impedance to the input pulse.
Relaxation Oscillator
Figure 3 illustrates a circuit used far oscillator, sweep generator, and timing applications.
The output is a saw-tooth voltage the amplitude
of which is dependent On the diode Ys• Frequency is dependent upon the RlC time constant and the supply voltage. The supply voltage
should be chosen so that the charging of C is
done in the linear portion of the curve. When C
reaches Ys the diode breaks down and conducts. C rapidly discharges through the diode.
Rl should be large enough so that it will not
pass Ih or the diode will remain in the ON can·
dition after C has discharged. With C discharged the diode turns OFF and C commences
to charge again. Rl must be able to pass the
switching current (Is) when C reaches Y, and
the diode flres again.
Jl
o--j~,0:1,0C
Voc
. ..'_
'~lf
Voc
Figure 5
L·C Pulse Generators
As with the circuits in foregoing section,
those in this section also require a pulse to flre
the diode. Y, of the diode is greater than the
supply voltage. In Figure 5, a negative pulse
is applied to the cathode which breaks down
the diode. C, which was charged to YoC
through R, discharges through the diode, L,
and Rl. This is a resonant circuit and the wave
shape across Rl is a half sinusoid. When the
current goes through zero, the voltage across
the diad e becomes negative, turning it 0 FF.
A smail positive output will occur due to the
pulse recovery current through the diad e.
J\
c
R'I
c
v
0---1
R2
Figure 6
L2
1J
0---1 H----1'---o
c
1[0---1
v
15-8
APPLICATION NOTES
FOUR-LAVER DIODE
the cathode, the four-layer diode (Ol) conducts.
RL is made large enough so that it will not
deliver the minimum Ih. C discharges through
the four-layer diode (Ol) the conventional
diode (02), and the inductive load_ C must be
large enough to supply the "read" peak current. The shape of the curve is dependent on
the inductances and R,_ The RLC product must
be selected so that C charges in less time than
the time from the end of the "read" pulse to
the beginning of the next complete cycle.
JL
Voe
Figure 7
lJ
This type of generator does not depend On
R being large enough not to pass Ih but rather
On the fact that ringing of the L-C loop turns
OFF the diode. Ouring the OFF half cycle C
charges to Voe but in the opposite polarity.
With the completion of the output pulse and
the cessation of ringing, C begins to recharge
toward the power supply voltage and polarity.
Figures 6 and 7 illustrate the same principle
but with a resonant charging circuit. C moy
charge to approximately twice the supply
voltage if the circuit Q is high. The resistance
of L must be. large enough to keep the current
through the four-layer diode below its rated
maximum. The anode af the diode must be kept
negative long enough to turn completely OFF,
otherwise the diode will turn back ON when
the anode goes positive. This requirement
limits the maximum operating repetition rate.
OFF
0---1
02
Figure 9
Relay Drivers
In Figure 9, V, is greater than Voe. A negative pulse on the cathode turns 0, ON_ It remains in this state until it is pulsed OFF by a
negative pulse on the anod e. This'is a typical
relay driver application. 02 prevents excessive
spiking caused by the relay inductance.
Voe
1f
e
Figure 10
Figure 8
circuit is to provide a current wave form which
Stroboscope
In Figure 10, the four-layer diodes replace
thyratrons as triggers to activate a stroboscope
flash tube. The diodes form a relaxation oscil-
reads the memory and then restores (writes)
the initial flux condition. In Figure 8, the V, of
the four-layer diode is greater than Voe. C
charges to Voe through RL When a negative
pulse of the proper magnitude is coupled to
lator delivering pulses up to 150V at a few
hundred per second depending on the circuit
constants. Because of the pulse magnitude two
diodes are used in series with equalizing resistors across them.
Magnetic Memory Driver Circuits
The purpose of a magnetic memory driving
15-9
APPLICATION NOTES
FOUR-LAYER DIODE
Voc
Figure 13
RI
R2
C2
~----If----+B
o-jf-+-......-+!...j!-------.
1J
02
01
Figure 11
B
A-Stable Circuit
YOC is greater than Y. of both diodes in
Figure 11. When power is applied, one of the
diodes will conduct. Let it be assumed that DI
flres flnt. Point A will go approximately to
ground potential and the current through RI
will be greater than Ih. The capacitor C will
begin to charge through R2 and DI to ground.
When the voltage at B exceeds the breakdown
potential of D2, it will conduct and point B will
go to ground. Since the capacitor can not
charge instantly, point A will drop approximately Y. volts. This puts a negative voltage
at A, which if kept there until the turn OFF
potential of DI is reached, will prevent it from
sWitching back until the voltage at A reaches
Y._ C therefore charges through RI. The circuit
oscillates back and forth from DI to D2 with the
frequency dependent On RI C and R2C and on
YOC and the switching voltage of the diodes.
A modiflcotion of the gate circuit where both'
diodes are in the OFF state until a pulse is
opplied is shown in Figure 13. The Y. of DI is
slightly higher than YoC. A pulse of currenl is
opplied through RL which turns Dl ON. C2
charges through Dl ond R2 to Yoc- Cl charges
through Rl and Dl toward YoC olso_ When the
voltage at point A reaches Y. of D2, it will commence to conduct. The voltage rise. at' B is
commutated back to DI, turning it OFF, which in
turn, turns OFF D2.
voc
02
01
RI
(-0
1f
1f
Figur'e 14
Figure 12
BI-Stable Multivlbrator Flip-Flop
The Y. of both diodes are chosen 50 that
they are greater than YOC in Figure 14. Whichever diode is ON, it remains in that condition
until a trigger pulse arrives turning OFF the
diode which was ON and turning ON the previously OFF diode by the commutating action
of C.
By interchanging one 4-layer diode with
its series cathode diode,-the circuit will become
sensitive to the polarity of the pulses. The
circuit will then switchover only when·. the
polarity of the trigger pulse reverses. This is
shown in Figure 15. Diode 1 triggers On negative·pulses only and diode 2 on positive pulses.
Th.erefore, a positive pulse keeps branch B ON
and a negative pulse keeps branch A ON.
Monostable Multivibrator
If diode Dl in Figure 12 is selected so that
it. switching voltage is less than Yoc, and diode
D2's is greater than YOC, diode Dl will normally
be in the ON condition and D2 will be OFF.
Capacitor Cwill charge through R2_ When D2 is
pulsed ON, DI will turn OFF due to the commutating action of C. The voltage at point A
will then start rising as C charges through Rl
and D2_ When the voltage at point A reaches
the switchover voltage of Dl it will turn ON ond
D2will turn OFF until another p.ulse is received.
Frequency is determined by Rl C, YoC, and Y.·of
diode Dl.
15-10
APPLICATION NOTES
FOUR-LAYtErFi2 DOODlE
Ring Counters
Figure 15
Figure 16
T
The basic requirement of a ring counter is
to turn one stag e at a time ON in a simple
progression. Each time a trigger pulse is applied, the ON stage will advance one stage.
The circuit forms a closed loop, or ring, so that
when the final stage has been activated the
next pulse will move the ON condition back to
the first stage where the cycle begins over
again. In Figure 17, one stage will turn ON as
soon as power is applied. The commutating
capacitor C between the ON stage and the
next successive stage charges through RL and
the ON 4-layer diode to VA, which is less than
the Vs of the diodes and keeps them from turning ON. A trigger pulse, either positive or
negative, causes VB to drop almost to ground
potential, which in turn, causes VA to drop at
the same time due to the coupling action of Cl.
Since Rl is large enough so that a current of
less than Ih flows through the trigger diodes, the
pulse is only momentary. The drop in voltage
at A turns OFF the ON diode. At the same
time Cl begins to charge and the voltage at A
rises again.
The voltage at the high end of the charged
commutating capacitor C adds to VA causing
the next stage to fire. The repetition rate of the
output pulses equals the rate of the trigger
pulses divided by the number of stages.
VI
T
A different steering circuit is shown in Figure
16. Assume thot Dl is ON. Point A will be ap·
proximately at ground potential and paint B
at VI. When a negative pulse is applied it is
blocked by CRI but passes through CR2, causing
swilchaver to take place. Current from V2
passes through Rand D2 to ground. The principal
source of current for the conducting branch
is V2. The RL'S are need"ed to maintain a voltage
of less than V. across the OFF diode.
Figure 18
Voc
Figure 17
Telephone Switching
When trigger signals of the polarity shown
in Figure 18 are simultaneously applied to the
lines, one of positive polarity to lines I, 2, or 3,
and the other of negative polarity to lines
4, 5, or 6, two of the lines will be connected.
If triggers are applied to lines 2 and 5 as
shown, the 4-layer diode A will conduct connecting them together. The series resistors
allow a current greater than Ih to flow, thus
keeping the diode in the ON state. To open the
circuit, a contact is opened to interrupt the
flow of current through the diode which will
then revert to its 0 FF condition.
Jl
o-j
1J
15-11
APPLICATION NOTES
FOUR-LAYER DIODE
A
Figure 21
REGULAR
POWER
SUPPLY
EMERGENCY
POWER
SUPPLY
Figure 19
Emergency Power Transfer
In the normal state, the 4-loyer diode in
Figure 19 is OFF and the regular power supply
is the source of power for the load RL. If the
supply voltage should fall off for any reason,
the voltage at point A will drop. If this change
in voltage is sufficient to cause the potential
from 8 to A to exceed the diad .. V" it will turn
ON and the emergency power supply will
provide power to the load until the condition
is corrected.
In Figure 21, succeeding half cycles can
have different firing angles since there are two
control diodes, One for each leg of the rectifier
circuit.
A.C.
C'
1J
Figure 20
Rectifier Control Circuits
Figure 20 illustrates a method for controlling
the power output of a rectifier by varying the
point at which a 4-layer diode is triggered.
Pulses may be applied at any phase angle
from the start of the input waveform (100%
power! to 180° (zero power!.
AC Control Circuits
The circuit in Figure 22 is useful for the control of AC power in such applications as light
dimmers and motor controls. The trigger portion is composed of two back-to-back relaxation oscillators with an adjustable resistor COntrolling the time at which they fore the control
diodes and thus the amount of current through
the load.
The load resistor of the oscillator and C set
up the time constant to fore the trigger diodes
at approximately 90° in each half cycle. When
a positive input cycle occurs the diode A will
break down at approximately 90°. The charged
capacitor C will discharg e through diad e A
with the result that a negative pulse will appear
at point CI.
This pulse will turn ON control diad e AI which
will allow current to flow until the half cycle is
completed. 80th diodes will then turn OFF
since the current through them will drop below
their holding current. This cycle is repeated
during the negative portion of the input waveform.
15-12
APPLICATION NOTES
FOUR-LAVER DIODE
+v
Figure 23
Figure 24
Invarter Circuits
The circuit in Figure 24 is a typical power
inverter used to convert DC power to AC power
over a range of frequency from 60 to a few
thousand cycles. When power is applied, one
of the 4-layer diodes begins to conduct. Assume this to be 01. The battery supplies current
through the coil L, primary t and 01. The reflected load limits the current through 01.
When a negative trigger pulse is applied 02
will conduct. The commutating capaciior C
which is reflected into the primary from across
RL will cause point A to go negative thus turning OFF 01. L smooths the current during
switching. The following negative trigger pulse
turns 01 ON again and C turns 02 OFF. This
completes one cycle.
The switchover voltage of the diodes must
be greater than 2XVoC and capacitor C must
be big enough so thot when reflected back into
the primary it can turn 0 FF the diode which
was ON just prior to the triggering pulse. The
capacitor can be across the primary or the
secondary.
SCR Phasing Circuit
Diode t and 2 are both designed into relaxation oscillator circuits in Figure 23. The diode t
circuit has a frequency of just under 60 cycles
per second. The half-wave supply circuit ot its
anode causes the frequency of the oscillator
to be synchronized with the line frequency. The
output at VA is a sawtooth which is coupled to
the cathode of 02. It is sup erimposed on a DC
value set by the potentiometer in the cathod e
of 02. As the voltage across 02 is increased by
decreasing the cathode potential, the negative
peak of the waveform from 01-will exceed V,
of 02 putting it into oscillation at a frequency
much greater than that of 01. This signal is fed
to the gate of the SCR which is flred by the
steep wave front at the start of oscillations.
The timing of the conduction of the SCR is
controlled by the setting of the potentiometer.
•
I
15-13
APPLICATION NOTES FOUR-LAVER DIODE
THYRISTOR DIODES
+-r
.020 '.002
t~=t:::I:::E
,0~4-tl.o".,
11
SEE NOTE
r--
.2S!I t.035
.•• L
~
.096*.011
.020 *.002
TE...... L
~
I
~~w
-
.iSOIA .
I '--1
~.51DIA.
.n_
L -U·025 OIl..
1.2.
NOTE;
WITHIN THIS ZONE. DIAMETER
NAY VARY TO ALLOW FOR LEAD
FINISHES AND IRREGULARITIES.
TOP HAT
00-7
00-7 PACKAGE
Reverse
TYPE
lN3831
1N3832
1N3833
1N3834
1N3835
1N3836
1N3837
1N3838
Switching Voltage (Vs)
(Volts)
Halding Current Ub)
25"C -40 to B5"C
14-25
20 ± 4
25 ± 4
19-30
30 ± 4
23-36
35 ± 4
28-41
40 ± 4
32-46
37-51
45 ± 4
50 ± 4
41-57
100 + 10 80-115
25"C
0.5-15
0.5-15
0.5-15
0.5-15
0.5-15
0.5-15
0.5-15
0.5-15
Switching Voltage (VsJ
(Volts)
Holding Current (Ib)
(Milliamps)
(Milliamps)
-40"C
40 max
40 max
40 max
40 max
40 max
40 max
40 max
40 max
Breakdown
25"C
12v min
15v min
18v min
21v min
24v min
27v min
30v min
60v min
Reverse
TYPE
25°C -40 to 58°C
1N3839
1N3840
1N3841
1N3842
1N3843
1N3844
1N3845
1N3846
20 ± 4
25 ± 4
30 ± 4
35 ± 4
40 ± 4
45 ± 4
50 ± 4
100 ± 10
14-25
19-30
23-36
24-81
32-46
37-51
41-57
80-115
25"C
14-50
14-50
14-50
14-50
14-50
14-50
14-50
14-50
B5"C
5 min
5 min
5 min
5 min
5 min
5 min
5 min
5 min
Capaci-
4E20M-8
4E20M-28
4E30M-8
4E30M-28
4E40M-8
4E40M-Z8
4E50M-8
4E50M-28
4El00M-8
4El00M-Z8
4E200M-8
4E200M-28
Capacitance
down
(Typical)
OV Bias
80
70
60
50
45
45
40
30
pI
pI
pI
pI
pI
pI
pI
pI
Switching Voltage (Ve)
TYPE
80 pI
70 pI
60 pI
50 pI
45 pI
45 pI
40 pI
30 pI
Break-
25"C
12v min
15v min
18v min
21v min
24v min
Z7v min
30v min
60v min
Mil-Line Series for extended temperature ranges
tance
(Typical)
OV Bias
25"C
-60 to l2S"C
ZO ± 4
20 ± 4
30 ± 4
30 ± 4
40 ± 4
40 ± 4
50 ± 4
50 ± 4
100 ± 10
100 ± 10
200 ± ZO
ZOO + 20
14-Z5
14-25
23-36
Z3-36
32-46
32-46
41-57
41-57
80-115
80-115
160-Z30
160-Z30
Holding
Current (Ih)
(rnA)
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
Series A (Broad Spec)
Switching
Voltaga (Ve)
(Volts)
TYPE
20 ± 6
30 ± 6
40± 6
50 + 6
4E20A
4E30A
4E40A
4E50A
Holding
Currant (Ib}
(rnA)
0.5-60
0.5-60
0_5-60
0.5-60
Commercial Series
(Volts)
Holding
Current (Ib)
(rnA)
20 ± 4
ZO ± 4
30 ± 4
30 ± 4
40 ± 4
40 ± 4
50;!: 4
50 ± 4
100 ± 10
100 ± 10
ZOO ± 20
200 + 20
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-45
1-15
14-15
Switching
TYPE
mO-8
4EZO-28
4E30-8
4E30-28
4E40-8
4E40-28
4E50-8
4E50-28
4El00-8
4El00-28
4EZOO-8
4E200-Z8
Voltage (Vs)
TOP-HAT PACKAGE-TYPE J
TYPE
4J50-5
4J50-25
4J100-5
4Jl00-Z5
4J200-5
4JZOO-25
Switching
Voltag. (V,}
(Volts}
Holding
Currant IIh)
50 ± 5
50 ± 5
100 ± 10
100 ± 10
ZOO ± 20
200 ± 20
1-10
9-45
1-10
9-45
1-10
9-45
(rnA)
Current Carrying Capacity: 300 rnA steady dc.
Maximum peak current rating 20 amperes - dependent on duty lactor.
repetition rale, pulse duralion, ,!'mbient temperature.
15-14
TYPE TAG
Plastic Encapsulated Tantalum Capacitors
TAG PLASTIC ENCAPSULATED
TANTALUM CAPACITORS
o ::.pR"';'."
rf:= Tq
• Extremely low leakage current
• Small size -
high component density
• Reliability -
long term stability
L
CASE SIZE
1-7; 0.72 ±0.20
~ ~g
• Outstanding performance over wide
frequency range
J
• Wide temperature range
CASE SIZE
1-70.016 DIA
8-150.020 DIA
The extremely stable oxide' layer of TAG capacitors allows only a very small leakage current
even after long storage. The solid electrolyte
guarantees very stable electrical performance
over wide temperature ranges and long time
periods.
TAG capacitors are finished in red epoxy and
can be mounted in any position. Rugged construction allows installation in moderate environments experiencing moderate shock and
vibration.
RATINGS
Capacitance ................. 0.1 to 680p.F
Tolerance Range ...... +50 - 20 %, (±20 %)
Voltage ...................... 3 to 50 volts
Temperature Range .... Continuous operation
between -55°C to +85°C
Leakage Current .......... CXVXO.05 (p.A)
or 2p.A, whichever is greater
Dissipation Factor at 120 Hz and 25°C
up to 100 p.F ............. less than 10%
over 150p.F ............... less than 12 %
Impedance ........ Nominally less than other
electrolytic types, see table
For further requirements see ITT data sheet on
TAP CAPACITORS featuring the following ratings:
Tolerance Range .......... ±20% (±10%,
±5%)
Leakage Current .......... CXVXO.02 (p.A;
or 1 p.A, whichever is greater
Dissipation Factor at 120 Hz and 25°C
up to 100 p.F .............. less than 6 %
over 100 p.F . . . . . . . . . . . . . . .. less than 8 %
UPPER EDGE OF
PRINTED CIRCUIT
. BOARD
TABLE-OUTLINE DIMENSIONS
Case Size
Diameter D
3
4
5
6
7
8
9
10
11
12
13
14
15
0.16
0.18
0.20
0.20
0.22
0.24
0.26
0.33
0.37
0.37
0.39
0.41
0.41
0.43
. 0.43
(maximum in inches)
Length L
0.28
0.28
0.31
0.33
0.35
0.37
0.39
0.45
0.53
0.55
0.55
0.59
0.63
0.65
0.67 .
-Applies to capacitors w/l,,·p",lght.leads only. For TAGIS see drawing.
16- I
Lead Space R"
0.11
0.11
0.12
0.12
0.12
0.12
0.14
0.22
0.22
0.22
0.22
0.24
0.24
0.24
0.24
TYPE TAG
.Plastiq Encapsulated Tantalum Capacitors
TABLE -
..
u
c
to
..
....
STANDARD RATINGS
.!!
-==1.&.
...:il "-
to
(.)
6.3 Volts
3Volls
III
to
(.)
Ii.
Ii.
.5 .5
.cto
E
0
z
II
.!!
.
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CD
(.)
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0.1
0.15
0.22
0.33
0.47
0.68
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16Volls
10Volls
Ii.
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Ii.
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II
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to
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to
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==
N
Ci)
(.)
==
Ii.
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E
0
z
r.o
1.5
2.2
3.3
4.7
6.8
10.0
15.0
22.0
33.0
47.0
68.0
100.0
150.0
220.0
330.0
470.0
680.0
1
1
2
3
4
5
6
7"
8
9
11
13
14
5.5
4.5
2
1.8
1.2
0.9
0.7
0.5
0.5
0.4
0.4
0.3
0.3
17
15.5
8.5
7.5
7
4.2
3.5
3
1.8
1.1
0.9
0.8
0.7
1
2
3
4
5
6
7
8
9
11
12
14
5.6
4
3
2
1.5
0.8
0.6
0.5
0.5
0.4
0.4
0.3
1 8
19
2 5
10.5 3
4
9.5 4
3
8.5 5 1.8
6
1
5
3.5 7 0.8
8 0.6
3
2.2 9 0.5
1:7 11 0.4
1.1 13 0.4
0.9 14 0.3
0.7
22
12
10.5
9.5
5.5
3.5
3.5
2.4
1.8
1.2
0.9
0.7
1
2
3
4
5
6
7
10 25
6.5 14.5
5
12
3.5 7.5
2.5 6.5
1.5 4
1
3.5
10
11
13
15
0.6
0.5
0.4
0.3
7
8
9
1.9 11
1.3 12
1 .14
0.8
1.5
1
0.8
0.7
0.6
0.5
"Case slleS In bold type are factory stocked Items. Sample quantities are availabla In most case
CATALOG ORDERING INFORMATION
JJ
(1)T:::I:mN
F[J20
4.7/35-50
Performed Leads
Ii.
...
N
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..
N
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II
to
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(.)
==
==
112
2 9
3 6.5
4 4.5
E 3
6 2
4
8 1.7
3
9 1.2
2.2 10 0.8
1.5 12 0.7
1.2 13 0.6
0.9
25
17
14.5
10
6
6.0
3.5
2.5
2.0
1.4
1.1
35 Volls
Ii.
.5
E
0
z
1 165
1 110
1 75
1 51
1 37
1 27
1 18
2 13
3 90
4
6
5
4
6
3
7
2.5
9
1.2
11
1
12
0.8
14
0.6
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Ii.
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310
50Volls
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~
1
200
1
150
1
105
2
68
2
53
3
34
4
.25
5
17
6
12
7
8
8
6
9
5.5 11
3
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170
105
80
50
32
25
16
13
8
6.2
3.5
2.2
1.8
310
180
130
85
60
45
32
23
15
11
7
4.5
3.5
==
SlZ88,
Environment & Mechanical Properties
HUMIDITY-Capacitors are tested after exposure to a maximum humidity of 95 % at
40·C for 21 days with no voltage applied.
LEAD STRENGTH-Leads are capable of withstanding a pull of 1 po.und for 10 seconds and
can tolerate two 90 degree bends without
failure.
Lead Spacing .2 In.
Capacitance 4.7 p.F
35 Volts - - ' - - - - - - - - '
Tolerance +5 -20% - - - - - - - '
(2) Optional Features on Special Order
A. Preformed 0.25" leads, model number codeu 25." Flexible leads, mod~
el number code "00."
B. Capacitance tolerance of ±20 %.
C. Numerical Stamping.
(3) Minimum Packaging Quantity units.
25 Volts
20 Volts
..
....
100
MOUNTING & SOLDERING-TAG tapacitors
can be dip~soldered with a maximum bath
temperature of 270·C. Acid flux is not suitable
and can damage the units. Soldering time
sho.':Ild no~ exceed 3 seconds and the cases
of tne- -units should not be dipped to closer
than Va" of the bath surface.
When bending leads, no stress should be applied to the case. Avoid mounting adjacent
to heat radiating components.
16-2
TYPE TAG
Plastic Encapsulated Tantalum Capacitors
Definitions and Ratings
Protective Circuit Resistance
Value measured at
The failure rate of TAG capacitors will be
A = 4,2 X 16 -u h -1 at 3 Ohm/voltage circuit
resistance 85°C and rated voltage
CAPACITANCE TOLERANCE Variation of
actual value from nominal rated value in per
cent (%).
Any lower resistance will increase the failure
rate.
RATED CAPACITANCE 60 cycles and +25°C.
RATED DC VOLTAGE - Listed rating in volts
DC at a surface temperature of +40°C.
CONTINUOUS MAXIMUM VOLTAGE-Highest
DC voltage which can be applied to capacitor.
Max voltage equals rated voltage up to +85°C
ambient temperature.
SURGE VOLTAGE-Maximum voltage to which
capaCitor may be subjected 5 times per hour
for one minute. Maximum value is 1.15 times
the rated voltage. Capacitors should not be
used in electrical circuits where the capacitor
is regularly charged and discharged to the
peak of the surge voltage.
REVERSE VOLTAGE-Not to exceed 0.5 Reverse voltage higher than this limit can be
handled by connecting 2 capacitors in antiseries (bipolar capacitor); Resulting capacitors
will be of same voltage, but half capacity of
single unit.
AC RIPPLE VOLTAGE-Sum of superimposed
peak AC voltage and DC voltage must not exceed rated voltage. See figures 3, 6 and 9.
LEAKAGE CURRENT· Current measured
throug h a 1,000n resistor with rated voltage
applied for 3 minutes at +25°C. This current
does not exceed 0.05 times capacitance (p.F)
times rated voltage (volts), or 2 p.A, whichever
is greater. At +85°C, typical leakage current
is less than 10 times the value at +25°C. See
figure 4.
IMPEDANCE-Measured at 10KHz and 25°C.
See figure 8.
This can be compensated by voltage derating.
See figures 12, 13, and 14.
Operational Reliability
The reliability is measured by the reject rate,
=
FR
m
nXh
=
where m
number of rejects. n X h = components X hours.
The reject rate increases with applied voltage
VB and ambient temperature
and falls with
increased circuit resistance R•. As a result of
comprehensive life-tests the reject rate has
and Rs.
been determined as a function of VB,
The reject rate for catastrophic failures for
the particular case can be determined from
Fig. 12 to 14 as follows:
1. Determine the reject rate of FR" as a function of the applied voltage from Fig. 12 with
= +85°C and Rs = 3nN.
2. Multiply FR" with the corresponding factor
from Fig. 13 for the actual ambient temperature to obtain the reject rate FR'.
3. Determine the final reject rate FR as a
function of the circuit resistance by multiplying
FR' with the corresponding correction factor
obtained from Fig. 13 (ambient temperature as
parameter).
EXAMPLE: Determination of F for
VB = SOOA,
llU
= 125'C
RS = InN
FR" = 2.8 • 10- 7 • h- I
FA
Variation of tanll with temperature is shown
in figure 10.
16 -3
(from Fig. 12)
h- I
(from Fig. 13)
Fe" = 2.8.10- 7 .9.2.8. h- '
FR
DISSIPATION FACTOR-(tangent of loss angle:,
tanll) defined by tanll =2".fRC, is measured at
a frequency of 120 Hz, at room temperature;
25°C.
= 2.8·
10- 7 .9.
.= 7.06 x
10- 6 h- 1
(from Fig. 14)
TYPE TAG
Plastic Encapsulated Tantalum Capacitors
.I
+10
CASE
SIZE
15
~
I
ASE
IZE
~
"''"
1111
11I1
11I1
.......,
i
~ +5
::i
il
CASE
"- i'SifE
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9.
~
~
'\
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.,.
I
~
I
0
Z
;!
>
~
U
"<1
~
100
IT
~
-.
-SS-40 -20
0
+20 +40 +60
+ 80 roo
CASE
SIZE
5
90
85
10"
--
/
V
3
/
/
10'
I
0.8
I
I
"
I
"''"
!}
~
0
>
1
~
0 .8
'r ,
0.'
IDI z
1
~!!-
0.2
,
, V-
I
0.1
10·'
-SS-40 -20
0
+20 +40 +60
+100
TEMPERATURE - CENTIGRADE - - -
Figure 4
o.oe
I.,
>~
V
V
1
Figure 3
•
I-t-::
,
,
'10'
Figure 2
,
~;
, , ,
10'
FREQUENCY- KHz
Figure 1
10'
,
, ,
TEMPERATURE _·C - -
0
"'~
V
~
!
04
OB
vl2
OPERATIONAL YOL.TAGE ~
-
10
I
,
,
10'
III
CASE
SIZE
6-10
I-
. j-j:!
,
,
'OV
~
i
10'
10V
10·'2
,3
~'IOO 2
I
"''"
~
~
>
"'
il:
~
-ir1.
,==
, ..
,-
~
rei
~ 7
3
_.
-
10'
',
-Ff
_.
-,
<,"V
)
2. V
~I 20V
"' '~
~
10
,
,
"'~" ,
,
c-- -
CASE
SIZE
11-15
10;~ ~
c
.,"'
10V
--- .j...
10V
I
10"'
10"
16-4
2
Figure 6
;1
Figure 8
~ 7
3
l\
10'
FREQUENCY' - KHz
>~
Figure 7
~
IO~ IIII~~~
10,==
FREOUENCY- t
/
1m
~SIZE
•• ~ I
~ Iii
20
,
f-
II
Figure 11
·,
10',:
1,[
11'1
FREQUEHCY- KHI -
Figure 10
10- 4
~
II,
IIIIIL J-
~
TEMPERATURE--C
I.
,
ill:'
....
i
-!S~·40
I
,i
!
0
'"
I--'
1,Ii
~ I I!
I i 'I
0.03
~ 0.04
SIZE
I
I
c.oe
I
CASE
,
1i:!\
i
I
.
o
i
,
,
,
0.01
,
SIZE
I
I
1 0.06
'"I
.J..-
CAS£
1111'
, II
0.07
SIZE
I--'
....
~ 0.03
0.08
V C1SEI
I
-
1
2
.
~·3.n/V
6•
.
TEMPERATURE ·C
100
~
Fig. 13 vs
Ambient Temperature
16 - 5
+12
I
"\
\
\
0.1
0.2
0.3 0.4
0.60.8 I
CIRCUIT RESISTANCE n l v
-
Fig. 14 vs
Circuit Resistance
2
-
TYPE TAP
PLASTIC ENCAPSULATED
TANTALUM CAPACITORS MINIATURE
TYPE SOLID-ELECTROLYTE
ITT - - - - SEMICONDUCTORS
TAP PLASTIC ENCAPSULATED
TANTALUM CAPACITORS
• Small size -
high component density
~L
• Reliability -
long term stability
'~==:-.1]R
• Extremely low leakage current
~I·
~
• Outstanding performance over wide
frequency range
qCASESIZE
1-3; 0.72 ±0,20
4-6; 0,8 ±0,20
''''',,]
• Wide temperature range
1-4 0.D16 DIA
5-60,020 DIA
The extremely stable oxide layer of TAP capacitors allows only a very small leakage current
even after long storage. The solid electrolyte
guarantees very stable electrical performance
over wide temperature ranges and long time
periods.
TAP capacitors are finished in red epoxy and
can be mounted in any position. Rugged construction allows installation in moderate environments experiencing moderate shock and
vibration.
CATALOG ORDERING INFORMATION
(1)
J
~~f:~~;';~~} rT~~
UPPER EDGE OF
PRINTED CIRCUIT
BOARD
TABLE - OUTLINE DIMENSIONS
(maximum in inches)
Case Size Diameter D Length L Lead Space R*
Capacitance 4.7 MF
35 Volts - - - - - - - - - '
Tolerance ±20"!o - - - - - - - '
(2) Optional Features on Special Order
A. Preformed 0.25" leads,
number code "25."
model
B. Capacitance tolerance of ±10"!o
or ±5"!o.
(3) Minimum Packaging Quantity units.
100
1
0.18
0.28'
0.10
2
0.20
0.30
0.10
3
0.26
0.36
0.10
4
0.34
0.40
0.10
5
0.40
0.56
0.20
6
0.44
0.68
0.20
* Applies to capacitors w/straight leads only.
For, TAG/S see drawing.
Information furnished by ITT is believed to be
accu rate and reliable. However, no responsibility is assumed by ITT for its use; nor for any
infringements of patents or other rights of
third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of ITT_
16 - 6
TYPE TAP
PLASTIC ENCAPSULATED
TANTALUM CAPACITORS MINIATURE
TYPE SOLID-ELECTROLYTE
TABLE -
..
..
u
c
ell
.~ U-
u
STANDARD RATINGS
~
ell "CCell
U
0.1
0.15
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4.7
6.8
10.0
15.0
22.0
33.0
47.0
68.0
100.0
150.0
220.0
330.0
470.0
680.0
.!::!
rn
Ol
UI
ell
U
6.3 Volts
3 Volts
Ii
..§
Ii
..§
E
ell
0
z ::E
"
..
..
N
iii
UI
ell
u
Ii
..§
10 Volts
Ii
..§
E
ell
0
z ::E
"
..
N
..
Ii
iii ..§
UI
ell
u
16 Volts
Ii
..§
E
III
0
z ::E
"
..
..
N
iii
UI
ell
u
Ii
Ii
..§
..§
E
ell
0
z ::E
"
1 12
1 10
1
1
2
2
6 18
5.5 16
4.5 12.5
2 8.5
1
8
20
2
4
10
3
3
3
3
4
4
1.2
0.9
0.7
0.5
5
5
6
6
0.4
0.4
0.3
0.3
5.5
3.6 4
2.5
2.0
5
0.9
0.8 6
0.7
0.6
1.5
4.0
0.6
2.0
4
0.4
0.9
0.3
0.7
0.8
3
2.5
5.0
4
1
2.5
5
5
6
6
0.6
0.5
0.4
0.3
1.5
1.1
0.9
0.8
4.5
2.2
5
0.4
1.0
6
0.3
0.8
N
UI
ell
u
Ii
..§
Ii
..§
E
ell
0
z ::E
"
1 19
30
2
9
15
3
3
4.5
3
7.5
5.5
4
1.7
2.8
5
0.8
1.8
6
0.6
1.0
6.5 13.5
5 12
1.8
..
..
iii
25
22
2
2
25 Volts
..
..
N
iii
UI
to
u
35 Volts
Ii
Ii
..
N
..§
..§
iii
E
0
z
::E
"
u
to
1 165 170
1 110 180
1 75 130
1 51
85
1 37
58
1 27
40
2 18
28
2 13
20
3 90
13
3
6
10
4
4
7
4
3
4.5
4
2.5
3.2
5
1.2
2.5
2.0
5
1
0.8
6
1.6
6
0.6
1.2
..
UI
ell
50 Volts
Ii
Ii
..§
..§
E
0
z
::E
"
to
1 170 270
1 105 280
1 80 130
1 50
85
2 32
55,
2 25
38
3 16
26
3 13
18
4
8
12
4
6.2
9
5
3.5
6.5
6
2.2
4.2
6
3.0
1.8
NOTE: Sample quantities are available in most case sizes.
RATINGS
Capacitance ................. 0.1 to 680 p.F
Tolerance Range .... +20% (±10%, ±5%)
Voltage ...................... 3 to 50 volts
Temperature Range .... Continuous operation
between ~55°C to +85°C
Leakage Current .......... CXVXO.02 (p.A)
or 1 p.A, whichever is greater
Dissipation Factor ...... at 120 Hz and 25°C
up to 100p.F less than 6 %
over 100 p.F less than 8 %
Impedance ...... Nominally less than other
electrolytic types, see table
For standard requirements see ITT data sheet
on TAG CAPACITORS featuring the following
ratings:
Tolerance Range ...... +50 -20% (±20%)
Leakage Current .......... C X V X 0.05 (p.A)
or 2 p.A, whichever is greater
Dissipation Factor ...... at 120 Hz and 25°C
up to 150 p.F less than 10%
over 150 p.F less than 12 %
Environment & Mechanical Properties
HUMIDITY-Capacitors are tested after exposure to a maximum humidity of 95 % at
40°C for 21 days with no voltage applied.
LEAD STRENGTH-Leads. are capable of withstanding a pull of 1 pound for 10 seconds and
can tolerate two 90 degree bends without
failure.
MOUNTING & SOLDERING-TAG capacitors
can be dip-soldered with a maximum bath
temperature of 270°C. Acid flux is not suitable
and can damage the units. Soldering time
should not exceed 3 seconds and the cases
of the units should not be dipped to closer
than ,/," of the bath surface.
When bending leads, no stress should be applied to the case. Avoid mounting adjacent
to heat radiating components.
16 -7
TYPE TAP
PLASTIC ENCAPSULATED
TANTALUM CAPACITORS MINIATURE
TYPE SOLID-ELECTROLYTE
Definitions and Ratings
RATED CAPACITANCE 60 cycles and +25°C.
Value measured at
CAPACITANCE TOLERANCE Variation of
actual value from nominal rated value in per
cent (%).
RATED DC VOLTAGE - Listed rating in volts
DC at a surface temperature of +40°C.
CONTINUOUS MAXIMUM VOLTAGE-Highest
DC voltage which can be applied to capacitor.
Max voltage equals rated voltage up to +85°C
ambient temperature.
SURGE VOLTAGE-Maximum voltage to which
capacitor may be subjected 5 times per hour
for one minute. Maximum value is 1.15 times
the rated voltage. Capacitors should not be
used in electrical circuits where the capacitor
is regularly charged and discharged to the
peak of the surge voltage.
REVERSE VOLTAGE-Not to exceed 0.5 Reverse voltage higher than this limit can be
handled by connecting 2 capacitors in antiseries (bipolar capacitor). Resulting capacitors
will be of same voltage, but half capacity of
single unit.
AC RIPPLE VOLTAGE-Sum of superimposed
peak AC voltage and DC voltage must not exceed rated voltage. See figures 3, 6 and 9.
LEAKAGE CURRENT --'- Current measured
through a 1,000n resistor with rated voltage
applied for 3 minutes at +25°C. This current
does not exceed 0.02 times capacitance (,u.F)
times rated voltage (volts), or 1 JJ.A, whichever
is greater. At +85°C, typical leakage current
is less than 10 times the value at +25°C. See
figure 4.
IMPEDANCE-Measured at 10KHz and 25°C.
See figure 8.
DISSIPATION FACTOR-(tangent of loss angle:,
defined by tan {l =2'lTfRC, is measured at
a frequency of 120 Hz, at room temperature,
25°C.
tant~)
Variation of tan,'j with temperature is shown
in figure 10.
Protective Circuit Resistance
The failure rate of TAP capacitors will be
70.=1 x 10- 0 h-l
at 3 Ohm/voltage circuit resistance
65°C arid rated voltage
Any lower resistance will increase the failure
rate.
This can be compensated by voltage derating.
See figures 12, 13, and 14.
CHARACTERISTIC CURVES
"0
CASE
SIZE
•
+
r'
~
SIZE
100
iT
I
CASE
SIZE
I
"-
I ••
~
CASE
SIZE
m
z
~5
0
•
90
!
-.
:i
-SIS -40 -20
0
+20 +40 +60 +BOtIOO
TEMPERATURE--C -
Figure 1
••
10"'
, , ,
, 10'
, ,
.
'10
FREQUENCY - KHz - -
Figure 2
16- 8
Figure 3
TYPE TAP
PLASTIC ENCAPSULATED
TANTALUM CAPACITORS MINIATURE
TYPE SOLID-ELECTROLYTE
CHARACTERISTIC CURVES (continued)
':~
,
,
1
I
.l-j-,
I
I
;
,
I
~ ~
~I -10
~
-
~+'~:
I'
I
I
•
•
'
I !
!
!
I
I
I
I
0
!
I
I
iff r-1T
-M-
i
!
I
10"
-~S-40
i
I
-20
!
0
I
:t
--
+20 +40 +60
TENPERATUREJC
+100
I
~
1\g
10.0
0.2
V
0.1
10'
,
,
CASE
SIZE
10'
4-'
,
~ ,
/
0.'
;1;
!
!
~
>~
V
I
0.0
t
i '.
0
/
~
,
,
I
'OV
'"VI I
23V
0;
~
/
~
10:~
16V
,
i 2H
iill~v
,
IOV
6.3V
0.05
0.4
0,8
V l2
OPERATIONAL VOLTAGE ~
-
10-' 2 3 ~ 7100 2 3 ~ 7 10' 2 3 5 7 102
..0
Figure 6
I
10'
H
0
~
f ,--
tl
~
~
~
~
~
0;
~
._,-+
- I
--jot
~
CASE
10'
S~ZE!_
,
,
=+-1=
<' ,"V
',,-
i
,+
-l
3V
0'
10°
16V
100rm_1I
I
6.3V
,- j+v
10'
10
10·'
, II
,
~
'"
1 100
, ,
5
,
FREQUENCY- KHz
FREQUENCY - KHz - -
,+
~ ,M-
--
10'
10'
Figure 9
Figure 8
o.os
;i
10V
~
Figure 7
10'
FREQUENCY - KHz - -
Figure 5
Figure 4
1\
I
16'
0
0.05
CASE
SIZE
0
10.04
CASE
]J;
1
i-'
0.03
0.03
,/
1--.-
~-
r--
----
1.1.
i-'
SIZE
I
0.02
0.01
1---
-20
0
+20 +40 +60
+100
TEMPERATURE _·C - -
Figure 10
0
I-10-'
CASE
SIZE
I
,
..
V
7
,/
0
-5e-40
,II
0.02
/
~
0.01
..
0 . 04
,I
.-
,
,
10°
FREQUENCY - KHz
Figure 11
16-9
,
--
m
10'
10·71~~~~~~~_~
~
so
40
60
100
OPERATING VOLTAGE· ~ % -
Fig. 12 Reject Rate
vs Applied Voltage
120
TYPE TAP
PLASTIC ENCAPSULATED
TANTALUM CAPACITORS MINIATURE
TYPE SOLID-ELECTROLYTE
CHARACTERISTIC CURVES (continued)
.0
,"
,
e ..
1 '0'
1
g •
/
~
~
z
0
~
~
§
-C
0.1
-
The reliability is measured by the reject rate.
=m
nXh
where m =:; number of rejects. n X h
ponents X hours.
= com-
The reject rate increases with applied voltage
Vn and ambient temperature il u ' and falls with
increased circuit resistance R,. As a result of
comprehensive life-tests the reject rate has
been determined as a function of Vn. il u and Rs.
The reject rate for catastrophic failures for
the particular case can be determined from
Fig. 12 to 14 as follows:
= 125°C
RS = 1nIV
0.:5 0.4
0.80.8 I
•
1. Determine the reject rate of FR" as a function of the applied voltage from Fig. 12 with
ilu
+85°C and Rs = 3nN.
=
2. Multiply FR" with the corresponding factor
from Fig. 13 for the actual ambient temperature to obtain the reject rate FR'.
3. Determine the final reject rate FR as a
function of the circuit resistance by multiplying
FR' with the corresponding correction factor
obtained from Fig. 13 (ambient temperature as
parameter).
EXAMPLE: Determination of F for
F " = 6.2.10- 8 • h-'
3U
0.'
Fig. 14 vs Circuit Resistance
Operational Reliability
VB = 50%
\
CIRCUIT RESISTANCE £l/V -
Fig. 13 vs Ambient Temperature
FR
•
•
•
,
IOl2Sb-l----.J"
••......L-,J
••=-"--..
,l,-J-l.,o•......L.,d
••
TEMPERATURE
•
•
R
F'
R
F'
R
= 6.2.10- 8 .9. h- 1 -
FR
= 7.56 x 70- 6 • h- 1
(from Fig. 12)
= 6.2.10- 8 .9.2.8. h-'
16-10
(from Fig. 13)
(from Fig. 14)
ITT
-----
TYPE TAM
Plastic Encapsulated Tantalum Capacitors
SEMICONDUCTORS
TAM PLASTIC ENCAPSULATED TANTALUM
CAPACITORS
• Sub-Miniature size-high component density
RATINGS
Capacitance .............. 0.015p,F to 6.8~F
Tolerance Range .................. ±20 %
Voltage ..................... 3 to 35 volts
Temperature Range ... Continuous operation
between -55°C to +85°C
Leakage Current ................ 1p,A, Max.
Dissipation Factor ...... at 120 Hz and 25 ° C
10% Max.
Impedance ........ Nominally less than other
electrolytic types
Fixed Capacitor.
Tantalum Electrolytic.
Solid Electrolyte:
Porous Anode:
Polar:
Resin Dipped:
The extremely stable oxide layer of TAM capacitors allows only a very small leakage current even after long storage. The solid electrolyte guarantees very stable electrical performance over wide temperature ranges and
long time periods.
Radial Terminations.
General Application.
TAM capacitors are finished in epoxy and can
be mounted in any position. Rugged construction allows installation in moderate environments experiencing moderate. shock and vibration.
1. Manufacturing dimensions are in millimetres.
2. Length of terminations (L,) 15mm (0.6in.)
minimum.
3. Marking for polarity shall be indicated, as
shown, by the position of the coloured spot
relative to the positive terminal.
TYPE TAM
CATALOG ORDERING INFORMATION
(1) Model No. TAM -
-
TantalumT
Capacitance 4.7 p,F
31
-
4.7/35 -
4. The complete capacitance/rated
range is given in Table 1.
~~
5. The t61erance on the wire diameter is
+ 10 % -0.05mm (0.002in.).
6. The maximum length of resin along the terminal wires is 1.5mm (0.055in.) and is contained within the maximum body length L,.
35 Volts - - - - - - - - - - ' Tolerance ±20 %- - - - - - - - - '
Table Case
Size
X
Y
voltage
Outline Dimensions
L,
mm
Max.
in.
D,
mm
Max.
in.
D'
mm
4.5
5.0
0.18
0.20
2.5
2.5
0.10
0.10
0.35
0.35
Nom.
in.
0.014
0.014
16 - 11
Capacitance Range and
Rated Voltage Range
3.3p,F 3V to 0.Q15~F 35V
3V to 0.68p,F 35V
6.8~F
Typical
Weight
(g)
0.064
0.073
TYPE TAM
Plastic Encapsulated Tantalum Capacitors
Factor
0.5
0.1
0.02
Frequency
1 kHz
10 kHz
100 kHz
These conditions apply at all temperatures up
to 85°C. Ripple voltage ratings at higher frequencies are obtained by multiplying the above
100 Hz values by the following factors:TYPICAL PERFORMANCE
Fig. 1-Variation of Capacitance with temperature (referred to 20°C)
Fig. 2-Variation of Power Factor with temperature (measured at 120Hz with maximum
working voltage applied).
5
10
~ 8
III 6
:!i'"
G2
~ 0
z
~ -2
~
-4
Q,
4
~~
4
i,,::::: P""
....
--
:.-
--
-
II:
~ 3
o
I-.
~
1:::=== P""
2
II:
III
3:
o
f-
f-
-8
-10
-60
o
-40
-20
0
20
TEMPERATURE
40
60
80
100
'"
--
I
Q,
'"
o -6
-60
-40
-20
°c
o
20
40
TEMPERATURE
60
80
100
°c
Fig. 4-Variation of Impedance with Frequency.
1000
r'\.
Fig; 3-Variation of leakage current with temperature (measured at maximum working voltage after 3 minutes).
100
d
10
~
z
~
r'\.
10
r---
Q,
!
1,0
./
V
0, I
/
I
100
V
/'
/
/
",
/'
/
/
10- 3
-60 -40
/'
/'
-20
0
/'
/'
20
40
TEMPERATURE OC
10k
lOOk
1M
10M
FREQUENCY Hz
1/
/
Ik
60
80
100
APPLICATION NOTES
These capacitors are suitable for coupling and
decoupling and general applications in electronic circuits. The reliability of these capacitors depends on circuit impedance. In very
low impedance (a.g. less than 3nJV) circuits,
such as power supplies, particular care is
necessary to ensure that the surge voltage
rating is not exceeded. The main mode of
failure is high leakage current or short circuit.
16-12
TYPE TAM
Plastic Encapsulated Tantalum Capacitors
TABLE STANDARD RATINGS
(letter denotes Case Size Code)
Capacilance
}.LF
0.015
0.022
0.033
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4.7
6.8
3V
Case Size
16V
6.3V 10V
25V
35V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Y
Y
LEAD STRENGTH-Leads are capable of withstanding a pull of .12 oz for 10 seconds and
can tolerate three 90 degree bends without
failure.
MOUNTING & SOLDERING-TAM capacitors
can be dip-soldered with a maximum bath
temperature of 270°C. Acid flux is not suitable
and can damage the units. Soldering time
should not exceed 3 seconds and the cases
of the units should not be dipped to closer
than '/." of the bath su rface·.
When bending leads, no stress should be applied to the case. Avoid mounting adjacent to
heat radiating components.
Protective Circuit Resistance
Y
Y
The failure rate of TAM capacitors will be
A
4.2 X 16-" h-, at 3 Ohm/voltage circuit
resistance 85°C and rated voltage
=
Y
Y
Any lower resistance will increase the failure
rate. This can be compensated by voltage
derating.
Y
Definitions and Ratings
Table 2-Ripple Voltage Ratings (r.m.s.)
Working Voltage
3 6.3 10 16 25 35V d.c.
Surge Voltage
3.5 7 12 13 30 40V d.c.
Maximum Reverse
0.3 0.5 0.5 0.5 0.5 0.5V d.c.
Voltage
AC RIPPLE VOLTAGE-Table 2 gives the maximum r.m.s. ripple voltage which may be applied at 100 Hz. The sum of the D.C. voltage
and the peak value of the superimposed alternating voltage must not exceed the normal
rated voltage and no inadmissible reverse polarity must occur.
LEAKAGE CURRENT-Maximum Leakage Current I}.LF (after 3 minutes at rated voltage with
1,000 n series resistance).
.
IMPEDANCE-Measured at 10 KHz and 25°C.
DISSIPATION FACTOR-(tangent of loss angle:,
2-fRC, is measured
tan defined by tan
at a frequency of 120 Hz at room temperature,
25°C. Dissipation Factor is 10% Max.
=
Variation of tan
Figure 2.
Environment & Mechanical Properties
HUMIDITY - Capacitors are tested after exposure to a maximum humidity of 95 % at 40°C
for 21 days with no voltage applied.
with temperature is shown in
Capacitance
}.LF
0.015
0.022
0.033
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4.7
6.8
16 -13
3
6.3
Rated Voltage D.G.
10
16
25
35
10
10
10
10
10
10
10
10
10
7.1
4.3
2.8
1.7
0.9
0.9
0.9
0.9
4.3
2.8
1.7
10
5.7
TYPE TAM
Plastic Encapsulated Tantalum Capacitors
Capacitance in p.F
Colour
Black
Brown
Red
Orange
Yellow
Green
Blue
Violet
Grey
White
D.C. Working
Voltage
1st 2nd Polarity &
Ring Ring Multiplier Colour
Volts
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
7
8
9
White
Yellow
Black
Green
Grey
Pink
3
6.3
10
16
25
35
1st 2nd
RING RING
POLARITY
VOLTAGE
a MULTIPLIER
Example
_BLUE 6}
·6.8,uF/3 volts
XO.001
XO.01
XO.1
_GREY 8
\----~
N.B.-The above sketch shows the position of
the coloured spot which serves both as multiplier and anode indicator.
16-14
WHITE 0.1
6.8JJF
-I
mm
PACKAGE DIMENSIONS
~~---------
SEMICONDUCTORS
Dual In-Line Plastic Package TO-116
~
ORDERING CODE FOR 930 DTL, 9000 TTL,
9300 TTL, 950 CTL AND LINEAR CIRCUITS
'"n ,nmm
Operating Temperature Range (add)
-1 for -55 to + 125°C
-5 for 0 to + 70° C
+ 75°C for digital
J:--~:o\
\'--15°TYP.
200
MAX.
. ,..:,I~
r-020 MIN.
~::r-
Package (add)
B for Flat Pack
C for TO-5 Style
D for Ceramic Dual In-Line
P for Plastic Dual In-Line
T
Example:
ITT709A-1 D
is -55 to -f125°C
Range in Dual In-Line Package
m
I"
.375
NOM.
,
I
14
.745
.760
~lli~
8
f...- .245_..J
.2601
14-Lead Ceramic Dual-In-Line
14-Lead Plastic Power Dual-In-Line
~
I~I
~
200
MAX .
.020
MIN.
""';0 n
I
iI
E
.375 NOM. ~
"-'''"
I
J~---:
=:0 \
\'--15°TYP.
I"
Jl'
.020±.002
~.--r'---1
.760
T--r'---1
U'
.375
NOM.
r-r~
.745
.760
f...- .245
---.J
.2601
17-1
I
14
~lli~
!------!
280 ~I
.250
I...
,
8
PACKAGE DIMENSIONS
16-Lead Ceramic Dual-In-Line
18-Lead Ceramic Dual-In-Line
.~~~ ~
I;
o,,_~
.009+-:-~
I
.125
i
MAX
.110
.375
NOM .'
.<
I
~TI
'c ---- --~--
I
I
~
I
-------
.090 _ _.r--,
n,
.785
L .....-.--"
t .. ___
--0,
.023-_ _
-',
MAX.
=::::::::;::::;JI
!-I<-:orn:~>1
.250
-;.1 f-.020MIN.
NOTES: All dimensions in inches.
Leads are intended for insertion in hole rows on
.300' centers. They' are purposely shipped with
"positive" misalignment to facilitate insertion.
18-Lead Plastic Dual-In-Line
16-Lead Plastic Dual-In-Line
I; .ii~
'I
''''''~t_cccc,
.009.
.011
•
/
.375
.. NOM
.1
.050.,
~_ _
TYP .• .._
_ _--'
.·~~~l ~~---,
L _ _.---,
,------'
.020 _ _~
,
TVP--_-'
'17~
PACKAGE DIMENSIONS
24 -Lead Ceramic Dual-In-Line
24 -Lead Plastic Dual-In-Line
I"
.020
.560
.550
·1
~JX~1 8
MIN.
L
1----.600-----1
I
Ii'
.020L
TYP.T
1.250
TYP.
~'~~~~.J
150
TYR
Mini DIP a-Lead Plastic Package
IMIN' I
-1 0. 02 1--
I
MAX. L
- j 0.20 I
0.067
[MAX.
T~'I
MAX
.433
1
17-3
~'2
"------.J.J
PACKAGE DIMENSIONS
DIMENSIONS -
FLAT PACK
1/4 X 3/16" 14 LEAD
1/4 X 1/4" 10 LEAD
---: ;---.0101.016
IruIUull.t.~t~
T
t
~
i_ : .:
:
- - .....
I
TOl6/020
:
I ...' _ .045/,055
-----i ~.Q20/.Q30
1,0035/.0060
NOTES:
I. PACKAGE WEIGHT: 26GRAMS
1/4 X 3/8" 16 LEAD
1/4 X 1/4" 14 LEAD
I'
f=
I
250
MIN.
f
1!4
300
I
11
718
.240
.260
I
!I
1.
'I
k
.L..-~==..=
L: 050TYP
L004~C==:JI..£*·06=5=MA=X.
T
I~
240 MIN
260MAX
.0050
.0035
IT
17-4
PACKAGE DIMENSIONS
DIMENSIONS -
DIODES
. DOUBLE PLUG DIODE
STANDARD
MECHANICAL DATA
Case: Hermetically sealed glass
Finish: All external surfaces corrosion
--.L.062
020
.rl-= r===('-_---"i)---d~
~I ... :I~
~I
resistant and leads readily solderable
Leads: Dumet, tin plated
Weight: 0.135 grams (approx.)
Mounting Position: Any
Marking: Diodes carry ITT identification,
l..!-1.00
MIN.
160
MAX.
00-35
and are EIA Color Coded. Bands 1, 2, 3
and 4 on the illustration above indicate
the first, second, third and fourth digit
respectively of the type designation
starting from the cathode, end of the
diode.
Black
o
Green
.5
Brown
... 1
Blue
... 6
Red
Violet
2
... 7
Orange
3
Gray
... 8
Yellow
White
.4
.9
.022
018
.110
,..--_ _ _---., --.L MAX.
", - ~I..[i'--~.
L.!-1.00
MIN.
.290
.250
00-7
EPOXY PACKAGE
Lead-Material Silver Plated Copper
00·29.
17-5
)I---r. 1.00
_.".
MIN.
~i
PACKAGE DIMENSIONS
PHYSICAL DIMENSIONS
1-,.195 --.J
.gl::180-1~05
.020
=fi190
MAXL
.-
,/
(f
.019/
3
LE~gS
(f
.500
MIN
(f
U Us U_ _
90
0
-
.200 LEAD
CIRCLE
033
TO-18
TO-5
1.
195 -0.-<
.180
020
MAX ~
~
,115
11 11 IT
019
3 LEADS
I
~-------+--4.150
r
.016
.230
I
-1~00
'LMIN
/ ..... 6
90 0
/
C
.225
·210
.100 LEAD
CIRCLE
TO-52
0
.209
.335
*t~:J,
.230
.370
175
.195
T
-+.030
.040
.170
.210
.165
.m5
8LEAg~, a~ ~ ~ ~ '~J~
8LE!:! ~ ~ ~ ~ ~~l~
SEATING
PLANE
TO-71
TO-78
TO-77
R-131c
ALL DIMENSIONS IN INCHES.
LEADS ARE GOLD-PLATED KOVAR.
NOTE: DIMENSIONS AS PER LATEST
JS-IO COMMITTEE.
17-6
PACKAGE DIMENSIONS
TO-92 PACKAGE
DIMENSIONS
R.-r
TO.100~;~
.335
f-'~~;--j
'.
.305 I
I
Ii
~~In'~f
-r- 5m
~9L~~~S
.016
.
Imnn nnnn
IWUU UUlllL
I
DIA.
T"t- -
.210
'~~
.500
MIN.
t_
.500
MIN.
~
00
SEATING
PLANE
~~3 .019
LEADS
.016
DIA .
•055
.045
TP.
NOTES: LEADS ARE GOLD-PLATED KOVAR
PACKAGE WEIGHT IS 1.32 GRAMS
TO·99
.370
.335-~
1-.335 -----..1
I
.305
I
SEATING
PLANE
'~1~~r"85
-.L
.165
T
8 LEADS-oO
..016
019
.040 M:.:.:,;Ac..:X
.:-,,-.-+---l~
t
0onU
.500
*
MIN .
NOTE-ON SPECIAL ORDER
ITT Semiconductors will provide
TO-18, TO-46 and TO-52 units
with formed leads to the requirements of the TO-S package. In
addition' disc insulators on the
above devices are also available
by special order.
NOTE: DIMENSIONS AS PER LATEST
J'S-IO COMMITTEE.
ALL DIMENSIONS IN INCHES.
LEADS ARE GOLD-PLATED
KOVAR.
PACKAGE WEIGHT IS 1.12
GRAMS.
17-7
For Price and Delivery Information
Call 'Your Local ITT Office
ARIZONA
MINNESOTA
ITT Semiconductors
Suite 209B
201 East Southern
Tempe , Arizona 85282
Telephone: 602-277-8166
ITT Semiconductors
Office 140
4510 West 77th Street
Minneapolis , Minnesota 55435
Telephone: 612-920-2943
Telex : 029-0105
CALIFORNIA
ITT Semiconductors
1121 San Antonio Road
Palo Alto , California 94303
Telephone : 415-961-5265
Tele x: 0348-450
ITT Semiconductors
Suite 540
11222 La Cienega Boulevard
I ng lewood, Cal iforn ia 90304
Telephone: 213-649-4644
Telex : 653-552
ILLINOIS
ITT Semiconductors
Suite 709
8550 West Bryn Mawr
• Chicago , Illinois 60631
Telephone: 312-693-7070
Telex: 025-4409
TWX : 910-253-4905
NEW YORK
ITT Semiconductors
Suite 3003
333 North Broadway
Jericho , Long Island , New York 11753
Telephone: 516-938-1191/2
Telex : 0961-416
ITT Semiconductors
7000 East Genesse Street
Fayetteville , New York 13066
Telephone: 315-445-0560
Telex: 093-7357
PENNSYLVANIA
ITT Semiconductors
676 East Swedesford Road
Wayne , Pennsylvania 19087
Telephone : 215-688-6990/1/2/3
Telex: 084-6351
TEXAS
MASSACHUSETTS
ITT Semiconductors
ITT Semiconductors
Suite 19
594 Marrett Road
Lexington , Mass. 02173
Telephone: 617-861-0880
Telex : 092-3470
2995 LBJ Freeway
Suite 204
Dallas ,Texas 75234
Telephone: 214-243-6631
MICHIGAN
ITT Semiconductors
23629 Liberty Street
Suite 104
Farmington , Michigan 48024
Telephone: 313-477-6060
Telex: 023-5353
CANADA
ITT Semiconductors
Unit 2
1855 Dundas Street
Mississauga , Ontario , Canada
Telephone: 416-625-9022
Telex : 0696-1313
semiconductors
TT
ITT SE M ICONDUC TORS IS A DIVISION OF INTERN ATIONAL TELEPHONE AND TELEGRAPH C O RPORAT ION. 3301 ELECTRON ICS WA Y, WEST PALM BEACH . FLORI DA 33407, (305) 842·2411
FACTORIES IN FLOR IDA· MAS SACHUSE TT S · ENGLAND· FR A N CE · GE RMANY· PORTUGAL· AUSTRALIA
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