1974_MECL_Integrated_Circuits_Series_A_Vol4 1974 MECL Integrated Circuits Series A Vol4
User Manual: 1974_MECL_Integrated_Circuits_Series_A_Vol4
Open the PDF directly: View PDF 
.
Page Count: 624
| Download | |
| Open PDF In Browser | View PDF |
Volume 4
MECL INTEGRATED CIRCUITS
Series A
• Technical Information
• MECL 10,000
• MECL III
• Phase-Locked Loop Components
frECHNICAL DATA]
MECL GENERAL INFORMATION
•
MECL SELECTOR GUIDES
MECL 10,000 Series
MECL III MC1600 Series
•
COMPATIBLE CIRCUITS
PHASE-LOCKED LOOP COMPONENTS
MIL-M-38510 PROGRAM
•
•
THE
SEMICONDUCTOR
DATA LIBRARY
SERIESA
VOLUME IV
prepared by
Technical I nformation Center
MECL INTEGRATED CIRCUITS
This book presents technical data for a broad line of MECL integrated circuits. Complete specifications for the individual monolithic circuits in the most popular MECL
families are provided in the form of data sheets. In addition, selector guides are included
to simplify the task of choosing the best combination of circuits for optimum system
archi teet ure .
The information in this book has been carefully checked and is believed to be reliable;
however, no responsibility is assumed for inaccuracies. Furthermore, this information
does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.
©
Printed in U.S.A.
Series A
MOTOROLA INC., 1974
"All Rights Reserved"
MECL, MECL I,MECL II, MECL III, MECL 10,000, MTTL,
MTTL III, and MDTL are trademarks of Motorola Inc.
CONTENTS
NUMERICAL INDEX . ....................... ii
GENERAL INFORMATION . .................. 1·1
HIGH SPEED lOGICS . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Definitions and Abbreviations . . . . . . . . . . . . . . . . 1-10
TECHNICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
OPERATIONAL DATA . . . . . . . . . . . . . . . . . . . . . . . . 1-20
SYSTEMS DESIGN CONSIDERATIONS . . . . . . . . . . . . 1-23
Package Outl ine Dimensions . . . . . . . . . . . . . . . . .1-32
APPLICATION NOTE ABSTRACTS . . . . . . . . . . . . . . . 1-34
MECL SELECTOR GUIDES . .................. 2-1
MECl II MC1000/MC1200 Series . . . . . . . . . . . . . . . . . 2-3
M ECl III MC1600 Series . . . . . . . . . . . . . . . . . . . . . . 2-5
MECl 10,000 Series . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
MECL 10,000 Series DATA SHEETS . ........... 3-1
MECL III MC1600 Series DATA SHEETS .. ...... 4-1
COMPATIBLE CiRCUITS ..... ................ 5-1
PHASE-LOCKED LOOP COMPONENT .......... 6-1
DATA SHEETS
MIL-M-38510 PROGRAM . .................... 7-1
NUMERICAL INDEX
DEVICE
MC1543L
MC1648
MC1650
MC1651
MC1654
MC1658
MC1660
MC1662
MC1664
MC1666
MC1668
MC1670
MC1672
MC1674
MC1678
MC1688
MC1690
MC1692
MC1694
MC7900C
MC10100
MC10101
MC10102
MC10103
MC10104
MCl 01 05
MC10l06
MC10107
MCl 01 09
MC10110
MC10111
MC10113
MC10114
MC10115
MC10116
MC10117
MC10118
MC10119
MC10121
MC10123
MC10124
MC10125
MC10128
MC10129
MC10130
MC10131
MC10132
MC10133
MC10134
MC10135
MC10136
MC10137
MC10138
MC10141
MC10153
DEVICE
PAGE
MC10160
MC10161
MC10162
MC10163
MC10164
MC10165
MC10166
MC10168
MC10171
MC10172
MC10173
MC10174
MC10175
MC10176
MC10177
MC10178
MC10179
MC10180
MC10181
MC10182
MC10193
MC10195
MC10197
MC10210
MC10211
MC01212
MC10216
MC10231
MC10287
MC10501
MC10502
MC10504
MC10505
MC10506
MC10507
MC10509
MC10514
MC10515
MC10516
MC10517
MC10518
MC10519
MC10521
MC10524
MC10525
MC10530
MC10531
MC10533
MC10535
MC10536
MC10537
MC10541
MC10560
MC10561
MC10562
5-3
4-3
4-10
4-10
4-23
4-26
4-30
4-34
4-38
4-42
4-47
4-52
4-60
4-64
4-68
4-72
4-75
4-81
4-85
5-9
3-3
3-5
3-8
3-11
3-13
3-16
3-19
3-22
3-25
3-28
3-31
3-34
3-36
3-39
3-42
3-45
3-48
3-51
3-54
3-57
3-59
3-62
3-65
3-71
3-75
3-79
3-83
3-88
3-92
3-97
3-101
3-107
3-111
3-114
3-118
ii
PAGE
3-121
3-125
3-129
3-133
3-141
3-146
3-150
3-154
3-157
3-161
3-165
3-170
3-173
3-177
3-180
3-183
3-186
3-191
3-195
3-199
3-133
3-204
3-207
3-210
3-212
3-214
3-217
3-221
3-225
3-232
3-235
3-238
3-241
3-244
3-247
3-250
3-253
3-256
3-259
3-262
3-265
3-268
3-271
3-274
3-277
3-280
3-284
3-288
3292
3-296
3-303
3-308
3-312
3-316
3-321
NUMERICAL INDEX(continued)
DEVICE
PAGE
MC10564
MC10571
MC10572
MC10574
MC10575
MC10579
MC10580
MC10581
MC10616
MC10631
MC12000
MC12012
MC12040
3-326
3-331
3-335
3-339
3-343
3-347
3-352
3-356
3-362
3-366
6-12
6-23
6-38
DEVICE
MC12060
~1C12061
MC12560
MC12561
MCM7001 L
MCM10140
MCM10142
MCM10143
MCM10144
MCM10145
MCM10147
MCM10148
MCM10150
PAGE
6-42
6-42
6-42
6-42
5-18
3-370
3-370
3-374
3-379
3-383
3-387
3-370
3-391
GENERAL
INFORMATION
MECL GENERAL INFORMATION
Table of Contents
PAGE
SECTION I: HIGH SPEED LOGICS
MECL Products ..
Family Comparison tables ..
MECL in Perspective
MECL Applications ..
Considerations for High Speed Logic Design ..
MECL Circuit Description ..
Variations among MECL Families
Definitions, Symbols, and abbreviations.
1-4
1-5
1-6
1-6
1·7
1-8
1-9
1-10
SECTION II: TECHNICAL DATA
General Characteristics and Specifications
Maximum Ratings.
Noise Margin
Maximum Ratings (table!
Logic Levels (table!
Logic Level variations - tables and graphs.
AC or time Parameters.
Variations in ac parameters (graphs!
Package Dimensioned Drawings.
1-12
1·12
1-12
1-13
1-13
1-13
1·17
1-17
1·32
SECTION III: OPERATIONAL DATA
Power supply considerations .. .
Loading characteristics . . . . . .
AC variations with loading (graphs!
Unused MECL inputs ..
1-20
1·21
1-22
1-23
SECTION IV: SYSTEM DESIGN CONSIDERATIONS
Thermal Management. ..
Thermal Data (tables! ....
Mounting and heat sinks for MECL III
Compatibility among MECL Families ..
Interfacing MECL to slow logic
Circuit Interconnections . . . . .
Clock Distribution . . . . . . . . . . . . . .
System Design - Summary Recommendations . . . . . . . . . . .
1-23
1-24
1-24
1-26
1-27
1-28
1-29
1-31
SECTION V: MECL LITERATURE
Application Note abstracts ..
Supplementary Literature . . . . . . . . . . . . . . . . . . .
MECL System Design Handbook - contents
1-34
1-37
1-38
1-3
GENERAL INFORMATION
SECTION I: HIGH SPEED LOGICS
of over 70 MHz. Speeds were later increased first to
120 MHz (typical) for the MC1027/MC1227 J·K
flip·flop circuit, and then to 180 MHz (min.) for
the MC1034 type 0 flip·flop.
Complex functions became available in MECL II
when production capabilities shifted toward more
complicated circuits. The family now has adders, data
selectors, multiplexers, decoders, and a gas display
tube decoder/driver.
Continuing development of MECL made possible
an even faster logic family. As a result, MECL III was
introduced in 1968. Its 1 ns gate propagation delays
and greater than 500 MHz flip·flop toggle rates
remain the industry leaders. For the moment, the
very high speed capabilities of MECL III appear to
have outstripped the general speed requirements of
today's computer systems, however they are being
utilized extensively in special high·speed sections of
computers and high speed test and communication
equipment. Motorola is continuing to develop and
expand this product line.
For general purpose computer applications, trends
in large high·speed systems showed the need for an
easy·to·use logic family with propagation delays on
the order of 2 ns. To match this requirement, the
MECL 10,000 Series was introduced in 1971.
An important feature of MECL 10,000 is its
compatibility with MECL III to facilitate using both
families in the same system. A second important
feature is its significant power economy - MECL
10,000 gates use less than one·half the power of
MECL III or high speed MECL II gates. Finally, low
gate power and advanced circuit design techniques
have permitted a new level of complexity for MECL
circuits. For example, complexity of the MC10181
four bit arithmetic unit compares favorably to that of
any bipolar integrated circuit on the market.
The basic MECL 10,000 Series has recently been
expanded by a subset of devices with even greater
speed. This additional series provides a selection of
MECL 10,000 logic functions with flip·flop repetition
rates up to 200 MHz min. The MECL 10,200 Series is
meant for use in critical timing chains, and for clock
distribution circuits. MECL 10,200 parts are other·
wise identical to their 10,000 Series counterparts
(subtract 100 from the MECL 10,200 part number to
obtain the equivalent standard MECL 10,000 part
number).
Although the basic design of all MECL families is
the same, there are differences other than the speed
and power capabilities. Comparisons of the key
characteristics of each family are given in the tables
of Figure 1.
For the purposes of this discussion, high speed
logic has either or both of two characteristics:
a) toggle rates over 50 MHz
b) gate propagation delays under 6 ns
Only two types of standard high speed logic
integrated circuits are commonly available in the
marketplace: Schottky·clamped TTL logic (TTL·S),
and non·saturating emitter·coupled logic (ECL).
Schottky·clamped TTL logic is similar to conven·
tional TTL logic in its circuit configuration and
operating characteristics. Conventional TTL is a
saturated form of logic; that is, during turn·on, both
the emitter·base and collector·base junctions of a
transistor are forward biased, causing an accumula·
tion of charged carriers in the base regions. Then,
when the transistor is turned off, this charge must
discharge through the collector. The finite time
required for this charge to dissipate causes a delay in
turning the transistor off. This "storage time" delay is
an integral part of all saturated logic forms. Schottky·
clamped TTL logic reduces storage time by means of
Schottky·diodes between base·collector junctions.
These diodes tend to keep the transistor out of
saturation, but they also tend to increase the input
capacitance of the Schottky·clamped transistor. Thus,
while the speed of TTL·S is greater than that of TTL,
due to a reduction in storage time, it is limited by the
RC time constant of the transistor input.
Emitter·Coupled Logic, being non·saturating by
design, completely avoids transistor storage time and
its attendent speed limitation without the tradeoffs
inherent in TTL·S. Gate delays of less than a
nanosecond and operating frequencies approaching a
gigahertz are currently feasible, and even these are
not ultimate limits.
MECL PRODUCTS
Motorola offers four ECL logic families under its
MECL trademark: MECL I, MECL II, MECL III, and
MECL 10,000.
The MECL I family, introduced by Motorola in
1962, was the first monolithic integrated circuit line
of emitter·coupled logic. Its propagation delay time
of 8 ns and toggle rate of 30 MHz, though no longer
considered state of the art, still places it above the
speed capabilities of most saturated logic lines. It is
still being produced in quantity for use in existing
equ ipment designs, but several features of the more
advanced MECL II, III, and MECL 10,000 families
favor the use of these families in new designs.
In 1966, Motorola introduced MECL II with gate
propagation delays of 4 ns, and flip·flop toggle rates
1-4
MECL FAMILY COMPARISONS
Feature
MECL 10,000
10,100 Series
10,200 Series
10,500 Series
10,600 Series
MECLI
MECL II
8 ns
4 ns
2 ns
1.5 ns
8.5 ns
4 ns
3.5 ns
2.5 ns
1 ns
3. Flip-Flop Toggle Speed (min)
30 MHz
165 MHz
125 MHz
200 MHz
500 MHz
4. Gate Power
31 mW
22mW
25mW
25mW
60mW
5. Speed-Power Product
250 pJ
88 pJ
50 pJ
37 pJ
60 pJ
6. Transmission Line Capability
No
On Some Devices
Ves
Ves
Ves
7. Wire-Wrap Capability
Ves
Ves
Ves
Ves
No
8. Output Pulldown Resistors
Ves
Optional
No
No
No
9. Input Pulldown Resistors
No
No
50 k!1
50 k!1
2 k!1 & 50 k!1
1. Gate Propagation Delay
2. Gate Edge Speed
MECL III
1 ns
FIGURE la - GENERAL CHARACTERISTICS
Ambient Temperature Range
MECLI
MECL II
MECL III
aOc to +75°C
MC350
MC1000
-
-30°C to +85°C (industrial)
-
-
-55°C to +125°C (military)
MC300
MC1200
(commercial)
-
MC1600F .L
.
FIGURE lb - OPERATING TEMPERATURE RANGE
~
--
Ceramic Flat Pack_ (Hermetic)
Plastic DIP
Ceramic DIP (Hermetic)
(For package dimensions see page 32)
MECL III
MECL 10,000
Ves
Ves
Ves
(selected types)
Ves
Ves
Yes
FIGURE 1c - PACKAGE STVLES
1-5
MECL 10,100
MECL 10,200
MECL 10,500
MECL 10,600
*Planned for selected devices.
Package Style
MECL 10,000
MECL IN PERSPECTIVE
CMOS (quiescent dissipation)
60
50
40
. ~
.
E
>
I
20
I
"0
o
o 10
.~
g' 7.0
~
I!
30
Gi
I
I __
I
-
-t
+ - -
1
consta~t 5?
93LOO
,:'
pJ Lone
}
__
t--+--+-H-~
18060
54LS/~4LS! 154/14
•
-l-t--'-+~i'd-H+
I-
60
~
TT\~
40
1./r;lJCL
"• 30
./
:0
80
~r5d~f==t==F=t~--+--t
, , l--+-++1
54L/~4~
t +
t--,--,-
20
i
ECL
IITI
I
10
2.0
10
1.0
-nW
I
MECL 10,000
rm
100
Frequency (MHz)
2
3
4 567
10
70100
Power dissipation (mW/gate)
FIGURE 2b - POWER DISSIPATION
versus FREQUENCY (MECL versus TTL-SI
FIGURE 2a - SPEED-POWER CHARACTERISTICS
OF MAJOR LOGIC LINES
MECL IN PERSPECTIVE
Wide Variety of Functions, including complex
functions facilitated by low power dissipation
(particularly in MECL 10,000 series). A basic MECL
10,000 gate consumes less than 8 mW in on-chip
power in some complex functions.
Wide Performance Flexibility due to differential
amplifier design which permits MECL circuits to be
used as linear as well as digital circuits.
Transmission Line Drive Capability is afforded by
the open emitter outputs of MECL devices. No "Line
Drivers" are listed in MECL families, because every
device is a line driver.
Wire-ORing reduces the number of logic devices
required in a design by producing additional OR gate
functions with only an interconnection.
Twisted Pair Drive Capability permits MECL
circuits to drive twisted-pair transmission lines as long
as 1000 feet.
In evaluating a logic line, speed and power
requirements are the obvious primary considerations.
In Figure 2, today's major logic families are compared
on the basis of these characteristics. But these are
only the start of any comparative analysis. While the
chart clearly shows that MECL and other ECL-type
families are without peer in the speed category, with
low power levels that rival some of the TTL lines,
there are a number of other characteristics that make
MECL highly desirable for systems implementation.
Among these:
Complementary Outputs cause a function and its
complement to appear simultaneously at the device
outputs, without the use of external inverters. It
reduces package count by eliminating the need for
associated invert functions and, at the same time, cuts
system power requirements and reduces timing differential problems arising from the time delays
introduced by inverters.
High Input Impedance and Low Output Impedance permit large fan out and versatile drive char·
acteristics.
Insignificant Power Supply Noise Generation, due
to differential amplifier design which eliminates
current spikes even during signal transition period.
Nearly Constant Power Supply Current Drain
simplifies power-supply design and reduces costs.
Low Cross-Talk due to low-current switching in
signal path and small (typically 850 mV) voltage
swing, and to relatively long rise and fall times.
MECL APPLICATIONS
The graduated speed ranges of the various MECL
Families satisfy a great many digital system requirements. MECL 10,000 is a general-purpose, high-speed
logic family specifically designed for smaller digital
systems and peripherals as well as large computers.
MECL III is recommended where its exceptionally
high speed can buy needed system performance. It is
used frequently in counter pre-scalers, high-speed
digital communication systems, VHF phase-locked
loops, high-speed digital processors, and high-speed
timing chains in computers.
1-6
to another are insignificant. But for a great many
externally interconnected parts, this can soon add up
to an appreciable delay time. Hence, the greater the
number of functions per chip, the higher the system
speed. MECL circuits, particularly those of the MECL
10,000 Series are designed with a propensity toward
complex functions to enhance overall system speed.
The compatibility among MECL families provides a bridge between system performance and
system cost. Thus, the many functions and complex
circuit members of the MECL 10,000 Line can be
conven iently mixed with the very-high-speed functions
of MECL III, in judicious combinations for system
optimization.
BASIC CONSIDERATIONS
LOGIC DESIGN
FOR
Waveform distortion due to line reflections also
becomes troublesome principally at state-of-the-art
speeds. At slow and medium speeds, reflections on
interconnecting lines are not usually a serious
problem. At extreme speeds, however, line lengths
can approach the wavelength of the signal and improperly terminated lines can result in reflections
that will cause false triggering (see Figure 3). The
solution, as in RF technology, is to employ "transmission-line" practices and properly terminate each
signal line with its characteristic impedance at the end
of its run. The low-impedance, emitter-follower outputs of MECL circuits facilitate transmission-line
practices without upsetting the voltage levels of the
system_
The increased affinity for crosstalk in high·speed
circuits is the result of very steep leading and trailing
edges (fast rise and fall times) of the high-speed
signal. These steep wavefronts are rich in harmonics
that couple readily to adjacent circuits. In the design
of MECL 10,000, the rise and fall times of the gate
waveforms have been deliberately slowed. This reduces
the affinity for crosstalk without compromising other
important performance parameters.
From the above, it is evident that the MECL logic
line is not simply capable of operating at high speed,
but has been specifically designed to reduce the
problems that are normally associated with highspeed operation.
HIGH SPEED
High-speed operation involves only four considerations that differ significantly from operation at jow
and medium speeds:
1. Time delays through interconnect wiring, which
may have been ignored in medium-speed systems,
become highly important at state-of-the·art speeds.
2. The possibility of distorted waveforms due to
reflections on signal lines increases with edge speed.
3. The possibility of "crosstalk" between adjacent
signal leads is proportionately increased in high speed
systems.
4. Electrical noise generation and pick-up are
more detrimental at higher speeds.
In general, these four characteristics are speed- and
frequency-dependent, and are virtually independent
of the type of logic employed. The merit of a
particular logic family is measured by how well it
compensates for these deleterious effects in system
applications.
The interconnect-wiring time delays can be
reduced only by reducing the length of the interconnecting lines. At logic speeds of two nanoseconds,
an equivalent "gate delay" is introduced by every
foot of interconnecting wiring. Obviously, for functions interconnected within a single monolithic chip
the time delays of signals travelling from one function
-~··8"---~-8"-
F-
~S!
RL - Zo
VTT"" -2 Vdc
~
+--
I
I
I
Receiving Gate
··
·, ;.
·.." f\
Input A
I
Low
.h
n
I,
:,
n"
I
High ~
1Jv..,..J
H:9h
I
I
V
:
,
\
,
,
Receiving Gate
Input A
(
I
Low
1
~ v
I
J
FIGURE 3b - PROPERLY TERMINATED
TRANSMISSION LINE
(Ground Plane Added)
FIGURE 3a - UNTERMINATED TRANSMISSION LINE
(No Ground Plane Used)
1-7
GATE TRANSFER CURVES
GATE CIRCUIT
Multiple
Input'
Oift~.nti.1
Bies
Amplifier
Network
Complementary
Output,
~
~
~
;---"-..
C2
-0.800
Hlth (-O.9 V typ.)
I---~-"----/I--
-::::~:
-1.200
VBS - -1.29 V
-+_VC_t-
Low(-1.75 V typ_)
·1.800
-1.200
-1.400
Input Voltage (Volt,)
A
B~A+B+C+O
C
o
~---v,...-----'
A+8+0+C
GATE SYMBOL
INPUTS
FIGURE 4 - MECL GATE STRUCTURE AND SWITCHING BEHAVIOR
CIRCUIT DESCRIPTION
The typical MECL circuit, Figure 4, consists of a
differential-amplifier input circuit, a temperature and
voltage compensated bias network, and emitterfollower outputs to restore dc levels and provide
buffering for transmission line driving. High fan-out
operation is possible because of the high input
impedance of the differential amplifier input and the
low output impedance of the emitter follower outputs. Power-supply noise is virtually eliminated by
the nearly constant current drain of the differential
amplifier, even during the transition period. Basic
gate design provides for simu Itaneous output of both
the OR function and its complement, the NOR
function.
are cut off because their P-N base-emitter junctions
are not conducting, and the forward-biased 05 is
conducting. Under these conditions, with the base of
05 held at -1.29 V by the VBB network, its emitter
will be one diode drop (0.8 V) more negative than its
base, or -2.09 V. (The 0.8 V differential is a
characteristic of this P-N junction.) The base-toemitter differential across 01 - 04 is then the
difference between the common emitter voltage
(-2.09 V) and the LOW logic level (-1.75 V) or 0.34
V. This is less than the threshold voltage of 01
through 04 so that these transistors will remain cut
off.
When anyone (or all) of the logic inputs are
shifted upward from the -1.75 V LOW state to the
-0.9 V HIGH state, the base voltage of that transistor
increases beyond the threshold point and the transistor turns on. When this happens, the voltage at the
common-emitter point rises from -2.09 V to -1.7 (one
diode drop below the -0.9 V base voltage of the input
transistor), and since the base voltage of the fixedbias transistor (05) is held at -1.29 V, the baseemitter voltage of 05 cannot sustain conduction.
Hence, this transistor is cut off.
This action is reversible, so that when the input
signal(s) return to the LOW state, 01 - 04 are again
turned off and 05 again becomes forward biased. The
collector voltages resulting from the switching action
of 01 - 04 and 05 are transferred through the output
emitter-follower to the output terminal. Note that
the differential action of the switching transistors
(one section being off when the other is on) furnishes
simultaneous complementary signals at the output.
This action also maintains constant power supply
current drain.
Power-Supply Connections - Any of the power
supply levels, VBB, VCC, or VEE may be used as
ground; however, the use of the VCC node as ground
results in best noise immunity. In such a case: VCC =
0, VBB = -1.15 to -1.3 V (depending on the specific
MECL family), VEE = -5.2 V.
System Logic Specifications - The output logic
swing of 0.B5 V, as shown by the typical transfer
characteristics curve, varies from a LOW state of VL =
-1.75 V to a HIGH state of VH = -0.9 V with respect
to ground. (These logic levels are valid for the MECL
10,000 and MECL III families. MECL I and II logic
levels differ slightly.)
Positive logic is used when reference is made to
logical "D's" or "l's." Then
"0" =
~1.75
V = LOW
typical
"1" = -0.9 V = HIGH
Circuit Operation - Beginning with all logic inputs
LOW (nominal -1.75 V), assume that 01 through 04
'-8
MECL I
MECL II
.,t;.'
Dittar•
Amplifier
Vee
Inputs
Bia.
Network
Follower Outputs
~~~~
Vee
,--"--..
270
Diff.rential
Amplifier
300
290
NOR
OR
1.18k
2k
2.30k
RL
RL
A
v
VARIATIONS AMONG MECL FAMILIES
Inputs
The basic gate circuits of the four MECL families
are illustrated in Figure 5. From these diagrams, it is
evident that some variations were employed as
technology advanced. The first of these is that the
bias driver for the MECL I Line is not included on the
chip, whereas all subsequent lines have this as an
internal feature.
Second, most corresponding resistor values differ
among all MECL Lines. This difference is necessary to
achieve the varying speed and power improvements of
the different lines. Of course, speed is not determined
by resistor values alone. Transistor geometries, while
not represented on a schematic, are a major deter·
minant. The transistor geometries in conjunction with
the resistor values provide the speed and power
characteristics of the different families.
Third, it will be noted that MECL 10,000 and
MECL III gates are supplied with base pull-down
resistors (Rp = 50,000 m in each of the input
transistors while the other two families are not. These
resistors provide a path for base leakage current to
unused input bases, causing them to be well turned
off. Where these resistors are not used, any unused
inputs must be externally tied to a suitable negative
potential, e.g., VEE.
A final significant difference among the families
is in the output circuits. MECL I circuits normally are
supplied with output pull·down resistors on the chip.
MECL II circuits can be obtained with or without
output resistors. MECL III and MECL 10,000 circuits
have open outputs.
The use of on·chip output resistors has both
advantages and limitations. On the plus side is the
obvious advantage that fewer external components
are required. On the minus side is the fact that
wire·ORing capability with on·chip pulldown resistors
is limited. Moreover, with open outputs the designer
can choose both the value and location of his
termination to meet the system requirements. And
finally, the use of external resistors reduces on·
chip heating and power dissipation, allowing more
complex LSI and increasing chip life and reliability.
MECL III
Emitter
MultIple t "puts
DIfferentIal
Ampllf,er
Network
Follower
Outputs
100
36'
2k
1958
MECL 10.000
EmItter
Multiple
D,fferentIal
Bias
FOllower
Input$
AmplifIer
Network
Outputs
~~~r---"-.
FIGURE 5 - BASIC GATE DIAGRAMS FOR
THE MECL FAMILIES
'-9
DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS
Current:
Voltage:
Base leakage current of a MECL expander
input when at VEE.
ICC
VBB
Reference bias supply voltage.
VBE
Base·to-emitter voltage drop of a transistor at specified collector and base
VCB
Collector-to-base voltage drop of
transistor at specified collector and base
currents.
Vce
General term for the most positive power
supply voltage to a MECL device (usually
Total power supply current drawn from
the positive supply by a MECL unit under
test (IC on older data sheets).
ICBO
Leakage current from input transistor on
MECL devices without pulldown resistors
when test voltage is applied.
ICCH
Current drain from VCC power supply
with all inputs at logic HIGH level.
ICCL
Current drain from VCC power supply
ICEX
Collector
currents.
ground, except for translator and interface circuits).
"CC1
with all inputs at logic LOW level.
cut·off
current
(VCE
devices.)
VBE(off) as specified). For a MECL gate
expander, this term signifies the total
VCC2
collector leakage current when all inputs
are at the negative supply potential.
Most negative power supply voltage for a
circuit (usually -5.2 V for MECL devices).
Forward diode current drawn from an
input of a saturated 10gic·to·MECL trans·
lator when that input is at ground
interface circuits.
Input voltage for measuring IF on TTL
Input logic HIGH voltage level (nominal
value).
potential.
*VIH max Maximum HIGH level input voltage: The
most positive lIeast negative) value of
high-level input voltage, for which
operation of the logic element within
when a maximum logic HIGH (VIH max)
is applied at that input.
HIGH level node input current into an
input node with a specified HIGH level
specification limits is guaranteed.
Input logic HIGH threshold voltage level.
(V I H max) logic voltage appl ied to that
node. (Same as lin for positive logic.)
VIHA min Minimum input logic HIGH level (threshold) voltage for which performance is
specified.
LOW level node input current. The cur·
rent flowing into an input node with a
specified LOW level IV I L min)
voltage applied to that node.
logic
'VIH min
Minimum HIGH level input voltage: The
least positive (most negative) value of
HIGH level input voltage for which operation of the logic element within specification limits is guaranteed.
VIL
Input logic LOW voltage level (nominal
value).
'VI L max
Maximum LOW level input voltage: The
most positive (least negative) value of
LOW level input voltage for which operation of the logic element within specification limits is guaranteed.
V I LA
I nput logic LOW threshold voltage level.
Load current that is drawn from a MECL
circuit output when measuring the output
HIGH level voltage.
HIGH level output current: the current
flowing into the output, at a specified
HIGH level output voltage.
*IOL
LOW level output current: the current
flowing into the output, at a specified
LOW level output voltage.
lOS
Output short circuit current.
lout
Output current (from a device or circuit,
under such
context).
conditions
mentioned
VILA max Maximum input logic LOW level (threshold) voltage for which performance is
specified.
in
Reverse current drawn from a transistor
input of a test unit when VEE is applied
at that input.
ISC
Most positive power supply voltage Icurrent switches and bias driverllusually
ground for MECL devices).
Total power supply current drawn from a
MECL test unit by the negative power
supply.
Current into the input of the test unit
*IOH
Most positive power supply voltage (output devices). (Usually ground for MECL
and
'VIL min
Short·circuit current drawn from a trans·
lator saturating output when that output
is at ground potential.
Minimum LOW level input voltage: The
least positive (most negative) value of
LOW level input voltage for which opera-
• JEDEC, EIA, NEMA standard definition
1-10
t-+
tion of the logic element within specification limits is guaranteed_
Yin
I nput voltage (to a circuit or device\-
V max
Maximum (most positive) supply voltage,
permitted under
specified set of
tpd
tx±y±
conditions.
'VOH
VOHA
Output logic HIGH voltage level: The
voltage level at an output terminal for a
specified output current, with the
specified conditions applied to establish a
HIGH level at the outpuL
Output logic HIGH
leveL
threshold voltage
t x+
Output waveform rise time as measured
from 10% to 90% or 20% to 80% points
on waveform (whichever is specified) at
pin x with input conditions as specified.
t x-
Output waveform fall time as measured
from 90% to 10% or 80% to 20% points
on waveform (whichever is specified) at
pin x, with input conditions as specified.
VOHA min Minimum output HIGH threshold voltage
level for which performance is specified.
VOH max
Maximum output HIGH
voltage for given inputs.
or high-level
Propagation Delay, see Figure 12.
Propagation delay, input to output from
the 50% point of the input waveform at
pin x (falling edge noted by - or rising
edge noted by +) to the 50% point of the
output waveform at pin y (falling edge
noted by -, or rising edge noted by +\- (Cf
Figure 12.)
f tog
Toggle
frequency
of
a
VOH min
Minimum output HIGH or high-level voltage for given inputs.
Shift rate for a shift register.
fshift
Te mperature:
'VOL
Output logic LOW voltage level: The
voltage level at the output terminal for a
specified output current, with the
specified conditions applied to establish a
LOW level at the outpuL
tstg
VOLA
TJ
Output logic LOW threshold voltage leveL
Maximum output LOW level voltage for
given inputs.
VOL min
Minimum output LOW level voltage for
given inputs.
°JC
Line load-resistor terminating voltage for
outputs from a MECL device.
Output logic LOW level on MECL 10,000
line receiver devices with all inputs at
VEE voltage leveL (This parameter is only
valid for devices on whose data sheets it is
specified).
LFPM
VOLS2
tr
Same as t+
tf
t+-
Same as tPropagation Delay, see Figure 12.
Linear feet per minute.
Miscellaneous:
Time Parameters:
Waveform fall time (HIGH to LOW), 90%
to 10%, or 80% to 20%, as specified.
Thermal resistance of an IC package,
Thermal resistance of an IC package, case
to ambient.
(This parameter is only valid for devices
on whose data sheets it is specified).
t-
Junction (or die) temperature of an integrated circuit device.
junction to case.
line receiver devices with all inputs open.
Waveform rise time (LOW to HIGH), 10%
to 90%, or 20% to 80%, as specified.
or
Thermal resistance of an IC package,
junction to ambienL
Output logic LOW level on MECL 10,000
t+
damage
Am bien t (environment) temperature
existing in the immediate vicinity of an
integrated circuit device package.
VOL max
VOLS1
or
Maximum temperature at which device
may be stored without
performance degradation.
VOLA max Maximum output LOW threshold voltage
level for which performance is specified.
VTT
flip-flop
counter device.
eg
Signal generator inputs to a test circuit_
TPin
Test point at input of unit under test.
TP out
Test point at output of unit under test.
O.U.T.
Device under test.
Zout
Output impedance.
'PO
The total dc power applied to a device,
not including any power delivered from
the device to a load_
Load Resistance.
Terminating (load) resistor.
Rp
An input pull-down resistor (i.e., connected to the most negative voltage).
• JEOEC, EIA, NEMA standard definition
1-11
SECTION II - TECHNICAL DATA
MECL TRANSFER CURVES
For MECL logic gates, the dual (complementary)
outputs must be represented by two transfer curves:
one to describe the OR switching action and one to
describe the NOR switching action. A typical transfer
curve and associated data for all MECL families is
shown in Figure 7a.
It is not necessary to measure transfer curves at all
points of the curves. To guarantee correct operation
it is sufficient merely to measure two sets of min/max
logic level parameters.
The first set is obtained by applying test voltages,
VI L min and VIH max (sequentially) to the gate
inputs, and measuring the OR and NOR output levels
to make sure they are between VOL max and VOL
min, and VOHmax and VOHmin specifications.
The second set of logic level parameters relates to
the switching thresholds. This set of data is
distinguished by an "A" in symbol subscripts. A test
voltage, VILA max, is applied to the gate and the
NO Rand 0 R outputs are measured to see that they
are above the VOHA min and below the VOLA max
levels, respectively. Similar checks are made using the
test input voltage VIHA min.
The result of these specifications insures that:
a) The switching threshold ('" VSS) falls within
the darkest rectangle; i.e. switching does not begin
outside this rectangle;
b) Quiescent logic levels fall in the lightest shaded
ranges;
c) Guaranteed noise immunity is met_
Figure 7b shows guaranteed 25 0 C logic level limits
and switching thresholds for each of the MECL families, along with typical HIGH and LOW logic levels.
GENERA L CHARACTERISTICS and
SPECIFICATIONS
(See pages 7 and 8 for definitions of symbols and
abbreviations)
In subsequent sections of this Data Sook, the
functional blocks of all four MECL lines are identified and characterized. Complete data sheets are
provided for each of the functions in the MECL II,
MECL III, and MECL 10,000 families'. To make
these data sheets as useful as possible, and to avoid a
great deal of repetition, the data that is common to
all functional blocks in a line is not repeated on each
individual sheet. Rather, these common characteristics, as well as the application information
that applies to each family, are discussed in this
section.
In general, the common characteristics of major
importance are:
Maximum Ratings, including both dc and ac
characteristics and temperature limits;
Transfer Characteristics, which define logic levels
and switching thresholds;
AC Parameters, such as propagation delays, rise
and fall times and other time dependent characteristics.
In addition, this section will discuss general layout and design guides that will help the designer
in building and testing systems with MECL circuits.
LETTER SYMBOLS AND ABBREVIATIONS
Throughout this section, and in the subsequent
data sheets, letter symbols and abbreviations will be
used in discussing electrical characteristics and
specifications. Recently, these symbols have been
under scrutiny by various industry organizations,
resulting in a number of additions and changes. The
symbols used in this book, and their definitions, are
listed on the preceeding two pages.
Of additional interest are the variations of these
parameters at Ii mit temperatures. These are given in
the tables of Figure 8, for the MECL II, III, and
10,000 families.
All of these specifications assume -5.2 V power
supply operation. Operation at other power-supply
voltages is possible, but will result in further transfer
curve changes. Transfer characteristic data obtained
for a variety of supply voltages are shown in Figure
9. The table accompanying these graphs indicates the
change rates of output voltages as a function of
power supply voltages.
Variations in logic swing amplitude for MECL II,
III, and 10,000 are shown in Figure 10.
MAXIMUM RATINGS
The dc limit parameters beyond which the life of
the devices may be impaired are given in the
following table in Figure 6 for all MECL families. In
addition, the table provides certain ac parameter
limits which, if exceeded, will not destroy the devices,
but could degrade the performance below that of the
guaranteed specifications.
NOISE MARGIN
"Noise margin" is a measure of a logic circuit's
resistance to undesired switching. MECL noise margin
is defined in terms of the specification points
surrounding the switching threshold. The critical
parameters of interest here are those designated with
"'Complete data sheets for MECL I functions are not included
because this line is recommended only for replacement
purposes. However, such data sheets are available and can be
by contacting your nearest Motorola
representative.
obtained
1-12
A. Limits beyond which device life may be impaired:
FamilY
Symbol
Unit
~~~------~M~E~C~L~II~A~~M~E~C~L~I~II~--7M=E~C~L~10~.~OOO~'
'MECL
I
Power Supply Voltage (VCC
VEE
Vdc
-10toOV
-10toOV
-8 to 0 V
-8 to 0 V
B.... Input Voltage (VCC
Vin
Vdc
0'0 VEe
o to Vee
o to vee
<20
<20
<40
o to VEE
5
5
o
~
>
50!1 Load
-0.2
...
C)
0(
+0.2
/I
0(
'JVEE' -J.6V
IoJ
1j-4.4V
5.2 V
6.0 V
-1.6
-1.2
-O.B
-0.4
~
-1.1
C)
0(
-1.3
...
TA
-2.B
-2.4
IoJ
o
>
~
-1.5
..55
o
;
-1.7
-1.9
-2.1
>0
I'--
)
"-
IoJ
-1.4
= 2SoC
-0.4
0
-0.7
<.:>
5.2 V
......
I::l
-1.7
-1.9
::l
TA
:::z
+25 0 C
0
50
>
-1.0
-O.S
w
It
~~ -B.OIV
-2.3
-1.B
-1.2
-0.9
0
4.4 V
V
-1.6
~ -1.1
-6.0V
I-- "~-7.0
-2.0
Vin.INPUT VOLTAGE (VOLTS!
u;
3.6
~
FIGURE 9b - MECL 111/10,000 "NOR"
iff
J Y. i"-
-
-2.2
-3.0
-3.2
0
-0.6
-0.2
0
-2.1
-2.3
-l.B
-1.4
-1.0
-0.2
-0.6
Yin. INPUT VOLTAGE (VOLTS!
Vin. INPUT VOLTAGE (VOLTS)
FIGURE 9c - MECL II "OR"
FIGURE 9d - MECL II "NOR"
MEClll
0.015
0.230
0.115
Voltage
~VOH/~VEE
~VOl/~VEE
~VBB/~VEE
MECl10,OOO"
0.016
0.250
0.148
0
MEClll1
0.033
0.27
0.14
"and subsets: 10,200; 10,500; 10,600.
FIGURE 9a - LEVEL CHANGE RATES
LOGIC SWING VARIATIONS WITH TEMPERATURE AND SUPPLY VOLTAGE
1.60
~ 1.44 50
n
'to -2
J
oJ
o
1.28
C)
1.12
~
......,:::,;;
Z
i
0.96
!:1
0.80
III
C)
Beoe ...
g 0.64
.
>0. 0 .48 ~ ~
~
0.32
-3.6
.......-:: ~
....-::::: ~
rP'
~~
'-Jooe
25°C
-4.4
-5.2
-6.0
VEE. SUPPLY VOLTAGE (VOLTS!
0.2 '--_'--_-1._ _......._ _'--_ _......._ _-"
-3.0 -3.8
-4.4
-5.2
-8.0
-7.0
-8.0
VEE. SUPPL.Y VOL. TAOE (VOLTS)
FIOURE 1Gb - MECL 111/10.000
FIOURE 10. - MECL II
1-15
".
-6.8
--------Jr+
·1.475
·1.105
1l.V
= High .Noise
Margm
VOHA min
{
V,HA min
1High
VOHA min
------t.o
·0.980
JSt8te
.6.
Gate
Output
Gate
Input
·1.630
VOLA max
V
, Low
i State
V,LA max
Vas
VILAmax
= Low Noise {
Margin
VOLA max
NOISE
MARGIN COMPUTATIONS
V,HA min
(switching threshold)
Family
SPECIFICATION POINTS FOR
DETERMINING NOISE MARGIN
MECL II
~
~~
Guaranteed
Worst·Case de
Noise Margin
Typical de
Noise Margin
0.175/0.150'
0.250/0.200'
All MECL 10.000
0.125
0.210
MECL III
01 L and Flat Package
0.115
0.200
*Depending on part type. See selector gUide or data sheet.
MECL NOISE MARGIN DATA'
ELEMENT 2 NOISE MARGIN MEASUREMENT
POINTS FOR MECL GATES
FIGURE 11
the "A" subscript (VOHA min, VOLA max, VIHA
min, V ILA max) in the transfer characteristic curves.
Guaranteed noise margin (NM) is defined as
follows:
between the two specification voltages, or for the
MECL 10,000 levels shown:
NMLOW = VILA max' VOLA max
= ·1.475 V· (·1.630 V)
= 155 mV.
Similarly, for the HIGH state:
NMHIGH = VOHA min' VIHA min
= ·0.980 V . (·1.105 V)
= 125 mV
Analogous results are obtained when considering
the "NOR" transfer data.
Note that these noise margins are absolute worst
case cond itions. The lesser of the two noise margins is
that for the HIGH state, 125 mV. This then,
constitutes the guaranteed margin against signal
undershoot, and power or thermal disturbances.
As shown in the table, typical noise margins are
usually better than guaranteed - by about 75 mV.
Noise margin is a dc specification that can be
calculated, since it is defined by specification points
tabulated on MECL data sheets. However, by itself,
this specification does not give a complete picture
regarding the noise immunity of a system built with a
particular set of circuits. Overall system noise im·
munity involves not only noise·margin specifications,
but also other circuit·related factors that determine
how difficult it is to apply a noise signal of sufficient
magnitude and duration to cause the circuit to
propagate a false logic state. In general, then, noise
immunity involves line impedances, circuit output
impedances, and propagation delay in addition to
noise·margin specifications. This subject is discussed
in greater detail in Application Notes AN·298 and
AN·592.
NMHIGH LEVEL = VOHA min' VIHA min
NMLOW LEVEL = VILA max' VOLA max·
To see how noise margin is computed, assume a
MECL gate drives a similar MECL gate, Figure 11.
At a gate input (point B) equal to VI LA max, MECL
gate #2 can begin to enter the shaded transition region.
This is a "worst case" condition, since the VOLA
max specification point guarantees that no gate can
enter the transition region before an input equal to
VI LA max is reached. Clearly then, VI LA max is one
critical point for noise margin computation, since it is
the edge of the transition region.
To find the other critical voltage, consider the
output from MECL gate #1 (point A). What is the
most positive value possible for this voltage (consider·
ing worst case gate specifications)? From Figure 11 it
can be observed that the VOLA max specification
insures that the LOW state OR output from gate 1
can be no greater than VOLA max.
Note that VOLA maxis more negative than VILA
max. Thus, with VOLA max at the input to gate #2,
the transition region is not yet reached. (The input
voltage to gate #2 is still to the left of VI LA max on
the transfer curve.)
In order to ever run the chance of switching gate
#2, we would need an additional voltage, to move the
input from VOLA max to VI LA max. This con·
stitutes the "safety factor" known as noise margin. It
can be calculated as the magnitude of the difference
1-16
AC OR TIME PARAMETERS
"conditions" associated with a particular parameter
may differ among logic families, the common MECL
waveform and propagation delay terminology are
depicted in Figure 12. Specific rise, fall, and propagation delay ti mes are given on the data sheet
for each specific functional block, but like the
transfer characteristics, ac parameters are temperature
and voltage dependent. Typical variations for the
MECL families are given in the curves of Figure 13.
Time dependent specifications are those that
define the effects of the circuit on a specified input
signal, as it travels through the circuit. They include
the time delay involved in changing the output level
from one logic state to another (t+; t-). In addition,
they include the ti me required for the output
of a circuit to respond to the input signal, des·
ignated as propagation delay. Since this terminol·
ogy has varied over the years, and because the
Undershoot
1
VIHA
t~~~~~~~~~~~~~.~i~~~~~~~H~i:9h~L~evel
VILA
Overshoot
50%
VBB
Undershoot
t
V out OR
Low Leval
-+
MECL WAVEFORM TERMINOLOGY
o%
Vout
~
10%
t--
t+
~
t+-
50%
20%
t-
-
t+ = tr
t- = tf
• Designated tpd· on older data sheets
•• Designated tpd+ on older data sheets
t+
t- .,.
MECL II, III RISE AND FALL TIMES
V out NOR
o%
Vout
~
tf
t+ "'" tr
MECL PROPAGATION DELAY
MECL 10,000 RISE AND FALL TIMES
FIGURE 12
2.6
]
2.5
~ I-sol n
LJad to l -2.0
~
_1+B5°
~ SOcj
:::;.. _30 0
I
>
OR
..: 2.4
.J
~ 2.3
~ 2.2
~ 2.1
..:
1-
t
1.9
t---
CL
1.8
~
1.7
1.6
~ 2.0
a:
---
NOR
-
r::-- .....
-~
I--
2.S
Jc
c
>
..:
.J
c
w
0
Z
I
l
2.1
2.0
1.9
0
1.8
:..
1.6
a:
t
-3.6
-4.4
-5.2
2.2
..:
C>
..:
..
.
sOei
30°C
2.3
9
....
8Soe
2.4 t - - t-so1n
3.7
w
~ 3.6
w
::;
3.5
~ 3.4
.J
.J
.....:
-
3.3
i'-..
I--
3.1
3.0
--r-
2.9
-3.6
-4.4
. / 8Soe
r-
-- 250~1
V
OA
__
30°C
1.S
-4.4
-S.2
-6.0
-6.8
FIGURE 13b - TYPICAL PROPAGATION DELAY t++-versus VEE and TEMPERATURE (MECL 10,000)
5.2
Load to -2.0 V
J'-..
_30 e
.......
• -Formerly designated tpd+
NOR
85 0
5.0
J
..
soc!
_30°C
I---
"
3.2
.n
r-r--
-I
25°,:1
o
VEE. SUPPLY VOLTAGE (VOLTS)
FIGURE 13a - TYPICAL PROPAGATION DELAY t··versus VEE and TEMPERATURE (MECL 10,000)
50
NJA
-3.6
• Formerly designated tpd-
3.8
./
I--
VEE. SUPPLY VOLTAGE (VOLTS)
3.9
85°C
r-
1.7
-6.8
-6.0
LO~d '°1_2 .0 Y
~
w
::;
4.8
4.6
r-:h.
-+--.-.
-S.2
-
t
8Soe
r---,~soei
-6.8
+-2.~
r
V
I
t::i-
T8s oe
-..,J25Oe
4.0
3.8
3.6
NiA
.........
1· 30oe
I
I
I
I
r--..
~ t-- - I -
OA
8SoC
-I-
25°C,
1.30°9
1
3.2
-3.6
VEE. SUPPLY VOLTAGE (VOLTS)
L10ad
"""'=:::I:::::::
3.4
1--..L'300e
-6.0
~I n
4.4
~ 4.2
w
!!?
a:
~
-4.4
-5.2
-6.0
-6.8
VEE,SUPPLY VOLTAGE (VOLTS)
FIGURE 13d - TYPICAL RISE TIME (10%to 90%)
_SUI TEMPERA TUR E and SUPPLY VO L TAG E
(MECL 10,100)
FIGURE 13c - TYPICAL FALL TIME (90%to 10%)
_sus TEMPERATURE and SUPPLY VOLTAGE
(MECL 10,100)
1·17
TYPICAL DELAY TIMES FOR MECL II FAMILY
7.S
-
r--.,.---r-----,--~---_._--___,
Input tT .. t- • 5.0 ns
Fen-out = 1
"'
+12SoC
~
+7S o C
j: 6.0 ~-+----I---
20
5.
+1250~ -..........
w
+750~~
~
"''"'+--'::O'......~£...-.---l
j:
>
«
>
w
w
«
-'
+2S0C,
OoC
10
-'
C
-SSoC
f'
Z
a
j:
~5.0
«
.."«c
"
~4.0~~~~~~~~~::::~::::::~~~~
__
-3.0
~
-3.6
____
~
____
-44
~
____-,-______
-S.2
-6.0
~
a:
Q.
t;.
-8.0
""
....,
,""X 'V/
/
~
A
...v
~
~
~-
I
2.0
-3.6
-4.4
-5.2
-6.0
- 7.0
-8.0
VEE. SUPPLY VOLTAGE (VOL TS)
FIGURE 131 - TYPICAL PROPAGATION DELAY
t++** versus TEMPERATURE and
SUPPLY VOLTAGE (MECL II)
11
7.0.----,----,-----,---,----,-----,
Input t+ = t- = 5.0 ns
Fan-out = 1
I
9.0
w S.O
:!
;:: 7.0
~
/
7'
FIGURE 138 - TYPICAL PROPAGATION DELAY
t- -* versus TEMPERATURE and
SUPPLY VOLTAGE (MECL II)
10
...
"0
>
........
z
Q
2.0
......
r-- ~
1.B
"'-........
........",.,
1.6
1.4
-3.6
-4.4
3.0
~
2.8
"""
~
-5.2
+12SoC
~
+250~
o
II:
-650~-
"-
J
+
-6.0
/
2.6
lL
2.4
...........
f--'
2.2
!.
-6.8
2.0
-3.6
~V
V
0
.;j5 C
-
-5.2
-4.4
1
-6.0
-6.8
•• Formerly designated tpd+
FIGURE 131 - TYPICAL PROPAGATION DELAY
t--* versus VEE and TEMPERATURE
FIGURE 13i - TYPICAL PROPAGATION DELAY
t++** venus VEE and TEMPERATURE
(MECL 10,500)
(MECL 10,500)
1.9
NOR
1.8
'"
1cio n
r----. 0
1.7
UJ
:;;
L~.d
to 1_ 2 .0
j: 1.6
1.5
2.2
V~c
'00
I
r-
~
r-... ~
..J
..J
«
u.
/
_55°C
/1
VEE,SUPPLY VOLTAGE VOLTS
-Formerly des;gnated tpd-
~
1
j:
«
(!)
1+1250~
/
VEE. SUPPLY VOLTAGE (VOLTS)
0
LO~d to -J.o Vd~
N6R
u!
o
II:
"-
100ln
3.2
«
I'---t-.,
2.2
....
«
t:l
«
"
o
7.4
«
..J
w
0
3.4
~2.0 V~C
~
.!.
2. 1
1
NOR
~
~
t
1.4
-5.2
-4.4
r--........
1.9
-6.0
1.8
II:
+2SOC
1.3
-3.6
-............
UJ
-550~-
-6.8
1.7
1.6
-3.6
Load Ito -2.ci Vd c
l""- t'-....
2.0
+125 0 C -
ri
r-- r--4.4
"'"f',.'\
~
.......
t--
-5.2
-55°C
~-
+12SoC
I
+25 0 C -
-6.0
1
-6.8
VEE,SUPPLY VOLTAGE (VOLTS)
VEE,SUPPLY VOLTAGE (VOLTS)
FIGURE 13k - TYPICAL FALL TIME
(80% to 20%) versus TEMPERATURE and
FIGURE 131 - TYPICAL RISE TIME (20% to 80%) versus
TEMPERATURE and SUPPLY VOLTAGE
(MECL 10,500)
(MECL 10,500)
SETUP AND HOLD TIMES
The tsetup and thold times are two ac specifications which can be confused unless clearly defined.
For MECL devices, tsetup is defined as the time
(50% - 50%) before a Clock transition that Data must
be present for a bistable circuit to "recognize" the
incoming Data.
The thold is similarly defined to be the time after the
Clock transition that Data must remain to insure that
bistable outputs retain their state.
In specifying devices, Motorola establishes and
guarantees values for tsetup and thold. The limits for
tsetup and thold insure proper logical function of
bistable circuits, but do not guarantee that propagation delay or noise specifications wi II be met under
all conditions when operating near the limits. For
MECL bistable circuits, proper device operation
usually occurs with Data present for somewhat less
time than that specified for tsetup and thold.
50%
D - - -J
50%
c---4--..J
tsetup
1-19
SECTION III - OPERATIONAL DATA
POWER SUPPLY CONSIDERATIONS
Output
Transistor
MECL circuits are characterized with the VCC
point at ground potential and the V EE point at -5_2
V_ While this MECL convention is not necessarily
mandatory, it does result in maximum noise immunity _ This is so because any noise induced on the
VEE line is applied to the circuit as a common-mode
signal which is rejected by the differential action of
the MECL input circuit_ Noise induced into the Vee
line is not cancelled out in this fashion_ Hence, a good
system ground at the Vce bus is required for best
noise immunity_
Power supply regulation of 10% or better is
recommended_ The -5.2 V power supply potential
will result in best circuit speed. Other values for VEE
may be used. A more negative voltage will increase
noise margins at a cost of increased power dissipation.
A less negative voltage will have just the opposite
effect.
On logic cards, a ground plane or ground bus
system should be used. A bus system should be wide
enough to prevent significant voltage drops between
supply and device and to produce a low source
inductance.
Although little power supply noise is generated by
MECL logic, power supply bypass capacitors are
recommended to handle switching currents caused by
stray capacitance and asymmetric circuit loading. A
parallel combination of a 1.0 /--IF and a 100 pF
capacitor at the power entrance to the board, and a
0.01 /--IF low-inductance capacitor between ground
and the -5.2 V line every four to six packages, are
recommended.
Most MECL 10,000 and MECL III circuits have
two Vec leads. Veel supplies current to the output
transistors and VCC2 is connected to the circuit logic
transistors. The separate VCC pins reduce cross·
coupling between individual circuits within a package
even when the outputs are driving heavy loads.
Circuits with large drive capability, similar to the
MC10ll0, have two Vee1 pins. The Vee pins should
be connected to the ground plane or ground bus as
close to the package as possible.
All MEeL II, MEeL III, and MECL 10,000 devices
have their own internal temperature and power-voltage-compensated bias voltage sources.
For further discussion of MECL power supply
considerations to be made in system designing, see
MECL System Design Handbook, Ch. 5.
Power
Terminating
Resistor Value
150 ohms to -2.0 Vdc
100 ohms to -2.0 Vdc
75 ohms to -2.0 Vdc
50 ohms to -2.0 Vdc
2.0 k ohms to VEE
1.0 k ohm to VEE
680 ohms to VEE
510 ohms to VEE
270 ohms to VEE
82 ohms to Vee and
130 ohms to VEE
Dissipation
(mWI
Terminating
Resistor
Power
Dissipation
(mWI
5.0
7.5
10
15
2.5
4.9
7.2
9.7
4.3
6.5
8.7
13
7.7
15.4
22.6
30.2
18.3
15
57.2
140
FIGURE 14 - TYPICAL POWER DISSIPATION
IN OUTPUT CIRCUIT WITH EXTERNAL
TERMINATING RESISTORS
system designer can compute total package power for
his particular termination technique by adding, IE x
5.2 + Output Device Power. Some of the devices in
the MECL I, II, and III Lines include on-chip
output pulldown resistors, so that adding termination power has already been accomplished. None of
the devices in the MECl 10,000 Series incorporate
internal output pulldown resistors.
The omission of these resistors permits the use of
external terminations designed to yield best system
performance. To obtain total operating power dissipation of a particular functional block in a system, the
dissipation of the output transistor, under load, must
be added to the specified power dissipation of those
circuits without internal termination.
The table in Figure 14 lists the power dissipation
in the output transistors plus that in the external
terminating resistors, for the more commonly used
termination values and circuit configurations. To
obtain true package power dissipation, one outputtransistor power-dissipation value must be added to
the specified package power dissipation for each
external termination resistor used in conjunction with
that package. To obtain system power dissipation, the
stated dissipation in the external terminating resistors
must be added as well. Unused outputs draw no
power and may be ignored.
The power dissipation of MEel functional blocks
varies with both temperature and VEE. Typical
variations are shown in Figure 15. The graph is
normalized so that it applies to all MEeL lines. The
reference temperature is 25°C and the reference
power is obtained by multiplying the typical IE value
(total power supply drain current specified on the
POWER DISSIPATION
The power dissipation of MEeL functional blocks
is specified on their respective data sheets. This
specification does not include power dissipated in the
output devices due to output termination. The
'-20
+1.0
3.0
J. - Lv
'~
"2.5
I
;::-
<•
L.!!
=~
'0&
2.0
I:~
~ ~1.5
Q '
wi
..J
5.2 V
:l~
-4~4
0:-
3.6V_
"~
-
-55
o
....
-
~ -1.0
:0
0_1.5
;
o
+25
+75
~
/-
~L
r
+126 0 C
2SOC
H
"-Issoc ,
VOH
~
+~2S0C
"
25°C
/
~
5SoC
>.
-
VOL I
VOL
-2.0
I
I
-2.5
+5.0
I
-25
r
-0.5
>
3.0 V
o
o
2!
V
Q
0.6
o
w
-7.0 V
I
~.::
1.0
.. >
......
r--
6.0 V
•
Z
;;;
1
W 0
L
Vee - -5.2 V
+0.5
(10
m •• j
-
- 5.0 - 10 -15 - 20 - 25
+125
30
35
- 40
LOAD CURRENT (mAl
T A. AMBIENT TEMPERATURE CDC)
FIGURE 168 - MECL II TYPICAL OUTPUT VOLTAGES
versus LOAD CURRENT and TEMPERATURE
FIGURE 15 - NORMALIZED POWER DISSIPATION
versus TEMPERATURE and SUPPLY VOLTAGE
+1. 0
Vee = -5.2 V
+0.
~...
data sheet) by VEE (5.2 V). For those devices where
only the maximum value of IE is specified on the
data sheet, nominal power dissipation is approximate·
Iy 80% of that calculated with the I E (max)
specification.
•
o
~
w
"«~
-0. 5
o
+7SoC
~r-- VOH
/
VOI
C
>
to- -1.0
:0
~
LOADING CHARACTERISTICS
:0
o
....
The differential input to MECL circuits offers
several advantages. Its common-mode·rejection
feature offers immunity against power-supply noise
injection, and its relatively high input impedance
makes it possible for any circuit to drive a relatively
large number of gate inputs without deterioration of
the guaranteed noise margin. Hence, dc fan·out with
MECL circuits does not normally present a design
problem.
The specified dc loading factors (the number of
gate inputs of the same family that can be driven by a
circuit output) for MECL I and MECL II families is
25. For MECL 10,000, it is 90; and for MECL III, it
is 70 or 7, depending on the input impedance of the
circuit (whether the system is implemented with
high-impedance or low-impedance devices).
Graphs showing typical output voltage levels as a
function of load current for MECL II, III, and 10,000
are shown in Figure 16. These graphs can be used to
determine the actual output voltages for loads
exceeding normal operation.
While dc loading causes a change in output voltage
levels, thereby tending to affect noise margins, ac
loading increases the capacitances associated with the
circuit and, therefore, affects circuit speed. The effect
of fan-out on MECL II speed is shown in the graphs
of Figure 17.
For MECL 10,000 and MECL III, best
performance at fan-outs greater than 10 and 6,
respectively, will occur with the use of transmission
lines.
-1. S
:0
~r-L- ---; V
v
H
v
L""::
1.<= .Loc
OOC
o
:> -2.0
F=
(10 m . . )
-2.5
5.0
+5.0
10
15
20
25
30
35
40
LOAQ CURRENT (mAl
FIGURE 16b - MECL II TYPICAL OUTPUT VOLTAGES
vemls LOAD CURRENT and TEMPERATURE O·C I!o +75·C
1-... 301-----i>--~'"
520~~~~~~+-~~-4~-*---*---+f-~
(LOAD LINES FOR TERMINATION TO VEE (-5.2 Vdcl250C
50
LHA
JI
40
VOH min
VOH
m~x J
~ 1I
200 Ohms
JOOOh~'
10
1K Ohm.
a :----2K
o
~
J••-vlA
I
I
I
I
I
I
I
I
I
1
VOl
rna.
l J0"L
moo
/
I
-
J
Ohm.
·0.5
1.0
1.5
2.0
VOUTCVOL TS)
FIGURE 16c- OUTPUT VOLTAGE LEVELS
versus DC LOADING, MECL III and MECL 10,000
1-21
10
I.
,n'put t1 = t· = 5.0 n.
Vee >= -5.2 V
30 -
;::;;-. ".....
--=="
:::;0-
;::;-55 0
~
I
4.0
10
I
I
]
E
2 SoC-..
20
;;;
~
ooJ ./
20
30
40
6
15
./..
10
8
50
60
10
12
FAN·aUT
70
80
90
100
16
18
20
14
,
~~
10
10
\
"- ·5SoC
r
I
~
r--
c
20
30 40
50
60
70
80
LOAD CAPACITANCE tpF)
8
10
12
14
16
90
100
18
20
FAN-OUT
.
~
>
~
6.0
FIGURE 17b - MEeL " FALL TIME versus
LOADING and TEMPERATURE,
(Single Pull-down Resistod
~
~
40
I""""
~
0
~
20
o
o
--- i~
20
,a
30
40
50
>
I--
-
I-- f.-
('-- o(
~
~
I-::::::
2',8
;
2. 6
IoU
2.4
~
2. 2
g
2.0
r-- ~o n
551°C
,"-- 2SoC
: \ ,lsoC I
'-rOCI
60
70
_
-
aD
90
'00
LOAD CAPACIT ANCE (pF)
6
B
10
12
14
16
FAN·OUT
18
20
°0~-'~0~~2~0~3~0~~40~~5~0~~60~~'~0~~~~~1~00
LOAD CAPACITANCE
6
1.8
1.6
~
1.4
I
4.0
6.0
B.O
6.0
~
5.5
I
j
I
I
~
5.0
.J
.J
4.5
~
I
,
,
I
2.0
]
~
I
1
12
14
16
18
20
6.5
t--
~
:
10
FIGURE 17d - MEeL" PROPAGATION DELAY t-versus LOADING and TEMPERATURE
I
t++
I
8
FAN·OUT
J J
Lood I
I
15~~--~--~--~-+~-p~+-~~~~~
o
FIGURE 17c - MEeL" PROPAGATION DELAY t++
versus LOADING and TEMPERATURE
3.0
20~-+--~--+-~---+--~--r-~---b~
~
-\ f.--
Z
o
1:7
tn~ut t+l= t. =150 n1
8.0
~
]
~
,"
~
Vee'" -5.2 v
]
-
~~
6
FIGURE 17a - MEeL" RISE TIME versus
LOADING and TEMPERATURE
~
'" ~ ~ ~
IY
~~~
,:
1./ /
LOAD CAPACITANCE (pF)
""
VV
,/
I
2.0
.J
/
(Single PulldOl/lln Resistor)
'5OC ........
I
w
0
I
125°C ........
5.0
w
~s
2.
,......,::;:f:::::::;-- -
6.0
~
~putt1
I
'" t· :. 50
Vee = ·5.2 V
~ ~~~
c
~
,:
35
l125l\
8.0
ii'
t-
.l
~
4.0
0
z
3.S
w
3.0
~
!!!
a:
i
I
I
I
I
I
10
12
14
16
18
..
t
20
2.5
-150 n l LOad l
-?
- -;.-
-
<:::
.;-
V
I
2.0
1.5
I
2.0
FANOUT (NUMBER OF GATE INPUTS)
f--:
4.0
6.0
8.0
10
12
14
16
18
20
FANOUT (NUMBER OF GATE INPUTS)
FIGURE 188 - MEeL 10,000 GATE PROPAGATION
DELAY TIME versus FANOUT (Fanout-at End of 14"
50 n Matched Transmission Linel
FIGURE 18b - MEeL 10,000 RISE and FALL TIME
(10% to 90%1 versus FANOUT (Fanout at End of 14" 50
Matched Transmission Linel
The propagation delay and rise time of a driving
gate are affected very little by capacitance loading
along a matched parallel-terminated transmission line_
However, the delay and characteristic impedance of
the transmission line itself are affected by the
distributed capacitance. Signal propagation down the
line will be increased by a factor,...; 1 + Cd/Co. Here
n
Co is the normal line capacitance, and Cd is the
distributed capacitance due to loading and stubs off
the line_
Maximum allowable stub lengths for loading off of
a MECL 10,000 transmission line vary with line
impedance_ For example, with Zo = 50 ohms,
maximum stub length would be 4_5 inches (1.8 in. for
'-22
MECL III). But when Zo = 100 ohms, the maximum
allowable stub length is decreased to 2.8 inches (1.0
in. for MECL III).
The input loading capacitance of a MECL 10,000
device is 2.9 pF (e.g. MC10l09). Therefore it is
recommended that non·transmission-line environment
fanout be limited to a maximum of 10 loads, due to
line delay increases which limit system speed.
The input loading capacitance of a MECL III logic
function is 3.3 pF. Therefore it is recommended
that non·transmission·line environment fanout be limi·
ted to a maximum of 6 loads.
Shown in Figure 18 are the effects of fanout on
MECL 10,000 time parameters.
reliable system operation. Most devices can use VEE
as the input return, but control inputs of series
reliable system operation. Most devices can use
VEE as the input return, but control inputs of
series gated devices such as the MC1019, MC1021,
MC1028, MC1035, MC1038, MC1045, and MC1066
should be returned to the VOL level. This protects
against voltage buildup on the unused inputs and
assures that noise immunity depends only on those
inputs actively used.
All single·ended input MECL 10,000 and MECL III
circuits contain input pull·down resistors between the
input transistor bases and VEE. As a result, unused
inputs may be left unconnected (the resistor provides
a sink for ICBO leakage currents, and inputs are held
sufficiently negative that circuits will not trigger due
to noise coupled into such inputs).
Input pull·down resistor values for the MECL III
high·impedance circuits and all MECL 10,000 devices
are typically 50 kn and are not to be used as
pull-down resistors for preceding open·emitter out·
puts.
Several MECL 10,000 devices don't contain input
pull·downs. Examples are the differential line reo
ceivers, MC10115 and MC10116. If a single dif·
ferential receiver of either device type is unused, one
input of that receiver must be tied to the VBB pin
provided, and the other input goes to VEE.
UNUSED MECL INPUTS
The input impedance of a differential amplifier, as
used in the typical MECL input circuit, is very high
when the applied signal level is low. Under low·signal
conditions, therefore, any leakage to the input
capacitance of the gate could cause a gradual build·up
of voltage on the input lead, thereby adversely
affecting the switching characteristics at low repeti·
tion rates.
For MECL I and MECL II circuits, the gate inputs
are essentially open. In use, therefore, any unused
inputs should be tied to a negative potential for
SECTION IV - SYSTEM DESIGN CONSIDERATIONS
/I JC = thermal resistance, junction to case
/lCA = thermal resistance, case to ambient
/I JA = thermal resistance, junction to ambient
Only two terms on the right side of equation (1)
can be varied by the user - the ambient temperature,
and the device case·to-ambient thermal resistance,
/lCA. (To some extent the device power dissipation
can be also controlled, but under recommended use
the VEE supply and loading dictate a fixed power
dissipation.) Hence, both system air flow and the
MECL package mounting technique affect the
thermal resistance term.
THERMAL MANAGEMENT
Circuit performance and long-term circuit reo
liability are affected by die temperature. Normally,
both are improved by keeping the IC junction
temperatures low.
Electrical power dissipated in any integrated cir·
cuit is a source of heat. This heat source increases the
temperature .of the die relative to some reference
point, normally the ambient temperature of 25°C in
still air. The temperature increase, then, depends on
the amount of power dissipated in the circuit and on
the net thermal resistance between the heat source
and the reference point.
the average temperature at the junction is a
function of the system's ability to remove heat
generated in the circuit - from the junction region to
the. ambient environment. The basic formula for
converting power dissipation to estimated junction
temperature is:
TJ
=
TA + Po (/lJC + /lCA)
OJA _ °CIWatt
IStillAir)
Package
°JC °CIWatt
Worst Case Typicat Worst Case
Ceramic Flat Pack
210
.166
60
Plastic Dual-In-line,
14 lead or 16 lead
(Gold Eutectic Die Bond)
150
100
70
Ceramic Dual-in-Line
14 or 16 lead
(Gold Eutectic Ole BondI
150
100
50
45'
10'
(Cerflat) 1I4x 1/4
(Gold Eutectic Die Bond)
(1)
or
Ceramic Dual-ln·Line
24 Lead
(2)
Plastic Dual-I n-Lme
where
24 Lead
T J = junction temperature
T A = ambient temperature
Po = calculated power dissipation
65··
"Data for 8200 SQ. mil die SIZe
0·500 If pm air flow
FIGURE 19"':" WORST CASE AND TYPICAL THERMAL
RESISTANCE RATINGS FOR SELECTED Ie PACKAG ES
1-23
Internally, thermal resistance of an integrated
circuit is a function of the package material and size,
and of the method used in bonding the IC die to the
package. For some standard IC packages, the worst·
case and typical thermal resistance values are given in
the table in Figure 19. In Figure 20, this basic data is
converted into a graph showing the maximum power
dissipation allowable at various ambient temperatures
for circuits mounted in the various packages, taking
into account the maximum permissible junction
temperature for devices packaged in plastic or ceramic.
These measurements are taken in still air.
The effect of air flow over the packages on 8 JA is
illustrated in the graph of Figure 21 for two different
mounting methods. This driven air flow reduces the
thermal resistance of the package, therefore per·
mitting a corresponding increase in power dissipation
without exceeding the maximum permissible junction
temperature.
As an example of the use of the information
above, the junction temperature for a quad MECL
10,000 gate loaded with ·four SO ohm loads can be
calculated. Typical total power dissipation (including
a load) for this quad gate is 164 mW. Assume for this
thermal study that air flow is 500 linear feet per
minute and that the device is soldered into a printed
circuit board. From Figure 21, curve #2, 8JA is
SOoCIW. With T A (air flow temperature at the device)
equal to 2SoC, the following junction temperature
results:
• 1200r---,---,---,---,----r--,
~
A
@:: 1000k--:-+- B
'" Ceramic Flat Package
-= Pla,tic Package.
3:
E
= Ceramic Dual In-Line
C
O~_~_~~~~_~_~~~
25
50
75
100
T A. Ambient Temperatur. (oC)
FIGURE 20 - AMBIENT TEMPERATURE
DERATING CURVE
100r---r--,r--,---.--~--r-~
Z A)(is
TJ
TJ
Package Tvpe - 1S-Lead Black CeramIc
Dissipation Le .... el - 200 mW
Air Flow - Z-Axis 2SoC·
Method - Calibrated Diode
Package Mounting #1 Barnes Socket
#2 Printed Circuit Board
.Ie
0.062" - 2 oz. Cu.
• x-axis air flow lowers 8 JA by SoC per watt.
FIGURE 21 - TYPICAL THERMAL RESISTANCES FOR
16-PIN BLACK CERAMIC DUAL IN·LINE PACKAGES
Pack_
Stud
Dual I n·Line
Low Power
Dual In·Line
High Power
(PD>500mW)
Ambient Condition
9JA
Copper heat si nk
37°C/W typ
MOUNTING and HEAT SINK SUGGESTIONS for
MECL.III
With large subnanosecond logic systems, the use of
multilayer printed circuit boards is recommended.
Such boards permit better ground planes and shorter
interconnection runs than single·layer boards and also
allow better use of stripline techniques.
MECL III circuits have an average power dissipa·
tion of approximately 60 mW per logic gate. Ade·
quate cooling should be provided to insure that
device junction temperatures do not exceed 110°C.
The dc data sheet specifications for MECL III are
given for an operating temperature range from -300 C
;;. 500 linear fpm blown air SOoC/W typ
Mounted in heat sink
and
500 linear fpm blown air
or
Mounted in heat sink
and
on printed circuit ground
plane using termal paste
8 JA + T A
(SOoCIW) + 2SoC = 33.2 °c
= (0.164 W)
Under the above operating conditions the MECL
10,000 quad gate has its junction elevated above
ambient temperature by only 8.2°C.
Ellen though devices on a printed circuit board
may each have different power dissipations, all will
have the same input and output levels provided that
each is subject to identical air flow and the same
ambient air temperature. This eases design, since the
only change in levels between devices is due to the
increase in ambient temperature as the air passes over
the devices, or differences in ambient temperature
between two devices.
AlA FLOW (LFPM)
4" )( 6"
= PD
35°C/W max
FIGURE 22 - THERMAL CONDITIONS FOR
DC SPECIFICATIONS - MECL III
'·24
to +850 C for the conditions described in the table
of Figure 22.
The designer may want to use MECL III under
conditions that vary from those given. The main
restriction facing the designer is that a few high power
dual in·line parts' dissipating typically 900 mW under
load require heat sinking to assure a 0 JA .;;; 350 C/W
which will keep iunction temperature below 1100 C.
The .Iow-power dual in-line parts may be used
without air and with higher 8JA. However, the
designer must bear in mind that junction temperatures will be higher for higher 8 JA, even though the
ambient temperature is the same. Higher junction
temperatures will cause logic levels to shift.
As an example, a 450 mW device operated at 8 JA
= BO°CIW shows a HIGH logic level shift of about
17.5 mV above the HIGH logic level when operated
with a 8JA = 50°CIW (level shift = 6TJ X 1.3
mVtC).
If logic levels of individual devices shift by
different amounts (depending on PD and 8 JA). noise
margins are somewhat reduced. Therefore, the system
designer must layout his system bearing in mind that
the mounting procedures to be used should minimize
thermal effects on noise margin.
The following sections on package mounting and
thermal characteristics are intended to provide the
designer with sufficient information to insure good
noise margins and high reliability in MECL III system
use.
thermal conduction and mechanical strength. Also,
mounting holes for low power devices may be
counter sunk to allow the package bottom to contact
the heat plane. This technique used along with
thermal paste will provide good thermal conduction.
Printed channeling is a useful technique for conduction of heat away from the MECL dual in-line
package when the device is soldered into a printed
circuit board. As illustrated in Figure 23, this heat
dissipation method could also serve as VEE voltage
distribution or as a ground bus. The channels should
terminate into channel strips at each side or the rear
of a plug-in type printed circuit board. The heat can
then be removed from the circuit board, or board
slide rack, by means of wipers that come into thermal
contact with the edge channels.
Top View
Ceramic Dual In-Line Package, Case 620
Pac:kage
MECL III low-power devices are specified with
OJA typically 50o CIW, and the high-power units (PD
> 500 mW} with 8JA equal to 35°CIW maximum. To
aid the designer in using the "L" (ceramic dual in-line}
package, curves and data showing thermal characteristics of the package are provided in Figure 21.
The use of multi-layer printed circuit boards is
recommended to provide both a ground plane and a
good thermal path for heat dissipation. Also, a
mUlti-layer board allows the use of microstrip line
techniques to provide transmission line interconnections.
Two-sided printed circuit boards. may be used
where board dimensions and package count are small.
If possible, the VCC ground plane should face the
bottom of the package to form the thermal conduction plane. If signal lines must be placed on both
sides of the board, the VEE plane may be used as the
thermal plane, and at the same time may be used as a
pseudo ground plane. The pseudo ground plane
becomes the ac ground reference under the signal
lines placed on the same side as the VCC ground
plane (now on the opposite side of the board from
the packages). thus maintain ing a' microstrip signal
line environment.
Two-ounce copper board i.s recommended for
Ceramic
Dual-In-Line
Flat
Spacing (Inchs,)
Cy
Cz
Cx
0.5
0.2
0.9
0.4
0.08
0.45
Side View
FIGURE 230 - TYPICAL MECL IIilMECL 10,000
CIRCUIT BOARD SPACING
FIGURE 23b - CHANNEL/WIPER HEAT SINKING ON
DOUBLE LAYER BOARD USED WITH MECL III
°i.e. MC1654. MC167B. MC1694, etc.
1-25
For the high-power devices requiring (}JA of
less than 350 C/W, a suitable heat sink is the
IERC-LlC-214A2WCB shown in Figure 24. The heat
sink should have a minimum of 500 Ifpm blown air
or be mounted directly on the copper ground plane
(using silicone paste) if used in still air, to meet the
350 C/W maximum rating. (See IERC Data Sheet for
lIC-214A2WCB.) The heat sink shown allows easy
access to the dual in·line IC pins for connection to
Microstrip line.
Air Flow
The majority of MECl III users employ some
form of air-flow cooling. As air passes over each
device on a printed circuit board, it absorbs heat from
each package. This heat gradient from the first
package to the last package is a function of the air
flow rate and individual package dissipations. Figure
25 provides gradient data at power levels of 200 mW.
250 mW, 300 mW, and 400 mW with an air flow rate
of 500 Ifpm. These figures show the proportionate
increase in the junction temperature of each dual
in-line package as the air passes over each device. For
higher rates of air flow the change in junction
temperature from package to package down the air
stream will be lower due to greater cooling.
(For further discussion of Thermal Management in
MECl systems, see MECl System Design Handbook,
Ch.6.)
FIGURE 24 - MECL III HIGH-POWER DUAL IN-LINE
PACKAGE MOUNTING (With Heat Sink, in 500 Ifpm of Airl
COMPATIBILITY AMONG MECL FAMILIES
Power Dissipation
Junction Temperature Gradient
(mWI
(OC/Package I
200
250
300
400
0.4
0.5
0.63
0.88
MECL circuits are designed to interface with each
other over a power supply voltage range of ±10%
from the nominal -5.2 V without loss of noise margin
(other than that due to reduced signal swing at low
voltage). However, if two circuits are at different
supply voltages or on the same power supply with a
voltage offset between circuits, there will be a
predictable loss of noise margin.
The MECL 10,000 logic family was designed to be
directly level compatible with the MECL III logic
family in dual in-line packages. The MECL II family
has somewhat higher output levels but is compatible
with the faster MECl 10,000 and MECL III inputs
when MECL II is loaded with the resistor pair, shown
in Figure 26. The resistor combination insures full
noise margin in the logic LOW level. An alternate
approach is to use a single 510 ohm resistor to VEE
on the MECl II output, but some loss of noise margin
takes place. Conversely, lightly loading the MECL
10,000 or MECL III outputs with a 1.5 kD resistor
raises the output logic levels to meet MECL II
requirements. MECL II will operate directly with
MECL 10,000 and MECL III, but there is a loss of
noise margin (at the interface point only).
Devices mounted on 0.062" PC board with Z aXIs spacing of
0.5". Air flow is 500 'fpm along the Z axis.
FIGURE 25 - THERMAL GRADIENT OF
JUNCTION TEMPERATURE
U6-Pin MECL Dual In·Line Packagel
MECL II'
6n
MECL 10.000
orMECLII'
~
1.5 k
MECL 10000
or MECL "'
VEE
MECL II
~
• no internal 1.5
kn
pulldown resistor
FIGURE 26 - INTERFACING MECL II TO
MECL III OR MECL 10,000
'-26
INTERFACING MECL to SLOWER LOGIC TYPES
~
MECL circuits are interfaceable with most other
logic forms. For MECLlMTTLlMDTL interfaces, when
MECL is operated at the recommended -5.2 volts and
TTL/DTL at +5 V supply, currently available translator circuits, such as MC10124 and MC10125, may
be used.
For systems where a dual supply (-5.2 V and + 5
V) is not practical, a discrete-component translator
can be designed. For details, see MECL System
Design Handbook, Ch. 8. Such circuits can easily be
made fast enough for any available TTL.
MECL also interfaces readily with MOS. With
CMOS operating at +5 V, any of the MECL to TTL
translators works very well. On the other hand,
CMOS will drive MECL directly when using a
common -5.2 V supply. P-channel MOS, operating
with a negative supply, requires simple translators to
equalize the differing logic levels.
Specific circuitry for use in interfacing MECL
families to other logic types is given in detail in
Chapter 8 of the MECL System Design Handbook.
Complex MECL 10,000 functions are presently
available to interface MECL 10,000 with MOS
logic, MOS memories, TTL tri-state circuits, and
IBM bus logic levels.
·5.2 V
(a)
~
(b)
~
(c)
·2.0 V
Rp
·5.2 V
FIGURE 27 - PULL-DOWN RESISTOR TECHNIQUES
power and load requirements (see MECL System
Design Handbook, Ch. 3). Power may be saved by
connecting pull-down resistors in the range of 50
ohms (100 ohm minimum for MC10,500 and
MC10,600 Series parts) to 150 ohms, to -2.0 Vdc, as
shown in Figure 27(b). Use of a series damping
resistor, Figure 27(c), will extend permissible lengths
of unmatched-impedance interconnections, with
some loss of edge speed.
With proper choice of the series damping resistor,
line lengths can be extended to any length', while
limiting overshoot and undershoot to a predetermined amount. Damping resistors usually range in
value from 10 ohms to 150 ohms, depending on the
line length, fanout, and impedance. The open emitterfollower outputs of MECL III and MECL 10,000 give
the system designer all possible line driving options.
CIRCUIT INTERCONNECTIONS
Though not necessarily essential, the use of multilayer printed circuit boards offers a number of
advantages in the development of high-speed logic
cards. Not only do multi-layer boards achieve a much
higher package density, interconnecting leads are kept
shorter, thus minimizing propagation delay between
packages. This is particularly beneficial with MECL
III which has relatively fast (1 ns) rise and fall times.
Moreover, the unbroken ground planes made possible
with multi-layer boards permit much more precise
control of transmission line impedances when these
are used for interconnecting purposes. Thus multilayer boards are recommended for MECL III layouts
and are justified when operating MECL 10,000 at top
circuit speed, when high-density packaging is a
requirement, or when transmission line interconnects
are used.
Point-to-point back-plane wiring without matched
line terminations may be employed for MECL interconnections if line runs are kept short. At MECL II
speeds, this applies to line runs up to 12 inches, for
MECL 10,000 up to 8 inches, and for MECL III up to
1 inch (maximum open wire lengths for less than 100
mV undershoot!. But, because of the open-emitter
outputs of MECL 10,000 and MECL III circuits,
pull-down resistors are always required. Several ways
of connecting such pull-down resistors are shown in
Figure 27.
Resistor values for the connection in Figure 27 (a)
may range from 270 ohms to 2 kn depending on
I----tpd - - - - - l
B
FIGURE 29. - PARALLEL TERMINATED LINE
~r=:) Rlf.~D=::J--)
Zo
R2
·5.2 V
fiGURE 29b - PARALLEL TERMINATION THEVENIN eQUIVALENT
• Limited only by line attenuation and
bandwidth characteristics.
1-27
~:t--c;=
Ap
l
VEE
A
8
c
"':+-r'L~-_-_-_-_~-_-_"i______.J 50%
FIGURE 31 - TWISTED PAIR LINE DRIVER/RECEIVER
FIGURE 30 - SERIES TERMINATED LINE
For board to board interconnections, coaxial cable
may be used for signal conductors. The termination
techniques just discussed also apply when using coax.
Coaxial cable has the advantages of good noise
immunity and low attenuation at higR frequencies.
No significant performance degradation occurs for
lengths up to 20 feet for MECL III, and up to 50 feet
for MECL 10,000.
Twisted pair lines are one of the most popular
methods of interconnecting cards or panels. MECL
complementary outputs are connected to one end of
the twisted-pair line, and a differential line receiver to
the other as shown in Figure 30. RT is used to
terminate the twisted pair line. The 1 to 1.5 V
common-mode noise rejection of the line receiver
ignores common·mode cross-talk, permitting multiple
twisted pair lines to be tied into cables. MECL signals
may be sent very long distances (> 1000 feet) on
twisted pair, although line attenuation will limit
bandwidth, degrading edge speeds when long line runs
are made.
One major advantage of MECL over saturated
logic is its capability for driving matched-impedance
transmission lines. Use of transmission lines retains
signal integrity over long distances. The MECL III and
MECL 10,000 emitter·follower output transistors will
drive a 50·ohm transmission line (100 ohms or greater
for MECL 10,500 and MC10,BOO Series) terminated
to ·2.0 Vdc. This is the equivalent current load of 22
mA in the HIGH logic state and B mA in the LOW
state.
Parallel termination of transmission lines can be
done in two ways. One, as shown in Figure 28(a),
uses a single resistor whose value is equal to the
impedance (Zo) of the line. A terminating voltage
(VTT) of ·2.0 Vdc must be supplied to the
terminating resistor.
Another method of parallel termination uses a pair
of resistors, Rl and R2. Figure 28(b) illustrates this
method. The following two equations are used to
calculate the values of R 1 and R2:
Rl
=
1.B Zo
-D
R2=Rl'Zo
Rl + Zo
~ 1000'
Limited by Cable Response
Only, Usually> 1000'
Limited by Cable Response
Only, Usually> 1000'
>25%
>50%
>75%
Yes
Yes
Not recommended
-
Yes
MSI/LSI Parts
Maximum Twisted Pair Length
(Differential Drive)
No
Yes
(Wire·OR)
The Ground Plane to Occupy
Percent Area of Card
Wirewrap may be used
Compatible with MECL 10,000
With
proper I ntertace
*Some devices may not be connected to VEE; see specific data sheet Information.
1-31
PACKAGE OUTLINE DIMENSIONS
A letter suffix to the MECL logic function part number is used to specify the package style (see drawings below).
See appropriate selector guide for specific packaging available for a given device type.
L SUFFIX
CERAMIC PACKAGE
CASE 620
F SUFFIX
CERAMIC PACKAGE
CASE 607·04
INCHES
MA.
MILLIMETERS
DIM
A
C
D
f
Ii
DIM MI.
Mil IMETERS
......
MAlt
S.10 S.!!!
A
•
076
203
0.250.41
0.08 015
1 2165C
013 089
C
0
•
..
, ''"
G
H
J
181(1
O.2!'!
1.62
OJOO
K
L
M
0
•
MA'
19.05 19.81
6.98
6.22
4.116
.111
0.51
0.38
1.85
1.40
2.54 ISC
1.14
0.51
0.30
0.20
4.06
3.18
1.31
7.87
0.51
'"
1.02
MIN
NOTES:
1 lEADS WITHIN 0.13 mm (O.DOS) RADIUS
0.780
0.245 0.215
0.160 0._
0.015 0.020
o.os. 0....
o.l00RSC
0.020 0.045
0.008 0.012
0.125 0.160
Q.150
-
0.020
OF TAUE POSITION AT SEATING PLANE
2 AT MAXIMUM MATERIAL CONDITION'
PKG. INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT'
3 DIM "t" TO CENTER OF LEADS
WHEN FORMED PARALLEL'
0.31
",
0.040
L SUFFIX
CERAMIC PACKAGE
CASE 632-02
L SUFFIX
CERAMIC PACKAGE
CASE 623
.
.
~
~
~
1
-1l-oJ
f
r- A-L.l
~-1c
DIM
M lIMET RS
MI.
MU
.,.
31.Z4
1.Z30
••
• ..
••
I.
C
D
J
K
L
32.21
13.1Z
..
.41
1.27
1.52
U4BSC
0.20
D."
..IS.248SC.. ..D.
M
•
•0.1
JIH" ~ I\I~~J~
INCME
D.'
0.016
aulD
0.1
0.0111
D.
[L
H~-lGf--
•• x
1.210
D.
D.
.020
0.060
C
DIM
..
A
B
C
asc
0
F
G
"
J
K
L
M
NOTES:
1. DIM "l" TO CENTER OF
LEADS WHEN FORMED
PARALLEl.
M
P
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
(WHEN fORMED PARALLEL)
SEATING K
PLANE
MILLIMETERS
MIN MAX
16.S
19.9
0.660
5.59
7.11 0.220
5.08
0.3SI 0.584
0.77
1.77
2.54 BSC
0.203 0.3SI
2.54
7.62 SSC
15"
0.51
0.76
8.25
NOTE, OIMENSION "L" TO CENTER OF
LEAOS WHEN FO RMED PARALLEL.
'-32
U
11_
J-,r-
PSUFFIX
PLASTIC PACKAGE
CASE 646
MllllMETlRS
DIM
MIN
MAX
A
18.16
610
4.06
0.38
18.80
660
4.57
•
•
C
f
0.51
H
1.02
152
254 lise
1.83
132
J
0.20
0.30
292
7.31
3.43
G
•
l
M
P
051
.13
Q
0.51
N
7.81
10'
102
0.38
0.76
iNCHt$
MAX
MI'
0740
0.715
0.240
0.160
0.015
~
0.180
0.040
0.060
0.052
0008
0.115
0.290
0.012
0.012
0.135
PSUFFIX
PLASTIC PACKAGE
CASE 649
NOTES
1 LlAOSWITHINO 13mm
(DOO~I
Dlooese
0.020
.0005
0020
RAOIUS
O~
TRUE
POSITIONATS(AT1NG
PLA/riEAT IoIAXIMUM
MATEAIAlCONOITION
2 DIMENSiON "l" TO
CHHEAOFUAOS
WH(NfORMED
PARAllEL
0.020
0.310
10'
0.040
0015
D.OlD
O"n~""o"
I~'n\.~
l In IUd C'''tf,I" .. ",h."
ga,an,1
F SUFFIX
CERAMIC PACKAGE
CASE 660
P SUFFIX
PLASTIC PACKAGE
CASE 648
MllliMITlHS
INCH(S
DIM
MIN
MAX
MIN
MA-~
A
20.10
2134
oel~
08~
B
610
6.60
02UJ
0160
ON UAOOROoro .. COvl P
III
,
0300008
3430115
lBl0190
100
0012
13
310
100
0 ~1
0.13
1.02
alB
0
051
01600200030
292
131
0
OOO!l
TOTAtOFTRuEPOSITlf)NAT
I OIM"L"TO CfNTEIIOf LEADS
WHENFOAMEO
PAR~LlEL
94 •
l
, •
I "
~OTES
j
~~"]-,],~:TI'11~(
lor
1. _.
HI-
_7--1
IN
~,~~~~~~.~
__~I_==_==K==~I~;
J
,I
I
c
f·
L SUFFIX
CERAMIC PACKAGE
CASE 690·05
MILLIMETERS
DIM
A
C
0
F
G
H
J
K
L
M
N
MIN
MAX
1S.80 19.23
2.79 3.S1
0.41 0.51
1.14 1.52
2.54 sse
0.33 0.S9
0.20 0.30
3.56 4.06
762 sse
10"
0.76
1.14
INCHES
MIN
MAX
0.740 0.757
0.110 0.150
0.016 0.020
0.04
.06(1
O.IIM sse
0.013 0.035
0.008 0.012
0.140 0.160
0.300 sse
10'
0.030 0.045
NOTES.
I. LEADSWITHtN 0.13 mm !0.0051 RAOIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.
1-33
0310
0245 0260
0060 aDA'
0015 0019
0.003 0006
00508
0.025 0035
0250 OJ
0.145
-
• "
G
H
,
INCHES
MAK
MI'
1016
2.03
f
'.lAXI'.lUMMAHRIAl COlo,01111".
.., ."
MILLIMETER
MIN
MAX
622
152
OJ,
C
1 LEAf)SWITIiIt.jO II n'''''O 005'
{~~~h;J~h~~~
f+~4B~r~O_~o~
oro
·"
A
1 LEAOt.lO ttOE'ltTlflE08¥!A8
~+-~ ~+: ~~--WafH-~JD!
J
K
L
M
OIM
~OTES
01.
'D1B ""
.64 '.5."'
.
1892
-
-
.38
"'00
-
0015
SECTION V - MECL LITERATURE
Application Note Abstracts
(Application notes are available from Motorola Inc.
at P.O. Box 20924, Phoenix, Arizona 85036)
AN-417A
"ICCrystal Controlled Oscillators"
Crystal controlled square wave oscillators can be used
as clock drivers, harmonic sources for frequency
markers, in frequency synthesizers, frequency comparators, etc_ It is difficult to obtain high frequency
square waves due to the long propagation delays of
most integrated circuits_ MECL 10,000 circuits with 2
ns propagation delays eliminate this problem_ This
note describes square wave oscillator circuits with
crystal control that are capable of output frequencies,
inverted and non-inverted, up to 200 MHz_
Exclusive-OR gates and parity trees available in the
MRTL, MTTL, MOTL, and MECL families to design
simple parity and single error Hamming parity detection and correction circuits is discussed.
AN-504
"The MC1600 Series MECl III Gates"
This application note explains the basic operation of
the various gates available in the MECL III logic
family. Typical operating characteristics are included
as an aid to the designer of high-speed logic along
with recommended layout, breadboarding, and testing procedures. This note will also provide the
designer with some insight into the overall capabilities
of this logic line as they apply to this application.
AN-418
"High Speed Monostable Multivibrators
Design with MECL Integrated Circuits"
This note describes two configurations of monostable
multivibrators using the MC1023 clock driver and a
delay element_ Operating frequencies in excess of 70
MHz and pulse widths of 4 nanoseconds are possible.
Methods of obtaining the predetermined delay are
also discussed.
AN-532-A
"MTTL and MECl
Avionics Digital Frequency Synthesizer"
This application note discusses several approaches
that illustrate applications of complex digital integrated circuits directed toward avionics frequency
synthesizers. The techniques presented point out the
simpliCity with which both MTTL and MECL digital
integrated circuits can be used to produce frequency
synthesis for avionic communications.
AN-487
"A High-Speed Ripple-Through
Arithmetic Processor"
A simple, systematic building block approach for
designing a high-speed, ripple-through arithmetic
processor is described. Using only gates and full
adders, ultra-high speed multiplication, division,
square root extraction, addition, and subtraction may
be performed. Several variations of an arithmetic
processor design are detailed and comparisons of
speed and package count using the MECL and MDTL
logic in l4-pin, l6-pin, 24-pin, 32-pin, and 64-pin
packages are given.
AN-534
"Com mutating Filter Techniques"
This note describes the design and construction of
commutating (digital) filters using Motorola MECL II,
MTTl III and MC7400 digital integrated circuits. A
short section on commuting filter theory is included
along with examples of filters and their responses.
AN-536
"Micro-T Packaged Transistors
for High Speed logic Systems"
Integrated circuits have become the first thought of
most designers faced with a digital problem. For
specialized needs such as extremely high speed, high
speed with minimum power dissipation, or unusual
logic functions, however, discrete transistors in the
ultra-small Micro-T package may prove advantageous.
AN-488
"High-Speed Addition
Using Lookahead Carry Techniques"
The use of the lookahead carry principle to increase
the operating speed of adder systems is described.
Several adders of different sizes using variations of
lookahead carry are developed and the logical
implementation of these using the MTTL III and
MECL II logic families is given.
AN-553
"A New Generation of
. Integrated Avionic Synthesizers"
The need to generate signals of a multitude of
different frequencies for avionic systems has resulted
in complex solutions in the past. With the introduction of certain standard product integrated circuits,
frequency synthesis using digital phase locked loop
techniques presents a more practical solution. Several
different types of servo phase locked loop systems are
AN-496-A
"Error Detection and Correction
Using Exclusive-OR Gates and Parity Trees"
The availability of Exclusive-OR gates and parity
trees allows digital system designers to use error
detection and correction codes to improve their
system reliability and maintainability without the
major cost penalty that has existed in the past. Use of
1-34
(Application notes are available from Motorola Inc.
at P.O. Box 20924, Phoenix, Arizona 85036)
APPLICATION NOTE ABSTRACTS(continuedl
discussed and a practical design example is given.
Results of design examples are presented along with
possible applications.
AN-581
"An MSI 500 MHz Frequency
Counter Using MECl & MTTl"
The design of an MSI a-digit lED readout 500 MHz
counter using MECl III, MECl 10,000 and TTL is
discussed. Described are two prescalers using MECl,
along with the designs for two input amplifiers. A
unique time-base controller is also shown for
providing a multiphase clock to the counter.
AN-556
"Interconnection Techniques
for Motorola's MECl 10,000 Series ECl"
This application note describes some of the characteristics of high speed digital signal lines and gives
wiring rules for MECl 10,000 emitter coupled logic.
The note includes discussions of printed circuit board
interconnects, board-to-board interconnects, and
wirewrapping techniques.
AN-583
"A MECl 10,000 Main Frame
Memory System Employing Dynamic
MMOS RAMS"
Thi.s application note describes the construction of a
dynamic MOS random access memory system that
employs MECl 10,000 for the memory control logic.
Considered in detail are the memory organization,
layout rules, interfacing, and generation of the
needed control signals.
AN-565
"Using Shift Registers
as Pulse Delay Networks"
This note discusses a high-speed clocked shift register
using MECl 10,000 flip-flops and employed as a
digitial incremental delay. The register may be
clocked with a frequency division counter to accom·
plish delay with increments as small as 7.5 ns. The
circuit, as developed, may be used for timing basic
computer decisions or as an adjustable digital delay
fine for pulses.
AN-584
"Programmable Counters Using the
MC10136 and MC10137 MECl 10,000
Universal Counters"
This application note describes operation of two
MECl 10,000 Universal counters, and their use in
high speed programmable counters. Circu it diagrams
and waveform traces are included.
AN-566
"High Speed Binary Multiplication
Using the MC10181"
With a MECl 4-bit arithmetic unit you can reduce
both package count and interconnections in a ripple
multiplier and achieve very fast multiply times.
AN-592
"AC Noise Immunity of MECl 10,000
Integrated Circuits"
This application note discusses ac noise immunity as
it relates to MECl systems. Test circuits for measuring
ac noise immunity are shown, and results to be
expected for typical MECl 10,000 circuits are
presented.
AN-567
"MECl Positive and Negative logic"
Either positive or negative logic assignments may
prove convenient to the MECl system designer. This
note describes the equivalences between the two
approaches and providing guides for converting
between them.
AN-700
"Simulate MECl System Interconnections
With A Computer Program
Circuit interconnections are an important part of
system design when using high speed logic circuits.
The design of interconnecting paths affects both system speed and system accuracy. This application note
describes the use of a computer program to simulate
interconnections for high speed digital systems.
AN-579
"Testing MECl 10,000
Integrated logic Circuits"
Circuit testing techniques become increasingly important as circuit speeds approach and exceed the 2
ns range. With MECl 10,000 and MECl III circuits it
is possible to exploit their 50-ohm output drive
capability to obtain highly accurate test data. This
application note describes techniques for testing
MECl 10,000 circuits for laboratory evaluation, and
discusses key parameters which should be measured
during incoming inspection rapid testing_
AN-701
'-Understanding MECl 10,000 DC and AC
Data Sheet Specifications"
The dc and ac specifications for emitter-coupled logic
are somewhat different than those for saturated logic.
This application note describes the specifications
found on a MECl 10,000 data sheet and provides
information for understanding these specifications for
persons unfamiliar with emitter-coupled logic.
'-35
(Application notes are available from Motorola
APPLICATION NOTE ABSTRACTS (continued)
at P.O. 60·x 20924, Phoenix, Arizona 85036)
AN-709
"MECL 10,000 Arithmetic Elements
MC10179, MC10180, MC10181"
The MECL 10,000 arithmetic functions include a
4-bit arithmetic unit, a dual adder/subtractor, and a
lookahead carry block. This application note describes
the devices and shows their operation in large system
configurations.
AN-720
"Interfacing With MECL 10,000"
This article describes some of the MECL circuits used
to interface with signals not meeting MEGL input or
output requirements. The characteristics of these circuits such as; input impedance, output drive, gain,
and bandwidth allow the system designer to use these
parts to optimize his system. MEGL interface circuits
overcome a problem area of many system designs,
which is the efficient coupling on non-compatible signals.
AN-726
"Bussing With MECL 10,000
Integrated Circuits"
High speed data bus lines are an important part of
modern computer systems. Features of the MEG L
10,000 family allow construction of data busses in a
transmission line environment. This application note
describes some of the guidelines to consider when
designing high speed bus lines and shows how the
MG10123 can be used for maximum bus performance.
1-36
SUPPLEMENTARY LITERATURE
1. "The Case for Emitter·Coupled Logic," by
Anthony A. Vacca, ELECTRONICS, April 26,
1971.
2. "Low Power ECL Bids for TTL Applications,"
by Ed Tynan, ELECTRONIC PRODUCTS, May
17,1971.
3. "High·Speed Translators Simplify ECL/TTL
Interface ," by Bill Blood, COMPUTER
HARDWARE, July 15, 1971.
4. "Speedup in ECL," by John Rhea,
ELECTRONIC NEWS, September 13,1971.
5. "Generate Stable High·Frequency Signals With
Digital Mixers and Phase Locked Loops," by R.
Treadway and l. J. Reed, ELECTRONIC
DESIGN, January 6, 1972.
6. "ECL vs. Schottky," Special Report by John
Rhea, ELECTRONIC NEWS, March 13, 1972.
7. "ECL Gates Stretch Oscillator Range," by W.
Blood, ELECTRONICS, March 13, 1972.
B. "ECL - Who's Leading the Band?" by Sheldon
Edelman, THE ELECTRONIC ENGINEER,
April 1972.
9. "ECL Arithmetic Unit Performs High·Speed
Binary Multiplication," by Tom Balph, EDN,
May 1, 1972.
10. "Measure Frequency and Propagation Delay with
High Speed ECL Circuits," by William R. Blood,
Jr., EDN, July 1, 1972.
11. "Use ECL 10,000 Layout Rules to Help Solve PC
Board I nterconnections, Part I," by Tom Balph,
ELECTRONIC DESIGN, August 17, 1972.
12. ibid, Part II, ELECTRONIC DESIGN, September
2,1972.
13. "ECL/MOS for Optimum Minicomputer
Systems," by P. Breedlove, COMPUTER
DESIGN, August 1972.
15. "Boost Counting Speed to 110 MHz with ECL
Universal Counters", by Tom Balph and Howard
Gnauden, ELECTRONIC DESIGN, April 1, 1973.
16. "Digital Alphabet Spells Change in IC Usage" by
Ed Tynan, ELECTRONIC BUYERS NEWS,
October 2, 1972.
17. "ECL Shift Registers make Versatile Pulse Delay
Networks", by Jon DeLaune, EDN, October15,
1972.
lB. "Testing MECL 10,000 - What it Takes to Get
High on Speed," by Bill Blood, ELECTRONIC
PRODUCTS, November 20, 1972. (AN·579)
19. "Blend ECL and TTL ICs to Obtain High Fre·
quency Counter Circuits," by Jon DeLaune,
ELECTRONIC DESIGN, March 15, 1973, page
112.
20. "Leapfrog Ahead with Standard Family MSII
LSI," by Bob Cushman, Special Features Editor,
EDN, April 5, 1972, page 30.
21. "Positive versus Negative Logic," by Tom Balph,
Electronic Products Magazine, August 21, 1972.
22. "Improve Fast·Logic Designs," by Bill Blood,
Electronic Design, May 10, 1973.
23. "Use ECL for Your High·Speed Design - Part I,"
by lloyd Maul, EDN, July 20, 1973.
24. "ECL 10,000 Layout and Loading Rules Part II," by lloyd Maul, EDN, August 5, 1973.
25. "Interface TTL Systems With ECL Circuits," by
George Adams, EDN, September 5, 1973.
26. "MECL 10 K Reliability Evaluation," by Paul
Greer, Electronic Buyers' News, November 26,
1973.
27. "Make Sure Your Logic Keeps Pace With Mem·
ory Cycle Times" by Dick Brunner, EON,
January 20, 1973.
2B.
14. "Testing MECL 10,000 - What it Takes to Get
High on Speed", by Bill Blood, ELECTRONIC
PRODUCTS, November 20, 1972.
'·37
"Increasing Minicomputer Speed With Emitter·
Coupled Logic" by Jon DeLaune, COMPUTER
DESIGN, February 1974.
Contents of the MECL SYSTEM DESIGN
HANDBOOK (206 pages):
CHAPTER 1 - MECL Families
The Basic MECL Gate
Noise Margin
MECL Circuit Types
MECL Flip-Flops
Operation of Flip-Flop
MECL Family Comparison
CHAPTER 6 - Thermal Considerations
MECL Integrated Circuit Heat Transfer
MECL DC Thermal Characteristics
Heat Dissipation Techniques
Mounting Techniques
CHAPTER 7 - Transmission Line Theory
Transmission Line Design Information, With
Examples
Signal Propagation Delay for Microstrip and Strip
Lines With Distributed or Lumped Loads
Microstrip Transmission Line Techniques,
Evaluated Using TOR Measurements, with
Examples
The Effect of Loading on a Parallel-Terminated
Transmission Line, With Examples
Analysis: Series Terminated Lines Compared to
Parallel Terminated Lines, With Example
Analysis of Series Damping Terminations
Bibliography
CHAPTER 2 - Using MECL
MECL II Design Rules
A_ Logic Design Considerations
B_ System Layout Considerations
C_ Circuit Board Layout Techniques
D_ Backplane Wiring
E_ System Considerations
MECL 10,000 Design Rules
A_ General Considerations
B_ Printed Circuit Card Layout Techniques
C_ Power Supply Bypassing on Circuit Cards
D_ Backplane and Loading Considerations
E_ System Distribution and Grounding
F_ Loading Rules for MECL 10,000
CHAPTER 8 - MECL Applications
Counters
Shift Registers
Adders
Code Converters
Memories
Oscillators
One-Shot Mu Itivibrators
Linear Applications
Translators
MECL III Design Rules
A Circuit Card Layout
B_ Transmission Line (Microstrip Line)
C_ On-Card Clock Distribution via Transmission
Lines
0_ Off-Card Clock Distribution
E_ Testing MECL III
CHAPTER 3 - Printed Circuit Board Connections
Transmission Line Geometries
Basic Transmission Line Operation
Unterminated Lines
Series Damped and Series Terminated Lines
Parallel Terminated Lines
Transmission Line Comparison
Wirewrapped Cards
CHAPTER 9 - AC Noise Immunity
Introduction
Test Circuits
Test Conditions
Test Results
Conclusions
CHAPTER 10 - MECL 10,000 For Military
Applications
Fanout
Termination and Interconnect Techniques
Power
Noise Margin
AC Performance
CHAPTER 4 - System Interconnections
Connectors
Coaxial Cable
Differential Twisted Pair Lines and Receivers
Ribbon Cable
Schottky Diode Termination
Parallel Wire Cables
Twisted Pair Cable, Driven Single-Ended
APPENDIX I - MECL Hardware and Components
CHAPTER 5 - Power Distribution
System Power Calculations
Power Supply Considerations
System Power Distribution
Backplane Power Distribution
On-Card Power Distribution
VTT Termination Voltage Distribution
Motorola's MECL System Design Handbook may be
purchased for $2.50 per copy. Copies may be obtained
by sending check or money order payable to Motorola
Inc., at P. D. Box 20924, Phoenix, Arizona 85036.
'-38
INTEGRATED CIRCUITS
SELECTOR GUI DES
2-1
INTEGRATED CIRCUITS
+750
MC1000 Series (0 to
C)
MC1200 Series (-55 to +1250 C)
FEATURES
The MECL II series of monolithic integrated logic circuits presents the system
design engineer with an integrated circuit family designed to permit system implementation with the fewest possible number of individual units. This approach offers
cost savings, reduced power supply requirements, smaller physical size and high
reliability.
• Propagation typically 4 ns
per logic decision
• Excellent noise immunity
characteristics
• Simultaneous OR/NOR
outputs
• High fan-in and fan-out
capabi Iities
• Internally temperature
compensated
MECL II circuits feature the fastest propagation delay times with commensurate
rise and fall times of any family of integrated circuits. This feature plus the constant
current feature of MECL imposes fewer restrictions on design, layout and system
fabrication than any other high·speed family.
FSUFFIX
CERAMIC PACKAGE
CASE 1107
LSUFFIX
CERAMIC PACKAGE
CASE 832
TO-ll11
LSUFFIX
PSUFFIX
CERAMIC PACKAGE
CASE 620
-
PLASTIC PACKAGE
CASE 1148
F SUFFIX
."''"OX
CERAMIC PACKAGE
CASE 650
PLASTIC PACKAGE
CASE 6411
FUNCTIONS AND CHARACTERISTICS
(VCC
=0
VEE
= -52
V TA
Typo
Function
= 25 0 CI
CD
o to +75 0 C
-55 to +1250 C
Loading
Factor
Each
Output
Propogation
Dolay
ns typ
Power
Dissipation
mW
typ/pkg
Caso
Single 6-lnput Gate, 3 OR Outputs w/Pulldowns
3 NOR Outputs w/Pulidowns
MC1201F,L
MC1001P
25
4.0
115
607,632,646
Dual4-lnput Gate, 2 OR Output's w/Pulidowns
MCI204F.L
MC1004P
25
4.0
95
607,632,646
Dual 4-1 nput Gate, 2 OR Outputs w/o Pulldowns
2 NOR Outputs w/o Pulldowns
MC1206F,L
MC1D06P
25
4.0
45
607,632,646
Triple 3·lnput Gate, 3 NOR Outputs w/Pulidowns
MC1207F,L
MC1007P
25
4.0
110
607,632,646
Quad 2-lnput Gate, 4 NOR Outputs w/Pulidowns
MC1210F,L
MC10l0P
25
4.5
115
607.632,646
Quad 2-lnput Gate, 2 NOR Outputs w/Pulldowns
MC1211F,L
MC10llP
25
4.5
95
607,632,646
2 NOR Outputs w/Pulidowns
2 NOR Outputs w/o Pulldowns
hm Load
nstyp
Type
CASE 632
-
PSUFFIX
PLASTIC PACKAGE
CASE 648
L SUFFIX
CEFtAMIC PACKAGE
'SUFFIX
PLASTIC PACKAGE
CASE 646
Power Dissipation
(No Load)
mW
typfpkg
Coso
150
607,632,646
Dual AID Comparator
MC1650
70
3.5
275
620,650
Dual AID Comparator
MC1651
70
3.0
275
620,650
Binary Counter
MCI654
70
"325 MHz typ
Voltage-Controlled Multivibrator
MC1658
70
"150 MHz tvP
750 LL/
620
125
620,648,650
Dual4-lnput ORINOR Gate
MCI660
70
1.1
120
620,650
Quad 2-1 nput NOR Gate
MCI662
70
1.1
240
620,650
Quad 2-lnput OR Gate
MCI664
70
1.1
240
620,650
Dual Clocked R-S Flip-Flop
MCI666
70
1.8
220
620,650
620,650
Dual Clocked Latch
MCI668
70
1.8
220
Mester-Slave Type D Flip-Flop
MC1670
70
"350 MHz typ
220
620,650
Triple 2-1 nput Exclusive OR Gate
MCI672
70
1.3
220
620,650
Triple 2-lnput Exclusive NOR Gete
MC1674
70
1.3
220
620,650
Bi-Quinary Counter
MC1678
70
"350 MHz tvP
Dual 4-5-lnput ORINOR Gate
MC1688
70
0.8
-500 MHz min
UHF Pre",sler Type D Flip-Flop
MC1690
70
Quad Line Receiver
MC1692
70
4-8it Shift Register
MC1694
70
"325 MHz typ
1 GHz Divide-By-Ten Counter
MC1696
-
·1 GHzmin
1.1
750 L.LJ
620
125
650
200
620,650
220
620,650
750 LL/
650
620
650
CD L suffix denotes Dual In-Line Ceramic Package, F suffix denotes Ceramic Flat Package, P suffix denotes Dual In-Line Plastic Package.
Ii.e., MCI600L = Ceramic Dual In-Line Package, MCI600F
= Ceramic Flat Packege, MCI600P =
U-' Requires Heat Sink - IERC-LIC-214A2WCB or equivalent.
-Toggle Frequency
#DC Loading F actors are based on:
1. Full load output current, IL = -25 mAdc max
2. Maximum input current, lin
=
350 "Adc
2-5
Plastic Dual In-Line Package).
~ rn (S ~ DOD
LOGIC DIAGRAMS
Numbers at ends of terminals denote pin numbers for L package (Case 620 unless noted
CASE
as Case 632) and P pecka99 (Case 646 unless noted as Case 648).
Numbers in parenthesis denote pin numbers for F package (Case 650 unless noted as Case 607).
VCC
VEE
Pin No.
Pin No.
4,5
1,16
12
8
650
620
See individual drawing
for devices withoth.rC .....
GATES------------------------------~----------~
MCl660
(81
.~
(81
5
B
X
3
(7J
(91
(101
6
C
y
2
(61
(101
(11 I
7
0
(91
(111
(14110~
(141
(151 11
15 (31
(161
---X
Po
3~2
5
B
(141
(111
6
(21
(141
=
(161
15
(31
(11
4~
5 B
2
(61
6~
7
3
01
10~
11
14
(21
12~ 15
(31
13
A+B
X
Po == 240 mW typ/pkg (no load)
14 (21
11~ 15
7
MCl688
DuaI4-5·lnput
Triple 2-lnput Exclusive NOR Gate
(61
(81
(91
2
8
(16113~
(101
(141
(31
3
5
(111
6
8
= A+B
tpd == 0.9 ns typ (S10-ohm load)
1.1 ns typ (50-ohm load)
1.1 ns typ (50-ohm load)
mW typ/pkg (no load)
= 240
MC1674
MC1672
Triple 2·lnput Exclusive OR Gate
(16113~
(111
tpd == 0.9 ns typ (510-ohm load)
Po == 120 mW typ/pkg (no loed)
(101
12~
= A+8+C+O
= A+B+C+O
1.1 ns typ (50-ohm load)
(91
(71
(101
(151
(11 13
tpd '" 0.9 ns typ (SlO-ohm load)
(81
(91
10~ 14
14 (21
(1113
(61
~~3
(15111
(81
Quad 2-lnput OR Gat.
B
2
4~
5
(161 12
X
Y
MCl664
MC1662
Quad 2-lnput NOR Gat.
Dual 4-lnput ORINOR Gat.
(61
ORINOR Gate
81
(91
(
(101
3=t=
(71
(61
(111
14 (21
11~
15
7
B
""¥
(141
(31
(21
(151
(31
(161
X=AeS+AeB
tpd'" 1.1 ns typ 15l0-ohm load)
"" 1.3 ns typ (50-ohm load)
Po
= 220 mW
typ/pkg
X=AeB+AeEi
tpd
Po
= 1.1 ns typ (510·ohm load)
= 1.3 ns type (50-ohm load)
= 220 mW typ/pkg
2·6
(11
tpd = 0.8 ns tvp
Po = 125 mW tYP/pkg (No Load)
LOGIC DIAGRAMS (continued)
FLiP-FlOPS------------------------.
MC1SSS
MC1SS8
Dual Clocked R-S Flip-Flop
Dual Clocked latch
(9)
5~a 2
(11)
7
C
(8)
4
R
a
(6)
(::)) : g s :2
(7)
(111
7
(8)
4
3
(16)12~a 15(3)
(14)
9
C
(1113
R
a
C
R
a
«116:):~gs
~
14(2)
(14) 9
C
A
a
(6)
3
(7)
15 (3)
14 (2)
(1) 13
tpd == 1.6 nstyp (5l0-ohm load)
== 1.8 ns typ (50-ohm load)
Po = 220 mW typ!pkg (no-load)
tpd == 1.6 ns typ (S10-ohm load)
= 1.8 ns tvp (50-ohm load)
PO::: 220 mW tvp/pkg (no-load)
(9)
(11)
5
MC1S70
MC1S90
Master·Slave Tvpe 0 Flip-Flop
UH F Prosealar Typo D Flip-Flop
S------,
7 C1
(14) 9 C2
(11) 7 C1
a
2 (6)
2 (6)
(14) 9 C2
(15) 11 01
(15) 11
(8)
4
0
Q 3 (7)
3 (7)
(16) 1202
A-------'
fTog = 500 MHz min
fTog == 350 MHz typ
PO;' 200 mW tvp/pkg (No Load)
Po = 220 mW typ/pkg (no load)
2-7
LOGIC DIAGRAMS (continued)
COUNTERS
MCI654
Binary Counter
00 5
50 3
Clock 1 15
C1
Clock 2
C2
7
01
6
52 9
02
53
11
14
03 12
o·
Q'
AT
AT
a
A
Reset
51
Q
C
10
00
03 13
4
·po = 750 mW typ/pkg
Operating Frequency'" 325 MHz typ
• Requires special heat sink IERe Lie 214A2WCB or equivalent.
MC1678
BI-Quinary Counter
SO
Clock
15
14
ao
13
51
10
Q1
11
52 3
02 4
53 7
03 6
C1
A
Reset
9
o----J---~-t==t==:::!=~==E===~~-J
aD
12
C2 2
03 5
·po
= 750
mW typ
Toggle Frequency
= 350
MHz typ
• Requires special heat sink IERe Lie 214A2WCB or equivalent.
2-8
LOGIC DIAGRAMS (continued)
COUNTERS
(cant.) - - - - - - - - - - - - - - - - - - - - - - - ,
MC1696
l-GHz Divide-By-Ton
Counter
11
vee1
= Pin
VCC2'"
VEE1 =
VEE2""
Bia. POint'"
Pin
Pin
Pin
Pin
ao
10
Q2
4
5
13
12
1•
o
o
a
a
710 Out
Clock 16
....- - - - - - - j c
Enable 2
ceQ
A
A
A
ftog = 1.2 GHz tvp
Po = 650 mW tvp/pkg (No Load)
Output Rise and Fall Times = '.0 ns (20% to 80%)
-This bias point permits capacitive decoupling for
a c performance enhancement.
SHIFT
REGISTER'------------------~
MCl694
4-Bit Shift Registo,
FLIP-FLOP TRUTH TABLE
INPUTS
UTPU
an
D C R S
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
°n_1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
°n_1
1
0
1
0
1
0
1
1
0
1
0
1
1
1
0
1
1
50
2
01
02
aD
13
51
10
01
12
52
3
a2
4
14
15
Clock
Reset
9
·Output State
Undefined
Total Power Dissipation
=<
750 mW typ/pkg
Shift Frequency"" 326 MHz typ
2·9
53
a3
6
5
LOGIC DIAGRAMS (continued)
MULTIVIBRATOR-----........,
OSCILLATOR------_
MC1648
Emitter Coupled Oscillator
MCI668
Voltage-Controlled
Muhivibrator
Co
~~;~~g <>-114--......- 0
Vcx
a
2
6
Bias Filter 12
Input Filter 13
4
veel
= Pin
Pins 1, 14
Vee
=:
VEE
= Pins
7,8
1
VCC2 = Pin 5
VEE=PinS
Operating Frequency
Po
= 225
z:
MHz typ
150 mW typ!pkg
(+5.0 Vdc Supply)
Operating Frequency"" 150 MHz typ
Po
= 125
L, C, Co are external components.
Co is a varactor diode.
mW typ!pkg
COMPARATOR-------------
RECEIVER-----------------MC1692
MCI660
MC16S1
Dual AID Comparator
v,.
6~O
(10)
(9) 5
c.
Quad Line Receiver
(8)
4
-
(6)
00
(7)
00
02
C
a
3
(8) 45~
(9)~
2
(6)
67~.
(10)~
3
(7)
(111
:~::~~~14
Cb(I)13~'5
(14)10~ 14 (2)
(2) 01
(15) 11
(1l12~
(3) 01
(16) 13
15 (3)
~9(13)
Vss
tpd = 3.5 ns typ (MC1650)
3.0 ns typ (MC16S1)
Po = 330 mW tvp/pkg (No load)
Vee = +5.0 V -= Pin 7,10· (11), (14)
VEE
Gnd
tpd
0.9 ns typ (SlO-ohm load)
'.1 ns typ (50·ohm load)
Po = 220 mW typ/pkg (No load)
= -5.2 V = Pin 8 (12)
= Pin I, 16 (4) (5)
2·10
=
MECL 10.000
SERIES
INTEGRATED CIRCUITS FROM MOTOROLA
MC10,100/10,200 Series (-30 to +850 C)
MC10,500/10,600 Series (-55 to +1250 C)
Circuit design with MECL 10,000 is unusually con·
venient. The differential amplifier input and emitter·
follower output permit high fanout, the wired·OR option,
and complementary outputs. MECL III is directly com·
patible with MECL 10,000, and can be used to extend the
speed capability of the MECL 10,000 series.
MECL 10,000 has an excellen t speed-power product,
has relatively slow rise and fall times, and transmission·
line drive capability. The combination of versatile logic
functions and the 2.0 ns propagation delay make MECL
10,000 a versatile family for data handling and processing
systems.
L SUFFIX
P SUFFIX
Cf::AAMIC PACKAGE
Pl-ASTIC PACKAGE
CASE 648
~
_;i"
'.
..
t
PSU'FI'
PL.ASTIC PAC!<::AGE
CASE 649
F SUFFIX
CERAMIC PACKAGE
CASE 652
i
FUNCTIONS AND CHARACTERISTICS
(Vcc'
0
VEE'
-52
V TA'
25°C)
TypoG)
Function
-30
to +850 C
-55
to +125 0 C
Propagation
Delay
nstyp
Power Dissipation
mW
typ/pkg*
Case
Quad 2-lnput NOR Gate With Strobe
MC10l00
-
2.0
100
620
Quad ORINOR Gate
MC10l0l
MC10501
2.0
100
620,648,650
Quad 2-lnput NOR Gate
MC10l02
MC10502
2.0
100
620,648 ,650
Quad 2-lnput OR Gate
MC10l03
-
2.0
100
620
Quad 2-lnput AND Gate
MC10l04
MC10504
2.7
140
620,648,650
Triple 2-3-2-lnput ORINOR Gate
MC10l05
MC10505
2.0
90
620.648,650
Triple 4-3-3-lnput NOR Gate
MC10l06
MC10506
2.0
90
620,648,650
!riple 2-lnput Exclusive OR/Exclusive NOR
MC10l07
MC10507
2.5
110
620,648,650
620,648,650
DuaI4-5-lnput OR/NOA Gate
MC10l09
MC10509
2.0
60
Ouar3-lnput 3-0utput OA Gate
MC10l10
-
2.4
160
620,648
Dual 3-lnput 3-0utput NOR Gate
MC10111
-
2.4
160
620,648
Qued Exclusive OR Gate
MC10113
-
2.5
175
620
Triple Line Receiver
MC10114
MC10514
2.4
145
620,648,650
Q.uad L.ine Receiver
MC10115
MC10515
2.0
110
620,648,650
Triple Line Rac&iver
MC10116
MC10516
2.0
85
620,648,650
Duel2·Wide 2·3·lnput OR·AND/OR·AND·
INVERT Gete
MC10117
MC10517
2.3
100
620,648,650
Dual 2-W'ida 3-lnput OR-AND Gate
MC10118
MC10518
2.3
100
620,648,650
4-Wldo 4,3·3·3·lnput OR·AND Gate
MC10119
MC10519
2.3
100
620,641.;650
:4--Wlde OR-AND/OR-AND-INVEAT Gate
MC10121
MC10521
2,3
100
620,648,650
T .. iple 4-3-3-lnput Bus Driver
MC10123
-
3.0
310
620
Quad MTTL to MECL Translator
MC10124
MC10524
3.5
380
620,648,650
Quad MECL to MTTL Translator
MC10125
MC10525
4.5
380
620,648,650
Dual MECL to MOS Translator
MC10127
-
-
620
BUI Driver
MC10128
-
12.0
700
620
MC10129
-
10.0
750
620
Dual Latch
MC10130
MC10530
2.5
155
620,648,650
Dua' Type 0 Master-Slave Flip-Flop
MC10131
MC10531
f'" 160 MHz
235
620,648,650
Dual Multiplexer With Latch and Common Reset
MC10132
-
3.0
225
Quad Latch
MC10133
MC1Q533
4.0
310
Multiplexer with Latch
MC10134
-
225
620,648
Dual J-K Master-Slave Flip-Flop
MC10135
MC10535
f
140 MHz
280
620,648,650
Universal Hexadecimal Counter
MC10136
MC10536
f - 150 MHz
625
620,650
Quad
CD
a us
Receiver
3.0
620,648
620,648,650
L suffix denotes Dual In-Une Ceramic Package. P suffix denotes Dual In-Une Plastic Package, F suffix denotes flat package
(i .••• MC10100L ~ C.ramic Dual In-Line Package. MC10l00P:: Plastic Dual In-Line Package and MC10500F "" Ceramic Flat Package,)
-External Load Power not included.
2-11
~ ~ ~ [110.000
LOGIC DIAGRAMS
Numbers In parenthesis denote pin numbers for F package (Case 650).
FUNCTIONS AND CHARACTERISTICS
(continued)
Propagati on
Power Dissipation
-30 to +850 C
-55 to + 125°C
Delay
ns typ
typ/pkV'
C ....
MC10137
MC10537
f'" 150 MHz
625
620,650
TypeQ)
Function
Universal Decade Counter
Bi-Quinary Counter
64-Bit Random Acces. Memory (900)
mW
MC10138
-
f::::: 150 MHz
370
620
MCM10140
-
tAccess'" 15 (max)
420
620,690
f = 200 MHz
425
620,648,650
tAccess - 10 (max)
420
620
MCM10143
-
tAccess::: 10
610
623
2S6-Bit Random Access Memory
MCM10144
-
t Access == 30 (max I
420
620,690
64-Bit Regilter Fila (RAM)
MCM10145
625
620
MCM10147
-
= 10
128-Bit Random Access Memory
tAccess
= 12 (max)
420
620
64-Bit Random Access Memory (50 fl)
MCM10148
-
tAecass
= 15
420
620
1 024-Bit Programmable Read Only Memory
MCM10150
-
-
690
Four-Bit Universal Shift Register
MC10141
64-Bit Random Accesl Memory (50 fl)
MCM10142
8)( 2 Multiport Regilter File (RAM)
Quad Latch
MC10153
12-Bit Parity Generator-Checker
MC10160
Binary to 1-8 Decoder (LOW)
Binary to 1-8 Decoder (High)
Error Detection-Correction Circuit
MC10163
S-Line Multiplexer
MC10164
MC10541
tAces"
(max)
tAccess::: 20
4.0
310
620
MC10560
5.0
320
620,648,650
MC10161
MC10561
4.0
315
620,648,650
MC10162
MC10562
4.0
315
620,648,660
5.0
520
620
3.0
310
620,648,650
MC10564
a-Input Priority Encoder
MC10165
-
7.0
545
620,648
5-Bit Magnitude Comparator
MC10166
6.0
440
620
Quad Latch
MC10168
-
3.0
310
620
Dual Binarv To 1-4 Decoder (Low)
MC10171
MC10571
4.0
325
620,648,650
MC10572
4.0
325
620,648,650
2.5
275
620,648
Dual Binary To 1-4 Decoder (High)
MC10172
Quad 2-lnput Multiplexer/Latch
MC10173
Dual 4 To 1 Multiplexer
MC10174
MC10574
3.5
305
620,650
Quint Latch
MC10175
MC10575
2.5
400
620
Hex "0" Malter-Slave Flip-Flop
MC10176
-
460
620
Triple MECL to NMOS Tranllator
MC10177
-
1.0W
620
Binary Counter
MC10178
-
Look-Ahead Carry Block
MC10179
MC10579
-
Dual High Speed Adder/Subtractor
MC10180
MC10580
4-Bit Arithmetic Logic Unit/Function Generator
MC10181
MC10581
2-Bit Arithmetic Logic Unit/Function Generator
MC10182
Error Detection-Correction Circuit
MC10193
Hex Inverter/Buffer
MC10195
Hex "AND" Gate
f = 250 MHz
f : 150 MHz
370
620
3.0 (Cn,P) 4.0 (G)
300
620,648,650
360
620,648,650
See Logic Oiag.
600
623,649,652
See Logic Dieg.
575
620
7.5
520
620
2.0
200
620
MC10197
-
2.8
200
620
High Speed Dual 3-lnput 3-0utput OR Gat.
MC10210
-
1.5
160
620
High Speed Dual "3-lnput 3-0utput NOR Gate
MC10211
-
1.5
160
620
High Sp.ed Dual 3-lnput 3-0utput OR/NOR Gate
MC10212
-
1.5
160
620
High Speed Triple Line Receiver
MC10216
MC10616
1.8
100
620,648,650
High Speed Dual Type 0 Matter-Slave Flip-Flop
MC10231
MC10631
270
620,648,650
High Sp. . d 2 x 1 Bit Array Multiplier Block
MC10287
400
620
CD
-
-
4.6
f - 225 MHz
-
L .ufflx denotel Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package
(I.e., MC10100L" Ceramic Dual In-Une Package, MC10100P '"' Pla.tlc Dual In-Line Package and MC10500F "" Ceramic Flat Package.)
-Load Power not included
2-12
LOGIC DIAGRAMS
CASE
VCCl
VCC2
VEE
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
GATES-----------------------------------------,
MCl0l00
Quad 2-lnput NOR Gate
With Strobe
MC10l0l
MC10&01
Quad OR/NOR Gate
4
2
(8)
(11 )
6
. . .,,---d. . .----
4
7
MCl0l02
MC 1 0&02
Quad 2-lnput NOR Gate
2
(6)
-"-~--- 5
(9)
--I-...,--...d/JI_"---- 3
(7)
t---L____- ......---- 6
( 1 0)
(14) 10~1-...'--...d/JI_"----14 (2)
10
......---- 11
t---L~-
14
11
(15)
(1) 13 ~I-...,--...d/JI_"---- 15 (3)
(16) 12
12
9
(13)
45~
(8)
.2
(9)~
(6)
(10)6~
(11)7~3(1)
(14)10~
(15) 11
14 (2)
(16) 12~15 (3)
(1)13~9(13)
15
13
Po = 25 mW typ/gate (No Load)
tpd = 2.0 ns typ
Po = 25 mW typ/gate (No Load)
tpd = 2.0 ns typ
MC10l03
MCl0l04
MC10504
Quad 2-lnput AND Gate
Quad 2·lnput
OR Gate
4-----,=C>--
:c>---
(8)4~
11
Po
= 25
3
MCl010&
MC 10505
Tripi. 2-3-2 Input OR/NOR Gate
_
(10)G~
(11)7~3(1)
(14)10~
_
('5),,~'4(2)
(IG)12~9(13)
(814~3(7)
(9)5~2(6)
[13)9~ 6
(14) 10
7
(10)
(11)
(15) 11
(1)13~'4(2)
:C>--'4
(')'3~'5(3)
mW typ/gate (No Load)
Po = 35 mW typ!gate (No Load)
tpd - 2.7 nstyp
Po 230 mW tvp/gate (No Load)
tpet '"" 2.0 nl typ
MC10107
MC10507
Triple 2-lnput Exclusive
OR/Exclusive NOR
MC10l09
MC10&09
Dual 4-5-lnput
OR/NOR Gat.
tpd :::: 2.0 ns typ
MC10l06
MC10506
Triple 4-3-3-lnput NOR Gate
(::::~3(7)
(11)7~
A
Y
[8)4~2161
19)5~317)
(13)
9~11 (15)
(11)7~'O(14)
(t3)9~
(14) 10
2 (G)
(2)'4~12(16)
(3)15~13(1)
(15) 11
(lG)12~
(1) 13
=
(9)5~2(G)
;~ ____~::~~':
10
Po =- 25 mW typ/gate (No Load)
tpel
2.0 ns typ
(IG)
12~15[3)
: : :~3
[10)
6
111)
7
;:::,:~
2
15
12
(1)
13
[6)
14 12)
(15) 11
(I G)
[7)
13)
15 (3)
(2) 14
Po = 30 mW typ!gate (No Load)
tpd = 2.0 ns typ
Po
tpd
z~ IA_S)+
(A_B)
Y
(A. BI
=-
LA. • HI
+
= 110 mW typ/pkg
= 2.5 ns typ
2-13
(No Load)
Po - 30 mW typ/gete (No Load)
tpel • 2.0 ns typ
LOGIC DIAGRAMS (continued)
GATES(continuedl - - - - - - - - - - - - - - - - - - - - - - - - - - - - " " "
MC10110
MC10210
Dual 3-lnput 3-Output
OR Gate
MC10lll
MC10211
Dual 3-1 nput 3-0utput
NOR Gate
5~~
6
7
'~~''2
"
'2
9
13
10
11
14
Po
Po'"" 160 mW tvp/pkg (No Load)
MC101'O
tpd "" 2.4 ns typ
MC1021D
tpd = 1.5 ns typ
3
10
14
Load)
MC10l17
MC10517
DU81 2-Wido 2-3-1 nput
OR-AND/OR-AND-INVERT
Gate
(8)
4
(91
5
,
6
= 160 mW ryp!pkg (No
13
tpd "" 2.4 ns 'tYP
MC1D211
tpd"" 1.5 ns typ
9
2
~
MC1D111
MC10113
Quad Exclusive
OR Gete
E
4
(101
6
(11\
7
(13)
9
(14)
10
(15)
11
r -___ "
= (A
+ B) • (e + 0 + E)
+ 0 + E)
3
(7)
y
2
(6)
X = (A + B) • (e
14
11
12
13
15
Po = 100 mW tYP/pkg (No Load)
tpd
=
2.3 ns typ
L-_r---"_ _ 14 (2)
.--,
Po'" 175 mW typ!pkg (No Load)
tpd
= 2.5 nl typ
J - - 1 5 (3)
(16) 12
(1)
3
MC10l19
MC10519
MC10118
MC1OS18
4-Wide 4-3-3-3 Input
OR-AND-Gate
Duel2-Wide 3-lnput
OR-AND Gete
(7) 3
(B) 4
(7) 3
(8) 4
(11) 7
(9)
(10)
(11)
(13)
(13) 9
(14) 10
(9) 5
2 (6)
(10) 6
(14) 10
(15) 11
(16) 12
(1) 13
(2) 14
(15)
(16)
(1)
(2)
(3)
15 (3)
6
7
9
2
(6)
11
12
13
14
15
·Collector Dot
Po = 100 mV typa/pkg (No Load)
• Collector Dot
PO:::: 100 mW typ!pkg (No Load)
tpd - 2.3
5
tpd:::O 2.3 ns typ
ns tYP
2·14
LOGIC DIAGRAMS (continued)
MC10196
MC10121
MC10621
Hex In_tw/Buffer
4-Wida
A
OR-AND/OR-AND-INVERT
Gate
:::;--~~~---------,
- - - 1 . _____- - - - ,
(10) 6
1111 7
(13)9
a
B
6
4
-~.,-...,o_--I----~
2(7)
114110
3(6)
13
10
(15)11
116112 ---"'---------.,
14
(1) 13 -~'''o_--l----
(2)14
(3) 1 5 ----,L -------
11
IS
12
Po ~ 200 mW typ/pkg INo Load)
tpd ::: 2.8
typ
n.
Po: 100 mW typ/pkg INo Load)
tpd '" 2.3 ns typ
MC10197
Hex AND Gate
MC10212
High Speed Duol 3-lhput
3-0utput OR/NOR Gote
3
-
5~:
4
6
2
7 --
-+___"o.L.-'i------ 13
10 ____
9
10
11
12-----
~
.
'2
13
14
VCC1 - 1,15
VCC2: 16
VEE :8
.,...----- 15
PO:: 160 mW typ/pkg (No Load)
tpd;;:: 1.5 nl typ (All Outputs Loaded)
Po'" 200 mW typ/pkg (No Load)
tpd :: 2.8
n. typ
2-15
LOGIC DIAGRAMS (continued)
TRANSLATORS==~-----------------------------MC10124
MC 10525
Quad MTTL to MECL Translator
MC10125
MC10525
Quad MECL to MTTL Translator
MC10127
Dual MECL to MOS Translator
(6)2~
(9) 5
4(8)
(10) 6
2(6)
III) 7
3 (7)
1(5)
12(16)
(14) 10
15 (3)
13(1)
(15) 11
(7)3~418)
(10)6~_
(11)7~519)
(14)10~
(15)11~12116)
(2)14~
=t>--j1.-
(3)'5~'311)
~'(5)
14(2)
Vse
Po = 380 mW typ/pkg (No Load)
tpd = 3.5 os typ
12
11
Po = 380 mW tvp/pkg (No Load)
13
,
,
14
9
....../'.r~
Vee = Gnd:= Pins 1, 2, 15.16
VEE=Pin8
VSS:= Pins 7, 9
tpd "" 4.5 01 typ (50% to
~1.5
Vdc out)
RECEIVE RS=====______---------------------=
MC10114
MC105l4
Triple Line Receiver
(8)4~216)
(9)5~317)
(13)9~6110)
(14)10~7111)
(16) 12~14(2)
(1)13~'513)
~11(15)
VSS
MC10115
MC10515
Quad Line Receiver
Triple L ina Receiver
le)4~216)
le)4~
(9)5~216)
(11)7~
(10)6~317)
(14)10~
(15)11~'412)
(1)13~
(16)12~'513)
'v-SS
tpd "" 2.4 nstyp (Single Ended Input)
tpd "" 2.0 ns typ (Differential Input)
Po "" 145 mW typ/pkg (No Load)
MCl0116, MCl05l6
MC102l6, MC106l6
9(13 )
(9)5~317)
(13)9~6110)
(14)10~7111)
(16)12~1412)
1')13~'513)
~"1'6)
MCIOl16, MCI0516
Vss
Po = 85 mW typ!pkg (No Load)
tpd "" 2.0 ns typ
MCI0216, MCI0616
PO"" 110 mW typ/pkg (No Load)
Po
~
tpd = 2.0 ns typ
tpd
= 1.8 ns typ
1400
100 mW typ/pkg INo Load)
MC10129
Quad Bus Receiver
1501
Po'"' 750 mW tvp/pkg (No Load)
tpd = 1001 typ
302
034
Hyster•• i.
Control
50-------'
Clock 11 u - - - - - - - '
R.MtIOo------~-~
Strobe 12
2-16
LOGIC DIAGRAMS (continued)
FLiP-FLOPS--------------------,
MC10131,MC10631
MC10231,MC10631
Duo! Type D M..ter·S!..,.
Flip-Flop
51
(9)
01 (11)
GEl (10)
R-8 TRUTH TABLE
5---------------.
7----..-ot
2
(6)
6
R
S
L
L
L
H
H
L
L
H
N.D.
H
3
(7)
Q
n +l
an
H
N.D. "" Not Defined
MC10131. MC10531
Rl
(8)
Cc (13)
R2
Po = 235 mW typ/pkg (No Load)
f = 160 MHz typ
4-+-------'
9
MC10231. MC10631
(1) 13--+------------.
PO::: 270 mW typ/pkg (No Load)
f'" 225 MHz typ
CLOCKED TRUTH TABLE
14 (2)
GE2 1'5)"---~__/
15 (3)
02 (14) 10-----.ao.t
lP
c
0
Q n +l
L
rp
an
H
L
L
H
H
H
= Don't Care
C = GE + CC'
52 (16) 12 - - - - - - - - - '
MC10176
MC10135
MC10535
H.x "D" M.st ..·S.... Flip-Flop
Duol J·K M.st.r-S ....
Flip·Flop
2 00
R-S TRUTH TABLE
51 (9) 5
Jl (11) 7
2(6)
Kl(10) 6
3(7)
Rl (8) 4
C(13) 9
52(16)12
R
S
°n+1
L
L
an
L
H
H
H
L
H
H
L
N.D.
3 01
4 02
CLOCKE.D TRUTH TABLE
N.D. '" Not Defined
CLOCK J·K TRUTH TABLE"
J2(14)10
15(3)
K2(15)11
14(2)
K
Q n +l
L
L
an
H
L
L
L
H
H
H
H
Q
R2 (1) 13
13 03
Q n +l
rp
On
H'
L
L
H'
H
H
• A clock H is 8 clock
transition from 8 low
to a high state.
n
15 Q5
positive transition of clock
for J-K input-condition
present.
= 280
0
L
(/> == Don't Care.
14 Q4
·Output states change on
Po
C
Po '" 460 mW typ!pkg (No Load)
mW tvp/pkg (No Load)
f tog ::: 150 MHz typ
f tog '" 140 MHz typ
2-17
LOGIC DIAGRAMS (continued)
DRIVER------------------------------------------~
MC10128
Bus Driver
MCl0123
Tripi. 4-3-3 Input Bu.s Driver
Dl
01
Clock
Reset "",,rl...,...---'
':~2
11~
Disable 1 o-';~-+---+-'
Disable 2
0--'''-1-+---+..,
D2
12~ 15
13
14
Stro~~--------~
Control 2
Po - 310 mW typ/pkg (No Load)
tpd = 3.0 ns typ
Po = 700 mW typ/pkg (No Load)
tpd = 12 ns typ
PARITY CHECKER - - - - - - - - - - - - - - - - - - - - - .
MC10160
MC10560
(7) 3
(B) 4
12-Bit Parity Generator-Checke,
INPUT
OUTPUT
Sum of
High Level
Pin 2
(9) 5
(10) •
(11) 7
Inputs
(13) 9
(14)1.
(15)11
(16)12
(1) 13
2 (6)
Even
Low
Odd
High
PD - 320 mW fVP!pkg (No Load)
tpd .. 5.0 ns typ
(2)14
(3) 15
ENCODER-----------------------------------~
MC10165
8-lnput
Priority Encoder
Vee 11 -
_ 1 6 Vee 2
012-
- 1 5 02
003-
- 1 4 03
e4-
- 1 3 D2
D05-
- 1 2 D5
D76-
- 1 1 D4
D17-
- 1 0 D3
VEEB-
-9
D6
DO
Dl
H
,. Don't Care
2-18
¢JIPHHHHHHHH
H
"
'"
(/)
L
L
L
L
L
L
l
A
L
L
L
H
aD Q1 Q2 Q3 04
H
L
H
L
L
L
as
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
l
L
L
L
H
L
L
L
L
H
l
H
L
L
L
L
L
H
H
L
L
L
L
L
H
H
L
H
L
L
L
L
L
"
L
L
l
l
L
L
L
H
L
L
L
L
L
L
H
•• •" ••
06 07
L
...
L
H
•
H
OUTPUTS
•
c
L
!)
Po
02
03
9
1106
14
4
3
13 04
9
12 05
C
00
01
A 7
13 04
B
6
5
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
Don t Care
315 mW typ/pkg (No Load)
tpd ... 4.0 n. typ
c
Po - 315 mW tvp/pkg (No Load)
tpd - 4.0 ns typ
MC10171
MC10172
Dual Binary To 1·4 Dacoder
Dual Binery To 1-4 Decoder
(Low)
(High)
10 003
10 00 3
'II 002
11 00 2
12 00 1
12 00 1
13 00 0
13 00 0
A 9
B 7
E
3 01
3
4 01
2
5 01
15
3 01 3
4 01 2
1
6 01
5 01 0
El 2
1
6 01 0
TRUTH TABLE
ENABLE INPUTS
E
EO
L
L
L
L
L
L
L
L
L
L
L
H
H
••
L
L
L
l
H
L
A
L
L
H
H
L
L
•
l
H
l
H
L
L
• • • •
TftUTHTAR.E
OUTPUTS
INPUTS
0.0
011
0'2
013
000
00.
002
003
l
H
H
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H,
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
•• Don't c.,.
H
H
H
H
H
H
L
H
H
H
•
f.
Eo
l
H
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
L
H
A
• a. 0
all 0.2 0.3 000 00' 002 003
l
L
H
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
• • • •
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
L
H
. - Oont Cere
Po -
Po -
325 mW typ/pkg(No Load)
tpd - 4.0 nl typ
!pet
2-19
~
325 mW typ/pkg (No LOIld)
4.0 no typ
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
LOGIC DIAGRAMS (continued)
DATA SELECTORS/MULTIPLEXERS----------Al1~
011
012
MC10132
MC10134
Dual Multiplex .. With
Dual Multiplexer with latch
r---
4
A06~
Latch and Common R_t
~2 01
~
A"'--U011
----:l
5
CEO 10
~3
Cc 7
R 6
(11
r---
4
012 5
CEO 10
j
9
021 13
eEl
~1502
~
02212
Cc 7
eEl
9
021 13
~'4Q2
R
0
C
CE
Ontl
L
L
L
L
L
L
L
H
H
L
H
L
an
an
an
L
L
L
H
L
L
L
H
H
H
H
H
H
an
an
an
L
H
L
H
H
H
H
*
:i
~3
~
~-
022 12
TRUTH TABLE
L
L
L
T
~2 01
01
~'5 02
-,402
TRUTH TABLE
Po
= 225
mW typ/pkg
(No Load)
tpd = 3.0 ns typ
C
AO
011
012
On+ 1
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
On
H
L
Po
= 225 mW typ/pkg
tpd
= 3.0 ns
(No Load)
typ
rJ> = Don't Care
c= Ce + Cc
rJ> - Don't Care
A (11) 7
L
B(13)9~
MCl0173
Quad 2-lnput
Multiplexer/Latch
MCtOt64
MCt0564
B-Lin. Multiplexer
S.'.ct9~
C(14)10~
Enable (6) 2
===\
-;
~
;-
=\
;-
XO (10) 6
Xl (9) 5
X2(B)4
r
H
X3 (7) 3
~
X4 (15)11
X6 (1) 13
-B
)"
'------='=\
;-
X7 (2) 14
0006
~-
0015
-0
~=
J=<
0104
P.o
= 310 mW typ/pkg
ns typ/pkg
~
-L./
02112
~:=
~
~
03011
ADDRESS INPUTS
ENABLE
C
B
A
Z
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
XO
Xl
X2
X3
H
H
L
L
H
H
H
H
H
H
~
H
L
H
L
201
~;= ~ 15 02
02013
TRUTH TABLE
100
~
0113
(No Load)
tpd'" 3.0
;-
R
X5 (16) 12
;-
15 (3) Z
03110
Clock 7 -
1403
'--
TRUTH TABLE
SELECT CLOCK
X4
H
xs
H
L
L
H
X6
X7
L
L
H
~
L
q, = Don't Car •
• - Don't Cere
2-20
OOn+l
000
001
aO n
Po
= 275 mW typ/pkg
tpd
~
(No Lo.ad)
2.5 n. typ
LOGIC DIAGRAMS
(continued)
DATA SELECTORS/MULTIPLEXERS
(continuedl
MC10174
MC10674
MCl0l.
MCl0530
Dual 4 to 1 Multiplex ..
Quell l.8teII
51 (9) 5
XO (7) 3 - - - - - - '
Xl (9) 5----H--,.-{~
01(11) 7
2 (6) Z
X2 (8) 4 ----H::8~
2 (6)
CEI (10) 6
X3 (10) 6 -----1-t-b8~
3 (7)
A (11) 7
Al (8) 4
C (13) 9
8 (13) 9
A2 (1) 13
Po ~ 305 mW tvp/pkg
(No Load)
YO (1) 13 ----+++1-1.____
14 (2)
Y 1 (15) 11 ----+-=H:....::{____
15 (3) W
CE2 (15) 11
02 (14) 10
Y2(16) 12'----F=f=L-/
Y3 (14)
15 (3)
10---===L____
S2 (16) 12
TRUTH TABLE
TRUTH TABLE
ENABLE
I'/>
ADDRESS INPUTS
OUTPUTS
E
B
A
Z
W
H
L
L
L
L
L
L
L
H
L
H
L
L
H
H
XO
Xl
X2
X3
YO
Yl
Y2
Y3
= Don't
D
C
CE
L
L
L
L
H
L
L
H
L
H
an
H
L
an
H
an
q,
H
cp - Don t Care.
Care
MC10175
MC10575
Quint Latch
LATCHES----------'
MC10133
MC10533
Quad Latch
°n+1
00I0---~
1400
-----t--t'"1
15 01
MC10153
Quad Latch
003------"'!
2 00
GO 5 , - - - - - [ - - - -.......,-,
01 7----4--~~~
003,------Ai,nn~~~
6 01
01 12
2 00
6 01
02 13 ----t---+-1
2 02
CE4
03 9
11 02
11 02
-----+--t"i
t
3 03
9 45 ----t-l''''I
404
CO 6
C17
15 Q3
Po::: 310 mW typ/pkg (No Load)
tpd "" 4.0 ns typ
15 03
Po::: 310 mW typ/pkg (No Load)
tpd = 4.0 ns typ
11----+-~
Aesat
Po
tpd
= 400 mW typ/pkg (No
= 2.5 ns typ
TRUTH TABLE
TRUTH TABLE
TRUTH TABLE
"G
C
D
Q n +1
"G
C
D
Q n +l
H
q,
L
H
q,
q,
L
H
q,
an
0
CO
C1 Reset
L
L
H
L
L
L
L
L
a n+1
L
L
L
an
L
L
H
L
L
L
L
L
L
H
L
H
H
H
L
L
H
H
q,
q,
q,
H
L
an
an
H
H
L
q,
H
H
L
tP c Don t Care
C=Cc+ce
I'/> '" Don't Care
C '" Cc + CE
2·21
Load)
H
LOGIC DIAGRAMS (continued)
SHIFT
REGISTERS----------------~
MC10141
MC10541
Four-Bit Universe. Shift Register
(1)
13
I
TRUTH TABLE
OL
( (8)
4-C
aD f---14
(16)
1 2 - DO
(15)
1 1 - 01
(13)
9 - 02
(10)
6 - 03
(14)
1 0 - SI
(11)
7 - S2
al f---15
SELECT
(2)
(3)
a2 f - - - 2
(6)
a3 - 3
(7)
5
S2
OPERATING MODE
02n +l
03n+l
l
L
Parallal Entry
DO
01
02
03
L
H
Shift Right-
aln
Q2 n
a3 n
DR
H
L
Shift Left-
Dl
aO n
aln
a2n
OOn+l 0l n+l
H
H
Stop Shift
aO n
aln
a2n
a3"
• Outputs .. exist after pulse appear, at "c" input with input condition.
as .hown. (Pulse "" Positive tran.ition of clock Input).
DR
(9)
OUTPUTS
SI
I
Po "" 425 mW tvp/pkg
fahift" 200 MHz typ
ERROR DETECTION-CORRECTION
MC10163. MC10193
Error Detection-C orraction
Circuit
MC10193 LOGIC DIAGRAM
MC10163 LOGIC DIAGRAM
81
B2
Bl
B2
6
7
6
)-f---15P4
15 POA
_B412
B711
B412
B711
)-t---3P3
3 P3
-
B5 4
B6 5
Jl5 4
B6 5
2 P5
2 POB
BO 9
B310
-
BO 9
B310
) - - - - 1 4 PI
> - - - - 1 4 PI
> - - - - 1 3 P2
>----13P2
IBM CODE
MOTOROLA CODE
POA = Bl, B2, B4, B7
POB = 80, B3, B5, 86
PI = Bl, B3, B5, 87
P2
;c
P3
= B4,
PI = Bl, B3, B5, B7
P2 = B2, B3, B6, B7
P3 = B4, B5, B6, B7
82, 83, 86. B7
P4
B5, B6, B7
P5
= 81, 82, 84, B7
= Byt. (BO, 1,2,3,4,5,6,7)
..
Po = 520 mW typ/pkg (No load)
tpd"" 7.5 ns typ (Pin 7 to Pin 2)
Po = 520 mW tvp/pkg (No Load)
tpd:: 5.0 ns tvp
2-22
LOGIC DIAGRAMS
(continued)
COUNTERS--------------------------------------~
(14)10(1)13(16)12(15)11(10) 6 (9) 5 (13) 9 (11) 7 -
-
Cin 00 r-14
C
r-15
DO 01
01
02 r-- 2
02
03
03 r-- 3
51
S2 C out r-- 4
MC10136
MC10536
Universal Hexadecimal
Counter
(2)
SEQUENTIAL TAUTH TABLE'
(3)
INPUTS
(6)
5'
L
(7)
L
(8)
52
H
H
H
H
H
-
FUNCTION SELECT TABLE
51
52 DO O.
Operating Mode
L
L
H
H
L
L
L
L
Pr..., (ProGram)
DlICr.mant (Count Cown)
OUTPUTS
02 03
H
CMrV
;;;
Clock
H
•• •• ••
• • •
•• •• •• ••
• • • •
•• •• ••
H
H
••
L
ao o.
H
H
H
H
H
H
H
H
L
•• ••
Carry
0,;
02 03
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
(/) "" Don't care.
HOLd (Stop Cound
'Truth table shows logic states assuming inputs vary in sequence
shown from top to bottom.
Po = 626 mW typ/pkg (No Load)
•• A clock H is defined as a clock input transition from a low to
f count -150MHztyp
a high logic level.
MC10137
U River ..1 Decade
Counter
.-10-C;n
~~=~O
1 1 - 01
6 - 02
5-03
9-51
00-14
SEaUENTIAl TRUTH TABLE'
5iTV
01-15
51
02-2
52 00 01
H
03-3
H
H
L
L
7 - 52 C ou, - 4
H
H
~
fUNCTION SELECT TABLE
51
52
OUTPUTS
INPUTS
Operating Mode
H
H
L
L
H
H
H
L
L
L
••"
•••
•
H
H
••
•
•••
•
H
02 03
H
•••
iii'
Clock
CXI
at
~
02 OJ
OUt
L
••
•
••
H
H
H
L
•
••• •• •
•
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
L
Incramant (Count Up)
OllCremant (Count Down)
q, = Don't care.
Hold (Stop Count)
-Truth table shows logic states assuming inputs vary in sequence
shown from top to bottom.
_. A clock H is defined as a clock input transition from a low to
8 high logic level.
Po = 625 mW typ/pkg (No Load)
f eount "" 150 MHz tvp
12-Cl
9-R
7-C2
11-50
10-51
6 - 52
5-53
MC10138
Bi-au inary Count.
0 0 r - 15
01r-13
02r- 4
03r-- 2
00r-14
03r-- 3
11-50
7 - 51
6-52
5 - 53
12-Cl
;O-C2
9- R
COUNTER TRUTH TABLES
BI·QUlNARY
BCD
(Clock conneettd to C2
.nd 03 connecttd to C1)
IClock connected to Cl
and CO connected to C2)
01
02
6
L
L
H
8
H
L
L
L
H
H
L
L
L
H
H
L
COUNT
0
1
2
3
•
,
6
•
00
ao
MC 1 0178
Binary Counter
COUNT
,
ao
O.
Q2
L
H
L
H
L
H
L
L
H
H
L
L
H
H
H
H
Po
00
0
= 370 mW
00-15
01-13
02-4
03-2
00-'4
03-3
TRUTH TABLE
INPUTS
R
50
5.
52
L
L
H
L
L
H
H
co
01 02
OJ
H
L
H'
LJ H
L
L
H
L
NoCounl
'YP/pkg
L
L
1'og - 150 MHz (Typ)
L
L
L
L
2
]
OUTPUTS
C2
*- •• ~•• I. \,1
(No Load)
L
3
L
H
S3 Cl
L
L
L
H
H
.L
L
L
~ - Oon't Care
Clock tran,itlon from VI L to VI H
may be applied to C 1 or C2 or both
Po "" 370 mW typ/pkg (No Load)
f tog "" 150 MHz typ
for
2-23
.ame effect.
LOGIC DIAGRAMS (continued)
ADDER AND ARITHMETIC FUNCTIONS-----------.
MC11l179
Look-Ahead Carry Block
G3
5
P3 13
9
J ./
P2 12
~"
G2
--L/
-= =:::;
Cn
~3
~
'"
15 PG
./
Gl
Po: 300 mW tvp/pkg
tpd "" 3.0 ns typ (Carry, Propagate)
4.0 ns typ (Generata)
7
PI 10
GO
GG
>-
~
II
~2
./
C n +4
)
4
6
C n +2
~
PO 14
(11) 7
(13) 9
(9) 5
(10) 6
(8) 4
MC10181
MC10581
4-Bit Arithmetic Logic
MC10180
MC10580
Dual High Speed
AddarlSubtr.ctor
.....
...
...
Unit/Function Generator
SelA
50 ......... 15 (3)
(19) 13
Sala
SO .........2 (6)
(21) 15
AO
Po
BO
....
= 360 mW typ/pkg
(23) 17
~
(20) 14
C out .........3 (7)
Cin
tpd (typ)
...
SalA
51
L-........
Sala
51
_
(IS) 11
(14) 10
(16) 12
......
-
~14(2)
~1(5)
50 51
Cin to C out = 2.2 ns
AO to SO = 4.5 ns
AO to C out = 4.5 ns
(3) 21------ AO
(2) 20------ BO
(24) lB------ Al
(1) 19------ Bl
(22) 16------ A2
Al
(17) 11------ B2
Bl
C out
~13(1)
r
52
53
FO - 2 ( B )
Fl - 3 ( 9 )
F2 - 7 ( 1 3 )
F3 - 6 ( 1 2 )
(16)10-- A3
GG - 4 ( 1 0 )
Positive Logic Only
(15) 9------ B3
( 4 ) 2 2 - - Cn
PG -8(14)
A': A 0SoIA: A (!)SoIA
(5)23--M
Cin
B' ~ B
0
C n +4 - 5 ( 1 1 )
SOla= B (!) Sola
FUNCTION SELECT TABLE
SoiA
SelB
H
H
Po
Function
~
600 mW typ/pkg (No Load)
A1 to F -6.5 n.
C n to C n + 4 - 3.1 nl
A1 tOPG'"'6.0nl
'pd (typ),
S - A plu. B
H
L
S - A minus B
L
L
H
S'" B minus A
A 1 to GG ,.. 4.5 nl
L
S - 0 minus A minus B
A1 to C n +4'" 5.0"s
2-24
LOGIC DIAGRAMS
(continued)
ADDER AND ARITHMETIC FUNCTIONS ( c o n t i n u e d ) - - - - - - - - - - - ,
MC10182
2-Bit Arithmetic Logic
Unit/Function Generator
9----------,
10-----,
SO
13
SI
cn
6
BO
12
Al
11
Bl
Po = 575 mW tvp/pkg (No Load)
FO
4
F1
14
C n to C n +2:: 2.7 ns
PG
15
A 1 to PG '"' 6.5 ns
A 1 to GG : 5.5 ns
GG
3
AO
tpd (typ) A 1 to F '" 7.5 ns
Al toC n +2= 7.0ns
C n +2
M
2
CO
aO
X
MCl0287
HighS.... d
1 Bit Array Multiplier
9
6
aO'
7
bO
4
bO°
MO
5
a'
"
2
SO
Po'" 400 mW typ/pkg (No Load)
tpd: (Outputs loaded 1 kfl to Vee)
co to C2 1.7nstyp
C,
aO to C2 2.8
aO to SO 2.7
bO to SO 3.'
5'
al' '0
b'
M'
3.9
4.4
MO
'3
"51' 12
aO to 51
bO to 51
'5
to 5'8.7
C2
'4
Vee'" Pin 16
VEE=Pin8
2-25
LOGIC DIAGRAMS (continued)
MEMORIES
MCM10145
64·8it Register File
(RAM)
MCM10143
8 x 2 Multiport Register
File (RAM)
Read Enable
4
6
BO
REB
B,
5
Write Enable
Data
9
14
15
Lines
13
8
Data
11
17
16
18
Chip Enable
,......
WEO
DO
aBO
3
Lines
AO
{
OC,
11
12
21
C,
_ Clock
C2 REC
Write Enable
00
AI
01
Data
Output
A3
DO
01
0,
OCO
AO
CE
A2
4
0 ...
'"."" {
Lines
WE,
Co
9
5
Lines
22
10
6
Data
Output
AI
A2
3
2
B2
10
Address
Write Enable
OB,
15
02
02
03 _ 0 3
WE
14
13
20 19
Read Enable - - - - - - - '
Clock - - - - - - - - - - '
tpel:
Clock to Data out = 5 ns (typ)
I Read Selected)
Address to Data out
=
Veca ::::
Pin
Veel
Pin 23
=
1
Vee = Pin 24
10 ns (typ)
(Clock High)
Read Enable to Data out = 3.5 ns
Vee:::: Pin 16
VEE=Pin8
Vee
= Pin
Po = 625 mW typ/pkg (No Load)
Access Time:::: 10 ns typ
12
(typ)
(Clock high, Addresses present)
PO::: 610 mW typ/pkg (No Load)
MCM10140 (90 {"I)
MCM10142 (50 fl)
MCM10148 (50 {"I)
64-Bit Random Access Memory
Address Inputs
The Chip is enabled
when
Po:::: 420 mW typ!pkg
EEl
and C E 2
inputs are at positive
logic "0"
tAccelS = 15 nl (maxI MCM10140, MCM10148
:::: 10 nl (max) MCM10142
CEI
CE2
Data Out
Data In O-:-=---------j
Write
2·26
o-----------i
Lines
LOGIC DIAGRAMS(continued)
MEMORIES
(continued) - - - - - - - - - - - - - - - - - - - - - - - ,
D out
Is is i7
1,5
~
Data Out
Buffer
Chip
Enable
Sense
J
Amplifier
r
AO------1~
A'
----2
A2~
A3~
i
.. "
~ :&
·. -1
•
•
,';0
'ON
«~
i
l
,,~
A4~~
B;, Add,." Buffe,/
1/8 Decoder
['0 ["
AS
r-L--
.
,,:::
c ,
J-
32 x 8
Memorv Cell
Array
0
u
MCM10144
256 Bit Random
A ..... M.mory
CE2 CE3
GE1
J
16
r-;-;;-
WE
tAcces.
=
30 ns (max) (Addrellinputs)
«III
!E
";:
nI
~:;
0
~Din
TRUTH TABLE
MODE
['2
A7
AS
= Pin
Vee
VEE:: Pin 8
INPUT
OUTPUT
CE
WE
Din
Write "0"
L
L
L
L
Write "1"
L
L
H
L
Read
L
H
a
Disabled
H
"
tP "" Don't Care
1,3
14[
Address
(
4
3 A,
2
5
6
7
'0
AO eEl
L
MCM10147
128 Bit Random
A ..... M.mory
Chip Enable
Chip Enable
°out
CE2
A2
A3
A4
AS
Q~OatBOut
AS
TRUTH TABLE
11
Data Input
D
WE
12
Read/Write
MODE
j
OUTPUT
WE
D
a
L
L
L
L
L
Writ.","
L
L
L
H
L
R.ad
L
L
H
H
L
4>
'"
a
Disabled
4>
L
L
H
4>
4>
L
= 415
mW tvp/pkg (No Load)
(Access = 10 ns typ (Address Inputs)
CE2
Writ. "0"
Enable
Po
INPUT
CE'
B
X
L
L
L
Word A = Word B
L
L
L
Word A > Word B
L
H
L
Word A < Word B
H
L
9
10
12
83 11
A2 13
82 14
6
Al
81
AD
80
5
4
E 15
Po = 440 mW typ/pkg
(No Load)
tpd = Data to output 6.0 ns tvp
E to output 2.5 ns typ
2·28
2 A> 8
3
A<8
INTEGRATED CIRCUITS
MECL 10.000
3-1
SERIES
MECL 10,000 series
, QUAD 2-INPUT NOR GATE
WITH STROBE
MC10l00
Advance
In~orIDatton
The MC10l00 is a quad NOR gate. Each gate has 3
inputs, two of which are independent and one of which is
tied common to all four gates. Input pulldown resistors
eliminate the need to tie unused inputs to a voltage
supply. Open emitter outputs permit wire-ORing and
direct connection to busses.
Po - 25 mW typ/gote (No Load)
~ 2.0 n. typ
tpd
POSITIVE LOGIC
NEGATIVE LOGIC
4
4
2
2
6
5
6
6
3
7
9
10
Vee1 - Pin 1
VCC2
14
12
:II:
Pin 16
VEe· Pin 8
11
3
9
10
14
11
12
16
13
15
13
2-4+"5+9
2-
'i"i"'"5i9
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS @l250 C
m
v e e1 '" vCC2
Vin
Co..
Input
+2.0 Vdc
V out
o~
r-----..,
25;
COOK
PROPAGATION DELAY
",F
Pulse Generator
Input Pulse
t+ == t- == 2.0
±. 0.2 ns
(20 to 80%1
V out
All input and output cables to the
scope are equal lengths of 50-ohm
coaKia' cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
VEE = -3.2 Vdc
Unused outputs connected to
a 50-ohm resistor to ground.
5O~hm
termination to
ground located in each
scope channel input.
SH General Information Section for packaging and maximum ratlngl.
This II advance information and specifications are subject to change without notice.
3-3
--.j....o"T-
...o...:s::
ELECTRICAL CHARACTERISTICS
(")
Eaeh MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit bo ..d and transverse air flow greater
o
o
8::I
than 500 linear fpm is maintained. Outputs
only one input and one output.
-
5
are terminated through a S().ohm resistor to
-2.0 volts. Test procedures are shown for
6
3
4
g§2
1~
The other
inputs and outputs are tested in the same
manner.
14
11
12
13
15
.....
::I
L SUFFIX
c:
CERAMIC PACKAGE
CASE 620
~
CD
TEST VOLTAGE VALUES
CVolts)
@THt
T emp8fatur.
-lOGe
+2SoC
T8SoC
w
~
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
linH
linL
Logic "1" Output Voltage
Logic "0" Output Voltage
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
Switching Times
(50-ohm load)
Propagation Delav
Rise Time
120% 10 80%1
Fall Time
C20%
10
VOH
VOL
VOHA
VOLA
Pi"
Under
Test
-lOoC
Min
-1.890
-0.810
-0.700
Min
Typ
-
8
4·
9
4·
-
-
2
14
-1.060
-1.060
-0.960
-0.960
2
14
-1.890
-1.890
-0.890
-0.890
-1.675
-1.675
2
3
14
15
-1.090
-1.090
-1.090
-1.090
-
-
-0.980
-0.980
-0.980
-0.980
2
3
14
15
-
-
-
'2+
'2_
2
-
-
-
-1.655
-1.655
-1.655
-1.655
-
0.5
-1.850
-1.850
-
-
-
-
-
-
-
-
80%)
·Individually test each input applying VIH or VI L to input under test.
-
VIHmax
Ma.
Min
Ma.
Unit
21
26
J.lAde
J.lAde
4·
9
-
-
-
245
470
-
mAde
-
J.lAde
-0.810
-0.810
-0.890
-0.890
Vdc
Vdc
-1.650
-1.650
-1.825
-1.825
-0.700
-0.700
-1.615
-1.615
-
Vdc
Vdc
4,5.9
9,10,11
-
-0.910
-0.910
-0.910
-0.910
-
Vdc
-1.630
-1.630
-1.630
-1.630
-
-1.595
-1.595
-1.595
-1.595
Vdc
-
--
-
2.0
j
-1.205
-1.500
-1.850
-1.105
-1.825
-1.035
-1.475
-1.440
VEE
-
-
-
-
-
-
t
t
ns
j
-
VILmin VIHAmin VILAmax
4·
-
-
-
-
-
-5.2
-
-
9
9
9
9
8
8
8
-
8
8
8
8
8
-
9
9
9
9
-
Pul.ln Pulse Out
-
-
-
-
-
4
VEE
-
-
2
I
-5.2
-5.2
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW:
+85 oC
+250 C
Ma.
VILmin VIHAmin VILAmax
-0.890
MC10100L Test Limits
2
2
2
t4+2t4-2+
VIHmax
8
•
CVCC)
Gnd
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
t
8
1,16
-3.2 V
+
+2.0 V
8
1,16
+
j j j j
f
'I
MECL 10,000
series~
\.---------'~
QUAD OR/NOR GATE
L -_ _....
MC10l0l
POSITIVE LOGIC
NEGATIVE LOGIC
4
4----~.-~,.----
--~~--~~~---3
-;-~~---3
t----'L__....
~---
6
r---~
10--~~,-~~-----14
__
~------6
..t:.I1~'d"~---14
10
~-"----11
r---~
13 1---~~~~-15
__~------11
P D = 25 mW typ/gate (No Load)
13-+-~1--~~----15
12
~,.<.-"'-----9
12
The MC10l0l is a quad 2-input OR/NOR
gate with one input from each gate common to
pin 12. Input pulldown resistors eliminate the
need to tie unused inputs to an external supply.
tpd = 2.0 ns tvp
9
Output Rise and Fall Time:
= 3.5
=
ns typ (10% - 90%)
2.0 ns typ (20% - 80%)
vee1 = Pin 1
VCC2 = Pin 16
VEE=Pin8
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@ 2SoC
Vee1
Vin
Input
= VCC2
+2.0 Vdc
""' t I±""'
To Channel "A"
--- - --...,
V aut
NOR
V aut
OR
To
PROPAGATION DELAY
Channel
"B"
I
+1.11 V
50%
Pulse Generator
' -____-J_ -------+0.31 V
Input Pulse
t+ = t- = 2.0 ±. 0.2 ns
V aut OR
(20'080%)
Unused outputs connected to
SO-ohm termination to
a 50-ohm resistor to ground.
ground located in each
scope channel input.
L ___ ~
_ _ ..J
V out NOR
All input and output cabl.s to the
scope are equal length, of 50-ohm
eoaxial eable. Wire length should
be < 1/4 inch from TPin to input
Din and TP out to output pin.
I-=
0.1 ,.,.F
VEE: -3.2 Vdc
See General Information section for packaging.
3-5
,+
,-
s:
ELECTRICAL CHARACTERISTICS
...o
...o
(')
Each MECL 10,000 series has been de·
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
"Ji' -
...
5
7
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
3
~4
10
only one gate. The other gates are tested
in the same manner.
iJ
15
'2
9
8
L SUFFIX
...
::J
CERAMIC PACKAGE
CASE 620
11
::J
c:
It!
c..
TEST VOLTAGE VALUES
(Volts)
@Test
VIHmax
Vilmin
VIHA min
-0.890
-0.810
-1.890
-1.205
. -1.500
+2SoC
-1.850
+85o C
-0.700
-1.825
-1.105
-1.035
-1.415
Temperature
-lOoe
MC10101l Test Limits
Pin
Characteristic
W
c»
I
Power Supply Drain Current
Input Current
Logic "1"
Output Voltage
I
I
I
Svmbol
Undo<
Test
Ie
8
I
VOL
Logic "1"
Threshold Voltage
I
VOHA
Propagation Delay
I
Rise Time
120 to IICJ%I
Fall Time
(20 to 80%1
I
12
-
-
5
5
-1.060
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
-0.890
-1.675
4
linL
Logic "0"
Output Voltage
Switching Times
(5()..ohm loadl
..
VOLA
'4+2-
I
5
5
1-1.890
f1890
I
5
5
1-
I
-1.675
-1.890 -1.675
-1.890 -1.675
1 .080
-1.080
-
1-1.080
-1.080
5
5
2
2
t4_2+
t4+5+
t4_5_
5
'2+
'5+
'2_
'5_
2
5
2
5
5
I
-
1.0
Ma.
Min
Ma.
Unit
-
20
26
-
mAde
-
-
265
535
~Adc
4
-
-
~Adc
-
"Ado
-
-0.700
Vdo
12
4
-1.850
-1.850
-1.850
-1.850
-0.980
-0.980
-0.980
-0.980
-
1.655
-1.655
-
-1.655
-
-
-1.655
-
-
3.1
~ +
1.1
Tv.
-
3.6
~ ~
1.0
+
1.1
+
2.0
j
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Min
0.5
05
-0.960
-0.960
-0.960
-0.960
-1.440
VEE
-5.2
+8S0C
+25 0 C
Ma.
-
12
VOH
I
"
linH
I
Logic "0"
Threshold Voltage
_lODe
Min
VILA max
-
-
-
-0.810 -0.890
-0.810 -0.890
-0.810 -0.890
-0.810 -0.890
-0.700
-0.700
-0.700
-1.650
-1.825
-1.615
-1.650
-1,650
-1.650
-1.825
-1.825
-1.615
-1.615
-1.615
-
--0.910
-1.630
-1.630
-1.630
-1.630
2.9
+
3.3
+
-1.825
-0.910
-0.910
-0.910
-
-1.595
-1.595
1.0
-1.595
-1.595
3.3
~ +
1.1
+
+
Vdo
+
Vdo
-
-
~Adc
3.7
+
+
Vdo
+
n,
VIHmax
12
-
VIL min
VIHA min
VILA max
Vee
-
-
-
-
4
12
8
8
8
8
-
-
-
-
-
-
-
12
4
-
-
-
-
-
-
j
-
-
1.1S
8
1,16
1,16
8
1.16
-
+
8
1,16
-
+8
1,16
+8
1,16
-
+
+
12
4
+
12
4
12
4
-
Pulse In
Pul. Out
-3.2V
+2.0V
2
2
8
1,16
4
-
1,16
1,16
-
-
-
Gnd
-
12
4
IVeel
j
5
5
2
5
2
,
+
+
j j
3:
0
...A
C
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been designed to meet the de specifications shown
-
.~.
in the test table. after thermal equilibrium
has been established. The circuit is in a
5
7
3
test socket or mounted on a printed circuit
board and tranSverse air flow greater than
500 linear fpm is maintained. Outputs are
10
terminated through a 50-ohm resistor to
13
15
"
9
':4
11
-2.0 volts. Test procedures are shown for
onlv one gate. The other gates are tested
in the same manner.
VIH max
+25 o C
-0.890
-0.810
+85o C
-0.700
MC10101P Test Limits
Pi"
Unci ..
To..
Symbol
4
12
4
12
5
5
2
2
linL
..:...
Logic "1"
Output Voltage
VOH
Logic "0"
Output Voltage
VOL
Propagation Delay
I
I
VOLA
'4+2l4-2+
l4+5+
t4-5AiseTime
(20 to 80%)
Fall Time
(20'0_1
Ma.
'2+
'5+
'2_
'5-
I
::J
....
S'
c
CD
Co
Min
TV.
Ma.
Min
Ma.
-1.060
-1.060
-1.060
-1.060
-1.890
-1.890
-1.890
-1.890
-0.890
-0.890
-0.890
-0.890
-1,675
-1.675
-1.675
-1.675
26
265
535
/JAde
/JAde
I
=
-0.810
-0.810
-0.810
-0.810
-1.650
-1.650
-1.650
-1.650
-1.630
-1.630
-1.630
-1.630
2.0
-1.825
-1.825
-1.825
-1.825
-0.700
-0.700
-0.700
-0.700
-1.615
-1.615
-1.615
-1.615
3.3
1
Vd,
~
_1.850
-1.105
-1.035
-1.825
VILAma"
-1.500
-1.475
-1.440
Vilmin
VIHA min
VILA mall(
12
4
12
12
+
+
Vdc
-1.595
-1.595
-1.595
-1.595
V'HAmi"
-1.205
Vdc
12
4
12
4
12
4
+
Vdc
+
12
4
12
4
Pulse In
4
2.9
~
+
1.1
~
-0.890
-0.890
-0.890
-0.890
-0.910
-0.910
-0.910
-0.910
-1.655
-1.655
-1.655
-1.655
1.0
VIH ma.
/JAde
-0.980
-0.980
-0.980
-0.980
1.080
-1.080
-1.080
-1.080
Unit
mAde
.Ad,
-0.960
-0.960
-0.960
-0.960
-1.850
-1.850
-1.850
-1.850
Vil min
-1.890
VEE
-5.2
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+SSoC
0.5
0.5
1-
VOHA
LogiC "'"
Threshold Voltage
Switching Times
(5().ohm load)
Min
20
linH
W
Logic "0"
Threshold Voltage
+25o C
-JO"C
IE
Input Current
g-
(VoIt.1
-3O"c
Characteristic
C
...A
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
IiiTost
Temperature
Power Supply Drain Current
...A
j
j
VEE
1,16
1,16
1,16
8
1,16
+8
1,16
+8
1.16
+
1.16
8
+
PuI.Out
(Veel
GncI
8
8
8
8
8
-3.2 V
1,16
1.16
+
+
+
+
+2.0V
1,16
1 j
f
L-._ _.....
QUAD 2-INPUT NOR GATE
"\
MECL 10,000 series
~"'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'
MC10102
POSITIVE LOGIC
The MC10l02 is a quad 2-input NOR gate,
Input pulldown resistors eliminate the need to
tie unused inputs to an external supply,
NEGATIVE LOGIC
:=::=:cr--:=::=:cr---
:~2
:~3
,O~
"~
,O~
'4
"~
12~15
2
3
'4
Po"" 25 mW typ!gate (No Load)
tpd :: 2.0 ns typ
Output Rise and Fall Time:
= 3.5 nstvp (10% - 90%)
= 2.0 n$ typ (20% - 80%)
'2~'5
13~9
'3~9
vee1 "" Pin 1
VCC2::: Pin 16
VEE=Pin8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC
Vin
To Channel "A"
Input
Pulse Generator
Input Pulse
t+ ::: t- = 2.0 ±. 0.2 ns
(20 to 80%)
Vee1
V out
NOR
= VCC2
+2.0 Vdc
1
'''',---± ---,
±""'
V out
OR
PROPAGATION DELAY
To
Channel
"S"
U>--+
~
V out OA
~
I
I
50·ohm termination to
9'0 und located in each
scope channel input,
L ___
All input and output cables to the
:~~~a~~a:~~81~~:t~~::h5~~~~:
V out NOR
~_ _ -l
l
0.1 JlF
Unused outputs connected to
a 50-ohm resistor to ground.
be < 1/4 inch from TPin to input
pin and TP out to output pin.
VeE = -3.2 Vdc
See General I nformation section for packaging.
3-8
s:
(")
ELECTRICAL CHARACTERISTICS
....
o
....
o
Each M·ECL 10.000 series has been de·
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
N
:~2
terminated through a 50-ohm resistor to
10~ 14
in the same manner.
8
-
:~3
-2.0 volts. Test procedures are shown for
onlv one gate. The other gates are tested
11
t2~15
lJ~9
=.c:
::J
::J
L SUFFIX
~
CERAMIC PACKAGE
CASE 620
I
TEST VOLTAGE VALUES
(Voltsl
@Test
T emperatur.
VIH max
VIL min
VIHAmin
\(ILAmax
VEE
-0.890
-0.810
-1.890
-1.205
-1.500
-5.2
+250 C
-1.105
-1.475
+85 0 C
-0.700
-1.850
-1.825
-1.035
-1.440
-5.2
-5.2
_30 D e
MC10102L Test Limits
Pin
w
cO
+25 o C
lOoe
Undo<
Ma.
Characteristic
Symbol
Te..
Power Supply Drain Current
'E
linH
8
12
IlnL
12
VOH
9
9
15
15
1.060 -0.890
-1.060 -0.890
9
9
15
15
9
9
15
15
I nput Current
Logic "1"
Output Voltage
Logic "0"
Output Voltage
Logic "1"
Threshold Voltage
Logic "0"
Threshold Voltage
VOL
VOHA
VOLA
9
9
15
15
Min
Min
0.5
Ma.
Min
20
26
-
-
265
-
-0.960
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+SSoC
Tvp
Ma.
-
R,seTime
120 to 80%1
Fall Time
120 to 80%)
t12+15112-15+
112+9+
t12-9115+
'9+
115_
'9_
15
15
9
9
15
9
15
9
VIH max
VEE
(Vee l
G"d
mAdc
-
8
1,16
,&lAde
12
8
1,16
8
1,16
8
1,16
-0.890
-0.890
-0.810
-0.810
-0.810
-0.810
-0.890
-0.890
-0.890
-0.700
-0.700
-0.700
-0.700
Vdc
-0.960
-0.960
-0.960
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.890 -1.675
-1.850
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.650
-1.825
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
-1.615
Vdc
-1.080
-1.080
-1.080
-1.080
-0.980
-1.060
-1.060
-
-
..
-
-0.910
-0.910
-0.910
-0.910
-0.980
-0.980
-0.980
-1.655
-1.655
-1.655
-1.655
-0.890
-
-1.630
-1.630
-1.630
-1.630
-
-
1.0
+
1.1
~
3.1
•~
3.6
1.0
+
1.1
+
2.0
j
2.9
+
3.3
+
1.0
~
~
1.1
+
+
VILmin
12
13
-1595
-1.595
-1.595
-1.595
3.3
12
13
-
Vdc
-
• j
•
12
13
12
13
12
13
+
-
-
-
-
-
-
-
-
+
8
1,16
+8
1.16
+
1.16
-
12
13
-
3.7
+
-
+
"'
VILA max
-
Vdc
-
VIHA min
12
,&lAde
SWltchmg Times
(50-ohm load)
Propagation Delay
Unit
8
+
+
+
+
Pulse In
Pul. Out
-3.2V
+2.0 V
12
15
15
9
9
8
1.16
j
15
9
15
9
j j
s:(')
...o
...
o
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 5--3
:: -----':-...0:=
10
11
~=.:[)--3
Po'" 25 mW typ/gate (No Load)
tpd:E 2.0 nt t:yp
12~15
13~9
1:
.
:[)--14 11
14
10==:[)=--
veel ""
Pin
1
VCC2 ~ Pin 16
VeE
= Pin 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @125°C
V out
NOR
PROPAGATION DELAY
Coax
Coax
+1.11 V
Input
50%
Pulse Generator
Input Pulse
t+ - t- = 2.0 ±. 0.2 ns
(20 to 80%1
SO-ohm termination to
ground located in each
scope channel input.
' - - - - - - ----+0.31 V
t:L>+
I
~
~-f
V out
OR
Unused outputs connected to
a 50·ohm resistor to ground.
V out NOR'
"--n-:'"'
VEE = -3.2 Vdc
All input end output cabl•• to the ICOpti .r. equal lengths of 50-ohm coexlal C8bl •.
Wire length should be< 114 inch from TPln to input pin end TPout to output pin.
See G.n .... ' Information Metlon for packaging and maximum r8tingl.
Thill, advance Information and .peclflc.tionl ar. subject to change without notice.
3·11
3:
ELECTRICAL CHARACTERISTICS
...o
("')
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test t~le. after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit bo.d and tr.,werse air flow greater
than 500 linear tpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. -Test procedures are shown for
...o
w
C')
o
:~2
:::l
manner.
:::l
-
;~3
only one input and one output. The other
inputs and outputs are tested in the ~me
=.
12~'5
13~9
10~'4
"~
c:
CD
a.
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
IVolts)
Ii! T",
Temp .... tur.
-30"<:
ctJ
.....
~
VIHmex
+2SoC
-0.890
-0.SI0
+8SoC
-0.700
MC10103L Test Limits
CharK.,iltic
Power SupplV Drain Current
Symbol
Ie
-1.035
-1.440
-5.2
M ••
Min
M ..
Unit
S
4"
-
-
26
245
-
mAde
-
IolAde
4"
-
-
-
IolAde
-
4"
-0.SI0
-O.SIO
-0.S90
-0.890
-0.700
-0.700
Vdc
Vdc
4,5
-1.650
-1.650
-I.S25
-1.S25
-1.615
-1.615
-
-0.910
-0.910
-
-1.630
-1.630
-
-1.595
-1.595
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
-
-
-
-
-
-
-
_30 oe
-
21
-
0.5
2
9
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
2
9
-1.S90
-1.S90
-1.675
-1.675
-1.850
-1.S50
-
-0.980
-0.9S0
VOL
-
-
VOHA
2
9
·1.080
·1.080
-
VOLA
2
9
-
-1.655
-1.655
-
-
t4+2+
t'2+9·
2
9
2
-
-
-
2.0
-
-
2
-
-
-
-
+85oC
+2SoC
-
Logic "0" Output Voltage
'2_
-1.S25
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW:
Typ
Logic "'" Output Voltage
'2+
-5.2
-5.2
Min
4"
Rise Tin.
(20%'0 SO%)
FaU Ti,...
(20%'080%)
-1.500
-1.475
M ••
'inL
VOH
Switching Times
(5O-ahm load)
Propagation oalav
-1.205
-1.105
Min
linH
Logic "0" Threshold Voltage
VEE
-1.890
-1.S50
Pi"
Undof
T. .
Input Current
L.ogic "'" Threshold Voltage
VILmin VIHAmin VILAm ••
·Individu:ellv Iftt .ach input eppIving VIH or VtL to input undar talt.
-
j
-
n.
j
VIHmax VILmin VIHAmin VILAm.x
-
-
12,13
-
-
-
-
-
-
4,5
-
-
12,13
VEE
8
8
1,16
8
8
S
1,16
1,16
1,16
1,16
1,16
1,16
1,16
S
8
8
8
8
S
Pul.ln Pul.Out -3.2 V
12,13
(Vee)
Gnd
4,5
1,16
1,16
1,16
+2.0 V
4
12
2
9
S
-
-
4
2
-
-
4
2
j j
1.16
f
QUAD 2-INPUT AND GATE
L -_ _....
'
MECL 10,000 series
"'-...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'
MC10l04
Po
= 35
lpd
=
The MC10l04 provides a very useful low power, high
speed logic AND function. High Z input pulldown resistors
allow high dc and ac fanouts and eliminate the need to
tie unused inputs to an external supply. The open emitter
outputs allow maximum flexibility in the selection of termination techniques and minimize the power requirements
when driving transmission lines. Open emitter outputs
also allow wire-ORing capability, which is very useful in
control, bussing, and communications in high speed central
processors, high speed peripherals, digital communications
systems, minicomputers and instrumentation.
mW typ/gate (No load)
2.7 ns typ
Output Rise and Fall Times:
~
3.5 ns typ (10% - 90%)
= 2.0
ns tYP (20% - 80%)
NEGATIVE LOGIC
POSITIVE LOGIC
:~2
;~3
10~ 14
10~
11
11~
12'~9
12~9
13~15
~14
13~15
veel
1
= Pin
VC C2 == Pin 16
VEE == Pin 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC
Vin
To Channel "A"
veel
= VCC2
+2.0 Vdc
Your
Your
NAND
AND
PROPAGATION DELAY
To
Channel
"8"
Input
Pulse Generator
Input Pulse
t+
= t-
=
2.0 ±. 0.2 ns
Your AND
(20 to 80%)
+1.11V~
0.1"F
J
L __
~_..J
Unused
outP~ts
connected to
a 50-ohm resistor to ground.
~0.1"F
SO-ohm termination to
ground located in each
SCOpe channel input.
VEE = -3.2 Vdc
All input and output cabl., to the scope ar. equallengthl of
50~hm
coaxial CIIbl•.
Wlr. length thould be< 1/4 inch from TP'n to input pin and TPout to output pin.
s~
G.".,..I Information Section for packaging and maximum ratings.
3-13
s:
ELECTRICAL CHARACTERISTICS
...o
...
(')
Each MECL 10,000 series has been de·
signed to meet the de spacifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are
terminated through a 5O-ohm resistor to
-
:~2
:~3
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
10~""14
in the same manner.
"~
12~9
-cp
Power SupplV Drain Current
Input Current
'E
linH·
linL
12
Logic "1"
VOH
15
.;:.
Output Voltage
VOL
Output Voltage
VOHA
15
9
9
15
15
Lgolc "0"
VOLA
Threshold Voltage
Switching Times·
(50-ohm load)
Propagation Delay
Max
VILAm..
-1.500
+2SoC
-0.810
-1.850
-1.105
-1.475
-5.2
+8S o C
-0.700
-1.825
-1.035
-1.440
-5.2
Typ
I
28
-1.060
-1.060
I
-0.890
-0.890
I
TEST VOLTAGE APPLIEO TO PINS LISTED BLEOW,
Max
Min
I
(Vec'
Mu
35
mAdc
265
220
/JAdc
/JAdc
0.5
-0.960
-0.960
-0.810 1-0.890 1-0.700
-0.810
-0.890
-0.700
-1.890 1-1.675
-1.890
-1.675
-1.850
-1.850
-1.650 1-1.825
-1.650
-1.825
-1.080
-1.0BO
-1.080
-1.080
-0.980
-0.980
-{I.980
-0.980
-0.910
-0.910
-0.910
-0910
-1.655
-1.655
-1.655
-1.655
9
9
15
15
Unit
-1.630
-1.630
-1.630
-1.630
-1.615
-1.615
I
VIH max
VILmin
t12+15+
t12-9+
9
t13~15+
15
9
t13+9Rise Time
(20 to 80%1
19+
15
9
t15-
15
19_
9
t15+
Fall Time
(20 '080%1
15
15
9
1.0
4.3
12.13
2.2
4.0
1.0
4.2
1.5
37
~
j
beh ..... ir:n~~y for K and linH Ylllu~.
l
T
l
1.5
8
8
1.16
1.16
8
1.16
8
1.16
1,16
Vdc
12,13
Vdc
12
13
12
13
13
12
12
3.5
1.5
1.16
1.16
~
~
Gnd
8
Vdc
~
-1.595
-1.595
-1.595
-1.595
VEE
Vdc
1,16
Vdc
2.7
2.7
·Inputs 4,7, 10, and 13 will behave similarly for ac and linH values.
12wil~
1.0
VILAl'ftllx
12
/JAde
Vdc
VIHAmin
12.13
13
I
I
-
-
+1~
'12-15112+9-
InputI5.S. 11 • .,d
Min
VEE
-5.2
VIHAmin
-1.205
+850 C
12
13
9
Logic "1"
Threshold VOltage
I
+25 0 C
8
9
Logic "0"
Min
Co
Vil min
-1.890
MC10104L Test Limits
I Tnt
c:
(I)
VIH m ••
-0.890
-30"<:
Symbol
....
::J
3"
Volts
ilTost
Temperatur.
Ch..acteristic
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
13~15
-lOOC
~
nO
L SUFFIX
3.6
t
-
-
I
I
12
13
8
1.16
-
~
~
8
1.16
12
13
~
~
Pulse In
Pul_Out
-3.2 V
+2.0V
12
15
15
9
9
8
1.16
13
12
13
12
~
13
13
I
I
-
15
9
15
9
t
15
9
3:.
ELECTRICAL CHARACTERISTICS
(')
-"
E.... MECL 10.000 ......... been de·
ligned to ..-1 the de _ificalionl shown
in the test bbll, 8fter th_mll equilibrium
. . been ntablilhed. The circuit is in I
test mcket or mounted on I printed circuit
boerd and ,,.nwe,.. lir flow gr••tar than
500 lin. . fpm is mlinhined. Outputs .r.
••min.ted through • 5O-ohm resistor to
•
:~2
~~3
-2.0 volts. Test procedures ara shown for
only ona gate. The other gates ar. tested
in the ume manner.
,.~11~'4
12~9
13
o
-"
o.p.
8:J
P SUFFIX
...s·
PLASTIC PACKAGE
CASE 648
c
CD
a.
TEST Val TAGE VALUES
15
Volts
@Test
Temperatur.
-30 oe
+25 o C
+85"c
MC10104P Test Limits
-lOoe
Ch..8Cteriscic
Power Supply Drain Current
C:J
.....
Input Current
U1
Symbol
IE
linHlinL
Logic "1"
Output Voltage
VOH
Logie "0"
OutPUt Volt.
Logic "1"
Threshold Voltage
Val
Lgoic "0"
Threshold Voltage
Switching Tim.(50-ohm 1... 1
Propegetion Delay
VOHA
VOLA
Min
Mo.
Min
Ty.
8
12
13
-
28
-
-
12
15
9
-
-
-1.()60
-1.060
-0.890
-0.890
0.5
0.960
-0.960
15
9
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
9
9
15
15
-1.080
-1.080
-1.080
-1.080
-
-0.980
-0.980
-0.980
-0.980
-
-1.655
-1.655
-1.655
-1.655
-
9
9
15
15
-
-
-
-
-
-
VIL min
VIHA min
-0.890
-0.810
-1.890
-1.850
-0.700
-1.825
-1.205
-1.105
-1.035
Rise Time
120 to 110%1
t'3"'5+
'13+9t15+
t9+
FeU Time
120 t.80%1
tl5t9-
15
15
9
9
15
9
15
9
15
9
-
-
-lnputs4, 7.10. and 13 will behave simil.ly for ac and I inH valulS.
Input'S. 6, " , and 12 will behave similarly for
a: and linH vatues.
1.0
2.2
~
2.7
2.7
1.5
2.0
VEE
-5.2
-1.475
-52
-1.440
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BlEOW,
1Veel
Gnd
M••
Min
M ••
Unit
VIH max
Vil min
VIHAmin
VILA max
VEE
35
265
220
-
mAde
-
-
-
/lAde
J.lAdc
12.13
13
-
jJAdc
-
-
8
8
8
1.16
-
-
-
-
-0.810
-0.810
0.890
-0.890
-0.700
-0.700
Vdc
Vdc
12.13
8
8
1.16
1.16
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Vdc
12.13
-
-0.910
-0.910
-0.910
-0.910
-
Vdc
12
13
-1.630
-1.630
-1.630
-1.630
-
~
-1.595
-1.595
-1.595
-1.595
Vdc
-
-
-
~
-
12
-
-
12
13
-
-
4.0
-
I
-
-
3.5
! ! !
-
-
-
ns
1.16
1.16
-
-
8
1,16
-
-
8
1.16
-
-
8
1,16
12
13
8
1,16
13
12
13
12
-
~
~
8
1.16
~
~
-
-
_.
-
-
12
13
Pulse In
Pulse Out
-3.2 V
+2.0V
12
15
15
9
9
15
9
15
9
15
9
8
1.16
13
~
12
12
-
-
-
-
+1.11 V
t'2+15+
tI2-15'12+9t12-9+·
VILA max
-1500
+8SoC
+25"c
Toot
VIH mall(
t
-
-
-
~
13
13
,I
MECL 10,000 series
TRIPLE 2-3-2 INPUT
OR/NOR GATE
MC10l05
The MC10l05 isa triple 2-3-2 input OR/NOR
gate. Input pulldown resistors eliminate the need
to tie unused inputs to an external supply.
POSITIVE LOGIC
NEGATIVE LOGIC
:~:
4~3
1:~~
1:~~
13~14
13~14
12~15
12~15
5~2
11~
11~
Po
= 30 mW typ/gate
(No Loa(H
tpd = 2.0 ns typ
Output Rise and Fall Time
=::: 3.5 ns typ (10%-90%)
"" 2.0 ns typ (20%-80%)
veel : :
Pin
1
VCC2 = Pin 16
VEe =Pin8
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS @ 25°C
VCC1 = VCC2
V out
V out
+2.0 Vdc
NOR
OR
PROPAGATION DELAY
Coax
Input Puis.
t+ = t- "" 2.0 ±. 0.2 ns
(20 to 80%1
50-ohm termination to
ground located in each
scope channel input.
Coax
~
~
~
L _ _ _
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
_ __
~
I
-I
V out OR
Unused outputs connected to
a 50-ohm resistor to ground.
V out NOR
0.1 jJF
_
-
VeE = -3.2 Vdc
s .. Ganeral Information _c:tion for
packa"ln".
3-16
3:
ELECTRICAL CHARACTERISTICS
...,
(')
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermat equi·
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input and one output. The other
inputs and outputs are tested in the same
manner.
o...,
~
8
::J
....
::J
c:
-
4~3
'~2
9
10~~'
11~
lJ~14
12~15
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(V ....,
@IT ...
Temperllture
C:-l
.....
'-I
Characteristic
Symbol
Pin
Under
Te"
Power Suppty Drain Current
Ie
8
tinH
4
tinL
4
tnput Current
-3IJOe
Min
Max
VILmin
VIHAmin
VILA max
VEE
-0.890
-1.890
-1.205
+2SoC
+8So C
-0.810
-1.850
-1.105
-0.700
-1.825
-1.035
-1.500
-1.475
-1.440
-5.2
-5.2
5.2
MCl0105L Test Limits
+25 o C
+8Soc
Min
TVp
-
17
0.5
LogiC "1"
Output Voltage
VOH
3
2
-1.060 -0.890
-1.060 -0.890
-0.960
LogiC "0"
Output Vottage
VOL
3
2
1.890 -1.675
-1.890 -1.675
-1.850
-1.850
-
LogiC "'"
Threshotd Voltage
VOHA
3
2
-1.080
-1.080
-
-0.980
-0.980
-
LogiC "0"
Threshotd Voltage
VOLA
-
-1.655
-1.655
-
3.1
1.0
3
2
VIH max
-lOoe
-0.960
-
Ma.
21
265
Min
M..
Unit
VIH max
VILmin
mAdc
-
-
/JAdc
4
-
-
/JAdc
-
4
4
-
-
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vd,
Vd,
-1.650
-1.825
-1.825
-1.615
-1.615
Vd,
Vd,
-0.910
-0.910
-
-
Vd,
Vd,
-1.595
-1.595
Vd,
Vd,
-1.650
-1.630
-
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
-1.630
4
-
-
-
-
-
-
-
SWitching Times
(50-ohm toad)
Propagation Detay
Rise Time
(20 to 80%)
Fait Time
(20 to 80%1
t4+3_
t4-3+
14+2+
14_2_
3
3
2
2
1.0
'3'
'2'
'3_
'2-
3
2
1.1
3
2
+ 3.6+
+
1.1
~ ~ ~
2.0
j
2.9
+
3.3
1.0
+
1.1
~ ~
3.3
+
3.7
~
"'
I
-
-
-
-
-
VIHA min
VILA max
VEE
(Vee)
Gnd
8
1.16
-
-
8
8
1.16
-
4
4
4
-
-
1,16
8
8
1,16
8
8
1,16
1,16
1,16
1,16
4
8
8
8
8
Pulse In
Pul.Out
-3.2 V
+2.0V
4
3
3
2
2
8
1,16
I
3
2
3
2
j
1.16
1,16
1.16
I
3:
ELECTRICAL CHARACTERISTICS
(')
--o
--~
Each MECl 10,000 series circuit has been
designed to meet the de specifications
shown in the test table. after thennal equilibrium has been established. The circuit is
in 8 test socket or mounted on a printed
circuit bo_d and transverse air flow greater
th., 500 line.. fpm is maintained. Outputs
are terminated through a S(k)hm resistor to
-2.0 volts. Test procedures are shown for
8
...5'
:I
c:
~
only one input and one output. The other
-
inputs and outputs are tested in the same
manner.
'~3
5~2
.~.
10~7
"1~~14
':Z~'5
PSUFFIX
PLASTIC PACKAGE
CASE 648 .
TEST VOLTAGE VALUES
IVoIts)
'fl
"Test
Temper8lure
(XI
--
Pin
Under
Chllracteristic
Power Supply Drain Current
Input Current
SVmbol
Test
'E
8
4
linH
linL
Logic "1"
Output Voltage
Logic "0"
Output Voltage
VOH
•
-300e
Min
Max
-
-
-
MC10105P T_ limits
+2SoC
+850 C
Min
Ma.
Min
Ma.
TV.
17
21
-
-
-1.890 -1.675
-1.890 -1.675
-1.850
-1.850
3
2
-1.080
-1.080
-0.980
Logic "0"
Threshold Voltage
VOLA
3
2
-
-1.655
-0.980
-1.655
-
-
1.0
-1.850
+8SoC
-0.700
-1.825
-5.2
-5.2
5.2
(Vee l
Uni1
VIH max
mAde
-
VIL min
VIHAmin
4
-
-0.810
-0.810
-0.890
Vdo
Vdo
-
-0.890
-0.700
-0.700
-
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdo
Vdo
•
-
-
-
-
-0.910
-0.910
-
Vdo
Vdo
-1.630
-
-1.595
-1,595
Vdc
Vdo
2.9
-
-1.630
4
-
Rise Time
(2010~)
Fell Time
(2010_1
'4+314-3+
14+2+
14-2-
3
3
2
2
'3+
'2+
3
2
'3-
3
2
'2_
-
-
-
-
-
•~
1.1
2.0
j •~
3.3
-
-
-
-
n,
j
-
VeE
Gnd
-
8
1,16
-
8
8
1,16
8
8
1.16
1.16
-
-
-
-
8
8
1,16
1,16
4
•
-
8
8
1,16
1,16
-
4
8
8
1,16
1,16
Pulse In
Pulse Out
-3.2 V
+2.0V
4
3
3
2
2
8
1,16
-
-
-
1,16
-
4
-
-
VILAm8x
-
Switching Times
(50-ohm load)
Propagation Delay
-1.440
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
-
-
-0.810
-1.500
-1.475
-",Adc
-
3
2
+25o C
-1.205
-1.105
-1.035
-
-
VOL
-1.890
-
265
VOHA
VeE
-0.890
4
-
Logic "1"
Threshold Voltage
VILA max
_lODe
j.lAdc
-
-1.060 -0.890
VIHA min
-
0.5
-0.960
-0.960
-1.0GO -0.890
VIL min
-
-
3
2
VIH max
j
3
2
3
2
II
MECL 10,000 series
TRIPLE 4-3-3 INPUT
NOR GATE
MC10106
The MC10l06 is a triple 4-3-3 input NOR
gate_ Input pulldown resistors eliminate the need
to tie unused inputs to an external supply_
POSITIVE LOGIC
NEGATIVE LOGIC
1:~--2
1:~2
11~
11~
12~
13
15
12~
13~15
14
14
veel
=
Po "" 30 mW tvp/gata (No Load)
tpd = 2.0 ns typ
n.
Output Rise and Fall Time
: 3_5
typ (10% - 90%)
::z: 2.0 ns typ (20% - 80%)
Pin 1
VCC2 "" Pin 16
Vee = Pin 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C
Vee,
Vee2
~
+2.0 Vdc
Coax
Input
''''i~''''
r--
PROPAGATION DELAY
Coax
--,
,.-----+1.11 V
I
I
I
-----+0_31 V
I
Input Pulse
t+:::; t- = 2.0±. 0.2 ns
120 to 80%)
5O~hm
termination to ground lo-
cated in each scope channel input.
~!
~nu"'d
'- --ti
_..J
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
N
V
~
< 1/4 inch from TP in to input
out
outputs connected to
• 50-ohm ,.sisto, to g,ound_
!
~O.II'F
pin and TP out to output pin.
Vee' -3.2 Vdc
&H Oen.,.llnformatlon section for packaging.
3-19
ELECTRICAL CHARACTERISTICS
s:
n
.....
o
.....
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
o0)
than 500 linear fpm is maintained. Outputs
:~3
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input and one output. The other
8::J
~,
::J
7
inputs and outputs are tested in the same
manner.
C
9~2
-
IO~
11
12~'5
13~
14
(I)
Co
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Volts)
ctJ
@Test
'"0
Temperature
_lOGe
+250 C
+8SoC
Characteristic
1 Symbol
Power Supply Drain Current
Input Current
l
'E
Pin
Und..
Te ..
-3O"c
Min
+2SoC
Max
Min
8
+85o C
Min
Max
-1.890 -1.675
-1.890 -1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Vdc
-1.080
-1.080
-0.980
-{).980
-0.910
-0.910
-1.655
-1.655
-1.630
-1.630
-1.595
-1.595
1.0
3.1
1.0
t4-3+
1.0
1.1
3.1
3.6
1.0
1.1
1.1
3.6
1.1
1
2.0
1
2.9
1.0
3.3
2.9
1.0
3.3
3.3
1.1
3.7
3.3
1.1
3.7
VIH max
VILmin
VIHAmin
VilA max
1,16
4
9
8
8
1,16
1,16
Vdc
Vdc
8
8
1,16
1,16
Vdc
Vdc
8
8
1,16
-3.2 V
+2.0 V
Switching Times
(50-ohm load)
14+3-
1VCCI
Gnd
1,16
3
2
Threshold Voltage
VEE
1.16
VOL
12111080%'
-5.2
-5.2
1.16
Logic "0"
,~
-1.440
~Adc
Vdc
Vdc
'3+
-1.035
1,16
-0.890 -0.700
-0.890 -{).7oo
120'080%'
-1.825
.,Adc
-0.810
-0.810
Rise Time
-0.100
265
0.5
Unit
-0.960
-{).960
Fa.. Time
-1.105
mAde
-1._ -0.890
-1.060 -0.890
Propagation Delay
-1.850
21
3
2
VOHA
-5.2
-0.810
-1.500
-1.475
17
VOH
VOLA
VEE
-1.205
Max
Logic "'"
Logic "0"
VILAma.
-1.890
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
4
Logic "'"
Threshold Voltage
VIHA min
-0.890
TV.
l,n H
Output Voltage
VILmin
MCl0106L Test Limits
ImL
Output Voltage
VIH max
1
1,16
Pulse In
Puis. Out
4
3
1
1 1 1
1.16
ELECTRICAL CHARACTERISTICS
3:
n
Each MECl 10,000 ..,ies circuit has been
designed to meet the dc specifications
shown in the test table, after thennal equilibrium has been established. The cirC1lit is
...a
C
...a
C
en
in a test socket or mounted on 8 printed
circuit bo ..d and tr.,sverse air flow greater
th... 500 linear fpm is maintained. Outputs
g
are terminated through a 50-0hm resistor to
-2.0 volts. Test procedures are shown for
....
:l
:;'
:~3
only one input and one output. The other
inputs and outputs are tested in the same
manner.
t:
CD
Co
-
7
9
'0~
11~2
12
'3~
14~'5
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Volts)
Co)
@Test
~
Temperature
_30 D e
+250 C
+8SoC
Pin
Chlnct.,istie
Power
Sup~y
I
Test
l
4
LogiC "1"
Output Voltage
VOH
3
LogiC "0"
Output VOltage
VOL
LogiC "1"
Threshold Voltage
a"
Logic ..
Threshold VOltage
-3O"c
Min
Mo.
Rise Time
120'080%1
Fall Time
120'080%1
-52
-0.810
-1.850
-1.105
-1475
-52
-0.700
-1.825
-1.035
-'440
-52
c
Max
(Vee'
Unit
mAde
1.16
265
J..IAde
1.16
J..IAdc
1.16
-0 700
-0700
Vdc
Vdc
1,16
1.16
-1.615
-1.615
Vdc
4
Vdc
9
0.5
-0.890
-0.810
-0.890
-1.890 -1.675
-1.890 -1.675
-1.850
-1.650
2
-1.850
-1.650
VOHA
3
-1.080
2
-1.080
VOLA
3
-0.980
-0.980
-1.825
-1.825
-0.910
-0.910
-1.655
-1.655
-1.630
-1.630
-1.595
-1.595
VIH max
VIL min
VIHAmin
1.0
t4-3+
1.0
'3'
1~
1
1.1
1.1
2.0
VILA max
VEE
8
8
1,16
1,16
Vdc
Vdc
1,16
1.16
Vdc
1.16
1,16
vdc
Pulse In
t4+3-
Gnd
21
Switchmg Times
ISO-ohm loacl)
Propagation Delay
-1.500
17
Min
-0.810
2
VEE
-1.205
Max
-0.960
--0.960
3
VILA max
-1.890
TVp
-1.060 -0.890
-1.060 -0.890
2
VIHA min
-0.890
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+8So
+2SoC
Min
Im H
ImL
Vilmin
MC10106P Test Limits
Ie
Oram Current
Input Current
Und.
Symbol
VIH max
2.9
4
PulseOul
-3.2 V
+-2.0 V
1.16
2.9
1
3.3
3.3
1
1
1 1 1
MECL 10,000 series
TRIPLE 2-INPUT EXCLUSIVE
"OR"/EXCLUSIVE "NOR"
MC10l07
POSITIVE LOGIC
NEGATIVE LOGIC
:~:
4~2
9~11
9~11
5~3
7~IO
7~IO
'4~'2
14~12
15~13
5)
(4 • 5)
3 : (4 •
2 :
+ (4 • 5)
+ (4 • 5)
This three gate array is designed to provide
the positive logic Exclusive OR and Exclusive
NOR functions in high speed applications.
Input pulldown resistors eliminate the need to
tie unused inputs to VEE·
15~13
3 :=; (4 .5)
2: (4 • 5)
vee1 "" Pin 1
Po
+ (4 • 5)
+ (4 • 5)
= 40 mW typ/gat8 (No
Load)
tpd "" 2.5 ns typ
Output Ri .. and Fall Time.
VCC2::::S Pin 16
"" 2.5 n. typ (20% to 80%)
"" 3.5 ns typ (10% to 90%)
VeE"" Pin 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
V out
VCCI : vCC2 EXCLUSIVE+2.0 Vdc
NOR
V out
EXCLUSIVEOR
PROPAGATION DELAY
Coax
Coax
-+1.11 V
Input Pulse
t
+
= t-
""
V out EXCLUSIVE-NOR
2.0 ± 0.2 ns
(20 to 80%)
t+
t-
50-ohm termination to ground located in each scope channel input.
V out EXCLUSIVE-OR
All input and output cables to the
scope are eQual lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
VIH
VEE: -3.2 Vdc
Unused outputs connected to
8
50-ohm resistor to ground.
See General I nformation section for packaging.
3-22
~
ELECTRICAL CHARACTERISTICS
-
Each MECL 10,000 _ies circuit has been
designed to meet the de specifications
shown in the test table, after thermat equilibrium has been established. The circuit is
in a test socket or mounted on a printed
4~'
5~3
9~11
7~'O
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
14~12
15~13
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
n
...a
o...a
LSUFFIX
...,o
CERAMIC PACKAGE
CASE 620
nO
::J
....
5'
c:
a
TEST VOLTAGE VALUES
IVoitsl
• Test
T-.nperature
-3O"c
+2SoC
+SSoC
W
r\.)
I
Characteristic
_30°C
Under
TH'
Symbol
Min
W
LogIC "0"
Threshold Voltage
VOL
I
VOHA
I
I
-1.060
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
-0.890
-0.960
-0.960
-0.960
...(}.960
-1.890
-1.890
-1.890
-1.890
-1.675
-'.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.850
H
,--
-1.2(1)
-1.500
-1.105
-1.035
-1.475
-0.810
-0.700
M.,.
Unit
VIH m..
mAde
All Inputs
265
220
j.lAdc
j.lAdc
Min
Inputs
4, 90r 14
to either
Output
Inputs
5,7, or 15
to either
Output
Rise Time
1.1
3.8
j j
I
VIL min
VIHAmin
12Oto~)
"IndIVidually test each Input applymg VI H or VI L to Input under test
"Any Output
VEE
-5.2
-5.2
I
-5.2
VILAmu
VEE
-0.890
-0.890
Vd,
-0.890
-0.700
-0.700
-0.700
-0.700
-1.825
-1.825
-1825
-1.825
-'.615
-1.615
-1.615
-1.615
Vd,
-0.890
-0.910
-0.910
-0.910
-0.910
Mo"
Ty.
Mu
11
2.0
3.7
~
2.8
+
1,16
1,16
4,5
•
5
4,5
40
+
+
j
j
1,16
+
8
1.16
8
+1.1 V
Pulsetn
Pu . . Out
5,7,15
Input
4,9,or
Correspondino
Ex-OR/E.·NQR
Outputs
~
4,9,14
••
Input
5.7, or
15
1.1
3.5
2.5
3.5
3,8
4,9,14
~
Any Input
1.1
3.5
2.5
J.5
3.8
4,9,14
Any Input
~
8
+
Vd,
Unit
1.'
Gnd
1.16
Vdo
-1.595
-1.595
-1.595
-1.595
-1.630
-1.630
-1.630
-'.630
+
tVee'
1,16
120 to 80%1
Fall Time
-1.440
I
.Ade
-0.810
-0.810
-0.810
-0.Bl0
-1.650
-1.650
-, 650
-1.650
-1.655
-1.655
-1.655
-1.655
SWitching Times 150 H Load)
,+-
-1.890
-1.850
-1.825
28
...(}.980
-0.980
-0.980
-0.980
-1.080
-1.080
-1.080
-1.080
VOLA
Propagation Oelay
VILAm..
-0.890
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
0.5
VoH
Logic "0"
Output Voltage
LogIC "1"
Threshold Voltage
Mox
Min
4,9,14
5,7,15
lin L
Logic "1"
Output Volt&ge
VIHA min
+asoc
+25"<:
Mu
'E
lin H
',p", Cu,,,",
VIL min
MC10107L T . . Limits
Pin
Power Supply Dram Current
VIHmax
Corresponding
e • .oR/h·NQR
Outputs
Corresponding
b-OR/Ex NOR
Outputs
+
-3.2 V
8
+
+
1.16
+
1.16
+
+2.0 V
1.16
s:
ELECTRICAL CHARACTERISTICS
("')
Each MECL 10.000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit bo..d and transverse air flow greater
-
4~2
S~3
9~11
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
7~1()
14~12
-2.0 volts. Test procedures are shown for
15~13
only one gate. The other gates are tested
....
in the same manner.
o....
o.....
PSUFFIX
CERAMIC PACKAGE
CASE 648
8::J
....
s·
c
CD
Co
TEST VOL TAGE VALUES
(Volts)
.Tut
Temper.ture
-3O"C
'.
Power SupplV Drain Current
W
I,np ", Cu",",
Min
-3O"c
-0.890
-1.500
-5.2
-0.810
-0.700
-1.890
-1.850
-1.825
-1.205
+25 o C
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
Min
-1.060
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
-0.890
-0.960
-0.960
-0.960
-0.960
Logic "0"
Output Voltage
VOL
-1.890
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.850
-1.080
-1.080
-1.080
-1.080
VOHA
I
Switchinll Times (50 n Load)
I
Propagation Oelav
VOLA
,++
,+,-+
I
I
-1.630
-1.630
-1630
-1.630
-1.655
-1.655
-1.655
-1.655
"
-0.890
-0.890
-0.890
-0.890
-0.700
-0.700
-0.700
-0.700
-1.815
-1825
-1.825
-1.825
-1.615
-1615
-1.615
-1.615
-0.910
-0.910
-0.910
-0910
-0.980
-0.980
-0.980
-0.980
Min
Inputs
4,9 or 14
to either
Output
-0.810
-0.810
-0.810
-0.810
-1.650
-1.650
-1650
-1.650
TVO
Mu
2.0
3)
Unit
VIHma.
mAde
All Inputs
VIL min
.uAdc
Vd,
'.'
+
Vd,
+
S
',S
+
+
1,16
+
1,16
+
Put. Out
-3.2 V
+2.0 V
,.
Corresponding
Ex-ORfEx·NOA
Outputs
8
1,16
Input
5,7, or
'S
Corresponding
Ex-OAfEx-NOR
Outputs
Anv Input
Fall Time
(20 to
2.S
3.S
4,9,14
Anv Input
VIH or Vil to input under test.
+
+
Input
4,9,or
4,9,14
input~lvinll
1.16
Pulse In
3.
·lndivkiu"ly t ..t each
··Any Output
+
8
5,7,15
2.'
*"'1
1,16
+1.1 V
Rise Time
(201080%)
,+-
2.8
1,16
8
+
8
+
Vd,
Unit
8
+
Vd,
-1.595
-1.595
-1.595
-1.595
Gnd
1,16
1,16
1,16
4,9,14
Inputs
5.7, or 15
to either
Output
V ••
8
i
i j
,-,++
VILA ma.
VIHAmin
_Ade
j.lAdc
O.S
VOH
Vee
IVee·
M..
220
lin L
LOllic "0"
Threshold Voltage
Mi"
26.
4,9,14
5,7,15
Logic "1"
Output Voltage
Logic "1"
Threshold Voltage
M ••
VILA
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+85o C
+25"1:
M..
28
lin H
~
~
T ..,
I
VIHAmin
MCl0107P Tnt Limi"
Pin
Undo,
Symbol
m."
VIL min
+85o e
Ch....:: ....... ic
I
VIHm.JII
+
i
I
Corresponding
Ex-OR/Ex NOR
Outputs
MECL 10,000 series
DUAL 4-5-INPUT
"OR/NOR" GATE
MC10109
POSITIVE LOGIC
The MC10l09 is a dual 4-5 input OR-NOR
gate which is pin compatible with the MECL III
MC1660L dual OR-NOR gate. All inputs are
terminated by a 50 k ohm resistor to VEE
eliminating the need to tie unused inputs low.
NEGATIVE LOGIC
:~3
:§=t=3
7
7
6
2
11:~
12
6
2
1:~
14
11
15
12
13
14
15
tpd
= 2.0 ns typ
PO::: 30 mW tvp/gate (No Load)
13
Output Rise and Fall Times
(10%t090%13.5 ns
(20% to 80%) 2.0 ns
vee1 = 1
VCC2" 16
VEE" 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC
Veel
Vin
To Channel "A"
=
V out
NOR
VCC2
i
+2.0 Vdc
,,»
£ ±""'
r---
V out
OR
PROPAGATION DELAY
To
Channel
··8"
---,
+1.11 V
50%
'--_ _....L_ - - - +0.31 V
I
Input Pulse
t+
:r::
t- :.: 2.0 ±. 0.2 ns
(20 to 80%)
50-ohm termination to
. ground located in each
scope
channel input.
.
~
L ______
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
V out OR
Unused outputs connected to
a 50-ohm resistor to ground.
t+
t-
V out NOR
J
~
I
'
-=
0 1 ~F
Vee::: -3.2 Vdc
See-Generellnformation section for packaging.
3-25
3:
ELECTRICAL CHARACTERISTICS
(')
.....
o.....
Each MECL 10.000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit bo .. d and tranwerse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a SG-ohm resistor to
-2.0 volts. Test procedures are shown for
~
8"
::J
.+
:i'
c:
:§=t'
only one input and one output. The other
inputs and outputs are tested in the same
manner.
•
~
-
2
7
9~
10
11
14
12
15
13
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Voltsl
I;> Test
W
VIHmu
VILmin
VIHA min
VILA max
-0.890
-1.890
-1.206
-1.500
+25"<:
-0.810
-1.850
-1.105
-1.475
+8SoC
-0.700
-1.825
-1.035
-1.440
Temper.tur.
_lOGe
~
CD
Characteristic
I Symbol
Power Supplv Drain Current
Input Current
l
Pin
Under
Test
MC10109L TN Limits
_JaDe
Min
+250 C
Max
Min
'E
VOH
Low Output Voltage
VOL
High Threshold Voltage
VOHA
Low Threshold Voltage
VOLA
-1.060
-H160
-1.890
-1.890
-1.080
-1.080
-0.890
-0.890
-1.675
-1.675
Max
14
mAde
265
JlAdc
-0.810
-0.810
1.650
-1.650
-1.630
-1.630
-1.655
-1.655
-0.890 -0.700
-0.890 -0,700
-1.825 -1.615
-1.825 -1.615
-0.910
-0.910
-1.595
-1.595
SWitching Times
(50-ohm load)
Propagation Delay
VIH max
Vilmin
VIHA min
14+314_3+
Rise Time
420 to 80%)
12+
13+
Fait Time
(20 to
'2'3_
1.0
3.1
1.0
l
3.6
~
~
1.1
1.1
l
J
l
2.0
~
-5.2
-5.2
2.9
10
~
1.1
3.3
~
3.3
~
3.7
l l l
VILA rna.
VEE
8
{Veel
Gnd
1.16
,I.IAdc
1.16
1.16
Vdc
Vdc
Vdc
Vdc
1.16
1.16
1.16
1.16
Vdc
Vdc
1.16
1.16
Vdc
Vdc
1.16
1.16
Pulse In
14+2+
14-2-
80%.
Unit
11
-0.960
-0.960
-1.850
-1.850
-0.980
-0.980
-5.2
I
+85D C
Min
Max
0.5
linL
High Output Voltage
VEE
TEST VOLTAGE APPLIED TO PINS BELOW:
TV.
ItnH
I
Pul .. Out
-3.2 V
+2.0 V
1,16
3:
n
.....
o.....
ELECTRICAL CHARACTERISTICS
_ie.
Eoch MECL 10,000
circuit ho. been
designed to meet the de specifications
shown in the test table, after thermal equilibrium hes been established. The circuit is
in I test socket or mounted on a printed
circuit bo.d and tranwerse air flow greater
th., 500 line... fpm is maintained. Outputs
are terminated through. SO-ohm resistor to
-2.0 volts. Test procedures are shown for
o
c.c
8
....
::l
:¥J
onlv one input and one output. The other
inputs and outputs are tested in the same
•
manner.
--
2
7
9~
10
11
14
12
15
13
3'
c
~
PSUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Volts)
iiITost
Temperatur.
_lOGe
w
N
"
+25oC
+85·C
MCl0109P Test Limits
Pin
-:ID"c
Under
Symbol
T_
Ie
Input Current
linH
High Output Voltage
VOH
CharK,.ristie
Power Supply Drain Current
linL
Low Output Voltage
M ..
8
11
14
4
4
-
265
-
-0.810
-0.810
2
3
VOLA
2
3
-
2
Low Threshold Voltage
M ••
-
VOHA
2
3
High Threshold Voltage
M;"
-1.060
-1.060
-1.890
-1.890
-1.080
-1.080
VOL
+25°C
Typ
3
VIH max
-0.890
-0.810
-0.700
Min
0.5
-0.890 -0.960
-0.890 -0.960
-1.675 -1.850
-1.675 -1.850
-0.980
-0.980
-1.655
-1.655
-
-
-
-1.630
-1.630
Rise Time
120'.80%1
Fall Time
120'.80%1
t4+2+
t4-2t4+3_
14!.3+
'2+
'3+
'2_
'3_
2
2
3
3
2
3
2
3
-
-
-
-
1.0
l
l
1.1
2.0
2.9
+85o C
Min
M..
-
1
3.3
l
-
-1.475
-5.2
-1.035
-1.440
-5.2
1VCCI
Unit
VIH max
mAde
-
,.,.Ade
4
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vll min
-
-
n,
j
VIHAmin
VILA mu:
4
.uAdc
-0.890 -0.700
-0.890 -0.700
-1.825 -1.615
-1.825 -1.615
-0.910
-0.910
-1.595
-1.595
-
-1.105
-1.850
-1.825
4
4
-
-
-
Switching Times
(50-ohm load)
Propagation Delay
VEE
-5.2
VILAmu
TEST VOLTAGE APPLIED TO PINS BELOW:
-1.650
-1.650
-1.500
-1.890
VIHAmin
-1.205
Vel min
-
-
-
_.
-
-
4
Gnd
8
8
1.16
1.16
8
1.16
8
8
8
8
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
4
-
8
8
8
8
Pulse In
Pul.Out
-3.2 V
+2.0 V
4
2
2
3
3
8
1.16
-
-
-
-
VEE
j
4
4
2
3
2
3
I
MEel 10,000 series
DUAL 3-INPUT 3-0UTPUT
"OR"GATE
MClono
POSITIVE LOGIC
NEGATIVE LOGIC
~~2
7
3
4
1~~12
1~~12
11
13
11
13
14
14
The Mel 011 0 is designed to drive up to three
transmission lines simultaneously. The multiple
outputs of this device also allow the wire·"OR"·
ing of several levels of gating for minimization
of gate and package count.
The ability to control three parallel lines
from a single point makes the Me 10 11 0 particu'
larly useful in clock distribution applications
where minimum clock skew is desired. Three
Vee pins are provided and each one should
be used.
Po = 80 mW typ/gate (No Load)
tpd "" 2.4 ns typ (All Outputs Loaded)
veel
VCC2
Output Rise and Fall Time: (All Outputs Loaded)
"" 2.2 ns typ (20% to 80%)
= 4.0 ns typ (10% to 90%)
= 1, 15
= 16
VEE = 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
PROPAGATION DELAY
Coax
r-----
Input
- - - - - +0.31 V
Pulse Generator
Input Pulse
t+ = t- '"" 2.0 ±. 0.2 ns
(20 to 80%)
5O-ohm termination to ground 10'
cated in each scope channel input.
All input and output cabl •• to the
scope are equal lengths of 50·oh m
coaxial cabl.. Wire 'ength should
be < 1/4 inch from TPin to input
+1.11 V
VEe = -3.2 Vdc
pin and TP out to output pin.
See General 1nformation section for packaging.
3-28
3:
ELECTRICAL CHARACTERISTICS
....oo
........
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
o
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
-
~~2
7
only one input and one output. The other
3
inputs and outpu ts are tested in the same
manner.
o
o
4
9~1213
10
11
14
::J
!:!.
::J
L SUFFIX
c:
CERAMIC PACKAGE
CASE 620
CD
.e:
TEST VOLTAGE VALUES
(Volts)
@Test
Temperature
W
~
CO
I
I
Characteristic
I Symbol
Power Supply Drain Current
I
Input Current
L
LogiC "1"
Ou tpu t Voltage
LogiC "0"
Output Voltage
Pin
Under
Te..
Min
Min
linL
5,6,7
Logic ·'1"
Threshold Voltage
VOHA
LogiC "0"
Threshold Voltage
VOLA
Max
Min
Rise Time
120 to 80%1
Fall Time
1201080%1
-0.890
-1.890
-1.205
VI LA max
-1.500
+2SOC
-0.810
-1.850
-1.105
-1.475
I
+85 0 C
-0.700
-1.825
-1.035
-1.440
I
Unit
VIH max
VILmin
VIHAmin
Vdc
Vdc
Vdc
1.15.16
-0890
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
Vdc
Vdc
Vdc
1.15.16
1,15.16
1,15.16
Vdc
Vdc
Vdc
1.15.16
Vdc
Vdc
Vdc
1.15.16
1.15.16
1,15.16
-0.810
-0.810
-0.810
2
3
4
-1.890
-1.890
-1890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.8S0
-1.650
-1.6S0
-1.650
'2+
'3+
'4+
'2_
'3_
'4_
3
•
4
-0.910
-0.910
-0.910
-0980
-0.980
-0.980
-1630
-1.630
-1.630
-1.595
-1.595
-1.595
1
3.5
1.5
1
1
1
1 11 1
10
-IndiVidually test each Input uSing the pm connections shown.
1.1
2.2
1.15.16
1,15,16
-0.960
-0.960
-0.960
2.4
8
1.15.16
-0.890
-0.890
1 .•
(Veel
Gnd
IJAdc
4
3.5
VEE
-0.700
-0.700
-0.700
-0.890
-0.890
1.4
VILA me)!
/JAdc
1,15,16
1,15,16
1,15,16
1,15,16
Pulse In
t5+2+
t5_2_
t5+3+
t5_3_
t5+4+
t5_4_
-5.2
-5.2
mAdc
0.5
-1.655
-1.655
-1.655
-5.2
38
-0.890
-1.080
-1.080
-1.080
VEE
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Max
Switching Times
(50-ohm load)
Propagation Delay
-JOoe
425
-1.060
-1.060
-1.060
VOH
VOL
TV.
30
5,6,7
VIHAmin
+8SoC
+250 C
Max
IE
linH
VILmin
MC10110L Test limits
_lODe
I
VIH max
1
1.2
3.8
Pul.Out
-3,2 V
+2_0 V
8
1,15,16
3:
ELECTRICAL CHARACTERISTICS
o
Each MECL 10,000 series circuit has been
o
~
~
designed to meet the de specifications
~
shown in the test table, aher thennal equilibrium has been established. The circuit is
in a test socket or mounted on 8 printed
circuit bo_d and transverse air flow greater
then 500 line. fpm is maintained. Outputs
o
-
~~2
are terminated through. 51k>hm resistor to
-2.0 volts. Test procedures are shown for
7
only one input and one output. The other
3
4
inputs and outputs are tested in the same
manner.
9~12
10
11
8
13
::J
....
P SUFFIX
3'
PLASTIC PACKAGE
CASE 648
a
TEST VOLTAGE VALUES
14
(Volts)
In...
Temperature
-lOoe
+26OC
+85oC
Pin
'rl
(,J
0
I
I
I
CharKteristic
Power Supplv Drain Current
I nput Current
Logic "'"
Output Voltage
Logic "0"
Output Vol1age
logic "1"
Threshold Voltage
Logic "0"
Threshold Voltage
I
I
~
u_,
Symbol
T ...
Mel0110P Tnt Limits
+25"<:
_lOGe
Min
Ma.
Min
Ty.
Ma.
Rise Time
1201080%)
Fell Time
(20 .. _1
M..
Unit
IE
8
38
mAde
5,6.7
5,6,7
425
/lAde
~.890
2
3
4
-1.060
-1.060
-1.060
-0.890
-0.960
-0.960
~.890
~.960
4
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
2
3
4
-1.080
-1.080
-1.080
VOL
VOHA
0.5
VOLA
-0.810
-0.810
-0.810
-1.650
-1.650
-1.650
-0.890
-0.890
-0.890
-1.825
-1.825
-1.825
-0.980
~.910
~.980
-0.910
-0.910
~.980
-1.655
-1.655
-1.655
-1.630
-1.630
-1.630
1.4
'2+
'3+
'4+
1.1
'2_
1 1I
'3_
·lndlViduetty tett eKh Inpu1 usn'll the PI" connlC1lon1lhown.
I
VIHAmin
~.890
-1.890
-1.205
-1.500
-0.810
-1.850
-1.105
-1.475
I
I
~.700
-1.825
-1.035
-1.440
I
VIH max
VILmin
VIHAmin
VEE
5.2
-5.2
-5.2
VILA max
VEE
(Veel
Gnd
8
1.15,16
1.15.16
-0.700
-0.700
Vdc
Vdc
Vdc
-1.615
-1.615
-1.615
Vde
Vdc
Vdc
~.700
1,15.16
8
8
8
Vde
Vdc
Vde
-1.595
-1.595
-1.595
2.4
3.5
1 1
2.2
!
1.15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
8
8
8
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
Vdc
Vdc
Vdc
Put. In
t5+2+
t5_2_
t5+3+
15-3t5+4+
t5_4-
....
VILA ma.
VILmin
/lAde
Switching Times
(50-ohm load)
Propagation Delay
+85·C
Min
VIH max
TEST VOLTAGE APPLlEO TO PINS LISTED BELOW,
linH
linL
VOH
~
Put.Ou1
-3.2 V
+2.0 V
2
2
3
3
8
1,15.16
MECL 10,000 series
DUAL 3-INPUT 3-0UTPUT
"NOR"GATE
MC10lll
POSITIVE LOGIC
9
10
11
~
NEGATIVE LOGIC
~
1~
12
13
.
14
12
The Me 10111 is designed to drive up to three
transmission lines simultaneously, The multiple
outputs of this device also allow the wire-"OR"ing of several levels of gating for minimization
of gate and package count.
The ability to control three parallel lines
from a single point makes the Me 10 111 particularly useful in clock distribution applications
where minimum clock skew is·desired. Three
Vee pins are provided and each one should be
used.
13
14
11
Po == 80 mW typ/gate (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
Output Ris. and Fall Time: (All Outputs Loaded)
==2.2 ns typ (20% to 80%)
== 4.0 nl tvp (10% to 90%)
VCCI = I, 15
VCC2 = 16
VEE = 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
VCC 1
= VCC2
+2.0 Vdc
Vout
~.
,,,,t1t""
r--Input
I
I
----,
~-+-_----J
V out
Pulse Generator
Input Pulse
t+ ;. t- = 2.0 ± 0.2 ns
(20 to 80%)
50-ohm termination to ground lo-
cated in each sCOpe etlannel input.
All Input and output cables to the
scope are equal lengths of 50-ohm
coaxial cabl.. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
s.. G,enera'
PROPAGAT)ON DELAY
VEE == -3.2 Vdc
Information section for packaging.
3-31
ELECTRICAL CHARACTERISTICS
3:
Each MECl 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in I test socket or mounted on 8 printed
circuit bo_d and tra"$Verse air flow greater
than 500 linear fpm is maintained. Outputs
.....
Q
.....
.....
.....
(')
~
~:
'"
7~4
are terminated through a 5o.ohm resistor to
9
-2.0 volts. Test procedures are shown for
10
11
~
12
13
14
only one input and one output. The other
inputs and outputs are tested in the same
manner.
lSUFFIX
CERAMIC PACKAGE
CASE 620
n-o
....
::J
:5'
I:
a
TEST VOLTAGE VALUES
(Voltsl
• Test
Temperatar.
Pin
'fJ
W
Charact.",tte
.
'"
Power Supply Dram Current
Inpu1 Current
LogiC "1"
Output Voltage
LogiC "0'
Output Voltage
LogiC "1"
Threshold Voltage
Symbol
Under
T ...
'E
8
IlnH
5,6.7
IlnL
5.6,7
VOH
2
I
VOLA
TV.
M..
-1.060
-1,060
-1.060
-0.890
-0.960
-0.890
-0.890
-0960
-1.675
-1.675
-1.675
-1850
-1.850
-1.850
I -1080
-1.080
-0.810
-0.810
-0.810
-1.650
-1650
-1.650
-0.960
-0.980
-0980
-0980
Rise Time
~20
to amc.I
Fall Time
IZOtoaa..1
VILA m..
VEE
-JOoC
-0.890
-1.890
-1.205
-1.500
-5.2
+25o C
-0.B10
-1.475
-0.700
-1.850
-1.825
-1.105
+8So C
-1.035
-1.440
-5.2
-5.2
Unit
VIH max
IVeel
VIL min
VIHA min
-0.890
~Adc
1.15,16
1,15,16
Vdo
Vdo
Vdo
1,15,16
1,15,16
1,15,16
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
Vdo
Vdo
Vdo
1,15,16
1,15,16
1,15,16
Vdo
Vdo
Vdc
1.15,16
1,15,16
1.15,16
Vdo
Vdo
Vdo
1.15,16
1,15.16
1,15,16
-1.595
-1.595
-1.595
14
'2'
'3'
'4'
'2_
'3_
10
1.1
2.2
1
1
1 1 1 1
'4_
1
-Individuelly test eech input using the pin connections stlown.
1
1
3.5
1
3.5
1,15,16
~Adc
Pul.ln
2.4
GncI
8
-0.700
-0.700
-0.700
-1630
-1630
-1630
14
VEE
-0.890
-0.890
t5+2_
15-2+
t5+3_
16-3+
15+4_
15_4+
3.5
VILA max
mAdc
S....lItchmg Times
(50·ohm load)
Propagation Delay
VIHA min
TEST VOL rAGE APPLIED TO PINS LISTED BELOW:
M..
-0.910
-0.910
-0.910
-1655
-1.655
-1.655
I
VIL min
+85o e
Mon
425
-1.080
LogiC "0"
Threshold Voltage
Min
0.5
-1.890
-1.890
VOHA
Max
38
I -1890
VOL
MCl0111l Test Limits
+25 o e
-lOoe
Min
VIH me.
1.5
3.8
1 1
1.2
3.8
Pul_Out
-3.2 V
+Z.oV
8
1,15,16
3:
n
.o
..-
ELECTRICAL CHARACTERISTICS
_ie.
Ea:h MECL 10,000
circuit has been
designed to moet the dc opecificetion.
shown in the test table, after thenn. equilibrium has been established_ The circuit i.
in I test mcket or mounted on I printed
ciraJit bo.d and trlnwene lir flow greater
th.. 500 linear fpm is maintained. Outputs
ant t .. minlted through a 5O-ohm resistor to
-2_0 volts. Test procedure. are shown for
only one input and one output. The other
inputs and outputs are tasted in the same
manner.
-
~:
:
7~4
9
10
11
~
'2
.-
8
::J
~
3'
c
PSUFFIX
PLASTIC PACKAGE
CASE 648
13
14
!l
TEST VOL TAGE VALUES
IVolts)
@T8'51
VIHm ...
Vilmin
VIHAmln
VILA mu
_lODe
-0.890
-1.890
-1.205
-1.500
+25o C
-0.810
-1.850
-1.105
-1.475
+85 Q C
-0.100
-1.825
-1.035
-1.440
Unit
VIHmax
T .mperature
Pin
~
W
W
CharKtaristic
vmbol
Toot
'E
8
Input Current
IlnH
5,6,1
Iml
5,6,7
LogiC "'"
VOH
2
Power SupplV Drain CurrenT
OutPUt Voltage
Logic "0"
Output Voltage
MCl0111P 111ft Limit.
+2SoC
_lOGe
u ...
Min
I
M..
Min
I Tvp I
MIX
38
425
-1.890
-1.890
-1.890
LogIC "1"
Threshold Volt.
VOHA
-1.080
-1.080
-1.080
Logic "0"
Threshold Voltage
VOLA
-0.890
-0.890
-0.890
-1.675
-1.675
-1675
-0960
-0960
-0960
-0810
-0810
-0.810
-1650
-1650
-1.650
-1850
-1850
-1.850
-0980
-0980
-0980
-0.890
-0.890
-0.890
-1.825
-1825
-1.825
-1.655
-1.655
-1.655
-1630
-1630
-1630
Vil min
VIHAmtn
1.4
2.4
'5-2+
15+3_
15-3+
'5+415-4+
Rise Time
'2.
'3.
12Ota_1
'4.
Fan Time
'2_
'3_
12Ota_1
'4USing
the pin connections shown.
1 1
1.1
2.2
!1
3.5
-52
-5.2
I
-52
tVee'
VEE
Gnd
8
1,15,16
J.lAde:
1,15,16
J.lAde:
1,15,16
-0.700
-0.700
Vdo
Vdo
Vdo
1,15,16
1,15,16
1,15,16
-1.615
-1.615
-1.615
Vdo
Vdo
Vdo
1,15.16
1,15,16
1,15,16
Vdo
Vdo
Vdo
1,15,16
1,15,16
1,15,16
Vdo
Vdo
Vdo
1.15,16
1,15,16
1,15,16
-0700
-1.595
-1.595
-1.595
Pulse In
15+2_
VILArn. .
mAde:
-0.910
-0.910
-0.910
SWitching Times
(5().ohm load'
-Individually test NCh input
Max
OS
-1.060
-1._
-1.060
VOL
ProP8glltlon Delay
I
VEE
TEST VOL TAGE APPLIED TO PINS LISTED BELOW'
+850 C
Mon
I
Pul_Out
-3.2 V
+2.0 V
8
1,15,16
MECL 10,000 series
QUAD EXCLUSIVE
OR GATE
MC10113
Advance InforIDation
POSITIVE LOGIC
E
9
2
6
TRUTH TABLE
A B E OUTPUT
3
L
L
H
H
10--"-~~
14
11
L
H
L
H
4> 4>
L
L
L
L
H
The MC10113 is a quad Exclusive OR gate,
with an enable common to all four gates. All
four outputs may be wire·ORed together to
perform a 4·bit comparison function (A = BI.
The enable is active low. Input pulldown reo
sistors included in the circuit make it un·
necessary to tie down unused inputs. Open
emitter outputs permit direct connection of
outputs to busses.
L
H
H
L
L
$"'">
r -
(~--~~--TI~~
Pulse Generator
I
Coax
- - -,
I
:>'"-Ir-+--------'
Input Pulse
t+
= t-
= 1.5.±. 0.2 ns
V out
(20 to 80%)
50-ohm termination to ground
located in each scope channel
input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TPin to input
<
pin and TP out to output pin.
VEE = -3.2 Vdc
Unused outputs connected to
a 50-ohm resistor to ground.
This is advance information and specifications are subject to change without notice.
See General I nformation section for packaging.
3-34
@
25°C
ELECTRICAL CHARACTERISTICS
"'"
The circuit is in a
6
3
-2.0 volts. Test procedures are shown
only for selected inputs and outputs. Other
10---'--'"
inputs and outputs are tested in a similar
manner.
"~
12
14
CERAMIC PACKAGE
CASE 620
8
::J
~.
::J
c:
CD
+25"C
+85oC
MCl0113l Test Limits
Pin
Power Supply Drain Current
Input Current
w
W
UI
lin L
Logic "1"
Output Voltage
VOH
Logic "0"
Output Voltage
VOL
Logic "1"
Threshold Voltage
VOHA
Logic "0"
Threshold Voltage
VOLA
Switching Times (50
n
Propagation Delav
2
3
14
15
2
3
14
15
2
3
14
15
2
3
14
15
-
-
-
-
-
-1.060
-1.060
-1.060
-t.060
-1.890
-t.890
-1.890
-.1.890
-1.080
-1.080
-1.080
-1:080
-0.890
-0.890
-0.890
-0.890
-1.675
-1.675
-1.675
-1.675
-
-
-
-
-
-
-0.960
-0.960
-0.960
-0.960
-1.850
-1.850
-1.850
-1.850
-0.980
-0.980
-0.980
-0.980
-
12+
2
2
2
2
2
12_
2
t9+2t9-2+
-
-
-
-
-
SlAdc
SlAdc
-
9
-
-
-
,.Adc
-
-0.890
-0.890
-0.890
-0.890
-1.825
-1.825
-1.825
-1.825
-0.910
-0.910
-0.910
-0.910
-0.700
-0.700
-0.700
-0.700
-1.615
-1.615
-1.615
-t.615
Vdc
4
7
11
13
-
Vdc
-
-1.595
-1.595
-1.595
-1.595
Vdc
-
-
-
-
2.0
-
Min
-
-
-
-
-
-
-
(20 to 80%)
. -
-Individuallv test each input applying VIH or V'L to input under test.
Unit
mAdc
,.Adc
l
Vdc
~
l
~
Unit
(20 to 80%)
Fall Time
-1.500
-1.475
-1.440
-
-
-
VILA mix
-1.205
-1.t05
-t.035
42
-
-
VIHAmin
-1.890
-1.850
-1.825
265
220
545
0.5
-0.810
-0.810
-0.810
-0.810
-1.650
-1.650
-1.650
-1.650
-
-
-
VILmin
Ma.
-
-1.630
-1.630
-1.630
-1.630
TVp Ma.
3.0
3.0
3.4
3.4
2.0
-
-1.655
-1.655
-1.655
-1.655
Min
t4+2+
Ma.
Min
VIH IftIIx
-0.890
-0.810
-0.700
VEE
-5.2
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+85oC
+25°C
Ma.
-
Min
Load)
14-2_
Rise Time
.
_lODe
.eo
TEST VOLTAGE VALUES
(Volts)
@Tost
Tlmp ••tur.
_30G e
1"5
13
Unci.
Symbol
Tort
8
IE
lin H 4,7,10,13
5,6,11,12
9
o
LSUFFIX
4
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
Characteristic
...
......w
o
9
designedta meet the de specifications shown
in the test table. after thermal equilibrium
has been established.
3:
E
Each MECL 10.000 series circuit has been
ns
I
--
VIH
mIIX
..
-
-
VILmin
.
-
-
4
7
11
13
-
-
-
+1.11 V
VIHAmln
VILAma.
-
-
-
-
-
-
4
6
10
12
-
-
-
5
7
11
13
-
VEE
8
8
8
8
8
8
(VCC)
GncI
t,16
1,16
1,16
1.16
1.16
1,16
8
1.16
! l
l l
l l
l l
8
t,16
8
l.t6
Pulse In
Pul_Out
-3.2 V
+2.0 V
4
4
9
9
4
2
8
1.16
-
-
-
-
4
4
4
I II
MECL 10,000 series
TRIPLE LINE RECEIVER
MC10114
The MC10114 is a triple line receiver designed for
use in sensing differential signals ovef long lines. An
active current source and translated emitter follower
inputs provide the line receiver with a common mode
noise rejection limit of one volt in either the positive
or the negative direction. This allows a large amount
of common mode noise immunity for extra long lines.
POSITIVE LOGIC
Another feature of the MC10114 is that the OR
outputs (pins 3,7, 15) go to a logic low level whenever
the inputs are left floating. The outputs are each cap.
able of driving 50 ohm transmission lines.
NEGATIVE LOGIC
4~2
Thisdevice is useful in high speed central processors,
minicomputers, peripheral controllers, digital communication systems, testing and instrumentation systems.
The MC10114 can also be used for MOS to MECL
interfacing and it is ideal as a sense amplifier for MOS
RAM's.
A VBB reference is provided which is useful in
making the MC10114 a Schmitt trigger, allowing singleended driving of the inputs, or other applications where
a stable reference voltage is necessary.
4~2
5~3
5~3
9~6
9~6
'0~7
'0~7
'2~'4
'2~'4
'3~'5
'3~'5
L-"
Vee
L-"
Vee
vee1 ""
Pin 1
VCC2 = Pin 16
VEE Pin 8
tpd = 2.4 ns typ (Single Ended Input)
tpd = 2.0 ns typ (Differential Input)
Po = 145 mW typ/pkg
=
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
VCC1 ::: VCC2
V out
+2.0 Vdc
Coax
Input
V out
PROPAGATION DELAY
""ill'' '
r-- ----,
I
Pu lse Generator
V out
Input pulse
Unused outputs
connected to a
50-ohm resistor
to ground.
t+ '" t - '" 2.0 ±. 0.2 ns
(20 to eO%)
I
I
I
L
50-ohm termination to ground 10'
.cated in each scope channel input.
All ;nput and output cables to the
scope ere equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
I O" "F
IlOne .Input from
-11-.-J
each gate must
be tied to Vee (Pin 11) during testing .
::to'IlF
-32 Vdc
See General I nformation section for packaging.
3-36
~
ELECTRICAL CHARACTERISTICS
......
...
Each MECL 10,000 series has been de-
o
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
~
4~2
nO
5~3
~.
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
:::J
:::J
9~6
c:
<»
10~7
in the same manner.
12~14
'3~'5
~"
VBB
.. T",
Temperatur.
w
W
......
Iu_
Pon
C.....act.,istic
Symbol
Test
Vil min
VIHA min
+zsOC
Min
Typ'
28
"
'inH
ICeD
+85OC
Me. I Min 1 Mall
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Voftsl
VILA
rna.
VIHH-I VllH-1 VtHl·\ VILL
V ••
-I
VEE
-30ot:
-O.B90
-1.890
-1.205
-1.500
F,~
+0.110
-0.890
-1.890
-2.890
.25OC
-0.B10
-1.850
-1.105
-1.475
Pm
+0190
-0.850
-1810
-2850
-5.2
-5.2
+8SOC
-0.700
-1.825
-1.035
-1.440
11
+0.300
-0.825
-1.700
-2.825
-5.2
MC1D114l T . . Limits
-30"<:
Min
M..
Power SupplV Drain Current
Input Current
VIH max
-
a.
TEST VOL TAGE APPLIED TO PINS BELOW:
Unit
I V'H rna.
V,L min
I V,HA min I V,LA mlJl. I
VBB
I V,HH·' VllH·' V,Hl· I VILl· I
35
mAd<
4,9.12
I
15,10,131
4'
.AoX
9,12
I
15,10,13
1.0
9,12
5,10,13
1
-
I
VEE
-
{Vee l
Gnd
1,16
1,16
8.4
1,16
I logiC "1" Output Volt.
VOH
-1.060
-1.060
-0.890
-0.890
-0.960
-0960
=~ :~~ I=~::: I =~:~:
9.12
4
5,10,13
5,10,13
1,16
I logiC "0' Output Voltage
VOL
-1.890
-1,890
-1.675
-1.675
-1.850
-1.850
=~::~~ I=~.:~~ I =~::~~
4
9,12
5,10,13
5.10,13
1,16
1,16
5.10,13
5.10,13
1,16
5.10,13
5,10,13
1,16
1,16
5,10,13
1,16
IlogiC ·'1"
Threshold Voltege
VOHA
LogiC ·'0" Threlhold Volt8lle
VOLA
-1.CIIO
-1.080
-0.980
-0.980
Vd,
VOX
-0.910
-0.910
-1.655
-1.655
9.12
9,12
1,16
-
-1.595
-1.595
Reference Voltage
Vea
-1.420
-1.280
-1350
-1.230
-1.295
-1.150
Vd,
Common Mode Rejection Tnt
VOH
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vd,
VOX
1.16
VOL
-1.890
-1.890
-1.675
-1.675
-1.850
-1.8SG
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vd,
VOX
1,16
1,16
Min
, 0
M..
Min
Tvp
M ••
'.0
2.4
40
Min
0 .•
M..
44
•
+ +
I.'
Swnchi", Ti_ (SO-ohm lOMt)
Prop...-Ilon oelav··
AI. Time (20% 1080%)
FaU Time (20% 10 80%)
14+2+
t4-2_
14+3t4_3+
'2.
'3·
'2_
'3_
I
11
1.-+
~
38
+ +
21
~
·V,HH = Input logiC "1" level shifted poSitive one volt for common mode rejection tests.
V, LH '" I nput logiC ..a" level shifted positive one volt for common mode rejection tests.
Y,HL '" Input logiC "I" level shifted negative one volt for common mode rejection tests.
Y,LL a Input logiC "O"level shifted negative one volt for common mode rejection tests.
·-Delay IS 2.0 ns With differentlellnput.
-1.630
-1.630
1,16
-
•
I.,+
+
+
3.'
43
Vd<
Vd,
+
9.12
1,16
Pul.'n
"
• j
3.7
9,12
4
j
-3.~V 1+2.0V
Pul.Oul
5,10,13
j
I 'J
ELECTRICAL CHARACTERISTICS
3:
n
....o
....
Each MECL 10.000 .ries has been designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and tranlV8rse air flow greater than
500 linear fpm is maintained. Outputs
t.min.ted· through 8 SD-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
....
~
.r.
n-O
5~3
..
9~6
c
4~2
:J
:j'
-
10~7
12~14
'3~'5
L-"
VBe
.T",
T . . . .atun
......""""
-30"1:
W
W
CO
'No
u_
C_ _ _ istic
T_
Power Supply Orein Current
Input Current
VOL
VOHA
logic "0" Threshold Voluee
VOLA
Common Mode Rltjection Tes.
V••
VOH
VOL
Swhchina T ..... (IO-oh... Loedl
P,opeption Oeley··
28
-1.060
Logic "'" ThreshOld Voigge
R.f8f"enCeVoltege
+25OC
8
Loaic "'" Output Vol• •
Logic "0" Output Volt.
MCl0114P Test Limits
-3QOc
MinlMulMifllTyplMa
'4+2.
....2'4+3-
I
J.
-1.060 -0.890
-1.890 -1.675
-0....
-0....
-1.850
-1.890
-1.080
-1.675
-
-0.980
-1.080
2
3·
11
-1.420
-1.060
-1.060
-1.890
-1.890
Min
~.890
-1.655
-'.655
-1.280
-0.890
-0.890
-1.675
-1.675
M,.
-1.850
-'.630
-1.630
-1.230
-0.810
-0.810
-1.650
-1.650
-1.350
-0.960
-0....
-1.850
-1.850
~
1.0
t
Ri. Time (2mC, to 8010'
'2.
'.5
11ft.
'3.
'2_
'3-
+
Typ
M..
2.4
4.0
+
2.'
~
·VIHH .. Input logic "l"level shifted po.iti.". one volt for common mod. rejechon tests.
VILH - Input logic "0" tlNel.hifted positiveonevolt tor common mode reiec1ion t ......
VIH.L '" Input logic "'''level.hitted ne.... iwone voh for common mode reiectfon tests.
'Vlll • Input lolic ..0'·. ...,.1 .r.iftad n ...trw OM 11011 for common mod. rejection test •.
--De&ay i. 2.0
with differ .... till input.
n.
36
45
1.0
-0.810
-0.810
-1.650
-1.650
-0.980
....3.
FilII Time (ZOK t.
I
•
3.5
+
.IS""M,.
Min
-0.890 -0.100
-0.890 -0.700
-1.825 -1.615
-1.825 -1.615
-0.910
-0.910
-1.595
-1.595
-1.295 -1.150
-0.890 -0.700
-0.890 -0.700
-1.825 -1.615
-1.825 -1.615
Min
M..
Unit
mAdo
"A""
"Ado
Vdo
Vde
Vde
Vde
Vde
Vde
Vde
Vde
Vde
Vde
Vde
Vde
Vde
CD
Co
PSUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
IV_
VIH", ..
Vllmin
VIHAmin
VILA max
V••
VIHH-I VILH-J VIHL -I VILL
-<>.890
-0.810
-0.700
-1.890
-1.850
-1.825
-1.205
-1.105
-1.035
-1.500
-1.475
-1.440
F,om
+0.110
+0.190
... 0.300
VIH",...
VIL min
VIHAmin
Pin
>1
-0.890
-0.850
-0.825
-1
VeE
-1.890
-1.810
- t. 700
-2.890
-2.850
-2.825
-5.2
-5.2
-5.2
VIHL-
VILL-
VEE
TEST VOLTAGE APPLIED TO PINS BELOW:
•
VILA max
4,9.12
9.12
9.12
9,12
9,12
9,12
4
4
9,12
9.12
V. .
5.10,13
5,10,13
5.10,13
5,10,13
5:10.13
5,10,13
5,10.13
5,10,13
5,10,13
5,10.13
5,10.13
5,10,13
4
9,12
9,12
9.12
Pul.ln
no
4
j
j
Pul_Out
5,10,13
j
V'HH-
VILH-
•
.,'
8
8
-3.2 V
8
lYeel
a ...
1.16
1.16
1,16
1.16
1,16
1,16
1.16
1.16
1,16
1.16
1,16
1,16
1.16
1,16
1,16
1.16
+2.0 V
1.16
j j
J
'--___
QUAD LINE RECEIVER
"'\
MECL 10,000 series
'--...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......J
MC10115
POSITIVE LOGIC
The MC10115 is a quad differential amplifier
designed for use in sensing differential signals
over long lines. The base bias supply (Va a) is
made available at pin 9 to make the device useful
as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC 10115
with excellent common mode noise rejection.
If any amplifier in a package is not used, one
input of that amplifier must be connected to
Vaa (pin 9) to prevent upsetting the current
source bias network.
NEGATIVE LOGIC
:~2
:~3
10~ 14
10~
13~ 16
L-g
12
13~ 16
11~14
11
12
VBB
L-g
tpd ... 2.0 n. typ
Po - 110 mW typ/pkg (No Load)
VBB
VCC1 - Pin 1
VCC2-Pln 16
VEE'" PinS
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS.:zsOc
VCC, - VCC2
,.,,± I±""
+2.0 Vdc
Input
V out
Coax
PROPAGATION DELAY
r----....,
I
l"putPul..
t+ - t- - 2.0±. 0.2 nl
Vout
(20 to 80%)
5O-ohm terminetion to ground 10'
cet. . in .ach tcope channel input.
All Input and output cable. to the
scope ar. equal I.ngths of 50-ohm
co.JCI.1 cabl.. WI,. length should
be < 1/4 Inch from TPln to Input
pin and TP out to output pin.
One Input from .ch gete must be t'-t to
(Pin 9) during tmlng.
Vas
unu.-:l outputl connected to • 50-0hm ,.Iaor
to ground.
VEE - -3.2 Vde
s_ Oen._1 I "formation _etlan for .peckaglng.
3-39
s:
o
~
o
~
~
(11
ELECTRICAL CHARACTERISTICS
nO
Each MECL 10,000 series has been designed to rnfit the de specifications shown
in the test table, .fter thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
::J
~,
::J
c:
(1)
a.
:~2
:~3
,O~
in the same manner.
11
-
,.
13~'5
L-g
Vea
12
lilT..,
Temper.ture
W
~
-lODe
0
+25"c
+85o C
Ch.rec:'eri.Uc
Power Supply Drain Current
I nput Current
Svmbol
Pin
Under
T..,
IE
8
+25"c
-lODe
M ..
M ..
lin H
IceD
Logic "'" Output VOltage
Logic "0" Output Voltage
Logic "'" Threshold Valt&ge
Logic "0" Threshold VOltage
Reference Voltage
Switching Times (50 n Load)
Propagation Delav
Rise Time (20% to 80%)
Fall Time (20% to 80%)
VOH
VOL
VOHA
-1.060
-1.890
VIL min
VIHA min
VILA me.
VBB
-0.890
-{J.810
-1.890
-1.205
-1.500
-1.850
-1.105
-1.475
From
Pin
26
mAde
95
-0.890
-0.700
-1.825
-0.910
1.615
/JAde
/JAde
Vde
Vde
Vde
1.295
-1.150
1.0
-0.810
-1.675
-1.850
-1.650
-{J.!lB0
1.280
-1.595
-1.630
-1.655
1.420
Unit
-{J.960
-1.350
t4_2+
t4+2_
1.0
1.0
'2+
'2_
3.1
3.1
3.6
1.0
1.0
1.1
1.1
1.1
3.6
1.1
-1.230
1.0
1.0
3.3
3.3
3.3
1.1
3.7
3.3
1.1
3.7
2.9
2.9
-1.035
-1.440
9
VEE
-6.2
~
~
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
M ••
Min
-1.825
-0.700
+ISOC
M ••
-0.890
-1.080
VOLA
V88
TEST VOLTAGE VALUES
VIHmax
MC10115L Test Limits
Min
L SUFFIX
CERAMIC PACKAGE
CASE 620
VIHmo
VILmin
~
VBB
VEE
4,7,10,13
5,6.11,12
8
7,10,13
5,6,11,12
7,'0,13
V.LAmb
(Vee)
Gnd
1,16
1,16
5,6,",12
5,6.11,12
8,4
4
7,10,13
5,6,11,12
8
1,16
7,10,13
5,6,11,12
8
1,16
7,10,13
5,6,11,12
8
1,16
-32 V
8
+2.0 V
1,16
7,10,13
Vde
Vde
VIHA min
8
Pul.Out
4
2
5,6,11.12
~
~
~
1,16
1,16
5,6,11,12
Pul_ln
1,16
!
~
~
o.....
o....
....
(J1
ELECTRICAL CHARACTERISTICS
8:J
Each MECL 10,000 series has been de·
...
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in 8
test socket or mOU'lted on a printed circuit
::J
c:
Cl)
a.
4=::::t>--2
7=::::t>--3
10 =::::t>--14
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
5
terminated through a 5(}'ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
-
6
11
13~15
12
L-9
v ••
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
~Test
Temperature
W
-lODe
~
Ch.rKteristic:
Power Supply Drain Current
I nput Current
Logic "1" Output Voltage
Logic "0" Output VOltage
Logic "'" Threshold Voltage
Logic "0" Threshold Voltage
Reference VOltage
Rise Time (20% to 80%1
Fall Tim. (20% to 80%1
VILmin
VIHA min
VILA max
Vaa
VEE
-0.890
-1.890
-1.205
-1.500
From
Pin
9
~
+25"c
-0.810
-1.850
-1.105
-1.475
+85°C
-0.700
-1.825
-1.035
-1.440
MCl01 15P Tnt Limhs
Symbol
Pin
Und.r
Test
IE
8
26
mAde
4,7,10,13
5,6,11,12
'in H
IcaO
4
4
95
IlAdc
7,10,13
1.0
}JAde
7,10,13
5,6,11,12
5,6,11,12
-lODe
Min
·-1.060
VOH
-1.890
VOL
VOLA
2
V88
9
Min
Min
Ma.
Unit
VIL min
V'Hmo
~.960
-0.810
-0.890
-0.700
Vdc
-1.675
-1.850
-1.650
-1.825
-0.910
-1.615
Vde
Vde
4
7,10.13
7,10,13
-1.595
Vde
7,10,13
-1.150
Vde
~.9B0
-1.630
-1.655
'.420
M ..
-0.890
-1.080
VOHA
+8SOC
+25"c
Ma.
1.280
-1.350
-1.230
1.295
t4_2+
t4+2-
1.0
1.0
2.9
2.9
'2+
'2_
1.1
3.3
1.1
3.3
~
-5.2
TEST VOLTAGE APPLIEO TO PINS LISTEO BELOW,
Switching Times (50 1l Load)
Propagation Delav
VIH max
~.
7,10.13
VIHA min
VILA max
Vaa
5,6.11,12
5,6,11,12
4
VEE
(Vee)
Gnd
1,16
1,16
8,4
8
1.16
1.16
1,16
5,6,11,12
1,16
5,6.'1.12
5,6.11.12
1,16
Pul.ln
Pul.Out
4
2
5,6,11,12
~
~
~
1,16
-3.2 V
+2,0 V
1,16
~ ~
MECL 10,000 series
TRIPLE LINE RECEIVER
MC10116
POSITIVE LOGIC
The MC10116 is a triple differenlial amplifier
designed for use in sensing differential signals over long
lines. The base bias supply (Vaa) is made ..ail_
at pin 11 to make the device u.ful as 8 Schmitt
trigger, or in other applications INhere a stable reference
voltage is necessery.
Active current sources provide the MC101 16 with
excellent common mode noi. rejection. If any amptifier in 8 package is not used, one input of that amplifter
must be connected to Ves (pin 111 to prevent upsetting
the current source bias network.
Complementary outputs are provided to allow driv·
ing twisted pair lines, to enable cascad ing of several
NEGATIVE LOGIC
:~:
:=:tt=~
9~6
9~6
10~7
10~7
12~14
12~14
13~16
13~16
L--ll
L--ll
Vaa
amplifiers in a chain, or simplv to provide complement
outputs of the input logic function.
Vaa
fpd - 2.0 ns typ
Po - 86 mW typ/pkg (No Load)
VCCI - Pin 1
VCC2 - Pin 16
VEE - Pin 8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25°C
VCCI - VCC2
+2.0 Vdc
Coax
V out
V out
PROPAGATION DELAY
25"F~0'I"F
Input
r - -......' - - - - - + 1 . 1 1
r£l~~
+0.31 V
V out
t+
t-
Input pulse
t+,.. t-- 2.0t. 0.2 ns
(20 to 80%)
50~hm termination to ground 10'
c.ted in each lCOpe channel input.
All Input and output cab'.. to the
IeOp. are equal langthl of 50-ohm
coaxial cabl._ WI,. length ahould
be < 1/4 Inch from TPln to Input
pin and TP out to output pin.
V
Unused outputl connected to
• 50-ohm res'ltor to ground.
One Input from each gete mult
be tied to Vee (Pin 11) during testing.
Sea Ganerallnformatlon ..etlon for packaglno.
3-42
ELECTRICAL CHARACTERISTICS
3':
...
......
C")
Each MECL 10,000 series has been designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
I:)
0)
c;O
:l
:::!.
:l
c:
only one gate. The other gates are tested
in the same manner.
~
-
4~2
5~3
9~6
'O~7
'2~14
13~'5
L-"
V
L SUFFIX
CERAMIC PACKAGE
CASE 620
""
TEST VOLTAGE VALUES
(Volts)
filTost
Temperature
w
.;:.
W
-0.890
VILmin
-1.890
VIHAmin
-1.205
VILA max
-3o"c
+25o C
-0.810
-1.850
+8So C
-0.700
-1.105
-1.035
-1.475
-1.440
VIHm ••
MC1Q116L T_ Limits
Pi"
u_,
Characteristic
Svmbol
T_
Power Supply Drain Current
'E
linH
8
4
4
Input Current
'eao
-3o"c
Min
-
High Output Vortage
VOH
2
3
-1.060
-1.060
low Output VOllage
VOL
2
3
-1.890
-1.890
VOHA
2
3
High Threshold Voltage
low Threshold Voltage
Reference V04tege
+2SoC
M ..
-
Min
-
Rise Time
(20% to 80'"
Fall Time
(20%1080%'
17
21
-0.890
-0.890
-1.675
-1.675
-0.960
-0.960
-LOBO
-LOBO
-
-0.980
-0.980
-1.850
-1.850
Min
M ••
/JAde
.-
1,16
9,12
5,10,13
5,10,13
8
8,4
1,16
1,16
5.10,13
5.10.13
5,10,13
5,10,13
8
8
1,16
1,16
8
8
1,16
1.16
5.10.13
5.10.13
8
8
5,10.13
5.10.13
8
8
1.16
1.16
1,16
5.10.13
8
1.16
-3.2 V
+2.0 V
8
1.16
Vdc
Vdc
4
9,12
9,12
4
-1.615
-1.615
Vdc
Vdc
9,12
4
4
9,12
-
-
-0.910
-0.910
-
Vdc
Vdc
-
9,12
9.12
-
4
-1.630
-1.630
-
-1.595
-1.595
Vdc
Vdc
-
9,12
9.12
-1.230
-1.295
-1.150
Vdc
-
-
-
-1.655
-1.655
-
-1.280
-1.350
Min
Mu
Min
Typ
M ••
Min
M ••
2
2
3
3
1.0
3.1
1.0
2.0
2.9
1.1
3.3
2
3
1.1
3.6
1.1
~
~
~
~
-
t ~
j t ~ ~
3.3
1.1
3.7
n,
j
VILA max
9,12
-0.700
-0.700
-
2
3
IVCCI
God
8
-1.825
-1.825
-1.420
t
4
VEE
-0.890
-0.890
2
3
~
~
Vas
-1.650
-1.650
11
~
11
VEE
~
-5.2
5,10,13
VIHAmin
-0.810
-0.810
Vas
'4+2+
'4-2"'+3'4-3+
12+
13+
12_
13_
Pin
4,9,12
VILmin
-
VOLA
-
VIH max
/JAde
-
-
Unit
mAde
95
1.0
Switching Times (50 n Load)
Propagation Delay
Ma.
Vaa
From
TEST VOLTAGE APPLIED TO PINS BELOW:
+8SoC
TV.
-1.825
-1.500
-
-
-
4
..
4
4
-
-
Pulse In
Put. Out
4
2
2
3
3
j
2
3
2
3
5.10.13
1.16
j j j
s:
(')
ELECTRICAL CHARACTERISTICS
...
...o...
Each MECL 10,000 series has been designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
Q)
8
:J
~,
:J
r:::
~
•
4~2
5~3
9~6
'O~7
'2~'4
'3~'5
L-"
V BB
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOL TAGE VALUES
(Volts)
@Test
to.)
Temperature
~
-30 De
~
-3o"e
Under
Characteristic
Power Supplv Oram Current
Input Current
Symbol
Tes'
'E
8
ImH
4
'CBO
HIgh Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Reference Voltage
VOH
Rise Time
120% to 80%)
Fall Time
'120% to 80%)
2
3
Min
-0890
-0.890
-1.675'
-1.675
VOL
2
3
- 1890
2
3
-1.080
VOLA
2
3
V88
"
VIHA min
-1.890
-1.205
VILA rna.
-1.500
From
p,n
11
+2SoC
-0.810
-'.850
-1.105
-1.415
+8So C
-0.700
-1.825
-1.035
-1.440
-1.890
-1.080
-
-
-1.655
Min
-0.960
-0.960
-1.850
-1.850
-0.980
-0980
--
M ••
17
21
mAde
95
)JAde
1.0
)JAde
-
M ••
9,12
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vd,
9,12
-
-0.910
-0.910
-
9,12
Vd,
-
-1.350
-1.230
-1.295
-1.150
Min
Ty.
M ••
Min
M ••
-
-
1.0
2.0
2.9
-
-
2
-
'2'3_
2
3
-
-
~
~
1.1
I
+
3.3
~
9.12
--
M ••
3
Vd,
Vd,
Vd,
Vd,
-1.280
'2+
'3+
Vdc
-1.595
-1.595
Min
--
•
•-
Vd,
Vd,
-1.420
-
•
-0.700
-0.700
-1655
2
2
3
3
VIH mall:
-0.890
-0.890
-
t4+2+
t4-2_
t4+3_
t4_3+
Unit
-0.810
-0.810
-1.630
-1.630
-
--
-:sT
~
(Vee l
Ty.
Min
VEE
-52
TEST VOLTAGE APPLIED TO PINS BELOW'
+8SoC
+2SoC
M ..
-1.060
-1.060
VOHA
SWitching Times 150 it load)
Propagat Ion Delav
•
VILmin
-0.890
MCl0116P Test limits
Pin
VBB
VIH max
-
--
-
n,
I
-
-
VILmin
4,9,12
VIHA min
VILA max
VBB
5,W,13
VEE
8
Gnd
1,16
9,12
5,10,13
8
1,16
9,12
5,10,13
8,'
1.16
5,10,13
5.10,13
8
8
1.16
1,16
-
5,10.13
5.10,13
8
8
1.16
1.16
•
5,10,13
5,10,13
8
8
1,16
1,16
4
5.10,13
5.10,13
8
8
1.16
1.16
-
5.10.13
9.12
•
•
9,12
9,12
-
-
-
-
-•
9, '2
-
-
-
--
-
-
4
-
-
-
Pulse In
Pulse Out
4
2
2
3
3
5.10.13
8
1,16
-3.2 V
+2.0 V
8
1.16
I II I
2
3
2
3
MECL 10,000 series
DUAL 2-WIDE 2-3-INPUT
"OR-AND/OR-AND-INVERT"
GATE
MC10117
The MelOl17 is a general purpose logic element designed for use in data control, such as
digital multiplexing or data distribution_ Pin 9
is common to both gates_
Po = 100 mW typ/pkg (No Load)
tpd
=
2.3 ns typ
Output Rise and Fall Times:
3.5 ns (10% to 90%)
= 2.2 ns (20% to 80%)
=
r------
POSITIVE LOGIC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NEGATIVE LOGIC _ _ _ _---,
4
4
5
5
3
2
6
9
9
10
10
11
L-_r---~
veel = Pin 1
____ 14
,,~_1~--
~_~--~~
VCC2 = Pin 16
VEe
15
= Pin
8
12
12
13
13
2 = (4.5) + (6.7.9)
3= (4e5) + (6-'-9)
2 = (4 + 5) • (6 + 7 + 9)
3
= (4
___ 14
~-~__~---o15
+ 5) • (6 + 7 +9)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250C
VCCI
= VCC2
''m
+2.0 Vdc
V out
OR-ANDI NVEAT
V out
OR-AND
Coax
PROPAGATION DELAY
""'c...
r - - - - - --.-------,
I
I
~----+1.11
V
---~-+O.31
V
V out OR·AND
Input Pulse
t+
t+ = t- = 2.0 ±. 0.2 ns
(20 to 80%)
tV out OR·AND·INVERT
L _ _ _ _ _ _ _ _ _ _ ----l
~
5O..ohm termin.tton to Ground 10CIIted
in •• ch scop. chenne' input.
I
All input and output cables to the
scope are equal lengths of 50-ohm
coaKial cable. Wire length should
:7n
~n~~~:~~ :~o:::Jt:~it"p~~.input
s.. Ganaral
Unused outputs connected to
a 50-ohm resistor to ground
0.1 ,.,F
_
VEE = -3.2 Vdc
I nformatlon section for packSging.
3-45
s:
ELECTRICAL CHARACTERISTICS
n
....o
....
Each MECL 10,QCK) series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than SOO linear fpm is maintained. Outputs
....
4
8""""
5
~3
are terminated through a 50-ohm resistor to
::J
~.
::J
6~
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
C
~
-
10
11
~14
15
12
13~
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(VoI..1
I
@IT.st
Temperature
t.)
,i.
0>
Characteristic
Power Supply Drain Current
Svm~
Pin
Under
Test
-lODe
Ma.
Min
-
-
-
IE
8
lin H
4
9
lin l
4
9
-
-
0.5
0.5
Logic "1" Output Voltage
VOH
2
3
-1.050
-1.050
-0.890
-0.890
-0.960
-0.960
Logic "0" Output Voltage
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
VOHA
2
3
-1.080
-1.080
-
-0.980
-0.980
2
3
-
-1.655
-1.655
-
Input Current
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
Switching Times (50
Propagation Delay
n
VOLA
Fall Time
(20 '0 110%1
VIHAmin
-1.890
-1.205
-1.500
-5.2
-1.850
-1.105
-1.475
-5.2
+85"C
-0.700
-1.825
-1.035
-1.440
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Ma.
Unit
VIH max
VIL min
VIHAmin
20
26
./JAde
./JAde
4
9
-
-
-
-
265
350
-
mAde
-
./JAde
.lJ Ade
-
4
9
-0.810
-0.810
-{).890
-{I.890
-0.700
-0.700
Vd,
Vd,
4,9
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vd,
Vd,
-
-
-0.910
-0.910
-
Vd,
Vd,
-
-
-1.630
-1.630
-
-1.595
-1.595
Vdc
Vd,
-
-
4.9
9
9
-
+1.11 V
t4+2+
t4-2_
'2+
'3+
'2_
'3_
2
2
3
3
1.4
2
3
0.9
2
3
~
~
3.9
~
4.1
+
'4
2.3
3.4
1.4
3.8
+
2.2
+
4.0
+
1.1
+
4.6
+
+
1.1
+
+ +
VEE
-0.810
Min
-
INX
-0.890
Ma.
TV.
VILA
_30 G e
Load)
t4+3t4-3+
Rise Time
(20'080%1
VILmin
+25o C
MCl0111L Test limits
+25"C
+850 C
Min
VIHma
+
ns
9
j
I
-
-
-
4
-
VILA max
VEE
IVeel
Gnd
8
1,16
-
8
8
-
8
8
1,16
1.16
1,16
1.16
8
8
1,16
1,16
8
8
1,16
1,16
8
8
1.16
1,16
-
-
-
4
4
-
8
8
Pul.ln
Pul_Out
-3.2 V
1,16
1.16
+2.0 V
4
2
2
3
3
2
3
2
3
8
1,16
j
4
Ij
3:
ELECTRICAL CHARACTERISTICS
(")
....
o
Each MECL 10,000 series circuit has been
........
......
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
8
4
5~
than 500 linear fpm is maintained. Outputs
are terminated through 8 50-ohm resistor to
::J
:.
::J
~3
c
2
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
6~
-
9
10
11
~14
'---"
12~
13
15
(Volts)
w
+85"C
Pin
Ch.KC.ristic
Power Supply Drain Current
Input Current
Symbol
IE
'in H
lin L
Logic "1" Output Voltage
VOH
Logic "0" Output Voltage
VOL
Tost
8
4
9
Mel0117P Te. Limfts
+25"C
+85"e
-30"e
Undlr
VILA max
VEE
-1.890
-1.205
-1.850
-1.105
-1.035
-1.500
-1.475
-1.440
-5.2
-5.2
-1.825
TEST VOLTAGE APPLIEO TO PINS LISTEO BelOW,
Ma.
Min
M ••
Unit
VIH max
VIL min
VIHAmin
VILA m.x
VEE
-
-
20
-
-
mAde
-
-
8
1Veel
Gnd
1.16
-
-
-
8
8
1.16
1.16
-
-
.Adc
-
-
-
.-
26
265
350
8
8
1.16
1.16
-
-0.810
-0.810
-0.890
-1.650
-1.650
-1.825
-1.825
8
8
8
8
1.16
1.16
-
8
8
1.16
1.16
8
8
-3.2 V
1.16
1.16
+2.0 V
8
1.16
4
9
2
3
2
3
-
-
-1.060
-1.060
-1.890
-1.890
-1.675
-1.675
-0.890
-0.890
0.5
0.5
-0.960
-0.960
-1.850
-1.850
-
2
3
-1.080
-1.080
-
-
-0.980
-0.980
VOLA
2
3
-
-1.655
-1.655
-
2
2
3
3
2
3
-
-
1.4
2.3
3.4
~
~
~
~890
~Adc
-0.700
-0.700
-1.615
-1.615
-
-0.910
-0.910
-
-1.630
-1.630
-
-1.595
-1.595
-
.Adc
.Adc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Switching Times (50 n loadl
4
9
-
-
4
9
4.9
-
4.9
9
.-
9
-
-
-
+1.11 V
~+2+
'4-2-
14+3'4-3+
'2+
'3+
'2_
'3_
2
3
!
-5.2
TVp
VOHA
120'080%1
VIHA min
Min
Logic "0" Threshold Voltage
Fall Time
VIL min
Mu
LogK: "'" Threshold Voltage
Rise Time
120'080%1
VIH max
-0.890
-0.810
-0.700
Min
-
Propagation Delay
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
tiT ...
Temperatur.
-30"C
+25o C
~
.....
~
-
-
-
-
-
1.1
2.2
4.0
~
!
~
-
-
-
-
ns
9
j
I
-
-
-
-
-
4
-
-
4
4
-
4
-
Pul.ln
Pul_Out
4
2
2
3
3
2
3
2
3
j
1.16
1.16
j j
MECL 10,000 series
DUAL 2-WIDE 3-INPUT
"OR-AND" GATE
MC10llS
The MC10118 is a basic logic building block
providing the OR-AND function, useful in data
control and digital multiplexing applications.
Po = 100 mW tvp/pkg (No Load)
tpd
=
2.3 ns tvp
Output Rise and Fall Times:
:::: 3.5 ns (10% to 90%)
= 2.5 ns (20% to 80%1
POSITIVE LOGIC
NEGATIVE LOGIC
3
4
5
2
6
2
6
Vee1 :::: Pin 1
VCC2:::< Pin 16
9
Vee
10
=
Pin
8
9
10
11
11
15
12
15
12
13
13
14
·Collector Dot
14
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@2SoC
VCCI
= VCC2
+2.0 Vdc
V out
CoaM.
PROPAGATION OELAY
Input
Pulse Generator
Input Pul ..
t+ .. t- ~ 2.0 ±. 0.2 ns
(20 to 80%1
5O..,hm to'mlnotlon to ground 10.
c.ted in ••ch &COp. channel input.
V out
L- - -
~-- - ---.J
Unused outputs connected to
a 50-ohm resistor to ground
I-= 0.1 ~F
All input and output coblo. to tho
scop. ar. equal lengths of 50-ohm
coe.iel cabl.. Wire length should
be < 1/4 inch from TPin to input
pin end TP out to output pin.
VeE = -3.2 Vdc
See Genera' I nformation section for packaging.
3-48
s:(")
....
C
....
....
00
ELEC1RICAL CHARACTERISTICS
Each MECL 10,000 series haS been de,
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flQW greater than
8
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
...5'
::J
-2.0 volts. Test procedures are shown for
onlv one gate. The other gates are tested
in the same manner.
11
c:
CD
15
a.
12
-
14
L SUFFIX
CERAMIC PACKAGE
eASE 620
,
TEST VOLTAGE VALUES
(Volts)
ct>
~
@Test
Temperature
_30 o e
Pin
Characteristic
Power Supply Drain Current
I nput Current
Symbol
IE
'In H
8
6
7
9
VtHA min
VILA max
VEE
+2SoC
-0,700
-1.205
-1.105
-1,035
-1.500
-1.475
-1,440
-5,2
-5.2
+8So C
-1.890
-1.850
-1.825
MC10118L Test Limits
+8So C
+25o C
-lOoe
Min
Max
Min
-
-
-
Max
Min
Max
Unit
VIH max
VIL min
20
26
-
-
mAde
-
265
265
370
~Ade
-
6
7
9
-
-
-
Typ
t
2
-1.060 -0.890
-0.960
-
-0.810
-0.890 -0,700
Vdc
-2.000 -1.675
-1.990
-
-1.650
-1.920 -1.615
Vdc
-0.910
Vdc
VOL
2
VOHA
2
Logic "0" Threshold Voltage
VOLA
2
.-
-
0.5
-0.980
1.080
-
-
-
-1.595
-1.630
-1.655
+
/JAde
-
+
-
6
7
9
3,9
-
Rise Time
Fall Time
C20 to 80%)
C20 to 80%1
t6+2+
2
~
t+
t-
1.4
1.4
2.3
2.3
3.4
3.4
1.4
1.4
3.8
3.8
4.1
1.5
2.5
4.0
1.5
4.6
4.1
1.5
2.5
4.0
1,5
4.6
1.4
1.4
3.9
3,9
0.8
0.8
-
-
n,
~
3
•
VILA max
-
-
-
-
-
3
9
+1.11 V
'6_ 2-
VIHA min
--
VEE
1Veel
Gnd
8
1.16
8
1.16
+
+
8
1.16
8
1.16
8
1.16
8
1,16
+
+
3
8
1,16
Pulse In
Pulse Out
-3.2V
+2.0V
6
2
8
1.16
~
~
~
~
Vdc
Switching Times (50 H Load)
Propagation Delay
-5.2
TEST VOLTAGE APPLlEO TO PINS LlSTEO BelOW:
VOH
6
7
9
Logic "'" Threshold Voltage
Logic "0" Output Voltage
Vil min
-0,890
-0.810
-
lin L
Logic "'" Output Voltage
Und ..
Tes.
VIHmax
ELECTRICAL CHARACTERISTICS
3:
Each MECL 10.000 series has be.n de-
n
o
3
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flew greater than
500 linear fpm is maintained. Outputs are
~
4
~
5
~
6
terminated through a 50-ohm resistor to
9
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
10
CO
8:::l
....
s·
11
in the same manner.
c:
15
12
(I)
Co
-
13
14
Col
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
g,
IVolh'
0
ilT ...
VIH max
VILmin
VIHA min
VILA !NIX
VEE
+25°C
-0_890
-0.810
-L205
-1.105
-0.700
-1.500
-1.475
-1.440
-5.2
-5_2
+85o C
-1.890
-L850
-1.825
T emperatur.
-lOoC
MCl0118P Test Limit.
Pin
Characteristic
JSYmbol
Power Supply Drain Current
I
I
Input Current
I
Ie
1m H
lin L
I
I
Unci..
Test
8
6
7
9
6
7
9
Logic "1" Output Voltage
VOH
2
Logic "0" Output Voltage
Logic "1" Threshold Voltage
VOL
VOHA
2
2
Logic "0" Threshold Voltage
VOLA
2
-lOOC
Min
Ma.
-
-
-
-1.060 -0.890
-2.000 -1.675
+25D C
Typ
Ma.
Min
-
20
26
-
-
-
265
265
370
-
0.5
+
-0.960
-1.990
-1.080
-
-0_980
-
-1.655
-
-
Ma.
-
VIH max
VILmin
VIHAmin
VILAIU.
VEE
mAde
-
-
1.16
6
7
9
-
8
/JAde
-
8
1.16
-
-
+
8
1.16
-0.810
-0.890 -0_700
+
+
Vdc
-1.650
-1.920 -L615
Vdc
-
IJAdc
Rise Time f20 to IO%J
fa!1 Time
120 10
10%'
-
--
6
7
9
3.9
-
-
-
-0_910
-
Vdc
9
-1.630
-
-1.595
Vdc
-
16+2+
.+
.-
2
~
-
-
-
1.4
L4
1.5
1.5
2.3
2_3
3_4
3.4
2.5
2_5
4.0
4.0
-
-
-
ns
l
3
•
-
GncI
+
-
-
-
3
-
8
8
-
Pulse In
3
Pul.Out
8
-3.2V
1.16
+2.0 V
6
2
8
1.16
l
l l
+1.11 V
ts- 2-
IVCC'
Unit
Switching Times (50 12 Loadl
Propagation Delay
-5.2
+lI!i"c
Min
-
-L035
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
-
+
8
+
1.16
1.16
1.16
~
MECL 10,000 series
4-WIDE 4-3-3-3 INPUT
"OR-AND" GATE
MC10119
POSITIVE LOGIC
The MC10119 is a 4-Wide 4-3-3-3 Input ORAND gate with one input from two gates common to pin 10_ Input pulldown resistors eliminate the need to tie unused inputs to an external
supply_
NEGATIVE LOGIC
3
3
4----"',r--'
4
5
--~
___
5
6
6
7
7-~'L._
9
9
10
10
11
11
12
12---"'.r--
13
2
Po = 100 mW typ/pkg (No Load)
tpd - 2.3 nl typ
Output Alse and Fell Time:
~ 3_5 n. typ (HI" - 90%)
- 2_5 n. typ (20% - 80%)
13--,,-_
14
14
15-...... . - -
15-""<::.r--
vee1 "" Pin 1
VCC2 = Pin 16
·Colleetor Dot
VEE=Pin8
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 1!l2SoC
+2.0 Vdc
nco..
I~
25I'FRO.'I'F
r--~l~-_-,
Coax
I
Pulse Generator
I
I
I
I
I
Input Pul ..
t+ - t- ., 2.0 ± 0.2 nl
(20 to 80")
PROPAGATION DELAY
I
I
I
I
I
~hm
I
t_ml".tlon to ground 10-
CMed in . .ch .co.,. channel input.
~=:
L ___
AU Input end output cabl •• to the
ICOpe .re equal length I of 50-ohm
co._la' cable. Wlr. length should
be < 1/4 Inch from TPln to input
pin and TP out to output pin.
VEE:-' -3.2 Vdc
See G.nera' Information seetion for p6ekaging_
3-51
V out
s:
C')
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is -in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
~
o
~
~
(C
8
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
....
:J
:J
C
onlv one gate. The other gates are tested
in the same manner.
[
'0
-
"
'2
,.'3
'5
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
Co)
&.
I\)
(Voltsl
@Test
Tempetoature
Pin
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unci.
Test
IE
B
lin H
7
9
10
lin L
logic "1" 0 utput Voltage
7
9
10
VOH
2
VIH max
Vil min
VIHA min
VILA max
VEE
_lOGe
-0.890
-1.890
-1.205
-1.500
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
-5.2
+8SoC
-0.700
-1.825
-1.035
-1.440
-5.2
MC10119L Test Limits
+25oC
-lOoe
Min
-
-
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Max
-
Min
0.5
+
-1.060 -0.890
-0.960
+8SoC
Typ
Max
20
26
-
265
265
370
-0.810
Min
Max
Unit
-
-
/.lAde
+
,uAde
+
-0.890 -0.700
Vdc
VOL
2
-2.000 -1.675
-1.990
-1.650 -1.920 -1.615
Vdc
Logic "1" Threshold Voltage
VOHA
2
-1.080
-0.980
-0.910
Vdc
Logic "0" Threshold Voltage
VOLA
2
t3+2+
'3-2-
2
Logic "0" Output Voltage
Switching Times (50
n
80%.
Fall Time (20 to 8O%J
VILmin
7
9
10
-
-
7
9
10
3,10,15
-
10,15
-1.595
Vdc
3.8
3.8
4.6
4.6
ns
,+
,-
~
1.4
1.4
3.9
3.9
1.4
1.4
2.3
2.3
3.4
3.4
1.4
1.4
10,13
0.8
4.1
4.1
1.5
2.5
4.0
1.5
1.5
2.5
4.0
1.5
0.8
~
~
VEE
(VCCI
Gnd
-
-
8
1,16
-
-
B
1,16
+
B
1,16
VIHA min
VILA max
-
-
3
3
+1.11 V
Load)
Propagation Delay
Rise "Time 120 to
-1.630
-1.655
VIH max
mAde
-
+
B
8
+
+
1.16
1,16
B
1,16
B
1,16
Pulse In
Pulse Out
-3.2V
+2.0 V
3
2
8
1,16
~
~
~
~
ELECTRICAL CHARACTERISTICS
3:
n
Each MECL 10,000 series has been designed to meet the de specifications shown
~
in the test table. after thermal equilibrium
has been established. The circuit is in a
Q
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
cg
~
~
nO
terminated through a 50-ohm resistor to
...::s:;-
-
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
'0
"'2
c:
CIl
Co
P SUFFIX
PLASTIC PACKAGE
CASE 648
.....
"tI~'tinl ~ ~
,.,.
'3
w
TEST VOLTAGE VALUES
~
IVoltsl
lilTost
T emperatur.
Pin
Ch.... ct.'i.ic
Power Supply Drain Current
Input Current
Sy_
IE
lin H
lin L
Logic "1" Output Voltage
Logic "0" Output Voltage
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
Und.
Toot
8
7
9
10
7
9
10
-
-
Min
-
-
-
0.5
-
+
-0.960
+25°C
Typ
20
-
VOL
2
2
-1.060 -0.890
-2.000 -1.675
-1.990
-
VOHA
VOLA
2
2
-LOBO
-
-0.980
-
-1.655
-
-
VOH
Rise Time
t20 to 80".
Fall Time 120 to 80%)
VIHAmin
-1.890
-1.850
-1.825
-1.205
-1.105
-1.035
Unit
VIH max
YILmin
VIHAmi"
VILA.,...
VEE
mAde
-
-
",Adc
7
9
10
7
9
10
3,10,15
-
-
8
8
-
-
2
'3-2.+
~
.-
-
-
-
1.4
1.4
1.5
1.5
2.3
2.3
2.5
2.5
miX
-1.500
-1.475
-1.440
-5.2
-5.2
-5.2
TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
Min
26
265
265
370
-
-
-
-
M..
-
-0.810 -0.890 -0.700
-1.650 -1.920 -1.615
-
-0.910
-
-1.630
-
-1.595
+
",Adc
+
Vdc
Vdc
Vdc
Vdc
10,15
+1.11 V
t3+2+
VILA
+85o C
Mo.
Switching Times (50 n Load)
Propagation Delay
VIL min
-0.890
-0.810
-0.700
MC10119P Test Limits
_30°C
Min
Mo.
VEE
VIHm..
-3O"c
+25°C
+85°C
3,4
3.4
4.0
4.0
-
-
-
ns
10,13
~
~
-
+
8
+
8
8
IVcel
Gnd
1,16
1,16
+
1,16
+
1,16
1,16
1,16
1,16
-
3
Pulse'n
Pul.Out
8
8
-3,2 V
3
2
8
+2,0 V
1,16
~
~
~
l
3
MECL 10,000 series
4-WIDE
"OR-AND/OR-AND-INVE RT"
GATE
MC10121
The MC10121 is a basic logic building block
providing the simultaneous OR-AND/OR-ANDINVERT function, useful in data control and
digital multiplexing applications_
Po = 100 mW typ/pkg (No Load)
tpd ::: 2.3 ns typ
Output Rise and Fall Times:
= 3.5 ns (10% to 90%)
= 2.5
ns (20% to 80%)
NEGATIVE LOGIC
POSITIVE LOGIC
:--~--~-------.
4
5
6 --L---'----,
7--~--~--~__,
7
9
&--'-----------,
9
2
3
10
11
12--'---./----.,.
veel :::
Pin
11
12 ---'_..r-~
1
VCC2 0 Pin 16
VEE-Pln8
13-~--~~~--~
~l-~-~--r--~
14
15--'--------2 ::: (4 ...
~
2
3
10
15 ---"L---'---
... 6) • (7 ... 9 + 10) • (10 + 11 + 12) • (13 + 14 + 15)
3= (4+ 5+6) .(7+ 9'+ 10)e(10+ 11 + 12) .(13+ 14+ 15)
2= (4_ se6) + (7 _9_ 10) + (10. 11.12) + (13.14.15)
3 - (4.5.6) + (7.9.10) + (10.11.12) + (13.14.15)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC
veel =: VCC2
+2.0 Vdc
~,tiJ'"
r----- - - - - -
V out
Coax
Coal(
---.,
I
50
Input Pul ••
PROPAGATION DELAY
50
:z 2.0 ± 0.2 ns
(20 to 80%)
t ... "" t-
+1.11 V
I
Vin
I
5O-ohm termln.tion to ground 10CIIted in ..ch lcope chennel input.
All input and output cables to the
scope are equal lengths of 50-ohm
I
I
----fl_ ::-,,~ -
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
1~
VE E
= -3.2
I
V out OR-AND
_.J
V out OR AND INVERT
Vdc
See General Information section for packaging.
3-54
ELECTRICAL CHARACTERISTICS
_ie.
E.:h MECL 10,000
circuit 11M b8en
delignod to meet tho de spocificotions
shown in the test table, after thermal equilibrium has been established. The circuit is
in 8 test socket or mounted on 8 printed
circuit bo..d and transverse air flow greater
...~
...
...
o
N
i~
th.. 500 linear fpm is maintained. Outputs
are terminated through a 5O-ohm resistor to
-2.0 volts. Test procedures are shown for
onlv one gate_ The other gates are tested
in the same manner.
8
::J
....
7~
2
3
1D
5-
-
9
11
12~
13~
14
15~
c:
It>
c..
LSUFFIX
CERAMIC PACKAGE
CASE 62D
TEST VDL TAGE VALUES
(Volts)
@Test
VIH max
VILmin
VIHAmin
VILA max
VEE
-30D e
-0.890
-1.890
-1.205
-1.500
-5.2
+2S o C
-0.810
-1.850
-1.105
-1.475
-5.2
+8SD C
-0.700
-1.825
-1.035
-1.440
-5.2
Temperature
Co.)
hm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
...
...
...
n
o
i~
N
8
...:;i'
:l
~~
-
2
3
10
11
12~
13~
14
15
c:
CD
Co
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Vellsl
@Test
Temperature
_30 Ge
W
C)
~
MlO,n,,,p -~
-~
~
I
1
VIH max
VILmin
VIHA min
-0.890
-1.890
-1.205
I
-1.500
-0.810
-1.850
.
-1.105
1
- --U./UU
-
--".LO
• "35
I
VILA max
1
VEE
I
-52
-1."75
1
-52
-1.440
I
-5.2
TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
Characteristic
1 Symbol
Power Supph,. Drain Current I
Input Current
Logic "1"
Output Voltage
lin H
I
logic "0"
Output Voltage
logic "1"
Threshold Voltage
Log" "0"
Threshold Voltage
IE
Unit
VIL min
mAd<:
.Ad<:
+
lin L
J..IAdc
VOH
Vdc
Vdc
VOL
VIH max
7
9
10
VILA max
VEE
IVeel
Gnd
8
1,16
8
1,16
+
8
+
Vdc
Vdc
VIHA min
10
4,10,13
4,10,13
+
+
1,16
+
1,16
1,16
1,16
1,16
I
VOHA
I
Vdc
Vdc
10.13
1,16
1,16
VOLA
Vd<:
Vdc
10,13
1,16
1,16
Switching Times
(SO n load)
Propeg8tion Delav
Rise Time
(20'080%)
FO\lT ....
,~ ... ~ it.-,"
iif'E9.j.111~~ r. CHVI4Vhm resistor to -2.0 volts. Test procedures are
shown for only one translator. The other
tl'1lnslatorlar& tested in the same manner.
-
4
6
2
3
10
12
11
15
13
...a
0
...a
N
~
8::J
L SUFFIX
CERAMIC PACKAGE
CASE 620
~.
::J
c::
ct>
C.
14
TEST VOLTAGE/CURRENT VALUES
Volt.
n ...
T.mper ..tur~
~
C)
C
......
Ch.,..::t.,,,hc
Sv_
NegatIVe Power Supply
T...
M,.
·lOoe
pOSllI\le Power SupplV
Moo,
Mi.
Tvo
Drain Current
forward Current
I,
I nput Breakdown Voltage
••
eV ln
Moo,
Min
Moo,
V,
High Output Voltage
VOH
-1060
-1.060
-0.890
-0890
LOW Output Voltage
VOL
-1.890
-1.890
-1.675
-1.675
Hogh Threshold Voltage
VOHA
VOLA
+8SoC
+4.0
><1'0
+1.80
Unit
,>3!) Vde 10 50%J(j)
•
~T'_I20"'0_1
fall TIrM'18O%to2O%1
(j)
I
16+1+
'6-1t7+1+
11_1_
11+3_
17-3+
25
mAde
200
SO
-12.8
-3.2
Jl.Ade
Jl.Ade
mAde
mAde
-1.080
-1.080
-0.960
-0960
-1.850
-1.850
00.40
v.
,240
+2.40
+2.40
I
Vee
'.00
I
VEE
.S>
I " I'i.
+1.0
+5.00
·5.2
10
·10
" 0
'.00
".2
·10
"
IS
10
IS
10
1.'
1.0
6 .•
6.0
6 .•
•.0
-0890
-0890
-0700
-0.700
Vd,
Vd,
-1.650
-1.650
-1.825
-1825
-1.615
-1615
Vd,
Vd,
-0.910
-0910
VllllWlx
VIHA"
0
VILA'
V,
V.
Vee
VEE
3.'
6.0
... 1 1 1
•.0
I"
1.0
'.2
2.'
3.'
'1·
1.0
'.2
2.5
3.'
10
"
10
1.'
1.0
15
6.0
60
..•
..0
'.3
1.1
j
GM
16
..
5,6.1,10,11.16
5,7.10,11
6
16
16
5},IO,11
6
16
16
5},10,11,16
6,16
16
16
6.7
16
16
6.7
6.7
..
16
16
6.7
..
16
I.
Vd,
Vd,
••
••
'in
16
Vd,
Vd,
-1595
-1.595
-1.630
-1630
IS
V,H
Vd,
Vd,
-0810
-0.810
-0980
-0.980
-1655
-1655
3
3
+0.90
I
Vd,
Vd,
·IS
IS
+
><140
5,6.7.10,11
$Wild,,", TirM t50-H lo.-n
PrOPdOJiI'lon Delav
v,
><1.40
+1.10
mAde
55
Clamp Input Voltage
LOW Threshold Vollage
><140
16
ICCL
'R
>--~ =:::t>--=:::t>--=:::t>--~
Each MECL 10,000 se,ies ci,cuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit
is in • test socket or mounted on a printed
circuit board and transverse air flow greater
th., 500 Ii.... fpm i. maintained. Test
procedures •• shown for only one trans'ator. The other translators are tested in
the urn. manner.
4
5
....s:
n
o
N
C1I
C')
o
10
11
12
14
13
15
::J
~.
::J
PSUFFIX
c:
PLASTIC PACKAGE
CASE 648
a
L-l
VSS
TEST VOL TAGE VALUES
(Volu!
. ''''
Temperature
-lOoe
m II
~
C.....ect.ristic
Symbol
N~r"e Power Supply
VIHml.
-0.890
-0.810
Vilmin
-1.890
+8SOC
-0700
-'850
-1825
VIH max
VIL min
MC10125P T_ Limit.
Pin
,_
U.....
W
+25°C
-3O"e
Min
Mo.
TV.
IE
Mo.
40
-1 105
-1475
+0.190 -0.850 -1.810 -2.850
-1035
-1440
'O:JJO -0.825 -17001. 282•
I
v..
I
From
Pm
Vee
•• 0
I
I
".0
VEE
·52
-5.2
+5.0
I
·.2
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+>sOC
Min
I
V.. Am,n VI LA ml" V,HH VILH VIHL VILl
-1205
-1500 +0110 -0.890 -1.890 -2890
Min
+8SOC
Mo.
Unit
VIHAmin VILAmu V:"iH VILH
mAdc
VIHL
VILL
V••
3,1,11.15
Vee
VEE
8
God
I
Output
Condition
16
Dram Current
POSItIve Power Supply
Drain Current
Input Current
leO-l
leCl
linH
Input Leekage Current
ICBO
HI~
VOH
Output Voltage
LOw Output VOltage
2.'
VOL
High Threshold VOltage
mAdc
II.
s.cAdc
1.0
J,lAdc
2.'
2.'
0.'
Vd,
16
3,1,11,15
2,6,10,14
2,6,10,14
.~
2,6,10,14
Vd,
2.'
3,1,11,15
2,6,10,14
Vd,
2.'
16
16
3,1,11,15
2,6,10,14
mAdc
a.•
0.'
2 .•
VOHA
.2
39
6,10,14
3,1,11,15
2,6,8,10,14
16
3,7,11.15
8
16
-20mA
3,7,11,15
16
20mA
3,7,11,15
16
16
-2.0 rnA
20mA
Low Threshold VOltage
VOLA
VOlSl
0.'
0.'
0.'
0.'
0.'
0.5
Vd,
Indelermin... Input
Protecttan Tests
Vd,
2,3,6,7,8,
10,11,14,15
16
20mA
VOlS2
0.'
0.'
100
-1,230
0.5
Vd,
8
20mA
-1.150
mA
Vd,
Vd,
Short·Circuit Current
lOS
Ret.,ence Volt.
VB.
-1,420
Common Mode
ReJection Tests
VOH
2.'
2.'
VOL
SWi.intTi ....
Prop-o-llon Oelav
(~to +1.5 Vd(1
RilO Timo 1+1.0Vdc 10 2.0 Vdcl
Fett Timtt+l,OVdc to 2,0 Vdd
(J-·',,"~idu.lly
I
2.'
2.5
-1295
2'
2.'
0.'
0.'
I~+~
'6-5+
12+412-4+
'4+
.....
-1,28
40
-1,350
0.'
0.'
A.
~
....... Inpu'r,.-v VIH INK to pin t,lnd., teat.
4.5
+
~
~
3,7,11,15
2,6,10,14
3,7,11,15
16
,.
Vd,
16
0.'
6.0
3.3
3.3
2,6,10,14
16
4,16
16
16
Pulse In
1.0
3,7,11,15
6,10,14
Pulse Out
1
~
~
-2 OmA
-2,0 rnA
Cl (pF)
2.
6
6
2
T
120mA
20mA
1
3,7,11,15
16
1 1 1 1
BUS DRIVER
"
MECL 10,000 series
'------------'
MC10128
Ad vance InforIllation
The MC10128 is designed to provide outputs which are
compatible with IBM·type bus levels; or, if desired, it will
drive TTL type loads andlor provide TTL three·state out·
puts. The inputs accept MECL 10,000 levels. The MC·
10128 output levels can be accepted by the MC10129
Bus Receiver.
The operating mode I BM or TTL is selected by tying
the external control pins to ground or leaving them open.
Leaving a control pin open selects the TTL mode, and
tying a control pin to ground selects the I BM mode.
The TTL mode will drive a 25-ohm load, terminated to
+1.5 Vdc or a 50·ohm load, terminated to ground. The
device has totem· pole type outputs, but it also has a dis·
able input for three· state logic operation when the circuit
is used in the TTL mode. When in the high state the disable
input causes the output to exhibit a high impedance state
when it would normally be a positive logic "1" state. When
the strobe is in the high state it inhibits the output data
to the low state.
Latches are provided on each data input for temporary
storage. When the clock input is in the low logic state,
information present at the data inputs Dl and D2 will be
fed directly to the latch output. When the clock goes high,
the input data is latched. The outputs are gated to allow
full bus driving and strobing capability.
The MC10128 is useful in interfacing and bus applica·
tions in central processors, mini·computers, and peripheral
equipment.
CONTROL'
'3
0"0'-----'-10
'0
CLOCK:6--~-~
RESETo7___+-~_~
DISABLE ,'2
6--~--l----+..J
01 SAB L E
5
2:0----+-1----+...,
6
020----+-1......,
R
_ _ _3
STROBEo------------~
4
CONTROL2
Vee = Pin 14
Gnd 1
Gnd 2
= Pin
=:
16
Pin 1
Gnd 3
=:
Pin 9
Po
= 700
mW pkg/typ (No Load)
tpd = 12 ns typ
VEE = PinS
Thfll, advance information and specifications are subject to change without notice.
S •• General I nformat-ion section for packaging, and maximum ratings.
3-65
~
"fl~~:ynl'
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal
equilibrium has been established. The
circuit is in a test socket or mounted on a
printed circuit board and transverse air
flovv greater than 500 linear fpm is
maintained.
Char.t.risttc:
Negat.v. Power Supply
Drain Current
@Test
Temperature
_lODe
Symbol
I
Pin
Und.r
Te>st
-JO"e
Min
I
Mn
ICC
Input Leakage Current
linH
I
Min
VOL
'5
2
logic "1"
Threshold Voltage
VOHA
'5
2
Logic "0"
Threshold Voltage
VOLA
'5
Output S~on Circuit Current
IsC
-0.-5~-
2.5
~
0.5
0.5
~
2._5_
0.5
0.5
-1.-
260
260
2
SwitehingTimes t
Propagation Delay
'10-15-
STROBE Input
Setup Time
Hold Time
17+1517+2-
mAde
'0
logIC "0"
Output Voltage
,5
'5
15
'5
3.5
$
13+1513-15+
13+113-1+
'5
'5
tsetupH
tsetupl
tholdH
lholdl
'5
'5
Rise Time 120% to 80%1
115+
'5
'5
'5
Fall Time (20% to 80%)
"5-
'5
Apply VILmin individu.lly to pin under test.
Negative Power Supply
Drain Current
D
~'.'-
W
cD
Q)
I
T...
'ee
Input Leak. Currant
linH
-0.810
-0.700
+25OC
+85 o c
1
-1.850
-1.825
MCl0128L T. limits
-3o"e
Min
M ••
+25 o C
Min
M ••
M ..
VEE
-5.2
Vee
+6.00
IOHl
-59.3
IOH2
-30
IOL
-240
-1.1OS
-1.475
-5.2 +6.00
-59.3
-30
-240
-1.035
-1.440
-5.2 +6.00
-59.3
-30
-240
VILAm••
Unit
VIHmax VILmin VIHAlnin
97
mAde
6,11
I.
73
mAde
6,11
/lAde
10
11
12
620
350
265
265
500
VILAmax
1,4,9,13,16
I'
1,4,9,13,16
"
l,4.9,P,16
8
1
7
10
11
12
j.LAdc
logic "'"
Output Voltage
VOH
5.85
Vd,
Vd,
11
11
8
8
Logic "0"
Output Voltage
VOL
15
2
-0.5
-0.5
0.15
0.15
Vd,
Vd,
3
3
8
logic "1"
Threshold Voltage
VOHA
15
2
2.9
2.9
Vd,
Vd,
11
6
7
logic "0"
Threshold Voltage
VOLA
15
2
15
2
0.25
0.25
Vd,
Vd,
11
6
7,10
7,10
320
320
mAde
mAd,
11
6
Data Input
111+15+
111-15110-15+
110-15t7+15_
17+2_
Reset Input
STROBE Input
Setup Time
HOld Time
Aise Time (20% to 80%)
Fall Time (20% to 80%)
15
15
15
15
3.5
ffi
~~
1
10
@
1O@
10
10
11
11
15
10
10,11
10,11
7,10
7,10
3
13+1513-15+
t3+2_
t3-2+
15
15
2
2
tsetupH
1setupL
lholdH
lholdl
t15+
t15_
15
15
15
15
15
1.0
8.0
10
11
15
1.0
8.0
10
11
ApplV VILmin individually to pin under test.
Output latched to logic High st ... prior 10 tnt.
ts..w.veforns
VILA--..j
IOH2
IOL
1
"
"
1,4,9,13,16
J
!
15
15
2
2
10.11
15
!
V,H
~l00n.ec-min
I
I
8
I "
1,4,9,13,16
1,4,9,13,16
2,15
2,15
2,15
2,15
1,4.9,13,16
1,4.9,13,16
2,15
2,15
1,4,9,13,'6
1,4,9,13,16
2,15
2,15
,.,.
Pulse Out
11
6
11
,.,."
,."
1.
1.
-0.890 V -1.690 V Pulse In
23
IOH1
1 1
0.5
Switching Times t
Propagation Delay
Gnd
I'
3.11
Clock Input
C!)
Vee
15
15
'se
c:
9;
8
All
Output Short Circuit Current
::l
~.
::l
VEe
linL
-0.5
-0.5
n0
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+8S oC
Min
N
CO
/JAde
-1.500
VIHmax VILmin VIHAmin
-0.890 -1.890
-1.205
-30°C
CO"lR~'
mAd.
Volts
Temperature
'E
Positive Power Supply
Drain Current
~
TEST VOLTAGE/CURRENT VALUES
Pin
Under
Symbol
~
0
TEST VOLTAGE VALUES
STlroil J
Cb8ractermic
::
(')
L SUFFIX
CERAMIC PACKAGE
CASE 620
I
,I
1,4,9,13,16
1,4,9,13,16
1,2,4,9,13,15,16
1,2,4,9,13,15,16
I -
I
1,4,9,13,16
MC10128 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @250C -IBM MODE
VfiC~6TOV:C, ~F
Vin
-=-
r - - - - - -'4
CONTROL 1
13
----
I
450
11
o--+--~D
10
56 !!
Pulse Generator
Input Pulse
t+ '" t- '" 2.0+ 0.2 ns
(20 to 80%)
PRF
V,H
VIL
= 1.0 MHz
= -0.890
= -1.690
12
5
CL - 50pF, Including test fixture
6
3
~---""' - - - - - - - 0 . 8 9 0
50%
\..-_ _ _ -1.690
50-ohm termination to ground lo-
r------- -0.890
cated in each $Cope channel input.
All input and output cables to the
c : - - - - - - J - - - - - - - - -1.690
scope are equal lengths of 50-ohm
coaxial cable, Wire 'ength should be
1/4 inch from TPin to input pin
<
and TP out to output pin.
3-69
MC10128 (continued)
VOLTAGE WAVEFORMS
DATA INPUT
Start Cycle
'11-15 -
,----_.+--+-------------- -0.890
Oata
4-------------1.690
Ou'
STROBE INPUT
-0.890
~
-1.690
Ou'
t3+1513+2-
t3-15+
t3_2+
CLOCK INPUT
-0.890
200 nl
Data
-1.690
Clock
140
nt
Output
'10_15_
RESET INPUT
Clock
-0.890
~60n.-I
35
Resat
nl
II
\
60 ns
-
Output
1.690
0.890
\
50%
+1.5 Volts
j.:==-
'7+2_
IBM - MODE
Vo L = 0.25 Volts Max
Vo H - 5.85 Volts Min
TTL - MODE
Vo L '" 0.5 Volts Max
VOH - 2.5 Volts Min
3-70
-1.690
MECL 10,000 series
'\
QUAD BUS RECEIVER
~...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----l
MC10129
inputs must be tied to VCC or Gnd. The clock, strobe,
and reset inputs each have 50 k ohm pulldown resistors to
VEE. They may be left floating, if not used.
The MC10129 will operate in either of two modes.
The first mode is obtained by tying the hysteresis control
input to VEE. In this mode, the input threshold points
of the 0 inputs are fixed. The second mode is obtained
by tying the hysteresis control input to ground. In this
mode, input hysteresis is achieved as shown in the test
table. This hysteresis is desirable where extra noise margin is required on the 0 inputs. The other input pins are
unaffected by the mode of operation used .
The MC10129 is especially useful in interface applications for central processors, mini-computers, and peripheral equipment.
The MC10129 bus receiver works in conjunction with
the MC10128 to allow interfacing of MECL 10,000 to
other forms of logic and logic buses. The data inputs are
compatible With, and accept MTTL logic levels as well as
levels compatible with IBM-type buses. The clock, strobe,
and reset inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage elements are provided to yield temporary latch storage of
the information after receiving it from the bus. The out. puts can be strobed to allow accurate synchronization of
signals and/or connection to MECL 10,000 level buses.
When the clock is low, the outputs will follow the D in.puts, and the reset input is disabled. The latches will
store the data on the rising edge of the clock. The outputs
are enabled when the strobe input is high. Unused D
POSITIVE LOGIC
DO
7
TRUTH TABLE
1400
0
C
_
V...
i II
iiI
'VW"-"'''''''IICIl_.,!he1-
Reset _ _ _ _ _ _ _J
1-=:::------
+1.11 V
' - - - - - +0.31 V
- - - - - +0.31 V
Clock
+1.1' V
tl1-14+
t11-14+0.31 V
FIGURE 5 - TSET UP AND THOLo WAVEFORMS
+1.11 V
50%
r----_, - - - - - - +5.00 V
/50%
o _ _ _-¥
20%
150%
----+2.400 V
D~L-
'~'up
+0.31 V
C
tl1-14+
t10+14-
3-74
F-'-h-O-'d---
+1.11V
50%
+0.31 V
'\
MECL 10,000 series
"-------------'
DUAL LATCH
MC10130
POSITIVE LOGIC
NEGATIVE LOGIC
515------,
C
Al 5 - - - - - - ,
9
5213-+-----,
~e2
11
eE2 11 - - , - - - - "
0210
15
A212------
TRUTH TABLE
CE
vee1 : : :
Pin 1
VCC2 "" Pin 16
VeE"" Pin 8
On+1
L
Co
Co
Co
f/! - Don', Ca,.
Po
tpd
= 155 mW typ/pkg
= 2.5 ns typ
(No Load)
CIRCUIT SCHEMATIC
s .. Gen • • llnformatlon section for
packaging.
3·75
The MC10130 is a clocked dual D type latch.
Each latch may be clocked separately by holding
the common clock in the low state, and using
the clock enable inputs for the clocking function.
If the common clock is to be used to clock the
latch, the clock enable (CE) inputs must be in
the low state. In this mode, the enable inputs
perform the function of controlling the common
clock (e).
Any change at the D input will be reflected
at the output while the clock is low. The outputs are latched on the positive transition of the
clock. While the clock is in the high state, a
change in the information present at the data
inputs will not affect the output information.
Input pulldown resistors eliminate the need
to tie unused inputs to VEE.
Output rise and fall times have been optimized to provide relaxation of system layout
and design criteria.
The set and reset inputs do not override the
clock and D inputs. They are effective only
when either C or CE or both are high.
ELECTRICAL CHARACTERISTICS
3:
n
o
...
...
Each MECL 10,000 series circuit has been
designed to meet the de specifications
Sl 5----------------
shown in the test table, after thermal equi·
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one latch. The other latch is tested
in the same manner.
01
7
CE 1
6
Col
o
8::J
..
3
Rl
-
4~
R~ 1:---r-1-----------14
CE211~
0210
~
S212
to)
~
0)
Characteristic
PO\l\ler Supply Drain Current
Input Current
Symbol
Pin
Und..
Test
-
Min
Typ
-
30
35
-
-
220
265
285
285
-
0.50
-
-
Max
Min
4-
VOH
2
-1.060
-0.890
-0.960
-
-0.810
VOL
2
-1.890
-1.675
-1.850
-
-1.650
VOHA
2
-1.080
-
-0.980
-
-
-0910
-
eASE 620
TEST VOLTAGE VALUES
VIHmax
VILmm
VIHAmin
VILAmax
VEE
_lODe
·0.890
-1.890
-1.205
-1.500
-5.2
+2SoC
-0.810
-1.850
-1.105
-1.475
-5.2
+8SoC
-0.700
-1.825
-1.035
-1.440
-5.2
TEST VOL TAGE APPlIEO TO PINS lISTEO BELOW,
+8So C
+2Soc
Max
~
L SUFFIX
CERAMIC PACKAGE
(Volts)
Temperature
I inL
8
6,11
9
Logic "1"
Output Voltage
_lODe
c:
@Test
-
IE
linH
4,5,9
7,10,12,13
Logic "0"
:~~15
MC10130L Test Limits
Min
~.
::J
-
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(Vee'
Gnd
mAde
-
--
-
1,16
6,11
9
4,5,9
7,10,12,13
-
8
/JAde
8
1,16
Ma.
Unit
-
-
9
-
-
J.lAdc
-
4
.-
-0.890
-0.700
Vdc
5
.-
-
-
-1.825
-1.615
Vdc
4
-
-
-
Vdc
-
9
7
-
-
-
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
7
5
4
6
2
8
1,16
-
+
+
+
8
1,16
8
1,16
8
1,16
8
1,16
Output Voltage
Logic ''1''
Threshold Voltage
Logic "0"
Threshold Voltage
Switching Times (50
(See Figure 1)
Propagation Delay
2
VOLA
-
-1.655
-
-
-1.630
-
-1.595
Vdc
n Load)
-
9
+1.11 V
17+2+
15+2+
14+216-2+
Rise Time (20% to 80%1
'2+
Fall Time (20% to 80%1
'2-
Setup Time
1.tup
Hold Time
thold.....::...:...
2
1.0
II
-All other inputsar. tested in the same manner
2
2
-
3.6
3.6
3.6
4.3
1.0
3.6
1.1
3.6
1.1
-
25
1.5
+
4.0
1.0
1.1
1.1
1.0
3.8
3.9
3.9
4.1
3.5
1.1
3.B
2.7
3.5
1.1
3.8
-
-
-
-
2.5
2.7
2.7
3.5
2.7
•
n,
-
-
I
6
6
-
n,
ns
-
an
H
L
L
H
H
H
L
H
L
H
H
L
L
L
If!
L
L
L
H
(/)
E
vee1
0= IA. 011) + IA. 012)
an
an
an
= Pin
1
VCC2 = Pin 16
VeE = Pin 8
H
an
an
On
Po
tpd
L
Don't Car.
SH General Information section for packaging.
3·83
=
225 mW tvp/pkg (No Load)
:::%
3.0 ns typ
s:
ELECTRICAL CHARACTERISTICS
n
Each MECL 10.000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal equ jlibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear 'pm is maintained. Outputs
are terminated through a SO-ohm resistor to
~
~e
~
Cc'
2
N
Q,
nO
~
0
' 2,.
5
CEO
manner.
to)
11""---'
011 4
-2.0 volts. Test procedures are shown for
only one Iltch. The other latches are tested
in the
o
Al1
::J
~.
3
---'~H;-
T
R6
01
::J
C
,-,
=:: ,: • III
~
.
_
LSUFFIX
CERAMIC PACKAGE
CASE 620
hL/.=:::r--
02212
CD
Q.
15 02
140.2
TEST VOL TAGE VALUES
(Volts)
~T"t
Tempere'ure
Co)
t
l
I
Ch"Kteriltic
Power Supply Current
I
I
Input Current
'in H
Test
_lOGe
Min
I
Min
Typ
M ..
44
55
290
290
390
290
265
265
4
5
6
7
10
11
'in L
logic "1"
Output Voltagl
VOH
Logic "0"
Output Voltage
VOL
Logic "'"
Threshold Voltage
VOHA
Logic "0"
Threshold Voltage
VOLA
VIHA min
-1.205
VILA max
-1.500
+2S oc
-0.810
-1.850
-1.105
-1.475
+8SoC
-0.700
-'.825
-1.035
-1.440
Min
1Vee'
M ••
Unit
1
Data
Aeset
Clock
Select
t4+2+
t6+2t7-2+
t11+2-+
Setup Time
Data
Select
tsetup
lsetup
Hold Time
Data
Sliect
Ri. Time (20% to 80%)
(2~
-All other inputs tIIted·in·th.
lt10ld
lt10ld
'2+
'2_
to 80%)
~ m"1I~.r.
7
10
11
-0.890
-0.890
-0.960
-0.960
-0.810
-0.890
-{I.890
-0.700
-0.810
-0,700
Vd,
Vd,
5,11
7,9,10
7,9,10
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1,615
-'.615
Vd,
Vd,
4
5,11
7,9,10
7,9,10
Vd,
Vd,
11
7,9,10
7,9,10
Vd,
Vd,
11
-0.910
-0.910
-1.655
-1,655
2
~
I
4
J.lAdc
-0.980
-0.980
-1,630
-1.630
1.0
1.0
1.0
1.0
2.5
3.5
1.5
1.0
1.5
1.'
-
I
I
3.3
3.8
5.7
4.6
3.5
3.5
VIHA min
VILA
INX
-1.595
-1.595
I
•
VEE
Gn.
a
1,16
---s- r--;-:-;s
l.11V
ProP8lJ8ltion Delay
Vll min
.uAdc
SWitching Times (5().ohm load)
hit Ti.,.
VIH max
mAde
-1.060
-1.060
-'.080
-1.080
-5.2
-5.2
-5.2
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
0.50
4"
VEE
+8S0C
+25 0 C
M ••
a
IE
VIL min
-1.890
MCl0132L Test Limits
Und",
PI"
Symbol
_lODe
VIH INX
-0.890
--
-
-
-
4
11
8
8
8
8
8·
1.16
1.16
8
1,16
1,16
1,16
1,16
5
-
a
7,9,10
7,9,10
4
5
-
8
8
1.16
1,16
+0.31 V
Pulse In
Pulse Out
-3.2 V
+2.0V
7,9,10
4
2
8
1,16
•
8
8
8
8
8
8
1,16
1,16
7
11
11
7
4,10
10,11
11
7
4,10
10,11
7,9,10
4
7,9,10
4
2
2
2
2
2
2
~
1,16
•
1,16
1.16
1,16
1,16
ElECTRICAL CHARACTERISTICS
r--=--"
!
3:
'"
Each MECL 10,000 senes circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The Circuit is
In a test socket or mounted on a printed
o
11.,---...
011 4
circuit board and transverse air flow greater
than 500 linear fpm IS maintained. Outputs
are terminated through a 5()..ohm reSIstor to
-2.0 volts. Test procedures are shown for
only one latch. The other latches are tested
in the same manner.
...
...
(")
All
2
Cc 7
A 6
O
::J
3
01
15 Q2
III~
~-===r--
02212
~.
-
r-----l
T
~:,',:
N
c:;-
~
0125
CEO
'0
W
Q,
::J
c:
(I)
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Voltsl
(ilT"t
Tempereture
_30o e
Under
w
U1
Characteristic
Po~r
Symbol
Supply Current
T...
~-:!!;~--+----r2!;!...!:,-~-+--:-::...:..::r-=::
44
-1.105
-1.475
-5.2
-1.825
-1.035
-1.440
-5.2
(Vee l
Unit
"f
Vd,
Vd,
VOL
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.615
-1.615
Vd,
Vd,
VOHA
-1080
-1.080
Vd,
Vd,
-0.980
-0.980
-1630
-1630
-1.595
-1.595
Vd,
Vd<
SWitching Times (Sl).ohm load)
Data
Reset
Clock
Select
t4+2+
ts+2t7_2+
tl1+2+
Setup Time
Data
Select
tsetup
tsBtup
Data
Select
thold
thold
HOld Time
R lie Time (20% to 80%)
'2'
'2-
Fall Time 120% to 80%)
• All other Inputs tested
In
the same manner.
2
~
1.0
1.0
1.0
1.0
2.5
3.5
1.5
1.0
1.5
1.5
I
Vll min
I VIHA min I
VILA INX I
3.3
3.8
5.7
4.6
3.5
3.5
VEE
Gnd
8
1.16
1,16
4
5
6
7
10
l'
1 1
1,16
~Adc
050
-1.655
-1.655
VIH m ••
mAde
55
-0.700
-0.700
Propagation Delav
-5.2
-1.850
-0.810
-0.810
VOLA
VILA ....
-1.500
VEE
-1.205
-0.700
-0.960
-0960
Logic "0"
Output Voltage
Logic "0"
Threshold Voltage
..
2
2
I VIHA min
-0.810
-0.890
-0.890
VOH
VIL min
-1.890
+8SoC
-1060
-1.060
Logie "I"
Output Voltage
Logic "'"
Tlue5l'l0ld Voltage
I
290
290
390
290
265
265
7
10
11
lin L
J
TEST VOL TAGE APPLIED TO PINS LISTED BELOW;
'E
lin H
Input Current
VIH m. .
-0.890
+2SoC
Pin
00
Co
PSUFFIX
5,11
1,16
1,16
7,9,10
7,9,10
11
1,9,10
1.9.10
8
8
8
8
1,16
1,16
PuI.Ou1
-3.2 V
+2.0V
2
8
1,16
8
7,9,10
11
7,9.10
+1.11 V
+0.31 V
Pul .. ln
I
7,9,10
•
1,18
1,16
8
5,11
7,9,10
7,9,10
4
7
tt
1i
4,10
10,11
7
11
7
7,9,10
7,9,10
4,10
10,11
1,16
1,16
• • •
2
2
8
8
1,16
1,16
2
2
8
8
1,16
1,16
1,16
1,16
MC10132 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
vee1 '" VCC2 =
+2.0 Vdc
25~F$f$01~F
Input Pulse
t+ = t- = 2.0 ± 0.2 nl
V out
r-----------,
I
(20 to 80%)
Coa)(
I
I
\
TP out
50 ol"lm termonation to ground 10
cated
In
each scope channel ,nput
All Input and outj.Jut cables to the
scope are equal lengths of 50 ohm
caallial cable
Wife length sho,Jld
be < 1/4 Inch from TP. n to Input
pm and TP out to output pm
Unused outputs connected to a
50-ohm resistor to ground.
-JI ______
C Input _ _ _ _
o
a
n
-
_
-
___
:~~::
~---------- +1.11 V
Input
--_'+. ___________ +0.31 V
D
"----+031 V
~-----+'.'1
V
Output
C - - - - -I ------------+031 V
~---'------ +1.11 V
A Input
_ _ _ _ _ _J ________________ +0.31 V
NOTE:
t setup is the minimum time before the positive transition of the clock pulse (e) that information mun be
pr.,ent at the data input (0).
thold is the minimum time .fter the positive tran·
litian of the clock pulse (e) that information must
remain uncnanged at the data input (D).
3-86
MC10132 (continued)
APPLICATION INFORMATION
A typical application of the MC10132 is temporary
,storage in a minicomputer. The arithmetic section of a
minicomputer might have a configuration similar to that
illustrated in Figure 1. Data may be entered into the "B"
register from either the register file or the input bus, re-
quiring a multiplexed input to the register.
Figure 2 shows the MC10132 as the elements in the
"B" register. Eight packages of the dual latch is necessary
to construct a 16-bit register. Note that reset is available
on the MC10132 if this capability is required.
FIGURE 1
Register File
16 x 16 Bit
Output Bus
Input Bus
FIGURE 2
Data lines from Register File
(_-----------------------------A-----------------------------~
Data
Lin ..
from
Input
BUI
Receiver
II
I
_I\J..~1I2 2~ ~I
I~ ~~ ~II~ ~~ -II~ 2- ~H~ 2~ 2~J I~ 2~ 2~II~ 2~
~II~ 2~
2
101 2
2
N
-N'"
Mgl0l~2
I
I
N
_N.....
'1lCl0~2
I
I
N
-N'"
Mffl0~2
I
I
N
_,..,
...
Me=101e
I
I
N
_N'"
MS=101e
I
I
Mi3
il
I
I
N"'t..)...
N
N
MpCl0le
I
I
_N
...
Mfole
I
I
\----------------------------~y-----------------------------~)
Data Lines to Arithmetic Logic
3-87
'\
QUAD LATCH
MECL 10,000 series
'-_ _ _ _ _ _- - - - - 1
MC10133
The MC10133 is a high speed, low 'power,
MECL quad latch consisting of four bistable
latch circuits with D type inputs and gated
outputs. Open emitters allow a large number of
outputs to be wire ORed together. Latch outputs are gated, allowing direct wiring to a bus.
When the clock is high, outputs will follow 0
inputs. Information is latched on negative going
transition of the clock.
'
a
TRUTH TABLE
G c 0 On+1
H
rt> rt>
L
L
L rt>
H L
an
L
H
H
Po = 310 mW typ/pkg (No Load)
L
tpd = 4.0 ns typ
H
L
tj)- Oont Care
C "" Cc + CE
DO 3
2
00
6
01
GO 5
01
7
CE
4
Cc 13
CE
12
02
9
1102
(3110
15 03
0314
veel = Pin 1
VCC2 = Pin 16
VEE=Pin8
See General Information section for packaging.
3·88
"I:i~'\rjM' ~::;, ~'~:. ~Q:
f'5J'!;rf::1I'~ ,l.r.,,~··-,rl<-:
',p"
';f.".'
ElECTRICAr'cHARAC"rERISftCS .
OO·.3~
2 00
~o.
6
EaCh MECL 10,000 seri •• has been de·
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Output :0 GIl::
'r to
01
7
EE
4
.~
I "'I
Cc 13
dor
~sted
Symbol
Pin
Under
Test
IF
8
linH
3
Power SUpply Drain Current
Input Current
lin
w
eX!
(D
LogiC "1"
OutPut Voltage
VOH
LogIC "0"
Output Voltage
VOL
Logic "1"
Threshold Voltage
Logic "0"
Threshold Voltage
VOHA
VOLA
VIH max
VIL min
VIHA min
VILA max
VEE
_30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25 0 C
-0.810
-1.850
-1.105
-0.700
-1.825
-1.035
-1.475
-1.440
-5.2
+85 0 C
0.3
MC10133L Test Limits
TVp
-
-
3
-
0.5
-
-
2
2
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
2
2
2
-1.890
-1.675
-1.850
2
2
2
2t
2tt
2tt
2
2
-1.080
2
2
2
2t
2tt
2tt
-
-1.655
-
1
-
1.0
1.0
1.0
5.6
1.0
3.2
-
-
j
-
-
-0.980
j
-
-
Max
Min
60
75
-
245
265
350
350
-
Max
2
2
3
3
Rise Time (20% to 80%)
'2+
2
1.0
3.6
2.5
1.5
1.1
Fall Time (20% to 80%)
'2-
2
1.0
3.6
1.1
tOutput level to be measured after
iii
,,4
-
+
:J
c:
CO
.e:
-5.2
Unit
VIH max
VIL min
VIHAmin
VILA max
VEE
tVccl
Gnd
..
mAdc
-
13
8
1,16
JiAdc
-
-
8
1,16
-
-
-
-
3
4
5
13
-
-
-
-
-
-
3
-
-
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
3.4
3,13
-
-
-1.650
-1.825
-1.615
Vdc
•
+
+
13
3,5,13
4
-
-
-
-
..
-
-
-
-0910
j
-1.630
1
,
Vdc
-
_.
-
-
+
JiAdc
-
-1.595
-
-
-
j
Vdc
1 1
3.4
4
3.4
3
3
3
3.4
4
4
3
3
-
5.4
5.4
3.1
.
-
clock pulse has been applied to the clock input (Pm 41.
ttData input at proper high/low level while clock pulse is high so that device latches at proper
highltow level. for test. Levels are measured after device has latched.
1.1
1.2
1.0
5.9
6.0
3.4
-
-
-
3.5
1.1
~~-
~~
3.8
3.8
ILV1Hma)(
VIL min
----
ns
j
4
3 •
-
•
•
-
-
3
3
.-
-
-
5
3
-
-
-
4
4
13
-
5
-
+
•
8
1,16
8
8
1,16
1,16
8
1.16
8
1,16
•
1
8
,
j
1,16
3
-
-
13
Pulse In
Pulse Out
-J,2V
+2.0V
3
4
5
3
3
2
2
2
2
2
8
1,16
3
2
3
2
-
-
' - -.
'--- • Latch set to zero state before test.
-
-
-
-
+1.11 V
2
t3+2+
t4+2+
t5_2+
tSetup
tHold
:J
!:'.
(Voltsl
+8SoC
Min
• • •
TEST VOLTAGE VALUES
TEST VOL TAGE APPLIED TO PINS LISTED BELDW,
+2SoC
_30D C
Switching Times
150 l! Loadl
Propagation Delay
8
15 Q3
Max
5
13
Co)
Co)
CERAMIC PACKAGE
CASE 620
@Test
Temperature
Gl10
Min
4
-
......
L SUFFIX
::':~"O'
0314
Characteristic
al
3:
n
o
--
1 1
j
I
E lECTR ICAl CHARACTER 1ST ICS
2
Each MECL 10,000 series has been de·
signed to meet the de specifications shown
in the test table. after thermal equfiibrium
has been established. The circuit is in a
~~
test socket or mounted on a printed circuit
CE
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
I~
4
00
6
--
01
Cc 13
a,,~
~,.~
"0'
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
_JODe
Under
Characteristic
Power Supply Drain Current
Input Current
::J
VIHA min
VILA max
VEE
c:
(1)
_JODe
-0.890
-1.890
-1.205
-1.500
-5.2
Q.
+250 C
-0.810
-1.850
-1.105
-1.475
-5.2
+8So C
-0.700
-1.825
-1.035
-1.440
-5.2
to)
~
Logic "1"
Output Voltage
Logic ·"0"
Logic "0"
Threshold Voltage
Ma.
Min
TVp
Ma.
Ma.
Unit
VIH maK
VIL min
'E
8
-
60
75
-
-
mAde
-
13
ImH
3
4
5
13
-
-
-
245
265
350
350
-
-
~Adc
3
4
5
13
-
-
3
'inL
3
VOH
2
2
-1.0E0
-1.0E0
-0.890
-0.890
-0.960
-0.960
VOL
2
2
2
-1.890
-1.675
-1.850
2
2
2
21
211
211
2
2
-1.080
VOHA
VOLA
2
2
2
21
211
211
0.5
-
-
-
-
-
-
+
.u.Adc
j
-
-1.655
-
-
-0.980
j
-
-
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
3.4
3,13
-1.650
-1.825
-1.615
Vdc
13
3,5,13
4
-
l
-
j
-
-
-
-
-1.630
-
-
-0.910
-
-
Vdc
j
1
-
-
-
-
3
-
3
..
-
3.4
4
4
-
-
-
Vdc
1 1
3
3
-
-
'Setup
'Hold
Rise Time 420% to 80%)
'2+
2
Fall Time 120% to 80%)
'2_
2
13+2+
'4+2+
'5-2+
-
-
-
1.0
+
2.5
1.5
1.1
1.1
-
5.4
5.4
3.1
at proper· high/low I41verwhile ctOek pulse is high so that devicalatches.jll Pfoper
high/low level for test. Level, ara measured aftar device has latched.
-
-
-
-
-
3.5
-
-
3.5
-
.Jl:VIHmax
YlL min.
ns
-
-
tOutput level to be measured after a clock pulse has been applied to the clock input"(Pin 41.
-
-
j
4
3 •
4
4
VILA max
VEE
(Vee l
Gnd
-
8
1,16
8
1,16
..
-
+
+
-
8
1,16
-
8
8
1.16
1,16
8
1.16
..
5
-
-
-1.595
..
-
..
..
-
-
3
3
-
-
-
3,4
4
3,4
3
VIHA min
-
3
..
..
-
-
-
-
4
4
13
-
5
-
t
8
,
1,16
j j
8
1,16
3
-
-
13
Pulse In
Pulse Out
-3.2V
+2.0V
2
2
2
2
2
8
1,16
-
3
4
5
3
3
-
3
2
3
2
-
+1.11 V
2
2
2
3
3
ttO ata input
Min
,,, ,,,,
Switching Times
(50 H Loadl
Propagation Delay
+8SoC
+25 O C
Min
Output Voltage
Logic "1"
Threshold Voltage
TEST VOLTAGE APPLIED TO PINS LISTED BElOW,
Test
-
IVolts)
VIL min
Symbol
-
(")
o
::J
,...
VIHmax
MC10133P Test Limits
Pin
w
@Test
Temperature
1503
03
....w
PLASTIC PACKAGE
CASE 648
TEST VOL TAGE VALUES
Gl10
0314
s:
(')
....
o
P SUFFIX
-
..
-
-
":• Latch set to zero state before test.
-
1
l
j j
MC10133(continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 250 C
VCCl : VCC2
+2.0 Vdc
Vin
V out
~"'t tt"" ~.
PROPAGATION DELAY
r----- -- --...,
I
+1.11 V
50%
Input Pulse
t+
c
t- = 2.0
± 0.2 ns
(20 to 80%)
Vout from 0 input
50-ohm termination to ground 10- I
,ceted in each scope channal input._.;-1------"'1
Vout from
-t-=-,----...J
I
L ____
Unused outputs connected to
a 50-ohm resistor to ground.
1
~
0.1
~F
G input
C
VEE: -3.2 Vdc
o
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cabl.. Wire length should
a
be < 1/4 Inch from TPin to input
pin and TP out to output pin.
1
_--.-J
tSetup is minimum time before the negative transition of the clock
pulse (e) that information must be present at the data input (D),
tHold is the minimum time after the negative transition of the clock
pulse ee) that information must remain unchanged at the data input (0).
The latch will store the data on the falling edge of the
clock. The outputs are gated when the output enable is
low. All four latches may be clocked at one time with the
common clock, or each half may be clocked separately
with its clock. This device is useful as a temporary storage
element in high speed central processors, accumulators,
register files, digital communication systems, instrumenta·
tion and test equipment.
APPLICATION INFORMATION
The MC10133 device consists of four bistable latch
circuits with 0 type inputs and gated Q outputs. When
the clock is high the outputs will follow the 0 inputs.
3-91
MECL 10,000 series
DUAL MULTIPLEXER
WITH LATCH
MC10134
The MC1D134 is a dual multiplexer with clocked D
type latches. Each latch may be clocked separately by
holding the common clock in the low state, and using the
clock enable inputs for the clocking function. If the com',
mon clock is to be used to clock the latch, the clock enable
(CE) inputs must be in the low state. In this mode, the
enable inputs perform the function of controlling the com,
mon clock (CC).
The data select inputs determine which data input is
enabled. A high (H) level on the AD input enables data input
D12 and a low (L) level on the AD input enables data input
D11. A high (H) level on the A1 input enables data input,
D22 and a low (L) level on the A 1 input enables data,
input D21.
Any change on the data input will be reflected at the
outputs while the clock is low. The outputs are latched.
on the positive transition of the clock. While the clock is
in the high state, a change in the information present at'
the data inputs will not affect the output information.
, Output rise and fall times have been optimized to pro,.
vide relaxation of system layout and design criteria.
POSITIVE LOGIC
NEGATIVE LOGIC
AO 6
AO 6
11
AlII
Al
011
4 ----+++I~I.....,
012 5
2
011 4
01
----++--w:......./
012 5
GE010
3 01
CE010
Gc
7
CEI
9
Cc 7
GEl
15 02
9
021 13 -----~~~--,
02113
14 02
02212
02212
TRUTH TABLE
C
AO
L
L
L
L
4>
H
H
H
4>
4>
4>
an
cP C
011
012
On+l
L
L
L
4>
4>
L
H
H
H
4>
L
L
= Pin
1
VCC2
= Pin
16
Vee =
Pin
8
H
Po = 225 mW tvp/pkg (No Load)
tpd'" 3.0 ns typo
Don t Care
= CE
veel
+ Cc
See General Information section for packaging.
3-92
,
~""""""~~_.:.r.~:~.'~:::'~~.10
......:;;:;'. ~'.< .
ELecTRICAL CHARACTERISTICS
E";h
MEet 10,000 ~r,sclri:ui'thas been
designed to· \ meet·· the dc specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one latch. The other latches are tested
in the same manner,
..o..
3:
.00.
AI
o
11
~~'~,~
CE1
~
IIII~
0114
.11 ~
II ==:::::
9
D2113
2
Q,
3
a,
15
~
nv;~:l~; if I:
g
::J
....
I
a~
5'
c(1)
L SUFFIX
CERAMIC PACKAGe
CASE 620
.e:
D2212~r---14C2
TEST VOL TAGE VALUES
(Voltsl
@Test
Temperature
-lOoe
+25 o C
+8So C
w
W
w
Characteristic
SYmbol
Power Supply Drain Current
Pin
Under
T..t
Min
M ••
Min
55
lin H
.....
290
7
290
10
logic "1"
Output Voltage
VOH
2
2
Logic "a"
Output Voltage
Unit
"f
290
4'
265
0.50
-0.890
-0.890
-0.960
-0.9S0
-0814[)
-0.890
-0.81~
-0890
-0.700
-0.700
Vdc
Vdc
VOL
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.651t)
-1.65eo
logic "1"
Threshold VOltage
-1.825
-1.825
-1615
-1.615
VOHA
-1.080
-1.080
Logic "0"
Threshold Voltage
VOLA
Propagation Delay
Setup Time
Hold Time
-0.980
-0.980
-1.655
-1.655
Data
Salect
Data
Seloct
Rise Time (20% to 80%)
Fall Time (20% to 80%)
• All other inputs tested in the same manner.
t.4+2+
tl0-2+
'6+2+
tsetup
t setup
lt10ld
thold
'2+
'2_
2
•
-0.910
-0.910
-1.6Jt:)
-163(;)
~
Data
Clock
Select
VILA milk
-1.500
VEE
-0.810
-1.850
-1.105
-1.475
-5.2
-0.700
-1.625
-1.035
-1.440
-5.2
1.0
1.0
1.0
2.5
3.5
VIH max
VIL min
I
VIHA min
I
VILA max
4
5
6
7.
10
5.2
VEE
-1.595
-1.595
1Veel
Gnd
1.16
1.16 '
4
5.6
6,7.10.
7.10
1,16
1,16
Vdc
Vdc
4.6.7,10.
5,7.10
1,16
1,16
Vdc
Vdc
6.7,10
7,10
Vdc
Vdc
6,7,10
M..
3.3
n•
5.7
t
4.6
I
11 T
~Adc
-1.060
-1.060
SWItchmg Times 150-ohm load)
VIHA min
-1.205
mAdc
265
lin L
VIL min
-1.890
TEST VOL TAGE APPLIED TO PINS LISTED BELOW
Ie
Input Current
VIH max
-0.890
~
8
8
1,16
1,16
Pul.Out
-l.2V
+2.0V
4
2
8
1,16
10
t
1,16
1,16
~.10
.0.31 V
., 6.7.10
7
·"'7.10
6.7
7,11
PuI_ln.
6
4,10
6.10
t
t
m
1.16
1.5
1.0
1.5
3.5
6.7.TIi
1.5
m
3.5
6,7.10
1.16
6.7
7.11
4.10
6.10
ill
1.16
....s:
ELECTRICAL CHARACTERISTICS
Each MEeL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures Ire shown for
only one latch. The other latches are tested
in the same manner.
o
AO 6
o
~
nO
A,111
Dl1
1111.,-...
4
;:;,:
Cc 7
•
II
II
~~:1:
~
-
0'
J
1502
~
::J
02212~~14Q2
::t,
::J
C
It>
P SUFFIX
Cl.
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Volts)
til Test
Temperature
c.l
~
CharKteristic
Symbol
Power Supply Drain Current
Pin
Under
T...
....
-30"<:
I
+2S0C
I Min
7
10
~
LogiC ''1''
Output Voltage
-1060
-1.060
-0.890
-0.960
-0.890
VOL
-1.890
-1.890
-1.675
-1.675
Logic "I"
Thresl"lold Voltage
VOHA
-1.080
-1.080
LogiC "0"
Threshold Voltage
VOLA
LogiC "0"
Output Voltage
Propagation Delay
Setup Time
Hold Time
Data
Clock
Select
Data
Select
l4+2+
tlO_2+
ts+2+
tsetup
tsetup
Data
Select
"'old
ltlold
Rise Time (20% to 80%1
'2.
Fall Time '(20% to 80%)
'2-
• All other inputs tested in the serne manner.
2
t
Min
-1.850
-1.105
-1.475
-5.2
+850 C
-0.700
-1.035
-1.440
-5.2
M..
Unit
"f
-1.625
I
-5.2
VIH m..
I
VIL min
I
VIHA min
I
VILA max
I
VEe
-0.960
-1.850
-1.850
-1.650
-1.650
-0.980
-0980
1,16
Min
M..
1.0
1.0
1.0
2.5
3.5
3.3
5.7
4.6
6.7,10.
7.10
1.16
1,16
Vdc
Vdc
4.6.7.10,
5,7,10
1,16
1,16
Vdc
Vdc
6,7,10
7,10
6,7,10
7,10
1,16
1,16
-0.890
-0.700
-0.700
Vdc
Vdc
-1.825
-1.825
-1.615
-1.615
-0.910
-0.910
-1.630
-1.630
-1.595
-1.595
4
5,6
Vdc
Vdc
+1.11 V
l
+0,31 V
7,10
6.7
6,7
1.0
~
3.5
1,16
1,16
Pulse In
6,7,10
7,11
1:5
(Vee l
Gnd
1.16
11 T
10
/JAdc
-0.890
1.5
I
min
mAdc
-0.810
-0.810
-1.655
-1.655
Switcl"llng Times 150-ohm loadl
-1.205
-0.810
+8S0C
I ....
0.50
4'
VOH
-1.890
VILA nux
-1.500
VEE
-0.890
Vil min
TEST VOL TAGE APPLIED TO PINS LISTED BELOW
55
290
290
265
290
265
'E
i";;"H
Input Current
I VIHA
-lOGe
MC10134P Test Limits
Min
I
+25 o c
VIH mu.
10
6
4,10
6,10
7,11
4,10
6,10
6,7,10
4
6,7,10
I
Pulse Out
I
-3.2 V
I +2.0 V
2
8
1,16
2
2
2
2
2
8
8
8
8
8
1,16
1,16
t
t
t
1,16
1,16
1,16
1,16
MC10134 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
V out
Input Pulse
t+ = t- = 2 a ns ±
a
2 n5
(20 to 80%)
Coax
n
Dalal~
TPin/
50-ohm termination to ground 10'
cated in each scope channel input
All input and output cables to the
scope are equal lengths of S.O-ohm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
Unused outputs are terminated
50-ohm resistor to ground.
I
I
~-----10~:-_1
VEE
LY2
Vdc
J/n ______ _____ :~::::
C Input _ _ _ _ _
~-----------
o
Input
~
+1. II V
___,,-+____________ +0.31
V
_ _......,,_ _ _ _ _ +1. II V
o
'-----+0.31 V
+---~-~thold
~
a
_ _ _ _ _ +1.11 V
Output
C - - - - - - ' - - - - - - - - +0.31 V
NOTE'
tsetup is the minimum time before the positive transition of the clock pulse (C) that information must be
pre.ent 8t the data input (0),
thold is the minimum time after the positive transition of the clock pulse (e) that information mult
remain unchanged at the date input (0),
3-95
a~
MC10134 (continued)
APPLICATION INFORMATION
A typical application of the MC10134 is temporary
storage in a minicomputer. The arithmetic section of a
minicomputer might have a configuration similar to that
illustrated in Figure 1. Data may be entered into the "B"
register from either the register file or the input bus, reo
quiring a multiplexed input to the register.
Figure 2 shows the MC10134 as the elements in the
"B" register. Eight dual latch packages are necessary to
construct a 16·bit register.
FIGURE 1
Aegister File
16 Ii( 16 Bit
Output Bus
Input Bus
FIGURE 2
Data Linas from Register Fil.
( r - - - - - - - - - - - -_________________ A~_____________________________,
Oeta
Lina,
from
Input
Bu.
Receiver
I I 1
[2 2~ ':[[2 2~ ~II~ 2~ ~1I2 2~ ~H2 2~ ~H2 2~ ~J 12 2~ ~112 2~ ~I
_p,J
1'1.)
...
MB10le 4
I
I
"'
...
IIJ
....
M§101§4
I
I
N
.... N
...
M8101~4
I
I
'"
..oN'"
MfOl~4
I
I
II.)
_I\J'"
MfOl§4
I
I
IIJ
... IIJ
...
M8101~4
I
I
N
.... I\J
...
M8101~4
I
I
N
_I\J
...
Me 101e 4
I
I
\------------------------------~y~----------------------------~)
Data Lines to Arithmetic Logic
3-96
MECL 10,000 series
DUAL J-K MASTER-SLAVE
FLIP-FLOP
MC10135
POSITIVE LOGtc
5'
•
,
.
"
The Me 10135 is a dual master-slave dc coupled J-K flip-flop" Asynchronous set (S) and reset
(R) are provided. The set and reset inputs override the clock.
A common clock is provided with separate
J-K inputs. When the clock is static. the J-i<
inputs do not effect the output .
The output states of the flip-flop change on
the positive transition of the clock .
Input pulldown "resistors eliminate the need
to tie unused inputs to VEE. Output rise and
fall times have been optimized to provide relaxation of system design and layout criteria.
NEGATIVE LOGIC
~,
5---~
J1
,
,•
"' ••
5212
• , 4_1-_--1
l! •
C
1212-1--~
J210
J210
15
'4
il211
"213
"213;----
vee1 '" Pin 1
VCC2 = Pin 16
CLOCK J.K TRUTH TABLE·
R-8 TRUTH TABLE
Qn
a n +1
an
H
L
Q n+1
Vee == Pin
8
Po ~ 280 mW typ/pk. (No Load)
fTog -= 140 MHz tvp
·Output l1.t.. ch,ne- on pOlio
,ive ,.,n,I,lon of clock fa.]·
N.D. - Not O.fined
i( input condition p ....nt.
CIRCUIT SCHEMATIC
1/20F CIRCUIT SHOWN
MASTER
h
rYl~ 51""'"
124
I
,0>-
1.914 k
'"17
>----
~
1.11Sk
647
30'
30'
1.34311
1.3"3k
)-
t·,
1.91" k
~
~~
~t'->=
)
~
Kt-<
~
!iii -':
~
y
"
I
'6.
~~~
,J"
'0'(
'"
'68
\-
rr
i
Y
)
124
Vee 2
Vee'
LAVE
R
13
,
..
,.,
I--
43
1.0910;
" L -_ _ _ _ _ _ _ _-'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.-J
8M G . . . .I Information section for packaging.
3-97
51
5
j 1
7 -------"'
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet thedc specifications shown
---'"
in the test table. after thermal equilibrium
K 1 6 - ---'"
has been established in an ambient temperature of 2SoC, while the circuit is in a test
Al
socku or mounted on a printed circuit
~
4
Q2111o.......-'5
w..
Other inputs tested in the same
J
A2 13
Symbol
W
CO
I
I
Min
lin H
+25 oC
+SSoC
MC10135L Test Limits
+2S oC
-lOoe
Max
Min
IE
Input Current
cO
Pin
Under
Test
@T...
Temperature
_JODe
62~14
j(:2 1 1 -------AI
manner.
ChllrKt_istic
!
r
' ] 2 1 0 - -"'"
TV.
54
6.7.9.10.11
4,5,12,13
3:
n
-
Ql~J
5212
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input, or for one set of input con-
Power Supply Drain Current
Ql~2
c ._
board and transverse air flow greater than
ditions.
.--l
Ma.
I
L SUFFIX
...
CERAMIC PACKAGE
CASE 620
Co)
...
0
U1
n0
TEST VOLTAGE VALUES
::J
.-+
Vdc.t.'"
VIH max
-0.890
-0.810
-0.700
VILmin
-1.890
1.850
1.825
5'
VIKAmin
-1.205
VILA INK
-1.500
VEE
-1.105
-1.475
-5.2
-1.035
-1.440
-5.2
Ma.
Unit
68
mAde
265
390
~Ade
~Adc
VIH
IMX
--------<>-...=...j
Input Pulse
t+ = t-
= 1.0 ns
Unused outputs connected to a
50-ohm resistor to ground.
Duty Cycle'" 50%
50-ohm termination to ground to
:::r:: 0.' I'F
cated in each scope channel input.
VEE" -3.2 Vdc
FIGURE 2 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2So C
veel = VCC2 '"
+2.0 Vdc
::rO., I'F
J
Vout
coa.
iT'P
All input and output cables to the
scope are aqua,! lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4' inch from TPin to input
pin and TP out to output pin.
out
Clock Input
Input Pulse
t+ " t- " 2.0 ns ± 0.2 ns
(20 to 80%1
50-ohm termination to ground 10·
cated in each scope channel input.
Unused outputs connected to a
SO-ohm resistor to ground.
XO.'I'F
VEE = -3:2 Vdc
+1.11 V
C
50%
+0.31 V
R Input
thold
+0.31 V
+1.11 V
K
S 'nput - - - - ' I
Q
Q
NOTE,
Output - - - - , , . . . ,
a Output
/
ts8'tup is the minimum time before the positive
transition of the clock pulse (C) that .information must
be present at the inputs} or K.
- - - -...... 1
thold is the minimum time after the positive transition of the clock pulse (C) that information must
remain unchanged at the inputs J or K.
3-100
MECL 10,000 series
UNIVERSAL HEXADECIMAL
COUNTER
MC10136
-The MC10136 is a high speed synchronous counter
that can count up, count down, preset, or stop count at
frequencies exceeding 100 MHz. This binary counter
is useful in high speed central processors and peripheral
controllers, minicomputen, high speed digital communications equipment and instrumentation. The flexibility of this device allows the designer to use one
SEQUENTIAL TRUTH TABLE'
INPUTS
ao
Ql
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
clock pulse is necessary to load the counter. and the
H
H
L
L
L
L
L
H
H
H
H
L
H
L
H
H
L
L
H
L
L
L
H
L
L
L
H
H
H
L
H
information present on the data inputs (DO, 01, 02.
and D3) will be entered into the counter. Carry Out
goes low on the terminal count. or when the counter
is being preset.
This device i. not designed for u ... with gated
iii"
L
H
H
L
L
L
L
L
H
L
H
H
H
L
rp
rp
H
H
rp
H
H
L
L
H
H
H
H
L
L
L
L
rp
rp
rp
L
L
L
L
S2
L
DO 01
02
rp
rp
rp
rp
Carry
H
H
H
H
03
L
H
H
H
SI
basic counter for most applications, and the synchronous count feature makes the MC10136 suitable for
either computers or instrumentatio_n._ _
ThreecontroilinoslSl,S2, and Carry In) determine
OUTPUTS
Carry Clock
02 03
Out
the operation mode of the counter. lines 51 and 52
determine one of four operations; pr:eset (program).
increment (count up), decrement (count down), or
hold 1stPI' count). Note that in the prosat mode a
clocks. Control i, via 51 and 52.
A proseal,r can b, constructed using the MC10136
in conjunction with the MC10231 which will operate
at over 200 MHz inputfroquency. A 500 MHz proseal,r
is possible using an MC1690 500 MHz 0 Flip-Flop, an
MC1670300MHz D Flip-Flop,and the MC10136 .
tP ... Don't cara .
• Truth table shows logic states assuming inputs vary in sequence
shown from top to bottom.
•• A cloek H is defined as a clock input transition from a low to a
high logic level.
I
1 0 - Cin
00
r- 14
01
f----- 15
02
rr- 3
13- C
1 2 - DO
1 1 - 01
6-
02
5 - 03
03
9 - SI
7 - S2
C out
2
FUNCTION SELECT TABLE
SI
S2
L
L
Preset (Program)
Incramant (Count Up)
Operating Mode
L
H
H
L
Decrement (Count Down)
H
H
Hold (Stop Count)
r- 4
Po; 625 mW typ/pkg (No Load)
vee1
:z
Pin
1
f eount = 150 MHz typ
VCC2= Pin 16
Vee = Pin 8
1 ..
i;-
!~
i---I
Input Pul ••
t+ .. t- .. 1.0ns
Duty Cycl. " 50%
~
All input and output cabl •• to the
scope are equal 'ength, of 50-ohm
coaxial cabl •. Wire length should
be < 1/4 inch from TP,n to input
pin and TP out to output pin.
UnuMd outputs .r. connected to
O.lJ.&FJ;
50-ohm t ... ml~tlon to ground 10CIIt.::t in .ach tcOp. channa' Input.
III 50-ohm r81iltor to ground.
+1.11 V
VEE'" -3.2 Vdc
UNIVERSAL BINARY UP/DOWN COUNTER
51 9
100-1-+----,
1200
14QO
1101
15Q1
602
3-104
202
503
303
MC10136
(continued)
APPLICATIONS INFORMATION
MC1670. Usa of the MC10231 in place of the MC1670 permits
200 MHz op.ration.
Th. MC10136 mav also be used as a programmable counter.
The configuration of Figure 3 requires no additional gates, although
To provide more than four bits of counting capability several
MCl0136 count.... may be cascadad. Th. C.rry In input ov.rrides
the clock when the counter is either in the increment mode or the
decrement mode of operation. This input allows several devices to
!be CIIICeded in a fully synchronous multistage counter as illustrated
'in Figura 1. Th. carry is advancad b.tween stages as shown with
:noexternal gating. The Carry In of thafirst device may be left open.
;The aystem clock is armmon to all devices.
maximum frequency is limited to about 50 MHz. The divider
modulus is equal to the program input plus one 1M
= N + 11. there
fore, the counter will divide by a modulus varying from 1 to 16.
A second programmable configuration is also illustrated in
Figure 4. A pulse swallowing technique is used to speed the counter
operation up to 110 MHz typically. The divider modulus for this
figuro is equal to the program input 1M = N). The minimum
modylus is 2 because of the pulse swallowing technique, and the
The various operational modes of the counter make it useful
for • wide variety of applications. If used with MECL III devices,
prelCalers with input toggle frequencies in excess of 300 MHz are
;possibl•. Figure 2 shows such a prasealer using the MC10136 and
modulus may vary from 2 to 15. This programmable configuration
requires an additional gato. such asllMC10l09 and a flip-flop such
as IIMC10131.
FIGURE 1 - 12 BIT SYNCHRONOUS COUNTER
MSB
LSB
~r;::m----~~----------
______________ ________________________--1
~
Note: S1 and S2 are set either for increment or decrement operation.
FIGURE 2 - 300 MHz PRESCALER
Logic High
MC10136
SI
S2
ar--r-------i~C
________
~--~
I "put F requencv
32
a
MC1670
3-105
MC10136(continued)
FIGURE 3 - 50 MHz PROGRAMMABLE COUNTER
Program Input
I I I I
fin
DO
C
t=
01
02
03
Cln
Cout
52
i
f out
51
fin
1 f out ""
Program I "put
+1
2 f max ~ 50 MHz Typ.
3 Divide Ratio is from 1 to 16.
FIGURE 4 - 100 MHz PROGRAMMABLE COUNTER
Program I "put
I I I I
DO
01
02
03
C
-
52
r--
51
MC10136
00
02
03
L
~
r-----"
%MC10l09
0
Q
J
YaMC10131
C
f out -
fin
::---"-"-Program I "put
2
1m.x ~ 110 MHz Typ.
3
Divide Ratio I, from 2 to 16.
3·106
°l
f out
ELECTRICAL CHARACTERISTICS
10
Cin
Each MECL 10,000 series circuit has been
13·
C
12
DO
11
01
6
02
designed to meet the de specifications
shown in the test table, after thermal equi.
librium has been established. The circuit
is in a test socket or mounted On a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Test
Procedures are shown only for selected
5
03
9
S1
inputs and outputs. Other inputs and outputs are tested in a similar manner.
.......
a...ect.i1lic
Po~r
SupplV Dr •• n Current
031-- 3
_30°C
Min
+25 0 C
M. .
Min
1m H
TyO
120
5,6,11,12
7
9,10
13
1m l
foP
.....
oCX)
All
CERAMIC PACKAGE
CASE 620
~
TE$TVOLTAGE VALUES
.T..
Cout~4
'E
Input Current
""
021--2
MCl0137l Tett Limits
"n
T.t
....
Min
...""
VEE
~,
-:JOllie
-5.2
::J
+25 I11 C
+85 I11 C
-5.2
r.t..
Unit
VIH mu
J.lAdc
5,6,11,12
~
9,10
I
Vil min
~
1,16
7,9
1,16
I. (2)
-1060
-0.890
-0.960
-0.810
-0.890
-0700
Vde
140
-1.890
-1675
-1.SSC
-1.650
-1.825
+1615
Vde
7.9
VOHA
"0
-1.080
Vde
7,9
VOLA
"<21
Vde
7,9
-1.630
-1.595
Swltchmg Times
lSO·ohm Load'
....
!Veel
VEE
eg.t ..... numb'"
VCCl
VCC2
'20 Vdc
You!
NOTE
t setup IS thE' minimum tim. before the pOsitive
tranSllton of the clock pulse (el that Information must
be present at the Input 0 or S.
thold .s the minImum tIme after The pOSItive tran·
Sitlon of the clock pu lse (el that information must
remain unchanged at the input 0 or S.
~
.'IIIV
Clock
tc.a.
a
Clock I.,~"t
50%
.
(Ol--+----o
\
+031 V
tc.a-
1+- 1-- 2.0n.
(20 10 eow,)
t
0,2n.
Output
'0·
,-----~--.1
11 V
VEE - -32Vdc
'0.31 V
50-ohm ~rmination to ground 10'
cat«:l in each scope channel input
o
or S
All input and outPut cabl . . to the
scope ar. equal length, of 50·ol'lm
coaxial cable. Wire lengtl'l thould
be
1/4 inch from TP,n to input
pin and TP out to outp ... t pin.
Unuied outpull .r. connected 10
a 50-ohm '"Itor to FO ... nd.
3·109
MC10137
(continued)
UNIVERSAL DECADE UP/DOWN COUNTER
519
527
10'0---+-+-
12 DO
1400
1101
1501
602
2 Q2
STATE DIAGRAMS
COUNT UP
3·110
503
3 03
4 Carry Out
~~__________________M
__E_C_L_l_0_,O_o_o__~_r_ie_s~
BI-QUINARY
COUNTER
MC10138
Advance In:forDl.ation
The MC10138 is a four bit counter capable of divide by two, five, or ten functions.
It is composed of four set-reset master-slave
flip-flops. Clock inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock,
allowing asynchronous Hset" or "clear". In·
dividual set and common reset inputs are
provided, as well as complementary outputs
for the first and fourth bits. True outputs
are available at all bits.
COUNTER TRUTH TABLES
BI-QUINARY
(Clock connected to C2
and Q3 connected to CII
COUNT
01
02
03
00
L
H
L
H
L
L
H
L
H
L
L
L
H
H
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
H
H
H
H
H
0
1
2
3
4
5
6
7
8
9
Po '" 370 mW typ/pkg (No Load)
1tog '" 150 MH:; typ
vee1
:c Pin 1
VCC2 :: Pin 16
Vee"" Pin 8
BCD
(Clock connected to Cl
and 00 connected to C21
COUNT
00
01
02
03
0
1
2
3
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
4
5
6
7
8
9
12 - - C1
00 - - 1 5
9- R
01 - - 1 3
7 - - C2
02 - - 4
1 1 - - 50
Q3
10 - - 51
00 - 1 4
6 - - 52
03
--2
--3
5 - 53
BLOCK DIAGRAM
50
11
00
51
15
5
L51
12
0--
C1
0'-
~
-
R
9
Reset
14
52
C2
or----
L51
-
o
R
R
1
I
I
1
Oro'r-of-
51
r - - 52
-
C2
R
3
C2
03
This i. advance information and specifications are subject to change without notice.
s..
Q~
C2
03
2
5
5
0'-
C1
-
7
00
53
4
5
ofo'r--
LB1
02
52
6
5
00',----
Clock
01
13
10
Genaral I nformation section for packaging and maximum ratings.
3-111
MC10138 (continued)
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal eqUIlibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear 'pm is maintained. Outputs
are terminated through a
5~ohm
onlv one input and qne output
ao
R
a1
13
C2
a2
4
50
OJ
10
51
00
14
6
52
03
3
9
resistor to
-2.0 volts. Test procedures are shown for
11
The other
inputs and outputs are tested In the !iame
manner
15
C1
12
L SUFFIX
CERAMIC PACKAGE
CASE 620
53
TEST VOLTAGE VALUES
(VollI)
Temp ....tur.
_30 oe
+250 C
+85 0 C
VIHmII. VILmin VIHAmini
-0.890
-1.890 -1.205
~.810
-1.850 -1.105
-0.700
-1.825 -, .035
Power Supply Dram Current
Symbol
T...
M ..
'E
1m H
12
5,6,10,11
lin L
All
LogIc "'"
Output Voltage
VOH
Logic "0"
Output Vollage
VOL
VOHA
TyO
.
Min
M"
....
Resel ell four flip-flops by ~plying pul ..
15
13
12
•2
7
15
I.
13
12
12
7
3.5
••
~
~
~
,."
15
2.'
15
I.
"2
"
IL~II~::
n
~
5.2
15
I.
VIH",.JO;
~
MH,
MH,
150
150
to pins 5,6,10,11 prior 10 applyIng tnt volt... indicated.
lEI pin 9 prior to IIPPlying test volt. indicated.
VILmin
3-112
11
11
9
9
11
11
•
12
I.
I•
13
"
I.
13
15
I.
,.
15
I.
I.
""
2
I.
1.16
MC10138 (continued)
COUNT FREQUENCY TEST CIRCUIT
"eCl· VCC2· +2.0 Vde:
CIOc:k Input ~_...J.---'Cl
Input Pul ••
t+ - t- '" 1.0 nl
Duty Cycle" SO%
01
C2
Q2
50
Cl3
51
00
Ci3
52
All Input MId output cebl.. to the
KOp • •
-.ual lengths 0' 50-ohm
cOI.i,1 c.... Wire I'nlth ....ould
be
1/4 inch from TPin to Input
00
R
5C).ohm .. ,min.tion to ,round located In leeh Kope channel Inp",t.
53
r.
r.
pin MId TP out to output pin:
Unu.d output•• connected to
• 5O-ohm , . . .tor to .ound.
VEe" .3.2 Vde:
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C
V,n
"CC1" VCC2" +2 0 Vde
"OUI
+1.11V
Cl or C2
Cl
QO
R
01
C2
Q2
50-ohm grmination to ,round 10CIted In ..,h KOpe enannl' input.
aOor 03
Output
50
Cl3
51
00
00 or 0.3
52
Ci3
Output
Clock Input
+O.31V
53
All input end output cabl .. to thl
.cope .r. lIqual langtl,. of 50·ot"lm
coaxi,1 cabl..
Wire length should
be
1/4 Inch from TP in to input
pin and TP out to output pin.
Un ... 1M! outputs .... oonnect~ to
• 5O-ohm , • •tor to .ound.
veE" -32 Vdc
COUNTER STATE DIAGRAM - POSITIVE LOGIC
00 c:onnocted to C2
Clock connected to C2
3·113
MECL 10,000 series
FOUR-BIT UNIVERSAL
SHIFT REGISTER
MC10141
The Me 10141 is a four-bit universal shift
register which performs shift le~t, or shift right,
serial/parallel in, and serial/parallel out operations with no external gating. Inputs SI and 52
control the four possible operations of the
register without external gating of the clock.
The flip-flops shift information on the positive
edge of the clock. The four operations are stop
shift, shift left, shift right, and parallel entry of
data. The other six inputs are all data type inputs; four for parallel entry data, and one for
shifting in from the left (OL) and one for shifting in from the right (DR). All four outputs
.
are car1ble of driving 50 ohm lines.
When the register is used for serial output
only, the unused emitter follower outputs can
be left open.
13
OL
4
C
12
DO
11
01
9
02
6
03
10
51
52
00
14
01
15
02
2
03
3
veel = Pin 1
VCC2:: Pin 16
VEE = Pin 8
DR
5---...J
TRUTH TABLE
SELECT
rs-;-'S2
OUTPUTS
OPERATING MODE
00n+1 Q1n+1
Q2n+1 Q3n +1
D.
P.r.II •• Entry
Shift Right·
0'"
Shift Left·
0'"
00"
Stop Shift
·Outputs .. eXI't
02"
00"
0'"
.tt., putM-.pCle.".' "e" input With
0'"
0."
rroput condition.
Po
= 425
mW tvp/pkg (No Load)
fShift = 200 MHz typ
. . .hown. (Put .. - Poaltiv. tran.ition of clock Input).
LOGIC DIAGRAM
0'
5'
52
OR~----~+----L~
OJ
02
See General Information section for packaging.
3-114
Q1
00
...."...., .... " ....,.
............,.
~-
---'-"-~-
13
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 _i .. circuit lin been
designed 'to meet the de specifications
shown in the tost tobie, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
Outputs are tenn inated through a 5O-ohm
resistor to -2.0 volts. Test procedures are
shown for only selected inputs and outputs.
Other inputs and outputs tested in the
same manner.
....
I
C11
I Logic "0"
Logic "1"
Output Voltage
12
DO
11
01
9
D2
10
00
14
01
15
02
SI
7 - 52
03 f - - 3
MC10141L Test Limits
+25 De
_lODC
I
Max
Min
-
I
-
-
Typ
82
I,n H
I
5
I
I
I
I
+BSDe
Max
102
Min
Max
Unit
mAdc
220
-
.!JAdc
0.5
-
-
-0.890
-0.960
-
-0,810
-0,890
-0,700
-1.675
-1.850
-
-1,650
-1.825
-1.615
-
-0.980
-
-0.910
-
-1.655
-
-
-1.630
-
lIn L
12
-
-
VOH
3
-1,060
VOL
3
-1.890
3
-1.080
n
0
....
::J
220
245
265
I I I I
I
+ssoe -0.700
-1.440 -5.2
-1.825
-1.035
TEST VOLTAGE APPLIED TO PINS
LISTED BELOW:
-
-
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
(Volts)
@Test
Temperature VIH mu: VILmin VIHAmi VILAmax VEE
_lODe -0.890
-1.500 -5.2
-1.890
-1.205
+25 De -0.810
-1.850
-1.105
-1.475 -5.2
J
Min
3:
....
....C
....
(")
TEST VOL TAGE VALUES
DR
8
Ie
I
Input Current
~
1SymbDlj U~::
C
D3
Pin
Characteristic
Power-Supply DraIn Current
-
OL
4
~
-
VIHmu VILmin VIHAmi VILAmax Vee
8
5
-
PI
P2
P3
-
-
-
8
8
-
-
IVee)
Gnd
1.16
1,16
~
4.5.6.7.9.
10.11,13
12
-
Vdc
6
-
-
-
8
4
-
-
1.16
Vdc
-
-
-
-
8
4
-
-
1.16
Vdc
-
-
6
-
8
4
1.16
t
@
@
7
~-
-
t
t
-
-
6
-
-
6
7
4
-
.!JAdc
t
-
-
1,16
Output Voltage
Logic "'"
Threshold Voltage
V8)A
I
Logic "0"
Threshold Voltage
3
V(bA
Sw;tch;ng T;mes 150 n Loadll
Propagation Delay
t4+3+
Setup Time (tsetupl
t'2+4+
t,2-4+
t10+4+
t10-4+
Hold Time (thold)
I t4+12+
t4+12t4+10+
t4+10R;se T;me 120% to 80%)
t3+
Fall TIme (20% to 80%1
t3ShIft Frequency
fShift
I
Pl
VIH
~VIL
t t
t
I
t t
P2
-
3
I.
j
3
3
-
0,9
3,9
-
-
-
1,0
1.0
150
3.4
3,'
VIHA
~VIL
-
-
1.0
2.5
2.5
5,0
5.0
~
t
2.9
3.8
U
u!
200
33
-
-1.595
Vdc
~
t
-
4.2
1.2
ns
6
6
0
-
-
-
6
7
-
8
~
•
-
4
-
-
••
:~
1.1
150
!
P3
!
11
150
!
VILA
JLVIL
36
36
-
!
-
-
-
LI ~
I .."'.-,"-_._"
'".~.,
2 See switching tIme test cIrcuIt for test procedures.
3 See shift frequency test circu~t for test procedures.
4 Reset to zero before performing test
5 Reset to one before performing test.
•-
• -•
-
1.5
1.5
1,0
-
-
~
1,16
t
~
1.16
:i"
c:
~
ELECTR ICAl CHARACTER ISTICS
13
Each MECL 10,000 series circuit has been
OL
designed to meet the de specifications
shown in the test table, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
4
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
Outputs are tenn inated through a 5O-ohm
resistor to -2.0 volts. Test procedures are
DO
11
01
9
02
6
03
-
14
00
C
12
15
01
02
2
1 0 - SI
shown for only selected inputs and outputs.
03
7 - S2
Other inputs and outputs tested in the
DR
same manner.
r-- 3
...&
MCl0141P Tost Limits
Ch.r.ct_istie
Power Supply Drain Current
I
Input Current
W
.:...
en
I Symbol
Logic "1"
Output Voltage
I
Logic "0"
Output Voltage
logic "1"
Threshold Voltage
Ie
Tnt
8
lIn H
5
I
P~VIH
VIL
M;n
I
- I
Ty.
82
I
Max
102
Min
Max
Unit
mAdc
220
220
245
265
-
JJAdc
5
~
6
7
4
4.5.6,7,9,
10,11,13
-
-
-
12
.-
-
-
-
0.5
-
-
-
VOH
3
-1.060
-0.890
-0.960
-
-0.810
-0.890
-0.700
Vde
6
VOL
3
-1.890
-1.675
-1.850
-
-1.650
-1.825
-1.615
Vde
-
.-
-
VOHA
3
1.080
-
-0.910
6
@)
@)
-
VThA
t4+10+
t4+10-
t3+
t3fShift
I
•t
3
3
14
1
3
3
-
-
t
-
-
-
-
-
-0.980
-
-
-
t •
-1.655
-
-
-
P2~VIHA
VIL
-
-
-
~
-
-
1.0
2.5
2.5
5.0
5.0
2.9
-
3.8
6
-
Vde
t t
-
-
CD
~s
-
-
6
-
~-
-
-
-
6
7
-
-
-
-,
-
-
-
P3
8
4
8
4
-
-
4
4
4
-
-
4
8
t
1Vee l
Gnd
1.16
8
~
7
P2
t
8
6
t
-1.595
-
PI
-
8
-
Vde
-
-1.630
jJ.Adc
-
t
-
ctI
a.
-1440 1 -52
VIHmax VILmin VIHAmu VILAmax Vee
8
12
t.t+12-
1
I
Max
lin L
Sw;'eh;ng T;mes (50 n Loadll
Propagation Delay
t4+3+
Setup Time Itsetup)
112+4+
t12-4+
t10+4+
t10-4+
Hold Time Ithold)
I t4+12+
R;s. T;me 120% to 80%1
Fall Time 120% to 80%)
ShIft Frequency
Min ~
I
:i'
c:
TEST VOLTAGE APPLIED TO PINS
LISTED BELOW:
+8So C
+2Soc
-1.035
-
(!)
Logic "0"
Threshold Voltage
_lODe
n0
:::J
....
TEST VOL TAGE VALUES
+8Soc -0.700 1-18251
Pin
0
...&
,JiIo
IVolts)
@I Test
Temperature IVIH max Vll min VIHAminVllAmax VeE
_lODe -0890
-1500
-52
-1.890
-1.205
-1.475
+2S o C -0.810
-5.2
-1850~ -1.105
-.J
Und.
3:
n
...&
P SUFFIX
PLASTIC PACKAGE
CASE 648
-
1,16
-
-
1.16
4
-
-
-
4
-
+
1,16
-
-
1,16
1,16
4
4
,3.2V
8
t
1,16
.,
+
~
1,16
1.5
1.5
1.0
1.0
1.1
1.1
150
I
17
1.7
200
I
33
-
I
=
I
P3JLVILA
VIL
-
I
LI m............_." _.,...
~,.
,,-"
2 See sw'teh;ng t,me test e;'eu,t fo, test pmeedu,",.
3 See shih frequency test .cirCUit for test procedures.
4 Reset to zero befort.perfQrmina.test. !
5 Reset to one before ·per1ori'lN~~:--:.
':~ "
MC10141 (continued)
~
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C
VCC1 • VCC2
V out
+2.0 Vdc
251' F
Input Pulse
t+ "" t-
l
Coax
lO.1I'F
= 2.0 ±O.2 ns
(20 to 80%)
Input
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
Pulse Generator
pin end TP out to output pin.
f'
50-ohm termination to ground located in each scope channel input.
Clock
I o.
1 I-l F
VEE· -3.2 Vdc
Q Output
MC10102
SHIFT FREQUENCY TEST CIRCUIT
VCC1 ~ VCC2
V out
+2.0 Vdc
lO.1I'F
Coax
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 114 inch from TP in to input
pin and TP out to output pin.
Input
Pulse Generator
Test Procedures:
1. Set 01,02,03 = +0.31 Vdc (Logic L)
DO:: +1.11 Vdc (Logic H)
50..ohm termination to ground located in each scope channel input.
2. Apply Clock pulse
n:~:~
3. Maintain Clock Low.
Set Sl = +0.31 Vdc (Logic U
52 = +1.11 Vdc (Loyic H)
4. Test Shift Frequency
I
O. 1 I'F
Vee = -32 Vdc
3·117
to set
ao
high.
'\
QUAD LATCH
M Eel 10,000 series
'--------------'
MC10153
Advance InforIllation
TRUTH TABLE
G c 0
H
°n+1
L
L
.e:
13
14
TEST VOLTAGE VALUES
15
(Vol..)
OT...
T emp....tur.
-30Ge
+250 C
+850 C
Characteristic
Power Supply Drain
W
.:..
Symbol
Pin
Und.r
T ...
IE
8
linH
3
4
MC10160P T•• Limits
-3O"c
Min
Mo.
+25oC
Min
Typ
62
Min
Ma.
VILmin
-1.890
VIHAmin
-1.205
VI LAm. .
-1.500
-0.810
-0.700
-1.850
-1.825
-1.105
-1.035
-1.475
-1.440
T VeE
-5.2
1 -5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+85·C
Ma.
78
VIHma"
-0.890
Unit
VIHmelt
mAde
4.5,9,10,13,14
VILmin
VIHAmin
VI LAm. .
VEE
(Vee)
GNI
8
1,16
8
8
1,16
1.16
1,16
Current
II npu. Curren'
I\J
W
265
220
0.5
linL
Logic "1"
Output Voltage
VOH
logic "0"
Output Voltage
VOL
Logic "'"
Threshold Voltage
VOHA
Logic "0"
Threshold Voltage
VOLA
/JAde
/JAde
IJAdc
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
4,5.6,7,9,10,
11,12,13,14,15
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
3.4,5,6,7,9,10,1
11,12,13,14.15
Vdc
4,5,6,7,9,10,11,1
12,13,14,15
Vdc
3,5,6,7,9,10,111
12,13,14,15
-1.080
-0.980
-0.910
-1.655
-1.630
-1.595
1,16
3
8
1.16
8
1,16
8
1,16
SWitching Times
(SO 0 Load)
Propagation Oelay
+1.11 V
t3+2+
t3+2-
'3-2t3-2+
t4+2+
'4+2'4-2'4-2+
2.0
5.0
7.5
Pul.ln
+2.0 V
3
1,16
4
j j j
Rise Time
(20% '080%)
'2+
1.1
2.0
3.3
Fall Time
(20% '080%)
'2_
1.1
2.0
3.3
4
+
4
+
,
3
Me1 0160 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SOC
:1.
Vin
Input Pulse
Generator
VCC1 ; VCC2
+2.0 Vdc
V out
25~F~ltO.1~F
r----
Coax
- - --.,
I
I
o----
.,
'25"C
Min
T,•
....7.
Unit
Mu
mAd<
220
-1.<160
-1.060
-1.890
-4.890
-4.890
-1.675
,Ad<
,Ad<
1..
1.0
1.0
-1.850
-4.980
-0.980
-1.080
-1.080
,.
-0.810
-0.810
-1.650
-0.960
-0.960
-1.655
6.2
6.2
3.3
3.3
-0.890
-4.890
-1.825
-0.910
-0.910
-1.630
,1...•
VIHAmin
VILAm..
-1.890
-1.850
-1.825
-1.205
-1.500
-5.2
-1.105
-',475
-5.2
-1.035
-1.440
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
.85"C
Mm
0.'
'3
'3
'3
13
t14_13+
Ri_Time 120% to 80%)
M'.
,.,.
linH
lin
....
-JO"c
u....
CharllC.,lstie
-0.100
-0.100
Vd<
Vd<
-1.615
Vdo
VIHm_
2,1,9,14,15
,.
,.,.
VIL min
1.1
1.1
2.0
6.0
6.0
3.3
3.3
1..
1..
1.1
1.1
2
,.,.
2
Vd<
~
Pul. Out
'3
~
V out
Coax
PROPAGA TlON DE LAY
Input
Pulse
Generator
Input Pulse
t+ = t- = 2.0 ±. 0.2 ns
(20 to 80%1
V out
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin
Unused outputs connected to
a 50-ohm resistor to ground.
VEE
0::
-3.2 Vdc
3-126
1Vccl
0 ...
l,1e
1,16
l,1e
l,t6
1,18
1,18
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2S0C
Coax
VEE
1,18
1,16
,.
6.'
6.'
3.'
3.'
VILAm..
,.
Vd<
Vd<
-1.595
VIHArnin
Pul.ln
'.0
'.0
2.0
VEE
VILmin
-12V
S
~
+2.0 V
',18
MC10161 (continued)
ELECTRICAL CHARACTERISTICS
Elen MECL 10,000 series clfe .... ' has been
cfntgned to meet the de specificatIons
-.own in the test table, after thermal eqUIt;briurn hh been established. The CirCUit '5
in • test socket or mounted on a pnnted
circuit bo.d and tranwerse air flow greater
~... 500 line.. fpm IS maintained. Outputs
in tlll'minlled through a 50-ohm resistor to
·2.0 volt •. Tnt proc:edures are shown for
anly one input/outpUt combination. Other
QClmbiMitions
te.ted according to the
avrh Ilbl •.
If.
-
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Voltsl
n ...
Temperatu,.
-30"<:
.,.,,<:
--
u_P'.
Sy_
...... Supply Dr. Current
l ....tCunwnt
_T_
Ou1pUtVoitaIgt
laIk "a' OutpUt Vo''''
LeIII:","
"
'inH
I.
"
"OH
13
13
VOL
13
VOHA
13
13
VOLA
13
"T"tNWIoIdVol....
"'''0''' Th ..... otd Vol . . .
(IDOL_'
~ionDel..,
I
-30"<:
Min
M.
8
linL
LAllie"'"
T. .
..."<:
MC'O'6'P THI Limits
R_ Time (~to 80%)
'13+
13
13
13
F.'TlrM(~toamc.,
'13-
13
114+131'4-13-t
-1.060
-1.060
-1.890
-1.080
-1.080
Min
•..
-".890
-0.890
-1.675
.,
• .."<:
Min
M.
'25"<:
TyO
M.
7.
220
-0.810
-0.810
-1.650
-1.655
-0.890
-0.890
-1.825
-0.910
-0.910
-1.630
I.,
1.1
1.1
VIHAmin
-0.890
-1.890
-1.850
-1825
-1.206
-'.500
"EE
-5.2
-1.105
-1.035
-1.475
-5.2
-1.440
-5.2
-0.8'0
·0,700
TEST VOLTAGE APPLIED TO PINS LISTED BELOW;
Unn
mAd<
,Ad<
-".560
-0.980
I.'
VILmin
V'H",.
..•
'.0
2.0
..0
•.0
3.3
2.0
3.3
-0.700
-0.700
"d<
"d<
I.
-1.615
"d<
"
"d<
"d<
-1.595
"d<
~
Val min
VIHA min
VILA max
VEE
2
(Veel
Gnd
1,16
2,7.9,14,15
14
,Ad<
-".560
-0.960
-1.850
VILA",..
V'Hm ..
1.16
1,16
1,16
1,16
"
1,16
1,16
1,16
1,16
2
"
"
Pul. In
Pul. Oul
-3.2 V
+2.0 V
14
13
8
1.16
~
A complete mux/demux operation on 16 bits for data
distribution is illustrated in Figure 1. This system, using
the MC10136 control counters, has the capability of incrementing, decrementing or holding data channels. When
both SO and Sf are low, the index counters reset, thus
initializing both the mux and demux units. Thefour binary
outputs of the counter are buffered by the MC10101s to
send twisted-pair select data to the multiplexer/demultiplexer units.
APPLICATION INFORMATION
The Mel01Bl is a true parallel decoder. No series
gating is used internally, eliminating unequal delay times
found in other decoders. This design provides the identical
4 ns delay from any address or enable input to any
output.
3-127
s:
(")
....
o....
FIGURE 1 - HIGH SPEED 16-BIT MULTIPLEXER/DEMULTIPLEXER
....
Control Selection
MC10101
0)
MC10115
8::J
....
::J
SO
SI
CR
A
15141312111098
7· 6
5 4
3
2
1 0
C
0
El
C
El
MC10164
B
A
DO
C
MC10164
B
A
DO
C;ol
....
I\J
CD
so
SO
SI
SI
CR
A
MC10136
B
C
Cl>
Q.
MC10136
B
c:
0
CR
El
C
EO
MC10161
El
C
B
B
A
A
1514131211109 B
EO
MC10161
765 4
3210
MECL 10,000 series
BINARY TO 1-8 DECODER
(HIGHI
MC10162
The MC10162 is designed to convert three
lines of input data to a one-of-eight output_ The
selected output will be high while all other outputs are low. The enable inputs, when either
or both are high, force all outputs low.
POSITIVE LOGIC
A 7
• 9
Po:::: 315 nl typ/pkg (No Load)
tpd '" 4.0 nl typ
C 14
vee1
= Pin 1
VCC2=Pln16
Vee E: PinS
TRUTH TABLE
INPUTS
OUTPUTS
Eo
E1
C
B
A
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
'i>
'i>
H
'i>
'i>
'i>
'i>
'i>
'i>
00 01
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Q2
03 04
os
06 07
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
'" - Don t Car•
. . . .Gen..1 Information section for peck-Uing.
3-129
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
MC10162(continued)
ELECTRICAL CHARACTERISTICS
Each MEeL 10,000 series circuit hal been
designed to I'TIHt the de specifications
shown in lne test table, after tMrmai equilibrium has been established. The eita.!!t is
in a test socket or mounted on a printed
Circuit bo.d and tran .. erse ai, flow greater
than 500 linear fpm is meinlained. Outputs
are terminated through 8 SG-ohm resistor to
- 2.0 volU. Test procedures .reshown for
L SUFFIX
_liv input/O\ltput combination. Other
combination, .... t-st~ Kcordinll to the
truth t8ble.
CERAMIC PACKAGE
CASE 620
~"Q'
TEST VOl.TAGE VALUES
~"Q'
IVahsl
@lIS!
VIHAmin
VILA milt
VEE
-lOoe
-0.890
-1.890
-1205
-1500
-5.2
+25 o C
-0810
-1.850
-1105
-1475
-5.2
+8SoC
-0700
-1825
-1035
-1440
-5.2
Temperltur.
VIHm..:
VILmln
MC10162L Tm Limilt
P'"
C ....
'.ct....
U....
ItIC
Symbol
Power Supply Or,lIo Current
T...
....
+2SoC
-lOoe
M,n
M,"
Input Current
T,p
ImH
O.
l,nL
log.c·"
M,n
1Veel
UnIt
M••
76
mAd.:
220
"Ade
VIHm. .
VIHAmin
VILAm ••
VEE
Gnd
8
1.16
1.16
1,16
13
·1060
-<7890
-0960
-0810
-0890
-0700
Vd,
14
VOL
13
13
., 890
-1890
-1675
-1675
-1850
., 650
-1650
1825
-1815
-1615
-1615
Vdc
2
15
VOHA
13
-1080
VOLA
13
13
Logie "0"
Output VOltage
VILmm
"Ade
VO"
Output Voltage
Log'c","
....
61
'E
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+SSoC
·1850
-0980
1,16
1,16
1,16
·0910
14
1,16
2
15
1.16
Threshold VOltage
LogIC "0"
Threshold Voltage
.1655
.1.655
-1630
-1595
-1595
., 630
V",
1,16
SWItChIng T ,mes
/SO-ohm loadl
13
13
I..
Pulse I"
PulMOut
13
-J.2V
+2DV
62
62
I.'
I.'
40
4.0
6.0
6.0
1.5
15
64
6.4
n,
14
15
Rise TIme
(20,*, 10 80%1
13
1.0
33
1.1
2.0
3.3
11
3.'
Fall TIme
(20~ to 80'1101
13
1.0
33
1.1
2.0
3.3
1.1
3.'
l
1 l l l
Propagllt.on Delav
ft4")+
'14-13-
1,16
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
VCC1 • VCC2
+2.0 Vdc
Coax
Input
~,,±
!t,,",
Vout
r---------..,I
I
,...
PROPAGATION DELAY
I
Pulse
~
I
Generator
Input Put . .
:c: t- = 2.0
t+
- ----+0.31 V
t++
t--
±. 0.2 ns
---......"
(20 to 80%)
V out
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
+1.11V
50%
Unused outputs connected to
a 50·ohm resistor to ground.
VEE"" -3.2 Vdc
3·130
80%
MC10162 (continued)
I!t.ECTRICAL CHARACTERISTICS
Eah MECL 10,000 serlu ClfCUlt has been
dftitned to meet the de specifications
~n in the test table, after thermal eQui·
librh.lm hn been established. The circuit is
-
in • test KlCket or mounted on II prmted
circuit bo.d and tr .... "'erw alf flow greater
thlnftOOline.fpmismaintained. Outputs
. . terminated through II 50-ohm resistor to
-2.0 vo'tI. Tnt proceduresllr. shown for
--.
only input/output combination.
Other
combiMtions ere t"tecl according to the
P SUFFIX
PLASTIC PACKAGE
CASE 648
TEST VOLTAGE VALUES
(Volu)
, .. -----r=r=
.-
Power SuPJlly Or.in Current
V,,
-1500
-5.2
-1105
-, 035
-1.475
-1440
-5.2
-52
I---,----,---,-----,------j
M~
8
"
linH
.Input Current
VILA me_
-'205
TEST VOLTAGE APf'lIED TO PINS LISTED BELOW:
Pin
Symbol
VIHAmin
-1890
-1850
-1.825
MCl0162P Tillt limitt
u ....
et.ad.iR,C
VILmm
M..
61
76
mAde
220
J'Ade
1,16
J'Adc
1,16
14
LOIIIIC "'"
VOH
13
-1.060
-
MC10136
) x=;( I
MC10101
76643210
o
rrar
I
EO
MC10162
1514131211 10 9 8
I
iBr
EO
MC10162
76543210
MECL 10,000 series
ERROR DETECTIONCORRECTION CIRCUIT
MC10163 • MC10193
Advance
In~orDl.ation
The MC10163 and the MC10193 are error detection
and correction circuits. They are building blocks designed
for use with memory systems. They offer economy in the
design of error detection/correction subsystems for mainframe and add-on memory systems. For example, using
eight MC10163's together with eight 12-bit parity checkers (MC10160), single-bit error detection/correction and
double-bit error detection can be done on a word of
64-bit length. Only eight check bits (80-87) need be
added to the word. A useful feature of this building block
is that the MC10193 option generates the parity of all
inputs to the block. Thus, if the MCl 0193 is applied in a
byte sequence, individual byte parity is automatically
available.
MCl0163 LOGIC DIAGRAM
MC10193 LOGIC DIAGRAM
81 7
82 II
81 7
82 6
16POA
15 P4
8412
8711
8412
8711
3 P3
86 4
86 6
3 P3
85 4
86 5
2 P5
2 P08
80 II
8310
80 9
8310
}-----14PI
r----14
}-----'-13P2
}-----13P2
IBM CODE
PO A
P08
PI
P2
P3
MOTOROLA CODE
= 81. 82. 84. 87
PI - 81. 83. 85. 87
P2 = 82. 83. 86. 87
P3 - 84. 85. 86. 87
P4- 81. 82. 84. 87
P5 = 8yt. (80.1.2.3.4.5.6.7)
- 80. 83. 85. 86
= 81. 83. 85. 87
= 82. 83. 86. 87
= 84. 85. 86. 87
VCCI = Pin 1
VCC2 - Pin 16
VEE - Pin 8
VCCI - Pin 1
VCC2 = Pin 16
VEE
= Pin 8
Po = 520 mW typ/pkg (No Load)
Po = 520 mW typ/pklj (No Load)
'Pd = 5.0 ns typ
tpd
Thill. advance information and specifications are subject to change without notice.
S- General Information section for packaging and maximum rating•.
3-133.
E:
7.5
n.
typ (pin 7 to pin 2)
PI
ELECTRICAL CHARACTERISTICS
-
15 PO",
flow greater than 500 linear fpm is main-
2 POe
I II I Ie
:~,~
tained. Outputs are terminated through
a 50-0hm r.sistor to -2.0 volts. Test pro-
s:("')
....
o
....
en
~
817
Each MECL 10,000 .ries circuit has been
designed to meet the de specifications
shown in the test table, after thermal
equilibrium has been established. The circuit is in a test mcket or mounted on a
printed circuit board and transverse air
to)
s:•
L SUFFIX
I
....
o
....
CO
("')
CERAMIC PACKAGE
CASE 620
cedures are shown only for selected inputs
and outputs. Other inputs and outputs are
tested in a similar manner.
to)
n
~...
@T.st
Temperatur.
_30 G e
'rl
~
w
~
CharleteristK:
Power Supply Drain Current
Input Current
Symbol
'E
linH
Min
Mo.
Logic "0" Output Voltage
-
-
2
3
13
14
VOL
~
Logic "0" Threshold Voltage
Switching Times
150 n Loadl
Propagation Delay
VOHA
VOLA
0.5
VOH
1.060
+
-1.890
+
2
3
13
14
-1.080
2
3
13
14
-
t7+15+
t4+14+
15
14
Rise Time (20% to 80%)
t15+
15
Fall Time (20% to 80%)
t15-
15
Typ
-
8
4.6.10
5.7.9.11.12
3
13
14
Logic "'" Threshold Voltage
Min
-Individually telt each input, apply VILmin to pin under test.
+
-
-0.890
+
-1.675
~
-
-1.655
+
-
-
0.960
~
-1.850
-1.825
~
-0.980
+
-
5.0
5.0
2.0
2.0
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW,
VIHmex
-
-
mAde
-
jJAde
jJAdc
4,6,10
5,7,9,11,12
jJAde
-
Vdc
4
4
11
11
+
-
-
-0.890
-0.700
+
-1.825
+
-
-0.910
-
~
-1.630
-
+
-
-
20
-5.2
-1.850
-0.700
125
+
-5.2
-1.440
-0.810
+8So C
Unit
-1.650
-1.475
-1.035
+25 oC
Mo.
-
-1.105
-1.205
Min
0.810
-
::J
C
R>
-5.2
-1.890
Ma.
220
265
VEE
-1.500
VILmin VIHAmin VILAmax
-0.890
+ssoc
+2SoC
linL
Logic "'" Output Voltage
VIHmax
MC10163L Test Limits
_lOGe
::J
....
(Volts)
13P2
Pin
Under
T ...
o
TEST VOLTAGE VALUES
+
-1.615
+
-
-
-1.595
+
Vdc
~
Vdc
+
Vdc
+
+
-
n.
-
~
-
-
-
IVcc l
Gnd
-
-
8
1.16
1.16
1.16
-
-
-
8
8
-
8
1,16
8
1.16
-
-
-
4
11
11
11
-
-
5
11
5
4
-
-
5
11
5
4
Pulse In Pul.Out
+1.11 V
-
VEE
VILmin VIHAmin VILAmax
-
7
4
15
14
-
7
15
7
15
+
+
8
1,16
+
1.16
8
+
8
+
+
~
1.16
+
-3.2 V
+2.0 V
8
1,'6
~
~
ELECTRICAL CHARACTERISTICS
r:C
:;; r
Each MECL to,ooo .rias circuit has been
designed to ineet the de specifications
shown in the test table. after thermal
equilibrium has been established. The cir·
-
.. ~ I,I I! )C
cuit is in a test socket or mounted on a
printed circuit board and transverse air
3:
flow greater than 500 linear fpm is main-
(')
~
o
en
~
w
•
s:
(')
L SUFFIX
tained. Outputs are terminated through
. a 5O-ohm resistor to -2.0 volts. Test procedures are shown only for selected inputs
and outputs. Other inputs and outputs are
tested in a similar manner.
CERAMIC PACKAGE
CASE 620
~
o
~
c.
ctJ
.....
W
.....,
FIGURE 2 - 370/146 PATTERN GENERATION
co = POAO
P080
P11
POAI
P081
Cl = Pl0
P12
P13
POA2
P14
P082
PIS
POA3
P16
P083
P17
C2= P20
P21
P22
P23
P24
P25
P26
P27
8(32)
8(32)
C4 = P30
P31
P32
P33
P34
P35
P36
P37
C8 = POAI
P081
POA3
P083
POA5
P085
POA7
P087
C16 = POA2
POA2
POA3
POA6
P086
POA7
P087
C32= POA4
P0s4
POA5
P0s3
P085 .
POA6
P086
POA7
P087
8(0)
CT= POAO
P081
P082
POA3
POA4
P085
P086
POA7
8(0)
Where for PNM: N = MC10163 OUtpUl
M = 8yt. Number
MC10163 • MC10193 (continued)
MC10193 APPLICATIONS INFORMATION
;n&;~~~I~m
0
ill
18
.,
is
ill
- - - E 8 D
[>---E81
56 S6 -
~.
EB2
~
E83
S7§ij ~
55
56 _
.57§ij ~
SI- D}
EC
52 - - - EC1
53---EC2
I
55 ---ECD
56 - - - EC1 (Byte. 4.7
57---EC2,
$1[ > - - - EB4
52 53
54
$152 S3 -
54
[ > - - - EB5
$1 52 53
- - [ > - - - EB6
54
51-
Byte. 0·3
~
S2 5354 ~E87
3·139
MC10163 • MC10193 (continued)
FIGURE 6 - SYNDROME AND CHECK BIT GENERATOR. M2 PATTERN
Bit
p
1
2
3
10
20
30
:
6
7
40
50
'IJ
{IJ"
,{ "IJ
...o{
"1" for Check Bits
"0" for Syndromes
10
12
54
56
664
21
31
20
22
54
57
·LIJ
rIJ
,{ ~IJ
5
55
S2
MC10160
665
30
32
54
57
31
33
56
S3
MC10160
MC10193
{~IJ
47
21
23
55
MC10193::
12
22
32
42
52
23
SI
MC10160
MC10193
1
15
11
13
55
866
13
23
33
43
53
40
42
55
57
41
43
56
S4
MC10160
667
14
24
34
44
54
14
16
50
52
15
17
51
MC10160
968
15
25
35
55
24
26
50
53
25
27
51
MC10193::
56
MC10160
869
16
26
36
46
56
34
36
50
53
35
37
52
MC1Q193
57
MC10160
870
'LIJ
17
27
37
47
57
44
46
51
53
871
3-140
45 '
47
52
58
MC10160
'\
8-LlNE MULTIPLEXER
MECL 10,000 series
\.--------------'
MC10164
The MC10164 is a high speed, low power
eight-channel data selector which routes data
present at one-ot-eight inputs to the output_
The data is routed eccording to the three bit
code present on the address inputs_ An enable
input is provided tor easy bit expansion_
TRUTH TABLE
--ENABLE
ADDRESS INPUTS
C
B
A
Z
L
L
H
H
L
H
L
H
XI
X2
L
L
L
L
L
L
L
.L
H
H
H
H
L
L
H
H
L
H
L
H
X6
X7
H
q,
q,
q,
L
L
L
i.
L
xo
X3
X4
X5
Po - 310 mW typ/pkg (No Load)
tpd - 3.0 nl typ (Oete to output)
t/J "" Don't Care
.-A
)
7
.---B
2
9
C 10
~
Jr-
15 Z
xo
6
Xl
5
X2
4
)
~
~T
T
R
r
R
X3
3
y
X4'1
~:;
X512
>--
R
X613
X714
--===4
T
Y
vee1 = Pin 1
VCC2
't.
r..~
= Pin
16
PinS
Vee =
_____________________________________________________________________________________
s .. Gen.r.1
--J
Information section for packaging.
3-141
ElECTR ICAl CHARACTER ISTICS
s:(')
Each MECL 10,000 series circuit has been
designed to meet thedcspecifications shown
in the test table, after thermal equilibrium
has been established in an ambient temperature of 2SoC, while the circuit is in a test
socket or mounted on a printed circu it
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
A
1
•
9
...o
...
~
o
C 10
o
~
111111
E"n.bi02
only one input. or for one set of input conditions. Other inputs tested in the same
manner.
t]§
)(5 12
)(6 13
)(7 14
~
~
I\)
Charut .. istic
Power SupplV Drain Current
I nput Current
Symbol
Pin
Under
T...
IE
8
lin H
2
4
lin L
-30"c
Min
Mo.
-
Min
Typ
-
-
Mo.
75
265
~.890
~.810
+85oC
~.700
VILmin
-1.890
-1.850
-1.825
VEE
-5.2
-5.2
-1.440
-5.2
Mo.
Unit
VIH ~ax
VILmin
8
IVcCI
Gnd
1,16
-
8
1,16
-
-
8
8
1,16
1,16
V'HAmin
VILA max
mAde
-
-
,.Ade
2
,.Ade
-
-
4
VEE
~.810
~.890
~.700
Vde
4,9
-1.675
-1.850
-
-1.650
-1.825
-1.615
Vde
9
-
-
-
8
1,16
-1.080
-
~.980
-
-
~.910
-
Vde
4,9
-
8
1,16
-1.655
-
-
-1.630
-
-1.595
Vde
9
-
-
2
-
2
8
1,16
Pulse Out
-3.2 V
+2.0 V
8
1,16
-1.060
~.890
Logic "0"
Output Voltage
VOL
15
-1.890
Logic "1"
Thres,",old Voltage
Logic "0"
Threshold Va Itage
VOHA
15
VOLA
15
Pul .. ln
+1.11 V
,-
VILA milK
-1.500
-1.475
~.960
15
t4+15+
'4-1&t7+15+
'7-15t2+15+
t2-15+
t+
VIHA min
-1.205
-1.105
-1.035
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
+l5oC
Min
VIH max
-30"c
+:ZSOC
-
VOH
Rise Time
120%'080%1
Fall Time
(2011 to 80%1
(Volts)
tilT ...
T emper.ture
0.5
Logic "1"
Output Voltage
Switching Times
150 n Loadl
Propagation Delav
<»
a.
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
MC10164L Tnt Limits
+25oC
60
-
::J
c::
L SUFFIX
t fTTT=L-.-
)(4 11
cp
::J
....
-
15 Z
-2.0 volts. Test procedures are shown for
15
15
15
15
15
15
1.5
1.5
1.9
1.9
0.9
0.9
4.7
4.7
6.3
6.3
3.3
3.3
1.5
1.5
2.0
2.0
1.0
1.0
15
0.9
3.3
1.1
15
0.9
3.3
1.1
3.0
3.0
4.0
4.0
2.0
~
4.5
4.5
6.0
6.0
2.9
2.9
1.6
1.6
2.2
2.2
1.0
1.0
3.3
1.2
4.8
4.8
6.5
6.5
3.1
3.1
3.6
3.3
1.2
3.6
ns
j
9
9
5
5
7,5
7,5
9
9
-
-
4
4
7
7
2
2
-
4
-
4
-
15
j j j
ELECTRICAL:Cti'ARACTERisTICS
Each MECL 10,000 series circuit has been
designed to meet thedcspecifications shown
in the test table. after thermal equilibrium
has been established in an ambient temperature of 2SoC, while the circuit is in a test
socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
A
7
B
9
3:
o
o
...
...
~
C '0
,n.bl.
I I I I I I
2
-2.0 volts. Test procedures are shown for
only one input. or for one set of input con-
4
X3
3
II I ffil--.II ffil--.-
L+R 'J
R 'J
-===\
)(7 14
~
Charact_istic
Power Supply Drain Current
, I nput Current
Logic "1"
Output Voltage
Logic "0"
Output Voltage
Logic "1"
Threshold Voltage
Logic "0"
Threshold Voltage
Switching Times
150 n Loadl
Propagatton Delay
Rise Time
(20%'080%1
Fill Time
120%'080%1
--- - - - - - -
Symbol
IVoltsl
@Test
T empM'.tur.
'E
lin H
lin L
r
MC10164P Test Limits
+2SoC
-30"e
Min
M..
Min
8
VIH
INX
-ao"e
~.890
+;zsoe
~.810
+850
~.700
C
VILmin
-1.890
-1.860
-1.825
Typ
Mox
Min
Mox
60
-
75
265
-
-
-
-
VOH
-1.060
~.890
~.960
Unit
VIHm..:
VIL min
-
~.810
~.890
~.700
VOL
15
-1.890
-1.675
-1.850
-
-1.650
-1.825
VOHA
15
-1.080
-
~.980
-
-
VOLA
15
-
-1.655
-
-
-1.630
,+
t-
15
'----~
-
-
-
1.5
1.5
2.0
2.0
1.0
1.0
1.1
-
-
1,1
-
-
3.0
3.0
4.0
4.0
2.0
~
4.5
4.5
6.0
6.0
2.9
2.9
-5.2
-5.2
-5.2
VIHAmin
VILA
IN.
-
-
-
-
8
1,16
4,9
-
-
2
8
1,16
9
-
4
4,9
-1.615
Vde
9
~.910
-
Vde
-
-1.595
Vde
3.3
-
-
3.3
-
-
n.
j
1,16
1,16
1,16
1,16
-
-
Vde
-
IVeel
GNI
8
8
8
8
,.Ade
-
VEE
-
-
,.Ade
Pul.ln
+1.11 V
-
VEE
-1.500
-1.475
-1.440
-
2
0.5
-
-1.035
VILA max
mAde
-
15
15
15
15
15
15
15
VIHAmin
-1.205
-1.105
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
+85o C
2
4
15
t4+15+
'4-15t7+15+
'7-15t2+15+
'2-15+
I
TEST VOLTAGE VALUES
~
)(6 13
Pin
U'T_
:::l
c:
(1)
a.
tmn ____
)(5 12
W
:::l
~.
P SUFFIX
PLASTIC PACKAGE
CASE 648
'
X411
~
.....
8
-
IIIIII G
X'.5
X2
'5 Z
II~
X06
ditions. Other inputs tested in the same
manner.
...,-----..,
9
9
5
5
7,5
7,5
9
-
4
4
7
7
2
2
4
9
-
4
2
PuI.Out
15
8
1,16
-32 V
+2.DV
8
1,16
j j
I
Me1 0164 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
@
25°C
VCC1 ~ VCC2
+2.0 Vdc
~"'rtJ'"'
Coax
r--------...---..
I
I
Input
I
Pul. Generetor
Input Pul ..
t+-t-""2.0±O.2ns
(20 to 80%)
)
-- - - - ---,
I
I
2-
I
~
)
~y
I
I
===\
I
I
~
I
I
I
I
I
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from Tpiin to input
~
;-
'5
B'5
~'5
I
t
pin and TP out to output pin.
'5
r
I
I
All Input and output cable. to the
--1,/
I
I
I
cated in each scope channal input.
1
,.
I
50..ohm termination to ground lo-
V out
VEE - -3.2 Vdc
PROPAGATION DELAY
V out
3·144
I
I
I
I
~
Coax
r'C10164 (continued)
i
'II-
_c
Itl{;-
Ii ei:'
!t::I!'~i ".
eight data inputs and an enable, A high level on the enable
forces the output low. The MC10164 can be connected
directly to a data bus, due to its open emitter output and
output enable.
Figure one illustrates how a 1·of-64 line multiplexer can
be built with eight MC10164's wire ORed at their outputs
and one MC10161 to drive the enables on each multiplexer, without speed degradation over a single MC10164
being experienced.
APPLICATION INFORMATION
f1.~~..,...;-.:.--.:-. .. ~.....:,....:.~ •.:._:<.,.,. ... ;:...;..:...;.~O.:.- ............,.;...
i
-
..... ~ ..... ,~~ .•
3
Each MECl 10,000 _ios circuit has been
designed to meet thedcspecifications shown
in the test table. after thermal equilibrium
has been established in an ambient temperature of 250 C. while the circuit is in a test
socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input, or for one set of input conditions. Other inputs tested in the same
manner.
100-- 03
110-- 04
Power Supply Drain Current
I nput Current
9 0 - - 06
6 0 - - 07
...'fl
.j:O
.....
Logic "0"
---~
(j)
(2)
-1.105
-1.475
-5.2
-0.700
-1.825
-1.035
-1.440
-5.2
+8SOC
Unit
VIH max
VIL min
VIHA min
VILA max
VEE
(VCC)
Gnd
-
mAdc
-
-
8
1,16
4
5(j)
-
-
"Adc
"Adc
-
-
8
8
1,16
1,16
"Adc
"Adc
Vdc
-
4
5(j)
4
-
8
8
6
-
8
1,16
1.16
1.16
+
8
1.16
+
8
1,16
+
8
1.16
105
131
-
-
-
-
245
220
-
-
4
5
-
-
0.5
0.5
-
-
-
2
3
14
15
-1.060
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
-0.890
-0.960
-0.960
-0.960
-0.960
-
-0.810
-0.810
-0.810
-0.810
-0.890
-0.890
-0.890
-0.890
-0.700
-0.700
-0.700
-0.700
2
3
14
·15
2
3
14
15
-1.890
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.650
-1.825
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
-1.615
Vdc
-1.060
-1.080
-1.080
-1.080
-
-0.980
-0.980
-0.980
-0.980
-
-0.910
-0.910
-0.910
-0.910
-
Vdc
2
3
14
15
-
-1.655
-1.655
-1.655
-1.655
-
-1.630
-1.630
-1.630
-1.630
-
-1.595
-1.595
-1.595
-1.595
Vdc
-
-
Min
-
+
+
-
+
+
-
+
~
-
+
+
Unit
'hold H
'3+
'3_
-
14
15
3
2
2
2@
3
j
-
-
-
-
4.4
6.5
11.0
7.0
7.0
-
3.5
3.4
3.0
-2.3
-2.7
-
2.0
2.0
-
-
-
-
-
-
-
-
The same limit applies for all D type input pins. To test input currents for other D inputs,
individually apply proper voltage to pin under test.
Output latched to low state prior to test.
5'
c
~
Max
-
tsetup H
tsetup L
'0 80%)
-1.850
-
thold L
Fall Time (20%
-5.2
-0.810
-
'13-2-
Rise Time (20% to 80%~
-1.500
+25OC
4
5
t13+2+
t4+2+
HOld Time
VILA max
-1.205
8
t7+14+
t11+15+
t7+3+
Clock Input
Setup Time
VIHAmin
-1.890
IE
-
::J
....
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Switching Times (50-ohm Load)
Propagation Delay
Data Input
VILmin
lin H
VOLA
C')
-0.890
Typ
Threshold Voltage
("')
o
VIH max
Min
VOHA
3:
U1
_30°C
Max
-
"-"1
...o
...
l.SUFFIX-CERAMIC PACKAGE
CASE 620
VEE
Min
VOL
Logic "1"
Threshold Voltage
Test
Temperature
+85 0 C
-
"-.-----
f· ...'..... ·~·
@II
MC10165 Test Limits
+25OC
Max
t', ..t:1
CI')
r---0 '4
-300C
"'",'"...'""
TEST VOL TAGE VALUES
(Volts)
Test
VOH
Logic "0"
Output Voltage
03
• PSUFFIX
PLAS-TIC PACKAGE
CASE 648
Symbol
lin L
Logic "1"
Output Voltage
02 --015
120-- 05
Pin
Under
Characteristic
-
2
'·1·'·
~~,.~-.
;-5L.ecT"ICALCHAR~RfST-tCS
ns
-
4
-
--
4
6
+
4
+
-
+
-
-
-
-
6
+
+
+
+
+
+
+1.11 V
+0.31 V
Pulse In
Pulse Out
-3.2 V
+2.0 V
-
4
7
11
7
13
13
14
15
3
2
2
8
1,16
4
4.7
3
3
7
!
-
-
-
-
-
-
-
4
4
+
7
7
---
*
-
j
--
To preserve reliable performance, the MC10165P (plastic-packaged device only)
is to be operated in ambient temperatures above 7SoC only when 500 Ifpm blown
air or equivalent heat sinking is provided.
MC10165 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VCC1
VCC2+2.0 Vdc
K
V out
25"F~
C08J1i
Input Pul ..
t+ ". t- "" 2.0
ns ± 0.2 n.
(20 to 80%)
Data Input [()o~---""-o
TPin
'--TP
J
Unu..c:l outputs connected to •
50-ohm rasistor to ground.
50-ohm termination to ground located in each lcope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cabl.. Wire length should
be < 1/4 inch from TPin to input
-3.2 Vdc
VEE
pin and TP out to output pin.
~--"""',-------+1.11
out
V
o Input
NOTE:
'------+0.31 V
tsetup is the minimum time before the positive
tra~
sitlon of the clock pulse (C) that information must be
pra.ent at the data Input (0).
thold is the minimum time after the positive transition of the clock pulse· (C) that information must
remain unchanged .at the data input (0).
~---+1.11V
.....--....,.,-+---- +0.31 V
C
+0.31 V
\"---3-148
MC10165 (continued)
i
I
nected to this encoder such that, when a given condition
exists, the respective input will be at a logic high level. This
scheme will select the one of 64 different system condi·
tions, as represented at the encoder inputs, which has
priority in determining the next system operation to be
performed. The binary code showing the address of the
highest priority input present will appear at the encoder
outputs to control other system logic functions.
APPLICATION INFORMATION
~typical application of the MC10165 is the decoding of
/It8qI
$tatus on a priority basis. A 64 line priority encoder
in the figure below. System status lines are con·
tboW"
64-LINE PRIORITY ENCODER
,---------------------------------------------OLse
112 MC10l0l
I
Iz
MC10164
XO .... X7ABC
i~r~!:'"~~
~
DO
"Input
07 l1 02
03 ~
C
i
J.
i
J.
i
J
i
o
I
.J.
"
k'Ow"t i
iprlority
:tnput
i..:.
J-
~z
I
MC10164
~O ~
o
l~l~
Im=tta'~Il=mm=tt:E11~1=~
Q1 f+-+++l+lf+--------J
r;:::::::=
r;::=
001--
01~---+1+If+-------~
OOt--
o 01~----1+If+---------~
u 02~----HHH-----------HHH_--------~
07 l1 03~----I+If+-----------I+IH-----------HHH_~
., 001----
DO ~ 01~-----HH----------u 021------H~-----------Hf+---------~
07 l1 03~-----H~-----------HH-----------_HH_~
aO'L....----~
C
10
DO
~ 01~----_4+_----------~
C
DO
02~----~+_----------~+_----------~
03~----~+_----------~+_----------_;;_---"
.
.,
00
01
U 02
07 l1 03
C
DO
0
.
.,
00
01
U 02
07 l1 03
0
3-149
I-<>
DO 00
a 1 I- I-<> ,
02 I--H> MSB
r-
011---++1+If+-------~
u 02~--~HH~--------~HHH_---------J
07 l1 03~--~HH~--------~HHH_--------~HH~
~O ~
Six bit output
XO ...... X7ABCJ
u 02~--~HH~--------~HH~------~
07 l1 03~--++1+I~--------++1+If+---------++1+I~
U
07 l1
;-
XO . . . X7ABC
Il
., 00r-
DO ..
C
J
~
MC10164
J
~:$!$~~===:$!$~~===~~~~===1rc---
Highest 0:
~'Io'ity ol-i
I
r- 07
'-----
~
word yielding
number of
hlghett priority
channel pr.sent
at input
MECL 10,000 series
5-BIT MAGNITUDE
COMPARATOR
MC10166
Advance InforIllation
The MC10166 is a high speed expandable
5-bit comparator for comparing the magnitude of two binary words. Two outputs 8Ff
provided: A < B and A
B. A = B can be
obtained by NORing the two outputs with ail·
additional gate. A high level on the enabl1t<
function forces both outputs low. Multlplr
MC10166s may be used for larger word comparisons.
TRUTH TABLE
I
I
A
X
H
8
A <8
A>8
X
L
L
L
Word A = Word B
L
Word A
> Word
L
Word A
<
Po
= 440 mW
tpd
=
>
Outputs
Inputs
E
L
L
B
L
H
Word B
H
L
tvp/pkg (No Load)
Data to output 6.0 ns typ
E to output 2.5 "I typ
LOGIC DIAGRAM
veel = Pin 1
VCC2'" Pin 16
Vee
A4
84
= Pin
8
9
10----.-~
./
A3 12
83
2A>8
11 - - - _...._ /
L
1
t
I
1
A2 13
B2
14
---~--n._/
t;
3A-_ _ _ _~
BO
4
E
15
!
!
\
I
This is advance information and specifications are subject to change without notice.
,.J
S•• Genera' Information ..ction for packaging.
3-150
...o...3:
ELECTRICAL CHARACTERIST'ICS
(")
Each ME C L 10.000 series has been de·
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established.
The circuit is in a
0')
0')
test socket or mounted on a printed circuit
board and transverse air flow greater than
nO
-
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only selected inputs and outputs. Other
inputs and outputs are tested in a similar
manner.
::J
::to
::J
L SUFFIX
ffi
CERAMIC PACKAGE
CASE 620
c.
TEST VOL TAGE VALUES
Volts
@Tost
Temperatur.
::!~
......
I
If'
U'I
Power Supply Drain Current
Test
+2SoC
-lOoe
Unci...
Symbol
VILmin
-0.890
-1.205
-1.500
-5.2
-0.810
-1.890
-1.850
-1.105
-1.475
-5.2
+850 C
-0.700
-1.825
-1.035
-1.440
-5.2
Min
M••
Min
Typ
85
+8SoC
Ma.
Min
Max
Unit
106
mAde
220
IlAdc
V.Hmax
linL
5
Logic "'" Output Voltage
VOH
2
3
-1.060
-1.060
-0.890
-0.890
0.5
-0,960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
Logic "0" Output Voltage
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.615
-1.615
Vdc
Vdc
Logic "'" Threshold Voltage
VOHA
2
3
-1.080
-1,080
-1.825
-1.825
-0.910
-0.910
5
4
5,15
4,15
Vdc
Vdc
5
4
Logic "0" Threshold Voltage
VOLA
Vdc
Vdc
5
4
-0.980
-0.980
-1.630
-1.630
Switching Time,
Rise Time (20% to 80%)
Fall Time (20% 10 80%)
-1.595
-1.595
-
(50 n Loadl
Enable to Output
VIHAmin VILAmex
+1.11 V
6.0
I
2.5
2.5
2.0
2.0
VEE
(VCC I
GncI
8
1,16
8
1,16
8
8
1,16
1,16
8
8
8
8
1,16
1,16
1,16
.uAdc
-1.655
-1.655
2
2
2
2
3
3
3
3
2
VILmin
4,7,10,11,14
'E
linH
t9+2+
'9_2_
t1'-2+
t,'+2_
17+3+
'7-3115-3+
t'5+3'2+
'2_
VEE
VOLTAGE APPLIED TO PINS LISTED BELOW,
Input Current
Propagation Delay
Data to Output
VIHAmin VILAmax
MC10166L Test Limits
Pin
Characteristic
VIHmax
-lO"c
+25"c
12
12
15
15
15
15
Pul.ln Pul.Out
9
9
11
11
6
6
10
10
15
15
9
9
1,16
1,16
1,16
1,16
8
8
-3,2 V
+2.0 V
8
1,16
MC10166 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C
~
VCCI
VCC2:
+2.0 Vdc
251'F ~
V out
,x.0.11<'F
Coax
Coax
A >B
A2
Oate Input
or----:6--o
TPinJ
B2
AI
Bl AB
Al
BO
AO
B19
A19
BIB
AlB
B17
A17
B16
A16
B15
A15
B4
B14
A14
B13
A13
B12
A12
Bll
All
Bl0
Al0
B4
A4
B3
A3 AB
Al
80
AO
B9
84
A4
B3
A3 AB
AI
BO
AO
A9
BB
AS
B7
A7
B6
AS
B5
A5
B4
A4
B3
A3
B2
A2
Bl
Al
BO
AO
MC10166
A>B
A4
B3
A3 AB
Al
BO
AO
B4
A4
B3
A3AB
AI
BO
AO
A6B6A6B6A7B7ABBB
MC10166
A8 A<8 A' 8
FOT 9-81t Word
B4
A4
B3
A-8
I-++---,A < 8
~==::jA2
FIGURE 2 - 25·BIT MAGNITUDE COMPARATOR
. - - - - - i B l A>BI-....- - - A > 8
A1
80
AO
The MC10166 compares the magnitude of two 5·bit
words. Two outputs are provided which give a high level
for A> B and A < B. The A = B function can be obtai ned
by wire·ORing these outputs (a low level indicates A = B)
or by NORing the outputs (a high level indicates A = B).
For longer word lengths, the MC10166 can be serially
expanded or cascaded. Figure 1 shows two devices in a
serial expansion for a 9-bit word length. The A> Band
A < B outputs are fed to the AO and BO inputs respectively
of the next device. The connection for an A = B output is
also shown. The worst case delay time of serial expansion
is equal to the number of comparators times the data· to·
output delay.
For shorter delay times than possible with serial ex·
pansion, devices can be cascaded. Figure 2 shows a 25-bit
cascaded comparator whose worst case delay is two data·
to·output delays. The cascaded scheme can be extended
to longer word lengths.
3·153
MECL 10,000 series
'\
"'---------'
QUAD LATCH
MC10168
Advance Infor:rnation
The MC10168 is a Quad Latch with common
clocking to all four latches. Separate output
enabling gates are provided for each latch,
allowing direct wiring to a bus. When the clock
is high. outputs will follow the 0 inputs. In·
formation is latched on the negative·going transition of the clock.
Po = 310 mW typ/pkg INo Load)
tpd: G to a,. 2 n. typ
o to a - 3 nl typ
C to a .. 4 n. typ
DO
3------------~~
GO
Gl
4------+-----------------~
00
5----~~~~~----------~--/
;c------- 6
01
01
Cc
02
13
9----~~------~
G2
12------+-----------------~~__/
G3
I 0 ----~----=----------~
03
14 ____________
;c-------
II
02
15
03
~~
G
H
0
L
L
L
H
H
L
0-dontcare
VCC1 "" Pin 1
VCC2 = Pin 16
VEE
= Pin
TRUTH TABLE
C
0
a,,+1
-
8
This is advance information end speciflcationsllr. subject to change without notice.
s . . General Information .action for peckaglng.
3·154
0
0
L
H
L
0
L
H
ELECTRICAL CHARACTERISTICS
3:
C')
Each MECL 10,000 series has been de·
signed to meet the de specifications shown
...&
o...&
in the test table. after thermal equilibrium
has been established.
The circuit is in a
0)
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
00
0o
-
only selected inputs and outputs. The
other inputs and outputs are tested in the
same manner.
I-~L../
:l
~.
:l
L SUFFIX
c:
CERAMIC PACKAGE
CASE 620
c.
ct>
TEST VOLTAGE VALUES
(Volts)
@Test
Temperature
C
Min
Max
Min
MCt017tP T . . Limits
+2S oC
+IS<>C
TVp
M..
Min
Ma.
+2S<>C
+15<>C
VIHma.
-0.890
-0.810
-0.700
VILmin
-1.890
-1.850
-1.825
V'HAmi"
-1.205
-1.105
-1.035
VILAma.
1.500
-1.475
-1.440
VEE
-5.2
-5.2
'
-5.2
I
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Unit
VIHm8.
VILmin
VIHAmin
VILA.....
VEE
IVCCI
Gnd
Ie
8
-
-
-
65
77
-
-
mAde:
2,7,9,14,15
-
-
-
8
1,16
linH
14
-
-
-
-
220
-
-
#lAde
14
-
-
-
8
1,16
linL
14
-
-
0.5
-
-
-
-
#lAde
-
14
-
-
8
1,16
VOH
6
13
13
6
13
-1.060
-1.060
-1.890
-1.080
-1.060
-0.890
-0.890
-1.675
-
-0.960
-0.960
-1.850
-0.980
-0.980
-
-0.110
-0.810
-1.650
-
-0.890
-0.190
-1.825
-0.910
-0.910
-0.700
-0.700
-1.615
-
Vdc
Vdc
Vdc
Vdc
Vdc
15
15
-
2,7,9,14,15
-
15
15
-
8
8
8
8
1,16
1,16
1,16
1,16
1,16
6
13
-
-1.655
-1.655
-
-
-1.630
-1.630
-
-1.595
-1.595
Vdc
Vdc
-
2,9,14,15
2,7,14,15
-
7
9
8
1
1,16
1,16
+0.31 V
Pulse In
Pulse Out
-3.2 V
+2.0 V
2'9'1~4'15
]7
:
8]
1,16
VOL
VOHA
. VOLA
Switching Times
(SO n Load)
Propagation Delay
PSUFFIX
PLASTIC PACKAGE
CASE 648
4 012
_30Ge
E1 2
U1
co
::J
c:
II>
Q.
:~~~:
::
::
t7+13+
13
-
-
t7-13-
1&+
13
6
-
-
Rise Time (20% to 80%1
t13+
13
6
-
-
-
-
Fall Time 120'1(, to 10%1
t13-
13
-
-
Ifl-
1~'5
t
1.1
4!.0
2,0
J
t
6 .0
::
::
-
-
-
-
-
-
! - -
3.3
"5
::
-
-
-
-
-
-
-
-
-
13
13
6
13
6
13
8
MC10171 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25"c
Vec, - VCC2
V out
+2.0 Vdc
Pul ..
V out
PROPAGATION DELAY
Gener.tor
Input Pul ••
t+ = t-:::: 2.0± 0.2 ns
(20 to 80%)
L-------T f;.-,:-----'
I
Vee
z
-3.2 Vdc
All input end outpu t eabl •• to th_
scop ..... equal length. of 5G-ohm
coaxial cabl.. Wlr. length thculd
<
be
1/4 inch from TPin to input
pin end TP out to output pin.
3-160
Unused outputs connected to
a 50-ohm resistor to ground.
MECL 10,000 series
DUAL
BINARY TO 1-4-DECODER
(HIGH)
MC10172
The MC10172 is a binary-coded 2 line to
dual 4 line decoder with selected outputs high.
With either ~O or El low, the corresponding
selected 4 outputs are low. The common enable ~, when high, forces all outputs low.
All propagation delay times are equal. High
impedance 50 k ohm resistors on all inputs
eliminate the need to tie unused inputs to Vee.
POSITIVE LOGIC
10003
11 002
12001
A 9
13 '00.0
301 3
Po - 326 mW typ/pkg (No Load)
tpd'" 4.0
typ
n.
B 7
401 2
E
16
601
1
6 01 0
E1 2
vee1 - Pin 1
VCC2 '!'" Pin 16
VEE-PinS
TRUTH TABLE
E
El
EO
A
B 010 011
L
H
H
H
H
H
H
H
H
L
L
L
H
H
L
L
L
H
H
H
"L
L
L
L
L
4>
4>
.4>
4>
L
L
L"
H
L
H
L
H
L
L
H
L
L
H
L
L
L
L
012 013 000 001
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
tP .. 00 nit Care
... G......,lnformetlon Mctlon for ~ck.liiJl"g and" ",..Imum ratlngl.
3-161
H
L
L
L
H
L
L
L
H
L
L
L
L
L
002 003
L
L
H
L
L
L
L
L
L
L
H
L
L
L
s:
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linaar fpm il maintained. Outputs
are terminated through a 5O-ohm resistor
to -2.0 volts. Test procadures are shown
only for selected inputs and outputs.
Other inputs and outputl are tested in a
similar manner.
....
....'-I
(')
EOt.
10
0
ao
3
12
ao
1
13
ao
0
A 9
nO
::J
~.
::J
c:
<»
c..
L SUFFIX
CERAMIC PACKAGE
CASE 620
3 01 3
•
N
-
11 00 2
7
4 01 2
E
15
5 01
1
o;2~6al0
TEST VOLTAGE VALUES
IVolts'
lilT...
Temperature
~
( I)
I\J
Pin
U_
CMrllCteriltic
POwtr Supply Drain Current
Input Currant
Logic "1"
Outpu,Vol_
T..
Min
IE
8
14
14
-
linH
linL
VOH
-
VILA,...x
-1.500
VEE
-5.2
+25"c
+S5"c
-0.810
-0.700
-1.850
-1.825
-1.105
-1.475
1.440
-5.2
+B5"c
Mo.
TVp
M...
Min
62
77
220
-
-
mAde
-
-
-
0.5
-0.960
-0.960
-1.850
-0.980
-0.980
-
-
-0.890
-0.890
-1.825
-0.910
-0.910
Unit
VILmin
VIHAmin
VILAmex
.Ade
14
-
-
",Adc
-
14
-
-
-0.700
-0.700
-1.615
Vdc
Vdc
Vdc
2
14
15
-
-
2,7,9,14
-
-
-
Vde
Vde
-
-
-
2
14
-
-
2.9,14
2,7.14
-
VOHA
6
13
-1.060
-1.060
-1.890
-1.060
-1.060
Logic "0"'
Th ..... oId Voltogo
VOLA
6
13
-
-1.655
-1.655
-
-
-1.630
-1.630
-
-1.595
-1.595
Vdc
Vde
'7+6t7-6+
6
6
13
13
6
1.5
6.2
1.5
4.0
6.0
1.5
6.4
ns
+
3.3
+
1.1
~
2.0
~
3.3
~
~
VOL
-
0.810
-0.810
-1.650
Switching Times
ISO 0 Lood.
Prop8ption DellIY
RiM Time (20% to 8ea)
Foil Time 120% 10_1
+1.11 V
t7+13'7-13+
'6+
t13+
'6'13-
13
6
13
,,!
1.0
~
-1.035
VIHm.x
Logic "0" Outpu, VoI_
Logic "1"
Th ..... oIdVoI_
6
13
13
-0.890
-0.890
-1.675
VIHAmin
-1.205
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
+25"c
Min
-
-
VILmin
-1.890
MC10172L T . . Limits
-30"c
SV-
_lO°e
VIHmax
-0.890
,,
~
1.1
~
3.4
2
2
14
14
2
14
2
14
+0.31 V
9,14
9,14
2,9
2,9
9,14
2,9
9.14
2,9
VEE
IVee'
Gnd
1,16
7
9
8
8
8
8
8
8
8
8
8
8
1.16
1.16
1,16
1.16
1,16
1,16
1,16
1,16
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
7
6
6
13
13
6
13
6
13
8
1,15
-
j
, EUemfOAL CHARACTERISTICS
:;:
n
.....
o.....
Each MECL 10,000 serias circuit has been
d.igned to meet the de specifications
shown in the test table, after thermal equilibrium has been established. The circuit is
E014
10
ao
3
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear 'pm is maintained. Outputs
are terminated through a 50-ohm resistor
11 aD 2
to -2.0 volts. Test procedures are shown
12
ao
1
13
ao
0
"
N
only for selected inputs and outputs.
Other inputs and outputs are tested in a
similar manner.
c;-
-
A 9
J Q1 3
O
...5'
::J
c:
(!)
a.
P SUFFIX
•
E
7
PLASTIC PACKAGE
CASE 648
15
5 Q1
1
601 0
e; :z
TEST VOLTAGE VALUES
(Volts)
@T...
4'
....
Temperature
0)
W
_lOGe
VIHmax
-0.890
+25"<:
-0.810
+85"<:
-0.700
I
I
I
I
VILmin
-1.890
I
-1.850
-1.825
I
VIHAmin
-1.205
VILAma •
-1.500
VEE
-5.2
-1105
-1.475
-5.2
-1.035
-1.440
-5.2
TEST VOLTAGE API'LIED TO PINS LISTED BELOW,
CNract_iltic
Power Supply Drain Current
Input Current
Logic "1"
OulpU.Vol_
Logic: "0" OuIPu, VoI_
Logic: "1"
I
linL
14
-
-
0.5
6
-1.060
-1.060
0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.700
-0.700
13
-1.890
-1.675
-1.850
-1.650
-1.615
6
13
-1.080
-1.080
-
-0.980
-0.980
6
13
-
VOH
13
I VOL
I VOH!.
I VOLA
Throohold Vol.age
62
77
8
14
Threshold Vohage
LOQic "0"
I
IE
linH
220
-1.655
-1.655
-1.595
-1.595
Switching Times
150 n Loadl
Propegetion OeIay
Fall TIme C20% to 80%)
VEE
IVee l
Gnd
8
1,16
14
8
1.16
2
14
15
t7+13'7-13+
ts+
t13+
ts'13-
6
6
1.5
4.0
6.0
!
~
6
1.1
2.0
~
3.3
13
6
13
~
~
~
13
13
14
8
1,16
1.16
1,16
2.7,9,14
8
8
8
8
8
1.16
1,16
8
8
1,16
1.16
2
14
2,9,14
2,7,14
+1.11 V
'7
H
OOn
Po ~ 275 mW tvp/pkg (No Lood)
tpd - 2.5 nl tvp
tP., Don't Cere
POSITIVE LOGIC
NEGATIVE LOGIC
00
I
1 00
000 6
000 60
001 5
DOl 50
201
201
0104
0104
011 3
011 3
15
15 02
Q2
020 13
020 13
021 12
021 12
1403
,
.(
1403
030 11
030 II
031 10
031 10
Clock 7 - - - - - - '
Vcc Vee
z
Pin 16
Pin 8
8M General Information section for packaging.
3-165
ELECTRICAL CHARACTERISTICS
-
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal
equilibrium has been established. The
circuit is in a test socket or mounted on a
printed circuit board and transverse air
flow greater than 500 linear fpm is
maintained. Outputs are terminated
through a 5().ohm resistor to -2.0 volts.
3:
L SUFFIX
...o
........
CERAMIC PACKAG E
CASE 620
c;-
o
W
O
::J
....
::J
~l
tEJ,,·
Ch • .ctl'risttc
Power Supply Drltin Current
I"put Current
....ctJOl II
Ol
j
I
I
Symbol
'E
linH
Input leakage Cur"'"t
linL
logic "'"
OutPUt Voltage
VOH
logic "0"
Output Voltage
VOL
Logic "'"
Thr8lhold Voltega
VOHA
Logic "0"
Threshold VoltagIJ
VOLA
lUnd
..
Test
-30"1:
+25"c
_DC
MC10173L T_ Limit.
+25"c
I
I
8
5
-30"1:
Min
I
- I
Max
Min
I
-
-
I
I
I
All
M..
Typ
56
I
I
-0.890
-0.890
-1.675
-1.675
-0.960
-0.960
-1.850
-1.850
-0.980
-0.980
-1.655
-1.655
M..
t5+1+
'5-1t7-1+
t7_1_
t9+1+
t9+1t9-1+
'9-1Setup Time
Data Input
Select Input
lsetup
lsetup
Hold Time
Data Input
Select Input
66
295
295
250
250
~Adc
thold
thold
-1.475
0.8
3.7
-0.810
-0.810
-1.650
-1.650
-0.890
-0.890
-1.825
-1.825
-0.700
-0.700
-1.615
-1.615
-0.910
-0.910
-1.630
-1.630
1.0
l l l
1.6
1.6
1.1
1.2
1.2
6.2
1.6
1.6
1.3
t t t
-1.595
-1.595
3.5
1.1
5.3
VIHma
I
VIL min
I
VIHA min
I
-
(VCCI
VEE
VILA mal
16
16
l
i6
Vdc
Vdc
6.9
5
Vdc
Vdc
6.8
5.1
1.4
1.4
1.2
Vdc
Vdc
+0.31 Vdc
I
6.8
6.8
6.1
l t l
2.0
3.0
I
Pul.ln
Pul_Out
6
6
5
5
5.7
5.1
1
9
I
I I 1
5.1
1,9
2.5
1.5
1.5
3.5
1.4
4.0
Fell Time
t-
1.2
4.0
1.5
3.5
1.4
4.0
16
16
16
16
16
16
16
16
-3.2 Vdc +2.0Vck
I
l l l
~.8
4.0
touch input pin, one at a time.
-1.440
Vdc
Vdc
1.2
(:!OlO_1".
VEE
-5.2
-5.2
-5.2
l
t+
_led
VILArnu
1.500
-1.105
-1.035
~Adc
RiNTime
(20 to 80%1
·VILmin
VIHAmin
-1.205
-1.850
-1.825
1.11 Vdc
16+1+
'&-1-
Select Input
Unit
mAde
Propagation Delay
Clock Input
VIL min
1.890
-0.810
-0.700
+85"c
Min
Switching Tun..
Data Input
VIH max
-0.890
VOL TAGE APPLIED TO PINS LISTED BELOW:
0.5
-1.060
-1.060
-1.890
-1.890
-1.(110
-1.080
Co
(Vohl)
• Toot
Temper.tuN
CIOC" 1 _ _
Pin
c:
ro
TEST VOLTAGE VALUES
5,1
1,9
8
8
8
I
16
I I I
EtEC'TRtCAt: CtlARACTE1llSTteS .
•
Each MECL 10,000 _ieo circuit hao been
designed to meet the de opacifications
_ n in the test table, eft.. thermal
. .uilbrium has been established. The
circuit is in a test lOCket or mounted on a
printed circuit board and transverse air
flow greet.. than 500 linear fpm is
maintained. Outputs are terminated
through a 51k>hm resistor to ·2.0 volts.
Power SupplV Drain Current
Input Currant
--Cf'en
III
Symbol
Toot
-...J
Logic "'"
Output Voltage
Logi.c "0"
I:
(I)
-30"<:
Min
Max
Min
+25"<:
Ty.
o Toot
T.........eture
-3O"c
+25"<:
+8&"<:
VOH
-1.060
-1.060
VOL
-1.890
-1.890
-1.080
-1.080
Output Voltage
VOHA
Logic "0"
Threshold Voltage
VOLA
T'h,lIhoid Voltage
VIH max
-0.890
-0.810
VILmin
-1.890
VIHAmin
-1.206
ViLA .....
-1.500
VEE
-1.850
-1.105
-1.475
~.2
-0.100
-1.825
-1.035
-1.440
~.2
-0.890
-0.890
-1.675
-1.675
~.2
VOLTAGE APPLIED TO PINS LISTED BELOW:
+85"<:
MIX
Min
Max
.-l
Unit
16
16
1
16
",Adc
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.100
-0.700
Vdc
Vdc
6.9
5
-1.850
-.1.850
-0.980
-0.980
-1.650
-1.650
-1.825
-1.825
-0.910
-0.910
-1.615
-1.615
Vdc
Vdc
9
-1.655
-1.655
-1.630
-1.630
Switchl", TI .....
-
IVeel
VIHmu
mAde
0.5
All
C.
(Volte)
MCt0173P TIM Limits
'E
lotte "'"
::J
....
TEST VOLTAGE VALUES
66
295
295
250
250
linL
n-O
:5.
linH
nput leek. Current
..&
PLASTIC PACKAGE
CASE 648
CIOC.'--
Ch ....:teriltic
..&
P SUFFIX
~-.,
Pin
Und.r
~
n
o
.....
Co)
I
I I
16
16
16
16
Vdc
Vdc
-1.595
-1.595
Vdc
Vdc
+1.11 Vdc
Pro~tion
Oetev
Oat. Input
16
2.5
16+1+
!
'6'115+1+
15-1_
Clock Input
17_1+
t7_1_
4.5
4.5
5.1
5.1
Select Input
19+1+
3.5
9
'9+1'9-1+
'9-1SetUP Tim.
Date Input
Select Input
Hold Time
D.t.lnput
S.lect Input
Ri.Time
120 to 80%1
F.II Time
(20 to 80%1
·Vllmin .pplied
10
1
1
ltetup
lsetup
1.5
2.5
5.1
1.9
thold
thold
0.0
-0.5
5,1
1.9
t+
2.0
t-
each input pin, one III
2.0
II
time.
MC10173 (continued)
SWITCHING TIMES TEST CIRCUIT
V out
oeta
Input
s.1~tg
t+ .. t- '"' 2.0 nl
000'
.;----+-I-ooJ
001 5
+----+_+<~
010"
+---++.j...o.J
011 3
-'-----1-+...j...~
02013
.!....--++.+ooJ
(20% to 80%)
f tOg a•• hown on wav",orml.
1 00
TP out
201
021 12 +-----1-+.j...o~
030 11
+---++-,O,J
03110
-'---+--'01
3.2 Vdc
50·ohm termination· -to ground fa·
cated in each ICOpe channel input.
All input and output cabl •• to the
scope ar. equal lengthl of SG-ohm
coaxl., cabl•. Wire length should be
<
1/4 inch from TPin to input pin
and TP out to output pin.
Unu_d outputl ar. connected to
50-ohm r.,lltor to ground.
3·168
t·
MC10173 (continued)
,I
L
WAVEFORMS.26"C
DATA TO OUTPUT WITH CLOCK AT VIL
CLOCK TO OUTPUT
J
OATA
f tog - 1.0 MHz
OUTPUT
o
."~)-t:'~O~I-d----------~~~~: ~
,
50%
c-------I-------- +0.31 V
NOTE:
t . . up I, the minimum time !Mfor. the pollttv.
tranlltlon of the clock put.. le) ttaM Info,,.,...tion mu.
be pr_nt at the Input (D) or (~).
. thold I, the mlnl~um time aft. the posltlv. tranIItJon of the clock put. (e) thet Inform8tion mu.
ramain unchllnged at the det.lnput (D) or (S),
i-
t
3-169
MECL 10,000 series
DUAL 4 TO 1 MULTIPLEXER
MC10174
The MC10174 is a high speed dual channe~
multiplexer with output enable capability. The:
select inputs determine one of four active data
inputs for each multiplexer. An output enable
forces both outputs low when in the high state~
The enable is also useful in wire·DRing several,
multiplexers to achieve additional channel caps-<
bility. Delay from data input to output is typi~
cally 3.5 nanoseconds.
Po = 305 mW .yp/pkg (No Load)
tpd == 3.5 nltyp (Data to output)
xo
3
X1
5
X2
4
X3
6
A
7
B
9
2
Z
e;;;bi; 14
VO 13
V111
15 W
V212
V310
TRUTH TABLE
ENABLE
VCC1 = Pin 1
VCC2 "" Pin 16
E
VEE""Pin8
H
L
L
L
L
4J -
s •• General
ADDRESS INPUTS
B
OUTPUTS
A
Z
W
'"
L
XO
X1
X2
X3
L
YO
Y1
Y2
Y3
'"
L
L
.L
H
L
H
H
H
Don't Cere
Information section for peck aging.
3·170
:r.
>~
_ _ ,_,' __
4 ____ "
~_
•.
~A""_"
.,,~
...
',"
~
t\
.. :.~.
,":'
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet thedcspecifications shown
in the test table, after thermal equilibrium
has been established in an ambient temperature of 25°C, while the circuit is in a test
socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
onlv one input, or for one set of input conditions. Other inputs tested in the same
manner.
30
X,
50
II
X2
40
III~
X3
60
A
7
•
9
3:
n
o
~
~
xo
~
.....
~
2
8
I I I l""'i
~'40
VO'30
Illl~
'''':
~'"
4J
+8SoC
Ur;:;.
eharact.istic
Power Supply Drain Current
-lOoe
L SUFFIX
CERAMIC PACKAGE
CASE 620
VIH max
-0.890
VIL m;n
-1.890
VIHA m;n
-1.205
VILA max
-1.500
VEE
-5.2
-0.810
-1,850
-1.105
-1.475
-5.2
-0.700
-1.825
-1.035
-1.440
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
+8So C
Min
-
CD
Co
(Voltsl
Temp... 'u,.
-3o"C
+25o C
Mel0174L Test limits
+25oe
:::I
c:
,=w,,~""""
@lTest
V3'O
.....
:::I
....
-
IIII
Y212
-
~
Z
SVmbol
Test
Min
Mu:
Min
Typ
IE
8
-
-
-
58
Max
73
Max
-
ImH
4
14
-
220
330
-
-
-
Unit
VIH max
mAdc
-
!JAdc
4
14
Vll min
VIHA min
VILA max
(Vee l
VeE
Gnd
8
1.16
-
8
8
-
1m L
4
-
-
0.5
JJAdc
-
4
-
-
8
1,16
1.16
1,16
LogiC "'"
Output Voltage
VOH
15
-1.060
-0.890
-0.960
-
-0.810
-0.890
-0700
Vdc
13
-
-
-
8
1,16
Logic "0"
Output Voltage
VOL
15
-1.890
-1.675
-1.850
-
-1.650
-1.825
-1.615
Vdc
14
-
-
-
8
1,16
-0.910
-
Vdc
-
-
13
-
8
1,16
-1.595
Vdc
-
-
14
-
8
1,16
Input Current
-
-
Logic "1"
Threshold Voltage
VOHA
15
-1.080
-
-0.980
-
-
logic "0"
Threshold Voltage
VOLA
15
-
-1.655
-
-
-1.630
+1.11 V
Switching Times
(50
n
-
-
Pulse In
Pulse Out
-3.2 V
+2.0 V
'5
j8
l'j'6
Load)
.,opaga"on O.'ay
Rise TIme
(20%
'0 80%)
Fall Time
(20% to 80%)
::;~,';~:~
t7+15_
15
'7_15+
15
'14+1515
'14-15+
15
t+'5
t-
15
::
::
:;
:~
::
::
!
;~
6.4
6.4
3.1
3.1
3.4
2.0
2.0
1.0
1.0
1.1
5.0
5.0
2.0
2.0
2.0
6.0
6.0
2.9
2.9
3.3
2.1
2.1
0.9
0.9
1.1
6.4
6.4
3.2
3.2
3.6
3.4
1.1
2.0
3.3
1.1
3.6
1.9
1.9
1.0
n,
=
=
:;
11
11
13
-
7
1
-
7
14
14
14
-
14
j
MC10174 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 26°C
Input
Input Pulse
t+
= t- = 2.0 1.
0.2 ns
(20 to 80%1
50-ohm t .... min.tion to ground lo-
I
cated in each scope channal input.
L----Fi---J
All input and output cabl.s to the
scope are equal lengths of 50-ohm
coaKia' cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
1:t
0.1 I'F
VEE:::;: -3.2 Vdc
Unu.d output connected to a
5O-ohm resistor to ground.
PROPAGATION DELAY
Vout
Vout
3-172
'\
QUINT LATCH
MC10175
MECL 10,000 series
' - - - - -_ _- - - - - l
The MC10175 is a high speed, low power quint latch.
It filatures five D type latches with common reset and a
eon,mon two-input clock. Data is transferred on the nega:tive edge of the clock and latched on the positive edge.
,The two clock inputs are "OR"ed together. Propagation
".ys are typically 2,5 nanoseconds from each data input
11) the output.
Any change on the data input will be reflected at the
.outputs while the clock is low. The outputs are latched
on the positive transition of the clock. While the clock
IS In the high state, a change in the information present
at the data inputs will not affect the output information.
The reset input is enabled only when the clock is in the
high state.
The MC10175 allows storage of five bits of information,
and ~t is useful in temporary storage applications in high
speed central proCessors, accumulators, register files, digital
communication systems, instrumentation, and test equip·
ment.
POSITIVE LOGIC
NEGATIVE LOGIC
001o-------------~~
1400
OOIOI---------------i
01 12'----------i-lf--l
1501
01
02
13---------~_I~
2
03 9-----------+-i~
3
04 5,----------i-lf--l
Co6
4 04
12'---------~_I~
15 01
02
0213-----------+-~~
2 02
03
03
3 03
04 5----------~_I~
4 01
CO 6
Ci 7
R.Mt11 ___________~~--~
CI
7
A.Hetl' ___________~~---J
"~------------------------------------------------------------~
TRUTH TABLE
:.!
...
0
CO
Cl
Reset
a n+l
L
L
L
L
H
L
L
L
L
H
X
X
X
X
H
X
L
On
X
H
L
On
H
X
H
L
X
H
H
L
vee1 '"
Pin 1
VCC2 "" Pin 16
VEe" Pin 8
Po:c: 400 mW typ/pkg (No Load)
tpd
..... General Information section for packaging and maximum ratings.
3-173
c
2.6 ns tvp (Oete to Output)
ELECTRICAL CHARACTERISTICS
"
:is:
00
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
~;
o....
"
I I I
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor
,
to -2.0 volts. Test procedures are shown
0'
onlv for selected inputs and outputs.
Other inputs and outputs are tested in a
similar manner.
~3
I I I
3
03
~.
R
04 5
co
6
Cl
7
...
I Power Supply Drain Current
.".
II nput Current
~
'-I
Ch.rc:teristic
I
Symbol
I
Test
Temperatur.
_30 Ge
a1
C
FI
+25"c
MC10175L Test Limits
-lOoe
Min
I
linH
I
Logic "'"
Output Voltage
VOH
14
15
-1.060
-1.060
Logic "0"
Output Voltage
VOL
14
15
14
15
-1.890
-1.890
-0.890
-0.890
-1.675
-1.675
-1.080
-1.080
VOLA
14
15
t10+14+
110-14t6-14+
ts-14t11+4 t11+14-
14
1.0
~
!
4
14
14
14
14
14
0.9
0.9
1
+8SoC
Min
1
MI.
Unit
.uAdc
!
-0.810
-0.810
-1.650
-1.650
-1.850
-1.850
-0.980
-0.980
-1.655
-1.655
Clock Input
Reset Input
Setup Time
Hold Time
-0.890
-0.810
-0.700
I VIH ma.
Rise Time (20 to 80%)
tsetup
thold
t+
Fall Time (20 to 80%)
t-
1.0
1"0
3.6
3.6
1.0
1.0
2.5
1.5
-
1.1
11
/
/
35
3.5
VILA.,...
-1.850
-1.205
-1.105
-1.500
-1.475
-1.825
-1.035
-1.440
VEE
-5.2
-5.2
-5.2
VIL min
I VIHA min I
VILA m ••
I
VEE
1,16
-
Vdc
Vdc
6
6
10
12
-
Vdc
Vdc
6
6
-
10
12
+0.31 Vdc
6.7
6,7
7
7
6
6
7
7
6,7
6,7
Pul_ln
Put. Out
10
10
10,6
10,6
7,11
7,11
6,10
6,10
10
14
1,16
8
1,16
8
1,16
8
1,16
8
-3,2 Vdc +2.0Vdc
1,16
8
!
l !
-1.8251-1.615
-1.825 -1.615
Vdc
Vdc
-0.910
-0.910
1.0
3.6
3.6
4.4
4.4
4.2
4.2
~
1.0
1.0
/
11/
1.1
CD Individually test 88Ch input; IPply VIL min to pin under test.
® Output I.tched ttJ h~ logic Itate prior to test.
.- -
ns
t
3.7
3.7
...
--
10
12
5
10
10
-
1~~
",.".-
._-- --.----- .......!
8
1,16
8
8
1,16
1,16
8
8
1,16
1,16
8
8
8
14
1,16
1,16
1,16
l t l
,r
...
Gnd
6
6
6,10
6,12
Vdc
Vdc
-1.595
-1.595
3.5
3.5
4.3
4.3
3.9
3.9
.~
VIHAmin
VILmin
-1.890
.e:
6
7
10
11
+1.11 Vdc
3.6
3.6
4.7
4.7
4.0
4.0
c:
mAdc
Switching Times
Data Input
VIH m ••
j..IAdc
0.5
-0.960
-0.960
~,
:J
VOLTAGE APPLIED TO PINS LISTED BELOW,
97
290
290
290
650
6
7
10
11
All
VOHA
M ••
78
linL
Logic "0"
Threshold Voltage
L
+25"1:
Typ
Min
'E
Input Leakage Current
Logic "1"
Threshold Voltage
M••
:J
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
CVOItI)
+85"c
I
C1I
nO
L SUFFIX
(IT"t
ReYll11
Pin
Under
o
....
.....
-
0'
.:, :0·
~~
,.; .
MC10175 (continued)
SWITCHING TIME TEST CIRCUIT
V out
Coax
Data Input
2
02
TP out
PRF == 1.0 MHz
t+ = t- = 2.0 n$
(20% to 80%)
9
VOL = 0.31 V
VOH=1.11V
04
4
01
5~-------t-t-1
CO 6
Cl
7
Reset 11--+________-+__---"
J
----f}~~~F
VEEL~'VdC
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TP in to input pin
and TP out to output pin.
3·175
MC10175 (continued)
VOLTAGE WAVEFORMS
RESET INPUT
CLOCK
--+1.11 V
~--1'-----+0.31
V
50%
tl1+14_+0.31 V
~+1.11V
50%
1'----+0.31 V
CLOCK INPUT
DATA INPUT
+0.31 V
r:==-~=h..j:::.!.::::":'::::- + 1. 11 V
+0.31 V
~---~------+1.11
V
50%
o
'-----+0.31 V
~------+1.11
V
C------...J'---------+0.31 V
NOTE:
tsetup i, the minimum time before the positive
transition of the clock pulse (C) that information mUlt
be present at the data Input (0),
thold i, the minimum time after the pOlitive
transition of the clock pulse eel that information mUlt
remain unchanged at the data input (0).
3-176
MECL 10,000 series
HEX "0" MASTER-SLAVE
FLIP-FLOP
MC10176
The MC10176 contains six high-speed, master slave lype "D" flip-flops. Clocking is common to all six flip-flops. Data is entered into
the master when the clock is low. Master to
slave data transfer takes place on the positive·
going Clock transition. Thus, outputs may
change only on a postive·going Clock transition.
A change in the information present at the data
(D) input will not affect the output information any other time due to the master-slave
construction of this device.
Po - 460 mW typ/pkg (No Load)
f'ogglo 150 MHz (typ)
2 00
3 01
VCCI - Pin 1
VCC2 - Pin 16
VEE - Pin 8
4 02
13 03
CLOCKED TRUTH TABLE
D
C
14 04
a,,+1
L
,.
HO
HO
L
L
H
H
an
tP '"' Don't Car.
15 06
• A elock H i, • clock transition
Clock 9
's.f ~,..r"
from a low to a high .tate.
Information Mction for peckaging.
3-177
ELECTRICAL CHARACTERISTICS
Each MECL 10.000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal
uilibrium has been established. Th e elf·
M'
on a
flow
ined.
-ohm
Q"'- =U-"Q,
=U-"Q'
s are
I the
C_.9
Power Supply Drain Current
Input Current
Symbol
Tm
IE
8
Mo.
+25OC
Typ
Min
88
'inH
9
'fJ
.....
Input Leakage Current
IVol..1
"8
V.Hme.
V'Lmin
VIHAmin
ViLA .....
VEE
_lODe
-0.890
-1.890
-1.205
-1.500
-5.2
+2S o C
-0.810
-1.850
-1.105
-1.475
-5.2
+85OC
-0.700
-1.826
-1.035
-1.440
-5.2
::J
~.
C
MCl0176l Test limits
-30D e
Min
'-I
en
TEST VOLTAGE VALUES
::J
~=U-"~
Pin
Und.
CharKt.ristic
OTm
Temperatur.
...
...
n
o
-
~"
Itr in·
nner.
-
:tJ '"
-
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
rinL
TEST VOLTAGE APPLIED TO PINS LlSTEO BELOW:
+8SoC
Mo.
Min
M. .
Unit
110
mAde;
220
310
~Ade;
VIHma.x
V'Lmin
V,HAmin
ViLA..... VEE
5
9
#JAde
0.5
0.5
9
l3.
8
1.16
8
1.16
1.16
8
5
9
~Ade;
IIICC I
Gnd
8
1.16
1.16
8
8
1.16
1.16
8
8
1.16
1.18
8
8
1.16
1.16
8
8
1.16
1.16
-3.2
llde;
+2.0
llde;
8
1.16
~
CD
Logic "'"
VOH
Logic "0"
IIOL
Output Voltage
Outpu t Voltage
Logic "'"
Threshold Voltage
IIOHA
Logic "0"
IIOLA
Threshold Voltage
2t
1St
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
IIde
llde;
2t
1St
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
llde;
llde;
2t
1St
-1.080
-1.080
-1.655
-1.655
2t
1St
-1.630
-1.630
12
IIde
IIde
-1.595
-1.595
12
llde;
llde;
12
+1.11 Vdc
Switching Times
Clock Input
Pr~tion Delay
'9+2+
'9+2'2+
'2-
Rise Tim. C20 to 80%)
FoU Time 120'080%1
1.4
1.4
1.0
1.0
1.5
1.5
1.1
1.1
4.6
4.6
4.1
4.1
Setup Time
tsetup
2.5
Hold Time
'hold
1.5
Toggle Fr_oncy
Ou"",t I~ to be ....
-0.910
-0.910
-0.980
-0.980
12
f.og
-\....
2
4.5
4.5
4.0
4.0
150
-.
~
'.'
-
.
-.
-.
- . -..
J
,"
.
MHz
. ". .
.
~
'-
_red after. clack pu" h. bean -'ied to C inpUt IpIn91JL ~~~ ~~
Pulse In
5.9
5.0
5.0
4.4
4.4
n,
n,
125
.
1.5
1.5
1.1
1.1
+0.3111de;
5.9
5.9
Put .. Out
2
II
j
8
1.18
8
1.16
8
1.16
IVIC10176 (continued)
L
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC
VCCI
= VCC2 =
Gnd
Coax
Coax
' T P out
Pulse Generator
Input Pulse
t+
= t-:::
2.0 ± 0.2 ns
(20 to 80%)
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
Unused outputs arG tied to a 50ohm resistor to ground.
< 1/4 inch from TPin to input
pin and TP out to output pin.
VEE::: -3.2 Vdc
PROPAGATION DELAY
r------""'----
+1.11 V
50%
+0.31 V
C
_---JI
.;;....0
o
f,etup is the minimum time before the positive
transition of the clock pul •• Ie) that information
mu,t be pr ...nt at the data input (0),
thold is the minimum time after the positive transition of the clock pulse (e) that information must
ramain unchanged at the data input (0). Note that
thold may be a negative number.
3-179
.,
:
~.
MECL 10,000 series
TRIPLE MECL TO
NMOS TRANSLATOR
MC10177
Advance In:for:rnation
tr.nsI~
•
•
Max Load: 350 pF
Po = 1.0 W typ/pkg @ 5.0 MHz
•
Operating Rate: 5.0 MHz typo
(all 3 translators in use simultaneously)
•
INPUT: MECL 10,000 (differential)
•
OUTPUT: NMOS + 0.5 V VOLmax
+ 3.0 V VOHmin'
The MC10171 consists of three MECL to MOS
tors which convert MECL 10,000 logic levels to NM~
levels. It is designed for use in N·channel memory systernt
as a ReadlWrite, Data/Address driver. It may also be usee!
as a high fanout (30) MECL to TTL translator, or in oth~
applications requiring the capability to drive high capacitive loads. A separate lead from each of the three translei
tors is brought out of the package. These leads may tMi
connected to VSS or to an external capacitor (0.01 tci
0.05/lF to ground). for waveform improvement, and shor.
circuit protection. When connection is made to an external
capacitor, VSS line fluctuations due to transient currend
are also reduced.
'
'May be raised by increasing VSS.
POSITIVE LOGIC
NEGATIVE LOGIC
~
2
~
4
---l(--l-
15
=t>----l>=
14
-l(-~
13
12
--i(1
13
4
12
11
11
10
10
Vee - Gnd
= Plnl
1,16
VEE - Pin B - -5.2 Vdc i5%
VSS - Pin 9 (+5.0 Vdc or +6.0 Vdc ± 10%)
Thl, I, advance Information and 1P8Clflcetlon••r. subject to chenge without notice.
S.. Gen.rel Inform.tlon IeCtlon of pecke"ln,.
3-180
· ...
~.-
..
~~
.-....
-._
....
_~._
- ..
.. _..
, ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained.
In general test procedures are shown for
only one input and one output. The other
inputs and outputs are tested in a similar
manner.
-
15~;
14
2
13~~
12
,,~:
10
Charac: .... istic
Power Supply Drain
Negative
Positive
Output Low
Output High
Input Current
Symbol
+25oC
Min
Mo.
Unit VIHm.x VILmin VIHAmi. VILAmlik Vee Vsc
mAde
8
mAde
8
1.0
~Adc
ISSL
ISSH
9
linH
10
11
12
13
14
15
Logic "1" Output Voltage
VOH
2
Logic "0" Output Voltage
VOL
Logic "1" Threshold Voltage
VOHA
Logic "0" Threshold Voltage
VOLA
~Adc
~
3.0
4.0
3.0
4.0
50
0.5
0.6
3.0
4.0
-90
0.5
0.6
-50
-90
!
t1~2_
0.5
0.6
3.0
4.0
6.0
t14+2t14-2+
+
3.0
4.0
0.5
0.6
t15+2+
I
-1.0
0.5
0.6
ISC
~
j
3.0
4.0
~.
:t5"
::J
C
C#
CD
a.
0.05
0.05
0.05
+85"C
Mo.
96
11
13
15
Rite Time
Typ
~F
TEST VOL TAGE/CURRENT APPLIEO TO PINS LISTED eELOW,
88
88
44
ICBq
Switching Times
(350 pF Load)
Propagation Delay
+25"c
Min
::J
mAdc:t1%
'E
~
.....
.....
Output Short-Circuit Current
Max
Volts
VIHmax VILmin VIHAmin VILAmo: VEE Vsc Vss lOLl 10LZ 10H
-0.890
-1.890
-1.205
-1.500
-5.2 +5.0 +6.0 +1.0 +20 -15
~.810
-1.850
-1.105
-1.475
-5.2 +5.0 +6.0 +1.0 +20 -15
~.700
-1.825
-1.035
-1.440
-5.2 +5.0 +6.0 +1.0 +20 -15
MC10177L T.st Limits
-30"!:
.....
n0
liT...
Temper.tur.
-30"!:
Min
~
0
.....
.....
CERAMIC PACKAGE
CASE 620
'550
00
Input Leakage Current
Te..
(')
TEST VOL TAGE~URRENT VALUES
+85"C
Pin
Under
3:
LSUFFIX
-50
10.12.14 11.13.15
11.13.15 10.12,14
10
11
12
13
14
15
11
10
13
12
15
14
15
15
14
14
Vdc
Vdc
14
14
15
15
Vde
Vdc
14
14
0.5
0.6
Vde
Vd.
-90
mAdc
15
14
n.
-l,29V
-1.69V
14
14
11,13
(Vee 1
Gnd
C#
1.16
9
~
~
1.16
8
9
1,16
+
j j
10
12
,14
Vdc
Vde
Vss lOLl 10LZ IOH
j
8.11
a,13
8,15
9
1,16
8
9
1.16
1.16
~
~
9
15
15
14
14
8
8
15
15
8
1.16
1.16
9
9
1.16
1.16
9
9
9
9
1.16
1.16
1.2.16
Pul.ln Pul.Out -5,2V
15
15
15
15
14
14
15
'2+
12
14
'2_
12
14
15
10,12,14
11,13.151
9
3.5.7
1.16
110%'090%1
FaU Time
110%'090%1
Supply Source Current
1@5.0MHzl
1350 pF Loadl
#See test circuit.
ISS
9
B3
mA
I
8
I- I
9
I
- I - I- I
3,5.7
I
1.16
MC10177
(continued)
SWITCHING TIME TEST CIRCUIT
Vee
=
Gnd
Vss
=:
+6.0 Vdc
V out
Coax
:;.oo~--+-----.
TP out
CL
350 pF
Input Pulse
t+
= t- =
2.0 ±O.2 ns
(20% to 80%)
PRF:: 5.0 MHz
Duty Cycle"" 50%
~
50-ohm termination to ground lo-
cated in each scope channel input,
and 50-ohm termination to ground
on each unmonitored input.
All input and output cables to the
scope are equal 'engths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TPin to input
<
.'''J
l'
VEE:: -5.2 Vdc
pin and TP out to output pin.
SWITCHING WAVEFORMS@ 250C
Switching times afe measured after the device under test
reaches a stabilized temperature (air flow ~ 500 .fpm)
,50%
_______ ....1
t++
t+
90%
10%
Vout::::::::::::::J
V out
3-182
MECL 10,000 series
'\
BINARY COUNTER
'---------------'
MCl0178
Advance InforIDation
The MC10178 is a four-bit counter capable of divideby-two, divide-by-four, divide-by-eight or a divide-bysixteen function_
Clock inputs trigger on the positive going edge of the
clock pulse_ Set and Reset inputs override the clock,
allowing asynchronous "set" or "clear"_ Individual Set
and common Reset inputs are provided, as well as complementary outputs for the first and fourth bits_ True
outputs are available at all bits_
Po - 370 mW typ!pkg (No Load)
ftoggl. 150 MHz (typ)
TRUTH TABLE
INPUTS
R
SO
51
52
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OUTPUTS
53 C1
C2 00
L
H
L
L
4>
4>
4>
4>
4>
H
4>
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
..
......
....
..
......
......
..
01 02
L IL
H
H
J
03
LI L
H
H
No Count
No Count
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
....
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
vee1
= Pin
1
VCC2:S Pin 16
VEe - Pin 8
f/) -= Don t Care
"VIL JV1H
Clock transition from VIL to VIH
may be applied to Cl or C2 or both
for same effect.
50
00
15
11
01
12
Clock 1
C1
10
Clock 2
C2
5
01
13
01
A'
0'
C1
0'
02
4
52
6
5
A'
a
R
R • •t
51
7
01
5
C1
a
03
2
53
5
5
A'
01
A'
0'
C1
a
a
0
0
R
R
R
9
14
Qij
3
Q3
th.ll Is edvance information on • new introduction and .paciflcatlons .r. subject to change without
a.. Gen.ral Information section for packaging.
3·183
notice.
s:
ELECTRICAL CHARACTERISTICS
....o
(")
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test ta~e. after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm
resistor to -2.0 volts. Test procedures are
shown for only selected inputs and outputs.
Other inputs and outputs tested in the
11
50
00
15
7
51
01
13
....
....,
6
52
00
5
53
12
Cl
10
C2
9
A
02
4
03
2
00
14
-
03
same manner.
0o
L SUFFIX
::J
a.
CERAMIC PACKAGE
CA5E 620
::J
C
(I)
a.
TEST VOLTAGE VALUES
IVolts)
r - - - r-
(jITest
T emperatur.
-1.890
-1.205
-1.500
-5.2
+25o C
-0.810
-0.700
-1.850
-1.825
-1.105
-1.475
-1.035
-1.440
-5.2
-5.2
':'l
~
(Xl
~
I
I
I Symbol I
Power Supply Drain Current
Input Current
IE
I
'inH
l
MCl0178L Test Limits
Pin
Und...
Test
I
+25o C
_3)°C
Min
M••
VOL
Logic "1" Threshold Voltage
I
Switching Times
I
VOLA
I
14
15
14
15
-1.060
-1.060
-1.890
-1.890
3
14
15
-1.080
-1.080
-1.080
3
14
15
-0.890
-0.890
-1.675
-1.675
Min
Max
mAde
245
220
410
/JAde
j.lAdc
#lAde
/JAde
-0.890
-0.890
-1.850
-1.850
-0.980
-0.980
-0.980
-1.650
-1.650
-1.825
-1.825
-0.910
-0.910
-0.910
-1.630
-1.630
-1.630
-1.655
-1.655
-1.655
3.5
6.0
8.5
11
Rise Time (20 to 80%)
Fall Time (20 to 80%)
'H,.
15
2.5
Set Input
tll-15+
15
5.2
Reset Input
t9-15+
15
5.2
Counting Frequency
fcount
15
150
test each input applving VIL to input under te.t.
Unit
88.5
-0.810
-0.810
15
13
4
3
15
·Jn~ivtdu,"v
;
M ..
-0.960
-0.960
'12+15+
'12-13t12+4t12-3+
t15+
Clock Input··
Propagation Delav
.,
VOHA
Logic "0" Threshold Voltage
TEST VOLTAGE APPLIED TO
PINS LISTED aELOw:
+85 oe
0.5
VOH
Logic "0" Output Voltage
Typ
8
12
11
9
linL
Logic "1" Output Voltage
Min
2.5
VEE
-0.890
+8S oC
Characteristic
VIHmlx VILmin V'HAm;n IvILAmex
-30"c
-0.700
-0.700
-1.615
-1.615
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
-1.595
-1.595
-1.595
Vdc
Vdc
Vdc
n.
l
I MHz
VEE
1Veel
Gnd
-
8
1.16
-
8
8
8
1.16
1.16
1.16
1.16
VIHmllx VILmin VIHAmin VILAmlix
9
12
11
9
-
-
-
-
1 l
~' I
9
11
8
-
-
-
I
=
-
-
-
5
11
9
-
....
~
8
8
8
8
8
8
8
8
8
8
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
5
1.16
11
1.16
9
Pul.ln Pul.Out -3.2 Vdc +2.0 Vdc
12
j
15
13
4
3
15
15
8
1.16
!!
11
15
9
15
8
1.16
1.16
12
16
8
1.16
8
rt'C1 0178 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25°C
veel
= VCC2::O::
+2.0 Vdc
V out
Coe.
Coax
Pulse Generator
I
I
L
Input Pulse
t+ = t-= 2.0
± 0.2 ns
(20 to 80%)
50-ohm termination to ground 10·
cated in each scope channel input.
VEE
ti
= -3.2
Vdc
Unused outputs are tied to a 50ohm resistor to ground.
~.II input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
0.1 jtF
< 1/4 inch from TPin to input
pin and TP out to output pin.
PROPAGATION DELAY
~
_ _ _ _""",,!"""-'-_ _ _ +1.11 V
+0.31 V
t+-
t-+
3-185
LOOK-AHEAD CARRY
BLOCK
~
1_0_.0_o_0_._r_ie_s~'r
___________________M_E_C_L__
MC10179
The MC10179 device has 12 low power gatIIS
internally connected to perform the look-ahud
carry function. This device has high Z input
pulldown resistors and open emitter ouUlU.1L,
This device has applications in fast look-ahead:
adders such as with the MC10181: It can b.used also as a boolean function generator.
Po - 300 mW typ/pkg (No Lood)
fpd - 3.0 nl typ (Corry, Propogoto)
4.0 nl tVP (Oener8t11)
POSITIVE LOGIC
G3
6
P3 13
G2
J
9
P2 12
3
'----"
C n +4
..-J
~
---
~>---L
en
11
..... ~
>-
1
--G1
7
P1 10
GO
4
)
~
PO 14
PG GG C n +2"
C n +4 -
Ir
~
PO + P1 + P2 + P3
(GO + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3
(en + PO + P1) (GO + Pl) G1
(C n + PO + P1 + P2 + P3) (GO + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3
3-186
6
C n+2
VCC1 - Pin 1
VCC2 = Pin 16
VeE = Pin 8
~
EtEeJ;,UCA1io ~(ll t"IStlC&
n
.....
~MCCL IO,QOO lliri. de.,iQO.habeen
designed to meet· the de specifications
Shown in the test tab~e. after thermal equi~ibrium has been established. The circuit
is in a test socket or mounted on I printed
circuit board and transverse air flow greater
than 500 lineaf fpm is maintain$d. O~tputs
o.....
&-----'
::~
are terminated through a SO-ohm resistor
to -2.0 volts. Test procedures are shown
only for selected input5and outputs. Other
inputs and outputs are tested in a similar
manner.
II
11
i
2
[Tffft "
i~)
....,
-
3
.16
1;~6
cg
nO
:I
~.
LSUFFIX
:I
CERAMIC PACKAGE
CASE 620
c:
CD
Q.
TEST VOL TAGE VALUES
(Volts'
lilT...
Temperature
-30"1:
+25"C
+85"C
14
VIHm ..
VIL min
VIHAmin
VILAm..
VEE
-0.890
-1.205
-1.500
-5.2
-0.810
-1.890
-1.850
-1.105
-1.475
-5.2
-0.700
-1.825
-1.035
-1.440
-5.2
TEST VOLTAGE APPLlEO TO PINS LISTED BELOW,
~
.-
Ch_.:twimc
Symbol
Power Supply Or." Current
IE
Input Current
linH
00
.....
linL
Lbgic: "I" Output VOI_
Logic: "0" Outpu. VoI_
Loge "'"
Threshold Voltage
Logic "0"
Threshold VoIUge
VOH
V
VOHA
VOLA
Mox
8
4.7.11
5.9
10.13
12
14
4
2
3
2
2
2
2
2
2
2
2
Swi1iChi"l Tim.
l60nLood'
t5+3+
t5-3t11+6+
tl1-615+2+
'1>-2_
t10+6+
'1D-6t10+15+
'lD-ll>-
3
3
6
6
2
2
6
6
15
15
Rise Time f2O" to· 80%)
'6+
FaU Time 120" to 80%)
'6_
6
6
Prop-a-tion Oat8y
Unit
~
270
225
440
395
355
-1.060
-1.890
1.080
+
-0.890
-1.675
-
-1.655
05
-0.960
-1.850
-0.980
+
-
•
1.0
~
-0.810
-
-1.650
-
-
-1.630
•
5.5
t
3.5
1.1
1.1
~
VIH m..
I Vil min I
YIHA min
I
VILA max
~r
-0.890
-1.825
-0.910
1 -0.700
-1.615
T
-
I
11
8
8
4
4.5.7.9
(Vtc'
Gnd
r
1.16
1.16
1.16
1.16
Vdc
• I-If T
-
4.7.11
5.9
10.13
12
14
~Adc
Vde
VEE
8
mAde
13
5.12
5.9
5
5
9
12
13
13
5
5
5.9
1
-
-
5
13
9
12
8
1.16
• •
• •
8
1.16
+1.11 V
Pul_ln
PV_OU,
-3.2 V
+2.0 V
4.7.9
4.7.9
4.7
4.7
4.7.9
4.7.9
4.7
4.7
12.13.14
12.13.14
5
5
11
11
5
5
10
10
10
10
3
3
6
6
2
2
6
6
15
15
8
1.16
4.7
11
6
4.7
11
6
ELECTRICAL CHARACTERISTICS
s:
Each MECL 10;000 series device has been
daignBd to meet the de specifications
shown in the test table, after thermal &qui·
librium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linearfpm is maintained. Outputs
...
o...
......
n
i
6
::~
. , terminated through • 5O-ohm resistor
to -2.0 volts. Test procedures are shown
only for.lected inputsond outputs. Other
inputs and outputs are tested in 8 similar
manner.
--
3
2
1I1FTff"' ./
11
I
Lff:!;:::I::j$ ")
15
~.
7
10
4'
14
o Toot
T."..per"ur.
-3o"c
Mel0179P Test Limits
Sy_
Ch...n.tic
CfJ
.....
~
II
Power Supply Drain Current
Input Curr,nt
IE
8
linH
4.7,11
5.9
10.13
12
~
4
linL
Logic ''1'' Output Volt.
Logic "0" Output Volt.
Threshold
VOHA
I
Logic "0"
-Ul60
-1.890
-1.080
VOH
V
Logic "1"
Threshold Voltage
-3O"c
M..
Min
+
VOLA
-0.890
-1.675
-
-
-1.655
V~tege
+
Switching Tim.
1500 Loodl
Propagation Delay
15+3+
15-3_
t11+6+
-
1.0
110+15+
'1a-l!>-
'6+
6
1.1
1.1
15+2+
15-2_
110+6+
t1()"6-
Foil T .... t~·tq 80%1
+
-
3
3
6
6
2
2
6
6
15
15
1'1_6-
, Rn. Time 120.'''0 80%1
-1.850
-0.980
....
6
j
VIHma
VILmin
VIHAmin
VILA mu.
VEE
-0.890
-0.810
-0.700
-1.890
-1.850
-1.825
-1.205
-1.105
-1.035
-1.500
-5.2
-5.2
-5.2
Mu
VEE
-
-
8
-
-
4
-
-
-
-
-
-
13
5.12
5,9
5
13
5
5
5,9
-
Vil min
VIHAmin
-
12
14
-
",Adc
-
Vdc
Vde
Vde
4,5,7.9
mAde
-
270
225
440
395
355
.Ade
4,7,11
-0,810
-1.650
-
-
-
-
-
-
-
-1.075
-1.440
VILAmu
VIH mIX
Unit
T
l
58 i l72
-
-1.630
+
5.5
j
3.5
~
I:
PLASTIC PACKAGE
CASElla
+85"c
Min
-
::J
'SUFFIX
(II
Co
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
+25"c
Min
05
-0.960
8
...:;'
TEST VOLTAGE VALUES
IVoIa)
+25"c
+85"c
Pin
U_.
T...
(C
!
-0.890
-1.825
-0.910
+
-
T-0.700
-1.615
-1.595
+
5,9
10,13
+
Vde
+
ns
8
-
~
I
4,7,9
4,7,9
4,7
4,7
4,7;~
4,7,9
4,7
4,7
12,13.14
12,13,14
4,7
4,7
5
9
12
13
Pulse In
-
-
5
5
11
11
5
5
10
10
10
10
11
11
-
5
13
9
12
Pul.Out
3
3
6
6
2
2
6
6
15
15
6
6
IVee l
Gnd
1,16
1,16
! !
8
1,16
1,16
1,16
1,16
+
8
1,16
8
8
8
+
+
+
-32V
+2.0 V
8
1,16
MC10179 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25"c
vee1
= VCC2::=
+2.0 Vdc
!
V out
""t i"'"
r----- ------,
G3 51
P3 131
G2
50-ohm termination to ground lo-
cated in each scope channel input.
Pulse
Generator
Input Pulse
t+ "" t- '" 2.0 ± 0.2 ns
(20 to 80%)
Coax
I
13
91
P2 121
C n 111
Gl 71
PI 101
GO 41
PO 141
PROPAGATION DELAY
1
I
L-----ti~,~,J
VEE = -3.2 Vdc
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
V out
t
APPLICATION INFORMATION
, The MC10179 is a high speed, low power, standard
:WlECL complex function that is designed to perform the
lobk-ahead carry function. This device can be used with
:1he MC10181 4-bit ALU directly, or with the MC10180
~ual arithmetic unit in any computer, instrumentation or
'digital communication application requiring high speed
arithmetic operation on long words.
When used with the MC10181, the MC10179 performs
a second order or higher look-ahead. Figure 2 shows a 16·
bit look·ahead carry arithmetic unit. Second order carry
is valuable for longer binary words. As an example, addition of two 32-bit words is imprOVed from 30 nanoseconds
with ripple-carry techniques, to 18 nanoseconds with carry
look-ahead techniques. A block diagram of a 32-bit ALU
is shown in Figure 1. The MC10179 may also be used in
many other applications. It can, for example, reduce system package count when used to generate functions of
several variables.
FIGURE 1 - 32·BIT ALU WITH CARRY LOOK·AHEAD
3-189
3:
...o
(')
........
Bl
A6
A2
AI
B5
B2
yi
.'-r--"so
, . - - 51
r-
.
A9
iii 1'r+.
If
A080 A1 81A,282A383
en + ..
C.
Cin
..
AD 80 Al 81A282A313
en
en
M
MelDl81
.-BIT ARITHMETIC
LOGIC UNIT
52
53
F
F1
F2
F3
Gr--
•
;--5.
_51
MelDl.'
Gf--
.·BIT ARITHMETIC
LOGIC UNIT
F.
Fl
F2
F3
F.
F'
F6
F7
.,.
B"
AI.
if
LJ
B. AI . , A2 B2
J3enJ3
5•
_51
r-
e.
AI.
:::l
I
en
+. f-o
;--M
G_
MelQl8'
.-BIT ARITHMETIC
LOGIC UNIT
52
53
F.
Fl
F2
-5.
~51
•
F3
MelDl81
".BIT ARITHMETIC
LOGIC UNIT
53
F.
Fl
F2
F3
Fl.
Fl'
51
52
53
F.
Fl
F2
F3
PO
C.
F.
GO
"
Gl
II
P2
G2
MC10178
CARRY LOOKAHEAD
'3
F.
FlO
Fl'
G3
G--o
.--0
en
+ 2
en + 4
bCl.
.. ..: ,~.v:
~j,.~ ~
_
'._"
.~.,.
".".J.
"'""'Rit ... _T Riu.. LOOK-AHIADCARR~~!'...~m."~WJ.L .
Gf--
r-
-52
M
8
.....
c:
8fS
A/f
AD 80 .,8'A282 A3 83
+ •
-M
r---
8:::l
Bl.
A"
r~9'
en
•
; - - 52
•3
f-o
(D
AI'
F12
F13
MECL 10,000 series
DUAL 2-BIT
ADDER/SUBTRACTOR
MC10180
The MC 10180 is a high speed, low power general-pu rpose adder/subtractor. It is designed to be used in special
purpose adders/subtractors or in high speed multiplier
arrays. The MC10180 can be used in any piece of equipment where these operations are necessary.
Inputs for each adder are Carry-in, operand A, and
operand B; outputs are Sum, Sum, and Carry-out. The
common Select inputs serve as'a control line to invert A
for subtract, and a control line to invert B. The speed
is very fast, with Carry-in to Carry-out propagation delay
of 2.2 ns and Operand in to Sum or Carry-out propagation
delay of 4.5 ns.
Po ~ 360 mW typ/pkg (No Load)
tpd (typ)
Cin to Cout - 2.2 "'
AO
to SO - 4.6 n'
AG to C out - 4.6 n.
POSITIVE LOGIC
NEGATIVE LOGIC
FUNCTION SELECT TABLE
Vec" Pin 10
SeI,4
\lEe" Pina
Sela
Function
S" A pl",l.
I" A mlnu,'
"••
'2
t3
S " . minul A
..
S .. 0 min .... A min .. , •
'2
POlIti". Lotlc Only
/lit' .. A
(i) SII" .. A
0
SelA
e' .. B@Se1e-,elf)Stl.
s=
C gut -
f,n lA' 8' + A' j') + Cln IA'"
t,,> j'l
Cln A,' + Cln e' t A' 8'
POSTIVE LOGIC DIAGRAM - 1/201 Circuit Shown
TRUTH TABLE
...
!'UNCTION
.-.
.-.0----++-----+--1
lutTII"'CT
u. '., "",m
: "
"
"
:"
:
c,"
.IV'"1t
IUITIIACT
:"
"
3-191
OUTPUTS
"
"
.:
"
"
"
"
"
.
"
.... G ......llnformatlen .alon for pedlealngend .".xlmum ratlng.inform.h)n.
. ''" " .
.
"
"
~
.
"
..
:
"
.:
"
0..,
"
"
"
~
~
-
ELECTRICAL CHARACTERISTICS
I.
SelA
Each MECL 10,000 series has been de-
signed to meet the de specifications shown
Sela
in the test table. after thermal equilibrium
AO
'
8O
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are
Cin
terminated through a 50-ohm resistor to
La.
-2.0 volts.
~
..
It
10
12
Characteristic
I Symbol I
Power Supply Drain Current
I
IE
I"put Current
I
linH
C:'
.....l
CD
(I,.)
Pin
Under
Test
SalA
Sl~14
Sela
SI-I
C out - 1 3
Max
Min
I
I
M ••
70
86
370
220
220
290
290
220
220
370
4
5
6
7
9
10
11
12
2
3
15
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
0.5
-0.960
-0.960
-0.960
-0.810
-0.810
-0.810
VOL
2
3
15
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
Logic "1"
Threshold Voltage
VOHA
2
3
15
-1.060
-1.080
-1.080
Logic "0"
Threshold Voltage
VOLA
Switching Times
Propagation Delay
Operand Input
t5+15+
t6+15+
Carry·m Input
Select Input
Ai_Time
(20'080%1
Fall Time
-0.810
-1.850
1.205
-1.105
+8S DC
-0.700
1.825
-1.035
Min
M ••
Unit
VIH max
jJ.Adc
j
-0.890
-0.890
-0.890
-1.825
-1.825
-1.825
-0.700
-0.700
-0.700
-1.615
-1.615
-1.615
-0.910
-0.910
-0.910
-1.630
-1.630
-1.630
Vdc
•~
Vdc
Vdc
-1.595
-1.595
-1.595
•
Vdc
•
n.
Pulse In
0.9
0.9
1.1
1.1
3.6
3.6
5.8
5.8
3.8
3.7
1.1
3.9
7,9
5.7,9
4,9
7.4
7,9
3.8
1.1
3.7
1.1
3.9
7,9
-....,_..-
:..-
16
16
•
•I
8
16
8
16
~
4
-3.2 V
Pulse Out
7,9
7,9
16
•
•
4
5
4
+1.11 V
3.3
3.3
5.4
5.4
-,_._".
16
16
•
4
1.3
1.3
1.1
~-
8
8
j
7,9
7,9
4,7,9
1.0
1.0
...
(Vee l
Gnd
8
5.8
5.8
1.0
VEE
5,7,9
7,9
7,9
7,9
4,7,9
7,9
3.4
3.4
16
VILA max
VIHAmin
8
5.8
5.8
'15_
VIL min
8
1.1
1.1
15
-5.2
7,9
4,5,7,9
4,7,9
5.4
5.4
t15+
5.2
-5.2
4
5
6
7
9
10
11
12
1.3
1.3
t7+15+
t9+15+
I
VEE
VILA max
1.500
-1.475
-1.440
VIHAmin
mAde
5.8
5.8
1.3
1.3
1.0
'Indlvll\lolly~IL mlft ...."'.. u - _.'
-0.890
1.3
1.3
1.0
1.0
15
3
15
15
'4+15+
14+3+
-0.980
-0.980
-0.980
-1.655
-1.655
-1.655
2
3
15
15
15
-300 e
+25"c
VIL min
-1.890
VIH max
jJ.Adc
All
Logic "0"
Output Voltage
0
::s
....
+B5"c
Typ
'inL
VOH
Logic "1"
Output Voltage
-"
CO
0
n
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
+2SoC
-30"c
0
Volts
CHest
Temperature
MCl0180 L Test Limits
Min
-"
,
TEST VOLTAGE VALUES
81
Cin
s:
0
•
+2.0 V
16
15
15
4
4
7
9
5
15
3
15
!
5
~:j~.
...-
".~
..
~."
~
.
.
.. ---..
~.-
.... _.. ,
5°
c:
CD
C.
3:
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been de·
SoIA
signed to meet the de specifications shown
Sela
in the test table. after thermal equilibrium
AO
has been established.
The circuit is in a
.0
test socket or mounted on a printed circuit
board and transverse air flow greater than
tin
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts.
...
n
1.
L..
~
SelA
Sale
.,
S1~'4
Power Supply Drain Current
Ie
Input Current
I
'inH
~
....CO
Co)
LogiC: "'"
Output Voltage
Logic "0"
Output Voltage
. . Cin
Cout
~'3
All
VOL
2
3
15
2
3
16
VOHA
Logic: "0"
Threlhold Voltage
VOLA
-30"1:
Min
Mo.
+250 C
Min
2
3
15
2
3
15
-1.060
-1.060
-1.060
-1.890
-1.890
-1.890
0.890
-0.890
-0.890
-1.675
-1.675
-1.675
-1.080
-1.080
-1.080
0.5
0.960
-0.960
-0.960
-1.850
-1.850
-1.850
Max
70
86
370
220
220
290
290
220
220
370
-0.810
-0.700
Max
Unit
VIH rna.
IJAdc
I
-0.890
-0.890
-0.890
-1.825
-1.825
-1.825
-5.2
-5.2
VIL min
VIHAmin
VILA max
5.4
5.4
VEE
(Vee l
Gnd
8
16
16
II
Vdc
7,9
4,5,7,9
4,7,9
8
16
16
-1.615
-1.615
-1.615
Vdc
5,7,9
7,9
7,9
7,9
4,7,9
7,9
8
16
8
t
t
16
8
16
-0.910
-0.910
-0.910
-1.630
-1.630
-1.630
ClI
-0.700
-0.700
-0.700
t
~
Vdc
~
-1.595
"1.595
-1.595
Vdc
t
ns
7,9
7,9
4,7,9
t
4
5
4
4
+'.'1 V
PuI,.ln
PuI.Out
7,9
7,9
7,9
5,7,9
5
6
4
4
4,9
7,4
7
9
15
15
15
3
15
1.3
1.3
t'5+
15
1.1
3.7
7,9
115-
15
1.1
3.7
7,9
·lndividuaUy apply VIL min to pin under test.
-5.2
-1.825
-1.205
4
5
6
7
9
10
11
12
17+15+
19+15+
'4+15+
1.4+3+
-1.440
-1.890
-1.850
mAde
3.3
3.3
5.4
5.4
Select Input
-1.035
VIHAmin
TEST VOLTAGE APPLIEO TO PINS LISTEO BELOW,
Min
1.3
1.3
1.0
1.0
'6+15+
VEE
-1.105
VILA mi.
-1.500
-1.475
VIL min
",Adc
0.810
-0.810
-0.810
-1.650
-1.650
-1.650
c:
I
l
+85"1:
Typ
-0.980
-0.980
-0.980
-1.655
-1.655
-1.655
VIH max
-0.890
15
15
15
3
15
15
'5+15+
C.ry.m Input
Ri.Time
1201080%1
Fall T"ime
MCl0180P Test Limits
4
5
6
7
9
10
11
12
'inL
VOH
Logic: "'"
Threshold Voltage
Switching Times
Propagation Delav
Operand Input
I
...5'
Volts
@Test
Temperature
_30 D e
+8SoC
Test
0
0-
J
TEST VOLTAGE VALUES
S'~'
A1
+25 oC
Pin
Under
00
PLASTIC PACKAGe
CASe 648
0
10
12
I Symbol I
0
::J
11
Ch.rllCteriitic
...
, . .W,,"
!
t
t
I
~
t
-3.2 V
+2.0 V
16
.9:
MC10180 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
veel
V out
VCC2"'" +2.0 Vdc
=
r--'~'j it:-,
Coax
I
Coal(
,
SoiA
7 ,
9,
5,
6,
.0.0
41
Cin
SO
Sole
BO
C out
I
TPin
./TP
1
I
Pul,. Generator
11
I
Input Pul..
10i------'-!
t+-t;-2.0n •• 0 . 2 n . '
111
(20 to 80")
12/
Cln
50..,hm tormlnotlon to ground
catea in .ach
10'
13
-11-.- __
.~p. channa' input. L.. - - - -
All input and output cabl •• to the
cO•• ia' cabl..
be < 1/4 inch
to ground.
Vee = -3.2 Vdc
PROPAGATION DELAY
~---,-------
+1.11 V
'------+0.31 V
TP out
TP out
3·194
UnuMd outputs
connected to •
50· ohm r.,i'tor
J
x_ 0.' ~F
scope .r. aqua' 'angth. of 50-ohm
Wlr. length .hould
from TPin to input
pin and TP out to OU1put pin.
1
L -_ _- - '
out
MECL 10,000 series
4-BIT ARITHMETIC LOGIC
UNIT/FUNCTION GENERATOR
MC10181
The MCIOISI is a high-speed arithmetic logic unit
i:apable of performing 16 logic operations and 16 arithmetic operations on two four-bit words. Full internal carry
is incorporated for ripple through operation.
Arithmetic logic operations are selected by apply ing the
Bppropriate binary word to the select inputs (SO through
53) as indicated in the tables of arithmetic/logic functions.
Group carry propagate (PG) and carry generate (GG) are
provided to allow fast operations on very long words using
a second order look ahead. The internal carry is enabled by
applying a low level voltage to the mode control input (M).
When used with the MC10179, full-carry look·ahead, as
a second order look ahead block, the MC101Sl provides
high speed arithmetic operations on very long words.
POSITIVE LOGIC
NEGATIVE LOGIC
13
13
15
15
17
17
14
14
SO SI
S2 S3
S3
21
21
20
3
Fl
18
Vee1 '" Pin 1
VCC2 ::: Pin 24
20
3
Fl
18
VEE - Pin 12
19
19
16
11
F3
6
Po
8
16
4
9
22
6
11
10
4
9
8
22
5
23
23
Po - 600 mW typ/pkg (No Load)
tpel (typ): Al to F - 6.6
C n to C n +4- 3.1 nl
A 1 to Po - 6.0 n.
A 1 to GG - 4.6 nl
Al to C n +4 "" 5.0
n.
NEGATIVE LOGIC
POSITIVE LOGIC
Logic Function.
Function Select
S3
S2
51
50
M i, Hlth C- D.C.
F
H
F""A
H
F=A+B
H
L·
L·
L
H
H
F '"
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H·
=
A ...
B
Logical " ' "
F=Aei
F =
Function Select
S3 52 51 SO
P:"A
B
••
L
H
F
H
L
F =
F = IA ... 8) pi .... (A
H
L
H
H
H
H
F=A+8
F • A plus IA + BI
H
H
F-A'ee
F '" IA ... 81 plus
F ~ A minus B minus 1
H
F = IA + BI plus IA • HI
F '" A plu. IA + iiI
H
H
H
H
F a minus 1 (two'. complement)
H
F = IA • SJ minus 1
H
H
F .. (A • HI minus 1
H
H
F" A minus 1
H
H
F = A@ B
F = 8
H
H
L
L
F '" A ... B
F = Logical "0"
H
F=Aei
H
L
F"AeH
H
H
F" A
a
3·195
F '" A plus (A +
iii
F " A plus (A + BI
F = A times 2
F ",A";'1j
F = (A • BI minus 1
F "8
F:A(i)B
F = fA • BI olus (A + 81
n
H
. . . General Information section for packaging.
B
F " LOllical "0"
H
.81
A.
Arithmetic Operation
M is Low C n of LSB must be High
F
F "A minus'
",ATi
F "' A plul (A. ill
F '" A plu. IA • BI
F = A time. 2
F = IA ... HI plus a
F ;: A plus 8
F=A
H
H
F
F
Logic Functions
M is High
F
F"Aplu.O
L
H
ArlthlTWtlc Oper.tion
Mi,Low Co I, low
F~Aph.. sH
F '" A.
F=A+H
F - A plus (A .81
F = A@,)B
F = A minus B minus 1
F=H
F"A.B
F = Logical "1"
F = (A • iiI minus'
F = {A .81 plus (A + Bl
F = (A •
BI
plus A
F = minus 1 (two's complementl
F=A+S
F
H
F"'A+B
F = (A + BI plus 0
H
F=A
H
&
(A + 81 plus 0
F "A plus 0
MC10181
(continued)
i·
5313
POSITIVE
5215
LOGIC DIAGRAM
S117
5014
8020)0--
Dt
P
f----tL./
rr:C>
~2F o
I-L
~
AO 2 1
811 90--
Dt
~
,~/
~
All 8
A2
~
16~
P
,~
~
§P-
9C>--
~
~,
F2
~
~
'~,
,~./
L...-..;
83
Fl
.~
W
J
82 llC>--
~,
6 F3
"
~~
./
~
A3 10
22
./
M 23
3·196
5 C n +4
MC10181 (continued)
ELECTRICAL CHARACTERISTICS
LSUFFIX
CERAMIC PACKAGE
CASE 623
E.:h MECL 10,000 series has boon de·
signed to meet the de specifications shown
in the test table, after thermal equilibrium
... been established. The circuit is in a
test lOCket or mounted on 8 printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
PSUFFIX
PLASTIC PACKAGE
CASE 649
TEST VOLTAGE VALUES
terminated through a 50-ohm resistor to
IYoIu)
-2.0 volts.
VIHrnp
I
-0.B90
-0.810
-0.700
I,
PoMr Su9Ply O,..in Current
Input CurNnt
'inH
....
T,.
I.•
,.,.
12
14S
246
220
24'
11
"
21
22
I.•
23
•. S
pAdc
11
13
14
15
16
17
I.
1.
"
20
20
21
21
22
22
2J
YOHA
23
-1.060 -O.8SIO
-0.980
-0.810 -0.890 -0.700
-2.000 -1.67S
-',990
-0.980
-1.6&0
-1.080
L.ow~Volt8ge
-1.630
-1.665
VOLA
-T_ alllnput-outpUt combln-,ions 8CCoromli to Function Tillbil .
•• For m~d IWI!
~,
apply dll"llllfloid input I..,.. to only _
12
1.24
.1.920 -1.615
Vd,
12
-0.910
"do
Vdo
12
1,24
1.24
1,24
-1.596
12
input pin It I timl
-lOoe·
Characteristic
Propagation Delay
Rise Time, F~II Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
1,24
2.
"
200
17
HWI ThrWIold Voluge
12
14
15
17
1.
VOH
VOL
1,24
1,24
13
18
H~OutpUtYoI . . .
God
12
12
11
13
14
15
t.- Output Vol."
-5.2
-5.2
-1.825
,.,.
290
I.
-5.2
-1.475
-1.440
11
220
9
-1.500
-1.105
-1.036
I.•
"Ade
2.'
2.
21
22
2'
VILArnp
-1.205
-1.850
VILA me",
285
220
286
220
2"
17
vlHAmln
TEST VOLTAGE APPLIED TO PINS BELOW:
....
200
266
13
14
IS
I""", LelkO CUrHnt
M'.
VEE
YtLmln
-1.890
Conditions t
Min
Me.
Min
Typ
M..
Min
Mo.
Unit
AO,A l,A2,A3
AO,A 1.A2,A3
5.1
1.0
3.2
1.0
7.2
1.7
7.2
1.7
5.3
1.3
2.6' 10.4
2.6 10.4
5.4
1.3
1.1
1.0
3.1
2.0
5.0
3.0
1.1
1.0
5.4
3.2
ns
n,
2.0
2.0
1.5
4.5
4.5
3.0
6.5
6.5
3.0
5.0
2.0
7.0
7.0
5.0
7.5
7.5
5.3
10.8
10.8
5.3
ns
10
10
5.0
2.0
2.0
1.5
3.0
3.0
1.5
6.5
3.5
2.0
1.1
ns
ns
Symbol
Input
Output
t++, t-t+,t-
Cn
Cn
Cn+4
C n +4
t++, t+t-+, t-t+, t-
Cn
Fl
AO
t++, t+t-+, t--
I
I
Al
I
I
j
Fl
-
50,53
SO.S3
AO,A2,A3.C n
AO,A2,A3,C n
1.6
0.8
1.1
1.2
7.0
3.7
7.4
6.1
t+, t-
AC SWitching Characteristics
+2S0C
+85D e·
-
Propagation Delay
Rise Time, Fall Time
t++, t-t+, t-
Al
Al
Pro~tion
Delay
Rise Time, Fall Time
t++, t-t+, t-
Al
Al
PG
PG
GG
GG
Prol»9ltion Delay
Rise Time, Fall Time
t+-, t-+
t+, t-
Al
Al
C n +4
C n+4
AO,A2,A3,C n
AO,A2,A3,C n
1.7
1.0
Propagation Delay
Aise Time, Fall Time
t++, t-+
t+, t-
Bl
Bl
Fl
F1
S3,C n
S3,C n
2.7
1.2
tLogic high level (+1.11 VdcJ applied to pins listed. All other
input pins are left floating or tied to +0.31 Vdc,
VCCl = VCC2 = +2.0 Vdc, VEE = -3.2 Vdc
2.0
1.1
I
n,
j
4.5
4.0
7.0
5.0
1,2
7.3
3,1
2.0
1.5
2.0
1.0
7.0
3.8
7.7
6.3
5.0
2.0
7.0
3.0
2.0
1.0
7.8
3.2
ns
ns
11.3
5.3
3.0
1.5
8.0
3.5
11
5.0
3,0
1.5
11.9
5.3
ns
ns
·L Suffix Only
3-197
3.0
3.0
1.5
1.3
ns
ns
MC10181 (continued)
ELECTRICAL CHARACTERISTICS (continuedl
AC Switching Ch•• cteri.ics
Conditions t
PG
PG
50,53
50.53
Rise Time, FIll Time
t++, t-t+, t-
GG
GG
53. Cn
53,C n
Propagation Deily
Rise Time, Fin Time
t+-. t-+
t+, t-
Bl
Bl
Cn +4
C n +4
53,C n
S3,C n
Propagation Delay
t++. t+-
M
M
Fl
F1
-
51
SI
Fl
Fl
Al,81
Al,81
51
SI
51
51
PG
PG
Cn+4
Cn +4
A3,83
A3.83
A3,83
A3.83
51
51
GG
GG
A3.83
A3.83
Propeglltlon DeilY
Rise Time, Fill Time
Pro~gation
Delay
Rise Time, Fall Time
Symbol
Output
Input
81
Bl
Bl
Bl
Ctt.lcteriltic
1++, t-t+, t-
H.1-
Propagation Delay
Rise Time, Fall Time
t+-. t-+
Propagation Deily
t-+, t+-
Rise Time, Fall Time
Propagation DeilY
Rise Time. Fill Time
Prop8ption OellV
Rise Time. Fill Time
1+, l-
t+. lt+-, t-+
t+, t-
t+-, t-+
t+, t-
-3O"C·
Min Mox
1.6
7,7
1.0
3.6
1.7
8.2
1.4
5.2
1.8
0.9
2.4
1.1
2.5
1.0
1.7
0.8
1.6
0.9
1.6
0.8
t~ogic high lovol (+1.11 Vdcl oppliod to pin.linod. All othor
8.2
3.1
10.3
5.1
10.7
5.4
8.3
5.1
9.3
6.3
9.6
8.2
+2SoC
Min
2.0
1.1
2.0
1.5
2.0
1.0
3.0
1.5
3.0
1.5
2.0
1.1
2.0
1.1
2.0
0.8
Typ
6.0
2.0
6.0
3.0
6.0
2.0
6.5
4.0
6.5
3.0
6.0
3.0
6.0
3.0
6.0
3.0
+860 C·
M..
8.0
2.0
3.9
1.1
2.0 8.6
1.2 5.4
Mox
7.5
3.5
B.O
5.0
8.0
3.0
10
5.0
10
5.0
8.0
5.0
9.0
5.0
9.0
6.0
Min
2.0
1.0
3.0
1.5
3.0
1.5
2.0
1.1
2.0
1.0
8.7
3.2
10.8
5.3
10.8
5.4
1.9
0.8
9.7
8.6
Unit
n.
n.
ns
ns
n.
ns
n,
n.
ns
n,
8.4
5.2
ns
ns
9.9
6.2
ns
ns
n.
n.
· l Suffix Only
Of' tied 10 +0.31 Vdc.
VCCI • VCC2' +2.0 Vdc, Vee' -3.2 Vdc
input pin, ere teft fla.ting
SWITCHING TIMe TEST CIRCUIT AND WAveFORMS., 250C
veel • Vee2 • +20 Vdc:
Von
V out
PROPAGATION
DE~AY
r---~-------+1.tt
V
TPin
'------+0.31 V
P ..... Gen.r.,or
'nput Pu'"
t+
~ t~
..
2.0! 0.2
n.
(20 to 80%)
l5O-ohm termine, ion 10 .,..oulld 10
miMi in . .e" IOOpe e .... n,...1 ",put.
Unu.-d ololtPlol1i
eonnected to a
50· ohm ,"ino'
to .,..ound.
AU Input and output eeblft 10 the
lCoPe
"101" Ientitti. D' 50·."m
e,.
co. .... e.... W.,. 'entltI'I .... OUld
tM; < 1/4 'nc" f,om TPln to input
p'n Md TP out to output pin.
VEE ..
~J.2
Vdc:
3·198
TP out
MECL 10,000 series
2-BIT ARITHMETIC LOGIC
UNIT/FUNCTION GENERATOR
MC10182
Advance InforDl.atlon
The MC10182 is a high-speed arithmetic logic unit
Capable of performing 4 logic operations and 4 arithmetic operations on two 2-bit words. Full internal carry
lis incorporated for arithmetic operation.
f Arithmetic logic operations are selected by applying the
ilPPropriate binary word to the select inputs (SO and
511 as indicated in the tables of arithmetic/logic functions.
!Group carry propagate (PG) and carry generate (GG) are
provided for a second order lOok ahead carry using the
MC10179. The internal carry is enabled by applying a low
level voltage to the mode control input (M).
The MC10182 provides an alternate to the MC10181
four-bit ALU for applications not requiring the extended
functions of the MC10181 or for applications requiring
a 16-pin package. The MC10182 also differs from the
MC10181 in that Word A and Word 8 are treated equally
for addition and subtraction (A plus B, A minus B,
Bminus A).
POSITIVE LOGIC
NEGATIVE LOGIC
9
9--------------~
10
10-------,
SO
Cn
13
S1
BO
12
A1
11
81
SO
Cn
13
AO
II
VCC1 - Pin 1
VCC2 - Pln·1e
VEE-Pine
FO
4
F1
14
Pa
15
aa
3
C n +2
2
S1
AO
e
II
80
12
A1
11
B1
FO
4
F1
14
Pa
1e
aa
3
C n +2
2
M
M
Po - 575 mw typ/pkg (No Load)
tpd (typ),A1 to F - 7.5 n.
en to C n +2 - 2.7 ".
A1 to'G - 6.S n,
A 1 to 00 - 5.5 n.
A1 to C n +2" 7.0 nl
POSITIVE LOGIC
Function Select
S1
SO
L
L
H
H
L
H
L
H
NEGATIVE LOGIC
Arithmetic Operation
Logic Function
Arithmetic Operation
M i.High
M ilLow
F
F
F
F
F - A plu. B plu. Carry
F - A plu. B plUI Carry
F-A 0B
F- A 0B
F - A plul i plu. Carry
F - A tim•• 2
F-AeB
F - A plus B plu. Carry
F - A plus B plu. Carry
F - A plu. i plu. Carry
F-Atlmft2
F-A 0B
F- ~0 B
F- A e B
F-A+B
Logic Function
Mi. High
F-A+B
See Gen.,.' Inform81ion ..etlon for p.ckagln'8nd maximum r.tln81 'nforrnlltlon.
Thill, advance Inform.tlon .,d tpeclflcetlon, .r. aubJact to ch.ne- without notice.
3-199
Mi.Low
MC10182 (continued)
POSITIVE LOGIC DIAGRAM
13
10
SOO-------------~~
9
sl~------------~1~~------,
M O-------------~1
____6-+_____,
FO
Fl
12
Al
o-----~~~--~--~
81
o---~~--~
11
__~----~
3·200
3:
...o
(')
...
TRUTH TABLE
Input
M
L
L
L
I.
H
H
H
H
51
L
L
H
H
L
L
H
H
H
L
H
I.
H
L
H
50
Al Bl AO BO
w
~
o
I.
Co
Fl FO PG
L
L
L
L
L
L
L
L
L L L L
I..
I..
I..
H
L L H L
L L H H
I..
H I.. I..
I..
H I.. H
L H H I..
I..
H H H
L
L
L
H
I..
H
H
H
L
H
L
L
I..
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L L L I..
L L L H
L I.. H L
I..
I..
H H
L H L L
L H L H
L H H L
L H H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
I..
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L L
I..
H
L H
H L
H I..
H H
H H
I..
L
H
L
H
L
H
L
H
L
H
H
L
I..
H
H L
H L
H H
I..
L
L
I..
L
L
H L
H H L
H I.. H
L L H
H I.. H
I..
I.. H
L H H
H H H
I..
H L H I..
H H H L
H H I.. H
I..
L L H
H H L H
L L L H
L L H H
L H H H
I..
C n +2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2 Fl FO PG
L
L
L
L
L
L
L
H L H
L I.. H
H H L
L L H
H H I..
L H L
H H H
I..
H
H
H
H
H
H
H
H
Go
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H L H
L I.. H
I..
H H
H H H
I..
H L
H H I..
H L H
L L H
L
H
H
H
I..
H
L
L
L
H
H
H
L
I..
I..
H
L
I..
H
H
H
L
H
I..
H
H
L
H
H
L
L
H
L
H
H
L
L
I..
L
I..
I..
L
H
I..
H
L
H
H
H
H
H
H
H
H
H
H
H
I..
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
L
L
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H H
L 1..
I..
L
L
I..
H
I..
H
I..
I..
H H
I..
H H H
H I.. H I..
H H H I..
H H L H
I..
I..
L H
I..
L H
I..
H
H I..
H L
H H
H H
L H
L H
L
H
L
L H H I..
H I.. H L
L L H L
H
L
L
L
H
L
H
H L H L
H H H L
H
L
I..
I..
L
H
H
H H
I..
L
H L
H H
L L
I..
H
H H
L
I..
H
L L
I..
H
L L
'L H
H I..
H H
H L
H H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
I..
H
H
I..
Go
L
I..
I..
L
L
L
L
I..
I..
L
I..
L
L
L
L
I..
I..
L
I..
H
H
L
L
L
L
H
H
H
Ii
H
H
L
L'
L
L
H L,
H L
'+V'L
~ L
L
I..
L
k
H
H
L
L
t
L
H H L
H ~>L.
L
L
L
L
L '\:"":' L
L
L
L
L
L
L
L
'L H.
L
L
I..
L
L
L
H
L
I..
H
H L H L
L
H H H L
L
L
L
H
H
!. H
''1'" 't;!.
I..
L
H
L
L
H
H
L
H
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
H
L
H
L
H
"-
L
L
L
H
'L
L L L
LLL.L
L L L L
Ii
H
L
L
·L
L
L
I..
L
L.
:'-'
H
L
L
L L L L
'L
H
L
L
L
L
H
H
HLHI.
'L
L
H H L!
H L Ii L
H L H L
H H H L
L
L L L H
L
I.
L
L
.t
H
L
L
'1..
I..
L
L
L
H
H
L H
11..
L
H
L
H
I..
I..
H
L
I..
it,·I.
.. H,
sj H
L
'H
H
H
H
L
I..
L
I..
I..
I..
H
L L L H'
L
H
H H
L
I..
L
L
I..
H.
H
L
L
H
L L
I..
H
L
I..
I..
H H H
H
I..
H 'M '" . 1+
H i.'H:
Ii
H H H L
H L It L
L
H
H
H
H
H
H
H
H
H 'H
I..
H
H
I..
L
I..
H H H H;
I..
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H H H H
I..
H
I..
H
I.
I.
L
H
H
H
H
H
H
H
L
L
... t
L
it.
L
L
L
I.
L
L
..
L
H H H L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
iii i.
.L"
I..
'H
H
L
I..
~
H
L
H
H H H .!:'~ ,.
H L H H 'H
L L L H
L H H H
H
H
HLHH:
H
H L .... H:H
H L H H
H
H
H
L ·,"7:
L
H 'H't'-H~")' H'
H
H
L
Ii
H
I..
H
H\",.'
L
H
H
L
tl.J'L
tl ....
I..
H
H
l.
L
H I.. H H
H L H H.
H
H H
H H
"K
L
I..
!-.
H
H
H H H H
H
I..
L L H
;l.
H
H
H
H
H .H··H
H
L,
H'
H
Ii:
I-
~
.Jot,
'H -
H
I..
H
H H.
H ...: ..
H L
H L
H L
H H H L
L
H
H L
L
L
L
L
L
L
L
L
H L H L
L
L
L
L
L
L
L
H
L
'"
I..
L
I.
H
H H.1'I L
H
L L
I..
H
H L
H H
H L
H H
H
::J
!:!.
J.
H H
H Ii
H
H
L
L H H H
L
The,. outputs ara not normally used during logic operation.
H
L
Ii
L L H H
L
L
H
H
L
I.
H
H
H
H
L
L
L
L
L
L L
I..
H
L H
I..
H
I..
H
I..
H
L H
H
H
H
I..
L L L H L
L L I. N ~
L L L L' ,L
L I.. L L
L
L I.. t H
L
L L L H
Ii
I..
H H'1i
If
L H H H
H
H
L
L
H
H
H
H
I..
L
L'
"L
:.1:\
~...
L
L
I..
H
H
H
H
H
H
H
H
H I..
H I..
H H
H H
L H
H
H
I..
H
H
H
H
H
H
H
H
H
L
L
H
L
I..
H
H H
I..
H
L
H
H
L
H
~
H
I.. L ~
H H H
H H H.
H H L
H ~ L
L L H
L L H
I.
I.
L
I.
L
L L H L
L H H L
H I.. H L
H H H L
H
N
8
Cn +2 Fl FO PG GG Cn+2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2
H
H
H
H
H
H
H
H
I..
00
H
H
H
H
I..
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H ·H H
H
H
H
H
H
L
H
H
L
H
H
Ii
H
H
H
H
,t!.
H
H
Ii
H
H
.M
H
H
H
H
H
H
H
,1:i
H
H H
Ii
H
.H
H
H
H
H
H
H
H
Ii
H
H
H
H
Ii
H
::J
C
to
Q.
ELECTRICAL CHARACTERISTICS
flow greater than 500 linear fpm is maintained. Outputs are terminated through a
5O-ohm relistor to -2.0 volts.
Power Supply Drain Current
Input Currlnt
I Sy_,1
I
I
'E
linH
I
I
------
-
logiC "'" Output Voltage
Logic "0" Output Voltage
CAl
~
0
r-J
Ir
Logtc "'" Threshold Volt.
Logic "0" Threshold Voltage
Switching Times
(SO n Load)
Prepagation Delay
I
I
I
I
VOH
VOL
M..
8
-
-
7
- I
VOHA
VOLA
1"3+2+
"3+4t5+4-
'&-4t12-14+
"'-14t5+2+
"2-2t6-2"'+2+
t5-15tti+l5+
15+3_
ts-3+
'7-4+
(11)..4A.Time
I2m' to 80%)
hllTime
1_ .. _1
I .....
'4+
-
-
0.5
-<1.890
-<1.960
I -1.060
:: II
I
I I I
I I I
I I
-1890
2
3
4
14
15
-1.080
2
3
4
14
15
-
2
4
4
4
14
14
2
2
2
.2
-
-
-
-
-1.675
-1.850
-
-<1.980
-1.655
-
I
-
-
Typ
. 110
....
138
I - I::
-
I
14
15
-
I
-
2
2
Min
I -
I
I
I
+25"1:
M..
5
I
-3O"c
':!:'
13
-
-
-
......,
+25"c
VIH",..
-<1.890
-0.810
-0.700
-
-
-
-
-
-
2.7
2.7
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.0
6.5
6.5
5.5
5.5
'.0
6.0
-
-
-
-
-
-
·r
-
-
5
5.6,11
I
Vdc
-
-1.595
Vdc
-
-
-
2.5
-
-
-
-
2."
-
-
-
-
-
-
12.13
I
7,9,10
II
-1.630
-
VILmin VIHAmi VILAma VEE
-
Vdc
-
-5.2
-
-
-
-5.2
-1.0W0
-
-0.910
-
-1.475
-1.035
-
-
-
-1.105
-
Vdc
-1.815
-5.2
7
5
6
13
-
-1.825
-1.500
-
mAde:
-0.700
I I I
I I I
I
I I
n0
-1.205
VIH".a
-<1.890
-1.650
N
-1.890
-1.860
-1.825
Unk
~.810
•
•
-
....
+1Ii"C
Min
I
I
n.
-
-
6.7.9
5,10,13
7,9,10
9,10
67"
6,7,9
5,10,13
7,9,10
9,10
6.7,9
-
-
-
-
-
-
-
-
-
n.
-
-
n.
-
00
v'Lmin vIHAm", VILAma VEE
VOLTAGE APPLIED TO
PINS LISTED BELOW:
.Adc
•
4
-30"\:
-
290
350
0
Volts
-
-
15
15
3
3
TEST VOL TAGE VALUES
.T...
T. . ..mr.
MCl0112L T . . Limits
UT
...
...
(')
CERAMIC PACKAGE
CASE 620
Pin
Ct.._rmic
3:
.w"g
Each MECL 10,000 series circuit has been
designed to meet the de specifications
snown in the tast table, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed circuit board and transverse air
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
6
5
5
5
-
-
-
5
6
5
5
5
+'.11 V Pu"ln Pu'.Out
13
2
10
13
5
5
7
9,10
6
12
14
11
5
2
9
12
2
9,10
6
2
10
11
2
12
15
10
5
15
10
6
5
3
10
6
9
3
9,10
7
6,11.13
10
8
8
...
::J
1Vee)
Gnd
1,16
1,16
II
8
1,16
8
1,16
8
1,16
II
I8 I
I8 If
1.16
II
i-3.2V
8
+2.0V
"1.16
-
"
-
5
5
I •• I 81
8
,.,8
1.1'
::J
c::
It)
-
c..
MC10182 (continued)
SWITCHING TIME TEST CIRCUlf AND WAVEFORMS CiI 25°C
V out
veel '" VCC2 '" +2.0 Vdc
Coax
25 IJ.F
J
I
Coale
0.1 ~F
"/TP
Pulse Generator
50·ohm termination to ground lo-
UnuMd outputl
cated in .ach 'COp. channel Input.
connected to •
50-ohm r.,i,tor
to ground.
All input and output cabl •• to the
scope ar. equal length, of 50-ohm
cOlucial cable, Wire length thould
be < 1/4 inch from TPln to input
pin and TP out to output pin.
VEE = -3.2Vdc
PROPAGATION DELAY
r-----' '--;---- +1.11 V
+0.31 V
t+-
t-+
3·203
out
MECL 10,000 series
HEX INVERTER/BUFFER
MC10195
Advance InforInation
The MC10195 is a Hex Buffer I nverter which is built
using six EXCLUSIVE NOR gates. There is a common input
to these gates which when placed low or left open alloYfs
them to act as inverters. With the common input connected
to a high logic level the MC10195 is a hex buffer. useful
for high fanout clock driving and reducing stub lengths
on long bus lines.
TRUTH TABLE
Inputs
B
L
L
L
H
H
H
Output
H
L
L
L
H
H
POSITIVE LOGIC
A
9
5
B
JJ
'"
./
Q
2
Po "" 200 mW typ/pk 9 (No Load)
6
JJ ./
tpd "" 2.8 ns typ
3
.~
7
JJ
./
10
JJ
./
4
13
,....---.
II
JJ
12
JJ
./
14
16
Thl. i. advance InformatIon and .paclflcatlon •• r. subject to change without notice.
S. . Gener.1 I "formatIon Metlon for peckaglng.
3-204
Vee1 "" Pin 1
VCC2"" Pin 16
VEE "" PinS
'
..... _.
...~o
...c.c
ELECTRICAL CHARACTERISTICS
A
:~2
Each MECL 10,000 series circuit has been
designed to meet the dc specifkations
shown in the test table. after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
Outputs are terminated through a 5().ohm
resistor to -2.0 volts. Test procedures are
shown for only selected inputs and outputs.
Other inputs and outputs tested in the
same manner,
U1
n
6
o
~I'
:J
e.
:J
C
'Y:~ynll!l
4
CD
a.
L SUFFIX
CERAMIC PACKAGE
CASE 620
13
10
14
11
)00"
15
12
TEST VOLTAGE VALUES
Volts
w
~
o
@Test
Temperatur.
-30"1:
+25o C
U1
+850 C
Pin
Cheruteristic
I
Power Supply Drain Current
I nput Current
I
Symbol
U_,
T ...
IE
8
finH
5
9
MC10195L Test Limits
-30"1:
Min
Max
VOH
Logic "0" Output Voltage
VOL
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
VOHA
VOlA
SWitchIng TIme
(50 ohm load)
Propagation Delay
t5+2-
39
49
mAde
265
",Adc
",Ade
-0.810
-1.675
-1.850
-1.650
-1.080
-0.980
Min
Max
-0.890
-1.825
Unit
-0.700
Vdc
-1.615
Vdc
-1.595
Vdc
Vdc
-0.910
-1.630
2.8
'11-14'2+
2
!
2.0
120%'080%1
120%'080%1
-1.205
-1.500
-5.2
-0.810
-1.850
-1.105
-1.475
-5.2
-0.700
-1.825
-1.035
-1.440
-5.2
---'---r'---'---~--II !Vee 1
VIHmax
IVILminlvlHAminlvlLAmu I Vee
GncI
1.16
8
8
1.16
1.16
1,16
",Ade
-1.655
4
13
14
tl0t13+
Fall Time
+85"1:
-0.890
VEE
-1.890
9
8
1,16
1,16
8
8
1.16
1,16
pUI.lnIPul.outl-3.2Vdcl +2.0Vdc
t7-4+
Rise Time
Max
290
-1.060
-1.890
VILmin VIHAmin VILAmu
-0.890
VOLTAGE APPLIED TO PINS LISTED BELOW,
+25"1:
Typ
0.5
-0.960
linL
Logic "1" Output Voltage
Min
VIHmax
'2_
2.0
ns
8
10
11
4
13
14
5
2
I
1,16
MC10195 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2&oC
VCCI - VCC2 - +2.0 Vdc
V out
~"' ± It··"
Co ••
rA--- ---:-1
B
Q
' T P out
Input Pul ..
t+
E
t-- 2.0 t 0.2 nl
'(20 '080%)
50-ohm t.rmin.tion to ground 10'
input.
e.ted In ••ch leope
en.nn,'
UnuHd outputs .r. tied to I 50·
All Input .nd output cab I•• to the
ohm r.,I,tor to ground.
tcope .r. equII 'Ingthl of eO-ohm
:I.'
co ..
cabl.. Wire I,ngth thould
be
1/4 Inch from TPin to input
<
pin .nd TP out to output pin.
VeE - -3.2 Vdc
PROPAGATION DELAY
~
_ _ _ _ _ _ L--'---_ _ _ +1.11 V
+0.31 V
.-+
.+-
3-206
MECL 10,000 series
"
HEX "AND" GATE
\.._--------'
MC10197
Advance Int'or:rnatlon
The MCtOt97 provides a high speed hex AND
function with strobe capability. Open emitter out·
puts allow wire DRing. This high density function is
useful in control, bussing, communications in high
speed central processors, high speed peripherals,
digital communications systems, minicomputers,
and instrumentation.
TRUTH TABLE
Inputs
A
B
L
L
H
H
L
H
L
H
Output
L
L
L
H
POSITIVE LOGIC
A
9
5
B
J~
Q
2
~
Po - 200 mW typ/pkg (No Loadl
~
tpd - 2.8 nl typ
3
6
J
7
-.--...
J ./
4
10
J
13
11
J
12
->oj
J
J
..
.~
.....
./
14
;
---...
./
15
~
i
r-''' II advance Information and speciflcatlonl .r. lubject to change without notice.
S- General
VCC1 - Pin 1
VCC2 - Pin 16
VEE"Pln8
~
Information section for packaging.
3-207
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
~
A
9
B
....0(")
....CD
2
designed to meet the de specifications
shown in the test table. after thermal
equilibrium has been established. The cir-
cuit is in a test socket or mounted on a
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
Outputs are terminated throu!tl a 50-ohm
resistor to -2.0 volts. Test procedures are
shown for only .Iected inputs and outputs.
Other inputs and outputs tested in the
6
--
4
Slme manner.
10
11
12
....,
nO
3
::::I
!:t.
::::I
C
<1>
.e:
L SUFFIX
13
CERAMIC PACKAGE
CASE 620
14
15
TEST VOLTAGE VALUES
ctJ
I'.)
o
Volts
@Telt
00
VILmin VIHAmin VILAm••
VEE
-30OC
-0.890
-1.890
-1.205
-1.500
-5.2
+2SoC
-0.810
-1.850
-1.105
-1.475
-5.2
+8SoC
-0.700
-1.825
-1.035
-1.440
-5.2
Temperature
1----::::;;::--,--=:.::::';;:'-=-=="'·'l·ir----+S::5:;OC==----,,----t1
Min
I
Max
VIHrnax
VOLTAGE APPLIED TO PINS LISTED BELOW,
Unit J VIHm.x
I VILminl VIHAminlVILAmax I VEE
mAde
8
,lJAdc
/JAde
8
j.lAdc
-0.890 I -0.700
I Vdc
-1.825 1.1.615
-0.910
-1.595
Vdc
Vdc
Vdc
8
5,9
Gnd
1.16
1.16
1.16
1,16
1,16
8
1,16
1,16
8
1.16
8
9
9
(Vee I
1.11Vdcl pUI.lnIPul.outl-3.2VdCI +2.0Vdc
ns
9
j
9
9
j j
l
L,.. _,
MC10197 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
veCl - VeC2' +2.0 Vdc
"., t
Coal(
9
5
I 1""
8
+1.11 V
o-r-o
O.l1'F
1
± 0.2 os
J
12
I
<
Wire length should
1/4. inch from TP in to input
pin and TP out to output pIn
4
I
I
.to.11 input and output cables to the
scope are equal lengths of 50-ohm
3
I
I
13
I
14
I
I
c:ated in each scope channel input
l
I
~~
11
50-ohm termination to ground 10
coaxial cable.
J
J
(20 to 80%)
be
I
1
I
Input Pulse
t+ = t-= 2.0
Con;
I
I
10
V out
I
I
I
Pulse Generator
2SoC
Ar-----.,a
I
6
@
-~
15
L _ _ _ _ _ ...J
!lo.l1'F
VEE'" -3.2 Vdc
PROPAGATION DELAY
V out AND
3-209
Unused outputs are tied to a 50·
ohm resistor to ground.
MEeL 10,000 series
HIGH SPEED DUAL 3-INPUT
3·0UTPUT "OR" GATE
MC10210
POSITIVE LOGIC
NEGATIVE LOGIC
~~2
7
3
4
1~~1213
1~~1213
11
11
14
14
VCCI
VCC2
z
D
Pin 1, 15
·Pln 16
The MC10210 is designed to drive up to six
transmission lines simultaneously. The multiple
outputs of this device also allow the wire "OR"·
ing of several levels of gating for minimization
of gate and pack age cou nt.
,
The ability to control three parallel lines wi~
minimum propagation delay from a single point
makes the MC10210 particularly useful in clod[
distribution applications where minimum clod[
skew is desired.
The MC 10210 is a higher speed version cit
the MC10ll0. It is a pin·for-pin replacemenit
for the device. Three VCC pins are provided
and each one shou Id be used.
Po = 160 mW tvp/pkg (No Load)
tpd - 1.5 nl typ (All Output Loaded)
VEE "" Pin8
Output RIM and Fell Time: (All Outputs Loaded)
- 1.6 ns
(20% to 80%)
tvp
CIRCUIT SCHEMATIC
16
VCC2
VCCI
1
50----------------,
6
, - - - - . . - - -.....- - _ 0
0---------..,
.........---+---+----0 4
"----+----03
2
110--+______________- - ,
10 0--+--------,
VCCI
,----.....---.,---0 15
~----~---+--_o14
9
~--__II__-o
8 VEe
See Gen.,el I "formation ..ction for packaging_
3·210
13
12
~Cl0210 (continued)
EJ,.ECTRICAL CHARACTERISTICS
·beh MECL 10,000 ..rias circuit ha. been
dlligned to ....t the de opacification. shown
in the tast table, after thermal equilibrium
..... been established. The circuit is in a
~~2
'te!It lOCket or mounted on a printed circuit
4
7
160wd end transverse air flow greater than
Pow. SUpply
~rain
Currlnt
u.""
T_
ItipUtCurfWIt
linH
5,6,1
linL
5,8,7
L."I"
OutputVolrage
"OH
LOIic"O"
Output Volt.
VOHA
LagIc"O"
l'ttt-tItIoldVolt.
VOLA
SWitching Timn
15O--oIam1OMt1
'~ionD.,1V
....
..."1:
Min
Typ
VILmin
~1.890
VIHAmin
-1.205
VILA IMlI
~.890
-1.500
-5.2
·21"1:
..."1:
-OSlO
-0.100
-1.850
-, 825
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
U ••
VIHm_
...0.890
...0.890
...0.890
-1.675
-1.675
-1.675
-UJ60
-1.(160
-1060
-1.890
-1.890
-1.890
-1.080
-1.080
-1.080
0.'
-0.960
Ma
~0.810
-1650
-1.650
-1.650
-1.850
VIHAm ....
YILAtnP
"EE
...0.890
...0.890
-0.890
-1.825
-1.825
-1.825
...0.700
...0.700
...0.700
-1.615
-1.615
-1.615
-1630
-1630
-1.630
I.S
-1.595
-'.595
-1.595
"do
Vdo
Vdo
V",
"do
Vdo
"do
"do
Vdo
Vdo
'u'.'n
2."
(Vee'
Gnd
1,15,'6
1,15.16
1,15,16
1,15,.16
1,15.16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1.15,18
1,15,1&
1,15,16
"Ado
-0.910
-0.910
...0.910
-1.655
-1.655
-1.655
1.0
VILmin
mAdo
"Ado
-0.810
-0.810
-<>.960
-0.960
-1.850
-1.850
-0.980
-0.980
-a.980
...,.
VEE
TEST VOLTAGE APPLIED TO PINS LISTED BELOW.:
_oc
M'.
JII
410
t6_2_
,
....
I
VIH"'b
-3O"c
TemperetuN
-. . .C
VOL
LotIc"I"
Ttlr.....o!dVolt. .
(Volta!
n ..
14
M ..
•
'E
TEST VOLTAGE VALUES
11
MC,02,OL Tal Limiu
Pin
Symbol
3
1~~1219
&00 linear fpm is maintained. Outputs are
_",in8ted through 8 5().ohm resistor to
-2.0 volts. Test procedures are shown for
only one get.. The other get. is tested in
the ame manner.
C~iI:
LSUFFIX
CERAMIC PACKAGE
CASE 620
' . . . Out
-3.2 V
+2.0 V
S
1,15,16
'"''
.....
...'2.
..' ..J-
·t
t5_ ....
.,.Tw.
(20"10%1
F.,T"",
120.11*1
'3•
'2-
'3-
-,lIdhoidlHHy.t ~h input ut.ing the pin conn8Ctionllihown.
TIME
CIRCUIT
l ; r -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _SWITCHING
______
_ _TEST
___
_ _ _ _AND
_ _ WAVEFORMS
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
"
"
Coax
,----+1.11 V
Input
- - - - - +0.31 V
Pul .. Generator
I
I
r=tt'
:
e.
, ,
,,
~-
Input Pulse
t+ _ t- _ 1.5.:!:. 0.2 ns
(20 to 80%)
1
(~
- - __'_'.0 m , ••0'
.L --
Vout
-r;:I
;1
cated in each lcope channel input
=:-<.
:
Unu ..d outputs connected to
a 50-ohm ,esistor to ground.
x_ 0.1 ",F
All Input and output cable. to the
~r:.~i:a~~;egtl:~;:h5!-:~~
VeE
~
-3.2 Vdc
be
1/4 Inch from TPln to Input
pin end TPout to output pin.
3·211
MECL 10,000 series
HIGH SPEED DUAL 3-INPUT
3-0UTPUT "NOR" GATE
MC10211
POSITIVE LOGIC
,g ~
.
The MC 10211 is designed to drive up to s.ix
transmission lines simultaneously. The multiple
outputs of this device also allow the wire "OR~(
ing of several levels of gating for minimization
of gate and package count.
The ability to control three parallel lines with
minimum propagation delay from a single point
makes the MC 10211 particularly useful in clook
distribution applications where minimum clock
skew is desired.
.
NEGATIVE LOGIC
'2
13
14
~
1~
'2
13
14
11
11
Po
= 75
mW typ/gate (Outputs Open)
tpd "" 1.5 ns typ (All Outpuu Loaded)
Output Rise and FeU Time: (All Outputs Loaded)
VCCI
= 1. 15
VCC2 = 16
VEE = 8
= 1.5 ns typ 120% to 80%)
CIRCUIT SCHEMATIC
16
VCC2
VCCI
r--'--~-_o
6
1
0--------,
"'---+--+----0 4
---+---03
110--+_ _ _ _ _ _ _ _-,
VCCI
100--+------,
.--~---~---O15
'---r--~-_o14
9
"---+--013
12
See General I nformation section for packaging.
3-212
: MC10211 (continued)
",m'
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications shown
in the test tabli, after thermal equilibrium
ha been established. The circuit is in a
test lOCket or mounted on a printed circuit
~d and transverse air flow greater than
500 linear fpm is maintained. Outputs are
5
~
terminated through a 50-oh m resistor to
1~
-2.0 volts. Test procedures are shown for
11
only one gate. The other gate is tested in
the same manner.
4
~ ::
T_
T"
"
LogIC"'"
OulputVo1tage
IInH
5.6.1
r,nL
5.6,7
VOH
2
3
,
4
Logie "0"
Va'
OulputVoilage
3
L09IC'"'"
VOHA
Threshold Vollage
..o.890
-1.675
-1675
-1675
-LOBO
-lOBO
-1.080
'LoglC "0"
(Volts!
I Vil min
VIHA min
VILA m ..
-0.890
-1.890
-1.205
+2SoC
-0.810
-1105
+8SoC
-0.700
-1.850
-1.825
-1.500
-1.475
-1440
r',",""a1u ••
_lOGe
VIH m ••
-1.035
ViH m..
38
ViL min
ViHA min
-'850
-1850
-1.850
-0980
-0.980
-0.980
..o.890
..o.890
-0890
-1.825
-1.825
-1.825
..o910
..o.910
-0910
-1.630
-1.630
-1630
1.0
1.'
120·to.w1
-'595
-1.595
-1.595
"'3_
120to.w1
'4_
·Ind.... idu.lly ,., each Inpul USIng Ihe P'" eonnKllons shown
SWITCHING TIME TEST CIRCUIT lIND WAVEFORMS@ 25°C
VCC 1 = VCC2
+2.0 Vdc
Coax
, , if t""
r- - -
,
Input
V out
,_.
- --,
r--4'------~
I
V out
Pulse Generator
Input Pulse
t+ t- "" 1.5 ±. 0.2 ns
(20 to 80')6)
:E
5O-ohm termination to ground located in each scope channel input.
All Input and output cables to the
ICOpe ar. aqual langths of 50-ohm
cOIIxl.1 cabl.. Wire length should
be < 1/4 Inch from TPin to input
pin end TP out to output pin.
i-A
~
Unused outputs connected to
50-ohm resistor to ground.
8
C_-!1-;'"
I
-S.2
-52
VEE
iVec l
Gnd
1.15.16
Pul_Out
+2.0 V
1.15.16
2.'
'3'
F"ITime
-52
1.15.16
1.15.16
1.15.16
1.15.16
1.15.16
1.15.16
1.15,16
1.15.16
1.15.16
1.15.16
1.15,16
1.15.16
".
'4.
Ri_Tome
VEE
1.15.16
1,15,16
-0.700
-0700
-0.700
-1.615
-1.615
-1.615
Pulse'n
15+2_
15-2115+315-3+
'51-415_401-
IN.
pAde
-0810
-0810
-0.810
-1.650
-1.650
-1650
SWItchIng TImes
(50-ohm load)
ProplJllltion Delay
ViLA
mAde
0'
-0.960
-0.960
-0.960
I
TEST VOLTAGE APPLi£D TO PiNS LiSTED BELOW,
M..
-1655
-'655
-1655
VOLA
Threshold Voltage
LSUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
410
-0.890
-0.890
-1.060
-1.060
-1.060
-1.890
-1.890
_'.890
"
~\ i
14
30
inputCurrenl
, I;
-lOoe
Undltr
Symbol
2
3
MCl0211L Test Limit.
Pin
CharecteristlC
~
I
VEE = -3.2 Vdc
3·213
MECL 10,000 series
HIGH SPEED DUAL 3-INPUT
3-0UTPUTOR/NOR GATE
MC10212
Advance InforIIlation
POSITIVE LOGIC
The MC10212 is designed to drive up to six
transmission lines simultaneously. The multipl~
outputs of this device also allow the wire "OR"-'
ing of several levels of gating for minimiiatiOn
of gate and package count.
The ability to control three parallel lines with
minimum propagation delay from a single point
makes the MC10212 particularly useful in clock"
distribution applications where minimum clock
'
,
skew is desired.
NEGATIVE LOGIC
5~:
6
2
7
9
10
11
~
'2
13
14
~
1~
'2
13
14
11
vee1
=
1. 15
Po ==160mW typ/pkg (No Load)
VCC2: 16
Vee: 8
tpd"" 1.5 n. typ (All Outputs Loadad)
Output Rise and Fall Time: (All Output. Loaded)
=
1.5 ns typ (20% to 80%)
CIRCUIT SCHEMATIC
16
6
VCC2
<>-------,
......--4--+---0 2
5 <>-+_--f
........-+--<>3
4
Ilo--+_ _ _ _ _ _ _
~
10o--+---~
VCCI
15
......_-1---+---<> 12
9
......- - 1 - - 0 1 3
8 Vee
Thi, i, edwnce information and .peclfleatlon•• re ,ubject to cheng. without notice.
S.. G.n .... ' Information ..ctktn for packaging.
3-214
14
3:
ELECTRICAL CHARACTERISTICS
E.,h MECL 10.000 _ies circuit h.. been
designed to !Met thode opecific.tions shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted,on a printed circuit
board and transverse air flow greater than
500 line. fpm is maintained. Outputs are
~
-
~:
7~2
terminated through a 50-ohm resistor to
9
-2.0 volts. Test procedures are shown for
only one gate. The other gate is tested in
10
11
~
'2
13
14
n
.....
o
N
LSUFFIX
....N
CERAMIC PACKAGE
CASE 620
nO
:::I
~.
:::I
C
(1)
the same manner.
Q.
TEST VOLTAGE VALUES
(Voltsl
til Test
Tempet'ature
w
~
.....
Characteristic
Symbol
Power SupplV Drain Current
Ie
Input Current
U1
'inH
5,6,7
'inL
5,6,7
logic "'"
Output Voltage
VOH
logic "0"
Output Voltage
VOL
_lODe
Min
VOHA
logic "0"
Threshold Voltage
VOLA
Min
TV.
30
Max
Min
-0.890
+25o c
+85·C
-0.810
-0.700
-1.890
·1.850
-1.105
-1.825
-1.035
Unit
V,H max
38
-1.890
-1.890
-1.890
I
-0.890
-0.890
-0.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-0.980
-0.980
-0.980
-1.080
-1.080
-1.080
I
-0.810
-0.810
-0.810
-1.650
-1.650
-1.650
-0.960
-0.960
-0.960
-0.890
-0.890
-0.890
-1.825
-1.825
-1.825
-0.700
-0.700
-0.100
-1.615
-1.615
":'.615
-0.910
-0.910
-0.910
-1.655
-1.655
-1.655
-1.630
-1.630
-1.630
VIHA
1 VILA mul
Vee
-1.500
-5.2
-1.205
I
I
-1.475
-1.440
I
I
-5.2
-5.2
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
M_
405
2
Threshold Voltage
-30"1'
+85o C
+25OC
Max
0.5
-1.060
-1.060
-1.060
3
logiC "'"
VILmin
MC10212L Test Limits
Pin
Under
Tnt
min
VIHmal(
-1.595
-1.595
-1.595
mAde
#JAde
!lAde
Vde
Vde
Vde
Vdc
Vde
Vdc
Vdc
Vde
Vdc
Vdc
Vdc
Vdc
I
V'L min
I
V'HA min
I
IVcCI
VeE
V,LA max
Gnd
1,15,16
5,6,7+
1.15,16
5.6.7+
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
1,15,16
8
8
8
1,15,16
1,15,16
1,15,16
Switching Times
Pulse In
(50-ohm load)
Propagation DeiaV
Rise Time
1201080%.
15+2+
t5-215+315-3+
15+415-4+
'2+
'3+
'4+
Fall Time
120'.80%1
'2.
'3_
'4_
-Individuallv test each input using the pin connections shown.
I
1.5
Pul. Out
I
-3.2 V I
+2.0 V
I
1,15,16
MC10212 (continued)
SWITCHING TIME TEST CIRCUIT PND WAVEFORMS@ 2SoC
Vee, = Vee2
V out
+2.0 Vdc
Coax
!
''-' £ ±" " ""
+0.31 V
±.10mV
r'- - - - ---,
,-+-_----J
I
Input
I
~--+-----+I~~_~~
Pulse Generator
Input Puis.
t+ '"' t- "" 2.0 ±. 0.2 ns
120 to 80%1
~
I
I
I
I
I
I
Unused outputs connected to
a 50-ohm resistor to ground. - - V out
I
50-ohm termination
to ground
located in each scope channel
input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TP in to input
pin and TP out to output pin.
<
C_
--fl-'"'"
VEE
= -3.2
Vdc
3-216
MECL 10,000 series
HIGH SPEED TRIPLE
LINE RECEIVER
MC10216
The MC10216 is a high speed triple differential
amplifier designed for use in sensing differential signals
over long lines. The basa bias supply (VSS) is made
available at pin 11 to make the device usaful as a
Schmitt trigger, or in other applications where a stable
reference voltage is necessary.
Active current sources provide the MC10216 with
POSITIVE LOGIC
excellent common mode noise rejection. If any ampli-
NEGATIVE LOGIC
4~2
fier in 8 package is not used, one input of that amplifier
must be connected to Vee (pin 11) to prevent upsetting
the current source bias network.
Complementary outputs are provided to allow driving twisted pair lines, to enable cascading of several
4~2
5~3
5~3
9~6
10~7
9~6
10~7
12~14
12~14
amplifiers in 8 chain, or simplv to provide complement
outputs of the input logic function.
13~15
~11
13~15
~11
Vaa
Vaa
vee1
Pin 1
VCC2 = Pin 16
VEE::: Pin 8
=
Po
=
100 mW typ/pkg (No Load)
tpd = 1.8 ns typ (Single ended)
= 1.5 nstyp (Oifferential)
CIRCUIT SCHEMATIC
3
6
VCC1
14
15
1
5
4
9
13
10
SM General Information section for packaging.
3·217
VCC2
16
12
..s:
..
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
desigred to meet the de specifications shown
-
4~2
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are
5~3
9~6
10~7
12~14
lJ~15
L~11
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
VB B
only one gate. The other gates are tested
in the same manner.
(")
o
L SUFFIX
N
CERAMIC PACKAGE
CASE 620
en
8
::J
....
:i"
c:
<11
3:
TEST VOLTAGE VALUES
(Volts)
lilT ...
Tanper.ture
...,W
... I
CO
Pm
Ch.rKte,istic
Symbol
Power Supply Drain Current
'E
linH
Input Current
IC80
Undor
TOft
MCl0218L Test Limits
+2SoC
-3O"c
M'"
Mo.
Min
20
•
•
9
High Output Voltage
VOH
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
low Output Voltage
VOL
-'.890
-1.890
-'.675
-'.675
-1.850
-1.850
High Threshold Voltage
VOHA
-1.080
-1.080
Low Threshold Voltage
VOLA
Ref.rence Voltage
V8S
Ty.
11
-1.420
Mo.
-'.500
VBB
From
+25o C
-0.810
-1.850
-1.105
-1.475
Pin
+85°C
-0.700
-1.825
-1.035
-1.440
11
M ••
Unit
Ri.Time
120% to 80%1
FatlTime
I";:
2
2
3
3
'3+
'2'3-Deily i. 1.5 ns when inputs •• driwn diHerwntially
Dttey II 1.8 ns when inputt •• driven tingle ended.
(~toemr.1
VIHmax
4,9,12
VILmin
VIHAmin
1VCCI
Gnd
1,16
9,'2
5,10,13
9,'2
','2
9,12
4
5,'0,'3
5,10,13
5,10,13
1,16
1,16
4
9,'2
9,12
5,10,13
5,10,13
','6
','6
9,12
5,10,13
5,10,13
-1.230
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
4
9,12
-1.825
-1.825
-1.615
-1.615
Vdc
Vdc
9,12
-1.295
Vdc
Vd,
-'595
-1.595
Vd,
Vdc
-1.150
Vdc
•
5,1~,13
9,'2
j
2
3
1,16
1.16
','6
1,16
8
8
1,16
1.16
1,16
-3.2
Vd,
+2.0
Vdc
1,16
5,'0,'3
Pu. . Out
5, '0,'3
j
1,16
8,'
8,9
5,'0,'3
5,10,13
9,12
2.5
j •~ j
1.5
VEE
/-lAde
/-lAde
-0.910
-0.910
1.8·
VBB
5,10,13
/-lAde
-1.630
-1.630
1.0
VILA max
'.0
'.0
Pullt ...
t4+2+
'4-2'4+3-
-5.2
~
mAde
Switching Tim..
(SO-ohm LOoecU
Propagation Delay
-:H-1
TEST VOLTAGE APPLIED TO PINS BELOW:
+SSoC
Min
VEE
25
-0.8'0
-0.8'0
-1.650
-1.650
-'.350
-'.205
VIH max
115
-0.980
-0.980
-1.655
-'.655
-1.280
VILA max
-0.890
VILmin
-1.890
VIHAmin
-3O"c
B
j j j
~--
._.--_.-..-
~ftECTR1CAt·eHARAtTERts'Tit:s'
. Each IIIIECL 10,000 series circuit h_ been
designed to meet the de specifications shown
3:
.-
(')
•
:~:
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a pr-inted circuit
board and transverse air flow greater than
500 'inear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
9~6
10
7
12~14
13~'5
~"
V BB
in the same manner.
2.-
PSUFFIX
PLASTIC PACKAGE
CASE 648
en
8
...S'
::J
c:
CD
.e:
TEST VOLTAGE VALUES
I
(Voltsl
i;>T...
Temper"uN
-lII"c
to)
N
....
to
Characteristic
s"mboI
Power Supplv Drain Current
'E
I "put Current
linH
'C80
High Output Voltage
low Output Voltage
VOH
VOL
Pin
Undo,
Tnt
-3O"c
+2SoC
Min
Mo.
8
4
4
9
-
-
2
3
-1.()60
-1.060
2
3
-1.890
-
-
Min
-0.960
-0.960
-0.100
25
115
1.0
10
-
mAde
..
J.lAde
J.lAde
.uAde
-1.890
-
-0.980
-0.980
-
VOHA
2
3
-
-1.655
-1.655
-
Reference Voltage
SWitchi .... Times
Vaa
2
3
11
-1.420
-1.280
-1.350
t.t+2+
'4-2'4+3'4-3+
2
2
3
3
-
-
1.0
I _ m l.... '
-
-
-
-
-
-
j
-
-
1.8'
~
1.5
!
-0.890
-0.890
-
-0.910
-0.910
-1.630
-l.630
-
-1.230
2.5
j
Mo-
-
-0.810
-0.810
-1.650
-1.650
-1.825
-1.825
-0.700
-0.700
-1.615
-1.615
Unit
V'Lmin
4
9,12
9,12
4.12
Vdc
Vdc
4
9.12
Vdc
Vdc
9.12
4
Vdc
Vdc
Vdc
Vdc
9,12
-1.295
-1.150
Vdc
-
-
-
-
-
-
n.
j
9.12
4
4
9.12
9.12
-
-
-1.825
VIH max
4,9.12
-1.595
-1.595
-
-1.850
VIHA min
VILA max
Vaa
VEE
-1.205
-1.105
-1.035
-1.500
F,om
-1.475
Pin
-1.440
11
~
~
-5.2
IVce'
20
-
VOLA
+BS"c
Min
-
VILmin
-1,890
TEST VOLTAGE APPLIED TO PINS BELOW:
M ••
-1.850
-1.850
Low Threshold Voltage
2
'2+
3
'3+
F8IITime
2
'2_
(20%1080%)
3
'3Oelav is 1.5 n. when inpu1s,,-. driven different.. Uy
O".y is 1.8 ns wt-n inputs ..e driven single ended
+SSoC
Ty.
-0.890
-0.890
-1.675
-1.675
-LOBO
-LOBO
Ri .. Time
(20% to 80%)
-0.890
-0.810
MC1021IP Test Limits
High Threshold Voltage
Propegltion Oelav
VIHmax
+25o C
9,12
-
V,HA min
4
-
9,12
-
-
-
-
-
4
Pul.ln
4
j
V,LA max
--
_.
4
4
-
Vaa
VEE
5,10,13
5,10,13
8
Gnd
1,16
8
8,4
8,9
-1.16
1.16
5.10.13
5,10.13
5.10.13
5.10.13
5,10.13
5,10.13
8
8
1.16
1.16
8
1.16
1.16
1.16
1.16
5,10,13
5,10,13
8
5.10.13
5.10.13
5.10,13
Pul.Out
2
2
3
3
2
3
2
3
5.10,13
8
8
8
1,16
8
8
1.16
1.16
1.16
-3.2
+2.0
Vdc
Vdc
8
1,16
j j j
MC10216 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
V out
+2.0 Vdc
Coax
Coax
Input pulse
t+
:II
t- '"' 1,5 ±. 0.2 ns
(20 to 80%)
n
I
I
I
I
I
I
L_-
lO.l/lF
I
-: 1 /l F
v:e
= -3.2 Vdc
50-ohm termination to ground lo-
Unused outputs connected to
cated In .ach scope channel input.
a 50-ohm resistor to ground.
All input and output cabl., to the
scope are equal lengths of 50-ohm
One input from each gate must
C08ICiai cabl.. Wire length should
be < 1/4 inch from TPin to input
be tied to Vee (Pin 11) during testing.
pin and TP out to output pin.
PROPAGATION DELAY
3-220
MEeL 10,000 series
HIGH SPEED DUAL TYPE D
MASTER-SLAVE FLIP-FLOP
MC10231
The MC10231 is a dual master-slave type 0
flip-flop. Asynchronous Set (5) and Reset (R)
override Clock(Cc)and Clock Enable (CE) inputs_
Each flip-flop may be clocked separately by
holding the common clock in the low state and
using' the enable inputs for the clocking function_
If the common clock is to be used to clock the
flip-flop, the Clock Enable inputs must be in the
low state_ In this case. the enable inputs perform
the'function of controlling the common clock_
The output states of the flip-flop change on
the positive transition of the clock _ A change
in the information present at the data (0) input
wi II 'not affect the output information at any
other time due to master slave construction.
Input pulldown resistors eliminate the need
to tie unused inputs to VEE:- Output rise and fall
times allow high frequency operation over 200
R-5 TRUTH TABLE
n +l
R
S
L
L
an
H
Q
L
H
H
L
L
H
H
N.D.
= Not
N.D.
Defined
CLOCKED TRUTH TABLE
C
0
Qn+l
L
q,
an
H
L
L
H
H
H
MHL
cP "" Don't Care
e = Ce + ee·
.
A clock H is 8 clock transition
from 8 low to a high state.
Po"" 270 mW typ/pkg (No Load)
f TOg
POSITIVE LOGIC
S1
01
GEl
225 MHz typ
NEGATIVE LOGIC
R1
5--------------'
7 - - - - - - - -....
~
2
01
6
eEl
5------------~
7 ---------""'I
6
3
R1
3
51
4--~----------~
ee g
R2
4 __~----------~
ee g
13--~----------,
52
13--~----------,
14
14
CE 2 11 ------..___'
02 10--------.....
C E 2 11 -----...__. /
15
02 10
R2
S212--------------~
vee1
== P n
1
VCC2=Pn 16
VEE = P n 8
s-,. General I nformation section for packaging.
3-221
--------..J::ot
12--------------~
15
ELECTRICAL CHARACTERISTICS
SI
Each MECL 10,000 series circuit has been
designa:d to meet thedc specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test prOCedures are shown for
only one input, or for one set of input con·
ditions. Other inputs tested in the same
manner.
01
CEI
eh.rKt.,istic
Input Current
Input Leakage Current
~
I\.)
I\.)
logic ",."
Threshold VQltage
logic "0"
Threshold Voltage
AI. 4~
CC~
"""§)=
CE2
"
0210----
-
-
-
-
-
-
-
-
0.5
0.5
VOH
2
2t
VOL
3
3'
2
2'
3
3'
-1.060
-1.060
-1.890
-1.890
-0.890
-0.890
-1.675
-1.675
-0.960
-0.960
-1.850
-1.850
-LOBO
-1.080
-
0.980
-0.98Q
-1.655
-1.655
-
VOLA
Q2
15
OTost
T........tur.
_30o e
MC10231L Test Limits
+250e
_30o e
-
VOHA
14
+25"<:
+85oe
8
4
5
6
7
9
4,5,·
6,7,9·
linL
02
5212
Min
Co)
Logic "1'
Output Voltage
logic "0"
Output Voltage
3·
Ma.
'E
linH
-
-
-
Ty.
52
-
t9+2t6+2+
2
2
1.4
1.4
Rise Time 120 to 80%'
'2+
2
0.9
3.4
3.4
3.3
Fall Time (20 to 80%)
'2-
2
0.9
3.3
1.0
1.0
Min
65
-
410
410
220
220
290
-
-
-
-0.810 0.890 -0.700
-0.810 -0.890 -0.700
-1.650 -1.825 -1.615
-1.650 -1.825 -1.615
-
-0.910
-0.910
-1.630
-1.630
-
1.5
1.5
t5+2+
t'2+15+
t5+3+
t'2+14-
·2
15
3
14
1.0
3.4
1.1
t4+2t'3+15_
t4+3t13+14+
-
p,.opagation Delay
Reset Input
P,.opagation Delay
Setup Time
tSetup
Hold Ti,!,e
tHold
2
15
3
14
7
7
T~.
ITog
2
Ff'equency 1M•• )
+ + ~
!l
1.1
+
-1.595
-1.595
3.3
3.3
1.5
1.5
3.1
3.1
1.0
3.7
3.7
3.5
1.0
3.5
1.1
3.7
-
-1.850
-1.105 ..
-1.475
-1.825
-1.035
-1.440
Unit
V,Hm••
mAde
-
-
",Ade
4
5
6
7
9
-
!
",Adc
J.lAde
Vdc
Vdc
V'Lmin
-
5
7
Vdc
Vdc
5
7
Vdc
Vdc
Vdc
Vdc
-
-
-
--
_'ied
: ,,", •
~
7
nS
7
-
3.3
! t
-
.-
200
~,_~._
n- VIH ....
. __ '
-
9
250'
.___ .
........
to ,fie ~ input Ipin61
'. _'.'
ns
ns
200
200
_ _-
;,;:"""', : _,,,,,,,-
-v.••, .......
V'LAm••
-1.500
CD
VEE
0-
-5.2
.-5.2
-5.2
6
-
+
ns
9
ns
MHz
..
VIHAmin
V,LA mi.
VEE
0'" "
-
-
8
8
1',16
1,16
-
-
! !
-
-
+
+
t:
-0.700
+ +
-
VIHAmin
-1.205
-0.810
+
-
...3'
IVolts'
-0.890
6
0.75
tobo _ _ . _ pujOl ' - boon
.' ,~ .. , : "'.~".. .,__ '''. _':, ',_, :.._'. .
3.3
1.0
.. ....
~~_"'!y,~~,i~~~;~~VLL·miJt'~oJ~,,_......... _.......__ ,
J\.
-
8::J
IVee
-
-
W
VOLTAGE APPLIED TD PINS LISTED BELOW,
M..
-
-
N
TEST VOLTAGE VALUES
V'Lmin
-1.890
+85 o e
M..
Set Input
tau.... _
V,Hm ••
...
L SUFFIX
CEAAMIC PACKAGE
CASE 620
-
-
-
5
7
9
5
7
-
Pulse
In
9
Pulse
Out
-
9
6
2
2
9
2
9
2
-
5
12
5
12
2
15.
3
14
-
4
13
4
13
6,7
6,7
2
15
3
14
2
-
+l.llVde
SWitching Times
Clock Input
P,.opagation Delay
,.:, .. :.:;-... ,.:•• :.:,;, ':,.' .i .. ::.;
-
7
6
Min
Symbol
Power Supply Drain Current
Pin
Und.r
T.,
s:
n
....
o
5----,
6
2
2
8
8
1,16
1,16
1,16
1,16
8
8
1,16
1,16
8
8
1,16
1,16
8
8
1,16
1,16
-3.2Vck:
+2.0 Vdc
8
1,16
8
8
! !
8
+
1,16
+
8
1,16
+
8
1,16
8
8
+
1,16
1,16
i
ELECTRICAL CHARACTERISTICS
S1
5
Each MECL 10,000 serias circuit has been
designed to meet thade specifications shown
01
CE1
7
6
in the test table, after thermal equilibrium
-
3
The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through 8 5(H)hm resistor to
-2.0 volts. Test procedures are shown for
has been established.
A1
"'O':~"
CE2 11
0210
only ona input, or for one set of input con·
ditions. Other inputs tested in the same
manner.
Pin
Characteristic
I Symbol I
linH
Input Leakage Current
l.nL
4,5,6,7,9-
~
N
CN
Logic "1'
Output Voltage
VOH
2
21
Logic "0"
Output Voltage
Logic "I"
Threshold Voltate
Logic "0"
Thre$hold Voltage
VOL
3
31
VOHA
2
21
VOLA
3
31
I
I
Switching Times
Clock Input
Propagation Delay
IE
19+21".2+
'2+
Fall Time (20 to 80%)
'2-
Set Input
Propagation Delay
Setup Time
Hold Time
Toggle Frequency (Maxi
I
I
ii Test
Temperatu,.
15
5212
MC10231P Test Limits
+2Soc
_lODe
Min
I
Max
Min
I
- I
I
Typ
M••
52
65
I
I
M..
-0.890
-0.890
-1.675
-1.675
-0.960
-0.960
-1.850
-1.850
-0.980
-0.980
-0.890 -0.700
-0.890 -0.700
-1.825 -1.615
-1.825 -1.615
-1.630
-1.630
'5+2+
t12+15+
15+3+
tI2+14-
I
14+2tI3+15_
t4+3_
tI3+14+
1 'Setup
1 'Hold
I 'T"II
2
2.0
2
2.0
-1.595
-1.595
1.3
VILA rna.
VEE
_lODe
-1.890
-1.205
-1.500
-5.2
+2SoC
-0.810
-1.850
-1.105
-1.475
-5.2
+85oC
-0.700
-1.825
-1.035
-1.440
-5.2
+
1.0
VIH mall
200
tOutput level to be menured after'. dock pul. has been epplied to the
Ce
VILmin
VIHA min
VILA mall
G'"
8
1,16
~
/JAde
/JAde
Vdc
Vdc
5
7
Vdc
Vdc
5
7
8
8
1,16
1,16
Vdc
Vdc
9
1,16
1,16
2.25
MHz
Vlfj max
VIL min
1,16
1,16
9
•
:..fL
~
1,16
1,16
1,16
1,16
Vdc
Vdc
+
input (pin 6)
VEE
1,16
Pulse
In
Pulse
Out
6
5
12
15
9
12
14
4
13
-IndIvidually test eec:h Input. apply VIL mIn to pin under test.
BO e> CO
bO
bO'
co
9
NEGATIVE LOGIC
C1-
M1
14
co
(AOe> BO e> MO) + AD (BO e
MO)
M1
.1
.1'
b1
A1 eB1 eM1
A1 (B1 e
S1 - A1 e> B1 e> C1
Mn
b1'
C2
Thi,l. advance Information end .peciflcatlon. ara .ubJect to change without notice.
S. 0." .... ' I "formation section for peckaglng.
3-225
Me 10287 (continued)
MC10287 FUNCTIONAL TRUTH TABLE
Ml MO bl bl' .1 .1 • bO bO'.o 00'
14 3
13 12 11 10 4
H
H
H
H
H
H H
H H
H .H
H H
H H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
H
H
L
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
L
H
L
H
H
H
L
H
L
L
78
79
80
81
82
H
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
H
H
L
L
L
H
L
H
L
H
L
H
H
H
L
L
L
H
L
H
H
H
L
83
84
85
86
87
H
L H
L· H
L H
L L
H
H
H
H
L
H
H
L
L
H
H
H
L
L
H
H
L
H
L
H
H
L
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
88
89
90
91
92
L
L
L
H
H
L
L
L
H
H
L
L
H
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
L
H
H
93
94
95
96
97
H
H
H
H
H
L
L
H
L
L
H
H
L
H
H
H
H
H
L
H
L
H
H
H
L
H
L
L
H
H
H
H
H
98
99
100
101
102
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
40
41
42
43
44
L
L
L
L
L
L
45
46
47
48
49
L
L
L
L
L
L
L
L
L
L
L
5
6
7
8
9
L
L
L
L
L
L
H
L
L
H
H L
H
H
H
H
L
L
L
L
L
L
L
L
10
11
12
13
14
L
H
L
L
H
H
L
H
H
H
L
H
H
H
H
15
16
L
H
H
L
H
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
H
H
L
L
L
L
L
H
H
H
H
H
H
18
19
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
20
21
22
23
24
L
L
L
H
H
25
26
27
28
29
L
L
L
L
L
H
H
H
L
L
L
H
H
H
L
H
H
H
H
L
H
H
H
30
31
32
33
34
L
L
L
L
L
H
L
H
H
L
L
H
L
L
L
L
H
L
L
L
35
36
37
38
39
H
L
H
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
L
L
L
L
L
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
H
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
L
L
H
L
H
L
L
H
H
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
H
L
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
L
L
L
H
H
L
L
L
H
H
H
L
L
H
H
H
L
L
H
H
L
H
H
H
H
L
H
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
17
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
L
L
L
L
L
H
L
H
H
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
L
L
H
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
L
L
H
H
H
H
H
L
103
104
105
106
107
H
H
H
H
L
H L
H L
H L
H ·L
L H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
L
L
L
H
108
109
110
111
112
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
L
H
L
L
H
L
H
H
H
L
H
L
113
114
115
116
117
H
H
L
L
L
H
H
H
L
L
H
H
L
L
L
L
L
H
H
L
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
H
H
H
H
H
L
L
L
L
L
118
119
120
121
122
L
L
L
L
H
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
L
L
H
H
L
L
L
L
L
123
124
125
126
127
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
128
129
130
131
132
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
H
H
L
L
L
L
L
L
133
134
135
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
55
56
57
58
59
L L
L ·L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
H
L
H
H
L
L
L
H
H
L
L
H
60
61
62
63
64
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
H L
L H
L L
L
L
H
L
L
L
H
H
H
65
66.
67
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
H
L
H
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
L
H
H
L
H
L
H
H
L
L
L
L
L
3·226
L
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
50
51
52
53
54
H
L
L
H
H
L
L
L
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
L
73
74
75
76
77
H
H
L
H
L
H
H
L
L
L
H
H
L
H
H
H
H
H
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H· H
H H
H H
L
L
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
L
L
L
H
H
H
L
L
L
L
H
L
L
H
H
0
1
2
3
4
H H
H H
H·'H
H H
H H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L.
H
H
H
H
H
H
L
L
L
L
L
L
H
L
L
H
L
H
H
H
H
L
H
L
H
68
69
70
71
72
H
L
H
L
L
L
L
L
H
Word
H
H
H
H
H
H
H
L
L
H
L
L
L
L
L
H
15
H
H
L
L
H
H
H
H
H
H
H
1
H
H
H
L
L
H
H
H
H
L
H
H
2
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
9
H
L
H
L
H
1 15
H
L
L
L
L
H
H
7
H
H
L
L
H
2
H
H
6
H
H
L
L
H
9
H
H
H
H
H
H
5
L
L
L
L
H
14 3· 13 12 11 10 4
Word
7
H
H
H
H.
H
L
Ml MO bl b" .1 .1' bO bO' .0 00' CO 5051 C2
51 C2
6
H
H
H
H
co so
5
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
L
L
H
L
H
L
L
H
L
..
~t;!CT1UCAt:
CHAlIACTERlST1CS
Each MECL 10.000 _ios circuit hils been
. designed to meet the de specifications
shown in
the tnt
table. after thermal
3
MO
6
eO
so
-
2
.0'
equilibrium has been .tabUlhed. The circuit is in a test socket or mounted on a
printed circuit board and transverse air flow
greater man ouu Imear rpm IS mamtam80.
Outputs are terminated through a 50-ohm
resistor to -2.0 volts. Test procedu res are
Ihown for only .Iected inputs and outputs.
Other inputs and outputs tested in the
.me mannar.
4
bO
5
bO'
9 - co
1 4 - Ml
11101 3 - bl
1 2 - bl'
-
.,
.,'
OT ...
Temperatur.
-30"1:
C2r-------15
+25o C
+85"1:
Met0287 Test Limits
Pin
Cherec.... illic
Po.,..r Supply Or.in Current
Input Current
w
~
Symbol
'E
'inH
lint
Logic "1" Output Vottege
VOH
I\J
-.J
Logic "0" Output Volt.
Logic "1" Thr..... old VOlt.
Logic "0" Thr..... old Vol ....
VOL
VOHA
VOLA
Un_r
T. .
8
3
4
6
9
3
1
2
15
1
2
15
1
2
15
I
2
15
'9+15+
'6-t14+2l4-t+
t11+1_
t13+1t3+1+
t3+15+
t14+15+
15
1
2
1
1
1
1
15
15
Ri_Tin.
(20%.080%1
'15+
F.U Tin.
(20%.080%1
'ts-
·Apply +0.31 V to all other inputs.
-1.890
-1.850
-1.825
-1.205
-1.105
-1.035
Typ
Max
Min
M••
Unit
VIH .....
-
-
77
-
3
4
6
9
-
0:5
-
-
-
#lAde
-
96
200
220
265
410
mAde
-
-
j.lAdc
-
3
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
~
~
~
~
~
t
5.9
9
6.9.10
-1.890
-1.675
-1.850
-1.650
-1.825
-t.615
Vdc
~
t
-
t
-
-
-
-
-
-0.910
-
Vdc
6.7
-
9
4
9
-1.630
-
-1.595
Vdc
t
+
t
-
-
-
~
-
-0.980
-1.655
-
~
t
-
-
-
-
~
~
-
t t
t
-1.500
-1.475
-1.440
-
-
-
-
!
~
t
-
6.7.10.11
6.7
-
-
-
6.7.10.11
+1.t1 V +0.31 V
.
-
-
-
-
-
Pul.ln
-
-
-
-
2.0
-
-
-
-
3
15
15
-
-
-
2.0
-
-
-
-
3
15
-
-
-
-
~
8
8
!
16
16
~
t
t
t
~
16
9
8
4
9
u . . Out -3.2 Vd. +2.0Vdc
11
13
3
3
14
15
1
2
1
1
1
1
15
15
4
16
16
16
-
-
8
8
8
-
-
-
(Vee 1
GncI
~
15
-
ns
VEE
-
-
-
-5.2
-5.2
-5.2
16
-
-
3
3
6
6
13
3.9
9
9.14
11
-
VEE
8
-
-
-
~.
c:
CD
c.
-
-
-
-
9
6
4
-
2.0
4.5
3.5
4.5
3.0
3.5
8.5
8.0
8.0
-
::J
::J
VILmin V.HAmi VILA......
Min
-1.060
8'
Volts
M••
-
......
TEST VOLTAGE VALUES
Min
Switching Tim ..
Prop. .tion Del-v
(50ohmlo~)
CUE~O
VOLTAGE APPLIED TO PINS LISTED BELOW,
+1Ii"l:
+25"1:
-30"1:
200
CERAMIC PACKAGE
VIM ...... VILmin VIHAm;' ViLA .....
-0.890
-0.810
-0.700
~
-.
Lwrnx
t
+
8
16
MC10287 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS" 25°C
Vee - +2.0 Vdc
COIX
i
5~F
V out
t
MO
Coax
0.1
SO ~
.0
.0'
bO
bO'
Pul •• Ganerator
CO
51 ~
Ml
Input Pulse
.1
t+ = t-:: 2.0 ± 0.2 ns
.1'
(20 to 80%1
bl
bl'
50-ohm termination to ground 10
c:ated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxi,1 cable. Wire length should
be
1/4 inch from TP in to input
pin and TP out to output pin.
C2 I - - - -
0,1
<
Vee' -3.2 Vde
±
~
Unused outpl.JU .re tied to a 50ohm resistor to ground.
PROPAGATION DELAY
_----~~-:---- +1.11 V
+0.31 V
t+-
t-+
3-228
MC10287 (continued)
APPLICATION INFORMATION
gram" matrix of the single·bit products (or summands)
can be written:
: The MC10287 is a stand alone fully iterative dual multi·
Plier' cell. It is intended for use in parallel multiplier
arrays where maximum speed is desired. Each cell is a
modified gated adder/subtractor individually controlled
by a mode select line. Internal carry lookahead (also
called anticipated carry) is used to minimize sum and
carry out delay times.
. The mode controls are specifically buffered such that
they.c'm be grounded. Normally. MECL 10.000 device
inputs should not be placed at ground to establish a high
logic level. However. MO and Ml can be used at ground
potential for ease of layout in large arrays.
An array multiplier is defined as a multi· input. multi·
output combinational logic circuit that forms the product
of two binary numbers. Binary multiplication can be
treated in two categories. that is. simple magnitude multi·
plication and 4·quadrant multiplication (requiring both
positive and negative numbers).
X3YO x2YO xlYO xOYO
x3Yl x2Yl XlVI xOYl
x3Y2 x2Y2 x 1V2 xOY2
x3Y3 x2Y3 xlY3 xOY3
Z7
z6
z5
MAGNITUDE BINARY MULTIPLICATION
'.;' Magnitude multiplication consists of the product of
two binary numbers in which all digits are number bits
(no sign bit). Magnitude representation then includes only
positive numbers.
Thus. for a 4·bit number X the representation is:
X=X3 x2 Xl xO
A 4-bit by 4-bit product becomes:
4
B.
12
lB
z2
zl
zO
xlY3 x3YO x2YO xlVO xOYO
The product consists of the sum of the single· bit products formed by this expression. The standard "parallelo-
Number of Bill
z3
x2Y3 x3Yl x2Yl xlYl xOYl
x3Y3 x3Y2 x2Y2 xlV2 xOY2
Z = X. Y = (X3 x2 Xl xO) • (Y3 Y2 Yl YO)
TA8LE 1 - TYPICAL MUL TIPL Y TIME FOR AN n-BIT BY
n.aIT BINARY MAGNITUDE ARRAY MULTIPLIER
z4
The MC10287 is used in an array summing the single·
bit products to form the final result. It is observed that
the arithmetic product of binary digits Xi and Yi is also the
logical product (Xi times Yi = Xi AND Vi· The AND
function on the operand inputs of the MC10287 forms the
single·bit products of the matrix directly and sums them
internally. For magnitude binary multiplication. the
MC10287 functions as a dual full adder (MO. Ml are
both low).
The partial product array can be summed using a
number of different techniques. The fastest technique is
some form of matrix reduction scheme that prevents
carry propagation until the final level of summation.
Several of these schemes are discussed in detail in
Reference 1.
As an example. if the matrix is rearranged and written
in a different form:
xOY3
Z7
z6
z5
z4
z3
22
zl
zO
FIGURE 1 - 4-BIT BY 4-BIT MAGNITUDE ARRAY MUL TIPLIER
Total Multiply Time
Inll
14
25
39
44
"0
3-229
Me 10287 (continued)
The summation of the partial products for this con·
figuration is shown in Figure 1. The number of MC10287's
for an n·bit by n·bit array is n (n·l)/2. Note also that the
least significant product bit (ZO = xOYOI is formed by an
individual AND gate (negative logicl.
Table 1 gives package count and typical multiplication
times for n·bit by n·bit magnitude multiplier arrays. The
mUltiply times do not include wiring delays, and the
package count does not include the gate for the least
significant product bit.
in which all inputs are positive quantities. If one input is
negative (such as 8). the outputs Cout and S must be
coded such that they can represent the 4 possible output
conditions. If 8 can be a negative one or zero, .tha-~
output can then be:
net output =
I
-~
+1
+2
FOUR·QUADRANT MULTIPLICATION
If Cout, whose weight is twice that of S, is assigned,
positive value and S is a negative value, the above vllu.is
can be represented:
.;
Sign·magnitude and 2's complement representations
are commonly used for 4·quadrant multiplication. For
sign·magnitude representation, the binary word consists of
a sign bit and magnitude bits which indicate the absolute
value of the number. For a 4·bit example:
where:
net output = 2 • Cout - S
-1 = 0 - 1
0= 0-0
= 2-1
+2= 2-0
+1
X= Xs x2 Xl xo
For X. y= Z
Z = X • Y = (xs x2 Xl xOI • (Ys Y2 Yl YO)
An array multiplier for this representation consists of
an (n·l)·bit by (n·l)·bit magnitUde multiplier that pro·
duces the product of the magnitude bits of X and Y and
of logic that produces the proper product sign bit
(zs = Xs @Ys)'
2's complement representation also inclUdes a sign
bit which is a negative bit. That is:
If the truth table is written and logic equations gen8/)
ated, the result is a subtractor. That is, a subtractor uS8Cf
in place of a full adder produces the proper outputs. The
symbol for the subtractor is:
.
A
! /-B
G-Cin
X = -x3 x2 Xl xo
co: ~
where x3 is the sign bit. The product of two 4·bit 2's
complement numbers becomes:
Z = X. Y = (-x3 x2 Xl xO). (-Y3 Y2 Yl YO)
-5
The matrix for this expression is:
Also, if the input variables are multiplied by -1, the
outputs also are multiplied by -1. Thus, the following
devices are equivalent:
-x3YO x2YO xlVO xoyo
x2Yl xlYl xOYl
x1V2 x OY2
-A
A
-Z7
z6
Z3
! /B
zO
The product is the sum of this array of single·bit
products. However, notice that several summands are nega·
tive quantities. Therefore, they can not be simply added
as is the magnitude binary multiplier. The subtraction
capability of the MC10287 is utilized when considering
these negative quantities.
A standard full adder is symbolized as:
c:U:
A
C ;n
~
.C:: ~
-5
A
-A
G-C;n
~
C; ~
5
-5
3·230
1/--
G--Ci;'
5
! /-B
! /a
G-C;n
c:U:
8-
! /G_-C
~~
5
in
MC10287 (continued)
A basic adder/subtractor can then handle all the varying
situations that appear in the multiplication matrix.
If the 2's complement matrix is rearranged:
IMPROVED SWITCHING DELAYS
The specified ac switching delays are given for output
loading of 50 n to -2 volts. With lower output current,
propagation delavs will be improved and decreased multi·
ply times can result. For output loading of 1 kn to VEE,
the following delavs are typical.
-xOY3
-X1Y3 -x3VO x2YO xlVO xOYO
-x2Y3 -x3Yl
x2Yl xlVl xOYl
x3Y3 -x3Y2 x2Y2 xlV2 xOY2
-z7 z6
z5
z4
z3
z2
Zl
Input
CO
AO
AO
BO
AO
BO
MO
zO
The adder/subtractor array for this configuration is
shown in Figure 2. Care must be taken to insure that the
proper mode of operation (add or subtract) appears at
each summing node as a function of the positive and
negative weighted inputs.
The summand matrix can be altered different ways to
speed up the multiplier array. Reference 2 discusses the
algorithm used with the MC10287 in detail. Also, the
techniques of Reference 1 also apply to 2's complement
arrays using the MC10287.
Table 2 gives typical multiply times for 2's complement
arrays for n'bit by n-bit multipliers.
REFERENCE AND ACKNOWLEDGEMENT
The techniques for implementing the MC10287 in
multiplier arrays resulted from work done originally at
M.I.T. Lincoln Laboratories. Also, applications information
presented here developed in part from personal correspondence with P. Blankenship of Lincoln Labs. The
following references are useful in developing multipliers
using the MC10287:
TABLE 2 - TYPICAL MULTIPLY TIME FOR AN n-BIT BY
n·BIT 2'.CO~LEMENT ARRAY MULTIPLIER
Total Multiply Time
Number of Bits
(ns)
Package Count
4
8
12
16
14
25
6
28
66
120
39
44
Delay (ns)
1.7
2.8
2.8
3.1
3.9
4.4
8.7
Output
C2
C2
SO
SO
51
51
51
1. A. Habibi and P.A. Wintz, "Fast Multipliers," IEEE
Trans. Computers (Short Notes!. Vol. C·19, Feb.
1970, pp. 153-157.
2. S.D. Pezaris, "A 40-ns 17-Bit by 17-Bit Array
Multiplier", IEEE Trans. Computers, Vol. C·20,
Number 4, April, 1971, pp. 442-447.
FIGURE 2 - 4-BIT BY 4-BIT 2'. COMPL EMENT ARRAY MULTIPLIER
'0
3-231
~f
')
QUAD OR/NOR GATE
~---------'
MC10501
POSITIVE LOGIC
(8) 4
2 (6)
r--L-~~--5
. / " - - - 5 (9)
(11)
The MC10501 is a quad 2·input OR/NOR
gate with one input from each gate common to
pin 12 in the L package and pin 16 in the F
package. Input pulldown resistors eliminate the
need to tie unused inputs to an external supply.
NEGATIVE LOGIC
...----...--~- 2 (6)
(81 4··
MECL 10,000 series
7-'L---r---"'-~-3
..--~~~--6
(7)
(9)
3 (71
(11) 7
"---L-~~--6
(10)
(10)
...L--<:",-"",,,,,,_ _ 14 (2)
(14)10
. - - , - - _ , , - - - 11 (15)
(1)13
Po
15(3)
(16) 12 _ _--.'---'_ _ _ 9 (13)
tpd
_ - , - _ . / " - - _ 9 (13)
= 25 mW typ/gate
= 2.0 ns typ
(No Load)
Output Rise and Fall Time:
= 3.5 ns typ (10% - 90%)
= 2.0 ns typ (20% - 80%)
Numbers at ends of terminals denote pin numbers for L package
(Case 620).
Numbers
(C ....
in
parenthesis
denote
pin
numbers
for
F
package
6501.
CASE
VCC1
VCC2
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
VEE
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25 0 C
V out
NOR
vee1 = VCC2
+2.0 Vdc
Coax
V out
OR
Coax
Coax
PROPAGATION DELAY
50
50
Input
+1.11 V
Pulse Generator
50%
Input Pulse
' -_ _....J_
t+ = t- = 2.0±. 0.2 ns
(20 to 80%)
---+0.31 V
t++
Unused outputs
connected to a
100.ohm resistor
to ground.
L_~_ @x_--o I~F
50 ohm termination to ground 10
cated In each scope channel Input
All Input and output cables to the
~~~~~a~:·a:~81~~~!tl~~;:h5~~~~~
V out OR
V aut NOR
,...
-32 Vdc
VEE
be <114 inch from TP in to input
pin and TP out to output pin. V out
is 2: 1 attenuated.
See General Information section for packaging.
3-232
ELECTRICAL CHARACTERISTICS
3:
Each full tamperatura range MECL 10,000
5
7
after thermal equilibrium has been astab--
lished.
...
~
o...
o
4~2
series circuit has been designed to meet the
de specifications shown in the test table,
The circuit is in a test socket or
mounted on a printed circu it board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 1~ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
same man ner.
3
10
~4
13
12
11
15
9
-
L SUFFIX
CERAMIC PACKAGE
CASE 620
8
::J
e.
::J
C
CD
0.
TEST VOLTAGE VALUES
CVoIt.1
ttT...
T ........tur.
-liIi"c
+:zsoC
+126"c
Co)
~
Co)
Co)
CherKt..istic
Sy .....
POwer Supplv Or8.n Current
IE
Input Current
l.nH
l.nL
Logte "',.
Output Voltage
LogiC "0"
VOH
VOL
Output Voltage
logic "'"
8
4
12
4
12
5
5
2
2
5
5
2
2
VOHA
5
5
2
2
VOLA
5
5
2
2
Threshold Vol lege
Logic "0"
Threshold Voll.
P,n
Unci.
Tnt
M;.
Max
Min
Typ
M_
-
29
450
910
-
20
26
-
0.5
0.5
-UJ80
t4+2l4-2+
14+5+
'4-5Rise Time
12010_'
Fall Time
12010_1
'2+
'5+
'2_
's-
2
2
5
5
2
5
2
5
-
~.880
+ ~
-1.920 -1.655
0.5
0.5
-0.930
~
-
-
1.0
j
-
-
1.635
+
3.7
+
..
-
-
2.0
j
+
2.9
+
33
~
VIHA min
VILA meK
VEE
~.880
-1.920
-1.255
-5.2
~.780
_1.850
-1.820
-1.106
-1.000
-1.510
_"'75
~.83O
-"'00
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
0.3
0.3
-0.825.
VIHmu
VILmin
VIHAmin
VILAmla
VEE
GncI
29
265
mAde
-
"Adc
4
12
-
8
8
1,16
",Adc
-
-
536
-
,.,Adc
-
-
.Adc
-
~.830
Vdc
12
-
+ ~
-1.545
~.845
~
-1.525
-
1.0
j
IVeel
IJn;t
+ + +
-1.600
1.0
+ +
~
-
-
1.1
-
....
VILmin
+125Oc
Mi..
-1.620 -1.820
-
+ +
4.0
265
536
~.780
-0.950
..
+
-
-1.850
+ + +
-1.100
Switching Times
I1,QO-ohm la.jl
Propagation Delay
MC101i01L T . . Lim.
+25o C
-li6"c
VIHmn
+
3.7
+
40
+
4
•
•
•
•
Vdc
Vdc
12
4
-
4
12
-
-
--
-
-
-
..
-
n,
I
-
-
..
-
-
-
-
-
12
4
-
-
1,16
8
8
!:!:
8
1,16
I
• •
8
+
1,16
+
8
1,16
+
1.16
-
12
4
-
12
4
12
4
-
Pu"'n
PuI.Out
-3.2 V
+2.0 V
4
2
2
5
5
8
1,16
Vdc
-
-
1,16
8
8
+
• •
I II
2
5
2
5
ELECTRICAL CHARACTERISTICS
s:
B~6~
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
....oo
C1'I
o....
11.
10
14
2
15
1
transverse air flow greater than 500 linear
~
3
16
fpm is maintained. Outputs are terminated
13
throu~
a l00-ohm resistor to -2.0 volts.
Test procedures are shown for onlv one
gate. The other gates are tested in the
same manner.
8:::J
....
F SUFFIX
5'
CERAMIC PACKAGE
CASE 650
t:
~
reST VOLTAGE VALUES
I
(Voltsl
@T ...
T ernperatu,e
VIH",,,
Vll min
VIHA min
-0.830
-0.720
-1.920
-1.255
+25o C
+ 125°C
-0.580
-1.850
-1.820
-1.105
-1.000
-55"<:
MCl0501F T_ Limits
Pin
(.)
~
~
Power Supply Dram Current
Input Curren I
Symbol
Test
Min
M..
Min
'E
12
-
29
-
ImH
8
16
8
16
9
9
6
6
9
9
6
6
450
910
-
ImL
logIC "1"
Oulpul VOltage
LogIC "0"
Output Voltagt!
VOH
VOL
Loglc'T'
Threshold Voltage
VOHA
9
9
6
6
LogIC "0"
Threshold Voltage
VOLA
9
9
6
6
-
RlseTlmt!
(2Ot08O%J
Fall Time
(2010_1
t8-9-
6
6
9
9
16+
19+
6
9
16-
8
t8+618-6+
t8+9+
~~
9
---
-
0.5
0.5
-1.080 -0.830
+
~
-1.920 -1.655
~
-1.100
+
-
+
-
SWltchulg Tlme~
(l00-ohm load)
Propagation Delay
+2SoC
-55"<:
Unci.
Charact",istlc
-
-
-
-
-
-
-1.635
~
-
-
0.5
0.5
-0.930
~
-1.850
+
-0.950
~
-
1.0
+
1.1
~.
TV.
20
-
-
-
-
2.0
VEE
-1.475
-5.2
-5.2
-1.400
-5.2
reST VOLTAGE APPLIED TO PINS LISTED BELOW:
+ 125°C
M..
Min
M..
Unit
VIHmaJ(
VIL mm
VIHA min
V,LA ma.
VEE
26
-
29
265
635
mAdc
-
-
-
,..Adc
/oIAdc
8
16
-
-
-
-
8
16
-
-
12
12
12
12
12
12
265
535
-
-
-0.720
~
0.3
0.3
-0.825
~
-1.620
-1.820
+
-
-0.845
-
-
-1.600
~
2.9
~
+
-
-
j
VILAma.
-1.510
+
3.3
~
-
i,.!Adc
-
.Ad,
-
-0.580
Vd,
16
8
~
+
-1.545
Vdc:
+
-
Vd,
-
-1.525
~
-
-
+
-
-
16
8
-
-
+
Vd,
+
0,
j
-
-
-
-
16
8
-
-
---- L-
-
-
-
+
12
+
16
8
-
-
4.5
4.5
4.5
4.5
4.5
4.5
+
4.5
+
12
4.5
+
4.5
-
16
8
16
8
12
+
•
+
Pulse In
PuI.Out
-l.2V
+2.0V
8
6
6
9
9
12
4.5
j
-
-
IVeel
GncI
6
9
6
9
lj
"')
QUAD 2-INPUT GATE
MEeL 10,000 series
\..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1
MC10502
The MC10502 is a quad 2-input NOR gate.
Input pu IIdown resistors elim inate the need to
tie unused inputs to an external supply.
NEGATIVE LOGIC
POSITIVE LOGIC
(8)
(9)
(10)
(11)
(14)
:~2
~~3
:~2
(8)
(6)
(!l)
~~3(7)
(10)
(7)
(11)
10~ 14
10~_14(2)
(14)
(2)
(15) 11
11~
(15)
(16)
12~15
(1)
13
9
(6)
Po'" 25 mW tvp/gata (No Load)
tpd = 2.0 ns tvp
Output Rise and Fall Time:
(16) 12~15(3)
(3)
113)
13~9(13)
11)
= 3.5
nstyp (10% - 90%)
= 2.0 ns typ (20% - 80%)
Number. at end. of terminals denote pin number, for L package
(C... 6201.
Numbers in
(C ... 660>-
parenthesis
danote
pin
numbers
CASE
VCCI
VCC2
VEE
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
for
F
package
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@ 25°C
VCCI
=
VCC2
+2.0 Vdc
Coax
V out NOR
V out OR
Coax
50
Coax
50
PROPAGATION DELAY
Input
Pulse Generator
Input Pulse
't+ = t- = 2.0 ±. 0.2 ns
(20 to 80%)
C_--f1:'~'
50-ohm termination to ground located in each scope channal input.
Unused outputs
connected to 8
100-0 h m reli stor
to ground.
L3fvdC
V out NOR
All input and output cables to the
scope are equa' lengths of 50-ohm
coaxial cable.
V out OR
Wire length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.
See General Information section for packaging and maximum ratings.
3-235
ELECTRICAL CHARACTERISITCS
s:
...nc
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been estab·
lished.
The circuit is in
8
test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
:~2
10~
through a 1~ohm resistor to -2.0 volts.
Test procedures are shown for only one
11
C
-
~~3
fpm is maintained. Outputs are terminated
gate. The other gates are tested in the
same manner.
C1I
"
12~15
13~9
N
8
...3'
:::J
c:
no
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
IVoIts)
lilT...
Temperatur.
-SS"C
+25o C
+125 0 C
MC10502L Test Limits
Pin
w
r()
w
en
-SS"C
Symbol
Power SupplV Drain Current
'E
linH
8
12
IlnL
12
VOt<
9
9
15
15
-1.080 -0.830
VOL
9
9
15
15
-1.920 -1.655
VOHA
9
9
15
15
-1.100
9
9
15
15
-
Logic "'"
Output Voltage
Logic "0"
Output Voltage
Logic "'"
Threshold Voltage
logic "0"
Threshold Voltage
Switching Times
(lOO-ohm loedl
Propagation Delay
Rise Time
(20'0_1
Fall Time
(20 to 8II%J
VOLA
112+15_
112-15+
'12+9+
'12-9'15+
'9+
'15'9-
15
15
9
9
15
9
15
~
M;n
0.5
~
+
~
-
1.0
j
VIL min
-1.920
-1.850
-1.820
VIHA min
-1.255
-1.105
-1.000
VllAm••
VEE
-1.510
-5.2
-1.415
-1.400
-5.2
-5.2
I
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+2SoC
Chllract.-istic
U.....
T...
Input Current
VIH m.x
-0.830
-0.720
-0.580
+t25°C
1Veel
Min
TV.
Max
Min
M. .
Unit
VIH malIC
VILmin
VIHA min
VllAmn
VEE
Gnd
20
26
265
-
29
mAde
-
-
-
1,16
265
j,lAdc
12
-
8
1,16
-
0.5
-
0.3
-
j.lAdc
-
12
-
-
8
450
-
-
8
1,16
-0.720
-0.825
-0.580
Vd,
8
1.16
~
~
-
+8
1,16
-
• •
M. .
29
~
~
-
-
-1.635
~
0.930
+
-1.850
+
-0.950
+
-
-
3.1
1.0
+
1.1
4.0
~
-
-
-
-
-
+
-1.620
+
-
-1.600
-
2.0
• j
+
~
.. 2.9
+
33
+
-1.820
-1.545
~
~
-0.845
+
-
-
1.0
j
+
Vd,
+
Vd,
-1.525
Vd,
3.1
~
~
4.0
-
-
-
~
12
13
+
+
n,
j
12
13
-
-
-
-
-
-
-
-
-
-
-
12
13
-
-
-
+
8
1,16
+
1,16
-
12
13
12
13
12
13
-
Pulse In
Put. Out
-3.2V
+2.0V
12
15
15
9
9
15
9
15
9
8
1.16
j
8
+
+
•
j j
3!:
n
....
ELECTRICAL CHARACTERISTICS
Each full temperature range MEeL 10,000
series circuit has been designed to meet the
:~6
de specifications shown in the test table,
,O~,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 10~ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate.
'4~
~
o
;
"~
2
,.~
'6~3
1_~13
N
8::l
~,
:J
c::
a
F SUFFIX
The other gates are tested in the
CERAMIC PACKAGE
CASE 650
same manner.
rEST VOLTAGE VALUES
(Voltsl
"'Tnt
T emperatur.
-55"<:
+2So C
+12SoC
w
N
w
......
Pin
-SSOC
Und ..
MCt0602F Telt Lim"s
+25 o C
+ 125°C
Typ
Min
M..
Min
M..
CNiract.i5tic
Svmbol
Te..
Min
M..
Power Supply Drarn Current
'E
IlnH
12
-
29
450
IlnL
16
13
13
3
3
13
13
3
3
0.5
-
0.5
-1.080
-0.880
-0.930
Input Current
logic "1"
Output Voltage
logic "0"
Output Voltage
logic "1"
Threshold Voltage
LogiC "0"
Threshold Voltage
SWitching Times
(100ohm loadl
Propagation Delay
Rise Time
1201080%)
Fall Time
120 to 80%)
16
VOH
VOL
VOHA
VOLA
13
13
3
3
13
13
3
3
t16+3'16+3+
t16+13+
t16+13-
3
3
13
13
'3+
t13+
'3_
t13-
3
13
3
13
-
•• •
• • •
+
•
+
-1.920 -1.655
-1.100
-
-
-
-
-1.850
20
26
-
265
-
-
-
-
-
-1.635
-
-
-
--
10
+
1.1
+
-
-
20
j
-0.780
-
+
-
-1.415
·1.400
-5.2
-5.2
-5.2
TEST VOL rAGE APPLIED TO PINS LISTED BELOW:
VILA m.x
VEE
-
-
265
j.lAdc
16
-
12
12
j.lAdc
-
16
-
+
-1.545
-
+
-1.105
-1.000
VIHA min
-1.525
3.3
-1.850
-1.820
VIL min
-
-
-1.510
-
-1.600
29
VEE
-1.255
mAde
-0.845
-
VILA mill
-1.920
29
-0.825 -0.630
1.820
-0.880
-0.780
-0.630
VIHA min
VIHmiJ_
• •
• • ••
• •
-1.620
r--
Vilmin
Unit
0.3
-0.950
-
-
VIHmn
-
-
Vd<
+
Vd<
-
-
+
16
1
+
-
Vd<
Vd<
+
0,
-
'6
1
-
-
-
-
j
-
-
-
-
16
1
-
-
I
-
-
-
-
16
I
4,5
12
4,5
12
4,5
+
12
+
+
4.5
+
12
4.5
+
4,5
+
-
16
1
16
1
-
+
Pulse In
PuI_Qut
-J.2V
+2.0 V
16
3
3
13
13
12
4,5
-
-
-
-
tVeel
Gnd
4,5
j
-
3
13
3
13
12
j
+
I
MECL 10,000 series
QUAD 2·INPUT AND GATE
MC10S04
The MC10504 provides a very useful low power, high
speed logic AND function. High Z input pulldown resistors
allow high dc and ac fanouts and eliminate the need to
tie unused inputs to an external supply. The open emitter
outputs allow maximum flexibility in the selection of ter·
mination techniques and minimize the power requirements
when driving transmission lines. Open emitter outputs
also allow wire·ORing capability, which is very useful in
control, bussing, and communications in high speed central
processors, high speed peripherals, digital communication
systems, minicomputers and instrumentation.
Po = 35 mW typ/gate (No load)
tpd '" 2.7 ns tYP
Output Rise and Fall Times'
= 3.5 ns typ (10% - 90%)
= 2.0
ns typ (20% - 80%)
POSITIVE LOGIC
(8)4~
~
(9)5~216)
(10)6~3
(7)
1111 7
NEGATIVE LOGIC
(14)10~
~14(2)
18)54~
(15)11~
~2(6)
(9)~
(16)12~9113)
1')'3~'513)
110)
67~- '~317)
(11)~
Numbers at ends of terminals denote pin numbers for
114)10~1
L package (Case 6201.
(2)
115) 11
Numbers in parenthesis denote pin numbers for
116)12~9113)
F package (Case 6501.
(1)13~1513)
CASE
620
650
Pin 1
Pin 5
Pin 16
Pin 4
Pin 8
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
veel
Vin
To Channel "A"
V CC2
t2.0 Vdc
V out
V out
NAND
AND
PROPAGATION DELAY
To
Channel
"8"
Input
Pulse Generator
50
50
Input Pulse
tt '" t- =- 2.0 !
0.2
ns
(20 to 80%)
I
+1.11V~
O.ljJF
L ____
~1:
I
50 ohm termmatlon to
ground located in each
scope channel Input
VEE
I
...J
Unused outputs connected to
a 1 aD-ohm resistor to ground.
0 1
~F
-3.2 Vdc
All input and output cables to the scope are equal lengths of 50-ohm coaxial cable.
Wire length should be
1/4 inch from TPin to input pin and TP out to output pin.
V out is 2: 1 attenuated.
<
See General I nformation Section for packaging and maximum ratings.
3-238
3:
o
o
U'I
o
ELECTRICAL CHARACTERISTICS
~
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
,o~
board and transverse air flow greater than
~ Imear rpm IS maintained. Outputs are
terminated through a 1()()..ohm resistor to
Power Supply Drain Current
w
~
W
CO
Symbol
_
11~14
12~9
13
-2.0 volts'- Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
Characteristic
-
:~2
:~3
Each MECL 10.000 series has been de·
15
L SUFFIX
~.
c..
Min
8
-
Max
39
Min
-
Typ
28
VILAmax
VEE
_55 0 e
-C.880
-1.920
-1.255
-1.510
-5.2
-C. 780
-1.850
-1.105
-1.475
-5.2
+1250 e
-0.630
-1.820
-1.000
-1.400
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+2SoC
-550 e
VIHAmin
+25o C
MCl0504L Test Limits
Pin
Under
Test
VILmin
+1250 e
Max
Min
35
265
220
VIHmax
VILmin
VIHAmin
VILAmax
VEE'
(Vee)
Gnd
mAde
-
-
8
1.16
13
12.13
-
-
..Adc
",Adc
-
-
8
8
1.16
1,16
8
1,16
-
8
1,16
•
1,16
8
1,16
Max
Unit
-
39
-
265
220
linL
12
0.5
-
0.5
-
-
0.3
-
",Adc
-
12'
VOH
9
9
9
15
-1.080
-0.880
0.930
-0.780
-0.825
-0.630
Vdc
-
~
12
13
12,13
9
15
15
15
-1.920
-
Vdc
12,13
-
13
12
-
-
9
9
15
15
-1.100
12
13
12
13
-
-
13
12
-
13
12
9
9
15
15
-
12
13
12
13
-
-
Logic "I"
Threshold Voltage
Logic "0"
Threshold Volt_
VOL
VOHA
VOLA
c:
(!)
(Volts)
VIHme.
Logic "I"
Output Voltage
::J
@Test
Temperatur.
Ie
I·
Logic "0"
8::J
TEST VOLTAGE VALUES
I "out Current
Output Voltage
.1=0
CERAMIC PACKAGE
CASE 620
13
12
450
375
+
t t
-1.655
t
•
+
-
-1.635
~
Switching Times-
1.850
t
0.950
t
-
-
-
-
+
-1.620
+
-1.820
t t
-
-C.845
-1.600
-
t
t
-
t'
-1.545
+
-
-
-1.525
+
t
Vdc
i
i
Vdc
-
-
+1.11 V
-
13
12
-
-
-
-
8
t
t t
~
8
~
1,16
t
-
-
13
12
Pulse In
purse Out
-3.2 V
+2.0 V
12
9
9
15
15
9
15
8
1,16
+
(l00-ohm load)
Propagation Dalay
Rise Time
(20%1080%)
Fall Time
(20%1080%)
112+9112-9+
112+15+
112-15113+9+
113+15-
9
9
15
15
9
15
19+
tl5+
9
15
19115-
9
15
-
-
-
-Inputs 4, 7, 10, and 13 will behave similarly for ac and I inH values.
Inputs 5, 6, 11, and 12 will behave similarly for ac and linH values.
-
-
-
-
-
-
1.0
2.2
4.0
j t
2.7
2.7
1.5
2.0
t ~
3.5
-
-
t
-
-
-
-
-
ns
13
~
12
j
-
-
-
t
13
l
9
15
9
15
s:
ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000
seriescircuit has been designed to meet the
8~
de specifications shown in the test table,
after thermal equilibrium has been estab-
10~_
mounted on a printed circuit board and
14~
-2
15~
16~13
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
same manner.
Characteristic
Power Supply Dram Current
Input Current
Symbol
'e
ImH
linL
~
o
Logic "1"
Output Voltage
Logic "0"
Output Voltage
Logic "1"
Threshold Voltage
Logic "0"
Threshold Voltage
Switching Times·
(100-ohm load)
Propagation Delay
Rise Time
(20%'08O%)
Fall Time
(20% '0 80%)
VOH
VOL
VOHA
VOLA
t16+3+
'16-3'16+13'16-13+
'1+3:t1+13+
'3+
t13+
'3_
'13_
1
o....
FSUFFIX
CERAMIC PACKAGE
CASE 650
~
11~7
lished. The circuit is in a test socket or
w
-6
9o-~
o
~
~
8
TEST VOL TAGE VALUES
3
::J
~.
IVoltsl
::J
c:
@Test
Temperature
Pin
Under
Tes.
Ma.
Min
TVp
12
39
-
1
16
16
-
450
375
0.5
-
0.5
3
13
13
t3
3
3
3
13
3
3
13
13
-1.080
-0.880
-0.930
3
3
13
13
-
3
3
13
13
3
13
-
3
13
3
13
i t
-1.920
-1.655
~
t
-1.850
t i
-
-1.100
t
-0.950
~
-1.635
-550 e
-0.880
-1.920
-t.255
-1.510
-5.2
-0.780
-1.850
-1.105
-1.475
-5.2
+12SoC
-0.630
-1.820
-1.000
-1.400
-5.2
-
-
39
mAde
1
1,16
4.5
4.5
-
16
-
-
12
12
1,16
-
4.5
,....Adc
,....Adc
-
12
-
265
220
12
12
4,5
4,5
-
12
-
16
1
-
12
0.3
-
,....Ade
-0.780
-0.825
-0.630
Vdc
~
~
i
~
-t.620
-1.820
-1.545
Vdc
~
~
-0.845
Vdc
-
-
-
-1.600
t
-
-1.525
Vdc
1.0
-
1.5
2.0
~
~
Inputs 9,10,15 and 16 will behave similarly for ec and linH yaJues_
VEe
-
-
• Inputs 1.. 8 .. 11 and 14will behave similarly for at and linH yalues_
V.LAme.
-
+
-
VIHAmin
-
-
-
VILmin
35
2.2
j t
2.7
2.7
!
~
4.0
j
!
3.5
IVee)
Gnd
VIHmax
265
220
-
a
Unit
28
-
-
-
-
VEE
Ma.
Min
-
VILAma.
+12SoC
Ma.
-
VIHAmin
TeST VOL TAGE APPLIED TO PINS LISTED aELOw:
+2SoC
-55 O e
VILmin
+2SoC
MCl0504F Test Limits
Min
VIHmax
-
i
-
-
-
-
+
t
t
ns
1
16
1
16
1,16
1
16
1
16
16
1
16
1
+1.11 V
-
t
-
j
-
1
16
-
-
-
16
1
t ~
t
4,5
+
4.5
t t
t ~
12
4,5
-
1
16
1
16
Pulse In
Pulse Out
-3.2 V
+2.0 V
3
3
13
13
3
13
12
4,5
16
t
1
j
-
3
13
3
13
MECL 10,000 series
TRIPLE 2·3-2 INPUT
OR/NOR GATE
MC10SOS
The Me 10505 is a triple 2-3-2 input gate.
Input pulldown resistors eliminate the need to
tie unused inputs to an external supply.
POSITIVE LOGIC
NEGATIVE LOGIC
18)4~317)
(8)4~3(7)
(9)5~2(6)
113)9~
(14) 10
~
(9)5~2(6)
(10)
(13)9~ 6
(11)
(14)10
(15) 11
7
(10)
(11)
(15) 11
(1)13~14(2)
(1)13~14(2)
(16)12~15(3)
(16)12~15(3)
Po = 30 mW typ/gate (No Load)
tpd '" 2.0 ns typ
Output Rise and Fall Time
== 3.5 ns typ (10% - 90%)
== 2.0 ns typ (20% - 80%)
Numbers at ends of terminals denote pin numbers for L package
(C. . . 620).
Numbers in parenthesis denote pin numbers for F package
(Case 650).
CAse
VCCI
VCC2
Vee
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250 C
Vee 1 = Vee2
V out NOR
+2.0 Vdc
~",t ii""'
r---
---,
V out OR
Coax
Coax
50
50
PROPAGATION DELAY
Unused outputs
connected to a
1QQ.880
-1.920 -1.855
-1.920 -1.655
-1.100
-1.100
-
-
V,Lmin
~.880
-1.920
-1.850
-1.820
-0.780
~,530
MC106015F T. . Limib
+25"1:
+125"1:
-li6"1:
Mm
V,H m ••
-'.635
-1.635
-
-1.850
-1.850
~.950
~.950
-
--
-
Rise Time
(2010_'
Fall Time
120 •• _ ,
18+1_
18-7+
18-+6.
'8-6'7+
'6+
'7_
'&-
7
7
6
6
7
6
7
6
-
-
1.0
2.0
!
TEST VOLTAGE APPLIED TD PINS LISTED BELOW:
VIHm8ll
V,Lmin
VIHAmin
V'LAm••
-
24
285
mAd,
-
-
-
-
~Adc
8
-
-
-
0.3
-
,.Adc
~.825
~,63O
~.825
-<>.630
-'.545
-1.545
Vd,
Vd,
-'.620 -'.820
-'.520 -1.820
-0.845
-0.845
-',600
-1.600
-
-
!
3.3
1.'
•
1
~
-5.2
-5.2
-5.2
Unit
~.780
2.9
VEE
-1.510
-1.475
-1.400
Ma.
-',525
-'.525
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
8
-8
-
8
-
-
-
-
Switching Times
(lQO.ohm la.jl
Propagation Delay
-1.106
-t.ooo
VILAmu
Mm
~.780
0.5
~.9;JO
~.930
V'HAmi"
-1.255
-
-
-
-
"'
-
-
-
1
-
-
--
VEE
IVeel
Gnd
-
8
'2
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Pul.ln
Pul.Out
-3.2 V
+2.0 V
8
7
7
6
6
'2
4.5
1
6
7
6
-
-
-
8
8
-
8
7
'2
'2
'2
'2
12
'2
12
'2
12
'2
II
f
'--_ _-'
TRIPLE 4-3-3 INPUT GATE
'
MECL 10,000 series
'--..._ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _____'
MC10506
The MC10506 is a triple 4-3-3 input NOR
gate. Input pulldown resistors eliminate the need
to tie unused inputs to an external supply.
POSITIVE LOGIC
181
NEGATIVE LOGIC
4
:~3171
1101
(11 )
7
111)
1131
1141
1:~2161
1151 11
1161
~~,
181
1101
191
191
1131
1141
171
1:~2161
Po'= 30 mW typ/gate (No Load)
tpd = 2.0 ns typ
1151 11
12~ 15131
1161
12~ 15
111 13
11) 13
121 14
121 14
Output Rise and Fall Time
== 3.5 nstyp (10% - 90%)
= 2.0 ns typ (20% - 80%)
13)
Numbers at ends of terminals denote pin numbers for L package
(Case 620).
Numbers In
(Case 650).
parenthesis
denote
pin
numbers
CASE
VCC1
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
for
F
package
VEE
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC
VCC1
=
VCC2
V out
50-ohm termination to ground 10-
+2.0 Vdc
catad in each scope channa' input.
"~m"~
All input and output cable. to the
scope ara aqual lengths of 50-ohm
coaxial cable. Wire langth should
ba <1/4 inch from T'Pin to input
pin and TP out to output pin. V out
il 2: 1 attenuated.
r------,
Coax
50
I
I
PROPAGATION DELAY
Input Pulse
= t- = 2.0 ±. 0.2 ns
t+
120 to 80%1
~----+1.11V
'---~
1-----+0.31 V
V out
See General Information section for packaging.
3-244
Unused outputs
connected to a
100-ohm resistor
to ground.
3:
o
..a
~
o
en
ELECTRICAL CHARACTERISITCS
Each full temperature range MECL 10.000
series circuit has been designed to meet the
:~3
de specifications shown in the test table,
after thermal equilibrium has been estab-
lished.
8
=.
7
The circuit is in a test socket or
,O~
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
11
12
'3~
through a 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
::l
-
9~2
mounted on a printed circuit board and
'4~15
gate. The other gates are tested in the
same manner.
::l
c:
~
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Voltst
@Test
VIHA min
VILAm . .
VEE
-55"c
-0.880
-1.920
-1.255
-1.510
-5.2
+2SoC
-0.780
-5.2
-0.630
-1.105
-1.000
-1.475
+l25 o C
-1.850
-1.820
-1.400
-5.2
Temperature
w
~
tTl
Under
Power Supply Drain Current
I nput Current
Svmbol
T."
log.c "".
24
~
Im H
VOH
-1920 -1.655
-1920 -1.655
VOL
Output Voltage
L99 l c "'"
Threshold Voltage
logiC "a"
Threshold Voltage
+2S0C
Min
t--
I
Typ
Max
I
17
21
265
0.5
1---05
-1.080 -0.880 -0.930
-1.080 -0.880 -0930
Output Voltage
logiC "0"
-55°C
Min I Max
'E
Ilnl
-1.100
VOHA
+l25 o C
Min
I
1 ..
T
-1.850
Unit
24
mAde
1,16
265
/-lAde
1,16
/-lAde
1,16
-0.780 -0.825
-0.180 -0.825
-0.630
-0.630
Vd,
Vd,
1-1.820
-1.820
-1.545
-1.545
Vd,
Vd,
-0.845
-0.845
-
Vd,
Vd,
-1.525
-1.525
Vd,
Vd,
-1.620
-1.620
-1.850
-1.635
-1.635
tVecl
Mo.
0.3
-0.950
-0950
-1.100
VOLA
I
Rise Time
1201080%.
Fall Time
1201080%)
VILmlR
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
-1.600
-16~1
-
2.9
1.0
1
SWitching Times.
(l00-ohm loadl
Propagation Delay
mall(
MC10506L Test limits
P,n
Characteristic
VIH
VIH max
Vll min
VIHAmin
1.0
'4_3+
3.7
10
2.9
3.7
3.7
'3'
4.0
1.1
3.3
4.0
4.0
11
,~
3
1.0
1 1
2.0
1
3.3
4.0
VEE
Gnd
1,16
1.16
4
1,16
9
1.16
1.16
1,16
1,16
4
9
Pulse In
3.7
14+3_
VILA max
1,16
Pulse OUI
-3.2 V
+2.0 V
1,16
1
1
1 1I 1
3:
n
.....
o
c.n
o
C)
ELECTRICAL CHARACTERISITCS
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been estab-
lished.
The circuit is in a test socket or
:~7
,o~
nO
"
'3~.
.
mounted on a printed circuit board and
transverse air flow greater than 500 linear
'4~
fpm is maintained. Outputs are terminated
through a l()().ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
'~~3
::J
# .. •./.~'
//&y
,
~
~.;.;.
,
~,
::J
c:
20
M ..
3 7
i
i j
2.
25
35
2S
35
-1.820
--5.2
-VEE
Unit
VIHm ••
mAd<
All Inputs
265
~Adc
220
~Adc
12
,..Adc
12
12
-0.630
+
-1.545
Vdo
+
Vdo
VIL min
VIHA min
VILAm..
(Veel
Gnd
12
--,-, I
.,9
+
•
12
:::
'oS
'oS
'oS
+
'oS
9
+
•
-1.525
-
-5.2
-5,2
-1.475
-1.400
31
+
-0.845
VEE
-1.510
M ..
03
-0.930
1.1
Min
I
VILA m..
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+ 12SoC
M ••
Os
Mo.
Inputs
Output
··Any Output
M",
6
LogIC "0"
Output Voltage
SWllct'llng Times (100 11 load'
6
VOH
Voltage
Min
D,S
I.n L
rut limit,
'25"1:
I
-
-
+
+
.,9
Vdo
+
+
',S
+
+
Vdo
Unit
+
12
'2
+1.11 V
3,9,11
~
Pulse In
Input
2.80r 13
2,8,13
Inpu1
j
3,9 or 11
Any InPlJ1
Any Input
+
Pu . . Out
-3.2 V
Co"npondlng
Ex.QR/Ex·NOA
Outputl
12
Corrnpondi r-.
Ex.QRJEx·NOR
OutpyU
I
Corresponding
EII.QRIEII·NQR
OutPUts
+
'oS
+
+2.0 V
',.
MECL 10,000 series
DUAL 4-5-INPUT
"OR/NOR" GATE
MC10509
POSITIVE LOGIC
NEGATIVE LOGIC
::::~3
(10)
6
(Ill
7
The MC10509 is a dual 4-5 input OR-NOR
gate which is pin compatible with the MECL III
MC1660L dual OR-NOR gate. All inputs are
terminated by a 50 k ohm resistor to VEE
eliminating the need to tie unus,ed inputs low.
2
(7)
(B)4~
(9) 5
3
(6)
(1319~
(10)
6
(Ill
7
2
(13)9~
(14) 10
.
(14110
14 (21
(15) 11
(7)
(6)
tpd = 2.0 ns typ
14 (2)
(15) 11
15 (31
(16) 12
(16112
(1113
(1113
Po == 30 mW tvp/gate (No Load)
15 (31
Output Rise and Fall Times
(10% to 90%) 3.5 ns
(20% to BO%I 2.0 ns
Numbers at ends of terminals denote pin numbers for L package
(Co. 6201.
Numbers
(Case
in
parenthesis
denote
pin
numbers
for
F
package
6501.
CASE
VCCI
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250C
veel - VCC2
+2.0 Vdc
Coax
Input
Pulse Generator
Input Pulse
t- "" 2.0 ±. 0.2 ns
(20 to 80%)
t+ ""
V out NOR
~"'m"'"'
r---
---,
I
V out OR
Coax
50
Coax
50
I
I
~
PROPAGATION DELAY
I
I
I
I
I
I
L ___
~__ J
:J;
50-ohm termination to ground 10
cated in each scope channel input
All input and output cables to the
seop • •,. equal lengths of 50-ohm
coaxial cable. Wire length should
Unused outputs
connected to 8
100-ohm resistor
to ground.
V out OR
0
1 jJF
-3 2 Vdc
Vee
b. <1/4 inch from TPin to input
V out NOR
pin and TP out to output pin. V out
is 2: 1 attenuated.
See General I nformation section for packaging.
3-250
3:
o
ELECTRICAL CHARACTERISTICS
..&
Each fuJi \a!1IP8rature range MECL 10,000
l81"iescircuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been estab~
'ished. The circuit is in a test socket or
mounted on
8
printed circuit board and
transverse-air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
same manner.
~
ocg
:~3
6
2
7
.~
'0
11
14
12
15
8::J
-
13
~,
::J
c::
(1)
c..
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
«Volts)
Test
T emperetur.
_55°C
+25 o C
(iI
+125 GC
CrJ
I\.)
....
Characteristic
5vmbot
Power Supply Drain Current
Input Current
'E
ImH
linl
High Output Voltage
VOH
Low Output Voltage
VOL
High ThreshOld Voltage
Low Threshold Voltage
VOHA
T..t
4
2
3
2
3
2
3
Min
Max
Min
16
Ty.
11
450
0.5
-1.080 -O.SIIO
-1.080 -O.SIIO
-1.920
1.655
-1.920 -1.655
1.100
-1.100
2
3
-
-1.635
-1.635
14+2+
14_2_
t4+3_
14-3+
2
2
3
3
1.0
3.7
'2+
t3+
3
'2_
t3-
2
3
VOLA
VEE
-1.510
-5.2
-0.780
-1.850
-1.106
-5.2
-0.630
-1.820
-1.000
-1.475
-1.400
M ••
Unit
1.
16
mAde
265
265
,!.lAde
M ••
05
-0.930
-0.930
-1.850
-1.850
-0.950
-0.950
Min
,!.lAde
0.3
-
-0.780
-0.780
-
1.620
-1.620
-
-
-0.845
-0.845
-
-
-
-1.600
-1.600
1.0
2.0
2.9
-
-0.825 0.630
-0.825 -0.630
-1.820 -1.545
-1.820 -1.545
Vdc
Vdc
Vdc
Vdc
-
Vdc
Vdc
VIH ma"
•
••
VILmin
•
-
Rise Time
(20 to l1li%1
Fall Time
(20'0l1li%1
-
-
-
2
l !
l !
4.0
1,1
t
Il
3.3
-
-1.525
-1.525
Vdc
Vdc
-
1.0
3.7
ns
-
-
~
I
VEE
-
8
8
-
8
-
1.16
-
8
8
8
8
1.16
1.16
1,16
1.16
4'
8
8
1.16
1.16
4
-
~
-
-
-
-
(Veel
Gnd
1.16
VILA ma.
-
-
-
.-
4.0
VIHA min
~-
SWitching Times
1100 ohm load)
Propagation Delay
I
-5.2
TEST VOLTAGE APPLIED TO PINS BELOW:
+125 o C
+25o C
-55"<:
8
•
VIHAmi"
-1.255
VILAnNIC
-o.SIIO
V'Lmin
-1.920
MC10601L T_ Limits
Pin
Under
U1
VIH ma.
1.16
4
4
-
8
8
1.16
1.16
Pulse In
Pulse Out
-3.2 V
+2.0 V
2
2
3
3
2
3
2
3
8
1.16
•
I
I
ELECTRICAL CHARACTERISTICS
Ea<;h full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 1()().ohm resistor to -2.0 IIolts.
Test procedures are shown for only one
gate. The other gates are tested in the
same manner.
B3=t=
s:
(')
....
o
•
1
10
•
·
V
11
lJ~ 2
"IS
I.
c.n
~
8::J
J
~~-"
1
:::,
::J
c:
~
-'.
~
F SUFFIX
CERAMIC PACKAGE
CASE 650
TEST VOLTAGE VALUES
(Volts)
@Test
Temperature
W
N
(JI
r-.)
I
Pin
Under
'E
Teo.
12
Input Current
IIIlH
8
High Output Voltage
VOH
CharactenSllC
Power Supply Oram Current
Symbol
ImL
Low Output Voltage
VOL
7
High Threshold Voltage
VOHA
Low Threshold Voltage
VOLA
6
Ma.
Min
16
450
0.5
-1.080
-1.080
-1.920
-1920
-1.100
t2O'.8O%1
-0.580
-0.930
-0.930
-1.655
-1.655
-1.850
-1.850
-0.950
-0.950
-1.850
-1.820
VIHA min
-1.255
VILA max
-1.105
-1.000
-1.475
Ma.
Unit
11
14
16
mAdc
265
265
/JAde
Min
0.3
-0.720
-0.720
-1.620
-1.620
VIH max
VILmin
VIHA min
'6-
6
'7-
!
!
1.1
7
29
l
l
3.3
VILA ....ax
/lAdc
-5.2
-5.2
I
-5.2
VEE
tVee l
Gnd
12
12
4,5
4,5
12
12
12
4,5
4,5
4,5
4,5
4,5
Vdc
Vdc
Vdc
Vdc
-0.845
Vdc
Vdc
12
12
4,5
4,5
Vdc
Vdc
12
12
4,5
4,5
-3.2 V
+2,0 V
12
4,5
-1.525
-1.525
12
12
Pulse In
'6+
'7+
-1.400
VEE
-0.825 0.580
-0.825 -0.580
-1.820 -1.545
-1.820 -1.545
-0.845
-1.600
-1.600
2.0
I
-1.510
TEST VOLTAGE APPLIED TO PINS BELOW:
M ••
05
-0.830
-0.830
1.0
t9+6+
t9-6_
t9-7+
Fall Time
+ 125°C
Typ
-1.635
-1.635
t9+7_
(20 to 8O%t
-1.920
-0.720
+125 o C
+2So C
-5SoC
Min
SWItchmg Times
(100 ohm load)
Rise Time
Vil min
-0.830
+25 o C
MC10509F Test Limits
-1.100
Propagation Delay
VIH max
-5SoC
8
I
Pulse Out
MECL 10,000 series
TRIPLE LINE RECEIVER
(HIGH COMMON MODE)
MC10514
The MC10514 is • triple line receiver designed for
use in sensing differential signals over long lines. An
active current source and translated emitter fOllower
inputs provide the line receiver with a oommon mode
noise rejection limit of one volt in either the positive
or the negative direction. This allows a large amount
NEGATIVE LOGIC
POSITIVE LOGIC
of common mode noise immunity for extra long lines.
Another feature of the MCt0514 is that the OR
outputs go to a logic low level whenever the inputs are
left floating. The outputs are each capable of driving
(8)4~2(6)
(a)4~2(6)
(9)5~317)
(9)5~3(7)
9~6 (10) (13) 9~6
(10)
(14)10~7 (11)(t4)tO~7
(11)
(13)
(16)12~t412)
l()(k)hm transmission lines.
This device is useful in high speed central processors.
minicomputers, peripheral controllers, digital commu·
nication systems. testing and instrumentation systems.
The MC10514 can also be used for MOS to MECL
interfacing and it is ideal as a sense amplifier for MOS
It6)12~1412)
RAM's.
(1)13~t513) (1)13~1513)
~11(15)
~11(15)
Vea
A Vee reference is provided which is useful in
making the MC10514 a Schmitt trigger, allowing single-
Vae
J
[CAsEivcc11vcc2JVEE
620
ended driving of the inputs, or other applications where
a stable reference voltage is necessary.
Pin 1 Pin 16 Pin 8
tpd":: 2.4 ns typ (Single Ended Input)
tpd '" 2.0 ns typ (Differential Input)
PO'" 145 mW typ!pkg (No Load)
Numbers at ends of terminals denote pin numbers for L package (Case 620),
Numbers in parenthesis denote p'in numbers for F package (Case 650).
SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS il250C
PROPAGATION DELAY
Coax
50
Input pulse
t+
Unused outputs
connected to 8
100-0hm resistor
to ground.
= t - = 2.0
±. 0.2 ns
(20 to 80%)
I
I
o--~f---t----l VB B
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cable. Wire length should
be
114 inch from TPin to input
pin and TPoutto output pin. V out
1.2: 1 attenuated.
<
L
-1]-
I
I
One Input from each gate must
J
I0
J O l jJ F
be tied to V SB during testing
1jJF
- 32 Vdc
VEE
See General Information section for packaging.
3-253
ELECTRICAL CHARACTERISTICS
s
Each full temperature range MECL 10,000
....
C')
series circuit has been designed to meet the
de specifications shown in the test table,
o
....
after thermal equilibrium has been estab-
0'1
lished. The circuit is in a test socket or
4~2
mounted on a printed circuit board and
~
5~3
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
input, or for one set of input conditions.
Other inputs or outputs are tested in the
sarne manner.
L SUFFIX
9~6
"""
10~7
12~t4
13~15
~"
VBB
8
CERAMIC PACKAGE
CASE 620
:J
!Z.
:J
c:
ct>
C-
TEST VOLTAGE VALUES
(Volts)
@IT.lt
Temperature
-5SoC
+2SOC
+12SoC
CharKteristic
W
r\J
Symbol
Power Supply Drain Current
Input Current
Logic "1" Output Voltage
BO
logic "1 'Threshold Voltage
VOLA
Aeference Voltage
VBB
Common Mode AeJection Test
A ise Time (20% to 80%1
Fall Time (20% to 80%1
I
3.
1.5
-0.880
-0.880
-1.655
-1.655
Logic "0' Threshold Voltage
Switching Tintel (l00-ohm Load)
Propagation Delay··
M..
linH
VOHA
I
Min
ICBO
VOH
-1.080
-1.080
-1.920
-1.920
-1.100
-1.100
VOL
Logic "0" Output Voltage
MC10514L T.t Limits
+2SoC
-6SoC
'E
01
"'"
Pin
Under
T ..,
Min
-1.080
-1.080
-0.830
-0.830
VOL
-1.920
-1.920
-1.655
-1.655
-0.930
-0.930
-1.850
-1.850
Min
M..
Min
t4+2+
t4_2_
t4+3_
t4_3+
'2'
'3'
'2_
'3_
-1.510
-1.475
-1.400
From
+0.170
+0.280
+0.420
-1.105
-1.000
Pm
11
-0.920
-O.B50
-0.B20
-I
-1.830
-1.720
-2.920
-1.580
-2.820
VIHL·
Vlll·
-2.B50
I
VEE
-5.2
-5.2
-5.2
VEE
(Veel
Gnd
8
1,16
3.
mAde
4,9,12
5.10.13
45
1.0
-0.780
-0.780
-1.620
-1.620
45
/JAdc
9,12
5,10,13
'0
-0.630
-0.630
-1.545
-1.545
/JAdc
9,12
5,10,13
8,'
9,12
4
5,10,13
5,10,13
8
8
9,12
5,10,13
5,10,13
Min
-0.B25
-0.825
-1.B20
-1.820
M..
-0.845
-0.845
9,12
Vdc
Vdc
9,12
4
Vdc
Vdc
Vdc
-1.620
-1.620
-1.820
-1.820
Ty,
M..
Min
M..
1.0
I
25
4.0
'5
21
3.5
~
~
+
·VI HH = Input logic "1" level shifted positive one volt for common mode rejection tests.
VILH = Input logic "0" level shifted positive one volt for common mode rejection tests.
VIHL = I nput logic "1" level shifted negative one volt for common mode rejection tests.
VILL = Input logic "0" I~vel shifted negative one volt for common mode rejection tests,
• -Delav is 2.0 ns with differential input.
VIH malt
Vdc
Vdc
-1.525
-1.525
-0.825
-0.825
+
-1.240
Unit
Vdc
Vdc
-1.120
-0.580
-0.580
-1.545
-1.545
•
-1.255
TEST VOLTAGE APPLIED TO PINS BELOW:
-1.230
-0.720
-0.720
,
VIHH-I V'lH-l VIHl-1 VILL
-1.920
-1.850
-1.820
+12So C
-1.600
-1.600
VOH
VBB
-0.880
-0.780
-0.630
35
-1.850
-1.850
-1.350
VllAm.x
M..
-0.950
-0.950
-1.320
VIHA min
28
-0.930
-0.930
-1.440
VIL mill
Ty,
-1.635
-1.635
11
VIHmax
VIL min
VIHA min
VILA max
9,12
9,12
9,12
9,12
VB.
VIHH·
VllH·
1,16
5,10,13
5,10,13
1,16
1,16
1,16
1,16
5,10.13
5,10,13
1,16
1,16
5,10,13
1,16
1,16
1,16
Vdc
Vdc
1,16
1,16
Vdc
Vdc
Pulse In
4
j
1.16
1,16
1,16
j
Pulse Out
5,10,13
j
-3.2 V
+2.DV
8
1,16
j j
ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
(')
.....
o
U1
.....
.;a
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
~
8~6
mounted on a printed circuit board and
transverse air flow greater than 500 linear
9~7
fpm is maintained. Outputs are terminated
13~10
through a 100-ohm resistor to -2.0 volts.
14~11
Test procedures are shown for only one
16~2
1~3
~15
input, or for one set of input conditions.
Other inputs or outputs are tested in the
same manner.
nO
::J
d.
::J
c:
F SUFFIX
CERAMIC PACKAGE
CASE 650
VBB
CD
Cl.
TEST VOLTAGE VALUES
(Volts)
@Test
T emper0ill1ure
-5SoC
+25"c
+12SoC
Pon
Under
Chaf.:te,istic
eN
r:.,
C11
C11
I
Power Supply Dram Current
Input Current
-SSoC
Symbol
T ...
'E
12
3.
IlnH
8
SO
1.5
-0.880
-0.880
Min
ICBO
LogiC "1" Output Voltage
VOH
LogiC "0" Output Voltage
VOL
L(i9lc "1" Threshold Vall.
LogiC "0" Threshold Voltage
MC10S14F Test Limit5
"'2So C
-1.080
-1.080
-1.920
-1.920
M..
-1.655
-1.655
-1.100
-1.100
VOHA
Min
15
-1.440
-1.320
-1.350
6
,
VOL
6
-1.080
-1.080
-1.920
-1.920
-0.830
-0.830
-1.655
-1.655
-0.930
-0.930
-1.850
-1.850
Min
M..
Min
1.0
Switch"" TinMI l100-ohm lOMt11
Prop8pIIOn Deley··
....,-
18+6+
18+718-7+
Rise Time (20% to 80%1
Fall Time (20% to 80%1
'B'
'"'B"-
~
1.5
VIHH·
-1.920
-1.850
-1.820
-1.255
-1.105
-1.000
-1.510
From
+0.170
-1.475
-1.400
Pm
+0.280
+0.420
IS
VBS
M..
Unit
39
mAdc
8,13,16
1.9,14
45
45
10
j.lAdc
13,16
1,9,14
j.lAd..:
-0.630
-0.630
Vd,
Vd,
8
13,16
13,16
13,16
8
-1.545
-1.545
Vd,
Vdc
Vd,
Vd,
13,16
8
13,16
Vd,
Vd,
13,16
1,9,14
1,9,14
1,9,14
1.9,14
1,9,14
1,9,14
1,9,14
1,9,14
1,9,14
1,9.14
Mon
-0.780
-0.780
-1.620
-1.620
-0.825
-0,825
-1.820
-1.820
-0.845
-0.845
-1.230
-0.720
-0.720
-1.620
-1.620
TVO
2.5
+
21
M..
4.0
-1.525
-1.525
-1.240
V'LH-l VIHL -I YILL -,
-0.920
-0.850
VEE
-1.830
-2.920
-5.2
-2.850
-5.2
-0.82"l-1.580~ -2.820~ -5.2
-1.720
TEST VOLTAGE APPLIED TO PINS BELOW:
3S
-1.600
-1.600
V88
VBB
-0.880
-0.790
-0.630
M..
-0.950
-0.950
VOH
VILAm ...
"'12So C
1.0
Common Mode Rejection Test
VIHAmin
28
-1.635
-1.635
VOLA
VILmm
TVO
-0.930
-0.930
-1850
-1.850
Reference Voltage
VtHmaK
-0.825
-0.825
-1.820
-1.820
-1.120
-0.580
-0.580
-1.545
-1.545
Min
M..
+
3.S
~ ~ ~
·VIHH::: Input logic "1" level shifted positive one volt for common mode rejection tests.
VILH = Input logic "0" level shifted positive one volt for common mode rejection tests,
VIHL = Input logiC "1"level shifted negative one volt for common mode rejection tests.
VILL = Input logic "O"level shifted negative one volt for common mode rejection tests.
··Delay is 2.0 ns with differential input,
VIHmali
Vll min
VIHA min
VllAmu
13,16
13,16
13,16
Vd,
Vd,
Vd,
Vd,
Vok
Puis. In
8
j
j
Pul.-Oul
1,9,14
j
VIHH-
VllH-
VIHl e
Ville
VEE
12
12
8,12
12
12
12
12
12
12
12
12
12
1VCC'
Gnd
4.5
4.5
4.5
4.5
4.5
12
12
12
12
-3,2 V
+2.0 V
12
45
j j
L--..-;f
(SI
'--------
MC10515
POSITIVE LOGIC
54~
(91~
MECL 10,000 series
"
QUAD LINE RECEIVER
NEGATIVE LOGIC
2
(SI
(SI
54
~~
(gl~
(1117~
(1117~
(14110~
(14110~
(10IS~3(71
14 (21
(15111
(1113~
Vse
2
(SI
(1016~3(71
(15111
(16112~
The MC10515 is a quad differential amplifier
designed for use in sensing differential signals
over long lines. The base bias supply (VBB) is
made available to make the device useful
as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC10515
with excellent common mode noise rejection.
If any amplifier in a "ackage is not used, one
input of that amplifier must be connected to
VBB to prevent upsetting the current source
bias network.
14 (21
(1113~
15(31
(16112
9 (131
~15(31
L - g (131
Vee
Numbers at ends of terminals denote pin numbers for L package
(Casa 620).
N umbers
in
parenthesis
denote
pin
numbers
for
F
package
tpd = 2.0 ns typ
Po = 110 mW tvp!pkg (No Load)
(Case 650).
CASE
VCCI
VCC2
VEE
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 250 C
+2.0 Vdc
Vout
Coax
PROPAGATION DELAY
50
Input Pulse
t+ = t- = 2.0 ±. 0.2 ns
Unused outputs
(20 to SO%I
connected to 8
1 OO"hm resistor
V out
to ground.
50-ohm termination to ground located in each scope channel input.
One input from each gate must be tied to
dur Ing testing.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable, Wire length should
be <1/4 inch from TP in to input
pinandTPouttooutputPin. V out
is 2: 1 attenuated.
See General I nformation section for packaging.
3-256
Vee
3:'
n
....
ElECTR ICAL CHARACTER ISITCS
Each full temperature range MECL 10,000
• ries circuit has been designed to meet the
~
....
trI
:=::t>---2
:=::t>---
de specifications· shown in the test table,
after thermal eQuilibr~um has been established. The circuit is in a test socket or
n
o
:::l
J.
mounted on a printed circuit board and
transverse air flow· greater than 500 linear
fpm is maintained. Outputs are terminated
::!.
10~ I.
:::l
C
11
(I)
13~15
through a 100-ohm resistor to -2.0 volts.
C:.
~9
12
Test procedures are shown- for only one
v ••
gate. The other gates are tested in the
same man ner.
~.
i'
"f1~~~nr Ii
j
I'
L SUFFIX
CERAMIC PACKAGE
CASE 620
w
li'T ...
r:.,
Temperature
U1
-ssOC
'"
+25"c
+12SoC
Charect.,iltic
Power SupplV Dr.in Current
Input Cur,ent
Symbol
Pin
Und.r
Test
-!SoC
IE
8
29
I," H
4
165
leBO
4
1.5
Min
-
Logic ",.. Output Voltage
VOH
2
-UlBO
-O.BBO
-0.930
Logic "0" Output Voltage
VOL
2
2
-1.920
1.100
-1.655
-1.850
-0.950
Logic "'" Threshold Voltage
logic "0" ThreshOld Voltage
Reference Voltage
VOHA
Propagation Delav
Fall Time (20% to 80%1
-1.850
-1.105
-0.630
-1.820
VIL min
4,7,10,13
VIHA min
VILA max
VB8
-
7,10,13
-
7,10,13
-
-
5,6,11,12
4
-
VIH max
Unit
26
-
29
mAde
95
1.0
IJAdc
JJAdc
-0.630
-1.545
Vd,
7,10,13
4
4
7,10,13
-
Vdc
Vd,
-
-1.820
-0.845
-1.000
-
7,10,13
2
-
-1.635
-
-1.600
-
-1.525
Vdc
-
7.10,13
4
Vee
9
-1.440
-1.320
-1.350
-1.230
-1.240
-1.120
Vd,
-
-
-
Min
Max
Min
M ••
Min
Max
1.0
3.5
3.5
1.0
1.0
2.9
2.9
1.0
14_2+
14+2_
2
2
'2+
'2_
2
2
~
3.9
1.1
3.3
3.9
1.1
3.3
~
-6.2
~
-6.2
TEST VOLTAGE APPLIED TO PINS L1STED BELOW,
VOLA
Switching Tjmes~ l000hm load)
Rise Time (20% to 80%1
-1.510
M ••
-0.780
-1.620
-1.400
9
-1.255
Min
-0.825
-1.475
-1.920
Max
95
1.0
VEE
~
-0.880
-0.780
+125o C
+25"c
Max
V88
From
Pin
V,L min
MC10515L Test Lilnits
Min
TEST VOLTAGE VALUeS
V,HA min
V'LAm ..
V,HmllX
4.0
4.0
4.4
4.4
4
-
Pul.ln
Pul.Out
ns
4
2
~
~
--
~
-
1Veel
GNI
8
1.16
5.6.11,12
8
5,6.11,12
8.4
1.16
1,16
5.6,11.12
8
1,16
5,6,11.12
5,6,11.12
8
1,16
8
1.16
5,6.11,12
8
1,16
5.6,11,12
8
1,16
-3.2 V
+2.0 V
8
1,16
5,6,11.12
-
VEE
l
~ ~
..
~
(")
..
~
ELECTRICAL CHARACTERISITCS
Each full temper.ture range MECL 10.000
:~6
series circu it has been designed to meet the
de specifications- shown in the test table,
"~
10~7
after thermal equilibrium has been estab-
lished.
The circuit is in a test socket or
8::J
!:!.
14~2
mounted on a printed circuit board and
transverse air flow greater than 500 linear
'~~
fpm is maintained. Outputs are terminated
through a l~ohm resistor to -2.0 volts.
::J
c:
(D
3
Co
16~13
v ••
Test procedurlts are shown for onlv one
gate.
U'I
~
The ot!"!er gates are tested in' the
same manner.
F SUFFIX
CERAMIC PACKAGE
CASE 650
w
~
OT ...
'hmper.ture
U1
CO
VILmin
-55"c
.2$"c
_55°C
U ....,
Ch.rKt."ic
Power Supply Drain Current
I nput Current
SVmbol
IE
II~ H
Toot
12
8
IC80
8
Logic "1" Output Volt.
VOH
6
Logic "e" Output Volt....
VOL
6
Logic "1" Threshold VOl..,.
VOHA
6
Logic "0" Threshold VOlt.
VOLA
Reference Voltage
V88
13
'8-6.
6
6
6'
8
Switching Times! 1000hm loed)
PropagahGn Del.,.
Rise Time·i2O% too ~I
hI! Time (20% to ..,.,
'8-6'6.
t&-
Min
I M~'
MC10515F T_ Limits
+25OC
+125o C
-1.440
Min
Mo.
1.1
1.1
I
3.3
3.3
VIL min
mAde
l,B,l'.14
#JAde
1,11.14
#JAde
-1.525
-1.120
-1.510
-1.475
-1.400
V_
VEE
From
r-:rr-
Pin
13
~.2
~
TEST VOLTAGE APPLIED TO 'INS LISTED BELOW,
VIH rna
165
1.5
-1.080 I -0.880 I -0.930
-1.920 I -1.655 I -1.850
-1.100
-0.950
-1.255
-1.105
-1.000
-1.920
-1.850
-1.820
+l25 DC
Pin
TEST VOLTAGE VALUES
VILA_
VIHA min
Vde
1.11,14
Vde
8
I
\lIHA min
VILA
1.11.14
8
Vde
1,11,14
1,11,14
Vde
1.11.14
8
Vde
V_
VEE
(Vee)
Gn1I
9.10.15.16
9.10.15.16
9.10.15.18
12
12
8.12
12
12
12
4.5
4.5
••5
4.5
4.5
4.5
9.10.15.16
9.10.15.18
9.10.15.16
9.10.15.16
9.10.15.16
Pul.ln
~
mb:
Pu"Out
'.10.15.16
8
!
1
12
4.5
4.5
12
-3.2 V +2.0 V
'2
4.5
! l l
MECL 10,000 series
TRIPLE LINE RECEIVER
MC10S16
The MC10516 is a triple differential amplifier
designed for use in sensing differential signals over long
POSITIVE LOGIC
lines. The base bias supply (VSS) is made available
to make the device useful as a Schmitt trigger,
or in other applications where a stable reference
NEGATIVE LOGIC
voltage is necessary.
(8)4~2
(6)
(9)
(7)
5
3
(8)4~2 (6)
(9)
5
3
17)
(13)9~6
110)
113)9~6 110)
7
1111
(14) 10
(14)10
1'6)'2~'412)
(1) 13
15
Active current sources provide the MC10516 with
excellent common mode noise rejection. If any ampli·
fier in a package is not used, one input of that amplifier
must be connected to VaB to prevent upsetting
the current source bias network.
Complementary outputs are provided to allow driv-
7
1111
ing twisted pair lines. to enable cascading of several
1'6)'2~'4(2)
11113
(3)
amplifiers in a chain, or simply to provide complement
outputs of the input logic function.
1513)
L - 11115 )
L-'11'5)
Vaa
Vaa
Numbers at ends of terminals denote pin numbers for L package
(Case 620),
Numbers in
(Case 650).
parenthesis
CASE
denote
pin
numbers
VeCl
for
F
tpd
= 2.0
ns typ
Po = 85 mW typ/pkg (No Load)
package
VEE
620
Pin'
Pin 16
Pin 8
650
Pin 5
Pin4
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C
50-ohm termination to ground located in each scope channel input.
VCC1 = VCC2
Vin
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cable. Wire length should
be <1/4 inch from TP in to input
pin and TP out to output pin. V out
is 2: 1 attenuated.
""dJ'"
r-
PROPAGATION DELAY
V out
+2.0 Vdc
--,
V out
Coax
50
Coax
50
Input pulse
t+
Unused outputs
connected to a
l00-ohm resistor
to ground.
= t- = 2.0 ±.
0.2 ns
(20 to aO%)
I
I
IlOne input from each oate must
I
L.
J;"
....J
"'-11::,"
Vee
See General I nformation section for packaging.
3-259
betted to VBBdurtngtestlng.
s:
n
..A
Each full temperature range MECL 10,000
4
lished.
=:::.r.:t:='
5 - 3
9~6
after thermal equilibrium has been estab-
12~t4
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
same man ner.
'3~15
0')
8
,
::J
~,
.,1\
10~7
The circuit is in a test socket or
mounted on a printed circuit board and
U1
-
ELECTRICAL CHARACTERISITCS
series circuit has been designed to meet the
de specifications shown in the test table,
o
..A
::J
c:
(1)
L SUFFIX
"
CERAMIC PACKAGE
CASE 620
Q.
~11
vBe
TEST VOLTAGE VALUES
tVolts)
@Test
Temperature
-SSoc
-t-2SoC
+ 12SoC
w
~
0)
o
Char~tenstM:
Symbol
Power Supply Drain Current
Ie
Input Current
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low'Threshold Voltage
Reference Voltage
SWitching Times
t l00-ohm load)
Propagation Delay
Pin
Under
Test
-SSoC
Min
Min
Unit
mAdc
95
95
,u.Adc
1.0
/JAdc
-0.630
-0,630
-1.545
-1.545
Vdc
Vdc
4
9,12
9,12
4
Vdc
Vdc
9,12
4
4
9,12
-0,880
-0.880
-0930
-0,930
VOL
2
3
-1.920
-1.920
-1.655
-1.655
-1.850
-1.850
..
VOHA
2
3
-1.100
-1.100
-
-0,950
-0,950
-
-
-
-
-1.635
-1.635
-.
-
-1.320
-1.350
RlseT.me
120% to 80%)
Fall Time
120% to 80%1
'213-
2
.3
2
3
-
Min
1.0
-
..
-0.780
-0.780
-0825
-0.825
-1.620
-1.620
-1,820
-1.820
-1.525
-1.525
Vdc
Vdc
-1.240
-1.120
Vdc
M ••
4.0
Min
TVO
M..
3,5
1.0
2.0
2.9
1.0
!
I
j ~ ~
1.1
~
3.3
!
-1.255
~
j ~
4,4
ns
j
V'Lmin
4,9,12
VIHAmin
V,LA max
9,12
V2
-
9,12
-
-1.230
M ••
4
9,12
-1.600
-1600
1.0
VIH max
Vdc
-
Min
~
~dc
-0.845
-0.845
Min
3,9
11
24
-1.080
-1.080
-1.440
-1.400
M..
2
3
2
3
-1.000
21
VOH
11
-1.820
14
ICBO
VBB
VILAmax
.-1.510
-1.475
VBB
From
-1.105
M ..
165
1.5
VOLA
VIHA min
TVO
4
24
VILmin
-1.920
-1.850
Pin
Vee
-5.2
~
~
TEST VOLTAGE APPLIED TO PINS BELOW:
+125 o C
+250 C
M ••
IlnH
2
2
3
3
-0,880
-0.780
-0.630
MC10516L Ted Limits
8
4
t4+2+
'4-2t4+3_
t4-3+
12+
'3+
VIHmalII
-
-
9,12
9,12
-
-
-
-
4
"
-
-
4
4
-
-
4
Pulse In
Pu •• Out
4
2
2
3
3
j
2
3
2
3
VBB
Vee
Gnd
5,10.13
5,10,13
8
8
1.16
1,16
5.10.13
8,4
1,16
5.10.13
5,10,13
8
8
5,10,13
5,10,13
8
8
1,16
1,16
1,16
1,16
5,10,13
5,10,13
8
8
1,16
1,16
5,10,13
• 5.10.13
8
8
1.16
1,16
5.10.13
8
1,16
-3,2 V
+2.0 V
8
.1,16
5.10.13
j j j
3:
n
o
~
U'I
~
ELECTRICAL CHARACTERISITCS
0)
8
Each full temperature range MECL 10,000
.=::tt=6
13=::tt=10
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
~
9 - 7
14
mounted on a printed circuit board and
transverse air flow greater than 500 linear
11
16~2
Test procedures are shown for only one
::J
c:
(I)
F SUFFIX
Co
CERAMIC PACKAGE
1~3
~'5
v ••
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 volts.
::J
~.
CASE 650
gate. The other gates are tested in the
same man ner.
TEST VOL T AGE VALUES
(Volts)
@T.st
Temperature
w
~
en
....
Characteristic
I SYmbol I
J,:;., I
rest
Min
_55°C
I Max
I
Min
1
+250 e
Tvp
17
11
Low Output Voltage
VO H
VOL
VOHA
Low Threshold Voltage
VOLA
Reference Vortage
V88
SWitching Times
fl00-ohm load)
Propagation Delay
Rise Time
(20% to 80'"
16+
'7+
Fall Time
120% to 80%.
17_
'6_
From
-1.475
~
-5.2
+ 125°C
-0.630
-1.820
-1.000
-1.400
Pin
15
I
I
Maw:
+125 0 e
M
'"
Ma.
Unit
Va8
24
mAde
1,9.14
12
4,5
j.lAdc
12
4,5
1.0
1.0
j.lAdc
1.9,14
1.9,14
8,12
4,5
1,9,14
12
12
4,5
4,5
1,9,14
1,9,14
12
12
13,16
1.9,14
1,9,14
12
12
4,5
4,5
4,5
4,5
13.16
1,9,14
1,9,14
12
12
4.5
4,5
1,9,14
12
4.5
-3.2 V
+2.0 V
12
4,5
-0.630
-0.630
Vd<
Vd<
13.16
-1.920
-1.655
-1.655
-1.850
-1.850
-1620
-1620
-1.820
-1.820
-1.545
Vd<
Vd<
13,16
9
Vd<
Vd<
13,16
1~40
-0.845
-1600
-1600
Moo
10
~
1.1
~
-1.545
-0.845
-0.950
~50
Max
-1.525
-1.525
Vd<
Vd<
Vdc
1.9,14
13,16
8
13,16
13,16
-1230
-1240
-1.120
TyO
M. .
Min
Max
Pulse In
20
2.9
-
8
-
-
j
1Veel
Gnd
95
21
-0825
-0825
-1350
VEE
95
-0.180
-1.320
~
TEST VOLTAGE APPLIED TO PINS BELOW:
-0.780
-1.635
-1.635
7
7
VEE
-1.510
-0930
-0930
-1.100
-1.100
6
6
VS8
-1.255
-1.105
-0.880
-0.880
Min
t8+6+
18-6_
18+7_
18-7+
VILA ma.
-1.850
-1.080
-1.080
-1.920
High Threshold Voltage
VllmIR
-1.920
-0.780
Me 10516F Test Limits
-,High Output Voltage
VIHmax
-0.880
VIHAmin
-SSoC
+250 C
3.3
*~
-
-
-
-
j
j
Pul.Out
1,9,14
j j j
MECL 10,000 series
DUAL 2-WIDE 2-3-INPUT
"OR-AND/OR-AND-INVERT"
GATE
MC10517
The Me 10517 is a general purpose logic element designed for use in data control, such as
digital multiplexing or data distribution. Input
E is common to both gates.
Po = 100 mW typ/pkg (No Load)
tpd = 2.3 ns typ
Output Rise and Fall Times:
'" 3.5 ns (10% to 90%)
= 2.2 ns (20 0 ,," to 80%)
POSITIVE LOGIC
(8)
NEGATIVE LOGIC
4
(8) 4
(9)
(9)
L.~.r-~"",,,
__
2
('0)
(6)
r--,--~~-~
6
9
(14) 10
('5)
3 (71
2 16)
110) 6
( 11)
('3)
5
3 (7)
Ill)
7
113)
9
1'4) '0
115) 11
11
14 (2)
' - - . . - -.....- - 1 4 (2)
15 (3)
~~--<>15
(16) '2
(1) '3
13)
116) 12
111 13
Y
Y = (A + B) • (e + 0 + E)
X
X = (A + B) • (C + 0 + E)
= (A
= (A
• S) + (C. 0 • E)
• B) + (C. 0 • E)
Numbers at end of terminals are pin numbers for L package (Case 620),
Pin 8
Pin 12
Numbers in parenthesis denotes pin numbers for F package (Case 650),
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C
Vee 1 = VCC2
"·'i It,,·,
+2.0 Vdc
V out
OR·AND
INVERT
V out
OR AND
PROPAGATION DELAY
r---- -----,
(~__~~~I~~
50
I
I
50
~~---+1.11
V
--~~-+0.31
V
V out OR-AND
Input Pulse
t+ = t- = 2.0! 0.2 ns
(20 to 80%)
t+
t-
9roun~l~
each scope channel
50-ohm termination to
cated
In
Input
All input and Output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 Inch from TP in to Input
pinand TPoutto output pin. V out
is 2:1 attenuated.
-
-
-h-__
V out OA·ANQ·INVERT
Unused outputs
connected to a
100-ohm resistor
to ground.
J
I-= 0.1 ~F
-3.2 Vdc
VEE
See General Information section for packaging and maximum ratings.
3-262
ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECL 10,000
C')
series circuit has been designed to meet the
de specifications shown in the test table,
~
lished.
~
4.-r---....
after thermal equilibrium has been estab-
~
The circuit is in a test socket or
......
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a l00-ohm resistor to -2.0 volts.
n-O
2
6
-
Test procedures are shown for only one
gate. The other gates are tested in the
same manner.
9
10
11
~14
15
12
::J
....
::J
c:
~
L SUFFIX
CERAMIC PACKAGE
CASE 620
13
TEST VOL TAGE VALUES
(Volts)
@Test
w
VIH max
VIL min
VIHA min
VILA max
VEE
-5SoC
-0.830
-1.920
-1.255
-1.510
-52
+2SoC
-0.120
-1.850
-1 105
-1475
-52
+ 125°C
-0.580
-1.820
-1.000
-1400
-52
Temperature
'"
0>
W
Characteristic
Symbol
Power Supply Drain Current
Inpul Current
Pin
Under
Teo.
MC10517L Test limits
+12SoC
+25 oC
-55°C
Min
Mox
'E
29
lin H
450
630
'm L
LogiC "1" Output Voltage
LogiC "0" Output Voltage
LogiC "1" Threshold Voltage
LogIC "0" Threshold Voltage
Min
TVp
Ma.
20
26
Min
265
370
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Ma.
Unit
29
265
370
mAdc
0.5
05
-0.930
_0.930
-0.720
-0.720
-0.825
-0.825
-0.580
-0.580
Vdo
Vdo
VOL
-1.655
-1.655
-1.620
-1.620
-1.820
-1.920
-1.850
-1.850
-1.545
-1.545
Vdo
Vdo
-0.845
-0.845
-0.950
-0.950
VOLA
-1.600
1.1
3.5
1.4
2.3
AlseTlme
(201080%1
'2+
13+
1.0
+
4.1
+
1.1
22
4.0
Fall Time
(20 to 80%)
'2_
'3_
+
~
~
~
-
'--
2
3
-
i
i
~
3.4
~
1.2
3.5
0.9
4.1
i
i
~
~
j
1,16
1.16
1,16
1 16
4,9
1.16
1,16
4,9
4,9
4.9
+1.11 V
t4+2+
14_2_
14+314-3+
1.16
4,9
4.9
Vdo
Vdo
SWitching Times (l00-ohm load)
Propagation Delay
(Vee)
Gnd
8
4,9
Vdo
Vdo
-1.525
-1.525
-1.600
VEE
1,16
1.16
-0.830
-0.830
-1.635
-1.635
VILA mall;
/JAdc
/JAdc
-1.920
-1.100
-1.100
V,HA min
1,16
1,16
-1.080
-1.080
VOHA
VIL min
/JAdc
/JAdc
VOH
-1.820
VIH max
j
4,9
1,16
1,16
Pulse In
-3.2 V
+2.0V
8
1.16
j
Pulse Out
j
j
s:
ELECTRICAL CHARACTERISTICS
...o
Each full temperature range MECL 10,000
("')
series circurt has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
-..J
9
;
~7
fpm is maintained. Outputs are terminated
6
10
through a ·lQO.ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate.
...
(J1
------r--...
8
11
The other gates are tested in the
same man ner.
13
14
8
...
:i'
::J
t:
(I)
0.
F SUFFIX
CERAMIC PACKAGE
CASE 650
15
3
16
11
TEST VOLTAGE VALUES
lVoltsl
@Test
trJ
VIHmu
Vil min
VIHA min
VILA max
VEE
-5SoC
-0.830
-1.920
-1.510
-5.2
+25 o C
-0.720
-{).S80
-1.850
-1.255
-1 105
-1.475
-5.2
-1.820
-1.000
-1.400
-52
T emperatu rll
'"
0)
~
+1ZSoC
I Symbol
Characteristic
Power SupplV Dram Current
Input Current
J
I
logic "1" Outpt:lt Voltage
Logic "0" Output Voltage
logic "1" Threshold Voltage
Logic "0" Threshold Voltage
MC10517F Test limIts
Pin
Under
Tes.
-5SOC
Min
M..
'E
12
29
1m H
8
450
630
'3
1m l
8
13
VOH
6
VOL
VOHA
VOLA
Min
TV.
20
MaN
t4+2+
'4+3_
t4-3+
l20t~80%)
FeU ·'lime
120 to 80%)
M..
Unit
29
265
370
mAdc
0.5
0.5
/.IAdc
-0.930
-0.930
-0.720
-0.720
-0.825
-{).825
-{).580
-{).580
Vd,
Vd,
-1.920
-1.655
-1.850
-1.620
-1545
-1.920
-1.655
-1.850
-1.620
-1.820
-1.820
Vd,
Vd,
-1.545
-0.845
-0.950
-{).950
-1.635
-1.600
-1.525
-1.635
-1.600
-1.525
'2+
'3+
'2_
'3_
1.4
~
2.3
~
34
~
1.1
2.2
4.0
~
~
~
VILA max
13
8.13
8,13
8.13
8,13
8,13
Vd,
Vd,
-0.845
VIHA min
13
,!JAdc
,!JAdc
-0.830
-{).830
-1.100
-1.100
Vll min
"Ad<
-LOBO
-1.080
VIH max
8.13
Vd<
Vd,
Pul_ln
VEE
IVee l
Gnd
12
12
12
12
12
4,5
12
12
12
12
4,5
4.5
4,5
4,5
12
12
4,5
4,5
4.5
4.5
4,5
4,5
8.13
'2
12
4.5
4.5
PuJseOut
-3.2 V
+2.0V
8,13
+1.11 V
'4-2_
Rise Time
Mon
26
265
370
SWitching Times (l00<»hm load)
Propagation Delav
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+125 oC
+25"1:
13
j j
j
j j
MECL 10,000 series
DUAL 2-WIDE 3-INPUT
"OR-AND" GATE
MC10518
Po
= 100
The MC10518 is a basic logic building block
providing the OR·AND function, useful in data
control and digital multiplexing applications.
mW typ/pkg (No Load)
tpd = 2.3 ns
Output Rise
= 3.5 ns
= 2.5 ns
typ
and Fall Times:
(10% to 90%)
(20% to 80%)
POSITIVE LOGIC
(7)
3
(8)
4
NEGATIVE LOGIC
(9)
(7)
3
(8)
4
(9)
(10)
2 (6)
6
(13)
9
(14) 10
2 (6)
6
(10)
(11)
(11 )
7
(13)
9
(14) 10
(15) 11
(15) 11
15 (3)
(16) 12
15 (3)
(16) 12
(1)
13
(1)
13
(2)
14..
(2)
14
Numbers at end of terminals are pin numbers for L package {Case 6201Numbers in parenthesis dEmotes pin numbers for F package (Case 650).
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC
v c el = VCC2
+2.0 Vdc
VOIJt
""m""'
,----
Input
Coax
---l
I
50
I
I
PROPAGATION DELAY
Pulse Generator
Input Pulse
t+
::0
t-
= 2.0 ±.
0.2 ns
(20 to 80%)
sb-ohm termination to ground 10i
o
100
C8ted in .ach tcOp. channal input.
V out
~II inpl4t and output cables to the
-.cope are equal lengths of 50-ohm
coaKiat cable. Wire length should
h c; 1/4 inch from TPin to input
pin and TPoutto output pin. V out
: "2:1 attenuated. '
See G"neta1 Information section for packaging and maximum ratings,
3-265
s:
ELECTRICAL CHARACTERISTICS
...
...
n
o
Each lull temperature range MECL 10.000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equ il ibrium has been estab-
C11
lished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
00
3
8
4
::J
fpm is maintained. Outputs are·terminated .
through a 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
6
gate. The other gates are tested in the
same manner.
9
!:!.
2
::J
c:
CII
Q.
-
10
11
15
12
13
14
w
LSUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Volts)
~
Ol
@!Test
VIH max
VIL min
VIHAmin
VILA max
VEE
-1.920
-1.255
-1.510
+2SoC
-0.880
-0.780
-1.850
-1.105
-1.475
-5.2
-5.2
+125"c
-0.630
-1.820
-1.000
-1.400
-5.2
Temperatur.
-56°C
Ch,...ct.,istic
Power Supply Drain Current
Input Current
Symbol
IE
lin H
lin L
Pi"
Und.
TOS1
Min
Max
8
6
7
9
-
29
6
7
9
-55·C
MC10518L Test limits
+25o C
+ 125°C
Typ
Min
Max
Min
Max
-
, ,
0.5
450
450
630
-
0.5
VOH
2
-1.080 -0.880
-0.930
VOL
2
-1.920 -1.655
-1.850
Logic "1" Threshokt Voltage
VOHA
2
-1.100
-
-0.950
Logic "0" Threshold Voltage
VOLA
2
-
-1.635
-
16+2+
'6- 2-
2
1.1
1.1
3.5
3.5
1.3
1.3
4.1
4.1'
1.4
1.4
1.5
1.5
Logic "'" Output Voltage
Logic "0" Output VOltage
20
26
-
265
265
370
-0.780
-1.620
,
, ,
-
Unit
VIH max
VILmin
29
mAde
-
265
265
370
",Ade
6
7
9
-
-
.$JAde
-
6
7
9
I
Rise Time C20 to 80%1
'2+
Fall Time C20to 11*)
'2_
~
VILA max
VEE
CVCCI
Gnd
8
1.16
-
-
8
1.16
-
8
1.16
VIHA min
-
-0.825 -0.630
Vdc
3.9
-
-1.820 -1.545
Vdc
-
3.9
-
-
0.3
-
-0.845
-
Vdc
9
-
3
-1.600
-
-1.525
Vdc
-
9
-
3.4
3.4
1.2
1.2
3.9
3.9
n.
+1.11 V
2.3
2.3
2.5
4.0
1.2
4.0
2.5
4.0
1.2
4.0
Switching Times (1QO-ohm load)
Propagation Oelay
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
l
3
+
-
-
-
,,
,
+
8
1.16
8
1.16
8
1.16
8
1.16
Pulse In
3
Pulse Out
-3.2 V
+2.0 V
6
2
8
1.16
l
l l l
ELECTRICAL CHARACTERISTICS
3:
...n
...
Each full temperature range MECl 10,000
series circuit has been designed 'to meet .the
de specifications shown in the test table,
0
(JI
after mermet equilibrium has bea:n esteblished. The circuit is in a test. sOcket or
mounted on a printed. circuit board and
transverse air flow greater than 500 linear
00
8
8
9
fpm is maintained. Outputs are ~erminated
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tasted in the
same manner.
...
~
6
10
:;'
11
~
CD
a.
13
14
15
3
16
F SUFFIX
CERAMIC PACKAGE
CASE 650
w
~
TEST VOL rAGE VALUES
....,
O'l
IVolts•
@Test
Temperatur.
VIH max
VIL min
VIHAmin
VILA max
VEE
_1.510
-0.580
-1.105
-1.000
-1.475
-1.400
-5.2
-5.2
+125"c
-1.920
-1.850
-1.820
-1.255
+2SoC
-0.830
-0.720
-5SoC
Characteri.ic
Power Supply Drain Current
input Current
Symbol
'E
lin H
lin l
logic "'" Output Voltage
logic "0" Output Voltage
logic "'" Threshold Voltage
Logic "0" Threshold Voltage
Pin
Unci.
Tos'
12
10
11
'3
10
11
13
VOH
6
VOL
6
VOHA
6
6
VOLA
MC10518F Test Limits
+25o C
-55"c
Min
-
,
-
Min
M..
Unit
VIH max
Vil min
VIHA min
VILA max
VEE
1Veel
Gnd
20
26
29
mAde
-
jJAdc
'0
11
'3
12
4.5
370
265
265
370
-
0.3
-
}.lAd\:
-
4.5
265
-
12
-
-
12
4,5
Min
29
450
450
630
-
-
-
0.5
-
-LOBO -0.830
-1.920 -1.655
+
-0.930
-1.850
-1.100
-
-0.950
-
-1.635
-
+ 125°C
M..
M••
0.5
TVp
-
-
Vdc
-
7,13
-
-
-0.845
-
Vdc
13
-
7
-1.600
-
-1.525
Vdc
-
'3
26~
-
~.720
-1.620
+
-
-0.825 -0.~80
-1.820 -1.545
Switching Times 1100-0hm 10.U
Propagation Delav
Rise Time 420 to 8O%J
Fall Time
e20 to 8Q%)
1'0+6+
'10-6-
'6+
'6_
6
~
~- '--
-
1.4
1.4
1.5
- - ~~
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
2.3
2.3
3.4
3.4
2.5
4.0
~- 4.0
-
-
+
-
-
+
-
10
'1
'3
Vdc
7. '3
-
n.
~
+1.11 V
7
+
-
-
,
+
'2
12
'2-
+
+
4,5
4.5
4,S
4,5·
-
7
Pulse In
Pulse Out
'2
-3.2 V
+2.0V
10
6
12
4,5
~
~
~
~
MECL 10,000 series
4-WIDE 4-3-3-3 INPUT
"OR-AND" GATE
MC10519
POSITIVE LOGIC
The MC10519 is a 4-Wide 4-3-3-3 Input ORAN D gate with one input for two gates common to pin 10 (14). Input pulldown resistors
eliminate the need to tie unused inputs to an
external supply.
NEGATIVE LOGIC
(7)
3
(7)
(8)
4
(8)
4
(9)
5
(9)
5
(10) 6
(10) 6
(11) 7
(11)
(13) 9
(13) 9
(14)10
2(6) (14)10
(15)11
(15)11
(16)12
(16)12
(1) 13
(I)
7
2(6)
Po =.100 mW typ/pkg (No Load)
tpd ::: 2.3 ns typ
Output Rise and Fall Time:
= 3.5 ns typ «10% - 90%)
= 2.5 ns typ (20% - 80%)
13
(2) 14
(2)
14
(3) 15
(3)
15
Numbers at end of terminals are pin numbers for L package (Case 620).
Numbers in parenthesis denotes pin numbers for F package (Case 650),
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC
vee1
VCC2
+2.0 Vdc
n
coa •
I~
V out
' ">$''">
Cqax
r--------.,
I
I
I
I
I
Pulse Generator
50
PROPAGATION DELAY
I
I
Input Pulse
t+ = t- :: 2.0
±. 0.2
nt
I
I
I
(20'080%)
I
I
I
I
50-ohm termination to ground located in each SCO.p9 channel Input.
All input and output cables to the
SCOpe are equal lengths of SO-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TPout to output pin. V out
is 2: 1 attenuated.
L ___
l1~~"~
LfvdC
VEE
See General Information section for packaging and maximum ratings.
3-268
V out
3:
ELECTRICAL CHARACTERISTICS
...
...
o
Each full temperature range MECL 10,000
serincircuit has been designed to meet the
de specifications shown in the t8St table,
after thermal equilibrium has been established. The circuit is in a test socket or
o
C11
3
--+-__,
(13)9
(11) 7
(13)9
2 (7)
(14)10
(15) 11
( 16) 12
2(7)
(14)10
3(6)
3(6)
(15)11
( 16) 12 ----,~../"---.
----<-....------,.
(1) 13 - -.......\~r_-t------.J
(2)14
(3) 1 5 ----,c....___----
(1)13
(2)14
(3) 15 ----,--../----
Logic equation using pin numbers for L package
2= (4+ 5+6)-(7 +9+ 10)- (10+ 11 + 12)_(13+ 14+ 15)
3= (4+ 5+6).(7+9+ 10)- (10+ 11
+ 12).(13+ 14+ 15)
Logic equation using pin numbers for L package
2~ (4. 5.6) + (7 .9.10) + (10.11. 12) + (13.14.15)
3= (4e5_6) + (1e9.10) + (10.11.12) + (13.14.15)
Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotes pin numbers for F package (Case 6501.
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C
VCC1 = VCC2
+2.0 Vdc
V out
""ffJ'"
CoaJIC
r---- -----
-
CoaJIC
--,
I
50
I nput Pulse
t+
= t- = 2.0 ±
PROPAGATION DELAY
50
0.2 ns
(20 to 80%)
+1.11 V
I
Vin
I
I
I
50-ohm termination to ground 10' ~-~"\"""..,.....-f------..J
cated in each scope channel input.
All input and output cables to the
,cope are equal length, of 50-ohm
coaxia' cable, Wire length should
be < 114 inch from TPin to input
pin and TP out to output pin. V out
I, 2: 1 anen uated.
I
V out OR-AND
L ______________ .J
t+
t-
V out OR·AND·INVERT
S" Gen"a' I nformation section for packaging end maximum ratingt.
3-271
s:
ELECTRICAL CHARACTERISTICS
Each full temperatura range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
n
....
;~
o
6
U1
N
....
after thermar equilibrium has been estab-
lished.
The circuit is in 8 test socket or
7~
mounted on a printed circuit board and
transverse air flow greater than 500 I inesf
fpm is maintained. Outputs are terminated
through. l00-ohm resistor to -2.0 volts.
Te,t procedures are shown for only one
gate. The other gates are tested in the
same manner.
2
3
10
n
-
9
11
12~
o
:J
~,
:J
c:
(I)
c.
L SUFFIX
CERAMIC PACKAGE
CASE 620
13~
14
15
TEST VOL TAGE VALUES
(Volts)
@Test
Tamperature
w
N
......
Characteristic:
Power Supply Drain Current
Input Current
VILA maw.
Vee
-55"<:
-0.830
-1.920
-1.255
-52
+2SoC
-0.720
-1.850
-1.105
-1.510
-1.475
-5.2
+lZS o C
-0.580
-1.820
-1.000
-1.400
-52
-55°C
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+l25 o C
+25"<:
(Vee)
Min
Max
Min
TVp
Max
Min
Max
Unit
VIH max
VIL min
VIHA min
VILA max
Vee
Gnd
Ie
8
-
29
26
mAde
-
1,16
265
265
370
265
265
370
,uAdc
7
9
10
-
8
-
-
-
450
450
630
-
29
7
-
20
-
-
8
1,16
-
-
-
-
0.3
-
,uAdc
-
-
lin H
9
10
,
3
2
-1.080
-1.080
-
-
Logic "1"
Output Voltage
VOH
Logte "0"
Output Voltage
VOL
3
2
-1.920
-1.920
VOHA
3
2
-1.100
3
2
-
-1.635
-
-1.635
-
-
t4+3_
t4-3+
t4+2+
t4-2-
3
3
2
2
1.2
3.6
14
2.3
'3+
'2+
'3_
'2_
3
2
1.0
+
4.5
11
+
2.5
4.0
t
0.9
+
4.4
~
~
~
~
~
~
~
lin L
VOLA
7
0.5
-1.100
-
05
-0.830
-0.830
-1.655
-1.655
-0.930
-0.930
-1.850
-1.850
-
-0.950
-0.950
+
-
-0.720
-0.720
-1,620
-1.620
-
+
-0.825
-0.825
-1.820
-1.820
+
-
-
+
-0.580
-0.580
Vdc
Vdc
-1.545
-1.545
Rise Time
120 to 80%1
Fall Time
t20 to 80"')
-
-
7
9
10
10,13
4
-
4.10.13
-
Vdc
Vde
4,10,13
-
10.13
4
Vdc
Vdc
10,13
10,13
-
-
10.13
10.13
-
,
-
-0.845
-
-0.845
-
-1.600
-1.600
-
-1.525
-
-1.525
Vdc
Vdc
3.'
1.1
3.5
ns
Switching Times
(100-ohm loadl
Propagation Delay
I
Test
10
Logic "0"
Threshold Voltage
VIHA min
Symbol
9
Logic "1"
Threshold Voltage
VIL min
MC10521L Test limits
Pin
Under
N
VIH max
-
+1.11 V
3
2
+
+
10,13
-
j
j
-
-
+
8
+
1,16
•
8
1,16
1,16
8
8
1,16
1,16
8
8
1.16
1.16
-
-
8
8
1,16
1.16
Pulse In
Pulse Out
-3.2 V
+2.0V
4
3
3
2
8
1.16
2
j j
-
-
8
,
,
4
-
+
-
-
+
j
3
2
3
2
s:
ELECT,"GAL CHARACTERISTICS
Each lUll temperature range MECL lO,OOO
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
...o
c.n
...
(')
~~
10
N
mounted on a printed circu"it board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
~~~
through a 1OQ-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested In the
same manner.
14
~
7
6
15
16~
8
...
c::
a
:::l
:::l
FWH~
CERAMIC PACKAGE
CA~~O
~~
TEST VOLTAGE VALUES
(Volts)
@Test
Temperature
W
i\.)
-...J
W
I
Power Supply Drain Current
Input Current
Symbol
IE
linH
lin L
LogiC "1"
Output Voltage
VOH
Logic "0"
Output Voltage
Test
12
11
13
14
11
13
14
_56°C
Min
0.5
+
Min
Tv.
20
,
Ma.
26
265
265
370
VILA mall(
VEE
_56°C
~.83O
-1.920
-1.255
-5.2
+2SoC
+l25 o C
~.720
-1.850
-1.105
-1.510
-1475
~.580
-1.820
-1.000
-1.400
-5.2
0.5
Unit
29
265
265
370
mAde
+
~.93O
~.930
~.720
~.825
~.580
~.720
~.825
~.580
-1.655
-1.655
-1.850
-1.850
-1.620
-1.620
-1.820
-1.820
-0.845
-1.545
-1.920
-1.920
VOHA
Logic "0"
Threshold Voltage
VOLA
~.830
~.950
~.950
-1.635
-1.635
-1.600
-1.600
t8+1_
t8-1+
t8+6+
t8-6-
1.4
~
~
~
'7+
1.1
25
4.0
~
-1.545
--0845
Switching Times
(1()(k)hm loadl
23
3.4
~ ~
j.J.Adc
,
+
V,Hmax
-1.525
-1.525
V,L min
V,HA min
V,LA max
11
13
14
j.J.Adc
0.3
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Ma.
~.830
-1.100
-1.100
'6+
'7_
'6_
Min
-1.080
-1.080
VOL
Rise Time
120'.80%1
Fall Time
(20'.80%1
VIHA min
+ 125°C
+25"C
Ma.
·29
450
450
630
LogiC "1"
Threshold Voltage
Propagation Delay
VIL min
MCl0521F Test Limits
Pin
Unde,
Char.ctertstfc
VIH max
VEE
IVeel
Gnd
12
4.5
12
4.5
, ,
+
11
13
14
+
12
4.5
12
12
4.5
4.5
Vdc
Vdc
1,14
1.8.14
Vdc
Vde
1,8,14
1.14
12
12
4.5
4.5
Vdc
Vdc
1.14
1,14
12
12
4.5
4.5
Vde
Vdc
1,14
1,14
8
12
12
4.5
4.5
+1.11 V
Pul.'n
-3.2 V
+2.0V
1,14
8
12
4.5
j
j j
j j
8
Pul.Out
MECL 10,000 series
QUAD MTTL TO MECL
TRANSLATOR
MC10S24
Advance In:forIDation
The MC10524 is a quad translator fQ( interfiw:ing
data and control signals between a saturated togic
section and the MECL section of digital systems. The
MC10S24 has MTTL compatible inputs, and MECL
complementary open-emitter outputs that allow use as
an inverting!non·inverting translator or as a differen-
POSITIVE LOGIC
(9) 5
(10)
NEGATIVE LOGIC
4
(8)
6-T""""-"""L_~--2
(6)
(10)
3
(7)
(11)7
..---"'--_~--1
(5)
(11) 7
(14)10
(9) 5
4
(8)
6-..--,--~~--2
(6)
12(16) (14110
(7)
1
(5)
12(161
~-,-_~--15(3)
(15111
3
15 (3)
13 (1) (15)11
13 (1)
14 (2)
14 (2)
tial line driver. When the common strobe input"is at
the low logic level, it forces· all true outputs to a
MECL low logic state and all inverting outputs to a
.
MECL high logic state.
Power supply .requirements are ground, +5.0 Volts,
and -S.2 Volts. Propagation delay of the MC10S24 is
typically 3.S ns. The dc )evels are standard or
Schottky TTL in, MECL 10,OOOout .
An advantage of this device is that MTTL level
information can be transmitted differentially. via
balanced twisted pair lines, to the MECL equipment.
where the signal can be received by the MC10515 o~
MC1051S differential line receivers. The MC10524 i.
useful in computers, instrumentation, peripheral
controllers, test equipment, and digital
communications systems.
Numbers at end. of terminals denote pin numbers for
L package (Case 620).
Numbers in parenthesis denote pin numbers for
F package (Case 650),
Po = 380 mW typ/pkg (No Load)
tpd "" 3.5 n·, typ (+1.5 Vdc in to 50% out)
Output Rise, Fall Times;
2.5 ns typ (20% to 80%)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C
Vee
+6.0 Vdc
C0811C
""J
V out
V out
NAND
AND
''''t rF~
r---'---,
50-ohm termination to ground lo-
cated in each scope channel input.
Co.x
Coax
All ioput and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TPln 10 input
pin and TP out to output pin. V out
is 2: 1 attenuated.
<
50
Input
Pulse Generator
PROPAGATION OELAY
Input Pul . .
t+ = t- ~ 5.5 ±.D.S ns
(10 to 90%1
O.lI'F
Unused outputs
con "ected to a
10G0hm resistor
L._
--11,,,,
to ground.
+2.0 Vdc
L3+VdC
VeE
This il advance Information and 'Pacifications .r. subject to change without notlc •.
S . . Ganaral Information Metlon for PRk."lng.
3·274
V out AND
VoutNAND
s:
(')
ELECTRICAl.. CHARACTERISTICS
....
Each full ~ure range MECL 10,000
_i_ circuit h_ been designed to meet the
de opecificlrtions shown in th" t . table,
lifter thermal equilibrium ~ been estoblilhed. The circuit is in 8 tett socket or
mounted on 8 printed circuit board and
tranlVene air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through 0 1OQ.ohm r_istor to -2.0 volts.
Test procedures . •8 shown for only one
input, or for one set of input conditions.
Other inputs or. outputs are tested in the
same nwnner.
o
U'I
~3
-
12
10
~15
11
13
~14
LSUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGEICURRENT VALUES
V_
• T_
T.......MUr.
• oo"c
W
"-:I
....,
C11
-
..-
II ..........
,.....~ppty
Dr_mC,,"1Int
"
~iwe"""SutIPfy
...
..TM
•
- ...
-III"<:
IE'ClUtLT_Umili
+2ri°C
....
T. .
Or.inCun'enl
'CCl
'.
F~C""rem
'F
•
•
•
Inpul~VOIt ...
8V,n
Ce.mp 1.....1 Volt...
V,
H. . OU....IVoltail
VOH
LOIOII Ovtpul Voh...
VOL
H" TtnItIoId V~
VOHA
L... Ttw........ VDh...
VOLA
200
50
-12.8
-3.2
1
.1
...
I.'
-1.,*,
-UBI
-1.120
-1.120
-
...
.......
-1.856
-1.856
-1.000
-1.000
........
.."
'CCH
R_CutTent
...
I.'
-1.&
-1.5
....830
....830
·1.850
-1.850
'-0.780
.... 180
-1.820
-1.820
.......
.......
-1.836
-1.100
-1.6QD
-1.835
. . . T_'...... _ ,
Fill Time"" to 28U
-
+2Ii"c
+I2Ii"c
...
+1"'"
.
......
.2.CI!
+1.110
j
1.0
+
3.'
•.0
+1.10
+4.0
.....
VIH ......
Vll .....
1
1
'6+
2'
3.'
'&-
2.'
3.'
Ci) ........... *- _ciraHt. ............ ~ for IhiI circuit . . . . if'-i f,om
. .. ..........,
-1.545
-t.545
Vw
.2.40
+2.40
+2.40
.....
.....
Vee
.....
VIE
~.2
~.2
~.2
V WH
VF
V.
Vee
VEE
·211
+ID
+ID
-1 +ID
'II
'"
...
....
I•
I.
5,e,7,10,1t
S.8.1,10,1',"
mAd<
,.Adc
5,1,10,11
,IoIAdc
6
"'
I.
I.
I•
~7.1Q."
•
Vd,
Vd,
••1
1
I.
I•
I.
I.
I.
I•
Vd,
Vd,
'.1
I.
I.
Vd<
Vde
•
."
Vd,
Vd,
-1.525
-1.525
CIl
c..
...
',. I ...
.,. ...
.".1."
'II
·1'
TEST YOlTAGEJCURRENT APPLIED TO PI" LIlTED .LOW:
Vd,
Vd,
..g.825
.....
VF
mAd,
I.
Vd,
Vd,
....•,. .........
I
6
1
1
3
3
VWH
"4.0
·'.80
...OV•
110+6+
11o-&111+"
tlt_&t11+7_
111-7"
VIL ....
+1.10
mAd<
mAd,
.......
....... .......
-1.820
-1.820
....
VIH",'"
mAd,
-0.845
-0.845
.............. '1 ....
Pr. . . . . ian~
'+3.5 Vck 10 ~t(j)
~
8::J
...:i'
c:
4
6~
j j
I •.
.7.0'1*
•
3.0_
~
I.
+
+1.5 Vdc in to the!iD% point on the outpl,lt --'Ofm. The +3.5 Vdc is II--. .... '**'- 811 . . .rId 1UPPY ....... 1hHtId 2 ............
j
s:
ELECTRICAL CHARACTERISTICS
(")
Each ·full temperature range MECL 10,000
series circuit has been designed to meet the
~
o
de specifications shown in the test t&bte,
U'1
after thermal equilibrium has been established. The circuit is in a test socket or
N
1~~8
11~6
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 100-0hm resistor to -2.0 volts.
Test proc;edures .e shown for only one
input, or for one set of input conditions.
Other inputs or outputs are tested in the
~
n-O
::J
....
5'
FSUFFIX
16
14
c:
(1)
CERAMIC PACKAGE
CASE 650
~3
Q.
15
same ITlIIInner.
TEST VOLTAGE/CURRENT VALUES
VoIII
mA
ill",
Tempe,.fur,
W
~
......
en
II.
ett..xtltnsuc
S, .....
......
A"v"'w Curr*1n!
forward
Curr~n!
B'~akdown
'npu!
CI~mp
Vollage
VAH
-SS°c'"
+2So C
-200
+1.10
+"'.0
"'40
+1.80
+110
+4.0
"'40
+2.40
+12SOC
-180
+0.80
.4.0
-040
+2.40
....
-SSoC
M"
+25~C
Mo"
T,.
....
M,"
....
03
"
mAde
03
10
25
200
50
mAde
'A
I,
10
·128
-3.2
mAde
IC~H
ICCL
V,
"10
"
10
5.5
5.5
5.5
55
5.5
5.5
VO"
-15
LowOulpu! VollagP
-1080
-1.080
VOL
-1920
-1.920
Vollage
'.(OHA
-1.000
-1.000
Low Tn,,'sholc1 VOlldgl;'
VOLA
Hogh
Th't~hold
-0.880
-0.880
-1655
-1.655
-0.930
-0.930
-0.180
-0,180
·1850
·1850
-1620
-1.620
-0.825
-0825
-1820
-1820
-0.630
-0.630
-1.545
-1545
-0845
-0845
-0.950
-0.950
-1600
-1635
-1635
-1600
tlo-5tl1 ... 5 ...
111-5111+-7-
I '.-
111-7"t
A~T'm.''''%'o80~1
Fatl Timit (8)% to 2CWd
l5
1)0"'6'"
.'
~~
1
1
60
1
25
3.'
25
3.
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
Vd,
-1.525
-1.5:15
Sw.ldu", TimelSO-ll loadl
P'Op"'!IilI,on OI#I~V
1'35Vdc!oS""",G)
VIHmin
VIL m.1I
VAH
VA
-240
m.s..'r"~~~~ I~ \at fi,cl.lit: ~~~tion "'ey ' !'" '"","Circuit" specified from "".5 Vde In to the 50% polnl on Ihe output
VA
9.11,14.15
I~
10
10
9,11,14,15
"
"
10
10
Vee
-500
-500
-500
VEE
-5.2
-S.2
100
-.0
-10
-5.2
-'0
"
"
"
VEE
12
03
12
03
13
13
13
13
13
12
12
02
02
02
12
02
10 ..11
02
12
02
02
12
12
10
10
10
10
03
13
03
13
""
""
"
10
"
Vee
03
13
03
03
13
13
13
10.11
10
Vile
Vd,
V.
'.10,11,14.1
uAde
uAde
-1.5
H'9n Output Vollage
"""
mAde
02
V.
',2
-12
-12
-12
I
I~
+1.0
+1.0
+1.0
TEST VOL TAGEICUARENT APPLIED TO PINS LISTED aELOW:
.,25oC
-66
'E
BV,n
Inpu! Vollag*1
T",
Vil ""'.
MC10624F Tefl' Limits
Po.
Nl'9d! 'v" Pow~. SupplV
a'don CU''''n!
POS,hvl' Power Supply
ar~,n Curlen!
VtH ",in
I"TI'2T ,;"
I - I - I -
1 -1 -1
1
t4i.OVdc
Pulse In
Pulse Out
+7.0 Vdc
·3.2 Vdc
""10
10
10
5
13
02
"
_
_
I
l
G...
•
14.9.10.11,14.15
'0
11
10
"
+
j j
w ....,form. Tne"'3.5 Vde i,lhQwn hllfe bec*-t. ell logic endlUpply Itve!,.,.ttliftecl 2voeb positivi.
n~
MECL 10,000 series
QUAD MECL TO MTTL
TRANSLATOR
MC10525
Advance InforIDation
The MC10525 is a quad translator for interfacing
data and control signals between the MECL section
POSITIVE LOGIC
(6)
(7)
(10)
(11)
:=::.:t>--~ =::.:t>--=::.:t>--=::.:t>---
NEGATIVE LOGIC
(6)
4 (S)
(3)
:~4(S)
17)
5 (9)
(11)
12 (16)
(14)10~
12 (16)
(15) 11
14
15
14~ 13
(2)
13 (1)
L--l
(3)
15
11)
L - 115 )
(5)
Vaa
Power supplV requ irements are ground, +5.0 Volts
and -5.2 Volts. Propagation delay of the MC10525
is typically 4.5 ns. The MC10525 has fanout of 6
MTTL loads. The dclevels are MECl, 10,000 in and
Schottky TTL, or MTTL out. This device has an
input common mode noise rejection" of ±1.0 Volt.
An advantage of this device is that MECL level
information can be received, via balanced twisted pair
~~5(9)
110)
(14) 10
(15) 11
(2)
and saturated logic sections of digital systems. The
MC10525 incorporatasdifferential inputs and Schottky
TTL "totem p>le" outputs. Differential inputs allow for use as an inverting/non-inverting translator or
as 8 differential line receiver. The Ves reference voltage is available for use in single-ended input biasing.
The outputs of the MC10525 go to a low logic level
whenever the inputs are left floating.
lines, in the MTTL equipment. This isolates the MECL
logic from the noisy MTTL environment. This device
is useful in computers, instr·umentation. peripheral can·
trollen, tBst equipment ~nd digital communications
$Vstems.
Vaa
Numbers at end of terminals denote pin numbers for
L package (Case 620).
Numbers in parenthesis denOte pin numbers for
F package (Case 650),
I CASE I
VCC
620
Pin 9
I
I
650
I
Pin 13
VEE
I
Pin 8
Pin 12
Po = 380 mW tvp/pkg (No
I
I
~ood)
tp::t - 4.5 ns typ (50% to +1.6 Vdc out)
Output Rise, Fall Times;
2.5 ns typ (20% to 80%)
VCCmax::: +7.00 Vdc
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2SoC
vee
Coa~
"out
5""
vee
+50 Vde
J O 1 p.F
Input
r--
--,
280
4.0
I
Pulse Gen •• ato.
fL
Input Pulse
t+ '" t- '"
2 0 1.0.2 ns
(20 to 80%)
_1 69 \Ide
All DIodes
MM07000
or Equlv
o--+.....--1-.....~
50'Ohm termination to ground 10·
cated In each $COpe channel Input
One 'I'IDut from
e,1ch gate must be tied to
Vee
during test,ng
All input and output cabllils to the
scope are equal lengths 01 SO-ohm
coal'llal cable. Wire length should
be
1/4 inch from TPin to input
pin and TP out to output pin. V out
il 10: t attenuated
<
PROPAGATION DELAY
V out
This is advance information and specifications are subject to change without notice.
See Goimerat Information section for packaging.
3-271
ELECTRICAL CHARACTERISTICS
3:
n
Each full temperature range MECL 10,000
series circu it has been designed to meet the
de specifications shown in the test table,
~
after thermal equilibrium has been estab-
fished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Test procedures are
:~4
C
~~5
U'I
c.n
N
-
10~ 12
shown for onlv one input, or for one set of
input conditions. Other inputs or outputs
11
are tested in the same manner.
14~ 13
15
L---,
VBB
8
::J
....
L SUFFIX
CERAMIC PACKAGE
CASE 620
::J
c::
(1)
a.
TEST VOLTAGE VALUES
(Voltsl
t>T...
T""pet'etur.
.-
C~ad"''''ic
W
N
--.I
IX)
l Neptive
Power Supply
Dr.ln Current
l
'E
POSttive Power Supply
Dr.in Current
Pin
Undo<
Toot
....""
Min
'>sOC
M..
Min
Ty.
e
'in H (J)
'eBoll)
Short-Circuit Current
HilJh Output VOlt.
'OS
VOH CD
Low Output Volt. .
VOL
High Threshold Volt.
Min
M..
52
39
115
ICCL
Input L . . . . . Current
M••
40
ICCH
Input Current
......,
MC10U5L T_ Limita
1.0
4.
VOHA
'.0
100
40
2.5
2.5
2.5
0.5
2.5
-0.180
-1.920
-1.860
-1.820
Unit
mAde
VIHmu
mAde
2,6,10,14
0.5
2.5
J'Ade
,.Ade
/JAde
,.Ade
3,7,11,15
Vd,
2,6,10,14
Vde
Vd,
6,10.14
VOLA
VOLSI
0.5
0.5
0.5
0.5
0.5
05
VOLS2
0.5
0.5
05
Vd,
-1.120
Vde
Vd,
05
0.5
Vde
Common Mode
. Re;ectton Tests
l
VOH
-'.440
2.5
2.5
VOL
...itdI.... T .....
Pt-opegetion Oel-V
I~ to +1.5 Vdcl
R"
Time l+l.0Vdc to 2.0 Vdd
F•• Time(+1.0Vdc t~2.0Vdc)
d>
-1.320 -1.350
I......~~
2.5
2.5
'2+4t2--4+
....... ~
IndiwiduMty wt IKh input, epp6y VIH ...... to pin undlr ,-"
IndMdulllty,. ~ oulDUl. foMcMI,. ............. for Din 4.
-1.240
2.5
2.5
0.5
0.5
fa) 1~1y_1Kh Input, ~ VEe to pin u""~
•
-1,230
0.5
0.5
+
4."
+
6.0
+
3.3
3.3
Vee
.50
I
VEE
-5.2
-5.2
+5.0
1
+5.0
V'Lmin
VIHAmin VILAm.a VIHH VILH
VIHL VILL
Vu
3.7.11.15
Vee
9
.1
-5.2
!
VEE
Gnd
e
16
3,7,11,15
'6
16
2,6,10,14
3.7,11,15
2,6.8,10,14
.6
.6
2,6,10.14
2,6,10,14
3,7,11,15
3,7,8,1115
B
4,16
2,6,10,14
3,7,11,15
3,7,11,15
3,7,11,15
6.10,14
3,7,11,15
1~,~'~::4~'5
•
3.7,11.15
Pu ... Out
~
~
!
3,7,11,15
Output
Condition
••
16
16
16
16
16
9
•
!!!
-2.0mA
12,0 rnA
-2.0mA
12.0 rnA
12,0 rnA
16
12,OmA
16
16
-2.0mA
-2.0mA
16
.6
12.0mA
12.0mA
CL IpFI
25
6
6
2
I
16
3,7,11,15
Vd,
Pul.'n
'.0
I
Vu
F,om
Pin
3,7,11,15
2,6,10,14
Low Threshold Volt.
Tv••
1 1v,LLl
VHAmin VILA",.. VIHH VILH VIHL
-1.510 100·11 -0.920 -1.8301-2.920
-1.256
-1.476 100·281: -0.860 - •. 1201-2.860
-1.106
-1.000
-1.400 100.4'" -0.820 -1.580 -2.820
TEST VOLTAGE APPLIED TO PINS LISTED 8ELOW:
1",,""ln. Input
Protct ion T lISts
Reference Vat ....
-0.630
mA
Vd,
2.5
0.5
VILmin
-0.880
'2sOC
+1260(:
mAdc
""
2
3
VIHm..
-56OC
16
1
3:
ELECTRICAL CHARACTERISTICS
...
o
Each full temperature range MECL 10,000
~~8
series circuit has been designed to meet the
de specifications shown in the test table.
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
10~
11~
o
U1
I\,)
F SUFFIX
U1
CERAMIC PACKAGE
CASE 650
0-
9
fpm is maintained. Test procedures are
14~ 16
shown for only one input. or for one set of
15
o
::J
~.
::J
:~1
input conditions. Other inputs or outputs
are tested in the same manner.
C
CD
Q.
~5
Vss
TEST VOL rAGE VALUES
(VollS)
@Test
Temper,ture
-..I
CO
I
I
Ch....I... mu:
Symbol
T..,
'E
12
Neg,t,1o'e Powe-r Supply
Dr"n Cun.nl
POJ'llIIt Pow.r SUPP'y
Dr"nC"rrenl
leeH
13
leCL
13
6
'tlPul Cun.nl
',nH (J)
Inpul leo. . . . Currenl
IC80<2)
-SS"c
M ••
'os
HI~ OutPUt Voll.
VO H Q)
lOW Output Volu.Je
VOL
"
M,"
T"
M ..
M,"
M ..
VOHA
25
40
05
VIH rn ••
VILm,n
VIHAmlll VILAm,. VIHH V'LH
05
Voll
-1240
25
60
110-9+
IndlVldUlilly tlllSt uch Input, apply VIH milt to pin under ttst
I%)
Individually tnt lt8Ch IIlPUt. applv VeE 10 pin unci., lesl
0'1
Indlyi~ltv tetteach output. folloM", '''Imple shown for Pin 8.
3.1,11,12,15
+ +
33
33
Ic~;::-;n
12
2.6.10,12,14
•
261014
13
12
761014
3.7.11.15
13
12
10mA
3)1115
13
13
13
12
12
12.0mA
10 mA
12
12.0mA
13
2.3.6,7.10,
11.12.14.15
12.0mA
13
12
120mA
13
13
13
13
12
12
12
12
12.0 rnA
12.0mA
13
12
261014
37.111!l
3.111.15
2.10.14
Vde
-1120
',8
3.11115
05
05
Puhlt In
"' Don"te •••
H
a"
Po ~ ;45 mW tYP/pkg (No Load)
tpd :::: 2.5 ns typ
Numbers at end of terminals ar. pin number. for L package (Ca•• 620).
Numbers In parenmnia denotes pin number. for F package (Ca .. 650).
CIRCUIT SCHEMATIC
This is advance information and specifications are subject to change VIo!ithout notice.
S.e General Information section for packaging.
3·280
The MC10530 is a clocked dual D type latch.
Each latch may be clocked separately by holding
the common clock in the low state, and using
the clock enable inputs for the clocking function.
If the common clock is to be used to clock the
latch, the clock enable (CEI inputs must be in
the low state. In this mode, the enable inputs
perform the function of controlling the common
clock (el.
Any change at the D input will be reflected
at the output while the clock is low. The out·
puts are latched on the positive transition of the
clock. While the clock is in the high state, a
change in the information present at the data
inputs will not affect the output information.
Input pulldown resistors eliminate the need
to tie unused inputs to VEE.
Output rise and fall times have been opti·
mized to provide relaxation of system layout
and design criteria.
The set and reset inputs do not override the
clock and D inputs. They are effective only
when either C or CE or both are high.
m~ f..,t: (·,i.~;'I··f
iCI
"f_! t:ft."ci-~''''t:.,;
S,
ELECTRICA[· CHARACTERISTICS
Each full temperature range MECL 10,000
series tircuit has been designed to meet the
dc specifications shown in the test table,
after t.hermal equilibrium has been estab·
lished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
input, or for one set of input conditions.
Other inputs or Ol.,ltputs are tested in the
same man ner.
5~--~-------,
0'
7
CE'
6
MPoj
2
~
....
o
-
3
R'4j
R~ ,:~~-+----------,
U'I
W
o
nO
LSUFFIX
CERAMIC PACKAGE
CASE 620
::J
r+
::J
C
(I)
~
14
CE211~
"1
02'0
Q2r--'5
TEST VOLTAGE VALUES
1
S2'2
(Voltsl
@Test
Temperature
-550 e
+2So C
+125 O e
w
..:.,
Pin
Und.
CX)
Char.ct .. irtic
Power Supply Drain Current
Input Current
Logic "0"
Output Voltage
Logic·"1"
Threshold Voltage
Logic "0"
Threshold Voltage
S'!Vitching T~mes (50
(See Figure 11
Propagation Delav
Fall Time (20% to 80%1
VILAm.x
VEE
-0.880
-'.920
-1.850
-'.255
-1.'05
-1.000
-'.5'0
-1.475
-5.2
-5.2
-5.2
-0.780
-0.630
-1.820
+125o C
Min
MI'
Min
Typ
Mo.
Min
MI'
Unit
IE
8
6
9
4
7
4·
-
39
375
450
485
485
-
28
-
35
220
265
285
285
-
39
220
265
285
285
0.5
-
0.3
-
~Ade
-
4
2
-1.0BO
-0.880
-0.930
-
-0.780
-0.825
-0.630
Vdc
7
VOL
2
-1.920
-1.655
-1.850
-
-1.620
-1.820
-'.545
Vdc
-
VOHA
2
-1.'00
-0.950
-
-
-0.845
-
Vdc
-
VOLA
2
-
-'.635
-
-
-'.600
-
-'.525
Vdc
-
t7+2+
t5+2+
t4+2_
'&-2-
2
-
-
1.0
2.7
2.7
2.7
3.5
_.
ns
-
t
-
-
l
6
-
-
-
-
0.5
VIHmax
VILmin
VIHAmin
VILAmax
VEE
mAde
9
-
/JAde
6
9
4,9
7,9
-
-
-
8
-
-
-
7
-
-
-
7
-
-
+
9
+1.11 V
'2+
'2_
Setup Time
tsetup
Hold Time
thold
I
-All other inputs are tested in the same manner
CD See test circuit for test procedures.
2
2
_.
-
-
+
1.1
-
1.1
2.7
2.7
2.5
1.5
-
4.0
3.5
3.5
-
-
-
-
-1.400
TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
Load)
Rise Time (20% to 80%1
VIHAmin
T..
'inL
VOH
n
-550 e
VILmin
Symbol
linH
Logic "1"
Output Voltage
MC10530L Test Limits
+2Soe
VIHmax
6
-
-
-
1.16
-
8
1.16
7
8
1,16
Pulse In
Pul. Out
-3.2 V
+2.0 V
7
5
4
6
7
2
8
1,16
6,7
CD
(j).
-
•
8
7
ns
+
1,16
1,16
6,7
-
-
'.16
1.16
8
-
ns
8
(Vee l
Gnd
8
I II
2
2
-
8
1.16
8
1.16
ELECTRICAL CHARACTERISTICS
3:
519
01 11
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
6
through a 10Q.ohm resistor to -2.0 volts.
R18
Test procedures are shown for only one
C 13
input, or for one set of input conditions.
R21
W
0
8
....
::l
5'
"1
0214
Q2r-- 3
eVolts)
@Te...
Temptrlltur.
VIHmn
VILmin
VIHAmin
VILAmlx
VEE
-SSoC
+2SoC
+12SoC
-0.880
-0.7BO
-1.920
-1.850
-1.255
-1.105
-1.510
-1.475
-5.2
-0.630
-1.820
-1.000
-1.400
MCl0530F Test Limit.
+2SoC
-55°C
(1)
TEST VOLTAGE VALUES
~
5216
w
c:
.eo
Q2~2
L.r-J
CE2 '5
Pin
U1
F SUFFIX
CERAMIC PACKAGE
CASE 650
Other inputs or outputs are tested in the
same manner.
,:.,
~
CEllO
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
CO
....
0
0
Each lull temperature range MECL 10,000
series circuit has been designed to meet the
-5.2
-5.2
TEST VOLTAGE APPl1ED TO PINS LISTED BELOW,
+l25°C
Und..
Test
Min
Ma.
Min
Typ
Ma.
Min
Mo.
Unit
VIHmlx
VILmin
VIHAmin
VILAmlx
VEE
12
10
13
8
11
-
39
-
28
35
220
265
285
285
-
-
-
13
10
13
8,13
11,13
-
-
39
220
265
285
285
mAde
375
450
485
485
-
-
-
12
12
linL
8'
0.5
-
0.5
-
0.3
-
/JAde
-
4
Logic "1"
Output Voltage
VOH
6
-1.0BO
-0.880
-0.930
-
-0.780
-0.825
-0.630
Vde
11
Logic "0"
Output Voltage
VOL
6
-1.920
-1.655
-1.850
-
-1.620
-1.820
-1.545
Vde
-
-0.845
-
-1.600
-
-1.525
2.7
2.7
2.7
3.5
-
-
ns
-
-
4.0
3.5
3.5
j
10
10
n.
ns
(j)
(j)
"-l
Chllr.ct.istic
Po~r
Supply Drain Current
Input Current
Symbol
IE
'inH
Logic "1"
Thntshold Voltage
VOHA
6
-
-0.950
_.
Logic "0"
Threshold Voltage
VOLA
6
-
-1.635
-
-
t11+6+
6
-
-
1.0
Switc;:hing Times {SO n Load)
(See Figure 1)
Propagation Oel8Y
Fen Time (20% to 80%)
Setup Tin.
t.tup
Hold Time
thold
I
-All other inputs.re tilted in the ..me ".nner
(i) s.._ circu~ IOf , . . " ' _ " -
6
6
-
-
~
1.1
1.1
2.5
1.5
2.7
2.7
+
-
-
-
-
-
-
Gnd
4,5
4,5
-
-
~
~
-
12
12
4,5
-
-
4,5
-
11
-
-
12
4,5
Vde
-
-
11
-
12
4,5
Vde
-
-
-
11
12
4,5
Pul.ln
Pul.Out
-3.2 V
+2.0Y
11
9
8
10
11
11
6
12
4,5
•
+1.11 V
'9+6+
'11+6'10-6_
'6+
'6-
Rise Time (20% to 80")
-1.100
/JAde
'''eel
-
-
-
-
.10,11
10,11
I II
6
6
12
12
4,5
4,5
MC10530 (continued)
FIGURE 1 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l250 C
veC1 = VeC2
+2.0 Vdc
=
V out
""ll'' '
r---
---,
I
Input Pulse
t+ = t- ::: 2.0
nl
± 0.2
S
"S
Clock Input lot----~'--o
(20 to 80%)
a
O--I---1D
50-ohm termination to ground located in each scope channel input.
A
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TP in to input
<
pin and TP out to output pin. V out
is 2; 1 attenuated.
+1.11 Vdc
V'H
+'.11 V
CIOCk'~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
+0.31 V
.~---.... - - - - - +1.1 1 V
C
50%
----",
'-----+0.31 V
thold
-----+1.11 V
R'npu,~
S Input
50%
r-+
+ _____JI
1 . 11V .
'--_ _
-
- - - - - - - - +1.11 V
'--_ _ _ _ _ _ _ +0.31 V
D
'-----+0.31 v
+0.31 V
'2+
tsetup
a
~
------:::r--~ to+o:--
I
NOTE:
t setup is the minimum time before the positive
transition of the clock pulse (e) that information must
be present at the data input (0).
thold is the minimum time after the pOSitive tran·
sition of the clock pulse (e) that information must
remain unchanged at the data input (0).
3-283
MECL 10,000 series
DUAL TYPE D MASTER-SLAVr
FLIP-FLOP
MC10531
The MC10531 is a dual master-slave type 0
flip-flop. Asynchronous inputs Set (51 and Reset
(RI override the Clock (CCI and Clock Enabie
(CEI inputs. Each flip·flop may be clocked separately by holding the common clock in the low
state and using the enable inputs for the clocking
function. If the common clock is to be used to
clock the fli poflop, the Clock Eiia1iie inputs mllst
be in the low state. In this case, the enable
inputs perform the function of controlling the
common clock.
The output states of the flip·flop change on
the positive transition of the clock. A change
in the information present at the data (01 input
will not affect the output information at any
other time due to master slave construction ..
Input pulldown resistors eliminate the need
to tie unused inputs to VEE. Output rise and fall
times have been optimized to provide relaxation
of system design and layout criteria.
R-5 TRUTH TABLE
R
S
L
L
On+l
Qn
H
L
H
H
L
L
H
H
N.D.
N.D.;::: Not Defined
CLOCKED TRUTH TABLE
¢
C
0
°n+l
L
4>
Qn
H
L
L
H
H
H
= Don't Care
C = CE + Cc·
A clock H is a clock transition
from a low to a high state.
CASE
VCCI
VCC2
VEE
620
Pin 1
Pin 16
Pin 8
650
Pin 5
Pin 4
Pin 12
Po
POSITIVE LOGIC
51
191
5
01 (111
7
CEI 1101
..
6~
Rl
181
Cc 1131
R2
Al
~2
161
~3
7
52
•
~
01
~3
171
~
02 ~14121
::;;r----;.
A2116112
Q2 ~15131
4
Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650),
3-284
161
4
11113
02114110
See General 1nformation section for packaging_
~2
9-<
CE2115111
~
Ql
6~
02 ~14121
Q2 ~15131
02 114110
b
r--
181 4
Cc 1131
111 13
52 116112
01 1111
51
9--<
CE2 115111
5
171
1
4
191
CEI 1101
01
mW tvpipkg
NEGATIVE LOGIC
,
Ql
= 235
f Tog ", 160 MHz typ
S1
ELECTRICAL CHARACTERISITCS
series circuit has been designed to meet the
de specifications shown in the test table,
=:J
(9) 5
01 (II)
eEl (10)
Each full temperature range MECL 10,000
7
6
3 (7)
after thermal equilibr.um has been established. The circuit is in a test socket or
Rt (8)
Cc (13)
4-+--9
~
152
'__
Pin
Symbol
Tes.
'E
8
l,nH
4
5
6
7
9
-
565
565
375
420
450
IInL
4,5,6,7,9'
0.5
0.5
-
LogiC "1"
Output Voltage
VOH
2
21
LogiC "0"
VOL
3
31
-1.080 -0.880
-1.080 -0.880
-1.920 -1.655
-1.920 -1.655
LogiC "1"
Threshold Voltage
VOHA
2
21
-1.100
-1.100
Logic "0"
Threshold Voltage
VOLA
3
31
-
Power Supply Dratn Current
Input Current
Input Leakage Current
w
~
C11
Output VOltage
SWitching Times(l00-ohm load)
Clock Input
Propagation Delay
Min
-
Q2
MC10531L Test Limits
+2S o C
-55°C
Under
Characteristic
-
2 (6)
Ma'
62
-
-
-
-1.635
-1.635
Min
-
-
--
-1.600
-1.600
-1.105
-1.475
-5.2
-1.820
-1.000
-1.400
-5.2
62
mAde
-
330
330
220
245
265
#JAde
4
-
-
~
5
6
7
9
-
}JAde
/JAde
0.825 -0.630
-0.825 -0.630
-1.820 -1.545
-1.820 -1.545
-0.845
-0.845
-
-
-1.525
-1.525
-
-
Vdc
Vdc
5
7
Vdc
Vdc
5
7
Vdc
Vdc
-
Vdc
-
Vdl.:
+1.11 Vdc
4.6
1.5
3.0
1.4
16+2+
16+2-
2
2
2
2
Rise Time (20 to 80%'
'2+
2
Fall Time (20 to 80%)
'2-
2
1.0
1.0
15+2+
112+15+
t5+3_
112+14-
2
15
3
14
1.1
4.5
~
~
+
+
14+2-
1.1
4.5
12
2.8
14+3+
113+14+
2
15
3
14
Setup Time
tsetup
7
-
Hold Time
thold
7
Toggle Frequency (Max)
fTog
2
19+2-
19+2+
~
J
~
4.5
~
1.5
~
5.0
ns
+
-
1.1
J
1.2
4.9
ns
2.5
1.1
2.5
J
1.1
1.2
2.8
4.3
7
7
4.9
4.9
1.1
Reset Input
Propagation Delay
'13+15-
+
+
4.3
+
~
1.2
+
-
• -•
2.5
1.5
1.5
-0.5
•
115
125
160
125
-
-
Individually test each input;.apply V, L min to pin under test.
··Pin 3 is tied to pm 7 for these tests.
- .
, rI-
tOutput level to be measured after a clock pulse has been applied to the CE mput (pin 6~
L
VtH max
VIL min
+
4.9
~-
+
ns
+
ns
ns
MHz
-+0.31 Vck
-
-
--
-
-
-
-
-
-
-
..
-
-
-
Set Input
Propagat Ion Delay
-5.2
~.
:::J
c:
M ..
03
0.3
-0.930
0
VIH max
+l25 oC
Typ
05
05
6
6f
T lsetup
I
I
0.5
0.5
VOHA
VOL
LogiC "1"
Threshold Voltage
M..
6
6f
7
7t
VOH
Output Voltag!!
W
Q2}- 3
+2SoC
12
Inpul Leakage Current
@Test
Temperature
MC10531F Test Limits
'E
13
8,9·
F SUFFIX
Vdc:t.l%
I
S2 16----- _.
uTne~~r
l,nH
s:C")
...
...
n
-~
r
TEST VOLTAGE VALUES
5;1..-2
CE2 15
D214--
I Svmbol I
I
I
Power Supply Dram Current
~
~--~
""~"'--"'"
""'/,:.,=
Other inputs are tested in the same manner.
Pm
~
GEl
meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is In a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
input, or for one set of input conditions.
Charactenstlc
9
Dl
+
10,11
6
12
4,5
10,11
6
6
12
12
',5
10
',5
MC10531 (continued)
FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT
V out
Coax
t+ '" t--~1.0ns
(20% '080%)
50
ot----~--------~CE
Clock Input
Qf-------'
O---------lc
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable.
Wire length should
100
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.
FIGURE 2 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
vee1 '" VCC2 '"
+2.0 Vdc
Input Pulse
t+
= t- ""
2.0 ns ± 0.2 ns
(20 to 80%)
PW
PRF
= ~2.0
ns
= 1.0 MHz
Clock Input (Ot------;~-
L
L
L
Qn
L
H
L
L
Po
tpd
'=
310 mW typ
= 4.0 ns typ
H
L H H
¢ - Don t Care
C==CC+
Ce
POSITIVE LOGIC
DO
GO
(7)
3
2
161
QO
6
1101 Ql
191
01 1111
7
CE
4
181
Cc
(1113
CE
116112
02 1131 9
11 1151 Q2
Gl (14110
15 131
03
Q3
12114
Numbers at end of terminals are pin numbers for L package (Case 6201Numbers
in.parenthe'i~
denotes pin numbers for F package (Case 6501.
Ca .. VCC1 VCC2 VEE
620
Pin 1 Pin 16 Pin 8
650
Pin 5
Pin 4 Pin 12
See General I "formation section for packaging.
3·288
'1i...,\/OM."" 'IOlt.tI.'~,* ti.t: UiM....~·i..,orqlii
~
-
-
-1.525
}ldc
1
Vdc
j .)
-
-
-
j
4
4
1.16
•
8
1.16
8
8
1.16
1.16
8
U6
+
-
-
,
5
.8
1.16
3
--
I
8
1.16
-3.2 V
+2.0 V
8
1.16
-
3
-
-
--
1.16
8
-
3
3
4
3·
-
Gnd
8
-
-
ns
-
VEE
3
3
3
3,4
4
4
-
-
-
-
-
~
5.4
5.4
3.1
:J
!:t.
TEST VOL TAGE APPLIED TO
PINS LISTED BELOW:
+12SoC
..
-1.820
-0.630
ilIH~i~
---
-
-
4
4
13
-
5
--3
-
-
-
-
13
PulSBln PulsaOut
3
4
5
3
3
2
2
2
2
2
3
2
3
2
'I
n
.....
~.
CERAMIC PACKAGE
CASE 620
.
VIHmax VILmin
-0.880
·1.920
-0.780
-1.850
MCl0533L Test Limits
VOH
VOLA
11Q2
0.3
logic "1" Output Voltage
logic "0" Threshold Voltage
,
tEST VOLTAGE VALUES
IVoltsl
~'15Q3
3
VOHA
.-
'
I
..
02
~110
Pin
Under
Test
f
....
13
lin l
logiC "1" Threshold Voltage
.. _., .. _ ..
I
0314
Symbol
~
CE4
fpm is main.tained. Outputs are terminated
through •. 100-ohm resistor to -2.0 volts.
Test procedures are shown for only one
input, or for one set of input conditions.
Other in"puts are tested in the same manner.
Characteristic
"'
..
O~:
6
.
:~;:,;;.~~~,.~~':f:~:::::::.~~~~~::::::~:'~~2~;?~: !::?2:~:~~~~=~!:~!:?:~~~~~~!?~r.F~~;~~~~~~~~~~~
•
j
j j
1j
00
ELECTRICAL CHARACTERISITCS
6 00
Each full temperature range MECL 10,000
series circuit has been cfltsigned to meet the
01
I ...
11
Cc
::~~'502
Input Current
w
Logl(~
8
Logic "0" Output Voltage
"1" Output Voltage
~
Logic "1" Threshold Voltage
Lo.gic "O!' Th.reshold Voltage
Switching Tinw.
l1oo..hmLOI.CII
Propagation Delay
Rise Time (20% to 80%.
f'aHTimo 120% .0'_1
-SSoC
Tnt
Min
Ie
12
-
lin H
7
8
9
lin L
VOH
VOL
VOHA
VOLA
13+2+
•7
-
-1.920
6
-1.100 .
6
6t
6tt
6tt
6
6
6
6
6
6t
6tt
6tt
6
6
6
7
7
14-2+
'5-2+
t.tup
'hold
·'2+
6
'2-
6
VIHlnlx
-55"C
+25"1:
-0.880
-0.780
+l25o C
-0.630
-
-
j
-
-
'-
-
-
-0.880
-0.880
. -1.655
-
-
-
-1.635
!
-
-
-1.820
-1.000
-1.400
VEE
Gnd
12
4,5
-
-
12
4,5
12
+
4,5
12
12
4,5
.';5
12
4,fi.
-
,,
9
12
4,5
B
Ij
Min
MIX
Unit
VIH.,...
-
60
75
-
-'
mAde
-
-
245
265
350
350
-
-
J,lAdc
7
8
9
1
--
-
0.5
-
-
-
J,iAdc
-
7
-
-
cO.930
-0.930
-
-0.780
-0.780
-1.620
-0.825
-0.825
Vdc
Vdc
7,8
1,7
1
1,7,9
-
-
-
•
-0.950
-
-
-
j
-
-
-
-
-1.600
-
1.0
~
2.5
1.5
1.1
1.1
-
-.
-
--
-
,,,
-
!
5.4
5.4
3.1
-1.820
-0.845
-0.630
-0.630
-1.545
-
-
J
-
~
-
-1.525
-
J
-
-
-
-
-
3.5
-
3.5
-
-
-
tOulpUt_1 to 1I......and.f. . . .lock pul. . . . bIo8n """lied 10 tlw oIacIi l"Pllt'!,"''''' . .IJ:VIH.....
-5.2
-
MI.
-1.850
IiCo
-5.2
1
TVp
-
VEE
-5.2
VlLmin VIHAmin VIHAmII.
Min
-
...5'
::J
Vilmin V.HAmin VIHAmII.
-1.920
-1.510
-1.255
-1.475
-1.105
"'.850
TEST VOL TAGE APPL1EO TO
PINS L.STEO BELOW:
+l2SoC
+25"C
M..
-
,•
-1.080
-1.080
6
6
6
6
6
Ii
Temperatur.
MC10633F Tnt Limi..
Symbol
8
(Voltsl
@Tnt
Q3
Pin
Under
3:
n
....
o
~
·W
F SUFFIX
CERAMIC PACKAGE
CASE 650
TE$T VOLTAGE VALUES
~303
2
Power Supply Drain Current
10 Q1
CE
,.
Chlr.cte,i5tic
~
llo
de specifications shown in the test table,
after thermal equilibriu"m has been estab·
lished. The circuit is in a test socket or
mounted on a printed circuit board and
-
•
•
Vdc
7
-
11
Vdc
7,8
Vdc'
!
7,8
7
-
7
7
7,8
8
8
-
-
7"
-
-
1,
7
-
-
7
1
9
-
-
-
-
1
-
1
J2
8
.
7
8
-
9
7
7
-
7
-
7
r.11i~~e="'~~~,_t~"·_~'''''~"""",~.,,~~ ,.,~.,l
6
6
6
6
6
8
8
+
4,5
! ,!
Pu . . ln PuI.Out -3.2 V
V
8
.
-
.-
7
7
I +1.11
-
-
-
ns
-
-
8
1
7·
-
12
1
+2.0 V
4,6
I
~ ~,~"i"~ 2~:,;":'1
;
'-::"'7-~"
;::~
"':--:-:""~
.- MC10533 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C
'-.,\
VCC1 = VCC2
+2.0 Vdc
Coax
""$''''
50
Input
V out
Coax
PROPAGATION DELAY
r----- ----.,
Pul,sa Generator
50
I
+1.11 V
Input Pulse
2.0±O.2ns
tt"'t-=-
. (20 to 80%)
V out from 0 Input
L----n--.J
5O-ohm termination to ground 10
each scope channel Input
cated
!"
V out from
G Input
~ 0.1 IJF
C
All Input and output cables to the
scope are equal lengths of 1 CO-ohm
coaxial cable. Wire length should
be < 1/4 ,inch from TP in to input
pin and TP out to output pin.
VEE
= ~3.2
Vdc
Unused outputs
connected to 8
100-ohm resistor
to ground.
o
a
t setup is minimum time before the negative transitiorl of the clock
pulse
ee)
that information must be present at the data input (OJ.
thold is the minimu~ time after the positive transition of the clock
pulse ee) that information must remain unchanged at the data input (0).
The latch will store the data on the falling edge of the
clock. The outputs are gated when the output enable is
low. All four latches may be clocked at one time with the
common clock, or each half may be clocked separately
with its clock. This devil:!! is useful as a temporary storage
element in high speed central processors, accumulators,
register files, digital communication systems, instrumenta·
tion and test equipment:
APPLICATION INFORMATION
. The Me 10533 device consists of four bistable latch
citcuits with D type inputs and gated a outputs. When
the clock is high the outputs will follow the D inputs.
3-291
MECL 10,000 series
DUAL J.K MASTER-SLAVE
FLIP-FLOP
MC10535
Advance
POSITIVE LOGIC
In~orIDatlon
re.tlI
NEGATIVE LOGIC
51 (9t 5 - - - - - ,
51
(9) 5 - - - - - ,
Jl (11.) 7
2 (6)
Jl (11) 7
2
Kl (10) 6
3 (7)
Kl (10) 6
3 (7)
(6)
AI (B) 4 -1---'
Rl (B) 4----1'----'
e (13) 9
52 (16)12-+--~
C(13) 9
52 (16) 12 -1------,
J2(14)10
15 (3)
J2 (14)10
K2 (15)11
'4 (2)
K2 (15) 11
Rl (1)13-----"
15 (3)
14(2)~'_·
____--,________________________________~.
AI (1) 1 3 - - - - - - '
R-S TRUTH TABLE
Num~ers
-,
The MC10535 is a dual master-slave de coup'
led J-K flip-flop. Asynchronous set (5) and
(R) are provided. The set and reset inputsover- j
ride the clock.
A common clock is provided with sep....
J-K inputs. When the clock is static, the j.j(
inputs do not effect the output.
.
The output states of the flip-flop change
the positive transition of the clock.
.
Input pulldown resistors eliminate the need
to tie .unused inputs to VEE. Output rise
fall. times have been optimized to provide relax.
tion of system desi9F1 and layout criteria_
CLOCK J-K TRUnt
TABLE'
at eods of terminals denote pin numbers for
L package (C•• 620),
L'
Numbers in parenthesis denote pin numbers for
F package (ease 650),
H
CASE
V CCI
V CC2
VEE
620
650
Pin 1
Pin 5
Pin 16
Pin 8
Pin 12
Pin 4
o
N.D.
(1.=
Not.Qellned
'Output .1at.. change on"";
t;1I8 trentilion of cJack for j
K ,nput condition p_~l.
Po ~ 280 mW tvp/pkg (No Loedl
'Tog· 1.0 MH, tVa
FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT
vee, "Vee2
=
+2.0 Vdc
V out
Coax
Clock Input
All input and output cables to the
seops are equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 Inch from TPin to Input
pin and TP out to output pin. V out
is 2: 1 attenuated.
(Ot---~-----(~-;
<
Input Pul ..
t+::: t-= 1.0n.
Duty Cycle""' 50%
SO.ohm termination to ground 10·
cated in each scope channel"input.
*O,'jlF
Unu.d outputs connected to •
50-ohm resistor to ground.
VEE = -3.2 Vdc
r
...__________________________________________________________________~--------------------------..-.:'#,~: i
;.·;rl~;
1
-::,i
SH Generel Information Nctlon for peckaging.
Thla la advance Information end speclflcatlona ere subject to chano- without notice.
3·292
'
..
"-.~,..,..;
..
• ...; ••_ _ .....
;~~P'81AA..."C\f~j:RISTICS
~.th(f~1I temp8'.fJ1ii'"r.ntli'MECL '111,odo .rfli.'cit-'
",,1t"tI8i; been' deslgnOd tbi'ineet tl18 dC".peciflCatlonS
J, ,
shown in 'the u.f'tablil,efter ther";'l equilibrium he,
been established. The circuit i. in e test socket or
mounted on a printed circuit board and transverse air
flow lII'elter ihen 500 Iineerfpm i. maintained. Outputs ere terminated through • 1QO-ohm resistor to
-2.0 volts. Test procedures Ire shown for only one
input, or for one sat of in put conditions. Other inputs
or outputs are tested in the same manner.
i(1
-
a
""y"
~211
15.2"
POMr Supply ~r.in CU~"t
Input Cur,.".
Input LNk.., Current
Co)
~
=
Symbol
'E
\ lin H
'Iin L
·~.·T"
Outpu.VaI • •
VOH
Lotic:·O"
Outpu.VoI_
VOL
Logic
_"1"
_ Vol_
8
6.7.9.10.11
4.5.12.13
4.5.6.7.9.
10.11.12.13
2
2C1>
3
j@
2
2@
3.
3@
VOHA.
Co)
. Logic "0"
Thnihokl Volt....
VOLA
-550 C
Min
Temperatur.
-5Soc
+250 C
+12&oC
-
+26"c
Ma.
75
450
665
-
0.5
0.5
-1.080 -0.880
-1.080 -0.880
·1.920 -1.655
-1.920
-1.655
-UOO'
. -UOO
"
--
--
-1.635
-1.635
Min
'
-
Mo.
·54
68
0.5
0.5
·0.530
-0.930
-1.850
:1.850
---
-0.950
-0.950
-.
-
-
"?':~:.~~,.~r-,:,:, t :.,~p"'" '~~':;~;':"';".,
•• N" •• : ••
Min
-
265
390
-
-
-0.780
-0.780
-1.620
-1.620
- ..
~
0.3
0.3
-0.825
-0.825
-1.820
·~1.820
-0.845
-0.845
_1.800'-1.800
--
75
265
390
-
-
·0.630
-0.630
-1.645
-1.645
'-
-1.525
-1.525
Unit
,'mAde
J.lAdc
J.lAde
J.lAdc
J.lAde
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Ri. Ti .... (20'0 BOlli
... fall Time (20'0 BOlli
Set 'np'it
PropegIition Del-V
t2+·tJ+
t2_·t3"-
.-.
'5+3-
o.-v
1.4+3+
'13+15•.. tuP
'hold
ime
Hold
To.a!' Frequ.ency
fT~.
-
----
2
3
15
14
7'
'4+2'13+14+
Setup Tim.
-
2
15
3
14
t5+2+
'12+15+
t12-+14-
R_t Input
Pr. .tiO!'
-
2
2
2.3
2.3
t9+2+
t9+2-
-
7
2
-
-
'--
-
-
--
--
4.5
1-1
.3.0
3.0
2.0
2.0
1.0
3.0
5.0
1.0
1.0
U
t
.~
1.0
3.0
~
~
1.5
2.5
125
~
~
5.0
~
All Input and output cables to the
scope .re equal lengths of 50-ohm
coaxial cable. Wire length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.
All unused outputs are tied to 100
ohm resistor to ground.
VEE' -3.2 Vdc
NOTE:
t ..tup is the minimum time before the positive
tr8n,itlon of the clock pulse (el that information must
be pr.sent at the input. J or K.
thold i'the minimum time after the positive tran·
Iition of the clock pulse (e) that information must
remain unchanged .t the Inputt J or K.
3-295
J1p1
;"i
MEeL 10,000 series
UNIVERSAL HEXADECIMAL
COUNTER
MC10536
The MC10536 is a high speed synchronoul coune.
that can count up, count down, pre.t, or stop count.
frequencies exceeding 100 MHz. This binar{ COU ......
is useful in high speed central processors and per. . . . .
controllers. minicomputers, high speed digital comtnunieations equipment Wid instrumentation. Theft.,. ..
INPUTS
01
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
I/l
I/l
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
I/l
I/l
I/l
I/l
L
L
L
L
H
H
H
H
L
H
L
H
H
L
L
H
L
L
L
H
L
L
L
H
H
H
L
H
DO
01
D2
D3
in
L
H
H
H
L
L
H
H
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
L
L
L
L
L
H
L
H
H
H
L
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
H
H
L
H
H
H
H
L
L
L
L
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
I/l
.,
ao
S2
L
L
L
L
either computers or instrumentation.
I/l
Th~ro
H
H
02 03
.
~---.._
••
' " -of
" 'the
.,,
.... ' " Lines
" '"' S1 ...
the operation
mode
counter.
Carry
H
H
H
H
SI
pile
basic counter for most ..plications, and the .,nchrOftous count f""ture makes the MC10536 suil8bie for
OUTPUTS
Carry Clock
u.
1
bility of this device allows the designer to
SEQUENTIAL TRUTH TABLE'
Out
determine one of four operations; preset {progrll'nl
increment (count up). decrement (count downl. Of
hold (stop count I. Note that in the pr_t _
clock pulse is necessary to load the counter. _
dIej
information presant on the data inputs (DO, Dl. D2#
and D31 will be entered into the counter .. Caory
goes low on the terminal count, or when
coun~
the
is being preset.
au
.
When an output is not needed, it can be left ~
to conserve system pow.. (The open emitter outpUt
will require no power if left open). The cau~ter ~
st-ate only on the positive going edge afl the clock.
Any other input may change at any time except durilll
the positive transition of the clock.
This device is not designed for use with _ _
clocks. Control. is via 51 and 52..
A prosealer can be constructed using the MC10531
in conjunction with the MC10631 which w~1 oper_
at over 200 MHz input frequency. A 500 MHz pr-.:'"
is possible using an MC1690 500 MHz D Flip-FlOP. 1ft
MC1670 300 MHz D Flip-Flop. and the MC10536.
tfJ "" Don't care.
I
• Truth tabla shows logic Itates assuming inputs vary in sequence
shown from top to bottom.
•• A clock H is defined as a clock input transition from a low to a
high logic level.
FUNCTION SELECT TABLE
114110- Cin
QO '--14(21
(1)13- C
(16112- 00
( 1 5 ) l t - 01
(10) 6 - 02
(91 5 - 03
(13) 9 - St
(11) 7 - S2
Ql -15(31
Q2 - 2 (61
Q3 - 3
SI
S2
L
L "
L
H
H
L.
H
H
Operating Mode
Preset (Program)
I ncrement (Count Up)
Decrement (Co .... nt Down)
Hold (StOP Count)
m
C out - 4 18)
--'fPo
f count
Numbers at ends of terminals denote pin numbers for L package
(Case 620).
Numbers in parenthesis denote pin numbers for F package
(Co.e 6501.
See General I nformatlon section for packagIOg.
3·296
= 625 mW typ/pkg (No Load)
=
150 MHz typ
ICose I VCCI I VCC2 I
1620
1650
I
I
Pin 1
Pin 5
VEE
J
I Pin 16 I Pin 8 J
I Pin 4 I Pin 12 I
'fL'I'm'iexeTBiA'fiJ:M1ft~TICi'
.....,..
",~"""",.,, " \ , . '
W,"'" ',.",
:t'iiifi:fuliliiTiji8retU,.'ri,.geMECLfO 000
..
_lei c/rwlt h.. been designed to ~ the
Q:,tp8Clflcatlonl shown In the toot table,
after thermal equilibrium h.. been _I>lisheil· The circuit is in a toot lOCket or
mounted on a printed circu it board and
transversa air flow groater than' 500 linear
fpm is maintained. Output""e terminated
through a 1QO.ohm resistor to -2.0 yolts.
Toot procedures are shown for Only one
inp~t. or. for one set of input conditions.
Othor inputs or output. are tested in tho
same manner.
0Wect8r...
lin H
.......,..
C
-0.830
-1.850
-1.820
-1.000
-5.2
VILmin
VtHAmtn
ViLA .....
VEE
-
165
-
-
-
-
8
1,16
/oIAdc
5,6,11,12
1
9,10
13
8
1,16
-
220
265
2••
290
0,3
-
l
"Ad,
~
~
...
IndividUllly appfy V I L min to Pin unctlr test,
",.•
CD
12
1,9
Vd,
Vd,
-
-0.845
-
Vd<
-
1,'
-1.600
-
-1.525
Vd,
-
1,'
+1.11 V
-to.31V
2.'
1.9
I,.
1,9
(b Measure output after clock pulse
..
8
1. IS
1,16
J.18
"'''In
_Out
-3.2 V
+2.0 V
13
,.
1.9
1,.9
12,13
12,13
•
7,13
10,13
10.13
.4
•
!,.
9,1l
.
"
,,
f
1.16
1,16
8
t
9
Vll
~
8
8
12
'0
'0
7,9"
1.1
l
8
13
13
-1.0
'25
-
12
12
5,2
6.2
1:l.6
12.6
1.6
1,6
-1.0
125
3.3
-
-1.645
1.'
1.'
2.'
-
-
-
-1.0
-2.5
-2.5
-1.6
3.'
0.9
150
'50
2,0
.....
VIH .....
3,1
115
115
IVcc·
Unit
-0.630
8.9'
6,.
<'D
Q.
m,Adc
-0.825
10.5
c:
...
-1.820
4,'
-1.400
TEST VOLTAGE APPLIED TO "NILISTED BELOW
~.780
..•
::J
~.
::J
IVofbl
VEE
-1.620
10.6
~
TEstVOLTAOE VAWES
I ~ILA me. I
·7.S
t ••
t14_
3,3
3,3
1.0
1,0
5.0
50
Q
CJ1
8
VIH.""ft
3,5
3,'
1,'
feountup
'cOuntdown
',4+
1.0
1,0
2,5
2.5
1.6
1.6
' LSUFFIX
Vll",,,,
+laoC
'n
...a
CERAMIC PACKAGE
CA5E 620
VIH",. .
TMftper"lIre
Switchi . . Til"Ml
1100-0ttm lotd)
Pra,...tton o.t.y
-
i
.
Q3,-- 3
MC10138L T... limha .
+26Q C
Ty.
0.5
-0.930
VOLA
Q1'
,_"T,·-·,:'
_t"It~~""':.~.~
9 - 51
Pi.
PoWer"Suppty Drain Current
Input Current
':-"""1S"'",,!,".'I'7¥1
12,13
12,.13
'.13
7,13
10,13
10,13
MH,
MH,
3,3
115
115
1,2
3,1
l
~
l
VIH appears at clock Input (pm 13)
13
1
(3)
Before test set 11111
a outputs to III logic high.
,.
,.•
1,16
ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in 8 test socket or
14
2
00
Cin
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 1()().ohm resistor to -2.0 volts.
Test procedures .8 shown for onlv one
16
DO
15
01
10
02
9 - 03
01
3
02
6
03 - 7
1 1 - 52
Caut
Pi.
Power
....""1.
Drein Cur,.n,
Inpul CUrtwnl
-eeoc
Mi.
--
T..........ure
~
CO
.a"c
T.,
120
+12fiOc
00;.
150
21S
2""
2~
-1.080
-<1.660
-0.930
-0.780
VOL
-1.120
-1.655
-1,850
-1.620
-1.820
Output VOltllll
Lotic "1"
ThNlhold VoI_
21Z
VOHA
2C1
-1.100
.....'0'.
VOLA
21Z
~Vol"
Swrritcfti,.Ti"..
~.950
-1.600
-1.256
-1~5'O
....2
-1.105
-1.475
-1.000
-1.400
.... 2
... .2
~.8110
-1.920
-1.850
-1.820
.,;aoc
-0.830
TEST VOL TAG! APPLIED TO ,'INS LIlTED _LOll
VIH ......
VILllllin
VIMA..-
v..
ViLA ....
12
12
9.10.15.16
11
13,14
~
-0.630
.Adc
Vdc
-1.545
Vdc
11.13
Vdc
11.13
Vdc
11.13
-1.526
...;5'
::J
v..
VIH ......
285
-0.845
-1.636
n0
VILA_
vlLlllin
-0180
.Adc
2""
26.
O.S
W
mAdc
260
VOH
All
0
U1
0)
VIH ....
.2&"c
.... ....
165
21S
260
"0
O.S
....
0.3
-0.825
Outpu. Vol~
..... '0'.
W
Mi.
36.
1
......,..
......
MC1D538F T. . Lirni1l
165
13,14
I,n L
....
(")
CERAMIC PACKAGE
CASE 650
IV... I
.r..
r--8
same manner.
I_I~
I "
I 12
I Ito H 19.10;~5.16
...
F SUFFIX
TEIT VOLTAGE YALUES
1 3 - 51
input, or for ana set of input conditions.
Other inputs or outputs are tested in the
3:
~
C
1
1
(j)
16
+1.11 V
11,13
.0.31 V
tl~mLOIdJ
CI)
Co
...
lVeel
'.5
4.5
~
12
12
'.'
'.5
12
4.5
12
'..
18
12
'.5
_0..
-3.2 V
+Z.V
1.
'.5
III
........
c:
~tOf'IOrtI.y
Clock Input
c;;;;TnTo~
art
'1+2+
t1+2"+8+
11+8-
"4+
'''+9+
2
2
I
I
ICI)
I
1.0
1.0
3.3
3.3
4.S
4.S
16
2.5
2.5
7.0
7.0
10.5
I."
5.0
1.6
5.0
6.9
6.9
11
11
11
11
t(}.S
I
1.
1.
Up Tim.
o.u Inputs
Stfect Inputl
c;;;Tn
Input
118+1+
118-1+
113+1+
111+1+
·114-H
11+14+
3.S
3.S
7."
7.'
3.7
11.13
11.13
1.16
13
13
1,13
1.11
1,1:4
1,14
11.13
11.13
1,11
'1.18 .
13
13
1.13
1,11
1.14
1,14
11
11
-1.0
1.18
Ho6d TifM
Oat. Inputs
Sttect InPf,ttl
~Inpul
Countj,. F,.quency
-.-
RiliTima
1 - .. - 1
PolIn....
11+18+
1.1+1&11+13+
11+11t1+1 .....
114+1+
fcountup
'countdown
...
'2+
ta'2-
-1.0
-1.0
-2.5
-2.5
-1'.6
3.1
125
126
1.1
~
MH,
MH.
150
150
2.0
~
1
13
3.3
11
l
J
~i~;,.,,~~~,t~ ....~,~~: "II~!"'l!!"oho!:!'OC"~~I&.£V1H~"~~tl~j31
.,,:.
11
11
11
I•
'
.
J
•.__ ,
I
2
I
"-":(;""
G,~-""'Q"""'''
\;'
MC10536 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS .. 25"c
NOTE:
.tup i, the minimum time before the pOliti.... e
tranlition of the clock pulse Ie) that informetlon "('Ult
be Aretant at the input 0 or S
.
thold' i. ttte minimum time after the pOliti.... e tran·
.ition of the clock pul .. ICI thet information mUlt
remain unchenged et the input 0 or S.
VCC1 '" VC;:C2 '" .2.0 Vdc
Vout
Co••
50
In~ut
Pul..
t+ :: t- "" 2.0 ns ± 0.2 ns
(20 tb 80%)
Clock Input @--.....- " - o
\
\
TP out
Ctock
.0.31 V
Q
Output
VEE = -3.2 Vdc
r-----__-- .'.1, V
c
+0.31 V
SO·ohm termination to ground located In each scope channel input.
o DrS
All Input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
114 Inch from TPln to input
pin and TP out to output pin. V out
is 2: 1 anem.Jated.
<
Unused outputs are connected to
8 100-ohm resistor to ground.
SET UP AND HOLD TIMES
L
'e) il the minimum time to WIIlt eft.,. the
counter hu ~n enebl~ to eJodt it.
Ib) I. the minimum 'tlme before the
counter ..... tt.-, dl.bled t ....t It rn.y
be elodled.
Clock
Ie} i. the m6nlmum time b4rfore t ....
count.r I, enabled tNt' a IOlock pul.
may be applied with no eftect on the
IUIte of the countllr.
, Id} I, the minimum time to welt eft_
the counter .. d_bled that • elodl
pul. rNY be applied with "0 effect In
the 1UIt. Of the count_.
(b) .,.d lei rn.sy be neeatlve "um",
3-299
MC10536 (continued)
COUNT FREQUENCY TEST CIRCUIT
Vee,· VCC2" +2.0 Vdc
V out
Co.x
Clock Input
@)--.....----<>--t
Input Pull.
t+ .. t- .. 1.0
Duty Cve'. -
n.
5o"
~
O.'''F
l
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cab! •. Wire· length shou~d
be
1/4 inch from TPjn to input
<
60-ohm termlnetlon to ground 10co," .n Neh ...... chon ...' 'nput.
pin and TP out to output pin. V out
is 2:1 attenuated.
...,... 0.1 "F
~
Unused outputs are connected to
• 100-ohm r.,istor to ground.
UNIVERSAL BINARY UP/DOWN COUNTER
r-------------------------------------~--~----------------------~
51 •
"--+---,
52 1 <>-1>-+-L__
12 DO
14QO
1101
16Q1
602
3-300
202
503
303
i
j'tr MC10536 (continued)
":-' f
APPLICATIONS INFORMATION
~.
ii
MC1670. Usa of the MCI0631 in place of the MCI670 permit.
To provide more than four bits of counting capability several
~10638 counter. may be cascadad. The Carry In input overrides
200 MHz operation.
'.
clock when the counter is either In the increment mode or the
t mode of operation. This input aUows several devices to
c-=eded in a fuliV synchronous multistage counter as illustrated
Figure 1. The carry is advanced between stages IS shown with
external gating. The CiiTyTri ofthe first device may be left open.
".,..; . . system clock is common to all devices.
~~: j I The various operational modes of the counter make it useful
wide variety of applications, If used with MECL III davices.
-I
with input toggle frequencies in excess of 300 MHz are
. ~
.
Figure 2 shows such a prescaler using the Me 10536 and
~' ~
The MCI0536 may .Iso be used I I a programmable counter.
The configuration of Figure 3 requires no additional gatas, although
maximum frequency is limited to about 50 MHz. The divider
modulus is equal to the program input plus one 1M - N + II. therefore. the counter will divide by • modulus varying from 1 to 16.
A second progr.-nmabl. configuration is also illustrated in
Figure 4. A pulse swallowing technique is used to speed the counter
operation up to 110 .MHz typically. The divider modulus for this
figure is equal to the progrem input 1M z NI. The minimum
modulus is 2 because of the pulse swallowing technique•• nd the
modulus may vary 'from 2 to 1S. This programmable confitJJration
requires In additional glte. such os %MCI0609 Ind I flip-flop such
os%MCI053I.
. :. '.t=.
1
$!
FIGURE 1 - 12 BIT SYNCHRONOUS COUNTER
MSB
LSB
~r:!:m----~~------------------------~--------------------------~
Note: 51 and 52 are set either for Increment or decrement operation.
FIGURE 2 - 300 MHz PRESCALER
Logic High
MC101i311
SI
S2
o
aJ--t-------1~C
________
~~~
'-_________ t nput Frequency
32
MC1670
3-301
MC10536 (continued)
FIGURE 3 - &8 MHz PROGRAMMABLE COUNTER
Progr.m I"put
fin - - -.....----1 C
Cln
<:out 1---....- - - f out
S2
Sl
1 f out "" ::-_ _..,f:;.ln:...-._-:
Program Input
2 f
3
+1
m•x ~ 50 MHz Typ.
Divide Ratio is from 1 to , 6.
FIGURE 4 - 100 MHz PROGRAMMABLE COUNTER
Program Input
I I I I
DO
01
02
03
C
-
S2
MC10536
; - - - ~1
00
02
03
-
L
1--,
~
0
0
1
%MC10509
%MC10531
C
fin
f out = ::----"':--Program Input
2
1m.x ~ 1'0 MHz Typ.
3
Divide Ratio i. from 2 to 15.
3-302
-
°l
f out
MEeL 10,000 series
UNIVERSAL DECADE
COUNTER
MC10S37
The MC10537 is a high speed synchronous counter
thatca" count up. count down, preset, or stop count at
frequencies exceeding 100 MHz. This decade counter
is useful in high speed central processors and peripheral
,
L
INPUTS
I
OUTPUTS
Carry
,--
, -,
controllers, minicomputers, high speed digital communications equipment and instrumentation. The flexibility of this device allows the designer to use one
SEOUENTIAL TRUTH TABLE"
51
52
L
L
L
L
L
H
H
H
L
L
L
H
L
H
H
H
H
L
H
H
H
L
L
L
DO 01
H
¢
''""
''""
'"
IIthad. Tho circuit i. in 0 test socket or
mounted on ". printed circuit boIird and
transverse air flow groator than 500 linear
fpm II maintained. Outputs ore terminated
1hrough • l()().ohm raslltorto -·2.0 volts.
Tast procadur..... shown for only one
Power Supply
Input Current
~.in
S,mbol
Cur,ent
"
lin H
Logic "'"
tTl
13
D3
.51
11
52
93
02~6
nO
031--7
Output Vol ....
Logic "0"
OutPUt "Vol ....
Logic "'."
Threlhold Votlell
........0 ..
::J
TEST VOLTAGE-VALUES
!!.
IV~I
::J
fOT. .
TMft.,.,et""e
Cout.r- 8
......
T..
I
-5.2
~5.2
12
165
9,10,15,16
11
376
4SO
13,1.
1
415
406
Typ
120
I
I
Mi.
Unit
Min
150
165
mAd,
220
26.
22Q
265
>45
290
245
290
~r
lin L
All
VOH
2(2)
-1.080
I
-0.880
I -0.930
-0.180
I
-0.825
I
-0.630
VOL
2(2)
-1.920
I
-1.855
,
-1.850
-1.620
I
-1.820
VOHA
2(2)
-1.100
I
I
-0.9SO
VOLA
2~
0.5
0.5
0.3
-1.636
-1.600
VIL min
I
VIHA min
I VILA INa I
Wec·
VEE
Gnd
12
'.5
r
9,10,15,18
11
13,14
1
(i)
4f
4.5
Vdc
",13
12
4.5
I
Vdc
",,3
12
4.5
I
Vdc
11,13
Vdc
I
-t.545 I
-0.845 I
-1.525
I
12
12
,&lAde
I
I
VII'I rna.
11,13
I
I'
~
TEST' VOLTAGE APPLIED TO PINS LJSTED BELOW
+1moc
I M..
+250 C
M;n
Mall
(I)
-5.2
+2SoC
+12S oc
MC10637F T... Limm
_56°C
Min
c:
VEE
_550C
P;n
~
Dl
D2
Thrlllhoid Voll...
Switching Times
(l00-0hm LOIdI
16
16
4.5
18
12
4.5
Pu_Out
-3.2 V
+2.0 V
16
2
2
12
4.5
11
11
8
+1.11V
1.a.31V
Pu".ln
Propepnon Del• .,
Clock InPUI
11+2+
11+2-
11+8+
1'+fIr
1'4_fIr
1'4+8+
ca;;;Tn To c;;;;ow
2
2
1.0
1.0
8
2.5
8
2.5
1.6
1.6
:~
3.3
3.3
7.0
7.0
5.0
5.0
4.5
4.5
10.5
10.5
6.9
6.9
14
14
11
11
SIt UpTime
o.,.lnpUlt
3.5
3.5
116+1+
116-1+
11,13
11,13
7.5
Select Inputs
tI3+'+
111+1+
75
~lnPUI
114-1+
11+14+
3.7
-1.0
Oet.lnputt
11+16+
11+16-
-1.0
-10
Inpull
11+13+
11+11+
-2.5
-2.5
Cetrv In Inpul
11+14_
114+1+
-1.6
3.1
1,16
!
1.16
1,13
I,ll
11
11
13
1,14
1,'4
11,13
11,13
1,16
1,16
Hold Time
~ect
Counting Frequency
RiM Time
(2OK to 80%)
Fell Ti....
(2OK 10 al'%)
'counlUP
fcountdown
18+
'2+
IS12_
CD IndividueliV .PPlv Vil min to pin unelllr test,
•
8
125
125
1.1
~
~ Me_ure output after clock pulse VIL ..r
~.
(!)
~
......
CERAMIC PACKAGE
CASE 650
01~3
ma""IH'.
aw-._
~
16
..
-.",,~-,.....~'.~~'~ ~~~'~~~ .. '~~-"":""-~-.'~~-:-~
F SUFFIX
DO
10
; ...
OO~2
C
1Ii
input, or for one"sat of input conditions.
Other inputs or outputs are tested in the
~.
co;;
14
,
1,13
I,ll
11
11
MH,
MH,
150
150
3.3
11
13
13
13
1,14
1,14
1
11
T l
V1H appears at clock
i~ut Ipin ,)
a> Before test counter must be stt to a zero count condition lall outputs low)
MC10537 (continued)
COUNT FREQUENCY TEST CIRCUIT
Coax
60
Clock Input@--....- - - o - - j
5O-oh." terminatIon to ground located In each ICOp. channel input.
Input PutN.
t+-t--1.0n.
All Input and output cables to the
~
Duty Cycle - 51H1.
O.II' F
scope are equal lengths of 5()..ohm
coaxial cabl •. WI,. length shOuld
be
114 Inch from TPln to Input
pin "and TP out to output pin. V out
Is 2: 1 attenuated.
I
<
Unused outputs are connected to
+1.11 V
a 100-ohm resistor to ground.
Vee =- -3.2 Vdc
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
,
~'
(a) Is the minimum time to walt after the counter
has been enabled to c:lock It.
(b) I. the minimum tim. before the counter has been
disabled that it may be clocked.
(e) is the minimum time before the counter is enabled that 8 clock pulse may be applied with no effect on the .tate of the cou owr.
(d) I, the minimum time to walt after the counter
I_ disabled that B clock pul_ may be applied with no
effect In the state of the counter.
(b) .,d (c) may be negative numbers.
Vln
VCC1""VCC2-+2.0Vdc
V out
NOTE:
"setup is the minimum time before. the positive
transition of the clock pulse (C) that Information
must be present at the Input 0 or S.
Coax
Coax
tra:~f1~n I~ft~~e r::~~,;up':I'::'7~) a::.:~ ;~:0~;:~~1:~
50
must remain unchanged at the Input 0 or s.
;.
~.
,
;
~;
Clock
~
+1.11V
50%
tc + Q+
tc + Q-
+0.31 V
Clock Input@--....--o
Input PUIM
\
t+ - t- a 2.0 ± 0.2 ns TP ln
(20 to 80%)
\TP
r-----~-- +1.11 V
C
+0.31 V
VEE = -3.2 Vdc
50-ohm termination to ground located in each seope
channel Input.
.
OarS
All input and output cables to the scope are eq~al
lengths of 50-ohm coax lal cable. Wire length shou-Id
be <114 Inch from TP in to Input pin and TP out to
output pin. V out Is 2:1 attenuated.
Unused outputs are connected to a 100-ohm resistor
to ground.
3-306
out
MC10537
(continued)
UNIVERSAL DECADE UP/DOWN COUNTER
12 DO
1400
1101
1501
602
202
STATE DIAGRAMS
COUNT UP
COUNT DOWN
(.;,.
3·307
503
3Q3
4~
MECL 10,000 series
FOUR-BIT UNIVERSAL
SHIFT REGISTER
MC10541
The MC10541 is a four-bit universal sbift
register which performs shift left. or shift riam.
serial/parallel in. and serial/parallel out ope~
tions with nO external gating. InputsS1 and
control the four, possible operations of •
register without external gatill9 of the cloc:lt.
The flip·flops shift information on the positiYe
edge of the clock. The four operations ~re st~'
shift. shift left, shift right, and parallel entry f
data. The other six inputs are all data type i,
puts; four for parallel entry data, and one ,f9r
shifting in from the left (DL) and one fOr shift·
ing in from the right (DR). All four out~
are capable of driving 100 ohm lines.
'
When the register is used for serial output
only, the unused emitter follower outputs cljn
be left open.
52
11113
OL
181 4
C
116112
00
14121
01
15131
02
'2
161
03
3
171
DO
115111
01
1131 9
02
1101 6
03
114110
51
1111 7
52
DR
191 5 - - - - ' - '
TRUTH TAILE
rT,=E~
OllTPIJTS
OPERATING MODE 00"+1 Qln+l Q2n+1 Q3n +1
P.,."" Entry
00
02
D.
Shift Right-
Q1".
a',
Shih Left"
OL
00,
a',
a',
02,
StopS""'
00,
a',
02,
a',
PR
:a:
425 mW typ/pkg (No Load)
fShift
• Outputs ..... In .fter pul .. IIPpe.,. M "c" Input with Input eoncUtlon •
150 MHz typ
.. 1tI_n. Wul.... PotJt ..... trantltion of .c:loclil Input).
ea••
VEE
620
650
Numbers at end of terminals .!!Ire pin numbers for L package (Case 620).
Numbers In parenthesis denotes pin numbers for F package (Case 650),
LOGIC DIAGRAM
D.
02
52
OR~------H----L~
03
02
See General Information section for packaging.
3-308
01
00
nrtmfl~t'CM••""~.
£.c"h-lulfi~u"i"'iiiit~lcL';O.OO(f .
i""'iHcireart .... beenrttlllGl'*! to me.t "' ......~
de _ilicadon •.¥.!9.\Nn in tit. test tabl.;
after thermal equilibrium has been astab- .
lish.ct . .Tht -~irct..lit i$ in a test socket "Qr
.. t3----..
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 100·ohm resistor to -2.0 volts.
Test procedures are shown only for selected inputs and outputs. Other inputs
and outputs are tested in a similar manner.
.I"
C
12
DO
11
01
9
02
6
03
•. r.~,,m~:~'.~...
."
'.'~, u..1J'J8'rt."?\!'
.•
:,", i~';~l""..
'1 0 " ' . •.•." .
'.
;.,.
' . . ..
.
Power SupplV Drain Current
I
Input Current
,
I
LOgie "1'~ Output Voltage
g LLogic "a.. Output Voltage
W
W I
I
lilT...
Temperature
_55°C
+25o C
I
MCl0541L Test Limits
+2S o C
-SS"C
CD
VIHmax
Propagation Delav
Fall Time (20% to 80%)
Shift Frequency
V,L
-1.820
-1.000
-5.2
-5.2
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW,
+ 125"c
TVp
Ma.
Min
M ••
Unit
VIHm••
110
-
100
mAde:
-
-
-
220
220
245
265
220
220
245
265
~Adc
4
375
375
415
450
-
110·
-
-
5
-
5
6
7
4
-
-
~
VILmin VIHAmi
-
-
-
-
-
0)
-
0.5
-
-
0.3
-
",Adc
4.5.6.7.9
10,11.13
12
-
-1.080
-0.880
-0.930
-
,0.780
-0.825
-0.630
Vdc
6
VOL
3
3
-1.920
-1.655
-1.850
-1.620
-1.820
-1.545
Vdc
-
-
-0.950
-
-
-0.845
-
6
-
~-
-
-
-
-1.600
T
-
-
-1.100
-
-
-
V8)A
I
~
3·
~
~
-
-
-1.635
3
14
j
t4+12+
14+1214+10+
14+10-
-
+
1.
3+
'3'Shift
-
-
-
-
-
-
3
-
3
-
-
-
+
-
-
-
1.0
2.5
2.5
5.0
5.0
1.5
1.5
1.0
1.0
11
11
150
I
~
-
-
~
2.9
3.8
1 71
1
7
33
33
-
-
-1.525
Vdc
~
~
-
n,
I I ILl
I
-
-
P2-.r-LVIHA
:
VIL
P3-.r-LVILA
V,L
6
6
6
@
~-
-
-
tVee l
7
6
7
-
-
P3
PI
P2
-
.-
8
-
-
-
1.16
'8
'4
-
-
1.16
8
4
4
4
VILAm..: VEE
3
Logic "I"
Output Vol_
Logic "0"
Min
+2I"e
-
IV-.
VI_
VII""..
VI_
VIa.-
VEE
~.880
~.780
-1.920
-1.850
-1.265
-1.106
-1.610
-1.475
~.830
-1.820
-1.000
-1.400
-5.2
-5.2
-6.2
TEST VOLTAGE APPLIED TO PINS LISTED IIILOW:
+121"1:
IVCCI
VEE
G_
12
4.6
12
·4.6
12
4.5
12
4.&
-
12
4.5
-
-
12
4.5
1.2.3.8.9.10.
11.13.14.15.16
7
-
12
4.5
1.2.3.7.9.10.
11.13.14.15.16
-
8
12
4.5
_In
_Out
-3.2 V
7
6
12
+2.0 V
4.&
Min
Typ
Max
Min
Max
Unit
VI_
-
62
78
-
86
mAde
1.2.8.9.13.14
220
....-
1
8
-
""de
-
7
VILmIn
VIH_
Ie
12
'inH
7
8
-
460
375
-
-
:116
220
'inL
VOH
0.5
-
0.5
-
-
-
1
0.3
-
6
-1.090
~.880
-11.930
-
-11.780
~.825
~.830
Vde
1
1.2.3.8.9.10.
11.13.14.15.16
-
6
-1.920
-1.6&5
-1.850
-
-1.620
-1.820
-1.545
Vde
-
1.2.3.1.8.9.10.
11.13.14.15.16
6
-1.100
-
-O.9S0
-
-
-O.B45
-
Vdc
-
6
-
-1.635
-
-
-1.600
-
-1.525
Vdc
-
6
-
-
4.0
7.5
-
-
n.
W
--
....
MCl0660F T_ Lima
..."1:
~
POONer Supply Or.in
Cu"lnt
Input Cu"ent
86
VOL
Output Voigge
Logic "1"
Thr.... old VoIt.ge
VOHA
Logic ''0''
Threlhold Voltage
VOLA
!:!.
:I
C
II>
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
~
II>
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
t/J • Oon't Cara
See Gen ... 1 Information section for packaging.
3·316
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
ELECTRICAL CHARACTERISTICS
3:
...
...
c;n
Each full temperatura range MECL 10.000
series circuit has' been designed to meet the
de specifications shown in the test table.
o
C11
after thermal equilibrium has been estab-
0)
lished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow grealer than 500 linear
fpm is maintained. Outputs are terminated
through a lOO-ohm resistor to -2.0 volts.
Test procedures are shown only for selected inputs and outputs. Other inputs
and outputs are tested in a sim ilar manner.
-
O
:J
....
S'
c:
(1)
a.
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
lVolts'
lilT...
Temper.ure
-&&"C
w
+:ZSOC
+,25"c
W
......
P;n
Undor
Test
Ch.racteristk;
Symbol
Power Supply Drain Current
'E
linH
14
linL
14
I nput Current
logtc .""
Output Voltage
logic "0" Output Voltage
-
+25"C
-a"C
Min
8
MHo
VOH
13
13
VOL
13
-1.920
Logic "'"
Threshold Voltage
VOHA
13
13
-1.100
-1.100
Logic "0" Threshold Voltage
VOLA
13
Typ
61
84
374
0.5
-1.0B0
-LOBO
-
MCl0&61L Tat Limits
I
Min
76
0.3
-{I.880
-{I.880
-{I.780
-{I.780
-{I.825
-{I.825
-1.855
-'.850
-1.620
-1.820
-0.845
-0.845
-1.600
VIHAmi"
-0.880
-0.780
-1.920
-1.850
-1.255
-1.510
-1.105
-1.475
-5.2
-0.630
-1.820
-1.000
-1.400
-5.2
mIX
I
-5.2
TEST VOLTAGE APPL'EO TO PINS LISTED BELOW,
220
-1.835
VILmin
+1260 C
0.5
-{I.930
-{I.930
-{I.950
-{I.950
VILA
I VEE
VIH max
Max
Unit
VIHm_
VIL min
VIHA min
VILA max
VEE
lVee'
Gntl
84
220
mAde
2.7,9,14,15
-
-
-
8
1,16
.Ade
14
8
14
-
-
8
1.16
1,16
-
8
8
1,16
1,16
.Ade
-
-0.630
-{I.630
Vdc
Vde
2
15
I -1.545
Vde
14
Vde
Vde
-
T
I -1.525
-
-
-
Vde
2
15
-
8
1,16
8
8
1,16
1,16
8
1,16
14
-
Pul.ln
PuI.Out
-3.2 V
+2.0 V
14
13
8
1,16
I ~
~
~
~
SWltdling TUMI
1100 o Load'
Propagation Celay
Rise Time (20% to 80%)
Fall Time (20% to 80%1
It14+1~ I
t14-13+
13
13
t13+
13
tl~
13
1.5
1.5
1.1
1.1
4.0
4.0
2.0
6.0
6.0
3.3
2.0
3.3
~
I
-
-
I
-
ELECTRICAL CHARACTERISTICS
s:
Ea:h full temperature ran,," M ECl 10,000
.rie. circujt hI. been designed to meet the
de _ifi""tion. Ihown in the toll tabla,
eftor thermol equilibrium ha. baan established. The circuit i, in 8 test socket or
mounted on
8
n
......
o
~
......
printed circuit board and
,,.."Mr. lir flow
gr.t., than 500 linear
nO
!pm i. maintained. OutpUt. ore terminated
::J
through a l000hm miotor to -2.0 volts.
Tilt pr~um are Ihown onlv for IIl.:tld inputo and output •. Other inputs
and output.ar. tested in a similar manner.
:!.
::J
C
...
(II
C.
F SUFFIX
CERAMIC PACKAGE
CASE 650
TEI;r VOLTAGE VALUES
'fl
to)
...
co
I
CVohll
.T. .
T _..
....C
+211"1:
+1a"C
~
Symbol
Pow.- Supply Onin Cu"..,t
Ie
I .. H
Input CUrTent
VOH
12
2
2
1
VOL
I
I
I ..
Logic "1"
Outpu.VoI_
Logic "ft' Outpu. Vol_
Logic "I"
Th_oIdVol_
VOHA
Logic "ft'Th_VoI_
VOLA
_"'T_
1100 n LolIIl
"'-Ion DoIoy
12+112-1+
11_ Timo 120'''0_1
F.I Timo 1_10 80!11
'1+
";~
1,>
•
PIn
U_
T. .
I
I
,
,
,
I
I
-
-II"c
Min
-
0.6
-1.0B0
-LOBO
-1.920-1.100
-1.100
84
374
-
- -
MC10&81F Tett Limitl
+211"1:
Min
Typ
-
61
0.6
-4.930
-4.930
-4.880
-4.880
-1.855
-I.B50
-
-4.950
-4.950
-
-1.836
-
-
-
1.5
1.5
1.1
1.1
4.0
4.0
2.0
2.0
Min
-
-
0.3
-4.825
-4.825
-1.820
-4.845
-4.846
-
VILmin
VIHAmln
VILA_
VEE
-4.880
-4.780
-4.630
-1.920
-1.850
-1.820
-t.256
-1.105
-1.610
-1.475
-1.400
-5.2
-5.2
-5.2
~1.000
,
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+ta"C
76
220
-4.780
-4.780
-1.820
VIH_
84
220
-
CVCCI
GIld
UMt
VIH .....
VILm"
V'HAmin
VlLAma:
VEE
mAde
2.3.6.11.13
2
-
-
-
'12
12
12
12
12
12
12
12
12
4,5
4,5
4,5
4,5
4,6
4,5
...._OU.
-3.2 V
+2.0 V
I
'2
4,5
.Ade
-4.630
-4.630
."de
Vde
Vde
-1.646
Vde
-
Vde
Vde
-1.800
-
-1.526
Vde
6.0
6.0
3.3
3.3
-
-
os
~
6
3
2
-
2
-
-
6
3
2
-
Pu.. ln
2
-
-
-
!
4.6
45
4.&
! ! !
MCl0561
(continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C
Vee,· VCC2
+2.0 Vdc
,,,.± j t""
Coax
Input
V out
~..
PROPAGATION OELAY
r---- ----,
I
I
I
50
Input Pul ..
1+ - t-· 2.0t.. 0.2
(20 to 80")
n.
V out
. IO-ohm t ... mln~k)n to ground 10ceted In Hch ICOpe ch.nnel Input.
UnuMd outputs I:onnected to I
All Input end output Clbl., to the
I.",~ of 50-ohm
1 OO-ohm ,.Iltor to ground.
IC" .r. equal
coa.'aI e..,I.. Wlr. 'enath Ihould
be < 1/. inch from TPln to
in~ut
pin and TPout to output pin,
VOU! I, 2:1 .ttenueted.
VEE· -3.2 Vdc
A complete mux/demux operation on 16 bits for data
distribution is illustrated in Figure 1. This system, using
the MC10536 control counters, has the capability of in·
crementing, decrementing or holding data channels. When
both SO and Sl are low, the index counters reset, thus
initializing both the mux and demux units. Thefour binary
outputs of the counter are buffered by the MC1050ls to
send twisted·pair select data to the multiplexer/demulti·
plexer units.
APPLICATION INFORMATION
The MC10561 is a true parallel decoder. No series
gating is used internally, eliminating unequal delay times
fOund in other decoders. This design provides the identical
.. lIS delay from any address or enable input to any
Cl!-'tput.
3-319
FIGURE 1 - HIGH SPEED 16-BIT MULTIPLEXERIDEMUL TlPLEXER
s:
n
c
~
en
en
Control Selection
MC10501
I::J }
~
r--
~
MC10515
nO
X'")(i)
- L
~
::J
51
1514131211109 8
::J
76543210
c:
CD
MC10536
E:
CR
A
t:J"}
!:!-
SO
B
C
'CJ. i
0
H>
E1
.--- C
r--
B
r-A
~
MC10564
E1
.---- C
r--
MC10564
B
.-A
DO
DO
w
W
'"o
MC10501
50
MC10515
H
W)~
~
~
50
51
~
~H>---
J 2. J"~~
X I
.
51
CR
A
CR
MC10536
B
C
0
~
LL
)("""X.
~
E1
~:
EO
~
MC10561
1514131211109 B
I
E1
rfr=:
EO
MC10561
-
76543210
MECL 10,000 series
BINARY TO '-8 DECODER
(HIGH)
MC10562
The MC10562 is designed to convert three
linesof input data to a one-of-eight output. The
selected output will be high while all other outputs are low. The enable inputs, when either
or both are high, force all outputs low.
POSITIVE LOGIC
EO
(8)
E1
(3) 15
2
6 (10100
5
(91 Q1
4 lSI Q2
A ,1') 7
3 (7) Q3
13 (1) Q4
8 (13) 9
Po
= 315
tpd =
C
Numbers at and of terminals ar. pin number. for L package (C.se 620).
Numbers in parenthesi, denote. pin numbers for F package (ca. 650).
ns typ/pkg (No Load)
nl
typ
I
Ca ..
I
VCCI
VCC2
VEE
I
620
I
Pin 1
Pin 16
Pin 8
I
660
I
Pin 6
Pin 4
Pin 12
TRUTH TABLE
INPUTS
£1 C
B
A
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L
L
H
H
H
H
"" ''"" ''""
'" ''Car.
'" Don't
H
G~.'lnform.tion
OUTPUTS
~O
~
S ..
4.0
(2) 14
00 01
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Q2 OJ
04 05
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
&
section for packaging.
3·321
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
ae
07
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
ELECTRICAL CHARACTERISTICS
3:
n
o
at
Each lull temperature range MECL 10.000
.riescircuit has been designed to meet the
de specifications shown in the test table.
after thermal equilibrium has been established. The circuit is in 8 test socket or
mounted on
8
~
m
N
printed circuit board and
transver. air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through 8 l00-0hm resistor to -2.0 volts.
nO
-
Test procedures ar. shown only for selected inputs and outputs. Other inputs
and outputs are tested in a similar manner.
::J
~.
::J
c:
CD
Q.
L SUFFIX
CERAMIC PACKAGE
CASE 620
TEST VOLTAGE VALUES
(Volt.1
f l ...
T ...per.tur•. VIH .....
....C
+25°C
+121i"C
~
"l
"l
Vil min
V'HAntin
ViLA ....
VEE
-0.8111
-1.920
-1.256
-1.510
-5.2
-0.780
-1.850
-1.105
-1.475
-5.2
-0.630
-1.820
-1.000
-1.400
-5.2
MC10512L Test Limit,
Ct.,.ct.i.ic
Power SupptV Drain Current
I nput Current
Symbol
Pin
Und.
TOIl
8
Ie
linH
14
+2&oC
-se"C
Min
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Mo.
84
-
-
Min
-
linL
14
0.5
-
0.5
Logic ''1''
Output Voltage
VOH
13
-1.080
-0.8111
-0.930
Logic "0"
Output Voltage
VOL
13
13
-1.920
-1.920
-1.655
-1.665
-1.850
-1.850
logiC
"1"
Threshold Voltage
VOHA
13
-1.100
-
Logic "0"
Threshold Voltage
VOLA
13
13
-
-1.835
-1.835
t14+13+
'14-13,+
13
13
-
-
-
13
-
-
,-
13
-
-
Typ
+121i"C
Mox
Min
Mo.
Unit
VIH
mil.
VIHAmin
ViLA ....
VEE
8
-
-
8
1.16
8
1.16
8
1.16
8
8
1.16
1.16
8
1.16
8
8
1.16
1.16
81
78
84
-
220
-
-
IoI Adc
-
-
0.3
-
,..Adc
"-
I.
-
14
-
-
-
-
-
-0.780
-0.825
-0.630
Vde
-
-1.620
-1.620
-1.820
-1.820
-1.545
-1.545
Vdc
Vde
2
15
-0.950
-
-
-0.845
-
Vde
-
-
-
-
-1.600
-1.600
-
-1.526
-1.525
Vde
Vde
-
-
1.5
1.5
1.1
4.0
4.0
6.0
6.0
3.3
-
-
ns
-
-
-
-
3.3
-
-
!
-
-
-
SVJitching Times
I1CJO.ohm loadl
ProJ)9tion Del.v
Rise Time
(20% to 110%1
F.U Time
(20%'080"1
1.1
2.0
2.0
(Veel
Gnd
V,Lmin
mAde
-
"
2
15
-
Pul .. ln
PulteOut
14
13
j j
-32 V
8
1.16
+2.DV
1.16
!i
ELECTRICAL CHARACTERiSTICS··· .
e..h full tom_.turo ,.ngo MECL 10.000
~
....
.rielcircujt hi. been designed to meet the
de lPfICificationl shOwn in the test table.
o
~
after thermal equilibrium has been IstaboIIshed. The circuit is in 8 test lOcket or
mounted on a printed circuit board and
trlnlYer. air flow greater than 500 lir)8ar
N
fpm is maintained. Outputs are terminated
8:::s
~
th,ough 8 l00-0hm , .. isto, to -2.0 volts.
Test procedures are shown only for selected inputs and outputs. Other inputs
and outputs are telted in 8 similar manner.
~.
:::s
5i
Co
F SUFFIX
CERAMICPACKAGE
CASE 650
TEST VOLTAGE VALUES
(Vah,)
.rOIl
VIHmIX
VILmin
VIHAmin
VILA_
VEE
-0.830
-1.255
-1.105
-1.000
-1.610
-1.415
+1211"C
-1.920
-1.850
-1.820
-5.2
+ZSoC
-0.880
-0.780
T....per8tur.
-55"c
ctJ
to)
p..)
to)
I
I
Chlr.ct.,istic
I Svmbol
Power Supply Dram Current
I nput Current
I
L
-55"c
tE
linH
2
-
2
1
0.5
-LOBO
1
1
1
-1.920
-1.920
-1.100
-1.655
-1.655
-1.850
-1.850
-
-0.950
1
1
-
-1.635
-1.635
-
-
-
-
-
1.6
1.5
1.1
4.0
4.0
I.
1
1
1
'-
1
-
-
1.1
VOH
Min
Min
Mo.
TV'
61
Mo.
Min
16
-
84
Unit
mAde
-
220
-
-
0.3
-0.825
-
,..Adc
-
,..Adc
-0.630
Vde
2
-1.820
-1.820
-0.845
-1.645
-1.645
6
3
-
-
Vde
Vde
Vde
-
-
2
-
-
-1.525
-1.525
Vde
Vde
-
-
-
-
n.
-
-
-
-
-
-
-
-
84
-
-
-0.880
0.5
-0.930
-
-1.620
-1.620
-
-1.600
-1.600
-0.180
VIHmelII
VILmi"
VIHAlllin
2
-
-
2
Output Voltage
LogiC "0"
VOL
Output Voltage
LogiC "1"
VOHA
Threshold Voltage
lOgiC "0"
VOLA
Threshold Voltage
-
-
-
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+l21oC
+2SoC
Mo.
T...
12
linL
LogiC "1"
MC1068ZF T. . Limill
Pin
Und... ·
-1.400
-
-
'Vee
Gnd
VILA . . .
VEE
12
-
-
-
-
12
12
12
4.6
-
-
12
12
12
4.5
4.5
4.5
8
3
-
12
12
4.6
4.5
Put_In
Pu. . Out
-3.2 V
+2.0 V
2
1
-
-
4.5
4.6
4.5
Switching Times
(l00-0hm loed)
Propeglltion Delay
t2+1+
'2_1_
Rise Time
(20%1080%1
Fall Time
(20% '0 80%1
I
-
-
2.0
6.0
6.0
3.3
2.0
3.3
-
-
-
!
12
4.6
I I !!
MC10562 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS ~ 2SoC
Vcc, = VCC2
"'2.0 Vdc
Input
.::±1t'~" ,. .
I
I
I
I
Generator
±. 0.2
PROPAGATION DELAY
I
Pulse
Input Pul ..
ti- ., t- ::: 2.0
Vout
50
Von
I
O%
t--
I
"S
(20 to 80%)
~
-----..
I
+'.11 V
- ----+0.31 V
t++
80%
V out
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
Unused outputs connected to •
scope are equal lengths of 50· ohm
coaxial cabl.. Wire length should
be < 1/4 inch from TP in to input
pin and TP out .t~ output pin.
V out i. 2: 1 attenuated.
l00-ohm resistor to ground.
veE = -3.2 Vdc
FIGURE 1 _. DEMULTIPLEXER (1 OF-S LOCATIONS)
APPLICATION INFORMATION
The MC10562 is a true parallel decoder. No series
gating is used internally, eliminating unequal delay times
found in other decoders.
Data Select
00
This device is ideally suited for demultiplexer applications as shown in Figure 1. One of the two enable inputs
is used as the data input, while the other is used as a data
enable input.
a,
02
c
Data In
Enable
A complete mux/demux operation on 16 bits for data
distribution is illustrated in Figure 2. This system, using
the MC 10536 control counters, has the capability of incrementing, decrementing or holding data channels. When
both SO and Sl are low, the index counters reset, thus
initializing both the mux and demux units. Control information via twisted pair lines is sent through MC10501
gates to the MC10515 line receivers to provide select
data to the multiplexer/demultiplexer units.
E,
MC'0552
Oata Output
3-324
~....
FIGURE 2 - HIGH SPEED 18-8IT MUL TIPLEXERIDEMULTIPLEXER
C
~
Control Selection
MC10501
N
0o
MC10515
~-.XJ. I
:J
~.
:J
Lso
r-
~Sl
1514131211109 8
76543210
CR
A
8
C
0
......
~
tU-
~
El
,---- C
;-- 8
~A
r - El
MC10564
-C
MC10564
-8
r-A
DO
DO
w
W
"l
U1
so
MC10601
~
MC10515
......
.--
-L)~
SO
Sl
j
)~
~'---V
Sl
MC10636
CR
A
CR
~
--L
XX
~
8
C
C
(I)
C.
MC10536
0
~
I
El
~:
EO
MC10562
1514131211109 8
~
r - - - El
~:
EO
MC10562
76543210
l . ._____________________--'·.1
MECL 10,000 series
a·LlNE MULTIPLEXER
MC10564
The MC10564 is a high speed. low power
MECL eight·channel data selector which routes
data present at one·of·eight inputs to the out·
put. The data is routed according to the three
bit code present on the address inputs. An en·
able input is provided for easy bit expansion.
TRUTH TABLE
---ENABLE
L
L
L
L
L
L
L
til -
DATA
ROUTED
FROM:
ADDRESS INPUTS
C
B
A
L
L
L
L
L
L
L
xo
H
H
H
L
Xl
X2
X3
H
L
L
L
L
H
H
H
H
H
H
H
X4
X6
X6
X7
H
4>
4>
4>
L
H
L
Po - 310 mW tvp/pkg (No Lo.d)
tpd - 3.0 nl tvp
Don't Cere
.:",
POSITIVE LOGIC
.,
A
(11)
7
:=.
B
(13)
C
(14)
En.bi8
(6)
)
1.
10~
9
-----
2
XO
(10)
6
Xl
(9)
5
X2
(B)
4
X3
(7)
3
X4
(16) 11
X6
(16) 12
X6
(1)
13
X7
(2)
14
)
15
..
(3)
J
-r-;R
.;:
:J
B'r
~
R
..
r
r
r
~
Numbers at end of terminals are pin numbers for L package (Case 620)
Number. in parenth..is denot.. pin numbers for F package (Case 6501
S .. Ganar.1 Information section for peckellnlend mexlmum r.tlnge.
3-326
Case
VCC1
VCC2
VEE
620
PinT
Pin 16
Pln8
660
Pin 5
Pin 4
Pin 12
,-'!'.":
••
~,'" /0': .":~. ·.1~. ,:',"~:~r- '~"~"':~'~':~::'~:~~~~~.~~'.' !~:~::'::~~~:=':~~:'t~~~:~~:~~::~:j~~'~~~~.r~~~~~~
~.
....
o
E'r'CT~L~ACf&RIUjCS.
hchfuU _ _.tur. r _ MECL 10.000
....i.. circ~it h. been designed to meet
the
A
de specification. thaw" in the test table,
after tharme' equilibrium h. been established. The circuit il in a test socket or
mounted on a printed circuit bo.d and
tranwerse air flow gr••ter than 500 line.r
fpm il maintained. Outputs are terminated
through 8 l()().ohm resistor to -2.0 volts.
Test procedures are shown for only one
1
en
••
c
'0
En"'.
2
~
c;I I I I I I
t Imn
xo.
input, or for one set of input conditions.
Other inputs are tested in the same manner.
x,
5
X'
4
X4 "
13
)(7,.
Co)
N
-...I
Pin
Ct.rect.. iltic
Symbol
Power Supply Drain Current
IE
I nput Current
(Votul
T .........
..."1:
+25"c
+12&"1:
V.Hmax
-0.880
-0.780
-0.830
+2SoC
VIH_
Typ
Mo.
Min
M..
Ik*
-
83
-
60
75
265
-
83
265
""'de
,.Adc
0.5
-0.930
V'HAmin
ViLA ....
VEE
-1.920
-1.850
-1.820
-1.265
-1.105
-1.000
-1.510
-1.475
-UOO
-5.2
-5.2
-5.2
-
VILmin
VIHAmin
VILA miX
VEE
-
-
-
8
.8
(Vee I
Gnd
-
0.3
-
,.Ade
-
-
~.780
~.825
~.630
Vde
4.9
4
2.7.10
-
-
8
8
1.16
1.16
1.16
1.16
455
-
VILmin
TEST VOLTAGE APPLlEO TO PiNS LISTED BELOW
+12&"1:
Min
~.880
CASE 820
TEST VOLTAGE VALUES
M..
0.5
-1.080
c:
It)
.eo
LSUFFIX
CERAMIC PACKAGE
fi_
Min
VOH
lin H
"",
MC10684L T_ Llmilo
_Oc
8
4
4
15
lin L
Logic "1"
Output Voltage
U_
TOM
:::J
,/
IliE
X612
~
o
...5'
,s
I I fTTT=L..-t I I fTF1-.-.IllfTn-I fTTT=L..--
X33
xe
"'"
-
2
VOL
15
-1.920
-1.655
-1.850
-
-1.620
-1.820
-1.545
Vdc
9
2.4.7.10
-
-
8
1.16
Logic "1"
Threshold Voltage
VOHA
15
-1.100
-
-0.950
-
-
-0.845
-
Vdc
9
7.10
4
2
8
1.16
Logic "0"
Threshold Voltage
VOLA
15
-
-1.635
-
-
-1.600
-
-1.525
Vde
-
4.7.10
Logic ''0''
Output Volt.
Switching Times
l1000hm loedl
Pro~tton Delay
Rise Time
1+
15
15
15
15
15
15
15
(2O%108O'W.1
FeI'Time
(2O%1080'l1.1
,-
IS
'4+15+
'4-1517+15+
'7-1512+1612_15+
1.3
1.3
1.8
1.8
0.9
!
4.6
4.6
6.1
6.1
3.0
3.0
3.3
1.5
1.5
2.0
2.0
1.0
1.0
1.1
3.3
1.1
3.0
3.0
4.0
4.0
2.0
~
4.5
4.5
6.0
6.0
2.9
2.9
3.3
3.3
1.2
1.2
1.9
1.9
0.9
!
4.5
4.5
6.0
6.0
2.9
2.9
3.4
3.4
n.
1
9
9
5
5
7.5
7.5
9
9
9
Pue-In
+1.11 V
-
-
-
4
4
7
7
2
2
4
4
8
1.16
PuI.Out
-3.2 V
+2.0 V
15
8
1.16
2
j j j
s:
ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10.000
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been estab·
lished. The circuit is in a test socket or
A
11
•
13
mounted on a printed circuit board and
transverse air flow greater than 500 linear
C
14
En.iii'8
fpm is maintained. Outputs are terminated
mrouWl a lOO-ohm resistor to. -2.0 voltl.
Test procedures are shown for onlv one
...o
(")
C1I
~
0o
6
:::1
XO
10
XI
9
X2
•
X3
7
!:!.
t I I I I I L--
:::1
X5
I~
~
1
X7
2
TEST VOLTAGE VALUES
(Volts)
IIgj
16
X6
CPT . .
TemfMr·tur.
-$"1:
+~e
CAl
I'.)
C..... ct.istic
Power Supply Drain Current
Input Current
Symbol
Pin
U_
T...
IE
12
lin H
lin L
MC10664F T_ Limits
+25oC
~5"1:
-0.780
-0.630
VIHmn
13
6.8.11.14
8
-
-
-0.845
-
Vdc
13
tt. 14
3
-
-
-
-1.600
-
-1.525
Vde
-
8.11.14
-
-
-
+1.11 V
1.1
4.1
Vde
-0.950
-
12
-1.545
-
-
t3+
8
-1.820
-1.850
-1.635
'
4,5
-1.620
-1.655
-1.100
..
12
8
6.11.14
3
"
-
8.13
0.5
-0.930
-
VOHA
j
4,5
-0.630
,.Ade
Vde
-
-0.780
0.3
-0.825
-
-
-
12
12
6
-
-1.920
Rise Time
(20"'0_)
F ... Time
(20%'080%1
4,5
4,5
mAde
,.Ade
-0.880
-
12
12
83
265
0.5
-1.080
1.5
1.5
2.0
2.0
1.0
1.0
1.1
(Veel
Gnd
-
-
-
Vee
75
265
455
-
-5.2
-5.2
-1.400
60
-
VILmin
3
3
-1.475
Unit
VOL
'8+3+
'8-3t11+3+
'11-3'8+3'8-3+
t3+
-1.105
-1.000
Mo.
Logic "0"
Output Voltage
VOLA
VEE
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
+125"1:
VOH
Switching Times
1100.ohm loedl
Pro~hon Delay
ViLA ....
-t.510
Min
Logic "1"
Output Voltage
Logic "0"
Threshold Voltage
VIHAmill
-t.255
Mo.
Mo.
83
+125"1:
VIL min
-1.920
-1.850
-1.820
Typ
Min
Min
VIH milK
-0.880
8
8
3
Logic "1"
Threshold Voltage
CD
a.
CERAMIC PACKAGE
CASE 650
X415
CD
c:
F SUFFIX
input, or for one set of input conditions.
Other inputs are tested in the same manner.
3.0
3.0
4.0
4.0
2.0
t
4.5
4.5
6.0
6.0
2.9
2.9
3.3
3.3
-
-
-
-
-
-
-
ns
I
13
13
9
9
9.11
9.11
13
13
VIHAmin
.-
13
Pu"ln
-
-
8
8
11
11
6
6
8
8
VILA
mil.
4.1
6
12
4.1
Pul.Out
-3.2 V
+2.0 V
12
4,5
15
III
MC10564 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2SoC
VCCI = VCC2
+2.0 Vdc
Coax
V out
""Cm""
Coax
r-------- --------,
I
I
I
Input
L
i
Pulse Generator
)~
~"
I
)
r
I
Input Pulse
t+ '" t- = 2.0 ±. 0.2
(20 to 80%)
ns
50-ohm termination to ground lo-
cated in each scope channel input
All input and output cables to the
scope are equal lengths of 50-9hm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TPoutto output pin. V out
50
_1-
~
I
:
R
-:;
:
R
r
:
-:;
i
~-:;
~
1
I
8;
~;
I
is 2: 1 attan uated.
VEE = -3.2 Vdc
PROPAGATION DELAY
O%
~
t--
I
+1.1111
- ----+0.31 V
t++
---"..L- 80%
V out
t+
3-329
]
)
~
./
MC10564 (continued)
eight data inputs and an enable. A high level on the enable!
forces the output low. The MC10564 can be connected!
directly to a data bus, due to its open emitter output andi
output enable.
!
Figure one illustrates how a 1-of-64 line multiplexer can:
be built with eight MC10564'swire ORed at their outPUt~
and one MC10161 to drive the enables on each multi-j
plexer, without speed degradation over a single MC10564:
being experienced.
'
APPLICATION INFORMATION
The MC10564 can be used wherever data multiplexing
or parallel to serial conversion is desirable. Full parallel
gating permits equal delays through any data path. The
output of the MC10564 incorporates a buffer gate with
FIGURE 1 - HIF-&4 LINE MULTIPLEXER
ABC
The Bit chosen is dependent on six-bit
code pre.nt on inputs 1. 9, 14 of the
MC10161 and the A. B. C inputs of the
MC10564.
3-330
MECL 10,000 series
DUAL BINARY TO
1-4 DECODER
(LOW)
MC10571
I
The MC10571 is a binary coded 2 line to
dual 4 line decoder with selected outputs low.
With either Eo or E1 high, the corresponding
selected 4 outputs are high. The common enable
E forces all outputs high.
All propagation delay ti mes are equal due to
the internal emitter dotting techniques used.
High impedance 50 k ohm resistors on all inputs
eliminate the need to tie unused inputs to VEE.
POSITIVE LOGIC
T--
fo (2) 14
10(14) QO 3
i ...Q
2
tl(le) QO
i
t2(16) QO 1
I-
A(13)9
r-
13 (1) QO 0
..
i
-,
3 (7) Ql
3
4 (8) Qt
2
e
1
Po - 330 mW typ/pkg (No Lood)
fpd - 4.0 n. typ
B(II)7
,
\
;
1"--'
E
(3) 16
(9) Ql
6 (10)Ql 0
El (6) 2
Number•• t end of termlnall .r. pin number. for L pickage (C ... 620).
Number. in parenthesis denot.. pin numa. for F pickage (ca. 650).
t ..
TRUTH TABLE
ENABLE INPUTS
,.to.
INPUTS
OUTPUTS
E
EO
Et
A
B
atO
att
at2
a13
000
oot
002
a03
L
L
L
L
L
L
H
L
L
L
L
L
H
~
L
L
L
L
H
L
~
L
L
H
L
H
L
L
~
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
L
L
4>
tP""' Don't Car.
See Generel Information section for Pick aging and maximum rating •.
3-331
ELECTRICAL CHARACTERISTICS
EO 14
s:
n
....
o
10 003
Each MECL 10.000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal &qui·
librium has been established. The circuit is
...~
11 002
in 8 test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
g
12 001
::J
ar. terminated through a 1()().ohm fesistor
d.
to -2.0 volts. Test procedures ar. shown
::J
only for _Iected inputs and outputs. Other
inputs and outputs are tested in a similar
manner.
3 013
B 7
4 012
E 15
TEST VOLTAGE VALUES
1~6010
IVo/III
-6&"c
Logic "1" Output Voltage
Logic "0''' Ou1put Voltagll
Logic: "1" Threahold Voitaga
Logic "0" Threshold Voltagll
Switching Tim..
1100,n Loodl
Propegation Delay
'E
linH
linL
VOH
VOL
VOHA
VOLA
t7+8+
'7-6t7+13+
'7-13-
te+
At. Time f2Q% to
~)
Foil Tlmo (20% '0 BOlli
t13+
'6'13
8
14
14
8
13
13
8
13
6
13
8
6
13
13
6
13
8
13
-16"c
Min
Max
Min
MCl0671L Toot Llm~.
+26"c
Typ
Max
-
-
-
0.5
-1.080
-1.080
-1.920
-1.100
-1.100
-
0.5
-0.930
-0.930
-1.860
-0.960
-0.960
-0.880
-0.880
-1.665
-
64
-
-
-
-
-
-
-
-0.780
-0.780
-1.620
-
-
-1.635
-1.635
-
77
220
+l26o C
M..
Min
0.3
-0.825
-0.826
-1.820
-0.846
-0.845
-1.600
-1.600
1.5
4.0
6.0
1.1
2.0
3.3
*~
~
.~
~*
-
-0.630
-0.630
-1.645
-1.525
-1.525
-
-
-
-
-
-
VILmln
-0.880
-1.920
-1.860
-1.820
+2lioC
-0.780
+126"c
-0.630
VIHAmln VILAm ..
-1.266 -1.610
-1.106 -1.476
-1.000 -1.400
VEE
-6.2
-6.2
-6.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Un~
VIHmax
VILmin
mAde
2.7.9.14.16
14
-
-
-
-
14
15
15
-
-
-
15
15
-
~Adc
,!.lAdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
n.
I
VIHAmin VILAma
2.7.9.14.15
-
-
+1.11 V
2.9.14.15
2,7.14.15
+0.31 V
14
14
2
2
I.
I.
2
2
2.9.15
2,9.15
9.14,15
9.14.16
2.9.16
9.14.16
2.9,1&
i.1416
7
9
VEE
8
8
8
8
8
8
8
8
8
8
Pu_ln ~IooOu' -3.2 V
7
6
6
13
13
6
13
8
13
8
IVeel
Gnd
1.18
1.18
1.18
1,16
118
1.16
1.16
1.16
1.16
1.18
+2.0 V
1.18
I II
r __ ._
•••
.
Power Supply Or.in Current
I nput Current
Pin
U_
Toot
VIH .....
~
1
I~
.
I
• Toot
Temper.tur.
Symbol
L SUFFIX
CERAMIC PACKAGE
CASE 620
5 all
El 2
Char8CtM'istic
4>
L
L
L
L
L
L
L
L
L
vo
H
L
XO
Xl
X2
H
H
X3
H
til = Don't Car.
t
0 . . . . 1 Inform.tion ..ction for p.ckaging •• nd maximum r.tings.
3·339
W
B
Numbers at end of terminals are pin numbers for L package (Ca .. 620).
Number. in parenthesis denotes pin numbers for F package (C• • 650),
, ...,
OUTPUTS
E
VI
Y2
Y3
ELECTRICAL CHARACTERISTICS
each full temperature range MECL 10,000
sari.. circuit his been designed to maet
the de specifications shown in the test
table, after thermel equilibrium hes been
elt8biilhed.
The circuit is in 8 test
socket or mounted on 8 printed circuit
board and transverse air flow greater than
XC
X150
II
~
X240
III
~
500 linear fpm is maintained. Outputs are
X3
terminated through a l000hm resistor to
-2.0 volts. Test procedures are shown for
only one input, or for one set of input conditions. Other inputs tested in the same
manner.
7
•
9
2
-
Z
IIII '\""'-
60
"
s:
(")
r----.
30
:
En;bi'; 140
YO 130
....
Y212
~ ...
W
Chlrut.istic
Power Supply Drain Current
I nput Current
Logic "1"
Output Voltage
Logic "0"
MCl11574L T . . Limits
+25o C
-65"e
Symbol
Unci.
Test
Min
IE
8
-
lin H
lin L
4
14
4
0.5
-
0.5
VOH
15
-1.080
-{I.880
VOL
15
-1.920
VOHA
15
-1.100
VOLA
15
'13+15+
113-1517+15_
17_15+
114+15_
114-15+
.+
15
15
15
15
15
15
-
CD
Q.
(Voltsl
T
'::"":.ur.
58
73
220
-0.930
-
-1.655
-1.850
-
-1.620
-1.820
-1.545
-
-{I.950
-
-
-{I.845
-
-1.635
-
-
-1.600
-
4.6
4.6
6.1
6.1
3.0
3.0
3.3
1.5
1.5
2.0
2.0
1.0
1.0
1.1
3.5
3.5
5.0
5.0
2.0
2.0
1.2
1.2
1.9
1.9
0.9
2.0
4.5
4.5
6.0
6.0
2.9
2.9
3.3
3.3
t. t
2.0
3.3
80
330
Vil min
VIHAmin
VILA miX
.s5"c
+25o C
-{I.SBO
-1.255
-1.105
-1.510
VEE
-5.2
-{I.780
-1.920
-1.850
-1.475
-5.2
+125°C
-{I.630
-1.820
-1.000
-1.400
-5.2
+125o C
-
-
Typ
VfHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Min
Min
565
Mo.
Unn
80
mAde
-
220
330
.,Ade
4
14
VIHmax
VIL min
-
-
VIHA min
-
Rise Tune
(20%'080%1
Fait Time
·1~.o8O!l1
.-
15
15
l
-
(Vcel
Gnd
1.16
8
8
1.16
1.16
8
1.16
8
1.16
0.3
-
.,Ade
-
4
-{I.630
Vde
13
-
Vde
14
-
-
-
8
1.16
Vde
-
-
13
14
8
1.16
-1.525
Vde
-
-
14
-
8
1.16
-3.2 V
+2.0 V
4.5
4.5
6.0
6.0
2.9
2.9
3.4
ns
8
1.16
Pul .. ln
+1.11 V
1.3
1.3
1.8
1.8
0.9
-
VEE
8
-0.825
Switching Times
(100 n Loadl
Propagation Delav
miX
-
Threshold Voltage
Logic "0"
Threshold Voltage
VILA
~.780
Output Voltage
Logic '.,.'
::J
c:
TEST VOLTAGE VALUES
Mo.
M..
375
::J
....
III I L...---
Co)
~
8
L SUFFIX
CERAMIC PACKAGE
CASE 620
II I I
Y310
Pin
....
o
~
-'="
!
3.4
.....
I
13
13
13
t3
13
13
-
-
13
13
7
7
14
14
-
14
-
14
Pul.Out
15
j
II
.-
~L~TRlG+&. oCM~""tSTICS,
Each full temperature range MECL 10,000
series circuit has been designed to meet
the de specifications shown in the test
table. after thermal equilibrium has been
established.
The circuit is in a test
socket or mounted on a printed Circuit
board and transverse alT flow greater than
500 Imear fpm IS maintained. Outputs are
7 0
X1
'0
II
~
X280
III
~
X3100
IIII
~
~
6 Z
~
e;;;,bie
2 0
YO
1 0
I I I I L--I I I
~'.
TEST VOLTAGE VALUES
IVoial
liT...
T.,...,.t...
-55"c
+25"c
+125"C
Input Current
Logic "'"
Output Voltage
Logic "0"
Output Voltage
Logic "1"
ThreshOld Voltage
Logic "0"
Threshold Voltage
SwitchinG Times
MC10674F T_ Limit,
Max
+l25o C
Min
Max
-
73
220
330
80
220
330
0.5
-0.930
-
-
-5s"C
Min
M..
80
375
555
0.5
-1.080 -0.880
-
lin L
VOH
Undor
T ...
12
8
2
8
3
VOL
3
-1.920
-1.655
-1.850
VOHA
3
-1.100
-
VOLA
3
-
-1.635
Symbol
Ie
lin H
r:::
It)
.e:
F SUFFIX
CERAMIC PACKAGE
CASE 650
IIII
Y314
Charact.istic
Power Supply Drain Current
::l
~~
813
Y216:
Pin
8
...5'
<-~~
VI 150
4J
~
.-
...o
n
'"
terminated through a 100-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input, or for one set of Input conditions. Other inputs tested in the same
manner
i:
,--"";-,,.-
xo
-
Min
+26"c
Typ
58
-
-
-
VIH ....
-0.880
-0.780
-0.630
VILmin
-1.920
-1.8&0
-1.820
VitIA min
-1.255
VILA_
_1.510
-1.105
-1.000
-.1.475
-1.400
VEE
-5.2
-5.2
-6.2
TEST VOLTAGE APPLlEO TO PINS LlSTEO BELOW
(Vee l
Unit
Gnd
-
VEE
12
12
12
12
12
VIH ....
VILmin
VIHAmin
ViLA ....
8
2
-
-
-
-
8
-
mAde
"Adc:
-
-
4,5
4,5
4,5
4,5
4,5
-0.780
0.3
-0.825
-0.630
"Adc
Vdc
-
-1.620
-1.820
-1.545
Vdc
2
-
-
-
12
4,5
-0.950
-
-
-0.845
-
Vdc
-
-
-
2
12
4,5
-
-
-1.600
-
-1.525
Vdc
-
-
1
+1.11 V
2
-
12
4,6
'ul.ln
'u,.Out
-l.2V
+2.0 V
1
1
11
11
2
3
12
4,5
110011 Leadl
Propagation Delay
Aiae Time
120%'0110%1
Fall Time
(20% '0 110%1
t'+3+
'1-3t11+3_
t11-3+
t2+3'2-3+
.+
3
3
3
3
3
3
3
.-
3
-
-
-
-
3.5
3.5
5.0
5.0
2.0
2.0
2.0
4.5
4.5
6.0
6.0
2.9
2.9
3.3
-
-
-
1.5
1.5
2.0
2.0
1.0
1.0
1.1
-
-
-
-
1.1
2.0
3.3
-
-
-
-
-
-
ns
1
j
-
-
-
j
MC 10574 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC
Vee,· Vee2
+2.0 V.dc
''''f
r-------
V out
it" .
------,
60
Input
TPout
Pul. Generator
Input Pulse
tT'" t- '"' 2.0 ±. 0.2 ns
(20 to 80%)
50..ohm termination to ground 10·
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cable. Wire length should
be < 114 inch from TPin to input
VEE = -3.2 Vdc
pin and TP out to output pin_
V out I, 2: 1 attenuated.
PROPAGATION DELAY
V out
V out
3-342
'\
QUINT LATCH
MECL 10,000 series
~----------'
MC10575
is in the high state, a change in the information present
at the data inputs will not affect the output information.
The reset input is enabled only when the clock is in the
high state.
ThrMC10575 is a high speed, low power quint .latch.
It features five 0 type latches with common reset and a
common ~o·!f1put clock. Data is tranSferred on the negative e4ge of the clock and latched on the positive edge.
t1f/o"1!lock inputs are "OR"ed together. Propagation
.Iays'are typically 2.1 nanO!l~n4s. from each data input
111 the :output.
. Any C;hal198. On the. data input will be reflected at the
ciltIlUfs while the clock is low. the outputs are latched
po.sitiye transition of the clock. While the clock
1M
The MC10575 alldwsstorage of five bits of information,
and it is useful in temporary storage applications in high
speed central processOrs, accumulators, register files, digital
communication systems, instrumentation, and test equ ip·
ment.
., tI1i
POSITIVE LOGIC
NEGATIVE LOGIC
00Io---------~--~
1400
DOlO-------------~
12-----------+-1~
1501
0213-----------+-i~
2 02
D21~--------_+_+~
2 02
03
9------~--4_~~
3 03
03
3 03
D.
5--~------4_~~
4 04
o.
4 01
I
!'
01
15 01
co
Co6
Ci
7
·A_t 11 ____________--4____-:'
TAUTHTA8LE
C{)
~
R_t
On+1
L
L
L
L
L
~
~
L
H
~
~
H
~
tP
H
L
L
an
an
PD - 400 mW typ/pkg (No Load)
~
~
H
tP
H
L
tpd - 2.6 netyp (Dllt. to Output)
~
H
H
L
H
~
VCCI - Pin 1
VCC2 - Pin 16
VEE -PinS
0
- don't car•
. . . . . . . . Infoml8ti!NIl8Cticin for packaging end "",ximum retingo.
~Gi
3-343
ELECTRICAL CHARACTERISTICS
,.
DO
s:
0
00
'0
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de spftcifications shown in the test table,
after thermal equilibrium has been esut>fished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow weater than 500 linear
fpm is maintained. Outputs are terminated
through a l000hm resistor to -2.0 volts.
Test Procedures are shown only for selected inputs and outputs. Other inputs
and outputs are tested in the same manner.
...a
Q,,
.
DJ
:
C
i
Chltactetittic
Power Supp4y Drain Current
IE
8
-
linH
6
7
10
11
All
14
15
14
15
-
Input Current
Input Leakage Current
linL
LOgic: "1"
Output Voltage
VOH
Logic "0"
Output Voltage
VOL
Logic: "1"
Threshold Voltage
Logic "0"
Threshold Voltage
Switcltinl Timet
Data Input
Clock Input
Reset Input
Setup Time
Hold Time
Ri. Time (20 to 80%1
Fon T,imo (20",_1
VOHA
VOLA
Min
+25o C
Typ
-
-
78
-
-
-
-65"c
Min
Mo.
0.5
-1.080
-1.080
14
t5
14
15
-
-
-
-
0.5
-0.930
-0.930
-
-1.920
-1.920
-0.880
-0.880
-1.655
-1.655
-1.100
-l.too
-
-1.850
-1.850
-0.950
-0.950
-1.635
-1.635
-
-
-
R
+25oC
+125 oC
-0.880
-0.7811
-0.630
-
Mo.
97
290
290
290
645
-0.780
-0,7811
-1.620
-1.620
-1.600
-1.600
+125Oc
Min
Mo.
Unit
V.H mix
t+
,-
-
14
-
t4
--
14
14
14
14
14
-
-
-
-
1.0
1.0
1.0
1.0
1.0
1.0
2.5
1.5
1.1
-
1.1
-
(i),1 'n~vidual'V ...t each input; apply Vel mm to pin unct.r telt.
a>~tpu~~~d ~o ~"'}~~~_~~or ta_tolt.
_
,""
::J
C
to
Cl.
-
mAde
-
-
0.3
-0.825
-0.825
-1.820
-1.820
-0.845
-0.845
-
-
-
-
2.1
2.1
2.6
2.6
2.8
2.8
-
2.0
2.0
3.5
3.5
4.3
4.3
3.9
3.9
-
3.5
3.5
-
-
-
VIL min
-1.920
-1.850
-1.820
VIHA min
-t.2I5
-1.111i
-1.000
~Adc
•
VIL min
VillA min
6
7
10
l'
-
-
-
CD
-0.630
-0.630
"Adc:
Vdc
Vdc
10
12
-1.545.
-1.545
Vdc
Vdc
-
6
6
6,10
6,12
-
-
Vdc
Vdc
Vdc
Vdc
-
6
6'
10
12
-
6
6
+0.31 Vd.
6,7
6,7,
7
7
6
6
7
7
6,7
8,7
-
-1.525
-1.525
-
-
-
ViLA .....
VEE
-5.2
-1.475
-1.400
-6.2
-5.2
-'.500
VOLTAGE APPLIED TO PINS LISTED BELOW:
+1.11 Vd.
'10>14+
'10-14t6-14+
'&-14t11+4'11+14tsetup
'hold
::J
(Vo""
V,H ....
MCl11i75L T. . Limk,
Pin
Und_
T. .
...
TEST VOLTAGE VALUES
OT. .
Tamperature
-lisOc
R, •• "
Sy_1
8"
L SUFFIX
CERAMIC PACKAGE
CASE 820
J
OJ
-~"
~:
e
CTI
.....
en
-
os
0'
ns
I
-
5
10
-
-
VILA ....
-
-
,
,
-
10
12
'ul.ln
PU .. OU.
10
10
6,10
6,10
7,11
7,11
6,10
6,10
10
14
'0
,
VEE
Gnd
8
8
1'6
1,16
~
1,18
1,16
1,16
1,16
8
8
1,18
1,18
8
1,18
8
1,18
8
116
8
-3.2Vdc +2.oVdc
1,16
8
8
8
8
:414~
.:..G
~. ~
; MC10575 (continued)
SWITCHING nME TEST CIRCUIT
Vee 1 =vCC2-
""ill""
r---DO
10
1
V out
---l
14
100
I
I
I
1
0,1
I
60
Data Input
TP out
PRF = 1.0 MHz
t+ = t- = 2.0 ns
(20% to 80%)
VOL ~ 0.31 V
VOH ~ 1.1, V
04 5'~1-------+-+~
~~ ~ I
R._t11~1~______~~__~
'----IF"~
VEEL~'VdC
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
1/4 inch from TPin to input pin
and TP out to output pin.
<
Unused outputs connected to a 100
n resistor to ground.
3-345
MC10575 (continued)
VOLTAGE WAVEFORMS
RESET INPUT
CLOCK~
\
/r-------+l.11
L J________ +0.31
v
RESET
+0.31 V
r--.....,.+----- +1.11 V
OUTPUT
'------+0.31 V
DATA INPUT
r-----.'----- +1.11
V
DATA
+0.31 V
~---.....,.:+---- +1.11 V
OUTPUT
+0.31 V
CLDCKINPUT
DATA
~----+1.11
V
CLOCK
'--"------+0.31 V
t6-14+
------+1.11 V
OUTPUT
'-----''---------+0.31
v
~---.....,.-----+1.11
V
D
'----+0.31 V
tsetup'-'+---r---t--thold
r-------+1.11 v
NOTE:
tsetup I, the minimum tima befbre the positive
tranlltlon of the clock pul .. (e) that information mUlt
ba pres.nt at the data Input (0),
thold I, the minimum tim. aftar the pOsitive
transition of the clock pul .. (e) that information mUlt
c
--------'·--------+0.31 V
a
remain unchanged at the data input (0).
3-346
_/
MECL 10,000 series
LOOK-AHEAD CARRY
BLOCK
MC10579
The MCI 0579 device has 12 low power gates
internally connected to perform the look-ahead
carry function. This device has high Z input
pulldown resistors and open emitter outputs.
This device has applications in fast look-ahead
adders such as with the MC10581. It can be
used also as a boolean function generator.
Po : 300 mW typ/pkg (No Load)
1pd = 3.0 ns typ (Carry. Propagete)
4.0
n.
tv'P (Generate)
POSITIVE LOGIC
G3(9)5 -----------'~
P3(1) 1 3 - - -...._ _ _ _ _ _ _....,,~_.,
G2(13)9---+-------'~
P2116) 12
~m=:
3(7) C n +4
---t:;:=======:4--" )c>---++.
C n (15)11
1513)PG
GlIll)7
P1114)10
6(10)C n +2
GO(S)4
L
P012)14
Pa - PO + P1 + P2 + P3
GG ~ IGO + PI + P2 + P3) (Gl + P2 + P3) (G2 + P3) G3
C n +2 = (C n + PO + P1) (GO + P1) Gl
C n +4 = (C n + PO + P1 + P2 + P3) (GO + P1 + P2 + P3) (Gl + P2 + P3) (02 + P3) G3
Numbers at end of terminals"ore pin numbers for L package (e ... 620).
Numbert In parenthesis denotes pin numbers for F package (CUll 660),
See General Information section for packaging.
3-347
VCCI
VCC2
VEE
~
~
~
Pin I (e)
Pin 16 (4)
Pin S 112)
s:
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has t..n designed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 100-0hm resistor to
-2.0 volts. Test procedures are shown only
for selected inputs and outputs. Other
inputs and outputs are tested in a similar
manner.
...
n
o
L:
5
::1, ~
U1
.....
c.c
nO
3
2
::J
~.
II I 1111"'"" -'
11
!
4i::!:::!::J::: ')
IIII:D
1~
t.
"""
15
~
6
~
::J
c:
L SUFFIX
RI
CERAMIC PACKAGE
CASE 620
Co
TEST VOLTAGE VALUES
(Voltsl
OT...
Temper.... ,.
VIHmu
VILmin
VIHAmin
VILAm ..
VEE
-1.920
+25"1:
-0.880
-0.750
-1.510
-1.475
-5.2
+126°0
-0.630
-1.820
-1.255
-1.105
-1.000
-1.400
-5.2
-55"c
Col)
~
Q)
Ch .....ristic
Power Supply Drain Current
Input Current
Symbol
Ie
linH
Pin
Undor
T...
8
4.7.11
5.9
10.13
12
14
linL
4
Logic "1" Output Voltage
VOH
2
Logic "0" Output Voltage
Logic "1"
Threshold Voltage
VOL
VOHA
3
2
2
2
2
Logic "0"
Threshold Voltage
Switching Tim.
150n Lo..1
Propagation Delay
Ri.Time 120"10 80%1
Flil Tim. (20"'0811%1
MCl0679L Test Limits
~50C
Min
Max
Min
Ty.
M ...
Min
Max
Unit
-
-
-
58
72
270
225
-
-
mAde
0.5
-
-1.080
-1.920
-1.100
~
-
-0.850
-0.930
-1.655
-1.850
-0.950
-
2
2
2
2
-
~
t11+6+
'11-6t5+2+
'5_2_
6
6
2
2
-
-
'6+
6
'I>-
6
VOLA
-1.635
~
-
-
-
-
440
395
355
-
-
-
-
-0.750
-0.825
-1.820
-0.845
-1.620
-1.600
~
-
-
~Ade
~
VIH max
VIL min
VIHAmin
-
-
-
4.7.11
5.9
10.13
12
14
~Ade
-
-0.630
-1.545
Vde
4.5.7.9
Vde
-
-
Vde
-
-1.525
Vde
~
~
13
5.12
5.9
5
13
5
5
5,9
-
ns
-
-
-
-
~
-
~
-
1.0
~
1.1
1.1
-
-
-
-
4.5
4.5
5.5
5.5
3.5
3.5
-
j
4,7
4.7
4.7,9
4.7.9
4.7
4,7
-
-
-
4
-
-
-
+1.11 V
-
-5.2
TEST VOLTAGE APPLlEO TO PINS LISTEO BELOW:
+l25oC
+2SoC
-1.850
-
-
5
9
12
13
VILA max
-
-
VEE
(Veel
Gnd
8
1,16
8
1,16
~ ~
8
8
8
8
1.16
1.16
1.16
1.16
~
~
8
1.16
-
5
13
9
12
~
~
Pulse In
Pul. Out
-3.2 V
+2.0 V
11
11
5
5
11
6
6
2
2
8
1.16
11
6
-
-
-
6
j j
s::
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 .rie. hOI been de,
signed to meet the de specifications shown
in the test table, efter thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
C')
-0
9
o
g]
-----I
::~
terminated through a 10Q-0hm resistor to
(S)
~
6
-2.0 volts. Test procedures are shown only
for selected inputs and outputs. Other
inputs and outputs are tested in a similar
manner.
15
nO
II I FTff"" ./
....::::l
3'
c
Q.
AO 80 At 81 A2 82 P.3 83
51
--
c:
SiS
M
w
~
en
-~
....
o
g:
en
t- ..
,---M
p
.3
.• O A' •• A2.2 A3
C
r-"
r-- 52
."
A.3
r~9'
9"f
t'y
en
4
G_
MC10581
,----50
-~
A.'
A'O
.'0
A"
AD 80 A1 81.4.282 A3 83
~M
r--"
.,
AS
rli
AD 80 A 1 81 .4.2 82 ,A,3 83
Cin
~?
CD
..
A.
,"
F.2
F1J
~
MEeL 10,000 series
DUAl2·BIT
ADDER/SUBTRACTOR
MC10580
The MCl0580 is a high speed, low power ganeral·pur·
pose adder/subtractor. It is designed to be used in spacial
purpose adderslsubtractors or in high speed multiplier'
arrays. The Mel 0580 eIIn be used in any piece of equipment where these operations are necessary.
Inputs for each adder are Carry·in, operand A, and
operand B; outputs are Sum, Sum, and Carry·out. The
common Select inputs serve as a control line to invert A
for subtract, and a control line to invert B. The speed
is very fast, with Carry·in to Carry·out propagation delay
of 2.2 ns and Operand in to Sum or Carry·out propagation'
delay of 4.5 ns.
Po - 380 mW typ/pkl (No Loodl
n.
tpd(typ): el n to C out - 2.2
AO 10 SO - 4.5 n.
AO to Cout - 4.15 n.
POSITIVE LOGIC
NEGATIVE LOGIC
(11)1
(11)7
1& 131
1131.
UU 15
(13) g
:2
{e,
(101 •
(1016
J
(71
'9' 5
(8) ..
(8) ..
, . (2)
1
(115)11
(Hi! 11
(14)10
(14' 10
(16112
(18) 12
Positive Logic Only
A' = A (!) SelA .. A
0
(5)
13 ell
Both Po,ltive end Negative Logic:
S
SetA
=
Cjn (A'S' + A' 8') + Cin (A'S' + A'S')
Cout :: Cin A' + Cjn B' + A'S'
S'" S@S.IS" S0SoiS
Numb.,.. at Wid of termlnel' .re pin number. for L peeke,. (Case 620).
Numbe,.ln pe,.,th..11 denot.. pin number. for F package (C... 650).
POSTIVE LOGIC DIAGRAM - 1/2 Of Circuit Shown
TRUTH TABLE
FUNCTION
.00
....
eo
C,"
o------++----t---l
SUBTRACT
REVERse
SUeTA.4CT
FUNCTION SELECT TABLE
.... ....
""
"
"""
""
""
""
""
""
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
FunctIon
S - .4plul a
S·.4 Wllnul a
S· B,,"nuI.4
S • 0 minUI A m,nul a
S. . Gen .. al Information ..ction for peck aging.
3·352
""
""
""
""
L
L
L
L
L
L
L
L
"""
""
""
"
L
L
L
L
L
L
L
L
INPUTS
OUTPUTS
AO
80
Cin
so
so
C~,
L
L
L
L
L
L
L
L
"
L
L
L
"""
"
L
L
L
L
""
"
"
L
L
L
L
"
""
"
L
L
L
L
"
"""
""
""
L
L
L
L
""
""
L
L
L
L
""
L
L
""
L
L
"
"
""
L
L
"
"
L
L
"L
"L
"
L
"
L
"L
"
L
"
"
L
L
"
L
"L
"
L
"
L
"
"
L
""
"
L
L
L
"
"
L
L
"L
"
""
L
L
"
"
""
L
L
"
"
""
L
L
L
L
L
""
"
L
L
L
"
L
L
L
L
L
"
"
"
"
"
""
L
L
L
L
"L
L
"
"
"
""
L
L
L
L
"
"
""
"
L
L
L
L
""
"
L
L
L
"
""
L
"
"
L
L
L
,.
ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown In the test table,
-
after thermal equilibrium has been estab·
lished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
'pm is maintained. Outputs are terminated
mruug" a
luu-onm reSistor fO -L U VOltS.
L:::
Test procedures are shown for only one
SelA
,.'2--- '"
':====
input, or for one set of input conditions.
Other inputs are tested in the same manner.
51
Sels
51
8'
Cin
Cout
~
CtwI'Kt_iRic
Power Supply Dr.in Cur,..nt
Input Current
$v_
IE
'inH
w
W
(11
w
linL
VOH
Logic "I"
OutPUt Volu.g.
logic "0"
OutPUt Vol . . .
VOL
Logic "1"
Thrnhold Voltlgl
Logic "0"
ThrW'told Voltlgl
Switching Times
PrOlMPtion 0tI1-V
Opwnlnput
C_ry·in Input
Select Input
Ri_Tim.
(20tollOlfol
F.,Time
·lndiYidu.lly
~Iy
VOHA
VOLA
Pin
U-'
TOIl
8
4
5
6
1
9
10
11
12
All
2
3
15
2
3
15
2
3
15
2
3
15
Min
.Tat
TemptntuN
~"
+25"c
Ty.
Mo.
10
86
-
-
630
314
314
493
483
314
314
630
310
220
220
290
290
220
220
310
0.6
-1.080
-1.080
-1.080
-1.920
-1.920
-1.920
-0.880
-0.880
-0.880
-1.665
-1.666
-1.666
-
-
-1.100
-1.100
-1.100
-
15
15
15
3
15
15
15
-
'IS-
IS
-
-
-
-1.635
-1.635
-1.635
-
-
-
-
-
-
-
-
0.5
-0.930
-0.930
-0.930
-1.850
-1.850
-1.650
-
-0.950
-0.950
-0.950
-
1.0
-
-
-
-
-0.180
-0.180
-0.180
-1.620
-1.620
-1.620
-aGe
+25"c
+1210 c
-
220
290
290
220
220
-
-
0.3
-0.825 -0.830
-0.825 -0.630
-0.826. -0.630
-1.820 -1.645
-1.820 -1.645
-1.820 -1.645
-
-1.525
-1.525
-1.625
-
-
3.3
3.3
5.4
5.4
3.1
-
-
3.1
-
-
2.2
2.2
1.1
1.1
2.0
-0.880
-0.180
VILmin
-1.920
-1.850
-0.630
-1.820
VIHmu
00
o
CERAMIC PACKAGE
CASE 620
o
o
::J
~.
::J
V'HAmin
-1.266
-1.106
-1.000
r::
CD
a.
VILA.,."
-1.510
-1.415
-1.400
VEE
-52
-5.2
-5.2
(Veel
Unit
VIH m••
VILmin
mAde
-
-
.Ade
j
310
-
4.5
4.5
2.0
_L---
95
310
220
-1.600
-1.600
-1.600
5.4
5.4
j
-
-
4.5
4.5
U1
L SUFFIX
TEST VOLTAOE APPLlEO TO PINS LISTED BELOW,
+1211"e
Min
Mo.
-0.845
-0.845
-0.845
-
....o
TEST VOLT AOE VALUES
Vol ..
~,
96
15+15+
tl+15+
1.4+15+
l4+3+
t'7+16+
'9+15+
t15+
Vil min to pin under test.
~,.
MC10680L Tell Limits
-56"c
Min
Mo.
s:(")
.Ade
Vdc
t
T
Vde
t
Vde
t
n.
-
-
-
-
-
1~
-
VIHAmin
-
-
-
-
-
-
-
-
5
4
4
1.9
1.9
1.9
5.1.9
4.9
1.4
1.9
-
1.9
-
-
-
VEE
and
8
8
16
16
-
-
4.5.1.9
4.1.9
5.1.9
1.9
1.9
1.9
4.1.9
1.9
1.9
1.9
4.1.9
+1.11 V
-
VILA.mp
-
-
j
8
8
18
16
8
16
t
t
4
8
-
8
-
t
t
t
,
16
I
16
5
-
~
Pul_ln
PuI_Out
-3.2 V
+Z.OV
15
15
15
3
15
8
16
-
6
6
4
4
1
9
5
-
5
-
4
1
s:
(")
....
o
ELECTRICAL CHARACTERISTICS
II
13
9
10
8
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown In the test table,
after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 Itnear
'pm is maintained. Outputs are terminated
3
~
6
--I--+---a.j
L:::
SelA
S1
8ele
51
.,
1 5 - - AI
14-1 6 - - C,n
Other inputs are tested in the same manner.
::J
~2
~5
POW'er Supply Drein Current
I nput Current
'E
linH
w
W
CTI
~
linL
VOH
Logic: "I"
OulPUIVoIlIIIO
LOIIic:"O"
Output Voigg.
VOL
Logic "1"
Thr.oId VolUge
VOHA
Logic "0"
Thf"llhold
VOLA
Vol~
Switching Timll
Propegetion DeI~
ap.end I"Put
C_ry·in Input
5eIect Input
Ai_Time
12010_'
FoIIT_
-Indhfiduelty
12
8
9
10
II
13
14
15
16
Cout
Temper.~,.
~1
-a"C
+2Ii"C
+121i"c
All
3
6
7
3
6
7
3
6
7
3
6
7
Min
Typ
-
98
830
-
-
374
374
483
483
374
374
630
0,5
-LOBO
-LOBO
-LOBO
-1.920
-1.920
-1.920
-{I.880
-{I.sao
-{I,880
-1.855
-1.655
-1.655
0.5
-{I.930
-{I.930
-{I.930
-1.850
-1.850
-1.850
-1.100
-1.100
-1.100
-
-0.950
-0,950
-{I,950
-
-
-1.635
-1.635
-1.635
--
-
-
1.0
t9+3+
t10+3+
ta+3+
ta+7+
111+3+
113+3+
3
3
3
7
3
3
13+
3
-
3
-
13-
IPP.'.¥ VIL min 10 pin under~.
-
-
--
Min
-1.000
-1.400
-{I,630
-5.2
-5.2
-5.2
70
B6
-
370
220
220
290
-
-
-
290
220
220
370
-
-
-0.780
-{I.780
-0.780
-1.620
-1.620
-1.620
-
-
-
0.3
-{I.825
-{I,825
-{I,825
-1.820
-1.820
-1.820
Unit
VIH mu:
VILmin
VIHAmin
VILA m ••
VEE
IVeel
Gnd
95
370
220
220
mAde
-
-
-
-
-
12
12
4
4
JlAdc
290
290
-
220
220
370
-
JlAdc
-{I.630
-{I,630
-{I.630
-1.545
-1.545
-1.545
Vdc
~
Vde
11,13
11,13
8,11,13
8,11,13
11,13
11,13
+1.11 V
~
-1.600
-1.600
-1,600
-
-1.525
-1.525
-1.525
Vdc
4.5
4.5
5.4
5.4
-
ns
2.2
2.2
-
4.5
4.5
2.0
3.3
3,3
5.4
5.4
3.7
-
~~1__ ~.O
3,7
-
-
-
-
-
8,11,13
11,13
8,9,11,13
11,13
9,11,13
11,13
-
-
i
~
11,13
11,13
11,13
9,11,13
-
6,13
8,11
-
11,13
- -~
-
-
Vdc
-
1.1
-1.820
-O.sao
-0,780
c.
VEE
, M ...
-{I.845
-{I,845
-{I.845
j
VILAmu
-1.510
-1.475
VILmin
+1211"C
Mo.
-
-
-1.920
-1.850
VIHAmin
-1.255
-1.106
VIHmu
TEST VOLTAGE APPLIED TO PINS LISTED ULOW,
+2Ii"c
Mo.
-
Cb
.T. .
Min
-
::J
c:
Vol ..
MC10610F T_ Limits
-W'c
~,
TEST VOLTAGE VALUES
'---
lo-
o
C"l
Test procedures are shown for only one
input, or for one set of input conditions.
Ctw. .illlic
(J'I
0)
o
through a l00-ohm resistor to -2.0 volts
PI.
U_
T. .
F SUFFIX
CERAMIC PACKAGE
CASE 650
~~
-
-
-
-
-
-
-
-
-
9
9
8
-
-
9
10
8
8
II
13
9
9
II
12
12
-
~
-
12
-
~
12
8
-
Pu"ln
-
-
-
8
8
PuI_Out
3
3
3
7
3
J
i
12
~
4
4
~
4
~
,
4
I
4
-3,2 V
+2.0 V
12
4
:MC10580 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l2SoC
Vee, : VCC2 -' +2.0 Vdc
V out
Coax
Coax
9
+-......--.I--t SelA
+ .....+--'~ SelB
5
AO
6
80
4
~--:"'15
60
C out
Cin
-~-~
3
TP in
14
Pulse Generator
11+------1-.
10+------1-.
12-i---aot
50-ohm termination to ground to
cated In each scope channel input.
All input and output cables to the
scope .re equal lengths of 50-ohm
co . .:ial cable. Wire length should
be < 1/4 inch from TP in to input
pin end T~out to
pin.
outPut
V out I, 2:1 att.,uated.
13
L----fi-1J
01
Unu_d outputl
connected to •
-l
100~hm r ..i,tor
to ground.
~F
VEE'" -3.2 Vdc
PROPAGATION DELAY
r---~-------+1.11
v
'-------+0.31 V
TP out
TP out
3-355
MECL 10,000 series
4-BIT ARITHMETIC lOGIC
UNIT/FUNCTION GENERATOR
MC10581
The MC10681 is a high-speed arithmetic logic unit
capable of performing 16 logic operations and 16 arithmetic operations on two four-bit words. Full internal carry
is incorporated. for ripple through operation.
Arithmetic operations are selected by applying the
appropriate binary word to the select inputs (SO through
S31 as indicated in the tables of arithmetic/logic functions.
Group carry propagate (PGI and carry generate (GGI are
provided to allow fast addition of very long words using a
second order look ahead. The internal carry is enabled by
applying a low level voltage to the mode control input (MI.
When used with the MC10579, full-carry look-ahead, as
a second order look ahead block, the MC10581 provides
high speed arithmetic operations on very long words.
POSITIVE LOGIC
NEGATIVE LOGIC
(19) 13
(19) 13
(21) 15
(21) 15
(23) 17
(23) 17
(20) 14
(20) 14
50
(3)
21
(2)
20
(8)
(24) 18
(11
19
(22)
16
(17)
11
F1
3
(9)
F2
7
(13)
F3
6
(12)
4
(10)
8
(14)
(16) 10
(15)
9
(4)
22
(6)
23
PG
(3)
21
(2)
20
51
52
53
2
(24) 18
(1)
19
(22)
16
(17) 11
(16) 10
(16)
(11)
9
(4)
22
(5)
23
(8)
3
(9)
7
(13)
6
(12)
4
(10)
8
(14)
5
(11)
Numben at end of terminals are pin numbers for L package (Case 620)
Numbers in parenthesis denotes pin numbers for F package (Case 650)
Po :: 600 mW typ/pkg (No Load)
tpd (typ):
Al to PG :=. 5.0 ns
A 1 to GG = 4.5 ns
Al to C n +4 = 5.0 ns
Al to F =6.5n5
en to C n +4 = 3.1 ns
POSITIVE LOGIC
Function Select
53
52
51
Arithmetic Operation
Mi,low
i,tow
F
F
50
F
F ~
H
F "
H
H
H
H
F
L
H
H
H
H
Ii
H
F
L
F" A
It
F
A ..
=
•
F "A" 8
L
F - Logical "0"
Anthmetlc Operation
M is High
M IS Lowen of LSB must be HIgh
F
Select
S1
SO
F
F'A,
F - A minus 1
A plus (A. iiI
F'~
A plus (A. Bt
F -
(A" SI plutO
A.
B
F -
H
,;:-;-s
F •
A plus B
F ~ AiDB
F
A plus (A .. 8)
FA.
F
(A"
BI
plus 0
F • A minus B minus 1
F
A plul (A"
F .
A
H
F
A@B
H
F " A • B
~
H
mmus 1 (twO's complement)
F ." A e B
F' (A e BI minUS 1
F
A mInus 1
+ B
F ." B
Ell
F '. (A e SI mInus 1
B
H
F • (A .. HI plus (A • BJ
F
H
F
<
~
3-356
~
ih
81
A times 2
F
fA. BI minus 1
(A • BI olus (A + Bl
A plus B
F - A plus (A. BI
F ~ (A • SI mInus 1
F
A mInus B mInus 1
F ~ (A .51 plus A
F
mInus 1 (two's complement'
8
F ~ (A + 51 plus 0
A + B
F - (A + BI plus 0
F - A
See General Information .. ction for peckaging.nd maximum ratingl.
A plus (A •
F
F ' (A .51 plus (A + BI
LogIcal "1'"
F " A +
F
F
F . A plus (A
B
F
F"'Aes
F'" A
S2
F ' (A .. II plus fA • 81
•
B
F", A0 B
F
Function
S3
A tlme52
.i.i
H
H
F
F
Logical "1"
H
H
H
en
LogiC Functions
F'" A plul 0
A
A .. ii
A+B
F-A".a
H
H
~
F
H
NEGATIVE LOGIC
Logic Fundion.
Mi, Htgh C .. D.C.
F . A plus 0
MC10581
(continued)
,S3
S2
POSITIVE LOGIC DIAGRAM
SI
so
BO
0--
~
~
f---J-L/
---D
~
FO
-L
~
AO
Bl
0--
~
~
,~/
~
0--
~
Vi
~
£>t
~
F2
~
~
,
0--
"
~
A2
B3
Fl
-L
AI
B2
~
.--"
F3
,~
~§P
A3
,/
M
3-357
ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECL 10,000
series circuit has been designed to meet
the de specifications shown in the test
table. after thennal equilibrium has been
mtablished.
The circuit is in 8 test
(")
~
socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear {pm is maintained. Outputs are
terminated through a 100-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input, or for one set of input conditions. Other inputs tested in the same
manner.
~
0
C11
CO
~
8
L SUFFIX
CERAMIC PACKAGE
CASE 623
:::l
~.
:::l
c:
CD
a.
TEST VOLTAGE VALUES
IVai..,
OT...
T .... perMu ...
Pin
Undo<
a.eracteriltic
W
W
POMr Supply Drein Currant
Iinpu. Cuneo.
Symbol
TOOl
IE
12
linH
9
10
11
13
U1
(Xl
"
15
16
17
18
19
20
21
22
23
Input Leakage Current
I
linL
I
9
10
11
13
14
15
16
17
18
19
20
21
22
23
-
0.5
Ma.
~.780
-1.850
-1.105
. +126"1:
~.630
-1.820
-1.000
-1.476
-1.400
VIH mill
180
145
-
245
220
245
200
160
245
220
245
200
265
265
220
265
220
2.5
2.5
220
290
200
mAde
420
375
420
340
-
/JAde
9
10
11
13
14
15
16
17
18
19
20
21
22
23
-
",Adc
-
450
450
375
460
375
420
420
376
496
340
-
-
-
0.5
TV.
-
-
220
265
220
245
245
220
290
200
-
-
-
--
-
-
-1.080 -0.8BO
-0.930
-1.920 -1.855
-1.850
-1.100
-0.950
-1.836
VOLA
-.lrest ell iDpUt-GloltpUt.CGnIbift.8tioDl.-:coa:l". to.function T.Ibla.
·-For ttw'fthoklle¥iM _ . apply thrnhold input IIwI to only one input pin • • time.
265
265
-
-
~.780
-1.620
-1.8110
-
-
0.3
-
-
-
-
~.825
I
I
I
VEE
-5.2
I
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS BELOW,
Unit
VOL
Low Thl'fthofd Volt. .
-1.510
Mao
VOH
.
VILA....,.
-1.266
Min
High Output Voltage
VOHA
VIHA min
-1.920
M..
Min
Low Output Voltage
High Threshold Voltage
Vil min
-0.880
MCl0511L T_ Limit.
+25 o C
+126"1:
~6"1:
Min
VIH,.,..
-&15"1:
+25o C
-
~.630
Vdc
-1B20 -1.545
Vdc
~.845
Vdc
-1.625
'Vdc
1
-
9
10
11
13
IVee'
Gild
VEE
VILA m ••
VIHA min
VILmin
I
1,24
12
1
-
1
-
T
12
I
1,24
I
-
I
-
I
12
I
1.24
"
15
16
17
18
19
20
21
22
23
.
-
....
-
.....
.
12
1,24
12
1,24
12
1,24
12
1,24 ..
' .'~~
EL.ECTRICAL CHARACTERISTICS
E.th full temporeture r..... MECL 10.000
_ies circuit has been dlligned to mftt the
dc ~pecificetions shown in the t-'t toble.
efter thermol equilibrium he, been astat>lished. The circuit is in 8 test .:Jeket or
mounted on 8 printed circuit board and
transverse air flow greater than 500 1inear
fpm is maintained. Outputs are terminated
t"'ough a HIO·ohm resistor to -2.0 volts.
~
....
~
0
U1
00
....
------
~
8
F SUFFIX
::J
CERAMIC PACKAGE
CASE 652
!:!.
::J
c:
~
TEST VOLTAGE VALUES
IVaitsl
@Test
T.... per.tur.
Ch.,.....istic
Po.,..., Supply Drain Current
W
W
II nput Current
Symbol
Pin
Under
T.,.
IE
18
160
linH
15
16
17
19
20
21
22
23
24
1
2
3
4
5
420
375
420
U1
CO
Input Leakage Current
I
linL
I
15
16
17
19
20
21
22
-5SoC
Min
MIX
MC10681F Test Limit.
+25"1:
+125oC
Min
Typ
MIX
Min
M ••
116
340
450
450
375
450
375
420
420
375
495
340
145
245
220
245
200
265
265
220
265
220
245
245
220
290
200
0.5
0.5
160
245
220
245
200
265
265
220
265
220
245
245
220
290
200
0.3
VIHAmin
-1.255
-1.510
-0.780
-1.850
+ 12SoC
-0.630
-1.820
-1.IOS
-1.000
-1.475
-1.400
I
mAde
",Adc
VILmin
VIHm••
15
16
17
19
I
",Adc
VOH
-1.080 -0.880 -0.930
-0.780
-0.825
-0.630
Vdc
-1.920
-1.620
Vdc
VOHA
-1.100
-1.820 -1.545
-0.845
-1.525
VOLA
·Test aUlnput-output combinatIOns eccordtng to Function Table.
··For threshold level test, apply threshold input level to only one input pin at a time.
1
Vee
-5.2
-5.2
-5.2
VILA
I
m.. I
I
I
I
I Vee)
VeE
18
I
6.7
18
I
Gnd
6.7
21
22
23
24
VOL
-1.600
I
I
20
15
16
17
19
20
21
22
24
1
2
3
4
5
-0.950
VIHA min
I
23
-1.635
I
TEST VOLTAGE APPLIED TO PINS BELOW:
Unit
24
1
2
3
4
5
-1.850
me.
-1.920
23
-1.655
VILA
-0.880
High Output Voltage
High Threshold Voltage
VILmin
_55°C
+25 o C
Low Output Voltage
Low Threshold Voltage
VIHma.
18
I
I
Vdc
Vdc
-1
1
1
I
1
1
18
6.7
I
6.7
18
1
6.7
18
1
6.7
18
1
6.7
MC10581
(continued)
ELECTRICAL CHARACTERISTICS (CONT'I
AC Switching CharaCleriSlies
+25o C
~s"C·
Min
MIl.
Min
Typ
M..
Min
MIl.
Unit
1.B
1.0
2.0
1.1
2.0
1.5
7.6
3.5
B.l
5.0
S3, C n
S3,C n
1.9
0.9
B.l
3.0
2.0
1.0
6.0
2.0
-
2.B
1.3
10.3
5.2
3.0
1.5
6.5
4.0
B.O
3.0
10
5.0
1.6
0.9
2.0
1.3
1.9
0.9
ns
ns
1.9
1.3
6.0
2.0
6.0
3.0
7.5
3.5
53, C n
S3,C n
7.6
3.5
B.l
5.0
Fl
FI
AI, Bl
AI, Bl
2.7
1.3
3.0
1.5
6.5
3.0
PG
A3, B3
A3 B3
1.9
1.0
10.2
5.2
B.l
5.1
2.0
1.1
Input
Output
Propagation Delay
Rise Time, Fall Time
t++. t-t+, t-
Propagation Delay
AiseT.rne Fall Tmle
tt+, t-tt t-
Bl
Bl
Bl
Bl
PG
PG
GG
GG
Propagation Delay
Rise Time, Fall TIrr'le
f+-, t-+
Bl
Bl
Cn +4
C n ?4
Propagation Delay
Rise TIlTle, Fall Time
It+, t+t+, t-
M
M
Fl
FI
Propagation Delay
Rise Time, Fall Time
t+-, t-+
f+, l-
51
SI
Propagation Delay
t-+,lt-
51
SI
P~
tt,
Rise Tmle, Fall Time
t-
f+, l-
+l25°C·
Conditions t
SO,S3
50,53
Symbol
Characteristic
B.O
5.0
ns
n.
ns
ns
2.B
1.3
B.l
3.0
10.2
5.2
10
5.0
2.6
1.3
10.2
5.2
ns
ns
6.0
3.0
8.0
5.0
1.8
1.0
8.1
5.1
ns
ns
ns
ns
51
51
C n +4
Cn+4
A3,83
A3,83
1.9
1.0
9.1
5.1
2.0
1.1
6.0
3.0
9.0
5.0
1.8
1.0
9.1
5.1
ns
n.
51
SI
GG
GG
A3, B3
A3,B3
1.7
0.8
9.2
6.2
2.0
0.8
6.0
3.0
9.0
6.0
1.7
0.8
9.1
6.2
ns
ns
Cn
Cn
C n +4
C n +4
AO,A I ,A2,A3
AO,A I ,A2,A3
5.1
3.1
Cn
Fl
I
I
3.1
2.0
4.5
4.5
3.0
5.1
3.1
7.1
7. I
5.2
Al
I
F(
2.9
2.9
1.3
5.0
3.0
7.0
7.0
5.0
10
10
5.0
0.9
0.3
2.0
2.0
1.3
t++, Ht-+, t-t+, t-
7.1
7. I
5.2
10.1
10.1
5.2
1.1
1.0
2.0
2.0
1.5
3.0
3.0
1.5
ns
ns
t++. t+t-+, t-t+, t-
1.0
0.9
1.9
1.9
1.3
2.8
2.8
1.3
Propagation Oelay
Rise Time, Fall Time
t++, t-t+, t-
Al
Al
6.6
3.5
2.0
1.1
1.8
1.0
Al
Al
1.9
1.3
7.1
5.2
2.0
1.5
5.0
2.0
4,5
4.0
6.5
3,5
t++, t-t+, t-
50,53
50,53
AO,A2,A3,C n
AO,A2,A3,C n
1.8
0.9
Propagation Delay
Rise Time, Fall Time
PG
PG
GG
GG
7.0
5.0
2.0
1,3
10.2
10.2
5.2
6.5
3.6
7.1
5.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t+-, t-+
t+, t-
Al
Al
Cn+4
C n+4
AO,A2,A3,C n
AO,A2,A3,C n
2.0
0.9
7. I
3.0
2.0.
1.0
5.0
2.0
7.0
3.0
1.9
0.9
7. I
3.1
ns
ns
Propagation Delay
Rise Time, F311 Time
t++, t-+
Bl
Bl
Fl
FI
53, C n
53,C n
2.9
1.3
11.1
5.2
3.0
1.5
8.0
3.5
11
5.0
2.7
1.3
11.2
5.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t+-, t-+
Propagation Delay
Rise Time, Fall Time
f+-, t-+
t+,l-
'+, l-
Propagation Delay
Rise Time, Fall Time
1++, t--
t+.t-
Propagation Oelay
Rise Time, FaU Time
Propagation Oelay
Rise Time, Fall Time
t+, t-
AO
I-
tLogic high level (+1.11 Vdd applied to pins listed. All other
input pins are left floating or tied to +0.31 Vdc.
VCCI
=
VCC2
=
+2.0 Vdc, VEE
=
6.5
6.5
3.0
-For L Suffix only.
-3,2 Vdc
3·360
ns
I
T
n.
ns
'MC10581
(continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25"<:
VCCl - ""CC2
+20 \,Ide
V oul
PROPAGATION DELAY
50
'------+0.31 V
TP,ro
'roput
Input Pul,e
2 ! 0.2 ns
(20 to 80%)
t+ = t- =
TP out
50-ohm termination 10 ground locat.cj
in lI..:h IeOp. chenne' input.
All input a"d output cabl" 10 the scope
ar. ~u.ll.ngths
at 50-ohm c08",ial clbla
Wire length should be
< 1/4 inch "om
TP in to input pin and TP out to output
pin. V out itl2:1 attenuated.
UnuHd outpuuconn..:ted to II 100 ohm
retl.tor to grou ... d.
3-361
MECL 10,000 series
HIGH SPEED TRIPLE
LINE RECEIVER
MC10616
POSITIVE lOGIC
The MC10616 is • high speed triple different..
amplifier designed for use in sensing differential IignM.
over long lines. The base bias supply (Vaal il ...available to make the device useful as a Schmitt
NEGATIVE lOGIC
trigger. or
in
other
appl ications where a stable
reference voltage is necessary.
(S)4~2
(9) 5
ActivB currant sources provide the MC10616 with
(6)
3 (7)
(S)4~2
(6)
(9)
(7)
5
3
(13)9~6 (10)
(13)9~6
(10)
(14)10
(14)107
(11)
7 (11)
(16)12~14(2)
(1)13
(16)12~14 (2)
15(3)
15 (3)
(1) 13
L - 11 (15)
excellent common mode noise rejection. If any ampli·
fier in a package is not used, one input of that amplifier
must be connected to Vas to prevent upsetting the
current source bias network.
Complementary outputs are provided to allow driv·
ing twisted pair lines, to enable cascading of several
amplifiers in a chain, or simply to provide complement
outputs of the input logic function.
L - l 1 (15)
Vaa
Vaa
Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotes pin numbers for F package (Case 650),
I Case I
I 620
I
650
I
I
VCC1
Pin 1
Pin 5
I VCC2 I
I
I
Pin 16
Pin 4
VEE
I
PO'" 100 mW typ/pkg (No LOad)
tpd '" 1.8 ns typ (Single ended)
'" 1.5 ns typ (Differential)
I Pin B I
I Pin 12 I
CIRCUIT SCHEMATIC
(6) 2
(7) 3
7 (111
(10)6
14 (21
vcel
VCC2
15 (3)
16 (4)
1 (5)
(g) 5
(S) 4
(13) 9
(14) 10
(1) 13
See General I nformation section for packaging.
3-362
(16112
8
VEE
(12)
ELECTRICAL CHARACTERISTICS
...3:o
Each lull temperatura range MECL·l0,OOO
_i •.circuit has been designed to meet the
de specifications shown in the test table.
mounted on a printed circuit board and
::=:tt=~
transverse air flow greater than 500 linear
fpm is maintained. Outputs ara terminated
through a 101k>hm resistor to -2.0 volts.
T.t procedures are shown only for selact-
9:=:tt=6
10
1
12~14
ed inputs and outputs. Other inputs and
13~'5
outputs are tested in a similar manner
...~
-
attar thermal equilibrium has baan established. The circuit is in a test socket or
~"
VBB
0)
L SUFFIX
8::J
CERAMIC PACKAGE
CASE 620
~.
::J
C
en
a.
TEST VOLT AGE VALUES
IV....I
.T...
Tem,.rature
w
W
en
w
Ch ___ ristic
Power Supply Or.in Current
Input Current
5¥mbol
'E
linH
'CBO
Hith Output Volt. .
Low Output Voltege
VOH
VOL
High Threshold Volt.
VOHA
Low Threshold Voll.
VOLA
R.ferenc::eVoltage
VIB
Pi"
U_,
T...
8
4
4
9
2
3
2
3
2
3
2
3
11
F.IITime
.2&"c
~.780
.1Z5"c
~.830
."1.820
-1._
-1.820
+25o C
Min
M..
-
28
195
1.5
1.5
-LOBO
-LOBO
-1.820
-1.920
-1.100
-1.100
-1.440
Min
-
M ••
20
25
115
1.0
1.0
~.880
~.930
-
-0.880
-1.8&1i
-1.8&1i
~.930
-
-1.850
-
~.950
~.850
-1.850
-1.835
-1.835
-1.320
-1350
-
.-
1.0
1.8'
-
Min
-
M ••
Unit
28
115
1.0
1.0
mAde
VIHm. .
VILmin
-
9.12
4.12
-
4
9.12
9.12
4
9,12
-
9,12
-
-
9.12
4
-
4
-
~Ade
~.780
~.625
~.630
-1.620
-1.620
-1.820
-1.820
-1.545
-1.545
Vdc
Vdc
-
Vdc
Vdc
9.12
-
Vdc
Vdc
-
9.12
9,12
Vdc
-
-
-1.240
2.5
-
-1.526
-1.525
-1.120
-
,!lAde
Vdc
Vdc
-
VILA .....
9,12
~.630
-1.BOO
-1.BOO
-1230
VIHAmin
4
~Ade
~.825
~.845
~.845
-1.510
-1.475
-1.400
4.9.12
~.780
-
ViLA .....
V. .
F..."
Pi"
11
VEE
-5.2
~
~
TEST VOLTAGE APPLIED TO PINS BELOW,
.1Z5"c
Ty.
V'HAmin
-1.2&1i
-1.106
-1.000
4
4
-
-
--
4
4
-
V. .
VEE
5.10.13
5.10.13
5.10.13
5.10.13
8
8
1,4
5.10.13
5.10.13
5.10.13
5.10.13
5.10.13
5.10.13
5.10.13
5.10.13
5.10.13
B.8
8
8
I
8
8
8
8
B
8
-3.2
14+2+
.... 2'4+3.... 3+
Ri.Time
120% to 80%)
VILmin
-0.880
Mel.1IL T . . L1_
-&Ii"c
Switching Til'Ml
ISCHhmLoodl
Propaptlon Oeley
VtHm ••
-5II"c
'2+
'3.
'2_
2
2
3
3
2
3
2
3
120%'080%1
'3D• ..., i, 1.5 n. when inputs .... driven diff.rentillUy
Delay i, 1.8 n. when inpuh •• driven lingle ended
-
-
-
-
j •~ j
1.5
-
-
-
n.
j
-
-
-
-
-
-
Pul.ln
Pul.Out
4
2
2
3
3
2
3
2
3
j
5.10.13
IVecl
Ond •
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1,16
1.16
1.16
Vdc
+2.0
Vdc
8
1.16
j j j
ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECL 10.000
series circuit has been designed to meet the
de specifications shown in the test table,
(')
...A
o0)
...
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
~
8~6
mounted on a printed circuit board and
9-~7
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 1OQ..ohm resistor to -2.0 volts.
Test procedures are shown only for selected inputs and outputs. Other inputs and
outputs are tested in a similar manner
0)
~FSUFFIX
13~10
14~11
16~2
8:::l
~.
CERAMIC PACKAGE
CASE 650
1-~-3
L ___ 15
:::l
c:
(1)
Co
VBe
TEST VOL TAOE VALUES
I
IV....'
.T...
T....per..u,.
eN
W
~
So-
T...
Power SupplV Drlin Current
'E
12
a
a
13
6
1
Input Current
linH
Icao
Htgh Output Volt. .
low Output Voltage
VOH
VOL
High Thrnhold Volt.
VOHA
low Threshold Voltage
VOLA
Reference Volt. .
Va8
6
1
6
1
6
,
15
V'lillin
V'HAIR.
VILA . . .
-SS"c
~.811)
.aoc
.laoc
~.180
-1.820
-1._
-1.820
-1.2M
-1.IOS
-1.110
-1.4111
~.630
Me,GS,., T. . limits
Pin
-SS"c
u....,
Characteristic
VIHIll. .
Min
-
-1.0B0
-1.0B0
-1.920
-1.920
-1.100
-1.100
-
-'.440
Min
Typ
M..
Min
M..
Unit
VIHm••
Vil min
28
195
1.5
1.5
-
20
25
lIS
1.0
10
-
28
115
1.0
'.0
mAde.
-
-
~Adc
8
-
8. '3.'6
'3.16
13.16
8.'3
~.825
~.630
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
8
13.'6
13.16
8
13.16
8
8
13.16
-
13.16
8
~.930
-
-
~.180
~.880
~.930
~.180
~.825
~.630
-1.855
-1.655
-1.850
-1.850
-1.620
-1.620
-1.820
-1.820
-1.545
-1.545
-
~.850
~.950
-1.635
-1.635
-1.320
-
-
-1.350
-
~.845
~.845
-
-1.600
-1.600
-
-1.230
-1.240
-1.525
-1.525
-1.120
-
.-
Pin
15
",Adc
",Adc
13.16
-
-
13.16
13.'6
-
-
VIHA min
-
-
8
VILAma
-.
-
-
8
8
-
-
-
Pul.ln
Pul_Out
V.
'.8.'4
1.8.'4
'.8.'4
'.8.'4
'.8.'4
'.8.'4
'.8.'4
'.8.'4
1.8.'4
1.8.'4
'.8.'4
19.'4
1.8.'4
Switching Times
~5O-ohm
Pr~ion
LoMI)
Oelav
te+6+
ta~-
lfI+1lfI-1+
Ri.Time
(20% to 80%1
'6+
Fell Time
(20% to 80%1
'6-
'1+
'1_
6
6
1
1
6
1
6
1
D.-y i, 1.6 "' wtwn input, •• driven d;tferenttlilly
D...., i, 1.8 ,.. when inpuh •• driven lint" ended
-
-
-
10
-
-
j
1.8'
+
1.5
~
2.5
j
-
~
~
-5.2
IVCCI
Mo.
~.880
-'.400
VEE
TEST VOL TIIOE .... LIEO TO PINS BELOW,
.,aoc
"25Q C
-',-
V.
F,om
n.
-
-
-
j
-
-
8
6
6
j
1
6
1
6
1.8.'4
VEE
,2
'2
8.'2
'2.'3
t2
0"'"
4.1
4.&
4.&
4.5
,2
12
8
4.11
4.11
4.&
4.11
4.1
4.11
4.11
4.1
4.11
-3.2
Vde
,2
+2.0
Vdc
4.6
'2
,2
,2
12
12
7
7
j j j
,- MC10616 (continued)
I
.....
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
veel : VCC2
Vout
+2.0 Vdc
V out
Coa ..
Input
Pulse Generator
Input pulse
t+
=
t-
=
1.5 ±. 0.2 ns
(20 to 80%)
-n
I
I
I
I
I
One input from each gate must
be tied to
Ves during testing.
I
L_-
JO.' ~F
I
-:, ~F
Unused outputs connected to
a 100-ohm resistor to ground.
V:E '" -3.2 Vdc
PROPAGATION DELAY
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coax ial cable. Wire length should
be
1/4 inch from TPln to input
<
pin and TP out to output pin. V out
Is 2:1 attenuated.
3-365
MECL 10,000 series
HIGH SPEED DUAL TYPE D
MASTER-SLAVE
FLIP-FLOP
MC10631
The MC 10631 is a dual master-slave type D
flip-flop. Asynchronous inputs Set (S) and Aeset
(A) override the Clock (CC) and Clock Enable
(eE) inputs. Each flip-flop may be clocked separately by hold ing the common clock in the low
state and using the enable inputs for the clack.ing
function. If the common clock is to be u~ to
clock the flip-flop, the Clock Enable inputs must
be in the low state. I n this case, the enai>le
inputs perform the function of controlling the
common clock.
The output states of the flip-flop change on
the positive transition of the clock. A chailge
in the information present at the data (0) input
will not affect the output information at any
other time due to master slave construction ..
Input pulldown resistors eliminate the nl!ed
to tie unused inputs to VEE. Output rise and fall
times have been optimized to provide relaxatjon
of system design and layout criteria.
R.s TRUTH TABLE
A
L
L
L
On+1
an
H
H
H
L
L
H
H
N.D.
S
N.D. '" Not Defined
CLOCKEO TRUTH TABLE
H
0
- - - - - - - - - - j
Writ. C > - - - - - - - - - - j
and
Data I nput Buffer
3-370
INPUT
OUTPUT
Din
°out
CE
WE
Write "0"
L
L
L
Write "1"
L
L
H
L
Read
L
H
'I>
Q
Disabled
H
'I>
'I>
L
~ =
Don't Care.
L
3:
n
3:
o
ELECTRICAL CHARACTERISTics
...
...
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal
equilibrium has been established. The cir·
cuit is in a test socket or mounted on a
printed circui.t board and transverse air flow
greater than 500 linear 'pm is maintained.
~CE2
3
.;..
CE1
AO
o
-..
~A1
3:
n
A2
Outputs are tenn inated through. So-ohm
resistor to -2.0 volts. Test procedures are
shown for only selected inputs and outputs.
Other inputs and outputs tested in the
same manner.
~A3
10 A4
D out
115
...s:
...
o
A5
13
Din
WE
it
TEST VOL TAGE VALUES
12
n-O
(Volts)
@Test
VILmin VIHAmin VILAmax
VEE
_30 oe
-0.890
-1.890
-1.500
-5.2
+2S"c
-0.810
-1.850
-1.105
-1.475
-5.2
+SSoC
-0.700
-1.825
-1.035
-1.440
-5.2
Tamperature
VIHmax
-1.205
::J
~,
::J
~
Q.
MCM10140, MCM10142, MCM10148 Test Limi"
Pin.J
W
W
.....
r
r
Und.r
Test
Characteristtc
Power Supply Drain Current
'E
linH
8
6
4
linL
6
Logic "1" Output Voltage
VOH
Logic "0" Output Voltage
VOL
Inpu. Cunen'
Logic "'" Threshold Voltage
Logic "0" Threshold Voltage
SWitching Times
Access Times
Chip Enable
1
-30G C
Min
,-
1 - ..1
Min
-
-
1
I
..1
Typ
Max
80
100
mAdc
265
50
",Adc
Min
I
VOLTAGE APPLIEO TO PINS LISTED BELOW,
+8S0C
+2SOC
Ma.
Max
Unit
•
VIHm•• ! VILmin !VIHAmin!V,LAmu ! VEE
6
-
-
15
-1.060
. -0.890
-0.960
-0.810
-0.890
-0.700
Vdc
14
I
15
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
14
VOHA
15
-1.090
-
-1.980
.1
VOLA
15
-
-1.655
0.5
-0.910
-1.630
Vdc
-1.595
6
-
I
.1
3,14
3,14
Vdc
Pul. In Pulse Out
4
15
4
'5
2
15
15
15
15
tCE-D+
tCe+D-
15
15
12
12
Address Inputs
tA+D+
tA+DtA_D+
tA-D-
15
15
15
15
10",15""
10",15""
10" ,15""
10" ,15""
Write Pulse Width
'WWE
12
10
13
Chip Enable Pulse Width
'WICEI
13
13
Write Strobe Mode Times Setup
Data
Chip Enable
Address
Hold
Data
Chip Enable
Address
"MCM10142
""MCM10140, MCM10148
-
0
12
12
tsetup(OtW-)
12
tsetup(CE-W-)
12
4
12
tsetup(AtW-)
12
4
12
thold(W+D±1
15
12
15
tholdIW+CE+)
4
tholdIW+A:t)
o
12
12
IIVCCI
Gnd
8
16
t
..1
8
1,16
8
8
8
1,16
-3,2 V
8
16
1,16
1,16
+2,0 V
1,16
MCM10140/MCM10148 (continued)
CHIP ENABLE ACCESS TIME
Dout
ADDRESS ACCESS TIME
Address
D out
WRITE STROBE MODE
Address
th01d(W+O±1
14---. . thold(W+CE+)
thold(W+A±)~
°aut
3-372
SWITCHING TIME TEST CIRCUIT., 25°C
r"
:
VCCI = VCC2= +2.0Vdc
,- d!
Coax
25 "F
--
-
r...
--
I
I
I
I
I
I
I
41
2
3
6
7
Pu I. Generator
Input Pulse
t+
= t-
., 2.0
± 0.2
120% to 80%)
"I
I
I
I
9
10
I
13
I
I
I
I
L
51
CEI
AO
AI
A2
CE2
A3
A4
I
D out
I
15
I
A5
I
Din
WE
I
112
I
I
I
-Q~
I
01"F
- 3 :Vdc
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope ar. equal lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TPin to input
pin and TP out to output pin.
<
3-373
Coe",
01 "F
I
Input
V out
MECL 10,000 series
8 x 2 MULTIPORT REGISTER
FILE (RAM)
MCM10143
8 x 2 MULTlPORT REGISTER FILE
(RAM)
The MC10143 isan 8 word by 2 bit multi port register file (RAM)
capable of reading two locations and writing one location simultaneously. Two sets of eight latches are used for data storage in this
LSI circuit.
L SUFFIX
CERAMIC PACKAGE
CASE 623
WRITE
The word to be written is selected by addresses AO-A2. Each bit
of the word has a separate write enable to allow more flexibility in
system design. A write occurs on the positive transition of the clock.
Data is enabled by having the write enables at a low level when the
clock makes the transition. To inhibit a bit from being written, the
bit enable must be at a high level when the clock goes low and not
change until the clock goes high. Operation of the clock and the bit
enables can be reversed. While the clock is Iowa positive transition of
the bit enable will write that bit into the address selected by AO-A2.
PIN ASSIGNMENT
READ
When the clock is high any two words may be read out simulta·
neously, as selected by addresses BO-B2 and Co-C2, including the
word written during the preceding half clock cycle. When the clock
goes low the addressed data is stored in the slaves. Level changes on
the read address lines have no effect on the output until the clock
again goes high. Read out is accomplished at any time by enabling
output gates (Bo-B,), (CO-C,).
3
4
21
5
20
6
19
18
tpd:
Clock to Data out = 5 ns (typ)
(Read Selected)
Address to Data out = 10 ns (typ)
(Clock High)
Read Enable to Data out = 2.8 ns (typ)
(Clock high, Addresses present)
Po = 610 mW/pkg (typ no load)
8
17
9
16
10
15
11
1.
12
13
Vcco" Pin 1
Vee1 = Pin 23
Vee - Pin 24
VEE
See General Information taetion for packaging.
3-374
= Pin
12
MCM 10143 (conti nued)
BLOCK DIAGRAM
4
REB
BO
B1
B2
OB1
6
5
aBo
WEo
DO
Clock
9
10
19
AO
A1
A2
14
15
13
WE1
01
8
11
Co
C1
C2
17
16
18
OC1
OCo
REC
20
3-375
MCM1 0143 (continued)
ELECTRICAL CHARACTERISTICS
80 REB
B,
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal
equilibrium has been established. The cir-
OB,
B2
WEo
'0
cuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs are terminated through a 5O-ohm
resistor to -2.0 volts. Test procedures are
Address
DO
080
3
AO
'5
Line,
Data
Output
A,
13
A2
OC,
22
Lines
shown only for selected inputs and outTEST VOLTAGE VALUES
puts. Other inputs and outputs are tested
in a similar manner.
Test
Temperllur.
@I
Symbol
I,
T..,
-lOoe
M~
....
Ty.
".
,.'..,.
,."
M. .
Min
M..
-1.890
-1.205
-1.500
-5.2
-0810
-1.850
-1105
-1.475
-5.2
+85o C
...(l700
Unit
'47
mAdc
200
/lAde:
-1.060
J
21
22
LogiC .. ,,, Threst10ld Voltage
22
Selup
Address
'setup(B-Clock-1
Hold
Address
'l'1old(Clock-B+1
WriteTirne@
Setup
Wnte Enable
Iselup(WE-Clock~)
'setup(WE+C10Ck-1
Address
'setup(A-Clock+)
Da~a
tsetupID-Clock+)
Hold
Wrote Enable
tl'1old(Clock+A+)
Data
tholdtClock+O+1
Write Pul. Width
""'WE
RIM Tune
-0.890
•
-0.910
-0.980
t
•
-1.655
t
-1.630
'0
10
i.
,.
,.,.
,.,.
5.0
10
(:=
12
1,23,=
12
1.21;
+
Vd,
4,20G)
12
,,no
t
Vd,
•
t
•
-, 595
Vd,
t•
t t
•+
4
llG)
10
10
+
4
20
"llG)
10
"
20
+
4.
20
20
Fiture
Put. In Pul.Out
5
5
4
19
19
19
-2.0
-20
-3.0
,.
,.
~2.6
'9
'0
20
---,
r-
L-....J
,.
-0810 V
-1.85 V
3-376
,.
'9
19
19
•
+
+
'9
2
•.:
12
'.23.:
'2
'.m
t
+ ..,1
-3.2 V
'2
14
10
120% 10 80"'{')
• Lim" appl'es for all 'nputs, indiVidually apply VI Lmm 10 pin under les!
In.
1.»;
20
20
30
2.0
2.0
fill T"",
AC liming f'9Ure$ do nOt show all tl'1e necessary pre· seiling cond,tlons
1.:n:':
12
19
(20% to 80%1
Datil has to be clocked
12
CD
10,11
-4.5
5.0
2
CD
•
+
-1.615
Vd,
5.5
,.
@
-0.700
• ++ •+
+ + +
thotd(Clock+~+1
IholdICtock+M-1
Address
4.5,6,7,8,
9,13,14,
15,16,17,
18.19,20
/-lAde
-0.Bl0
-1815
21
Read Enable
Data
0.5
-0960
-1.650
VOLA
tB-OS_
tS+08+
t/rE_Q8+
tClock+QB_
'"'V""I-H-_-.""""'Vo-"'L-m-'n""""'Vo-",H-""'-'n"V'""'L......
--.-.-V"".-.--f
20
10
-1850
22
SWltch.ng Tun., @
AccessT'me
Address Input
-1675
-1080
VOHA
21
Log'c "0" Tl'1reshold Voltage
-0890
+ + +
-1890
VOL
-5.2
,...,,.
,."
245
245
245
lin L
21
22
-1.825
-1035
-1.440
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW:
13
'4
15
20
10
Log'c "0" Output Voltage
VEE'
-0890
+25o c
13
14
'5
VOH
!Vohsl
VILmin VIHArmn VILA",..
_lOGe
+85oe
+25°e
M"
12
Input Current
LogiC .. ,., Outpul Vollage
VIHmu
MCM10143L Test Limits
Pin
Undo<
Power Supply Dram Currenl
f-----.-,
.
'.23.1
MCM10143(continued)
SWITCHING TIME TEST CIRCUIT. 25°C
Vcc
~
VCCO = VCCI = +2.0 Vdc
±O.I~F
Coax
Coax
,----- -----,
I
I
,
:
{
BO
O-----;Ic--i
0---'---1
0----'-1--1
1
•
0-----;1,----1
«
o--~Ic--i
REB
Bl
B2
DB 1
WEO
00
'®-~ H~====~:===~ ::
Pulse Generator
Input Pulse
t+ "" t- : 2.0 ± 0.2 ".
(20% to BO%)
WE 1
n.
1------;---<>
OCI
1----;---<>
0---
0---71I -...,0 1
{o----+:
--I
1
~~ _ c~~c: 1-----;---<>
C 2 REC
PRR "" 1 MHz
PW ;:;:'20
OBO
0-----+,_---'I
I
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
Unused output. connected to a 50-ohm resistor
scope ar. aqual lengths of 50-ohm
coaxial cable_ Wire length should
be
1/4 inch from TPin to input
pin and TP out to output pin.
to ground.
<
3·377
MCM10143(continued)
READ TIMING DIAGRAMS
FIGURE 1
Enable
RE
a
t~'''.Q'-
·,,~·t ~
FIGURE 2
FIGURE 3
Setup .nd Hold
t/~-----------d~'
_________1
B
_
_
FIGURE 4
,_. _ _ _ _ _ _ _
~
Clock
. ~-'-ho-l-d---r-----------
'.,up
WRITE TIMING DIAGRAMS
Enable
WE
Clock
Diloble
WE
Clock
PuiloWidth
r~·"'=r·M·1
F~·'l F'""4==
WE
FIGURE 6
FIGURE 7
'»'hOld
Clock
Ad....
FIGURE 5
FIGURES
A
Clock _____________________'1
3-378
MECL 10,000 series
256 BIT RANDOM
ACCESS MEMORY
MCM10144
256 X 1 BIT RANDOM ACCESS MEMOR Y
The MCM10144 is a fully decoded 256-bit Random Access
Read/Write Memory organized as 256 one bit words. Stored data is
.Iected by means of an eight bit address, consisting of inputs AO
through A7.
The MCM10144 has three active· low chip enable inputs for
increased logic flexibility permitting memory expansion up to 2048
words without additional decoding. For larger memories, the upper
inputs for
address words are selected by using one of the
enabling 1024 word segments.
The MCM10144 operating mode (all ~ inputs low) is controlled by the W£ input. With W£ low, the chip is in the WRITE
mode, the output, Dout, is tow and the data state present at the data
input (pin 13) is stored at the selected address. With the ~ high
the chip is in the READ mode and the data state at the selected
memory location will be presented, noninverted at the data output
(pin 15).
Open emitter outputs permit full wire-ORing to data buses, with
1-· .Q low when the chip is disabled.
The device is fully compatible with the MECL 10,000 logic
family. It is designed for use in high speed scratch pad, control,
cache, and buffer storage applications.
CERAMIC PACKAGE
CASE 620
cr
MCM10144AL
CERAMIC PACKAGE
CASE 690
BLOCK DIAGRAM
PIN ASSIGNMENT
A2
A3
A4
VCC
16
Al
Dout
15
3
A2
WE
14
4
A3
Din
13
5
CEI
A7
6
CE2
-;:
AO
A1
AO
2
2
3
4
9
:
i
';.
III",
"':::,
~
" 0
n
-DO
14
WE
8
12
11
CE3
A5
10
VEE
A4
9
«III
.
8=
"~';;
"'N
«l:!
is
"'-
0
13
Din
~
TRUTH TABLE
INPUT
MODE
A5
A6
A7
Dout
WE
Din
Writ. "0"
L
L
L
L
Write "1"
L
L
H
L
R..d
L
H
H
t/J
t/J
t/J
Q
Disabled
tP -
3-379
OUTPUT
CE
Don't Car•.
L
ElECTR ICAl CHARACTER ISTICS
3i:
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal eQui-
(")
...c3i:
librium has been established. The circuit
is in a test Socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5O~hm
resistor to -2.0 volts. Test procedures are
shown for selected inputs; other inputs
are tested in the same manner.
...
t
A,
A,
AJ
A4
~T
11
A6
12
A7
13
Din
Dout
nO
I,.
....
::J
:;'
c:
CI>
~
TEST VOLTAGE VALUES
We
IVott.,
l'T ...
remp ••tur.
1'4
VIHINJI:
VILmin
VIHAmin
_lOGe
-0.890
-1.890
-1205
+2SoC
-0.810
-1.850
-1.105
+8SoC
-0.700
-1.825
-1.035
I VILAmiX 1 VEE
-1.500
-1.475
1
-1.440
I
·1
I
-5.2
-5.2
-5.2
MCM10144 Test Limits
Pin
Under
Charecteristic
W
W
00
I Power SupplV Drain Current
I,npu, Cunen'
Symbol
T...
+25o
_lODe
Min
M..
Ie
'in H
0
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+8SoC
M••
M..
80
100
mAde
265
50
50
50
IJAde
Min
VOH
15
-1.060
-0.890
-1.675
VOL
15
-1.890
VOHA
15
-1.0BO
Logic "0"
Threshold Voltage
VqLA
15
tCE_D out +
15
Unit
I
05
Logic "1"
Threshold Voltage
Logic "0"
Output Voltage
c
TV.
5
1
12
14
IlnL
Logic "1"
Output Voltage
Min
Write Strobe Mode Times
Setup
Data
Chip Enable
Address
Hold
Data
Chip Enable
Address
tsetuplO±W-
thold(W+D±)
thold(W+~+1
tholdlW+A±1
Recovery Aher Writ" Time
tW+Dout +
tW-Do ... t-
Wri~
tw(WE)
Ptli. Width
15
tsetup(A!VJ:)
Vdc
-1.850
-1.650
-1.825
-1.615
Vdc
"
Vdc
13,14
Vdc·
13·,14
-0.910
-1.655
-1.630
10
10
30
30
-1.595
ns
I
I
16
1,2,3,4,5,6,
7,9,10,11,1"2
16
1,2,3.4.5,6,7,
9.10,l1,1:l,13
1,2,3,4,5,6,
7,9,10,11,12
1,2,3,4,5,6,
7,9,10,",12
5,6,7
Pulse In
Pul .. Out
6,7
5
15
2.0
2.0
0
13,14
7,14
1,14
14
14
14
16
16
5,6,7
13,14
5,14
1,14
30
Vee
Gnd
16
2.0
2.0
10
17
17
12
13,14
-0.700
-0.980
VEE
16
-~.890
18
18
tsetup(~-W-)
VILA ... x
16
-0.810
tA±Dout +
tA±Dout -
VIHAmin
5
1
12
14
-0.960
t~+Dout-
Address Inputs
VILMin
IJAde
Switching Times
Access Times
Chip Enable
V1H""x
16
MCM10144 (continued)
SWITCHING TIME TEST CIRCUIT. 250 C
Vee"" +2.0 Vdc
V out
,,~rtt"~
Coax
,- - - ---.----,
I
I
I
Input
Pulse Generator
Input pulse
t+ = t - '" 2.0 ±. 0.2 ns
(20 to 80%)
I
I
1
I
I
3
sl
51
I
7
I
I
CEI CE2 CE3
AO
2
Al
I
A2
4
I
A3
I
9
I
I
10
I
I
11
12
I
A4
A5
15
Dout
AS
A7
I
I
I
I
I
I
I
J
I
I
13
Din
I
IL _ _ _ _
WE
114
I
I
I
-fl ~,~,
1-3~vdc
50-ohm tarmin,tion to ground located in e.ch scope channel input.
.r.
All input end output cables to the
ICOpe
equel lengths of 50-ohm
coaxial cable. Wire length should
be
1/4 inch from TPin to input
<
pin end TP out to output pin.
3-381
eoa.
..-
MCM 10144 (continued)
CHIP ENABLE ACCESS TIME
Dout
ADDRESS ACCESS TIME
Addrell
Dout
WRITE STROBE MOOE
Addr....
'hold(W+O±l1
\4---.....+'hold(W+CE+)
'hOld(W+A±)-..l
Oaut
3-382
MECL 10,000 series
64-BIT REGISTER FILE
(RAMI
MCM10145
64-BIT REGISTER FILE
(RAMI
The MC10145 is a 64-Bit RAM organized as a 16x4 array. This
organization and the high speed make the MC10145 particularly useful in register file or small scratch pad applications. Fully decoded
inputs, together with a chip enable, provide expansion of memory
capacity. The Write Enable input, when low, allows data to be
entered; when high, disables the data inputs. The Chip Enable input
when low, allows full functional operation of the device; when high,
all outputs go to a low logic state. The Chip Enable, together with
open emitter outputs allow full wire-OR ing and data bussing capability. On-chip input pulldown resistors allow unused inputs to
remain open.
L SUFFIX
CERAMIC PACKAGE
CASE 620
BLOCK DIAGRAM
PIN ASSIGNMENT
Chip Enable
AO_{
Lines
AO
CE
00
16
AI
A2
01
A3
"_,",o.{
Lines
DO
Dl
2
15
Data
3
14
Output
Lines
4
13
02
D2
5
12
6
11
10
D3 _ 0 3
WE
9
8
Write Enable
TRUTH TABLE
VCC = Gnd
MODE
VEE - -5.2 Vdc
Po"" 625 mW tvp!pkg (No Load)
tAeces. = 10 ns tvp (Addre. Inputs)
3-383
OUTPUT
a
WE
D
Writ. "0"
L
L
L
L
Writ. "1"
L
L
H
L
R.ed
L
H
Disabled
H
4J See General Information section for packaging.
INPUT
CE
Don't Care.
o
L
MCM10145 (continued)
ElECTRICAL CHARACTERISTICS
Chip Enable - - - - - ,
Each MECL 10,000 series circuit has been
10
designed to meet the de specifications shown
9
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed cirCUit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
Addre .. {
Lines
5
08t8ln ut'{
p
Lines
4
11
12
QO
A1
A2
6
-2.0 volts.
AO
3
Ce
Q1
Data
A3
Output
DO
Q2
01
Lines
15
02
03 _ Q 3
14
WE
13
Write Enable - - - -.....
nST VOLTAGE VALUES
(Yohs)
"Tao
T.n""'I1'"
~n
a..-....
..m...
Power Supptv O,.,n Current
InputCurrllOt
'.
I,n H
...T_
•
---"'C
MCM10146l T . . Llml..
+25o C
Tv.
'SO
'0
"
'3
-1.060
OutputVoltaga
-0.890
I
VOL
,
'5
LogIe "',.
Thrll'Shold Voltage
VOHA
,.
,
,.
2
'5
Logie "0"
VOLA
-U90
~1.675
I
I
WrIte Strobe Mode T,,""
Setup
Do,.
ChIP Eneble
Add,..,
t~tuplO'WI
tMtupIC""!·W
lyluPIA.W
-, 890
-1850
-1.105
...·c
-0.700
-1.825
-1.035
....
~Adc
4
7
•
'0
.Ad,
Vdo
I
I
I
I
I
-0_
~
I
-1.825
I
I
-1,615
~1.630
I
IIde
Vd,
-0.910
~1.655
"'3
12
I
I
I
I
-1.595
I
Vd,
,~,
"
I
a>
I
I
5
12
"
<2l
5
"
+1.11.11
r---
7.0
7.0
PUI.ln
PUI.Out
6,1,9.10
1,2,14,15
())
!
10,0
l
l
!
2
1,2,14.15
0
3.5
3.5
5,13
3.13
8,1,9,10,13
1,2.14,15
3.0
3.0
3.'
7.5
7.5
7_5
5,13
3,13
6,1.9,10,13
2
1,2.14,15
7.5
11.0
3.0
3.5
3.13
3,6,1.9,10
1,2,14.15
3.0
3.0
3.0
7.5
3_5
3.13
3.6.1.9.10
2
1,2,14,15
Hold
0 ...
....,"'
ChIP EnMJI.
Reeo_y Ah., Wnt. Time
Wnte Pulse Width
Chip Enable
Strobe Mode Timll'l;
setup
0010
Write Enlble
--
o.t'
Wrote Enabl'
Hold
tholdlW·OI
'hold IW.e-E1
tholdlW'·AI
tW+Q+
tW+Q_
PWw
.1.tupIO-CE1
t.tup(W..c"l1
'lHupIA-C"!")
Chip Enable Pulse Wldlh
RIM TIme
120%10110%1
FilII Til""
t20%fO
10%1
2
2
1,2.14,15
2
1
1.2,14.15
'hold let.OI
lholdle1:;·WI
2
2
1,2.14.15
PWce
2
....no lhotdler·AI
-52
-5.2
-52
-1440
-..
5
6
~1.650
V ••
-1.500
3
220
200
200
200
200
220
220
.70
I
~1.850
VILA"".
TEST VOLTAGE APftLIEO TO PINS USTED BELOW
220
-0.700
-1.080
1,2,14.15
-<1.8'0
-0.810
-0.890
SlJritchi",n. . . ~
Atasl Times
Addr. . ,nP\lIl
-lOoe
+25o C
YIHAnlln
-1.205
-0.810
2
ICE...Q+
tCE+QlA+Q+
lA...Q+
lA+Q+
lA-Q_
VILmin
-0.....
'5
Ch,pEnlble
...
0_5
lin l
VOH
logic "0"
Output Vollage
Mn
200
12
LogIC ","
....
VIHmK
!
,
,
,
'3
'3
'3
3.0
())
3.0
())
·Llmlt IIPPhM for.1I inputs, ind''lldUlilly apply V'L mIn to pm un_ IHI.
·-For definItIon of tlml,.. per,met.rs, _ F,g .....,·
a.
TEST VOLTAGE VALUES
tVoltol
@II Test
Temperature
-lOoe
w
~
I'J
Characteristic
Power S~pply Drain Current
I nput Current
-1.890
-1.205
-1.!!QO
.5.2
+25"<:
~.810
-1.850
-1.475
+85oC
-0.700
-1.825
-1.105
-1.035
-5.2
-5.2
MCM10150AL Test Limits
IE
ImH
2
-
-
-
-
linL
-
-
-
-
-
-
~Adc
-1.060
-0.890
0.5
-0.960
-0.810
~.890
~.7oo
Vdc
-1.675
-1.850
-
-1.650
-1.825
0.910
-1.615
Vdc
-1.655
-
-1.595
Min
Min
TVp
110
Logic" 1" Output Voltage
VOH"
2
15
Logic "0" Output Voltage
VOL
15
Logic" 1" Threshold Voltage
VOHA'
15
-1.890
-0.080
Logic "0" Threshold Voltage
VOLA
15
-
+8SoC
+2SoC
Ma.
-0.980
-
-
-1.630
Ma.
Unit
V,Hmax
V,Lmin V,HAmin V,LAmax
Min
-
-
~Adc
2
-
-
-
.
-
-
-
mAdc
13
2
Address Inputs"
tC'E-D ou.t +
tCE.+D out tA+D out +
tA-O out +
Rise Time
/20% to 80%)
t15+
Fall Time
(20% to 80%1
t15-
15
-
j
-
-
-
-
7.0
7.0
20
20
4.0
-
-
-
-
4.0
-
-
·VOH measurement pattern dependent .
•• AC tests shown for only one address line and one output /times are pattern dependent).
-
-
-
Vdc
Vdc
-
-
Switching Times (SO n Load)
Access Time
Chip Enable
-1.440
TEST VOLTAGE APPLIED TO PINS
LISTED BELOW,
Max
150
265
-3d'e
VEE
~.890
Pin
Under
Te..
8
Symbol
V,Hm.x V,Lmin VIHAmin VI LAm. .
-
-
-
ns
j
-
-
-
-
-
-
-
13
Pula In Pula Out
13
13
7
7
7
7
15
VEE
Vee
Gnd
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-32 V
+2.0 V
8
1,16
j j
I
MCMl 0150 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC
Veel "" v CC2 .. +2.0 Vdc
Coax
0.1 IlF
AD
AI
A2
A3
A4
A5
A6
Pulse Generator
V out
Co ••
°outO
°out1
°out2
' T P out
A7
CE
°out3
Input Pulse
t+ = t-'" 2.0 ± 0.2 ns
(20 to 80%)
50-ohm termination to ground 10
cated in each scope channel input.
0.1 IlF
VEE· -3.2 Vdc
Unused output• • r. tied to a 50ohm r.,iltor to ground.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be
< 1/4 inch
from TPin to input
pin and TP out to output pin.
ADDRESS PROPAGATION DELAY
CHIP ENABLE PROPAGATION DELAY
NOTE: Addr • • mult be.t up
_ to produce a high state
on the output being
examined.
3-393
MCM 10150 (continued)
MASTER PART NUMBER
----
MOT'CHIOLA 'NO.
101_11111,1.1111,111'111111,2
~
'V
Sentlconduc 1.0
Megohm must
•• The 1200 -ohm resistor and the scope termination
impedance constitute a 25: 1 attenuator probe.
Coax shall be CT 070-50 or equivalent .
••• Bvpass only that supply opposite ground.
'.
Duty Cycle (VOC) '" _.
'b
4-4
MC1648 (continued)
OPERATING CHARACTERISTICS
Figure 1 illustrates the circuit schematic forthe MC1648.
The oscillator incorporates positive feedback by coupling
the base of transistor 07 to the collector of 08. An auto·
matic gain control (AGC) is incorporated to limit the cur·
rent through the emitter·coupled pair of transistors (07
and 08) and allow optimum frequency response of the
oscillator.
In order to maintain the high 0 of the oscillator, and pro·
vide high spectral purity at the output, a cascode transistor
(04) is used to translate from the emitter follower (05) to
the output differential pair 02 and 03. 02 and 03, in
conjunction with output transistor 01, provide a highly
buffered output which produces a square wave. Transistors
010 thru 014 provide the bias drive for the oscillator and
output buffer. Figure 2 indicates the high spectral purity
of the oscillator output (pin 3).
FIGURE 4 - THE MC1648 OPERATING IN THE VOLTAGE
CONTROLLED MODE
When operating the oscillator in the voltage controlled
mode (Figure 4). it should be noted that the cathode of
the varactor diode (0) should be biased at least 2 VSE
above VEE ('" 1.4 V for positive supply operation).
When the MC1648 is used with a constant dc voltage
to the varactor diode, the output frequency will vary
slightly because of internal noise. This variation is plotted
versus operating frequency in Figure 5.
FIGURE 5 - NOISE DEVIATION TEST CIRCUIT AND WAVEFORM
I
.,::;
100
z·
Q
~
I-
:5
>
w
0
vcc
a:
10
V
5.0 Vdc
Oscillator Tank Components
{Circuit of Figure 4J
>-
f
MHz
0
L
jlH
1.0·10
MV2115
100
10-60
MV2115
2.3
60·100
MV2106
0.15
u
z
W
::J
0
W
a:
u.
52
48
w
44
d
w
40
..
32
:J
...a:
I:J
I:J
0
;
_0
4 turns of No. 22 copper wire.
Vin
56
U
z
L, Micro Metal Toroidal Core #T44-1D,
60
./
/'
36
""
"'~'~'
~
1 k
L:
-=
,
I
II.....
24
20
/'
16
12
8.0
M~1401
/'
1.0
2.0
I
f out
I (31
L_______ J
(121
(51
Veel '-' VCC2 = +5 Vdc
51'FJ
3.0
4.0
5.0
7.0
6.0
8.0
9.0
O. 1 1'F
X
VEE 1 ," VEE2 '" Gnd
1-0
I
I'FI
L
28
[J
(10)
-The 1200 ohm resistor and the scope termination impedance constitute a 25: 1 attenuatar
probe. Coax shall be CT -070-50 or equivalent.
10
Vin. INPUT VOLTAGE (VOLTS)
FIGURE 7
18
N
L' Micro Metal Toroidal Core 6T44 10,
4 turns of No. 22 copper wire.
17
I
~
>
Von
16
C '" 500 pF
U
15
:J
14
zw
0
w
...a:
.
I:J
I-
._- -- -
13
12
/
11
:J
0
;
_0
V
10
/
9.0
/
~
f.-r---- t--
0
1.0
,r,~
1 k
(:
:
I'FI
~
I
L
C:
1200'
I
f out
I (~
=,
1 L_______ J
/
,,~
MV1401
51'FJ
2.0
0.1
U...
1/
8.0
J
(10)
-- ----- ---- - - -
3.0
4.0
5.0
6.0
7.0
8.0
9.0
(121
(51
Veel '" VCC2 '" +5 Vdc
VEEl = VEE2::::' Gnd
XO"1'F
-The 1200 ohm resistor and the scope termina-
10
tion impedance constitute a 25; 1 attenuatar
probe. Coax shall be CT-070-50 or equivalent.
Vin. INPUT VOLTAGE (VOLTS)
FIGURE 8
190
i
~
>
u
Z
w
:J
0
w
...a:
..
I:J
I:J
5 turns of No. 20 copper wire.
170
/'
160
./
150
140
130
120
/
;
70
60
......0
51k -
-
:!
1.0
2.0
3.0
./
"m
0
""'
,r--------,
I
L
I
I
1200'
I
f out
, (3)
I
I
I
IL _ _ _ _ _ _
1121
L'
4.0
(10)
f:.)
./
50
I=
VCC1=-VCC2-+ 5Vdc
"ceo
~
/.
90
_0
V
£
I'FX
>
100
80
V tn
51'F
1/
110
0
£U
L, Micro Metal Torodial Core #T30·22.
180
I
_J
(51
::r:: 0.1 I'F
5.0
6.0
7.0
8_0
9.0
Vin. INPUT VOLTAGE (VOLTS)
4-6
10
·The 1200 ohm resistor and the scope termination impedance constitute a 25: 1 attenuator
probe. Coax shall be CT -070·50 or equivalent.
MC1648 (continued)
Typical transfer characteristics for the oscillator in the
voltage controlled mode are shown in Figures 6, 7 and 8.
Figures 6 and 8 show transfer characteristics employing
onl~ the capacitance of the varactor diode (pluse the input
capdcitance of the oscillator, 6 pF typical). Figure 7 illus·
trates the oscillator operating in a voltage controlled mode
with the output frequency range Ii mited. This is achieved
by adding a capacitor in parallel with the tank circuit as
shown. The 1 kn resistor in Figures 6 and 7 is used to pro·
tect the varactor diode during testing. It is not necessary
as long as the dc input voltage does not cause the diode to
become forward biased. The larger·valued resistor (51 kn)
in Figure 8 is required to provide isolation for the high·
impedance junctions of the two varactor diodes.
Good R F and low-frequency bypassing is necessary on
the power supply pins (see Figure 2).
Capacitors (Cl and C2 of Figure 4) should be used to
bypass the AGC point and the VCO input (varactor
diode), guaranteeing only dc levels at these points.
For output frequency operation between 1 MHz and 50
MHz a 0.1 /IF capacitor is sufficient for Cl and C2. At
higher frequencies, smaller values of capacitance should be
used; at lower frequencies, larger values of capacitance. At
higher frequencies the value of bypass capacitors depends
directly upon the physical layout of the system. All bypassing should be as close to the package pins as possible
to minimize unwanted lead inductance.
The peak-to·peak swing of the tank circuit is set internally by the AGC circuitry. Since voltage swing of the
tank circuit provides the drive for the output buffer, the
AGC potential directly affects the output waveform. If it
is desired to have a sine wave at the output of the IViC1648,
a series resistor is tied from the AGC point to the most
negative power potential (ground if +5.0 volt supply is
used, -5.2 volts if a negative supply is used) as shown in
Figure 10.
At frequencies above 100 MHz typ, it may be necessary
to increase the tank circuit peak-to· peak voltage in order to
maintain a square wave at the output of the MC1648. This
is accomplished by tying a series resistor (1 kn minimum)
from the AGC to the most positive power potential (+5.0
volts if a +5.0 volt supply is used, ground if a -5.2 volt
supply is used). Figure 11 illustrates this principle.
The tuning range of the oscillator in the voltage con·
trolled mode may be calculated as:
f max
yco (max) + Cs
fmin
yCo (min) + Cs
1
--:--r=:=======
where fmin =
2tr y L (CO (max) + CS)
Cs = shunt capacitance (input plus external
capacitance) .
CD = varactor capacitance as a function of
bias voltage.
APPLICATIONS INFORMATION
erable over RF switching with a multiple crystal system),
and a broad range of tuning (up to 150 MHz, the range
being set by the varactor diode).
The phase locked loop shown in Figure 9 illustrates the
use of the MC 1648 as a voltage controlled oscillator. The
figure illustrates a frequency synthesizer useful in tuners
for FM broadcast, general aviation, maritime and landmobile communications, amateur and CB receivers. The
system operates from a single +5.0 Vdc supply, and requires
no internal translation, since all components are com·
patible.
The output frequency of the synthesizer loop is determined by the reference frequency and the number programmed at the programmable counter; fout = Nfref. The
channel spacing is equal to frequency (fref).
For additional information on applications and designs
for phase locked·loops and digital frequency synthesizers,
Frequency generation of this type offers the advantages
of single crystal operation, simple channel selection, and
elimination of special circuitry to prevent harmonic lock·
up. Additional features include de digital switching (pref-
see Motorola Application Notes AN-532A, AN-535, AN-553,
AN-564, AN-594, or Phase-Locked Loop Systems Data
Book.
4·7
MC1648
(continued)
FIGURE 9 - TYPICAL FREQUENCY SYNTHESIZER APPLICATION
VoltageControlled
Oscillator
MC1648
f - -....~_fout
fout = Nfref
where
N
=
Np • P
+A
N = Np. P + A
Figure 10 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To obtain a sine
wave at the output, a resistor is added from the AGC
circuit (pin 5) to VEE.
Figure 11 shows the MC 1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To extend the
useful range of the device (maintain a square wave output
above 175 MHz), a resistor is added to the AGC circuit at
pin 5 (1 k·ohm minimum).
Figure 12 shows the MC1648 operating from +5.0 Vdc
and +9.0 Vdc power supplies. This permits a higher voltage
swing and higher output power than is possible from the
MECL output (pin 3). Plots of output power versus total
collector load resistance at pin 1 are given in Figures 13
and 14 for 100 MHz and 10 MHz operation. The total
collector load includes R in parallel with Rp of L 1 and
Cl at resonance. The optimum value for R at 100 MHz is
approximately 850 ohms.
FIGURE 10-METHODOF OBTAINING ASINE·WAVE OUTPUT
FIGURE 11 - METHOD OF EXTENDING THE USEFUL RANGE
OF THE MC1648 (SQUARE WAVE OUTPUT)
+5.0Vdc
+5.0 Vdc
1--+---0 Output
1 k min
8
I
4-8
MC1648 (continued)
FIGURE 12 - CIRCUIT SCHEMATIC USED FOR COLLECTOR OUTPUT OPERATION
+9.0 V
~.01 jJF
R
VCC2
(14)
+5.0
Output
v
~----~--_1----_+--_1Ql0
t-----+-----+---~ all
Q12
02
(10)
(7)
Bias Pt.
'.2 k
L2
+--__::#~::::C=o2_'
VEEl
('2)
(8)
V EE 2
(5)
ILl. I , 0
'T'''_ 'T' .
AGC~
~
"f
.. +5.0 V
~
ci
Tank
FIGURE 13 - POWER OUTPUT varsus COLLECTOR LOAD
FIGURE 14 - POWER OUTPUT varsus COLLECTOR LOAD
$eetestcircuit, Figure 12,f= 100MHz
S.etestcircuit, Figur.12,f:::: 10MHz
C3 = 3.0 - 35 pF
C3 = 470 pF
Collector Tank
Collector Tank
Ll=0.22jJH
Cl=1.0-7.0pF
R=50n-l0kn
Rpof Ll andCl:::: 11 k{l@100MHzResonance
L1 = 2.7 jJH
C' = 24 - 200 pF
R = 50 n - 10kn
Rp of L 1 and Cl
Oscillator Tank
L2 = 4 turns #20 AWG 3/16" 10
C2 = 1.0 - 7.0 pF
= 6.8 kn@
10 MHz Resonance
Oscillator Tank
L2 = 2.7 jJH
C2 = 16 - 150 pF
14
_ 6
~
-4
I
/
I:;)
~ 3
o
a: 2
w
\
!II
~
a: 5
:;)
'\
_'2
!II
~
a:,O
\
~
S
..
/
8
V
l-
\
:;)
I-
~
ioo'"
6
~
:;)
\
0
a: 4
w
.
~
..
~
01
0
2
0
100
1000
TOTAL COLLECTOR LOAD (ohms)
'0,000
10
100
1000
TOTAL COLLECTOR LOAD (ohm,)
10,000
MC1650. MC1651
The MC1650 and the MC1651 are very high speed
comparators utilizing differential amplifier inputs to sense
analog signals above or below a reference level. An output
latch provides a unique sample-hold feature. The MC1650
provides high impedance Darlington inputs, while the MC·
1651 is a lower impedance option, with higher input slew
rate and higher speed capability.
Complementary outputs permit maximum utility for
applications in high speed test equipment, frequency meas·
urement, sample and hold, peak voltage detection, transmitters, receivers, memory translation, sense amplifiers
and more.
The clock inputs (Ca and Cb) operate from MECL III
or MECL 10,000 digital levels. When Ca is at a logic high
level, ao will be at a logic high level provided that V 1
V2 (Vl is more positive than V2).
is the logic com·
plement of ao. When the clock input goes to a low logic
level, the outputs are latched in their present state.
Assessment of the performance differences between the
MC1650 and the MC1651 may be based upon the relative
behaviors shown in Figures 3 and 6.
Positive Logic
_O~
V1a(10)
V2a(9) 56 3 :
- 1+ 0
C. (8)
4·
a
C
2(6)_00
3 (7) 00
'----'
0_~14(2)_01
V1b(16)
1 2 3- : 1 +0
V2b(15)11
Cb(1) 13
a
C
15(3)01
L.......-_...J
v CC • +5.0 V - P;n 7,10 - (11). (14)
VEE - -5.2 V D P;n 8 (12)
Po = 330 mW tvp/pkg (No Load)
•
tpd "" 3.5 ns typ (MC1650)
•
Input Slew Rate = 350 V/",s (MC16501
•
Differential Input Voltage:
-5.0 V to +5.0 V (-30o e to +8SoC)
•
Common Mode Range:
-3.0 V to +2.5 V (-30o e
-2.5 V to +3.0 V (-30o C
= 3.0 ns typ (MC1651)
- 500 VII" (MC1651)
TRUTH TABLE
to +SSoCI (MC1651)
to +8SoC) (MC1650)
•
Resolution: ~20 mV (_30o e to +8SoC)
•
Drive. 50
n
>
ao
Gnd"" Pin 1,16 (4) (5)
•
lines
Number at end of tarminal danotes pin number for L package (Case 6201,
Number in parenthesis denotes pin number for F package (Case 650).
t/J ""
C
V1, V2
00n+1
H
V1>V2
H
L
H
V1 3 a:
(7)
} - - - - - - - --0
' - - - -_______- - -- -E
MC16S1 Inputs
,---_------ A
+--------8
t---+-------- C
O-------r--+-+-~~-+~
V1 (10) 6
E-------~----~~--~----_+~--~----+---~
Rp
}--------o
4
Clock
--- E
S. Gen.,.' Inform.tion Metion for p.::k . . ing Informetion.
4-10
-
POSITIVE LOGIC
ELECTRICAL CHARACTERISTICS
5 _ 0: 2:0
V1a6~
V~.
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink (lERC-LlC214A2WCB or equivalent) or a transverse
Ca 4
C
3 00
Q
3:
....
(")
O'l
CJ'I
o
L SUFFIX
V1b12~
V2bl1
0
Q
14Ql
airflow greater than 500 linear fpm should
be maintained while the circuit is either in a
test socket or is mounted on a printed
(;b13
a
C
•
CERAMIC PACKAGE
CASE 620
3:
....
(")
1501
circuit board. Test procedures are shown
for selected inputs and selected outputs.
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
a 50-ohm resistor to -2.0 Vdc. See general
Pin
Und ..
T",
'CC
7,10
S
VIHm. .
VILmln VIHA.min VILAm. .
_30°C
+25 oC
-0.875
-1.890
-0.810
+8So C
-0.700
data.
Symbol
....
CJ'I
(Valt,)
Clock Aperture Time_Q}_
RiltTi ....
110%'0 _ I
FellTi ...
110%'090%1
NOTES:
Mel11iOU11161 L T... Limits
_oe
+25o C
-:JIIOe
Sell F iou'. 8.
Sell No ••
@
VlO(
Vee a>
VEE a>
+2.00
+7.00
+1.110
+2.00
+1.190
+2.00
+7.00
+7.00
-3.20
-3.20
-3.20
See Figure 2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Min
Mo.
Min
Mo.
Min
Mo.
Unit
VR'
VR2
VR3
Vx
Vxx
Vee a>
VE~a>
PI
P2
'3
2.0
5.0
2.0
5.0
2.0
5.7
ns
5
-
-
4
1,11,16
7,10
8
6
-
-
-
-
'2+
13+
'2_
2
2
2
3
3
3
2
2
2
3
3
3
2
2
3
3
6
6
2
3
2
.~
3
'&-2'6-2'&-2t6-3+
'&-3+
'6-3+
t4+2+
t4+2t4+3+
t4+3t.tUD
.~
-
5
5
~
-
1.0
1.0
1.0
1.0
4.7
2.0
!- !
-
3.5
3.5
3.0
3.0
2.5
1.5
1.0
1.0
1.0
1.0
4.7
2.0
5.2
n.
~ ~ ~ ~
-
-
-
-
-
3.5
3.5
3.0
3.0
1.0
1.0
1.0
1.0
3.8
3.8
3.3
3.3
n.
n.
n.
n.
n.
n.
5
-
5
-
-
-
5
5
-
-
5
2.0
CD Mlximum Power Supply VoltllQII (bayond which device life may be iq)8ired:
IVccl+ IVEEI"12Vdc.
® Unu.d clock input. may be tied to ground.
(3)
~
+2.000
Vx
+1.040
T...
'6+~
Clock Enable Time
VR3
t6+2+
t6+2+
t6+2+
'6+~
<2>
VR2
Symbol
t6+3-
Clod< '0 Ou'PU'
VRI
~
5
6
6
5
5
5
5
5
5
5
-
-
-
-
5
-
6
5
5
-
-
6
6
-
5
-
-
-
1,11,16
7,10
8
-
l
~
~
-
-
-
-
4
4
4
4
1,11,16
1,11,16
1,11,16
1,11,16
1,11,16
1,11,16
7,10
7,10
7,10
7,10
7,10
7,10
@)
8
8
8
8
8
8
6
5
5
6
6
6
6
6
6
6
I All T. .pero.u...
I
MC16&O
I
MC1861
6
6
6
6
-
-
6
6
-
'4
--~
6
-
-
4
-
B
-
-
~
4
4
-
-
-
-
VR2
I
VR3
I +4.900 I ~.4OO
I +4.400 I ~.9OO
ELECTRICAL CHARACTERISTICS
POSITIVE LOGIC
"'."~
Thil MECL III circuit has bHn deligned to
milt the de ip8cificationl Iho'M'1 in the
tl.t table, after thermal equilibrium hal
t:.en estabtished. Air flow greater than
500 linear fpm thould be maintained while
the circuit il either in a test lOCket or is
mounted on a printed circuit board. Telt
procedures are shown for selected inputs
and selected outputs. The other inputs
and outputl are tested in 8 simitar manner.
Jutputs are tested with 8 50-ohm resistor
to -2.0 Vdc. See genera' information
.ction for complete thermal data.
V2.
9
Ca
8
.
-
0
0
6
00
C
Q
7
00
2
01
" "~
'V2b
Cb
15
-
0
0
1
C
0
Power SupPIv Or.,n Current
Positive
Neptive
~
.....
w
ICC
'e
Input Current
lin
MCl650
MC165!
Input Le.k. Cur...nt
MC1650
MC1651
Input Clock Current
'R
10
10
L09IC "1" Output Voigge
LogiC "0" Output VOltaige
L.g;c "I" n ... ho'd V.'~
a>
Log;c "0" T",.. hold
6
6
VOH
6
6
6
6
7
7
7
7
6
6
6
6
7
7
7
7
VOL
f
VOHA
2
3
4
v.'-r
a> '
3
<
10
10
lin H
lin L
VOLA
~
•
FSUFFIX
3:
...
CERAMIC PACKAGE
CASE 650
(")
m
...
-3D"c
-0.875
-1.890
-1.180
-1.515
+0.020
-<1.020
v".
+26 oC
-0.810
-0.700
-1.850
-1.095
-1.025
-1.485
-1.440
+0.020
-0.020
See NotefD
-+(1.020
-0.020
_·c
MC161OF/1651F T... Limits (j)
_"c
-3O"c
+25 o C
U ....
Tost M"
Min
Min
11,14
12
~
(Vah.)
Pin
Sy_'
(")
TEST VOL TAGE VALUES
OT ...
Temperatur.
C....ct• •ic
~
01
3
...3:
-.
....,..,;
....
-
-
-
-
....
....
YA<
YA3
VAl
g
Ycc<3l YEE<3
...
::l
+5.0
+5.0
-5.2
-5.2
:;'
+5.0
-5.2
t:
Yc~
y.;110-7+
Clock to Output
(l)
Clock Enable Time
G>
Clock Aperture Time
R_Time
G>
(10%'090%1
Fill Time
(10%'090%1
NOTES:
aired:
(2) Unu.d clock
@ See F igur. 8.
Ma. Unit
5.7
VR3
TEST VOLTAGE APPLlEO TO PINS LISTEO BELOW
+85°C
M..
110-7+
110-7+
t7_
+25 oC
Min
VR2
_lODe
+8SoC
Pin
Under
T. .
VRl
9
10
10
9
-
9
-
9
-
9
-
9
9
9
9
9
-
-
10
-
9
--
-
-
-
-
4.5.16
11,14
12
-
4,5,16
11,14
12
10
8
4,5,16
4,5,16
11.14
11,14
12
12
10
10
4,5,16
4,5,16
11,14
11,14
1.·
12
10
10
8
8
8
!
11.14
~
@)
12
~
-
8
-
10
-
4.5.16
-
-
-
P4
10
10
10
-
10
10
-
P3
10
10
-
9
-
-
-
9
P2
10
9
9
10
10
-
-
r All Tempor ••ur•• I
VR2
10
-
-
-
-
~
8
8
-
I VR3
I -0.400
I
Me1650
I +4.900
I
MC1651
I +4.400 I -0.900
MC1650, MC1651 (continued)
FIGURE 1 - SWITCHING TIME TEST CIRCUIT @ 25°C
V In to Channel A
'~"p-+----+---+-----+-11':~:f1
fr'~
~J
I
~~ I
PI
~
·V out to
Channe' B
Gnd - - ,
Q~-+--"'"
I
Q~-~-----'
VEE·
-3.2 Vdc
50-ohm termination to ground located
in each scope channel input
All input and output cables to the scope
are equal lengths of 50-ohm coaxial cable.
·Complement of output under te.t should
always be loaded with 50-ohms to ground.
4-15
MC1650. MC1651(continued)
FIGURE 2 - SWITCHING AND PROPAGATION WAVEFORMS @2s"C
The pulse levels shown are used to check Be parameters
over the full common-mode range.
V - I nput to Output
~V'H
7
50%---VA
_ _ _ _oJ
.._ _ _ _ _ v, L
a
t+
Test pulses:
t+. t_
f
="
1.5 ±O.2 n$ (10% to 90%)
= 5.0 MHz
50% Duty Cycle
VIH is applied to
C during tests.
TEST PULSE lEVELS
Pulse 1
Pulse 2
Pulse 3
MCI650
MC1651
MCI650
MC1651
MCI650
MC1651
+2.100V
+2.100 V
+5.000 V
+4.500 V
-0.300 V
-0.800 V
VR
+2.000 V
+2.000 V
+4.900 V
+4.400 V
-0.400 V
-0.900 V
VIL
+1.900V
+1.900 V
+4.800 V
+4.300 V
-0.500 V
-1.000V
VIH
Clock to Output
PI
V'H +2.100 V
VA +2.000 V
Vin
VIL + 1.900 V
+1.'10 V
P4
C
+0.310 V
a
P4, t+. C "" 1.5
± 0.2
ns.
4-16
MC1650. MC1651
(continued)
FIGURE 3 - PROPAGATION OELAY Itpdl versus INPUT PULSE AMPLlTUOE ANO CONSTANT OVERDRIVE
Test Circuit
,-------1
t>-D
Vin
C
V ,H
= Gnd
I
L
1
'=
50
50
-2.0
a
C
50
Vref
I
% Device
I
a
II
a
-
Vref
______
~
Negative Pulse Diagram
Positive Pulse Diagram
Positive
Overdrive
.. ~
,pr-
"
Vm
j
t
V::f Pe
V
PA
a
v
I
o
50%
Negative
Ove,d,;v.
t
~
Input switching time is constant
at 1.5 ns (10% to 90%),
Propagation Delay versus Pulse Amplituda
5
11TT
T T T;]IIII
- 4~ 1
OverdrIVe Constant@100mV
w
~
~
>
I---
-
-
-
I
Positive Going Pulse
- - - Negative Going Pulse
MC1650"
3
III tll,~
)<
11:') f;(V
~
'"z
'">=
'"'"
i
MC1651,V
2
l-
I
f----t- tPC! referenced to PA, Ps '" 20 mV
i'-..
........ 1'
o
0.01
0.02
0.05
0.10
0.20
0.50
1.0
PULSE AMPLITUDE PA. PB (VOL TSI
4-17
2.5
10
MC1650. MC1651 (continued)
FIGURE 3 (continued)
Propagation Delay versus Overdrive
P~. p~ C;n~ta~tl~ 100 ~v
1\
2
-
-
I
I I
Positive Overdrive (PAl
-
- - - Negative Overdrive (PSI
1\
\.\1
tpd is measured from Vrel on the input
to 50% on the output.
MC1650
-/
r~
1
MC1S51
0
0.01
~:\
\:
~
~
tpd Isreterenced to 2.5 V overdrIve.
II'f
~
0.02
0.04
0.07 0.10
0.2
0.3
05
0.7
1.0
II I
2.5
OVERDRIVE (VOLTS)
FIGURE 4 - LOGIC THRESHOLO TESTS (WAVEFORM SEQUENCE DIAGRAM)
+0.020 V
Vin
-0.020 V
I
(I i
\
I
I
V 1HA
I
I
C
"'"
Q
"0"
i\
"1"
I
5
"0"
Sequential
Test Number
(See Test Table)
3
4-18
4
10
MC1650. MC1651 (continued)
FIGURE 5 - TRANSFER CHARACTERISTICS (0 venusVini
Test Configuration
Dif,f:~:~tia' ~
Vin
{
I
4>--- - - -1
o-----4~-t__"..J1:
V IH
Q~-;'-I-'----O Q
D
I
I
% DeVice
Q~:
_____ ~
o-c----1----
~
=>
~
~
=>
o
-1j-------- [ - -
-
--f-;.------+--t-
,...+--.....
...--+-+-+
.........+t--...., logic "I"
- -1-- - - - t - -
t----- t---- f--1rI- --
~
--- - - - - t - -
t--
w
'"
;
--
----1--+-----1
- ---
-
~-t---
---
-t---t-
ci
---t------j logic "0"
-:2~O-~-175-~-1~O---5~-.r-~~-~lO~-~,~5-~20
Vrel
V m, DIFFEAENTIAllNPUT VOLTAGE (m VOLTS)
4-19
MC1650. MC1651
(continued)
FIGURE 6 - OUTPUT VOLTAGE SWING vorsus FREQUENCY
(AI Test Circuit
r-------,
V,
""
V,H
v2
C
*
I
t>-o
I
Q
f
50
50
I
Q
C
Q
I
I
Y:. Device
-2.0 Vdc
I
I
L ______
~
(BI Tvpical Output Logic Swing versus Frequencv
0.850
MC,651
.......
v;
~
~
,
0.650
~
l"'-~
r---..:'
~
1\'"
\ \ f'\..'"~
I\.
l-
~
g 0.450
.:
~
~ 0.250
\
"
50
~
\ 1\
\ \
mV
20
30
70
50
~
75\ '00\
Input Voltage
0.050
10
\\
leak to
200
pear-
100
200
\~O
300
FREQUENCY (MHz)
0.850
-r-...
MC,650
v;
:;
~ 0.650
-....... .......
.......
........
I-
=>
~
...;;~
r-....
.........
"-
t'--,.
"-
I-
~ 0.450
"'"
~
~ 0.250
~
'"
""
" '" '"
'"'" ('-----r=="",-
\
50
"
~
\
75' 100'
100\
lboo
Input Voltage
mV Peak to Peak
0.050
10
,\
\
f',
20
30
50
70
FREQUENCY (MHz)
4·20
100
200
300
MC1650. MC1651
(continued)
FIGURE 7 - INPUT CURRENT versus INPUT VOLTAGE
TEST CIRCUIT
lr--rTo+50
50
J- i
_ : 50
b
Vee
Vdc
O.l/JFI
r - Vee- -Vee ---,I
r---~-~~,l--it>-- °
I
'I
Q
-2.0 Vdc
c
I
lin
e
Q
I
VIH:~:
I -
f+
,
0
Q
I
e
Q
I
L VEE
Gnd
Gnd
0'~1--9
r'lVEE
,
,
I
J
=
-5.2 Vdc
Typical MCI650 (Complementary Input Grourdedl
1---+--+--= ~-:---=~-+-
151----j--l--+--+-~-_~30~07e-+--+-...+.-..~···~·
.~k:....."....
:;;---,...- -
1
10r-~r--j-_+--+--+--~-'~~~'~"'~"~'~"'-+-~
~
....
...•....
+250C~ __
~
+85 0e
~ 15r----jI--j--+--+--Hi-~
___
-~~+-~+-~
+25'e
I---t----t--f ---+----t-+:'
.......•
3
a....
- )--
.. ' .... .'
5I----jl--l---I---- - - -30'e
4'
~
~
~ 10r----j1--j-_+--+--H~~~~~--~·~~-------+--~
..- -- -
"""
j
-
. Y:;;
0
Typical MC1SSl (Complementary Input Grourdodl
30,--,-,--,--,-,--,-,-,--,-,--,
---f--+---II---+--t---j
~
5r----jI--j--+--+-~-~-+_-+_-+~85~O~e~
0b;t;_~~=+=+=+=~
-5
-5 .,.,...••...
-1.5
-1
-1
+1
+2
+2.5
-1.5
-1
-1
Vin, INPUT VOLTAGE (VOLTS)
Vin.INPUT VOLTAGE (VOLTS)
4-21
2
1.5
MC1650. MC1651 (continued)
FIGURE 8 - CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS@250C
Vee =
Vin to Channel A
+7.0
0:;1
VXX
= +2.0
V out to Channel B
hCo,
I'F:Jri_~I'F
r-
Vee
V;no---f---<~-+-"'l+
VR
0
U
CO--------I---""ole
1
Gnd--'
1
_+-__
..J
0 .....
1
_ _-+1_--,
Or
1
i
DO
1
e
1
1
1
I
1
Q
1
50
1
1
L ___VEE _ _ ~
r---11 T
-=-
0.' I'F
0 VEE
= -3.2
Vdc
50-ohm termination to ground located
in each scope channel input.
All input and output cables to the scope
are equal lengths of 50-ohm coaxial cable.
Analog Signal Positive and Negative Slew case
Vin Negative - -
-
~----------VR
--,,\
"
Vin Positive ---~
+ 100 mV = +2.100 V
VA = 2.000 V
'- -
-
-
-CIOCkE~abl;-VR -100 mV "" +1.900V
c ---+--.---,.
VtH=+1.'10V
X-------V'L
~V:-:---
=
+0.3'0
V
.. , ..
-L
Positi...,e ----+-----...r.... '--l--\j'----"O"
50%
Q
o Nega,;ve
-----ic=---,-Pd-3-_F u! __ u': ',
-%
.....
50
Clock enable time = minimum time between analog and clock
signal such that output switches, and tpd (analog to 0) is not
degraded by more than 200 ps.
- - - - - - Clock aperture time = time difference between clock enable time
and time that output does not switch and V is less than 150 mV.
4-22
'l~
BINARY COUNTER
________~____
M
__E_C_L_I_II_M_C__16_0_0_~
__ri_es~
MC1654
The MC1654 is a four-bit counter capable of divideby-two, divide-by-four, divide-by-eight, or a divide-by-16
functions_ When used independently, the divide-by-16
section will toggle at 325 MHz typically. Clock inputs
trigger on the positive going edge of the Clock pulse.
Set and Reset inputs override the Clock, allowing asynchronous "set" or "clear". Individual Set and common
Reset inputs are provided, as well as complementary outputs for the first and fourth bits. True outputs are available
at all bits.
TRUTH TABLE
OUTPUTS
INPUTS
C2
00
R
SO
Sl
S2
S3
Cl
1
a
a
a
a
a
0
a
a
a
a
a
a
a
a
a
a
a
a
a
0
1
1
1
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
0
a
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
(/J = Don t
0
a
a
a
a
a
a
a
a
a
a
a
0
a
-
125
~>-
D
Cl 0 - ' - -
100
300
<»
125
:>c
100
1
100
~
>- -----t
.J ....
~
....
~
x
...f
~~
Q
~~~~
60
1235
f- f-
C2
5
50 k 50 k
50 k
50
50 k k 560
~
1-
r----rt:
R
~
1.3 k
1.3 k
~~
(05
675
325
~
)
675
.Iv EE
~
1.5 k
1 k
1.5 k
FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT
VCC VEE
-3.2 Vdc
+2.0 Vdc
Coax
Coax
Coax
50
50
Clock 1nput {ot----1~--O---
100
0".
I
2
3
Cl
00
C2
03
12
50
51
9
14
10
50
100
52
4
53
00
R
01
03
02
6
11
All input and output cables to
the scope are equal lengths of
50,ohm coaxial cable.
Open
4·24
13
100
-=-
0
S03005
51
7
Qt
•
52902'"
ELECTRICAL CHARACTERISTICS
This MEeL III circuit has been designed to
-
-
me,
11'
R_.,
o
Cl
2
Clock 2
C2 R
a
c
u
11'
AT
c
A
-
u
11'
AT
AT
Clock 1 15
s
-
"
11'
12
a
@Test
Temperatur V'Hmu
-JOoc
-0.875
10
oo! ..
o
53 13
t
Pin
Power Supply Drain Current
Input Current
LogiC "1"
",.
~
c.n
+8SoC
-0.700
Set Delay
Reset Delay
Rise Time
Fall TIme
MaXimum Toggle Frequency
~
---
-5.2
::J
C
-1.025
-1.440
-5.2
Co
-1.850
-1.830
+8SoC
VEE
Gnd
8
1.16
-
-
8
8
1.16
1.16
-
-
8
8
1.16
1.16
8
8
1.16
1.16
1.16
1.16
3.7.9.14
10
8
8
1.16
10
3.7.9.14
8
8
1.16
1.16
Max
Min
Ma.
Unit
VIHmax
IE
8
-
-
200
mAde
10
-
10
2.3.7.9.14.15
-
1.00
0.60
-
mAde
mAde
10
-
1m L
10
2.3.7.9.14.15
-
0.5
0.5
-
-
-
'in H
-
-
j.JAdc
/JAde
-
10
-0.875
-0.875
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
-
3.7.9.14
10
-
-
10
3.7.9.14
-
-
-
VOH
G) -1.045
4.13
5.6.11.12 ~ -1.045
VOL
4.13
~ -1.890
5.6.11.12 1 -1.890
-
-1.650
-1.650
-1.850
-1.850
-1.620
-1.620
-1.830
-1.830
-1.575
-1.575
Vdc
Vdc
-1.065
-1.065
-
-0.980
-0.980
-
-0.910
-0.910
-
Vdc
Vdc
-
-1.630
-1.630
-
-
-1.600
-1.600
-
-1.555
-1.555
Vdc
Vdc
2.9
1.0
2.7
1.0
3.1
ns
2.7
1.0
~
2.0
2.0
~
~
3.1
3.7
2.0
2.0
4.1
4.1
~
~
2.0
2.0
4.1
4.1
ns
ns
ns
ns
VOHA
4.13 ,~
5.6.11.12 4
VOLA
4.13
5.6.11.12
'15+4+
1.0
'15+5+
'2+4+
'2+5+
4
5
4
5
'15+4'15+5'2+4'2+5-
4
5
4
5
1.0
t3+4+
t3+5_
4
5
2.0
2.0
39
39
'10+4+
tl0+5-
4
5
2.0
2.0
3.9
3.9
2.0
2.0
3.1
3.7
14+
15+
14_
IS_
4
5
1.0
1.0
2.9
2.9
1.0
1.0
2.7
2.7
1.0
1.0
3.1
3.1
4
1.0
1.0
2.8
2.8
1.0
1.0
3.0
3.0
ns
ns
260
1.0
1.0
300
2.6
2.6
-
260
-
MHz
~
II
-Individually apply VIH or VIL to tnput under test
2.9
~
~
S
3
~
~
®
- -
--
~
1.0
+
-
~
~
-
-
-
10
a.> Set all four flip-flops by applYing PAt to pins 3,7,9,
and t4 Simultaneously
Q) Reset
3.1
+
ns
ns
ns
-
-
-
-
all four fltp-flaps by applYl!lg PA 2 to pin 10
---,-VIH
PAl
L..-VIL
8
8
1~
PutSBln Put. Out -3.2Vdc +2.0Vdc
15
4
8
1.16
IS
5
2
4
2
5
-
-
-
-
3
3
4
5
8
8
1.16
1.16
-
-
10
10
4
5
8
8
1.16
1.16
-
15
IS
4
-
5
8
8
1.16
1.16
15
15
4
5
8
8
1.16
1.16
-
-
8
1.16
-
-
~
-
15
15
2
2
4
5
4
5
-
1t-Q
Vcx
6
Q
~
-
-2.0 volts.
Bias Filter 12
F SUFFIX
CERAMIC PACKAGE
CASE 6S0
P SUFFIX
Q
Input Filter 13
PLASTIC PACKAGE
CASE 648
4
TEST VOLTAGE VALUES
Vdc±'%
Test
Temperature
V,H
-3O"c
0.0
+25o C
0.0
0.0
(@I
~
'"
+85o C
'"
MC1658 T.t Limits
Pin
Under
Ch.racteristic
Power Supply Orain Current
Symbol
Test
'E
M..
Min
Ty.
V3
-1.0
VIHA
-2.0
-1.0
-2.0
-1.0
+2.0
+2.0
Min
Input Current
linH
I nput Leakage Current
linL
2·
"0" High
Output Voltage
VOH
4·
S··
-1.045
-1.045
-0.875
-0.960
-0.960
-0.810
-0.890
-0.875
-0.810
-0.890
"0" Low
OutPUt VOltage
VOL
4·
S··
-1.890
-1.890
-1.650
-1.850
-1.830
-1.650
-1.850
-1.620
-1.S20
Mo.
Unit
32
32
mAde
350
.uAdc
V,H
2
V,L
V3
0.5
-1.830
Vdc
VOC
Oscillator Frequency
Tuning Ratio Test t
1.S
1.'
2.7
130
155
175
78
90
100
TR
3.1
4.5
·Germaruum dIode (0.4 drop) forward bIased from 11 to 14 (11
• -Germanium diode (0.4 drop) forward bUlSed from 14 to 11 (11
tTR '" Output frequency at V!;;X '" Gnd
OutPut frequency at VCX -2.0 V
130
2.7
2.7
fosc2
foscl
~
---+t----
14).
141.
VIHA
VEE
-1.575
-1.575
Vdc
Vdc
1,5
MHz
MHz
C1 =
C2 =
CX1'"
CX2 '"
1,5
1,5
1,5
1,5
3.0
3.0
110
1Vcel
Gnd
1,5
1,5
1,5
8
8
CXl
2.7
I -5.2
.uAdc
-0.700
-0.700
(Tests shown for one output, but
checked on both)
t+
t-
VEE
-S.2
-S.2
mAde
AC Charecteristics (Figure 2)
Rise Time (10% to 90%)
I
+8SoC
Mo.
8·
8··
2·
Fall Time (10% to 90%)
+2.0
VOL T AGE APPLIED TO PINS LISTED BELOW:
+2SoC
-3O"c
Min
V,L
-2.0
CX2
Gnd
VEE
-3.2 V
VCC
+2.0 V
11,14
11.14
1,15
1.15
11.14
1,5
11.14
1,5
11,14
1,5
O.OlI-6F connected from pin 12 to Gnd.
0.1)01 "F connected from pin 13 to Gnd.
10pF connected from pin 11 to pin 14.
5 pF connected from pin 11 to pin 14.
n
o
::l
~,
::l
C
ct>
Q.
MC1658
(continued)
FIGURE 2 - AC TEST CIRCUIT AND WAVEFORMS
Vee
+2.0 Vdc
Input
Filter
Coax iei Cables
'---"t----o---! vex
(Equal lengths, typ 2 places)
To Scope
ex
50-ohm termination to ground located in each scope channel input.
*O.I"F
-3.2 Vdc
VEE
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
a
4-28
MC1658
(continued)
FIGURE 4 - RMS NOISE O.EVIATION
versus OPERATING FREQUENCY
FIGURE 3 - OUTPUT FREQUENCY varsus CAPACITANCE FOR
VARIOUS VALUES OF INPUT VOLTAGE
1000
150 MHz
@
10,000
5.0 pF
1111111
100
Z
0
1
75 MHz @ 5.0 pF
N
~
>-
~
VEE'
:;;
w_
o N
35 MHz @ 5.0 pF
I:
Vee'" +5.2 Vdc
i=
<
>-!
u'"
z::;
10
w
~a:
::>
Cl
-
w
II:
IL
1.0
0,0 Vde
1000
===
Vcx
U~lx
w
a:
IL
/i\
.lllJv de
'Z.
1.0
1""-
11111111
10
DC CONTROL INPUT' 4.0 Vde
III
I I 11111~_LLUl
1.0
10
100
10
L
0.1
VIC~ "Ifi~ Vdt
o. 1
100
Cl
o Vdc
100
1000
CX(PICOFARODS)
f. OPERATING FREQUENCY (MHz)
"
10,000
FIGURE 5 - FREQUENCY·CAPACITANCE PROOUCT varsus
CONTROL VOLTAGE (VCXI
...U
:;:J
o
o
a:
Q.
1500
1400
w
1200
Z
1100
U
<
...
U
<
<
~
>U
Q.
Frequency-Capacitance Product at Desired
/
7' - . -
aw
400
IL
300
--- _ . -
./
700
500
..,.L.
--/ /'
800
600
Vex _
Desired Frequency (MHz)
900
Z
a:
=
1000
:;:J
w
CX(pf)
1300
L
/'
./
f-"'"
x
u
•
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
Vcx, INPUT VOLTAGE (Vde)
4-29
-0.4
-0.2
o
MECL III MC1600 series
DUAL 4-INPUT GATE
MC1660
MC1660 provides simultaneous OR-NOR or ANDNAN D output functions with the capability of driving
50-ohm lines_
These devices contain an internal bias
reference voltage insuring that the threshold point is
POSITIVE LOGIC
::: : § = t i =X : 3
(10)
6
(11)
7
C
(14) 10
(1S) "
always in the center of the transition region over the
(7)
y
2
§=x=
o
(16) 12
temperature range (-300 to +850 C)_ The input pulldown
(6)
resistors eliminate the need to tie unused inputs to VEE.
X=A+B+C+D
Y =A + B + C + D
14
(2)
1S (3)
(1) 13
NEGATIVE LOGIC
(8)4~A
B
X
(9)
S
(10)
6
(11)
7
c
y
§=x=
3
(7)
2
(6)
tpd'" 0.9 ns typ 15l0-ohm load)
== 1.1 ns typ ( 50-ohm load)
0
(14) 10
(1S) 11
(16) 12
Po = 120 mW typ/pkg (No load)
X=A_S_C_O
Y=A-S-C_O
Full Load Current, I L -= -25 mAde ma)(
14 (2)
1S (3)
(1) 13
Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).
CIRCUIT SCHEMATIC
(4)
(S)
16
VCC2
(6)
OR
2
(3)
o---I--~~
----+-----sOC
+86°C
P ..
~UPPIY Drain Cur,..nt
Input Current
NOR Logic "1" Output Voltaglt
Svmbol
Tat
.>sOC
-3O"c
M..
M..
IE
linH
linL
M..
_DC
M..
Min
-0.875
-0.960
-1,890
-1.850
-1.830
-1.180
-1.095
-1.025
-1.515
-1.485
-1.440
VEE
-5.2
-5.2
-5.2
TEST VOLTAGE APPLI ED TO
PINS LISTED BELOW:
M..
Unit
VIHmo VILmin VIHAmin VILAmax
IVCCI
VEE
Ond
28
mAde
1,18
350
~Adc
1,18
1,18
0.5
-1.045
VOHtP
-0.815
-0.810
-0.700
MC1116DL Test LimiU
u_
Cher.n.inic
VIHmu VILmin VIHAmk'l VILAm ••
-0.810
-<).890
-0.700
/o'Adc
Vd,
1,16
j
I 1 1 1 1 w,1
j ! 1 1 l 1 1
j ! 1 1 l I 1
1
1
1
1
1
1
1
1
NOR LogiC "0" Output Voltage
VOl. tP
-1.890
-1.650
-1.850
-1.620
-1.830
-1.575
OR Logic "1" Output Voltage
VOHtP
-1.045
-0.875
-0.960
-0.810
-0.890
-0.700
Vd,
1,16
OR Logic "0" Output Volta.
VOL41
-1.890
-1.650
-1.850
-1.620
-1.830
-'.575
Vd,
1,'6
2
I
NOR Logic "'"
Threshold Voltage
VOHAtP
3
NOR Logic "0"
Threshold Voltage
VOLAtI>
I
I
OR Logic "'" Threshold Voltage VOHA41
j
-'.065
j
-'.065
I
OR Logic "0" Threshold Voltage VOLAtP
Switcl'ling Times (50 n load)
Propagation Delay
Ri. Time
Fall Time
14+3t4_2_
t4+2+
t4-3+
'3·
'2.
'3'2-
j
1 1 1 1 1
1
1
1
j
j 1
1
1
1
I
j
1 1
-0.980
-1.630
3
1,18
-0.910
-1.600
-0.980
-1.555
-0.910
Vdo
1,16
Vd,
',18
Vdo
1,16
1,16
-1.630
-1.600
-1.555
Vd,
18
18
16
1.6
2.2
2.2
2.2
2.2
1.7
1.7
1.5
15
2.1
2.1
2.1
2.1
1.9
1.9
1.7
1.7
2.3
2.3
2.3
2.3
"'
Pul.ln Pul.Out
4
3
2
-3.2 V
8
I 1
I 1
',16
1,16
1,16
1,16
4
•
4
-IndiVidually test each Input applying VIH or VIL to the Input under test.
+2,0 V
1,18
tP NOTES
The electrical spacifiClltions shown abow apply to the MCl880
under the following conditions:
1. The packagl is hou.d in a suitable "'at sink. t
D'
2. Air is blown transwr.ly ovar the PICkage. See 91ne,..1
information section for mora details.
tA suitable heat sink is an IERC UC14A2U or equivalent.
4-32
MC1660 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C
V out OR
Vin to Channel "A"
V out NOR
To
Channel
"8"
Coax
50 , - - Input
~____~~__;'__~
-
--.,
Coax
50
50
100
100
I
I
Pulse Generator
§xt:
I
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
100
Input Pulse
t+
=::
t- =
I
I
I
I
L ______ ...JI
1.5 i.O.2 ns
Unused outputs connected to 8 50-ohm resistor to ground
PROPAGATION DELAY
,-----+1.11 V
+0.31 V
V out OR
t+
t-
V out NOR
4-33
MECL III MC1600 series
QUAD 2-INPUT "NOR" GATE
MC1662
NEGATIVE LOGIC
POSITIVE LOGIC
(8)
(9)
(10)
(11 )
4~
S
2
(6)
~==Lr--3
(7)
B
(14)10~
(8)
4~
2
(6)
(10)6~3
(7)
(9) S
B
Four 2-input NOR or NAND gating functions
in a single package. An internal bias reference
voltage insures that the threshold point remains
in the center of the transition region over the
temperature range (-30 to +850 C).
Input pulldown resistors eliminate the need
to tie unused inputs to VEE.
(11) 7
14 (2)
(lS) 11
(14)10~
14 (2)
(lS) 11
(16)12~
(1) 13
X=
15 (3)
(16)12~
lS (3)
(1) 13
x = .A""iB
A+B
tpd "" 0.9 ns typ (510-ohm load)
1.1 ns typ (50-ohm load)
=
Po == 240 mW typ/pkg (No load)
Full Load Current. I L = -25 mAde max
Number at end of terminals denotes pin number of L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).
CIRCUIT SCHEMATIC
(11 )
(4)
(10)
6
(S)
(8)
4
(9)
5
--++--
CL
LSUFFIX
CERAMIC PACKAGE
CASE 620
14
12~
13~15
TEST VOLTAGE VALUES
IVoIts)
,I::>
@Test
~
Temperature
o
-JO"c
Under
Power Supply Drain Current
Input Current
Logic ''1''
Sy ... bol
Tost
Logic "0"
Logic "0"
Min
-1.045
-1.045
VOL
-1.890
-1.890
-1.065
-1.065
VOLA
Threshold Voltage
Min
Fall Time
-1.890
-1.180
-1.515
-5.2
-'.850
-1.095
-5.2
+8SoC
-1).700
·1.830
-1.025
-1.485
-1.440
Max
-0.875
-0.875
-1.650
-1.650
-0.960
-0.960
-1.850
-1.850
350
~Adc
V'H max
14+2+
'2+
'2_
·lndividually test each input applying VIH or VIL to input under test.
VILmin
-5.2
-0.810
-0.810
-0.890
-0.890
-1.620
-1.620
-1.830
-1.830
-0.910
-0.910
-1.600
-1.600
-0.700
-0.700
-1.515
-1.575
-1.555
-1.555
VIHAmin
VILA max
VEE
Gnd
8
1.16
1,16
8
.uAdc
-0.980
-0.980
-1.630
-1.630
Unit
mAde
1,16
1,16
Vdc
Vdc
1.16
1,16
Vdc
Vdc
1,16
1,16
Vdc
Vdc
1,16
1,16
Pulse Out
-3.2 V
+2.0V
1,16
1,16
1.6
1.8
1.5
2.1
1.7
1.9
2.3
8
8
2.2
2.2
2.1
2.3
8
1.7
1,16
Vdc
Vdc
Pulse In
'4-2Rise Time
VEE
-0.875
-0.810
56
Switching Times (50 n Load)
Propagation Delay
V,LA max
_30 De
+2S o C
+8S0C
Max
05
VOH
VOHA
V'HA min
TEST VOLTAGE APPLIED TO PINS LISTED BelOW,
+250 C
Max
~
'in L
Output Voltage
Logic "1"
Threshold Voltage
Min
IE
Output Voltage
V'lmin
MCl664L Test Limits
Pin
Characteristic
VIH max
1,16
1,16
MC1664(continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 2SD C
V In to Chennel "A"
V out to Channel "s"
Coax
50
Input
r-----...,
,
~
50
I
----+0.31 V
t- -
I
PUI .. Generetor
100
-=
~
100
-+-L-./I
I
I
~
~
L _ _ _ _ _ ..I
+1.11V
50%
V out
AU input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
Input Puis. t+., C.,. 1.6 (±O.2) ns
Unused outputs connected to a 50-ohm resistor to ground.
4-41
t++
MECL III MC1600 series
DUAL CLOCKED R-S FLIP-FLOP
MC1666
This device consists of two Set· Reset flip· flops in a
single package which require a clock input to enable the
set·reset inputs. Internal input pull·down resistors eliminate
the need to return unused inputs to a negative voltage.
The device is usefu I as a high-speed dual storage element.
POSITIVE LOGIC
(9)
(6)
(11) 5
7
C =t
t
(8)
4
A
a
2
3
(7)
(16) 1 2 t = t 0 15(3)
(14)
9
C
11) 13
R
a
14 (2)
tpd "" '.6 ns tvp (51 O-ohm load)
= 1.8 ns typ (50-ohm load)
P D = 220 mW typ!pk 9 (No Load)
TRUTH TABLE
R
C
S
0
1
0
1
0
0
1
0
vee1 = Pin 1 (5)
VCC2 = Pin 16 (4)
VEE = Pin 8 (12)
°n+1
On
On
1
0
N.D.
Numbers at ends of terminals denote pin numbers for L package (Case 620).
(/) - Do n't Care
N.D.
= Not
Numbers in parenthesis denote pin numbers for F package (Case 650).
Defined
CIRCUIT SCHEMATIC
C
(14)
9
a
VCC2 S
(4) (16) (2)
16 12 14
Q
R
11)
15 13
(3)
vee1
R Q
·0
S
C
(5)
(8) (6)
(7)
(9)
111)
7
1
4
2
3
50 k
8
(12)
Vee
Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).
See Ganeral Information section for packaging.
4-42
3:
....
en
(")
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
~
meet the de tp8cifications shown in the
test table, aft.r thermal equilibrium has
bean established. Air flow greater than 500
linear fpm should be maintained while the
circuit is either in a test socket or is
mounted on a printed circuit board. Test
6
11
9c U
8
A
7
a
procedures are shown for only one input
and one output. The other inputs and
16U3
14
c
1
A
a 2
Characteristic
I
Symbol
~
(.oJ
Under
Test
I
12
1
16
14
CD
Povver Supply Drain Current
I
IE
Input Current
I
ImH
ImL
~
I
+2SoC
-30°C
Min
M"
-
0" LOyle .. , , Output Voltage
VOH
I
"0" Lagle "0" Output Voltage
VOL
"0" Lagle "1 'Output Voltage
VOH
-1.890
+25 0 C
-0.810
+8SoC
-0700
Min
55
-5.2
TEST VOL TAGE APPLIED TO
PINS LISTED BELOW:
Max
Gnd
11.14
12
4.5
1.14
14.16
14
12
12
12
12
12
12
12
4.5
4.5
4.5
VIHmax
mAde
mAde
mAde
mAde
-
-
VILmln VIHAmm VILAmaM
-0 810
-0810
-0 890
-0.890
-0700
-0700
3~
5
-1 620
-1620
-t 830
3
-1 850
-1 850
-1 575
-1 575
Vrl,
Vdc
22~
5
-1 045
-1 045
-0.875
~O 875
·0.960
-0 960
-0 810
·0810
-0 890
-0 890
-0700
-0700
Vrl,
Vd,
-1 650
-1 650
-1 850
-1850
-1 620
-1 620
-1 830
-1830
-, 575
-1 575
Vdc
Vrl,
-
1
14
-
-0910
-0910
-
VOLA
3@
VOHA
2@
"0" Logic "0" Output
Threshold VOltage
VOLA
2@
2(Z)
-0.980
·0.980
-1630
-1 600
-0 980
-1 065
-1 830
-1630
-1630
., 555
-1.555
-1600
1,14
-
1
14
-
-
16
14
-
-
16
14
-
Vrl,
Vdc
-1.555
-1 600
16
/JAde
jJAdc
-0910
t16+3+
t16+211+2+
11+3-
,.
,-
2.7
10
25
11
2.8
• • • • • •
1a
2.5
10
23
3
2
~
!
~
~
2.3
08
2.8
09
05
2.4
0.8
05
20
2.3
22
05
Notes appear on page lollowlng Elecl(lcal Characte(lstlcs tables
11
4.5
4.5
12
12
4.5
4.5
4.5
4.5
4.5
4.5
1
16
1
16
12
16
14
-
14
-
1
Pulse In Pulse Out
10
12
12
Velc
Vdc
Vd,
1
4.5
4.5
4.5
4.5
Vdc
1
16
14
ns
~
2.7
ns
! !
"'
ns
14
•
3
3
2
2
16
16
3
2
ns
1
1
2
3
2.9
ns
14
2.3
2.6
ns
14
2.3
4.5
4.5
12
12
12
12
12
SWitching Times (50 H Load)
3
3
2
2
3
2
(Vee l
VEE
Unit
·0.960
-0 960
"0" LogiC "1" Output
Threshold Voltage
o
-5.2
-1 440
-1650
-, 650
"0" LogiC "0" Output
Thleshold Voltdge
Rise Time
-1 485
-1 025
-0875
-0875
33~
7
Fall Time
-1.095
-1 830
-1 890
-1 890
VOHA
Reset Input
-1.850
3
3 $
3
-1.065
-1.065
Set Input
-5.2
Vrl,
Vdc
-1 890
-1 890
I
VEE
-1 515
0.5
0.5
~~
114+3+
t14+3t14+2114+2+
::l
C
-1 180
-
VOL
Clock Input
::l
VILmin VIHAmln VllAmax
-0875
-, 045
-, 045
16
"0" LogiC .. ,., Output
Threshold Voltage
"0' Lagle' 0" Output Voltage
V'Hma)(
-JOoC
+85
M"
0.370
0370
0.225
1.14
I.
Mon
0
~.
@Test
Temperature
MC1666F Test Limits
Pon
r;-
TEST VOL TAGE VALUES
(Volts)
outputs are tested in a similar manner.
Outputs af. t.sted with a 5CHlhm resistor
to -2.0 Vdc. See general information section for complete thermal data.
en
en
F SUFFIX
CERAMIC PACKAGE
CASE 650
12
12
4.5
4.5
-3.2 V
+2.0V
12
4.5
12
12
•
4.5
4.5
12
12
12
4.5
4.5
4.5
12
4.5
-
-
-
..
-
•
ro
a.
ELECTRICAL CHARACTERISTICS
3:
n
....
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been e.tablished. The package should be
hou.d in a suitabte heat sink (lERC-
O'l
O'l
O'l
14A2CB or equivalent) or a transverse air
flow gr.ater than 500 linear fpm should
be maintained while the circuit is either in
a test socket or is mounted on a printed
circuit board. Test procedures are shown
for only one input and one output. The
other inputs and outputs are tested in a
similar manner. Outputs are tested with a
!iO-<>hm ...istor to -2.0 Vdc. See general
C
4
R
9
C
13
A
a
Characteristic
I
Symbol
P01/\le1 Supply Drain Current
I
'E
Input Current
I
lonH
5", l-
Vin3
Vin2 to S (VIH to VIL)
H
f
Vin2
Vin1 to C (VIH to VIL)
Vin2 to R (VIH to VIL)
L
®
Apply Sequentially:
®
Apply Vin3 to C (VIH to VIL)
(J)
Apply Vin3 to S (VIH to VIL)
H
~
Vin1 to A (VIH to VIL)
Vin1 to S (VIH to VIL)
Vin2 to R (VIH to VIL)
L
test
4-45
Me 1666 (conti nued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @25 0 C
V out
To Chanr.el "8"
Vin
To Channel "A"
All input and output cables to
the scope are equal lengths of
Coax
100
50-ohm coaxial cable.
Coax
50
Coax
50
50
C2
Q2
+2.0 Vdc
1/2
02
52 R2
Input pulses
by 2 pulse
51
generators
g
g
I
----'-----
--~
50
1
Plo---~,,~------------_+----~t->---------------lr_,----~5~0~il~c~o-a-x~-o5
100
Vin
To Channel "A"
100
50
MC1670
Pl
o
P2
---+1.11 V
n
-----
+0.31 V
1\-
::::120 n.I----------------'
-----+1.11V
'-----------+0.31 V
S
A
SET/RESET TO
ta_
a/a
(Switch Sl in position shown)
a
0
to+
C
5
A
CLOCK TOO/a
(Switch S1 in opposite position)
Q
0
4-46
MECL III MC1600 series
DUAL CLOCKED LATCH
MC1668
This device is a Dual Clocked Latch/R-S Flip-Flop.
Whenever the Clock is low, the R-S inputs control the
output state. Whenever the Clock is high, the output follows the data (D) input.
POSITIVE LOGIC
(9)
5
~
S
(10)
6-0
(11 ) 7 - C
a
""'-----2
0""'-----3
(6)
TRUTH TABLE
(7)
R
(8) 4
(16) 12
(IS) 1 1 - - 0
~
~
S
S
R
0
I
0
I
0
0
I
I
''""
''""
On+1
'"
''""
0
0
0
0
I
I
On
I
0
'"
0
I
(Vee)
Gnd
-1.650
-1.650
-0.890
-0.890
VOLA
1.15,16
VEE
12
-1.890
-1.890
-1.620
-1.620
"0" LogiC "0" Output
Threshold Voltage
I VIHA min I VILA max I
Vd,
Vd,
-0.810
-0.810
2@
-5.2
-0.700
-0.700
-1.850
-1.850
-0.980
2
-1.440
-0.890
-0.890
-0.960
-0.960
VOHA
-5.2
-5.2
-1.u25
-1.810
-1.810
-1.650
-1.650
3
VIH mulVIL min
11,14 I
.'lAdc
/.IAdc
0.500
-0.875
-0.875
3@
3@
-1.095
-0960
-0.960
-1.890
-1.890
2@
Vee
-1.515
-1.485
-0.875
-0.875
-1.045
VOHA
VILA mex
-1.180
-1.045
-1.045
-1,045
'"0" LogiC "I" Output
Threshold Voltage
Reset Input
Max
20>
VOLA
Set Input
I
2@
2@
"0" LogiC "0'" Outpu t
Threshold Voltage
n
Min
VOL
3@
Switching Times (50
Clock Input
+8soe
Mu
VIHA min
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
VOH
Output Voltage
"a'"
3e
3@
I
C.
(Volts)
@Test
13
"a"
(I)
TEST VOLTAGE VALUES
Pon
Power Supply Ora In Current
0)
~
'*
~
+8so cl -0.700 I -I.H.JU
Symbol
3:
n
8
1
B
to -2.0 Vdc. See general information
section for complete thermal data.
ChliracteristlC
~
CERAMIC PACKAGE
CASE 650
..
2,9
14
t
16
12
15
15
Vd,
15
14
'i'
Pulse In IPulseout
3
14
2,3
2.6
14
2,3
2.7
2.7
2,7
2.7
16
16
+
+
+
+
4,5
•
-32 V
I!
+2.0 V
4,5
12
12
4,5
12
12
4,5
4,5
12
12
4,5
4,5
~
4,5
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink (I ERC·LIC·
214A2WCB or equivalent) or a transverse
5~
60
S Q
2
:
R Q
3
C
12~
11
0
S
Q
15
9
C
RQ1
14
LSUFFIX
13
airflow greater than 500 linear fpm should
be maintained while the circuit is either in a
-
:s::
....
C')
0)
~
8
CERAMIC PACKAGE
CASE 620
test socket or is mounted on a printed
...
::J
::J
circuit board. Test procedures are shown
for selected inputs and selected outputs.
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
8 5O-ohm resistor to -2.0 Vdc. See general
information section for complete thermal
Power Supply Drain Current
Input Current
IE (HI'Z)
T...
-100C
Min
"'.i:-"
Min
1m H
1'1,'2,13(2)
9
lin L
111.12.13(i)
I
Max
Min
I
0.500
0.500
VOH
15@
15@
-1.045
-1.045
-0.960 1-1.810
-0.960
-1.810
-0.890
-0.890
"0" Logic "a"
Output Logic
VOL
15@
1~
-1.890 1-1.650
-1.890
-1.650
-1.850
-1.850
620
-1.620
-1.830
-1830
"O"Logic "1"
Output Voltage
VOH
14@
14®
-1.045 1-0.875
-1.045
-0,875
-0.960 1-0.810
-0.960
-0.810
-0.890
-0.890
14 Q)
14@)
-1.890 1-1.650
-1.890
-1.650
-1.065
-1.850 1-1.620
-1.850
-1.620
-0.980
-1.830
-1830
15
15
15
VOL
"0" LogiC "1" Output
Threshold Voltage
VOHA
"0" LogIC "0" Output
Threshold Voltage
VOLA
"0" Logic" '" Output
Threshold Voltage
VOLA
"0" Logic "0" Output
Threshold Voltage
Switching Times (SO
Clock Input
n
VOLA
t9+15+
t9+14ts+14+
Fan Time
.+
,-
Set Input
112+15+
t12+14Reset Input
®
15
15®
15Q)
14
14®
14Q)
14
14 (i)
14®
•
113+14+
tt3+15-
15
15
14
14
-0.87~
,•
-1630
-1.065
•
Load)
t9+15-
Rise Time
(i)
-0.875
't
14,15
0.8
14,15
15
14
0.5
1.0
1.0
14
15
1.0
1.0
ONotes appear on page following Electneal Characterlstic51ables
-0.980
-1.630
•
2.7
1-'
•
t
':T5i'5
-1.095
-1.485
·52
+S50C
-0.700
-1.830
-1025
~
~
2!
1.1
0.9
0.5
2.5
2.2
0.9
0.5
2.5
25
1.1
1.1
2.3
23
1.1
25
25
1.1
1.(
2.3
2.3
~
2.8
2.4
~
•
1.1
1.1
1.1
Unit
I
VIH maxlVIL min
mAde
7,9
mAde
mAde
11,12,131
9
-0.700
-0.700
Vdo
Vdo
13
Vdo
Vdo
12
-0.700
-0.700
Vdo
Vdo
12
-1.575
-1.575
Vdo
Vdo
'3
Vdo
"f V1•
I VIHA min I VILA max
• •
13
12
11
11
13
12
11
~
2.9
2.6
27
27
2.7
27
12
~
11
9
I
PUI~ In Pul~_Out
15
15
14
14
l
14,15
Gnd
1,16
1,16
13
11
2.8
1,16
1,16
1,16
9
Vdo
(Vee I
I
1,16
1,16
1,16
1,16
"
11
I
1,16
1,16
1,16
1,16
12
V1
-1555
VEE
11,12,13
9
-1.575
-1.575
-0910
•
'TI
~
-1.850
jJAdc
jJAdc
-0.910
-1600
-1.600
1.0
,
I
I
I
I
VEE
TEST VOL TAGE APPLIED TO PINS LISTED BELOW;
Max
55
0.370
0.225
"0" LogiC "1"
Output Voltage
"0" Logic "0"
Output Voltage
I
VILA max
-0.810
+8S o C
+2SoC
Max
11
9
CC
I
VIHA min
+2SoC
MCl668L Test Limits
Pin
Under
Symbol
~
(Volts)
Temperature VIH max Vil min
-30°C -0875
-1.890
data.
Chilractaristic
c:
TEST VOLTAGE VALUES
@lTest
13
8
1,16
• •
•t •
•
•
8
1,16
8
1,16
8
1,16
-3.2 V
,
+2.0 V
1T
1,16
14,15
1,16
12
12
15
14
1,16
1,16
13
13
14
1,16
'5
1,16
MC1668 (continued)
NOTES
CD
I E is measured with no output pulldown resistors.
®
Test voltage applied to pin under test.
(SLVIH)
V,L
H
--.~--.
@)
Apply S8Cluentially:
Vin2 to C (V'H, V,L)
Vin3 to 0 (V,H to V,L)
Vinl
~
1~5 ns
H
Vin2
®
Apply Sequentially:
Vinl to S (V,H to V,L)
(i)
Apply Sequentially:
Vinl to A (V,H to V,L)
Vin2 to C (VIH. V,L)
---{
~5
ns
Vin3
~5 ns~
t"" 0
Vinl to R (V,H to VIL)
~
H
L
test
4-50
Vin2 to C (V,H. V,L)
Me 1668 (continued)
SWITCHING TIMES TEST CIRCUIT AND WAVEFORMS@250C
Vin
V out
To Channel "A"
To Channel "S"
All input and output cables to
Coax
100
the scope are equal lengths of
50-ohm coaxial cable.
Coax
Coax
Vee'" +2.0 Vdc
VEE
50
Cl
50
02
1/2
1/2
Ql
D
51 Rl
I nput pulses
by 2 pulse
eenerators
Vdc
C2
01
D
= -3.2
50
Q2
52 R2
o
o
0
0
Plv---~T<~__________~______________________~~~__~5AO~-U====J--05
+____________-l--~_-,\5A°;"""--fI-J._OR
Vin
Coax
P2v--~I<~+_ _ _ _ _
To Channel "A"
Coax
100
100
--+1.11 V
Pl
r-\
P2
+0.31 V
r-'\---. ---- +1.11 V
- - - - - - : : ] 2 0 n,f-~-----.J
'------- +0.31
5
A
'0-
SET/RESET TO a/a
(Switch 51 in position shown)
0
5
to+
C
D
CLOCK TOO/a
(Switch S1 in opposite position)
0
5
4-51
V
MC1670
The MC1670 is a Type D Master-Slave Flip-Flop
designed for use in high speed digital applications.
Master slave construction renders the MC1670 relatively insensitive to the shape of the clock waveform,
since only the voltage levels at the clock inputs control
the transfer of information from data input (D) to output.
When both clock inputs (Cl and C2) are in the low
state, the data input affects only the "Master" portion of
the flip-flop. The data present in the "Master" is transferred to the "Slave" when clock inputs (Cl "OR" C2) are
taken from a low to a high level. In other words, the output state of the fl ip-flop changes on the positive transition
of the clock pu lse.
While either Cl "OR" C2 is in the high state, the
"Master" (and data input) is disabled.
Asynchronous Set (S) and Reset (R) override Clock (C)
and Data (D) inputs.
Input pulldown resistors eliminate the need to tie unused
inputs to VEE.
POSITIVE LOGIC
NEGATIVE LOGIC
1915 S--------,
1111
7 C1
1141 9 C2
1151 11 D
181 4
191 5
S------,
a
2 161
1111 7 e:1~ro,r-"
1141 9 C2-_____../1
a
2 161
a
3 171
1151 11
a
3
D
171
1814 R-------.J
R------"
Number at end of terminal denotes pin number for L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).
veel
VCC2
= Pin
= Pin
1 (5)
16 (4)
VEE::: Pin 8 (12)
Power Dissipation = 220 mW typical (No Load)
ftog = 350 MHz typ
TRUTH TABLE
TIMING DIAGRAM
C
\'------
R
S
D
C
On+1
L
H
4>
4>
H
H
L
4>
4>
L
H
H
4>
4>
N.D.
L
L
L
L
an
L
L
L
-F
L
L
L
L
H
On
L
L
H
L
L
H
...r
On
L
L
L
H
H
---+-----'''' 0
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
Open [:
100
t
100
50
l
O. 1 1'F
-3.2 Vdc
SET UP TIME WAVEFORMS@ 2s"C
, - - - - -...... - - - - - - + 1 . 1 1 V
' - - - - - - - +0.31 V
TPin2
Clock
+0.31 V
TP out
Q
Output
~
\'--HOLD TIME WAVEFORMS
@
250 C
,..----+1.11 V
" - - - - - - ' , - - - - +0.31 V
TPin2
Clock
+0.31 V
TPout
QoutPut~
\'------'/
Set up time I, the minimum time before the positive transition of the clock pulse (C) that information mUlt
be pr...nt at the data (D) Input.
Hold time I, the minimum tlma after the positive tranlitlon of the clock pulse (e) that information mUlt
remain unchangad at the dna (D) input.
4-56
MC1670 (continued)
FIGURE 4 - TOGGLE FREQUENCY TEST CI RCUIT
+2.0 Vdc
Coax
Coax
l
50
o.... F
al"'-----~
Sine-Wave Generator,
VSias
= 0.71
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
Vdc
'00
(Use High
I mpedance Probe
to Adjust VBias)
I o.
50
1IlF
de Supply
-3.2 Vdc
FIGURE 5 - TOGGLE FREQUENCY WAVEFORMS
TA = 2 SoC
-+1.11V
Clock Input
--- +0.71 V Sias
300
MHz-max
-+0.31 V
-r
aora
600 mV min
Output
The maximum toggle frequency of the MC1670
has been exceeded when either:
1. The output peak-To-peak voltage swing falls below
600 mill ivoln.
OR
2. The device ceases to toggle (divide bV two).
~
FIGURE 6 - MAXIMUM TQGGLE FREQUENCY (TYPICAL)
+1.050
+1.000
+0.950
+-0.900
'6 +0.850
C +0.800
~ +0.150
~ +0.700
~ +0.650
1+0 .500
ii +0.450
> +0.400
+0.350
+0.300
+0.250
.75
-,
-
.........
.......
=
2SoC
=
+2.0 Vdc
Vee
::<
-3.2 Vdc
Figure 6 illustrates the variation in toggle frequency with the
de offset voltage (VBia,) of the input clock ,ignal. VBia, i, defined
by the test circuit in Figure 4, and waveform Figure 5.
Figures 8 and 9 illustrate minimum clock pulse width recom·
mended for reliable operation of the MC1670.
.....
225
TA
Vee
275
325
'\
./
375
425
fTog (MHz)
4-57
MC1670(continued)
FIGURE 7 - TYPICAL MAXIMUM TOGGLE FREQUENCY
.ersus TEMPERATURE
400
350
1".000
,
-
-
300
250
o
-30
85
50
25
T A. AMBIENT TEMPERATURE (oC)
FIGURE 8 - MINIMUM "DOWN TIME" TO CLOCK
OUTPUT LOAD = 50 n
I
.1
I
o or ~
L
i
r
--
;-...
- - CJCK
V
1\
j
..L
1
J
\J ~
II
10 ns/OIV
FIGURE 9 - MINIMUM "UP TIME" TO CLOCK
OUTPUT LOAD = 50 n
I_
V\
a or a r-/'
.1
r yI
I
L f\
1.0 ns/DIV.
4-58
CLOCK
MC1670 (continued)
u
u
>
<>----L
~Cl
--:.c'Cl
=n
----:"1-
~
~
A
~
A
~,i
rOIVN
U
U
>
~,L
<.)
y
A-
i=
«
:t
w
x
<.)
¥
A
~
w
w
>
III
....
:5
<.)
a:
(3
Ir=7\
0
....
CD
U
I-
:t
W
I
:;!
w
~
a:
J
¥
A
::J
t!l
~\
'::,,L
"0
"'
~
.fi.-
"0
"'
~
~
~
J
r;
u:
"
0
"'
"
0
"'
0"
"'
u (/)
C[
0
4·59
MECL III MC1600 series
TRIPLE 2-INPUT
EXCLUSIVE-OR GATE
MC1672
This three gate array is designed to provide the positive
logic Exclusive-OR function in high speed applications.
These devices contain a temperature compensated internal
bias which insures that the threshold point remains in the
center of the transition region over the temperature range
(-30°C to +85 0 C). Input pulldown resistors eliminate the
need to tie unused inputs to VEE.
POSITIVE LOGIC
(8)
(9)
(16)
(10)
(14)
(11)
3~
8
2 (6)
S
13~
6
14 (2)
1:~lS(3)
X=AeS+Aes
ve e l = Pin
NEGATIVE LOGIC
(8)
(9)
(16)
(10)
(14)
(11)
1 (5)
VCC2 == Pin 16 (4)
VEE == Pin 8 (12)
3~2(6)
S
B
tpd == 1.1 ns typ (5l0-ohm load)
1:~14(2)
== 1.3 os typ (50-ohm load)
Po = 220 mW typ/pkg
1:~lS(3)
Full Load Current, IL = -25 mAde mal(
X=AeB+Aes
Number at end of terminal denotes pin number fOl" L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).
CIRCUIT SCHEMATIC
Vee,
VCC2
16 (4)
2 (6)
7( 11)
14 (2)
1 (S)
(3)
......-+-1-<>
3 (8)
8
13 (16)
(12)
VEE
Number at end of terminal denote. pin number for L package (Case 620).
Number in parenthesis denote. pin number for F package (Ca.. 650).
S . . General 1nformation section for packaging.
4-60
11 (14)
15
...3:
ELECTRICAL CHARACTERISTICS
C')
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. Air flow greater than
500 linear fpm should be maintained while
the circuit is either in a test socket or is
mounted on a printed circuit board. Test
procedures are shown for selected inputs
~
I\)
8
::I
F SUFFIX
~
CERAMIC PACKAGE
CASE 650
and selected outputs. The other inputs
::I
c:
a
8~_X.6
and outputs are tested in a similar manner.
9~
Outputs are tested with a 50-ohm resistor
to
~
-2.0 Vdc. See general information
16~2
TEST VOL TAGE VALUES
(Volts)
@l
Tost
Temperature
Pin
~
~
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
linH
0.75 linH
linL
Logic "1" Output Voltage
Logic "0" Output Voltage
Logic "I" Threshold Voltage
Logic "0" Threshold Voltage
Switching Times (50
VOH
VOL
VOHA
VOLA
Under
Test
12
8,14,16
.
9,10,11
6
6
6
6
6
6
6
6
-30"c
Max
-
Min
-1.045
-1.045
-1.890
-1.890
-1.065
-1.065
-
-0.875
-0.875
-1.650
-1.650
-1.630
-1.630
MC 1672F To.t Limits
+25"c
+85"c
Min
Max
Min
Max
55
350
-
0.5
-0.960
-0.960
-1.850
-1.850
-0.980
-0.980
-
-
270
-0.810
-0.810
-1.620
-1.620
-
-0.700
-0.700
-1.600
-1.600
-0.890
-0.890
-1.830
-1.830
-0.910
-0.910
-
1.8
1.8
1.9
1.9
2.3
-
2.3
2.3
2.4
2.4
2.8
-
-1.575
-1.575
-
-1.555
-1.555
VIHmax
V'Lmin VIHAmin VILAmax VEE
-3O"c
+25"c
-0.875
-1.890
-1.180
-1.515
-5.2
-0.810
+85"c
-0.700
-1.850
-1.830
-1.095
-1.025
-1.485
-1.440
-5.2
-5.2
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
Unit
mAde
"Adc
"Adc
"Adc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
V,Hmax V'Lmin VIHAmin V,LAmax VEE
..
All Inputs
-
-
-
-
-
-
-
-
-
.
9
8
8,9
-
-
8
9
8,9
-
-
-
-
-
-
n Load)
Propagation Delay
-
8
9
8,9
-
-
9
8
8,9
(Vce)
Gnd
12
12
12
12
4,5
4,5
4,5
4,5
12
12
12
12
12
12
12
12
4,5
4,5
4,5
4,5
4,5
4,5
4,5
4,5
12
4,5
Pulse In Pulse Out
6
-
j
-
Rise Time
6
-
2.7
-
2.5
-
2.9
Fall Time
'6_
6
-
2.4
-
2.2
-
2.6
-
-Individually test each input applving V I H or V IL to input under test.
2.0
2.0
2.1
2.1
2.5
-
'8+6+
t8-6+
'8+6t8-6t9+6+
t9-6+
'9+6t9-6t6+
+
-
-
-
+
-
+
ns
j
ns
ns
-
8
6
+
9
j jj
-
-
-
+
8
-
8
6
6
12
4,5
12
4,5
s:(')
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink IIERC·LlC214A2WCB or equivalent) or a transverse
...a
~
-
airflow greater than 500 linear fpm should
be maintained while the circuit is either in a
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs.
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
::J
....
::J
C
a
CERAMIC PACKAGE
CASE 620
1:~14
information section for complete thermal
8
LSUFFIX
3~2
5~
a 50-ohm resistor to -2.0 Vdc. See general
N
1~~15
data.
TEST VOLTAGE VALUES
(Volts)
"T ...
Temper.lure
.".
-JO"c
~
+25 o C
+8Sac
m
Pin
Und_
Characteristic
Symbol
Power Supply Drain Current
T...
8
MC1672L Tnt limits
+25o C
-JO"c
Min
M..
Min
"
Input Current
I.., H
0.751.., H
Logic "0"
Output Voltage
VOL
VOHA
Voltage
Logic "0"
Threshold Voltage
SWltchmg Tunes (50
PropagatIon Delay
A.seTlme
Fall Time
5.6,7
'mL
VOH
LogIC "'"
Output Voltage
Logic "'"
Thremold
3,11.13
LoatU
-1.045
·".045
-1.890
·1.890
'2+
'2_
"IndivtduaUy test each input applying VIH or V,L to input under test.
-0.875
-0.875
-'.650
-1.650
-1.065
-1.065
-0.960
-0.960
-1.850
-1.850
M..
-0.875
-0.810
-1.890
-1.850
-1.180
-1.515
-5.2
-1.485
-5.2
-0.700
-1.830
-1.095
-1.025
-1.440
-5.2
VILA tUX
VEe
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Min
M..
Unit
mAde
VIHmu
All Inputs
VILmin
VIHA min
VILA
IMX
VEE
•
(Vee l
Gnd
1,16
J.lAde
,.Ad,
1,16
-0.810
-0.810
-0.700
-0.700
/.lAde
Vd,
Vd,
1,16
1,16
1,16
-1.575
-1.575
Vd,
Vd,
-1.620
-1.620
-0.890
-0.890
-1.830
-1.830
M..
-1.555
-1.555
Min
1,16
1,16
1,16
3,'
3,'
Vd,
Vd,
-0.910
-0.910
-1.600
-1.600
Min
VIHA min
350
270
-0.980
-0.980
-1.630
-1.630
Min
t3+2+
t3-2+
t3+2_
t3-2_
t5+2+
t5_2+
t5+2_
t5_2_
••
1
Vllmin
+8SOc
0.'
VOLA
n
M..
I
VIHmu
Vd,
Vd,
1.•
1.•
1.9
1.9
2.3
2.3
2.3
2.'
2'
2.8
+
2.7
+
2.'
+
2.9
2.'
2.2
2 .•
1,16
1,16
3,'
-3.2 V
+2.0 V
Pul.ln
Pul.Out
"'
3
2
j
+
•
j j j
Max
2.0
2.0
2.1
2.1
2.'
1,16
1,16
3,'
+
•
1,16
1.16
1,16
MC1672 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@25"<:
V out to Channel "8"
Vin to Channal "A"
Coax
Input
Coax
50
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
r-------,
50
Pulse Generator
I
Coax
50
I
~
+0. 31V
~
=:J
100
a>
Power Supply Drain Current
Input Current
Symbol
Logic "1" Output Voltage
-30"1:
Under
Test
Min
-1.180
-1.515
-5.2
-1.850
-1.095
-1.485
-5.2
+85"1:
-0.700
-1.830
-1.025
-1.440
-5.2
+25"1:
TEST VOL TAGE APPLIED TO
PINS LISTED BELOW
+85"1:
Min
Max
Min
Max
Unit
-
55
-
-
-
mAde
350
'E
8
-
-
3,11,13
-
0. 751 inH
5,6,7
-
.
-1.890
-0.810
Max
'inH
linL
-0.875
+25"1:
MC1674L Test Limits
Pin
Characteristic
VIHrnax VILmin VIHAmin VILAmax VEE
-30"1:
-
270
0.5
/JAdc
uAde
VIHmax VILmin VIHAmin VILAmax VEE
..
All Inputs
,u.Ade
VOH
2
2
-1.045
-1.045
-0.875
-0.875
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
3,5
VOL
2
2
-1.890
-1.890
-1.650
-1.650
-1.850
-1.850
-1.620
-1.620
-1.830
-1.830
-1.575
-1.575
Vdc
Vdc
VOHA
2
2
-1.065
-1.065
-
-0.980
-0.980
-
-0.910
-0.910
-
VOLA
2
2
-
-1.630
-1.630
-
-
-
-1.600
-1.600
-
'3+2+
'3-2+
'3t2'3-2'5+2+
'5-2+
'5+2'5-2_
2
2
2
2
2
2
2
2
-
1.8
1.8
1.9
1.9
2.3
-
Rise Time
'6+
2
2.7
-
2.5
-
2.9
Fall Time
'6_
2
2.4
-
2.2
-
2.6
Logic "0" Output Voltage
Logic "I" Threshold Vol.age
Logic "0" Threshold Vol.age
Swi'ching Times (50
n
Propagation Delay
-
-
-
B
1,16
-
-
-
8
1,16
.
-
-
8
1,16
8
1,16
1,16
1,16
-
3,5
-
3
5
5
3
-
Vdc
Vdc
-
3,5
-1.555
-1.555
Vdc
Vdc
-
-
2.3
2.3
2.4
2.4
2.8
ns
-
(VCC)
Gnd
Load)
3
5
-
8
8
-
B
B
3,5
8
1,16
1,16
5
3
8
8
1,16
1,16
8
1,16
8
1,16
1,16
Pulse In Pulse Out
-
-
-
-
-
-
-Individually test each input applying VIH or V,L to input under test.
2.0
2.0
2.1
2.1
2.5
+
-
+
-
-
+
-
ns
-
-
+
3
2
B
1,16
ns
-
-
3
2
8
1,16
j
3
2
+
j jj
-
-
-
5
MC1674 (continued)
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C
V out to Channel
Vin to Channal "A"
Coax
t+ = t- = 1.5 ±. 0.2 ns
All input and output cables to
the scope are eQual lengths of
50-ohm coaxial cable.
50
Input
,-
Pulse Generator
--
I
---,
Coax
50
1
~
~
+1.11V~i
+0.31 V
o----J
(i)
Apply Vin to input A
and +1.11 V to input B
@
Apply Vin to input A
100
~
~
~
1
I
L _____ ...J
and +0.31 V to input B
Unused outputs connected to
8
50-ohm resistor to ground.
PROPAGATION DELAY
J,-----+1.11 V
-,.::.=::.........:."1------ +0.31 V
@
V out
4-67
100
"e"
MECL III MC1600 series
BI-QUINARY COUNTER
MC1678
The MC1678 is a four-bit counter capable of divideby-two, divide-by-five, or divide-by-lO functions_ When
used independently, the divide-by-two section will toggle
at 350 MHz typically, while the divide-by-five section will
toggle at 325 MHz typically. Clock inputs trigger on the
positive going edge of the clock pulse.
Set and Reset inputs override the clock, allowing asynchronous "set" or "clear". I ndividual Set and common
Reset inputs are provided, as well as complementary outputs for the first and fourth bits. True outputs are avai lable
at all bits.
A = 2.40
DC Input Loading Factor
C1 '" 0.77
C2=1.23
5
=
1.00
SO
14
DC Output Loading Factor == 70
Power Dissipation == 750 mW typ
fTog
= 350
MHz typ
00
S1
13
10
Q1
11
52 3
53 7
02 4
03 6
Cl
Clock 15
R
Reset
9
o----l---L-t==t===!~~==:;t====~~-J
0.0
12
2
C2
03 5
CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN
100
K ~
125
I~~~
02
100
300
100
I
K
---x- 1:r~:t- H::
~>-
l.,
,)""
~
""
~~
~
Q
-<~~r<
Cl
60
1235
I-- I--
C2
s
~
R
50
50
50
50
50
50
k
k
k
k
k
k
560
1.3 k
'r
~
1.3 k
~
675
(,05
J
100
bV EE
See General I nformation section for peckaging.
4-68
~
~
~
H::
325
675
50
1.5 k 1 k 1 k
1.5 k
i5
MC1678 (continued)
COUNTER TRUTH TABLES
BCD
BI-QUINARY
(Clock connected to C1
(Clock connected to C2
and 0.0 connected to C2)
R-S
and 53 connected to C 1 )
COUNT
ao
a1
a2
a3
COUNT
a1
a2
03
00
C
R
5
a,,+1
0
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
0
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
¢
¢
¢
¢
L
H
L
H
L
L
H
H
an
1
2
3
4
5
6
7
8
9
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
H
L
L
L
L
H
H
1
2
3
4
5
6
7
8
9
L
L
H
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
H
L
L
H
H
H
¢ '" Don't Care
NO:::: Not Defined
COUNTER STATE DIAGRAM - POSITIVE LOGIC
ao connected to C2
Clock connected to C2
o
FIGURE 1 - TOGGLE FREOUENCY TEST CIRCUIT
-3.2 Vdc
+2.0 Vdc
Coax
Coax
Coax
50
50
50
15
Clock Input
I
14
100
10
0,.,
3
C1
00
C2
03
50
51
100
52
53
50
R
01
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
03
02
11
Open
4-69
4
100
H
H
NO
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink (I ERC·LlC214A2WCB or equivalent) or a transverse
--""""
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs.
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
a 5O-<)hm resistor to -2.0 Vdc. See general
airflow greater than 500 linear fpm should
information section for complete thermal
be maintained while the circuit is either in a
data.
I
Power Supply Drain Current
Input Current
I
Symbo'
'E
I,n H
I
_lODe
Min
Min
.:...t
0
r
M..
Min
M..
9
2
Unit
200
mAde
1.00
mAde
0.70
0.45
0.45
0.5
05
0.5
3,7,10,14,15
.jOo
+
+
VOH
5,12
~
4,6,11,'3
-1.045
-1.045
-0.875
-0.875
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0700
Vd,
Vd,
Logic "0"
Output Voltage
VOL
5,12
~
4,6,11,13 1
-, .890
-1.890
-1.650
-1.650
-1.850
-1.850
-1.620
-1.620
-1.830
-1.830
-1 575
-1.575
Vd,
Vd,
VOHA
5,12
~
6,8,11,134
-1.065
-1.065
VOLA
5,12
4,6,13,16
r l'1h~~~~ld
Voltage
@
Q)
-0.980
-0.980
t15+12+
115+13+
t2+11+
t2+4+
12+6+
t2+5+
12
13
115+12'15+1313+11t2+4_
t2+612+5-
12
13
Set Delay
114+13+
114+12_
13
12
vlHAmin
-1.890
-1.180
VILAlNx
-1.515
-0.810
-".850
-1.095
-1.485
-5.2
-0.700
-1.830
-1.025
-1.440
-5.2
-1600
-1.630
-1.630
10
29
2.9
3.2
-I 555
-1.555
-1.600
10
2.7
2.7
30
1.0
!•! !
! ! 1
"
4
6
5
1.0
"
4
6
5
29
2.9
3.2
1.0
+
VIHmlllIl
Vllmin
VIHAmin
VllAmillil
9
2
15
::J
::J
c:
(!)
Co
+
2.7
2.7
3.0
+
1.0
+
31
31
3.4
+
1
n,
1
Gnd
8
1.16
8
1.16
8
3.7.10,14
,
1,16
1,16
9
116
9
1,16
3,7,10,14
1 16
Vd,
Vd,
3.1
3.1
3.4
VEE
+ +
+
Vd,
Vd,
-0.910
-0.910
AC C.. ,uteristics
Clock Delays
50 n Loads
vilmin
/oIAdc
Logic "1"
Output Voltage
logic "1"
Threshold Voltage
...
vEE
-5.2
vlHmu
-0.-875
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+8S o C
+2SoC
M..
9
2
15
I
'"00
n0
TEST VOLTAGE VALUES
MC1678l Test limits
-lOoe
T ...
3,7,10,14
lin L
~
0)
@T ...
Temper.tur.
Pin
Un.r·
I
0
CERAMIC PACKAGE
CASE 620
+2Soc
+8S oC
ChI,.cterittic
s:
3.7,10,14
1,16
9
1 16
1,1'6
1,16
3,7,10,14
Pulse In
Pulte Out
15
15
2
2
2
12
13
-3.2Vde +2.0Vde
8
!
"
15
15
2
2
2
2
12
13
8
t
"
4
6
5
1,16
t
1.16
1
2.0
2.0
3.9
3.9
2.0
2.0
3.7
3.7
2.0
2.0
41
41
14
14
13
12
1,16
1,16
Reset Delay
t9+12+
19+13_
12
13
2.0
2.0
3.9
3.9
2.0
20
3.7
3.7
2.0
2.0
4.1
4.1
1,16
1,16
t13+
'12+
13
12
1.0
1.0
2.9
2.9
1.0
1.0
2.7
2.7
1.0
10
3.1
3.1
9
9
15
15
12
13
AiseTime
13
12
1.16
1,16
Fall Time
t13112_
13
12
1.0
1.0
2.8
2.8
10
10
2.6
2.6
1.0
1.0
30
3.0
15
15
13
12
1,16
1,16
13 @
6 @
260
250
M8lIimum Toggle Frequency
50 n load
't
't
300
275
260
250
MH,
MH,
1,16
1,16
-Individually apply VIH or Vll to mput under test.
ill
Reset all four flip, flops by applymg PA to pin 9.
@
Set all four fllp.flops by applYing PA 10 pins 3, 7, 10,
and 14 Simultaneously.
@
Reset all four flip-flops by applYing PA, to pin 9.
@)
®
Set all four fllp·flops by applYing PA 10 pms 3. 7, 10,
and 14 simultaneously.
PA~
See Figure 1 for toggle lesl circuit
VIL
MC1678(continued)
APPLICATIONS INFORMATION
With the addition of a single gate package, the Me 1678 wi II
count in a fully synchronous mode, as shown below.
50 14
1/2 MC1662
00 13
S1
10
01
11
52 3
02 4
53 7
03 6
Clock
15
»-----o--iC1
R
Reset
9
o----JL---J--1=====t======~~::::t:::::::~--~
Cio 12
2
C2
03 5
4-71
MECL III MC1600 series
DUAL 4-5-INPUT
OR/NOR GATE
MC1688
Advance InforIllation
The MC1688 is a dual 4-5 input OR-NOR
gate. All inputs are terminated by a 50 k ohm
resistor to VEE eliminating the need to tie
unused inputs low.
POSITIVE LOGIC
8~
NEGATIVE LOGIC
9
7
10
6
8¥
11
9
7
10
6
11
13~
14
15
16
13~
14
2
15
3
2
3
16
1
tpd "" 0.8 ns typ
1
VCC1
~
Po = 125 mW tvp/pkg (No Load)
Output Rise and Fall Times
(10% to 90%) 1.7 ns
(20% to 80%) 1.1 ns
4
VCC2 = 5
VEE = 12
CIRCUIT SCHEMATIC
4
OR 6
------+-- - - 15 (3)
12
Vaa
L
P D '" 220 mW typ/pkg (No load)
9(13)
Full Load Current, I L ::: -25 mAde max
Number at end of terminals denotes pin number for L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).
CIRCUIT SCHEMATIC
(6)
(7)
(2)
(5)
2
3
14
1
(4)
(3)·
15
16
VCC2
100
100
100
100
100
350
100
Vaa
9
(13)
1958
365
4
(8)
5
(9)
7
(11)
6
(10)
11
(15)
10
(14)
13
(1)
8
(12)
12
(16)
Number at and of terminel denotes pin number for L package (Case 620),
Number in parenthe$is denotes pin number for F package (Case 6501.
Sea General I nformation section for packaging information.
4-81
2k
s
...
en
ELECTRICAL CHARACTERISTICS
(')
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been establ ished. Air flow greater than
500 linear fpm should be maintained while
the circuit is either in a test socket or is
U)
N
n
o
:::J
mounted on a printed circuit board. Test
~,
procedures are shown for selected inputs
:::J
C
~
and selected outputs. The other inputs
and outputs are tested in a similar manner.
Outputs are tested with a 50-ohm resistor
to -2.0 Vdc. See general information
section for complete thermal data.
(1)
0..
F SUFFIX
CERAMIC PACKAGE
CASE 650
:~6
11~
10~7
14~
15~2
1;~3
Vaa
.".
L1
3
cD
I\J
TEST VOLTAGE VALUES
@Test
VIH max
VIL min
VIHA min
VILA max
Vaa
VEE
-0.875
-1.890
-1.180
+2SOc
-0.810
-1.850
-1.095
-1.515
-1.485
From
Pin
+8SoC
-0.700
-1.830
-1.025
-1.440
13
~
~
Temperature
_30°C
MC1692F Test Limits
Symbol
Pin
Under
Test
Power Supplv Drain Current
'E
12
50
mAdc
Input Current
I in
8
250
J.lAdc
I nput Leakage Current
'R
100
J.lAdc
Characteristic
logic "1" Output VOltage
LogIc "0" Output Voltage
_JODC
Min
Min
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
+85~C
+25"<:
Max
Max
Min
Max
Unit
VIH max
VOH
-1.045
-0.875
-<).960
-0.810
-0.890
-0.700
Vdc
1.11,14
VOL
-1.890
-1.650
-1.850
-1.620
-1.830
-1.575
Vdc
8
Logic "1" Threshold Voltage
VOHA
-1.065
Logic "0" Threshold Voltage
VOLA
Reference Voltage
SwitchIng Times (50
Propagation Delay
RIse Tune
Fall Time
n Load)
Vaa
t8-6+
t8+6-
'6+
'6-
-1.630
13
6
6
-1.600
Vaa
VEE
(VCC)
Gnd
1,8,11,14
9,10,15,16
12
4.5
1,11,14
9,10,15,16
12
4.5
1,11,14
9,10.15,16
8,12
4,5
VIL min
VIHA min
VILA max
9,10,15,16
12
4.5
1,11,14
9,10,15,16
12
4.5
Vdc
1,11,14
9,10,15,16
12
4,5
-1.555
Vdc
1.11,14
9,10,15,16
12
4.5
Vdc
9,10,15,16
12
4,5
12
4.5
-0.910
-0.980
-5.2
1.375
1.275
-1.35
-1.25
1.30
1.20
Min
Max
Min
Max
Min
Max
Pulse In
Pul.Out
a
6
9,10,15,16
~
~
~
1.6
1.8
1.5
1.7
1.7
1.9
2.2
2.2
2.1
2.3
2.1
2.3
~
~ I~
s:
(")
....
ELECTRICAL CHARACTERISTICS
en
This MECL III circuit has been designed to
meet the dc specifications shown in the
test table. after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink OERC-UC214A2WCB or equivalent} or a transverse
airflow greater than 500 linear fpm should
be maintained while the circuit is either in a
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs.
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
a 5O-ohm resistor to -2.0 Vdc. See general
information section for complete thermal
data.
CD
to.)
Cl
o
:::J
!:.',
:::J
-
C
(I)
a.
LSUFFIX
CERAMIC PACKAGE
CASE 620
:=.:t>--2
~=:::t>-3
"'"
~
10~'4
11~
13
12
=:::::r>--vaa
Symbol
Pin
Und.r
T ...
IE
8
I nput Current
lin
4
I nput Leakage-Current
Logic "1" Output Voltage
'R
4
VOH
2
Chllracteristic
Power Supply Drain Current
Logic "0" Output Voltage
Logic" I" Threshold Voltage
LogiC "0" Threshold Voltage
Reference Voltage
VOL
2
VOHA
VOLA
2
Vaa
9
Propagation Delay
Rise Time
_
Fall Time
2
2
t4_2+
t4+2-
2
'2+
t2 ___
-
2
V'H max
Vil min
VIHA min
VILA m••
Vaa
VEE
-1.890
-1.850
-1.180
-1.095
-1.515
-1,485
From
Pin
~,2
+25"<:
-0,875
-0,810
+8SGe
-0.700
-1.830
-1.025
-1,440
Temper.ture
_lOGe
Lg
MCl692l T.t Limits
_lOGe
Min
-1.045
-1.890
-1.065
-0.875
-1.650
Min
Ma.
Min
Ma.
Unit
-
50
-
-
mAd,
-0,960
-1.850
VIHmb
VIL min
VIHA min
-
4
4,7,10,13
7,10,13
250
#Adc
100
J,lAdc
-0.810
-O,B90
-0,700
Vd,
7,10,13
-1.620
-1,830
1.575
Vd,
•
-0.980
-
-0.910
-
Vd,
-
-1.600
-
-1.555
Vd,
-
1.375
1.275
-1.35
-1.25
1.30
1.20
Vd,
-
Min
Ma.
Min
Ma.
Min
Ma.
-
1.6
1.8
-
1.5
1.7
2.2
-
2.1
2.3
-
-
2.1
'-----
~
-
1.7
1.9
2.3
-
4
7,10,13
7,10,13
-
7,10,13
4
-
-
n,
~
VILA m ••
7,10,13
-1.630
-
9
I
1---0-::-
~
~,2
I
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
+8S GC
+25"<:
Ma.
-
2
Switching Times (SO H Loadl
TEST VOLTAGE VALUES
In...
15
-
Vaa
VEE
Gnd
5,6,11,12
8
1,16
5,6,11,12
5,6,11,12
B
1,16
5,6,11,12
B,'
8
5,6,11,12
8
4
5,6,11,12
8
1,16
-
5,6,11,12
8
-
5,6,11,12
8
1.16
1,16
B
1,16
Pul.ln
Pul.Out
4
2
5,6,11,12
~
~
~
--
'--
1,16
1,16
1,16
~ ~
MC1692
(continued)
the differential line receiver inputs of the MC1692. Illustrated in
Figure 2 is the sending and receiving waveforms at a data rate of
400 megabits per second over an 18 foot twisted pair cable. The
APPLICATIONS INFORMATION
waveform picture of Figure 3 shows a 5 nanosecond pulse being
propagated down the 18 foot line. The delay time for the line
is 1.68 ns/toot.
The MC1692 Quad line receiver is used prlmanly to receive
data from balanced twisted pair lines, as Indicated In Figure 1.
The MC1692 may also be applied as a high frequency schmitt
trigger as illustrated In Figure 4. ThiS Circuit has been used in excess of 200 MHz. The MC1692 when loaded Into 50 ohms will
produce an output rising edge of about 1.5 nanoseconds.
The line is driven with a MC1660 OR/NOR gate. The MC1660
is terminated with 50 ohm resistors to -2.0 volts.
A t the end of
the tWIsted pair a 100 ohm termination resistor is placed across
FIGURE 1 - LINE DRIVER/RECEIVER
FIGURE 2 - 400 MBS WAVEFORMS
FIGURE 3 - PULSE PROPAGATION WAVEFORMS
Sending
End
Sending
End
2 ns/cm
5 ns/cm
Receiving
End
ReceiVing
End
VEE
= -5.2
V
MC1692
-1.3V~ )-----'-1
3
FIGURE 4 - 200 MHz SCHMITT TRIGGER
9
500
0.01
0.01
J.lF
J.lF
50
E--y1
100
VTT = -2 V
4-84
MECL III MC1600 series
4-BIT SHIFT REGISTER
MC1694
The MC1694 is a 4-Bit register capable of shift rates up
to 325 MHz (typical). This shift register operates in the
shift·right mode, accepting serial data at either data input
01 or 02. A master reset and individual set inputs override
the clock allowing asynchronous entry of information.
FLIP-FLOP TRUTH TABLE
Inputs
D C R S
Output
an
0 0 a a
a a a I
a a I a
a a I I
a I a a
a I a I
a I
a
a
a a a
a a
a
a
a
a a
1 1 a 1
1 1 1 a
°n-l
I
a
a
, ,, , a
,,
, ,
,, ,, , a
,,
,
1
1
1
I
LOGIC DIAGRAM
°n-1
VCC,: 1
VCC2: 16
VEE: 8
50
2
00
13
S1
Q1
10
12
52
3
02
53
6
4
03
5
1
a
01
02
1
·Output State
14
15
Undefined
DC Input Loading Factors
Reset = 2.5 Set = 1.0
Clock
= 1.6
Data
,,:::=::=j====j==~=:t=~
Clock
Reset
97 0
__J
= 0,9
DC Output Loading Factor
=
70
Total po ......er Dissipation = 750 mW typ/pkg
Shift Frequency = 325 MHz typ
FLIP-FLOP ELEMENT CIRCUIT SCHEMATIC
114 OF CI RCUIT SHOWN
o·
100
~
>-
100
300
pc
~rl ~ >- ~>125
01
02
100
100
K-
Il
>
~
~
I----"" r---
~~
0
~~
C
60
1235
f-- f-R
50 50 50 k
k
k
50 k 50 560
k
1.3k
~
1.3 k
[os
~
~k
675
bv EE
S.. General I nformation section for packaging.
4-85
~
~
)-
r----rt
s
325
675
~
1.5 k
I k
1.5 k
MC1694 (continued)
ELECTRICAL CHARACTERISTICS
so
'1
This MECL III circuit has been designed to
meet the de specifications shown in the
test table. after thermal equilibrium has
been established. The package should be
housed in a suitable heat sink (lERe-LIC214A2VVCB or equivalent) or a transverse
01
14
02
15
aD
51
01
52
Q'1
S3
03
13
10
12
:]
4
6
5
L SUFFIX
airflow greater than 500 linear fpm should
CERAMIC PACKAGE
CASE 620
Clock
be maintained while the circuit is either in a
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs,
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
a 5O.-ahm resistor to -2.0 Vdc. See general
information section for complete thermal
data.
TEST VOLTAGE VALUES
@Test
Temperature
_30°C
Power Supply Drain Current
Input Current
Symbol
Logic'
-3O"c
M,n
1m H
LogiC "0' Output Voltage
VOH
M"
M,n
7
0750
2,3,6,10
14,15
OS
-1.485
-5.2
+85 0C
-0700
-1830
-1.025
-1440
-52
Unit
VILmin VIHAmin VILAmu
t
-1045
-0.875
-0 960
-0810
-0.890
-0 700
-1650
-, 850
-1620
-1830
-1575
V
®
1,16
1,16
CD Reset all four flip flops bv applvmg PAl
to pin 9
and 10 SImultaneously
Reset all lour flip Ilops bV applVIng PA2 to Pin 10
PA1~~II~
4-86
X
X
-3,2 V
+2,QV
8
8
1,16
1,16
1,16
1,16
1,16
1,16
30
~ Set all four fl'p·flops by applVIng PAl to PinS 2,3,6,
Q)
7
3.1
250
•
1.16
1,16
Pulse In Pul.Out
t9+X-
1.16
• •
(j)
AC Characteristics
AlseTlme
Gnd
1.16
/JAde
-0.980
VEE
8
+
05
-, 630
VIHrm.
mAde
LogiC "0' Threshold Voltage
LogiC
-1.095
mAde
05
0.5
05
7.•
4,5,12,13
-1850
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW:
M"
200
, 0
2,3,6,10
14,15
' Output Voltage
M,n
VEE
52
-0 810
+8S 0C
+2SoC
Mo,
'E
Ion L
,
.. ,
T...
VILmin VIHAmin VILAma.
-1.890
-1.180
-1.515
+ZSoC
MC1694L
Pin
Undflf
Chlr.elenstle
VIHma.
-0 875
MH,
@)Set all four fl,p·flops bV applVlng PA2 to pins 2,3,6,
and 14 Simuitaneousiv
PA2
-----c=~:~:
® See Figure 1 tor shift freQuency test cirCUit.
MC1694 (continued)
FIGURE 1 - SHIFT FREQUENCY TEST CIRCUIT
V out
+2.0 Vdc
AIJ input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
- 3.2 Vdc
Coax
II'F
I'FI
0.1
0.1
1
50
168
50
Clock Input
100
100
100
1/4 MC1662
4-87
COMPATIBLE
INTEGRATED CIRCUITS
5-1
\ - ._ _ _ _ _ _D_U_A_L_S_E_N_S_E_A_M_PL_I_F_IE_R----'l
MC1543L
DUAL MECL
CORE MEMORY
SENSE AMPLIFIER
INTEGRATED CIRCUIT
MONOLITHIC DUAL MECL CORE
MEMORY SENSE AMPLIFIER
MONOLITHIC SILICON
EPITAXIAL PASSIVATED
· .. a dual de coupled sense amplifier providing output levels compatible with emitter-coupled logic levels_ The MC1543L offers
adjustable threshold and excellent threshold stabilitv over a wide
range of power-supply voltage variation_
•
Input Threshold - Adjustable from 10 to 40 mV
(positive or Negative Signals)
•
Both OR and NOR Outputs Available
14
•
Low Power Dissipation
•
Threshold Insensitive VCC or VEE Voltage Variation
•
Each Amplifier is Separately Strobed
CERAMIC PACKAGE
CASE 632
TO·116
CIRCUIT SCHEMATIC
Vee
OUTPUTS
,
No,,,,"Hy
lOVO
6
, "
13
GilD
VE(
"U"
frlg,,,,oUy
HIGH
I
(1"~!~HOlO
v,.,
AOJUST)
,
,
OUTPUTS
J"l.
frlo,m.lI.
".
See General Information section for packaging
5-3
MC1543L (continued)
MAXIMUM RATINGS
ITA = +25 0 C unless otherwise noted.l
Rating
Povver SupplV Voltage
Symbol
Value
Unit
VCC
VEE
+10
-10
Vde
Vde
VID
±5.0
Vde
VICM
±5.0
Vde
IL
25
mA
1000
6.7
mW
mW/oC
°c
°c
Differential Input Voltage
Common-Mode Input Voltage
Load Current
Po
POlNSr Dissipation (Package Limitation)
Ceramic Dual-tn-Line Package
Derate above T A
=
+2S o C
Operating Temperature Range
TA
-55 to +125
Storage Temperature Range
T"g
-65 to +150
ELECTRICAL CHARACTERISTICS
lEach Amplifierl IVCC = +5.0 Vdc ±5%, VEE = -5.2 Vdc ±5%, Vref = 0.54 V 1.1%,
TA = +25 0 C unless otherwise noted.)
Fig.No.
Symbol
Min
Typ
M..
Input Threshold Voltage
8
VTH
17
20
23
mV
Power Supply Currents
(V2= V3= Vll = V12= V14 =01
6
6
ICC
lEE
-
-
9.5
26.5
12
33
mAde
mAde
Input Bias Current
7
liB
10
~Ade
7
110
-
3.5
Input Offset Current
0.05
0.5
!lAdc
Output Voltage High
9
VOH
-0.85
-0.8
-0.67
Vdc
Output Voltage Low
9
VOL
-1.7
-1.46
Vdc
Strobe Threshold Level
10
VST
Strobe Input Current High
10
ISH
Strobe Input Current Low
10
ISL
-
Input Common Mode Range
14
VCMA
3.0
-
10-40
-
mV
185
230
mW
10
40
"A
ns
Characteristic
Unit
-1.30
-
Vde
25
50
,."Adc
0.01
0.1
4.0
-
"Ade
Vdc
Input Threshold Aange(by varying Vrefl
8
VTHA
Power Dissipation
6
Po
Aeference Supply Input Current (Pin 131
6
'ref
-
-
28
35
16
20
ns
18
30
ns
SWITCHING CHARACTERISTICS
Propagation Delay (Input to Output)
1
tlO
Propagation Delay (Strobe to Output)
12
tso
Strobe Release Time
12
tSA
-
Recovery Time (Differential-Model
(ein = 400 mVdcl
13
tDA
-
10
15
ns
Aecovery Time (Common-Model
(ein = 3.0 Vdel
14
tCMA
-
3.0
15
ns
Strobe Width Minimum
12
ts
-
8.0
-
ns
8
VTH
18
15
21.5
18.5
25
22
TEMPERATURE TESTS (-55 0 C to +125 0 CI
Input Threshold Voltage
TA - -55 0 C
TA = +125 0 C
Input Bias Current
Input Offset Current
mV
7
liB
2.2
7.0
20
"Ade
7
110
0.02
'0.1
1.0
"Ade
5-4
MC1543L (continued)
EQUIVALENT CIRCUIT
INPUTS
REFERENCE 13
VOLTAGE
INPUTS
Il
STROBE
TYPICAL CHARACTERISTICS
(VCC
= +5.0
Vdc. VEE
= -5.2
Vdc. V re, set for 20 mV Threshold. TA
noted.1
45
4
40
!
2
= +25 0 C unle.. otherwise
FIGURE 2 - TYPICAL INPUT THRESHOLD
vorsus REFERENCE VOL TAGE
FIGURE 1 - TYPICAL INPUT THRESHOLO
v.rsus TEMPERATURE
\
:>
.§ 35
r--
0
c
~
------- -r--"---
8
0
~
'"i=
~
----
~
~
+25
25
+50
+75
+100
\
I
T
......
20
................
15
5.0
---- r- -
~
I
o
+125
II
\.
25
> 10
16
-55 50
30
I
Recommended voltage tor 20 mV _
Threshold: Vref:: 0.540 Volt
0.2
TA. AMBIENT TEMPERATURE lOCI
0.4
0.6
0.8
1.0
1.2
1.4
Vref. REFERENCE VOLTAGE (VOLTSI
FIGURE 38 - TYPICAL INPUT THRESHOLD versus VEE
FIGURE 3A - TYPICAL INPUT THRESHOLD versus VCC
4.----------.------------r---------~
4
:>
2
.§
=:
c
:r
2~----------+_-----------+----------~
0
;=~
""
ii!
O~
I~~~~~~--~------------~~~~====~::j
8
~
8~------------~------------~------------_1
~
16
4.5
5.0
5.5
6.0
~~f:,.5-------..,51::.0-------..,.5L,-.5-------::'-6.0
6.5
Vee. POSITIVE SUPPL Y VOLTAGE IVOL TS)
VEE. NEGATIVE SUPPLY VOLTAGE (VOLTS)
5-5
MC1543L
(continued)
TYPICAL CHARACTERISTICS Icontinuedl
(Vee = +5.0 Vdc, VeE = -5.2 Vdc, Vref set for 20 mV Threshold. T A = +25 0 C unless otherwise noted.)
FIGURE 4 - TYPICAL INPUT THRESHOLD
varsus INPUT PULSE WIDTH
FIGURE 5 - INPUT·OUTPUT TRANSFER
CHARACTERISTICS lona outputl
-0. 5
0
"NOR"! Output
:;
E
u;
;;; 50
\
'"
~
o
> 40
:J
~ 30
%
~
.c
o
~ -1 0
w
~
~
>>~
:;
'"
~
o
"'-.
20
...>
~
~ -1. 5
r---.
o
---f ~O.5 mr Transitior Width
:>
-2. 0
-40
10
o
10
20
40
30
t. INPUT PULSE WIDTH
50
60
30
20
losl
.10
10
+ 20
t
'in. INPUT VOLTAGE ImVI
TEST CIRCUITS
(Vee = +5.0 Vdc, VEE'" -5.2 Vdc, Vref
FIGURE 6 -
=
0.54 V, TA = +25 0 C unless otherwise noted.!
POWER SUPPL Y CURRENT DRAIN
FIGURE 7 - INPUT BIAS CURRENT
INPUT OFFSET CURRENT
+5.0 Vdc
+5.0 Vdc
A
13
Unless otherwise specifier!
Vref should beset for
20 mV threshold
IV re !" 0.4 VI
14
12f-o--+
111-0--....
101-0--"
A
-52 Vdc
FIGURE 8 -
INPUT THRESHOLD LEVEL
FIGURE 9 -
OUTPUT VOLTAGE LEVELS
+5.0 Vdc
to voltmeter
5.1k
990
±.O.l%
11
50
51
12
10
!O.l%
-5.2 Vdc
to voltmeter
5-6
30
.
40
MC1543L (continued)
TEST CIRCUITS (continued I
FIGURE 10 - STROBE THRESHOLD LEVEL
STROBE INPUT CURRENTS
FIGURE 11 - PROPAGATION OELAYINPUT TO OUTPUT
Ito dual-trace
oscilloscope)
5.1 k
51
25 mV
INPUT
FIGURE 12 - PROPAGATION OELAY - STROBE TO
OUTPUT and STROBE RELEASE TIME
+5.0 Vdc
5.1 k
<1%
51
<1%
FIGURE 13 - OIFFERENTIAL MOOE RECOVERY TIME
(See definition section)
Vret
+5.0 Vdc
(to dual·trace
ostilloscope)
(to oscilloltop,)
11
3
12
-=
-=
-5.2 Vdc
Ito dUII·lrm
oscilloscope)
-0.7V
DIFFERENTIAL 400 mV
INPUT
-1./V
STROBE
-....;.:;"----.,f')
DUffUT_________________________
5-7
-1./ V
MC1543L
(continued)
TEST CIRCUITS (continued I
FIGURE 14 - COMMON MOOE RECOVERY TIME
COMMON MOOE INPUT RANGE
IS.8 definition section.
+5.0 Vdc
Vref
(to ostilloscopel
-5.2 Vdc
COMMON
MOOE
INPUT tPLH
3.0 V
0
10 no
STROBE
-1.7 V
i
"VT,....I------
OUTPUT
100mV
DEFINITIONS
tso Propagation Delay. Strobe I nput to Amplifier Output - The
time required for the amplifier output pulse to achieve 50%
110 Input Offset Current - The difference between amplifier
input current velu .. IlIA - 12AI or 111B - 12BI·
of its final value referenced to 50% of the strobe input pul.
ISH Strobe High Current - The amount of input current when
at pins 4 or 10.
the strobe pin il grounded.
tSR Strobe Release Time - The time required for the output to
change to 50% of its swing after the strobe reach.. 50% of
its level going low. A dc level of 50 mV is the input signal.
ISL Strobe Low Current - The leakage current when the strobe
input il tied to the _tive .. pply.
Po Power Oillipetion - The amount of power dissipated in the
unit.
leMR Common-Mode Recovery Time -
veMR
The minimum time by
Maximum Common-Mode Input Range - The common-mode
input voltage which causes the output voltage level of the
amplifier to change by 100 mV (strobe high).
which the strobe input may follow the high level common
mode Input "MI without elusing 8 signal to appear at the
amplifier output.
VOH Output Voltage High - The high·leval output voltage It pinl
6 and B with no input - or at pins 5 and 9 with Input
abova threshold.
tOR Differential-Mode Recovery Time - Differential recovery
time. the minimum time by which thl strobe input may
follOW the high .....1 differential input lignal without cauling
a . .nal to 8PPMr at tha amplifi.. output.
VOL OutPUt Voltage Low - Tha low·level output voltage 81 pinl
5 and 9 with no input - or at pinl 6 and 8 with input above
threshold.
tlO Pro-,Ion Oalay. Ampllfi.. Input to Ampliflar Output The time required for the amplifier output 10 reach 50'J1. of
III flM! vel . . . . ref..- to lim' of tha level of tha pUl.
inpUt.(Amplifi.. input· 26% over set threshold or approxi·
mately 26 mVdc.)
\1sT Strobe Threshold Level - The voltage It which the IIrobe
turns the 8mplifier to the ON ltate.
VTH Input Threshold - Input pul. amplitude .t pins 2,3.11. or
12 thet ceu_ the ..utpUt gatl to just reach ill new vel....
VOL or VOH·
IS Strobe Width - The amount of time the strobe must be high
to " I n a IMn output. Minimum strobe width ilth81 min-
VTHR Input Threshold Ringe - The maximum lPI"eed of input
threshold level that can be Ittained by _ying tha thrnhold
voltage reference. Vrof.
Imum time __ Ired to cau. the output to complete a full
..tng VOL 10 VOH or VOH to VOL.
5-8
MC7900C
l . . __
N_E_G_A_T_I_V_E_V_O_L_T_A_G_E_R_E_G_U_L_A_T_O_R_S---J
Series
MC7900C SERIES THREE-TERMINAL
NEG.ATIVE VOLTAGE REGULATORS
THREE-TERMINAL
NEGATIVE FIXED
VOLTAGE REGULATORS
The MC7900C Series of fixed output negative voltage regulators
are intended as complements to the popular MC7800C Series devices.
These negative regulators are available in the same seven-voltage
options as the MC7800C devices. In addition, two extra voltage
options commonly employed in MECL systems are al!D available
in the negative MC7900C Series.
Available in fixed output voltage options from -2.0 to -24 volts,
these regulators employ current limiting, thermal shutdown, and
safe·area compensation - mak ing them remarkably rugged under
most operating conditions. With adequate heat·sinking they can
deliver output currents in excess of 1.0 ampere.
MONOLITHIC SILICON
INTEGRATED CIRCUITS
• No External Components Required
• Internal Thermal Overload Protection
• Internal Short·Circuit Current Limiting
K SUFFIX
METAL PACKAGE
CASE 11
(TO·3 TYPE)
• Output Transistor Safe·Area Compensation
• Packaged in the Plastic Case 199·04
(Pin Compatible with the VERSAWATTt or TO·nO)
Or Hermetic TO-3 Type Metal Power Package
SCHEMATIC DIAGRAM
P SUFFIX
PLASTIC PACKAGE
CASE 199-04
Pin 1 GNO (8)
Pin 2 Output (E)
Pin 3 Input (e)
Heat sink surface connected
to pin 3.
.---+--1-0 v 0
STANDARD APPLICATION
0.3
A common ground il required between the
input and the output volta" ••. The input voltege mUlt remain typicallv 2.0 V more negative
even during the high point on the input ripple
voltage.
xx '" these two digit$ of the
type number indi-
cate voltage .
• '" Cin i$ required if regulator i$ located an
appreciable distance from power supply
filter.
DEVICE TYPE/NOMINAL OUTPUT VOLTAGE
MC7902C - 2.0 VolU
MC7906C - 6.0 Volts
MC7905C - 5.0 Volts
MC790S.2C - 5.2 Volt,
MC7908C - 8.0 Volu
MC7912C - 12 Volts
MC7915C - 15 Volt'
MC7918C - 18 VOlts
MC7924C - 24 Volts
5-9
•• = Co
improves stability and transient respon$e.
MC7900C Series (continued)
MC7900C Series MAXIMUM RATINGS IT A = +25 0 C unlessotherw"e noted I
Rlting
Symbol
Input Voltage (2.0 V - 18 VI
(24 VI
Value
Power Dissipation and Thermal Characteristics
Plastic Package
TA = +250 C
Derate above T A = +2SoC
Po
Watts
mW/oC
°C/W
15
SOO
2.0
Watts
mW/oC
2.S
28.6
35
Watts
mW/oC
°C/W
mW/oC
°JA
TC = +2SoC
Derate above TC = +9SoC (See Figure 1)
Po
1/0JC
Thermal Resistance. Junction to Case
Vdc
2.0
20
50
1/0JA
Thermal Resistance. Junction to Air
Unit
-35
-40
Vin
°JC
°C/W
Metal Package
TA = +250 C
Derate above T A = +250 C
Po
1/0JA
Thermal Resistance, Junction to Air
°JA
TC = +2SoC
Derate above T C = +6SoC
Po
Storage Junction Temperature Range
Operating Junction Temperature Range
MC7902C ELECTRICAL CHARACTERISTICS IV
Characteristic
Output Voltage (TJ
°JC
15
250
4.0
T stg
-20 to +150
°c
TJ
Oto +125
°c
1/0 J C
Thermal Resistance, Junction to Case
'"
- 10 V
'a
=
500 rnA OOC
«
0.1
50
75
125
100
NO HEAT
SINK
~ 1. 0
F"== i==NO HEAT SINK
25
INFINITE
HEAT SINK
~
(5 5.0
I-=::;; C-
2.0
ffi
L-
or--
o
;::
~ r--
CI<
f
....
50
:t
Q
;
i::
iz
150
--
'"
"
=
IIJOCJW
HEAT SINK-
"
oI
+25
+50
+75
+100
+125
+150
TA, AMBIENT TEMPERATURE 1°C)
TA. AMBIENT TEMPERATURE 1°C)
FIGURE 3 - PEAK OUTPUT CURRENT AS A FUNCTION OF
INPUT·OUTPUT DIFFERENTIAL VOLTAGE
FIGURE 4 - RIPPLE REJECTION AS A FUNCTION
OF FREOUENCY
2. 5
100
Vin=-tl V
H++H1+1tH++lfttill-+++-t-tttttt- Vo • -S.O V
/1----.
0
....... i'..
If
;
"
5
z
0
~
"r-..
"
....
.......
~
S.O
3.0
9.0
12
15
21
IB
60
....
40
i:
"'
........
::0.
o
o
10·20 mA
80
24
27
"
20
0
10
30
100
FIGURE 5 - RIPPLE REJECTION AS A FUNCTION OF
OUTPUT VOLTAGES
lOOk
FIGURE 6 - OUTPUT VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
BO
S.26
or---
~
\
10·20 mA
~vin
6.2 2
o
:r....
;o
f'" 120 Hz
............ r-
'" 1.0 V(RMS)
-
Cl
--........
6.1 8
~
!j
40
4.0
S.O
B.o
10
12
14
IS
18
20
./
~ 6.14
6.10
S.OS
-25
22
VO, OUTPUT VOLTAGE IVOLTS)
5-15
./
-
---
V
./
--
f.-"1
~
>
0
2.0
10 k
1.0 k
I, FREQUENCY 1Hz)
IVin-Voutl, INPUT·OUTPUT VOLTAGE DIFFERENTIAL (VOLTS)
I
I
Vio = -11 V
Vo·-S.OV10 ·20mA
Y
I
+25
"'50
+75
+100
+125
TJ, JUNCTION TEMPERATURE 1°C)
+150
+115
MC7900C Series (continued)
TYPICAL CHARACTERISTICS Icont,nued)
fiGURE 7 - OUIESCENT CURRENT AS A FUNCTION
OF TEMPERATURE
DEfiNITIONS
Line Aegulation - The change In output voltage for a change In
the input voltage. The measurement IS made under conditions of
5. 2
low dissipation or by uSing pulse techniques such that the average
O~
chip temperature is not significantly affected.
Load Regulation -- The change 10 output voltage for a change
load current at constant chip temperature.
.......
r-......
8
MaXimum Power Dissipation - The maximum total deVice dissipation for which the regulator Will operate within speCifications .
.........
............
6
Yin = -11 V
o
25
QUiescent Current -
VO·-6.0V'0' 20mA
.......
"
4.2
100
That part of the Input current that IS not
delivered to the toad.
--
..................
50
75
TJ. JUNCTION TEMPERATURE 10C)
Output Noise Voltage -- The rms ae voltage at the output. with
constant load and no Input ripple, measured over a specified fre·
quency range.
Long Term Stability - Output voltage stability under accelerated
life test conditions with the ma)(lmum rated voltage listed in the
devices' electncal characteristics and maximum power dissipatIOn
125
OUTLINE DIMENSIONS
MIUIMETE S
O.M
ll~
r~,
LEAO CONFIGURATION
PIN 1. GNO
2. OUTPUT
CASE: INPUT
's~1
PLAN"
•
~
J
__
M
I.
10
NOn:
I.OIM··C··ISOIA
•••
.J
MAX
INeMU
M••
MAX
..""
I. ...
lU7
2'"
1
".
34'
... ....
•
0."
O.OB
1.117
11.11
0..20
1115
12.19
0.SS5
,.• • ....
"
'09
11.18
'.84
OISI
21.67
0.043
0.135
1.197
.....
0.2
0.175
0....
0.161
'05'
R
G
L.d111t90 ld pliledCtlp""to'edKo"'"
'T"d.nwko'WnI'nIlIhr;lu.EII(Ir,cCofpll""OO
G,oundeonnKlidtoCl•.
Md••
,.c""
~~I
~=t-+~
FTrfM
tH
.---..1
I(
0-!!tGL
IIILLIMETERS
• X
•
16.0. 11.33
12.57 12.13
3.11 3.43
0 ..
DJI
3.11
2.!t4ISC
2.01
2.t2
0.43 0."
14.73 lUI
,...
l ]
S
m
•
1.47
I.n
S.O
.1
,
4.1
11
.11
S.
--JL-J
~~l
r r
13 2
lEAD CONFIGURATION
PIN 1. GND
PIN 2 OUTPUT
PIN] INPUT
CAU"·II
Helll,nk,u,l.utonnectedtop,03
5-16
D'.
UI
...
7.4
.,,
H
X
0.03' 0.'"
..
0.... 0....
.• 25
0.020 D....
0.142 0.152
D.'
o.le
.11
0.011 DO
0.... 0.590
T
o.osa o.oa
.1
.1
O.
O.
O.D
.275
NOTES
101M '"G . IS TO CENTUI OF LEADS
PLASTIC PACKAGE
CASE 111-04
PSUFFIX
W."h!.2U9'iml
MC7900C Series (continued)
APPLICATIONS INFORMATION
Onign Consi_ationl
In many low current applications, compensation capacitors are
not required. However, it is recommended that the regulator
input be bypassed with 8 capacitor if the regulator is connected
to the power supply filter with·long wire lengths, or if the output
load capacitance is large. An input bypass capacitor ,should be
selected to provide> good high-frequency characteristics to insure
stable operation under all load conditions. A 0.33 ~F or larger
tantalum, mylar, or other capacitor having low internal impedance
at high frequencies should be chosen. If an aluminum electrolytic capacitor is used, its value should be 1.0 ",F or larger. The
bypass capacitor should be mounted with the shortest possible
leads directly across the regulators input terminals. Normally good
construction techniques should be used to minimize ground loops
and lead resistance drops since the regulator has no. external
sense lead. Bypassing the output is also recommended.
FIGURE 8 - CURRENT REGULATOR
FIGURE 9 - CURRENT BOOST REGULATOR
The MC7900c Series of fiJCed voltage regulators are desi!Jled
with Thermel Overload Protection that shuts down the circuit
when subjected to an excessive power overload condition, I "ternal
Short-Circuit Protection that limits the maximum current the circuit will piss, and Output Transistor Safe-Area Compensation that
reduces the output short-circuit current 85 the voltage across the
PBH transistor is increased.
(-5.0 V@ 4.0 A, With 5.0 A current limiting)
-10 V
I nput
____
.....
--'\N\~
~(
'),-------------....._
-5.0 V
Output
10 = 200 mA
Input
Vo ~10 V
2'+ 1.0 ",F
e-~----------------~+---------__
.Gnd
The MC7902. -2.0 V regulator can be used as a constant current
source when connected as above. The output current is the sum of
resistor R current and quiescent bias current as follows:
Gnde---------------~------+_------~_eGnd
-Mounted on common heet sink, Motorola MS·100r equivalent.
When a boost transistor is used, short-circuit currents are equal
to the sum of the series pass and regulator limits, which are
measured at 3.2 A and 1.8 A respectively in this case. Series pass
limiting is approximately equal to 0.6 V/ASC. Operation beyond
this point to the peak current capability of the MC7905C is pos·
sible if the regulator is mounted on a heat sink; otherwise thermal
shutdown will occur when the additional load current is picked up
by the regulator.
The quiescent current for this regulator is typically 4.3 rnA.
The 2.0 volt regulator was chosen to minimize dissipation and to
allow the output voltage to operate to within 6.0 V below the
input voltage.
FIGURE 10 - OPERATIONAL AMPLIFIER SUPPLY
(±15V@1.0AI
+20 V
+15 V
Input
Output
0.33"F
Gnd
FIGURE 11 - TYPICAL MECL SYSTEM POWER SUPPLY
(-5.2 V@ 4.0 A and -2.0 V@ 2.0 A: lor PC Board)
-12 V
Input
-5.2 V
>-----'V'."v-------_--_Output
1N4001
or Equiv
Gnd
-2.0 V
.....--~W\r------e---+_ Output
-20 V
-15 V
Input
Output
Gnd
The MC7815 and MC7915 positive and negative regulators may
When current·boost power transistors are used, 4 J·ohm base·to·
emitter resistors (RI must be used to bypass the quiescent current
at no load. These resistors, in conjunction with the VBe of the
NPN transistors, determine when the pass transistors begin conducting. The 1-ohm and 4-ohm dropping resistors were chosen to
reduce the power dissipated in the boost transistors but still leave
at least 2.0 V across these devices for good regulation.
be connected as shovvn to obtain a dual power supply for oper·
ationll amplifiers. A clamp diode should be used at the output of
tlw MC7815 to prevent potential latch·up problems.
5-17
RANDOM ACCESS MEMORY
MCM7001L "\
MCM7001L-l ~-----------'
Advance Inf'orxnation
MOS
1024-BIT STATIC RANDOM ACCESS MEMORY
IN-CHANNEL. METAL GATE)
The MCM7001 memory is fabricated with high-density, highlyreliable, N-channel, metal-gate MOS technology_ The device utilizes
low-voltage inputs (except Chip Select) and on-chip address registers,
and has low power consumption. Low output capacitance and a Chip
Select input allow memory expansion without speed degradation.
The charge pump technique is used to automatically refresh all
memory cells without affecting memory access_
•
Organized as 1024 Words of 1 Bit
•
Access Time
= 55 ns Maximum
= 75 ns Maximum
(MCM7001 L)
(MCM7001.L-l)
•
Cycle Time = 180 ns Minimum
•
Static Operation
•
Low Power Dissipation
640 IIW/Bit Maximum Active
60 IIW/Bit Maximum Standby
•
Differential Current Sinking Outputs
•
On-Chip Address Registers
CERAMIC PACKAGE
CASE 694
•
Low-Voltage Inputs (Except Chip Select)
•
Chip Select for Memory Expansion
•
MCM7001 L Direct Replacement for AMS7001
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (See Note 11
(Referenced to most negative supply voltage, Vsx.l
Rating
Supply Voltages
Symbol
Value
Unit
VDD
-0.5 to +25
Vdc
VREF
-0.5 to +25
Vdc
VSS
-0.5 to +10
Vdc
Vin,V out
-0.5 to +25
Vdc
Operating Temperature Range
TA
o to + 70
Storage Temperature Range
T stg
-55 to +125
ue
°e
I nput and Output Voltages
NOTE 1
1024-BIT STATIC
RANDOM ACCESS
MEMORY
Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGSareex-
VSX
22
At
AO
21
A2
VSS
20
A3
NC
19
A"
op
18
VDD
D,n
17
D out
WE
16
Dout
A9
15
VAEF
A8
CS
NC
A5
A7
10
"
13
A6
11
12
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT·
ING CONDITIONS. Exposure to higher than recommended or maximum voltages
for extended periods of time could affect deyice reliability
BLOCK
DIAGRAM
VDD
VSS·
v,x
'0
17 Data Oel' IDoel,1
Ditta (" 10,,,1 60--
16 Da';I0ul (OOul'
W",. E"abl. lWEI 7 0 - - - - - - - - - 0 - 1
C"cu,uy
AO
A'
AJ
Buff."
14 CI'I,pSelec\ ICSI
This is advance Information and specifications are subject to change without notice.
5-18
This deyice contains circuitry to protect the
Inputs against damage due to hIgh static voltages or electric fIelds; however. it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high Impedance CIrCUIt.
MCM7001 L,MCM7001 L-l (continued)
RECOMMENDED OPERATING CONDITIONS IF ull T emperature R ange
Parameter
Symbol
Min
Nom
Max
VOO
14.7
15.5
16.3
V
VREF
7.0
7.5
8.0
V
Supply Voltages
Unit
VSS
0
0
0
V
VSx
-2.7
-3.0
3.3
V
-
5.5
V
Logic Leyels
Input High Voltage IAn, Din, WE)
VIH
4.0
Input Low Voltage (An. Din. WE)
VIL
-1.0
Chip Select High Voltage
VCSH
VOO -1.0
Chip Select Low Voltage
0.8
V
VOO + 1.0
V
VCSL
-1.0
V
VpH
8.0
-
1.0
Charge Pump High Voltage
12
V
Charge Pump Low Voltage
VPL
VSx - 2.0
-
VSx - 5.0
V
Timing (tCSr and tCSf - 10 ns)
Chip Select On Time
TCS
80
-
500
ns
Chip Select Off Time
TCS
100
-
-
ns
Chip Select Rise Time
tCSr
5.0
-
40
ns
Chip Select Fall Time
tCSf
Cycle Time (Read or Write)
Teye
5.0
180
-
Setup Time (An. Din, WE)
TIS
0
Address Hold Time
TAh
40
-
Write Valid Time
TWv
TCS + TIS
Data I n Valid Time
TOv
TCS + TIS
f pump
200
-
Charge Pump Input Frequency
(See Figure 1 for waveform
40
ns
-
ns
ns
ns
ns
ns
kHz
1000
characteristics)
DC ELECTRICAL CHARACTERISTICS IFull operating voltage and temperature range unless otherwise noted.1
Symbol
Characteristic
Input Current (An. Din)
IIH
Min
-
Typ
Max
Unit
0.4
1.0
mA
IVI = 4.0 V, VCS = 01
Write Enable I "put Current (V I - 4.0 V. V CS - OJ
IWH
Chip Select I nput Current, Average Over Operating Mode
IVA = VI L, T eye = 180 nsl
ICSH
Chip Select Low Input Current
IV A = 4.0 V, V CS = 01
Differential Output Sink Current
ICSL
100
0.2
Supply Current, Unselected Mode
IVCS = 01
ISXU
-
IDOU
IREFU
Supply Current, Operating Mode
ITeye= 180nsl
-
-
100
~A
10
mA
-11
mA
-
mA
-
-100
~A
2.5
3.0
mA
-
60
-400
ISX
IREF
10
-
~A
25
35
"A
mA
6.0
10
mA
AC ELECTRICAL CHARACTERISTICSIFul1 operating voltage and temperature range unless otherwise noted.1
Characteristic
MCM7001 L
MCM7001 L-l
Access Time (I DO '" 0.2 mA, tCSr - 10 ns,
RL = 100ohms,CL = 50pF, Figure 21
Address Capacitance'"
.
Write Enable Capacitance
Data In Capaci tance
.
Symbol
Min
Typ
Max
Unit
T aee
-
45
-
55
75
ns
ns
5.0
6.0
pF
5.0
6.0
pF
5.0
6.0
pF
65
80
pF
6.0
pF
80
pF
CA
CWE
VI = VSS,
f = 1.0 MHz
-
COl
Charge Pump I nput Capacitance-
COP
Data Output Capacitance'"
IVCS = VSS, f = 1.0 MHzl
COO
Effective Chip Select Capacitance (Figure 3)-
CCSIEFFI
·Capacitances are periodically sampled rather than 100% tested.
5-19
-
-
65
MCM7001 L, MCM7001 L-l (continued)
FIGURE 1 - CHARGE PUMP OSCILLATOR WAVEFORM REQUIREMENTS
Characteristic
Rise Time
High Level Dwell Time
Fall Time
Low Level Dwell Time
Symbol
Min
"
100
tQPH
100
"
100
tQPL
Max
Unit
ns
ns
500
100
FIGURE 2 - MEMORY TIMING OIAGRAM
___-+____ Read Cycle
(T eye)
VCSH
Chip
Select
VCSL
V,H
Address
V,L
Write
Enable
V'L
V'H
Data
In
V ,L
Data
£\
Out
Current
0
FIGURE 3 - MEASUREMENT OF EFFECTIVE CHIP SELECT CAPACITANCE
.. 15 V
o----1CS MCM70011
The effective capacitance of the Chip Select input
terminal CCS(EFFl is determined by measuring the difference In rise times of the voltage waveforms at pOint A
with and without the Chip Select terminal connected
CCSIEFFI ",Kt.t,
where K ~ 'K/V (15 V)
'K ~ 100 rnA
5-20
MCM7001 L,MCM7001 L-1 (continued)
APPLICATIONS INFORMATION
The MCM7001 static random access memory provides
the high speed and low power required for large memory
systems. Only a single clock input is required with this
memory. Data Output and its complement can be detected
using a differential amplifier for sensing. The outputs of
several devices can be wire-ORed with no significant
degradation in speed.
Operation of the Charge Pump input is shown by the
basic memory cell in Figure 4. Assume the arbitrary state
of 03 "on" and 04 "off". In this state, Cl is charged and
C2 discharged. Over a period of time, Cl will lose its
charge due to leakage unless the charge is replenished. By
driving the charge pump devices with an oscillator of the
correct frequency, the memory will be refreshed.
The Charge Pump oscillator must operate within the
frequency and amplitude limits listed under Recommended
Operating Conditions. These frequencies and voltages provide low power consumption and static operation. The
Charge Pump input does not need to be operated synchronously with any other input signal and has no effect
on access ti me.
the address inputs (approximately 400 pF for a 32 k x 2
or 4 k x 16 memory board). This will maintain a fast
access measured from the address input_ The circuit of
Figure 6 should also be used to drive the write enable
input. The circuit of Figure 7 is capable of driving the
four data inputs required in a 4 k x 16 memory board,
but the circuit of Figure 6 should be used if more than
four devices are being driven. Interface circuits MC3459
(Ouad TTL-to-N channel) and MC10177 (triple ECL-to-N
channel) will be available in 1974 for system use,
The Chip Select driver must charge its capacitive load
with the specified rise time to maintain the fast access
time, In addition, it must supply a small dc current in
both the High and Low states. Figure 8 shows a MECL
interface circuit which will drive a load of eight devices
(one byte) to the required level of VDD ± 1.0 volt.
MECL level translation is first made through a differential
amplifier. The amplifier turns on a switch which in turn
drives the output transistors. In order to minimize rise
time and overshoot, proper line integrity and termination
must be used. Some rules for achieving this are found
in the MECL System Design Handbook.
Another approach for driving the Chip Select inputs,
although slower, is to use the MC10127 dual clock driver
for MECL systems or the MMH0026 for TTL systems.
The data outputs, D out and Dout, are current sinking
terminals and require pullup resistors. If a logic "1" exists
in the addressed location, Dout will sink a minimum
current of 200 IJ,A toward ground, while Dout is a high
impedance. If a logic "0" exists, Dout will be a high
impedance and Dout sinks current. The output data from
the memory then is referenced around the supply voltage
connected to the pullup resistors.
A simple, fast, and reliable output sensing circuit is
shown in Figure 9. The PNP transistors are used to translate the memory outputs to a voltage that can be detected
by the differential amplifier. The 3.6 k-ohm resistors are
used as 2.0 mA current sources that produce a 1.0-volt
drop across the 510 ohm resistors. The voltage at the data
outputs (D out and Doutl is fixed at one diode drop above
VR EF· When one data output sinks current, less current is
available across the 510 ohm resistor and a lesser voltage
appears at that terminal of the differential amplifier
(e.g., .:l200 IJ,A = Lll00 mV; Ll400 IJ,A = Ll200 mV). For a
fast MECL system the MC 1650 dual comparator should
be used (propagation delay = 3,5 ns). It requires a low
overdrive, low input switching current and has a latch for
data storage. If desired, the MC10115 quad line rece'iver
could also be used for the differential amplifier, The
MC10125 quad MECL·to·MTTL translator, which has a
propagation delay of 5.0 ns can be used as the differential
amplifier with TTL systems. If longer delays are tolerable,
the MC1514, MC3450 or MC75107 can be used.
A major advantage of the technique used in Figure 9 is
that up to 16 memory outputs can be tied together
without appreciably affecting the access time.
The Charge Pump oscillator of Figure 5 uses the Charge
Pump input capacitance of the MCM7001 as part of a
Colpitts-type oscillator. The oscillator can drive from B to
64 devices in a push-pull manner by connecting half of the
RAM charge pump inputs to each end of the inductor. The
zener and resistor are used to control the oscillator amplitude. The positive peak of the swing is determined by the
zener voltage and the negative swing is 0.6 V below the
VSS voltage (-5.2 V). It is important that the maximum
voltage rating of the MC14049 feedback buffer be
observed.
Frequency of oscillation is dependent on the number
of RAMs to be driven. The inductance is determined as
L""--_--;:
10 n COP f2
where n = total number of RAMs,
COP = charge pump capacitance, and
f = frequency.
Typical values will therefore be
Frequency
Number of RAMs
Inductance (Ll
800kHz
8
16
30QjJ.H
32
64
150,uH
75.uH
37.uH
Figures 6 and 7 show possible interface circuits for
driving the address and data inputs of the MCM7001. The
MC10125 MECL-to-MTTL translator is used if ECL logic
is being interfaced to the memory card; if TTL is being
used, an MTTL gate such as the MC3000 can be used. The
pullup resistor at the output is needed to meet the required "1" level. The extra drive circuitry shown in
Figure 6 is required to drive the normally heavy load of
5-21
MCM7001 L,MCM7001 L-1
(continued)
FIGURE 4 - BASIC MEMORY CELL
FIGURE 5 - CHARGE PUMP OSCILLATOR
From Oscillator
Charge
Pump
~
Charge
15.5 V
10 V
180
Pump
Sit/Sense
,", ..
Bit/Sense
"0"
-S.2V
,,
B
A
,
MCM70010pH
MCM7001
H a p MCM7001
QP~
6..-10P
MCM7001
Vss
F rom Decoder
FIGURE 6 - ADDRESS INPUT DRIVER
150
,;4
MC10125
r---,
I
v
.. 5.0 V
470
I
I
ME C L 0-----1--<1
>--;---0............- .
Input
I
I
I
HAn
I
MCM7001
I
LJ
[An
MCM7001i
.
PACKAGE DIMENSIONS
CASE 694
CASE 677
NOTES
1 OIM"V"TO INSIDE
OF LEADS (MEASURED
O~I mm
(0.0201 FROM
PACKAGE BASE)
2
lEADSWITtUNO~
RADIUM OF TRUE
POSITION (TP)AT
SEATING PLANE
WITH MAlIlMUM
MATERIAL
CONDITION
J LEAD No. 1 IDENTI
FifO BY NOTCH ON
TOP
DIM
A
B
C
D
F
G
H
J
K
L
+.
N
MILLIMETERS
MIN MAX
INCHES
MIN MAX
26.54 27.94
9.02
9.40
3.30
4.06
0.38
0.53
1.02
1.27
2.54 SSC
0.89
1.40
0.20
0.30
2.92
3.68
9.78 10.79
15'
0~51 ·'.52
1.045 1.100
0.355 0.370
0.130 0.160
0.D15 0.021
0.040 0.050
0.100 8SC
0.035 0.055
0.008 0.012
0.115 0.145
0.385 0.425
15'
0.020 0.060
The MCM7001 may be pack·
aged in Case 677 (white ceramic)
rather than in Case 694. If your
application requires precise toler
ances, consult the factory.
SEATING PLANE
5-22
DIM
A
MILLIMETERS
MIN
MAX
27.05 21.94
INCHES
MIN
MAX
1.065 1.100
C
D
F
G
H
2.16
3.
0.43
0.58
1.02 REF
2.54BSC
0.76
1.78
0.085 0.14
0.017 0.023
0.040 REF
0.100BSC
0.030 0.070
MCM7001 L,MCM7001 L·1 (continued)
FIGURE 7 - DATA INPUT DRIVER
+5.0 V
1/4
MC10125
MECL
Input
330
I
I
MCM7001 I
Din
FIGURE 8 - CHIP SELECT DRIVER
+15Ve_--~------------------~----._----__,
10
620
MPS3646
1 k
MPS834
MPS834
or Equiv
MECL
Input
91
360
-5.2
360
Ve_-_._--------_---------'
FIGURE 9 - OUTPUT SENSE CIRCUIT
IMCM7001
~out~
00ut
I
I
I
I
I
2N4209
or Equiv
510
1%
Amp!.
.-<>--'----Ic
2N4209
or Equiv
I
I
L ______ -.J
510
1%
Strobe
5·23
PHASE·LOCKED LOOP
COMPONENTS
6-1
LOGIC PRODUCTS
for
PHASE-LOCKED LOOP APPLICATIONS
Motorola offers the designer a choice of specially designed integrated circuits for performing
phase-locked loop functions: phase detection, frequency division, filtering, and voltage-controlled
signal generation. In addition, the choice of circuits permits the designer to select TTL circuits
where speed is not critical «25 MHz), or ECL circuits where high speed is required. The MC12000
series circuits will operate at either +5.0 V or -5.2 V, and translators are included where needed so
that all functions are compatible.
SPEED
DEVICE
NUMBER
LDGIC
FAMILY
(TYP)
Phase-Frequency Detector
MC4044
MTTL
10
Consists of two diSital phase detectors,
charge pump. and amplifier
FUNCTION
MHz
CHARACTERISTICS
Phase-Frequency Detector
MC12040
MECL
80
Operation similar to MC4044
Voltalle·Controlied Multivibrator
MC4024
MTTL
25
Contains two independent voltagecontrolled multivibrators with output
buffers
Voltage-Controlled Oscillator
MCI648
MECL
200
Emitter-coupled oscillator
with output levels
compatible with MECL III
MCI2000
MECL
250
A "0" flip·flop with MTTL to MECL and
MECL to MTTL translators
Two-Modulus Prescaler
MCI2012
MECL
200
~2,
Two-Modulus Prescaler
MC12013'
MECL
400
'710/11, '710/12
Counter Control Logic
MCI2014
MTTL
25
Crystal Oscillator
MCI2060
MECL
Crystal Oscillator
MC12061
MECL
Programmable Divide By N
Decade Counter
MC74416
(MC4016)
MTTL
10··
'70 throullh 9
Two Programmable Divide By N
Counters
MC74417
MTTL
10··
'70·1, '70 through 4
Programmable Divide By N
Hexadecimal Counter
MC74418
(MC4018)
MTTL
10··
'70 throullh 15
Two Programmable Divide By N
Counters
MC74419
MTTL
10··
'70 through 3
Universal Counter
MC4023
MTTL
30
'72 through 12 except 7 and 11
Decade Counter
MC7490
MTTL
20
'72,'75, '710
Digital Mixer/Translator
'75/'76,
~IOh·11,
'710/'712
Used with MCl2012 and MC74416
to accomplish direct high-frequency
programming
100 kHz to Provide complerflentary sine wave,
2 MHz
~fn~r~~~d:~artt~iil~'!~~r~~:p~t~~
2 MHz to
20 MHz
Frequency stability prOllided by external
crystal (fundamental, series mode).
COUNTER OPTIONS
Bi·Quinary Counter
MCI678
MECL
325
'72, '75,'710
UHF Prescaler Type D Flip-Flop
MCI690
MECL
500
'72
Universal Hexadecimal Counter
MCIOl36
MECL
150···
Universal BCD Decade Counter
MCIOl37
MECL
150··· '710
o to
15
Decade Counter· Divider
MCI4017
MeMOS
5
'710
Binary Counter
MC14040
MeMOS
10
'7(2")
'710
BCD Presettable Up/Down Counter
MCI4510
MeMOS
6
Binary Up/Down Counter
MCI4516
MeMOS
6
'716
Dual BCD Up Counter
MCI4518
MeMOS
6
'7100r'7JOO
Dual Binary Up Counter
MCl4520
MeMOS
6
'716 or '7256
BCD Prollrammable Divide By N
MCl4522
MeMOS
5
'70 throullh 9
Binary Programmable Divide By N
MCI4526
MeMOS
5
'70 throullh 15
(.) To be announced.
( .. ) Speed can be increased to 25 MHz (typ) when used with MC12014
( ••• ) When used as a prescaler, it is possible to extend the input frequency to over 200 MHz with the
MCI0231; to 300 MHz with the MC1670; or to over 500 MHz with the MCI690
6-3
CONTENTS
PAGE
MC1648
Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . ..
6·5
MC12000
Digital Mixer/Translator. . . . . . . . . . . . . . . . . . . . . . . ..
6·12
MC12012
Two Modulus Prescaler . . . . . . . . . . . . . . . . . . . . . . . . ..
6·23
MC12040
Phase Frequency Detector. . . . . . . . . . . . . . . . . . . . . . ..
6·38
MC12060, MC12560
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6·42
MC12061, MC12561
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6·42
NOTE: For individual data sheets on other products listed in the selector guide write Motorola Semiconductor Products Inc.
P.O. Box 20924
Phoenix, Arizona 85036
6-4
MECL III MC1600 series
VOLTAGE·CONTROLLED
OSCILLATOR
MC1648
The MC1648 is an emitter·coupled oscillator, constructed on a single monolithic silicon chip. Output levels are
compatible with MECL III logic levels. The oscillator requires an external parallel tank circuit consisting of the
inductor (L) and capacitor (C).
A varactor diode may be incorporated into the tank
circuit to provide a voltage variable input for the oscillator
(VCO). The MC1648 was designed for use in the Motorola
Phase-Locked Loop shown in Figure 9. This device may
also be used in many other applications requiring a fixed
or variable frequency clock source of high spectral purity
(See Figure 2).
The MC1648 may be operated from a +5.0 Vdc supply
or a -5.2 Vdc supply, depending upon system requirements.
110)
112)
15)
Numbers in parenthesis denote pin number for
F package (Case 607) L package (Case 632), and
P package (Case 646).
Input Capacitance = 6 pF typ
Maximum Series Resistance for L (External Inductance) = 50 51 typ
Power Dissipation = 150 mW typ/pkg (+5.0 Vdc Supply)
Maximum Output Frequency == 225 MHz typ
I
SUPPLY VOLTAGE
GND PINS
SUPPl Y PINS
I
+5.0 Vdc
7,8
1,14
-5.2 Vdc
1,14
7,8
l
FIGURE 1 - CIRCUIT SCHEMATIC
vee1
VCC2
(141
+---+---+---+---{
t---t---t---i
11)
a1 0
Output
all
a12
014
Q13
f-T-+-,-+--++-t
D2
(101
(121
(8)
(5)
171
818S Pt
Tank
Vee 2 AGe
Vee 1
Numbers in parerUhesls denote pm number for F package (Case 6071, L package (Case 632), and P pacKage (Cas.e 6461
FIGURE 2 - SPECTRAL PURITY OF SIGNAL AT OUTPUT
L: Micro Metal torroid #T20-22, 8 turns
#30 Enamlad Copper wire.
C'" 3.0 - 35 pF
r--"'~"--"''''''
+5.0 Vdc
110)
1200'
(3)
(12)
(5)
X
B.W. "" 10 kHz
Canter Frequency"" 100 MHz
Scan Width = 50 k Hz/div
Vertical Scale:: 10 dB/div
Signal
Under
Test
0.1jlF
-The 1200 ohm resistor and the scope termina·
tion impedance constitute a 25: 1 attenuator
probe. Coax shall be CT ·010·50 or equivalent.
MC1648 (continued)
ELECTRICAL CHARACTERISTICS
r-------,
Vol~ ~
SupplV
(101
+5.0 volts
I
I
:
: (31
I
(121
Output
TEST VOL 'AGE/CUAAlNT VALUES
(Voitel
I
L_______ J
.T...
r..,....''''.
(51
OI._~I"IC
logK .""
Symbol
·"'c
..
"
VO:~
,
YO'
".
,.,
Output Vall.
LOOOC "0"
Oulpul Volt.
B, .. Voll.
Ve,n"
P• ..,·la·P.... rink Voll-.JII
1I!).p
VDC
OseillatlOnF~uerw:y
"Thl'
mUlUrll~1
'-.
YIL,,"n
-..,,<:
+1.800
+1410
., JOO
+1.680
+1180
'0
M:164. Tnt L"","
...
"'.
" ..
3<0
320
M..
..
,
....
T"
OutPUt Duty Cyel.
YIHma.
. . .·C
....
p"
p _ Supply 0 ••," CU"'n!
·,..C
"
-..,,<:
....
·'.960
Vee
'L
SO
SO
SO
·SO
·SO
·SO
TEST VOL 'A.GE/CURRENT ... HlIED TO
'INS LISTED BELOW
+850 C
M..
.0
.,S
IGndl
7.8
1.14
,...
7.'
1.1"
7.'
'SO
1,14
7.'
'.'
7.8
••
J2'
'1.0 Megphm must
be used).
.
• -The 1200-ohm resistor and the scope termination
Impedance constitute a 25: 1 attenuator probe.
Coax shall be CT ·070·50 or .eQuivalent .
r~'1LJ!l,
I
I
• _. Bypass only that supply opposite ground.
I
I
I
6-6
(Ond)
1.1"
Vee
~ ...
Vee
Vllm.n
7.8
....
T, •
-I
-4000
I
7.'
Vd<
s..F'lIur.3
50
1
M;"
VILmin
-3300
·3-400
-3500
TEST VOL TAGE/CURIUNT APPLIED TO
PINS LISTED BEL.OW
.. -
.,
M..
-0815
VOH
+l6 o C
M(:1&48T ... L.imiti
(VoIu)
VIHm. .
I.'"
I.'"
MC1648 (continued)
OPERATING CHARACTERISTICS
Figure 1 illustrates the circu it schematic for the MC 1648.
The oscillator incorporates positive feedback by coupling
the base of transistor 07 to the collector of 08. An auto·
matic gain control (AGC) is incorporated to limit the cur·
rent through the emitter·coupled pair of transistors (07
and 08) and allow optimum frequency response of the
oScillator.
In orderto maintain the high a of the oscillator, and pro·
vide high spectral purity at the output, a cascode transistor
(04) is used to translate from the emitter follower (05) to
the output differential pair 02 and 03. 02 and 03, in
conjunction with output transistor 01, provide a highly
buffered output which produces a square wave. Transistors
010 thru 014 provide the bias drive for the oscillator and
output buffer. Figure 2 indicates the high spectral purity
of the oscillator output (pin 3).
FIGURE 4 - THE MCl648 OPERATING IN THE VOLTAGE
CONTROLLED MODE
When operating the oscillator in the voltage controlled
mode (Figure 41. it should be noted that the cathode of
the varactor diode (D) should be biased at least 2 VBE
above VEE ("" 1.4 V for positive supply operation).
When the MCl648 is used with a constant dc voltage
to the varactor diode, the output frequency will vary
slightly because of internal noise. This variation is plotted
versus operating frequency in Figure 5.
(12)
(5)
~C2
FIGURE 5 - NOISE DEVIATION TEST CIRCUIT AND WAVEFORM
!
100
"'~
VCC
5.0 Vdc
Oscillator Tank Components
(Circuit of Figure 4)
It
z"
Q
~
I-
«
:;
w
Q
10
.......
>
u
f
MHz
0
L
I'H
1.0·10
MV2115
100
10-60
MV2115
2.3
60·100
MV2106
0.15
zw
:J"
0
w
It
u.
~
1.0
1.0
10
100
f, OPERATING FREQUENCY, (MHz)
I
l
20 kHz .bov, MCI648 Froquoncy ~
Signal Generator
HP 608
or EQuiv
I
300mV
II'
MC1~
Under TI.
Attenuator
lI
10mV
MCI848
Product
O.tector
Frequency (1)
F requlncy Deviation·
I
20 kHz
I
IB.W. - 1.0 kHz
Fr~u.ncy
L
Mo""
HP~~OA
or E ulv
(HP5210A oUtJ)ut voltlge) (Full Selll Frequency)
1.0 Voll
NOTE: Any frequency deviation clulld by thl •• n.I'. . . .tor end MC1648 power
iu_'y Ihould bl determined end mlnlmzld prior to tlltlnl.
6·7
Voltmeter
RMS
HP3400A or Equiv
I
MC1648 (continued)
TRANSFER CHARACTERISTICS IN THE VOLTAGE CONTROLLED MODE
USING EXTERNAL VARACTOR DIODE AND COIL. TA· 25°C
FIGURES
.
1:
!
>
U
Z
III
:>
a
III
a:
II.
l-
:>
o.
I:>
0
,
;.
_0
64
L: Micro Metel Torold.1 Cor. #T44-10.
4 turn, of No. 22 copper wir •.
60
56
Vin
92
48
...... 1-""
44
40
/'
36
32
28
24
20
"~'~'
• k
I'FI!L
I
= (I
/'
,,1
/
16
.2
8.0
0
51' F
V
3.0
2.0
4.0
5.0
7.0
6.0
8.0
9.0
.0
Vin,lNPUT VOLTAGE (VOLTS)
l
I
f
: (3) out
L.
I _______
II"
1\.0
IJ
(10)
V
('2)
MV140.
I
~
(5)
Vee1 .: VCC2 == +5 Vdc:
Vee 1 '" VEE2 ::: God
:;J;0.'I'F
-The 1200 ohm resistor and the scope termInation impedance constitute II 25: 1 attenuatar
probe. Coax shall be CT -010-50 or equivalent.
FIGURE 7
.8
r
!
>
U
Z
III
:>
a
III
L: Micro Metal Toroidal Core IT44·10,
4 turns of No. 22 copper wire.
17
Vin
16
C
.5
a:
13
I-
12
/
:>
o.
I:>
\I
0
10
_0
9.0
;
/
/
I k
I'FI ( :
CL
M~O'
1.0
(12)
I
:
I
I
f out
(3)
'---------'
(5)
/
5I'FI_
= +5 Vdc
= Gnd
Vee, '" VCC2
VEE1 "" VEE2
2.0
1200·
:
C I
= 1
,,~
8.0
0
;--------""]
/
/
IJ
500 pF
0"r:(~0~)
.4
II.
=
3.0
4.0
5.0
6.0
7.0
8.0
9.0
'0
Vin. INPUT VOLTAGE (VOLTS)
""= 0.1 ",F
..L
-The 1200 ohm resistor and the scope termina-
tion impedance constitute a 25: 1 attenuator
probe. Coa", shall be CT -070-50 or equivalent.
FIGURE B
190
r
!
>
U
z
III
:>
170
V
a:
120
II.
I-
110
100
,
_0
1/
90
60
50
~
.......
0
1.0
2.0
3.0
./
•
0
('0)
L
~'-'
I
I
:
:
(
I (3)
L.
I _______
(12)
V
4.0
VEEl
~g
=~~ )
./
70
VCCI = VCC2 = +S Vdc
= VeE2 '" Gnd
-!="
,
/
/'
ao
Von
0.'
I'F:t
51'Ff
51 k
./
ISO
,.0
130
0
./
160
aw
:>
o.
I:>
L: Micro Metal Torodial Core #T30-22.
5 turn, of No. 20 copper wir •.
180
f out
0
~
(5)
:;J;0.'I'F
6.0
6.0
7.0
Vin. INPUT VOLTAGE (VOLTS)
8.0
9.0
10
-The 1200 ohm resistor and the scop. termination impeda'lce con,titute a 25: 1 attenuator
probe. Co.", shall be CT -070-50 or equivalent.
MC1648 (continued)
Typical transfer characteristics for the oscillator in the
voltage controlled mode are shown in Figures 6, 7 and 8.
Figures 6 and 8 show transfer characteristics employing
only the capacitance of the varactor diode (pluse the input
capacitance of the oscillator, 6 pF typical). Figure 7 iIIus·
trates the osci lIator operating in a voltage controlled mode
with the output frequency range Ii mited. This is achieved
by adding a capacitor in parallel with the tank circuit as
shown. The 1 kn resistor in Figures 6 and 7 is used to pro·
tect the varactor diode during testing. It is not necessary
as long as the dc input voltage does not cause the diode to
become forward biased. The larger·valued resistor (51 kn)
in Figure 8 is required to provide isolation for the high·
impedance junctions of the two varactor diodes.
Good R F and low-frequency bypassing is necessary on
the power supply pins (see Figure 2).
Capacitors (Cl and C2 of Figure 4) should be used to
bypass the AGC point and the VCO input (varactor
diode). guaranteeing only dc levels at these points.
For output frequency operation between 1 MHz and 50
MHz a 0.1 J.lF capacitor is sufficient for Cl and C2. At
higher frequencies, smaller values of capacitance should be
used; at lower frequencies, larger values of capacitance. At
higher frequencies the value of bypass capacitors depends
directly upon the physical layout of the system. All by·
passing should be as close to the package pins as possible
to minimize unwanted lead inductance.
The peak·to·peak swing of the tank circuit is set inter·
nally by the AGC circuitry. Since voltage swing of the
tank circuit provides the drive for the output buffer, the
AGC potential directly affects the output waveform. If it
is desired to have a sine wave at the output of the MCl648,
a series resistor is tied from the AGC point to the most
negative power potential (ground if +5.0 volt supply is
used. -5.2 volts if a negative supply is used) as shown in
Figure 10.
At frequencies above 100 MHz typ, it may be necessary
to increase the tank circuit peak·to·peak voltage in order to
maintain a square wave at the output of the MCl648. This
is accomplished by tying a series resistor (1 kn minimum)
from the AGC to the most positive power potential (+5.0
volts if a +5.0 volt supply is used. ground if a -5.2 volt
supply is used). Figure 11 illustrates this principle.
The tuning range of the oscillator in the voltage con·
trolled mode may be calculated as:
f max
fmin
where fmin
yco (max) + Cs
yco (min) + Cs
1
=
21T
YL (CO (max) + Cs)
Cs = shunt capacitance (input plus external
capacitance ).
CD = varactor capacitance as a function of
bias Voltage.
APPLICATIONS INFORMATION
erable over RF switching with a multiple crystal system),
and a broad range of tuning (up to 150 MHz, the range
being set by the varactor diode).
The output frequency of the synthesizer loop is deter·
mined by the reference frequency and the number program·
med at the programmable counter; f out = Nfref. The
channel spacing is equal to frequency (fref).
For additional informatIon on applications and designs
for phase locked·loops and digital frequency synthesizers,
see Motorola Application Notes AN-532A, AN·535, AN-553,
AN·564, and AN·594.
The phase locked loop shown in Figure 9 illustrates the
use of the MC 1648 as a voltage controlled oscillator. The
figure illustrates a frequency synthesizer useful in tuners
for FM broadcast, general aviation, maritime and land·
mobile communications, amateur and CB receivers. The
system operates from a single +5.0 Vdc supply, and requires
no internal translation, since all components are com·
patible.
Frequency generation of this type offers the advantages
of single crystal operation. simple channel selection, and
elimination of speCial circuitry to prevent harmonic lock·
up. Additional features include dc digital switching (pref·
6-9
MC1648 (continued)
FIGURE 9 - TYPICAL FREQUENCY SYNTHESIZER APPLICATlQN
VoltageControlled
Oscillator
MC1648
r---.....- - f out
f out = Nfref
where
N = Np. P + A
N :: Np. P + A
Figure 10 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To obtain a sine
wave at the output, a resistor is added from the AGC
circuit (pin 5) to VEE.
Figure 11 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To extend the
useful range of the device (maintain a square wave output
above 175 MHz!. a resistor is added to the AGC circuit at
pin 5 (1 k·ohm minimum).
Figure 12 shows the MC1648 operating from +5.0 Vdc
and +9.0 Vdc power supplies. This permits a higher voltage
swing and higher output power than is possible from the
MECL output (pin 3). Plots of output power versus total
collector load resistance at pin 1 are given in Figures 13
and 14 for 100 MHz and 10 MHz operation. The total
collector load includes R in parallel with Rp of L 1 and
Cl at resonance. The opti mum value for R at 100 MH z is
approximately 850 ohms.
FIGURE 10-METHOOOF OBTAINING ASINE·WAVE OUTPUT
FIGURE 11 - METHOO OF EXTENOING THE USEfUL RANGE
Of THE MCI648 ISQUARE WAVE OUTPUTI
+5.0 Vdc
+5.0 Vdc
1--+--<> Output
1 k min
8
I
6-10
MC1648
(continued)
FIGURE 12 - CIRCUIT SCHEMATIC USED FOR COLLECTOR OUTPUT OPERATION
+9.0 V
l' .01.I'F
A
VCC2
(14)
+5.0
11) _
8
....
12
'0
5·
~
4
TEST VOLTAGE/CURRENT VALUES
V....
{,
"T...
Tlrnpermfl
MTll
0""
25""
70""
+25 o C
. .e
Min
MM
Min
TyO
o.
Power Supply Or.in Current
9l
.....
TM
Inpl,l1CuITent
CAl
3.8
3.8
IINLI
-1.6
IINL2
Logic"'"
OutpUt Volt....
8
9
4
10
11
121
13'
6
VOH'
I
Logic "0"
OutpUtVol~
logic "'"
Thrllhold Voltage
I
logic: "0"
Th"""ald Voltege
Short Cin:uit Curr.nt
tOulput Lwei to be
~..t
T
M..
VOH2
I 1~
VOLl
11
12t
13.
VOL2T 6
VOMA
I 1~
VOLA
I
Osc
T
11
121
13.
4
10
11
12.
13'
6
4.000
l
l
l
2.400
3.130
4.160
3.8
2.0
4.040
6."
4 .•
4.190
3.150
~
j
3.380
0.500
+3.150
+3.895
+3.525
+3.110
"'3.955
+3.550
-20
l
~"
4.100
2.400
J 170
·65
after. clock pul. h. tlMn -,plied to the C Input (pin 2)
V,Hmp
IlVILmin
VIHAmin
VILAmu:
VOL
VOH VIHH V.
VIHT VILT Vee
IloLT'oH
14
!
°L
1
18
18
-1.8
-1.8
-1.8
4.280
V""
14
Vd,
,.
V""
14
Vd,
Vd,
,. •
3.410
3.430
~"
Vd,
mAde
fYElI
00H1 and
jl=I=I=IH
rnA""
+
°OL
1
-1.6
0.500
-20
VIHmax; VILmin
/lAde
j
3.400
-2.
."
14
.A""
4.080
3.390
IVIH IVIHAIVR IVIHTIVILTlvcc
IL
+0.5 +2.4 +5.0 +4.
:t"5.0 '2.
to.5 +2.4 +5.0 +4.5 +2.0 +0.8 +5.0 -2.5
+0.5 +2.4 +5.0 +4.5 +2.0 +0.8 +5.0 -2.5
rnA""
rnA""
0.500
4.020
3.980
Unit
l l l l
l l l l
l l
l
l
l
2.400
3.370
40
6."
6."
2.0
2.0
2.0
-1.6
IL_ . .
o.unnd
IINL3
+4.190
mA
I VIL
TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW:
Min
2.0
200
200
40
4.0
IINH2
IINH3
+3.855
YllAmu
+3.510
.76OC
M..
85
IINH1
I V'HAmin I
+4.280
MC12000
Pin
u_.
.... _0
Ch8rlCteri.dc
YIHrnu VILmin
+4.160
+3.130
l
,.l
1
14
l
,.
•
10
11
12
13
•
10
11
12
13
10
11
12
13
•
10
11
12
13
- I
I - I
8.7
s:
ELECTRICAL CHARACTERISTICS
...
n
Supply Voltage - -5.2 V
N
o
o
o
,~"
2~12
8
...
::J
,~"
~"
-8>-
::J
c:
~
TH
S
'0
Moe
'=t>--Mm
_
10
•
"
.T.. .
T_
6
n
TEST VOL TAGE!CURRENT VALUES
V_
"'"
IL
o"c
.. "I:
-
Me .....
PI.
I .._I u;:-
Pow. Supply Oqjn Current
InputCul"l'Wl'
IE
I
-
I - I - I - I
-
Min
~.
200
C{J
....
40
IIINH'
•
40
6.S
6.'
3.0
3.0
IINH3
IINL2
:
IINL3
•••
Logic··,·---;----~VOH1
Output VOI'-81
11
',t
tl.
VOlt
I I.•
VOLl
'"
I•
VOH.
logic "0"
OutPUt Vol ....
-1.8
-1.000
-<1.640
11
VOHA
Th~Vol ....
..I.,
VOLA
Shon Circuit CurNnt
tO~1PUt
L.vet lObe
~r.t
T
ISC
I •••
T
11
•• t
tlt
6
-1.820
-1.020
-4.700
..
-
-0.720
Vd.
1
l
-1.596
-4.700
-0.980
-0.920
1
1
-1.600
-1.815
....1
-2.800
-1.830
mAde:
~
VILArNx
VIL
VIH VIHH VR
VIHT VILT V ••
-1.575
l
.... ..
..
-
-
lifter • dock pul.habeen IPPlild to ItI.C input !pin 21
"IHm...
.n.VILmin
ION
-1.8
to
-1 .•
18
-1.8
IOL
IoL
....
I'
••
7
!
l
-1.6
VIMAmin
1
••
1.7
'.7
3.7
:
:
I.•
I.•
11
t.
tl
Vd.
Vd,
1 1 ~
~.700
tl,
Tlu...tuMd Vol.
-1.860
mAd'
.Ad<
~
-<1.900
IL
1.
lVeel
VIH_ VILmin
.Ad<
1
1
11
L.ooi<"."
~~
~.810
-2.800
-1.836
tl,
logic"'"
~:
-
IEH1371
t+ '" t- '" 5.0 ± 0.5 os
50
~
I
50
1191
.-~__-----t---o-1~
L-~o-~__-+__-o-;~18~
161
1/2
MC10l09
50
OR
100
EQUIV.
CT = 15 pF
= total
parasitic capacitance, which includes
probe, widng, and load capacitances.
6-16
I
)--~~~--~~.--.
400
MC12000 (continued)
FIGURE 4 - AC TEST VOLTAGE WAVEFORMS
Pulse
Generator
1
Pulse
Generator
2
Q
(131
Q
(121
OR
(111
NOR
(101
(91
MTTL
Out
(61
Pulse
Generator
3
MECL
Out
(41
NOTES:
1. Vee + 1.5 V
2. Vee + 0.5 V max
6·17
MC12000 (continued)
FIGURE 5 - SETUP AND HOLD TIME WAVEFORMS (See Figure 31
Pulse
Generator
1
Clock
Pulse
Generator
2
o
0(13)
Pulse
Generator
2
o
1
0(13)
\ ' - - _ _--1
FIGURE 6 - TOGGLE FREQUENCY TEST CIRCUIT
Vee
=
+2.0 Vdc
V out
Coax
O.lI'F
~
Sine Wave in = 800 mV P-to-P
Sine Wave Generator
AC Coupled
HP 32008 or
Equivalent
50
0.1 ,sF
~
TPin
/
--,
r-
\I----<~---_il__l
~
450
I
I
I
C
01-1-----'TP out
VSia5 = +0.700 Vdc o------~
(Use High
Impedance Probe
to Adjust V Bias)
100
VEE
OC Supply
-3.2 Vdc or -3.0 V
The maximum Toggle frequency of MC12000
h . been exceeded when either:
1. The output Peak-ta-Peak voltage swing
falls below 600 mV
2. The device. cease to Toggle (divide bV 21.
6-18
MC12000 (continued)
MC12000 DIGITAL MIXER
This device is a digital mixer designed to operate with
logic levels at its input and output ports. I n operation it
is an MECL type "0" flip-flop with level translators to
and from MTTL to accomodate most interfacing demands.
Output frequency (fa) as a function of "0" and clock
inputs is shown in Figure 7. I t can be seen that either
direct or harmonic mixing may be employed, that is, fa
may be either the difference between fO and fC or the
difference between fO and the Nth harmonic of fC.
One particular advantage of mixing in phase locked
loops (PLL) is that lower frequencies may be generated
for use in portions of the circuit where digital processing
is done (with divide-by-P network and/or phase detector).
Lower frequency operation often reduces overall system
cost since a less expensive logic form may be utilized.
However use of the mixing technique is not a panacea for
all VHF applications and the design of such synthesizer
systems must be approached with care.
FIGURE 7
fa
output frequency may be changed by varying either fl or
fC. the clock input is usually crystal controlled since it is
of the same magnitude as fO and more difficult to stabilize.
FIGURE 9
fe----------------~
Combining a standard synthesis configuration with the
mixer yields a circuit capable of high frequency operation
at low cost (Figure 9). if the output frequency range is
relatively small (P max - Pmin) fl
fC12. In fact the
choice of harmonic or non-harmonic mixing is largely
based on the availability of a suitable crystal or other
reference source for fC versus the needed frequency coverage. Considering all the restrictions on fC. its value (and
the maximum harmonic number N) are dictated by the
following expressions:
<
N
Use of the MC12000 in a non-harmonic PLL is straightforward (Figure 8). Output frequency is the sum of both
input quantities (fl + fe) as long as fl is less than fC/2
(See Figure 7). since fa can go no higher than that. Unless VCO output range is restricted somewhat there is a
chance also that the loop may operate at the second harmonic of fC. This problem is minimal in the loop of
Figure 8. however. since the output frequency would have
to vary more than 2: 1.
Mixing is used because the digital phase detector has
an upper frequency limit of about 10 MHz and many
loops require direct locks at 20 MHz or more. Oirect
down-mixing does not change any loop characteristics except the sampling rate which restricts loop natural frequency to about fC/l0 in practical circuits. Although
FIGURE 8
<
fO(min) - fl
(1)
2~fO
Nfc = fO(min) - fl
(2)
where NO = change in output frequency.
FIGURE 10
Ie
----------------~
Using Equations (1) and (2) above the minimum value
of fC may be found for the circuit of Figure 10 and still
get adequate frequency coverage. In this minimum configuration all necessary output frequencies may be generat·
ed by programming the "P" count string. But the divide
number might bear no obvious relation to the output frequency such as often happens with non-mix ing synthesizers.
6-19
MC12000 (continued)
DESIGN EXAMPLES
Example #1
Example #2
Output Frequency: 48-54 MHz
Frequency Increments: 10 kHz
Using Equations (1) and (2), a minimum frequency
(fe) version can be designed:
Output Frequency: 144-148 MHz
Frequency Increments: 10 kHz
f1 = increment = 10 kHz
144_00 - 0.01
fl = increment = 10 kHz
N<
48 MHz - 10 kHz
N<-----2 (54-48) MHz
N< 18
2 (4)
LetN=
17
Nfe =
N<4
144.00 - 0.01 MHz
143.99
Let N = 3
Nfe = 47_99 MHz
47_99
3
Nfe
fe =
8.470 MHz
N
Pmin =
15.99666 MHz
4MHz
Pmax =
fe = 15.996666 MHz
Pmin.= 1
10 kHz
+ 1
401
afo
Pmax = - - - + Pmin
10 kHz
(3)
fa(max) = Pmax fl = 4.01 MHz
6MHz
Pm ax = 10 kHz + Pmin
Pmax = 601
fa(max) = Pmax fl
= 6.01 MHz
(4)
Equation (4) above puts the divider string (divide-by-P)
into a medium frequency situation where devices such as
the Me4016/4316 may be utilized. Note that the divider
number now indicates the channel selected rather than
output frequency_ That is, at fO = 48.000 MHz, P = 1;
at fO = 54.000 MHz, P = 601.
If "proper" divide-by·P readings are desired for direct
frequency readout a slight circuit modification is necessary.
To enable a division at 48_000 MHz the first divide-by-P
must be 100 rather than 1, and Pmax would then be 700
to cover all 6 MHz. Recalculating fa(max) from Equation
4 we still find that the 7 MHz maximum value allows use
of the same components. The next question concerns the
allowable rang~ of fa in relation to fe (fa < fel2)_ Since
fe is nearly 16 MHz, the range of fa can be contained.
A cosmetic change to the most significant digit switch
completes the design. Instead of reading 1 through 7 it
must be modified to display 48 through 54.
Maximum frequency seen by the divide-by·P chain is
still well within the Me4016 rating.
When converting this synthesizer to one that reads fre·
quency directly, a "1" is again added to the most signifi·
cant digit (MSO). This results in a Pmin of 100 to Pmax
of 500. In this example, however, fa(max) is 5 MHz
which easily exceeds fel2. To alleviate this difficulty,
the "N" factor must be decreased in order to raise fe to
at least 10 MHz.
Let fe = 10 MHz
N<-14.4
Let N = 14.
Nfe = 143.99 (from above)
143.99
Nfe
fe=
N
=
14
fe = 10.28500 MHz
6-20
(5)
MC12000 (continued)
VCO RANGE RESTRICTIONS
As in all harmonically locked PLL's, it is possible for
the loop to lock on the wrong harmonic if there is too
wide a range in the VCO. Th is situation is shown in Figure
11 where the possible false lock areas are ind icated near
the (N - 1) and (N + 11 harmonic points. The problem of
VCO restraint however is more than just mak ing sure that
output frequency fO isn't able to go to B or A' (the closeest false lock points). Actual operating limits are C and C',
symmetrically placed frequencies corresponding to fO(min)
about NfC and fO(max) about (Nf+l/21 fC. If the veo
drops below C while the feedback counter is at Pmin the
phase detector will try to push fO even lower, toward the
stable condition at A (Figure 12). Likewise, at C' (when
P = Pmax l the tendency is for the loop to accelerate toward lockup at B' (Figure 131. When Cor C' are exceeded
the loop will "hang up" and not attain the proper lock.
The VCO frequency constraints may be quite severe if
the minimum fC formulation is followed and the Nth harmonic is quite high. Where VCO constraint may pose a
problem, decrease N below the maximum indicated by
Equation (11 until sufficient room is generated by placing
the operating range of fa on only a small part of the fO
slope (F igure 141. Note that fC goes up as we approach
the more idealized case (Equation 51.
FIGURE 14
'Q'.:~'~
tQ(m;n)
_
_ ___________________ _
c
:
NfC to(min)
FIGURE 11
fa
fO(max)
to(m;nl:
~
u---~___t_~nH~~_~
,,
:a(m~XI ~m~
,'
Q(mln)~
(N - l ) f e
to
NfC
(N + 1) fC
The most likely reasons for a "latched up" state in a
harmonic loop are turn-on transients and loop overshoot
when changing frequency abruptly from One end of the
range to the other.
SUMMARY OF SYNTHESIS PROCEDURE
1. Compute harmonic number N
FIGURE 12
Toward
Toward
Latch up
Lock-up
N
< fO(minl
- fl
2/lfO
Lock
Point
where /lfO = change in output frequency
fl = channel spacing
to
fQ{min)
2. Compute minimum mixing frequency fC
NfC - fQ(min)
fO(minl - fl
fC=----'--'---N
10 (min)
to
3. Calculate feedback divider's maximum value
/lfO
Pm ax
= --
+ Pmin
fl
FIGURE 13
where Pmin = 1 for minimum fC-
Lock
Point
I
Toward I Toward
Lock-up I Latch-up
4. Find maximum divide-by-P frequency
-+--
fO(max) = /lfO + fl
5. Calculate allowable VCO swing
,Q,...{----- ---
NfC - fl
T
to(max)
(N + 1) fC - fQ(max)
< fVCO < (N
+ 11 fC - fO(max)
6. If the above constraints are too tight choose the next
lower number for N and repeat steps 2 and 5 until
satisfied.
6-21
MC12000 (continued)
SKIP-LOCK TUNING
Harmonic mixing provides an alternate means to frequency synthesis without the feedback divide-by-P network. In th is instance the design objective is to provide
a large frequency coverage with a set (and relatively wide)
channel spacing. The configuration is identical to a single
frequency PLL (Figure 15) except it operates in the harmonic mode and tuning is accomplished at the veo. Output frequency is fixed as being f 1 above all harmonics of
fe. As the veo is tuned through its range, the loop will
acquire and lose signals spaced fe apart. Since these must
be some frequency for the phase detector to operate with,
the output frequency cannot be a direct harmonic of fe.
This facet of the circuit often causes users to refer to fl
as the" offset" frequency.
The value of fl is often dictated by output frequency
and channel spacing requ irements. However the relation-
ship of fl to fe has a large effect on the tunability both
up and down the frequency range. If, for example, the
loop were locked at point A (Figure 16) and B were tlie
next desired point, then the veo must be "dragged" from
A to A' before lock can be achieved. This frequency adjustment may be quite critical since the frequency difference between A' and B is only 2fl. If the veo is tuned
past B the opportunity for lock has been passed.
On the other hand, in going from B to A, the upper
end of the veo control range must only cross A' before
the loop acqu ires frequency A. I n either case it's apparent
that the loop will not "jump" from one lock point to
another and some indication of loop lock should be added.
This is normally done by monitoring the veo dc control
line with a pair of comparators and noting when the line
reaches its I im its.
FIGURE 15
FIGURE 16
.
veo
1
Range
I
t------Capture -------.
!
I
,
I
:
(N+2)fC
NfC
MAXIMUM RATINGS
I
Symbol
Ch ..actaristic
Rating
Unit
Ratings above which device lif, may be impaired'
Power Supply Voltage IVCC
I nput Voltage IV CC
=0)
=0)
Output Source Current
Storage Temperature Range
VEE
-8.0
Vde
Vin
10
Oto VIL min
40
mAde
T stg
-55 to +125
°c
Operating Temperature Range
DC Fan-Out' IGates 8nd Flip-Flops)
• AC fan-out is limited by desired system performance.
6-22
Vde
MECL Phase-Locked Loop Components
TWO-MODULUS PRESCALER
MC12012
The MC12012 is a two-modulus presealer which consists of three functional blocks: 1) a controllable divide
by 5/divide by 6 presealer; 2) a divide by 2 presealer; and
3) a MECL to MTTL translator_ When used with the
MC 12014 Counter Control Logic function and the MC4016
programmable counter. a divide by N programmable counter can be constructed for operation to 200 MHz. This
arrangement is especially useful in frequency synthesizer
ilPplications.
LSUFFIX
CERAMIC PACKAGE
CASE 620
PIN ASSIGNMENT
o
I nput Toggle 1
16 VCC
•
-;'2. -;'51+6. -;'10/-;'11. -;'10/-;.12
03 2
15 04
•
MECL to MTTL Translator on Chip
03 3
14 04
•
+5.0 or -5.2 V Operation'
I-I 4
13 E2 MECL
•
200 MHz (typ) Toggle Frequency
(+)
12 CLOCK
MTTL VCC 6
11 E1 MECL
MTTL Output
'When using +5.0 V supply. apply +5.0 V to pin 16 (VCCI and
ground pin 8 (VEE). When using -5.2 V supply. ground pin 16
(VCCI and apply -5.2 V to pin 8 (VEE).
10 E4 MTTL
9 E3 MTTL
VEE 8
FIGURE 1 _. LOGIC DIAGRAM
To obtain an MTTL output connect 5 and 4 to
2 and 3 or 14 and 15 respectively. The MECL
outputs (2, 3, 14, 151 require terminating resistors. When used, the translator (4 and 5) will
provide the proper termination for connection
to IT.
MTTL E4 10
MTTL E3
MECL
to
Toggla
Flip
Flop
9
MECL E2 13
MTTL
Trans
-Iator
MECLE111
12
3 7 1
0303 Input
C
141554
Q4Q4+ -
MTTL
OUT
Toggle
FIGURE 2 - TYPICAL FREQUENCY SYNTHESIZER APPLICATION
VoltegeControlled
Phase
Detector
Oscillator
MC1648
MC4044
6-23
-_f out
f - -....
s:
MAXIMUM RATINGS
R.ting
Unit
VEE
-8.0
Vd,
V,"
Oto VIL min
Vd,
'0
T
20
-55to +125
mAd,
Symbol
C ....ct.. i.ic
n
.....
N
Rati . . . .boWl which device life .... y be imPIJired:
Power Supply Voltage
Input Voltage
(Vee = 01
(Vee = o.
Output Source Current
Storage Temperature Range
s1g
Recommended .... ximum ratings abo". which performance may be d . .aded:
I
I
OperatIng Temperature Range
DC Fan..()ut· (Giltes and F lip-F lops)
I
I
TA
o to +15
10
I
I
0
.....
N
e:;-
°c
°c
0
l
I
-AC fan-out is limited by desired system performance.
ELECTRICAL CHARACTERISTICS
Supply Voltage -5.2 V
Ch.rect_istic
I
Pin
Und.r
Test
Symbol
+25o C
o"c
Min
M..
Min
TV.
8
100
100
200
IINH2
1
11
13
40
40
40
en
'INHJ
9
10
100
100
100
40
40
~
IINH4
4
5
'E
'"
3.5
3.5
IINL1
lea kage Current
11
12
13
1.1
1.1
9
IINL:7
10
4
5
IINL3
OutPUt Voltage
(i)
VOH2
Logic "0"
VOLI
Output Voltage
(i)
logic "0"
Threshold Voltage
I
I
Short Circuit Current
I
Logic "'"
Threshold Voltage
14
15
T
I
VOHA
VOLA
I ~~
14
15
'OS
-1.850
-{l.120
-1.880
-1.595
~
-20
-1.620
t
-4.100
-0.980
-1.615
+
-65
+
-20
VILAlNlx
V,HT
-3.2
V,LT
-4.4
VEE
-5.2
'L
-2.5
IOL
16
IOH
-1.6
-4.1
+0.3
-3.2
-4.4
-5.2
-2.5
16
-1.6
-4.1
+0.3
-3.2
-4.4
-5.2
-2.5
16
-1.6
'L
'OL
IOH
V,L
V,HH
V,HT
V,LT
9
10
4
4
9
10
+
9.10
9,10
11,13
11,13
Vd,
4
+
-4.700
Vd,
11,13
+
+
Vd,
9,10
9,10
+
-65
-20
-1.515
+
-65
•
mAde
16
16
8
8
6
6
1.8
8.11
8,12
8,13
16
8
8
16
16
8
~
~
16
18
2
3
14
15
16
2
3
14
15
16
11,13
11,13
8
2
3
14
15
16
9,10
9,10
+
8
2
3
14
15
16
~
8
~
6
•
•
6
8
9,10
9,10
11.13
11,13
-1.600
8
8
8
+
Vd,
16
16
16
8
Vd,
-{l.920
8
8
8
+
11,13
+
!Vee)
Gnd
6,16
8
8
mAde
mAde
Vdc
VEE
16
mAde
mAde
-1.830
+
VIHAmin
+
•
2.2
2.2
+
-1.020
1
11
13
~Adc
+
-4.700
"Adc
mAde
-2.800
-1.850
V'HH
+0.3
8
12
mAde
•
-1.635
VIHml. VILmin
~Adc
2.0
• • •
• + •
-2.800
Unit
5.5
5.5
0.960
-{l.840
-1.106
-1.045
V,L
-4.1
/lAde
-0.120
-1.810
i
-0.810
VILAma.
-1.490
-1.415
-1.450
mAde
-0.900
2
3
14
15
14 4
15 4
M ••
6.5
4.0
-2.800
I~
Min
-0.810
1
1
VOL21
25"c
75°C
VIHAmin
-1.145
I
TEST VOL TAGE/eURRENT APPLIED TO PINS LISTED BELOW,
3.8
2.0
-1.000
VOHl
Logic "',.
-1.810
+15"c
Mo.
12
Input Current
-0.840
MC12012
1"NHl
Power Supply Drain Current
VIHmax VILmin
:::J
I
mA
Volts
@Test
Temperatur.
oOe
:::J
....
I
TEST VOL TAGE/eUAAENT VALUES
+
8
c:
It!
a.
...3:
o...
(')
N
N
8
::J
~.
::J
TEST VOLTAGE/CURRENT VALUES
mA
Volts
@Test
Temperatur.
O·C
ELECTRICAL CHARACTERISTICS
Supply Voltage +5.0 V
25"C
7SoC
Pin
Power Supply Dr.in Current
Input Current
Symbol
T...
IE
8
12
IINHl
IINH2
Q)
N
UI
Leakage Current
logic "'"
Output Volta.
Logic "',.
-
tlNH4
4
5
1
11
12
13
-
-
-
IINL2
9
10
-
-
I'NL3
4
5
-
-
VOH1
(2)
VOLl
2
3
14
15
1
®
2
3
14
15
VOL2
1
VOHA
1~'
15 4
Short Circuit Current
-
-
IINLl
VOLA
'OS
l~i®
15
1
+3.170
4.000
4.160
+
+
3.190
3.430
2.400
+
+
0.500
3.980
+
-
-20
Min
-
3.450
+
-65
+5.5
mAde
~Adc
12
~Adc
1
11
13
-
-
-
-
-
-
-
-
-
-
9
10
-
-
40
40
40
100
100
100
40
40
-
2.0
~
-
Min
Max
-
-
-
-
-
Unit
VIHmu VILmin
j.lAdc
-
-
mAde
mAde
5
5
4
4
-
IlAdc
-
-
~
-
2.2
2.2
-
-
mAde
mAde
-
-
-
6.5
4.0
-
-
mAde
mAde
4
4
5
5
11.13
-
-
2.400
4.190
4.100
4.280
Vdc
2.400
-
3.440
3.230
3.410
0.500
-
-
-
-
-20
-
-
3.460
+
-65
-
-
5
4
-
11.13
11.13
Vdc
Vdc
11,13
4
-
5
Vdc
4.080
-
Vdc
+ t + +
t t ,I ,I
t
+
0.500
+
-
+5.0
+0.5
-
4.020
-
to.8
+3.550
200
5.5
5.5
~
+2.0
+3.525
+2.0
95
100
-
3.210
+2.0
VIHT
+5.0
+5.0
IL
-2.5
IOH
-1.6
-2.5
IOL
16
16
-2.5
16
1.6
1.6
IL
IOL
IOH
+7SOC
-
+
+3.955
Vee
VIHH
+5.5
+5.5
Max
-
1.1
1.1
3.8
2.0
4.040
+3.855
+3.895
VILT
to.8
+0.8
VIL
+0.5
to.5
VILAm.x
+3.510
TV.
3.5
3.5
-
VIHAmin
0..
TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW,
+25"C
Max
-
9
10
Threshold Voltage
Logic "0"
Threshold Voltage
oOC
Min
'INH3
VOH2
Logic "0"
Output Voltage
1
11
13
+4.280
MCl2012
lind.,
Characteristic
I:
(I)
VIHm8lC VILmin
+4.160 +3.130
+4.190 +3.150
-
-
3.490
-20
-65
+
Vdc
+
mAde
-
-
-
-
-
5
4
VIHAmin
-
-
VILAma.
VIL
VIHH
VIHT
VILT
VCC
-
-
-
-
6.16
16
-
-
-
-
-
9
10
-
-
-
-
-
9.10
9.10
-
-
16
16
6
6
16
-
-
-
16
16
16
+
16
16
6
6
16
-
-
~
8
8
-
-
-
-
-
-
-
-
-
-
2
3
14
15
11.13
11.13
-
-
-
-
11.13
11.13
-
9.10
9.10
-
-
-
-
-
-
-
,
16
-
I
-
-
-
-
-
-
9.10
9.10
-
-
16
+
16
~
6
------~
-
-
1
6
9.10
9.10
7
2
3
14
15
8
8
8
8
8
8
8
1.8
8.11
8.12
8.13
8
8
8
8
8
6
-
(VEE)
Ond
~
8
,I
8
8
2
3
14
15
-
-
2
3
14
15
-
-
-
8
~
8
+
8
Ch.'lICteristic
Propagotion Deloy
(So. Figures 3 and 41
Output Ri .. Tim.
(See F igur. 41
Output F ell Time
(Soe Figure 41
cp
I\,)
O'l
Sotup Tim.
(See Figure 51
R.I .... Tim.
(See Figure 51
Symbol
'12+2+
'12+3+
'12+
'12+3'1+14+
'1+15+
'1+14'1+15t5+7+
15-7-
12,2
12,3
12,2
12,3
1,14
1,15
1,14
1,15
5,7
5,7
-
'2+
13+
t14+
t15+
2
3
14
15
-
-
-
'2t3'14t15-
2
3
14
15
11,13
9,10
11,13
9,10
-
-
-
-
-
-
-
-
-
-
2
2
14
14
-
'setup 1
tsetup2
Toggi. Frequ.ncy
Figure 6 (751
(761
(+21
Figure 7 (7100r 111
MC12012
+25"<:
+75"<:
Min Typ Mox Min MIX
Pin
Und.r
Test
',.11
t r.12
f max
~
O"e
Min MIx
-
-
2.0
-
-
-
-
--
-
-
-
-
-
-
4.0
7.0
2.5
4.0
-
-
-
-
-
-
3.0
3.0
2.8
2.8
3.0
3.0
2.8
2.8
8.0
5.0
2.0
2.0
2.0
2.0
-
-
-
-
-
-
-
-
12.0
10.0
-
-
-
-
-
-
j
-
-
Unit
ns
12
+
1
t
-
-
A
A
ns
t
-
-
2.0
2.0
2.0
2.0
-
-
-
-
-
-
-
-
2.4
5.0
3.0
7.0
2.0
3.5
-
4.0
8.5
ns
ns
-
2.0
2.0
ns
ns
MHz
-
-
-
-
-
~
-
1.2
2.5
175
200
+
(j) All MECL OUlputs (2,3,14,15) are lerminated 10 VEE Ihrough
an external 510 n resistor during the DC tests.
-
4.0
TEST VOL TAGESIWAVEFORMS APPLIED TO PINS LISTED BELOW:
Pul..
G.n. 1
•
-
-
-
-
-
ns
+
@
12
12
1
1
12
12
1
1
Pul..
Gen. 2
-
-
-
Pul..
Gon.l
VIHmin
+1.100
VILmin
+O.ll0
-
-
11,13
11,13
11,13
11,13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VF
VEE
Vee
-l.OV -3.011'-3.2 +2.0
9,10
9,10
9,10
9,10
-
-
c.
11,13
11,13
9,10
9,10
-
-
11,13
11,13
9,10
9,10
-
-
-
-
-
-
-
-
12
12
12
12
11/13
-
-
9/10
-
11113
-
-
-
9/10
-
-
-
-
-
-
11
-
-
-
-
-
-
n
VILmin
nVIHmax
VILmin
--.J
L
---1
+
6,16
8
+
~
+
8
8
6,16
6,16
13
11,13
9,10
9,10
8
16
+
+
--
L
In addition to meeting the output levels specified, the device
must divide bV 6 during this test. The clock input is
I n addition to meeting the output levels specified, the device
must divide by 5 during this test. The clock input is
6,16
13/11
11,13
nVIHmax
@
8
6,16
6,16
-
--.J
r:::
CD
8
8
In addition t6 meeting the output levels specified the device
must divide by 2 with a clock input of
VILAmax
::J
9,10
10/9
9,10
10/9
13/11
11,13
nVIHAmin
®
::J
!:!.
must be maintained between tests. The clock input is
L
....oN
8'
-
the truth table. All input, power supply and ground voltages
--.J
6,16
-
Test outputs of the device must be tested by sequencing through
VILmin
8
s:(")
....
N
VIHmax
L
MC12012 (continued)
FIGURE 3 - AC TEST CIRCUIT
rtJ
VCC. +2.0 V
6,16
251'F
J
10"I'F
r--------
--------~
I
I
I
I
Pulse
Generator
Vee = +2.0 V
04
11'2
Toggle
o - , - - - - - - - - - - - l c Flip-
(EH 137)
400
Flop
PuIs. Generator '3
(EH 137)
V out
I
D'}------+-<>
Input Pulse
t+ ... t- = S.O±. 0.5 ns
50
04
I
~~(5~)+_------------~+
100
MM06150
MECL
or equiv
to
MTTL
Trans-
(4)
~
A MC10109Lor_.
__q6-u-;v------t . .
MTTL OUT
lator
-
-
~~:±-l~,~.~ :,=:,~
-- ~
MM07000
17)
or equiv
VEE
All input and output cables to the scope are equal lengths of
50
n
coaxial cable.
V
The 950-ohm resistor and the scope termination impedance
All unused cables must be terminated with 50 ohms.
All r.sistors are
= -3.2 or -3.0
wiring, and load capacitance.
constitute 8 20:8 attenuator probe.
+ 1%.
CT :: 15 pF "" total parasitic capacitance which includes probe,
The 50-ohm resistor and the scope termination impedance constitute a 2: 1 attenuatar probe.
FIGURE 4 - AC VOLTAGE WAVEFORMS
Pulse
Generator
1
03
12)
03
13)
04
114)
04
(15)
15)
MTTL
Out
17)
6-27
MC12012 (continued)
FIGURE 5 - SETUP AND RELEASE TIME WAVEFORMS
Pul,.
Generator
1
Pulse
Generator
2
t setup 2
Pul,.
Generator
3
\
03
(2)
Pulse
Generator
1
Pul.e
Genefator
2
Pulse
Generator
3
Q3
(2)
Divide by 5
FIGURE 6 - MAXIMUM FREQUENCY TEST CIRCUIT
cD
CC:+2.0V
25 I'F
J
J 0.1 I'F
r-------
V out V out
--------~
I
I
1
1
1
03 H-o----t---,
1(14)
04r-----------~~-~
<>1---------.,
Toggle
FlipFlop
04r-----~----~>_,
Pul ••
Generator
o1---__________
100
~MECL
(EH 122)
to
MTTL
or equlv
<>-'----------j
(4)L -
-
MTTL OUT
---..=..=J,- - - - - - - __ .J
0.1I'F±
NOTE: Output Waveform. are
Trans
lator
bVEE--3.20r-3.0V
sam a .1 shown in Figure. 4 and 5.
6-28
(7)
100
MC12012 (continued)
FIGURE 7 - MAXIMUM FREQUENCY TEST CIRCUIT
V out
Vee = +2.0 V
50
r-------------
-----,
Q4 15
+MECL
to
Toggle
~~.:~ 17
Flip·
Flop
_ lator
04
Pulse
Generator
1
_ _ -.J
0
(EH 122)
3
2
14
100
"'JlJ
+o~
5
Vee'" -3.2 or -3.0 V
V
NOTE:
For divide by 11 connect 11 to VIL "" +0.130 and 9 and 10 to VF "" -3.0 V
For divide bV 10 connect 11 to VIH
= +1.160 or9 or 10 to VA = 0.0 V
FIGURE 8 - STATE DIAGRAMS
6-29
4
MC12012 (continued)
FIGURE 9 - .;. 5/6
MTTL E4 10
MTTL E3
MECL
MECL E2 13
MECL E1
to
Toggle
Flip
Flop
9
MTTL
Trans
'Iator
11
12
3 2
C
(13
1
141554
Q4Q4+ -
Q3 C4
MTTL
OUT
Divide by 2
use Toggle
Flip·Flop
El+E2+E13 + E4
COUNT
01
Q2
03
6
7
0
1
1
1
1
1
5
1
0
1
1
1
0
0
0
0
0
0
0
1
0
=1
2
".".,:
3
+
E4
=
0
To obtain a MTTL output connect 5 and 4 to
2 and 3 or 14 and 15 respectively.
FIGURE 10 - .;. 10/11
MTTL E4
ECL
to
Togle
Flip
Flop
MECL E2
3 2
C
El + E3 + E4
=1
12
14 155
03 03
03
04
1
1
1
1
1
1
1
1
COUNT
01
02
14
0
15
1
13
1
0
9
8
1
0
0
1
0
0
0
1
10
0
1
0
1
7
1
1
.1
0
5
1
0
1
0
1
1
0
0
0
0
0
0
0
0
2
0
1
0
0
To obtain a MTTL output connect 5 and 4 to
14 end 15 respectively.
6-30
TTL
Translator
C4
04
4
04
MTTL
Out
E 1 + E3 + E4= 0
MC12012 (continued)
FIGURE 11 - - - 10/12
MTTL E4 10
MTTL E3
MECL
to
Toggle
Flip
Flop
9
MECL E2 13
MTTL
Trans
-Iator
MECL El 11
12
To obtain
8
MTTL outPut connect 5 and 4 to C
14 and 15 respectively.
,-------I4=~=EEE~jij~8----1
El + E2+ E3+ E4= 1
FIGURE 12 -- 20/21
~~~
~l
% MC3060
~
MTTL E4 10
MTTL E3
9
l-
03
f-4
~
'------.J
rt-I~
El+E3
2 1
~C4
03
z
1
COUNT
01
02
03
04
05
30
31
29
0
1
,
1
1
,
1
0
1
1
1
25
24
26
23
21
1
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
1
,
1
0
0
1
1
17
16
18
1
0
0
0
0
0
0
0
0
1
1
,
0
,
0
1
0
0
0
'5
'3
9
8
10
7
5
1
0
2
,
,
,
0
0
1
1
1
0
0
1
0
1
0
0
0
1
,
0
0
0
1
,
1
,
,
0
0
0
1
1
1
1
0
0
0
0
0
0
0
D
,
6-31
14
04
to
C
-Iator
+ -
El + E3 = 0
0
'---
554
04
1
0
0
0
0
0
0
MECL
~
1
"0
L~ ~
r---MTTL
Trans
~
03
C
f--- .--
-
3
12
To obtain a divide by 20/22 omit as to 10.
To obtain a divide by 20124 omit 14 to 13.
Toggle
Flip
Flop
.--
MECL E213
MECL E 1 11
r----
7
MC12012 (continued)
FUNCTION DESCRIPTION
INTRODUCTION
The MC12012 isone part of a variable modulus (divisor)
prescaling subsystem used in certain Digital Phase-Locked
Loops (PLL).
More often than not, the feedback loop of any PLL
contains a counter·d ivider. Many methods are available
for building a divider, but not all are simple, economical,
or convenient in a particular application.
The technique and system described here offer a new
approach to the construction of a phase· locked loop divi·
der. In addition to using the MC12012 variable modulus
prescaler, this system requires an MC12014 Counter Con·
trol Logic function, together with suitable programmable
counters (e.g. MC4016s). Data sheets for these additional
devices should be consulted for their particular functional
descriptions.
THE MC12012 TWO MODULUS PRESCALER
Three functional blocks are contained in the MC12012
variable modulus prescaler: 1) a controllable 75/76 pre·
scaler; 2) a 72 prescaler; and 3) an ECL to TTL translator
(for single power supply operation).
Selection of division by 5 or by 6 is made by inputs
to E 1 through E4. I f all E inputs are low before the tran·
sition of the clock pulse driving 03 high, 03 will stay
high for 3 clock pulses, then will go low for 3 clock pulses.
This provides a divide by 6 function.
On the other hand, if anyone or all of the E inputs
are high prior to the positive transition of the clock pulse
driving 03 high, 03 will stay high for only 2 clock pulses,
then will go low for 3 clock pulses. The result is division
by 5.
For the 75 operation, at least one of the E inputs must
go high sometime before the clock pulse. This time is
referred to as the "setup time." Specifications for setup
time are given in the electrical characteristics table: tsetup 1
and t se tup2 for El and E2 (MECL inputs), and E3 and
E4 (MTTL inputs).
For the divide by 6 operation all E inputs must be low
for some time prior to the clock pulse. This time is reo
ferred to as the "release time." Data for release time is
given in the electrical characteristics table; tre 1 and t re 2
for E 1, E2, E3, E4.
The data given in the tables for setup and release times
are referenced to the positive transition of the clock pu lse
causing 03 to go high. If it is necessary to reference the
setup and release times to the positive transition of 03,
add t++ (specified for 03) to the setuplrelease times given.
It should be noted that the logic states for the enable
inputs are important only for only one clock pulse which
causes 03 to go high (within the limits specified by setup
and release times).
The 7 5/7 6 prescaler may be connected externally to
the 7 2 prescaler to form a 7 10/7 11 prescaler (Figure 10)
ora7 10/712 prescaler (Figure 11).
By way of an example showing how a 7 10/7 11 pre·
scaler operates, note that if El, E3, and E4 (Figure 10)
are held in a low state, the counter divides by 11. To do
this, a feedback connection is established from 04 to E2
(or to Ell. With this feedback, the 75/76 prescaler di·
vides by 5 when 04 is high, and by 6 when 04 is low.
Since 04 changes state with each positive transition of
03, the prescaler alternates between 7 5 and 7 6 resulting
in a 7 11 at 04.
If anyone or all of the E inputs are high (Figure 10),
the 5/6 prescaler always divides by 5 and a divide by 10
results at 04.
With the addition of external flip·flops and counters
(MECL or MTTL) various other modulus prescalers may
be produced (20/21,20/22,20124,40/41,50/51, 1001
101, etc.).
THE TECHNIQUE OF DIRECT PROGRAMMING BY
UTILIZING A TWO MODULUS PRESCALER (MC12012)
The disadvantage of using a fixed modulus (7 P) for
frequency division in high frequency phase·locked loops
(PLL) is that it requires dividing the desired reference
frequency by P also (desired reference frequency equals
channel spacing.)
The MC12012 is specially designed for use with a tech·
nique called "variable modulus prescaling". This technique
allows a simple MECL two·modulus prescaler (MC12012)
to be controlled by a relatively slow MTTL programmable
counter. The use of this technique permits direct high·
frequency prescaling without any sacrifice in resolution
since it is no longer necessary to divide the reference fre·
quency by the modulus of the high frequency prescaler.
6·32
MC12012 (continued)
The theory of "variable modulus prescaling" may be
explained by considering the system shown in Figure 13.
For the loop shown:
fout = N. p. fref
to multiply by a fractional number, equation 4 must be
synthesized by some other means.
Taking equation 3 and adding ±AP to the coefficient
of fref, the equation becomes:
(1)
fout = (Np • P + A + A • P - A. P) fref.
(5)
FIGURE 13 - FREQUENCY SYNTHESIS BY PRESCALING
Collecting terms and factoring gives:
fout""Nepefref
Reforonco@-ha-ase
. F Is)
veD
Frequencv ~
(fref)
fout= [(Np - A) P+ A (P+ 1)] fref
/
oet.
(6)
From equation 6 it becomes apparent that the frac·
tional part of N can be synthesized by using a two·modu·
Ius counter (P and P + 1) and dividing by the upper modu·
Ius, A times, and the lower modulus (Np - A) times.
This equation (6) suggests the circuit configuration in
Figure 15. The A counter shown must be the type that
FIGURE 15 - FREQUENCY SYNTHESIS BY TWO
MODULUS PRESCALING
where P is fixed and N is variable. For a change of 1 in N,
the output frequency changes by P • fref. If fref equals
the desired channel spacing, then only every P channel
may be programmed using th is method. A problem reo
mains: how to program intermediate channels.
One solution to this problem is shown in Figure 14.
Frequency
(frof)
FIGURE 14 - FREQUENCY SYNTHESIS BY PRESCALING
Roference &@-ha--fOU'=N-\frOf
Fr.qu.ncv~ -;-p
(f re 1)
ase
F (s)
veo
Det.
N""' N p • P+A
counts from the programmed state (A) to the enable state,
and remains in this state until divide by Np is completed
in the programmable counter.
In operation, the prescaler divides by P + 1, A times.
For every P + 1 pulse into the prescaler, both the A coun·
ter and Np counter are decremented by 1. The prescaler
divides by P + 1 until the A counter reaches the zero state.
At the end of (P + 1) • A pulses, the state of the Np
counter equals (Np - A). The modulus of the prescaler
then changes to P. The variable modulus counter divides
by P until the remaining count, (Np - A) in the Np counter,
is decremented to zero. Finally, when this is completed,
the A and Np counters are reset and the cycle repeats.
To further understand this prescaling technique, consi·
der the case with P = 10. Equation 6 becomes:
A .;. P is placed in series with the desired channel spacing
(frequency) to give a new reference frequency: channel
spacing/Po
Another solution is found by considering the defining
equation (1) for fout of Figure 13. From the equation
itmay be seen that only every P channel can be programmed
simply, because N is always an integer. To obtain inter·
mediate channels, P must be multiplied by an integer plus
a fraction. This fraction would be of the form: A/P. If
N is defined to be an integer number, Np, plus a fraction,
AlP, N may be expressed as:
N = Np+ AlP.
Substituting this expression for N in equation 1 gives:
or:
fout = (Np + A/P) • P. fref
(2)
fout = (Np P + A) • fref
(3)
fout = Np. P • fref + A. fref.
(4)
fout = (A + 10 Np). fref
If Np consists of 2 decades of counters then:
Np = 10 Npl + NPO
(Npl is the most significant digit),
Equation 4 shows that all channels can be obtained directly
if N can take on fractional values. Since it is difficult
and equation 7 becomes:
6-33
(7)
MC12012
(continued\
FIGURE 16 - DIRECT PROGRAMMING UTILIZING
TWO-MODULUS PRESCALER
2:0
2:,
Eo
2:2
L.E
-
MC12D12'
MTTL out
r---
®
2:3
®
fin
PO
C,
MC12014
P'
'Connected
fout
P2
f01"710/11
r-
LOOQ'OO~~
000,0203
MC40,8
'--C
C
MC40'6
P3
B'
Be---<
C
MC40'8
_ R
fiE
fiE
PE
t , , t1
r r 1r t
-
t t ttl
I I I I
I I I I
N'
A
@
c----<>--
NO
FIGURE 17 - WAVEFORMS FOR DIVIDE BY 43
11 Pulsel
I
11 Pulses
11 Pulse!
I
10 Pulses
11 Pulses
11 Pulses
11 Pulses
fin
®
®
©
1 CYcle = 43 Pulses
r
f out
FIGURE 18 - WAVEFORMS FOR DIVIDE BY 42
11 Pulses
11 Puls.s
10 Pulses
I
10 Pulses
I
11 Pulses
10 Pulses
11 Pulses
I
fin
®
®
©
1 Cycle = 42 Pulses
I-
1
tout
·1
1
,--
FIGURE 19 - WAVEFORMS FOR DIVIDE BY 44
11 Pulses
®
®
©
I
11 Pulses
11 Pulses
,.
11 Pulses
I
11 Pulses
1 CYcle - 44 Pulses
f out
6-34
11 Pulses
11 Pulses
I..._ _ _--'r
MC12012 (continued)
and the A counter goes to O. The zero state of the
A counter is detected by the MC12014, causing point
@to go to 1 and changing the modulus of the MC12012 to
10 at the start of the cycle.
When fout goes low, the programmable counters are
reset to the programmed number. After 11 pulses (the
enable went high after the start of the cycle and therefore
doesn't change the modulus until the next cycle), point
makes another positive transition. This positive transi·
tion causes fout to return high, release the preset on the
counter, and generates a pulse to clear the latch (return
point ® to 0).
After 10 pulses the cycle begins again (point
was
going high). The number of input
high prior to point
pulses that have occured during this entire operation is:
11 + 11 + 11 + 10 = 43. Figures 18 and 19 show the
waveforms for divide by 42 and divide by 44 respectively.
fout = (100 Npl + 10 NPO + A) fref.
To do variable modulus prescaling using the MC12012
and programmable divide by N counters (MC4016,
MC4018, one additional part is required: the MC12014
(Counter Control Logic).
In variable modulus prescaling the MC12014 serves a
dual purpose: it detects the terminal (zero) count of the
A counter, to switch the modulus of the MC 12012; and
it extends the maximum operating frequency of the pro·
grammable counters to above 25 MHz. (See the MC12014
data sheet for a detailed description of the Counter Con·
trol Logic).
Figure 16 shows the method of interconnecting the
MC12012, MC12014, and MC4016 (or MC4018) for vari·
able modulus prescaling. To understand the operation of
the circuit shown in Figure 16, consider division by 43.
Division by 43 is done by programming Npl = 0, NPO = 4,
.nd A= 3.
Waveforms for various points in the circu it are shown
in Figure 17 for this division. From the waveforms it
may be seen that the two·modulus prescaler starts in the
divide by 11 mode, and the first input pulse causes point
A to go high. This positive transition decrements the
Np counter to 3, and counter A to 2.
After 11 pulses, point ® again goes high; the Np
counter decrements to 2 and the A counter to 1. The
"2" contained in the Np counter enables the inputs
to the frequency extender portion of the MC12014. After
11 more pulses point ® goes high again.
With this position transition at ® ' the output (fout)
of the MC12014 goes low, the Np counter goes to 1,
®
®
®
The variable modulus prescaling technique may be used
in any application as long as the number in the Np counter
is greater than or equal to the number in the A counter.
Failure to observe this rule will result in erroneous results.
(For example, for the system shown in Figure 16 if the
number 45 is programmed, the circuit actually will divide
by 44. This is not a serious restriction since Np is greater
than A in most applications).
It is important to note that the A counter has been
composed of only one counter for discussion only; where
required, the A counter may be made as large as needed
by cascading several programmable counters. Figure 20
shows the method of interconnecting counters. Opera·
tion is previously described. The number of stages in the
A counter should not exceed the number of stages for the
FIGURE 20 - METHOO OF INTERCONNECTING COUNTERS
zo
Zl
Z2
Z3
B2
f' n MC120l4
PO
PI
,...----. P2
f out
EOU
I
E MTTLoutl
C~C12012
fin
I
yc I~ ~"
MC40l~B t-:c:a~~J
h
00010203
MC40,;1
PE
,
ffLP
03
B
MC40'63
PE
fffff
I lA'
C
PE
V
~
C
I
A2
,
I
I
Q3
B
,--'
Lt
fftU
TTTft
Tffff
NpO
Np,
Np2
v
A Counter
Np Counter
A- '00A2+ lOA, + AD
Np
6-35
~
____ ~EJ
PE
PE
,
,...---1-
1 --Q3--l:
03
C
PE
I
------,
MC40~ Yc MC4016~ MC4016{~ MC40'6~:J
,----
00Q1Q2Q3
T'TT~"
II
1
t tf t f
I
r=~
------~
03
f out
'00 Np2 + '0 Np, + NpO
:::::
-I-rrr"'-,
MC12012 (continued)
FIGURE 21 - DIRECT PROGRAMMING 100-200 MHz SYNTHESIZER IN 50 kHz STEPS
50kHz
Reference
f out - 100 to 200 MHz
VCO
MCI648
F(I)
Frequency
in 50 kHz
step,.
+ 10/+ 11
MTTL
100 MHz
10MHz
1 MHz
100kHz
60 kHz
·Used·1II Modulus Two Programmable Count.r.
Also could u .. MC4017.
FIGURE 22 - FM BAND SYNTHESIZER WITH 10.7 MHz I.F. OFFSET
MC4044
f - - - - -...... f out
DIAL
IT]
DIAL
0 0 1
0
0
0 1 1
0
2
3
4
5
6
7
8
9
0 0 0 0
0 0 0
0 o 1 0
0 0 1 1
0 1 0 0
0 1
0
0
0
0 1
0 o 0
1 0 o 1
.3
.5
.7
CD
.9
6-36
1
1
1
0 1
1 0
0
0
0
0
0
1
1
0
0
1
0
1
0
&
98.8-118.6 MHz
in 200 kHz steps.
MC12012 (continued)
Np counters. As many counters as desired may be cascaded, as long as fan-in and fan-out rules for each part
are observed.
The theory of "variable modulus prescaling" developed
above, examined a case in which the upper modulus of
the two-modulus prescaler was 1 greater than the lower
modulus. However, the tedhnique described is by no means
limited to this one special case. There are applications
in which it is desirable to use moduli other than P/(P + 1).
It can be shown that for a general case in which the
moduli of the two-modulus prescaler are P and P + M,
equation 6 becomes:
From equation 8 it may be seen that the upper modulus
of the two-modulus prescaler has no effect on the Np
counter, and that the number programmed in the A counter is simply multiplied by M.
APPLICATIONS
There is no one procedure which will always yield the
best counter configuration for all possible MC12012 applications, Each designer will develop his own special design
for the counter portion of his PLL system.
An insight into some of the various possible counter
schemes may be obtained by considering the various PLL
systems shown in Figures 21,22, and 23. These examples
were chosen to show some of the moduli that may be
obtained by using the MC12012.
f out = [(Np-A)P+A(p+M)Jefref
or
(8)
fout = [Np e P + M e AJ e fref.
FIGURE 23 - UHF SYNTHESIZER USING 10112 COUNTER
f out
MC4044
= 103.2-186.0 MHz
in 1.2 MHz step •.
\
600 kHz
f out ::: 516-930 MHz
in 6 MHz steps.
I.F. Strip
SWITCH
READING
1
2
3
4
5
5
1
8
0 0
0 0
0
0
1 0
1 0
1 1
1 1
0
0
0
2
3
4
0
1
0
5
6
1
8
9
6-37
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1 0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
MECL Phase-Locked Loop Components
PHASE-FREQUENCY
DETECTOR
MC12040
The MC12040 is a phase-frequency detector intended for use in systems requiring zero phase and
frequency difference at lock. In combination with a
voltage controlled oscillator (such as the MC16481,
it is useful in a broad range of phase-locked loop
applications. Operation of this device is identical to
that of Phase Detector #1 of the MC4044. A dis·
cussion of the theory of operation and applications
information is given on the MC4344/4044 data sheet.
CERAMIC PACKAGE
CASE 632-02
VCC1
•
Operating Frequency
=
80 MHz typical
14
VCC2
NC
2
13
NC
U
3
12
D
U
4
11
0
NC
5
10
NC
R
6
VEE
9
V
8
NC
NC - No Connection
--....o-~--o 4 U (IR> Ivl
./'----0
R60----/
V90----\
3
0
(IR > IVI
12DIIV>IRi
VCC1 = Pin 1
VCC2 = Pin 14
VCC3 = Pin 7
6-38
MC12040 (continued)
ELECTRICAL CHARACTERISTICS
INPU
00
01
1 1
o 1
1 1
o
1
R
6
U
4
o
3
1
1
1
1
o 1--11
o
1
9- V
OUTPUT
TRUTH TABLE
RVUOOO
The MC12040 has been designed to meet the de specifications shown in the test table after thermal equilibrium
has been established. Outputs are terminated through a
50 ohm resistor to +3.0 V for +5.0 V tests and through
a 50 ohm resistor to -2.0 V for -5.2 V tests.
XXXX
XXXX
X X X X
'X X X X
1 0 0 1
This is not strictly a functional
truth table; Le., it does not cover
all possibile modes of operation.
However it gives a sufficient num·
ber of tests to ensure that the de-
1
1
0
1
1
0
0
o
1
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1 1
1 0
l O X " " Oon't Care
1
1
1
0
0
0
1
1
0
1
1
1
[jf---12
0
vice will function properly in all
modes of operati on.
0
0
0
TEST VOLTAGE VALUES
IVoh11
.T",
Temptr.tu ..
OOc
,.·c
Supply VOltage .. -S.2V
75"0
MCl2040
Pin
Symbol
Pow.r Supply Ora," Current
Und.r
Test
M.x
Min
Typ
-90
'e
Input Current
VIL min
VIMA "un
VILA m..
VEE
-0840
-1870
-1.145
-1490
-52
-0810
-1.850
-1.105
-1475
-52
-0 720
-1 830
-1.045
1.450
-5 2
TEST VOLTAGE APfiLIED TO PINS LISTEO BELOW:
oGe
Min
VIM m..
M ..
Unit
-120
mAdc
VIH max
VIL min
VIHA mIn
VILA m..
VeE
1,14
1,14
350
350
1,14
os
os
LogIc "1"
Output Voltage
-1000
-0840
~
~
~
-1.870
-1.635
-1.850
-1.620
11
12
LClglc "0"
Output Voltage
~
4
11
12
L09'c ''1''
-1.020
OHA(l:
-0810
-0960
J,lAdc
1,
J,lAdc
1,14
114
-0900
-0.720
Vd<
~
j
-1.830
-1595
Vd,
1.14
~
~
~
-0.980
-0.920
Vd<
~
6,9
11
12
LOllI(: "0"
Threshold Voltage
12
1.14
~
~
Threshold Voltage
1Vee'
Grtd
-1.615
-1600
-1575
Vdc
1.14
~
~
~
~
~
TEST VOLTAGE VALUES
!Votu'
fitTest
T,ml"'r.tu.,
O·C
25'C
Supply Voltage = +S.OV
7S Cl C
MC12040
p,"
Symbol
Power SupplV
O'~ln
Current
Under
Tesl
-85
OS
4000
4.160
~
~
3.190
3.430
3.210
12
LogIC "0"
Output
~
Voll~ge
11
12
LogIC ", ..
!vOHA@:
4.040
3.440
1
12
+3.550
+5.0
VIL mIn
VIHA mIn
VILA m..
Vee
,Ad<
1,14
1.14
1,14
U4
1.14
!
~
3.230
3.470
1,14
~
~
j
Vd<
'6.9
~
3.450
3.460
3.490
Vdc
~
~
~
~
:_.Q) Outputs of the device must
®
+5.0
Ad,
J,lAdc
J,lAdc
~
11
12
Threshold Vollage
+3.510
+3525
4280
4080
Th!e$hold Voltage
LogIC "0"
+3.855
+3895
+3.955
4.100
T~
4.020
3.980
Vee
+3.130
+3.150
+3.170
1,14
350
350
11
VILA m..
+4.160
+4190
+4.280
-lIS
os
Lqglc"I'
Oulpur Voltage
VIHA mIn
VIH max
-60
',""ut Current
.
VIL mIn
TEST VOL TAGE APfiLIED TO PINS LISTED BELOW'
M ••
'e
VIH m..
be tested by sequencing through .the truth table. All input. power supply and ground voltages
must be maintained between tests.
The device must also function according to the truth table during these tests.
6-39
1.14
(VEE]
Gnd
MC12040
(continued)
AC TESTS
To Scope Channel A
6.01'F
1
1
0 1
.
I'F
14
6
U
R
U
3
To Scope Channa' B
11
0
0 ) - - - -.....- - 0
v
0
0.1
12
Vee ". -3.2 or -3.0 V
NOTES,
.f.
Pul ••
Gen. 1
1. All input and output cables to the Icope
equal lengths of 50
n
+0.3V
coaxial cable.
\-----+I.IV
2. Unused input and output. are connected
to a 50 n resl'tor to ground.
Pulse
Gen. 2
'-'-= ___-X'-_ _ _ _
3.
The device under test mUlt be precondi·
tioned before performing the Be tests.
Preconditioning may be accomplished by
+0.3V
Output
applying pulse "en8rator 1 for I minimum
of two pulses prior to pulse "enerator 2.
The device mUlt be preconditioned again
Waveform A
when inputl to pins 6 and 9 are interchanged. The ••me technique applies.
Output
Waveform B
TEST VOLTAGES!WAVEFORMS
Pin
Cher.n.-Ntic
Propeption Delay
Symbol
....+
1&+12+
'11+31&+111&+11+
'9+3+
'9+12OutpUt Ri. Tim.
Output F.II Tim.
Und.
Ton
6.4
6.12
6.3
6.11
9.11
OUtpu'
Pu_
Mo. Unit Gen. 1
+1&OC
Min
Mo.
Min
Typ
Mo.
Min
8
-
2.8
4.5
2.8
4.8
2.8
4.5
2.8
4.8
2.4
1.6
2.6
1.6
2.8
1.6
2.6
1.6
2.8
-
0.8
1.5
2.8
4.5
2.8
4.8
2.8
4.5
2.8
4.8
2.4
-
3.8
5.7
3.8
6.1
3.8
5.7
3.8
6.1
3.1
-
3.1
A
A
8
8
-'3+
'4+
t11+
t12+
3
4
11
12
A
'3_
3
4
A
t1'_
t12_
oac
w.."orm
9,3
9.12
9,4
<4-
APPLIED TO PINS LISTED BELOW:
MC12CMO
+:z&OC
A
A
8
8
8
A
l'
8
8
12
A
-
-
-
-
-
-
III
1 I I
2.4
0.8
6-40
1.5
1
2.4
-
1 --
6
6
9
9
7
1.14
6
6
9
9
7
no
1 1
Vee
+2.0 V
1,14
6
9
6
9
9
6
9
8
no
VEE
-3.0 or -3.2 V
7
n.
1 1
Pu_
Gen. 2
9
6
9
I I
1
1,'4
1
MC12040 (continued)
APPLICATIONS INFORMATION
detector (U and 01. Using this technique the Quiescent differential
voltage to the operational amplifier is zero (assuming matched "1"
levels from the phase detector). The 0 and [) outputs are then used
to pass along phase information to the operational amplifier. Phase
error summing is accompHshed through resistors .A 1 connected to
the inputs of the operational amplifier. Some A-C filtering imbedded within the input network (Figure 2) may be very beneficial since the very narrow correctional pulses of the MC12040
would not normally be integrated by the amplifier. General design guides for calculating A1, A2, and C are included in the
MC4044 data sheet. Phase detector gain for this configuration is approximately 0.16 volts/radian.
System phase error stems from input offset voltage in the operational amplifier, mismatching of nominally equal resistors, and
mismatching of phase detector "high" states between the outputs
used for threshold setting and phase measuring. All these effects
are reflected in the gain constant. For example, a 16 mV offset voltage in the amplifier would cause an error of 0.016/0.16 =
0.1 radian or 5.7 degrees of error. Phase error can be trimmed to
zero 'initially by trimming either input offset or one of the threshold
resistors (R1 in Figure 2), Phase error over temperature depends
on how much the offending parameters drift. If better performance
were desired. the "charge pump" concept of the MC4044 could be
implemented and subsequent errors could be reduced considerably
since offsets no longer enter the picture.
The MC12040 is a logic network designed for use as a phase
comparator for MECL-compatible input signals. It determines the
"'ead" or "lag" phase relationsh ip and the time difference between
the leading edges of the waveforms. Since these edges occur only
once per cycle. the detector has a range of i211' radians.
Operation of the device may be illustrated by assuming two
waveforms. R and V (Figura 1), of the same frequency but dif-
fering in phase.
R
If the logic had established by past history that
was leading V, the U output of the detector (pin 4) would pro-
duce a positive pulse width equal to the phase difference and the 0
output (pin 11) would simply remain low.
On the other hand, it is also possible that V was leading A
(Figure 1), giving rise to a positive pulse on the 0 output and a con~
stant low level on the U output pin. Both outputs for the sample
condition are valid since the determination of lead or lag is dependent on past edge crossing and initial conditions at start-up. A
stable phase-locked loop will result from either condition.
Phase error information is contained in the output duty cycle that is, the ratio of the output pulse width to total period. By
integrating or low~pass filtering the outputs of the detector and
shifting the level to accommodate Eel swings, usable analog information for the voltage-controlled oscillator can be developed. A
circuit useful for this function is shown in Figure 2.
Proper level shifting is acomplished by differentially driving the
operational amplifier from the normally high outputs of the phase
FIGURE 1 - TIMING DIAGRAM
R_~--v ___ ~-
--j
(0
r- Lead
.JnL_____-Jn._
1.C --U
~u;:~~s= ~.o:)Jl'-_____
V leads A
(U Output =: "0")
Lag
FIGURE 2 - TYPICAL FILTER AND SUMMING NETWORK
c
3
u f-o-r'Mr'T""'Nv-~-I
>-0....__.. To
MC12040 510
6-41
VCO
MTTL Phase-Locked Loop Components
CRYSTAL OSCILLATOR
M C12 060. M C12 5 60
MC12061·MC12561
The MC12060/12560 and MC12061/12561 are designed for use with an
external crystal to form a crystal controlled oscillator. In addition to the
fundamental series mode crystal, two bypass capacitors are required (plus
usual power supply pin bypass capacitors). Translators are provided internally
for MECL and IiIITTL outputs.
•
Frequency Range = 100 kHz to 2.0 MHz for MC12060/12560
= 2.0 MHz to 20 MHz for MC12061/12561
•
Temperature Range = -550 C to +125 0 C for MC12560, 61
=
to +700 C for MC12060, 61
•
Single Supply Operation: +5.0 Vdc or -5.2 Vdc
•
Three Outputs Available:
1. Complementary Sine Wave (600 mVp-p typ)
2. Complementary MECL
3. Single Ended MTTL
L SUFFIX
CERAMIC PACKAGE
CASE 620
,- ,~''''
ooc
PLA~T~~::~KAGE
1
MC12060/MC12061onlv.
FIGURE 1 - BLOCK DIAGRAM
Bias
Bypass
0.1 jlF
AGC
Filter
0.1 jlF
VCC
--
Sine Wave
Output
MECL
+
1 VCC
4
3
2
14
11
VCC
MECL
to
MTTL
10
Trans-
MTTL
Output
lator
Note: 0.1 ",F power supply
pin bypass capacitors
not shown.
TYPICAL CIRCUIT CONFIGURATIONS
FIGURE 2 SINE WAVE OUTPUT
CRYSTAL
REQUIREMENTS
Note: Start-up stabilization
time is a function of
crystal series resistance.
The lower the resistance,
Note: 0.1 JlF power supply pin bypass capacitors not shown.
FIGURE 3 - MTTL OUTPUT
FIGURE 4 - MECL OUTPUT
1+5.0 V Supply)
Characteristic
MC12060112560
FIGURE 5 - MECL OUTPUT
1-5.2 V Supply)
MC12061/12561
Fundamental Series Resonance
Mode of Operation
100 kHz - 2.0 MHz
Frequency Range
Series Resistance, Al
2.0 MHz - 20 MHz
Minimum at Fundamental
the faster the circuit I-M':":"':":'"'-'-=Ef'-'f::....:'-'·'-R'-'--·---R-----1t-----4-k-o-h-m-'----.-----15-5-0-hm-'-----1
stabilizes.
aXlmum
ectlVe
eSlstance,
E(max)
6-42
3:3:
ELECTRICAL CHARACTERISTICS
......
(')(')
NN
Vee
00
F,11 ... Si .... W ....
0')0')
01,.F
.....0
3:3:
......
NN
(')(')
UIUI
0')0')
"'0
nO
::J
~.
::J
C
(I)
TEST VOLTAGE/CURAENT VALUES
....
Volt,
Unt
T.ml"'~':~
MC12560, MC12561
0)
.;.
w
MCl2080. MCl2061
Vee
VIHm. . VILmin VIHAmin VILAlMx VIHT VCCL
4.07
3.18
3.72
3.49
+25o C '
+12SoC
4.19
3.21
3.90
3.52
4.37
4.16
4.19
3.25
3.19
3.21
4.03
3.86
3.90
3.60
3.51
3.52
+7S o C
4.28
3.23
3.96
3.55
4.0
I+a~
4.0
4.5
5.0
4.0
4.5
4.0
4.0
4.0
4.5
4.75
4.75
4.75
C.
VCCH IOl
10H
IL
5.5
1'6
-0.4
-2.5
5.0
5.5
16
-0.4
-2.5
5.0
5.0
5.0
5.5
5.25
5.25
'6
16
16
-0.4
-0.4
-0.4
-2.5
-2.5
-2.5
5.0
5.25
16
-0.4
-2.5
TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW
C ..... cr.illic
Unit VIHnwli1 VILminl VIHArnmiVllAIM.lVIHT]VCCL! Vee IVCCHlloL
PoWIr Supply Or.m Currenl
- MCI2060112560
- Mel 2061/12561
ICC
InPIJtCurrent
'INH
"NL
Olfferentlel Othet Volt9
MCl2060112560
MC12061112561
Output Voltege Lel/el
.Y
I
-
-
-220
-100
2 to 3
I
VOM,.I
VOH2
VOl1-
16
23
30
19
~
40
VOl2
VOHA
Logic "0" Threshold VoltegB:
VOLA
Output Short-Circuit Current
'os
-
-
-
13
18
-
"'220
+100
16
n
19
~
-
-
30
40
-
-
-
-
2.4 I -
2.4 I -' I 2.4
I 2.4
12
13
10
4.02·
4.02
J.41
J.41
20
60
~~I=I~~I=I~:
4.15
3.98
4.15
3." -
-
-
2.4
3.00.
3.00
3.441 3.041 J.50 12.981 J.4J
J.44 3.04 3.50 2.98 3.43
12 12"'13.3913.00
2.97 3.39 3.00' 10
0.5
10
0.5
g I~::I -
14
15
- 1:::~
14
15
15
15
14
J.46'
• J.46
-
60
20
20
-Devices will meet st.ncMrd MECl logic levels using VEE = -5.2 Vdc end Vee '" O.
3.52
3.52
60
I:~~'
:~:1
-
= I~::'
-
6O~.1
20
20
I Ydc
14
15
14
14
1.
15
14
15
15
-
- • 4.081 - I
4.081 - I
~::: I
60
1
1
60
1mAdcl
15
-
14
14
15
14
15
14
15
,.
...•••
-
8,14
• 8,15
•
+
+
,.
'11,16'
16
16
..'
.....'
~~
1.
12
13
12
13
- '1\9,10
16
• 11,'6'
12
13
10
1.
1.
,.
15
-
and
-
- "1,161 - ",J6l !g
15
Vdc
Vdc
=I ~::: I ~:~
20
IL
1
••
+
-
I IOH I
16
Yd,
Ydo
2.4 I
,.,.
,.
,.
'11,161
5.6
=1::~:I::!gl::~:1 ~~~I !~
15
~::: I ~:~~ I ~::; I ~:~
14
~:~l = I g::1 ~=~
-
-
mYdc
35
3.5
~; 1~::~I::g~I:::1 =.I::!:I::gl::~;I:::I::!:I:::1
10
.
- I:::~ ,.
1325
-300
-200
3.5
3.5
13
logic "1" Tt'lreshold Volt.
-
1= 1= 1= 1= 1~~ 1= 1= 1= 1= 1= 1=1~~
I :: 1= 1= 1= 1= 1:~ 1= 1= 1=1= 1= 1=1:~
14'0'1-1-140 1-13251 -1- 1-1- 140 I 2t03
Y out
13
18
-
I ::
logic ''1'' Output Volt9
LOgiC "0" Output Volt.
~ I -I -I ~ I ~ I ~ I -I -I -I -I ~ I ~ I ~ I -I -ImAdO'!
1
1
11
-
I
MC12060, MC12560
MC12061, MC12561
(continued)
FIGURE 6 - AC CHARACTERISTICS - MECL AND MTTL OUTPUTS'
Vee"" +2.0 Vdc
+200 mV
0.1jlF
f
16
"
13
450
12
450
10
1.2 k
Pul .. Generator
(EH 137 or Equiv)
2.0
PRF MHz
t- "'" 2.0 ± 0.2
t+
MECL Output
(Pin 13)
---+=""1
t+
tf[-+
50~
t-
n.
t-
outPut--"::"8=-~:':~~-
MECL
(P;n 121
IE
14
_
2:.:0:.:"=-____
L-.---r-~rr~~r=~4:00~~
.--l4--.. . . .~'V--o+~d~
t+
MM06150
or Equiv
MM07000
or EQuiv
VEe
= -3.0
Vdc
-3.0 Vdc
All Input and output cable, to the scope
are equal length, of 50 n coaxial cable.
Unu.,d outputs are connectad to • 50 n
±1% r.sistor to ground.
CT "" 15 pF - total parasitic capacitance
which Includes probe, wiring, and load
capacitance.
C ...... _ _ ic
Propeg.tlonOeI.v
..-,
1'5+10+
'15_10"5+12-
'15-'2+
115+13+
Ri. Time
hUTirne
1'5_13112.
t13+
t12"3-
p~
u....
T. .
,."
"""
"
""
""
....
MCl25l1O. Mel21e'
· ...c
+aGe
T"
JO
"" "
..."
5 .•
4 .•
5 .•
3 .•
3.'
3.
3 .•
....,.
"
6 .•
5.5
54
S.2
3.
3 .•
'.5
4.S
3 .•
3 .•
55
5.2
5 .•
5 .•
..
4 .•
MCl2060, MCl2061
+25 o C
"c
JO
.....• ..•
..•
'.3
37
-
+l25Gc
Min
S .•
5 .•
6-44
T,.
""
""
.....
4 .•
-
,.
,."
:IS
......"
....•..•
4.3
5.'
5.
4 .•
5 .•
TEST VOL TAGES/WAVEFORMS
55
5.2
5 .•
S .•
-
"
.. ! !""
3 .•
3 .•
-
4.'
4 .•
..•
...
PuI_ln Put-Out .2.oVclc -3.0Vdc
5 .•
5.2
52
5.'
3.
3 .•
,.,.
APPLIED TO PINS LISTED BELOW:
+l'SoC
"'
"'
"
"'
""
"""
""
"
""
11,16
G...
"
! ...! !
11.16
11,16
11.16
11,16
...
..9
""
'.' ""
MC12060, MC12560 (continued)
MC12061, MC12561
FIGURE 7 - AC TEST CIRCUIT - SINE WAVE OUTPUT
Vee
Crystal -
= +2.0 Vdc
O.I/OF
Reeves Hoffman Series Mode
Series Aesistance Minimum
at F u "dame" tal
•
MCI2060/12560,
O.I/OF
fz:500kHz
Re
=1
k n
MC12061/12561'
f= 10MHz
Re
c
,..-.l-_--L_ _ _ _....L-, 3
450
2
450
5 n
'RS - MCI2060/12560= 3 kn
MC12061112561 c 150 n
AS is inserted only for test
purposes. When used with
the above specified crystal.
6
it guarantees oscillation with
any crystal which has an equivalent series resistance ~4 kn
for MC12060/12560 and
155
n
.....---<1>----. Vee· -3.0 Vdc
for MC12061/12561.
Cry""1
All output cables to the scope are equal
D~
.n
lengths of 50
coaxial cable. All unused
cables must be terminated with 8 50 n
±'% resistor to ground.
450 n resistor and the scope termination
impedance constitute 8 10:1 attenuatar
probe.
Pin
Characteristic
MCI2560
MC12561
+25 o C
MC12060
MCI2061
TEST VOLTAGE
APPLIED TO PINS
LISTED BELOW
+250 C
Undar
Test
Min
Typ
Min
Typ
2
3
600
600
675
675
500
500
650
650
2
700
700
750
750
650
650
750
750
Unit
+2.0Vdc -3.0Vdc
Sine Wave Amplitude
MC12060/12560
MC12061/12561
3
1
8,9
p
mr
+ +
OPERATING CHARACTERISTICS
The MC12060/12560 and MC12061/12561 consist of three
basic section5: an oscillator with AGe and two translators
(Figure 1). Buffered complementary sine wave outputs are avail8~e from the oscillator section. The translators convert these sine
wave outputs to levels compatible with MECL andlor MTTL.
Series mode aystals should be used with the oscillator. If it is
necessary or desirable to adjust the crystal frequency, a reactive
elen'Ent can be inserted in series with the crystal - an inductor to
lower the frequency or a capacitor to raise it. When such an adjustment is necessary, it is recommended that the crystal be
specified slightly lower in frequency and a series trimmer capacitor
be added to bring the oscillator back on frequency. As the
oscillator frequency is changed from the natural resonance of the
aystal, more and more dependence is placed on the external reactance, and temperature drift of the trimming oomponents then
affects overall oscillator IJE!'rformance.
The MC12060/12560and MC12061/12561 are designed to operlta from • single supply - either +5.0 Vdc or -5.2 Vdc. Although
each translator has separate VCC and Vee supply pins, the circuit
is NOT designed to operate from both voltage levels at the same
time. The separate VEE pin from the MTTL translator helps
minimize transient disturbance. If neither translator is being used,
all unused pins (9 thru 16) should be connected to VEE (pin 81.
With the translators not IX)vvered, supply current drain is typically
rodUC8d from 35 mA to 16 mA for the MC12060/12560, and
from 42 mA to 23 mA for the MC12061/12561.
Frequency Stability
Output frequency of different oscifiator circuits (of a given
device type number) will very somewhat when used with a given
test .tup, however the variation should be within approximately
±O.001% from unit to unit.
Frequency variations with temperature (independent of the
crystal, which is held at 2sDC) are smoll - about -0.08 ppmfDC
for MC12061/12561 operating at 8.0 MHz, and about -0.16
ppmfDC lor MC12060/125600peratingat 1.0 MHz (see Figure 81.
Signal Chlract.istics
The sine wave outputs at either pin 2 or pin 3 will typically
range from 800 mVp-p (no load) to SOO mVp·p (120 ohm ac load).
Approximately 500 mVp-p can be provided across 50 ohms by
slightly increaSing the dc current in the output buffer by the
addition of an external resistor (680 ohms) from pin 2 or 3 to
ground, as shown in Figure 9. Frequency drift is typically less than
0.0003% when going from a high-impedance load 11 megohm,
15 pF) to the 50-ohm load of Figure 9. The dc voltage level at
pin 2 or 3 is nominally 3.5 Vdc with Vee = +5.0 Vdc.
Harmonic distortion content in the sine wave outputs is crystal
as well as circuit dependent. The largest harmonic (third) will
usually be at least 15 dB down from the fundamental. The har·
monic content is approximately load independent except that the
higher harmonic levels (greater than the fifth) are increased when
the MECl translator is being driven.
Typically. the MECl outputs (pins 12and 13) will drive upto
five gates, as defined in Figure 10, and the MTTl output (pin 10)
will drive up to ten gates, as defined in Figure 11.
Noi. Cher.~.iltics
Noise level evaluation of the sine wave outputs using the
circuit of Figure 12, with operation at 1.0 MHz for MC120601
12560 or 9.0 MHz for MC12061/12561, indicates the following
characteristics:
1. Noise floor (200 kHz from oscillator center frequency) is
approximately -122 dB when referenced to a 1.0 Hz bandwidth. Noise floor is not sensitive to load conditions andlor
translator operation.
2. Close-in noise (100 Hz from OScillator center frequency)
is approximately -88 dB when referenced to a 1.0 Hz
bandwidth.
MC12060, MC12560
MC12061, MC12561
(continued)
FIGURE 9 - DRIVING LOW-IMPEOANCE LOADS
FIGURE 8 - FREOUENCY SHIFT versus TEMPERATURE
+10~-----r----'r----'-----'-----'-----'-----'
+5.0 V
O.1I.lF
O.1IJF
E
!
....
~
~
-10
S
0.' IlF
To
~
~ -20~----4-----~---1-----+----~----+-~~
-30'--_ _"'-_........._ _........_ _'--_-'-_ _-'-_--'
-55
-25
75
100
125
25
50
·See te)(t under signal characteristics.
lA. AMBIENT TEMPERATURE (DC)
FIGURE 10 - MECL TRANSLATOR LOAD CAPABILITY
Vee
=
FIGURE 11 - MTTL TRANSLATOR LOAD CAPABILITY
+6.0 V
Vee "'" +5.0 V
+5.0 V
~ O.l/lF
16
11
........,------0 13
Sine
to
MECL
270
MECL
10
to
MTTL
All
Trans-
diodes
1.5 k
lator
8.2 k
MBol0l
or
EQuiv
9
FIGURE 12 - NOISE MEASUREMENT TEST CIRCUIT
+5.0 V
ANALYZER SETTING
O.1IJ,F
Video
Sweep
Bandwidth
Filter
Noise Floor
50 kHz/div
10 kHz
10 Hz
Close-In Noise
20 kHz/div
10 Hz
10 Hz
Measurement
To HP8552B/53B
Spectrum Analyzer
or Equiv
6-46
RESISTOR
R 1 (2 Placo.)
R2(2Placos)
R3 (2 Place.)
I
I
10kn
5 kn
MC12061112561
200 n
400n
2 kn
3:3:
......
00
NN
00
en en
CIRCUIT SCHEMATIC
.....0
3:3:
Sine to MECL
Voltage Regulator
Amplifier! AG C
Oscillator
MECL TO MTTL
Translator
Translator
Sina Wave Output
2 3
I
I 16
VCC
2.98
1k
014-
NN
U'IU'I
en en
MECLI
"'0
O,u;~~t I
15 +
......
00
11 ~VCC
1.2 k
>100
nO
,...:J
:J
c:
(!)
0.
0)
.r..
-...I
1.5 '>1.5
k
60 Crystal
05
9 VEE
INTEGRATED CIRCUITS
MIL-M-38510
PROGRAM
7-1
MOTOROLA
MIL-M-38S10
PROGRAM
- the ultimate
in quality assurance,
for integrated circuits
Motorola is the industry's pioneer manufacturer of high-reliability integrated circuits,
having been the first company to be qualified
as a MIL-M-38510 approved facility_by the
Defense Electronics Supply Center of the Department of Defense early iri 1971. Motorola's
extensive experience in high-reliability military
and manned spacecraft programs such as
Apollo, Minuteman and Safeguard, coupled with
an investment of millions of dollars for research
and development, has resulted in the ultimate
in quality assurance for integrated circuits: the
MOTOROLA MIL-M-38510 PROGRAM_
The MOTOROLA MIL-M-38510 PROGRAM is
designed to facilitate delivery and to minimize
specification preparation time_ Beginning with a
nucleus of popular IC types from our high-volume
lines, the program is continually adding more
devices to the list of MIL-M-38510 JAN-Qualified
products_
Because it is a "standard" hi-rei program,
the MOTOROLA MIL-M-38510 PROGRAM aids
in reducing the high costs and delivery delays
normally associated with "custom" hi-rei programs in the past.
It is a functional. operating program, based
on the Military's own long-range objective to
improve and demonstrate integrated circuit
reliability, and is designed to provide hi-rei customers with the finest in quality, reliability and
performance - fast!
This comprehensive program is structured to
provide an environment in which proven methods
of manufacturing, quality assurance, monitoring, screening and testing can thrive - to give
you the most reliable product on the market
today - and to give it to you fast!
The MOTOROLA MIL-M-38510 PROGRAM is
designed to support a broad base of test and
evaluation programs for micro-electronic d\!vices:
materials, workmanship, performance capabilities, identification and processing - applied to
all Motorola standard integrated circuit product,
with appropriate levels of reliability_ This product can be ordered in accordance with MIL-M38510 JAN-Qualified standards or to the lowercost, but similar hi-rei specifications designated
as MIL-M-38510 JAN-Processing. (See ordering
information.)
THE MOTOROLA MIL-M-38S10 PROGRAM
OFFERS YOU THESE BENEFITS:
L Standardization of environmental and
electrical test procedures
2_ Less specification writing required
3_ Less time required in negotiating
specifications
4_ Fast delivery
5_ Lower costs
7-2
I
J
MI L·M·38510Ioontin ",d)
MIL -M-3851 0 processed devices are offered by Motorola
in the MECL 10,000 family for both commercial and
military temperature range use. Hermetically·sealed ceramic
dual in line and flat packages are available. Industry·wide
"slash-specs" are being issued, and when available, will
permit Motorola to provide MIL·M-3851O qualified MECL
10,000 devices.
Most devices in the MECL II, and MECL III families
can also be processed to meet MIL·M-38510 requirements.
Motorola's MIL-M-38510 Program supplants our former
high reliability "Checkmate" program. You are invited to
inquire directly to Motorola for price and delivery quotations on your MIL·M-38510 MECL device requirements.
MECL MIL-M-38510 SELECTOR
MECL 10,000
MC10,OXX
MC10,lXX
MC10,2XX
MC10,3XX
MC10,4XX
MC10,5XX
MC10,6XX
MC10,7XX
Rated
Temperature Range
Package
Styles Available
-30 0 C/+850C
L
L
-55 0 C/+1250C
L,F
L,F
-300 C/+850C
L,F
MECLIII
MC16XX
7-3
THE MOTOROLA MIL·M·38510 PROGRAM
Under this program, Motorola integrated circuits may be procured to the specifications of MIL·M·
38510 and to four levels of processing which meet the screening requirements of MIL·STD·883.
MIL·M·38510 JAN·QUALIFIED PRODUCT
I
I
I
CassA
Class B
CassC
JAN·QUALIFIED DEVICE MARKINGS
JM38510/XXXXXAXX
JM38510/XXXXXBXX
JAN QUALIFIED
JM38510/XXXXXCXX
Examples of MIL·M·38510 JAN·Qualified markings:
1. G.S.I. (Government Source Inspection)
Linear
Digital
provided upon request.
2. Must be manufactured in a Government·
approved facility.
DEVICE:
MC1741BCBJ
ORDER:
MCI74IBCBJ
MC5400BCBJ
MC5400BCBJ
MARKING: JM385IO/lOIOIBCB
3. Product inventoried in distributor and OEM
warehouses.
JM385IO/OOI04BCB
HOW TO ORDER MIL·M·38510 JAN·QUALIFIED PRODUCT
BaSIC Numbering Parameters -
M38510
')'
(2)
/XXX
xx
,3)
B
C
B
15'
(6)
rll
(1) = J - This Indrcates a qualified deVice.
(2) = M385IO - The military designator.
(3) = /XXX - This three·dlglt number signifies the detail
specification In which the device type is found. The
detail specifications. also referred to as "slash specs,"
generally contain more than one device type and are
written for various generic groupings (i.e .. TTL NAND
Gates. TTL NAND Buffers, TTL Flip·Flops. Op Amps.
Voltage Regulators. etc.)
(4) = xx - ThiS two·digit number Identifies the device type
within the detail specification.
(5) = B - This is a single letter and specifies the device
class per MIL·M·385IO and will be class A, B or C.
(6) = Case Outline. (See listings in adjacent column).
(7) = Lead finish. (See lIStings in adlacent column).
The Motorola equivalent of the JAN M385IO part num·
ber is as shown In the following example and should be
referenced when ordering your specific device requirement.
MCXXXX
BCB
J
(1)
(2)
(3)
1. The MCXXltX designates the Motorola source deVice
type.
2. The first three letters after the part type have the same
meaning and order as in the JAN part numbering sys·
tern. This will simplify your cross· referencing.
3. J. which is the last letter in the part number. desig·
nates a JAN·qualified device.
Example: JM38510/XXXXXBCB
Case outline and lead finish designations
are common to both JAN Qualified
andJAN~de~
QUALIFIED # (6) PROCESSED # (3)
C - This is a single letter
and specifies the package or case
outline. A list of the currently·
defined package types (the letters
define the same case outline for
all detail speCifications) is shown
below:
CASE OUTLINE
DESIGNATOR
*A
B
C
*0
E
F
G
H
I
J
K
Z
-
CASE OUTLINE
1/.' x 1,4" flat
pack, l4'pin
I/S' x 1,4" flat pack, l4-pin
1,4" x %" dual-in· line, l4·pin
1/4 " X
If.'' flat pack, l4'pin
1/.' x 3,4" dual·in-line,
1/4 " X
8-lead can
1,4" x 1,4" flat pack, lO-lead
lO·lead can
%" x 11,4" dual·in·line, 24-pin
3fa" x I/Z" flat pack, 24-pin
1,4" X 1/2 " flat pack, 24-pin
- A and D outlines are Interchangeable
7·4
l6-pin
If.'' flat pack, l6'pin
MIL-M-38S10 JAN· PROCESSED PRODUCT
I
I
Class A
I
Class B
I
Class D
Class C
JAN·PROCESSED DEVICE MARKINGS
MC38510/XXXXAXXM MC38510/XXXXBXXM MC38510/XXXXCXXM MC38510/XXXXDXXM
MC38510/XXXXAXXS MC38510/XXXXBXXS MC38510/xxxxcxxs MC38510/XXXXDXXS
JAN PROCESSED
2. Government·approved facility
not required.
3. Product supplied with MIL·M·
38510 elect rica Is will be desig·
nated by an "M" suffix.
4. Product supplied with Motorola
standard data sheet electricals
Examples of MIL·M·38510
JAN·Processed markings:
linear
DEVICE:
MCI741BCBIM or 51
MCI741BCBIMor51
ORDER:
MARKINGS: MC3851011741BCB 1M or SI
will be designated by an "S"
suffix.
1. No G.S.I. provided.
5. Devices will be manufactured
using design and processing
guidelines contained in MIL·M·
38510.
Digital
DEVICE:
MC5400BCB 1M or 51
ORDER:
MC5400BCB 1M or 51
MARKINGS: MC38510/5400BCB 1M or 51
6. Inventories will be maintained
prior to burn·in and final elec·
trical tests.
HOW TO ORDER MIL·M·38510
JAN·PROCESSED PRODUCT
QUALIFIED #(7) PROCESSED
# (4)
B - This is a single letter
and specifies the finish to be
used on the package leads. There
are three types of lead finishes
which are acceptable for JAN
product. They are:
LEAD FINISH
SYMBOL
A
B
c
LEAD FINISH
- Kovar or Alloy 42. with hot
solder dip
- Kovar or Alloy 42. with bright
acid tin plate
- Kovar or Alloy 42. with
gold plate
Note: For other Motorola standard pack·
aging. not currently identified in MIL·M·
38510. contact your Motorola represen·
tative.
EXAMPLE: If you wish to enter an order for an MCXXXX
Class B device in a 14·pin. dual·in·line ceramic package
with the lead finish to be tin plate and electrically tested
to Motorola's standard data sheet electricals. the order
would be entered as follows:
MCXXXX
il)
(1)
(2)
B
C
(3)
B
,"
S
(5)
=
Motorola deVice type.
This is a single letter and specifies the device
ciass per MIL·M·38510 for Classes A. Band C.
Class D is an added Motorola JAN processing class
and is the same as the MIL·M·38510 Class B
except for the differences shown in the following
screening procedures table.
(3) = Case Outline. (See listings in adjacent column).
(4) = Lead finish. (See listings in adjacent column).
(5) = S - This is a single letter and specifies the elec·
trical specifications to which the device is to be
screened during electrical test and will be either an
S or M. "S" specifies the use of Motorola stan·
dard data sheet electricals. "M" specifies the use
of JAN slash·sheet electricals where they exist.
=B -
Electrical Test Symbols
Test Level
S
- Motorola standard
data sheet electricals
- JAN slash·sheet
electricals
M
7·5
SCREENING PROCEDURES
(To MIL·STD·883 Requirements)
This program establishes screening pro·
cedures for total lot screening of integrated
circuits to assist in achieving levels of quality
and reliability commensurate with the intended
application. In recognition of· the fact that the
level of screening has a direct impact on the
cost of the product as well as Its quality and
reliability, four standard levels of screening are
provided to coincide with four device classes or
levels of product assurance.
Flexibility is provided in the choice of con·
ditions and stress levels to provide screens.
tailored to a particular product or application.
Selection of a level better than that required for
the specific product and application will. of
course, result in unnecessary expense. A level
less than that required will result in an unwar·
ranted risk that reliability and other require·
ments will not be met. For general hi·rel
applications. the Class B screening level should
be considered.
CLASS A
SCREEN
CLASS B
RQMT
METHOD
ROMT
Internal Visual (Precap)
2010 Cond
A and 38510
100%
2010 Cond
Band 38510
100%
Stabilization Bake
100824 hrs
min. test
100%
1008. 24 hrs
min, test
condition C
)')0%
1010. Cond C
100%
condition C
Thermal Shock
lOll. Cond A
100%
Temperature Cycling
1010, Cond C
100%
2002 Cond F
One Shock In
V, plane only
or 5 shocks
100%
Mechanical Shock
at Cond B
y, plane
Seal (a) Fine
(b) Gross
(min) in
VI
plane then
V, plane
100%
1014
100%
JAN slash -sheet
ROMT
METHOD
RQMT
100%
2010 Cond
Band 38510
100%
10OS. 24 hrs
100%
min, test
condition C
100%
100%
1010, Cond C
100%
condition C
2001 Cond E
(min) YI
plane
100%
1010 Cond C
-
1014
100%
2001 Cond E
(min) y,
100%
plane
-
1014
2001 Cond E
(min) y,
100%
plane
100%
1014
100%
100%
100%
-
Motorola stand.
data sheet
electrical specs
unless otherwise
ir.dicated
1015
168 hrs@
125·C min
100%
-
1015
168 hrs@
125·C min
100%
JAN slash-sheet
electrical
specifications
unless otherwise
designated
100%
Motorola stand.
data sheet
electrical specs
unless otherwise
Indicated
100%
JAN slash·sheet
100%
electrical
specifications
unless otherwise
designated
Burn-in test
1015
240 hrs @
125°C min
100%
Interim Electricals
JAN slash-sheet
electrical specIfications unless
otherwise
deSignated
100%
Reverse Bias Burn-In
1015 Cond A
or C 72 hrs
at 150·C min
100%
Final Electrical tests
(a) Static tests
(1) 25' C (Subgroup
1 table 1 5005)
JAN slash-sheet
electrical
specifications
unless otherwise
designated
100%
(2) Max and min
rated op. temperature
(subgroups 2 and 3
table I. 5005)
(b) Dynamic tests and/or
switching tests 2S·C
(subgroup 4 and 9 .
table 1. 5005)
(C) functional test
25'C (subgroup 7
table I. 5005)
2010 Cond
Band 38510
10OS, 24 hrs
min, test
-
electrical
specification
unless otherwise
designated
Interim Electrical
Parameters
METHOD
In
2001 Cond E
Constant Acceleration
CLASS D
CLASS C
METHOD
JAN slash-sheet
electrical
specifications
unless otherwise
designated
100%
100%
100%
-
-
100%
100%
-
-
100%
100%
100%
100%
-
-
5005
Class B
2009
Radiographic
2012
Qualification or quality
conformance inspection
5005
Class A
100%
per
38510
External Visual
2009
100°0
.
.
- Group A per 5005, Generic data available for .roups B & C on deVices
produced to Class B. C. 0 for JAN processed (from JAN pro. ram)
7-6
per
38510
5005
Class C
100%
2009
.
-
per
38510
5005
Class B
100%
2009
::>
100%
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Create Date : 2014:07:19 19:10:08+02:00 Creator : Adobe Acrobat 11.0.7 Modify Date : 2014:07:21 21:07:08-07:00 Title : XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Metadata Date : 2014:07:21 21:07:08-07:00 Creator Tool : Adobe Acrobat 11.0.7 Format : application/pdf Document ID : uuid:c4b4106e-1da8-4ba1-aba8-f3c22567a1c2 Instance ID : uuid:7b5f8cf5-545e-9c41-ac10-29006f713a3f Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Page Layout : SinglePage Page Count : 624EXIF Metadata provided by EXIF.tools