1974_National_Digital_Integrated_Circuits 1974 National Digital Integrated Circuits
User Manual: 1974_National_Digital_Integrated_Circuits
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Edge Index
by Product Family
Here is the new Digital Data Handbook from National. It gives complete specifications for devices useful
in building nearly all types of electronic systems, from small Instruments to computer designs.
For information regarding newer devices introduced since the printing of thiS handbook, or for further
information on listed parts, please contact our local representative, distributor, or regional office.
Series 54/74 '
Series 54H/74H
Series 54L/74L
o
g
o
Series 74S
9
Series 930
GIl
Series 9000
[!II
Series 10,000
fJI
Interface Circuits
Future Products
AC Test Circuits and Waveforms
Manufactured under one or more of the following U S patents 3083262,3189758,3231797,3303356,3317671,3323071, 3381071, 3408542,3421025,3426423,3440498,3518750, 3519897. 3557431, 3560765
3566218,357163U,J575609,3579059,3593069,3597640,3607469,3617859,353\312,3633052,3638131,3648071,3651565,3693248
National does not assume any responSibility for use of any CirCUitry desCflbed, no CIrCUit patent licenses are Implied, and Natronal reserves the right, at any time I'/,thout nO:lce, to change said Clfcu,try
o
D
lID
Product Line
DIGITAL
I
I
RAMs
Shift
Regirten
I
I
TTL
MOS
Logic
Elemen
Series
54U74L
DTL
Series
930
Hybrid
Driven
I
HYBRIDS
~1.l.1
A..I.g
Switch..
Op.lld....
Amplifiers
LINEAR
I
DpellMnal
I
Inlerfece
I
Vollege
Amplif,ers
Circuits
RegulltOrs
I
I
Consumer
Circuits
I
I
Compelltonl
Buffers
Hybrids
A.dio
Driven
I
Sense
Amplifiers
Pe"phlral
Drivers
Line Drivenl
ReceiveR
T.V.
Communication
Circuits
Analog
Swotch..
Operati.nal
Amplifiers
TRANSISTORS
I
LED's
~
Lamps
DISplays
Transducen
I
Power
TranSistors
NPN Il PNP Small Signel
Sihcon Transistors
I
-~
Amplifiers Il
Switch..
M.n.lithic
D••ls
iii
Ordering Information
For available packages, consult the tables which precede each section. Then refer to the package drawings
(pages I through VI) in the back of the catalog.
The ordering Information for National devices covered in this catalog is as follows:
DM
541193
-, -r-
T
F
~PACKAGE
' - - - - - - - - - - DEVICE \\lUMBER
' - - - - - - - - - - - - - DEVICE FAMilY
DEVICE FAMilY
PACKAGE
AH - Analog Hybrid
D - Glass/Metal Dual·ln-Line Package
AM - Analog Monolithic
F - Flat Package (0.25" wide)
DM - Digital Monolithic
G - TO·8 (12 lead) Metal Can
LH - Linear Hybrid
H - TO·5 (multi·lead) Metal Can
LM - Linear Monolithic
J - Glass/Glass Dual·ln·Line Package
MM - MaS MonolithiC
N - Molded Dual·ln·Line Package
W - Flat Package (0.275" wide)
DEVICE NUMBER
4, 5, or 6 digit number.
Suffix Indicators:
A - I mproved Electrical SpeCification
C - Reduced Temperature Range
For most of the products listed in this catalog the temperature range can be obtained from the first one or
two numbers following the family deSignation. For example:
iv
DM54XX
All numbers beginning with 5 denote -55°C to +125°C temperature operation.
DM74XX
If the "74" is Indicated, the operating temperature is O°C to +70°C.
DM7XXX
All other numbers beginning with 7 (besides the "74" shown above) are NSC
proprietary products and a 7 here indicates -55°C to +125°C.
DM8XXX
All numbers beginning with 8 denote O°C to +70°C temperature operation.
Table of Contents
Edge Index by Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Function Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIES 54/74 -
.
.
.
.
iii
iv
xiii
SECTION 1
Reference to Package Dimensions, Waveforms, Test CirCUits, and Ordenng Information
DM5400/DM7400 (SN5400/SN7400) Quad 2·lnput NAND Gate . . . . . . . . . . . .
DM5401/DM7401 (SN5401/SN7401) Quad 2-lnput Gate (Open Collector) . . .. .
DM5402/DM7402 (SN5402/SN7402) Quad 2-lnp'ut NOR Gate . ... . ...
DM5403/DM7403 (SN5403/SN7403) Quad 2-lnput Gate (Open Collector)
DM5404/DM7404 (SN5404/SN7404) Hex Inverter ..
DM5405/DM7405 (SN5405/SN7405) Hex Inverter (Open Collector) .
DM5406IDM7406 (SN5406/SN7406) Hex Inverter Buffer/Dnver
DM5407/DM7407 (SN5407/SN7407) Hex Buffer/Driver
DM5408/DM7408 (SN5408/SN7408) Quad 2·lnput AND Gate
DM5409/DM7409 (SN5409/SN7409) Quad 2·lnput AND Gate (Open Collector)
DM5410/DM7410 (SN5410/SN7410) Triple 3·lnput NAND Gate
DM5411/DM7411 (SN5411/SN7411) 3·lnput Positive AND Gate ... .
DM5413/DM7413 (SN5413/SN7413) Dual Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5414/DM7414 (SN5414/SN7414) Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5416/DM7416 (SN5416/SN7416) Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . .
DM5417/DM7417 (SN5417/SN7417) Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5420/DM7420 (SN5420/SN7420) Dual 4-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5423/DM7423 (SN5423/SN7423) Expandable Dual 4-lnput NOR Gate with Strobe . . . . . . . . . .
DM5425/DM7425 (SN5425/SN7425) Dual 4-lnput NOR Gate with Strobe . . . . . . . . . . . . . . . . . . .
DM5426/DM7426 (SN5426/SN7426) Quad 2-1 nput TTL-MOS I nterface Gate . . . . . . . . . . . . . . . . .
DM5427/DM7427 (SN5427/SN7427) Triple 3-lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5430/DM7430 (SN5430/SN7430) 8·lnput Gate.
DM5432/DM7432 (SN5432/SN7432) Quad 2·lnput OR Gate
DM5437/DM7437 (SN5437/SN7437) Quad 2·1 nput NAND Buffer
DM5438/DM7438 (SN5438/SN7438) Quad 2·lnput NAND Buffer (Open Collector)
DM5440/DM7440 (SN5440/SN7440) Dual 4·lnput Buffer
DM5441A/DM7441A (SN5441A/SN7441A) BCD to Decimal Decoder/Nlxle™ Driver ...
DM5442/DM7442 (SN5442/SN7442) BCD to Decimal Decoder ...
DM5445/DM7445 (SN5445/SN7445) BCD to Decimal Decoder/Driver . .'
DM5446A/DM7446A (SN5446A/SN7446A) BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . .
DM5447A/DM7447A (SN5447A/SN7447A) BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . .
DM5448/DM7448 (SN5448/SN7448) BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . .
DM5450/DM7450 (SN5450/SN7450) Expandable Dual 2,Wlde 2·lnput AND·OR·INVERT Gate
DM5451/DM7451 (SN5451 /SN7451) Dual 2,Wlde 2·lnput AND·OR-INVERT Gate
DM5453/DM7453 (SN5453/SN7453) Expandable 4-Wlde 2·lnput AND·OR·INVERT Gate
DM5454/DM7454 (SN5454/SN7454) 4,Wlde 2·lnput AND·OR·INVERT Gate
DM5460/DM7460 (SN5460/SN7460) Dual 4·lnput Expander
DM5470/DM7470 (SN5470/SN7470) Edge·Trlggered JK Flip Flop
DM5472/DM7472 (SN5472/SN7472) JK Master/Slave Flip Flop
DM5473/DM7473 (SN5473/SN7473) Dual JK Master/Slave Flip Flop
DM5474/DM7474 (SN5474/SN7474) Dual 0 Flip Flop
DM5475/DM7475 (SN5475/SN7475) Quad Latch
DM5476/DM7476 (SN5476/SN7476) Dual JK Master/Slave Flip Flop.
DM5483/DM7483 (SN5483/SN7483) 4·Blt Binary Full Adder and Dual Single· Bit Binary Full Adder
DM5485/DM7485 (SN5485/SN7485) 4·Blt Magnitude Comparator
DM5486/DM7486 (SN5486/SN7486) Quad EXCLUSIVE·OR Gate ..
DM5488/DM7488 (SN5488/SN7488) 256·Blt Read Only Memory
DM5489/DM7489 (SN5489/SN7489) 64·Blt Random Access Read/Write Memory
.
.
.
.
.
.
.
.
.
.
.
.
1'1
1-1
1·3
1·5
1·3
1·7
1·3
1·9
1·11
1·13
1·13
1·1
1·15
1-17
1-19
1-9
1-11
1-1
1-21
1-21
1-24
1-21
1-26
1-28
1-30
1-30
1-32
1-34
1-36
1-38
9·1
9·1
9-1
1-40
1-40
1-40
1-40
1-40
1-43
1-45
1-47
1-49
1-51
1-47
1-53
9-2
1-56
1-58
1-62
v
SERIES 54/74 - SECTION 1 (CONTINUED)
DM5490/DM7490 (SN5490/SN7490) Decade Counter .
DM5491A/DM7491A (SN5491A/SN7491A) 8-Blt Shift Register
DM5492/DM7492 (SN5492/SN7492) D,v,de by 12 Counter
DM5493/DM7493 (SN5493/SN7493) 4·Blt Binary Counter.
DM5495/DM7495 (SN5495/SN7495) 4·Blt R,ght·Shlft/Left·Shlft Register
DM5496/DM7496 (SN5496/SN7496) 5·B,t Parallel·ln/Parallel·Out Shift Register
DM54107/DM74107 (SN54107/SN74107) Dual JK Master/Slave Flip Flop
DM54121/DM74121 (SN54121/SN74121) Monostable Multlvlbrator . ........
DM54123/DM74123 (SN54123/SN74123) TTLIMonostable Multlvlbrator. . .
. ......
DM54125/DM74125 (SN54125/SN74125) (See DM7093/DM8093).
DM54126/DM74126 (SN54126/SN74126) (See DM7094/DM8094) . . . . . . . . . . . . . . . . . . . . . . . . .
DM54132/DM74132 (SN54132/SN74132) Quad Schmitt Tngger . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54141/DM74141 (SN54141/SN74141) BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . .
DM54145/DM74145 (SN54145/SN74145) BCD to Decimal Decoder/Dnver .. . .
DM54150IDM74150 (SN54150/SN74150) 16·Llne to I-Line Multiplexer..
DM54151/DM74151 (SN54151 /SN74151) 8-Channel Digital Multiplexer ..... .
DM54153/DM74153 (SN54153/SN74153) Dual 4:1 Multiplexer.
DM54154/DM74154 (SN54154/SN74154) 4-Llne to 16-Llne Decoder/Demultiplexer ....
DM54155/DM74155 (SN54155/SN74155) Dual 2:4 Demultiplexer. . . . .. . ...
. ....... .
DM54156/DM74156 (SN54156/SN74156) Dual 2:4 Demultiplexer . . . . . . . . . . . . . . . .
DM54157/DM74157 (SN54157/SN74157) (See DM9322/DM8322) . . . . . . . . . .
DM54160/DM74160 (SN54160/SN74160) Decade Counter with Asynchronous Clear . . . . . . . . . . .
DM54161/DM74161 (SN54161/SN74161) Binary Couqter with Asynchronous Clear . . . . . . . . . . . . .
DM54162/DM74162 (SN54162/SN74162) Decade Counter with Asynchronous Clear . . . . . . . . . . . .
DM54163/DM74163 (SN54163/SN74163) Binary Counter with Asynchronous Clear . . . . . . . . . . . . .
DM54164IDM74164 (SN54164/SN74164) (See DM7570/DM8570) . . . . . . . . . . . . . . . . . . . . . . . . '.
DM54165/DM74165 (SN54165/SN74165) (See DM7590/DM8590) . . . . . . . . . . . . . . . . . . . . . . . .
DM54166/DM74166 (SN54166/SN74166) 8-Blt Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54170/DM74170 (SN54170/SN74170) 4 by 4 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54173/DM74173 (SN54173/SN74173) (See DM7551/DM8551) ...........................
DM54174/DM74174 (SN54174/SN74174) Hex D Flip Flop with Clear ..... " . . . . . . . . . . . . . . .
DM54175/DM74175 (SN54175/SN74175) Quad D Flip Flop with Clear. . . . ... ........
DM54176/DM74176 (SN54176/SN74176) (See DM7280IDM8280) . . . . . . . . . . . . . . . . . . . . . . . . .
DM54177/DM74177 (SN54177/SN74177) (See DM7281/DM8281). . . . . . . . . .
DM54180/DM74180 (SN54180/SN74180) 8-Blt Odd/Even Panty Generator/Checker. . . . . . . . . . . ..
DM54181/DM74181 (SN54181/SN74181) Anthmetic LogiC Unit. . . . . . . . . . . . . . .. ......
DM54182/DM74182 (SN54182/SN74182) Look-Ahead Carry Generator. . . . . . . . . . . . . . . . .
DM54184/DM74184 (SN54184/SN74184) BCD·to-Blnary Converter. . . . . . . . . . . . . . . . . . . .
DM54185AIDM74185A (SN54185A/SN74185A) Blnary-to-BCD Converter .. . . . . . .
DM54187/DM74187 (SN54187/SN74187) 1024·Bit Read Only Memory . . . . . . . . . . . . . . . . .
DM54190IDM74190 (SN54190/SN74190) Up-Down Decade Counter . . . . . . . . . . . . . . . . . . . . . . .
DM54191/DM74191 (SN54191/SN74191) Up-Down Binary Counter . . . . . . . . . . . . . . . . . . . . . .
DM54192IDM74192 (SN54192/SN74192) (See DM7560/DM8560). . .. . . . . . . . . . . . . . . . .
DM54193/DM74193 (SN54193/SN74193) (See DM7563/DM8563) . . . . . . . . . . . . . . . . . . . . . . . . .
DM54194/DM74194 (SN54194/SN74194) 4-Blt Bidirectional Universal Shift Register. . . . . . . . . . ..
DM54195/DM74195 (SN54195/SN74195) 4-Bit Parallel-Access Shift Register . . . . . . . . . . . . . . . . .
DM54196/DM74196 (SN54196/SN74196) 40 MHz Presettable Decade Counter/Latch. . . . . . . . . . ..
DM54197/DM74197 (SN54197/SN74197) 40 MHz Presettable Binary Counter/Latch. . . . . . . . . . ..
DM54198/DM74198 (SN54198/SN74198) 8-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54199/DM74199 (SN54199/SN74199) 8-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74200 (SN74200) TRI·STATE@ 256·B,t Random Access Memory . . . . . . . . . . . . . . . . . . . . . . .
DM7090/DM8090 Quad Inverter/Dual 2-lnput NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7091/DM8091 Quad 2·lnput NAND Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7092IDM8092 Dual 5-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7093/DM8093 TRI·STATE@ Quad Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7094/DM8094 TRI·STATE@ Quad Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7095/DM8095 TRI·STATE@ Hex Buffer. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .
DM7096/DM8096 TRI·STATE@ Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7097/DM8097 TRI·STATE@ Hex Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
1-64
1-68
1-64
1-64
1-70
1-73
1-47
1-75
9-2
1-130
1-130
1-19
9-3
1-38
1-77
1-80
1-82
1-84
1-87
1-87
6-12
9-4
9-4
9-4
9-4
1-191
1·204
1-89
9·5
1·176
1·91
1-91
1·160
1·160
1·94
1-96
1·102
1-104
1-104
1-106
1-109
1·111
1·185
1·188
1·113
9-5
1-116
1·116
1·120
1·122
1·163
1·124
1·126
1·128
1·130
1·130
1-133
1·133
1·133
SERIES 54/74 - SECTION 1 (CONTINUED)
DM7098/DM8098 TRI-STATE® Hex Inverter.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7121/DM8121 TRI-STATE® 8-Channel Digital Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7123/DM8123 TRI-STATE® Quad 2-lnput Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7130/DM8130 10·Blt Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7131/DM8131 6-Bit Unified Bus Comparator. . . . . . . .. .............. ......... ..
DM7136/DM8136 6-Bit Unified Bus Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7160/DM8160 6-Blt Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7200/DM8200 4·Blt Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7210/DM8210 8-Channel Digital SWitch. . . . . . . . . . . . . . . . . . . . .. ... ...... . ..... .
DM7211/DM8211 8-Channel Digital SWitch. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
DM7214/DM8214 TRI-STAIE® Dual 4:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7219/DM8219 TRI-STATE® 16-Llne to l-Llne Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7220/DM8220 Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7223/DM8223 l-Llne to 8-Llne Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7230/DM8230 TRI-STATE® Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
DM7280/DM8280 (S8280/N8280) Presettable Decade Counter ............ . ............ .
DM7281/DM8281 (S8281/N8281) Presettable Binary Counter. . . . . . . . . . . . . . . . . . . .. . .... .
DM7288/DM8288 (S8288/N8288) Presettable D,v,de by 12 Counter . . . . . . . . . . . . . . . . . . . . . . .
DM7511/DM8511 Dual Gated 0 Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7512/DM8512 Dual Gated Master/Slave JK/D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7520/D~8520 Modulo-N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7542/DM8542 TRI-STATE® Quad I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7544/DM8544 TRI-STATE® Quad Switch Debouncer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7551/DM8551 TRI-STATE® Quad 0 Flip Flop. .............. . . ......... . .. .
. . . . . . . . . . . . . . . . . . . . .. .
DM7552/DM8552 TRI-STATE® Decade Counter/Latch. . . . . ..
DM7553/DM8553 TRI-STATE® 8-Blt Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7554/DM8554 TRI-STATE® Binary Counter/Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7555/DM8555 TRI-STATE® Programmable Decade Counter. . . . . . . . . . . . . . . . . . . . .. . .. .
DM7556/DM8556 TRI-S:rATE® Programmable Binary Counter. . . . .. . . . . . . . . . . . . . . . . . . .
DM7560/DM8560 (SN54192/SN74192) Up/Down Decade Counter. . . . .. .... .,. . ....... .
. ...... .
DM7563/DM8563 (SN54193/SN74193) Up/Down Binary Counter. . . . .
DM7570/DM8570 (SN54164/SN74164) 8-Blt Serial-In Parallel-Out Shift Register .............. .
DM7573/DM8573 1024·Bit Field-Programmable Read Only Memory .. ............. ... ..
DM7574/DM8574 TRI-STATE® 1024-Blt Field-Programmable Read Only Memory . .
DM7575/DM8575 Programmable Logic Array (PLA). . . . . . . . . .. ........ ..... . ...... .
DM7576/DM8576 Programmable Logic Array (PLA). .. .
. . . . . . . .. .. . ... .
DM8582 256-Blt Random Access Memory (Open Collector) . . . . . . . .
. . . . . .. . .
DM7590/DM8590 (SN54165/SN74165) 8·Blt Parallel-In Serial-Out Shift Register .... .. ..
. . . . . . . . . . .. ...... ... .
DM7595/DM8595 4096·Blt Bipolar Read Only Memory. . . . .
DM7596/DM8596 TRI-STATE® 4096-Blt Bipolar Read Only Memory. . . . .. ......... . ... .
DM7597/DM8597 TRI·STATE® 1024-B,t Read Only Memory
.................... .
DM7598/DM8598 TRI-STATE® 256-Blt Read Only Memory. . . . . . .. .. . ......... . ... .
DM7599/DM8599 TRI-STATE® 64-Blt Random Access Read/Write Memory. . . .. '"
.. . ... .
DM75491 MOS to LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75492 MOS to LED Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75493 4-Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..... .
DM75494 6-Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7613/DM8613 Quad Gated 0 Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7695/DM8695 4096-Bit Bipolar Read Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7696/DM8696 TRI-STATE® 4096-Blt Bipolar Read Only Memory . . . . . . . . . . . . . . . . . . . . . .
DM7800/DM8800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7802/DM8802 High Speed MOS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7806/DM8806 High Speed MOS to TTL Level Converter. . .. ..... .... .. . ... .
DM7810/DM8810 Quad 2-lnput TTL-MOS Interface Gate. .. . . . . . .
.,. . .. .
DM7811/DM8811 Quad 2-lnput TTL-MOS Interface Gate . ... ... .
DM7812/DM8812 TTL-MOS Hex Inverter ..
. . . . . .. ........... . ......... .
DM7819/DM8819 Quad 2-lnput TTL·MOS AND Gate ........
. ............. .
DM7820/DM8820 Dual LI ne Receiver. . . . . . . .. . ... .
DM7820AlDM8820A Dual Line Receiver . '. . . . .. . .... .
1-133
1-135
1-137
1-139
1-141
1-141
1-139
1-143
1·145
1-145
1-148
1-150
1-153
1-155
1-157
1-160
1-160
1-160
1-165
1-165
1-169
1-173
9-6
1-176
1-179
1-183
1-179
9-6
9-7
1-185
1-188
1-191
1-193
1-196
1-199
1-199
1-163
1-204
1-206
1-208
1-211
1-214
1-219
1-221
1-221
9-7
9-7
1-165
1-206
1-208
1-223
1-226
1-226
1-229
1-229
1-229
1-231
1-233
1-235
vii
SERIES 54/74 - SECTION 1 (CONTINUED)
DM7822/DM8822 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7830/DM8830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7831/DM8831 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7832/DM8832 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7833/DM8833 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7834/DM8834 Quad TRI·STATE® Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7835/DM8835 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . .. . .........
DM7836/DM8836 Quad NOR Unified Bus Receiver. . . . . . .. ........... .. ... .......
DM7837/DM8837 Hex Unified Bus Receiver. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7838/DM8838 Quad Unified Bus Transceiver. . . . . . . .. . . . . . . . . . . . . . . . . . ........
DM7839/DM8839 Quad TRI·STATE® Transceiver..
. ...............................
DM7853/DM8853 Dual Retriggerable Resettable Monostable Multivibrator . . . . . . . . . . . . . . . . . . .
DM7856/DM8856 BCD to 7·Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8857 BCD to 7-Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7858/DM8858 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8859 TTL Compatible Hex LED Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8861 MOS to LED 5-Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . ..
DM8863 MOS to LED 8·Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8864 9-Digit LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8866 7·Diglt LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8869 TTL Compatible Hex LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7B75A/DM8875A TRI·STATE® 4-Blt Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7875B/DM8875B TRI-STATE® 4-Bit Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7880/DM8880 High Voltage 7·Segment Decoder/Driver (for Driving Sperry and
Panaplex IITM Displays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8884A High Voltage Cathode Decoder/Driver (for Driving Sperry and Panaplex IITM Displays) . ..
DM8885 MOS to High Voltage Cathode Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7887/DM8887 8·Dlglt High Voltage Anode Driver (Actlve·High Inputs) . . . . . . . . . . . . . . . . . . .
DM7889/DM8889 High Voltage Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7897/DM8897 8-Dlgit High Voltage Anode Driver (Active· Low Inputs) . . . . . . . . . . . . . . . . . . .
1·237
1·239
1·241
1·241
9·8
9·8
9·8
1·244
1-246
1·248
9·8
1·250
9·9
9·9
9·9
1·253
1·255
1·255
9·10
9·10
1·253
1·258
1·258
1·260
1·263
1·265
9·10
9-10
9-10
SERIES 54H/74H - SECTION 2
Reference to Package
DM54HOO/DM74HOO
DM54H01/DM74HOl
DM54H04/DM74H04
DM54H05/DM74H05
DM54H08/DM74H08
DM54H10/DM74H10
DM54Hl1/DM74H11
DM54H20/DM74H20
DM54H21/DM74H21
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
DM54H50/DM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
DM54H54/DM74H54
DM54H55/DM74H55
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73/DM74H73
viii
Dimensions, Waveforms, Test CircUits, and Ordering Information. . . . . . . . . ..
(SN54HOO/SN74HOO) Quad 2·lnput NAND Gate. . . . . . . . . . . . . . . . . . . . ..
(SN54H01/SN74H01) Quad 2·lnput NAND Gate (Open Collector) ..........
(SN54H04/SN74H04) Hex Inverter. . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
(SN54H05/SN74H05) Hex Inverter (Open Collector) . . . . . . . . . . . . . . . . . ..
(SN54H08/SN74H08) Quad 2·lnput AND Gate. . . . . . . . . . . . . . . . . . . . . ..
(SN54Hl0/SN74H10) Triple 3·lnput NAND Gate. . . . . . . . . . . . . . .. ....
(SN54H11/SN74H11) Triple 3·lnput AND Gate . . . . . . . . . . . . . . . . . . . . . .
(SN54H20/SN74H20) Dual 4·lnput NAND Gate. . . . . . . . . . . . . . . . . . . . ..
(SN54H21/SN74H2l) Dual 4·lnput AND Gate . . . . . . . . . . . . . . . . . . . . . . .
(SN54H22/SN74H22) Dual 4·lnput NAND Gate (Open Collector) . . . . . . . . ..
(SN54H30/SN74H30) 8-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . ..
(SN54H40/SN74H40) Dual 4·lnput NAND Buffer. . . . . . . . . . . . . . . . . . . ..
(SN54H50/SN74H50) Expandable Dual AND·OR·INVERT Gate .. . . . . . . . ..
(SN54H51/SN74H51) Dual AND-OR·INVERT Gate. . . . . . . . . . . . . . . . . . ..
(SN54H52/SN74H52) Expandable AND·OR Gate . . . . . . . . . . . . . . . . . . . . .
(SN54H53/SN74H53) Expandable AND·OR·INVERT Gate. . . . . . . . . . . . . ..
(SN54H54/SN74H54) AND-OR·INVERT Gate . . . . . . . . . . . . . . . . . . . . . . .
(SN54H55/SN74H55) Expandable AND·OR·INVERT Gate. . . . . . . . . . . . . ..
(SN54H60/SN74H60) Dual 4·lnput Expander. . . . . . . . . . . . . . . . . . . . . . ..
(SN54H61/SN74H61) Triple 3·lnput Expander . . . . . . . . . . . . . . . . . . . . . . ,
(SN54H62/SN74H62) 3-2·2·3·lnput Expander . . . . . . . . . . . . . . . . . . . . . . . .
(SN54H71/SN74H71) JK Flip Flop with AND·OR Inputs ...............
(SN54H72/SN74H72) JK Master/Slave Flip Flop. . . . . . . . . . . . . . . . . . . . ..
(SN54H73/SN74H73) Dual JK Flip Flop with Separate Clocks. .. .........
2·j
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
SERIES 54H/74H - SECTION 2 (CONTINUED)
DM54H74/DM74H74 (SN54H74/SN74H74) Dual 0 Edge-Triggered Flip Flop
DM54H76/DM74H76 (SN54H76/SN74H76) Dual JK Master/Slave Flip Flop
DM54H78/DM74H78 (SN54H78/SN74H78) Dual JK Flip Flop with Preset and Clear Inputs
2·6
2-6
2-6
SERIES 54L!74L - SECTION 3
Reference to Package Dimensions, Waveforms, Test CirCUits, and Ordering Information
DM54LOO/DM74LOO (SN54LOO/SN74LOO) Quad 2-lnput NAND Gate ............ .
DM54L01/DM74L01 (SN54L01/SN74L01) Quad 2-lnput NAND Gate (Open Collector) ..
DM54L02/DM74L02 (SN54L02/SN74L02) Quad 2-lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . .
DM54L03/DM74L03 (SN54L03/SN74L03) Quad 2-lnput NAND Gate (Open Collector)
DM54L04/DM74L04 (SN54L04/SN74L04) Hex Inverter. . . . . . . . . . .. ........ . ........ .
DM54L10/DM74L10 (SN54L 10/SN74L10) Triple 3-lnput NAND Gate ........ . ..
DM54L20/DM74L20 (SN54L20/SN74L20) Dual 4-lnput NAND Gate. . . . .. ..... . ....... .
DM54L30/DM74L30 (SN54L30/SN74L30) 8-lnput NAND Gate. . . . . . . . . . . . .. ....... . ..
DM54L42A/DM74L42A (SN54L42A/SN74L42A) BCD to Decimal Decoder .................. .
DM54L51/DM74L51 (SN54L51/SN74L51) Dual 2-Wlde AND-OR-INVERT Gate . . . . . . . . . . . . . .
DM54L54/DM74L54 (SN54L54/SN74L54) 4-Wide 3·2·2-3· Input AND-OR-INVERT Gate. . .. . .. .
DM54L55/DM74L55 (SN54L55!SN74L55) 2-Wide 4-lnput AND-OR-INVERT Gate ............ .
DM54L71/DM74L71 (SN54L71/SN74L71) RS Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L72/DM74L72 (SN54L72/SN74L72) JK Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L73/DM74L73 (SN54L73/SN74L73) Dual JK Flip Flop .......... . .............. .
DM54L74/DM74L74 (SN54L74/SN74L74) Dual 0 Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L78/DM74L78 (SN54L78/SN74L78) Dual JK Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L85/DM74L85 (SN54L85/SN74L85) 4-Blt Magnitude Comparator. . . . . . . . . . . . . .. . ... .
DM54L86/DM74L86 (SN54L86/SN74L86) Quad EXCLUSIVE-OR Gate ......... .
DM54L89A/DM74L89A (SN54L89A/DM74L89A) 64-Blt Random Access Memory
.......... .
DM54L90/DM74L90 (SN54L90/SN14L90) Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L91/DM74L91 (SN54L91/SN74L91) 8-Blt Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L93/DM74L93 (SN54L93/SN74L93) Ripple Bmary Counter. . . . . . . . . . .. . .......... .
DM54L95/DM74L95 (SN54L95/SN74L95) 4-Blt Parallel-In Parallel-Out Shift Register .......... .
DM54L98/DM74L98 (SN54L98/SN74L98) 4-Blt Data Selector/Storage Register ............ ..
DM54L123/DM74L123 (SN54L123/SN74L123) Dual TTL/Monostable Multlvlbrator .... . ..... .
DM54L154A/DM74L154A (SN54L154A/SN74L154A 4-Line to 16-Lme Decoder/Demultiplexer .... .
DM54L 164/DM74L 164 (See DM76L70/DM86L70 and DM78L70/DM88L70) ................. .
DM54L165A/DM74L165A (SN54L165A/SN74L165A) Parallel-In Serial-Out 8-Bit Shift Register .... .
DM54L187A/DM74L187A (SN54L187A/SN74L187A) 1024-Blt Read Only Memory ..
DM54L192/DM74L192 (SN54L192/SN74L192) Up-Down Decade Counter .. .
DM54L193/DM74L193 (SN54L193/SN74L193) Up-Down Bmary Counter ......... .
DM70L95 TRI-STATE® Hex Buffer ................. .
DM70L96 TRI-STATE® Hex Buffer
DM70L97 TRI-STATE® Hex Buffer
DM70L98 TRI-STATE® Hex Buffer
DM71 L22/DM81 L22 Quad 2-lnput Multiplexer. ..
DM71 L23/DM81 L23 Quad 2-lnput Multiplexer. . .. . ....
DM75L11/DM85L11 TTL Dual Gated 0 Flip Flop ...
DM75L 12/DM85L 12 Dual JK, 0 Flip Flop. . . . . . . . .. ..
DM75L51/DM85L51 TRI-STATE® Quad 0 Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L52/DM85L52 TRI-STATE® Decade Counter/Latch ..
DM75L54/DM85L54 TRI-STATE® Bmary Counter/Latch.. . .....
DM76L 13/DM86L 13 Quad Gated 0 Flip Flop. .. .... ..
DM76L24/DM86L24 TRI-STATE® 4-Blt Magnitude Comparator with A Almost B ............. .
DM76L70/DM86L70 8-Bit Serial-In Parallel-Out Shift Register ............................ .
DM76L75/DM86L75 Presettable Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76L76/DM86L76 Presettable Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76L93/DM86L93 Ripple Bmary Counter. .. . ....... .
DM76L97/DM86L97 TRI·STATE® 1024·Blt Read Only Memory ... . ..
DM76L99/DM86L99 TRI-STATE® 64-Blt Random Access Memory. .. .
DM78L12/DM88L12 TTL-MOS Hex Inverter/Interface Gate ....... .
DM78L70/DM88L70 (DM76L70 Flat Package Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-3
3-3
3-3
3-3
3-3
3-3
3-3
3·3
3-31
3-7
3-7
3-7
3-10
3-10
3-10
3·11
3-10
3·34
3·22
3·37
3·40
3-43
3-45
3·25
3·48
9·11
3·50
3-29
3·52
3·55
3·58
3-58
9·11
9-12
9-11
9-12
3-65
3-65
3-69
3·72
3-75
3-80
3-80
3-86
3-88
3-29
3-91
3-91
3-45
3-93
3-96
3-99
3-29
ix
SERIES 74S - SECTION 4
Reference to Package Dimensions, Waveforms, Test CirCUits, and Ordering Information. . . . . .. ...
DM74S00 (SN74S00) Schottky Quad 2·lnput NAND Gate. . . .
. . . . . . . . . . .. ..
DM74S03 (SN74S03) Schottky Quad 2·lnput NAND Gate (Open Collector).
. . . . . . . . . . . . . ..
DM74S04 (SN74S04) Schottky Hex Inverter.
. . . . . . . . . . . . . ..
DM74S05 (SN74S05) Schottky Hex Inverter (Open Collector) .
. . . . . . . . ..
DM74S10 (SN74S10) Schottky Triple 3·lnput NAND Gate. . .
. .. . . . . . . . . . . . . . . . .
DM74S11 (SN74S11) Schottky Triple 3·lnput AND Gate. . .
. . . . . . . . . . . ..
DM74S15 (SN74S15) Schottky Triple 3·lnput AND Gate (Open Collector) . . . . . . .
DM74S20 (SN74S20) Schottky Dual 4·lnput NAND Gate. .
. . . . . . . . . . . . . . . . . . . ..
DM74S22 (SN74S22) Schottky Dual 4·lnput NAND Gate (Open Collector) .
DM74S40 (SN74S40) Schottky Dual 4·lnput NAND Buffer .
. . . . . .. . . . .
DM74S64 (SN74S64) Schottky AND·OR·INVERT Gate
. . . . . . . . . . . . . . . . .. .....
DM74S65 (SN74S65) Schottky AND·OR·INVERT Gate (Open Collector). .
. . . . . . . . . ..
DM74S74 (SN74S74) Schottky Dual 0 Flip Flop. .
. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S86 (SN74S86) Schottky Quad EXCLUSIVE·OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S112 (SN74S112) Schottky Dual JK Flip Flop with Preset and Clear . . . . . . . . . . . . . . . . . . .
DM74S113 (SN74S113) Schottky Dual JK Flip Flop with Preset . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S114 (SN74S114) Schottky Dual JK Flip Flop with Common Clock and Clear . . . . . . . . . . . ,
DM74S135 (SN74S135) Schottky Quad EXCLUSIVE·OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . ..
DM74S140 (SN74S140) Schottky Dual 4·lnput NAND Line Driver . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S151/DM74S251 (SN74S151/SN74S251) Schottky 8·lnput Multiplexer with True
and Complement Outputs. . . . . . . .
. .................... .
DM74S153/DM74S253 (SN74S153/SN74S253) Schottky Dual 4·Llne to 1-Lme Data
Selector/Multiplexer. . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S157/DM74S257 (SN74S157/SN74S257) Schottky Quad 2·Lme to l·Llne Data
Selector/Multiplexer. . . . . . . . . . . . .. . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S158/DM74S258 (SN54S158/SN74S258) Schottky Quad 2·Lme to l·Lme Data
Selector/Multiplexer (Inverting) . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . ..
4·[
4·1
4·1
4·1
4·1
4·1
4-1
4-1
4·1
4·1
4·1
4·1
4·1
4·1
4·5
4·1
4·1
4-1
4·5
4·1
4-7
4·7
4·7
4·7
DM54S200/DM74S200 (SN54S200/SN74S200) Schottky 256-Bit ReadlWrite Memories
with TRI-STATE® Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
SERIES 930 -
SECTION 5
Reference to Package Dimensions, Waveforms, Test Circuits, and Ordering Information . . . . . . . . . . .. 5-i
DM930 Dual 4-lnput Gate with Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
DM932 Dual 4-lnput Buffer with Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 5-5
DM933 Dual 4·lnput Extender .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·5
5-3
DM935 Hex Inverter
5-3
DM936 Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
DM937 Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM944 Dual 4-lnput Power Gate with Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5·5
DM945 RS Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... .... . .. 5-7
5-3
DM946 Quad 2·lnput Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM948 RS Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5·3
DM949 Quad 2·lnput Gate. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM957 Quad 2·lnput Buffer. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .
5-5
DM958 Quad 2·lnput Power Gate. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
DM961 Dual 4-lnput Gate with Expander .. _ .
5-3
DM962 Triple 3-lnput Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5·3
DM963 Triple 3-lnput Gate . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
5-3
DM1800 Dual 5-lnput Gate
. . . . .. ..
. ....... .
DM1801 Dual 5-lnput Gate
. . . . . . . . . . . . . . . . .. . .. ... . ..
5·3
DM9093 Dual JK Flip Flop
. . . . . . . . . . . . . . . . . . . . . .. . ....
5-8
. . . . . . . . . . . . . . . . 5-8
DM9094 Dual JK Flip Flop
DM9097 Dual JK Flip Flop
5-8
5-8
DM9099 Dual JK Flip Flop
x
SERIES 9000 - SECTION 6
Reference to Package Dimensions, Waveforms, Test CirCUitS, and Ordering Information .... .. . .
DM9002C Quad 2·lnput NAND Gate. .. . . . . . . . . . . . . . . . . . . . . . . . .. ...
. . . . . ..
DM9003C Triple 3·lnput NAND Gate. . . . . . . . . . . . . . .. .....
. . .. .. ...
DM9004C Dual 4·lnput NAND Gate. . . . . . . . .. ...........
.. ... .. ....
DM9005C Dual AND·OR·INVERT Gate/Expander. . .
. . . ... , . . . . . . . . . . . . . . . . . . . . . .
DM9006C Dual 4·lnput Expander. . . . . . . . . . . ..
.. . .. ... .. ........ ..........
DM9008C 2·2-2·3·lnput AND·OR·INVERT Gate. . . . . . . . . . . . . . .. ..
.,. ...... ....
DM9009C Dual 4-lnput NAND Gate/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9012C Quad 2·lnput NAND Gate (Open Collector) . . . . .. ...
. . . . . . . . . . . . . . . . . . ..
DM9016C Hex Inverter. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .. ..... ......... ...
DM9300/DM8300 (SN54195/SN74195) 4·Blt Shltt Register
............................
DM9301/DM8301 BCD to Decimal Decoder ......
. . . . . . .. .......
. .. .. ..
DM9309/DM8309 Dual 4·lnput Multiplexer ........ . ., ........... . .. . ... .
DM9312/DM8312 8·lnput Multiplexer. . . . . . . . . . .. .
DM9322/DM8322 Quad 2·lnput Multiplexer .. . . . . . . . . . . . . . . . . . . .
DM9334/DM8334 8·Blt Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9601/DM8601 Retrlggerable Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9602/DM8602 Dual TTLlMonostable Multivlbrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-i
6·1
6·1
6·1
6·1
6·1
6·1
6·1
6·1
6·1
6·4
6·6
6·8
6·10
6·12
6·14
6·17
6·21
SERIES 10000 - SECTION 7
Reference
DM10l0l
DM10102
DM10l05
DM10106
DM10l07
DM10109
DM10ll0
DM10lll
DM10112
DM10115
DM10116
DM10117
DM10118
DM10119
DM10121
DM10124
to Package Dimensions, Waveforms, Test CirCUits, and Ordering Information. .........
(MC10l01) Quad OR/NOR Gate with Strobe.. "
.............
..........
(MC10102) Quad Gate
.. . "
........ . .. .
(MC10l05) Triple 2·3·2·0R/NOR Gate. . .. .... .. ... .
(MC10l06) Triple 4·3·3· Input NOR Gate .. ... .
(MC10l07) Triple EXCLUSIVE·OR/NOR Gate ..... .
(MC10109) Dual 4·5-lnput OR/NOR Gate
. . . . .. . ..
(MC10l10) Dual 3·lnput/3·0utput OR Gate .. ..
(MC10ll1) Dual 3·lnput/3·0utput NOR Gate ...... .
(MC10112) Dual 3·lnput 1 ORf2 NOR Gate . . . . . . . . . . . .
(MC10115) Quad Differential Amplifier.
(MC10116) Triple Differential Line Receiver
(MC10117C) Dual 2,Wlde OR·AND/OR·AND·INVERT Gate
(MC10118) Dual 2·Wlde OR·AND Gate... ......... . .....
. ......... .
(MC10119) 4·Wlde 4·3·3·3·lnput OR/AND Gate .. .
(MC10121) OR·AND/OR·AND·INVERT Gate . . . . . . . . .
(MC10124) Quad TTL to ECL Translator/Differential Line Driver ..
7·[
7·1
7·3
7·5
7·7
7·9
7·11
7·13
7·15
7·17
7·19
7·21
7·23
7·25
7·27
7·29
7·31
INTERFACE CIRCUITS - SECTION 8
Reference to Package Dimensions, Waveforms, Test CirCUitS, and Ordering Information
DH0006/DH0006C Current Driver
. .. . ..
DH0008/DH0008C High Voltage, High Current Driver
.......... .
DH0011/DH0011 C/DH0011CN (SH2001/SH2002/SH2002P) High Voltage High Current Drivers
. . . ... .
DH0016CN High Voltage High Current Driver. .. .. .... .. ..
DH0017CN (SH2200P) High Voltage High Current Driver. .
. .. . ....
. ...... .
DH0018CN High Voltage High Current Driver. .. .. ..
. . . . . . .. .. . ..
DH0028C/DH0028CN Hammer Driver
DH0034/DH0034C High Speed Dual Level Translator. .. .
DH0035/DH0035C PIN Diode SWitch Driver ..
DH3467C Quad PNP Core Driver. . .... . . . ...
DH3725C Quad NPN Core Driver .... . .. .
.............. .
LH2111/LH2211/LH2311 Dual Voltage Comparator .. .....
. . .. .. .. . ... .
LM106/LM206 Voltage Comparator/Buffer .......
. ....... .
LM306 Voltage Comparator/Buffer. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
LM 111/ LM211 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .... .
LM311 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8·[
8·1
.8-4
8·7
8·10
8-10
8-10
8-13
8-15
8-18
8-20
8-22
8-24
8-26
8-28
8-30
8-35
xi
INTERFACE CIRCUITS - SECTION 8 (CONTINUED)
LM139/LM239/LM339 Quad Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM 160/LM260/LM360 High Speed Differential Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM 161/LM261 /U1I361 High Speed Differential Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM163/LM363 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM350 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM363A Dual MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM710 Voltage Comparator
LM710C Voltage Comparator
LM711 Dual Comparator
LM711 C Dual Comparator
LM 1488 Quad Line Driver
LM1489/LM 1489A Quad Line Receiver
LM1514/LM1414 Dual Differential Voltage Comparator
LM5520/LM7520 Dual Core Memory Sense Amplifier
LM5521/LM7521 Dual Core Memory Sense Amplifier
LM5522/LM7522 Dual Core Memory Sense Amplifier
LM5523/LM7523 Dual Core Memory Sense Amplifier
LM5524/LM7524 Dual Core Memory Sense Amplifier
LM5525/LM7525 Dual Core Memory Sense Amplifier
LM5528/LM7528 Dual Core Memory Sense Amplifier
LM5529/LM7529 Dual Core Memory Sense Amplifier
LM5534/LM7534 Dual Core Memory Sense Amplifier
LM5535/LM7535 Dual Core Memory Sense Amplifier
LM5538/LM7538 Dual Core Memory Sense Amplifier
LM5539/LM7539 Dual Core Memory Sense Amplifier
LM55107A/LM75107A Dual Line Receiver. . .
LM55108A/LM75108A Dual Line Receiver. . .
LM75207 Dual MOS Sense Amplifier. . . . . . .
LM75208 Dual MOS Sense Amplifier. . . . . . .
LM75324 Memory Driver with Decode Inputs.
LM55325/LM75325 Memory Driver. . . . . . . .
.
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LM75450A Dual Peripheral Driver
LM75451 A Dual Peripheral Driver
LM75452 Dual Peripheral Driver
LM75453 Dual Peripheral Driver
LM75454 Dual NOR Peripheral Line Driver
LM75461 Dual Peripheral Drrver (High Voltage!
LM75462 Dual Peripheral Drrver (High Voltage!
LM75463 Dual Peripheral Driver (High Voltage!
LM75464 Dual Peripheral Drrver (High Voltage)
MH0007/MH0007C DC Coupled MOS Clock Drrver
MH0009/MH0009C DC Coupled Two Phase MOS Clock Driver
MH0012/MH0012C High Speed MOS Clock Driver
MH0013/MH0013C Two Phase MOS Clock Drrver
MH0025/MH0025C Two Phase MOS Clock Drrver
MH0026/MH0026C 5 MHz Two Phase MOS Clock Driver
MH7803/MH8803 Oscillator/Clock Drrver
MH7807/MH8807 Oscillator/Clock Driver. .
MH8804 Quad MOS Memory Drrver . . . . . . . . . . . . . .
MH8805 Dual MOS Memory Drrver . . . . . .. . ... .
MH8808 Dual High Speed MOS Clock Driver ...
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..
..
..
..
..
..
8-40
8-44
8-46
8·79
8-48
8·79
8·50
8·52
8·54
8·56
8·58
8·61
8·63
8·66
8·66
8·69
8·69
8·71
8·71
8·73
8·73
8·75
8·75
8·77
8·77
8·79
8·79
8·79
8·79
8·86
8·92
8-48
8·99
8·99
8·99
8·101
9-13
9-13
9·13
9-13
8·103
8·105
8·107
8·109
8·113
8·116
9·14
9·14
9·15
9·15
8·125
FUTURE PRODUCTS - SECTION 9
9·1
AC TEST CIRCUITS AND WAVEFORMS - SECTION 10
10·1
PhYSical DimenSions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Available Digital Applications Literature. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . Inside Rear Cover
xii
""CI
...
o
CL
c
Product Function Guide
...
n
-n
c
::l
n
GATES
DM5400/DM7400
DM5401/DM7401
DM5402/DM7402
DM5403/DM7403
DM5404/DM7404
DM5405/DM7405
DM5408/DM7408
DM5409/DM7409
DM5410/DM7410
DM5411/DM7411
DM5413/DM7413
DM5414/DM7414
DM5420/DM7420
DM 5423/DM 7423
DM5425/DM7425
DM5427/DM7427
DM5430/DM7430
DM5432/DM7432
DM5450/DM7450
DM5451/DM7451
DM5453/DM7453
DM5454/DM7454
DM 5460/DM 7460
DM5486/DM7486
DM54132/DM74132
DM7090/DM8090
DM7091/DM8091
DM7092/DM8092
DM54HOO/DM74HOO
DM54H01/DM74HOl
DM54H04IDM74H04
DM54H05/DM74H05
DM54H08/DM74H08
DM54Hl0/DM74Hl0
DM54Hll/DM74Hll
DM54H20/DM74H20
DM54H21/DM74H21
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
DM54H50IDM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
DM54H54/DM74H54
DM54H55/DM74H55
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM54LOO/DM74LOO
DM54L01/DM74LOl
DM54L02/DM74L02
DM54L03/DM74L03
DM54L04/DM74L04
DM54L10/DM74L10
DM54L20/DM74L20
DM54L30/DM74L30
DM54L42A/DM74L42A
DM54L51/DM74L51
DM54L54A/DM74L54A
DM54L55/DM74L55
DM54L86/DM74L86
DM74S00
DM74S03
DM74S04
DM74S05
DM74S10
DM74S11
DM74S15
DM74S20
DM74S22
DM74S64
DM74S65
DM74S86
DM74S135
DM930
DM933
DM935
DM936
DM937
DM946
DM949
DM961
DM962
DM963
DM1800
DM1801
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM10l0l
DM10l02
DM10l05
DM10l06
DM10l07
DM10l09
DM10ll0
...O·
DM10lll
DM10112
DM10115
DM10116
DM10117
DM10118
DM10119
DM10121
::l
Ci)
C
CL
CD
BUFFERS/DRIVERS
DM5406/DM7406
DM5407/DM7407
DM5416/DM7416
DM5417/DM7417
DM5437/DM7437
DM5438/DM7438
DM5440/DM7440
DM54125/DM74125
DM54126IDM74126
DM7093/DM8093
DM7094/DM8094
DM7095IDM8095
DM7096/DM8096
DM7097/DM8097
DM 7098/DM8098
DM7806/DM8806
DM54H40/DM74H40
DM70L95/DM80L95
DM70L96/DM80L96
DM70L97/DM80L97
DM70L98/DM80L98
DM74S40
DM74S140
DM932
DM944
DM957
DM958
FLIP FLOPS
LATCHES
STORAGE REGISTERS
DM5470/DM7470
DM5472/DM7472
DM5473/DM7473
DM5474/DM7474
DM5475/DM7475
DM5476/DM7476
DM54107/DM74107
DM54173/DM74173
DM54174/DM74174
DM54175/DM74175
DM7511/DM8511
xiii
CD
"C
:::J
~
FLIP FLOPS
LATCHES
STORAGE REGISTERS
(can't)
..
..
C
0
U
C
:::J
U.
DM7512/DM8512
DM7542/DM8542
DM7544/DM8544
DM7551/DM8551
DM7553/DM8553
DM7613/DM8613
U
:::J
"C
...
0
D..
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73IDM74H73
DM54H74/DM74H74
DM54H76IDM74H76
DM54H78/DM74H78
DM54L71/DM74L71
DM54L72/DM74L72
DM54L73/DM74L73
DM54L74IDM74L74
DM54L78/DM74L78
DM54L98/DM74L98
DM75L11/DM85L11
DM75LI2/DM85L12
DM75L51/DM85L51
DM76L13/DM86L13
DM74S74
DM74S112
DM74S113
DM74S114
DM945
DM948
DM9093
DM9094
DM9097
DM9099
DM9334/DM8334
DM7290/DM8290
DM7291/DM8291
DM7520/DM8520
DM7552/DM8552
DM7554/DM8554
DM7555/DM8555
DM7556/DM8556
DM7560/DM8560
DM7563/DM8563
DM54L90/DM74L90
DM54L93/DM74L93
DM54L192/DM74L 192
DM54L 193/DM74193
DM75L52/DM85L52
DM75L54/DM85L54
DM76L75/DM86L75
DM76L76/DM86L76
DM76L93/DM86L93
SHIFT REGISTERS
DM5491 AIDM7491 A
DM5495/DM7495
DM5496/DM7496
DM54164/DM74164
DM54165/DM74165
DM54166/DM74166
DM54194/DM74194
DM 54195/DM7 4195
DM54198/DM74198
DM54199/DM74199
DM7570/DM8570
DM7590/DM8590
DM54L91/DM74L91
DM54L95IDM74L95
DM54L 164/DM74L164
DM54L165A!DM74L165A
DM76L70/DM86L70
DM76L90/DM86L90
DM9300/DM8300
COUNTERS
DM5490/DM7490
DM5492/DM7492
DM5493/DM7493
DM54160/DM74160
DM54161/DM74161
DM54162/DM74162
DM54163/DM74163
DM54176/DM74176
DM54177/DM74177
DM54190/DM74190
DM54191/DM74191
DM54192/DM74192
DM54193/DM74193
DM54196/DM74196
DM54197/DM74197
DM7280/DM8280
DM7281/0M8281
DM7288/DM8288
xiv
MUL TIPLEXERS
DEMUL TIPLEXERS
DM54150/DM74150
DM54151/DM74151
DM54153/DM74153
DM54155/DM74155
DM54156/DM74156
DM54157/DM74157
DM7121/DM8121
DM7123/DM8123
DM7210/DM8210
DM7211/DM8211
DM7214/DM8214
DM7219/DM8219
DM 7223/DM8223
DM7230/0M8230
DM71 L22/0M81 L22
DM71 L23/DM81 L23
DM74S151/DM74S251
DM74S153/DM74S253
DM74S157/DM74S257
DM74S158/DM74S258
DM9309/DM8309
DM9312/DM8312
DM93221DM8322
DECODERS
DECODER/DRIVERS
DM5441A/DM7441A
DM5442/DM7442
DM5445/DM7445
DM5446A!DM7446A
DM5447 A/DM7447 A
DM5448/DM7448
DM54141/DM74141
DM54145/DM74145
DM54154/DM74154
DM8880
DM7856/DM8856
DM7858/DM8858
DM8857
DM7884/DM8884
DM7885/DM8885
DM54L42A/DM74L42A
DISPLAY DRIVERS
DM5441A/DM7441A
DM5446A/DM7446A
DM5447A!DM7447A
DM5448/DM7448
DM54141/DM74141
DM75491
DM75492
DM75493
DM75494
DM7856/DM8856
DM8857
DM7858/DM8858
DM8859
DM8861
DM8863
DM8864
DM8866
DM8869
DM8880
DM7884A/DM8884A
DM 7885/DM8885
DM7887/DM8887
DM7889/DM8889
DM7897/DM8897
MEMORY PRODUCTS
DM5488/DM7488
DM5489/DM7489
DM54170/DM74170
OM 54 184/DM7 4184
.
"'tJ
0
MEMORY PRODUCTS
(con't)
DM54185A/DM74185A
DM54187/DM74187
DM74200
DM7573/DM8573
DM7574/DM8574
DM7575/DM8575
DM7576/DM8576
DM8582
DM7595/DM8595
DM7596/DM8596
DM7597/DM8597
DM7598/DM8598
DM7599/DM8599
DM54L89A/DM74L89A
DM54L 187A/DM74L187A
DM76L97/DM86L97
DM76L99/DM86L99
DM54S200/DM74S200
COMPARATORS
DM5485/DM7485
DM7130/DM8130
DM7131/DM8131
DM7136/DM8136
DM7160/DM8160
DM7200/DM8200
DM54L85/DM74L85
DM76L24/DM86L24
ARITHMETIC CIRCUITS
DM5483/DM7483
DM54181/DM74181
DM54182/DM74182
MULTIPLIERS
DM7875A/DM8875A
DM78758/DM88758
c..
DM7819/DM8819
DM7833/DM8833
DM7834/DM8834
DM7835/DM8835
DM7836/DM8836
DM7837/DM8837
DM7838/DM8838
DM7839/DM8839
C
(')
'*
"T1
C
:::I
(')
'*
0
:::I
DM78L 12/DM88L12
PARITY GENERATORS
DM54180/DM74180
DM7220/DM8220
ONE SHOT
DM7853/DM8853
DM54121/DM74121
DM54123/DM74123
DM54L 123/DM74L 123
DM9601/DM8601
DM9602/DM8602
INTERFACE CIRCUITS
DM5426/DM7426
DM7800/DM8800
DM7802/DM8802
DM7806/DM8806
DM7810/DM8810
DM7811/DM8811
DM7812/DM8812
G')
c
DM10124
c..
CD
LM 139/LM239/LM339
LM 160/LM260/LM360
LM 1611LM261 /LM361
LM163/LM363
LM363A
LM55107A/LM75107A
LM55108A/LM75108A
LM75207
LM75208
LM75324
LM55325/LM75325
LM75461
LM75462
LM75463
LM75464
MH7803/MH8803
MH7807/MH8807
MH8804
MH8805
xv
~s
...
Series 54/74
REFERENCE
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below. * Refer to the alpha-numerical index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
OM5400
OM7400
OM5401
DM7401
DM5402
DM7402
DM5403
DM7403
DM5404
DM7404
DM5405
DM7405
OM5406
DM7406
DM5407
OM7407
DM5408
DM7408
DM5409
OM7409
DM5410
OM7410
DM5411
DM7411
DM5413
DM7413
DM5414
OM7414
DM5416
DM7416
OM5417
DM7417
DM5420
DM7420
DM5423
OM7423
DM5425
OM7425
OM5426
OM7426
OM 5427
OM7427
OM5430
DM7430
DM5432
OM7432
DM5437
DM7437
OM5438
DM7438
DM5440
DM7440
DM5441A
DM7441A
Pg.
1-1
1-1
1·3
1·3
1-5
1·5
1-3
1-3
1-7
1-7
1·3
1·3
1·9
1·9
1·11
1·11
1·13
1·13
1·13
1·13
1·1
1·1
1·15
1·15
1·17
1·17
1·19
1·19
1·9
1·9
1·11
1·11
1·1
1·1
1·21
1·21
1-21
1·21
1·24
1-24
1·21
1·21
1-26
1·26
1-28
1·28
1·30
1·30
1·30
1·30
1·32
1·32
1·34
1·34
Cavity DIP (O)(J)
Flat Pack (F)(W)
Type
Fig.
Pg.
Fig.
Pg.
Type
Fig.
Pg.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
18
18
V
V
V
W
W
W
18
V
W
18
V
W
19
19
18
18
V
V
V
V
W
W
W
W
18
18
18
V
V
V
W
W
W
18
V
W
18
18
18
18
18
V
V
V
V
V
W
W
W
W
W
19
V
W
II
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
18
5
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
11
11
11
11
11
11
12
12
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
Metal Can (G)(H)
Fig.
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
3
3
1
1
3
3
42
42
55
55
2
2
3
3
1
1
1
1
1
1
4
4
1
1
1
1
3
3
1
1
1
1
1
1
10-5
10-5
10·5
10·5
10·5
10·5
10-5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·19
10·19
10·29
10·29
10·5
10·5
10·5
10·5
10·5
10·5
10·9
10·9
10·9
10·9
10·5
10·5
10·9
10·9
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
10·5
1
1
2
2
1
1
2
2
1
1
2
2
4
4
4
4
1
1
2
2
1
1
1
1
1
1
1
1
4
4
4
4
1
1
1
1
1
1
2
2
1
1
1
1
1
1
6
6
2
2
6
6
10·1
10·1
10·1
10-1
10·1
10·1
10·1
10-1
10·1
10·1
10·1
10·1
10·1
10-1
10-1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10-1
10·1
10·1
10·1
10-1
10·1
10·1
10·1
10-1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10-1
10·1
o
*Order Numbers: use Device No. suffixed with package letter, i.e. DM7800W.
**Also available In 0 package. See page III.
l·j
DATA SHEETS
PACKAGES
Molded DIP (N)
l-ii
Devices
Pg.
DM5442
DM7442
DM5445
DM7445
DM5450
DM7450
DM5451
DM7451
DM5453
DM7453
DM5454
DM7454
DM5460
DM7460
DM5470
DM7470
DM5472
DM7472
DM5473
DM7473
DM5474
DM7474
DM5475
DM7475
DM5476
DM7476
DM5483
DM7483
DM5486
DM7486
DM5488
DM7488
DM5489
DM7489
DM5490
DM7490
DM5491A
DM7491A
DM5492
DM7492
DM5493
DM7493
DM5495
DM7495
DM5496
DM7496
DM54107
DM74107
DM54121
DM74121
DM54132
DM74132
DM54145
DM74145
DM54150
DM74150
DM54151
DM74151
DM54153
DM74153
DM54154
DM74154
DM54155
DM74155
DM54156
DM74156
DM54166
DM74166
DM54174
1-36
1-36
1-38
1-38
1-40
1-40
1-40
1-40
1-40
1-40
1-40
1-40
1-40
1-40
1-43
1-43
1·45
1-45
1-47
1-47
1-49
1-49
1-51
1-51
1·47
1-47
1-53
1-53
1-56
1-56
1-58
1-58
1-62
1-62
1-64
1-64
1-68
1-68
1-64
1-64
1-64
1-64
1-70
1-70
1-73
1-73
1-47
1-47
1-75
1-75
1-19
1-19
1-38
1-38
1-77
1-77
1-80
1-80
1-82
1-82
1-84
1-84
1-87
1-87
1-87
1-87
1-89
1-89
1-91
Fig.
Pg.
5
II
5
3
3
3
3
II
II
3
3
3
3
3
3
3
3
3
3
3
3
5
5
5
5
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
5
3
3
5
5
II
II
II
II
II
5
3
3
3
3
3
II
II
II
II
II
II
II
II
II
II
II
3
3
3
3
3
3
3
3
II
II
II
II
II
II
II
5
II
7
III
5
II
5
II
7
III
5
II
5
II
5
5
II
II
5
5
5
3
3
3
Cavity DIP (D)(J)
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Pg.
Type
Fig.
Pg.
Fig.
12
12
12
12
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
11
11
12
12
12
12
11
11
11
11
11
11
11
11
11
11
12
12
12
12
11
11
11
11
12
12
13
13
12
12
12
12
13
13
12
12
12
12
12
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
19
V
W
19
19
18
V
V
V
W
W
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
18
V
W
19
V
W
19
V
W
19
V
W
18
V
W
19
19
V
V
W
W
18
V
W
18
18
18
V
V
V
W
W
W
18
V
W
18
V
W
19
V
W
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Type
Pg.
Type
WAVEFORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
5
5
9
9
1
1
1
1
1
1
1
1
10-5
10-5
10-6
10-6
10-5
10-5
10-5
10-5
10-5
10-5
10-5
10-5
1
1
2
2
1
1
1
1
1
1
1
1
10-1
10-1
10-4
10-1
10-1
10-1
10-1
10-1
10·1
10-1
10-1
10-1
6
6
6
6
7
7
8
8
6
6
10-5
10-5
10-5
10-5
10-6
10-6
10-6
10-6
10-5
10-5
1
1
1
1
1
1
1
1
1
1
10-1
10-1
10-1
10·1
10-1
10-1
10-1
10-1
10-1
10-1
15
15
13
13
16
16
18
18
56
56
18
18
18
18
14
14
10-9
10-9
10-8
10-8
10-9
10-9
10-10
10-10
10-29
10-29
10-10
10-10
10-10
10-10
10-9
10-9
1
1
2
2
7
7
1
1
26
26
1
1
1
1
1
1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-8
10-8
10-1
10-1
10-1
10-1
10-1
10·1
6
6
10-5
10-5
10-1
10-1
10·1
10-1
10-1
10-1
10-1
10·1
18
V
W
18
18
19
19
17
V
V
V
V
V
W
W
W
W
F
55
55
9
9
10-29
10-29
10-6
10-6
1
1
1
1
1
1
2
2
19
19
19
19
17
17
19
19
19
19
19
19
19
V
V
V
V
V
V
V
V
V
V
V
V
V
W
W
W
W
F
F
W
9
9
3
3
19
19
9
9
9
9
10-6
10-6
10-5
10-5
10-10
10-10
10-6
10-6
10-6
10-6
1
1
1
1
1
1
1
1
2
2
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
57
10-29
1
10-1
W
W
W
W
W
W
DATA SHEETS
PACKAGES
Molded DIP (N)
Devices
DM74174
DM54175
DM74175
DM54180
DM74180
DM54181
DM74181
DM54182
DM74182
DM54184
DM74184
DM54185A
DM74185A
DM54187
DM74187
DM54190
DM74190
DM54191
DM74191
DM54194
DM74194
DM54196
DM74196
DM54197
DM74197
DM54198
DM74198
DM54199
DM74199
DM74200
DM7090
DM8090
DM7091
DM8091
DM7092
DM8092
DM7093
DM8093
DM7094
DM8094
DM7095
DM8095
DM7096
DM8096
DM7097
DM8097
DM7098
DM8098
DM7121
DM8121
DM7123
DM8123
DM7130
DM8130
DM7131
DM8131
DM7136
DM8136
DM7160
DM8160
[JM7200
DM8200
DM7210
DM8210
DM7211
DM8211
DM7214
DM8214
DM7219
DM8219
Pg1-91
1-91
1-91
1-94
1-94
1-96
1-96
1·102
1-102
1-104
1-104
1-104
1-104
1-106
1-106
1-109
1-109
1-111
1-111
1.113
1-113
1-116
1-116
1-116
1·116
1·120
1-120
1-122
1-122
1-163
1-124
1-124
1-126
1-126
1-128
1-128
1-130
1-130
1-130
1-130
1-133
1-133
1-133
1-133
1-133
1-133
1-133
1-133
1-135
1-135
1-137
1-137
1-139
1-139
1-141
1-141
1-141
1-141
1-139
1-139
1-143
1-143
1-145
1-145
1-145
1-145
1-148
1-148
1-150
1-150
Fig.
Cavity DIP (D)(J)
Flat Pack (F)(W)
Pg.
Fig.
5
5
5
II
3
II
7
III
5
II
5
II
5
II
5
II
5
II
5
II
12
12
12
11
11
13
13
12
12
12
12
12
12
12
12
12
12
12
12
12
12
11
11
11
11
13
13
13
13
9
12
12
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
10
10
12
12
12
II
II
5
3
3
3
3
II
II
II
II
II
7
III
7
5
5
5
3
3
3
3
3
III
II
II
II
II
II
II
II
II
3
II
5
II
5
II
5
II
5
II
5
II
5
II
7
5
5
III
II
II
5
II
5
3
3
II
II
II
3
II
5
II
5
II
7
III
9
12
11
11
11
11
12
12
12
12
10
10
Pg.
Type
Fig.
Pg.
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
19
19
19
19
18
V
V
V
V
V
J
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
III
D
IV
IV
J
J
J
J
J
J
J
J
J
J
J
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
III
III
D
D
IV
IV
IV
J
J
J
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
D
J
J
J
J
Type
W
W
W
W
W
19
19
19
19
V
V
V
V
W
19
19
19
19
19
19
V
V
V
V
V
V
W
W
17
17
17
17
V
V
V
V
F
F
F
F
19
19
18
18
18
18
18
V
V
V
V
V
V
V
W
18
V
W
19
19
19
19
19
19
19
19
19
19
19
16
17
17
19
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
19
V
W
19
19
18
V
V
V
W
W
W
18
V
W
19
V
W
19
19
17
17
V
V
V
V
W
W
W
W
W
J
D
D
Fig.
Pg.
Type
WAVEFORMS
Fig.
Pg-
57
07
57
9
9
20
20
3
3
13
13
13
13
13
13
10-29
10-29
10-29
10-6
10-6
10-10
10·10
10·5
10-5
10-8
10·8
10-8
10-8
10·8
10-8
58
58
51
51
51
51
1
1
1
1
1
1
10
10
10
10
21
21
21
21
21
21
21
21
12
12
12
12
11
11
TEST
CIRCUITS
Fig.
Pg.
1
1
1
10-1
10-1
10·1
12
12
1
1
2
2
2
2
7
7
10·4
10-4
10-1
10·1
10-1
10-1
10-1
10-1
10-1
10-1
10-30
10-30
10-27
10-27
10-27
10-27
1
1
1
1
1
1
10-1
10-1
10-1
10-1
10-1
10-1
10-5
10-5
10-5
10-5
10-5
10-5
10-7
10-7
10·7
10-7
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-8
10-8
10-8
10-8
10-8
10-8
1
1
6
6
1
1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
11
10-8
10-8
11
22 10-12
22 10-12
23 10-12
23 10-12
23 10-12
23 10-12
12 10-8
12 10-8
12-A 10-8
12-A 10-8
2
2
1
1
1
1
1
1
3
3
15
15
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-1
10-4
10-4
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
F
F
F
2
o
W
J
J
J
J
Metal Can (G)(H)
F
F
1-iii
DATA SHEETS
.
Q)
(/)
'·iv
Devices
Pg.
DM7220
DM8220
DM7223
DM8223
DM7230
DM8230
DM7280
DM8280
DM7281
DM8281
DM7288
DM8288
DM7511
DM8511
DM7512
DM8512
DM7520
DM8520
DM7542
DM8542
DM7551
DM8551
DM7552
DM8552
DM7553
DM8553
DM7554
DM8554
DM7560
DM8560
DM7563
DM8563
DM7570
DM8570
DM7573
DM8573
DM7574
DM8574
DM7575
DM8575
DM7576
DM8576
DM8582
DM7590
DM8590
DM7595
DM8595
DM7596
DM8596
DM7597
DM8597
DM7598
DM8598
DM7599
DM8599
DM75491
DM75492
DM7613
DM8613
DM7695
DM8695
DM7696
DM8696
DM7800
DM8800
DM7802
DM8802
DM7806
DM8806
DM7810
1·153
1·153
1·155
1·155
,.,57
1·157
1·160
1·160
1·160
,.,60
1·160
1·160
1·165
1·165
1·165
1·165
1·169
,.,69
,.,73
1·173
1·176
1·176
1·179
1·179
1·183
1·183
1·179
1·179
1·185
1·185
1·188
1·188
1·191
1·191
1·193
1·193
1·196
1·196
1·199
1·199
1·199
1·199
1·163
1·204
1·204
1·206
1·206
1·208
1·208
1·211
1·211
1·214
1·214
1·219
1·219
1·221
1·221
1·165
1·165
1·206
1·206
1·208
1·208
1·223
1·223
1·226
1·226
1·226
1·226
1·229
PACKAGES
Molded DIP (N)
Cavity DIP (D)(J)
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Pg.
Type
Fig.
18
V
W
19
V
W
18
18
18
18
18
18
19
19
19
19
19
V
V
V
V
V
V
V
V
V
V
V
W
W
W
W
W
W
W
W
W
W
W
19
19
19
V
V
V
W
W
W
19
19
19
19
19
19
19
V
V
V
V
V
V
V
W
W
W
W
W
W
W
19
V
W
18
V
W
19
V
W
Fig.
Po.
Fig.
Pg.
3
3
II
II
11
11
5
II
5
II
3
II
3
II
3
5
5
5
5
II
II
II
II
II
5
5
5
II
II
II
5
II
5
II
5
II
5
II
5
II
12
12
12
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
11
11
9
9
9
9
10
10
10
10
9
12
12
10
10
10
10
9
12
12
12
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
III
III
III
III
III
III
III
IV
IV
III
III
III
III
III
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
D
D
0
D
0
0
0
0
D
J
J
0
0
0
0
0
J
J
J
J
J
12
12
10
10
10
10
IV
IV
III
III
III
III
J
J
0
0
D
0
5
II
3
II
7
III
7
5
III
II
5
II
7
III
7
III
5
II
5
II
5
3
3
5
5
II
II
II
II
II
7
III
7
III
F
Type
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
19
19
V
V
II
3
II
3
II
12
12
11
11
11
IV
IV
IV
IV
IV
J
J
J
J
J
18
18
V
V
Type
W
W
21
21
5
Po.
W
W
V
V
H
H
WAVE·
FORMS
Fig.
Pg.
9
9
5
5
12
12
18
18
18
18
18
18
50
50
50
50
24
24
54
54
25
25
26
26
27
27
26
26
28
28
28
28
29
29
31
31
10·6
10·6
10·5
10·5
10·8
10·8
10·10
10·10
10·10
10·10
10·10
10·10
10·26
10·26
10·26
10·26
10·12
10·12
10·28
10·28
10·12
10·12
10·13
10·13
10·14
10·14
10·13
10·13
10·15
TEST
CIRCUITS
Fig.
Pg.
10·15
10·15
10·15
10·15
10·15
10·16
10·16
1
1
1
1
3
3
1
1
1
1
1
1
23
23
23
23
1
1
25
25
3
3
11
11
13
13
11
11
1
1
1
1
5
5
7
7
10·1
10·1
10·1
10·1
10·1
10·1
10·1
101
10·1
101
10·1
10·1
10·7
10·7
10·7
10·7
10·1
10·1
10·7
10·7
10·1
101
10·3
10·3
10·4
10-4
10·3
10·3
10·1
33
30
30
10·16
10·15
10·15
2
1
1
10·1
10·1
10·1
32
32
32
32
17
17
43
43
50
50
10·16
10·16
10·16
10·16
10·9
10·9
10·23
10·23
10·26
10·26
3
3
3
3
3
3
16A
16B
23
23
10·1
10·1
10·1
10·1
10·1
10·1
10·5
10·5
10·7
10·7
34
34
46
46
46
46
4
10·17
10·17
10·24
10·24
10·24
10·24
10·5
20
20
20
20
2
10·6
10·6
10·6
10·6
10·1
10·1
10·1
10·1
10·1
10·1
10·1
10·1
PACKAGES
DATA SHEETS
Molded DIP (N)
Devices
Pg.
DM8810
DM7811
DM8811
DM7812
DM8812
DM7819
DM8819
DM7820
DM8820
DM7820A
DM8820A
DM7822
DM8822
DM7830
DM8830
DM7831
DM8831
DM7832
DM8832
DM7836
DM8836
DM7837
DM8837
DM7838
DM8838
DM7853
DM8853
DM8859
DM8861
DM8863
DM8869
DM7875A
DM8875A
DM78758
DM8875B
DM7880
DM8880
DM8884A
DM8885
1-229
1·229
1·229
1·229
1·229
1-231
1·231
1-233
1·233
1·235
1·235
1-237
1·237
1·239
1·239
1·241
1-241
1-241
1-241
1-244
1·244
1-246
1·246
1·248
1-248
1-250
1·250
1-253
1·255
1·255
1-253
1·258
1-258
1·258
1-258
1·260
1-260
1·263
1·265
Cavity DIP (D)(J)
Flat Pack (F)(W)
Fig.
F,g.
Pg.
Fig.
Pg.
Type
3
3
3
3
3
3
3
II
II
II
II
II
II
II
3
II
3
II
11
11
11
11
11
11
11
11
11
11
11
11
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J**
J
J**
J
J**
3
II
3
II
5
II
5
II
II
5
II
5
II
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J**
J
J**
J
J**
J**
J
3
5
5
6A
6A
5
II
II
III
III
II
11
11
12
12
12
12
11
11
12
12
12
12
12
12
12
5
II
5
II
5
5
5
II
II
II
IV
J
J
J
J
J
J
J
J
12
9
12
9
12
12
12
IV
III
IV
III
IV
IV
IV
J
D
J
D
J
J
J
12
IV
J
IV
IV
Pg.
Type
18
18
18
18
18
18
18
18
18
18
V
V
W
W
W
W
W
W
W
W
W
W
18
18
19
19
19
19
V
V
V
V
V
V
W
W
W
W
W
W
19
19
19
V
V
V
W
W
W
19
19
V
V
W
W
V
V
V
V
V
V
V
V
Metal Can (G)(H)
Fig.
Pg.
Type
WAVEFORMS
TEST
CIRCUITS
F,g.
Pg.
Fig.
4
4
4
4
4
35
35
10-5
10·5
10-5
10-5
10-5
10-17
10·17
2
2
2
2
2
2
2
10-1
10-1
10·1
10·1
10·1
10·1
10·1
Pg.
47
47
44
43
43
44
12
12
12
12
10·25
10-25
10·23
10-23
10·23
10-23
10-8
10·8
10·8
10-8
21
21
17
l6A
16C
17
3
3
3
3
10·6
10-6
10·5
10-5
10·5
10-5
10-1
10·1
10-1
10-1
l-v
cc
s:s:
U'IU'I
Series 54/74
0l:I00l:I0
"'0
00
"
Cc
DM5400/DM7400(SN5400/SN7400) quadruple 2-input NAND gate
DM5410/DM7410(SN5410/SN7410) triple 3-input NAND gate
DM5420/DM7420(SN5420/SN7420) dual4-input NAND gate
S:s:
..........
:!!01:10
general description
00
Employing TTL (Transistor-Transistor-Loglc) to
achieve high speed at moderate power dissipation,
these gates provide the basic functions used in the
implementation of digital integrated circuit systems. Characteristics of the circuits include high
noise immunity, low output Impedance, good
capacitive drive capability, and minimal variation
in switching times with temperature. The gates
are compatible with and interchangeable with
Series 54/74 equivalent.
features
• Typical Noise Immunity
• Guaranteed Noise Immunity
•
•
•
Fan Out
Average Propagation Delay
Average Power DISsipation
c
s:
1V
400 mV
U'I
0l:Io
N
10
13 ns
10 mW per gate
,o
c
s:.....
0l:Io
N
o
schematic and connection diagrams
.....- - -....- - - ' "
,.----(shown for DM5410/DM7410)
DM5400/DM7400
Dual·1 n-Line Package
DM5400
DM5410/DM7410
Dual-In-Line Package
Dual-In-Line Package
DM5420
DM5410
Flat Package
DM5420/DM7420
Flat Package
Flat Package
1-1
o
operating conditions
absolute maximum ratings
Vee
Input Voltage
Storage Temperature Range
Fan-Out
Lead Temperature (Soldering, 10 sec)
...,....o
:!:
300"e
electrical characteristics
"It
Supply Voltage (Vee)
DM54XX
DM74XX
Temperature (TA)
DM54XX
DM74XX
7.0V
5.5V
_65°e to +150o e
10
MIN
MAX
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
"e
"e
UNITS
(Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
-1.5
UNITS
V
Q
Input Diode Clamp Voltage
Vcc: 5.0V, T A : 25°C, liN: -12 mA
...
Logical "1"
I nput Voltage
Vee: Min
Logical "0"
Input Voltage
Vee: Min
Logical "1"
Output Voltage
Vee: Min V IN : 0.8V, lOUT: -400 /lA
Logical "0"
Output Voltage
Vee: Min V IN : 2.0V, lOUT: 16 mA
Logical "1"
I nput Current
Vee: Max VIN :2.4V
40
Logical "1"
I nput Current
Vee: Max V IN : 5.5V
1
mA
Logical "0"
Input Current
Vee: Max V IN : 0.4V
-1.6
mA
Output Short
Circu it Current
(Note 2)
Vee: Max V IN : OV, Vo: OV
Supply CurrentLogical "0"
(Note 3)
Vee: Max V IN : 5.0V
3
5.1
mA
Supply CurrentLogical "1"
(Note 3)
Vee: Max V IN : OV
1
1.8
mA
Propagation Delay Time to
Logical "0", tpdO
Vcc: 5.0V,
TA : 25°C,
C: 50 pF
8
15
ns
Propagation Delay Time to
Logical" 1", tpd 1
Vee: 5.0V,
T A : 25°C,
C: 50 pF
13
25
ns
.......
o
"It
V
2.0
It)
:!:
Q
0.8
DM74XX
DM54XX
V
2.4
0.4
-55
-57
-20
-18
Note 1: Unless otherwise specifIed minImax limits apply across the _55°C to +12So C temperature range for the DM54XX and
across the aOc to 70°C range for the DM74XX. All typicals are given for Vee = S.OV and TA = 2SoC.
Nota 2: Not more than 1 output should be shorted at a time.
Note 3: Each gate.
'-2
V
V
/lA
mA
mA
Series 54/74
DM5401/DM7401 (SN5401/SN7401) quad 2-input gate (open collector)
DM5403/DM7403(SN5403/SN7403) quad 2-input gate (open collector)
DM5405/DM7405(SN5405/SN7405) hex inverter (open collector)
general description
These Series 54/74 functions are
applications where the normal TTL
output configuration is not wanted.
tions include implementation of
function
designed for
"totem-pole"
Such applicathe Wire-OR
Aside from the output, the circuitry is identical
to the standard quad two-input gate (DM5400/
DM7400) and hex inverter (DM5404/DM7404).
schematic and connection diagrams
r------1t-----------OO vcc
r-----~.-------ov~
4K
11K
INPUT
INPUTS
OUTPUT
OUTPUT
o-::-I--.....J
.
,
.....-----1...--00 •••
......- -....-0 .•.
DM5405/DM740S
DMS401/DM7401, DMS403/DM7403
DMS401/DM7401
Dual-I "-Line Package
DMS403/DM7403
DMS40S/DM740S
Dual-In-Line Package
Dual-In-Line Package
DM5401
DMS40S
Flat Package
Flat Package
1-3
absolute maximum ratings
7V
Vee
Input Voltage
5.5V
Operating Temperature Range DM5401, DM5403, DM5405 _55°C to +125°C
O°C to 70°C
DM7401, DM7403, DM7405
_65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
300°C
electrical characteristics
(Note 1)
PARAMETER
MIN
CONDITIONS
Input Diode Clamp Voltage
T A ~ 25°C
Vee ~50V,
liN = -12 mA
MAX
-1.5
UNITS
V
Logical "I" Input Voltage
DM5401,3,5
DM7401,3,5
Vee = 4 5V
Vee - 4 75V
Logical "0" Input Voltage
DM5401,3,5
DIVI7401,3,5
Vee=45V
Vee - 4.75V
Logical "I" Output Current
DM5401,3,5
DM7401,3,5
Vee=5.5V
Vee _ 5.25V Y'N = 0.8V, VOUT = 5.5V
Logical "0" Output Voltage
DM5401,3,5
DM7401,3,5
Vee = 4.5V
Vee 475V. Y'N = 2.0V
Logical "I" Input Current
DM5401,3,5
DM7401,3,5
Vee ~ 5.5V
Vee - 5.25V, Y,N = 2.4V
40
I1A
Logical "I" Input Current
DM5401,3,5
DM7401,3,5
Vee ~ 5.5V
Vee - 5.25V, Y'N ~ 5.5V
1
mA
Logical "0" Input Current
DM5401,3,5
DM7401,3,5
Vee ~ 5.5V
Vee - 5.25V, Y'N =04V
-1.6
mA
Supply Current-Logical "0" DM5401,3,5
(Each Gate)
DM7401,3,5
Vec = 5.5V
Vee - 5.25V, V ,N =50V
3.0
5.1
mA
Supply Current-Logical "I" DM5401,3,5
(Each Gate)
DM7401,3,5
Vee = 5.5V
Vee - 5.25V, Y'N
1.0
1.8
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee = 5.0V, T A = 25°C
C OUT = 15 pF, RL = 390n (Note 2)
3
Propagation Delay Time to a
Logical "1", t pd ,
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = 3.9 kn (Note 2)
18
2.0
lOUT
~
V
0.8
Y'N
~
O.OV, V OUT
~
5.5V
V
250
I1A
40
I1A
0.4
V
16 mA
~
OV
Note 1: Mm/Max units apply across the guaranteed temperature range unless otherwise specified.
All tYPlcals are given for Vee = 5.0V and TA = 25 0 e.
Note 2: COUT mcludes device output capacitance of approximately 8.5 pF and wiring capacitance.
1-4
TYP
7.5
28
15
ns
45
ns
c
s:
U'I
Series 54/74
~
o
N
"C
s:.....
DM5402/DM7402 (SN5402/SN7402) quad 2-input NOR gate
~
o
N
general description
The DM5402/DM7402 is a quad 2-input NOR gate
utilizing TTL (Transistor-Transistor Logic) to
achieve high speed at nominal power dissipation. It
is completely compatible with other Series 54174
devices.
10
• Fan-out
• Allowable Power Supply Variation
DM5402
DM7402
features
• Input Clamping Diodes
• Typical Noise Immunity
400 mV
• Guaranteed Noise Immunity
1V
4.5V to 5.5V
4.75V to 5.25V
• Average Propagation Delay
12 ns (with 50 pF)
• Average Power Dissipation
14 mW per gate
schematic and connection diagrams
DM5402/DM7402 (each gatel
,---,---",---",-0
16K
v"
4K
4K
lK
DM5402IDM7402
Dual·ln-Line Package
DM5402
Flat Package
GND
TOP VIEW
1-5
absolute maximum ratings
7V
5.5V
Vee
Input Voltage
Operating Temperature Range
DM7402
DM5402
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
oOe to 70°C
-55°C to +125°e
-65°C to +150o e
300°C
(Note 1)
PARAMETER
CONDITIONS
MIN TVP MAX UNITS
Vee =5.0V TA = 25°C
I'N = -12mA
Input Diode Clamp Voltage
-1.0
V
Logical "I" Input Voltage
DM5402
DM7402
Vee = 4.5V
Vee -4.75V
Logical "0" Input Voltage
DM5402
DM7402
Vee = 4.5V
Vee - 4.75V
Logical "I" Output Voltage
DM5402
DM7402
V ee =4.5V
_
_
Vee = 4.75V V'N - 0.8V, lOUT - -4OOIlA
Logical "0" Output Voltage
DM5402
DM7402
Vee =4.5V
Vee =4.75V V'N =2.0V,l oUT = 16mA
Logical "I" Input Current
DM5402
DM7402
Vee = 5.5V
_
Vee - 5.25V V'N - 2.4V
40
IlA
Logical "I" I nput Current
DM5402
DM7402
_
Vee =5.5V
Vee - 5.25V V'N - 5.5V
1
mA
Logical "0" Input Current
DM5402
DM7402
Vee = 5.5V
_
Vee =5.25V V'N - 0.4V
Output Short Circuit Current (Note 2)
DM5402
DM7402
Vee = 5.5V
_
Vee = 5.25V V OUT - 0
Supply Current-Logical "0"
(each gate)
DM5402
DM7402
Vee = 5.5V
_
Vee - 5.25V V'N - 5.0V
3.6
6.3
mA
Supply Current-Logical "I"
(each gate)
DM5402
DM7402
Vee =5.5V V'N = OV
Vee - 5.25V
2.0
3.6
mA
2.0
V
0.8
2.4
-20
-18
V
V
0.4
V
-1.0 -1.6
mA
-32 -55
mA
Propagation Delay to a
Logical "0", tpdO
Vee =5.0V TA = 25°C
C = 50 pF
N= 10
3
9
15
ns
Propagation Delay to a
Logical "1", tpd1
Vee =5.0V TA
C= 50pF
=25'C
N= 10
5
13
22
ns
Note 1: M,nlmax limits apply across the guaranteed temperature range of oOe to 70°C for the
DM7402 and -55°C to +125°e for the DM5402 unless otherwise spec,f,ed. All typ,cal. are given for
Vee =5.0V and T A =25°C.
Nota 2: Only one output at a time shoulil be short Circuited.
1-6
-1.5
Series 54/74
DM5404/DM7404(SN5404/SN7404) hex inverter
general description
The DM5404/DM7404 is a hex inverter utilizing
TTL to achieve high speed at nominal power dissipation. It is totally compatible with other Series
54/74 devices.
•
•
•
features
•
•
•
Input clamping diodes
Typical Noise Immunity
1V
•
400mV
Guaranteed Noise Immunity
10
Fan-out
Allowable Power Supply Variation
DM5404
4.5V to 5.5V
DM7404
4.75V to 5.25V
Average Propagation
12 ns (with 50 pF)
Delay
Average Power Dissipation 10 mW per gate
schematic and connection diagrams
o
DM5404/DM7404
4K
16K
130
DM5404
DM5404/DM7404
Dual-In-Line Package
Flat Package
GNO
14
13
IZ
11
10
GNO
TOP VIEW
TOP VIEW
1-7
absolute maximum ratings
7V
5.5V
Vee
Input Voltage
Operating Temperature Range
DM7404
DM5404
Storage Temperature Range
Lead Temperature (soldering. 10 sec)
electrical characteristics
O°C to 70°C
-55°C to +125°C
_65°C to +150°C
300°C
(Note 1)
PARAMETER
CONDITIONS
Input diode clamp voltage
Vee = 5.0V
liN = -12 mA
MIN
TYP
T A = 25°c
MAX UNITS
-1.5
V
Logical "I" Input Voltage
DM5404
DM7404
Vee=4.5V
V ee =4.75V
Logical "0" Input Voltage
DM5404
DM7404
Vee = 4.5V
Vee =4.75V
Logical "1" Output Voltage
DM5404
DM7404
Vee = 4.5V
Vee - 4.75V
Y,N = 0.8V. lOUT = -400 J.l.A
Logical "0" Output Voltage
DM5404
DM7404
Vee = 4.5V
Vee - 4.75V
Y'N = 2.0V. lOUT = 16 mA
Logical "1" Input Current
DM5404
DM7404
Vee = 5.5V
Vee - 5.25V
Y'N = 2.4V
40
J.l.A
Logical "1" Input Current
DM5404
DM7404
Vee = 5.5V
Vee = 5.25V
Y'N = 5.5V
1
mA
Logical "0" Input Current
DM5404
DM7404
Vee = 5.5V
Vee = 5.25V
Y'N = 0.4V
-1.6
mA
Output Short Circuit Current
(Note 2)
DM5404
DM7404
Vee =5.5V
Vee = 5.25V
V OUT = 0
Supply Current· Logical "0"
(each gate)
DM5404
DM7404
Vee = 5.5V
Vee - 5.25V
Supply Current· Logical "1"
(each gate)
DM5404
DM7404
Vee = 5.5V
Vee = 5.25V
Propagation Delay to a
Logical "1". tpd1
T A = 25°C
N = 10
Vee = 5.0V
C = 50 pF
5
16
22
ns
Propagation Delay to a
Logical "0" tpdO
TA = 25°C
N = 10
Vee = 5.0V
C = 50 pF
3
9
15
ns
2.0
0.8
2.4
-1.0
-20
-18
1·8
V
V
0.4
V
-30 -55
mA
Y,N = 5.0V
3.0
5.f
mA
Y'N =0
1.0
1.8
mA
Note 1. Min/Max limits apply across the guaranteed temperature range of OoC to 700 e for the
DM7404, and -5SoC to +12SoC for the DM5404, unless otherwise specified. All typlcals.are given for
Vee = 5.0V and T A = 25°C
Note 2. Only one output at a time should be short cirCUited.
V
c
s:
Series 54/74
U1
~
o
,
0')
C
s:
DM5406/DM7406.DM5416/DM7416
(SN5406/SN7406.SN5416/SN7416)
hex inverter buffers/drivers
general description
features
These TTL hex inverter buffers/drivers are fully
compatible for use with TTL and DTL logic circuits. Each inverter features high·voltage, opencollector outputs (DM5406/DM7406 30 volts
minimum breakdown and DM5416IDM7416 15
volts minimum breakdown). These inverters also
feature high sink current capability. (DM5406,
DM5416 30 mA and DM7406, DM7416 40 mAl.
•
•
•
•
~
o""'"
0')
I nput clamp diodes
High voltage open-collector outputs
DM5406/DM7406
DM5416/DM7416
High sink current capability
DM5406, DM5416
DM7406, DM7416
15 ns typical propagation delay time
30V
15V
30 mA
40 mA
u
schematic and connection diagrams
Dual-In-Line and Flat Package
.....-----o v"
.---~p-----
14
13
12
11
10
OUTPUT
.K
3K
2K
INPuro-_-
2K
L------4I~-....-
NoUi Component Yllues shown are nomlllll!
-.....--+_~
GNO
TOPVIEW
GNO
1-9
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltogo
DM5406/DM7406
DM5416/DM7416
Storage Temperature Range
Lead Temperature, (Soldering, 10 Sec)
(Note 1)
operating conditions
7.0V
5.5V
30V
15V
-65'C to +150'C
3OO'C
·
o
CD
Supply Voltoge
DM5406,DM5416
DM7406,DM7416
Temperature (TAl
DM5406,DM5416
DM7406,DM7416
Output Sink Current
DM5406,DM5416
DM1406,DM7416
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
'c
'c
30
40
rnA
rnA
~
I"'-
electrical characteristics
:E
(Note 2)
....Q
CD
PARAMETER
o
~
Logical "1" Input Voltage
:E
Log,cal "0" Input Voltage
In
Q
CONDITIONS
MIN
TVP
MAX
2
V
0.8
Output Breakdown Voltage
DM5406/DM7406
DM5416/DM7416
Logical "1" Output Current
DM5406/0M7406
OM5416/0M7416
UNITS
V
Vee = Ma., 10FF = 250 "A,
V'N = 0.8V
30
V
Vee = Ma., 10FF = 250 "A,
V'N = 0.8V
15
V
Vee = Ma., V OH = 3OV, V'N = O.BV
Vee = Ma., VOH = 15V, V'N = 0.8V
250
250
"A
"A
Log,.al "0" Output Voltage
Vee = Min, }IOUT = Max,
V'N = 2V, lOUT = 16 mA
0.7
0.4
V
V
Logical "1" Input Current
Vee = Ma., V'N = 2.4V
Vee' Ma., V'N = 5.5V
LogICal "0" Input Current
Vee = Ma., V'N = 0.4V
Supply Current - Log,eal "1"
Vee = Ma., V'N =OV
30
Log,eal "0"
Vee = Ma., V'N = 5V
27
Input Clamp Voltoge
Vee = 5.0V, I'N = -12 mA,
TA = 25'C
Propagat,on Oolay to a Log,eal "0", tpd.
Vee = 5.0V, T A = 25'C,
CL = 15 pF, RL = 1100
Vee = 5.0V, T A = 25'C,
CoL = 15 pF, R~ = 1100
Propagation Oolay to a Logical "1",
t.."
40
1
"A
mA
-16
mA
42
mA
38
mA
-1.5
V
15
23
ns
10
15
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the operation of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note;l: Unless otherwISe spee,f,ed m,n/max Iomits apply across the -55'C to +125'C temperature range for the DM5406,
DM5416 and across the O'C to 70'C range for the DM7406,DM7416. All typ,cal. are g,ven for VCC = 5.0V and TA = 25'C.
1·10
o
s:
Series 54/74
U1
-1=10
o
....
......
o
....s:
OM5407/0M7407,OM5417/0M7417
(SN5401lSN7407,SN54111SN7417) hex buffers/drivers
-1=10
o
....
o
s:
features
general description
U1
.......
-1=10
These TTL hex buffers/drivers are fully compatible
for use with TTL and DTL logic circuits. Each
buffer features high·voltage, open-collector outputs
(DM5407/DM7407 30V minimum breakdown and
DM5417/DM7417 15V minimum breakdown).
These buffers also feature high sink current capa·
bility (DM5407, DM5417 30 mA and DM7407,
DM7417 40 rnA).
•
•
•
•
•
Input clamp diodes
High voltage open-collector outputs
DM5407/DM7407
DM5417/DM7417
High sink current capability
DM5407,DM5417
DM7407,DM7417
......
o
s:
....
30V
15V
.......
-1=10
30mA
40mA
14 ns typical propagation delay time
145 mW typical power dissipation
u
schematic and connection diagrams
Dual·ln·Line and Flat Package
r---p--""""1-----00
v",
OUTPUT
INPUT
14
0-_-
11
12
11
10
z.
L - - - -.....~-_4--. . .--oGND
Note Component nI... shown •• nomlnll
TOP VIEW
GN.
1·11
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
(Note 1)
7.0V
5.5V
30V
15V
-65°e to +150oe
3000 e
DM5407/DM7407
DM5417/DM7417
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
operating conditions
MIN
MAX
UNITS
Supply Voltage (Vee)
DM5407,DM5417
DM7407. DM7417
4.5
4.75
5.5
5.25
V
V
Temperature (T A)
DM5407.DM5417
DM7407.DM7417
-55
0
+125
70
°e
°e
Output Sink Current
DM5407.DM5417
DM7407.DM7417
o"""
30
40
mA
mA
o::t
"""
:?!
c
~
electrical characteristics
o
(Note 2)
o::t
It)
PARAMETER
:?!
c
MIN
CONDITIONS
TYP
MAX
2
Logical "1" Input Voltage
V
Logical "0" Input Voltage
O.B
Output Breakdown Voltage
DM5407/DM7407
Max,
IOFF ""
250J.LA, V IN::: 2.0V
30
Vee::: Max,
'OFF =
250llA,
15
Vee
DM5417/DM7417
Logical "0" Output Voltage
<::
Vcc=MIn}
V'N=08V
Y,N =
20V
Vee = Max
Vcc=Max
V ,N "" 2.4V
Y,N = 5 5V
Logical "0" Input Current
Vee = Max
VIN = D.4V
Supply Current - Logical "'"
Vee = Max
Y,N = 5.0V
Logical "0"
Vee:: Max
Y,N :::QV
V
V
V
0.7
0.4
IOUT=Max
IOUT= l6mA
Logical "1" Input Current
UNITS
V
V
40
1
iJ A
rnA
-1.6
rnA
29
21
41
30
rnA
rnA
-1.5
V
Propagation Delay to a Logical "0",
tpdO
Vee = 5.0V, TA = 25°C, CL = 15 pF, RL = lIOn
20
30
ns
Propagation Delay to a Logical "1",
tpd1
Vee = 5.0V, TA = 2SoC, CL = 15 pF, RL = 1100
6
10
ns
Input Clamp Voltage
Vee = 5.0V I'N = -12 rnA, TA = 25°C
Note 1: "Absolute MaXimum Ratings" are those values beyond which the operation of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the deVices should be operated at these limits. The table
of "Electrical Charactenstlcs" provides conditions for actual deVice operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DM5407,
DM5417 and across the oOe to 700 e range for the DM7407, DM7417. All typieals are g,ven for Vee = 5.0V and TA = 25°C.
1·12
c
illS
s:UI
Series 54/74
~
o
co
......
c
s:
......
DM540S/DM740S(SN540S/SN740S) quad 2-input
AND gate
DM5409/DM7409(SN5409/SN7409) quad 2-input
AND gate (open collector)
~
o
co
c
s:
UI
general description
~
o
The DM5408/DM7408 and DM5409/DM7409 provide the non-inverting AND function in the popular quad 2-input pin configuration_
CD
......
C
s:
......
~--------------------------------------------------------------~
~
0
CD
schematic and connection diagrams
II
DM5409, DM7409
DM5408, DM7408
.K
"
Dual-In-Line and Flat Package
TOP VIEW
,.,3
absolute maximum ratings
(Note 1)
Supply Voltage
7V
5.5V
Input Voltage
5.5V
Output Voltage
-65°C to +150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)
operating conditions
MIN
MAX
UNITS
Supply Voltage(Vcc)
DM5408.DM5409
DM7408.DM7409
4.5
4.75
5.5
5.25
V
V
Temperature (TA)
DM5408.DM5409
DM7408.DM7409
-55
0
+125
70
9C
°c
co
o
~
....
:!
Q
......
CO
o
electrical characteristics
(Note 2)
PARAMETER
~
CONDITIONS
Logical "1" Input Voltage
It)
:!
Logical "0" Input Voltage
Q
MIN
Vee = Min
TYP
O.B
DM540B
DM740B
Vee = Min, Y'N = 2V, lOUT = -BOO /J.A
Logical "I" Output
Current
DM5409
DM7409
Vee = Min, V OUT = 5.5V, Y,N = 2.0V
Logical "I" Input Current
UNITS
V
Vee = Min
Logical "1" Output
Voltage
Logical "0" Output Voltage
MAX
2
2.4
V
V
250
0.4
Vee = Min, Y'N = O.BV, lOUT = 16 mA
/J.A
V
Vee = Max, Y,N = 2.4V
40
/J.A
Vee = Max, Y'N = 5.5V
1
mA
Logical "0" Input Current
Vee = Max, Y,N = 0.4V
-1.6
mA
Output Short Circuit
Current (Note 3)
Vee = Max
DM540B
DM740B
-20
-lB
-55
-55
mA
Supply Current - Logical "1"
(each device)
Logical "0"
Vee = Max, Y,N = 5V
11
21
mA
Vee = Max, V IN = OV
20
33
mA
Input Clamp Voltage
Vee = 5.0V, TA = 25°C, liN = -12 mA
-1.0
-1.5
V
Propagation Delay to a Logical "0"
from DM540B/DM740B Any Input
to Output, tpdO
Vee = 5.0V
TA = 25°C
14
19
ns
Propagation Delay to a Logical "0"
from DM5409/DM7409 Any Input
to Output, tpdO
Vee = 5.0V
TA = 25°C
15
24
ns
Propagation Delay to a Logical "I"
from DM540B/DM740B Any Input
to Output, tpd1
Vee = 5.0V
TA = 25°C
13
27
ns
Propagation Delay to a Logical "I"
From DM5409/DM7409 Any Input
to Output, tpd1
Vee = 5.0V
TA = 25°C
17
32
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to + 12SoC temperature range for the
DM5408,DM5409 and across the O°C to 70°C range for the DM7408,DM7409. All typicals are given for VCC = 5 OV and T A
= 25°C.
Note 3: Only one output at a time should be shorted.
1-14
Series 54/74
DM54111DM7411(SN54111SN7411)
3-input positive AN D gate
general description
The DM5411/DM7411 provides the AND function
for the triple 3-input gate. Its pin-out is the same
as the DM5410/DM7410.
schematic and connection diagrams
D
~--~------.--.--ov~
OUTPUT
Dual-In-Line Package
TOPVIEW
1-15
absolute maximum ratings
operating conditions
MIN
MAX
UNITS
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldermg, 10 sec)
Supply Voltage (Vee)
DM5411
DM7411
4.5
4.75
5.5
5.25
V
V
Temperature (T A)
DM5411
DM7411
-55
0
+125
70
°e
°e
MAX
UNITS
7.0V
5.5V
5.5V
_65°e to +150o e
3000 e
electrical characteristics
(Note 1)
PARAMETER
= Mon
Vee
LogIcal "0" Input Voltage
Vee Mon
Vee
= Mon, V ,N = 2V,
Vee
= Mon, V ,N = O.BV,
Vee
Vee
= Max, V ,N = 2.4V
= Max, V ,N = 5.5V
Vee
= Max,
LogIcal "0" Input Current
V
O.B
Logical "0" Output Voltage
Output Short CorCUlt Current
(Note 3)
TYP
2
LogIcal "I" Output Voltage
LogIcal "I" Input Current
MIN
CONDITIONS
LogIcal "I" Input Voltage
V,N
lOUT
= -BOOIIA
lOUT
2.4
V
= 16mA
0.4
= O.4V
DM5411
DM7411
V
-20
-IB
V
40
IIA
1
mA
-1.6
mA
-55
-55
mA
Vee
= Max
Supply Current - LogIcal "I"
(each devIce)
Logical "0"
Vee
= Max, V ,N = 5V
15
mA
Vee
= Max,
22
mA
= 5.0V, TA = 25°C,
V ,N
= OV
Input Clamp Voltage
Vee
Propagation Delay to a LogIcal "0"
from Any I nput to Output, tpdO
Vee = 5.0V
TA = 25°C
CL
PropagatIon Delay to a LogIcal "I"
from Any I nput to Output, tpd1
Vee = 5.0V
TA = 25°C
CL
= -12 mA
-1.0
-1.5
V
= 50 pF
14
19
ns
= 50 pF
13
27
ns
l'N
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operatlng Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
NDte 2: Unless otherwise specified minimax Iomlts apply across the _55°e to +125°C temperature range for the DM5411 and
across the oOe to 700 e range for the DM7411. All typicals are given for Vce = 5.0V and TA = 25°C.
NDte 3: Only one output at a time should be shorted.
1-16
c
~
Series 54/74
U'I
...,....
W
C
~
............
OM5413/0M7413(SN5413/SN7413)
dual Schmitt-trigger
W
general description
features
The DM5413/DM7413 is a dual Schmitt-trigger
with input gating. It differs from a conventional
dual 4-input gate in that instead of having a single
threshold voltage, the DM5413/DM7413 has different thresholds for positive- and negative-going
inputs. When the output is in the logical "0"
state an input must be lowered to 0.9 volts
typically before the output changes state. Conversely in order to return to the logical "0" state
the input must rise to 1.7V typically. This hysteresis is extremely beneficial in applications where
slow rise and fall time signals are prevalent.
•
•
•
•
•
•
Series 54/74 compatible
800 mV hysteresis typo - higher noise immunity
Operation from very slow ramp voltages
Temperature compensated design
Typical propagation delay - 17 ns
Typical power dissipation 42 mW per function
D
applications
• Pulse shaper
• Th reshold detector
logic and connection diagram
Dual-In-Line and Flat Package
v'"
I,.
,
"
13
,
'I
I"
I" I.
~
r1
•
5
'I
•
:!o
TOP VIEW
'-17
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM5413
DM7413
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 11
7V
5.5V
5.5V
DM5413
DM7413
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
(Note 2)
PARAMETER
CONDITIONS
MIN
TVP
UNITS
V ee ·5V
1.5
1.7
2.0
V
VT_Negative·Going Threshold Voltage
Vee = 5V
0.6
0.9
1.1
V
V T> - VT_ Hysteresis
Vee = 6V
0.4
0.8
V
IT+ Input Current at
Positlve·Going Threshold
Vee = 5V. V,N = VT+
-0.65
rnA
Vee = 5V. V,N = VT_
-0.86
rnA
IT_ Input Current at
Negative-Going Threshold
LogIcal "1" Output Voltage
DM5413 Vee = 4.5V
DM7413 Vee = 4.75V
lOUT = -800IiA. V ,N = 0.6V
LogIcal "0" Output Voltage
DM5413 Vee = 4.5V
OM7413 Vee = 4.75V
lOUT = 16 rnA. V ,N = 2.0V
Logical "1" Input Current
DM5413 Vee = 5.5V
DM7413 Vee = 5.25V
V,N = 2.4V
40
p.A
DM5413 Vee = 5.5V
DM7413 Vee - 5.25V
V ,N = 5.5V
1
rnA
Logical "0" Input Current
DM5413 Vee = 5.5V
OM7413 Vee - 5.25V
V ,N = 04V
-1.6
rnA
Output Short Circuit Current
INote3)
DM5413 Vee=55V
DM7413 Vee' 5.25V
Supply Current - LogIcal "1"
I Each DevIce)
DM5413 Vee = 5.5V
DM7413 Vee - 5.25V
V ,N = OV
Logical "0"
DM5413 Vee = 5.5V
DM7413 V ee '525V
V,N ' 4 5V
0.4
-1
Propagation Delay to a Logical "0" from
Vee '50V
TA = 25°C
50 pF Load
5
Vee' 5.0V
T A ' 25°C
50pFLoad
5
tpdO
Any Input to Output,
tpd1
rnA
14
23
rnA
20
32
rnA
-1.5
V
15
22
ns
18
27
ns
Note 1: "Absolute MaXImum Ratings" are those values beyond whIch the safety of the devIce cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these
for actual device operation.
limits.
The table of "Electrical Characteristics" provides conditions
Note 2: Unless otherwISe speCIfIed minimax limIts apply across the -55°C to +125°C temperature
range for the DM5413 and across the DoC to 70°C range for the DM7413. All typlcals are gIven for
VCC = 5.0V and T A = 2SoC.
Note 3: Only one output at a time should be shorted.
V
-55
-18
Vee' 5.0V. l'N = -12 rnA. T A ' 25°C
Propagation Delay to a Logical "1" from
V
2.4
Input Clamp Voltage
any Input to Output,
1-18
MAX
VT + Positive-Going Threshold Voltage
Series 54/74
DM5414/DM7414(SN5414/SN7414) hex schmitt trigger
DM54132/DM74132(SN541321SN74132) quad schmitt trigger
general description
features
Both the DM5414/DM7414 and the DM54132/
DM74132 complement the DM5413/DM7413 in
providing multiple Schmitt Triggers in a package.
The DM5414/DM7414 provides six inverters each
with input hysteresis. The DM54132/DM74132 is
a quad two input inverting gate which copies the
pin-out of the DM5400/DM7400.
• Series 54/74 compatible
• 800 mV hysteresis typ.-higher noise immunity
• Operation from very slow ramp voltages
D
schematic and connection diagrams
..
,
NOM
_v'"
r - -.....--4......---4......
13'
NOM
INPun { :
OUTPUTY
,.
Dual·ln·Line and Flat Package
Dual·1 n·Line and Flat Package
DM54132/DM74132
DM5414/DM7414
18
IV
I.
TOP VIEW
"
IV
GNO
1·19
N
('I)
~
absolute maximum ratings
operating conditions
Supply Voltage, V CC
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
~5·C to +150"C
Lead Temperature (Soldering, 10 seconds)
300"c
Supply Voltage (VCC)
DM5414, DM54132
DM7414, DM74132
:E
Q
.......
N
('I)
:;:
U)
:E
Q
.
~
electrical characteristics
~
PARAMETER
:E
Q
Temperature (TA)
DM5414, DM54132
DM7414, DM74132
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
·C
·C
-55
0
(Note 2)
CONDITIONS
MIN
TYP
MAX
UNITS
.......
Positive Going Threshold Voltage
(VT +)
Vee = 5.0V
1.5
1.7
2.0
V
~
Negat,ve Going Threshold
Voltage (VT -)
Vee = 5.0V
0.6
0.9
1.1
V
U)
:E
Hysteresis (V T + - V T -)
Vee = 5.0V
0.4
0.8
Input Clamp Voltage (V,)
Vee = MIn,I, =-12 mA
-1.5
V
H'gh Level Output Voltage (V OH )
Vee = Min, V, = V T - min,
10H = Max
Low Level Output Voltage (Voel
Vee = Min, V, = V T + max,
10L = Max
Input Current at POSitive GOing
Threshold (IT+)
Vee = 5.0V, V, = V T +
-0.43
mA
Input Current at Negat,ve GOing
Threshold (IT - )
Vee = 5.0V, V, = V T -
-0.56
mA
Input Current at Maximum Input
Voltage (I,)
Vee = Max, V, = 5.5V
High Level Input Current (I'H)
Vee = Max, V, = 2.4V
Low Level Input Current (I,eI
Vee = Max, V'L = 0.4V
...
~
Q
2.4
V
3.4
0.2
V
0.4
1.0
-0.8
V
mA
40
jJ.A
-1.2
mA
High Level Output Current (lOH)
-800
jJ.A
Low Level Output Current {lo eI
16
mA
-55
mA
Short Circuit Output Current (los)
(Note 3)
Vee = Max
-18
Supply Current {led
DM5414/DM7414
Output H ,gh Current
Output Low Current
Average Per Gate
Vee = Max
Vee = Max
50% Duty Cycle
22
39
5.1
36
60
mA
mA
mA
Supply Current (led
DM54132/DM74132
Output H'gh Current
Output Low Current
Average Per Gate
Vee = Max
Vee = Max
50% Duty Cycle
15
26
5.1
24
40
mA
mA
mA
Propagation Delay Time, Low to
High Level Output (tPLH)
CL = 15 pF, RL = 4000
15
22
ns
Propagation Delay Time, High to
Low Level Output (tPHL)
CL = 15 pF, RL = 4000
15
22
ns
Not. 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of nElectrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55"C to +125"C temperature range for DM5414,
DM54132and across the O·C to +70"C range forth. DM7414, DM74132. All typicals are given for VCC· 5.0V and TA = 25·C.
Note 3: Not more than one output should be shorted at a time.
1·20
Series 54/74
DM5423/DM7423(SN5423/SN7423) expandable dual 4-input
NOR gate with strobe
DM5425/DM7425(SN5425/SN7425) dual 4-input
NOR gate with strobe
DM5427/DM7427(SN54271SN7427) triple 3-input NOR gate
general description
The three NOR gates described here were designed
to provide additional versatility to the line of
Series 54/74 functions.
DM7460, dual 4·input expander gate, resulting
in a larger number of OR'ed terms.
The DM5425/DM7425 is similar to the DM5423/
DM7423 except that it has no expandable inputs.
The DM5423/DM7423 has the added features of
a Strobe input which is AND'ed with the four
normal inputs, and a pair of expandable inputs
which can accept logic levels from the DM5460/
The DM5427/DM7427 has neither expandable
inputs nor Strobe.
D
logic and connection diagrams
Dual-In-Line and Flat Package
Dual-in-Line and Flat Package
STROBE
STROBE
0,
14
X,
EXPANDER
INPUTS
A,
8,
G,
C,
0,
V,
G,
B,
A,
Y,
c,
0,
Y,
GND
12
13
A,
GNU
c,
B,
STROBE
Y" G iA + 8 + C + D) + x
x" OUTPUT OF OM5460/0M1460
V =G iA+8+C+0l
TOPVIEW
TOP VIEW
DM5423/DM7423
DM5425/DM7425
Dual-In-Line and Flat Package
A,
B,
A,
c,
B,
A,
Y,
B,
c,
Y,
GND
Y"'A+ 8+C
TOP VIEW
DM5427/DM7427
1·21
absolute maximum ratings
(Note 1)
operating conditions
MIN
Supply Voltage
7.0V
I nput Voltage
5.5V
5.5V
Output Voltage
Storage Temperature Range
-65°e to +150o e
300°C
Lead Temperature ISolderlng, 10 secondsl
electrical characteristics
5.5
5.25
Temperature ITAI
DM5423, DM5425, DM5427 -55
DM7423, DM7425, DM7427
0
+125
+70
PARAMETER
CONDITIONS
Vee =MIn
Logical "0" Input Voltage
Vee
Logical "1" Output Voltage
Vee = Min, 10 = -BOOIlA, VIN = 0 BV
Logical "0" Output Voltage
Vee = Min, 10 = 16 rnA, VIN = 2 OV
Data Inputs
Strobe Inputs
Expander Current II x I
DM5423
OM 7423
Base-Emitter Voltage of Output
TranSIStor 101 IVBE(Q)I
DM5423
DM7423
Hlgh·Level Output Voltage IVoHI
DM5423
DM7423
Low Level Output Voltage IVoei
DM5423
DM7423
Logical "0" Input Current
Vee
UNITS
V
V
(Note 2)
Logical "1" Input Voltage
Logical "'" Input Current
MAX
Supply Voltage IVeel
DM5423, DM5425, DM5427 4.5
DM7423, DM7425, DM7427 4.75
MIN
TYP
UNITS
V
= Mm
lIB
MAX
20
08
V
04
V
2.4
V
Max
VIN =24V
VIN =55V
VIN =24V
VIN = 5 5V
V, = O.4V,l oL = 16 rnA IS.. Figure 11
Vee = 4.5V, T A = -55°C
Vee=475V,TA=0°C
40
10
160
1.0
IlA
rnA
IlA
rnA
2.9
31
rnA
mA
1.0
1.0
V
V
10L = 16 rnA, A, = 0 ISee Figure 21
Vee = 4.5V, T A = -55°C, I, = 0.41 rnA
Vee = 4.75V, TA = O°C, I, = 0.62 rnA
10H = -4001lA ISee Figure 31
Vee = 4.5V, TA = -55°C, I, = 150llA
12 =-150IlA
Vee = 4 75V, TA = O°C,I, = 270llA,
12 =-270IlA
2.4
3.3
V
24
33
V
10L = 16 rnA ISee Figure 21
Vee = 4 5V, T A = -55°C, I, = 0 3 rnA,
A, = 13Bn
Vee =475V,TA =O°C,I, =043 rnA,
A, = 130n
Vee = Max, VIN = O.4V
Data Inputs
Strobe Inputs
0.22
0.4
V
0.22
04
V
-1.6
-6.4
rnA
rnA
-55
-55
rnA
rnA
Output Short CircUit Current (Note 3)
DM54XX
DM74XX
Supply Current - Logical "1"
Vee = Max
Vee:= Max
-20
-18
Vee
= Max
16
rnA
Vee
= Max
= Max
19
26
rnA
rnA
Supply Current - Logical "0"
DM5423, DM7423, DM5425, DM7425
DM5427, DM7427
Vee
Input Clarnp Voltage
Vee = 5.0V, TA = 25°C, lIN = -12 rnA
Propagation Delay to a Logical "0" From
Vee = 5 OV, T A = 25°C, CL = 50 pF
Expander PinS Open, RL = 4000
Vee = 5.0V, T A = 25°C, CL = 50 pF
Expander PinS Open, RL = 4000
Data or Strobe to Output Itpdol
Propagation Delay to a Logical "'" From
Data or Strobe to Output Itpd ,I
DM5423, DM7423, DM5425, DM7425
DM5427, DM7427
-15
V
15
15
ns
ns
22
11
ns
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" prOVides conditions for actual device operation.
Note 2: Unless otherWISe specified minimax limits apply aeross the -55°C to +125°e temperature range for the DM5423,
DM5425, DM5427 and across the oOe to +70°C range for the DM7423, DM7425, DM7427. All typicals are given for
Vce = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
1·22
cc
~~
(J1(J1
typical applications
0l:I00l:I0
NN
(J1W
................
CC
~~
~~
NN
(J1W
C
~
(J1
0l:Io
N
.....
........
C
~
~
N
.....
FIGURE 2.
FIGURE 1.
o
FIGURE 3.
'·23
Series 54/74
DM5426/DM7426(SN5426/SN7426 )
quad 2-input TTL-MOS interface gate
general description
These Series 54/74 compatible gates are high output voltage versions of the DM5403 (SN5403),
DM7403 (SN7403)_ Their open-collector outputs
may be "pulled-up" to +15 volts in the logical
"1" state thus providing guaranteed interface between TTL and MOS logic levels_
In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 15 volts_
features
•
15V standoff voltage
• Pin compatible with DM5403/DM7403
schematic and connection diagrams
Dual-In-Line Package
~----~~-----ov~
4K
INPUTS
16K
OUTPUT
0-;;.+-....,
L---+--o.O.
.0.
TOP VIEW
typical applications
'5V
"V
L-
Note Normlll voltages apphed
to MOS"'dtftglstershl'le
-12V
1-24
b•• nslllfhdby+10Volu
for tIlls IppllcatJon
absolute maximum ratings
7V
5.5V
15V
Vee
Input Voltage
Output Voltage
Operating Temperature Range
DM5426
DM7426
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
Input Diode Clamp Voltage
_55°C to 125°C
O°C to 70°C
_65°C to + 150°C
300°C
(Note 1)
CONDITIONS
MIN
TYP
Vee = 5.0V, T A= 25°C
liN = -12 mA
Logical "1" Input Voltage
4.5V
Vee = 4.75V
Logical "0" Input Voltage
4.5V
Vee = 4.75V
Logical "1" Output Current
4.5V
Vee: 4.75V
MAX
UNITS
-1.5
V
V
2.0
0.8
V IN : 0.8V
50
o
V
J1.A
V OUT : 12V
Logical "1" Output Breakdown
Voltage
Logical "0" Output Voltage
4.5V
Vee: 4.75V
V IN : OV
V
15
IOUT= 1 mA
4.5V
Vee: 4.75V
V IN : 2.0V
0.4
V
lOUT: 16 mA
Logical" 1" I nput Current
5.5V
Vee: 5.25V
V IN : 2.4V
40
J1.A
Logical "1" Input Current
5.5V
Vee: 5.25V
V IN : 5.5V
1
mA
Logical "0" Input Current
5.5V
Vee: 5.25V V IN : O.4V
-1.6
mA
Supply Current - Logical "0"
(Each Gate)
5.5V
Vee: 5.25V V IN : 5.0V
3.0
5.1
mA
Supply Current - Logical "1"
(Each Gate)
5.5V
Vee = 5.25V V IN ·= OV
1.0
1.8
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee: 5.0V, T A = 25°C
COUT = 15pF, RL = lk
8
17
ns
Propagation Delay Time to a
Logical "1 ", tpd1
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = lk
14
24
ns
Note 1: Mm/Max UOIts apply across the guaranteed temperature range -25°C to +125°C for the DM5426 and across the
to +70°C for the DM7426 unless otherwise specified. All typicals are given for Vee = 5.0V and TA = 25°C.
aOc
1·25
Series 54/74
DM5430/DM7430(SN5430/SN7430) 8-input gate
general description
features
Employing TTL (Transistor-Transistor Logic) to
achieve high speed at moderate power dissipation,
the DM5430IDM7430 provides the basic functions
used in the implementation of digital integrated
circuit systems. Characteristics of the circuit include high noise immunity, low output Impedance, good capacitive drive capability, and
minimal variation in switching times with temperature.
•
Typical Noise Immunity
•
Guaranteed Noise Immunity
•
•
Fan Out
Average Propagation Delay
•
Average Power Dissipation
schematic and connection diagrams
UK
4K
(ProtectJve DIodes Connected
To Each Input)
DM5430/DM7430
DM5430
DualMI n-Line Package
Flat Package
GND
TOP VIEW
1·26
1V
400mV
10
13 ns
10 mW per gate
c
absolute maximum ratings
operating conditions
MIN
Vee
Input Voltage
Storage Temperature Range
Fan-Out
Lead Temperature (Soldering. 10 sec)
:is:
7V
5.5V
_65°C to +150o e
10
300°C
Supply Voltage IVeel
DM5430
DM7430
Temperature IT AI
DM5430
DM7430
C1I
MAX
UNITS
~
W
0
.......
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°e
C
:is:
....,
~
W
0
electrical characteristics
(Note 1)
CONDITIONS
PARAMETER
MIN
TYP
MAX
Input Diode Clamp Voltage
Vee = 5.0V, T A = 25°C, liN = -12 mA
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
Vee = Min, V IN = 0.8V, lOUT = -400 IlA
Logical "0" Output Voltage
Vee = Min, V IN = 2.0V, lOUT = 16 mA
Logical "1" Input Current
Vee
Max, V IN = 2.4V
40
Logical "1" Input Current
Vee = Max, V IN = 5.5V
1
mA
Logical "0" I nput Current
Vee = Max, V IN = O.4V
-1.6
mA
Output Short Circuit Current
Vee = Max, V IN
Supply Current-Logical "0"
Vee = Max, V IN = 5.0V
5.1
mA
Supply Current-Logical" 1"
Vee = Max, V IN = OV
1.8
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee = 5.0V, T A = 25°C, C = 50 pF
Propagation Delay Time to a
Logical "1 ", tpdl
Vee = 5.0V, T A = 25°C, C = 50 pF
=
-1.5
UNITS
V
2.0
0.8
=
OV
DM5430
DM7430
V
2.4
V
D
V
0.4
"':'55
-20
-18
12
V
IlA
mA
mA
15
ns
22
ns
Note 1: Unless otherwise specified minImax limits apply across the -5SoC to + 12S oC temperature range for the DM5430 and
across the oOe to 70°C range for the DM7430. All typical, are given for Vee = 5.0V and T A = 25°C.
1·27
illS
Series 54/74
OM5432/0M7432(SN5432/SN7432)
quad 2-input OR gate
general description
features
The DM5432/DM7432 (SN5432/SN7432) is a
quad 2-input OR gate utilizing TTL (TransistorTransistor Logic) to provide the basic functions
used in the implementation of digital integrated
circuit systems_ The device is completely compatible with all other Series 54/74 devices.
• Popular digital logic block
• Saves inverter function when sign inversion is
not needed
logic and connection diagram
Dual-In-Line and Flat Package
GND
TDPVIEW
1·28
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM7032
DM8032
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
7V
5.5V
5.5V
-55°e to 125°e
oOe to 700 e
-65°e to 1500 e
3000 e
(Note 2)
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
LogIcal "1" Input Voltage
DM5432
DM7432
Vee = 4.5V
Vee = 4.75V
LogIcal "0" Input Voltage
DM5432
DM7432
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Voltage
DM5432
DM7432
Vee = 4.5V
Vee - 4.75V
VI .. =2.011, lOUT = -400 p.A
LogIcal "0" Output Voltage
DM5432
DM7432
Vee = 4.5V
Vee - 4 75V
VIN = 8V. lOUT = 16 mA
Logical "1" Input Current
DM5432
DM7432
Vee = 5.5V
Vee = 5.25V
V IN = 2 4V
40
p.A
DM5432
DM7432
Vee = 5.5V
Vee = 5.25V
V IN = 5 5V
1
mA
Logical "0" Input Current
DM5432
DM7432
Vee = 5.5V
Vee = 525V
V IN = 0.4V
-1.6
mA
Output Short ClfCUlt Current
(Note 31
DM5432
DM7432
Vee = 5.5V
Vee - 5.25V
Supply Current - LogIcal "1"
(Each Devicel
DM5432
DM7432
Vee= 5.5V
Vee = 5.25V
V IN = 5.0V Each Gate
LogIcal "0"
DM5432
DM7432
Vee=55V
Vee = 5.25V
VI .. = OV Each Gate
2.0
.8
2.4
Vee = 5.0V. TA = 25°C. lIN = -12 mA
Propagation Delay to a Logical "0", tpdO
Vee = 5 OV. TA = 25°C. Cc = 50 pF.
Rc = 4000
Propagation Delay to a Logical "1",
Vee = 5.0V. TA = 25°C. Cc = 50 pF.
Rc = 4000
V
V
.4
-1.0
-20
-18
Input Clamp Voltage
tpd1
V
-32
-55
V
D
mA
4.4
mA
8.8
mA
-1.0
-1.5
V
5
15
22
ns
5
12
18
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Nota 2: Unless otherwise specified minimax limits apply across the _55°C to +125°C temperature
range for the DM5432 and across the 0° C to 70° C range for the DM7432. All tyPlcals are gIven for
VCC = 5.0V and TA = 25°C.
Note 3: Only one output at a tIme should be shorted.
1-29
Series 54/74
DM5437/DM7437(SN5437/SN7437) quad 2-input NAND buffer
DM5438/DM7438(SN5438/SN7438) quad 2-input NAND buffer
(open collector)
features
general description
These are quad two-input NAND buffers. The
DM5437/DM7437 has a normal TTL "Darlington"
output configuration whereas the DM5438/
DM7438 has an open-collector. Aside from the
output, the circuitry is identical.
•
Series 54/74 TTL and DTL compatible
•
I nput clamping diodes
• Typical noise immunity
1V
•
30
Fan Out
schematic and connection diagrams
DM5437/DM7437
DM5438/DM7438
4Kn
GOOn
loo!!
" , - - " " , - - - - 0 v"
OUTPUT V
INPun {
:0--+-.
'--""'--""'--11-00 G••
'--""'--+---11-""'--0 G••
Dual-In-Line and Flat Package
10
II
IV
2A
TOP VIEW
"
3A
3V
2B
2Y
GN.
t
POSITIVE LOGIC V.,Q
tplO ...om_1s far ttIasa CircUits In the lime for all pacag.
1-30
OUTPUT Y
absolute maximum ratings
VCC
Input Voltage
Output Voltage
operating conditions
(Note 1)
MIN
7.0V
5.5V
5.5V
Operating Temperature Range
Storage Temperature Range
Supply Voltage
DM5437,DM5438
DM7437,DM7438
aOc to +70°C
-65°C to +150°C
Lead Temperature (Solderong, 10 sec)
4.5
4.75
Temperature (TA)
DM5437, DM5438
DM7437, DM7438
300°C
MAX
-55
0
5.5
5.25
UNITS
V
V
°c
°c
+125
70
c
3:
UI
~
W
CD
.......
electrical characteristics
c
.....
(Note 2)
3:
~
W
PARAMETER
CONDITIONS
Logical "I" Input Voltage
Vee
= Min
Logical "0" Input Voltage
Vee
= Min
Logical "I" Output Voltage
DM5437
--DM7437
Vec
= Min, V ,N = 0 8V,
Logical "I" Output Current
DM5438
DM7438
Vec
= Min,
Logical "0" Output Voltage
Vec
= Min, V ,N = 2 OV,
Logical "I" Input Current
_
V ,N
Vec - Max, V ,N
Logical "0" Input Current
Vee
= Max,
DM5437
-_.
DM7437
Vee
=
Supply Current DM5437/DM7437
Logical "I" (each deVice) DM5438/DM7438
Vee
= Max, All
DM5437/DM7437
DM5438/DM7438
Vee
= Max
Vee
= Min, T A = 25°C,
Output Short
CirCUit
Current
(Note 3)
Logical "0"
Input Clamp Voltage
MIN
TYP
MAX
08
V ,N
V ,N
lOUT = 4 2 mA
2.4
250.0
= 48 mA
= 24V
= 5 5V
= 0 4V
-200
Max
Il A
04
V
400
10
IlA
mA
-16
mA
-70.0
mA
Inputs at OV
9
15.5
mA
All Inputs at 5V
34
540
,11A
-15
V
liN
= -12 mA
Propagation Delay to a
Logical "0" tpdO
DM5437
DM7437
= 5.0V
T A = 25°C
9
150
ns
Propagation Delay to a
Logical "0" tpdO
DM5438
DM7438
TA
= SOV
= 2SoC
11
180
ns
Propagation Delav to a
DM5437
DM7437
TA
Vr;c=50\t
= 2S"C
13
220
ns
DM5438
DM7438
TA
= SOV
= 2SoC
14
22.0
ns
Logical "I"
tpdl
Propagation Delay to a
Logical "I" tpdl
Vee
Vee
Vee
CD
01
V
V
= a 8V, V OUT = 5 5V
lOUT
UNITS
V
20
Not8 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The
table of "Electrical Characteristics" prOVides conditions for actual deVice operation.
Nota 2: Unless otherwise specified minImax limits apply across the -S5°C to +12SoC temperature range for the DM54371
DM5438 and across the rf C to 70°C range for the DM7437, DM7438. All tYPical. are given for V CC = 5.0V and T A = 25° C.
Nota 3: Only one output at a time should be shorted.
1-31
Series 54/74
DM5440/DM7440(SN5440/SN7440) dual 4-input buffer
general description
features
Employing TTL (Transistor-Transistor-Logic) the
DM5440/DM7440 buffer is used when the high
fan-out is desirable_ In addition to driving a large
number of TTL inputs, this buffer can be used to
drive lines between equipments, to operate small
relays and lamps (50 mA). and to act as a clock
driver for synchronous logic systems_ It is completely compatible with other Series 74 devices_
•
Typical Noise Immunity
•
Guaranteed Noise Immunity
•
Fan Out
•
Diode Clamps on Inputs
Vee
OUTPUT X
Schematic shows one half of dual unit
Dual-I n-Line Package
1-32
400mV
30
schematic and connection diagrams
DM5440/DM7440
1V
DM5440
Flat Package
absolute maximum ratings
Vee
Input Voltage
Storage Temperature Range
Fan-Out
Lead Temperature (Soldenng, 10 sec)
operating conditions
7.0V
5.5V
_65°C to +150°C
30
3000 e
electrical characteristics
PARAMETER
Supply Voltage (Vee)
OM 5440
OM 7440
Temperature (T A)
OM5440
OM7440
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°e
(Note 1)
CONDITIONS
MIN.
TYP.
MAX.
UNITS
-1.0
-l.S
V
Input Diode Clamp Voltage
Vee = S.OV, TA = 2Soc, liN = -12 mA
Logical "1"
Input Voltage
Vee= Min
Logical "0"
I nput Voltage
Vee=Min
Logical "1"
Output Voltage
Vee= Min, Y'N = 0.8V, lOUT = -1.2 mA
Logical "0"
Output Voltage
Vee=Min, Y'N = 2.0V,l oUT = 48 mA
Logical "1"
I nput Current
Vee = Max, Y'N = 2.4V
Logical "1"
I nput Current
Vee= Max, Y'N = S.SV
1.0
mA
Logical "0"
Input Current
Vee = Max, Y'N = O.4V
-1.6
mA
Output Short
Circuit Current
(Note 2)
Vee = Max, Y'N = OV
-SS
-70.0
mA
Supply Current - Logical "0"
(Note 3)
Vee = Max, Y'N = S.OV, 2SoC
8.6
11.4
mA
Supply Current - Logical" 1"
(Note 3)
Vee = Max, Y'N = OV, 2SoC
2.0
3.6
mA
Propagation Delay Time to
Logical "0", tpd 0
Vee = S.OV, TA = 2SoC, C = SO pF
F.O. = 30
10
lS
ns
Propagation Delay Time to
Logical "1", tpd1
Vee = S.OV, T A = 2Soc, C = SO pF
F.O. = 30
8
2S
ns
2.0
V
0.8
2.4
V
0.4
40
-24.0
V
V
I1A
Note 1: Unless otherwise specified minimax limits apply across the _55°C to +12S oC temperature range for the DM5440 and
across the oOe to 700 e range for the OM7440. All typicals are given for Vee = 5.0V and TA = 25°e.
Note 2: Not more than 1 output should be shorted at a time.
Note 3: Each gate.
1·33
«
....
'It
~
~S
Series 54/74
c
.......
«
....'It
'It
It)
:e
DM5441A/DM7441A (SN5441A/SN7441A)
BCD to decimal decoder/nixie* driver
C
general description
The DM5441 A/DM7441 A is monolithic binarycoded-decimal to decimal decoder. The BCD
number to be decoded is applied to the four
input lines; and the unique output corresponding
to the decimal equivalent of the input number
falls to a logical 0 level. Outputs are designed to
dnve gas-filled-readout (Nixie") tubes but are also
able to operate with other low current lamps
and relays.
An over-range feature provides that if binary numbers between 10 and 15 are applied to the input
the least significant bit of these numbers (0
through 5) will be decoded on the output.
logic table
connection diagram
Dual~1 n~Line
and Flat Package
.N.
INPUT
•
lOW OUTPUT
0
C
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
2
3
0
1
0
0
0
1
0
1
0
1
0
1
A
0
0
0
4
5
•
7
0
1
1
1
1
0
0
0
8
0
0
1
9
0
0
1
1
(OVER RANGE)
typical applications
1
0
1
1
0
1
1
1
1
0
0
2
1
1
1
3
4
1
1
0
1
1
1
1
0
1
5
Nixie* Readout
"
Over-Range Decoding
INDICATOR TUBE
OVER RANGE
INDICATOR
:~~-:.t::~: DM5441AfoM7441A
8CO INPUT
Note: Values for B+ and RL are as specified by the
tube manufacturer.
*Trademark of Burroughs Corporation
1-34
absolute maximum ratings
Supply Voltage (Veel
Output Voltage
I nput Voltage
Operating Temperature Range
7.0V
70V
5.5V
_55°C to +125°C
OOC to +700 C
_65°C to +1500 C
300°C
DM5441A
DM7441A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 1\
PARAMETER
Logical 1 Input Voltage
Logical 0 Input Voltage
Logical 1 I nput Current
(all inputs)
Logical 1 I nput Current
Logical 0 I nput Current
Supply Current
.
MIN
CONDITIONS
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
Logical 1 Output Breakdown DM7441A
Vee; 4.5V
Vee = 5.25V
Vee; 5.5V
Vee - 5.25V
Vee = 5.5V
Vee - 5.25V
Vee; 5.5V
Vee - 5.25V
Vee = 5.5V
Vee - 5.25V
Logical 1 Output Current
DM5441A
DM7441A
Vee = 5.5V
Logical 0 Output Voltage
DM5441A
DM7441A
Vee = 4.5V
Vee = 5.25V
Vee = 4.75V
MAX
UNITS
2.0
Vee; 4.75V
Vee; 4.5V
Vee = 4.75V
Vee; 5.5V
TVP
(Note 2)
V
0.8
V 1N = 2.4V
3
V 1N = 5.5V
40
V
iJ.A
1
mA
V 1N ; O.4V
-1.0
-1.6
mA
V 1N ; O.OV
21
36
mA
70
lOUT = 1.0 mA
85
V
V OUT = 50V
125°
70°
25°
0°
_55°
60
40
1.8
1.8
1.8
iJ. A
lOUT = 7 mA
125°
70°
25°
0°
_55°
3.0
2.5
2.5
2.5
2.5
V
1.4
Note 1: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the DM5441A,
and the O°C to +70°C temperature range for the DM7441A.
Note 2: All typicals apply at 25°C for
Vee
:0:
5V.
1·35
.......
...
10
DM5442/DM7442 (SN5442/SN7442) BCO-to- decimal decoder
:E
general description
N
Series 54/74
:E
Q
......
N
Q
The DM5442'/DM7442 utilizes Series 54/74 compatible circuitry to decode a four-bit BCD number
to one-of-ten decimal outputs_ These ten decimal
outputs are capable of driving 10 standard TTL
loads each.
The decoding logic is designed such that when
binary numbers between 10 and 15 are applied to
the inputs, no outputs are enabled.
logic and connection diagrams
Dual-In-Line and Flat Package
, ,
,
OU1l'UTOUTftlTOUTI'Ut
v"
OUTPUT OUTPUT OUTPUt Out",YDUTPIIT OUY'UT OUTPUT
•
I
•
I
4
5
I
logic table
IN""'TS
DC8A
000
000
00 1
00 1
01 0
0
1
0
1
0
o10
o11
o11
0
1
1
1 0 0 0
, 0 0 1
1 0 1 0
OUTNT'
, 0 1 1
1 1 00
1 1 0 1
1 1 1 0
1111
01
01
10
II
II
II
II
II
II
II
II
II
II
II
II
II
II
.. .
OUTPUTS
23
II
II
01
10
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
01
I 0
II
II
II
II
II
II
II
II
II
II
, 88
II
II
II
II
II
II
I
I 0
II
II
II
II
II
II
II
II
o
II
II
II
II
II
II
II
II
I
10
II
II
II
II
II
II
o
typical application
r--------,
DAlOG
OUTPUT
I
I
I
---------.,I
I
I
~I~--~
I
DEtaDEA
OuTPUT
""
~
~TDMM451
GATE
lI,f
10k
IlTlRfACEIIUWllRK
FOR EACH lIlIE
4511UllC
I
I
L. __
USE381T
SYIICHRONOUS
COUfiTER
ASIItPUT
1-36
absolute maximum ratings
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range
DM5442
DM7442
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
Logical "1" Input Voltage
LogIcal "0" Input Voltage
Logical" 1" Output Voltage
Logical "0" Output Voltage
LogIcal "1" Input Current"
Logical "1" Input Current
Logical "0" Input Current
Input Clamp Diode (All Inputs)
Output Short Circuit Current
(Note 2)
Power Supply Current
+7V
+5.5V
10
_65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
(Note 1)
MIN
CONDITION
DM5442
DM7442
Vce
Vee
DM5442
Vee
DM7442
Vee
= 4.5V
= 4.75V
0.8
DM5442
Vee
Vee
= 4.5V
lOUT = -400 IJ.A
= 4.75V
DM5442
Vee
= 4.5V
DM7442
Vee - 4.75V
DM5442
Vee
DM7442
Vee - 5.25V
DM5442
Vee
DM7442
Vee
= 5.5V
V ,N = 5.5V
= 5.25V
DM5442
Vee
= 5.5V
DM7442
Vee - 5.25V
DM5442
Vee
Vee
V ,N
V ,N
= 16 mA
0.4
= 2.4
= 0.4V
= 5 5V V
OUT
= 5.25V
DM5442
Vee
Vee
DM5442
Vee = 5.5V
Vee - 5.25V
=
OV
-20
-18
V
V
2.4
= 5.5V
l'N = -12 mA
= 5.25V
DM7442
DM7442
lOUT
UNITS
V
= 4.5V
= 4.75V
= 5.5V
MAX
2.0
DM7442
DM7442
TVP
V
40
IJ.A
1
mA
-1.0
-1.6
mA
-1.0
-1.5
V
-32
-55
mA
28
56
mA
PropagatIon Delay T,me to a
LogIcal "0" (2 LogIc Levels)
Vee = 5.0V, TA = 25°C,
C.o UT = 50 pF F.O. = 10
10
23
30
ns
PropagatIon Delay Time to a
Logical" 1" (2 Logic Levels)
Vee = 5.0V, T A = 25°C,
COUT = 50 pF F.O. = 10
8
17
25
ns
PropagatIon Delay Time to a
Logical "0" (3 Logic Levels)
Vee = 5.0V, T A = 25°C,
COUT = 50 pF F.O. = 10
12
24
35
ns
PropagatIon Delay Time to a
Logical "1" (3 Logic Levels)
Vee = 5.0V, T A = 25°C,
COUT = 50 pF F.O =10
12
26
35
ns
Note 1: MinImax limits apply across the guaranteed operating temperature range _55°C to +12SoC
for DM5442 and
aOc
to 70°C for the DM7442 unless otherwise specified. All typicals are given for
VCC = S.OV and TA = 2SoC.
Note 2. Only one output may be shorted at a time
1-37
Series 54/74
DM5445/DM7445(SN5445/SN7445)
DM54145/DM74145(SN54145/SN74145)
BCD-to-decimal decoder/drivers
general description
The DM5442/DM7442 and DM54145/DM74145
BCD-to-decimal decoder/drivers are fully compatible for use with TTL or DTL logic circuits. Each
circuit features fljll decoding of all valid BCD
input conditions (0 to 9) ensuring that all outputs
will be off for any invalid input condition. Each
output transistor is capable of sinking 80 rnA.
I n the off condition each transistor can withstand
high breakdown voltages (DM5445/DM7445 = 30V
and DM54145/DM74145 = 15V).
features
• 210 mW typical power dissipation
• 30 ns maximum propagation delay
• Series 54/74 compatible
logic and connection diagrams
Dual·1 n-line and Flat Package
OIlTPUT OUTPUT OUTPUl
9
•
,
OUTPUTOIITf'UTOUTPUT OllTPUTOU1PUTDUTPUTOUTPUT
o
1
2
3
4
5
6
truth table
INPUTS
DeB A
o 0 0 0
o 0 0 1
o
o
0
0
0
0
1
1
1
1
1
1
1
1
'-38
0
0
1
1
1
1
o
o
o
o
1
1
1
1
1 0
1 1
0
1
1 0
1 1
0 0
0 1
1 0
1
0
1
1 0
1 1
o
o
,
o
o
OUTPUTS
o
1
01
1 0
11
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1 1
1 1
1 1
1 1
23
1 1
1 1
o1
1 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
, ,,
1
1
1
1
1
1
1
1
4 5
6 7
1 1
1 1
1 1
11
1
1 0
1 1
11
11
1 1
1 1
11
1 1
1 1
1 1
1 1
1
1
1
1
1
1
o
o
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
B 9
1
1
1
1
1
1
1
1
o
1
1
, ,
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
absolute maximum ratingS(Note
Supply Voltage
Input Voltage
Output Voltage
operating conditions
1)
7V
5.5V
30V
15V
DM6445JDM7445
DM54145JDM74145
Supply Voltage (Veel
DM5445,DM54145
DM7445,DM74145
Operating Temperature Range
MIN
MAX
UNITS
45
4.75
5.5
5.25
V
V
DM5445,DM54145 -55°C to +125°e
DoC to +70o
DM7445,DM74145
Storage Temperature Range
_65°C to +150o e
Lead Temperature (Soldering, 10 secl
300°C
e
electrical characteristics (Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
V
Logic "1" Input Voltage
Logic "0" Input Voltage
Output Breakdown Voltage
08
Vee = Max,
Vee = Max,
10FF
10FF
= 250j.lA
= 250j.lA
Logical "0" Output Voltage
Vee = Min, lOUT = 80 mA
Vee = Min, lOUT = 20 mA
Logical "'" Input Current
Vee = Max, Y'N = 24V
Vee = Max, V ,N = 5 5V
Logical "0" Input Current
Vee = Max, Y'N = 04V
Supply Current
Vee =: Max
Vee = Max
Input Clamp Voltage
Vee = 50
TA = 25°C
Propagation Delay to a logical "0",
Vee = 50
TA=250e e L = 15pF R L = lOOn
Vee = 5 0
TA = 25°C CL = 15 pF RL = lOOn
tpdO
Propagation Delay to a Logical "'"
DM5445JDM54145
DM7445JDM74145
liN
30
15
V
V
05
02
09
04
1
j.lA
mA
-16
mA
62
70
mA
mA
40
42
42
= -12 mA
V
V
-15
V
17
30
ns
18
30
ns
D
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operatmg Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" prOVides conditions for actual device operation
Note 2: Unless otherwise speCified minImax limits apply across the _55°C to +12SoC temperature range for the OM5445.
DM54145 and across the O°C to 70°C range for the DM7445,DM74145 All tYPlcals are given for VCC = 5 OV and TA = 25°C.
1-39
o
CD
.......
Series 54/74
~
LO
.......
M
LO
...
DM5450/DM7450(SN5450/SN7450) expandable dual 2-wide 2-input
AND-OR-INVERT gate
DM5451/DM7451(SN5451/SN7451) dual 2-wide 2-input
AND-OR-INVERT gate
DM5453/DM7453(SN5453/SN7453) expandable 4-wide 2-input
AND-OR-INVERT gate
DM5454/DM7454(SN5454/SN7454) 4-wide 2-input
AND-OR-INVERT gate
DM5460/DM7460(SN5460/SN7460) dual 4-input expander
.......
LO
.......
o
LO
~
.....
:E
Q
.......
o
LO
~
LO
:E
Q
general description
features
The devices described in this data sheet employ
TTL to achieve high speed at moderate power
dissipation. They are consolidated onto one sheet
since they perform the AND-OR-INVERT function with only differing numbers of AND inputs
and 0 R terms. Characteristics include high noise
immunity, low output impedance, good capacitance drive capability, and minimal variation in
switching time with temperature. The gates are
compatible with and interchangeable with Series
54/74 devices.
• Input Clamping Diodes
• Typical Noise Immunity
• Guaranteed Noise Immunity
• Fan-out
• Average Propagation Delay
• Average Power Dissipation
1 Volt
400mV
10
13 ns
14 mW/ gate
schematic diagrams
DM54531DM7453,DM5454/DM7454
DM5450/DM7450, DM5451/DM7451 (each gate)
INPUTS
OUTPUT
IN'UTS
EXPANDER
Y
iDM545l/DM145J
~::~~D:=
GAlE I Of
DM5450/1)M145B
ONLY
I' O:====:::"'-~--..!:E-t
I: 0--+_....
\
INPUTS
I' ~===:::j:=1fi=~
l!
ONLY
xO
~--II--O: \INPUTS
DM5460/DM7460 (each gets)
NOTES 1 CDnnlCtptn 90rl21opon 12 of DM64511/DM1450 or DM5453/0M1453
2 Connect PI" 10 IIf 11 to pIn 11 01 DM545OJDM145D 0< DM5453/DM1453
1·40
~+=+:::g:
c
absolute maximum ratings
Vee
Input Voltage
Storage Temperature Range
Fan-Out
Lead Temperature (Soldenng, 10 sec)
s:
U1
operating conditions
7V
5.5V
-65°C to +150 o e
10
300°C
Supply Voltage (Veel
DM54XX
DM74XX
~
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
-55
0
+125
70
o
........
c
s:
"U1
V
Temperature (T A)
DM54XX
DM74XX
U1
~
o
electrical characteristics
........
U1
-A
(Notes 1, 3) (DM5450/DM7450, DM5451/DM7451, DM5453/DM7453,
........
U1
DM5454/DM7454)
PARAMETER
Input Diode Clamp Voltage
CONDITIONS
TYP
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
Vee = Min, V ,N = 0.8V
lOUT = -400 pA
"a" Output Voltage
Vee = Min, V ,N = 2.0V
lOUT = 16 mA
MAX
-1.5
Vce = 5.0V, T A = 25°C
liN =-12 mA
Logical "I" Input Voltage
Logical
MIN
~
o
V
2.0
0.8
204
V
V
0.4
Vee = Max, V ,N = 5.5V
1
mA
Vee = Max, V ,N = Oo4V
- 1.6
mA
Output Short Circuit Current
(Note 2)
Vee = Max, V ,N = OV
Supply Current - Logical "a" (Each Gate)
DM5450/DM7450, DM5451/DM7451
DM5453/DM7453, DM5454/DM7454
Vee = Max, V,N = 5.0V
Supply Current - Logical "1" (Each Gate)
Vee = Max, V,N = OV
DM5450/DM7450, DM5451/DM7451
DM5453/DM7453, DM5454/DM7454
40
-18
-55
0
V
Logical "1" Input Cu rrent
I nput Current
........
0)
Vee = Max, V,N = 204V
"a"
U1
V
Lugical "1" Input Current
Logical
W
........
UNITS
pA
mA
3.7
5.1
6.5
9.5
mA
mA
2.0
4.0
3.6
8.0
mA
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee = 5.0V, T A = 25°C
C=50pF,N=10
15
ns
Propagation Delay Time to a
Logical "1", tpd1
Vee = 5.0V, TA = 25°C
C = 50 pF, N = 10
25
ns
Propagation Delay Time to
Logical "a" Level
(through DM5450/DM7450 or
DM5453/DM7453)
Vee = 5.0V, T A = 25°C
C= 50pF, N = 10
20
ns
Propagation Delay Time to
Logical "1" Level
(through DM5450/DM7450 or
DM5453/DM7453)
Vee = 5.0V, TA = 25°C
C = 50 pF, N = 10
34
os
Note 1: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature range for the DM54XX and
across the cOe to 70°C range for the DM74XX. All typicals are given for Vee = 5.0V and T A = 25°C.
Note 2: Not more than 1 output should be shorted at a time.
Note 3: Measurements made with expandable mputs open.
1-41
o
CD
"'~
an
"'(W)
an
"'an
"'o
an
electrical characteristics
(Note 1) (DM5460/DM7460)
PARAMETER
...
~
r-.
TEST CONDITIONS
Input Diode Clamp
Voltage
Vee = S.OV
liN =-'2mA
Logical "," Input
Voltage
Vee = Min
Logical "0" Input
Voltage
Vee = Min
Rv cc to
MIN
TYP
TA=2SoC
VEMITTEA
COLLECTOR =
REMITTER to GRO
MAX
UNIT
-,.S
V
2
= lV,
V
1.1 k!l, TA = O°C
= 1.2 kn,
V COLLECTOR = 4.5V.
ICOLLECTOR = 0.27 mA,
O.B
V
Y'N = 2V,
0.4
V
T A = O°C
:E
Q
"'o
an
~
an
Logical "0" Output
Voltage (With
Respect to Emitter)
Vee
Logical "," Output
Current
Vee
Logical "0" Output
Current
Vee
= Mm, Y,N = 2V
VEMITTER = IV
DM7460 T A = oOe
DM5460 T A = -55°C
Logical "0" Input
Current
Vee=Max
Y'N = O.4V
-'.6
mA
Logical "," Input
Current
Vee = Max
Y'N = 2.4V
Y'N = S.SV
40
p.A
mA
Logical "0" Supply
Current (Each Gate)
Vee = 5.25V,
VEMITTER = 0.B5V
Y'N = 5V,
0.6
1.25
mA
Logical "," Supply
Current (Each Gate)
Vee = 5.25V,
VEMITTER = 0.B5V
Y'N =0
'.0
I.B
mA
:E
Q
=
Min
VEMITTER
= lV
RVec to
= Min, V ,N = O.BV
VeoLLEeToR = 4.5V
REMITTER to GRD = 1.2
Vee = Max
COLLECTOR
DM7460 TA = DoC
DM5460 TA = -55°C
Expander Current
= O°C for
= Min
'50
p.A
p.A
V P1N
11 to PIN 12
-0.43
-0.3
mA
mA
74XX and T A
MIN
TEST CONDITIONS
Vee
270
kn
(OM5450/DM7450, DM5453/DM7453 only) using expander inputs, T A
PARAMETER
= 1.1 kn.
TYP
= -55°C
for 54XX
MAX
UNIT
3.'
mA
= O.4V
ISINK ='6 mA
Base·Emitter Voltage
of Output
Transistor (Q)
Vee= Min
IplN 11 = 0.62 mA,
ISINK = '6 mA,
RplN 11 to PIN 12 = 0
Logical "," Output
Voltage
Vee = Min
IplN ,,= 0.27 mA,
I LOAD = -400 p.A,
IplN 12 = -0.27 mA
Logical "0" Output
Voltage
Vee = Min
IplN " = 0.43 mA,
ISINK = '6 mA,
RplN 11 to 12 = 130!1
V
2.4
V
0.4
V
Note 1: Unless otherwIse specified minImax limits apply across the _55°C to +125°C temperature range for the DM54XX and
across the O°C to 70°C range for the DM74XX. All tYPical, are given for Vee = 5.0V and T A = 25°e.
connection diagrams
DM5450/DM7450, DM545'/DM7451
Dual·ln·Line Packages (Flat Packages Not Shown)
DM5453/DM7453, DM5454/DM7454
DM5460/DM7460
"
"
",
y " (AB) + JCD) + x
x"
x" ABeD from OM1460
Note 1 Expandtr nodes X Ind Xare on the
DM7450 only. If not used, leave open
Note 2' Make no nternal connection to
pms 11 and 12 of the DM1451
Note 3 A total of four ekpander gates may
lie connected to the DM7450 expandible
....
1·42
Y'" (AB)+(CD)"'(EF)t(GH)+X
."
x = ABeD
X = ABCDfromDM7460
Note 1 Expander nodes XandXareon the
DM1453 only If nOlused,leave open
Note 2. Make no nternal ~onnectlon to
pms 11 and 12 01 tile OM1454
Note 3 Atotijl of four 9Kpander gates may
be connected to the DM1453 expandable
Note 1 Connect Pm 9 or 12 to pm 12 of
DM1450 or OM1453.
Note 2' Connectl'1n 100r 11 tapm 11 of
DM7450
III
OM7453
c
s:
er
+G'" Inputs 1G and 2G connected together
1-87
absolute maximum ratings
(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Operating Temperature Range DM54155,DM54156 _55°C to +125°C
O°C to +70°C
DM74155,DM74156
Storage Temperature Range
_65°C to +150°C
Lead Temperature (soldering, 10 sec)
300°C
electrical characteristics
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
UNITS
Logical "1" Input Voltage
Vee = 45V
Vee 475V
Logical "0" Input Voltage
DM54155,DM54156
DM74155,DM74156
Vee = 4.5V
Vee - 475V
Logical "1" Output Voltage
DM54155
DM74155
Vee = 45V
Vee - 4 75V
lOUT = -800 IlA
Logical "1" Output Current
DM54156
DM74156
Vee = 5 5V
Vee - 525V
VouT=55V
Logical "0" Output Voltage
DM54155,DM54156
DM74155,DM74156
Vee
V ee =45V
475V
lOUT = 16 rnA
DM54155,DM54156
DM74155,DM74156
Vee = 5 5V
V ee -525V
V'N = 24V
40
I'A
DM54155,DM54156
DM74155,DM74156
Vee= 55V
Vee 525V
V'N = 5 5V
1
rnA
DM54155,DM54156
DM74155,DM74156
Vee=55V
Vee - 525V
V'N=04V
-1.6
rnA
DM54155
DM74155
Vee = 55V
Vee - 525V
V OUT = OV
V OUT = OV
Supply Current
DM54155,DM54156
DM74155,DM74156
Vee = 5.5V
Vee = 5.25V
Input Clamp Voltage
DM54155,DM54156
DM74155,DM74156
Vee = 5.5V
Vee - 5.25V
Logical "1" Input Current
Logical "0" Input Current
Output Short Circuit Current
(Note 3)
switching characteristics
Vee
PARAMETER
FROM
INPUT
TO
OUTPUT
LEVELS
OF LOGIC
tpdl
A, B, 2C,
lG, or 2G
Y
2
tpdO
A, B, 2C
lG, or 2G
Y
2
tpdl
A or B
Y
3
tpdO
AorB
Y
tpdl
lC
tpdO
lC
=
5V, T A
=
20
V
0.8
24
250
IlA
0.4
-1.0
-20
-18
liN = -12 rnA
V
V
V
-32
-55
rnA
25
40
rnA
-1.0
-1.5
V
25°C, N = 10
TEST
CONDITIONS
DM54155/DM74155
MIN TYP MAX
DM54156/DM74156
MIN
TYP MAX
UNIT
17
26
ns
14
21
19
30
19
30
ns
18
27
22
33
ns
3
17
26
18
27
ns
Y
3
18
27
21
32
ns
Y
3
17
26
18
27
ns
CL = 50 pF,
RL = 400Q
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electncal Characterlstlcs" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM54155,DM54156 and across the O°C to 70°C range for the DM74155,DM74156.
All typlcals are given for VCC = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
1-88
MAX
DM54155,DM54156
DM74155,DM74156
c
s::
CJI
Series 54/74
...en
~
en
......
c
s::......
DM54166/DM74166(SN54166/SN74166) 8-bit shift register
...en
~
general description
The DM54166/DM74166 is a parallel-in serial-in,
serial-out eight-bit shift register containing a gated
Clock, and overriding Clear. The parallel-in or
serial-in modes are determined by the Shift/Load input. The truth table below indicates the operation.
During parallel loading shifting is prohibited. Clocking is accomplished on the rising edge of the
clock pulse through a 2-input NOR gate, permitting one input to be used as a clock-inhibit
en
function. Holding either of the inputs high inhibits clocking. To prevent false clocking the clock
inhibit input should be taken high only when the
clock input is high.
features
• Shift Frequency
35 MHz
•
360mW
Power Dissipation
o
logic diagram
CLEAIISERIAl SHlfTl A
DATA
H
LOAD
CLOCk CLOCK
INHIBIT
connection diagram
Dual-I n-Line and Flat Package
PARALLEL
Vee
I.
15
I
SERIAL
INPUT
PARALLELIN'UTS
~~!~I IN~UT OU~:UT
2
14
l
E ' CLEAR
i
"
12
11
,
SHIFT LOAD
.• .
A
10
truth table
0
'--_~_--'
1
CLOCK CLOCK
INHIBIT
FUNCTION
1
Serial In Serial Out
0
Parallel In Senal Out
r
GND
PARAllELINPUT$
TOPVIEft
1-89
CD
CD
w-
~
.....
absolute maximum ratings (Note
1)
operating conditions
~
MIN
Q
.......
Supply Voltage
Input Voltage
CD
CD
Output Voltage
W-
Storage Temperature Range
~
Lead Temperature (Soldering. 10 sec)
It)
7V
55V
5.5V
_65°C to +150oe
300°C
~
Supply Voltage (Vee)
DM54166
DM74166
Temperature (T A)
DM54166
DM74166
4.5
475
-55
0
UNITS
MAX
5.5
525
V
V
°e
°e
+125
70
Q
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee
= Mm
Logical "0" Input Voltage
Vee
= Min
Logical "'" Output Voltage
Vee = Mm
V ,H = 2V
lOUT = -800 /-IA
V'L = 0 8V
Logical "0" Output Voltage
Vee = Min
V ,H = 2V
lOUT = 16 rnA
V'L =08V
Logical" 1" I nput Current
Vee
= Max
Y'N = 2 4V
Input Current at Max Input Voltage
Vee
= Max
Y'N = 5 SV
Logical "0" Input Current
Vee
= Max
Y'N =04V
Output Short Circuit Current
(Note 3)
Vee"" Max
Supply Current
Vee
==-
MIN
TYP
MAX
2
UNITS
V
08
24
V
V
04
V
40
IlA
1
rnA
-16
rnA
-20
-18
Max
-55
-57
rnA
rnA
104
116
rnA
Input Clamp Voltage
Vee'" Mm
liN =-12 mA
Propagation Delay to a Logical "0" from
Clear to Output. tpdO
Vcc=SOV
T A = 25°C
CL ° SO pF. RL = 40012
3S
ns
Propagation Delay to a Logical "0" from
Vcc=SOV
TA = 2SoC
CL = SO pF. RL = 40012
30
ns
Propagation Delay to a Logical "1" from
Clock to Output, tpd1
VccoSOV
TA = 2SoC
CL = SO pF. RL = 40012
26
ns
MaXimum Clock Frequency
Vcc=SOV
TA = 2SoC
Clock to Output,
tpdO
-1 S
2S
V
3S
MHz
Minimum Clock and Clear Pulse Width
Vcc=SOV
T A = 2SoC. CL = 50 pF
20
Data Setup Time
Vcc=SOV
T A = 2Soe, CL = SO pF
20
ns
Mode Control Setup Time tSETUP
Vcc=SOV
T A = 2Soe. CL = SO pF
30
ns
Hold Time at Any Input, tHOLO
Vcc=SOV
T A = 2SoC. CL = 50 pF
0
ns
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed.
Except for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these
limits. The table of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherwise specifIed mm/max limits apply across the --55°e to +125°e temperature range for the DM54166
and across the oOe to +70oe range for the DM74166. All typicals are given for Vee = 5.0V and TA = 25°C.
Note 3: Only one output at a time should be shorted.
1·90
Series 54/74
OM 54174/DM74174(SN54174/SN74174),
OM 54175/DM74175(SN54175/SN74175)
hex/quad D-type flip-flops with clear
general description
These monolithic, positive edge triggered flipflops utilize TTL circuitry to implement D-type
flip-flop logic. All have a direct clear input, and
the DM54175/DM74175 feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup
time requirements is transferred to the Q outputs
on the positive going edge of the clock pulse.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive going pulse. When the clock
input is at either the high or low level, the D input
signal has no effect at the output.
These circu its are fully compatible for use with
most TTL or DTL circuits. A full fan out to 10
normalized series 54/74 loads is available from
each output at low logic levels, and to 20 loads
at high logic levels to facilitate connection of
unused inputs to used inputs. Maximum clock
frequency is typically 35 MHz, with a typical
power dissipation of 38 mW per flip-flop.
The DM54174 and DM54175 are characterized
for operation ° over the f~1I military temperature
range of -55 C to +125 C. The DM74174 and
DM74175 are characterized for operation from
O°C to + 70°C.
features
o
•
DM54174/DM74174 contain six flip·flops with
single-rail outputs
• DM54175/DM74175 contain four flip-flops with
double-rail outputs
• 8uffered clock and direct clear inputs
• Individual data input to each flip-flop
applications
• 8uffer/storage registers
• Shift registers
• Pattern generators
connection diagrams
DM54175/DM74175
DM54174/DM74174
Dual·1 n-Line and Flat Package
/
Vee
60
60
50
CLEAR
10
10
ZD
20
TOP VIEW
30
Dual-In-Line and Flat Package
3D
GND
TOP VIEW
1·91
absolute maximum ratings (Note
1)
Supply Voltage (Vee)
DM54174, DM54175
DM74174,DM74175
7.0V
5.5V
5.5V
Supply Voltage, Vee (Note 4)
Input Voltage (Note 4)
Output Voltage
Storage Temperature Range
-6SoC to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
electrical characteristics
operating conditions
Temperature (T A)
DM54174,DM54175
DM74174,DM74175
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
°e
-55
0
(Note 2)
PARAMETER
CONDITIONS
High Level Input Voltage (V ,H )
MIN
TVP
MAX
Low Level Input Voltage (V ,L )
~
= -12 mA
Input Clamp Voltage (V,)
Vee
High Level Output Voltage (V OH )
Vee ~ Min, V ,H = 2.0V
V'L = 0.8V, 10H = -8001lA
Low Level Output Voltage (VOL)
Vee ~ Min, V ,H = 2.0V
V'L = 0.8V, 10L = 16 mA
Input Current at Maximum Input
Voltage (I,)
Vee
High Level Input Current (I,H)
Vee ~ Max, V, = 2AV
Low Level I nput Current (I, cI
Vee
~
~
Min, I,
UNITS
V
2.0
0.8
V
-1.5
V
204
V
Max, V, = 5.5V
Max, V, = OAV
004
V
1.0
mA
40
IlA
-1.6
mA
0
20
ns
20
30
ns
ns
0
ns
Setup Time (tsETUP) (See waveforms)
Data Input
Clear Inactlve State
Data Hold Time (t HoLO )
(See waveforms)
30
MHz
Input Clock Frequency (feLoeK)
Width of Clock or Clear Pulse (tw)
(See waveforms)
Short CircUit Output Current (los)
(Note 3)
DM54174,DM54175
DM74174,DM74175
Vee ~ Max
Vee = Max
Supply Current (I eel
DM54174/DM74174
DM54175/DM74175
V ec ~ Max (Note 2)
Vee = Max (Note 2)
Maximum Input Clock Frequency
(f MAX )
RL = 40011, CL = 50 pF
(See Figures 1 and 2)
Propagallon Delay Time, Low to
High Level Output from Clear (t PLH )
DM54175/DM74175 only
RL = 40011, C L ~ 50 pF
(See ac test circuit)
14
25
ns
Propagation Delay Time, High to
Low Level Output from Clear (tPHL)
RL = 40011, C L = 50 pF
(See ac test CirCUit)
20
30
ns
PropagatIOn Delay Time, Low to
High Level Output from Clock (teLH)
RL = 40011, C L = 50 pF
(See ac test circuit)
14
25
ns
Propagation Delay Time, High to
Low Level Output fr9m Clock (tPHcI
RL = 40011, C L = 50 pF
(See ac test circuit)
17
25
ns
-20
-18
45
30
30
-57
-57
mA
mA
65
45
mA
mA
MHz
40
Note 1: "Absoh.. te Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +125°C temperature range for the DM54174
and DM54175 and across tlte oOe to +70o e range for the DM74174 and DM74175. All typicals are given for Vee ~ 5.0V and
TA = 25°C.
Note 3: Note more than one output should be shorted at a time.
Note 4: Voltage vaJues are with respect to network ground terminal.
Nete 5: With all outputs open and 4.SV applied to all data and clear inputs, ICC is measured after the mom~ntary ground,
tIIen 4.5V, is applied to clock.
1·92
truth table
(each flip-flop)
OUTPUTS
INPUTS
0
CLOCK
CLEAR
0
0*
H '" high level {steady statel
L tow level (steady state)
H
x '" .rr~levant
L
X
X
L
H
t
t
H
H
L
H
L
L
H
H
L
X
Qo
=0
t '"
tranSition from low to high level
0 0 '" the level of Q before the indicated steady-state
Input conditions were established
-
*DM54175/DM74175 only
Qo
block diagrams
DM54174/DM74174
10
Q
(2)
1Q
CK
DM54175/DM74175
CLEAR
20
JD
10
(.)
(6)
'0
141
Q
'"
10
III
I.
151
161
40
(12)
1111
..
(13)
.0
(131
(t4)
60
,.
(11)
3D
50
D
••
(14)
CLEAR
111
ClOCI("""--I .....~_--'
ClEAR'~I1:!..J<>I~>o--........._.J
---1>,
DYNAMIC ,.PUT ACTIVATED BY TRANSOTla" fROM A HIGH LEVEl TO A laW LEVEl
1-93
o
...
CO
Series 54/74
~
....
:!
Q
......
o
...
CO
~
DM54180/DM74180(SN54180/SN74180)
8-bit odd/even parity generator/checker
It)
:!
Q
general description
features
The DM54180(DM74180 can both generate and
check parity on eight bits of information. Separate
Inputs are provided which perform a two·fold pur·
pose. They can be used to gate the outputs to a
known state regardless of the conditions on the
data Input.s; and in addition they can be used for
conven lent expansion of longer words.
•
TYPical propagation delay
30 ns
•
Typical power dissipation
180mW
•
Ease of expansion
logic diagram
EVEN
OUTPUT
DATA
INPUTS
ODD
OUTPUT
IN~~~ o_-------------.,......---'
I~~~~o-------------------'
connection diagram
truth table
Dual-In-Line and Flat Package
DATA
INPUTS
I"
13
12
11
10
•
9
NUMBER OF BIT "1 "S
AT DATA INPUTS
Even Number
Odd Number
Even Number
Odd Number
Even or Odd
-
1
1
G
H
---..----'
3
EVEN
INPUT
4
DO~
INPUT
DATA
INPUTS
TOPV1EW
1·94
Even or Odd
f-
5
6
EVEN
000
OUTPUT OUTPUT
I'
GND
INPUTS
OUTPUTS
EVEN
ODD
EVEN
1
0
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
ODD
0
c
3:
absolute maximum ratings
Supply Voltage
Input Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
(Note 1)
7V
5.5V
-65'C to +150'C
300'C
UI
...
operating conditions
Supply Voltage (VCC)
DM54180
DM74180
Temperature (T A)
DM54180
DM74180
~
00
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
"C
-55
0
+125
70
'c
~
0
3:
...
~
'C
00
0
electrical characteristics
(Note 2)
PARAMETER
CONDITIONS
Vee
Logical "0" Input Voltage
Vee -= Min
Logical "1" Output Voltage
Vee
=
Logical "0" Output Voltage
Vee
= Mm
Logical "1" Input Current
Vee
=
Mm
TYP
MAX
20
lOUT = -80011A
V
08
V
04
V
2.4
V
lOUT = 16 rnA
V ,N
V ,N
V ,N
V ,N
Vee = Max
= 24V
=55V
- 24V
= 5 5V
40
10
80
1.0
-16
-3.2
Output Short Circuit Current DM54180
(Note 3)
DM74180
Vee::: Max
Supply Current
(Each Device)
Vee::: Max
Input Diode
Vee
Clamp Voltage
=
Min
I1A
rnA
I1A
rnA
U
V ,N = 04V
At Each
Data Inputs (A to H)
At Even or Odd Input
DM54180
DM74180
UNITS
Max
At Each
Data Inputs (A to H)
At Even or Odd Input
Logical "0" Input Current
MIN
= Min
Logical "1" Input Voltage
V OUT = OV
-20
=T8
36.6
366
liN = -12 rnA
TA = 25°C
rnA
-55
--57
rnA
49
56
rnA
-
-15
V
40
45
60
68
ns
ns
32
25
48
38
ns
ns
32
25
48
38
ns
ns
Parameter
tpdl
From Input
To Output
Data
Even
tpdO
tpdl
Odd Input Grounded
Vee = 5.0V
TA = 25'C
Data
Odd
Data
Even
Data
Odd
40
45
60
68
ns
ns
tpd1
Even or Odd
tpdO
Even or Odd
Even or Odd
Even or Odd
13
8
20
10
ns
ns
tpdO
tpdl
tpdO
tpdl
Even Input Grounded
tpdO
C L = 50 pF
F 0 = 10
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherwise specified mm/max limits apply across the -5SoC to +12SoC temperature range for the DM54180,
and across the O'C to 70°C range for the DM74180. All typicals are given for VCC = 5.0V and TA = 25°C.
Note 3: Only one output at a time should be shorted.
1-95
....
00
....
~
Series 54/74
.....
:E
Q
....
00
....
.......
~
DM541811DM74181 (SN541811SN74181) arithmetic logic unit
II)
:E
Q
general description
The DM54181/DM74181 (SN54181/SN74181) IS
a high-speed arithmetic logic unit (ALU)/function
generator that has a complexity of 75 equivalent
gates on a monolithic chip. This circuit performs
16 binary arithmetic operations on two 4-bit words
as shown in the function table. These operations
are selected by the fou r function-select lines (So,
S" 52, S3) and Include addition, subtraction,
decrement, and straight transfer. When perform ing
arithmetic manipulations, the internal carnes must
be enabled by applying a low-level voltage to the
mode control input (M). A full carry look· ahead
scheme is made available in the device for fast,
simultaneous carry generation with a group carry
propagate (1') and carry generate (u) for the four
bits in the package.
High speed arithmetic operations can be performed for up to N-bit words when the DM54181/
DM74181 is used in conjunction with the
DM541821DM74182.
For example, the typical addition time for the
DM54181/DM74181 is 24 ns for four bits. When
expanding to 16-bit addition with the DM54182/
DM74182, only 13 ns further delay is added so
that the total addition time is 37 ns, or 2.3 ns per
bit. One DM54182/DM74182 is needed for every
16 bits (four DM54181/DM74181 circuits).
If high speed is not of Importance, a ripple·carry
input (C n ) and a ripple·carry output (C n +4 ) are
available. However, the ripple-carry delay has also
been minimized so that arithmetic manipulations
for small word lengths can be performed without
external circuitry. The tYPical delay for the ripple
carry is 12 ns for four bits. With a tYPical addition
time of 24 ns for four bits, addition of two 8-blt
words IS accomplished typically in 36 ns when
employ ing the ripple carry.
The DM54181 and DM54182 are characterIZed for
operation over the full military temperature range
of _55°C to 125°C; the DM74181 and DM74182
are chdl acterized for operation from O°C to 70°C.
features
•
Full look·ahead for high·speed operations on
long words
•
Input clamping diodes minimize transmissionline effects
•
Darlington outputs reduce turn·off time
•
ArithmetiC operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
•
Logic function modes:
Exclusive-OR
Comparator
AND,NAND,OR,NOR
plus ten other logical operations
•
24 ns typical add time for four bits
•
12 ns typical carry time for four bits
connection diagram and table
Dual-I n-Line Package
INPUTS
OUTPUTS
~~~----~,
v.IN ~!ID ~!In
fA!
~
~z
1m
,~--~--~
r" ',1,8" j, 'r
~
11 ',6
~ "i' "
IIi
I~
DM54181/0M74181
PIN DESIGNATIONS
13
I I I IIIII II
DESIGNATION
PIN NOS.
FUNCTION
A'"'"B
P
I.
IS
C,,+4
16
Comparator Output
Carry Propagate
Output
Carry Output
DESIGNATION
PIN NOS.
A3.A2,A,.AO
83 ,82 :B, .Bo
19,21,23,2
18,20,22 1
Word A Inputs
Word B Inputs
§"3.S2,S,,!j'O
3,4,5,6
Function-Select
Co
7
Carry Input
G
17
Carry Generate
Output
M
8
Mode Control
Vee
2'
Supply Voltage
F3,F2.Fl.FO
13,11,10,9
Input
Function-Outputs
GNO
12
GROUND
FUNCTION
Inputs
!
liD
111111 I I I I
I' I' I' I' I' I' I' I' J" I" .lIZ
lo
~
s~
~ Jo
~l
sl3
:1
Cn
INPUTS
----.....-OUTPUTS
TOPVIEW
1·96
,
Fl
GNO
c
absolute maximum ratings
s:C1I
(Note 1)
...
...
~
7V
Supply Voltage
55V
55V
_55°C to 125"C
O°C to 70°C
_65°C 10 150"C
300°C
Input Voltage
Output Voltage
Operatmg Temperature Range DM54181
DM74181
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
CO
"s:c
.....
...
...
~
CO
electrical characteristics
(Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
DM54181
DM74181
Vcc=45V
--Vee == 4 75V
Logical "0" Input Voltage
DM54181
DM74181
Vcc=45V
Vee - 4 75V
Logical "1" Output Voltage
DM54181
DM74181
V cc =45V
Vee - 4 75V
V 1H =2V,V 1L =OBV
Logical "0" Output Voltage
DM54181
DM74181
Vcc=45V
Vee - 4 75V
V 1H =2V,V 1L =08V
tOUT = 16 rnA
Logical "1" Input Current
(Mode Input)
DM54181
DM74181
Vcc=55V
Vee - 525V
Logical "1" Input Current
DM54181
DM74181
Vcc=55V
Vee - 525V
Logical" 1" Input Current
(Any S Input)
DM54181
DM74181
Vcc=55V
V cc - 525V
Logical" 1" I nput Current
(Carry Input)
DM54181
DM74181
Vee
Logical" 1" I nput Current
(Any Input)
DM54181
DM74181
Vee'" 55V
V ee - 525V
Logical "0" Input Current
(Mode Input)
DM54181
Vee=55V
--.-;"-"---DM74181V ee =525V
Logical "0" Input Current
DM54181
DM74181
(Any
(Any
A or B I nputl
Ii.. or B Input)
MIN
TYP
MAX
V
2
08
lOUT = -80011A
UNITS
24
V
V
04
V
40
pA
120
pA
160
pA
200
pA
1
rnA
-1
-16
rnA
-3
-48
rnA
VIN -= 24V
Vee
=
55V
525V
V IN
'"
5 5V
Vee'" 5.SV
V ee - 52SV
V!N == 04V
Logical "0" Input Current
(Any S Input)
DM54181
DM74181
~,.--
Vce==5SV
Vee = 525V
-39
-64
rnA
Logical "0" Input Current
(Carry I npu t)
~~;:~~+-
~_=55~
Vee'" 5 25V
-48
-6
rnA
Output Short Circuit Current
DM54181
DM74181·
~,e= 55V
Vee = 525V
(Note 31
-55
-57
rnA
rnA
rnA
rnA
rnA
88
88
DM54181
OM74181
Vee": 5 5V
Vee - 525V
92
92
135
150
DM54181
DM74181
Vee =\4 5V
Vee - 4 7SV
IIN=-12mA
-1
-15
V
Vee'" 50V
TA = 25'C
Ddf Mode (Note 4)
14
19
ns
Vee=50V
TA = 25°C
Dlff Mode
9
18
ns
Vee=50V
TA = 25°C
O!ffMode
13
16
os
Vee = 50V
TA = 25°C
Olff Mode
11
19
ns
Vee = SOV
TA = 25°C
Olff Mode
15
25
ns
Vee=50V
T A = 25()C
Olff Mode
12
25
ns
Vee'" 50V
TA=2S"C
Olff Mode
17
25
ns
Vee == 50V
TA = 25'C
Dlff Mode
11
25
ns
Vee = 50V
T A = 25~'C
o Iff Mode
14
34
ns
GND All As. Bs & Co.
Other Inputs HIGH
Input Clamp Voltage
Propagation Delay to a Logical "0" from
Cn to Cn +4 , tpdO
Propagation Delay to a Logical "1" from
Cn to Cn+4 , tpdl
Propagation Delay to a Logical "0" from
C n to Any F, tpdQ
Propagation Delay to a Logical "1" from
Cn to Any F, tpdl
Propagation Delay to a Logical "0" from
Any A or B to G, tpdQ
Propagation Delay to a Logical" 1" from
tpdl
Propagation Delay to a Logical "0" from
Any A or B to P, tpdQ
Propagation Delay to a Logical "1" from
Any A or B to P, tpdl
Propagation Delay to a Logical "O"from
r, tpdQ
-20
-18
Vec=55V
Vee == 525V
DM54181
DM74181-
Any A or B to
OV
-c;=----
Supply Current - (GND All
& Cn, Other Inputs HIGH)
G,
==
127
140
Bs
Any A or B to
V OUT
1-97
...
...
co
o::t
,....
electrical characteristics (cont.)
:!
PARAMETER
Q
.......
......
o::t
CO
CONDITIONS
TYP
MAX
UNITS
14
48
ns
14
34
ns
16
48
ns
Dlff Mode
26
48
ns
Vee = 5V
T A : 25°C
Dlff Mode
25
50
ns
Propagation Delay to a Logical "0" from
Vee'" 5V
Sum Mode
en to Cn + 4 •
TA= 2SQ C
INote 6)
14
19
ns
Sum Mode
9
18
ns
Sum Mode
13
18
ns
Sum Mode
12
19
ns
Sum Mode
16
19
ns
Sum Mode
13
19
ns
Sum Mode
17
25
ns
Sum Mode
12
19
ns
Sum Mode
15
32
ns
Sum Mode
14
42
ns
Propagation Delay to a Logical" 1" from
Vee
Any A or B to F,
TA
tpdl
Propagation Delay to a Logical "0" from
Any A or B to Any F,
Il)
tpdO
Propagation Delay to a Logical" 1" from
:!
Any
Q
A to B to Any F,
tpdl
Propagation Delay to a logical "1" from
Any A to B to A::oB, tpdQ
A or B to A=B,
tpdl
tpdO
Vee =: 5V
T A : 25°C
Logic Mode M
TA
Propagation Delay to a Logical "0" from
f,
Logic Mode M
INote 5)
:
25°C
Vee = SV
Cn+ 4 • tpdl
en to Any
:
25°C
Vee = 5V
TA = 2SoC
tpdQ
Propagation Delay to a Logical" 1" from
en to Any F, tpd1
TA
Propagation Delay to a Logical "0" from
Any A or B to <3, tpdO
TA
Vee == 5V
:
25°C
Vee = 5V
:
25°C
= 5V
Propagation Delay to a Logical "1" from
Any A or B to <3, tpdl
TA
Propagation Delay to a Logical "0" from
Any A or 8 to P, tpdO
TA
Propagation Delay to a Logical" 1" from
Any A or B to P, tpd1
T A :25°C
Propagation Delay to a Logical "0" from
Any A to B to Any F, tpdO
Vee
= 5V
TA
25°C
Propagation Delay to a Logical" 1" from
Any A or B to Any F, tpdl
Dlff Mode
Vee = 5V
T A :25°C
TA
Propagation Delay to a Logical "1" from
en to
5V
2SQC
=:
Vee = 5V
Propagation Delay to a Logical "0" from
Any
=:
MIN
Vee
:::
25°C
Vee = 5V
:
25°C
Vee'" 5V
:
Vee = 5V
TA
:
2SoC
=
4 5V
=:
4 5V
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electncal Characteristics" provides conditIOns for actual deVice operation.
Note 2: Unless otherWise specified minimax limits apply across the ~55°e to +125°e temperature range for the DM54181
and across the oOe to 700 e range for the DM74181. All tYPlcals are given for Vee"" 5.0V and TA = 25°e.
Note 3: Only one output at a time should be shorted.
Note 4: 0,11 Mode· S, = S2 = 4.5V, So = S3 = M = OV.
Note 5: LogiC Mode: S, = S2 = M = 4.5V, So = S3 = OV.
Note 6: Sum Mode: So = S3 = 4.5V, S, = S2 = M = OV.
truth table
TABLE OF ARITHMETIC OPERATIONS
fUNCTION
OUTPUT FUNCTION
SELECT
S3 S2 81
so
L
L
L
L
L
LOW LEVELS ACTIVE
F-Ammus1
HIGH LEVELS ACTIVE
f""A
L
L
H
F = AB minus 1
L
L
H
L
F '" AS minus 1
F = A+B
L
L
H
H
F = minus 1 12's complement)
F'" mmus 1 12's complement)
L
H
L
L
F '" A plus [A+Sl
F = A plus AS
L H L H
L H H L
L H H H
H
L
F = AB plus IA+SJ
F = A+B
F
0=
F '" A mmus B minus 1
F"'ABmmus1
L
L
F '" A plus [A+BJ
F = A plus AS
H
L
L
H
F = A plus B
F=AplusB
H
L
H
L
F = AS plus {A+SJ
F = (A+SJ plus AB
H
L
H
H
F = A+B
F=ABmmus1
H
H
L
L
F = A plus At
F= A plus At
H H L H
F=ABplusA
F'" {A+BJ plus A
H
F = AS plus A
F '" (A+Sl plus A
F==A
F=Ammus1
H
H
L
H H H H
Wlth mode control (M) and CnioW
tEach bit
1-98
[A+BJ plus AS
F = A minus Bmlnus 1
F'" A+S
IS
shifted to the next more Significant pOSition
c
3:
mode of operation
U'I
The OM54181/0M74181 has been designed to not
only incorporate all of the designer's requirements
for arithmetic operations, but also to provide 16
possible functions of two Boolean variables without the use of external circultry_ These logic functions are selected by use of the four function-select
inputs (So, S1, S2, S3) with the mode control
input (M) at a high level to disable the internal
carry. The 16 logic functions are detailed In the
function table and include exclUSive-OR, NAND,
AND, NOR, and OR functions.
Active-low data:
....JIo
...
.......
CO
No Input carry, Cn = 0
(HIGH logic level)
No output carry, Cn +4 = 0
(H IGH logic level)
c
3:
.....
...
...
Subtraction IS accomplished by 1's complement
addition where the l's complement of the subtrahend is generated internally. The resultant output is A-B-l which requires an end-around or
forced carry to prov ide A-B.
.JIo
CO
The DM54181/DM74181 can also be utilized as a
comparator. The A = B output IS internally de·
coded from the function outputs (Fa, F 1, 1'2, F 3)
so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a highlevel state to indicate equality (A = B). The device
should be m the subtract mode when performmg
thiS comparison. The A= B output is open-collector
so that It can be wire-AND connected to give a
comparison for more than four bits. The carry
output (C n +4 ) can also be used to supply relative
magnitude Information. Again, the ALU should
be placed m the subtract mode by plaCing the
control lines at LHHL.
The DM54181/DM74181 IS designed with a Dar·
lington output configuration (54H174H type) to
reduce the high-logic-level output Impedance and
thereby improve the turn-off propagation delay
time. All outputs are rated at a normalIZed fan·
out of ten at the low logic level and Increased to a
fan· out of 20 at the high logic level. The Increased
hlgh·loglc·level fan·out allows the sy;tem designer
more freedom In tying unused mputs to driven
mputs.
The DM54181/DM74181 will accommodate actlvehigh or active-low data If the mput carry and out·
put carry are remterpreted.
III
Active-high data: Cn +4 = 1 (HIGH logic level)
A~B
C n +4 = 0 (LOW logic level)
AB
C n +4 = 0 (HIGH logic level)
A:::;B
Active-high data: No Input carry, C n = 1
(H IGH logic level)
No output carry, Cn + 4 = 1
(HIGH logic level)
truth table (cont.)
TABLE OF LOGIC FUNCTIONS
FUNCTION
OUTPUT FUNCTION
SELECT
S3 52 81
so
NEGATIVE LOGIC
POSITIVE LOGIC
L
L
L
L
F=A
L
L
L
H
F=Aa
f=A+B
l
H
l
F '"' A+B
F
l
l H
H l
l
H
l
H
H
f=A
AS
F '" Logical 0
F=
F;S
l
eo
F = Logical 1
F '" A+B
AS
f=B
H H
F = Ae8
F '" AfIl8
H H H
F = A+B
F'" AS
l
l
F '" AS
F '" A+B
l
l
F '" Ae8
F = Ae8
L
H
F '" B
F '" B
H
l
H
F '" A+B
F '" AS
H
H
l
L
F '" Logical 0
F'" Logical 1
H H L H
F
=
AS
F'" A+B
H
F
=
AS
F = A+B
H
H
L
H H H H
F=A
With mode control (M) HIGH
For positIVe logiC logical 1 '"
logical 0 =
For negative logiC logical 1 =
logical 0 '"
F=A
Cn Irrelevant
HIGH Voltage
LOW Voltage
LOW Voltage
HIGH Voltage
1-99
....
co
....
,...-.:t
switching parameter measurement information
:i!
c
........
....
OIFF MODE TEST TABLE
co
....
FUNCTION INPUTS
-.:t
LD
PARAMETER
:i!
C
tpLH
tpHL
INPUT
UNDER
TEST
A
tPLH
tPHL
tpLH
tPHL
A
tPLH
tpHL
tpHL
II
tpLH
tPLH
tpHL
tPLH
tpHL
tPLH
tPHL
tPLH
tpHL
S1 '" 52 '" 4.5V.
OTHER INPUT
SAME BIT
APPLY
4.SV
so '" 83 = M = OV
OTHER DATA INPUTS
APPLY
GND
APPLY
4.5V
APPLY
GND
None
B
Remaining
Remaining
A
None
None
A
B. Cn
Remalnmg
Remamlng
S, Cn
II
None
A and B, C n
None
None
Aand B. Cn
B
None
None
None
A
None
A
None
B
A
None
Cn
None
None
UNDER
TEST
Any
F
Any
F
Remaining
A
Remaining
OUTPUT
Remalnmg
Remaining
AandB,C n
Remaining
A and S,
Cn
Remaining
G
G
A"'B
II
B, C n
Remaining
Remalnmg
B, C n
A""'B
None
Cn +4
II
All
Aand Ef
SUM MODE TEST TABLE
FUNCTION INPUTS SO:: 53 = 4.SV. 51'" 52 = M = OV
PARAMETER
INPUT
UNDER
TEST
tPLH
tPHL
II
OTHER INPUT
SAME 8fT
APPLY
4.SV
APPLY
B
None
tPLH
tPHL
B
A
tPLH
tPHL
A
B
GND
OTHER DATA INPUTS
APPLY
4.5V
Remaining
APPLY
GND
OUTPUT
UNDER
TEST
F
Cn
Any
None
Remaining
A and B
Cn
Any F
None
None
Remaining
A and B, C n
p
Remaining
Aand B,C n
p
A andS
tpLH
tpHL
B
II
None
None
tPLH
tPHL
A
None
B
Remaining
tPLH
tPHL
B
None
A
tPLH
tpHL
Cn
None
None
B
Remaining
Remaining
A,C n
G
G
B
Remaining
A, Cn
All
All
Any F
II
B
or Cn +4
LOGIC MODE TEST TABLE
FUNCTION INPUTS. S1 = S2 = M "" 4 5V, SO '" S3 '" OV
INPUT
PARAMETER
UNDER
TEST
tpLH
tpHL
tPLH
tPHL
1-100
A
B
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
APPLY
APPLY
APPLY
APPLY
45V
GND
4.5V
GND
None
B
None
A and B, C n
None
A
None
RemalOlng
Remaining
AandB,C n
OUTPUT
UNDER
TEST
Any
F
Any F
c
s:
logic diagram
U1
....
co
....
........
~
C
s:.....
....
~
co
....
0-------,
j3)
SJ
~4)
S20---------'
(6)
(5)
So ....
SI
__
~::==i:Ul _::I~
GorY
(m
>,o-+--i-H++1
'.,
(16)
PorX
US)
F3
(13)
I,
O::+--H+t1r1
)-Ht---,,,oO, "
.".
)-~~------------111'~~----~(10~' "
) - -....- - - 0 ••
'91
•• 0 - - - - - - -....-1
' .m 0 - - - - - - - - - - - - - - - - '
Vcc =PIN24
GND·PINlZ
1-101
N
...co
Series 54/74
~
~
Q
.......
.-...
DM54182/DM74182 (SN54182/SN74182)
look-ahead carry generator
~
general description
N
co
1ft
Q
The DM54182/DM74182 (SN54182/SN74182) is
a high-speed, look-ahead carry generator capable of
anticipating a carry across four binary adders or
group of adders_ It is cascadable to perform full
look-ahead across n-bit adders, with only 13 ns
delay for each level of look-ahead. Carry, generatecarry, and propagate-carry functions are provided
as enumerated in the pin designation table.
propagate (1)) and carry generate (G) are in negated
form; therefore, the carry (input, outputs, generate, and propagate) functions of the look-ahead circuit are implemented in the compatible forms. Reinterpretations of carry functions at the DM54181/
DM74181 are also applicable and compatible with
the look-ahead package. Logic equations are:
Cn+x
Cn+y
Cn+z
Go + PoCn
G, + P,G o + P,PoC n
G2 + P2 G, + P2 P,GO + P2 P,POCn
G
G 3 + P3G2 + P 3 P2 G, + P3 P 2P,G O
P=~
High speed arithmetic operations can be performed
for up to N-bit words when the DM54181/
DM74181 is used in conjunction with the
DM54182/DM74182.
For example, the typical addition time for the
DM54181/DM74181 is 24 ns for four bits. When
expanding to 16-bit addition with the DM54182/
DM74182, only 13 ns further delay is added so
that the total addition time is 37 ns, or 2.3 ns
per bit. One DM54182/DM74182 is needed for
every 16 bits (four DM54181/DM74181 circuits).
Carry inputs and outputs of the DM54181/
DM74181 are in their true form and the carry
Inputs of the DM54182/DM74182 are diodeclamped to minimize transmission-line effects, and
Darlington outputs are employed to improve turnoff times and reduce propagation delay times.
Typically, the average carry time is 13 ns, and
power dissipation is typically 180 mW or 11 mW
per gate.
logic diagram
connection diagram and table
Dual-In-Lina Pack","
OUTPUTS
INPUTS
••
1IM1it11Z/DM14112
c..
••
TOP VIEW
.'~=tt::j:O
',0-;-'oo"oo-+--+---I-r-..
.00,,----.....
-1-1.../
c, <>::---c)O------I
1-102
DM64'82/0M74182
PIN DESIGNATIONS
DESIGNATION
PIN NOS
FUNCTION
Go.G, ,02 .53
3,1,14.6
""'~LOW
Carry Generlte Inputli
PO.P'.P2.Pa
4.2,16,6
C.
"
c...~.C~+y
c".,
Ac1,veI..OW
..
DESIGNATION PIN NOS
i'
~lOW
Carry Propeg8te Output
CarrV PrDpI9a1alnpuu
12,11,9
FUNCTION
Active LOW
CIIrryGilnerateOutpU't
Carry Input
V~
ClrryOutpUtl
GND
"
SupplyVoItllflB
GROUND
C
absolute maximum ratings
3:
(Note 1)
CJI
...
~
7V
5.5V
55V
_55°C to 125G
e
oOe to 70 Ge
e
-65°C to 150G
300°C
Su ppl y Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM54182
DM74182
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
00
N
......
C
3:
.....
...
~
electrical characteristics
00
N
(Note 2)
PARAMETER
CONDITIONS
MIN
TV.
MAX
UNITS
Logical "1 ' Input Voltage
DMS4182
DM74182
Logical "0" Input Voltage
DM54182
DM7~
Logical "1" Output Voltage
DM54182
DM74182
V cc =45V
Vee 475V
10
Logical "0" Output Voltage
DMS4182
DM74182
V cc =4SV
Vee 475V
10= l6mA
Logical "1" Input Current
(C n Input)
DM54182
DM74182
Vcc=55V
Vee 525V
V 1N =24V
80
MA
Logical "1" 'nput Current
(P3 Input)
DMS4182 ~_=55~
DM74182 Vee'" 5 25V
VIN = 24V
120
MA
Logical "1" Input Current
(P2 Input)
DM54182
DM74182
Vee'" 55V
V cc - 525V
VIN = 24V
160
MA
Logical "1" Input Current
(Po, 15 1 , or G 3 Input)
DM54182
DM74182
Vce=55V
Vee - 525V
V
,N "'" 2 4V
200
MA
Logical "1" Input Current
(Go or G 2 Input)
DM54182
OM74182
Vee= 55V
Vee - 525V
V ,N = 24V
360
MA
Logical "1" Input Current
(G 1 Input)
OM54182 ~~5V
OM 74182
Vee" 525V
Y'N = 24V
400
MA
Logical "1" I nput Current
(Any Input)
DM54182
OM74182
Vee'" 55V
V ee -525V
V ,N =55V
1
mA
Logical "0" I nput Current
(C n Input)
OM54182
OM74182
Vee=55V
Vee- 52q,V
-32
mA
Logical "0" Input Current
lP3 Input)
DM54182
OM74182
Vee=55V
Vee 525V
-48
mA
Logical "0" Input Current
(152 Input)
DM54182
DM74182
V ee ""'55V
Vee 525V
-64
mA
Logical "0" Input Current
DM54182
DM74182
Vee=55V
Vee - 525V
-8
mA
(Go or (;2 Inputs)
DM54182
DM74182
Vee=55V
V ee -525V
-144
mA
Logical "0" Input Current
((;1 Input)
DMS4182
DM74182
V ee ""'55V
Vee 525V
-16
mA
Output Short C'fCUlt Current
(Note 3)
g~~:~~
Vee=55V
Vee = 5 25V
-100
rnA
Supply Current - All
Outputs HIGH
DM54182
DM74182
Vee = 5 5V
Vee 525V
27
Supply Current Ali
Outputs LOW
DM54182
DM74182
Vee=55V
Vee 525V
45
45
65
72
mA
(Po, Pl or G 3 Input)
Logical "0" Input Current
Vee = 4 5V
V cc -475V
V
20
~-::;~v
08
V
=
-800.uA
24
V
V
0.4
V
,N = a 4V
-40
mA
Propagation Delay to a Logical "0" from
Carry Input to Carry Output, tpoo
Vee=50V
TA = 25°C
C L = 50 pF, RL = 400n
14
22
ns
Propagation Delay to a Logical "0" from
Carry Propagate Inputs (P 3 ) to Carry
Generate (G) & Carry Propagate (P)
Outputs, tpdQ
Vee= 50V
TA == 25°C
C L "'" 50 pF, AL = 400n
11
22
os
Propagation Delay to a Logical "1" from
Carry I nput to Carry Output~, tpd1
Vec=50V
TA = 25°C
C L = 50 pF, AL = 400[2
11
17
ns
C L = 50 pF, AL = 400n
10
17
os
Propagation Delay to a Logical "1" from
Carry Propagate Inputs (Ps) to Carry
Generate (G) & (p) Propagate, tpdl
Vee=50V
TA == 25°C
0
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise speCified minImax limits apply across the ~55°C to +125° C temperature range for the DM54182
and across the oOe to +70°C range for the DM74182. All typicals are given for VCC "" 5 OV and TA::: 25°C.
Note 3: Only one output at a time should be shorted.
1·103
illS
Series 54/74
DM54184/DM74184(SN54184/SN74184)
BCD-to-binary converter
DM54185A/DM74185A(SN54185A/SN74185A)
binary-to-BCD converter
general description
When the enable input is taken to the logic "I"
level all outputs go high. In addition, the unused
states of the DM54184/DM74184 and the unused
outputs of the DM541B5A/DM74185A are pro·
grammed to be logical "I'''s.
Both of these converters are mask optIOns of the
DM5488/DM74BB 256·bit Read·Only Memories.
In normal operation the least significant bit by·
passes the converter since in all cases the binary
and BCD LSB's are the same. Thus each device
performs a 6·bit conversion.
connection diagram
Dual·1 n·Line and Flat Package
81I1ARVSElECT
'r..1.
i.. in
il,i
G
il1 i" "•
112
1 , I I .I I
~~z
VI
\
OUT1'UT
ENAILE
0
YJ
I
J:
1
l
3
y3
Y4
A+
c
" " "
I I I I
,r v~f J/
Jr,!i
Gl:
OUTPUTS
TOP VIEW
truth tables
DM54185A/DM74185A
Binary·to·BCD Convarts.
BINARV
WOROS
DM541B4/DM74184
BCD-to-Binary Converter
OUTPUTS
(See Note 81
INPUTS
(See Note AI
BCD
INORDS
BINARY SELECT
ENABLE
E
D
C
B
A
G
V5
V4
V3
V2
V,
0·1
2·3
4·5
6·7
8·9
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
L
10-11
12-13
14-15
16-17
18-19
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
H
H
H
H
L
H
H
H
H
H
L
L
L
H
L
H
H
L
L
L
L
L
H
L
L
H
L
H
L
X
X
H
20-21
22-23
24-25
28-29
H
H
H
30-31
32·33
H
24-27
H
34-35
36-37
38·39
H
H
H
H
H
H
L
L
L
L
H
ANV
X
X
X
H
L
L
L
H
H
H
L
L
H
H
L
H
L
L
H
L
L
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
L
H
H
H = high level. L = low level, X = Irrelevant
Note A Input conditions other than those shown produce high at
outputs Y 1 through V5
Note B Outputs ve, V 7, and VB are not used for BCO-to-bmary
converSion
1·104
INPUTS
OUTPUTS
BINARV SELECT
ENABLE
E
D
C
B
A
G
VB
V7
va
V5
V4
V3
Y2
V,
0·1
2·3
4·5
6-7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
L
H
L
H
H
H
8·9
10-11
12-13
14-15
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
L
H
L
L
L
16·17
18-19
20-21
22-23
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
24-25
:)G.31
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
32·33
H
34-35
36·37
38·39
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
H
H
L
L
L
L
26-27
28·29
40-41
42--43
44-45
46-47
H
H
H
H
H
H
48-4.
60-51
H
H
52·63
54-56
H
H
H
H
H
56·57
H
H
H
H
H
62-63
H
H
ALL
X
68-69
60-61
H
H
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
L
L
L
H
L
L
H
L
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
L
H
L
L
L
H
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
L
H
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
H
L
H
L
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
H
H
H
L
L
H
L
L
L
L
L
L
L
H
L
H
L
H
L
L
H
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
L
00
absolute maximum ratingS(Note
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
1)
7V
5.5V
5.5V
_65°C to +150 o e
300°C
electrical characteristics
PARAMETER
3:3:
operating conditions
Supply Voltage (Vee)
DM54184, DM54185A
DM74184, DM74185A
tntn
MIN
MAX
UNITS
4.5
4.75
55
5.25
V
V
-55
0
+125
70
°e
°e
CONDITIONS
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Current
Vee = Max, Vo = 5.5V
Logical "0" Output Voltage
Vee = Min, 10 = 12 mA
Logical "1" Input Current
Vee = Max, V, = 2AV
MIN
TYP
MAX
2.0
0.8
100
0.4
V
JlA
V
40
JlA
1
mA
Vee = Max, V, = OAV
-1.6
mA
Supply Current
Vee = Max
80
mA
Input Clamp Voltage
Vee = Min, I, = - 12 mA
Propagation Delay to a Logical "0" from
Vee = 5.0V
T A = 25°C
C L = 15 pF
32
50
ns
Vee = 5.0V
T A = 25°C
C L = 15 pF
34
50
ns
Vee = 5.0V
T A = 25°C
C L =15pF
28
50
ns
Vee = 5.0V
T A = 25°C
C L =15pF
27
50
ns
Enable to Output, tpdO
Propagation Delay to a Logical" 1" from
Address to Output, tpdl
Propagation Delay to a Logical "1" from
Enable to Output, tpdl
50
-1.5
".JIo
.JIo'"
... 00
OO.Jlo
tn'
l>
V
Vee = Max, V, = 55V
Propagation Delay to a Logical "0" from
03:
3:"
UNITS
Logical "0" Input Current
Address to Output, tpdO
tn.Jlo
(Note 2)
Logical "1" Input Voltage
0000
l> .......
....... 0
Temperature (T A)
DM54184, DM54185A
DM74184, DM74185A
.JIo.Jlo
......
o
V
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electncal Characteristics" provides conditions for actual deVice operation
Note 2: Unless otherwise specIfied min/max limits apply across the _55°C to +125°C temperature range for the DM54184,
DM54185A and across the oOe to 70°C range for the DM74184, DM74185A All tYPlcals are given for Vee = 5.0V and T A =
25°C.
1·105
Series 54/74
DM54187/DM74187 (SN54187/SN74187)
1024-bit read only memory
general description
The DM54187/DM74187 is a custom-programmed
read-only memory organized as 256 four-bit words_
Selection of the proper word is accomplished
through the eight select inputs_ Two overriding
memory enable inputs are provided; and when one
IS taken to the logical "1" state, it will cause all
four outputs to go to the logical "I" state_
• 20 ns typical delay from enable to output
• Open collector outputs for expansion
applications
• Microprogramming
• Code conversions
features
• Look-up tables
• 36 ns typical delay from address to output
• Use for any memory where content is fixed
logic diagram
'"
'"
'51
MEMORY
rOA
ENABlEllia
il3)
(14)
connection diagram
Dual-In-Line Package
1-106
absolute maximum ratings
c
3:
(Note 1)
C1I
...
.J:Io
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM54187
DM74187
Storage Temperature Range
Lead Temperature (Soldering, 10 see)
electrical characteristics
PARAMETER
CO
7V
.....
c
3:
~
CO
.....
5.5V
5.5V
.......
- 55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
...
(Note 2)
CONDITIONS
MAX
TYP
MAX
UNITS
Logical "I" Input Voltage
DM54187 Vee = 4.5V
DM74187 Vee = 4.75V
Logical "0" Input Voltage
DM54187 Vee = 4.5V
DM74187 Vee - 4.75V
Logical "I" Output Current
DM54187 Vee = 5.5V
DM74187 Vee = 5.25V
Va = 5.5V
Logical "0" Output Voltage
DM54187 Vee = 4.5V
DM74187 Vee = 4.75V
la=16mA
Logical "1" Input Current
DM54187 Vee = 5.5V
DM74187 Vee = 5.25V
V IN = 2.4V
40
J1A
DM54187 Vee = 5.5V
DM74187 Vee - 5.25V
VIN = 5.5V
1
mA
DM54187 Vee = 5.5V
DM74187 Vee = 5.25V
V IN = O.4V
-1.0
mA
Supply Current
(each device)
DM54187 Vee = 5.5V
DM74187 Vee - 5.25V
All Inputs at GND.
Input Clamp Voltage
DM54187 Vee = 4.5V
DM74187 Vee = 4.75V
liN =-12 mA
Logical
"a"
I nput Current
V
2.0
0.8
40
0.4
75
110
V
/lA
II
V
mA
-1.5
V
Propagation Delay to a Logical "0" from Vee = 5.0V
Enable to Output, tpdO
TA = 25°C
CL = 30 pF
20
30
ns
Propagation Delay to a Logical "0" from Vee = 5.0V
TA = 25°C
Address to Output, tpdO
CL = 30 pF
37
60
ns
Propagation Delay to a Logical "I" from Vee = 5.0V
Enable to Output, tpd 1
TA = 25°C
CL = 30 pF
20
30
ns
Propagation Delay to a Logical "I" from Vee = 5.0V
T A =25°C
Address to Output, tpd 1
CL = 30 pF
36
60
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice
cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Charactenstics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -55°C to + 12SoC temperature
range for the DM54187 and across the oOe to 700 e range for the DM74187. All typical. are given
for Vee = 5.0V and T A = 25°e.
1-107
.....
.,..
00
ordering instructions
~
.....
~
Q
.......
.....
Programming instructions for the OM54187 or
OM74187 are solicited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAO) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.
.,..
00
~
LO
~
Q
Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched_ Cards should be
punched according to the data card format shown.
10-13
14
15-18
19
20-23
24
25-28
29
30-33
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.
40-43
44
45-48
49
50-51
data card format
1- 3
4
5- 7
8- 9
1-108
52
53-55
Column
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
Punch a "-" (Minus sign)
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H", "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
34, Blank
35-38
39
supplementary ordering data
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H ~ highlevel output, L ~ low-level output, X ~
output irrelevant.
56
57-58
59
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Blank
Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.
60-61
Punch "OM"
62-66
Punch the National Semiconductor part
number 54187 or 74187.
Blank
67-70
Blank
Series 54/74
DM54190/DM74190(SN54190/SN74190)
up/down decade counter
general description
The DM54190/DM74190 is a four-bit up/down
decade counter capable of being preset to any
number from 0 through 9_ A single Clock line is
provided and depending upon the logic level on the
down/up control, proper direction of counting is
achieved_ The flip flops are triggered on the
positive-going transition of the clock providing
that the Enable input is low_ A logical 1 at the
Enable input inhibits counting_ Level changes at
the Enable input should be made only when the
Clock input is high_ Information can be asynchronously entered by putting the desired logic
levels on the Data inputs and then taking the Load
input low_ This may be done independent of the
state of the clock_
Two outputs have been made available to perform
the cascading function: ripple clock and maximum/
minimum count. The latter output produces a
high-level output pulse with a duration approximately equal to one complete cycle of the clock
when the counter overflows or underflows_ The
ripple clock output produces a low-level output
pulse equal in width to the low-level portion of
the clock input when an overflow or underflow
condition exists_ The counters can be easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel
clocking is used, or to the clock input if parallel
enabling is used_ The maximum/minimum count
output can be used to accomplish look-ahead for
high-speed operation_
logic and connection diagrams
Dual-I n~line and Flat Package
OA;:PlITSR~
A
RIPPLE
CLOCk
)---+-+-....---"""';~~/U~N
CLOCK CLOCK MIN
r:" " "
n
LOAD
DATA
C
"
'"
"
~
.
}
.
, ,
,
DATA
DATA
0
DB
OA
B
~
~
INPUT
OUTPUTS
INPUTS
ASYNCHRONOUS INPUTS
, ,
,
UI/A8lEOOWNI
Or
I'
Do
GND
______
OUTPUTS
lOWll\iPUTTO lOAOSETSO A
0B-BUe
CANDDo
A
0
operating modes
DOWN/UP
X
X
L
H
ENABLE
LOAD
MOOE
X
H
L
L
L
H
H
H
Parallel Load
No Change
Count Up
Count Down
H'" high level, L = low leve!, X" Irrelevant
Pm(16!='lcc Pm(8)"GNU
1-109
D
o
...,...v
en
absolute maximum ratingS(Note
c
~
Supply Voltage
Input Voltage
Output Voltage
o
Storage Temperature Range
Lead Temperature (Soldermg. 10 sec)
operating conditions
1)
MIN
........
...v
en
-65°e to +~~g:g
electrical characteristics (Note
It)
~
PARAMETER
c
Supply Voltage (Vee I
DM54190
DM74190
Temperature (TAl
DM54190
DM74190
7V
5.5V
5.5V
Vec '" Mm
Logical "0" Input Voltage
Vee'" Mm
Logical "1" Output Voltage
Vee'" Min
V IH '" 2V
Logical "0" Output Voltage
Vee'" Mm
V IH ~ 2V
Logical "1" Input GUrlent at
Maximum Input Voltage
Vee'" Max
o
5.5
5.25
+125
70
MIN
TYP
MAX
UNITS
v
08
lOUT'"
V IL
-800.uA
",oav
24
V
lOUT'" 16 rnA
V 1L
V
04
",oav
V
rnA
Logical "1" Input Current at Any
Input Except Enable
Vee'" Max
VIN '" 2 4V
40
Logical "1" Input Current at Enable
Vee'" Max
VIN '" 2 4V
120
Logical "0" Input Current at Any
Input Except Enable
Vee'" Max
-16
rnA
Vee'" Max
-48
rnA
Logical "0" Input Current at Enable
Output Short CircUit Current
(Note 3)
Vec '" Max
V OUT '" OV
-20
-18
-65
rnA
105
rnA
Supply Current (each device)
Vee'" Max
Input Clamp Voltage
Vee = Mm
Propagation Delay to a Logical "0" from
Vee "'50V
T A =25°C
31
46
Vee =50V
T A'" 25°C
25
38
Vee=50V
T A "'25 C
16
24
22
36
21
52
Load to Outputs,
tpdO
Propagation Delay to a Logical "0" from
Data to Output, tpdO
Propagation Delay to a Logical "0" from
Clock to Ripple Clock, tpdO
Propagation Delay to a Logical "0" from
66
liN
-15
=-12mA
Q
Clock to Outputs, tpdO
Vee ""50V
T A =25°C
Propagation Delay to a Logical "0" from
Clock to MaxlMm, tpdO
Vee'" 50V
TA '" 25 Q C
Propagation Delay to a Logical "0" from
Down/Up to Ripple Clock, tpdO
Vee;: 50V
C L =- 50 pF, RL '" 400ft
25
38
Vee "'50V
TA '" 25°C
13
20
Vee "'50V
TA '" 25°C
25
37
Data to Outputs, tpdl
Vee'" 50V
TA == 25°C
14
21
Propagation Delay to a Logical "1" from
Clock to Ripple Clock, tpdl
Vee=50V
TA
25°C
16
24
Propagation Delay to a Logical "1" from
Vee "'50V
T A =25°C
19
24
Clock to Max/Mm, tpdl
Vee=50V
T A =25°C
36
54
Propagation Delay to a Lgolcal "1" from
Down/Up to Ripple Clock, tpd1
Vee "'50V
TA '" 25"C
22
45
Propagation Delay to a Logical "1" from
Vee'" 50V
TA '" 25"C
16
24
Propagation Delay to a Logical "0" from
Down/Up to MaxIMin, tpdO
Propagation Delay to a Logical "1" from
Load to Outputs, tpdl
Propagation Delay to a Logical "1" from
Clock to Outputs, tpdl
Propagation Delay to a Logical "1" from
Down/Up to Max/Min, tpd1
Maximum Clock Frequency f MAX
TA
'"
25 Q C
Vee "'50V
TA '" 25 Q C
20
o
Width of Input Pulse tWlcLoeKI
25
Width of Load Input Pulse tWILOAOl
35
Data Setup Time, tSETUP
20
o
Note 1 "Absolute Ma:O:lmum Ratings" are those values beyond which the safety of the device cannot be guaranteed E:o:cept
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electncal CharactenstlCS" prOVides conditions for actual device operation
Note 2 Unless otherWise speCified mm/ma:o: limits apply across the _5S cC to +125°e temperature range for the DM54190
and across the oOe to 700 e range for the DM74190 All tYPlcals are gIven for Vee ~ 50V and T A = 25°e
Note 3 Only one output at a tm1e should be shorted
V
=0
Input Clock Frequency fCLoeK
Data Hold Time, tHOLD
1-110
-55
UNITS
2)
CONDITIONS
Logical "1" Input Voltage
4.5
4.75
MAX
MHz
25
20
MHz
illS
Series 54/74
DM54191/DM74191(SN54191/SN74191)
up/down binary counter
general description
The DM541911DM74191 is an up/down binary
counter capable of being preset to any number
from 0 through 15. A single Clock line is pro·
vided and depending upon the logic level on the
down/up control, proper direction of counting is
achieved. The flip flops are triggered on the
positive·going transition of the clock providing
that the Enable input is low. A logical 1 at the
Enable input inhibits counting. Level changes at
the Enable input should be made only when the
Clock input is high. Information can be asyn·
chronously entered by putting the desired logic
levels on the Data inputs and then taking the Load
input low. This may be done independent of the
state of the clock.
Two outputs have been made available to perform
the cascading function: ripple clock and maximum/
minimum count. The latter output produces a
high·level output pulse with a duration approxi·
mately equal to one complete cycle of the clock
when the counter overflows or underflows. The
ripple clock output produces a low·level output
pulse equal in width to the low·level portion of
the clock input when an overflow or underflow
condition exists. The counters can be easily cas·
caded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel
clocking is used, or to the clock input if parallel
enabling is used. The maximum/minimum count
output can be used to accomplish look·ahead for
high·speed operation.
logic and connection diagrams
Dual-I n-Line and Flat Package
IIIIPUT5
OUTPUTS
~~
v"~
J;
RIPPLE
CLOCK
DATA
A
RIPPLE
Cl[lCK CLOCK
MAX i
MIN
LOAD
" " " "
)---+-+---4---= ~~::U~'N
DATA
DATA
C
0
rl
,
DATA
,
" "
r
.
, ,
0,
O.
~N
~u
,
,
;
DOWN
0,
01:
O.
~
OUTPUTS
ASVNCHRONOUSINPUTS
LfrWINPUTTOlOAOSETSD.
G,
Ba,
C 11111000
A
0
operating modes
DOWN/UP
X
X
L
H
H
=
ENABLE
LOAD
MODE
X
H
L
L
L
H
H
H
Parallel Load
No Change
Count Up
Count Down
high level, L" low level, X" Irrelevant
P,n (161' Vee P,nI81' GND
1·111
D
absolute maximum ratings (Note
1)
operating conditions
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
7V
5.5V
5.5V
-65'e to +150'e
300'e
Supply Voltage (Veel
DM54191
DM74191
Temperature (TAl
DM54191
DM74191
4.5
4.75
-55
0
MAX
5.5
5.25
+125
70
UNITS
V
V
'e
'e
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee ·= Mill
Logical "0" Input Voltage
Vee =- Mill
logical "1" Output Voltage
LOglCdl "0" Output Voltage
Logical "1" Input Current at
Vee =- Mill
V 1H
""
2V
TYP
lOUT eo -800 /JA
V 1L =08V
Vee'" 2V
V 1H '" 2V
V 1L "'08V
24
VIN =- 5 5V
Vee'" Max
Logical "1" Input Current at Enable
Vee =- Max
Input Except Enable
Vee'" Max
VIN =Q4V
Logical "0" Input Current at Enable
Vee'" Max
V 1N "'04V
V
V
lOUT"" 16 rnA
Vee'" Max
UNITS
V
08
04
V
1
mA
VIN =24V
40
"A
VIN '" 2 4V
120
Logical "0" Input Current at Any
Output Short Circuit Current
(Note 3)
Vee'" Max
Supply Current (each device)
Vee'" Max
Input Clamp Voltage
Vee'" Mm
Propagation Delay to a Logical "0" from
Load to Outputs, tpdQ
Vee'" 50V
T A'" 25°C
C L '" 50 pF. RL "" 400n
PropagatIOn Delay to a Logical "0" from
Data to Output. tpdO
Vee "'50V
TA = 25°C
Propagation Oelay to a Logical "0" from
Clock to Ripple Clock. tpdQ
V OUT
'"
OV
-20
-18
"A
-16
mA
-48
mA
-65
mA
105
mA
-15
V
31
46
n,
CL '" 50 pF, RL '" 400n'
25
38
n,
Vee=50V
T A =25°C
CL '" 50 pF, RL '" 400ft
16
24
n,
Propagation Delay to a Logical "0" from
Clock to Outputs, tpdQ
Vec "'50V
TA=25 D C
CL == 50 pF, RL '" 400.0
22
36
n,
Propagation Delay to a Logical "0" from
Clock to Max/Mm, tpdQ
Vee'" S OV
TA == 25 D C
C L =SOpF, RL '" 400n
21
52
n,
PropagatIOn Delay to a Logical "0" from
Down/Up to Ripple Clock, tpdO
Vcc=SOV
TA ==2SoC
C L ==50pF, RL '" 400n
25
38
n,
Propagation Delay to a Logical "0" from
Down/Up to MaxlMm, tpdO
Vee = 50V
TA '" 2SoC
CL '" 50 pF, RL '" 400n
13
20
n,
Propagation Delay to a Logical "1" from
Load to Outputs, tpdl
Vee ",SOV
TA =2SoC
CL '" 50 pF, RL '" 400n
25
37
n,
Propagation Delay to a Logical ''1'' from
Data to Outputs, tpdl
Vee -= 50V
T A '" 25°C
CL '" 50 pF, RL '" 400n
14
21
n,
PropaglltlOn Delay to a Logical "1" from
Clock to Ripple Clock, tpdl
Vee'" SOV
T A '" 2SoC
CL '" SO pF. RL '" 400.0
16
24
n,
Propagation Delay to a Logical "1" from
Clock to Outputs. tpdl
Vcc"'SOV
T A '" 2Soc
CL '" 50 pF, RL '" 400n
19
24
n,
Propagation Delay to a Logical ''1'' from
Clock to Max/Mm, tpdl
Vce "'50V
T A =2S D C
CL '" SO pF, AL =400n
36
54
n,
Propagation Delay to a Logical "1" from
DownlUp to Ripple Clock, tpdl
Vee "'50V
T A '" 25°C
C L '" 50 pF, RL '" 400n
22
45
n,
Propagation Delay to a Logical "1" from
DownlUp to MaxiMin, tpdl
Vcc==SOV
TA '" 25°C
CL '" 50 pF, RL '" 400n
16
24
n,
MaXimum Clock Frequency f MAX
Vee"" SOV
T A '" 25 D C
CL '" 50 pF. AL '" 400n
20
MH,
Input Clock Frequency fCLoeK
liN =-12mA
20
0
Width of Input Pulse tW(CLOeK)
25
Width of Load Input Pulse tWILOADI
35
Data Setup Time, tSETUP
20
Data Hold Time, t HoLD
0
Note 1. "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
01 "Electrical Characteristics" prOVides conditions for actual deVice operation
Not. 2 Unless otherwise speCified minImax limits apply across the -S5Qe to +12SQ e temperature range for the OMS4191
and across the OQ e to 70Qe range for the DM74191 All typical, afe gIVen for Vee = 50V and TA = 2SQe
Note 3- Only one output at a time should be shorted
1-112
MAX
2
Logical" 1" Input Current at Any
Input Except Enable
Ma)llmum Input Voltage
MIN
MH,
25
n'
n,
n,
"'
Series 54/74
DM54194/DM74194(SN54194/SN74194)
4-bit bidirectional universal shift registers
general description
The DM54194/DM74194 are bidirectional shift
registers designed to incorporate virtually all of
the features a system designer may want in a shift
register. The circuit contains 46 equivalent gates
and features parallel inputs, parallel outputs, rightshift and left-shift serial inputs, operating mode
control inputs, and a direct overriding clear line.
The register has four distinct modes of operation,
namely:
S, is low. Serial data for this mode is entered at
the shift-left serial input.
Clocking of the flip·flop is inhibited when both
mode control inputs are low. The mode controls
should be changed only while the clock input is
high.
features
Parallel (Broadside) Load
Shift Right (In the direction Q A toward QD)
Shift Left (I n the direction Q D toward QA)
Inhibit Clock (Do nothing)
• TYPical power dissipation
195 mW
• Typical clock frequency
Synchronous parallel loading is accomplished by
applying the four bits of data and taking both
mode control inputs, So and S" high. The data
is loaded into the associated flip-flop and appears
at the outputs after the positive transition of the
clock input. During loading, serial data flow is
inhibited.
36 MHz (max)
• Parallel inputs and outputs
•
Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
• Positive edge-triggered clocking
Shift right is accomplished synchronously with the
rising edge of the clock pulse when So is high and
• Direct overriding clear
block diagram
SHIfT
SHIFT
LEFT
PARALLEL INPUTS
RIGHT
SERIAL
o
INPUT
121
'31
'51
'41
(15)
Q.
..
(14)
SERIAL
INPUT
'"
lUI
Dc
lIZ
Go
PARALLEL OUTPUTS
1·113
o
-=t
en
.-=t
,....
absolute maximum ratings
operating conditions
(Note 1)
~
C
........
-=t
en
.-=t
It)
~
C
7.0V
Supply Voltage. Vee (Note 4)
Input Voltage
5.5V
5.5V
Output Voltage
-j)5°e to +1500 e
Storage Temperature Range
Lead Temperature (Soldering. 10 seconds)
300°C
electrical characteristics
Supply Voltage (Vee)
DM54194
DM74194
Temperature (TA)
DM54194
DM74194
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
°e
°e
(Note 2)
PARAMETER
CONDITIONS
High Level Input Voltage (V ,H )
MIN
TYP
MAX
Low Level Input Voltage (V'L)
= Min.
UNITS
V
2.0
= -12 mA
O.B
V
-1.5
V
Input Clamp Voltage (V,)
Vee
High Level Output Voltage (V OH)
Vee = Min. V ,H = 2.0V.
V ,L = O.BV. 10H = -BOOJ1A
Low Level Output Voltage (Voe!
Vec = Min. V ,H
V ,L = O.BV. 10L
Input Current at Maximum Input
Voltage (1,1
Vcc
= Max. V, = 5.5V
High Level I nput Current (I, H )
Vee
= Max.
V,
= 2.4V
40
J1A
Low Level Input Current (I,L)
Vee
= Max.
V,
= O.4V
-1.6
mA
I,
2.4
= 2.0V.
= 16 mA
V
3.4
0.2
High Level Output Current (l oH )
V
1.0
mA
-BOO
J1A
16
mA
25
MHz
,
Low Level Output Current (lOL)
0.4
Clock Frequency (fCLOCK)
0
Width of Clock or Clear Pulse (tw )
20
ns
Setup Time (tSETUP )
Mode Control
Serial and Parallel Data
Clear I nactlve State
30
20
25
ns
ns
ns
Hold Time at Any Input (tHO LD )
0
ns
Short Clfcuit Output Current (los)
(Note 3)
DM54194
DM74194
Supply Current (Ieel
= Max
= Max
Vee = Max (Note
-20
-IB
Vee
Vcc
39
5)
Maximum Clock Frequency (f MAX )
CL = 50 pF. RL = 40011
(AC Test ClfCUlt)
Propagation Delay Time. High to Low
Level Output From Clear (tPHe!
CL = 50 pF. RL = 40011
(AC Test ClfCUlt)
Propagation Delay Time. Low to High
Level Output From Clock (tpLH)
CL = 50 pF. RL = 40011
(AC Test ClfCUlt)
Propagation Delay Time. High to Low
Level Output From Clock (tPHe!
CL = 50 pF. RL = 40011
(AC Test CirCuit)
-57
-57
25
63
mA
mA
mA
MHz
36
19
30
ns
7.0
14
22
ns
7.0
14
26
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature range for DM54194
and acros5th. 0° e to +70° C range for the DM74194. All typicals are given for V ce
= 5.0V and T A = 25° C.
Note 3: Note more than one output should be shorted at a time.
Note 4: Voltage values are with respect to network ground terminal.
Note 5: With all outputs open, Inputs A through 0 grounded, and 4.5V applied to SO, S1. clear, and the serial Inputs, ICC is
tested with a momentary GND. then 4.5V applied to clock.
1·114
connection diagram and table
Dual-In-Line Package
CLEAR
TD,VIEW
., ..
~
CLEAR
L
X
X
INPUTS
CLOCK
X
H
X
X
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
L
t
t
t
t
t
H
L
L
X
OUTPUTS
PARALLEL
SERIAL
lEFT
RIGHT
A
B
C
D
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
b
X
X
X
X
d
X
X
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
,
c
°A
""
Oe
L
L
L
,
0"
OCO
C
aDO
H
a ••
a ••
L
Oe.
Oe.
0..
0..
a ••
OC.
OC.
aD.
aD.
H
OAO
0.0
0"
aDO
L
0. 0
b
"".
0"
d
D
L
H = hi'" level hte&etv state!
L ~ low level (steady state)
X " .rrelevant lanv Input, including tran51110ns)
t - transilion from low to high level
e, b, c, d" the level of steady 51ale Input at inputs A, B, C, or 0, respeCtively
GAO. Oeo. Oeo. aDO 0: the level of 0A. OS. Ce. or QO. respectively, before the mdu:ated steady Slate Input conditions were established
~n. 0Sn. Cen. QDn - the level 01 0A. aS. Oc 00. respectively. before the most recent I IranSltlon of the clock
timing diagram
CLEAR
SEDR~~~ {R
INPUTS
L
-++-+---------t-t-'
PARALlEL ( :
DATA
INPUTS
C
O_~+--+--------------~~----------_+------------r__
0,:
(.. :
OUTPUTS
:~
--I----INHIBIT
CLEAR LOAD
CLEAR
1-115
Series 54/74
OM54196/0M74196(SN54196/SN741961.
OM 54197/0M74197(SN54197/SN741971
40 MHz presettable decade and binary counters/latches
general description
These high-speed monolithic counters consist of
four dc coupled master/slave flip-flops which are
internally interconnected to provide either a divideby-two and a divide-by-five counter (DM54196/
DM74196) or a divide-by-two and a divide-by-eight
counter DM54197/DM74197. These counters are
fully programmable; that is, the outputs may be
preset to any state by placing a low on the count/
load input and entering the desired data at the
data inputs. The outputs will change to agree with
the data inputs independent of the state of the
clocks.
pulse. The counters feature a direct clear which
when taken low sets all outputs low regardless of
the states of the clocks.
All inputs are diode-clamped to minimize transmission line effects and simplify system design.
The circuits are compatible with most TTL and
DTL logic families. Typical power dissipation is
150 mW. The DM54196 and DM54197 circuits are
characterized for operation over the full military
temperature range of -55°C to +125°C; the
DM74196 and DM74197 circuits are characterized
for operation from 0° C to +70° C.
These counters may also be used as 4-bit latches
by using the count/load input as the strobe and
entering data at the data inputs. The outputs will
directly follow the data inputs when the count!
load is low, but will remain unchanged when the
count/load is high and the clock inputs are inactive.
features
•
DC coupled counters designed to replace Signetics 8280, 8281, 8290, and 8291 counters
in most applications
Performs BCD, bi-quinary, or binary counting
Fully independent clear input
Guaranteed to count at input frequencies from
o to 40 MHz
Input clamping diodes simplify system design
•
•
•
These high-speed counters will accept count frequencies of 0 to 40 MHz at the clock 1 input and
Oto 20 MHz at the clock 2 input. During the count
operation, transfer of information to the outputs
occurs on the negative-going edge of the clock
•
connection diagram
Dual-In-Line Package
DATA INPUTS
,..--...-...,
T
14
CLEAR
13
B
QD
12
"
CLOCK
Q.
I
\0
0-
COUNTf
LOAD
Oc
-------DATA INPUTS
TOP VIEW
1-116
Q.
CLOCK
2
absolute maximum ratings
operating conditions
Supply Voltage. VCC (Note 1)
7.0V
Input Voltage (Note 11
5.5V
Interemltter Voltage (Note 21
5.5V
Storage Temperature Range
-4!5°C to +150°C
Lead Temperature (Soldering. 10 secondsl
300°C
Supply Voltage (VCCI
DM54196.DM54197
DM74196.DM74197
Temperature (TAl
DM54196.DM54197
DM74196.DM74197
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
-55
0
+125
+70
V
°c
°c
recommended operating conditions
CONDITIONS
MIN
MAX
TVP
Normalized Fan Out From Each O"tput (N)
High Logic Level
Low Logic Level
UNITS
20
10
Count Frequency (Figure 1)
Clock 1 Input
Clock 2 Input
o
o
Pulse Width (tw) (Figure 1)
Clock 1 Input
Clock 2 Input
Clear
Load
28
20
25
ns
ns
ns
ns
tWILOAO)
tWILOAOI
ns
ns
15
ns
ns
40
MHz
MHz
20
14
Input Hold Time (tHOLO) (Figure 1)
High Level Data
Low Level Data
Input Setup Time (t SETUP) (Figure 1)
High Level Data
Low Level Data
20
Count Enable Time (TENABLE) (Note 3) (Figure 1)
25
o
ns
Clock Input Pulse Fall Time (tF) (Figure 1)
75
ns
electrical characteristics
DM54197. DM74197
DM54196. DM74196
PARAMETER
CONDITIONS (N ... 51
MIN
TVP
(NoteS)
MAX
TVP
MAX
Low Level Input Voltage eVIL)
UNITS
(Note e)
v
20
20
High Level Input Voltage (V 1H I
MIN
08
08
-1.5
-15
V
V
Input Clamp Voltage (V I)
Vee'" Min. I, '" -12 rnA
High Level Output Voltage (V OH )
Vee = Min, VIH = 2.0V
VII = O.8V,l oH =-8OO$lA
Low Level Output Voltage (Vod
Vee = Min, V1H = 2.0V
V 1L ,. O.SV.tOL '" 16 mA (Note 7)
04
04
V
Input Current at Maximum Input
Vee'" Max, VI = 5 5V
10
10
mA
2.4
V
24
Voltage (1,1
HlltIlevellnputCurrent(lIH)
Data, Count/Load
Vee'" Max. VI = 2.4V
40
40
Cleat. Clock 1
80
80
Clock 2
120
80
Low Level Input Current (I'Ll
Vee'" Max, VI =04V
-16
-32
-48
-48
Data, Count/Load
Clear
Clock 1
Clock 2
Short-CIrcUit Output Current (los 1
-16
-32
-48
-32
mA
mA
mA
mA
-57
-57
mA
mA
54
mA
Vee ""Max
(NoteS)
-20
-18
DM54196. DM54\97
DM74196.DM74197
Supply Current (Icc I
Vee = Max, INote 41
-57
-57
39
54
-20
-18
39
,.,17
....en
;;:
....
:E
Q
switching characteristics
Vee = S.OV, RL. = 400n, CL. = so pF, T A = 2SoC, N = 10 (Figure 1)
~
FROM
INPUT
PARAMETER
en
;;:
TO
OUTPUT
Maximum Input Count
Frequency IfMAX I
It)
:E
MIN
40
OM54196. DM74196
TYP
MAX
60
DM64197. DM74197
MAX
MIN
TVP
40
60
UNITS
MHz
Clock 1
aA
10
15
10
15
ns
Clock 1
~
12
18
12
18
ns
Clock 2
aB
11
17
11
17
ns
Clock 2
Os
17
23
17
23
ns
Clock 2
Cle
25
37
25
37
ns
Clock 2
Cle
31
45
31
45
ns
Clock 2
OD
13
20
40
60
n.
Clock 2
00
18
25
48
72
ns
A.8.C.O
QA.
as. Oc. 00
16
24
16
24
ns
A.B.C.O
a A • a B • Cle. aD
12
24
12
24
ns
Propagation Oelay Tune, Low
to High Level Output (tPLH I
Load
Any
18
27
18
27
ns
Propagation Oelay Time, High
to Low Level Output ItpHd
Load
Any
20
30
20
30
ns
Propagation Delay Time, Hiltl
to Low level Output ItpHL I
Clear
Any
25
37
25
37
ns
Propagation Delay Time, Low
to High Level Output (tPl.H I
Q
Propagation Delay Time, High
U)
...
to Low Level Output ItPHd
en
~
Propagation Delay Time. Low
to HIgh Level Output (tPLH)
Propagation Delay Time, High
:E
to Low Level Output ItpHd
Q
.......
Propagation Delay Time, Low
U)
to High Level Output (tpLH)
;;:
Propagation Delay Time. HIg,
It)
Propagation Delay Time, Low
:E
to
en
to Low Level Output ItpHL)
Q
High Level Output (tpLH)
Propagation Delay Time, High
to Low Level Output (tPHL)
Propagation Delay Time, Low
to High Level Output (tpLH)
Propagation Delay Time, High
to Low Level Output (tPH L)
Note 1: Voltage values are With respect to network ground terminal.
Note 2: ThiS is the voltage between two emitters of a multlpte-emltter transistor. For thiS Circuit, thiS rating apphes between
the clear and count/load inputs.
Nota 3: Count enable time IS the Interval Immediately preceding the negatlVe"golng edge of the clock pulse during which
Interval the count/load and clear inputs must both be high to ensure counting.
Note 4: ICC IS measured With all Inputs grounded and all outputs open.
Note 5: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions
for the applicable device type.
Note 6: All typical values are at Vce = 5 av, TA = 25°C.
Not. 7: QA outputs are tested at tOl .. 16 mA plus the limit value of tIL for the clock 2 Input ThiS permits driVing the clock
2 I"PUt while fanning out to 10 Series 54n4 loads
Note 8: Not more than one output .hould be shorted at a time
typical count configurations
DM54196 AND DM74196
of ten), the' Go output must be externally
connected to the clock 1 input. The input count
is then applied at the clack 2 input and a
divide-by-ten square wave is obtained at output
QA in accordance with the bi-quinary function
table above.
The output of flip-flop A is not internally connected to the succeeding flip-flops; therefore, the
count may be operated in three independent
modes:
• When used as a binary-cooed-decimal decade
counter, the clock 2 input must be externally
connected to the QA output. The clack 1 input
receives the incoming count, and a count
sequence is obtained in accordance with the
BCD count sequence function table shown at
right.
• If a symmetrical divide-by-ten count is desired
for frequency synthesizers (or other applications
requiring division of a binary count by a power
1-118
•
For operation as a divide-by-two 'counter and a
divide-by-five counter, no external interconnections are required. Flip-flop A is used as a binary
element for the divide-by-two function. The
clock 2 input is used to obtain binary divideby-five operation at the Qs, Clc, and QD
outputs. In this mode, the tWD counters operate
independently; however, all four flip-flops are
loaded and cleared simultaneously.
typical count configurations (con't)
DM54197 AND DM74197
The output of flip-flop A is not internally connected to the succeeding flip-flops, therefore the
counter may be operated in two independent
modes:
at the OA, OB' Oc, and OD outputs are shown
in the function table at right.
• When used as a 3-bit ripple·through counter,
the input count pulses are applied to the clock 2
input. Simultaneous frequency divisions by 2,
4, and 8 are available at the OB, Oc, and OD
outputs. Independent use of flip·flop A is
available if the load and clear functions coincide
with those of the 3-bit ripple·through counter.
• When used as a high-speed 4-bit ripple-through
counter, output OA must be externally connected to the clock 2 input. The input count
pulses are applied to the clock 1 input. Simultaneous divisions by 2, 4, 8, and 16 are performed
function tables
DECADE (BCD)
BI-QUINARY (5-2)
DM54196/DM74196 (Note A)
COUNT
DM54197/DM74197 (Note AI
OUTPUT
OUTPUT
OUTPUT
COUNT
FUNCTION TABLE
DM54196/DM74196 (Note BI
aD Oc
as
aA
aA aD Oc
0
L
L
L
L
0
L
L
L
L
1
2
L
L
L
H
1
L
L
L
H
L
L
H
L
2
L
L
H
3
L
L
H
H
3
L
L
H
4
L
H
L
L
4
L
H
L
L
5
6
1
8
9
L
H
L
H
5
H
L
L
L
L
H
H
L
L
L
H
H
H
H
H
L
H
L
H
L
L
L
H
L
H
H
H
L
L
H
6
1
8
9
H
L
H
H
L
L
as
COUNT
aA
00 Oc
as
0
L
L
L
L
1
L
L
L
H
L
2
L
L
H
L
H
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
1
L
H
H
H
8
9
10
11
H
L
L
L
H
L
L
H
L
H
L
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
Note A: Output QA connected to clock 2 input.
Note B: Output QD connected to clock 1 input.
H
o
logic diagrams
DM54197/DM74197
DM54196/DM74196
::::T~ O----:::l:fJ'""1--------,
LOAD
CLEAR~"""",,,,,,,,,,,,,
CLOCK I
DATAB
CLEAR
o----H-J
ClOCK 1
o----t-i;r=)~~~:==~
CLOCK2o---~t_l---I_--t_....q
DATAC
.,
COUNT!
lOAD
o-----H--'
I1ATA.<>----ttr=)::=:~=~
.
o----+y;r=)~~~:t;;;;;;;;;~-~
CLOCK2o-----HI---t_----q
DATAC
DATA
..
o----H::fJo-t-----4==,-J
Do-----H~~o-,.:=::--I==:;:_--'
Do
1-119
Series 54/74
DM54198/DM74198(SN54198/SN74198) 8-bit shift register
general description
The DM54198/DM74198 is an eight-bit shift
register capable of being operated in four modes:
(1) Parallel-Load, (2) Shift-Right, (3) Shift-Left,
(4) Clock Inhibit (do nothing)_
With inputs So and SI at logic "1" levels the
data on the A through H inputs will be entered
on the next clock pulse_ Whether shifting left or
right, clocking occurs on the rising edge of the
clock pulse. During loading shifting is inhibited.
Cascading is accomplished by connecting the
Shift·Right and Shift-Left inputs to the outputs of
of the preceeding register or Q A of the following
register respectively. Clocking is inhibited when
both mode control inputs are low. The mode
control inputs should be changed only when the
clock input is high.
QH
features
• Shift Frequency
35MHz
• Power Dissipation
360mW
logic and connection diagrams
Duel In-Line and Flat Package
SHIFT
LEFT
SERIAL INPUT
Vee
S, INPUT
I"
23
Z2
H
21
INPUT
Ow
G
20
19
Do
INPUT
18
F
a"
17
INPUT
E
" "
Ot:
CLEAR
,.
13
truth table
INPUTS
,
MODE
p-
r-
2
3
•
5
6
1
8
•
RIGHT
INPUT
A
BCD
1-120
TOP VIEW
So
L
L
H
L
H
L
H
H
10
t1
1'2
So SHIFT INPUT QA INPUT Oa INPUT Oe INPUT Do CLOCK GNO
SERIAL
S,
I nhlblt Clock
Sh,ft Right
Shift Left
Parallel Load
o
absolute maximum ratings (Note 1)
operating conditions
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Supply Voltage (VCC)
DM54198
DM74198
Temperature (T A)
DM54198
DM74198
MIN
7V
5.5V
5.5V
-65°C to +150°C
300°C
4.5
4.75
-55
0
s:
U1
.j:Io
....
CD
MAX
5.5
5.25
+125
70
UNITS
CO
........
o
V
V
s:
....
°c
°c
.j:Io
....
CD
CO
electrical characteristics
(Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
V
2
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee:::: Mm
Logical "1" Output Voltage
Vee:::: Min
V ,H = 2V
lOUT = -800 pA
V'L = 0.8V
Logical "0" Output Voltage
Vee:::: Min
V ,H = 2V
lOUT = 16 mA
V'L = 0.8V
Logical" 1" I nput Current
Vee = Max
Y,N = 2.4V
40
pA
Vee:::: Max
Y,N =55V
1
mA
Vee == Max
Y,N =04V
Vee = Max
Vo = OV
Input CUrrent at Maximum Input
Voltage
Logical "0" Input Current
Output Short Circuit Current
(Note 3)
Supply Current (each device)
Vee:::: Max
08
V
V
2.4
04
V
mA
-1.6
-20
-18
72
-57
mA
104
116
mA
V
-1.5
Input Clamp Voltage
Vee == Min
liN = -12 mA
Propagation Delay to a Logical "0" from
Clear to Output, tpdO
Vee = 5.0V
TA = 25°C
CL = 50 pF, RL = 400~
35
ns
Propagation Delay to a Logical "0" from
Vee = 5.0V
TA = 25°C
CL = 50 pF, RL = 400~
30
ns
PropagatIOn Delay to a Logical "1" from
Clock to Output, tpd1
Vee = 5.0V
TA = 25°C
CL = 50 pF, RL = 400~
26
ns
Maximum Clock Frequency
Vee = 5.0V
TA = 25°C
Minimum Clock and Clear Pulse Width
Vee = 5.0V
T A = 25°C, CL = 50 pF
20
ns
Data Setup Time
Vee = 5.0V
TA = 25°C,C L ~50pF
20
ns
Vee = 5.0V
T A = 25°C, CL = 50 pF
30
ns
Vee=50V
TA = 25°C, CL = 50 pF
0
ns
Clock to Output,
tpdO
Mode Control Setup Time
tSETUP
Hold Time at Any Input, tHoLD
25
0
35
MHz
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed.
Except for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these
limits The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified mm/max limits apply across the -55°C to +12SoC temperature range for the DM54198
and across the O°C to +70°C range for the OM74198 All tYPlcals are given for Vee = 5.0V and TA = 2SoC.
Note 3: Only one output at a time should be shorted.
1-121
Series 54/74
OM54199/0M74199(SN54199/SN74199) a-bit shift register
general description
The DM54199/DM74199 is an 8-bit shift register capable of being operated in three modes:
(1) Parallel-Load, (2) Shift-Right, (3) Inhibit Clock.
Parallel load is accomplished by applying the eight
bits of data and taking the Shift/Load control
mput low when the clock input is not inhibited.
Data appears as the output after the positive transition of the next clock pulse. During loading
shifting is inhibited. Shifting is accomplished
synchronously when Shift/Load is high and the
clock input is not inhibited. Serial data is entered
at the J-K inputs. In order to cascade devices,
connect the Q H output of one stage to the J-K
inputs (tied together) of the following stage. Both
Clock and Clock Inhibit are identical in function
and may be used interchangeably to serve as
clock or a clock inhibit inputs. Holding either high
inhibits clocking; but when one is held low, the
other will clock the register. Therefore the clock
inhibit input should be changed from low to high
only while the clock input is high.
features
•
Shift Frequency
35 MHz
•
Power Dissipation
360mW
logic and connection diagrams
ClDCKCLOCKJ
INHIBIT
RSHlfTl
A
LOAD
Dual-tn-Line and Flat Package
SHIFTflNPUT
Vee
I.,
LOAD
13
H
22
INPUT
OH
21
G
INPUT
QG
2D
F
INPUT
Of
19
18
E
17
Q E CLEAR CLOCK
16
15
14
13
truth table
J-K INPUTS
r-
I-
2
1
K
J
SERIAL
INPUTS
J
, ,
6
1
TOP VIEW
1-122
8
INPUT Ojl INPUT 0 8 INPUT Dc
ABC
,
10
11
112
INPUT Qo CLOCK GND
0
INHIBIT
INPUTS
OUTPUT
at tn
tn+1
J
K
CA
L
L
H
H
H
L
H
L
CAn
L
H
(jAn
H eo high level, L '" low level
NOTE A tn = bit time before clock pulse
NOTE B. tn+1 = bit time after clock pulse
C
absolute maximum ratings (Note
1)
operating conditions
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
7V
5.5V
5.5V
-65°C to +150°C
300°C
3:
Supply Voltage (VCC)
DM54199
DM74199
45
475
U'I
MAX
5.5
5.25
...
oIloo
UNITS
CD
CD
V
V
......
°c
°c
3:
.....
C
Temperature (T A)
DM54199
DM74199
-55
0
+125
70
...
oIloo
CD
CD
electrical characteristics (Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
Logical" 1" Input Voltage
Vee;= Min
Logical "0" Input Voltage
Vee == Mm
Logical" 1 " Output Voltage
Vee Min
V ,H ° 2V
lOUT ° -800 IlA
V ,L o 08V
LogIcal "0" Output Voltage
Vee '= Mm
V ,H ° 2V
lOUT ° 16 rnA
V,LoOSV
Logical" 1" I rput Current
Vee == Max
Y'N ° 2 4V
40
iJ.A
Vee"" Max
Y'N ° 5 5V
1
rnA
Vee
Y'N °04V
Input Current at MaXimum Input
Voltage
Logical "0" Input Current
Output Short Circuit Current
(Note 3)
0;;;
:co
Max
Vee == Max
2
V
O.S
Y'N ° OV
24
V
V
04
-16
V
72
-57
rnA
104
116
rnA
Supply Current (each deVice)
Vee:::: Max
Input Clamp Voltage
Vee = Min
liN = -12 rnA
PropagatIon Delay to a Logical "OH from
Vee ° 50V
TA = 25°C
CL ° 50 pF, RL ° 400[2
35
ns
Clock to Output, tpdO
Vce=50V
TA 25°C
CL = 50 pF, RL ° 400[2
30
ns
Propagation Delay to a Logical "1" from
Clock to Output, tpdl
Vee = 50V
TA = 25°C
CL = 50 pF, RL = 400[2
26
ns
Maximum Clock Frequency
Vee=50V
TA = 25°C
MInimum Clock and Clear Pulse Width
Vee = 50V
T A = 25°C, C L = 50 pF
20
ns
Data Setup Time
Vee ° 50V
TAo 25°C, C L ° 50 pF
20
ns
Mo<;le Control Setup Time tSETUP
Vee = 5.0V
T A = 25°C, C L = 50 pF
30
ns
Hold Time at Any Input, tHOLD
Vee=50V
T A = 25°C, C L = 50 pF
0
ns
Clear to Output,
tpdO
Propagation Delay to a Logical "0" from
-15
25
D
rnA
-20
-18
V
35
MHz
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the deVice cannot be guaranteed.
Except for "Operating Temperature Range" they are not meant to Imply that the deVIces should be operated at these
limits. The table of "Electrical CharacteristIcs" provides condItIons for actual deVIce operation.
Note 2: Unless otherwise speCified mm/max limits apply across the -55°C to +125°C temperature range for the DM54199
and across the O°C to +70°C range for the DM74199. All tYPlcals are given for Vee = 5.0V and TA = 25°C.
Note 3: Only one output at a time should be shorted.
1·123
o
en
o
co
:E
Series 54/74
c
.......
o
en
o
.....
:E
DM7090/DM8090 quad inverter/dual 2-input NAND buffer
c
general description
The DM7090/DM8090 optimizes the flexibility of
the 16-pin package by providing two 2-input
NAND gates and four inverters in the same package_ The electncal specifications are totally compatible with all Senes 54/74 devices_
schematic and connection diagrams
Dual~ln-Line and Flat Package
r---e--+--ovee
vee
130n
INVE~r~~ 0--"'-'1"
OUTPUT
GND
TOP VIEW
1-124
c
absolute maximum ratings
--.
...,
==
operating conditions
(Note 11
o
CD
MIN
Supply Voltage
Input Voltage
Output Voltage
7.0V
5.5V
5.5V
_65°e to +150o e
3000 e
Storage Temperature Range
lead Temperature (Soldering, 10 sec)
Supply Voltage (Vee)
DM7090
DM8090
4.5
4.75
Temperature (TA)
DM7090
DM8090
-55
0
MAX
5.55.25
+125
70
UNITS
V
V
o
......
c
==
o
00
CD
°e
°e
o
"
electrical characteristics
(Note 21
CONDITIONS
PARAMETER
MIN
Logical "'" Input Voltage
v~c= Min
Logical "0" Input Voltage
Vee" Mm
Logical "'" Output Voltage
Vcc = Mm, VIN "" 0 av, lOUT =
TYP
MAX
20
V
08
-400~A
UNITS
24
V
V
Logical "1" Output Current
Logical "0" Output Voltage
Vee
= MIn:VIN = 2 nv,
LogIcal "'" Input Current
Vee
=Max, V IN = 24V
Vee"" Max, V IN
Output Short CirCUit Current
(Note 3)
Vee = Max, V OUT
-20
-18
1
mA
-16
mA
Vee = Max, V IN = 0
11
mA
Vee = Max, V IN == 50V
31
mA
Propagation Delay to a LogIcal "0"
from Inputs to Outputs, tpdO
Vec=50V
TA = 25°e
Vce=50V
= 25°C
tpd1
DM7090
DM8090
I'A
mA
Vec ' 50V, liN
Propagation Delay to a Logical "1"
=0
V
40
-55
Input Clamp Voltage
from Inputs to Outputs,
04
= 5 5V
Vee
Logical "0"
= 16 rnA
= Max, VIN = 0 4V
Logical "0" I nput Current
Supply Current - Logical "'"
(each device)
lOUT
= -12 mA, T A = 25°e
TA
-1.5
V
9
15
ns
13
25
ns
-10
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -SSoC to +12SoC temperature range for the DM7090 and
acroSS the O°C to 700 e range for the DM8090. All typlcals are given for Vee
Note 3: Only one output at a time should be shorted.
= 5.0V and TA = 25°e.
1-125
0
...en
o
CX)
Series 54/74
::E
......
Q
...en
o
,...
::E
DM70911DM8091 quad 2-input NAND buffer
Q
general description
The DM7091/DM8091 provides four 2-input gates
each with a fan-out of 30, in the same package_
The electrical specifications are totally compatible
with all Series 54/74 devices_
schematic and connection diagrams
~--.---....-ov"
INPUT
o-_~,.
INPUT
0---+-.
loon
SODn
4K
OUTPUT
Dual·ln-Line and Flat Package
GNO
14
13
12
"
TOPVIEW
1-126
10
c
3:
absolute maximum ratings
"0CD
operating conditions
...&
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
7.0V
55V
55V
-65'e to +150'e
300'e
electrical characteristics
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
'e
'e
TYP
MAX
= Min
Logical "0" I nput Voltage
Vee
= Mm
Logical "1" Output Voltage
Vee
= Mm,
MIN
Logical "0" Output Voltage
Vee
Logical "1" I nput Current
0.8
= 0.8V,
= Min,
V ,N
= 2.0V,
Vee
Vee
= Max,
= Max,
V ,N
V ,N
= 2.4V
= 5.5V
V ,N
= O.4V
Logical "0" I nput Current
Vee
= Max,
Output Short Circuit Current
(Note 3)
Vee
= Max
Supply Current - Logical "1"
Vee
Logical "0"
Vee
= Max,
= Max,
Vee
= 5.0V, TA = 25°C,
lOUT
= -1.2
lOUT
= 48 mA
mA
V
2.4
0.4
-18
V ,N
V ,N
=a
= 5.0V
liN
= -12 mA
-1.0
V
40
1
IlA
mA
-1.6
mA
-70
rnA
15
rnA
46
mA
-1.5
V
15
ns
= 5.0V
= 25°C
13
22
ns
Propagation Delay to a Logical "1"
from Any Input to Output, tpd'
TA
...&
V
8
TA
00
U)
UNITS
= 5.0V
= 25°C
Vee
from Any Input to Output, tpdO
3:
V
2
V ,N
Propagation Delay to a Logical "0"
.......
C
0
Temperature (TAl
DM7091
DM8091
CONDITIONS
Vee
Input Clamp Voltage
MAX
(Note 1)
PARAMETER
Logical "1" Input Voltage
Supply Voltage (Vee)
DM7091
DM8091
MIN
Vee
0
Note 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" prOVides conditions for actual device operation
Note 2 Unless otherWise speclfted min/max limits apply across the -55"C to +12SoC temperature range for the DM7091 and
across the oOe to 70°C range for the OM8091 All typlcals are given for Vee -'" 5 OV and T A'" 25°C
Note 3: Only one output at a time should be shorted
1-127
N
d)
o
00
:E
Series 54/74
Q
"N
G)
o
r-.
:E
Q
DM7092/DM8092 dual 5-input NAND gate
general description
features
The DM7092/DM8092 is a dual 5-input NAND
gate utilizing TTL (Transistor-Transistor Logic)_
The device fills a gap in the standard 54/74 series
in that it replaces two single 8-input gates (with
tied inputs) or an assembly of smaller gates_ Also
either of the two 5-input gates can be used as a
smaller gate_
• Series 54/74 compatibility
• No longer necessitates use of SN5430/SN7430
(eight-input-gate) for the five-input function
• Specifications identical to standard SN54XX/
SN74XX gate
logic and connection diagram
Dual-In-Line and Flat Package
1
14
I
13
1"
11
~
2
,
•
~
I' •
4
TOP VIEW
1-128
10
B
J~
c
absolute maximum ratings
~
......
(Note 1)
o
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM7092
DM8092
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
electrical characteristics
CD
N
7V
5.5V
5.5V
........
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
CD
N
C
~
00
o
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DM7092
DM8092
Vee" 4.5V
V ee - 475V
DM7092
DM8092
Vee" 4.5V
Vee 4.75V
logical "1" Output Voltage
DM7092
DM8092
Vee" 4.5V
Vee - 4.75V
lOUT" -400/lA, V ,N " 0 8V
Logical "0" Output Voltage
DM7092
DM8092
Vee" 4.5V
V ee -475V
lOUT"" 16 rnA; V IN
Logical "1" Input Current
DM7092
DM8092
Vee "55V
V ,N "24V
Vee 525V
40
/lA
DM7092
DM8092
Vee"55V
V ,N " 5 5V
Vee 525V
1
mA
DM7092
DM8092
Vee" 5.5V
Y'N "OAV
Vee - 5.25V
-1.6
mA
DM7092
DM8092
Vee"55V
Vee 5.25V
V OUT
Supply Current - Logical" 1"
(Each Device)
DM7092
DM8092
Vee"55V
V ce -525V
VIN = OV
Logical "0"
DM7092
DM8092
Vee"55V
V ,N "50V
Vee 525V
logical "1" Input Voltage
Logical
"a"
Input Voltage
Logical "0" I nput Current
Output Short CircUit Current
(Note 3)
V
20
08
.
V
24
= 2 OV
= OV
V
0.4
-20
-18
-55
mA
1
18
mA
3
51
mA
-12 rnA, TA = 25°C
Input Clamp Voltage
Vee
-15
V
Propagation Delay to a Logical "0", tpdO
V ec "50V, T A "25°C,C"50pF
8
15
ns
Propagation Delay to a LogIcal "1", tpdl
Vee = 5.QV, TA = 25°C, C = 50 pF
13
25
ns
=
5 OV, liN
=
D
V
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of HElectrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM7092 and across the O°C to 70°C range for the DM8092. All typlcals are given for
VCe" S.OV and T A " 25°C.
Note 3: Only one output at a time should be shorted.
1-129
qo
en
o
Series 54/74
CO
::?!
Q
......
qo
en
o
,...
::?!
Q
®
DM7093/DM8093TRI-STATE quad buffer
DM7094/DM8094 TRI-STATE quad buffer
(W)
en
o
general description
CO
::?!
Q
......
(W)
en
o,...
::?!
Q
• Up to 128 Buffers can be Connected to a Common Bus-Line
The DM7093/DM8093 and DM7094/DM8094 are
quad 2-input buffers which accept normal TTL or
DTL input levels and have outputs which provide
either normal low-impedance TTL output characteristics or a high impedance state. One of the two
inputs to each buffer is used as a control line to
gate the output into the high impedance state. The
other input simply passes the non-inverted data
through the buffer. The DM7093/DM8093 and
DM7094/DM8094 differ only in the activating
logic state of the control input. The
DM7093/DM8093 provides the high impedance
state when a logical "1" is applied to the control
input; the DM7094/DM8094 operates similarly
with a logical "0".
• 12 ns Propagation Delay
• High Capacitive Drive Capability
• I ndependent Control of each Buffer
Thisunique TRI-STATE concept allows outputs to
be tied together and then connected to a common
bus line. Normal TTL outputs cannot be connected due to the low-impedance logical "1" output current which one device would have to sink
from the other. If however on all but one of the
connected devices both the upper and lower output transistors are turned off, then the one remaining device in the normal low impedance state will
have to supply to or sink from the other devices
only a small amount of leakage current. This is
exactly what occurs on the DM7093/DM8093 and
DM7094/DM8094.
features
• Series 54/74 TTL and 930 DTL Compatible
• Same Pin Breakout as SN5400/SN7400 TTL
and 946 DTL
(Continued on following pages)
logic and connection diagram
Dual-In-Line and Flat Package
CONTROL
\Icc
GONTROl
OATA
OU,TPUT
OUTPUT
CONTAOL
DATA
OUTPUT
~ONTROL
*1<>-.----t---.+--+-.-II--I-....+-+---,
z,
connection diagram
z,
z.
truth table
Dual-In-Line and Flat Package
Vee
SELECT
ENABLE
Joe
i,c
Zc
lOA
100
Za
ENABLE
SELECT
INPUT
I,
10
OUTPUT
1
X
X
X
0
1
X
0
0
0
0
1
X
1
1
0
0
0
X
0
1
X
1
HI-ZState
0
GND
TOP VIEW
1-137
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM7123
DM8123
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 1)
7V
5.5V
5.5V
_55°C to 125'C
O°C to 70°C
_65°C to 150°C
300°C
electrical characteristics
(Note 2)
PARAMETER
Logical "I" Input Voltage
Logical
"a" Input Voltage
CONDITIONS
DM7123
DM8123
Vee = 4.5V
Vee - 4.75V
MAX
2.0
lOUT = -2.0 mA, V'N = 2V
lOUT = -5.2 mA, V'N = 2V
Vee = 4.5V
Vee = 4.75V
"a" Output Voltage
DM7123
DM8123
Vee = 4.5V
Vee - 4.75V
lOUT = 16 mA, V'N = .8V
Third State Output Current
DM7123
DM8123
Vee = 5.5V
Vee - 5.25V
0.40:-;; V OLH :-;; 2.4V
V'N (Enable) = 2V
Logical "1" In pu t Cu rrent
DM7123
DM8123
Vee = 5.5V
Vee = 5.25V
DM7123
DM8123
UNITS
V
.8
DM7123
DM8123
V
V
2.4
.4
V
40
p.A
V'N=24V
40
p.A
Vee = 5.5V
Vee 5.25V
V'N = 5.5V
1
mA
DM7123
DM8123
Vee = 5.5V
Vee - 5.25V
V'N = O.4V
-1.6
mA
Output Short Circuit Current
(Note 3)
DM7123
DM8123
Vee = 5.5V
Vee - 5.25V
V'N = 4.5V
-50
-70
mA
Supply Current
DM7123
DM8123
Vee = 5.5V
Vee = 5.25V
V'N (Enable) = 4.5V
Other Inputs OV
40
51
mA
Input Clamp Voltage
DM7123 Vee = 5.0V
DM8123 TA - 25 C
I'N = -12 mA
-1.0
-1.5
V
Logical
"a" Input Current
-40
-1.0
-30
Propagation Delay to a Log,cal
Data to Output, tpdO
"a" from
Vee = 5.0V
TA = 25°C
5
11
18
ns
Propagat,on Delay to a Logical
Select to ZA, tpdO
"a" from
Vee = 5.0V
TA = 25°C
8
17
24
ns
Propagation Delay to a Logical" r' from
Data to Output, tpd1
Vee = 5.0V
T A = 25°C
4
8
15
ns
Propagation Delay to a Logical "I" from
Select to ZA, tpd1
Vee = 5.0V
TA = 25°C
5
15
23
ns
Delay from Disable to H,gh Impedance
State (from Logical "I" Level), t, H
Vee = 5.0V
TA = 25°C
4
7
11
ns
Delay from Disable to H'gh Impedance
State (from Logical "a" Levell. tOH
Vee = 5.0V
TA = 25°C
9
19
27
ns
Delay from Disable to Logical" 1" Level
Vee = 5.0V
TA = 25°C
9
18
25
ns
Vee = 5.0V
TA = 25°C
10
23
30
ns
(from High Impedance State). tH1
Delay from Disable to Log,cal "a" Level
(from High Impedance State), tHO
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherWise specified mm/max limits apply across the _55°C to +12SoC temperature
range for the DM7123 and across the O°C to 70°C range for the DM8123. All tYPlcals are given for
Vee· 5.0V and TA = 25"e.
Nota 3: Only one output at a time should be shorted.
1-138
TYP
DM7123 Vee = 4.5V
DM8123 Vee = 4.75V
Logical" 1" Output Voltage
Logical
MIN
c
s:.....
....W
Series 54/74
o
......
c
s:
00
....
DM7130/DM8130 10-bit comparator
DM7160/DM8160 6-bit comparator
W
o
c
general decription
features
The DM7130/DM8130and DM7160/DM8160comparators determine equality or non-equality between two binary words. The DM7130/DM8130
compares two ten-bit words while the DM7160/
DM8160 compares two six-bit words. A strobe
over-ride is provided on both devices which when
taken to a logical "1" will force the output to a
logical "1 ".
•
Series 54/74 compatible
•
20 ns tYPical compare delay
•
TYPical power dissipation
DM7130/DM8130
DM7160/DM8160
•
s:.....
....
0)
o
......
c
s:
00
240mW
205mW
....
Open collector outputs for expandabli,ty
0)
o
logic and connection diagrams
Ao
80
A,
II,
A,
B,
A,
8,
A.
D
Dual-I n-line and Flat Package
Dual-In-Line and Flat Package
B. STROBE GND
DM7160/DM8160
DM7130iOM8130
truth table
CONDITION
STROBE
Z
S
A=B,A*B
A=B
A*B
1
0
0
1
1
0
For DM7130/DM8130:
IAI = Ag . - . - - - Ao
IBI = B9 . - .... Bo
z = s + (Xo . X,
• X 2 . X3 • X 4 . X5 ' X6 . X,· Xs' X9
I
For DM7160/DM8160:
IAI = A5
. - - AD
IBI = B5 . - .. - . Bo
z = s + (Xo
. X, . X 2 • X3 ,X 4 . X5
I
where.
Xo
=
Ao Bo + Ao 8 0 . X,
=
A, B1 + A, 8,
1-139
o
...
cg
CIO
~
C
......
o
...
absolute maximum ratings
(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
cg
Outpu t Voltage
.....
Operating Temperature Range DM8130, DM8160
O°C to 70°C
DM7130,DM7160
-55°C to +125°C
C
Storage Temperature Range
~
5.5V
-65°C to +150°C
300°C
Lead Temperature (Soldering, 10 sec)
o
...
('I)
CIO
~
C
......
o
electrical characteristics
...
('I)
.....
~
C
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
DM7130,DM71S0
DMS130,DMS1S0
Vee = 4.5V
Vee = 4 75V
Logical "0" Input Voltage
DM7130,DM71S0
DMS13O,DMS1S0
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Current
DM7130,DM7160
DMS13O,DMS1S0
Vee = 5.5V
Vee 5.25V
V OUT = 5.5V
Logical "0" Output Voltage
DM7130,DM71S0
DMS130,DMS1S0
Vee=45V
Vee - 4.75V
IOL = IS rnA
Logical "1" Input Current
DM7130/DM7160
DMS13O,DMS1S0
Vee = 5.SV
Vee- 525V
Y,N = 2.4V
40
IlA
DM7130,DM71S0
DMS130,DMS1S0
Vee = 5.SV
Vee 5.2SV
Y,N = 5.5V
I
rnA
Logical "0" I nput Current
DM7130,DM7160
DMSI30,DMS1S0
Vee = S.SV
Vee - 5.2SV
Y,N = O.4V
-1.S
rnA
Supply Current
DM7130,DM71S0
DMS130,DMS1S0
Vee = 5.5V
Vee = 5.2SV
4S
70
rnA
DM7130,DM7160
DMS130,DMS1S0
Vee = 5.5V
Vee - 5.25V
41
SO
rnA
DM7130,DM71aO
DMS130,DMS160
Vee=45V
Vee - 4 75V
liN = -12 rnA, TA = 2S'C
Propagation Delay to a logical "0" from Strobe
to Output, tpdO
Vee = S.OV
T A =25'e
See ae test Circuit
Propagation Delay to a Logical "1" from Strobe
Vee=SOV
TA=2S'e
Input Clamp Voltage
to Output,
tpdl
Propagation Delay to a Logical "0" from Data
to Output,
tpdO
Propagation Delay to a Logical "1" from Data
to Output, tpdl
2
O.S
100
0.2
0.4
V
IlA
V
-1.5
V
20
30
ns
See ae test clrcu It
g
IS
ns
Vee = S.OV
TA=2S'e
See ae test CI rcu It
27
40
ns
Vee = S.OV
TA=25'e
See ae test circuit
IS
25
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operatmg Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherWise specified mm/max limits apply across the -5SoC to +12SoC temperature
range for the DM7130 and DM7160 and across the o'e to 70'e range for the DMS130 and DMSt60.
All tYPleals are given for Vee = 5.0V and T A = 2S'e.
1-140
V
c
Series 54/74
~
.....
....
....
W
.......
C
DM71311DM8131. DM7136/DM8136
6-bit unified bus comparator
general description
The DM7131/DM8131, DM7136!DM8136 compare two binary words of two-to-six-bits in
length and indicates matching bit-far-bit of the
two words, Inputs for one word are 54/74 seriescompatible TT L inputs, whereas those of the
second word are high impedance receivers driven
by a terminated data bus, These bus inputs include 1V typical hysteresis which provides 1.8V
noise immunity. The DM7131/DM8131 has active
pu II up output and goes to the low state upon
comparison, The DM7136/DM8136 has opencollector output which goes to high state upon
comparison and is expandable to n bits by collector-ORing. Both devices have an output latch
which is strobe controlled_
The transfer of information to the output occurs
when the STROBE input goes from a logic "1"
s:00
....
....
W
c
s:.....
to logic "0" state. Inputs may be changed while
the STROBE is at the logic "1" level without
affecting the state of output. These devices are
useful as address comparators in computer systems
utilizing unified data bus organization.
....
W
(7)
.......
C
s:
features
•
00
....
W
15J.LA typ
Low bus input current
(7)
1.8V typ
• High bus input noise immunity
• High fan out
•
Input clamping diodes
• Output compatible with TTL circuits
01
• Output latch provision
logic and connection diagrams
Dual-In-Line and Flat Package
(BUSINPUTl 811
1BVce
{TTlINPUTI 11 2
1586
1416
OUTPUT
{DM11311
13B5
T2 •
OUTPUT
(DMl13B)
"
1215
5
T3 •
"84
STROBE 1
IOT4
GND I
!J OUTPUT
TOP VIEW
R= HIGH IMPEDANCE
BUS RECEIVER
1-141
absolute maximum ratings
operating conditions
Supply Voltage
TTL and Strobe Input Voltage
Fan Out
Supply Voltage
DM7131,DM7136
DM8131,DM8136
Temperature IT AI
DM7131,DM7136
DM8131,DM8136
Storage Temperature Range
7V
5.5V
10
-65°C to +150°C
electrical cha racteristics
PARAMETER
TYP
MAX
UNITS
4.5
4.75
5
5
5.5
5.25
V
V
-55
0
+25
+25
+125
+70
°c
°c
(Operating Temperature Range - Unless Otherwise Specified)
MIN
CONDITIONS
TYP
MAX
UNITS
V
Input "1" Voltage (Except Bus Inputs)
Vee = Min
Input "0" Voltage (Except Bus Inputs)
Vee'" Mm
Bus Input "1" Threshold Voltage
DM7131,DM7136
OM8131,DM8136
165
180
Bus Input "0" Threshold Voltage
DM7131.DM7136
DM8131.DM8136
097
105
Input Clamp Diode Voltage
Vee = Max, lIN'" -12 mA
T A = +25°C
-15
TTL Input "1" Current
Vee = Max, VIN == 2 4V
VIN '" 5 5V
40
1
MA
rnA
20
08
V
225
225
265
250
V
V
13
13
163
155
V
V
V
TTL Input "0" Current
Vee = Max, VIN "" 0 4V
-16
rnA
Strobe Input "1" Current
Vcc=Max,VIN=24V
VIN = 5 5V
80
2
MA
rnA
Strobe Input "0" Current
Vee =Max, VIN =04V
-2.4
rnA
MaXimum Bus Input Current
Vee = Max, VIN '" 4V
Vee == av, VIN == 4V
50
50
MA
MA
LogiC "0" Output Voltage
Vee = Mm, lOUT = 16 rnA
LogiC "1" Output Voltage
Vee::: Mm, lOUT::: -400 ilA
DM7131
DM8131
15
1
04
LogiC "1" Output Current
Vec'" Max, VOUT ::: SV
DM7136
DM8136
Output Short CirCUit Current
Vee::: Max, VOUT ::: OV
DM7131
DM8131
V
V
24
-20
-18
250
MA
-55
-55
74
rnA
rnA
rnA
Power Supply Current
Vee::: Max
50
Propdgatlon Delays
TTL Input to Output, tpdl
Vee::: SV, TA '" 2SoC
20
ns
TTL Input to Output, tpdO
Vee::: SV, TA '" 2SoC
20
ns
Bus Input to Output, tpdl
Vee'" SV, TA '" 2SoC
30
ns
Bus Input to Output, tpdO
Vee'" SV, TA '" 2SoC
30
ns
Strobe Input to Output, tpdl
Vee'" SV, T A'" 2SoC
20
ns
Strobe Input to Output, fpdO
Vee '" SV, TA::: 2SoC
20
ns
/'
1-142
MIN
c
illS
Series 54/74
!:
....N
o
o
.......
c
!:
CO
N
OM7200/0M8200 4-bit comparator
o
general description
features
The DM7200/DM8200 is a monolithic TTL
(Transistor-Transistor Logic) circuit which is used
to compare the numerical values of two four-bit
binary numbers. Outputs indicate (1) whether
number A is greater than number B. (2) whether
number B is greater than number A. or (3) whether
the two numbers are equal. A strobe input overrides all other inputs and places the outputs in a
definite state. The design chosen provides maximum speed with minimum circuit complexity.
Numerical comparisons of words longer than four
bits may be made by using additional DM7200/
DM8200' s only.
•
•
Series 54/74 Compatible
Typical Noise Immunity
•
Guaranteed Noise Immunity
o
1V
400mV
•
Typical Propagation Delay
20 ns
•
Typical Power Dissipation
175mW
applications
•
Digital stepping-motor control applications
•
Convergence applications
•
Summing junction for digital servo systems
o
logic and connection diagram (Dual-In-Linoand FlatPackago)
A. IS 'N mod "InlllUllt Itlt at A
logic table
Input
Number A4A3A2A,
Output
Number B4B3B2B,
Strobe
X
Y
B
0
1
0
A
>
<
B
0
0
1
A
=
B
0
1
1
A
~
B
1
0
0
A
1-143
o
o
N
CIO
absolute maximum ratings
~
Supply Voltage
Input Voltage
........
o
Operating Temperature Range
N
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
Q
o
.....
~
Q
electrical
7V
5.5V
_55°C to +125°C
DM7200
DM8200
O°C to +70°C
_65°C to +150°C
300°C
characteristics(Note 1)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" O... tput Voltage
Logical "0" Output Voltage
Logical "1" Input Current
Logical "0" I nput Current
Logical "1" Input Current
Output Short Circuit
Current (Note 2)
Supply Current
DM7200
Vee = 4.5V
DM8200
Vee = 4.75V
DM7200
Vee = 4.5V
DM8200
Vee = 4.75V
DM7200
Vee = 4.5V
DM8200
Vee = 4.75V
DM7200
Vee = 4.5V
DM8200
Vee - 4.75V
lOUT = -400 JJ.A
2.4
DM7200
Vee = 5.5V
Vee - 5.25V
DM7200
Vee = 5.5V
DM8200
Vee = 5.25V
DM7200
Vee = 5.5V
DM8200
Vee = 5.25V
DM7200
Vee = 5.5V
-20
DM8200
Vee = 5.25V
-18
DM7200
Vee = 5.5V
DM8200
Vee = 5.25V
V
V
.4
DM8200
UNITS
V
lOUT = 16 mA
V
V 1N = 2.4V
80
JJ.A
V 1N = O.4V
-3.2
mA
V 1N = 5.5V
1
mA
-55
-57
mA
rnA
35
53
mA
24
40
ns
17
30
ns
15
27
ns
8
18
ns
0
10
ns
-10
0
ns
TA = 25°C
Propagation Delay to a
Logical "0" from Any Data
tpd
I nput to Output
0
Vee = 5.0V
T A = 25°C
Propagation Delay to a
Logical" 1" from Strobe
Input to Output
tpd
1
T A = 25°C
Propagation Delay to a
Logical "0" from Strobe
tpd
Input to Output
0
T A = 25°C
Vee = 5.0V
Vee = 5.0V
Vee = 5.0V
Vee = 5.0V
TA = 25°C
Vee = 5.0V
TA = 25°C
Note 1: Unless otherwise specified, limits shown apply from -5SoC to +1250 C for the OM7200 and
OoC to +70oC for the DM8200. Typical values apply to supply voltages of 5.0V.
Note 2: Only one output should be shorted at 8 time.
1·144
MAX
.8
1
Time Prior to Removal of
Strobe that Data Inputs
Must Be Stabilized I tSET UP
TYP
2.0
Propagation Delay to a
Logical" 1" from Any Data
Input to Output
tpd
Time After Activation of
Strobe that Data Inputs
Must be Held I t HOLD
MIN
c
3:
......
Series 54/74
...
N
o
......
c
3:
DM7210/DM8210 8-channel digital switch
DM7211/DM8211 8-channel digital switch
00
N
...
o
general description
c
3:
eight b,ts of parallel Information are applied to the
inputs, and if the bmary numbers 000 through 111
are sequenced on the select lines, the output will
provIde a serial presentation of the mput bits
The DM72101DM8210 and DM7211/DM8211 are
digItal bIpolar mtegrated cIrcuIts employmg TTL,
used to multiplex eight INPUT channels to a single
OUTPUT. Dependmg upon the 3·bit bmary num·
ber applied to the SELECT Imes, the digital bit on
the unique INPUT selected appears on the output.
..................
N
c
features
The DM7211/DM8211 provides a strobe input
which when taken to a logical "I" level places
the output m the logical "I" state.
The circuit can also be used to convert parallel
mput mformation to serial output informatIon. If
•
•
TTL CircUItry
Input Clampmg Diodes
•
1 Volt Typical Noise Immunity
•
400 mV Guaranteed Noise Immunity
•
Completely compatible with Senes 54/74 circuits
3:
00
N
...
01
connection diagrams
DM7211
Dual-In-Line and Flat Packages
INPUT
Vee
INPUT
INPUT
5
A
INPUT
STROBE* OUTPUT
11
10
STROBE
r-_ _ _-I~:~~~~'ON
INPUT
o
OUTPUT
1+-++-+....1
INPUT
INPUT
INPUT
1
2
3
NC
GND
*A LogtCBI1 Oft the strobe mput causes the output 'to 90 the Logical 1 date
A LO!!llcal 0 on the strobe mput allows mformatlon to be routed through thB devICe
DM7210
Vee
1,4
A
13
INPUTl
INPUre
111
12
INPUTS
1.0
INPUre
I
9
'"""--
I
OUTPUT
•
"-SELECTION
INPUTS
roo-
OUTPUT
DATA INPUTS
1111
1
2
3
INPUT 0
14
INPUT 1
16
INPUT 2
16
INPUT 3
r
GND
1-145
......
N
00
absolute maximum ratings
::E
Q
...
,...
Supply Voltage
Input Voltage
Fanout
Storage Temperature Range
Operating Temperature Range
.......
N
DM7210, DM7211
DM8210, DM8211
Lead Temperature (soldering, 10 seel
::E
Q
...
o
N
00
electrical characteristics
::E
Q
.......
o
(Note 11
PARAMETER
...,...
N
Logical "1" Input Voltage
::E
Q
LogIcal "0" I nput Voltage
Logical "1" Output Voltage
CONDITION
OM7210,OM7211
Vee = 4 5V
OM8210,OM8211
Vee = 4.75V
OM721O,OM7211
Vee =45V
OM8210,OM8211
Vee = 4.75V
OM7210,OM7211
Vee = 4.5V
OM8210,DM8211
Vee - 4.75V
DM7210,DM7211
Vee = 4.5V
DM8210,DM8211
Vee=475V
LogIcal" 1" I nput Current
(Allinputsl
DM7210,DM7211
Vee = 5.5V
DM8210,DM8211
Vee = 5.25V
Logical" 1" I nput Current
(Allinputsl
DM7210,DM7211
Vee = 5.5V
OM8210,DM8211
Vee = 5.25V
LogIcal "0" Input Current
(Allinputsl
DM7210,DM7211
Vee = 5.5V
DM8210,DM8211
Vee - 5.2SV
Input Clamp DIode
(Allinputsl
DM7210,DM7211
Vee = 5.5V
DM8210,DM8211
Vee = 5.25V
DM7210,DM7211
Vee = 5.5V
DM8210,DM8211
Vee = 5.25V
DM7210,DM7211
Vee = 5.5V
DM8210,DM8211
Vee = 5.25V
Logical "0" Output Voltage
Output Short CirCUIt Current
Power Supply Current
(All Inputs GND)
7V
5.5V
10
_65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
MIN TYP MAX
0.8
V
V
2.4
0.4
lOUT = 16 mA
Y'N = 2.4V
40
Y'N = S.5V
1
V
j.tA
mA
Y'N =0.4V
-1.0 -1.6
mA
l'N = -12 mA, TA = 25°C
-1.0 -1.5
V
V OUT = 0
-20
-55
mA
-18
20
33
mA
PropagatIon Delay to a LogIcal "0"
From Data Input to Output, tpdO
Vee = 5.0V, TA = 25°C
10
21
30
ns
PropagatIon Delay to a LogIcal "0"
From Strobe Input to Output
Vee =50V,T A = 25°C
10
19
27
ns
Propagation Delay to a LogIcal "1"
From Data Input to Output, t pd ,
Vee = 5.0V, T A = 25°C
10
23
32
ns
Propagation Delay to a LogIcal" 1"
From Strobe Input to Output
Vee = 5.0V, T A = 25°C
10
21
30
ns
Data SelectIon Settling Time From
0"1 TransItion on A, B, C h.d
Vee = 5.0V, TA = 25°C
15
31
43
ns
Data Selection Settling Time From
1"'0 TransitIon on A, B, C (too)
Vee = 5 OV, TA = 25°C
15
31
42
ns
Note 1: Unless otherWise specified the min-max limits apply across the -55°C to + 125°C temperature
range for the DM7210 and DM7211 and across the OOC to 70°C temperature range for the DM8210
and DM8211 TYPlcals are gIven for Vee = 5 OV and 2Soe.
1·146
V
2.0
lOUT = -400j.tA
UNITS
c
3:
.....
logic table
N
....
o
.......
c
SELECTION INPUTS
STROBE
3:
DATA INPUTS
C
B
A
10M 7211/0M8211
ONLY)
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
1
1
0
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
0
0
0
0
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
0
0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
1
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
0
1
1
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
0
1
1
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
0
1
1
1
1
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
X
X
X
1
X
X
X
X
X
X
X
X
1
x=
1
1
1
1
1
00
N
OUTPUT
....
o
1
c
3:
.....
1
N
....
....
1
.......
c
3:
1
00
........N
1
o
"Don't Care" Condition
typical application
ONE-Of-SIXTEEN CHANNEL
DIGITAL DATA MULTIPLEXER
15 14 13 12 11 10
CLOCK
DM753J/DM8533
OR
OM7563/DM8563
9
8
16543210
OM1210/
OM8210
OM12101
OM8210
OUTPUT
OUTPUT
-------,
I
I
I
I
I
L ____________ J
OUTPUT
1-147
Series 54/74
DM7214/DM8214 TRI-STATE®dual 4:1 multiplexer
general description
The DM7214/DM8214 IS a TRI-STATE dual fourline to one-line multiplexer. The device acts as a
double-pole four-throw switch. One data line is
selected from each of two four-line inputs. Two
SELECT lines determine which of the four inputs
is chosen; however the same input of both four-line
selections will be selected. TRI-STATE logic allows
for the added feature that the outputs of the device can be tied to outputs of similar devices and
connected to a common bus-line. Nominal TTL
outputs cannot be connected due to the lowimpedance logical "1" output current which one
device would have to sink from the other. If,
however, on all but one of the connected devices
both the upper and lower output transistors are
turned off, then the one remaining device in the
normal low-impedance state will have to supply to
or sink from the other devices only a small amount
of leakage current. This is exactly what occurs on
the DM7214/DM8214. The STROBE Input is used
to place the output in this unique high-impedance
state.
features
•
Pin-for-pin compatible with SN54153/SN74153
•
Organized for party-line systems
•
•
Up to 128 devices can be connected to a
common bus-line
Propagation delay 20 ns typical
•
Power dissipation 170 mW typical
•
Input diode clamps
•
Serie5 54174 compatible.
The DM7214 is characterized for operation over
the full military temperature range of -55°C to
+125°C; the DM8214 is characterized for operation from O°C to 70°C.
logic and connection diagrams
Dual-In-Line and Flat Package
Vee
STAOBE
A
OUTPUT
21l
ADDllfSS
"
OUTPUT
"
STROBEB~OUTPUT
lG
ADDRESS
1Y
TOP VIEW
Analogous to DP4T Switch
OUTPUT
"
--0
--0
INPUTS
truth table
DATA INPUTS
ADDRESS INPUTS
1-148
y
X
1
HI-Z
x
0
0
0
0
0
0
0
0
0
CO
Cl
X
0
0
X
0
0
X
0
X
X
x
x
0
0
1
X
X
0
X
X
1
1
1
0
0
X
X
X
X
X
X
0
X
X
X
X
1
X
X
0
X
X
1
1
1
1
1
DON T CARE
1
X
X
X
C2
OUTPUT
G
A
1
x-
STROBE
B
C3
1
0
1
0
1
0
1
OUTPUTS
absolute maximum ratings
(Note 1)
7V
5.5V
5.5V
Vee
Input Voltage
Output Voltage
Time that two bus-connected dev,ces may
be in opposite low impedance states
simultaneously
(5% Duty Cycle)
Storage Temperature Range
Operating Temperature Range DM7214
DM8214
Lead Temperature (Soldering, 10 sec)
electrical characteristics
Indefinitely
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
(Note 2)
PARAMETER
CONDITIONS
Input Diode Clamp Voltage
MIN
TYP
Vee: 5.0V, I'N: -12 mA
T A : 25°C
Logical "I" Input Voltage
DM7214
DM8214
Vee: 4.5V
Vee - 4.75V
Logical "0" Input Voltage
DM7214
DM8214
Vee: 4.5V
Vee - 4.75V
Logical "I" Output Voltage
DM7214
DM8214
Vee: 4.5V
Vec 4.75V
lOUT: -2.0 mA
lOUT -5.2mA
Logical "0" Output Voltage
DM7214
DM8214
Vee: 4.5V
Vee - 4.75V
lOUT: 16 mA
Logical "I" Input Current
DM7214
DM8214
Vee: 5.5V
Vec - 5.25V
V'N: 2.4V
MAX
UNITS
-1.5
V
2.0
V
0.8
2.4
3.2
0.2
V
V
0.4
40
J1.A
V'N: 5.5V
1.0
mA
-1.6
mA
Logical "0" Input Current
DM7214
DM8214
Vee: 5.5V
Vee - 5.25V
V'N: O.4V
Short-Circuit Output Current
(Note 3)
DM7214
DM8214
Vee: 5.5V
Vee - 5.25V
V OUT : OV
-20
-18
-55
-57
mA
Output Disable Current
(Hi-Z Output State)
DM7214
DM8214
Vee: 5.5V
Vee - 5.25V
V OUT : 0.4V to 2.4V --40
V OUT - O.4V to 2.4V --40
40
40
J1.A
Supply Current
DM7214
DM8214
Vee: 5.5V
Vec - 5.25V
All inputs at GND
34
34
56
65
mA
ns
Propagation Delay from Data to
Output, t pd'
tpdQ
Propagation Delay from Address
to Output, tpd,
tpdQ
Vee: 5.0V. T A: 25°C, CL
:
50 pF
15
12
23
18
Vec: 5.0V, T A: 25°C, CL
:
50 pF
20
20
34
34
ns
Delay from Log,cal "I" to Hi-Z
Output State, t, H
Vee: 5.0V, T A
:
25°C
5
10
ns
Delay from Logical "0" to Hi-Z
Output State, tOH
Vee: 5.0V, T A
:
25°C
15
23
ns
Delay from Hi-Z to Logical "I"
Output State, t H'
Vee: 5.0V, T A
:
.25°C,
50 pF
12
18
ns
Delay from Hi-Z to Logical "0"
Output State, t HQ
Vec: 5.0V, T A
:
25°C, CL
50 pF
14
21
ns
CL:
:
0
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electncal Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature
range for the DM7214 and across the OOC to 70°C range for the DM8214. All typicals are given
for Vee: 5.0V and T A : 25°e.
Note 3: Only one output at a time should be shorted.
1-149
en
,PO
N
00
Series 54/74
::IE
Q
......
en
po
N
.....
DM7219/DM8219 TRI-STATE®
16-line to one-line multiplexer
::IE
Q
general description
features
The DM7219/DM8219 multiplexes sixteen digital
lines to one output. A four-bit code determines
the particular one-of-sixteen inputs which is routed
to the output. The data is inverted from input to
output. A strobe over-ride places the output in the
high-impedance state.
• Typical propagation delay
10 ns
• Typical power dissipation
225mW
• Series 54/74 compatible
logic and connection diagrams
OUTPUT
•
A
1jlf
rtr
l
Ii
rlr
11
II
1. ~ ~ [5v~ 1.. l~ 1l
II
III
III
II
Or rl
D
c
(
~
;:.
,
STROB
(eMAIL
"
IL~ IL~
L~ L~
~'-'---'-'----~--~"--~~--~"----"~--'~'~yr-~~--~~---'~"---'~"--~'''~-='''~-='''~-=''~$..~'--~.~--~
DATA
INPUTS
Dual-I n·lin. and Flat Pa.kaga
DATA
~____~D~AT~AI~NP~UT~S______, ~
I..
ri
1
E,
E"
E
E,•
E.
,
21
"
Z3
.
E.
3
20
"
18
17
En
E"
E"
E"
E,
E,
E.
E,
• , ,
1
8
,16
DATA INPUTS
15
W
8
13
10
:+
11
112
t S~~::T t
OUTPUT
TOP VIEW
,.
A
E"
' -_ _ _ _ _ _-----',STROBE
1·150
•
D
C
GND
DATA
SElECT
(BINARYI
absolute maximum ratings (Note 11
operating conditions
MIN
Supply Voltage
I nput Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
7V
5.5V
_65°C to +150°C
300°C
electrical characteristics
CONDITIONS
Logical "1" Input Voltage
Vee: Min
Logical "0" Input Voltage
Vee: Min
DM7219
5iiiiii2i9
UNITS
MAX
4.5
4.75
5.5
5.25
v
v
-55
0
+125
70
°c
°c
(Note 21
PARAMETER
Logical "1" Output Voltage
Supply Voltage (V CCI
DM7219
DM8219
Temperature ITAI
DM7219
DM8219
Vee: Min
V'N(1): 2.0V
V IN (0) : 0.8V
MIN
TYP
MAX
V
2.0
0.8
lOUT: -2.0 mA
lOUT: -5.2 mA
Logical "0" Output Voltage
Vee: Min, V(N(1): 2V, V'N(O): 0.8V
IOUT:+16 mA
Third State Output Current
Vee: Max, Vo : O.4V to 2.4V
Logical "1" Input Current
Vee: Max, V ,N : 2.4V
V ,N : 5 5V
Logical "0" Input Current
Vee: Max, V ,N : 0 4V
UNITS
V
V
2.4
0.4
±40
-40
V
IlA
40
10
p.A
mA
-1.6
mA
-100
-100
mA
mA
Vee: Max, V'N: 4 5V
68
mA
Input Diode Clamp Voltage
Vee: Min, liN: -12 mA
T A : 25°C
-15
Propagation Delay to a Logical "0"
from Data Select Inputs to Output,
Vee: 5.0V
T A : 25°C
DM7219
Output Short CircUit Current
DM8219
Vee: Max, V OUT : OV
Supply Current
CL
-30
-28
:
RL :
50 pF
400n
0
V'
22
33
ns
21
35
ns
14
ns
20
ns
10
ns
tpdO
Propagation Delay to a Logical "1"
from Data Select Inputs to Output,
tpd,
Vee: 5 OV
T A : 25°C
Propagation Delay to a Logical "0"
from Data Inputs to Output, tpdO
Vee: 50V
T A : 25°C
Propagation Delay to a Logical "1"
from Data I nputs to Output, tpd1
Vee: 5OV
T A : 25°C
Delay from Strobe to High Imped·
ance State (from Logical "1" Level),
Vee: 5OV
T A : 25°C
8.5
13
50
t'H
Delay from Strobe to High I mped·
ance State (from Logical "0" Level),
Vee: 5OV
T A : 25°C
21
30
ns
Vee: 5OV
T A : 25°C
15
23
ns
Vee: 50V
T A : 25°C
17
27
ns
tOH
Delay from Strobe to Logical "1"
Level (from High Impedance Statel,
tH'
Delay from Strobe to Logical "0"
Level (from High Impedance Statel,
tHO
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherWise specified minImax limits apply across the _55°e to +125°e temperature range for the OM7219 and
across the O°C to 70 0 e range for the OM8219 All typlcals are given for Vee = 5 OV and TA = 25°e
Note 3: Only one output at a time should be shorted
1-151
...
en
N
00
truth table
:E
Q
......
en
...
OUTPUT
INPUTS
N
.....
:E
Q
0
C
B
A
STROBE
E.
E,
E,
E.
Eo
E.
E.
E,
Eo
Eo
E,.
E"
E..
E"
E,.
E"
W
X
x
x
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HI-Z
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
X
1
0
0
0
0
0
1
X
X
X
0
X
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
1
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
X
0
X
X
0
0
0
0
1
0
0
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
1
0
0
x
X
X
X
X
X
X
0
X
X
X
0
1
1
0
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
1
X
X
X
1
X
X
1
0
X
X
X
X
X
X
X
X
X
0
1
0
0
0
x
x
x
x
x
x
x
x
x
x
X
1
0
0
0
x
x
0
1
x
x
x
0
x
x
X
1
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
0
X
1
0
X
X
1
1
1
1
0
0
x
x
x
x
0
x
x
x
x
x
x
x
x
1
1
0
0
x
x
x
0
x
x
x
x
X
1
X
X
X
X
X
X
X
X
X
0
1
1
1
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
1
U
1
1
1
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
1
0
0
0
0
x
x
x
x
x
X
1
x
x
x
x
0
x
x
0
0
x
x
x
0
x
x
x
0
x
x
x
1
x
X
1
X
X
X
X
X
X
X
0
1
0
0
1
0
x
x
x
X
1
0
0
1
0
X
X
X
X
X
X
X
X
X
1
X
X
X
x
x
x
1
x
x
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
X
1
x
x
x
x
0
x
x
0
1
x
x
x
0
x
x
x
1
0
0
X
1
X
X
X
X
X
0
1
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
1
1
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
0
1
1
0
0
0
x
x
x
x
x
x
x
x
x
x
X
1
~
x
x
x
0
x
x
x
0
x
x
0
0
x
x
x
1
x
x
x
1
X
1
X
X
X
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
0
1
1
1
0
0
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
1
x
x
X
X
X
1
X
0
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
1
0
0
1-152
1
X
X
X
X
X
X
X
x
x
0
1
c
Series 54/74
3:
.....
N
N
o
.......
c
3:
DM7220/DM8220 parity generator and checker
00
N
general description
The DM7220/DM8220 is a monolithic integrated
circuit which can be used to both generate a parity
bit and check for parity. Nine inputs and a single
output are provided. When it is desired to generate
a parity bit, eight of the nine inputs are connected
to the eight data transmission lines. Depending
upon whether odd parity or even parity is desired
a logical 1 or a logical 0 is applied to the ninth
N
o
input. For a parity check, the output of the parity
generator (sending end) is connected to the ninth
input of the parity checker (receiver end). The
resulting output of the parity checker will remain
in one particular logic state unless a bit is "lost"
during transmission.
The device is fully compatible with other
Series 54/74 circuits.
schematic and connection diagrams
Dual-I n-Line and Flat Package
o
l· Vcc
OUTPlJT
X=A@B(t)C@O(t)EE>FG@H@P
typical application
If the control hne
IS a
logICal "0" the parity generator
will generate odd parity The panty checker will acknowledge the presence of an odd number of "''''$
(odd parity) With a logical "0" on Its output.
If the control hne IS a logICal "1" the panty generator
will generate even panty. The parity checker will acknowledge the presence of an even number of "1"'s
(even panty) With a logical "," on Its output
1·153
o
N
N
00
absolute maximum ratings
:E
c
"o
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range DM7220
DM8220
Lead Temperature (Soldering, 10 sec.)
N
N
.....
:E
c
electrical characteristics
PARAMETER
7V
5.5V
10
_65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
(Note ')
CONDITIONS
Logical "," Input Voltage
DM7220
DM8220
Vee = 4.5V
Vee = 4.75V
Logical "0" Input Voltage
DM7220
DM8220
Vee = 4.5V
Vee - 4.75V
Logical "," Output Voltage
DM7220
DM8220
Vee = 4.5V
Vee = 4.75V
lOUT = -400 IJ.A
Logical "0" Output Voltage
DM7220
DM8220
Vee = 4.5V
Vee = 4.75V
IOUT= '6mA
Logical "," Input Current
DM7220
DM8220
Vee = 5.5V
Vee - 5.25V
V IN = 2.4V
Input Diode Clamp Voltage
DM7220
DM8220
Vee = 5.5V
Vee = 5.25V
Logical "," Input Current
DM7220
DM8220
Vee = 5.5V
Vee = 5.25V
V IN = 5.5V
Logical "0" Input Current
DM7220
DM8220
Vee = 5.5V
V ee - 5.25V
V IN =0.4V
Output Short Circuit Current
DM7220. Vee= 5.5V
DM8220
Vee = 5.25V
V OUT = OV
Power Supply Current
DM7220
DM8220
MIN
TYP
0.8
0.4
40
-I.'
-1.0
TA = 25°C
Propagation Delay to Logical "0", tpdO
Inputs A, B, C, D, E, F, G, H
Vee = 5.0V
Co = 50pF
TA = 25°C
Propagation Delay to Logical ",", tpd1
Input P
Vee = 5.0V
Co = 50 pF
TA = 25°C
Propagation Delay to Logical "0", tpdO
Input P
Vee = 5.0V
Co = 50 pF
TA = 25°C
F.O. = 10
F.O. ='0
F.O. ='0
F.O. ='0
-'.5
V
IJ.A
V
'.0
mA
-'.6
mA
-55
-57
mA
mA
26
35
mA
36
58
ns
32
52
ns
B
21
35
ns
7
'4
25
ns
-20
-18
Vee = 5.5V
Vee = 5.25V
Vee = 5.0V
Co = 50 pF
V
V
2.4
liN =-'2mA
TA = 25°C
UNITS
V
2.0
Propagation Delay to Logical ",", tpd1
Inputs A, B, C, D, E, F, G, H
15
"
Note 1: Unle.. otherwise specified the min-max limits apply across the -55°C to +125°C temperatura
range for the OM 7220 and across the OOc to 70°C temperature range for the OM8220. All typicals ara
given for Vee = 5.0V and T A = 25°C.
1-154
MAX
c
illS
3:
.....
Series 54/74
N
N
W
......
c
3:
00
N
N
W
DM7223/DM8223 1-line to 8-line demultiplexer
general description
The DM7223/DM8223 1-line to 8-line demultiplexer utilizes Series 54n4 compatible circuitry to
demultiplex a data train to one of eight outputs.
These eight outputs are capable of driving 10
standard TTL loads each. Three address lines
determine which output receives the data train.
When the data input is a logical "0" only the
addressed output will be a logical "0". When the
data input is a logical "1", all outputs, and therefore the addressed output, will be logical "1 's".
connection diagram
logic table
o
Dual-In-Uno Package
ADDRESS
DATA
0
0
0
0
0
0
0
0
1
ADDRESS
INPUTS
C
B
A
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
OUTPUTS
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
2
1
1
0
1
1
1
1
1
1
3
4
5
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
6
1
1
1
1
1
1
0
1
1
7
1
1
1
1
1
1
1
0
1
x = Don't Care
OUTPUTS
*Do not IIIIb COnMftlDn to PIIII 10 or 11
TOP VIEW
typical application
Digital Data Demultiploxer (1 Line to 64 Lines)
ADDRESSIN'UTS
DATAI.PUT
I
• 0111:223
A
a
1 2
....-----+4-+--IJ
III
III
1
A
•
C
1JM12Z3
DATA
I
I
"
rll
1 ABC
II1II1223
DATA
1
A
I
I
C
OMl223
DATA
3
4
DATA
6
& 1
Pt..:::::=======::::::;-------,
I I
Til
III
I' '~DA"I I' ',.:",·'' 1 I' ' ':",·'' 1 I' ·..:",,·"'1
32
.
41
"
.
1-155
C")
N
N
00
~
Q
"N
C")
N
~
~
Q
absolute maximum ratings
(Note 1)
Supply Voltage
I nput Voltage
Fan Out
Operating Temperature Range
DM7223
DM8223
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
7V
5.5V
10
_55°C to +125°C
O°C to 70°C
-65°C to +150°C
300°C
(Note 2)
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "I" Input Voltage
DM7223
DM8223
Vee = 4.5V
Vee -4.75V
Logical "0" Input Voltage
DM7223
DM8223
Vee = 4.5V
V ee -4.75V
Logical "I" Output Voltage
DM7223
DM8223
V ee =4.5V
Vee =4.75V
lOUT = -400 jlA
Logical "0" Output Voltage
DM7223
DM8223
Vee = 4.5V
Vee - 4.75V
lOUT = 16mA
Logical "I" Input Current
DM7223
DM8223
Vee = 5.5V
Vee - 5.25V
Y,N = 2.4V
40
p.A
DM7223
DM8223
Vee = 5.5V
V ee =5.25V
Y'N = 5.5V
1
mA
Logical "0" I nput Current
DM7223
DM8223
V ee =5.5V
Vee -5.25V
Y,N = O.4V
-1.6
mA
Output Short Circuit Current
(Note 3)
DM7223
DM8223
Vee = 5.5V
Vee -5.25V
V OUT = OV
Supply Current
DM7223
DM8223
Vee = 5.5V
Vee - 5.25V
Input Clamp Voltage
DM7223
DM8223
V ee =5.5V
Vee -5.25V
V
2.0
0.8
2.4
V
0.4
-1.0
-20
-18
l'N = -12 mA
V
V
-32
-55
-57
mA
mA
28
41
mA
-1.0
-1.5
V
Propagation Delay to a Logical "0"
Vee = 5.0V
TA = 25°C
COUT = 50 pF, F.O. = 10
12
24
35
ns
Propagation Delay to a Logical "I"
Vee=5.0V
TA = 25°C
COUT = 50 pF, F.O. = 10
12
26
35
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temper8ture Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electncal Characteristics" prOVides conditions
for actual deVice operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM7223 and across the rfc to 70'C range for the DM8223. All typIcal. are gIven for
VCC = 5.0V and TA = 25°C.
Note 3: Only one output at a tIme should be shorted.
1-156
r
c
3:
....N
Series 54/74
W
o
®
.......
.
c
3:
OM7230/0M8230 TRI-STATE demultiplexer
general description
features
The DM7230/DM8230 demultiplexer is another
device in National's TRI-STATE logic family_
•
•
•
•
Series 54/74 compatible
20 ns propagation delay
Data complement capability
Very low output impedance-high dnve
capability
• Separate Input disable controls
• High-impedance output state which allows many
outputs to be connected to a common bus-line.
Digital signals applied to two input lines can be
routed to two-of-four output lines depending upon
the logic on the Address inputs. Outputs can be
directly connected to other similar outputs for use
in bus-organized systems.
00
N
W
o
logic and connection diagrams
.
Dual-In-Line and Flat Package
c~u:~~ c·.......:..--L.J
OAT:
AJlDRUlDIIAILE DISAIU
o......-::--r,
"'cc
"
•
A
OATA
DATA
COIM'lE-COMPU-
•
A
. . .TI • • TA
o
ADDRESS
.~~=m:t~
.
ADDRESS
DISAIL:
O"----HH>c-----'
logic table
DATA
COMP
0
0
I
0
•
•
DATA
COMP
,
,
x
x
x
x
,
0
0
0
,
0
I
0
0
I
,
,,
0
0
,
0
1
0
1
0
1
0
1
0
X
X
X
1
X
X
X
x
X
•
X
X
x
x
x
x
x
x
x
x
X
X
x
X
X
X
X
X
x
X
X
X
x
X
x
x
X
X
0
1
0
1
0
1
0
1
0
0
x
x
x
x
x
X
X
X
X
X
1
1
0
0
I
I
0
x
x
0
X
X
X
X
X
X
X
X
1
I
X
X
X
X
X
X
•
0
0
,
,
X
,.
ADOR£SSA
"
0
0
0
0
0
0
0
0
1
1
1
I
x
x
x
I
I
I
X
X
X
X
X
X
x
x
0
X
0
X
X
X
X
X
X
X
,
0
0
I
I
I
x
x
X
X
X
X
X
X
x
x
X
X
X
X
X
X
0
x
x
1
0
1
0
X
X
X
X
X
X
x
x
x
x
X
X
X
X
X
X
,
0
I
X
"x
0
,
,, ,
1
,.
ADDRESS 8
x
x
x
x
0
0
0
X
X
,
X
x
x
X
0
0
0
0
0
0
0
0
X
0
0
0
0
,,
,
,, ,
,
, ,
,
0
0
0
1
0
1
1
1
1
X
,
X
. •,
OlS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,,
,,
,
I
1
I
1
I
1
1
1
1
1
DIS
,
1
1
1
1
1
1
0
,,
,,
,
,
0
0
OUT
1
1
0
1
I
1
1
1
1
0
,
1
0
1
I
1
I
0
0
0
0
0
1
,
1
1
1
1
1
,
,,
H"
OUT
3
, ,,
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
,
OUT
,
,,
,
, ,
1
OUT
,
,
,,
,
,
I
I
I
I
I
0
1
1
0
1
,
1
I
1
1
1
1
H, ,
,
I
,
,
I
I
1
1
,, ,,
1
,,
,
0
1
I
1
1
0
1
1
0
1
,,
,
, ,,
,,
,
I
I
0
I
I
0
I
I
1
I
I
I
,
,
I
,
,
0
0
H,' H.,
1-157
o('I)
absolute maximum ratings
N
CO
7V
55V
55V
Supply Voltage
Input Voltage
Output Voltage
Time that two bus-connected
deviceS may be In oPPosite
low Impedance states simultaneously
(5% duty cycle)
:E
Q
......
o('I)
....N
Lead Temperature (Soldering, 10 sec)
Q
Logical "0" Input Vattage
Logta'''''' OutPUt Voltage
QM7230
V cc =4SV
UMO'.U
Vee =
OM7230
Vee=45V
"a"
Input Current
LogIC,1 ' 1" Input Current
Logical "," Input Current
MIN
TYP
DM7230
OMo,30
DM7230
DM8230
UNITS
V
20
08
;;;:rii;i~~"~i<-~----t----i;~"'~~-::-::;;~"~IT-V, :~~~: =~;~A
OM 7230
MAX
f 1:31
CC ' 4 / . ,
OM7230
logical "0" Output Voltage OM8230
LOQlcal
(Note 1)
CONDITIONS
PARAMETER
logical .. ,.. Input VoUage
-55°C to +125°C
oOe to +70°C
300°C
Indefinite
electrical characteristics
:E
_65°C to +l50°C
Storage Temperature Range
()peratlng Temperature Range
OM 7230
OM8230
24
vee'" 4 5V
Vee 475V lOUT'" 16 mA
Vee"55V V "04V
Vee":J;t:»v IN
Dlsablemputs
All other Inputs
V
V
35
02
04
V
-20
-10
-32
-16
mA
mA
80
"A
"A
Vee=55V V "'24V
Vee = :JL:JV IN
Olsable mputs
All other mputs
40
Vee" 5 5V V
55V
Vee" 5 z'::N IN ~
10
mA
OMo230
°RiMii;7r,2~30r_ _t-_-;Vv;>c",C"':i5~5V~v
cc . . ."
Vo = 0 4V to 2 4V
-40
40
.A
Output Short Current
INoie 21
DM7230
V e" 55V
Vo ~ DOV
OM8230
Vee' •
-30
-28
-70
mA
Supply Current
OM7230
OMaL.su
Vee"55V V =50V
Vee =:J L:»V IN
75
mA
Ou4-0t Disable Current
2>V
Input Diode Clamp Voltage
Vee" 50V. T.'" 25 C
liN = -12mA
ProPillJiltlon Delay to LOgical ","
from Data or Complement Input. tpd1
Vec =50V.T."'25C
C L =50pF
Nomnvertlng
Invertmg
PrOPillJiltlon Delav to LOgical "0"
from Data or Complement Input. tpdO
C L "'50pF
Propagation Delav to Logical "," from
Address Input, Ipd1 INote 3)
Propagation Delav to Logical "0" from
Address Input, tpdO (Note 3)
V ee =50V.T.=25°C
C L =50pF
PrOpagation Delay to lOgical "1" from
Olsable Input, Ipdt (Note 4)
Vee = SOY. TA = 25°C
C L " 50pF
PropagatIon Delay to logical "0" from
Olsable Input, tpdO (Note 41
Vee "'SOV. TA '" 25°C
48
-15
24
36
Nonmvertm9 or Inverting
18
26
Vee = SOY. T. = 25"C
C L " 50pF
20
36
n,
n,
20
30
n,
13
25
n,
16
25
n,
7
14
27
n,
n,
23
n,
n,
Vee =50V.T.=25C
C L = 50pF
15
tOH
Impedance State (Note 51. lHI
tHO
Vee = SOY, T. = 2s"C
CL .. 50 pF
15
18
27
Note 1: MinImax values apply across the -5frC to +126°e temperature range for the DM7230 and across the O"C to 70"C
range for the DM8230 unless otherwise specified. TYPlcals are given for TA 26"C and Vee = 5.0V.
Note 2: Only one output at a tune snoula De snon CirCUited.
Note 3: The only conditions under which a tpdO from the Address Inputs can be observed IS when an output goes from being
nonselected to being selected and the information being routed to that output is a logical "0 " If the Information had been a
logical "1," no change would have occurred and no measurement could have been made. Similarly, the only time a tpd1 from
the Address Inputs can be observed, IS when an output does from being selected to being nonselected and the Information that
had been routed to that output was a logical "0." If the information had been a logical "1:' no change would have occurred
and no measurement could have been made.
Note 4: Information In Note 3 concerning tpdO and tpd1 from the address inputs are applicable here also.
Nota 5: All delays mvolvlfig transitions to or from the High Impedance state are measured With respect to the Disable Inputs.
For example, with A information at a logical "0" and Disable 8 at a logical "1" the selected output Will go from a logical "0"
to the High Impedance state some time, tOH. after Disable A has gone from a logical "0" to a logical "1 ..
II:
1-158
n,
n,
13
20
Delay 'rom Disable Input to High
Impedance State (Note 5), tlH
Delav from Olsable Input to Low
V
c
3:
.....
mode of operation
N
COMPLEMENT AND DATA INPUTS
When Complement A is a logical "1", Data A will
appear inverted at the output. When Complement A is a logical "0", Data A will appear noninverted at the output.
This function is accomplished on the chip through
the use of a two-input exclusive-OR gate with
Complement A and Data A as the two inputs.
Therefore, the A information that is routed to the
outputs is actually (Complement A Gl Data A).
That this is the case may be verified by examining
the logic diagram.
The two inputs of this exclusive-OR gate have
identical characteristics, allowing the functions of
these two inputs to be reversed. Also the propagation delay from either input to the output will be
the same. This is also true for the Complement B
and Data B inputs.
ADDRESS INPUTS
The Address A inputs select to which of the four
outputs A information will be routed. The same is
true for the Address B inputs and B information.
If A and B information are both routed to the
same output simultaneously, that output will be a
logical "0" if either the A or B information is a
logical "0". All outputs which are not selected for
W
either A or B information will be in the logical "1"
state.
DISABLE INPIJTS
The Disable inputs are similar to higher order
Address inputs in that when Disable A is a logical
"1", A information is not routed to any output.
All four outputs are nonselected for A information. The same is true for Disable Band B information. The Disable inputs have the additional feature that when both Disable A and Disable B are a
logical "1" all outputs go to the High Impedance
state. When multiple outputs are connected to a
bus line, only one device at a time can be in the
normal low impedance state. All others should be
gated into the high Impedance state (Figure 1).
The selected device therefore has the normal TTL
low impedance output providing good capacitive
drive capability and waveform integrity especially
during the transition from the logical "0" to logical "1" state. The other outputs-in the high impedance state-take only a small amount of leakage current from the low impedance outputs.
Since the logical "1" output current of the selected device is 13 times that of a conventional
Series 54/74 device (5.2 mA vs 400 /-LA), the output is easily able to supply that leakage current to
as many as 127 other DM7230/DM8230's and still
have available drive for the bus-line. (Figure 2)
BUS LINES
1Z01tA FOR DRIVING OTHER LPTTL INPUTS
~
ONE OF FOUR
OUTPUTS
o
M
SELECTED AS
DRIVING ---.
DEVICE
•
2
J
SELECTED AS
DRIVING
52mA
DEVICE
o
o
M
•
20Jl.Ax 45 OUTPUTS".9 rnA
LEAKAGE CURRENT
GATED INTO
THIRD STATE
2
J
o
o
M
GATED INTO
8
THIRD STATE ----.
GATED INTO
THIRD STATE
2
J
o
Figure 1
20pA LEAKAGE CURRENT
Figure 2
1-159
o
......
c
3:
00
N
W
o
·CO
°co
CON
NCO
CO:::E
:::EO
0 ......
...... CO
CON
°co
N,....
""':::E
:::EO
o
...
CO
N
CO
:::E
o
......
...
CO
,....
N
:::E
o
Series 54/74
DM7280/DM8280(S8280/N8280) presettable decade counter
DM72811DM8281 (S82811N8281) presettable binary counter
DM7288/DM8288 (S8288/N8288) presettable -:-12 counter
general description
The counters in this series are four-bit monolithic
subsystems containing a divide-by-two counter
with one clock input and a second counter with a
second clock input. The two clock inputs and the
other logic functions provided will implement a
wide variety of counter and storage register functions.
•
Two clock inputs for additional flexibility
•
Strobed parallel·entry capability
•
Reset inputs common to all stages
•
Typical toggle rates to 45 MHz
•
Typical power dissipation of 130 mW
features
•
Direct·coupled stages
•
•
Available in cavity or molded DIP
Series 54/74 compatible
connection diagrams
(Dual·ln·Line Package.)
DM7281!DM8281
(DM54177!DM74177)
DM7280!DM8280
(DM54176!DM74176)
DM7288!DM8288
1-160
absolute maximum ratings
Supply Voltage
Input Voltage
Operating Temperature Range
DM7280, DM7281, DM7288
DM8280, DM8281, DM8288
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
_55°C to +125°C
O°C to +70°C
_65°C to +15d'C
300°C
(Notes 1, 2)
LIMITS
CHARACTERISTICS
MIN
"1" Output Voltage(3) (4)
7V
5.5V
TV.
CLOCK
CLOCK
2
DATA
INPUTS
RESET
475V
50V
475V
08V
08V
08V
20V
20V
20V
20V
20V
20V
Output A
Output A
Output A
O°C
+25°C
+75°C
475V
50V
475V
08V
D,BV
08V
08V
O.BV
08V
o 8V
Output A
Output A
Output A
mA
mA
mA
mA
mA
mA
mA
mA
+25°C
525V
525V
04V
+25°C
+25°C
+25°C
525V
525V
pll
pA
pA
pA
pA
pA
+75°C
+7SoC
+75°C
+7SoC
+7SoC
+75°C
50V
50V
50V
5.0V
50V
50V
25
25
"'
ns
+2SoC
+25°C
50V
50V
64mA
25
25
ns
ns
+25°C
+25°C
50V
50V
64 mA
35
ns
+25°C
50V
64mA
Vee
V
V
V
O°C
+25°C
+75°C
04
04
04
V
V
V
-16
-12
-30
-28
-32
-16
-32
-16
25
25
75
50
75
75
26
28
26
"0" Output Voltage(31 (5)
DATA
STROBE
TEMP
MAX
UNITS
1
O.BV
08V
OUTPUTS
-200J,J.A
-200pA
-200/lA
64mA
64mA
64mA
"0" Input Current
Data Strobe
Data Inputs
Re'let (DM82BO, DM8281i
Reset (OMB28S)
Clock 1 (DM8280, DM8281)
Clock 1 (DM8288)
Clock 2 (DM8280)
Clock 2 (DM8281, DM8288)
-01
-01
-01
-01
-01
-01
-01
-01
+2SoC
+25°C
+2SoC
+2SoC
04V
04V
04V
04V
525V
525V
04V
04V
Data Input
Reset (DM8280, DM8281)
Reset (DM8288)
Clock,
Clock 2
45V
45V
45V
45V
45V
45V
Clock Mode TON Delay
Bit A
Bit B,C, D
Clock Mode T OFF Delay
Bit A
Bit B, C, 0
Data/Strobe TON Delay
Bit A, B, C, D
Data/Strobe T OFF Delay
45
Bit A, B, C, D
20
Toggle Rate
45
35
Clock Mode SWitching Test(6l
Output Fall Time
130
Power Consumption
ns
+25°C
50V
6AmA
MHz
MHz
+25°C
+25°C
50V
5.0V
6.4mA
64mA
~
ns
+25°C
50V
50
nA
+2SoC
475V
194
mW
+25°C
525V
V
V
V
+25°C
+2SoC
+2SoC
50V
50V
50V
lOrnA
mA
+25°C
5.0V
OV
pF
+2SoC
50V
Pulse
Pulse
OV
OV
100 pF
OV
Input Voltage Rating
55
55
55
Data Strobe
Data Inputs
R,set
lOrnA
lOrnA
Output Short Circuit
-10
Current
-60
3.0
Input Capacitance
Strobe Memory Holding
Time with "1" to "0"
Clock or Output
TranSition
With no "1" to "0"
Clock or Output
TranSition
35
ns
+2SoC
50V
08V
20V
20V
Output A
17
35
ns
+ 2SoC
50V
20V
20V
20V
Output A
0.8V
20V
20V
Output A
20V
Output A
25
ns
+2SoC
5.0V
Reset Pulse Width
30
ns
+25°C
50V
Not8 1:
that are
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
OV
17
Strobe Pulse Width
20V
08V
.......
C
s::
o
"1" Input Current
Data Strobe
N
CO
CO
CO
N
CO
CO
04V
525V
525V
c
s::
......
All voltage and capacitance measurements are referenced to the ground terminal. Terminals
not specifically referenced are left electrically open.
Positive current flow is defined as the current into the referenced terminal.
Measurements of each output and the associated data input apply independently.
Output source current is supplied through a reSistor to ground.
Output sink current is supplied through a resistor to Vee.
The unit will tolerate any fall time on the clock due to the De design.
1·161
·CO
°co
CON
general description (cont.)
NCO
CO~
~C
C ......
°co
CON
N"",
""'~
~C
C
Counting is performed on the negative-going edge
of the clock pulse in all three types_ The divideby-two stages may be toggled at up to 45 MHz,
typical, approximately twice the maximum frequency of the Clock 2 input_
The DM7280!DM8280 counter operates as a divideby-two and divide-by-five counter with no external
connections_ When the A output is connected to
the Clock 2 input, it counts in the familiar BCD
mode_ The bi-quinary mode is obtained by connecting the 0 output to the Clock 1 input while
applying the clock to the Clock 2 input_ This
produces a square-wave output at f/10 on the A
output that is particularly useful in frequency
synthesizers_
...... CO
....
CO
N
CO
All three have parallel inputs which may be used
to set the corresponding outputs to desired states_
The parallel input logic levels are transferred to the
outputs when the strobe line is placed at the logical "0" level. A "0" on the reset line will place
all four outputs in the "0" state_
The DM7281/DM8281 is a 2,2,4,8 counter when
operated with two clock inputs and no external
connections_ It is a 2,4,8,16 counter when the A
output is connected to the Clock 2 input_ Thus,
it may be used as a divide-by-two, -eight, or
-sixteen counter.
~
C
......
....
CO
N
The register-storage function can be obtained by
using the strobed parallel-entry capability_ Data to
be stored is entered by the method indicated above
and retained on the outputs holding both clock
inputs at logical "1" (Ved- The register may be
reloaded with a new parallel entry and strobe
operation or cleared by the reset line_
The DM72881DM8288 consists of divide-by-two
and divide-by-six counters_ For divide-by-twelve
operation, output A is connected to the Clock 2
input_
"'~"
C
connection diagram
(Flat Package)
0,
BOUT
I"
13
c,
GND
12,
11
C2
,
AOUT
10
-
1
0,
8
r-
1
Dour
3
4
Vee
,
0
STROBE
6
COUT
I'
DM7280/DM8280, DM7281/DM8281, DM7288/DM8288
(Not applicable to DM54176W or DM54177WI
1-162
c
s:.....
Series 54/74
.j::Io
N
o
o
c
DM74200(SN74200) TRI-STATE®
256-bit random access memory
s:CO
DM8582 256-bit random
access memory (open collector)
CO
N
U1
genera I description
The DM74200 and the DM8582 are 256 x 1 read/
write random access. TTL memories which can be
used in applications ranging from scratch·pad to
main memories. Eight address inputs select the
proper bit·location and a Write-Enable input determines whether the read mode or write mode is
chosen. Three chip-enable inputs determ ine whether
the output' is in the conventional logical "1" or
logical "0" state or whether it is gated into the
off-state (DM8582) or the high-impedance state
DM74200. The off-state and high-impedance states
are usefu I when connection is made to a common
bus-line.
features
•
•
•
•
40 ns typical address access time, DM74200
50 ns typical address access time, DM8582
20 ns typical chip select access time
<2 mW/bit typical power dissipation
III
connection diagram
Dual-I n-line Package
DATA
VT'16
IN
14
15
WE
13
11
12
10
-
CE,
CE,
CE,
DATA
OUT
J:
TOPVIEW
truth table
CE
WE
H
H
H
OPERATION
OUTPUT
IDM8582}
Write
Logical "1"
(Open Collector)
OUTPUT
IDM74200}
High Z
o (Complement
Read
D {Complement
of Stored Data)
Do Nothing
Logical "1"
HlghZ
Do Nothmg
Logical" 1"
High Z
of Stored Data)
1-163
N
00
It)
absolute maximum ratings
(Note 1)
00
:!
c
o
o
N
~
.....
:!
c
Supply Voltage
Input Voltage
Output Voltage
7V
5.5V
5.5V
0°Cto+70°C
_65°C to +150°C
300°C
Operating Temperature Range DM74200, DM8582
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
f
electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
OM74200
OM8582
Vee
= 4.75V
Logical "0" Input Voltage
OM 74200
OM8582
Vee
= 4.75V
Logical "1" Output Voltage
OM74200
Vee
= 4.75V
, IsouReE
Logical "1" Output Current
OM8582
Vee
= 5.25V
,VOUT
= 5.5V
50
/lA
Logical "0" Output Voltage
OM74200
OM8582
Vee
= 4.75V
, ISINK
= 24 mA
004
V
Third State Output Current
DM74200
Vee
= 5.25V
, V OUT
= O.4V or 2AV
Logical "1" Input Current
OM74200
OM8582
Vee
= 5.25V
Y,N = 2.4V
'V'N = 5.5V
25
1.0
/lA
mA
Logical "0" I nput Current
OM74200
OM8582
Vee = 5.25V
,V ,N = O.4V
-1.0
mA
Output Short Circuit Current
(Note 3)
OM74200
Vee
= 5.25V
Supply Current
OM74200
OM8582
Vee
= 5.0V
Input Clamp Voltage
OM74200
OM8582
Vee = 4.75V ,1'N=-12mA
Output Ground Clamp Voltage
OM74200
lOUT
Address Access Time, tAA
OM8582
OM74200
Vee
V
2.0
0.8
,VOUT
= 10 mA
= OV
2.4
+40
-40
99
96
= 12 mA
= 5.0V
Chip Select Access Time, tAcs
V
\
-40
V
/lA
-80
mA
'130
125
mA
mA
-1.5
V
-1.5
V
50
40
ns
ns
20
ns
Chip Select Recovery Time, tRCS
TA
= 25°C
20
ns
Write Enable Pulsewidth, twp
= 300n
CL = 30 p~
25
ns
40
ns
Sense Recovery Time,
tSR
RL
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Ter'nperatl.4re Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual deVice operation.
Note 2: Unless otherwise specified mm/max limits apply across the O°C to 700 e range for the
OM74200 and OM8582. All typicals are given for Vee
Note 3: Only one output at a time should be shorted.
1-164
= 5.0V and T A = 25°e.
00
s:s:
..........
en en
......
Series 54/74
N'"
....... ""'"
00
s:S:
0000
......
enS!
OM7511/0M8511 dual gated 0 flip-flop
N-
OM7512/0M8512 dual gated master/slave JK/O flip-flop
O
OM7613/0M8613 quad gated 0 flip-flop
s:.....
general description
.......
...
0)
W
The OM7511/0M8511 is a dual gated 0 flip-flop.
Each flip-flop has its own clock, clear and two
gated inputs. Both gate inputs must be low to
enable data transfer to the output.
set to a logical "1" level will inhibit data entry
from the data input.
The OM7512/0M8512 is a dual flip-flop which
can operate in either a J, K mode or in a Ootype
mode. Both flip-flops operate from a common
clock and a common asynchronous clear but have
separate mode inputs so that one can operate as a
J, K. flip-flop while the other is operating as a
Ootype flip-flop~ (See truth table.)
• Additional "do:nothing" state
• Positive edge triggering
• Guaranteed operation
OM7511/0M8511
30MHz
20MHz
OM7512/0M8512
20MHz
OM7613/0M8613
• OM7512/DM8512 pin compatible with
OM75L 12/0M85L 12
• OM7613/0M8613 common clock and clear
o
s:00
....
0)
features
The OM7613/0M8613 is a quad gated 0 flip-flop
with direct clear and gated inputs. The latter if
W
III
connection diagrams
DM7512/DM8512
Dual-In-Line and Flat Packages
DM7511/DM8511
DuaHn-lina and Flat Packages
Vee
CLOCK
G2
CLOCK
G2
"
CLEAR
CLEAR
0,
GNO
M,
K,
Q,
0,
GNO
TOPVIEW
TOPVIEW
DM7613/DM8613
Dual-In-Line and Flat Packages
v~
Go
Do
Do
G,
0,
'"
CLEAR
CLOCK
GAo
DAo
U...
GB
DB
Oe
GND
TGP VIEW
1-165
absolute maximum ratings (Note
1)
Supply Voltage
Input Voltage
Output Voltage
7.0V
5.5V
5.5V
Storage Temperature Range
-65°e to +150o e
Lead Temperature (Soldering, 10 seconds)
3000 e
electrical characteristics
operating conditions
Supply Voltage (Vee)
DM7511, DM7512, DM7613
DM8511, DM8512, DM8613
Temperature (TA)
DM7511, DM7512, DM7613
DM8511, DM8512, DM8613
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
°e
--55
0
DM7511/DM8511 (Notes 2 and 3)
LIMITS
PARAMETER
CONDITIONS
MIN
TVP
MAX
20
UNITS
V
Logical "1" Input Voltage (V1Hl
Vee
=
Logical "'" Input Current (lIH)
Vee
Vee
= Max, VIN = 2 4V
=
Max, VIN '" 5 5V
40
10
Logical "0" Input Voltage (V1d
Vee
=
Min
08
v
Logical "0" Input Current (lId
Vce '" Max, VIN '" 0 4V
-16
mA
Input Clamp Voltage (V co)
Vee
-15
v
Logical "1" Output Voltage (V OH )
IOH '" -800IlA
=
Min
-10
Max, liN = -12 mA
"A
mA
V
24
Output Short CirCUit Current (Iosl
(Note 41
OM7511
OM8511
Vee
Vee
Logical "0" Output Voltage
(VOL)
Supply Current (Iccl
=
=
Max
Max
-55
-55
-20
-18
Vee'" Min, IOL '" 16 mA
04
Vee'" Max, Clear'" Clock'" 3 OV
All Other Inputs'" OV
55
Propagation Delay to a Logical "0"
19
30
19
30
135
20
from Clock to Output (tpdO)
Propagation Delay to a Logical "0"
from Cleat to Output (tpdO)
Propagation Delay to a Logical "1"
from Clock to Output (tpd1
TA = 25°C
)
MaXimum Clock Frequency (f MAX
Minimum Set-Up (tsET up)
Minimum Hold Time (t HOLD )
)
Vcc=50V,
CL = 50pF
30
45
10
0
MInimum Clock Pulse
(tPW(CLoeK)
11
20
Minimum Clear Pulse
(tPW(CLEAR1)
10
20
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVICes should be operated at these limits The
table of "Electrical CharacteristIcs" provIdes condItions for actual deVIce operatIon,
Note 2: Unless otherwIse specIfied minimax limits apply across the -55°e to +125°e temperature range for the DM7511 and
across the O"e to +70°C range for the DM8511 All tYPlcals are gIven for Vec = 5 OV and T A = 2SoC.
Note 3: All currents Into device PinS shown as pOSitIve, out of deVIce PinS as negatIve All voltages referenced to ground unless
otherWise noted. All values shown as max or min on absolute value baSIS
Note 4: Only one output at a time should be shorted.
1-166
15
-50
mA
mA
mA
,electrical characteristics (con't)
PARAMETER
DM7512/DM8512 (Notes 2 and 3)
LIMITS
CONDITIONS
Logical "1" Input Voltage (V 1H )
Vee"" Min
Logical "1" Input Current (I'H)
Vee == Max, V IN
Vee'" Max, V IN
MIN
TVP
MAX
20
40
10
== 24V
==
5 5V
==
a 4V
Logical "0" Input Voltage (V 1L )
Vee = Min
Logical "0" Input Current (lId
Vee
Input Clamp Voltage (V eo )
Vee = Max, liN = -12 mA
Loglcal"l"OutputVoltage (V OH )
Vee = Mm, lOUT = -BOO,uA
VIN(1~ = 2.0V. VIN(o) = 0 8V
08
== Max,
V IN
-10
-16
-10
-15
24
Vee = Max, VOUT = OV
Output Short Circuit Currenr (los)
(Note 4)
DM7512
DM8512
-20
-18
Vee'" Max, VOUT '" OV
Vee == Max, VOUT == OV
Logical "0" Output Voltage (VoLl
-55
-55
Vee = Mm. IOl = 16 rnA
V IN11l '" 2
Supply Current (Ieel
av. V1N(0)
04
== 0
8V
Vee = Max, Clock, Clear'" 3 OV
All Other Inputs == OV
57
Propagation Delay to a Logical "0"
from Clock to Output (tpdo)
26
40
Propagation Delay to a Logical "0"
from Clear to Output (tpdO)
26
40
Propagation Delay to a Logical "1"
from Clock to Output (tpd1 )
21
35
Propagation Delay to a Logical "1"
from Clear to Output (t p dl)
22
35
MaXimum Clock Frequency (f MAX )
20
TA = 25°C,
Vee =5.0V,
C l "" 50 pF
Minimum Clock Pulse
o
28
15
25
Minimum Clear Pulse
13
25
J, 0 Set·Up Time for "0" (tso)
87
15
J, D Set-Up Time for "1" (tS1)
90
15
M Set-Up Time for "0" (tsa)
15
25
M Set-Up Time for "t" (ts,)
20
30
K Set-Up Time for "1" (ts 1 )
13
20
K Set-Up Time for "0" (tso)
13
20
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operatmg Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The
table of "Electrical Characteristics" prOVides conditions for actual deVice operatIOn
Note 2: Unless otherWise specified min/max limits apply across the -55°C to +125°C temperature range for the DM7512 and
across the rfc to +70°C range for the DM8512 All typlcals are given for Vec '" 5 OV and T A'" 25°C.
Note 3: All currents Into deVice pins shown as POSitive, out of deVice PinS as negative All voltages referenced to ground unless
otherwise noted All values shown as max or mm on absolute value baSIS
Note 4: Only one output at a time should be shorted
truth tables
DM7511
DM7512
K
M
CLR
DM7613
~+1
D
G
CLR
~+1
QN
1
X
1
X
X
X
X
X
QN
X
ON
0
"Asynchronous transition
X = Irrelevant
ON
ON
l'
X
X
X
X
o
X
ON
X
QN
X
0'"
D
X
0'
* Asynchronous tranSition
X'" Irrelevant
* Asynchronous transitIOn
X'" Irrelevant
1-167
electrical characteristics (con't)
PARAMETER
DM7613/DM8613 (Notes 2 and 3)
LIMITS
CONDITIONS
MIN
TYP
MAX
V
20
Logical "1" Input Voltage (V 1H )
Vee'" Mm
Logical "1" Input Current (I'H)
Vee"" Max, VIN '" 2 4V
Vee'" Max, VIN '" 5 5V
Logical "0" Input Voltage (V 1L )
Vee'" Mm
Logical "0" Input Current (lId
Vee'" Max, V IN
'"
Input Clamp Voltage (V eo )
VC~
'" Max, liN
Logical "1" Output Voltage (V OH )
Vee
= Min, IOH == -800,uA
Vee
Vee
==
==
Max
Max
Logical "0" Output Voltage (VOL)
Vee
==
Min, IOL
Supply Current Oed
Vee
==
Max,
==
40
10
0 4V
-12 mA
UNITS
"A
mA
08
V
-10
-16
mA
-10
-15
V
-55
-55
mA
mA
24
Output Short ClrcUl~ Current (1os)
(Note 4)
OM7613
OM8613
-20
-18
==
04
v
58
76
mA
22
33
21
31
17
24
16 rnA
Clear'" Clock == 3 OV
All Other Inputs
==
OV
Propagation Delay to a Logical "0"
from Clock to Output (tpdHd
Propagation Delay to a Logical "0"
from Clear to Output (tpdH L)
Propagation Delay to a Logical "1"
from Clock to Output (tpdLH I
TA == 25°C
Vee'" 50V,
C L =50pF
20
MaXimum Clock Frequency (f MAX )
30
Minimum Clock Pulse Width
16
24
Set·Up Time for "1" (tS1)
16
24
Set-Up Time tor "0" (t50)
12
18
Note 1: "Absolute MaXImum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these lImits The
table of "Electrical Characteristics" proVides conditions for actual deVice operation
Note 2: Unless otherWise speCifIed min/max limits apply across the -55°C to +125°C temperature range for the DM7613 and
across the ODC to +70°C range for the DM8613 All tYPlcals are given for Vce == 5 OV and T A == 25°e
Note 3: All currents Into deVice PinS shown as positive, out of deVice PinS as negative All voltages referenced to ground unless
otherWise noted All values shown as max or min on absolute value baSIS
Note 4: Only one output at a time should be shorted
logic diagrams
DM7512/DM8512
DM7511/DM8511
CLOCK
r----------
6,10
CP
L. _ _ _ _ _ _ _ _ _ _
CLEAR
DM7613/DM8613
1-168
_ _ _ .J
X>----------.....~---
o
3:
Series 54/74
"N
U'I
o
"-
o
3:
DM7520/DM8520 modulo-n divider
00
U'I
general description
N
The DM7520/DM8520 combines TTL technology
and MSI (Medium Scale Integration) design to provide a circuit equal in complexity to more than 50
gates_
Although extremely versatile in a number of digital applications, its primary usage will be realized
in two areas:
1. MODULO-N DIVIDER
A single DM7520/DM8520 can be programmed
without external components to divide by any
number from 2 to 15. Cascading of these dividers will provide division by any number
from 2 to very large numbers.
2. SHIFT REGISTER
Since the basic organization of the logic is that
of a serial shift register, the device may be used
where four-bit parallel-in-serial out shifting is
required.
logic diagram
PRESET
-f><>-----......-+-------f---------l-::;~====----_.
SERIAL
OUTPUT
OUTPUT
0000
OETECT
table for division by n
connection diagram
Dual-In-Line and Flat Package
SERIAL
INPUT
p,-
P,
PARALLEL
INPUT
"
P4
';'BY
EXTERNAL
2
EXOR
INPUT
SERIAL
SETTING
P2
P3
EXOR
OUTPUT
0000
OETECT
SERIAL
OUTPUT
EXOP.
CONTROL
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1-169
o
o
N
In
00
:t
c
......
absolute maximum ratings
Q
N
In
Supply Voltage
Input Voltage
Operating Temperature Range
c
Storage Temperature Range
Lead Temperature (Soldering, '0 sec.)
":t
7V
5.5V
-55°C to +'25°C
O°C to +70°C
-65°C to +'50°C
300°C
DM7520
DM8520
electrical characteristics
(Note' )
PARAMETER
Logical "," Input Voltage
Logical "0" Input Voltage
Logical "," Output Voltage
Logical "0" Output Voltage
Logical "0" Input Current
(All inputs except pin 9)
Logical "0" I nput Current
(Pin 9)
Logical "," Input Current
CONDITIONS
DM7520
Vee: 4.5V
DM8520
VeG: 4.75V
DM7520
Vee: 4.5V
DM8520
Vee: 4.75V
DM7520
Vee: 4.5V
DM8520
Vee: 4.75V
DM7520
Vee: 4.5V
DM8520
Vee: 4.75V
DM7520
Vee: 5.5V
DM8520
Vee: 5.25V
DM7520
Vcc: 5.5V
DM8520
Vcc: 5.25V
DM7520
Vee: 5.5V
DM8520
Vee: 5.25V
lOUT: -400 IJA
V 1N
0.4
VIN: 0.4V
-3.2
IJA
V 1N
:
2.4V
40
IJA
V 1N
:
2.4V
80
IJA
V 1N
:
5.5V
Vee: 5.5V
Vee: 5.25V
DM7520
Vee: 5.5V
DM8520
Vee: 5.25V
V OUT = OV (Note'2)
Power Supply Current
Vee: 5.0V
T A :25°C
Counting Frequency
Vee: 5.0V
TA
:
25°C
,
mA
-20
-'8
50
'5
55
mA
75
mA
20
MHz
CL : 50 pF, T A : 25°C
50
ns
RL : 390n, Vee: 5.0V
55
ns
Note 1: Unless' otherwise specified, limits shown apply across the -550C to +125 0 C temperature
range for the DM7520 and the OOC to +70 0 C temperature range for the DM8520. Typical values
apply to supply voltages of 5.0V.
Note 2:
Only one output should be shorted at a time.
Nota 3:
Serial and exclusive OR outputs.
'·170
V
mA
DM8520
"b"
V
2.4
-'.6
DM7520
Propagation Delay to a Logical.","
V
O.4V
:
Vee: 5.5V
Propagation Delay to a Logical
UNITS
V
lOUT: '6 mA
Vee: 5.25V
Output Short Circuit Current
(Note 3)
MAX
0.8
DM8520
Logical "," Input Current
(All inputs except pin 9)
TYP
2.0
DM7520
Logical "'" I nput Current
(Pin 9)
MIN
o
3:
theory of operation
The basic operation of the DM7520/DM8520 is
derived from the fact that when several outputs of
a shift register are EXCLUSIVE OR'ed and the
result fed back to the register's input, a unique
progression of stable states results on the outputs
of the flip-flops_ Depending upon which outputs
are EXCLUSIVE OR'ed the number of different
states can be varied_ Even if optimum gating is
provided the most states which can be obtained is
2"-1, where n is equal to the number of flip-flops
in the register. The all-zero state is precluded; and,
therefore, the maximum number of states is
always one less than the theoretical maximum
number. Since the DM7520/DM8520 contains
four flip-flops, its maximum number of states is
15_ Because the 1111 state occurs only once during a 15-state sequence, this state is detected; and
its output becomes the output of the divider.
To obtain frequency division by numbers other
than the maximum, it is necessary to cause the
register to "jump" immediately from its initial
1111 to the state which it would normally reach in
16-m (m = desired frequency division) pulses. For
example, to divide by eleven it would be necessary
to jump to the fifth state and then simply allow
the register to normally progress forward to its
original state. The output of the divider is also
used as a control pulse. Since the 1111 state is
detected and since the "jump-state" information is
of interest only at the time that this state is
reached, the OUTPUT is used to gate the parallel
inputs, through the SERIAL/PARALLEL input,
so that it recognizes this "jump-state" information
only at this time. Subsequently as the states
change, the parallel input information is locked
from the divider.
Should the divider ever be accidently set in the
forbidden 0000 state, an output is provided to detect this state. If this output is in turn fed into the
EXTERNAL EX-OR input, a 1 will be forced into
the register at the next clock pulse, thus clearing
the unallowed state.
LEf::OR
CONTROL
0000
DETECT
SERIAL
INPUT
A PRESET input is provided which when taken to
a logical "1" level overrides all other inputs and
sets the register to the 1111 state_
I
PRESET
Other connections are shown_ (Figure 1 indicates
connections for 2 dividers or a maximum frequency division of 255_ For division by higher
numbers, a more complete discussion of the interconnection techniques will be given in the final
data sheet.)
To divide by numbers between 16 and 255, the
table in Figure 2 will apply.
Thus to summarize, the following connections
should be made for operation of a single DM7520/
DM8520.
Ex-Or Output to Serial Input
0000 Detect to External Ex-Or Input
Output to Serial/Parallel Input
Preset to Grou nd
Ex-Or Control to Ground
EX'O~ I J]~XOR
~EXTERNAl
EX·OR
OUTPUT
SERIAL
OUTPUT
SERIAL
INPUT
~
INPUT
-
CONTROL
INPUT
FREQUENCY
1
0000
DETECT
EXTERNAL
EX·OR
DM7520/DMB520
SERIAL/PARAllEl
o
CO
UI
N
o
To divide by numbers greater than 15, it is necessary to cascade DM7520/DM8520's. Both the
OUTPUT and the 0000 DETECT output are capable of being connected directly to other like outputs thus providing the "WI RED-OR" configuration_ These outputs should be connected to the
similar outputs on other dividers for proper operation. All SERIAL/PARALLEL inputs should be
connected to the common OUTPUT.
DM7S20/DMB520
INP~
o
......
3:
lOGICAL I
OUTPUT
LEXO~I
-..I
UI
N
OUTPUT
~t<>
r
SERIAL/PARAllEL
RESET
FIGURE 1. Connection for 2 Divider or Maximum Frequency Division of 255
1-171
o
o
N
., ., .,
It)
DIVIDER 1
00
:::E
Q
"o
N
It)
"""
:::E
Q
SETTING
I
., I .,
., ., ••
8Y
DIVIDER 2
., ., .,
SETTING
I
DIVIDER 1
., ., .,
p·1
P,
1
1
1
1
1
0
1
0
0
1
I
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
255
254
253
252
251
250
249
248
247
246
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
I
0
1
0
0
1
1
1
1
0
I
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
I
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
245
244
243
242
241
240
239
238
237
236
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
235
234
233
232
231
230
229
228
227
226
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
225
224
223
222
221
220
219
218
217
216
0
1
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
215
214
213
212
211
210
209
207
206
0
1
0
1
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
205
204
203
202
201
200
199
198
197
196
1
1
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
I
0
1
0
0
1
0
0
0
0
I
1
0
1
0
0
1
0
0
0
I
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
0
1
0
I
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
., ., .,
I
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
155
154
153
152
151
150
149
148
147
146
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
195
194
193
192
191
190
189
188
187
196
0
0
0
0
1
1
0
0
1
0
185
184
183
182
181
180
179
178
117
176
175
174
173
172
171
170
169
168
167
166
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
., ., .,
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
8Y
DIVIDER 2
.,1 .,
1
1
1
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
75
74
73
72
71
70
69
68
67
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
6b
64
63
62
61
60
59
58
57
56
0
0
66"
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
0
145
144
143
142
141
140
139
138
137
136
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
55
54
53
52
51
50
49
48
47
46
1
0
0
1
1
1
0
0
1
0
135
134
133
132
131
130
129
128
127
126
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
1
0
0
0
1
45
44
43
42
41
40
39
38
37
36
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
125
124
123
122
121
120
119
118
117
116
0
1
0
0
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
1
0
35
34
33
32
31
30
29
28
27
26
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
115
114
113
112
111
110
109
108
107
106
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
25
24
23
22
21
20
19
18
17
16
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
105
104
103
102
101
100
99
98
97
96
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
15
14
13
12
0
0
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
5
4
3
2
Ii
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
1
0
0
FIGURE 2. DM7520/DM8520 Shift Register Divider Input Coding Table (2 Package Combinations)
1-172
SETTING
DIVIDER 1
165
164
163
162
161
160
159
158
157
156
1
1
0
1
1
0
1
0
0
1
208
8Y
DIVIDER 2
0
11
10
9
8
7
6
Series 54/74
DM7542/DM8542 TRI-STATE® quad I/O register
general description
features
The DM7542/DM8542 is a 4-bit storage register
with two terminals per bit which may be used as
either inputs or outputs when tied to two bus
lines. Storage capability is obtained with positive
edge triggered flip·flops having common clock
and asynchronous clear. Each 1/0 terminal can
be forced to a high impedance state (Hi-z state)
using the Output Disable controls.
• Series 54/74 compatible
• Input clamp diodes
• Propagation delays
• Power dissipation
• Operation
25 ns
400 mW
40 MHz
logic and connection diagrams
o
CLOCK
ClEAR
E,
E,
Dual-In-Line and Flat Package
TOP VIEW
1-173
N
~
an
absolute maximum ratings
00
:E
(Note 1)
operating conditions
Q
"N
Supply Voltage
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
~5·e to +150·e
3OO·e
Laad Temperature (Soldering, 10 seconds)
~
an
""Q
:E
electrical characteristics
PARAMETER
MAX
4.75
4.5
5.25
5.5
0
-55
40
vA
1.0
rnA
Vee =Mln
0.8
V
-1.6
rnA
-1.5
V
-70
mA
MIN
TYP
V
2.0
-1.0
Vee = Max, VIN = D.4V
Input Clamp Voltage (V eD )
Vee - Mm, liN = -12 mA
Logocal"I" Output Voltage (VoHI
Vee - Mm, lOUT = -BClOItA
Output Short Circuit Current (los)
(Note 41
Vee = Max, VOUT = OV
logical "0" Output Voltage (VOL)
Vee = Mln,loUT = 16 rnA
0.4
Vee = Max
120
TRI·STATE I/O Current With Inputs
and Outputs Disabled
Vee - Max, VIN - 2.4V
Propagation Delay to a Logical "0"
From Clock to Output (....,1
RL • 400n. CL = 50 pF
TA - 2SoC
Propagation Delay to a Logical "0"
From Clear to Output (tpdO)
V
2.4
-25
V
mA
40
-40
vA
23
35
ns
RL = 40011. CL • 50 pF
TA =26°C
24
36
ns
Propagation Delay to a Logical "1"
From Clock to Output (tpet, )
RL • 400n. CL = 50 pF
TA =26°C
25
38
ns
Dalay From Disable to High Impedance
State (From Logical"'" Levell (t'H)
RL - 40011. CL • 6.0 pF
TA =2SoC
6.0
15
ns
Delay From Disable to High Impedance
State (From logical "0" .Levell (toH I
RL • 40011. CL - 5.0 pF
TA - 2SoC
15
25
ns
Delay From Disable to Logical "1"
Level (From HIWllmpedanceState) (tH1)
RL = 4OO!l, CL = 50 pF
TA = 25°C
20
30
n.
Delay From Disable to Logical "0"
Level (From High Impedance State) (tHO)
RL =4000, CL '" 50 pF
TA = 25°C
17
25
ns
Maximum Clock Frequency (fMAX)
RL = 40011. CL - 50 pF
TA = 25°C
30
40
MHz
Enable to Clock Set-Up Time (tao)
RL - 4000, CL = 50 pF
TA = 26°C
20
13
ns
Enable to Clock Set-Up Time Itsl)
RL = 40011. CL - 50 pF
TA - 25°C
20
12
n.
Data to Clock Set-Up Time ltao)
RL = 40011. CL = 50 pF
TA = 25°C
10
4.5
ns
Data to Clock Set-Up Time h~u I
RL = 40011. CL
T A =25°C
=50 pF
5.0
-4.0
ns
Data to Clock Hold Time (tHO I
RL - 40011. CL = 50 pF
TA ""25°C
10
4.5
ns
Data to Clock Hold Time ItHI)
RL = 40011. CL = 50 pF
T A =26°C
5.0
-3.5
ns
MInimum Clock Pulse Width (PWMIN I
RL = 40011. CL - 50 pF
T A "25°C
20
n.
Minimum Clear Pulse Width (PW MIN )
RL = 40011, CL - 50 pF
TA "25°C
20
ns
Vee" Max, VIN .. O.4V
Note 1: "Absolute MaXimum Ratln,,'" are those values beyond which the safety of the devICe cannot be guaranteMl. Except
for "Operatmg Temperature Rangs" they are not meant to imply that the devices should be operated at these limits. The
table of "Electncal CharacterIStiCS" provideS conditions for actual device operation.
Note 2: Unle.. otherwise specified minImax hmlts apply across the --65°C to +125°C temperature range for the OM7542
and acron the crc to +7crC range for the DM8542. All typlcals are glYen for Vee - 5.0V and TA - ~C.
Note 3: All currents Into device pins shown as pOSitive, out of device pins as negative, all voltages referenced to ground unl_
othelWlse noted. All values shown as max or min on absolute value baSIS
Note 4: Only one output at a time should be shorted.
'·174
·e
·e
+70
+125
Vee = Max, VIN = 2.4V
Vee" Max, VIN = 6.5V
Logical'''O'' Input Voltage (V 1L )
tied
V
V
UNITS
Logical "1" Input Current (lIH)
Supply Current
UNITS
MAX
CONDITIONS
Vcc,.Mm
(I.d
Temperature, T A
DM8542
DM7542
MIN
(Notes 2 and 3)
logical "I" Input Volt.ge (V'HI
logical "0" Input Current
Supply Voltage. Vee
DM8542
DM7542
~A
c
3:
.....
modes of operation
U'I
~
N
......
CLEAR
DIS,
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
X
X
X
X
X
X
0
1
DIS2
E,
c
COMMENTS
A, .•
B, .•
1
a
HI-z
Output Data to Bus A
1
HI-z
Output Data to Bus B
a
a
a
HI-z
HI-z
Store Data With Outputs
1
Data
ON
0
0
ON
Data
Data
Data
Enter Data From Both
X
Buses (Logic "1" on Either
Will Dommate)
Clear
E2
3:
00
U'I
~
Output Data to Both Buses
N
In HI'z State
1
X
X
0
X
X
X
Enter Data From Bus A
Enter Data From Bus B
x '" Don't Care State
On '" Data
After Clock TranSition
o
1·175
tIt)
It)
co
Series 54/74
~
c
.......
tIt)
It)
.....
®
DM7551/DM8551 TRI-STATE quad 0 flip flop
~
c
general description
The DM7551/DM8551 isaTRI-STATE logic device
which provides four D-type flip flops in one package which operate synchronously from a common
clock.
features
•
Series 54/74 compatible
•
23 ns typical propagation delay
•
250 mW typical power dissipation
•
Outputs directly connectable for bus-line operation
•
A "do-nothing" state accomplished without gating the clock
•
Simple disable encoding
A unique three-state output allows the device to
be used in bus-organized systems. The outputs can
be directly wired to outputs of other DM75511
DM8551 '5 without encountering the problems normally met with "collector- DRing" TTL circuits.
This is accomplished by gating the normally low
impedance logical "1" or logical "0" output into
a high Impedance state.
(Continued)
logic and connection diagrams
Dual-In-Line and Flat Package
OATAINPurj
INPUT
DISABlES
OUT1'UT
DISABLES
INPUT
INPUT
INPUT
INPUT
ABC
0
OuTPUT OUTPUT OUTPUT
OUTPUT
ABC
0
DATA
INPUT
DISABLE DISABLE
j
INPUTIo------+t--r,
OUTPUT
OUTPUT
DISABLE DISABLE
CP
truth tab Ie (Both Output Disables Lowl
'n
DATA INPUT DISABLE
DATA
INPUT
OUTPUT
Logical" 1" on 1 or both Inputs
X
On
Logical "0" on both Inputs
1
1
LogIcal "0" on both Inputs
0
0
x '" Don't Care
1-176
tn+1
c
absolute maximum ratings
s:.....
(Note 1)
UI
UI
...
7V
5.5V
5.5V
Supply Voltage
I nput Voltage
Output Voltage
Storage Temperature Range
Operating Temperature Range DM7551
DM8551
.......
C
-6SoC to +150°C
s:CO
-55"C to +125"C
O°C to +70°C
300"C
Lead Temperature (Soldering, 10 sec)
UI
UI
...
Time that two bus-connected devices may
be 10 opposite low Impedance states
Indefmitely
simultaneously
electrical characteristics
(Note 2)
PARAMETERS
CONDITIONS
Logical "1" Input Voltage
DM7551
DM8551
Vee = 4.5V
Vee - 4 75V
Logical "0" Input Voltage
DM7551
DM8551
V ee =45V
Vee - 4 75V
Output Voltage
DM7551
DM8551
Vee = 4 5V
V ee -475V
lOUT ~ -2 0 rnA
lOUT - -5 2 mA
Logical "0" Output Voltage
DM7551
DM8551
Vee = 4.5V
Vee - 4 75V
lOUT = 16 rnA
Logical "0" Input Current
DM7551
DM8551
Vee = 5.5V
Vee - 5.25V
V ,N =040V
DM7551
DM8551
Vee = 525V
Vee - 525V
V ,N =24V
V 1N = 5 5V
DM7551
DM8551
Vee=55V
V ee -525V
Va = OAV to 2AV
DM7551
DM8551
Vee = 5.5V
Vee- 525V
DM7551
DM8551
Vee=55V
Vee - 5.25V
Logical
Logical
"1"
"1"
Input Current
Output Current
In High Impedance State
Supply Current
Output Short Current
(Note 3)
MIN
TYP
MAX
2.0
V
080
24
02
-10
-40
-30
V
V
33
50
VOUT=OOV
UNITS
040
V
-16
rnA
40
1
pA
rnA
40
pA
72
rnA
-70
rnA
MaXimum Clock Frequency
Vee=50V
C L = 50 pF
TA = 25"C
25
30
Propagation Delay from Clock
Vee=50V
CL = 50 pF
TA = 25"C
11
20
28
ns
to Logical "0", tpdO
Propagation Delay from Clock
to Logical" 1", tpd 1
Vee=50V
CL = 50 pF
TA = 25"C
11
16
25
ns
Input Data Setup Time, ts
ns
Input Data Hold Time, tH
Input Disable Setup Time,
MHz
Vee=50V
TA = 25°C
3
10
DATA
Vee=50V
TA = 25"C
4
10
ns
ts DIS
Vee=50V
TA = 25°C
7
14
ns
DATA
Vee=50V
T A"" 25°C
-7
0
ns
Delay from "Output Disable" to High
Impedance State (from LogIcal "1"
Level), tlH
Vee = 50V
TA = 25"e
3
5
30
ns
Delay from "Output Disable" to High
Impedance State (from Logical "0"
Level), tOH
Vee = 5.0V
TA = 25"C
3
11
30
ns
Delay from "Output Disable" to
Logical "1" Level (from HIgh
Impedance State), tHl
Vee=50V
T A = 25"C
7
16
30
ns
Delay from "Output Disable" to
Logical "0" Level (from High
Impedance State), tHO
Vee=50V
TA = 25°C
.,
21
30
ns
Propagation Delay from Clear
to Output, tpd A
Vee = 5.0V
TA = 25"C
18
27
ns
Input Disable Hold Time, tH
DIS
Note 1: Absolute maximum ratmgs are those values beyond which the safety of the deVIce cannot
be guaranteed. Except for "Operatmg Temperature Range", they are not meant to Imply operating
condItions.
Note 2: Unless otherWise speCified the min-max limits across the _55°C to +125°C temperature
range for the DM7551 and across the OoC to 70°C temperature range for the DM8551. All tvpicals are
given for Vee = 5.0V and TA = 25°e.
Note 3: Only 1 output at a time should be shorted.
1·177
o
IUS LINES
120 rnA fOR DRIVING OTHER TTL INPUTS
~
SELECTED AS
DRIVING DEVICE - - - -
SELECTED AS
DRIVING
OEVICE
40J'A ~ 127 OUTPUTS", 5 08 rnA
LEAKAGE CURRENT
GATED INTO
THIROSTATE
GATED INTO
THIRD STATE
40 iJA LEAKAGE CURRENT
FIGURE 1
FIGURE 3
FIGURE 2
general description (cant.)
The high impedance state occurs.on all outputs of
all devices except the four outputs of the one device selected (Figure 11. The result is that the
selected device has a normal TTL low impedance
output providing good capacitive drive capability
and waveform integrity especially during the transition from a logical "0" to a logical "1". The
other outputs are all In the "third-state" and take
only a small amount of leakage current from the
driving outputs. Since the logical "1" output current of the selected device IS 13 times that of a
normal Series 54/74 output (5.2 mA vs 400 pAl.
the output is easily able to supply that leakage
current to as many as 127 connected devices and
still retain enough drive for a full Series 54/74
fan-out of 3 at the end of the bus line (Figure 21.
A two-input NOR gate facilitates selection of the
driving device through the use of only two octal
decoders for as many as 64 DM7551/DM8551's
(Figure 31.
A problem inherent in conventional D-type flip
flops is that it is impossible to code the data input
in such a way as to cause the flip flop to remain in
Its present state when clocked. Because flexibility
1-178
is not as great as with a J-K flip flop (and its J=O,
K=O statel, to keep a D-type flip flop in Its present
state it is usually necessary to gate the clock,
which Increases the danger of false-clocking. The
DM7551/DM8551 contains a gated input disable
which does not disrupt clocking, but rather recirculates information from the Q output to the D
input. In this manner the flip flop does not change
state and the possibility of false-clocking IS
eliminated.
The following logic levels control the device.
•
Clocking occurs on the positive-going transition.
•
Clearing is enabled by taking the input to a
Logical "1" level.
•
Outputs are placed In the "third-state" if either
of the two Output Disable Inputs is taken to a
Logical" 1" level.
•
The flip flops will remain in their prevIous state
when clocked so long as either of the two Data
I nput Disable Inputs is taken to a Logical "1"
level
The DM7551/DM8551 is completely compatible
with other Series 54/74 devices.
c
s::......
Series 54/74
illS
U1
U1
N
......
DM7552/DM8552 TRI-STATE® decade counter/latch
DM7554/DM8554 TRI-STATE
C
s::CO
binary counter/latch
U1
U1
N
general description
The DM7552/DM8552 and DM7554/DM8554 are
TTL TR I-STATE Synchronous Decode and Binary
counter/latch circuits respectively. The circuits
consist of a counter made up of four edge-triggered
JK flip-flops.
• 30 ns typical propagation delay
• Count mode and Terminal Count output are
operable when the outputs are in the high
impedance .state or latch mode
• Blanking capability with the DM7552/DM8552
• Positive true logic
features
The circuits logically combine the function of
counters for frequency division, latches to hold
the counter's information, and output buffer gates
which allow active TTL outputs as well as the high
impedance (3rd) state for output multiplexing of
data.
• Series 54/74 compatible
• 330 mW typical power dissipation
• TRI-STATE outputs directly connectable for
bus-line operation
• TR I-STATE outputs information may be latched
Dual-I n-Line and Flat Package
1. "
.
=-.'.
I
2
3
I'fIESET CLEAR
Ne
CEP
IJ
12
11
10
•
5
I
7
.;.C-";O:::UT~P::UTS:::--·~· ~~:r
eET
•
I'
GND
TOP VIEW
typical application
Multi-Stage Synchronous Counter with Visual Display
DISPLAY
UNIT
DISPLAY
UNIT
DISPLAY
UNIT
s::......
U1
U1
~
......
C
s::CO
U1
U1
~
o
connection diagram
TRANSfER
Vee ENABLE CP
c
DISPLAY
UNIT
v" o--.---t-HH--t-,
COUNT
ENABLE
i~:~:~"T
I
==
STAGES
STRD:~~t=~IST~S~TA~G~E==~t=~2N~D~ST~AG~E~~j=~~3R~D~ST~AG~E=~j:=~';TH~S;'TA;G;E
Counter stages can be cascaded as shown above to prOVide multiple stage BCD or binary synchronous counting by uSing the
DM7552/DM8552 or the DM7554/DM8554 respectively. With a Terminal Count (TCI fan out of
SIX
the above scheme allows
seven stages to operate at the maximum frequency eqUivalent to a two stage counter.
The characters displayed can be held with a low level on the strobe line while the counters can continue counting. The
display can be updated by applYing a positive pulse to the strobe line.
1-179
"It
an
an
absolute maximum ratings
co
:E
operating conditions
(Note 1)
Q
.......
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
"It
an
an
I"-
7.0V
5.5V
5.5V
-65°e to +150 oe
3000 e
:E
Lead Temperature (Soldering, 10 sec)
N
electrical characteristics
Q
an
an
co
PARAMETER
:E
Q
Logical "1" Input Voltage
N
Logical "0" Input Voltage
.......
an
an
I"-
:E
Q
Supply Voltage (Vee)
DM7552/54
DM8552/54
Temperature (T A)
DM7552/54
DM8552/54
CONDITIONS
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°e
MIN
TYP
MAX
2.0
UNITS
V
0.8
V
Logical "1" Output Voltage Te Output
lOUT = -0.4 mA
2.4
3.3
V
Logical "1" Output Voltage (Other Outputs)
lOUT = -2 mA (DM7552/54)
lOUT = -5.2 mA(DM8552/54)
2.4 .
3.3
V
Logical "0" Output Voltage
lOUT = 16 mA
Third State Output Current
V OUT = O.4V to 2.4V
Logical "1" Input Current
"CET"
"Other Inputs"
Logical "0" Input Current "CET"
"Other Inputs"
0.2
0.4
V
±40
p.A
V ,N = 2.4V
V ,N = 5.5V
80
2
p.A
mA
V ,N = 2.4V
V ,N = 5.5V
40
1
p.A
mA
V ,N = O.4V
-2.0
-3.2
mA
V ,N =O.4V
-1.0
-1.6
mA
Output Short C ircu it Current (Note 3)
TC Output
Other Outputs
V OUT = OV
V OUT = OV
Supply Current (each device) lee (max)
-20
-30
-55
-70
66
106
rnA
mA
mA
Input Clamp Voltage
liN = -12 mA
Output Vee Clamp Voltage
Vee = OV louT= 12mA
Output Ground Clamp Voltage
Vee = OV lOUT = -12 mA
Propagation Delay to a Logical "0" from
Clock to Any Output, tpdO
Vee = 5.0V
T A = 25°C
23
45
ns
Propagation Delay to a Logical "'" from
Clock to Any Output, tpd1
Vee = 5.0V
T A = 25°C
34
70
ns
Propagation Delay from TE to
Output, tpd (TE)
Vee = 5.0V
T A = 25°C
26
50
ns
-1.5
V
1.5
V
-1.5
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +12SoC temperature range for the DM7552!
DM7554 and across the 0° e to 70° e range for the DM8552/DM8554. All typicals are given for Vee = 5.0V and T A = 25° e.
Note 3: Only one output at a time should be shorted.
1-180
c
3:
electrical characteristics (cont.)
"
U'I
U'I
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
2.7
8
ns
17
40
ns
Vee = 5.0
TA = 25°C
21
45
ns
Delay from Output Disable to Logical
"0" Level (from High Impedance State), tHO
Vee = 5.0
TA = 25°C
25
50
ns
Maximum Clock Frequency
Vee = 5.0
TA = 25°C
Delay from Output Disable to High
Impedance State (from LogIcal "1" Level), t'H
Vee = 5.0
TA =25°C
Delay from Output Disable to High
Impedance State (from Logical "0" Level), tOH
Vee = 5.0
TA = 25°C
Delay from Output Disable to Logical
"1" Level (from High Impedance State), tHl
15
23
N
......
c
3:
00
U'I
U'I
N
MHz
mode of operation
When the Transfer Enable (TE) is at a logical "I"
level the data transfer paths between the counter
outputs and the output buffer gates are maintained.
When the Transfer Enable (TE) is at a logical "0"
level, the data transfer paths are inhibited, and the
state of the output buffer gates are locked in by
the latches. The counter and Terminal Count (TC)
output remain operable during this time.
CET is high. The Terminal Count logic equations
are:
OM7552/0M8552 TC = CET . A . B . C . 0
OM7554/0M8554 TC = CET . A . B . C . 0
o
The following logic levels control the device:
• The counter changes state on the positive·going
transition of the clock.
• Clearing or Presetting is enabled by taking the
respective input to a logical "I" level.
• To enable the count mode both CET and CEP
inputs must be at a logical "1" level.
• To latch the outputs the Transfer Enable (TE)
input must be taken to the logical "0" level.
• To place the TRI-STATE outputs into the
''Third-State'' either of the Output 0 isable (00)
inputs must be taken to the logical "I" level.
Asynchronous Clear (C L) resets the counter to
0000.
Asynchronous Preset (PR E) resets the counter
to 1111.
The 1111 state may be used in the OM7552/
OM8552 for blanking out leading zeroes in visual
displays. The next clock pulse will advance the
OM7552/0M8552 to 0001 which denotes the first
count of the blanked zero. The next clock pulse
will advance the OM7554/0M8554 to 0000.
The clock input must be high during the high to
low transition of CEP and/or CET for correct
logic operation. The CEP and CET inputs may be
used in a high speed look ahead technique (see
application) .
The Terminal Count (TC) output is active high
when the counters are at term inal cou nt and the
logic tables
DM7552/DM8552
FUNCTION TABLE
INPUTS
001
002
1
X
X
1
0
0
0
0
0
0
0
•
ce' ceT
X
X
X
X
PRESET
Te
X
X
X
X
X
X
1
0
X
X
X
1
1
0
X
X
X
X
X
X
1
1
OUTPUTS
CLEAR
-Function of the count sequence
•
1
•
I
DM7554/DM8554
DECADE COUNT SEQUENCE BINARY COUNT SEQUENCE
AI 81
C
10
"High Impedance State"
. H~Toj·T~"··
1
1
1
LATCH
COUNT
1
TC
COUNT
•
1
2
3
4
5
6
7
8
•
A
8
UTPU.II.
C
0
OUTPUTS
TC
• •• •• •• ••
• • • •
• •• • ••• ••
•
• • • •
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
0
1
1
1
**ItPreset
Applied
Next
Cou",
• ••
1
"The 1111 Sta11t mey be used In conjunction With
certain dacodflrfdffiIIIB I ' , DM5446. OM5447
and DM5448 for blinking leading zeJ'Ollf
COUNT
A
8
C
• • •• ••
• •
•
• ••
1
2
1
3
4
1
6
7
8
9
,.
11
12
13
"
"
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
•
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
TC
• •
•• ••
••
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
•
0
0
0
0
0
1
1-181
logic diagrams
DM7552/DM8552
,
OUTl'lIT
.
OUTPUT
OUTl'UT
C
OUTPUT<>::=:::r::;IO-_____4~f_------..._t--------4~+-------J
OISABlESO
N
an
an
co
:!
Q
......
N
an
an
:!
TRANSFER
ENABLE
"
Q
COl/NT ENABLE
TRICKLE
COUNTENA8lE
PARALLEL
DM7554/DM8554
,
OUTl'UT
OUTPUT
DISABlES
TRANSFER
ENABLE
COUITENABLE
TRICKLE
COl/NfENABLE
PARALLEl
ClOCK
1-182
.
OUTPUT
DUTl'UT
C
OUTPUT
D
TERMINAL
COUNT
OUTPUT
c
Series 54/74
...,~
U'I
U'I
W
......
C
~
00
U'I
U'I
DM7553/DM8553 TRI-STATE® eight bit latch
W
general description
The DM7553/DM8553 provides eight latcheswhose
inputs and outputs are accessed on the same leads.
The fact that the outputs utilize TRI·STATE cir·
cuitry allows this to be done. While in the high·
impedance state, the outputs and inputs are disabl·
ed and no information can be entered. When the
outputs are active the gating associated with each
latch prevents information from being entered. The
outputs are disabled while information is entered.
In this manner eight bits of storage can be accomplished with parallel inputs and outputs in a 16·pin
package.
features
• Series 54/74 compatible
• Typical power dissipation
• Typical propagation delay
330mW
25 ns
o
logic and connection diagrams
Vee "'6
1---------;-1
GND~8
Dual-In-Line and Flat Package
I
DATA INPUT/OUTPUT 1
I
DATAINPUT/OUTPUT2
DATA INPUTS/OUTPUTS
v~
I
I
I"
,,",-++...,"'\
15
14
ENABLE
CLEAR
11
13
11
10
--
READ
DATA INPliTS/OUTPUTS
.N.I'
TOP VIEW
truth table
CLEAR
ENABLE
READ"
WRITE"'·
OPERATION
STATE OF
BUS
Enter 0
Enter 0
HI-z
Do Nothing
Write
HI-z
HI-z
, orO ......
Read
1 orO"""
Do Nothing
WRITE
WRITE
fiiAID
""""'--"L._
u-,,..----.,--'
*Both Read tnputs
HBothW"telnpLJ1$
.UDependson State of latch
~n:::~~)o---------------------jl-------~
0.
READ
CLEAR
1·183
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
operating conditions
(Note 1)
Supply Voltage (Vee)
DM7553
DM8553
7V
5.5V or 0.5V above Vee
Storage Temperature Range
-65°eto+150oe
Lead Temperature (Soldering, 10 sec)
300
0
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
-55
0
+125
70
V
Temperature (T A)
e
DM7553
DM8553
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage,
Output Enabled
-2.0 rnA (7553)
Vee = Min, lOUT =
-5.2 rnA (8553)
Logical "0" Output Voltage,
Output Enabled
Vee
Logical "1" Input Current, Input Enabled
Vee = Max, V ,N = 5.5V
TYP
MAX
0.8
V ,N
= 2.4V
Vee = Max, V ,N = 0.4V
TRI·STATE I/O Current with Inputs &
Outputs Disabled
V I/O
Output Short Circu it Current
(Note 31
8553
Vee = Max, 7553
or 0.4V
Supply Current
-28
-30
66
= OV, lOUT = +12 rnA
Input/Output Vee Clamp Voltage
Vee
Input/Output Ground Clamp Voltage,
Outputs Disabled
Vee = 5V, lOUT = -12 rnA
V
V
2.4
16 rnA
Logical "0" Input Current, Input Enabled
UNITS
V
2.0
= Min, lOUT =
= 2.4V
MIN
0.4
V
1.0
rnA
40
JJA
-1.6
rnA
±40
JJA
-70
rnA
93
rnA
1.5
V
-1.5
V
TRI-STATE OUTPUT CHARACTERISTICS
Delay from Output to High Impedance
State (from Logical "1" Level), t'H
Vee
Delay from Output to High Impedance
State (from Logical "0" Level), tOH
Vee = 5.0V, TA
Delay from Output to Logical "1" Level
(from High Impedance Statel, tHl
Vee
Delay from Output to Logical "0" Level
(from High Impedance Statel, tHO
Vee = 5.0V, TA
= 5.0V, TA = 25°C
7
12
ns
= 25°C
20
30
ns
= 5.0V, TA = 25°C
22
33
ns
= 25°C
25
38
ns
21
32
ns
Delay from Clear I nput to Output =
Logical "0", tpdR
Min Clear Pulse Width Required, t,pw
Data Setup Time, ts
10
15
ns
Data = 1
14
20
ns
a
26
36
ns
Data = 1
-26
-15
ns
a
-14
-8
ns
28
40
ns
Data =
Data Hold Time, th
Data =
Min Write Pulse Width Required, !wpw
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherWise specified minImax limits apply across the -55°C to +125°C temperature range for the DM7553
and across the O°C to 700 e range for the DM8553. All typlcals are given for Vee = 5.0V and T A = 25°e.
Note 3: Only one output at a time should be shorted.
1·184
CI
Series 54/74
....~
U'I
G)
o
'"CI
~
co
U'I
OM7560/0M8560(SN54192/SN74192) up/down decade counter
G)
o
general description
The DM7560/DM8560 is a TTL, Series 54/74 compatible, up-down decade counter which is capable
of being preset to any number from 0 through 9.
A load input controls the asynchronous entry of
these numbers, and sets all outputs to appropriate
state.
Counting is performed through two clock lines-
one controlling the count in the up direction, and
the other in the down direction. Two outputs, Borrow and Carry, are connected to the clock inputs
of subsequent counters to provide for counting to
numbers greater than 9. The counter is synchronous by itself, and "semi-synchronous" (two gate
delays between stages) when cascaded.
logic diagram
r~;~~~~~~J----..!l('.!l.3
r
l-t-R==l==l=t=====c)o-------.!!(1:!!.Z)
o
BORROW
OUTPUT
CARRY
OUTPUT
13I DUTPUT ilA.
Iz) OUTPUT D.I
_~
D.T.'
U
INPUTC~
(6) OUTPUTIlc
(11 OUIPUT 110
LOAD 11
1-185
oCQ
It)
absolute maximum ratings
CO
:::E
Q
......
Vee
I nput Voltage
Operating Temperature Range
o
CQ
It)
I'
7.0V
5.5V
_55°C to +125°C
O°C to + 70°C
_65°C to +150°C
10
300°C
DM7560
DM8560
Storage Temperature Range
Fanout
Lead Temperature (Soldering, 10 secl
:::E
Q
electrical characteristics
(Note 11
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
DM7560
DM8560
Vee = 4.5V
Vee - 4.75V
Logical "0" Input Voltage
DM7560
DM8560
Vee=45V
Vee - 4.75V
Logical" 1" Output Voltage
DM7560
DM8560
Vee = 4.5V
Vee - 4.75V
lOUT = -400 IJA
Logical "0" Output Voltage
DM7560
DM8560
Vee=45V
Vee - 4.75V
lOUT = 16 mA
Logical" 1" I nput Current
(All Inputsl
DM7560
DM8560
Vee = 5.5V
Vee = 5.25V
VIN = 2.4V
40
IJA
Logical" 1" I nput Current
(All Inputsl
DM7560
DM8560
Vee = 5.5V
Vee - 5.25V
VIN = 5.5V
1
mA
Logical "0" I nput Current
DM7560
DM8560
Vee = 5.5V
Vee = 5.25V
VIN = O.4V
-1.6
mA
Output Short CirCUit Current
(Note 21
DM7560
DM8560
Vee = 5.5V
Vee = 5.25V
V OUT = 0
Supply Current
DM7560
DM8560
Vee = 5.5V
Vee - 5.25V
2.0
0.8
Propagation Delay to a
logical" 1", tpd 1
Vee = 5.0V
T A =25°C
From Clock to Carry/Borrow
Propagation Delay to a
Logical "0", tpdQ
Vee = 50V
T A = 25°C
From Clock to Carry/Borrow
Maximum Clock Frequency
Vee = 5.0V
T A =25°C
24
-20
-18
From Clock to Output
-
20
aOc to
700 e for the DM8560 unless otherwise specified. Typu,als are given for Vee = 5V and TA = 25°e only.
1·186
V
V
0.4
From Clock to Output
Note 1: Specifications apply across -55°C to +12SoC temperature range for the DM7560 and
Note 2: Only 1 output may be shorted at a time.
V
V
-55
-57
mA
rnA
65
65
89
102
mA
mA
25
17
38
26
ns
ns
31
16
47
24
ns
ns
30
MHz
logic waveforms
(Exlmple shown for (1) clun.... (2) nynchronoully HtI'1il to
(3) countl" "up" to two, Ind (4) COURtinti ......... to light.)
...... count,
-11__________________________
CLEAR
---rLJ
LOAD
A,N-.L...!...._~--B~-.~
__ ______
~
C'N--,..-+__-+-______
4l-f1-fl.-.1
CLOCK UP
CLOCK DOWN
I
!
,
I
I
I
I
I
I
I
I
I
I
I
I
,
BouT
DOUT
CARRY
LflJlSU
, ,
,
I
I
I
I
-.~~------+-~~~--~Ir----i~I--~~~~------: :
,
-.
o
L-.J
j
--------~U~!~------~~-----
u
BORROW
NOTES' 1. A, B. C AND 0 INPUTS ARE FREE TO CHANGE AfTER LOAD INPUT IS DISABLED
2. WHEN COUNTING "UP". THE "DOWN" CLOCK MUST BE IN THE LOGICAL 1 STATE, AND CONVERSELV.
cascading counters
1-----1 CLOCK UP
I-__-I~~~K
connection diagram
Dual-I n-Line and Flat Package
Vee
BIN
A'N CLEAR BORROW CARRY LOAD
BoUT
AOUT
CLOCK CLOCK
DOWN
UP
TOP VIEW
COUT
CIN
DOUT
DIN
GROUND
1-187
Series 54/74
DM7563/DM8563(SN54193/SN74193) up/down binary counter
general description
one controlling the count in the up direction, and
the other in the down direction. Two outputs, Bor·
row and Carry, are connected to the clock inputs
of subsequent counters to provide for counting to
numbers greater than 15. The counter is synchronous by itself, and "semi-synchronous" (two
gate delays between stages) when cascaded.
The DM7563/DM8563 is a TTL, Series 54/74 compatible, up-down binary counter which is capable
of being preset to any number from 0 through 15.
A load input controls the asynchronous entry of
these numbers, and sets all outputs to appropriate
state.
Counting is performed through two clock lines-
logic diagram
(l3) BORROW
OUTPUT
(121 CARRY
OUTPUT
OAT A IS
INPUT A
(4'
DOWN
COUNT
...........
::n:,:
OAT A(l)
INPUT
•
~$
DUTPUTO A
<.
UP(6)
COUNT
~$
-t...../
~
DurpUlD"
<,
:flo
DATA (10)
INPUTC
...........
J
'91
DATA
INPUTD
CLEA'R
(14)
(11)
LOAD
1-188
~~
n
OllTPUTOc
~~rnr
OUTPUTIla
absolute maximum ratings
Vee
Input Voltage
Operating Temperature Range
7.0V
5.5V
-55°C to +125°C
OOC to +70o C
_65°C to +150°C
10
300°C
DM7563
DM8563
Storage Temperature Range
Fanout
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 1)
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
logIcal ··1" Input Voltage
DM7563
DM8563
V"''; 4.5V
Vee; 4.75V
logIcal "0'· Input Voltage
DM7563
DM8563
Vee; 4.5V
Vee; 475V
logIcal" 1" Output Voltage
DM7563
DM8563
Vee; 4.5V
Vee; 475V
lOUT; -400 J.lA
logIcal ·'0" Output Voltage
DM7563
DM8563
Vee; 45V
Vee; 475V
lOUT; 16 rnA
logIcal"'" I nput Current
(All Inputs)
DM7563
DM8563
Vee; 55V
V ,N ; 2.4V
Vee; 5.25V
40
J.lA
logIcal""· Input Current
(All Inputs)
DM7563
DM8563
Vee; 5.5V
V ,N ; 5 5V
Vee - 5.25V
1
mA
logIcal "0" I nput Current
DM7563
DM8563
Vee; 5.5V
V ,N ; O.4V
Vee; 5.25V
-1.6
mA
Output Short CirCUIt Current
(Note 2)
DM7563
DM8563
Vee; 55V
V OUT = 0
Vee = 525V
Supply Current
DM7563
DM8563
Vee = 55V
Vee - 5.25V
PropagatIon Delay to a
logIcal" 1", tpd 1
Vee; 5.0V
T A; 25°C
PropagatIon Delay to a
logIcal "0'·, tpdQ
Vee: 50V
TA ; 25°C
Maximum Clock Frequency
Vee; 5.0V
T A ; 25°C
2.0
V
0.8
2.4
V
V
0.4
-20
-18
V
-55
-57
mA
mA
65
65
89
102
mA
mA
From Clock to Output
25
from Clock to Carry/Borrow
17
38
30
ns
ns
from Clock to Output
31
16
47
24
ns
ns
From Clock to Carry/Borrow
20
30
MHz
Note 1: SpeCIfIcations apply across _55°e to +1250 e temperature range for the DM7563 and O"c to
70"e for the DM8563 unless otherwise specifIed. TYPlcals are gIven for Vee; 5V and T A =25°e only.
Note 2: Only 1 output may be shorted at a tIme
1-189
o
logic waveforms
[Example shown for (1) cleanng, (2) asynchronously setting to fourteen count,
(3) counting "up" to two, and (4) countmg "down" to fourteen,1
J1
CLEAR
I
~--------------------------------------------
~r------------------------------------------------
LOAD
,
A,.!
B1N-.J
CIN-.J
OIN-.J
:
~
CLOCK UP
I
I
I
1
,,,
CLOCK DOWN
I
,,, Ln...JULJ
ttl
I
I
I
I
I
I
AOUT
I
BOUT
I!-,
-U
I
I
I
r-----I
----:---~
----7--:~
!o,
Cou ,
---Uri------:--':---11
°ou,
-U,...-----:-...:,--II!-'_....!._--''-_ _.l..._...L.....;...~
:
1----'-----
_________~-;~~I__________...L..~_ _ _ _ ____
CARRY
BORROW
-------------------------------;LJr'-------NOTES, 1. A, B, C, AND 0 INPUTS ARE FREE TO CHANGE AFTER LOAD INPUT IS DISABLED,
2, WHEN COUNTING "UP", THE "DOWN" CLOCK MUST BE IN THE LOGICAL I STATE, AND CONVERSELY,
cascading counters
1-----\ CLOCK UP
I-___-\~~~~K
connection diagram
Dual·1 n·Line and Flat Package
vee
BIN
A'III CLEAR BORROW CARRY LOAD
BOUT
AOUT
CLOCK CLOCK
DOWN
UP
TOP VIEW
1-190
COUT
tiN
DOUT
D'N
GROUND
c
3:
.....
.....
o
.......
c
3:
Series 54/74
U1
OM7570/0M8570 (SN54164/SN74164)
CD
U1
a-bit serial-in parallel-out shift register
o
.....
general description
The DM7570/DM8570 utilizes Series 54174 compatible TTL circuitry to provide an eight-bit
serial-in parallel-out shift register designed to operate at frequencies of 20 MHz. Other features in·
clude gated serial inputs for strobe capability and a
clear input which, when taken to a logical 0, asyn·
chronously sets all flip flops to the logical 0 state.
Because the flip flops are R·S instead of J-K, input
information may be changed immediately prior to
the triggering edge of the clock waveform. Logi·
cal 1 levels on SA and SB enter logical 1's into the
shift register. Clocking occurs on the positive·going
edge of the clock pulse.
logic and connection diagrams
o
Dual~ln-Line
SA
so
and Flat Package
Q2
03
o.
.ND
TOP VIEW
1·191
o
....
absolute maximum ratings
It)
CO
:t
Supply Voltage
Input Voltage
Fanout
Storage Temperature Range
Operating Temperature Range
Q
......
....o
....
It)
7V
5.5V
5
-65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
DM7570
DM8570
Lead Temperature (Soldering. 10 sec.)
:t
Q
electrical characteristics
(Note 1)
PARAMETER
CONDITIONS
logical "," Input Voltage
Logical "0" Input Voltage
LOgical "1" Output Yoltage
Logical "0" Output Voltage
Logical "1" Input Current (Except Clear Input)
Logical "1" Input Current ('Clear Input)
Logical "1" Input Current
Logical "0" Input Current
Output Short Circuit Current (Note 2)
Power Supply Current
DM7570
Vee"" 4.SV
DM8570
Vee - 4.75V
DM7570
Vee'" 4.5V
DM8570
V cc -415V
DM7570
Vee
DM8570
Vee
DM7570
Vee = 4 5V
DM8570
Vee =- 4 75V
= 4.5V
= 4.75V
= 5.5V
DM7570
Vee
DMB570
Vee - 5.25V
DM7570
Vee:= S.SV
DM8570
Vee - 5.25V
DM7570
Vcc=55V
DM8570
Vee - 5 25V
DM7570
Vee
DM8570
Vee
DM7570
Vee = S.SV
DM8570
Vee - 5.25V
DM7570
Vee
DM8570
Vee - 5.25V
=5.5V
= 5.25V
MIN
TVP
MAX
20
V
0.8
lOUT =-400IJ,A
UNITS
V
V
24
04
lOUT'" 8 mA
V
2.4V
40
~A
V IN ;;.24V
80
~A
V IN
V IN
'"
'"
5.SV
VIN = O.4V
V OUT =
OV
-10
1
mA
-1.6
mA
-27.5
mA
-9
= 5 5V
36
54
mA
mHz
Maximum Clock Frequency
Vee"" 5 OV, 2SQ C, 50% Duty Cycle
14
20
Propagation Delay to a Logical "0" from Clock
to Output. tpdO
Vee'" S.OV, TA '" 2SoC, C = 50 pF
10
28
40
ns
Vee::: S.OV, TA = 25°C, C = 50 pF
10
28
40
ns
Vee::: S.OV, T A = 2SoC, C:: 50pf
34
50
ns
MIOImum Clock Pulse Width
Vee'" SOY, T A ::: 2SOC, C::: 50pF
25
45
n,
MInimum Clear Pulse Width
Vee'" 5 av, T A
30
45
n,
MInimum Time that SA S8 Data Must be Set-up
Prtor to Clock Pulse, t.-t.lP
Vee
Clock Pulse Width'" 50 ns
15
30
ns
Minimum Time that SA . Sa Data Must be Held
Vee"" SOY, TA '" 2SoC,C:: 50 pF,
Clock Pulse Width = 50 ns
-15
0
ns
Propagation Delay to a Logical
to Output. tpdl
"1" from Clock
Propagation Delay to a Logical "0" from Clear
to Output
After Clock Pulse, t"OI(l
Note' Unteu otherwise speCified, limits SnOW" applv from _55°C to +12SoC for the DM7570 and
OOc 10 HOoC for the OM8570 Typical values apply to supply vOltages of 5.DV and 25°C
Note 2. Only one output should be shorted at a time
1·192
:::
2SOC. C::: 50 pF
= 5.0V, TA =25'C, C = 5OpF,
Series 54/74
DM7573/DM8573 1024-bit field-programmable read only memory
general description
state, a 9V level is applied to the most significant
address input, Pin 15. This feature will allow a
much more complete test to be made before a part
is shipped, thus minimizing customer returns.
The DM7573/DM8573 is a field-programmable
read-only memory organized as 256 four-bit
words_ Selection of the proper word is accomplished through the eight select inputs. Two overriding memory enable inputs are provided; when
either or both of the enable inputs are taken to a
high state, all the outputs will be turned off. A
logical "1" has been built into each bit location. A
logical "0" can be programmed into any bit by
selecting the proper word, disabling the chip, and
applying a programming pulse to the proper
output.
features
• Can be programmed in 1 sec (50% logical l's;
50% logical O's)
• Pin compatible with SN54187(SN74187
• Can be programmed after being connected in a
system
• Outputs can be fully tested before programming
400mW
• Typical power dissipation
60 ns
• Propagation delay
An additional feature of the DM7573/DM8573 is
that its outputs can be tested in the logical "0"
state without permanently programming the memory. In order to place all outputs in the logical "0"
01
logic and connection diagrams
BINARY
SElECT
A~
(11
A,
(6/
Au
(51
MEMORY [ME10;1~"'!::!::::::r::)----:
UNITS
V
V'N = 2.4V
DM7575176
DMS575/76
MAX
O.S
Logical "1" Input Current
Output Short Circuit Current
INote 3)
TYP
2
/lA
V
40
1
/lA
rnA
-1.0
rnA
-55/-3.5
-55/-3.3
rnA
170
rnA
-1.5
V
100
ns
SO
ns
Not8 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical CharacteristicS" provides conditions for actual device operation.
Nota 2: Unless otherwise specified min/max limits apply across the -55°C to +12SoC temperature range for the DM7575/76
and across the ife to 700 e range for the DM8575/76. All typical, are given for Vee
Nota 3: Only one output at a time should be shorted.
1-200
= 5.0V and T A = 25°e.
c
s::
.....
information needed to program the PLA
Information to program the PLA can be supplied
In
one of two formats,
1. Punched 80-column cards
2 The applicable section of thIS data sheet (manual
entry of information).
punched cards
CARD 1: (Used to determine whether outputs are
presented In their true or Invened form. If thIS
card IS not used It is assumed that all eight outputs
are true.)
Col. 1-6: DM7575 or DM8575 or DM7576 or
DM8576.
Col. 7-9: (Blank)
Col. 10·17: Output Data. Outputs are Fa (most
Significant) to F, (least Significant). All eight
outputs must be specified.
A 'T' In an output location indicates that the
output is true.
A 'C' In an output location indicates that the
output IS complemented (inverted).
Col. 18·39: (Blank)
Col. 40·75: ThIS space IS reserved for any unique
letters/numbers deSIred by the customer (special
part number, program number, etc) However the
exact combination of characters must appear on
all cards, but only those cards, associated With that
particular deVice.
Col. 76·78: (Blank)
Col. 79·80' 00
CARDS 2·97: Term Data Cards. Used to specify the
Input and output condition>.
Col. 1·6: DM7575 or DM8575 or DM7576 or
DM8576.
Col. 7·9: (Blank)
Col. 10-17: Output Connections. Outputs Me Fa
(most Significant) to F, (least Significant). ThIS
field describes the outputs on which the product
term appears.
A '+' in one of the eight output locations indicates that the term described by the card IS one
of the "OR" terms in that output.
A '(blank)' in one of the eight output locations
indicates that the term described by the card
IS not one of the "OR" terms in that output.
(Care should be exercised in punching this particular field; since in most cases, unless a product term
IS repeated, thIS field will appear as one '+' and
seven blanks_)
Col. 18: (Blank)
Col. 19: = (equal Sign)
Col. 20: (Blank)
Col. 21·34: Input Data. Inputs are 1'3 (most Significant) to 10 (least significant).
An 'H' In one of the fourteen locations indio
cates that Input appears in the high state In the
output term.
An 'L' in one of the fourteen Input locations
indicates that Input appears In the low state in
the output term.
An 'X' in one of the fourteen Input locations
indicates that mput does not appear in the
output term.
en
.....
Col. 35·39: (Blank)
en
Col. 40·75: ThIS space IS reserved for any unique
letter/number deSIred by the customer (special
part numbel, program number, etc.) However the
"-
exact combmatlon of characters must appear on
CO
all cards, but only those cards, associated With that
particular deVice. The purpose of thIS section IS to
prevent mlxmg of cards.
Col. 76·78: (Blank)
C
s::
en
.....
en
c
Col. 79·80: Product Term Number 01 to 90. (All
96 cards need not be used.) Zero In column 79 may
be suppressed.
s::
.....
manual entry
0)
en
.....
The matrlx·blank shown In this data sheet can be
used in lieu of punched cards to submit information
for programming the PLA.
"-
INSTRUCTIONS
CO
1. Circle the appropriate part number. In the event
a catalog part IS not being purchased, Circle the
closest catalog part number. If an electrical
screen IS required between the military and
C
s::
en
.....
0)
commerical devices, the military designation
should be Circled.
2. Customer should write the name of hIS company.
3. Enter the total number of unique product terms
found In all eight outputs. Repeated terms
count only once.
4. Output Inverter Option. Under the appropriate
output deSignation speCify a T when the high
(true) level IS desired on the output for the
given Input conditions. SpeCify a 'C' If the
complement IS needed.
5. MatriX
a. Input data. This block IS used to deSCribe
what comprises each of the 96 (maxl'mum)
product terms. In each row, oppoSIte the
appropriate Product Term number, informa·
tlon on the fourteen Input Data locations is
entered. Information must be entered on all
14 Inputs.
1). Enter an "H" under the appropriate
Input deSignation if that particular input
appears In the product term as a high
(true) level.
2). Enter an "L" under the appropriate in·
put designation If that particular input
appears In the product term as a low
(complemented) level.
3). Enter an "X" under the appropriate input
designation if that particular input does
not appear in the product term.
If less than 96 product terms are used leave
all spaces for the unused terms blank.
b. Output Data. This block IS used to describe
the outputs on which the product terms
appear.
1). Enter a '+' under the appropriate output
designation if the product term is can·
tained in that output's expression.
2). Leave a location blank if the product
term is not contained in that output's
expression.
1·201
01
truth table/order blank
1. PART NO. - (DM7575, DM8575, DM7576, DM8576)
2. CUSTOMER IDENTIFICATION-
3. TOTAL NO. OF UNIQUE PRODUCT TERMS USED (Repeated Terms Count Only Once)
It)
.....
co
:E
Q
......
It)
.....
It)
.....
:E
4. OUTPUT INVERTER OPTION
It)
5. MATRIX
PRODUCT
TERM
OUTPUT DATA
INPUT DATA
1'4 1'3 1'2 111 1'0 19
Is
17
Is
15
14
13
12
I,
Fs F5 F4 F3 F2 F,
FS F7
1
2
3
4
Q
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1-202
,
c
s:-...I
truth table/order blank (con't)
PRODUCT
TERM
INPUT DATA
1'4 1'3 112 111 1'0
19
Is
17
Is
U'I
-...I
U'I
OUTPUT DATA
Is
14 13
12
I,
Fa F7
.......
C
F6 Fs F4 F3 F2 F,
43
44
45
46
47
s:00
U'I
-...I
U'I
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
D
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
1-203
o
en
It)
CO
:E
~s
Series 54/74
Q
.......
o
en
It)
I'
:E
DM7590/DM8590(SN54165/SN74165)
8-bit parallel-in serial-out shift register
Q
general description
There is no difference between the Clock input
and the Clock Inhibit input. Their functions may
be reversed if ease of layout results.
The OM7590/0M8590 utilizes Series 54/74 compatible TTL circuitry to provide an eight-bit
parallel-in serial-out shift register designed to
operate at frequencies of 20 MHz. The device also
features gating to inhibit clocking, parallel load
control, and both Q and Q outputs from the last
flip flop for added flexibility.
Clocking occurs on the positive-going transition
of the Clock input.
Data on the 01 through 08 inputs will be entered
on the negative-going transition of the Load input.
This information is entered independent of the
state of the Clock, Clock Inhibit, or Serial Input
lines. Information on these parallel inputs may be
changed while the Load line is enabled thus changing the information in the register.
characteristics
The Clock Inhibit input, when in the logical "1"
state, will inhibit the Clock. It must be in the
logical "0" state for clocking to occur.
The logic level applied to the Serial Input is entered
into the first flip flop when the register is clocked.
logic and connection diagrams
Dual-In-Line and Flat Package
CLOCK
1-204
Vee INHIIIT 1M
01
D2
0'
LOAU CLOCK OS
01
01
DI
SERIAL
..... T Q
II
GilD
c
~
.....
absolute maximum ratings
+7V
+5.5V
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range DM7590
DM8590
electrical characteristics
C1I
CD
0
.......
C
~
10
_65°C to +150 o C
_55°C to +125°C
O°C to +70°C
CO
C1I
CD
0
(Note 1)
CONDITION
PARAMETER
MIN
TYP
MAX
-1.5
Vee == 5 OV. TA = 25°C. liN"" -12 mA
Input Diode Clamp Voltage
UNITS
V
Logical "1" Input Voltage
DM7590
DM8590
Vee ==4.5V
Vee 4.75V
Logical "0" Input Voltage
OM7590
DM8590
Vee = 4.5V
Vee 4.75V
Logical "," Output Voltage
DM7590
DM8590
V ee =45V
Vee 4.75V
lOUT = -800 JlA
Logical "0" Output Voltage
DM7590
DMH5!IU
Vee = 4.5V
Vee 4.75V
lOUT = 16mA
DM7590
DM8590
Ver "" 5.5V
Vee 5.25V
V IN == 2.4V
40
Logical "1" Input Current
(Load Input)
DM7590
DM8590
~~~ == ~'~~V
V IN
BO
Logical "1" Input Current
DM7590
DM8590
~~~ ~:~~V
V 1N = 5.SV
Logical "0" Input Current
DM7590
DM8590
~~~ = ~'~~V
V IN = O.4V
Logical "0" Input Current
(Load Input)
DM7590
OMB590
~~~ = :'~~V
VIN
Output Short Circuit Current
DM7590
DM8590
~~~: ~:~~V
-55
rnA
Power Supply Current
DM7590
DMB590
Vee = 5.5V
Vee - 5.25V
40
63
rnA
Vee = 5.0V. TA = 2SoC
35
50
ns
Logical "," Input Current
(All Inputs Except Load Input)
(All Inputs Except Load Input)
Propagation Delay to a Logical "0"
from Clock to a or Q, !PdO
Propagation Delay to a logical ","
=
V
2.0
OB
'"
2.4
V
0.4
2.4V
V
"A
"A
rnA
= O.4V
V OUT = OV
V
-20
-18
-1.6
rnA
-3.2
rnA
26
40
ns
Propagation Delay to a Logical "0"
from 0 8 to Q or 0, t p dO(D81
36
50
ns
Propagation Delay to a Logical "1"
from DB to 0 or 0, tpd1 (08)
25
40
ns
Propagation Delay to a Logical "0"
from Load to Q or 0., tpdClOosd)
42
60
ns
34
50
ns
23
40
ns
from Clock to
a or Q. tpd1
Vee'" SOV, TA = 25°C
Propagation Delay to a Logical "1"
from Load to Q or
tpd 1 (load)
a,
Minimum Time That Serial Input Data
Must Be Set Up Prior to Clock Pulse,
tset
up
(clock)
Minimum Time That Senal Input Data
Must Be Held after Clock Pulse,
ns
!t.old (clock)
Mmimum Time That 0 1 -08 Input
Data Must Be Set Up Prior to Load
Pulse Termination, "tset UP (load)
10
25
Minimum Time That 0 1 -08 Input
Data Must Be Held after to Load
Pulse Termination, thold (load)
ns
ns
Minimum Clock Pulse Width
Vee =S.OV, TA =2SoC
25
35
Minimum Load Pulse Width
Vee = S.OV. TA = 2SoC
24
35
Maximum Shift Frequency
Vee = 5.0V. TA = 2SoC,40%-60%
DutY Cycle
14
20
ns
ns
MH,
Note 1: Unless otherwise specified, limits shown apply from -55°C to +1250 C for the DM7590 and
ci'c to +7ci'C for the DM8590. Typical values apply to supply voltages of 5.0V.
1·205
III
an
en
CD
Series 54/74
00
:E
o
........
an
en
CD
.....
:E
o
an
en
an
00
:E
o
........
an
m
an
.....
:E
o
DM7595/DM8595 4096-bit bipolar ROM
DM7695/DM8695 4096-bit bipolar ROM
general description
features
The DM7595/DM8595 and DM7695/DM8695 are
4096-bit bipolar mask-programmable ROMs organized as 512 eight-bit words_ Nine address inputs
select the desired one-of-512 words. Four enable
lines are used to either enable or disable the
circuit. The two devices differ in the enable logic.
Truth tables and logic diagrams for each device
are shown below. Open collector outputs allow for
expansion to greater number of words.
• Series 54/74 specification compatibility
• Pin compatible with monolithic memories
5240/6240
• Typical address time - 90 ns
• Open collector output
logic and connection diagrams
Dual-In-Line Package
ENABLES
BINARY
Vee
OUTPUTS
SElECT
As
NC
I"
22
23
21
"
20
18
16
17
15
14
-
r-
,
I
A1
~
• ,
3
6
1
TOP VIEW
logic diagrams and truth tables for enable circuitry
DM7585/DM8595
II
IE'~'
I
I E, "
I E, 21
I
L _______ ...J
., ·2 " .
DM7585/DM8595
0
I
X
X
X
0
X
I
X
X
0
X
X
1
X
0
X
X
X
1
OUTPUT
Read Stored Data
logltla''''''
logical"'"
logical"'"
Loglca''''''
X:t Don't Care
ENABLE =
DM7695/DM8696
r-I;-------,
I~~'
I
I~. :
I
.... _______ ..JI
IE,
E, . E2 . E3 . 'E.
., " "
1
"
X
X
0
X
0
X
DM7696/DM8695
X
0
X
X
0
1
X
1
X= Don't Care
ENABLE = E, '
1-206
B
Ao
As
As_ _ _ _ _
~__
A3_ _ _
Az_ _AI_ _- J
__
BINARY SELECT
,-------,
I ..
I
13
1
OUTPUT
Read Stored Data
Read Stored Data
Disable
Disable
E2 + E3 '
E.
•
0,
10
02
11 ,,2
03
~
OUTPUTS
GND
absolute maximum ratings
(Note 1)
operating conditions
MIN
Supply Voltage
I nput Voltage
Output Voltage
7V
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
5.5V
5.5V
_65°C to +150°C
300°C
electrical characteristics
Supply Voltage (VCC)
DM7595, DM7695
DM8595, DM8695
Temperature (T A)
DM7595, DM7695
DM8595, DM8695
4.5
4.75
-55
o
MAX
UNITS
5.5
5.25
+125
70
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UN'lTS
Logical "1" Input Voltage
Vee;;: Min
Logical "0" Input Voltage
Vee
=
Mm
Logical "1" Output Current
Vee
=
Max
Logical "0" Output Voltage
Vee
=
Min
Logical "1" Input Current
Vee = Max
Y'N ° 24V
Vee ;;:Max
Y'N ° 5 5V
1
mA
Y'N °04V
-10
mA
2
V OUT ° 5 5V
Vee
= Max
Supply Current (each device)
Vee
=
Max
Chip Enabled
Input Clamp Voltage
Vee;;: Min
liN o-12mA
Propagation Delay to a Logical "0" from
Vee ° 50V
TA ~ 25°C
CL ° 30 pF
Vee ~ 50V
TA ~ 25°C
CL
Propagation Delay to a Logical "1" from
Enable to Output, tpd1
Propagation Delay to a Logical "1" from
Enable to Output,
tpdO
Address to Output,
tpdO
Address to Output, tpdl
50
IOLo12mA
Loglcat "0" Input Current
Propagation Delay to a Logical "0" from
V
0.8
04
40
103
-15
158
V
J1A
V
J1A
mA
V
30
ns
30 pF
100
ns
Vee ~ 50V
TA ~ 25°C
CL ° 30 pF
30
ns
Vee ° 5 OV
TA ~ 25°C
CL o30pF
80
ns
~
o
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electncal Characteristics" provides conditIOns for actual device operation
Note .2: Unless otherWise speCified mm/max limits apply across the -55°e to +125°C temperature range for the DM7595
and DM7695 and across the O°C to 70°C range for the DM8595 and DM8695 AU tYPlcals are given for Vee = 5.0V and
TAo 25°C.
SO-column card program data format
Col. 1-3: 3 Character ID code any 3 AlphaNumeric characters. Must be the same on all cards
associated with a particular pattern, but different
for the ID code used on other patterns. The
purpose of this code is to prevent mixing of cards.
Col. 4: (Blank)
Col. 5-12: Word Data. Order is08 (most significant)
to 01 (least significant). Note 1. Characters - For
TTL high level are: H or 1. Characters For
TTL low are L or O. "Don't Care" is X.
Col. 13: (Blank)
Col. 14-21: Word Data Col. 22: (Blank)
same format as 5-12.
Col. 23-30: Word Data
Col. 31: (Blank)
Col. 32-39: Word Data
Col. 40: (Blank)
Col.
Col.
Col.
Col.
41-48: Word Data
49: (Blank)
50-57: Word Data
58: (Blank)
Col. 59-66: Word Data
Col. 67: (Blank)
Col. 68-75: Word Data
Col. 76-78: (Blank)
Col. 79-80: Card sequence number. 1 to 64.
Leading zeros may be punched or suppressed.
(Note 2)
NOTE 1. The words are listed In sequence beginning on the first card with the word associated with address 0 and ending on
the last card with the word associated with address 512, If all 4096·blts are programmed. Address input AS is the most
significant; AO. the least significant.
NOTE 2. Card sequence numbers reference a specific group of 8 words, I.e.;
Card 01: Word address 0 to 7
Card 02: Word address 8 to 15
Card 03: Word address 16 to 23
Card 64: Word address 504 to 511.
1-207
Series 54/74
DM7596/DM8596 TRI-STATE® 4096-bit bipolar ROM
DM7696/DM8696 TRI-STATE 4096-bit bipolar ROM
general description
features
The DM7596/DM8596 and DM7696/DM8696 are
4096-bit bipolar mask-programmable ROMs organized as 512 eight-bit words. Nine address inputs
select the desired one-of-512 words. Four enable
lines are used to either enable or disable the
circuit. The two devices differ in the enable logic.
Truth tables and logic diagrams for each device
are shown below. TRI-STATE outputs allow for
expansion to greater numbers of words without
sacrifice in speed as would be evidenced by opencollector outputs.
• Series 54/74 specification compatibility
• Pin compatible with
5240/6240
monolithic memories
• Typical address time - 90 ns
• TRI-STATE outputs
logic and connection diagrams
Dual-In-Line Package
BINARY
SELECT
Vee
As
NC
I"
ENABLES
E,
E2
Z1
22
23
OUTPUTS
~-~-~• •,..--~---.
E3
20
E4
19
0,
18
17
16
15
14
"
f-
A,
A,
A,
,
2
,
4
3
6
, •
TOP VIEW
logic diagrams and truth tables for enable circuitry
18
.,
20
,
DM7596/DM8596
r--------,
I E.
I
IE,~g
I
I
(2
DM7596/DM8596
E,
X
IL E,_______
Z1
...JI
X
X
x
=
r-,,-----..,
I"
IE, "
IE,
X
X
1
X
X
OUTPUT
Read Stored Data
HI-Z
HI-Z
HI -2
HI- Z
E, • E2 • E3 • E4
DM7696/DM8696
OUTPUT
I
20
:E,
'- _______ ...JI
Z1
"
X
X
Don't Care
ENABLE'"
DM7696/DM8696
E,
X
x
X
0
X
0
AeadStored Data
Read Stored Data
HI-Z
HI-Z
X'" Don t Care
ENABLE'" e\ . E2 + E3 • E4
1-208
9
"
11
112
absolute maximum ratings
(Note 1)
operating conditions
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7V
5.5V
5.5V
-65°C to +150·C
300°C
c
3:
Supply Voltage (VCC)
DM7596, DM7696
DM8596, DM8696
Temperature (T A)
DM7596, DM7696
DM8596, DM8696
4.5
4.75
-55
0
-...I
C1I
MAX
5.5
5.25
+125
70
UNITS
CD
Q)
"C
V
V
3:
00
C1I
°c
°c
CD
Q)
electrical characteristics
C
(Note 2)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
3:
-...I
Q)
V
CD
V
Q)
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage DM7596/DM7696
DM8596/DM8696
Vee
Logical "0" Output Voltage
Vee::: Min
10L
Third State Output Current
Vee::: Max
Vo=04Vor24V
Logical "1" Input Current
Vee::: Max
V ,N = 2 4V
Vee:::; Max
V ,N = 5 5V
1
/lA
Logical "0" Input Current
Vee::: Max
V ,N =04V
-10
rnA
0:=
Min
2
08
lOUT = -2.0 mA
5.2 mA
lOUT -
"C
V
24
3:
00
04
= 12 rnA
-30
/lA
40
/lA
-70
rnA
158
rnA
Output Short Circuit Current (Note 3)
Vee == Max
VOUT
Vee = Max
Chip DISabled
Input Clamp Voltage
Vee = Min
V ,N =-12mA
Propagation Delay to a Logical "0" from
Vee = 50V
TA = 25°c
RL = 4002
C L = 50 pF
100
ns
Vee = 5.0V
TA = 25°C
CL
RL = 4002
= 50 pF
70
ns
Address to Output,
tpdO
Propagation Delay to a Logical "1" from
Address to Output.
tpdl
OV
±40
Supply Current (each deVice)
==
106
Q)
V
CD
Q)
0
V
-15
Delay from Enable to High Impedance
State (from Logical "1" Level), t'H
Vcc = 5.0V
TA = 25°C
10
ns
Delay from Enable to High Impedance
State (from Logical "0" Level), tOH
Vee = 50V
T A = 25°C
15
ns
Delay from Enable to Logical "'"
Level (from High Impedance State), tH1
Vee = 5.0V
TA = 25°C
CL
= 50 pF
25
ns
Delay from Enable to Logical "0"
Level (from High Impedance State I. tHO
Vee = 5.0V
TA = 25°C
CL
= 50 pF
30
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" provides conditions for actual deVice operation
Note 2: Unless otherwise specified minimax limits apply across the -5SoC to +12S"'C temperature range for the DM7596
and DM7696 and across the O°c to 70°C range for the DM8596 and DM8696 All tYPlcals are given for Vee'" 5 OV and
TA" 25"C
1-209
SO-column card program data format
Col. 1-3: 3 Character ID code any 3 AlphaNumeric characters. Must be the same on all cards
associated with a particular pattern, but different
for the ID code used on other patterns. The
purpose of this code is to prevent mixing of cards.
Col. 4: (Blank)
Col. 5-12: Word Data. Order is 08 (most significant)
to 01 (least significant). Note 1. Characters - For
TTL high level are: H or 1. Characters - For
TTL low are L or O. "Don't Care" is X.
Col. 13: (Blank)
Col. 14-21: Word Data - same format as 5-12.
Col. 22: (Blank)
Col. 23-30: Word Data
Col. 31: (Blank)
CD
en
Ln
CO
:iE
o
"enCD
....Ln
:iE
Col. 32-39: Word Data
Col. 40: (Blank)
Col. 41-48: Word Data
Col. 49: (Blank)
Col. 50-57: Word Data
Col. 58: (Blank)
Col. 59-66: Word Data
Col. 67: (Blank)
Col. 68-75: Word Data
Col. 76-78: (Blank)
Col. 79-80: Card sequence number. 1 to 64.
Leading zeros may be punched or suppressed.
(Note 2)
NOTE 1. The words are listed in sequence beginning on the first card with the word associated with address 0 and ending on
the last card with the word associated with address 512, if all 4096·bits are programmed. Address Input AS IS the most
significant; AO, the least significant.
o
NOTE 2. Card sequence numbers reference a specific group of 8 words, i.e.;
Card 01: Word address 0 to 7
Card 02: Word address 8 to 15
Card 03: Word address 16 to 23
Card 64: Word address 504 to 511
1-210
c
Series 54/74
3:
......
en
CD
......
.......
c
DM7597/DM8597 TRI-STATE@'024-bit read only memory
3:
00
general description
en
CD
The DM7597/DM8597 is a custom-programmed
read-only memory organized as 256 four-bit words.
Selection of the proper word is accompl ished
through the eight select inputs. Two overriding
memory enable inputs are provided, which when
mask-programmed in one of three options described will cause all four outputs to either read
the normal memory contents or go to the "high
impedance" state. In this state both the upper and
lower output transistors are turned off. The outputs may therefore be paralleled to increase word
......
capacity; since in the high-impedance state they
present only a minimal load to the active output.
features
•
Pin compatible with SN54187/SN74187
•
35 ns typical delay from address to output
•
Can be expanded to 32,768 4-bit words by
simple paralleling of outputs
•
Programmable memory enable inputs
logic diagram
D
171
MEMORY
rME1"'''~1==::::r:::)---~liJ---""-lrn.---Y;;;;---_.J
ENA8LElME20(!4)
::~~
OPTIONZ
connection diagram
Dual-In-Line Package
Oth.optIooIDRlIItIIIory ........ lllm
MEI~
ME2~
OPTION 3
truth table
T·ABlE of Programmable Memory Enable Options
OPTION
ME.
ME2
1
0
0
X
1
X
2
•
0
X
3
•
X
0
1
OUTPUTS
Normal
HIGH Impedance
HIGH Impedance
1
X
0
Normal
0
Normal
1
X
HIGH Impedance
HIGH Impedance
HIGH Impedance
HIGH Impedance
x = don't care
TOP VIEW
1-211
"
0)
an
absolute maximum ratings
00
(Note 1)
::E
Q
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM7597
DM8597
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
.......
"an
"::E
0)
Q
7V
5.5V
5.5V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
MIN
TVP
UNITS
Logical "1" Input Voltage
Vee=45V
Vee 475V
Logical "0" Input Voltage
DM7597
DM8597
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Voltage
DM7597
DM8597
Vee
Vee = 4.5V
4.75V
10 = -2 rnA
10 = -5.2 rnA
Logical "0" Output Voltage
DM7597
DM8597
Vee = 4.5V
Vee =4.75V
10 = 16 rnA
Third State Output Current
DM7597
DM8597
Vee = 5.5V
Vee - 5.25V
Vo = 204V
Vo = Oo4V
40
-40
j.lA
j.lA
Logical "1" Input Current
DM7597
DM8597
Vee = 5.5V
Vee 525V
VIN = 2 4V
40
j.lA
DM7597
DM8597
Vee = 5.5V
Vee 5.25V
V ,N = 5.5V
1.0
rnA
DM7597
DM8597
Vee = 5.5V
Vee - 5.25V
V ,N = Oo4V
-1.0
rnA
DM7597
DM8597
Vee = 5.5V
Vee - 5.25V
Vo = O.OV
DM7597
DM8597
Vee = 5.5V
Vee = 5.25V
All Inputs at GND
DM7597
DM8597
Vee = 4.5V
Vee - 4.75V
lIN = -12 rnA
Logical "a" Input Current
Output Short Circuit Current
(Note 31
Supply Current
Input Clamp Voltage
2.0
V
0.8
204
V
V
004
-20
75
V
-70
rnA
110
rnA
-1.5
V
39
60
ns
Vee = 5.0V
TA = 25°C
31
60
ns
State (from Logical "1" Levell, t1H
Vee = 5.0V
TA = 25°C
13
30
ns
Delay from Enable to High Impedance
State (from Logical "0" Level), tOH
Vee = 5.0V
TA = 25°e
16
30
ns
Delay from Enable to Logical "1" Level
(from High Impedance State), tH1
Vee = 5.0V
TA = 25°C
18
30
ns
Delay from Enable to Logical "0" Level
(from High Impedance State), tHo
Vee = 5.0V
TA = 25°C
20
30
ns
Propagation Delay to a Logical "0" from
Address to Output, 'tpdO
Vee = 5.0V
T A =25°C
Propagation Delay to a Logical "1" from
Address to Output, tpd1
Delay from Enable to High Impedance
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Teml1erature~ Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electncal Characteristics" provides conditions
for actual deVice operation.
Note 2: Unless otherWise specified mm/max limits apply across the -5SoC to +12SoC temperature
range for the DM7597 and"across the O°C to 70°C range for the DM8597. All typicals are given for
Vee = 5.0V and T A = 25°e.
Note 3: Only one output at a time should be shorted.
1·212
MAX
DM7597
DM8597
ordering instructions
Programming instructions for the DM7597 or
DM8597 are solicited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card'
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.
Each card in the data deck prepared by the pur·
chaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched accord ing to the data card format shown.
10-13
14
15-18
19
20-23
24
25·28
29
30-33
34
35-38
39
4043
supplementary ordering data
44
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.
4548
49
50-51
52
53-55
data card format
56
Column
1- 3
4
5- 7
8- 9
57 -58
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs V4, V3, V2,
and Vl in that order) for the first set of
outputs specified on the card. H = high·
level output, L = low·level output, X =
output irrelevant.
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H", "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
6().61
Punch "OM"
Punch a "-" (Minus sign)
62-65
Punch 7597 or 8597
Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.
66·70
Blank
71
Punch 1, 2, or 3 for memory enable
option desired (assumed 1 if not punched).
59
Blank
Blank
1·213
o
00
en
an
00
:E
c
illS
Series 54/74
.......
00
en
an
":E
c
®
DM7598/DM8598 TRI-STATE
256-bit read only memory
general description
The DM7598/DM8598 is a customer programmed
256-bit read-only memory organized as 32 B-bit
words. A five-bit input code selects the appropriate
word which then appears on the eight outputs. An
enable input overrides the select inputs and blanks
all outputs.
Although the DM7598/DM8598 can have its outputs tied together for word-expansion, the outputs
are not open-collector, but rather the familiartotempole output with the capability of being placed
in a "third-state". This unique three state concept
allows outputs to be tied together and then connected to a common bus line. Normal TTL outputs
cannot be connected due to the low-impedance
logical "1" output current which one device would
have to sink from the other. If however, on all but
one of the connected devices both the upper and
lower output transistors are turned off, then the
one remaining device in the normal low impedance
state will have to supply to or sink from the other
devices only a small amount of leakage current.
This is exactly what occurs on the DM75981
DM8598.
A typical system connection demonstrating expansion to greater numbers of words is shown in Figure 1. While it is true that in a TTL system opencollector gates could be used to perform the logic
function of these three-state elements, neither
waveform integrity nor optimum 'speed wou Id be
achieved. The low output impedance of the
DM 7598/0M8598 provides good capacitance drive
capability and rapid transition from the logical
"0" to logical "1" level thus assuring both speed
and waveform integrity.
It is possible to connect as many as 128 DM8598s
to a common bus line and still have adequate drive
capability to allow fan out from the bus. The
example shown in Figure 2 indicates how this
guarantee can be made under worst-case conditions.
Figure 3 indicates how multiple packages can be
used to increase word length.
features
•
•
•
•
•
•
•
•
Pin compatible with SN5488/SN7488
Organized as 32 8-bit words
Full internal decoding
30 ns typical access time
350 mW typical power dissipation
Input clamp diodes
Designed for bus-organized systems
Strobe override
logic and connection diagrams
I",....
Dual-I "-Line Package
L",....
112)V
I ...
'--I,....:><>--+-++++t
IIl)V
-
J t-...
'-00
,....--+-t-t-t-t-t-...
(14)
1
....
115)
v
PROGRAMMING
'OT
SIIDWN
1-214
c
....3:
absolute maximum ratings
(Note 1)
Supply Voltage
7V
5.5V
5.5V
-55°C to +125°C
O°C to +70°C
_65°C to +15O°C
300°C
Input Voltage
Output Voltage
Operating Temperature Range DM7598
DM8598
Storage Temperature Range
lead Temperature {Soldenng, 10 sec)
UI
CD
00
"-
c
3:
00
UI
electrical characteristics
CD
(Note 2)
PARAMETER
00
CONDITIONS
Logical "1" Input Voltage
DM7598
DM8598
Logical "0" Input Voltage
DM7598 ~~4.5V
DM8598 Vee"475V
Logical "1" Output Voltage
DM7598
DM8598
Vee" 4 5V
Vee 475V
Logical "0" Output Voltage
DM7598
DM8598
Vee "45V
Vee 475V
10
ThIrd State Output Current
DM7598
DM8598
Vee"55V
Vee 525V
Va" 24V
Va" 04V
DM7598
DM8598
Vee" 5 5V
Vee 5 25V
Vee"45V
Vee - 4.75V
MIN
TYP
MAX
20
V
08
lo=-2mA
52mA
10
24
V
V
04
+12 mA
=
UNITS
±4Q
V
±40
IlA
IlA
40
IlA
80
IlA
1
mA
Logical "1" Input Current
Address Inputs
Enable Input
Any Input
DM7~~~"55V
V ,N
DM7598
DMS59!l
Y'N " 5 5V
DM8598
V ee-"-525V
" 24V
Vee" 55V
V~e" 525V
0
Logical "0" Input Current
Address Inputs
DM7598
DM8598
Enable Input
DM7598
DM8598
Vee" 55V
Vee 5.25V
V 1N
0 4V
-1 6
mA
Vee" 5 5V
5 25V
V ,N "04V
-32
mA
Vee" 5 5V
Vee "52511
Va" OV
-It ee "
Output Short CircUIt Cunent
(Note 3)
DM7598
DM8598
Su pply Current
DM7598
Vee" 5 5V
DM859SI-Vee "52511
Input Clamp Voltage
DM7598
Vee" 4 5V
DM8598-~~ 4 75V
Propagation Delay to a Logical "0" from
=
Inputs Grounded
'IN =
-20
70
-12 mA
-70
mA
99
mA
-1 5
V
Address to Output, tpdO
Vee" 50V
T A " 25°C
29
50
ns
Propagation Delay to a Logical "1" from
Address to Output, tpdl
Vee "50V
T A " 25°C
33
50
ns
Delay from Enable to High Impedance
State (from Logical "1" Level).tlH
Vee"50V
T A "25°C
CL
"
5 pF
13
20
ns
Delay from Enable to High Impedance
State (from Logical "0" Levell. tOH
V ec "50V
T A " 25°C
CL
"
5 pF
24
36
ns
Delay from Enable to Logical "1" Level
(from High Impedance State). tHl
Vee" 5.0V
T A " 25°C
CL "50pF
16
25
ns
Delay from Enable to Logical "0" Level
(from High Impedance State), tHO
Vee" 5.0V
T A " 25°C
CL
26
40
ns
"
50 pF
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operatmg Temperature Range" they are not meant to imply that the
deVices should be operated at these limits. The table of "Electncal Characteristics" prOVides conditions
for actual device operation.
Note 2: Unless otherWise specified minimax limits apply across the _55°C to +125°C temperature
range for the DM7598 and across the O°C to 70°C range for the DM8598. All tYPlcals are given for
VCC = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
1-215
co
en
It)
co
:E
Q
......
co
en
typical applications
j'"
UTPUTS
OFO THER
"E" DRIES
BUS!
LINE
It)
.....
:E
Y,
II
Y2
V3
Q
Y4
Vs
Y6
Y7
1I I
Y,
Ye
;--<
DMl598IPM8598
Y2
YJ
r"E
A
8
C
0
Y4
Y5
V7
Y,
Ys
OM7598/DM8598
ME
A.
E
CO
E
11
NARY
}
TOBICTINI'IJTS
SElE
OFO THER
ME. DRIES
TO ENABLE INPUTS OF OTHER MEMORIES
, ,
t , t. t.t,
2
.
.,
7
12
1011
DMS4154/DM74154
A
A
8
CD
E
IIII
F
H
1
J
C
0
G,
G,
ENABLE
lOW
II
J
BINARVSELECTREGISTER
FIGURE 1. Expansion to Larger Word Capacity
120mA
GATEDINlP
LOW IMPEDANCE
LOGICAL"'"
STATE
GATED1NlD
HIGH IMPEDANCE
40"Ax121-50BmA
GATED INTO
HIGH IMPEDANCE
STATE
OTHEROM759B1DM85!18
OUTPUTS
FIGURE 2.
16 BIT WORD
DMl598IDM8598
ENABLE
ABC
0
E
ABC
0
E
FIGURE 3.
1-216
tt
13
1415
c
s:.....
DM7598AA TRUTH TABLE
U1
(g
00
A special pattern has been generated for the DM7598/DM8598. The AA pattern provides a sine table. The 5-bit
input code linearly divides 90° into 32 equal segments. Each 8-bit output IS therefore the sme of the angle
applied.
......
C
s:00
U1
EXAMPLE: Input 11010 means 26/32 of 90°, or about 73°. The corresponding output 11110100 mdicates
(1/2 + 1/4 + 1/8 + 1/16 + 1/64) or about .95, which is close to the sine of 73°. Roundmg-off has not been
employed, smce without roundmg-off It IS possible to extend the accuracy with additional ROMs.
(g
00
The truth table is shown:
INPUTS
WORD
OUTPUTS
BINARY SELECT
ENABLE
E
D
C
B
A
ME
YB
Y7
Y6
Y5
Y4
Y3
Y2
Yl
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
2
0
0
0
1
0
0
0
0
0
1
1
0
0
1
3
0
0
0
1
1
0
0
0
1
0
0
1
0
1
4
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
1
0
5
0
0
1
0
1
0
1
0
6
0
0
1
1
0
0
0
1
0
0
1
0
1
0
7
0
0
1
1
1
0
0
1
0
1
0
1
0
8
9
10
11
12
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
0
0
0
a
a
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
1
1
1
0
13
0
1
1
0
1
0
1
0
0
1
1
a
0
0
14
0
1
1
1
0
0
1
0
1
0
0
0
1
0
15
0
1
1
1
1
0
1
0
1
0
1
0
1
1
16
1
0
0
0
0
0
0
1
1
0
0
1
17
1
0
0
0
1
0
1
1
0
1
1
1
0
1
18
1
0
0
1
0
0
1
1
0
0
0
0
1
19
1
0
0
1
1
0
1
1
0
0
1
20
1
0
1
0
0
0
1
1
0
1
0
0
1
1
21
1
0
1
0
1
0
1
1
0
1
1
22
1
0
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
23
1
0
1
1
1
0
1
1
1
0
0
1
1
1
24
1
1
0
0
0
0
1
1
1
0
1
1
0
0
25
1
1
0
0
1
0
1
1
1
1
0
0
0
1
26
1
1
0
1
0
0
1
1
1
1
0
0
0
0
0
1
1
Hi-Z
HI-Z
30
1
1
1
1
0
0
1
1
1
1
1
31
1
1
1
1
1
0
1
1
1
1
All
X
X
X
X
X
1
Hi-Z
1
Hi-Z
1
0
0
1
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
27
1
1
0
1
1
0
1
1
1
1
1
28
1
1
1
0
0
1
1
1
1
1
29
1
1
1
0
0
1
0
1
1
1
1
1
D
0
1
0
0
1
1
0
1
1
1
0
1
1
0
x = Don't Care
1-217
ClO
en
It)
TRUTH TABLE/ORDER BLANK
ClO
:E
c
The output levels are not shown on the truth table since the customer specifies the output condition he deSIres
at each of the eight outputs for each of the 32 words (256 bits). The customer does this by filling ~ut the
Truth Table on this data sheet, and sending It in with his purchase order.
........
ClO
en
.....
:E
It)
c
INPUTS
WORD
OUTPUTS
BINARY SELECT
EO:ABLE
E
D
C
B
A
ME
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
11
0
0
0
0
12
0
0
1
2
3
4
5
6
7
8
9
10
1
a
1
0
0
0
1
1
1
1
0
1
0
1
0
1
1
0
1
1
1
1
15
0
1
1
16
1
1
0
0
1
0
0
0
17
1
a
a
0
1
0
0
1
19
1
0
1
20
1
1
0
1
1
22
23
24
25
26
27
1
1
28
1
1
1
29
1
1
1
30
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
21
0
0
0
0
0
1
1
1
1
1
0
1
a
18
31
1
1
1
1
1
0
All
X
X
X
X
X
1
1
0
0
0
0
Y4
Y3
Y2
Y1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
0
0
0
1
Y5
0
0
0
1
Y6
a
14
1
Y7
0
0
0
0
13
1
1
YB
0
0
0
0
0
0
0
0
0
0
0
0
x
= Don't Care
Notice: This sheet must be completed and signed by an authorized representative of the customer's company before an
order can be entered.
' ,
To be used by National only
AuthorIZed Representative
Date
_ _ _ _ _ _ _ _ Part Number
_ _ _ _ _ _ _ _ S.O. Number
Company
_ _ _ _ _ _ _ _ Date Received
DeSIred Part
1-218
o
DM7598
o
DM8598
illS
Series 54/74
DM7599/DM8599 TRI-STATE®
64-bit random access rea_d/write memory
general description
The DM7599/DM8599 is a fully decoded 64-bit
RAM organized as 16 4-bit words. The-memory
is addressed by applying a binary number to the,
four Address inputs. After addressing, information
may be either written into or read from the
memory. To write, both the Memory Enable and
the Write Enable' inputs must be in the logical "0"
state. Information applied to the four Write inputs
will then be written into the addressed location.
To read information from the memory the Memory Enable input must be in the logical "0" state
and the Write Enable input in the logical "1" state.
Information will be read as the complement of
what was written into the' memory. When the
Memory Enable input is in the logical "1". state,
,the outputs will go to the high-impedance state_
This allows up to 128 memories to be connected
to a common bus-line without the use of pull-up
resistors. All memories except one are gated into
the high-impedance while the one selected memory exhibits the normally totem-pole low impedance output characteristics of TTL.
features
•
•
•
•
Series 54/74 compatible
Same pin-out as SN5489/SN7489
Organized- as 16 4-bit words
Expandable to 2048 4-bit words without additional resistors (DM8599 only)
20ns
• Typical access from chip enable
28ns
• Typical access tirne
400mW
• Typical power dissipation
block diagram
,.....
,ADDREII
.."
I~" Q-------lCj~>_----~------------!-----+_~:r~
..
" .......
"------t=~~--------------~--~~=r~
connection diagram
truth table
Dual-In-Line Package
.
..
MEMORY
ENABLE
WRITE
-ENABLE
Op,ERATION
0
0
0
'1
Write
Read
Comptement of Data
1
X
Hold
H.-Z State
OUTPUTS
HI-ZState
Stored In Memory
1-219
D
en
en
In
00
absolute maximum ratings
::E
(Note 1)
Supply Voltage
Q
Output Voltage
Time that two bus-connected devices may be In
oPPosite low impedance states simultaneously
en
en
_65°C to +150°C
Storage Temperature Range
Operating Temperature Range
7V
5.5V
5.5V
I nput Voltage
.......
_55°C to +12SoC
O°C to +70°C
DM7599
DMB599
Lead Temperature (Soldenng, 10 sec)
Indefinite
300°C
In
....
::E
Q
electrical cha racteristics
(Note 2)
CONOITIONS
PARAMETER
TYP
MAX
UNITS
Logical "1" Input Voltage
Vcc"'45V
Vee 475V
Logical "0" Input Voltage
DM7599
DMB599
V cc =45V
Vee - 4 75V
Logical "1" Output Voltage
DM7599
DMB599
Vcc=45V
Vee 475V
Logical "0" Output Voltage
DM7599
DMB599
Vee'" 4,5V
Vee 475V
lo=12mA
Third State Output Current
DM7599
DMB599
Vcc=55V
Vee 525V
Vo '" 0 4V
Vo '" 2 4V
±40
±40
~A
Logical "1" Input Current
DM7599
DMB599
Vee'" 5 5V
Vee - 525V
V IN ",24V
40
~A
DM7599
DM8599
Vee'" 5 5V
Vee 525V
VIN '" 5 5V
I
rnA
Logical "0" Input Current
DM7599
DM8599
Vcc"'SSV
Vee 525V
V IN '" 0 4V
-16
rnA
Output Short Circuit Current
(Note 3)
DM7599
DM8599
Vee'" 55V
Vee 525V
Supply Current
DM7599
DMB599
Vee'" 5 5V
Vee 525V
All Inputs at GND
Input Clamp Voltage
DM7599
DMB599
Vee "'45V
Vee 4.75V
liN'" -12 mA
V
20
OB
10 '" -2 rnA
lo=-S2mA
V
V
V
24
2.4
04
-30
80
V
-70
rnA
120
rnA
-15
V
Propagation Delay to a Logical "0" from
Address to Output, tpdO
Vee"" 5.DV
T A ", 25°C
2B
45
n,
PropagatIOn Delay to a Logical "1" from
Address to Output, t p d1
Vee'" SOV
TA '" 2SoC
27
45
n'
Delay from Memory Enable to High
Impedance State (from Logical "1"
Level), t1H
Vee'" S.OV
TA = 2SoC
12
20
n,
Delay from Memory Enable to High
Impedance State (from Logical "0"
Level), toH
Vee'" S,DV
TA = 2SoC
21
30
n'
Delay from Memory Enable to
Logical "1" Level (from High
Impedance State I. tHt
Vee=50V
TA '" 2SoC
14
20
n,
Delay from Memory Enable to
Logical "0" Level (from High
Impedance State), tHO
Vee = S.OV
T A '" 2SoC
19
30
n,
Write Enable Pulsewldth. twP
Vee'" S.DV, T A "" 2SoC
40
23
Setup Time. Data
Vee'" S.OV, TA '" 2SoC
0
-15
Hold Time, Data
Vee'" SOV. T A ::: 2SoC
0
-14
Setup Time Address
Vee'" S OV, T A = 2Soc
0
-17
Hold Time, Address
Vee'" S.DV, T A'" 25°C
5
-7
Sense Recovery Time
Vee = SOV, TA::o 2SoC
Note 1: "Absolute Maximum Rattngs" are those values beyond which the safety of the device cannot
be guaranteed, Except for "Operating Temperature Range" they are not meant to Imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" prOVides conditions
for actual device operation
Note 2: Unless otherwise speCified min/max limits apply across the -5SoC to +125°C temperature
range for the DM7599 and across the COc to 70°C range for the OM8599. All tYPlcals are given
for Vee '" S.OV and TAle 2SoC
Note 3: Only one output at a time should be shorted.
1-220
MIN
DM7599
DMB599
42
60
n'
n,
n,
n,
n,
n'
Series 54/74
DM75491 MOS-to-LED quad segment driver
DM75492 MOS-to-LED hex digit driver
features
general description
The DM75491 and DM75492 are interface circuits
designed to be used in conjunction with MOS
integrated circuits and common-cathode LED's in
serially addressed mUlti-digit displays_ The number of drivers required for this time-multiplexed
system is minimized as a result of the segmentaddress-and-digit-scan method of LED drive_
•
Source or sink capability
per driver (DM75491)
•
Sink capability per
driver (DM75492)
•
MOS compatability (low input current)
•
Low standby power
•
High-gain Darlington circuits
50 mA
250 mA
D
schematic and connection diagrams
DM75491 (each drover)
DM75492 (each drover)
11.1,8.14)
114,J,5,8,lD.12}
A - . . .JV1>1'v-....
--t
DM75492 Dual-In-Line Package
DM75491 Dual-In-Line Package
4.
14
lA
..
13
IE
4C
"
1C
3C
11
GND
TOP VIEW
3E
3A
"
2A
10
2C
Order Number DM75491N or DM75492N
See Package 22
1-221
absolute maximum ratings
Input Voltage Range (Note 1)
Collector Output Voltage (Note 2)
Collector Output to Input Voltage
Emitter to Ground Voltage (V I :::: SV)
Emitter to Input Voltage
Voltage at Vss Terminal With Respect to
Any Other Device Terminal
Collector Output Current
Each Collector Output
All Collector Outputs
Continuous Total Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
DM75491
DM75492
-5V to Vss
10V
10V
10V
SV
-SV to Vss
10V
10V
10V
10V
50mA
200mA
800mW
O°C to +70°C
-6SoC to +150°C
300°C
250mA
600mA
800mW
O°C to +70°C
-65°C to +150°C
300°C
dc electrical characteristics
DM75491 1Vss
= 10V. TA = O°C to +70°C unless otherwise notedl
PARAMETER
CONOITIONS
On State Collector Emitter Voltage
Input'" 8 5V through 1 kn, V F
tV CE ON )
Ie
=::
VC '" lOV, Ve ::: 0, liN
Off State Collector Current (Ie
Vc '" lOV, VE
I
'"
MAX
.9
5V,
50 mA
Off State Collector Current (Ie OFF)
OFF
TYP
MIN
Input'" 8.5V through 1 kU, Ve "" 5V,
Ie"" 50 rnA, TA =:: 2SoC
On State Collector Emitter Voltage (VeE ON!
'"
O. V IN
=::
1.5
V
100
7V
100
Input Current at MaXimum Input Voltage (II)
VIN '" 10V, V E =0, Ie =20mA
Emitter Reverse Current (I E )
VIN :: O. V E = 5V, Ie "" 0
22
~A
"A
mA
3.3
100
"A
1
mA
Current Into Vss Terminal (Iss)
DM754921VSS = 10V. TA
V
4Q,uA
'"
UNITS
1.2
= O°C to +70°C unless otherwise noted)
Low Level Output Voltage (Vod
MIN
CONDITIONS
PARAMETER
Low Level Output Voltage (Vod
Input
=::
6.5V through 1
kn,
lOUT
=
.9
TA '" 25°C
UNITS
MAX
TYP
250 rnA
Input'" 6 5V through 1 kn, lOUT'" 250 mA
1.2
V
15
V
High Level Output Current HOH)
VOH '" lOY, liN"" 40j..tA
200
High Level Output Current (lOH)
VOH = lOY, VIN = 5V
200
Input Current at MaXimum Input Voltage (Ill
V IN '" lOV, IOL = 20 rnA
22
Current Into Vss Terminal (Iss)
~A
"A
3.3
mA
1
rnA
ac switching characteristics
DM75491 1Vss
= 7.5V. T A = 25°C)
PARAMETER
CONDITIONS
Propagation Delay Time, Low to High Level Output (Collector) (tPLH )
V IH =45V,V e "'O,
Propagation Delay Time, High to Low' Level Output (Collector) (tPHL)
RL '" 200[2, C L = 15 pF
DM75492 (VSS
MIN
MAX
UNITS
100
ns
20
ns
= 7.5V. T A = 25°C)
PARAMETER
CONDITIONS
PlIOpagatlon Delay Time, Low to High Level Output (tPLH)
V 1H '" 7 5V, RL '" 39n,
Propagation Delay Time, High to Low Level Output (tPHd
CL '" 15pF
MIN
Note 1: The input is the only device terminal which may be negative with respect to ground.
Note 2: Voltage values are with respect to network ground terminal unless otherwise noted.
1-222
TYP
TYP
MAX
UNITS
300
ns
30
ns
c
~s
s:
.....
Series 54/74
CD
o
o
.......
c
s:CD
DM7800/DM8800 dual voltage translator
CD
general description
features
The DM7800/DM8800 are dual voltage translators
designed for interfacing between conventional TTL
or DTL voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices_ The design allows the user a wide latitude
in his selection of power supply voltages, thus providing custom control of the output swing_ The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required.
•
o
o
31 volt (max) output swing
•
1 mW power dissipation in normal state
•
Standard 5V power supply
•
Temperature range:
DM7800
DM8800
•
_55°C to +125°C
O°C to +70 o C
Compatible with all MOS devices
schematic and connection diagrams
D
"
Rl
20K
R2
45K
Metal Can Package
"'
t----tlH-OUTPUTK
OUTPUT X
t----[)D3
TopvrEW
....-"
'----
typical applications
Bipolar to MOS Interfacing
4-Channel Analog Switch
T
T
r------I
rlo1 ___ ~..,1
SWITCH l_L--.J'........
I
MM451
I
ANALOG INPUT 1"
·1
I
I
ANALOG INPUTZ
I
I
UTl
DR
TTL
I
INPUT
LEVElS
ANALOG INPUT 3
SWITCH 3_.L...I.J'........
I
I
I
SWIlCH
4-,,-"~-'-"'_..LL
'---r-',
ANALOG INPUT 4
II
ANALOG OUTPUT
-22' L _____
I
I
rJ---0
UTl~MOSSHIFT
OR
REGISTER
TTL
DM7100
I
INPUT~
LEVELS~
L1---f
-=
-IOV
I
-l
·Alllloilil.....5W1thlntilt Ilng:ol+8va1l1to-8.DIII
1-223
o
o
00
00
absolute maximum ratings
~
Q
Vee Supply Voltage
7.0V
V 2 Supply Voltage
-30V
V3 Supply Voltage
+30V
V 3,V 2 Voltage Differential
40V
Input Voltage
5.5V
_65°C to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
DM7800
DM8800
O°C to 70°C
Lead Temperature (Soldering, 10 sec)
300°C
"oo
00
"'~"
Q
electrical characteristics
(Note 1)
PARAMETER
CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
Logical "1" I nput Voltage
DM7800 Vce ~ 4.5V
DM8800 V ee -4.75V
Logical "0" Input Voltage
DM7800 Vee ~ 4.5V
DM8800 Vee - 4.75V
Logical "1" Input Current
DM7800 Vee~ 5.5V
DM8800 V ee - 5.25V
V 1N
2.4V
5
J.l.A
Logical "1" Input Current
DM7800 Vee~ 5.5V
DM8800 Vee - 5.25V
V 1N = 5.5V
1
mA
Logical "0" I nput Current
DM7800 Vee ~ 5.5V
DM8800 Vee - 5.25V
V 1N
~
-0.4
mA
Output Leakage Current (Note 2)
DM7800 Vee~ 5.5V
DM8800 Vee - 5.25V
V 1N
= 0.8V
10
J.l.A
20.0
kn
V 2 + 2.0
V
2.0
0.8
~
O.4V
-Q.2
(Note 5)
TA ~ 25°C
Output Collector Resistor
V
11.5
16.0
V
Logical "0" Output Voltage
DM7800 Vee = 4.5V
DM8800 Vee - 4.75V
V 1N
= 2.0V
Power Supply Current
Logical "0" (Note 3)
(Each Gate)
DM7800 Vee = 5.5V
DM8800 Vee'" 5.25V
V 1N
~
4.5V
0.85
1.6
mA
Power Supply Current
Logical "1" (Note 3)
(Each Gate)
DM7800
DM8800
Vee = 5.5V
Vee - 5.25V
V 1N
~
OV
0.22
0.41
mA
= 25°C
C = 15 pF (Note 6)
25
70
125
ns
• TA ~ 25°C
C = 15 pF (Note 7)
25
62
125
ns
Transition Time to Logical "0" Output
Transition Time to Logical "1" Output
(Note 5)
TA
Note 1: MinImax limits apply across the guaranteed temperature range of -5SoC to +125~C for the DM7800 and O°C to +70°C
for the DM8800 unless otherwise specified.
Note 2: Current measured is drawn from V3 supply.
Note 3: Current measured is drawn from Vee supply.
Not. 4: All typical values are measured at T A
= 2Soe with
Vee
= S.OV,
Note 5: Specification applies for a" allowable values of V2 and V3.
Note 6: Measured from lo5V on input to 50% level on output.
Note 7: Measured from 1.5V on input to logic "0" voltage, plus 1V.
1·224
V2
= -22V,
V3
= +8V.
c
3:
....
00
o
o
theory of operation
......
c
3:
The two input diodes perform the AND function
on TTL or OTL input voltage levels. When at least
one input voltage is a logical "0", current from Vee
(nominally 5.0V) passes through R, and out the
input(s) which is at the low voltage. Other than
small leakage currents, this current drawn from Vee
through the 20 kn resistor is the only source of
power dissipation in the logical "I" output state.
When both inputs are at logical "1" levels, current
passes through R, and diverts to transistor a" turn·
ing it on and thus pulling current through R2 • Cur·
rent is then supplied to the PNP transistor, O2 . The
voltage losses caused by current through a" 0 3 ,
and O2 necessitate that node P reach a voltage suf·
ficient to overcome these losses before current be·
gins to flow. To achieve th is voltage at node P, the
inputs must be raised to a voltage level which is one
diode potential lower than node P. Since these levels
are exactly the same as those experienced with con·
ventional TTL and OTL, the interfacing with these
types of circuits is achieved.
Transistor A. provides "constant current switch·
ing" to the output due to the common base con·
nection of a •. When at least one input is at the
logical "0" level, no current is delivered to O2 ; so
that its collector supplies essentially zero current
to the output stage. But when both inputs are raised
to a logical "I" level current is supplied to O2 •
Since this current is relatively constant, the collector of O2 acts as a constant current source for the
output stage. Logic inversion is performed since
logical "I" input voltages cause current to be supplied to O2 and to 0 3 • And when 0 3 turns on the
output voltage drops to the logical "0" level.
o
o
The reason for the PNP current source, O2 , is so
that the output stage can be driven from a high
impedance. This allows voltage V2 to be adjusted
in accordance with the application. Negative volt·
ages to -25V can be applied to V2. Since the out·
put will neither source nor sink large amounts of
current, the output voltage range is almost exclu·
sively dependent upon the values selected for V2
and V3 .
Maximum leakage current through the output tran·
sistor 0 3 is specified at 10 /lA under worst·case
voltage between V. and V3- This will result in a
logical "1" output voltage which is 0.2V below V3.
Likewise the clamping action of diodes 0 4, Os, and
06- prevents the logical "0" output voltage from
falling lower than 2V above V2, thus establishing
the output voltage swing at typically 2 volts less
than the voltage separation between V2 and V3-
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. The
range of operation for power supply V2 is shown
on the X axis. It must be between -25V and -BV.
The allowable range for power supply V3 is gov·
erned by supply V•. With a value chosen for V,. V3
may be selected as any value along a vertical line
passing through the V2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.
00
00
i.'
OPERATING
'17·
2.
,.
21
11
•
a
...
-11
-15
-a
-a
1·225
o
CD
o
00
00
:E
c
.......
~s
Series 54/74
CD
o
~
:E
c
DM7802/DM8802. DM780S/DM880S
high speed MOS to TTL level converters
N
o
00
00
general description
features
c
The DM7802/DM8802, DM7806/DM8806 are high
speed MOS to TTL level converters. These circuits
act as an interface level converter between MOS
and TTL logic devices. It consists of two 1-input
converters with common strobe input to inhibit
"0" entry when strobe is high. It allows parallel
entry when strobe is low and the internal latch
is preset by the common preset input. TRISTATE@ output logic is implemented in this
circuit to facilitate high speed time sharing of
decoder-drivers, fast random-access (or sequential)
memory arrays, etc.
• Very low output impedance ability
:E
.......
N
o
~
:E
c
• High impedance output state which allows
many outputs to be connected to a common
bus line
• Average power dissipation 110 mW per converter
logic and connection diagrams
~CURRENT
IN.
INPUT)
OUTPUT A
IN,
(CURRENT INPUT)
OUTPUT B
PRESET
Dual-In-Line Package
=
Dual-In-Line and Flat Package
16
V"
15
NO
"
OUTPUT A
13
PRESET
DM7802JDM8B02
NO
"
11
GND
lD
INPUT A
"
!Tl!lffi
NO
13
OUTPUT A
OUTPUT B
"
PRESET
DISABLE
NO
NO
OM7806/0MB806
DISABLE
NO
GND
GND
INPUT 8
INPUT A
GND
TOPVIEW
1-226
V"
OUTPUT B
INPUT 8
GND
TOP VIEW
11
lD
GND
GND
GND
high drive
c
absolute maximum ratings
3:
.....
operating conditions
(Note 1)
CO
o
MIN
Supply Voltage
7.0V
I nput Vol tage
55V
Output Voltage
5.5V
Storage Temperature Range
Supply Voltage (Veel
DM7802. DM7806
DM8802. DM8806
Temperature (T A)
DM7802. DM7806
DM8802. DM8806
-65°C to 150°C
300°C
Lead Temperature (Soldering, 10 seconds)
45
475
-55
a
MAX
UNITS
5.5
5.25
V
V
+125
+70
N
"-
c
3:
CO
CO
'e
°e
o
N
C
3:
electrical characteristics
CONDITIONS
PARAMETER
Logical "1" Input Current
(lINA' IINS!
Logical "0" Input Current
(lINA. 'INS)
~
o
0)
(Note 2)
Vee
= Min
MIN
TYP
Vee
=
200
Logical "0" Input Voltage, Strobe,
Vee
= Min
"-
c
3:
CO
CO
!-LA
V
20
Min
UNITS
!-LA
Vee == Min
Logical "1" Input Voltage. Strobe,
Preset, Disabl-e
MAX
500
o
0)
08
V
Preset, Disable
V
24
Logical "1" Output Voltage
Vee -= Min, lOUT
Logical "0" Output Voltage
Vee
Third State Output Current
Vee =Max, Vo =24V
Vee := Max, Vo == 0 4 V
Logical "1" Input Current
Vee = Max, VIN = 24V
Vee = Max, VIN = 5 5V
40
10
!-LA
rnA
-16
rnA
40
rnA
= Min,
=
'OUT::
-15 mA
16 mA
Logical "0" Input Current
Vee = Max, VIN = 0 4V
Supply Current
Vee Max, VINWISABLE):O:: 2
Other Inputs = ¢V
Input Clamp Voltage
Vee = Mm, liN
Output Short Circuit Current (Note 3)
Vee = Max, Va = OV
DM7802, DM7806
DM 8802, D M8806
:0::
=
-12 mA
-20
-18
04
V
40
-40
!-LA
!-LA
-15
V
-70
-70
rnA
rnA
Propagation Delay to a Logical "0" From
STROBE to Output (tds )
Vee=50V (See waveforms)
T A = 25°C
17
25
ns
Propagation Delay to a Logical "1" From
Preset to Output (tdp)
Vee=50V (See waveforms)
TA = 25°C
22
32
ns
Delay From Disable Input to High Impedance
State (from Logical "1" Level)(t 1H )
Vee=50V (See ac test Circuit)
T A = 25°C
70
11
ns
Delay From Disable Input to High Impedance
State (From Logical "0" Level)(toH )
Vee = 5.0V (See ac test circUit)
TA = 2SOC
17
25
ns
Delay From Disable Input to Logical "1"
Level (From High Impedance State)(t H1 )
Vee=50V (See ac test circUit)
TA = 25°C
90
14
ns
Delay From Disable Input to Logical "0"
Level (From High Impedance State)(tHO)
Vee =50V (See ae test circuit)
TA = 25°C
13.5
16
ns
III
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed, Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherwise specified mm/max limits apply across the'-55°C to +12SoC temperature range for the DM7802,
DM7806 and across the oOe to +70o e range for the DM8802. DM8806. All tYPlcals are given for Vee
= 5.0V. T A = 25°C.
Note 3: Only one output at a time should be shorted.
1-227
CD
o
00
00
typical input circuit
:E
Q
"CD
o
Ie
:E
'H
5.0k
Q
N
o
00
00
:E
Q
"N
o
00
....
:E
Q
truth table
INAORB
,
0
,
0
x
X = Don't care
1-228
ST
P
,, ,,
0
0
x
0
0
0
0
0
,,
,
x
,,
QAOROs
,
0
Hi-Z
CC
s:s:
Series 54/74
""'00
0000
......
,0
C·
s:C
oos:
0000
DM7810/DM8810 quad 2-input TTL-MOS interface gate
DM7811/DM8811 quad 2-input TTL-MOS interface gate
DM7812/DM8812 TTL-MOS hex inverter
...... 00
:::::
cC
general description
These Series 54/74 compatible gates are high output voltage versions of the DM5401/DM7401
(SN5401/SN7401), DM5403/DM7403
(SN5403/SN7403), and DM5405/DM7405
(SN5405/SN7405). Their open-collector outputs
may be "pulled-up" to +14 volts in the logical "1"
state thus providing guaranteed interface between
TTL and MOS logic levels.
s:3:
....,00
In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 14 volts.
0000
......
NN
....
C
3:
00
00
...
N
schematic and connection diagrams
r------.------Ov~
4k
r---~""'------Ov"
16K
INPUT
INPUTS
OUTPUT
OUTPUT
0-,:-+--......
"
. . . .----_--o.N.
' - - -....-0 •••
DM7812/DM8812
DM7810/DM8810, DM7811/DM8811
Dual~ln·Line
Dual~ln·Line
Package
•••
TOP VIEW
TOP VIEW
"
.N•
DM7811/DM8811
DM7810/DM8810
v,
and Flat Package
Oual-I "-Line and Flat Package
13
12
11
10
rOPVIEW
.N.
DM7812/DM8812
1-229
absolute maximum ratings
operating conditions
Supply Voltage (Veel
DM78XX
DM88XX
Temperature ITAI
DM78XX
DM88XX
7V
5.5V
14V
-65°e to +150o e
3000 e
Vee
I nput Voltage
Output Voltage
Storage Temperature Range
Lead TEmperature (Soldering, 10 ,ecl
......
00
00
:!
electrical characteristics
MIN
MAX
UNITS
4.75
4.75
5.25
5.25
V
V
-55
0
+125
70
°e
°e
(Note 1)
c
...
"00
.....
:!
c
PARAMETER
CONOITIONS
MIN
TYP
MAX
UNITS
Input Diode Clamp Voltage
Vee ~ 5.0V, T A ~ 25°c
liN ~ -12 mA
Logical "1" Input Voltage
Vee = Min
Logical "0" I nput Voltage
Vce ~ Min
Logical "1" Output Current
Vee = Min
VOUT= 10V
Logical "1" Output Breakdown
Voltage
Vee = Min, VIN
IOUT= 1 mA
Logical "0" Output Voltage
Vee ~ Min, VIN = 2.0V
lOUT = 16 mA
Logical "1" Input Current
Vee = Max, V IN = 2.4V
40
Logical "1" Input Current
Vee = Max, VIN = 5.5V
1
mA
Logical "0" I nput Current
Vee = Max, VIN = O.4V
-1.6
mA
Supply Current - Logical "0"
(Each Gate)
Supply Current - Logical "1"
(Each Gate)
Propagation Delay Time to a
Logical "0", tpdO
Vee = Max, VIN = 5.0V
3.0
5.1
mA
Vee = Max, VIN = OV
1.0
1.8
mA
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = 1k
4
12
18
ns
Propagation Delay Time to a
Logical "1", tpd1
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = 1k
18
29
45
ns
-1.5
2.0'
V
0.8
VIN ~ 0.8V
VIN ~ O.OV
~
OV
V
250
40
V
I1A
I1A
V
14
0.4
V
I1A
Note 1: Unless otherwise specified min/max limits apply across the _55°C to +12SoC temperature range for the DM78XX and
across the oOe 10 700 e range for the DM88XX. All tYPical, are given for Vee'; 5.0V and T A ~ 25°e.
typical applications
+10V
3K
+12V
75K
I.
GROUND
'-jD--+--!INPUT
DM8810, DM1811, DMlI12
I
CLOCK
1
+Vl
":"
DM8810, OMBIll, OM8812
NSC MUS shift reg,sta,
'---"";'l---'
N5CMOS ROM
(E!c:ampleMM6Z1)
(Example MM506)
Note Normalvoltagasapphed
to MDSshift reglstersbaVl
-6V
I
-v,
Voo
.J:.
+lDVL-
1-230
I
'-JO----+--II'NPUT
beenslllftedby+l0Votls
fltl'thlsapplrcabon
-12V
Series 54/74
DM7819/DM8819 quad 2-inputTTL-MOS AND gate
general description
thus providing guaranteed interface between TTL
and MOS logic levels.
The DM7819 is the high output voltage version of
the SN5409. Its open-collector outputs may be
"pulled-up" to +14 volts in the logical "1" state
schematic and connection diagrams
u
.K
16K
2K
lK
Dual~ln-Line
and Flat Package
TOP VIEW
1-231
...
(7)
00
00
absolute maximum ratings
::E
(Note 1)
operating conditions
Q
"(7)
...
Supply Voltage
Input Voltage
Output Voltage
00
"'"
::E
Storage Temperature Range
Q
Lead Temperature (Soldermg, 10 sec)
7.0V
5.5V
5.5V
-65°C to +125°C
300°C
electrical characteristics
Supply Voltage (V Ccl
DM7819
DM8819
Temperature (TAl
DM7819
DM8819
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°c
°c
(Note 2)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
V
2.0
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Current
Vee
Vee
= Min. V ,N =2.0V. VOUT = 10V
= Min. V ,N = 4.5V. V OUT = 14V
Logical "0" Output Voltage
Vee
= Min. V ,N =0.8V.
004
V
Logical "1" Input Current
V ,N
Vee = Max,
V ,N
= 204V
= 5.5V
40.0
1.0
I'A
mA
Logical "0" Input Current
Vee = Max, V ,N
= Oo4V
-1.6
mA
Supply Current - Logical" 1"
Logical "0"
Vee = Max, V ,N
Vee = Max, V ,N
21.0
33.0
mA
mA
-1.5
V
lOUT
= 16 mA
08
V
40,0
1.0
I'A
mA
Input Clamp Voltage
= 5V
= OV
Vee = 5.0V. TA = 25°C.
Propagation Delay to a Logical "0" tpdO
DM7819
DM8819
Vee = 5.0V
TA = 25°C
16,0
24.0
ns
Vee = 5,OV
TA = 25°C
16,0
32,0
ns
Propagation Delay to a Logical" 1"
DM7819
DM8819
11.0
20.0
liN
= -12 mA
tpd1
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVIce cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Charactenstlcs" prmfldes conditions for actual device operatlo~
0
Note 2: Unless otherWise Specified minimax limits apply across the -55 C to +125 C temperature range for the DM7819
and across the ooe to 70 0 e range for the DM8819 All typlcals are given for Vee'" 5 OV and T A = 25°C
1·232
c
Series 54/74
!:
....
01)
N
o
......
c
!:
01)
01)
DM7820/DM8820 dual line receiver
N
general description
o
The DM7820, specified from _55°e to 125°e, and
the DM8820, specified from oOe to 70o e, are
digital line receivers with two completely independent units fabricated on a single silicon chip_
Intended for use with digital systems connected
by twisted pair lines, they have a differential input
designed to reject large common mode signals while
responding to small differential signals_ The output
is directly compatible with RTL, DTL or TTL
integrated circuits.
• Each channel can be strobed Independently
• High input resistance
• Fanout of two with either DTL or TTL
integrated circuits
The response time can be controlled with an external capacitor to eliminate noise spikes, and the
output state is determined for open inputs. Termination resistors for the twisted pair line are
also included in the circuit. Both the DM7820 and
the DM8820 are specified, worst case, over their
full operating temperature range, for ±10-percent
supply voltage variations and over the entire input
voltage range.
features
• Operation from a single +5V logic supply
• Input voltage range of ±15V
schematic and connection diagrams
RESPOtdETIMt:
CONTROL
v'
--.IO
'"
""'
NONIIIVERTIIIG
.....UT
-~
"'
.... •.
.n
~:
-
"
"'
.n
INPUT
"
v"
INPUT
TEW"INAnON
'"
'"
OUTPUT
.....
..
STROlE
OUTPUT
.14
IK
OUTPUT
GROUND
'"
"'
INVERnlG
INPUT
4;u ~., "r ."
IK
"'
HI
.
HI
IK
Dual-I n-Lina and Flat Package
10K
... 010
D2
III
TERMINAnON
.n
.11
51
.11
TOP VIEW
GROUND
"''"
STROlE
typical application
c,t
o81/tF
LINE DRIVER AND RECEIVERi'
lf2DM7B3D
TWISTEO PAIR LINE
OUTPUT
fvcc ll45VtoliliV
'trbothtbtDM7lZG
Inll DM7I3O
tE..............
on II", ......
STROBE
-o......lteClIt1rOl
"'Po_tim.
1-233
o
0
N
00
00
absolute maximum ratings
Q
Supply Voltage
Input Voltage
Differential Input Voltage
Strobe Voltage
Output Sink Current
Power Dissipation (Note 1)
Operating Temperature Range
DM7820
DM8820
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
~
.......
0
N
00
.....
:E
Q
8.0V
±20V
±20V
8.0V
25mA
600mW
-55°C to +125°C
OoC to +70°C
-65°C to +150°C
300·C
electrical characteristics
PARAMETER
(Notes 2 & 3)
CONDITIONS
Input Threshold Voltage
V IN = 0
- 15V :S VIN:S 15V
High Output Level
lOUT
Low Output Level
Islnk
MIN
-0.5'
-1.0
:s 0.2 mA
:s 3.5 mA
0
0
MAX
UNITS
0.5
1.0
V
V
2.5
5.5
V
0
0.4
V
Inverting Input Resistance
3.6
5.0
kn
Non-inverting Input Resistance
1.8
2.5
kn
Line Termination Resistance
TA = 25°C
Response Time
Cdelay = 0
Cdelay = 100 pF
Strobe Current
V strobe =O.4V
Vstrobe = 5.5V
1.0
1.4
-5.0
mA
IJA
Power Supply Current
V IN = 15V
V IN = 0
VIN=-15V
3.2
5.8
8.3
6.0
10.2
15.0
mA
mA
mA
Non-inverting Input Current
V IN = 15V
VIN=O
V IN = -15V
5.0
-1.0
,-7.0
7.0
-1.6
-9.8
mA
mA
mA
4.2
-4.2
3.0
0
-3.0
mA
mA
mA
Inverting Input Current
120
V IN = 15V
VIN=O
V IN = -15V
Note 1. For operating at oelelJated temperatures, the deVice must be derated ~ased on a
thermal resistance of 100 C!W and a maximum Junction temperature of 160 C for the
DM7820 or 10SoC for the DM8820
Note 2: These speclflcailons apply for 4 5V ~ Vee S; 5,5V, -15V:S VCM::S; 15V and
-55°C ~ TA .s; 12SQC for the DM7820 or O°C.s; TA .s; 70 0 e for the DM8820 unless
otherwise speCified' tVPlcal values gIVen are for Vee:: 5 OV, T A :: 25°C and V CM = 0
unless stated differently
Note 3: The specifications and curves given are for one Side only Therefore, the total
package diSSipation and supply currents will be double the values given when both
receIVers are operated under Identical conditions
1-234
TYP
170
250
n
ns
ns
40
150
-D.5
c
s:
....,
Series 54/74
CO
N
o
»
.......
OM7820A/OM8820A dual line receiver
c
s:CO
general description
The DM7820A and the DM8820A are improved
performance digital line receivers with two completely independent units fabricated on a single
silicon chip. Intended for use with digital systems
connected by twisted pair I ines, they have a differential input designed to reject large common mode
signals while responding to small differential signals. The output is directly compatible with RTL,
DTL or TTL integrated circuits.
•
Operation from a single +5V logic supply
•
Input vGltage range of ±'5V
• Series 54/74 compatible
The response time can be controlled with an external capacitor to reject input noise spikes. The
output state is a logic "," for both inputs open.
Termination resistors for the twisted pair line are
also included in the circuit. Both the DM7820A
and the DM8820A are specified, worst case, over
their full operating temperature range (-55°C
to '25°C and DoC to 70°C respectively), over the
entire input voltage range, for ±1O% supply voltage variations.
• Strobe low forces output to "," state
•
»
• Outputs can be wire OWed, 3 (max)
features
•
CO
N
o
Fanout of ten with either DTL or TTL integrated circuits
High input resistance
schematic and connection diagrams
RUPONSETIME
CONTROL
".'"
Dual-I "-Line and Flat Packages
~
'"""
""
~
""'
NON INVERTING
INPUT
'-I
'""
"
""'
'""'
INVERTING
INPUT
'-I
""
~.
"'
-,..---
"
""'
"""
""'
""'
"'
'"
'"""
~"'
" 'co
"
,
01.
-INPUT
TERMINATION
,,~
12 TERMINATION
""
11 + INPUT
~.
""
'"
10
.
STROBE
""
';0
No~
typical applications
S.he"",uesho~on~halfotun't
Single Ended (EIA-RS232CI ReceIver with Hysteresis
Differential Line Driver and Receiver
Cl,Ol"F
(OUTPUT - "'" FOR
OPEN INPUT)
*Optional to control response time.
'-235
01
: 2.5V
V OUT -S;O.4V
I nput Current
Open Circuit Input Voltage
CONDITIONS
V
1.4
-1.0 mA
mA
24.0
mA
125
ns
c
3:
....,
Series 54/74
00
W
o
........
c
3:
DM7830/DM8830 dual differential line driver
00
00
W
general description
The DM7830/DM8830 is a dual differential line
driver that also performs the dual four-input NAND
or dual four-input AND function.
normally associated with single-wire transmissions.
o
features
TTL (Transistor-Transistor-Logic) mUltiple emitter
inputs allow this line driver to interface with standard TTL or DTL systems. The differential outputs
are balanced and are designed to drive long lengths
of coaxial cable, strip line, or twisted pair transmission lines with characteristic impedances of
500 . to 500ft The differential feature of the
output eliminates troublesome ground-loop errors
• Single 5 volt power supply
• Diode protected outputs for termination of
positive and negative voltage transients
• Diode protected inputs to prevent line ringing
• High Speed
• Short Circuit Protection
schematic"'and connection diagrams
Oual~ln·Line
o
and Flat Package
AND
OUTPUT
NAND
OUTPUT
AND
NAND
GND
OUTPUT
OUTPUT
v'"
TOPVIEW
typical application
Digital Data Transmission
CIt
001/.1F
LINE DRIVER AND RECEIVERt
1/2DM183D
TWISTED PAIR LINE
OUTPUT
6
tVee IS 4 5V tn 5 5V
for both the OM7IIZO
tExm valul d.pends
00 hne length
·OptlOnal to control
fespunsetlme
andDM18JO
STROBE
1-239
0
(W)
absolute maximum ratings
co
co
:eC
Vee
Input Voltage
Operating Temperature
.......
0
7.0V
5.5V
_55°C to +125°C
O°C to 70°C
_65°C to +150°C
300°C
1 second
DM7830
DM8830
C")
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Output Short Circuit Duration (125°C)
CO
....
:e
C
electrical characteristics
PARAMETER
(Note 1)
CONDITIONS
Logical "1" Input Voltage
MIN
TVP
MAX.
2.0
UNITS
V
Logical "0" Input Voltage
0.8
V
Logical "1" Output Voltage
V 1N = 0.8V lOUT = -0.8 mA
2.4
Logical "l"Output Voltage
V1N = 0.8V IOUT= 40 mA
1.8
Logical "0" Output Voltage
V1N = 2.0V lOUT = +32 mA
0.2
0.4
V
, 'Logical "0" Output Voltage
V1N = 2.0V lOUT = +40 mA
0.22
0.5
V
V
V
3.3
Logical "1" Input Current
V1N = +2.4V
120
/lA
Logical "1" Input Current
V 1N = 5.5V
2
mA
Logical "0" Input Current
V 1N = O.4V
4.8
mA
Output Short Circuit Current
Vce = 5.0V
100
Note 2
120
mA
Supply Current
V1N = 5.0V
(Each Driver)
11
18
mA
TA = 25°C
8
12
ns
Vee = 5.0V
11
18
ns
C L =15pF
8
12
ns
See Figure 1
5
8
ns
12
16
ns
12
16
ns
Propagation Delay AND Gate
}
tpd1
tpdO
Propagation Delay NAND Gate tpd1
tpdO
Differential Delay t1
Note 2
40
} Load, lOOn and 5000 pF
Differential Delay t2
See Figure 2
Note 1: Specifications apply for OM783Q -5SoC ::; T A ~ +1250 c, Vee = +5V ±10%, DM8830 aoc
5. TA S. 700C, Vee = +5V ±5% unless otherwise stated. Typical values given are for TA :: 2SoC,
Vce = 5,OV.
Note 2: Applies for T A = +1250 C only.
"PUTS{4~
~c j~ . ,"
.I...J....
T
e•
..
~SAMELDAD
FIGURE 1.
1-240
,",UTS
'~
1St
{i
4
v,
loon
5DOOpF
v,
FIGURE 2.
c
Series 54/74
3:
~
w
...
......
.
c
®
DM7831/DM8831.DM7832/DM8832 TRI-STATE
3:
line drivers
00
00
W
general description
Through simple logic control, the DM7831/
DM8831, DM7832/DM8832 can be used as either
a quad single-ended line driver or a dual differential
line driver. They are specifically designed for
party line (bus-organized) systems. The DM7832/
DM8832 does not have the Vee clamp diodes
found on the DM7831/DM8831.
• High impedance output state which allows
many outputs to be connected to a common
bus line,
mode of operation
To operate as a quad single-ended IlOe driver apply
logical "O"s to the Output Disable pins (to keep
the outputs in the normal low impedance mode)
and apply logical "0'" s to both Differential/
Single-ended Mode Control inputs. All four
channels will then operate independently and no
signal inversion will occur between inputs and
outputs,
The DM7831 & DM7832 are specified for operation over the -55°C to +125°C military temperature range. The DM8831 & DM8832 are specified
for operation over the O°C to + 70°C temperature
range.
To operate as a dual differential line driver apply
logical "O"s to the Output Disable pins and apply
at least one logical "1" to the Differential/Singleended Mode Control inputs, The inputs to the A
channels should be connected together and the
inputs to the B channels should be connected toIn this mode the signals applied to the resulting
inputs will pass non-inverted on the A2 and B2 outputs and inverted on the A, and B I outputs.
features
• Series 54/74 compatible
• 17 ns propagation delay
low output impedance-high drive
• Very
capability
• 40 mA sink and source currents
• Gating control to allow either single-ended or
differential operation
When operating in a bus-organized system with
outputs tied directly to outputs of other
(Continued)
connection and logic diagram
Dual~ln-Line
"A" OUTPUT
ENABlE
OUTPUT
"'" OUTPUT
a,
ENABLE
and Flat Package
OUTPUT
"2
INPUT
"2
OUTPUT
A,
DIFFERENTlAll
INPUT SINGLE ENDED
A,
MODE CONTROL
INPUT OUTPUT INPUT DIFFERENTIALI GNU
82
B," 8,
SINGLE ENDED
MODE CONTROL
TOP VIEW
truth-table
(Shown for A Channels Only)
"A" OUTPUT DISABLE
0
0
0
0
1
X
X
1
DIFFERENTIAL!
SINGLE-ENDED
MODE CONTROL
INPUT A,
Logical" 1" or
0
0
X
1
Logical" 1" or
1
X
LogIcal "0"
X
X
Logical "0"
X
OUTPUT Al
Same as
Input A,
OpPOsite of
Input A,
High
Impedance
state
INPUT A2
Logical "1" or
OUTPUT A2
Same as
Logical "0"
Input A2
Logical" 1 " or
Same as
Logical "0"
Input A2
High
X
Impedance
state
x - Don t Care
1-241
...
c
....3:
00
W
N
......
c
3:
00
00
W
N
o
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Operating Temperature Range
7V
55V
5.5V
-il5'C to +150'C
-55'C to +125'C
O°C to +70°C
300'C
OM7831. OM7832
OM8831 , OM8832
Lead Temperature (Soldering, 10 sec)
Time that 2 bus-connected devices may be In
OPPosite low Impedance states simultaneously
...
~
('I)
00
00
electrical characteristics
::E
Q
...
.......
(Note 1)
PARAMETER
('I)
Ie
~
Q
CONDITIONS
MIN
Logical "1" Input Voltage
OM 7831 ,OM7832 Vee = 4.5V
OM8831,OM8832 Vee =475V
Logical "0" Input Voltage
OM7831,OM7832 ~=45V
OM8831,OM8832 Vee - 4.75V
Logical "1" Output Voltage
10=-40mA
Vee=45V
10 = -2 mA
OM7831,OM7832
10 - -40 mA
OM8831,OM8832
Vee =475V
10 = -5 2 mA
Logical "0" Output Voltage
OM7831,OM7832
OM8831,OM8832
Logical "1" Input Current
OM7831,OM7832 Vee = 5.5V Y'N =55V
OM8831,OM8832 Vee = 525V Y,N 2.4V
Logical "0" Input Current
OM7831,OM7832 Vee = S.5V
Y,N = O.4V
OM8831,OM8832 Vee 525V
Output Disable Current
OM7831,OM7832 Vee = 6.5V
Vo = 2.4V or O.4V
OM8831,OM8832 Vee = S.2SV
08
2.3
27
2.5
2.9
10 =40mA
10 = 32 mA
10-40mA
10 =32mA
029
0.29
-1.0
-40
-40
INote21
UNITS
V
1.8
2.4
18
2.4
OM7831,OM7832 Vee = 5.SV
OM8831,OM8832 Vee 525V
-100
65
Vee=SOV, TA =2S'e
liN = -12 mA
Input Diode Clamp Voltage
MAX
2.0
OM7831,OM7832 Vee = 5.5V
Output Short Circuit Current
OM8831,OM8832 Vee 5.25V
Supply Current
TYP
V
V
V
V
V
0.50
0.40
0.50
0.40
V
V
V
V
1
40
mA
IlA
-16
mA
40
IlA
120
INote21
mA
90
,."
-1.S
V
-15
V
Vee +l 5
V
----
Output Diode Clamp Voltage
OM7831.0M7832 lOUT = -12 mA.Yee = 5 OV, TA = 25'C
OM8831 , DM8832
OM7831,DM8831 lOUT -+12mA.Yee-5.OV, TA 25 C
Propagation Delay to a Logical "0"
from Inputs A 1 , A 2 , B 1 • B2 O,fferentlal Single-ended Mode Control to
Outputs, tpdO
Vee=50V, TA = 25'e
13
25
n.
Vee = 5.0V, TA = 25'C
13
25
ns
Delay from Disable Inputs to High
Impedance State (from Logical "1"
Level), t1 H
Vee=50V, TA = 25'C
6
12
ns
Delay from Disable Inputs to High
Impedance State (from Logical "0"
Level), tOH
Vee = 50V, TA = 25'C
14
22
ns
~ee = 50V,
TA = 25'e
14
22
. n.
Vee=SOV, TA = 25°C
18
27
n'
Propagation Delay to a Logical "1"
from Inputs A" A 2 , B" B2 Dlfferentlal Single-ended Mode Control to
Outputs, tpd 1
Propagation Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State). tH
1
Propagation Delay from Disable Inputs
to Logical "0" Level (from High
Impedance State), tHO
Note 1: Unless otherWise specified mm/max limits apply across the -55°C to +12SoC temperature
range for the OM7831, OM7832 and across the O'C to 70'C temperature range for the OM8831,
OM8832. All tYPical. are given for Vce = 5.0V and TA = 2S'e.
Note 2: Applies for TA = 12SoC only Only one output should be shorted at a time
1-242
c
s:
.....
mode of operation (cont.)
DM7831/DM8831's, DM7832/DM8832's (Figure
11, all devices except one must be placed In the
"high impedance" state. This is accomplished by
ensuring that a logical "1" is applied to at least
one of the Output Disable pins of each device
which is to be in the "high impedance" state. A
NOR gate was purposely chosen for this function
since It is possible with only two DM5442/
DM7442, BCD·to·decimal decoders, to decode as
many as 100 DM7831/DM8831's, DM7832/
DM8832's (F Igure 21.
The unique device whose Disable inputs receive
two logical "0" levels assumes the normal low
Impedance output state, providing good capacitive
drtve capability and waveform integrtty especially
dUring the transition from the logical "0" to
logical "1" state. The other outputs-in the high
impedance state-take only a small amount of
leakage current from the low Impedance outputs.
Since the logical "1" output current from the
selected' device IS 100 times that of a conventional
Series 54174 device (40 mA vs. 400 J.l.AI, the
output IS easily able to supply that leakage current
for several hundred other DM7831 /DM8831 's,
DM7832/DM8832's and still have available drive
for the bus line (Figure 31.
00
W
...
.......
C
s:00
00
W
...
c
s:.....
00
W
N
.......
C
s:00
00
W
N
BUS LINES
~
SELECTED AS
DRrVING~
DEVICE
D
o0
GATED INTO
THIRD STATE -
MM
8 8
8 8
nHH-+,.
Figure 1
Figure 2
FOR DRIVING OTHER TTL INPUTS
SElECTED AS
DRIVING DEVICE
40mA
D 0
GATED INTO
HI IMPEDANCE
STATE
MM
8
8
3
1
8
8
3
2
o0
GATED INTO
HI IMPEDANCE
STATE
MM
8
8
3
1
8
8
3
2
-
40,uA
LEAKAGE
CURRENT
PER CONN
-
40pA
Figure 3
1·243
CD
(It)
CO
CO
Series 54/74
~
Q
.......
CD
(It)
CO
.....
DM7836/DM8836 quad NOR unified bus receiver
Q
general description
~
features
The DM7836/DM8836 are quad 2-input receivers
designed for use in bus organized data transmission
systems interconnected by terminated 120n impedance lines_ The external termination is intended to be 180n resistor from the bus to the +5V
logic supply together with a 390n resistor from
the bus to ground_ The design employs a built-in
input hysteresis providing substantial noise immunity_ Low input current allows up to 27 driver/
receiver pairs to uti lize a common bus_ This receiver has been specifically configured to replace
the SP380 gate pin-for-pin to provide the distinct
advantages of the DM7837 receiver design in existing systems_
•
Plug-in replacement for SP380 gate
•
Low input current with
Vee = OV (151lA typ)
•
Built-in input hysteresis (lV typ)
normal
•
High noise immunity (2V typ)
•
Temperature-insensitive input thresholds track
bus logic levels
•
DTL/TTL compatible output
•
Matched, optimized noise immunity for "1"
and "0" levels
•
High speed (18 ns typ)
typical application
.,y
.,y
l80n
laos!
120.0 Unified Data Bus
---, r-
390,11
I I
I I
I I
I
_.J
connection diagram
Dual-In-Line Package
OUTl
OUT4
IN4A
IN4B
IN 3A
IN3B
QUlZ
OUTl
IN1A
IN 18
IN ZA
14
GND
TOPVIEW
1-244
Vee or
IN 28
390u
c
absolute maximum ratings
3:
......
(Note 1)
00
Supply Voltage
Input Voltage
Power Dissipation
Operating temperature range:
DM7836
DM8836
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
W
(J)
7.0V
5.5V
600mW
......
_55°C to +125°C
0°Cto+70°C
-65°C to +150°C
300°C
00
00
C
~
W
(J)
electrical characteristics
The following apply for V L
::5 Vee ::5 V H , T L ::5 T A ::5 T H, unless otherwise specified (Note 2)
PARAMETER
INPUT
High level Input Threshold'
DM7836
DM8836
MIN
TYP
OUTPUT
COMMENTS
MAX
UNIT
V TH
V TH
16mA
16mA
Output< O.4V
Output < O.4V
1.65
1.80
2.25
2.25
2.65
2.50
V
V
V TH
V TH
-4001lA
-4001lA
Output> 2.4V
Output> 2.4V
0.97
1.05
1.30
1.30
1.63
1.55
V
V
Low Level Input Threshold:
DM7836
DM8836
Maximum Input Current
4V
Vee"" V H
Maximum Input Current
4V
Vee
Loglc"l" Output Voltage
0.5V
=
OV
-4001lA
Logic "0" Output Voltage
4V
16mA
Output Short Circuit Current
0.5V
OV
15
50
IlA
1
50
IlA
0.25
Vee
= VH
-18
0.4
V
-55
mA
mA
Power Supply Current
4V
Per Package
25
40
Input Clamp Diode Voltage
-12mA
TA = 25°C
-1
-1.5
V
20
18
30
30
ns
ns
The following apply for Vee = 5V. TA
Propagation Delays
Input to Logic "1" Output
Input to Logic "0" Output
I
0
V
2.4
= 25°C unless otherwise speCified
I
Note 3
I
Note 4
Note 1: Voltage values are with respect to network ground terminal. Positive current is defined as current into the reference pin.
Note 2: For DM7836: V L = 4.5V, VH = 5.5V, TL = _55°C, TH = +125°C.
For DM8836: VL = 4.75V, VH = 5.25V, TL = O·C, TH = +7rfC.
Note 3: Fan-out.of 10 load, CLOAD = 15 pF total, measured from VIN = 1.3V to VOUT
Note 4: Fan-Qut of 10 load, CLO AD
= 15 pF total, measured from
V1N
= 1.5V, V1N = OV to 3V pulse.
= 2.3V to VOUT = 1.5V, VIN = OV to 3V pulse.
1-245
Series 54/74
DM7837/DM8837 hex unified bus receiver
general description
features
The DM7837/DMSS37 are high speed receivers de·
signed for use in bus organized data transmission
systems interconnected by terminated l20n im·
pedance lines. The external termination is intend·
ed to be lS0n resistor from the bus to the +5V
logic supply together with a 390n resistor from
the bus to ground. The receiver design employs a
built·in input hysteresis providing substantial noise
immunity. Low input current allows up to 27 driv·
er/receiver pairs to utilize a common bus. Disable
inputs provide time discrimination. Disable inputs
and receiver outputs are DTLmL compatible.
•
Low receiver input current for normal Vee or
Vee = OV (15,uA typ)
•
Six separate receivers per package
•
Suilt·in receiver input hysteresis (1 V typ)
•
High receiver noise immunity (2V typ)
• Temperature insensitive receiver input thres·
holds track bus logic levels
• DTL/TTL compatible disable and output
•
Molded or cavity dual·in·line or flat package
•
High speed
typical application
+5V
+5V
18Dn
fBUn
120.0 Unified Data Bus
--, r- --,
390n
I I
I I
I 1
I I".
_.J
~1.!!6
I
I
_.J
connection diagram
Dual·ln·lina and Flat Package
Vee
IN 1
OUT 1
IN 2
OUT 2
IN 4
OUT 4
IN &
OUT 5
IN 6
TOP VIEW
1·246
IN 3
OUT 3 DISABLE A
OUT 6 DISABLE B GNU
I
I
3BUn
c
s::
absolute maximum ratings
~
w
....
......
(Note 1)
7V
Supply Voltage
Input Voltage
Power Dissipation
C
5.5V
s::CO
600mW
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering,
CO
W
_55°e to +125°e
oOe to +70oe
_65°e to +150oe
DM7837
DM8837
....
3000 e
10 sec)
electrical characteristics
The following apply for V L
$
V CC
$
V H, T L
'RECEIVER
INPUT
PARAMETER
$
TA
DISABLE
INPUT
$
T H, unless otherwise specified (Note 2)
OUTPUT
COMMENTS
MIN
TVP
MAX
UNIT
High Level Receiver Threshold DM7B37
VTH
OBV
l6mA
Output<04V
1,65
225
265
V
High level Receiver Threshold
DMBB37
VTH
OBV
l6mA
Output<04V
180
225
250
V
Low Level Receiver Threshold
V
DM7837
VTH
O,BV
-400 rnA
Output>24V
097
130
163
Low Level Receiver Threshold DMB837
VTH
OBV
-400 rnA
Output>24V
105
1.30
1 55
Maximum Receiver Input Current
4V
Maximum Receiver Input Current
Vee = V H
4V
Vee = OV
Logic "1" Input Voltage
Disable
05V
Y,N
l6mA
Output<04V
Logic "0" Input Voltage
Disable
05V
Y,N
-400~A
Output> 24V
05V
OBV
-400~A
4V
OBV
l6mA
Logic ",;, Output Voltage
Logic "0" Output Voltage
logiC
"'"
Input Current
500
p.A
10
500
~A
20
V
OB
V
V
24
025
24V
Disable
V
150
04
V
SO.O
~A
55V
20
rnA
Logic "0" Input Current. Disable
4V
04V
-32
rnA
Output Short Circuit Current
05V
OV
-550
rnA
Power Supply Current
4V
OV
Per Package
45.0
600
rnA
Input Clamp Diode
-12mA
-12 rnA
TA
-10
-15
V
logiC
"''''nput Current Disable
OV
Vee'" V H
",
25°C
-18.0
The following apply for Vee'" 5V. TA = 2SoC unless otherwise specified.
Propagation Delays.
Receiver Input to Logic "1" Output
OV
Note 3
20
30
ns
Receiver Input to Logic "0" Output
OV
Note 4
18
30
ns
Disable I nput to Logic "1" Output
OV
Note 5
9
15
ns
Disable Input to Logic "0" Output
OV
Note 5
4
10
ns
Note 1: Voltage values are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
Note 2: For DM7837: VL =4.6V, VH = 5.6V, TL =-55·C, TH = +125·C
For DM8837: VL = 4.75V, VH = 5.26V. TL = O"C. T H ';' +70·C
Note 3: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 1.3V to VOUT = 1.5V, VIN = OV to 3V pulse.
Note 4: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 2.3V to VOUT = 1.6V, VIN = OV to 3V pulse.
Note 5: Fan-out of 10 load, CLO AO = 15 pF total. Measured from VIN = 1.5V to VOUT = 1.5V, VIN = OV to 3V pulse.
1·247
D
00
(W)
00
00
Series 54/74
:=IE
c
"00
(W)
00
.....
DM7838/0M8838 quad unified bus transceiver
general description
features
The DM7838/DM8838 are quad high speed drivers/
receivers designed for use in bus organized data
transmission systems interconnected by terminated l20n impedance lines. The external termination is intended to be a l80n resistor from the
bus to the +5V logic supply together with a 3900
resistor from the bus to ground. The bus can be
terminated at one or both ends. Low bus pin current allows up to 27 driver/receiver pairs to utilize
a common bus. The bus loading is unchanged
when Vee = OV. The receivers incorporate hysteresis to greatly enhance bus noise immunity. One
two-input NOR gate is included to disable all
drivers in a package simultaneously.
• 4 totally separate driver/receiver pairs per
package
• 1V typical receiver input hystereSiS
• Receiver hysteresis independent of receiver
output load
• Guaranteed minimum bus noise immunity of
1.3V, 2V typo
• Temperature·insensitive receiver thresholds
track bus logic levels
• 20~A typical bus terminal current with normal
Vee or with Vee = OV
• Open collector driver output allows wire-OR
connection
• High speed
• Series 74 TTL compatible driver and disable
inputs and receiver outputs
:=IE
c'
typical application
+5V
laon
120n Unified Data Bus
--, r- --,
1I
I I
11
I I".
_.J
~.!!.'I
connection diagram
Dual In·Line and Flat Package
IUS 3
•.,3
OUT3
IUS4
114
TO' VIEW
1-248
DUT4 DISABLES
GaD
1
1
1
1
_.J
3900
c
3:
....
CD
absolute maximum ratings
7V
55V
600mW
Supply Voltage
Input and Output Voltage
Power DIssipation
Operating Temperature Range
DM7838
DM8838
Storage Temperature Range
-5SoC to +12SoC
o°cto +70°C
-6SoC to +150oC
300·C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
DM7838/0M8838. The following apply for V L ~ vee:::;'; V H' T L
PARAMETER
DISABLE
INPUT
DRIVER
INPUT
s: T
BUS
PIN
A
COMMENTS
MIN
8u.< 100~A
2.0
logiC "1" Input
Voltage' Disable
V
,N
2V
4V
Logic "0" Input
Voltage Disable
V ,N
2V
50mA
Bu.<07V
logic "1" Input
Voltage. Driver
08V
V ,N
50.mA
Bu.24V
097
1.30
163
V
08V
VTH
-400~A
Receiver output
> 2.4V
105
1.30
155
V
mA
<04V
DM7838
Low Level Receiver
Thre.hold. DM8838
logiC "1" Input
Current: Disable
and Driver
5.5V
5.5V
1
Logic "1" Input
Current. Disable
and Driver
2.4V
2.4V
40
~A
logiC "0" Input
Current: Disable
and Dnv9r
04V
04V
-16
mA
MaXimum Sus
Current
OSV
0.8V
4V
Vee;; V H
20
100
~A
MaXimum Bus
Current
OSV
08V
4V
Vee'" OV
2
100
~A
Low Level Bus
Voltage
OSV
2V
logiC "1" Output
Voltage. Receiver
0.8V
O.SV
0.5V
LogiC "0" Output
Voltage Receiver
08V
O.SV
4V
16mA
Output Short Circuit
Current. Receiver
0.8V
O.SV
O.5V
OV
0.4
SOmA
07
V
2.4
-4oo~A
0.25
Vee
=V H
V
-18
0.4
V
-55
mA
50
70
mA
=25°C
-1
-1.5
V
Propagation Delays
Disable to Bus "1"
Note 3
19
30
ns
Disable to Bus "0"
Note 3
15
23
n.
Draver Input to Bus "1"
Note 3
17
25
n.
Driver Input to Bus "0"
Note 3
9
15
n.
Bus to LogiC "1"
Receiver Output
Note 4
20
30
n.
8us to Logic "0"
Receiver Output
Note 5
18
30
ns
Supply Current
Input Diode Clamp
Voltage
(1)
V
High Level Receiver
Threshold DM8838
Threshold
c
3:
W
TYP
Bu.< l00~A
Thre.hold· DM7838
CD
(1)
(1)
~ T H unless otherwise specified (Note 2).
RECEIVER
OUTPUT
W
.......
OV
2V
-12mA
-12mA
Per Package
-12mA
TA
The follOWing apply for Vee = 5V, T A '" 25°C unless otherwise specified
Note l' VDttaga values are With respect to network ground terminal Positive current II defined as current Into the referenced
.on
-'2'
For DM7838 VL -45V. VH =6 5V. TL = -Sji°C. TH = ' o2SoC
For DMBB38 VL"4 75V. VH = 525. TL =0 C, TH -70 C
Note3' 91 n from bus Pin to Vee and 2QO{l from bus pin to ground, CLOAD -15 pF total Measured from VIN == 1 5V to
Vaus-15V.VIN ==OV to 3V pulse
Note 4: Fan-out of 10 load. CLOAO - 16pF total Measured from VIN -1.3V to VOUT "" 1 5V, VIN -OV to 3V pulse
Note 6: Fan-out of 10 load. CLOAO = 15 pF tota~ Measured from VIN '"' 2 3V to VOUT = 1 5V, VIN - OV to 3V pulse
1-249
o
Series 54/74
DM7853/DM8853 dual retriggerable resettable
monostable multivibrator
general description
The DM7853/DM8853 is a dual retriggerable,
resettable monostable multivibrator similar to the
DM9602/DM8602 but with a unique input triggering logic.
Once fired, the accuracy and performance of the
DM7853/DM8853 is identical to that of the
DM9602/DM8602.
This device has two trigger inputs-a standard
input and a delayed input-which are Exclusive
OR'ed together_,In the dual-edge triggering mode,
the two inputs are tied together. On eithEr a
positive or negative transition the Exclusive-OR
logic is satisfied for a length of time equal to the
delay on the delayed input-approximately 15 nsthus triggering or retriggering the one-shot.
• 72 ns to 00 output width range
• Retriggerable 0 to 100% duty cycle
• TTL input gating-leading AND/OR trailing
edge triggering
• Complementary TTL outputs
• Pulse width compensated for V cc and
temperature variations
• Resettable
features
01*~
1**
2**
t.LJ
GND
TOP VIEW
Co
**PINS fOR EXTERNAL TIMING
*A NON INVERTING BUFFER WITH DELAY
truth tables
Triggering Truth Table
t
L~H
H
H~L
1-250
CD
OPERATION
L
H
H
H
H
H
H
L
Trigger
H~L
H
L
L~H
H~L
$ameast
L~H
Sameast
X
X
Loading Rules
Dt
Trigger
LOAD
INPUTS
HIGH
3,4,5,11,12,13
1U L
I
I
LOW
1U L
Trigger
Trigger
Trigger
OUTPUTS
Trtgger
Reset
6,7,9,10
DRIVE FACTOR
HIGH
I
LOW
16 U L
I
8UL
absolute maximum ratings
Storage Temperature
--65°C to +150°C
Ambient Temperature Under Bias
-55°C to +125°C
Vee Pin Potential to Ground (Note 1)
-Q.5V to +8.0V
-Q.5V to +5.5V
Input Voltage (de) (Note 2)
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output When Output is HIGH-Q.5Vto +Vee value
Current Into Output When Output is LOW
50 mA
electrical characteristics
PARAMETER
DM7853 (T A = -55°C to +125°C, Vee = 5.0V ±10%)
LIMITS
+2SoC
-ss°c
CONDITIONS INote 3)
MIN
TVP
MAX
MIN
24
24
TVP
UNITS
+12SoC
MAX
MIN
TVP
MAX
Output HIGH Voltage (V OH )
Vee = 4.5V, IOH '" -0 80 rnA (Note 4)
Output LOW Voltage (VOL)
Vee'" 4 5V, IOL ::: 16 rnA (Note 4)
Input HIGH Voltage (V IH )
Guaranteed Input HIGH Threshold
Voltage
Input LOW Voltage (V 1L )
Guaranteed Input LOW Threshold
Voltage
Input LOW Current Hid
Vcc=55V.VIN"'04V
-16
-11
-16
-16
mA
Input HIGH Current (lIH)
Vee'" 5 5V, VIN =4 5V
60
10
60
60
~A
Input Clamp Voltage
V cc =50V,IIN=-12mA
-10
-15
V
Short CirCUit Current (lscl
Vee'" 5.5V, V OUT
-25
mA
Quiescent Power Supply
Vcc=55V
'"
04
20
33
02
04
20
20
OBO
080
1 OV (Note 4)
72
V
2.'
04
55
080
72
72
V
V
V
mA
Dram (lpo)
Standard Trigger I"put to
True Output ('ttoLH I
Delayed Tngger Input
Vcc =50V,R x =50kO
Cx "'O,C L ""15pF
Standard Trigger Input to
Complement Output (tPHL)
Delayed Trigger Input
Vee = 5 OV, Rx ;; 5.0 kn
ex ",o,e L
MInimum True Output
Pulse Width (tMIN)
Vee'" 50V, Rx "'50kSl
ex ",o,e L '" 15pf
MInimum Complement
Output Pulse Width (tMIN)
Vee "'50V,R x =50kn
Cx ",a,e L "'15pF
Pulse W,dth It)
Vee"" 5.0V, Rx "" 10 kSl
ex "1000 pF
Maximum Allowable Wiring
Cap. (Pins 2 and 14) (eSTRAY)
PinS 2 and 14 to GND
'"
25
35
ns
40
53
ns
29
43
ns
44
61
ns
72
90
ns
18
100
ns
342
3.16
lSpf
308
50
Timing Resistor (R x I
Note 1: The maximum Vee value of 8.0V IS not the primary factor
50
25
~s
50
50
25
50
50
OF
25
kn
determining the maximum Vee which may be applied
to a number of Interconnected devices. The voltage at a HIGH output IS approxlITI8tely 1 0 VBE below the Vee voltage, so
the primary limit 0(1 the Vee IS that the voltage at any Input may not go above 5 5V unless the current IS limited ThiS effectively Itmlts the system Vee to approximately 7 OV
Note 2: Because of the mput clamp duxfBS, excess current can be drawn out of the Inputs If the de Input voltage IS more negative than -Q.5V The mode ts designed to clamp off large negatlveac SWIngs associated With fast fall times and long lines ThiS
rMXlmum rating IS Intended only to limit the steady state Input voltage and current
Nota 3, Unless otherwise noted. 10 kSl resIStor placed between Pm 2 (141 and Vee, for all tests. IRX)
Not.4: Ground Pin 1 (151 for VOL on Pin 7 (9), or for VOH on Pin 6 (10), or for ISC on Pin 6 1101, also, apply momentary
wound to Pm 4 (12) Open Pm 1 (15) for VOL on Pm 6 (10), or for VOH on Pm 7 (9), or for ISC on Pin 7 (91
In
1·251
U
electrical cha racteristics
DM8853 (T A
= O°c to +75°C, Vee = 5.0V ±5%)
LIMITS
PARAMETER
+2SoC
DoC
CONDITIONS (Not. 31
MIN
TVP
MAX
MIN
TVP
2.4
3.4
+75°C
MAX
MIN
TVP
UNITS
MAX
Output HIGH Voltage (V OH )
Vee"" 4.75V, IOH = -0.80 rnA (Note 4)
Output LOW Voltage {VeLl
Vee"" 4.75V, IOL = 16 rnA (Note 4)
Input HIGH Voltage (V'H)
Guaranteed Input HIGH Threshold
Voltage
Input LOW Voltage (V 1L )
Guaranteed Input LOW Threshold
Voltage
Input LOW Current (I ILl
Vee"" 5 25V, VIN = O.4SY
-16
-1.0
-16
-16
rnA
Input HIGH Curtent (lIH)
Vee'" 5 25V, VIN "" 4 5V
60
10
60
60
~A
Input Clamp Voltage
Vee =50V,IIN '" 12mA
-10
-15
V
Short Circuit Current (Iscl
Vee = 5 25V, VOUT = 1.0V (Note 4)
-35
rnA
Quiescent Power Supply
Dram (lpo)
Vee = 5.25V, Ground PinS 1 and 2
Standard Trigger Input to
True Output (tPLH I
2.4
0.2
0.40
2.0
2.0
080
Complement Output (tPHL)
Delayed Trigger Input
V
V
0.80
V
55
72
kn
25
40
ns
40
58
os
Vee'" S.OY, Ax = 5 0 kn
Cx = 0, C L = 15 pF
29
48
ns
44
66
os
Vee = S.OY, Ax = 5.0
= 0, CL = 15 pF
72
V
0.40.
2.0
0.80
72
rnA
ex
Delayed Tngger Input
Standard Trigger Input to
2.4
0.40
Minimum True Output Pulse
Width (tMIN)
Vee = 50V, Rx '" 5.0kn
Cx = 0, CL = 15 pF
72
100
ns
Minimum Complement
Output Pulse Width (tMLN)
V ee =50V,R x =50kn
Cx =D, CL = 15 pF
78
110
ns
Pulse Width (t)
V ee =5.DV,R x =10kr!
CX :: 1000 pF
342
376
"S
Maximum Allowable WIring
Cap. (Pms 2 and 14)(CSTAAY)
Pms 2 and 14 to GND
Timing ReSIStor (R x )
308
50
50
50
50
50
50
Note 3:: Unless otherwise noted, 10 kfl resistor placed between Pm 2 (14) and Vee, for all tests (RX i
Note 4: Ground Pin 1 (15) for VOL on Pin 7 (9), or for VOH on Pm 6 (10). or for ISC on Pin 6 (10), also, apply momentary
ground to Pm 4 (12) Open Pm 1 (15) for VOL on Pm 6 (10), or for VOH on Pin 7 (9). or for ISC on Pm 7 (9)
1-252
50
50
pF
50
kQ
Series 54/74
DM8869. DM8869 TTL compatible hex LED drivers
general description
The DM8859, DM8869 are TTL compatible hex
LED drivers with programmable current source
outputs. The current sources are nominally set
at 20 mA but may be adjusted by external
resistors for any value between O-SO mAo Each
device contains six latches which may be set by
input data terminals. A strobe common to all six
latches enables the data input terminals. The
DM8859 current source outputs are switched on
by entering a high level into the latches and the
DM8869 current source outputs are switched on
by entering a low level into the latches.
The devices are available in either a molded or
cavity package. In order not to damage the devices
there is a limit placed on the power dissipation
allowable for each package type. This information
is shown in the graph on the back page.
o
schematic diagram
OM8859INPUT
DATA 1
-,""-.-. r--"" OUTPUT 1
COMMON
CURRENT
CONTROL
COMMON
STROlE
TO OTHER
lATCHES
TO OTHER
CURRENT
SOURCES
truth table
connection diagram
Dual-In-Line Package
Vee
La
I"OJ
..
DATA lIP,
"
DIP,
DATA lIP,
12
13
DIP,
11
DATA I/P3
10
01P3
I
COMMON
STROBE
0
0
1
1
2
STROBE DATA lIP,
3
•
DIP, DATA lIP,
5
DIPs
6
DATA lIP..
1
II
DIP.
GND
lIP
OM8859
DM8869
OIP (t+11
OIP (t+11
0
OFF
1
X
ON
OFF
alP (t)
alP
ON
(t)
TO. VIEW
1-253
absolute maximum ratings
(Note 1)
Supply Voltage
I nput Voltage
Output Voltage
+7.0V
+5.5V
+5.5V
Storage Temperature Range
~5°e to +150o e
Lead Temperature (Soldering, 10 seconds)
3000 e
electrical characteristics
PARAMETER
operating conditions
MIN
MAX
UNITS
Supply Voltage (Vee)
DM8859, DM8869
4.75
5.25
V
Temperature (T A)
DM8859, DM8869
0
+70
°e
MAX
UNITS
(Note 2)
CONDITIONS
MIN
TYP
Logical "1"'nput Voltage
Vee'" 4.75V
Logical "0" Input Voltage
Vee' 4.75V
0.8
Logical "1" Input Current
Vee' 5.25V, Y,N • 2.4V
40
Logical "0" Input Current
Vee' 5.25V, Y'N ·0.4V
Typical Output Current
Vee"" 5.0V, IADJ Pm Open, 25°C
Supply Current (each device)
Vee
Input Clamp Voltage
liN'" -12mA
2.0
V
-1.0
= 5.25V. Current Sources "Off"
-1.1
Note 1: "Absolute MaxImum Ratings" are those values beyond which the safety of the devIce cannot be Quaranteed. Except
fOr "Operatmg Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The
table of "Electncal CharacteristIcs" provides conditions for actual device operation
Note 2: Unless otherWIse specified minImax limits apply across the ooe to +70oe temperature range for the DM8859 and the
DM8869. All lVplcals are gillen for Vee = 5 OV and T A"" 25°C.
1·254
-1.6
20
V
~A
mA
mA
50
mA
-1.5
V
c
Series 54/74
'3:
00
00
...en
c
s:00
00
en
w
DM8861 MOS-to-LED 5-segment driver
DM8863 MOS-to-LED 8-digit driver
general description
features
The DM8861 and DM8863 are designed to be
used In conjunction with MOS Integrated CirCUitS
and common-cathode LED's In serially addressed
multi-digit dISplays.
•
Source or sink capability
per driver, DM8861
•
Sink capability per
drlver,DM8863
The DM8861 IS a 5-segment drrver capable of
Slnkrng or sour'crng up to 50 mA from each driver
•
MOS compatibility Ilow Input current)
The DM8863 IS an 8-dlglt driver Each driver IS
capable of Sinking up to 500 mA_
50mA
500 mA
•
Low standby power
•
High gain Darlington CirCUitS
u
schematic and connection diagrams
DM8861
DM8863
(1,4,5,7,10,12.1416)
(4,6,12,13,16)
(2,3,6,8,11,13,15,17)
A
-t-JVl.IV-.....-1
Dual-In-Line Package
~
E5
INS
C4
1:5
1:1
El
INt
Dual-In-Line Package
E4
IN4
I~
E3
0
Vss
IN8
OUT8
IN7
Ne
IN2
E2
C2
VOD
Dun
INt
IN2
Dun
TOP VIEW
Dun
IN6
OUTS
INS
OUTS
nUll
IN3
OU14
IN4
Voo
TOP VIEW
Order Numbers DM8861N or DM8863N
See Package 29
1·255
('I)
CD
CO
CO
:t
absolute maxim.um ratings
1
DM8861
Q
~
Input Voltage Range (Note 1)
CD
CO
CO
Collector (Output) Voltage (Note 2)
Collector (Output)-to-Input Voltage
:t
Q
DM8863
-5V to Vss
10V
10V
Emltter-to-Ground Voltage (V, :::: 5V)
Emltter-to-Input Voltage
-5V to Vss
10V
10V
10V
5V
Voltage at Vss Terminal With Respect to
Any Other Device Terminal
Collector (Output) Current
Each Col1ector (Output)
All Collectors (Output)
Continuous Total Dissipation
Operating Temperature Range
Storage Temperature Range
Lead TemperatUle (Soldering, 10 sec)
10V
10V
50mA
200 mA
800mW
O°C to +70°C
-65°C to +150°C
500 mA
600 mA
800mW
O°C to +70°C
300°C
-tl5°C to +150°C
300°C
dc electrical characteristics
DM8861 (V ss = 10V, T A = O°C to +70°C unless otherwise noted)
PARAMETER
CONDITIONS
On State Collector Emitter Voltage (VeE
ON)
Input
= 8.5V through
Ie " 50 rnA, T A
"
kn.
1
MIN
Input" 8 5V through 1 kD, VE "5V,
Ie" 50 rnA
Off State Collector Current (Ie
Ve " 10V, VE TO, lIN "40MA
1.2
1.5
100
Ve " lOY, VE "0, Y'N " _7V
Input Current at Maximum Input Voltage (II)
V,N " 10V,V E "O.le " 20 rnA
Emitter Reverse Current (IE)
Y'N "0, VE
2.2
5V, Ie "0
V
V
MA
3.3
Current Into Vss Terminal (Iss)
UNIT
MA
100
Off Set Collector Current (Ie OFF)
"
MAX
_9
25°C
On State Collector Emitter Voltage (VeE ON)
OFF)
TYP
V E = 5V.
rnA
100
MA
1
rnA
MAX
UNIT
DM8863 (V ss = 10V, TA = O°C to +70°C unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
= 25°C
V
15
Low Level Output Voltage (V OL I
VIN :::: 7V, lOUT:::: 500 mA, TA
Low Level Output Voltage (VOL)
VIN = 7V, lOUT
High Level Output Current UOH )
V OH "lOV, liN" 40MA
250
pA
High Level Output Current UOH )
VOH = lOY, VIN = 5V
250
pA
2
rnA
1
rnA
Input Current at MaxImum Input Voltage
(ld
=
1.6
500 mA
V IN '" 10V, loL = 20 mA
Current Into Vss Termmal (Iss)
V
ac switching characteristics
DM8861 (V ss = 7.5V. TA = 25°C)
PARAMETER
CONDITIONS
PropagatIon Delay TIme, Low to HIgh Level Output (Collector) (tPLH)
V 1H = 4 5V, V E =
PropagatIon Delay TIme, HIgh to Low Level Output (Collector) (tPHL)
RL
"200n, CL·"
MIN
a
15 pF
TYP
MAX
UNIT
100
n,
20
n,
DM8863 (V SS ~ 7.5V, T A = 25°C)
PARAMETER
CONDITIONS
PropagatIon Delay Time, Low to HIgh Level Output (tf'LH)
V'H
PropagatIon Delay Time, HIgh to Low Level Output (t PHL )
CL
BV, RL
21S1.
15 pF
Note 1: The Input IS the only devIce terminal whIch may be negatIve wIth respect to ground
Note
'-256
2: Voltage values are with respect to network ground termmal unless otherWIse noted.
MIN
TYP
300
30
MAX
.UNIT
n,
n,
c
s:
00
00
typical application
CJ)
...&
c
3:
00
00
B-Digit Calculator With LED Display
r-------,
* .l1~rJ..;,U
I
~
11
3
41U'
51012~-
~
r-____________
CJ)
W
I
I
140P
~"r.R~:~~~~,,~~.~,~,--~~,~,--~--~--~--~DI:,,~.--~~~~.~ -~
D
Voor--2av
26 R,
Voo fL--35V
25 R2
~~
osc, 1__ :::::B2~f vo"
~L-R_'-,r__-;'T-'__.'T-'__-,r__-ii-"__-ii'__-ii__-ii'._D--,SC'~VD"
CLEAR
MOST
SIGNIF
DIGI1181
+__+__+__+___'l-__l-__·l-I__'Ll---':'!!.'I---"",,--n-"~I.!L--1-____~
tfiNENSN4'
11~"
DIGIT LED
LEAST
SIGNIFICANT
DIGIT(H
I":-L~I~'\.-~~I~"-·~--+I"-~·~__
I""
j
f"--I------+OIGITI7)
I~
~
P - - I - - - - - - + DlGll15)
-!
I"-
1-'--1------+01011141
..!.
op'":-
'"-
1':--
1"-
~ ENTER
"t
IAtHRNATIVElV USE TWO NSNJ3 TRIPLE 118' DlGns AND ONE NSN131 DOUBlE 118
DIGIT WITH SEPARATE ""NUSSIGN AND CHANGE RESISTOR VALUES TO IOO'!
f-'---t------+omIT!31
-""
'·257
m
V
"
1.00
~
z
V-
\
1.02
Output Characteristic
V
ON CURRENTS
ON CURRENT RATIOS
1.04
:il
0:
I'
I I
1.06
0:
~
~
1.08
1
90
120
OUTPUT VOLTAGE {VI
typical application
'"
(1711-20DVDC)
R~22K
"*
c;'VP::;:--
{NOTE 2)
==:jt::::=='1
______
~0_
........V y y yy Y y......
,,
'"
SPERRY
~:::::OR
DISPLAVTUBE
5V~10%
DECODER/DRIVER
BI/RBO
OM5475
DUADLATCH
c D+--~~~~JT
AI 81
DM5490
COUNT
INPUT
DECADE
COUNTER
truth table
DECIMAL
OR
FUNCTION
RBI
0
1-262
D
C
B
A
0
0
0
0
1
X
0
0
0
1
2
X
0
0
3
x
0
0
4
X
0
0
0
5
X
0
0
1
6
X
0
0
7
X
0
8
X
0
0
9
X
0
0
BI/RBO
0
0
0
10
X
0
11
X
0
12
X
0
13
X
0
14
X
15
X
BI
X
X
X
X
X
0
RBI
0
0
0
0
0
0
0
b
c
d
0
0
0
0
0
11
I_I
I
I
0
1
0
0
i?
0
0
0
0
1
0
=1
_I
0
0
1
0
0
Lj
0
0
0
1
0
0
0
0
0
0
0
0
5
Ei-,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
DISPLAY
0
0
0
9
0
I
CJ
0
0
1-1
0
0
_I
C!
0
0
0
0
1 {
0
0
0
0
L
0
0
0
0
0
0
0
0
,-
1-1
L
-1
0
1-1
0
0
E
0
0
I
C
a
f/-;-/b
"/ Ie
d
SEGMENT
IDENTIFICATION
Series 54/74
c
3:
CO
CO
CO
-1=10
»
DM8884A high voltage cathode decoder/driver
(for driving Sperry and Panaplex IITM displays)
genera I description
The DM8884A is designed to decode four lines of
BCD input and drive seven·segment digits of gas'
filled readout displays. Two separate inputs are
provided for driving the decimal point and comma
cathodes.
program input in accordance with the programming
curve.
All outputs consist of switchable and program·
able current sinks which provide constant current
to the tube cathodes, even with high tube anode
supply tolerance. Output currents may be varied
over the 0.2 to 1.2 rnA range for multiplex opera·
tion. The output current is adjusted by connecting
an external program resistor (Rp ) from Vee to the
• Usable with AC or DC input coupling
• Current sink outputs
features
• High output breakdown voltage
• Low input load current
• Intended for multiplex operation.
• Input pullups increase noise immunity
o
logic and connection diagrams
v~
r-------------L----------,
:
OUTPUTS
j~~---L~
I
I
I
I
I
I
Dual-. n-L ins Package
INPUTS
lSfGMENT
DECODER
PROG
INPUT
A
o
0 PT COMMA CO.... A
INPUT INPUT OUTPUT
GND
TOPVIEW
....
OPT
COMMA
PROGRAMMABLE
:~:::I~~--+I------------I
L------------l-----------~
'NO
1-263
c(
~
CIO
co
co
:E
Q
absolute maximum ratings
Vee
Input Voltage (Note 11
Segment Output Voltage
Power Dissipation (Note 21
Transient Segment Output Current (Note 31
Operating Temperature Range
Storage Temperature Range
7V
Vee
80V
600mW
50mA
O°C to +70°C
-65°C to +150°C
electrical characteristics (ooe ~ T A ~ 70 e -
Unless otherwise noted). Vee
0
PARAMETER
CONDITIONS
MAX
UNITS
2.0
LogiC "1" Input Voltage
Vee
LogiC "0" Input Voltage
Vee = 4.75V
Logic "1" Input Current
Vee = 5.25V, V ,N = 2.4V
Positive Input Clamp Voltage
Vee = 4.7S, liN
Logic uO" I nput Current
Vee = 5.25V, V ,N
Power Supply Current
MIN
= 4.75V
= 5V ± 5%.
V
1.0
= 1 mA
= O.4V
p.A
-250
p.A
40
mA
S.O
V
Rp= 2.Sk,
Vee= S.25V,
V
15
All Inputs = SV
Negative Input Clamp Voltage
Vee
Segment Outputs:
All Outputs ON Current Ratio
= SV, liN = -12 mA, TA = 2SOC
-1.S
All Outputs = 50V
Output b Current = Ref.
Output b ON Current
Vee = SV, V OUT b = SOV,
TA =2SoC, Rp= lS.lk
Rp = 7.03k
Rp = 3.40k
Rp = 2.80k
Output Leakage Current
V OUT = 7SV
Output Breakdown Voltage
lOUT = 250p.A
Propagation Delay:
Any I nput to Segment Output
V
0.9
1.1
O.lS
0.45
0.90
LOS
0.22
O.SS
1.10
1.32
mA
mA
mA
mA
5
p.A
V
SO
Vee=5V,TA= 2SoC
p.s
10
Nota 1: ThiS limit can be higher for a current limiting voltage source.
Note 2: The maximum junction temperature IS 140°C, For operation at elevated temperatures, the deVice must be derated
based on a thermal resistance of 140°C/W 8 JA.
Nota 3: 'In -all applications tranSient segment output current must be limited to 50 rnA. This may be accomplished In DC applications by connecting a 2.2k resistor from the anode--supplv filter capacitor to the display anode, or by current limitmg
the anode dnver In multiplex applications.
truth table
_ _A
FUNCTION
,
0
2
··,
3
8
8
'0
"
""
"
'0'"
.
·Comml
.,,, .,,,
, ,
OPT
,
,,,
,,
,,
.
,
,
0
0
,
°
°0
0
0
0
0
0
,
, ,
, ,,
,
, ,
, ,
,, ,
, ,,
, ,
.
0
x
x
. . , . . ·.,
·
,
,
., ,
,
C
A
0
0
0
0
0
0
0
0
,
, ,
0
0
,
0
0
0
,
0
, ,
, , ,
,, ,,
, ,
,
, ,
, , ,
, , ,
, x x
0
0
0
0
0
0
0
0
X
X
0
0
X
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
,
°0
0
0
0
0
0
,
,
,° ,
,
,
,
,
,
, , ,
, ,
0
0
0
, ,
,
, ,
, ,, °
,
,
, °
,•
, ,
, ,, ,
, ,
0
°0
0
0
0
.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x x x x x x
X
X
X
X
X
X
typical application
DISf'f.AY
,
0
I
0
0
0
2
3
y
5
,
, ~
B
, LlS
j
r--v""----..,
I
I
I
I
I
I
0
0
0
0
0
0
./-:-/,
,, R::;
,
.r;I'
i
a
.
,
(nc,mal POint
P Comml
'Ollelmal PQlnt and CQfnml c.n bt displayed with or WIthout any numeral
typical performance characteristics
1·264
I
I
~YH9?9?~
: .'1:
I J..j
I
I ....
:
foI
BLANKING
I
I
I
~I!!'!-~---
I
I
::J
.".
(see DM7880 data sheet)
PANAPlHIIDISPlAY
1,1'1, I' I, , I'l~l"'"
DM8884A
! ++~
F:".....
i-
'"
Series 54/74
DM8885 MOS to high voltage cathode buffer
general discription
The 0 M8885 interfaces MOS calcu lator or cou nterlatch-decoder-driver circuits directly to sevensegment high-voltage gas-filled displays. The six
inputs A, B, 0, E, F, G are decoded to drive the
seven segments of the tube.
multiplex operation. The output current is adjusted
by connecting a program resistor (Rp) from Vee to
the program input.
Each output constitutes a switchable, adjustable
current source wh ich provides constant current to
the tube segment, even with high tube anode supply
tolerance or fluctuation. These current sources have
a voltage compliance from 3V to at least 80V. Each
current, source is ratioed to the b·output current
as required for even illumination of all segments.
Output currents may be varied over the 0.2 to
1.5 mA range for driving various tube types or
•
•
•
•
•
•
•
connection diagram
features
Current source outputs
Adjustable output currents 0.2 to 1.5 mA
High output breakdown voltage 80V min
Suitable for mUltiplex operation
Low fan-in and low power
Blanking via program input
Also drives overrange, polarity, decimal point
cathodes
n
truth tables
Dual-In-Line Package
A
B
D
E
F
G
DISPLAY
1
1
1
1
1
1
1
1
1
_I
r'
0
0
1
1
1
0
0
0
0
0
2
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1-1
U
0
0
0
0
0
0
0
0
1
'-I
0
0
1
1
0
0
0
0
0
0
0
0
1
0
INPUT"
j
OUTPUT"
0
1 (OFF)
1
o (ON)
~
_I
*Posltive Logic
'-j
5
5..,
1
EI
'3
.
b
cr
,cr
'i-:}
'C/'
Cf
d
C=(A·SD+EI"
TOP VIEW
typical applications
'5V
'5V
---I
---I
---I
VGGo--L.......
____ J
VGG
0-"'-...--0
____ ...I
-12V
Open-Drain MOS Output
Push-Pull MOS Output
1-265
10
00
00
00
absolute maximum ratings
::E
Q
7V
6V
80V
600mW
50mA
O°C to +70°C
-65°C to +150°C
300°C
Vee
Input Voltage
Segment Output Voltage
Power Dissipation (Note 1)
Transient Segment Output Current (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 3)
PARAMETER
CONDITIONS
Logic "1" Input Voltage
Vcc=47SV
Logic "0" Input Voltage
Vee"" 4.7SV
Logic "'" Input Current
Vee = 5 25V, VIN = 2 4V
Vee'" 5.2SV. VIN = 5 5V
Logic "O"'nput Current
Vee = 5.2SV. VIN = 04V
Power Supply Current
Vee = 5 25V, All Inputs =
Input Diode Clamp Voltage
V cc = 5V, liN'" -12 rnA. T A
MIN
TYP
MAX
20
V
0.8
2
av,
'"
Rp
UNITS
V
15
"A
4
400
"A
-300
-600
"A
22
31
rnA
-09
-15
= 2 2k
2SoC
V
Segment Outputs.
Outputs a, f, 9 OnCurre"t RatiO
All Outputs'" SOV, Output b Curr = Ref.
0.84
093
1:02
Output c On Current RatiO
All Outputs = SOV, Output b Cun = Ref
1.12
125
D8
Output d On Current RatiO
All Outputs = 5OV. Output b Curr '" Ref
0.90
1.00
1.10
Output e On Current RatiO
All Outputs = SOV. Output b Curr '" Ref
0.99
110
ill
Output b On Current
Vee = 5V, V OUT b = SOY, TA = 2SoC, Rp '" 181k
018
0.20
0.22
rnA
Vee'" 5V, V OUT b= 50V, TA '" 25°C, Rp '" 7 03k
045
050
0.55
rnA
Vee = 5V. V OUT b= 50V. T A = 25°C, Rp:= 340k
090
100
1.10
rnA
Vee = 5V, Your b= 5OV, TA = 25°C, Rp = 220k
135
1.50
1.65
rnA
Output Saturation Voltage
Vee = 4.75V,l ouT b = 2 rnA, Rp '" 1k ± 5% (Note 4)
08
25
Output leakage Current
VouT=75V,VIN"'08V, Rp!:: 1k
0003
0.003
3
"A
3
"A
Output Breakdown Voltage
lOUT = 250 /JA, VIN = O,SV
VOUT= 75V, VPAOG = 0 4V
80
110
V
V
Propagation Delays
I nput to Segment Output
Vee = 5V, TA = 25°C
04
10
~s
Note 1: Maximum junction temperature is 130°C. For operating at elevated temperatures, the deVice must be derated based
on a thermal resistance of 150°C/We JA.
Nota 2: In all applications transient segment output current must be limited to 50 mAo This may be accomplished
In DC applicatio'ns by connecting a 2.2k resistor from the anode-supply filter capacitor to the display anode, or by current limiting the
anode driver in multiplex applications.
Nota 3: MinImax limits apply across the guaranteed operating temperature range of ooe to +70o e, unless otherwise specified.
Typicals are for Vce = 5V, TA = 2SoC. Positive current is defined as current into the referenced pin.
Note 4: For saturation mode the segment output currents are externally limited and ratioed.
typical performance characteristics
1-266
(see DM7880 data sheet)
Series 54H/74H
illS
REFERENCE
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below.' Refer to the alpha·numerical index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
Devices
Pg.
DM54HOO
DM74HOO
DM54H01
DM74H01
DM54H04
DM74H04
DM54H05
DM74H05
DM54HOB
DM74HOB
DM54H10
DM74H10
DM54H11
DM74H11
DM54H20
DM74H20
DM54H21
DM74H21
DM54H22
DM74H22
DM54H30
DM74H30
DM54H40
DM74H40
DM54H50
DM74H50
DM54H51
DM74H51
DM54H52
DM74H52
DM54H53
DM74H53
DM54H54
DM74H54
DM54H55
DM74H55
DM54H60
DM74H60
DM54H61
DM74H61
DM54H62
DM74H62
DM54H71
DM74H71
DM54H72
DM74H72
DM54H73
DM74H73
DM54H74
DM74H74
DM54H76
DM74H76
DM54H7B
DM74H7B
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·1
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
2·6
:i·6
2·6
2·6
2·6
2-6
2·6
2·6
2-6
2·6
2·6
PACKAGES
Molded DIP (N)
Fig.
3
3
3
3
3
3
3
3
3
3
3
3
.3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
3
3
Pg.
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
Cavity DIP (D}(J)
Fig.
Pg.
Type
11
11
11
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
11
11
Flat Pack (F}(W)
Fig.
Pg.
Type
Metal Can (G}(H)
Fig.
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
2·9
TEST
CIRCUITS
Fig.
Pg.
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
2·7
'Order Numbers: use Device No. suffixed with package letter, i.e. DM54HOW.
2·i
en
.
CD
Series 54H/74H
CD
tn
Series DM54H/DM74H
general description
The Series 54H/74H extends the breadth of the
Series 54/74 Family by adding a product lir,e
which is approximately twice as fast as the basic
series. The products are completely miscible
connection diagrams
within a system; and it is generally considered
good engineering to optimize a design by utilizing
the Series 54H/74H only where needed for higher
speed.
Dual·ln·Line Package Only (Can't on Page 2·6)
DM54HOO/DM74HOO
quad 2·onput NAND gate
DM54H01/DM74H01
quad 2·onput NAND gate
(open collectorl
DM54H04/DM74H04
hex inverter
DM54H05/DM74H05
DM54HOB/DM74HOB
quad 2·onput AN 0 gate
DM54H10/DM74H10
trople 3·onput NAND gate
hex Inverter
(open collectorl
7
GND
DM54H 11/DM74H 11
triple 3-input AND gate
DM54H20/DM74H20
dual 4·input NAND gate
DM54H21/DM74H21
dual 4-input AND gate
DM54H22/DM74H22
dual4·input NAND gate
(open collector)
DM54H30/DM74H30
8·,nput NAND gate
DM54H40/DM74H40
dual 4·input NAND buffer
7
GND
2·'
absolute maximum ratings
Supply Voltage
Input Voltage
operating conditions
7V
5.5V
Supply Voltage
DM54HXX
DM74HXX
Operating Temperature Range
--6SoC to +125°C
Senes 54H
Senes 74H
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
125
70
°e
°e
Temperature
oOe to +70oe
-65°e to +150oe
300°C
DM54HXX
DM74HXX
1/1
.~
...
electrical cha racteristics
CI)
CIJ
\
PARAMETER
CONDITIONS
Input Diode Clamp Voltage
Vee = 5.0V, TA = 25°e,11N =-12 mA
Logical "1" Input Voltage
Vee = Mm
Logical "0" Input Voltage
Vcc=Mln
MIN
TYP
MAX
UNITS
-1.5
V
0.8
V
20
V
Logical "1 ".Output Voltage
All Devices, Except DM54H40/DM74H40
Vee = Min, 10 = -500J.lA, Y'N = 2.0V or 0.8V
2.4
V
Vee = Min, 10 = -1.5 mA, Y'N = 2 OV or 0.8V
24
V
and Open Collector Circuits
DM54H4Q1DM74H40
Logical"O" Output Voltage
All Devices, Except DM54H40/DM74H40
DM54H40/DM74H40
0.4
0.4
Vee = Min, 10 = 20 mA; Y'N = 2.0V or 0 8V
Vee = Mln,l o = 60 mA, Y'N = 2.0Vor 0.8V
V
V
Logical "1" Output Current
All Open Collector CirCUits
Except DM54H60,DM54H62
DM74H60,DM74H62
DM54H61. DM74H61
250
320
570
50
Vee = M In, V OUT = 5.5V, Y'N = 2.0V or O.SV
@-55°e
@ooe
V OUT =22V
Logical "0" Input Current
Vee = Max, VIN
Logical "1" Input Current
Vee = Max, VIN
Vee = Max
=O.4V
=2.4V
-2.0
50
1.0
J.lA
J.lA
J.lA
J.lA
mA
J.lA
mA
Output Short CirCUit Current (Note )
All CirCUits Except DM54H40/DM74H40
and Open Collector Circuits
DM54H40/DM74H40
Vee = Max, V OUT = OV
-40
-100
mA
VOUT = OV
-40
-125
mA
Supply Current
Vee = Max
DM54HOO/DM74HOO
Logical "0"
Logical' 1"
26
10
40
168
mA
mA
DM54H01/DM74HOl
Logical "0"
Logical "1"
26
68
40
10
mA
mA
DM 54H04/DM 74H04
Logical "0"
Logical "1"
40
16
58
26
mA
mA
DM54H05/DM74H05
Logical "0"
Logical "1"
40
16
58
26
mA
mA
DM 54H 081 DM 74H08
Logical "0"
Logical "1"
42
28
64
40
mA
mA
DM54H1Q1DM74Hl0
Logical "0"
Logical "1"
19.5
7.5
30
126
mA
mA
DM54H20/DM74H20
Logical "0"
Logical "1"
13
5.0
20
84
mA
mA
DM54H21/DM74H21
Logical "0"
Logical "1"
20
12
32
20
mA
mA
DM54H22/DM74H22
Logical "0"
Logical "1"
13
34
20
50
mA
mA
Note 1: Not more than one output shorted at a time, duration of short-circUit test not to exceed 1 second, and all tYPical
values are at Vee = 5V, TA = 25"e
2·2
...
electrical characteristics (con't)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
65
25
10
42
rnA
rnA
25
10.4
40
16
rnA
rnA
152
B.2
24
12.B
rnA
rnA
152
20
24
31
rnA
rnA
94
71
14
11
rnA
rnA
75
45
12
64
rnA
rnA
19
30
35
45
rnA
rnA
11
50
16
70
rnA
rnA
3.8
60
70
90
rnA
rnA
DM54H30/DM74H30
Logical "0"
Logical "1"
DM54H40/DIV\74H40
logical "0"
Logical "1"
DM54H50/DM74H50
DM54H51/DM74H51
Logical "0"
Logical "1"
DM54H521DM74H52
Logical "0"
Logical "1"
DM54H531DM74H53
DM54H541DM74H54
Logical "0"
Logical "1"
DM54H55/DM74H55
Logical "0"
Logical "1"
DM54H601DM74H60
On Level Current
Off level Current
DM54H61/DM74H6!
On Level Cu rrent
Off Level Current
DM54H62/DM74H62
On Level Current
Off Level Current
DM54H71/DM74H71
19
30
rnA
DM54H721DM74H72
16
25
rnA
DM54H731DM74H73
32
50
rnA
DM54H74/DM74H74
30
50
rnA
DM54H761DM74H76
32
50
rnA
DM54H78/DM74H78
32
50
rnA
MAX
UNITS
62
59
10
10
ns
ns
75
10
12
15
ns
ns
6.5
60
10
10
ns
ns
75
10
12
15
ns
ns
8.8
76
12
12
ns
ns
switching characteristics
PARAMETER
TA
= 25°C, Vee = 5V; N = 10, C = 25 pF, RL = 280n
CONDITIONS
MIN
TYP
DM54HOO/DM74HOO
tpdO
tpd1
DM54H01/DM74HOl
tpdO
tpd1
DM54H04/DM74H04
t"dO
tpd1
DM54H05/DM74H05
tpdO
tpd1
DM54HOBlDM74H08
tpda
tpd1
2-3
switching characteristics (con't)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
6.3
5.9
10
10
ns
ns
8.8
7.6
12
12
ns
ns
7.0
6.0
10
10
ns
ns
8.8
7.6
12
12
ns
ns
7.5
10
12
15
ns
ns
8.9
6.8
12
10
ns
ns
65
8.5
12
12
ns
ns
62
68
11
11
ns
6.2
68
11
11
liS
92
106
15
15
ns
ns
62
70
11
11
ns
ns
62
70
11
11
ns
ns
6.5
7.0
11
11
ns
ns
DM54H101DM74H10
tpdO
tpd'
DM54H111DM74H11
tpdD
...
tpdl
DM54H201DM74H20
G)
CIJ
tpdO
tpdl
DM54H21/DM74H21
t"dD
tpdl
DM54H22/DM74H22
tpdO
tpd'
DM54H30/DM74H30
tpdO
tpdl
DM54H401DM74H40
tpdO
tpdl
DM54H50/DM74H50
tpdO
tpd'
DM54H51/DM74H51
tpdD
tpdl
ns
ns
DM54H521DM74H52
tpdO
tpdl
DM54H53/DM74H53
tpdO
tpd'
DM54H541DM74H54
tpdO
tpdl
DM54H55/DM74H55
tpdO
tpdl
DM54H601DM74H60
(Thru Expandable Gates)
tpdO
tpd'
7.4
11.4
ns
ns
9.8
14.8
ns
ns
74
114
ns
ns
DM54H61/DM74H61
(Thru Expandable Gates)
tpdO
too,
DM54H62/DM74H62
(Thru Expandable Gatesl
t"dD
tpd'
DM54H71/DM74H71
tpdO(CLOCK)
tpd1 (CLOCK)
tpdO(PRESET)
tpd1(PAESETI
2-4
22
14
12
60
27
21
24
13
ns
ns
ns
ns
switching characteristics (con't)
CI)
en
CONDITIONS
PARAMETER
Maximum Clock Frequency
MIN
TYP
25
30
MAX
UNITS
ns
DM54H721DM74H72
DM54H71'DM74H73
DM54H761DM74H76
DM54H78/DM74H78
22
14
12
tpdO(CLOCK)
tpdl (CLOCK)
tpdO(CLEA R,PRESET)
60
t pdl(CLEAR.PRESET)
25
Maximum Clock Frequency
27
21
24
13
ns
ns
ns
ns
ns
30
DM54H74/DM74H74
13
85
tpdO(CLOCKI
t pd1 (CLOCKI
tpdO(C .... :AA,PRESETJ
tpdl (CLEAR,PRESET)
35
Maximum Clock Frequency
43
20
15
30
20
ns
ns
ns
ns
ns
loading table
DEVICES
DM54HOO(DM74HOO
DM54H01!OM 74HOl
DM54H04/0M74H04
DM54H05/DM74HQ5
DM54H08/DM74H08
DM54Hl0/0M74HlO
DM54Hl1/DM74Hll
DM54H20/0M74H20
DM54H21/DM74H21
DM54H22/DM74H22
DM54H30/DM74H30
DM54H40/DM74H40
DM54H50/DM74H50
DM54H51/DM74H51
DM54H52/DM74H52
DM54H53/DM74H53
DM54H54/DM74H54
DM54H551DM74H55
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM54H71/0M74H71
All I nputs Except
Preset and Clock
Preset
Clock
WEIGHTED
LOADS
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
DM54H72/DM74H72
All Inputs Except
Preset and Clear
Preset, Clear
1
2
DM54H73/DM74H73
J, K, and Clock
Clear
1
2
DM54H74/DM74H74
D
1
Preset and Clock
Clear
3
2
DM54H76iDM74H76
J, K, and Clock
Preset and Clear
DM54H78iDM74H78
J and K
Preset and Clock
Clear
1 Load
1
2
1
2
4
= 50 fJ.A @24V Logical "1" Input Current
= 2 rnA @ OAV Logical "0" Input Current
(All Inputs are guaranteed 1 rnA @ 5.5V for Logical
"1" breakdown test)
2·5
connection diagrams (con't)
III
Q)
DM54H50/DM74H50
expandable dual 2-wlde
2-Input AND-OR-INVERT gate
DM54H51/DM74H51
DM54H52/DM74H52
dual 2-wide 2-input
expandable 2-2-2-3-input
AND-OR-INVERT gate
AND-OR gate
GNU
DM54H53/DM74H53
expandable 2-2-2-3-lnput
AND-OR-INVERT gate
DM54H54/DM74H54
DM54H55/DM74H55
4-wlde 2-mput
expandable 2-wlde 4-input
A;'D-OR-INVERT gate
AND-OR-INVERT gate
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
dual 4-mput expander
tnple 3-mput expander
3-2-2-3-mput expander
DM54H71/DM74H71
DM54H72/DM74H72
DM54H73/DM74H73
J-K flip flop with AND-OR Inputs
J-K master-slave flip flop
dual J-K flip flop with
separate clocks
DM54H74/DM74H74
DM54H76/DM74H76
dual 0 edge-triggered flip flop
dual J-K master-slave flip flop
DM54H78/DM74H78
dual J-K flip flop with preset
and clear Inputs
2-6
en
...
CD
ac test circuits
CD
en
Va:=5V
R.
R.
!IOu
"'''
DINPUT
CLOCK
SEEIIOTE.
PULSE
...
~25~F
-:lFEILOTEC
oui,~ 0-....- - - - - '
NOTE A Clock Input ,... . hH die follOWIng chancttnltll:.
twlCLOCKI = 20 ns. PAR" I MHz
NOTE B 0 IAput (pula AI has die fafllMlnl ch.....1ItJCI
1sETUP = 10 ns, tw -aons, PAR .. 51% otclock'RR 0 1R,et
(pu" II ha the 1010I11III1 chlAlrtmlbCs !HOLD· 0 III. tw •
60 III, PRR .. MofclockPRR
NOTE C CL IIdu" ....IM Ind III Clpa;IIIMe
' - - - -......--o~~UT
Switching Characteristics, Clock and Synchronous Inputs
(High Lavel Datal
Vcc=5Y
R.
R.
DI!1
"'"
"'''TEe
r ;}.
DIIII'IIT
ClOCK
PULSE
SEEMOTE.
NOTE A Clock Input pul. hu the foll_ng ChlrRlenltll:s
= 20 M. PRR = 1 MHz
tw
NOTE B 0 Input (pulSl AI hH till follo"'lDl eIIlllICtlnlbes
Ism.... = 16 lIS, Iw = BOos-PRR= 1 MHz IndPRR 11&11% of
1~' clock PAR 0 mput(palse 81_ the foilowlfIg chUactlnlbCl
tHOLD .. 0 os. tw '" 8D os. Ind PAR II IIt% of clock PAR
NOTE C CL Inclullts pralle Ind Jt9 cI!NlCltanc.
TEST oJ..+-.::=::ii------t==-_l-oTE"
OUTPUT
OUTPUT
SWitching Characteristics. Clock and Synchronous I"puts
(Low-Level Datal
r--;;:----l
IIcc ·511
n.,
I
I
I
I
I
--.J
r ......
I
I
I
I
~~~--.----.-~
I
I
I
i
I
I
IL-
I
~~~~ 0---1-
I
c.
z&,FT
...
SEENQTEC
I
I
I
I
-!!"~~~J
--o::.~
NOTE A anr or Preset Inpu1l 1ft dominate regIIrdless of dOlk
er.lKlnputs
NOTEB a.,or P'lIRllnpulpubechara:bnsbcs VINClI"'3V,
VINIDI • IV, 1, • 10 • 7 1\1 'lptcLEARI • IpPRUETI • 18 ns.
PRR=1 MHz
NOTEt.CLlnctu"JigcI,lCItlnce
TEn
OI/TPI/T .....
Flip Flop Pr858t1Clear Propagation Delay Time.
R.
R.
noo
"'"
PRESET
CLEAR
INPUT
INPUT
TEST
OUTPUT
()l-+~=::i'------t==-_l-oTEST
OUTPIIT
NOTE A a.a, and Ptellt 10,111 dOminate dock or 0 IftJluts
NOTE 8 CIIII or Preset Inpuka clNl,.lIInltrcs IWCCLEARI '"
twlPRESETJ '" 25 ns. PRR z 1 MHz
NOTE C CL Includ.. ,ro" and III c.p...._
Asynchronous I nputs Switching Characteristics
2-7
Vco;:'5V
ac test circuits (con't)
I
GATt
BEING
TESTED
PULSE
GENERATOR
SEE NOTE A
"
t
JL
II
II
1..- _ _ _
C.
~15PF
-=
~
I
lOAD CIRCUIT FOR
DARLINGTON
5011
I:
I
1
"
I
LOADCIRcunfDR
I
I
I
1
c.
~E~:~EO
I
I
lOAD
_~
_ _':'JI
_
TEST
OUTPUT
Non A When testing tpdQ aod Ip,t, (all types), the clock IOput pulse chlnctenstlcs Ire' VINCU = 3V,
VINfO) = OV, t, = to = 1 ns, ""CLOCKI = 20 lIS, and PRR = 1 MHz.
NOTE B: AIIJ and K Inpub are It 2.4V.
NOTE C' When teltlng fCLOCK the clock Input cltalacttrtshts Ire VIN(OI = 3V, VINIOI = OV, t, = to '" 3 ns,
t"lClOCKI '" 10 AS. PAR = 40 MHz All J and K Inputs ale at 2 4V
NOTED CLlncludesprobeandllgc.aplICltaoce
Flip Flop Propagation Delay Times
truth tables
Vcc·SV
I
'. II
28Gn
I
I
I
tn
tn+1
J
0
0
K
a
0
ON
1
0
1
1
0
1
1
ON
all J-K flip flops
1
~
Non A VtN (11 = 3V, VINCOI = OV, to = t, = los, duty cycle = 50%, PRR = 1 MHz.
NOTE B CLlnchldes proba and I'll capac:ltaoCi.
NOn C. Ci Includes Jig capacltlnea
DM54H50, DM54H53, DM54H55
2-8
Tell
~~L~~~--1
280n
1
L-
1
I
I
r--;;:----l
I
I
.-11
Vcc- 5V
DM54H52/DM74H52 Loading For Gates
DM54H52/DM74H52
I
_
l.!!'"~_-=
DM14H04, DM54H05/DM74H05, DM54H1Di
DM74H1Q, DM54Hl1/DM74Hl1, OM54H2DI
DM74H20, DM54H21/DM14HZ1, OM54H2Z/
DM14H22, DM54HJO/DM74HJO, or DM54H401
DM74H40gatfi
(2) Inputpul5llisapph8lltoooeinputofoneAND
sectlOo, and 24V 15 applied to all unused
mputs of that AND section of the DM54H50/
DM74H50, OM54H51/0M14H51, OM54H52/
OM14H52, OM64H53/DM74H53, DM54H54/
DM74H54, or DM54H55/DM74H55 pte All
inputs of all unused AND sections ate grounded
NOn C AligatesarelnY~rtmgexcept the DM54Hll/
OM74Hll, DM54H21/0M74H21, and DM54H52/
OM74H52 only
NOTE 0 CL mcludes probe and liD capacitance
':"
I
I
DM14HOO, DM54H01/DM14H01, OM54H04/
"~'""
1
I~c'
NOTE A Tha pulse generator has the follOWing
characteristics V.,l1l = JV, Vm1m = OV, 11 = to = 7
RS, PRR = 1 MHz, duty cycle = 50%, and l"u' '" son
NOTE 8 InpUt con,htlons are establIShed for each
gate as follows
(1)
Input pulse IS apphed to onB Input and24VIs
apphad to aU unused mputs of tile DM54HOO/
sH~LonB
NOTE A V1N(1) = lV, V'N!O'" OV, to" I, = 7 RS. duty ~vc:le" 50%, PRR = 1 MHz, ZOUT
NOTE B CL loclud8Sllgcapacltance
NOTE C til ,ncludes'lg~apac'tlnce.
" I
I
tn
tn+1
0
ala
0
0
1
1
11
0
DM74H74 only
0CD
~
switching time waveforms
CD
en
C
3:
3V
UI
BV
:::t
.......
.p.
CLOCK
.NPUT
o INPUT
(PULSE A)
(SEE NOTE B)
C
3V
..
,
3:
....
.p.
IV
<".
:::t
3V
o INPUT
(PULSE BI
ISEE NOTE B)
---DV
v..,
DOUTPUT
Vo,
VOH
15V
tiOUTPUT
NOTE A Clock IIIIII! pul. hi. the follOloWng charKllrlll1CS fwrcLOCICI" 20 ... PAR .. 1 MHz
NOTE B 0 .put (pube AI hn the foilOWlflg clllrKllrlltlllS !sETUP = 10 III, tv. = 60 II, PAR IS SII% of
doll! PAR 0 .nput (pulse BI .... the foll_nl
ttmLD • 0 ns, Iw " 60 RI, PRR 15 511% 01
_act.,.tICS
deck PAR
NOTE C CL IlICIudn ,robe and flU eaplII:ltlillCe
Switching Characteristics. Clock and Synchronous Inputs
(High Level Datal
<7"
~~~~~+-~~----------3V
CLOCK
INPUT
~~------------------w
Je~~------------3V
INPUT
(PULSE A)
(SEEMOn 81
~9-------~~=r--t=-----------w
D'1O'\IT
(PULSE)
(SEE NOTE II
-,.;=----IV
---------+------~~--------------~H
11 OUTPUT
'------------------------ Vo,
11 OUTPUT
,------------------------V..,
-----------------'---------------~,
NOTE A. C..k. . . p........ t ... 'd.... chlrlctanlba t... 28 "'AA -, MHz
1I0TE B: D Input!.... AI"thefoll....... chll'ICtInItla tsETUP = 15
sa .... PAR =1MHz
andPAR .. 5I%ofthlclOlk'RR DmputlpulslBI_thlfollewnltlhlfICtIndJcI fttOLD"'O ....
1w. BI ns,lnd PAR 11611% ., cleck PAn
NOTE C. CLlncludlsprobt •• ,..cal*ltIIIIII
-.Iw.
Switching Characteristics, Clock and Synchronous Inputs
(Low Level Datal
2-9
switching time waveforms (con't)
1-=----------
V IN (1)
CLEAR
INPUT
I/)
PflESET
INPUT
CI)
...
CI)
C/)
Q OUTPUT
VOUTIOJ
VouTm
iI OUTPUT
VOUTIOI
NOTE A Clear or P,eset Inpuls are dommate re~alrlluss of clock or JK mputs.
NOTE B Clear or Preset topUI pulse charactenstlcs V'Nm = 3V, V'NID) " OV, I, "to = hs, lpjCLEAR) =
"'!PRESET) = 16 ns, PRR = 1 MHz
NOTE eeL meludes Jig capacllellce
Flip Flop Preset/Clear Propagation Delay Time.
3V
CLEAR
INPUT
OV
3V
PRESET
INPUT
r,;;;;;o------- Vo,
OOUTPur
,5V
'-------+-"----------Vo,
'"
-=;r=
' ' f:
--------,-+----------~,
iiOUT'UT
1.5V
..
I ,'_V_ _ _ _ __
-
VOL
NOTE A Cleat' and Prnet ,"put dominate clock 01 0 '''PLlts
NOTE B ClUJ' or Preset mput.. characteristICS' lwlCLEARI = tw(PflESETI = 25 liS, PRR" 1 MHz.
NOTE C: CL mcludll plObe .nd Jig CI,ilCltance.
Asynchronous I "puts SWitching Characteristics
ir.:::::-----::",...J-+--- V
1Nt1I
INPUT
OUTPUT
VOUTKlI
NOTE A. VINi11 =3V, V'MKI) = av, to .. 1, .. 7111,duty cycle- 60%,PRR" 1 MHz. lour "" son.
NOTE B' CL mcilides 1111 capacitance.
NOTE C e" Includnlig Capacltlnce.
DM54H52/DM74H52
2-10
en
...
CD
switching time waveforms (can't)
CD
CII
C
V1NW
s:
INPUT
U'I
V 1N10l
~
J:
......
VOUTI1I
C
INVERTING
OUTPUTS
s:
VOUTIOI
.....
~
VOUT(ll
J:
NON INVERTING
OUTPUTS
VOUTIOl
NOTE A V1N (1f" lV, VINIOI "OV, I, = to" 7 liS, PRR T MHz, duty cycle = 50%, lOUT"" 50%
NOTE B Cl Includes probe and Jig cap8elt~lIce. RL = 280n on all gates eKeept DM54H40 where Rl
=
93u
nOTE c CL =25pF on all devices
NOTE 0 C. = 1 3 pF tYPICal for ellpanders
DM54H52/DM74H52 Propagation Delays
CLOCK
INPUT PULSE
1'-_"",%_ _ _
VINIOI
,-----+-----VINllJ
'-------j------VINIOI
-------------1-"""'i---VOUTC1l
nOR Q OUTPUT
VOUTIO)
VOUTI1!
OOUTPUl
-------------1-"---- VOUTIOI
NOTE A When testing
tpdO
and tpd1 (all types), the clock mput pulse characteristics are VIN I1) = lV,
VIN1n) = OV, I, = to = 7 ns, \.IcLOCKI = 20 liS, and PRR = 1 MHz
NOTEB AtlJandKlnputsareat24V.
NOTE C When testmg fClOCK the clock mput charactenstlcs are
'fpIClOCK) "10 AS. PRR" 40 MHz AU J and K mputs are al 2 4V
NOTE 0 CL mcludes probe and IlgcaplCltance
VINIOI"
3V, V1NIO) = OV, I, = to = 3 ns,
Flip Flop Propagation Delay Times
INPUT
l"=----VINIOI
VOUTl11
OUTPUT
'----I--J+----Vounol
NOTE A V1N l1I" lV, VINIOI = OV, to = t1 7 OS, duty cycle = 50%, PRR
NOTE B CL mdudes probe and Ilg capaclIance
NOTEC C. mcludesllgcaplCllance
1 MHz
DM54H50, DM54H53, DM54H55
2-11
..
en
CD
Series 54L/74L
illS
REFERENCE
The following table references all Physical Dimension Drawings for the devices In this section. For Order
Numbers, see below. * Refer to the alpha-numerical index at the front of this catalog for complete device
title and function. Packages (pages I thru VI) are in the back of the catalog.
PACKAGES
DATA SHEETS
Molded DIP (N)
Devices
DM54LOO
DM74LOO
DM54LOl
DM74LOl
DM54L02
DM74L02
DM54L03
DM74L03
DM54L04
DM74L04
DM54L10
DM74L10
DM54L20
DM74L20
DM54L30
DM74L30
DM54L42A
DM74L42A
DM54L51
DM74L51
DM54L54
DM74L54
DM54L55
DM74L55
DM54L71
DM74L71
DM54L72
DM74L72
DM54l73
DM74L73
DM54L74
DM74L74
DM54L78
DM74L78
DM54L85
DM74L85
DM54L86
DM74L86
DM54L89A
DM74L89A
DM54L90
DM74L90
DM54L91
DM74L91
DM54L93
DM74L93
DM54L95
DM74L95
DM54L98
DM74L98
DM54L154A
DM74L154A
DM54L 164
DM74L164
DM54L165A
DM741165A
Pg.
3·3
3·3
3·3
3-3
3·3
3·3
3·3
3·3
3-3
3·3
3·3
3-3
3·3
3-3
3-3
3-3
3-31
3-31
3-7
3-7
3-7
3-7
3-7
3-7
3-10
3-10
3-10
3-10
3-10
3-10
3-11
3-10
3-10
3-10
3-34
3-34
3-22
3-22
3-37
3-37
3-40
3-40
3-43
3-43
3-45
3-45
3-25
3-25
3-48
3-48
3-50
3-50
3-29
3-29
3-52
3-52
Cavity DIP (D)(J)
Flat Pack (F )(W)
Fig.
Pg.
Fig.
Pg.
Type
Fig.
Pg.
Type
3
3
II
II
11
11
IV
J
J
IV
IV
IV
F
F
F
F
3
3
3
3
3
3
3
3
3
3
3
3
5
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
3
3
5
5
3
3
3
3
3
3
3
3
5
5
7
7
3
3
5
5
II
II
II
II
II
II
II
II
II
11
11
11
11
11
11
11
11
11
11
11
11
9
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
9
11
11
12
12
11
11
11
11
11
11
11
11
12
12
10
10
11
11
12
12
IV
IV
IV
IV
15
15
15
15
15
15
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
III
III
II
II
II
II
IV
IV
IV
F
IV
F
15
15
15
15
15
15
15
15
16
16
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
15
15
19
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
IV
IV
F
F
IV
IV
IV
IV
IV
IV
IV
V
V
V
V
F
F
F
F
F
F
F
F
F
V
V
F
F
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
III
III
D
D
15
15
15
15
15
15
15
15
16
16
17
17
IV
IV
J
J
J
J
16
16
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
III
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
V
IV
Metal can (G)(H)
Fig.
Pg.
Type
WAVEFORMS
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
18
18
10-5
10-5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
W
45A8C 10-23
45ABC 10-23
F
F
F
*Order Numbers: use Device No. suffixed with package letter. i.e. DM54LOOF.
3-i
PACKAGES
DATA SHEETS
Molded DIP (N)
Devices
DM54L187A
DM74L187A
DM54L192
DM74L192
DM54L193
DM74L193
DM71 L22
DM81 L22
DM71 L23
DM81 L23
DM75L11
DM85L11
DM75L12
DM85L12
DM75L51
DM85L51
DM75L52
DM85L52
DM75L54
DM85L54
DM76L 13
DM86L 13
DM76L24
DM86L24
DM76L70
DM86L70
DM76L75
DM86L75
DM76L76
DM86L76
DM76L93
DM86L93
DM76L97
DM86L97
DM76L99
DM86L99
DM78L12
DM88L12
DM78L70
DM88L70
3·ii
Pg.
3·55
3·55
3·58
3·58
3·58
3·58
3·65
3·65
3·65
3·65
3·69
3·69
3·72
3·72
3·75
3·75
3·80
3·80
3·80
3·80
3·86
3·86
3·88
3-88
3·29
3·29
3·91
3·91
3·91
3·91
3·45
3-45
3·93
3·93
3·96
3·96
3·99
3·99
3·29
3·29
Cavity DIP (D)W
Flat Pack (FIlWI
Metal Can (G)(H)
Fig.
Fig.
Pg.
F,g.
Pg.
Type
Fig.
Pg.
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3
3
5
5
5
5
3
3
5
5
5
5
3
3
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
12
12
12
12
12
12
12
12
12
12
9
9
12
12
12
12
12
12
12
12
12
12
12
12
11
11
12
12
12
12
11
11
12
12
12
12
11
11
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
III
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
15
15
16
16
16
16
15
15
16
16
19
IV
IV
V
V
V
V
IV
IV
V
V
V
15
15
15
15
IV
IV
V
V
II
II
II
II
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
Type
F
F
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
53
53
10·28
10·28
18
18
10·5
10·5
49
49
52
52
10·26
10·26
10·28
10·28
22
22
19
19
10·7
10·7
10·5
10·5
52
52
45ABDE
45ABDE
10·28
10·28
10·23
10·23
19
19
19
19
10·5
10·5
10·5
10·5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
W
F
F
F
F
Series 54L/74L
LOW POWER TRANSISTOR-TRANSISTOR LOGIC
general description
The Series 54L174L family is designed for applications requiring very low power dissipation.
Typically a system can be built with a factor-often power saving over the conventional TTL
integrated circuits, such as Series 54/74. Gates
typically draw 0.2 mA from a 5 volt supply thus
dissipating 1 mW. Flip flops pull about 1.0 mA
and therefore dissipate about 5 mW_ Speed however is not proportionately sacrificed. Flip flops
can typically be clocked at 11 MHz. Gate delays
are typically 25 ns.
The Series is manufactured with TTL circuitry and
employs low impedance Darlington outputs which
maintain output voltage waveform integrity when
capacitively loaded. The Darlington outputs also
allow greater guaranteed logical "1" fan out (20)
in case it is desirable to connect unused Inputs to
used inputs.
National's Low Power Series is also guaranteed to
drive two standard TTL unit loads from O°C to
70°C_
features
• Low power dissipation-typically 1 mW/gate,
5 mW/flip flop.
• Relatively high speed
Typical gate propagation delay time of 25 ns.
Typical flip flop toggle frequency at 11 MHz.
Typical MSI shift register toggle frequency at
12to 14 MHz.
• High dc noise margin-typically
TA = 25°C.
1 volt at
• Low impedance Darlington outputs provide low
ac noise susceptibility.
• Fan Out
10 Series 54L loads in logical "0" state
20 Series 54L loads in logical "1" state
2 Series 74 loads (74L only)
1 Series 54 load and 2 Series 54L loads
1 Series 54H load.
• TTL and DTL compatible.
Device types specified in the data sheet include:
NAND, NOR GATES
DM54LOOIDM74LOO (SN54LOO/SN74LOO)
Quad 2-lnput NAND Gate
DM54L01/DM74L01 (SN54L01/SN74L01)
Quad 2-ln[lut NAND Gate, O(l.en Collector
DM54L02/DM74L02 (SI'J54L02/SN74L02) Quad
2-lnput NOR Gate
DM54L03/DM74L03 (SN54L03/SN74L03) Quad
2-lnput NAND Gate, Open Collector
DM54L04/DM74L04 (SN54L04/SN74L04)
Hex Inverter
DM54L10/DM74L10 (SN54L 10/SN74L10)
Triple 3-lnput NAND Gate
DM54L20/DM74L20 (SN54L20/SN74L20)
Dual4-lnput NAND Gate
DM54L30/DM74L30 (SN54L30/SN74L30)
Eight-Input NAND Gate
AND-OR-INVERT GATES
DM54L51IDM74L51 (SN54L51/SN74L51)
Dual 2-wide AND-OR-INVERT Gate
DM54L54/DM74L54 (SN54L54/SN74L54)
Four-wide 3-2-2-3-lnput AND-OR-INVERT
Gate
DM54L55/DM74L55 (SN54L55/SN74L55)
Two-wide 4-lnput AND-OR-INVERT Gate
table of contents
General Description . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . ..
3-1
Absolute Maximum Ratings ... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . ..
3-2
Guaranteed Operating Conditions . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . _ 3-2
NAND, NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..
3-3
AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
Flip Flops . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-10
EXCLUSIVE-OR Gates . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . ..
3-22
Shift Registers .. _ ...... _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-25
3-1
general description (cont.)
FLIP FLOPS
DM54L78/DM74L78 (SN54L78/SN74L78)
Dual J-K Flip Flop
DM54L71/DM74L71 (SN54L71/SN74L71)
R-S Flip Flop
Operation is the same as the DM54L73/DM74L73
except that common CLEAR and CLOCK inputs
feed both flip flops. This frees two pins which are
used for separate PRESET inputs.
These R-S flip-flops use master-slave construction
so the slave is stable when the clock is held either
high or low. Clock disable at data inputs results in
hold times of 0 ns, and also clock-controlled data
entry.
..
EXCLUSIVE-OR GATES
DM54L86/DM74L86 (SN54L86/SN74L86)
Quad EXCLUSIVE-OR Gate
II)
~,
DM54L72/DM74L72 (SN54L72/SN74L72)
J-K Flip Flop
o
0..
The DM54L86/DM74L86 (SN54L86/SN74L86)
quad EXCLUSIVE-OR circuit performs as a halfadder: the output is a logical "1" only when the
inputs are at different logical states.
These J-K flip-flops use master-slave construction
so the slave is stable when the clock is held either
high or low. Clock disable at data inputs results in
hold times of 0 ns, and also clock-controlled data
entry.
~
o
-I
SHIFT REGISTERS
DM54L95/DM74L95 (SN54L95/SN74L95)
Four-bit Parallel-In Parallel-out Shift Register
Parallel or serial operation is selected by the
MODE input, which also enables one of the two
clock inputs. Parallel information must be
clocked-in allowing shift-left operation by connecting each output to the left-adjacent parallel
input.
DM54L73/DM74L73 (SN54L73/SN74L73)
Dual J-K Flip Flop
Operation is the same as the DM54L72/DM74L72
except that only single J and K inputs are
available.
DM76L70/DM86L70 Eight-Bit Serial-In ParallelOut Shift Register
DM54L74/DM74L74 (SN54L74/SN74L74)
Dual D Flip Flop
The DM76L70/DM86L70 utilizes Series 54L174L
compatible TTL circuitry to provide an eight-bit
serial-in parallel-out shift register. Other features
include gated serial inputs for strobe capability
and a clear input which, when taken to a logical
"0", asynchronously sets all flip flops to the
logical "0" state.
These monolithic, low-power, dual, edge-triggered
flip flops utilize TTL circuitry to perform D-type
flip flop logic. Each flip flop has individual clear
and preset inputs, and complementary Q and 0
outputs.
Information at D-input is transferred to the Q
output on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the
transition time of the positive-going pulse. When
the clock input is at either the high or low level,
the D-input signal has no effect on the state of the
output.
Because the flip flops are R-S instead of J-K, input
information may be changed immediately prior to
the triggering edge of the clock waveform. Logical
"1" levels on SA and SB enter logical "1's" into
the shift register. Clocking occurs on the positivegoing edge of the clock pulse.
absolute maximum ratings
Power Supply Voltage
Input Voltage
Fan Out Logic" 1"
Logic "0"
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
8.0V
5.5V
20
10
-65°C to 150°C
300°C
guaranteed operating conditions
3-2
Power Supply Voltage
DM54LXX, DM7XLXX
DM74LXX, DM8XLXX
4_5V to 5.5V
4.75V to 5.25V
Operating Temperature
DM54LXX, DM7XLXX
DM74LXX, DM8XLXX
-55°C to 125°C
O°C to 70°C
r-
o
NAND. NOR GATES
~
DM54LOO/DM74LOO. DM54L01/DM74L01. DM54L021
DM74L02. DM54L03/DM74L03. DM54L04/DM74L04.
DM54L 10/DM74L 10. DM54L20/DM74L20.DM54L301
DM74L30
."
o
~
...
CD
.....
.....
schematic diagrams
...
.
"
.r-
..
en
CD
::::! •
...
CD
Ul
""
U1
~
r-
.......
"r-
~
DM54LOO/DM74LOO. DM54L 10/DM74L 10
DM54L20/DM74L20. DM54L30/DM74L30
..
...
-
DM54L01/DM74L01
DM54L03/DM74L03
...
12.
V'"A+B
DM54L04/DM74L04
DM54L02/DM74L02
dual-in-line package connection diagrams
DM54LOO/DM74LOO
DM54L03/DM74L03
DM54L02lDM74L02
DM54L04/DM74L04
3·3
SUMMARY
dual-in-line package connection diagrams (cont.)
~
lI-
...CD
~
o
Q.
~
"
o
DM54L 10/DM74L 10
~
DM54L20/DM74L20
DM54L30/DM74L30
NAND, NOR GATES
flat package connection diagrams
.,.
__~"~~IO__~,
14~~"~~"
DM54LOO/DM74LOO
DM54L01/DM74LOl
.N•
• N•
,. ~~"~-r:1Z~-L!"~-r:IO~~,
DM54L02/DM74L02
DM54L04/DM74L04
.N.
Ne
DM54L 10/DM74L 10
3·4
Vee
Ne
DM54L20/DM74L20
DM54L30/DM74L30
NAND, NOR GATES
dc electrical characteristics
SYMBOL
PARAMETER
CONDITIONS
TEST
FIGURE
MIN
2
TYP
(NOTE 11
MAX
Logical "," Input Voltage
Vee'" MIN
I
V 1N1m
Logical "0" Input Voltage
Vee = MIN
2
VOUTtll
Logical "," Output
Voltage (Except
DM54LOI/DM74LOI,
DM54L03/DM74L031
Vee'" MIN. lOUT'" -200 pA,
V IN '" 0 7V. Other Inputs'" 2V
2
V IN '" 03V, Vee "'MIN.
V OUT '" 5.5V
6A
50
6A
6A
Output Current
DM54LOI/DM74L03
IOUTUl
DM54LOI/DM54L03
DM74LOI/DM74L03
V IN
'"
DaV, Vee =MIN,
V OUT '" 5 5V
V 1N =07V, Vee =MIN.
V OUT = 5.5V
VOUTIOI
Logical "0" Output Voltage
Vee" MIN. lOUT =: 2 mA,
V IN (All Inputs! '" 2V
VOUTIO}
Logical "0" Output Voltage
(Senes 74L Only)
Vee = MIN, lOUT =3.6 rnA,
V IN (All Inputs) = 2V
I
logical "," Input Current
Vee'" MAX, V IN '" 2.4V.
Other Inputs'" OV
4
Vee'" MAX, V IN = 5.5V
4
IIN(1)
I
Note 1: All tYPlcals at T A = 25°C.
Note 2: For the DM54L02/DM74L02, leeO)
Note 3: For the DM54L02/DM74L02, lee(O)
CD
CD
"A
III
200
"A
U1
200
"A
0.3
~
r-
.......
.....
~
V
V
"A
-180
"A
-8
-15
mA
6
120
200
"A
6
330
510
"A
5
Vcc = MAX,
V IN (All Inputs) '" 5V,
en
-120
Vcc '" MAX, V IN
VOUT '" OV
Logical "0" State
Power Supply Current
(Per Gate) (Except
DM54L02/DM74L021
(Note 31
V
"A
los
lec(o)
-I
-I
r-
10
Logical "1" Output
Short,Clrcult Current
(Except
DM54LOI/DM74LOI,
DM54L03/DM74L031
Vee'" MAX,
V IN (All Inputs) = OV,
lOUT'" 0
V
100
3
Logical "1" State
Power Supply Current
(Per Gate) (Except
DM54L02fDM74L02)
(Note 2)
2.8
0.4
Vee'" MAX, V IN '" 0 3V,
Other Inputs'" 4 5V
'eem
0.7
r-
Logical "0" Input Current
OV,
13
015
I'NIOI
'"
13
2.4
UNITS
V
V 1NIH
probe and 119 capacitance
Figure 38
EXCLUSIVE-OR GATES
(DM54L86/DM74L86)
schematic diagram
...
Note SchematiC diagram shows onlv one of
the four exclusive OR -gates
DM54L86/DM74L86
3-22
--OV
.Jt:90::;.;'--------,...
;;;:-+-I±-1~I~nI3V
111%
1
I
:<''''''T------'''''''~-~- - - - --l !"4-ISns
o INPUT (PULSE 01
I
1--1
QOUTPUT
>---i----- ____-.:
.. ::1',;;"",---3V
I
15ns--l
3V
i-oi'~---
I
'"
o INPUT (fIULSEC)
10%
~ t~~ld 104-
o INPUT (PULSE B)
""'''''''------oV
'--15ns
90% 1_-} _ _ _ _ _ _ _ 3V
19
I''''
CLOCK INPUT
----l
111%
OV
r-
o
:e
EXCLUSIVE-OR GATES
DM54L86/DM74L86
"'tI
o
:e
...
flat package connection
diagram
dual-in-line package
connection diagram
CD
-t
-t
r
C/)
...
CD
GN'
"
3A
3Y
CD
en
0'1
-1=0
r-
.......
......
-1=0
r-
"
"
2.
GN,
DM54L86/DM74L86
DM54L86/DM74L86
D
dc electrical characteristics
SYMBOL
PARAMETER
TEST
FIGURE
CONDITIONS (Note 1)
MIN
TYP
(Note 2)
MAX
UNITS
V 'N (1)
Input Voltage Required
to Ensure Logical "1" at
Any Input Terminal
39
Vee = MIN
V'N(O)
Input Voltage Required
to Ensure Logical "0" at
Any Input Terminal
39
Vee = MIN
V OUT (1)
Logical "1" Output Voltage
39
Vee = MIN, V 'N (1) = 2V,
V'N!O) = 0.7V,I LOAD = -200/lA
VOUT(O)
Logical "0" Output Voltage
40
Vee = MIN, V 'N (1) = 2V,
V'N(OJ = 0.7V, I OUT = 2mA
0.15
0.3
V
V OUTlOJ
Logical "0" Output Voltage
(Senes 74L Only)
Vee = MIN, ISINK =3.6 mA
V IN (All Inputs) = 2V
0.2
0.4
V
I'N(lI
Logical" 1" Level Input
Current (Each Input)
41
Vee = MAX, Y'N
Vee = MAX, Y'N
= 2.4V
= 5.5V
<2
I'N(O)
Logical "0" Level Input
Current (Each Input)
42
Vee
= MAX,
Y'N
= 0.3V
-0.22
los
Short Circuit Output
Current
43
Vee
= MAX,
V 'N (1)
lee(OI
Supply Current (Per Gate)
44
Vee = MAX
1.67
mA
43
Vee = MAX, V 'N (lI = 4.5V,
1.10
mA
lee(lI
Supply Current (per Gate)
2
1.3
= 4.5V,
V'N!O) = 0
V'N(O)
2.4
-3
V
1.3
0.7
2.8
-g
=0
V
V
20
200
-0.36
-15
/lA
/lA
mA
mA
Note 1: For conditiOns shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable Circuit type.
3-23
EXCLUSIVE-OR GATES
switching characteristics
PARAMETER
TEST
FIGURE
tpdO
PropagatIOn Delay Time to
Logical "0" Level (Other
Input Low)
45
tpd1
PropagatIOn Delay Time to
Logical "1" Level IOther
Input Low)
tpdO
tpdl
TYP
(Note 1)
MAX
UNITS
C L = 50 pF, R L = 4 kn
21
60
ns
45
CL =50pF,R L =4kn
37
60
ns
Propagation Delay Time to
Logical "0" Level IOther
Input High)
45
CL = 50 pF, R L = 4 kn
35
60
ns
Propagation Delay Time to
Logical" 1" Level IOther
Input High)
45
CL = 50pF, RL =4 kn
25
60
ns
SYMBOL
.
Q)
~
o
D..
~
o
CONDITIONS
MIN
Note 1: Switching parameter limits, sWitching parameter tYPlcals, and electrlcal parameter tYPlcals are given for
at T A = 25"C only.
..J
Vee -
5V
dc test circuits
v'"~'"'
~tl
Note
Each mput IS tested separately
Note- logical "0" and logical "1" mput
conditions are tested
Figure 39
Note
v.• ",
Note
Figure 40
Notes
Each Input IS tested separately
Note
Figure 43
v'f
OUTPUT
GE~~~!~OR ~_ 9'I=--_A~:::lS['
::::J1L,>_;-_'joI".1B--1~R-1'....._'•••*"--1*-,
~50 J-
'J
...._...:
Note
I
I
I
INPUT
OUTPUT
(SIINPDSITION A)
10%
CL Includes probe and 119 capacitance
~
150S---J
-+ ____ 'v
I
90%
I
I
90%
vT
Vr
1~1I'S-------1-=1O",%---ov
--i ~.. r
i~
--i~" 1--
vT
i
I
I '---+-1_..J__ -
I
I
~'''Z
I /v,
(SlIN
~15ns
---..j
I
poS~~ri~UB~ - - - - '
Vou,[D)
~v."'"
II
v,
lpdO
Figure 45
3·24
-
V
"''''
I
---i
IS
tested separately.
logical "0" and logical "1" mput
conditions are tested.
Figure 44
ac test circuits and waveforms
INPUT
Each mput
Figure 41
1 Each gate IS tested separately
2 When testlOg ICC('I, the output IS open
Figure 42
~
«-OPEN
i-
VoutlD)
O.9V
1.1V
13V
14V
16V
r-
o
:E
SHIFT REGISTERS
DM54L95/DM74L95
"tI
o
:E
...
CD
connection diagram
dual-in-line package
.
SERIAL
INPUT
flat package connection
diagram
.
'"'
fI
INI'UT
C
INPUT
Vee
en
...
CD
•N,ut
I""ur
-I
-I
r-
'"'
ClOCK 2
,
SERIAL
INPUT
CLOCK 1
INPUT
B
INPUt
C
INPUT
Vee
0
INPUT
MODE
DMS4L9S/DM74L9S
DM54L9S/DM74L9S
logic diagram
TRUTH TABLE
Mod. "'n InpAn Inp Bn
1
1
1
InpCn InpOn An+1 8 n +1
1
1
1
1
1
On+1
1
0
0
0
0
0
1
1
An
Bn
Cn
0
0
0
An
Bn
Cn
0
1
0
0
0
en +1
DM54L9S/DM74L9S
3-25
SHIFT REGISTERS
electrical characteristics (DM54L95/DM74L95)
SYMBOL
...I
lI-
...CD
~
o
Q..
o
CONDITIONS
= MIN'
= MIN
Vee = MIN
Vee = MIN
Vee = MIN
TEST
FIGURE
V 'NllI
Logical "1" Input Voltage
Vee
46,48
V 'NIO )
Logical "0" Input Voltage
Vee
47,49
= -200/lA
VOU T(l)
Logical "1" Output Voltage
VOUTIO)
Logical "0" Output Voltage
VOUT(Ol
Logical "0" Output Voltage
I'NIDI
Logical "0" Input Current
(Except Mode)
Vee
= MAX
V ,N
= 0.3V
50
I'N(Q)
Logical "0" Input Current
(Mode Only)
Vee
= MAX
V ,N
= 0.3V
50
I'N(1)
Logical "1" I nput Current
(Except Mode)
Vee
= MAX
I'N(1)
Logical "1" Input Current
(Mode Only)
Vee
= MAX
los
Short-Circuit Output Current
Vee
Icc
Supply Current
Vee
= MAX
= MAX
~
...I
PARAMETER
switching characteristics
SYMBOL
PARAMETER
lOUT
10UT= +2 mA
lOUT
= 3.6 mA
= 2.4V
= 5.SV
V ,N = 2.4V
V ,N = 5.5V
V OUT = OV
V ,N
V ,N
46,48
MIN
TYP
MAX
2.0
UNITS
V
0.7
2.4
3.1
47,49
0.13
0.3
V
47,49
0.2
0.4
V
-0.1
-0.18
mA
-0.2
-0.36
mA
51
10
100
/lA
/lA
51
20
200
/lA
/lA
-15
mA
52
-3
53
-9
4.8
8.0
TYP
MAX
mA
(DM54L95/DM74L95) (Note 1)
CONDITIONS
TEST
FIGURE
f MAX
Maximum Shift Frequency
Vee = 5.0V
CL = 50 pF
54
tpwICLOCK)
Clock Pulse Width
Vee = S.OV
CL = 50 pF
54
t pd (l)
Propagation Delay to a
Logical "1" A, B, C, or D
Vee = 5.0V
CL = 50 pF
tpd(O)
Propagation Delay to a
Logical "0" A, B, C, or D
tl
MIN
UNITS
14
MHz
90
44
ns
54
15
42
90
ns
Vee = 5.0V
CL = 50 pF
54
15
48
90
ns
Mode Control Logical "0" Setup
Time With Respect to CP 1
Vee = 5.0V
CL = 50 pF
55
120
55
ns
t2
Mode Control LogIcal "1" Setup
Time With Respect to CP2
Vee = 5.0V
CL = 50 pF
56
100
45
ns
t3
Mode Control Logical "0" Setup
Time With Respect to CP2
Vee = 5.0V
(Note 2)
CL = 50 pF
56
0
-43
ns
t,
Mode Control Logical" 1 " Setup
Time With Respect to CPl
Vee = S.OV
(Note 2)
CL = 50 pF
55
0
-50
ns
ts
Logical "1" Setup TIme at
Serial, A, B, C, or D Inputs
Vee = 5.0V
CL = 50 pF
54
50
20
ns
Is
Logical "0" Setup Time at
Serial, A, B, C, or D Inputs
Vee = 5.0V
C L = 50pF
54
50
13
ns
t7
Logical "1" Hold Time at
Serial, A, B, C, or D Inputs
Vee = 5.0V
(Note 2)
CL = 50 pF
54
0
-14
ns
ts
Logical "0" Hold Time at
Serial, A, B, C, or 0 Inputs
Vee = 5.0V
(Note 2)
C L = 50pF
54
0
-20
ns
6.0
Note 1: Switching parameter limits, sWitching parameter typicals, and electrical parameter typicals are given for VCC= 5V at
TA = 25°C only.
Note 2: Negative hold time values mdicate that data can be released prior to the time the clock reaches its 1.3V level.
3·26
SHIFT REGISTERS
dc test circuits
(DM54L95/DM74L95)
v"
MODE
V,nll)
V,nll)
CONTROL
OPEN
A
SERIAL
INPUT
A
"ood
1+
C
VlnlO)
0
OPEN
CLOCK
CLOCK 1
CLOCK 2
CLOCK
I
~
"-------I
~13V
CLOCK
Vy---3V
I
1----;>90
Note. Each output
OV
ov
TEST vou.I')
TESTVoutlOI
Note: Each output
tested separately.
IS
15
tested separately.
Figure 47
Figure 46
V"
v"
V,nlOI
MIJDE
V,nOI
SERIAL
'"nk
' '>od
~
v'nU))
CONTROL A
INPUT
r
--t=3
OPEN {
loPE, v..."'
OPEN {
CLOCK
OPEN
1
CLOCK 1
CLOCK 2
OPEN
":'
":"
I
~:2::90ns--------l
-
-
SEE
TEST
CLOCK 1
CLOCK 2
"::
Note
)-
":"
Each Input
IS
OV
TESTVou.IOI
TEST TABLE
CONTROL A
SERIAL
INPUT
TABLE
I
Figure 49
MODE
v,.
Vy
1--_>90 .. --------I
TESTVou.lll
v"
l,nUIl
.".
--,.ov
Vy
I
OV
Figure 48
45V
CLOCK 2
":"
ClOCK~--'V
Vy
Vy
I
lop"
CLOCK 1
CLOCK
tested separately.
APPLY GND
TEST
APPLV4.5V
MODE CONTROL
CLOCK 2
NONE
SERIAL INPUT
NONE
MODE CONTROL
A INPUT
MODE CONTROL
NONE
B INPUT
MODE CONTROL
NONE
C INPUT
MODE CONTROL
NONE
D INPUT
MODE CONTROL
NONE
CLOCK 1
NONE
MODE CONTROL
CLOCK 2
MODE CONTROL
NONE
Figure 50
TEST TABLE
v"
TEST
MODE
45V
CONTROL A
~
V,.
SEE
TEST
SERIAL
INPUT
TABLE
CLOCK 1
CLOCK 2
."
j""
.".
Note. Each Input IS tested separately.
APPLY 4.5V
APPLVGND
MODE CONTROL
NONE
SERIAL INPUT
MODE CONTROL
CLOCK 2
NONE
A INPUT
NONE
MODE CONTROL
B INPUT
NONE
MODE CONTROL
C INPUT
NONE
MODE CONTROL
MODE CONTROL
D INPUT
NONE
CLOCK 1
MODE CONTROL
NONE
CLOCK 2
NONE
MODE CONTROL
Figure 51
3-27
SHIFT REGISTERS
dc test circuits (cont.)
(DM54L95/DM74L951
Voo
MODE
CONTROL A
v,"
OPEN
SERIAL
INPUT
OPEN
CLOCK 1
OPEN
CLOCK I
CLOCK o----t~CL""OC~K.!.2_.J
...
CLOCK
CLOC~----3V
Q)
~
VT
I
CLDCKZ
O-+--"'"i!:!o!
CLOC~----'V
VT
I
o
VT
OV
Note Each output
~
15
VT
I
I---- ;;:':90us----.j
D.
I
OV
1----;;:-:90ns----.j
tested separately
TEST los
TEST Icc
Figure 53
Figure 52
o
)-
SERIAL
INPUT
...I
ac test circuits and waveforms (DM54L95/DM74L951
INPUTS
r---------i
I
I
Rl
IN9t6
-
4K IN916
lN918
-
L _ _ _l~C~I!2r- - - -L;;;c~ro-
lN916
-
I
I
I
I
I
___ J
- - -l
L- _ _
~m~D~r~ _ _ _
..J
.--
-Lrnc;;&iiro -
-,
L- _ _ ~Sa==L::,C:::l~
-
-
__ ..J
r---LiiAoCfficuiT4--- --,
___ ...J
L- _ _ ..!-=:l~lrC~
Notes
1. The pulse generators have the follOWing characteristics t1 '" 10 ns to 12 ns, to = 10 ns to 12 ns, and Zout ~ son
For pulse generator A tp > 150 ns and PRR ::: 500 kHz. For pulse generator B t p "'" 10 ns and PRR '" 1 MHz
When testing f max • vary PRR
2. Voltage values are With respect to network ground terminal.
3. CL Includes probe and Jig c::apaC::ltance
TA
VT
125°C
70°C
25°C
O°C
_55°C
O,9V
llV
13V
14V
16V
Figure 54
SERIAL lit
r-\
J
NOTE
r-\-------V'N'"
'--------I
A INPUT,",V'N=DV
Figure 55
3-28
' - - - - V'N'"
r-
o
SHIFT REGISTERS
~
connection diagrams (DM76L70/DM86L70, DM78L70/DM88L70) (DM54L164/DM74L 164)
-g
o
~
...
CD
en
...
CD
CD
en
U'I
~
Flat Package
DM76L 70/DM86L 70
Dual~ln~Line Package
DM76L70/DM86L70 (DM54L 164/DM74L 164)
r-
.......
.....
Flat Package
DM78L70/DM88L70 (DM54L 164/DM74L 164)
logic diagrams
Q2
OJ
~
r-
..
.,
06
.0
DM76L70/DM86L70, DM78L70/DM88L70 (DM54L 164/DM74L 164)
electrical characteristics(DM76L70/DM88L70,DM78L70/DM88L70) (Note 1)
SYMBOL
CONDITIONS
PARAMETER
MIN
TYP
V'Nlt)
Logical "1" I nput Voltage
Vee
V'NIO)
Logical "0" Input Voltage
Vee
VOUTlt)
Logical "1" Output Voltage
Vee
VOUTIO)
Logical "0" Output Voltage
Vee
= MIN
= MAX
= MIN, lOUT = -200 IlA
= MIN, lOUT = 2 rnA
VOUTIO)
Logical "0" Output Voltage
(Senes 74L Only)
Vee
= MIN,loUT = 3.6 rnA
<1
I'NI1I
Logical "1" Input Current
(Except Clear Input)
Vee
= MAX, V'N = 2.4V
<2
I'Nlt)
Logical "1" Input Current (Clear Input)
Vee
= MAX, V'N = 2.4V
I'Nlt)
Logical "1" Input Current
(Except Clear Input)
Vee
= MAX,
V'N
I'Nlt)
Logical "1" Input Current (Clear Input)
Vee
= MAX,
I'Nlt)
Logical "0" Input Current
(Except Clear Input)
Vee
= MAX,
I'NIO)
Logical "0" Input Current (Clear Input)
Vee
los
Output Short Circuit Current (Note 2)
Vee
Icc
Power Supply Current
Vee
= MAX, V'N = 0.3V
= MAX, VOUT = OV
= MAX
2.0
MAX
V
1.3
1.3
2.4
UNITS
V
0.7
2.8
V
0.3
V
0.4
V
10
IlA
20
Il A
= 5.5V
100
IlA
V'N
= 5.5V
200
IlA
V'N
= 0.3V
-120
-180
IlA
-240
-360
Il A
-9
-15
rnA
6
9
rnA
-3
Note 1: SWitching parameter limits, switching parameter typicals, and electrical parameter typicals are gIVen for
Vee
= 5V
at T A = 25°C only.
Note 2: Only one output should be shorted at a time.
3·29
...J
....'lit
.......
SHIFT REGISTERS
switching characteristics
'lit
SYMBOL
(DM76L70/DM86L70, DM78L70/DM88L70)
...J
It)
en
II)
...
II)
en
..i
lI-
...
II)
PARAMETER
CONDITIONS
TYP
6
12
UNITS
Minimum Clock Frequency
V cc
= 5.0V,
50% Duty Cycle
tpdO
Propagation Delay to a Logical "0"
From Clock to Output
Vcc
= 5.0V,
CL
= 50 pF
70
120
ns
tpd1
Propagation Delay to a Logical "I"
F rom Clock to Output
Vcc
= 5.0V, C L = 50 pF
40
90
ns
tpdO
Propagation Delay to a Logical "0"
From Clear to Output
Vcc
= 5.0V, C L = 50 pF
90
160
ns
= 5.0V, CL = 50 pF
= 5.0V, C L = 50 pF
tpw(CLOCKI Minimum Clock Pulse Width
Vcc
tpW(CLEARI Minimum Clear Pulse Width
Vcc
~
tSET-UP
Minimum Time That SA • 58 Data Must
Vcc
be Set·up Prior to Clock Pulse, t set . u p
= 5.0V, C L = 50 pF
...J
tHO LD
Minimum Time That SA • 58 Data Must
Vcc
be Held After Clock Pulse, t hold
= 5.0V,
teR
Clear Recovery Time'
0
CL
= 50 pF
Vee = 5.0V, T A
CL = 50 pF
= 25°C,
25
ns
40
25
ns
35
-10
80
(DM76L70/DM86L70, DM78L70/DM88L70)
30V
Y,
Y.
Y,
Notes: 1. Clock may be at either a Logical "1" or a Logical "0" while clearing.
2. NegatIve hold time values ind1cate SA- Sa infon:nation may be released
prior to the time the clock pulse reaches its 1.3v level.
3. Clear and Clock Waveforms: tr = tf = 15 ns (10%-90%,90%-10%
transition) f = 1 MHz
15M--j
I--
I ...",,,....------c=-J{OO%
j" ,,,
ov
I..9B%
I
~
CLOCK
VT
OY
---I
1(1%
~lS~$
.,~
S,,=5&
~
3V
Z 4V
CLEAR RECOVERY TIME
Figure 56
3V
60
-35
*Time required after removal of clear signal for clocking to occur.
switching waveforms
MHz
40
**Negative hold times indicate that data may be released prior to time clock reaches its 1.3V level.
3·30
MAX
'MIN
~
0
D.
MIN
ns
ns
120
ns
Series 54L/74L
DM54L42A/DM74L42A (SN54L42A/SN74L42A)
low power BCD to decimal decoder
general description
features
The DM54L42AiDM74L42A one-of-ten decoder
produces a low-power TTL logical "0" for the
decimal output corresponding to a BCD input
value from zero to nine, and a logical "1" for the
other nine outputs. When a BCD input greater
than nine is presented, all outputs are logical "1".
Conventional low-power TTL output gates assure
excellent low-power speeds and fan-out.
• Series 54L/74L compatible
• 15 mW typical power dissipation
• 50 ns typical propagation delay
logic and connection diagrams
Dual-In-Line Package & Flat Package
OUTPUTS
OUTPUT 0
INPUT A
L
15
14
11
12
"
10
9
OUTPUT 1
OUTPUl2
p-
r<
OUTPUl3
INPUT B
3
2
I
4
•
5
1
J
OUTPUT 4
GNO
OUTPUTS
TOPVIEW
DUTPUT5
INPUT C
DUTPUT6
OUTPU17
truth table
INPUT 0
INPUTS
OUTPUTS
OUTPUT 9
0
C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
•
0
1
2
3
4
5
6
1
0
I
1
I
1
I
1
1
I
1
1
0
1
I
0
1
I
1
0
I
0
1
1
1
1
1
1
1
1
0
1
1
1
I
0
1
I
1
1
1
0
1
1
1
1
1
1
1
0
1
0
I
0
I
1
1
1
1
0
1
I
I
I
1
1
1
1
1
1
0
I
1
1
1
0
1
1
1
1
1
0
0
I
I
0
0
I
I
0
0
I
1
1
1
1
1
1
1
1
1
OUTPUTS
A
0
0
1
1
1
.
9
I
I
I
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
I
I
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
3·31
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
(Note 1)
+8V
+5.5V
+5.5V
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
DM54L42A
DM74L42A
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
electrical characteristics
PARAMETER
+300°C
(Note 2)
CONDITIONS
MIN
TYP
2.0
1.3
MAX
UNITS
Logical "I" Input Voltage
DM54L42A Vee ~ 4.5V
DM74L42A Vee - 4.75V
Logical "0" Input Voltage
DM54L42A Vee ~ 4.5V
DM74L42A Vee - 4.75V
Logical "I" Output Voltage
DM54L42A Vee ~ 4.5V
DM74L42A Vee - 4.75V
lOUT ~ - 2OO IlA
Logical "0" Output Voltage
DM54L42A Vee ~ 4.5V
DM74L42A Vee - 4.75V
lOUT ~ 2 mA
lOUT ~ 3.6 mA
0.15
0.20
Logical "I" Input Current
DM54L42A Vee ~ 5.5V
DM74L42A Vee - 5.25V
V ,N
~
2.4V
<1
10
IlA
DM54L42A Vee ~ 5.5V
DM74L42A Vee - 5.25V
V ,N
~
5.5V
<1
100
IlA
Logical "0" Input Current
DM54L42A Vee ~ 5.5V
DM74L42A Vee - 5.25V
V ,N
~
0.3V
-0.10
Output Short Circu it Current
(Note 3)
DM54L42A Vee ~ 5.5V
DM74L42A Vee - 5.25V
V OUT
Supply Current
lee max
DM54L42A Vee ~ 5.5V
DM74L42A Vee - 5.25V
V
0.7
1.3
Propagation Delay to a Logical
"0" from Any BCD Input to Any
Output. tpdO
Vee ~ 5.0V
TA ~ 25°C
RL
Propagation Delay to a Logical
"I" from Any BCD I nput to Any
Output. tpd1
Vee~ 5.0V
TA ~ 25°C
RL ~4
~
~
2.4
OV
4 kn. CL
kn,C L
2.8
V
V
0.30
0.40
-0.18
V
V
mA
-3.0 -9.0
-15.0
mA
3.0
5.3
IT!A
~
50 pF
35
70
140
ns
~
50 pF
15
35
70
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherWise specified minImax limits apply across the _55°C to +12SoC temperature range for the DM54L42A
and across the oOe to 700e range for the DM74L42A. All typ,cals are given for Vee = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
switching times
TVPICAllNPIiT
VOLTAGE
WAVEfORMS
(SeeNllteU
TVPICAlOIiTPUT
VOLTAGE
WAVEFORMS
(SEE NOTE 4)
------t-...L.~~~- VOlin/II
V OUTI11
(SEE NOTES)
Note 1 The truth table gane,,,to, hIs tIIa follOWing ~hlrar:l.mIlCi VOUTI1,? 24V, VOUTIOI ::;; 04V,
t,. and l! < 15 ns, and PRR ~ 1 MHz Input 8, C, and 0 ttanSftfon$o~~urilfmultanIl'OUslywltho,
pno, to Input A trantilOOnS
Note2 CL.neludasp.obeand ,'gC8ll1lCItan••
Note 3 All diodes a.elN3064 0' equl~.lenl
3·32
,~
Notll4 Thfiwavefo,mrepreseot lIIeO output when A 1M g08$flom "0" 10"1"
he) wfth8=C=D~"O"
NOIli 5 ThiS wlI¥afo'm Ilpresantsthe 0 output when A goes from
h.e)
"1"to"O"wlth8=C~D="0"
VOUTIO,
dc test circuits
-j
.. j
reST
PER
TRUTH
TABlE
TEST
PER
TRUTH
TABLE
Note Eachauqlutl$Ieu.clMlHlmelv
.. j
reST
b----lt
PER
TRUTH
TABLE
v,.
SEE
OPEN
NOTE
Note Each.npullS ....... SIpIrIteIy
Note EachoutpullstesttdupI.ately
"
v,.
SEE
NOTE
OPEN
Note 1 Wlmt """'III'''((II.eII 'lI4IuI 'II"'" "Irattly
Note:l Wllln tt«1CIII1cc alt Inputs art FO\In~" Ind IMItputs 1ft open
3-33
Series 54L/74L
DM54L85/DM74L85 (SN54L85/SN74L85)
4-bit magnitude comparator
general description
The DM54L85/DM74L85 low power TTL 4-bit
magnitude comparator is compatible with most
TTL and DTL families. This comparator compares
two 4-bit words and determines their relative
magnitude with the result being indicated by a
high level at the A>B. AB.
AB and
AB
AB
AB
DunUT
A,
,
2
)
AIJ' ~!iII!l
N... 2AII .... d..... 'N1D64.,equ ....,,1
N01eIC'-' .. I.d .. " ..... ,d,'II • .,... _
N... 4 t....
~
Nott5V . . . . .' ........ >1hrespootI01I"' .....
3-42
J----IBDtN
Note 1 Each mput IS tested sepa,ataly
Note 2: When testmg ROI'I or R9(1111pply 4 5V to ROI2) or 89121'
Note 3' Whentestlllg RO(2)or Rgl2JIPply 45V to Rom or Rg.,)
£achlnputlstllltedsepalitely
When testlng ROil) Dr Rein grOllnd Roi21 or 8'(2)'
Whentestmg Ror2I or Rgl2lground Ro(1l or Rsl,I'
When testing Icc reset all outputs to loglC8l "0",
graundall mputl, then ITlNSUre Icc-
IN
Each output Istesled mthe loytcal "I" state
d
]- ···-l
1-----IBD1N
V
TEST
PER
TRUTH
TABLE
'm'...
Vn'N~3V.Io-I,SI5 ...
]-
Series 54L/74L
DM54L911DM74L91(SN54L911SN74L91) 8-bit shift register
general description
The DM54L91/DM74L91 is a serial-in, serial-out, 8bit shift register which utilizes low-power transistortransistor logic (TTL) circuits. The shift register,
composed of eight R-S master-slave flip-flops,
includes input gating and a clock driver. The register
is capable of storing and transferring data at
typical clock rates of 8 MHz. Power dissipation is
typically 17.5 milliwatts, and full fan-out of 10 is
available from the outputs.
The register will shift information to the output on
the positive transition of the clock.
features
• SN54L/74L Series compatible
• Fully compatible with edge-triggering flip-flops
logic and connection diagrams
Flat Package
NC
NC
NC
Vee
Ne
Dual-tn-Line Package
NC
NC
NC
NC
NC
TOP VIEW
Nt
GNO
CP
NC
Vee
NC
NC
TOP VIEW
dc test circuit
Vee = 5V
OUTPUT
r - - -lOADcmcm - - - ,
I
r-----
PULSE
GENERATOR
(SleNole1)
I
I
I
1 - - -......--1 ;><>-t--ct cp
INPUT A n-.l-n-"
24V~-r-......~
-,
V"
I
1
5V
I
:~"
1
1
1
c,
I
c,
11;'""1;""
':" J1
L _________
r- -
-~o~U;_;
L __
~M~L~C~UI!.2.. _ _
---1
...I
3-43
'I"'"
en
...I
absolute maximum ratings
~
.....
:E
(Note 1)
MIN
Supply Voltage
Q
BOV
"en
Input Voltage
5.5V
'I"'"
Output Voltage
5.5V
...I
Storage Temperature Range
~
Lead Temperature (Soldering, 10 sec)
:E
electrical characteristics
-65°e to 1500 e
300 e
0
Supply Voltage (Vee)
DM54L91
DM74L91
Temperature (T A)
DM54L91
DM74L91
MAX
4.5
4.75
YNITS
5.5
5.25
-55
0
V
V
°e
°e
+125
70
It)
Q
(Note 2)
PAf;tAMETER
MIN
CONDITIONS
Logical "1" Input Voltage
2
Logical "0" Input Voltage
TYP
13
V
13
logical "1" Output Voltage
Vee
Logical "0" Output Voltage
(DM54L91)
Vee'" Min, lOUT'" 2 rnA
Vee Mm, lOUT 36mA (DM74L911
Logical "1" Input Current
Vee'" Max. Other Inputs"
0=
24
Min, lOUT :-200 I1A
av, VIN '"
2 4V
Logical "0" I nput Current
Vee = Max, Other Inputs = 4 5V,
Output Short Circuit Current
Vee'" Max, VOUT '" OV
VIN
=03V
-'l
V
07
28
V
015
02
VIN '" 5 5V
UNITS
MAX
V
V
03
04
<1
10
<10
100
"A
-110
-180
"A
-8
-15
mA
"A
(Note 3)
Supply Current
~Vcc
35
'" Max, VIN = 5V
mA
66
Icc (Max)
f MAX (maximum Input clock frequency)
4
Vcc"'oOV
TA
"
MH,
8
25°C
Propagation Delay to a Logical "0" from
Clock to Output, tpdO
Vcc=50V
T A'" 25°C
65
130
os
Propagation Delay to a Logical "1" from
Clock to Output, tpdl
Vcc=50V
T A '" 25°C
40
80
os
Minimum Width of logical "0" Level
Clock Pulse, tpolClock}
Vcc=50V
TA = 25"C
120
60
ns
MInimum Width of logical "1" Level
Clock Pulse, tpl (clock)
Vcc=50V
TA = 25°C
120
60
ns
Input Setup Time, t$8t\lp
Vcc=50V
TA = 25°C
120
ns
Input Hold Time, t hold
Vcc=50V
TA = 25°C
0
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electncal Charactenstics" provides conditions for actual device operation.
Note 2: Unless otherwise speCifIed min/max limits apply across the -5SoC to +125°C temperature range for the DM54L91,
and across the oOe to 700 e range for the DM74L91. All typicals are g,ven for Vee
= 5.0V and T A = 25°e.
Note 3: Only one output at a tIme should be shorted.
switching time waveforms
3V
CLOCK PULSE
INPUT
CLOCK-PULSEJ"13:""
INPUT
'
11.IT
---JL_aa. __ ._~_--IL ___ ._____
_n .... ____ .. _....JL
2 ~,:!U_f1JUl7
8 9 _th.!.~"JlJUlJ1J1'5
16 17 18 19 ~'!~nruum21
24 25 26 27
CLOCK PULSE
INPUT
INPU1A
OUTPUlo. _ _ _ ....
DU1PU1QORQ
DU1PU100RU
-''''''''=1I----
_~:VO"""
llV
::~:
--
~;~,--l
JT,:"" ~:::::
-./~--VOUTIOI
lYPICALINI'UTIOUTPUTWAVEFORMS
Note 1 The generator has the followmg characteristICs V1N10f .:;; 0 JV, V1N(1)?: 2 4V, t, " to" 15 ns,
\.d(ClOCK!" 500 ns, 1p.,oiClOCK!" 500 ns, PRR "1 MHz, and ZOUT '" 50n
Note2 Cl 1n~ludesprobeandJI"capacltance
Note3 Eachoulllutistesteds8f)IIrately
3-44
OV
I3V
""
_lUI
INPUT
ADRI
INPUl
AORB
"'"
I3V
I3V
J
"
1lV
go<
3V
'"'ov
~.
•
V""lll
1(,3V
VlNlOl
1-tt.0Id101
V' .. 111
1lV
'-.UI- '-----VINIOI
-r-1t.OId111
Note 4 Voltage values are With respect to network ground terminal
Note5 Alidiodesare1NJ064orequI¥81ent
Note 6" 'MAX use 50% duty cycle
o
3:
Series 54L/74L
U'I
~
~
W
"-
o
3:
.....
DM54L93/DM74L93(SN54L93/SN74L93) and
DM76L93/DM86L93 ripple binary counters
~
r-
CD
W
general description
The DM54L93/DM74L93 and DM76L93/DM86L93
ripple binary counters enable a systems designer to
have some flexibility in his design. The DM76L93/
DM86L93 has the same pin out as the standard
SN5493/SN7493, but the same power specifications
as the SN54L93/SN74L93 low-power counter.
Both counters can be used to divide-by-2, 8, or 16.
Two reset inputs are provided to allow for initializing the counters. Resetting occurs asynchronous·
Iy when both reset inputs are high. Darlington
outputs provide for a fanout capability of two
o
3:
.....
0)
standard TTL unit loads over the commercial
temperature range and 10 54L/74L loads in the
low state. In addition these devices can fan out to
20 54L/74L loads in the high state.
r-
CD
W
"-
o
features
3:
• Series 54L/74L compatible
• 15 MHz typical clock frequency
• 18 mW typical power dissipation
CIO
0)
r-
CD
W
logic and connection diagrams
OUTPUTS
OUTPUTS
.-----,
,
,-..........
0
TOP VIEW
Dual-In-Line Package
DM76L93/DM86L93
Dual-In-Line Package
DM54L93/DM74L93
,
INPUT
OUTPUTS
~GND
OUTPUTS
~INPUTB
,
INPUT
Nt
TOPVIEW
Flat Package
Flat Package
DM54L93/DM74L93
DM76L93/DM86L93
3-45
p)
~
absolute maximum ratings (Note 1)
CD
00
=t
Q
......
CW)
+8.0V
Supply Voltage
+5.5V
Input Voltage
+5.5V
Output Voltage
Operating Temperature Range DM54L93,DM76L93 _55°C to +125°C
O°Cto +70°C
DM74L93,DM86L93
-65°C to +150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)
....
G)
CD
r-.
=t
Q
electrical characteristics(Note 2)
p)
~
•=t
PARAMETER
1:'00
MIN
CONDITIONS
TVP
MAX
UNITS
Loglca' ","'nput Voltage
DM54L93, DM76L93
DM74L93, DMS6L93
Vee=45V
Vee 4.75V
......
Logical "0" Input Voltage
DM54L93, DM76L93
DM74L93, DMS6L93
Vee =4 5V
Vee - 4 75V
....
Logical "'" Output Voltage
DM54L93, DM76L93
DM74L93, DMS6L93
Vee=45V
V ee -475V
lOUT = -200pA
aD
Logical "0" Output Voltage
DM54L93. DM 76L93
DM74L93, DMS6L93
Vee=45V
Vee - 4 75V
lOUT'" 2mA
lOUT = 3.6mA
Q
Logical "1" l"putCurrent
DM54L93, DM76L93
DM74L93, DMS6L93
Vee = 5.5V
V ee -525V
V IN '" 2.4V Reset Inputs
VIN = 5.5V Reset Inputs
10
100
/lA
/lA
DM54L93, DM76L93
DM74L93, DMS6L93
Vee= 55V
V cc -525V
VIN = 2.4V AIN &. BIN
V IN = 5.5V AIN &. BIN
20
200
/lA
/lA
DM54L93. DM76L93
DM74L93, DMS6L93
Vee=55V
Vee = 525V
VIN
&. R02
-018
rnA
DM54L93, DM76L93
DM74L93, DMS6L93
Vee = 5.5V
Vee - 5.25V
VIN = O.3V, AIN &. BIN
-036
rnA
DM54L93, DM76L93
DM74L93, DM86L93
Vee = 5.5V
Vee - 5.25V
VOUT=
DM54L93, DM76L93
DM74L93, DM86L93
Vee = 5.5V
Vee = 5.25V
Q
CW)
G)
•=t
Logical "O"'nput Current
Output Short Circuit Current
(Note 3)
'ce max
20
AIN
&.
1.3
12
13
BIN
Reset Inputs
= 0 3V, R01
24
28
0.15
0.20
-3
OV
V
0.6
07
-9
V
V
V
0.3
0.4
-15
5.50
V
V
rnA
rnA
Propagation Delay to a Logical "0" from AIN to
DouT.'fpdo
Vee = 5.0V
TA = 25°C
CL = 50 pF, RL = 4 kO
230
400
ns
Propagation Delay to a Logical "'" from AIN to
Vee = 5.0V
TA = 25°C
Cc = 50 pF,
210
400
ns
MaXimum Clock Frequency
Vee = 50V
TA = 25°C
CL = 50pF. RL = 4k!l
Minimum Clock Pulse Width
Vee = 5.0V
TA = 25°C
CL c 50 pF, RL = 4 kO
DOUT,
tpd1
RL = 4 k!l
6
MHz
15
60
100
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operatong Temperature Range" they are not meant to imply that the devices should be operated at these limIts. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Not.2: Unle .. otherwIse specIfied monlmax limIts apply across the _55°C to +125°e temperature range for the OM54L93,
DM76L93 and acro .. the oOe to 70°C range for the DM74L93,OM86L93. All typlcals are gIven for Vee = 5.0V and
TA=25°e.
Note 3: Only one output at a time should be shorted.
ac test circuit
switching time waveforms
,..-- -------,
T i t ',.4K
L~~I~I__~~+H~
•
) ':~F
~~·"'F
.I
PULSE
GE..ERATOR
(SEE .. OTEI)
.,. .,.
5lJ
~
-r
~""'_-IA.
c
a..o
':'
0
I
I
I
I
~)
'- _ _ _ !;!AD.£!.CI!!ll _ _ _ ..I
- - - LOAomuii"i -_ _
---,
L. _ _ _
_ .J
~"!!sE-
rL. -_ _
- _
- LiiioCiiicliiii -_ _
- - ,
_ .J
~AM~S.!L
r---liiAoCiiicUiT4---'
___
_ _ _ .J
..l.SAM~.!L
3·46
n. ......"_ .........
liliiii1
IMI.. ....,.... VIlEIf~l'I.to=11s:11 ..
1p~111... PflR-I.Ib.Zour .. 1IIl
.... 2 AlilllIII. . . , .. 3I64orlqlMllnt
..... 3 CLIIIII....l1Ib1 ... JlB ....IIIRIB
.... 4tp, .. ~
NiIIII VDllltlVlIIII, .. MdlI8IIII __ .11IIIId1tnll1lllll
parameter measurement information
1
TEST
TEST
PER
PER
V'N
TRUTH
TABlE
TRUTH
TABLE
c
3:
.....
0)
Note1 EachoutflutlStestedmtheloglcal'T'state
Note 1 Each output IS tested m the loglca!"O" state
v"
j
v"
CD
W
.......
d
)~. ... ~
B,"
A,"
'"
r-
j
I"
I"
c
B,"
3:
j...
A,"
00
0)
r-
R,
CD
W
GND
GND
-=-
-=Note 1 Eachmputlstestedseparately
Note 1 Eachmputlstestedseparately
Note2 Whente$llngRol1l groum! ROl21
NoteJ WhentestmgRol2)graund ROlli
Note 2 When testmg Rom apply 4 5V to Ro!21
Note3 Whentestrog RU12,ajlply45V to ROlli
Note4 Whentestlnglcca11mputsandoutputsareopen
HI
1
TEST
PER
Y'N
TRUTH
TABlE
GND
Note 1 Eachoutputlstestedmthelogrcal"l"state
truth table
ISee Notes 1 and 2)
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OUTPUT
C B
A
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
NOTES.
Output A connected to mput B.
To reset all outputs to logical "0" both RoO)
and R o (2)' Inputs must be at a logical "1".
3. Either (or both) reset inputs A o (1) and Ro (2)
must be at a logical "0" to count.
0
1
0
1
0
1
3-47
ClO
en
....
Series 54L/74L
'It
r-.
:E
Q
.......
ClO
'It
OM 54L98/ OM74 L98(SN 54L98/SN74L98)
4-bit data selector/storage register
:E
general description
en
....
It)
Q
The DM54L98/DM74L98 4-bit data selector/storage register is composed of four R-S fl ip flops with
associated gating arranged to allow entry of data
from one of two four-bit words_ When the Word
Select input is at the logical "0" level. word 1 is
presented to the flip flop inputs_ Conversely a
logical "1" level allows word 2 to be selected_ The
selected word is entered into the flip flops during
the negative-going transition of the clock_
features
• 30 mW typical power dissipation
• 12 MHz typical clock frequency
• Fan-out to two standard 74 Series loads
block diagram
AI
WO"
SlLECT
~::t;::;;::::;:[)
"o---+H-.J
connection diagrams
Dual-In-Una Package
Rat Package
Vee
~="'--~,
a... Oa Oc
L"
WORD
ClOCKSELECT
.
.
~
, , ,
3-48
Go
" " " "
~
,1102
01
1101
...,r
c
s:U'1
absolute maximum ratings
~
r-
CD
8.0V
5.5V
5.5V
-55°C to +125°C
O°C to+70°C
-65°C to +150°C
300°C
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM54L98
DM74L98
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
CO
.......
C
s:.....
~
r-
CD
CO
electrica I characteristics
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
Logical "1" Input Voltage
DM54L98
DM74L98
Vee = 4.5V
Vee ~ 4.75V
Logical "0" Input Voltage
DM54L98
DM74L98
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Voltage
DM54L98
DM74L98
Vee = 4.5V
Vee = 4.75V
lOUT = ~200 /lA,
All Data Inputs = 2V
Logical "0" Output Voltage
DM54L98
DM74L98
Vee = 4.5V
Vee 4.75V
lOUT'" 2 rnA, All Data Inputs = 0 7V
Logical"l" Input Current
DM54L98
DM74L98
Vee = 5.5V
Vee = 5.25V
Y'N = 2.4V
Input
10
IlA
DM54L98
DM74L98
Vee = 5.5V
Vee - 5.25V
Y'N = 5.5V
Y'N = 5.5V, Any Input
100
IlA
Logical "0" Input Current
DM54L98
DM74L98
Vee = 5.5V
Vee - 5.25V
Y'N = 0.3V
V IN = O_3V, Any Input
Output Short Circuit Current (Note 3)
DM54L98
DM74L98
Vee = 5.5V
Vee - 5.25V
VOUT= OV
Supply Current Icc Max.
DM54L98
DM74L98
Vee ~ 5.5V
Vee - 5.25V
2.0
1.3
lOUT
VIN
= 3.6
2.4
Data Inputs = 2V
0.7
0.15
0.3
04
-0 18
-3
-9
6.0
V
V
2.8
rnA
= 2.4V, Any
V
1.3
-15
8.0
V
V
rnA
rnA
rnA
Propagation Delay to a Logical "0"
from Clock to Any Out, tpdO
Vee~ 5.0V
T" = 25°C
65
100
ns
Propagation Delay to a Logical "1"
Vee~ 5.0V
T" = 25°C
40
80
ns
from Clock to Any Out, tpd1
MaXimum Clock Frequency
Vee = 5.0V
TA = 25°C
6
12
MHz
Minimum Pulse Width on Clock
Vee = 5.0V
T" = 25°C
100
65
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditIOns
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the'DM54L98 and across the oOe to 700 e range for the DM74L98. All tYPleals are given for
Vce ~ 5.0V and T A ~ 25°C.
Note 3: Only one output at a time should be shorted.
3·49
D
Series 54L/74L
DM54L154A/DM74L154A(SN54L154A/SN74L154A)
low power 4-line to 16-line decoder/demultiplexer
general description
while the other control input must be maintained
in the logical "0" state. The information will then
be transmitted to the selected output, as determined by the 4-1 ine input address.
The DM54L 154A/DM74L 154A is a one of sixteen
decoder utilizing a true Senes 54L/74L technology providing a full factor-of-ten power saving
over conventional Series 54/74. The device is
provided with two control inputs, both of which
must be in the logical "0" state for normal operation. If either control input is in the logical "1"
state, all 16 outputs will go to the logical "1" state.
features
• 20 mW typical power dissipation
• 55 ns typical propagation delay
• Pin compatible with SN54154/SN74154
To use the product as a demultiplexer, one of the
control inputs serves as the data input terminal,
connection diagram
truth table
Dual-I n-Lin~ Package
INPUTS
CONTROL
----OUTPUTS
"
11
TOP VIEW
INPUTS
OUTPUTS
Gl
G2
0
C
B
A
0
1
2
3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H = high, L
ac test circuit
~
H
X
X
X
low, X
~
H
•
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
•
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
7
8
9
10
11
12
13
I.
15
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
don't care
switching time waveforms
'm, I--
'''" f---
Ir""
~
ODD NUMBERED
tlll
13V
OUTPUTS
------IIOl
NOTE 1 Thetruth table generator and the pulse generator have tile followmg charact&rI&tlcl PRR 1 MHz,
lOUT"" 500., t",= lOOns
NOTE 2 Cllncludesprobeandjlgc.apacltmce
NOTE 3 When mellSUnng select Input-to output times the 51robe Inputs are grounded When measuring
sttobll-Input-toollf!lut tlmlS, the unte5ted strobe IOplll IS grounded Select mputs determine
output undll test through truth tlIble genlrato(
NOTE 4 All dlodl!$ are 1N3064 01 equlvillent
3-50
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM54L 154A
DM74L154A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
+8V
+5.5V
+5.5V
_55°C to +125°e
oOe to +70o e
-65°C to +150o e
300°C
electrica I characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
OM54L 154
DM74L 154
Vee=45V
Vee - 4.75V
Logical "0" Input Voltage
DM54L154
DM74L 154
Vee = 4.5V
Vee - 4.75V
Logical "'" Output Voltage
DM54L 154
DM74L154
Vee=45V
V ee -475V
lOUT = -200)lA
Logical "0" Output Voltage
DM54L 154
DM74L 154
Vee = 4.5V
V ee -475V
lOUT"" 2 rnA
lOUT - 3.6 rnA
LogIcal "1" Input Current
DM54L154
DM74L154
Vee=55V
Vee - 525V
Y'N = 2.4V
10
)lA
DM54L154
DM74L 154
Vee = 5.5V
V ee -525V
Y'N = 5.5V
100
)lA
logical "0" Input Current
DM54L 154
DM74L 154
Vee=55V
Vee 525V
Y'N = 0.3V
Output Short CircUit Current
(Note 31
DM54L 154
DM74L154
Vee = 5.5V
Vee - 5.25V
VOUT
lee
DM54L 154
DM74L 154
Vee = 5.5V
V ec =525V
20
V
0.7
::::
OV
2.4
-0.11
-3
V
28
0.15
020
-9
4.8
V
030
0.40
-018
-15
6.0
V
V
rnA
rnA
Propagation Delay to a Logical "0"
from any I nput to any Output, tpdO
Vee=50V
T A =25°C
CL =50pF.
RL = 4 H~
75
150
ns
Propagation Delay to a Logical "0"
Vee = 5.0V
TA = 25°C
CL =50pF.
RL = 4 kn
55
110
ns
from any Input to any Output, tpd1
Vee=50V
TA = 25°C
C L =50pF.
RL = 4 kn
35
70
ns
Propagation Delay to a Logical "1"
from G 1 or G2 to any Output, tpd1
Vee = 5.0V
TA = 25°C
CL = 50pF.
RL = 4 kn
35
70
ns
from G 1 or G2 to any Output,
tpdO
Propagation Delay to a Loglca''',''
0
rnA
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electrical Charactenstlcs" provides conditions
for actual deVice operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM54L154 and across the O°C to 70°C range for the DM74L154 All tYPlcals are given
for Vec = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
3-51
Series 54L/74L
DM54L165A/DM74L165A (SN54L165A/SN74L165A)
low power parallel-in serial-out 8-bit shift register
general description
The DM54L 165A/DM74L 165A utilizes Series 54L/
74L compatible low-power TTL circuitry to provide
an 8 bit parallel-in serial-out shift register. The
device features internal gating for clock inhibit,
parallel load control, and both Q & Q outputs
are available from the last flip flop for added
flexibility.
Clocking occurs on the positive-going transition
of the clock. Data Dl thru DB will be entered on
the negative-going transition of the load input.
features
The clock inhibit must be a logical "0" for
clocking to occur. A "1" on the clock inhibit line
disables the clock. The function of these two
inputs is completely interchangeable and they may
be switched to facilitate die layout.
•
Series 54L/74L compatible - true
1/10 -power technology
•
Pin compatible with DM7590/DM8590
and SN54165/SN74165
• Typical power dissipation
• Typical shift frequency
30mW
14 MHz
logic diagram
SERIAL
INPUT
CLOCK
INHIBIT
connection diagram
truth table
Dual-In-Line and Flat Package
r
\I
CLOCK
INHIBIT
SERIAL
04
03
02.
01
tNPUT
Q
" " " " " " '"
~
, , ,
}
•
. . , I'
-
3-52
,
SERIAL
IN
DATA IN
ClK
ClK INH
lOAD
FUNCTION
X
X
1
0
1
0
X
X
X
X
X
X
X
X
1
0
X
1
1
X
0
0
CP
CP
X
X
1
1
1
1
1
1
0
0
Do Nothing
00 Nothing
Shift "1"5
Shift "O"s
Shift "1"5
Shift "O"s
Load "1" Asynchronously
Load "0" Asynchronously
CP
CP
0
0
X
X
absolute maximum ratings
Operating Temperature Range
DM54L165A
DM74L165A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 1)
+8.0V
+5.5V
+5.5V
-55'C to +125'C
O'C to +70'C
-65'C to +150'C
300'C
Supply Voltage
Input Voltage
Output Voltage
(Note 1)
CONDITIONS
PARAMETER
Logical "1" Input Voltage
DM54L 165A
DM74L165A
Vee = 4.5V
Vee - 4.75V
Logical "0" Input Voltage
DM54L165A
DM74L165A
Vee = 4.5V
Vee = 4.75V
Logical "1" Output Voltage
DM54L165A
DM74L165A
Vee = 4.5V
Vee = 4.75V
lOUT = -200 JlA
Logical "0" Output Voltage
DM54L165A
DM74L 165A
Vee=45V
Vee - 4.75V
lOUT = 2 mA
lOUT = 3.6 mA
Logical "1" Input Current
DM54L165A
DM74L165A
Vee = 5.5V
Vee = 5.25V
Y'N = 2.4V
Y'N = 5.5V
Logical "0" Input Current
DM54L165A
DM74L165A
Vee = 5.5V
Vee = 5.25V
Y'N = 0.3V
Output Short CirCUit Current DM54L 165A
(Note 3)
DM74L165A
Vee = 5.5V
Vee - 5.25V
V OUT = OV
Supply Current
Vee = 5.5V
Vee = 5.25V
DM54Ll65A
DM74L165A
Icc max
MIN
TYP
2.0
1.3
1.3
2.4
MAX
V
0.7
2.8
0.15
0.20
-9
V
V
0.3
0.4
10
100
-3
UNITS
V
V
I1A
JlA
-0.18
mA
15
mA
9.5
mA
Propagation Delay to a Logical "0" from
Clock or Clock Inhibit to Q or 0, tpdO
Vee = 5.0V
TA = 25'C
R L = 4 kr2, CL = 50 pF
50
100
ns
Propagation Delay to a Logical "0" from
Vee=50V
TA = 25'C
RL = 4 kr2, CL = 50 pF
62
124
ns
Vee = 5.0V
TA = 25'C
RL = 4 kr2, CL = 50 pF
35
70
ns
Vee = 5.0V
TA = 25'C
RL = 4 kr2, CL = 50 pF
44
88
ns
Vee = 5.0V
TA = 25'C
RL = 4 kr2, CL = 50 pF
Vee= 5.0V
TA = 25'C
RL = 4 kr2, C L = 50 pF
Input Data (Load)
Vee = 5.0V
TA = 25°C
RL = 4 kr2, CL = 50 pF
t HOLD Minimum Hold Time for
Parallel Input Data (Load)
Vee = 5.0V.
T A =25'C
tsETUP (Clock) Minimum Setup
Time for Senal Data
Load to Q or
5, tpdO
Propagation Delay to a Logical "1" from
Clock or Clock Inhibit to Q or 0, tpd1
Propagation Delay to a Logical "1" from
Load to Q or 0, tpd1
Maximum Clock Frequency
6
14
MHz
100
100
ns
ns
22
44
ns
RL = 4 kQ, C L = 50 pF
0
0
ns
Vee = 5.0V
TA = 25'C
RL = 4 kr2, C L = 50 pF
22
44
ns
t HOLD (Clock) Minimum Hold
Time for Serial Data
Vee:: 5.0V
T A = 25'C
RL = 4 kr2, C L = 50 pF
0
0
ns
Propagation Delay to Logical "1" from
Vee = 5.0V
TA = 25'C
RL = 4 kr2, CL = 50 pF
56
112
ns
Vee = 5.0V
TA = 25'C
R L = 4 kr2, CL = 50 pF
33
66
ns
Minimum Clock Pulse Width
Minimum Load Pulse Width
tSETUP
Data
In
Minimum Setup Time for
to
Q
or
5, tpd1
Propagation Delay to Logical "0" from
Data in to Q or
Q,
tpdO
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operatlng Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherWise specified minImax limits apply across the _55°C to +125°C temperature range for the DM54L 165A
and across the O'C to 70'C range for the DM74L165A. All tYPleals are given for VCC = 5.0V and TA = 25'C.
Note 3: Only one output at a time should be shorted.
3-53
parameter measurement information
ICC
."
~~~~CtOCK
~
CLINH
LOAD
TRUTH
!
TABLE
VOH
ClOCK
CLINH
m
m
TRUTH
TABLE
TRUnt
TABLE
switching time waveforms
D.~""
lr
LOAD
k
0,
~
lOAD
~
v.::--
"'''''''''1
~
13V~'JV
13V
t Pd 1llo8dl-J
lr
Q~
SERlAL'NPUT~
=...\
'3V~
irt,eIIlP(Cl<>Ckl
13VVlnnnnnn
CLOCK----.J
~
UUUUUUlJI'~·Ir
-..j
t p d1(clockl
_ _----IF
3-54
SER'AlINPUT~I--",,,I,,",,,
lJvYlnnnnnn
~
ClD"-.J UUUUUU~ ~::i
Q
~
Series 54L/74L
DM54L187A/DM74L187A(SN54L187A1SN74L187A)
low power 1024-bit read only memory
general description
The DM54L 187A/DM74L187A is a customprogrammed Read Only Memory organized as
256 4-bit words. Selection of the proper word is
accomplished through the eight select inputs.
The "A" suffix is used to denote that full "tenthpower" technology has been employed in building
this ROM.
Two overriding memory enable inputs are provided
which when mask·programmed in one of the three
options described will cause all four outputs to
read either the normal memory contents or go to
the logical "1" state.
features
•
•
•
•
•
•
Full tenth-power technology
Pin compatible with SN54187/SN74187
Typical power dissipation
90 mW
Typical access time
85 ns
Custom-programmed memory enable inputs
Open-collector outputs
logic diagram
1024-BITMEMDRV CELL
3"32
MEMORY MATRIX
.,
..
A,
111
'I)
(5)
~ME'
MEMORV
(13)
ENABLE ME z
(14)
OPTION 1
Y,
PmCtI)=Vcc ".(1)=810
Y,
OUTPUTS
ME,~
.E2~
OPTION 2
ME,~
ME2~
OPTION 3
3·55
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
~5°C
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
(Note 1)
7.0V
5.5V
5.5V
to +150°C
300°C
operating conditions
Supply Voltage (VCC)
DM54L 187
DM74L187
Temperature (TA)
DM54L 187
DM74L187
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
o
+125
+70
°c
°c
TYP
MAX
UNITS
(Note 2)
CONDITIONS
PARAMETER
Logical "1" Input Voltage
Vcc : Mm
Logical "0" Input Voltage
Vee
Logical "I" Output Current
MIN
V
2.0
=Min
0.7
V
Vcc : Max, Va: 5.5V
(Memory Enable: Logical 1)
50
JJ.A
Vce : Min, 10 : 2.0 mA
Vcc : Mm, 10 : 3.2 mA
0.3
0.4
Logical "1" Input Current
Vec : Max, V,N : 2.4V
Vce : Max, V,N :5.5V
10
100
Logical "0" Output Voltage
DM54L187
DM74L187
V
V
JJ.A
JJ.A
-120
-180
JJ.A
18
25
mA
Logical"Q" Input Current
Vee: Max, V,N : 0.3V
Supply Current (Each Device)
Vec : Max, All Inputs at GND
Input Clamp Voltage
Vec: Mm,I'N : -12 mA
-1.5
V
Propagation Delay to a Logical "0"
Vcc ': 5.0V, CL : 15 pF,
TA : 25°C, RL : 2.0 kn
46
70
ns
Vec: 5.0V,C L : 15 pF.
TA : 25°C. RL : 2.0 kn
65
98
ns
From Address to Output (tpdO)
Propagation Delay to a Logical "1"
From Enable to Output (tpd1)
Vcc :5.0V.C L : 15 pF.
TA : 25°C, RL : 2.0 kn
85
130
ns
Propagation Delay to a Logical "1"
From Address to Output (tpd1)
Vec :5.0V,C L : 15pF.
T A : 25°C. RL : 2.0 kn
120
180
ns
From Enable to Output (tpdO)
Propagation Delay to a Logical "0"
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits.
Note 2: Unless otherwise specified mm/max limits apply across the --55°C to +125°C temperature range for the DM54L 187
and across the ODe to +70°C range for the DM74L187. All typlcals are given for Vee = 5.0V and TA = 25°C.
ordering instructions
Programming instructions for the DM54L187 or
DM74L 187 are solicited in the form of a sequenced
deck of 32 standard 80·column data cards pro·
viding the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a com·
puter run will be made from the deck of cards
which will produce a I;omplete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer·lllltomated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.
3·56
Each card in the data deck prepared by the pur·
chaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.
supplementary ordering data
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.
data card format
Column
1- 3
4
5- 7
8- 9
10-13
14
15-18
19
20-23
24
25-28
29
30-33
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
34
35-38
Punch a "-" (Minus sign)
Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.
39
40-43
44
Blank
45-48
Punch "H", "L", or "X" for bits four,
three, two, arid one (outputs Y 4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H = highlevel output, L = low-level output, X =
output irrelevant.
50-51
Blank
53-55
Punch "H", "L", or "X" for the second
set of outputs.
49
52
56
57-58
Blank
Punch "H", "L", or "X" for the third set
of outputs.
59
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month_
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Blank
Blank
60-61
Punch "DM"
Punch "H", "L", or "X" for the fourth set
of outputs.
62-67
Punch the National Semiconductor part
number 54L 187 or 74L 187
Blank
68-70
Blank
truth table
connection diagram
Dual-in-Line and Flat Package
MEMORY
ENABLE
l.
BINARY
sELi:r H
"
OUTPUTS
,.---.....-.
'I~'
14
MI'IJ:
,
I'" l'" I'
10
I I I I I I
OPTION
Y,
•
,
2
r-
I I I I I I
BINARY SELECT
3
OUTPUTS
ME,
ME2
0
0
Normal
1
X
Logical 1
X
1
Logical 1
1
1
Normal
0
X
Logical 1
X
0
Logical 1
1
0
Normal
X
1
Logical 1
0
X
Logical 1
X = Don't care
TOP VIEW
3-57
M
...
en
Series 54L/74L
....I
~
"'Q~"
.......
DM54L192/DM74L192{SN54L192/SN74L192)
M
...
up-down decade counter
~
DM54L193/DM74L193(SN54L193/SN74L193)
en
....I
an
up-down binary counter
~
Q
general description
N
...en
The counters can drive two standard TTL loads
over the commercial temperature range and 10
and 20 low power TTL loads in the "0" and "1"
states respectively over the military temperature
range.
The DM54L192/DM74L192 and DM54L 193/
DM74L 193 are up-down decade and up-down
binary counters respectively. Separate clock inputs
determine up or down counting. The u nu sed
clock input must be tied high when not in use.
....I
~
"'Q~"
Asynchronous clear and load inputs with clear
override provide for parallel data entry. Clear
overrides the load as far as asynchronous data
entry is concerned. Carry and borrow outpu ts are
controlled synchronously. Normal synchronous
operation requires clear = "0" and load = 1.
.......
N
...
en
....I
~
an
features
•
Series 54Li74L compatible
•
40 mW tYPical power dissipation
•
50 ns typical propagation delay
~
Q
connection diagram
Dual"1 n·Line and Flat Package
T1,6
DATA
A
CLEAR BORROW CARRY LOAO
15
14
13
11
11
-
DATA
B
DATA
0
10
-
IIa
Q.
COUNT COUNT
DOWN
UP
TOP VIEW
3-58
DATA
C
lie
c
Series 54/74
~
C;J
...
W
"'-
DM78311DM8831,DM7832/DM8832 TRI-STATE
®
C
~
line drivers
CO
CO
W
general description
Through simple logic control, the DM7831/
DM8831, DM7832/DM8832 can be used as either
a quad single-ended line driver or a dual differential
line driver. They are specifically designed for
party line (bus-organized) systems_ The DM7832/
DM8832 does not have the Vee clamp diodes
found on the DM7831/DM8831_
• High Impedance output state which allows
many outputs to be connected to a common
bus line.
mode of operation
To operate as a quad single-ended line driver apply
logical "O"s to the Output Disable pins (to keep
the outputs in the normal low impedance mode)
and apply logical "O'''s to both Differential/
Single-ended Mode Control inputs_ All four
channels will then operate independently and no
signal inversion will occur between inputs and
outputs.
The DM7831 & DM7832 are specified for operation over the -55°C to +125°C military temperature range. The DM8831 & DM8832 are specified
for operation over the O°C to +70°C temperature
range.
To operate as a dual differential line driver apply
logical "O"s to the Output Disable pins and apply
at least one logical "1" to the Differential/Singleended Mode Control inputs. The inputs to the A
channels should be connected together and the
inputs to the 8 channels should be connected toIn this mode the signals applied to the resulting
inputs will pass non-inverted on the A2 and 8 2 outputs and inverted on the Al and 8 1 outputs.
features
• Series 54/74 compatible
• 17 ns propagation delay
• Very
low output impedance-high drive
capability
• 40 mA sink and source currents
• Gating control to allow either single-ended or
differential operation
When operating in a bus-organized system with
outputs tied directly to outputs of other
(Continued)
connection and logic diagram
Dual-In-Line and Flat Package
"A" OUTPUT
eNABLE
OUTPUT
82
".' OUTPUT
ENABLE
OUTPUT
A2
INPUT
II,
INPUT
Az
OUTPUT
A,
DIFfERENTlAl/
INPUT SINGLE ENDED
A,
MODE CONTROL
OUTPUT INPUT DIFfERENTIAll GNU
8, '1. 8,
SINGLE ENDED
MODE CONTROL
TOP VIEW
truth-table
(Shown for A Channels Only)
"A" OUTPUT DISABLE
DIFFERENTIAL!
SINGLE·ENDED
MODE CONTROL
INPUT At
OUTPUT A,
INPUT A2
OUTPUT A2
0
0
0
0
Logical "1" or
LogIcal "0"
Same as
Input A,
Logical "1" or
Logical "0"
Same as
0
0
X
1
1
X
Logical" 1" or
Logical "0"
OpPosite of
Input A,
logIcal "1" or
Same as
LogIcal "0"
Input A2
1
X
X
1
X
High
Impedance
X
X
state
Input A2
High
X
Impedance
state
x - Don t Care
1-241
...
c
~
.....
CO
W
N
"'C
~
CO
CO
W
N
D
N
M
co
co
absolute maximum ratings
~
c
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Operating Temperature Range
......
N
M
co
....
7V
55V
55V
-6SoC to +150 oC
-5SoC to +125°C
aOc to +70°C
DM7831, DM7832
DM8831, DM8832
Lead Temperature (Soldering, 10 sec)
Time that 2 bus-connected devices may be In
Opposite low Impedance states simultaneously
~
C
electrical characteristics
300"e
~
(Note 11
PARAMETER
CONDITIONS
MIN
Logical "1" Input Voltage
DM 7831 ,DM7832 Vee"45V
DM8831,DM8832 Vee 475V
Logical "0" I nput Voltage
DM7831,DM7832 Vee "45V
DM8831,DM8832 Vee - 4.75V
Logical "1" Output Voltage
DM7831,DM7832
DM8831,DM8832
Logical "0" Output Voltage
DM7831,DM7832
DM8831,DM8832
Logical "1" Input Current
DM7831,DM7832 Vee" 5.5V Y'N " 5 5V
DM8831,DM8832 V ee -525V Y'N -24V
Logical "0" Input Current
DM7831,DM7832 Vee = 5,5V
Y,N = 04V
DM8831,DM8832 Vee -525V
Output Disable Current
DM7831,DM7832 Vee = 5.5V
Vo "2.4V or 0 4V
DM8831,DM8832 Vee 525V
-40 mA
-2 mA
-40mA
-5,2 mA
1.8
24
18
2.4
029
0.29
-10
-40
DM7831 ,DM 7832 Vee" 5.5V
DM8831,DM8832 Vee 5.25V
-100
65
Vee = 5.0V, TA =25°C
liN =-12mA
Input Diode Clamp Voltage
V
V
V
V
V
23
27
2.5
2.9
10 "40mA
10" 32 mA
10 40mA
10" 32 mA
-40
(Note 21
UNITS
V
08
DM7831,DM7832 Vee=55V
Output Short Circuit Current
DM8831,DM8832 Vee 5.25V
Supply Current
MAX
2,0
10"
10"
10
Vee"475V
10"
Vee" 4 5V
TYP
0.50
040
0,50
0.40
V
V
V
V
1
40
mA
IJ.A
-1.6
mA
40
IJ.A
120
(Note 21
mA
90
~A
-15
V
-15
V
V ee +l 5
V
---
Output Diode Clamp Voltage
DM7831, DM7832 lOUT
DM8831, DM8832
DM7831,DM8831 lOUT
=
-12 mANce = 5 OV, TA '" 2SoC
+12 mA,Vee
~
S.OV, TA
25 e
Propagation Delay to a Logical "0"
from Inputs A 1 , A 2 , 8 1 ,8 2 Dlfferen·
tlal Single·ended Mode Control to
Outputs, tpdO
Vee=50V,
TA " 25°e
13
25
ns
Propagation Delay to a Logical "1"
from Inputs A" A 2 , 8 1 ,8 2 Dlfferentlal Smgle-ended Mode Control to
Outputs, tpd 1
Vee = 5.0V,
TA " 25°e
13
25
ns
Delay from Disable Inputs to High
Impedance State (from Logical "1"
Leven, t1 H
Vee" 5.0V,
T A =25c C
6
12
ns
Delay from Disable Inputs to High
Impedance State (from Logical "0"
Level), tOH
Vee "50V, TA " 25°e
14
22
ns
Propagation Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State). tH 1
V.cc =50V,
TA = 25°e
14
22
ns
Propagation Delay from Disable Inputs
to Logical "0" Level (from High
Impedance State), tHO
Vee =50V,
T A " 25°e
18
27
ns
Note 1: Unless otherwise specified minImax limits apply across the -5S c C to +12SoC tempt!rature
range for the DM7831, DM7832 and across the O°C to 700 e temperature range for the DM8831,
DM8832. All tYPleals are given for Vee = S.OV and T A = 2S"e
Note 2: Applies for TA "" 125°C only Only one output should be shorted at a time
1-242
c
absolute maximum ratings (Note
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
operating conditions
1)
Supply Voltage (Veel
DM54L192. DM54L193
DM74L 192. DM74L 193
Temperature (TAl
DM54L 192. DM54L 193
DM74L 192. DM74L 193
B.OV
5.5V
5.5V
_65°e to +150oe
3000 e
electrical characteristics
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°e
CONDITIONS
Vee'" Min
Logical "0" Input Voltage
Vee"" Mm
Logical "1" Output Voltage
DM54L192.DM54L193
DM74L192,DM74L193
Logical "1" Input Current
MIN
TYP
2.0
1.3
13
Vee'" Mm
lOUT"" -200 llA
Vcc"'45V
V cc -475V
lOUT = 2 mA
2.4
IOUT= 3.6 mA
Vee'" Max,
VIN '" 2.4V
<1
C
s::
Vee = Max,
VIN '" 5.5V
<1
-010
Vee'" Max,
V OUT =
DM54L 192IDM74L 192
DM54L 193IDM74L 193
-3
OV
-9
8.0
75
Vee:: Max
Vee Max
0.7
10
U1
.1:10
...r-
MA
100
-0.18
-15
13
12.S
C
s::
'-I
.1:10
mA
...r-
mA
mA
Vee'" 5.0V
TA = 25°C
RL = 4 kll, CL " 50 pF
60
120
ns
Propagation Delay to a Logical "'" from
Either Count Input to Output, tpd1
Vcc=50V
T A '" 25°C
RL = 4 kll, CL = SOpF
4S
gO
ns
Propagation Delay to a LogIcal "1" from
Count Up to Carry, tpd1
Vee = 5.0V
TA = 25°C
RL = 4 kll, CL " 50 pF
30
60
ns
MaXImum Clock Frequency
Vcc=50V
TA = 25°C
RL = 4 kll, CL = SO pF
PropagatIon Delay to Logical "1" from
Cou nt Down to Borrow, tpd 1
Vee = 5.0V
TA = 2SoC
RL
PropagatIon Delay to Logical "0" from
Cou nt Down to Borrow, tpdD
Vee=50V
CD
W
MHz
12
= 50pF
30
60
ns
RL = 4 kll, CL = SO pF
SO
100
ns
RL = 4 kll. CL = SO pF
S
30
ns
RL = 4 kll, CL = SO pF
3S
70
ns
=- 4 kn. CL
......
mA
PropagatIon Delay to a LogIcal "0" from
Count Up to Carry, tpdO
6
W
MA
ns
Vcc = 5.0V
TA = 25°C
s::
V
V
lS0
TA = 2SoC
c
V
0.3
04
7S
Vcc=50V
CD
N
V
RL = 4 kll. CL = SO pF
TA = 25°C
...r-
V
Vcc=50V
T A = 2SoC
Minimum Clock Pulse Width
......
UNITS
Propagation Delay to a Logical "0" from
Either Count Input to Output, tpdO
tSETUP - Minimum Input Setup
CD
N
CD
VIN '" O.3V
Output Short Circuit Current
(Note 3)
MAX
28
0.15
020
Vee'" Max,
Logical "0" Input Current
.1:10
...r'-I
.1:10
PARAMETER
Supply Current Icc Max
MAX
(Note 2)
Logical "1" Input Voltage
Logical "0" Output Voltage
MIN
s::
U1
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operatlng Temperature Range" they are not meant to Imply that the
deVices should be operated at these limIts The table of "Electrical Charactenstlcs" provides conditions
for actual deVice operation.
Note 2: Unless otherWise specified minimax limits apply across the -5SoC to +12SoC temperature
range for the DM54L192, DM54L193 and across the oOe to 700 e range for the DM74L192,
DM74L193 All typical, are given for Vee = 5.0V and TA " 25°e.
Note 3: Only one output at a time should be shorted
3-59
logic diagrams
DM54L 192/DM74L 192
•unUT
ORROW
0
CARRY
OUTPUT
N
...
0')
DATA
...I
INPUT A
-.::t
.....
~
l
DOWN
COUNT
:Ii!
T
Q
Q'rr--o
a,
......
UP
N
COUNT
...
0')
D
...I
gj
-.::t
It)
DATA
INPUT
:Ii!
•
Q
l ~
~
~
T-
o,t---<
OUTPUT I1g
T
0.1-
n ~
OAT A
INPUT C
.~
t:> ~r1~
OUTPUT Dc
n
OAT A
INPUT 0
CLEAR
~
W
LOA D
3-60
l
Ool----=-J
logic diagrams (cont.)
DM54L 193/DM74L 193
BORROW
OUTPUT
c
CARRY
s:
OUTPUT
U'I
DATA
INPUT A
r---'
~
Jrr
DOWN
COUNT
....
CD
r-
0, ........ 0-0 OUTPUT~
Co.)
T
UP
COUNT
~
DATA
INPUTB
.......
ff
C
s:
~
"""
....
CD
r-
r---r
6=):>
!~~
Co.)
.,1---< 0-0 DUlPUTGa
T
::n.:
DATA
INPUTe
l
~
~
T
., ........ >--0 OUTPUTGc
.,t-
CLEAR
~
:!J
DATA
INfUlD
CLEAR
~
l
.0_>--0 OUTPUTDD
T
..........
LOAD
00
~
3-61
dc test circuits
v"
V"~TEST
."~..
UP
DOWN
PER
BORROW
CARRY
0,
0,
0,
TRUTH
TABLE
V"
V"
N
.......
DOWN
PER
TRUTH
TABLE
en
UP
CLEAR
CLEAR
LOAD
LOAD
Eaeh output IS tested separately
Do
EacltOlltputlstl:!'ltedseparatety
~
":E
Q
.......
N
.......
en
~
It)
45V
:E
v"
V"
Q
CARRY
0,
...
lie
Do
}~.
NotR1 EachmputlStestedseparately
Note 2 Apply V, to mput under test and ground other mputs eKeept
when testing data mput$, apply 4 5V to clear and IQad mputs
UP
-
DOWN
}"..
V,
0,
...
0,
CLEAR
Do
Note 1 Elch mput Iii tested separately.
Note 2 Apply VI to Input under test and !!found other mput$.
V"
roo
45V
UP
45V
UP
DOWN
DOWN
BORROW
CARRY
0,
0,
0,
CLEAR
0,
0,
}."
LOAD
"::"
"::"
Each output IS tested separ8tely m the h'gh level stete
lOS
ICC
... Arrows indicate actual direction of current flow. Current Into a terminal is a positive value.
3-62
o
3:
switching time waveforms
C1'I
~
...r-
CD
N
1 Clearoutllutstozero
2 load (preset to BCD seven
3 CountuptoBlght,nme,carrV,zero,oneandtwo
4 Counldowntoone,zero,borrow,nme,Blght,andseven
.......
o
3:
ClEAR---1lf-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
,
,
LOAD:
I
......
~
U
...
r-
L================
c...1
: :f.===========:'=====
-+'-!--l-'~C== === =====:. ==:. ==
'...1 ::
,
:
CD
N
_______________ _
~-----------------
~I
"
I~
o
"
3:
I
I,
cou~~-_+,-',-_+-:,--Lf1..flll..nj--;------------
I
I,
C1'I
~
...r-
--------'--,
cg~~~--:--'--:--;--'-,
,
CD
W
I
.......
o
3:
,
,
,
I
!
I
10
1'1
CARRY
SEQUENCE
......
~
r-
...
u
i.,
0
,
CD
W
_'I
r---COUNTUP~
DM54L 192/DM74L 192
lItustratedbeiowIs1l!IIfniiowIDgsequence
1 ClearoutpulstolefO
Z LOMI(preset)toBCDthlrteen
3 Coulltuplofourteen,frlteen,carry, zero, one,lIodtwo
4 Count down to one, zero, burrow,flfieen, fourteen, and thirteen
CLfAA---1l
,
u
,
....1
,
IC================
=== === === =======
'...1
_ _:_--:---;-.:-!i----- - -- -- -- -- --- -c...1....-:--+----:--1:~---------------
-- -- - -- - -- - - - -0...1r-i---'---:-,;-,
~----------------
COU~!--+-'--,......,--Lf1..flll..nj--;-i-----------
COUNT~_:_-'--'---'-',
---------,-,
DOWN
OUTPUTS!
I
G'~_"
I
G,: lLJi-'----'------,L-__
-:---'-__---'
I,
I
~:lLJr+---'---.
I, "
I" I
r-----~
u
I
,
BOIIROW--''''''''''--'C---;'---;-'----------7,--:,----,U
I
SEQUENCE
10 1 Inl I 14 I~OUNT~P 1 _21 1_ I :OUNT~~WN--~~I
IllUSTRATeD
rctEAR ~
~
~
r-
r--
DM54L 193/DM74L 193
3-63
switching characteristics
OUTPUTS
I
Q"Q c
D. OA ACARRYBORR(lWI
CLEAR
'--loAnciiicrnTr--'
LOAD
_~~!.fU.O~~~T.!.!._J
r---loAiiciiiciiiTr--'
_(~M!..A!,!;0!!l.£!!l£!!!T..!l, _ J
L....---i'=;:MI~TI;c;~;=J
L-----ir-=;I~~C;~,;=J
N
...
0')
L....-----;r=~MI~~;c;~;=J
..J
~
,....
Note 1 Tile pulse generaton haYe the followmg ~har~~terl$tICs ZOUT "" son, for the data pulse geneflltol,
pnR'" 500kHz, duty ~elB '" 50%;101 the load pulse generator, PRn = 1 MHz, duty cvcle = 50%
Note2. Cllncludesprobeand,'gCllpacltance
::?i
Note 3 All diodes 1111 lN3064, or equlVllent
Test Circuit 1
Q
.......
N
OUTPUTS
...
~
0')
..J
r-,;,':".;-------,
~
Joh:
~~tt~I~~~~~
:
: T Cts;.!D!21'So.Nottll _ :
In
I
::?i
Q
I ~
- I
L __ ~A!CI~l!!!~ __ .J
--TiiADciRcUiTr--,
L..._{$.!.M!.!'~O~ £!!!~T..!.!._.J
--'loAiiciiiciiiTr--'
L._~1.A!..!:~£!!I~~_.J
--UiAotiRciiii'r--,
L
..
_(~M~!!.O~ ~IU!lT.!l.._.J
,
Note l' The pulse generator has the following cluiractensbcs' PRn = 1 MHz, ZOUT "" son, duty cycle =
Note2 CL IACludes probe and 119clplcrtance.
No1ll3' All dHHles an 1N3064.
Note 4' Count·up Bnd count·down pulses mown are for tile SN54193/SN14193 blna,y cOllnlll,s. Count
cycle fo, SN5419Z decade counlll, IS 1 th'ol$ll~ 10
Nolll 5 Waveforms for outputs GA, Ga, amiDe
omitted to Simplify the drawing.
.,e
Test Circuit 2
~ISIll---l
l.--
--l l-
i;'.."...------"...,,,.-J..,.,+,,-"'----- ----
OATA
l""UT~llV
~'j'Jk
~-1
lOAD
~-~
,J·r
INPUT
----.j
w
~~ ____ _
+--:0: 15n.
...J/
OUTl'U~ _ _ _ _ _ _ _
Voltage Waveforms 1
H r-J"Toi\:_-=J}-U,
'5n.~
COUNT
~N'::
(See
Note4)
OU~UT
a;eeNote5)
"'\
\....J 9~~~
15nl
~
r.:::;"'\
LJr'3V
n
t. r:'\. .. r.:--\.!J
'3V~I~V
~~
\...:.J
--!'P"lt--
\1JV
•
i
!
:
~Vru+
't---Vo<
-.,~tPH1=it.CH~
BORROW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Vo..
13V~VOl
OUTPUT
Voltage Waveforms 2
3-64
3V
: --i.P:~-OV
c
Series 54L/74L
..&
r-
N
N
DM71L22/DM81L22 quad 2-input multiplexers
DM71L23/DM81L23 TRI-STATE®quad 2-input multiplexers
general description
......
C
Each buffered output can fanout to two standard
TTL unit loads over the commercial temperature
range, and 10 54L174L unit loads In the low state
over the Mil temperature range_ In addition these
devices can fanout to 20 54L174L unit loads with
the output in the high state ("1").
The DM71 L22/DM81 L22 and DM71 L23/DM81 L23
are quad 2-input multiplexers which select one of
two word inputs, and outputs the data when
enabled_ The enable input can be used to synchronize data transfer and forces the output to the "0"
state (DM71 L22/DM81 L22) or high impedance
state (DM71L23/DM81L23) when enable = "1"_
The advantageofthe DM71 L23/DM81 L23 is that it
makes "wlre-orlng" of the outputs possible_
....s:
s:
co
..&
r-
N
N
C
s:....
..&
r-
N
W
......
connection diagram
C
s:co
Dual-In-Lin. and Flat Packages
Vee
ENI
Dc
1e
touT
Do
lD
DouT
..&
I"
15
14
~
1
,
SELECT 0"
3
'...
t2
"
N
W
~
.,
Aou-r
r-
,
10
11
0,
, I'
•
1.
BOUT
GNO
TOP VIEW
truth tables and logic diagrams
ENABLE
E
1
•
••
•
SELECT
INPUT
S
X
1
1
INPUTS
OUTPUT
tPx 1x
X X
X
X 1
Z,
• ••
1
x
•• •
1
•
1
X
t2
Ycc=PlNI6
z,
z.
GNU" PIN I
z,
z.
DM71L22/DMB1L22
I"
I..
I",
I"
I,.
I"
I"
I"
15
ENABLE
E
1
•
••
SELECT
INPUT
S
X
1
1
••
INPUTS
OUTPUT
., 1,
Z,
HIZ
X
X
X
X
•
4>
x
1
X
1
4>
1
4>
1
Vee=PIN 16
GND=PlNB
z.
z.
z.
z,
DM71L23/DMB1L23
3-65
('I)
N
...
absolute maximum ratings
~
Q
.......
Supply Voltage
I nput Voltage
Output Voltage
...I
(Note 1)
operating conditions
00
('I)
+80V
+5.5V
+55V
Operating Temperature Range
OM71 L22, OM71 L23
OM81 L22, OM81 L23
N
...
...I
Storage Temperature Range
"'"
Lead Temperature (Soldering, 10 sec)
~
-55"e to +125"e
o"e to +70 o e
-65"e to +150o e
+300 o e
Supply Voltage (Vee)
OM71 L22, OM71 L23
OM81 L22, OMS1 L23
Temperature (TAl
OM71 L22, OM71 L23
OM81 L22, OM81 L23
MIN
MAX
UNITS
4.5
4.75
5.5
V
525
V
-55
0
+125
70
"e
"e
Q
N
N
electrical characteristics
...
(Note 2)
...I
PARAMETER
00
~
Vee
Q
Logical "0" Input Voltage
Vcc=Mm
.......
Logical "1" Output Voltage
10H:
Logical "0" Output Voltage
Mil.
N
N
...
...I
"'"
20
TYP
24
UNITS
V
0.7
V
030
040
V
V
2.S
015
020
= 2 rnA, Vee = Mm.
lOUT = 3.6 mA
lOUT
MAX
13
13
-200MA, Vee: Min.
Comm
~
Q
MIN
CONDITIONS
= Min
Logical "1" Input Voltage
V
+20
MA
V 1N = 2.4V, Vee = Max.
10
MA
V 1N = 5.5V, Vee = Max
100
Third State Output Current
DM71L23/DMS1 L23 Only, Vee: Max
Logical "1" Input Current
Logical "0" Input Current
V 1N
Output Short Circuit Current
(Note 3)
V OUT
""
-40
-0 IS
0 3V, Vee = Max.
= av.
Vee
-3
= Max
-9
-15
p.A
rnA
rnA
MAX
DM71L22/DMS1L22
See DC Test Ckts, Vee = Max
4
rnA
'CCMAX
DM71L23/DMS1L23
See DC Test Ckts, Vee = Max
53
rnA
Icc
Input Clamp Voltage
Output Vce Clamp Voltage
Output Ground Clamp Voltage
20
40
SO
ns
Vee: 50V, T A : 25"C, RL :4kr!,CL : 50pF
25
50
100
ns
Vee: 5.0V, T A : 25°C, RL : 4 kr!, e L : 50 pF
20
40
SO
ns
Vee = 5 OV, T A : 25°C, RL : 4 kr!, CL : 50 pF
35
70
140
ns
Vee: 50V, T A : 25"C, RL : 4 kr!, CL : 50 pF
DM71 L23/DMS1 L23 Only
15
30
60
ns
Logical "'" to High Impedance State
Delay from Enable to Output from
Logical "0" to High Impedance State
Vee: 5 OV, TA : 25"C, RL : 4 kr!, CL : 50 pF
DM71 L23/DMSI L23 Only
35
75
150
ns
Delay from Enable to Output from
Vee: 50V, T A : 25°C, R L : 4 kr!, CL : 50 pF
DM71 L23/DMSI L23 Only
15
30
60
ns
High Impedance State to Logical "1"
Delay from Enable to Output from
High Impedance State to Logical "0"
Vee: 5 OV, TA : 25°C, RL : 4 kr!, CL
DM71L23/DMSI L23 Only
20
35
70
ns
Propagation Delay to a Logical "1" from
DM71 L22/DMSI L22 Only
30
60
120
ns
DM71 L22/DMSI L22 Only
30
60
120
ns
Propagation Delay to a Logical "0" from
¢ or 1 to ZOUT, 'tpdO
Propagation Delay to a Logical "0" from
Select to ZOUT. tpdO
PropagatIon Delay to a LogIcal "1" from
¢ or 1 to ZOUT. tpd1
Propagation Delay to a Logical "1" from
Select to ZOUT. tpd1
Delay from Enable to Output from
:
50 pF
Enable to ZOUT. tpd1
Propagation Delay to
a Logical "0" from
Enable to ZOUT, tpdO
Note 1: "Absolute MaXimum Ratings" are those values beyond whIch the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electncal Characteristics" provides conditIons for actual devIce operatIon.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DM71L22,
DM71L23 and across the oOe to 70"e range for the OM81L22, DM81L23 All tYPlcals are given for Vee: 50V and
TA : 25°C.
Note 3: Only one output at a time should be shorted.
3-66
o
.......s::r-
DM71L22, DM71L23 dc test circuits
N
N
"'C
s::
v,.
v"
...r-
00
TEST
TEST
..R
.. R
N
N
o
TRUTH
TABLE
TRUTH
TABLE
1 '
.......s::r-
I
hc:h output tested SIpI,ately
ElChouqtultestld..,.,.tely
C
N
W
"'C
4,5V
SEE NOTE
-
I"
'.
'.
"
'.
Vee
v~
0
j. .
0
0
1
0
'.
1
s::00
...r-
l'~
N
'.
'
A
.
•
,
"
'.
0
w
}~.
V"
'::'
NOTE For '11i1HI OIl, tlkl'nlbll ,nput to 4 5V.1Id 110 to Dvom
For In.. 011 all, ground enable and take select Input to OV/4.5V
Tat IIH I. IlL on select I. lneblt Inputs "p.,ately WIth no speclll conditions on atlll' Inputs
':'
':'
Each uutputtested separ'tlly
ICC
lOS
DM71L22 ac test setup
VOUT
r--
I
"
....1---114
13
~.t-+-----I"
'A
-----,
I
I
I
~30PF
'::' .JI
_________
50 PF1'
L
z,
r---------,
r---------,
L. _ _ _
___ ...J
L ___
"':AM~S~ _ _ _
.J
~M~S:"
rL _
- _
- _
- _
-;M-;;;:S;- _
-_
___
..,
.J
3-67
P,)
N
...
...I
DM71L23 ac test setup
co
:E
o
Q
.......
YOUl
r-
CW)
N
...r-.
...I
:E
=
q
::: ~A~M!!A!:m~ : J
MEASURE
,..---------,..J
,..---------,
... __
__ .J
N
N
FROM
... _ _ ~D~~A!_~ _ _
...co
...I
"0"
~'!!!~-.!..~
:E
Q
...r-.
C,
Closed
"
"'" cC,"'
....
C,"""
c_
Closed
OFF
"'"
OFF
Clo&IICI
''0''
Opm
0",
OFF
.,..
N
N
.,
"0"
OFF
.......
TO
"1"
Closed
C,"'"
""pF
50pF
'pF
5pF
:E
Q
"
V.. II IIPUm
IV
- ttl'"
7-
13\1 level
'01
EllAIU
aLECT
~
'j
IV
"
,
11, ..
IL t -
J
V~
,_
nv
v..
W
-~
j n
',w
-
V
f\. f-I
vn
VI\. f-I
V",III.UTI}
- ,_
IV
- '... I- ...
.""'.'1"
101.',,,,,
_Ir......,.....
"..........
t-
I-
1,.,1
I-
t ..... " " _ 1 _ ....' . . . . '1" .......... 1IIPId
'.11-""
t~~""
'-
f-
...
I-
IOtnMIt..,.n
I .....'
I... ·"" _"-1.·,.... " .... 111 . .1....'
DM71L23 ac switching characteristics
IV
-
'-' 1--- '... I--
V
m
~
,---1
IV
3V
,
1311 {
~
-=- ....'
IV
IV
SELECT
'IV
,w
V
- ')r-~
'\
\L1 '
-
...
~
IVHI1.
\-
V.I1II1PU11)
IV
·hatI...,"_ .... .... ..
....... ·."' .... w11nl1ll . . .O..'I.Hunm .... I........ ""'"
",11.-"" ..... '1_.
1....
1 t o l . ' ..... IIIIct.1II/1
"·118"'ZI_.IIIIII"~""""
t,Hn= .... dlllyfrDIIIKllltltetG.I.·,duetotIIPI......1
I,ot.·Prop • .t.yt'DIIIH'I_IOIIofIc'O..... Ia ...... ,1IJIIII
3-68
-
'-
1--
....
-
-
",., I--
05VChange
13VlIIVei
~~
w
05VChange
""pF
1["·
!!!!.
TO
13VLtnlei
50pF
DM71L22 ac switching characteristics
...I
MEASURE
13\1 Level
Series 54L/74L
DM75L111DM85L11 TTL dual gated 0 flip flop
general description
features
The DM75L 11/DM85L 11 IS a low power TTL
dual gated 0 flip flop utilizing two gate Inputs.
Both gate inputs must be low to enable data transfer to the Q and Q outputs. If either gate input is
high the data on the Q and Q outputs IS constant.
•
Positive edge triggered, buffered clock
•
18 mW typical power dissipation
•
70 ns typical propagation delay
•
Pin compatible with STO TTL DM75111
DM8511
logic and connection diagrams
Dual-In-Line and Flat Package
Vee
ClR
ClOCK
G2
G1
CLEAR
116
15
"
13
11
1
2
3
4
,
11
10
•
7
9
G1
CP
G2
ClK
CLOCK
G2
-Q
G1
CLEAR
r
GNO
TOP VIEW
truth table
0
G,
G2
CLR
Q n+1
0
1
X
X
1
0
0
0
0
1
X
X
X
0
0
X
0
1
0
0
1
On
On
X
1
0
0
On
On
l'
On+1
* Asynchronous Transition
X = Irrelevant (Don't Care)
3-69
.....~
LO
absolute maximum ratings
co
(Note 1)
operating conditions
:iE
c
MIN
......
.......
Supply Voltage
~
Input Voltage
Output Voltage
LO
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
":iEc
+8.0 VDe
+55 VDe
+5.5 VDe
--65°e to +150o e
300°C
electrical characteristics
Supply Voltage (Vee)
DM75L 11
DM85L11
Temperature (TAl
DM75L11
DM85Lll
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°e
(Note 2)
CONDITIONS
PARAMETER
MAX
Vee = Min, lOUT = -2001lA
Logical "0" Output Voltage
DM75L11
DM85Lll
Logical "1" Input Current
All Inputs
DM75Lll Vee = Min, V ,N = 2.4V
DM85L 11 Vee = Min, V ,N = Vee
Logical "0" I nput Current
All Inputs
Vee = Max, V ,N = 0.3V
Output Short Crrcult Current
(Note 3)
Vee = Max, V OUT = OV
MIN
20
TYP
MAX
V
1.3
0.7
13
204
-3
V
V
2.8
0.30
0.15
0.20
Vee = Min, lOUT = 2 0 mA
Vee=MIn,louT=3.6mA
UNITS
0040
V
V
10
100
Il A
IlA
-100
-180
Il A
-9
-15
mA
4.9
3.5
mA
Supply Current (Per Package)
Vee = Max
Propagation Delay to a Logical "0"
from t pHL Clock to Output, tpdO
Vee = 5 OV, T A = 25°C
Figure 1 Waveforms A
75
125
ns
Propagation Delay to a Logical" 1"
from tpLH Clock to Output, t pd ,
Vee = 5.0V, TA = 25°C
Figure 1 Waveforms A
55
95
ns
Propagation Delay to a Logical "0"
from tpH L Clear to Output, tpdO
Vee = 5.0V, TA = 25°C
Figure 2 Waveforms B
75
125
ns
Propagation Delay to a Logical "1"
Vee = 50V, TA = 25°C
Figure 2 Waveforms B
55
95
ns
from tpLH Clear to Output, tpdl
Maximum Clock Frequency
Vee = 5 OV, T A = 25°C
Figure 1 Waveforms A
Minimum Clear Pulse Width, tW(eLEAA)
Vee = 5.0V, T A = 25°C
Figure 2 Waveforms B
30
100
ns
Minimum Clock Pulse Width, tW(eLOeK)
Vee = 5.0V, T A = 25°C
Figure 1 Waveforms A
30
100
ns
Vee = 5 OV, TA = 25°C
Figure 3 Waveforms C
40
80
ns
Vee = 5.0V, T A = 25°C
Figure 3 Waveforms C
30
60
ns
for Data Input
Minimum Set-Up Time tS(G) for
G, or G 2 Input
Vee = 5.0V, T A = 25°C
Figure 4 Waveforms D
40
80
ns
Minimum Hold Time tH(G) for
Vee = 5.0V, T A = 25°C
Figure 4 Waveforms D
30
60
ns
Minimum Set·Up Time for Data
Input, tS(DATA)
M,nimum Hold Time tH(DATAI
G, or G2 Input
6
MHz
9
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operatlng Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DM75L 11 and
across the O°C to 70°C range for the DM85L 11. All tYPlcals are given for VCC = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be shorted.
Note 4: SWitching parameters guaranteed to change less than 50% over the full operating temperature range.
3-70
c
....3:c.n
switching time waveforms
......r-
All times measured 110m 1lV level
PULSE GEN A
t.:ot,"15ns
3V
OV
PULSE GEN
t,u \f'" 15D5
V"
Vo,
Q OUTPUT
---.<,....11
ii DUTPUT
---1-"
3:
Q OUTPUT
Vo.
Vo,
......r-
c.n
V,"
V"
(b)
1--- -;t-:t
r-----
3V
ov
Pl~lSt~G~~n~ ---1oourpUT
C
00
V""
Vo,
_
OV
3V
ov
(a)
"q,'''"'
......
PULSE GEN B
1,"t,=1505
nOUTPUT
PULSE GENA
3V
::
1,101
----=.JC ______
~::
(d)
(e)
ac test circuits
FIGURE 2. Use Waveforms B
FIGURE 1. Use Waveforms A
"
"
"
FIGURE 4. Use Waveforms 0
FIGURE 3. Use Waveforms C
~
=
-II4-....~~W-..,
OUTPUT-. . .
ALL DIODES
lN3064 OR EQUIVALENT
FIGURE 5.
3-71
...
N
...I
Series 54Ll74L
in
CIO
:E
Q
.......
...
N
DM75L12/DM85L12 dual JK, D flip flop
...I
in
"'"
:E
general description
Q
a
The DM75L 12/DM85L 12 IS a dual JK, D flip flop
with a common clock and common clear. A
mode control input on each flip flop determines
the type of flip flop operation. (Mode = "I"
enables the JK mode, and mode = "0" enables the
D mode.) The clear input is an asynchronous
Input which overrides all other Inputs.
a
and
outputs are both provided on each
flip flop. TYPical propagation delays from clock
to outputs are approximately equal to three low
power TTL gate delays.
logic and connection diagrams
r---------- ----.,
CLEAR
I
I
I
I
I
I"
.,
MODE2
0,
15
"
"
12
CLEAR
Q,
10
11
,
rCP
CP
L
I
I
I
2
1
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ ...J
CP
0,
3
MODE 1
4
K,
TOP VIEW
"ONLY lOGIC FOR ONE Of THE TWO FLIP flOPS IS SHOWN
""'CLOCK AND CLEAR ARE COMMON TO BOTH FLIP flOPS
truth table
J
K
M
CLEAR
On+l
0
1
0
0
0
1
0
0
0
0
0
an
1
X
X
1
1
X
X
1
1
1
0
X
1
* Asynchronous Transition
3·72
1
0
On
D
0*
•
-Q,
•
1
Q,
I'
'NO
o
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 1)
+8.0 VDe
+5.5 VDe
+5.5 VDe
_65°C to +150oe
JOOoe
....3l:
....
operating conditions
Supply Voltage (Vee)
DM75L12
DM85L12
UI
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°e
°c
N
......
o
3l:
Temperature (T A)
DM75L12
DM85L12
00
UI
....
N
electrical characteristics
(Note 2)
Vee = 5.0V, T A = 25°C, RL = 4k!2, CL = 50 pF
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee'" Max
Logical "0" Input Voltage
Vee = Max
Loglca''','' Output Voltage
lOUT
Logical "0" Output Voltage
Mil lOUT'" 2 rnA,
Vee
Com lOUT = 36 rnA.
Logical "1" Input Current
Y,N :24V
V 1N "'55V
VIN
logical "0" Input Current
Vee
Output Short Circuit Current
(No.e 31
= -200J,l.A. Vee'" Min
24
015
020
= Mm
D. J, K, M, Inputs, CP, CLEAR
= 0 3V, Atllnputs
= Max
V OUT =
av. Vee'" Max
-3
-9
"1" from Clock to Output,
tpd1
Propagation Delay to a Logical
'"
tpdO
6
MaXimum Clock Frequency
UNITS
V
07
V
V
03
04
V
V
10
100
IlA
IlA
-180
IlA
-15
rnA
45
"
'2
tpdO
MAX
28
Vee'" Max
Clock to Output,
tHOLD Minimum
13
Vee = Max
Propagation Delay to a Logical
tSETUP MInimum
TYP
2
13
Propagation Delay to a logical
"0" from Clear to Output,
MIN
M, '" M2 = CP = "0", All Other Inputs::: "1"
Supply Current - Icc Max
"a" from
WAVEFORM
REFta
rnA
60
120
ns
35
70
ns
57
114
10
JK
t3, t4
77
Mode
t 7 , tl0
Data
t 12. t13
81
45
JK
t51 t6
77
Mode
ts. tg
Data
t 14 • t 15
81
45
HI
ns
MHz
140
160
90
ns
ns
ns
140
150
90
ns
ns
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "E lectrical Characteristics" provides conditions for actual device operation.
Nota 2: Unless otherwise specified minimax limits apply across the -S5°C to +125°e temperature range for the DM75L 12
and across the oOe to 70°C range for the DM85L12. All typicals are given for Vec: S.OV and TA: 2Soe.
Note 3: Only one output at a time should be shorted.
3·73
....
...I
('II
ac test circuit
It)
CIO
:!
c
.......
('II
....
...I
,...
+5V
+5V
It)
4K
:!
c
OUTPUTS
+5V
T
ALL DIODES 1N916
CL = INCLUDES PROBE AND JIG CAPACITANCE
switching time waveforms
3-74
c
s:
.....
Series 54L/74L
U1
r-
...
U1
.......
C
s:00
U1
r-
DM75L511DM85L51 low power TRI-STATE® quad-D flip flop
general description
features
The DM75L51/DM85L51 IS a TRI-STATE ® logic
device which provides four D-type flip flops in one
package which operate synchronously from a common clock.
•
Series 54L/74L compatible
•
50 ns tYPical propagation delay
A unique three-state output allows the device to
be used In bus-organized systems. The outputs can
be directly wired to outputs of other DM75L51/
DM85L51s without encountering the problems
normally met with "coliector-ORing" LP TTL circuits. This is accomplished by gating the normally
low impedance logical "1" or logical "0" output
into a high impedance state.
....U1
•
30 mW tYPical power dissipation
•
Outputs directly connectable for bus-line operation
•
A "do-noth Ing" state accomplished without
gating the clock
•
Simple disable encoding
The DM75L51/DM85L51 is completely compatible
with other Series 54L/74L devices.
logic and connection diagrams
Dual·1 n-Line and Flat Package
DATA
INPUT
DISABLE
~
Vee
CLEAR
I..
A
.
" " " " " "
~
~
,
,
2
. . . , I'
OUTPUT
DISABLE
truth table
(Both Output Disables Low)
'.
DATA INPUT DISABLES
Log"al"l"onlorbothmpuIS
Log,c~1
On
"0" on both Inputs
Log,cal"O"onbothonputs
3-75
----
'I""
II)
.....
co
:E
absolute maximum ratings
II)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM75L51
DM85L51
Q
.......
(Note 1)
8.0V
55V
5.5V
_55°C to 125°C
O°C to 7efC
_65°C to 150°C
300°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
'I""
II)
electrical characteristics
.....
.....
:E
II)
PARAMETER
Q
(Note 2)
CONDITIONS
Logical "I" Input Voltage
DM75L51 ~~=4.5~
DM85L51- Vee = 4.75V
Logical "0" Input Voltage
DM75L51
DM85L51
Vee = 4.5V
Vee = 4.75V
Logical "I" Output Voltage
DM75L51
DM85L51
Vee = 4.5V
Vee = 4.75V
lOUT = -1 mA
lOUT = -1 mA
Logical "0" Output Voltage
DM75L51
DM85L51
Vee = 4.5V
Vee = 4.75V
lOUT = 2 mA
lOUT = 3.6mA
Third State Output Current
DM75L51
DM85L51
Vee=55V
Vee = 5.25V
V OUT = 2.4V
VOUT=O.3V
Logical "1" Input Current
DM75L51 ~:5.5V
DM85L51- Vee = 5.25V
Y'N = 2.4V
Y'N = 5.5V
Logical "0" Input Current
DM75L51
DM85L51
Vee = 5.5V
Vee=525V
Y'N = 0.3V
Output Short CirCUit Current
(Note 3)
DM75L51
DM85L51
Vee= 55V
Vee = 525V
V OUT = OV
Supply Current· (each device)
DM75L51
DM85L51
Vee = 5.5V
Vee = 5.25V
Icc (max)
MIN
2
2
TYP
1.3
1.3
2.4
2.4
UNITS
V
V
0.7
0.7
2.7
2.7
0.15
0.2
-3
-3
MAX
1.3
1.3
V
V
V
V
0.3
04
V
V
20
-40
IlA
IlA
<1
<10
10
100
IlA
IlA
-120
-120
-180
-180
IlA
IlA
-8
-8
-15
-15
mA
mA
9
mA
5.5
Propagation Delay to a Logical "0" from
Clock to Output, tpdO
Vee = 5.0V
TA = 25°C
77
120
ns
Propagation Delay to a Logical "I" from
Clock to Output, t pd,
Vee = 5.0V
TA = 25°C
39
70
ns
Propagation Delay from Clear to
Output, tpdR
Vee = 5.0V
TA = 25°C
72
110
ns
Delay from Output DISable to High
Impedance State (from Logical "I"
Level), t'H
Vee = 50V
TA = 25°C
18
50
ns
Delay from Output DISable to High
Impedance State (from Logical "0"
Level), tOH
Vee = 5.0V
TA = 25°C
32
75
ns
Delay from Output DISable to
Logical "I" Level (from High
Impedance Statel. t H,
Vee = 5.0V
T A =25°C
28
55
ns
Delay from Output DISable to
Logical "0" Level (from High
Impedance State), tHO
Vee = 5.0V
TA = 25°C
35
60
ns
MaXimum Clock Frequency
Input Data Setup Time, tSOATA
Input Data Hold Time, tHOATA
Vee = 5.0V
TA = 25°C
Vee = 5.0V
TA = 25°C
Vee = 5.0V
TA = 25°C
6
15
+5.7
10
MHz
+10
+2
ns
ns
IS OIS
Vee=50V
TA = 25°C
33
45
ns
Input DISable Hold Time, tHOIS
Vee = 5.0V
TA = 25°C
19
40
ns
Input Disable Setup Time,
Not. 1: "Absolute Maximum Ratings" are those values beyond whieh the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at thesa limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Not. 2: Unless otherwise specified min/max hmits apply across the -55°C to +125°C temperature range for the DM75L51 and
across the COc t9 70°C range for the DMB5L51. All typical. are given for VCC = 5.0V and TA ~ 25°C.
Note 3: Only one output at a time should be shorted.
3·76
..
c
3:
"""
UI
I"'"
...
UI
.......
c
3:
00
UI
, mA fOR DRIVING OTHER LmllNPUTS
I"'"
...
IUILlJfEl
UI
~
SELECTED AS
DRIVING
DEVICE
SELECTED AS
DRiViNG ......
DEVICE
2bAx45DUTPUTS= SmA
LEAKAGE CURRENT
GATED INTO
THIRD STATE
GATED INTO
THIRDSTATE-
GAllO INTO
THIRD STATE
GATED INTO
THIRDSTATE-----
20 "A LEAKAGE CURRENT
FIGURE 1
FIGURE 2
FIGURE 3
mode of operation
The high impedance state occurs on all outputs of
all devices except the four outputs of the one de·
vice selected (Figure 1). The result is that the
selected device has a normal LPTTL low impedance output providing good capacitive drive capability and waveform integrity especially during the
transition from a logical "0" to a logical "1". The
other outputs are all in the "third·state" and take
only a small amount of leakage current from the
driving outputs. Since the logical "1" output current of the selected device is 5 times that of a
normal Series 54L/74L output (1.0mA vs 200J.lA),
the output is easily able to supply that leakage
current to as many as 45 connected devices and
stili retain enough drive for a full Series 54L/74L
fanout of 10 at the end of the bus line (Figure 2).
A two·mput NOR gate facilitates selection of the
driving device through the use of only two 1 out of
5 decoders for as many as 64 DM75L51/DM85L51s
(Figure 3).
A problem inherent in conventional D·type flip
flops is that It is impossible to code the data input
in such a way as to cause the flip flop to remain in
its present state when clocked. Because flexibility
is not as great as with a J..K flip flop (and its J=O,
K=O state), to keep a D-type flip flop in its present
state it is usually necessary to gate the clock,
which increases the danger of false·clocking. The
DM75L51IDM85L51 contains a gated input disable
which does not disrupt clocking, but rather recirculates information from the Q output to the D
input. In this manner the flip flop does not change
state and the possibility of false·clocking is elimi·
nated.
The following logic levels control the device:
• Clocking occurs on the positive-going transition.
• Clearing is enabled by taking the input to a
logical "1" level.
• Outputs are placed in the "third·state" if either
of the two Output Disable inputs is taken to a
logical "1" level.
• The flip flops will remain in their previous state
when clocked so long as either of the two Data
Input Disable inputs is taken to a logical "1"
level.
3-77
switching time waveforms
CLOCK
INPUT
tS£E NOTE 21
r---------,------------w
;---------,----------W
13V
------oV
----------ov
1......
INPUT
(PULSE 1)
(SEE NOTE 31
r-t-------,----------------3V
13V
------OV
I.....
r-------------W
INPUT
('ULSEI)
1lY
t--------------- OV
(SEE NOTE 3)
- - -...
l p (d ... )
'. ,
VOM
DOUT'UT
v.,
DOUT'UT
13V
v.,
rti
v..
II OUTPUT
VOM
}-
OOUWUT
13V
V"'-
v••
v.,
j~,
'...
r---""'\----- W
CLOCK
INPUT
lW
(SEENOTEZ)
.....____ ov
r---~------------------_,,-----+--------------3V
DATA
INPUT
13V
-+------..
1......
,...,..._,-_________ 3V
13V
-'I
IN'UT
DISABlE _ _ _ _ _ _ _ _
I'------·V
tSDIS
r------------V~
..JI__
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
j
13_V_ _ _ _ _ _ _ _ _ _ _ _ .,
V
r----,-----------3V
CLEAR-{
CSEf NOTE 4)
_'_
.._ _ _ _ _ _ _ _
ov
'""f._v.
',,-
OU1PUT
1.._13_V_ _ _ _ _ _ _ _ __
-
3-78
VOL
Nett'
NDteZ
Note3
....
Allnplltpu... hMl.-t."'llins
CW.aput 1p~):?:2aOnslndPRR=5ODkHz Whln tfttlq'-. Ultse" duty cycle
'u""Mpulse:r: t p =10DIII,.PRRII6O%oIthlclock'RR
\.4_,=:?:10DIII,.PRRII600ItHz
NDtlIi IpIDATAI· 41pCdUTC~l
'""
'"'
'"'
ISEENOTE41J
Closed
Closed
5,F
0","
Closed
5O,F
Open
{SWITCH'
Pulsegan PRR = 500kHz, tp(dockl 2: 200 ns, t,= t,= 15 ns.
See at switching tlme waveforms.
Ttethesetnputstogether,seBacSWltchmgtlmeWl'ieforms
Includes Jig and probe capacltlInce.
All dlodHI~ 1N3064 Of etjulVaient
Jlgcapaclmnce
Use 50% duty cVcle
{See Note 61
50pF
5O,F
tHOATA
tSOIS
Closed
5O,F
tHotS
Closed
5O,F
f<.,,~
}
5O,F
tSOATA
Note 1
Note 2.
Note3
Note 4.
Note 5
Note&
Note1
5FF
Closed
5O,F
3·79
Series 54L/74L
DM75L52/DM85L52 TRI-STATE® decade counter/latch
DM75L54/DM85L54 TRI-STATE
binary counter/latch
general description
features
The OM 75L52/DM85 L52 and OM 75L541DM85L54
are LPTTL TRI-STATE synchronous decade and
binary counter/latch circuits respectively. The circuit consists of a counter made up of four edgetriggered J:K flip-flops.
• Series 54L/74L compatible
• 38 mW typical power dissipation
• TRI-STATE outputs directly connectable for
bus-line operation
• TR I-5T ATE outputs information may be latched
• 50 ns typical propagation delay
The circuits logically combine the function of
counters for frequency division, latches to hold
the counter's information, and output buffer gates
which allow active LPTTL outputs as well as the
high impedance (3rd) state for output multiplexing
of data.
• Count mode and terminal count output are
operable when the outputs are in the high
impedance state or latch mode_
• Blanking capability with the OM75L52/
OM85L52
• Positive true logic
logic and connection diagram
Dual-In-Line and Flat Package
,
T" "
cr
'RESETCUAfI
CE'
"
" " "
"
'"
,
..
t
~
, , ,
. . . , I'
_ _ _ _ _ OUTPUTOUTPUTOUTPUTOUTl'UT TERM
OUTPUT
DISA&LU
COB
A
GMO
COUIn
rOPYIEW
typical application
Multi-Stage Synchronous Counter with Visual Display
DISPLAY
DISPLAY
UNIT
UNIT
DISPLAY
UNIT
DISPLAY
UNIT
Y", o--...-+......Hf-~h
COUNT
ENABLE
~O-~~~~~~---4~~~~~~~+-~~~~~~~~~~~~
STR08Eo--...--.."'sr=.T"'..""---...---,,"'.0'"'.., ,."'."",--"'--"',.""o"'sr"'.o"',--"'---,::..""o..=.o"",--
3-80
I
TOMOR'
SIGNIFICANT
STAGES
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
(Note 1)
8.0V
5.5V
5.5V
_65°C to 150"C
300"C
3:
.....
operating conditions
U1
r-
MIN
MAX
UNITS
U1
4.5
4.75
5.5
5.25
V
......
-55
+125
70
"C
"C
N
Supply Voltage (VCC)
DM75L52175L54
DM85L52/85L54
Temperature (T A)
DM75L52,DM75L54
DM85L52,DM85L54
o
c
V
3:
CO
U1
r-
U1
electrical characteristics
N
(Note 2)
C
PARAMETER
CONDITIONS
MIN
2.4
Logical "1" Input Voltage
Logical "1" Output Voltage
Vol~ge
- Terminal Count
logical "0" Output Voltage
lOUT = -1 mA
2.4
lOUT; -200 iJ.A
2.4
"CET"
U1
r-
0.7
U1
.Jlo
......
c
3:
28
DM75L52/DM75L54, lOUT = 2 rnA
015
DM85L52/DM85L54, lOUT = 3.6 mA
02
0.3
CO
0.4
20
U1
r-
-40
U1
V'N=24V
<2
20
.Jlo
V'N ; 5.5V
<20
200
V OUT = 0.3V
Logical "'" I nput Current
V'N; 2.4V
<1
10
V'N=55V
<10
100
"CET"
V'N = 0.3V
-240
-360
"Other Inputs"
V ,N =03V
-120
-180
iJ.A
-8
-15
rnA
"Other Inputs"
3:
.....
UNITS
2.7
VOUT= 24V
Third State Output Current
MAX
13
13
Logical "0" Input Voltage
Logical "1" Output
TYP
Logical "0" Input Current
Output Short Circuit Current (Note 3)
Supply Current - (Each Dev,ce)
V OUT = OV
-3
lee (Max)
"a" from
7.6
130
rnA
75
150
ns
115
220
ns
Vee; 5.0V, T A; 25"C
90
160
ns
Delay from Output Disable to High Impedance
State (from Logical "1" Level), t'H
Vee; 5.0V, TA = 25"C
8
15
ns
Delay from Output Disable to High Impedance
State (from Logical "0" Levell, tOH
Vee = 5.0V, TA = 25"C
57
105
ns
Delay from Output Disable to Logical "1"
Level (from High Impedance State), tH1
Vee = 5.0V, TA = 25"C
75
150
ns
Delay from Output Disable to Logical "0"
Level (from High Impedance State), tHO
Vee= 5.0V, TA = 25°C
90
150
ns
Propagation Delay to a Logical
Clock to any Output,
Vee; 5.0V, T A ; 25°C
iJ.A
tpdO
Propagation Delay to a Logical "1" from
Clock to any Output,
tpd1
Propagation Delay from
TE to Output,
tpd (TE)
MaXimum Clock Frequency
6
11
MHz
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Unless otherWise specified min/max limits apply across th~ _55°C to +125°C temperature range for the DM75L52,
DM75L54 and across the O°C to 70°C range for the DM85L52,DM85L54. All typlcals are given for Vee = 5.0V and
TA=25"C
Note 3: Only one output at a time should be shorted.
3-81
mode of operation
When the Transfer Enable (TE) IS at a logical "1"
level the data transfer paths between the counter
outputs and the output buffer gates are maintained.
When the Transfer Enable is at a logical "0" level,
the data transfer paths are inhibited, and the state
of the output buffer gates are locked in by the
latches. The counter and Terminal Count (TC)
output remain op~rable during this time.
• Clearing or presetting is enabled by taking the
respective onput to a logical "1" level.
Asynchronous Clear (CL) resets the counter to
0000.
• To place the TRI-STATE outputs into the
"third-state" either of the Output Disable (OD)
inputs must be taken to the logical "1" level.
• To enable the count mode both CET and CEP
onputs must be at a logical "1" level.
• To latch the outputs the Transfer Enable (TE)
input must be taken to the logical "0" level.
Asynchronous Preset (PRE) sets the counter to
1111. The 1111 state may be used on the
DM 75L52/DM85L52 for blanking out leading
zeroes in visual displays. The next clock pulse
will advance the DM75L52/DM85L52 to 0001
which denotes the first count of the blanked
zero. The next clock pulse will advance the
DM75L54/DM85L54 to 0000.
The clock input must be high during the high to
low transition of CEP and/or CET for correct
logic operation. The CEP and CET inputs may be
used in a high speed look ahead technique (see
application).
Counter stages can be cascaded as shown above
to provide multiple stage BCD or Binary synchronouscounting by using the DM75L52/DM85L52 or
the DM75L54/DM85L54 respectively. With a Terminal Count (TC) fan out of ten the above scheme
allows eleven stages to operate at the maximum
frequency equ ivaient to a two stage counter.
The Terminal Count (TC) output is active high
when the counters are at terminal count and the
CET is high. The Terminal Count logiC equations
are:
DM75L52/DM85L52
TC = CET'AS'C'D
DM75L54IDM85L54
TC
=
CET'A'B'C'D
The characters displayed can be held with a low
level on the strobe line while the counters can
continue counting. The display can be updated by
applying a positive pulse to the strobe line.
The following logic levels control the device:
• The counters changes state on the positivegoing transition of the clock.
logic tables
FUNCTION TABLE
OUTPUTS
INPUTS
001
002
CEP
CET
CLEAR
PRESET
TE
1
X
0
0
0
0
X
1
0
0
0
0
X
X
X
X
X
X
X
1
0
X
X
X
1
X
X
1
x
x
x
x
x
1
1
x
x
0
0
A
8
C
D
TC
"High Impedance State"
,
H~r;p:j s~,,·
0
1
LATCH
COUNT
1
1
1
0
1
·Functlon of the count sequence
DM75L52/DM85L52
DECADE COUNT SEQUENCE
DM75L54/DM85L54
BINARY COUNT SEQUENCE
---~
OUTPUTS
OUTPUTS
COUNT
A
8
C
0
TC
0
1
2
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
Next
1
Count
1
1
0
1
0
1
0
0
0
3
•
5
6
7
B
9
UtfPreset
Applied
..
The 1111 state may be used
In
conjunction with
certain decoder/dnvers Ie. DM5446. DM5447
and DM5448 for blankmg leading zeroes
3-82
COUNT
0
1
2
3
•
5
6
7
B
9
10
11
12
13
I.
15
A
B
C
D
TC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
o
s:
......
logic diagrams
C1I
r-
DM75L52/DM85L52
.
,
OUTPUT
OUTPUT"::=:::[~IODISABlES O
C1I
OUTPUT
""-+______
_____""'-1f-______
N
,
OUTPUT
~~+
"o
s:CO
_______J
C1I
r-
C1I
N
o
s:
......
C1I
r-
C1I
410
"o
s:CO
C1I
r-
C1I
410
COUNT ENABLE
TRICKLE
COUNT ENABLE
PARALlel
DI
DM75L54/DM85L54
,
OUTPUT
.
OUTPUT
,
OUTPUT
,
OUTPUT
TERMINAL
COUNT
OUTPUT
DISABLES
TR::!~~:o---D
_______'--I_+""____'--I_+""____""+_H_______""+-I1-'
COUNT
ENABLE
TRICKLE
COUNT
ENABLE
PARAllEl
3-83
o:t
It)
....I
ac test circuit
It)
co
:E
Q
........
o:t
~
....I
L----
SEE
It)
TABLE 1
It)
~
At
DM15l52,
DM75l54
LOAD
~
"'"
:E
Q
FIGURE 1
N
It)
....I
It)
co
INPUT CONDITIONS
:E
001
TEST
Q
002
CET
CEP
CLEAR
PRESET
CP
TRANSFER
ENABLE
........
N
tpdO
GND
GND
Vee
Vee
GND
GND
See Note 1
Vee
It)
tpd1
GND
GND
Vee
Vee
GND
GND
See Note 1
Vee
See Note 2
....I
It)
"'"
:E
Q
tpd(TE)
GND
GND
Vee
Vee
GND
GND
See Note 1
t'H
See Note 4
See Note 4
GND
GND
GND
Vee
GND
Vee
tOH
See Note 4
See Note 4
GND
GND
Vee
GND
GND
Vee
tH'
See Note 4
See Note 4
GND
GND
GND
Vee
GND
Vee
tHO
See Note 4
See Note 4
GND
GND
Vee
GND
GND
Vee
fCLOCK
GND
GND
Vee
Vee
GND
GND
See Note 9
Vee
TABLE 1
ac load circuit
I"
TEST
SWITCH S1 SWITCH S2
CL
400n
INPUTS
-
OM75l5Z,
DM15l54
tpdO
Closed
Closed
50 pF
tpd1
Closed
Closed
50 pF
tpd(TE)
Closed
Closed
50 pF
t'H
Closed
Closed
50 pF (See Note B)
tOH
Closed
Closed
50 pF (See Note 8)
t H,
Open
Closed
50 pF
tHO
Closed
Open
50 pF
f eJock
Closed
Closed
50 pF
FIGURE 2
Note 1. Pulse gen PRR..;:; 1 MHz, t,:::;: 15 ns. t...;:; 5 ns, Iplclod B, A < B, A == Band
A- B.
The A < Band A > B are active High outputs,
active with the relative magnitude of WA (Word A)
and WB input conditions.
a standard multiple input NAND gate with each of
the A - B outputs connected to a gate input will
indicate a WA -WB'
The maximum speed method of cascading and
typical comparison times are shown in Figure Y.
TRI-STATE outputs are activated by tying both
active low input enables to a logical "Low."
Raising either to a logical "High" forces the outputs to the High Impedance state.
The A == B is High only when all of WA and WB
inputs are identical.
features
The A - B output is unique with the device and is
described as "WA (Word A) Almost (But not
Equal to) WB (Word B)." The A - B output is
High only when WA is within one binary count
of WB'
For maximum function expansion (Figure X) the
A > B and A < B outputs of the less significant
bit compar~n be connected to the least
significant bit input of the next most significant
comparator. For expansion of the A - B function:
75 mW
• Typical power dissipation
70 ns
• Typical prop. delay
• May be cascaded to compare words of greater
length.
• A Almost B (A - B) output for look-ahead
and anticipation of a match
• TRI-STATE outputs
• A > B, A
available
<
B, A == B and A - B outputs
logic and connection diagrams
Dual-In-Line Package
TRISTATE
OUTPUTS
OUTPUT ENABLES
WORD A
MSB
V"
A,
ACTIVE lOW
E,
-----------
A-'
A;;;;B
12
11
13
A<.
A>.
10
256 X4
lOW POWER
ROM
OUTPUT {
ENABLE
--..t'+--'++-~--.
Az
A>B
A='B
A-B
Al
AB
x
X
X
X
X
X
X
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
H
x
A, >8,
x
x
x
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
Ao>Bo
L
L
L
L
H
H
AoB3
A3 82
Aa = 8 a
A2
A3
= Ba
= 8a
Aa = 8a
A2 Word B By 1
"Word A < Word B By 1
H = High Level, L" Low Level, X = Irrelevant
Figure X. 16-Bit Comparator, Maximum Logic Expansion: A
< B, A > B,~. A"" B
(MSB}
(LSB}
OUTPUT
ENABLE
COMPARE
CIRCUIT DELAY
1-4 BITS
51 BITS
1 DElAY
8-10 BITS
2DEtAYS
2DELAVS
NUMBER
OF CIRCUITS
2DELAVS
Figure Y. Maximum Speed Expansion (Not Suitable for A ....... B)
3-90
c
s:.....
Series 54L/74L
0)
r.....
U'I
DM76L75/DM86L75 low power presettable decade counter
DM76L76/DM86L76 low power presettable binary counter
"'C
s:00
general description
0)
Cj
Operation can best be understood by realizing that
in order for counting to occur both GEP and GET
must be at logical "'" levels. In addition the Tc
output is a logical "'" only when a counter is at
its maximum count (gfor the DM76L75/DM86L75;
and '5 for the DM76L76/DM86L76) and when
the GET input is at a logical "'" level. Therefore
if counters are connected as shown, a more significant counter stage cannot be clocked until all
previous counters are at their maximum count.
The reason for the feedforward connection from
the least significant counter to all GEP inputs is
that no counter needs to wait for a ripple from the
previous counter when the least significant counter
changes from a maximum count to zero.
The DM76L75/DM86L75 and DM76L76/DM86L76
are synchronous up decade and binary counters
respectively. They have synchronous parallel load
capability, overriding asynchronous master reset,
terminal count and carry look-ahead logic for high
speed multi-decade operation.
The counters are synchronous, with the counter
outputs changing state after the logical "0" to
logical "'" transition of the clock. When the
parallel enable input is low, the parallel inputs
determine the next state of the counter synchronously with the clock.
Mode selection is accomplished as shown in the
table below. However the transition of GEP or
GET from logical "'" to logical "0" or of PE from
logical "0" to logical "'" may only be done with
GP in the logical "'" state.
U'I
c
s:.....
0)
r.....
0)
"'C
s:00
0)
r.....
0)
features
•
A logical "0" level on M R will reset all outputs
to log ical "0".
The purpose of the GEP and GET inputs and the T c
output is to provide for a fast propagation delay
when cascading several decades (shown below).
32 mW typical power
•
'3 MHz typical count frequency
•
Series 54L/74L compatible
•
Pin compatible with 93L' 0, 93L'6
logic and connection diagrams
"
f'
l ~r-.
il" ~-
,
~"
I
I
?"
p"
i
~.o
~.'
I
-fd~
L
-~~,
L
t;:-r\'
------
"'-l~>
~":
~
IL __
<.r=c>-
I'
I'
I
I
-- ---- ----- -- I-
I
I
I
..
~
.
~'i.'i.~~I:
~
J" .
.
Note OllttedlineportlonsapphcabletoOM16L15/DM8bl750nly
Dual-I n~-Line and Flat Package
Vc:c
Tc
Do
11,
112
14
~T
Jir
3-9'
CD
.....
...I
absolute maximum ratings
CD
CO
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM76L75, DM76L76
DMB6L75, DMB6L76
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
:E
C
"CD.....
...I
CD
.....
:E
electrical characteristics
C
PARAMETER
It)
BV
5.5V
5.5V
_55°e to +125°e
oOe to +70 o e
-65°e to +150 o e
3000 e
(Note 2)
CONDITIONS
DM76L75/76
DM86L75/76
Vee = 4 5V
V cc -475V
CD
CO
logical "0" Input Voltage
DM76L75/76
DM86L75176
Vcc=45V
Vee 4.75V
:E
Logical "1" Output Voltage
DM76L75/76
DM86L75/76
Vcc=45V
Vee 475V
lOUT = -200 /J.A
lOUT
...I
C
".....
It)
...I
CD
.....
:E
C
2.0
UNITS
MAX
TYP
MIN
Logical "1" Input Voltage
.....
V
1.3
13
2.4
V
0.7
V
3.1
V
V
0.3
0.4
0.2
0.2
DM76L75176
Vee:: 4 5V
DM86L75176
Vee
DM76L75/76
DM86L75176
Vcc=55V
Y,N = 2 4V
Vee - 5.25V
VIN '" 5 5V
10
100
~A
All Inputs Except CET
C'T
DM76L75/76
DM86L75/76
Vee = 5 5V
20
200
~A
Vcc -525V
VIN = 2 4V
V 1N =55V
Logical "0" Input Current
All Inputs Except C ET
DM76L75/76
DM86L75/76
Vee = 5.5V
V cc -525V
VIN = O.3V
VIN = 04V
-100
-180
~A
.c'T
DM76L75/76
DM86L75/76
Vee = 5 5V
V cc =525V
VIN = 0 3V
VIN = 04V
-200
-360
~A
DM76L75/76
DM86L75176
Vcc=55V
-9
-15
mA
DM76L75176
DMB6L75176
Vee = 5 5V
9
mA
Logical "0" Output Voltage
Logical "'" Input Current
Output Short CirCUit Current
INole 31
Supply Current
4.75V
lOUT
=
2 0 mA
3.6mA
-3
V cc -525V
Vee
6.5
525V
~A
~
Propagation Delays
Clock to Any Q Output
tpd1
65
45
110
75
ns
ns
IpdO
Ipdl
85
70
140
115
ns
ns
tpdO
35
35
60
60
ns
.ns
"'dO
Clock to T c Output
GeT to T c Output
"'dl
I,ICE)
I,ICEI
Setup Time CE
Release Time CE
40
50
65
80
ns
ns
I,
I,
Setup Time P Inputs
Release Time P Inputs
15
15
30
30
ns
ns
1,1,,")
1,1,,")
Setup Time Parallel Entry
Release Time Parallel Entry
40
40
65
65
ns
ns
Count Frequency
6
13
MHz
Clock Pulse Width
60
25
ns
Reset Pulse Width
80
30
ns
-Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature
range for the DM76L75 and DM76L76 and across the O°C to 70°C range for the DM86L75 and
DM86L76. All typieals are given/or V CC = 5.0V and T A = 25°C.
mode selection
PE
CE
MODE
1
1
1
Count
No Change
Preset
o
o
X
cascading counters
~
CC-C"'~PCEP
To
~
en
~
To
en
~
To
en
~
COUNT-....- - - -....- - - -....- - - -....- -
3·92
Series 54L/74L
DM76L97/DM86L97 TRI-STATE®low power
1024-bit read only memory
general description
features
The DM76L97/DM86L97 is a custom-programmed
Read Only Memory organized as 256 four-bit
words. Selection of the proper word is accomplished through the eight select inputs.
•
Full tenth-power technology
•
Pin compatible with SN54187/SN74187
• Typical power dissipation
Two overriding memory enable inputs are provided
which when mask-programmed in one of the
three options described will cause all four outputs
to read either the normal memory contents or
go to the high impedance state.
• Typical access time
75mW
70 ns
• Custom-programmed memory enable inputs
• TRI-STATE outputs
logic and connection diagrams
MEIo10AY
~>
m
A,
(tl
"0
(5)
f,..e'''''~'''==:::::l::J-I-\--I_+__I_f-_--,
UAUfLME'oJ1'1
Dual-In-Line and Flat Package
MEMORY
ENABLE
OUTPUTS
BINARY
Vee
SELECT H
ME2
ME,
V,
Y,
BINARY SELECT
TOP VIEW
3-93
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
7.0V
5.5V
5.5V
Storage Temperature Range
~5°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
electrical characteristics
operating conditions
Supply Voltage (V CC)
DM76L97
DM86L97
Temperature (T A)
DM76L97
DM86L97
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
°c
°c
+125
+70
(Note 2)
CONDITIONS
PARAMETER
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee
Logical "1" Output Voltage
Vee = Mm, 10 = -1.0 mA
Logical "0" Output Voltage
DM76L97
DM86L97
Vee = Min, 10 = 2.0 mA
Vee = Mm, 10 = 3.2 mA
Third State Output Current
DM76L97
DM86L97
Vee = Max, Vo = 2.4V
Vee = Max, Va = O.4V
MIN
TYP
Vee = Max, V ,N = 2.4V
Vee = Max, V ,N = 5.5V
Logical "0" Input Current
Vee = Max, V ,N = 0.3V
UNITS
V
2.0
0.7
= Min
Logical "1" Input Current
MAX
V
V
2.4
0.3
0.4
V
±40
±40
Jl.A
Jl.A
10
100
-6.0
V
Jl.A
Jl.A
-180
Jl.A
-30
mA
20
mA
Jl.A
Output Short CirCUit Current (Note 3)
Vee = Max, Va = OV
Supply Current
Vee = Max, All Inputs at GND
Third State Output Current
Vee = Max, V OUT = 2.4V
Vee =Max, V OUT =O.4V
+40
-40
Input Clamp Voltage
Vee = Min, liN = -12 mA
-1.5
V
85
ns
15
JJ.A
From Address to Output (tpdo)
Vee = 5.0V, e L = 50 pF
TA = 25°C
55
Propagation Delay to a Logical "1"
From Address to Output (tpd')
Vee = 5.0V, CL = 50 pF
TA = 25°C
86
130
ns
Delay From Enable to High Impedance
State (From Logical "1" Level) (t'H)
Vee = 5.0V, CL = 5.0 pF
TA = 25°C
15
23
ns
Delay From Enable to High Impedance
State (From Logical "0" Level) (tOH)
Vee = 5.0V, C L = 5.0 pF
TA = 25°C
57
86
ns
Delay From Enable to Logical" 1" Level
(From High Impedance State) (tH')
V ee =5.0V,C L =50pF
TA = 25°C
34
51
ns
Delay From Enable to Logical "0" Level
(From High Impedance State) (tHO)
Vee = 5.0V, C L = 50 pF
TA = 25°C
47
70
ns
Propagation Delay to a Logical "0"
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature range for the DM76L97
and acrass the oOe to +70o e range for the DM86L97. All typicals are given for Vee = 5.0V and TA = 25°C.
Note 3: Only one output at a time should be shorted.
3·94
ordering instructions
10-13
Programming instructions for the DM76L97 or
DM86L97 are sol icited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data_ Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part_ This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.
14
15-18
19
20-23
24
25-28
29
Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched accord ing to the data card format shown.
30-33
34
35-38
39
40-43
supplementary ordering data
44
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.
45-48
49
50-51
data card format
52
Column
1- 3 Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
4
5- 7
8- 9
53-55
56
57-58
Punch a "-" (Minus sign)
59
Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.
Blank
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card_ H = highlevel output, L = low-level output, X =
output irrelevant.
Blank
Punch "Fl " , "L", or "X" for the second
set of outputs_
Blank
Punch "H", "L", or "X" for the third set
of outputs_
Blank
Punch "H", "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs_
Blank
Punch "H", "L", or "X" for the eighth
set of outputs_
Blank
Punch a right-justified integer representing
the current calendar day of the month_
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Blank
60-61
Punch "DM"
62-67
Punch the National Semiconductor part
number DM76L97 or DM86L97.
68-70
Blank
truth table
OUTPUTS
OPTION
ME,
MEz
1
0
1
0
Normal
X
High Impedance
X
1
High Impedance
1
1
Normal
0
X
High Impedance
X
0
High Impedance
2
3
1
0
Normal
X
1
High Impedance
0
X
High Impedance
x = Don't care
3-95
Series 54L/74L
DM76L99/DM86L99 TRI-STATE®low power 64-bit
random access memory
general description
The DM76Ui9/DM86L99 is a fully decoded 64-bit
RAM organized as 16 4-bit words. The memory
is addressed by applying a binary number to the
four Address inputs. After addressing, information may be either written into or read from the
memory. To write, both the Memory Enable
and the Write Enable inputs must be in the logical
"0" state. Information applied to the four Write
inputs will then be written into the addressed
location. To read information from the memory
the Memory Enable input must be in the logical
"0" state and the Write Enable input in the logical
"1" state. Information will be read as the complement of what was written into the memory.
When the Memory Enable input is in the logical
"1" state, the outputs will go to the highimpedance state. This allows up to 75 memories
to be connected to a common bus·line without
the use of pull-up resistors. All memories except
one are gated into the high-impedance while the
one selected memory exhibits the normally totempole low impedance output characteristics of
TTL.
features
• Series 54L/74L compatible
• Same pin-out as SN5489/SN7489, 3101,
MM5501
• Organized as 16 4-bit words
• Expandable to 1200 4-bit words without additional resistors
• Typical access from chip enable
50 ns
80 ns
• Typical access time
• Typical power dissipation
75mW
logic diagram
A,
~A'
A,
A,
~A'
A,
ADDRESS
INPUTS
A,
~A'
A,
A,
~A'
A,
D1
S,
D2
DATA
S,
INPUTS
D3
S,
D4
WE
ME
3-96
..
SENSE
OUTPUTS
absolute maximum ratings (Note 1)
operating conditions
MIN
Supply Voltage
7.0V
I nput Voltage
55V
Output Voltage
5.5V
Storage Temperature Range
-65'C to +150·C
Lead Temperature (Soldering, 10 seconds)
JOO'C
electrical characteristics (Notes 2 and 3)
PARAMETER
Supply Voltage (VCC)
DM76L99
DM86L99
MAX
'c
'c
Vee = 5.0V, TA = 25°C unless otherwise specified.
CD
CD
Temperature (TA)
DM76L99
DM86L99
CONDITIONS
-65
0
+125
+70
LIMITS
MIN
TYP
V
V
5.5
5.25
MAX
Vee = Max, VIN :::: 2 4V
Vee'" Max, VIN :: 5 5V
10
100
LOgical "0" Input Voltage (V,d
Vee::::: Mm
07
V
-180
JlA
-15
V
2.0
V
= Max, VIN :: 0 3V
= Mm, liN = -12 rnA
JlA
JlA
Input Clamp Voltage (Veo )
Vee
Logical "1" Output Voltage (V OH )
Vee = Min, lOUT:::: -10 rnA
Output Short CircUit Current (Note 4) (los)
Vee = Max. V OUT ;; OV
Logical "0" Output Voltage (VOl.)
DM76L99
DM86L99
Vee = M)n, lOUT
Vee:: Mm, lOUT
Supply Current ('cc)
Vee
Third State Output Current
Vee'" Max, VOUT
VOUT = 04V
Propagation Delay to a Logical "0" From
Address to Output (tpdO)
Vee =50V.TA = 2SoC
77
150
ns
Propagation Delay to a Logical "1" From
Address to Output (tpd1 )
Vee
25°C
51
120
ns
Delay From Memory Enable to High Impedance
State (From Logical"'" Level)(t1H)
Vee· 5.0V, T A • 25°e
18
27
ns
Delay From Memory Enable to High Impedance
State (From LOglcal "0" Level)(loH)
Vee = 50V, TA
=2SoC
37
56
ns
Delay From Memory Enable to Logical "1" Level
(From High Impedance State) (tH1 I
Vee = 50V, TA
=2SoC
30
50
ns
Delay From Memory Enable to Logical "0" Level
(From High Impedance State)(tHO)
Vee "'50V,TA "'2SoC
29
43
ns
24
=
5.0V. TA
V
-6.0
= 2 0 mA
= 3 2 mA
= Max
15
=
r-
UNITS
Vee = Min
Vee
CD
CD
......
c
3:
00
en
4.5
4.75
Loglca'''l'''nput Voltage (V 1H )
(I,d
r-
UNITS
Logical "1" Input Current flIH)
Logical "0" Input Current
c
3:
~
= 2 4V
-30
mA
03
0.4
V
V
19
mA
±4O
JlA
Write Enable Pulse Width
Vee'" SOV, TA '" 25°C
50
Setup Time, Data Input
Vee'" S.OV, TA ", 2SoC
0
Hold Time, Data Input
Vee· 5.0V, TA • 26'e
0
ns
Setup Time, Address
Vee - 5.0V, TA - 25'e
0
ns
D
ns
30
ns
Hold Time. Address
Vee - 5.0V, TA - 26'e
0
ns
Setup Time. Memory Enable
Vee = 5.0V, TA ", 26°~
0
ns
Hold Time, Memory Enable
Vee = 5.0V, T A = 26'e
0
Sense Recovery Time From Wnte Enable (taR)
Vee = 6.0V, TA = 25'e
110
165
ns
Disable Time From Wnte Enable (tiN1
Vee" 5.0V, TA = 2SoC
73
110
ns
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The
table of "Electncal Characteristics" provides conditions for actual device operation.
Nota 2: Unless otherwise specified mmlmax limits apply across the -56°C to +125°C temperature range for the DM76L99
and across the O°C to +70°C range for the DM86L99. All typicals are given for VCC'" 5.0V and TA .. 2~C.
Note 3: All currents into device pms shown as positive, out of device pms as negative. All voltages referenced to ground unless
otherwise noted. All values shown as max or min on absoluta value basiS.
Note 4: Only one output at a tune should be shorted.
3·97
connection diagram
Dual-In-Line Package
'I:"
I.. I.. I" I.. I..
11 I I
A,
A,
A,
D.
S.
I"
I
D,
s, C>-
-A,
.,
",
T T
1
9
I'
I'
D,
s,
I
T
I'
I'
D,
s,
T
I'
J:
I'
TOI'VIEW
truth table
MEMORY
ENABLE
WRITE
ENABLE
0
0
0
1
Write
HI-Z State
Read
Complement of Data
1
X
Hold
HI-Z State
OPERATION
OUTPUTS
Stored
,
3-98
In
Memory
c
s::
Series 54L/74L
00
00
...rN
DM88L12 TTL-MOS hex inverter I interface gate
general description
The DM88L 12 is a low power TTL to MOS hex
inverter element. The outputs may be "pulled up"
to +14V in the logical "1" state, thus providing
guaranteed interface between TTL and MOS logic
levels. The gate may also be operated with Vee
levels up to +14V without resistive pull·ups at the
outputs and still providing a guaranteed logical "1"
level of Vee - 2.2V With an output current of
-2001lA.
schematic and connection diagrams
Dual-I n-Line and Flat Package
".
".
"0
v"
o
GNO
TOP VIEW
UK
NGte ShownlsschemallCtureacilllMrter
typical applications
TTL Interface to MaS ROM
With Resistive Pull-Up
TTL Interface to MaS ROM
Without Resistive Pull-Up
NATlONAlMOSROM
IEXAMPLEMM5211
ac test circuits
Vcc ·14DV
,,.-~-.
switching time waveforms
Vcc'SV
Yf.".,
~
,
,
,
--,ov
-\3V--
·'00.
INPUT
r"'"'
FOAV"c· 14V
FORVcc ·50V
Figure 1
Figure 2
,'
I
,
OUTFLT~::
,
'
,
I
I
1..0-----;
1,
~,,=
10 ...
PW-l00n.
--- 50%---,
I
I
I
I,
I
!_---: :__ 1,..,
3·99
....
...I
N
co
CO
absolute maximum ratings
:E
Supply Voltage
Input Voltage
Output Voltage
Q
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
operating conditions
(Note 1)
15V
5.5V
15V
--65'e to +150'e
300'e
electrical characteristics
Supply Voltage
DM78L12
DM88L12
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
--65
0
125
70
'e
'e
MAX
UNITS
Temperature
DM78L12
DM88L12
(Note 2)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee = 14.0V
Vee"" Min
Logical "0" Input Voltage
Vee = 14.0V
Vee = Min
TYP
MIN
V
V
1.3
1.3
2.0
2.0
1.3
1.3
118
145
Vee=1.1V
07
0.7
V
V
V
V
V
12.0
150
Vee = 14.0V VIN "" O.7V
Y,N = 0.7V
Vee = Min
Vee = Min
Y'N = OV
lOUT = -200 JlA
lOUT = +200 JlA
lOUT = -5.0JlA
Logical "0" Output Voltage
Vee = 14.0V Y'N = 2.0V
Y'N = 2.0V
Vee = Min
lOUT"" 12 rnA
lOUT = 3.6 mA
Logical "1" Input Current
Vee = 14.0V Y'N = 2.4V
Y,N = 2.4V
Vee = Max
<1
<1
20
10
JlA
JlA
Vee = 14.0V Y'N = 5.5V
Y,N = 5.5V
Vee = Max
<1
<1
100
100
JlA
JlA
Logical "0" Input Current
Vee = 14.0V Y,N = O.4V
Vee = Max
Y'N = O.4V
-320
-100
-500
-180
JlA
JlA
Output Short CirCUit Current (Note 3)
Vee = 14.0V V OUT = OV
V OUT = OV
Vee = Max
-25
-50
-15
rnA
rnA
logical "1" Output Voltage
Supply Current - Logical "1"
(Each Inverter)
Logical "0"
0.5
02
-10
-3
-8
1.0
0.4
V
V
Vee = 14.0V Y'N = OV
Vee = Max
Y'N = OV
0.32
0.11
0.50
0.16
rnA
rnA
Vee = 14.0V Y,N = 5.25V
Vee = Max
Y'N = 5.25V
1.0
0.3
1.5
0.5
rnA
rnA
Propagation Delay to a Logical "0"
from I nput to Output, tpdO
Vee = 5.0V
TA = 25'e
See Figure 2
27
45
ns
Propagation Delay to a Logical "0"
from Input to Output, tpdO
Vee = 14.0V
See Figure 1
TA = 25'C
11
20
ns
Propagation Delay to a Logical "1"
from Input to Output, tpdl (Note 4)
Vee = 5.0V
TA = 25'e
See Figure 2
79
100
ns
Propagation Delay to a Loglcal"l"
from Input to Output, !Pdl
Vee = 14.0V
See Figure 1
TA = 25'e
34
55
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electncal Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature
range for the DM78L12 and across the o'e to +70'e range for the DM88L12. All tYPleals are
given for Vee = 5.0V and TA = 25'e, or for Vee = 14.0V and TA = 25'e.
Note 3: Only one output at a time should be shorted.
Note 4: t pd1 for Vce
3-100
MIN
= 5.0V is dependent upon the resistance and capacitance used.
...
Series 74S
REFERENCE
The following table references all Physical Dimension Drawings for the devices in this section. For Order
Numbers. see below. * Refer to the alpha·numerlcal index at the front of this catalog for complete device
title and function. Packages (pages I thru VI) are In the back of the catalog.
DATA SHEETS
Devices
DM74S00
DM74S03
DM74S04
DM74S05
DM74S10
DM74S11
DM74S15
DM74S20
DM74S22
DM74S40
DM74S64
DM74S65
DM74S74
DM74S86
DM74S112
DM74S113
DM74S114
DM74S135
DM74S140
DM74S151
DM74S251
DM74S153
DM74S253
DM74S157
DM74S257
DM74S158
DM74S258
Pg.
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4·1
4·1
4-1
4-1
4·1
4·1
4·5
4·1
4·1
4-1
4-5
4·1
4·7
4·7
4-7
4-7
4-7
4-7
4-7
4-7
PACKAGES
Molded DIP (N)
Fig.
Pg.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
5
3
5
5
5
5
5
5
5
5
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
Cavity DIP (D)(J)
Flat Pack (F)(W)
Fig.
Fig.
Pg.
Type
Pg.
Type
Metal Can (G)(H)
Fig.
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
*Order Numbers: use Device No. suffixed with package letter, i.e. DM74S00N.
4-i
(f)
...
CD
Series 74S
CD
en
series DM74S schottky-clamped transistor-transistor logic
general description
The gates, inverters, buffers and flip flops In the
DM74S series are ultra-high speed versions of the
similarly numbered devices in National's standard
series 54/74 family. They can be used in combination with series 54/74 circuits whenever the absolute
minimum propagation delays are required.
• Higher source and sink currents than standard
features
• Pin identical to lower speed devices
• Typical gate delay of 3 ns
•
TTL
•
Fanout of 10 series DM74S loads or 12 standard
series 54/74 loads
• Compatible with all series 54/74 families
19 mW typical power dissipation
connection diagrams (Dual-in-Line Package, Top Views)
DM74S00
DM74S03
DM74S05
DM74S04
tpd",3nstyp
lpd= 5nstyp
\.t""3 nstyp
tpel"
Po '" 19 mW tvp/Gate
Po =17 mW typ/Gate
Po '" 19 mW typ/Gate
Po " 17 mW typ!Gate
DM74S11
DM74S15
DM74S20
DM74S10
5nstyp
9
tpd=3nstyp
tpel"
Po
Po " 32 mW typ!Gate
=
19 mW typ/Gate
DM74S22
5 nstyp
DM74S64, DM74S65
IpcI"6nstyp
lpd"lllstyp
Po
Po" 19 mW typ!Gate
=
29 mW typ/Gate
DM74S74
DM74S112
7
GND
3 5 ns tvP. Po " 39 mW typ
Ipd"'5nstyp
DM14S64
Po " 11 mW typfGate
DM74S65 !pd" 5 ns tvp, Po " 36 mW tvp
DM74S113
fma~ "
125 MHz tvp Po = 75 mW typ/FF
CLOCK = High to low Transition
!peI =
fmax '" 90 MHz tvp Po" 75 mW typ/FF
fmax '" 125 MHz typ Po" 75 mW typ/FF
CLOCK = Low to High Transition
CLOCK'" High to Low TranSitIOn
DM74S114
f max "125MHztyp Po = 15mWtyp/FF
CLOCK::: High to low Transition
DM74S40, DM74S140
tpd
"4 nstyp
Po'" 41 mW typ/Gate
4-1
absolute maximum ratings
operating conditions
MIN
Supply Voltage, vee
Input Voltage
Interemitter Voltage
I/)
Q)
...
Operating
Free~Air
Temperature Range
Storage Temperature Range
Q)
7V
5.5V
5.5V
oOe to 70°C
~5°e to 150°C
Supply Voltage, Vee
Operating Free~Air
Temperature Range
(Note 1)
NOM
MAX
4.75
5.0
5.25
oOe
25°C
70°C
en
high speed gates, buffers and line drivers
dc electrical characteristics (Vee = +5V, TA = 25°C)
over operating free-air temperature range (unless otherwise noted)
SYMBOLS
I
PARAMETER
CONDITIONS (Note')
I
MIN
I
TVP (Note 2)
I
MAX
I UNIT
DM14S00. DM14S04, DM74S10. DM74S20
V'H
High-Level Input Voltage
V"
V,
Low·levellnput Voltage
Input Clamp Voltage
Vee = Mm, II = -18 rnA
VOH
Hlgh·Level Output Voltage
V cc =Mm,V 1L =08V,
IOH = -lmA
Voe
Low-Level Output Voltage
V cc ""Mm,V1H =2V,
toL -20rnA
05
I,
Input Current at Maximum Input Voltage
Vee Max, VI = 55V
1
mA
IH
50
-2
-100
"A
mA
2
V
08
-12
27
34
V
V
V
V
High-Level Input Current (Each Input)
Vee = Max, VI -=27V
I"
Low·Levellnput Current {Each Input)
Vee = Max, VI "'05V
'0'
Short,Clrcult Output Current (Note 3)
Vcc '" Max
ICCH
Supply Current, Hlgh·level Output (Average Per Gate)
Vec '" Max, AU Inputs at OV
25
4
mA
lecL
Supply Current, low·Level Output (Average Per Gate)
Vec "" Max, All Inputs at 5V
5
9
mA
-40
mA
DM74S03, DM74S05, DM74S22
V'H
Hlgh·level Input Voltage
V"
V,
low·Level Input Voltage
Input Clamp Voltage
Vec '" Mm, II '" -18 mA
VOH
Hlgh·level Output Current
Vee "'Min, VIL "'DaV,
VOH "'55V
V
2
08
-12
250
V
V
"A
Voe
low· level Output Voltage
Vee = Mm, VIH = 2V,
IOL"'2DmA
I,
Input Current at Maximum Input Voltage
V ec =Max,VI =55V
IH
Hlgh.Levellnput Current (Each Input)
Vce = Max, VI =27V
I"
low·Level Input Current (Each Input)
Vce "'Max, VI =D5V
ICCH
Supply Current, High-level Output (Average Per Gate)
Vec = Max, All Inputs at DV
15
33
mA
Iccl.
Supply Current, low-Level Output (Average Per Gate)
Vec = Max, All Inputs at 5V
5
9
mA
05
1
50
-2
V
mA
"A
mA
DM74S40, DM74S140
V'H
High-level Input Voltage
V"
V,
Low-Level Input Voltage
VOH
Input Clamp Voltage
Vee =MIn,V IL =08V,
IOH=-3mA
High-level Output Voltage
I,
Input Current at MaXimum Input Voltage
Vec = MilX, VI =55V
High Level Input Current (Each Inputl
Vce = Max, VI = 2 7V
I"
Low-Level Input Current (Each Input)
Vec =Max, VI =05V
'0'
Short-Circuit Output Current
Vec = Max
lecH
Supply Current, High-Level Output (Average Per Gate)
Vee = Max, All Inputs at OV
lecL
Supply Current, Low-level Output (Average Per Gate)
Vee = Max, All Inputs at 5V
ac switching characteristics
SYMBOLS
PARAMETER
27
Vce = Min, VI =05V,
(R o = 50 n to GNO, DM74S140)
Vce = Mm, VIH = 2V,
IOL=60mA
low-Level Output Voltage
(Vee
I
V
08
-12
Vee = Mm, II = -18 mA
Voe
"H
V
2
V
34
V
V
2
05
V
1
mA
100
-4
"A
mA
-225
mA
5
9
mA
125
22
mA
UNIT
-50
= +5V, TA = 25°C)
H
MIN
TYP (Note 2)
MAX
CL = 15pF, RL =280n
CL = 50pF, RL = 280 n
2
3
45
45
CI,. = 15pF, RL "'280n
CL =50pF,R L =280n
2
3
5
5
CI,.=15pF,R L -2BOn
CL "'50pF,R L =280n
2
2
5
75
45
7
75
CL =15pF,R L =280n
CL =50pF,R L =280n
CL =50pF,R L =93D:
CL =:.150pF, RL "'93n
2
CL =50pF,R L =93n
CI. = 150pF, RL =93n
2
CONDITIONS (Note
DM74S00, OM74S04, DM74S10, DM74S20
tpLH
tpHI.
Propagation Delay Time, Low-to-Hlgh-Level Output
Propagation Delay Time, High to-Low-Level Output
DM74S03, DM74S05, OM74S22
tpHL
tpHI.
I
Propagation Delay Time, low-to-Hlgh-Level Output
Propagation Delay Time, Hlgh-to-Low-Level Output
I
7
"'
"'
"'
"'
OM74S40, OM74S140
tpHI.
Propagation Delay Time, Low-to-Hlgh-Level Output
tpHL
Propagation Delay Time, Hlgh-to-Low-Level Output
I
4
6
4
6
65
65
"'
"'
"'
"'
Note 1: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 2: All typical values are at Vee 0= 5V, TA = 2SoC.
Note 3: Not more than one output should be shorted at a time, and duration of the short-CIrCUit test should not exceed one second.
4-2
VJ
ultra high speed schottky TTL flip-flops
dc electrical characteristics (Vee = +5V, TA = 25°C)
SYMBOLS I
PARAMETER
I
CONDITIONS (Note 11
...
CD
I
MIN
I TYP (Note 2)
MAX
I
CD
III
UNIT
DM74S74
V'H
Hlgh·Level Input Voltage
V"
V,
Low-Level Input Voltage
Input Clamp Voltage
Vee'" Mm, II '" -18 rnA
VOH
High-Level Output Voltage
Vee'" Mm, V 1H '" 2V,
V 1L =08,l oH =-1 rnA
V
08
-, 2
Low-level Output Voltage
Vee'" Min, V 1H '" 2V,
V 1L =08, IOL '" 20 rnA
Input Current at MaXimum Input Voltage
Vee = Max, VI = 5 5V
"H
High-level Input Current
Vee'" Max,
VI = 2 7V
D Input
Clock or Preset
Clear
I"
Low-Level Input Current
Vee'" Max,
VI =- 0 5V
D Input
Clock or Preset
;';Iear
'0'
Short-CircUIt Output Current (Note 3)
Vee = Max
Supply Current
Vee'" Max, (Note 4)
Va'
Icc
V
34
27
V
05
mA
50
'00
'50
-2
-4
-6
-40
MA
mA
-100
mA
50
mA
30
DM74S112
V'H
High-level Input Voltage
V"
V,
Low-level Input Voltage
Input Clamp Voltage
Vee"" Mm, II "·-18 mA
VOH
High-Level Output Voltage
Vee'" Mm, V IH '" 2V,
V IL "'D8V, IOH =-1 mA
Va'
"H
V
08
-, 2
27
Low-Level Output Voltage
Vee'" Mm, V IH = 2V,
V 1L =08V,l oL =20mA
Input Current at MaXimum Input Voltage
Vee'" Max, VI '" 5 5V
High-Level Input Current
Vee'" Max,
VI = 2 7V
Jar K Input
Clock, Preset, or Clear
J or K Input
Clock
Preset or Clear
I"
Low-Level Input Current
Vee'" Max,
VI = 5V
'0,
Short-CircUit Output Current (Note 3)
Vee'" Max,
Icc
Supply Current
Vee = Max, (Note 4)
a
PARAMETER
V
mA
50
'00
-, 6
-4
-7
-40
MA
mA
-100
mA
50
mA
30
DM74S114
UNIT
CONDITIONS
MIN
V'H
Hlgh·Levellnput Voltage
V"
V,
Low-Level Input Voltage
Input Clamp Voltage
Vec = Min, I, '" -18 mA
VOH
High-Level Output Voltage
Vee = Min, V 1H = 2V,
V IL =08V,l oH "'-lmA
Va'
Low·Level Output Voltage
Vee = Min, V IH = 2V,
VIL"'08V,loL=20mA
Input Current at MaXimum Input Voltage
Vee "'Max,V I =55V
"H
High-Level Input Current
Vee"'"' Max,
VI = 2 7V
Jar K Input
Clock
Preset
Clear
I"
Low-Level Input Current
Vcc '" Max,
VI'" 0 5V
J or K Input
Clock
Preset
Clear
10'
Short Circuit Output Current (Note 3}
Vcc '" Max
Icc
Supply Current
Vee'" Max, (Note 4}
Note 1:
Note 2:
Note 3:
Note 4:
V
05
DM74S113
SYMBOLS
V
34
TVP
MAX
TVP
MIN
MAX
V
08
-, 2
27
34
08
-, 2
27
V
34
V
05
05
V
mA
50
'00
100
-, 6
-4
-7
-40
-100
30
-40
50
30
50
200
100
200
MA
-, 6
-8
-7
-'4
mA
-100
mA
50
mA
For conditions shown as Min or Max, use the appropnate value spt:!clfled under recommended operating conditions.
All tYPical values are at Vce '" 5V, T A = 25 D C
Not more than one output should be shorted at a time, and dUratIOn of the short-CirCUit test should not exceed one second.
Ice IS measured With outputS open, clock grounded, and J, K, preset, and clear at 4 5V
ac switching characteristics
PARAMETER
SYMBOLS I
(Vee
= +5V, TA = 25°C)
CONDITIONS (Note 1)
MIN
TVP (Note 2)
I
MAX
I
UNIT
DM74S74
MaXImum Clock Frequency
tpLH
75
110
80
'25
Propagation Delay Time, Low·to-Hlgh·Level OutpUI, From
Clear or Preset
Propagation Delay Time. High-to-Low-Level Output, From
Clear or Preset {Clock Low}
tpLH
tpHI.-
Propagation Delay TIme, Low-to Hlgh·Level Output, From
Clock
Propagation Delay Time, Hlgh-to-low-Level Output, From
Clock
DM74S112, DM74S113, DM74S114
MaXimum Clock Frequency
tpLH
Propagation Delay Time, Low-to·Hlgh-Level Output
From Clear or Preset
Propagation Delay Time, Hlgh·to-Low·Level Output,
From Clear or Preset
tpLH
PropagatIOn Delay Time, Low-to-Hlgh-Level Output.
From Clock
tpHL
Propagation Delay Time, High to-Low· Level Output,
From Clock
4-3
ultra high speed AND/AND-OR-INVERT gates
dc electrical characteristics (Vee = +5V, TA = 25°C)
DM74S11
SYMBOLS
CONDITION
PARAMETER
DM74S16
UNIT
MIN
TVP
MAX
MIN
TVP
MAX
Hlgh·Level Input Voltage
Low-Level Input Voltage
08
Input Clamp Voltage
08
-,2
-, 2
Vee'" Min, I. =-18 rnA
V
V
V
Vee'" Mm,
Hlgh·Level Output Voltage
V 1H = 2V.
Hlgh·Level Output Current
Vcc .. Mtn,V 1H
27
IOH =-1 rnA
'OH
..
Vee'" Min, V 1L = 0 BV,
IOL=20mA
Input Current at Maximum Input Voltage
Vee = Max, VI'" 5 5V
"H
High-level Input Current (Each Input)
Vee" Max, VI = 2 7V
Low·levellnput Current (Each Input)
Vee = Max, VI =05V
'os
Short-CIrcUIt Output Current (Note 3)
Vee'" Max
Supply Current High-Level Output
(Average Per Gate)
Vee = Max, All Inputs at 5V
Supply Current. Low-Level Output
(Average Per Gatel
Vee'" Max, All Inputs at OV
ICCH
leeL
34
2V.
250
VOH ""56V
low-Level Output Voltage
'll
V
05
05
PARAMETER
50
-2
50
-2
35
45
'4
MIN
65
'4
mA
UNIT
TYP
MAX
MIN
TVP
MAX
V
Low·Levellnput Voltage
los
Input Clamp Voltage
Vec'" Mm, I, =-18 rnA
H,gh·Level Output Voltage
Vee'" Min, V ,H ... 0 8V,
10H _-I mA
H,gh·Level Output Current
Vcc = Mm, V
VoH "'55V
Low· Level Output Voltaga
Vee'" Mm, V'I- =- 2V,
101- =20mA
Input Current at Maximum Input Voltage
Vee'" Max, V, =55V
HIgh·Levellnput Current (Each Input)
Vee'" Max, V," 2 7V
Low· Level Input Current (Each Input)
Vee "Max, V, =05V
Short,C,rcult Output Current (Note 3)
Vee'" Max
Supply Current, Hlgh·LeYflI Output
Vee'" Max, (Note 5)
ICCI-
Supply Current, Low·Level Output
VCC
a
ac switching characteristics
27
08
08
V
-, 2
-'2
V
34
V
,H '" 0 av,
ICCH
250
05
05
PARAMETER
50
-2
12.5
16
a5
11
85
'6
DM74S16
UNIT
MIN
TVP
PropagatIon Delay TIme, Low-to High
Level Output
CL =15pF,A L =280n
CL =50 pF, AI.. =280 n
25
45
6
PropagatIon Delay Time, High to Low·
Level Output
CL =15pF,A L =280n
CL "'50pF,R L "'28012
25
5
75
MAX
MIN
25
75
TVP
55
85
MAX
85
25
DM74S65
UNIT
CONDITIONS
Propagation Delay T,"\8, Low·to·Hlgh
Level Output
CL =15pF,R L "'280n
CL =50pF,R L "'280S2
Propagation Delay Time, Hlgh-to-Low
Level Output
CL '" 15pF. RL "'280n
CL =50pF,R L =280n
TVP
MAX
35
5
35
55
For condItIons shown as M,n or Max, use the appropriate value specIfIed under recommended operatmg condItIons
All typIcal values are at Vee = 5V, T A'" 2SoC
Not more than one output should be shorted at a time, and duratIon of the short-CIrcUit test should not exceed one second
ICC IS measured With outputs open, clock grounded, and J, K, preset, and clear at 4 5V
ICCH IS measured With all inPUts grounded, and the outputs open
'CCl IS measured WIth all inputs of one gata 115V, the remaining Inputs grounded, and the outputs open
switching time waveforms
Nott'YMpllll8"..'_Ioa.thefDII_..... n ..."rt'.. V.. llj·3VV.. IOj:0Y.I,:1o·2& ..
PAR· 1 MHI.O.ty CycI'~&"',ZouT~ 511'
Neu2 CL"lIlud8lp,alrlllldJ'gClplCrt8...
4-4
"A
mA
mA
mA
mA
(Vee = +5V, TA = 25°C)
MIN
Note 1
Note 2
Note 3
Nate 4
Nate 6.
Nate 6
50
CONDITION
PARAMETER
V
-2
-100
-40
Max, (Note 6)
DM74S64
SYMBOLS
"A
mA
DM74S11
SYMBOLS
mA
DM74S65
H,gh·Levellnput Voltage
I,"
"L
"A
mA
mA
-'00
-40
CONDITIONS
V
mA
OM74S64
SYMBOLS
"A
MIN
TVP
55
55
MAX
75
55
65
85
Series 74S
DM74S86(SN74S86) Schottky quad EXCLUSIVE-OR gate
DM74S135{SN74S135) Schottky quad
EXCLUSIVE-OR/NOR gate
general description
features
The DM74S86 and DM74S135 are quad-two input
EXCLUSIVE-OR gates designed for ultra high
speed, high performance systems. Both devices
are completely compatible with series 74, series
74H, series 74L, other series 74S devices and most
DTL.
•
Fully Compatible with Most TTL and TTL
MSI Circuits
•
Fully Schottky Clamping Reduces Delay Times:
DM74S86
7 ns typo
DM74S135
8 ns typo
The DM74S86 is functionally identical to the
DM7486 and can be used to upgrade existing
designs with a minimum of logic changes.
The DM74S135 can operate as an EXCLUSIVE-OR
gate (with C input LOW) or as an EXCLUSIVE
NOR gate (C input HIGH).
logic and connection diagrams
lA
DM74S86
DM74S135
Dual-In-Line Package
Dual-In-Line Package
18
2B
2A
IV
2V
GNO
lA
TOP VIEW
H
H
L
H
L
H
3A
3V
lY
lC,21:
2A
2B
2Y
GND
DM74S135
OUTPUT
9~1{L'.;.;..___ \I'Nl l
OUTPUT
INPUTS
y
A
B
C
y
L
H
H
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L
L
H
H
H
H
L
H.
H
L
H
L
L
H
H = High Level, L'" low level
38
switching time waveforms
DM74S86
L
L
3C,41:
POSITIVE lOGIC WITH C lOW, y,. AmB" AB + AI
WITH C HIGH, Y =~=AB+1Ur
A8 + AS
function tables
AS""""
4Y
TOPVIEW
POSITIVE lOGIC Y'" A B"
INPUTS
18
4A
-
\/"010)
VOUTIII
tp"L(lIIegGoongOutput)
Not. 1 Tbe p"l.. g_.e,atn, ~.. lh. foiIOWlf>g cb.,ac!""t"" II'NO) "311 V'N(QI
PRR ~ 1 MHz. Duty Cycle" iII% ZOUT" 50')
1110102 Cl,oelude'p,obeand,'gcapac.'ance
Oil, I, " to" 2 ~ "5,
4-5
ID
...
(W)
absolute maximum ratings
(I)
~
.....
:E
Supply Voltage (Note 1)
Input Voltage
Q
operating conditions
7V
5.5V
Supply Voltage, V CC
oOe to JOoe
From Each Output, N
MIN
TYP
4.75
5
MAX
UNITS
V
5.25
Normalized Fan-Out
Operating Free-Air Temperature Range'
DM74S86, DM74S135 CirCUitS
Storage Temperature Range
High Logi c Level
Low LogiC Level
-65°C to 150°C
20
10
°c
70
0
Temperature, T A
electrical cha racte ristics over recommended operating free-air temperature range (unless otherwise noted)
SYMBOL
CONDITIONS (NOTE 2)
PARAMETER
V'H
High-Level Input Voltage
V,c
Low-Level Input Voltage
V,
V OH
MIN
TYP(NOTE 3)
MAX
Input Clamp Voltage
Vee'" Mm, II'" -18 mA
High-Level Output Voltage
Vee'" Min, V 1H = 2V,
V 1L - 08V,l oH ::=-1 rnA
Vee = Min, V 1H
:::
UNITS
V
2
2.7
0.8
V
-1.2
V
V
3.4
2V,
0.5
V
VOL
Low-Level Output Voltage
I,
Input Current at MaXimum
Input Voltage
Vee'" Max, VI'" 5 5V
1
I'H
High-Level Input Current
V ee "'Max,V I =27V
50
~A
I'L
Low-Level Input Current
Vee'" Max, V I '" 0 5V
-2
rnA
los
Icc
V 1L ::: O.8V, 'OL '" 20 rnA
Short-Circuit Output Current
-40
Vee'" Max
(Note 4)
DM74S86
DM74S135
Supply Current
-100
rnA
75
99
rnA
rnA
50
65
Vee'" Max (Note 5)
rnA
Note 1: All voltage values are with respect to network ground terminal,
Note 2: For con-dldons shown as Mm or Max, use the appropriate value speCified under recommended operating conditions
for the applicable device type,
Note 3: All typical values are at Vce = 5V, T A = 25°C.
Note 4: Not more than one output should be shorted at a time, and duration of the short-cIrcuit test should not exceed one
second.
Note 5: IcC IS measured with the mputs grounded and the outputs open_
switching characteristics
PARAMETER'
FROM
!INPUT)
CONDITIONS
12
135
ns
10
6.5
15
10
ns
8.5
7
12
II
ns
ns
7
65
105
10
8
9
B or A = L, C = H
C L '" 15 pF
RL " 280r!
B or A = H, C = H
85
tPLH
tpHL
C
A"B
8
9.5
12
145
tpLH
tpHL
C
A*B
7.5
8
115
12
• tpLH;:;; propagation delay time, low-to-hlgh-Ievel output.
tpHl.;:;: propagation delav time, hlgh-to-Iow-Ievel output.
4-6
ns
B or A = H, C = L **
Aor B
**
References to C Input are applicable to DM74S135 only_
UNITS
13
15
II
tpLH
tpHL
AorB
DM74S135
TYP
MAX
**
B or A = L, C = L
AorB
MIN
105
10
Aor B
tpLH
tpHL
DM74S86
TYP
MAX
7
65
tpLH
tpHL
tpLH
tpHL
MIN
ns
en
..,CD
Series 74S
CD
en
series DM74S schottky-clamped mu Itiplexers
general description
These devices in the DM74S series are Schottky·
clamped, high performance, data selectors/multi'
plexers designed for use in very·high·speed data
routing applications. These multiplexers select one
of the "N" data sources when so directed by the
binary address inputs. Each multiplexer is available
with standard two·state outputs or National's
TRI·STATE® outputs.
The DM74S151, DM74S153, DM74S157 and
DM74S158 have Schottky TTL totem·pole out·
puts. The strobe inputs force all outputs low
(complement outputs high) to permit further
logic expanSion,
The DM74S251, DM74S253, DM74S257 and
DM74S258 have Schottky TTL TRI·STATE out·
puts. The strobe inputs force the outputs to a high
impedance state permitting N·bit (paralleled) data
selectors with up to 129 sources connected to a
data bus line. To minimize the possibility that
two outputs will attempt to take a common bus to
opposite logic levels, the output·enable circuitry
is designed so that the output disable time is faster
than the output enables,
features
•
Schottky clamped for Significant reduction in
delay times
•
High speed selection for one of eight, four or
two data sources
•
High fan·out, low impedance totem·pole outputs
•
Strobe/output control. Line provided for ex·
pansion to N lines
•
TRI·STATE outputs, Interface directly with
System Bus
•
Fully compatible with most TTL and DTL
circuits
connection diagrams
DM74S153/DM74S253
DM74S1511DM74SZ51
DM74S158/DM74S258
DM74S157/DM74S257
'h"
(OUTPUT
INPUTS
CONTROLI
,--......,
STROBE
100
400
101
'---...-'
(OUTPUT
INPUTS
. . - - - . - . . OUTPUT
laO
301
)Y
401
Vee
1Y
OUTl'UT
iNPUTS
INPUTS
.------.,
CONTROL)~
400
100
101
1Y
,-"OUTf'UT
--......--..
INPUTS
INPUTS
OUTi'lIT
401
"
200
201
2Y
~omUT
ordering information
All DM74S Series multiplexers are available
In
the 16·lead Molded Dual·ln·Line (N) package.
Order all DM74S Series deVices by their specific number, and add the package designation letter (N).
4·7
operating conditions
absolute maximum ratings
over operating free-air temperature range
(unless otherwise noted)
...CD
7V
5.5V
Supply Voltage, Vee
Input Voltage
Operating Free-air Temperature Range
en
Storage Temperature Range
-65°e to +150o e
V!H
V1L
v,
I,"
Icc
(Vee
=
+5V, TA
=
NOM
4.75
5
MAX UNITS
5.25
V
-1.0
rnA
20
rnA
70
°e
25°C)
TV'
MIN
CONDITIONS (Note 1)
PARAMETER
MIN
Current,IOL
Operating Free-Air
Temperature, T A
oOe to +70o e
dc electrical characteristics
SYMBOL
Supply Voltage, Vee
High-Level Output
Current, IOH
Low- Level Output
(Note 2)
MAX
UNITS
HIgh level Input Voltage
I..,ow-Ievellnput Voltage
Input Clamp Voltage
Vee'" Min, I,
High-level Output Voltage
Vee = Mm, V 1H = 2V. V 1L = 0 BV
10 )-1 = Max
=
-18 rnA
34
32
27
24
DM74S151/153/157/158
DM74S251f253i257/258
Low-level Output Voltage
Vee =Mm, V!H =2V, V. L =GaV, tOL =20mA
Off-state!Hlgh-lmpedancestatelOutputCurrent
Vee = Mal(, Vo = 2 7V toVo = 04V
Input Current at Max
Input Voltage
Vcc=Max V.=55V
High-level Input Current
Vcc =Ma)(,V,=27V
50
pA
Low-level Input Current
Vee =Max, VI =Q5V
-2
rnA
Short-cIrcUit Output Current
Vee = Max
~100
rnA
Supply Current
Vec
Vcc
Vec
Vcc
Vcc
Vcc
Vce
Vec
70
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
-40
Max, All Inputs at +4 5V
= Max, All Inputs GND
= Max, AllinputsGND
= Max, All Inputs Open
Max, AlIlnputs Open
=
50
pA
rnA
= Max, All Inputs at +4 5V
=
-50
= Max, All Inputs Open
= Max, All Inputs Open
45
55
45
55
DM74S151
OM74S251
OM74S153
DM74S253
DM74S157
OM74S257
OM74St58
OM74S258
85
70
70
78
99
61
50
64
39
56
.7
Note l' For conditions shown as min or max, use the appropriate value speCIfied under recommended operating conditions
for the applicable deVice type
Note 2: AU typical values are at Vee = 5V, T A = 25°e
Note 3: Not more than one output should be shorted at a time and duration of the short CirCUit test should not exceed one
second
ac switching characteristics
(Vee = +5V, T A
=
25°C)
OM74S151/DM74S251
SYMBOL
FROM
(INPUT)
PARAMETER
TEST
CONDITIONS
OM74S151
MIN
OM75S251
TYP
MAX
12
18
MIN
TYP
I.
MAX
Propagation Delay Time,
Low-to-Hlgh-LeveIOutput
A, B, or C
tpHL
Propagation Delay Time,
High-to Low Level Output
A, B,or C
i4levels)
tpLtl
Propagation Delay Time,
Low-to-Hlgh Level Output
A, a,or C
i3levels}
w
tpHI.
Propagation Delay Time,
Hlgh-to-Low Level Output
A, B, or C
13 levels}
w
tpLH
Propagation Delay Time,
Low-to-Hlgh-LeveIOutput
Data
12
12
tPHl
Propagation Delay Tune,
Hlgh-to-Low-LeveIOutput
Data
12
12
tpLH
Propagation Delay Time,
Low-to-Hlgh-LeveIOutput
Data
w
w
tplH
(4 levels)
12
10
CL = 15 pF,
RI. = 280n,
INote 1}
15
45
13
195
10
15
135
45
45
Propagation Delay Time,
Hlghto-low-LeveIOutput
Data
tPLH
Propagation Delay Time,
Low to-High level Output
Strobe
"
tpHl
Propagation Delay Time,
High to Low-Level Output
Strobe
12
tpl..H
Propagation Delay Time,
Low-to-Hlgh-LeveIOutput
Strobe
w
tpHl
PropagatIOn Delay Time,
High-to Low Level Output
Strobe
w
',"
Output Enable Time to
High Level
Output Control
Output Enable Time to
Low Level
Output Control
Output Enable Time to
High Level
Output Control
w
Output Enable Tim!! to
Low level
Output Control
w
Note 1_ See load Circuits and waveforms on page 4 of thiS data sheet
I.
12
135
tpHl
""
4-8
TO
(OUTPUT)
45
165
I.
13
85
CI.
= 50pF,
RI. = 280n,
(Note H
12
13
195
14
21
13
195
14
21
UNITS
en
...
CD
ac switching characteristics (con't)
CD
III
DM74S151/DM74S251
SYMBOL
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
t<,
Output Disable Tm"le From
High level
QutputControl
t"
Output Disable Time
Output Control
TEST
CONDITIONS
DM74S151
MIN
DM75S251
TY.
MAX
MIN
TY'
MAX
"
8'
...,s:
~
14
C L =5 pF,
From Low level
C
UNITS
en
RL '" 280n,
t<,
Output Disable Time
From High Level
Output Control
W
t"
Output Disable Time
from low Level
Output Control
W
(Note
n
"
8'
14
DM74S153/DM74S253
FROM
(INPUT)
PARAMETER
SYMBOL
TO
{OUTPUTI
TEST
CONDITIONS
DM74S153
DM74S253
TY'
MAX
"'
Select
t pLH
Propagation Delay Time,
low to High Level Output
Data
t pHL
Propagation Delay Time,
High to Low level Output
Data
t plH
Propagation Delay Time,
Low to High level Output
Select
MIN
CL " 15pF,
RL "280n,
MIN
TY'
MAX
18
"'
18
12
18
12
18
10
15
(Note 1)
t pHL
Propagallon Delay Time,
UNITS
High to Low Level Output
t pLH
Propagation Delay Time,
Low to High Level Output
Strobe
t pHL
Propagation Delay Time,
High to Low Level Output
Strobe
t,"
Output Enable Time to
High Level
Output Control
t"
Output Enable Time to
Low Level
Output Control
t<,
Output Disable Time
From High Level
Output Control
t"
Output Disable Time
From Low Level
Output Control
13'
C L = 50 pF,
RL = 280rz,
(Note 1)
13
19'
14
21
55
CL = 5pF,
RL = 280£2,
(Note 1)
8'
14
DM74S157/DM74S257
SYMBOL
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST
CONDITIONS
DM74S257
DM74S157
MIN
TY'
MAX
MIN
TY'
75
t pLH
PropagatIOn Delay Time,
Low to High Level Output
Data
t pHL
Propagation Delay Time,
High-to Low Le~el Output
Data
tpLH
Propagation Delay Time,
Low to High Level Output
Select
t pHL
Propagation Delay Time,
High to Low Level Output
Select
9'
15
tPLH
Propagation Delay Time,
Low to High Level Output
Strobe
85
12'
t pHL
Propagation Delay Time,
High to Low Level Output
Strobe
75
12
t,"
Output Enable Time to
High Level
Output Control
t"
Output Enable Time to
low Level
Output Control
t",
Output Disable Time
From High Level
Output Control
t"
Output Disable Time
From Low Level
Output Control
4'
CL '" 15 pF,
RL = 280H,
(Note 1)
9'
MAX
~
UNITS
75
65
4'
8,
15
CL '" 50 pF,
RL = 280n,
(Note 1)
6'
15
13
19'
14
21
55
C L = 5pF,
RL = 280n,
(Note 1)
8'
14
DM74S158/DM74S258
SYMBOL
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
Data
Any
PrOpagation Delay Time,
High to low level Output
Data
Ac,
tPLH
Propagation Delay Time,
Low to H,gh level Output
Select
Acy
tpHL
Propagation Delay T,me,
High to low Level Output
Select
AllY
tpLH
Propagation Delay T>me,
LowtoHlgh Level Output
tpHL
TEST
CONDITIONS
C L = 15pF,
RL = 28aH
INote 1)
DM74S158
MIN
TY'
DM74S258
MAX
MIN
TY'
12
12
MAX
UNITS
12
75
12
Note 1 See load circuits and waveforms on page 4 of thiS data sheet
4-9
ac switching characteristics (con't)
DM74S158/DM74S258
FROM
(INPUT)
PARAMETER
SYMBOL
1/1
DM74S1S8
TO
TEST
(OUTPUT)
CONDITIONS
MIN
TY.
DM74S258
MAX
MIN
...
Strobe
Aoy
tpHL
Propagation Delay Time,
Hlgh-ta-Low Level Output
Strobe
Aoy
t,"
Output Enable Time to
Output Control
Aoy
t"
Output Enable Tmw to
Output Control
Aoy
t",
Output Disable Time
Output Control
Aoy
tPL.H
Propagation Delay Time,
Low-to-Hlgh-LeveIOutput
Q)
en
Cl
'"
15 pF,
.5
12
7
12
MAX
TY'
Q)
UNITS
"'
RL '" 280n,
High Level
(Note 1)
"'
CL "'50pF,
RL "'280n.
(Note 1)
13
'95
"'
14
21
"'
Low Level
From High Level
Output Control
Output Disable Time
t"
Aoy
55
CL =5pF.
RL- = 280n,
.5
"'
,.
9
(Note 1}
"'
From Low Level
Note 1: See load CirCUits and waveforms on page 4 of this data sheet
ac load circuits
voltage waveforms
Propagation Delay Times
Bi-state Totem-pole Outputs
u"
POIfiT
---il
IV
~v
TRI-STATE Outputs
,;>",
INPUT - - . /
TEST
POINT
Y"
C.
"'·"1 ."
~
fROM OUTPUT
UNDtRTEST
UNDEATE5T
OUT OF PHASE
OUTPUT
'"
,~:'"
'"
IN PHAse
OUTPUT
f"I"
"'
~'"~--:l
r-""
Y"
Y"
~
15V
Vo
"
15V
---Y"
INote2)
(NUle2)
II"~::::\,~"
(15)
"
"
~
~
"' '"
" '"
"
"'
IIlI
1121
'"
'" '"
" '"
r= ~
('
B
1141
~
IIlI
112)
~~
111)
~,
110)
~. ,
C
'"
,
1510UTPUTY
en
...
CD
logic diagrams (con't)
CD
(II
DM745253
DM745153
"'" [:::0"'-'01-------f'f'FL..)
'" 0"''------+11-+'1='1-.)
"",,{
'" o"''-----;:===~~FL.)
:
'"
D""l:::::==:~~::
. , { o-!!"-----+I-++-"
"'o-!!"-----+I-++.........
2O'o-!!"------j-.I---...f:t==__
OUTPUT
COriTROl
DM745257
DM745157
"'
OUTPUT
CONTROL
0'
.,'"
(15)
'"
'"
.,
(11)
(lOJ
(11)
(14)
(13)
'"
91
(14)
(15)
'"
DM745158
DM745258
4-11
truth tables
DM74S151/DM74S251
OUTPUTS
INPUTS
UI
Q)
...
SELECT
Q)
en
OM74S151
DATA
OM74S251
STROBE
OUTPUT
CONTROL
DO
01
02
03
0'
OS
06
07
V
W
v
W
H
X
X
X
X
X
X
X
X
L
H
Z
Z
H
C
•
A
x
x
X
L
L
L
L
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
H
X
X
X
X
X
X
X
H
L
H
L
L
L
H
L
X
L
X
X
X
X
X
X
L
H
L
H
L
L
H
L
H
X
X
X
X
X
X
H
L
H
L
L
L
H
L
X
L
X
X
X
X
X
L
H
L
H
H
L
L
L
X
X
X
X
X
X
L
L
X
X
H
H
X
X
L
H
X
L
H
L
L
H
L
H
L
H
H
H
X
X
X
L
H
L
L
L
X
X
X
X
L
X
L
H
L
H
H
L
L
L
X
X
X
H
X
X
H
L
H
L
X
X
X
X
X
X
X
X
X
X
H
H
L
L
X
X
X
X
X
X
L
X
X
H
X
L
X
X
X
X
L
H
L
H
L
H
H
H
L
L
L
H
H
H
H
H
H
L
H
H
H
X
X
H
X
X
X
X
X
X
X
L
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
L
H
L
H
X
H
L
H
L
X
X
L
H
L
H
H
L
H
L
L
L
H
L
H
H
H
L
H
L
DM74S153/DM74S253
STROBE
OUTPUT
CONTROL
SELECT
INPUTS
OUTPUTS
DATA
INPUTS
DM74S153
DM74S253
V
•
A
G
CO
Cl
C2
C3
V
X
X
H
X
X
X
X
L
Z
L
L
L
L
X
X
X
L
L
L
L
L
H
X
X
X
H
H
L
L
H
L
X
L
X
X
H
X
X
X
L
X
X
L
H
H
L
L
L
L
L
H
H
X
X
X
X
X
X
H
X
L
L
H
H
H
H
H
L
L
H
H
X
X
X
H
L
L
L
L
H
H
DM74S157/DM74S257,DM74S158/DM74S258
SELECT
INPUT
STROBe
OUTPUT
CONTROL
X
L
•
DM74S157
OM74S158
DM74S257
H
L
X
X
L
H
Z
Z
L
X
H
L
H
H
H
L
L
L
H
X
L
H
L
X
H
L
H " hIgh level, L
4-12
OUTPUT V
DATA
A
~
X
L
H
low level, X - ",elevan\, Z - hIgh Impedance (of!)
DM74S258
H
L
H
L
H
L
H
L
L
.
(J)
CD
Series 930
CD
III
CD
W
REFERENCE
o
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below. * Refer to the alpha·numerical index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
Devices
DM930
DM932
DM933
DM935
DM936
DM937
DM944
DM945
DM946
DM948
DM949
DM957
DM958
DM961
DM962
DM963
DM1800
DM1801
DM9093
DM9094
DM9097
DM9099
Pg.
5-3
5-5
5-5
5-3
5-3
5-3
5-5
5-7
5-3
5-7
5-3
5-5
5-5
5-3
5-3
5-3
5-3
5-3
5-8
5-8
5-8
5-8
PACKAGES
Molded DIP (N)
Fig.
Pg.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
Cavity DIP (D)(J)
Fig.
Pg.
Type
Flat Pack (F)(W)
Fig.
Pg.
Type
Metal Can (G)(H)
Fig.
Pg.
Type
WAVE·
FORMS
Fig.
Pg.
5-4
5-6
5-6
5-4
5-4
5-4
5-6
5-9
5-4
5-9
5-4
5-6
5-6
5-4
5-4
5-4
5-4
5-4
5-9
5-9
5-9
5-9
TEST
CIRCUITS
Fig.
Pg.
5-4
5-6
5-6
5-4
5-4
5-4
5-6
5-9
5-4
5-9
5-4
5-6
5-6
5-4
5-4
5-4
5-4
5-4
5-9
5-9
5-9
5-9
*Order Numbers: use Device No. suffixed with package letter, i.e. DM930N.
5-j
Series 930
...
~
en
CD
DTL series 930 integrated circuits
W
o
general description
The National Semiconductor family of DTL
(Diode-Transistor-Logic) is a complete line of compatible monolithic integrated circuits designed to
operate at medium speed with medium power dissipation and high fan-out. The DTL family is available in 14-pin, silicone, dual-in-line packages for
operation over the O°C to 75°C temperature range.
The DTL line is composed of a variety of NAND
gates that allow complete design flexibility. The
gates are available with either 6K pull-Up resistors
for low power dissipation, or 2K pull-up resistors
for increased speed. The gate outputs can be wired"
together to achieve the wired-OR function.
The NAND gates are complemented with the
DM932 and DM957 buffers which provide higher
fan·out; the DM944 and DM958 power gates
which have an open collector, and the DM933
extender which allows increased fan-in for both
buffers and the DM930 and DM961 gates.
The binaries in this family are of the direct coupled master-slave type with direct clear and direct
set lines. The dual flip flops include ones with
either common or separate clocks.
The DM930 series is directly compatible with the
TTL devices manufactured by National and can be
used In conjunction with them in those portions
of a system where speed is not the main consideration.
table of contents
Absolute Maximum Ratings., ••• _•••••• _••••••••••••.•••• _•••• __ .... _. ',' ___ .• _••••• __ . _., __ ••• __ . 5-2
Connection/Logic Diagrams ••• _••• _•••••••••••• _•• _• _••••..•• ___ ••• __ .• __ .•• __ ••.•• __ .•• _•••• _••• 5-2
NAND Gates _._ •••. _•••••••• _•••• _. _.••..•. __ .•••••. _.......................................... 5-3
DM930, DM961 - dual four Input gates with expanders
DM935, DM936, DM937 - hex inverters
DM946, DM949 - quad two Input gates
DM962, DM963 - triple three input gates
DM1800, DM1801- dual five input g~(es
Buffers/Extender ••••••.•.•••••••••••••••.•••••.•••.•.•.•.••.••.•••••.•••••••••••• , ••..•••..••••. 5-5
DM932 - dual four input buffer with expander
DM933 - dual four input extender
DM944 - dual four input power gate with expander
DM957 - quad two input buffer
DM958 - quad two Input power gate
Binaries ........................................................................................ 5-7
DM945, DM948 - RS flip flops
DM9093, DM9094, DM9097, DM9099 - dual JK flip flops
5-1
o
M
en
absolute maximum ratings
I/)
CD
Power Supply Voltage
Continuous
Pulsed < 1 sec.
I nput Forward Current
I nput Reverse Current
Output Current
Gates and Binaries
Buffers
Storage Temperature
Operating Temperature
';::
CD
t/)
........
Q
8.0V
12.0V
10mA
1.0mA
30mA
100 mA
-65 c C to 150c C
OC C to 75 c C
connection/logic diagrams
1O-"""T"-",-=:::I
n_-'-_..r-::::I
13-+---'
11--+_ _ _-1
13-+-----\
DM930/DM961
DM932/DM944
DM1800/DM1801
13_-+__'"
-:><>----+--10
11
1O=t=::[)o--r-
':><>--1-- 12
DM935/DM936/DM937
DM946/DM949
X>--+-"
1O--+----i
11_-+_ _'"
DM962/DM963
13
"=1==::[Y---t"
10-"'--1-=
12_-I-_r-":::::I
13-+---'
}-__-+_11
DM933
DM957/DM958
10-+----...,
,,~~
10-+---,
1 1 - , -......JIL....:"_..J
13-+--01
,,-+---\
10-++-+----.
l1-+--HH
12-f-.....JH
13-+--<"'---'
DM945/DM948
5-2
DM9093/DM9094
DM9097/DM9099
C
-t
r-
NAND gates
f/)
CD
::::!.
CD
The DM1800 and DM1801 dual 5-input NAND
gates are new DTL gates completely compatible
with DM930 series gates.
The DM930, DM936, DM946 and DM962 are a
variety of NAND gates with a 6K pull-up resistor.
The DM961, DM937, DM949 and DM963 are the
2K pull-up versions of the respective gates_ The
DM935 is a hex inverter similar to the DM936
with the exception that it has no input diodes.
!II
CD
Co\)
o
schematic diagrams*
14 (Vccl
14 (Vee!
1 191
61BI
o-.....~....--t
2 (4, 6, B. 10. 121
1 (3. 5. 9, II, 131 o--I'III-.--t
2 1101
3 1111
4 1121
5 1131
11GNOI
DM935/DM936/DM937
DM930/DM961
14 (Vcc!
14 Pled
316.'.111
1(4.9.1210-........--1
1216.BI
113.910--1'11".-04
214,101
215.10.131
1315.111
71GNoi
71GNDI
DM962/DM963
DM946/DM949
14 (Vccl
1 191
0--1'111-.--1
2 1101
'-.1--4...-t
311110-. . . . . .
4 (12)
5 1131
71GNoi
DM1800/DM1801
*Only one circuit element
IS
shown. Pm connections are given
In
parentheses for other circuit elements.
5-3
o
(t)
electrical characteristics
0')
III
.!
...
Pin 14 (Vee)
=:
5 0 volts, Pin 7
= GND,
unspecified PinS open unless otherwise stated .
Q)
LIMITS
CONDITIONS
en
SYMBOL
PARAMETER
PART
25i-'.:.C_-jf--_.:.'5i-',:,C_-IUNITS
t-_=-:::-..;I;,:NP:,::U:.;.T:.5_ _ _ _+_:.0U:.;T..;PU:.T:.:5_+-_ _0i-'.:.C_--I_ _.:.
INPUT
OTHER
MIN
MIN
MAX
MIN
MAX
UNDER TEST
045
V"
Output Low Voltage
All gates
v,"
Output High Voltage
All gates'
Ie
Input RelferseCurrent
All
I,
Input Forward Current
All except
935
'"l
Output Leakage Current
6kgates
2kgates
GNO
GNO
VCEX
V CEX
I"
Output Short CirCuit
Current
6kgates
2kgates
GNO
GNO
GNO
GNO
I"
Power Supply Current
per gate
6kgates
2kgates
Ve
Max Supply Current
All
GNO
045
050
26
26
Ve
25
except 935
except
Ve
GNO
V,
Ve
10
935
Input Current
cEx
I MAX
per gate (Vee
935"
~
-140
_140
V,
_140
-133
mA
-061
-185
MA
MA
-125
-130
-390
mA
R~400n,C=50pF
...
6k gates
2kgates
Turn-On Delay
6kgates
2kgates
R=39kn,C=30pF
R '" 39kH,C= 30pF
R"'400n,C=50pF
10
10
30
30
25
80
60
15
FD600 diode or eqUivalent on mput under test
test conditions
(6k)
(6k)
(2k)
(2k)
TEMP,
V,H
VOLTS
V,L
VOLTS
VR
VOLTS
VF
VOLTS
VCEX
VOLTS
IOL
rnA
IOH
rnA
IOL
rnA
IOH
rnA
O'C
+25°C
+75'C
2.0
1.9
1.8
1.2
1.1
0.95
4.0
4.0
4.0
0.45
0.45
0.50
5.0
12.0
12.0
11.4
-0.12
-0.12
-0.12
11.0
11.0
10.4
-0.5
-0.5
-0.5
switching time test circuit and waveforms
Vcc=SV
.. . ...
r--.
./I
1.3V
'1
------------------------G.D
5-4
mA
mA
mA
mA
59
Turn-On Delay
~Usean
mA
BV,
t pd _
'
-133
100
100
130
""
-140
C
-I
r-
buffers and extender
en
CD
The DM932, DM944, DM957, and DM958 are
power gates which are capable of sinking high
currents.
::::!.
CD
of two four input diode nodes and can be used to
extend the fan·in of the DM930, DM961, DM932,
and DM944.
en
CD
W
o
The DM933 is an extender element which consists
schematic diagrams*
(Vccl14
IVc cl14
185K
185K
1 (9)
1(5,8,12)
150
200)
I"
2(6,9,1l}
6(8)
3(11)
3(4,10,11)
4(12}
2K
5(13)
",0
630
(GND)7
IGNO)1
DM957
DM932
'§
:-*r~--§":
3
12
1(GND)
DM933
IVee ) 14
V"
lK
"'0
""
1 (9)
1/5,8,121
2(10}
2(6,9,13)
6(B)
J(l1)
3/4,10,11}
2K
4(12)
5lll}
630
"'0
(GND)1
(GNO) 1
DM944
*Only one Circuit element 15 shown. Pm connections are given
DM958
In
parentheses for other Circuit elements.
5-5
o(W')
en
electrical characteristics
III
.!!
...
Pin 14 (Vee)
=
5.0 volts, Pin 7
=
GND, unspecified PinS open unless otherwise stated .
Q)
en
-'
CONDITIONS
SYMBOL
PARAMETER
PART
LIMITS
INPUTS
OUTPUTS
UNITS
I-
o
INPUT UNDER TEST OTHER
Output Low Voltage
932.944
957.958
Output High Voltage
932.957
Input Reverse Current
932.944
957,958
933
932,944
957,958
V FD
Input Forward Voltage
Ise
Output Short
ICEX
Output Leakage Current
elf.
2.6
MIN.
GND
0.45
5
GND
"'D
932,957
075
GND
090
068
=
Turn-On Delay
Turn-Off Delay
0.60
10
pA
rnA
0.75
pA
200
4.5
4
rnA
957
SO.O
12.5
932
957
R o 150n,C o 500pF
944
958
R
932
957
R
944
958
R
15
40
100 pF
10
35
510n, Co 500pF
25
80
510n, C 20 pF
15
50
150n, C
0
0
0
0
0
ns
ns
test conditions
957
TEMP.
VIH
VOLTS
VIL
VOLTS
2.0
1.9
1.8
0.95
VR
VOLTS
VF
VCEX
VOLTS
VOLTS
4.0
4.0
4.0
0.45
0.45
0.50
1.2
1.1
-2rnA
-2m A
-2rnA
5.0
958
944
957
rnA
IOL
rnA
IOH
rnA
36
36
34
40
40
36
-2.0
-2.5
-3.0
932
IOL
932
switching time test circuit and waveforms
Vee = 5V
1"::"\
2.0K
~~
02
D3
:'4
v,.o-~"r'f<>HT"((995-5B~-,~~'-~"-_~O'll••;'IIL;V'll_-A-Ll"-'II\Ii,~,."
.. +-.I-~"'h!,
.J:
PULSE IN
~EN)
~
D5
DI.".
PW>1000s
n
V'.~
15V
I'-
----J~'~.
~
~."
15V
------------GOO
NOTE When testmg 958 Of 944 sllon diode 01, remove diodes
02, Ol, D4 and D5 and add capac nor C2 = 20 pF as shown
5·6
pA
rnA
rnA
rnA
rnA
944
GND
v
rnA
100
100
25
V CEX
pA
-133
-14
V CEX
v
V
30.0
932,944
957,958
BV)
0.82
-16
-16
GND
958
per gate (Vee
25
-1.40
932
Max. Supply Current
MAX.
0.50
5
-1.40
GND
GND
GND
944,958
I MAX
MIN.
2.6
VR
933
Power DraIn Current
MAX.
10
932,957
Cur.
MAX.
0.45
GND
Input Reverse Current
Input Forward Current
MIN.
o
-t
r-
binaries
en
...
CD
The DM945 and DM948 are R-S flip flops which
can be externally cross coupled to perform in the
JK mode. They are of the master slave type with
output buffers to provide isolation from the out·
put load. These flip flops feature both asynchro·
nous set and clear lines. The DM945 has a 6K
pull-up resistor and the DM948 has a 2K pullup resistor.
(D'
of the DM945 and DM948 variety respectively.
Both flip flops have separate clocks and no asyn·
chronous clear lines.
(II
CD
W
o
The DM9097 and DM9099 are dual JK flip flops
of the DM948 and DM945 variety respectively.
Both flip flops have common clocks and both
asynchronous set and clear lines.
The DM9093 and DM9094 are dual JK flip flops
schematic diagrams
Vee (141
Vcc( 14)
Cp GND
Cp GND
(2)
(2)
m
DM945
m
DM948
truth tables
tn
St
Pin 3
S.
Pin 4
Pin 12
C.
Pin 11
X
0
0
X
0
x
x
0
X
X
0
0
0
X
0
x
x
0
,,,
X
o-
C,
,,
0
1
,,
x
,
0
Low State (more negative)
1 - High State (more poSitive)
U - Indetennmate State
J-K TRUTH TABLE
ASYNCHRONOUS TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
,,
x
0
1
X -
tn + 1
So
CD
Q
Q
Q
Pin 10
Pin 5
Pin 6
Pin9
1
0
1
0
1
1
0
0
NC
Pin 6
an
an
an
an
0
0
,
,
0
1
NC
0
1
1
.. +'
tn
St
Pin3
Ct
Q
Pin 12
Pln6
ON
o
ON
(Connect 51 to B., C1 to OJ Asynchronous Inputs,
direct set (Sol and direct clear (Col, override the
1
sync"fOnous mputs, they are Independent of all
U
other Inputs
State of the
mput does not
affect the state
ot the clrQ..Ilt
5·7
o
en
(W)
schematic diagrams
II)
CD
'i:
CD
tJ)
...I
I-
o
DM9094
• U$fdonedlllllllnpliceoftr.nllStor
... R'slStorwt!utlsZKohms,
DM9093/DM9094 (DM9093 shown)
[""""
r-----;:=========~-___.,v"r-----;:=============t--___,
c,t----t::=========~-----1
13
DMIOI9
.. U. dotted hnt IneludlItD rntStor Ind t"nllltor In plRe of INfect tp Input
*"' Rado, .llte II IK ohms.
DM9097/DM9099 (DM9097 shown)
truth table
J-K TRUTH TABLE
tn
tn
5,
Pin 3
0
1
0
1
C,
Pin 12
0
0
1
1
+1
a
Pin6
ON
1
0
ON
Direct set (So) and direct clear (CD), overnde the
synchronous inputs, they are independent of all
other Inputs.
5-8
C
-t
r-
switching time test circuits and waveforms
en
CD
...
II cc ·5V
CD
en
CD
W
o
Pllt~S£ o--tc>t-t+---,
IV'NI
DM945/DM948
(3,11)
(2,12)
---,
14
~VCC_5V
v" o--fO+-<>--'----ih
r-l
1
."
.1
,I
lil
1
1
FIXED
lOAD
I
---"
~15V_ _
IIcc- 5V
~I
VARIABLE
I
1
LOAD
/
__
--.J
~1-3~15-V--_
GNO
1.SV
GNO
Cl and C21nclucle probe ilod Jig CilPilC1tV
All dlOcieure FD600 OJ equivalent ilt +25 C
DM9093/DM9094 (one-half circuit shown)
15V
-"----GOO
NlllETt2SV
)
I
I
I
I
I
)
I
I
I
ov
I
I
I
I
I
I
I
PRESET
REMOVED
TEST
CP,
5·10
I
>25V
)
I
I
VCPTH
)
)
o.
)
)
I
I
I
I
I
I
I
)
TEST
PRESET
REMOVED
CPo
I
VCEX
VOLTS
-
5.0
C
-I
r-
OM9093/0M9094/0M9097/0M9099
en
CD
...
electrical characteristics
Pin 14 IVeel
=
5.0 volts, Pm 7
=
CD
en
GND
CD
LIMITS
SYMBOL
PARAMETER
PART
oOc
CONDITIONS
M.N
Voc
Output Low Voltage
All
IOL on output under test
VOH
Output High Voltage
All
loH on output under test
loc
Output Short Circuit
_75°C
+25°C
M.N
MAX
-
-
045
"
-
26
',e
'"
"
-
050
V
25
-
V
2k
GND output under test
~1
-42
-177
-42
-160
-40
rnA
6k
GNO output under test
-059
-141
-059
-141
-055
-138
rnA
Input Forward Cllrrent
(Data Input)
All
V F on tnput under test
V A on other Inputs
-
-095
-
-095
-
-090
rnA
Input Forward Current
9097
-
-56
-
-534
rnA
9099
-
-56
(Clock and Direct Clear
Inputs)
V F on mput under test
V R on other mputs
Input Forward Current
(Clock Input)
9093
V F on Input under test
-
-28
-
-267
rnA
V R on others
-
-28
9094
Input Forward Current
(Direct Set Inputs)
All
V F on Input under test
VR on other mputs
-28
-
-28
-267
rnA
Input Reverse Current
All
V R on Input under test
GND on other Inputs
50
-
50
.00
"A
9097&
V R on Input under test
GND on other Inputs
20
"A
,0
"A
(AU except clock Inputs
and Direct clear Input
on 9097, 9099)
"
Input Reverse Current
Direct (Clear Input)
"
Input Reverse Current
(Clock Inputs)
"
"0
I MAX
MAX
-
045
77
Current
""
UNITS
M.N
MAX
Power Drain Current
Max Supply Current
(V ce '" 8V)
9099
9094
VR on Input under test
GND on other inputs
9097&
9099
V R on Input under test
GND on other Inputs
9093
9094
9099
9097
Inputs Open
Inputs Open
Inputs Open
Inputs Open
9093
GNDalilOputs
9093&
-
9094
9097
t pd _
Turn-On Delay
All
R"'3300,C"50pF
',~
Turn-Off Delay
6k
R=2k,C=30pF
R=2k,C=30pF
2k
20
40
-
-
9099
-
'0
-
--
10
20
40
28
34
28
34
--
-
-
-
36
-
45
15
55
--
-
-
-
--
.00
25
25
60
75
-
"A
rnA
rnA
rnA
rnA
rnA
rnA
"'
"'
"'
test conditions
TEMP_
0° C
+25°C
+75°C
16k)
IOL
12k)
IOL
16kl
IOH
12k1
IOH
mA
mA
mA
mA
16.8
16.8
16.0
15.4
15.4
14.6
-0.12
-0.12
-0.12
-0.5
-0.5
-0.5
>25V
,y
VF
VOLTS
0.45
0.45
0.50
VR
VOLTS
2.0
1.9
1.8
4.0
4.0
4.0
I
I
I
I
I
I
I
I
I
I
, I
I
I
I
I
I
TEST
PRESET
REMOVED
CP,
I
V.H
VOLTS
>25V
VCPTIi
,y
9093-9
V.L
VOLTS
2K
VCPTH
VCPTH
1.15
0.95
0.65
1.30
115
0.85
1.2
1.1
0.95
I
I
I
I
I
I
I
I
9094-7
6K
I
I
I
I
I
I
I
I
TEST
PRESET
REMOVED
CP,
5-11
W
o
en
CD
~.
Series 9000
~s
CD
en
CD
o
o
o
REFERENCE
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below.* Refer to the alpha-numerical Index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
Devices
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM8300
DM9300
DM8301
DM9301
DM8309
DM9309
DM8312
DM9312
DM8322
DM9322
DM8334
DM9334
DM8601
DM9601
DM8602
DM9602
Pg.
6·1
6-1
6-1
6-1
6-1
6-1
6·1
6-1
6-1
6-4
6·4
6-6
6·6
6·8
6·8
6·10
6-10
6-12
6-12
6·14
6-14
6-17
6·17
6·21
6-21
PACKAGES
Molded DIP (N)
Cavity DIP (D)(J)
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Fig.
Pg.
Fig.
Pg.
Type
Fig.
Pg.
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
5
5
5
II
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
11
11
12
12
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
19
19
19
19
19
19
19
19
19
19
19
19
18
18
19
19
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
3
5
5
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
Type
Pg.
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Type
WAVEFORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
36
36
5
5
39
39
40
40
37
37
48
48
38
38
47
47
10-17
10-17
10-5
10-5
10-18
10-18
10·18
10-18
10·17
10-17
10-25
10·25
10·17
10-17
10·25
10·25
9
9
1
1
1
1
1
1
14
14
1
1
8
8
24
24
10·2
10-2
10-1
10·1
10-1
10·1
10-1
10·1
10-4
10-4
10·1
10-1
10·2
10·2
10-7
10-7
*Order Numbers: use Device Number suffixed with package letter, i.e., DM9002CN.
6·j
en
CD
.
Series 9000
ii'
III
CD
o
o
o
DM9002C quad 2-input NAND gate
DM9003C triple 3-input NAND gate
DM9004C dual 4-input NAND gate
DM9005C dual AND-OR-INVERT gate/expander
DM9006C dual 4-input expander
DM9008C 2-2-2-3-input AND-OR- INVERT gate
DM9009C dual 4-input NAND gate/buffer
DM9012C quad 2-input NAND gate(open collector)
DM9016C hex inverter
general description
The above gate functions are commercial temperature range (O°C to +75°C) plug-in equivalents for
connection diagrams
the DM9000 Series devices. The "C" designation
is used in place of the earlier "-59X" suffix.
IDual-ln-Line and Flat Packages)
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
.0.
DM9OO9C
DM9012C
DM9016C
6-1
o
o
o
en
absolute maximum ratings
III
G)
...
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
G)
o
7V
5.5V
O°C to +75°C
_65°C to +150°C
300°C
electrical characteristics
DM90002C, DM9003C, DM9004C, DM9012C, DM9016C
PARAMETER
(Note 1)
CONDITIONS
Logical "1" Input Voltage
Vee = 4.75V
Logical "0" Input Voltage
Vee = 4.75V
Logical "1" Output Voltage
Vee = 4.75V, lOUT = -1.2 rnA, V'N = .85V
MIN
MAX
UNITS
V
1.6
.85
2.4
V
V
Except DM9012C
Logical "0" Output Voltage
Vee = 4.75V, lOUT = +14.1 rnA, V'N = 1.6V
Vee = 5.25V, lOUT = +16 rnA, V'N = 5.25V
Logical "1" Output Current
Vee = 4.75V, VOUT = 5.5V, V'N = .85V
.45
.45
250
V
V
/lA
IDM9012C)
Logical "1" Input Current
Vee = 5.25V, V'N = 4.5V
60
/lA
Logical "0" Input Current
Vee = 5.25V, V'N = .45V
Vee = 4.75V. V'N = .45V
-1.6
-1.41
rnA
rnA
Supply Current - Logical "0" Output
Vee = 5.0V
6.1
rnA
Vee = 5.0V
1.7
rnA
leach gate)
Supply Current - Logical "1" Output
leach gate)
Propagation Delay Time to a Logical "'"
Except DM9012C
DM9012C
Propagation Delay Time to a Logical "0"
Except DM9012C
DM9012C
30
13
ns
ns
Vee = 5.0V,C L = 15 pF, RL = 4 kn
3.0
45
Vee = 5.0V, C L = 15 pF, T A = 25°C
3.0
15
ns
Vee = 5.0V, C L = 15 pF, RL = 400n,
T A = 25°C
3.0
15
ns
MIN
MAX
DM9005C, DM9006C, DM9008C (Note 1)
PARAMETER
CONDITIONS
1.6
Logical "1" Input Voltage
Vee = 4.75V
Logical "0" I "put Voltage
Vee =4.75V
Logical "1" Output Voltage
Vee = 4 75V, lOUT = -1.2 rnA,
V'N = .85V
Logical "0" Output Voltage
Vee=4.75V,loUT=14.1 rnA,
V'N = 1.6V
Vee = 4.75V, lOUT = 16 rnA,
V'N = 5.25V
UNITS
V
.85
2.4
V
V
.45
V
.45
V
Logical "'" Input Current
Except DM9005C Non·
Vee = 4.75V, V'N = 4.5V
90
/lA
Vee = 4.75V, V'N = 4.5V
60
/lA
Vee
Vee
Vee
Vee
-2.12
-2.4
-1.41
-1.6
rnA
rnA
rnA
rnA
7.7
13.6
17.7
rnA
rnA
rnA
Extendable Gate
DM9005C Non·Extendable Gate
Logical
"a·· Input Current
Ex~ept DM9005C Non·
Extendable Gate
OM9005C Non-Extendable Gate
= 4.75V,
= 5.25V,
= 4.75V,
= 5.25V,
V'N
V'N
V'N
V'N
= .45V
= .45V
= .45V
= .45V
Supply Current - LogIcal "0" Output
DM9005C Non·Extendable Gate
DM9005C Extendable Gate
DM900ac
Vee = 5.0V
Vee = 5.0V
Vee = 5.0V
Note 1: All devices are guaranteed across the O°C to +75°Ctemperature range except where specified differently.
6-2
en
...
CD
electrical characteristics (con't)
CD
UI
CD
0
0
0
DM9005C, DM9006C, DM9008C (can't)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
3.4
5.1
10.2
rnA
rnA
rnA
Supply Current - Logical "1" Output
DM9005C Non-Extendable Gate
DM9005C Extendable Gate
DM900ac
Vee = 5.0V
Vee = 5.0V
Vee=50V
6Supply Current
Additional Supply
Current when one DM9006C
Vee=50V
2.05
rnA
Vee=50V
254
rnA
Extender
IS
connected to a
DM900SC Gate in the Logical"Q" State
Additional
•.. In
the Logical "1" State
Propagation Delay Time to a Logical "1"
DM9005C Non-Extendable Gate Only
DM9005C Extendable Gate, and
DM9008C
DM9006C (Note 2)
Propagation Delay Time to a Logical "0"
DM9005C Non-Extendable Gate Only
DM9005C Extendable Gate, and DM9008C
DM9008C
DM9006C (Note 2)
V ee =50V,C L =15pF,
TA =- 2SOC
3.0
30
C N = 5.0 pF
-20
12
15
4.0
ns
ns
ns
Vee = 5 OV, C L = 15 pF,
T A = 25°C
30
30
C N = 5.0 pF
14
12
-20
40
MIN
MAX
ns
ns
ns
DM9009C (Note 1)
PARAMETER
CONDITIONS
logical"1" Input Voltage
Vee = 4.75V
Logical "0" Input Voltage
Vee = 4.75V
logical "1" Output Voltage
Vee = 4 75V.
V 'N = .85V
Logical
"a" Output Voltage
.B5
lOUT =
-3.6 rnA,
UNITS
V
1.6
24
V
V
Vee = 4 75V, lOUT = 42.3 rnA,
V 'N = 1.6V
Vee = 5.25V, lOUT = 48 rnA,
V ,N =525V
.45
V
.45
V
Logical "1" Input Current
Vee = 5 25V, V ,N = 4.5V
Logical "0" Input Current
Vee = 5 25V, V ,N = .45V
Vee = 4.75V, V ,N = .45V
-32
-282
rnA
rnA
120
Supply Current - Logical "0" Output
Vee = 5,OV, V ,N = 4.5V
14.6
rnA
Supply Current - Logical "1" Output
Vee = 5.0V, V ,N = GND
3.4
rnA
Propagation Delay to
Logical "1"
Vee = 5.0V, C L = 15 pF, TA = 25°C
3,0
17
ns
Propagation Delay to a Logical "0"
Vee = 5.0V, C L = 15 pF, TA = 25°C
2.0
13
ns
it
~
}1A
Note 1: All devices are guaranteed across the O°C to +75°C temperature range except where specified differently.
Note 2: The DM9006C is tested by measuring its propagation delay through the DM9005C. The delay readings shall not exceed
the DM9005C reading by the specified amount.
6-3
o
o
('t)
Series 9000
CO
:E
c
........
OM9300/0M8300(SN54195/SN74195) 4-bit shift register
o
general description
:E
The DM9300/DM8300 is a 4-bit multi-function
shift register designed to work at typical speeds of
25 MHz.
o
('t)
0)
c
It features a common asynchronous Reset input
which resets the register independent of any other
input. In addition, the J and K inputs to the first
flip flop enable greater fleXibility in the operation
of the register. (See truth table.)
shifted right. When the PE input is In the logical
"0" state, the information on the parallel inputs
will be entered Into the flip flops on the subsequent clock pulse. A logical "1" level on the PE
control will allow shifting to the nght.
The outputs change state on the positive-going
transition of the clock input.
The PE (Parallel Enable) control allows information to be entered from the parallel Inputs or be
This register is completely compatible with Series
54/74 and CCSL deVices. Input diode clamps are
provided for additional system reliability.
connection diagram
truth table
Dual-In-line and Flat Package
J
K
0
0
0
1
1
0
(PE
00
at tn+1
0
00 at tn
1
(no change)
00 at tn
1
(toggle)
1
= logical '"1'", MR = loglcal"l")
typical application
Eight Bit Left/Right Shift Register
ThiS register shifts left or right on each shift clock, depending upon the condition of the LS/RS select
Input. If thiS Input IS high, right shift occurs and If low, left shift occurs.
lSJRSSELECT
RS DATA IN
L~~
lS DATA OUT
CLOCK
PE
II
P,
..
P,
I
P,
P,
n,
OM930lliDM8300
MR
0,
II
0,
I
n,
-:I~
K
PE
III
P,
P,
..
P,
lS DATA IN
P,
n,
DM9300/DM8300
MR
0,
II
0,
n,
I
MASTER RESET
equivalent circuits
...-----.....-,,,
OUTPlIltURRENTV£RSIISOIITPUTVDLTA6E
lo.o,o,n,ANOii,1
6-4
RS DATA OUT
c
:s:
CD
absolute maximum ratings
v cc Voltage Range
Input Voltage Range
Output Voltage (Logical "1" state)
Operating Temperature Range DM9300
DM8300
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
w
o
o
-.5V to 7V
-.5V to 5.5V
5.5V
_55°C to +125°C
OO.C to 75°C
-65°C to +150°C
300°C
......
c
:s:CD
w
o
o
ITA = _55°C to +125°C, Vee = 5.0V ±10%1
LIMITS 25°C
PARAMETERS
MIN
Input High Voltage
TYP
2.0
In put Low Voltage
0.8
-1.5
Input Clamp Diode Voltage
Output High Voltage
2.4
CONDITIONS
UNITS
MAX
3.6
Volts
Guaranteed Input High Voltage for All Inputs
Volts
Guaranteed Input Low Voltage for All Inputs
Volts
Vcc ""Mtn, liN =-12mA,T A =25°C
Vee
Volts
= Mm,
for 00-03
Output Low Voltage
0.2
0.4
Vee
Volts
for
= Mm,
IOH
VIN
tOL
00-Q3 VIN
= -640,uA for 0:;-, and -480J,lA
= V IH or V 1L per Truth Table
= 12.8 rnA for 0; and 9.6 rnA
= V 1H or V 1L per Truth Table
Input High Current
J, K,MR, Po, P" P2 , P3 + PE
40
80
CP
Input High Current, All Inputs
JlA
Vee
= Max, VIN = 2.4V
10
rnA
Vee
= Max, VIN
-1.6
-3.2
= Max, VIN
=
5.5V
Input Low Current
J,
K. MR, Po, P"
P2 , P3 +
PE
mA
Vee
-55
-55
mA
mA
DM9300
DM8300
Vee
Vee
86
92
mA
mA
DM9300
DM8300
Vee = Max
Inputs High
CP
-20
-18
Output Short CirCUit Current
INote51
Power Supply Current
switching characteristics
SYMBOL
CHARACTER ISTIC
tpd+
tpd_
Turn Off Delay
f"
Shift Right
Frequency
Clock Pulse Width
CPpw
MIN
Turn On Delay
t,
t,
t,IPE)
Set-up Time
Release Time
t,IPEI
tpd_IMR)
Release Time for
trec(MR)
Recovery Time for MR
MRpw
Min Reset Pulse Width
Set-up Time for
-
PE
PE
Reset Time for MR
OV
OV
ITA = 25°C)
TYP
12
19
MAX
22
26
UNITS
ns
n,
30
38
MHz
17
30
11
ns
ns
ns
ns
ns
45
= DAV
= Max, V OUT =
= Max, V OUT =
13
10
20
17
28
13
15
0
10
CONDITIONS & COMMENTS
Vee - 5.0V, CL - 15 pF
ISee Figs. 1 & 2al
Vee = 5.0V, CL = 15 pF
(See Figs. 1 & 2e)
Vee = 5.0V
CL=15pF
ISee Figs. 2. & 2b)
ns
ns
ns
SET UP TIME' ts IS defined as the minimum time reqUired for the logic level to be present at the logic
Input prior to the clock tranSition from low to high In order for the flip flop(s) to respond
RELEASE TIME' tr IS defined as the maximum time allowed for the logic level to be present at the
logiC Input pnor to the clock transition from low to high In order for the flIp flop(s) not to respond
MR:
RECOVERY TIME FOR
trec(MA) 15 defined as the minimum time reqUired between the end of
the reset pulse and the clock tranSitIOn from low to hIgh In order for the flip flop(s) to respond to the
clock
6·5
...
o
M
Series 9000
00
::!
Q
...o
.......
M
en
::!
DM9301lDM8301 BCD-to-decimal decoder
Q
general description
features
The DM9301/DM8301 utilizes Series 54/74 compatible circuitry to decode a four-bit BCD number
to one-of-ten decimal outputs_ These ten decimal
outputs are capable of driving 10 standard TTL
loads each_
•
125 mW tYPical power dissipation
•
20 ns typical propagation delay
•
Clamp diodes on inputs
The decoding logic is designed such that when
binary numbers between 10 and 15 are applied to
the inputs, no outputs are enabled.
logic and connection diagrams
Dual-I n-Line and Flat Package
logic table
OUTPUTS
INPUTS
OUTl'OTl
OUTI'UTS
D
C B
A
0
1
2
3
4
5
6
7
B
9
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
6-6
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c
absolute maximum ratings
Supply Voltage
Input Voltage
Fan Out
Storage Temperature Range
Operating Temperature Range DM9301
DM8301
Lead Temperature (soldering, 10 sec)
electrical characteristics
CONDITION
Logical "1" Input Voltage
Vee = 4.5V
Vee - 4.75V
Logical "0" Input Voltage
DM9301
DM8301
Vee= 4.5V
V ee -4.75V
Logical "1" Output Voltage
DM9301
DM8301
Vee= 4.5V
Vee - 475V
lOUT = -800/lA
Logical "0" Output Voltage
DM9301
DM8301
Vee=45V
Vee - 4 75V
lOUT = 16 rnA
Logical "1" Input Current
DM9301
DM8301
Vee= 55V
Vee - 525V
V ,N = 4.5
Logical "1" Input Current
DM9301
DM8301
Vee=55V
Vee - 5.25V
V ,N ,055V
Logical "0" Input Current
DM9301
DM8301
Vee = 5.5V
Vee = 5.25V
V ,N = 04V
Input Clamp Diode (All Inputs)
DM9301
DM8301
Vee= 5.5V
Vee - 525V
I'N=-12mA
DM9301
DM8301
Vee = 5.5V
Vee - 525V
VOUT=OV
DM9301
DM8301
Vee=55V
Vee - 5.25V
Power Supply Current
3:
00
w
o...A
(Note 2)
DM9301
DM8301
(Note 3)
.....
c
7V
5.5V
10
_65°C to +150°C
_55°C to +125°C
DoC to +70°C
300°C
PARAMETER
Output Short Clrcu It Current
3:
CD
w
o...A
(Note 1)
~,---
MIN
TYP
MAX
2.0
V
0.8
2.4
V
V
04
-20
-18
UNITS
V
40
/lA
1
mA
-10
-16
mA
-1.0
-15
V
-32
-55
-57
mA
mA
25
41
mA
Propagation Delay Time to a Logical "0"
Vee = 5.0V. T A = 25°C,
COUT = 50pF, F.O. = 10
8
19
30
ns
Propagation Delay Time to a Logical "1"
Vee = 5.0V, T A = 25°e,
e OUT = 50 pF, F.O. = 10
8
20
30
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot
be guaranteed. Except for "Operatmg Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Minimax limits apply across the guaranteed operating temperature range -55°C to +12SoC for
DM9301 and O°C to 70°C for the DM8301 unless otherwise specified. All tYPlcals are given for
Vee = 5.0V and T A = 25°e.
Note 3: Only one output may be shorted at a time.
6·7
G)
Q
(W)
Series 9000
co
:E
Q
......
en
Q
(W)
DM9309/DM8309 dual 4-input multiplexer
G)
:E
Q
general description
features
The DM9309/DM8309 is a dual four-input digital
multiplexer. It consists of two multiplexing circuits with common input select data logic. Each
circuit contains four inputs and fully buffered
complementary outputs.
• Series 54/74 T2L and DTL compatible
•
Input clamping diode
•
Fully buffered complementary outputs
•
Fan-out of 10
logic and connection diagrams
'.
1
Dual-In-Line and Flat Package
'. •
131
•
Iz.
to
'1.
10.
11
12
1"
•
"
,
truth table
SELECT INPUTS
S,
lOA
l'A
L
L
L
X
L
L
H
H
L
X
X
L
H
L
X
H
OUTPUTS
I'A
X
13A
X
ZA
ZA
L
H
X
X
H
L
X
X
L
H
X
H
L
L
H
X
X
L
X
H
X
X
H
X
L
H
H
L
H
H
X
X
X
L
L
H
X
L
H
H
X
X
X
H
H
L
So
S,
loa
I,.
I,.
13.
z.
z.
H
L
L
L
L
X
X
X
L
L
H
X
X'
X
H
L
H
L
X
L
X
X
L
H
H
L
X
H
X
X
H
L
L
H
X
X
L
X
L
H
L
H
X
X
H
X
H
L
H
H
X
X
X
L
L
H
H
H
X
X
X
H
H
L
L = Low Voltage Level
H = High Voltage level
X = Irrelevant
6-8
INPUTS
So
14
OJ
3
• , •
12
" "
1
9
r
C
absolute maximum ratings
s:
operating conditions
(Note 1)
U)
w
0
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7V
5.5V
5.5V
-65'C to +150'C
300°C
Supply Voltage (VCC)
DM9309
DM8309
MIN
MAX
UNITS
4.5
475
5.5
5.25
V
V
-55
0
+125
70
"C
°c
U)
........
C
s:CO
Temperature (T A)
DM9309
DM8309
W
0
U)
electrical characteristics
(Note 2)
CONDITIONS
PARAMETER
MIN
Logical "1" Input Voltage
Vcc=MIn
Logical "0" Input Voltage
Vee = Mm
Logical "1" Output Voltage
_
V 'NllI = 2V
Vee - Mm, V'N{QI = 8V
10H -
Logical "0" Output Voltage
_
V'NI1I=2V
Vee - Mm, V,NIOI = 8V
10L -
Logical "1" I nput Current
Vee = Max, V IN
Logical "0" Input Current
Output Short Circuit Current
(Note 3)
PropagatIOn Delay to a Logical "0"
Z. tpdO
Propagation Delay to a Logical "1"
from Data to Z,
tpdl
Propagation Delay to a Logical "1"
from Data to
Z,
tpd 1
24
V
_
04
16 mA
V
JiA
1
mA
-1.6
mA
Vee
=:
=:
Max, VIN = 4V
Vee = Max
Vee
from Data to
-8001lA
V
40
Vee = Max
tpdO
V
08
_
UNITS
2 4V
Input Clamp Voltage
from Data to Z,
MAX
Vce = Max, Y'N = 5 5V
Supply Current
Propagation Delay to a Logical "0"
TYP
2
=:
-30
-27
27
Min, I'N=-12mA
-85
mA
44
mA
-1.5
V
Vee = 5.0V, TA = 25'C
24
35
ns
Vee = 5.0V, T A = 25"C
10
15
ns
Vee = 5.0V, TA = 25"C
20
28
ns
Vee = 5 OV, T A = 25"C
15
22
ns
Vce= 50V, TA = 25°C
30
25
45
37
ns
ns
Vee = 5 OV, T A = 25°C
17
21
25
31
ns
ns
[II
Data Select to Z
tpdl
tpdO
Data Select to Z
tpdl
tpdO
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits The table
of "Electncal Charactenstlcs" provides conditions for actual device operation
Note 2: Unless otherWise specified minImax limits apply across the _55°C to +125°C temperature range for the DM9309
and across the O'C to 70°C range for the DM8309, All tYPlcals are given for Vec = 5,OV and T A = 25'C
Note 3: Only one output at a time should be shorted.
6·9
Series 9000
DM9312/DM8312 8-input multiplexer
general description
features
The DM9312/DM8312 is an eight-input digital
multiplexer which provides in one package the
ability to select one bit of data from up to eight
sources. When the enable input is taken to a
logical "0", it will enable the multiplexer to fu nco
tion.
• Series 54/74 FL and DTL compatible
• Input clamping diodes
• Selects one·of·eight data sources
• Fan·out of 10
• Fully buffered complementary outputs
logic and connection diagrams
Dual-In-Line and Flat Package
L
1
15
14
\3
11
11
10
,
3
4
5
,
1
I,
"
TOP VIEW
truth table
E
S,
s, So
I.
I,
I,
13
I,
Is
I.
17
Z
Z
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
L
L
L
L
H
H
H'
H
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
'I x
X
X
X
X
X
X
X
X
X
H '" High Voltage Level
L = Low Voltage Level
6·10
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
x = Irrelevant
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
"
9
T
GND
C
operating conditions
absolute maximum ratings (Note 1)
MIN
Supply Voltage
Input Voltage
Dutput Voltage
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
3:
Supply Voltage (VCC)
DM9312
DM8312
Temperature (T A)
DM9312
DM8312
7V
5.5V
5.5V
_65°C to +150°C
300°C
CD
MAX
...
W
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
70
°c
°c
N
.......
C
3:
CO
...
W
N
electrical characteristics
(Note 2)
MIN
CONDITIONS
PARAMETER
TYP
MAX
UNITS
V
Logical" 1" I nput Voltage
Vee
= Min
Logical "0" Input Voltage
Vee
= Min
Logical "1" Output Voltage
V,N(1 )
Vee = Min, V 'NIO )
Logical "1" Output Current
V OUT "" 5 5V
Vee = Max, V 1N = OV
Logical "0" Output Voltage
Vee = Min, V 'N (1)
V 'NIO )
Logical "1" Input Current
Vee
= Max, V,N = 2.4V
40
IIA
Vee
= Max, V ,N = O.5V
1
mA
Vee
= Max, V,N = 4V
-1.6
mA
Logical "0" Input Current
Output Short Circu It Current
2
0.8
= 2V
= .8V
IOH
= 2V
= 8V,
= Max
Supply Current
Vee
= Max
Input Clamp Voltage
Vee
= Min, liN = -12 mA
Propagation Delay to a Logical "0"
from Data to Z, tpdO
Vee
= 5.0V, TA = 25°C
Vee
Propagation Delay to a Logical "1"
from Data to Z, tpdl
Propagation Delay to a Logical "1"
from Data to Z, tpdl
Propagation Delay to a Logical "0"
from Data to Z, tpdO
V
2.4
250
IOL
0.4
= 16 mA
-30
-27
Vee
(Note 3)
= -8001lA
V
33
IlA
V
-85
mA
44
mA
-1.5
V
23
34
ns
= 5.0V, TAo 25°C
9
14
ns
Vee
= 5.0V, TA = 25°C
19
28
ns
Vee
= 5.0V, T A = 25°C
15
23
ns
Vee
= 5.0V, TA = 25°C
29
25
43
37
ns
ns
Vee
= 5.0V, TA = 25°C
20
18
30
27
ns
ns
Vee
= 5.0V,
= 25°C
28
25
42
37
ns
ns
Vee
= 5.0V, TA = 25°C
17
18
25
27
ns
ns
Data Select to Z
tpdl
tpdO
D
Data Select to Z
tpdl
tpdO
Enable to Z
tpdl
tpdO
TA
Enable to Z
tpdl
tpdO
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the safety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherWise specified minImax limits apply across the -55"C to +125"C temperature range for the DM9312
and across the oOe to 70"e range for the DM8312 All typlcals are given for Vee"" 5 OV and TA "" 2S"C.
Note 3: Only one output at a time shoufd be shorted
6-11
Series 9000
DM9322/DM8322.(DM54157/0M74157) quad 2-input multiplexer
N
N
(")
co
:E
Q
"NN
(")
en
:E
Q
general description
features
The DM9322/DM8322 consists of four 2-input
multiplexers with common input select logic and
common output disable circuitry. It allows two
groups of four bits each to be multiplexed to four
parallel outputs. When the Enable input is at the
logical "0" level the outputs reflect information
on the selected inputs. However, when a logical
"1" is applied, the outputs assume the logical "0"
level.
• Typically 10 ns from data to output
•
The DM9322/DM8322 is pin compatible and functionally compatible with the FSC9322 and the
SN54157/SN74157. Features of the device are:
• Available in either cavity or molded dual-in·
line package
• Power dissipation 150 mW typ
• Pin compatible with FSC9322 and SN54157/
SN74157
Diode clamped inputs
logic and connection diagram
Dual-In-Line and Flat Package
TOP VIEW
truth table
ENABLE
E
INPUT
OUTPUT
10
I,
Zx
x
0
0
,
a
0
,
,
x
x
x
0
0
0
0
,
0
0
x
x
,
0
6·12
SELECT
S
x
,
,
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM9322
DM8322
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
s:
CD
(Note 1)
W
N
N
7V
5.5V
5.5V
_55°C to 125°C
O°C to 70°C
_55°C to 150°C
300°C
"s:o
CO
W
N
N
o
electrical characteristics
s:
U1
(Note 2)
~
PARAMETER
CONDITIONS
MIN
TYP
MAX
U1
V
"o
DM9322
DM8322
Vee = 4.5V
Vee - 4.75V
DM9322
DM8322
Vee = 4.5V
Vee - 4.75V
Logical "1" Output Voltage
DM9322
DM8322
Vee = 4.5V
Vee - 4.75V
lOUT = -800 /1A V ,N = 2V
Logical "0" Output Voltage
DM9322
DM8322
Vee = 4.5V
Vee = 4 75V
lOUT = 16 mA V ,N = 0.8V
Logical" 1" I nput Current
DM9322
DM8322
Vee = 5.5V
Vee - 5.25V
V ,N = 24V
40
/1A
DM9322
DM8322
Vee = 5.5V
Vee - 5.25V
V ,N = 5.5V
1
mA
Logical "0" Input Current
DM9322
DM8322
Vee = 5.5V
Vee - 5.25V
V ,N =O.4V
-16
mA
Output Short Circuit Current
INote 3)
DM9322
DM8322
Vee = 5.5V
Vee = 5.25V
V OUT = OV
Supply Current - leach deVice)
DM9322
DM8322
Vee = S.SV
Vee - 5.25V
All Inputs = 4.SV
Input Clamp Voltage
~
DM8322
Vee = SV
TA = 25°C
liN = -12 mA
Logical "1" Input Voltage
Logical
"a"
Input Voltage
2.0
0.8
2.4
0.4
-1
-20
-18
30
s:.....
V
U1
-55
-55
mA
mA
48
mA
11
16
ns
8
17
27
ns
4
8
15
ns
Vee=50V
TA = 2SoC
5
IS
25
ns
Enable to OutPut,tpdo
Vee = SV
TA = 2SoC
7
16
23
ns
Enable to Output,
Vee = 5V
TA = 2SoC
6
14.
20
ns
tpdO
6
Propagation Delay to a Logical
"0" from Select to lA. tpdO
Vee = 5 OV
TA = 2SoC
Propagation Delay to a Logical
"1" from Data to Output, tpdl
Vee = S.OV
TA = 2SoC
Propagation Delay to a Logical
"a" from Data to Output,
"1" from Select to ZA,
tpdl
tpdl
~
-"
-.....
V
V
Vee = 5.0V
TA = 2SOC
.....
V
-1 S
Propagation Delay to a Logical
-"
UNITS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
deVices should be operated at these limits. The table of "Electrical Characteristics" prOVides conditions
for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the _55°C to +125°C temperature
range for the DM9322 and across the O°C to 70°C range for the DM8322. All typicals are gIVen for
Vce = S.OV and TA = 25°C.
Note 3: Only one output at a time should be shorted.
6-13
~
M
; illS
Series 9000
Q
.......
~
M
~
~
DM9334/DM8334 8-bit addressable latch
general description
The DM9334/DM8334 is a high speed 8-Bit
Addressable Latch designed for general purpose
storage applications in digital systems. It is a
multifunctional device capable of storing single
line data in eight addressable latches, and being a
one-of-eight decoder and demultiplexer with active
level High outputs. The device also incorporates
an active level Low common clear for resetting all
latches, as well as, an active level Low enable.
state. In the clear mode all outputs are Low and
unaffected by the address and data inputs.
When operating the device as an addressable latch,
changing more than one bit of the address could
impose a transient wrong address. Therefore, this
should only be done while in the memory mode.
The truth table below summarizes the operation
of the product.
The DM9334/DM8334 has four modes of operation
which are shown in the mode selection table. In
the addressable latch mode, data on the data
line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous
states. In the memory mode, all latches remain
in their previous state and are unaffected by the
data or address inputs.
features
• Serial to parallel capability
• 8-bits of storage with output of each bit
available
• Random (addressable) data entry
• Active high demultiplexing or decoding
capability
• Easily expandable
• Common clear
• Input clamp diodes limit high speed termination
effects
In the one-of-eight decoding or demultiplexing
mode, the addressed output will follow the state
of the D input with all other inputs in the Low
logic and connection diagrams
Dual·in·Line and Flat Packages
66
as
12
01
TOP VIEW
6·14
Q4
10
Q2
III
GNO
c
absolute maximum ratings
operattng conditions
(Note 1)
MIN
Supply Voltage
Input Voltage
Voltage Applied to Outputs
(Output High)
Output Current (de) (Output Low)
-{).5V to +7.0V
-{).5V to +5.5V
-{).5V to + V CC val ue
Supply Voltage (VCC)
DM8334
DM9334
+30mA
Storage Temperature Range
--B5"C to +150"C
Lead Temperature (Soldering, 10 seconds)
300"C
electrical characteristics
s:CD
Temperature (T A)
DM8334
DM9334
4.75
4.5
0
-55
w
MAX
5.25
5.5
+75
+125
W
UNITS
~
.......
C
V
V
s:CO
W
W
"C
"C
~
(Notes 2 and 3)
LIMITS
PARAMETER
CONDITIONS
Output High Voltage (V OH )
Vee = Min, IOH = -800flA
V IN = V 1H or V 1L (Truth Table)
Output Low Voltage (VOL)
Vee = Mm, IOL = 16 rnA
V ,N = V ,H or V'L (Truth Table)
Input High Level (V ,H )
Guaranteed I nput Logical High
MIN
TYP
(Note 2)
24
3.6
02
UNITS
MAX
V
04
V
V
20
Voltage for all Inputs
Input Low Level (V ,L )
Guaranteed I nput Logical Low
Voltage for all Inputs
Input Clamp Diode Voltage (V eD )
Vee == Mm, liN
Input Low Current (I,el
Vee
-
:=;
=
Max, VIN
E
A 2 , D,
Vee = Max, VIN
-15
V
-096
-144
-16
-24
mA
mA
10
15
40
60
flA
flA
= a 4V
E
AD, A"
V
-12 mA
AD, A" A 2 , D, C
Input High Current (I,H)
08
= 24V
C
= 55V
Input High Current (I'H)
Vee = Max, VIN
Output Short Crreult Current (lse)(Note 4)
Vee = Max, V OUT
Power Supply Current (Icc
Vee
= Max
switching characteristics
TA
= 25°C, CL = 50 pF, Vee = 5.0V
= OV
-30
-65
56
1.0
mA
-100
mA
86
mA
a
LIMITS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Turn Off Delay Enable tD Output (tPLH)
(See waveform a )
19
28
Turn On Delay Enable to Output (tPHd
(See waveform a.)
18
27
ns
ns
Turn Off Delay Data to Output (tPLH)
(See waveform b )
24
35
ns
Turn On Delay Data to Output (tPHd
(See waveform b.)
19
28
ns
Turn Off Delay Address to Output (tPLH)
(See waveform c.)
23
35
ns
Turn On Delay Address to Output (tPHL)
(See waveform c.)
21
35
ns
Turn On Delay Clear to Output (tPH d
(See waveform e )
21
31
ns
6-15
switching set-up requirements
PARAMETER
TA = 25°C, CL = 50 pF, Vee = 5.0V
LIMITS
CONDITIONS
MIN
TYP
MAX
Set·Up Time HIgh Data to Enable It, (H)]
(See waveforrT) d.)
20
Hold Time HIgh Data to Enable [t h (H)]
(See waveform d.)
0
13
ns
-10
Set·Up Time Low Data to Enable It, (LlI
(See waveform d.)
20
ns
14
Hold Time Low Data to Enable [th (L)]
(See waveform d.)
0
ns
-13
Set·Up TIme Address to Enable It, (A·E)]
(Note 5)
(See waveform f.)
10
5.0
ns
ns
Enable Pulse Width [tpw (Ell
(See waveform a.)
19
13
ns
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits The
table of "Electrical CharacterIStics" provides conditions for actual deVice operatIOn
Note 2: Unless otherwise specified mm/max limits apply across the --55°C to +125°C temperature range for the DM9334
and across the O°C to +75°C range for the DM8334 All tYPlcals are gIVen for
Vee
::=
50V and TAO': 25°C
Note 3: All currents mto deVice pms shown as positive, out of deVice pins as negative, all voltages referenced to ground unless
otherwise noted. All values shown as max or mm on absolute value baSIS
Note 4: Only one output at a time should be shorted
Note 5: The Address to Enable Set·Up Time IS the time before the High to Low Enable transition that the Address must be
stable so that the correct latch IS addressed and the other latches are not affected
Note 6: The shaded areas Indicate when the Inputs are permitted to change for predictable output performance
truth tables
MODE SELECTION
E
c
MODE
L
H
H
H
Addressable Latch
Memory
L
L
Active High Eight·
Channel Demultiplexer
H
L
Clear
PRESENT OUTPUT STATES
C
E
0
Ao
A,
A2
00
0,
°2
Q,
Q.
Q5
00
a,
L
H
X
X
X
X
L
L
L
L
L
L
L
L
CLEAR
L
DEMULTIPLEX
L
X
6·16
UNITS
~
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
···
L
L
L
L
H
ON'
··· ··· ···
H
H
L
L
H
H
H
X
H
L
H
L
H
H
H
···
H
H
L
X
X
X
0"
L
L
L
L
L
ON'
ON'
H
L
L
L
H
QN'
L
L
H
L
L
ON'
ON'
L
ON'
L
H
··· ··· ···
H
L
··
L
ON'
H
ON'
H
L
L
H
·
H
H
ON'
H
L
H
H
H
H
ON'
Don't Care Condition, L
~
L
···
Low Voltage Level, H ~ High Voltage Level, 0N.1 ~ PrevIous Output State
··
.·
..
ON'
L
ON'
H
MODE
MEMORY
ADDRESSABLE
LATCH
c
s:
Series 9000
(g
0)
...
o
......
C
s:CO
DM9601lDM8601 retriggerable monostable multivibrator
0)
general description
features
The DM9601/DM8601 is both pin-for-pin and
spec-for-spec interchangeable with the 9601 oneshot. Pulse widths range from 50 ns upward
depending upon the values of the external R &C
used. The retriggerable feature allows for output
pulse widths to be extended beyond the normal
range attainable with just a resistor and capacitor.
• Input Clamping Diodes
• Complementary DC Level Sensitive Inputs
• Flexibility of Operation-Optional Retrigger·
ing/Lockout Capability
• DTLlTTL Compatible Logic Levels
• High Speed Operation-Input Repetition
Rate> 10 MHz
• Output Pulse Width Range 50 ns to =
• Leading or Trailing Edge Triggering
• Complementary Outputs
...o
schematic and connection diagrams
L
Dual-I n-Line and Flat Package
I
ex
R
I
t''''~---II---.,
v"
A,
A,
B,
NC
B,
TOP VIEW
6-17
...o
CD
DM9601
absolute maximum ratings
CO
:E
c
Supply Voltage to Ground
Input Voltage
Voltage Applied to Outputs
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
...
......
o
CD
en
:E
c
-0.5V to +8.0V
-0.5V to +5.5V
-0.5V to +Vcc
-65°e to +150o e
_55°e to +125°e
300 0 e
electrical characteristics
TABLE I
Limits
Symbol
_55°C
Parameter
Mm.
VO"
Output High Voltage
+125°C
+25Q C
Max
M,n
24
24
Typ.
Max.
33
Mm.
Umts
Conditions
(Note 1)
Max.
24
V
Vee "'45V
IOH '" -012 rnA
(Note 21
VOL
Output Low Voltage
04
02
04
04
V
Vcc=45V
IOL = 10 rnA
(Note 2)
V,"
Input High Voltage
VOL
Input Low Voltage
I,
Input Load Current
IR
Input Leakage Current
Ise
Short Circuit Current
I'D
QUiescent Power
tpd'
Negative Tngger Input
to True Output
20
17
14
085
090
-16
085
V
Vee'" 4.5V
V
Vcc=55V
(Note 31
Vee'" 5 5V
-1 I
-16
-16
mA
15
60
60
"A
V,
VR
-10
-40
=0 4V
Vcc=55V
= 4 5V
Vee'" 5.0V
V OUT
Supply Dram
25
25
25
OV (Note 2)
mA
Vee == 5 5V
Vee'" 5.0V
25
40
ns
25
40
n,
Rx
tpd.
'"
= 5.0
Kll
Negative Tngger Input
to Complement Output
ex'" 0
C L '" 15 pF
tpw(mln)
tpw
CstrilV
Rx
Minimum True Output
Pulse Width
45
Pulse Width
30B
MaXimum Allowable
Wlrmg Capacitance
(Pm 13)
External Timing ReSistor
50
50
25
342
Rx = 5.0
"'
Vcc==50V
50
pF
Pm 13 to GND
25
kll
3.76
50
50
25
5.0
Note 1: Unless otherwise specified, RX::::; 10 Kn. between Pm 13 and Vee on all tests.
Note 2: Ground Pm 11 for VOL test on Pin 6, VOH test on Pm 8 and Ise test on Pm 8.
Open Pm 11 for VOL test on Pm 8, VOH test on Pm 6 and Ise test on PIn 6.
Note 3: Pulse test to determme VIH and VIL (Mm PW = 40 ns).
6·18
Kn
n,
65
Rx
= 10 Kll. C x = 1.000 pF
c
3:
(g
en
o
OM8601
absolute maximum ratings
Supply Voltage to Ground
Input Voltage
Voltage Applied to Outputs
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
...
-O.5V to +8.0V
-O.5V to +5.5V
-O.5V to +V cc
_65°C to +150°C
O°C to +75°C
300°C
........
c
3:
00
en
o
...
electrical characteristics
TABLE II
Limits
Symbol
o°c
Parameter
Mm,
VOH
Output High Voltage
+7SoC
+2S0C
Max.
2.4
Max.
Typ.
Mm.
2.4
3.4
Min.
Units
Conditions
(Note 1)
Max.
24
V
Vee "'4 75V
IOH '='-096mA
INote 21
VOL
045
Output low Voltage
045
02
045
V
Vee "'4 75V
IOL=128mA
INote 21
V'H
Input High Voltage
V'L
Input low Voltage
IF
Input Load Current
19
1.8
16
0.85
0.85
0.85
-1.6
-10
-1.6
-16
V
Vee = 4 75V
V
Vee'" 5.25V
(Note 3)
mA
Vee =525V
V, =045V
I"
Input Leakage Current
Ise
Short Circuit Current
Ipo
QUiescent Power
15
60
60
~A
Vee=525V
VA '" 4.5V
-10
-40
mA
Vcc=50V
V OUT
Supply Dram
tpdt
25
25
25
mA
= OV
(Note 2)
Vee "'525V
GND Pms 1 & 2
Negative Trigger Input
25
to True Output
40
ns
Vee "'50V
Rx = 5.0 Kn
t pd _
Negative Tngger Input
to Complement Output
40
25
ns
ex = 0
CL = 15 pF
Lpw~mlnl
Minimum True Output
~tpw
Pulse Width Vanatlon
Pulse Width
45
3.08
65
3.42
ns
3.76
~s
Vee =SOV
Rx = 10 Kn.C x = 1.000 pF
estray
Rx
MaXimum Allowable
Wiring Capacitance
(Pin 131
E)(ternal Timing Resistor
Note 1: Unless otherwise specified,
50
5.0
RX
50
=
50
5.0
50
5.0
50
pF
50
kn
Pm 13to GND
Vee on all tests.
Ise test on Pm 8
Ise test on Pm 6
10 Ki1 between Pin 13 and
Note 2: Ground Pin 11 for VOL test on Pin 6, VOH test on Pm 8 and
Open Pm 11 for VOL test on Pm 8, VOH test on Pin 6 and
Note 3: Pulse test to determme VIH and VIL (Min PW
=
40 ns).
6-19
....
o
<0
00
~
operating rules
c
.......
....
o
<0
en
1. An external resistor Rx and an external capacitor C x are required for operation. The value of
Rx can vary between the limits shown on
tables I and II. The value of C x is optional and
may be adjusted to achieve the required output
pulse width.
2. Output pulse width tpw may be calculated as
follows:
~
c
tpw
= 0.32 RxCx
[1 + ~·:1 (for Cx 2: 10
3
tance and noise pickup. If remote trimming is
required, Rx may be split up such that at least
Rx 1M IN) must be as close as possible to the
circuit and the remote portion of the trimming
resistor R < RXIMAX)-Rx
4. Set·up time(t 1 ) for Input trigger pulse >40 ns.
(See Figure 1)
Release time(t 2 ) for input trigger pulse >40 ns.
(See Figure 2)
5. Retrigger pulse width (see Figure 3) is calculated
as follows:
pF)
Rx in Kn, C x in pF and tpw in ns
For C x < 103 pF, see curve.
3. Rx and Cx must be kept as close as possible to
the circuit in order to minimize stray capaci-
tw
[ 0.7]
= tpw + t pd + = 0.32 Rx Cx 1 + Rx + t pd +
~,.
Figure 1
Figure 2
INPUT
Q. OUTPUT
~
i
Figure 3
6·20
L
c
3:
CD
Series 9000
en
o
N
.......
c
3:
CO
en
o
DM9602/DM8602 dual TTL/monostable multivibrator
general description
features
The TTL/Monostable DM9602/DM8602 dual retriggerable, resettable monostable multivibrator
provides an output pulse whose duration and accuracy is a function of external timing components.
The DM9602/DM8602 has excellent immunity to
noise on the Vee and ground lines. The DM9602/
DM8602 uses TTL inputs and outputs for high
speed and high fanout capability and is compatible
with all members of the TTL family.
• 70 ns to
•
•
•
•
•
00
N
output width range
Resettable and retriggerable 0% to 100% duty
cycle
TTL input gating-leading or trailing edge
triggering
Complementary TTL outputs
Optional retrigger lock-out capability
Pulse width compensated for Vee and temperature variations
logic and connection diagrams
C,
C,
R,
V'"
10
n
CD
CD
13
Dual-In-Line and Flat Package
v'"
"
,,-
,.-
C,
R,
C,
R,
CD
13
CD
," ,.
BND
TOP VIEW
"INS fOR EXTERNAL TIMING
6-21
N
o
CD
CO
absolute maximum ratings
operating conditions
........
N
Supply Voltage
Input Voltage (Note 2)
OUtput Voltage
Supply Voltage (Vee)
DM9602
DM8602
~
C
7.0V
5.5V
5.5V
Storage Temperature Range
-£5°e to +150o e
Lead Temperature (Soldering, 10 seconds)
300 0 e
o
CD
0')
MIN
MAX
4.5
4.75
5.5
5.25
UNITS
V
V
+125
+70
°e
°e
Temperature (T A)
DM9602
DM8602
~
-55
0
C
electrical characteristics
(DM9602) (T A = -55°C to +125°C, Vee = 5.0V ±10%)
LIMITS
PARAMETER
-55°C
CONDITIONS (Note 3)
MIN
Output High Voltage (V OH )
Vee'" 4 5V, IOH =-0 SOmA
(Note 2)
Output Low Voltage (Vod
Vee =45V,l oL '" 16mA
TYP
+2S"C
MAX
24
MIN
TYP
24
33
04
0.2
+12S"C
MAX
MIN
TYP
UNITS
MAX
24
V
04
04
V
(Note 21
Input High Voltage (V 1H )
Guaranteed Input High Threshold Voltage
Input Low Voltage (V 1L )
Guaranteed Input Low Threshold Voltage
Input Low Current (IlL)
Vee =55V,V'N =04V
V cc =45V,V 1N =04V
Input High Current (lIH)
V cc =55V,V 1N =45V
Input Clamp Voltage
Vee =45V,I L =-12mA
-15
Short CncUit Current Oscl
Vee =55V,VOUT = 1 OV
(Note 2)
-'25
QUiescent Power Supply
Dram (Ipc)
Vee'" 50V
Negative Tngger I nput to
True Output (tPLH)
Negative Trtgger Input to
Complement Output (tPHd
(VCLAMP)
20
17
1.5
085
-16
-124
-11
-097
10
45
V
090
085
V
-16
-124
-16
-1.24
mA
mA
60
60
~A
V
rnA
39
45
Vee =50V,R x =50kn,
C X = 0, C L = 15 pF
25
35
"'
Vee =50V,R x =50kn,
ex = 0, CL '" 15 pF
29
43
ns
Mmlmum True Output
Pulse Width (tMIN)
Vee'" 5 OV. Rx '" 5 0 kn,
ex '" 0, CL = 15 pF
72
90
ns
Mmlmum Complement
Output Pulse Width (t MIN I
Vee'" 50V, Rx = 50kn,
Cx =O,C L '" 15pF
78
100
ns
Pulse Width (t)
Vee'" 5.0V, Ax '" 10 kn,
Cx == 1000 pF
342
376
~s
MaXimum Allowable Wiring
Cap lPms 2 and 14) (CSTRA y)
Pms 2 and 14 to Ground
Tlmmg ReSIStor (Ax)
308
50
50
electrical characteristics
25
45
50
50
25
50
rnA
50
pF
25
kQ
(DM8602) (T A = O°C to +75°C, Vee = 5.0V ±5%)
LIMITS
PARAMETER
o°c
CONDITIONS (Note 3)
MIN
6·22
Output High Voltage (VOH )
Vee =4 75V, IOH =--oaOmA
(Note 2)
Output Low Voltage (VOL)
Vee'" 4 75V, IOL:= 16 mA
(Note 2)
Input High Voltage (V 1H )
Guaranteed Input High Threshold Voltage
Input Low Voltage (Vld
Guaranteed Input Low Threshold Voltage
Input Low Current (I ILl
Vee'" 5 25V, VIr. = 0 45V
Vee'" 4 75V, VIN '" 0 45V
TYP
+25°C
MAX
24
MIN
TYP
24
34
045
19
OJ<
+75°C
MAX
TYP
UNITS
MAX
24
045
18
V
045
165
085
-16
MIN
085
-10
-141
V
V
085
V
-141
-16
-141
mA
mA
60
60
~A
-16
Input High Current (lIH)
Vee'" 5 25V, VIN '" 4 5V
Input Clamp Voltage (VeLAMP)
Vee'" 4 75V, I L
-12 mA
-15
V
Short Circuit Current Uscl
Vee == 5 25V, V OUT = 1 OV
(Note 2)
-35
mA
Quiescent Power Supply
Dram (lpo)
Vee'" 5 OV, Ground Pms 1
and 2
'"
10
52
39
50
52
rnA
c
electrical characteristics (con't)
s:
(D
(DM8602) (T A = o°c to +75°C, Vee = 5,OV ±5%)
c:n
o
N
LIMITS
PARAMETER
o°c
CONDITIONS (Note 3)
+25°C
+75°C
UNITS
"'C
TYP
MAX
25
40
True Output (tPLH)
Vee'" 5 OV, Rx ~ 5.0 kil,
ex ",o,e L == 15pF
"'
s:00
Negative Trigger I nput to
Complement Output (tPHLJ
Vee == 5 av, Rx '" 5 0 kn,
ex '" 0, C L '" 15 pF
29
48
n,
o
Minimum True Output
Pulse Width (t M1N )
Vee "'50V,R x =50kn,
ex '" 0, C L '" 15 pF
72
100
"'
Minimum Complement Output
Pulse Width (tM IN)
Vee"" 5 av, Rx '" 5.0 kU,
ex == D, C L '" 15 pF
78
110
"'
Pulse Width (t)
Vee'" 5 OV, Rx '" 10 kil,
342
376
Maximum Allowable WIring
Pins 2 and 14 to Ground
MIN
Negative Trigger J nput to
ex
TYP
MAX
MIN
MIN
TYP
MAX
c:n
N
3 08
"'
== 1000 pF
50
50
50
pF
50
kll
Cap (Pms2and14){CSTRAY)
Timing Resistor (R x )
50
50
50
50
50
Note 1: The maximum Vee value of 8.0V is not the primary factor In determining the maximum Vee which may be applied
to a number of Interconnected devices. The voltage at a High output IS approximately 1.0 VeE below the Vee voltage, so the
primary limit on the Vee IS that the voltage at any input may not go above 5.5V unless the current is limited. This effectively
limits the system Vee to approximately 7.0V.
Note 2: Because of the input clamp diodes, excess current can be drawn out of the inputs if the de input voltage IS more negative than -o.5V. The diode is designed to clamp off large negative ae swings associated with fast fall times and long lines. This
maximum rating IS Intended only to limit the steady state input voltage and current.
Note 3: Unless otherwise noted, 10 kn resistor placed between Pin 2 (14) and Vee, for all tests. (RX)
Note 4: Ground Pin 1 (15) for VOL on Pin 7 (91, or for VOH on Pin 6 (101, or for ISC on PinS 6 (101; also, apply momentary
ground to Pin 4 (121. Open Pin 1 (15) for VOL on Pin 6 (10), or for VOH on Pin 7 (9), or for ISC on Pin 7 191,
truth tables
Triggering Truth Table
TTL Input Load and Drive Factors
INPUTS
HIGH
3,4,5,11,12,13
OUTPUTS
1U L
I
I
5(111
LOW
1U L
16 U L
J
LOW
I 8UL
OPERATION
4(121
3(131
H~L
L
H
Tngger
H
L-H
H
Trigger
X
X
L
Reset
DRIVE FACTOR
HIGH
6,7,9,10
PIN NO'S,
LOAD
H
=
HIgh Voltage level 2. VIH
l
=
low Voltage Level :5 Vll
x
=
Don't Care
H---L '" HIgh to Low Voltage Level TranSItIon
1 Unit load {U l J = GOllA HIGH/l G rnA lOW
L-H '" low to High Voltage Level TransitIon
6,23
f/)
...
CD
Series 10,000
CD
en
...a
.oo
REFERENCE
o
o
The following table references all Physical Dimension Drawings, Waveforms, and Test Circuits for the devices
in this section. For Order Numbers, see below.' Refer to the alpha·numerlcal index at the front of this
catalog for complete device title and function. Packages (pages I thru VI) are in the back of the catalog.
DATA SHEETS
PACKAGES
Molded DIP (NI
Devices
DM10l0l
DM10l02
DM10l05
DM10l06
DM10107
DM10l09
DM10ll0
DM10lll
DM10112
DM10115
DM10116
DM10117
DM10118
DM10119
DM10121
DM10124
Pg.
7·1
7·3
7·5
7·7
7·9
7·11
7·13
7·15
7·17
7·19
7-21
7·23
7·25
7·27
7·29
7·31
Fig.
Pg.
Cavity DIP (D)(JI
Fig.
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Pg.
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Type
Flat Pack (F)(W)
Metal Can (G)(H)
Fig.
Fig.
Pg.
Type
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
Pg.
Type
WAVE·
FORMS
TEST
CIRCUITS
Fig.
Pg.
Fig.
Pg.
41
41
41
41
41
41
1()'18
10·18
1()'18
10·18
10·18
10·18
10
10
10
10
10
10
10·2
10·2
10·2
10·2
10·2
10·2
'Order Numbers: use Device No. suffixed with package letter, i.e. DM10l01J.
7-i
c
...s:
...oo
...
Series 10,000
DM10101(MC10101) quad OR/NOR gate with strobe
general description
The DM10101 quad gate IS a low power, high
speed, standard ECl logic device. High Z input
pulldowns allow high DC and AC fanout and
elim inate the need to tie unused inputs to an
external supply. The open emitter outputs allow
maximum flexibility in the selection of termina·
tion techniques and minimize the power requirements when driving transmission lines. Wire"OR"ing of outputs is available with the open
emitter outputs.
applications
The DM10l0l is useful In control, bussing and
communications in high speed central processors,
high speed peripherals, digital communications
systems, minicomputers and instrumentation. This
device is commonly used for control and bussing
data by using the wire OR capability of the basic
ECl gate and/or the common enable input. The
complementary outputs on all gates makes this
part useful as a quad line driver for twisted pair
lines thus reducing package count.
features
3.5 ns
•
Slow rise and fall times
•
High speed
2.0 ns
•
low power
25 mW/gate
•
•
High fanout
50n line driving capability
50 mA/output
•
High Z input pulldowns
•
Open emitter follower outputs
•
Wire OR capabi lity
•
Complementary output for added versatility
•
Standard end power pins for conventional layout
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
Dual~1 n-Line
Package
VCC2
15
"
0
14
11
!O
Vee1
V"
TOP VIEW
8
V"
7-1
...
...
o
o
...:E
absolute maximum ratings
\
Q
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
lead Temperature (Soldering, 10 sec)
oto Vee
50mA
-30°C to +85°C
-55°C to +125°C
300°C
electrical characteristics
@TEST
TEMP
30 e
+25°C
D
+85°C
DM'0101
PIN
CHARACTERISTIC
Power Supply Drain Current
Input Current
logiC ''1'' Output Voltage
SYMBOL
MIN
MAX
I,
8
ImH
13
-
-
l,nH
12
-
ImL
12.13
-
-
-108
-089
-096
-108
-089
-096
,.
-108
-089
-108
9
VOH
VOL
logiC "a" Threshold Voltage
VOHA
VOLA
V'HA
MIN
-089
081
-070
-189
-185
-1206
-1105
-1825
-'035
TVP
MIN
MAX
-
-
V••
mAde
-
-
-
-
8
1,16
"Ad.
13
12
-
-
8
1,16
8
1,16
8
1,16
8
1,16
8
8
1,16
8
8
1,16
26
-
/-lAde
-
-
-
-
05
-
/JAde
-
-089
-070
Vd.
12
-
-
-081
-089
-070
Vdc
13
-
-
-098
-
-081
-081
-089
-070
Vd.
-089
-098
-
-081
-089
-070
Vd.
-189
-1675
-185
-165
-1825 -1615
Vd,
,.
,.
-189
-1675
-185
-165
-1825 -1615
Vd.
-189
-1675
-185
-165
-1825 -1615
Vd.
12
-189
-, 675
-185
-
-
-165
-1825 -1615
Vd.
13
9
-108
-098
-
-
"
-108
-098
-
15
-108
-
-098
15
-108
-
-
-098
9
-
-1655
"
15
15
-1655
-1655
-1655
-
12,13
13
12
13
Vd.
-
-
Vd.
-
-
-091
-
Vd,
-
-
-091
-
Vd.
-
-091
-
Vd.
-
-091
-
Vd.
-
-163
-1595
Vd.
-
-163
-1595
Vd.
-1 B3
-
-1595
-163
-
-1595
1,2+,5_
t ,2_ ,5+
1,2_9_
f20to 80%)
Fall Trme
(201080%
15
15
"
"
1'5+
15
Ig.
9
t ,5 _
15
Ig.
9
-
-
-
10
20
2"
-
10
20
10
20
2"
29
10
20
29
11
20
33
11
20
33
11
20
33
11
20
33
-
-
-
-
-
-
-
-
-
-
-
"'
"'
-
"'
'"
"'
"'
"'
-
"'
-
-
-
1,16
8
1,16
8
8
1,16
-
1,16
1,16
8
1,16
12
8
1,16
13
8
1,16
12
8
1,16
13
8
1,16
1,16
13
-
GND
-
12
12
-
13
-
8
8
Pul"
-32V
+20V
Pulse
I,
t ,2+9+
RrseTrme
-
12
Swrtchlng Times
(50-ohm loadl
Propagation Delay
(Vee)
V,LA
MAX
26.
-
V
V
V
V.HA
MIN
-
-
UNITS
V,L
MIN
20
"
"
V••
-52
-52
-52
LISTED BELOW
MAX
550
-150
-1476
-144
V,H
MAX
-
-
VILA
MAX
TEST VOLTAGE APPLIED TO PINS
UNITS
+86°C
-
9
LogiC "1" Threshold Voltage
MIN
V,L
MIN
TEST LIMITS
+25°C
TEST
15
LogIC "0" Output Voltage
_30o e
UNDER
TEST VOLTAGE VALUES
V,H
MAX
001
1,16
-
12
15
8
1,16
12
15
1,16
12
9
8
8
-
12
"
8
1,16
8
1,16
8
1,16
-
12
"
8
1,16
-
12
"
8
1,16
12
12
15
15
1,16
Note: Each DM10,OOO se"es Circuit has been deSigned to meet the DC specifications shown In the test table, after thermal
equilibrium has been established. The cirCUit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test pro~
cedures are shown for only one gate. The other gates are tested in the same manner.
7·2
c
...o
...o
~
Series 10,000
N
DM10102(MC10102) quad gate
genera I description
The DM10102 quad gate is a low power, high
speed, standard ECl logic device. High Z input
pulldowns allow high DC and AC fanout and
eliminate the need to tie unused inputs to an
external supply. The open emitter outputs allow
maximum flexibility in the selection of termination techniques and minimize the power requirements when driving transmission lines. Wire Oring
of outputs is available with the open emitter
outputs.
applications
The DM 101 02 is very useful in control, bussing,
and communications in high speed central processors, high speed peripherals, digital communications systems, minicomputers and instrumentation.
This device IS commonly used for control and
bussing data by using the wire OR capability of
the basIc ECl gate. The additional non-inverting
output on one gate adds to the flexibility of this
part.
features
3.5 ns
Slow rise and fall times
2.0 ns
High speed
25 mW/gate
lowpower
50 rnA/output
High fanout
50n line driving capability
High Z input pulldowns
Open emitter follower outputs
Wire OR capability
Complementary output for added versatility
Standard end power pins for conventional layout
• Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
•
•
•
•
•
•
•
•
•
•
schematic and logic diagrams
Dual-In-Line Package
"
15
t---+---o13
v"
v""
TopvrEW
11
•
1Z
v"
7-3
N
...
o
o
:!E
...
absolute maximum ratings
c
-BV
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30°C to +85°C
-55°C to +125°C
300°C
electrical characteristics
@TEST
TEMP.
30
0
e
+2SoC
+85°C
Power Supply Dram Current
Input Current
Logic "1" Output Voltage
LogiC "0" Output Voltage
LogiC "1" Threshold Voltage
LogiC "0" Threshold Voltage
SYMBOL
UNDER
TEST
_30 c e
MAX
MIN
-
05
I.
8
12
I,nt.
12
-
Voe
VOHA
VOLA
9
-106
-089
-096
9
-106
-089
-096
15
-106
-089
-096
15
-106
-089
-096
9
-189
-1675
-185
9
-189
-1675
-185
15
-189
-1675
-185
15
-189
-1675
-185
9
-108
-098
•
-108
-
15
-108
15
-108
•
-1655
15
-
15
-
-1655
9
V 1HA
MIN
MAX
V••
UNITS
089
-081
-070
189
-185
-1825
-1.205
-1105
-1035
-150
-1475
-144
52
-52
-52
V
V
V
-1655
-1655
-098
-098
-098
-
TVP
LISTED BELOW:
+85°C
UNITS
V,H
MAX
VOL
MIN
VIHA
-
MAX
MIN
MAX
20
26
mAde
-
-
265
-
-
-
-
/lAde
12
-
-
-
-
,uAde
-
-081
-089
-070
Vdo
12
-081
-089
-070
Vdo
13
-081
-089
-070
Vdo
12
-081
-089
-070
Vdo
-
-165
-1825 -1615
Vdo
12
-
-
-165
-1825 -1615
Vdo
-
13
-165
-1825 -1615
Vdo
12
-
-165
-1825 -1615
Vdo
13
-
Vdo
-
Vdo
Vdo
-
-1595
Vdo
-
-1595
Vdo
-
-163
-1595
Vdo
-1595
Vdo
-
-091
-163
-
-163
-1.63
-091
-091
-091
Vdo
-
t 12+ 15-
15
t12_ 15+
15
t 12+ 9+
9
t 12-9Rise Time
(20 to 80%)
Fall Time
(20 to 80%
•
t 15+
15
t 15_
15
tg-
9
,,.
9
-
-
-
10
20
2.
10
20
29
10
20
29
10
20
2.
11
20
3.3
11
20
33
11
20
33
11
20
33
-
-
n,
-
n,
-
n,
-
n,
-
n,
-
n,
n,
n,
-
MIN
12
13
-
SWitching Times
(5(}.ohm load)
Propagation Delay
VILA
TEST VOLTAGE APPLIED TO PINS
+25°C
MIN
l,nH
VOH
VOL
MIN
DM10102 TEST LIMITS
PIN
CHARACTERISTIC
TEST VOLrAGE VALUES
V,H
MAX
-
V,LA
MAX
-
12
13
(Vee)
V••
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-
12
8
1,16
-
13
8
1,16
-
12
8
1,16
13
8
1,16
8
1,16
-
12
13
8
1,16
-32V
+20V
Pulse
In
Pulse
Out
12
15
8
1,16
12
15
8
1,16
12
9
8
1,16
12
9
8
1,16
12
15
8
1,16
12
9
8
1.16
12
15
8
1,16
12
9
8
1,16
Note: Each DM10,OOO series CirCUit has been deSigned to meet the DC speCifications shown in the test table, after thermal
equilibrtum has been established. The CirCUit IS In a test socket or mounted on a prtnted Circuit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
7-4
GNO
c
...
!:
...
Series 10,000
o
o
en
DM10105(MC10105) triple 2-3-2 OR/NOR gate
features
general description
The DM10105 triple gate is a low power, high
speed, ECl logic device with the standard ECl
high Z inputs and open emitter outputs. This
offers the system designer maximum flexibility
in layout and design. The open emitter output
allows a maximum number of gates to be wire
ORed. This device is useful in high speed digital
communications systems, central processors, peri·
pheral controllers, minicomputers, instrumenta·
tion, and testing systems. The DM10105 is a
general purpose gate which generates both true
and complement of a control signal and can be
used to drive twisted pair lines.
3.5 ns
• Slow rise and fall times
• High speed
•
tpd
= 2.0 ns
low power
50 rnA/output
• High fanout
• Open emitter follower outputs for wire OR
• Complementary outputs simultaneous functions
• Standard end power pins conventional layout
• Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
I.
"
13
Dual·ln·Lin. Package
TOPVIEW
v"
1.
11
7·5
In
o....
o
....
absolute maximum ratings
c
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
:E
-8V
o to VEE
50mA
-30 C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
(Volts)
V,H
MAX
VIL
MIN
VIHA
_30 o e
-0890
-1890
-1205
-1500
-52
+2SOC
-0810
-1850
-1105
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
SYMBOL
PIN
UNDER
TEST
Power SupplV Dram Current
-lOoe
MAX
I,
Input Current
l,nH
Logrc"l"Output Voltage
VOH
LogiC 'Q"Qutput Voltage
Voe
LogiC "0" Threshold Voltage
V OHA
VOLA
TYP
15
AlseTlme
(20 to 80%)
Fall Time
(20 to 80%)
MIN
MAX
V,H
MAX
VIL
MIN
V1HA
MIN
VILA
MAX
VEE
21
mAde
1,16
265
~Adc
1,16
05
~Adc
1,16
-0960
-0810
-0890
-0700
Vdo
1,16
-1060
-0890
-0960
-0810
-0890
-0700
Vdo
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vdo
1,16
-1890
-1675
-1850
-1650
-1825
-1615
Vdo
1,16
1,16
-1080
-0980
- 910
Vdo
-1080
-0980
- 910
Vdo
1,16
-1655
-1630
-1595
Vdo
1,16
-1655
-1630
-1595
Vdc
1,16
Pulse
I,
Pulse
0",
-32V
+20V
t4+3_
20
1,16
t 4-3+
20
1,16
t4+2+
20
1,16
t4:2_
20
1,16
t"
20
1,16
t"
20
1,16
t,
20
1,16
t,_
20
1,16
Note: Each DM10,OOO series CirCUit has been designed to meet the DC specifications shown In the test table, after thermal
equillbrtum has been established. The CirCUit IS 10 a test socket or mounted on a prlOted CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm reSistor to -2.0 volts, Test procedures are shown for only one gate. The other gates are tested in the same manner.
7-6
(Vee)
GNO
-0890
SWitch 109 Times
(50 ohm load)
Propagation DeidY
MAX
-1060
l,nL
logIC "" Threshold Voltage
MIN
VEE
+8SoC
+2SoC
UNITS
MIN
VILA
MAX
TEST VOLTAGE APPLIED TO
PINS LISTED VELOW
DM10105 TEST LIMITS
CHARACTERISTIC
MIN
Series 10,000
DM10106(MC10106) triple 4-3-3-input NOR gate
general description
features
The DM10l06 triple gate is a low power, high
speed, ECl logic device with the standard ECl
high Z inputs and open emitter outputs. This offers
the system designer maximum flexibility in layout
and design. The open emitter output allows a
maximum number of gates to be wire ORed. This
device is useful in high speed digital communica·
tions systems, central processors, peripheral con·
trollers, minicomputers, instrumentation, and test·
ing systems. Busing data with wire OR is a useful function of the DM10106 and it is also useful
as a general purpose gate.
• Slow ri se and fall times
•
3.5 ns
High speed
•
low power
•
High fanout
tpd
= 2.0 ns
50 mA/output
• Open emitter follower outputs for wire OR
• Standard end power pins conventional layout
• Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
Dual-In-Line Package
TOP VIEW
•
v"
7·7
CD
...o
o...
::E
absolute maximum ratings
Q
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
OtOV EE
50mA
-30 C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP.
(Volts)
V,"
MAX
VIL
MIN
VIHA
MIN
MAX
-30"C
-0890
-1890
-1205
-1500
-52
+2S"C
-0810
-1850
-1105
-1475
-52
+85"C
-0700
-1825
-1035
-1440
-52
DMl0106 TEST LIMITS
CHARACTERISTIC
SYMBOL
PIN
UNDER
TEST
Power Supply Dram Current
Input Current
LogiC "I" Output Voltage
LogiC "0" Output Voltage
LogiC "I" Threshold Voltage
LogiC "0" Threshold Voltage
_30 o e
MAX
MIN
-
-
I,
8
l,nH
4
l,nL
4
-
VOH
3
-1060
-0890
-0960
Voc
3
-1890
-1675
-1850
V OHA
3
3
-1080
-
-0980
-
-1655
VOLA
TYP
15
05
-
-
+8S"C
MAX
UNITS
V,"
MAX
VIHA
VILA
MIN
MAX
8
1,16
-
-
8
1,16
4
-
8
1,16
4
-
-
8
1,16
-
8
1,16
1,16
-
8
8
-32V
+20V
1,16
MAX
-
~Adc
-
-
-
J.lAdc
-
-0810
-0890
-0700
Vd,
-
-1650
-1825
-1615
Vd,
-
-0910
-
Vd,
-
-
-1630
--
-1595
Vd,
-
-
21
mAde
4
4
AiseTIme (20 to 80%1
Fall Time (20 to 80%1
-
t4+3_
3
t4_34
3
-
I"
3
-
1,-
3
-
-
-
20
20
20
20
-
-
-
-
-
eo
-
eo
eo
eo
-
-
SWitching Times
(50 ohm load)
Propagation Delav
-
(Vee)
VIL
MIN
MIN
265
VEE
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
+2S"C
MIN
VILA
-
4
4
VEE
GND
1,16
Pulse
10
Pulse
4
3
8
4
3
8
1,16
4
3
3
8
8
1,16
4
0",
1,16
Note: Each DM10,000 series circuit has been designed to meet the DC specifications shown In the test table, after thermal
eqUilibrium has been established. The CirCUit IS in a test socket or mounted on a printed cirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts, Test procedures are shown for only one gate. The other gates are tested in the same manner.
7-8
c
3:
....
o
....
o
Series 10,000
~
DM10107(MC10107) triple EXCLUSIVE-OR/NOR gate
general description
features
The DM10l07 triple gate is a low power, high
speed, ECl logic device with the standard ECl
high Z Inputs and open em itter outputs. Th is
offers the system designer maximum flexibility in
layout and design. The open emitter output allows
a maximum number of gates to be wired ORed. This
device is useful in high speed digital communica·
tions systems, central processors, peripheral con·
trollers, minicomputers, instrumentation, and test·
ing systems. The DM10l07 provides the Exclusive
OR and the complement function simultaneously.
This device can selectively invert control signals,
and can be used to bu ild special purpose adders or
counters.
• Slow rise and fall times
3.5 ns
tpd;
• High speed
2.0 ns
• low power
50 rnA/output
• High fanout
• Open emitter follower outputs for wire OR
• Standard end power pins conventional layout
• Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
.
Dual·ln·Line Package
"
v",
III
IIVCCl
v~.
v"
TOf'VIEW
.
vu
7·9
absolute maximum ratings
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-BV
o to VEE
50mA
-30 C to +B5°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@lEST
(Volts)
TEMP
CHARACTERISTIC
Power Supply Dram Current
Input Current
SYMBOL
TEST
MIN
MAX
MIN
I,
8
-
-
-
l,nH
4,9,14
l,nL
LogiC "1" Output Voltage
LogiC "0" Output Voltage
logiC "1" Threshold Voltage
logiC "0" Threshold Voltage
VO"
Voc
VOHA
VOLA
.
-
-1060
-0890
Rise Time
Fall Time
(201080%)
-1850
-1 105
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
MAX
-
-
-
UNITS
mAde
#lAde
-
265
-
/JAde
~Adc
VIHMAX
-0810
-0890
-0700
Vd,
4,5
-
-0810
-0890
-0700
Vd,
-
4,5
-0810
-0890
-0700
Vd,
4
5
3
-1060
-<>890
-0960
-0810
-0890
-0700
Vd,
5
2
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
2
-1890
-1675
-1850
-1650
-1825
-1615
3
1,16
8
1,16
4
-
8
1,16
4
5
-
-
8
1,16
Vd,
5
4
-
8
1,16
8
1,16
8
1,16
4,5
-
8
1,16
-
4,5
8
1,16
4
5
8
1,16
5
4
8
1,16
4
5
-1675
-1850
-1650
-1825
-1615
Vd,
4,5
-
-1890
-1850
-1650
-1825
-1615
Vd,
-1080
-0980
3
-1080
3
-1080
-
Vd,
-1080
-
-0910
2
-
-
4,5
2
-1595
Vd,
-1595
Vd,
-
-
2
-1655
-
-1655
TVP
MAX
Inputs
-
'""
Output
-
Inputs
-
5,7 or 15
-
to either
..
Ouput
..
-
-0910
-1630
-
Vd,
Vd,
Vd,
-1595
Vd,
-1630
-
-1595
Vd,
TVP
MAX
TVP
MAX
UNITS
-
20
-
-
"'
5,7,15
"'
5,7,15
28
-
25
-
25
-1655
-1655
20
20
20
28
28
28
-1630
-1630
-
-
-
-
-
-
-
-
1,16
-
8
-1675
-0980
1,16
1,16
8
-
-
-1890
-0910
-
3
-0980
1,16
8
8
-
-0960
-0910
1,16
8
VILA MAX
-
-0960
-0980
GND
8
VIHAMIN
-
..
-0960
VEE
VILMIN
All Inputs
-0890
to either
"
,"
1201080%J
-52
-0890
4,9 or 14
,--
-1500
-1060
,~
,~
-1205
-1060
-
,'"
-1890
-0810
2
SWitching Times (SOn load)
,"
v"
-0890
3
3
I"
-
2
2
,"
28
MIN
05
3
Propagation Delay
VILA MAX
_30°C
+8SoC
MAX
355
5,7,15
VIHA MIN
TEST VOLTAGE APPLIeD TO PINS LISTED BELOW
+2SOC
_30°C
UNDER
V1LMIN
+2SOC
DM10107 TEST LIMITS
PIN
VIHMAX
"'
5,7,15
"'
5,7,15
"'
"'
4,9,14
-
~
"'
4,9,14
-
"'
4,9,14
-
"'
"'
4,9,14
4,9,14
4,9,14
8
1,16
5
4
8
1,16
4,5
-
8
1,16
-
4,5
8
Pulse In
Pulse Out
-32V
Input
Corresponding
8
1,16
4,9,or
ORINOR
8
1,16
14
Outputs
8
1,16
8
1,16
Input
Corresponding
8
1,16
5,7, or
OR/NOR
8
1,16
15
Outputs
8
1,16
8
1,16
8
1,16
8
1,16
Any Input
Any Input
Corresponding
OR/NOR
Outputs
* IndiVidually test each Input applYing Vu. , or V1L to Input under test
* * Any Output
Note:
Each DM10,OOO series CirCUit has been deSigned to meet the DC speCifications shown
eqUilibrium has been established.
flow greater than 500 linear fpm
The· CirCUit IS In a test
IS malntal~ed. Outputs
7-10
In the test table, after thermal
socket or mounted on a printed CirCUit board and transverse air
are terminated through a 50-ohm resistor to -2.0 volts. Test pro-
cedures are shown for only one gate. The other gates are tested in the sarne manner.
1,16
+20V
c
s:
....
Series 10,000
o
....
o
CD
DM10109 (MC10109) dual 4-5-input OR/NOR gate
genera I description
features
Open emitter outputs, high Z inputs, high speed,
and low power are the outstanding characteristics
of the DM10l09 dual gate. The high Z inputs and
open emitter outputs allow a maximum fanout
with minimum power requirements. Slow rise and
fall times, characteristic of EC L 10,000 series
gates, allow conventional Interconnect techniques.
The open emitter outputs allow a maximum num·
ber of outputs to be wire ORed and stili drive a
heavy fanout. In addition, unused outputs may be
left open and do not waste power. This device is
designed for use in high speed central processor,
peripheral controllers, minicomputers, digital com·
munications systems, and instrumentation and test·
Ing systems.
•
Slow rise and fall times
•
High speed
•
Low power
•
High fanout
•
Multiple open emitter follower outputs
•
Multiple wire OR capability
•
Complementary outputs
•
Standard end power pins
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
The DM10l09 is a general purpose gate that can
be used in control. The complementary outputs
are also useful in driving twisted pair lines when
it IS necessary to send control signals or data a long
distance.
3.5 ns
tpd
= 2.0 ns
50 mA/output
schematic and connection diagrams
Dual-In-Line Package
.
v"
7·11
en
o.o
.::!
c
absolute maximum ratings
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
_30° C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
DM10109
Power Supply Dram Current
Input Current
SYMBOL
•
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Yo,
V OHA
VOLA
MAX
MIN
TVF
-
-
10
-
265
05
-
-
~
2
-1060
-0890
-0960
3
-1060
-0890
-0960
2
-1890
-1675
-1850
3
-1890
-1675
-1850
-
2
-1080
-0980
-
-0980
-
-
3
-1080
-
2
-
-1655
3
~
-1205
-1500
+2SoC
-0810
-1850
-1 105
-1475
~5
2
+8SoC
-0700
-1825
-1035
-1440
~5
2
-1655
MAX
MIN
MAX
-
"
~
~
~Adc
-
,uAde
-0890
-0700
Vd,
-0810
-0890
-0700
Vd,
-1650
-1825
-1615
Vd,
-1650
-1825
-1615
Vd,
-
-0910
-1630
V,L
VIHA
VILA
MAX
MIN
MIN
MAX
mAde
-0810
-1630
V,H
~
Vd,
-0910
-
Vd,
-
-1595
Vd,
-1595
Vd,
••
-
•
~
•
~
-
t"
2
-
t4'3
3
t 4 _3 +
3
Rise Time
t,.
2
-
(20
I,.
3
t,
2
~
t,
3
~
Fall Time
(20 to 80%)
~
~
10
20
29
-
~
10
20
29
-
-
10
20
29
-
~
10
20
29
-
11
20
33
-
11
20
33
-
11
20
33
-
11
20
33
-
_.
~
-
~
-
~
~
~
~
"'
"'
"'
"'
"'
"'
"'
"'
1,16
8
1,16
~
8
1,16
1,16
-
-
8
-
~
8
1,16
•
-
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-
~
-
-
-
~
4
-
-
~
~
~
4
•
•
~
Pulse
0",
8
1,16
-32V
+20V
•
2
8
1,16
-
-
4
2
8
1,16
-
-
4
3
8
1,16
-
3
8
1,16
-
-
2
8
1,16
3
8
1,16
2
8
1,16
3
8
1,16
~
-
~
-
-
•
•
4
•
4
Note: Each DM10,OOO series Circuit has been deSigned to meet the DC specificatiOns shown In the test table, after thermal
eqUIlibrium has been established. The CirCUit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm resIstor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner.
7·12
GNO
8
4
-
-
VEE
-
10
2
80%)
52
UNITS
Pulse
t 4• 2+
to
VEE
MAX
1890
SWitching Times
(50-ohm load)
Propagation Delay
VILA
MIN
-0890
TEST VOLTAGE APPLIED TO
+8S"C
MIN
-
l,nH
V'HA
_30°C
TEST LIMITS
+25 G C
•
8
V OH
_30°C
-
I,
l,nL
High Output Voltage
UNDER
TEST
VIL
MIN
PINS LISTED BelOW
FIN
CHARACTERISTIC
(Volts)
V,H
MAX
c
...o...3:
o
Series 10,000
DM10110(MC10110) dual 3-input/3-output OR gate
general description
features
The DM 1011 0 is designed to dnve up to three
transmission lines simultaneously. The multiple
outputs of this device also allow the wire"OR"ing
of several levels of gatmg for minimization of gate
and package count.
•
Slow rise and fall times
•
High speed
•
Low power
50 mA/output
High fanout
Multiple open emitter follower outputs
•
•
The ability to control three parallel lines from a
single pOint makes the DM10110 particularly use·
ful in clock distribution applications where min·
imum clock skew is deSIred.
3.5 ns
tpd
= 2.0 ns
•
Multiple wire OR capability
•
•
Standard end power pinS
Separate Vee pins maintain high speed and
minimIZe crosstalk and nOise generation
schematic and connection diagrams
V CC2
16
VCCT
r l....- - O l
Dual-I n-L roe Package
TOPVIEW
110-1-----,
.....4 ........- - - '
100-+----,
r-......-
VCC1
015
·"'-+-1--0 14
"'--'-_"13
12
v"
7·13
o
po
po
opo
absolute maximum ratings
:::E
Q
-8V
Supply Voltage
Input Voltage
Output Current
Operatmg Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50 rnA
_30°C to +85°C
-55°C to +125°C
300°C
TEST VOLTAGE VALUES
electrical characteristics
o 'EST
TEMP
SYMBOL
PIN
UNDER
TEST
MIN
MAX
-0890
-1890
-1205
-1500
-52
+?SoC
-0810
-1850
-1105
-1475
-52
+8S"C
-0700
Power Supply Dram Current
Input Current
Logic" 1" Output Voltage
LogiC "0" Output Voltage
LogiC ."" Threshold Voltage
logiC "0" Threshold Voltage
DMl01'O TEST LIMITS
-lO°C
MIN
',nH
5,6,7
I.,
5,6,7
VOH
Vo ,
VOHA
-1035 -1440 -52
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
-1825
V'H
VOL
VIHA
VILA
MAX
MIN
MIN
MAX
VEE
IVeel
GND
3.
mAde
1,15,16
'3.
"Ad,
1,15,16
pAdc
1,15,16
-0960
-0810
-0890
-0700
Vd,
1,15,16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
1,15.16
1,15.16
I, IS, 16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
-1890
-1675
-1850
-1650
-1825
-16 1 5
Vd,
-1890
-1675
-1850
-1650
-1825
-'615
Vd,
I, '6, 16
-1890
-1675
-1850
-1650
-1825
-1815
Vd,
1,15,16
-lOBO
-0980
-0910
Vd,
1,15,16
-lOBO
-0980
-0910
Vd,
1,15,16
-lOBO
-0980
-0910
Vd,
1,15,16
1,15,16
VOLA
-1655
-1630
-1595
Vd,
-1655
-1630
-1595
Vd,
-1655
-1630
-1595
Vt •.
1,15,16
1,15,16
Pul..
In
2.
Pulse
Out
-32V
+20V
3.
1,15,16
3.
1,15,16
1,15,16
2.
3'
3.
2.
35
1,15,16
J5
1,15,16
11
2.
22
35
1,15,16
11
22
3.
1,15,16
11
22
3.
1,15,16
11
22
22
3'
3.
1,1&.16
11
11
22
3'
1,15,18
"
"
,."
2.
2.
1,15,16
1,16.18
·lndtvld".lly tlSt I!-=tIlnp\l1 eppIYlnl VIH (It' VIL to Pin "ndIr teat
Note: Each DM10,OOO senes circuit has been designed to meet the DC specifications shown In the test table, after thermal
equIlibrium has been established. The Circuit IS in a test socket or mounted on a printed cirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2_0 volts. Test procedures are shown for only one gate. The other gate is tested In the same manner.
7-14
c
...os:
......
Series 10,000
DM10111 (MC10111) dual 3-input/3-output NOR gate
general description
features
The DM 10111 is designed to drive up to three
transmission lines simultaneously. The multiple
outputs of this device also allow the wire-"OR"ing
of several levels of gating for minimization of
gate and package cou nt.
•
Slow rise and fall times
•
High speed
•
Low power
50 mA/outputHigh fanout
Multiple open emitter follower outputs
•
•
The ability to control three parallel lines from a
single point makes the D.Ml0l11 particularly useful in clock distribution applications where minimum clock skew is desired.
3.5 ns
tpd
= 2.0 ns
•
Multiple wire OR capability
•
Standard end power pins
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and logic diagrams
VCC2
"
Dual-In-Line Package
110--1-------,
HI
v"
100-+----,
TOP VIEW
......-++-0
14
.......--'--~1J
12
v"
7-15
po
po
po
o
absolute maximum ratings
po
:E
Q
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30°C to +85°C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
CHARACTERISTIC
Power Supply Dram Current
SYMBOL
PIN
UNDER
TEST
',nH
5,6,7
I.,
5,6,7
LogiC "'" Output Voltage
VOH
LogiC "0" Output Voltage
LogIC "1" Threshold Voltage
LogiC
"a.. Threshold Voltage
Va'
V OHA
VOLA
MAX
+8SoC
+25°C
MIN
TVP
MAX
Rise Time
(20to8D%1
Felt Time
(20 to 80%)
MIN
MIN
MAX
_30°C
-0890
-1890
-1206
-1500
+25 c C
+8SoC
-<1700
-0810
V1HA
VILA
V..
-52
-1850
-1105
-1475
-52
-1825
-1035
-1440
-52
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
UNITS
MAX
38
435
V'H
VIL
VIHA
VILA
MAX
MIN
MIN
MAX
VEE
(Vee)
GND
mAde
1,15,16
JjAdc
1,15,16
"Ad,
1,15,16
-1060
-0890
-<1960
-0810
-0890
-0700
Vd,
1,15,16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
1,15,16
-1060
-0890
-0960
-0810
-0890
-0700
Vd,
1,15,16
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,16,16
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,15,16
-1890
-1675
-1850
-1650
-1825
-1615
Vd,
1,15,18
O.
-1080
-0980
-0910
Vd,
1,15,16
-1080
-0980
-0910
Vd,
1,15,16
-1080
-0 980
-0910
Vd,
1,15,16
-1655
-1630
-1595
Vd,
1,15,18
-1655
-1630
-1595
Vd,
1,15,16
-1655
-1630
-1595
Vd,
SWitching Times
150 ohm loadl
Propagation Delay
VIL
MIN
DMl0111 TEST LIMITS
_30°C
MIN
I,
Input Current
(Volts)
V'H
MAX
1,15,16
Pulse
Pulse
'"
OUI
-32V
+20V
14
24
tS_2+
14
24
35
I.
1,15,16
tS+3_
24
3.
1,15,16
\s-3+
14
24
3.
1,15,16
\s+4_
14
24
3.
1,15,16
tS_4+
14
24
3.
1,15,16
I,.
11
3.
1,15,16
...
1,_
..
11
11
22
22
22
22
11
22
3.
1,15,16
11
22
3.
1,16,16
\s+2-
I,.
I,
-
11
3.
1,15,16
3.
1,15,16
3.
1,15,16
3.
1,15,16
"IndlVlduaUy test each Input applYing VinH or VlnL to Pin under tnt
Note: Each DM10,OOO senes circuit has been deSigned to meet the DC specifications shown In the test table, after thermal
eqUIlibrium has been established. The cirCUit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are' terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner,
7-16
c
3:
..a
Series 10,000
o
..a
..a
N
DM10112{MC10112) dual 3-input 1 ORf2 NOR gate
general description
features
The DM10112 is a dual 3 input 1 OR/2 NOR
gate. The DM 10112 is useful for driving multiple transmission lines. The open emitter outputs allow the use of wire 0 R in data bus applications.
•
•
•
•
•
•
•
•
The ability to drive multiple transmission lines
from a single gate make the DM 10112 particularly useful in clock distribution app'iications where
minimum clock skew is desired. The DM10112 is
also useful for memory chip select decoding.
3.5 ns
Slow rise and fall times
tpd = 2.0 ns
High speed
Low power
50 mA/output
High fanout
Multiple open emitter follower outputs
Multiple wire OR capability
Standard end power pins
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
schematic and connection diagrams
Dual-In-Line Package
VCCJ
vcc,
]11 lIS
I'
~
~
no-t-------,
I'
v""
,
13
r
I"
'c,
3
I'
11
• •
"
7
•
I'
v"
TOP VIEW
V"O--'--+--4_ _+-_~O--_---'
"
7-17
N
....
....
o....
absolute maximum ratings
::!
c
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
-8V
o to VEE
50mA
_30° C to +85° C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
(Volts)
V,H
MAX
V,L
MIN
VIHA
MIN
MAX
-0890
-1890
-1205
-1500
-52
+2SoC
-0810
-1850
-1105
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
~30°C
DM10112 TEST LIMITS
PIN
CHARACTERISTIC
SYMBOL
UNDER
TEST
PINS LISTED BELOW
+8S"C
UNITS
MIN
MAX
MIN
TYP
MAX
MIN
MAX
I,
8
-
l,nH
5,6,7
-
-
-
-
-
}JAde
5,6,7
-
435
',"l
as
38
Input Current
-
Logic "1" Output Voltage
VOH
2
-1060
-0890
-0960
-
-0810
-0890
-0700
Vdo
3
-1060
-0890
-0960
-
-0810
-0890
-0700
Vdo
4
-1060
-0890
-0960
-0810
-0890
-0700
2
-1890
-1675
-1850
-1650
-1825
3
-1890
-1675
-t 850
-
-1650
4
-1890
-1675
-1850
-
-
-0 980
-
-0980
-0 980
Power Supply Dram Current
Logic "0" Output Voltage
LogIc "1" Threshold Voltage
LogIc "0" Threshold Voltage
VOL
VOHA
VOLA
2
-1080
3
-1080
4
-1080
2
-
3
4
-1655
-1655
-1655
-
V,H
MAX
V,L
MIN
VIHA
VILA
MIN
MAX
V"
GND
-
-
-
-
8
1,15,16
8
1,15,16
-
8
1,15,16
-
8
1,15.16
8
1,15,16
8
1,15,16
8
1,15,16
•
1,15,16
8
1,15,16
8
1,15,16
6
8
1,15,16
7
8
1,15,16
5
8
1,15,16
8
1,15,16
8
1,15,16
mAde
-
/-lAde
6
Vdo
-1615
Vdo
-
5
-1825
-1615
Vdo
6
-
-1650
-1825
-1615
Vdo
7
-
-0 910
-
-
-0910
-
Vdo
-
-1630
-
-1595
Vdo
-
-1630
-
-1595
Vdo
-
-1630
-
-1595
Vdo
-
-
-0 910
Vdo
Vdo
Plopagatlon Delay
Rise Time
(20 to 80%)
Fall Time
(20 to 80%)
t"
2
-
-
II
22
35
t,.
3
-
-
11
22
35
t,.
4
-
-
11
22
35
t,_
2
-
-
II
22
35
t,.
3
-
-
11
22
35
-
t,.
4
-
-
11
22
35
-
2
-
-
14
t5_2_
2
-
24
35
3
-
14
24
35
t5_3+
3
-
14
24
35
t5+4_
4
14
24
35
t5_4+
4
-
14
t5+3_
14
24
35
t5+2+
-
24
3'
-
-
-
e,
e,"'
e'
"'
"'
"'
"'e,
"'
"'
"'
-
7
SWItching Times
(SO·ohm load)
_.
_.
-
5
-
-
VEE
TEST VOLTAGE APPLIED TO
+2SOC
-lO"C
VILA
5
-
-
6
7
Pulse
I,
Pulse
Out
2
(Vee)
-32V
+20V
8
1,15,16
-
-
5
-
-
5
2
8
1,15,16
5
3
8
1,15,16
5
3
8
~,
5
4
8
1,15,16
-
-
4
5
8
1,15,16
-
5
2
e
1,15,16
5
3
8
1,15,16
5
4
8
1,15,16
-
5
2
8
1,15,16
-
5
3
8
1,15,16
-
5
4
8
1,15,16
-IndIVidually test each Input uSing the pin connections shown
Note: Each DM1D,000 senes CirCUIt has been designed to meet the DC specifications shown In the test table, after thermal
eqUIlibrium has been established, The Circuit IS In a test socket or mounted on a pnnted CircUit board and transverse air
flow greater than 500 Imear fpm IS maintained. Outputs are termmated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested 10 the same manner.
7·18
15, 16
-
c
s:
-A
Series 10,000
o
-A
-A
UI
DM10115(MC101151 quad differential amplifier
general description
features
The OM10115 is a quad differential amplifier
designed for use in sensing differential signals
over long lines. The base bias supply (V BS ) is
made available at pin 9 to make the device useful
as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
•
Slow rise and fall times
•
High speed
Active current sources provide the OM 10115
with excellent common mode noise rejection.
If any amplifier in a package is not used, one
input must be connected to Vss (pin 9) to prevent overloading the current source bias network.
3.5 ns
tpd
= 2.0ns
•
Low power
•
High fanout
•
Open emitter follower outputs for wire OR
•
Standard end power pins conventional layout
•
Separate Vee pins maintain high speed and
minimize crosstalk and noise generation
50 mA/output
schematic and connection diagrams
Vee1
15
14
1
v"
10
11
\3
12
v"
Dual-In-Line Package
TOP VIEW
7·19
...
o
I.C)
...
absolute maximum ratings
::!
C
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
_30° C to +85° C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
(Volts I
CHARACTER ISTIC
SYMBOL
V,H
MAX
VIL
MIN
VIH"
MIN
VilA
MAX
v••
VEE
_30°C
-0890
-1890
-1205
-, 500
From
-52
+2SOC
-08'0
-1850
-1105
-1475
Pm
-52
+8S o C
-0100
-1825
-'035
-1440
DM1011S TEST LIMITS
PIN
UNDER
TEST
@TEST
TEMP
+2S"C
-30°C
MIN
MAX
MIN
+85°C
MAX
-52
TEST VOLTAGE APPLIED TO PINS LISTeD BELOW
MIN
MAX
UNITS
V,H
MAX
VIL
MIN
V 1HA
VILA
MIN
MAX
V••
VEE
Power Supply Dram Current
I,
26
mAde
4,7, to, 13
Input Current
"0
100
)lAde
7,10,13
5,6,11,12
Input Leakage Current
I,
10
/JAde
7,10,13
5,6, '1, 12
8,4
5,6,11,12
8
VO"
Vo ,
-1060
-0890
-1890
-1675
LogIc "1" Threshold Voltage
VOHA
-1080
LogIC "0" Threshold Voltage
VOLA
LogIC "'" Output Voltage
LogIC "0" Output Voltage
Reference Voltage
V"
Sw!tchlngTlmes
(50-ohm LO
-
3
-
-
-
22
-
23
22
22
-
-
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
4,9
8
1,16
4,9
-
8
1,16
Pulse
Pulse
I,
0",
-32V
+20V
4,9
SWltchmg Times
(50a Load)
Propagation Delay
VEE
VIHA
3
--
VEE
-52
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
DM10117 TEST LIMITS
PIN
CHARACTERISTIC
VIL.A
2
8
1,16
9
-
4
"'m
4
2
8
1,16
9
-
4
3
8
1,16
"'
9
-
-
-
-
m
9
-
4
3
8
1,16
-
-
m
9
-
4
2
8
1,16
-
m
9
-
4
3
8
1,16
"'
9
-
4
2
8
1,16
4
3
8
1,16
-
-
m
9
Note: Each DM10,OOO senes Circuit has been deSigned to meet the DC specifications shown In the test table, after thermal
equIlibrium has been established. The Circuit IS In a test socket or mounted on a printed CircUit board and transverse alf
flow greater than 500 linear fpm IS maintained Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner
7-24
Series 10,000
DM10118(MC101181 dual 2-wide OR-AND gate
general description
The DM10118 IS a basic logic building block providing the OR-AND function, useful in data control and digital multiplexing applications.
features
•
50£2 line driving capability
•
High Z input pulldowns - for lower power
dissipation
•
Open emitter follower outputs
•
Internal collector dot for maximum logic utility
and speed
•
Slow rise and fall times
4.0 ns
•
High speed
tpd = 2.5 ns for two levels of logic
•
Wire OR capability - for bus oriented systems
•
Low power
100 mW/package
•
•
High fanout
50 mA/output
Standard end power pinS - standard layout
requirements
schematic and connection diagrams
VCC1
115
~
C>--1
:S
~
)-
~
"'--
~
,----< ~
~
;~r<
ts
~
12
13
r
2: ;r~
14
'--
rK
r-r:C:--
10
~
2: ]-~
11
Dual-In-Line Package
TOP VIEW
7-25
...
...
00
o
absolute maximum ratings
~
c
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-8V
o to VEE
50mA
_30°C to +85°C
-55°C to +125°C
300°C
TEST VOLTAGE VALUES
electrical characteristics
!Volu)
@TEST
TEMP
V'H
MAX
MIN
MIN
MAX
VEE
_30°C
-0890
-1890
-1205
-1500
-52
+2S OC
-0810
-1850
-1 150
-1475
-52
+8SoC
-0700
-1825
-1035
-1440
-52
DM10118 TEST LIMITS
PIN
CHARACTERISTIC
SYMBOL
Power Supply Dram Current
I nput Current
I,
I,,,H
_30°C
•
+2S"C
UNITS
MAX
MIN
TVP
MAX
MIN
MAX
-
20
26
-
265
-
-
-
-
-
-
7
-
9
-
-
05
-
265
355
LogiC '1" Output Voltage
VOH
2
-1060
-0890
-0960
logiC '0" Output Voltage
Va'
2
-2000
-1676
-1990
-
LogiC '1" Threshold Voltage
V OHA
2
-1080
-
-0980
-
-
-0910
logiC "0" Threshold Voltage
VOLA
2
-
-1655
-
-1630
-
l,nL
6
7
-
05
05
-
-
-
-
-
-0810
-0890
-1650
-1 920
V'H
VIL
VU'4A
VILA
MAX
MIN
M'N
MAX
mAde
-
/JAde
6
-
-
-
}.lAde
7
J.lAdc
9
pAde
6
}.lAde
-
-0700
Vd,
3,9
-
-1615
Vd,
-
3,9
}.lAde
Vd,
-1595
Vd,
7
9
-
SWltchmg Times
(5C-ohm load)
t6+2+
2
-
-
, 4
23
34
16_2
2
-
-
,4
23
34
Rise Time (20 to 80%!
t,
2
-
-
25
40
Fall Time (20 to 80%)
t
2
-
-
15
, 5
-
25
40
-
Propagation Delay
VILA
PINS LISTED BELOW
+8S"C
MIN
6
9
VIHA
TEST VOLTAGE APPLIED TO
UNDER
TEST
VIL
-
m
3
m
3
-
m
3
-
m
3
-
3,9
-
-
3,9
Pulse
Pulse
10
6
0"
2
6
2
6
6
VEE
•
1,16
8
1,16
•
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
-32V
+20V
8
1,16
8
1,16
2
8
1,16
2
8
1,16
Note: Each DM10,OOO series cirCUit has been designed to meet the DC specifications shown In the test table, after therfTlal
eqUilibrium has been established. The Circuit IS In a test socket or mounted on a printed cirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gate IS tested In the same manner.
7-26
(Vee)
GND
c
...3:o
...
Series 10,000
CD
DM10119(MC10119) 4-wide 4-3-3-3-input OR/AND gate
general description
The DM10119 IS a 4-Wlde 4-3-3-3 Input OR/
AND gate with one input from two gates common
to pin 10 Input pulldown resistors eliminate the
need to tie unused inputs to an external supply.
•
•
High fanout
50£2 line driving capability
•
High Z Input pulldowns - for lower power
dissl pation
features
•
Open emitter follower outputs
•
Internal collector dot for maximum logic utility
and speed
•
Slow rise and fall times
4.0 ns
•
High speed
tpd ~ 2.5 ns for two levels of logic
•
Low power
100 mW/package
50 mA/output
•
Wire OR capability - for bus oriented systems
•
Standard end power pinS - standard layout
requirements
schematic and logic diagrams
Dual-In-Line Package
TOP VIEW
7-27
en
....
....
o
....
absolute maximum ratings
:?!
c
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 10 secl
-8V
o to VEE
50mA
_30° C to +85° C
_55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
(Volts)
@TEST
DM10119
CHARACTERISTIC
SYMBOL
PIN
UNDER
_30 o e
TEMP
V'H
MAX
VlL
MIN
VIHA
MIN
MAX
~30°C
-0890
-1890
-1205
-1500
~5
2
+25"C
-0810
-1850
-1105
-1475
~5
2
+8SoC
-0700
-1825
-1035
-1440
~5
2
TEST LIMITS
+2SoC
+85"C
Power Supply Dram Current
Input Current
8
"
l,nH
7
9
10
l,nL
7
9
10
LogiC ''1'' Output Voltage
LogiC "0" Output Voltage
logiC "1" Threshold Voltage
LogiC "0" Threshold Voltage
MAX
MIN
TVP
-
-
-
20
26
-
-
265
-
-
-
-
-
05
-
05
05
-
-
VOH
2
-1060
-0890
-0960
Voc
2
-2000
-1675
-1990
VOHA
2
-1080
-
-0980
VOLA
2
-
-1655
-
-
-
MAX
265
355
UNITS
MIN
MAX
V'H
MAX
V'l
MIN
VIHA
VILA
MIN
MAX
-
-
mAde
-
/JAde
7
-
-
-
pAde
9
/JAde
10
-
!lAde
-
7
/JAde
-
9
-
-
10
-0890
-0700
Vde
3,10,15
-
-1650
-1920
-1615
Vde
-
-0910
-
Vde
-
-1630
-
-1595
Vde
-
-
-0810
-
/JAde
3,10,15
-
SWitching Times
(50·ohm load)
Propagation Delay
-
-
14
23
34
14
23
34
-
2
-
-
15
25
40
2
-
-
15
25
40
-
14+2+
2
14_2_
2
Rise Time (20 to 80%)
t.
Fall Time (20 to 80%)
'-
VEE
TEST VOLTAGE APPLIED TO
PINS LISTED BElOW
TEST
MIN
VILA
-
-
"'
"'
"'
"'
-
3,10,15
-
3,10,15
Pulse
10
Pulse
0",
VEE
GND
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1, 16
8
1,16
8
1,16
8
1,16
8
1,16
-32V
+20V
-
4
2
8
10,13
-
4
2
8
1,16
10,13
-
4
2
8
1,16
4
2
8
1,16
10,13
10,13
Note: Each DM10,OOO senes CircuIt has been deSigned to meet the DC specIficatIOns shown In the test table, after thermal
eqUilibrium has been established. The CirCUIt IS 10 a test socket or mounted on a prmted CirCUit board and transverse air
flow greater than 500 Imear fpm IS mamtamed. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other mputs are tested m the same manner.
7-28
(Vee)
8
1,16
Series 10,000
DM10121(MC10121) OR-AND/OR-AND-INVERT gate
general description
The DM10121 is a basic logic building block
providing the simultaneous OR-AND/OR-ANDINVERT function, useful in data control and digital multiplexing applications_
•
•
•
•
features
•
•
Slow rISe and fall times
4_0 ns
High speed tpd = 2_5 ns for two levels of logic
•
•
Low power
High fanout
50n line driving capability
High Z input pulldowns - for lower power
dissipation
Open emitter follower outputs
I nternal collector dot and em itter dot - for
maximum logic utility and speed
Wire OR capability - for buss oriented systems
Complementary outputs - added versatility
Standard end power pins - standard layout
requ irements
•
•
•
100 mW/pkg
50 rnA/output
schematic and connection diagrams
I
K
~
f--M"
v"
.
~ ~ tSi-
J
r---.t.
1B
.;
-----l
~
r;~
l
~
2= ?~
r-~
0-
r----t
" V""
r-f---"
IZ
13
14
11
"
r- f-o 15
,~
II
LSJ K~ ~ ;=r-
~~
?-
t
1
>- >
•v"
Dual-In-Line Package
V~,
TOP VIEW
7-29
...
...
o
...
::E
N
absolute maximum ratings
c
-8V
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
o to VEE
50mA
-30°C to +85°C
-55°C to +125°C
300°C
electrical characteristics
TEST VOLTAGE VALUES
@TEST
TEMP
OM10121
PIN
CHARACTERISTIC
SYMBOL
UNDER
TEST
Power Supply Dram Current
Input Current
_30°C
MIN
MAX
I,
Logic "1 ' Output Voltage
Logic "0' Output Voltage
Logic "1" Threshold Voltage
Logic "0" Threshold Voltage
Vo<
Voe
VOHA
VOLA
VILA
MIN
MIN
MAX
-1205
-1500
-52
-1890
+2S"C
-0810
-1850
-1105
-1475
-52
+85"C
-0700
-1825
-1035
-1440
-5.2
TEST VOLTAGE APPLIED TO
PINS LISTED BELOW
+85°C
MIN
UNITS
MAX
V,H
VOL
VIHA
VILA
MAX
MIN
MIN
MAX
26
mAde
1,16
265
~Adc
1,16
265
J1Adc
355
/.lAde
O.
O.
O.
(20to 80%)
Fall Time
(20to 80%)
VEE
1,16
1,16
1,16
/.lAde
10
}JAde
1,16
-1060
-0780
-0960
-0700
-0890
-0590
Vd,
-1060
-0780
-0960
-0700
-0890
-0590
Vd,
4,10,13
1,16
1,16
-2000
-1675
-1990
-1650
-1920
-1615
Vd,
4,10,13
1,16
-2000
-1675
-1990
-1650
-1920
-1615
Vd,
1,16
-1080
-0980
-0910
Vd,
-1080
-0980
-0910
Vd,
4,10,13
-1595
Vdo
4,10,13
-1595
Vd,
-1630
-1655
-1630
1,16
1,16
1,16
1,16
Pul~e
Pulse
10
0",
-32V
+20V
t 4 +3
23
10,13
1,16
t 4_3+
23
10,13
1,16
1,16
t4+2+
23
10,13
14_2_
23
10,13
1,16
t"
t,.
t,
t,_
2.
10,13
1,16
25
10,13
1,16
2.
10,13
1,16
2.
10,13
1,16
Note: Each DM10,OOO series CirCUit has been designed to meet the DC specifications shown In the test table, after thermal
eqUIlibrium has been established The circuit IS In a test socket or mounted on a printed CirCUit board and transverse air
flow greater than 500 linear fpm IS maintained. Outputs are terminated through a 50~ohm resistor to -2.0 volts. Test pro~
cedures are shown for only one gate. The other Inputs are tested In the same manner.
7-30
GNO
1,16
10
/JAde
-1655
Rise Time
(Vee)
20
SWltchmg Times
(50 ohm load)
Propagation Delay
VEE
-0890
MAX
10
10
VIHA
MAX
~30°C
TVP
l,nH
l,nL
VOL
TEST LIMITS
+25°C
MIN
(Volts)
V,H
Series 10,000
DM10124(MC10124) quad TTL to ECL
translator/differential line driver
general description
The DM10124 is a quad TTL to ECl translator
which may also be used as a quad TTL to ECl
differential line driver. The input levels are compatible with the series 7400, series 74HOO and
Schottky series 74500.
• Complementary outputs with ECl 10,000 levels
• High output capacity, drives B 50£2 lines
• TTL compatible inputs, input strobe
• Four translators per package
The output logic levels are ECl 10,000 compatible
over the recommended operating temperature
range. Complementary emitter follower outputs
provide for inverting, non-inverting or differential
line driving applications. A common TTL strobe
input is provided which when held at a TTL logic
"0" forces all true (non-inverting) outputs to an
ECl logic logical "0" lOW and all compliments
(inverting) outputs to an ECl logical "1" HIGH.
applications
The DM10124 may be used as either an inverting
or non·inverting TTL to ECl translator. One differential line driving application includes very high
speed data transmission in a TTL system by converting the data to ECl levels and driving through
terminated twisted line pairs. The DM 10125 is the
logical complement to the DM10124 and can be
used to translate the differential ECl levels back to
standard TTL ones. The advantages of ECl transmission line characteristics (i.e. controlled edge
speeds, terminations, very high speed data rates)
may then be utilized in a TTL system .
features
• High speed
• Power dissipation
tpd '" 3.5 ns typical
250 mW/pkg typical
connection diagram
Dual-In-Line Package
15
I,.
I
5'
6'
TOPVIEW
' . TTL LEVELS
Vee'" PIN 9 = +5.0V
VEE =PIN8=-52V
GND • PIN 16 • OV
7·31
absolute maximum ratings
Supply Voltage:.
VEE
Vee
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
-BV
+7V
+5,5V
50mA
-30°C to +B5°C
-65°C to +150°C
3OQ°C
electrical ch aracteristics
CHARACTERISTIC
SYMBOL
Power Supply Drain Current
lEE
Icc
Logic "1" Input Current
"H
"H
Logic "0" Input Current
"L
"L
logiC "1" Input Voltage
V 1HA
Logic "0" Input Voltage
VILA
Input Clamp Voltage
logic "1" Output Voltage
PIN
UNDER
TEST
DM10124 TEST LIMITS
-30°C
MIN
MAX
TYP
MAX
MIN
mA
mA
2,7,10,11
6
4
16
~A
5,7,10,11
6
-16
-60
mA
mA
~A
+20
V
V
08
1,2,14,15
-15
-106
-089
-096
-081
V
-0.89
-0.70
V
VOH
3,4,12,13
-106
-089
-096
-081
-089
-070
V
logic "0" Output Voltage
VOL
1,2.14,15
-189
-1675
-185
-165
-1.825
-1615
V
Logic "0" Output Voltage
VOL
3,4,12,13
-189
-1675
-185
-1.65
-1825
-1615
V
logic "1" Threshold Voltage
V OHA
1,2,14,15
-108
-098
-091
V
logiC
"1" Threshold Voltage
V OHA
3,4,12,13
-108
-098
-091
V
logiC
"0" Threshold Voltage
VOLA
1,2,14,15
-1655
-163
1.595
V
-1655
-163
-1595
V
logiC
"1" Output Voltage
logiC "0" Threshold Voltage
VOLA
3,4,12,13
Switching Times 500 Load
ProPItIation Delay (3V p.p
tpd++
5,6,7,10,11
tpd--
.... +.... -+
Input at tr '" t, '" 2 ns,
20% -80%)
50
ns
35
60
35
50
10
35
60
ns
ns
ns
ns
ns
10
35
5.6.7.10.11
1.0
5,6,7,10.11
10
5,6,7,10,11
80%
t,
Outputs
11
20
3.3
FallTlme 20% - 80%
tf
Outputs
11
20
3.3
RISe Time. 20%
~
CONDITIONS
UNITS
MAX
38
25
, 8
9
5,6,10,11
VOH
+86°C
+25°C
MIN
Inputs &. Outputs
OPEN
VIN =VIH =+27V
VIN .. V1L = +O.4V
Threshold InputsUse for Test
Measured at IT '" -12 rnA
500to-20V
All Inputs '" V IH
-
son to -2,OV
Pm 6 "" V1L - +O.4V
500to-2.0V
AlllnpuU'" VIN - +2.7
500 to-2.0V
Inputs at V IHA
..
+2.0
500 to -2,OV
Input at VILA - +0.8
500 to-2 OV
Inputs at V1LA = +0.8
500 to-2OV
Inputs at V1HA - +2.0
Each Input In Sequence.
Undrlven Inputs to
Vee (NOM) = +5V
Nota 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
7-32
2.7
500 to-2.0V
Pin 6'" V1L " O.4V
...
::2
illS
.
CD
Interface Circuits
....
III
n
CD
REFERENCE
.
(')
The following table references all Physical DimenSion DraWings for the deVices In this section. For Order
n
c
...
Numbers, see below.' Refer to the alpha·numerocal Index at the front of this catalog for complete device
title and function. Packages (pages I thru VI) are In the back of the catalog.
III
DATA SHEETS
Devices
DHOO06
DHOOO6C
OHOO08
OHOO08C
OH0011
DHOOllC
OHOOllCN
OHOO16CN
OHOO17CN
OHOO18CN
OH0028C
OH0028CN
OH0034
OH0034C
OHOO35
OH0035C
OH3467C
OH3725C
LH2111
LH2211
LH2311
LM106
LM206
LM306
LMlll
LM211
LM311
LM139
LM239
LM339
LM160
LM260
LM360
LM161
LM261
LM361
LM163
LM363
LM350
LM363A
LM710
LM710C
LM711
LM711C
LM1414
LM1514
LM1488
LM1489A
LM5520
LM7520
LM5521
LM7521
LM5522
LM7522
Pg.
8·1
8·1
8·4
8·4
8·7
8·7
8·7
8·10
8·10
8·10
8·13
8·13
8·15
8·15
8·18
8·18
8·20
8·22
8·24
8·24
8·24
8·26
8·26
8·28
8·30
8·30
8·30
8-40
8-40
8-40
8-44
8-44
8-44
8·46
8-46
8-46
8-79
8·79
8·48
8·79
8·50
8·52
8·54
8·56
8·63
8·63
8·58
8·61
8·66
8·66
8·66
8·66
8-69
8·69
PACKAGES
Molded DIP (N)
Fig.
Pg.
2
II
2
II
2
2
2
2
2
2
2
II
II
II
II
II
II
II
Cavity DIP (D)(J)
Fig.
Pg. Type
IV
IV
J
J
Metal Can (G)(H)
Fig.
Pg. Type
21
21
21
21
21
21
21
V
V
V
V
V
V
V
H
H
H
H
H
H
H
21
21
21
21
24
24
V
V
V
V
VI
VI
H
H
H
H
G
20
20
20
20
20
20
V
V
V
V
V
V
H
H
H
H
H
H
20
20
20
21
21
VI
VI
VI
VI
VI
H
H
H
H
H
20
23
22
23
V
VI
V
VI
H
H
H
H
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
G
II
II
9
9
9
3
II
3
II
3
Flat Pack (F)(W)
Fig.
,
11
11
3
3
Pg. Type
WAVE·
FORMS
II
3
II
3
3
3
1
3
II
II
II
II
II
3
3
II
II
5
II
5
II
5
II
III
III
III
8
8
8
8
8
8
8
8
8
8
8
8
11
11
III
III
III
III
III
III
III
III
III
III
11
11
11
11
11
12
12
12
12
12
12
0
0
D
0
D
D
D
D
D
D
D
V
V
V
IV
F
F
F
F
14
14
14
15
IV
IV
IV
V
F
F
F
F
15
V
F
15
V
F
D
III
D
D
III
IV
IV
D
J
J
IV
J
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
16
16
16
15
J
J
J
J
J
J
J
J
J
J
'Order Numbers: use Device No. suffixed with package letter, i.e. DHOOO6H.
8--i
(.)
CD
(,)
IV
...
~
....CCD
DATA SHEETS
PACKAGES
Molded DIP IN)
Devices
LM5523
LM7523
LM5524
LM7524
LM5525
LM7525
LM5528
LM7528
LM5529
LM7529
LM5534
LM7534
LM5535
LM7535
LM5538
LM7538
LM5539
LM7539
LM55107A
LM75107A
LM55108A
LM75108A
LM75207
LM75208
LM75324
LM55325
LM75325
LM75450A
LM75451A
LM75452
LM75453
LM75454
MHOO07
MHOO07C
MHOO09
MHOOO9C
MHOO12
MHOO12C
MHOO13
MHOO13C
MH0025
MH0025C
MH0026
MH0026C
MH8808
B·ii
Pg.
8·69
8·69
8·71
8·71
8·71
8·71
8·73
8·73
8·73
8·73
8·75
8·75
8·75
8·75
8·77
8·77
8·77
8·77
8·79
8-79
8·79
8·79
8-79
8-79
8·86
8·92
8·92
8·48
8·99
8·99
8·99
8·101
8·103
8·103
8·105
8·105
8·107
8·107
8·109
8·109
8·113
8·113
8·116
8·116
8·125
Fig.
Pg.
5
II
5
II
5
II
5
II
5
II
5
II
5
II
5
II
5
II
3
II
3
3
3
3
II
II
II
II
5
3
1
1
1
1
II
II
II
II
II
II
1
II
1
5
II
II
Cavity DIP ID)(J)
Fig.
Pg.
Type
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
11
11
11
IV
IV
IV
IV
IV
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
11
11
12
12
12
IV
IV
IV
IV
IV
J
J
J
J
J
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Flat Pack IF)(W)
Fig.
Pg.
Type
Metal Can IG)(H)
FIg.
Pg.
22
22
24
24
24
24
24
24
20
20
24
20
V
V
V
V
VI
VI
VI
VI
VI
V
VI
V
Type
H
H
G
G
G
G
G
G
H
H
G
H
WAVE·
FORMS
Fig.
Pg.
TEST
CIRCUITS
Fig.
Pg.
C
%
o
o
Interface Circuits
o
CD
........
C
%
o
o
o
CD
n
OHOOOS/OHOOOSC ·current driver
general description
there is less I ikelihood of false turn·on due to an
inadvertent short in the drive line
The DH0006/DH0006C IS an integrated high
voltage, high current driver designed to accept
standard DTL or TTL logic levels and dnve
a load of up to 400 mA at 28 volts. AND inputs
are provided along with an Expander connection,
should additional gating be required. The addition
of an external capacitor provides control of
the rise and fall times of the output in order to
decrease cold lamp surges or to minimize electro·
magnetic interference if long lines are driven.
features
• Operation from a Single +10V to +45V Power
Supply.
• Low Standby Power Dissipation of only 35 mW
for 28V Power Supply.
• 1.5A, 50 ms, Pulse Current Capability.
Since one side of the load is normally grounded,
'Previously called NH0006/NH0006C
schematic and connection diagrams
Metal Can Package
OUTPUT
RESPONSE
TO"
CONTROL
- ...- - - 4.....- - - - 4...--4...- . .-0."
.C
.-+-0
TOP VIEW
OUTPUT
Dual·ln·Line Package
INPUT
10
INPUT
OUTPUT
EXPANDER
IN'UT_-':+_-,
INPUT
INPUT
C}RESPONSE
TIME
B CONTROL
INPUT
"'l1lI.....--4..............- - - - - - 0 ••••••
EXP~:~~~_"":"I--+I--.J
GROUND
IN'UT_"";'+---1 L.._ _~_ _ INPUT
typical applications
Lamp Driver with Expanded Inputs
Relay Driver
OUTPUT
~:p~' {---<-__
'"'AM"
A
EXPANDER INPUT
OTLmL
R£LAY
COIL
lOGIC
INPUTS
\-~USHTO
~TEST
8·1
(.)
CD
o
o
o
absolute maximum ratings
~
Peak Power Supply Voltage (for 0.1 sec)
Continuous Supply Voltage
Input Voltage
Input Extender Current
Peak Output Current (50 ms On/1 sec Off)
Operating Temperature
DH0006
DH0006C, DH0006CN
Storage Temperature
o
.......
CD
o
o
o
~
o
electrical characteristics
PARAMETER
60V
45V
5.5V
5.0mA
1.5A
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
(Note 1)
CONDITIONS
MIN
Logical "1" Input Voltage
Vee
= 45V to 10V
Logical "0" I nput Voltage
Vee
= 45V to 10V
Logical "1" Output Voltage
Vee
= 28V, V ,N = 2.OV, lOUT = 400 mA 26.5
Logical "0" Output Voltage
Vee
= 45V, V ,N = 0.8V, RL = 1K
Logical "1" Output Voltage
Vee
= 10V, V ,N = 2.0V, lOUT = 150 mA
Logical "0" Input Current
Vee
= 45V, V ,N = .4V
Logical "1" Input Current
Vee
= 45V, V ,N = 2.4V
TVP
(Note 2)
2.0
27.0
0.5
= 45V, V ,N = 5.5V
"Off" Power Supply Current Vee = 45V, V ,N = 0.8V
"On" Power Supply Current Vee = 45V, V ,N = 2.0V, lOUT
Vee
Fall Time
Vee
Ton
Vee
Tofl
Vee
= 28V,
= 28V,
= 28V,
= 28V,
RL
RL
RL
RL
1.6
=
0 mA
. . . "t::...:::j., r-PULSE
INPUT
50%--+1----\+--
~===*r---ll====~---,
~.,--
90%--+-+-1+--'1--1--
.'0
ID%
8·2
f
~,o,:\
PULSE OUTPUT
8
mA
J1S
2.2
J1S
a standard DIP socket.
90%--++==\-+--
mA
J1S
Note 5: Power rating for the DH0006CN Molded DIP based on a maximum Junction temperature of
+150°C and a thermal resistance of 150oC/W when mounted on a 1/16 Inch thIck, epoxy-glass board
wIth ten 0 03 Inch wIde 2 ounce copper conductors
switching time waveforms
J1A
2.0
0.26
Note 4: Power rating for the DH0006CN Molded DIP based on a maximum Junction temperature of
.....
J1A
J1S
Note 2: TYPical values are for 25°C ambient
J
5.0
0.8
Note 3: Power ratings for the TO-5 based on a maximum Junction temperature of +17SoC and a ¢JA
of 210°C/W
(I
V
mA
0.10
Note 1: Unless otherwise specified, limits shown apply from -55°C to 125°C for DH0006 and DoC to
70°C for DH0006C.
In
V
-1.0
100
= 82n
= 82n
= 82n
= 82n
+150o C and a thermal resistance of 175°C/W when mounted
.01
9.2
-0.8
V
V
.001
8.8
UNITS
V
0.8
Vee
Rise Time
MAX
C
:I:
0
0
0
typical performance
Maximum Continuous Output
Current For TO..s
Maximum Continuous Output
Current For Molded DIP
en
.......
C
Input Threshold Voltage
vs Temperature
:I:
0
0
0
2.2
...~
..
~
..
>
~
..
..
.
....a'"
..
40
~
2.0
c
1.1
~
>
~
30
~~~~,,~~~~~~'~L~
m
en
1.1
n
1.4
1.2
1.0
E 0.8
!!
0.6
200
480
&00
-50 -25
lOa
MAXIMUM CONTINUOUS OUTPUT CURRENT (mAl
MAXIMUM CONTINUOUS OUTPUT CURRENT (mAl
logical "0" Input Current
"OFF" Supply Current Drain
2.0
1600
....
i
~ 1000
+25°C
i
100
-55'C,~
~
600
~ ::;.-
~400
~ 200
a
.'"
.....
r<
~~ i--'"
~
:>
Jc lY ~
I
g 1/
.!
~ ~~
~ ~ +25°C
1.0
+25'~~
~
+12So C
A~ I-'
l.oII!!l ~
fi ~ e"
~ +125°C
0.5
..... ~ F""'"
30
20
40
50
10
20
SUPPLY VOLTAGE (VI
,
300
r--
,
-15 -50 -25
0
CL"llpF
V,"· 3.0V PULSE
,,';;10 ..
25
a
Available Output Current
~
T~' J25'~
t
>'~
.1
f
.6
"PULSE CONDITION
1ms"ON"
100 ml"OFF"
.
~
Te '25'C
~
r- if·1,~
.4
.2
a
.
I I
./.'!..
'"
I I
a
10
20
30
50
48
SUPPLY VOLTAGE. Vee. (VI
50
~
2.0 f,-
~
.
..
'"
.;
,.;
~
>
-
15 100 125
c>=
~
....
~
.~
13
12
1.1
10
09
al
0.1
0.6
m
la
-
a
200
400
810
800
1000
OUTPUT CURRENT. 1,._.. (mAl
Turn On Control
40
..
""J ..
~
20
E
!!
30
50
1.6
15
1.4
Turn Off Control
4.0
12
1.0
,-
K.a~~
\\~~
25
48
30
Output Saturation Voltage
~
TEMPERATURE rCI
2.0
1.6
1.4
a
-15 -50 -25
50 15 100 125
TEMPERATURE rCI
5 1.'
20
SUPPLY VOLTAGE (VI
~
1/" I
....
..l. ;:;;~
,
1.0
I I
I I
a
3.0
CL "0pF
V,.' 3.oV PULSE
.. ,,10 ..
RISETIME
laD
-
Vee'" zav
RL "IBn
....
Vee = zav
RL -un
I
I
11
50
Turn Off and Fall Time
4.0
TulNOlTIJE
40
30
SUPPLY VOLTAGE (VI
Turn On And Rise Time
480
V 1/
.."Y
+125'C-
~
o
10
15 100 125
50
"ON" Supply Current Drain
-55'~ ...... ~
C 1.5
~ 1200
25
I
V..
1480
a
AMIIENT TEMPERATURE ('CI
Vee =2aV
RL"'Un
~
T. - 25'C
\ 1"C,= I\c, . . .
apF
50
loa
TIME "'.1
150
..~
.
:>
KjIO'F
,=3ODpF
200
250
t"'r
a
C,'380pF
~
CL-j'PF
f--
30
20
10
CF zllO ifF
c,.oy
......
~V
~LIV
RL '6812
T", =Z5°C
CL·ID.F
2.0
4.0
60
1.0
1.
TIME",.)
8-3
(.)
00
o
o
o
Interface Ci rcuits
::E:
C
.......
o
DHOOOS/DH ooose·
high voltage, high current driver
::E:
general description
00
o
o
C
The DH0008/DH0008C IS an integrated high volt·
age, high current driver, designed to accept stan·
dard DTL or TTL input levels and provide a pulsed
load of up to 3A from a continuous supply voltage
up to 45V. AND inputs are provided with an EX·
PANDER connection, should additional gating be
required.
circuit also requires only one power supply for
circuit functional operation.
The DH0008 IS available in a 1O·pin TO·5 package;
the DH0008C IS also available in a 1O,pin TO·5, in
addition to a 10·lead molded dual·in·line package.
features
Since one side of the load is normally grounded,
there is less likelihood of false turn·on due to an
inadvertent short in the drive line.
The high pulse current capability makes the
DH0008/DH0008C ideal for driving nonlinear
resistive loads sllch as incandescent lamps. The
'Prevlously called NH0008/NH0008C
• Operation from a Single +10V to +45V Power
Supply.
• Low Standby Power Dissipation of only 35 mW
for 28V Power Supply.
• 3.0A, 50 ms, Pulse Current Capability.
schematic and connection diagrams
Metal Can Package
OUTPUT
RISE AND
fAll
RESPONSE CONTROL
TIME
CONTROL
r---"'--+-4I~-"'-"'-oV"
TOP VIEW
INPUT
Dual·ln·Line Package
L..._. .- JA
of 210o C/w
Note 4: Power ratmgs for the DHOOOSCN Molded DIP based on a maximum junction temperature of
1500 C and a thermal resistance of 150oC/w when mounted
In
a standard DIP socket
Note 5: Power ratings for the DHOOoaCN Molded DIP based on a maximum junction temperature of
150°C and a thermal resistance of 115°C/w when mounted on a 1/16 Inch thiCk, epoxy-glass board
with ten 0.03 Inch Wide 2 ounce copper conductors.
switching time waveforms
......,t::....:j.,H%---+~--~~----
PULSE
A
,,, __-+I-"--=":.:'U"-'---1t1-----
".
8-5
(.)
00
o
o
o
typical performance
::t
Maximum Continuous Output
Current for TO-5 Package
Q
.......
Maximum Continuous Output
Current for Molded DIP
Available Output Current
00
4.0
3.6
o
o
o
~
Q
"!:;'"
40
28 Tc; 12rC
2.4
~
::t
I I
I I
32
..
20
36
>
~
Tc ·25°C/
16
~
I V
12 Te: -55°(;
20
0.8
400
200
10
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
Input Threshold Voltage
vs Temperature
1.1
1.0
'"~
.8
>
.7
;:
.6
...
..
"....a:
'"~
....
e;
.'"
~
.9
....
>
~
~
.5
.4
:c
....
~
.3
.2
!!!
1600
2.0
1.... 1400
1.8
~
~
~
1.6
1.4
!!!
12
~
~
10
:3
a
0.8
=:
0.6
.2 .3 .4
.5
.6
.7
8 .9 1.0
-50 -25
OUTPUT CURRENT IAI
0
50
25
75 100 125
I
+25°~~
~::::-::
~
~
~
~ ....cV"
+12n,/
C 1.5
E
P
....
~
a:
a:
13
t
40
0.5
p
~ ?'
e
];
+125°C
~
;:
+25°C
~
~
!!!
-
20
~
10
.~
0
I
8-6
20 -~
rJ"
!;
!;
150
V
I-
-75
50
200
250
10
I
,.... -l--+-r
~FALL TIME
-25
+25
700
r-r-
=2aV
RL '" 39n
CL = 10pF
VIN '" 3.0V PULSE
I, -:;;:10 ns
600
i
500
;
400
I
Cl =lOpF
TA =25°C
RF =51 kn
I I
4
6
8 10 12 14 16 18
TIME 1",1
I
TURN ON TIME
~ 300
+125
--
I
1/
o 2
+75
Vee
-
~~ f-Vcc ·28V
~q~ ~ro'b~
RL "'J9n
~~2
IlK
Ti RN iFF I'ME
TEMPERATURE lOCI
I
l'7.v
"
Turn ON and Rise Time
1
30
TIME (ps)
40
T, = aprroxim'j'V 10 n5
3Q,
100
30
I I I I
....
50
./
6.0
4.0
20
./
8.0
Turn OFF Control
!!!
50
V
SUPPL Y VOLTAGE IVI
~
40
30
tf~10ns
10.0
2.0
10
~
.
20
Vee = l8V
RL "'39n
CL = 10pF
VIN =l.OV PULSE
o
Turn ON Control
~
o
12.0
./
~ ~
1.0
50
+125°C
..... ,e F""
14.0
-'l
_55°~-..,.
SUPt'LY VOLTAGE IVI
~
....:~ ::::- -<
400
200
Turn OFF and Fall Times
/,
"l
30
600
...
~ ~ f..;
16.0
>
l..oI/!! ~
20
_55°C,~
OFF Supply Current Drain
V V
50
SUPPL Y VOLTAGE IVI
o
10
+25°C
800
10
2.0
In I--
40
1200
1000
AM81ENTTEMPERATURE lOCI
ON Supply Current Dram
30
Logical "0" I nput Current
2.2
~
"!:;'"
20
SUPPLY VOLTAGE. Vcc.IVI
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
Output Saturation Voltage
~
I I
800
600
PULSE CONOI.t:
1 MS"ON"
100 MS "OFF"
J 1
04
~
'(I
11/
200
RISE TIME
100
I
-50 -25
0
+25 +50 +15 +100 +125
TEMPERATURE rCI
C
%
o
Interface Circuits
...o
"C
%
...oo
n
DH0011*(SH2001)
DH0011C*(SH2002)
DH0011CN*(SH2002P)
"-
c
%
o
......
o
n
high voltage high current drivers
z
general description
The DH0011 high voltage, high current driver
family consists of hybrid integrated circuits which
provide a wide range of variations in temperature
range, package, and output current drive capability. A summary of the variations is listed below.
Applications include driving lamps, relays, cores,
and other devices requiring several hundred milliamp currents at voltages up to 40V. Logic flexibility is provided through a 4-input NAND gate, a
NOR input and an input which bypasses the gating
and connects the base of the output transistor.
'Previously called NHOOll, NH0011C, NHOOllCN
logic diagram
Vee
10
ordering information
NSC DESIGNATION
SH DESIGNATION
PACKAGE
TEMPERATURE RANGE
OUTPUT CURRENT
CAPABILlTV
DHool1H
SH200i
TO·' 00
-5SoC to +125°C
250mA
DHOO11CH
SH2002
TO·lOO
DoC to +70oC
150mA
DHOOI1CN
SH2002 P
EpoxV "8" DIP
O°C to +70°C
150mA
8-7
z
...
o
(J
absolute maximum ratings
o
8V
Vee
Collector Voltage (Output)
40V
I nput Reverse Current
1.0mA
Power Dissipation
800mW
_55°C to +125°C
Operating Temperature Range DHOOll
O°C to +70°C
DHOOllC/DHOOllCN
_65°C to 150°C
Storage Temperature
::I:
C
........
......
o
(J
o
::I:
C
........
..o
o
::I:
C
electrical characteristics
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 7
PIN 8
1
V 1H
V 1H
V 1H
V 1H
GND
GND
lou
2
V 1L
GND
GND
lou
3
V 1L
GND
TEST NO.
4
V 1L
5
V 1L
PIN 6
PIN 9
PIN 10
SENSE
V CeL
Va
VOL
V ecL
Va
IOL2
V CCL
V6
VOL
V OL2
GND
IOL2
V CCL
V6
V OL2
GND
IOL2
V ecL
V6
V OL2
V CCL
V6
V OL2
V CCL
V6
V OL2
6
V 1L
GND
IOL2
7
GND
GND
IOL2
V 1L
V 1H
MIN
8
VR
GND
GND
GND
GND
V CCH
11
IR
9
GND
VR
GND
GND
GND
V CCH
12
IR
10
GND
GND
VR
GND
GND
V CCH
13
IR
11
GND
GND
GND
VR
GND
V CCH
14
IR
V CCH
19
IR
13
VF
VR
VR
VR
GND
V CCH
11
-IF
-IF
12
VR
GND
14
VR
VF
VR
VR
GND
V eCH
12
15
VR
VR
VF
VR
GND
V CCH
13
-IF
16
VR
VR
VR
VF
GND
14
-IF
GND
GND
V CCH
V CC'H
V CCL
V6
V CCL
la
lox
V PD
110
IpDH
110
17
18
19
GND
20
21
GND
VF
GND
GND
GND
GND
GND
GND
Vox
-IF
19
V OH
GND
V MAX
22'
GND
V PD
tON
I MAX
23'
GND
V PD
tOFF
*See Test Circuits and Waveforms on Page 4.
forcing functions
PARAMETER
(Note 1) DHOOll
_55°C
+25°C
+125°C
UNITS
V CCL
4.5
4.5
4.5
V
V CCH
5.5
5.5
5.5
V
V PD
5.0
V MAX
8.0
V
V
V 1L
1.4
1.1
0.8
V
V 1H
2.1
1.9
1.7
V
VR
4.0
4.0
4.0
V
VF
0.0
0.0
0.0
V
lou
250
250
250
mA
IOL2
8.0
8.0
7.5
mA
Vox
40.0
40.0
40.0
V
Note 1: Temperature Range _55°C to +125°C
8·8
MAX
o
:::J:
o
forcing functions (Note 2) DHOOllC, DHOOllCN
O°C
PARAMETER
+70°C
+25°C
......o
UNITS
V CCL
5.00
5.0
5.0
V
.......
V CCH
5.00
5.0
5.0
V
:::J:
V PD
5.0
V
V MAX
8.0
V
o
o
V ,L
1.20
1.1
V
......o
V ,H
2.00
1.9
1.8
V
.......
VR
4.00
4.0
4.0
V
:::J:
VF
o
o
o
V
150
150
(')
mA
0.5
0.45
0.45
150
lOLl
.95
...
IOL2
8.0
8.0
7.5
mA
(')
Vox
40.00
40.0
40.0
V
Z
test limits (Note 1) DHOOll
PARAMETER
MIN
VaLl
V OL2
V OH
-55°C
MAX
+25°C
MAX
MIN
MIN
+125°C
MAX
UNITS
0.45
0.4
0.45
V
0.45
0.4
0.45
V
5.0
1.5
JlA
mA
V
1.80
2.00
2.20
2.0
IR
-IF
1.6
1.60
200
5.0
lox
i pDH
'MAX
30.6
JlA
mA
29.6
mA
tON
160
tOFF
220
ns
ns
test limits (Note 2) DHOOllC, DHOOllCN
o°c
PARAMETER
VaLl
V OL2
V OH
+25°C
MAX
MIN
MIN
+70°C
MAX
0.45
0.45
0.5
V
0.45
0.45
0.5
V
10.0
JlA
mA
2.05
1.95
V
1.85
5.0
IR
-IF
UNITS
MAX
MIN
1.ZI0
1.35
1.4
5.0
lox
i PDH
I MAX
200
30.6
JlA
mA
34.0
mA
Note 1: Temperature Range -5SoC to +1 25"C
Note 2: Temperature Range aOc to +70OC
switching time test circuit
c
sov
.,
PIN 10"' Vee" SV
PULSE
~
100 kHz
DUTY £YClE = 50%
±
C~".F·W'."G
~
GE'
FREQ
Typical Switching Times
OUTPUT
PIN 5, PIN 7 GND
CAP.
!
lI!
;:
":"
switching time waveforms
'"
'"
'"
\O~f
",-
so
'r
q,
INPUT
~
"
"
"
\" \" "
~,"--1
',oj
-SO¢C
25"&
12S"e
TEMPERATURE (eel
8-9
z
(.J
...
co
o
o
Interface Ci rcuits
~
c
z
(.J
...o.....
DH0016CN*
D H0017CN*(SH2200P)
DH0018CN*
o
~
c
z
(.J
...
o
high voltage high current drivers
CD
o
~
c
general description
This high-voltage, high-current driver family consists of hybrid integrated circuits which provide a
wide range of output currents and output voltages_
Applications include driving lamps, relays, cores,
and other devices requiring up to 500 mA and
withstanding voltages up to 100V_ Logic flexibility is provided through a 4-input NAND gate, a
NOR input and an input which bypasses the gating
and connects to the base of the output transistor_
'Previously called NH0016CN, NH0017CN, NH0018CN
logic diagram
Vee
10
ordering information
N5C DESIGNATION SH DESIGNATiON
PACKAGE
OUTPUT CHARACTERISTICS
Maximum Standoff
Voltage
8-10
Current
DHOO16CN
N/A
Epoxy "8" DIP
70V
250mA
DHOO17CN
SH2200P
Epoxy "B" DIP
50V
500mA
DHOO18CN
N/A
Epoxy "8" DIP
100V
500mA
C
:::I:
o
o
en
absolute maximum ratings
~
8V
8V
70V
50V
100V
LOA
2.0A
455mW
O°C to +70°C
-65°C to +150°C
Vee
I nput Voltage
Collector Voltage
DHOO16CN
DHOO17CN
DHOO18CN
DHOO16CN
Output Surge Current
DH0017CN & DHOO18CN
Power 0 issipation
Operating Temperature Range
Storage Temperature
(")
Z
C
:::I:
o
o
~
"Z
(")
electrical characteristics
TEST
PIN 1
NO.
2
V rH
3
V'L
4
PIN 2
PIN 3
PIN 4
V rH
V rH
V'H
V'L
5
V'L
6
7
V'L
V'L
8
V'L
9
V'L
10
11
C
:::I:
PIN 5 PIN 6
PIN 7
PIN 8
PIN 9
GND
GND
lOLl
GND
GND
lOLl
V'L
GND
GND
lOLl
V'L
GND
GND
lOLl
V'L
GND
GND
lOLl
V'L
PIN 10
SENSE
MIN
MAX
Vs
VaLl
Vee
Vs
VaLl
Vee
Vs
VaLl
Vee
Vs
VaLl
Vee
Vs
VaLl
Vee
GND
IOL2
Vee
Vs
V OL2
GND
IOL2
Vee
Vs
V OL2
GND
IOL2
Vee
Vs
V OL2
Vee
Vs
V OL2
Vee
Vs
V OL2
V'L
GND
GND
IOL2
GND
IOL2
V'H
12
VR
GND
GND
GND
GND
Vee
11
IR
13
GND
VR
GND
GND
GND
Vce
12
IR
14
GND
GND
VR
GND
GND
Vee
13
IR
15
GND
GND
GND
VR
GND
Vee
14
IR
17
VF
VR
VR
VR
18
VR
VF
VR
VR
19
VR
VR
VF
VR
20
VR
VR
VR
VF
GND
GND
GND
16
GND
21
22
23
Vee
19
IR
Vee
11
-IF
GND
Vee
12
-IF
GND
Vee
13
-IF
Vee
14
-IF
Vee
19
Vee
Vs
Vee
Is
110
lox
110
I MAX
VF
GND
GND
GND
24
25
VR
GND
GND
IOL3
GND
Vox
GND
GND
GND
GND
VPO
V MAX
o
o
LIMITS
~
00
(")
Z
-IF
V OH1
Ipo
forcing functions
O°C
+25°C
Vee
Vpo
V MAX
5.0
V'L
V'H
VR
VF
Vox
Vox
Vox
lOLl
IOL 1
IOL2
IOL3
0.85
1.9
4.5
0.45
50
5.0
8.0
0.85
1.8
4.5
0.45
70
50
100
500
250
16
8.0
SYMBOL
(DHOO16CN)
(DHOO17CN)
(DHOO18CN)
(DH0017CN, DHOO18CN)
(DHOO16CN)
500
250
16
+JO°C
5.0
0.85
1.6
45
0.45
70
50
100
500
250
16
UNITS
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
8·11
z
(J
...
co
o
o
test limits
O°C
0.6
0.45
1.95
SYMBOL
::t:
~
V OL1
C
V OL2
Z
V OHI
(J
"...
o
+25°C
0.6
0.45
1.85
60
1.6
5.0
12.2
10
IA
o
-IF
Z
I MAX
1.6
lox
::t:
C
IpD
+70°C
0.6
0.45
1.65
60
1.6
200
UNITS
V
V
V
IJA
mA
IJA
mA
mA
(J
...
CD
o
o
::t:
C
Typical Output Voltages V$ Temperatura
Typical Switching Times IC = 250 rnA
Typical Switching Times IC = 500 rnA
DHOO16CN
DH0017CN, DH0018CN
~ 04
....~"
~
DHD017CN,DHOO18CN Ie' 500 mA
co
....
co 02
- -
03
>
z
!;i
g;
...
...:1i
!
.,.
I- DH0016CN Ie = 250 mA-
i
a1
r- to~F
-~
-
z 400
~
:0
..
600
~ 500 '-;::
300
--'
...... ......
!
30
.,.
2.0
~
Z
i
200
100
1.0
-I-
ioN
k-"
,., .... '
ION
0
0
25
50
15
0
25
TEMPERATURE rCI
50
15
0
TEMPERATURE rCI
lOY
AI
tc.
---
"N1I- Vcc· SV
PULSE
•••
fRED ·'00 kHz
DUTV CVCLE·_
PlNS,ptN7GND
OUTPUT
....
lI .' ... AI ••
":'
RI
R1
=
2000 (DHOOIICNI
-,oon (DH,,"7CN,
DHOO18CNI
switching time waveform
INPUT
D.
~
1
\
5IJV
\
I.
J
--IoN ....
••
25
50
TEMPERATURE lOCI
switching time test circuit
8·12
-
'oFF
\
II"
f-to" ....
••
our
15
C
::I:
o
o
Interface Circuits
N
00
o
.....
C
::I:
DH0028C/DH0028CN*hammer driver
o
o
N
00
general description
features
The DH0028C/DH0028CN IS a high current
hammer driver designed for utilization in a wide
variety of printer appl ications. The device is
capable of driving 6 amp pulsed loads at duty
cycles up to 10% (1 ms ON/l0 ms OFF). The
input is DTL/TTL compatible and requires only a
single voltage supply in the range of 10V to 45V.
• Low standby power: 45 mW at Vee
35 mW at Vee = 28V.
• AND input
flexibility.
with
expander
affords
o
z
= 36V,
logic
• Fast turn·on, typically 200 ns.
'Previously called NH0028C/NH0028CN
connection diagrams
Metal Can Package
Molded Dual-In-Line Package
OUTPUT
V"
1
10
INPUT
2
,
INPUT
,
EXPANOER
4
INPUT
,
NC
OUTPUT
NC
INTERNAL
CONNECTION
1
GROIIND
•
INPUT
TOP VIEW
typical application
COLUMN ONE
COLUMN TWO
INPUT
INPUT
r-----+----..----1I-~+l6V
~*47j.lF
r-+___-+_____....>-_ _ _+-____
INHIBIT
-;~~g~;Rc;LClE
)-------<~-------_4-...- - - - - - - - + _ 4
2n
3W
HAMMER #1
HAMMER::2
10V
*Use one decouplmg capacitor per SIX hammer dnvers for Improved AC nOise Immumty.
**Zener is used to control the dynamiCs of the hammer.
8·13
z
u
00
N
absolute maximum ratings
o
Continuous Supply VOltage
Instantaneous Peak Supply Voltage
(Pin 1 to Ground for 0.1 sec)
Input Voltage
Expander Input Current
Peak Otuput Current (1 ms ON/l0 ms OFF)
Continuous Output Current DH0028C at 25°C
DH0028CN at 25°C
Operating Tem~ ·ature
Storage Temperature
Lead Soldering Temperature (10 sec)
o
:E:
o
.......
u
00
N
o
o
:E:
Q
electrical characteristics
PARAMETER
45V
60V
5.5V
5.0mA
6.5A
750mA
1000mA
O°C to 70°C
-65°C to +175°C
300°C
(Note 1)
CONDITIONS
MIN
TVP
MAX
UNITS
DB
v
mA
(Note 1.
Logical "1" Input Voltage
v
20
Vee - lOV to 45V
Logical "0" Input Voltage
Vee'" lOV to 45V
Logical "0" Input Current
Vee'" 45V. V IN
0 4V
08
10
Logical "1" Input Current
Vee'" 45V, V IN '" 2 4V
Vee'" 45V, VIN '" 5 5V
05
50
1000
Logical "1" Output Voltage
Vee'" 45V, VIN '" 2 av,
lOUT" 1 6A
Vee'" 36V, VIN "" 2 av,
lOUT'" SA
(Note 2)
Logical "0" Output Voltage
'"
43.0
435
v
335
340
v
020
Vee'" 45V, RL '" lk, VIN '" 0 BV
aov
16
OFF Power Supply Current
Vee'" 45V, V IN
Rise Time (10% to 90%)
Vee'" 45V, RL '" 39!2
VIN := 5 OV peak, PRF '" 1 kHz
02
Fall Time (90% to 10%)
Vee'" 45V, RL = 39H
VIN '" 5 OV peak, PRF '" 1 kHz
30
Vee'" 45V, RL = 39n
VIN '" 5 OV peak, PRF '" 1 kHz
04
Vee = 45V, RL = 39H
VIN '" 5 OV peak, PRF '" 1 kHz
70
TOFF
'"
typical performance characteristics
Waveforms for Typical
Drum Printer Hammer
0
,j
30
20
10
Vec" J6V
TON" 1 ms
TOFf "10 ms
TA '" 25 C
r--
I--
Q
0
0
.!?
I-- I--~AJME~
I-- IIRELiA~
1\
4
IAI
2
K""
R,
6
0
VI I I
0
I'\.
02 04 06 08 10 12 14 16
TIME (ms)
8·14
V,
-L
-10
~
20
v
mA
~s
,
Note 1: These specifications apply for ambient temperatures from DoC to 70°C unless otherwise
speCIfied All tYPIcal values are for 25°C ambIent
Note 2: Measurement made at 1 ms ON and 10 ms OFF
Note 3: Povver ratings for the DH0028C are based on a maxImum Junction temperature of 175°C and
a thermal reSIStance of 2100 C/W
Note 4: Power ratings for the DH0028CN are based on a maxImum Junction temperature of 175°C
and a thermal resIstance of 150oC/W
~
100
C
:I:
o
o
w
Interface Circuits
~
.......
C
:I:
o
o
w
DH0034/DH0034C high speed dual level translator
~
(")
general description
features
The DH0034/DH0034C is a high speed level translator suitable for interfacing to MaS or junction
FET analog switches. It may also be used as a
universal logic level shifter capable of accepting
TTL/DTL input levels and shifting to CML, MaS,
or SL T levels.
• Fast switching, tpdO: typically 15 ns; tpd1:
typically 35 ns
• Large output voltage range: 25V
• I nput is TTL/DTL compatible
• Low output leakage: typically 0.1 IlA
• High output currents: up to ±100 mA
schematic and connection diagrams
Metal Can Package
Dual·in·Line Package
v~
NO
I
14
"
2
"
B,
3
12
B,
4
11
Ne
,
,
7
•
OUTPUT 1
,TOP VIEW
JI1ClrcullSliown
GNO
,
1D
y-
GNO
V"
NO
vONO
.,
y-
OUTPUT 2
Ne
TOPVIEW
typical applications
5 MHz Analog Switch
TTL to IBM (Sl T) Logic Levels
SOY
r--I
_J ----,
I
.10
-::-
I
INPUT 1
>>-.f--+--
OUTPUT 1
-3.
INPUT2
-15
.,OY
> __...--
OUTPUT2
.10
8-15
(.)
~
M
o
o
absolute maximum ratings
c
Vee Supply Voltage
Negative Supply Voltage
-30V
~
Positive Supply Voltage
Differential Supply Voltage
+25V
25V
::z::
......
M
o
o
::z::
c
7.0V
Maximum Output Current
100mA
Input Voltage
Operating Temperature Range:
DH0034
DH0034C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
+5.5V
-55°C to +125°C
O°C to +85°C
-65°C to +150°C
300°C
(See Notes 1 & 2)
CONDITIONS
MIN
DH0034
TYP
MAX
Logical "1"
Input Voltage
Vee = 4.5V
Vee = 4.75V
Logical "0"
Input Voltage
Vee = 5.5V
Vee =4.75V
Logical "1"
Input Current
Vee = 5.5V, Y'N = 2.4V
Vee = 5.25V, Y,N = 2.4V
Logical "1"
Input Current
Vee = 5.5V, Y'N = 5.5V
Vee = 5.25V, Y'N = 5.5V
1.0
Logical "0"
Input Current
Vee = 5.5V, Y'N = O.4V
Vee = 5.25V, Y'N = 0.4V
1.6
Power Supply
30
LogiC "0"
(Note 3)
Vee = 5.5V, Y'N = 4.5V
Vee = 5.25V, Y'N = 4.5V
Power Supply
Current
LogiC "1"
(Note 3)
Vee = 5.5V, Y'N = OV
Vee = 5.25V, Y,N = OV
37
Logical "0"
Output Voltage
Vee = 4.5V, lOUT = 100 rnA
Vee = 4.5V, lOUT = 50 rnA
V- + .50 V- + .75
V- +.3 V- + .50
Output Leakage
Current
Vee = 5.5V, Y'N = 0.8V
V+· V- = 25V
Transition Time to
Logical "0"
Vee = 5.0V, V3= OV,T A= 25°C
V- = -25V, RL = 510n
15
25
Transition Time to
Logical "1"
Vee = 5.0V, TA = 25°C
V- = -25V, RL = 510n
35
60
Current
MIN
DH0034C
TYP
2.0
V
0.8
0.8
40
IJA
40
rnA
10
rnA
1.6
0.1
rnA
38
30
38
37
48
V- + .50
V- +.3
V- + .80
V- + .65
48
rnA
0.1
5
8·16
V
V
5
IJA
15
35
ns
35
65
ns
,
and O°C to +85°C for the DH0034C with a 510 ohm resistor connected between output and ground,
and V- connected to -25V, unless otherwise specified.
Note 3: Current measured is total drawn from V cc supply.
UNITS
V
2.0
Note 1: These specifications apply over the temperature range -5SoC to +12SoC for the DHOO34
Note 2: All typical values are for TA = 25°C.
MAX
C
J:
o
o
w
~
"-
theory of operation
C
J:
When both inputs of the DHDD34 are raised to
logic "1", the input AND gate is turned "on"
allowing aI's emitter to become forward biased.
01 provides a level shift and constant output cur·
rent. The collector current is essentially the same
Vee - V BE
as the emitter which is given by
R1
Approximately 7.0 mA flows out of 01's col·
lector.
o
o
w
About 2 mA of 01's collector current is drawn off
by pull down resistor, R2. The balance, 5 mA, is
available as base drive to 02 and to charge its
associated Miller capacitance. The output is pulled
to within a VSAT of V-. When either (or both)
input to the DHDD34 is lowered to logic "0," the
AND gate output drops to D.2V turning 01 off.
Deprived of base drive 02 rapidly turns off causing
the output to rise to the V3 supply Voltage. Since
02's emitter operates between D.6V and D.2V, the
speed of the DHDD34 is greatly enhanced.
~
(')
applications information
1. Paralleling the Outputs
The outputs of the DHDD34 may be paralleled to
increase output drive capability or to accomplish
the "wire OR". In order to prevent current hog·
ging by one output transistor or the other, resis·
tors of 2 ohms!lDD mA value should be inserted
between the emitters of the output transistors and
the minus supply.
2. Recommended Output Voltage Swing
The graph shows boundary conditions which
govern proper operation of the DHDD34. The
range of operation for the negative supply is
shown on the X axis and must be between -3V
and -25V. The allowable range for the positive
supply is governed by the value chosen for V-. V+
may be selected by drawing a vertical line through
the selected value for V- and terminated by the
boundaries of the operating region. For example, a
value of V- equal to -6V would dictate values of
25
~
20
w
15
~
10
V <-JV
./
~
>
5
::;
~
r--
v+ - V-::;;Z5V
X
~OPERATING REGION -
>
-10
~
-20
,....
>= -15
-25
-
...-
-5
V
-24
-18
-12
-6
NEGATIVE SUPPLY VOLTAGE
I-VI
V+ between -5V and +19V. In general, it is desirable to maintain at least 5V difference between
the suppl ies.
8·17
(,)
It)
(W)
Interface Ci rcuits
o
o
::J:
Q
.......
It)
(W)
o
DH0035/DH0035C PIN diode switch driver
o
::J:
Q
general description
•
•
The DH0035/DH0035C is a high speed digital
driver designed to drive PIN diodes in RF modulators and switches. The device is used in conjunction
with an input buffer such as the DM7830/DM8830
or DM5440/DM7440.
The DH0035/DH0035C is capable of driving a
variety of PIN diode types mcluding parallel,
serial, anode grounded and cathode grounded. For
additional information, see AN-49 PIN Diode
Drivers.
features
•
•
Large output voltage swing - 30V
Peak output current in excess of 1 Amp
•
Inputs TTLlDTL compatible
Short propogatlon delay - 10 ns
High repetition rate - 5 MHz
The DH0035 is guaranteed over the temperature
range _55°C to +125°C whereas the DH0035C is
guaranteed from 0° C to 85°C.
schematic and connection diagrams
Metal Can Package
,,."
""
TOP VIEW
typical applications
Grounded Cath ode Design
".
62!l
Ir---'
II Dr:~E
I
II SWITCH
I
IL __ ...J
;><>--;----t--H
1
211pF
l ' ..
"--L-l~D~~
-
!
V-"-10V
"SJ
Note C~lhode grounded PIN dIOde Rp ~ 6zn limits diode fOlWard cu,ront to 100 rnA Typical SWitching 10'
HP336114A, RF tUrBon 25 os, turn-off 5 AS C2 ~ 250 pF, Rp ~ on, Cl ~ 01F
8-18
-=
C
:I:
o
oto)
absolute maximum ratings
V- Supply Vortage Differential (Pm 5 to Pm 1 or 2)
40V
V+ Supply Voltage Differential (Pin 1 or 2 to Pm 8 or 9)
30V
Input Current (Pm 3 or 7)
±75 rnA
Peak Output Current
± 1 0 Amps
Power DISSipation (Note 3)
1 5W
Storage Temperature Range
-6S0C to +150°C
Operating Temperature Range DH0035
-55°C to +12So C
O°C to +85°C
DH0035C
Lead Temperature (Soldering, 10 sec)
300°C
c.n
......
C
:I:
o
o
to)
electrical characteristics
c.n
n
(Notes 1, 2)
PARAMETER
CONDITIONS
Input LogiC "1" Threshold
V OUT = -8V, RL = lOOn
Input LogiC "0" Threshold
V OUT = +8V, RL = 1000
Positive Output Swing
lOUT
= 100 rnA
Negative Output SWing
lOUT
= 100 rnA
Positive Short CircUit Current
V,N=OV,RL=On
(Pulse Test; Duty Cycle
LIMITS
TYP
MIN
MAX
15
UNITS
V
7.0
0.4
V
-7.0
V
V
+8.0
-8.0
400
800
rnA
800
-1000
rnA
<;: 3%)
Negative Short CircUIt Current
V ,N = 1.5V. liN = 50 rnA, RL = on
(Pulse Test, Duty Cycle <;: 3%)
ns
Turn-On Delay
V ,N = 1.5V. V OUT = -3V
10
15
Turn·Off Delay
VIN = 1 5V, V OUT = +3V
15
30
ns
On Supply Current
V ,N = 1 5V
45
60
rnA
Note 1: Unless otherwise speCified, these specifications apply for V+ = 10.0V, V- = -10.0V, pin 5
grounded, over the temperature range _55°C to +125°C for the DHOO35, and O°C to 85°C for the
DH0035C.
Note 2: All typical values are for T A = 25°C.
Note 3: Derate linearly at 10 mWrC for ambient temperatures above 25°C.
typical applications (cont.)
Grounded Anode Design
Y+=lIlY
~"F
5l1li
~----.1.k,
I~
i
1-
r--..2J.----,
I
I
I
I
I
I
I
lOGIC
INPUT
I
I
IL
...L
I
Q
21l0pF
111
71
I.
>O-7I~--~~H
---J--1/2 OM7B30/0M88l1l
121lPF~
..J
4
OHII035
-~--RM
56n
ch
120pF
-=
V-=-10DV
NOle Anode Graunded PIN dmde, RM .. 56n limIts dlade farwa.d eurrent to 100 rnA Tvplcal SWltthlng for
HPJ3622A, RF turn on 5 ns, turn aff 4 os Cl = 4111 pF, C2 = D1 I'f, RM = on
Alternate Current Limiting
V·
TO
>>---t--<....,W.....--~I~OE
8·19
Interface Circuits
DH3467C quad PNP core driver
typical characteristics
general description
The DH3467C consists of four 2N3467 type PNP
transistors mounted In a 14-pin molded dual-in-Ilne
package. The device IS primarily intended for core
memory application requiring operating currents
in the ampere range, high stand-off voltage, and
fast turn-on and turn-off times.
connection diagram
Turn-ON Time
18 ns
Turn-OFF Time
45 ns
1A
Collector Current
120V typo
Collector-Base Breakdown Voltage
Collector Saturation Voltage
atle=lA
Collector Saturation Voltage
at Ie = O.5A
O.55V
O.31V
Dual-In-Line Package
NO
TOP VIEW
-JOV
-JOV
590
59"
SCOPE
]J
20Qn
lN916
13<1ps
DUTY CYCLE" 2%
SCOPE
200n
PW=200ns
RISETlME:;:;;2 ns
DUlY CYCLE" 2%
"v
fiGURE 2. Turn-Off Equivalent Test Circuit
FIGURE 1. Turn-On Equivalent Test Circuit
Vcc=-30V
DUTY CYCLE" 2%
59.(1
lJ1
1S0n
I'>V
~10V
----\
1
~
C=o
C
TIME---
con
:-10 >IS
FIGURE 3. 0T Test Circuit
8-20
c1s, duty cycle = 1 %
8·21
(.)
It)
N
Interface Circuits
.....
M
::I:
Q
DH3725C quad NPN core driver
typical characteristics
general description
Turn-ON Time
The DH3725C consists of four 2N3725 type NPN
transistors mounted in a 14-pin molded dual-in-line
package_ The device is primarily intended for core
memory application requiring operating currents
in the ampere range, high stand-off voltage, and
fast turn-on and turn-off times_
18 ns
45 ns
Turn-OFF Time
Collector Current
1A
Collector-Base Breakdown Voltage
Collector Saturation Voltage
at le= 1A
Collector Saturation Voltage
at Ie = O.5A
connection diagram
Dual~ln·Line
Package
14
NC
NC
TOP VIEW
switching time test circuit
-Jav
+30V
15n
IKn
TO SAMPLING SCDPE
~
V'N ••"
t,&tt<:;;;l ns
PW"<::l/lS
ZIN=50n
DUTY CYCLE
t..'-t--------:~i:UT
§'"v~sv
"
IIIJSl
"
lN151
"
"
"
10K'
lN451
lN461
-+_------.,-
' - - - - < t - - - - - - - - -.....
:~~:UT
'""
'AdIU' ,,,, •.,.......1,,,:.1 "'•• ,'
w... t.ntwll,nV, ..
SQUARE
5,.V
'""
fMon ....... c.....""c.20pf
~.,n""nlrtll\ll .. yfiOkK.
'""
10 Hz to 10 kHz Voltage Controlled Oscillator
RI
1111
Vt ·5V
1M
5111
RI
V+05V
lilt
A6
llC
'lour
saL/ARE
WAV(
OUTl'UT'
"
llillf"
Low Voltage Adjustable Reference Supply
Zero Crossing Detector driving MOS logic
"
..."
100 kHz Free Running Multivibrator
V··5V
"
IIMOO!
""
OUTl'UT
"
Tn
""
OUTPUT
"
2NlJ48
MAGNETIC
PICKUP
Zero Crossing Detector DriVing MOS SWitch
8-32
Detector for Magnetic Transducer
Comparator and Solenoid Driver
r-
................s:
typical applications (con't)
r-
s:
......
N
fR,QUE' On All Comparators
T A =+25°C
±30
±2S
±5 a
V+-15
08
20
08
Voltage Gam
RL
15 kH, TA = +2SoC
200
200
Large Signal Response Time
V IN = TTL LogiC SWing,
V REF ~ +14 V oc , V RL =
300
300
:;:::
±50
nAoc
V+-t 5
VDC
20
mAoc
V/mV
50V oc and RL =51 kH
Response Time (Note 7)
V RL =50Voc and RL =
51 k!1, T A = +25°C
13
13
"'
Output Sink Current
VIN~ ) :;:::+1 OV ec , V IN1 +) =0
16
16
mAec
and Vo ::;+15 Vec, TA =+2SoC
SaturatIOn Voltage
V IN ( ):;::: +10 Vee, VIN(+l == 0
and ISINK ~40mA, TA ==+2SOC
Output Leakage Current
V IN1 +) :;:::+1 aVec, V INH =0
and V OUT = 5 aVec, T A = +2Soc
Input Offset Voltage
At Output SWitch Pomt, Vo
250
500
250
500
01
01
mVec
nAoc
90
90
rnVec
±100
±15Q
nAoc
300
400
nAoc
V L 20
V+-20
V DC
V IN (_) :;:::+1 OV oc , V IN {+} = 0
and ISINK S 4 rnA
700
700
mVoc
Output Leakage Current
V IN (+) :;:::+1 avoc, V1NH =0
and V OUT = 30 Voc
10
10
/lAce
Differential Input Voltage
(Note 8)
Keep All VIN'S:;:::OV oc {or
V-, If used)
36
36
V DC
0=
14 Vec, V REF == +14 Vac and
Rs =
on
Input Offset Current
IIN(+) - IINH
Input Bias Current
IIN(+) or IINH With Output m
Linear Range
Input Common·Mode Voltage
Range
SaturatIOn Voltage
a
Note 1 For operatmg at high temperatures, the LM339 must be derated based on a +12S C maximum Junction temperature
and a thermal resistance of 175°C/W which applieS for the deVice soldered m a printed CirCUit board, operating m a stili air am·
blent The LM239 and LM139 must be derated based on a +150°C maximum Junction temperature The low bias diSSipation
and the ON-OFF characteristic of the outputs keeps the chip diSSipation very small (Pd ;;:; 100 mW), prOVided the output
transistors are allowed to saturate
Q
Note 2 Short Circuits from the output to V+ can cause excessive heatmg and eventual destructIOn The maximum output
current IS approximately 20 mA Independent qf the magnitude of V+
Note 3' ThiS Inputcurrentwtll only eXist when the voltage at any of the Input leads IS dnven negatIve It IS due to the collector·
base Junction of the Input PNP transistors becoming forward biased and thereby actmg as mput diode clamps I n addItion to
thiS dIode actIon, there IS also lateral NPN parasitic tranSistor action on the IC chip ThiS tranSIstor action can cause the output
voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an mput IS dnven negative ThiS IS not destructive and normal output states WIll re-establish when the mput voltage, whIch was
negative, again returns to a value greater than -03 VOC
Note 4: These speCIfications apply for V+ = +5 0 VOC and -55°C;;:; T A:S +125°C, unless otherWIse stated With the LM239,
all temperature speCificatIons are limited to -2SoC :S T A ;;:; +85°C and the LM339 temperature speCifications are limited to
O"C:STA ;;:;+70"C
Note 5: The direction of the Input current IS out of the IC due to the PNP Input stage ThiS current IS essentially constant,
mdependent of the state of the output so no loadmg change eXIsts on the reference or mput Imes.
Note 6: The mput common·mode voltage or eIther Input Signal voltage should not be allowed to go negative by more than
The upper end of the common·mode voltage range IS V+ -1 5V, but either or both Inputs can go to +30 VOC Without
damage
Note 7: The response time speCified IS for a 100 mV Input step With 5.0 mV overdrive For larger overdrive Signals 300 ns can
be obtamed, see tYPical performance characteristics section
Note 8: The POSItive excurSions of the mputs can exceed the power supply voltage level, and If the other Input voltage remains
Wlthm the common-mode voltage range, the comparator Will prOVide a proper output state. The low Input voltage state
must not be less than -0.3 VOC (or 03 VDC below the magnitude of the negatIve power supply voltage, If used).
o 3V
8·41
en
M
M
typical performance cha racteristics
:E
...I
......
en
Supply Current
M
N
..
:E
...I
......
en
1.0
0.8
oS
T. - -55°s...+-
. -;
......
. .,
....
M
>
~
~
0.4
I
0.2
~
0
'I:
~
TA - +70°C
J 1
I I
60
1....
!-f.'::25°C
!l;
+-
r-
L. T~ =olc
....
ili 0.6
a:
B
Output Saturation Voltage
I nput Current
80
I
40
TA
:!
20
TA=+125°~
=
I
I I
~j
10
30
40
20
v+ - SUPPLY VOLTAGE (Vee)
0
'"'"
....
~0»
>~~
~
~
3
2
1
0
1--1 I I I I
2om~'~L~
100 mV
I I I
I I I
0
-50
> •
iA=ksoL
!;;> -100
!!
0.5
1.0
1.5
2.0
TIME (#Asec)
0.1
TA = +25°C
@'TA--55°C
~I'"
~V
I
0
rtcl-
fH
TA=+125°~
~
a:
.... 0.01
:Ji
>
0.001
40
1
"TA=+25°C
I/:: V
0.01
10 -
I
0.1
1.0
10
100
OUTPUT SINK CURRENT (rnA)
Response Time for Various
Input Overdrives - Positive
Transition
~
~g?!
!;::
~
6
o;:-'NPUT OVERORIVE =100 mV
5
I
Ll 1
LL 5mV
20 mV 11
2
1
0
'"~> 100
C;.! 50
> •
0
f>
I !
4
3
,~~.
H
- '.
t-t-1A~21
I
I I I
:!
0
z
f r-
1A:f
=
1\
0>
.... >
"'~.§.
'"'"
1.0
~>
10
20
30
v+ - SUPPLY VOLTAGE (Vee)
5 mV = INPUT OVERDRIVE
4
w
.
Response Time for Various
Input Overdrives - Negative
6
5
OUT OF
r- r- -SATURATION
~
1(J9n
Transition
..;
~
=0 Voe
O°C
~
I RL =-
V1NjCMI
R1N!CM' ~
T; =_J5°C
....
i<
T. -+12SOC- t-
10
0
0.5
1.5
1
TIME",,,)
2
application hints
The LM139 is a high gain, wide bandwidth
device; which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed
to capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator changes states. Power supply bypassing is not reqUired to solve this problem. Standard PC board
layout is helpful as it reduces stray input-output
coupling. Reducing the input resistors to <10 kn
reduces the feedback signal levels and finally,
adding even a small amount (1 to 10 mV) of posi·
tive feedback (hysteresis) causes such a rapid tran·
sition that oscillations due to stray feedback are
not possible. Simply socketing the IIC and attaching resistors to the pinS will cause input·output
oscillations during the small transition intervals
unless hysteresis IS used. If the Input signal is a
pulse waveform, with relatively fast nse and fall
times, hysteresIs IS not required.
All pins of any unused comparators should be
grounded.
The bias network of the LM139 establishes a
drain current which is independent of the magnltude of the power supply voltage over the range of
from 2V DC to 30 V DC .
It is usually unnecessary to use a bypass capacitor
across the power supply line.
8-42
The differential Input voltage may be larger than
V+ without damaging the device. Protection should
be provided to prevent the input voltages from
gOing negative more than -0.3 V DC (at 25° C). An
input clamp diode and input resistor can be used
as shown in the applications section.
The output of the LM 139 IS the uncommitted
collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OWing function. An output "pullup" resistor can be connected to any available
power supply voltage within the permitted supply
voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which
is applied to the V+ terminal of the LM 139 pack·
age. The output can also be used as a simple SPST
switch to ground (when a "pull-up" resistor is not
used). The amount of current which the output
device can sink is limited by the drive available
(which is independent of V+) and the ~ of this
device. When the maximum current limit is
reached (approximately 16 mAl. the output transistor will come out of saturation and the output
voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60n
rsat of the output transistor. The low offset voltage
of the output transistor (1 mV) allows the output
to clamp essentially to ground level for small load
currents.
~
....
typical applications (con't)
Co)
CD
.......
r-
+5V oc
3:
v·
N
Co)
CD
.......
r-
39k
3:
Co)
- 12V oc
TEMPERATURE
SENSING
THERMOCOUPLE
Co)
DM14XX
CD
*ClAMPS II LEVEL
MOS to TTL Logic Translator
Ground Referenced Thermocouple
in Single Supply System
v·
j5V oc )
+5V oc
lN914
P
1M
+VREf4
'"
Remote Temperature Sensing
+5 Vue
360
+5Voc
p
+V REF3
10.
+5V oc
V,.
36.
TTL to MOS Logic Converter
P
+ISVoc
+VREF2
"
1M
R2
IIlOk
36.
BOpF
,r1
V·
61l~o
",
1M
1M
1M
Visible Voltage Indicator
*FOR lARGE RATIOS OF AI/R2.
01 CAN BE OMITTED
Pu lse Generator
8-43
o
CD
M
Interface Circuits
:E
o
...I
........
CD
N
~
........
LM160/LM260/LM360 high speed differential comparator
o
...
CD
~
general description
features
The LM 160/LM260/LM360 IS a very high speed
differential mput, complementary TTL output
voltage comparator with Improved characterIStiCS
over the IlA76011lA760C, for which It IS a pm-forpm replacement. The device has been optimIZed
for greater speed, mput Impedance and fan-out,
and lower mput offset voltage TYPically delay
vanes only 3 ns for overdrive vanatlons of 5 mV
to 500 mY.
•
Guaranteed high speed
•
Tight delay matchmg on both outputs
•
Complementary TTL outputs
•
High Input Impedance
•
Low speed variation with overdrive variation
•
Fan-out of 4
•
Low Input offset voltage
•
Series 74 TTL compatible
Complementary outputs having mmlmum skew
are provided. Applications IOvolve high speed
analog to digital convertors and zero-crossmg
detectors In disc file systems.
20 ns max
schematic and connection diagrams
Metal Can Package
Order Number LMI60H, LM260H, or LM360H
See Package 11
Dual-In-Line and Flat Packages
Order Number LM360N
See Package 22
or
Order Number LMI60D, LM260D, or LM360D
See Package 1
or
Order Number LM160F
See Package 4
8-44
r-
....s:
absolute maximum ratings
en
o
Positive Supply Voltage
+8V
Negative Supply Voltage
~8V
Peak Output Current
Differential Input Voltage
Input Voltage
v+
20 rnA
±5V
?V 1N ?V~
........
Operatmg Temperature Range
LM160
LM260
LM360
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
iN
~55°C to
+125°C
-25°C to +85°C
en
o
O°C to +70D C
-65°C to +150°C
300°C
........
r-
s:
Co.)
en
o
electrical characteristics
(T M1N 'STA 'ST MAX )
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Conditions
Supply Voltage Vee +
Supply Voltage Vee
-
4.5
5
65
5
~5
-65
V
5
mV
~4
Input Offset Voltage
Rs
:S
200D.
2
Input Offset Current
V
3
J.lA
20
J.lA
13
25
ns
T A = 25°C. Vs = ±5V INote 21
12
20
ns
T A = 25°C. Vs = ±5V INote 31
14
ns
.5
Input Bias Current
5
Output Resistance (Either Output)
V OUT
Response Time
T A = 25°C, Vs = ±5V INote 1)
=
V OH
D.
100
Response Time Difference Between Outputs
(t pd of
+VIN 1) -
(t pd of +V IN2 )
(tPd
of +V IN1
(tpd
of -V IN1)
-
) -
(t pd of -V IN2)
T A = 25°C. INote 11
2
ns
(t pd of -V IN1
)
TA = 25°C, (Note 1)
2
ns
(tpd of +V 1N2 )
T A = 25°C, INote 11
2
ns
(tpd of -V IN2 )
TA = 25°C, INote 1)
2
ns
kD.
Input Resistance
f= 1 MHz
17
Input Capacitance
f= 1 MHz
3
pF
Average Temperature CoeffiCient of Input
Offset Voltage
Rs = 50D.
8
J.lV/"C
7
nA/oC
±45
V
Average Temperature CoeffiCient of Input
Offset Current
Common Mode Input Voltage Range
±4
Vs = ±6 5V
V
±5
Differential Input Voltage Range
Output High Voltage (Either Output)
lOUT = -320}1A, Vs
Output Low Voltage (Either Output)
ISINK =
Positive Supply Current
Vs = ±6.5V
18
32
mA
Negative Supply Cur ;ent
Vs=±65V
~9
-16
mA
=
±4 5V
24
V
3
.4
25
6.4 mA
V
Note 1: Response time measured from the 50% pOint of a 30 mVp.p 10 MHz sinusoidal Input to the 50% pOint of the output.
Note 2: Response time measured "rom the 50% point of a 2 Vp.p 10 MHz sinUSOidal Input to the 50% point of the output.
Note 3: Response time measured from the start of a 100 mV Input step with 5 mV overdrive to the time when the output
crosses the logic threshold.
8-45
illS
Interface Circuits
LM1611LM2611LM361 high speed differential comparators
general description
features
The LM161/LM261/LM361 IS a very high speed
dlfferentl'al Input, complementary TTL output
voltage comparator with Improved characterIStics
over the SE529/NE529 for which It IS a pln-for-pln
replacement The deVice has been optimized for
greater speed performance and lower Input offset
voltage_ TYPically delay varies only 3 ns for
over-drive variations of 5 mV to 500 mV. It may
be operated from op amp supplies (± 15V I
•
I ndependent strobes
•
Guaranteed high speed
•
Tight delay matchmg on both outputs
•
Complementary TTL outputs
•
Operates from op amp supplies
•
Low speed variation with overdrive variation
•
Low Input offset voltage
•
Versatile supply voltage range
Complementary outputs haVing minimum skew
are prOVided. Applications Involve high speed
analog to digital convertors and zero-crossing
detectors In diSC file systems
schematic and connection diagrams
20 ns max
±15V
Dual-I n-Line and Flat Package
"
Order Number LM361N
See Package 22
or
Order Number LM161D, LM261D or LM361D
See Package 1
or
Order Number LM161 F
See Package 4
Metal Can Package
".
Order Number LM161H or LM261H
See Package 12
logic diagram
"
8-46
r-
absolute maximum ratings
operating conditions
Positive Supply Voltage, V+
Negative Supply Voltage, VGate Supply Voltage, Vee
Output Voltage
Differential Input Voltage
Input Common Mode Voltage
Power DISSipation
Storage Temperature Range
Operating Temperature Range
LM161
LM261
LM361
Lead Temperature (Soldering, 10 sec)
Supply Voltage V+
LM1611LM261
LM361
Supply Voltage VLM161/LM261
LM361
Supply Voltage Vee
LM161/LM261
LM361
MAX
.......
5V
5V
15V
15V
s:
N
-6V
-6V
-15V
-15V
MIN
+16V
-16V
+7V
+7V
±5V
±6V
600 mW
-65°C to +150°C
......s:
en
TYP
45V
4.75V
5V
5V
r-
...
en
.......
r-
s:W
...en
55V
525V
-5SoC to +125°C
-2SoC to +85°C
O°C to +70°C
300°C
electrical characteristics
(y+" +lOV, Vee'" +5V, Y-
=
-lOV, TMIN S;; T A ~ T MAX. unless noted~
LIMITS
PARAMETER
lM161/LM261
CONDITIONS
MIN
TVP
UNITS
LM361
MAX
MIN
TVP
MAX
IniJut Offset Voltage
mV
Input Bias Current
u
TA - 2S C
10
30
20
"A
"A
Input Offset Current
TA _ 25°C
"A
"A
Voltage Gain
TA - 25'C
V/mV
Input Resistancf'
T A - 25"C, f
Logical "'" Output Voltage
Logical "0" Output Voltage
1 kH7
20
475V,
ISOURCE - -SmA
Vco
Vco
~
24
H1
20
33
24
V
33
4 75V,
V
64 rnA
ISINK
525V,
Strobe Input "1 ' Current
200
24V
525V,
- 4V
Strobe Input "0" Current
200
-16
16
mA
V
Strobe Input "0" Voltage
Vco
475V
Strobe Input "1 ' Voltage
Vco
475V
Output Short CirCUit Cwrent
Vco
5 2SV. V OUT
Supply Current It
y+ = lOY. V - -IOV,
Vee'" 5 25V,
-5S u C:O; T A <::: 12SQc
V
OV
18
55
--55
18
mA
mA
45
V+"" lOY, V '" -lOV,
Vee = 525V,
SUlJpiy Current It
"A
mA
DoC:::' TA.s; 70°C
Vt- '" lOY, y-" -lOV,
Vee
Supply Current I
=
mA
10
525V,
55'C C. for operating at elevated temperatures,
deVices must be derated linearly at 12 5 mWt>C LM1414 ceramiC package The maximum Junction temperature IS +95°C for
operating at elevated temperatures, deVices must be derated linearly at 125 mW/"C LM1414 molded package The maximum
Junction temperature IS +115"C, for operating at elevated temperatures, deVices must be derated linearly at 6 7 mW/"C
Note 3 The response time specified (see Definitions) for a 100 mV Input step With 5 mV overdnve
Note 4' For LM1514, TL = _55°C, TH:: +125°C For LM1414, TL:: O°C, TH = +70"C
8-64
~
mA
r-
s:UI
Interface Circuits
UI
N
o
.......
LM5520/LM7520 series
dual core memory sense amplifiers
general description
The devices in this series of dual core sense
amplifiers convert bipolar millivolt-level memory
sense signals to saturated logic levels. The design
employs a common reference input which allows
the input threshold voltage level of both amplifiers
to be adjusted. Separate strobe Inputs provide time
discrimination for each channel. Logic inputs and
outputs are DTLlTTL compatible. All devices of
the series have identical preamplifier configurations, while various logic connections are provided
to suit the specific application.
The LM5520/LM7520 has output latch capabli Ity
and provides sense, strobe, and memory function
for two sense lines. The LM5522/LM7522 contains a single open collector output which may be
used to expand the number of inputs of the
LM5520/LM7520, or to drive an external Memory
Data Register (MDR). Intended for small memories the two channels of the LM5524/LM7524 are
ind~pendent with two separate outputs. The
LM5534/LM7534 is similar to the LM5524/
LM7524 but has uncommitted, wire-ORable outputs. The LM5528/LM7528 has the same logic
configuration of the LM5524/LM7524 and in
addition provides separate low impedance Test
Points at each preamplifier output. A similar
device having uncommitted, wire-O Rabie outputs
is the LM5538/LM7538.
features
• High speed
•
Guaranteed narrow threshold uncertainty over
temperature.
r-
s:
.....
UI
N
o
• Adjustable input threshold voltage
rJ)
.,
(\)
• Fast overload recovery times
(\)
1/1
• Two ampl ifiers per package
• Molded or cavity dual-in-line package
• Six logic configurations
The part number ending with an even number
(e.g, LM5520) designates a tighter guaranteed
input threshold uncertainty than the subsequent
odd number ending (e.g., LM55211. The remaining
specifications for the two are identical. All devices
meet or exceed the specifications for the corresponding device (where applicable) in the
SN5520/SN7520 series and are pin-for-pin replacements.
absolute maximum ratings
Supply Voltage
Differential or Reference Input
Voltage
Logic Input Voltage
Operating Temperature Range
LM55XX
LM75XX
Storage Temperature Range
±7V
±5V
+5.5V
-55°e to +125°e
oOe to +70 o e
-65°e to +150 o e
typical application
Expanded Small Memory System
8-65
(II
ell
'':::
ell
en
o
N
an
.....
:E
LM5520/LM7520 and LM55211LM7521
electrical characteristics
.......
LM5520/LM5521 : The following apply for -55°e:<;; TA :<;; 125°e (Note 1)
....I
o
TEST CONDITIONS lEACH AMPLIFIER)
N
an
an
:E
....I
PARAMETER
MIN
1018)
Differential Input
Threshold Voltage
(VTHI INoie 2)
35(33)
Differential & Reference
TYP
15
15
40
40
20(22)
451471
100
30
Input Bias Current
MAX
UNIT
mV
mV
mV
mV
"A
DIFF
INPUT
REF
INPUT
tV TH
:!:VTH
16mV
15mV
40mV
tV TH
OV
:!:VTH
STROBE
INPUT
GATEQ
INPUT
+5V
+5V
40mV
+5V
+5V
+5V
+5V
OV
+525V
+525V
GATEii
INPUT
'5V
+5V
LOGIC
OUTPUT
INOTE3)
SUPPLY
VOLT
+16mA(Q)
-400 "AIO)
+16mA(O}
±5V
±5V
±5V
-400 "AIOI
tSV
+525V
COMMENTS
Logic Output <0 4V
Logic Output >2 4V
Logic Output <0 4V
Logic Output >2 4V
±S2SV
LM7520/LM7521: The following apply for oOe:::; T A :::; 700 e
11(8)
D,fferentlallnput
Threshold Voltage
361331
(VTHI (Note 4)
D.fferentlal & Reference
Input BIas Current
15
15
40
40
441471
mV
mV
mV
mV
30
75
"A
19(22)
tV TH
40mV
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
OV
+525V
+525V
+525V
±525V
+525V
±525V
:!:VTH
15mV
15mV
40mV
:!:VTH
OV
:!:VTH
+16 mAtO)
-400 "AIOI
+16 mAtO)
-400 "AIOI
±5V
±5V
±5V
±SV
Logic Output <0 4V
Logic Output >2 4V
Logic Output <0 4V
Logic Output >2 4V
LM5520/LM5521: The following apply for -55°e:::; T A :::; 125°e
LM7520/LM7521: The following apply for oOe:::; T A :::; 700 e
Differential Input Offset
LogiC "1" Input Voltage
(Strobes)
(GateQ)
{Gate
a)
a)
LogIC "0" Input Current
-1
LogIC "1" Input Current
(Strobe & Gate
(Gate a)
5
a)
02
5
02
a)
24
24
24
LogIC "0" Output Voltage
(Strobe)
(Gate a)
(Gate
a Output Short
Circuit Current
+525V
+525V
V
V
V
40 mV
40 mV
40mV
20mV
20mV
20mV
+2V
OV
OV
.475V
+2V
OV
08
08
OB
V
V
V
40 mV
40mV
40mV
20mV
20mV
20mV
+08V
OV
OV
-16
mA
40mV
20mV
40
1
40
1
"A
mA
"A
onA
OV
OV
40mV
40mV
20mV
20mV
20mV
20mV
V
V
V
40mV
40mV
40mV
V
V
V
39
39
39
025
025
025
a)
a Output Short
CircUit Current
OV
"A
2
2
2
LogiC "0" Input Voltage
(Strobes)
(Gate a)
(Gate
LogIC "1" Output Voltage
(Strobel
(Gateal
(Gate
OV
05
Current
040
040
040
'2V
-400 "AIO)
+16mAta)
+16 mAIO)
±5V
±5V
±5V
LogiC Output >2 4V
LogiC Output <0 4V
LogiC Output <04V
+475V
+08V
OV
+16mAla)
+OSV
-400 "Aliil
±5V
±5V
±5V
LogiC Output <0 4V
LogIC Output >2 4V
LogiC Output >2 4V
+04V
+04V
+04V
±525V
Each Input
+24V
+525V
+525V
+525V
+525V
+525V
+24V
+525V
+24V
+525V
±525V
±525V
±525V
±S 25V
Each Input
Each Input
20mV
20mV
20mV
+20V
OV
t475V
+525V
+OSV
OV
+0 BV
40mV
OV
OV
20mV
20mV
20mV
tOBV
OV
OV
+475V
+2V
OV
+2V
-400~IOI
-3
-4
-5
mA
OV
20mV
OV
OV
-21
-28
-35
mA
OV
20mV
OV
OV
ov
-400 "AIOI
-400 "AIOI
-400.uA{Q)
±475V
±475V
:t475V
+16mA(a)
+16mA(al
+16mA(OI
±475V
±475V
±475V
OVIOI
±525V
OVla)
±525V
V+ Supply Current
21
35
mA
OV
20mV
OV
OV
OV
±525V
V- Supply Currel1t
-13
-18
mA
OV
20mV
OV
OV
OV
±525V
Note 1 For OOC ~ T A ~ 70°C operation, electncal characterIStics for lM5520 and lM5521 are
guaranteed the same as LM7520 and lM7521, respectively
Note 2
Note 3
Limits m parentheses pertam to LM5521. other limits pertam to lM5520
a or Q m parentheses indIcate a or a logiC output, respectively
Note 4. limits 10 parentheses pertam to lM7521, other limits pertam to LM7520
NoteS POSItive current IS defmed as current mto the referenced pm
Note 6
8-66
Pm 1 to have ~100 pF capacitor connected to ground
r-
s:
en
en
N
o
r-
......
LM5520/LM7520 and
electrical characteristics
s:-...I
LM55211LM7521
en
LM5520/LM5521 and LM7520/LM7521: The following apply for T A
N
= 25°C, V+ = 5V, V- = -5V
o
en
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
DIFF
INPUT
REF.
INPUT
STROBE
AND
GATE
INPUTS
AC Common Mode
Input FIring Voltage
V
±25
PULSE
20mV
'5V
Q
LOGIC
OUTPUT
ACTEST
CIRCUIT
20
O,fferentlallnput to
logical "0" Output
Differential Input to
Logical "1" jj Output
D,fferentlallnput to
Logical "0" Q Output
28
10
a
a
Strobe Input to
Logical "1"
a Output
Strobe Input to
Logical "0"
Output
a
ns
20mV
1
28
ns
20mV
1
36
ns
20mV
1
55
ns
20mV
1
30
ns
20mV
1
ns
20mV
20
33
Strobe Input to
Logical "0" Q Output
16
Gate a Input to
Logical "1" Q Output
12
a
Gate Input to
logical "0" Q Output
Gate
a Input to
Logical "1"
aOutput
Gate 0 Input to
ns
20mV
1
55
ns
20mV
1
20
ns
20mV
2
6
ns
20mV
2
17
ns
20mV
2
ns
20mV
2
ns
20mV
2
ns
20mV
2
aOutput
19
Gate is: Input to
LogIcal "1"
Output
12
Logical "0"
a
a
Gate Input to
LogIcal "0" Output
a
Dlff Input Overload
Recovery TIme
Common Mode Input
Overload Recovery
TIme
Min Cycle Time
1
"
Strobe Input to
Logical" 1" Output
a
40
6
30
20
10
ns
5
ns
200
ns
:::!.
CD
UI
SCOPE
Propagation Delays
DIfferential Input to
Logical "1" Output
CD
8·67
III
CI)
''::::
LM5520/LM7520 and LM5521/LM7521
CI)
o
o
N
Ln
.....
schematic diagram
:iE
......I
"o
v·o-----------~----~--------_,
N
Ln
Ln
:iE
......I
GAT~ o----l----I-~==+=!:==~~!::+_------__,
OUTPUT
O------ji---------t--'
GAT~ o------ii---------t----+--++--'
D
STROBE B
L----__-.e----~~-----.~O-OG.D
connection diagram
Dual-In-Line Package
STROBE
GATE
V·AQ
elM'
"----...,...-DIFFERENTIAL
INPUT A
8-68
OUTPUT OUTPUT STROBE
0.0:
-
+
~
REFERENCE
."'UT
GATE
BIIGNO
~
DifFERENTIAL
INPUT I
v-
roo
LM5522/LM7522 and LM5523/LM7523
electrical characteristics
3:
LM5522/LM5523: The following apply for -55°C::; T A ::; 125°C (Note 1)
N
en
en
o
......
roo
3:
.....
TEST CONDITIONS (EACH AMPLIFIER)
PARAMETER
Differential Input
Threshold Voltage
(VTt-i) (Note 2)
MIN
TVP
10(8)
'5
'5
35(33) 40
40
Differential & Reference
Input Bias Current
30
MAX
201221
45(47)
'00
UNIT
DIFF
INPUT
mV
mV
mV
mV
±VTH
±VTH
±VTH
"A
OV
±VTH
REF
STROBE
GATE
LOGIC
INPUT
INPUT
INPUT
OUTPUT
SUPPLY
VOLT
15mV
15mV
40mV
40mV
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
-400J.l,A
+16mA
-400 p.A
+16mA
±5V
±5V
±5V
±5V
+525V
+S25V
OV
COMMENTS
en
logic Output >2 4V
logic Output <0 4V
LogiC Output >2 4V
N
o
LogiC Output <0 4V
en
±S 2bV
CD
LM7522/LM7523: The following apply for O°C::; T A ::; 70°C
DifferentIal Input
Threshold Voltage
IV TH ) (Note 3)
'5
'5
381331 40
40
44(47)
mV
mV
mV
mV
±VTH
75
"A
OV
'"81
Differential & Reterence
Input Bias Current
30
19(22)
±VTH
tV TH
tV TH
15mV
15mV
40mV
40mV
OV
CD
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+525V
+S25V
-400 ~A
+16mA
-400 "A
+16mA
±5V
±5V
±5V
±5V
III
logiC Output >2 4V
logiC Output <0 4V
logiC Output >2 4V
logiC Out~t <0 4V
:t525V
LM5522/LM5523: The following apply for -SSoC::; TA ::; 125°C
LM7522/LM7523: The following apply for O°C::; T A ::; 70°C
Olff Input Offset Current
LogiC "1" Input Voltage
(Strobes)
(Gate)
LogIC ''0'' Input VoJtage
(Strobes)
(Gate)
-,
logIC "0" Input Current
LogiC "1" Input Current
(Strobes)
+525V
40mV
40mV
20mV
20mV
+2V
OV
+475V
+2V
08
08
V
40mV
40mV
20mV
V
20mV
+08V
OV
+08V
-, 6
mA
40mV
20mV
+04V
+04V
40
"A
mA
40
"A
OV
OV
40mV
mA
40mV
20mV
20mV
20mV
20mV
+24V
+525V
+525V
+525V
+525V
T525V
+24V
+525V
±S 25V
±S 25V
±525V
±525V
V
40mV
20mV
+08V
+2V
V
V
40mV
40mV
20mV
20mV
+2V
OV
+08V
mA
40mV
"A
,
,
(Gate)
lowc "'" Output Voltage
+525V
V
V
05
2
2
24
39
OV
OV
+475V
±525V
+16mA
-400 I-/A
t5V
±5V
-400I-/A
+16mA
t5V
logiC Output >2 4V
LogiC OutPUt <0 4V
±525V
Each Input
±5V
LogiC Output <0 4V
logiC Output >2 4V
-4OO1-/A
±475V
+16mA
+16mA
±475V
±475V
TlePms 10and 12
TIe PIns 10 and 12
OV
±525V
Tie Pins 10 and 12
T525V
±475V
a"
LogiC .. Output Voltage
(Strobes)
(Gatel
Output Short CIrCUit
Current
Output Leakage Current
025
025
-2 ,
-28
00'
040
040
-35
250
"A
+475V
20mV
OV
+525V
OV
20mV
OV
+2V
V+ Supply Current
23
38
mA
OV
20mV
OV
OV
±525V
V- Supply Current
-'3
-'8
mA
OV
20mV
OV
OV
±525V
LM5522/LM5523 and LM7522/LM7523: The following apply for TA ; 25°C, V+; 5V, V-; -5V
AC Common Mode Input
Firing Voltage
Propagation Delays
Differential Input to
logical "1" Output
26
ns
20mV
Ae Test Circuit
ns
20mV
AC Test CircUit
ns
20mV
AC Test Circuit
ns
20mV
AC Test Circuit
ns
20mV
AC Test Circuit
ns
20mV
ACTest C,rC\lIt
2'
Strobe Input to
LogICal"'" Output
22
Strobe Input to
Logical "0" Output
'2
Gate Input to
logical"'" OutPUt
4
Gate Input to
logical "0" Output
'5
Differential Input Overload Recovery Time
'0
ns
5
ns
200
ns
Min Cycle Time
45
40
25
20mV
SCOPE
V
Olfferentlal Input to
LogICal "0" Output
Common Mode Input
Overload Recovery
Time
PULSE
t25
+5V
+5V
Note' For aOc :::; T A :5 70"C operation, electrical characteristics for LM5522 and LM5523 are
guaranteed the same as LM7522 and LM7523, respectively
Note 2' Limits In parentheses pertain to LM5623, other Itmlts penaln to LM5522
Nen. 3: Limits In parentheses pertaIn to LM7523. other limits pertain to LM7522
Note 4' POSitive current IS defined as current Into the referenced Pin
Note 6. Pm 1 to have> 100 pF capacitor connected to ground
8-69
(II
CD
Q;
LM5522/LM7522 and LM5523/LM7523
(f)
o
N
LO
.....
schematic diagram
::iii
-I
......
v-o------.--_t-------.
o
N
.J---+------<~CUT
LO
LO
::iii
-I
G. .TEo---4----W~==:j::~==~~~+_-.....,
OlFfERE.TIAL{
'IruTA
STROlE ...
o----t---+1I---+-+-.1
".
OUTPUT
STAOIE
100---t--------+-.1
vL-...-
connection diagram
Dual-' n-Line Package
STROlE
CEXT~~
DiffERENTIAL
REFEREfilCE
INPUT A
INPUT
8-70
~
DiffERENTIAL
INPUT I
v-
....~GND2
r-
s:UI
UI
N
o
.......
r-
s:-...I
LM5524/LM7524 and LM5525/LM7525
electrical characteristics
UI
N
LM5524/LM5525: The following apply for -55°e ~ T A ~ 125°e (Note 1)
o
TEST CONDITIONS (EACH AMPLIFIER)
PARAMETER
MIN
10(B)
Differential Input
Threshold Voltage
35(33)
(VtH) (Note 21
Differential & Reference
Input Bias Current
TVP
15
15
40
40
30
MAX
20(22)
45(47)
100
DIFF.
INPUT
REF.
INPUT
mV
mV
mV
mV
±VTH
15mV
15mV
4QmV
4QmV
"A
OV
UNIT
±VTH
±VTH
±VTH
STROBE
INPUT
OV
+5V
+5V
+5V
+5V
LOGIC
OUTPUT
+16mA
-400jJA
+16 rnA
-40QjJ.A
SUPPLY
VOLT.
±5V
±5V
±5V
±5V
C/)
COMMENTS
Logic
Logic
Logic
Logic
Output <0
Output >2
Output <0
Output >2
LogIc
Logic
Logic
Logic
Output
Output
Output
Output
CD
::::!.
4V
4V
4V
4V
CD
!II
±525V
+525V
LM7524/LM7525 : The following apply for oOe ~ T A :-:;; 70 0 e
11 (B)
Differential Input
Threshold Voltage
(VTHl (Note 3)
36(33)
Differential & Reference
Input Bias Current
15
15
40
40
30
44(471
mV
mV
mV
mV
±VTH
±VTH
±VTH
±VTH
75
"A
OV
19(22)
15mV
15mV
40mV
4QmV
OV
+5V
+5V
+5V
+5V
+16mA
-400p.A
+16mA
-400 "A
±5V
±5V
±5V
±5V
<0 4 V
>2 4 V
<0 4 V
>2 4V
±S 25V
+525V
LM5524/LM5525: The following apply for -55°e ~ T A ~ 125°e
LM7524/LM7525: The following apply for oOe ~ T A ~ 70 0 e
Olff Input Offset Current
Logic "1" Input Voltage
05
Logic "0" Input Voltage
-1
Logic "0" Input Current
Logic "1" Input
Current
5
002
Logic "1" Output Voltage
Logic
"a" Output
24
Voltage
Output Short Circuit
Current
"A
-21
-28
OV
±S 25V
+525V
-400pA
±5V
Logic Output >2 4V
+16 rnA
±5V
Logic Output <0 4 V
40mV
20mV
+2V
OB
V
40mV
20 mV
+0 BV
-16
mA
40mV
20mV
+04V
±525V
40
1
"A
mA
OV
OV
20mV
20 mV
+24V
+525V
±525V
±525V
V
40mV
20mV
+20V
V
40mV
20mV
+0 BV
-35
mA
40mV
20mV
+525V
39
025
OV
V
2
040
-400pA
±475V
+16mA
±475V
OV
±525V
V+ Supply Current
29
40
mA
OV
20mV
OV
±525V
V- Supply Current
-13
-18
mA
OV
20mV
OV
±525V
LM5524/LM5525 and LM7524/LM7525: The following apply for TA = 25°e, V+ = 5V, V- = -5V
AC Common-Mode Input
FIring Voltage
V
±25
PULSE
20 mV
+5V
SCOPE
Propagation Delays
Differential Input to
Logical "1" Output
20
Differential Input to
Logical "a" Output
28
Strobe Input to
Logical "1" Output
10
Strobe Input to
Logical "0" Output
Differential Input Overload Recovery Time
Common-Mode Input
Overload Recovery
Time
MIO Cycle Time
ns
20 mV
AC Test Circuit
ns
20 mV
AC Test CirCUit
ns
20 mV
AC Test CirCUit
20
ns
20mV
AC Test CirCUit
10
ns
5
ns
200
ns
40
30
'S
Note 1: For OoC
T A ~ 70°C operation, electrical characteristics for LM5524 and LM5525 are
guaranteed the same as lM7524 and LM7525 respectively
Note 2: Limits In parentheses pertain to LM5525. other limits pertalO to LM5524
Note 3: Limits 10 parentheses pertain to LM7525, other limits pertalO to LM7524
Note 4: POSitive current IS defined as current Into the referenced Pin
NoteS: Pin 1 to have ~100 pF capacitor connected to ground.
8·71
LM5524/LM7524 and LM5525/LM7525
schematic diagram
v'
~
_ _ _ _ _-.._ _-.._ _ _ _--,
OUTPUT A
OUTPUT I
STROBE aO - - - I - - - - - - - - - t -....
GND2
connection diagram
Dual-In-Line Package
v·
CEXT
STROBE OUTPUT
A
A
~
DiffERENTIAL
INPUT A
8-72
OUTPUT STROBE
GND2
B
-~+
REFERENCE
INPUT
B
NO
CONN
'----.---'
DIfFERENTIAL
INPUT I
GNU1
v-
r-
3:
en
en
LM5528/LM7528 and LM5529/LM7529
electrical characteristics
LM5528/LM5529: The following apply for -55Q C::; TA ::; 125·C (Note 1)
N
o
TEST CONDITIONS lEACH AMPLIFIERI
PARAMETER
Dlfferentlsl Input
Threshold Voltage
(VTH I
(Note 2)
MIN
10181
35(33)
Differential & Reference
Input Bias Current
TYP
15
15
40
40
30
MAX
20(22)
45(47)
100
DIFF.
INPUT
REF.
INPUT
STROBE
INPUT
mV
mV
mV
mV
tV TH
tV TH
15mV
15mV
40mV
40mV
+5V
+5V
+5V
+5V
"A
OV
UNIT
±VTH
±VTH
OV
LOGIC
OUTPUT
+16mA
-400 "A
+16mA
-400 "A
+525V
SUPPLY
VOLT.
COMMENTS
±5V
Logic Output <0 4V
Logic Output >2 4V
±5V
±5V
Logic Output <0 4V
LogiC Output >2 4V
±5V
.......
r-
....3:
en
N
o
en
CD
1525V
LM7528/LM7529 : The following apply for O°C::; TA ::; 70·C
~.
CD
Differential Input
Threshold Voltage
NTH) (Note 3)
11181
361331
Differential & Reference
Input Bias Current
15
15
40
40
30
±VTH
±VTH
441471
mV
mV
mV
mV
75
"A
OV
191221
tV TH
tV TH
15mV
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
+16mA
-400 "A
+16mA
-400 "A
15V
LogiC Output <04V
±5V
logiC
±5V
LogiC Output <0 4V
LogiC Output >2 4V
±5V
til
Output >2 4V
1525V
+525V
LM5528/LM5529: The following apply for -55°C::; TA ::; 125·C
LM7528/LM7529 : The following apply for O°C::; T A ::; 70°C
011f I nput Offset Current
logiC "'" Input Voltage
05
logiC "0" Input Voltage
-1
logiC "0" Input Current
5
002
logiC "'" Input
Current
LogiC "1" Output Voltage
24
LogiC "0" Output Voltage
Output Short CircUit
Current
"A
2
-21
OV
±525V
+525V
±5V
LogiC OutPUt >2 4V
±5V
LogiC Output <0 4 V
40mV
20mV
+2V
08
V
40mV
20mV
+08V
-16
mA
40mV
20mV
+04V
'525V
40
1
"A
mA
OV
OV
20mV
+24V
20mV
+5 25V
±525V
±525V
V
40mV
20mV
+20V
V
40mV
20mV
+08V
+5 25V
39
025
OV
V
040
-400fJA
+16mA
-400 "A
+16mA
±475V
±475V
-28
-35
mA
40mV
20mV
V+ Supply Current
29
40
mA
OV
20mV
OV
±525V
V- Supply Current
-13
-18
mA
OJ
20mV
OV
±525V
OV
1525V
LM5528/LM5529 and LM7528/LM7529: The following apply for T A = 25°C. V+ = 5V. V- = -5V
AC Common-Mode Input
FIring Voltage
V
±25
PULSE
20mV
+5V
SCOPE
Propagation Delays
Differential Input to
Logical "1" Output
20
Differential Input to
Logical "0" Output
28
Strobe Input to
Logical "1" Output
10
Strobe Input to
Logical "0" Output
Differential Input Overload Recovery Time
Common-Mode Input
Overload Recovery
Time
Min Cycle Time
40
ns
20mV
AC Test CirCUit
ns
20mV
AC Test Circuit
ns
20mV
AC Test CircUit
20
ns
20mV
AC Test CirCUit
10
ns
5
ns
200
ns
30
Note 1. For OOC ~ TA ~ 70°C operation, electrical characteristics for LM5528 and LM5529 are
guaranteed tha same as LM7528 and LM7529 respectively
Note 2: Limits In parentheses pertain to LM5529, other limIts pertain to LM5528
Note 3: Limits
In. parentheses
pertain to LM7529, other limits pertain to LM7528
Note 4: POSttlve current IS defined as current mto the referenced pm
Note 5: Pin 1 to have ~ 100 pf capacitor connected to ground
Note 6: Each test point to have ::5: 15 pF capacitive load to ground
8·73
!II
CI)
''::::
LM5528/LM7528 and LM5529/LM7529
CI)
en
o
N
Ln
....
schematic diagram
:E
...I
"o
v·o-----------~~----.---------~
N
Ln
Ln
:E
...I
I-__-l+-==:::j~;--....- ...l
TEST!OINTo-_ _
OUTPUT A
OUTPUT I
STROBEl
TfST POINT 8
0---1---------1--'
0---/---------+
L-----4-~~--~~~OG,O
V·
connection diagram
Dual-In-Line Package
TEST
v+
CE)(T
POINT
TEST
STROBE OUTPUT OUTPUT STROBe
A
A
~
DIffERENTIAL
INPUT A
8-74
A
B
~
REFERENCE
INPUT
POINT
B
•
"--v--'
DIFfERENTIAL
INPUT B
GNG
v-
r-
3:
LM5534/LM7534 and LM5535/LM7535
electrical characteristics
C1I
C1I
N
LM5534/LM5535: The following apply for -55°C::; T A ::; 125°C (Note 11
o
.......
TEST CONOITIONS lEACH AMPLIFIER)
PARAMETER
Differential Input
Threshold Voltage
MIN
TYP
10(8)
15
15
40
40
35(33)
(V TH ) (Note 2)
Differential & Reference
Input Bias Current
30
MAX
20(22)
451471
100
UNIT
mV
mV
mV
mV
"A
DIFF
INPUT
±V nt
±VTH
±VTH
±VTH
OV
REF
INPUT
15mV
15mV
40mV
40mV
OV
STROBE
INPUT
+5V
+5V
+5V
+5V
LOGIC
OUTPUT
+525V
+20mA
+525V
+20 rnA
+52SV
SUPPLY
VOLT
±5V
±5V
±5V
±5V
r-
3:
COMMENTS
Logic
Logic
logic
LogIc
Output
Output
OutPut
Output
.....
<250 ~A
<0 4V
<250 IlA
<0 4V
C1I
N
o
en
±S 25V
aI
~.
LM7534/LM7535: The following apply for O°C::; T A ::;; 70°C
11(8)
DifferentIal Input
Threshold Voltage
(V TH ) (Note 3)
36(33)
Differential & Reference
Input Bias Current
15
15
40
40
30
441471
mV
mV
mV
mV
iV TH
75
"A
OV
19(22)
±VTH
±VTH
±VTH
15 rroV
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
+525V
+20 rnA
+525V
+20mA
±5V
±5V
±5V
±5V
Logic Output <260 J.I.A
Logic Output <0 4V
Logic Output <250 J1A
Logic Output <0 4V
±S 25V
+525V
LM5534/LM5535 : The following apply for -55°C::; TA ::; 125°C
LM7534/LM7535 : The following apply for O°C::; T A ::; 70°C
05
Olff Input Offset Current
Logic "1" Input Voltage
Logic "0" Input Current
"A
logic "1" Input
Current
5
002
logic "0" Output Voltage
025
Output Leakage Current
001
OV
±525V
+525V
40mV
20mV
+08V
+525V
±5V
Logic Output <250 J.l.A
V
40mV
20mV
+20V
+20 mA
±5V
Logic Output <0 4V
-16
mA
40mV
20mV
+04V
±525V
40
"A
mA
OV
OV
20mV
20 mV
+24V
+525V
±525V
±S 25V
20
-1
OV
V
08
Logic "0" Input Voltage
1
V
40mV
20mV
+2V
+20 rnA
:!:475V
250
"A
40rnV
20rnV
+08V
+525V
:!:475V
040
V+ Supply Current
28
38
mA
OV
20rnV
OV
±S 25V
V- Supply Current
-13
-18
mA
OV
20mV
OV
:!:525V
LM5534/LM5535 and LM7534/LM7535: The following apply for TA = 25°C, V+ = 5V, V- = -5V
AC Common-Mode Input
FIring Voltage
PULSE
20mV
+5V
SCOPE
±25
V
24
ns
20 mV
AC Test Circuit
ns
20mV
AC Test CirCUit
ns
20mV
AC Test Circuit
ns
20mV
AC Test Circuit
Propagation Delays
Differential Input to
logical "'" Output
Differential Input to
logical "0" Output
20
Strobe Input to
Logical "1" Output
16
Strobe Input to
logical "0" Output
10
Differential Input Overload Recovery Time
10
ns
5
ns
200
ns
Common-Mode Input
Overload Recovery
Time
Min Cycle Time
40
30
Note 1: For O°C ~T A ~ 70°C operation, electrical characterIStics for LM5534 and lM5535 are
guaranteed the same as LM7534 and LM7535 respectively
Note "2: Limits
In
parentheses pertain to LM5535. other limits pertain to LM5534
Note 3: limits In parentheses pertain to LM7535. other limits pertain to lM7534
Note 4: Positive current IS defined as current mto the referenced pm
Note 5: Pm 1 to have ~ 100 pF capacitor connected to ground
8-75
LM5534/LM7534 and LM5535/LM7535
schematic diagram
v'o-------------~----~~--------_,
OUTPUT A
OUTPUT B
STROBE B
o-----t-----------------1r---'
vGN02
connection diagram
Dual-In-Line Package
v+
CUT
STROBE
A
OUTPUT
A
~
DIFFERENTIAL
INPUT A
8-76
GNOZ
DU11'UT STROBE
8
,
-~+
REFERENCE
INPUT
NO
CONN
~
DIFFERENTIAL
INPUT B
GNol
v-
r-
3:
LM5538/LM7538 and LM5539/LM7539
electrical characteristics
U'I
U'I
LM5538/LM5539: The following apply for -55°C ~ TA ~ 125°C (Note 1)
N
o
.....
TEST CONDITIONS lEACH AMPLIFIER)
PARAMETER
MIN
1018)
Differential Input
Threshold Voltage
(V TH l (Note 2)
35133)
Differential & Reference
Input Bias Current
TYP
15
15
40
40
30
MAX
UNIT
20122)
45t47J
100
DIFF
INPUT
mV
mV
mV
mV
±VTH
±VTH
±VTH
"A
OV
iV TH
REF.
INPUT
STROBE
INPUT
15mV
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
LOGIC
OUTPUT
SUPPLY
VOLT
+525V
120mA
+525V
+20mA
±5V
±5V
±5V
±5V
r-
COMMENTS
3:
.....
LOgiC Output <250 /.lA
U'I
Logic Output <0 4V
Logic Output <250 p.A
Logic Output <0 4V
N
o
en
±S 25V
+525V
CD
LM7538/LM7539: The following apply for
1118)
Olfferentlal Input
Threshold Voltage
(V TH ) (Note 3)
36133)
Differential & Reference
Input Bias Current
15
15
40
40
30
oOe ~ T A
~ 70°C
±VTH
±VTH
15mV
44147)
mV
mV
mV
mV
iV TH
iV TH
40mV
40mV
75
"A
OV
19122)
15mV
OV
CD
+5V
+5V
+5V
+5V
+525V
+20 rnA
+525V
+20mA
+525V
±5V
±5V
±5V
±5V
1/1
LogiC Output <250 /J.A
LogiC Output <0 4V
LogiC Output <250 /J.A
LogiC Output <04V
±S 25V
LM5538/LM5539 : The following apply for -55°C ~ T A ~ 125°C
LM7538/LM7539 : The followi ng apply for 0° e ~ T A ~ 70° e
Olff Input Offset Current
pA
05
LogiC "1" Input Voltage
LogiC "0" Input Voltage
-I
LogiC "0" Input Current
LogIC "1" Input
Current
5
002
LogiC "0" Output Voltage
025
Output Leakage Current
001
OV
OV
40mV
20 mV
+2V
+20mA
±5V
LogiC Output <0 4V
08
V
40mV
20 mV
+oav
+525V
±5V
LogIC Output <250 pA
-16
mA
40mV
20mV
+04V
±525V
40
I
"A
mA
OV
OV
20 mV
20mV
+24V
+525V
±525V
±525V
V
40 mV
20mV
+2 OV
+20mA
±475V
250
"A
40mV
20mV
+OBV
+525V
±475V
040
V+ Supply Current
28
38
mA
OV
20mV
OV
V- Supply Current
-13
-18
mA
OV
20mV
OV
LM5538/LM5539 and LM7538/LM7539: The following apply for TA
AC Common-Mode Input
Flrmg Voltage
±525V
+525V
V
2
±525V
±S 25V
=
25°C, V+
=
5V, V-
=
-5V
SCOPE
±25
V
PULSE 20 mV
DifferentIal Input to
LogIcal "1" Output
24
ns
20 mV
AC Test Cm:::ult
Differential Input to
Logical "0" Output
20
ns
20 mV
AC Test CirCUit
ns
20mV
AC Test Circuit
ns
20mV
AC Test CIrcuit
+5V
Propagation Delays
Strobe I nput to
40
16
logical "'" Output
Strobe Input to
Logical "0" Output
10
Olfferentlal Input Overload Recovery Time
10
ns
5
ns
200
ns
Common-Mode Input
Overload Recovery
Time
Mm Cycle Time
30
Note 1: For oOr; :::;T A:::; 70°C operation, electrical characteristics for lM5538 and lM5539 are
guaranteed the same as LM7538 and LM7539 respectIVely
Note 2: Limits In parentheses pertain to LM5539, other limits pertain to LM5538
Note 3: Limits
In
parentheses pertain to LM7539. other limits pertain to LM7538
Note 4: Positive current
IS
defined as current Into the referenced Pin
Note 5: Pin 1 to have ~ 100 pF capacitor connected to ground
Note 6: Each test pOint to have:::; 15 pF capacitive load to ground
8-77
1/1
Q)
Q;
LM5538/LM7538 and LM5539/LM7539
CIJ
o
N
It)
schematic diagram
"~
...I
~~---------1----~--------'
.......
o
.r--II-----+-oc'"
N
It)
It)
~
REFERENCE{'
INPUT
...I
TEST POINT A
o--~~---l-+--==:::t~---""--......-----..---1>--------......--------<>,,,
TIMI"G
INPUTS
ADDRESS
INPUTS
"
MODESELrCT
~'''"'::~·:'C>''l~l-t~+==~
SELECL
+ __1-'
00-....
Dual·ln-Line Package (J)
8-86
GNU
OUTPUT
Z
2
ISI/IIK)
OUTPUT SOU ACE OUTPUT
V
COLLEt
X
Vee
~SO URCE)
TO RS
(SOURCE)
Dual-In-Line Package IN)
OUTPUT
W
GND
OUTPUT
Z
(SINK)
I
!SINK)
Vee
OUTPUT
V
SOURCE
COLLEC
(SOURCE)
TORS
OUTPUT
X
OUTPUT
W
(SINK)
r-
s:
.....
absolute maximum ratings
(J1
Co)
N
Supply Voltage Vee (Note 1)
Input Voltage (Note 2)
Operating Case Temperature Range
Continuous Total Power DISSipation at
lor Below) +70oC Case Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
17V
5.5V
O°C to +70°C
800 mW
-65°C to +150°C
300°C
dc electric'al characteristics
PARAMETER
Input Voltage Required to Insure logical
"'" At Any Input (V IN(1))
Input Voltage Required to Insure Logical
"0" At Any Input (V IN1OJ )
Logical"'" Level Address Input
Current (1INI1))
Logical"'" Level Tlmmg Input
Current (1INI1))
Logical "0" Level Address Input
Current (I'Nlo)1
Logical "0" Level Tlmmg Input
Current {lINIO)1
(Vee = 14V, Te = o°c to +70°C unless otherwise noted)
CONDITIONS
MIN
Figure 1
0.8
I"A
VIN '" 5V, Figure 1
100
I"A
av, Figure 1
-6
mA
-12
mA
VIN =
VIN "" OV, Figure 1
Source Saturation Voltage (V$at)
VIN = OV, Figure 1
Supply Current. Atl Sources and Sinks
Off IIcci
VIN ==
Supply Current, Either Sink Selected (Icc)
Figure 4
av,
Supply Current, Either S,ource Selected (lcd
Figure 4
Input Clamp Voltage IV 1)
liN
"=
=
075
47 Sil,
075
125
Figure 3
-12 mA, T A
ac switching ch aracteristics
"=
(Vee
=
=
14V, Te
500n, C L
085
200
=
V
I"A
15
mA
40
mA
25
35
mA
V
25°C)
MIN
=
V
125
-15
CONDITIONS
Au'" 53n, RL2
Figure 5
085
30
25°C
TYP
MAX
UNITS
90
ns
50
ns
110
ns
40
ns
70
ns
20 pF,
Propagation Delay Time to Logical "1"
Level, Smk Output (t pd1 )
Smk Storage Time
V
200
Output Reverse Current (Off State) (lOFF)
Propagation Delay Time to Logical "0"
Level, Sink Output (t pdO )
UNITS
VIN '" 5V, Figure 1
'SOURCE':::::: -420 rnA, Rl
Figure 2
Propagation Delay Time to Logical "0"
Level, Source Output (tpdO)
MAX
V
Figure 1
'SINK':';:: 420 rnA, RL = 53Q, Figure 2
PARAMETER
TYP
35
Smk Saturation Voltage (Vsat )
Propagation Delay Time to Logical "1"
Level, Source Output (tPd1 )
.j::Io
AL '" 53n, CL '" 20 pF,
Figure 6
(~)
Fall
Note 1: Voltage values are with respect to network ground terminal.
Note 2: Input Signals must be zero or positive with respect to network ground terminal
8-87
o::t
N
~
truth table
......
~
INPUTS
ADDRESS
OUTPUTS
TIMING
SINK
SOURCES
SINK
A B C D E F G
W
X
Y
Z
0 0 1 1 1
0 1 0 1 1
ON
OFF
OFF
OFF
1
1
1 0
X X
X X
X X
0 0
1 0
X X
X X
X X
1
1
1
1
OFF
ON
OFF
OFF
1
1
1
OFF
OFF
ON
OFF
1
1
1
OFF
OFF
OFF
ON
0 X X
X 0 X
X X 0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
test circuits and switching time waveforms
fTlMiNGiNPiirs - - - - - - - ---,
E
Vee
¢f--------.-t----oO .,.
NOTES)
NOTES I CHECK VINI 1) AND '1".(01 PER TRUTH TABLE
NOTES 2 MEASURE IINlOl PfR TEST TABLE
NOTES 3 WHEN MEASURING liNn). ALL OTHER INPUTS ARE AT GND EACH INPUT IS
TESTED SEPARATELY
TEST TABLE FOR I'NIDI
TEST
I 'NIDI
APPLY 3.5V
GROUND
B, C, E, F, and G
Aand 0
A
B. C. E. F.and G
A and 0
D
A. D. E, F, and G
Band C
B
A, D, E, F,and G
Band C
C
A, B, C, D, F, and G
E
E
A, B, C, D, E,and G
F
F
A, B, C, D, E, and F
G
G
FIGURE 1. VIN(OI. VIN(l). IIN(OI. IIN(l). and IOFF
8·88
test circuits and switching time waveforms (con't)
'5V
riMirW1;uTs"----
-----,¢
Vee
· - - - - - - 0 +14V
I
I
} - -.........-'V'IIr-o+23V
'5V
SEE
TRUTH
TABLE
}-...+----{)."
VSAT
1
NOTE THIS PARAMETER MUST 8E MEASURED USING PULSE TECHNIQUES
tp. 500
"s.
duty cycle S 1%
FIGURE 2. V(SATI
~,;;;-,;;uTs'"---------A ~
Vccyl-'- - - - - - 0 +14V
I
I
53!!
,,"
(NON INDUCTIVE)
}----+--._-.....--<>
50.",
OUTPUT V
--------j
I
'5V----+--r----~
INPUT
"'' ).'..
.
O~~~U~ - - - - - - - '
FIGURE 5. Source-Output Switching Times
8-90
NOTE 2 WHEN MEASURING DELAY TIMES AT OUTPUT
X, APPLY +5V TO INPUT 0, AND GND A WHEN MEASUR
ING DElAY TIMES AT OUTPUT Y. APPLY +5V TO INPUT
A. AND GND 0
test circuits and switching time waveforms (con't)
rTiMiNGiNPii'Ts----------...,
I
v"
9___
- - - - - < 0 H4V
I
I
R,
53!!
(NON
5.
INOUCTlVE~
}-....--1......w..--o +2JV
'-...i--<> +1lV
TI033
NOTE 1 THE INPUT WAVEfORM IS SUPPLIED BY A
GENERATOR WITH THE FOLLOWING CHARACTERISTICS
11.-+-----0 +lV
t, ~ It ~ 10 lIS, DUTY CYCLE 51%, ZOUT '" 5011
NOTE 2 WHEN MEASURING DElAY TIMES AT OUTPUT
W, APPLY +5V TO INPUT 0, AND GNO A WHEN MEASUR
~~GA~riLt:OT~MES AT OUTPUT Z. APPl Y +5V TO INPUT
NOTE J Cl INCLUDES PROBE AND JIG CAPACITANCE
SEE
NOTE
2
)---">-----0 OUTPUT
INPUT
.v
OUTPUT - - - - - ,
FIGURE 6. Sink-Output Switching Times
8-91
Interface Circuits
LM55325/LM75325 memory drivers
general description
The LM55325 and LM75325 are monolithic memory drivers which feature high current outputs as
well as Internal decoding of logiC Inputs. These Cir-
operate at higher source currents for a given
junction temperature If thiS method of source
current setting IS not deSired, then Nodes Rand
CUits are deSigned for use with magnetic memories
RINT
The CirCUit contains two 600 mA sink-switch
pairs and two 600 mA source-switch pairs Inputs
A and B determine source selection while the
source strobe (S,I allows the selected source turn
on In the same manner, Inputs C and 0 determine
Sink s~lectlon while the Sink strobe (S 2 1 allows the
selected Sink turn on
Internal reSIStor connected from V CC2 to Node R
ThiS prOVides adequate base drive for source
currents up to 375 mA With V CC2 = 15V or
600 mA With V CC2 = 24V.
Sink-output collectors feature an Internal pull-up
reSIStor In parallel With a clamping diode connected
to V CC2 This protects the outputs from voltage
surges associated With sWitching inductive loads
The source stage features Node R which allows
extreme fleXibility In source CUI rent selection by
controlling the amount of base drive to each source
tranSIStor ThiS method of setting the base drive
brings the power associated With the reSIStol outSide the package thereby allOWing the CirCUit to
be
can
shorted
externally
activating an
The LM55325 operates over the full military
temperature range of -55°C to +125°C, while the
LM75325 operates from O°C to +70°C
features
•
600 mA output capability
•
24V output capability
•
Dual Sink and dual source outputs
•
Fast SWitching times
•
Source base drive externally adjustable
•
Input clamping diodes
•
DTLlTTL compatible
schematic and connection diagrams
Dual-In-Llne Package
truth table
ADDRESS INPUTS
SINK
SOURCE
STROBE INPUTS
SOURCE
SINK
OUTPUTS
SOURce
B
C
0
51
'2
W
X
v
Z
L
H
X
X
L
H
ON
OFF
OFF
OFF
H
L
X
X
L
H
OFF
ON
OFF
OFF
X
X
L
H
H
L
OFF
OFF
ON
X
X
H
L
H
L
OFF
OFF
OFF
ON
X
X
X
X
H
H
OFF
OFF
OFF
OFF
H
H
H
H
X
X
OFF
OFF
OFF
OFF
,,10lwo"3t ll'V '''''' "m,'
8-92
SINK
A
OFF
r
3:
UI
UI
absolute maximum ratings
Supply Voltage Veel (Note 1)
7V
Supply Voltage VeC2 (Note 1)
25V
Input Voltage (Any Address or Strobe Input)
W
N
UI
........
r
55V
ContinUOus Total DISSipation at (or Below)
+70°C Free-Air Temperature (Note 2)
Operating Temperature Range
LM55325
3:
.....
800mW
-55°C to +125°C
LM75325
UI
O°C to +70°C
-65"C to +150°C
300°C
Storage Tempetature Range
Lead Tempel ature (Soldel mg, 10 sec)
W
N
UI
dc electrical characteristics
LIMITS
PARAMETER
CONDITIONS
LM55325
MIN
High Level Input Voltage
TYP*
UNITS
LM75325
MAX
MIN
TYP*
MAX
V
Figure 1 and 2
(V 1H )
Low Level Input Voltage
(V1d
08
Figure 3 and 4
V ee1 '" 4 5V, V CC2 = 24V,
liN = -12 mA, T A'" 2SoC,
Input Clamp Voltage (VI)
-13
-17
·1 3
08
V
-1 7
V
Figure 5
Source Collector$ Termmal
Off State Current (lOFF)
Vee,
Source Collectors Termmal
Off State Current (I OFF )
Vec1 =45V,V CC2 =24V,
T A '" 25°C, Figure 1
High Level Sink Output
Voltage (V OH )
V ee1 '" 4 5V, V ee2 '" 24V,
lOUT'" OV, Figure 2
Saturation Voltage Source
OutPuts~" (V SAT )
VeC1 '" 4 5V, VCC2 '" 15V,
RL = 24n, ISOURCE "" -600 rnA,
Full Range, (Note 3) Figure 3
Saturation Voltage Source
Outputs .... (VSAT )
Vee1 '" 4 5V, VCC2 '" 15V,
RL '" 24n, ISOURCE ::,; -600 rnA,
T A '" 25°C, (Note 3) Figure 3
Saturation Voltage Sink
Outputs"" (VSAT )
V CC1 ::= 4 5V, V CC2 = 15V,
RL ::= 24n, ISINK ~ 600 mA,
Full Range, (Note 3) Figure 4
Saturation Voltage Sink
Outputs ** (V SAT )
VCC1 '" 4 5V, VCC2 '" 15V,
RL '" 24n, ISINK ~ 600 mA,
T A '" 25"C, (Note 3) Figure 4
Input Current at Maximum
Input Voltage Address Inputs
=
4 5V, VCC2
= 24V,
Full Range, Figure 1
19
500
200
pA
150
200
pA
19
23
09
043
07
043
09
043
07
V
23
043
09
V
075
V
09
V
075
V
VCC1 '" 5 5V, V CC2 '" 24V,
VI'" 5 5V, Figure 5
mA
Input Current at Maximum
Input Voltage Strobe Inputs (II)
V CC1 = 5 5V, VCC2 '" 24V,
VI ::= 5 5V, Figure 5
mA
High Level Input Current
Address Inputs (lIH)
VCC1 '" 5 5V, VCC2 '" 24V,
VI"" 2 4V, Figure 5
40
40
pA
High Level Input Current
Strobe Inputs (lIH)
Vec1 '" 5 5V, VCC2 '" 24V,
VI'" 2 4V, Figure 5
80
80
pA
Low Level Input Current
Address Inputs (lId
VCC1 '" 5 5V, VCC2 '" 24V,
VI ::= 0 4V, Figure 5
-1
-16
-1
-16
mA
Low Level Input Current
Strobe Inputs (lId
VCC1 '" 5 5V, VCC2 '" 24V,
VI ::= 0 4V, Figure 5
-2
-32
-2
-32
mA
Supply Current, All Sources and
Sinks Off From VCC1 (lCCOFF)
V ec1 =55V, VCC'2 =24V,
T A ::= 25°C, Figure 6
14
22
14
22
mA
Supply Current, All Sources and
Sinks Off From VCC2 (Icc OFF)
VCC1 '" 5 5V, VCC2 '" 24V,
T A '" 25"C, Figure 6
20
mA
Supply Current From V CC1,
Either Stnk On (lCC1)
VCC1
Supply Current From V CC'2,
Either Source On (lCC2)
V CC1 '" 5 5V, Vcc '" 24V,
IsouRce '" -;-50 rnA, T A '" 25°C,
Figure 8
(ld
::= 5 5V, V CC2 '" 24V,
ISINK '" 50 rnA, T A'" 25°C,
Figure 7
75
20
75
55
70
55
70
mA
32
50
32
50
mA
[;]I
Note 1: Voltage values are with respect to network ground term mal
Note 2: For operation of LM55325 above +70°C free-air temperature, refer to DISSipation Deratmg Curve (Figure 12).
Note 3: These parameters must be measured uSing pulse techniques tw"" 200/-ls, duty cycle::: 2%
.. All typical values are at T A "" 25° C
""Not more than one output IS to be on at anyone time
8-93
It)
N
('I)
ac switching characteristics
,....
It)
(V CC1
= 5V, TA = 25°C)
:!
...J
.......
LIMITS
PARAMETER
It)
CONDITIONS
UNITS
MIN
TYP
MAX
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
25
50
ns
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
25
50
ns
Output to Source Outputs (tTLH)
V ee2 = 20V, RL = 1 k~,
C L = 25 pF, Figure 10
55
Transition Time, Hlg~ to Low Level
Output to Source Outputs (tTH L)
V ee2 = 20V, RL = 1 k~,
C L = 25 pF, Figure 10
Propagation Delay Time, Low to High
Level Output to Sink Outputs (tPLH)
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
20
45
ns
Propagation Delay Time, High to Low
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
20
45
ns
15
ns
N
('I)
Propagation Delay Time, Low to High
It)
It)
Level Output to Source Collectors (tPLH)
:!
...J
Propagation Delay Time, High to Low
Level Output to Source Collectors (tPHL)
Transition Time, Low to High Level
Level Output
to
Sink Outputs (tPHL)
n;
ns
Transition Time-, Low to High Level
Output to Sink Outputs (tTLH)
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
Transition Time, High to Low Level
Output to Sink Outputs (tTHL)
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
9
20
ns
Storage Time, Sink Outputs (ts)
V ee2 = 15V, RL = 24~,
C L = 25 pF, Figure 9
15
30
ns
dc test circuits
'2VJ
'::'
15££
TEST
TABLEI
'45V~
+
(SEE
TEST
r---_'"
". "."
LV
+45V
+45V
TEST TABLE
TEST TABLE
A
B
Sl
c
0
S2
GND
GND
.2V
2V
45V
GND
2V
2V
GND
2V
VOH
45V
45V
2V
OPEN
OPEN
GND
OPEN
VOH
45V
GND
2V
OPEN
VOH
GND
FIGURE 1. IOFF
8·94
...J
y
VOH
FIGURE 2. VIH and VOH
Z
r-
3:
CJ1
CJ1
W
N
CJ1
de test eireuits(eon't)
+15V
.......
r-
3:
.....
",v1
.,v
CJ1
W
N
CJ1
R,
24
(SEE
TEST
TABLE!
' '1
OPEN
OPEN
<4
lK
L!(xI
_ _ _ _ OND
(SEE
TEST
lAIlLEI
'v
.. IV
NOn: 1 FIGURE 3 AND 4 PARAMETERS MUST BE MEASURED USING PULSE TECHNIQUES
tw ~ 2UII>z
700
~~
600
!!o
~~
=>0
" ..
..~ffi
~
.......
.......
500
'"
400
300
200
DERATE
10.7 mwrc
100
I
I
GNO
_
_ ..I
V OR Z
o
70
80
""H"I
f-- f-- F:5~~90
100
110
120
TA - AM81ENT TEMPERATURE
130
ee)
NOTE" FOR CLARITY, PARTIAL LOGIC DIAGRAMS OF TWO lM551Z5'S ARE SHOWN
NOTE 2 SOURCE AND SINK SHOWN ARE IN DIFFERENT PACKAGES
FIGURE 11. Typ,cal Application Data
8·98
FIGURE 12. Thermal Information
Interface Circuits
LM75451, LM75452, LM75453 dual peripheral drivers
general description
features
These devices are general purpose dual peripheral
drivers, each capable of sinking two independent
300 mA loads to ground. In the off state (or with
Vee = OV) the outputs will withstand 30V. Inputs
are fully DTL!TTL compatible. The LM75451
meets or exceeds the specifications for both the
SN75451 and SN75451A and is a pin-for-pin
replacement. The LM75452 and LM75453 meet
or exceed the specifications for SN75452 and
SN75453, respectively, and are pin-for-pin replace-
•
High speed - 20 ns max (LM75451, LM75453)
25 ns max (LM75452)
•
Both outputs can sink 300 mA simultaneously
•
Withstands 30V on output with Vee = OV for
power strobing applications
•
Input clamp diodes
•
Two separate drivers per package
ments.
schematic diagrams
LM75453
LM75452
LM75451
connection diagrams
truth tables
PositIve logIc
Positive logic
AB= X
AS'" X
A +B- X
B
OUTPUT X·
1
0
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
B
OUTPUT X·
A
B
OUTPUT X*
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
·"0" Output S; 0 7V
"1" Output S 100 p.A
-
PosItive logic
A
A
·"0" Output S 0 7V
"l"OutputS lOO}JA
* "0" Output S O,7V
"1" Output S 100 pA
8-99
absolute maximum ratings
(Note 1)
Supply Voltage Vee
Input Voltage
Output Voltage (Note 2)
Continuous Output Current
Continuous Total Power Dissipation (Note 3)
Operating Free Air Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
7V
5.5V
30V
300mA
800mW
O°C to 70°C
_65°C to 150°C
300°C
electrical characteristics
The following apply for
aOc ~ T A:-:; 70°C, Vee"" 5V ±5%, unless otherWise specified
OUTPUT
Logic "1" Input Voltage
Y'N
30V 1300 rnA)
4.75V
Output~
Logic "0" Input Voltage
Y,N
300 rnA 130V)
475V
Output ~ O.7V
Output leakage Currents
2V 108V)
30V
30V
4.75V
OV
Output LOW Voltages
oav 12V)
l00mA
08V 12V)
300 rnA
4.75V
475V
PARAMETER
SUPPLY
VOLTAGE
(Note 4)
LOGIC
INPUT
Logic "1" Input Currents
24V
55V
5.25V
525V
Logic "0" Input Current
0.4V
525V
OV
5V
OV
5.25V
5.25V
525V
5V
OV
5V
-12mA
COMMENTS
l00IlA 1~0.7V)
MIN
TYP
MAX
2
UNIT
V
08
(::;100~AI
100
100
0.25
0.5
0.4
0.7
V
IlA
IlA
V
V
40
1
IlA
rnA
-1
-1.6
rnA
Per Paokage
48
51
50
60
65
63
rnA
rnA
rnA
5.25V
5.25V
5.25V
Per Package
Per Package
Per Package
7
9
9
11
14
14
rnA
rnA
rnA
5V
TA = 25°C
Supply Currents:
Output Low
LM75451
LM75452
LM75453
Per Package
Per Package
Output High
LM75451
LM75452
LM75453
Input Diode Clamp Voltage
-15
V
The following apply for Vee = 5V, T A = 25°C
Propagation Delay Times'
Input to Output HIGH
LM75451 & LM75453
LM75452
(Note 5)
11
13
20
25
ns
ns
INote5)
INote5)
16
19
20
25
ns
ns
INote 5)
Input to Output LOW
LM75451 & LM75453
LM75452
Output Risetime
4
ns
Output Fatltlme
10
ns
Note 1: All voltage values are wIth respect to ground term mal. PosItIve current IS defined to be current
mto referenced pm.
Note 2: MaxImum voltage to be applied to either output in the off state.
Note 3: The maximum junction temperature is 150°C. For operatmg at elevated temperatures, the
package must be derated based on a thermal resistance of 110°C/W 8JA.
Note 4: Test conditions m parentheses pertam to LM75452, other test conditions pertain to
LM75451 and LM75453.
Note 5: Delays measured with 50n load to 10V. 15 pF total load capacitance; measured from 1.5V
Input to 50% of output.
8·100
Interface Circuits
LM75454 dual NOR peripheral line driver
general description
features
The LM75454 is a dual NOR peripheral line
driver with output transistors rated up to 300mA
continuous current. Both output transistors can
sink this current at the same time, bringing maximum chip power dissipation to 820mW. Switching
speeds are compatible with standard TTL and logic
levels interface directly with TTL, DTL, and
LPTTL logic families. The overall input to output
NOR function allows pin for pin replacement with
TI's SN75454 posItive logic NOR driver.
•
High speed, 25 ns maximum
•
Both outputs can sink 300 mA simultaneously
•
Withstands 30V on outputs
•
Input clamp diodes
•
MaxImum package power dissipation at maximum current rating ~ 820 mW
schematic diagram
veeo---~I-----~~-----t~----------~---,
GNoo-~----I---~~----------~I-----~---t~---e--~
NOTE 1/2 SCHEMATIC SHOWN
connection diagram
Dual~1 n-line
vee
truth table
Package
A,
B,
x,
A
B
X
0
0
1
1
0
1
0
1
1
0
0
0
TOP VIEW
8-101
absolute maximum ratings
(Note 1)
7V
5.5V
30V
300mA
820mW
O°C to +70°C
-65°C to +150°C
300°C
Supply Voltage, vee
Input Voltage
Output Voltage (Note 4)
Continuous Output Current
Continuous Total Power Dissipation (Note 2)
Operating Free Air Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
e lectrica I characteristics
The following apply at
LOGIC
INPUT
OUTPUT
logical "1" Input Voltage
V ,N
300mA
475V
logical "0" Input Voltage
V ,N
30V
475V
PARAMETER
Logical "1" Input Current
o"c;; TA ;; +70"c, Vee
SUPPLY
VOLTAGE
= 5V
COMMENTS
MIN
Output
~
a 7V
20
Output
~
100j..tA
+ 5% unless otherwISe noted.
TYP
MAX
UNITS
V
DB
V
24V
5.25V
40
55V
525V
1
"A
rnA
-16
rnA
-10
525V
Logical "0" Input Current
04V
Output Low Voltage
20V
lOOmA
475V
025
04
20V
300mA
475V
05
07
o BV
30V
475V
100
"A
OBV
30V
OV
100
"A
Output leakage Current
Supply Currents
A, =5V
Output Low
B1 "'OV
Output High
A, '" B, :;; OV
Input Clamp Diode Voltage
Propagation Delay Times
-12mA
The follOWing Apply for Vee'" 5V, T A
=
V
V
5 25V
Per Package
61
79
rnA
525V
Per Package
13
17
rnA
5V
TA
:::
2SOC
-15
V
2Soc
t pd1 , Input "0" to Output "'"
(Note 3)
13
25
n,
t pd1 • Input "1" to Output "0"
(Note 3)
19
25
n,
Output Rlsetlme
n,
Output Falltlme
n,
Note 1:
All voltage values are with respect to ground. Positive current IS defined to be current Into referenced Pin.
Note 2: Maximum junction temperature is 150°C. For operating at elevated temperatures, the package must be derated
based on a thermal resistance, (JJA, of 110°C/W.
Note 3: Delay IS measured With a 50n load to 10V, 15pF load capacitance, measured from 1.5V Input to 50% POint on
output. Unused Inputs should be grounded for this test.
Note 4: Maximum voltage to be applied to either output In the off state.
8·102
Interface Circuits
3:
o
o
o
:z:
.:::!
3:
o
o
o
.....
::I:
MH0007/MH0007C dc coupled MOS clock driver
(")
general description
features
The MH0007 is a voltage translator and power
booster designed for interfacing between conventional TTL or DTL voltage levels and those levels
associated with inputs or clocks of MOS FET type
devices. The design allows the user a wide latitude
in selection of supply voltages, and is especially
useful in normally" off" appl ications, since power
dissipation is typically only 5 milliwatts in the
"off" state.
• 30 volts (max) output swing
• Standard 5V power supply
• Peak currents in excess of ±300 mA available
• Compatible with all MOS devices
• High speed: 5 MHz with nominal load
• External trimming possible for increased performance
schematic and connection diagram
v~
,
10
.J
4.
v'
.s
10 Pin TO-100 Pack_
Jkn
01
v'
INPUT 1
7
INPUT 2
GND
OUTPUT
INPUT
4 --~I--['
TOP VIEW
R2
soon
L.._ _ _.........-._ _ _ _ 6
v-
typical applications
Switching Time Test Configuration
High Speed Operation
2'
INPUT
INPUT
INPUT
INPUT
>-....
r - - - - -.....
--OUTPUT
--OUTPUT
ns} Cl =200 PF
t",,==-30
1aff==-40 M
8-103
(J
o"'"
o
o
l:
~
;:::
o
o
o
l:
~
absolute maximum ratings
Vee Supply Voltage
V- Supply Voltage
V+ Supply Voltage
(V+ - V-I Voltage Differential
Input Voltage
Power Dissipation (T A = 25°C)
Peak Output Current
Storage Temperature Range
Operating Temperature Range MHOOO7
MHOOO7C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
8V
-4OV
+28V
30V
5.5V
800mW
:'.500mA
-65°C to +150"C
_55°C to +125"C
O"Cto +85"C
300"C
(Note 1)
PARAMETER
CONDITIONS
TYP
(Note 2)
MIN
Logical "1" Input Voltage
Vee = 4.5V
Logical "0" Input Voltage
Vee = 4.5V
Logical "1" Input Current
Vee = 5.5V, V IN = 5.5V
Logical "0" Input Current
Vee = 5.5V, V IN = O.4V
Logical "1" Output Voltage
Vee = 5.5V, lOUT = 30 mA, V IN = 0.8V
Vee = 5.5V, lOUT = 1 mA, V IN = 0.8V
MAX
UNITS
V
2.2
0.8
100
1.0
1.5
V+ -4.0
V
p.A
mA
V
V
V+ - 2.0
V- + 2.0
Logical "0" Output Voltage
Vee = 4.5V, lOUT = 30 mA, V IN = 2.2V
Transition Time to
Logical "0" Output
CL = 200 pF (Note 3)
50
ns
Transition Time to
Logical "1" Output
CL = 200 pF (Note 3)
75
ns
Note 1: Min/max limits apply across the guaranteed range of -5SoC to +12SoCfor the MHOOO7,and
from oOe 10 +85°e for Ihe MH0007e, for all allowable values of V- and V+
Note 2: Ali tYPIcal values measured ~I T A = 2Soe Wllh Vee = 5.0 volls, V- =-25 volts, v+ =0 volts.
Note 3: Transition time measured from time VIN
final value.
=
50% value until VOUT has reached 80% of
Allowable Values for V- and V+
V'
VOLTS
or
VOLTS
...
/
7
REGION
8·104
.
..
Maximum Power Dissipation
I.Z
I
.f'.
_ 1.0
C~E
~
"
II
.
·ID
...
.3D
...
i!io.a
;:
::ili 0.&
AM~IENT
Q
r-
ffiOA
~
0.2
i'--..
r---..~
I
0
0
2&
50
16
-
"
100
TEMPERATURE rCI
125
160
V
3:
Interface Circuits
:::I:
o
o
o
CD
.......
3:
:::I:
o
o
MH0009/MH0009C dc coupled two phase MOS clock driver
general description
features
The MH0009/MHOO09C IS high speed, DC coupled,
dual MOS clock driver designed to operate in
conjunction with high speed line drivers such as
the DM8830, DM7440, or DM7093. The transition
from TTL/DTL to MOS logic level IS accomplished
by PNP input transistors which also assure accurate
control of the output pulse width.
• DC logically controlled operation
o
CD
n
• Output Swings - to 30V
• Output Currents - in excess of ±500 rnA
•
High rep rate -
•
Low standby power
In
excess of 2 MHz
schematic and connection diagrams
12· Lead TO·S Package
. - - I . - _ t 2 ~1 OUTPUT
o,INPUTI •
v-
----41--.....- ,
5----41---+--t
., INPUTI 8 - - -....-
....-
....-11 V'
....- { ;
....__14--..... 1•
4Iz INPUT A
.,OUTPUT
V'-"';'v
v·
V'
-12V
typical application
.v~
-----,
I
v:_-~.,
I
I
v -uv
.,
I
I
I
II!..~1I3...!fD_Ml..!.3D___ .J
FIGURE 1
8·105
(.)
en
o
o
o
l:
~
.......
en
o
o
o
l:
~
absolute maximum ratings
V- Supply Voltage: Differential (Pin 5 to Pin 3) or
(Pin 5 to Pin 7)
V+Supply Voltage: Differential (pin 11 to Pin 5)
Input Current: (Pin 2, 4, 6 or 8)
Peak Ol:ltput Current
Power Dissipation (Note 2 and Figure 2)
Storage Temperature
Operating Temperature: MH0009
MH0009C
Lead Temperature (Soldering, 10 Sec.)
electrical characteristics
Pulse Width (50% to 50%)
(Note 1)
MIN
TYP
UNITS
C L = 001 J.lF
10
35
ns
C'N = .0022 J.lF
C L = .001 J.lF
40
50
ns
C'N = .0022 J.lF
C L = 001 J.lF
400
440
ns
C'N = 0022 J.lF
C L = .001 J.lF
80
120
ns
C'N = 600 pF
CL
= 200 pF
10
ns
= 600 pF
CL
= 200 pF
15
ns
C'N = 600 pF
C L = 200 pF
= 600 pF
C L = 200 pF
C'N
340
40
70
40
Note 1: Characteristics apply for Circuit of Figure 1. With V- = -20 volts; V+ = 0 volts; Vee = 5.0
volts. MInimum and maximum limits apply from _55°C to +125°C for the MH0009 and from aOc to
+85°C for the MH0009C. Typical values are for T A 25°C.
Note 2: Transient power IS given by P"" tel (v+ - V-I 2 watts, where f = repetItion rate, CL = load
capaCItance, and (V+ - V-I = output swmg.
Note 3: For typical performance data see the MH0013/MHOO13C data sheet.
i
~
1.50
1-*---1-+-+-+--+-1
1 25
~-II~"->i<--t_+--+-+--I
10
1-+---1"'-""-+-+--+-1
~015~-r--lr-,i"_~-+_+--I
~
«
0.5
0.25
"
~-r-1-+-+-+--+--I
OL-~-L~~
o
25
__L-~-"
50 15 100 125 150
TEMPERATURE I'CI
FIGURE 2. Maximum Power Dissipation
8-106
MAX
C'N = .0022 J.lF
C'N
Pulse Width (50% to 50%)
1.5W
-65°C to +150°C
-55°C to +125°C
O°C to 85°C
300°C
CONDITIONS
PARAMETER
tON
-40V
30V
±75 mA
±500 mA
120
ns
ns
3:
Interface Circuits
::r:
o
...o
N
........
3:
o
::r:
...o
MH0012/MH0012C high speed MOS clock driver
N
n
general description
features
The MHOO12/MH0012C is a high performance
clock driver that is designed to be driven by the
DM7830/DM8830 or other line drivers or buffers
with high output current capability. It will provide a fixed width pulse suitable for driving MOS
shift registers and other clocked MOS devices.
• High output voltage swings-12 to 30 volts
• High output current drive capability-lOOO mA
peak
.
• High repetition rate-l0 MHz at 18 volts into
l00pF
• Low standby power-less than 30 mW
schematic and connection diagrams
.
y'
,
12·lead TO·S Package
R9
'"
c.....
INPUT1 1
~
"IOUTPUT
'"'"
OUTPUT
...14-+--1-0"
GilD &
INPUTZ 3
c_.
R2
1K
TO' VIEW
1
2
y'
typical application
timing diagram
(ac test circuit)
y•
......._.'.T
100
V' -2OV
8-107
(J
...
N
absolute maximum ratings
o
o
Maximum Output Load-See Figure 2
Y- Supply Voltage
Differential (Pm 1 or 2 to
Pm 5)
y+ Supply Voltage Differential (Pm 8 or 9
~
:!
......
to Pm 1 or 2)
...
o
30V
±75 rnA
±1oo0 rnA
Input Current (Pm 3 or 7)
Peak Output Current
N
dc electrical characteristics
o
~
PARAMETER
:!
Power DISSipation-See Figure 1
Storage Temperature
Operating Temperature MHOO12
-40V
15W
-65"C to +150°C
-5SoC to + 12SoC
O"C to +B5°C
MHOO12C
Lead Temperdture (Soldermg, 10 sec)
300°C
(Note 1)
CONDITIONS
MIN
logic "1" Input Voltage
(PinS 7 and 3)
y+ - V - 20V, VOUTY+ -15V
TYP
MAX
UNITS
10
20
V
2V
t
04
06
V
(PinS 7 and 3)
V- + 10
y+ - Y- '" 20V, lOUT'" lmA,
LogiC "1" Output Voltage
Y- + 20
V
VIN =20V
logiC "0" Output Voltage
V t - V- "" 20V, lOUT = - lmA,
V 1N =04V
IDe (V- Supply)
V" - V- == 20V, VIN "" 2 OV
v+ -
y+ - 07
15
V
34
60
TYP
MAX
10
15
ns
5
10
ns
35
50
ns
35
45
ns
rnA
ac electrical characteristics
CONDITIONS (Note 3)
PARAMETER
MIN
Turn-On Delay (toN)
Vj
CL
TA
Rise Time (t,)
Turn-Off Delay (tOFF)
V- '" 20V, V cc = 50V
== 200 pF, f =- 1 0 MHz
== 25"C
-
Fall Time hll
UNITS
Note 1: Characteristics apply for CirCUit of Figure 1_ Mm and max limits apply from -5SoC to +125°C
for the MHOO12 and from O°C to +85"C for the MHOO12C_ Typical values are for T A'" 25°C.
Note 2: Due to the very fast rise and fall times. and the high currents Involved, extremely short connections and good by passing techniques are reqUired.
Note 3: All conditions apply for each parameter.
Maximum Output Load
vs Voltage Swing vs Rise Times
Power Dissipation
Rise and Fall Times vs
Load Capacitance
40
1.5
~
1'\
1.0
C=~
L (V+ _ V-I
i'-.
0:
~
30
~c:>
"-
.5
,.
..,.,.;:;
,
"'-
20
\ _\ !~
I-I--
i
r\,
~ ("
I'
~
:; 30
"
~:
~
~ l- I-
35
!
'%-
" "o~.t ........
~.t
10
~ ~7.
L
~
"-
......
-
;25 r-v' -v- -
..'"
20
~
10
~
r- TA _25°C
20V
~ 15
;:
;;:
-~
S
I-
l-
0
0
25
50
15
100
125
0
150 115
400
1600
1200
800
MAXIMUM OUTPUT LOAO IpFI
AMBIENT TEMPERATURE I'CI
200
400
600
800
1000
LOAD CAPACITANCE, CL IpFI
Figure 2.
Figure 1.
applications information
Power DiSSipation Considerations
Where
The power dissipated by the MH0012 may be
diVided Into three areas of operation'" ON. OFF
and swltchmg The OFF power IS approximately
30 mW and IS diSSipated by R2 when Pm 3 is In
the logic "l"state The OFF power Isnegllbleand
Will be Ignored In the subsequent diSCUSSion. The
ON power IS dISSipated prlmanly by 0 3 and Rg
and IS given by'
_
PON
8·108
:;<
!V+ - V-)2
{tv IIIN + -R-g- - 1 DC
111
ON Time
DC'" Duty Cycle = ON Time & OFF Time
V 1N - V BE3
liN IS given by - - R - , - - and equation !1)
becomes
PON = [IV 'N
-
VRB,E3il v-l +
IV'R~ V-1
The tranSient power Incurred durmg SWitching IS
given by.
PAC = (V+ _V-)2 Clf
131
For V+ '" OV, V- = -20V, C L == 200 pF. and
f"" 5.0 MHz, PAC"" 400 mW
The total power IS given by
2
]
DC 121
PT
'"
PAC +
PON
PT ~ PMAX
For V tN =2 5V, V BE3 = 0 7V. V+ =OV, V- '" -20V,
and DC = 20%, PON :;< 200 mW
For the above example. PT
'"
600 mW.
141
s:
Interface Circuits
::t
o
o
...
to)
.......
s:
MH0013/MH0013C two phase MOS clock driver
::t
o
o
...
general description
features
The MH0013/MH0013C is a general purpose clock
driver that IS designed to be driven by DTL or
TTL line drivers or buffers with high output current capability. It will provide fixed width clock
pulses for both high threshold and low threshold
MOS devices. Two external Input coupling capa·
citors set the pulse width maXimum, below which
the output pu Ise width will closely follow the
Input pulse width or logiC control of output pulse
width may be obtained by uSing larger value input
capacitors and no input resistors.
• High Output Voltage Swings~up to 30V
to)
• High Output Current Drive
500 rnA
• High Repetition
Rate~up
Capability~up
(")
to
to 5.0 MHz
• Pin Compatible with the MH0009/MH0009C
• "Zero" Quiescent Power
schematic and connection diagrams
12-Lead TO-8 Package
D2
.--4.-.....
INPUT A z 4
12 OUTPUT A
INPUT Al
----+-.....-1"
01
v-
5-----t-~--t
11 V'
OJ
INPUTB 1 6---+--..4o--{·
INPUT 82
'--t. .- .... l0
OUTPUT B
TOPVfEW
D4
typical applications
tV ee
~~Pt~~
OUTPUT:
:
Ur - - - -
PUlSE~
INPUT
PULSE
OUTPUT
PUl"
:
U
U-\
8·109
(,)
...o
(W)
o
:t
~
.......
...
(W)
o
o
:t
~
absolute maximum ratings
(V+ - V-I Voltage Differential
30V
Input Current (Pin 2, 4, 6 or 8)
±75mA
Peak Output Current
±600mA
Power Dissipation (Figure 7)
1.5W
-65°C to +150°C
Storage Temperature
-55°C to +125°C
Operating Temperature MHOO13
O°C to +85°C
MHOO13C
300·C
Lead Temperature (Soldering,10 sec 1/16"from Case)
electrical characteristics
(Note 1 and Figure 8)
CONDITIONS
PARAMETER
MIN
Logical "0" Output Voltage
lOUT =-50mA liN'" 1 OmA
IOUT=-10mA I'N=1.0mA
logical "," Output Voltage
10UT=50mA
Power Supply leakage Current
(V t
_
vt
_
30
IIN=10mA
V-) = 30V
MAX
UNITS
V+-10
v+ - 0 7
v+ -05
V
V
v- + 15
V- + 20
V
V
100
p.A
TVP
10
lOUT = liN = 0 rnA
NegatlV9 Input Voltage Clamp
V- -12
liN = -lOrnA
V- - 08
V
20
35
ns
35
50
ns
30
60
ns
40
50
60
ns
40
70
120
ns
340
420
490
ns
"ON
CIN = 00022,uF
1d OFF (Note 21
RIN
trail (Note 21
ltall
=on
CL. = 0OO1pF
(Note 31
Pulse Width (50% to 50%) (Note 3)
'ttall
Pulse Width (50% to 60%) (Note 3)
15
ns
20
ns
110
Cl = 200 pF
ns
PositIVe Output Voltage SWmg
V-+-07V
V
NegatIVe Output Voltage Swing
V- +0 7V
V
Note 1: MinIMax limits apply over guaranteed operatmg temperature range of _55°C to +125°C for
MH0013 and O°C to +85°C for MH0013C, with V- = -20V and V+ = OV unless otherwISe speclf,ed.
TYPical values are for 2SoC.
'
Note 2: Parameter values apply for clock pulse width determined by input pulse wlctlth.
Note 3: Parameter values apply for Input pulse width greater than output dock pulse width
TABLE I, Typical Drive Capability of One Half MHOO13 at 70°C Ambient
'V3- V!)
VOLTS
26
20
16
TYPICAL RIN
.s
!l
_-
40
100
0
750
50
200
350
7
10
20
200
10
1600
100
400
700
I.
10
200
0
2300
400
1000
1700
TYPICAL CIN
16
2.
20
18
28
20
16
RISE TIME
LlMITns 2
PULSE WIDTH
MH.
26
20
OUTPUT DRIVE
CAPABILITY IN pF I
FREaUENCY
O'
600
10
4000
2800
.600
.300
-
•
14
"
34
4,
130
183
248
Note 1: Output load is the maximum load that can be dnven at 70°C without exceeding the package
rating under the gIVen conditions.
Note 2: The rise time given is the minimum that can be used without exceeding the peak transient
output current for the full rated output load.
circuit operation
Input current forced mto the base of 01 through
the coupling capacitor CI N causes 01 to be driven
into saturation, swinging the output to
V- + VeE (SAT) + VDIODE.
When the input current has decayed, or has been
switched, such that 01 turns off, 02 receives base
8·110
drive through R2, turning 02 on. This supplies
current to the load and the output swings positive
to V+ - VBE .
It may be noted that 01 always sWitches off
before 02 beginS to supply current; hence, high
Internal transient currents from V+ to V- cannot
occur.
3:
o
o
w
.......
3:
l:
o
o
l:
typical performance characteristics
FIGURE 1. Output Load vs Voltage
FIGURE 2. Transient Power vs Rep.
FIGURE 3. Transient Power vs Rep.
Rate vs CL
Rate vsCL
Swing
1
t, = 10 ns
30
j;
,
20
il'"
f
>- 400
"
10
il'"
500
f
1\ '\.\ ~
,""" ;::..... ::--.. .......
~
700
~
.! 600
~
1\\ ,\
,\ I..\'\.
~
700
.! 600
~
~
in
300
in
300
200
"'">-
200
z
100
1000
2000
FIGURE 4. Average Internal Power vs
Output Swing vs Duty Cycle
30
/
~
~,
20
~
10
30%
40%
V ..,..,- ~
\50%
/
I' ~ ~
I I I I
!
>'"
"i
500
~
I''''
300
100
200
300
-
FOR TYPICAL APPLICATION
DM7830/8830 DRIVER
~
CIN " 4300 pF
Cl '" 1000 pF
I-
-55 -35 -15 5
400
~3000
R1N
w
~ 2000
R,"
RIN
~
"
=on
10n
~
y
,;
V
V
./
/
ilV
V
I/, '/: P ..,- "R =9m
~~
=20n,....,.
=47f2
>-
~ 1000
....
~
25 45 65 85 105 125
100
AMBIENT TEMPERATURE rC)
AVERAGE POWER (mW)
DM8830 DRIVER
5V
RIN
u
;:
~~
400
==
z
I I I J.--
w
"
"u
lIt ~
Vee
TEST CIRCUIT (FIG. 8)
CIN '" 2200 pF
C, = 1000 of .............
~
~
//. :% ;...--
REPETITION RATE (MHd
FIGURE 5. Typical Clock Pulse Variations FIGURE 6. R'N vs C'N vs Pulse Width
vs Ambient Temperature
600
20%
1.0 2.0 3.0 4.0 5.0 6.0 7.0
REPETITION RATE (MH,)
MAXIMUM OUTPUT LOAD loF)
10%
o
100
1.0 2.0 3.0 4.0 50 6.0 7.0
3000
...w
500
400
::"
z
20 ns 30 ns 40 ns 50 ns 60 ns
>-
...
200
300
400
PULSE WIDTH (ns)
FIGURE 7. Package Power Derating
1.5
~
il'"
1.0
f
'"
['\.
.5
25
50
'""
75
100 125
150 175
AMBIENT TEMPERATURE rC)
ac test circuit
timing diagram
-
A InllutpU!sewrdth
>cfDCkpulsa
V
~
IN
Blnp UI PUIseWldlh. ft . .
5V
~
/\/190%
:,~:ockPUIse ~~t.lo," --l'~____V'_' ~
Clock pulse
output
l~O'"
lr~'"o,,"----
V3 -OV
Your
F"-=~-+----- V~ --16V
Figure 8
8-111
(J
...
C")
o
o
pulse width
:E
......
Maximum output pulse width is a function of the
input driver characteristics and the coupl ing
capacitance and resistance. After being turned on,
the input current must fall from its initial value
liN peak to below the input threshold current
liN min ~ V sE /Rl for the clock driver to turn
off. For example, referring to the test circuit of
Figure 8, the output pulse width, 50% to 50%, is
given by
~
...
C")
o
o
~
:E
+ RaC'N In liN peak
~ 400 ns.
liN min
For operation with the input pulse shorter than
the above maximum pulse width, the output pulse
width will be directly determined by the input
pulse width.
Typical maximum pulse width for various C, Nand
R'N values are given in Figure 6.
fan-out calculation
The drive capability of the MH0013 is a function
of system requirements, I.e., speed, ambient temperature, voltage swing, drive circuitry, and stray
wiring capacity.
The following equations cover the necessary calculations to enable the fan-out to be calculated for
any system condition. Some typical fan-outs for
conditions are given in Table 1.
Transient Current
The maximum peak output current of the MH0013
is given as 600 mAo Average transient current reqUired from the driver can be calculated from'
I
=
C L (V+ - V-I
TR
(1)
ThiS can give a maximum limit to the load.
Figure 1 shows maximum voltage sWing and
capacitive load for various rISe times.
1. Transient Output Power
The average transient power (PAC I diSSipated IS
equal to the energy needed to charge and discharge
the output capacitive load (C L I multiplied by the
frequency of operation (F).
.
PAC = C L X (V+ - V-)2 X F
(2)
Figures 2 and 3 show transient power for two different values of (V+ - V-I versus output lo~ and
frequency.
2. Internal Power
"0" State
Negligible «3 mW)
"1" State
(3)
8-112
Figure 4 gives various values of internal power
versus ou ptut voltage and duty cycle .
3. Input Power
The average Input power IS a functIOn of the Input
current and duty cycle Due to Input voltage
clamping, thiS power contribution IS small and can
therefore be neglected. At maximum duty cycle of
50%, at 25°C, the average Input power IS less than
10 mW per phase for R, NC, N controlled pulse
Widths. For pulse Widths much shorter than
R I N C, N, and maximum duty cycle of 50%, Input
power could be as high as 30 mW, since I, N peak IS
maintained for the full duration of the pulse
Width
4. Package Power Dissipation
Total Average Power
c
TranSient Output Power +
Internal Power + Input
Power
Typical Example CalculatIOn for One Half
MH0013C
How many MM506 shift registers can be driven by
an MH0013C driver at 1 MHz using a clock pulse
Width of 400 ns, rISe time 30-50 ns and 16 volts
amplitude over the temperature range O-lO°C}
Power Dissipation
From the graph of power dissipation versus temperature, Figure 1, it can be seen that an
MH0013C at 10°C can dissipate lW without a heat
sink, therefore, each half can diSSipate 500 mW.
Transient Peak Current Limitation
From Figure 1 (equation I); it can be seen that
at 16V and 30 ns, the maximum load that can be
driven IS limited to 1140 pF.
Average Internal Power
Figure 4 (equation 3) gives an average power of
102 mW at 16V 40% duty cycle.
Input power will be a maximum of 8 mW.
Transient Output Power
For one half of the MH0013C
500 mW c 102 mW + 8 mW
+ tranSient output power
390 mW = transient output power
Using Figure 2 (equation 2) at 16V, 1 MHz and
390 mW, each half of the MH0013C can drive a
1520 pF load. ThiS IS, however, In excess of the
load derived from the transient current limitation
(Figure I, equation 11. and so a maximum load
of 1140 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load IS 80 pF. Therefore the number
1140
of deVices driven IS "80 or 14 registers.
For nonsymmetrical clock Widths, drive capability
IS Improved.
s::::J:
o
o
Interface Circuits
N
C1I
......
MH0025/MH0025C two phase MOS clock driver
general description
features
The MH0025/MH0025C IS monolithic, low cost,
two phase MOS clock driver that is deSigned to be
driven by TTLlDTL line drivers or buffers such as
the DM932, DM8830, or DM7440. Two input
coupling capacitors are used to perform the level
shift from TTLlDTL to MOS logic levels. Optimum
performance In turn-off delay and fall time are
obtained when the output pulse is logically can·
trolled by the Input. However, output pulse widths
may be set by selection of the Input capacitors
eliminating the need for tight input pulse control.
•
s::::J:
o
o
8-lead TO-5 or 8-lead dual-In-Ilne package
N
C1I
• High Output Voltage SWings-up to 30V
n
• High Output Current Drive Capability-up to
1.5A
• Rep Rate· 1 0 MHz Into> 1000 pF
• Driven by DM932, DM8830, DM7440(SN7440)
• "Zero" QUiescent Power
connection diagrams
Metal Can Package
Dual-I n-Line Package
v'
Ne
8 N.C
1
INPUT A 2
7 OUTPUT A
v- 3
v·
6 V·
INPUT 8 4
Nute Pm 4 connected to case.
TOP VIEW
5 OUTPUTB
TOP VIEW
typical application
timing diagram
ac test circuit
Input waveform
PRR~05
Vpp
w
MHl
VOUTl
50V
._-clock pulse
Width
~
~
5V
OV
1,~tfsl0ns
Pulsew,dtb
A 10"s
I/'=OV
B 200llli
8 Inputpulsewtdth - £ ] 9 0 % - - - - - V , - , - 5 V
sets
10%
WIdthclock pulse
_ _ _ _ _ _ _ DV
Clock pulse
output
*Ql
IS a selec:ted
t"ON
10%
r-tdOfF
V3~OV
10%
high speed NPN wolltchlOg Irarl!!$10r
~----~--+------- V2
-16\1
8-113
(.)
In
N
o
a·pplications information
o
:::r:::
Circuit Operation
~
......
Input current forced into the base of 0, through the
coupling capacitor C'N causes 0, to be driven into
saturation, swinging the output to V- + VCE(sat) +
V O,ede'
In
N
o
o
:::r:::
When the input current has decayed, or has been
switched, such that 0, turns off, O2 receives base
drive through R2, turning O2 on. This supplies
current to the load and the output swings positive
to V· - V BE •
~
It may be noted that 0, must switch off before
O2 beginS to supply current, hence high internal
transients currents form V- to V· cannot occur.
, - -.....-ov·
J
t:1
t::
culatlons to enable the fan-out to be calculated
for any system condition.
Transient Current
The maximum peak output current of the MH0025
is given as 1.5A. Average transient current required
from the driver can be calculated from:
(1)
Typical rise times into 1000 pF load is 25 ns
For V· - V- = 20V, I = O.SA.
Transient Output Power
The average transient power (Pac) dissipated, is
equal to the energy needed to charge and discharge
the output capacitive load (Cd multiplied by the
frequency of operation (f).
PAC = CL
OUTPUT
INPUT
..."
(V· - V-)2
X
f
Internal Power
Neglig.ible «3 mW)
"1" State
(3)
Fan-Out Calculation
The drive capability of the MH0025 is a function
of system requirements, i.e. speed, ambient temperature, voltage swing, drive circuitry, and stray
wiring capacity.
The following equations cover the necessary cal-
(2)
For V· - V- = 20V, f = 1.0 MHz, CL = 1000 pF,
PAC = 400 mW.
"0" State
FIGURE 1. MHOO25 Schematic (One-Half Circuit!
X
= SO mW for V· - V- = 20V, DC = 20%
Package Power Dissipation
Total average power
interna I powe r
=
transient output power +
example calculation
How many MM506 shift registers can be driven by
an MHOO25CN drIVer at 1 MHz using a clock pulse
width of 200 ns, rISe time 30-50 ns and 16V amplitude over the temperature range 0-70°C?
Power DiSSipation:
At 70°C the MH0025CN can dissipate 630 mW
when soldered Into printed Circuit board.
Transient Peak Current limitation:
From equation (1). It can be seen that at 16V and
30 ns, the maximum load that can be driven is
limited to 2S00 pF.
Average Internal Power:
Equation (3). gives an average power of 50 mW at
16V and a 20% duty cycle.
S-I14
For one half of the MH0025C, 630 mW -;- 2 can be
dissipated.
315 mW = 50 mW + transient output power
265 mW = transient output power
Using equation (2) at 16V, 1 MHz and 250 mW,
each half of the MH0025CN can drive a 975 pF
load. This IS, less than the load imposed by the
transient current limitation of equation (1) and
so a maximum load of 975 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load is SO pF. Therefore the number
975
of deVices driven IS 00 or 12 registers.
3:
o
o
::I:
absolute maximum ratings
(v+ - V-I Voltage Differential
Input Current
Peak Output Current
Power Dissipation
Storage Temperature
Operating Temperature MH0025
MH0025C
Lead Temperature (Soldering, 10 sec)
30V
100mA
1.5A
See Curves
-65°C to +150°C
_55°C to +125°C
O°C to +85°C
300°C
electrical characteristics
PARAMETER
N
U1
.......
3:
::I:
o
o
N
U1
o
(Note 1) See test circuit.
CONDITIONS
TYP
MAX
UNITS
15
30
ns
25
50
ns
30
60
ns
60
90
120
ns
100
150
250
ns
500
ns
V+ - 1.0
V+ - 0 7V
V
MIN
..,
T dON
Tnse
C'N ~ .001 flF
T doFF (Note 2)
R'N ~
T lall (Note 21
CL
~
on
.001 flF
T lall (Note 3)
P.W. (50% to 50%) (Note 3)
Y'N ~ OV, lOUT ~ -1 mA
Positive Output Voltage SWing
V- + 1.5V
V- + 0.7V
Negative Output Voltage Swing liN ~ 10 mA, IOUT~ 1 mA
V
Note 1. MiniMax limits apply across the guaranteed operating temperature range of _55°C to +125°C
for MH0025 and aOc to 85°C for MH0025C. TYPical values are for +25°C
Note 2. Parameter values apply for clock pulse width determined by Input pulse width
Note 3. Parameter values apply for Input pulse width greater than output clock pulse width
typical performance
Package Power Derating
~
Transient Power vs Rep. Rate
14 -
MH0025CN SOLDERED INTO PC
i=
12
BOARD WITH 8 Cu CONDUCTORS
20Z, 03 IN WIDE
~
'0
'"
0.8
z
0
:.
c
~
06
"'"
"'"
.5
~
- "" l\.
....
"
"
'::t
1i o.
"x
~
"-
0.2
'60
300
Cl -lOOOP;1 CL "1500pf
C"=lOIlOpF
/'/
4+
I /
200
/
0
SO
2S
75
'DO
TEMPERATURE rCI
'"
~
S
, 0
~
~
3200
~2800
;
2400
~ 2000
....
MHO~25CN
K
1\
'\
~ 1600
j
1/
g
800
.00
"'-
=lOVT.=l;C
""
...... t--..
MIlOOl5CN~-~1.VT'=lOc7
V _V-'16V T.=JOC
.... F
MHOOl~
0
02 04 06 08 10 12 14 16 18 20
l
< (PMAX ) 11k) -
(V+ - V~)2 (DC)
(f) (1k) (V+ _ V-)2
<
V
/
/y
X
l/v·)",dv_
J?'
0
20
'0
30
40
50
60
PAC'" (v+ - V-)2f CL
(V' - V-I' (OCI
Poc"'--'k--
70 8S
Output P .W. Controlled by CIN
1100
OUTPUTPUlSfWIOTHVS
INPUT PULSES
c,~
FOfllONG
FOflINPUTPUlSE<6§.RoC,~ln~
900
!
....
'"
~
IM'~
OUTPUTPUlSEW1DTH-INPUTPUlSEWIDn
HU~9IIn.
1/
700
1-500
I>-
~
V
300
'00
D~32~RlVlR rD~j
...
DRIVER
......
50QPUtlUP
~
200
600
'ODD 1400 '800
2200
CIN (pF)
FREOUENCY (MHz)
C
/
DUTY CYCLE (%)
iii
......
20
/
PULSE REPETITION RATE (MHzl
0
.......
t-...: -......
0
.,
MHOOZ5CV
.'-
5 1200
lOVT.=1f>C
'0
{.?.b
V /
80
60
20
'5
1
v -v
'00
16V
MaXimum Load Capacitance
1 1
~c
II / ~
./
II 'J /
r!J 'l ./ &
V
/
0
II. ~ ./ ~ .;:::::; 'c'L =200pf
~ ~P"
0
1/
.5 120
Cl=JSOPF
100125 '50
OC=1111>
""
X
V· - V-"2OV/
140
CL=750rF
V' - V-
0
-25
DC Power (POC) vs Duty Cycle
'00
-- -MH0025H &MH,0025CH STill AIR
(I pk) It,)
v+ _ V-
IMAX
~
Peak currentdehvered bV Driver
IMIIII==~-I!.!
Rl
,.
8-115
(,)
U)
N
Interface Circuits
o
o
::I:
:?!
.......
U)
N
o
o
::I:
MH0026/MH0026C 5 MHz two phase MOS clock driver
general description
:?!
The MH0026/MH0026C IS a low cost monolithic
high speed two phase MOS clock driver and interface circult_ Unique circuit design along with
advanced processing provide both very high speed
operation and the ability to drive large capacitive
loads_ The deVice accepts standard TTL/DTL outputs and converts them to MOS logic levels_ I t may
be drIVen from standard 54174 series gates and
flip-flops or from drivers such as the DM8830 or
DM7440_ The MH0026 is intended for applications
In which the output pulse width is logically controlled: I_e_, the output pulse width is equal to the
Input pulse width_
•
•
The MH0026 is intended to fulfill a wide variety of
MOS interface requirements_ As a MOS clock driver
for long sll icon gate sh ift registers, a single dev Ice
can drive over 10k bits at 5 MHz_ Six deVices provide input address and precharge drive for a 8k by
16bitMMll03 RAM memory system_ Information
on the correct usage of the MH0026 in these as well
as other systems is included in the application section starting on page 5_ A thorough understanding
of its usage will insure optimum performance of the
device_
features
•
•
•
•
•
Low power consumption in MOS "0" state2 mW
Drives to OAV of GND for RAM address drive
Fast rise and fall tlmes-20 ns with 1000 pF load
High output sWlng-20V
High output current drive-±1.5 amps
TTL/DTL compatible Inputs
High rep rate-5 to 10 MHz depending on load
The device IS available In 8-lead TO-5, one watt
copper lead frame 8-pln mini-DIP, and one and a
half watt TO-8 packages_
schematic diagram
connection diagrams
11/2 of CIfCUII Shown)
12-Lead TO-S
v'
EXTERNAL
C"
.B
MHOO26H/MHOO26CH
0-1 hNPUT
a·Lead Dual-I n-Line Package
OUTPUT
"B'"
INPUT A 2
V·
1 OUTPUT A
6 V'
3
INPUTB "
5 OUTPUTS
TOP VIEW
MHOO26CN
••
S-Lead TO-5
v-
V"
Noto P,n4eonnectedtoCl"
T(JPVIEIo\I
MH0026G/MH0026CG
8-116
s:
:I:
absolute maximum ratings
v+ -V- Differential Voltage
Input Current
Input Voltage (V ,N - V-)
Peak Output Current
Power Dissipation
Operating Temperature Range
MH0026
MH0026C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
dc electrical characteristics
..
----
o
o
22V
100mA
5.5V
1.5A
See curves
_55°C to +125°C
O°C to 85°C
-65°C to +150°C
300°C
N
en
.......
s:
:I:
o
o
N
en
n
(Notes 1 & 2)
LIMITS
PARAMETER
CONDITIONS
Logic "1" Input Voltage
V OUT = V- + 1.0V
Logic "1" Input Current
V ,N - V- = 2.5V, V OUT = If"' + 1.0V
2.5
Logic "0" Input Voltage
V OUT = V+ - 1.0V
LogiC "0" Input Current
V ,N - V- = OV, V OUT = V+ - 1.0V
Logic "0" Output Voltage
TYP
MIN
MAX
V
1.5
10
0.4
-0.005
V
-10
J1.A
V+ = +5.0V, V- = -12.0V
4.0
V
V ,N - V- = OAV
Logic "1" Output Voltage
V+ = +5.0V, V- = -12.0V
V ,N = -9.5V
Logic "1" Output Voltage
V ,N - V- = 2.5V
V- + 0.5
"ON" Supply Current
V+ - V- = 20V, V ,N - V- = 2.5V
"OFF" Supply Current
V+ - V- = 20V, V ,N - V- = O.OV
ac electrical characteristics
V+ - 1.0
4.3
Logic "0" Output Voltage
V+ - 0.7
-11.5
5.0
Turn·Off Delay (tOFF)
5.0
V
-11.0
V
V- + 1.0
V
30
40
mA
10
100
J1.A
12
ns
15
ns
(Notes 1 & 2,AC test CIrCUit, TA
Turn·On Delay (tON)
Falltime (tf) - Note 3
mA
15
0.6
V'N=-11.6
Rise time (t,) - Note 3
UNITS
= 25°C)
7.5
12
V+ - V- = 17V, CL = 250 pF
12
V+ - V- = 17V, CL = 500 pF
15
18
CL = 1000 pF
20
35
V+ - V- = 17V, CL = 250 pF
10
V+ - V- = 17V, CL = 500 pF
12
16
ns
CL = 1000 pF
17
25
ns
ns
ns
ns
ns
Note 1: These specifications apply for V+ - v10V to 20V, CL = 1000 pF, over the temperature range -55°C to +125°C
for the MH0026 and O°C to +85°C for the MH0026C, unless otherWise specified.
:0:
Note 2: All typical values for the T A = 25°C.
Note 3: Rise and fall time are given for MOS logiC levels,
I.e.,
rise time
IS
transistion from logic "0" to logiC "1" which
IS
voltage
fall. See waveforms on the follOWing pages.
ac test circuit
switching time
waveforms
10%
INPUT -----J
I
8-117
o
CD
N
typical performance characteristics
o
o
l:
DC Power (PDCI vs
,:E
TO-S & DIP Power Ratings
Duty Cycle
400
MH0026G AND MH0026CG IN
CD
N
1.0
o
o
~
:E
Q
l:
Package Power Rating
TO~8
3.0
~iii
c:
~
~
z
0.8
0
;::
:1:
iii
0.6
Ci
a:
0.4
~
0.2
25
50
75
100
125
-
2.0
320
TYPE 215-1.9 DR EOUIV.)
280
lO
.5 240
. . . . " 1/
1.5
I"- .......... ~
1.0
't
MH0026G AND...._I=>MHOi26CG STIlIL AIR
0.5
150
25
AMBIENT TEMPERATURE rC)
360
r- ~~I!i ~I:K~~T:E~~:~~DY
-
2.5
50
75
a:
~
~
~
"
10
150
Y
V
V
V
l>"
/. V V
120
AMBIENT TEMPERATURE ('C)
./
./
160
80
125
V
V' -V-=20V_
V' - V-= 17V '-,
V' - V-= 12~)(
200
40
100
TA = 25°C
Cl. = 0
(V- _ V-I'
Poc=~(DC)
20
30
40
50
60
70
80
DUTY CYCLE (%)
Transient Power (PAC) vs
Frequency
900
800
!i"
700
a:
600
.5
...~
iil
iii
~
I
/
I
V
J
lL
...
500pF
i
~
C, 200 pt,.-f.-'
~
~;....-
~
L1 L
1.0
2.0
30
DUTY CYCLE = 20%
f= 1 MHz
CL = 0
ao
7.5
70
65
6.0
4.0
5.0
.
;::
~
!2 OUTPUT
INPUT
INPUT
-12V
Transistor Coupled MOS Clock Driver
TTL INPUTS
{O---1>-,
1
JOSHIFT
IIEGISTERS
'><>-+--
-12V
Logically Controlled AC Coupled Clock Driver
.----....- -....- - - - - -....- -....- -....-----0 •••
TTL CLOCK
Jl
INPUT O-....- - : ! . j
210
TO ADDITIONAL
} SHIFT REGISTERS
~--:::==t==~-<>-12V
f'---I
~
•
b
CLOCK INPUT -ZfG
ONE SHOT OUTPUT - ADJPULSE WIDTH
PHAS£ ONE OUTPUT
PHASE TWO OUTPUT
8-120
3:
o
o
::I:
application information
1.0 Introduction
The MH0026 is capable of delivering 30 watts
peak power (1.5 amps at 20V needed to rapidly
charge large capacitative loads) while its package is
limited to the watt range. This section describes
the operation of the circuit and how to obtain
optimum system performance. If additional design
information is required, please contact your local
National field application engineer.
N
a simplified diagram, D, (Figure 3) provides 0.7V
dead zone so that 0 3 is turned ON for a rising
input pulse and O 2 OFF prior to a, turning ON a
few nanoseconds later. D2 prevents zenerlng of the
emitter·base junction of O 2 and provides an initial
discharge path for the load via 0 3 , During a falling
input, the stored charge in 0 3 IS used beneficially
to keep 0 3 ON thus preventing O2 from conduct·
ing until a, is OFF. a, stored charge is quickly
discharged by means of common·base transistor
04,
en
.......
3:
o
::I:
o
N
en
(")
2.0 Theory of Operation
Conventional MOS clock drivers like the MH0013
and similar deVices have relied on the circuit
configuration In Figure 1. The AC coupling of an
input pulse allows the device to work over a wide
range of supplies while the output pulse width
may be controlled by the time constant - R, X C,.
The complete circuit of the MH0026 (see sche·
matic on page 1) basi<.ally makes Darllngtons out
of each of the transistors in Figure 3.
. - - -....<>v'
,--",,-0 v'
EXTERNAL
1N0-/C1~
"'MlH~OUT
C1
EXTERNAL
02
1N0-/~
L-....-
....ov-
FIGURE 1. Conventional MOS Clock Drive
D2 provides 0.7V of dead-zone thus preventing a,
and O 2 from conducting at the same time. In
order to drive large capacitive loads, a, and O 2
are large geometry devices but Cob now limits
useful output rise time. A high voltage TTL output
stage (Figure 2) could be used; however, during
switching until the stored charge IS removed from
0" both output devices conduct at the same time.
This is familiar in TTL with supply line glitches in
the order of 60 to 100 mAo A clock driver built
this way would introduce 1.5 amp spikes into the
supply lines.
""",-",,-0 v'
EXTERNAL
C1
OUT
100-/ ~
D1
L-...._ _........-ov-
FIGURE 2.
OUT
FIGURE 3. Simplified MH0026
When the output of the TTL input element (not
shown) goes to the logic "1" state, current IS
supplied through C 'N to the base of a, and O 2
turning them ON, and 0 3 and 0 4 OFF when the
input voltages reaches 0.7V. Initial discharge of
the load as well as E·B protection for 0 3 and 0.
are provided by D, and D2 . When the input
voltage reaches about 1.5V, G.,; and 0 7 begin to
conduct and the load is rapidly discharged by 0 7 ,
As the input goes low, the input side of C, N goes
negative with respect to V- causing 0 8 and 0 9 to
conduct momentarily to assure rapid turn·off of
O2 and 0 7 respectively. When 0, and O 2 turn
OFF, Darlington connected 0 3 and Q4 rapidly
charge the load toward V+ volts. R6 assures that
the output will reach to within one VB E of the
V+ supply.
The real secret of the device's performance is
proper selection of transistor geometries and resistor values so that Q4 and Q 7 do not conduct at
the same time while minimizing delay from input
to output.
3.0 Power Dissipation Considerations
Alternate MOS Clock Drive
Unique circuit design and advanced semiconductor
processing overcome these clasic problems allow·
ing the high volume manufacture of a device, the
MH0026, that delivers 1.5A peak output currents
with 20ns rise and fall times Into 1000pF loads. In
There are four considerations in determining
power dissipations.
1. Average DC power
2. Average AC power
3. Package and heat sink selection
4. Remember-2 drivers per package
8·121
(J
cD
N
application information (cont.)
o
o
The total average power dissipated by the MH0026
is the sum of the DC power and AC transient
power. The total must be less than given package
power ratings.
::I:
:!!
........
cD
N
3.2 AC Transient Power (per driver)
o
o
::I:
:!!
Thus for RAM address line applications, package
type and heat sink technique will limit drive
capability rather than AC power.
AC Transient power is given by:
Since the device dissipates only 2mW with output
voltage high (MaS logic "0"), the dominating
factor in average DC power is duty cycle or the
percent of time in output voltage low state (MaS
logic "1"). Percent of total power contributed by
Poc is usually neglible in shift register applications
where duty cycle is less than 25%. Poc dominates
in RAM address line driver applications where
duty cycle can exceed 50%.
where: f = frequency of operation
C L = Load capacitance (including all
strays and wiring)
Example 3: (V+
= +5V, V- = -12V)
PAC = 17 X 17 X f(MHz) X 106 X
3.1 DC Power (per driver)
CL (nF) X 10- 9
DC Power is given by:
PAC = 290mW per MHz per 1000pF
ON time
)
(
OFF time-ON time
or Poc = (Output Low Power) X (Duty Cycle)
where: IS(LOW) = Is
Example I: (V+
@
= +5V,
(V+ - V-I
V-
= -12V)
a) Duty cycle = 25%, therefore
Poc = 17V X 40mA X 17/20 X 25%
Po c = 145mW worst·case, each side
b) Duty cycle = 5%
Poc = 21mW
c) See graph on page 3
The above illustrates that for shift register applica·
tions, the minimum clock width allowable for the
given type of shift register should be used in order
to drive the largest number of registers per clock
driver.
= GND):
a) Duty cycle = 50%
Po c = 290mW worst·case
Poc = 218mW typically
b) Duty cycle = 100%
Poc = 580mW
8·122
3.3 Package Selection
Power ratings are based on a maximum junction
rating of 175°C. The following guidelines are
suggested for package selection. Graphs on page 3
illustrate derating for various operating tempera,
tures.
3.31 TO-5 ("H") Package: Rated at 600mW still
air (derate at 4.0mW/"C above 25°C) and 900mW
with clip on heat sink (derate at 6.0mW/"C above
25°C). This popular hermetic package is recom·
mended for small systems. Low cost (about 10¢)
clip·on·heat sink increases driving capability by
50%.
Poc = 109mW typically
Example 2: (V+ = +17V, V-
Thus at 5MHz, a 1000pF load will cause any driver
to dissipate one and one half watts. For long shift
registers, a driver with the highest package power
rating will drive the largest number of bits for the
lowest cost per bit.
3.32 8·Pin ("N") Molded Mini·DIP: Rated at
600mW still air (derate at 4.0mW/"C above 25°C)
and 1.0 watt soldered to PC board (derate at
6.6mW/"C). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly
where automatic insertion is used. (Please note for
prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down.)
3.33 TO-8 ("G") Package: Rated at 1.5 watts
still air (derate at 10mW/oC above 25°C) and 2.3
watts with clip on heat sink (Wakefield type
215-1.9 or equivalent-derate at 15mW/"C).
Selected for its power handling capability and
moderate cost, this hermetic package will drive
very large systems at the lowest cost per bit.
~
:::I:
o
o
application information (cont.)
3.4 Summary-Package Power Considerations
Dc
In
pFI ~
n10-
Time in output low
In
+ Time In
output high state
The MH0026 is intended for applications in which
the input pulse width sets the output pulse width;
i.e., the output pulse width is logically controlled
by the input pulse. The output pulse width is given
by:
3
X
pFI ~ 5X 10-3 X
Two external Input coupling capacitors are reqUired to perform the level translation between
TTLlDTL and MOS logic levels. Selection of the
capacitor size is determined by the desired output
pulse width. Minimum delay and optimum per·
formance is attained when the voltage at the input
of the MH0026 discharges to just above the
devices threshold (about 1.5V). I f the input IS
allowed to discharge below the threshold, to F F
and tl Will be degraded. The graph on page 3
shows optimum values for C'N vs desired output
pulse width. The value for C 'N may be roughly
pred Icted by:
Pm,,(mWI X 500 - V S ' X Dc X 103
V S ' X 500 X f(MHzl
Where: n = number of drivers per pkg. (2 for
the MH0026)
Pm axl mW) (T A' pkg) = Package power
rating in milliwatts for given package,
heat sink, and max, ambient temperature (See graphs)
Req
.......
~
4.0 Pulse Width Control
(V'" - V I' X Req X f(MHzl
C L (ma~
0)
Table I illustrates MH0026 drive capability under
various system conditions.
Pm,,(mW) (T A,pkgl X Req - (V+ - V-I' X (Dcl X 103
or:
N
Duty Cycle =
Time in output low state
The maximum capacitative load that the MH0026
can drive is thus determined by package type, heat
sink technique, ambient temperature, AC power
(which is proportional to frequency and capacitive
load) and DC power (which is principally determined by duty cycle). Combining equations previously given, the following formula is valid for
any clock driver with negligible input power and
negligible power in output high state:
C L (max
~
= equivalent internal resistance
C'N = (2 X 10-3 ) (PW)OUT
(V+ - V-)/I SI Low) = 500 ohms (worst
case over temperature for the MH0026 or
660 ohms typically)
Req =
For an output pulse width of 500ns, the optimum
value for C, N is:
Vs = (V+ - V-) = total supply voltage across
device
C, N
=
(2 X 10-3 )(500 X 10-9
) 2;
1000pF
TAB LE 1. Worst Case Maximum Drive Capability for .MH0026*
TO-SWITH
HEAT SINK
PACKAGE TYPE
TO-S
FREE AIR
MINI· DIP
SOLDERED DOWN
TO-5 AND MINI·DIP
FREE AIR
Max.
Max.
Operating
tS
Temp.
Frequency j
60"C
85°C
60°C
85°C
60°C
85°C
60°C
85°C
4
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.5k
500kHz
10%
6.5k
5.1k
4.1k
3.2k
2.7k
2k
1.5k
lMHz
20%
2.9k
2.2k
1.8k
14k
1.1k
5.8k
1.1k
840
600
430
2MHz
25%
850
650
550
400
280
190
5MHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
-
*Note
l.4k
1.lk
Values In pF and assume both Sides In use as non-overlaplng 2 phase dnver, each Side operating
at same frequency and duty cycle With (V+ - V-) '" 17V For loads greater than 1200 pF,
me and fall times will be limited by output current, see Section 50
8-123
:::I:
o
o
N
0)
(")
(.)
CD
N
o
o
:::I:
~
.......
CD
N
o
o
application information (cont.)
5.0 Rise & Fall Time Considerations(Note 3)
The MH0026's peak output current is limited to
1.5A. The peak current limitation restricts the
maximum load capacitance which the device is
capable of driving and is given by:
:::I:
~
I
;cLaf" 1.5A
7.0 Clock Line Cross Talk
The rise time, t r, for various loads may be
predicted by:
tr; (LW) (250 X 10-12 + C L )
Where: l:N; The change in voltage across CL
~V+ -VCL ; The load capacitance
For V+ - V-; 20V, C L ; 1000pF, tr is:
tr ~ (20V) (250 X 10- 12 + 10-12 )
; 25ns
For small values of CL , equation above predicts
optimistiC values for t r. The graph on page 3
shows typical rise times for various load capaci·
tances.
The output fall time (see Graph) may be predicted
by:
~ ~ 2.2R(C s +~)
hFE
+1
6.0 Clock Overshoot
The output waveform of the MH0026 can over·
shoot. The overshoot is due to finite inductance of
the clock lines. It occurs on the negative going
edge when 0 7 saturates, and on the positive edge
when 0 3 turns OFF as the output goes through
V+ - Vb.' The problem can be eliminated by
placing a small series resistor in the ouput of the
MH0026. The critical valve for R,;2y'L/CQ where
L is the self·inductance of the clock line. In
8·124
practice, determination of a value for L is rather
difficult. However,R, IS readily determined emper·
ically, and values typically range between 10 and
51 ohms. R, does reduce rise and fall times as
given by:
At the system level,voltage spikes from 1 may be
transmitted to 1/)2 (and vice·versa) during the
transition of 1 to MOS logic "1". The spike is
due to mutual capacitance between clock lines and
is, in general, aggravated by long clock lines when
numerous registers are being driven. Transistors
0 3 and
on the 2 side of the MH0026 are
essentially "OFF" when 2 is in the MOS logic
"0" state since only micro·amperes are drawn
from the device. When the spike is coupled to 2,
the output has to drop at least 2 VB E before 0 3
and 0 4 come on and pull the output back to V+.
A simple method for eliminating or minimizing
this effect is to add bleed resistors between the
MH0026 outputs and ground causing a current of
a few milliamps to flow in 0 4 , When a spike is
coupled to the clock line
is already "ON" with
a finite h fe • The spike is quickly clamped, by 0 4 ,
Values for R depend on layout and the number of
registers being driven and vary typically between
2k and 10k ohms.
a.
a.
8.0 Power Supply Oecoupling
Power supply decoupling is a widespread and
accepted practice. Oecol1pling of V+ to V- supply
lines with at least 0.1 /IF noninductlve capacitors
as close as possible to each MH0026 is strongly
recommended. This decoupling is necessary
because otherwise 1.5 ampere currents flow during
logic transition in order to rapidly charge clock
lines.
Interface Circuits
s:J:
CO
CO
o
CO
MH8808 dual high speed MOS clock driver
general description
features
The MH8808 is a high speed dual MOS clock
driver intended to drive the two phases of a
memory array of 500 pF per phase at rates up to
4 MHz. The design includes output current limit·
ing for controlled rISe and fall times, and thermal
shutdown which protects the chip against exces·
sive power dissipation or accidental output shorts.
Two DTLITTL compatible status outputs monitor
clock outputs and provide a corresponding TTL
logic level for status indication. Both direct and
internally damped outputs are available for each
phase to suit the particular application. It is ideally
suited for driving MM5262 2k RAMs.
•
High Speed: 18 ns typ delay and 20 ns typ rise
and fall times with 500 pF load
•
Current limited outputs ±450 mA typ
•
Direct and damped outputs available
• Thermal shutdown protection
• TTL compatible status outputs
•
1W dissipation capability at 25°C T A
•
16 pin cavity dual·in·llne package
• Output high level clamped to +5V
connection diagram
DualRln~Line
voo
DAMPED
Vss
OUT
16
'~O
15
Package
DAMPED
OUT
OUT
14
12
11
OUT
NC
10
NOT CoNNECTTo THIS PIN.
TOP VIEW
8·125
co
o
CO
CO
::I:
absolute maximum ratings
:!
+7V
26V
lW
Vss
Vss - Voo
Total Power DISSipation (Note 1)
O°C to +70°C
Operatmg Temperature Range
electrical characteristics
The following apply for V BS
=
+7V, Vss "" +5V, V DD == -15V, TA
PARAMETER
=
25°C unless otherwise stated
CONDITIONS
I nput Current
Y'N ° -9V (Note 21
Output Low Voltage
lOUT = +1 rnA, VIN
0::
-lOY
MIN
MAX
UNITS
10
mA
-14
V
(Note 21
Output High Voltage
lOUT = -1 mA, VIN = -14V
45
Status" 1" Voltage
lOUT ° -250)./A, Y'N ° -14V
3
Status "0" Voltage
lOUT ° 20 mA, Y'N ° -10V
(Note 21
Output Leakage Current
V BB ° +8.5V, Vss ° 5V
Vooo-175V,VOUTo+85V
VIN = open
53
V
05
100
IBB
V ,N o-115V
Vss ° +6 5V, Voo ° -17 5V
V BB ° +8 5V (Note 21
Iss
V'N~-115V
V
)./A
S1
4
Damping Resistor
V
32
mA
Vss ° +6 5V, Voo ° -17 5V
V BB ° +8 5V (Note 21
23
mA
100
V ,N o-115V
Vss ° +6 5V, Voo ° -17 5V
V BB ° +8 5V (Note 21
-55
mA
Output Rise Time
C L o 500pF
26
ns
Output Fall Time
C L ° 500 pF
26
ns
Delay to Negatlve·Gomg Output
C L ° 500 pF
7
22
ns
Delay to Positive-Going Output
C L ° 500 pF
10
25
ns
Note l' Maximum Junction temperature
IS
110"C For operation above 25"C derate at 85°C/W 0JA for stili air
Note 2. Test only one Input high (more POSitive) at a time
8-126
Future Products
DM5446A/DM7446A(SN5446A/SN7446A),
DM5447A/DM7447A{SN5447A/SN7447A),
DM 5448/DM7448 (SN5448/SN7448)
BCD to 7-segment decoder/drivers
general description
This versatile series of 7-segment display drivers
fulfills a wide variety of requirements for most
active high (common cathode) and active low
(common anode) Light Emitting Diodes (LED)
or lamp displays_ Each device fully decodes a
4-bit BCD input into a number from 0 through 9
in the standard 7-segment display format, and
BCD numbers above 9 Into unique patterns that
verify operatlon_ All circuits operate off of a
Single 5_0V supply_
The DM5446A/DM7446A has active-low, opencollector outputs that Will drive segments requiring
, up to 40 mA of current. The outputs are capable
of withstanding 30V at a maximum leakage current
of 2501lA. ThiS configuration IS particularly well
sUited for common anode LED displays or higher
voltage lamp displays. The high sink current
capability also allows this circuit to be used in
the multiplex or nonmultiplex mode ,of display
drlve_ In addition, the device may be used to
drive logic circuits since ItS normalized fanout
is 25.
The DM5447A/DM7447A has the same output
characteristics as the DM5446A/DM7446A except
that the outputs Withstand 15V at a maximum
leakage current of 2501lA. Si nce its output configuration is the same as the DM5446A/DM7446A
ItS applications Will also be the same, the only
restriction is that a lower voltage type display be
used because of the reduced output voltage limit
of 15V.
The DM5448/DM7448 has active-high, passivepull up outputs With a fanout of 4. Typical source
current is 2.0 mA at an output voltage of 0.85V.
The sink capability is 6.4 mA at a maximum
drop of 0.4V. It IS normally used to drive logic
circuits, operate high-voltage loads such as electro·
luminescent displays through buffer transistors or
SCR switches, and in low current common cathode
Non-Multiplex LED applications.
features
•
•
Lamp-test input
Leading/trailing zero suppression (RBI and
RBO)
• Blanking input that may be used to modulate
lamp intensity or inhibit output
• TTL and DTL compatible
• Input clamping diodes
connection diagrams
TOP VIEW
DM54481DM7448
TOP VIEW
DM5446A1DM7446A
DM5447AlDM7447 A
9-1
DM5485/DM7485{SN5485/SN7485)
4-blt magnitude comparator
general description
The DM5485/DM7485 performs magnitude comparison of straight binary and BCD (8421) codes.
Three fully decoded decisions on two 4-bit words
(A & B) are made and brought to three outputs.
•
•
connection diagram
This device is fully expandable by use of cascading
inputs. When expanded the total comparison time
is a function of word length and is two gate delays
("" 12 ns) for each four bit section added to the
basic device delay.
It)
co
"It
"'~"
Easily expandable through high speed cascading
inputs
Typical power
275 mW
features
c
•
.......
It)
co
Greater than, less than and equal to in one
package
truth table
"It
It)
~
COMPARING
INPUTS
c
CASCADING
INPUTS
OUTPUTS
A-B
A3, B3
A2,B2
Al,Bl
AO,BO
A>B
AB
AB3
A3B1
A1 <61
A1- 61
A1' B1
A1- 61
A1' B1
A1-B1
x
x
x
x
x
x
x
x
L
L
L
H
A2>B2
A2< B2
A2' B2
A2- B2
A2- B2
A2- B2
A2 - 62
A2- B2
A2' B2
X
AO>BO
AO< 60
AO' BO
AO' BO
AO'BO
X
L
H
L
H
L
L
L
H
L
H
L
H
L
L
H
L
L
L
L
L
L
L
NOTE: H '" high level, L = low level, X '" Irrelevant
DM54123/DM74123(SN54123/SN74123)
TTl/monostable multivibrator
general description
features
The DM54123/DM74123 is a dual retriggerable,
resettable monostable multivibrator providing an
output pulse whose duration and accuracy is a
function of external timing components. Its inputs
and outputs are standard TTL and compatible with
all 5400 and 7400 products.
•
•
•
•
•
There are two inputs per function, one active LOW
and one active HIGH. This permits triggenng on
either the leading (positive going) or trailing (negative going) edge. Triggering is independent of Input
transition time or pulse width. An input cycle
time shorter than the output R'C cycle time will
retrigger the DM54123 and result in a continuous
output.
Retriggering may be inhibited by tying the Q output to the active LOW trigger mput or the Q
output to the active HIGH input.
The true output may be forced LOW during any
phase of input or output timing by connecting a
logic LOW level to the reset input.
9-2
•
Retriggerable
0% to 100% duty cycle
TTL compatible inputs and outputs
Triggers on leading or trailing edge
Complementary outputs
Compensated for temperature and power supply
variations
21 ns (typ.)
High speed trigger to Q
connection diagram
DM541411DM74141 (SN541411SN74141)
BCD to decimal decoder/driver
general description
The DM54141/DM74141 is a second-generation
BCD-to-decimal decoder designed specifically to
drive cold cathode indicator tubes_ This decoder
demonstrates an improved capability to minimize
switching transients in order to maintain a stable
display_
Full decoding is provided for all possible input
states_ For binary inputs 10 through 15, all the outputs are off_ Therefore the DM54141/DM74141,
combined with a minimum of external circuitry,
can use these invalid codes in blanking I'eadingand/or trailing-edge zeros in a display as shown in
the typical application data. The ten high-performance NPN output transistors have a maximum
reverse current of 50llA at 55V_
Low-forward-impedance diodes are also provided
for each input to clamp negative-voltage transitions
in order to minimize transmission-line effects.
Power dissipation is typically 55 mW, which is
about one-half the power requirement of earlier
designs_
features
•
•
•
•
•
Drives cold cathode numeric indicator tubes
directly
Low leakage current at 55V (50IlA max.)
Low power dissipation of 55 mW (typ_)
Fully decoded inputs ensure all outputs off for
invalid codes
Input clamp diodes for minimizing transmission
line effects
connection diagram
9-3
(I)
II)
.;:
DM54160/DM74160(SN54160/SN74160)
decade counter with asynchronous clear
DM541611DM74161 (SN541611SN74161)
binary counter with asynchronous clear
DM54162/DM74162(SN54162/SN74162)
decade counter with synchronous clear
DM54163/DM74163(SN54163/SN74163)
binary counter with synchronous clear
II)
t/)
o
...'l1li'
CD
"""
::E
Q
.......
o
...
CD
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general description
Q
These synchronous, presettable counters feature
an internal carry look·ahead for application in
high-speed counting schemes_ The DM54160/
DM74160 and DM54162/DM74162 are decade
counters and the DM54161/DM74161 and
DM54163/DM74163 are 4-bit binary counters_
enable the carry out_ The earry output is a
positive pulse with a duration approximately equal
to the positive portion of QA and can be used to
enable successive cascaded stages. High to low
level transitions at the enable P or T inputs
should occur only when the clock is high.
A low level at the load input disables counting
and causes the outputs to agree wi th the data
input after the next positive clock edge. The
clear function for the DM54162/DM74162 and
DM54163/DM74163 is synchronous and a low
level at the clear input sets all four outputs low
after the next positive clock edge. The clear
function for the DM54160/DM74160 and
DM54161/DM74161 is asynchronous and a low
level at the clear input sets all four outputs low
regardless of the state of the clock.
features
• Internal look-ahead for fast counting schemes
• Carry output for n-bit cascading
• Synchronous counting
• Synchronously programmable
• Load control line
• Diode-clamped inputs
Counting is enabled when both count enable
inputs are high. Input T is fed forward to also
• Typical max input clock frequency
connection diagram
V~6
115 114 113 112 111 110
g
I I II I I
ri:::
I Lei
11
12
n.
~TP;S
T' °i"
13
14
oj" oj"
15
TDPVIEW
9-4
no
16
OT ~
i
11 G~8D
35MHz
o
3:
DM54170/DM74170(SN54170/SN74170) 4-by-4 register file
U'I
........
~
general description
o
This 16-bit Register File is organized as four
4-bit words. Separate Read Select and Write Select
inputs allow simultaneous reading and writing
from different locations.
.......
o
the output, a high·level is applied at the data input
for that particular bit location. The latch inputs
are arranged so that new data will be accepted
only if both internal address gate inputs are high.
When this condition exists, data at the D input is
transferred to the latch output. When the write
enable input, Gw , is high, the data inputs are
inhibited and their levels can cause no change in
the information stored in the internal latches.
When the read enable input, GR , is high, the data
outputs are inhibited and remain high.
Four data inputs are available which are used to
supply the 4-bit word to be stored. Location of the
word is determined by the write address inputs A
and B in conjunction with a write·enable signal.
Data appl ied at the inputs should be in its true
form. That is, if a high·level signal is desired from
3:
.....
........
~
o
c
3:
U'I
...
~
CD
U'I
connection diagram
.......
o
3:
.....
~
CD
U'I
TOP VIEW
DM54195/DM74195(SN54195/SN74195)
4-bit parallel-access shift registers
general description
permit the first stage to perform as a J.j(, D·, or
T·type flip·flop as shown in the function table.
The DM54195/DM74195 are 4-bit shift registers
which feature parallel inputs, parallel outputs, J.j(
serial inputs, shift/load control input, and a direct
overriding clear. All inputs are buffered to lower
the input drive requirements. The registers have two
modes of operation:
Parallel (Broadside) Load
Shift (In direction OA toward 0D)
Parallel loading is accomplished by applying the
four bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flop and appears at the outputs after the
positive transition of the clock input. During
loading, serial data flow is inhibited.
features
• Synchronous parallel load
• Positive edge triggered clocking
• Parallel Inputs and outputs from each flip-flop
• Direct overriding clear
• J and K inputs to first stage
• Complementary outputs from last stage
• For use in high performance:
Accumulators/Processors
Serial to parallel, parallel to serial converters
• Typical power dissipation
195 mW
• Typical clock frequency
39 MHz max
Shifting is accomplished synchronously when the
shift/load control input is high. Serial data for this
mode is entered at the J.j( inputs. These Inputs
connection diagram
TOP VIEW
9·5
DM7544/DM8544 TRI-STATE®quad switch debouncer
general description
features
The DM7544/DM8544 is a Quad SWitch Debouncer
for use in front panel and similar applications.
The part consists of four RS flip·flops, with
internal pull up resistors for increased noise
immunity, which store the switch condition information. A strobe output is available wh ich allows
sampling of the sWitch Information at a predetermined time. TRI·STATE® outputs are provided for switch line bus connections.
• Eliminates push-button noise
• Allows clocked devices to be operated from
sWitches
250mA
• Maximum power dissipation
• Bus·llne connectable
connection diagram
GND
TDPVIEW
DM7555/DM8555 TRI-STATE®programmable decade counter
connection diagram
general description
The DM7555/DM8555 is a TRI-STATE four-bit
decade counter which has both conventional and
TRI·STATE outputs. When the TRI-STATE out·
puts are in the high-impedance mode, they can be
used to load information into the subsequent stage.
This is particularly useful in applications involving
program counters. Fully synchronous operation
results when these devices are cascaded.
features
375mW
27 ns
50MHz
• Typical power dissipation
• Target propagation delay
• Target clock frequency
logic diagram
.. "
Dr'ro.
~
, .......
~
r-
,
.
.
~::
&,J
J
...--,
.
I
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I
,
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~:-
fT'
~r:-:
~:.
"-';. .
~
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L
:rJo..
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Vo;e
~
1/08
--= P-Yl ,--
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GND:8
9-6
-Dl-
Qt,'ro.
Pr'
.
.
G,
" coo.,.
MAX
3
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,
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3:
.....
®
DM7556/DM8556 TRI-STATE programmable binary counter
general description
C1I
C1I
0)
connection diagram
......
c
The DM7556/DM8556 is a TRI-STATE four-bit
binary counter which has both conventional and
TRI-STATE outputs_ When the TRI-STATE outputs are in the high-impedance mode they can be
used to load information into the subsequent stage_
This is particularly useful in applications involving
program counters_ Fully synchronous operation
results when these devices are cascaded_
3:
00
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3:
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features
~
w
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375mW
27 ns
50 MHz
• Typical power dissipation
• Target propagation delay
• Target clock frequency
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3:
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logic diagram
CD
~
.
Vee-IS
,
"
,
,
'.
"
GND-I
"
DM75493 4-segment LED driver
DM75494 6-digit LED driver
general description
The DM75493 and DM75494 are designed to be
used to interface between MOS and LED displays_
These two devices are pin equivalent to the
DM75491 and DM75492 but have several advantages_ The DM75493 and DM75494 can be
operated at lower supply voltages and therefore
will reduce power consumption_ The DM75493
is designed to give a relatively constant current
through an external resistor, independent of supply voltage_ Each circuit has a blanking input_
connection diagrams
vee
Vss
Vss
Voo
Voo
TOP VIEW
TOP VIEW
DM75493
DM75494
9-7
\.
DM7833/DM 8833, DM7834/DM8834, DM7835/DM8835,
DM7839/DM~839 quad TRI-STATE® transceivers
general description
This family of TRI-STATE® party line transceivers offer extreme versatility in bus organized
data transm ission systems. The data bus may be
unterminated, or terminated DC or AC at one or
both ends. Drivers in the third (high impedance)
state load the data bus with a negligible leakage
current. The receiver input current is low allowing
at least 100 driver/receiver pairs to utilize a single
bus. The bus loading is unchanged when Vee = OV.
The receiver incorporates hysteresis to provide
greater noise immunity. All devices utilize a high
current TRI-STATE output driver. The DM7833/
DM8833 and DM7835/DM8835 employ TRISTATE outputs on the, receiver also, while on
the DM7834/DM8834 and DM7839/DM8839 the
receiver outputs are standard active pull up T2 L
10
CW)
00
00
:E
Q
.......
10
CW)
,...
CO
:E
Q
~
C")
The DM7833/DM8833 are non-inverting quad
transceivers with a common driver disable control and a common receiver disable control.
00
CO
:E
The DM7839/DM8839 are non-inverting quad
transceivers with a common two-input driver
disable control.
Q
.......
~
The DM7834/DM8834 are inverting quad transceivers with a common two input driver disable
C")
,...
00
~ontrol.
:E
TJ1e DM7835/DM8835 are inverting quad transceivers with a common driver disable control
and a common receiver disable control.
features
450mV (typ)
Receiver hysteresis
l.4V (typ)
Receiver noise immunity
50ILA (max)
Receiver input current
for norma I Vee or
Vee = OV
• Receivers
16 mA at O.4V (max)
Sink
Source
2.0 mA (mil)
2 4V ( .)
5,2 mA (com) at.
min
•
•
•
•
Drivers
Sink
50 mA at 0.5V (max) or
32 mA at O.4V (max)
10.4 mA at
2.4V (min)
Source
•
•
Drivers have TR I-STATE outputs
DM78331DM8833 and DM7835/DM8835 receivers have TR I-STATE outputs
• Capable of driving lOOn DC terminated buses
• 74 series'TTL compatible
Q
connection diagrams
C")
C")
00
00
:E
Q
.......
C")
C")
,...
00
:E
Q
TOP VIEW
DM78331DM8833
TOP VIEW
DM7835/DM8835
9-8
TOP VIEW
DM78341DM8834
TOP VIEW
DM7839/DM8839
c
s:
"0001
DM7856/DM8856,
DM8857,
DM7858/DM8858 BCD-to-7segment LED drivers
en
"-
c
s:
00
00
general description
01
en
C
In addition, with the use of an external current
limit resistor per segment, thiS circuit can be used
in higher current nonmultiplex LED applications.
This series of 7-segment display drivers fulfills a
wide variety of requirements for most active high
(common cathode) Light Emitting Diodes (LED)_
Each device fully decodes a 4-bit BCD input into a
number from 0 through 9 in the standard 7-segment
display format, and BCD numbers above 9 into
unique patterns that verify operation_ All circuits
operate off of a single 5.OV supply.
s:00
00
01
"C
The DM7858/DM8858 has active high outputs
with source current adjustable with the use of
external current limit resistors, one per segment_
ThiS feature allows extreme flexibility in source
current value selection for either multiplex or
non-multiplex common cathode LED drive applications. It allows the system designer freedom to tailor
the drive current for his particular applications.
The DM7856/DM8856 has active-high, passive
pull-up outputs which prOVide a typical source
current of 6.0 mA at an output voltage of 1.7V.
The applications are the same as for the DM5448/
DM7448 except that more design freedom is
'allowed with higher source current levels. This
CirCUit was designed to drive the MAN-4 or equivalent type display directly without the use of
external current limit resistors.
s:
"
00
01
00
"C
s:
features
•
•
Lamp-test input
Leading/trailing zero suppression
00
00
01
(RBI
00
and
RBO)
The DM8857 has active-high outputs and IS designed to be used with common cathode LED's
in the multiplex mode. It provides a typical source
current of 50 mA at an output voltage of 2.3V.
•
Blanking Input that may be used to modulate
lamp intensity or inhibit output
•
TTL and DTL compatible
•
Input clamping diodes
connection diagram
TOP VIEW
9-9
"
en
co
co
DM8864 9-digit LED driver
DM8866 7-digit LED driver
:!
c
.......
"enco
:!
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general description
display operating up to 50 mAo In a multiplex
mode. They feature a "low battery" indicator
driver which will light a decimal point whenever a
9.0V battery drops below 6.5V typically.
The DM8864 is a 9-digit LED cathode driver and
the DM8866 is a 7-digit LED cathode driver. They
are designed to interface between MaS calculator
or clock circuits supplying 2.0 mA, and LED
en
co
co
co
connection diagrams
:!
c
.......
en
co
co
"
:!
c
GNO
"coco
co
TOP VIEW
TOP VIEW
DM8864
DM8866
:E
c
.......
DM7887/DM8887 8-digit high voltage
anode driver (active-high inputs)
DM7889/DM8889 high voltage segment driver
DM7897/DM8897 8-digit high voltage
anode driver (active-low inputs)
"
:!
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co
co
CD
CD
CO
CO
general description
:!
The DM7887/DM8887 and DM7897/0M8897 are
deSigned to drive the individual anodes of a·seven
segment (cathodes) high-voltage gas discharge panel
In a time multiplexed fashion.
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~
CD
CO
CO
constant output sink current, which can be adjusted
by external program resistor, Rp. The program
current is half that of output on current. In the
"OFF" state the outputs can tolerate more than
80V. The ratio of "ON" output currents is within
±10%. Inputs have negative clamp diodes. Active
high input logic. The main application of the
device is to interface MaS CirCUits to high·voltage
displays. The total power dissipation in the package
is low.
When driven with appropriate input signals, the
driver will switch voltage and impedance levels at
the anode. This will allow or prevent IonIZation
of gas around selected cathode In order to form a
numeric display. Their main application will be
to act as buffers between MaS outputs (fully·
decoded) and the anodes of a gas·dlscharge panel,
Since the devices can source up to 16 mA at a low
impedance and can tolerate more than 55V In the
off state.
:!
c
features
• Versatile circuits for a wide range of display
applications
• High breakdown voltages
• Low power dissipation
DM7889/DM8889 is capable of driving eight
segments of a high-voltage display tube with a
connection diagrams
TOP VIEW
DM78871DM8887
9-10
DM7889/DM8889
DM7897/DM8897
c
3:
U'I
DM54L123/DM74L123(SN54L123/SN74L123)
dual TTL/monostable multivibrator
general description
features
The DM54L 123 is a low power dual retriggerable,
resettable monostable multivibrator providing an
output pulse whose duration and accuracy is a
function of external timing components. Its inputs
and outputs are compatible with all 54L and 74L
products.
•
•
There are two inputs per function, one active LOW
and one active HIGH. This permits triggering on
either the leading (positive going) or trailing (negative going) edge. Triggering is independent of
input transition time or pulse width. An input
cycle time shorter than the output R *C cycle time
will retrigger the DM54L 123 and result in a continuous output.
•
•
•
•
•
.j:IIo
!:;
N
W
......
c
3:
~
25mW
Low power
'O%to 100%
Resettable and
retriggerable
duty cycle
Low power TTL compatible inputs and outputs
Triggers on leading or trailing edge
Complementary outputs
Compensated for temperature power supply
variations
50 ns (typ)
High speed, trigger to Q
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c
3:
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connection diagram
......
c
3:
00
o
Retriggering may be inhibited by tying the 6 output to the active LOW trigger input or the Q
output to the active HIGH input.
r-
CD
U'I
C
The true output may be forced LOW during any
phase of input or output timing by connecting a
logic LOW level to the reset input.
3:
'-I
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r-
CD
~
C
3:
DM70L95/DM80L95.
®
DM70L97/DM80L97 TRI-STATE hex buffers
00
o
Ii)
'-I
general description
features
The DM70L95/DM80L95 and DM70L97/DM80L97
are a collection of six non-inverting buffer gates
which can be disabled to provide a high impedance
(TRI-STATE) output. The disable function is performed by two inputs, DlS 1 and DIS 2 , which produce the TRI-STATE when taken high. For the
DM70L95/DM80L95 all outputs go to the Hi-z
STATE if DIS 1 or DIS 2 are high. For
DM70L97/
DM80L97, outputs 1, 2, 3, and 4 are disabled
(Hi-z) when DIS1 = "1" and outputs 5 and 6 are
disabled (Hi-z)' for DIS 2 = "1."
• TRI-STATE outputs
• Typical power diSSIpation
22mW
• TYPIcal propagation delay
40 ns
the
• DM70L95/DM80L95 and DM70L97/DM80L97
have same pinouts as DM7095 and DM7097
respectively
connection diagrams
DM70L95/DM80L95
DM70L97/DM80L97
9-11
o
o
N
DM70L96/DM80L96,DM70L98/DM80L98 TRI-STATE® hex buffers
general description
features
tJ)
r:t
~
The DM70L96/DM80L96 and DM70L98/DM80L98
are a collection of six inverting buffer gates which
can be disabled to provide a high impedance
(TRI-STATE) output. The disable function is performed by two inputs, DIS 1 and DIS 2 , which
produce the TR I-STATE when taken high. For the
DM70L96/DM80L96 all outputs go to the Hi-z
STATE if DIS 1 or DIS 2 are high. For the
DM70L98/DM80L98, outputs 1, 2, 3, and 4 are
disabled (Hi-z) when DIS 1 = "1" and outputs 5
and 6 are disabled (Hi-z) for DIS 2 = "1."
c
........
o
o
N
tn
~
In
~
C
00
en
...J
o
•
TRI-STATE outputs
•
TYPical power dISSipation
17mW
•
Typical propagation delay
30 ns
•
DM70L96/DM80L96 and DM70L98/DM80L96
have same pinouts as DM7096 and DM7098
respectively
connection diagrams
00
~
C
........
00
en
...J
o
.....
1
~
C
DM70L9.S/DM80L9S
CD
8
GNO
DM70L98/DM80L98
DM54S200/DM74S200 (SN54S200/SN74S200)
256-bit read/write memories with TRI-STATE®outputs
en
...J
o
00
~
C
........
general description
The DM54S200/DM74S200 256-bit active-element
memories are monolithic transistor-transistor logic
(TTL) integrated circuits organized as 256 words
of one bit each. They are fully decoded and have
three gated memory-enable inputs to simplify
decoding required to achieve the desired system
organization. The memories feature PNP input
transistors which reduce the low-level input current
requirement to a maximum of -0.25 milliamperes,
only one-eight that of a normalized Series 54S/74S
load factor. The memory-enable circuitry is implemented with minimal delay times to compensate
for added system decoding.
CD
en
...J
o.....
~
C
The TRI-STATE output combines the convenience
of an open-collector with the speed of a totempole output; it can be bus-connected to other
similar outputs, yet it retains the fast-rise-tlme
characteristics of the TTL totem-pole output.
the write cycle) IS avaJiable at the output when the
write-enable input is high and the three memoryenable inputs are low_ When anyone of the
memory enable inputs IS high, the output will be
In the high-impedance state.
features
• SchottkY-clamped for high-speed memory
systems:
Access from memory-enable Inputs 20 ns typ
Access from address inputs
31 ns typ
Power dissipation
1.7 mW/blt typ
•
TRI-STATE output for driving bus-organized
systems and/or highly capacitive loads
•
Fully decoded, organized as 256 words of one
bit each
•
Compatible with most TTL and DTL logic
cirCUits
Multiple memory-enable Inputs to minimIZe
external decoding
•
Write Cycle: The complement of the information
at the data input is written into the selected
location when all memory-enable inputs and writeenable Input are low. While the write-enable input
is low, the output is in the high-Impedance state.
When a number of outputs are bus-connected, this
high-Impedance output state Will neither load nor
drive the bus line, but it will allow the bus line to
be driven by another active output or a passive
pull-up if demed.
Read Cycle: The stored Information (complement
of information applied at the data input during
9-12
connection diagram
LM75461, LM75462, LM75463, LM75464
dual peripheral drivers (high voltage)
general description
These circuits are high voltage versions of the
LM75451A, LM75452, LM75453, and LM75454
series. Pin configurations for the corresponding
parts in the two series are identical. Each circuit
contains two independent high voltage transistors
each capable of sinking 300 mA at the same time.
features
•
•
High breakdown
Outputs withstand high voltage with Vcc = OV
for power strobing applications
•
Both outputs can sink 300 mA simultaneously
•
Two separate drivers per package
•
Identical pin configurations as the lower voltage
LM75450 series equivalents
•
a·pin mini·dual·in-line package
•
Inputs have clamp diodes and are DTL/TTL
compatible
connection diagrams
vee
B2
A2
X2
vee
B2
A2
X2
Al
Bl
Xl
GNO
Al
Bl
Xl
GNO
LM75462
LM75461
vee
Al
Bl
LM75463
lA
2B
2A
2V
lB
IV
GNO
LM75464
9-13
o"
00
00
MH7803/MH8803.
MH7807/MH8807 oscillator/clock drivers
::t
:E
""o
00
general description
"::t:E
The MH7803/MH8803 and MH7807/MH8807 are
complete self-contained two-phase oscillators and
clock driver subsystems for MOS micro-computer,
calculator and shift register systems.
(W)
o
00
00
features
::t
"o
• No external tir'1ing components
• Two non-overlapping outputs
• Both frequency and pulse width are voltage
controlled
"::t
logic diagram
:E
(W)
•
Frequency adjustable from 100 kHz to 500 kHz
(MH7803/MH8803) and from 400 kHz to
2 MHz (MH7807/MH8807)
•
Pulse width adjustable from 300 ns to 2J..ls
•
Low power for battery operation
•
TTL outputs for verification and synchronization
•
Both direct and damped MOS outputs
00
:E
--ov·
--ov·
FREQUENCY CONTROL
PULSE WIDTH CONTROL
--0 INHIBIT
--0 TEST
0--------...1
.........--ovcc
TIL OUTPUTS
DAMPED MOS OUTPUTS
10<1
.,o-JV~-;---t-+--1
.,
.....- . .--oGND
DIRECT MOS OUTPUTS
connection diagrams
14
INHIBIT INPUT
<1>1
v+
13 TEST
PW CONTROL
INHIBIT
MUS DAMP:ED
<1>1
MUS
v'
4 -.........::1-1
¢'2MOS DAMPED
TEST
'1>2
Mas 4 -.........::1-1
v-
'hITTL)
GND (TTL)
FREQ CONTROL
TOP VIEW
MH7803/MH8803
9-14
MH7807/MH8807
s:
l:
MH8804 quad MOS memory driver
MH8805 dual MOS memory driver
00
00
o
.fao
general description
s:
features
The quad MH8804 and the dual MH8805 are
bipolar to MOS drivers specifically designed to
drive input address lines for MOS memory arrays
using MM1103 type RAMs. The MH8804 is pin
compatible with the 13207 and the MH8805 with
the SN75361.
l:
•
Current mode output drive
•
Rise and fall times
•
•
Delay times
High output voltage
•
Low output voltage
•
Input levels
±500 mA
00
00
20 ns
U'I
o
15 ns
Vss - 1.0V
0.3V
TTUDTL
connection diagrams
16
v"
15
0,
v"
O.
0,
v"
14
0,
O.
13
"
0,
E.
12
E,
11
0,
10
0,
GNO
E,
0,
0,
0,
0,
v"
GNO
v"
TOP VIEW
TOPVIEW
MH8804
MH8805
9·15
»
o
AC Test Circuits
-I
C1I
UI
r+
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.!
5V
o
...
(')
'5V
400n
OUTPUT
INPUT
T
T
+24V
50PF
I:
;:+'
UI
Coo,
Test Circuit 2
Test Circuit 1
,V
Vcc=5V
-
CL
tpdl
50 pF
tpdO
50 pF
tOH
5 pF*
t, H
5 pF'
tHO
50 pF
tH ,
50 pI'
* Approximate value
of jig capacitance only.
':'
Test Circuit 3
Vcc= 5V
SOV
800n
>--"'---<0
INPUT
OUTPUT
Test Circuit 4
Test Circuit 5
SOV
,v
JODI!
5V
OUTPUT
130
INPUTo--==t._;o--t~"""-J*"".t-~f-]
60Dl!
DIOOES·FD100
Test Circuit 6
Test Circuit 7
10-1
+45V
(J
5.0 Krl±l%
....III
Q)
1>-,,--+0) Your
I(J
«
P--...--tO) V
OUT
Test Circuit 8
Vee "'+5V
VON
2K
PULSE GENERATOR OUTPUT
1. SWITCHING TIME (t..... &.
RISE TIME
tpdJ
TESTS
< 15 ns
eCT
fALL TIME < 15 ns
AMPLITUDE"" 4V
FREIL. '" 2 MHz ±S% AT 50% DUTY CYCLE
2 SHIFT RIGHT FREQUENCY TEST
RISE TIME < 15 NS
FAll TIME < 15 NS
AMPLITUDE"" 4V
fREQ. =
CL INCLUDES
PROBE AND JIG
CAPACITANCE
15 MHz WITH PULSE WIDTH
ADJUSTMENT SO THAT VIN HAS
DUTY CYCLE OF APPROX. 50%
Your
Your Your
YOUT
Your
Test Circuit 9
VIN
Vee1 " VCC2
VOUT
Your
TO CHANNEL "A"
+20 Vdc
OR
NOR
TO
CHANNEl
"8"
INPUT
PLllSE
GENERATOR
INPUT PULSE
t+=I-=20t020s
(20t080%1
A.LL INPUT AND OUTPUT CABLES TO THE SCOPE ARE EnUAllENGTHS OF 5G-OHM COAXIAL CABLE
WIRE LENGTH SHOULD BE < 1/4 INCH FROM TP'N TO INPUT PIN AND TP OUT TO OUTPUT PIN.
Test Circuit 10
10-2
~
AC
~
SEE
TABLE 1
.
LOAD
n
~
I -
C')
C
Figure 1 (Test Circuit)
INPUT CONDITIONS
TEST
TRANSFER
ENABLE
Vee
CLEAR
PRESET
CP
Vee
GND
GND
See Note 1
Vee
GND
GND
See Note 1
Vee
GND
Vee
GND
GND
See Note 1
See Note 2
001
002
CE
tpdO
GND
GND
tpd'
GND
GND
tpd(TEI
GND
t'H
See Note 3
See Note 3
GND
GND
Vee
GND
Vee
tOH
See Note 3
See Note 3
GND
Vee
GND
GND
Vee
t H,
See Note 3
See Note 3
GND
GND
Vee
GND
Vee
tHO
See Note 3
See Note 3
GND
Vee
GND
GND
Vee
GND
GND
Vee
GND
GND
See Note 8
Vee
fctock
Table 1
5V
40012
NOTE 1 PULSE GEN PRR
-
$ MHz, t,. $15 ns, It ::; 5 ns,
tp (CLOCK)
2: 200115
NOTE 2 See AC SWITCHING TIME WAVEFORMS
NOTE 3 TIE THESE INPUTS TOGETHER, SEE SWITCHING TIME
WAVEfORMS.
NOTE 4 INCLUDES JIG CAPACITANCE
NOTE 5. ALL DIODES ARE FD1DO OR EQUIVALENT
NOTE 6 OPEN SWITCH 83 FOR ~(TCI, tpell (T&), tpdO(CETl, AND
INPUTS
~
-
DIODES
,. (SEE
NOTE 5)
"
t".i,tCETl.
NOTE 1. JIG CAPACITANCE
NOTE S' fCLOCK USE 50% DUTY CYCLE
Figure 2 (Load Circuit)
TEST
CL
tpdO
50 pF
tpdl
50 pF
tpd(TE)
50 pF
"H
tOH
5 pF (See Note 71
5 pF (See Nole 71
t H,
50 pF
tHO
50 pF
f clock
50 pF
Table 2
Test Circuit 11
10-3
en
.t::
..
~
~
CJ
r - -V;;--- ----,
I
I
I
R,·",n
I
I
I C, '15"
I
...en
CD
l-
s,
s,
CJ
s,
«
s"
ii,
A,
I,
A,
F,
F,
ii,
..
A,
Co
F,
F,
L~ _~O~~
_
-.:-
5V
DATA
40Dn
CONTROL
01
J
"
r---V~-----'
I
I
I
I
I
R,',oon
A., I-.L-_-"
-:r
L __
C
"15"
Load Diagram
,---
:
~D.E!.!!.C'!!.T.!
CL
_ _ -.J
t5. tho tpdR
50 pF
NOTE 1- USE LOAD CIRCUIT Z FOR A = B OUTPUT ONLY. LOAD CIRCUIT 1 SHOULD BE
USED TO TEST THE REST OF THE OUTPUTS.
t wpw • t rpw
50 pF
NOTE 2 FOR INPUT PULSE, F = 1 MHz, lOUT"" SOn 50% DUTY CYCLE,
to = l!:::; 10 nl.
NOTE 3. Cl INCLUDES PROBE AND JIG CAPACITANCE.
NOTE 4: ALL DIODES ARE IN3064
IOH
= 3V
VIN PP
ITH
Test Circuit 12
5 pF'
5 pF'
IHO
50 pF
IHT
50 pF
*Approximate value
of jig capacitance only.
Test Circuit 13
Vcc"SV
Test Circuit 14
50V
400n
r-----,
01
fO~UT~PU~T~t-_~_~r-+
ALL DIODES ARE fDl00
Test Circuit 15
10-4
»
(")
tHV
-t
CD
en
....
75V
.
(")
"~--<~OUTPUT
n
c
Ct ""15pF
....en
TINOT'"
(a)
(b)
OUTPUT
NOTE 1 THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS ZOUT
PRR-l00 KHz,t w "'If'i
NOTE 2 CL INCLUDes PROBE AND JIG CAPACITANCE
50n,
(e)
Test Circuit 16
Vee = SOV
r+
v"
I
I
10k
OUTPUT
27k
IADJ
56'
L+
-
-=-
Test Circuit 17
Test Circuit 18
Vee = 50V
40k
OUTPUT
DIODES ARE lN914
Test Circuit 19
10-5
....
I/)
'5
...u
t,)
....
I/)
OUTPUT
CD
lt,)
«
SWITCH S,
SWITCH S2
CL
tdp
Closed
Closed
50 pF
to.
Closed
Closed
50 pF
tOH
Closed
Closed
'5 pF
t'H
Closed
Closed
'5 pF
tHO
Closed
Open
50 pF
tH'
Open
Closed
50 pF
* Jig capacitance
(,)
llpF
q
+5DV
+50V
'NruTA,B
PUlSEGEN NO 3
(CURRENT)
SfifOBE
PUlSEGENN02
OPEN
PRESET
0-----<>-1
DISABLE
PULSEGENNOI
51
t,=t,·5nl
Ro ~ 51 FOR PG II!. 2
Ipw: tsw: 20 ",MAX
IS =
t Dw :200m,MAX
lOV
20~,MAX
.".
(e)
(b)
+50V
INPUTA,B
OPEN
0-----<>-1
DISABLE
'0
lOW
ZOO ns MAX
(dl
Test Circuit 20
Test Circuit 21
10·6
l>
n
-I
CD
III
r+
.
n
n
c
r+
III
Test Circuit 22
(b)
(a)
(e)
Test Circuit 23
OUTl'UT
o-_--
CO
50%
DUTY CYCLE
~
OV
CLOCK
[
'.-,
15VO___ n
-----.-li--O
"-__
I
~I~
O%
~
:,\15V---:J
15V
:L-Y!
'O~
CLOCK
I
n
r;AVEFORM USED TO_MEASURE
tpd 0 (Q) AND tpd 1 (0)
I
10%
__I :"-""
~'OV-T~
90%
I WAVEfDRM USED TQ.MEASURE
~d 0 (0)
lid
'''' --::-.
I
I
I
1
I
I
I
I
tpdl~
AND ~d 1 (O)
f4- -+I
\4-t p dO
(0)
OORn--------~---------J
QORQ ________~------------~
15V
CLOCK
NOTE
NO MAXIMUM RISE AND fALL TIMES ARE IMPOSED UPON
THE CLOCK VOLTAGE. HOWEVER VERY SLOW TRANSITIONS WHICH
ALLOW AN INPUT TO REMAIN IN THRESHOLD REGION CAN CAUSE
NOISE PROBLEMS.
(b)
Waveform 7
Waveform 8
INPUT OV
OUTPUT
OUTPUT
FREIlUENCY'" 1 MHz
DUTY CYCLE = 50%
t,=~=IDns
Waveform 9
10-10
~
tpdl & tpdO
II)
I
...o<
r------ 3V
tOH
~
I
I
CD
...
I
I
3
I
I
I
I
I
en
CONTROL
ov ::10,,07,,",,3/.:;0";;;';;;";;;31-,
ov
I
OUTPUT
I
----..j ~
LOGICAL '0" LEVEL
3V
tot!
CONTROL
I
(DM1094/DM8094)
:
I
'-------ov
la)
Ib)
3V----,
3V-----"\
CONTROL
OUTPUT - 5V-VOl
,-",IO;;;07;;;";;;".:;00;;.;'",":;:;31_ _ ov
CONTROL
\........;;;10..:;.7,.;;";::"-,0";;,;',;;;".;.;31_ ov
LOGICAL ","lEVEl
OUTPUT
LOGICAL "0" lEVEL
ov'------"1
rf,=-~C::0:::NT::R~OL--3V
I
r+-;;;;;~;_--3V
(DM1094/DM8D94)
ov-----'
ov-------J
Id)
Ie)
LOGICAL "1" lEVEL
ou~]oov
i'---~l5V
:
3V
I
I
I
I
I
I
CONTROL
!
ov..;.IO:;:;";;.;,";;;93;;;/O;;;"","",93...
1
JV
INPUT CHARACTERISTICS
I
I
~
FREQUENCY 1 MHz
PULSE WIDTH lOOns
t,.=~:::;10ns
AMPLITUDE
CONTROL
=
JV
(DM7094!DM8094)
'--------ov
Ie)
Waveform 10
10-11
(I)
E
...
....o
--I, I--
CI)
I I
>
10
~
,~~"'~
INPUT
I
---j
OUTPUT
--j.[-
3V
I
I
'~'*1~
I
y.
r""
3V
I
I
---j
I
....
'\
INPUT CHARACTERISTICS
AMPLlTUDE=JV
FREQUENCY '" 1 MHz
t,=tf=10ns
Waveform 11
tHO & tHl
tpdl & tpdO
IN'::J'V
STROBE-x..15V
\'V
ov:
1
~\.dO~
tOH & tlH
OUTPUTS
I
~tpdlr--
-
STROBE - - - . J - l 5V
'"'
~
OUIPUT
I
1
15V
I
I
OUTPUT
i"'j
15V
I
I
15V
~-'50V
15V
VOLTAGE
~I'{
15V
OUTPUTS
ACTUAL "0"
.,v
f" 1 MHz
t,=tt::;;10ns(10%to90%)
DUTY CYCLE'" 50%
15V
-
'"'
- '~h.
P05V
t
05V
~
ACTUAL "I"
VOLTAGE
;;,:r
- ""~
~
(e)
(b)
(a)
Waveform 12
15V
MEMORY~
ENABLE
15V
r-
ADDRESS
INPUTS
--
------'
1\'5V
- - - - - - - --f--tpdl
f---tpdO
15V
15V
OUTPUTS
J
1-- '....
15V-f
~,~~
10-12
INPUT PULSES
t,=IOns
,,"'IOns
f=1 MHz
Waveform 13
",15V
",,15V
~
II)
3DV
15V
OOV
3DV
15V
OOV
3DV
<
(1)
~
..,
0
3
1.5V
1/1
OOV
t,
=
If
=
10 ns (10% to 90%) ON CLOCK AND INPUT DATA WAVEFORMS
NOTE 1 INPUT DATA IS APPLIED TO SERIAL INPIJT WHEN MODE CONTROL
EQUALS A LOGICAL ZERO INPUT DATA IS APPLIED TO INPUT A, B. C, OR 0,
WHEN MODE CONTROL EIlUALS A LOGICAL ONE
Waveform 14
.};"'--...",;±-t---- 3V
OV
t,-tl-IOns
PW=100ns
FREQUENCY = 1 MH!
Vcc =+50V
Waveform 15
Read Cycle
Write Cycle
·OUTPUT
ME
WE--+-,"",
ADDRESS-----.J.
ADDRESS
A
t hold
,
ADDRESS
ADDRESS
C
OUTPUT_-
"OUTPUT SHOWN FOR STORED DATA IN
ADDRESS A = " IN ADDRESS B = 0
-
-_-_-_-_-_-_-.+.~-+--..~-
-
(al
~---
tSf
_
~'0~5:,v
_ _ _ __ ",,15V
(bl
Waveform 16
Write Cycle
MEMORY
ENABLE~15V
OUTPUTS
OUTPUTS
ME
""
WE--+-""'\l
05V
Ac:~ti~~~---+_....~
I " i - - - - - - , 15V
1.5V
.OV----+-J
OUTPUT_-
_
15V
-_-_-_-_-_-_-.+~-+--..~-
-
~---
t..
(al
""I
_
(bl
(cl
Waveform 17
10-13
!II
E
...
....o
-1m
v'.~
1iV
CD
G10Rli z
>
CIJ
\._----
-.l ~.. ~
TO ,UmIT
~
•
.... I---
~
I
m'
VOUT
1_
F
(al
V'.~
f
15V \ \ . ._ _ _ _ _
-J .... r-
",B,e,ORO
Tt!OUTPUT
~
11V
. . r-
15Vfr-----....~
VOUT
lbl
Waveform 18
OUTPUT------+-..J
'-=:1
DUTPUTI---------~
t,.:I,=10ns
1=1 MHz
Waveform 19
FR£ClUEICY-,MItr
... ·IrSIi.
~~-~:J~-----------w
II.:::'--_ _ _ _ IV
IIII'UT
C.or'a
OUTPUT WAVEfORM ,
~:,c...l"c
_____..J
v.,
(.1
OUTPUT WAVEFORM 2
v••
"v\------+--~... ~
r- --'I
t~I'
VOL
WOTE 1 CL m !iOpF INCLUDING PROBE AND.tII CAPACITANCE FOR DM54112. OM14IU
WOlEZ ALLDIODESAREIN3OI4
(bl
Waveform 20
10·14
~
<
CD
II)
....
o
3
C/)
tOH
~
LOGICAL "'" LEVEL
OU~]"V
,-----3V
i"'--- ~"V
rt,'- - - - - - 3V
-",,15V
'V.,:"::;;":::o:...-__-'
OUTPUT
LOGICAL "0" lEVEl
I
I
I
,
I
I
I
~ tGH \ . -
,v
I
DISABLE INPUT
I
I
t'H~
(b)
(0)
3V----"""'\
3V-----"'\
OUTPUT- 5V-VOI
,----=0;;:"::.;":;,:'.:.',;:'O::,;'U:;,:1_ _ 'V
\--"-'="'-''"-'---ov
LOGICAL "1" lEVEL
LOGICAL "0" LEVEl
OV _ _.....;;0.:.U1;;.'U",1_--r
--...:
tHl
(d)
(e)
tpd1 & tpdO
OUTPUT
INPUT CHARACTERISTI(:
AMPLITUDE = JV
FREQUENCY" 1 MHz, 50% DUTY CYCLE
t,.""t..:S 10ns(10%to90%)
(e)
Waveform 21
10-15
Ul
E
...
o
op-
"~'~*~-f'
CD
>
1"11
~
DATA INPUTS"
..."
YC
15V
OUTPUT
m~' ~
••
~
5V
STROBE INPUT
\'5V
J.5V
tpdO
DATA INPUTS" _ _ _- '
OUTPUT - - - - - - - - - - - - -
(DATA INPUTS- TO PROVIDE LOGICAL "1" ON OUTPUT UNOER TEST)
STROBE INPUT
~
~Y
EITHERDUTPUT
(DATA INPUTS- TO PROVIDE LOGICAL "I" ON OUTPUT UNDER TEST)
15V
"THE DATA INPUT WAVEFORMS SHOWN MAY NOT NECESSARilY REPRESENT THE ACTUAL DIRECTION OF THE TRANSI·
TION FOR A PARTICULAR DATA INPUT PIN THE TRANSITIONS
EITHER OUTPUT
t,,,
SHOWN INDICATE ALSO WHAT AN OUTPUT WOULD DO IF IT
WEREN'T FOR THE STROBE INPUT IN ALL CASES THE WORST
CASE INPUT·TO-OUTPUT PATH IS SPECIFIED REGARDLESS OF
THE TRANSITIONS SHOWN
15V
(b)
(a)
Waveform 22
1. PROPAGATION DELAYS FROM DATA INPUTS TO OUTPUT
2 SETTLING TIMES FROM CHANGE OF A, B, or C TO CORRECT DATA OUTPUT
DATA INPUT
SELECT INPUT
(NOTE 1)
OUTPUI _ _ _ _"""'
DATA INPUTS CONNECTED IN ANY LOGIC CONFIGURATION
NOTE 1 WHEN THE SELECT INPUTS ARE TAKEN TO OPPOSITE LOGICAL LEVELS SIMULTANEOUSLY, THE
ONE (ONES) MAKING THE LOGICAL "I" TO LOGICAL "0" TRANSITION PROVIDE THE WORST·CASE PATH
NOTE Z TRANSITION TIMES SPECIFIED ARE INDEPENDENT OF THE DIRECTION OF THE OUTPUT WAVEFORM
SET INPUTS A, B, C SUCH THAT TESTED INPUT IS ROUTED TO THE OUTPUT
(a)
(b)
Waveform 23
CLEAR
1.5V
INPUT
DISABLE
rT\.~.,
,
•
\.,
INPUT ~
- I ...'
L.--'= I
DATA
OUTPUT
CLOCK
OUTPUT
Waveform 24
10-16
~r-
___ 3~11~515V~_____________
Waveform 25
~
<
CD
I»
....
o...
3
CP----t--t--,r-+--------
III
IN'U'~3V
15V
3V
15V
---------------- W
'v
,-~------- 3V
~
"
PRESET--i------~---/--\-----'------'V
_
15V
CLEAR--i-----~------l-'L-=
15V
15V
OUTPUT
'V
(bl
3V
CE-~I~~~H_~~~~~~-
15V
tHO
'V
INPUT
]
3V
TE-~~~~+~~~~~~-
3V
15V
15V
OUTPUT
OUTPUTS---r--t---+-t----I---~\--OR
15V
OUTP~~ _ _-+-....JI
,-----15V
Voc
t..,
(TC)
(.1
(el
3V
'V_'N'u't,,,~
TE
15V
,.• I------3V
~
15V
~~-t-----'V __--"L_ -
LO~,~ti~~;-------------=-+--.l--ACTUAL
OUTPUT
3V
t5V-1E
OUTPUTS
5V
---",15V
OH
V
'V
VOH
tPd1t--::~~~~~~~~~-\- :::
I-- -"
(TEl
(dl
tpdO
(TEl
(el
toH
f----------
IN'jU'-t
_
3V
1.5V
'V
~'Jq
ACTUAL
OUTPUT
LO~lgt;~~;--------'·
""lSV
--r
'V
(II
Waveform 26
10-17
....oE
II)
G)
Clear Pulse Width and Dalay
>
ca
~
Data Satup and Hold
~ROTE
-----.1
06V
DATA HOLD
TIME
I5V
ISV
CLEAR _ _ _-'I
JI
DATA _ _ _ _ _ _ _
OUTPUT
----1----.
10RI
DATA - - - - -_ _""
(al
(bl
3V-----.
~-----3V
tOH
OUTPUT - 5V-VDl
VI
.v
i
I
II'rn!
OUTPUT
LOGICAL "0" LEVEL
'--""=;;.;,;=--.V
~"v
D,V
1
-....J I.tOH
LOGICAL "0" LEVEL
(el
.':_'T'M'
(dl
K
I
3V----....,.
.::.1.&V
,--,D",IS",",,';;.'",OO",PU"T_ _ ,V
rtl - - - - - -..
I
LOGICAL "1" LEVEL
1
1
1
1
I
ov
DISABLE INPUT
~.
(el
1
1
:-
,V _ _...;;DU",T",PU"T_-f
INPUT CHARACTERISTICS
FRED 1 MHz
PULSE WIDTH.
1.
dl
1,.=t, S 10ns
AMPLITUDE = 3Y
Waveform 27
10-18
:e
I»
"J-
<
CD
.....
o...
3
10%
CLOCK
III
CARRY, BORROW
IS.
OUTPUT---f-J
OUTPUT---+--"'\
Waveform 28
3D.
NOTE 1 CLOCK MAY BE AT EITHER A LOGICAL "1" OR A LOGICAL ''O''WHILE CLEARING'
NOTE 2' NEGATIVE HOLD TIME VAlUES INDICATE SA . S8 INFORMATION MAV BE RElEASFD
PRIOR TOTHE TIME THE CLOCK PULSE REACHES ITS 1.5V LEVEL
NOTE 3. CLEAR AND CLOCK WAVEfORMS
to '" It "10 ns(10%-90%, 90%-10% TRANSITION);
f=1 MHz
Waveform 29
D.~
D.------"""'x=-
....
~
Ir
LOAD
""''''''''1
~
LDAD~
t pd1 l1oadl-J
Ir
D~
SERIALIN'UT~
~
15V
irt..,tUPICIOCkl
III nnnnnn
CLOCK~
-r.::-
""""""
15VYlnnnnnn
uuuuuULJI'~Y
-...j
~5{
SERIAL INPUT
CLOCK
_ _--JF
C-
---.J UUUUUULII, '~Y
irtpdllCIOCkl
D
\c
-------=::.I~"'i
Waveform 30
10-19
!II
...E
MEMORY
..-o
15V
ENABLE
1SV
Q)
>
cu
~
ADDRESS
INPUTS
15V
OUTPUTS
15V
16V
INPUT PULSE CONDITIONS
t,.;O t f<__>C
..~: ____JXI.._____~
WRITE
ENABLE
1SV
DATA
OUT _ _ _ _ _ _- '
(al
PULSE AMPLITUDE = 3 ov
RISE TIME AND FALL TIME $ ns.
I/Vaveform 33
10-20
(bl
~
I»
<
....
o
CD
...
3
en
INPUT
OUTPUT--_-t_"'\
t"1 MHz
t,"'"1j "'10m
PW=100n5
Waveform 34
Waveform 35
t.,.l, S TO Z"
PIN 2, 15 = GND PIN 3" Vee
v"
DATA __
SERIAL OR
PARALLEL
15V
CP
15V
VOUTZ
tal
OUTPUT
t.,.l,ETO~
ALL OTHER INPUTS HIGH
V,. ________15V
tal
Voo,---------~
15V
15V
tbl
tpel.I OA TOZA
SEOR~!~~--------------------'-1.5V
v,.
~r---~"
:::j t"t:: j '---It"" - 15Vr\
\.-- - - - - -
Voo, - _ _ _ _
tel
OUTPUT~-------,r
Waveform 37
tbl
VIN 15
!PIN120~Of1i~
VOUT FREQUENCY'" 1/2 X VIN FREQUENCY
tel
Waveform 36
NOTE CAPACITANCE INCLUDES JIG AND PROBE
Waveform 38
10-21
l '. r-
11'1
E
...
o
....
Q)
PIN 13
>
ca
SElECT
90%
I 90%
15V
DATA INPUT
DATA
15V
~
10%
INPUT
=tFr1 V"",
,~, ~
PIN2
I
ZOUTPur
)
PIN2
VOUT1 "
FREQUENCY" 1 MHz
'
DUTY CYCLE" 50%
t,.=1j"10ns
AMPLITUDE=3V
i
~
ZOUTPUT
PIN4
V,"""
---VOUTIOI
~"-
l!iV
15V
PIN 1
1-:,.---,-t---
VOUTIOI
SELECT DATA INPUT TO OUTPUT VOL rAGE
WAVEFORMS E IS LOGICAL '0 ,10 IS LOGICAL T' & VI
=
VOUTllI
ZOUTPUT
PIN 1
VOUTIOI
DATA INPUT TO OUTPUT VOL rAGE WAVEFORMS
PINSS,6,7,9, 10, 11 = Vee
DV
PINS3,5, 11= GNU
E & So ARE LOGICAL "0" & V, "4 5V
PINS4,6,7,9,10,12:V.;c
PINSJ,13"GND
(a)
(b)
Waveform 39
SELECT
DATA INPUT
ENABLE
INPUT
YOUTI1l
Z:OUTPUT
ZOUTPUT
1-,r-----...--1r-- YOUTlll
ZOUTPUT
ZQUTPUT
Vounol
SELECT DATA INPUT TO·OUTPUT VOLTAGE
WAVEFORMS E IS LOGICAL "0", 10 IS LOGICAL "1" & V, - OV
ENABlE TO OUTPUT VOLTAGE WAVEFORMS
So IS LOGICAL "0",10 IS LOGICAL "1" &
v, .. 4 5V
(b)
(at
ir:::::--=-,I--t----VINlll
DATA
INPUT
VOUT(II
FRE(lUENCY= IMHz
DUTY CYCLE - 50%
ZOUIPur
t,.=tt=10ns
AMPLITUDE" lV
Z OUTPUT
DATA INPUT TO OUTPUT VOL rAGE WAVEFORMS
E & SoARE LOGICAL "0" & V, "4 5V
(e)
Waveform 40
10-22
~
III
<
CD
.....
o
3
CIl
'NPUT
30V
~I v~'"'
OV
,~"
OUTPUT
Waveform 41
Waveform 42
i__ :5
,I
Max Power Dissipation Curve
10ns
____ _
50
I
I
~
I
"
40
,,
,,I
I
I
,
,
I
"'''L"n
Waveform 43
Waveform 44
Write Cycle
l't r
11v:"
AoaRES'
'NO"' ~j
t
~
1"[-_lOV
2O:,r["OV
'." ..jI
'·v,~
ounUT~11
ov
V
OUTIH
~--~-VOVT((I)
OUTPUT _ _ _ _ _ _
(a)
(b)
4_5________________
waveform_
'10.23
!II
Read Cycle
E
...
....o
.'~
"""UT~'" ~",--j ~
'~--jh
G)
>
"
~
. .
AOORESS-----..I..
'ADDRESS
ADDRESS
I
ADDRESS
C
-OUTPUT IHOWN FOR STORED DATA IN
ADDftEIS A-1. IN ADDftESS 8 =0
Cc)
Memory Enable
tot!
MEMORY
--1
tHO & tHI
& tlH
MEMORY
ENAllE
VI
v,
E~ILE~
~V
"IJV
:-H~
...
'IV
~--tr
I3V
VOUTIIU
YOUTlIl
i1
,---
.3V
'"1:1V
V
,",
Cd)
Ce)
NOTE. THE PULIE IEIERATUft HAl THE FDLLOWIIID CHlRACTlRm'1CI V·:I OV.
1,.. ,. .... 1, -lllII,f- "IIHI,. DUTY CYCLE-lin V.-13vewc
_louT
Waveform 45 (Con't)
r------- "V
,,
INPUT
I
IV
I
-1'"':I
n.-I
ACTU"
OUIPUT
_ - - - - .. 15V
1
~~~~AIiLET _ _ _ _oJ
Cb)
Ca)
"V
'''''''
\ 1&.
I
I
~
_______________ IV
I
:, '---------IV
,",
I
OUTPUT
OUTPUT
IiV
Cd)
Cc)
Waveform 46
10-24
:E
I»
<
·~-----------l,-----------
....
o...
CD
~-----------I~--~--~----'
:::.~.
"lav
3
{-
!II
.
-------..,'""'
"'" _ _ _ _ _ _ _ _~.
+1tv-
"
(el
Waveform 46 (Con't)
Output Pulse Width vs Timing
Resistance and Capacitance for
CX<103 pF
INPUT PULSES
v.
Va
V.
ex - TIMING CAPACITANCE C,FI
Waveform 47
""I;:
!15V
OTHER CONDITIONS E ~ l. f
~
H, A ~ STABLE
(bl
OTHERCON.IT"''"',.,......H-.A-."-m-'_ ......
(.1
A,
A,
.,
DTHERCONDITlONS C"-H A'STABLE
OTHER CONDITIONS £-L,C"-L,O-H
(dl
Ie)
.rr
\
STABLE ADDRESS
___
w __
OTHER CONDITIONS E"-H
If)
(el
Waveform 48
10·25
II)
E
...
....o
Q)
>
«I
CLEAR
3:
CLOCK
ov --+---1'--'1
JOV--+---I,~--n
OV _ _+-_J
v,, ______
DUTfUlQ
1. :; 10 ni
It S; 11 III
FREQUENCY
~
PUUE WIDTH
10 MHz
~
100 lIS
Waveform 49
CLEAR
OV
CLOCK
OV---r---1'~-J
lOV--+---t;----n
OV ----+-----'
v"
OUTPUlD
----+--"" I
v,,---r--,'-----+---J
vo. ----'--t-r-------'---, I
OU1'U10
v,, ____---I'
NOTE THE INPUT 'ULSES ARE SUPPLIED BV A GENERATOR HAVING THE FOLLOWING
CHARACTERISTICS t, s; 10 ns. It S; 10 lIS, PRR s; I MHz OUTPUT CYCLE:; 50%,
lOUT '"
5Ol! VARY PRR TO MEASURE fMAX
(a)
CLOCK(CPI
CLEAR~U
NOTE ALL At MEASUREMENTS ARE TAKEN AT TRANSITION POINTS OF (15V)
t, ::;10
nl
t,S;10nl
FREQUENCY = 1 0 MHI
PULSEWIDTH~
lOOns
(b)
Waveform 50
10-26
CLEAR
CLOCK
ov --+----+'-~'I
DATA
3OV--+----+,--k.
ov _ _+-_...J
V~
OUTPUTQ
_ _ __
V.< ______'-___- . J
t,:S: 10 1\1
It:;;; 10..
FREQUENCY =' 10 MHz
PULSE WIDTH = 100m
(cl
Waveform 50 (Con't)
Clock Enable Waveforms
Clock-Mode Waveforms
3OV-----,----"V--;-,r--~
COUNT/LOAD
URClEAR
CLQCK I DR
CLOCK 2IN.UT
ov
OV
3OV----I-::"..,[
V~------4---~,---
t,(NOT£2)
CLOCK 1
INPUT
OUTPUT
.. , .. , lie, O. Do
OV------1----t~~~-
V~-------4-~~
V~----~--L
.
V~------~-,
OUTPUT
OUTPUT
OR DD
~,DB,Dc.
V~--------J
Vo<---------'-----
(bl
(al
Claar and Load Waveforms
35Y
CLEAR
ov--4-'-_...J
... ---+-------,..-!--~
DATA INPUTS
A,I,C,ANDD
OV---!-----"
J5Y __-+_____-'-_"
COUNT/LOAD
INPUT
OV--+-~------r~~--'
Y~
OUTPUTS
11,... 0.. IIe,AND000
(cl
NOTE 1 THE INPUT PULSE IS SUPPLIED IV A GENERATOR HAVING THE FOllOWING
CHARACTERlnlCS 'RR:;;;'. MHz, DUTY C'ICLE :;;; 511%, t, < & 0 In. AND UNLESS
SPECIFIED It < s . . . .HEIII TESTING 'MAX. VARY PRR
NOTE Z OPERATION OF THE COUNTER WITH CLOCK It = 15 . . . TESTED WITH CGUNTI
LOAD AND CLEAR HIGH wtlElil MEASURING CLOCK ENAILE TIME, It < & 0 II
NOTE 3 Cl INCLUDES PflDIE ANa JIB CAPACITANCE
NOTE" All DIODES ARE lN3114
NOTE & UNLESS OTHERWISE SPECIFIED. 11,.. IS CONNECTED TO CLOCK Z
Waveform 51
10-27
III
"r:L"--F----'v
~
i
E
...
o
'Po
20V
I
AD~:~~ I ov
G)
>
v,
I
1
--:
1'0
20V
v,
1 OV
r--
Ipdt!
~
I"",
OV
r--
OUTPUT~:
·:Voo,,11
~
,
I
V,
V,
jNote4)
----V""'(O!
(al
Memory Enable
tOH & tlH
OUTPUT
ENABLE
tHO & tHl
V,
OU11'UT
ENABLE
""IOV
IOV
VOUTlol
VOUTIOI
VoUTm
VOUlty,
IOV
"'IV
(el
'"
lhl
NOTE. THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS V =3OV, t,. '" 15 nl,
t. "50 .... 1"5GO kllz, DUTY CYCLE = 50%, loUT '" 5011: V." I.3VilU'C
Waveform 52
3OV-+Ir::-:"..-----,"""
ADDRESS
INPUT
..
VOUll'l
OUTPUT
~
,~,
V,
V,
VOUT(O(----
(al
NOTE THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS V ~ 30V,
I, ~ 15 11$, If = SO nl, f = 500 kHz, DUTY CYCLE ~ 50%, ZoUT =
v, = I]V @ 2iv e
son,
Waveform 53
(al
DATA
CLOCK
ENABLE
F~
ISV
(bl
Waveform 54
10·28
~
<
I»
".......o
3
til
Waveform 54 (Con't)
3OV--"---,-....,,.
INPut
(Notel)
OV
',w-l_
V,,----
y;~~
OUTPUT
Vo,------'------'
NOTE 3 REFERENCE VOLTAGES ARE
VREF~M! ~
l1V AND
VREF(~I =
0 9V
NOTE 4 THE INPUT WAVEFORM IS 1 0 MHz IN FREQUENCY WITH 10 ns RISETIME
{III% TO 90%)
Waveform 55
30V
CLOCK PULSE
INPUT
CLOCK PULSE
INPUT
OV
VOUTlll
OUTPUT Q OR
V IN (l)
INPUT
ii
A OR B
VOUTIO)
VOUT ll)
OUTPUT 0 OR
INPUT
AOR B
i'i
VOUTIO)
VINIO)
(.1
(bl
NOTE 1 THE GENERATOR HAS THE FOLLOWING CHARACTERISTICS VINIOl S 03V,
VIN [11 <:: 24V, I," to: 10 rts, t~l!CLOCKI" 500 ns,
(CLOCK) ~ 500 ns, PRR E 1 MHz,
AND ZOUT "" 50n
'pC
NOTE 2 Cl INCLUDES PROBE AND JIG CAPACITANCE
NOTE 3 EACH OUTPUT IS TESTED SEPARATelY
NOTE 4 VOLTAGE VALUES ARE WITH RESflECT TO NETWORK GROUND TERMINAL
NOTE 5 All DioDes ARE 1143064
Waveform 56
, -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 30V
CLOCK
OV
30V
DATA
OUll'UTO
OUTPUT ij
(DM54114/
OM74115)
NOTE THE INPUT PULSES ARE SUPPLIED BY A GENERATOR HAVING THE FOllOWING
CHARACTERISTICS t, S 10 nl, 1t ::; 10 ns, PRR ::; 10 MHz, DUTY CYCLE ::; 50%,
lOI,lT ,,501, VARY PRR TO MEASURE 'MAX
Waveform 57
10-29
1/1
E
...
....o
twecLEAR!
CD
3OV---"
>
ca
CLEAR
tn ••
DV----t'---J
~
CLOCK
OV
DATA
30V - - - - t - - - - - - - j - r - ' h .
INPUT
(SEE TESTTABLE\
OV
----t------J
V""-----_
OUTPUT 0
NOTE A THE CLOCK PULSE GENERATOR HAS THE fOLLOWING CHARACTERISTICS
louT'" 5011 AND PRR S; 10 MHI I,::; 70 n5 AND 1,::; 10 IH
NOTE B CL INCLUDES PROBE AND JIG CAPACITANCE
NOTE C ALL DIODES ARE 1N3064
NOTE 0 A CLEAR PULSE 15 APPLIED PRIOR TO EACH 1'"51
NOTE E VAEF
~
1 5V
NOTE E PROPAGATION DELAY TIMES (tPLtI AND Tl'ttd ARE MEASURED AT t"q
PROPER SHIfTING OF DATA IS VERIFIED AT tn+4 WITH A FUNCTIONAL TEST
NOTE G In = BIT TIME BEFORE CLOCK TRANSITION t no ! = BIT TIME AFTER ONE
CLOCKING TRANSITION tn •• = BIT TIME AFTER fOUR CLOCKING TRANSITIONS
Waveform 58
10-30
Physical Dimensions
c
3
CD
=
III
o
=
III
PACKAGES
DUAL·IN·LINE PACKAGES
(N)
All devices ordered with the "N" suffix are supplied in either the 14·pm, 16-pin, or 24-pin molded
dual-in-line package_ Molding material IS EPOXY B, a highly reliable compound suitable for military
as well as commercial temperature range applications. Lead material is Alloy 42 with a hot solder
dipped surface to allow for ease of solderability.
(J)
All devices ordered with the "J" suffix are supplied in either the 14-pin, 16-pin, or 24-pin ceramic
dual-in-line package. The body of the package is made of ceramic and hermetlcity is accomplished
through a high temperature sealing of the package. Lead material is tin-plated kovar.
(0)
All devices ordered with the "0" suffix are supplied in either 14-pm or 16-pin glass/metal dual-in-line
package. The top and bottom of the package are gold-plated kovar as are the leads. The side walls are
glass, through which the leads extend forming a hermetic seal.
METAL CAN PACKAGES
(H)
All devices ordered with the "H" suffix are supplied in either 8-pin or 10-pin TO-5 style metal can
package. The cap is chrome-plated kovar and the leads are gold-plated kovar.
(G)
All devices ordered with the "G" suffix are supplied in a 12-pm TO-8 style metal can package. The cap
is chrome-plated kovar and the leads are gold plated kovar.
FLAT PACKAGES
(W)
All devices ordered with the "W" suffix are supplied in either the 14-pin, 16-pin, or 24-pin ceramic flat
package. The body of the package is made of ceramic and hermetlclty is accomplished through a high
temperature sealing of the package. Lead matenal IS tin-plated kovar.
(F)
All devices ordered with the "F" suffix are supplied in either the 14-pin, 16-pin, or 24-pin glass/metal
flat package. The top and bottom of the package are gold-plated kovar as are the leads. The side walls
are glass, through which the leads extend forming a hermetic seal.
Four combinations of bottom insulator and formed leads are supplied. Suffix coding is as follows:
Suffix
-00 (Ex: OM54LOOF-00)
-01
-06
-07
Bottom Insulator
Formed Leads
No
Yes
Yes
No
No
Yes
No
Yes
If no suffix IS added, parts will be supplied as if the -00 suffix had been ordered.
Note: All dimensions are in inches.
I/)
c
o
c
I/)
C1l
E
0092
DlANOM
o
'
"
ft
J
PIN NO 1 INDENT
(g
Co)
04'
~~
I/)
TVP
>
.c
0..
110115
f-
J1til
I
I
0325 +0025
0045
-0015-j
±0015
MAX
TVP
--
I'
I
0030
0130
iODUS
0065t~
---rT
---I~?~'
0125 MIN
f--
1
0018 MIN
':1:0003
0325+0025
I
~ b'~
---I
0075
-O,OHi-l
±0015
0130
±00U5
L
=r:J,
0018
tODOl
'~,~
MIN
0100
rvp
0100
TYP
Package 1
8 Lead Molded Mini DIP (N)
Package 2
10 Lead Molded DIP (N)
ft~'770:J
MAX
0090
NOM
0092 DIA NOM
PIN NO 1 INDENT
r- °Oi
03
~t'
~.",
~
Ir "1t=1'
03
±0005
I~""
-+-0015
I 325 +0025 I
~ -0015-1
'J
0065
-
I 1_
0.075
±0015~
L
0100
TYP
---IL =r:J;,
O~1~5
0018
MIN
:1:0003
r~~~:1 ~y;
I
0325 +0025
I
-OOIS-j
~OT~~O
0015
0130
~
11Iml
I
f--
--l"TYPt--
0015
~ ~ ~ ~~ 0018 ~,~
OHIO
TYP
11
---t. '
~11~5
0018
--I1--±0003
'Jr-~
Jtll
~OlJO
±0005
00&5
0075
±OOIS
0018
--1I-!0003
0100
TYP
Package 5
16 Lead Molded DIP (N)
II
.,.
±0003
Package 4
t -=---j":"
fD015
-
14 Lead Molded DIP (N-01)
(Staggered Leads)
~OO09'r-J
I-
±0005
~
0065
±0015
Package 3
14 Lead Molded DIP (N)
Ir "kFT
I ---~0015
~~
'J
~,
~0130
Package 6
16 Lead Molded DIP (N-01)
(Staggered Leads)
~
=:[1"
(1100 MIN
MIN
"'U
':Z
t I
r
I
f---
\0008
0012
0625 +0.025
I
-0015---1
Package 10
24 Lead Cavity DIP (D)
0025
0025
RAD
RAD
j--""--j
,
~
'oo. IT
J
0200
1c::032D::J~
~
11.012
I~ 0316
. ----lI
±O 026
0.100
MAX
BOTH ENOS
~ ~~ 0018
I 0385 I
I-- iO 025----l
I "00 I
f-- ±OD1D~
Package 11
14 Lead Cavity DIP (J)
t0002
Package 12
16 Lead Cavity DIP (J)
0025
RAD
PIN NO 1
IOENT
J
0054
TV'
U 165
~~~MAxm:
re:rEl
~ +0012
_'OD8
I OJOD I
I-- REF-l
0050
tUOID
I
I--
I I
0100
±OOlU--t
I--
Package12A
18 Lead Cavity DIP (J)
IV
II
0015
0020-11--
D~,~5
DmD07'
MIN
1290
MAX
I"
0025
RAD
"tI
;:r
I
<1/1
0600
f'
(')
CI)
C
0515
0525
J
3
CD
::::l
1/1
0
0200
MAX
~ ~
L0100---J~OOt8
"-0010
.to 002
::::l
~
0125
MIN
1/1
0010
I
Package 13
24 Lead Cavity DIP (J)
IF ~::f~
I
0050
to 005
..!lli..!lli:--.
I
:Il'
PIN NO 1
!DENT
t.
0040
0215 0
""I
'~"r
--H--::~~
Package 14
10 Lead Flat Package IF)
PIN NO 1
~50
0215
IOENT~
J
I
D020
~0040
I\--0040
0020
0015~~
O(J19
II
0015
r
MAX 0880
,,, .. U
0019---jf--
Package 16
16 Lead Flat Package (F)
Package 15
14 Lead Flat Package (F)
0050
±OnDS
PIN NO 1
IDE NT
L0020
0040
Package 17
24 Lead Flat Package (F)
Il-
0015
0019--i
Package 18
14 Lead Flat Package (W)
0015
II
OOI9-i1-Package 19
16 Lead Flat Package (W)
v
I/)
c
o
I/)
c
'~I=:;::DlA--j1
01H
0185
't" I
CD
E
o
Jt
.-l
D"5L~
-n=
r ~I~ ~ ~I~ D1~:~'A
:;~:DIA-
O~
' INSULATOR
l~
01115
,,40MAX
MAX
0016 0lA
0019
i
I
05000040
IlJ~
~ ~~'--8LEAOS
I
0335
F
::~:~"60
L
0370
0319---1
0329. 1
I
gMAX
I--- 0 310 DIA
"03"~
030S01A-----I
0335
"90
0500
~u ~~~
jJ~~D160
::~~~f----
0016 OIA 10 LEADS
0019
0200
TVP
Package 20
S Lead Metal Can Package (H)
Package 21
10 Lead Metal Can Package (H)
Package 22
10 Lead Metal Can Package (H)
(Hybrids Only)
r-ijfr0550DlAREF1
!l110
MAX
L
t-
OSllO
=T-
LJ~
0022
II
0030
--ll--lEADSO 011 OIA
Package 24
12 Lead TO-S Metal Can Package (G)
Package 23
12 Lead TO-S Metal Can Package (G)
(Hybrids Only)
INCHES TO MILLIMETERS CONVERSION TABLE
INCHES
MM
INCHES
MM
INCHES
"001
.002
.0254
.010
.254
.100
2.54
.0508
.0762
.020
.030
.508
.762
"200
.300
5.08
.1016
.1270
.1524
.1778
.2032
.040
.050
.060
.070
.080
.090
.400
.500
.600
.700
.800
.900
10.16
12.70
15.24
.2286
1.016
1.270
1.524
1.778
2.032
2.286
.003
.004
.005
.006
.007
.008
.009
Note: All package dimensions are in inches.
VI
MM
7.62
17.78
20.32
22.86
National Semiconductor Corporation
2900 Semiconductor Drive
Santa Clara, California 95051
(408) 732-5000
TWX: 910-339-9240
National Semiconductor GmbH
D 808 Fuerstenfeldbruck
Industriestrasse 10
West Germany
Telephone: (08141) 1371
Telex : 27649
National Semiconductor Electronics SDNBHD
Batu Berendam
Free Trade Zone
Malacca, Malaysia
Telephone : 5171
Telex : NSELECT 519 MALACCA (c/o Kuala Lumpur)
National Semiconductor (UK) Ltd.
Larkfield Industrial Estates
Greenock, Scotland
Telephone : (0475) 33251
Telex: 778632
National Semiconductor (Pte.) Ltd.
No. 1100 Lower Delta Rd.
Singapore 3
Telephone: 630011
Telex: 21402
REGIONAL AND DISTRICT SALES OFFICES
ALABAMA
DIXIE DISTRICT OFFICE
3322 Memorial Pkway, S.W. #67
Huntsville, Alabllma 35802
(205) 881-0622
TWX: 810-726·2207
FLORIDA
AREA SALES OFFICE
2721 South Bayshore Drive, Suite 121
Miami , Florlde 33133
(305) 446-8309
TWX : 810-848-9725
MICHIGAN
DISTRICT SALES OFFICE
23629 Liberty Street
Farmington, Michigan 46024
(313) 477-0400
ARIZONA
ROCKY MOUNTAIN REGIONAL OFFICE
3313 North 6~th Street, No. 114
Scottsdale, Arizona 85251
(602) 945-8473
CARIBBEAN REGIONAL SALES OFFICE
P.O. Box 6335
Clearwater, Florida 3351 8
(813) 441-3504
MINNESOTA
DISTRICT SALES OFFICE
9701 Penn Avenue S. , Suite 109
Minneapolis, Minnesota 55431
(612) 888-4666
TWX : 910-576-3415
CALIFORNIA
NORTH-WEST REGIONAL OFFICE
2680 Bayshore Frontage Road, Suite 112
Mountain View, California 94043
(415) 961 -4740
TWX: 910-379-6432
SOUTH-WEST REGIONAL OFFICE
Vallay Freeway Conter Building
15300 Ventura Boulevard, S.'lte 305
Sherman Oaks, Californ la 91403
(213) 783-8272
TWX : 910-495-1773
DISTRICT SALES OFFIC
17452 Irvine Bouleward, Hulte M
Tustin, California 9~680
(714) 832-8113
TWX: 910-595-1523
CONNECTICUT
AREA OFFICE
Commerce Park
Danbury, Connecticu~ 0681(1
(203) 744-2350
ILLINOIS
NORTH-CENTRAL REGIONAL OFFICE
800 E. Northwest Highway, Suite 1060
Palatine, illinois 60067
W,~: ~~~~~~~4805
INDIANA
DISTRICT SALES OFFICE
P.O. Box 40073
Indianapolis, Indiana 46240
(317) 255-5822
KANSAS
DISTRICT SALES OFFICE
13201 West 82nd Street
Lenexa , Kansas 66215
(816) 358-8102
MARYLAND
CAPITAL REGIONAL SALES OFFICE
300 Hospital Drive, No. 232
Glen Burnie, Maryland 21081
(301) 760-5220
TWX: 710-861-0519
MASSACHUSETTS
NORTH-EAST REGIONAL OFFICE
NO. 3 New England, Exec. Office Park
Burlington, Massachusetts 01803
(617) 273-1350
TWX: 710-332-()186
DISTRICT SALES OFFICE
25 Sylvan Road South
Westport, Connecticut OS880
(203) 228-6833
NEW JERSEY/NEW YORK CITY
MID-ATLANTIC REGIONAL OFFICE
301 Sylvan Avenue
Eng lewood Cliffs, New Jersey 07632
(201) 871-4410
TWX: 710-991-9734
NEW YORK (UPSTATE)
CAN-AM REGIONAL SALES OFFICE
104 Pickard Drive
Syracuse, New York 13211
(315) 455-5858
OHIO/PENNSYLVANIA!
W. VIRGINIAtKENTUCKY
EAST-CENTRAL REGIONAL OFFICE
Financial South Building
5335 Far Hills, Suite 214
Dayton, Ohio 45429
(513) 434-0097
TEXAS
SOUTH-CENTRAL REGIONAL OFFICE
5925 Forest Lane, Suite 205
Dallas, Texas 75230
(214) 233-8601
TWX : 910-880-5091
WASHINGTON
DISTRICT OFFICE
300 120th Ave"nue N.E.
Building 2, Suite 205
Bellevue, Washington 96005
(206) 454-4600
INTERNATIONAL SALES OFFICES
AUSTRALIA
NATIONAL SEMICONDUCTOR
ELECTRONICS PTY, LTD.
Cnr. Stud Road & Mountain Highway
Bayswater, Victoria 3153
Australia
Telephone: 729-0733
Telex : 32096
ENGLAND
NATIONAL SEMICONDUCTOR (UK) LTD.
The Prec inct
Broxbourne, Hertfordshire
England
Telephone: 69571
Telex: 267-204
JAPAN
NATIONAL SEMICONDUCTOR JAPAN
Nakazawa Building
1-19 Yotauya, Shlniuku-Ku
Tokyo, Japan 160
Telephone: 03-359-4571
Telex: J 28592
CANADA
NATIONAL SEMICONDUCTO
1111 Finch Avenue West
Downavlew, Ontario, Canada
(416) 635-9880
TWX : 610-492-2510
FRANCE
NATIONAL SEMICONDUCTOR
FRANCE S.A.R.L.
28, Rue de Is Redoute
92260-FontenaY-Aux-Roses
Telephone : e60-81-4O
TWX : NSF 259561'
SWEDEN
NATIONAL SEMICONDUCTOR SWEDEN
Slkvagen 17
13500 Tyrelo
Stockholm
Sweden
T~lePhone: (08) 712-04-80
HONG KONG
NATIONAL SEMICONDUCTOR
HONG KONG LTrl.
9 Lai Yip Street
Kwun Tung, Kowloon
liong K('ng
Telephone : 3-45111188
Telex : HX3866
WEST GERMANY
NATIONAL SEMICONDUCTOR GMBH
8000 Munch!)n 81
COI""ltrasae 4
Tel~phone:{~11) 915-027
I)ENMARK
NATIONAL SEMICONDUCTOR
SC/\NDINAVIA
Vor<.lJngborggade 22
2100 Copenhagen
Denmark
~:i:r:~b~e~~g~)J~~~~0-5610
CORP.
~1974 NATIONAL SEMICONDl;ICTOR CORP. PRINTED IN U.S.A.
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